Patent ID: 7154345

Claim:
A PLL circuit comprising a voltage controlled oscillator (VCO), a phase error detector (PED) for detecting a phase error between an output signal from said voltage controlled oscillator (VCO) divided by a frequency divider (DIV) and a reference signal (fin), and a loop filter (LF) inserted between an error signal output of said phase error detector (PED) and a control input of said voltage controlled oscillator (VCO), wherein said loop filter (LF) comprises two charge pumps (C P1 , C P2 ), each delivering a respective output current (I CP1 , I CP2 ) according to a level of the error signal at said error signal output, a first resistor (R 2 ) and a first transistor (N 2 ), the first resistor (R 2 ) having a first terminal connected to a first supply potential (V+) and the first transistor (N 2 ) having a current path connected between a second terminal of the first resistor (R 2 ) and a second supply potential (GND), a capacitor (C′), a first electrode of which is connected to the current output of the first charge pump (C P1 ) and a second electrode of which is connected to one of said supply potentials (V+), and a control circuit (OA, N 1 , R 1 ) having an input connected to the first electrode of said capacitor (C′) and an output connected to a control electrode of said first transistor (N 2 ), for controlling the equivalent resistance of the first transistor (N 2 ) so that said equivalent resistance divided by the resistance value of the first resistor (R 2 ) equals the potential difference between said second supply potential (GND) and said first electrode of said capacitor (C′) divided by the potential difference (VC′) between said first supply potential (V+) and said first electrode of said capacitor (C′), an intermediate point between said first resistor (R 2 ) and said first transistor (N 2 ) being connected to a current output of said second charge pump (C P2 ) and connected to the control voltage input of the voltage controlled oscillator and the output current of the first charge pump (C P1 ) for a given level of the error signal being less than the output current of the second charge pump (C P2 ).