Patent ID: 7548475

Claim:
An apparatus for processing a signal in a memory device, the apparatus comprising: an input buffering section configured to amplify an input control signal to a digital level, and output a first output signal in accordance with the amplification; a noise sense removing circuit configured to sense a notch phenomenon or a glitch phenomenon occurring to the first output signal, remove the notch phenomenon or the glitch phenomenon, and output a second output signal in accordance with the removal, wherein the noise sense removing circuit comprises: a falling edge signal delaying circuit configured to delay a falling edge of the first output signal for a preset time, thereby outputting a first delay output signal; a falling edge sensing circuit configured to generate a pulse signal by sensing the falling edge of the first output signal; a flip-flop configured to output the first delay output signal in accordance with the clock signal, and operate using an output signal of the falling edge sensing circuit as a reset signal; and a first logic operation circuit configured to perform a logic operation on an output signal of the flip-flop and the first output signal delayed for the preset time, thereby generating the second output signal; and a clock generator configured to generate a clock signal using the second output signal.