Patent ID: 8138044

Claim:
A method comprising: forming a hard mask pattern by depositing an oxide film over a semiconductor substrate and performing patterning and a first etching process on the oxide film; forming a tunnel oxide film over the semiconductor substrate including the hard mask; forming a first spacer serving as a floating gate at sidewalls of the hard mask by depositing a first polysilicon layer over the semiconductor substrate, the hard mask pattern and the tunnel oxide film and then performing a second etching process; performing a third etching process removing the hard mask pattern and a portion of the tunnel oxide film; forming a source/drain region self-aligned with the first spacer by conducting a first ion-implantation process on the semiconductor substrate; forming a second spacer at sidewalls of the first spacer by forming an insulating layer over the entire surface of the semiconductor substrate and then performing a fourth etching process on the insulating layer; forming a dielectric film over the entire surface of the semiconductor substrate including the first spacer and the second spacer; and then forming a control gate over the first spacer and the second spacer by depositing a second polysilicon layer over the dielectric film and then patterning and a fifth etching process the second polysilicon layer.