Patent ID: 8176250

Claim:
A computer system comprising: a processor; a memory; and a memory controller coupled to the processor with a first connection and the memory with a second connection that is separate from the first connection; wherein the memory controller comprises a first cache separate from the memory and a cache control, wherein the cache control is configured to cause a portion of the memory to be copied from the memory into the first cache in the memory controller across the second connection, wherein the memory controller is configured to perform testing on the portion by providing a plurality of test transactions to the portion across the second connection subsequent to the portion being copied into the first cache, and wherein the cache control is configured to cause first information to be provided from the first cache in the memory controller to the processor across the first connection without accessing the memory during the testing of the portion in response to receiving a read transaction from the processor that includes an address corresponding to the portion of memory during the testing of the portion.