Patent ID: 8407406

Claim:
A nonvolatile semiconductor memory device, comprising: a first memory cell array and a second memory cell array acting in parallel to each other, the first memory cell array including a plurality of first blocks and the second memory cell array including a plurality of second blocks, and each of the blocks being an erase unit; a plurality of flag registers configured to correspond to each of the first blocks and each of the second blocks, flag data are capable of being written to the flag registers by selecting a block address; a control circuit reading out the flag data in the flag register corresponding to one of the first blocks and the flag data in the flag register corresponding to one of the second blocks in parallel fashion; a first counter register storing a first counting value of the flag data in the flag registers corresponding to the first blocks of the first memory cell array; and a second counter register storing a second counting value of the flag data in the flag registers corresponding to the second blocks of the second memory cell array.