Patent ID: 8230297

Claim:
An error correction device comprising: a demodulation circuit which demodulates modulated data to generate a cluster, wherein the cluster includes a parity-appended block that has been subjected to interleaving, the parity-appended block includes a data block, which has a plurality of data elements arranged in rows and columns to form a predetermined number of data frames, and a parity, which is appended to the data block in a column direction, and the data block includes scramble data that is generated by scrambling each data frame; an internal memory unit which stores at least one of a plurality of divisional clusters divided from the cluster; a syndrome calculation result generation circuit which reads the parity-appended block while de-interleaving each of the plurality of divisional clusters using the internal memory unit and generating a syndrome calculation result for each column of the parity-appended block; a descramble circuit which reads the data block as a plurality of read blocks while de-interleaving each of the plurality of divisional clusters using the internal memory unit and descrambles the scramble data of each read block to generate descramble data; and an error correction circuit which performs error correction on the descramble data based on the syndrome calculation result; wherein the descramble circuit includes: a first exclusive OR circuit which applies a predetermined scramble value to a data element of the descramble data read from the internal memory unit to calculate the data element of the scramble data; a first shift calculator which generates a first calculated value by shifting the scramble value by one byte in accordance with a first generation polynomial; a second shift calculator which generates a second calculated value by shifting the scramble value by a number of bytes corresponding to {(total number of bytes of the data block in the column direction)+1−(total number of bytes of each read block in the column direction)} in accordance with the first generation polynomial; and a first selector which provides the first exclusive OR circuit, the first shift calculator, and the second shift calculator with the first calculated value or the second calculated value as the scramble value in accordance with the data element of the scramble data that is input to the first exclusive OR circuit.