Patent ID: 7570646

Claim:
In a system in which an ATM slave processing unit is coupled to an ATM master processing unit by a communication bus, the interaction between the ATM master processing unit and the ATM slave processing unit having a UTOPIA format, an ATM slave interface unit providing an interface between the communication bus and a direct memory access unit coupled to the ATM slave processing unit, the interface unit comprising: an input unit, the input unit receiving data cells and exchanging control signals with the ATM master processing unit; an input buffer unit receiving data signals and exchanging control signals with the input unit, the input buffer unit including: a buffer storage unit coupled to the input unit, the buffer storage unit being a first-in/first-out memory unit configured to store two data cells received from the input unit to permit the data cells to be transferred on consecutive clock cycles to a destination location when the destination location is available, the buffer storage unit transferring data cells to the direct memory access unit in response to a first READY signal; and a calculation unit; a register, each data cell including a cell portion having the destination location encoded therein, the calculation unit responsive to the contents of the register and to the cell portion for generating the destination location for the data cell in the ATM slave processing unit; an output buffer unit, the output buffer unit being a first-in first-out storage unit for storing data cells, the output buffer unit receiving data cells from the direct memory access unit in response to a second READY signal and exchanging control signals with the direct memory access unit; and an output unit, the output unit receiving data cells from the output buffer unit and applying data cells to the communication bus, the output unit exchanging control signals with the ATM master processing unit.