Patent ID: 7109739

Claim:
A wafer-level testing arrangement for use with an integrated opto-electronic silicon-on-insulator (SOI)-based structure formed on a silicon wafer, the arrangement comprising an opto-electronic testing element for removably contacting a top major surface of the silicon water, the opto-electronic testing element including at least one optical input fiber for directing at least one optical test signal toward the SOI-based structure; and a plurality of electrical test pins, disposed in a pattern matching a plurality of bond pads on the surface of the opto-electronic SOI-based structure being tested, the plurality of electrical test pins for energizing the opto-electronic SOI-based structure being tested and providing electrical test signals to and electrical response signals from the opto-electronic SOI-based structure being tested; and optical coupling features disposed between the opto-electronic testing element and the surface of a specific opto-electronic SOI-based structure being tested for coupling optical test signals into the specific opto-electronic SOI-based structure being tested, wherein the at least one optical input fiber is disposed through the opto-electronic testing element at a predetermined angle so as to provide for a desired degree of optical coupling into the optical coupling features.