Patent ID: 7924967

Claim:
A shift register, comprising a plurality of stages, {S n }, n=1, 2, . . . , N, N being a positive integer, wherein each stage S n comprises: (a) a pull-up circuit having an input for receiving a first clock signal, CK 1 , an output for responsively outputting an output signal, O n , and an input node Q n ; (b) a pull-up control circuit electrically coupled to the input node Q n of the pull-up circuit and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Q n of the pull-up circuit to turn on the pull-up circuit; (c) a pull-down circuit electrically coupled to the input node Q n of the pull-up circuit and configured to provide a first voltage to one of the input node Q n and the output of the pull-up circuit; and (d) a pull-down control circuit configured to receive one of a third clock signal, CK 2 , and a fourth clock signal, XCK 2 , and responsively generate the first voltage to turn on the pull-down circuit of the stage S n and the pull-down circuit of the stage S n+1 ; and (e) a key pull-down circuit electrically coupled to the pull-down circuit and configured to receive a second input signal.