Patent ID: 8461642

Claim:
A semiconductor device having a nonvolatile memory cell equipped with a first field effect transistor in a first region of a memory region, a second field effect transistor adjacent to the first field effect transistor in a second region of the memory region over a main surface of a semiconductor substrate, and a third field effect transistor in a peripheral circuit region over the main surface of the semiconductor substrate, the semiconductor device comprising: a first insulating film formed in the first region; a first gate electrode of the first field effect transistor formed in the first region over the first insulating film; a second insulating film formed in the second region and having a charge storage layer having a charge storage function; a second gate electrode of the second field effect transistor formed in the second region over the second insulating film; a third insulating film formed in the peripheral circuit region; a third gate electrode of the third field effect transistor formed in the peripheral circuit region over the third insulating film; and a semiconductor region of the third field effect transistor formed in the semiconductor substrate in the peripheral circuit region, wherein a height of the first gate electrode from the main surface of the semiconductor substrate is less than a height of the second gate electrode from the main surface of the semiconductor substrate, wherein a height of the third gate electrode of the third field effect transistor from the main surface of the semiconductor substrate is equal to or less than the height of the first gate electrode from the main surface of the semiconductor substrate, wherein a first sidewall is formed over a side surface of the second gate electrode at a side of the second gate electrode that is opposite the first gate electrode, wherein a second sidewall is formed over a side surface of the third gate electrode, the semiconductor region being adjacent to the second sidewall, wherein a width of the first sidewall is greater than a width of the second sidewall, wherein a shared contact hole reaching the third gate electrode and the semiconductor region is formed over the second sidewall, and wherein the third gate electrode and the semiconductor region are electrically coupled together via a conductor film filling the shared contact hole.