Patent ID: 7442969

Claim:
An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first and second contact points are separated from each other by an insulating material, and wherein said passivation layer comprises a nitride layer; a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers, and wherein a third opening in said polymer layer is over said first contact point, and a fourth opening in said polymer layer is over said second contact point; and a second metallization structure on said polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure comprises electroplated copper in said third opening and over said polymer layer.