Patent ID: 8429353

Claim:
A processor system, comprising: a first local memory; a first processor node, wherein the first processor node is coupled to the first local memory, and wherein the first local memory is local to the first processor node, wherein the first processor node comprises: a first processor; and a first local arbiter, wherein the first local arbiter is configured to: in response to a memory conflict between a request for access to the first local memory and a request for access to the first local memory by one of other processor nodes, perform a coherency check on the first local memory, wherein the coherency check on the first local memory resolves the memory conflict for the first local memory in accordance with a coherency protocol; and a switch coupled to the first local arbiter for enabling or disabling the first local arbiter, wherein the switch is configured to turn the first local arbiter off for a central arbiter configuration in which a central arbiter maintains memory coherence of the first local memory and local memory of the other processor nodes, or on for a local arbiter configuration in which the first local arbiter maintains memory coherence of the first local memory and other local arbiters maintain memory coherence of the other processor nodes respectively.