Patent ID: 8483216

Claim:
A system for transmitting packets, comprising: an upstream packet counter (UPC), an upstream packet window counter (UPWC), and a plurality of upstream switch packet counters (USPCs) configured to change in response to forwarding a first set of upstream packets, a second set of upstream packets, and a third set of upstream packets to a downstream switch; a local packet queue (LPQ) storing a local packet for transmission to the downstream switch after forwarding the first set of upstream packets to the downstream switch and before forwarding the second set of upstream packets to the downstream switch; a local packet counter (LPC) configured to decrement in response to forwarding the local packet; a UPWC register for restoring the UPWC before the third set of upstream packets is forwarded to the downstream switch; and a scheduling engine operatively connected to the UPC, the plurality of USPCs, the UPWC, the UPWC register, and the LPQ, and configured to obtain a sum of the USPCs and set the UPWC register to the sum after performing a plurality of bitwise right shift operations on the sum, wherein at least one of the plurality of USPCs equals a predetermined value after the first set of upstream packets is forwarded to the downstream switch, wherein the scheduling engine, the UPC, the plurality of USPCs, the UPWC, the UPWC register, and the LPQ are located on a local switch operatively connected to the downstream switch, and wherein the first set of upstream packets, the second set of upstream packets, and the third set of upstream packets are generated by at least one upstream source operatively connected to the local switch.