Patent ID: 7669042

Claim:
An instruction execution pipeline for use in a software-defined radio data processor comprising: an instruction fetch stage; a decode stage; an execution stage; a write-back stage; said instruction execution pipeline repetitively executes a first loop of instructions by fetching and decoding a first instruction associated with said first loop during a first iteration of said first loop, storing first decode instruction information associated with said first instruction during said first iteration of said first loop, using said stored first decoded instruction information during at least a second iteration of said first loop, and replacing said fetching and said decoding of said first instruction during at least said second iteration of said first loop with idle operations, and repetitively executes a second loop of instructions by fetching and decoding a second instruction associated with said second instruction during said first loop, using said stored second decoded instruction information during at least a first iteration of said second loop, and replacing said fetching and said decoding of said second instruction during at least said first iteration of said second loop with idle operations; wherein said instruction fetch stage is idle during said at least said first iteration of said second loop and said decode stage is idle during said at least a said first iteration of said second loop; and a pipeline controller comprising: a first decoded instruction register storing said first decoded instruction information during said first iteration of said first loop; a second decoded instruction register storing said second decoded instruction information during said first loop; a first loop register storing first loop control information associated with said first loop of instructions during said first iteration of said first loop; and a second loop register storing second loop control information associated with said second loop of instructions during said first loop; wherein said first loop register and said second loop register comprises at least a Start Address field, an Address Length field and a Count field.