Patent ID: 7507623

Claim:
A fabricating method of a semiconductor device, comprising: forming a first metal layer on a substrate and patterning the first metal layer to form a bottom metal line and a bottom electrode of a capacitor; forming an interlayer insulating layer on the resulting structure; forming a via hole in the interlayer insulating layer; forming a contact by depositing a metal for connecting to the bottom metal line; after forming the contact, exposing the interlayer insulating layer through planarization using a chemical mechanical polishing (CMP) process; forming a titanium nitride (TiN) layer on the resulting structure after the CMP process; etching the titanium nitride layer and the interlayer insulating layer to form a trench exposing the bottom electrode; forming a dielectric layer on the resulting structure, and exposing the interlayer insulating layer through a chemical mechanical polishing (CMP) process; and forming a second metal layer on the resulting structure to form a top metal line and a top electrode of the capacitor.