Patent ID: 7773712

Claim:
A clock switching circuit, in which one clock signal is selected from 2 N -phase input clock signals with the same frequency but with each shifted in phase (where N is an integer equal to or greater than 3), based on an N-bit selection signal, and is output as an output clock signal, the clock switching circuit comprising: a selector group having 2 N −1 selectors each of which selects and outputs one clock signal from two input clock signals; and an operation control circuit which generates 2 N −1 operation control signals to execute control to set said 2 N −1 selectors into an active state or into a sleep state, wherein said selector group comprises: a first layer, having first to 2 N-1 th selectors, each of which input two input clocks among said input clocks and selects and outputs one of said two input clocks, a second layer, having 2 N-1 +1th to 2 N-1 th+2 N-2 th selectors, each of which input the output clocks of the two selectors of said first layer as input and selects and outputs one of said two clocks, and 3rd to Nth layers (where in this case N is equal to or greater than 4), in which said Nth layer has the 2 N −1th selector, which input as input clocks the output clocks of the two selectors in the N−1th layer and selects and outputs one of said two clocks, and wherein a first selection signal is supplied to said first layer selectors using positive logic or negative logic, a second selection signal is supplied to said second layer selectors using positive logic or negative logic, third to N−1th selection signals are similarly supplied to the third to N−1th layer selectors using positive logic or negative logic, and an Nth selection signal is supplied to the selector of said Nth layer, and said operation control circuit, according to the state of said N-bit selection signal, generates said operation control signals to set a portion of said 2 N −1 selectors to an active state, and to set the remaining selectors to a sleep state.