Patent ID: 8054276

Claim:
A display apparatus comprising: a liquid crystal panel; a source driver which is coupled to source lines of the liquid crystal panel to drive the source lines; a gate driver which is coupled to gate lines of the liquid crystal panel to drive the gate lines; and a timing controller which is coupled to the source driver and the gate driver to output a predetermined timing signal and predetermined display data to the source driver and the gate driver, wherein the source driver includes: a line buffer which includes a plurality of latch circuits and receives sequential input of the display data to latch the input display data into the latch circuits; and a horizontal shift register which is coupled to the line buffer to sequentially output a latch signal to the latch circuits, wherein the horizontal shift register includes: a plurality of output lines from which the latch signal is output; a plurality of flip-flops which are coupled to respective output lines to output the latch signal to the output lines and a plurality of change-over switches, each of which is coupled to any two of the flip-flops to connect a data input terminal of a subsequent stage flip-flop among the two flip-flops to either one of a data output terminal or a data input terminal of a preceding stage flip-flop, wherein a plurality of couples of the change-over switches are provided among the plurality of the flip-flops of the horizontal shift register at a predetermined interval from each other, wherein the gate driver includes a vertical shift register to output a timing signal for sequentially driving the gate lines, wherein the vertical shift register include: a plurality of output lines to output the timing signal; a plurality of flip-flops which are coupled to respective output lines to output the timing signal to the output lines; and a plurality of change-over switches, each of which is coupled to any two of the flip-flops to connect a data input terminal of a subsequent stage flip-flop among the two flip-flops to either one of a data output terminal or a data input terminal of a preceding stage flip-flop, wherein a plurality of couples of the change-over switches are provided among the plurality of the flip-flops of the vertical shift register at a predetermined interval from each other.