Patent ID: 7765686

Claim:
A method of manufacturing a multilayer wiring structure, comprising: a step of forming plural pairs of alignment marks on each end of a substrate on which a first metal wiring element is formed; a step of forming a via post on the first metal wiring element while subsequently reading the pairs of alignment marks formed on each end of the substrate, feeding back positions of the alignment marks, and correcting a position of the substrate by using the positions of the alignment marks; a step of printing an interlayer insulation film on the first metal wiring element, with use of a screen mask having a non-ejection area slightly larger than a head of the via post, such that the interlayer insulation film has an upper surface at a level lower than the head of the via post, while aligning the non-ejection area with the head of the via post; a step of curing the interlayer insulation film; and a step of forming a second metal wiring element in contact with the via post on the interlayer insulation film such that the first metal wiring element and the second metal wiring element are connected through the via post.