Patent ID: 6943113

Claim:
A chemical mechanical polishing process for minimizing dishing of metal lines formed in trenches in an insulation layer of each of a plurality of semiconductor wafers during fabrication thereof, comprising for each wafer: a first, bulk polishing, step of chemically mechanically polishing a metal layer disposed on the insulation layer of the corresponding wafer and having a lower portion located in the trenches of the insulation layer for forming individual metal lines and an upper portion overlying the lower portion; the first step polishing being effected with a first polishing pad sufficiently to remove the bulk of the upper portion of the metal layer while generating concomitant chemical mechanical polishing residue, and to leave a minimized remainder of the metal layer upper portion substantially without dishing of the metal layer lower portion in the trenches; and a second, overpolishing, step of continuing the polishing with a second polishing pad sufficiently to remove the remainder of the metal layer upper portion with attendant minimized dishing of the metal layer lower portion to an extent for providing the metal lines as individual metal lines correspondingly disposed in the trenches; each of the wafers being subjected to the first step polishing with the first polishing pad and thereafter to the second step polishing with the second polishing pad; and wherein each of a further plurality of said wafers is subjected to said first and second steps, using said second polishing pad for said first polishing step and a third polishing pad for said second step.