Patent ID: 8773169

Claim:
A high frequency input signal comparator for reducing group delay, minimizing statistical offset in the latch core, and minimizing frequency dependent offset, comprising: a pair of isolation switches; a latch core including a pair of latch switches; comparator outputs connected to outputs of the latch core for providing a digital representative of an input signal; wherein: the latch core samples the input signal, and includes a first inverter and a second inverter coupled directly to the pair of isolation switches, wherein an input of the first inverter is connected to a first terminal of a first capacitor and an output of the second inverter is connected to a second terminal of the first capacitor, and an input of the second inverter is connected to a second output of the comparator, and to a first terminal of a second capacitor, wherein a second terminal of the second capacitor is connected to the input of the first inverter; the pair of latch switches connects an inverter input to an inverter output of each respective inverter in the latch core; and a control signal controls the pair of isolation switches and the pair of latch switches such that in a first phase, the pair of isolation switches and the pair of latch switches are closed, and in a second phase immediately subsequent to the first phase, the pair of isolation switches and the pair of latch switches are open.