Patent ID: 7096177

Claim:
A multiprocessor array which includes: a) a first processor shadow register unit ( 1 ) which operates within a first clock domain and includes i) a first processor ( 2 ), and ii) a first shadow register unit ( 3 ) which is connected to the first processor ( 2 ) so as to transmit data bidirectionally, b) at least one second processor shadow register unit ( 9 ) which i) operates within a corresponding second clock domain, ii) includes a second processor ( 10 ), and iii) a second shadow register unit ( 11 ) which is connected to the second processor ( 10 ) so as to transmit data bidirectionally, and c) a peripheral unit ( 17 ) which operates within a peripheral clock domain and includes i) a multiplexer unit ( 18 ) which is connected to the first shadow register unit ( 3 ) and the at least one second shadow register unit ( 11 ) so as to transmit data bidirectionally, ii) a register unit ( 20 ) having the construction and identical function of the first shadow register unit ( 3 ) and the at least one second shadow register unit ( 11 ), and iii) a priority unit ( 19 ) directly connected to a multiplexer unit ( 18 ) via only a single action connection for applying control signals thereto and for allocating the multiplexer unit ( 18 ) for data transmission to the first shadow register unit ( 3 ) or to the at least one second shadow register unit ( 11 ) based on at least one criterion, the priority unit ( 19 ) being connected to the first shadow register unit ( 3 ) and to the at least one second shadow register unit ( 11 ), via a corresponding asynchronous request line, said request line informing the priority unit of changes in a corresponding shadow register.