Patent ID: 8730626

Claim:
A chip comprising: a first circuit having a first node, a first operational voltage node, and a first reference voltage node; a second circuit having a second node, a second operational voltage node, and a second reference voltage node; a first interconnect configured to electrically connect the first node and the second node to form a 2.5D or a 3D integrated circuit; at least one protection circuit located at one or a combination of the following locations a first location between the first operational voltage node and the first node; a second location between the first node and the first reference voltage node; a third location between the second operational voltage node and the second node; a fourth location between the second node and the second reference voltage node; a fifth location between the first operational voltage node and a second interconnect that is coupled to the second operational voltage node; a sixth location between the second operational voltage node and a third interconnect that is coupled to the first operational node; a seventh location between the first reference voltage node and a fourth interconnect that is coupled to the second reference voltage node; an eight location between the second reference voltage node and a fifth interconnect that is coupled to the first reference voltage node; a ninth location between the first operational voltage node and a sixth interconnect that is coupled to the second reference voltage node; a tenth location between the second reference voltage node and a seventh interconnect that is coupled to the first operational voltage node; an eleventh location between the first reference voltage node and an eighth interconnect that is coupled to the second operational voltage node; and a twelfth location between the second operational voltage node and a ninth interconnect that is coupled to the first reference voltage node.