Patent ID: 6844753

Claim:
An output circuit of a semiconductor integrated circuit device comprising: a first CMOS inverter circuit including a PMOS transistor (P 2 ) and an NMOS transistor (N 2 ) connected in series via a first variable resistance unit having a control electrode between a first power-supply potential and a second power-supply potential; a second CMOS inverter circuit including a PMOS transistor (P 3 ) and an NMOS transistor (N 3 ) connected in series via a second variable resistance unit having a control electrode between the first power-supply potential and the second power-supply potential; a first CMOS circuit including a PMOS transistor (P 4 ) and an NMOS transistor (N 4 ) connected in series via a node n 1 between the first power-supply potential and the second power supply potential, the node n 1 being connected to the control electrodes of the first and second variable resistance units, the PMOS transistor (P 4 ) having a gate connected to a drain (node n 2 ) of the PMOS transistor (P 2 ), the NMOS transistor (N 4 ) having a gate connected to a drain (node n 3 ) of the NMOS transistor (N 3 ); a second CMOS circuit including a PMOS transistor (P 5 ) and an NMOS transistor (N 5 ) connected in series via a node n 4 between the first power-supply potential and the second power-supply potential, the PMOS transistor (P 5 ) having a gate connected to the node n 2 , the NMOS transistor (N 5 ) having a gate connected to the node n 3 ; a third CMOS circuit including a PMOS transistor (P 1 ) and an NMOS transistor (N 1 ) connected in series via the node n 4 between the first power-supply potential and the second power-supply potential; a first resistance unit connected between a gate of the PMOS transistor (P 1 ) and the node n 2 ; a second resistance unit connected between a gate of the NMOS transistor (N 1 ) and the node n 3 ; a PMOS transistor (P 7 ) having a source connected to the first power-supply potential, a gate connected to the node n 2 , and a drain connected to the gate of the PMOS transistor (P 1 ); and an NMOS transistor (N 7 ) having a source connected to the second power-supply potential, a gate connected to the node n 3 , and a drain connected to the gate of the NMOS transistor (N 1 ).