Patent ID: 7353368

Claim:
A multi-mode processor comprising: a first instruction set engine to process instructions from a first instruction set architecture (ISA), the first ISA designed for a first processor having a first word size that defines the maximum number of bits that the first processor can handle as a single unit; a second instruction set engine to process instructions from a second ISA, the second ISA designed for a second processor having a second word size that defines the maximum number of bits that the second processor can handle as a single unit, a bit length of the second word size being greater than a bit length of the first word size; a mode identifier; a plurality of floating-point registers shared by the first instruction set engine and the second instruction set engine; and a floating-point unit coupled to the floating-point registers, the floating-point unit including: pre-processing hardware to bypass an arithmetic unit if a token exists in an input and the mode identifier indicates a second ISA mode; the arithmetic unit to process the input to produce an arithmetic result unless the input bypasses the arithmetic unit; and post-processing hardware to perform a token specific operation if another token exists in the input and bypasses the arithmetic unit to produce an output.