Patent ID: 8510498

Claim:
A memory system comprising: a plurality of memory chips laid out with a plurality of erasure blocks, the erasure blocks respectively being formed by laying out with a plurality of pages and being an erasure unit, the pages respectively being formed by laying out with a plurality of memory cells and being a writing unit or a reading unit to be written and read; and a plurality of IO line groups connected to the plurality of memory chips, and transferring an address signal determining the erasure block, and transferring data to be written into the memory cells and data to be read from the memory cells; wherein the memory chips, which are connected to the same IO line group out of the plurality of IO line groups, form a memory group, and the memory group in each of the plurality of IO line groups is divided into a plurality of sub-memory groups, number of bad blocks of the memory chip having a smallest number of bad blocks in a first sub-memory group in the plurality of memory groups is larger than number of bad blocks of the memory chip having a largest number of the bad blocks in a second sub-memory group adjacent to the first sub-memory group in the plurality of memory groups, the bad blocks being the erasure blocks in which erasing, writing or reading of data cannot be performed correctly.