Patent ID: 7869498

Claim:
A decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI), with each slice of the DFE system, comprising: a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data through applying adaptive weights to previous data; a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch; a second set of decision feedback DACs to generate a second DFE data through applying the adaptive weights and a negative threshold value to the previous data; a second data latch to generate a negative error data of the each slice through applying the second DFE data to the input data of the each slice in the second data latch to remove a second delay caused by performing the applying the second DFE data to the input data outside of the second data latch; a third set of decision feedback DACs to generate a third DFE data through applying the adaptive weights and a positive threshold value to the previous data; a third data latch to generate a positive error data of the each slice through applying the third DFE data from the input data of the each slice in the third data latch to remove a third delay caused by performing the applying the third DFE data to the input data outside of the third data latch; a clock and a data recovery circuit to generate an optimum location to sample the input data based on the output data, the negative error data, and the positive error data; an adaptor circuit to adjust the adaptive weights based on the output data, the negative error data, and the positive error data, wherein the adaptive weights are amounts of ISI injects of the previous data to the input data; and a phase interpolator to adjust a timing of a clock based on a voltage controlled oscillator (VCO), wherein the timing obtained through the clock and the data recovery circuit controls sampling of the input data, wherein an average power consumption of the DFE system is lowered by 2 to 3 mili-watts per each of the first data latch, the second data latch, and the third data latch when compared to a DFE system with additional circuits to perform the applying the first DFE data, the second DFE data, and the third DFE data to the input data.