Patent ID: 7187027

Claim:
A semiconductor device comprising: a semiconductor substrate; an element separating insulating film formed in the semiconductor substrate, the element separating insulating film separating an element region; MOS transistors, formed in the element region, each of the MOS transistors having a gate insulating film, a gate electrode connected to a word line and source/drain regions; a first insulating film covering the element separating insulating film and the MOS transistors; first contact holes formed in the first insulating film, and reaching one of the source/drain regions of the MOS transistors; second contact holes formed in the first insulating film, and reaching the other of the source/drain region of the MOS transistors; first conductive plugs filling up the first contact holes; second conductive plugs filling up the second contact holes; a second insulating film covering the first insulating film and the first and second conductive plugs; bit line contacts formed in the second insulating film, and reaching the first conductive plug; bit lines formed on the second insulating film and the bit line contacts, a lower part of each of the bit lines being composed of a conductive film and an upper part being composed of a third insulating film; a fourth insulating film formed on the second insulating film and between the bit lines; third contact holes formed through the fourth insulating film and the second insulating film; a fifth insulating film formed in the third contact holes and on at least a side wall of the conductive film of the bit lines and a side wall of the second insulating film; a third conductive plugs filling up the third contact holes; and capacitors, each having a storage node electrode, a capacitor insulating film formed on the storage node electrode, and a plate electrode formed on the capacitor insulating film, wherein the storage node electrode is electrically connected to each of the second conductive plugs by each of the third conductive plugs.