Patent ID: 7696578

Claim:
A semiconductor structure comprising: a PMOS device comprising: a first gate structure over a substrate; a first gate spacer on a sidewall of the first gate structure; a first source/drain region substantially aligned with a side edge of the first gate spacer; a barrier layer over at least a portion of the first gate structure, the first gate spacer, and the first source/drain region, wherein the barrier layer is a composite layer comprising two sub layers formed of different materials; and a first stressed contact etch stop layer having a compressive stress over the barrier layer; and an NMOS device comprising: a second gate structure over the substrate; a second gate spacer on a sidewall of the second gate structure; a second source/drain region substantially aligned with a side edge of the second gate spacer; and a second stressed contact etch stop layer having a tensile stress over at least a portion of the second gate structure, the second gate spacer, and the second source/drain region, wherein the barrier layer is substantially not located under the second stressed contact etch stop layer.