Patent ID: 7790540

Claim:
A method of fabricating a semiconductor structure comprising: providing at least one field effect transistor (FET) on a surface of a semiconductor substrate, said at least one FET including at least a gate dielectric, an overlying gate electrode, a silicided source region located within the semiconductor substrate on one side of the FET and a silicided drain region located within the semiconductor substrate on another side of the FET; forming a compressive stress liner on a portion of said semiconductor substrate and surrounding said at least one FET including atop both the silicided source region and the silicided drain region, wherein said compressive stress liner has a dielectric constant of less than 4.0; and subjecting the compressive stress liner to UV treatment, said UV treatment converts said compressive stress liner into a tensile stress liner, said tensile stress liner is located at least atop the at least one FET and the entirety of the silicided source region and the silicided drain region, and wherein said compressive stress liner has a stress value of about 50 MPa or greater, and said tensile stress liner has a stress value of about 100 MPa to about 500 MPa.