Patent ID: 8837238

Claim:
A semiconductor device comprising: a plurality of first memory modules; and a logic circuit capable of providing to the plurality of first memory modules a resume control signal having a first level and a second level different from the first level, the first level being defined for a normal mode of the plurality of first memory modules, and the second level being defined for a resume mode of the plurality of first memory modules; wherein each of the plurality of first memory module comprises: a memory array; an I/O circuit; a decoder circuit; a switch which cuts off, in the resume mode, a source voltage supply to the I/O circuit and the decoder circuit and for providing, in the normal mode, the source voltage supply to the I/O circuit and the decoder circuit; and a delay circuit which receives the resume control signal ordering a transition from the resume mode to the normal mode and outputs a delayed resume control signal delayed from the inputted resume control signal to a next-stage memory module, wherein the each memory module comprises a control circuit including inverters of plural stages to which, in the normal mode, a first control signal for controlling a constituent element of the each memory module is inputted and which generate, by delaying the inputted first control signal, a second control signal for controlling another constituent element of the each memory module and to which, in the resume mode, the resume control signal is inputted and which generate, by delaying the inputted resume control signal, an intermediate signal, and wherein the delay circuit includes inverters of plural stages to which the intermediate signal is inputted from the plural-stage inverters included in the control circuit and which generate, by delaying the inputted intermediate signal, a resume control signal to be outputted to the next-stage memory module.