Patent ID: 8271730

Claim:
A data processing apparatus, comprising: a plurality of processing units for performing data processing operations requiring access to data in shared memory; each processing unit having a cache associated therewith for storing a subset of said data for access by that processing unit; cache coherency logic employing a cache coherency protocol to ensure data accessed by each processing unit is up-to-date; each processing unit being configured to issue a write access request when outputting a data value for storing in said shared memory, wherein when the write access request is of a type requiring both the associated cache and the shared memory to be updated, the processing unit issuing the write access request is configured to treat the write access request as a write access request that does not require a cache lookup by the processing unit; the cache coherency logic being configured, when the write access request is of a type requiring both the associated cache and the shared memory to be updated, to initiate and perform a coherency operation in respect of the caches associated with the plurality of processing units, including the cache associated with the processing unit issuing the write access request, in order to ensure that the data in those caches is kept coherent; and the cache coherency logic further being configured to issue an update request to said shared memory in respect of the data value the subject of the write access request.