Patent ID: 7213091

Claim:
A bus architecture for a plurality of dedicated SRAM blocks in an integrated circuit comprising: a plurality of pass-through interconnect conductors, each of said plurality of said pass-through interconnect conductors having a first end connected to one of a first plurality of programmable connectors that connect said plurality of SRAM blocks to a first set of circuitry and a second end connected to one of a second plurality of programmable connectors that connect said plurality of dedicate SRAM blocks to a second set of circuitry; an address bus disposed in one of said plurality of dedicated SRAM blocks forming first intersections with said plurality of pass-through interconnect conductors; a data bus disposed in one of said plurality of dedicated SRAM blocks forming second intersections with said plurality of pass-through interconnect conductors; a control signal line disposed in one of said plurality of dedicated SRAM blocks forming third interconnect intersections with said plurality of pass-through interconnect conductors; and programmable elements disposed at selected ones of said first, second and third intersections.