Patent ID: 7715484

Claim:
An orthogonal frequency division multiplexing system with PN-sequence, comprising: a modulate circuit, for modulating a transmitting terminal signal to a complex number frequency domain signal at a transmitting terminal; an Inverse Fast Fourier Transformer, for transforming the complex number frequency domain signal at the transmitting terminal to a complex number time domain signal at the transmitting terminal; a PN-sequence generating circuit, for generating a PN-sequence signal; a cyclic prefix inserter, for inserting cyclic prefixes to the complex number time domain signal at the transmitting terminal and the PN-sequence signal respectively; a first adder, for adding the complex number time domain signal having cyclic prefixes at the transmitting terminal and the PN-sequence signal having cyclic prefixes to form a transmitting signal; a time and frequency synchronization device, for receiving a receiving signal formed by the transmitting signal though a channel, and for calculating and compensating the timing offset and frequency offset of the receiving signal according to cyclic prefixes and the PN-sequence signal; a cyclic prefix remover, for removing the cyclic prefix of the receiving signal compensated by the time and frequency synchronization device; a Fast Fourier Transformer, for transforming the receiving signal without the cyclic prefix to a complex number frequency domain signal at a receiving terminal; and a demodulate circuit, for demodulating the complex number frequency domain signal at the receiving terminal to a receiving terminal signal, wherein the time and frequency synchronization device comprises a timing offset synchronization device, a frequency offset synchronization device, and a compensation device, the timing offset synchronization device is used for calculating the timing offset of the receiving signal, the frequency offset synchronization device is used for calculating the frequency offset of the receiving signal, and the compensation device is used for compensating the receiving signal according to the timing offset and the frequency offset, and wherein the timing offset synchronization device comprises: a first timing offset synchronization circuit, for generating a first timing metric formed by the cyclic prefix; a second timing offset synchronization circuit, for generating a second timing metric formed by the PN-sequence; a first multiplier, for multiplying the first timing metric by a first coefficient ρ; a second multiplier, for multiplying the second timing metric by a second coefficient α(1−ρ); a second adder, for adding the first timing metric multiplied by the first coefficient ρ and the second timing metric multiplied by the second α(1−ρ); and a first maximum value circuit, for obtaining a maximum value among the output of the second adder to be the timing offset of the receiving signal.