Patent ID: 8030961

Claim:
A semiconductor integrated circuit comprising: a first variable terminating resistor including a plurality of first transistors of a first conductivity type each having a current path with one end connected to a first power supply and having a control terminal to which one of a plurality of first control signals are input, and a plurality of first resistor elements each having one end connected to the other end of the current path of the associated one of the plurality of first transistors and having the other end connected to a first output terminal; a second variable terminating resistor including a plurality of second transistors of the first conductivity type each having a current path with one end connected to the first power supply and having a control terminal to which one of a plurality of second control signals are input, and a plurality of second resistor elements each having one end connected to the other end of the current path of the associated one of the plurality of second transistors and having the other end connected to a second output terminal; a third transistor of a second conductivity type, which has a current path with one end connected to the other end of the first resistor terminal, and has a control terminal to which a third control signal is input; a fourth transistor of the second conductivity type, which has a current path with one end connected to the other end of the second resistor terminal, and has a control terminal to which a fourth control signal is input; a fifth transistor of the second conductivity type, which has a current path with one end connected to the other end of the current path of the third transistor and to the other end of the current path of the fourth transistor, and with the other end connected to a second power supply, and has a control terminal to which a fifth control signal is input; an information holding circuit is configured to generate select signals selecting the first and second control signals; and a control signal generating circuit which sets, at least at a time of a first state, the plurality of first control signals selected by the information holding circuit, and fifth control signals at a first voltage level, and the second, third and fourth control signals at a second voltage level, and sets, at a time of a second state, the first and second control signals selected by the information holding circuit and the third to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.