Patent ID: 8406058

Claim:
A read only memory, comprising: a control circuit, powered by a first power source, for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range, wherein the top voltage level of the second voltage range is higher than that of the top voltage level of the first voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; the read only memory cell array having a plurality of read only memory cells, wherein the plurality of read only memory cells are made up of a plurality of word lines and bit lines, and each read only memory cell has an n-type transistor having a gate coupled to a respective corresponding word line and a drain coupled to a respective corresponding bit line; and an input/output circuit, for connecting the plurality of bit lines to read out messages, wherein the input/output circuit comprises a row select module, a sensing amplifier and an output latch for implementing bit line selection, sensing and amplifying, and output latch to read messages, and the input/output circuit is powered by the first power source.