Patent ID: 8756406

Claim:
A method for processing data, comprising: identifying one or more instructions by a main core; loading, by the main core, a loop buffer of a co-processor with the one or more instructions of a first instruction thread for the co-processor to execute the one or more instructions independent of the main core in a first mode, the main core and the co-processor being decoupled in the first mode; simultaneously executing a second instruction thread at the main core while the co-processor executes the one or more instructions loaded into the loop buffer while in the first mode; verifying that the co-processor is available based on a first state of a flap; changing a mode of operation of the co-processor from the first mode to a second mode when the co-processor completes the execution of the one or more instructions, the decoupled main core and co-processor being re-coupled in the second mode; and setting the flag to a second state.