Patent ID: 7183660

Claim:
A semiconductor chip package, comprising: a tape circuit substrate including a base film made of an insulating material, and a wiring pattern layer that is formed on the base film and has first leads that are connected to electrode pads arranged near a periphery of a semiconductor chip and second leads that are connected to electrode pads arranged near a center of the semiconductor chip, wherein each of the first and second leads is configured so that a tip end thereof to be bonded to its respective electrode pad has a width larger than that of a body portion thereof; and the semiconductor chip that includes a plurality of electrode pads with chip bumps formed thereon at a main surface thereof, wherein the semiconductor chip is bonded to the first and second leads of the wiring pattern layer through the chip bumps so that the semiconductor chip can be mounted on the tape circuit substrate, wherein the tip end of each of the first and second leads has a width smaller than that of the chip bumps.