Patent ID: 7184736

Claim:
A circuit for suppressing dynamic DC offset, comprising: a capacitor receiving an input signal; a fixed impedance comprising a MOS transistor forming a high pass filter with the capacitor; an impedance control circuit providing a voltage to a gate of the MOS transistor of the fixed impedance, the impedance control circuit comprising a source follower receiving a source voltage at its drain and a constant current source coupled to the source of the source follower, wherein the input signal is provided to the gate of the source follower and to the source of the MOS transistor of the fixed impedance, and wherein the source voltage of the source follower is provided to the gate of the MOS transistor of the fixed impedance; a variable impedance in parallel with the fixed impedance; and a control circuit receiving an output signal of said capacitor and controlling the value of the variable impedance in correspondence with the value of a dynamic DC offset in the output signal of said capacitor to control the corner frequency of the high pass filter in response to the magnitude of the dynamic DC offset.