Patent ID: 7954114

Claim:
A method of interfacing a reconfigurable logic device with a processor and a memory that are external to the reconfigurable logic device, the reconfigurable logic device comprising at least one firmware application module, the firmware application module configured to perform a command-specified data processing operation, the method comprising: the processor writing a plurality of descriptors to a buffer, each descriptor identifying a location in the external memory where an associated block of information for a direct memory access (DMA) transfer is stored, the descriptors comprising a plurality of command descriptors and a plurality of target data descriptors, each command descriptor corresponding to a command information block that defines the data processing operation for the at least one firmware application module, each target data descriptor corresponding to a target data information block that defines target data for delivery to the at least one firmware application module for the at least one firmware application module to perform the command-specified data processing operation upon; the reconfigurable logic device receiving an indication from the processor that information is available in the external memory for the DMA transfer into the reconfigurable logic device; in response to the received indication, the reconfigurable logic device (1) reading a descriptor from the buffer, (2) performing the DMA transfer of the information block identified by the read descriptor from the external memory to the reconfigurable logic device, (3) monitoring whether the DMA transfer is to continue, and (4) repeating the reading and performing steps for the other descriptors in the buffer to thereby transfer the information blocks as a stream into the reconfigurable logic device without requiring intervention by the processor apart from the writing step so long as the monitoring step results in a determination that the DMA transfer is to continue, the stream comprising interleaved command information blocks and target data information blocks such that the at least one firmware application module continuously processes command information blocks and target data information blocks without interruption even when the stream transitions from a target data information block to a command information block and from a command information block to a target data information block.