Patent ID: 8791448

Claim:
A semiconductor memory device, comprising: a plurality of cell regions and a plurality of strapping regions between adjacent cell regions on a semiconductor substrate, wherein the cell regions are spaced apart from one another in a first direction and the cell regions and strapping regions extend in a second direction intersecting the first direction; a plurality of active patterns extending in the first direction throughout the cell regions and strapping regions, wherein the plurality of active patterns are spaced apart from one another in the second direction intersecting the first direction; a plurality of first interconnection lines extending in the first direction throughout the cell regions and the strapping regions, wherein the plurality of first interconnection lines are spaced apart from one another in the second direction and overlap with the active patterns; a plurality of second interconnection lines extending in the second direction and intersecting the active patterns and the first interconnection lines in the cell regions, wherein the plurality of second interconnection lines are spaced apart from one another in the first direction; a plurality of memory cells each at intersection portions of the first and second interconnection lines in the cell regions; and a plurality of strapping contacts in the strapping regions, wherein the active patterns contact the first interconnection lines through the strapping contacts and the strapping contacts in each of the strapping regions are on at least one of the active patterns, wherein the strapping contacts in each of the strapping regions are on the active patterns in a zigzag form in the second direction, and wherein the strapping contacts are along every x of the memory cells on each of the active patterns in the first direction, x representing a number of the second interconnection lines between the strapping regions along each of the active patterns.