Patent ID: 8736471

Claim:
A calibration control circuit for calibrating a stage in a pipeline analog-to-digital converter (ADC), the stage including an analog-to-digital subconverter (ADSC) and a multiplying digital-to-analog converter (MDAC), said ADSC including a plurality of comparators for comparing an input analog signal to reference values to obtain a digital output signal resolving a given number of bits of the input analog signal when the ADC is in an operation mode, said MDAC converting the digital output signal from the ADSC to an analog signal and subtracting it from the input analog signal and amplifying the result to obtain a stage residue signal when the ADC is in an operation mode, said MDAC including an analog multiplexer (AMUX) comprising a plurality of reference switches controlled by the digital output signal from the ADSC for selectively applying reference voltages to capacitors in the MDAC, wherein the calibration control circuit comprises: circuitry coupled to the comparators in the ADSC to force said comparators to output a predetermined digital output signal set by a calibration control signal when the ADC is in a calibration mode to thereby control the reference switches in the AMUX to selectively apply reference voltages to the capacitors in the MDAC to obtain a predetermined stage residue signal.