Patent ID: 6877079

Claim:
A memory module for use in a memory system, the memory module comprising: a first memory module including a memory device, a first buffer, and a second buffer, the first buffer receiving a first write clock signal and a control signal that includes a read or write command in a first direction of transmission, the second buffer receiving the first write clock signal in the first direction of transmission and a first read clock signal in a second direction of transmission, the second buffer being coupled to a first data bus and a second data bus; the first memory module generating a second write clock signal in response to, and in phase with, the first write clock signal, for transmitting data from the second buffer in the first direction of transmission if the write command indicates that data is to be written to a second memory module in the memory system, the first read clock signal and the second write clock signal being transmitted over independent signal lines, and generating a memory write clock signal in response to, and in phase with, the first write clock signal, for writing data from the second buffer to the memory device if the write command indicates that data is to be written to the memory device in the first memory module; and the first memory module generating a memory read clock signal in response to, and in phase with, a memory write clock signal, for reading data from the memory device to the second buffer if the read command indicates that data is to be read from the memory device in the first memory module, the memory write clock signal having substantially the same propagation delay as data transferred from the second buffer to the memory device and the memory read clock signal having substantially the same propagation delay as data transferred from the memory device to the second buffer.