Patent ID: 8890630

Claim:
An oscillator, comprising: a voltage input terminal to receive an input voltage signal; a synchronizing signal input terminal to receive a synchronizing signal; a ramp timing resistance; a ramp timing capacitor which is charged by the input voltage signal through the ramp timing resistance; an input voltage resistor divider network coupled to the voltage input terminal and which produces a discharge trigger reference voltage that is proportional to a voltage of the input voltage signal; a comparator that compares a voltage across the ramp timing capacitor to the discharge trigger reference voltage; a logic circuit that in response to a first state of a synchronization signal, discharges the ramp timing capacitor and that in response to a second state of the synchronization signal when the value of the voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage, delays a discharging of the ramp timing capacitor, wherein at least the comparator and the logic circuit are each formed of a number of discrete semiconductor components; a control transistor; a discharge controlling capacitor; a discharge termination transistor; and a discharge controlling transistor, the control transistor responsive to at least an output of the comparator to selectively charge the discharge controlling capacitor from the voltage input terminal, the discharge controlling capacitor coupled to selectively cause the discharge controlling transistor and the discharge termination transistor to discharge the ramp timing capacitor.