Patent ID: 8270471

Claim:
An encoder for MBAFF coding, wherein frame coding and field coding processes of MBAFF coding comprise at least two encoding stages respectively, the encoder comprising: a first set of processing engines, comprising: a first processing engine for executing a first encoding stage of the frame coding process; and a second processing engine for obtaining a processed macroblock (MB) pair or a processed frame of a MB pair from the first processing engine, executing a second encoding stage of the frame coding process on the obtained MB pair or frame while the first processing engine executes the first encoding stage of the frame coding process on a subsequent MB pair or frame; and a second set of processing engines, comprising; a first processing engine for executing one of the encoding stages of the field coding process on the MB pair or a field of the MB pair in parallel with the corresponding encoding stage executed by one processing engine of the first set of processing engines, and executing a first encoding stage of the field coding process while the first processing engine of the first set executes the first encoding stage of the frame coding process; wherein the first processing engine of the second set executes a first encoding stage of the field coding process while the first processing engine of the first set executes the first encoding stage of the frame coding process, and the second processing engine of the first set obtains the processed MB pair or field from the first processing engine of the second set and sequentially executes a second encoding stage of the field coding process on the obtained processed MB pair or field and the second encoding stage of the frame coding process.