Patent ID: 8749028

Claim:
A semiconductor device comprising: a substrate having a semiconductor element formed on a front surface side thereof; a first metal wiring formed on the substrate; a circuit wiring made from a same metal layer as the first metal wiring, the circuit wiring being electrically connected to the semiconductor element and constituting part of a circuit network; a Low-k insulating film formed to bury the metal wiring and the circuit wiring; and a silicon through electrode extending from a back surface side of the substrate to within the Low-k insulating film, wherein a moisture barrier is formed between the silicon through electrode and the circuit wiring, the moisture barrier comprises a plurality of metal wirings formed in two or more different wiring layers and one or more connection vias connecting one of the plurality of metal wirings formed in an upper wiring layer with another of the plurality of metal wirings formed in one of the wiring layers below the upper wiring layer, the moisture barrier forms, in plan view, one or more ring-shaped frames made up of said plurality of metal wirings and the one or more connection vias, the silicon through electrode is surrounded by the one or more ring-shaped frames in the plan view, said one of the plurality of metal wirings is disposed above the silicon through electrode so as to cover the silicon through electrode, a portion of the low-k insulating film is between a bottom surface of said one of the plurality of metal wirings and a top surface of the silicon through electrode, and said another of the plurality of metal wirings is disposed to a side of the silicon through electrode so as to surround the silicon through electrode in the plan view.