Patent ID: 7989922

Claim:
A metal-oxide-semiconductor (MOS) varactor structure configured to provide a variable capacitance by applying voltage bias of different polarities across electrodes and without physically moving any component therein, comprising: an array of trenches located in a semiconductor substrate; a semiconductor bottom plate of unitary and contiguous construction and comprising a doped single-crystalline semiconductor material located directly on and outside said array of trenches and embedded in said semiconductor substrate, wherein said semiconductor bottom plate contiguously extends laterally from each sidewall of said array of trenches to a sidewall of an adjacent trench among said array of trenches, and said semiconductor bottom plate having a doping of a first conductivity type at a first dopant concentration throughout, and wherein said semiconductor bottom plate is not directly contacting any other semiconductor material located directly on or within said array of trenches; a capacitor dielectric directly contacting all sidewall surfaces and all bottom surfaces of all trenches in said array of trenches and portions of a top surface of said semiconductor substrate between said array of trenches; a semiconductor top plate directly contacting said capacitor dielectric and comprising a doped polycrystalline or amorphous semiconductor material that completely fills said array of trenches; and means for applying voltage biases of different polarities across said top semiconductor top plate and said semiconductor bottom plate with different polarities, wherein said MOS varactor structure has different capacitance depending on a polarity of an applied voltage bias across said top semiconductor top plate and said semiconductor bottom plate.