Patent ID: 6983429

Claim:
A process for determining the optimum load driving capacity for a driving node in a logic circuit comprising the steps of: A) extracting the logic equations of the logic circuit from a circuit description thereof; B) analyzing the fan-out of the driving node to determine if the total number of pass transistor loads is excessive compared to a predetermined driving capacity; C) if, during step B), it is determined that the total number of pass transistor loads is exceeds an absolute maximum, then: 1) to the logic equations of the logic circuit, adding logic equations which represent the sum of the pass transistor loads; 2) to the logic equations of the logic circuit, adding comparator logic equations to compare the number of pass transistors turned on from one to the absolute maximum; 3) using a formal proof program to analyze the logic circuit and determine which of the comparators have a true output; 4) identifying the comparator for the largest number which has a possible true output to determine the highest possible actual load; and 5) if necessary, adjusting the driving capacity of the driving node to handle the determined highest possible actual load.