Patent ID: 7280060

Claim:
A gigabit Ethernet controller, comprising: sixteen sets of digital-to-analog converters (DACs), wherein the sixteen sets of DACs are arranged in parallel, wherein each DAC within a set of DACs is configured to receive an input signal and to provide an output signal, wherein each of the sixteen sets of DACs comprises a corresponding replica current circuit and wherein each of the sixteen sets of DACs comprises: N current sources arranged in parallel, wherein each of the N current sources includes a respective control input, and wherein the output signal provided by each DAC comprises a sum of outputs of the N current sources; and M delay elements, wherein an input of a first one of the M delay elements receives the input signal, wherein an mth one of the M delay elements includes an input in communication with an m−1th one of the M delay elements, wherein an output of one of the M delay elements controls a corresponding control input of one of the N current sources, and wherein a sum of each output signal from a respective one of the sixteen sets of DACs forms an accumulated output signal.