Patent ID: 7292107

Claim:
A phase-locked loop (PLL) modulation circuit, comprising: a modulator for generating a modulation signal; a crystal oscillator for receiving the modulation signal and generating an oscillating signal with a first frequency; a first divisor-controllable frequency divider electrically coupled to the crystal oscillator for dividing the first frequency of the oscillating signal by a first divisor of the first divisor-controllable frequency divider; a PLL unit for receiving the oscillating signal whose frequency has been divided by the first divisor, and the frequency of the oscillating signal divided by the first divisor is sewed as a phase-locked reference frequency; a voltage-controlled oscillator (VCO) for receiving an output from the PLL unit and generating an oscillating signal with a second frequency; and a second divisor-controllable frequency divider for receiving the oscillating signal with the second frequency, and dividing the second frequency of the oscillating signal by a second divisor of the second divisor-controllable frequency divider and providing an output to the PLL unit, wherein the frequency of the oscillating signal divided by the second divisor is served as a feedback frequency of the PLL unit, and the PLL unit performs a phase-locked operation basing on the phase-locked reference frequency and the feedback frequency, wherein the first divisor of the first divisor-controllable frequency divider is synchronized with the second divisor of the second divisor-controllable frequency divider based on data to be modulated.