Patent ID: 8345479

Claim:
A nonvolatile semiconductor memory comprising: a semiconductor substrate; a first memory cell array comprised of plurality of first blocks disposed on the semiconductor substrate, and each of plurality of blocks arranged in a first direction; a second memory cell array comprised of plurality of second blocks disposed on the semiconductor substrate, and each of plurality of blocks arranged in a first direction; a first driver disposed on the semiconductor substrate; and a second driver disposed on the semiconductor substrate, wherein each of the plurality of first blocks and the plurality of second blocks is comprised of at least three conductive layers stacked on the semiconductor substrate by being insulated from each other, and columnar semiconductors passing through the at least three conductive layers, wherein an uppermost layer of the at least three conductive layers is comprised of first select gate lines extending in a second direction orthogonal to the first direction, a lowermost layer of the at least three conductive layers is a second select gate line, remaining conductive layers excluding the uppermost layer and the lowermost layer of the at least three conductive layers are a word line, wherein select gate transistors are comprised of the first select gate lines and the columnar semiconductors, and the second select gate line and the columnar semiconductors, respectively, and memory cells are comprised of the word line and the columnar semiconductor, respectively, and a selected first cell unit and non-selected second cell units are connected to the bit line, and each of the selected first cell unit and the non-selected second cell units is comprised of the memory cells and the select gate transistors, and wherein one of the first select gate lines in one of the plurality of first blocks and one of the first select gate lines in another of the plurality of first blocks are commonly connected, and one of the first select gate lines in one of the plurality of second blocks and one of the first select gate lines in another of the plurality of second blocks are commonly connected.