Patent ID: 8566563

Claim:
Apparatus for processing data comprising: memory address translation circuitry configured to perform a top down page table walk operation to translate a virtual memory address to a physical memory address using translation data stored in a hierarchy of translation tables; wherein said translation data specifies translations between pages of 2 N contiguous bytes of virtual memory addresses and corresponding pages of 2 N contiguous bytes of physical memory addresses, where N is a positive integer; said hierarchy of translation tables comprises translation tables of 2 N contiguous bytes in size such that a complete translation table is stored within one page of said physical memory; and said memory address translation circuitry is responsive to a page size variable specifying a current value of N to control said memory address translation circuitry to operate with a selected size of pages of physical memory addresses, pages of virtual memory addresses and translation tables, wherein different values of said page size variable specify a physical page size of 2 X bytes and a physical page size of 2 Y bytes, where X and Y are integers and said translation data includes contiguousness hint data for specifying that 2 Y−X physical pages of size 2 X bytes are contiguously located within a physical address space.