Patent ID: 8916962

Claim:
A transistor comprising: a III-nitride stack comprising at least a first layer and a second layer, wherein a heterojunction is formed between the first layer and the second layer such that a two-dimensional electron gas layer is formed in the second layer, and wherein the III-nitride stack has a back side surface adjacent to the first layer and a front side surface opposite the back side surface; at least one electrode set formed on the front side surface, wherein each electrode set comprises a source electrode, a drain electrode, and a gate electrode formed between the source electrode and the drain electrode, wherein a first area is formed by the source electrode, a region between the source electrode and the gate electrode, the gate electrode, and a region directly adjacent to the gate electrode, and wherein the first area is separated from the drain electrode by a distance; an insulation layer formed over the at least one electrode set on the front side surface; a carrier substrate attached to the insulation layer; and for each of the at least one electrode sets: (i) an electrically conductive back plate formed on the back side surface, wherein the electrically conductive back plate is electrically connected to the source electrode and covers at least a second area of the back side surface that directly faces the first area, (ii) a back side passivation layer formed on a portion of the back side surface not covered by the electrically conductive back plate, (iii) a source contact pad electrically connected to the source electrode, (iv) a drain contact pad electrically connected to the drain electrode, and (v) a gate contact pad electrically connected to the gate electrode.