Patent ID: 7570525

Claim:
A semiconductor memory device comprising: a plurality of static memory cells arranged in rows and columns, each memory cell including, in a data storage portion, a load transistor connected to a cell power supply node and a drive transistor connected in series to said load transistor; a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row; and a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal, each word line driver including a level shift element for shifting a voltage level of a driver power supply node to a voltage level lower than a voltage of said driver power supply node, and for driving the corresponding word line to the voltage level level-shifted by said level shift element when the corresponding word line is selected, said level shift element being formed of a transistor element, having threshold voltage characteristics similar to those of said load transistor, of a same conductivity type as the load transistor.