Patent ID: 8868873

Claim:
A memory controller, comprising: a mode controller to select a first mode of operation or a second mode of operation; and a memory interface coupled to the mode controller to provide a set of data signals, a first data strobe signal component, and a second data strobe signal component, wherein: in the first mode of operation the memory interface is further to provide a differential data strobe signal, comprising the first and second data strobe signal components, as a timing reference for an entirety of the set of data signals; and in the second mode of operation the memory interface is further to provide the first data strobe signal component, but not the second data strobe signal component, as a timing reference for a first portion of the set of data signals and provide the second data strobe signal component, but not the first data strobe signal component, as a timing reference for a second portion of the set of data signals, wherein the first portion and the second portion are mutually exclusive.