Patent ID: 7234025

Claim:
A microprocessor for executing a prefetch instruction specifying a block of cache lines to be prefetched from a system memory into a cache of the microprocessor, the microprocessor comprising: a prefetch count register, for storing a count of the cache lines remaining to be prefetched; a general purpose register, coupled to said prefetch count register, for storing an initial value of said count, said initial value loaded into said general purpose register by an instruction prior to the prefetch instruction; and control logic, coupled to said prefetch count register, for copying said initial value from said general purpose register to said prefetch count register in response to decoding the prefetch instruction, wherein the prefetch instruction comprises an opcode preceded by a prefix, wherein said opcode is two bytes having predetermined hexadecimal values 0F 18, wherein said prefix is a byte having a predetermined hexadecimal value of F2 or F3.