Patent ID: 7478027

Claim:
A co-simulation system for simulating an integrated design implemented on a data processing system having a machine-accessible medium storing a plurality of program modules, the system comprising: a processor; a memory coupled to said processor; one or more software components stored on the machine-accessible medium and exucuted by the processor to simulate software of the integrated design, the one or more software components each having a single cycle timer and an associated single cycle timing caller to receive requests exclusively from a cycle synchronizer to instruct its associated single cycle timer to begin a new cycle; one or more software function blocks included in each of the one or more software components, each software function block having a single cycle timer and an associated single cycle timing caller to receive requests exclusively from a cycle synchronizer to instruct its associated single cycle timer to begin a new cycle; one or more hardware components stored on the machine-accessible medium to simulate hardware models of the integrated design, the one or more hardware components each having a single cycle timer and an associated single cycle timing caller to receive requests exclusively from a cycle synchronizer to instruct its associated single cycle timer to begin a new cycle; one or more hardware function blocks included in each of the one or more hardware components, each hardware function block having a single cycle timer and an associated single cycle timing caller to receive requests exclusively from a cycle synchronizer to instruct its associated single cycle timer to begin a new cycle; and a cycle synchronizer stored on the machine-accessible medium and in direct communication with each of the one or more software components the software function blocks of each software component, the one or more hardware components, and the hardware function blocks of each hardware component, the cycle synchronizer being adapted to generate cycles used to simulate clock cycles of the co-simulation system and to call once per generated cycle the single cycle timers of each of the one or more software components, the software function blocks of each software component, the one or more hardware components, and the hardware function blocks of each hardware component.