Patent ID: 8559581

Claim:
A reception apparatus comprising: a Clock Data Recovery circuit, abbreviated as a CDR circuit, configured to receive a serial data signal propagated over a data line and regularly inserted with a signal transition to recover a clock and data in accordance with the received serial data signal, said CDR circuit including a divider having a delay element for extracting, as a trigger, a data input regularly inserted with a signal transition and a latch for latching an input data signal in synchronization with a clock extracted by said divider, wherein said divider has a flip-flop configured to enter data from a data input terminal of said flip-flop in synchronization with an input signal into a clock input terminal of said flip-flop and output the held data from a data output terminal of said flip-flop as an extraction clock, and one of one delay element connected to said data output terminal of said flip-flop and a plurality of delay elements cascaded to said data output terminal of said flip-flop; each of said delay elements outputs an extracted clock obtained by delaying an input clock; and an inverted signal of an output extracted clock of any one of said one delay element and said plurality of delay elements is supplied to said data input terminal of said flip-flop.