Patent ID: 8510697

Claim:
A method for improving simultaneous switching output (SSO) noise analysis, comprising: determining, by a processor, a current sharing factor of adjacent areas of an integrated circuit (IC) chip package based upon package inductance, on chip power bus resistance, on chip power bus capacitance, and rise time of actual I/O devices of the IC chip package, wherein the current sharing factor is a ratio of voltage compression between the adjacent areas of the IC chip package; and determining an offload scaling factor of the IC chip package based upon the determined current sharing factor for the adjacent areas of the IC chip package and the actual I/O devices in the adjacent areas of the IC chip package, to perform the SSO noise analysis, wherein the determining the offload scaling factor includes determining a number of equivalent I/O devices in a first area of the adjacent areas of the IC chip package having a highest number of the actual I/O devices in comparison to a number of the actual I/O devices in at least one second area of the adjacent areas of the IC chip package that is adjacent to the first area having the highest number of the actual I/O devices, wherein the offload scaling factor is a ratio of the number of the equivalent I/O devices in the first area to the highest number of the actual I/O devices in the first area; and wherein the adjacent areas of the IC chip package are modeling windows.