Patent ID: 7295458

Claim:
A static random access memory comprising in combination: a plurality of bi-stable memory cells arranged in rows and columns; each of said plurality of memory cells includes a first pull-up transistor and a first pull-down transistor coupled in series between a supply voltage and common and cross coupled with a second pull-transistor and a second pull-down transistor connected in series between said supply voltage and common, and with a first node between said first pull-up transistor and said second pull-down transistor and a second node between said second pull-up transistor and said second pull-down transistor; cells in a column each connected via a pair of write access devices to a pair of write bit lines for writing data into said cell; said cells in a column each connected via a read access device to a read bit line, separate from said pair of write bit lines, for reading data from said cell; and cells in a row each connected via a word line access device to a single word line; whereby activation to respective predetermined states of said word line and said pair of write bit lines writes data to said cell and activation of said word line and said read bit line reads data from said cell.