Patent ID: 8471737

Claim:
A data processing system comprising: a plurality of digital-to-analog (“DA”) converters each converting a portion of a digital input signal to a corresponding analog output signal; an adder configured to add a low-order analog output signal from one of the plurality of DA converters to a high-order analog output signal from another one of the plurality of DA converters and output a combined analog output signal after a predetermined weight has been applied to at least one of the low-order analog output signal and the high-order analog output signal, wherein the low-order analog output signal corresponds to a low-order portion of the digital input signal, the high-order analog output signal corresponds to a high-order portion of the digital input signal, and the predetermined weight is based on a respective relationship between the low-order portion of the digital input signal and the high-order portion of the digital input signal; an analog-to-digital (“AD”) converter that converts the combined analog output signal to a digital feedback signal, the AD converter having a number of bits that is larger than a sum of the number of bits of each of the plurality of DA converters; and a program control circuit configured to control a calibrating process and a high-precision DA converting process, wherein the calibrating process determines whether an error between the predetermined weight and an actual weight is outside an allowable range, the actual weight based on the digital feedback signal, and when it is determined that the error is outside the allowable range, determines a correction factor for correcting the digital input signal, or portions thereof, so as to reduce influence of the error, and wherein the high-precision DA converting process corrects the digital input signal, or portions thereof, with the correction factor before being converted by the plurality of DA converters.