Patent ID: 8554972

Claim:
A logic chip, comprising: a plurality of individually-addressable resource blocks, each comprising logic circuitry; a bus comprising a plurality of bus information lines; wherein a first of the resource blocks comprises a coupling between a first strict sub-set of the bus information lines and the logic circuitry of the first resource block; wherein a second of the resource blocks, which is adjacent to the first resource block, comprises a coupling between a second strict sub-set of the bus information lines and the logic circuitry of the second resource blocks; wherein the first and second sub-sets comprise different bus lines; wherein the bus comprises a plurality of sub-sets of bus information lines; wherein the first strict sub-set of the bus information lines is periodically, in terms of space, coupled with resource block logic circuitry once per N of the individually-addressable resource blocks; wherein the second strict sub-set of the bus information lines is periodically, in terms of space, coupled with resource block logic circuitry once per N of the individually-addressable resource blocks; wherein N is greater than or equal to 2; wherein the bus information lines of the first sub-set are coupled to block logic circuitry of different resource blocks than the bus information lines of the second sub-set; wherein the different sub-sets of bus information lines are periodically connected to coupling circuits with a periodicity of N resource blocks, such that each of N subsequent resource blocks comprises a coupling circuit connected to a different sub-set of the bus information lines and such that a line of resource blocks comprises a periodic sequence of couplings with different subsets of the bus information lines with a spatial periodicity of N; and wherein the coupling circuits are configured to provide a coupling between the bus information lines connected thereto and the logic circuitry of the respective resource blocks.