Patent ID: 8692754

Claim:
A LCD panel, with a visible zone of a dual-gate thin film transistor array, comprising: an invisible zone comprising a gate driver and a wiring zone, wherein the gate driver sequentially outputs plural pulse signals, and by the wiring zone, a (6n+1)-th pulse signal is converted into a (6n+1)-th gate driving signal, a (6n+2)-th pulse signal is converted into a (6n+4)-th gate driving signal, a (6n+3)-th pulse signal is converted into a (6n+5)-th gate driving signal, a (6n+4)-th pulse signal is converted into (6n+2)-th gate driving signal, a (6n+5)-th pulse signal is converted into a (6n+3)-th gate driving signal and a (6n+6)-th pulse signal is converted into a (6n+6)-th gate driving signal; the visible zone of the dual-gate thin film transistor array, comprising a data line, plural sub-pixels and plural gate lines for sequentially receiving the plural gate driving signals, wherein the plural sub-pixels are connected with the data line, the sub-pixels in a same row are alternatively connected to two gate lines respectively, and the same data line is connected to two sub-pixels in a same row, wherein a (6n+1)-th data is received by a (6n+1)-th sub-pixel in response to the (6n+1)-th gate driving signal, a (6n+2)-th data is received by a (6n+2)-th sub-pixel in response to the (6n+4)-th gate driving signal, a (6n+3)-th data is received by a (6n+3)-th sub-pixel in response to the (6n+5)-th gate driving signal, a (6n+4)-th data is received by a (6n+4)-th sub-pixel in response to the (6n+2)-th gate driving signal, a (6n+5)-th data is received by a (6n+5)-th sub-pixel in response to the (6n+3)-th gate driving signal, and a (6n+6)-th data is received by a (6n+6)-th sub-pixel in response to the (6n+6)-th gate driving signal, where n is zero or a positive integer; wherein the data line outputs three same-polarity data sequentially during an initial 3T time intervals, and then the data line outputs six data sequentially while changing polarities once every next 6T time intervals.