Patent ID: 8694747

Claim:
A method for loading and executing, with deterministic execution cycles, a plurality of instructions in an avionic system including at least one processor including at least two cores and at least one memory controller, each of the at least two cores including a private memory, the plurality of instructions being loaded and executed by execution slots, and the method comprising: during a first execution slot: authorizing a first of the at least two cores to access at least one memory controller, the first core transmitting to the at least one memory controller at least one datum stored in the private, previously modified, memory of the first core, and receiving at least one datum and at least one instruction of the plurality of instructions, the at least one datum and the at least one instruction received being stored in the private memory of the first core; prohibiting a second of the at least two cores from accessing the at least one memory controller, the second core executing at least one instruction previously stored in the private memory of the second core; during a second execution slot: prohibiting the first core from accessing the at least one memory controller, the first core executing at least one instruction previously stored in the private memory of the first core; and authorizing the second core to access the at least one memory controller, the second core transmitting to the at least one memory controller at least one datum stored in the private, previously modified, memory of the second core, and receiving at least one datum and at least one instruction of the plurality of instructions, the at least one datum and the at least one instruction received being stored in the private memory of the second core.