Patent ID: 7088730

Claim:
A method for dynamically allocates memories in an Ethernet Switching architecture, comprising steps of: Providing a plurality of input ports and output ports for respectively receiving and transmitting packet segments of a plurality of packets; Providing a dynamic random access memory as a shared memory to store the packet segments after been received from the plurality of input ports but before transmitted out from the plurality of output ports; Providing a first link RAM mapping to the shared memory for controlling a making of a single linked list for the packet segments of each of the plurality of packets while writing the plurality of packets onto the shared memory, and for controlling a reading of the single linked list while reading the plurality of packets; and Providing a second link RAM serving as a first in first out device for co-managing an obtaining of the link address spaces at the corresponding input port before the single linked list been made, and a releasing of the link address spaces at the corresponding output ports after the single linked list been read.