Patent ID: 8094769

Claim:
A phase-locked loop system comprising: a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock; a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses; and a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses, wherein the phase-error spreading circuit comprises: a timing relationship analysis module configured to generate a digital indicia of the phase difference between the reference clock and the feedback clock; and a phase-spread pulses generator for generating the phase-spread pulses based on the digital indicia of the phase difference between the reference clock and the feedback clock, and wherein the phase-spread pulses generator comprises: a programmable ring oscillator for generating a counter clock; a pulse generation controller for generating a plurality of signals by comparing a count value to a plurality of predetermined values; and a pulse width weighted pulse generator for generating the phase-spread pulses based on the plurality of signals and the counter clock.