Patent ID: 8040709

Claim:
A semiconductor storage device comprising: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively driving the first and second wirings, in applying, by the control circuit, a certain potential difference to a selected memory cell positioned at an intersection between the first and second wirings, the plurality of first wirings specified and selectively driven at the same time by one of a plurality of address signals being separately arranged with other first wirings interposed therebetween within the memory cell array, the first wirings being arranged such that a first set of the plurality of first wirings specified and selectively driven at the same time by a first address signal are positioned apart from a second set of the plurality of first wirings specified and selectively driven at the same time by the first address signal, with other first wirings interposed between the first and second set in the memory cell array, and a plurality of sets of the first wirings being repeatedly arranged in the memory cell array, each of the first wirings in one of the plurality of sets being specified by different ones of the address signals.