Patent ID: 7185303

Claim:
A method for generating layout data with a computer to lay out a plurality of macro cells in a core region of a semiconductor device, the method comprising: determining auxiliary layout regions respectively corresponding to the macro cells; storing information of the auxiliary layout regions in a memory; calculating the area of a maximum standard cell region by subtracting the area of the macro cells and the area of the auxiliary layout regions from the area of the core region; storing the area of the maximum standard cell region in the memory; calculating the area of an actual standard cell region in which layout of standard cells is enabled in the core region in accordance with a floor plan result in which the macro cells are laid out; storing the area of the standard cell region in the memory; reading the area of the maximum standard cell region and the area of the actual standard cell region from the memory; calculating a dead space percentage of the floor plan from the area of the maximum standard cell region and the area of the actual standard cell region; comparing the dead space percentage with a reference value; and changing the layout of the macro cells corresponding to the floor plan based on the result of said comparing with the computer so that the dead space percentage becomes less than or equal to the reference value.