Patent ID: 7568176

Claim:
A method for hierarchical integrated circuit repartitioning, comprising: receiving parent level placement data from a computer for one or more interconnecting elements; designating at least one child on a child level by using the computer to receive a pushdown of the one or more interconnecting elements from the parent level, the parent level physically stacked on the child level forming a three-dimension physical structure; and performing for each child designated to receive the pushdown of the one or more interconnecting elements: determining a physical coverage area of the child; identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child via tracing between the child and each interconnecting element within the physical coverage area of the child to verify that the child is the only non-interconnecting element connected to one of an input and an output of each interconnecting element, wherein the verifying results in interconnecting element identification; generating an interconnecting element pushdown list for the child, including wiring layer information; and outputting the interconnecting element pushdown list performing for each common interconnecting element that is identified within the physical coverage area of more than one child; calculating a furthest distance between the common interconnecting element and the more than one child; retaining the identification for the common interconnecting element with the furthest distance; and removing the identification for all of the common interconnecting elements except for the common interconnecting element with the furthest distance.