Patent ID: 7676772

Claim:
A method of optimizing a chip layout section, comprising: generating an initial version of a chip layout section to include a number of locked fill units and a number of shadow fill units, wherein the locked fill units are not removable from the chip layout section during integration of the chip layout section into an overall chip layout, and wherein the shadow fill units are removable from the chip layout section during integration of the chip layout section into the overall chip layout, wherein generating the initial version of the chip layout section includes generating an annotation of one or more electrical effects caused by each shadow fill unit, whereby the one or more electrical effects caused by a given shadow fill unit on a number of affected conductive features within the chip layout section is tabulated against the given shadow fill unit for each of the number of affected conductive features within the chip layout section, wherein evaluating the annotation is performed by a computer; and evaluating the annotation of the one or more electrical effects caused by each shadow fill unit as tabulated within the initial version of the chip layout section to identify which of the number of shadow fill units are to be removed from the initial version of the chip layout section to generate an optimized version of the chip layout section; removing the identified shadow fill units from the initial version of the chip layout section to generate the optimized version of the chip layout section.