Patent ID: 7103697

Claim:
An apparatus for providing a selectively transparent interface for transactions between one or more primary devices on a primary bus and a secondary device on a secondary bus, wherein one or more unique protocols are supported on the primary bus but not on the secondary bus, the apparatus comprising: a first primary input register (PIREG 1 ) for transferring transaction address, control and data information from the primary bus to the secondary bus with a delay of only one clock cycle; a device select (DEVSEL) detector circuit coupled to PIREG 1 for detecting if a transaction address received in PIREG 1 is associated with one of the unique protocols; and a state machine coupled to PIREG 1 and the DEVSEL detector circuit for performing operations to implement one of the unique protocols if the DEVSEL detector circuit determines that the transaction address received in PIREG 1 is associated with one of the unique protocols.