Patent ID: 8199870

Claim:
A shift register unit, comprising: a first thin film transistor, a drain and a gate of which are both connected to a signal input terminal; a second thin film transistor, a drain of which is connected to the source of the first thin film transistor, a gate of which is connected to a reset signal input terminal, and a source of which is connected to a low voltage signal input terminal; a third thin film transistor, a drain of which is connected to a first clock signal input terminal, a gate of which is connected to the source of the first thin film transistor, and a source of which is connected to a signal output terminal; a fourth thin film transistor, a drain of which is connected to the source of the third thin film transistor, a gate of which is connected to the reset signal input terminal, and a source of which is connected to the low voltage signal input terminal; a fifth thin film transistor, a drain of which is connected to the source of the first thin film transistor, and a source of which is connected to the low voltage signal input terminal; a sixth thin film transistor, a drain of which is connected to the source of the third thin film transistor, and a source of which is connected to the low voltage signal input terminal; a seventh thin film transistor, a drain of which is connected to a second clock signal input terminal, and a source of which is connected to the gate of the fifth thin film transistor and the gate of the sixth thin film transistor respectively; a eighth thin film transistor, a drain of which is connected to the source of the seventh thin film transistor, a gate of which is connected to the source of the first thin film transistor, and a source of which is connected to the low voltage signal input terminal; a ninth thin film transistor, a drain and a gate of which are both connected to the second clock signal input terminal, and a source of which is connected to the gate of the seventh thin film transistor; a tenth thin film transistor, a drain of which is connected to the source of the ninth thin film transistor, a gate of which is connected to the source of the first thin film transistor, and a source of which is connected to the low voltage signal input terminal; a capacitor, two ends of which are connected to the gate of the third thin film transistor and the signal output terminal, respectively; and a twelfth thin film transistor, a drain of which is connected to the signal output terminal, a source of which is connected to the low voltage signal input terminal, and a gate of which is connected to the second clock signal input terminal.