Patent ID: 7508899

Claim:
An apparatus for generating a phase offset pulse width modulation (PWM) signal, comprising: a multiple counter comprising: a master timer having an increasing master time value; a period register having a period value; a first comparator having a first input coupled to the master timer and a second input coupled to the period register, wherein when the increasing master time value and the period value are equal an output of the first comparator resets the master time value; and a plurality of pulse width modulation (PWM) generator timer/counters, each of the plurality of pulse width modulation (PWM) generator timer/counters comprises: an offset register; a PWM channel timer having a data input coupled to the offset register, a load input coupled to the first comparator output, a data output and a reset input; a second comparator having a first input coupled to the period register, a second input coupled to the data output of the PWM channel timer, wherein when the period value and the data output of the PWM channel timer are equal an output of the second comparator resets the PWM channel timer; a duty cycle register having a duty cycle value; and a third comparator having a first input coupled to the duty cycle register and a second input coupled to the data output of the PWM channel timer, and an output for generating the phase offset PWM signal.