Patent ID: 7517703

Claim:
A method for forming a ferroelectric memory device, comprising: forming two lower electrode patterns on an interlayer insulating layer covering a semiconductor substrate; forming a seed layer pattern to fill up a space defined between the two lower electrode patterns, wherein a surface that includes the seed layer pattern and the two lower electrode patterns is planar; forming a ferroelectric layer on the planar surface; and forming an upper electrode pattern on the ferroelectric layer, the upper electrode overlapping the two lower electrode patterns wherein: forming the seed layer pattern includes: forming a seed layer on the semiconductor substrate having the two lower electrode patterns, the seed layer filling the space defined between the two lower electrode patterns; and removing a part of the seed layer by performing a planarization process, to expose the two lower electrode patterns and to leave the seed layer pattern for filling up the space defined between the two lower electrode patterns, and the planarization process includes: a chemical mechanical polishing process performed using a pressure for pressing a wafer in a range from about 1 to 5 psi, a pressure for fixing the wafer in a range from about 1 to 5 psi, a speed for rotating a table on which the wafer is placed in a range from about 30 to 50 rpm, and a speed for rotating a head for chucking the wafer in a range from about 10 to 30 rpm.