Patent ID: 7376774

Claim:
In a media access controller system including a processor, a control generator for a processor bridge, comprising: a finite state machine for translating a first register address of a first address space to a second register address of a second address space, wherein the first address space is substantially smaller than the second address space; a plurality of registers associated with the first address space coupled to the processor for receiving a write instruction, the write instruction being initiated by a software program executable by the processor; the plurality of registers include first registers associated with a processor bridge associated with the processor; the finite state machine is configured to bridge the first registers associated with the first address space responsive to the write instruction to map the first registers to second registers for the translating of the first register address to the second register address; the second registers being associated with a media access controller and being associated with the second address space; the finite state machine being broken up into a plurality of finite state machines for mapping the first registers to the second registers; the second registers being control registers associated with the media access controller; and the processor bridge using the plurality of finite state machines configured to emulate host interface signals of a host interface of the processor for access to the control registers.