Patent ID: 7340537

Claim:
A memory agent comprising: a link interface having a plurality of bit lanes to transfer memory read or write data; wherein the memory agent is capable of utilizing more than one of the plurality of bit lanes to detect the presence of another memory agent coupled to the link interface; and wherein the link interface is a first link interface, and the memory agent comprises a memory buffer further including: second, third and fourth link interfaces having second, third and fourth pluralities of bit lanes, respectively, to transfer memory read or write data; a first redrive circuit to redrive memory read or write data from the first link interface to the second link interface; a second redrive circuit to redrive memory read or write data from the third link interface to the fourth link interface; and a memory interface coupled to the first and second redrive circuits; wherein the memory buffer may utilize more than one of the second plurality of bit lanes to signal its presence to another memory agent coupled to the second link interface.