Patent ID: 8502296

Claim:
A method comprising: forming a first insulative layer over a semiconductor substrate; forming at least one control gate comprising first conductive material over the first insulative layer, each control gate having a bottom surface that contacts the first insulative layer and top and side surfaces; forming a second insulative layer over the at least one control gate and over the first insulative layer, the second insulative layer contacting and covering the top and side surfaces of the at least one control gate but not covering the bottom surface of the at least one control gate; depositing a layer of second conductive material over the second insulative layer; and etching the layer of second conductive material to form multiple spacers adjacent to the at least one control gate, the spacers having a height that is less than a height of the first conductive material forming the at least one control gate, wherein at least one of the spacers forms at least one floating gate in at least one memory cell.