Patent ID: 8885785

Claim:
A clock data recovery (CDR) circuit, configured to perform clock synchronization in a terminal with an energy efficient Ethernet (EEE) function, and wherein the CDR circuit comprises: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine; wherein: the state machine is configured to generate a first state signal after receiving an indication based on a timer that the terminal has entered a REFRESH state from a QUIET state, and input the first state signal into the first phase signal selector, the phase signal generator, and the second phase signal selector; the phase detector is configured to acquire a phase error between the terminal and a peer end from training data sent by the peer end, and input the phase error into the first phase signal selector; the first phase signal selector is configured to select an input phase signal between a previously input phase signal 0 and the phase error input by the phase detector, and input the input phase signal into the loop filter, wherein the first phase signal selector selects the previously input phase signal 0 as the input phase signal based on receiving the first state signal from the state machine; the loop filter is configured to output, according to the previously input phase signal 0, a first phase error saved in a first register module to the numerical controlled oscillator; the numerical controlled oscillator is configured to accumulate the first phase error saved in the first register module and a second phase error saved in a second register module of the numerical controlled oscillator, and input an accumulated value of the first and second phase errors into the second phase signal selector; the phase signal generator is configured to generate, according to the indication of the first state signal and an initial phase signal saved in the phase signal generator, a phase signal satisfying a preset clock synchronization condition, and input the phase signal into the second phase signal selector; and the second phase signal selector is configured to select, according to the indication of the first state signal, the phase signal satisfying the preset clock synchronization condition and input by the phase signal generator as a phase selection signal of the CDR circuit, wherein the phase selection signal is used to enable the terminal to implement the clock synchronization with the peer end according to the phase selection signal.