Patent ID: 7761171

Claim:
An apparatus to generate a schedule to execute functions in a process control system, the apparatus comprising: a processor apparatus, comprising: a first interface configured to identify a first function to be performed by a first field device communicatively coupled to a process controller via a data bus and a second function to be performed by a second field device communicatively coupled to the process controller via the data bus, wherein the first field device communicates first information associated with the first function via the data bus based on a first data communication time period, and wherein the second field device communicates second information associated with the second function via the data bus based on a second data communication time period; a sub-schedule generator configured to generate a first sub-schedule associated with a first sub-schedule time period, wherein the first sub-schedule indicates a first execution time at which the first function is to be performed; a schedule generator configured to form a schedule associated with a schedule time period based on two instances of the first sub-schedule and based on the first data communication time period being less than the second data communication time period, wherein the schedule indicates the first execution time and a second execution time at which the first function is to be performed; and a start time offset determiner configured to determine a quantity of start time offsets indicating a quantity of times that the first function is to be performed during the first sub-schedule, the quantity of start time offsets based on a slowest function block execution period associated with the first field device configured to perform the first function and a function block execution period of the first function.