Patent ID: 7317643

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cell transistors arranged in matrix form, each of the memory cell transistors having a first main electrode, a second main electrode and a control electrode, each of the memory cell transistors being written with a stored value depending on whether a connection is made between the first main electrode thereof and a first voltage line; a plurality of word lines connected to the control electrodes of the memory cell transistors of corresponding rows of the memory cell array, respectively; a plurality of bit lines connected to the second main electrodes of the memory cell transistors of corresponding columns of the memory cell array, respectively; a data line for selectively outputting voltages of the bit lines; a plurality of selector circuits, each of the selector circuits being installed between a corresponding one of the bit lines and the data line, each of the selector circuits electrically connecting the corresponding bit line with the data line when a select signal inputted thereto assumes a select level, and electrically isolating the corresponding bit line from the data line when the inputted select signal assumes a non-select level; at least one precharge circuit connected to a first input signal line, the first input signal line transferring a common first input signal having any one of a first active level and a first inactive level, the precharge circuit precharging the bit lines to a predetermined voltage level, the predetermined voltage level being different from a voltage level of the first voltage line; and at least one pull-down circuit connected to a second input signal line, the second input signal line transferring a common second input signal having any one of a second active level and a second inactive level, the pull-down circuit pulling the bit lines down to the voltage level of the first voltage line.