Patent ID: 7180803

Claim:
A data compression circuit in a memory device, comprising: a plurality of first buffer circuits, each first buffer circuit for receiving a data signal corresponding to a given bit location of a word of an output page of the memory device and for driving a first current level if the data signal has a first data value and for sinking a second current level if the data signal has a second data value, wherein there is a first buffer circuit for each word of the output page and wherein the first current level is greater than a product of the second current level times the number of first buffer circuits minus one; a plurality of second buffer circuits, each second buffer circuit for receiving the data signal corresponding to the given bit location of the word of the output page of the memory device and for driving a third current level if the data signal has the second data value and for sinking a fourth current level if the data signal has the first data value, wherein there is a second buffer circuit for each word of the output page and wherein the fourth current level is greater than a product of the third current level times the number of second buffer circuits minus one; and a logic circuit for receiving a first signal indicative of a sum of the current levels from the number of first buffer circuits at a first input, for receiving a second signal indicative of a sum of the current levels from the number of second buffer circuits at a second input, and for providing a control signal indicative of whether the first and second signals have differing logic levels.