Patent ID: 8111542

Claim:
A static random access memory (SRAM) cell comprising: a pair of cross-coupled inverters having a first storage node; a first NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the first storage node, a read word-line (RWL) and a first read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation; a second storage node belonging to the pair of cross-coupled inverters, the second storage node being complementary to the first storage node; and a second NMOS transistor having a gate terminal, a third and a fourth source/drain terminal connected to the second storage node, the RWL and a second RBL, respectively; a third NMOS transistor having a gate terminal, a fifth and sixth source/drain terminal connected to a write word-line (WWL), the first storage node and a first write bit-line (WBL), respectively; and an inverter having a voltage supply, an input and an output connected to a first select line, a second select line and the WWL, respectively.