Patent ID: 8090913

Claim:
An apparatus comprising: an integrated circuit including a multi processor core circuit, wherein the multi processor core circuit is operable to include: a first coherency group, wherein the first coherency group includes a first plurality of processor cores of the multi processor core circuit, the processor cores of the first coherency group are serially communicatively coupled to propagate information packets, wherein each processor core of the first coherency group receives cache coherency information from write packets to a memory generated by other processor cores of the first coherency group; a second coherency group, wherein the second coherency group includes a second plurality of processor cores of the multi processor core circuit, the processor cores of the second coherency group are serially communicatively coupled to propagate information packets, wherein each processor core of the second coherency group receives cache coherency information from write packets to the memory generated by other processor cores of the second coherency group and does not receive cache coherency information of write packets to the memory generated by the processor cores of the first coherency group; wherein each processor core of the first coherency group does not receive cache coherency information of write packets to the memory generated by the processor cores of the second coherency group.