Patent ID: 7723828

Claim:
A semiconductor package primarily comprising: a chip having an active surface with a first row of bonding pads and a second row of bonding pads disposed on the active surface in parallel; a leadframe including a plurality of first leads and at least a bus bar, wherein each first lead has a first finger, the first leads are attached to the active surface of the chip in a manner that the first fingers are located above the active surface and adjacent to the first row of bonding pads, wherein the bus bar is also attached to the active surface of the chip and is disposed between the first row of bonding pads and the first to fingers, wherein the attached portion of the bus bar on the active surface includes a bent section bent away from one of the first fingers; a plurality of first bonding wires electrically connecting the first row of bonding pads to the first fingers; and at least a long bonding wire electrically connecting one of the second row of bonding pads to the one of the first fingers by overpassing the bent section of the bus bar; wherein the chip has a non-pad open area interposed into the first row of bonding pads, wherein the length of the non-pad open area is greater than the average spacing of the first row of bonding pads, and wherein the bent section is overlapped on the open area.