Patent ID: 7723229

Claim:
A process of forming a contact opening in a semiconductor device, wherein the semiconductor device includes one or more gate electrode structure formed over a substrate, a spacer formed on a sidewall of the gate electrode structure, a bottom liner layer laid over the substrate and adjacent to the spacer, and a dielectric material covering the gate electrode structure, the process comprising: forming a patterned masking layer on a surface of the dielectric material; etching a portion of the dielectric material through the masking layer until a shoulder of the spacer is reached; forming a masking deposit on the shoulder of the spacer from residue of the etched dielectric material; etching the dielectric material with the masking deposit on the shoulder of the spacer until the bottom liner layer is exposed, wherein etching the dielectric material produces a protective layer on a sidewall of the spacer; removing the masking deposit from the shoulder of the spacer; and etching the exposed bottom liner layer using the protective layer as a mask.