Patent ID: 8258856

Claim:
An antifuse circuit comprising: a protection circuit including a first protection unit connected between a first pad and a common node of a common line, and configured to apply a program voltage, received from the first pad, to the common node when the program voltage is higher than a boost voltage and the first protection unit is configured to prevent application of the program voltage to the common node when the program voltage is lower than the boost voltage; and at least one antifuse unit connected to the protection circuit along the common line, each of the at least one antifuse unit including an antifuse, and configured to program the antifuse with the program voltage in response to a selection signal and a program mode signal in a program mode and output an output signal according to a program state of the antifuse in a normal mode, wherein the first protection unit comprises: a PMOS transistor connected between the first pad and the common node and having a gate to which the boost voltage is applied; and a diode connected between a body of the PMOS transistor and a power supply voltage that is lower than the boost voltage.