Patent ID: 7816187

Claim:
A method for fabricating a semiconductor package, comprising the steps of: preparing a metal carrier; applying a dielectric material layer over a surface of the metal carrier, and forming a plurality of openings through the dielectric material layer; applying a conductive material in the openings of the dielectric material layer; forming a conductive layer on the dielectric material layer and the conductive material, wherein the conductive layer comprises a plurality of conductive traces, and each of the conductive traces has a terminal; mounting at least one chip on the dielectric material layer via a bottom surface of the chip, and electrically connecting the chip to the terminals of the conductive traces; forming an encapsulant for encapsulating the chip and the conductive layer, wherein side surfaces of the chip are encapsulated by the encapsulant; and removing the metal carrier to partly expose the dielectric material layer and the conductive material.