Patent ID: 8436399

Claim:
A semiconductor device comprising: a substrate; a nitride semiconductor layer formed above said substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of said nitride semiconductor layer; and a field-effect transistor formed in a region of said nitride semiconductor layer, the region being different from the region in which said heterojunction bipolar transistor is formed, wherein said nitride semiconductor layer includes: a first nitride semiconductor layer formed above said substrate; a second nitride semiconductor layer formed on said first nitride semiconductor layer; and a third nitride semiconductor layer formed on said second nitride semiconductor layer, and said semiconductor device further comprises: an isolation region which separates each of said first nitride semiconductor layer, said second nitride semiconductor layer, and said third nitride semiconductor layer into a first region in which said heterojunction bipolar transistor is formed and a second region in which said field-effect transistor is formed, said first region and said second region being electrically isolated from each other, a collector electrode of said heterojunction bipolar transistor is electrically connected to said first nitride semiconductor layer in said first region, a base electrode of said heterojunction bipolar transistor is electrically connected to said second nitride semiconductor layer in said first region, an emitter electrode of said heterojunction bipolar transistor is electrically connected to said third nitride semiconductor layer in said first region, a source electrode and a drain electrode of said field-effect transistor are electrically connected to one of said first nitride semiconductor, said second nitride semiconductor layer, and said third nitride semiconductor layer in said second region, and a gate electrode of said field-effect transistor is formed on one of said first nitride semiconductor, said second nitride semiconductor layer, and said third nitride semiconductor layer in said second region.