Patent ID: 7923337

Claim:
A method for fabricating a field effect transistor device, the method comprising the steps of: providing a substrate having a silicon layer thereon; patterning a fin lithography hardmask on the silicon layer; placing a dummy gate structure over a central portion of the patterned fin lithography hardmask; depositing a filler layer around the dummy gate structure; removing the dummy gate structure to reveal a trench in the filler layer, centered over the central portion of the patterned fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device; using the patterned fin lithography hardmask in the fin region revealed after the dummy gate structure is removed to etch a plurality of fins in the silicon layer; filling the trench with a gate material to form a gate stack over the fins; and removing the filler layer to reveal the source and drain regions of the device, wherein the source and drain regions are intact and self-aligned with the gate stack.