Patent ID: 7885203

Claim:
A system for testing asynchronous transfer mode traffic, the system comprising: an interface to connect to a network that carries asynchronous transfer mode traffic; a processor configurable by software for conducting a test of the asynchronous transfer mode traffic on the network; and a memory storing instructions for causing the processor to control the system to execute an algorithm comprising: specifying a particular asynchronous transfer mode (ATM) connection on the network; establishing a plurality of counters, each of which counters is associated with a corresponding intra-cell delay time between receipt of a pair of consecutively-received ATM cells for the specified ATM connection and is configured to generate a count value indicating a number of occurrences of the corresponding intra-cell delay time; receiving a plurality of new ATM cells for the specified ATM connection; for each received new ATM cell for the specified ATM connection: measuring an intra-cell delay between an arrival time of the new ATN cell and an arrival time of an immediately previously received ATM cell for the specified ATM connection, identifying one of the counters corresponding to the measured intra-cell delay time, and incrementing the identified counter; and displaying a graph indicating a distribution of the numbers of occurrences of the intra-cell delay times, based on the count values of the plurality of counters.