Patent ID: 7365377

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; a first well region of the first conductivity type which is formed in a first region of the semiconductor substrate; a plurality of second well regions of a second conductivity type which are formed in the first region of the semiconductor substrate excluding the region where the first well region has been formed; a third well region of the second conductivity type which is formed under the first and second well regions in the first region of the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed and which connects the second well regions to one another electrically, the third well region is provided under the first well region and has a window which connects the first well region to the semiconductor substrate electrically; a fourth well region of the first conductivity type which is formed in a second region of the semiconductor substrate; a fifth well region of the second conductivity type which is formed in the second region of the semiconductor substrate so as to enclose the fourth well region; a sixth well region which is formed under the fourth and fifth well regions in the semiconductor substrate so as to separate the fourth well region from the semiconductor substrate electrically; a first group of MOS transistors which is formed in each of the first and second well regions and operates on a first power supply voltage; a second group of MOS transistors which is formed in each of the fourth and fifth well regions and operates on a second power supply voltage; at least one first terminal which applies a first bias potential to the first well region; at least one second terminal which applies a second bias potential to the second and third well regions; and at least one third terminal which applies a third bias potential to the fourth well region.