Patent ID: 8103896

Claim:
For use with an I 2 C bus having a clock signal, a method of using logic circuitry to control the clock signal on the I 2 C bus, the logic circuitry arranged in a state machine to implement the method comprising: in a first state of the state machine, determining whether to effect a clock stretching delay; in a second state of the state machine and in response to determining not to effect a clock stretching delay, determining whether the I 2 C bus is configured to run in a standard clock mode or in another one of multiple faster clock modes including a fast clock mode; in a third state of the state machine and in response to determining that the device is not configured to run in either the standard clock mode or the fast clock mode, driving the clock signal in one binary logic state for more than about 0.5 microseconds and less than about 2.5 microseconds before allowing the clock signal to be driven in the other binary logic state and allowing the clock signal to remain in the other binary logic state for more than about 0.5 microseconds and less than about 2.5 microseconds before driving the clock signal in the one binary logic state.