Patent ID: 7796456

Claim:
A semiconductor device comprising: a first fuse circuit; a second fuse circuit; a program control circuit performing, when allowed, a programming operation on the first fuse circuit; and a gate circuit allowing the program control circuit to perform the programming operation on the first fuse circuit when the second fuse circuit produces a first level and inhibiting the program control circuit from performing the programming operation on the first fuse circuit when the second fuse circuit produces a second level, wherein the second fuse circuit is programmed from the first level to the second level before the first fuse circuit has been programmed, wherein the device further comprises a third fuse circuit, and a fourth fuse circuit, the program control circuit performs, when allowed, a programming operation on the third fuse circuit, the device further comprising an additional gate circuit allowing the program control circuit to perform the programming operation on the third fuse circuit when the fourth fuse produces the first level and inhibiting the program control circuit from performing the programming operation on the third fuse circuit when the fourth fuse circuit produces the second level, the fourth fuse circuit being programmed from the first level to the second level after the third fuse circuit has been programmed.