Patent ID: 8088687

Claim:
A method for forming a copper line of a semiconductor device, comprising the steps of: forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the interlayer dielectric and on a surface of the metal line forming region; adsorbing catalytic particles on a surface of the self-assembled monolayer; forming a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto by using an electroless plating technique; and forming a copper layer on the copper seed layer to substantially fill in the metal line forming region, wherein the step of forming the self-assembled monolayer comprises the steps of: modifying a surface of the semiconductor substrate having the metal line forming region to form hydroxyl groups bonded to the surface of the semiconductor substrate; dipping the resultant surface-modified semiconductor substrate in a chemical solution having either amine silane groups or thiol silane groups mixed in an organic solvent to bond either the amine silane groups or the thiol silane groups to the surface of the semiconductor substrate; and silanizing the amine silane groups or thiol silane groups bonded to the surface of the semiconductor substrate.