Patent ID: 7222146

Claim:
An apparatus that facilitates performing exception-free arithmetic operations within a computer system, comprising: an arithmetic unit that is configured to receive an instruction to perform an arithmetic operation during execution of a program on the computer system, wherein the arithmetic operation manipulates floating-point values, wherein the arithmetic operation is an interval operation that manipulates at least one interval, and wherein the interval is defined by a first floating-point value that specifies a left endpoint (lower bound) of the interval and a second floating-point value that specifies a right endpoint (upper bound) of the interval; and wherein in response to the instruction, the arithmetic unit is configured to perform the arithmetic operation; wherein if the arithmetic operation manipulates a floating-point value representing {+0}, the arithmetic operation is performed in a manner consistent with {+0} representing the limit of a sequence of values that approaches zero only from above; and wherein if the arithmetic operation manipulates a floating-point value representing {−0}, the arithmetic operation is performed in a manner consistent with {−0} representing the limit of a sequence of values that approaches zero only from below.