Patent ID: 7698079

Claim:
A computer-implemented method of characterizing process variations between integrated circuit (IC) dies, the method comprising: a computer recording electric current measurements at each power supply pad in an integrated circuit (IC) die that is being tested, wherein the electrical current measurements are of a quiescent current (IDDQ) drawn at each power supply pad, and wherein the IDDQ is current that is caused by leakage in the IC die; the computer combining recorded electrical current measurements for every power supply pad in the IC die to create a global IDDQ signature for the IC die, wherein the global IDDQ signature is created by forming an n-tuple of individual IDDQ ratios for each power supply pad in the IC die, and wherein each individual IDDQ ratio for each power supply pad is calculated from a ratio IDDQpad/IDDQglobal, wherein IDDQpad is a measured quiescent electric current at a particular power supply pad and IDDQglobal is a measured quiescent electric current for all of the IC die, and wherein each global IDDQ signature indicates how much electric current is drawn at each power supply pad during quiescent activity periods for the IC die; the computer storing the global IDDQ signature as a stored unique signature, wherein the stored unique signatures describe a plurality of spatially correlated across-die process variations that occurred during manufacturing of the IC die; the computer comparing a current IC unique signature with stored unique signatures of other IC dies, wherein the current IC unique signature is calculated as another n-tuple by using the ratio IDDQpad/IDDQglobal for every power supply pad in a current IC die being tested; and the computer ranking, and sorting for binning, the current IC die by comparing the current IC unique signature for the current IC die to stored unique signatures for the other IC dies.