Patent ID: 8566504

Claim:
A method of operating a block-erasable nonvolatile memory array comprising: programming first data to a first plurality of blocks in parallel, each of the first plurality of blocks from a different one of a plurality of planes and from a first metablock, the first metablock having a fixed storage capacity; programming second data to a second plurality of blocks in parallel, each of the second plurality of blocks from a different one of the plurality of planes and from a second metablock, the second metablock having a fixed storage capacity equal to the fixed storage capacity of the first metablock; subsequently performing a first operation comprising copying data from a first block of the first plurality of blocks, without copying data from other ones of the first plurality of blocks, the first block located in a first plane of the plurality of planes; and in parallel with performing the first operation comprising copying data from the first block, accessing a second block of the second plurality of blocks, the second block located in a second plane of the plurality of planes, wherein the first plane from which the first block is copied differs from the second plane from which the second block is accessed, and wherein accessing the second block comprises performing a second operation separate and independent from the first operation comprising copying data from the first block.