Patent ID: 8202754

Claim:
A method for packaging a microelectronic device, comprising: aligning a first element, an intermediate element and a second element to form a support member, the first element comprising: a first conductive layer of the first element, a first insulating layer bonded to the first conductive layer of the first element, and a second conductive layer of the first element having: one side bonded to the first insulating layer, and another side bonded to the intermediate element, the second element comprising: a first conductive layer of the second element having: one side bonded to the intermediate element, and another side bonded to a second insulating layer, the second insulating layer bonded to the first conductive layer of the second element, and a second conductive layer of the second element bonded to the second insulating layer wherein the support member has a cavity including a first cavity portion and a second cavity portion; and wherein the first cavity portion extends directly through apertures in the first conductive layer, the second conductive layer, the insulating layer of the first element, and the intermediate element; and wherein the second cavity portion extends directly through apertures in the first conductive layer of the second element and the second insulating layer of the second element, the second conductive layer of the second element forming a closed end of the cavity, and wherein the first and second cavities are substantially aligned to form an opening through which the second cavity portion is accessible; positioning a microelectronic device in the cavity of the support member, the microelectronic device including a first surface, a second surface facing opposite from the first surface, and bond sites at the first surface and at the second surface, the second surface facing toward and carried by the second conductive layer of the second element; and electrically coupling bond sites of the microelectronic device at the first surface of the microelectronic device to the second conductive layer of the second element.