Patent ID: 8391052

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array, the memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of electrically rewritable memory cells disposed at each of intersections of the first lines and the second lines, each of the memory cells being configured from a variable resistor operative to store a resistance value of the variable resistor as data in a nonvolatile manner; a voltage supply circuit operative to apply a certain voltage to the memory cells via the first lines and the second lines during writing data to the memory cells or forming of the memory cells; a detection circuit operative to detect a change of the resistance value of the variable resistor in the memory cell during application of the certain voltage to the memory cells and output the detected change of the resistance value of the variable resistor as detection information; and an output circuit operative to output to external at least a portion of the detection information outputted from the detection circuit.