Patent ID: 7428672

Claim:
A method for testing a memory device comprising: placing said memory device in a test mode; disconnecting all match lines of said memory device from a priority encoder of said memory device; confirming proper operation of a control line used to enable output from a match line under test; connecting an output from the match line under test to the priority encoder; decoding an address of a selected memory storage location corresponding to said match line under test; loading said selected memory storage location and a comparand register with a known data pattern; performing a search operation, for the known data pattern in the comparand register, on said memory device; outputting a result of said search operation; comparing said result of said search operation with an expected result of said search operation, said expected result comprising an expected match indication on the match line under test; confirming proper operation of said memory device if said result of said search operation is equal to said expected result of said search operation; and indicating an error of said memory device if said result of said search operation is not equal to said expected result of said search operation.