Patent ID: 8295698

Claim:
A time-coherent network comprising: a plurality of primary switch units arranged in a first matrix having μ columns and μ rows, each primary switch unit having a primary controller, m bufferless inlet ports and m outlet ports, μ>1, m>1; and a plurality of secondary switch units arranged in a second matrix having ν columns and ν rows, each secondary switch unit having a secondary controller, n bufferless inlet ports and n outlet ports, ν≧μ, 1<n≦m; a plurality of edge nodes, each edge node having: an edge controller; a primary upstream channel carrying payload and control signals to a primary switch unit in each column of said first matrix; a secondary upstream channel carrying payload and control signals to a secondary switch unit in each column of said second matrix; a primary downstream channel carrying payload and control signals from a primary switch unit in each row of said first matrix; a secondary downstream channel carrying payload and control signals from a secondary switch unit in each row of said second matrix; wherein μ, m, ν, and n are selected so that μ×m=ν×n.