Patent ID: 7200040

Claim:
A method of operating a P-channel memory having a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and the gate, and a first source/drain and a second source/drain formed in the substrate adjacent two sides of the charge trapping structure, the method comprising: performing a programming operation to inject electrons in the side of the charge trapping structure adjacent to the first source/drain to store a first bit in the P-channel memory; and performing an erasing operation by applying a first voltage to the second source/drain, applying a second voltage to the first source/drain, applying a third voltage to the gate, and applying a fourth voltage to the substrate to inject hot holes in the side of the charge trapping structure adjacent to the first source/drain by a tertiary hot hole mechanism to erase the first bit stored in the P-channel memory, wherein a voltage differential between the third voltage and the fourth voltage is smaller than or equal to 6V, and the second voltage is smaller than the third voltage.