Patent ID: 7943456

Claim:
A method for fabricating a CMOS integrated circuit (IC) comprising devices having embedded epitaxial strain inducing regions, comprising: providing a substrate having a semiconductor surface comprising PMOS regions for PMOS devices and NMOS regions for NMOS devices; forming gate stacks each comprising a gate electrode layer on a gate dielectric layer, in or on both said PMOS regions and said NMOS regions; n-type doping to create n-type wet etch sensitized regions on opposing sides of each of said gate stacks in said PMOS and said NMOS regions; wet etching to remove said n-type wet etch sensitized regions in at least a portion of said PMOS regions to form a plurality of PMOS source/drain recesses; and forming a compressive strain inducing epitaxial layer in said plurality of PMOS source/drain recesses.