Patent ID: 6897531

Claim:
A semiconductor memory device having full depletion type MISFETs to constitute memory cells on a semiconductor substrate via an insulating film, each of the MISFETs comprising: a semiconductor layer formed on the insulating film; a source region formed in the semiconductor layer; a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a main gate formed on a first side of the channel body to form a channel in the channel body; and an auxiliary gate formed on a second side of the channel body, the second side being opposite to the first side, a portion of the second side of the channel body being capable of accumulating majority carriers under conditions in which the channel body is fully depleted by an electric field from the main gate and an electric field is applied to the channel body from the auxiliary gate, wherein the MISFET has a first data state in which the majority carriers are accumulated in the portion of the second side of the channel body and a second data state in which the majority carriers accumulated in the portion of the second side of the channel body are emitted, wherein the MISFETs are arranged in the form of a matrix to constitute a cell array, the drain regions are connected to bit lines, the main gates constitute word lines intersecting the bit lines, the source regions are connected to a fixed potential line and the auxiliary gate is formed as a common electrode shared among the memory cells, wherein the first side of the channel body is a top side face of the semiconductor layer, the second side of the channel body is a back side face of the semiconductor layer and the main gate is formed on the ton side face via a gate insulating film, and wherein the auxiliary gate is an impurity doping layer buried between the semiconductor substrate and the insulating film.