Patent ID: 8766399

Claim:
A semiconductor device comprising: a semiconductor substrate; a groove formed in the semiconductor substrate; a first insulating film embedded in the groove; a first active region of the semiconductor substrate, a plurality of second active regions of the semiconductor substrate, and a third active region of the semiconductor substrate defined by the groove; a first MISFET formed in the first active region; a second insulating film formed over the first and second active regions so as to cover the first MISFET; and a first metal pattern and a second metal pattern formed over a second insulating film portion which is formed over the second active regions, wherein the first metal pattern comprises one electrode of a first capacitance element, wherein the second metal pattern comprises another electrode of the first capacitance element, wherein the second active regions do not function as part of a MISFET, wherein, in a plan view, each of the second active regions is disposed below the first capacitance element so as not to overlap the first metal pattern and the second metal pattern, wherein a third metal pattern which is a shielding metal pattern substantially surrounds the first and second metal patterns and is connected to a fixed potential, wherein, in the plan view, the third active region surrounds the second active regions, is disposed below the third metal pattern, and is electrically coupled to the third metal pattern, and wherein the third second active regions are electrically coupled to the third mental patter through the third active region.