Patent ID: 7640418

Claim:
A system for implementing a memory architecture, the system comprising: a first read-only memory (ROM) storing first microcode; a first random access memory (RAM) storing second microcode and a select bit for selecting one of the first microcode and the second microcode; a first multiplexer coupled to the ROM and the RAM and adapted to receive the first microcode, the second microcode and the select bit, the first multiplexer being adapted to provide a first output signal of microcode selected from the first microcode and the second microcode as determined by the select bit; a second ROM storing third microcode; a second RAM storing fourth microcode; a counter adapted to provide a control signal having at least two data bits for selecting one of the third microcode, the fourth microcode, and the first output signal for execution; a second multiplexer coupled to the second ROM, to the second RAM, and to the first multiplexer and adapted to receive the third microcode, the fourth microcode, and the first output signal, the second multiplexer being adapted to receive the control signal from the counter and adapted to provide a second output signal selected from one of the third microcode, the fourth microcode, and the first output signal as determined by the control signal.