Patent ID: 7754566

Claim:
A process for manufacturing an integrated power electronic device on a semiconductor substrate of a first type of conductivity comprising a plurality of elemental units comprising the steps of: forming a first semiconductor layer of the first type of conductivity and of a first resistivity value on said highly doped semiconductor substrate, forming, for each elemental unit, a first sub-region of a second type of conductivity by means of a first selective implant step with a first implant dose, forming at least a second semiconductor layer of the first type of conductivity and of a second resistivity value on said first semiconductor layer, said second resistivity value being different than said first resistivity value, forming a second sub-region of the second type of conductivity in said second semiconductor layer by means of a second implant selective step with a second implant dose, said second sub-region being aligned with said first sub-region, wherein the amount of charge of each doped sub-regions balances the amount of charge of the semiconductor layer in which each doped sub-region is realized, forming a surface semiconductor layer of the first type of conductivity of a third resistivity value on said second semiconductor layer, said third resistivity value being different than said second resistivity value, forming in said surface semiconductor layer a body region of the second type of conductivity, aligned with said sub-regions, carrying out a thermal diffusion step so that said first sub-region and second sub-region form a single column region.