Patent ID: 7440303

Claim:
A semiconductor memory device comprising a matrix-like arrangement of memory elements in rows and columns, the semiconductor memory device comprising: a plurality of selection transistors, each selection transistor having two source/drain regions and an intervening channel controlled by a gate electrode, the selection transistors being arranged in rows and columns, said rows defined as being parallel to word lines and said columns defined as being parallel to bitlines; a plurality of word lines, each word line being coupled to the gate electrodes of selection transistors arranged in a row; a plurality of bit lines, each bit line being coupled to a respective source/drain region of a plurality of selection transistors arranged along said bit line, no two of said pairs arranged in the same row, wherein each selection transistor is coupled to precisely one bit line; and a plurality of memory elements formed as resistance memory elements, each one of the memory elements being coupled to only one read/write line, and each memory element being further coupled between its respective read/write line and a source/drain region of a selection transistor that is not coupled to a bit line, wherein memory elements in adjacent columns along a read/write line are coupled to selection transistors that are coupled to different word lines.