Patent ID: 7830906

Claim:
A system comprising: a master device having a clock terminal, a frame terminal, a data-in terminal, and a data-out terminal, wherein a frame synchronous signal is received through the frame terminal, and wherein master device supplies a device identifier setting command through its data-out terminal in synchronization with a frame synchronous signal; and a plurality of slave devices that are coupled to one another in a cascading sequence through daisy-chain input and output terminals within each of the slave devices, wherein each slave device includes: a clock input terminal coupled to the clock signal of the master device; a frame terminal coupled to the frame signal terminal of the master device; a data-in terminal coupled to the data-out terminal of the master device; a data-out terminal coupled to the data-in terminal of the master device; a device ID assignment circuit coupled to each of its daisy-chain input and output terminals, wherein the device ID assignment circuit includes: a sequence initiation control circuit that outputs a sequence signal that indicates a device identifier decision sequence in response to the device identifier setting command and the frame synchronous signal; a counter that counts the clock signal in response to the sequence signal; a token generation circuit that generates a device identifier setting token for a subsequent slave device in the sequence in response to the clock signal and one of a predetermined logic signal from the master device and the device identifier setting token from a previous slave device; and a time slot allocation circuit coupled to each of its daisy-chain input and output terminals.