Patent ID: 7299390

Claim:
A circuit for encrypting scan data, comprising: an interlinked chain of exclusive-or logic gates and registers, wherein a first input of each exclusive-or logic gate is connected to an output of a preceding register and an input of each register is connected to an output of a preceding exclusive-or logic gate; and a plurality of scan output chains, each of the plurality of scan output chains having an output connected to a second input of a respective exclusive-or logic gate within the interlinked chain of exclusive-or logic gates and registers, wherein the interlinked chain of exclusive-or logic gates and registers includes an originating exclusive-or logic gate having its first input connected to an output of an originating scan output chain rather than to a preceding register, the interlinked chain of exclusive-or logic gates and registers including a terminating exclusive-or logic gate having an output defined to provide scan signature data, the scan signature data representing an encrypted version of scan test data output by each scan output chain.