Patent ID: 8594262

Claim:
An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit, comprising: a number of N−1 comparators for comparing an input data stream to N−1 configurable thresholds, wherein the input data stream is N-PAM modulated and the N−1 configurable thresholds are N−1 different voltage levels; a number of N−1 of edge detectors respectively connected to the N−1 comparators for detecting transitions from one logic value to another logic value, wherein N is a discrete number greater than two; a determination unit for determining if a detected transition is any one of a major transition and a minor transition, wherein a major transition is a logic value change in a most significant bit (MSB) and a least significant bit (LSB) remains at a low-logic value, and a minor transition is a logic value change in a LSB or a logic value change in the MSB and the LSB remains at a high-logic value, wherein the MSB and LSB are two bits out of 2 bits in the input data stream; and asserting a transition signal if only a major transition or a minor transition has occurred, wherein the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream by phase aligning to the transitions in the input data stream.