Patent ID: 8648424

Claim:
A semiconductor device comprising: a substrate having a channel region, and a pair of recesses therein on both sides of the channel region; a gate insulation layer on the channel region; a gate electrode on the gate insulation layer; and a source region and a drain region on surfaces delimiting bottoms of the recesses, respectively, at least one of the source and drain regions including: a lower main layer of material comprising Ge and having a bottommost point disposed at a level in the device higher than that of the bottoms of the recesses and lower than that of the bottom surface of the gate insulation layer, and a top surface no portion of which is disposed above the level of the bottom surface of the gate insulation layer, and an upper main layer contacting the lower main layer, and having a topmost point disposed at a level in the device higher than that of the bottom surface of the gate insulation layer, and wherein the Ge content in terms of atomic % of the lower main layer is greater than that of the upper main layer; and a buffer layer disposed in the recesses and interposed entirely between the lower main layer and the substrate, and wherein none of the lower main layer contacts the substrate, and the Ge content of the lower main layer is greater than that of the buffer layer.