Patent ID: 7908527

Claim:
A semiconductor integrated circuit comprising: a memory macro which includes a main memory cell array having a plurality of memory cells, a redundancy memory cell array having a plurality of redundancy cells and a redundancy repair mechanism; a repair information analyzing circuit having a nonvolatile memory element which stores memory identification information used to identify the memory macro; and a repair information transferring circuit which transfers unit repair information configured by at least the memory identification information and repair information to the repair information analyzing circuit, the repair information analyzing circuit fetching the repair information of the transferred unit repair information therein, outputting the repair information to the memory macro having the redundancy repair mechanism and subjecting the memory macro to a redundancy repair process by means of the redundancy repair mechanism of the memory macro in a case where the memory identification information of the transferred unit repair information coincides with the memory identification information stored in the nonvolatile memory element, wherein the repair information analyzing circuit includes a first register which stores the memory identification information, a second register which stores the repair information, and a state machine having a rest state, a memory information fetching state, and a repair information fetching state, the unit repair information further contains mark information used as a mark required for the state machine to start state transition, and the state machine is set in the rest state before the unit repair information is input, transited to the memory information fetching state when mark information of the unit repair information transferred is set to a preset value, and transited to the repair information fetching state in which the unit repair information transferred is fetched during a preset clock period.