Patent ID: 7176539

Claim:
A semiconductor device with substrate-triggered electrostatic discharge (ESD) protection, comprising: a guard ring formed in a substrate for surrounding a region having four sides; a plurality of contacting pads formed on the guard ring along a first direction and arranged as two lines oppositely positioned at two of the four sides of the guard ring, none of the contacting pads is positioned at the other two sides of the guard ring, and the guard ring is connected to a first node via die contacting pads; a first metal-oxide-semiconductor (MOS) transistor array formed in the region and having at least one first finger-type gate extending along the first direction; a second MOS transistor array formed in the region and having at least one second finger-type gate extending along the first direction; a substrate-triggered portion formed in the region along the first direction and positioned between the first MOS transistor array and the second MOS transistor array; two rows of first N-wells formed in the region and connected to drains of the MOS transistors, the first N-wells being extending merely along a second direction perpendicular to the first direction; and two columns of second N-wells formed in the region and connected to the first node, the second N-wells being extending along the first direction, wherein the two rows of first N-wells and the two columns of second N-wells together encompass the first and second MOS transistor arrays.