Patent ID: 7396720

Claim:
A method for fabricating a memory cell, the method comprising: forming a tunnel dielectric over a substrate; forming a single layer floating gate over the tunnel dielectric; performing shallow trench isolation to form isolation trenches in the substrate that extend through the tunnel dielectric and floating gate, the isolation trenches comprising dielectric material each having a lower portion and an upper portion wherein the upper portion extends above the substrate and into the floating gate such that the floating gate extends along each upper portion; forming a trough in the floating gate to create a concave shape on top of the floating gate, wherein the trough has first and second sidewalls such that the first and second sidewalls are substantially aligned with edges of the tunnel dielectric; narrowing the upper portions of the isolation material such that uppermost edges of the upper portions are narrower than edges of the lower portions of the isolation material in the tunnel dielectric and substrate; forming an intergate dielectric over the floating gate; and forming a control gate over the intergate dielectric wherein the control gate is composed of a polysilicon/silicide/metal structure.