Patent ID: 8310895

Claim:
A semiconductor memory device comprising: a memory cell array that is divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, and each of the subarrays having a sense amplifier unit; a first pad column that is formed outside the memory cell array, the first pad column comprising a plurality of first pads that are arranged in a first direction being elongated to run substantially parallel to a word line; a second pad column that is formed in a middle section of the memory cell array, the second pad column comprising a plurality of second pads that are arranged to be substantially parallel to the first direction, a circuit that is arranged in the middle section or at the outside of the memory cell array; and a line that is formed in a second direction substantially perpendicular to the first direction, the line being directly connected to the circuit, wherein the sense amplifier unit includes a plurality of sense amplifier circuits which are arranged continuously in the first direction.