Patent ID: 7319606

Claim:
A memory comprising: a first memory cell array having a plurality of first memory cells; a second memory cell array having a plurality of second memory cells different in type from said first memory cells; a selection control circuit provided separately from said first memory cell array and said second memory cell array for controlling selection of either said first memory cell array or said second memory cell array, wherein the selection control circuit selects all of only one memory cell array at a time and simultaneously prevents access to the non-selected memory cell array; a first bit line connected to said first memory cells of said first memory cell array, and a second bit line connected to said second memory cells of said second memory cell array, wherein the first bit line and the second bit line are arranged in a same column, and said selection control circuit directly controls selection of at least said first bit line between said first bit line and said second bit line in response to a single activation selection signal.