Patent ID: 7903684

Claim:
A memory device couplable to a plurality of accessing devices, the memory device comprising: a plurality of memory banks for storing data; a plurality of bank caches, each of the plurality of bank caches coupled to one of the plurality of memory banks and configured to hold symbols for writing to or reading from the memory bank; a plurality of ports for accessing the plurality of memory banks, each of the plurality of ports receiving symbols from an accessing device and transmitting symbols to the accessing device, the symbols being comprised of a plurality of bits and the plurality of bits being received and transmitted serially by each port; and a switching network for selectively routing symbols between the plurality of ports and the plurality of bank caches via paths between the plurality of ports and the plurality of bank caches, wherein the bits of the symbols are routed by the switching network in parallel; wherein the switching network includes a plurality of switches coupled with interconnecting communication links to establish the paths between the plurality of ports and the plurality of bank caches, and wherein upon the switching network receiving a packet to be routed to a bank cache the switching network is to determine whether a previous packet of the same transaction has been transmitted by the switching network, and, if so, the switching network is to identify the same path for the packet as the previous packet.