Patent ID: 7378860

Claim:
A multi-sided wafer test head architecture comprising: a front panel for electrically connecting to a first wafer under test and a back panel for electrically connecting to a second wafer under test; a first backplane being substantially perpendicular to said front panel and said back panel, said first backplane being spaced from and substantially parallel with a first side panel; a second backplane being substantially perpendicular to said front panel and said back panel, said second backplane being substantially parallel to and spaced from a second side panel; a first plurality of PCBs electrically connected to said first backplane, said first plurality of PCBs each having a first interface end proximate to said front panel in order to minimize signal delay between said first plurality of PCBs and said first wafer under test and a second interface end proximate to said back panel in order to minimize signal delay between said first plurality of PCBs and said second wafer under test; and a second plurality of PCBs electrically connected to said second backplane, said second plurality of PCBs being similar to said first plurality of PCBs in that said second plurality of PCBs also have a first interface end proximate to said front panel and a second interface end proximate to said back panel.