Patent ID: 7388798

Claim:
A semiconductor memory device including a memory cell without a capacitor, the device comprising: a memory cell array block configured to store data, the memory cell array block including first memory cells and second memory cells, each first memory cell having a floating body connected between a first bit line and a set of first word lines, each second memory cell having a floating body connected between a second bit line and a set of second word lines; and a reference memory cell array block configured to output a reference signal, the reference memory cell array block including first reference memory cells and second reference memory cells, each first reference memory cell having a floating body connected between a first reference bit line that is connected to the first bit line and a first reference word line, each second reference memory cell having a floating body connected between a second reference bit line that is connected to the second bit line and a second reference word line, wherein when the first word lines are selected, the second reference memory cells are selected, when the second word lines are selected, the first reference memory cells are selected, and the reference signal is generated from a combination of data “1” and data “0” that are stored in a first reference memory cell and second reference memory cell.