Patent ID: 8385134

Claim:
A semiconductor integrated circuit device comprising: a static memory with a normal operation state and a standby state of retaining data of a memory cell, wherein the static memory has a plurality of memory cells arranged in a matrix, the memory cells each include an inverter made up of an N-type MOS transistor and a P-type MOS transistor, a cell power supply voltage line for giving a power supply voltage to the P-type MOS transistor and a cell source voltage line for giving a source voltage to the N-type MOS transistor are provided, the static memory in the standby state is able to be set in any of a first state and a second state, and the cell power supply voltage line in both of the first state and the second state has a voltage lower than a voltage in the normal operation state, and the cell power supply voltage line and the cell source voltage line in the first state have voltages lower than voltages thereof in the second state.