Patent ID: 8866829

Claim:
A device comprising: a memory with a first memory pad to an ith memory pad and a jth memory pad to a kth (1<i<j<k) memory pad; an integrated circuit device, wherein the memory is stacked on the integrated circuit device, the integrated circuit device comprising: a first pad to an ith pad connected to the first memory pad to the ith memory pad; a jth pad to a kth pad connected to the jth memory pad to the kth (1<i<j<k) memory pad; and at least one pad arranged between the ith pad and the jth pad, wherein the at least one pad is not connected to a memory pad of the memory and serves as a pad for inputting or outputting a signal between an external device and the integrated circuit device, and a power supply pad that is not connected to a substrate that supports the first pad to the ith pad, the jth pad to the kth pad and the at least one pad but is instead arranged on the memory between the ith memory pad and the jth memory pad, wherein the power supply pad is not connected to the first pad to the ith pad, the jth pad to the kth pad and the at least one pad.