Patent ID: 7034518

Claim:
A timing generator comprising: a variable delay circuit having a first group of delay devices and a second group of delay devices for generating delay times different from each other are connected in series; and a linearization memory which stores delay paths and delay times obtained based on a combination of the delay devices in the order of the delay times and outputs path data which specifies a delay path where the path data is configured by a first group of bits for selecting delay devices in the first group of delay devices and a second group of bits for selecting delay devices in the second group of delay devices, the timing generator outputting a delayed clock signal obtained by delaying a reference clock signal as much as a predetermined time, wherein delay device candidates more than the bit number of the second group of bits are provided in the second group of delay devices, and wherein the timing generator includes a selection unit which selects the delay devices whose number is equal to the bit number of the second group of bits from the delay device candidates in the second group of delay devices.