Patent ID: 8232604

Claim:
A transistor comprising: a silicon layer including a source region and a drain region; a gate stack disposed on the silicon layer between the source region and the drain region, the gate stack comprising a first layer comprising a first high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer consisting of one of silicon and polysilicon; a sidewall spacer disposed on sidewalls of the gate stack, the sidewall spacer comprising a second high dielectric constant material and covering the sidewalls of the second and third layers of the gate stack; and source/drain extensions in the silicon layer, each of the source/drain extensions underlying part but not all of the sidewall spacer, wherein a bottom surface of the second layer of the gate stack directly contacts a top surface of the first layer of the gate stack, a bottom surface of the third layer of the gate stack directly contacts a top surface of the second layer of the gate stack, the second high dielectric constant material has a dielectric constant greater than about 10, and a lateral extent of the first layer of the gate stack is greater than a lateral extent of the second layer of the gate stack.