Patent ID: 7569878

Claim:
An integrated circuit that comprises a memory cell array, the memory cell array comprising: a plurality of memory cells that are at least partially formed in a semiconductor substrate, each of the memory cells comprising a storage capacitor, a select transistor including a channel region and a gate electrode, wherein the gate electrode surrounds at least two sides of the channel region, each select transistor including first and second source/drain regions that are oriented such that a flow of current through each channel region includes a portion that is substantially horizontal with respect to a top surface of the semiconductor substrate; and a plurality of word lines, the word lines being connected to the gate electrodes; wherein, in a cross section of the memory cell array through each channel region, a bottom edge of the gate electrode surrounding at least two sides of the channel region is disposed at a distance from the top surface of the semiconductor substrate that is different in relation to a distance of the bottom edges of the word lines from the top surface of the semiconductor substrate.