Patent ID: 7639043

Claim:
A low-voltage differential signaling (LVDS) receiver circuit, comprising: a common terminal pair having a first common terminal and a second common terminal; a differential-input transistor pair having a gate-terminal pair for receiving a differential input voltage and one terminal pair connected to the common terminal pair, wherein the differential-input transistor pair includes first and second input transistors, the first input transistor is connected to the first common terminal and the second input transistor is connected to the second common terminal; a control transistor pair having at least one terminal pair connected to the common terminal pair, wherein the control transistor pair includes first and second control transistors, the first control transistor is connected to the first common terminal and the second control transistor is connected to the second common terminal; a current-mirror-load circuit having one terminal pair connected to the common terminal pair, wherein the terminal pair includes a reference current input terminal and a voltage output terminal, the reference current input terminal is connected to the first common terminal of the common terminal pair, and the voltage output terminal is connected to the second common terminal of the common terminal pair; a first feedback inverter having an input terminal and an output terminal, wherein the input terminal is connected to the second common terminal, and the output terminal is connected to the gate terminal of the first control transistor; and a second feedback inverter having an input terminal and an output terminal, wherein the input terminal is connected to the output terminal of the first feedback inverter, and the output terminal is connected to the gate terminal of the second control transistor; wherein the first feedback inverter and the second feedback inverter constitute a negative feedback with the control transistor pair.