Patent ID: 8748263

Claim:
A method of fabricating a semiconductor device, the method comprising: forming isolation structures in a substrate to define active regions; forming conductive structures on the substrate to cross over at least two of the active regions and the isolation structures, the conductive structures extending in a first direction; prior to formation of the conductive structures, forming trenches in the substrate to extend in a second direction intersecting the active regions; prior to formation of the conductive structures, forming buried gate patterns in respective ones of the trenches; conformally forming an interfacial layer on the substrate in contact with the conductive structures; and forming a first insulation layer on the interfacial layer, wherein the first insulation layer is formed using a flowable chemical vapor deposition (CVD) process, and wherein the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed.