Patent ID: 8232202

Claim:
A fabricating method of a package, comprising: providing a substrate with a semiconductor device and an electrode layer electrically connected to the semiconductor device; forming a cavity in a front surface of the substrate; filling the cavity with an insulator, wherein the insulator in the cavity is completely covered with the electrode layer; disposing a covering plate over the front surface of the substrate; forming a support member on the covering plate; defining a wafer scribe channel under the support member; thinning a bottom surface of the substrate to expose the insulator, wherein a bottom surface of the insulator is level with the bottom surface of the substrate after the step of thinning; forming an insulating layer covering the bottom surface of the substrate and the entire bottom surface of insulator; removing an inner portion of the insulator to form a hole surrounded by an outer portion of the insulator; filling a conductive layer within the hole and producing an electrical connection between the conductive layer and the electrode layer; and forming a solder bump under the conductive layer.