Patent ID: 7768331

Claim:
A system comprising: a master flip flop that receives and stores state information during active mode operation from a plurality of input signals; a slave flip flop that receives and stores state information during the active mode operation and a standby mode operation from the master flip flop; a standby mode control circuit having an output, the standby mode control circuit configured to control a state of the master flip flop and slave flip flop during the active mode operation and the standby mode operation based on at least two control signals, wherein the control signals include a clock input signal and a standby mode control input signal used in combination to generate, from the output, a standby mode control output signal; a first transfer gate (i) coupled to the output of the standby mode control circuit and (ii) configured to receive the standby mode control output signal, the first transfer gate configured to gate current flow to and from the master flip flop; a second transfer gate (i) coupled to the output of the standby mode control circuit and (ii) configured to receive the standby mode control output signal, the second transfer gate configured to gate current flow to and from the slave flip flop; a first inverter having (i) an input coupled to the output of the standby mode control circuit and (ii) an output coupled to each of the first transfer gate and the second transfer gate; a second inverter for inverting an output of the slave flip flop for generating an output signal of a positive-edge state-retentive master-slave flip flop; a first power supply that supplies the master flip flop during the active mode operation; and a second power supply that supplies each of the slave flip flop and the standby mode control circuit during the active mode operation and the standby mode operation.