Patent ID: 8078846

Claim:
A processor that implements a conditional move instruction, comprising: an instruction decode and dispatch unit configured to receive the conditional move instruction comprising a first, second, and third operand, the third operand being both a source and a destination, to output a first decoded instruction comprising the second and third operands from the conditional move instruction and a second decoded instruction comprising the first and second operands from the conditional move instruction, and to allocate a register in a completion buffer as a destination register to temporarily store any result of the first and second decoded instructions, wherein the first decoded instruction causes the processor to move the third operand to the completion buffer register if a first condition is satisfied, and the second decoded instruction causes the processor to move the first operand to the completion buffer register if the first condition is not satisfied, wherein the first condition is evaluated by comparing the second operand from the conditional move instruction with a predetermined value, a hardware execution unit, coupled to the instruction decode and dispatch unit, configured to execute the first decoded instruction and the second decoded instruction, and; a graduation unit configured to graduate either the first or the second decoded instruction, wherein, if the first condition is not satisfied, the second decoded instruction is graduated and the first decoded instruction is invalidated, and wherein, if the first condition is satisfied, the first decoded instruction is graduated and the second decoded instruction is invalidated.