Patent ID: 8296626

Claim:
A system that corrects bit errors in a memory device, comprising: a sensing circuit configured to measure bit levels of a set of memory cells; a reference component that compiles at least a subset of the measured bit levels into two bit level distributions and establishes a region between the two bit level distributions, the region defines suspected error bits of the two bit level distributions; and an error detection component that applies an error detection code (EDC) algorithm to the suspected error bits that is configured to identify whether multiple error bits exist among the suspected error bits, wherein the error detection component is further configured to apply a swapping algorithm configured to change a logical association of one of the suspected error bits to facilitate reducing a number of the multiple error bits, in response to the EDC identifying multiple error bits, further wherein the error detection component is configured to identify the one of the suspected error bits as an error bit in response to the number of the multiple error bits decreasing following applying the swapping algorithm.