Patent ID: 7227781

Claim:
A non-volatile semiconductor memory device comprising: a plurality of bit lines; a bit line contact provided so as to correspond to the bit lines; a first NAND string and a second NAND string both connected to a common bit line via the bit line contact; a first string selective transistor and a second string selective transistor both connected in series to the first NAND string between the first NAND string and the bit line contact; and a third string selective transistor and a fourth string selective transistor both connected in series to the second NAND string between the second NAND string and the bit line contact, wherein the first and third string selective transistors are connected to each other, whereas the second and fourth string selective transistors are connected to each other, and each of the first and fourth string selective transistors has a first gate length and each of the second and third string selective transistors has a second gate length differing from the first gate length.