Patent ID: 7668001

Claim:
A semiconductor memory device comprising a memory cell array provided with memory cells each having a variable resistance element capable of storing information when its electric resistance is changed by application of a voltage pulse, the memory cells being arranged in at least one direction of a row direction and column direction, the memory cell array being provided by connecting one end of each of the memory cells in the same row to a common word line and the other end of each of the memory cells in the same column to a common bit line, wherein at least one of a voltage amplitude and a pulse width of a voltage pulse applied to an end of at least one of a selected word line connected to a selected memory cell among the word lines and a selected bit line connected to the selected memory cell among the bit lines is adjusted based on an arranged position of the selected memory cell in the memory cell array so that an electric resistance change of the variable resistance element after programming or erasing falls within a certain range regardless of the arranged position in the memory cell array according to an effective voltage amplitude or pulse width of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased among the memory cells in the memory cell array.