Patent ID: 7859043

Claim:
A complimentary metal-oxide-silicon (CMOS) integrated circuit (IC) comprising: a substrate; and a multi-terminal non-volatile memory (NVM) cell including: a first source region and a second source region, each including a first dopant diffused into the substrate such that the first source region is electrically isolated from the second source region; a drain region including a second dopant diffused into the substrate and disposed such that the drain region is separated from the first source region by a first channel region and separated from the second source region by a second channel region; and a polycrystalline silicon (polysilicon) floating gate including a first portion that is at least partially disposed over the first channel region, a second portion that is at least partially disposed over the second channel region, and a third portion that is at least partially disposed over the drain region; wherein the floating gate, the first and second source regions and the drain region are formed such that a gate-drain capacitance between said floating gate and said drain region is substantially higher than both a first gate-source capacitance between said floating gate and said first source region, and a second gate-source capacitance between said floating gate and said second source region.