Patent ID: 8305329

Claim:
An integrated gate driver circuit configured to receive a plurality of clocks and comprising a plurality of driving units cascaded in series, each driving unit being for driving a load and comprising: a signal input terminal; an output terminal; a first switch, having a first terminal coupled to the signal input terminal, a second terminal coupled to a first node, and a control terminal configured to receive a first clock, the first switch being configured to be turned on when the first clock is at a high level; a second switch, having a first terminal configured to receive a second clock, a second terminal coupled to the output terminal, and a control terminal coupled to the first node, wherein the second clock is for charging and discharging the load through the second switch when the first node is at a high level; and a voltage stabilizing circuit coupled between the second terminal of the second switch and the output terminal, wherein the voltage stabilizing circuit comprises a third switch, a fourth switch and a fifth switch, wherein the third switch has a first terminal coupled to a second node, a second terminal coupled to receive a first biasing voltage, and a control terminal coupled to the output terminal, wherein the fourth switch has a first terminal coupled to receive a second biasing voltage, a second terminal coupled to the second node, and a control terminal coupled to the first terminal of the fourth switch, wherein the fifth switch has a first terminal coupled to the output terminal, a second terminal coupled to receive the first biasing voltage, and a control terminal coupled to the second node, wherein the first biasing voltage is lower than the second biasing voltage, and wherein the output terminal of each driving unit is coupled to the signal input terminal of the immediately succeeding driving unit.