Patent ID: 7310274

Claim:
A semiconductor device comprising: a first memory block including a plurality of first memory cells, a plurality of first bit line pairs connected to the first memory cells, and a plurality of first word lines connected to the first memory cells, the first memory block having a first address space; a second memory block including a plurality of second memory cells, a plurality of second bit line pairs connected to the second memory cells, and a plurality of second word lines connected to the second memory cells, the second memory block having a second address space which is smaller than the first address space; a plurality of first dummy transistors connected in series between one bit line of each of the second bit line pairs and a ground potential; a plurality of second dummy transistors connected in series between another bit line of each of the second bit line pairs and the ground potential; a first dummy word line connected to a gate electrode of each of the first dummy transistors; a second dummy word line connected to a gate electrode of each of the second dummy transistors; and a test circuit supplies a test address and a test control signal to the first memory block and the second memory block, and tests the first memory block and the second memory block simultaneously, the test address including a first test address to select the first bit line pairs and the second bit line pairs and a second test address to select the first word lines and the second word lines, wherein the second memory block includes: a storage circuit which stores an address corresponding to the second address space; and a control circuit which activates one of the first dummy word line and the second dummy word line when the second test address falls outside the second address space.