Patent ID: 8426263

Claim:
A method of making a MOSFET in a transistor region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising: forming a first dielectric layer on the substrate in the transistor region and the NVM region; forming a first conductive layer on the first dielectric layer; forming a second dielectric layer on the first conductive layer; forming a second conductive layer over the second dielectric layer; performing a patterned etch to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer in the transistor region; forming a first mask over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the non-volatile memory cell; performing a patterned etch through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the gate stack of the MOSFET in the transistor region and the second pattern of the gate stack in the NVM region; and implanting using the gate stack in the NVM region as a mask to provide source/drain regions adjacent to the gate stack in the NVM region and using a remaining portion of the second conductive layer and the first conductive layer of the gate stack in the MOSFET region to provide source/drain regions in the MOSFET region adjacent to the first conductive layer of the gate stack of the MOSFET.