Patent ID: 7867839

Claim:
A method of forming a p-type field effect transistor, said method comprising: providing a substrate having a top surface; forming a silicon germanium layer on said top surface of said substrate; forming a gate stack on said silicon germanium layer, said gate stack comprising a high-k gate dielectric layer in contact with said silicon germanium layer above a designated channel region; one of before said forming of said gate stack and after said forming of said gate stack, performing an implant process using a dopant material having negatively charged ions; and performing additional processing to complete said field effect transistor, said performing of said additional processing comprising performing at least one thermal process so as to cause said dopant material to diffuse into said gate dielectric layer leaving a predetermined concentration of said dopant material at an interface between said gate dielectric layer and said silicon germanium layer in order to selectively adjust a threshold voltage of said field effect transistor to between −0.3V and −0.45V, said performing of said implant process comprising, before said forming of said gate dielectric layer: forming a protective layer on said substrate; implanting said dopant material through said protective layer into said silicon germanium layer without damaging said silicon germanium layer; and removing said protective layer, said at least one thermal process causing said dopant material to diffuse directly from said silicon germanium layer into said gate dielectric layer.