Patent ID: 7375003

Claim:
A method of manufacturing a semiconductor device comprising: forming a first mold layer on a substrate; partially etching the first mold layer to form a first mold layer pattern including an opening for a capacitor; forming a first lower electrode layer on a surface of the first mold layer pattern; forming a micelle in the opening; forming a preliminary second mold layer in the opening and on the first lower electrode layer to surround the micelle; removing the micelle to form a second mold layer having a plurality of second pores in the opening; forming a second lower electrode layer in the opening and on the first lower electrode layer to fill the second pores of the second mold layer, the second lower electrode layer having a plurality of first pores; partially removing the first lower electrode layer and the second lower electrode layer to form a first lower electrode and a second lower electrode in the opening; and forming a dielectric layer on the first lower electrode and the second lower electrode, and an upper electrode on the dielectric layer.