Patent ID: 8724001

Claim:
An analog-to-digital converter, comprising: a ramp generator for providing a substantially ramped output voltage; a plurality of comparators, each having a first input coupled to the ramp generator, a second input coupled to a respective analog input voltage to be converted to digital, and a respective comparator output; a plurality of latches coupled to the comparator outputs; a counter coupled to the latches for latching a counter count in response to the comparator outputs; a look-ahead controller coupled to the outputs of the comparators, the ramp generator, and the counter, the look-ahead controller generating a signal causing a step in the ramped output voltage and an associated change in the counter count and for detecting changes in the comparator outputs in response to the step in the ramped output voltage; and a predictor circuit coupled between each comparator output and the look-ahead controller, wherein the predictor circuit includes a capacitor coupled at a first end to the respective comparator output and at a second end to the look-ahead controller.