Patent ID: 8889494

Claim:
A method for forming a device comprising: providing a substrate prepared with a device region which includes a doped isolation well and a dielectric layer over the doped isolation well in the substrate, wherein the dielectric layer includes a second dielectric sub-layer over a first dielectric sub-layer, wherein the dielectric sub-layers comprise materials which can be removed selectively to each other, and the first dielectric sub-layer comprises silicon nitride and the second dielectric sub-layer comprises silicon oxide; forming a fin structure in the dielectric layer after the doped isolation well is provided, wherein forming the fin structure comprises forming an opening in the dielectric layer to expose a portion of the substrate, forming an amorphous semiconductor layer over the substrate to fill the opening and cover the dielectric layer, removing excess amorphous semiconductor layer over the dielectric layer and above the opening to form a planar top surface between the dielectric layer and the amorphous semiconductor layer in the opening, and performing an anneal to recrystallize the amorphous semiconductor layer in the opening; removing a portion of the dielectric layer, wherein removing the portion of the dielectric layer leaves an upper portion of the fin structure extending above a top surface of the first dielectric sub-layer; forming a gate which traverses the fin structure; and forming doped S/D regions in the fin structure adjacent to the gate.