Patent ID: 8724387

Claim:
A system for reading flash memory cells, the system comprising: multiple flash memory cells that are arranged in multiple columns and in multiple rows; a bias voltage unit; a read unit; and a controller; wherein the read unit is configured to: perform a first read operation of flash memory cells of a certain row of the multiple rows while supplying a read threshold to the flash memory cells of the certain row and while the bias voltage unit supplies a first bias voltage to flash memory cells of other rows of the multiple rows, the other rows differ from the certain row to provide first read results of the flash memory cells of the certain row; perform a second read operation of flash memory cells of the certain row while supplying the read threshold to the flash memory cells of the certain row while the bias voltage unit supplies to flash memory cells of the other rows a second bias voltage to provide second read results of the flash memory cells of the certain row, wherein the first bias voltage is higher than the second bias voltage, and provide to the controller a read outcome that is responsive to the first read results and to the second read results; wherein the read unit is configured to provide the second read results by comparing a content of the multiple non-volatile memory cells to a first threshold set to zero, and to a second threshold that has a value between a lowest positive lobe and a second lower positive lobe of a threshold voltage distribution of the non-volatile memory cells.