Patent ID: 7075123

Claim:
An input protection circuit comprising: a semiconductor substrate of a first conductivity type provided with a circuit to be protected; an input terminal formed above the semiconductor substrate for supplying an input signal to the circuit to be protected; a first well region of the first conductivity type, formed in one principal surface area of said semiconductor substrate; a second well region of a second conductivity type opposite to the first conductivity type, formed in the principal surface area of said semiconductor substrate, and forming a PN junction with said semiconductor substrate; third and fourth well regions of the second conductivity type formed in said first well region, and forming a first lateral bipolar transistor with a portion of said first well region serving as a base, the bottoms of said third and fourth well regions forming PN junctions with said first well region or with said semiconductor substrate and the third and fourth well regions not being part of a MOS transistor; and first and second impurity doped regions of the first conductivity type, formed in said second well region and forming a second lateral bipolar transistor with a portion of said second well region serving as a base, wherein said input terminal is connected to said third well region, said fourth well region and the base of said first lateral bipolar transistor are connected to said first impurity doped region, said first lateral bipolar transistor operates without a fixed base bias, and said second impurity doped region and the base of the second lateral bipolar transistor are connected to a reference potential node.