Patent ID: 7333310

Claim:
A bonding pad arrangement for an integrated circuit comprising: a bonding pad fabricated on an integrated circuit package bonding area to enable bonding; a first ESD resistor fabricated adjacent the integrated circuit package bonding area; and at least a second ESD resistor electrically coupled to the first ESD resistor and the integrated circuit package bonding area, a first diode pair having first terminals coupled between said bonding pad and a first terminal of said first ESD resistor and second terminals coupled to a circuit ground; and at least a second diode pair having first terminals coupled between said bonding pad and a first terminal of said at least second ESD resistor and second terminals coupled to the circuit ground, wherein said bonding pad is coupled to said first ESD resistor and to said at least a second ESD resistor, thereby providing at least two input ESD circuits for at least one current consuming electronic circuit from the bonding pad and wherein said bonding pad extends beyond said bonding area to further connect said first diode pair and said at least second diode pair to said bonding pad.