Patent ID: 8432754

Claim:
A synchronous memory control apparatus for enabling the reception of data read from a memory circuit in synchronism with a strobe signal from the memory circuit, the apparatus comprising: a mask circuit configured to mask the strobe signal using a mask signal; a timing measuring circuit configured to delay the strobe signal in plural units of delay and configured to latch data of each of the delayed strobe signals; and a mask generating circuit configured to generate the mask signal, wherein the timing measuring circuit latches the data of each of the delayed strobe signals at the first rise edge of the corresponding masked strobe signal, wherein the mask generating circuit controls the generation of the mask signal in accordance with a signal from a command control circuit of the memory circuit, wherein the mask generating circuit further includes a delay circuit having plural units of delay, the mask generating circuit adjusting a start timing of the mask signal in synchronism with an internal clock, and outputting a signal having a delay amount corresponding to a selected unit of delay by the delay circuit as the mask signal.