Patent ID: 8603869

Claim:
A method of fabricating a thin film transistor, comprising: forming a gate line disposed in one direction on a substrate, the gate line being straight; sequentially forming a gate insulating layer and an amorphous silicon layer on an entire surface of the substrate; applying an electric field to the gate line to crystallize the amorphous silicon layer formed on a region overlapping the gate line into a polysilicon layer; patterning a silicon layer, in which the region overlapping the gate line is crystallized into the polysilicon layer, to form a semiconductor layer crossing the gate line; and forming source and drain electrodes connected to source and drain region of the semiconductor layer, wherein the semiconductor layer has a channel region formed of the polysilicon layer at a region overlapping the gate line and the source and drain regions formed of the amorphous silicon layer at a region not overlapping the gate line.