Patent ID: 8889504

Claim:
A method of forming a semiconductor structure comprising: forming sidewalls and spacers adjacent to a gate stack structure; forming a recess in the gate stack structure; epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure; and relaxing the epitaxially-grown straining material such that a lattice constant of the straining material is an intrinsic lattice constant of Si:C that is smaller than a lattice constant of the polysilicon layer, wherein the straining material is Si:C and the gate stack structure is a PFET gate stack structure, wherein the straining material is grown above and covering a top surface of the sidewalls and the spacers, and wherein the method further comprises: forming a gate oxide layer on a wafer of the semiconductor structure; forming the polysilicon layer on the gate oxide layer; and forming a SiGe layer on the polysilicon layer.