Patent ID: 8175116

Claim:
A network processing apparatus comprising: a receive buffer, which receives from a network a plurality of packets with a data length equal to or less than a maximum transmission unit defined for the network, the receive buffer comprising a header buffer and a payload buffer that respectively stores headers and payloads separated from the respective packets; a payload concatenating unit, which concatenates the payloads of the plurality of packets on a connection-by-connection basis so as to generate a concatenated payload in the payload buffer; a header aggregating unit, which aggregates headers of the plurality of packets on a connection-by-connection basis so as to generate an aggregated header for the concatenated payload in the header buffer; and an input/output interface, which transfers to an upper layer the aggregated header from the header buffer and the concatenated payload from the payload buffer, independently of each other, and which transfers each individual header of the plurality of packets to be processed on a connection-by-connection basis, together with the aggregated header or in substitution for the aggregated header, wherein: the network processing apparatus is connected with a multiprocessor system comprising a main processor, a plurality of subprocessors each including a local memory and controlled by the main processor, and a main memory that is external to and shared by the main processor and the plurality of subprocessors, a designated subprocessor among the plurality of subprocessors designated by the main processor as a dedicated subprocessor to implement a protocol stack for performing protocol processing on data to be exchanged via a network, offloading network processing of kernel level data of the rest of the subprocessors to the designated subprocessor when the rest of the subprocessors execute an application that uses the network; and the input/output interface transfers the individual headers and the aggregated header, either alone or in combination, to the local memory of the designated subprocessor, while transferring the concatenated payload to an area in main memory to be referred to by the main processor and the rest of the subprocessors.