Patent ID: 7247928

Claim:
A semiconductor device comprising: an electrical connection support plate; an integrated circuit chip placed at a certain location on the support plate and placed at a certain distance from this support plate; a plurality of electrical connection balls connecting electrical connection regions of the support plate and corresponding electrical connection pads on the chip; an interlayer made of an insulating material disposed on a surface of the support plate and between the chip and the support plate, wherein apertures are provided in the interlayer directly above the electrical connection regions, and wherein complementary flow channels that include the apertures are provided in the interlayer to permit, when the chip is placed on the certain location on the support plate, liquid fill material in channels at a central part of the certain location to flow substantially parallel to the surface of the chip through the channels and over the support plate to fill empty space between the chip and the surface of the support plate, wherein the complementary flow channels in the interlayer include at least one peripheral flow channel that passes directly above a plurality of the electrical connection regions and connects to a plurality of apertures respectively directly above the plurality of the electrical connection regions, and radial flow channels that extend outwardly from a central part of the certain location and are connected to the at least one peripheral flow channel; and a fill material at least partly filling the space separating the chip from the support plate.