Patent ID: 7154304

Claim:
A phase frequency detector (PFD) system, comprising: a first circuit having a first output, said first circuit being adapted to receive a first clock signal and a first voltage and to apply said first voltage to said first output in response to a transition in said first clock signal; a second circuit having a second output, said second circuit being adapted to receive a second clock signal and a second voltage and to apply said second voltage to said second output in response to a transition in said second clock signal; a third circuit adapted to: determine whether said first clock signal was received by said first circuit and whether said second clock signal was received by said second circuit; reset said second circuit if said first clock signal was received by said first circuit and said second clock signal was received by said second circuit, said second circuit being adapted to remove said second voltage from said second output in response to being reset; and control whether said second output is provided to an output of said PFD, said third circuit being adapted to prevent said second voltage from being applied to said output of said PFD if said first clock signal was not received by said first circuit and to allow said second voltage to be applied to said output of said PFD if said first clock signal is subsequently received by said first circuit.