Patent ID: 7078774

Claim:
A semiconductor memory device comprising: an N-well and a P-well formed in a semiconductor substrate, and isolated from each other with a plurality of isolation regions each having a trench structure; a first CMOS inverter circuit including a first P-channel MOS transistor, which has a gate electrode, a source region, a drain region and a channel region, and is formed on the N-well, and a first N-channel MOS transistor, which has a gate electrode connected common to the gate electrode of the first P-channel MOS transistor, a source region, a drain region connected common to the drain region of the first P-channel MOS transistor and a channel region, and is formed on the P-well; a second CMOS inverter circuit including a second P-channel MOS transistor, which has a gate electrode, a source region, a drain region and a channel region, and is formed on the N-well, and a second N-channel MOS transistor, which has a gate electrode connected common to the gate electrode of the second P-channel MOS transistor, a source region, a drain region connected common to the drain region of the second P-channel MOS transistor and a channel region, and is formed on the P-well, the second CMOS inverter circuit forming a static memory cell together with the first CMOS inverter circuit; a first capacitor connected between a gate electrode common connection node of the first P-channel and N-channel MOS transistors and one of the N-well and the P-well; and a second capacitor connected between a gate electrode common connection node of the second P-channel and N-channel MOS transistors and one of the N-well and the P-well.