Patent ID: 6891384

Claim:
An interface structure for routing test signals between various packaged integrated circuits and a device tester having a docking area including a plurality of test probes, comprising: a first portion adapted to align with and mount on the docking area of the device tester, the first portion having an outer peripheral boundary that fits within the docking area of the device tester and comprising: a first socket for receiving a first packaged integrated circuit, the first socket having a plurality of pins for connecting to the first packaged integrated circuit; a plurality of contacts formed in a predetermined arrangement to contact corresponding test probes of the device tester; and a plurality of first conductive traces, each connected between a corresponding contact and a corresponding pin of the first socket; and a second portion extending laterally beyond the first portion to provide an additional testing area, the second portion having an outer peripheral boundary positioned beyond the docking area of the device tester and comprising: a second socket for receiving a second packaged integrated circuit, the second socket having a plurality of pins for connecting to the second packaged integrated circuit; and a plurality of second conductive traces, each extending into the first portion and connected between a corresponding contact and a corresponding pin of the second socket.