Patent ID: 7528478

Claim:
A semiconductor device having post-passivation interconnects, the semiconductor device comprising: an integrated circuit formed on a substrate, the integrated circuit comprising a plurality of metal lines extending therefrom; a first plurality of contact pads formed in a first connection pattern, the first plurality of contact pads being configured to provide electrical connection to an external component in packaging the integrated circuit by the formation of wire bonds or solder balls on the first plurality of contact pads; a passivation layer formed over the integrated circuit and over the first plurality of contact pads, the passivation layer being formed from a non-oxide material; a buffer layer formed over the passivation layer, the buffer layer comprising a silicon oxide layer; and a patterned post-passivation metal layer formed over the buffer layer and formed in a second connection pattern, the patterned post-passivation metal layer comprising a second plurality of contact pads, wherein portions of the patterned post-passivation metal layer are electrically coupled to the first plurality of contact pads, wherein the second connection pattern differs from the first connection pattern.