Patent ID: 8836422

Claim:
A control stage comprising: a) a first path for receiving an input signal and for generating a replica signal representing the low frequency content of such signal; b) a second path for receiving the input signal and for generating an error signal representing an error in the replica signal, the second path including: i) a delay stage for generating a delay signal being a delayed version of the input signal over a frequency range of interest, the delay amount corresponding to a time delay of the first path in generating the replica signal from the input signal, and ii) a difference block for receiving as inputs an output signal and the delay signal and for generating the error signal, wherein the delay stage applies a delay to generate the delayed version of the input signal such that the signals at the two inputs of the difference block are substantially identical over the frequency range of interest, and the low frequency content of the error signal generated by the difference block is thereby reduced such that the difference block does not provide substantially any output power over the frequency range of interest; and c) a transformer for combining the replica signal with the error signal to generate the output signal, wherein the transformer is not required to handle low frequency signals in the error signal.