Patent ID: 7061338

Claim:
A circuit, realizing an oscillator circuit with an Average Controlled (AC) Resonator Driver and producing a square wave clock signal with a precise duty-cycle of exactly 50%, comprising: an oscillation signal generating circuit in form of a basic three-point oscillator configuration, having three nodes ( 1 , 2 and 3 ) and containing a resonator element located between said first node 1 and said second node 2 ; a terminal pin for supply voltage connection; a terminal pin for ground connection, which is tied to said third node 3 ; two capacitors and one resistor as passive components, whereby said passive components are embedding said resonator element between said two capacitors, all components arranged in PI-configuration, bridging said resonator with said resistor and arranged in such a way, that capacitor one is tied with its first pole to said first node 1 and capacitor two, also with its first pole, is tied to said second node 2 ; a current source as active supply component connected to said supply voltage and arranged in such a way, that said active supply component supplying a bias-current is located between said voltage supply terminal and said second node 2 ; a first Field Effect Transistor (FET) as basic active component for inducing and sustaining resonator two-pole controlled sinusoidal oscillations; a second FET for stabilizing the voltage average of said sinusoidal oscillation signal as auxiliary active component; a resistive voltage divider made up of two resistors, delivering at its intermediate connection node a reference voltage; a differential operational amplifier with inverting and non-inverting inputs for said voltage average control, its inverting input connected to said first node 1 and its non-inverting input connected to said intermediate connection node of said resistive voltage divider whereas the amplifier output is being tied to the gate of said second FET as auxiliary active component, thus controlling said voltage average stabilization operation; and a Schmitt Trigger or comparator device with signal and reference inputs, its reference input connected to said intermediate connection node of said resistive voltage divider and its signal input connected to said first node 1 and delivering a square wave clock signal on its output, whereby said comparison of said voltage average stabilized sinus wave oscillation signal with said reference voltage also used for averaging results in an exact determination of sinus wave zero crossings, triggering a polarity change of said square wave clock signal and thus effectively stabilizing said square wave clock signal generation especially with regard to precision and stability of its 50% duty-cycle.