Patent ID: 8488032

Claim:
An image sensor comprising: a pixel array including a plurality of pixels, each of the plurality of pixels being configured to output a reset signal and a corresponding image signal; a sample-and-hold array circuit configured to receive and sample-hold the plurality of reset signals and corresponding image signals, the sample-and-hold array circuit being further configured to sequentially output each of the plurality of reset signals through a first bus and each of the corresponding image signals through a second bus; and an output stage connected to the first bus and the second bus, the output stage being configured to cancel an effect of a parasitic capacitance of the first bus and the second bus, convert each reset signal and corresponding image signal to a single ended signal, and output the converted single ended signal as a digital image signal, wherein the output stage includes, a signal converter configured to convert each reset signal and corresponding image signal to a single ended signal, and output the single ended signal, an interface connected between the sample-and-hold array circuit and the signal converter, the interface being configured to cancel the effect of a parasitic capacitance of the first bus and the second bus, and an output buffer configured to buffer the single ended signal, wherein the interface includes, a first capacitor and a second capacitor; a first operational amplifier including a first input terminal connected to the first bus and the second input terminal connected to a first power supply; a second operational amplifier including a third input terminal connected to a second bus and a fourth input terminal connected to the first power supply; and a switching circuit including a plurality of switches, the plurality of switches being configured to, connect the first capacitor between the first power supply and the first input terminal, and to connect the second capacitor between the first power supply and the third input terminal in a sampling phase, and connect the first capacitor between an output terminal of the first operational amplifier and the first input terminal and to connect the second capacitor between an output terminal of the second operational amplifier and the third input terminal in an evaluation phase.