Patent ID: 8048743

Claim:
A method for fabricating a vertical channel type nonvolatile memory device, comprising: stacking a plurality of interlayer insulating layers alternately with a plurality of conductive layers over a substrate; etching the interlayer insulating layers and the conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over a resulting structure obtained from the etching of the interlayer insulating layers and the conductive layers, wherein the resulting structure includes the channel trench; doping the undoped first channel layer with impurities through a plasma doping process to form a doped first channel layer; etching the doped first channel layer to a predetermined thickness; filling the channel trench with a second channel layer after the etching of the first doped channel layer, performing a planarization process to expose an upper surface of the uppermost interlayer insulting layer among the plurality of interlayer insulating layers: and diffusing the impurities from the doped first channel layer into the second channel layer after the performing of the planarization process.