Patent ID: 8324051

Claim:
A method of manufacturing a NOR-type flash memory device, comprising: forming a tunnel oxide layer on a substrate; forming a first conductive layer on the tunnel oxide layer; forming first mask patterns parallel to one another on the first conductive layer in a y direction of the substrate; selectively removing the first conductive layer and the tunnel oxide layer using the first mask patterns as an etch mask, thereby forming first conductive patterns and tunnel oxide patterns, and forming first trenches exposing a surface of the substrate between the first conductive patterns and the tunnel oxide patterns; forming a second mask pattern to open at least one of the first trenches; implanting impurity ions using the second mask pattern as a first ion implantation mask, and forming an impurity region extending in the y direction of the substrate; removing the second mask pattern; annealing the substrate and diffusing the impurity region, thereby forming an impurity expansion region further expanding in an x direction of the substrate; selectively removing the substrate using the first mask patterns as an etch mask, and forming second trenches corresponding to the first trenches; and forming isolation layers defining active regions in the second trenches.