Patent ID: 8638626

Claim:
A row address control circuit of a semiconductor memory device including dynamic memory cells, the row address control circuit comprising: a test mode setting unit configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; an address counter configured to generate a first address that increases gradually; and a row address generating unit configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided, wherein the row address generating unit is configured such that the row address generating unit operates in a normal mode when the test mode signal has a first logic level, and the row address generating unit operates in a test mode when the test mode signal has a second logic level, and wherein, the row address generating circuit is configured such that, when the test mode signal has the second logic level, a refresh operation based on a refresh command and an active operation based on an active command are both performed on a same bitline of the semiconductor memory device based on the externally provided second address.