Patent ID: 8004921

Claim:
A memory device which is operated in response to a command sent from a memory controller, the memory device comprising: a plurality of banks which respectively have memory cores including memory cell arrays and are selected by bank addresses; and a control circuit which controls operation of the memory cell arrays within the banks, wherein each of the plurality of banks stores two-dimensionally arrayed data on the basis of a memory mapping of which a memory logical space has a plurality of page areas that are selected by the bank addresses and row addresses, in which the plurality of page areas are arranged in rows and columns, and in which adjacent page areas are associated with different bank addresses, and during a period of horizontal access in which the two-dimensionally arrayed data is accessed horizontally, the control circuit causes the memory cores within banks selected by the bank addresses to execute normal memory operation corresponding to a normal operation command in response to the normal operation command corresponding to the horizontal access, and further causes a memory core within a refresh target bank other than the horizontal access target bank to execute refresh operation in response to a background refresh command.