Patent ID: 7876132

Claim:
A circuit comprising: a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage; a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad; and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block, wherein a voltage across at least one constituent active element of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation, wherein the failsafe operation is a mode where the supply voltage is zero, and wherein the tolerant operation is a mode where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage.