Patent ID: 7491997

Claim:
A memory device comprising: a semiconductor substrate; a gate stack structure formed to a predetermined width on the semiconductor substrate and including a first oxide layer, a dielectric nitride layer, a second oxide layer and a gate electrode layer sequentially positioned directly on the semiconductor substrate, the dielectric nitride layer formed of a uniform material; and source and drain regions that are formed in the top surface portion of the semiconductor substrate, contact the gate stack structure, and are doped with a dopant whose polarity is opposite to the polarity of a material for the semiconductor substrate, wherein the width of each of the first oxide layer and the dielectric nitride layer of the gate stack structure increase from top to bottom, such that the first oxide layer and the dielectric nitride layer each have an isosceles trapezoidal cross-sectional shape, wherein upper and lower sides are substantially parallel and the other sides are substantially of equal length and congruent base angles, and wherein the base angles of the first oxide layer are smaller than the base angles of the dielectric nitride layer in that the base angles are measured within the isosceles trapezoidal cross-sectional shape between the lower sides and the other sides.