Patent ID: 7598459

Claim:
An electronic board comprising: a substrate; an electronic circuit on the substrate, the electronic circuit having connection terminals; a stress-relaxation layer on the substrate, the stress-relaxation layer being formed of a dielectric material; a rearrangement wiring for the connection terminal, the rearrangement wiring being disposed at a top side of the stress-relaxation layer; a first wiring that extends from one of the connection terminals, the one of the connection terminals being disposed lateral to the stress-relaxation layer, a part of the first wiring being covered by the stress-relaxation layer, another part of the first wiring not being covered by the stress-relaxation layer; a first electrode disposed between the substrate and the stress-relaxation layer, the first electrode being at least a portion of the part of the first wiring; a second wiring that extends from another one of the connection terminals, the another one of the connection terminals being disposed lateral to the stress-relaxation layer, at least a part of the second wiring being disposed at the top side of the stress-relaxation layer; a second electrode disposed at the top side of the stress-relaxation layer, the second electrode being at least a portion of the part of the second wiring; and a capacitor including the first electrode, a part of the stress-relaxation layer, and the second electrode, the capacitor being formed at a region where the first wiring and the second wiring overlap in a plan view, wherein the second wiring is a part of the rearrangement wiring.