Patent ID: 7285860

Claim:
An integrated circuit power bus grid structure adapted for monitoring manufacturing defects, comprising: a first plurality of wire pairs formed on a first metal interconnect level, said first plurality of wire pairs arranged in a manner such that a first wire in each of said first plurality of wire pairs is electrically coupled to conductive structures beneath said first metal interconnect level, and a second wire in each of said first plurality of wire pairs is initially electrically isolated from said conductive structures beneath said first metal interconnect level; a first via level formed over said first metal interconnect level, said first via level having via connections arranged to electrically couple said first and said second wires in each of said plurality of wire pairs in said first metal interconnect level; a second metal interconnect level formed over said first via level, said second metal interconnect level including a second plurality of wire pairs; and said second plurality of wire pairs arranged in a manner such that a first wire in each of said second plurality of wire pairs is electrically coupled to said via connections of said first via level, and a second wire in each of said second plurality of wire pairs is initially electrically isolated from said via connections of said first via level; wherein said first wire in each of said first plurality of wire pairs and said first wire in each of said second plurality of wire pairs are configured to be biased to a known voltage so as to facilitate a charge contrast inspection between said first wire and said second wire of each of said first plurality of wire pairs, and between said first wire and said second wire of each of said second plurality of wire pairs.