Patent ID: 8659934

Claim:
A semiconductor device comprising: a first line; a second line; a memory cell; a first circuit configured to select and output any of a plurality of writing potentials to the first line; and a second circuit configured to compare a potential of the second line and a plurality of reference potentials to read data out, wherein the memory cell comprises: a first transistor including a first gate, a first source and a first drain; a second transistor including a second gate, a second source and a second drain; and a third transistor including a third gate, a third source and a third drain, wherein the second transistor includes an oxide semiconductor layer, wherein the first gate and one of the second source and the second drain are electrically connected to each other, wherein the first drain and the third source are electrically connected to each other, wherein the second line and the third drain are electrically connected to each other, and wherein the first line and the other of the second source and the second drain are electrically connected to each other.