Patent ID: 8569755

Claim:
An antifuse, comprising: a unitary monocrystalline semiconductor body including first and second semiconductor regions each having a same first conductivity type being one of n-type or p-type, and a third semiconductor region between the first and second semiconductor regions having a second conductivity type being one of n-type or p-type, the second conductivity type being opposite the first conductivity type; a gate overlying the third semiconductor region, the gate having a longest dimension extending in a direction in which the third semiconductor region extends; a conductive region including at least one of a metal, a conductive compound or an alloy of a metal contacting the first semiconductor region, the conductive region having a longest dimension extending in a direction transverse to a direction of the longest dimension of the gate; an anode spaced apart from the first semiconductor region in a direction of the longest dimension of the conductive region; and a contact electrically connected with the second semiconductor region, the antifuse being adapted such that application of a programming voltage between the anode and the contact with application of gate bias sufficient to turn field effect transistor operation of the antifuse fully on heats the first semiconductor region sufficiently to reach a temperature which drives a dopant outwardly therefrom, causing an edge of the first semiconductor region to move closer to an adjacent edge of the second semiconductor region, thereby permanently reducing electrical resistance between the first and second semiconductor regions by one or more orders of magnitude.