Patent ID: 7183177

Claim:
A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, each of said wafers having opposing first and second surfaces, said method comprising: forming an oxide layer on at least a first surface of a first one of said wafers; performing a cleavage ion implantation step on one of said pair of wafers by ion implanting a second species to define a cleavage plane across a diameter of said wafer at a predetermined depth below the top surface of said one wafer; performing a bonding enhancement implantation step by ion implantation of a first species in the first surface of at least either of said pair of wafers; bonding said pair of wafers together by placing the first surfaces of said pair of wafers onto one another so as to form an semiconductor-on-insulator structure; separating said one wafer along said cleavage plane so as to remove a portion of said one wafer between said second surface and said cleavage plane, whereby to form an exposed cleaved surface of a remaining portion of said one wafer on said semiconductor-on-insulator structure; smoothing said cleaved surface; wherein said bonding enhancement implantation step comprises plasma immersion ion implantation of said first species; and wherein the step of plasma immersion ion implantation of said first species comprises: placing either of said pair of wafers in a first process zone; introducing a first process gas containing a precursor of said first species; generating a first oscillating plasma current from said first process gas in a first closed torroidal path extending through a first reentrant conduit external of said first process zone and through said first process zone.