Patent ID: 7376011

Claim:
A memory system, comprising: a controller circuit to manage the transfer of data between the memory system and a host to which it is connected; and a non-volatile memory device, including: an array of non-volatile memory cells; a first data register connectable to receive data transferred from the controller to the memory device; a second data register connectable to receive data transferred from first data register; program circuitry connectable to the second data register and the array to write data the second data register into the array; read circuitry connectable to the second data register and the array to read data from the array into the second data register; a third data register connectable to receive data transferred from first data register; compare circuitry connectable to the second and third data registers to compare the data content thereof, wherein, subsequent to receiving from the controller a first data set and copying the first data set from the first data register to the second and third data registers, the memory device maintains the first data set in the third data register while writing the first data set from the second data register into the array, reading back the first data set as written from the array into the second data register independently a plurality of times, and individually comparing the first data set as maintained in the third register with the plurality of independent reads of the first data as held in the second register.