Patent ID: 8502586

Claim:
A method comprising: discharging a capacitor to reduce the voltage across the capacitor to zero; selecting a phase delay for a clock output signal; charging the capacitor with a first weighted current during a first phase input clock, the first weighted current weighted N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay; charging the capacitor with a second weighted current during a portion of a second phase input clock differing from the first phase input clock, the second weighted current weighted M out of M to charge the capacitor with a constant rate of change; determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay; and a predetermined period of time after the generation of the first edge in the clock output the method further includes generating a second edge of the clock output signal; and discharging the capacitor to reduce the voltage across the capacitor to zero to reset it for the next charging cycle and the next generation of the first edge in the clock output signal.