Patent ID: 7447812

Claim:
An integrated circuit chip, comprising: a multi-queue first-in first-out (FIFO) memory device having a write flag counter register file therein that is configured to support flow-through of write counter updates to at least first, second, third and fourth read ports of the write flag counter register file when an active write queue and an active read queue within said FIFO memory device are the same, said multi-queue FIFO memory device further comprising: a first write count generator having a first input electrically connected to the first read port, said first write count generator configured to generate at least one flag associated with the active write queue; and a second write count generator having second, third and fourth inputs electrically connected to the second, third and fourth read ports, respectively, said second write count generator configured to generate at least one flag associated with the active read queue; and wherein said write flag counter register file is configured to update the first read port associated with the active write queue and the second read port associated with the active read queue with an equivalent write count value during an operation to switch a write queue of said multi-queue FIFO memory device to an equivalent read queue of said multi-queue FIFO memory device; and wherein said write flag register file is further configured to sequentially update the second, third and fourth ports with respective write count values during the operation to switch the write queue of said multi-queue FIFO memory device to the equivalent read queue of said multi-queue FIFO memory device.