Patent ID: 8473880

Claim:
A method of creating a pipelined design from a high level language (HLL) specification, comprising: translating the HLL specification into an intermediate level language specification of operations of the pipelined circuit design; creating a data dependency graph of the operations; identifying from the dependency graph a sequence of operations that is bounded by two write operations and has no intervening write operations between the two write operations; identifying two or more read operations within the sequence; generating a pipelined design specification from the dependency graph and hardware components associated with the operations in the intermediate level language specification using a programmed processor; wherein the generated pipelined design specification includes a dataflow memory and an external memory, the dataflow memory including respective first-in-first-out (FIFO) buffers coupled between pairs of the hardware components; wherein at least two of the components corresponding to the two or more read operations access the external memory in parallel; wherein each component of two or more of the hardware components corresponding to the two or more read operations requires a respective synchronization token input from a respective first one of the FIFO buffers, outputs data read from the external memory to a respective second FIFO buffer of the FIFO buffers, and outputs a synchronization token to a respective third FIFO buffer of the FIFO buffers; and wherein each component of two of the hardware components corresponding to the two write operations requires a synchronization token as input from a respective fourth one of the FIFO buffers, requires data and address as input from respective fifth and sixth ones of the FIFO buffers, and outputs a synchronization token to a respective seventh one of the FIFO buffers upon completion of the operation.