Patent ID: 8843807

Claim:
A circular pipeline processing system, comprising: a plurality of processing stages, each processing stage including: at least one processing circuit configured to perform one processing iteration on a first block of data, the processing iteration including: performing a first set of soft-input-soft-output (SISO) decoding operations on the first block of data to produce an intermediate block of data; and performing a second set of SISO decoding operations on the intermediate data block to complete the one decoding iteration; a memory buffer; and wherein the plurality of processing stages is configured to operate in a circular pipeline of identical processing stages, each processing stage being configured to: output a fully processed data block in response to completing a final processing iteration, and otherwise, store a partially processed data block in the memory buffer of the processing stage; select between an unprocessed data block and a partially processed data block from the memory buffer of a preceding processing stage, based on availability of storage sufficient for an unprocessed data block and availability of a partially processed data block; and process the selected data block.