Patent ID: 8437164

Claim:
A memory device comprising: a first plurality of contact pads arranged in a pattern on a first surface of the memory device; a second plurality of contact pads arranged in a same pattern on a second surface of the memory device, wherein each contact pad of the second plurality of contact pads is electrically coupled to the corresponding contact pad using a via; wherein a first portion of both the first and the second plurality of contact pads are further coupled to data signals of the memory device for connection to a memory bus; wherein in response to the memory device being oriented in a first orientation and stacked in vertical alignment and electrical connection upon a second memory device having the same pattern of contact pads, each data signal of the memory bus is coupled to a corresponding data signal of both the memory device and the second memory device; and wherein in response to the memory device being oriented in a second orientation and stacked in vertical alignment and electrical connection upon the second memory device, a given data signal of the memory bus is coupled to the corresponding data signal of one of the memory device or the second memory device.