Patent ID: 7144800

Claim:
A method of packaging integrated circuits comprising: providing a semiconductor wafer that has an any of mother dice formed therein mounting a multiplicity of singulated daughter dice on the wafer, wherein each daughter die is mounted on an associated mother die and electrically connected to the mother die by direct soldering using a flip chip mounting approach, and wherein the daughter dice have shorter lengths and widths than the mother dice such that the mother dice have at least some contacts that are exposed relative to their respective daughter dice; dicing the semiconductor wafer having daughter dice mounted onto the mother dice on the wafer to create a multiplicity of individual chip stacks; positioning a selected plurality of the chip stacks on a lead frame panel having a multiplicity of device areas, wherein each selected chip stack is positioned in an associated device area; electrically connecting the exposed contacts on the mother dice of the selected chip stacks to contacts within their associated device area; encapsulating the device areas of the lead frame panel; and singulating the device areas after the encapsulation to create a multiplicity of individual stacked multi-chip packages.