Patent ID: 6969659

Claim:
A method for fabricating a semiconductor structure, the method comprising the steps of: (a) providing a semiconductor channel region in a semiconductor substrate; (b) forming a gate dielectric layer on top of the semiconductor channel region; (c) forming a gate stack on top of the gate dielectric layer, wherein the gate stack is electrically isolated from the semiconductor channel region by the gate dielectric layer, wherein the gate stack comprises (i) a gate region on top of the gate dielectric layer, and (ii) a gate stack mask on top of the gate region, wherein the gate stack mask comprises a gate mandrel and first and second gate spacers, and wherein the gate mandrel is sandwiched between the first and second gate spacers; (d) forming first and second source/drain regions in the substrate using the gate stack as an alignment mask; (e) removing the first and second gate spacers; (f) removing portions of the gate region beneath the removed first and second gate spacers; and (g) filling a dielectric side plate material into spaces of the removed first and second gate spacers and the removed portions of the gate region beneath the removed first and second gate spacers so as to form first and second gate dielectric side plates.