Patent ID: 7785959

Claim:
A method of manufacturing a memory cell having multiple ports for permitting read and write access to a data bit, comprising: etching a plurality of trenches into a substrate including a single-crystal semiconductor region to form a first trench and a second trench spaced apart from said first trench in a direction along a major surface of said single-crystal semiconductor region; forming first and second trench capacitors having capacitor dielectric layers extending along walls of said first and second trenches, respectively, said plurality of trench capacitors having first capacitor plates and second capacitor plates opposite said capacitor dielectric layers from said first capacitor plates, said first capacitor plates being conductively tied together through buried strap outdiffusions (“BSODs”) extending outwardly from said first and second trench capacitors into said substrate and said second capacitor plates being conductively tied together, such that said first capacitor plates are adapted to receive a same variable voltage and said second capacitor plates are adapted to receive a same fixed voltage; forming a plurality of access transistors including a first access transistor and a second access transistor, said first access transistor having a gate conductor disposed within said first trench and said second access transistor having a gate conductor disposed within said second trench, each of said access transistors having a drain region conductively connected to said first and second trench capacitors; and forming a plurality of conductors operable to carry a plurality of control signals to operate said plurality of access transistors and to carry a plurality of data bit signals each representing a state of a data bit for a purpose of at least one of reading said data bit when said data bit is stored in said memory cell or writing said data bit when said data bit is to be stored to said memory cell.