Patent ID: 8245004

Claim:
A data processing system comprising: a processor; a memory coupled to the processor and including a plurality of physical locations having corresponding real addresses and in which data are stored; a plurality of architected registers within which the processor places state and other information to communicate said information to an asynchronous memory mover in order to initiate and control an asynchronous memory move (AMM) operation; and an asynchronous memory mover coupled to the processor that: in response to receiving a set of parameters associated with a data move operation initiated by the processor utilizing a source effective address and a destination effective address, said asynchronous memory mover performs the AMM operation by which data is moved from a first memory location having a source real address corresponding to the source effective address to a second memory location having a destination real address corresponding to the destination effective address, wherein the set of parameters are received via processor placement in one or more of the plurality of architected registers to trigger the asynchronous memory mover to perform the AMM operation; and in response to a condition that causes one of a pause or a stop of the AMM operation, said asynchronous memory mover: saves a current state information of the AMM operation within the plurality of architected registers; and subsequently retrieves the state information from the plurality of architected registers in response to the asynchronous memory mover initiating a resumption of the AMM operation.