Patent ID: 7177381

Claim:
A noise-resistive, burst-mode receiving apparatus comprising: a voltage control signal generator for multiplying a frequency of a system clock signal and for generating a voltage control signal having a level that corresponds to the multiplied frequency of the system clock signal; a reset signal generator for delaying an input signal which is irregularly input in the unit of a packet, in response to the voltage control signal, for performing an exclusive OR operation on the delayed signal and the input signal, and for outputting the result of the exclusive OR operation as a reset signal; a clock signal generator for generating a current recovered clock signal in response to the reset signal, the voltage control signal and a recovered clock signal, for generating at least two clock signals, forming at least one of the at least two clock signals by delaying the recovered clock signal in accordance with the voltage control signal, for selecting between the at least two clock signals in accordance with the reset signal, and for outputting the current recovered clock signal; and an output buffer for buffering the input signal and for outputting the buffered signal as recovered data in response to the current recovered clock signal.