Patent ID: 7239571

Claim:
A semiconductor memory device comprising a memory cell array in which sub-arrays are arranged at least in a column direction, wherein the sub-array comprises memory cells each having a first electrode and a pair of second electrodes and being able to read out memory contents by a conductive state between the second electrodes depending on a potential of the first electrode, which are arranged with even numbers in a row direction and with plural numbers in the column direction in the shape of an array, the sub-array is provided such that the first electrodes of the memory cells in the same row are connected to a common word line, the second electrodes on one side are connected between the adjacent two memory cells in the row direction, the second electrodes on one side of the memory cells in the same column are connected to a common first bit line, the second electrodes on the other side of the memory cells in the same column are connected to a common second bit line, and the first bit lines and the second bit lines are alternately provided, each of the sub-arrays in the same column comprises a common first main bit line and a common second main bit line, the first bit lines of one half of the sub-arrays positioned in the same column are connected to the first main bit line through selection transistors and the second bit lines thereof are connected to the second main bit line through selection transistors, the first bit lines of the other half of the sub-arrays positioned in the same column are connected to the second main bit line through selection transistors and the second bit lines thereof are connected to the first main bit line through selection transistors.