Patent ID: 6856658

Claim:
A digital PLL (phase locked loop) circuit comprising: a sampling circuit sampling a burst data signal in response to a multi-phase clock signal to produce N (N is a positive integer larger than one) sampled data signals, said multi-phase clock signal including N clock signals, each of which has substantially the same frequency as said data signal and which have phases different by a predetermined component from one after another; a plurality of internal circuits, each of which is selected in response to a first selection signal, and outputting a set of a selected one of said N clock signals and an identified data signal from said N sampled data signals, which corresponds to said selected one of said N clock signals, in response to said selected one of said N clock signals, when said internal circuit is selected; and an output switching circuit selecting said set corresponding to said selected internal circuit from among said set from said plurality of internal circuits based on a second selection signal.