Patent ID: 8213303

Claim:
An apparatus comprising: a circuit card of a first network node, said circuit card comprising circuitry configured to: receive data from a second network node, said data representing a buffering capability of said second network node; determine a lower power consumption state buffering capability of said first network node; determine a latency time period during which said first network node can remain in said lower power consumption state without resulting in partial loss of a packet received and buffered by said second network node, wherein said latency time period is based, at least in part, on said buffering capabilities of said first and said second network nodes, and wherein said latency time period is based, at least in part, on a storage capability of one or more buffers of said second network node and an incoming packet transmission rate to said one or more buffers of said second network node; and upon elapse of said latency time period, receive a wake up signal from said second network node, said wake up signal configured to cause said first network node to transition from said lower power consumption state to a higher power consumption state in which said first network node is configured to receive packets from said second network node.