Patent ID: 8878763

Claim:
A display apparatus comprising: a display panel comprising a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines; a timing controller to generate a gate control signal, a data control signal, and a clock signal; a gate driver to sequentially apply a gate signal to the gate lines in response to the gate control signal; a first source driver to apply a first data voltage to the data lines in response to the data control signal; and a second source driver disposed at an opposite side of the display panel from the first source driver with respect to the display panel, the second source driver being configured to apply a second data voltage to the data lines at every time period, at which the gate signal is applied to the gate lines, in response to the clock signal, wherein the pixels display a gray scale in response to the first data voltage and the second data voltage, a time period of a rising edge of the clock signal is the same as a time period of a rising edge of the gate signal, and the clock signal has a high level period shorter than a high level period of the gate signal.