Patent ID: 6887758

Claim:
A semiconductor device, comprising: a semiconductor substrate; a first highly doped layer having a first conductivity type formed in the semiconductor substrate a first distance below a surface of the semiconductor substrate; a first insulating layer formed over the semiconductor substrate; a charge storage layer formed over the first insulating layer; a second insulating layer formed over the charge storage layer; a source having a second conductivity type formed in a first predetermined region of the semiconductor substrate; a drain having the second conductivity type formed in a second predetermined region of the semiconductor substrate, wherein the first highly doped layer does not extend below a depth of the source and the drain; a channel region between the source and the drain below the first insulating layer; and a second highly doped layer having the first conductivity type formed in only a drain side of the first insulating layer and extending through the drain and under the first insulating layer a second distance from an edge of the first insulating layer, wherein the second highly doped region increases a dopant gradient within the second distance; wherein the semiconductor device is a non-volatile memory cell and during an access to the non-volatile memory cell a depletion region forms in the channel region at an edge of the channel region to mask the increased dopant gradient within the second distance.