Patent ID: 8867183

Claim:
An integrated circuit comprising: first and second electrostatic discharge (ESD) protection devices to protect first and second circuits, respectively, from an ESD event, where the first circuit is configured to be biased by a first supply voltage through a first VDD circuit node and a VSS circuit node; and where the second circuit is configured to be biased by a second supply voltage though a second VDD circuit node and the VSS circuit node, where the second supply voltage has a different DC voltage level than the first supply voltage; wherein the first ESD protection device comprises: a first electrical path extending between the first VDD circuit node and the VSS circuit node and including first and second ESD detection elements arranged in series thereon; and a second electrical path extending between the first VDD circuit node and the VSS circuit node and in parallel with the first electrical path, the second electrical path including first and second inverters to pass current between the VDD circuit node and the VSS circuit node, wherein the first and second inverters have first and second inputs, respectively, coupled to respective first and second outputs of the first and second ESD detection elements, respectively; and a voltage controlled shunt network including a third electrical path in parallel with the first and second electrical paths and also including a fourth electrical path in parallel with the first, second, and third electrical paths, wherein the third electrical path is configured to shunt energy of the ESD event based on an output of the first inverter and independent of an output of the second inverter, and wherein the fourth electrical path is configured to shunt energy of the ESD event based on the output of the second inverter and independent of the output of the first inverter.