Patent ID: 7232745

Claim:
A semiconductor structure comprising a silicon-on-insulator substrate comprising an upper patterned Si-containing layer located atop a buried insulating layer, said patterned Si-containing layer having source/drain diffusions located therein; a plurality of transistors, each including a wordline gate conductor, located on a surface of said patterned Si-containing layer, wherein a bitline stud which extends to an overlaying bitline is in contact with one of said source/drain diffusions; a source line located atop said patterned Si-containing layer adjacent to selected transistors, said source line is in contact with another of said source/drain diffusions; and a capacitor plate beneath each wordline gate conductor and located within said patterned Si-containing layer and extending down through said buried insulating layer, wherein said source drain diffusions, said wordline gate conductor and said capacitor plate have edges that are aligned to each other.