Patent ID: 8241959

Claim:
A method of making microelectronic packages comprising: making a subassembly including providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a dielectric compliant layer to the top surface of said plate, said dielectric compliant layer having openings that are aligned with the openings extending through said plate, providing electrically conductive features including electrically conductive traces on said dielectric compliant layer, said traces having at least portions separated from the plate by the dielectric compliant layer, said dielectric compliant layer insulating at least some of said electrically conductive features from one another; after making said subassembly, juxtaposing said plate with a semiconductor wafer having a top surface and contacts accessible at the top surface; attaching the bottom surface of said plate with the top surface of said semiconductor wafer so that the openings extending through said plate are aligned with the contacts on said wafer; electrically interconnecting at least some of the electrically conductive features on said dielectric compliant layer and the contacts on said semiconductor wafer; and then dicing the semiconductor wafer and the attached subassembly into a plurality of microelectronic packages, each package including one or more semiconductor die being a severed portion of the semiconductor wafer and including a severed portion of the subassembly.