Patent ID: 8446303

Claim:
An analog-to-digital converter system, comprising: a pipeline including N successively-cascaded signal converters, each converting, according to a first clock signal, a respective portion of an input signal of the pipeline into digital codes, wherein: a) all but a last one of the signal converters include an amplifier for amplifying a signal received at an amplifier input node with a gain; and b) the digital codes generated by a signal converter correspond to an output signal of a preceding signal converter in the pipeline; a code aligner for receiving and aligning the digital codes from the signal converters in the pipeline into a digital output of the system; an error extractor coupled to the amplifier input node of a selected one signal converter via a first switch for extracting an error signal, wherein: a) the first switch is engaged/disengaged according to a second clock signal; and b) when the first switch is engaged, the error extractor exerts a load to the pipeline; and a load system coupled to the amplifier input node of the selected one signal converter via a second switch, wherein: a) the second switch is engaged/disengaged according to a third clock signal; and b) when the second switch is engaged, the load system provides a load substantially the same as the load of the error extractor to the pipeline.