Patent ID: 7478202

Claim:
A method executed by a first processor for maintaining cache coherency between a first local cache of the first processor and one or more other local caches, the method comprising: issuing, by said first processor, a global memory request to perform an operation in connection with a portion of global memory; processing, by said first processor, any invalidate commands to invalidate cache lines of global memory included in said first local cache; determining whether the global memory request is a request to write to said portion of global memory; processing the global memory request by the first processor, wherein if said global memory request is a request to write to said portion of global memory, the first processor performing processing as an atomic operation, said processing performed as an atomic operation including: updating the portion of global memory in accordance with the request, said updating of global memory being performed prior to invalidating any copy of said portion of global memory in said one or more other local caches by one or more other processors; receiving one or more acknowledgements from said one or more other processors that said one or more other processors will invalidate local copies of said portion of global memory; and updating the first local cache to include a copy of said portion of said global memory in accordance with the request to write to said portion.