Patent ID: 7835463

Claim:
A digital radio frequency memory comprising: (a) an analog-to-digital converter for receiving and converting a first IF signal having a frequency of approximately 70 MHz to a 14-bit digital signal, wherein said first IF signal is converted to said 14-bit digital signal at a sampling rate of approximately 100 MHz which down-converts said 14-bit digital signal to a frequency of approximately 30 MHz; (b) a wideband receive signal processor for receiving said 14-bit digital signal from said analog-to-digital converter, separating said 14-bit digital signal into I and Q component signals having a frequency of zero hertz and phase shifting said I and Q component signals by ninety degrees with respect to each other; (c) said wideband receive signal processor including a decimate by two circuit for dividing said sampling rate of approximately 100 MHz by a factor of two which produces a sample frequency of approximately 50 MHz; (d) a first-in-first-out (FIFO) memory for providing a signal time delay by storing said I and Q component signals at said sample frequency of approximately 50 MHz; (e) a digital upconverter for receiving said I and Q component signals from said FIFO memory after said signal time delay occurs and up-converting said sample frequency of approximately 50 MHz to a sample frequency of approximately 200 MHz; (f) said digital upconverter up-converting said I and Q component signals from said frequency of zero hertz to said frequency of approximately 70 MHz and vectorially adding said I and Q component signals to regenerate said 14-bit digital signal which is delayed by said signal time delay provided by said FIFO memory; and (g) said digital upconverter including a digital-to-analog converter for converting said 14-bit digital signal to a second IF signal which is equivalent to said first IF signal and is delayed by said signal time delay provided by said FIFO memory.