Patent ID: 8494099

Claim:
A machine-implemented method for signal processing, comprising: (a) a processor receiving an electrical input signal via one or more terminals; (b) the processor processing the electrical input signal to generate a matrix M; (c) the processor inverting the matrix M to generate an inverted matrix M −1 by: (c1) decomposing the matrix M into a plurality of first sub-matrices, (c2) generating, based on the first sub-matrices and without any division operations, numerators for a plurality of second sub-matrices of the inverted matrix M −1 , (c3) generating, based on the first sub-matrices and without any division operations, denominators for the second sub-matrices, and (c4) generating the second sub-matrices based on the numerators and denominators; and (d) the processor processing the inverted matrix M −1 to generate an electrical output signal, wherein processing the inverted matrix M −1 to generate an electrical output signal comprises equalizing one or more signals based on the inverted matrix M −1 .