Patent ID: 7193924

Claim:
A memory, comprising: a row decoder; column logic; and a memory array coupled to the row decoder and the column logic, comprising: a plurality of memory cells arranged in rows and columns; a plurality of word lines, coupled to the row decoder, running in a row direction; a plurality of read bit lines, coupled to the column logic, running in a column direction that carry data that has been read from the plurality of memory cells; a plurality of write bit lines, coupled to the column logic, running in the column direction, wherein the write bit lines carry data for writing into the plurality of memory cells; a plurality of column selection lines, coupled to the column logic, running in the column direction; a plurality of logic circuits; wherein: each memory cell of the plurality of memory cells is coupled to a predetermined one of the plurality of logic circuits, a predetermined one of the read bit lines of the plurality of read bit lines, and a first predetermined one of the write bit lines of the plurality of write bit lines; and each logic circuit comprises; a transmission gate having a signal input coupled to a predetermined one of the plurality of word lines, a signal output coupled to a predetermined one of the memory cells, and a first control input coupled to a predetermined one of the plurality of column select lines; an inverter having an input coupled to the column select line and an output coupled to a second control input of the transmission gate; and a first transistor having a control input coupled to the column select line, a first current electrode coupled to a ground terminal, and a second current electrode coupled to the output of the transmission gate.