Patent ID: 7158413

Claim:
A semiconductor memory device comprising: memory cells each of which includes a first MOS transistor having a charge accumulation layer and a control gate and into which data is written by exchanging electrons with the charge accumulation layer by FN tunneling, the first MOS transistor having one end of a current path and other end of the current path; write bit lines to each of which the one ends of the current paths of the first MOS transistors are connected electrically; read bit lines to each of which the one ends of the current paths of the first MOS transistors are connected electrically; latch circuits which are provided for the write bit lines in a one-to-one correspondence and which hold write data for the memory cells; a n-channel MOS transistor which transfer “1” data to the latch circuit in a data latch operation; and voltage setting circuits which apply a potential corresponding to “0” data to the write bit lines in a read operation, in the data latch operation, the latch circuits corresponding to the write bit line connected to the memory cell into which “0” data is to be written latching the potential applied to the write bit lines in the read operation.