Patent ID: 7971043

Claim:
An electronic system comprising: a pipeline operating in a first mode with a first number of operation stages being coupled in series, operating in a second mode with a second number of operation stages being coupled in series, and operating in a third mode with a third number of operation stages being coupled in series, wherein in the first mode all operation stages are primitive stages, and in a second mode and in a third mode each operation stage is a primitive stage or is fused from two or more adjacent primitive stages in the first mode; a main clock signal applied to each operation stage; and a pipeline control unit for controlling the pipeline and generating output data, wherein for each operation stage with two or more primitive stages, the main clock signal clocks the first primitive stage, and the pipeline control unit generates a set of sequentially increasing phase-delayed versions of the main clock signal having the same period as the main clock signal to clock each subsequent primitive stage respectively, wherein each operation stage outputs data to a next operation stage at each cycle of the main clock signal.