Patent ID: 8325490

Claim:
A method of making an integrated circuit, comprising: providing a core comprising a dielectric layer with a pattern of large-diameter conductive vias extending therethrough from a top side to a bottom side of the core, wherein the large-diameter conductive vias include signal-bearing vias and voltage plane vias; laminating a first top insulating layer on the top side of the core; depositing a top transmission line reference plane metal layer on a top side of the first top insulating layer; laminating a second top insulating layer on a top side of the top transmission line reference plane metal layer; and forming a top signal layer on a top side of the second top insulating layer having top conductive paths routed above the large-diameter conductive vias, and wherein the depositing the top transmission line reference plane metal layer defines voids above the signal-bearing vias so that capacitive coupling between the tops of the signal-bearing vias and the top transmission line reference plane metal layer is substantially reduced, and wherein at least some of the top conductive paths are routed above the signal-bearing vias, and wherein the top transmission line reference plane metal layer includes conductive stripes extending across the voids in the plane of the reference plane metal layer underneath the at least some top conductive paths and above the corresponding signal-bearing vias, to isolate the at least some conductive paths from the signal-bearing vias.