Patent ID: 8402326

Claim:
An integrated circuit device comprising: a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns, wherein the columns comprise a plurality of normal columns and at least one redundant column; multiplexer circuitry coupled to the memory cell array, wherein the multiplexer circuitry comprises a plurality of data multiplexers, wherein each data multiplexer comprises a plurality of inputs and an associated output to responsively output data from one of the plurality of inputs, wherein the plurality of inputs comprise: (i) a first input to receive write data; and (ii) a second input to receive read data; and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data; and (ii) a read data syndrome vector using the read data, wherein at least one of the write data syndrome vector and the read data syndrome vector determine a use of the plurality of normal columns and the at least one redundant column.