Patent ID: 8466816

Claim:
A circuit for serializing a plurality of bits comprising: a clock circuit configured to receive a master clock signal and to generate a plurality of clock signals from the master clock signal, the plurality of clock signals comprising: a first clock signal having a frequency substantially below the frequency of the master clock signal, a second and third clock signals, the second clock signal out of phase with the third clock signal, wherein a rising edge and its corresponding falling edge of the second and third clock signals are inset between the rising edge of the first clock signal and the next rising edge of the first clock signal, and a plurality of rotary clock signals, each rotary clock signal out of phase with the other rotary clock signals in the plurality of rotary clock signals; and a serializer, wherein the plurality of bits is transmitted to the serializer in response to a transition of the first clock signal, the serializer comprising: a first latch configured to receive a bit from the plurality of bits in response to a first transition of the second clock signal, a second latch coupled to the output of the first latch and configured to receive the output of the first latch in response to a transition of the third clock signal, a third latch configured to receive a second bit from the plurality of bits in response to the transition of the third clock signal; a fourth latch coupled to the output of the third latch and configured to receive the output of the third latch in response to a second transition of the second clock signal; and a rotary circuit coupled to the outputs of the second and fourth latches, the rotary circuit configured to output, in response to a transition of a rotary clock signal in the plurality of rotary clock signals, the bit from the plurality of bits, and the rotary circuit further configured to output, in response to a transition of a second rotary clock signal in the plurality of rotary clock signals, the second bit from the plurality of bits, wherein the second rotary clock signal generates a rising edge at least one period of the master clock signal after the rotary clock signal generates a rising edge.