Patent ID: 8732532

Claim:
A memory controller that is connected with a memory module having a plurality of unit memory regions and controls access to the memory module, the memory controller comprising: an error detector configured to perform an error detection on data read from the memory module; a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, cause the error detector to detect an error in the read data and perform a failure inspection; and a determining unit configured to determine existence of a memory failure and a transmission path failure based on a state of the error detected by comparing error information of a memory region including inspection information of the plurality of memory regions with failure inspection data, wherein the state of the error, determined by the determining unit, indicates one of the memory failure and the transmission path failure, the memory failure being caused by a failure that occurs in the memory module, and the transmission path failure being caused by a failure of a data transmission path located outside of the memory module.