Patent ID: 8250440

Claim:
A computer implemented method for address generation checking, the method comprising: receiving a starting memory address for a data, an ending memory address for the data, a length value of the data, and an address wrap indicator value that indicates if the data wraps from an end of a memory block to a start of the memory block; generating a modulus-3 residue of the starting memory address, the ending memory address, the length value, and the address wrap indicator value; determining, by a computer, that the ending memory address is not equal to a sum of the starting memory address added to a difference of the length value to the address wrap indicator value, wherein the determining comprises determining that the modulus-3 residue of the ending memory address is not equal to a sum of the modulus-3 residue of the starting memory address added to a difference of the modulus-3 residue of the length value to the modulus-3 residue of the address wrap indicator value; transmitting an error signal that indicates that an error occurred in a generation of at least one of the starting memory address and the ending memory address, the transmitting responsive to the determining; and triggering a blocking of a checkpoint operation for a completion of a processing of the data.