Patent ID: 8078854

Claim:
A computing device that uses register rename maps to facilitate precise exception semantics, comprising: a processor that supports out-of-order execution, wherein the processor includes a plurality of register rename maps that track mappings between architectural registers and physical registers for a program executing on the processor; wherein the plurality of register rename maps include: a working rename map that maps architectural registers associated with a decoded instruction to corresponding physical registers; a retire rename map that tracks and preserves a set of physical registers that are associated with retired instructions; and a checkpoint rename map that stores a mapping between a set of architectural registers and a set of physical registers for a preceding checkpoint in the program; wherein when the program causes an exception, the processor is configured to use the checkpoint rename map to roll back program execution to the preceding checkpoint; wherein the program executes in a virtual machine that is configured to deliver the exception at a precise virtual program counter and with a precise state defined by the instruction set architecture of the virtual machine.