Patent ID: 8473797

Claim:
A clock malfunction detection circuit in a System on chip (SoC) comprising: a primary clock circuit comprising a primary clock and a GRAY code counter, the GRAY code counter configured to generate a GRAY code sequence based on a number of clock pulses generated by the primary clock; a secondary clock circuit comprising a secondary clock and a secondary clock counter, the secondary clock circuit configured to output a secondary clock pulse on each of a number of saturations of the secondary clock counter; a clock gated register circuit associated with the primary clock circuit and the secondary clock circuit and clocked by the secondary clock pulse, the clock gated register circuit configured to store a plurality of values of the GRAY code sequence, and to update the plurality of values of the GRAY code sequence on each of the number of saturations of the secondary clock counter; and an error detection circuit associated with the clock gated register circuit and configured to output a signal indicative of malfunction of the primary clock based on a comparison of the updated plurality of values of the GRAY code sequence with at least one predetermined threshold associated with the malfunction of the primary clock, wherein the primary clock is operative in a first independent clock domain and the secondary clock is operative in a second independent clock domain, and wherein the secondary clock counter comprises a binary counter.