Patent ID: 7386771

Claim:
A memory sub-system, comprising: (a) a main memory; (b) an ECC (Error Correction Code) circuit electrically coupled to the main memory; and (c) a hard fail identifier circuit electrically coupled to the ECC circuit, wherein the ECC circuit is configured to detect a first bit fail at a first bit location at a first location address of the main memory, wherein the ECC circuit is further configured to send an error flag signal to the hard fail identifier circuit to notify the hard fail identifier circuit about the first bit fail, wherein the ECC circuit is further configured to send the first location address of the first bit fail to the hard fail identifier circuit, wherein the ECC circuit is further configured to send the first bit location of the first bit fail to the hard fail identifier circuit, wherein the ECC circuit is further configured to correct data from the first location address and send the corrected data to the hard fail identifier circuit, wherein the hard fail identifier circuit is configured to, in response to the error flag signal being sent, determine and track the number of times of failure occurring at the first location address and the first bit location, wherein the hard fail identifier circuit is further configured to determine whether the number of times of failure at the first location address and the first bit location is equal to a predetermined threshold value, and wherein the hard fail identifier circuit is further configured to, in response to the hard fail identifier circuit determining that the number of times of failure is equal to the predetermined threshold value, generate a threshold reached signal to indicate that the first bit fail is a hard fail, wherein the hard fail identifier circuit comprises a failure stack electrically coupled to the ECC circuit, wherein the failure stack comprises N entries, wherein N is a positive integer, wherein each of the N entries comprises a use bit, an address field, an age field, and a bit location field, wherein the N entries comprises M unavailable entries and P available entries, M and P being non-negative integers, wherein M plus P is equal to N, and wherein each of the M unavailable entries stores a bit fail.