Patent ID: 8330232

Claim:
A multi-bit memory cell, comprising: a substrate; a tunnel layer over the substrate; a dielectric charge-trapping layer as a data storage layer over the tunnel layer; an insulating layer over the dielectric charge-trapping layer; a gate over the insulating layer having a first lateral side and a second lateral side; a source region in the substrate, a portion of the source region being under the first lateral side of the gate; a drain region in the substrate, a portion of the drain region being under the second lateral side of the gate; and a channel region in the substrate between the source region and the drain region, the channel region having one of a p-type doping and an n-type doping, the doping being configured to provide a highest doping concentration near a central portion of the channel region, wherein the dielectric charge-trapping layer has two charge-trapping regions near the source region and the drain region, respectively, and wherein the highest doping concentration is located between the adjacent two charge-trapping regions.