Patent ID: 7576563

Claim:
A programmable logic device comprising: an array of logic blocks; a primary clock network adapted to route primary clock signals to logic blocks throughout the device; and a secondary clock network adapted to route secondary clock signals to logic blocks within secondary clock regions of the device, the secondary clock network comprising: a vertical spline running through the logic block array and adapted to receive a secondary clock signal; a plurality of horizontal splines running through the logic block array and adapted to receive the secondary clock signal from the vertical spline; a plurality of vertical spline taps running through the logic block array and adapted to receive the secondary clock signal from a horizontal spline; and a horizontal secondary branch connected to a vertical spline tap and connected directly to a plurality of logic blocks in adjacent columns of the logic block array, the horizontal secondary branch adapted to route the secondary clock signal from the vertical spline tap to the directly connected logic blocks, wherein the logic blocks directly connected to the horizontal secondary branch form a secondary clock region with minimum timing skew within the region.