Patent ID: 7403054

Claim:
A sub-picosecond multi-phase clock generator comprising: an N-stage delay locked loop (DLL) having N serially connected variable delay stages and including phase detector feedback control device for controlling a delay of said N-stages to lock a clock input signal therein, said DLL initially receiving a clock signal (CLK/M) input equal to said clock input signal (CLK) divided by M, where M is a prime number greater than 1 and N=X·M and X is a non-integer value>1, and locking said CLK/M clock signal input; a counter device receiving said CLK clock input signal and counting a predetermined time corresponding to a time for locking said CLK/M clock signal input in said DLL and asserting a switch signal at said predetermined time; a synchronization device responsive to said asserted switch signal for switching said DLL input from said CLK/M clock signal input to said CLK clock signal input signal, and during input of a first cycle of said CLK clock input signal signal to said DLL generating a signal for temporarily halting said phase detector feedback control device from performing said DLL locking operation while enabling injection of M clock cycles in said DLL during said temporary halting, said synchronization device further enabling said phase detector feedback control device to resume said DLL locking operation at a time corresponding to input of said Mth additional CLK signal additional cycle of said CLK clock input signal such that said N-stage delay locked loop locks M number of CLK clock signals to form multiphase clock outputs having Tpd/M clock spacing, where Tpd is a propagation delay of each DLL stage.