Patent ID: 7656210

Claim:
A semiconductor integrated circuit operating on multiple supply potentials including a first supply potential and a second supply potential that is higher than the first supply potential, comprising: a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor whose gate and drain receive the second supply potential and that outputs a third supply potential from a source thereof, the third supply potential being lower than the second supply potential; a judging circuit operating on the third supply potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level; a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit, the judging circuit including: a first inverter that receives and inverts the first supply potential; and multiple P-channel MOS transistors whose source-drain paths are series-connected between the second supply potential and an output node of the first inverter, and the judging circuit includes a second inverter that inverts a signal outputted from the first inverter, a signal outputted from the second inverter is fed to a gate of a first P-channel MOS transistor out of the multiple P-channel MOS transistors, and a gate of another P-channel MOS transistor out of the multiple P-channel MOS transistors is connected to the first supply potential.