Patent ID: 8514636

Claim:
A semiconductor storage device, comprising: a memory cell array including a plurality of memory cells in rows and columns; an even-numbered bit line connected to the memory cells connected to an even-numbered column; an odd-numbered bit line connected to the memory cells connected to an odd-numbered column adjacent to the even-numbered column; and a plurality of sense amplifiers each of which is selectively connected to the odd-numbered bit line or the even-numbered bit line, wherein each of the sense amplifiers includes: a latch circuit including a first node and a second node, which holds the data supplied to the first node; a first transistor of which gate is connected to wiring selectively connected to the even-numbered bit line or the odd-numbered bit line, one end of a current pathway of the first transistor is connected to the first node of the latch circuit, the first transistor supplies read data to the latch circuit on the basis of a potential of the wiring when reading the data; a second transistor of which current pathway is connected between the first node of the latch circuit and the wiring, which transfers the data held by the latch circuit to the wiring when performing arithmetic of the data; and a third transistor of which current pathway is connected between the second node of the latch circuit and the wiring, which transfers the data held by the latch circuit to the wiring when writing the data.