Patent ID: 7259702

Claim:
A memory device equipped with a memory array that includes a plurality of memory elements respectively identified by unique address values, wherein the memory device reads data out of a memory element identified by an address value when the address value is input from at least one of external terminals and outputs the readout data to at least one of the external terminals, comprising: a serial-parallel conversion section for converting serial data into parallel data; a parallel-serial conversion section for converting parallel data into serial data; a parallel-parallel conversion section for changing a bit width of the parallel data; and a multiplexer for connecting at least some of the external terminals to one of the serial-parallel conversion section, the parallel-serial conversion section, and the parallel-parallel conversion section, wherein the multiplexer, when access using a serial interface is performed, connects one of the external terminals to the serial-parallel conversion section and connects another of the external terminals to the parallel-serial conversion section, and the multiplexer, when access using a parallel interface is performed, connects a plurality of the external terminals to the parallel-parallel conversion section.