Patent ID: 7986547

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of first and second word lines, a plurality of first through fourth bit lines, and a plurality of memory cells arranged in array, wherein said memory cell includes a flip-flop circuit containing a first inverter composed of a first NMOS transistor and a first PMOS transistor and a second inverter composed of a second NMOS transistor and a second PMOS transistor, said first inverter having an output terminal connected to the input terminal of said second inverter, said first inverter having an input terminal connected to the output terminal of said second inverter, a third NMOS transistor connected between said output terminal of said first inverter and said first bit line and having a gate connected to said first word line, a fourth NMOS transistor connected between said output terminal of said second inverter and said second bit line and having a gate connected to said first word line, a fifth NMOS transistor connected between said second word line and said third bit line and having a gate connected to said output terminal of said second inverter, and a sixth NMOS transistor connected between said second word line and said fourth bit line and having a gate connected to said output terminal of said first inverter.