Patent ID: 8055473

Claim:
A performance monitor hardware unit that is included in a processor, the performance monitor hardware unit monitoring the performance of the processor, the performance monitor hardware unit comprising: a plurality of hardware counters that count only a selected subset of a plurality of performance event signals received by the performance monitor hardware unit; a hardware event register that intercepts the plurality of performance event signals and outputs the selected subset of the plurality of performance signals to the plurality of hardware counters; a single unit in the hardware event register that stores current values of the plurality of performance event signals received by the processor, the single unit being a full set of available performance event signals that indicates the current full event state of the processor at a particular time; control logic that is coupled to the hardware event register utilizing a freeze state line; control logic that receives a notification of a freeze condition; control logic that causes the hardware event register to enter a freeze state in response to the control logic receiving the notification of the freeze condition; control logic that receives the notification that the freeze condition no longer exists; and control logic that causes the hardware event register to enter a normal, non-freeze state in response to the control logic receiving the notification that the freeze condition no longer exists.