Patent ID: 7816956

Claim:
A power-on reset circuit, comprising: an input control unit configured to generate a default input signal in response to a power-on reset signal and a clock; a counting unit configured to perform a counting operation in response to the default input signal to generate a count offset signal; a power-on reset unit configured to perform a counting operation in response to the count offset signal to generate the power-on reset signal, and a switching, unit configured to receive a clock and a ground voltage, to output the clock as a count control clock before the power-on reset signal is enabled, and to output the ground voltage as the count control clock when the power-on reset signal is enabled, wherein the default input signal includes a first default input signal and a second default input signal, and when the power-on reset signal is disabled, the input control unit is configured to generate the first default input signal and the second default input signal toggling between opposite logic levels in response to the count control clock, and wherein the input control unit includes: a 2-bit counter configured to generate a 2-bit signal in response to the power-on reset signal and the count control clock, and a signal generator configured to receive the output signal of the 2-bit counter and to generate the first default input signal and the second default input signal.