Patent ID: 7797618

Claim:
An integrated circuit capable of conducting a decoding operation on a received sequence of k symbols, the received sequence presumed to include an encoded message sequence of n symbols encoded according to a convolutional code of rate n/k, having a constraint K, and having 2 M code states, where M is equal to K−1, the received sequence received according to a symbol rate associated with the encoded message sequence, the integrated circuit comprising: 2 M-1 parallel connected Add Compare Select (ACS) elements associated with the 2 M code states configured to: add a number of branch metric values associated with the received sequence to previous path metrics to form added metrics, compare the added metrics, and select a surviving path metric to form a selected surviving path metric; a track buffer track buffer including 2 M path registers configured to be capable of storing decisions indicative of the respective selected surviving path metrics from the 2 M-1 parallel connected ACS elements; and a voting unit configured to be capable of generating a decision bit based on the contents of the 2 M path registers by voting for the decision bit according to a voting protocol, wherein each of the 2 M-1 parallel connected ACS elements includes two path metric output lines providing ACS decision signals and two path feedback lines providing feedback signals, wherein the two path metric output lines in each of the 2 M-1 parallel connected ACS elements are connected to a track buffer, wherein the two path feedback lines in each of the 2 M-1 parallel connected ACS elements are respectively connected directly as input lines to two different ACS elements selected from the 2 M-1 parallel connected ACS elements, wherein the decoding operation includes a maximum a posteriori (MAP) decoding operation.