Patent ID: 8030165

Claim:
A method for forming flash memory devices, the method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a silicon material and having a periphery region and a cell region; forming an isolation structure between the cell region and the periphery region; forming an ONO layer overlying the cell region and the periphery region, the ONO layer comprising a bottom oxide layer, a nitride layer, and a top oxide layer; removing the ONO layer overlying the periphery region to expose silicon material in the periphery region; forming a gate dielectric layer overlying the periphery region, while protecting the ONO layer in the cell region; forming a polysilicon layer overlying the cell region and the periphery region; patterning the polysilicon layer to form a first gate structure in the cell region, while stopping on at least the top oxide layer of the ONO layer and to form a second gate structure in the periphery region, while stopping on the gate dielectric in the periphery region; forming first dielectric spacer structures on the first gate structure with an etch process that stops at the nitride layer of the ONO layer and forming second dielectric spacer structures on the second gate structure; removing remaining portions of the ONO layer unmasked by the first dielectric spacer structures to expose the silicon material in the cell region and removing exposed portion of the gate dielectric to expose the silicon material in the periphery region, wherein forming the first and second dielectric spacer structures also exposes top surfaces of the first and the second gate structures, respectfully; and forming salicide material overlying the first gate structure and a first source and a first drain associated with the first gate structure, the salicide material also overlying the second gate structure and a second source and a second drain associated with the second gate structure.