Patent ID: 7330377

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of data-storing memory cells arranged at intersection of a word line and bit line; a decoder operative to select a memory cell in said memory cell array; a driver configured to charge said word line or bit line; a voltage generator operative to generate a voltage supplied to said driver; a sequence controller operative to control operations of said voltage generator and said driver in accordance with a procedure instructed by a command and along an operation timing indicated by a control signal; a control signal generator configured to generate said control signal and including a resistor, said resistor having a resistance variable to change the state of said control signal; a storage unit operative to store adjustment data for setting a resistance of said resistor at a designed resistance; and a control unit operative to refer to said storage unit for stored data and switch said resistor to control the state of said control signal, and operative to control said driver to change a rate of charging said word line or bit line.