Patent ID: 7078248

Claim:
A method for implementing defect inspection of an integrated circuit, the method comprising: configuring a power bus grid structure on a first metal interconnect level, said power bus grid structure including a first plurality of wire pairs; said first plurality of wire pairs arranged in a manner such that a first wire in each of said first plurality of wire pairs is electrically coupled to conductive structures beneath said first metal interconnect level, and a second wire in each of said first plurality of wire pairs is initially electrically isolated from said conductive structures beneath said first metal interconnect level; forming a first via level over said first metal interconnect level, said first via level having via connections arranged to electrically couple said first and said second wires in each of said plurality of wire pairs in said first metal interconnect level; forming a second metal interconnect level over said first via level, said second metal interconnect level including a second plurality of wire pairs; said second plurality of wire pairs arranged in a manner such that a first wire in each of said second plurality of wire pairs is electrically coupled to said via connections of said first via level, and a second wire in each of said second plurality of wire pairs is initially electrically isolated from said via connections of said first via level; biasing said first wire in each of said first plurality of wire pairs to a known voltage; performing a charge contrast inspection between said first wire and said second wire of each of said first plurality of wire pairs; biasing said first wire in each of said second plurality of wire pairs to said known voltage; and performing a charge contrast inspection between said first wire and said second wire of each of said second plurality of wire pairs.