Patent ID: 8188530

Claim:
A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device comprising: a semiconductor substrate; an insulating film provided on the semiconductor substrate in the cell array section; a back gate electrode provided on the insulating film; a stacked body provided on the back gate electrode and including a plurality of insulating films and electrode films alternately stacked; a plurality of semiconductor pillars extending in a stacking direction of the insulating films and the electrode films of the stacked body and piercing the stacked body; connection members provided in or on the back gate electrode, each of the connection members connecting a lower end of one of the semiconductor pillars to a lower end of another one of the semiconductor pillars; charge storage layers provided between the electrode films and the semiconductor pillars and between the back gate electrode and the connection members; a back-gate electrode contact applying a potential to the back gate electrode; a pair of source/drain regions formed apart from each other in an upper layer portion of the semiconductor substrate in the peripheral circuit section; a gate insulating film provided immediately above a region between the source/drain regions on the semiconductor substrate; a gate electrode provided on the gate insulating film; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.