Patent ID: 7023750

Claim:
A circuit, realizing a Sense Electronics Endowed (SEE) memory device with dynamical biasing of memory sense amplifiers, comprising: a memory array for realizing an SEE-memory device with dynamical biasing of memory sense amplifiers using a sense amplifier with bias current control facility controlled by a “System Clock” signal and having external Address and Data I/O bus system connections; a sense amplifier with read data input and output as well as a bias current control input, whereby said bias current control input is delivered from a bias regulation unit; a bias regulation unit with address change detect signal input generating a time dependent bias current control output signal; and an address transition detection logic delivering said address change detect signal for said bias regulation unit, whereby said address change detect signal is generated from an address being altered on said external Address bus system, then causing the reading of memory data from a memory address location as addressed via said Address bus system with a fully biased memory sense amplifier and finally putting said memory data on said external data I/O bus, whereas said memory sense amplifier is normally biased in order to reduce said bias current according to a dynamical bias current control scheme established within said bias regulation unit until the next address change detect signal is furnished by said address transition detection logic and said dynamical bias current control scheme for application within a read cycle operation governed by said “System Clock” signal; the dynamical bias current control scheme being generated so, that the bias current is controlled by said address change detect signal and defined in a time dependent manner reducing after a certain time of said bias current.