Patent ID: 6946877

Claim:
A circuit for evaluating logic level input signals, said circuit comprising: a pre-charge node; a clock evaluate node coupled to cause charging of said pre-charge node in response to the logic level of said clock evaluate node; an output node coupled to said pre-charge node through an inverter logic subcircuit; a plurality of logic input signal nodes configured to receive logic level input signals; and multiple pull-down stacks interconnected with said pre-charge node, each said pull-down stack comprising an interstitial node and coupled to discharge said pre-charge node to ground in response to said logic level input signals; said interstitial node of each said pull-down stack coupled to an interstitial pre-charger device, said interstitial pre-charger device further coupled to deliver charge to said interstitial node in response to the logic level of said clock evaluate node; and said interstitial node coupled to an interstitial discharger device, said interstitial discharger device gated to ground and coupled to discharge said interstitial node to ground in response to said logic level of said clock evaluate node.