Patent ID: 6861307

Claim:
A method of fabricating a dual bit charge storage device on a silicon substrate, the method comprising: a) fabricating a layered island on the surface of the substrate with an island perimeter defining a gate region, the layered island comprising a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer; b) removing a portion of the isolation barrier dielectric layer to form an undercut region within the gate region; c) depositing a charge trapping material within the undercut region; d) forming a charge trapping layer positioned between the tunnel dielectric layer and the top dielectric layer from the charge trapping material, the charge trapping layer including a source charge trapping region towards one end of the charge trapping layer, a drain charge trapping region towards an opposite end of the charge trapping layer, and an isolation barrier interposed between the source charge trapping region and the drain charge trapping region, wherein the isolation barrier is substantially less conductive relative to the source charge trapping region and the drain charge trapping region, and functions to reduce charge spread through the charge trapping layer between the source charge trapping region and the drain charge trapping region.