Patent ID: 8095701

Claim:
A computer system, comprising: a CPU (central processing unit) module including a plurality of CPU cores, an I/O (input/output) bridge that is connected to the CPU cores, and a main memory that can be accessed from the CPU cores and the I/O bridge; and an I/O switch that connects the I/O bridge of the CPU module to an I/O module, wherein the CPU module includes a firmware that divides the plurality of CPU cores and the main memory into a plurality of logical partitions, wherein the I/O bridge: constructs a down packet denoting an I/O access originated from one of said logical partitions, by adding first turn pool information which identifies a route from the I/O bridge to the I/O module, and second turn pool information, which is turn pool information of a virtual switch virtually formed in the I/O bridge, and which identifies the logical partition that originates said I/O access information obtained from the logical partition; extracts, from a response packet received via the I/O switch, third turn pool information which inherits the second turn pool information transferred to the I/O module, and identifies a destination of an entity of the response packet; and reads the extracted third turn pool information and forwards the entity of the response packet to a logical partition identified by the third turn pool information, stores a base address and a size of a region on the main memory to which the corresponding logical partition is allocated in association with each of the logical partitions; extracts a command that is included in the response packet received via the I/O switch; acquires, when the extracted command is a DMA (Direct Memory Access) command, the base address and the size corresponding to the respective logical partition, and adds the base address to a DMA address that is included in the DMA command; and conducts DMA access directly to the respective address of the main memory obtained as a result of adding the base address to the DMA address, the respective address being an address other than a result obtained by adding the base address to the DMA address that exceeds the respective region on the main memory which is respectively allocated to the corresponding logical partition indicated by size, wherein the I/O switch transfers the down packet and the response packet according to the route identified by the first turn pool information.