Patent ID: 8106691

Claim:
A phase adjustment circuit, comprising: a multiphase clock-generation circuit configured to generate multiphase clocks having a frequency twice as high as the frequency of a reference clock; a first selection circuit configured to select one of the multiphase clocks based on a phase selection signal and output the one as a selected clock; a second selection circuit configured to select a clock, among the multiphase clocks, apart in phase from both the reference clock and the selected clock and output the clock as an intermediate clock; a first ½ frequency division circuit having a phase inversion function configured to divide the frequency of the intermediate clock by two and output the resultant clock as an intermediate reference clock; a second ½ frequency division circuit having a phase inversion function configured to divide the frequency of the selected clock and output the resultant clock as a phase-adjusted clock; a first phase control circuit configured to control the output phase of the first ½ frequency division circuit having the phase inversion function that generates the intermediate reference clock so that the reference clock and the intermediate reference clock are in a phase relationship based on the phase selection signal; and a second phase control circuit configured to control the output phase of the second ½ frequency division circuit having the phase inversion function that generates the phase-adjusted clock so that the intermediate reference clock and the phase-adjusted clock are in a phase relationship based on the phase selection signal.