Patent ID: 7574648

Claim:
A semiconductor device comprising: a plurality of sub-array blocks, each said block including a memory array having a plurality of word lines, a plurality of first data lines, a plurality of first memory cells disposed at nodes of said plurality of word lines and said plurality of first data lines, a plurality of second data lines, and a plurality of second memory cells disposed at nodes of said plurality of word lines and said plurality of second data lines, said plurality of second memory cells being provided to check for errors; a plurality of sense amplifier circuits connected to said plurality of first data lines and said plurality of second data lines; and error detection and correction circuitry connected to the plurality of first data lines and the plurality of second data lines to detect and correct an error in data read out of said plurality of first memory cells and said plurality of second memory cells; and an I/O data line which is commonly connected to said plurality of sub-array blocks and carries out I/O operations of data with a sub-array block selected from among said plurality of sub-array blocks, wherein a number of said plurality of first memory cells connected to one of said plurality of word lines is larger than that of said plurality of second memory cells connected to the same word line.