Patent ID: 8456935

Claim:
A memory comprising: a local data line pair; a local data line precharge circuit coupled to said local data line pair and to a first voltage representative of a first logic state; a local sense amplifier coupled to said local data line pair and active in response to a first control signal; a global data line pair; a global data line precharge circuit coupled to said global data line pair and to a second voltage representative of a second logic state; a driver circuit having inputs coupled to said local data line pair and to said first voltage, and outputs coupled to said global data line pair; a global sense amplifier coupled to said global data lines and active in response to a second control signal; and a control circuit responsive to a read cycle to activate said first control signal while said second control signal is inactive, to activate said second control while said first control signal remains active, and to deactivate said first control signal while said second control signal remains active.