Patent ID: 8227841

Claim:
A semiconductor device comprising: a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region; the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; the entire portion of the first source/drain region that forms a boundary with the intermediate region being separated vertically from the top of the intermediate region, wherein the portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the lowest part of the second source/drain region, and wherein the first source/drain region is disposed within a trench etched into a substrate of the device, and further comprising a corresponding device formed on the substrate immediately adjacent to said device, the first source/drain region of each device sharing the trench.