Patent ID: 6995063

Claim:
A method of fabricating a memory cell in a semiconductor device, comprising the steps of: defining a source area, a first floating gate area, a control gate area, a second floating gate area, and a drain area on a substrate to have the control gate area lie between the first and second floating gate areas; forming source and drain regions on the source and drain areas of the substrate, respectively; forming a gate oxide layer on the semiconductor substrate; reducing the gate oxide layer on the first and second floating gate areas in thickness; forming first and second floating gates on the reduced gate oxide layer in the first and second gate areas, respectively; forming an oxide-nitride-oxide layer on top sides and confronting sidewalls of the first and second floating gates; and forming a control gate on the oxide-nitride-oxide layer and the gate oxide layer on the control gate area to be overlapped with the first and second floating gates.