Patent ID: 8283261

Claim:
A method of fabricating a nonvolatile charge trap memory device, the method comprising: oxidizing a portion of a charge-trapping layer disposed above a substrate to form a blocking dielectric layer above the charge-trapping layer, the oxidizing performed by exposing the charge-trapping layer to a hydrogen and oxygen radical oxidation process, wherein the charge-trapping layer comprises a bottom oxygen-rich silicon oxy-nitride portion having a thickness approximately in the range of 2.5-3.5 nanometers and a top silicon-rich silicon oxy-nitride portion having a thickness approximately in the range of 9-10 nanometers, and wherein oxidizing the portion of the charge-trapping layer comprises oxidizing the top approximately 2 nanometers to approximately 3 nanometers of the top silicon-rich silicon oxy-nitride portion to form the blocking dielectric layer having a thickness approximately in the range of 3.5-4.5 nanometers.