Patent ID: 7005931

Claim:
A semiconductor integrated circuit having a plurality of CMOS inverters connected in an odd number of stages and a ring oscillator circuit for feeding a final-stage output signal of a final-stage CMOS inverter back to an input end of a first-stage CMOS inverter thereby causing self-oscillation, the semiconductor integrated circuit wherein: the first-stage CMOS inverter comprises a transistor series circuit including PMOS and NMOS transistors connected between a power voltage terminal and a reference voltage terminal, and a delay circuit for delaying a first-stage output signal of the first-stage CMOS inverter; and the delay circuit comprises a capacitor coupled between an output node of the first-stage CMOS inverter and the reference voltage terminal, and a resistance parallel circuit inserted and coupled on a current passage of the transistor series circuit at between the output node and the reference voltage terminal; the resistance parallel circuit being configured by a parallel connection of a plurality of resistance elements different in resistance-value temperature characteristic.