Patent ID: 8190863

Claim:
A method comprising: populating a first resource utilization register of a first processor core of a chip multiprocessor to define a first resource utilization policy within a minimum utilization level and a maximum utilization level, said first resource utilization register to limit a maximum instruction issue rate of said first processor core; populating a second resource utilization register of a second processor core of said chip multiprocessor to define a second resource utilization policy for the second processor core that is within the minimum utilization level and the maximum utilization level and is different from the first resource utilization policy of the first processor core, said second resource utilization register to limit a maximum instruction issue rate of said second processor core; periodically receiving an instruction processed count from one of the first processor core and the second processor core; and updating one of the first and the second resource utilization registers to adjust a resource utilization policy of one of the first processor core and the second processor core responsive to the processed count, each of the first and second resource utilization.