Patent ID: 8199575

Claim:
A memory cell array of a memory, comprising: a main memory cell array, comprising: a plurality of local bit lines comprising a first local bit line and a second local bit line; a plurality of word lines; and a plurality of memory cells, each of which corresponds to and is connected to one of the local bit lines and one of the word lines and, for storing data; and a selected array, comprising: at least one global bit line; at least one first bit line transistor (BLT) control line; at least one first transistor, which is coupled to the global bit line, the first local bit line and the first BLT control line and may be controlled by the first BLT control line to selectively turn on to connect the global bit line to the first local bit line; and at least one first fixed value memory cell, which is coupled to the global bit line, the second local bit line and the first BLT control line and programmed to a fixed value such that a threshold voltage of the first fixed value memory cell is greater than a threshold voltage of the first transistor.