Patent ID: 7319628

Claim:
A semiconductor memory comprising: a plurality of memory portions; and a plurality of spare memory portions, wherein each of said plurality of memory portions includes: a main cell array which includes a plurality of memory cells, each of said plurality of memory cells stores data in a nonvolatile state, a first reference cell which stores a first reference data in a nonvolatile state, and a first sense amplifier which reads a first state of said each of the plurality of memory cells, based on said first state and a second state of said first reference cell, each of said plurality of spare memory portions includes: a spare cell array which is provided as a spare of said main cell array, and includes a plurality of spare cells as spares of said plurality of memory cells, a second reference cell which stores a second reference data in a nonvolatile state, and a second sense amplifier which reads a third state of said each of the plurality of spare cells, based on said third state and a fourth state of said second reference cell, one of said plurality of memory portions is replaced with one of said plurality of spare memory portions, if said one of said plurality of memory portions is a defective memory portion which has a defect on said first reference cell.