Patent ID: 8441033

Claim:
A semiconductor device comprising: a semiconductor substrate; a gate electrode; a recess in said semiconductor substrate; a gate insulating film lining said recess; stress applying layers for applying a stress to a channel part under said gate electrode; and extensions of a source region and a drain region in said semiconductor substrate, wherein, said stress applying layers are formed in said semiconductor substrate respectively on both sides of said gate electrode and extend to a first position below a surface of said semiconductor substrate, said recess extends below the surface of said semiconductor substrate and is between said stress applying layers, said recess extends below said extensions of the source and the drain region, said gate insulating film that lines said recess is at least one insulating layer, and the same at least one insulating layer is formed along both a bottom surface of said recess and side surfaces of said recess; said gate electrode is received within said recess and is in contact with said gate insulating film along both said bottom surface of said recess and said side surfaces of said recess, said stress applying layers are formed of a semiconductor material having a different lattice constant from that of said semiconductor substrate and are formed by epitaxial growth in recessed portions in said semiconductor substrate, said semiconductor substrate is formed of single-crystal silicon, said stress applying layers are formed of silicon containing an elemental material having a different lattice constant from that of silicon, said channel part is at a second position below the surface of said semiconductor substrate, and said second position of said channel part with respect to the surface of said semiconductor substrate is shallower than said first position of said stress applying layers.