Patent ID: 7269225

Claim:
A serial digital signal transmission system comprising a residual time stamp (RTS) generator circuit for separating high definition television (HDTV) serial digital signals to be transmitted into parallel data and time information residual time stamps (RTSs) and transmitting said parallel data and said time information RTSs, and an RTS receiver circuit for receiving said parallel data and said time information RTSs that have been transmitted and obtaining said HDTV serial digital signals as they were originally, wherein: said RTS generator circuit has: first frequency dividing means for dividing a network clock into a prescribed first frequency, a serial-to-parallel converter for subjecting said HDTV serial digital signals to be transmitted to serial-to-parallel conversion, transmitting data of the resultant parallel signals and supplying a clock divided into a second frequency, a first counter for dividing said frequency-divided clock supplied from said serial-to-parallel converter into a 1/N frequency, and a latch circuit for latching at the output timing of said first counter the clock resulting from the frequency division by said first frequency dividing means to supply said time information RTSs, and said RTS receiver circuit comprises: second frequency dividing means for dividing the frequency of said network clock into said prescribed first frequency, gate pulse generating means for generating a gate pulse on the basis of said network clock, memory means for temporarily storing said RTSs which have been transmitted, a comparator for comparing the clock resulting from frequency division by said second frequency dividing means and said RTSs read out of said memory means, a gate circuit for gating the output signal of said comparator on the basis of said gate pulse from said gate pulse generating means, frequency multiplying means for regenerating the clock of said second frequency by multiplying the frequency of the output signal of said gate circuit to said N-multiplied frequency, and a parallel-to-serial converter for receiving as its inputs regenerated clock of said second frequency supplied from said frequency multiplying means and data of said parallel signals that have been transmitted, and subjecting regenerated clock and data of parallel signals to parallel-to-serial conversion to obtain said HDTV serial digital signals, 8 , 15 or 16 being selected as the value of said N.