Patent ID: 8880779

Claim:
A memory subsystem comprising: non-volatile memory; a memory controller coupled to the non-volatile memory via a first bus; a host interface coupled to a host controller via a second bus, wherein the host interface is configured to receive commands to be executed by the memory controller from the host controller; and a joint test action group (JTAG) interface coupled to the host controller via a third bus, wherein the JTAG interface is configured to: provide state information associated with the memory controller to the host controller responsive to a request from the host controller; receive input test data from the host controller via the third bus; send the input test data to the non-volatile memory via the first bus; retrieve output data from the non-volatile memory via the first bus; and send the output test data to the host controller via the third bus; wherein the memory subsystem is configured to be coupled to a board-level memory device that includes the host controller.