Patent ID: 7715250

Claim:
An apparatus, comprising: a plurality of multiple-type memories, wherein the plurality of multiple-type memories are vertically configured memories; a first circuitry configured to invert a bit of a memory address; a second circuitry configured to select the bit of the memory address or the inverted bit from the first circuitry configured to invert the bit based on a polarity select parameter; a first logic circuit in electrical communication with the second circuitry and configured to select the bit, the first logic circuit being configured to output a memory select value operative to select one of the plurality of multiple-type memories for a data operation; and a logic plane positioned in a substrate, the logic plane including the first circuitry, the second circuitry, and the first logic circuit, and the vertically configured memories are in contact with the substrate and are positioned directly over the substrate and in electrical communication with the logic plane.