Patent ID: 8680628

Claim:
A semiconductor structure comprising: a substrate having a surface; and a plurality of gate structure devices at least partially overlying the substrate, where the plurality of gate structure devices comprises a first gate structure device and a second gate structure device defining a gate-to-gate spacing therebetween, the first gate structure device coupled to the second gate structure device via a first raised source/drain formed in a gate-to-gate source/drain area defined by the gate-to-gate spacing and having a first length determined by a minimum gate-to-gate source/drain area operable to minimize parasitic capacitance associated with the first gate structure device and the second gate structure device and having a first height, where the first gate structure device is further coupled to a second raised source/drain having a second length and a second height, where the first gate structure device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overlie the surface of the substrate by said first height and said second height, respectively, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length so that the second raised source/drain having the relatively greater second length is effective for providing the terminal electrical contact, and the second height is greater than the first height, where the first raised source/drain and the second raised source/drain comprise a faceted epitaxy structure having a generally triangle-shaped cross section, and the faceted epitaxy structure of the second raised source/drain is larger than the faceted epitaxy structure of the first raised source/drain.