Patent ID: 8213467

Claim:
A system comprising: an application specific integrated circuit (ASIC) comprising: a plurality of components for providing a first level of signal channel reduction and a second level of signal channel reduction, wherein said first and second levels of signal channel reduction are achieved by selecting which of said components to enable; and a plurality of multiplexers providing N to M signal multiplexing, wherein in the first level of signal channel reduction said ASIC is configured to provide N to M signal multiplexing; wherein in the second level of signal channel reduction said ASIC is configured to provide N to M/2 signal multiplexing; wherein said plurality of multiplexers include N signal inputs, M signal outputs, at least one select signal input, and at least one enable signal input, said enable signal input being utilized in providing said N to M/2 signal multiplexing in said second level of signal channel reduction; and wherein said plurality of multiplexers are divided into hardwired pairs, and only one of each pair is enabled during a receive operation.