Patent ID: 7086018

Claim:
An electronic circuit designing method comprising: an analyzing step analyzing noise with respect to a wiring pair; and a correcting step automatically correcting the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise by said analyzing step, wherein said analyzing step detects a noise error if a parallel wiring length for which adjacent wirings of a victim net and an aggressor net are parallel to each other in an adjacent wiring portion between the victim net and the aggressor net exceeds a tolerable parallel wiring length L described by: L≦f 6( Ra, Rv, Cc ) where Ra denotes an aggressor side driver resistance, Rv denotes a victim side driver resistance, and Cc denotes a coupling capacitance between two adiacent wirings.