Patent ID: 7476920

Claim:
An integrated circuit, comprising: a first access transistor, a second access transistor, a third access transistor, and a fourth access transistor, each access transistor comprising a gate electrode and an active area, each active area being formed in a substrate and adjacent to a pattern surface of the substrate, each gate electrode being disposed at least in part in a recess groove that is formed in the active area between a respective node contact section and a respective bit line contact section formed within the respective active area, the third access transistor being arranged adjacent to the second access transistor such that the bit line contact sections of the second and third access transistors form a common bit line contact section and such that the active areas of the second and third access transistors form a contiguous semiconductor line; an isolation transistor arranged between the first and the second access transistors, the first and the second access transistors facing laterally reversed and opposing the isolation transistor, the node contact sections of the first and second access transistors being adjacent to the isolation transistor; and a further isolation transistor arranged between the third and the fourth access transistors, the third and fourth access transistors facing laterally reversed and opposing the further isolation transistor, the node contact sections of the third and fourth access transistors being adjacent to the further isolation transistor; wherein the isolation transistors are controllable by isolation gate lines, each isolation gate line being disposed at least in part in an isolation groove and being separated from the substrate by an isolation gate dielectric, the isolation groove being formed in the substrate between the node contact sections of the first and the second access transistors and between the node contact sections of the third and the fourth access transistors.