Patent ID: 7456055

Claim:
A process for forming an electronic device comprising: providing a workpiece including a base layer, a first semiconductor layer that overlies and is spaced apart from the base layer, a second semiconductor layer, and an insulating layer lying between the first semiconductor layer and the second semiconductor layer; forming a first opening in the insulating layer extending to the first semiconductor layer, wherein the insulating layer lies between the first and second semiconductor layers; epitaxially growing a third semiconductor layer from the first semiconductor layer after forming the first opening; removing a portion of the second semiconductor layer to form a first semiconductor fin that overlies and is spaced apart from the first semiconductor layer, and removing a portion of the third semiconductor layer to form a second semiconductor fin that is spaced apart from the first semiconductor fin, wherein: before removing the portion of the second semiconductor layer and removing the portion of the third semiconductor layer, top surfaces of the second and third semiconductor layers lie along a same plane; and removing the portion of the second semiconductor layer and removing the portion of the third semiconductor layer are performed substantially simultaneously during at least one point in time; forming a first gate electrode overlying the first semiconductor fin; and doping portions of the first semiconductor fin to form first source/drain regions entirely within the first semiconductor fin, wherein a first transistor includes the first semiconductor fin, the first gate electrode, and the first source/drain regions.