Patent ID: 7528021

Claim:
A method of manufacturing a thin film transistor array panel, comprising: forming a semiconductor of a polysilicon layer on an insulating substrate; forming a gate insulating layer on the semiconductor; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key on the insulating substrate simultaneously with the semiconductor, wherein the first alignment key includes a display portion made in relief and representing a shape of the first alignment key, a circumferential portion surrounding the display portion and made in intaglio, and a detection portion defining the outline of the circumference portion and made in relief.