Patent ID: 8669156

Claim:
A method of manufacturing a semiconductor circuit device including an NMOS and a PMOS transistor, an EDS protection device, and a capacitor element, the method comprising: selectively forming a LOCOS film on a semiconductor substrate to form an active region; forming a gate insulating film on a surface of the active region; forming a first polysilicon film on the gate insulating film and the LOCOS film; patterning the first polysilicon film to form a lower electrode of the capacitor element and gate electrodes of the NMOS transistor, the PMOS transistor, and a gate electrode of the ESD protection device; after forming the lower electrode and the gate electrodes, implanting high concentration N-type impurities into a region for the ESD protection device which is not of an LDD type and the lower electrode of the capacitor element at a dose of 5×10 14 ions/cm 2 to 2×10 16 ions/cm 2 , wherein the gate electrode of the ESD protection device comprises a first resistance element having a first electrical resistance and the upper electrode of the capacitor element comprises a second resistance element having a second electrical resistance that is higher than the first electrical resistance; implanting N-type impurities into a region for the NMOS transistor which is of an LDD type to form N-type LDD regions, and implanting P-type impurities into a region for the PMOS transistor which is of the LDD type to form P-type LDD regions; forming a capacitor film; forming a second polysilicon film on the capacitor film; patterning the second polysilicon film to form an upper electrode of the capacitor element and a resistor element; implanting N-type impurities at a dose of 5×10 14 ions/cm 2 to 2×10 16 ions/cm 2 to form N-type source and drain regions, an N-type polysilicon gate electrode, an N-type upper electrode of the capacitor, and an N-type contact region; and implanting P-type impurities at a dose of 5×10 14 ions/cm 2 to 2×10 16 ions/cm 2 to form P-type source and drain regions, a P-type polysilicon gate electrode, an P-type upper electrode of the capacitor, and a P-type contact region.