Patent ID: 7135880

Claim:
A test apparatus for testing a device under test (DUT), comprising: a pattern generator for generating a pattern data of a test signal supplied to said device under test; a waveform formatter for formatting said test signal indicated by said pattern data; and a driver for outputting said test signal formatted by said waveform formatter to said device under test, wherein said waveform formatter comprises: a first delay circuit for delaying a set signal to control timing of a first change point of said test signal during a predetermined cycle of a cycle reference signal; a second delay circuit for delaying a reset signal to control timing of a second change point of said test signal changed by the set signal delayed by said first delay circuit; a third delay circuit for delaying a set signal to control timing of a third change point of said test signal during said predetermined cycle of said cycle reference signal; a fourth delay circuit for delaying a reset signal to control timing of a fourth change point of said test signal changed by the set signal delayed by said third delay circuit; a fifth delay circuit for delaying a set signal to control timing of a first change point of an enable signal with regard to said driver during said predetermined cycle of said cycle reference signal; and a sixth delay circuit for delaying a reset signal to control timing of a second change point of said enable signal for said driver during said predetermined cycle of said cycle reference signal.