Patent ID: 7852124

Claim:
A circuit for correlated double sampling with low noise and low power dissipation, the circuit comprising: an amplifier having an input which is directly connected to a reset voltage or a signal voltage and is arranged to provide a reset voltage replica and a signal voltage replica; a plurality of capacitors coupled to the amplifier, the plurality of capacitors including a first capacitor, a second capacitor and a third capacitor; and a switch matrix coupled to the amplifier and the plurality of capacitors, and configured to receive a voltage from the amplifier, wherein the switch matrix is configured to control a plurality of switches to perform correlated double sampling, the correlated double sampling having at least three phases including: a first phase for sampling a charge representing the reset voltage replica from the amplifier on the first and second capacitors while producing a kTC noise from the first and second capacitors, a second phase for sampling a charge representing the reset voltage replica and the kTC noise on the third capacitor, and a third phase for introducing the signal voltage replica in the switch matrix and for subtracting a charge representing the signal voltage replica, the kTC noise and the reset voltage replica, combined, from the charge sampled in the second phase to provide an output voltage.