Patent ID: 8245087

Claim:
An apparatus comprising: a random access memory device including a plurality of addressable memory locations; a first memory manager coupled to the memory device, the first memory manager including an input queue operable to receive and store a plurality of requests from a processor for data to be read from memory locations in the memory device, wherein a memory manager transaction identifier (MMTID) is also stored with each stored request in the input queue that uniquely identifies the stored request; and a scrub engine coupled to the first memory manager, wherein the scrub engine is operable to request data to be read from the memory device and to detect and correct single bit errors in the read data, and wherein the first memory manager further includes a scheduling unit operable: to detect whether there is a multi-bit error in data read from a memory location in the memory device due to a data_read operation, to perform a retry operation that includes up to N re-read operations of the data read operation that resulted in the detected multi-bit error, wherein the re-read operations continue up to N times as long as the data read from the first memory location includes detected multi-bit errors, in order to distinguish between an intermittent multi-bit error and a persistent multi-bit error, to determine that the multi-bit error is an intermittent error if one of the re-read operations results in not having a detected multi-bit error, to determine that the multi-bit error is a persistent error if the re-read operations have occurred N times, where N is greater than one, and the data read on each of the N re-read operations has had a detected multi-bit error, and to log an address of the memory location associated with those multi-bit errors that are determined to be persistent multi-bit errors.