Patent ID: 7385865

Claim:
A circuit, comprising: (a) a global bit line; and (b) local bit cell groups coupled to the global bit line, each local bit cell group comprising: (i) a local bit line and bit cells controllably coupled to the local bit line, the local bit line being controllably coupled to the global bit line and comprising a complementary pair of bit lines to be precharged at substantially the same level, wherein the bit cells have substantially unity cell ratios. (ii) a local precharge circuit coupled to its associated local bit line to charge the bit line during a precharge state, and (iii) one or more gates to controllably couple its associated local bit line to the global bit line, wherein the local precharge circuit and one or more gates are part of a common precharge/gate circuit controlled by a common control signal; and (c) a global precharge circuit coupled to the global bit line for charging it during the precharge state.