Patent ID: 7767499

Claim:
A method for forming a vertically oriented p-i-n diode, the method comprising: forming a first rail-shaped conductor above a substrate; forming the p-i-n diode by: (a) forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductor; (b) forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type region of deposited semiconductor material, wherein the middle intrinsic or lightly doped region of deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy; (c) patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a pillar; (d) forming a top heavily doped n-type region of deposited semiconductor material by doping with arsenic; forming a silicide-forming metal region in contact with the top heavily doped n-type region of the p-i-n diode; forming a silicide, germanide, or silicide-germanide by reacting the silicide-forming metal region with the top heavily doped n-type region of the p-i-n diode; and annealing to crystallize the deposited semiconductor material, where some portion of the deposited semiconductor material was amorphous as deposited and is in contact with the silicide, germanide, or silicide-germanide before the annealing step.