Patent ID: 6937290

Claim:
A circuit for generating a train of synthesized sync pulses in accordance with the Bresenham algorithm in response to an input clock having frequency F i , including: first circuitry coupled to receive the input clock and configured to generate a control signal indicative of events having time-averaged frequency at least nearly equal to (A/T)F i , where A and T are integer values, such that accumulated error, between a first time from a first one to a last one of Z consecutive ones of said events and a second time equal to ZT/(AF i ), never exceeds 1/F i ; and second circuitry coupled to receive the control signal and configured to assert the sync pulses in response to said control signal such that leading edges of the pulses occur at least nearly periodically, with said time-averaged frequency at least nearly equal to (A/T)F i , and with accumulated error, between a third time from a first one to a last one of Z consecutive ones of said leading edges and the second time ZT/(AF i ), that never exceeds 1/F i .