Patent ID: 8434043

Claim:
A method for developing a violation free IC layout, comprising: identifying a violation path that has two adjacent shapes that cannot be decomposed in a manner that does not violate a minimum spacing rule by using a computer, wherein the violation path extends between two or more pre-colored shapes within a double patterning technology (DPT) layer of a pre-colored IC layout having two or more pre-colored shapes, and wherein upon being decomposed pre-colored shapes of the DPT layer having a first color are assigned to a first photomask and pre-colored shapes of the DPT layer having a second color are assigned to a second, different photomask; identifying good paths and bad paths between the two or more pre-colored shapes by using the computer, wherein upon being decomposed the good paths will have no adjacent shapes with a same color and the bad paths will have adjacent shapes with a same color; and providing hints or warnings based upon the good paths and the bad paths, wherein the hints or warnings provide guidance to eliminate the violation path.