Patent ID: 7657802

Claim:
A memory device comprising: an array of memory cells; and data compression read circuitry, the circuitry comprising: a first data compression circuit for generating a first match signal when a predetermined bit of each of a plurality of data words are all equal to a first logical state, the first circuit comprising a plurality of logical state match circuits each having a complementary transfer gate controlled by a logical combination of the predetermined bit of the plurality of data words and an enable signal; a second data compression circuit for generating a second match signal when the predetermined bit of each of the plurality of data words are all equal to a second logical state, the second circuit comprising a plurality of logical state match circuits each having a complementary transfer gate controlled by a logical combination of the predetermined bit of the plurality of data words and the enable signal; and an output buffer circuit for passing either the data state of the predetermined bit or the output buffer circuit being in a high impedance state in response to the first or second match signals.