Patent ID: 6924682

Claim:
A latch circuit with a metastability trap comprising: at least three input latches each having an input terminal for receiving an input signal, a clock terminal for receiving a first clock signal, and an output terminal, said at least three input latches latching values of said input signal compared to at least three corresponding different threshold voltages at a predetermined point in time to provide at least three corresponding latched values; a first logic gate having input terminals coupled to corresponding output terminals of each of said at least three input latches, and an output terminal for providing a first intermediate signal, said first logic gate activating said first intermediate signal in response to signals at all of said input terminals being in a first logic state, and keeping said first intermediate signal inactive otherwise; a second logic gate having input terminals coupled to corresponding output terminals of each of said at least three input latches, and an output terminal for providing a second intermediate signal, said second logic gate activating said second intermediate signal in response to signals at all of said input terminals being in a second logic state, and keeping said second intermediate signal inactive otherwise; and a flip-flop having a set input terminal coupled to said output terminal of said second logic gate, a reset terminal coupled to said output terminal of said first logic gate, and an output terminal for providing an output signal of the latch circuit.