Patent ID: 6895518

Claim:
An arrangement of a plurality of integrated circuit devices including a first integrated circuit device driven by a first clock signal at a first clock rate, the arrangement comprising: a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal; a universal asynchronous receiver/transmitter (UART) chip including a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal, a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit, and a data-storage-register circuit adapted to output status data to the parallel data bus, the status data indicative of states of at least one of the serial communication circuit and the parallel bus interface circuit; and a clock control circuit adapted to reduce the first clock rate in response to a clock control signal and therein provide a power-reduced UART mode in which the serial communication circuit is adapted to continue communication of serial data at the second rate.