Patent ID: 7440320

Claim:
A semiconductor memory device comprising: a memory cell array comprising first through n-th memory blocks where “n” is 2 or a natural number greater than 2; a row decoder decoding a block address signal and activating one block selection signal among first through n-th block selection signals to select one memory block among the first through n-th memory blocks; and a row-line voltage level selector decoding a word line address signal and generating voltages to be respectively applied to row lines in a memory block corresponding to the activated one block selection signal, wherein the row decoder comprises: an address decoder decoding the block address signal and activating one enable signal among first through n-th enable signals; and first through n-th selection signal generators each electrically connecting a boosted voltage node to an output node to activate the corresponding one block selection signal when the corresponding one enable signal among the first through n-th enable signals is activated and electrically breaking a path between the boosted voltage node and the output node and a path between the boosted voltage node and a ground voltage node when the corresponding enable signal is deactivated.