Patent ID: 7725696

Claim:
A method comprising: associating one of a plurality of dispatch registers of a dispatch stage of a processor to one of a plurality of buffer circuits of the dispatch stage, and to one of a plurality of functional units of the processor, and associating the one of a plurality of buffer circuits to the one of a plurality of functional units for executing a number of loop iterations of a loop including at least a first loop iteration and a subsequent loop iteration by the processor, the loop including a prologue set of loop instructions, a kernel set of loop instructions and an epilogue set of loop instructions; receiving in the plurality of dispatch registers the kernel set of loop instructions from an instruction stream fetched by the processor in the first loop iteration, with the one of the plurality of dispatch registers receiving at least one instruction of the kernel set of loop instructions to be executed by the one of the plurality of functional units; routing by the dispatch stage in the first loop iteration the at least one instruction from the one of the plurality of dispatch registers both to the one of the plurality of buffer circuits for storage and to the one of the plurality of functional units for execution; storing by the dispatch stage in the first loop iteration the at least one given instruction in the one of the plurality of buffer circuits; and causing with a control logic in at least the subsequent iteration the at least one instruction to be selectively issued from the one of the plurality of buffer circuits to the one of the plurality of functional units of the processor for execution in accordance with a plurality of stored loop parameters.