Patent ID: 8683158

Claim:
An apparatus comprising: a processor including: a status indicator to indicate whether the processor is operating in a system management mode (SMM); a base storage location to store a base address, where the base address is to specify a system management mode memory region (SMMR) of a system memory at which system management code is to be accessed; an abort storage location to store an abort address, where the abort address is to specify an other memory region of the system memory to which accesses to the system management mode memory region are to be steered in response to the processor not operating in the SMM, the other memory region to store code other than the system management code; steering logic to steer SMMR accesses to the other memory region in response to the processor not operating in the SMM; and control logic to: responsive to the processor not operating in the SMM, permit a first SMMR access to be steered to the other memory region via the steering logic, prevent the first SMMR access from access to the SMMR, and assign an un-cacheable memory type to the first SMMR access; and responsive to the processor operating in the SMM, allow the first SMMR access to access the SMMR and assign a memory type of the SMMR to the first SMMR access.