Patent ID: 8497160

Claim:
A method for reducing an undesirable parasitic impedance, attributable to a fabricated semiconductor device die having a top metal layer for interconnecting a number of its active terminals to its operating environment, the method comprises: step (a) patterning the top metal layer into a first plurality of contact zones and a second plurality of contact enhancement zones; step (b) electrically connecting at least one contact zone, through the interior device structure of the fabricated semiconductor device die, to at least one of the contact enhancement zones; and step (c) for each of said contact enhancement zones, attaching a solder layer atop it, the top surface of the solder layer being free of any electrical connection, for an increased composite thickness thus a correspondingly lowered parasitic impedance, including parasitic resistance and parasitic inductance components, against a surface current flow there through whereby reduce the undesirable parasitic impedance, attributable to the fabricated semiconductor device die, through said at least one contact zone.