Patent ID: 7669102

Claim:
A method for configuring a Serial Peripheral Interface Programmable Read Only Memory (SPI PROM) used in conjunction with a programmable logic device (PLD), the method comprising: providing a Joint Test Action Group (JTAG) port having a JTAG state machine contained within the PLD; loading a soft core into the PLD; coupling the soft core to the JTAG port; and coupling the SPI PROM to the soft core, wherein instructions and data are sent to the SPI PROM and data is received from the SPI PROM via the JTAG port and the soft core, sending, by a programming host device, a first synchronization code to the soft core; sending an identification code from the soft core; and sending, by the programming host device, a second synchronization code to the soft core, wherein the programming host device and the soft core are synchronized by the second synchronization code, and the second synchronization code instructs the soft core to send an instruction received from the programming host device to the SPI PROM, wherein the instruction and each new instruction is preceded by the first synchronization code and the second synchronization code.