Patent ID: 7265006

Claim:
A method of fabricating a heterojunction device module monolithically integrated with a CMOS structure in a semiconductor substrate, comprising the steps of: (a) In said semiconductor substrate, forming at least one heterojunction device active area surrounded by field oxide (FOX) regions, employing any of the conventional isolation technologies used in CMOS processes, said heterojunction active area containing at least one embedded well semiconductor region of a defined polarity implanted therein, said embedded semiconductor well being surrounded laterally at least on one side and underneath by semiconductor regions implanted with doping impurities of the opposite polarity, and having lateral dimensions such that said embedded well can be biased independently from other neighbouring embedded wells, said embedded semiconductor well extending itself under a selected portion of the surrounding field oxide regions and overlapping at least a fraction of a selected adjacent active area, said overlapped fraction of adjacent active area including a surface region with high doping concentration of the same polarity of the embedded semiconductor well; (b) formation of key regions of MOSFET devices, including growth and/or deposition of gate dielectric, deposition and patterning of gate electrode, ion-implantation of lightly-doped source/drain (LDD) regions (c) epitaxially growing the heterojunction device layers on said at least one heterojunction active area; (d) forming dielectric spacers, followed by ion-implantation of high-doped source/drain (HDD) regions of MOSFET devices; (e) forming an ohmic contact region on at least one selected area of each of said epitaxially grown heterojunction device layers; (f) forming a planarized dielectric layer over the entire substrate;and (g) forming a columnar metal interconnect layer on top of each selected area of said epitaxially grown heterojunction device layers.