Patent ID: 7978705

Claim:
A system, comprising: at least one bus; at least one external device comprising a graphics processing unit (GPU) and a memory controller; and a system on a chip (SOC) having one or more processor cores, a transmit buffer for holding packets of data to be sent from the one or more processor cores to the at least one external device over the bus, and self-healing link logic circuitry configured to: receive, from the at least one external device, a packet containing an expected sequence count for packets transmitted to the external device by the SOC and, if a current sequence count maintained by the SOC does not match the expected sequence count, adjust the current sequence count to match the expected sequence count by modifying one or more pointers in the transmit buffer, wherein modifying the one or more pointers comprises: setting a start pointer indicating an earliest packet of the packets in the transmit buffer that has been sent, but not acknowledged, to the same value as the expected sequence count; adjusting a free-next pointer indicative of a location in the transmit buffer containing an earliest packet of the packets that has been transmitted but not yet cleared from the transmit buffer; and once the free-next pointer has reached a send pointer indicative of a next packet to be sent, adjusting the free-next and send pointers together beyond the send pointer and not beyond the start pointer.