Patent ID: 8729662

Claim:
A semiconductor device comprising: a semiconductor substrate of a first general conductivity type; a semiconductor layer of a second general conductivity type disposed on the semiconductor substrate; an isolation region of the first general conductivity type formed in the semiconductor layer so as to surround and electrically isolate a portion of the semiconductor layer; a first depressed portion and a second depressed portion that are formed in the semiconductor layer of the second general conductivity type so as to be adjacent to the isolation region of the first general conductivity type but not in direct contact with the isolation region, the first depressed portion being disposed on one side of the isolation region, and the second depressed portion being disposed on another side of the isolation region, wherein a width of an upper end of the isolation region and a width of a lower end of the isolation region are smaller than a width of a center of the isolation region, and the first depressed portion and the second depressed portion include no metal wiring.