Patent ID: 6911856

Claim:
A clock distribution circuit comprising: a clock source to generate a clock signal; a clock divider to divide the clock signal and produce a divided clock signal, and including a flip-flop that introduces a first propagation delay to the divided clock signal; and a delay matching circuit to distribute the clock signal, and to introduce a second propagation delay to the clock signal, the second propagation delay substantially matching the first propagation delay introduced in the divided clock signal by the flip-flop, wherein the delay matching circuit includes: a multiplexer having a first input coupled to drive a first transmission gate, a second input coupled to drive a second transmission gate, a select input coupled to the clock source to selectively enable one of the transmission gates, and an output coupled to the first and second transmission gates, wherein the transmission gates are configured to correspond substantially to a slave transmission gate in the flip-flop; a PMOS transistor having a drain coupled to the first input, a gate coupled to ground, and a source coupled to a supply voltage, wherein the PMOS transistor is configured to correspond substantially to a PMOS transistor in a master output driver of the flip-flop; and an NMOS transistor having a drain coupled to the second input, a gate coupled to the supply voltage, and a source coupled to ground, wherein the NMOS transistor is configured to correspond substantially to an NMOS transistor in the master output driver of the flip-flop.