Patent ID: 6900541

Claim:
An integrated circuit comprising: a bondable metal pad defined on a stress-buffering dielectric layer; a damascened intermediate metal layer fabricated in a first inter-metal dielectric (IMD) layer that is under said stress-buffering dielectric layer, and said damascened intermediate metal layer being disposed directly under said bondable metal pad and electrically connected to said bondable metal pad through a plurality of via plugs integrated with said bondable metal pad; at least one electrically isolated damascened metal frame fabricated in a second IMD layer under said first IMD layer, said damascened metal frame, having four sides and dimensions corresponding to peripheral contour of overlying said intermediate metal layer exhibits ability in counteracting mechanical stress exerted on said bondable metal pad during bonding, being disposed directly under said damascened intermediate metal layer; and a portions of active circuit components of said integrated circuit disposed directly under said damascened metal frame.