Patent ID: 8271930

Claim:
A method of optimizing of a library for use in circuit design comprising: providing an initial circuit netlist; providing one or more sets of existing cells; providing one or more sets of additionally admissible cells, which are additional to the one or more sets of existing cells; using at least one computer processor, remapping the initial circuit netlist to find cells that reduce implementation costs considering the initially existing set of cells and the additional set of admissible cells to obtain a remapped netlist; and outputting the remapped netlist and one or more new cell library specifications and descriptions, wherein the additional set of admissible cells comprises a set of functionalities or cells which is implicitly defined by a maximum allowed number of switches in series in a general transistor implementation; and wherein the additional set of admissible functions is defined by an allowed number of switches in the exact lower bounds for the number of switches in series in both transistor plans to implement a logic function.