Patent ID: 7123062

Claim:
A power initialization circuit for a semiconductor memory device, comprising: a power supply voltage level follower unit to provide a bias voltage which varies linearly with a power supply voltage; a power supply voltage detection unit to detect when a level of the power supply voltage reaches a predetermined level to thereby generate a detection signal; and a reset prevention unit to generate a power-up signal to thereby prevent a logic level of the power-up signal from transitioning during a power drop of the power supply voltage having a duration less than or equal to a predetetermined period, wherein the reset prevention unit includes: a first pull-up means and a first pull-down means controlled by the detection signal; a delay unit for delaying the detection signal by a predetermined time; and a second pull-up means connected between the first pull-up means and a power supply voltage, and controlled by an output signal of the delay unit, wherein the power supply voltage detection unit includes: a load element connected between the power supply voltage and a first node; an NMOS transistor which is connected between a ground voltage and the first node and whose gate receives the bias voltage; and an inverter, which is connected to the first node, for outputting the detection signal.