Patent ID: 7319351

Claim:
A method for delaying a signal comprising: receiving an input signal at an input terminal of a delay locked loop, the delay locked loop including a first controlled delay circuit; delaying, using the delay locked loop, the input signal in accordance with a control signal to generate a first group of one or more delayed signals; receiving, at a control signal generator, the input signal and one of the first group of signals; providing substantially symmetric signal paths through logic units in the control signal generator for the received input signal and the one of the first group of signals; generating, using the control signal generator, the control signal in accordance with the received input signal and the one of the first group of signals; receiving, at a second controlled delay circuit, one of the first group of signals and the control signal; using the second controlled delay circuit, delaying the one of the first group of signals received at the second controlled delay circuit in accordance with the control signal to generate a second group of one or more delayed signals; and selecting one of the first group of signals and the second group of signals as a delayed output signal.