Patent ID: 8667196

Claim:
A method for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system, the system including a plurality of bus matrices for interfacing between the one or more slave devices and the at least one master device, the method comprising steps of: receiving an address map corresponding to the system; receiving information regarding connectivity of at least a subset of the one or more slave devices through at least one of the plurality of bus matrices; determining whether the at least one master device has more than one default slave unit associated therewith; and when the at least one master device has more than one default slave unit associated therewith: generating a first address mapping defining a correspondence between an address space utilized by the at least one master device and an address space utilized by a corresponding bus matrix that does not require a default slave unit; generating a second address mapping defining a correspondence between an address space utilized by the bus matrix that does not require a default slave unit and an address space used to access a corresponding one of the slave devices, such that an address generated by the at least one master device and an address seen by a corresponding one of the slave devices is the same; and configuring the system to have no more than one default slave unit per master device.