Patent ID: 8924824

Claim:
A solid-state storage device comprising: a non-volatile solid-state memory array comprising a plurality of non-volatile solid-state memory devices configured to store data; and a controller configured to generate multiple-bit log likelihood ratios (LLRs) associated with a memory location by at least: determining a reference bit stream stored in a reference memory location; performing a plurality of reads of the reference memory location, wherein each of the plurality of reads is performed at one of a plurality of voltage read levels; calculating 1-to-0 and 0-to-1 bit flip count data corresponding to each of the plurality of voltage read levels, the calculating based at least in part on the reference bit stream and bit values from the plurality of reads of the reference memory location; generating possible LLRs associated with the reference memory location based at least in part on the 1-to-0 and 0-to-1 bit flip count data; generating a sequence of LLRs based at least in part on the possible LLRs and on bit patterns from a multiple read operation on a target memory location; and decoding data from the target memory location using the generated sequence of LLRs.