Patent ID: 7737469

Claim:
A semiconductor device comprising: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode provided on a side opposite to the major surface of the semiconductor layer; a first semiconductor region of the second conductivity type selectively provided on the first semiconductor pillar region and the second semiconductor pillar region in a device central region; a second semiconductor region of the first conductivity type selectively provided in a surface of the first semiconductor region; a third semiconductor region of the second conductivity type provided in a boundary region between the device central region and an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region; a second main electrode provided in contact with the first semiconductor region, the second semiconductor region and the third semiconductor region; a control electrode provided on the first semiconductor region, the second semiconductor region, and the first semiconductor pillar region via an insulating film; and a high-resistance semiconductor layer provided on the semiconductor layer in the edge termination section, the high-resistance semiconductor layer having a lower dopant concentration than the first semiconductor pillar region, the first semiconductor pillar region and the second semiconductor pillar region being provided below the third semiconductor region in the boundary region and neither of the first semiconductor pillar region and the second semiconductor pillar region being provided in the edge termination section, and the first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region having a depth decreasing stepwise toward the edge termination section.