Patent ID: 7428653

Claim:
A method of pipelining data comprising: inputting to a logic circuit a first data set of a first thread on a rising edge of a first clock pulse; inputting to the logic circuit a first data set of a second thread on a falling edge of the first clock pulse; executing in the logic circuit the first data set of the first thread during the time between the rising and falling edges of the first clock pulse; moving the executed first data set signal of the first thread to a feedback node on the falling edge of the first clock pulse; inputting to the logic circuit a second data set from the first thread, together with the feed back data from the first data set signal of the first thread on a rising edge of the second, subsequent clock pulse; executing in the logic circuit the first data set of the second thread during the time between the falling and rising edges of the first and second clock pulses; moving the executed first data set signal of the second thread to a feedback node on the rising edge of the second clock pulse; and inputting to the logic circuit a second data set from the second thread, together with the feed back data from the first data set signal of the second thread on a falling edge of the second, subsequent clock pulse; outputting a completed first data set of the first thread to an output node on the rising edge of the second clock pulse.