Patent ID: 8138544

Claim:
A castellated-gate MOSFET tetrode device capable of fully depleted operation comprising: a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface; a source region, a drain region, as well as adjoined primary and secondary channel-forming regions disposed laterally between said source and drain regions, all of which are formed in said semiconductor substrate region; trench isolation insulator islands surrounding said source and drain regions as well as said primary and secondary channel-forming regions, and having upper and lower surfaces; said primary channel-forming region comprising a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along said device between said source and drain regions; said secondary channel-forming regions comprising a plurality of thin, spaced, vertically-orientated conductive channel elements that are positioned longitudinally between said primary channel-forming region and said drain and/or said source regions; a first gate structure in the form of a first plurality of spaced, castellated gate elements interposed between said primary channel elements, and a first top gate member interconnecting said first gate elements at their upper vertical ends to cover said primary channel elements; one or two second gate structures in the form of second pluralities of spaced, castellated gate elements interposed between said secondary channel elements, and one or two second top gate members interconnecting said second gate elements at their upper vertical ends to cover said secondary channel elements; a first dielectric layer separating said primary conductive channel elements from said first gate structure; and a second dielectric layer separating said secondary conductive channel elements from said second gate structure.