Patent ID: 8504802

Claim:
An apparatus comprising: a decode unit, of a hardware implementation, capable of decoding instructions of a legacy first instruction set and of a new second instruction set, said decode unit to receive a vector instruction of a format including an opcode field identifying an opcode and one or more operand type specifier fields identifying a set of operands; wherein the presence of a first plurality of fields including one or more predefined prefixes or existing escape codes used as part of said legacy first instruction set identifies the vector instruction as one of a first type, and wherein the presence of a second plurality of fields including a new escape code and one or more payload bytes used as part of said new second instruction set identifies the vector instruction as one of a second type; said decode unit to decode the opcode field into signals to carry out the operations prescribed by the opcode, and said one or more operand type specifier fields and said one or more payload bytes to comprise one or more new features for the opcode including an extra register operand address responsive to the vector instruction being identified as one of the second type, but said one or more operand type specifier fields not to include an extra register operand address responsive to the vector instruction being identified as one of the first type.