Patent ID: 7305517

Claim:
A structure of sequencers for handling differing types of initial and periodic calibrations of at least one of a plurality of memory channels for busses associated with a Dynamic Random Access Memory (DRAM) controller for memory systems, comprising: a first half DRAM controller; a second half DRAM controller identical to the first half controller; at least one of the controller halves interfacing at least one of the plurality of memory channels; and at least one of a plurality of sequencers is associated with at least one of the controller halves for handling differing types of a plurality of calibrations, wherein at least one of the plurality of sequencers is a current/impedance calibration sequencer; wherein each current/impedance calibration sequencer further comprises: at least one pathway that is configured to handle input/output cell current and termination calibrations; at least one pathway that is at least configured to handle DRAM termination impedance calibrations; and at least one pathway that is at least configured to handle DRAM current calibrations.