Patent ID: 8441063

Claim:
A memory array comprising: a plurality of bit lines; and a plurality of word lines including a first word line and a second word line, wherein said first word line comprises a first gate region adjacent to a first charge trapping layer and adjacent to a first spacer, wherein said second word line comprises a second gate region adjacent to a second charge trapping layer and adjacent to a second spacer, each of said first and second charge trapping layers comprising a nitride layer and each of said first and second charge trapping layers between a first oxide layer and a second oxide layer, wherein said first charge trapping layer is wider than said first word line and said second charge trapping layer is wider than said second word line, wherein further the region between said first and second spacers and said first and second charge trapping layers is filled with dielectric material, said memory array further comprising an oxide region formed on each end of the nitride layers of said first and second charge trapping layers, wherein said oxide region does not extend beyond the edges of said nitride layers to said first oxide layer and to said second oxide layer, wherein said dielectric material that fills said region between said first and second spacers is in contact with said first and second oxide layers but not said nitride layers.