Patent ID: 8074142

Claim:
A decoding apparatus that decodes pseudo cyclic low density parity check codes in error correction coding and outputs an estimated transmission bit sequence which is the result of decoding, said apparatus comprising: variable-to-check message generating means including a plurality of feedback shift registers of a predetermined number of stages including a plurality of registers; said variable-to-check message generating means receiving a sequence of received data, generating and outputting a variable-to-check message and an estimated transmission bit sequence; said variable-to-check message comprising data inclusive of a sum of a log likelihood ratio and an a-priori value; check-to-variable message generating means including a plurality of feedback shift registers of a preset number of stages including a plurality of registers; said check-to-variable message generating means outputting, on receipt of the variable-to-check message, output from said variable-to-check message generating means, a check-to-variable message including data generated responsive to said variable-to-check message received; and normalization processing means that multiplies preset data included in said check-to-variable message output by said check-to-variable message generating means with a preset constant and outputs the resulting product to said variable-to-check message generating means; wherein said variable-to-check message generating means includes variable-to-check processing means that sums data corresponding to an output of said check-to-variable message generating means to preset data out of data retained in the registers of said feedback shift register included in said variable-to-check message generating means, saves the resulting sum in the next stage register, and outputs at a preset timing, the estimated transmission bit sequence and a variable-to-check message including data retained in said register; and wherein said check-to-variable message generating means includes check-to-variable processing means that selects two data out of the data retained by said registers of said feedback shift register of said check-to-variable message generating means, and data of the smallest value and data of the second smallest value out of the data output by said variable-to-check processing means, saves the data selected in the next stage register and outputs the data retained in said register at a preset timing as check-to-variable message; said variable-to-check message generating means being arranged between the registers of said feedback shift register of said check-to-variable message generating means; said check-to-variable message generating means being arranged between the registers of said feedback shift register of said check-to-variable message generating means.