Patent ID: 8095765

Claim:
A memory controller, comprising: control circuitry coupled to one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes, and wherein the control circuitry is configured to: determine defective physical blocks within the planes; if none of the physical blocks at a particular block position are determined to be defective, assign the physical blocks at the particular block position to a super block; and if one or more of the physical blocks at a particular block position are determined to be defective: assign the physical blocks at the particular block position that were not determined to be defective to a super block; and assign a respective replacement physical block to the super block for each of the one or more physical blocks at the particular block position that were determined to be defective; wherein the respective replacement physical block is selected from a number of physical blocks within a respective one of the planes that includes a respective physical block that was determined to be defective.