Patent ID: 8525349

Claim:
A semiconductor package, comprising: a first package including a first substrate and at least one semiconductor chip mounted on the first substrate; a redistribution wiring layer disposed above the first package and including a connection pad, a bonding pad electrically connected to the connection pad and a dummy bonding pad electrically connected to the bonding pad; a second package stacked on the first package via the redistribution wiring layer and electrically connected to the connection pad through a first connection member; a bonding wire extending from the bonding pad to a substrate pad disposed on an upper surface of the first substrate of the first package, wherein the bonding wire is connected to the substrate pad and electrically connects the bonding pad to the first substrate; and a dummy bonding wire extending from the dummy bonding pad to a dummy substrate pad disposed on the upper surface of the first substrate of the first package, wherein the dummy bonding wire is connected to the dummy substrate pad and electrically connects the dummy bonding pad to the first substrate, and wherein the dummy bonding wire is electrically connected to the bonding wire throw the dummy bonding pad and the bonding pad to provide a closed dummy circuit.