Patent ID: 7227394

Claim:
A signal synchronizer comprising: a delay register adapted to receive a feedback signal, wherein said delay register comprises delay circuits; and a storage register adapted to receive a reference signal, wherein said storage resister comprises a series of storage devices, and wherein each storage device is adapted to store a feedback signal state of a corresponding one of said delay circuits, wherein said delay circuits are adapted to delay said feedback signal at different time intervals, and wherein said storage devices are adapted to simultaneously store feedback signal states of said delay circuits; buffers respectively connected to said delay register and said storage register; and a control subsystem connected to said storage register and said delay register, wherein said control subsystem is adapted to output said feedback signal to said delay register and, to adjust a phase of said feedback signal supplied to said delay register based on a position of a phase transition storage device within said storage register, wherein, within said storage register, all storage devices on one side of said phase transition storage device have a first signal state and all storage devices on the other side of said phase transition storage device have a second signal state, different than said first signal state, and wherein said buffers delay said feedback signal and said reference signal in such a manner that if said reference signal and said feedback signal are synchronized, a change in feedback signal state will occur at a middle delay device and be recorded in a middle storage device.