Patent ID: 7054402

Claim:
A data regenerator, comprising: a phase comparator; a clock regenerator, the clock regenerator and the phase comparator serving to recover a clock signal from a binary input signal; a controller; a first sampling device for sampling the binary input signal, serving as an operating sampling device, having a decision threshold and a sampling time instant which are set by the controller without interfering with the clock signal; a second sampling device for sampling the binary input signal, serving as a measurement sampling device, having an independently adjustable sampling time instant and an independently adjustable decision threshold that are varied by the controller without interfering with the clock signal; and a comparator circuit connected to the first and second sampling devices for bit-by-bit comparison of sampled binary signals from the first and second sampling devices; wherein the controller varies the respective decision thresholds and the sampling time instants of the first and second sampling devices relative to the clock signal, based on the comparison values obtained in the process, and optimizes the decision threshold and the sampling time instant of the first sampling device.