Patent ID: 7284141

Claim:
An apparatus for sampling an input signal, wherein the apparatus receives a clock signal synchronous with the input signal, the apparatus comprising: a synthesizer for receiving the synchronous clock signal, wherein the synthesizer produces a synthesized signal having a synthesized signal frequency dependent on the synchronous clock signal; a sampling module coupled to the synthesizer, wherein the sampling module samples the input signal based on the synthesized signal frequency; and a processing unit coupled to the sampling module, wherein the processing unit analyzes a sampled point from the sampling module and arranges the sampled point in an eye diagram; wherein the synthesized signal frequency F DDS is programmed as the function F DDS = 1 R · ( N N + 1 ) ⁢ F CLK wherein R is an integer, N is an amount of sample points per unit interval and F CLK is the clock frequency of the synchronous clock signal or a frequency scaled from the synchronous clock signal; and wherein the eye diagram is formed by arranging an x-coordinate of a particular sample point using the function: x ( i )=mod( R·C·i, N ) wherein C is the predetermined number of counts and i is the particular sample point.