Patent ID: 7994847

Claim:
A bias signal circuit, comprising: a first current branch comprising a first cascode transistor, and a constant current source connected in series with the first cascode transistor; a second current branch comprising a second cascode transistor with a channel width-to-length ratio that is approximately 4 times a channel width-to-length ratio of the first cascode transistor, a gate of the first cascode transistor and a gate of the second cascode transistor being connected to a common node, a short channel mirror device transistor connected in series with the second cascode transistor, and a trim resistor connected in series between the second cascode transistor and the short channel mirror device transistor; and an operational amplifier, a first input node of the operational amplifier connected between the trim resistor and the short channel mirror device transistor at a drain terminal of the short channel mirror device transistor, a second input node of the operational amplifier connected between the first cascode transistor and the constant current source, and an output node connected to a gate terminal of the short channel mirror device transistor.