Patent ID: 8554984

Claim:
A memory system comprising: a nonvolatile memory including a plurality of blocks, each one of the plurality of blocks being a data erasing unit and including a plurality of pages, each one of the plurality of pages being a data programming or reading unit; and a controller configured to: receive logical addresses in association with a read request provided by a host apparatus; retrieve information associated with physical addresses of the nonvolatile memory by searching a first address management table with the logical addresses; readout data from at least one of the plurality of pages indicated by the information associated with the physical addresses of the nonvolatile memory; retrieve information associated with the logical addresses by searching a second address management table with the physical addresses of the nonvolatile memory; and determine a first block including a plurality of invalid data, specify valid data stored in the first block by using the second address management table, and copy valid data stored in the first block to a second block, wherein the first address management table is managed with a first management unit smaller than a size of one page and a second management unit larger than a size of one page and smaller than a size of one block, the second address management table is managed with the first management unit and the second management unit, and the first address management table and the second address management table are linked with each other by information corresponding to the same data.