Patent ID: 8748268

Claim:
A method for fabricating a MOSFET integrated with Schottky diode (MOSFET/SKY), expressed in an X-Y-Z Cartesian coordinate system with the X-Y plane parallel to its major semiconductor chip plane, comprising: a) forming, in an epitaxial layer overlaying a semiconductor substrate, a gate trench and depositing gate material therein; b) forming a body region in the epitaxial layer, a source region atop the body region and a dielectric region atop the gate trench and the source region; c) etching a top contact trench (TCT) with vertical side walls defining a Schottky diode cross-sectional width SDCW: c1) through the dielectric region and the source region thus defining a source-contact depth (SCD); and c2) partially into the body region by a predetermined total body-contact depth (TBCD); d) creating: d1) into the side walls of the TCT and beneath the SCD, a heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD; and d2) into a sub-contact trench zone (SCTZ) beneath the floor of the TCT, an embedded Shannon implant region (ESIR); and e) forming a metal layer: e1) in contact with the ESIR, the body region and the source region; and e2) filling the TCT and covering the dielectric region whereby completing the MOSFET/SKY with only one-time etching of its TCT.