Patent ID: 8198936

Claim:
A semiconductor device comprising: a first demodulation circuit having an output portion; a second demodulation circuit having an output portion; a first bias circuit having a first input portion, a second input portion, and an output portion; a second bias circuit having a first input portion, a second input portion, and an output portion; a comparator having a first input portion, a second input portion, and an output portion; an analog buffer circuit having an input portion and an output portion; and a pulse detection circuit having an input portion, a first output portion, and a second output portion, wherein the output portion of the first demodulation circuit is electrically connected to the first input portion of the first bias circuit, wherein the output portion of the second demodulation circuit is electrically connected to the first input portion of the second bias circuit, wherein the second input portion of the first bias circuit is electrically connected to the first output portion of the pulse detection circuit, wherein the second input portion of the second bias circuit is electrically connected to the second output portion of the pulse detection circuit, wherein the output portion of the first bias circuit is electrically connected to the first input portion of the comparator, wherein the output portion of the second bias circuit is electrically connected to the second input portion of the comparator, wherein the output portion of the comparator is electrically connected to the input portion of the analog buffer circuit, and wherein the output portion of the analog buffer circuit is electrically connected to the input portion of the pulse detection circuit.