Patent ID: 7519525

Claim:
A method of simulating a logic circuit comprising running a central electronic core simulator in a high level simulator up whereby to create a post-initial microcode load state, and thereafter transferring the post-initial microcode state from the central electonic core simulation to a post-initial microcode state from the central electronic core simulation to a post-initial microcode load co-simulator model to simulate the logic circuit comprising the steps of: running an initial microcode load in a first configuration in the high level simulator that parallels the post-initial microcode load state in a post-initial microcode cosimulator environment, wherein the initial microcode load initializes the simulated logic circuit and loads firmware to support code execution using the simulated logic circuit; creating a snapshot of the post-initial microcode load state in the high level simulator of all micro-architected facilities, a Hardware System Area, and associated data areas in memory in response to completing the initial microcode load; superimposing the processor post-initial microcode load state onto the post-initial microcode load cosimulation hardware model using simulator API commands, and loading the registers into the model along with associated error correcting code (ecc) and parity to update the model state to run on a co-simulator; and loading the Hardware System Area data into a memory section of the post-initial microcode load cosimulator model; inserting a new program status word (PSW) for a test case; asserting a notification that a restart is requested; retrieving the new PSW in response to applying a clock to the post-initial microcode load cosimulator model; and beginning post-initial microcode load cosimulator model execution on the co-simulator at an instruction address that points to the test case.