Patent ID: 8074154

Claim:
An (n, k) cyclic code encoder (the Encoder), comprising: an input data signal configured to receive M message symbols from an external host per cycle, wherein the M message symbols form the Symbol Vector, wherein M is a positive integer; a vector table configured to output a set of pre-calculated IR Vectors; a register unit configured to latch the output vector of a arithmetic unit at the end of each cycle, wherein the register unit content may be cleared to zero by a reset mechanism such as an input reset signal, wherein the upper M symbols in the register unit form the Register Coefficient Vector and the rest of the register unit content shifted higher by M symbols form the Register Feedback Vector; the arithmetic unit configured to perform an addition of the Symbol Vector and the Register Coefficient Vector in each cycle, wherein the sum of said addition forms the Adder Coefficient Vector, the arithmetic unit further configured to perform a linear combination of the IR Vectors and the Register Feedback Vector in each cycle, wherein, in said linear combination, each IR Vector is multiplied by a coefficient which is a corresponding symbol in the Adder Coefficient Vector and the Register Feedback Vector is multiplied by a coefficient equal to one, wherein the sum of said linear combination is the output vector of the arithmetic unit; and an output data signal configured to output the content of the register unit as the output of the Encoder.