Patent ID: 8178904

Claim:
A gate array comprising: a plurality of unit cells, the unit cells arranged in parallel on a semiconductor substrate and each having a same pattern including a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor each including a gate, a source and a drain, the gate of the first MOS transistor and the gate of the second MOS transistor being connected by gate wiring, with the gate wiring having a first gate terminal portion and a second gate terminal portion; a plurality of metal wiring lines on the unit cells with an insulating layer there between; and a plurality of contacts, that make electrical connections between the metal wiring lines and the first gate terminal portions, the second gate terminal portions, the sources or the drains, wherein in one of the unit cells neither the first MOS transistor nor the second MOS transistor is being used, and there is one of the plurality of contacts at each of the first gate terminal portion and at the second gate terminal portion, wherein the unit cells also have a source potential region and a ground potential region, and the source and the drain of the one of the first MOS transistors that is not being used together with the source and the drain of the one of the second MOS transistors that is not being used are connected to the source potential region or the ground potential region, and wherein the gate wiring between the one of the first MOS transistors and the one of the second MOS transistors that are not being used provides connection between the plurality of unit cells.