Patent ID: 8509021

Claim:
A processor-based system comprising: a processing apparatus operable to process data and to provide memory requests and addresses; a plurality of memory devices; a system controller in communication with the processing apparatus, the system controller operable to receive and transmit memory commands, addresses and data, and to receive memory requests corresponding to a first region of one or more of the plurality of memory devices, the system controller operable to communicate the memory requests to the one or more of the plurality of memory devices and transmit memory data from the one or more of the plurality of memory devices in response to at least one of the memory requests; and a selection block configured to receive the memory requests corresponding to the first region of the one or more of the plurality of memory devices and to receive an input signal indicating a number of defective cells that are replaced by redundant cells in at least one region of the one or more of the plurality of memory devices selectable by the selection block relative to that of at least another region of the one or more of the plurality of memory devices selectable by the selection block, the selection block operable to map the memory requests to a second region of the one or more of the plurality of memory devices based on the input signal; wherein the processing apparatus is configured to: access a first memory device of the plurality of memory devices in response to a first memory request; and access a second memory device of the plurality of memory devices in response to a second memory request, the first memory request preceding the second memory request; and wherein: the access of the second memory device occurs substantially contemporaneously with the access of the first memory device; and the input signal is associated with at least one of the first and the second memory requests.