Patent ID: 7772891

Claim:
A circuit comprising: a pulse generating circuit to generate at least a first logic signal, said pulse generating circuit comprising a first logic gate circuit to generate a first logic gate output signal based, at least in part, on a first evaluation node signal, a second evaluation node signal and a scan enable signal, and a second logic gate circuit to generate said first logic signal based, at least in part, on said first evaluation node signal and a clock signal; and a discharge path circuit coupled to said pulse generating circuit, said discharge path circuit comprising at least a first transistor within a first stack of transistors, said first transistor being operatively responsive to said first logic signal, said discharge path circuit further comprising at least a second transistor within a second stack of transistors, said second transistor arranged in series with said first transistor, and wherein said first evaluation node signal is selectively discharged via a path through both said first and second transistors.