Patent ID: 6880117

Claim:
A testing system comprising: a timing generator constructed to generate a clock signal that is to be provided as an input timing signal to a memory device under test; a pattern generator configured to produce an address signal; and a waveform shaping circuit operatively coupled to the pattern generator, the waveform shaping circuit being constructed to receive the address signal from the pattern generator and to provide the address signal to the memory device synchronized to every x cycles of the clock signal wherein x is greater than 1: wherein during a data read and compare generator, the pattern generator and the waveform shaping circuit are configured to: (i) produce a control signal, a strobe signal, and expected data, wherein the control signal directs the memory device to provide stored data at an address specified by the address signal, and (ii) provide the control signal to the memory device along with the address signal; wherein the wave form shaping circuit provides the address signal to the memory device for x cycles of the clock signal; wherein the testing system produces the strobe signal during only one cycle of the x cycles of the clock signal; wherein x is an integer; and wherein the testing system is configured to first perform the read and compare operation for even addresses in an address space of the memory device, and to then perform the read and compare operation for odd addresses in the address space of the memory device.