Patent ID: 7204914

Claim:
A system for controlling a processor, comprising: at least one sampling port connected to a stage of said processor and configured to sample a reactant product from the processor; a controller having inputs that provide measurements of the at least one property of the reactant product and that provide a target value for the at least one reactant property; said controller having error calculation units configured to compare the at least one reactant property to the target value in need to control at least one processing parameter of the processor based on measurements of the at least one property of the reactant product such that changes to the at least one processing parameter maintain-the target value for said at least one property of the reactant product; and a dead time compensator included in said controller and including a process evaluator configured to evaluate said at least one property to determine if said at least one effect has been realized at a plurality of sequential times offset from a dead time wherein said dead time relates to a time before at least one effect of at least one of said changes to the at least one processing parameter is fully realized in said at least one property of the reactant product, wherein the dead time compensator comprises: (i) a plurality of sequential delay circuits connected in parallel and configured to offset said dead time by a fixed time interval, (ii) a plurality of comparators connected in series to respective ones of the sequential delay circuits and configured to compare, at said dead time and at fixed time intervals from said dead time, responses of the digester to said changes, and (iii) an evaluator configured to receive outputs from the plurality of comparators and to evaluate if said at least one effect is realized and to output a subsequent change for said at least one processing parameter.