Patent ID: 8076199

Claim:
A method of fabricating polysilicon lines of a memory, comprising: forming a layered stack on a core section and a peripheral section of a substrate, wherein the layered stack includes a charge trapping component that is positioned on the core section and the peripheral section, and a core polysilicon layer that is positioned on the charge trapping component; removing a portion of the layered stack that is located at the peripheral section, wherein removing the layered stack from the peripheral section includes removing the core polysilicon layer from the peripheral section; forming a peripheral polysilicon layer on the peripheral section and the layered stack of the core section such that the peripheral polysilicon is thicker than the core polysilicon layer; removing a portion of the peripheral polysilicon layer that is located on the layered stack of the core section; and patterning individual polysilicon lines in the layered stack of the core section.