Patent ID: 8023521

Claim:
A hierarchical packet-buffering system of memory structures for processing packets in a network, the network having a network bandwidth, the system comprising: a first memory including one or more first packet buffers configured to receive data packets from the network, each of the one or more first packet buffers having a first packet-buffer bandwidth and a first packet-buffer depth, wherein a sum of first packet-buffer bandwidths is equal to or greater than the network bandwidth; and a second memory different from the first memory and including one or more second packet buffers configured to receive packets from at least one of the one or more first packet buffers, each of the one or more second packet buffers having a second packet-buffer bandwidth and a second packet-buffer depth and being organized as a plurality of queues, each of the plurality of queues being configurable, by a configuration parameter stored in memory, to independently operate in one of a fairness-based mode and a priority based-mode, wherein a sum of the second packet-buffer depths is equal to or greater than a sum of first packet-buffer depths of the at least one of the one or more first packet buffers and a sum of the second packet-buffer bandwidths is equal to or greater than a sum of first packet-buffer bandwidths of the at least one of the one or more first packet buffers.