Patent ID: 7851846

Claim:
An electrically programmable and erasable memory device comprising: a substrate of semiconductor material having a first conductivity type and a surface; a trench formed into the surface of the substrate; first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region in the substrate there between, wherein the second region is formed under the trench, and the channel region includes a first portion that extends substantially along a bottom wall of the trench, a second portion that extends substantially along a sidewall of the trench, and a third portion that extends substantially along the surface of the substrate; an electrically conductive floating gate disposed over and insulated from the channel region third portion for controlling a conductivity of the channel region third portion; an electrically conductive control gate disposed adjacent to and insulated from the floating gate; an electrically conductive select gate at least partially disposed in the trench and adjacent to and insulated from the channel region first and second portions for controlling a conductivity of the channel region first and second portions; and an electrically conductive erase gate disposed adjacent to and insulated from the floating gate.