Patent ID: 8847329

Claim:
An integrated circuit, comprising: a first conductive gate level feature forming a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, the first conductive gate level feature providing an electrical connection between the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type; a second conductive gate level feature forming a gate electrode of a second transistor of the first transistor type; a third conductive gate level feature forming a gate electrode of a second transistor of the second transistor type, wherein the gate electrodes of the first and second transistors of the first transistor type and of the first and second transistors of the second transistor type extend lengthwise in a parallel direction, wherein lengthwise centerlines of the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type are substantially aligned in the parallel direction, wherein the second and third gate level features are positioned on opposite sides of the first gate level feature, wherein the first and second transistors of the first transistor type are formed by diffusion regions of a first diffusion type, and the first and second transistors of the second transistor type are formed by diffusion regions of a second diffusion type, the diffusion regions of the first diffusion type collectively separated from the diffusion regions of the second diffusion type by a non-diffusion region, wherein each of the first and second transistors of the first transistor type and the first and second transistors of the second transistor type has a respective diffusion region electrically connected to a common node; a first conductive contacting structure connected to the second conductive gate level feature at a location not over the non-diffusion region; and a second conductive contacting structure connected to the third conductive gate level feature at a location not over the non-diffusion region, the third conductive gate level feature electrically connected to the second conductive gate level feature through the first and second conductive contacting structures, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.