Patent ID: 7484019

Claim:
A serial-connection and parallel-communication fast interface, comprising: a Programmable Logic-Controller (PLC) host comprising an external connector unit and a first microprocessor; and at least one expansion device comprising at least one connector connected to the PLC host and another expansion device; wherein the PLC host and the at least one expansion device are connected in a serial-connection and parallel-communication manner, which is established by address lines, data lines, control lines and I/O addressing lines of a shared bus connected between the PLC host and the at least one expansion device; and wherein the at least one expansion device automatically assigns the order thereof and automatically allows or prohibits data accessing of the PLC host according to clamping values sent through the I/O addressing lines, and the at least one expansion device further comprises; a second microprocessor; a memory unit connected to address lines, data lines and control lines of the first microprocessor and address lines, data lines and control lines of the shared bus; and a clamping and decoding circuit connected to output addressing lines of the I/O addressing lines to get one clamping value of the at least one expansion device of previous stage and converting the clamping value for sending to the at least one expansion device of next stage through output addressing lines of the I/O addressing lines, the clamping and decoding circuit deciding whether the PLC host is connected to the memory unit and the data lines thereof are activated for date accessing according to the clamping value from input addressing lines, wherein the clamping and decoding circuit comprises a clamping circuit and a decoding circuit, and the clamping circuit comprises a sum circuit, a first logic circuit and a second logic circuit, the sum circuit receives the clamping values sent from the output addressing lines of the PLC host or the at least one expansion device of the previous stage and an output enable level signal from the PLC host to output another clamping value to the at least one expansion device of the next stage, the signals of the input addressing lines are processed by the first logic circuit to form input signal of the second logic circuit, the output of the PLC host or the input enable level signal of the at least one expansion device of the previous stage is processed by the second logic circuit to generate another output enable level signal which is an input enable level signal for the at least one expansion device of the next stage.