Patent ID: 7343573

Claim:
A method for performing verification of an electronic design, said method comprising: receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers; generating a binary decision diagram analysis of said design, wherein said step of generating a binary decision diagram analysis of said design includes: declaring a first set of one or more binary decision diagram variables corresponding to one or more of said one or more registers in said first register set and one or more inputs in said primary input set; building a first binary decision diagram for said first target set over said first set of one or more binary decision diagram variables; and declaring a second set of one or more binary decision variables corresponding to one or more of said one or more registers in said first register set and one or more inputs in said primary input set corresponding to one or more of said one or more registers in said first register set at one or more variable initial values and one or more inputs in said primary input set at variable initial values; performing a recursive extraction of one or more next states of selected registers in said first register set using said binary decision diagram analysis of said first target set and said primary input set; decomposing said recursive extraction to generate a second target set; and verifying said second target set.