Patent ID: 8468287

Claim:
An information processor comprising: a plurality of master cores that are arithmetic devices capable of programmed operation; a plurality of slave cores that are peripheral devices of the master cores; a plurality of slave adapters connected to each of said plurality of slave cores; and an interconnected network for connecting said master cores and said slave adapters by way of a plurality of router nodes; wherein: said slave adapters compare a first access request transmitted by a first master core among said plurality of master cores and a second access request transmitted by a second master core other than said first master core among said plurality of master cores based on a request from said first master core and a request from said second master core; when said first access request and said second access request match, transmit said first access request or said second access request to the slave core that is connected to the slave adapter; and transmit an error response to said first master core and said second master core when said first access request and said second access request do not match.