Patent ID: 7359257

Claim:
A semiconductor memory module comprising: a circuit substrate; a first, a second, a third and a fourth rank of memory chips each rank including a plurality of memory chips and each being disposed on said circuit substrate; a first register and a second register each disposed on said circuit substrate, said first register and said second register each comprising: a first input for receiving a chip select signal having one of an active or an inactive level; a second input for receiving a other chip select signal having one of an active or an inactive level; at least one third input for receiving command/address signals; a first output coupled to transmit said chip select signal to said memory chips of said first rank and said third rank; a second output coupled to transmit said other chip select signal to said memory chips of said second rank and said fourth rank; at least one third output, wherein said at least one third output of said first register is coupled to transmit said command/address signals to said memory chips of said first rank and to said memory chips of said second rank, if at least one of said chip select signal received at said first input of said first register and said other chip select signal received at said second input of said first register is active, and to block a transmission of said command/address signals to said memory chips of said first rank and to said memory chips of said second rank, if both said chip select signal received at said first input of said first register and said other chip select signal received at said second input of said first register are inactive; and said at least one third output of said second register is coupled to transmit said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if at least one of said chip select signal received at said first input of said second register and said other chip select signal received at said second input of said second register is active, and to block a transmission of said command/address signals to said memory chips of said third rank and to said memory chips of said fourth rank, if both said chip select signal received at said first input of said second register and said other chip select signal received at said second input of said second register are inactive.