Patent ID: 8062947

Claim:
A semiconductor device manufacturing method comprising: forming a gate electrode via a gate insulating film in each of a memory unit and a logic unit on a semiconductor substrate; covering the gate electrodes and a top surface of the substrate with a cover film; removing the cover film formed on the top surface of the substrate from at least one side of the gate electrode of a first transistor of the memory unit which is to form a shared contact and from both sides of the gate electrode of a second transistor of the logic unit which is to cause distortion in a channel region; forming grooves in the substrate by etching a top surface part of the substrate using the cover film as a mask; removing the cover film formed on the gate electrode from at least one of sidewall surfaces of the gate electrode of the first transistor; filling each of the grooves provided in the substrate with a semiconductor layer by epitaxially growing the semiconductor layer in each of the grooves such that the epitaxial growth reaches said at least one sidewall surface of the gate electrode of the first transistor to electrically connect said at least one sidewall surface of the gate electrode of the first transistor and the substrate; and forming a source/drain region in one of the top surface part of the substrate and the semiconductor layer using the gate electrode as a mask.