Patent ID: 7642583

Claim:
A ferroelectric memory device comprising a plurality of memory cells, each memory cell of the plurality of memory cells including a respective memory cell transistor and a respective memory cell capacitor, and the plurality of memory cells being arranged in a matrix along a first direction and along a second direction that is perpendicular to the first direction, wherein each respective memory cell capacitor of the plurality of memory cells comprises: a lower electrode connected to a bit line via the respective memory cell transistor; a ferroelectric layer formed on an upper surface of the lower electrode and having a width direction that is the same as a width direction of the lower electrode; and an upper electrode formed on an upper surface of the ferroelectric layer and having a width direction that is the same as the width direction of the lower electrode, wherein the lower electrode of each respective memory cell capacitor is independent from the lower electrodes of other memory cell capacitors, such that each respective memory cell capacitor includes a separate lower electrode, wherein each respective upper electrode of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction forms a continuous plate electrode covering only the respective independent lower electrodes of each respective memory cell capacitor of the plurality of memory cells that are only arranged along the second direction, and wherein the width of each respective upper electrode in the first direction is narrower than the width of each respective ferroelectric layer in the first direction.