Patent ID: 7555610

Claim:
A cache memory, comprising: an addition unit which adds, to each cache entry holding line data, a caching termination attribute indicating whether or not caching of the cache entry is allowed to be terminated; a selection unit which selects a cache entry that has been added with a caching termination attribute indicating that caching is allowed to be terminated, and has been set with a dirty flag indicating that the cache entry has been written into; and a write back unit which writes back, to a memory, line data of the selected cache entry, regardless of an occurrence of a cache miss, a holding unit which holds an address range specified by a processor, said holding unit being configured as a register that can be accessed by the processor through an instruction; a search unit which searches for a cache entry holding line data within the address range held in said holding unit; and a setting unit which sets, to the searched-out cache entry, the caching termination attribute indicating that caching is allowed to be terminated, while said cache memory is not being accessed by the processor; wherein storing of the address range in said holding unit is performed according to a data transfer instruction for transferring data to said holding unit.