Patent ID: 7236037

Claim:
Circuitry comprising a delay loop having: a first device adapted to generate a first clock signal based on an input clock signal; a second device adapted to generate a second clock signal based on the input clock signal; and a plurality of sequentially arranged delay elements, each delay element connected to receive the first and second clock signals and adapted to generate a corresponding output clock signal, wherein: the delay loop is adapted to control (1) the generation of the first and second clock signals by the first and second devices and (2) selection of one of the first and second clock signals for injection into one of the delay elements, such that, when a currently selected clock signal is generated by an on-line one of the first and second devices, the other device is off-line; and the delay loop is adapted to use the off-line device to generate a next clock signal to be injected into one of the delay elements.