Patent ID: 7215269

Claim:
An analog-to-digital converter, comprising: a delta-sigma modulator having a first terminal adapted to receive an analog signal, and a plurality of second terminals for providing a multi-bit digital output signal, the delta-sigma modulator comprising: a loop filter having a plurality of serially coupled integrators, and a multi-bit quantizer coupled to the loop filter; the multi-bit quantizer comprising an analog-to-digital converter (ADC) operable to produce the multi-bit digital output signal, the ADC coupled to a digital-to-analog converter (DAC) having dual DAC feedback loops, and a dynamic element matching function; a first digital decimation filter coupled to the plurality of second terminals of the delta-sigma modulator to receive the multi-bit digital output signal, the first digital decimation filter operable to provide an output In accordance with the relation: y 1 ⁡ ( m ) = ∑ t = 0 L 1 - 1 ⁢ h 1 ⁡ ( t ) · x ⁡ ( 4 ⁢ ⁢ m - t ) where the first digital decimation filter coefficients are represented as h 1 (t), 0≦t≦L−1; a second digital decimation filter coupled to the first digital decimation filter, the second digital decimation filter operable to provide an output In accordance with the relation: y 3 ⁡ ( m ) = ∑ t = 0 L3 - 1 ⁢ h 3 ⁡ ( t ) · y 2 ′ ⁡ ( 2 ⁢ ⁢ m - t ) where the second digital decimation filter coefficients are represented as h 3 (t), 0≦t≦L 3 −1; wherein the loop filter comprises five serially coupled integrators, and further include a first feedback path between an output of the fifth integrator and an input of the fifth integrator, and a second feedback path between an output of the third integrator and an input of the third integrator.