Patent ID: 7516427

Claim:
A methodology for characterization of an IP (Intellectual Property) component, comprising: recognizing input pins among digital pins; classifying first layers of the IP component based on the input pins, wherein the first layers are first circuit stages of the IP component; extracting second layers of the IP component, wherein the second layers are second circuit stages of the IP component; simulating the IP component based on the first and second layers of the IP component; and generating an IP library, wherein one of the first layers and one of the second layers corresponding to each other are recognized as both inverters if the input pin corresponding to the one of the first layers is connected to a gate terminal of the one of the first layers, and the one of the first layers and the one of the second layers corresponding to each other are recognized as a transmission gate and a capacitor respectively if the input pin corresponding to the one of the first layers is connected to one of source and drain terminals of the one of the first layers.