Patent ID: 8537602

Claim:
A memory device of SRAM type integrated in a chip of semiconductor material, the memory device including a plurality of memory cells each for storing a binary data having a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage, wherein each memory cell includes a bistable latch having a main terminal and a complementary terminal, each bistable latch including cross-coupled inverters and each cross-coupled inverter including a field effect main storage transistor and a field effect complementary storage transistor, the field effect main storage transistors coupled to the main terminal for maintaining the main terminal at the reference voltage corresponding to the stored logic value or to a complement thereof, the field effect complementary storage transistors coupled to the complementary terminal for maintaining the complementary terminal at the reference voltage corresponding to the complement of the logic value associated with the main terminal, and a field effect access transistor for accessing the main terminal, and wherein the chip includes an isolated well, the access transistor and at least one of the complementary storage transistors being formed in the isolated well.