Patent ID: 7360068

Claim:
A dynamically reconfigurable processing unit comprising: a system bus; a microprocessor coupled to said system bus; at least one coprocessor coupled to said system bus; an embedded Flash memory for nonvolatile storage of code, data and bit-streams, said embedded Flash memory comprising a field programmable gate array (FPGA) port; a direct memory access (DMA) channel; and an SRAM embedded FPGA comprising an FPGA programming interface connected to the FPGA port of said embedded Flash memory through said DMA channel, an instruction extension interface for extending a datapath of said microprocessor for supporting a set of additional microprocessor instructions, a master/slave interface for supporting said at least one coprocessor, and an input/output interface for interfacing with external sensors with application-specific communication protocols; said microprocessor, said at least one coprocessor, said system bus, said embedded Flash memory, said DMA channel and said SRAM embedded FPGA being integrated as a single chip.