Patent ID: 7244659

Claim:
A method of forming a field effect transistor, comprising: forming electrically insulative trench isolation material within isolation trenches formed within bulk semiconductive silicon-comprising material, the bulk semiconductive silicon-comprising material having an outermost surface; etching some of the trench isolation material effective to recess it relative to said outermost surface and expose sidewalls of the bulk semiconductive silicon-comprising material within the isolation trenches, the etching forming recesses within the bulk semiconductive silicon-comprising material relative to said outermost surface over the trench isolation material within the isolation trenches; growing epitaxially-grown silicon-comprising material from said exposed sidewalls effective to form epitaxially-grown silicon-comprising material within the isolation trenches and forming crystalline stacking faults in part of the epitaxially-grown silicon-comprising material; and forming a field effect transistor comprising a gate, a channel region, and a pair of source/drain regions; at least a portion of at least one of a) the channel region and b) at least one of the source/drain regions being received within the epitaxially-grown silicon-comprising material, removing said part of the epitaxially-grown silicon-comprising material effective to remove the crystalline stacking faults prior to forming said portion.