Patent ID: 7339825

Claim:
A nonvolatile semiconductor memory comprising a plurality of independently operable banks, each bank including: a plurality of sectors, each having a plurality of nonvolatile memory cells and at least one local bit line connected to the memory cell; at least one write global bit line, wired commonly to said sectors, that transfers write data to said memory cells during write operation and transfers verify data from said memory cells during verify operation after write operation and after erase operation; at least one read global bit line, wired commonly to said sectors, that transfers read data from said memory cells during read operation; and a plurality of switch circuits, formed in said sectors respectively, that connect said local bit line to said write global bit line or said read global bit line according to operation modes; a verify sense amplifier that, during said verify operation, amplifies verify data read to said write global bit line from one of said memory cells; and a read sense amplifier that, during said read operation, amplifies read data read to said read global bit line from one of sad memory cells, wherein said read sense amplifier has drivability higher than that of said verify sense amplifier.