Patent ID: 8642371

Claim:
A method for fabricating an Ion-Selective Field-Effect Transistor (ISFET) with nano porous structures, the method comprises: providing a p-type silicon substrate; forming a silicon dioxide layer on the p-type silicon substrate; depositing a poly silicon layer on the silicon dioxide layer formed on the p-type silicon substrate; patterning the poly silicon layer deposited on the silicon dioxide layer as a gate region; forming a source region and a drain region in the silicon dioxide layer; depositing a passivation layer on the gate region, the source region and the drain region formed in the p-type silicon substrate; etching the passivation layer deposited on the patterned poly silicon layer using a buffered HF; and transforming the poly silicon layer into a nano porous layer on the gate region of the p-type silicon substrate by a sequential reactive ion etching process.