Patent ID: 8479134

Claim:
A method of specifying system level constraints for connecting an interface between first and second fabrics of an electronic device, the interface having a net to be connected from one connector in the first fabric to a second connector in the second fabric, the connectors being defined by their respective location within the corresponding one of the first and second fabrics, the method comprising: specifying, using one or more processors, one or more first condition relating to a placement of the interface within one of the first and second fabrics; specifying, using one or more processors, one or more second condition relating to a connection of the net in the interface between the first and second fabrics; generating, using one or more processors, one or more first equation expressing the first condition as a function of the location of the connectors within the one of the first and second fabrics; generating, using one or more processors, one or more second equation expressing the second condition as a function of the location of connectors within the one of the first and second fabrics; generating, using one or more processors, one or more third equation expressing an optimality criterion for the interface; and outputting, using one or more processors, the one or more first equation, the one or more second equation and the one or more third equation to a data file in a computer readable format.