Patent ID: 8514011

Claim:
An apparatus comprising: a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source to provide a first overdrive voltage to the first NMOS transistor circuit; a second NMOS transistor circuit coupled to the first voltage source to provide a second overdrive voltage to the second NMOS transistor circuit, the second overdrive voltage being different than the first overdrive voltage, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit; a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit; and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.