Patent ID: 7719405

Claim:
A method of operating a circuit for processing a digital data signal, the circuit including a plurality of circuit stages having respective enabled states, the method comprising: (a) establishing a present signal path including a plurality of circuit stages in enabled states; (b) disabling power to selected circuit stages not used in the present signal path so as to minimize power consumption in the disabled circuit stages; (c) processing a digital data signal through the circuit stages in the present signal path controlled by a digital clocking signal; (d) while processing the digital data signal through the present signal path, enabling power to selected disabled circuit stages in a next signal path to allow the enabled circuit stages to approach their respective enabled states; (e) at least one cycle of the clocking signal after enabling power to the selected disable circuit stages, establishing the next signal path including the enabled circuit stages in enabled states; and (f) processing the digital data signal through the circuit stages in the next signal path.