Patent ID: 7754579

Claim:
A method of forming an integrated circuit, the method comprising: depositing a fill material on at least a portion of a substrate and on a dielectric layer disposed on said substrate, said dielectric layer having an opening located above said substrate portion, said fill material filling said opening; removing the fill material disposed above said dielectric layer, thereby leaving an exposed top surface of said dielectric layer and residual fill material within said opening; forming a hard mask material on said exposed top surface of said dielectric layer and on said residual fill material; patterning said hard mask material for forming a hard mask exposing at least two portions of said residual fill material adjacent to said dielectric layer and portions of said dielectric layer adjacent to said residual fill material; and anisotropically etching exposed portions of said dielectric layer and said residual fill material and said substrate selectively to said hard mask to form a trench extending from a top surface of said residual fill material to an exposed surface of the substrate, wherein said trench has a first width adjacent said top surface of said residual fill material, and a second width adjacent said exposed surface of the substrate, wherein said first width is smaller than said second width.