Patent ID: 8214725

Claim:
A memory access system comprising: a memory controller for controlling access to a memory; and a host for outputting a command to said memory controller, wherein said memory controller comprises: a first syndrome generating part for generating a first syndrome of first data not yet written to said memory, said first syndrome being used to correct a first error occurring in said first data; a second syndrome generating part for generating a second syndrome of second data already written to said memory, said second syndrome being used to detect a second error occurring in said second data; an error detection part for detecting said second error using said second syndrome, said second error occurring in third data read from said memory; a first error correction part for correcting said first error using said first syndrome, said first error occurring in data in which said second error has been detected, out of said third data; and a data writing part for writing data in which said first error has been corrected to said memory.