Patent ID: 8086915

Claim:
A memory controller comprising: a write data buffer configured to store write data received from one or more write operations on an interconnect to which the memory controller is coupled; a first plurality of drivers and a first plurality of receivers coupled to a first plurality of pins to which a plurality of memory modules are configured to be coupled, wherein the first plurality of pins couple to a data portion of an interface to the plurality of memory modules, and wherein a separate, second plurality of pins couple to an address/control portion of the interface to the plurality of memory modules, and wherein the interface is separate from the interconnect on which the one or more write operations are received into the memory controller, and wherein a given write operation is transmitted to the plurality of memory modules via transmission of address/control information for the given write operation on the address/control portion of the interface and transmission of the data for the given write operation on the data portion of the interface; and a controller configured, in a loopback test mode of operation, to cause first write data to be transmitted from the write data buffer, through the first plurality of drivers and the first plurality of receivers, to be captured in another buffer in the memory controller in response to a first write operation.