Patent ID: 6879529

Claim:
A semiconductor memory including first and second memory cell arrays each constituted of a number of memory cells arranged in the form of a matrix having a number of rows and a number of columns, and a defective memory cell relief means, wherein each of said first and second memory cell arrays includes main memory cells arranged in the form of a matrix having a number of rows and a number of columns, at least one row of substitution information storing memory cells and at least one column of redundant memory cells, the substitution information for said first memory cell array being stored in said substitution information storing memory cells in said second memory cell array, the substitution information for said second memory cell array being stored in said substitution information storing memory cells in said first memory cell array, so that when said first memory cell array is accessed, substitution information is simultaneously read out from said substitution information storing memory cells in said second memory cell array in order to relieve a defective memory cell within said first memory cell array.