Patent ID: 8234611

Claim:
A method for improving simultaneous switching output (SSO) noise analysis, comprising: determining, by a processor, a current sharing factor of areas of an integrated circuit (IC) chip package; and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package, to perform an SSO noise analysis, wherein the current sharing factor is determined according to equation: Δ ⁢ ⁢ V ⁢ ⁢ 2 Δ ⁢ ⁢ V ⁢ ⁢ 1 = 1 1 + R ⁡ ( Δ ⁢ ⁢ t L + C Δ ⁢ ⁢ t ) , wherein ΔV1 is a change in voltage of a package power pin, ΔV2 is a change in voltage of package inductance, (ΔV2/ΔV1) is the current sharing factor, R is on chip power bus resistance, L is package inductance, C is on chip power bus capacitance, and Δt is rise time of I/O devices of IC the chip package, and wherein the determining the offload scaling factor includes determining an equivalent number of I/O devices in an area of the IC chip package having a highest number of actual I/O devices in comparison to numbers of actual I/O devices in areas of the IC chip package adjacent to the area of the IC chip package having the highest number of actual I/O devices.