Patent ID: 7153744

Claim:
A method of manufacturing a microelectronic device, comprising: providing a substrate having a protective layer located thereon and a plurality of isolation structures extending through the protective layer and at least partially into the substrate; forming a mask over a first portion of a surface collectively formed by the protective layer and the plurality of isolation structures, the masked first portion thereby sharing a boundary with an unmasked second portion of the surface; removing sacrificial portions of the protective layer from within the unmasked second portion; removing the mask; forming a conformal layer over remaining portions of the protective layer, the isolation structures, and in voids created by the removal of the sacrificial portions of the protective layer; planarizing the conformal layer such that the conformal layer, the isolation structures, and the remaining portions of the protective layer are substantially coplanar; removing the remaining portions of the protective layer; and forming transistors in voids created by the removal of the remaining portions of the protective layer; wherein planarizing the conformal layer comprises planarizing by at least one of a chemical mechanical polishing (CMP) process and an etching process.