Patent ID: 8214780

Claim:
A method comprising: selecting a first verification point and a second verification point of a model of an integrated circuit design; determining, by using a processor, whether the first and second verification points are isomorphic; verifying only a selected one of the first and second verification points in case the first and the second verification points are isomorphic; determining a result of verifying the selected one of the first and second verification points; extending the determined result of the selected one of the first and second verification points to one of the first and second verification points that was not selected for verification; wherein said determining whether the first and second verification points are isomorphic comprises: analyzing a first Boolean expression and a second Boolean expression for the first and the second verification points, respectively; and converting the first Boolean expression and the second Boolean expression into corresponding canonical representations of the first and the second Boolean expressions, respectively; wherein said determining whether the first and second verification points are isomorphic further comprises: generating a first signature and a second signature for the first and the second verification points, respectively, based at least in part on the canonical representations of the first and the second Boolean expressions, respectively, wherein the first and second signatures are unique to the canonical representations of the first and the second Boolean expressions, respectively; comparing the first signature with the second signature; and determining whether the first and second verification points are isomorphic based at least in part on said comparing.