Patent ID: 8074056

Claim:
A processor having a plurality of pipeline stages for processing instructions, the processor comprising: a buffer to store an instruction during an instruction fetch stage associated with the processor; a decoder to decode the instruction and generate a corresponding decoded instruction during a decode stage associated with the processor; issue logic to issue the decoded instruction for execution based on a predetermined criterion, the decoded instruction being issued during an instruction issue stage associated with the processor; a processor register file to store one or more operands; a plurality of pipeline registers operable to store an issued instruction from the issue logic and to latch data between a plurality of execution pipeline stages; a plurality of execution units corresponding to each of the plurality of pipeline registers, each of the execution units having one of the plurality of pipeline registers at an input and another one of the plurality of pipeline registers at an output, the plurality of pipeline registers at the input and the plurality of pipeline registers at the output being different for each of the execution units, wherein each of the execution units is operable to respectively execute a stored instruction received from a corresponding one of the plurality of pipeline registers at the input during an execution pipeline stage of the plurality of execution pipeline stages, wherein the one of the plurality of pipeline registers at the input receives a decoded instruction to be executed by a corresponding execution unit, wherein at least one of the plurality of execution units includes a different number of execution pipeline stages relative to another execution unit, and wherein the one or more operands are provided to the plurality of execution units on a need-only basis using the plurality of pipeline registers, the plurality of execution units including, at least one composite load/store execution unit operable to execute decoded load instructions and decoded store instructions in addition to decoded arithmetic logic unit (ALU) instructions; and a co-processor pipeline having a co-processor register file that stores one or more operands, wherein the decoder is operable to recognize an instruction to be processed by the co-processor pipeline and pass the recognized instruction to the co-processor pipeline for decoding, where a decoded recognized instruction is executable by the co-processor pipeline using the one or more operands stored in the co-processor register file, wherein a result associated with the decoded recognized instruction executed by the co-processor pipeline is written to the processor register file; and wherein executing the decoded recognized instruction by the co-processor pipeline and writing the result to the processor register file are performed in a same operation.