Patent ID: 7323380

Claim:
A method of forming a memory cell, comprising: forming a vertical transistor having a source region, a drain region, and a floating body region therebetween; forming a gate on a first side of the vertical transistor, the gate opposing the floating body region and separated therefrom by a gate oxide; forming a floating body back gate on a second side of the vertical transistor, the floating body back gate opposing the floating body region, the floating body back gate having a thickness approximately equal to a thickness of the gate; connecting the gate to a word line to selectively provide the gate with at least a first word line potential and a second word line potential during memory cell operation; connecting the drain region to a bit line to selectively provide the drain region with at least a first bit line potential and a second bit line potential during memory cell operation; connecting the source region to a source line to selectively provide the source region with at least a first source line potential and a second source line potential during memory cell operation; and connecting the floating body back gate to a means for applying a fixed potential to the floating body back gate during memory cell operation.