Patent ID: 7581087

Claim:
A multicore system comprising: a first processor core operative to generate a first hardware signal in response to receiving a resume software command indicating resumption of operation from a stop during debugging of the first processor core and operative to send the first hardware signal to a second processor core, the second processor core coupled to the first processor core and operative in response to receiving the first hardware signal from the first processor core to resume operation from a stop during debugging of the second processor core; whereby the first processor core resumes operation when the first hardware signal is generated, and the second processor core resumes operation within a predetermined number of cycles after receiving the first hardware signal; and the first processor core is operative to generate a second hardware signal indicating the stop, whereby the second processor core is operative to stop in response to receiving the second hardware signal; and the second processor core is operative to generate a second hardware signal indicating a stop of the second processor core during debugging of the second processor core, whereby the first processor core is operative to receive the second hardware signal and to stop synchronously with the second processor core upon receiving the second hardware signal.