Patent ID: 7944260

Claim:
A clock control circuit comprising: a clock delay device configured to generate a delayed rising clock and a delayed falling clock by delaying a rising clock and a falling clock, which are transferred from a clock generation circuit, in response to a control signal, and to transfer the delayed rising clock and the delayed falling clock to a data output buffer, wherein the clock delay device includes a first clock delay device configured to generate the delayed rising clock by delaying the rising clock in response to the control signal, and a second clock delay device configured to generate the delayed falling clock by delaying the falling clock in response to the control signal; an edge detection device configured to detect a difference between an edge timing of the delayed rising clock and an edge timing of the delayed failing clock to generate edge detection signals; a phase determination device configured to detect a duty ratio of each of the edge detection signals to generate phase determination signals; and a delay control device configured to generate the control signal in response to the phase determination signals.