Patent ID: 7085882

Claim:
A static random access memory compatible (SRAM-compatible) memory having a plurality of memory banks each having a plurality of dynamic random access memory (DRAM) cells arranged in a matrix form defined by rows and columns, the SRAM-compatible memory interfacing with an external system in which no timing period is externally set for a refresh operation of the DRAM cells, comprising: the plurality of memory banks configured to separately store input data corresponding to a single bit in DRAM cells specified by an input address externally provided, wherein write operations of the memory banks are independently controlled such that when a refresh operation or a write operation for a previous frame is being performed in a certain memory bank, write operation of input data is independently performed with respect to the respective memory banks except for the certain memory bank in both of the refresh and write operations; a parity generator for generating an input parity based on the input data, the input parity having a certain preset parity value in conjunction with the input data; and a parity bank for storing the input parity.