Patent ID: 8923049

Claim:
A two-transistor-two-bit (2T2b) Flash-based EEPROM cell comprising: a first floating gate transistor and a second floating gate transistor formed a paired cell structure in series along a Y direction on a P-type substrate without any middle contact region, wherein paired cell structure comprises, a common Deep N-well (DNW) region formed in the P-type substrate; a common Triple P-well (TPW) region formed within the DNW region; a common drain region formed within the TPW region; a common source region formed within the TPW region, the common source region being separated from the common drain region by a distance in the Y direction defined as a channel length; a first floating gate disposed on a first gate oxide overlying a first portion of the channel length; a first control gate disposed on an insulating layer over the top the first floating gate, the first control gate including first extended regions surrounded edges of the first floating gate in X direction and the Y direction, the X direction being perpendicular to the Y direction; a second floating gate disposed on a second gate oxide overlying a second portion of the channel length separated from the first portion of the channel length by a middle portion belonging to the TPW region without any contact region; a second control gate disposed on an insulating layer over the top of the second floating gate, the second control gate including second extended regions surrounded edges of the second floating gate in the X and Y directions; wherein the DNW region includes a first N+ contact region as a DNW node, the TPW region includes a P+ contact region as a TPW node, the common source region includes a second N+ contact region surrounded by the TPW region, the common drain region includes a third N+ contact region surrounded by the TPW region, the first control gate is connected to a first word line, and the second control gate is separately connected to a second word line.