Patent ID: 7457191

Claim:
An apparatus of generating an output enable signal for semiconductor memory apparatus, comprising: a timing signal generator configured to generate a timing signal when an external clock is synchronized with a predetermined internal timing; a frequency-divided clock generator configured to divide a frequency of a DLL (Delay Locked Loop) clock so as to generate an even-numbered divided clock signal and an odd-numbered divided clock; an even-numbered output enable signal generator configured to generate an even-numbered output enable signal on the basis of an external read command, the timing signal, a CL (CAS Latency), and the even-numbered divided clock; an odd-numbered output enable signal generator configured to generate an odd-numbered output enable signal on the basis of the external read command, a second timing signal in which the timing signal is inverted, the CL, and the odd-numbered divided clock; and a logical unit configured to operate on the even-numbered output enable signal and the odd-numbered output enable signal and output an output enable signal.