Patent ID: 7996810

Claim:
A computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to said processor, said memory unit containing instructions that when executed by said processor implement a method for designing a monotonic CMOS circuit with reduced current leakage, said method comprising the computer implemented steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, said standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing said standard design elements of said selected logic stages with reduced current leakage elements, said reduced current leakage elements including: thin gate dielectric and high threshold voltage PFETs with respect to said reference PFET, for logic stages having predominantly high input states; thick gate dielectric and low threshold voltage NFETs with respect to said reference NFET, for logic stages having predominantly high input states; thick gate dielectric and low threshold voltage PFETs with respect to said reference PFET, for a logic stages having predominantly low input states; and thin gate dielectric and high threshold voltage NFETs with respect to said reference NFET, for said logic stages having predominantly low input states.