Patent ID: 8629052

Claim:
A method of forming a semiconductor device, the method comprising: forming a conductive layer on a substrate; forming a lower mask layer on the conductive layer; forming an upper mask layer on the lower mask layer; patterning the upper mask layer to form a first upper mask pattern, a second upper mask pattern and a third upper mask pattern between the first upper mask pattern and the second upper mask pattern, where the first through third upper mask patterns are connected to one another and a width of the second upper mask pattern is greater than a width of the first upper mask pattern; forming first, second and third spacers, where the first spacer covers sidewalls of the first upper mask pattern, the second spacer covers sidewalls of the second upper mask pattern, and the third spacer covers sidewalls of the third upper mask pattern; removing the first and third upper mask patterns while retaining the second upper mask pattern; patterning the lower mask layer using the first, second and third spacers and the second upper mask pattern as etch masks to form a lower mask pattern; and patterning the conductive layer using the lower mask pattern as an etch mask to form a conductive pattern.