Patent ID: 7210023

Claim:
A data processing apparatus, comprising: a register data store having a plurality of registers operable to store data elements; a processor operable to perform a data processing operation on one or more of said data elements accessed in at least one of said registers; access logic operable in response to an access instruction to perform an access operation in order to move a number of said data elements between specified registers of said plurality of registers and a portion of a memory, the portion having a start address specified by the access instruction; the access instruction having an alignment specifier associated therewith which is settable either to a first value or one of a plurality of second values, the first value indicating that the start address is to be treated as byte aligned, and each of the second values indicating a different predetermined alignment that the start address is to be treated as conforming to; and the access logic being operable to adapt the access operation in dependence on the value of the alignment specifier.