Patent ID: 7148764

Claim:
A communication semiconductor integrated circuit device comprising: a phase-locked loop (PLL) circuit comprising an oscillator circuit for oscillating a signal in a plurality of frequency bands, a phase detection circuit configured to detect a difference between a phase of a reference frequency signal received from a reference oscillator circuit and a phase of said signal from said oscillator circuit, and charge pump and a filter capacitor for generating a voltage in response to output of said phase detection circuit; fixed voltage supply means for supplying a predetermined direct-current (dc) voltage as a control voltage of said oscillator circuit; a frequency counter, coupled to said oscillation circuit, for determining an oscillation frequency of said oscillator circuit; storage means for storing frequency information determined for each frequency band of said oscillator circuit; a control circuit which causes, in a state in which said PLL circuit is set to an open loop state, said oscillator circuit to conduct an operation of oscillation by a dc voltage from said fixed voltage supply means, to determine a frequency of the oscillation for each frequency band of said oscillator circuit, and causes said storage means to store the frequency.