Patent ID: 7594196

Claim:
A computer-implemented method for stitching an electronic block, comprising: identifying an electronic block in a layer for which stitching is desired; identifying a stitching region by decomposing at least a portion of the layer into a plurality of candidate regions, and selecting the switching region from the plurality of candidate regions based at least in part upon a criterion; determining at least one first wiring direction to stitch, the at least one first wiring direction being internal to the electronic block; determining at least one second wiring direction to stitch, the at least one second wiring direction being external to the electronic block; determining routability of the stitching region or determining whether the stitching region causes a negative impact on access to a circuit component; displaying the at least one first wiring direction and the at least one second wiring direction on a display apparatus or storing the at least one first wiring direction and the at least one second wiring direction on a computer readable medium or a storage device; and configuring the stitching region to stitch together the at least one first wiring direction and the at least one second wiring direction, wherein the act of configuring the stitching region is performed by a processor.