Patent ID: 7629650

Claim:
A semiconductor device comprising: an insulation substrate; a semiconductor layer disposed on the insulation substrate, the semiconductor layer comprising a source, a drain, a channel disposed between the source and the drain and a low impurity concentration region disposed between the channel and the source or between the channel and the drain, the low impurity concentration region having an impurity concentration lower than an impurity concentration of the source or the drain; a gate insulation film disposed on the semiconductor layer; a gate wiring disposed on the gate insulation film; an interlayer insulation film disposed on the gate wiring; a source wiring disposed on the interlayer insulation film and connected with the source; and a drain wiring disposed on the interlayer insulation film and connected with the drain, wherein a lateral edge of the source wiring or the drain wiring is positioned between a first lateral edge of the gate wiring and a second lateral edge of the gate wiring, the first and second lateral edges defining a width of the gate wiring, and in plan view of the semiconductor device, the low impurity concentration region is covered completely by the source wiring or the drain wiring.