Patent ID: 6847080

Claim:
An integrated circuit, comprising: a first transistor, having a first breakdown voltage, in a first region near the surface of a semiconductor substrate; a second transistor, having a second breakdown voltage substantially higher than the first breakdown voltage, in a second region near the surface of the semiconductor substrate, wherein: the first transistor has a first gate electrode and the second transistor has a second gate electrode, wherein the gate electrodes are separated from the semiconductor substrate by a layer of dielectric material; the first transistor has a first channel region near the surface of the semiconductor substrate underneath the first gate electrode and the second transistor has a second channel region near the surface of the semiconductor substrate underneath the second electrode; the channel regions are doped with dopant of a common first conductivity; the transistor has first inner sidewall spacers adjacent the first gate electrode and first outer sidewall spacers adjacent to the first sidewall spacers; the second transistor has second inner sidewall spacers, substantially identical to the first inner sidewall spacers, adjacent the second gate electrode and second outer sidewall spacers, substantially identical to the second outer sidewall spacers, adjacent to the second inner sidewall spacers; the first transistor has first lightly doped source and drain regions underneath the first inner sidewall spacers, doped with dopant of a second conductivity opposite the first conductivity, adjacent and receding from the first channel region; the second transistor has second lightly doped source and drain regions underneath the second inner sidewall spacers and the second outer spacers, doped with dopant of th second conductivity, adjacent and receding from the second channel region and; the first transistor has first heavily doped source and drain regions underneath the first outer sidewall spacers, doped with dopant of the second conductivity, adjacent the first lightly doped source and drain regions and receding from under the first inner sidewall spacers; and the second transistor has second heavily doped source and drain regions, doped with dopant of the second conductivity, adjacent the second lightly doped source and drain regions and receding from under the second sidewall pacers.