Patent ID: 7117462

Claim:
A circuit operation verifying method for verifying that each of a number of circuit elements of a semiconductor circuit in layout design satisfies specifications, the method comprising the steps of: loading condition information of the semiconductor circuit as electrical specifications on voltages and currents applied to the circuit elements, circuit diagram data representing connection information of the semiconductor circuit, and input patterns of voltages and currents used for circuit operation simulation with respect to time; simulating operation of the semiconductor circuit by computing voltage values or current values with respect to time of the circuit elements of the semiconductor circuit being based on the loaded circuit diagram data and input patterns, said simulating operation being performed at each of a plurality of specific times which are incrementally increasing, and storing the computed values in a memory after each simulating operation; verifying that the circuit elements of the semiconductor circuit satisfy the loaded condition information using the voltage values or the current values of the circuit elements stored in the memory, said verifying step being performed after each simulating operation; and calculating a next specific time used for a next simulating step and a next verification step by adding an infinitesimal time to the specific time after the verifying step, wherein the simulating step, the verifying step and the calculated step are performed repeatedly, and wherein a low-precision, high-speed operation simulation is executed for the semiconductor circuit using the input patterns, to prepare operation information on the circuit elements of the semiconductor circuit and circuit hierarchical information on the semiconductor circuit.