Patent ID: 7425767

Claim:
A semiconductor chip assembly comprising: a chip comprising a semiconductor substrate, a MOS device in or on said semiconductor substrate, a metallization structure over said semiconductor substrate, a passivation layer over said metallization structure, wherein said passivation layer comprises a nitride layer, and wherein a first opening in said passivation layer is over an original IC connection point of said metallization structure and exposes said original IC connection point, a metal trace over said passivation layer and over said original IC connection point, wherein said metal trace is connected to said original IC connection point through said first opening, and a redistributed pad connected to said original IC connection point through said metal trace, wherein said metal trace does not connect said original IC connection point to any other metal portion under said passivation layer, wherein said redistributed pad has a position from a top view different from that of said original IC connection point, wherein said redistributed pad is entirely over said passivation layer, and no opening in said passivation layer is under said redistributed pad, wherein said redistributed pad comprises an adhesion/barrier layer, a first gold layer over said adhesion/barrier layer, and a second gold layer over said first gold layer, wherein said second gold layer contains gold with greater than 90 weight percent and has a thickness between 2 and 30 micrometers, and wherein said chip has a first edge and a second edge neighboring to said first edge, wherein the minimum distance between said first edge and said original IC connection point is smaller than that between said second edge and said original IC connection point, and the minimum distance between said first edge and said redistributed pad is greater than that between said second edge and said redistributed pad; and a wire wirebonded to said redistributed pad, wherein said wire is across said second edge.