Patent ID: 8748305

Claim:
A semiconductor device, comprising: a semiconductor substrate having a plurality of microelectronic elements formed therein; an interconnect structure formed over the substrate, the interconnect structure including a plurality of metal layers and a plurality of inter-metal dielectric (IMD) layers for isolating the metal layers, the metal layers including a topmost metal layer, a bottommost metal layer, and at least two metal layers disposed between the topmost metal layer and the bottommost metal layer; a plurality of dummy metal vias formed within one or more of the IMD layers disposed between the at least two metal layers; a plurality of real metal vias formed within the one or more of the IMD layers disposed between the at least two metal layers; and a pad structure formed directly over the dummy metal vias, wherein the plurality of dummy metal vias are not electrically connected to the semiconductor substrate, the pad structure, and any functional circuit, wherein the plurality of real metal vias are electrically connected to the semiconductor substrate and the pad structure, wherein at least one real metal via from the plurality of real metal vias is disposed between a first dummy metal via and a second dummy metal via from the plurality of dummy vias directly under the pad structure.