Patent ID: 7442596

Claim:
A method of manufacturing a fin type field effect transistor, the method comprising: forming a first hard mask layer pattern on a substrate comprising a semiconductor material; partially etching the substrate using the first hard mask layer pattern as an etching mask to form an active fin extending in a direction away from a major surface of the substrate, wherein the active fin comprises a semiconductor material; forming a gate insulation layer pattern on a sidewall portion of the active fin; forming a first conductive layer pattern comprising a metal silicide on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask layer pattern; forming a first dummy layer pattern on the first conductive layer pattern, the first dummy layer pattern having a first etching selectivity with respect to the first conductive layer pattern; forming a second dummy layer pattern on the first dummy layer pattern, the second dummy layer pattern having a second etching selectivity with respect to the first conductive layer pattern; and forming source/drain regions in the active fin on opposite sides of the first conductive layer pattern.