Patent ID: 7100104

Claim:
A turbo decoder comprising: an error correction decoding unit for performing error correction decoding of an inputted data series; a first memory to which the data series subjected to error correction coding by said error correction decoding unit is written; and an address generator for supplying, when writing said data series undergoing error correction decoding is written to said first memory, write addresses and when said data series written to said first memory is read out of said first memory, supplying random read addresses, wherein said address generator converts values pursuant to a predetermined rule into said random read addresses and decides whether said random read addresses correspond to data storage portions on said first memory, and wherein said address generator randomly reads the data series written to said first memory by using said random mad addresses when a result of said decision indicates that said random read addresses correspond to data storage portions on said first memory, and it randomly reads the data series written to said first memory by using different random read addresses substituting for said random read addresses when said random read addresses do not correspond to any data storage portion on said first memory.