Patent ID: 8339561

Claim:
A wiring substrate comprising: a base film including a chip-mounting region, the chip-mounting region configured to mount a semiconductor chip thereon; a plurality of first wirings extending in a first direction from inside the chip-mounting region to outside the chip-mounting region, the first wirings including first connection end portions extending in a second direction different from the first direction, and the first connection end portions being formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip; and a plurality of second wirings extending in the first direction from inside the chip-mounting region to outside the chip-mounting region, the second wirings including second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions being formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip, wherein the first connection end portions of the first wirings are respectively arranged in a plurality of first lines parallel to an extending direction of a side of the chip-mounting region and the second connection end portions of the second wirings are respectively arranged in a plurality of second lines positioned between the adjacent first connection end portions.