Patent ID: 7499364

Claim:
A semiconductor memory device, comprising: a plurality of input/output ports including a first input/output port and a second input/output port; and a memory array including a plurality of memory regions comprising a first memory region and a second memory region each having a plurality of memory banks, wherein the first memory region and the second memory region are accessed by using only the first input/output port as a shared port first mode, where a first signal is input/output to the first memory region and the second memory region from the first input/output port and where a second signal different from the first signal is input/output to each of the first memory region and second memory region from each of the first input/output port and the second input/output port, and wherein the first memory region is accessed by using the first input/output port in a second mode, where the first signal is input/output to the first memory region only from the first input/output port and where the second signal is input/output to each of the first memory region and the second memory region from the first input/output port.