Patent ID: 7805698

Claim:
A computer implemented method of generating a physical circuit design having a physical design from a logical design, wherein the physical design comprises a first plurality of physical cells from a physical cell library, and the logical design comprises a second plurality of logical cells from a logical cell library, the method comprising: using a computer system to read the logical design and identify logical cells of the second plurality; retrieving configuration data used to map the identified logical cell of the second plurality to the physical design; retrieving a logical to physical mapping attribute used to map the identified logical cell of the second plurality to a physical cell of the first plurality; and creating a physical design from the logical design by mapping the logical design into a physical domain based on the configuration data and the logical to physical mapping attribute, wherein the logical to physical mapping attribute is stored in one of a plurality of attribute libraries, each attribute library containing logical to physical mapping attributes specifying how cells in the logical library map to physical cells in the physical library.