Patent ID: 8274080

Claim:
A semiconductor wafer, comprising: semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns; and scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other, wherein the process monitoring pattern includes: a first lower conductive layer, a first insulating layer on the first lower conductive laver, a first capping layer on the first insulating laver, the first capping layer including a denser insulating material than the first insulating layer, and a first upper conductive layer on the first capping layer, and wherein the outer guard ring patterns include: a second lower conductive layer being made of and merged with the first lower conductive layer, a second insulating layer on the second lower conductive layer, the second insulating layer being made of and merged with the first insulating layer, a second capping layer on the second insulating layer, the second capping layer being made of and merged with the first capping layer, and a second upper conductive layer on the second capping layer, the second upper conductive layer being made of and merged with the first upper conductive layer.