Patent ID: 6953959

Claim:
An integrated circuit device comprising: a substrate; a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row; source and drain regions in the active regions arranged such that each active region comprises a drain region disposed between two source regions; a plurality of word line structures on the substrate, arranged transverse to the rows of active regions such that word line structures cross the active regions between the source regions and the drain regions; respective rows of separate conductive pads disposed between respective adjacent word line structures, each row of conductive pads including separate first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive pads on isolation regions separating active regions; an interlayer insulating layer on the substrate; and a plurality of bit line structures on the substrate extending transverse to the word line structures and contacting the second conductive pads, the bit line structures comprising a plurality of conductive plugs extending through the interlayer insulating layer to contact the second conductive pads, wherein the conductive plugs also contact the third conductive pads.