Patent ID: 8670520

Claim:
A one-of-many selection circuit comprising a one-of-many shift register comprising a data input and a clock input, the one-of-many shift register comprising: a plurality of series-connected shift registers, wherein each shift register comprises: a first latch which is implemented to take over a signal state applied to its data input in a transparent operating state and to maintain the taken-over signal state in a non-transparent operating state; a second latch which is implemented to take over a signal state applied to its data input in a transparent operating state and to maintain the taken-over signal state in a non-transparent operating state; wherein the first latch and the second latch are series-connected; wherein clock inputs of the latches are switched such that the second latch is in the transparent operating state when the first latch is in the non-transparent operating state and vice versa; a first output circuit which is implemented to provide a predetermined level independent of the signal state existing in the first latch at a first shift register output of the shift register in the transparent operating state of the first latch and to provide a level depending on the signal state stored in the first latch in the non-transparent operating state of the first latch; and a second output circuit which is implemented to provide a predetermined level independent of the signal state existing in the second latch at a second shift register output of the shift register in the transparent operating state of the second latch and to provide a level depending on the signal state stored in the second latch in the non-transparent operating state of the second latch; wherein the shift registers are coupled to the data input and the clock input such that a “1” applied to the data input is shifted through the shift registers such that with a falling clock edge at the clock input the “1” is shifted on from a first shift register output of a first shift register of the plurality of shift registers to a second shift register output of the same shift register and that with a rising clock edge the “1” is shifted on from the second shift register output of the first shift register to a first shift register output of a subsequent shift register; or that with a rising clock edge at the clock input the “1” is shifted on from a first shift register output of a first shift register of the plurality of shift registers to a second shift register output of the same shift register and that with a falling clock edge the “1” is shifted on from the second shift register output of the first shift register to a first shift register output of a subsequent shift register.