Patent ID: 7652947

Claim:
A personalization decode for use in a semiconductor memory comprising a first circuit block connected, comprising a first decode layer, to four (4) data lines using two (2) address line inputs, the first circuit block comprising: first, second, third and fourth FET devices, where each FET device includes a source, a drain, a gate and a back gate, the drains of which are connected to one each of the four (4) data lines, and the source of each FET device is connected to ground for NOR-like decode functionality; wherein the gates of the first and third FET devices are connected to the first address line input, and the gates of the second and fourth FET devices are connected through an inverter to the first address line input; wherein the back gates of the first and second FET devices are connected to the second address line input, and the back gates of the third and fourth FET devices are connected through an inverter to the second address line input; and wherein address decode signals asserted through the first and second address line inputs during decode operation at the back gate of the FET devices bias the devices to lower the relative threshold voltage for “on” state operation, and to elevate the relative voltage threshold for “off” state operation.