Patent ID: 7790268

Claim:
A circuit assembly, comprising two or more circuit laminates, each comprising a conductive metal layer disposed on a poly(aryl ene ether ketone) dielectric substrate layer as a core material, wherein at least one of the conductive metal layers of each circuit laminate has been patterned to form a circuit; and a thermoplastic bond ply layer disposed between the circuit laminates, wherein the bond ply has a melting point between 250° C. and 370° C., a T d of greater than about 290° C., wherein T d is the temperature at which the bond ply has a cumulative weight loss of 5% as measured by a thermogravimetric analyzer, and a dissipation factor of less than 0.01 at 10 GHz, wherein at least one of the poly(aryl ene ether ketone) substrate layers is in contact with the bond ply layer and wherein the bond ply comprises a liquid crystalline polymer, polyimide, perfluoroalkoxy copolymer, fluorinated ethylene propylene, or polytetrafluoroethylene.