Patent ID: 7155721

Claim:
An apparatus for allowing direct read and write communication between lock step, processors, comprising: two or more processors operating in a lock step mode, wherein each of the two or more processors comprise a processor logic to execute a code sequence, wherein an identical code sequence is executed by the processor logic of each of the two or more processors; and a lock step logic block operable to read and compare the output of each of the two or more processors, the lock step logic block comprising: a processor-specific resource referenced by the code sequence, and a multiplexer coupled to the processor-specific resource, wherein the multiplexer is controlled to read data based on an identification of the processor specific resource, the identification of the processor specific resource determining which processor supplies the read data, wherein the two or more processors operating in the lock step mode can perform inter-processor read and write communications without resorting to load and store instructions that cause a loss of lock step.