Patent ID: 8772157

Claim:
A method of forming Cu interconnects comprising: Step 1: depositing an etch stop layer; Step 2: depositing an insulating layer with certain thickness on the etch stop layer; Step 3: applying photolithography and etching process to the insulating layer to form vias and trenches in the insulating layer; Step 4: depositing a diffusion barrier layer and depositing a copper seed layer on the diffusion barrier layer using PVD; Step 5: applying electroplating process to the top surface of the copper seed layer to form the copper interconnects; Step 6, depositing a layer of filling materials adhering to copper and then reflowing the filling materials to eliminate the uneven surface topography of the copper interconnects, wherein the step 6 of applying CMP process further comprised: Step 61, removing all the filling materials and parts of the copper interconnects on the diffusion barrier layer with the same removal rate; Step 62, removing all the copper interconnects on the to surface of the insulating layer with high selectivity ratio of copper to the diffusion barrier layer, and stopping on the diffusion barrier layer; and Step 63, removing the entire diffusion barrier layer on the to surface of the insulating layer; And Step 7, applying annealing and CMP to planarize the top surface of the copper interconnects, and rinsing.