Patent ID: 8683291

Claim:
A method of processing a byte sequence into a cyclic redundancy check (CRC) value in a current pass, the method comprising: dividing the byte sequence into blocks in one clock cycle, each block having a corresponding original width; if a block's original width is less than a maximum number of bytes, padding the block until a new width is equal to the maximum number of bytes; based on a first state vector and the padded block, computing, by a CRC unit, a first internal vector; generating, by multiplying the internal vector by one or more first correction matrices, a first set of products; and if the one or more first correction matrices form a complete set, selecting, in the one clock cycle, by a first control signal determined by the original width, a second state vector from the first set of products, wherein the method is implemented as steps executed by a system-on-chip (SoC) network processor.