Patent ID: 8654570

Claim:
A memory cell, comprising: a latch circuit having a true node and a complement node; a first true bit line node; a first complement bit line node; a first transistor source-drain coupled between the first true bit line node and the true node of the latch circuit, a control terminal of the first transistor coupled to a first word line node; a second transistor source-drain coupled between the first complement bit line node and the complement node of the latch circuit, a control terminal of the second transistor coupled to a second word line node; a third transistor source-drain coupled between the true node and the first word line node, a control terminal of the third transistor coupled to the first complement bit line node; and a fourth transistor source-drain coupled between the complement node and the second word line node, a control terminal of the fourth transistor coupled to the first true bit line node.