Patent ID: 7981799

Claim:
A fabrication method of a room temperature-operating single-electron device, the method comprising the steps of: arming an SOI substrate by sequentially stacking an insulating layer 11 and a silicon layer 10 on a silicon substrate 12 , and etching the silicon layer 10 of the SOI substrate to thereby form an active region 10 a; forming a mask 20 on a central channel portion of the active region 10 a , and injecting impurity ions into a part of the active region 10 a to form a source region and a drain region; arming a silicon oxide film 30 on an entire top surface of the SOI substrate; etching a channel portion of the active region 10 a to form a silicide trench 31 ; depositing an oxide film 40 on the entire top surface of the SOI substrate; depositing a metal film 42 on the entire top surface of the oxide film; thermally treating a part of the metal film 42 to achieve silicidization of the metal dots, and removing the silicon oxide film 30 and the metal film 42 which is not silicidized to form serially-arrayed silicide quantum dots 41 ; depositing gate oxide films 50 a and 50 b on the entire top surface of the SOI substrate; etching a part of the gate oxide films 50 a and 50 b positioned on the top of a source 13 and a drain 14 formed on both ends of the active region 10 a to form each contact hole, and depositing a metal film to fill the contact hole to form a source pad 60 and a drain pad 61 ; and forming a resist pattern on the silicide trench 31 to form a gate.