Patent ID: 8127208

Claim:
A parity bit generator for generating at least eight parity bits {P 0 , P 1 , P 2 . . . P 7 } corresponding to 64 data bits {D 0 , D 1 , D 2 . . . D 63 }, comprising: at least one electronic logic circuit configured to calculate said parity bits as follows: P 7 =D 63 ^D 62 ^D 61 ^D 60 ^D 59 ^D 58 ^D 57 ^D 56 ^D 55 ^D 54 ^D 53 ^D 52 ^D 51 ^D 50 ^D 49 ^D 48 ^D 43 ^D 42 ^D 41 ^D 40 ^D 39 ; P 6 =D 63 ^D 62 ^D 61 ^D 60 ^D 59 ^D 58 ^D 47 ^D 46 ^D 38 ^D 37 ^D 36 ^D 35 ^D 34 ^D 33 ^D 32 ^D 31 ^D 30 ^D 29 ^D 28 ^D 27 ^D 26 ^D 25 ^D 24 ; P 5 =D 63 ^D 57 ^D 56 ^D 55 ^D 54 ^D 53 ^D 45 ^D 44 ^D 38 ^D 37 ^D 36 ^D 35 ^D 34 ^D 23 ^D 22 ^D 21 ^D 19 ^D 18 ^D 17 ^D 16 ^D 15 ^D 14 ^D 13 ^D 12 ^D 11 ^D 10 ; P 4 =D 62 ^D 57 ^D 52 ^D 51 ^D 50 ^D 49 ^D 47 ^D 45 ^D 44 ^D 38 ^D 33 ^D 32 ^D 31 ^D 30 ^D 23 ^D 22 ^D 20 ^D 19 ^D 18 ^D 17 ^D 16 ^D 9 ^D 8 ^D 7 ^D 6 ^D 5 ^D 4 ; P 3 =D 61 ^D 56 ^D 52 ^D 48 ^D 46 ^D 45 ^D 44 ^D 43 ^D 42 ^D 37 ^D 33 ^D 29 ^D 28 ^D 27 ^D 23 ^D 21 ^D 20 ^D 19 ^D 15 ^D 14 ^D 13 ^D 9 ^D 8 ^D 7 ^D 3 ^D 2 ^D 1 ; P 2 =D 60 ^D 55 ^D 51 ^D 48 ^D 47 ^D 46 ^D 45 ^D 44 ^D 41 ^D 40 ^D 36 ^D 32 ^D 29 ^D 26 ^D 25 ^D 22 ^D 21 ^D 20 ^D 18 ^D 15 ^D 12 ^D 11 ^D 9 ^D 6 ^D 5 ^D 3 ^D 2 ^D 0 ; P 1 =D 59 ^D 54 ^D 50 ^D 47 ^D 46 ^D 45 ^D 43 ^D 41 ^D 39 ^D 35 ^D 31 ^D 28 ^D 26 ^D 24 ^D 23 ^D 22 ^D 20 ^D 17 ^D 14 ^D 12 ^D 10 ^D 8 ^D 6 ^D 4 ^D 3 ^D 1 ^D 0 ; and P 0 =D 58 ^D 53 ^D 49 ^D 47 ^D 46 ^D 44 ^D 42 ^D 40 ^D 39 ^D 34 ^D 30 ^D 27 ^D 25 ^D 24 ^D 23 ^D 22 ^D 21 ^D 20 ^D 16 ^D 13 ^D 11 ^D 10 ^D 7 ^D 5 ^D 4 ^D 2 ^D 1 ^D 0 .