Patent ID: 7119598

Claim:
A clock controlling circuit comprising: a clock propagation path at least one branching to a first forward branch route and a second forward branch route which are direction-reversed on a side spaced apart from the branching and extend as a first return branch route and second return branch route, respectively, said first return branch route and said second return branch route extending along said second forward branch route and said first forward branch route, respectively, in anti-parallel fashion, and at least one timing averaging circuit receiving a clock from a first or second position on said first or second forward branch route and a clock from a second or first position on said second or first return branch route, respectively, each for outputting a signal of delay time corresponding to a time obtained by dividing a timing difference between these clocks in two portions, wherein said timing averaging circuit is arranged for charging or discharging an internal node based on a first of said two input clocks undergoing transition at an earlier time and for charging or discharging said internal node based on a second of said two input clocks undergoing transition with a delay time from said first of said two input clocks, wherein said timing averaging circuit comprises a plurality of switches, wherein at least two of said plurality of switches have a substantially equal on-current, wherein said at least two of said plurality of switches are connected across a first power source and said internal node, and wherein another of said plurality of switches is connected across said internal node and a second power source.