Patent ID: 7895502

Claim:
A method of error control for memories permitting subline accesses comprising the steps of: dividing a line of data into a plurality of sublines of data in memory, wherein a line of data is a first level of access granularity and a subline of data is a second level of access granularity smaller than said first level of access granularity; adding a first level of code to each of said plurality of subtitles of data, said first level of code providing local protection for each of said plurality of sublines of data; adding a second level of code to the line of data, said second level of code providing global protection for said plurality of sublines of data; retrieving one or more subtitles of data, wherein accessed sublines of data may be in different lines of data and multiple subtitles may be concurrently retrieved; detecting errors in sublines of data using said first level of code; and correcting errors in sublines of data by accessing a line of data containing subtitles of data having detected errors and using said second level of code.