Patent ID: 7793070

Claim:
A method for managing memory of a processing system comprising at least one processor, the method comprising: detecting, through the use of the at least one processor, a translation lookaside buffer miss; identifying, through the use of the at least one processor, one or more missed virtual addresses corresponding to the translation lookaside buffer miss; updating, through the use of the at least one processor, a first translation lookaside buffer with information corresponding to the one or more missed virtual addresses only if memory page size information for the one or more missed virtual addresses corresponds to a first memory page size supported by the first translation lookaside buffer; and updating, through the use of the at least one processor, a second translation lookaside buffer with information corresponding to the one or more missed virtual addresses only if memory page size information for the one or more missed virtual addresses corresponds to a second memory page size supported by the second translation lookaside buffer, where the second memory page size is different than the first memory page size.