Patent ID: 8138775

Claim:
A CMOS-controlled printhead sense circuit, comprising: a CMOS control circuit module operable as a transmission gate transformable between first and second signal levels, the control circuit module having a first number of PMOS FETs equal to a second number of NMOS FETs wherein each of the PMOS FETs are serially arranged with one another as entirely enhancement mode transistors and each of the NMOS FETs are serially arranged with another including enhancement mode transistors and a gate-controlled transistor, the PMOS FETs and the NMOS FETs also being entirely arranged in series with a voltage control output residing between the PMOS FETs and the NMOS FETs; and a CMOS sense circuit module operable in a sense mode in response to said control circuit module being transformed to said first signal level and in a transparent mode in response to said control circuit module being transformed to said second signal level, the sense circuit module having a third number of PMOS FET equal to a fourth number of NMOS FET wherein the NMOS FET of the sense circuit module act only as a load on the PMOS FET of the sense circuit module and the PMOS FET of the sense circuit module is a transistor gate-controlled by the voltage control output from the control circuit module.