Patent ID: 8555494

Claim:
A method for manufacturing a coreless substrate, the method comprising: forming at least one solder resist layer on at least one of a first side and a second side of a metal panel; forming a first and at least a second opening in the at least one solder resist layer extending to the metal panel; forming a metal plating comprising copper directly on the surface of the metal panel in the first and at least second opening by electroplating; forming a surface finish layer on the metal plating in each of the first and at least second opening; electrolytic plating the surface finish layer in each of the openings with copper to form a discrete copper plating on the surface finish layer in each of the first and at least second opening, each discrete copper plating having a pin shape extending over a portion of the solder resist layer and a height which exceeds a height of the solder resist layer; forming at least one dielectric layer covering the discrete copper platings; and forming at least one microvia in the at least one dielectric layer, wherein at least a portion of the microvia extends to said discrete copper plating in each of said first and at least second opening; and separating said metal panel and said metal plating from said at least one solder resist layer and said surface finish layer.