Patent ID: 6915443

Claim:
A computer system, comprising: a main memory array coupled to a memory controller by way of a memory bus; a host clock generator having a host clock signal coupled to a phase locked loop (PLL) device and said memory controller; said PLL device having a plurality of PLL output signals having the same frequency as the host clock output signal, but differing in phase relationship; one of said PLL outputs signals coupled to said main memory array, and one of said PLL output signals coupled to said memory controller; a clock delay circuit coupled between said PLL output signal and said memory controller, said clock delay circuit time delays said PLL output signal, said clock delay circuit comprising: a first signal path having a first length, said first signal path selectable by a first electrically controlled switch coupled to the first signal path; and a second signal path having a length longer than said first length, said second signal path selectable by a second electrically controlled switch coupled to the second signal path; wherein said clock delay circuit routes said PLL output signal along one of said first signal path for a short time delay, and said second signal path for a long time delay.