Patent ID: 7830713

Claim:
A nonvolatile memory structure comprising: a plurality of dual-sided charge-trapping nonvolatile memory cells connected in a NAND series string; and a pair of serially connected top select transistors, wherein each of the pair of serially connected top select transistors have a first source/drain and each of the first source/drains are connected together, wherein a first of the serially connected top select transistors has an implant to make a threshold voltage of the implanted first serially connected select transistor different from a non-implanted second serially connected top select transistor, wherein a second source/drain of one of the pair of serially connected transistors is connected to a top dual-sided charge-trapping nonvolatile memory cell of the NAND series string of dual-sided charge-trapping nonvolatile memory cells, and wherein a second source/drain of another of the serially connected transistors is connected to a first of two bit lines associated with the NAND series string nonvolatile memory structure; and wherein both of the pair of serially connected top select transistors are turned on only when a first select voltage applied to a gate of the one implanted transistor of the pair of serially connected top select transistors and a second select voltage applied to a gate of the other non-implanted pair of serially connected top select transistors are greater than the threshold voltages of the pair of serially connected top select transistors to connect the top dual-sided charge-trapping nonvolatile memory cell to the first of two bit lines with the NAND series string.