Patent ID: 7718994

Claim:
An array substrate for use in a thin film transistor liquid crystal display, comprising: a substrate comprising a gate line area with a gate region, a gate pad area connected to an end portion of the gate line area, a source line area crossing the gate line area, a source pad area connected to an end portion of the source line area, and a pixel area defined by the crossing gate and source lines; a transparent conductive layer formed on the substrate in the gate pad area, the gate line area, the gate region, the source pad area and the pixel area; a first metal layer formed on the transparent conductive layer in the gate line area and the gate region; a first insulating layer formed on the first metal layer; a semiconductor layer formed on the first insulating layer; an insulating spacer formed on at least sidewalls of the first metal layer; a second insulating layer formed on part of the semiconductor layer; and a second metal layer formed above the substrate in the source line area, on part of the semiconductor layer in the gate region and part of the transparent conductive layer in the pixel area.