Patent ID: 8581652

Claim:
A flip-flop circuit for retaining input data, comprising: a first master latch circuit for latching the input data; a second master latch circuit for latching the input data; a first C-element circuit for receiving an inverted output of the first master latch circuit and an inverted output of the second master latch circuit; a second C-element circuit for receiving a non-inverted output of the first master latch circuit and a non-inverted output of the second master latch circuit; a first slave latch circuit for latching an output of the first C-element circuit; a second slave latch circuit for latching an output of the second C-element circuit; a third C-element circuit for receiving an inverted output of the first slave latch circuit and an inverted output of the second slave latch circuit; a fourth C-element circuit for receiving a non-inverted output of the first slave latch circuit and a non-inverted output of the second slave latch circuit; a first inverter circuit; a second inverter circuit being interconnected to the first inverter circuit; a third inverter circuit; and a fourth inverter circuit being interconnected to the third inverter circuit, an input terminal of the first inverter circuit and an output terminal of the second inverter circuit being connected to a connection point between an output terminal of the first C-element circuit and a data input terminal of the first slave latch circuit, an output terminal of the first inverter circuit and an input terminal of the second inverter circuit being connected to a connection point between an output terminal of the second C-element circuit and a data input terminal of the second slave latch circuit, an input terminal of the third inverter circuit and an output terminal of the fourth inverter circuit being connected to an output terminal of the third C-element circuit, an output terminal of the third inverter circuit and an input terminal of the fourth inverter circuit being connected to an output terminal of the fourth C-element circuit.