Patent ID: 7119009

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie; forming an interlayer insulating film on the insulating etch stopper film, the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer, the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film to an intermediate depth of the first kind of the insulating layer, and overlapping or including the first contact hole as viewed in plan; removing the protective filler; removing the insulating etching stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes.