Patent ID: 8667370

Claim:
A system, comprising: a processor, wherein the processor includes a processor core; a memory in communication with the processor core, wherein the processor core is configured to (i) process data stored in the memory, and (ii) execute instructions using the memory; a first-in first-out buffer configured to (i) receive streaming data, and (ii) output the streaming data to the memory for processing by the processor core; and an arbiter module configured to in response to the first-in first-out buffer not being filled to a predetermined threshold with the streaming data, allow the processor core to access the memory at a higher priority than the first-in first-out buffer to permit the processor core to (i) process data stored in the memory including any streaming data output to the memory by the first-in-first-out buffer, and (ii) execute instructions using the memory; and in response to the first-in first-out buffer being filled to the predetermined threshold with the streaming data, allow the first-in first-out buffer to access the memory at the higher priority than the processor core to permit the first-in-first-out buffer to output the streaming data, without having the first-in first-out buffer overflow, to the memory for processing by the processor core.