Patent ID: 7266027

Claim:
An integrated semiconductor memory with test circuit, comprising: an external terminal; a word line; a terminal for applying a first voltage potential; a terminal for applying a second voltage potential; a first controllable switch; a comparator circuit with a first input terminal for applying an input signal and a second input terminal for applying a reference signal and an output terminal for generating an evaluation signal, wherein a level of the reference signal lies between the first and second voltage potentials, and the evaluation signal generated by the comparator circuit on the output side is fed to the external terminal of the integrated semiconductor memory; and a second controllable switch, wherein the word line is connected via the first controllable switch to the terminal for applying the first voltage potential, the word line is connected via the second controllable switch to the terminal for applying a second voltage potential, the terminal for applying the second voltage potential is connected to the first input terminal of the comparator circuit, and the terminal for applying the second voltage potential is isolated from the second voltage potential.