Patent ID: 7913000

Claim:
A stacked memory apparatus providing read data in response to a read command and comprising: an interface device comprising; a main control circuit configured to generate a main buffer output signal and a main buffer input signal, and a main buffer configured to provide the read data to an external circuit in response to the main buffer output signal; and a plurality of memory devices vertically stacked on the interface device, wherein each memory device in the plurality of memory devices comprises; a memory core configured to provide the read data in response to a device read signal, a device buffer configured to receive the read data from the memory core in response to a device buffer input signal and provide the read data to the main buffer in response to a device buffer output signal, and a device control circuit receiving the read command and the main buffer input signal, and configured to generate the device read signal in response to the read command, the device buffer input signal in relation to a read data access delay associated with the memory core, and the device buffer output signal in relation to the main buffer input signal.