Patent ID: 7126229

Claim:
A semiconductor package, comprising: at least one chip having an active surface, wherein a plurality of first bonding points are formed on the active surface of the chip; a carrier having a plurality of conductive members and mounted with the chip thereon, wherein a plurality of second bonding points are formed on the conductive members; a plurality of first wires and a plurality of second wires alternatively arranged with the first wires in a staggered manner, wherein the first wires and the second wires electrically connect the first bonding points of the chip to the second bonding points on the conductive members of the carrier, and wire loops of the second wires are each downwardly deformed to form a deformed portion being lower in height than the active surface of the chip so as to provide a height difference between the wire loop of each of the second wires and that of each of the first wires; and an encapsulant for encapsulating the chip, the first wires, the second wires and a portion of the carrier.