Patent ID: 7339400

Claim:
A programmable logic device (PLD), comprising: an array of programmable tiles including a plurality of programmable logic resources and a plurality of programmable interconnect resources; a set of electrically programmable fuses that is electrically programmed with an identifier of the PLD, wherein a respective one of the electrically programmable fuses is electrically programmed with each of a plurality of bits of the identifier; an interface port including a control port and a first and second serial data signals, the interface port coupled to a subset of the programmable tiles, wherein the control port includes a clock signal, a read signal, and a shift signal; and a shift register coupled to the set of electrically programmable fuses and the interface port, the shift register having a parallel input port and serial input and output signals, the shift register adapted to load the identifier from the set of electrically programmable fuses via the parallel input port in response to a read command of the control port of the interface port, the shift register adapted to serially shift by one bit in response to a shift command of the control port of the interface port, including shifting a bit from the subset of the programmable tiles to the serial input signal of the shift register via the first serial data signal of the interface port and shifting a bit from the serial output signal of the shift register to the subset of the programmable tiles via the second serial data signal of the interface port.