Patent ID: 7394137

Claim:
A semiconductor device comprising: a semiconductor layer; a gate insulating layer formed above the semiconductor layer; a gate electrode formed above the gate insulating layer; a channel region formed in the semiconductor layer; a source region and a drain region formed in the semiconductor layer; a guard ring region formed in the semiconductor layer; an offset insulating layer formed in the semiconductor layer in a transistor formation region other than at least the channel region, the source region, and the drain region, the transistor formation region being enclosed by the guard ring region when viewed from a top side; a first interlayer dielectric formed above the semiconductor layer; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric formed above the first interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.