Patent ID: 7157333

Claim:
A method of fabricating a non-volatile memory, comprising: providing a substrate; forming a plurality of columns of isolation structures on the substrate; forming a plurality of rows of stacked gate structures, wherein the stacked gate structures cross over the isolation structures, and each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate; forming a plurality of doping regions in the substrate between two neighboring stacked gate structures; forming a plurality of stripes of spacers on the sidewalls of the stacked gate structures; forming a plurality of first dielectric layers on a portion of the isolation structures adjacent to two rows of stacked gate structures, wherein one isolation structure is between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and isolation structure are arranged in an interlacing manner; and forming a plurality of first conductive layers between two neighboring first dielectric layers in the same row.