Patent ID: 7652605

Claim:
A semiconductor device comprising: a first D/A converter circuit formed on a first semiconductor chip couples to a common node; a second D/A converter circuit formed on a second semiconductor chip couples to the common node; a clock generation circuit formed on the first semiconductor chip, couples to the common node, to generate a clock signal for the first D/A converter circuit and supply it to the first D/A converter circuit and a clock signal for the second D/A converter circuit and supply it to the second D/A converter circuit; a main processor formed on a third semiconductor chip that connects with the first D/A converter circuit, wherein the first D/A converter circuit receives a first data from the main processor; and a digital signaling processor formed on the first semiconductor chip that couples between the main processor and the second D/A converter circuit, wherein the second D/A converter circuit receives a third data generated by the digital signaling processor based on a second data supplied from the main processor.