Patent ID: 8119500

Claim:
A method comprising: bonding a first wafer to a lower surface of a second wafer, a first gap being defined by an unfilled area between outer edges of the first wafer and the second wafer after the bonding, each of the first wafer and the second wafer having electronic circuitry formed thereon; providing a sealing layer in the first gap, the sealing layer at least partially filling the first gap, but not extending over edges of the first wafer and the second wafer, wherein the edges of the second wafer comprise a non-perpendicular rounded shape joining a periphery of the lower surface with a periphery of an opposite upper surface of the second wafer, and wherein a diameter of the second wafer is larger within the second wafer than the lower or the upper surface of the second wafer; and thinning the second wafer after the providing until the sealing layer under the second wafer is exposed and until the upper surface of the second wafer has a diameter less than the first wafer and greater than the lower surface of the second wafer, a thinned surface of the second wafer being co-planar with a surface of the sealing layer, the thinning being performed on at least a portion of the second wafer overlying the sealing layer.