Patent ID: 8501602

Claim:
A method comprising: etching a plurality of trenches in a substrate; disposing a thin oxide layer on the substrate and in each of the plurality of trenches; disposing an isolation oxide over the thin oxide layer in each of the plurality of trenches; etching a cavity along at least one sidewall of each of the plurality of trenches to provide a respective exposed edge of the substrate in the cavity; depositing a doped polysilicon into the cavity; forming a doped region in the substrate directly adjacent to the doped polysilicon; etching the doped polysilicon in the cavity of a first of the plurality of trenches to form a drain of a transistor; and etching the doped polysilicon in the cavity of a second of the plurality of trenches to form a source of the transistor, wherein the first and second of the plurality of trenches are adjacent to one another.