Patent ID: 6980463

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a memory cell portion disposed above said semiconductor substrate; a first magneto resistive element disposed in said memory cell portion; a memory cell circuit including a bit line and a word line and disposed in said memory cell portion, said memory cell circuit directly writing data into said first magneto resistive element by generating a current magnetic field and electrically and directly reading out said data from said first magneto resistive element; and a peripheral circuit which is not included in said memory cell circuit and controls said memory cell circuit, the peripheral circuit being disposed outside said memory cell portion, at least a portion of said peripheral circuit being disposed in a region below said memory cell portion, said region being held between said first magneto resistive element and said semiconductor substrate, the peripheral circuit being electrically isolated from said first magneto resistive element in said memory cell portion, and said memory cell portion having a memory function and being a region where a plurality of first magneto resistive elements, each identical in function to said first magneto resistive element, are arranged in cyclic arrays.