Patent ID: 6901568

Claim:
A method for fabricating a transistor with a predetermined threshold voltage, comprising the steps of: forming a gate film of a transistor and measuring a film thickness of the gate film (S 101 ); forming a gate electrode of the transistor on the gate film and measuring a gate length of the gate electrode (S 102 ); inputting a fabrication parameter in fabrication of the transistor (S 103 ); determining whether or not the fabrication parameter deviates from a predetermined value of a fabrication parameter (S 104 ); when the fabrication parameter varies from the predetermined value, calculating a fabrication parameter discrepancy between the fabrication parameter and the predetermined value and predicting a deviation of the fabrication parameter (S 105 ); in a lamp-annealing step of the transistor to be subsequently fabricated, deciding an oxygen concentration in inert gas of the lamp annealing, corresponding to the variation of the fabrication parameter (S 106 ); forming source and drain regions of the transistor, respectively, by ion implantation (S 107 ), performing the lamp-annealing in the regions with the oxygen concentration in the inert gas of the lamp annealing (S 106 ) and setting the threshold value to the predetermined value; and in the case where the fabrication parameter does not deviate from the predetermined value in the Step S 104 , deciding the oxygen concentration in the inert gas of the lamp annealing to be 0% (S 110 ), and proceeding to Step S 107 .