Patent ID: 7380099

Claim:
A method comprising: generating a carry-in for at least one group of propagate and generate signals formed from a plurality of logical address components; generating a conditional sum for a logic 0 carry-in and an associated conditional sum for a logic 1 carry-in for the at least one group of propagate and generate signals; and selecting between the conditional sum for the logic 0 carry-in and for the associated conditional logic 1 carry-in according to the generated carry-in, wherein a first group of carry-in signals is generated during a first stage of an effective address calculation and prior to generation of a second group of carry-in signals during a second stage of the effective address calculation, the first group of carry-in signals to enable calculation of a first portion of an effective address during the first stage and prior to calculation of a second portion of the effective address during the second stage of the effective address calculation from the logical address components.