Patent ID: 7869290

Claim:
A NAND-type flash memory comprising: a memory cell array having NAND cells, each having memory cells capable of being rewritten electrically, a drain of one memory cell and a source of the other memory cell neighboring in a first direction being connected to each other, each of the NAND cells being arranged in a second direction; a plurality of bit lines, each being provided for each of the NAND cells; a plurality of sense amplifiers, each being provided for each of the bit lines; a plurality of data latch circuits, each being provided for each of the sense amplifiers, each of the data latch circuits temporarily holding data sent to and received from the corresponding sense amplifier; at least one test latch circuit which temporarily holds test data supplied from outside; and a data switching circuit which performs control for supplying at least two among the data latch circuits with data held in the test latch circuit.