Patent ID: 7962883

Claim:
A semiconductor circuit design method for designing a clock wiring structure supplying a clock to a flip-flop of a semiconductor circuit by using a computer, the computer comprising a logic synthesis processor, a gated-clock structure generator and a flip-flop replacement portion, the method comprising: in the logic synthesis processor, setting the flip-flop based on circuit information on a semiconductor integrated circuit; in the gated-clock structure generator, obtaining a control signal controlling the flip-flop; calculating a first evaluation value indicating a power consumption and a magnitude of a clock skew time when clock gating is applied to the flip-flop; and generating a gated clock structure for the flip-flop when the first evaluation value is higher than a first threshold; in the flip-flop replacement portion, selecting a type of flip-flop as a replacing candidate flip-flop based on a switching rate of a value held in the flip-flop per unit time; calculating a cell area and a timing margin of the flip-flop when the flip-flop is replaced by the replacing candidate flip-flop; and replacing the flip-flop by the replacing candidate flip-flop when the cell area and the timing margin of the flip-flop fall within allowable ranges, respectively.