Patent ID: 8900900

Claim:
A manufacturing method of an array substrate comprising: providing a substrate having a pixel region and a peripheral region adjacent to the pixel region; forming a plurality of pixel structures in the pixel region, wherein steps of forming at least one of the pixel structures comprise: forming a patterned first metal layer, a gate insulating layer, and a patterned second metal layer on the substrate, wherein the patterned first metal layer comprises a gate electrode, and the patterned second metal layer comprises a source electrode and a drain electrode ; forming a patterned semiconductor layer on the substrate, wherein the patterned semiconductor layer comprises a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern is substantially corresponding to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode, and the second semiconductor pattern covers a portion of the drain electrode; forming a first passivation layer on the substrate, wherein the first passivation layer has a first opening exposing a portion of the second semiconductor pattern; and forming a first patterned transparent conductive layer on the first passivation layer, wherein the first patterned transparent conductive layer comprises a transparent conductive pattern, the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.