Patent ID: 6861700

Claim:
Flash memory formed on an integrated circuit substrate, comprising: a plurality of global bit lines, a plurality of global control lines, a plurality of memory cell array segments that individually comprise a plurality of source and drain diffusions elongated in a first direction across the substrate and being spaced apart in a second direction, the first and second directions being perpendicular with each other, a two-dimensional array of charge storage elements with at least one charge storage element being coupled with at least a portion of individual memory cell channels formed between adjacent source and drain diffusions in the second direction, a plurality of control lines with lengths extending across the charge storage elements in the first direction forming control gates operably coupled therewith and being spaced apart in the second direction, a first plurality of select transistors connected between the plurality of source and drain diffusions and the plurality of global bit lines, and a second plurality of select transistors connected between the plurality of control lines and the plurality of global control lines, whereby the individual memory cell array segments may be selectively connected with the global bit and control lines by activating their respective first and second plurality of select transistors.