Patent ID: 7835188

Claim:
A memory device operable under a normal mode and a test mode, comprising: a plurality of memory cells each configured to exhibit two discrete states of positive and negative potentials to thereby store one bit of information; a comparator configured to switch a polarity of its output according to a relative voltage difference between a threshold voltage and a cell voltage across a drain and a source of a selected memory cell; a variable voltage source operable under the test mode to apply a progressively changing test voltage to a gate of the selected memory cell to progressively change a resistance of the selected memory cell; means for defining, under the normal mode, the relative voltage difference such that the comparator switches the polarity of its output under the normal mode so as to indicate the respective states of the selected memory cell, whereas under the test mode, adjusting according to the state of the selected memory cell one of (a) electric current flowing through the selected memory cell and (b) the threshold voltage, such that in the respective states of the selected memory cell, the comparator switches the polarity of its output under the test mode, as the variable voltage source progressively changes the test voltage within a measurable range.