Patent ID: 8707103

Claim:
A debugging apparatus for a computer system, comprising: a testing unit, testing said computer system and producing a power-on self-test code; a detecting unit, detecting if a debugging unit connects to said computer system, and producing a detecting signal containing information of one of a plurality of busses in said computer system to which said debugging unit electrically connects, wherein each bus of the plurality of busses is a different standard than the remaining busses; and a selection unit, selecting said bus of said computer system according to said detecting signal, and using said selected bus to output said power-on self-test code to said debugging unit; wherein said selection unit further comprises: a first multiplexer, receiving a clock signal; and a second multiplexer, receiving said power-on self-test code; where said first multiplexer and said second multiplexer output said clock signal and said power-on self-test code to said bus in said computer system according to said detecting signal.