Patent ID: 8514630

Claim:
In a memory circuit having memory cells of one or more arrays formed along word-lines, a method of determining whether one or more of the word-lines are defective, the method comprising: applying a voltage to a first array while all of the word-line selection switches thereof are turned off; establishing a first current level, where the first current level is the level of current drawn by the first array while all of the word-line selection switches thereof are turned off; applying the voltage to a second array while the word-line selection switches of a selected set of the word-lines of the second array are turned on and all of the other word-line selection switches for the second array are turned off; establishing a second current level, where the second current level is the level of current drawn by the second array while the word-line selection switches of the selected set of the word-lines of the second array are turned on and all of the other word-line selection switches for the second array are turned off; performing a comparison of the first and second current levels; and based upon the comparison, determining whether the selected set of word-lines includes one or more defective word-lines.