Patent ID: 8327072

Claim:
A method of data processing in a data processing system including a processor core having an associated upper level cache and a lower level victim cache, said method comprising: in response to a memory access request of the processor core: determining whether the memory access request hits or misses in a directory of the lower level victim cache; the upper level cache determining whether a castout from the upper level cache is to be performed and selecting a victim coherency granule for eviction from a congruence class in a set-associative data array in the upper level cache; in response to determining that a castout from the upper level cache is to be performed, the upper level cache evicting the selected victim coherency granule, wherein the evicting includes reading out the victim coherency granule from the congruence class in the set-associative data array of the upper level cache only in response to an indication that the memory access request misses in the directory of the lower level victim cache.