Patent ID: 7982483

Claim:
A circuit, comprising: a supply voltage terminal configured to receive a supply voltage of the circuit, wherein a trigger impulse is superimposed on the supply voltage; a signal terminal configured to output an output signal voltage of the circuit, wherein a bit of a data signal is superimposed on the output signal voltage; a detector configured to detect the trigger impulse and configured to provide a trigger signal in response to the trigger impulse; and an adjuster, which is implemented to extract the bit from the output signal voltage in response to the trigger signal in order to receive the bit and, configured to output a bit, superimpose the output signal voltage with the bit of the data signal in order to output the bit, wherein the adjuster configured to output the bit is implemented to impress an upper data voltage value on the output signal voltage when the bit to be output has a first logic value, and to impress a lower data voltage value on the output signal voltage when the bit has a second logic value.