Patent ID: 7965551

Claim:
A method for metal line arrangement being applied to a memory, which is a virtual ground array memory and has a plurality of memory cell blocks, each of the memory cell blocks having a plurality of memory cells, a plurality of select transistors corresponding to the memory cells, and m metal bit lines corresponding to the memory cells, comprising a metal bit line 0 , a metal bit line 1 , . . . , and a metal bit line (m−1), wherein m is a positive integer, the m metal bit lines are respectively and electrically connected to the corresponding memory cells via the select transistors, the metal bit line electrically connected to a drain of a target memory cell of the memory cells is defined as a drain metal bit line, and the metal bit line electrically connected to a source of the target memory cell is defined as a source metal bit line, the method comprising the steps of: arranging the m metal bit lines such that every charged up metal bit line of the arrangement is not adjacent to the source metal bit line, wherein the select transistors are controlled by n select signals, and when the target memory cell is being read, a first select signal of the n select signals turns on a first select transistor of the select transistors so that the drain of the target memory cell is electrically connected to the drain metal bit line, and a second select signal of the n select signals turns on a second select transistor of the select transistors so that the source of the target memory cell is electrically connected to the source metal bit line, n being a positive integer.