Patent ID: 8049273

Claim:
A power semiconductor device, comprising: a backside metal layer; a substrate formed on the backside metal layer; a semiconductor layer formed on the substrate, comprising: a first trench structure comprising a first gate oxide layer formed around a first trench with poly-Si implant; a second trench structure comprising a second gate oxide layer formed around a second trench with poly-Si implant; a p-base region formed between the first trench structure and the second trench structure; a plurality of n+ source regions formed on the p-base region and between the first trench structure and the second trench structure; and a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source regions; and a frontside metal region formed on the semiconductor layer and filling gaps formed between the plurality of n+ source regions on the p-base region, wherein the gaps are arranged in a chessboard form.