Patent ID: 7694255

Claim:
An electronic device including an electronic circuit capable of operating at a plurality of different operation speeds, the electronic device comprising: a delay circuit that applies time delays of different lengths to an input signal of the electronic circuit in accordance with the operation speeds, wherein the delay circuit comprises: a variable delay assigning section that outputs, in an actual operation of the electronic device, an input signal to a second device within the electronic circuit by being delayed by a first time delay that is varied according to characteristics of the electronic device, the input signal having been inputted either from an outside input terminal of the electronic device or from a first device within the electronic circuit; a low-speed operation delay assigning section that outputs, in low-speed operation of the electronic device, the input signal to the second device within the electronic circuit by being delayed by a second time delay having been pre-set, wherein the low-speed operation delay assigning section delays the input signal by the second time delay in the case of low-speed logic verification or a low-speed test of the electronic device; and a test register that sets a test mode in which the electronic device is subjected to the low-speed logic verification or the low-speed test, and wherein the low-speed operation delay assigning section outputs the input signal to the second device by being delayed by the second time delay, when the test mode has been set in the test register.