Patent ID: 7797578

Claim:
A motherboard-based tester that locates defects in memory chips without crashing comprising: a test adaptor board, having a test socket for receiving a memory chip under test for testing by the motherboard-based tester, the test adaptor board for electrically connecting the memory chip under test inserted into the test socket to a motherboard attached to the test adaptor board, the motherboard using the memory chip under test inserted into the test socket as a middle portion of a main memory of the motherboard; additional memory chips mounted on the test adaptor board, wherein the additional memory chips and the memory chip under test inserted into the test socket together form an emulated memory-module memory; wherein the motherboard is a main board for a computer using memory modules as the main memory; a first module slot on the motherboard, the first module slot connecting to a first memory module socket on a component side of the motherboard and having a first known good memory module inserted; a second module slot connecting to a location of a second memory module socket on the component side of the motherboard and also connecting to the test adaptor board, wherein the memory chip under test inserted into the test socket on the test adaptor board is accessed through the second module slot; a third module slot on the motherboard, the third module slot connecting to a third memory module socket on the component side of the motherboard and having a second known good memory module inserted; a copy of a basic input-output system (BIOS) stored in the second known good memory module; an operating system image stored in the first known good memory module; a test program stored in the first known good memory module, wherein the test program is executed by a processor on the motherboard that causes memory locations in the memory chip under test to be written and read without crashing the motherboard; and a defect location within the memory chip under test identified by the test program executing on the processor, the defect location being reported to a user, whereby the defect location is identified by the test program without crashing the motherboard by the test program that is not loaded into the memory chip under test.