Patent ID: 7030654

Claim:
A shifter circuit comprising: a matched translation stack comprising at least first and second stacks each of which comprising multiple transistors, the matched translation stack being configured to provide a primary logic level shift between a voltage level away from which a shift is desired (V ddL ) and a voltage level to which the shift is desired (V ddH ); one or more high voltage buffer stages at least one of which being connected with and biased by the matched translation stack, said at least one high voltage buffer stage comprising: multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack, the transistor stack being biased by said first stack of the matched translation stack, and being connected to receive an input supplied by said second stack of the matched translation stack; and an inverter comprising multiple inputs and an output, individual inverter inputs being connected to a respective intermediate node of the transistor stack; a low voltage buffer stage having an input and an output, the input being connected to an input voltage V in , and being connected between the voltage level away from which the shifted is desired (V ddL ) and a lower voltage; and an output buffer stage driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.