Patent ID: 7238981

Claim:
A non-volatile memory device comprising: a memory array of non-volatile memory cells to store data; control circuitry to control memory operations to the memory array; an address register to selectively couple address requests to the memory array; an input/output buffer to smooth out data flowing to and from the memory array; and a charge pump circuit to boost voltage levels during select memory operations, the charge pump circuit having capacitors, each capacitor including, a contiguous poly silicon layer, a discontinuous first metal layer overlying the poly silicon layer, the first metal layer having a first terminal and a second terminal, wherein discontinuities in the first metal layer separate the first terminal from the second terminal so that the first terminal is electrically isolated from the second terminal, wherein the discontinuities in the first metal layer overlie and align with portions of the poly silicon layer, and a contiguous second metal layer overlying the first metal layer, wherein portions of the second metal layer overlie and align with the discontinuities in the first metal layer.