Patent ID: 7829438

Claim:
A method of manufacturing a stacked microelectronic package comprising the steps of: (a) forming a first element including a first wafer and a second wafer overlying the first wafer, each of the first and second wafers including a plurality of microelectronic elements, a plurality of first saw lanes extending in a first direction and a plurality of second saw lanes extending in a second direction transverse to the first direction, a given first saw lane of the second wafer being aligned with and positioned above a given saw lane of the first wafer, wherein the plurality of first saw lanes and the plurality of second saw lanes extend between adjacent ones of the microelectronic elements of each wafer, at least one microelectronic element has a plurality of contacts exposed at a face of the first wafer or of the second wafer and a plurality of metal traces electrically connected with respective ones of the contacts and extending toward the aligned first saw lanes, and the first element further includes an insulating region extending in the first direction and aligned with the aligned first saw lanes; (b) forming at least one opening in the insulating region in alignment with the aligned first saw lanes, each at least one opening exposing no more than a single trace of the plurality of traces of the at least one microelectronic element; (c) forming a lead within the at least one opening, the lead being electrically connected to no more than a single trace of the at least one microelectronic element; and (d) severing the first and the second wafers along the aligned first saw lanes and through the insulating regions into a plurality of assemblies, each assembly including a plurality of stacked microelectronic elements and exposed leads.