Patent ID: 7876629

Claim:
A memory control circuit receiving a data signal and an original data strobe signal of a memory, the memory control circuit comprising: at least one first delay unit for generating at least a first data strobe signal, a second data strobe signal, and a third data strobe signal according to the original data strobe signal to provide at least three sampling points respectively; a sampling unit, coupled to the first delay unit, for sampling according to the data signal by utilizing the first data strobe signal, the second data strobe signal, and the third data strobe signal, to derive a first sample signal, a second sample signal, and a third sample signal respectively; a determining unit, coupled to the sampling unit, for comparing the first sample signal, the second sample signal, and the third sample signal to adjust spans between the sampling points respectively corresponding to the first data strobe signal, the second data strobe signal, and the third data strobe signal; and at least one second delay unit to provide an adjustable delay to the data signal, wherein the determining unit is coupled to control the adjustable delay provided by the second delay unit.