Patent ID: 8044831

Claim:
A decoding apparatus, comprising: a shifter which detects a start bit of a codeword from coded data; a memory which stores a first table, a second table and a third table, wherein the first table stores decode values of a plurality of symbol data at one address, the second table stores a shift amount of the shifter, and the third table is used to generate a data length of the decode values of the plurality of symbol data; a first decoder which is used to generate an address of the first table from the coded data; a second decoder which is used to generate an address of the second and third tables from the coded data; and an output unit which is used to couple or separate the decode values of the plurality of symbol data to data for a predetermined fixed number of bits; wherein the decoding apparatus decodes coded data generated by executing variable length coding to have a pixel block including a plurality of pixels (the number of pixels N) as a unit, and wherein letting P (bits) be a code size of the pixel block, T (pixels/clock cycle) be a target throughput, x (bits/clock cycle) be a code size to be processed per clock cycle, and y (pixels/clock cycle) be the number of pixels to be processed per clock cycle, at least either of: x ≧( P/N )× T and y≧T is satisfied.