Patent ID: 8144689

Claim:
A method, in an integrated circuit, for performing a synchronous operation across a synchronous/asynchronous clock domain boundary, comprising: switching one or more first devices in an asynchronous clock domain of the integrated circuit from an asynchronous clock mode of operation to a synchronous clock mode of operation; performing the synchronous operation using one or more second devices in a synchronous clock domain and the one or more first devices in the asynchronous clock domain of the integrated circuit; and returning the one or more first devices in the asynchronous clock domain of the integrated circuit to the asynchronous clock mode of operation, wherein switching the one or more first devices in an asynchronous clock domain from an asynchronous clock mode of operation to a synchronous clock mode of operation, comprises controlling a test mode input signal, a system clock enable signal, and an asynchronous clock hold signal so as to switch an input clock signal to the one or more first devices from a local asynchronous clock signal to a synchronous system clock signal, wherein the test mode input signal indicates whether latches in asynchronous clock distribution logic are permitted to be clocked by asynchronous signals or not, the system clock enable signal indicates whether the synchronous system clock signal is to be used or not, and the asynchronous clock hold signal controls switching between the local asynchronous clock signal and the synchronous system clock signal.