Patent ID: 7570089

Claim:
An output stage interface circuit for interfacing with a data bus, the interface circuit comprising: a first rail for receiving one of a high voltage and a low voltage of a power supply voltage, a second rail for receiving the other of the high voltage and the low voltage of the power supply voltage, a data output terminal for outputting data to the data bus, a first main switch element coupled between the data output terminal and the first rail for selectively determining at least one of a logic high and a logic low state of the data output terminal, the first main switch element comprising a first main MOS device having a gate and an independently configurable back gate, and being responsive to a first data control signal applied to the gate thereof for pulling the voltage on the data output terminal towards the voltage on the first rail for determining the one of the logic high and the logic low states of the data output terminal, and a first control circuit responsive to the voltage on the data output terminal being pulled from a first state across a first voltage reference to a second state for coupling the back gate of the first main MOS device to the data output terminal and for accommodating coupling of the gate of the first main MOS device to the data output terminal, so that the first main MOS device presents a high impedance on the data output terminal when the voltage on the data output terminal is pulled to the second state.