Patent ID: 8798206

Claim:
A digital input interface circuit comprising: a line carrying an input signal; a first optocoupler, a first resistor, and a second resistor, connected in series on the line; a capacitor connected in parallel with the first optocoupler and connected in series with the first resistor and with the second resistor; a Zener diode and at least one additional optocoupler connected in series, the Zener diode and the at least one additional optocoupler being connected in parallel with the capacitor, being connected in parallel with the first optocoupler, and being connected in series with the first resistor and with the second resistor; for each additional optocoupler, a corresponding input processor configured to receive electrical signals from a receiving side of the additional optocoupler; and a Latent Failure Detection (LFD) engine configured to receive signals from the at least one input processor and configured to send signals to open and close the first optocoupler, whereby in response to commands from one of the at least one input processor the LFD engine is able to send signals to the first optocoupler causing the first optocoupler to close for a predetermined duration and then open; wherein each of the at least one input processor is configured to determine a response time of the capacitor from signals received from the corresponding additional optocoupler, and wherein each of the at least one input processor is configured to determine that the digital input interface is unreliable if the input processor determines that the response time of the capacitor falls outside a predetermined range.