Patent ID: 7202566

Claim:
An integrated circuit device, comprising: a substrate; a plurality of microelectronic devices, each comprising a patterned feature located over the substrate, wherein the patterned feature comprises at least one electrical contact; a plurality of interconnect layers, each comprising a plurality of conductive members configured for distributing electrical power to one of the plurality of microelectronic devices, wherein the plurality of interconnect layers includes a first, second, and third interconnect layers, with the third interconnect layer adjacent the second interconnect layer and the second interconnect layer adjacent the first interconnect layer; the plurality of conductive members of the third interconnect layer straddle the plurality of conductive members of the second interconnect layer; and the plurality of conductive members of the second interconnect layer straddle the plurality of conductive members of the first interconnect layer; and a plurality of bond pads each connected to at least one of the plurality of conductive members of one of the plurality of interconnect layers.