Patent ID: 7761617

Claim:
A direct memory access (DMA) circuit, comprising: a read port; a read port scheduler coupled to the read port; a write port; a write port scheduler coupled to the write port; a request port coupled to the read and write port schedulers; thread circuitry for holding next access addresses, wherein the read port is configured to support “m” threads and the write port is configured to support “n” threads, where each thread is configured to support a single access and a burst access transaction and the read and write ports are configured to work on different data transfers at the same time; and channel context circuitry interconnected with the read port, write port and thread circuitry for storing channel context, wherein the channel context circuitry is configured to instantiate a plurality of virtual channels in excess of the number of threads, such that a free thread is associated with a selected virtual channel to initiate an access and then released.