Patent ID: 7205853

Claim:
A method for configuring a phase-locked loop circuit (PLL), said method comprising: inducing a frequency output from a voltage-controlled oscillator, wherein said frequency output comprises a substantially minimum or a substantially maximum for the voltage-controlled oscillator and said inducing comprises manipulating inputs to a charge pump, wherein the charge pump is configured to provide input to the voltage-controlled-oscillator; asserting a test signal prior to said inducing, wherein said PLL operates normally when a test signal is unasserted: providing a control signal, wherein the frequency output is a minimum frequency when the control signal is unasserted, and wherein the frequency output is a maximum frequency when the control signal is asserted; configuring a phase-frequency-detector, wherein the phase-frequency-detector has outputs coincident with inputs to the charge pump, and wherein said configuring comprises adapting to receive as inputs said test signal and said control signal; and configuring a divider, wherein said configuring comprises setting a dividing ratio based on said frequency output, wherein said configuring comprises measuring said frequency output and selecting a dividing ratio based on said measured frequency output.