Patent ID: 7081758

Claim:
An inspection method of a semiconductor device, wherein the semiconductor device includes a multi-layer wiring structure, and an inspection pattern for detection of a latent defect of the multi-layer wiring structure; and wherein the inspection pattern includes: a plurality of lower-layer wiring portions arranged so as to be spaced at a distance; a plurality of upper-layer wiring portions arranged so as to be spaced at a distance; an insulating layer provided between the plurality of lower-layer wiring portions and the plurality of upper-layer wiring portions; a plurality of contact units which electrically connects the plurality of lower-layer wiring portions and the plurality of upper-layer wiring portions so as to form a contact chain including the plurality of lower-layer wiring portions and the plurality of upper-layer wiring portions alternately connected in series; and a pair of electrode terminals, one of the electrode terminals being electrically connected to one end of the contact chain, the other of the electrode terminals being electrically connected to the other end of the contact chain; the inspection method comprising: acquiring an applied-voltage versus measured-current characteristic of the inspection pattern by applying a voltage to between the pair of electrode terminals and measuring a current flowing through the contact chain for a plurality of applied-voltages having different values; and judging presence or absence of a latent defect of the inspection pattern on the basis of the applied-voltage versus measured-current characteristic of the inspection pattern.