Patent ID: 8436800

Claim:
A shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages comprising: a first thin film transistor configured to have one main electrode connected to a clock input terminal and the other main electrode connected to an output terminal; a second thin film transistor configured to have one main electrode connected to the output terminal and the other main electrode connected to a first power supply; a 3(1)-th thin film transistor configured to have one main electrode connected to the first power supply and the other main electrode connected to a control interconnect of the second thin film transistor; a 3(2)-th thin film transistor configured to have one main electrode connected to the first power supply, the other main electrode electrically connected to the control interconnect of the second thin film transistor, and a control electrode electrically connected to a control interconnect of the first thin film transistor; a 4(1)-th thin film transistor configured to have one main electrode connected to the first power supply and the other main electrode electrically connected to the control interconnect of the first thin film transistor; a 4(2)-th thin film transistor configured to have one main electrode connected to the first power supply, the other main electrode connected to the control interconnect of the first thin film transistor, and a control electrode electrically connected to the control interconnect of the second thin film transistor; a fifth thin film transistor configured to have one main electrode connected to a second power supply, the other main electrode connected to the control interconnect of the second thin film transistor, and a control electrode electrically connected to a control interconnect of the 4(1)-th thin film transistor and a second input terminal; and a sixth thin film transistor configured to have one main electrode connected to the second power supply, the other main electrode connected to the control interconnect of the first thin film transistor, and a control electrode connected to a control interconnect of the 3(1)-th thin film transistor and a first input terminal.