Patent ID: 7795940

Claim:
A design structure embodied in a machine readable medium used in a design flow process, said design structure comprising a phase adjusting circuit comprising: an input node for receiving a first signal; an output node; a variable delay device comprising a plurality of field effect transistors comprising input diffusion regions adapted to be selectively biased, gates connected in series to said input node such that said first signal is propagated to said gates sequentially and output diffusions regions connected in parallel to said output node; and a current source connected to said output node and adapted to bias said output node when all of said field effect transistors are off, wherein a second signal is transmitted through a selected field effect transistor to said output node when an input diffusion region of said selected field effect transistor is selectively biased and when an active edge of said first signal is propagated from said input node to a gate of said selected field effect transistor, and wherein a phase difference between said first signal and said second signal is based on delay in propagation of said first signal from said input node to said gate.