Patent ID: 8426268

Claim:
A method of forming a memory cell in a semiconductor device, comprising: forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall, wherein the layered semiconductor structure comprises a buried insulating layer over a bulk layer, a semiconductor-on-insulator (SOI) layer over the buried insulating layer, and a dielectric layer over the SOI layer; filling the trenches with polysilicon; forming a patterning layer over the layered semiconductor structure; patterning an opening through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench; and etching the trenches and layered semiconductor structure, wherein said etching the trenches and the layered semiconductor structure comprises: performing a first vertical reactive ion etch (RIE) process to remove the dielectric layer between the trenches; and performing a second vertical RIE process to remove the patterning layer, the SOI layer between the trenches, and only the vertical portion of the polysilicon along the inner sidewall of each trench.