Patent ID: 7671411

Claim:
A transistor comprising: a p-type substrate; a high voltage (HV) n-well formed in a surface area of the p-type substrate; a source including: a p-doped p-body implanted in the HV n-well, a p-doped p+ region within the p-body, a first n-doped n+ region within the p-body and abutting the p+ region, the n+ region being on a side of the p-doped p+ region closer to the gate, and a n-doped lightly doped source (N-LDS) region overlapping the first n-doped n+ region and extending laterally beneath a portion of the gate, a drain including a second n-doped n+ region; and a gate to control a depletion region between the source and the drain, wherein the n-doped lightly doped source is implanted only in the source and not in the drain.