Patent ID: 7570539

Claim:
A computer implemented method for identifying bit cells and connections, the method comprising: receiving a bit cell netlist; defining a reference bit pattern for each bit cell node in at least one memory bit cell, wherein each reference bit pattern comprises a combination of bit values, and wherein each combination of bit values indicates a type of memory bit cell node; receiving a circuit block netlist associated with a circuit block to be analyzed; defining a node pattern for each node in the circuit block; matching the node patterns of the circuit block with the reference bit patterns of the at least one memory bit cell; identifying at least one type of memory bit cell node in the circuit block based on a combination of different matched reference bit patterns, wherein the at least one type of memory bit cell node is a single-port bit cell if the memory bit cell node comprises cross-coupled memory bit cell nodes each having a bit pattern [1,1,1,1,1], wherein the bit pattern [1,1,1,1,1] indicates that there is 1 pass-gate drain connection, 1 pull-down drain connection, 1 pull-down gate connection, 1 pull-up gate connection, and 1 pull-up drain connection; and wherein the at least one type of memory bit cell node is a multi-port bit cell if the memory bit cell node comprises cross-coupled memory bit cell nodes each having one of two bit patterns [1,1,1,1,1] or [1,1,2,1,1], wherein the bit pattern [1,1,1,1,1] indicates that there is 1 pass-gate drain connection, 1 pull-down drain connection, 1 pull-down gate connection, 1 pull-up gate connection, and 1 pull-up drain connection, wherein the bit pattern [1,1,2,1,1] indicates that there is 1 pass-gate drain connection, 1 pull-down drain connection, 2 pull-down gate connections, 1 pull-up gate connection, and 1 pull-up drain connection, wherein a multi-port bit cell further comprises a read port memory bit cell node each having a bit pattern [1,1,0,0,0], wherein the bit pattern [1,1,0,0,0] indicates that there is 1 pass-gate drain connection, 1 pull-down drain connection, 0 pull-down gate connection, 0 pull-up gate connection, and 0 pull-up drain connection; identifying at least one type of memory bit cell in the circuit block based on the at least one identified type of memory bit cell node; and identifying memory bit cells in the circuit block and corresponding bit line connections and word line connections in the circuit block based on the at least one identified type of memory bit cell.