Patent ID: 8738836

Claim:
A non-volatile memory device, comprising: a non-volatile memory cell array having a plurality of memory cells for storing multi-values by setting a plurality of different threshold voltages for each memory cell of the memory cell array; and a control circuit, controlling a write-in operation to the memory cell array, wherein when data has been written into a memory cell, the control circuit selects an adjacent word line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page, such that a narrow-banded erasing level distribution is realized in an adjacent memory cell, the data of one page being a set of bit data which is to be written into a plurality of memory cells on a word line during one write-in operation, and the control circuit stores LSB (Least Significant Bit) data which is to be written into the memory cell which is an operation target, in the second latch, responds to a program generating command of a write-in instruction, transfers the LSB data from the second latch to a first latch for copying, writes the LSB data into the memory cell, and then selects an adjacent word line which the LSB data is to be written in next in a column direction on an identical bit line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page.