Patent ID: 8614110

Claim:
A method comprising the steps of: providing a first silicon-on-insulator (SOI) wafer comprising a first SOI wafer device layer, a first SOI wafer buried oxide (BOX) layer directly coupled to the first SOI wafer device layer, and a first SOI wafer handle layer directly coupled to the first SOI wafer BOX layer, wherein the first SOI wafer handle layer has multiple cavities extending therethrough that substantially define a proof mass, wherein the multiple cavities are separated by tethered regions connecting the proof mass to a support structure, the tethered regions formed within the first SOI wafer handle layer; bonding a second SOI wafer to the first SOI wafer, the second SOI wafer comprising a second SOI wafer oxide layer, and a second SOI wafer device layer directly coupled to the second SOI wafer oxide layer, wherein the second SOI wafer is bonded to the first SOI wafer such that the second SOI wafer oxide layer is directly coupled to the first SOI wafer handle layer; forming an upper spring system by etching more than one portions of the second SOI wafer device layer proximate to the multiple cavities; and forming a lower spring system by etching more than one portions of the first SOI wafer device layer proximate to the multiple cavities.