Patent ID: 7430264

Claim:
A method for reducing transient current swings during mode transitions of high frequency/high power circuits, comprising: providing a high frequency clocking signal; and reducing the frequency over a plurality of pulses to control rate of change of current consumption from a power supply, wherein reducing the frequency over a plurality of pulses comprises: generating, by a finite state machine, an n-bit shift register input and a load signal; receiving, by an n-bit ring shift register divider, the load signal and the n-bit shift register input; responsive to the load signal being asserted generating, by the n-bit ring shift register divider, a register output; receiving the load signal, the high frequency clocking signal, and the register output at a logic module; masking, by the logic module, the high frequency clocking signal according to the register output to generate a divided clock signal and selecting, by the logic module, between the high frequency clocking signal and the divided clock signal based on the load signal.