Patent ID: 7335598

Claim:
A chemical mechanical polishing process for manufacturing a semiconductor device, comprising the steps of: forming a conductive layer over a first dielectric layer formed over a semiconductor substrate; patterning said conductive layer to form a patterned conductive layer with multiple first openings; forming at least one second dielectric layer to cover said patterned conductive layer and to fill said multiple first openings, said at least one dielectric layer having a first thickness; polishing said at least one second dielectric layer to form a planar surface; forming at least one cap layer over said planar surface having a second thickness and covering scratches formed in said at least one second dielectric layer during said polishing step, and which second thickness is substantially less than said first thickness, wherein said at least one cap layer and said at least one second dielectric layer are formed by using different deposition processes and/or using different materials; patterning said at least one cap layer and said at least one dielectric layer to form multiple second openings; and forming conductive vias in said multiple second openings.