Patent ID: 8243517

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell unit including a plurality of electrically connected memory cells, each memory cell having an electric charge accumulation layer and a control gate stacked thereon; and a source side selection transistor electrically connected to said memory cell of one end of said plurality of memory cells; and a drain side selection transistor electrically connected to the other end of said plurality of memory cells; a plurality of word lines each of which is electrically connected to a control electrode of one of said plurality of memory cells; a source line which is electrically connected to said source side selection transistor; and a gate control circuit, in which on a data readout operation, said drain side selection transistor is operated after the operation of said source side selection transistor when the number of memory cells between a selected memory cell and said source side selection memory cell is equal to a predetermined number, and said source side selection transistor is operated after the operation of said drain side selection transistor when the number of memory cells between a selected memory cell and said source side selection memory cell is greater than said predetermined number by one.