Patent ID: 7982538

Claim:
A differential output circuit comprising: a first current mirror circuit; a second current mirror circuit; a first load resistor and a second load resistor that are connected at respective ends; and a bias power supply to bias a connecting node between a first end of said first load resistor and a first end of said second load resistor to a predetermined potential, wherein said first current mirror circuit comprises: a first master transistor having a gate and a drain, a first current source connected to said drain of said first master transistor, a first slave transistor having a drain connected to a second end of said first load resistor, and a first voltage follower to supply a first gate voltage of said first master transistor to a gate of said first slave transistor, where a first slew rate at a rise time is equal to a first slew rate at a fall time, and said second current mirror circuit comprises: a second master transistor having a gate and a drain, a second current source connected to said drain of said second master transistor, a second slave transistor having a drain connected to a second end of said second load resistor, and a second voltage follower to supply a second gate voltage of said second master transistor to a gate of said second slave transistor, where a second slew rate at a rise time is equal to a second slew rate at a fall time.