Patent ID: 8681918

Claim:
A method for recovery of a clock from a received digital data stream, the method comprising: a) generating N phase-shifted dock signals; b) determining one of the N phase-shifted clock signals as a clock signal M; c) determining another one of the N phase-shifted dock signals as a clock signal R, wherein the phase of the clock signal R differs from the phase of the clock signal M by a first predetermined phase-shift; d) determining another one of the N phase-shifted clock signals as a clock signal L, wherein the phase of the clock signal L differs from the phase of the clock signal M by a second predetermined phase-shift; e) selecting a rising/falling edge of the clock signal M; f) selecting in the clock signal R a rising/falling edge that is nearest in the positive time direction to the selected rising/falling edge of the clock signal M; g) selecting in the clock signal L a rising/falling edge that is nearest in the negative time direction to the selected rising/falling edge of the clock signal M; h) determining an I-value, an m-value and an r-value by respectively sampling the received digital data stream at the selected rising/falling edges of the clock signals L, M, and R; i) increasing a counter value LC by a predetermined amount, if the I-value differs from the m-value; j) increasing a counter value RC by the predetermined amount, if the r-value differs from the m-value; k) selecting one of the N phase-shifted clock signals which has a phase that differs from the phase of the clock signal M and defining the selected signal as the clock signal M if the counter value LC is greater than the counter value RC; and l) selecting one of the N phase-shifted clock signals which has a phase that differs from the phase of the dock signal M and defining the selected signal as the dock signal M if the counter value RC is greater than the counter value LC wherein N is an integer; M, L, and R respectively denote middle, left, and right; m-value, I-value, and r-value are digital values; LC and RC are counter values; and wherein the method is practiced by a clock recovery circuit.