Patent ID: 7523331

Claim:
An apparatus that is switchable to a low power operating mode and to a normal operating mode, the apparatus comprising: an instruction processing circuit; a main memory for providing instructions for the instruction processing circuit during execution by the instruction processing circuit; a cache memory coupled between the instruction processing circuit and the main memory, operable in the normal operating mode to cache a part of data and/or instructions that the instruction processing circuit addresses in the main memory during execution, and to substitute cached data and/or instructions when the instruction processing circuit addresses the data and/or instructions in the main memory; low power operating mode activating circuit, arranged to keep part of the apparatus deactivated during operation in the low power operating mode, said part of the apparatus including the main memory, but excluding at least part of the cache memory, the low power mode activating circuit being arranged to load a program of instructions for executing a function during operation in the low power operating mode into said at least part of the cache memory before switching to the low power operating mode; wherein the instruction processing circuit is configured to: detect when it is no longer necessary to operate in the normal operating mode; cause the program of instructions to be loaded into the cache memory when the instruction processing circuit has determined that it is no longer necessary to operate in the normal operating mode; and signal to a main power supply circuit to deactivate itself when the instruction processing circuit has determined that it is no longer necessary to operate in the normal operating mode, wherein a cache management unit of the cache memory is deactivated in the low power operating mode.