Patent ID: 8140803

Claim:
A design structure embodied in a non-transitory machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: a processor memory system comprising: a processor; and a memory controller in communication with the processor through a bus, the memory controller comprising: a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data; and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus, wherein the delay adjustment circuit operates in multiple modes for adjusting the predetermined delay, including a manual mode, an automatic mode, and a speed up mode, the speed up mode being a mode of operation that is useable responsive to the processor or the bus leaving a low power state.