Patent ID: 8520571

Claim:
An integrated circuit comprising: a memory that stores a first task list and a second task list; a first buffer; a second buffer; a third buffer; a bus coupled to the memory; a first Wireless Communication System Modem Sub-Circuit (WCSMSC) adapted to read task instructions of the first task list out of the memory across the bus, wherein a first task instruction of the first task list includes a source address field and a destination address field, wherein the source address field contains a source address value that identifies where in the first buffer input data for a first operation to be performed by the first WCSMSC is stored, wherein the destination address field contains a destination address value that identifies where in the second buffer the first WCSMSC will write data results of the first operation, wherein a second task instruction of the first task list is a push task instruction that causes the first WCSMSC to write identified data into the memory; a second WCSMSC adapted to read task instructions of the second task list out of the memory across the bus, wherein a first task instruction of the second task list configures the second WCSMSC to perform a second operation, wherein a second task instruction of the second task list includes a source address field and a destination address field, wherein the source address field contains a source address value that identifies where in the second buffer input data for the second operation to be performed by the second WCSMSC is stored, and wherein the destination address field contains a destination address value that identifies where in the third buffer the second WCSMSC will write data results of the second operation; and a processor adapted to maintain the first and second task lists, wherein the processor uses the data written into the memory as a result of the push task instruction to make a determination.