Patent ID: 8739091

Claim:
A computer-performed method performed by a general-purpose computer system that verifies a logic design, the method comprising: capturing behavior of at least a portion of the logic design with a computer system to obtain a sequence of events during sequential simulation or operation of the logic design; segmenting results of the capturing into multiple segments corresponding to different sequential intervals of the simulation or operation, wherein the multiple segments are stored within the computer system; processing, by the computer system, the segments individually to verify the behavior of the portion of the at least a portion of logic design, wherein the processing comprises reading individual ones of the multiple segments, checking correspondences between events stored in a current segment, and additional information indicating events in the simulating or operation of the logic design corresponding to a segment other than the current segment; checking the events stored in the corresponding ones of the multiple segments for correct resulting events, wherein the checking checks for resulting events within the current segment; responsive to the checking not finding a resulting event corresponding to a causative event in the current segment, concatenating at least a portion of a next one of the multiple segments with the current segment to provide the additional information; and repeating the checking on the concatenated current segment.