Patent ID: 8796817

Claim:
A semiconductor device comprising: a multilayer substrate having upper and lower surfaces and a permittivity; a semiconductor element secured to said upper surface of said multilayer substrate; an intra-substrate via that is connected electrically to said semiconductor element and located in said multilayer substrate, extending to said lower surface of said multilayer substrate; a first metal pattern located on a portion of said lower surface of said multilayer substrate; a second metal pattern in contact with a lower end of said intra-substrate via; a dielectric having a higher permittivity than the permittivity of said multilayer substrate and located on said lower surface of said multilayer substrate, covering said first and second metal patterns; a first intra-dielectric via located in said dielectric, connected at an upper end to said first metal pattern, and extending to a lower surface of said dielectric; a second intra-dielectric via located in said dielectric, connected at an upper end to said second metal pattern, and extending to said lower surface of said dielectric; a ground pattern connected to a lower end of said first intra-dielectric via; and a bottom surface electrode connected to a lower end of said second intra-dielectric via, wherein a portion of said first metal pattern is disposed on said dielectric directly opposite a portion of said bottom surface electrode, and said bottom surface electrode, said dielectric, and said first metal pattern, together, constitute a bypass capacitor.