Patent ID: 6987685

Claim:
A readout circuit comprising: a line memory constituted by a plurality of memory units for holding signals; first switches, each connected to each memory unit of said line memory; a first common signal line comprising a predetermined number of said first switches connected together, and a second switch for connecting said first common signal line to a second common signal line; a signal readout unit for selectively reading out signals to be held in each memory unit of said line memory on said second common signal line via said first switch, said first common signal line, and said second switch; and a control unit for controlling opening/closing of said first and second switches, wherein said readout circuit has outgoing wiring to be provided between an electrode of said second switch and said second common signal line, and control wiring for being connected from said control unit to at least either said first switch or said second switch, wherein said control wiring has first signal supply wiring and anti-signal second signal supply wiring to which a pair of a first signal and a second signal an anti-signal, in which a logical level has been reversed with respect to each other, are respectively supplied, and wherein said positive first signal supply wiring and said anti-signal second signal supply wiring are arranged so as to be line-symmetric with respect to said outgoing wiring.