Patent ID: 7813156

Claim:
A semiconductor device comprising: a plurality of first and second word lines; a first bit line; a second bit line; a third bit line; a fourth bit line; a plurality of first memory cells provided at intersections of said first word lines and said first bit line; a plurality of second memory cells provided at intersections of said second word lines and said second bit line; a first MOSFET having a source and drain path coupled to said first bit line and said third bit line; a second MOSFET having a source and drain path coupled to said second bit line and said fourth bit line; a sense amplifier coupled to said third and fourth bit lines; a first control line coupled to a gate of said first MOSFET; and a second control line coupled to a gate of said second MOSFET, wherein when one of said plurality of first word lines is selected, said first MOSFET is in on-state and said first MOSFET is in off-state during a rewriting operation, and wherein when one of said plurality of second word lines is selected, said second MOSFET is in on-state and said first MOSFET is in off-state during said rewriting operation.