Patent ID: 6959398

Claim:
A computer system, comprising: a first logic circuit; a second logic circuit; and an interface coupling the first logic circuit to the second logic circuit, wherein the interface includes: an input logic block that receives an incoming data stream and a first clock from the first logic circuit, the input logic block provides an intermediate signal, wherein if the incoming data stream includes a first asserted signal, the intermediate signal inverts its logic state, wherein the input logic block includes; a multiplexor, the multiplexor receives the incoming data stream; and a first register coupled to the multiplexor; the first register is clocked by the first clock; wherein the multiplexor provides the first register the inverted version of the output of the first register when the incoming data stream includes the first asserted signal, the first register provides the intermediate signal; and an output logic block coupled to the input logic block, the output logic block receives the intermediate signal and a second clock, wherein the output logic block provides to the second logic circuit an output signal, the output signal is a second asserted signal for one clock period of the second clock, when the output logic block detects a logic state change in the intermediate signal.