Patent ID: 8086989

Claim:
A circuit design structure of a circuit design tangibly embodied in a machine readable device for processing by a design process, the circuit design structure, when processed by a processor, generating a physical representation comprising: a circuit for managing clock signal switching with logic devices, comprising: an asynchronous clock group comprising one or more glitchless control blocks for outputting asynchronous clock sources; one or more synchronous clock groups comprising a plurality of glitchless control blocks for outputting synchronous clock sources; and a multiplexer for receiving delayed input clock signals from the glitchless control blocks for the asynchronous clock sources and from the glitchless control blocks for the synchronous clock sources; wherein a switching latency from a first input clock signal which belongs to a synchronous clock group to a second input clock signal which belongs to a same synchronous clock group is less than one clock cycle of the second input clock signal; and wherein the switching latency is a period in which no clock pulse appears at a final output clock signal of the circuit.