Patent ID: 8422621

Claim:
A shift register comprising a plurality of stages for sequentially outputting scan pulses, wherein an nth one of the stages (where n is a natural number) comprises: a node controller for controlling voltages at nodes; and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage in response to the voltages at the nodes, wherein the nodes comprise a set node, a first reset node and a second reset node, wherein the node controller of the nth stage comprises: a first switching device controlled by a voltage supplied to the first reset node for supplying a second discharging voltage to the set node; a second switching device controlled by a voltage supplied to the second reset node for supplying the second discharging voltage to the set node; a first inverter circuit controlled by a voltage supplied to the set node for supplying any one of a first charging voltage and a third discharging voltage to the first reset node; and a second inverter circuit controlled by the voltage supplied to the set node for supplying any one of a second charging voltage and a fourth discharging voltage to the second reset node, and wherein the third discharging voltage and the fourth discharging voltage are lower than the second discharging voltage.