Patent ID: 6901010

Claim:
A methodology of erasing flash memory cells in a multi-bit flash memory array with bits in the flash memory cells disposed in normal and complimentary locations, the methodology comprising: (a) programming all cells in a sector of the multi-bit flash memory array; (b) setting an address location to an initial setting; (c) performing an erase verify of a bit in a normal bit location; (d) if the bit does not verify as erased, determining if a maximum erase pulse count has been reached; (e) if the maximum erase pulse count has been reached, a failure is indicated and the erase methodology is terminated; (f) if the maximum pulse count has not been reached applying an erase pulse to the normal and complimentary bit locations; (g) performing an erase verify of a bit in a complimentary bit location; (h) if the bit does not verify as erased, determining if the maximum erase pulse count has been reached; (i) if the maximum erase pulse count has been reached, a failure is indicated and the erase methodology is terminated; (j) if the maximum pulse count has not been reached applying an erase pulse to complimentary and normal bit locations.