Patent ID: 6878982

Claim:
A method of forming a contact structure for a ferroelectric memory device integrated in a semiconductor substrate and including a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor; said MOS device having first and second conduction terminals and being covered with an insulating layer; and said ferroelectric capacitor having lower plate formed on said insulating layer above said first conduction terminal and coupled to said first conduction terminal, and said lower plate being covered with a layer of a ferroelectric material and coupled capacitively to an upper plate, the method comprising: forming a first plurality of plugs by forming a first plurality of openings in the insulating layer, the first plurality of openings extending from the first conduction terminals to the lower plates of the ferroelectric capacitors, lining the first plurality of openings with a conductive material, and filling the first plurality of openings with a non-conductive material; and forming a second plurality of plugs by forming a second plurality of openings in the insulating layer, the second plurality of openings extending from the second conduction terminals, lining the second plurality of openings with a conductive material, and filling the second plurality of openings with a conductive material.