Patent ID: 8498170

Claim:
A semiconductor memory device, comprising: first and second memory cell array regions having a plurality of memory cells, respectively; a plurality of sense amplifiers driving bit lines to which the memory cells are connected, the sense amplifiers having a plurality of first transistors and a plurality of second transistors which are arranged between the first and second memory cell array regions, each of the first transistors comprising a first diffusion region in a first well region, each of the second transistors comprising a second diffusion region in a second well region, the second well region being adjacent to the first well region and being different conductivity type from the first well region; a plurality of sense amplifier drivers controlling the sense amplifiers, each of the sense amplifier drivers having a first driver transistor and a second driver transistor, the first and second driver transistors arranged in the first and second well regions, respectively, the first and second driver transistors facing first and second boundaries between the first and second well regions, respectively, the first boundary being farther from the first memory cell array region than the second boundary; and wherein the first diffusion region has a first side facing the first memory cell array region, the second diffusion region has a second side facing the second memory cell array region, a distance from the first side to the second side is shorter than a sum of a first distance from the first side to the first boundary and a second distance from the second side to the second boundary.