Patent ID: 7626432

Claim:
A DLL circuit comprising: an input circuit configured to generate a synchronization reference signal on the basis of an input signal; a first delay unit configured to delay the synchronization reference signal; a timing offset circuit configured to adjust a synchronization position of the synchronization reference signal delayed by the first delay unit to generate a signal to be synchronized; a phase comparison circuit configured to compare phase of the synchronization reference signal with that of the signal to be synchronized; a first control circuit configured to select an output signal of the first delay unit on the basis of a comparison result of the phase comparison circuit; a second delay unit configured to delay one of the synchronization reference signal or the signal to be synchronized; and a second control circuit configured to select an output signal of the second delay unit in the case where the comparison result of the phase comparison circuit is within a predetermined range, wherein the phase comparison circuit compares the phase of the one of the synchronization reference signal or the signal to be synchronized that is delayed by the second delay unit with the phase of the other of the synchronization reference signal or the signal to be synchronized not delayed by the second delay unit.