Patent ID: 8775888

Claim:
An integrated circuit comprising: a block of circuitry components operable to generate internal operational signals for performing designated functions; a test multiplexer (MUX) hierarchy coupled to receive the internal operational signals and controllably operable to select subsets of the internal operational signals for acquisition and to apply the selected subsets to a testing element; a clock generator operable to generate a clock signal for the signals selected via the test MUX hierarchy; a test logic timer operable to receive the clock signal, to increment a counter value based upon the clock signal, and further operable to apply the counter value to the testing element; and an event detector operable to reset the counter value to a predefined value upon detection of an event, such that a first subset of the internal operational signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event are correlated in time with a second subset of the internal operational signals acquired responsive to detection of a second instance of the event.