Patent ID: 8307539

Claim:
A method for modeling devices in a wafer, comprising the steps of: providing the wafer comprising a first plurality of devices having a track width TW and a first stripe height SH 1 , a second plurality of devices having the track width TW and a second stripe height SH 2 , and a third plurality of devices having the track width TW and a third stripe height SH 3 ; measuring resistance values for the first, second and third plurality of devices to obtain a data set correlating a stripe height and a resistance value for each of the first, second and third plurality of devices; and estimating a linear relationship between resistance and inverse stripe height for the first, second and third plurality of devices based on the data set, wherein SH 1 differs from SH 2 by a first predetermined amount δH 1 , and wherein SH 2 differs from SH 3 by a second predetermined amount δH 2 , such that SH 1 +δH 1 =SH 2 and SH 2 +δH 2 =SH 3 .