Patent ID: 7795929

Claim:
A voltage detection circuit, comprising: an input buffer comprising a current source and a first MOS transistor which are connected in series, which outputs a detection voltage which is input to a gate of the first MOS transistor as an input voltage; an output buffer comprising a second MOS transistor of a p-channel type having a source connected to a power supply and a drain connected to a signal output terminal, and a third MOS transistor of an n-channel type having a source grounded and a drain connected to the signal output terminal; a timing adjustment circuit having a signal input terminal connected to a drain of the first MOS transistor, a first output terminal connected to a gate of the second MOS transistor, a second output terminal connected to a gate of the third MOS transistor, which drops voltage of the first output terminal and voltage of the second output terminal when the input voltage that is input to the signal input terminal rises, raises the voltage of the first output terminal and the voltage of the second output terminal when the input voltage drops, and shifts dropping timing and raising timing between the voltage of the first output terminal and the voltage of the second output terminal; and a voltage detection section that accelerates rising and dropping speeds of the input voltage based on a change in the voltage of the first output terminal and the voltage of the second output terminal, and a change in a voltage of the signal output terminal.