Patent ID: 7018882

Claim:
A method of forming a substrate for use in CMOS device fabrication comprising: prepare a silicon substrate, including doping a bulk silicon ( 100 ) substrate with ions taken from the group of ions to form a doped substrate taken from the group of doped substrates consisting of n-type doped substrates and p-type doped substrates; forming a first relaxed SiGe layer on the silicon substrate; forming a first tensile-strained silicon cap on the first relaxed SiGe layer; forming a second relaxed SiGe layer on the first tensile-strained silicon cap; forming a second tensile-strained silicon cap on the second relaxed SiGe layer; and completing a CMOS device on the tensile-strained silicon cap, wherein the CMOS device includes a source region and a drain region which are both in electrical contact with a tensile-strained silicon cap, including well ion implantation, threshold voltage adjustment, STI device isolation, gate oxidation, gate electrode and sidewall nitride formation; etching of gate oxide after formation of sidewall nitride; etching of exposed second tensile-strained silicon cap to expose second relaxed SiGe layer in the source region and the drain region; selectively laterally etching of any SiGe layer at the source and drain region and selectively laterally etching of any SiGe layer located beneath the gate and nitride spacers, forming a resulting tunnel, which is left empty or filled with a dielectric.