Patent ID: 8729947

Claim:
A clock switching system comprising: a first clock domain subsystem that is clocked according to clock timing of a first input clock signal and comprises: a first domain pre-synchronization circuit operable to asynchronously receive a clock select signal and generate a synchronized clock select signal that is synchronized with respect to the clock timing of the first input clock signal; and a first domain disable circuit operable, using the synchronized clock select signal, to disable the first input clock signal from controlling a clock output signal after a disable delay that is a function of the clock timing of the first input clock signal; a second clock domain subsystem that is clocked according to clock timing of a second input clock signal, the clock timing of the second input clock signal being different from the clock timing of the first input clock signal, the second clock domain subsystem comprising: a second domain enable circuit operable, using the synchronized clock select signal, to enable the second clock signal to control the clock output signal after an enable delay that is a function of the clock timing of the second input clock signal and is longer than the disable delay; and a feedback delay circuit operable to prevent changes in the selection output from the enable select circuit after a transition in the selection output occurs for a feedback delay that is a function of the clock timing of the first input clock signal.