Patent ID: 7535048

Claim:
An array of memory cells configured to store at least one bit per one F 2 comprising: memory cells arranged in rows and columns each coupled to respective row and column decoding circuitry, wherein each memory cell comprises: first doped regions formed on a surface of a semiconductor substrate; an array of incisions formed into the substrate to provide an array of substantially vertical edge surfaces, pairs of the edge surfaces facing one another as sidewalls of a trench and spaced apart a distance equal to one half of a pitch of the array of edge surfaces; second doped regions formed only between the pairs of edge surfaces at the bottom of the trench; respective ONO structures each providing an electronic memory function, without an additional floating gate, disposed only on the vertical edge surfaces such that a nitride layer of the ONO structure is formed only on the vertical edge surfaces and a lower oxide layer of the ONO structure is formed, without the nitride layer, on the surface of the semiconductor substrate over the first doped regions and on the bottom of the trenches; a shared gate formed between the ONO structures; and electrical contacts to the first and second regions and to the structures providing the electronic memory function.