Patent ID: 7243208

Claim:
A data processor, comprising: a central processing unit; and an address translation unit that receives virtual addresses output from the central processing unit and outputs physical addresses; wherein the address translation unit includes a first translation lookaside buffer, a second translation lookaside buffer, and a control circuit for selecting one of the first and second translation lookaside buffers, wherein the control circuit selectively controls operation of the first and second translation lookaside buffers to selectively output a physical address based on stored enable information, wherein the control circuit includes storage for storing the stored enable information and a selector coupled to outputs of the first translation lookaside buffer and the second translation lookaside buffer, wherein the selector selectively operates to output the physical address based on the stored enable information, wherein upon reset of the date processor the stored enable information controls the selector so that it does not output any physical address from either the first translation lookaside buffer or the second translation lookaside buffer, wherein the address translation unit performs address translation in accordance with an area of a virtual address space of a virtual address received from the central processing unit.