Patent ID: 8014226

Claim:
An integrated circuit memory comprising: a first array of memory cells; a second array of memory cells; word line driver circuitry located between said first array and said second array; a first plurality of word lines extending from a first side of said word line driver circuitry through said first array; a second plurality of word lines extending from a second side of said word line driver circuitry through said second array; a first plurality of word line helper circuits coupled to respective word lines of said first plurality of word lines; and a second plurality of word line helper circuits coupled to respective word lines of said second plurality of word lines; wherein said word line driver circuitry is responsive to an access request to drive a first word line signal upon a first driven word line of said first plurality of word lines toward a first asserted value and to drive a second word line signal upon a second driven word line of said second plurality of word lines toward a second asserted value; said first plurality of word line helper circuits include a first word line helper circuit coupled to said first driven word line and switched by said first word line signal being driven toward said first asserted value to further drive said first word line signal toward said first asserted value such that said first word line signal value more rapidly reaches said first asserted value; and said second plurality of word line helper circuits include a second word line helper circuit coupled to said second driven word line and switched by said second word line signal being driven toward said second asserted value to further drive said second word line signal toward said second asserted value such that said second word line signal value more rapidly reaches said second asserted value.