Patent ID: 7501339

Claim:
A method for fabricating a multi-layer inter-metal dielectric semiconductor structure, comprising: fabricating metallization lines within a base dielectric layer by etching and filling with metallization; depositing a barrier over the metallization lines and the base dielectric layer; depositing an inorganic dielectric layer over the barrier; depositing a low dielectric constant (low K) layer over the deposited inorganic dielectric layer immediately after the inorganic dielectric layer is deposited, wherein a thickness of the low dielectric constant layer is greater than a thickness of the inorganic dielectric layer; etching a trench in the low K layer using a first etch chemistry, the etching being timed to etch through a partial thickness of the low K layer, and wherein the first etch chemistry is optimized to a selected low dielectric constant material; defining locations of via holes in the trench with a photoresist mask; etching the via holes through a remaining thickness of the low dielectric constant layer using the first etch chemistry; and etching the via holes through the inorganic dielectric layer to the barrier using a second etch chemistry, the second etch chemistry being highly selective to the barrier.