Patent ID: 8421146

Claim:
A semiconductor device comprising: an active region defined by an isolation region; an insulating pillar protruding from the active region; a first semiconductor pillar protruding from the active region and including a first side surface portion that is contact with a part of the insulating pillar, the first semiconductor pillar including a second side surface portion that is apart from the insulating pillar; a second semiconductor pillar protruding from the active region and including a third side surface portion that is contact with another part of the insulating pillar, the second semiconductor pillar including a fourth side surface portion that is apart from the insulating pillar; a gate insulating film covering at least the second side surface portion of the first semiconductor pillar and the fourth side surface portion of the second semiconductor pillar; a gate electrode formed on the gate insulation film to cover the second side surface portion of the first semiconductor pillar and the fourth side surface portion of the second semiconductor pillar; first and second diffusion regions for a first transistor that includes the second side surface portion of the first semiconductor pillar as a channel region; and third and fourth diffusion regions for a second transistor that includes the fourth side surface portion of the second semiconductor pillar as a channel region.