Patent ID: 8861553

Claim:
An asynchronous master-slave serial communication system, comprising: a master control module for generating a check code according to an address information and a data information, generating a data package according to the address information, the data information, the check code and a master clock signal, and transmitting the data package; and a slave control module for receiving the data package, generating a decoding data according to the data package and a slave clock signal, and generating the address information, the data information and the check code according to the decoding data, the slave control module comprising: a decoder for decoding the data package into a second serial data according to the slave clock signal; a data dividing circuit for dividing the second serial data into the address information and the data information, comprising: a serial-to-parallel shift register for outputting a parallel data according to the second serial data; and a data dividing latch device for outputting the address information and the data information according to the parallel data; and a second data error check device for outputting the check code according to the second serial data; wherein the master control module further comprises a control unit for setting a time interval between the data package and another data package.