Patent ID: 8406038

Claim:
A semiconductor device comprising: a plurality of memory cells comprising a first transistor and a second transistor; a reading circuit comprising an amplifier circuit and a switch element; and a refresh control circuit, wherein the first transistor comprises a first channel formation region, a first gate electrode, a first gate insulating layer between the first channel formation region and the first gate electrode, and a first source electrode and a first drain electrode electrically connected to the first channel formation region, wherein the second transistor comprises a second channel formation region, a second gate electrode, a second gate insulating layer between the second channel formation region and the second gate electrode, and a second source electrode and a second drain electrode electrically connected to the second channel formation region, wherein the first channel formation region and the second channel formation region contain different materials as respective main components, wherein the first gate electrode is electrically connected to one of the second source electrode and the second drain electrode, wherein the other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit, wherein an output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element, and wherein the refresh control circuit is configured to control whether the switch element is turned on or off.