Patent ID: 8836442

Claim:
An oscillation circuit comprising: a delay lock loop circuit configured to generate (i) a plurality of incremental delay line signals and (ii) a delay line output signal, wherein the plurality of incremental delay line signals and the delay line output signal are generated based on a clock signal received from an oscillator; a pulse-width modulation control module configured to generate a pulse-width modulation control signal; a tunable circuit configured to adjust operation of the oscillator, the tunable circuit comprising a transistor having a control terminal, a first terminal and a second terminal, the transistor configured to provide a variable impedance across the first terminal and the second terminal thereof based on an adjustment signal input to the control terminal, and a capacitance in communication with the oscillator and one of the first and second terminals; and a delay line selection circuit configured to generate the adjustment signal based on (i) the delay line output signal, (ii) the pulse-width modulation control signal, and (iii) one of the incremental delay line signals.