Patent ID: 7200730

Claim:
A method of operating a memory at a maximum rate, comprising: initiating a first memory operation; identifying a completion of the first memory operation; generating a cycle ready strobe signal upon the identified completion; employing the cycle ready strobe signal for initiation of a next memory operation; wherein initiating the first memory operation or initiating the next memory operation comprises: triggering a transition of an internal memory clock signal; transitioning a bit line precharge signal to disable a bit line precharge operation based on the transition of the internal memory clock signal; enabling selected row and column decoder circuitry for addressing one or more selected memory cells within the memory based on the transition of the internal memory clock signal; initiating a tracking circuit that waits a predetermined tracking time associated with a time needed for selected true and complementary bit lines associated with the one or more selected memory cells to establish a voltage differential therebetween based on a state of the one ore more selected memory cells, the initiation of the tracking circuit based on the transition of the internal memory clock signal; and outputting a reset signal from the tracking circuit after the predetermined tracking time, thereby disabling the internal memory clock signal, and initiating a bit line precharge operation.