Patent ID: 8477445

Claim:
A write clock synchronization apparatus for magnetic recording disk drives with patterned media comprising: A. an analog to digital converter (ADC) for receiving an analog read back signal from a magnetic read head, and converting the analog read back signal into a digital read back signal; B. a preamble processor having a read back signal input coupled to receive the digital read back signal, a digital clock input, an address mark output, a phase deviation output, and a sector length output, wherein said preamble processor is operative to: i. detect preambles and address marks in the read back signal, ii. generate address mark (AM) pulses indicative of the detection of an occurrence of address marks in the read back signal, and apply the AM pulses to the address mark output, iii. derive a preamble clock from the respective preambles and for each preamble clock, determine a phase deviation between the preamble clock and a digital clock at the digital clock input, and apply the respective phase deviations on the phase deviation output; and iv. for each detected preamble, determine a length value representative of a time interval between detection of a current preamble and a detection of a preceding preamble, and apply the respective length values on the sector length output; C. a next sector length predictor having a sector length input, an address mark input, an index input, and a predicted sector length output, wherein said sector length predictor is operative for a current detected preamble, to: i. calculate a ratio of a length value for a previous sector to a length value for the current sector, ii. determine an average ratio value for each sector during a revolution of the disk, iii. determine a next sector predicted length value representative of a product of the current sector length by the corresponding average ratio on the output, and apply the next sector predicted length value on the predicted sector length output, D. a phase increment calculator responsive to the address mark and the phase deviation from the preamble processor and next predicted sector length from the next sector length predictor, and operative to generate a phase increment value at a calculator output; and E. a clock generator responsive to the phase increment value from the phase increment calculator output, and operative to: i. generate the digital clock and apply the digital clock to the digital clock input of the preamble processor, and ii. generate an analog write clock signal at a write clock output, wherein the phase and the frequency of the digital clock and the analog write clock signal are determined by the phase increment value.