Patent ID: 8214169

Claim:
A method for characterizing device mismatch in a semiconductor integrated circuit, comprising the steps of: obtaining DC voltage characteristic data for one or more device pair of an integrated circuit, the device pair selected by a testing apparatus and coupled to a test circuit of the testing apparatus, wherein each of the device pair comprises neighboring first and second transistors in the integrated circuit, wherein the DC voltage characteristic data for the selected device pair comprises an output DC voltage V OUT as a function of an input DC voltage V IN , wherein V IN is applied to a gate of at least one of the first and second transistors and wherein V OUT is obtained at a common node connection of the first and second transistors, and wherein the DC voltage characteristic data is obtained with the first and second transistor devices operating in a subthreshold region; determining a distribution of Vt (threshold voltage) mismatch for the selected device pair using corresponding DC voltage characteristic data for the selected device pair; determining a Vt variation of transistors in the integrated circuit using one or more determined distributions of Vt mismatch for selected device pairs; and characterizing random variations of the integrated circuit using one or more determined Vt variations of transistors of the integrated circuit, wherein the step of determining the distribution of Vt mismatch for the selected device pair using the corresponding DC voltage characteristic data for the device pair, comprises: determining a distribution of V IN for a given output voltage, V OUT ; and determining a distribution of Vt mismatch of the first and second transistors from the distribution of V IN , wherein the distribution of V IN corresponds to a distribution of one-half the Vt mismatch between the first and second transistors when the first and second transistors comprise an NFET and PFET.