Patent ID: 8731025

Claim:
An offset phase-locked loop (PLL) transmitter, comprising: a clock generator that generates a first clock signal; a detector that detects a phase difference between an input data signal and a feedback data signal to generate a control signal; a controlled oscillator, coupled to the detector, that generates an output data signal according to the control signal; a mixer, coupled to the controlled oscillator and the clock generator, that mixes the output data signal according to the first clock signal to generate the feedback data signal; and a control circuit, coupled to the detector and the controlled oscillator, that adjusts an operating frequency curve of the controlled oscillator by one of a first step distance and a second step distance smaller than the first step distance such that the control signal is substantially equal to a predetermined value, wherein the control circuit comprises: a determining module, coupled to the detector, that generates a first adjustment signal or a second adjustment signal according to the control signal; an adjusting module that changes the operating frequency curve of the controlled oscillator once according to the first adjustment signal or the second adjustment signal, the adjusting module changing the operating frequency curve of the controlled oscillator by the first step distance upon receiving the first adjustment signal, or changing the operating frequency curve of the controlled oscillator by the second step distance upon receiving the second adjustment signal; and a counter that records a count value representing a current operating frequency curve, and wherein the determining module comprises: a first comparing circuit that determines whether the control signal is substantially equal to the predetermined value to generate a first comparison result; a first determining circuit, coupled to the first comparing circuit, that generates the first adjustment signal or a first determination result according to the first comparison result and the count value; a second comparing circuit that determines whether the control signal is substantially equal to the predetermined value according to the first determination result to generate a second comparison result; and a second determining circuit, coupled to the second comparing circuit, that generates the second adjustment signal according to the second comparison result.