Patent ID: 7401165

Claim:
A data processor constructed on a single semiconductor substrate comprising: a plurality of first terminals connected to a first external bus; a plurality of second terminals connected to a second external bus; a first internal circuit including a first operating state during which instructions are executed and a second operating state; a second internal circuit; a first signal route connected to said second terminals from said first terminals via said first and second internal circuits; a second signal route connected to said second terminals from said first terminals via said second internal circuit; and a power supply control circuit for controlling supply of a first power source for said first internal circuit and supply of a second power source for said second internal circuit, wherein said second internal circuit is capable of providing data, which is received from said first bus, to said second bus via said second signal route when said first internal circuit is in the second operating state, wherein said second internal circuit is capable of providing data, which is processed by said first internal circuit, to said second bus via said first signal route when said first internal circuit is in the first operating state, and wherein said power supply control circuit is capable of suspending supply of the first power source to said first internal circuit when said second signal route is selected.