Patent ID: 8222099

Claim:
A method of manufacturing a semiconductor device, comprising; a) providing a semiconductor substrate having a first region and a second region, wherein the first region and the second region are isolated from each other by an isolation region; b) forming a dummy gate oxide layer, a dummy gate and a sidewall spacer thereof belonging to the first region and the second region on the semiconductor substrate, respectively, forming a source region and a drain region belonging to the first region and the second region in the semiconductor substrate, respectively, and forming an inner dielectric layer covering the source region and drain region of the first and second regions and the isolation region of the first and second regions; c) removing the dummy gates of the first and second regions to form a first opening and a second opening; d) forming, in the first opening and the second opening, a first high-k interface layer belonging to the first region and a second high-k interface layer belonging to the second region, respectively, wherein the first and second high-k interface layers contain elements of the substrate; e) forming a first high-k gate dielectric layer on the first high-k interface layer, and forming a second high-k gate dielectric layer on the second high-k interface layer, wherein the dielectric constants of the first high-k gate dielectric layer and the second high-k gate dielectric layer are higher than those of the first and second high-k interface layers, respectively; f) forming a first metal gate layer on the first high-k gate dielectric layer, and forming a second gate layer on the second high-k gate dielectric layer; and g) processing the device to form a first gate stack belonging to the first region and a second gate stack belonging to a second region, respectively.