Patent ID: 7026857

Claim:
A multiplier circuit, comprising: a multiplier core with first and second cross-coupled transistor pairs, wherein each transistor comprises a control input and a controlled path and wherein the control inputs of the transistors of the first and second transistor pair form control inputs of the multiplier core; a first signal source for receiving a first signal to be multiplied comprising: an output; an inverted complementary output; and a first impedance; wherein the output of the first signal source is connected to the control input of the first transistor of the first transistor pair and to the control input of the second transistor of the first transistor pair, and wherein the inverted complementary output of the first signal source is connected to both the control inputs of the first and second transistor of the second transistor pair; and a second signal source for receiving a second signal to be multiplied comprising: an output, an inverted complementary output; and a second impedance equal to the first impedance such that two electrically equivalent signal inputs are provided to the multiplier core; wherein the output of the second signal source is connected to the control input of the first transistor of the first transistor pair and to the control input of the second transistor of the second transistor pair, and wherein the inverted complementary output of the second signal source is connected to the control input of the second transistor of the first transistor pair and to the first transistor of the second transistor pair.