Patent ID: 8558390

Claim:
A semiconductor device, comprising: a lower layer wiring; and an upper layer wiring disposed over the lower layer wiring interposing two or more layers of intermediate wirings and conductors connecting respective wirings between the lower layer wiring and the upper layer wiring, the upper layer wiring drawn in the same direction as a direction in which the lower layer wiring is drawn, wherein the two or more layers of intermediate wirings comprise: a first intermediate wiring between the lower layer wiring and the upper layer wiring, and a second intermediate wiring between the first intermediate wiring and the upper layer wiring, and wherein the conductors comprise: a plurality of first conductors connecting the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting the upper layer wiring and the second intermediate wiring, and a plurality of third conductors connecting the first intermediate wiring and the second intermediate wiring, the plurality of third conductors less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring.