Patent ID: 7825497

Claim:
A semiconductor device comprising: a semiconductor substrate having a first surface; two first gate electrodes formed along a first direction on the first surface; second gate electrodes formed on the first surface; first source/drain areas formed in the first surface and sandwiching a first channel region under each of the first gate electrodes; second source/drain areas formed in the first surface and sandwiching a second channel region under each of the second gate electrodes; a first interlayer insulating layer filling a region between the first gate electrodes and having a top lower in level than a top of each of the first gate electrodes, and formed on a side of the second gate electrodes; a second interlayer insulating layer formed above the first gate electrodes and the first interlayer insulating layer; a third interlayer insulating layer formed above the second gate electrodes and the first interlayer insulating layer; a first interconnect layer formed in the second interlayer insulating layer along a direction which intersects the first direction; a second interconnect layer formed in the third interlayer insulating layer; a first contact plug formed in the first interlayer insulating layer and the second interlayer insulating layer and being in contact with one of the interconnect layers and one of the first source/drain areas and being in contact with the first interconnect layer; and a second contact plug in the first interlayer insulating layer and the third interlayer insulating layer and being in contact with one of the interconnect layers and one of the second source/drain areas and being in contact with the second interconnect layer; wherein a bottom surface of the first interconnect layer is equal as a bottom surface of the second interconnect layer.