Patent ID: 8212595

Claim:
A method of improving efficiency of a delay-locked loop (DLL), comprising: interposing a phase detector and selection system between an external clock signal and a clock tree driver (CTD); wherein the selection system is interposed between the clock tree driver (CTD) and a delay line, the phase detector comprising a pair of registers, the registers receiving a clock input signal (CIN), and clock feedback signal (CKFB), each signal having timing characteristics, and outputting a pair of logical levels from the registers, the logical levels defining four or more timing conditions corresponding to pre-defined phases of the signals and based upon the timing characteristics, wherein the delay line is configured to receive the CIN and to output one of: a clock signal (CLK) and an inverted clock signal (CLK′) based on the four or more timing conditions; selecting a clock tree driver input directly from the selection system based on the delay line output and one of the four or more timing conditions of the phase detector; providing a delay signal from the clock tree driver to an I/O model, wherein the CKFB is output from the I/O model; and selectively directing the signals based upon the pre-defined phases of the signals.