Patent ID: 7613991

Claim:
An integrated circuit including a CRC circuit that receives a plurality of messages, each from one of a plurality of channels, and provides CRC bits for each message, wherein a message is composed of a plurality of words, the CRC circuit comprising: a feedforward circuit that serially receives the words of the messages and provides a feedforward result from a received word to a first summing circuit; a feedback circuit that is coupled with an output of the first summing circuit and that provides a feedback result to an input of the first summing circuit, wherein the feedback circuit includes a first timing device; and a first context buffer having an input coupled with an output of the first timing device and having an output coupled with an input of the first summing circuit, wherein the first context buffer is on a signal path between the first timing device and the summing circuit, wherein the first context buffer stores the feedback results for at least two messages of different channels and outputs a feedback result for a specific channel to be summed with a feedforward result for that specific channel.