Patent ID: 7605036

Claim:
A method of forming a floating gate array of a flash memory device, comprising: (a) forming a plurality of device isolations, which define active device regions, in a semiconductor substrate, the device isolations being formed such that upper portions thereof protrude from a surface of the substrate by a predetermined height; (b) forming tunnel oxide layers in the active device regions; (c) forming a floating gate-forming layer throughout an entire region of the substrate, including regions in which the plurality of device isolations and the active device regions are formed, the floating gate-forming layer being formed such that grooves are formed along the active device regions; (d) forming a hard mask layer on the floating gate-forming layer to maintain the grooves that are formed along the active device regions; (e) filling only the grooved portions formed on the hard mask layer with masking materials; (f) patterning the hard mask layer, using the masking materials filling the grooves as an etching mask; and (g) patterning the floating gate-forming layer using the patterned hard mask layer as an etching mask.