Patent ID: 7073149

Claim:
A method of operating a computer to provide a floor planning tool to an integrated circuit designer, comprising the steps: A) storing the data structures of a logical netlist; B) displaying on one portion of a computer display a representation of the instances defined by said logical netlist; C) providing one or more tools a user can invoke to create and locate physical blocks (pblocks) on a floorplan of an integrated circuit being designed, said floor plan comprising one or more pblocks which may be nested to establish a physical hierarchy, and responding to invocation of one or more of said tools by creating one or more said pblock(s), each pblock represented by a data object having a predetermined structure, said floorplan being displayed on the same computer display as said representation of said instances defined by said logical netlist; D) providing one or more tools a user can invoke to assign instances from said displayed representation of instances defined by said logical netlist into pblocks in said displayed hierarchy of pblocks, wherein any of the instances are assignable by a user to any of the pblocks without regard to the hierarchical structure of the logical netlist; E) responding to such assignment operations by changing the data in said data objects representing said pblocks to reflect which instances are assigned to each pblock; and F) further responding to such assignment operations by determining the original connectivity between instances defined in said logical netlist and automatically changing data in predetermined data objects of said physical hierarchy so as to recreate said original connectivity by creating new nets and new pins as necessary which recreate said original connectivity.