Patent ID: 6859382

Claim:
A non-volatile RAM comprising: a plurality of memory cells formed on a semiconductor substrate each cell capable of being selected through a select line and a data line, and having a semiconductor device that controls current flow depending on the voltage of the select line; a multi-resistive state material that changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material; changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse; maintains the resistive state even if power ceases to be supplied to the memory cell; and wherein the resistive state of the memory cell determines the information stored in the memory cell; at least one intermediary resistive state is used so that the memory cell is capable of storing more than one bit of information, whereby the multi-resistive state material is placed in the various resistive states through voltage pulses of varying magnitude, polarity, and/or duration; the resistive range between the high resistive state and the low resistive state is substantially evenly subdivided by the at least one intermediary resistive state; and the intermediary resistive state logarithmically subdivides the high resistive state and the low resistive state.