Patent ID: 8836126

Claim:
A semiconductor device comprising: a first insulating layer formed over a semiconductor substrate, the first insulating layer including oxygen; a first wire formed in the first insulating layer; an interlayer insulating layer formed on the first insulating layer; a second insulating layer formed over the interlayer insulating layer; a second wire formed in the second insulating layer over the first wire, the second wire including a first upper plug and a first lower plug whose width is smaller than a width of the first upper plug, the first upper plug and the first lower plug formed in the second insulating layer, the first lower plug being in contact with the first wire through an upper surface in the interlayer insulating layer, and the second wire containing manganese, oxygen, and copper; and a third wire formed in the second insulating layer, the third wire including a second upper plug and a second lower plug whose width is smaller than a width of the second upper plug, the second upper plug and the second lower plug formed in the second insulating layer, extending downwardly and spaced apart from the first wire, and a bottom of the second lower plug is in contact with the interlayer insulating layer.