Patent ID: 7391280

Claim:
A circuit for performing pulse width modulation suitable for generating a PWM signal according to an input data with M+N bits, the pulse width of the PWM signal dithering in 2^N frames and corresponding to a value of the input data, comprising: a pulse density modulator (PDM), for receiving the least N bits of the input data and generating a pulse density modulation signal, wherein a number of pulse of the pulse density modulation signal in 2^N frames correspond to a value of the least N bits of the input data; a first adder, electrically coupled to the PDM for generating a PWM data by adding the most M bits of the input data to a value of the pulse density modulation signal; and a pulse width modulator, electrically coupled to the first adder for generating a PWM signal dithering in 2^N frames according to the PWM data, wherein before a value of the most M bits of the input data is added to the value of the pulse density modulation signal by the first adder, the M bits input data is sign-extended to an input data with at least M+1 bits, so as to generate the PWM data with at least M+1 bits.