Patent ID: 8332591

Claim:
A cache memory unit, comprising: a cache memory; a history table for storing therein a history of write operations to the cache memory unit; an early write-back condition checking unit for checking whether an early write-back condition has been satisfied, wherein the early write-back condition checking unit determines that the early write-back condition has been satisfied in response to information received from the history table indicating that write addresses received by the cache memory unit have sequentially increased N times consecutively, where N>2, and wherein the early write-back condition checking unit determines that the early write-back condition has not been satisfied in response to information received from the history table indicating that the write addresses received by the cache memory unit have not sequentially increased N times consecutively; and an early write-back execution unit for monitoring a memory bus connecting the cache memory unit and an external memory unit, and in response to the memory bus being idle and the early write-back condition being satisfied, for causing dirty data in the cache memory to be written back to the external memory unit using the memory bus, wherein the early write-back condition checking unit determines whether the early write-back condition has been satisfied further in response to special function register information provided to the cache memory unit, and wherein the special function register information indicates a number of blocks of data to be written back to the external memory unit.