Patent ID: 7704844

Claim:
A method of fabricating a semiconductor structure comprising: providing a semiconductor structure having an oxide layer and at least one patterned material stack located on an active area of a semiconductor substrate, said semiconductor substrate having at least one trench isolation region that extends above the surface of said oxide layer and said patterned material stack comprises a lower portion of SiGe and an upper portion of a first nitride and a second nitride; performing an angled implantation process at an angle incident to the semiconductor substrate of less than 60°, at an energy from about 0.5 to about 30 keV and utilizing an ion dose from about 10 12 to about 5×10 14 atoms/cm 2 which forms a well region of a first conductivity type within the semiconductor substrate at an interface with said oxide layer, wherein the well region has a central portion and two horizontally abutting end portions, said central portion having a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions, wherein said central portion has a dopant concentration from about 2×10 18 to about 7×10 18 atoms/cm 3 and said two horizontally abutting end portions of said well region have a dopant concentration from about 10 18 to about 3×10 18 atoms/cm 3 , and wherein said central portion forms an abutting interface with each end portion, said abutting interface has a change in dopant concentration that is on an order of about 10 per about 5 to about 10 nm; removing the lower portion of said at least one patterned material stack by isotropic etching, while maintaining the upper portion of said at least one patterned material stack, said maintained upper portion of said at least patterned material stack is supported by said at least one trench isolation region; removing said oxide layer to expose said semiconductor substrate within said active area; forming an epitaxial semiconductor layer on said exposed semiconductor substrate; forming a gate dielectric on said epitaxial semiconductor layer and on exposed sidewalls and bottom wall of said upper portion of said at least one patterned material stack; forming a first gate electrode portion on a surface of said epitaxial semiconductor layer, wherein a top surface of said first gate electrode portion abuts said gate dielectric on said bottom wall of said upper portion of said at least one patterned material stack; removing the upper portion of said at least one patterned material stack and said gate dielectric located on said sidewalls and said bottom wall of said upper portion of said at least one patterned material stack; and forming a second gate electrode portion on an upper surface of said first gate electrode portion.