Patent ID: 7772068

Claim:
A method of fabricating a non-volatile memory, comprising: sequentially forming a dielectric charge trapping layer, a first conductive layer and a patterned mask layer on a substrate; removing a portion of the first conductive layer using the patterned mask layer as a mask to expose portions of the dielectric charge trapping layer and form a first plurality of gates having sidewalls and top surfaces, the exposed portions extending between adjacent gates in the first plurality of gates; performing an oxidation process to form an oxide layer on the sidewalls of the gates in the first plurality of gates while protecting the top surfaces of the gates in the first plurality of gates from the oxidation process; removing the patterned mask layer after performing the oxidation process; forming a second plurality of gates, after removing the patterned mask layer, on the exposed portions of the dielectric charge trapping layer, the gates in the second plurality of gates interleaved with the gates in the first plurality of gates to define a plurality of respective memory cells in a NAND string, wherein the plurality of memory cells include data storage sites in the dielectric charge trapping layer beneath each gate in the first and second pluralities of gates; and forming a doped region in the substrate adjacent to the NAND string.