Patent ID: 7760625

Claim:
An exchange node comprising: an input buffer unit for writing input data which is connection type packet data to a shift register and outputting input buffer data at completion of the writing of the input data; a distribution unit, which is input with the input buffer data from the input buffer unit, for outputting the input buffer data from the input buffer unit as priority control processing data by a priority control signal indicating that the input data input to the input buffer unit is priority control processing data; an identification unit for identifying the priority control signal contained in the input data input to the input buffer unit, and outputting the priority control signal to the distribution unit; a time slot allocation circuit for obtaining time slot information indicating that a time slot for writing the priority control processing data is unused, specifying number of time slots according to the length of the priority control processing data, and outputting a time slot specifying signal specifying a time slot of write destination of the priority control processing data from the unused time slots; a multiplexing circuit for writing the priority control processing data from the distribution unit to the shift register allocated by the time slot specifying signal from the time slot allocation circuit, and outputting multiplexed data at completion of the writing of the priority control processing data; and an output/distribution unit for transmitting the multiplexed data from the multiplexing circuit to an outgoing line and outputting information of the unused time slot of the multiplexed data from the multiplexing circuit to the time slot allocation circuit as time slot information.