Patent ID: 7122478

Claim:
A method of manufacturing a semiconductor device, the method comprising: (a) forming an interlayer dielectric over a semiconductor substrate; (b) forming a polysilicon layer pattern over the interlayer dielectric; (c) forming a contact hole in the interlayer dielectric by etching the interlayer dielectric using the polysilicon layer pattern as an etching mask; (d) removing the polysilicon layer pattern by an etching process that has a large etching selectivity of the polysilicon layer with respect to the interlayer dielectric and about 3% or less etching uniformity; and (e) forming a contact by filling the contact hole with a conductive material, forming an etch stop layer on the semiconductor substrate before step (a), and etching the etch stop layer exposed by the contact hole after step (d), wherein the etching of the polysilicon layer pattern is performed with a large etching selectivity of the polysilicon layer pattern with respect to the etch stop layer, wherein the etching selectivity of the polysilicon layer pattern with respect to the interlayer dielectric is greater than about 50:1 and with respect to the etch stop layer is greater than about 25:1, wherein the polysilicon layer pattern is removed by a chemical dry etching (CDE) method using a remote plasma, wherein the interlayer dielectric is a silicon oxide layer and the etch stop layer is a silicon nitride layer, and the CDE method is conducted using an etchant comprising a CF 4 and O 2 gas, and wherein a flow ratio of CF 4 :O 2 gas is about 150 sccm:60 sccm.