Patent ID: 8732628

Claim:
A method comprising: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT); grouping circuit patterns near the selected circuit pattern or network into one or more groups, such that adjacent circuit patterns within each group are separated from each other by less than a predetermined distance, and the circuit patterns within each group are separated from the selected circuit pattern by a distance greater than the predetermined distance and not more than three times the predetermined distance; for each group, using a computer to calculate a respective expected increase in parasitic resistance-capacitance (RC) coupling associated with a predetermined mask alignment error, for two different sets of mask assignments, based on a difference between a ratio of coextensive length over spacing between the selected circuit pattern and each circuit pattern in the group in the absence of a mask alignment error, and on the ratio of coextensive length over spacing between the selected circuit pattern and each circuit pattern in the group in the presence of the predetermined mask alignment error; and assigning the circuit patterns in the one or more groups to be patterned by respective photomasks, so as to minimize a total of the expected increase in parasitic RC coupling.