Patent ID: 8605475

Claim:
A system, comprising: a semiconductor memory device and a controller, the semiconductor memory device comprising: a first external terminal provided to receive a system clock with a first frequency or a second frequency; a second external terminal provided to receive a read command; a third external terminal configured to output a data strobe signal in response to the read command, the data strobe signal including a read preamble and a toggle transition following to the read preamble; a fourth external terminal provided to output a read data in synchronization with the toggle transition of the data strobe signal; and a control circuit configured to control a length of the read preamble of the data strobe signal based on a preamble length information, the controller comprising: a fifth external terminal provided to correspond to the system clock; a sixth external terminal provided to output the read command; a seventh external terminal provided to receive the read data; an eighth external terminal provided to receive the data strobe signal related to the read data; and a ninth external terminal provided to output the preamble length information, so that the length of the read preamble includes first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.