Patent ID: 7119565

Claim:
A chip carrier for testing electrical performance of a passive component, having at least one passive component mounted on a surface of the chip carrier, the chip carrier comprising: a core layer having a plurality of conductive traces formed on at least one surface thereof, the conductive traces comprising: at least one first trace connected with the passive component and having a first predetermined position and two ends, wherein the two ends are respectively electrically connected to a first bond finger formed on the surface, mounted with the passive component, of the chip carrier, and to a first ball pad formed on an opposite surface of the chip carrier, and wherein the first predetermined position and the first bond finger are located on the same side relative to the passive component; and at least one second trace free of connection with the passive component and having two ends and a second predetermined position located on the same surface as the first predetermined position, wherein one of the ends of the second trace is electrically connected to a second ball pad located on the same surface as the first ball pad; and a solder mask layer applied over the conductive traces and formed with a plurality of openings for at least exposing the first predetermined position and the second predetermined position.