Patent ID: 6898687

Claim:
A computer system, comprising: a node including a memory controller and a memory; N other nodes, wherein N is an integer equal to or greater than one; and an interconnect coupling the memory controller to N other memory controllers, wherein each of the N other memory controllers is included in a respective one of the N other nodes; wherein a portion of a semaphore region of the memory is associated with a shared resource accessible by both the node and the N other nodes, wherein the portion of the semaphore region includes one writeable unit of data and N read-only units of data, wherein each of the N read-only units of data is associated with a respective one of the N other nodes, and wherein a value of each of the N read-only data units indicates whether the respective one of the N other nodes is currently requesting access to the shared resource; wherein the memory controller is configured to update a value of one of the N read-only units of data in response to receiving a write request specifying the one of the N read-only units of data from a memory controller in the respective one of the N other nodes via the interconnect.