Patent ID: 7471560

Claim:
An electronic device comprising: a first bit line; a second bit line; a third bit line; a first set of memory cells including a first memory cell, wherein; each memory cell within the first set of memory cells has a first source/drain region and a second source/drain region; the first source/drain region of each memory cell within the first set of memory cells is electrically connected to the first bit line; and the second source/drain region of each memory cell within the first set of memory cells is electrically connected to the third bit line; a second set of memory cells including a second memory cell, wherein: each memory cell within the second set of memory cells has a first source/drain region and a second source/drain region; the first source/drain region of each memory cell within the second set of memory cells is electrically connected to the second bit line; and the second source/drain region of each memory cell within the first and second sets of memory cells is electrically connected to one another and to the third bit line; a control module coupled to the first and second bit lines, wherein the electronic device is configured such that carriers can flow (1) from the first bit line to the second bit line via the second source/drain regions of the first and second memory cells or (2) from the second bit line to the first bit line via the second source/drain regions of the first and second memory cells.