Patent ID: 7671633

Claim:
An electronic clock switch for switching between a first clock signal and a second clock signal providing either the first clock signal or the second clock signal as an output clock signal comprising: a first tristate buffer (TBUF 0 ) having an input receiving the first clock signal (CLK 0 ), a control input receiving a first tristate control signal ( 3 ST 0 ) and an output having a high impedance tristate output when said first tristate control signal ( 3 ST 0 ) has a predetermined digital state; a second tristate buffer (TBUF 1 ) having an input receiving the second clock signal (CLK 1 ), a control input receiving a second tristate control signal ( 3 ST 1 ) and an output having a high impedance tristate output when said second tristate control signal ( 3 ST 1 ) has said predetermined digital state; a multiplexer (MUX) having a first input coupled to said output of said first tristate buffer (TBUF 0 ), a second input coupled to said output of said second tristate buffer (TBUF 1 ), a control input receiving a multiplexer control signal (MUX_SEL) and an output, said multiplexer (MUX) outputting either said first clock signal (CLK 0 ) or said second clock signal (CLK 1 ) at said output in response to a digital state of said multiplexer control signal (MUX_SEL); and a control stage (CONTROL) having an input receiving a clock selection signal (SEL) having a first digital state indicating output of said first clock signal (CLK 0 ) and a second digital state indicating of output said second clock signal (CLK 1 ), a first output generating said multiplexer control signal (MUX_SEL) having a first digital state controlling said multiplexer (MUX) to output aid first clock signal (CLK 0 ) and a second digital state controlling said multiplexer (MUX) to output said second clock signal (CLK 1 ) through the multiplexer, a second output generating said first tristate control signal ( 3 ST 0 ) from a logical gating of said clock selection signal (SEL) and said multiplexer control signal (MUX_SLE) and a third output generating said second tristate control signal ( 3 ST 1 ) from a logical gating of said clock selection signal (SEL) and said multiplexer control signal (MUX_SLE), said control stage operable whereby a change of said multiplexer control signal (MUX_SEL) from said first digital state to said second digital state is synchronous with an edge of said second clock (CLK 1 ) and a change of said multiplexer control signal (MUX_SEL) from said second digital state to said first digital state is synchronous with an edge of said first clock signal (CLK 0 ).