Patent ID: 8175214

Claim:
A frequency divider comprising: a plurality of programmable latches connected in a feedback shift register configuration, the plurality of programmable latches including a first programmable latch that includes a program input to receive a program signal and a control terminal to receive a clock signal, the first programmable latch being configured to select a polarity of the first programmable latch among two opposite polarities based on the program signal, and set the behavior of the first programmable latch in accordance with the selected polarity and the clock signal; a configuration module structured to provide the program signal to the program input of the first programmable latch to modify a divisor parameter of the frequency divider; an inverter placed between a sub-plurality of programmable latches of said plurality of programmable latches and a feedback sub-plurality of programmable latches of said plurality of programmable latches; and an input latch having a signal input, a clock input, a hold input, and an output, the signal input being connected to an output of the inverter, the hold input being configured to receive a hold signal from the configuration module, the clock input being configured to receive the clock signal, the output being coupled to a consecutive programmable latch of the sub-plurality of programmable latches, and the input latch being structured to: hold fixed an output value at the output of the input latch, regardless of the clock signal, in response to receiving a first value of the hold signal, and vary the output value at the output of the input latch according to the clock signal, in response to receiving a second value of the hold signal, wherein said first programmable latch comprises: an input differential stage connected to a signal input; an output differential stage connected to a signal output: a first control differential stage coupled to the control terminal and connected to the in and output differential stages the first control differential stage being configured to be enabled by the program signal in the first polarity and disabled by the program signal in the second polarity, and a second control differential stage coupled to the control terminal and connected to the input and output differential stages, the second control differential stage being configured to be disabled in the first polarity and enabled in the second polarity.