Patent ID: 7627003

Claim:
A clock synchronization buffer circuit for use with a counter clock flow pipelined circuit that includes a cascade of processing modules in which each processing module receives input data from a previous processing module in the cascade, processes the received data and then sends output results to a following processing module in the cascade, the clock synchronization buffer circuit being arranged to receive a clock input signal and a delay select signal and to provide delayed clock signals having a selected delay to a local processing module and to a next pipeline stage, comprising: a selectable delay stage arranged to receive a clock input signal and a delay select signal and to output a delayed clock signal having a selected delay, the selectable delay stage comprising: a first inverter and a second inverter connected in series, the first inverter arranged to receive the clock input signal, and the second inverter arranged to output a delayed clock signal, and a multiplexer connected to the second inverter, the multiplexer arranged to receive the delayed clock signal at a first input, the clock input signal at a second input, and the delay select signal at a third input, and to output the delayed clock signal having a selected delay, wherein the delayed clock signal output from the multiplexer is shifted in phase from the input clock signal based on the delay select signal; a first amplifier that is a non inverting amplifier connected to the selectable delay stage and arranged to receive the delayed clock signal having a selected delay output from the multiplexer and to output a non inverted delayed clock signal having a selected delay to a local processing module in the cascade that corresponds to the clock synchronization buffer circuit; and a second amplifier that is an inverting amplifier connected to the selectable delay stage and arranged to receive the delayed clock signal having a selected delay output from the multiplexer and to output an inverted delayed clock signal having a selected delay to the next pipeline stage.