Patent ID: 8179120

Claim:
A test structure for an integrated circuit device, comprising: a generally rectangular outer perimeter comprising an input/output (I/O) VDD bus having a pair of I/O VDD pads at opposing ends thereof; a generally rectangular inner perimeter surrounded by the outer perimeter, the inner perimeter further comprising: a plurality of experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, each of the experiments comprising one or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; a plurality of additional I/O pads in a generally linear arrangement with respect to the I/O VDD pads; one or more common ground buses; and one or more decoupling capacitors; wherein the outer and inner perimeter, including the plurality of experiments are disposed, and are fully testable, at a first level of metal wiring (M 1 ) in the integrated circuit device.