Patent ID: 7449386

Claim:
A method of manufacturing a plurality of MOS transistors, comprising: providing at least a portion of a semiconductor substrate of a first conductivity type having first and second regions; forming a plurality of gate structures in each of the first and second regions, each gate structure having defined with respect thereto source and drain region sides and a channel region under the gate structure, respective drain sides of immediately adjacent ones of the gate structures being adjacent one another; forming a mask layer only on the first region and not on the second region of the substrate, the mask layer having mask portions that only partially mask portions of the substrate between the respective drain sides of the gate structures only in the first region; implanting dopant of the first conductivity type at first and second respectively positive and negative predetermined non-zero degree tilt angles relative to a normal perpendicular to the substrate using the mask layer as an implantation mask; implanting dopant of a second conductivity type, opposite the first conductivity type, into both the first and second regions of the substrate at a 0 degree angle relative to the normal to the substrate; and implanting dopant of the second conductivity type into the first and second regions of the substrate at third and fourth respectively positive and negative angles relative to the normal perpendicular to the substrate using the mask layer as an implantation mask.