Patent ID: 7208933

Claim:
A semiconductor integrated circuit comprising: a plurality of aging devices in which an age-based change occurs while a power supply is disconnected, and output signals sensed in read change over time; a plurality of operational circuits arranged in correspondence with the plurality of aging devices, and having at least three terminals, respectively, first terminals of which receives the output signals from the plurality of aging devices, respectively; a first memory area electrically connected to second terminals of the plurality of operational circuits, and storing at least one predetermined signal level; an adder electrically connected to third terminals of the plurality of operational circuits and adding the output signals from the plurality of operational circuits appearing at the third terminals; a plurality of circuit breakers which cut off output signals from the plurality of aging devices before the adder receives the output signals on the basis of operational results of the plurality of operational circuits that are obtained by comparing the output signals from the plurality of aging devices with the at least one predetermined signal level; a second memory area where a predetermined reference signal is stored, and a sense circuit which compares an output signal from the adder and the reference signal stored in the second memory.