Patent ID: 8863065

Claim:
A method comprising: receiving, at a computer system, a design functionality for a device; receiving, at the computer system, a selection of a first die from a library, the first die comprising a plurality of programmable chip blocks, the plurality of programmable chip blocks including a first programmable chip block and a second programmable chip block, wherein the second programmable chip block includes memory; receiving, at the computer system, a selection of a second die, the second die comprising a plurality of interconnects, wherein the second die includes a switch having an input or output for connecting an interconnect of the plurality of interconnects with the first programmable chip block or the second programmable chip block of the plurality of programmable chip blocks included in the first die, wherein the second die further includes a direct memory access engine to provide the first programmable chip block of the first die access to the memory of the second programmable chip block of the first die; and connecting the first and second dies.