Patent ID: 7768333

Claim:
An apparatus for generating a reference clock for a DLL circuit, the apparatus comprising: a buffering unit configured to buffer a positive external clock and a negative external clock to generate a first reference clock and a second reference clock, to invert the second reference clock to generate a negative second reference clock and to output the first reference clock and the negative second reference clock, wherein the buffering unit comprises: a first clock buffer configured to buffer the positive external clock and the negative external clock to generate the first reference clock; a second clock buffer configured to buffer the positive external clock and the negative external clock to generate the second reference clock; and an inverting unit configured to invert the second reference clock to generate the negative second reference clock; and a duty cycle compensating unit configured to receive the first reference clock and the negative second reference clock and generate a reference clock, wherein the first reference clock and the second reference clock are generated at the same time.