Patent ID: 7728637

Claim:
A phase-lock loop generating an output clock signal responsive to an input clock signal, comprising: a phase detector having a first input receiving the input clock signal and a second input receiving a feedback clock signal, the phase detector generating a phase error signal at an output that is indicative of a relationship between the phase of the input clock signal and the phase of the feedback clock signal; a voltage controlled ring oscillator having an input coupled to the output of the phase detector, the voltage controlled oscillator comprising a plurality of delay elements that are coupled to each other in a ring in an unstable relationship, each of the delay elements having a respective delay control terminal that controls the signal propagation delay through the delay element, the delay control terminal of each of the delay elements being coupled to the output of the phase detector so that the signal propagation delay of each of the delay elements corresponds to the phase error signal and so that a clock signal generated at an output of the voltage controlled oscillator has a frequency corresponding the phase error signal and each of the delay elements generate a respective phase of the clock signal generated by the voltage controlled oscillator; a clock tree coupled to the voltage controlled oscillator to receive the phases of the clock signal generated by the respective delay elements; and a frequency multiplier having an input coupled to receive the clock signal from the output of the voltage controlled oscillator, the frequency multiplier generating the feedback clock signal at an output having a frequency that is a multiple of the frequency of the clock signal received from the output of the voltage controlled oscillator, the feedback clock signal at the output of the frequency multiplier being applied to the second input of the phase detector.