Patent ID: 7723798

Claim:
A circuit structure, comprising: at least one NFET device, said NFET device comprises an n-channel hosted in a Si based material, and an NFET gate stack overlapping said n-channel; at least one PFET device, said PFET device comprises a p-channel hosted in said Si based material, and a PFET gate stack overlapping said p-channel; wherein said NFET gate stack and said PFET gate stack each has a portion which is identical in said NFET device and in said PFET device, wherein said portion comprises at least a gate metal layer and a cap layer, wherein said gate metal layer and said cap layer are directly interfacing with each other; wherein said NFET device further comprises an NFET gate insulator, wherein said NFET gate insulator comprises a layer of a first high-k material, wherein said layer of said first high-k material directly interfaces with said cap layer in said NFET device; wherein said PFET device further comprises a PFET gate insulator, wherein said PFET gate insulator comprises a layer of a second high-k material, wherein said layer of said second high-k material directly interfaces with said cap layer in said PFET device; and wherein absolute values of the saturation thresholds of said NFET and said PFET devices are higher than about 0.4 V.