Patent ID: 8253163

Claim:
A high voltage semiconductor device, comprising: a semiconductor substrate of a first conductivity type having first and second main surfaces; a first semiconductor region of a second conductivity type formed in said first main surface of said semiconductor substrate and surrounded by said semiconductor substrate in said first main surface; a second semiconductor region of the first conductivity type formed in said first main surface and sandwiching said first semiconductor region between it and said semiconductor substrate; a third semiconductor region of the first conductivity type formed adjacent to an end surface of said semiconductor substrate, from said first main surface toward said second main surface, with a depth not penetrating said semiconductor substrate; a fourth semiconductor region of the second conductivity type formed in said second main surface of said semiconductor substrate; an electric field relaxing portion in an annular shape formed in said first main surface of said semiconductor substrate and surrounding said first semiconductor region in said first main surface; a control electrode formed to face a channel region in said first semiconductor region sandwiched between said semiconductor substrate and said second semiconductor region, with an insulating film interposed therebetween; a first main electrode formed in contact with both of said first semiconductor region and said second semiconductor region; a second main electrode formed in contact with said fourth semiconductor region; a third main electrode formed in contact with said third semiconductor region; and a conductive wire electrically connecting said second and third main electrodes, a resistance between said first semiconductor region and said third semiconductor region being greater than a resistance between said first semiconductor region and said fourth semiconductor region.