Patent ID: 8416895

Claim:
A digital signal processor (DSP) configured to compensate for an in-phase/quadrature phase (I/Q) imbalance between an in-phase sequence of data and a quadrature phase sequence of data in a communications receiver, the in-phase sequence of data and the quadrature phase sequence of data being characterized by one or more sequence parameters, comprising: an I/Q compensation module configured to compensate for the I/Q imbalance by adjusting the one or more sequence parameters in response to one or more sequence parameter values to provide a compensated in-phase sequence of data and a compensated quadrature phase sequence of data; a combination module configured to combine the compensated in-phase sequence of data and the compensated quadrature phase sequence of data to provide an intermediate recovered sequence of data; and an interferer processing module configured to determine one or more signal metrics of one or more images from the intermediate recovered sequence of data, and to provide the one or more sequence parameter values based upon the one or more signal metrics, wherein the I/Q compensation module is further configured to scale the in-phase sequence of data based upon the one or more sequence parameter values to provide an additive component of the in-phase sequence of data, and to combine the additive component and the quadrature phase sequence of data the compensated quadrature phase sequence of data.