Patent ID: 7341903

Claim:
A method of forming a semiconductor structure, comprising: providing a substrate comprising a first transistor element and a second transistor element; forming a first stressed layer over said first transistor element; forming a first dielectric layer over said first transistor element but not over said second transistor element; forming a second stressed layer over said second transistor element after formation of said first dielectric layer, wherein said second stressed layer does not cover said first transistor element; forming a second dielectric layer over said substrate after formation of said second stressed layer; and planarizing said first dielectric layer and said second dielectric layer, wherein a portion of said second dielectric layer located over said first transistor element is removed in said planarization; wherein at least one of said first stressed layer and said second stressed layer is formed using a plasma enhanced chemical vapor deposition process performed substantially without a bias voltage and has a predetermined compressive intrinsic stress, said predetermined compressive intrinsic stress having an absolute value of at least 2 GPa.