Patent ID: 7990180

Claim:
A fast dynamic register circuit, comprising: a first precharge circuit which precharges a first precharge node high while a clock node is low, which maintains said first precharge node high after said clock node goes high when a data node is low, which discharges said first precharge node low if said data node is high when said clock node goes high, and which keeps said first precharge node discharged low while said clock node is high if said first precharge node was discharged low when said clock node went high regardless of any change of said data node while said clock node is high; a second precharge circuit which precharges a second precharge node high while said clock node is low, and which discharges said second precharge node low if said first precharge node remains high after said clock node went high; a full keeper circuit which keeps a state of said second precharge node immediately after either one of said first and second precharge nodes switches state while said clock node is high; and an output circuit which drives an output node to a next state based on said second precharge node immediately after either one of said first and second precharge nodes switches state after said clock node goes high and which maintains said output node at said next state when said clock node next goes low regardless of any change of state of said second precharge node.