Patent ID: 7386703

Claim:
A method, comprising: providing a processor: providing M independent vector register files within the processor; storing a matrix of L data elements in the M vector register files, each data element having B binary bits, said matrix having N rows and M columns, said L=N*M, said N=K*M, each column having K subcolumns, said N≧2, said M≧2, said K≧2, said N=K*M, said B≧1, each row of said N rows being addressable, each subcolumn of said K subcolumns being addressable, said processor not duplicatively storing said L data elements; and wherein M multiplexors are coupled to the M vector register files such that each of the M multiplexors has a different value, wherein each multiplexor of the M multiplexors comprises a set of binary switches subject to each binary switch being on or off and respectively represented by a binary bit 1 or 0 such that the value of the multiplexor consists of the composite value of said binary bits, wherein the method further comprises providing M address registers within the processor, wherein each address register of the M address registers is associated with a corresponding one of the M vector register files, wherein each of the M vector register files includes an array of N registers, wherein each of the N*M registers of the M vector register files stores a data element of the L data elements, wherein each vector register file is independently addressable through its associated address register being adapted to point to one of the N registers of said vector register file, wherein the data elements of each subcolumn are stored in different vector register files, and wherein the data elements of each row are stored in different vector register files.