Patent ID: 8806102

Claim:
A cache system, comprising: a computation unit; primary cache memory configured to input and output data between the computation unit; the primary cache memory includes a storing unit including multi-port memory units that store unit data having a first data size, a writing unit that simultaneously writes a plurality of unit data sequentially inputted via input port registers to consecutive locations of the storing unit, and an outputting unit that reads out and outputs the plurality of unit data written in the storing unit by the writing unit to a plurality of output port registers; wherein when writing data having a second data size that is an arbitrary multiple of a first data size and is segmented into unit data to the primary cache memory, the data is stored in different multi-port memory units by conducting a first write operation that writes the sequential unit data to the input port registers in a subset of the multi-port memory units, and a second write operation that writes the sequential unit data to the input port registers in another subset of the multi-port memory units; and when reading out data from the primary cache memory, the data is read out from different multi-port memory units by conducting a first read operation that reads a sequential unit data from the output port registers of a subset of the multi-port memory units, and a second read operation that reads a sequential unit data from the output port registers of the remaining subset of the multi-port memory units.