Patent ID: 7779333

Claim:
A semiconductor device comprising: a memory cell array for storing data signals and parity signals; sense amplifiers for reading the stored data signals and the stored parity signals; an error correction circuit for receiving the read data signals and the read parity signals and correcting an error contained in the data signals; and a memory module interface circuit for retrieving output data signals outputted from the error correction circuit and outputting the output data signals to a data bus, wherein the error correction circuit includes: a syndrome generator portion for combining the read data signals and the read parity data signals with each other to generate syndrome signals; a decoder portion for specifying an error bit in the data signals from the syndrome signals; and an error corrector portion for correcting the error in the data signals based on output signals from the decoder portion, wherein the memory module interface circuit includes: a data retrieval clock generator portion for generating a data buffer retrieval clock signal giving a timing for retrieving the output data signals, and an error detection signal determination clock signal for giving a timing for determining whether or not an error is contained in the data signals; and a data buffer for retrieving the output data signals in response to the data buffer retrieval clock signal, the semiconductor device further comprising: an error detector portion for detecting whether or not an error is contained in the data signals; and a sense amplifier activation signal generator portion for generating a sense amplifier activation signal activating an operation of each of the sense amplifiers, wherein when the error detection signal has been activated at a time at which the error detection signal determination clock signal shifts, each of the data buffer retrieval clock and the sense amplifier activation signal is delayed by a specified time.