Patent ID: 7704885

Claim:
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a first interlayer dielectric layer, a first interconnection metal layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first interconnection metal layer to expose the first interlayer dielectric layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first interconnection metal layer, wherein the openings are formed without passing through the first interlayer dielectric layer; forming a second interlayer dielectric layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second interlayer dielectric layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second interlayer dielectric layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer; and performing a photolithography process to form a conductive pillar on the patterned first interconnection layer, wherein a side of the remaining second interlayer dielectric layer simultaneously contacts a side of the patterned first interconnection layer and a side of the conductive pillar.