Patent ID: 8019982

Claim:
A data processing system comprising: a processor core which executes a program; a loop accelerator comprising an array having a plurality of data processing cells, wherein the loop accelerator executes a loop in a program by configuring the array according to a set of configuration bits; and a centralized register file which allows data used in the program execution to be shared by the processor core and the loop accelerator, wherein the loop accelerator divides the configuration of the array in a single iteration of the loop into at least three phases according to whether data exchange with the central register file is conducted during the loop execution, wherein the at least three phases comprise a first phase which fetches data for the loop execution from the central register file, a second phase which executes the loop using the data, and a third phase which writes data obtained through the loop execution to the central register file, and wherein the loop accelerator releases the central register file from the processor core during the second phase, wherein at least some data processing cells of the plurality of data processing cells which are used to fetch data for the loop execution from the central file register in the first phase, are used to execute the loop in the second phase; and wherein the loop accelerator comprises a configuration memory which stores at least three sets of configuration bits for configuring the array according to the at least three phases.