Patent ID: 7886176

Claim:
A double data rate memory system comprising: a double data rate memory that is responsive to a clock signal and is configured to generate read data and a read data strobe signal; a clocked read data latch that is responsive to the read data; a first variable digital delay line that is configured to delay the read data strobe signal in response to a digital delay control signal and to clock the clocked read data latch with the read data strobe signal that is delayed; a clock period measurement system that is responsive to the clock signal to generate a delay measurement value; and an adjustment system that is responsive to the delay measurement value and is configured to adjust the delay measurement value to produce the digital delay control signal; wherein the clock period measurement system comprises: a second variable digital delay line that is coupled to the clock signal and is responsive to a digital control word; a flip-flop that is responsive to the second variable digital delay line and is clocked by a complement of the clock signal; and a controller that is responsive to the flip-flop and is configured to cycle the digital control word and to identify a value of the digital control word responsive to the flip-flop changing state to provide the delay measurement value.