Patent ID: 8014224

Claim:
A semiconductor device comprising: a first power supply pad, externally supplying a first external voltage; a second power supply pad, externally supplying a second external voltage lower than said first external voltage; a third power supply pad, externally supplying a ground voltage lower than said second external voltage; a power supply module for stepping down said first external voltage to supply an internal voltage; a logic circuit portion for performing a logical operation based on data to be input; and a memory macro, wherein said memory macro includes: a memory array having a plurality of memory cells, each holding data to be used in said logic circuit portion, arranged in a matrix; a first load circuit having a sense amplifier for sensing data on a bit line connected to a memory cell, said first load circuit being supplied with said internal voltage; and a second load circuit having a data input/output circuit for performing data input/output between said logic circuit portion and a memory cell, said second load circuit being supplied with said second external voltage.