Patent ID: 7848147

Claim:
A nonvolatile semiconductor memory device comprising: a cell array; a controller configured to receive input data from an outside source; an address latch unit configured to store a Y-address of the input data and at least two X-addresses respectively corresponding to at least two wordlines based on an address of the input data output from the controller; a latch controller controlling the address latch unit to store a first X-address corresponding to a first wordline in an X-address latch and to store at least one next X-address corresponding to a wordline next to the first wordline in at least one next X-address latch when it is determined based on the address of the input data output from the controller that the input data is written to the next wordline; and a page buffer configured to receive the input data from the controller and temporarily store the input data, wherein the controller operates to write the data stored in the page buffer over the at least two wordlines in the cell array based on the at least two X-addresses and the Y-address.