Patent ID: 7049846

Claim:
A clock tree distribution network for a field programmable gate array (FPGA) comprising: an interface having a root signal selected from at least one of an external clock signal, an internal clock signal and a plurality of phase lock loop cell output signals, said interface having programmable elements; a logic array having a plurality of local signals and having programmable elements; a programmable routing architecture coupled to said programmable elements of said interface and said logic array; a routed clock network that selects a signal from at least one of said root signal, a local signal from said logic array, a positive power supply signal, and a ground signal and routes said selected signal to at least one of a plurality of logic modules and a plurality of flip-flops in said logic array; and a hardwired clock network that selects a signal from at least one of said root signal, a local signal from said logic array, a positive power supply signal, and a ground signal and routes said selected signal to said plurality of flip-flops in said logic array.