Patent ID: 6872609

Claim:
A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising: forming a portion of a charge trapping dielectric layer over the substrate; forming a resist over the portion of the charge trapping dielectric layer; patterning the resist to form a plurality of resist features having respective first spacings therebetween; applying Safier material to sidewalls of the resist features; treating the Safier material so that it becomes attached to sidewalls of the resist features and defines respective second spacings between the resist features that are less than the first spacings; performing a bitline implant through the second spacings and the portion of the charge trapping dielectric layer to establish buried bitlines within the substrate having respective widths corresponding generally to that of the second spacings; removing the patterned resist and Safier material; forming the remainder of the charge trapping dielectric layer over the portion of the charge trapping dielectric layer; forming a wordline material over the remainder of the charge trapping dielectric layer; and patterning the wordline material to form wordlines that overlie the bitlines.