Patent ID: 8626813

Claim:
A floating-point fused dot product unit, comprising: a first multiplier tree adapted to multiply a first and second significand operands to produce a first significand pair; a second multiplier tree adapted to multiply a third and fourth significand operands to produce a second significand pair; a first multiplexer coupled to said first and second multiplier trees, wherein said first multiplexer is configured to select a smaller significand pair of said first and second significand pairs; a second multiplexer coupled to said first and second multiplier trees, wherein said second multiplexer is configured to select a greater significand pair of said first and second significand pairs; an alignment and sticky unit coupled to said first multiplexer, wherein said alignment and sticky unit is configured to align said smaller significand pair and perform sticky logic on said smaller significand pair to generate a first sticky bit; and a sticky unit coupled to said second multiplexer, wherein said sticky unit is configured to perform sticky logic on said greater significand pair to generate a second sticky bit; wherein least significant bits under said first and second sticky bits are discarded to thereby reduce a length of said first and second significand pairs.