Patent ID: 7961054

Claim:
An apparatus comprising: a frequency acquisition loop to lock a voltage controlled oscillator (VCO) clock in a zone lock frequency band from a plurality of frequency bands of a multi-band VCO to a reference clock, the frequency acquisition loop generating first and second feedback clocks from the VCO clock, the zone lock frequency band having a smallest frequency difference between the first feedback clock and the reference clock; a data lock phase loop coupled to the frequency acquisition loop to generate a driving signal corresponding to a phase error signal from interleaved partial response signal (PRS) samples based on the second feedback clock, the driving signal controlling the multi-band VCO in a data phase lock mode; and a lock detect controller coupled to the frequency acquisition loop to detect a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode based on the first feedback clock and the reference clock; wherein the frequency acquisition loop comprises: a divider to divide the VCO clock to provide the first and second feedback clocks; a loop filter coupled to the multi-band VCO to filter a control signal, the filtered control signal controlling the multi-band VCO; a loop multiplexer coupled to the loop filter to select the control signal from a common mode signal, a frequency error signal, and the driving signal based on a multiplexer select code; and a phase frequency detector (PFD) and a charge pump coupled to the loop multiplexer and the divider to provide the frequency error signal based on the reference clock and the first feedback clock.