Patent ID: 7960266

Claim:
A method of making a non-volatile memory array using a semiconductor substrate, comprising: forming a layer of charge storage material across a surface of a substrate with a first layer of dielectric material therebetween; forming a layer of pad material over the layer of charge storage material; forming an intervening layer over the layer of pad material; forming a set of sacrificial strips having sidewalls elongated in a first direction over the intervening layer with spaces between strips adjacent in a second direction, the sidewalls extending in a substantially vertical direction with respect to the surface of the substrate, the first and second directions being substantially perpendicular; forming a set of spacers along the sidewalls of the sacrificial strips, the spacers having a lower surface in contact across an upper surface of the intervening layer which is over the layer of pad material, the spacers having a material composition that is similar to a material composition of the intervening layer; removing the set of sacrificial strips thereby exposing the intervening layer between spacers adjacent in the second direction; etching the intervening layer and the layer of charge storage material using the set of spacers as a pattern to form a plurality of charge storage regions separated in the second direction with spaces therebetween; forming an inter-gate dielectric layer after forming the plurality of charge storage regions; and forming a set of control gates for the plurality of charge storage regions, the control gates being separated from the charge storage regions by the inter-gate dielectric material.