Patent ID: 7835465

Claim:
A method comprising: providing an analog to digital converter (ADC); during a first time interval, sampling a first one of a pair of analog signals in the ADC to provide a first digital signal; during a second time interval non-overlapping the first time interval, sampling the other one of the pair of analog signals in the ADC to provide a second digital signal, wherein the pair of analog signals have a predetermined phase relationship; and aligning the first and second digital signals to compensate for phase difference introduced by the sampling during the first and second time intervals, wherein the aligning comprises: delaying one of the first and second digital signals; and interpolating the other one of the first and second digital signals to compensate for the phase difference introduced by the sampling during the first and second time intervals, wherein interpolating the other one of the first and second digital signals realizes a delay of (2k+1)/2 clock cycles, where k is an integer.