Patent ID: 8539414

Claim:
A method of inserting a pipeline storage element into a logic design, said method comprising: using a computer, identifying a clock period of a clock signal of said logic design; selecting an asynchronous signal of said logic design having a delay from a source of said asynchronous signal to at least two destination storage elements that is approximately the same as or greater than said clock period; inserting a pipeline storage element after said asynchronous signal source and before a distribution buffer that routes said asynchronous signal to said at least two destination storage elements, wherein said pipeline storage element is inserted based on a determination that said delay is greater than or equal to said clock period; connecting said asynchronous signal source to an input of said pipeline storage element and connecting an output of said pipeline storage element to an input of said distribution buffer; and connecting said clock signal to a clock input of said pipeline storage element, whereby said asynchronous signal arrives at said at least two destination storage elements within a same clock cycle of said clock signal via the connection with said pipeline storage element.