Patent ID: 7284143

Claim:
A delay equalizer for balancing clock signals in a clock tree, comprising: a register operable to: receive a divided input clock signal; receive a non-divided input clock signal; and generate a first output clock signal based on the received divided input clock signal and the received non-divided input clock signal, the first output clock signal being associated with a first delay; a delay line operable to: receive the non-divided input clock signal; delay the non-divided input clock signal for a time substantially equivalent to the first delay associated with the first output clock signal; and generate a second output clock signal being associated with a second delay substantially equal to the first delay of the first output signal; and a multiplexer operable to: receive the first output clock signal and the second output clock signal; receive a select control signal indicating which of the first output clock signal or the second output clock signal to select, wherein the select control signal is programmable on the fly, and wherein the select control signal transitions only when the first output clock signal and the second output clock signal have the same phase; select either the received first output clock signal or the second output clock signal based on the select control signal; and generate the selected first output clock signal or second output clock signal as a substantially balanced third output clock signal.