Patent ID: 7124160

Claim:
A processing core, comprising: a first source register including a plurality of first operands, wherein the source address of each first operand is identified in a single instruction; a plurality of second operands, wherein: the plurality of second operands are equal in value to an immediate value, and the immediate value is specified in the single instruction, a prescaler which scales the plurality of operands according to a predetermined scaling factor which is divisable by two; a bitwise inverter coupled to at least one of the first plurality of operands and the prescaled second plurality of operands; a destination register including a plurality of results, a plurality of arithmetic processors respectively coupled to the first operands, prescaled second operands and results, wherein each arithmetic processor computes one of a sum and a difference of the first operand and a respective prescaled second operand, and wherein the computation operation to be undertaken by each arithmetic processor is specified in the single instruction.