Patent ID: 7724087

Claim:
A differential receiver circuit comprising: a first supply voltage port as a first rail for receiving of a first potential; a second supply voltage port as a second rail for receiving of a second potential that is lower than the first potential; a differential signal splitter including a first branch and a second branch disposed between the first supply voltage port and the second supply voltage port, the differential signal splitter further including a first input port and a second input port for receiving of a differential input signal and first through fourth output ports for providing of two complementary differential output signals; a common mode voltage normalization stage for level shifting the two complementary differential output signals to form one complementary differential output signal, the common mode voltage normalization stage including first through fourth input ports electrically coupled with the first through fourth output ports of the differential signal splitter stage, and further including first and second output ports of the common mode voltage normalization stage; a transimpedance amplifier including first and second input ports of the transimpedance amplifier electrically coupled with the first and second output ports of the common mode voltage normalization stage, and further including first and second output ports of the transimpedance amplifier for providing a rail to rail complementary differential output signal having low signal skew and symmetry; wherein the differential signal splitter the common mode voltage normalization stage and the transimpedance amplifier are disposed between the first supply voltage port and the second supply voltage port for receiving of the first potential and the second potential; wherein the first branch comprises: a first PMOS device having gate, drain and source terminals; a first NMOS device having a gate terminal and drain and source terminals electrically coupled with the drain and source terminals of the first PMOS device; wherein the second branch comprises: a second PMOS device having gate, drain and source terminals; a second NMOS device having a gate terminal and drain and source terminals electrically coupled with the drain and source terminals of the second PMOS device where the gate terminals of the first PMOS device and the second NMOS device are electrically coupled together and form the first input port of the differential signal splitter stage and the gate terminals of the second PMOS device and the first NMOS device form the second input port of the differential signal splitter stage.