Patent ID: 8089102

Claim:
A method for fabricating an integrated circuit device, comprising: fabricating a gate electrode level region that forms part of an overall gate electrode level of the integrated circuit device, wherein fabricating the gate electrode level region includes fabricating three or more linear conductive segments each fabricated to have a respective length and a respective width, wherein a size of the length of a given linear conductive segment is greater than a size of the width of the given linear conductive segment, and wherein the three or more linear conductive segments are fabricated to have their lengths extend in a first direction in a parallel manner, and wherein each of the three or more linear conductive segments is fabricated to have a substantially equal length as measured in the first direction, and wherein the three or more linear conductive segments are positioned in a side-by-side spaced-apart manner according to a substantially equal centerline-to-centerline spacing as measured in a second direction perpendicular to the first direction, and wherein some of the three or more linear conductive segments include one or more gate electrode portions that respectively form gate electrodes of transistor devices, and wherein at least one of the three or more linear conductive segments forms gate electrodes of two or more transistor devices including at least two different transistor device types.