Patent ID: 7958181

Claim:
A method comprising: receiving, in a processor, an instruction code that is of an instruction format comprising a first field and a second field, the first field to indicate a first multi-bit operand and the second field to indicate a second multi-bit operand; modifying, in the processor, a first status flag to a first value responsive to the instruction code and determining that a first intermediate result of a bit-wise logical AND operation of the value in each of one or more bit positions of the first operand with the complement of the value in the same respective bit position of the second operand is zero, and modifying the first status flag to a second value responsive to determining that the first intermediate result is non-zero; and modifying a second status flag to a third value responsive to the instruction code and determining that a second intermediate result of a bit-wise logical AND operation of the value in each of one or more bit positions of the first operand with the value in the same respective bit position of the second operand is zero, and modifying the second status flag to a fourth value responsive to determining that the second intermediate result is non-zero.