Patent ID: 6993633

Claim:
A computer system including a CPU, a memory, and a cache located in a hierarchy class between said CPU and said memory, said computer system comprising: a coherent controller for determining whether a request supplied from said CPU hits said cache to thereby issue a request to said cache or said memory; and a cache data controller for controlling reading or writing of data registered in said cache, in accordance with a request issued by said coherent controller; wherein upon accepting a read request from said CPU, said coherent controller conducts hit decision of said cache, issues an advanced speculative read request to said cache data controller before a result of the hit decision is indicated, and issues a read request to said cache data controller if the hit decision is a cache hit, and wherein said cache data controller comprises: means, responsive to acceptance of an advanced speculative read request issued by said coherent controller, for reading data from said cache and holding the data, and means responsive to acceptance of a read request and a cache hit decision for sending said held speculative read data to said CPU as response data.