Patent ID: 8524522

Claim:
A process, comprising: producing a first multi-layer substrate having a top surface and a bottom surface, the multi-layer substrate including a top layer defining the top surface, a first intermediate SiGe layer below the top layer, a second intermediate Si layer below the first intermediate layer and a substrate layer below the second intermediate layer and defining the bottom surface; producing electronic devices in and on the top layer of the first multi-layer substrate; producing an interconnect layer over the electronic devices; producing an encapsulating layer over the interconnect layer; attaching a second substrate to the encapsulating layer; thinning the first multi-layer substrate by use of an etch selective of Si so as to remove the substrate layer and second intermediate layer and leaving the top layer and first intermediate SiGe layer; and producing a passivation layer on a bottom etched surface of the first intermediate SiGe layer of the thinned first multi-layer substrate.