Patent ID: 8401059

Claim:
A radio communication system comprising a first radio terminal and a second radio terminal which are linked for wireless communication with each other, said first radio terminal comprising: a first transmitter configured to transmit a first data indicative of a specific event; said second radio terminal comprising: a second battery energizing said second radio terminal; a second receiver configured to receive said first data from said first radio terminal; a data analyzer configured to analyze said first data and generate information designated by said first data; an information provider configured to output said information; a second signal intensity detector configured to provide a receiving signal strength indication, wherein said first radio terminal includes a first bit interpolator configured to insert a check bit pattern at a predetermined cycle into one frame of said first data to make up a first bit-interpolated data to be transmitted to said second radio terminal, said check bit pattern being a bit series of “0” alternating with “1”; and said second radio terminal includes a second power controller configured to intermittently activate said second receiver at predetermined time intervals in order to receive said first bit-interpolated data from said first transmitter; said second power controller being configured to terminate a current receiving operation by deactivating the second receiver when the receiving strength indication provided by said second signal intensity detector is lower than a predetermined threshold; said second power controller being configured to enable a current receiving operation for a predetermined second detection time period shorter than a length of said frame of the first data in order to receive the first bit-interpolated data from said first transmitter when the receiving strength indication is greater than the predetermined threshold, said second radio terminal includes a second check bit detector configured to find whether said check bit pattern is detected from within said first bit-interpolated data received from said first radio transmitter, said second check bit detector being configured to issue a stop signal immediately upon occurrence of that said check bit pattern fails to appear within a predetermined second detection time period shorter than a length of said frame of the first data; said second power controller being configured to terminate a current receiving operation of said second receiver in response to said stop signal from said second check bit detector.