Patent ID: 6839888

Claim:
A bit-swapping method for use in a field programmable gate array, the field programmable gate array comprising 1) a first configurable logic block (CLB) having an N-bit output and a second CLB having an N-bit input; 2) a plurality of interconnects; and 3) interconnect switches for coupling ones of the interconnects to each other and to inputs and outputs of the first and second configurable logic blocks, the method comprising the steps of: setting the interconnect switches to a first switch configuration in which a first group of interconnects coupled to the N-bit output of the first CLB are connected to a second group of interconnects coupled to the N-bit input of the second CLB according to a first connection mapping; receiving a second switch configuration; and setting the interconnect switches to the second switch configuration in which the first group of interconnects are connected to the second group of interconnects according to a second connection mapping.