Patent ID: 8336017

Claim:
A method to automatically generate a processor architecture for a custom integrated circuit (IC) specified by a user code, the IC having at least one or more timing and hardware constraints, comprising: a. extracting parameters defining the processor architecture from a static profile and a dynamic profile of the user code, wherein extracting parameters further comprises: determining an execution cycle time for each instruction; determining an execution clock cycle count for each loop; generating an operator statistic table; generating statistics for each function; and sorting inner loops (kernels) by descending order of execution count; b. iteratively optimizing the processor architecture by changing one or more parameters of the processor architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO) and a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration to arrive at a customized architecture with an application specific instruction set; c. synthesizing the customized processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication; and d. changing the processor instruction set by automatically generating new instructions uniquely customized to the computer readable code to improve performance of the processor architecture, further including: identifying required memory bandwidth; replacing one or more software implemented flags as one or more hardware flags; and combining two or more operations into a new instruction.