Patent ID: 8183899

Claim:
A semiconductor integrated circuit comprising: a first circuit that operates using a first power-supply voltage supplied from a power supplying Large Scale Integration (LSI) circuit; a second circuit that operates using a second power-supply voltage; a clock generation circuit that generates a clock; a clock tree that transmits the clock generated by the clock generation circuit to the first circuit and the second circuit; a clock synchronization circuit having a plurality of delay stages that perform clock delay adjustment between a first path for transmitting the clock to the first circuit and a second path for transmitting the clock to the second circuit along the clock tree to synchronize the clock in the first and second paths; and a control circuit that notifies the power supplying LSI circuit of change control over the first power-supply voltage, wherein the power supplying LSI circuit is notified of a voltage change velocity for applying variable control to the first power-supply voltage, wherein control is performed to match a phase between the clock as supplied to the first circuit and the clock as supplied to the second circuit when a voltage of the first circuit is changed at the voltage change velocity, and wherein the clock synchronization circuit comprises: a second comparison circuit for comparing a phase between a clock output signal from a variable delay circuit and a clock signal propagated along a through path thereof; and a delay control circuit for controlling a delay setting provided by the variable delay circuit, wherein the delay control circuit, based on a comparison result from the second comparison circuit, sets a delay equivalent to an integral multiple of a clock cycle to an output from the variable delay circuit in accordance with the clock signal propagated along the through path, wherein the delay control circuit responds to an instruction to change the first power-supply voltage from a standard voltage to another voltage, wherein the delay control circuit allows a selection circuit to select an output from the variable delay circuit and adjusts a delay setting of the variable delay circuit based on a comparison result from a first comparison circuit, and wherein the delay control circuit controls phase synchronization between the clock transmitted to the first circuit and the clock transmitted to the second circuit.