Patent ID: 7783835

Claim:
A data processing system, comprising: a system memory, including a page table; and a processor, coupled to said system memory via an interconnect, wherein said processor further includes: a translation lookaside buffer (TLB) that determines whether a task switch has occurred, wherein the TLB includes: a first-level cache memory that casts out an invalidated page table entry and associated first page directory base address; and a second-level cache memory coupled to said first-level cache memory, wherein said second-level cache memory includes a second-level cache directory including: a current-running task directory associated with a first task for storing at least one page table entry evicted from said first-level cache memory; a task switch directory for storing at least one plurality of page table entries associated with at least one other task and sending a first plurality of page table entries associated with a new task to enable improved task switching without requiring access to said page table stored in said system memory to retrieve said first plurality of page table entries.