Patent ID: 8394692

Claim:
A method comprising: providing a semiconductor substrate; forming a transistor that includes a gate structure disposed over the semiconductor substrate, a source feature, and a drain feature, wherein the gate structure interposes the source feature and the drain feature and the gate structure includes a dummy gate; forming a first dielectric layer over the semiconductor substrate and the transistor; forming a first contact feature having a first width in the first dielectric layer, wherein the first contact feature is coupled to one of the source feature and the drain feature; removing a portion of the first dielectric layer such that the dummy gate of the gate structure is exposed and a portion of the first dielectric layer remains; replacing the dummy gate of the gate structure with a metal gate; after replacing the dummy gate, forming a second dielectric layer over the remaining portion of the first dielectric layer; and forming a second contact feature having a second width in the second dielectric layer, the second width being substantially the same as the first width, wherein the second contact feature is coupled to the first contact feature.