Patent ID: 7334168

Claim:
A semiconductor integrated circuit, comprising: a first electrical source terminal which receives a first electrical source voltage; a second electrical source terminal which receives a second electrical source voltage lower than the first electrical source voltage; a plurality of external input terminals which receives a plurality of external test signals; a logic circuit, coupled to the external input terminals, which outputs a plurality of internal test signals based on the external test signals; a circuit under test (CUT), coupled to the logic circuit, which receives the internal test signals; a delay time measurement terminal from which a delay time measurement signal is output, wherein the delay time measurement signal is turned in accordance with a transition of one of the internal test signals; a current generator coupled between the first electrical source terminal and the delay time measurement terminal; and a plurality of delay time measurement transistors which are coupled in parallel between the delay time measurement terminal and the second electrical source terminal and which have a plurality of control electrodes, wherein the control electrodes of the delay time measurement transistors are coupled to the logic circuit to receive the internal test signals.