Patent ID: 7330953

Claim:
A system comprising: a first set of interconnect resources to convey: a sense command; and after the sense command, a write command that specifies a write operation; a second set of interconnect resources to convey: a row address that identifies row of a memory array to sense in response to the sense command; and after the row address, a column address that identifies a column location of the row; a third set of interconnect resources to convey data; and a memory device comprising: a memory core including a plurality of memory cells; a first set of pins coupled to the first set of interconnect resources, the first set of pins to receive the sense command and the write command, wherein, after a first delay time transpires from when the write command is received at the first set of pins, the memory device applies a control signal to convey a plurality of data bits to the column location, in response to the write command; a second set of pins coupled to the second set of interconnect resources, the second set of pins to receive the row address and the column address; and a third set of pins coupled to the third set of interconnect resources, the third set of pins to receive the plurality of data bits after a second delay time has transpired from when the write command is received at the second set of pins.