Patent ID: 6854078

Claim:
A multi-bit test circuit for determining a match in logical level among a plurality of data bits read out in parallel from a memory array, comprising: a plurality of first determining circuits, arranged corresponding to said plurality of data bits, each for receiving, as a pair, a corresponding data bit and a teacher data bit placed in a predetermined relation with said corresponding data bit in the plurality of data bits, and determining a match in logical level between received data bits, data bits in each pair including different teacher data bits from other pair(s), said plurality of data bits being divided into at least three groups, and the first determining circuits being arranged such that a data bit in a group of said at least three groups is compared with a data bit in each of other two groups, and the number of said plurality of first determining circuits being the same as the number of said plurality of data bits; and a final determining circuit for outputting a final determination signal indicating a match in logical level among said plurality of data bits in accordance with output signals of said plurality of first determining circuits.