Patent ID: 7812751

Claim:
An apparatus comprising: a delay element arranged to produce a delayed version of a digital signal having a plurality of first data-bits, the delayed version having a same number of second data-bits as a number of first data-bits, the delay element arranged to delay each of the second data bits by a same amount; and at least one of the following: a first level shifter arranged to modify a level of said digital signal and a second level shifter arranged to modify a level of said delayed version of said digital signal; and a digital-to-analog conversion circuitry arranged to convert said digital signal into a first analog signal, to convert said delayed version of said digital signal into a second analog signal, and to produce a filtered analog signal as a combination of said first analog signal and said second analog signal; wherein the digital-to-analog conversion circuitry comprises a first set of conversion cells arranged to produce said first analog signal and a second set of conversion cells arranged to produce said second analog signal, each conversion cell including a current source arranged to produce an electrical current, a pair of selector switches, and a current division switch that is arranged to control, according to a value of a carrier signal, distribution of the electrical current between the selector switches, the pair of selector switches being arranged to control, according to a value of a data-bit, a flow path of the electrical current.