Patent ID: 8161272

Claim:
A memory control circuit comprising: a branch detection section to detect a branch instruction from an instruction fetched from a memory unit including a plurality of operation modes; and a mode control section to change an operation mode of the memory unit according to a detection result by the branch detection section, wherein: the memory unit comprises a plurality of memories, the plurality of operation modes comprise a normal mode allowing access and a standby mode consuming a lower power than the normal mode, and in response to the detection of a branch instruction from an instruction fetched from any one of the plurality of memories, the mode control section makes standby release of the other memories, the branch detection section detects a branch instruction from an instruction prefetched according to a fetch address output from a central processing unit (CPU), the fetch address being an instruction address to be fetched, the mode control section makes the standby release at a timing determined by a timing when the prefetched branch instruction is fetched and a predetermined time, and the mode control section calculates the timing to make the standby release from the instruction address of the branch instruction and the predetermined time, and makes the standby release when the fetch address output from the CPU becomes an address indicating the timing to make the standby release.