Patent ID: 8395937

Claim:
An integrated circuit device comprising: a memory cell array comprising: a plurality of bit lines; a plurality of bit line segments, wherein at least two bit line segments are associated with each of the plurality of bit lines, and wherein each of the plurality of bit line segments is configured to be selectively and responsively coupled to or decoupled from an associated bit line; a plurality of word lines; and a plurality of memory cells, wherein each of the plurality of memory cells stores at least two data states and comprises a transistor, wherein the transistor comprises: a first region coupled to an associated bit line segment; a second region; a body region disposed between the first region and the second region; and a gate coupled to an associated word line; wherein: (i) a first group of memory cells is coupled to a first bit line via a first bit line segment; and (ii) a second group of memory cells is coupled to the first bit line via a second bit line segment; and a plurality of isolation circuits, wherein each of the plurality of isolation circuits is associated with a bit line segment and is disposed between the associated bit line segment and an associated bit line, and comprises a transistor comprising: (i) a first region coupled to the associated bit line; (ii) a second region coupled to the associated bit line segment; (iii) a body region disposed between the first region and the second region; and (iv) a gate configured to receive a control signal, wherein: (i) a first isolation circuit is disposed between the first bit line segment and the first bit line; and(ii) a second isolation circuit is disposed between the second bit line segment and the first bit line.