Patent ID: 8115194

Claim:
A semiconductor device, comprising: two transistors, each of the two transistors comprising a first source or drain region and a second source or drain region disposed on a substrate, and a gate structure disposed on a channel region between the first source or drain region and the second source or drain region, wherein the channel regions of the two transistors have identical lengths, and the first source or drain region and the second source or drain region of the same transistor are different in width along a channel length direction; two strain layers, each of the two strain layers comprising a first strain layer and a second strain layer embedded at two sides of the gate structure of each of the two transistors in the substrate respectively, wherein the first strain layer and the second strain layer are either completely or partially overlapped with and covered by the first source or drain region and the second source or drain region respectively, and the first strain layers have an identical first width along the channel length direction, and the second strain layers have an identical second width along the channel length direction; and a contact, disposed above the second source or drain region of each of the two transistors not overlapped with the second strain layer.