Patent ID: 7838929

Claim:
A semiconductor device comprising: a substrate; an isolation layer disposed in the substrate to define an active region such that interfaces between the isolation layer and the active region are constituted by opposite edges of the active region, respectively, and the active region has a respective recess in each of at least one of the opposite edges thereof; a gate electrode extending lengthwise across the active region so as to lie over said opposite edges of the active region; a source region and a drain region disposed in the active region on both sides of the gate electrode, respectively, each said recess having a width in the lengthwise direction of the gate electrode that is less than the width of active region in the lengthwise direction such that the recess is delimited by and between the isolation layer and a central portion of the active region that spans the source and drain regions; and a respective gate extension contiguous with the gate electrode and occupying the recess in abutment with the isolation layer and the central part of the active region, whereby each said recess and the respective gate extension occupying the same constitute a recessed region, and wherein the device has a first effective channel length between the source region and the drain region along said one of the opposite edges of the active region, and a second effective channel length between the source region and the drain region along the central portion of the active region, and the first effective channel length is greater than the second effective channel length.