Patent ID: 8129816

Claim:
A semiconductor device, comprising: a semiconductor substrate having an upper surface; an element isolation region including a plurality of trenches being formed in the semiconductor substrate along a first direction and a second direction crossing the first direction, the trench having a sidewall and a bottom surface located at a first depth and being filled with an element isolation insulating film; an element forming region formed on the semiconductor substrate, the element forming region being surrounded by the element isolation region; a gate electrode formed along the first direction on the element forming region via a gate insulating film, the gate electrode extending over the element isolation insulating film filled in the trenches extending along the second direction; a source/drain region formed in a portion of the element forming region located beside the gate electrode; the source/drain region having a second depth less than the first depth, and having an exposed surface exposed to the sidewall of the trench; a first silicon oxide film formed on a sidewall of the gate electrode; a first silicon nitride film constituting a spacer formed on the first silicon oxide film; a second silicon oxide film formed on the first silicon nitride film, on an upper surface of the source/drain region, and on an upper surface of the element isolation insulating film; and a second silicon nitride film formed on the second oxide film; wherein an upper surface of the element isolation insulating film exclusive of a portion underlying the gate electrode is located at a third depth greater than the second depth and less than the first depth so that the exposed surface of the source/drain region does not contact the element isolation insulating film.