Patent ID: 6975139

Claim:
An integrated circuit, comprising: a first plurality of M number of conductors; a second plurality of k sets of N number of conductors (k×N number of conductors); and a switching network (SN), wherein M is at least k+N, where k is at least two and N is at least two; wherein the SN comprises: a plurality of switches; a third plurality of I0 number of conductors, including N0 sets of I0 i number of conductors for i=[1−N0], wherein N0 is at least two, N is at least N0, I0 is at least equal to M and between M and (k×N) when M is less than (k×N); any two conductors of the first plurality of M number of conductors to selectively couple to at least two different conductors selected each from at least two different I0 p number of conductors and I0 q number of conductors, respectively, for p, q=[1−N0] through the plurality of switches without requiring traversal of another conductor; a first conductor of said at least two different conductors to selectively couple to a first set of at most (k×(M/N0)) number of conductors through the SN, wherein the first set of at most (k×(M/N0)) number of conductors has at most (M/N0) number of conductors from each of the k sets of N number of conductors; and a second conductor of the at least two different conductors to selectively couple to a second set of at most (k×(M/N0)) number of conductors through the SN, wherein the second set of at most (k×(M/N0)) number of conductors has at most (M/N0) number of conductors, different from the first set of at most (k×(M/N0)) number of conductors, from each of the k sets of N number of conductors.