Patent ID: 7335566

Claim:
A method for forming a semiconductor integrated circuit device comprising: providing a semiconductor substrate; forming a dielectric layer overlying the semiconductor substrate; forming a polysilicon gate layer overlying the dielectric layer, the polysilicon gate layer being overlying a channel region in the semiconductor substrate; forming a hard mask layer overlying the polysilicon gate layer; patterning the polysilicon gate layer, including the hard mask layer, to form a gate structure including edges; forming a dielectric layer overlying the gate structure and hard mask layer to protect the gate structure including the edges; patterning the dielectric layer to form sidewall spacer structures on the gate structure, including the edges, and exposing a portion of the hard mask layer; etching a source region and a drain region adjacent to the gate structure using the sidewall spacer structures, and said portion of the hard mask layer and sidewall spacer structures are used as a protective structure for the gate layer; depositing silicon germanium fill material into the source region and the drain region to fill the etched source region and the etched drain region while causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region; forming a blanket layer of material having an initial thickness overlying the source region, the drain region, and the gate structure to cover an upper surface of the gate structure, including the hard mask layer, to form a substantially planarized surface region from the blanket layer; removing a portion of the initial thickness of the blanket layer to remove the hard mask layer and expose a portion of the gate layer; and introducing dopant impurities into the portion of the gate layer using at least an implantation process to dope the gate layer, while maintaining the source region and the drain region free from the dopant impurities.