Patent ID: 7847409

Claim:
An interconnect structure comprising: a lower metal wiring level comprising first metal lines positioned within a dielectric stack including a lower low-k dielectric and a first rigid dielectric layer located on said lower low-k dielectric, wherein each of said first metal lines has an upper surface that is coplanar with an upper surface of the first rigid dielectric layer; an upper metal wiring level atop said lower metal wiring level, said upper metal wiring level comprising second metal lines positioned within an upper low-k dielectric; and a plurality of metallic filled vias through a portion of said upper low-k dielectric electrically connecting said lower metal wiring level and said upper metal wiring level, where said plurality of metallic filled vias comprise a set of rigid dielectric sidewall spacers, wherein at least some of the rigid dielectric sidewall spacer have an upper surface that is coplanar with an upper surface of said plurality of metallic filled via, wherein a dielectric material for said rigid dielectric sidewall spacer is selected from the group consisting of SiCH, SiC, SiNH, SiN, and SiO 2 .