Patent ID: 8115295

Claim:
A semiconductor device comprising: a semiconductor chip including a main surface, a back surface opposite to the main surface, a plurality of pads arranged over the main surface, a low noise amplifier for amplifying an inputted signal arranged over the main surface, and a RFVCO (Radio Frequency Voltage Controlled Oscillator) configured to convert a frequency of a signal supplied from the low noise amplifier arranged over the main surface, the plurality of the pads including a first pad and a second pad, the first pad and the second pad being electrically connected to the low noise amplifier and the RFVCO, respectively; a wiring substrate including a main surface, a back surface opposite to the main surface, a first side, a second side different from the first side, a plurality of bonding electrodes arranged over a peripheral portion of the main surface of the wiring substrate, the plurality of the bonding electrodes including a first bonding electrode, a second bonding electrode, a first GND bonding electrode, a second GND bonding electrode, a third GND bonding electrode, and a fourth GND bonding electrode; a sealing body sealing the semiconductor chip; a plurality of external terminals arranged over the back surface of the wiring substrate and being electrically connected to the plurality of the bonding electrodes; and a plurality of solder balls mounted over the plurality of external terminals, respectively; wherein the semiconductor chip is mounted over the main surface of the wiring substrate, and the first pad and the second pad of the semiconductor chip are electrically connected to the first bonding electrode and the second bonding electrode of the wiring substrate with a first conductive wire and a second conductive wire respectively, wherein the first bonding electrode is disposed between the first GND bonding electrode and the second GND bonding electrode, and the second bonding electrode is disposed between the third GND bonding electrode and the fourth GND bonding electrode, wherein the wiring substrate further includes a first conductor pattern and a second conductor pattern which are disposed over the main surface thereof, wherein the first conductor pattern electrically connects the first GND bonding electrode and the second GND bonding electrode to each other such that the first conductor pattern surrounds the first bonding electrode in a plan view, wherein the second conductor pattern electrically connects the third GND bonding electrode and the fourth GND bonding electrode to each other such that the second conductor pattern surrounds the second bonding electrode in the plan view, and wherein the first bonding electrode, the first GND bonding electrode, and the second GND bonding electrode are disposed along the first side of the wiring substrate, and the second bonding electrode, the third GND bonding electrode, and the fourth GND bonding electrodes are disposed along the second side of the wiring substrate.