Patent ID: 8759923

Claim:
A semiconductor device structure, comprising: a semiconductor substrate; a channel region buried in the semiconductor substrate and formed by epitaxial growth; a gate stack formed on the channel region; source/drain regions formed on opposite sides of the channel region, wherein the semiconductor device structure further comprising a sidewall spacer formed only on lateral sides of the gate stack, wherein in the direction of gate width, a cut is positioned between adjacent gate stacks and adjacent sidewall spacers, and a dielectric material is filled in the cut, so as to achieve electrical isolation between the gate stacks, wherein the end of the sidewall spacer is flush with the end of the gate electrode in the direction of the gate width, and wherein the semiconductor device structure further comprises lower contact portions and upper contact portions, the lower contact portions being in contact with the source/drain regions and level with the top of the gate stack, and the upper contact portions being in contact with the top of the gate stack and the lower contact portions, respectively, and wherein, on the source/drain regions, the lower contact portions are aligned with the upper contact portions, and the top of the lower contact portions is of the same high as the top of the gate stack.