Patent ID: 7057226

Claim:
A semiconductor device, comprising: a device isolation film arranged on a portion of a semiconductor substrate and restricting an active region, wherein the substrate includes a trench region and the device isolation film is filled in the trench region; a word line crossing over the active region; a gate pattern including a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern in the stated order with the word line contacting the control gate electrode; and a tunnel oxide film disposed between the gate pattern and the active region, wherein: the gate pattern is isolated by, and is self-aligned to the device isolation film so that the gate pattern and the device isolation film contact each other and the gate pattern is positioned between the word line and tunnel oxide film, a gate sidewall dielectric film and a sidewall spacer cover a sidewall of the gate pattern, and the control gate electrode pattern and the sidewall spacer are connected together to the word line, the sidewall spacer is a conductive film, and the sidewall spacer conductive film is a poly-silicon film.