Patent ID: 7366809

Claim:
A system for improving data speed in an I 2 C system including a serial clock conductor for conducting a serial clock signal SCK and a serial data conductor for conducting a serial data signal SDA, the system comprising: (a) a master device coupled to the serial clock conductor and the serial data conductor for sending and receiving data signals on the serial data conductor and generating the serial clock signal SCK on the serial clock conductor, the master device including a master CPU, a control circuit coupled to the master CPU and the serial clock conductor and the serial data conductor, and a clock generation circuit, the control circuit being coupled to the master CPU, the control circuit including a finite state machine; (b) a start instruction circuit coupled between the master CPU and the control circuit, a stop instruction circuit coupled between the master CPU and the control circuit, and an address instruction circuit coupled between the master CPU and the control circuit; (c) the master CPU executing a combined stop/start/address instruction by setting a stop bit in the stop instruction circuit, setting a start bit in the start instruction circuit, and storing an address byte in the address instruction circuit; (d) the control circuit causing a stop condition to be sent via the interface circuit to the serial clock conductor and the serial data conductor in response to the stop bit, the control circuit causing a start condition to be automatically sent via the interface circuit to the serial clock conductor and the serial data conductor in response to the start bit a predetermined delay after the stop condition has been sent; and (e) the control circuit operating in response to the address instruction circuit, without the master CPU being first notified that the start condition has been sent, to cause the address byte to be automatically sent via the interface circuit to the serial clock conductor and the serial data conductor after the start condition has been sent.