Patent ID: 8841752

Claim:
A semiconductor structure, comprising: a plurality of interposer dice on an un-singulated semiconductor wafer, wherein scribe lanes between neighboring pairs of the dice have widths of at least 5.0% of the width of each interposer die plus an amount that compensates for material that would be removed in singulating the wafer, and each interposer die including: a first contact array formed on a first side of the interposer die; a plurality of vias formed through the interposer die; one or more wiring layers formed on the first side of the interposer die and electrically coupling each contact of the first contact array to a corresponding one of the plurality of vias; and a second contact array formed on a second side of the interposer die, each contact in the second contact array coupled to a corresponding one of the plurality of vias; and for each interposer die of the plurality of interposer dice, one or more stiffening structures formed in and completely confined to one or more of the scribe lanes that circumscribe the interposer die, respectively, the one or more stiffening structures having a width of at least 2.5% of the width of each interposer die plus an amount that compensates for material that would be removed in singulating the wafer.