Patent ID: 7557022

Claim:
A method of forming an NMOS transistor comprising: performing an LDD implantation to establish source/drain extension regions in a substrate on either side of a gate structure formed on the substrate, where the LDD implantation comprises: implanting at least one of arsenic, phosphorous and antimony; and implanting at least one of carbon, atomic fluorine and molecular fluorine (F 2 ); forming source/drain regions in the substrate on ether side of the gate structure, the source/drain regions being distanced from the gate structure further than the source/drain extension regions; and forming halo regions in the substrate on ether side of the gate structure, the source/drain regions being distanced from the gate structure further than the halo regions, forming the halo regions comprising: implanting at least one of arsenic, phosphorous and antimony; and implanting at least one of boron, indium and/or boron di-fluoride (BF 2 ).