Patent ID: 8102712

Claim:
A method of programming a NAND memory array, comprising: selecting a word line of the NAND memory array to program at least two memory cells coupled to the word line, the word line being coupled to a plurality of memory cells; programming the at least two memory cells coupled to the word line by applying a programming voltage Vpgm as a double pulse to the word line if a data pattern associated with at least two memory cells that are to be programmed is a two-sided column-stripe (CS2) data pattern, a first memory cell of the at least two memory cells being programmed by the first programming voltage pulse and a second memory cell of the at least two memory cells being programmed by the second programming voltage pulse; and programming the at least two memory cells coupled to the word line by applying a programming voltage Vpgm as a single pulse to the word line if a data pattern associated with at least two memory cells that are to be programmed is not a two-sided column-stripe (CS2) data pattern.