Patent ID: 7710094

Claim:
A power-current sensing circuit comprising: an input having an input voltage; a power transistor having a gate receiving a first clock, for conducting a power current from the input to a power node when the first clock is active during a first state and for isolating the input from the power node during a second state; a mirror transistor having a gate receiving a third clock, for conducting current from the input to a mirror node when the third clock is active during the first state and for isolating the input from the mirror node during the second state; a first switch that connects the power node to a first compare node during the first state and isolates the power node from the first compare node during the second state; a second switch that connects the mirror node to a second compare node during the first state and isolates the mirror node from the second compare node during the second state; an amplifier that compares voltages of the first compare node and the second compare node to generate a compare output; a sensing transistor having a gate receiving the compare output, for conducting a sense current from the mirror node to a sense node; and a bistable that is triggered into the first state by a periodic clock and is triggered into the second state by the sense node, whereby the second switch matches offsets created by the first switch.