Patent ID: 7394682

Claim:
A bit line dummy core-cell, comprising: (a) at least a first inverter and at least a second inverter which are cross-coupled to form a bistable flip-flop, wherein the first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential and the second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node, wherein the source of the second PMOS transistor and the second internal storage node are connected to the low reference potential, so that the first internal storage node always stores a logic high level; (b) a dummy bit line configured to provide a self-timing signal; and (c) a first access transistor coupled between the dummy bit line and the first internal node that stores the logic high level.