Patent ID: 7286431

Claim:
A memory device comprising: a plurality of normal memory cells including respective electrically conductive magnetic elements; a plurality of normal bit lines provided correspondingly to the plurality of columns of said plurality of normal memory cells; a plurality of first reference memory cells provided on a column placed in parallel with said plurality of columns of said plurality of normal memory cells; a first reference bit line provided correspondingly to said column of said plurality of first reference memory cells; a plurality of spare memory cells each used instead of a defective memory cell when said defective memory cell exists in said plurality of normal memory cells; a plurality of spare bit lines provided correspondingly to the plurality of columns of said plurality of spare memory cells; and a read circuit connected to at least three bit lines including a first bit line of said plurality of normal bit lines to which a memory cell to be read is connected, a second bit line to which a spare memory cell corresponding to said memory cell to be read is connected and said first reference bit line according to said address signal to read data from one of said memory cell to be read and said spare memory cell corresponding to said memory cell to be read.