Patent ID: 6912687

Claim:
A parity assist circuit for use with a controller, comprising: a scatter-gather list processor adapted for coupling to a cache memory of the controller to process a scatter-gather list each entry of which specifies parameters of at least one XOR computation to be performed; and an XOR engine coupled to said scatter-gather list processor that produces an XOR product of data stored in the cache memory in accordance with parameters supplied by said scatter-gather list processors, wherein the parity assist circuit is operable in accordance with parameters supplied by said scatter-gather list processor to read data previously stored in the cache memory by operation of the counter, and wherein the parity assist circuit is operable to read the data to compute the XOR product without transferring the read data to a device external to the controller, and wherein the parity assist circuit is configurable to generate a single interrupt applied to a CPU of the controller regardless of the number of XOR products computer by its operation.