Patent ID: 7962724

Claim:
A system comprising: a memory configured to store instructions corresponding to one or more threads of a computer program; and an instruction fetch unit coupled to the memory, wherein the instruction fetch unit is configured to: store a small branch state bit, wherein a value of the bit indicates whether an immediately prior fetched memory line included a small backward branch instruction, wherein a small backward branch instruction is a given branch instruction with a target that is in a same memory line as the given branch instruction and is younger in program order than the given branch instruction; maintain a prefetch inhibit signal, wherein when set the prefetch inhibit signal prevents speculative prefetching of instructions; in response to a request for a first memory line: fetch the first memory line of instructions; speculatively prefetch a second memory line, in response to detecting the inhibit signal is not asserted; inhibit prefetch of the second memory line, in response to detecting the inhibit signal is asserted; in response to detecting the first memory line includes a branch instruction and identifying the branch instruction as a small backward branch instruction: in response to determining the small branch state bit is set, set the prefetch inhibit signal, otherwise, set the small branch state bit; in response to detecting the first memory line does not include a small backward branch instruction: clear the prefetch inhibit signal; and clear the small branch state bit.