Patent ID: 8461674

Claim:
A thermal plate, configured to overlay a temperature controlled base plate of a substrate support assembly used to support a semiconductor substrate in a semiconductor processing apparatus, the thermal plate comprising: an electrically insulating plate; planar thermal zones comprising at least first, second, third and fourth planar thermal zones, each comprising one or more Peltier devices as thermoelectric elements, the planar thermal zones laterally distributed across the electrically insulating plate and operable to tune a spatial temperature profile on the substrate; positive voltage lines comprising first and second electrically conductive positive voltage lines laterally distributed across the electrically insulating plate; negative voltage lines comprising first and second electrically conductive negative voltage lines laterally distributed across the electrically insulating plate; common lines comprising first and second electrically conductive common lines laterally distributed across the electrically insulating plate; first, second, third, fourth, fifth, sixth, seventh and eighth diodes laterally distributed across the electrically insulating plate; wherein: an anode of the first diode is connected to the first positive voltage line and a cathode of the first diode is connected to the first planar thermal zone; an anode of the second diode is connected to the first planar thermal zone and a cathode of the second diode is connected to the first negative voltage line; an anode of the third diode is connected to the first positive voltage line and a cathode of the third diode is connected to the second planar thermal zone; an anode of the fourth diode is connected to the second planar thermal zone and a cathode of the fourth diode is connected to the first negative voltage line; an anode of the fifth diode is connected to the second positive voltage line and a cathode of the fifth diode is connected to the third planar thermal zone; an anode of the sixth diode is connected to the third planar thermal zone and a cathode of the sixth diode is connected to the second negative voltage line; an anode of the seventh diode is connected to the second positive voltage line and a cathode of the seventh diode is connected to the fourth planar thermal zone; an anode of the eighth diode is connected to the fourth planar thermal zone and a cathode of the eighth diode is connected to the second negative voltage line; the first common line is connected to both the first and third planar thermal zones; and the second common line is connected to both the second and fourth planar thermal zones.