Patent ID: 8347067

Claim:
Apparatus for processing data comprising: pre-decoding circuitry, responsive to program instructions fetched from a memory, configured to perform pre-decoding operations upon said program instructions to form pre-decoded instructions; a cache memory coupled to said pre-decoding circuitry configured to store said pre-decoded instructions; decoding circuitry, responsive to pre-decoded instructions read from said cache memory, configured to generate control signals; and processing circuitry, responsive to said control signals, configured to perform processing operations specified by said pre-decoded instructions; wherein said program instructions are from a plurality of different instruction sets; said pre-decoding circuitry maps a first program instruction from a first instruction set and a second program instruction from a second instruction set to pre-decoded instructions having a same format to represent a shared functionality, said first and second program instructions of said first and second instructions sets having both said shared functionality and a non-shared functionality; and a shared portion of said decoding circuitry, responsive to said pre-decoded instructions having said same format, configured to generate said control signals to control said processing circuitry with respect to said shared functionality, wherein said pre-decoded instructions having said same format include one or more bit fields used to represent said functionality not shared by said first and second program instructions.