Patent ID: 7130220

Claim:
A method for operating a memory, comprising: programming one or more floating gate transistors in a memory array, wherein each floating gate transistor in the memory array includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric, each floating gate transistor having a plug coupling the source region to an array plate and a bitline coupled to the drain region along rows in the memory array, and wherein programming the one or more floating gate transistors in a reverse direction includes: applying a first voltage potential to a drain region of the floating gate transistor; applying a second voltage potential to a source region of the floating gate transistor; applying a gate potential to a control gate of the floating gate transistor; and wherein applying the first, second and control gate potentials to the one or more floating gate transistors includes creating a hot electron injection into the floating gate of the one or more floating gate transistors adjacent to the source region such that the one or more floating gate transistors become programmed floating gate transistors and operate at reduced drain source current in a forward direction.