Patent ID: 7856074

Claim:
A signal processing system comprising: a first signal processing circuit comprising a first flip flop circuit outputting parallel data signals and a first part of a first PLL circuit providing a first clock signal to the first flip flop circuit for outputting the parallel data signals from the first flip flop circuit at a timing of the first clock signal; and a second signal processing circuit comprising a second flip flop circuit and a third flip flop circuit, the second flip flop circuit receiving the parallel data signals output from the first signal processing circuit via a transmission path, and the third flip flop circuit receiving parallel data signals from the second flip flop circuit via a transmission path, a second part of the first PLL circuit providing a first clock signal to the second flip flop circuit, and a second PLL circuit providing a second clock signal to the third flip flop circuit, the third flip flop circuit outputting the parallel data signals received from the second flip flop circuit at a timing of the second clock signal, wherein: the second part of the first PLL circuit comprises a phase comparison circuit carrying out phase comparison between the first clock signal transmitted from the first part of the first PLL circuit via a clock transmission path between the first and second signal processing circuits and the second clock signal provided by the second PLL circuit; and the first PLL circuit is configured to control, based on a comparison result of the phase comparison circuit, phase of the first clock signal to provide in such a manner that a phase difference between the first clock signal and the second clock signal is fixed in the second signal processing circuit.