Patent ID: 7982252

Claim:
A non-volatile memory comprising: a memory array having strings of serially connected memory cells arranged along rows and columns and a common bottom wordline plane comprising a conductive material, each serially connected memory cell comprising: a first gate forming part of the common bottom wordline plane; a first dielectric layer extending over the first gate; a semiconductor region extending over the first dielectric layer, the semiconductor region including a channel region extending directly over the first gate; a second dielectric layer extending over the semiconductor region; a ferroelectric layer extending over the second dielectric layer; and a second gate comprising a second conductive material extending over the ferroelectric layer, the second gate forming part of one of a plurality of top wordlines, the plurality of top wordlines extending along the rows parallel to the common bottom wordline plane, wherein the channel regions of the serially connected memory cells are isolated from each other along the horizontal dimension, and the common bottom wordline plane extends continuously under multiple wordlines of the plurality of top wordlines.