Patent ID: 6867994

Claim:
A semiconductor memory device comprising: a plurality of memory cells, arranged in rows and columns, each including a transistor and a capacitor; a plurality of bit lines provided corresponding to respective memory cell columns; and a plurality of word lines provided corresponding to respective memory cell rows and crossing said plurality of bit lines, each memory cell including an active region arranged extending in a direction between a direction of extension of a corresponding word line and a direction of extension of a bit line and arranged crossing the word line and the bit line and a storage node electrically connected to said active region and serving as one electrode of said capacitor, said active region defining a transistor formation region of said each memory cell, and a bit line contact for electrically connecting the active region of each of the memory cells and a corresponding bit line being provided in alignment for each bit line in a row direction, two word lines being provided between bit line contacts adjacent in a column direction, and each bit line contact being shared by two memory cells adjacent in the column direction.