Patent ID: 7467124

Claim:
A logic circuit comprising: an input data node for carrying input data; a configurable logic block (CLB) control logic circuit having a first input, a second input, a third input, a fourth input and an output; at least one look-up table in which a switching function of at least one conditional branch is implemented with content addressability, wherein the at least one look-up table generates an “if then else” branch that realizes a comparison of the input data with comparison data previously stored in the at least one look-up table, and wherein a result output of the at least one look-up table is provided to a third input of the CLB control logic circuit; an input data bus coupled between the input data node and a bus input of the at least one look-up table, wherein the first input of the CLB control logic circuit is coupled to the input data node via the input data bus; at least one multiplexer having a control input coupled to the input data node and also to the first input of the CLB control logic circuit via at least part of the bit width of the input data bus, an output of the at least one multiplexer being coupled to a fourth input of the CLB control logic circuit; a control input node coupled via a control bus to the second input of the CLB control logic circuit; and at least one register data bus coupled between a register data bus output of the at least one look-up table and a bus input of the at least one multiplexer.