Patent ID: 8901981

Claim:
A multi-stage phase mixer circuit comprising: a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to first coarse control of a first coarse control signal; a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to second coarse control of a second coarse control signal; and a third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to fine control of a fine control signal, the fine control adjusting a phase of the output clock signal more finely than the first and second coarse controls adjust phases of the first and second intermediate clock signals, respectively, wherein each of the first, second, and third phase mixers comprises two or more inverting logic circuits, and wherein an inverting logic circuit among the two or more inverting logic circuits of the first phase mixer includes a string that has two PMOS transistors and two NMOS transistors coupled in series, a gate of one of the PMOS transistors coupled to ground, and a gate of one of the NMOS transistors coupled to a power source that provides a voltage level corresponding to a logical high value.