Patent ID: 8665197

Claim:
A display device comprising: a substrate; a driver circuit over the substrate; and a pixel over the substrate, and electrically connected to the driver circuit, wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein the pixel comprises a seventh transistor and a display element, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor have a same conductivity type, wherein a gate of the first transistor is electrically connected to a first input terminal, wherein a gate of the second transistor is electrically connected to a second input terminal, wherein a gate of the third transistor is electrically connected to the gate of the second transistor, wherein a gate of the fourth transistor is electrically connected to the gate of the first transistor, wherein a gate of the fifth transistor is electrically connected to one of source and drain of the first transistor, wherein the gate of the fifth transistor is electrically connected to one of source and drain of the second transistor, wherein a gate of the sixth transistor is electrically connected to one of source and drain of the fourth transistor, wherein the gate of the sixth transistor is electrically connected to one of source and drain of the third transistor, wherein a first wiring is electrically connected to the other of source and drain of the first transistor, wherein a second wiring is electrically connected to the other of source and drain of the second transistor, wherein the second wiring is electrically connected to the other of source and drain of the fourth transistor, wherein a wiring for supplying a clock signal is electrically connected to one of source and drain of the fifth transistor, wherein an output terminal is electrically connected to the other of source and drain of the fifth transistor, wherein the output terminal is electrically connected to one of source and drain of the sixth transistor, and wherein the other of source and drain of the sixth transistor is electrically connected to the second wiring.