Patent ID: 7132870

Claim:
A circuit, comprising: an input conveying an input signal: a first pass gate coupled to the input and enabling a first signal in response to the input signal and in response to a master clock signal generating a clock signal; a first storage node having an input coupled to the first pass gate and having an output storing the first signal; a second pass gate connected to the output of the first storage node and enabling a second signal in response to the first signal stored on the output of the first storage node and in response to a slave clock signal, wherein the slave clock is a compliment to the master clock signal; a first inverter connected to the output of the first storage node and generating a first inverted signal in response to the first signal stored on the output of the first storage node; a third pass gate connected to the first inverter and enabling a third signal in response to the first inverted signal and in response to the slave clock signal; and an unclocked second storage node having a signal node coupled to the second pass gate and having a complementary signal node coupled to the third pass gate, the signal node storing the second signal and the complementary signal node storing the third signal.