Patent ID: 8332788

Claim:
A method of processing a logical netlist for implementing a circuit design within a programmable integrated circuit, the method comprising: within the logical netlist, identifying a dynamically reconfigurable module (DRM) comprising a port, wherein the DRM defines a dynamically reconfigurable region of the programmable integrated circuit that communicates with a module of the logical netlist that is not dynamically reconfigurable via the port; implementing, by a computer system and within the logical netlist, first circuitry for implementation within the DRM and circuitry external to the DRM, wherein the first circuitry connects to the circuitry external to the DRM via the port, and wherein the circuitry external to the DRM is within the module that is not dynamically reconfigurable; locking, by the computer system, routing resources connecting the circuitry external to the DRM to a location associated with a boundary of the DRM for the port; and implementing, by the computer system and within the logical netlist, second circuitry, different from the first circuitry, for implementation within the DRM in place of the first circuitry, wherein the second circuitry couples to the external circuitry through the locked routing resources, and wherein the second circuitry is routed within the DRM to connect to the location associated with the boundary of the DRM for the port.