Patent ID: 8010912

Claim:
A method to design an integrated circuit (IC) mask, comprising: determining a critical dimension of an IC element, wherein the critical dimension is the smallest dimension of a functioning IC element; defining a first design rule based on the critical dimension at a first process feature size, wherein the first design rule governs the possible placement of IC elements to form an integrated circuit, based on die area and/or layout sensitivity; designing, using at least one processor, a full-size mask for an integrated circuit having a first plurality of features including the IC element, comprising: enlarging said first design rule linearly to determine a second design rule, wherein said second design rule has a second process feature size that is larger than said first process feature size; designing said first plurality of features based on said second design rule; and linearly reducing, using at least one processor, a size of said first plurality of features to said first process feature size to create a reduced-size mask for an integrated circuit including the IC element having a second plurality of features.