Patent ID: 8508272

Claim:
A data output circuit, comprising: a delay locked loop configured to output a first internal clock, which is delay-locked and duty ratio-corrected, and output a correction enable signal when the operation of correcting the duty ratio for the first internal clock is completed; a duty ratio correction block configured to correct the duty ratio of the delay locked loop output clock signal by using a duty ratio detection signal in response to the correction enable signal, and output the corrected first internal clock as an output clock; and an output unit configured to generate the duty ratio detection signal by detecting a duty ratio of the output clock, and output a data strobe signal in response to the output clock, wherein the duty ratio correction block comprises: a duty ratio control unit configured to be enabled by the correction enable signal and generate a duty ratio correction code corresponding to the duty ratio detection signal: and a duty ratio correction unit configured to output the output clock by correcting the duty ratio of the first internal clock in response to the duty ratio correction code.