Patent ID: 7933148

Claim:
An apparatus, comprising: a memory cell coupled to a bit line and configured to hold data, wherein the data includes first data or second data; a first transistor having at least a base, wherein the first transistor is configured to read the data by amplifying a current corresponding to the data that appears on the bit line if the data is read; and a second transistor having at least a first terminal, a second terminal, a third terminal, and a channel between the second and third terminals, wherein the second transistor is configured to feed different quantities of currents to the base of the first transistor through the channel, in response to reading the first data or the second data, by changing a potential difference between a first terminal of the second transistor and either a second terminal or a third terminal of the second transistor; wherein the first transistor has a collector coupled to a first end of a third transistor, and wherein a second end of the third transistor is coupled to a sense amplifier.