Patent ID: 7403033

Claim:
A MOS driver circuit comprising: a first MOS transistor configured to receive a controlled voltage at a first input terminal thereof; and a second MOS transistor coupled to said first MOS transistor and configured to receive a differential voltage at a second input terminal thereof, wherein said second MOS transistor is configured to have an increased output impedance when output impedance of said first MOS transistor decreases, and vice versa; a signal adder circuit coupled to said first and said second MOS transistors, wherein a first output of said signal adder circuit is coupled to said second input terminal to provide said differential voltage to said second MOS transistor, and wherein a first output terminal of said first MOS transistor is coupled to a first input of said signal adder circuit to provide a first input voltage thereto; a scaled replica of said MOS driver circuit having a second output coupled to a second input of said signal adder circuit to provide a second input voltage thereto; and a linearizing resistor coupled in series with said first output terminal of said first MOS transistor and a second output terminal of said second MOS transistor.