Patent ID: 8150360

Claim:
An integrated circuit, comprising: a direct conversion receiver including: a front end; a mixer coupled to the front end; a back end coupled to the mixer, the back end comprising at least one baseband amplifier, each baseband amplifier having a plurality of baseband gain settings; and a DC offset correction system configured for: while at least a portion of the front end is disabled, operating the DC offset correction system in a closed loop configuration to determine a plurality of initial first offset data corresponding to each gain setting of the at least one baseband amplifier, while the front end is enabled, operating, in an RF controlled environment, the DC offset correction system in a closed loop configuration to determine a plurality of initial second offset data corresponding to each gain setting of the at least one baseband amplifier, while at least a portion of the front end is disabled, again operating the DC offset correction system in a closed loop configuration to determine a plurality of subsequent first offset data corresponding to each gain setting of the at least one baseband amplifier, from the plurality of initial first offset data, the plurality of initial second offset data and the plurality of subsequent first offset data, calculating a plurality of subsequent second offset data corresponding to each gain setting of the at least one baseband amplifier, and while the front end is enabled, operating the DC offset correction system in an open loop configuration using one subsequent second offset data of the plurality of subsequent second offset data, to reduce DC offset in the direct conversion receiver.