Patent ID: 8078847

Claim:
A method for performing parallel operations in a computer system when one or more memory hazards may be present, comprising: receiving instructions for detecting conflict between memory addresses in vectors when memory operations are performed in parallel using at least a portion of the vectors, and tracking positions in at least one of the vectors of any detected conflict between the memory addresses, wherein the instructions are inserted in program code prior to runtime, and wherein the conflict between memory addresses includes a conflict that is data-dependent and therefore cannot be detected until after the memory addresses have been resolved at runtime; and executing the instructions for detecting the conflict between the memory addresses and tracking the positions, wherein executing the instructions causes a processor to detect the conflict between the memory addresses and to track the positions, and wherein while executing the instructions, the processor generates one or more stop indicators based on the tracked positions in the at least one of the vectors, wherein the one or more stop indicators indicate positions to break the at least one of the vectors into sub-vectors to ensure correct program behavior when the memory operations are performed in parallel.