Patent ID: 7309915

Claim:
A semiconductor device comprising: a semiconductor chip; a plurality of conductive patterns formed on a top surface of the semiconductor chip, each of the plurality of conductive patterns includes a first connection area and a second connection area; a protective film which covers the top surface of the semiconductor chip and the conductive patterns, wherein each of the first connection areas is exposed from respective first openings formed in the protective film, and each of the second connection areas is exposed from respective second openings formed in the protective film; and a plurality of bumps formed on each of the second connection areas, wherein each of the first connection areas has a configuration suitable for a wire connection, and wherein at least one of the plurality of conductive patterns also includes a third connection area exposed from a third opening in the protective film so that the second and third connection areas of the at least one of the plurality of conductive patterns are formed to one first connection area, and a bump is formed on the third connection area.