Patent ID: 7903159

Claim:
Arrangement for converting analog pixel values from an array of pixels to a digital video signal, said array comprising a plurality of columns and at least one row, each column having at least one pixel therein, and each column providing a respective pixel value; the arrangement comprising a source of clock signals; a source of counts of up to N bits, provided in a predetermined sequence; an N-bit counter having a clock input coupled to said source of clock signals, and a count input; means for applying said counts to the count input of said N-bit counter; an N-bit DAC connected to said counter and having a ramp output providing a level corresponding to a count existing on said counter; a plurality of digital counter/latch elements each associated with a respective one of said columns and each also coupled to said source of clock signals; a plurality of comparators each associated with a respective one of said columns, and having one input connected to receive the respective column pixel value, another input connected to the ramp output of said N-bit counter, and a comparator output connected to a gating terminal of the respective digital counter/latch element; a video readout bus; and means selectively transferring contents of said digital counter/latch elements to said video output bus to produce said digital video signal; wherein each said digital counter/latch element includes a ripple counter; wherein said ripple counter is adapted to be configured to count in one direction during black level digitization, then complement the resulting count to obtain a two's complement thereof, and then in said one direction during video-level digitization, thereby creating a digital value that corresponds to the difference between the black level and the video level for each said pixel resulting from two's complement arithmetic.