Patent ID: 8420451

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a wiring substrate having an upper surface, a plurality of bonding electrodes formed on the upper surface, a lower surface opposite to the upper surface, a plurality of holes each formed between the upper surface and the lower surface, a plurality of hole wirings formed inside of the holes, respectively, a plurality of land portions formed on the lower surface and electrically connected with the bonding electrodes via the hole wirings, respectively, a line formed in an area surrounded by the holes in a plan view, a plurality of first lead-out wirings connected with the hole wirings, respectively, and a plating layer formed on each of the land portions, the first lead-out wirings being extended from the hole wirings toward the line, respectively; (b) after the step (a), mounting a semiconductor chip, having a plurality of pads, over the upper surface of the wiring substrate; (c) after the step (b), electrically connecting the pads of the semiconductor chip with the bonding electrodes of the wiring substrate via a plurality of conductive materials, respectively; (d) after the step (c), sealing the semiconductor chip with resin, wherein a shape in the plan view of the line is formed in a circular pattern; and wherein after forming the plating layer, and before the step (b), the first lead-out wirings are electrically separated from each other by removing a part of each of the first lead-out wirings.