Patent ID: 7151698

Claim:
A read circuit for reading a resistive memory cell, said circuit comprising: an access transistor for causing a current to pass through said memory cell to a digit line during a read operation; a first capacitor coupled to said digit line for charging up a voltage on said digit line in response to said current; a clocked comparator having a first input coupled to said digit line and a second input for receiving a reference voltage, said comparator making a comparison of voltage levels at said first and second inputs in response to a first state of a first clock signal and providing a first output state if said digit line voltage is greater than said reference voltage and a second output state if said reference voltage is greater than said digit line voltage; a second capacitor; a first switch element responsive to said first state of said comparator for coupling said second capacitor to said digit line to reduce the voltage on said digit line and being responsive to said second state of said comparator for uncoupling said second capacitor from said digit line; and a second switch element for operating at a time when said second capacitor is not connected to said digit line for discharging said second capacitor.