Patent ID: 7220629

Claim:
A method of manufacturing an integrated circuit (IC) on a semiconductor die, the method comprising: locating a control circuit in a first area of the semiconductor die, the control circuit having a length that extends along a first side and a width that extends along a second side; locating a first output field-effect transistors (FETs) adjacent the second side of the control circuit, the first output FET having a width substantially equal to the width of the control circuit; locating a second output FET adjacent the first side of the control circuit, the second output FET having a length substantially equal to the length of the control circuit plus a length of the first output FET, the length of the second output FET being at least 20% longer than the length of the control circuit; coupling the control circuit to at least one of the first or second output FETs; and wherein the control circuit, first output FET, and second output FET are sized such that the semiconductor die has an aspect ratio within a range of 0.5 to 2.0.