Patent ID: 7138834

Claim:
A method of providing symmetric differential logic operations comprising: receiving, at a first differential logic unit, first and second differential logic signals on first and second pairs of differential inputs, respectively; performing, by the first differential logic unit, a logical operation on the first and second logic signals; producing, by the first differential logic unit, first differential output signals on a first pair of differential outputs, wherein a first circuit configuration is associated with the first pair of differential inputs and a second circuit configuration, different than the first circuit configuration, is associated with the second pair of differential inputs; receiving, at a second differential logic unit, the second differential logic signals on a third pair of differential inputs coupled to the second pair of inputs on the first logic unit; receiving, at the second differential logic unit, the first differential logic signals on a fourth pair of differential inputs coupled to the first pair of signals on the first logic unit; performing, by the second differential logic unit, the logical operation on the first and second logic signals; and producing, by the second differential logic unit, second differential output signals on a second pair of differential outputs coupled to the first pair of differential outputs, wherein the first circuit configuration is associated with the third pair of differential inputs and the second circuit configuration is associated with the fourth pair of differential inputs.