Patent ID: 6933560

Claim:
A power device comprising: a semiconductor substrate having a first conductivity type; a burying layer having a high concentration of a second conductivity type arranged deep in the semiconductor substrate; a well having a low concentration of a second conductivity type formed on the burying layer of the semiconductor substrate; a body region having a first conductivity type formed in a predetermined portion in the well having a low concentration of a second conductivity type; first and second channel stop regions having a low concentration of a second conductivity type, the first channel stop region being formed in a predetermined portion of the body region and the second channel stop region being formed on at least one side of the body region having a first conductivity type; a gate electrode including a gate insulating layer, formed on a space between the first and second channel stop regions; source and drain regions having a high concentration of a second conductivity type formed in the first and second channel stop regions on both sides of the gate electrode; and a body contact region formed in the source region; wherein only the body region having a first conductivity type exists between the first and second channel stop regions, and a channel is formed between the first and second channel stop regions such that a uniform concentration can be obtained in a channel region.