Patent ID: 8748249

Claim:
A method of manufacturing a vertical structure non-volatile memory device, the method comprising: forming a first sacrificial layer on a substrate; alternately stacking insulating layers and second sacrificial layers having different etch selectivities with respect to the first sacrificial layer, on the first sacrificial layer; forming a first middle opening for exposing the first sacrificial layer through the second sacrificial layers and the insulating layers; forming a first opening having sidewalls for exposing a first portion of the substrate, by etching the first exposed sacrificial layer; forming a gate dielectric layer on sidewalls and a bottom surface of the first opening; forming a channel layer that is electrically connected to the substrate, on the gate dielectric layer; forming a second opening to be separated from the first opening, the second opening exposing a second portion of the substrate through the insulating layers and the first sacrificial layer; removing the second sacrificial layers exposed through the second opening; removing the first sacrificial layer exposed through the second opening; and filling a conductive material layer in a space formed by removing the first sacrificial layer and the second sacrificial layers.