Patent ID: 8347728

Claim:
An integrated circuit comprising: a stack of wafer layers, each of said wafer layers being separately formed and then stacked to form said stack; a plurality of through silicon vias, each of said through silicon vias extending through a subject wafer layer and containing a conductive material to provide an electrical connection with an adjacent wafer layer within said stack; and at least one strain sensor disposed within one of said wafer layers proximal to a through silicon via, said strain sensor generating a strain signal indicative of mechanical strain associated with said through silicon via within said one of said wafer layers, wherein said through silicon via is surrounded by a plurality of strain sensors disposed such that, independently of a direction of said mechanical strain, at least one of said plurality of strain sensors generates a strain signal indicative of said mechanical strain, wherein said through silicon via is surrounded by two pairs of strain sensors, each pair of strain sensors having one sensor one either side of a point at which said through silicon via intersects said one of said wafer layers.