Patent ID: 8274421

Claim:
A converter circuit for digitizing the magnitude of a first parameter, which can be inferred by applying to the first parameter a second parameter having a nominal second magnitude and digitizing the magnitude of a resulting third parameter, comprising: a parameter-applying circuit which applies said second parameter having said second magnitude to said first parameter, said converter circuit arranged such that the value of said first parameter can result in the actual value of said second parameter differing from said nominal value, which results in an error being incurred when the digitized value of the third magnitude is used to infer a digitized value of the magnitude of said first parameter, said parameter-applying circuit having an associated bias point with which the actual magnitude of said second parameter also varies; and a sequential-trial analog-to-digital converter (ADC), said converter circuit arranged to adjust the bias point of the parameter-applying circuit with each successive trial and said ADC arranged to perform sequential comparisons between said third magnitude and respective decision thresholds which are different for each of said comparisons, such that there is no error in the actual magnitude of the second parameter when the third magnitude is equal to the decision threshold for a particular trial, and therefore a digitized value of the first parameter can be inferred from the digitized value of the third parameter without incurring any error.