Patent ID: 8030204

Claim:
A method of manufacturing a semiconductor device, comprising: forming an insulation layer on a substrate including various conductive structures, and planarizing the insulation layer; partially removing portions of the insulation layer to form at least one opening in the insulation layer, the substrate being partially exposed through the at least one opening; forming a barrier layer on a sidewall and bottom of the at least one opening, the barrier layer including a residual metal layer formed on the bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer formed on the residual metal layer and an upper sidewall of the at least one opening; and forming a metal plug in the at least one opening by filling up the at least one opening with a metal material, wherein forming the barrier layer includes: forming a metal layer on the sidewall and bottom of the at least one opening and on the upper surface of the insulation layer, the metal layer comprising a first conductive metal; forming the residual metal layer on the bottom and the lower portion of the sidewall of the at least one opening by partially removing the metal layer from the upper surface of the insulation layer and the upper portion of the sidewall of the at least one opening; and forming the metal nitride layer on the upper surface of the insulation layer, on the upper portion of the sidewall of the at least one opening, and on a surface of the residual metal layer, the metal nitride layer comprising a second conductive metal, and wherein forming the metal layer includes: providing first reaction gases including the first conductive metal into a process chamber in which the substrate including the insulation layer and the at least one opening is positioned, so that a portion of the first reaction gases is chemisorbed onto the sidewall and bottom of the at least one opening and onto the upper surface of the insulation layer; purging non-chemisorbed first reaction gases, which are not chemisorbed onto the sidewall and bottom of the at least one opening and onto the upper surface of the insulation layer, out of the process chamber by providing a purge gas into the process chamber; and depositing the first conductive metal onto the sidewall and bottom of the at least one opening and onto the upper surface of the insulation layer by providing second reaction gases into the process chamber.