Patent ID: 7299386

Claim:
A comparator unit for use in testing and debugging a processor, the comparator unit comprising: an first comparator responsive to a first address signal group and to first control signals, the first comparator determining when one of a plurality selected characteristics are present in the first address signal group; a second comparator responsive to a second address signal group and to second control signals, the second comparator determining when a second of the plurality of selected characteristics is present in the second address signal group; an inter-comparator conductor, the inter-comparator conductor applying an indicia of an identification of the second selected characteristic to the first comparator, the first comparator generating an event signal when the first and the second selected characteristics are present; and a data qualification unit coupled to the first and second comparators, the data qualification unit receiving architecture status signals from the processor, the data qualification unit applying enabling signals to the first and second comparators.