Patent ID: 7369957

Claim:
A method for generating test pulses from a test pattern to test an electronic element operating at a test clock rate, comprising: receiving a binary digit (bit) representing part of said test pattern; receiving a plurality of test pulse setting parameters; transforming said binary digit to a plurality of serial data bits according to said plurality of test pulse setting parameters, said test clock rate and a transmission clock rate; and transmitting said serial data bits to said electronic element at said transmission clock rate, wherein said transmission clock rate is higher than said test clock rate, and said plurality of test pulse setting parameters specify a format of the test pulses, a transition point of the test pulses and a width of a main pulse of the test pulses, said format comprising RZ (return-to-zero), NRZ (non-return-to-zero), RO (return-to-one) or NRO (non-return-to-one).