Patent ID: 7536496

Claim:
A method of transmitting data in an integrated circuit, the method comprising the steps of: creating multiple cores that implement a desired function; creating multiple hubs that simultaneously transmit a plurality of redundant data packets between the cores, the multiple hubs each comprising at least one FIFO, the plurality of redundant data packets each comprising a copy of data to be transferred, and a header; the header comprises a unique identifier, and a means for recording timing information, the timing information comprises the time a data packet is stored in the FIFO; creating a table in an arbiter that contains all valid path routings and timing information for the data packets to travel from a source core to one or more destination cores using one or more of the hubs, the arbiter residing in a location separate from the hubs, the source core being any one of the multiple cores from which the data packet originates and the destination cores being any one or more of the multiple cores to which the data packet is intended to be transferred; transmitting a request from the source core to the arbiter to transmit data from the source core to one or more of the destination cores; selecting, from the table, one or more of the valid path routings for transmitting the data packets from the source core to one or more of the destination cores; sending the selected path routings from the arbiter to the source core; generating the plurality of redundant data packets and populating header information in each of the redundant data packets which corresponds to the selected path routing and the unique identifier; simultaneously transmitting the plurality of redundant data packets according to their selected path routings from the source core to one or more of the hubs or the destination core; recording the unique identifier and the timing information when the data packet is received in the destination core, and sending the unique identifier and the timing information to the arbiter; identifying when a first of the plurality of redundant data packets is received by one or more of the destination cores; flushing each of the FIFOs which are storing or transmitting the redundant data packets via a status/flush signal from the arbiter; and updating the table according to a predetermined prioritization scheme using the timing information provided by the destination cores.