Patent ID: 6876587

Claim:
A semiconductor memory device, comprising: a memory cell array; a decoder unit selecting a word line of the memory cell array; a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line; a second dummy cell array connected to a second dummy bit line and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location; a timing control unit determining timing of activation and deactivation of an internal control signal, wherein the timing control unit determines the timing of activation of the internal control signal based on a first signal passing the first dummy bit line through a corresponding dummy cell of the first dummy cell array, and determines the timing of deactivation of the internal control signal based on a second signal passing the second dummy bit line through a corresponding dummy cell of the second dummy cell array.