Patent ID: 7459374

Claim:
A method for manufacturing a semiconductor heterostructure, which comprises: manufacturing a donor wafer by providing a first substrate with a first in-plane lattice parameter, providing on the first substrate an at least spatially graded buffer layer having on top in a relaxed state a second in-plane lattice parameter, and forming on the graded buffer layer an ungraded layer of a semiconductor material which is a strained smoothing layer of a semiconductor material having in a relaxed state a third in-plane lattice parameter which has a value between that of the first and second lattice parameters, forming on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface of the top layer of the donor wafer, wherein, when present, the superficial layer has a thickness that is equal to or smaller than 10 nanometers, and manufacturing a handle wafer by providing a second substrate, forming on the second substrate an insulator layer, and bonding the donor wafer with the handle wafer; wherein the handle wafer is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer that is present on the top surface of the top layer of the donor wafer.