Patent ID: 7189617

Claim:
A manufacturing method for a recessed channel array transistor, comprising: providing a semiconductor substrate of a first conductivity type having isolation trenches adjoining a forming area for the recessed channel array transistor at least in a first direction which is perpendicular to a current flow direction of the recessed channel array transistor, the isolation trenches being filled with an isolation material; forming a sacrificial layer on the surface of the semiconductor substrate; providing a sacrificial layer opening extending in the first direction and exposing at least the substrate in a part of the forming area; etching a trench in the substrate using the sacrificial layer opening as a mask opening, the trench extending in the first direction at least between the second isolation trenches; etching the isolation trenches for broadening the trench in the first direction and for providing an underetching region in the isolation trenches adjoining the substrate and extending below a bottom of the trench; forming a gate dielectric on the substrate in the trench; providing a gate electrode in the trench on the gate dielectric which extends to a same upper surface as the sacrificial layer; removing the sacrificial layer; forming self-adjusting first isolating spacers along the gate electrode on the substrate; and forming source and drain regions by introducing impurities of a second conductivity type into the exposed part of the substrate in the forming area using the first spacers as a mask.