Patent ID: 8132144

Claim:
A method for providing clock gating for a circuit, comprising, in at least one computer: receiving the circuit, wherein the circuit includes a plurality of clocked memory elements; identifying a feedback path from an output of a clocked memory element to an input of the clocked memory element, wherein the feedback path passes through intervening combinational logic, but does not pass through other clocked memory elements in the circuit; gating a clock signal to the clocked memory element so that the clock signal is disabled when the feedback path causes a value which appears at the output of the clocked memory element to be appear at the input of the clocked memory element; and determining if a data input of a downstream clocked memory element is coupled to outputs of two or more upstream clock-gated memory elements by passing through intervening combinational logic but not passing through other clocked memory elements in the circuit; and if the two or more upstream clocked memo elements are clock-gated by one or more signals, gating a clock signal to the downstream clocked memory element so that the clock signal to the downstream clocked memory element is enabled when any of the clock signals to the upstream memory elements are active.