Patent ID: 6927139

Claim:
A semiconductor memory comprising a memory cell matrix including a plurality of cell columns arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors serially arranged along a column-direction, the memory cell matrix comprising: a plurality of device isolation films running along the column-direction, arranged alternatively between the cell columns; a plurality of first conductive layers having top surfaces lower than a level of top surfaces of the device isolation films, arranged along the row and column-directions, a group of the first conductive layers arranged along the column-direction is assigned to a corresponding cell column, adjacent groups of the first conductive layers assigned to adjacent cell columns are isolated from each other by the device isolation film disposed between the adjacent groups; a plurality of inter-electrode dielectrics arranged selectively and respectively on corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and a plurality of second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.