Patent ID: 7535768

Claim:
A method of controlling a copy-back operation of a flash memory device including a plurality of Multi-Level Cells (MLCs) connected to bit lines and word lines, the method comprising the steps of: initializing an upper bit register in response to a reset control signal and initializing a lower bit register in response to a first lower read control signal; reading upper bit data from a source MLC of the plurality of MLCs by applying a first read voltage to a word line to which the source MLC is connected, and storing first upper sensing data in the upper bit register based on the read upper bit data; reading lower bit data from a target MLC of the plurality of MLCs by applying a second read voltage to a word line to which the target MLC is connected, and storing first lower program prohibit data in the lower bit register based on the read lower bit data and the first upper sensing data; generating program data based on the first upper sensing data and the first lower program prohibit data and storing the program data in the upper bit register; determining whether the program data will be modified; if it is determined that the program data will not be modified, generating first last program data based on the program data and the first lower program prohibit data, and firstly programming the first last program data into the target MLC; if it is determined that the program data will be modified, storing second lower program prohibit data in the lower bit register and storing modified program data in the upper bit register; and generating second last program data based on the modified program data and the second lower program prohibit data, and secondly programming the second last program data in the target MLC.