Patent ID: 7616039

Claim:
A memory reset apparatus, comprising: a first inverse circuit, for receiving a control signal by a north bridge at an input end, inversing the control signal, and generating a first signal at an output end, wherein the control signal controls reset of a plurality of memories; a logic circuit, having a first input end, a second input end, and an output end, wherein the first input end the second input end of the logic circuit respectively receive the first signal and an indicating signal, so as to perform a logical operation of the first signal and the indicating signal, and generate a second signal at the output end of the logic circuit, wherein the indicating signal indicates each component of a computer system is completely powered on; and a plurality of second inverse circuits, respectively coupled between the logic circuit and the memories, wherein input ends of the second inverse circuits receive the second signal, and inverse the second signal, so as to respectively generate a plurality of reset signals to the memories at output ends of the second inverse circuits, thereby resetting the memories.