Patent ID: 7665052

Claim:
A computer-implemented method for performing timing aware of a circuit design for redundant via insertion, the method comprising: generating by a processor a layout with inserted redundant vias for the circuit design, while a timing of the circuit design is preserved, comprising: evaluating clock nets of the circuit design for redundant via insertion prior to evaluating signal nets of the circuit design for redundant via insertion wherein the signal nets comprise critical signal nets and non-critical signal nets; analyzing the timing of the circuit design based at least in part upon the act of evaluating the clock nets for redundant via insertion; selecting a set of critical signal nets for redundant via insertion; inserting redundant vias for the set of critical signal nets; analyzing the timing of the circuit design for the set of critical signal nets with the inserted redundant vias; and inserting redundant vias for the non-critical signal nets with no detailed timing analysis; and storing the layout in a volatile or non-volatile computer readable medium or displaying the layout on a display device.