Patent ID: 6930918

Claim:
A semiconductor memory array comprising: a plurality of memory cells arranged in a matrix of rows and columns, the plurality of memory cells include a first memory cell and a second memory cell, wherein the first and second memory cells each include at least a transistor to constitute the memory cell and wherein the transistor includes: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate spaced apart from, and capacitively coupled to, the body region; wherein each memory cell includes: a first data state representative of a first charge in the body region; and a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and wherein the drain region of the transistor of the first memory cell and the drain region of the transistor of the second memory cell are the same region.