Patent ID: 7979765

Claim:
A generation device for generating a test vector for a logic circuit by assigning a logic value to each of a plurality of unspecified bits (X-bits) included in a test cube, the logic circuit being full-scan sequential circuit, the generation device comprising: selection unit that selects, among the plurality of X-bits, a target X-bit, which is an X-bit to which a logic value is to be assigned, where the selection is based on a selection criterion in which the X-bit with the largest X-score is selected wherein the X-score is the degree of spread of signal value transition in the logic circuit; capture transition metric calculation unit that calculates capture transition metric (PWT(v)) for a test cube (v) including at least one X-bit, with outputs of all of logic elements in the logic circuit, using probabilistic weighted formula shown below; and logic value assignment unit that assigns, to the selected target X-bit (b), a logic value which causes a smaller capture transition metric, by applying the capture transition metric calculation unit to a first test cube obtained by assigning a logic value 0 to the selected target X-bit and to a second test cube obtained by assigning a logic value 1 to the target X-bit, and by comparing a capture transition metric caused by a first test cube (PWT (v: b=0)) and a capture transition metric caused by a second test cube (PWT (v: b=1)), wherein logic values are assigned to target X-bits based on calculation results by the capture transition metric calculation unit until logic values are assigned to all of the plurality of X-bits, and P ⁢ ⁢ W ⁢ ⁢ T ⁡ ( v ) = ∑ i = 1 n ⁢ ( w i × p i ) where n is number of all nodes of the logic circuit, wi denotes a factor related to node i for calculating a capture transition metric, and pi is transition probability which is probability that a transition (0 to 1 or 1 to 0) occurs at an output of node i.