Patent ID: 8279704

Claim:
A method for decoding a memory array, said method comprising: providing a first decoder circuit with an operating voltage of a first magnitude until all decoded outputs thereof are stable and a first voltage differential is established between a selected and unselected decoded outputs thereof, each decoded output being coupled to a respective plurality of array line driver circuits; and providing a first inactive voltage level on each bus line of a source select bus, said source select bus coupled to each of the respective pluralities of array line driver circuits, each respective array line driver circuit of a given plurality of array line driver circuits for coupling a respective bus line of the source select bus to a respective array line of a first type responsive to a decoded output of the first decoder circuit coupled to the given plurality of array line driver circuits; then increasing the operating voltage of the first decoder circuit to a second magnitude larger than the first magnitude, to thereby increase the differential voltage between selected and unselected decoded outputs to a second differential voltage greater than the first differential voltage; then pulsing a first bus line of the source select bus to a first active voltage level then back to the first inactive voltage level, to thereby pulse a first array line of the first type corresponding to the selected decoded output of the first decoder circuit; then decreasing the operating voltage of the first decoder to the first magnitude before allowing any decoded outputs thereof to change states.