Patent ID: 8749681

Claim:
A semiconductor memory, comprising: a row decoder; a plurality of memory cells, each memory cell comprising: a first transistor selectable by a WR line controlled by the row decoder; a second transistor having a gate coupled to receive an input voltage signal from a vertical input signal line via the first transistor when the first transistor is selected; and a capacitor having a first terminal connected to the gate and a second terminal connected to an RD line controlled by the row decoder, the RD line being driven to couple the gate through the capacitor to turn on the second transistor during a read of said each memory cell so that the second transistor outputs an output signal; a digital-to-analog converter that converts a multi-bit input datum into an analog input signal to be stored into one of the plurality of memory cells at a time; an analog-to-digital that retrieves an analog output signal from one of the plurality of memory cells at a time and converts it to a multi-bit digital output datum; and a reference memory cell, wherein a storage reference signal is stored in the reference memory cell and then subtracted from the analog output signal before the analog output signal is converted to digital.