Patent ID: 8018071

Claim:
A stacked semiconductor device structure comprising: a wiring substrate including first and second control pins; a first semiconductor device on the wiring substrate, the first semiconductor device including: a first bonding pad array including: a first signal bonding pad disposed on an active surface; a first control pin bonding pad electrically coupled to the first control pin and disposed on the active surface; a first stacking bonding pad disposed on the active surface between the first signal bonding pad and the first control pin bonding pad and electrically coupled to the second control pin; and a first electrical die sorting bonding pad; a second semiconductor device on the first semiconductor device, the second semiconductor device including: a second bonding pad array including: a second signal bonding pad; a second control pin bonding pad; a second stacking bonding pad between the second signal bonding pad and the second control pin bonding pad and electrically coupled to and aligned with the first stacking bonding pad; a connection line that electrically couples the second stacking bonding pad and the second control pin bonding pad; and a second electrical die sorting bonding pad spaced apart from the first electrical die sorting pad, spaced apart from the connection line, and spaced apart from the first and second control pins.