Patent ID: 8542693

Claim:
A processor for managing packet-based communications, comprising: an addressable memory for storing packet descriptors and data packets, each data packet associated with one of the packet descriptors, the addressable memory comprising: a first memory resource; and a second memory resource, the second memory resource having slower access performance relative to the processor than the first memory resource; and a queue manager coupled to the first memory resource and second memory resource for localizing linking, comprising: queue manager logic circuitry; linking memory, coupled to the queue manager and having a plurality of entries, each entry mapped to one of a plurality of packet descriptor index values, each packet descriptor index value mapped to a memory address in the addressable memory, and each entry of the linking memory having a field for storing a next packet descriptor index value; and a free packet descriptor queue control register; wherein the queue manager keeps base queue information in the first memory resource and adds a packet descriptor to a free packet descriptor queue associated with a free packet descriptor queue control register by performing a sequence of operations comprising: receiving a return request including a pointer to the location in memory of the packet descriptor to be added; determining whether the packet descriptor is located in the first memory resource or the second memory resource; responsive to the packet descriptor being located in the first memory resource, updating a head packet descriptor index field in the free packet descriptor queue control register to refer to the packet descriptor to be added; and responsive to the packet descriptor being located in the second memory resource, updating a tail packet descriptor index field in the free packet descriptor queue control register to refer to the packet descriptor to be added.