Patent ID: 6990508

Claim:
A programmable logic block in an integrated circuit comprising: a plurality of macrocells comprising logic configured to (i) generate and propagate an inverted carry-input signal and (ii) generate a sum bit; an AND-array comprising at least two product terms per macrocell; an OR-array configured to generate a sum-of-products term for each macrocell in response to said two product terms; and a logic circuit configured to (a) receive (i) said product terms and (ii) the carry-input signal generated by a first macrocell of said plurality of macrocells and (b) generate (i) a block carry-propagate signal, (ii) a block carry-generate signal, and (iii) a block carry-output signal, wherein said logic in said macrocells comprises (i) a carry generator configured to select a first product term or a second product term as said inverted carry-input signal and (ii) a second logic circuit configured to logically combine said inverted carry-input signal and said sum-of-products term to generate said sum bit.