Patent ID: 7971124

Claim:
An apparatus for distinguishing correctable bit errors in memory, the apparatus comprising: a bit error detection module configured to detect a correctable bit error in a data memory, the correctable bit error correctable using error-correcting code (“ECC”); a comparison module configured to compare an error location indicator with a stored error location indicator, the error location indicator comprising an indication of location in the data memory of the correctable bit error, the stored error location indicator corresponding to at least one previously stored error location indicator of a previously detected correctable bit error; a storage module configured to store the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator; and a random bit error counter module configured to increase a random bit error counter in response to the comparison module determining that the error location indicator differs from a stored error location indicator and to not increase the random bit error counter in response to the comparison module determining that the error location indicator matches a stored error location indicator.