Patent ID: 7053667

Claim:
A single-wire digital interface for receiving digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having defined “first” and “second” pulse widths, respectively, comprising: an input node for receiving said stream of pulses; a low-pass filter arranged to produce an output that increases from an initial minimum value at a known rate for the duration of a single pulse received at said input node and returns to said initial minimum value when said single pulse terminates; a comparator which produces an output that toggles from a logic ‘0’ to a logic ‘1’ when said low-pass filter output exceeds a first predetermined threshold; a clock generator arranged to output a clock signal which has an edge having a first polarity when each pulse received at said input node terminates; and a latch which receives said comparator output and said clock generator output at respective inputs and which latches said comparator output upon receipt of a clock edge having said first polarity; said low-pass filter and comparator arranged such that said latch latches a logic ‘1’ when a pulse received at said input node has a pulse width about equal to said “first” pulse width, and such that said latch latches a logic ‘0’ when a pulse received at said input node has a pulse width about equal to said second pulse width.