Patent ID: 8619474

Claim:
A method of operating a memory device having a plurality of memory cells, the method comprising: enabling one or more memory cells to be programmed; biasing a first portion of data lines of a plurality of data lines to a first program inhibit voltage, where the first portion of data lines are coupled to memory cells to be inhibited from programming, and applying a first plurality of programming pulses to the enabled memory cells while biasing the first portion of data lines to the first program inhibit voltage; and biasing a second portion of data lines of the plurality of data lines to a second program inhibit voltage, where the second portion of data lines are coupled to memory cells to be inhibited from programming, and applying a second plurality of programming pulses to the enabled memory cells while biasing the second portion of data lines to the second program inhibit voltage; wherein the second program inhibit voltage is greater than the first program inhibit voltage and where the second plurality of programming pulses are applied following the first plurality of programming pulses; wherein a particular programming pulse of the first plurality of programming pulses has a voltage level greater than a preceding programming pulse of the first plurality of programming pulses; and wherein a particular programming pulse of the second plurality of programming pulses has a voltage level greater than a preceding programming pulse of the second plurality of programming pulses.