Patent ID: 7495488

Claim:
A phase-locked loop (PLL) circuit comprising: a phase/frequency detector (PFD) configured to generate an up signal and a down signal in response to a phase difference or a frequency difference between a reference signal and a feedback signal; a charge pump configured to generate a first voltage signal that is changed in response to the up signal and the down signal; a loop filter configured to filter the first voltage signal to generate an oscillation- control voltage; a control circuit configured to generate a digital control signal in response to the up signal, the down signal, and the oscillation-control voltage, the control circuit comprising a control voltage range detecting circuit configured to set an upper limit voltage and a lower limit voltage in response to a threshold voltage of a metal-oxide semiconductor (MOS) transistor and to compare the oscillation-control voltage with the upper limit voltage and the lower limit voltage to generate a voltage range detecting signal used to enable the digital control signal; a voltage-controlled oscillator (VCO) configured to generate an output signal, a frequency of the output signal being changed in response to the oscillation-control voltage and the digital control signal; and a feedback circuit configured to generate the feedback signal in response to the output signal.