Patent ID: 8114728

Claim:
A method for making an NMOS transistor and a PMOS transistor, comprising: providing a semiconductor substrate containing an NMOS transistor and a PMOS transistor, wherein said NMOS transistor includes: a gate dielectric coupled to said semiconductor substrate; a polysilicon gate electrode coupled to said gate dielectric; extension regions within said semiconductor substrate; source/drain sidewalls coupled to said gate electrode; source/drain regions within said semiconductor substrate; and a pre-metal dielectric layer coupled to said gate electrode, said source/drain sidewalls, and said source/drain regions; further wherein said PMOS transistor includes: a gate dielectric coupled to said semiconductor substrate; a polysilicon gate electrode coupled to said gate dielectric and doped with p-type dopant; source/drain sidewalls coupled to said gate electrode; source/drain regions within said semiconductor substrate, said source/drain regions comprising SiGe; and a pre-metal dielectric layer coupled to said gate electrode, said source/drain sidewalls, and said SiGe source/drain regions; reducing a thickness of said pre-metal dielectric layer to expose said gate electrode of said NMOS transistor and said gate electrode of said PMOS transistor; with said gate electrodes of both said NMOS and PMOS transistors exposed, selectively removing said gate electrode of said NMOS transistor without removing said gate electrode of said PMOS transistor using a wet etch chemistry that is selective to polysilicon doped with the p-type dopant; with said gate electrode of said NMOS transistor removed, depositing an NMOS-metal layer over said semiconductor substrate including between said source/drain sidewalls of said NMOS transistor; depositing a fill-metal layer over said NMOS-metal layer including between said source/drain sidewalls of said NMOS transistor; and reducing a thickness of said NMOS-metal layer and said fill-metal layer to expose said gate electrode of said PMOS transistor and to leave portions of said NMOS-metal layer and said fill-metal layer in replacement for said gate electrode of said NMOS transistor.