Patent ID: 7534675

Claim:
A method of fabricating a field-effect transistor (FET), the method comprising the steps of: providing a substrate having a silicon-on-insulator (SOI) layer; depositing at least one nanowire over the SOI layer; forming a sacrificial gate over the SOI layer so as to cover a portion of the nanowire that forms a channel region; selectively growing an epitaxial semiconductor material from the SOI layer that covers the nanowire and attaches the nanowire to the SOI layer in a source region and in a drain region; removing the sacrificial gate; forming an oxide that divides the SOI layer into at least two electrically isolated sections, one section included in the source region and the other section included in the drain region; forming a gate dielectric layer over the channel region; forming a gate over the channel region separated from the nanowire by the gate dielectric layer; and forming a metal-semiconductor alloy over the source and drain regions.