Patent ID: 7177175

Claim:
A dynamic random access memory cell for storing a first data state and a second data state, the memory cell comprising: an electrically floating body transistor having: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate spaced apart from, and capacitively coupled to, the body region; wherein the electrically floating body transistor includes a first data state representative of a first amount of majority carriers in the body region, and a second data state representative of a second amount of majority carriers in the body region, wherein the first amount of majority carriers is less than the second amount of majority carriers; wherein the first data state is provided by applying a first voltage to the gate, a second voltage to the drain region, a third voltage to the source region such that, in response to the first, second and third voltages, the electrically floating body transistor is off or substantially off; and wherein the second voltage is greater than the first voltage and the absolute value of the difference between the first voltage and the third voltage is less than the absolute value of the threshold voltage of the electrically floating body transistor.