Patent ID: 8811087

Claim:
A nonvolatile memory device, comprising: a memory cell array comprising a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line; a voltage generator that provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation; and a page buffer that senses a level of the bit line after applying a precharge voltage to the bit line in response to a bit line connection signal during the read operation, wherein the read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor, and wherein a voltage level of the bit line connection signal of a selected memory cell located closest to the string selection transistor is set to be higher than a voltage level of the bit line connection signal for a selected memory cell located closest to the ground selection transistor.