Patent ID: 7117404

Claim:
Test circuit for testing a synchronous memory circuit having: (a) a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor in order to produce a high-frequency clock signal for the synchronous memory chip to be tested; (b) a test data generator which produces test data on the basis of data control signals received from the external test unit and outputs them to a data output driver in order to write them to the synchronous memory circuit to be tested, wherein in the test data generator test data patterns are stored which are read out at a frequency of the high-frequency clock signal to produce the test data; (c) a first signal delay circuit for delaying the test data which are output by the test data generator by an adjustable first delay time; (d) a second signal delay circuit for delaying data which are read out of the synchronous memory circuit to be tested and are received by a data input driver in the test circuit by an adjustable second delay time; (e) and having a data comparison circuit which compares the test data produced by the test data generator with the data read out of the memory circuit and, on the basis of the comparison result, outputs an indicator signal to the external test unit which indicates whether the synchronous memory circuit to be tested is operable.