Patent ID: 6928570

Claim:
A system clock synchronization circuit comprising: a first synchronization and timing delay circuit synchronizing an input clock with a system clock and sending out a first signal which is obtained by delaying the synchronized signal by a first delay amount; an input data latching means for latching input data which changes at a first changing point of said input clock, said latching being in synchronization with a second changing point of said input clock; an input enable signal latching means for latching in synchronization with said input clock an input enable signal which is active when said input data is valid and inactive when said input data is invalid; a mask signal generation circuit generating in synchronization with said first signal a mask signal which has a prescribed pulse width; a second synchronization and timing delay circuit synchronizing a signal sent out from said input data latching means with said system clock and sending out a second signal which is obtained by delaying the synchronized signal by a second delay amount; a third synchronization and timing delay circuit synchronizing a signal sent out from said input enable signal latching means with said system clock and sending out a third signal which is obtained by delaying the synchronized signal by a third delay amount; a masking means for taking in said mask signal and said third signal, sending out said third signal when said mask signal is active, and masking said third signal when said mask signal is inactive; a first output latching means for latching in synchronization with said system clock a fourth signal from said masking means and sending out an output enable signal; and a second output latching means for taking in said fourth signal at a write enable terminal and said second signal at a data input terminal, latching in synchronization with said system clock said second signal when said fourth signal is active, and holding and sending out as output data said second signal which is taken immediately before when said fourth signal is inactive.