Patent ID: 8037120

Claim:
A method for performing a comparison operation on a first N-bit vector A[N−1:0] and a second N-bit vector B[N−1:0] in a digital logic circuit, wherein N is a nonzero positive number, comprising: performing, with a bit-wise complement circuit, a bit-wise inversion of B[N−1:0] to obtain ˜B[N−1:0]; obtaining a third N-bit vector by performing, with a bitwise AND circuit, a bit-wise AND operation using the A[N−1:0] and the ˜B[N−1:0] N-bit vectors; obtaining a fourth N-bit vector by performing, with a first bit-wise XOR circuit, a bitwise XOR operation using the A[N−1:0] and the ˜B[N−1:0] N-bit vectors; obtaining a fifth N-bit vector by performing, with a bit-wise XNOR circuit, a bit-wise XNOR operating using the fourth N-bit vector and a one-bit-right-shifted version of the fourth N-bit vector; obtaining a sixth N-bit vector by performing, with a second bit-wise XOR circuit, a bitwise XOR operation using the third N-bit vector and the fifth N-bit vector; and obtaining a 1-bit result by performing, with an N+1 input AND circuit, an AND operation using the sixth N-bit vector and the result of ORing the third N-bit vector, wherein the result is a first value if a difference between the A[N−1:0] and B[N−1:0] vectors is equal to +1 and a second value for other differences therebetween.