Patent ID: 7277989

Claim:
An apparatus for selectively fetching a store instruction during speculative-execution, comprising: an execution mechanism configured to issue instructions for execution in program order during execution of a program in a normal-execution mode; wherein upon encountering a launch condition during an instruction which causes the processor to enter a speculative-execution mode, the execution mechanism is configured to perform a checkpoint and begin execution of instructions in a speculative-execution mode; wherein upon encountering a store instruction during the speculative-execution mode, the execution mechanism is configured to, check an L1 data cache for a cache line containing a target for the store instruction and to check a store buffer for a store to the cache line containing the target for the store instruction; if the cache line containing the target for the store instruction is already present in the L1 data cache or a store to the cache line containing the target for the store instruction is already present in the store buffer, the execution mechanism is configured to suppress generation of a fetch for the cache line containing the target for the store instruction, and otherwise the execution mechanism is configured to generate a fetch for the cache line containing the target for the store instruction.