Patent ID: 7192822

Claim:
A method of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device, the method comprising: providing a semiconductor substrate having a field isolation layer, a first conductivity type well, and a second conductivity type well; forming an insulated first gate electrode on the first conductivity type well, and an insulated second initial gate electrode on the second conductivity type well; forming a first lower interlayer insulating layer exposing a top surface of the first gate electrode on the first conductivity type well, and a second lower interlayer insulating layer exposing a top surface of the second initial gate electrode on the second conductivity type well; implanting first conductivity type impurity ions into the second initial gate electrode to form a second gate electrode; forming a first ion implantation mask pattern over the first gate electrode, and a second ion implantation mask pattern over the second gate electrode; etching the first lower interlayer insulating layer to expose a top surface of the first conductivity type well at both sides of the first gate electrode; implanting second conductivity type impurity ions into the first conductivity type well, using the first ion implantation mask pattern as an ion implantation mask, to form first source and drain regions at both sides of the first gate electrode; etching the second lower interlayer insulating layer, using the second ion implantation mask pattern as an etch mask, to expose a top surface of the second conductivity type well at both sides of the second gate electrode; and implanting first conductivity type impurity ions into the second conductivity type well, using the second ion implantation mask pattern as an ion implantation mask, to form second source and drain regions at both sides of the second gate electrode.