Patent ID: 7420395

Claim:
An output buffer circuit comprising: an output transistor having a source supplied with a first potential selected from a VDD potential and a GND potential, a drain connected to an output terminal, and a gate; a capacitor element having a first terminal connected to the output terminal, and a second terminal; a driving circuit that controls the output transistor by changing a potential of the gate of the output transistor, the driving circuit operates such that the output transistor changes from an OFF-state to an ON-state during a first period and such that the output transistor is in the OFF-state during a second period prior to the first period; a first switch that connects the second terminal of the capacitor element to the gate of the output transistor when it is in an ON-state; and a second switch that supplies a second potential selected from the VDD potential and the GND potential, where the second potential is different from the first potential, to the second terminal of the capacitor element when it is in an ON-state, wherein the first switch is in the ON-state and the second switch is in an OFF-state during the first period, and the first switch is in an OFF-state and the second switch is in the ON-state during the second period.