Patent ID: 8207559

Claim:
A Schottky junction field effect transistor (JFET) structure formed in a semiconductor substrate, the JFET structure comprising: an n-channel region formed in a channel surface portion of the semiconductor substrate, the n-channel region being surrounded by shallow trench isolation dielectric material; a metal silicide gate formed over the n-channel region; p+ guard rings formed in the outer edges of the channel surface portion adjacent the shallow trench isolation dielectric material; an n+ source contact region formed in the semiconductor substrate and spaced-apart from the n-channel region by the shallow trench isolation dielectric material, the n+ source contact region having metal silicide formed thereon; an n+ drain contact region formed in the semiconductor substrate and spaced-apart from the n-channel region by the shallow trench isolation dielectric material, the n+ drain contact region having metal silicide formed thereon; a source contact N+ buried layer (NBL) formed beneath an upper surface of the semiconductor substrate and beneath and spaced-apart from the n+ source contact region; a drain contact N+ buried layer (NBL) formed beneath the upper surface of the semiconductor and beneath a spaced-apart from the n+ drain contact region; an n+ source sinker region formed in the semiconductor substrate to extend from the n+ source contact region to the source contact N+ buried layer; and an n+ drain sinker region formed in the semiconductor substrate to extend from the n+ drain contact region to the drain contact N+ buried layer.