Patent ID: 6990557

Claim:
A cache memory for use in a multithreaded processor, the cache memory comprising a plurality of thread caches, at least a given one of the thread caches comprising: a memory array comprising a plurality of sets of memory locations; and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations, the directory having a plurality of entries each storing multiple ones of the tags; wherein an entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event based at least in part on at least a portion of a thread identifier of the given thread cache, by utilizing one or more least significant bits of the thread identifier to identify a subset of a total number of tags in a given entry of the directory, with the entry selected for eviction being selected as an entry corresponding to a tag in the identified subset of the total number of tags in the given entry of the directory.