Patent ID: 8194492

Claim:
A variable resistance memory device comprising: a memory cell array including a plurality of variable resistance memory cells divided into a first area and a second area; an input/output circuit configured to access the memory cell array; and a control logic configured to control the input/output circuit to access the first area or the second area in response to an external command, wherein the input/output circuit supplies read current to at least one memory cell during a read operation, wherein the first area has higher response speed and shorter data access time than the second area, wherein the control logic is further configured to erase the second area as a first logic state and program selected memory cells of the second area as a second logic state, wherein the variable resistance memory device further comprises a memory interface configured to control the control logic in response to externally applied control signals and a select signal selecting between the first area and the second area, and wherein the control signals include a command, an address, and data.