Patent ID: 7447091

Claim:
A semiconductor memory device comprising: a first amplifier circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors; and a second amplifier circuit for amplifying, to a power-supply voltage amplitude, information read from a memory cell, wherein a gate of said first N-channel MOS transistor and a gate of said second N-channel MOS transistor are connected to a first power-supply potential, a source of said first N-channel MOS transistor is connected to a first input terminal, and a source of said second N-channel MOS transistor is connected to a second input terminal, a gate of said first P-channel MOS transistor and a gate of said second P-channel MOS transistor are connected to a ground potential, a source of said first P-channel MOS transistor and a source of said second P-channel MOS transistor are connected to said first power-supply potential, a drain of said first N-channel MOS transistor is connected to a drain of said first P-channel MOS transistor, and a drain of said second N-channel MOS transistor is connected to a drain of said second N-channel MOS transistor, and said first and second N-channel MOS transistors receive inputs of the information read from said memory cell prior to said first and second P-channel MOS transistors.