Patent ID: 7684424

Claim:
A system for memory interleaving in a high-speed switching environment, the system comprising: a plurality of memory units; an interconnection network coupling the plurality of memory units to a plurality of port modules; a first port module of the plurality of port modules, the first port module operable to receive a packet from a first component and to write the packet to one or more of the plurality of memory units according to a first schedule, the first schedule allowing a first number of write operations over a period of time; and a second port module of the plurality of port modules, the second port module operable to read the packet from the one or more memory units according to a second schedule, the second schedule allowing a second number of read operations over the period of time, the second number being greater than the first number, the second port module further operable to send the packet to a second component; wherein the second port module is operable to read a first portion of the packet before the first port module has written a second portion of the packet.