Patent ID: 7243313

Claim:
A method of transforming a first topology to a reduced topology, said first topology representing an abstraction of one or more objects, said first topology further comprising a plurality of inter-connected elements, said method comprising: identifying one or more elements, wherein the identifying comprises generating a minimum spanning tree (MST) of the first topology and identifying one or more small-valued circuit elements in the MST; analyzing an effect of reducing one or more of said identified elements on topological and physical characteristics of said one or more objects, wherein the analyzing comprises analyzing a variation of one or more delay measurements after eliminating one or more of said small-valued circuit elements; generating a second topology reflecting a reduction of one or more identified elements in response to the effect of reducing one or more of said identified elements has negligible effect on the topological and physical characteristics of said one or more objects, wherein the reducing one or more said identified elements comprises eliminating one or more of said small-valued circuit elements in the MST.