Patent ID: 8669609

Claim:
A method for forming a semiconductor device comprising: forming a first dielectric layer over a semiconductor layer; forming a first conductive gate layer over the first dielectric layer; forming a second dielectric layer over the first conductive gate layer; forming a third dielectric layer over the second dielectric layer, the third dielectric layer having a different etch characteristic than the second dielectric layer; performing a first etch to form a first sidewall of the first conductive gate layer, wherein the first etch exposes a portion of the semiconductor layer; performing a second etch to remove a portion of the first dielectric layer between the semiconductor layer and the first conductive gate layer, resulting in a first undercut between the semiconductor layer and the first conductive gate layer, and to remove a portion of the second dielectric layer between the third dielectric layer and the first conductive gate layer, resulting in a second undercut between the third dielectric layer and the first conductive gate layer, wherein the first undercut exposes a bottom corner of the first conductive gate layer and the second undercut exposes a top corner of the first conductive gate layer; growing an oxide layer on the first sidewall of the first conductive gate layer, around the top corner and around the bottom corner of the first conductive gate layer, and over the exposed portion of the semiconductor layer, wherein the growing the oxide layer results in rounding each of the top corner and the bottom corner of the first conductive gate layer; removing the oxide layer; forming a charge storage layer over the third dielectric layer, along the first sidewall of the first conductive gate layer, and over the semiconductor layer; forming a second conductive gate layer over the charge storage layer; and patterning the second conductive gate layer to form a first sidewall of the second conductive gate layer over the first conductive gate layer and a second sidewall of the second conductive gate layer over the semiconductor layer, wherein the second conductive gate layer overlaps the first sidewall of the first conductive gate layer and overlaps a top portion of the first conductive gate layer.