Patent ID: 7528426

Claim:
A lateral junction field-effect transistor comprising: a first semiconductor layer ( 2 ) placed on a semiconductor substrate ( 1 ) and containing impurities of a first conductivity type (p); a second semiconductor layer ( 3 ) placed on said first semiconductor layer ( 2 ) and containing impurities of a second conductivity type (n) with a higher impurity concentration than that of said first semiconductor layer ( 2 ); a third semiconductor layer ( 6 ) placed on said second semiconductor layer ( 3 ) and containing impurities of the first conductivity type (p); source and drain region layers ( 5 , 9 ) spaced from each other by a predetermined distance in said third semiconductor layer ( 6 ) and containing impurities of the second conductivity type (n) with a higher impurity concentration than that of said second semiconductor layer ( 3 ); a gate region layer ( 7 ) provided between said source and drain region layers ( 5 , 9 ) in said third semiconductor layer ( 6 ), having a bottom surface of said gate region layer ( 7 ) extending into said second semiconductor layer ( 3 ), and said gate region layer ( 7 ) containing impurities of the first conductivity type (p) with a higher impurity concentration than that of said second semiconductor layer ( 3 ); wherein a first portion of said third semiconductor layer ( 6 ) is between and in contact with said gate region layer ( 7 ) and said source region layer ( 5 ), and wherein a second portion of said third semiconductor layer ( 6 ) is between and in contact with said gate region layer ( 7 ) and said drain region layer ( 9 ); and further comprising a side layer ( 4 ) that contains impurities of the first conductivity type (p) and that is disposed contacting a lateral side of said source region layer opposite said first portion of said third semiconductor layer and that has a thickness spanning thicknesses of said third and second semiconductor layers and penetrating partially into said first semiconductor layer.