Patent ID: 8253167

Claim:
An integrated circuit structure comprising: a substrate; a first plurality of III-V semiconductor layers comprising: a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer, the first top barrier having a first top surface; a first field-effect transistor (FET) comprising a first channel region, wherein the first channel region comprises a portion of the first channel layer; a second plurality of III-V semiconductor layers over the first plurality of III-V semiconductor layers and comprising: a second bottom barrier having a second top surface, the second top surface spaced from the first top surface in a direction orthogonal to a major surface of the substrate; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer; and a second FET comprising a second channel region, wherein the second channel region comprises a portion of the second channel layer.