Patent ID: 7418617

Claim:
An adjusting circuit for adjusting timings of memory signals of a computer system, the adjusting circuit comprising: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit connected to the clock generator for receiving the reference signals, wherein the multiplexing unit selects a first reference signal according to a selecting signal; a control module for generating a signal being a data indication signal (DQS) or a data signal (DQ); an adjusting unit connected to the control module and the multiplexing unit for receiving the signal from the control module and delaying to output the signal according to the first reference signal selected by the multiplexing unit; a comparing module connected to the control module for comparing the delayed signal to see if the delayed signal is correct; and a scanning module connected to the control module for reselecting the first reference signal from the reference signals if the comparing result is not correct.