Patent ID: 7299323

Claim:
A memory controller, wherein the memory controller is connected to a memory, wherein the memory controller is connected to intellectual property (IP) blocks and a microprocessor via a system bus, and wherein, in response to one of read, write, and modify request signals received from the one of the IP blocks or the microprocessor and an address signal, the memory controller reads a data signal from the memory, writes a write data signal to the memory, or modifies the data signal read from the memory and writes the modified data signal to the memory, wherein the memory controller comprises: a controller, in response to the read, write, and modify request signals, outputting first to ninth control signals, and outputting a read command signal or a write command signal together with a chip selection signal and a memory clock signal; an address generation unit, in response to the first control signal, storing the address signal received via the system bus, and generating a read address signal or a write address signal based on the stored address signal; an address buffer, in response to the second control signal, storing the read address signal or the write address signal, and outputting the stored read address signal or write address signal to the memory; an input buffer, in response to the third control signal, storing a read data signal received from the memory, and outputting the stored read data signal; and a data modification unit being enabled or disabled in response to the fourth control signal, wherein, when the data modification unit is enabled, in response to the fifth control signal, the data modification unit performs an arithmetic operation on the read data signal and an arithmetic data signal, and outputs the result of the arithmetic operation as a modify data signal.