Patent ID: 7842581

Claim:
A method of fabricating a capacitor comprising: forming an interlayer insulating layer on a semiconductor substrate; forming a contact plug that penetrates the interlayer insulating layer; forming a metal layer on the contact plug by performing a deposition cycle that includes at least one cycle of supplying a first metal source, and then purging, and then supplying an oxygen source, and then purging, and then plasma processing in a reduction gas ambient, and then purging; removing a portion of the metal layer to form a lower electrode; forming a dielectric film on a surface of the lower electrode; forming an upper electrode on an upper surface of the dielectric film; and forming a metal interconnect in direct contact with the upper electrode; wherein the deposition cycle further includes at least one cycle of supplying a second metal source, purging, supplying the oxygen source, and purging, and wherein the first metal source and the second metal source consist of the same material, wherein forming the upper electrode comprises: forming a third metal layer on an upper surface of the dielectric film by repeating a cycle of supplying a metal source, and then purging, and then supplying the oxygen source, and then purging, wherein the cycle of supplying the metal source, and then purging, and then supplying the oxygen source, and then purging that is repeated multiple times to form the third metal layer on the upper surface of the dielectric film does not include any plasma processing in a reduction gas ambient purging; and then forming a fourth metal layer on an upper surface of the third metal layer by repeating a cycle of supplying the metal source, and then purging, and then supplying the oxygen source, and then purging, and then plasma processing in a reduction gas ambient and then purging.