Patent ID: 7084450

Claim:
A semiconductor memory device comprising: a semiconductor substrate; an element region provided on the semiconductor substrate; an element-isolating region provided around the element region and on the semiconductor substrate; a trench provided in the semiconductor substrate, the trench contacting the element region; a capacitor having a first electrode provided in the semiconductor substrate and a second electrode provided in the trench; a first insulating film provided on a side surface of the trench and on the capacitor; a first conductive layer provided on the first insulating film and the second electrode so as to bury the trench; a second insulating film provided on a side surface of the trench and on the first insulating film, and provided on both side surfaces of the element region; a gate electrode provided on the element region through a gate insulating film; a source region and a drain region provided in the element region on both sides of the gate electrode; and a contact layer provided on the first conductive layer and the element region so as to connect the first conductive layer with the source region or the drain region.