Patent ID: 8922029

Claim:
An apparatus comprising: a wiring board; and first, second and third memory devices each mounted on the wiring board; the wiring board comprising: a main bus line including first, second and third nodes arranged such that a signal is transferred from the first node to the third node through the second node; and first, second and third sub bus lines branching respectively from the first, second and third nodes and electrically coupled respectively to the first, second and third memory devices; the first and second nodes defining a first line portion therebetween, and the second and third nodes defining a second line portion therebetween, the first line portion being greater in length than the second line portion, wherein each of the first and second line portions is free from an additional node from which an additional sub bus line branches, the wiring board further comprising a fourth memory device mounted on the wiring board, wherein the main bus line of the wiring board further includes a fourth node arranged adjacently to the third node such that the signal is transferred from the third node to the fourth node, the wiring board further comprising a fourth sub bus line branching from the fourth node and electrically coupled to the fourth memory device, the third and fourth nodes defining a third line portion therebetween, and the third line portion being substantially equal in length to the second line portion.