Patent ID: 8305507

Claim:
A thin film transistor array panel, comprising: a gate line; a data line intersecting the gate line; a storage electrode apart from the gate line and the data line; a semiconductor disposed under the storage electrode and contacting the storage electrode; a thin film transistor connected to the gate line and the data line and having a drain electrode formed of the same layer as the storage electrode; a pixel electrode connected to the drain electrode and electrically separated from the storage electrode; a first insulating layer over the storage electrode and the drain electrode and disposed under the pixel electrode; a second insulating layer disposed on the first insulating layer, and having an opening exposing the first insulating layer on the storage electrode, a shielding electrode disposed in the same layer as the pixel electrode and transmitting a common voltage, the shielding electrode contacting the storage electrode, wherein the shielding electrode comprises a first portion extending along the data line and covering the data line.