Patent ID: 8288823

Claim:
Double gate transistor microelectronic device comprising: a support, a structure suited to forming at least one multi-branch channel and comprising a plurality of separate parallel semi-conductor rods having a longitudinal direction parallel to a principal plane of the support and situated in a plane orthogonal to the principal plane of the support, the semi-conductor rods linking in said longitudinal direction a first block suited to form a source region of the transistor and a second block suited to form a drain region of the transistor, a first gate electrode situated on one side of said structure adjacent lateral sides of said semi-conductor rods, a second gate electrode, separate from the first gate and situated on another side of the structure adjacent opposite lateral sides of the semi-conductor rods, wherein the semi-conductor rods, and one or several insulating rods having a longitudinal direction parallel to said longitudinal direction of said semi-conductor rods and situated between the semi-conductor rods, separate the first gate electrode and the second gate electrode, the insulating rods having a width Wes less than a width Wsi of the semi-conductor rods, wherein a ratio between the width Wsi of the semi-conductor rods and the width Wes of the insulating rods is so as to confer to said microelectronic device a DIBL factor inferior to a predetermined maximum threshold DIBL max and/or so as to confer to said microelectronic device at least one coupling factor between the two gate electrodes, superior to a predetermined minimum coupling factor Î± 0 .