Patent ID: 8878273

Claim:
A semiconductor memory device, comprising: an active region protruding from a substrate, the active region comprising first and second doped regions therein and a trench therein separating the first and second doped regions; a buried gate structure extending in a first direction along the trench between first and second opposing sidewalls thereof; a conductive interconnection plug on the first doped region adjacent the first sidewall of the trench; a conductive interconnection line on the conductive interconnection plug opposite the first doped region and extending in a second direction substantially perpendicular to the first direction, wherein the conductive interconnection line and the conductive interconnection plug have a substantially similar width along the first direction such that opposing sidewalls thereof are aligned at an interface therebetween; a conductive landing pad on the second doped region adjacent the second sidewall of the trench, the conductive landing pad having a width greater than that of the second doped region of the active region along the first direction; a conductive storage node contact plug on the conductive landing pad opposite the second doped region, the conductive storage node contact plug having a narrower width than the conductive landing pad along the first direction; and a storage element on the conductive storage node contact plug opposite the conductive landing pad, wherein the conductive storage node contact plug extends from the conductive landing pad to the storage element.