Patent ID: 7729898

Claim:
A method comprising: receiving a first logic block provided with a plurality of first logic block configuration options, the first logic block configured to select an optimal first logic block configuration option from the plurality of first logic block configuration options based on designated functional specifications, the plurality of first logic block configuration options identifying a first configuration specifying a first number of logic elements and a second number of digital signal processing blocks and a second configuration specifying a third number of logic elements and a fourth number of digital signal processing blocks, wherein the first, second, third, and fourth numbers are different values; receiving a second logic block provided with a plurality of second logic block configuration options; analyzing a plurality of heterogeneous device options, the plurality of first logic block configuration options and the plurality of second logic block configuration options; selecting a programmable chip optimal first logic block configuration option from the plurality of first logic block configuration options using a linear search of combinations of configuration options comprising one option from the plurality of first logic block configuration options and one option from the plurality of second logic block configuration options; implementing the first logic block and the second logic block on a heterogeneous device.