Patent ID: 8441040

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a cell array block having, above the semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells connected to respective intersections of the first and second wirings, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, directly connected to the first wiring in an n 1 -th layer (n 1 is a natural number) of the cell array block and at least one of the first wiring in an n 2 -th layer (n 2 is a natural number other than n 1 ), the semiconductor substrate and another metal wiring, and extending in a laminating direction of the cell array block, the first via wiring having a cross section orthogonal to the laminating direction of the cell array block, the cross section having an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.