Patent ID: 8067965

Claim:
A clock and data recovery circuit, comprising: a phase detector for receiving a data signal and a first output clock signal, and comparing the data signal with the first output clock signal, thereby generating a judging signal; a charge pump electrically connected to the phase detector for generating a switching signal according to the judging signal; a loop filter electrically connected to the charge pump for receiving the switching signal and generating a corresponding control voltage; a voltage-controlled oscillator connected to the loop filter and the phase detector for generating a second output clock signal and adjusting the frequency of the second output clock signal according to the control voltage, wherein the voltage-controlled oscillator comprises: a current mirror having a current-controlling path and a current-outputting path, wherein the current-controlling path and the current-outputting path are in a proportional relationship; a control circuit electrically connected to the loop filter and the current-controlling path for adjusting the current flowing through the current-controlling path according to the control voltage; a current modulation module for generating a differential current according to the judging signal; and a current-controlled oscillator electrically connected to the current-outputting path and the current modulation module for adjusting the phase of the second output clock signal according to the sum of the differential current and the current flowing through the current-outputting path; and a frequency divider electrically connected to the current-controlled oscillator for performing frequency division on the second output clock signal, thereby generating the first output clock signal.