Patent ID: 8780636

Claim:
A nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a memory cell array including a plurality of memory cells, the memory cells being stacked above the semiconductor substrate and being connected in series; and a power supply circuit configured to supply a first voltage to the memory cell array, the power supply circuit comprising: a pump circuit configured to generate the first voltage and supply the first voltage to the memory cell array; a limiter circuit connected to an output terminal of the pump circuit, the limiter circuit being configured to output a control signal for activating the pump circuit according to a comparison result between a voltage value of the output terminal and a first value; a capacitor having one end connected to the output terminal, the capacitor being provided between the memory cell array and the semiconductor substrate; a boost circuit connected to the other end of the capacitor, the boost circuit being configured to charge the capacitor by using a current based on the control signal; and a switch configured to inhibit a charge operation of the boost circuit.