Patent ID: 7961732

Claim:
Apparatus for implementing frame alteration commands in a communications network processor for a plurality of packet types comprising: a set of frame alteration instruction templates defined in a frame alteration table within hardware; each of said set of frame alteration instruction templates having different frame alteration commands to be performed on a packet and including a plurality of bytes 0 -N; each of said set of frame alteration instruction templates being enabled to obtain data from an original header data together with data from classification leafs hit during a packet classification including from table lookup results and from memory; a packet type recognition hardware function for receiving a packet header and identifying a frame alteration instruction template from said set of frame alteration instruction templates based upon a packet type recognition result; and a frame alteration instruction stream generating logic utilizing said frame alteration instruction template for generating a frame alteration instruction stream, and said frame alteration instruction stream generating logic including a mask with each byte of said plurality of bytes 0 -N of said identified frame alteration instruction template for providing frame alteration data in said frame alteration instruction stream; said mask includes a plurality of bits 0 -N, each bit of said mask being used to select a byte from said identified frame alteration instruction template, and to select a byte pointed to by the frame alteration instruction template in one or more of said original packet data, said table lookup results, and said memory.