Patent ID: 7888186

Claim:
A method for assembling a stackable semiconductor package, comprising: providing a substrate having a first surface and a second surface, wherein the first surface comprises a plurality of bond pads and one or more die pads for attaching one or more semiconductor dies; attaching the one or more semiconductor dies on the one or more die pads; forming a plurality of conductive bumps on the plurality of bond pads; placing the substrate in a side-gate molding cast, such that the molding cast surrounds the first surface of the substrate, the one or more semiconductor dies and the plurality of conductive bumps; and supplying a mold material to the first surface of the substrate via side-gates of the molding cast, wherein the mold material covers the one or more semiconductor dies and at least partially covers the plurality of conductive bumps, wherein a portion of each of the plurality of conductive bumps is exposed for providing electrical connection to a second semiconductor package, whereby, a first semiconductor package comprising a first boundary layer and a second boundary layer is formed, the first boundary layer being delineated by a first surface of the mold material and the exposed portion of the plurality of conductive bumps and the second boundary layer being delineated by the second surface of the substrate.