Patent ID: 7307897

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cell array blocks in turn including first and second memory cell array blocks, a number of word lines activated when the first memory cell array blocks are selected being greater than a number of word lines activated when the second memory cell array blocks are selected; a first boosting voltage generating means generating a first driving signal when the semiconductor memory device operates in an active mode and supplying a boosting voltage that is higher than a power supply voltage to an output terminal in response to the first driving signal; and a second boosting voltage generating means including first and second boosting voltage generators, the first boosting voltage generator generating a second driving signal when a level of the boosting voltage of the output terminal is below a target level in the active mode and pumping the boosting voltage in response to the second driving signal, the second boosting voltage generator pumping the boosting voltage in response to an activated third driving signal, the third driving signal being activated in response to the first driving signal when the first memory cell array blocks are selected as indicated by a selecting signal, and in response to the second driving signal when the second memory cell array blocks are selected as indicated by the selecting signal.