Patent ID: 8214623

Claim:
A data processing system comprising: a bus; a memory connected to the bus, wherein a set of instructions are located in the memory; and a processor connected to the bus, wherein the processor executes the set of instructions to: responsive to running a primary operation, identify all pre and post operations based on predefined metadata and an environment context of the application, wherein the processor executes the set of instructions to identify by: responsive to running the primary operation, determining if a cycle is present in an execution path of the primary operation; if no cycle is present, populating an extended operation cache with cached extended operation identifiers, wherein populating comprises: reading a plurality of operation extensions for a given primary operation identifier; determining if each corresponding operation extension in the plurality of operation extensions defines a corresponding at least one of a pre or post operation identifier; associating the corresponding at least one of pre or post operation identifier with a corresponding function group identifier; for each corresponding operation extension in the plurality of operation extensions, creating a corresponding primary operation record for each operation extension, and placing the corresponding primary operation record in the extended operation cache; and wherein the processor further executes the set of instructions to identify by: identifying a plurality of pre operation identifiers and post operation identifiers from the cached extended operation identifiers; and wherein the processor further executes the set of instructions to: recursively run all pre operations in a predefined order; execute the primary operation; and recursively run all post operations in a predefined order.