Patent ID: 7952384

Claim:
A semiconductor device transmitting data using a multilevel signal, the semiconductor device comprising: a parity bit control unit configured to generate a parity bit in accordance with a number of the data having a most significant bit (MSB) and a least significant bit (LSB) that are different, and comprising: a plurality of XOR gates each configured to perform an exclusive OR operation on an input of the MSB and the LSB of corresponding data, a counter configured to count the number of the data and provide a corresponding count value in response to output signals provided by the plurality of XOR gates, and a parity bit generation unit configured to generate the parity bit in a first logic state when the count value is less than or equal to half of a total number of the data, or generate the parity bit in a second logic state when the count value is greater than half of the total number of the data; a data conversion unit configured to either inversely output one of the MSB and LSB, or output the data without a change in response to the parity bit; and a plurality of transmission units configured to transmit data output from the data conversion unit using the multilevel signal.