Patent ID: 7730544

Claim:
A processor, comprising: at least one execution unit; an instruction scheduler connected to the at least one execution unit; an interrupt controller; a memory management circuit; at least two simultaneous execution contexts including: at least one nonprivileged execution context connected to the instruction scheduler and the interrupt controller and accessible in a user mode, the nonprivileged execution context comprising a first data register; at least one privileged execution context connected to the at least one nonprivileged execution context and accessible only by an operating system of the processor in a privileged mode, and further connected to the at least one execution unit, the instruction scheduler, and the interrupt controller, the privileged execution context comprising a second data register; wherein the privileged context is configured to use a demultiplexer to: restrict use of at least one of the instruction scheduler, interrupt controller, and memory management circuit by at least one non privileged context, control and operate the at least one nonprivileged contexts, isolate at least one of the nonprivileged contexts from other of the at least one nonprivileged contexts, control the at least one execution unit, the instruction scheduler, and the interrupt controller and exclusively access tables of memory pages in the memory management circuit.