Patent ID: 8466732

Claim:
A circuit comprising: a first inverter, an input of the first inverter configured to serve as an input node; a second inverter, an output of the first inverter coupled to an input of the second inverter; an output of the second inverter configured to serve as an output node; a third inverter, an input of the third inverter coupled to the input of the first inverter; and a first NMOS transistor, a gate of the first NMOS transistor coupled to an output of the third inverter; a drain of the first NMOS transistor coupled to the second inverter; a source of the first NMOS transistor configured to serve as an input level node, wherein when the input node is configured to receive a low logic level, the output node is configured to receive a voltage value provided by a voltage value at the level input node, and wherein the second inverter includes a PMOS transistor having a PMOS source, a PMOS drain, and a PMOS gate; and a second NMOS transistor having a second NMOS drain, a second NMOS source, and a second NMOS gate; and the second NMOS source directly coupled to the drain of the first NMOS transistor.