Patent ID: 7406637

Claim:
A semiconductor memory device comprising: a memory core including a plurality of memory cells arranged in rows and columns and storing data, the memory core further including a plurality of spare memory cells configured to replace the memory cells when any one of the memory cells is defective, the memory core also including a to-be replaced unit of a preset number of memory cells included in the plurality of memory cells, the to-be replaced unit being replaceable in any one of the rows and the columns when the to-be replaced unit is replaced with the spare memory cells, the to-be replaced unit being provided at an intersection of a first memory cell region and a second memory cell region, the first memory cell region being simultaneously replaceable with memory cells of one of the rows, the second memory cell region being simultaneously replaceable with memory cells of one of the columns; a data register which stores test data input corresponding to input of a command; a data control circuit configured to read a number j (j is a natural number not less than 2) of data items from the memory cells of the data items from memory cells included in the to-be replaced unit included in the to-be-replaced unit in synchrony with a clock signal; and a data output compression circuit configured to use the test data as an expected value, and compare each of the number j of the data items, read from the memory cells in synchrony with the clock signal, with the expected value, the data output compression circuit outputting, for a period corresponding to j cycles, information indicating that the data items are not equal to the expected value, if at least one of the data items is not equal to the expected value.