Patent ID: 7101768

Claim:
A method of forming an enhanced capacitance trench capacitor, comprising: forming a trench in a semiconductor substrate; forming an isolation collar on a sidewall of said trench having at least an exposed layer of oxide, said isolation collar occupying only a collar portion of said sidewall; providing a capacitor portion of said sidewall of said trench below said isolation collar, said capacitor portion self-aligned to a bottom of said isolation collar; selectively depositing a seeding layer including silicon nitride on said capacitor portion of said sidewall to self-align said seeding layer to said bottom of said isolation collar; selectively depositing hemispherical silicon grains on said seeding layer to form a hemispherical silicon grain covered region of said trench sidewall self-aligned to said bottom of said isolation collar; and depositing a capacitor dielectric material and another material in order, over said hemispherical silicon grains, the another material including at least one of doped polysilicon, metal and metal silicide, to form said enhanced capacitance trench capacitor self-aligned to said bottom of said isolation collar.