Patent ID: 7020027

Claim:
A method of programming a memory cell with a plurality of P-channel insulated gate field effect transistors (P-IGFETs), each having a gate, a drain, a source and an N-well, and including a control P-IGFET with a control electrode connecting its drain, source and N-well, a write P-IGFET with a write electrode connecting its source and N-well, a read P-IGFET with a read electrode connecting its source and N-well, an erase P-IGFET with an erase electrode connecting its drain, source and N-well, and a shared electrode connecting said control, write, read and erase P-IGFET gates, said method comprising: applying a substantially fixed reference voltage to said control electrode, said write P-IGFET drain, said write electrode, said read P-IGFET drain, said read electrode and said erase electrode; applying to said write electrode a substantially fixed programming voltage which is more positive than said reference voltage; and applying to said control electrode a variable voltage having a magnitude which is approximately ramped from said reference voltage to a predetermined voltage which is more positive than said reference voltage.