Patent ID: 8571169

Claim:
A scanning line driving circuit comprising a multi-stage shift register, wherein: each stage of said multi-stage shift register comprises: an output terminal for outputting an output signal; a first input terminal receiving an output signal of a preceding stage; a second input terminal receiving an output signal of a subsequent stage; a first voltage signal terminal supplied with a first voltage signal; a second voltage signal terminal supplied with a second voltage signal; a clock terminal; a first transistor supplying a clock signal input to said clock terminal to said output terminal; a second transistor discharging said output terminal; a third transistor connected between a first node connected with a control electrode of said first transistor and said first voltage signal terminal and including a control electrode connected to said first input terminal; and a fourth transistor connected between said first node and said second voltage signal terminal and including a control electrode connected to said second input terminal; each stage of said multi-stage shift register changes a scanning direction by switching levels of said first and second voltage signals; said first input terminal at the first stage and said second input terminal at the last stage of said multi-stage shift register receive the same start pulse, the first stage and the last stage not being a dummy stage; and after a lapse of an activation period of an output signal at a specific stage of said multi-stage shift register, a clock signal supplied to said clock terminal at said specific stage is kept at a deactivation level until said start pulse is activated during a next frame period, said specific stage being activated last during a frame period.