Patent ID: 7734866

Claim:
A memory controller comprising: a first integrated circuit chip including refresh control circuitry configured to generate a first-type refresh command at a first refresh rate by a first refresh address generator, and directed to a first row of storage cells within an external memory device at the first refresh rate and configured to generate a second-type refresh command at a second refresh rate by a second refresh address generator, and directed to a second row of storage cells within the external memory device at the second refresh rate, wherein the second-type refresh command comprises an accelerated refresh rate which is higher than the first refresh rate; and wherein the first row is one of a plurality of rows that exhibit at least a first retention time, and the second row of storage cells within the memory device exhibits a retention time that is shorter than the first retention time, wherein the refresh control circuitry further comprises an address generating circuit configured to generate a series of repeating sequences of row addresses, each sequence of row addresses including a singular instance of a first address that corresponds to the first row of storage cells and plural instances of a second address that corresponds to the second row of storage cells, wherein, within a single sequence of the series of repeating sequences of row addresses, the singular instance of the first address may be located either before or after the location of any of the plural instances of the second address; and output circuitry configured to output the first and second refresh command types to the external memory device according to the generated series of repeating sequences of row addresses, the external memory device comprising a second integrated circuit chip.