Patent ID: 8091060

Claim:
A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC), the method comprising: storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate placement of components to different clock regions of the programmable IC; determining, using a processor, a result indicating whether a feasible clock domain partitioning exists for the circuit design by minimizing a first objective function subject to the plurality of constraints; responsive to determining that the circuit design is infeasible, modifying at least one of the plurality of constraints to include error variables, wherein the error variables cause a clock domain partitioning to be determined in which a number of global clocks within each clock region is permitted to exceed a maximum number of allowable global clocks; defining a second objective function that depends upon a sum of the error variables; and minimizing the second objective function subject to the plurality of constraints.