Patent ID: 7315551

Claim:
A synchronous Input/Output (I/O) interface bus system comprising: a master bus controller configured to generate and transmit at least one system timing signal, transmit a time-division multiplexed (TDM) slave output data signal, and receive a TDM slave input data signal, the TDM slave output data signal and the TDM slave input data signal being synchronous relative to the at least one system timing signal; a bus having a plurality of wires; and at least one slave device synchronously coupled to the bus by way of the at least one system timing signal, the at least one slave device being configured to de-multiplex slave device output data in a device-ready format from the TDM slave output data signal during a predetermined output data signal time slot, and to multiplex slave device input data in a processor-ready format into the TDM slave input data signal during a predetermined input data signal time slot; a memory; an input array coupled to the memory and configured to receive and de-multiplex a TDM slave input data signal, and write the slave input data into the memory; an output array coupled to the memory and configured to retrieve slave output data from the memory, multiplex the slave output data into a TDM slave output signal, and transmit the slave output data signal; and a processor configured to at least control the operation of the input and output arrays.