Patent ID: RE40695

Claim:
A clock phase detecting circuit arranged in a receiving unit of multiplex radio equipment, comprising: an identifying circuit for identifying a signal at a predetermined identification level, said signal being obtained by demodulating a multilevel orthogonal modulated signal; a clock regenerating circuit for regenerating a signal identification clock for said identifying circuit to supply said clock to said identifying circuit; an equalizing circuit for subjecting said signal obtained by demodulating the multilevel orthogonal modulated signal to an equalizing process; and a clock phase detecting unit for detecting a phase component of said signal identification clock based on errors between input and output signals of said equalizing circuit and then for supplying said phase component to said clock regenerating circuit; wherein said clock phase detecting unit includes: an error detecting unit for detecting a signal error between said input and output signals of said equalizing circuit: and a clock phase calculating unit for detecting the phase component of said signal identification clock by calculating the detection outputs from said error detecting unit.