Patent ID: 7335589

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming first spacers on sidewalls of first structures, wherein the first structures include conductive pattern layers and insulation pattern layers stacked on a semiconductor substrate, wherein the insulation pattern layers are formed on the conductive pattern layers, and wherein each conductive pattern has a first width and wherein a thickness of each of the insulation pattern layers is at least four times thinner than a thickness of each of the conductive pattern layers; forming a first insulation film to cover the first structures including the first spacers and regions between the first structures; forming first insulation film patterns in the regions between the first structures by planarizing the first insulation film until upper faces of the insulation pattern layers are exposed; forming second structures directly on the insulation pattern layers, wherein first portions of the first insulation film patterns are exposed between the second structures, and wherein the second structures have second widths extending in a horizontal direction by a distance of about 5 to about 35 percent of intervals between the first structures, and wherein the second structures prevent etching of the first structures; forming a second insulation film filling regions between the second structures; and forming openings exposing portions of the semiconductor substrate by partially etching portions of the second insulation film and successively etching the first portions of the first insulation film patterns using the second structures and the first spacers as etching masks.