Patent ID: 7965531

Claim:
A memory system comprising: a memory controller; a first memory module; and wirings for a system data signal which have a predetermined data width, the system data signal being transferred between the memory controller and the first memory module, wherein: the first memory module comprises: a first IO chip; a plurality of memory chips stacked over the first IO chip; first through electrodes extending through the plurality of stacked memory chips, and connecting between the first IO chip and each of the memory chips; and signal terminals electrically connected to the first IO chip, the system data signal being input to the first IO chip by the signal terminals, and the system data signal being output from the first IO chip by the signal terminals, wherein: the first IO chip performs a conversion between the system data signal and a first internal data signal transferred by the first through electrodes in the first memory module, and a width of the first internal data signal is broader than a width of the system data signal.