Patent ID: 7787319

Claim:
An integrated circuit device comprising: a memory cell array having a plurality of memory cells; sense amplifier circuitry, coupled to the memory cell array, to sense a data state stored in a memory cell wherein the memory cell is one of the plurality of the memory cells in the memory cell array, the sense amplifier circuitry including: first and second capacitors, each capacitor having first and second terminals; a first input electrically coupled to (i) the memory cell to receive a signal which is representative of the data state stored in the memory cell and (ii) the first terminal of the first capacitor; a second input electrically coupled to (i) a first predetermined voltage and (ii) the first terminal of the second capacitor; a first current source having first and second terminals; a first transistor having a gate, a first region and a second region, wherein: the gate is electrically coupled to the second terminals of the first and second capacitors, and the first region is electrically coupled to the first terminal of the first current source; and wherein, during a sense phase of operation of the sense amplifier circuitry, the sense amplifier circuitry senses the data state stored in the memory cell based on the signal which is representative of the data state stored in the memory cell.