Patent ID: 8253424

Claim:
A topology for surveying the integrity of a plurality of capacitors connected in series between a pair of bus lines designed and arranged to be connected to a DC-power source, the topology comprising: a plurality of resistors connected in series between the pair of bus lines, the plurality of resistors being connected in parallel to the plurality of capacitors; and a comparator comparing the electric potential of an intermediate point between two capacitors of the plurality of capacitors with the electric potential of an intermediate point between two resistors of the plurality of resistors, and providing a signal signaling a difference between these two electric potentials which indicates a loss of integrity of one capacitor of the plurality of capacitors, wherein the signal signals whether a difference between the two electric potentials exceeds a predetermined threshold value, and wherein voltages dropping over the capacitors on both sides of the intermediate point between the two capacitors of the plurality of capacitors are defined by means of further resistors connected in parallel to these capacitors, and wherein a ratio of resistances of these further resistors on both sides of the intermediate point between the two capacitors, and a ratio of resistances of the resistors of the plurality of resistors on both sides of the intermediate point between the two resistors of the plurality of resistors are equal.