Patent ID: 8627262

Claim:
A computer-implemented method for generating merged mode for a circuit that is equivalent to a plurality of individual modes for the circuit, the method comprising: generating, by a computer, a merged mode by combining timing constraints from a plurality of individual modes, at least one extraneous timing relationship not present in the plurality of individual modes but present in the merged mode; determining, by the computer, a first set of timing relationships for the merged mode and a second set of timing relationships for each individual mode; identifying a plurality of data paths from a plurality of timing paths between a start timing node and an end timing node in the merged mode; identifying a reconvergent node between the start timing node and the end timing node; comparing, by the computer, the first set of timing relationships with the second set of timing relationships to identify the at least one extraneous timing relationship of data paths connected to the reconvergent node; and adding, by the computer, a timing constraint associated with at least one of the data paths to the merged mode to eliminate the extraneous timing relationship.