Patent ID: 8356361

Claim:
An apparatus that facilitates integrated security capabilities, comprising: a memory module that includes non-volatile memory that stores security software; and a security processor that: accesses the security software from the non-volatile memory; performs security functions based on the stored security software; controls the non-volatile memory and monitors traffic to and from the non-volatile memory; exclusively executes interrupts associated with the security software; controls a cryptographic accelerator that supports the encryption and decryption of data; coordinates read and write operations to the non-volatile memory with a host processor, wherein a first integrated circuit comprises the security processor and a second integrated circuit comprises the host processor; executes a rights object handling application stored in a first partition of the non-volatile memory in a heightened security environment and the host processor contemporaneously executes a content handling application stored in a second partition of the non-volatile memory in a lessened security environment, wherein the rights object handling application is a secure part of the non-volatile memory that communicates exclusively with the security processor and the content handling application is a non-secure part of the non-volatile memory that communicates directly with the host processor; the security processor comprising: the cryptographic accelerator that supports the encryption and decryption of data between the host processor and the flash memory, the cryptographic accelerator enables the flash memory to be an encrypted storage device; a flash buffer that holds data to and from the flash memory such that a first page can be processed as a second page is received; a joint test action group port that prevents tempering and serves as a mechanism for debugging the security processor; and a CPU that controls the data flow through the security processor, the host processor arbitrates with the security processor for access to the non-volatile memory, and the security processor sits in series with the host processor and the non-volatile memory.