Patent ID: 8054857

Claim:
A data-processing system, comprising: an I/O interface for managing the transfer of data directly between a processor and at least one memory, said processor associated with said I/O interface; a task queue, wherein said processor comprises said task queue, said task queue containing a plurality of transmit tasks for transmitting a plurality of frames over said I/O interface, at least one processing unit for executing said plurality of transmit tasks, said memory, and interface logic for accessing said memory and said task queue; a transmit word router that communicates with a transmit frame router comprising said task queue; wherein said processor assembles a first frame from among said plurality of frames containing primitives, header information, and frame data, transmits said first frame from among said plurality of frames over said I/O interface wherein said transmitting comprises of sending only said primitive from one address, sending only said leader information from another address, sending only said frame data from a data FIFO, and sending only another said primitive from yet another address and thereafter processes and assembles a subsequent frame from among said plurality of frames while said first frame is transmitting to a recipient, thereby providing enhanced flexibility and speed for the assembly and transmission of said plurality of frames across said I/O interface; wherein said at least one processing unit comprises a custom processor that includes a module for driving said task queue.