Patent ID: 6882207

Claim:
An offset control circuit for adjusting offset voltages contained in differential voltages that are input from a pair of differential voltage input terminals and outputting the adjusted differential voltages from a pair of differential voltage output terminals, the offset control circuit comprising: a voltage/current converting portion that includes the pair of differential voltage input terminals and a pair of differential current output terminals, that generates a pair of differential output currents corresponding to a potential difference between a pair of differential input voltages input from the pair of differential voltage input terminals, and that outputs the pair of differential output currents from the pair of differential current output terminals; an offset adjusting current-generating portion that includes a pair of offset adjusting current-output terminals connected to the pair of differential current output terminals of the voltage/current converting portion, and at least two offset adjusting current-control terminals, that generates a pair of offset adjusting currents by being controlled by offset adjusting current control signals input from the offset adjusting current-control terminals, and that outputs the pair of offset adjusting currents from the pair of offset adjusting current-output terminals; and a current/voltage converting portion that includes a pair of differential terminals connected to the pair of differential current output terminals of the voltage/current converting portion, the pair of offset adjusting current-output terminals of the offset adjusting current-generating portion and the pair of differential voltage output terminals, that feeds a current flowing between the two differential terminals constituting the pair of differential terminals, that converts the current into a corresponding voltage, an that generates the converted voltage at the pair of differential voltage output terminals, wherein the voltage/current converting portion includes: a pair of bias current sources connected to the pair of differential current output terminals; a pair of first transistors whose first driving terminals are connected to the pair of differential current output terminals, respectively, and whose gates are both connected to a control terminal; and a pair of second transistors whose first driving terminals are connected to second driving terminals of the pair of first transistors, respectively, whose gates are connected to the pair of differential voltage input terminals, respectively, and whose second driving terminals are connected to a reference potential supplying point.