Patent ID: 7183655

Claim:
A packaged semiconductor device comprising: at least one integrated chip having formed thereon: an integrated circuit for realizing a device function, and first bump connection pads formed at predetermined intervals; and a non-integrated chip having formed thereon only: second bump connection pads formed so as to face the first bump connection pads, lead connection pads formed at intervals greater than the predetermined intervals; and wiring conductors for electrically connecting together the second bump connection pads and the lead connection pads, wherein no integrated circuit requiring a semiconductor process such as selective impurity diffusion is formed on the non-integrated chip and the integrated and non-integrated chips are connected together by way of bumps and are then sealed in resin, and wherein the second bump connection pads each have a central portion thereof elevated so as to have two levels so that, when the second bump connection pads are seen in a plan view, higher-level portions thereof have a smaller area than lower-level portions thereof.