Patent ID: 7411842

Claim:
A data arrangement control signal generation circuit for use in a semiconductor memory device, comprising: a plurality of data arrangement control signal generation units connected in series for selectively generating a data arrangement control signal according to a CAS pulse (CASP) signal or a CAS Latency signal based on column address strobe (CAS) latency information and an output of a delay locked loop (DLL), wherein a first data arrangement control signal generation unit logically combines the CASP signal enabled based on an external read command and a predetermined address to output a first data arrangement control signal; a second data arrangement control signal generation unit transfers the first data arrangement control signal in response to a rising clock that is outputted from the DLL to output a second data arrangement control signal; and a third data arrangement control signal generation unit selectively transfers the first or second data arrangement control signal in response to a first CAS latency signal and the rising clock, the first CAS latency signal having a first CAS latency information including a first CAS latency value to output a third data arrangement control signal; and a fourth data arrangement control signal generation unit selectively transfers the third data arrangement control signal in response to the first CAS latency signal, a second CAS latency signal and a falling clock that is outputted from the DLL, the second CAS latency signal having a second CAS latency information including a second CAS latency value to output a fourth data arrangement control signal.