Patent ID: 8336011

Claim:
A method for fabricating an integrated circuit comprising: providing a logical design for the integrated circuit, the logical design including a plurality of elements; developing a library of element patterns derived by identifying layout patterns having electrical properties that deviate from modeled properties using a software tool on a computer, the library further including a quantitative measure of deviation from modeled properties, wherein the step of developing comprises: measuring electrical parameters on semiconductor test devices and comparing measured parameters to results generated by standard models using the software tool on the computer, adjusting physical properties of the semiconductor test devices and determining the effect on the measured parameters using the software tool on the computer, and determining the quantitative measure of deviation caused by the adjusted physical properties using the software tool on the computer and grouping results in measured parameters falling within a specified range; comparing elements in the logical design to the library of element patterns using the software tool on the computer; determining, in response to the comparing and with consideration of the quantitative measure, whether the elements are acceptable in the logical design using the software tool on the computer; modifying elements that are not acceptable; generating a mask set implementing the logical design using the elements or modified elements; employing the mask set to implement the logical design in and on a semiconductor substrate.