Patent ID: 8589775

Claim:
A memory circuit, comprising: a plurality of memory element pairs respectively configured to store a data unit, wherein respective memory element pairs comprise a first memory storage element and a second memory storage element; and a parity bit comparison logic configured to calculate a first parity bit by collectively using data written to each of the plurality of memory element pairs and a real time second parity bit by collectively using data read from each of second memory storage elements, to store the first parity bit as a stored first parity bit, and to generate a control signal that is provided to one or more selection circuits based upon a relationship between the stored first parity bit and the real time second parity bit, wherein the control signal causes the one or more selection circuits to selectively output data from the second memory storage element if the relationship indicates that no error is present in the second memory storage elements, or from the first memory storage element if the relationship indicates that an error is present in the second memory storage elements.