Patent ID: 7978534

Claim:
A configurable address buffer, comprising: a plurality of input buffers coupled to receive respective address signals, each of the input buffers passing the address signal received by the input buffer to an output terminal; a first address register coupled to the output terminals of a first subset of the input buffers to receive a corresponding subset of the address signals, the first address register storing the received address register signals responsive to the first enable signal; a multiplexer coupled to the output terminals of the input buffers in the first subset, the multiplexer further being coupled to the output terminals of a second subset of the input buffers to receive a corresponding subset of the address signals, the multiplexer being responsive to a first mode signal to couple address signals from the output terminals of the input buffers in the second subset to a set of output terminals, and being responsive to a second mode signal to couple address signals from the output terminals of the input buffers in the first subset of the set of output terminals, and; a second address register coupled to receive the address signals from the output terminals of the signal routing device, the second address register storing the received address register signals responsive to a second enable signal; a mode register; and a control circuit operable to generate the first and second enable signals and the first and second mode signals, the control circuit being operable in a first mode to generate the first mode signal and to simultaneously generate the first and second enable signals, and being operable in a second mode to generate the second mode signal and to sequentially generate the first and second enable signals wherein the mode register is programmable to store the first and second mode control signals wherein an address bus coupled to the input buffers in one mode has a width equal to the number of address terminals and in the other mode the address bus has a width less than the number of address terminals, wherein in the mode in which the address bus width is less than the number of address terminals, the excess address terminals are coupled to ground.