Patent ID: 6920544

Claim:
A processor comprising: an address counter for counting up and down; a memory unit storing a plurality of instructions, each instruction having a plurality of constituent bytes; and a controller controlling the address counter and the memory unit; wherein each of said constituent bytes is stored at a separate address in the memory unit; the constituent bytes constituting said each instruction are stored in ascending or descending address order in an address group consisting of consecutive addresses; a leading constituent byte of a first instruction and a leading constituent byte of a second instruction are stored at mutually adjacent addresses; the constituent bytes of the first instruction are stored in descending address order, the constituent bytes of the second instruction being stored in ascending address order; an address pointer indicating the address of the leading constituent byte of the first or second instruction is provided; an initial count value is set in the address counter according to the address pointer, the constituent bytes of the first instruction are read in sequential order while the address counter counts down, and the first instruction is executed; and another initial count value is set in the address counter according to the address pointer, the constituent bytes of the second instruction are read in sequential order while the address counter counts up, and the second instruction is executed.