Patent ID: 8711607

Claim:
A semiconductor device, comprising: a logic circuit including a plurality of MOS transistors and a source node; a first SRAM memory cell array including a plurality of first memory cell transistors; a second SRAM memory cell array including a plurality of second memory cell transistors; a first voltage supply line to supply a first voltage to the logic circuit, the first SRAM memory cell array and the second SRAM cell memory array; a first switch coupled between the first voltage supply line and the source node; a second switch coupled between the first voltage supply line and the second SRAM memory cell array; a control circuit to control a substrate bias of the first memory cell array, wherein the first SRAM memory cell array is directly coupled to the first voltage supply line, wherein the first memory transistors include nMOS transistors, and in a standby mode, the first switch is off and a threshold voltage of the nMOS transistors is higher than the threshold voltage of the nMOS transistors in an operation mode, wherein while a power supply of the first voltage to the second SRAM memory cell array is cut off by the second switch in the standby mode, the first SRAM memory cell array is supplied with the first voltage from the first supply line.