Patent ID: 8058087

Claim:
A method for fabricating a thin film transistor array substrate, the method comprising: providing a substrate, the substrate having a pixel region and a peripheral circuit region that surrounds the pixel region; forming a gate pattern on the substrate in the pixel region and forming a first pad pattern on the substrate in the peripheral circuit region; sequentially forming a gate insulation layer and a semiconductor layer on the substrate for covering the gate pattern and the first pad pattern; forming a patterned photoresist layer on the semiconductor layer, wherein the patterned photoresist layer comprises a first resist block and a second resist block, the first resist block is disposed above the gate pattern, the second resist block has a first opening and corresponds to regions on which the gate pattern is not formed, the first opening is disposed above the first pad pattern, and a thickness of the first resist block is greater than a thickness of the second resist block; performing an etching process with use of the patterned photoresist layer as a mask for removing the semiconductor layer and a portion of the gate insulation layer corresponding to the first opening; reducing a thickness of the patterned photoresist layer until the second resist block is removed to form a remaining patterned photoresist layer; performing an etching process with use of the remaining patterned photoresist layer as the mask for removing the exposed semiconductor layer and the gate insulation layer corresponding to the first opening; removing the remaining patterned photoresist layer; respectively forming a source pattern and a drain pattern on the semiconductor layer within the pixel region and forming a second pad pattern in the peripheral circuit region, wherein the source pattern and the drain pattern are respectively disposed at opposite sides of the gate pattern, and the second pad pattern is electrically connected to the corresponding first pad pattern through the first opening; and forming a patterned passivation layer on the gate insulation layer for covering the source pattern, the drain pattern, and a portion of the second pad pattern, wherein the patterned passivation layer has a second opening in the pixel region, the second opening exposes the corresponding source pattern or the corresponding drain pattern, the patterned passivation layer has a third opening in the peripheral circuit region, and the third opening exposes the second pad pattern.