Patent ID: 7851314

Claim:
A method for making a short channel LMOS (Lateral MOSFET) with interpenetrating drain-body protrusions (IDBP), the method comprises: a) providing a partially fabricated semiconductor wafer oriented in a horizontal plane with: a1) a substrate and a lower device bulk layer of first conductivity type atop; a2) an upper body-contact region of second conductivity type and an upper drain region of first conductivity type, both located atop while being separated by the lower device bulk layer, the upper drain region has a pre-determined drain contact location and the upper body-contact region has a pre-determined body contact location; a3) a body-contact field oxide region atop the upper body-contact region for separating neighboring LMOS devices on the wafer; and a4) a drain-gate field oxide region atop the upper drain region for separating the drain contact location from a gate structure; b) within the upper part of the lower device bulk layer, creating an upper body region of second conductivity type having: b1) its first lateral profile placed close to the upper drain region and shaped to form, together with the lower device bulk layer, a drain-body interface having an interpenetrating drain-body protrusion (IDBP) structure along a vertical plane with a surface drain protrusion lies atop a buried body protrusion while revealing a pre-determined top body surface area of the upper body region with the tip of the surface drain protrusion defining a first end of the LMOS channel length; and b2) its second lateral profile placed close to the upper body-contact region and overlapping therewith; c) forming the gate structure atop the revealed top body surface area and the drain-gate field oxide region with a first edge of the gate structure atop the drain-gate field oxide region and a second edge of the gate structure atop the revealed top body surface area and further spaced from the first end of the LMOS channel length by a pre-determined reference distance; d) creating a drain contact zone of first conductivity type at the drain contact location and creating an upper source region of first conductivity type atop the revealed top body surface area with a first end of the upper source region undercutting the second edge of the gate structure by a pre-determined undercut distance such that the first end of the upper source region defines a second end of the LMOS channel length with: reference distance−undercut distance=the desired LMOS channel length; and e) forming device passivation layers atop the wafer, patterning the device passivation layers for external electrical contacts then forming contact electrodes onto the drain contact zone, the source contact zone and at the body contact location.