Patent ID: 8384425

Claim:
A semiconductor device structure formed on a semiconductor-on-insulator substrate (SeOI), with the semiconductor-on-insulator substrate comprising a thin film of semiconductor material separated from a base substrate by an insulating film, and the device structure comprising: an array of patterns, with each pattern formed by at least one field-effect transistor with each such field-effect transistor having, within the thin semiconductor film of the SeOI substrate, a source region, a drain region, a channel region which is delimited by the source and drain regions, and a front control gate formed above the channel region; wherein the patterns of the array are arranged in rows, with the source and drain regions of any one row having the same dimensions and being spaced apart by front control gates of a fixed dimension, and wherein at least one such field-effect transistor of at least one pattern includes a back control gate formed within the base substrate of the SeOI substrate beneath the channel region, with the back control gate being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor.