Patent ID: 6854003

Claim:
An integrated circuit using a memory, said integrated circuit comprising: an interface circuit configured to control access to said memory, said interface circuit coupled to said memory; an embedded processor configured to control said integrated circuit, said embedded processor receiving information from said interface circuit; and an array processor for performing mathematical calculations on data received from said interface circuit and connected to said embedded processor via an internal bus, said array processor comprising: a plurality of multiplier/accumulator circuits; a plurality of shared operand circuits coupled to said plurality of multiplier/accumulator circuits for simultaneously providing a shared operand to at least two of said plurality of multiplier/accumulator circuits; and a shared output and feedback interface coupled to receive outputs from the at least two of the plurality of multiplier/accumulator circuits and to provide them for further processing by the at least two of the multiplier/accumulator circuits, wherein each of the plurality of shared operand circuits comprise: a front end unit for determining a fixed point result by performing a fixed point addition or subtraction on a plurality of operands; and a floating point conversion unit for converting said fixed point result to a first floating point result.