Patent ID: 8711595

Claim:
A system, comprising: a controller comprising a first external terminal outputting an address or a command, a second external terminal related to a data, a third external terminal related to a strobe signal, a fourth external terminal outputting a first chip select signal, a fifth external terminal outputting a second chip select signal, and a sixth external terminal outputting a system clock; a first semiconductor memory device comprising a first external terminal receiving the address or the command, a second external terminal related to the data, a third external terminal related to the strobe signal, a fourth external terminal receiving the first chip select signal and a fifth external terminal receiving the system clock; and a second semiconductor memory device comprising a first external terminal receiving the address or the command, a second external terminal related to the data, a third external terminal related to the strobe signal, a fourth external terminal receiving the second chip select signal, and a fifth external terminal receiving the system clock; wherein the controller is configured to send an information specifying a length of a preamble of the strobe signal, and wherein the length of preamble of the strobe signal of each of the first and second memory devices can be set with a length shorter than one period of the system clock.