Patent ID: 7091773

Claim:
A limiting circuit comprises: an input transconductance stage operably coupled to convert an input voltage signal into an input current signal; a first resistive load operably coupled to convert the input current signal and a feedback current signal into an intermediate output voltage signal; an output transconductance stage operably coupled to convert the intermediate output voltage signal into an output current signal; a second resistive load operably coupled to convert the output current signal into an output voltage signal; a feedback transconductance stage operably coupled to produce the feedback current signal based on the output voltage signal; and a level limiting module operably coupled to limit at least one voltage level of the feedback transconductance stage; wherein: the input transconductance stage includes: a first differential transistor pair operably coupled to receive the input voltage signal and operably coupled to the first resistive load; and a first current sink operably coupled to sink current from the first differential transistor pair; the feedback transconductance stage includes: a second differential transistor pair operably coupled to receive the output voltage signal and operably coupled to the first resistive load; and a second current sink operably coupled to sink current from the second differential transistor pair, wherein the level limiting module is operably coupled to at least one of the second differential transistor pair and the second current sink; and the output transconductance stage includes: a third differential transistor pair operably coupled to receive the intermediate output voltage signal and operably coupled to the second resistive load; and a third current sink operably coupled to sink current from the third differential transistor pair.