Patent ID: 7034365

Claim:
An integrated circuit device comprising: an integrated circuit substrate; first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions; a first gate electrode on the first active region, the first gate electrode having a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region; a second gate electrode on the second active region; and an insulating layer on the first, second and third insulating regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode, the first gate electrode being free of a gate contact hole on the first portion, and a second gate contact hole on the second active region that exposes at least a portion of the second gate electrode; wherein the second gate electrode comprises a first portion on the second active region that extends on the third insulating region and a second portion at an end of the first portion on the third insulating region and wherein the second gate contact hole exposes at least a portion of the first portion of the second gate electrode, wherein the insulating layer further defines a third gate contact hole, and wherein the third gate contact hole exposes at least a portion of the second portion of the second gate electrode.