Patent ID: 6962294

Claim:
An integrated circuit comprising: security-critical circuit components arranged in a lower plane; data lines arranged in an upper plane, situated at least in part above the security-critical circuit components arranged in the lower plane, and connected to the security-critical circuit components; and a detector circuit that identifies an attack on the integrated circuit, comprising: a transmitting device that transmits predetermined test data into the security-critical circuit components arranged in the lower plane; a receiving device that receives the data processed by the security-critical circuit components arranged in the lower plane; and an evaluation device that compares the received data with expected data and that ascertains any non-correspondence, wherein the integrated circuit is operable in a normal mode and a test mode, the data lines carry the predetermined test data that is transmitted by the transmitting device and is processed by the security-critical circuit components in the test mode, and the data lines carry data that is processed by the security critical circuit components in the normal mode.