Patent ID: 8861669

Claim:
A stream clock recovery device, comprising: a sink device coupled to receive data from a link channel, the data including frequency clock data; the sink device comprising: a data extractor to extract the frequency clock data to obtain extracted frequency clock data; a data calibrator to adjust the extracted frequency clock data to obtain adjusted frequency clock data; a data translator having an integer and fraction value generator, generating an integer part and a fractional part of the adjusted frequency clock data; a phase locked loop (PLL) for synthesizing a recovered stream clock from the integer part and the fractional part of the adjusted frequency clock data, wherein the PLL is a pulse-swallow divider, and wherein the PLL with pulse-swallow divider further comprises: a first frequency divider for dividing an input clock ratio into a reference clock; a second frequency divider for dividing a clock output into an output clock, wherein the second frequency divider is configured to divide by multiple factors; a phase/frequency detector coupled to receive the reference clock and a feedback clock and to provide up and down signals; a charge pump coupled to receive the up and down signals; a low-pass filter coupled to an output signal of the charge pump; a voltage controlled oscillator coupled to receive the output signal of the charge pump for frequency synthesis to generate the clock output; and a third frequency divider and a prescaler coupled to the voltage controlled oscillator for fractional divisional control, wherein the third frequency divider is programmable and the third frequency divider generates the feedback clock; and a sigma-delta-modulator (SDM) for generating an integer divisor for the PLL by modulating the fractional part of the clock data.