Patent ID: 7586791

Claim:
A semiconductor memory device for storing data in an array of memory cells interconnected to bit lines and word lines, comprising: a charging circuit for charging the bit lines; an adjustment circuit for adjusting a pre-charging time charging the bit lines; and a voltage supply circuit for supplying a first internal voltage and a second internal voltage associated with increase and decrease of cell current flowing through the memory cells, said adjustment circuit including: a P-channel MOS transistor as a delay device responsive to the internal voltage to control a pulse width of an address transition detection signal for the array of memory cells and having a first gate electrode controllable to adjust the pulse width; an inverter for inverting an output from the P-channel MOS transistor; and an N-channel MOS transistor as a delay device responsive to the internal voltage to control the pulse width of an address transition detection signal for the array of memory cells and having a second gate electrode controllable to adjust the pulse width.