Patent ID: 7298192

Claim:
A computer-readable storage medium storing a computer-readable program/codes for executing a digital DLL control method for providing a delay to an input clock signal so as to equally divide a clock cycle T into N parts (N being an integer), said digital DLL control method comprising: N first variable delay steps each of which is formed of an arbitrary number of unit delay buffers connected in series with one another; N second variable delay steps each of which is connected with the last stage of said first variable delay sections, each of said second variable delay sections being formed of an arbitrary number of unit delay buffers connected in series with one another; a phase comparison step of making a compare between the phase of said input clock signal and the phase of an output signal which is said input signal having been delayed while passing through all said first and second variable delay steps, and outputting a result of said comparison; and a delay control step of calculating a total number of unit delay buffers S required based on said phase comparison result, setting a quotient Q of S divided by N to be the number of unit delay buffers for each of said first variable delay steps, setting a remainder R of S divided by N to be a total number of unit delay buffers for said second variable delay steps, and allocating R to said second variable delay steps, respectively.