Patent ID: 8912657

Claim:
A semiconductor device comprising: a semiconductor substrate; a lower insulating layer laminated on the semiconductor substrate; a lower conductive portion embedded in the lower insulating layer; a first upper insulating layer laminated on the lower insulating layer, the first upper insulating layer having a first layer and a second layer laminated in this order from the lower insulating layer; an upper conductive portion embedded in the first upper insulating layer such that the upper conductive portion reaches an upper surface of the lower insulating layer through the first and second layers; a first upper dummy wire embedded in the first upper insulating layer such that the first upper dummy wire reaches an upper surface of the lower insulating layer through the first and second layers; a lower dummy wire disposed below the first upper dummy wire with the first upper dummy wire over the lower dummy wire in plan view, the lower dummy wire electrically connected to the first upper dummy wire; a second upper insulating layer laminated on the first upper insulating layer; and an upper wire disposed above the first upper dummy wire with the upper wire over the first upper dummy wire in plan view.