Patent ID: 8530247

Claim:
A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate comprising an active region and one or more moat regions, wherein the one or more moat regions comprise an oxide disposed within one or more trenches, and wherein a step having a step height is defined between a top surface of the active region and a top surface of the one or more moat regions; measuring the step height; after measuring the step height, forming a photoresist layer over the semiconductor substrate; determining a modeled step height offset for a given photoresist pattern critical dimension for patterning of the photoresist layer as an ion implantation mask, wherein the modeled step height offset is determined from the measured step height and a predetermined relationship between variation in step height and variation in the given critical dimension; determining a dosage of energy to pattern the photoresist layer with the given critical dimension, wherein the determination is made using the modeled step height offset; and patterning the photoresist layer with the determined dosage of energy to form the ion implantation mask.