Patent ID: 8169828

Claim:
A method comprising at least one of: providing a floating gate over a semiconductor substrate including an N-well region and below a bit line, a word line below said floating gate, a common source below said word line, and a control gate connected to said floating gate by a contact through a dielectric; programming by applying a preset programming voltage to said common source and said N-well region, at least one of grounding and floating said control gate, and grounding said word line and the bit line; erasing by at least one of floating and grounding said word line, applying a preset erase voltage to said control gate, and grounding said N-well, said bit line and said common source; and reading by at least one of grounding and floating said control gate, applying a preset read voltage to said N-well and said common source, grounding said word line, and applying a preset drain voltage to said bit line.