Patent ID: 7485943

Claim:
A dielectric isolation type semiconductor device including a dielectric isolation type substrate, said dielectric isolation type substrate comprising: a support substrate; an embedded dielectric layer formed on an entire area of a first principal plane of said support substrate; and a semiconductor substrate of a first conductive type having a low impurity concentration being laminated on said support substrate through said embedded dielectric layer; wherein said semiconductor substrate comprises: a first semiconductor region of a first conductive type having a high impurity concentration that is selectively formed; a second semiconductor region of a second conductive type having a high impurity concentration that is arranged so as to surround said first semiconductor region in a manner spaced a predetermined distance from an outer peripheral edge thereof; a first main electrode that is joined to a surface of said first semiconductor region; and a second main electrode that is joined to a surface of said second semiconductor region; wherein said dielectric isolation type semiconductor device comprises: a first dielectric portion that is arranged adjacent to said embedded dielectric layer in a manner so as to surround a region of said support substrate that is superposed on said first semiconductor region in a direction of lamination thereof; and a wire that is connected with said first main electrode.