Patent ID: 7124390

Claim:
A method for generating through electronic data processing at least one split power plane of a multi-layer printed circuit board (PCB), comprising: (a) creating a printed circuit board outline; (b) determining associated locations of a plurality of components within the PCB outline; (c) creating a power fanout that represents an electrical power distribution to each of the plurality of components, the power fanout supporting a plurality of electrical potentials; (d) creating a split plane wireframe comprising: (i) generating through electronic data processing a plurality of initial voltage wireframes; (ii) generating through electronic data processing an enhanced set of voltage wireframes specifying trace paths which account for stored current requirements of associated components and have no or a reduced quantity of crossover, a crossover corresponding to an intersection of different voltage wireframes, the trace paths specified by the enhanced set of voltage wireframes including at least one new trace path not included in the plurality of initial voltage wireframes; and (iii) determining through electronic data processing a trace width for each segment of the split plane wireframe in accordance with the stored current requirements of the associated components; and (e) creating a first split power plane from the split plane wireframe, the first split power plane comprising a first constituent plane associated with a first voltage and a second constituent plane associated with a second voltage.