Patent ID: 7852248

Claim:
A Sigma-Delta analog-to-digital converter (ADC) having at least one stage with at least one input and at least one output comprising: an operational amplifier having a first and second input nodes and being responsive to at least one analog input and operative to generate an output; at least one input resistor coupled between one of the inputs of the ADC stage and the first input node of the operational amplifier; at least one integration capacitor coupled between at least one of the outputs of the ADC stage and the first node of the operational amplifier, the integration capacitor being discharged during integration cycle; at least one feedback capacitor having two ends with one end coupled to an alternating current (AC) ground; and at least one variable resistor having a first programmably alterable resistance and being coupled at one end to the first node and at the other end to the other end of the feedback capacitor, wherein when voltage is applied at the at least one analog input, at the outset of the integration time, the first programmably alterable resistance is programmed to a maximum value and reduced during the remainder of the integration time and programmed to substantially zero at the end of the integration time.