Patent ID: 8062919

Claim:
A method for building an integrated circuit using a conventional BiCMOS process, the conventional BiCMOS process comprising extensive use of planarization techniques, the method comprising the steps of: manufacturing, using the conventional BiCMOS process, a phototransistor having a base including an SiGe base layer of a pre-determined germanium composition and a thickness of more than 65 nm and less than about 90 nm; said phototransistor being comprised of a number of active regions, each active region, except a bottom active region, vertically disposed over another active region; coupling a transimpedance amplifier (TIA) to the phototransistor; configuring the TIA to receive an output directly from the phototransistor; configuring a capacitor between a collector of the phototransistor and an input to the TIA; said capacitor reducing an effect of collector-substrate junction on bandwidth; and configuring the phototransistor and the TIA on a silicon substrate.