Patent ID: 8634234

Claim:
A method of manufacturing a magnetic random access memory (MRAM) cell comprising: forming a plurality of diffusion regions and a transistor gate, collectively defining an access transistor, in a silicon substrate; forming a first set of plurality of ILD layers on top of the access transistor with each layer of the first set of plurality of ILD layers being formed on top of a previous layer of the first set of plurality of ILD layers; forming a hard-to-etch metal layer on top of a top most one of the first set of plurality of ILD layers; forming an MRAM area definition mask on a portion of the top of the hard-to-etch metal layer and covering a first metal that is in close proximity with the bit line and the bit line, the MRAM area definition mask defining an MRAM area where MRAM is to be formed; forming a second set of plurality of ILD layers on top of the first set of plurality of ILD layers with each of the layers of the second set of plurality of ILD layers being formed on top of a previous layer of the second set of plurality of ILD layers; etching to remove a portion of the second set of plurality of ILD layers that are on top of the hard-to-etch metal layer defined as the MRAM area; etching the hard-to-etch metal layer; and forming a magneto tunnel junction (MTJ) on top of the first set of plurality of ILD layers and substantially on top of the first metal and in the MRAM area.