Patent ID: 7902862

Claim:
A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure comprising: a first network of pipeline registers including a first plurality of pipeline registers, a second plurality of pipeline registers, and a third plurality of pipeline registers; first one or more connectors selectively joining a first select circuit to the first plurality of pipeline registers responsive to at least one first select signal, the first select circuit including a first plurality of logic circuits and a first plurality of special-purpose circuits; second one or more connectors selectively joining the first plurality of pipeline registers to the second plurality of pipeline registers responsive to at least one second select signal; third one or more connectors selectively joining the second plurality of pipeline registers to the third plurality of pipeline registers responsive to at least one third select signal; and fourth one or more connectors selectively joining the third plurality of pipeline registers to a second select circuit responsive to at least one fourth select signal, the second select circuit including a second plurality of logic circuits and a second plurality of special-purpose circuits.