Patent ID: 7812633

Claim:
A programmable logic device, comprising a plurality of logic blocks organized in an array, each of the logic blocks including logic elements, a plurality of the logic elements including: an N-stage look up table (LUT) structure having configuration bit inputs and a LUT output; dedicated hardware for performing a non-LUT logic function and for generating a non-LUT logic function output, wherein the non-LUT logic function is one of the following: addition, subtraction, multiplication, division, and digital signal processing; and an over-ride element coupled to the LUT and configured to selectively force a stage within the N stage look up table to select either one or more of the configuration bit inputs or the non-LUT logic function output so that the selected one or more of the configuration bit inputs or the non-LUT logic function output is provided at the LUT output, wherein the over-ride element comprises a register and a configuration random access memory (RAM) bit that allows a user to selectively enable or disable the over-ride function.