Patent ID: 7864596

Claim:
A flash device comprising: one or more sector configure registers that select a decoding scheme for a first region and a second region in the flash device; the first region comprising a plurality of single program and erase entities comprising two adjacent dual bit physical memory cells, the first region being programmed and erased to a high voltage state or a low voltage state on a basis of the single program and erase entity; and the second region comprising a plurality of dual bit memory cells, the second region being erased to a low voltage state on a sector basis, wherein the single program and erase entities in the first region are programmed and erased by applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground; or applying a hot-hole-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.