Patent ID: 7490306

Claim:
A method for designing a distributed capacitor bank for a power supply system to suppress noise below a target impedance Z T , where multiple power supplies and multiple clock frequencies may be provided on the board and the method steps are repeated for each power supply voltage and clock frequency combination, comprising: grouping electrical circuits on the board into groups that are powered by the same power supply voltage and driven at the same clock frequency and for each group; determining an aggregate capacitance C LOAD for the group; determining a maximum transient current I MAX generated by the group of electronics powered by the same power supply voltage and driven at the same clock frequency; determining a target impedance Z T required of the power supply voltage for suppression of noise from the group of electronics powered by that power supply voltage and driven at the same clock frequency; identifying a fundamental frequency F FUND corresponding to the clock frequency, the third harmonic F 3rd , and a high frequency noise F H correlated to an edge transition time; plotting the identified frequencies on an impedance vs. frequency chart along with the target impedance Z T ; determining a capacitor component C 1 , C 2 and C 3 with a frequency corresponding to each of the frequencies F FUND , F 3rd , and F H and plotting capacitors C 1 , C 2 and C 3 onto the impedance vs. frequency chart; determining the plane capacitance C PLANE for the particular board material used for the power supply and electrical circuit and plotting C PLANE on the impedance vs. frequency chart; determining the multiples of C 1 , C 2 and/or C 3 needed to support the capacitance C LOAD ; analyzing intersecting points of the capacitor component frequency plots for C 1 , C 2 , C 3 and C PLANE to determine whether all intersecting points occur below the target impedance Z T ; and determining that a distributed capacitor bank from the identified capacitor components is viable to suppress noise in the power supply below threshold Z T if all intersecting points occur below target impedance Z T and if all intersecting points are not below the target impedance retaining capacitor components, C 1 , C 2 and C 3 in any subsequent iterative determination of additional capacitor components.