Patent ID: 8756545

Claim:
A delay time calculating apparatus for calculating a delay time of nets within a circuit included in design data, the delay time calculating apparatus comprising: a processing unit configured to perform a process including first selecting a first delay calculating procedure to calculate the delay time of a net when the net satisfies a first condition that is determined from logical information of the circuit; when the first delay calculating procedure is not selected by the first selecting, second selecting the first delay calculating procedure to calculate the delay time of the net when the net satisfies a second condition that is determined from physical information of the circuit, and selecting a second delay calculating procedure to calculate the delay time of the net when the net does not satisfy the second condition; and calculating the delay time of the net by one of the first and second delay calculating procedures selected by one of the first and second selecting, wherein the first delay calculating procedure has a calculation accuracy higher than that of the second delay calculating procedure.