Patent ID: 7534707

Claim:
A method of fabricating a MOS transistor, the method comprising: defining an active region in a semiconductor substrate; forming a first layer on the surface of the substrate; forming a second layer on the first layer; forming a groove that penetrates the second layer and the first layer, wherein a width of the groove in the first layer is greater than a width of the groove in the second layer so as to form a pair of undercut regions in the first layer; and forming a gate pattern on the active region and in the groove, the gate pattern having a first lateral protrusion extending from a lower portion of a first sidewall of the gate pattern and a second lateral protrusion extending from a lower portion of a second sidewall of the gate pattern so as to provide a gate pattern having an inverted T-shape, the first and second lateral protrusions filling the pair of undercut regions; forming a drain region in the substrate comprising a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region that is deeper than the first lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region; and forming a source region in the substrate comprising a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region that is deeper than the first lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region.