Patent ID: 8195441

Claim:
A system configured for hardware co-simulation involving a processor, disposed within a programmable integrated circuit (IC), and communicating with a host processing system executing a circuit simulation involving the processor, the bus proxy system comprising: a bus proxy comprising a primary slave disposed within the programmable IC and coupled to the processor via a bus, wherein the primary slave is configured to operate at a speed of, and is synchronized with, the bus; a hardware co-simulation interface disposed within the programmable IC, wherein the hardware co-simulation interface is coupled to the bus proxy and is coupled to the host processing system via a communication link, wherein the hardware co-simulation interface is configured to buffer simulation data from the bus proxy and the host processing system; and a secondary slave configured to execute with the host processing system at a simulation speed that is asynchronous to the speed of the bus, wherein the secondary slave is configured to read data from, and write data to, the hardware co-simulation interface over the communication link, and communicate with at least one high level modeling system (HLMS) block executing within the circuit simulation, wherein the primary slave is configured to exert a slave wait signal on the bus responsive to detecting a bus request from the processor specifying an address corresponding to the HLMS block within the host processing system.