Patent ID: 8739090

Claim:
A computer-implemented method, comprising: running a first emulation cycle for a circuit design under test to generate a first plurality of emulation bits representing waveform data captured from at least one net of the circuit design under test at a first time; organizing the first plurality of emulation bits into a first plurality of emulation bytes; running a second emulation cycle for the circuit design under test to generate a second plurality of emulation bits representing waveform data captured from the at least one net of the circuit design under test at a second time; organizing the second plurality of emulation bits into a second plurality of emulation bytes; comparing the first plurality of emulation bits with the second plurality of emulation bits to generate a plurality of result bytes containing information about which emulation bits have changed value from the first emulation cycle to the second emulation cycle; calculating a status byte containing information about which of the second plurality of emulation bytes contain emulation bits that have changed value; and compressing together the status byte and one of: any one or more emulation bytes of the second plurality of emulation bytes containing bits that have changed value; or any one or more result bytes corresponding to the any one or more emulation bytes.