Patent ID: 7326985

Claim:
A memory cell formed on a substrate, comprising: a trench capacitor; and a select transistor, comprising: a diffusion region forming a source/drain electrode of the select transistor; a bit-line contact formed in an insulator layer and comprising a filling comprising at least one of a metal and a metal alloy, wherein the bit-line contact connects the source/drain electrode to an associated bit line; and a doped region formed within the source/drain electrode, wherein the doped region is completely surrounded by the source/drain electrode except for a surface to contact the filling of the bit-line contact, at least a portion of the source/drain electrode disposed between the doped region and the substrate preventing contact between the doped region and the substrate, the doped region comprising a locally limited electrically conductive contact layer which is formed substantially underneath the bit-line contact in the diffusion region and which has substantially no lateral migration underneath the insulator layer adjoining the bit-line contact.