Patent ID: 8564065

Claim:
An integrated circuit comprising: a first pad disposed above a surface of a substrate; a first metal oxide semiconductor (MOS) transistor of the substrate and of a first type, the first MOS transistor including a gate, a source, and a drain, the drain electrically connected to the first pad and the source electrically connected to a first supply voltage; a second MOS transistor of the substrate and of a second type opposite the first type, the second MOS transistor including a gate, a source, a drain, and a body, the gate configured to receive a control signal and the drain electrically connected to the gate of the first MOS transistor; a third MOS transistor of the substrate and of the first type, the third MOS transistor including a gate, a drain, a source, and a body, the gate configured to receive a bias signal, the drain electrically connected to a second supply voltage, the source electrically connected to the source of the second MOS transistor, and the body electrically connected to a first reference voltage; and a fourth MOS transistor of the substrate and of the first type, the fourth MOS transistor including a gate, a drain, and a source, the gate electrically connected to the control signal and the drain electrically connected to the gate of the first MOS transistor; wherein the body of the second MOS transistor is electrically connected to the source of the third MOS transistor so as to prevent a current flowing from the drain of the second MOS transistor to the second supply voltage through the body of the second MOS transistor when a transient signal event is received on the first pad.