Patent ID: 8006143

Claim:
A semiconductor memory device comprising: n first memory blocks, each of the n first memory blocks being used when determined that each of the n first memory blocks is normal; a second memory block that is used as an alternative of one of the n first memory blocks when determined that the second memory block is normal and that the one of the n first memory blocks is abnormal; n write latches that store n write data respectively; n write selectors that write the n write data stored in the n write latches into the n first memory blocks respectively according to an instruction; a first circuit that writes one of the n write data stored in one of the n write latches into the second memory block; and n read selectors that receive the n write data stored in the n first memory blocks by, receive the one of the n write data stored in the second memory block, and select n data from the received n write data and the received one of the n write data according to the instruction; a second circuit that outputs a data based on the one of the n write data stored in the second memory block; n first read latches that store the selected n data respectively; and a second read latch that stores the outputted data.