Patent ID: 7436710

Claim:
A memory device, comprising: a p-doped substrate; a plurality of electrically-conductive bit lines extending along a bit line direction; a plurality of electrically-conductive word lines extending along a word line direction; a plurality of electrically-conductive control gate lines extending along said word line direction; and a plurality of memory cells arranged respectively along said bit lines and said word lines, wherein each memory cell comprises: a program/erase PMOS transistor including a first gate, and first and second P+ regions formed within an n-doped well which, in turn, is formed within said p-doped substrate, wherein said first P+ region is electrically connected to a corresponding bit line; an access PMOS transistor including a second gate, and third and fourth P+ regions formed within said n-doped well, wherein said third P+ region is electrically connected to said second P+ region of said program/erase PMOS transistor, and said second gate is electrically connected to a corresponding word line; and a control gate NMOS transistor formed in a p-doped pocket which, in turn, is formed within said n-doped well, wherein said control gate NMOS transistor comprises a third gate, and first and second N+ regions formed within said p-doped pocket, wherein said first and second N+ regions are electrically connected to a corresponding control gate line, and said third gate is electrically connected to said first gate of said program/erase PMOS transistor to form a floating gate.