Patent ID: 7969779

Claim:
An integrated circuit device comprising: a memory cell array including: a plurality of bit lines; a plurality of bit line segments, wherein at least two bit line segments are associated with each bit line and wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line; a plurality of word lines; and a plurality of memory cells, wherein each memory cell stores at least two data states and includes a transistor, wherein the transistor includes: a first region coupled to an associated bit line segment; a second region; a body region disposed between the first region and the second region; and a gate coupled to an associated word line; wherein: (i) a first group of memory cells is coupled to a first bit line via a first bit line segment, (ii) a second group of memory cells is coupled to the first bit line via a second bit line segment, (iii) a third group of memory cells is coupled to a second bit line via a third bit line segment, and (iv) a fourth group of memory cells is coupled to the second bit line via a fourth bit line segment; a plurality of isolation circuits, wherein each isolation circuit is associated with a bit line segment and wherein each isolation circuit is disposed between the associated bit line segment and the associated bit line thereof, and includes a first transistor including: (i) a first region coupled to the associated bit line, (ii) a second region coupled to the associated bit line segment, (iii) a body region disposed between the first region and the second region, and (iv) a gate configured to receive a control signal, wherein: a first isolation circuit is disposed between the first bit line segment and the first bit line, a second isolation circuit is disposed between the second bit line segment and the first bit line, a third isolation circuit is disposed between the third bit line segment and the second bit line, and a fourth isolation circuit is disposed between the fourth bit line segment and the second bit line; a plurality of clamp circuits, wherein (i) each clamp circuit is associated with a bit line segment and, (ii) when enabled, couples a predetermined voltage to the associated bit line segment; and data sense circuitry, coupled to the first and second bit lines, to sense data states stored in selected memory cells of the first, second, third and fourth groups of memory cells.