Patent ID: 7848477

Claim:
A shift register, comprising: a plurality of shift register units substantially cascaded, each controlled by a first clock signal and a second clock signal opposite to each other for generating an output signal, wherein the output signal is activated periodically, and each of the shift register units comprises: a first switch device for providing the output signal through an output node; a first driving device for driving the first switch device according to a first input signal to activate the output signal; a second driving device, coupled to a first voltage signal, for providing the first voltage signal, according to the first clock signal, to drive the first switch device and de-activate the output signal; and a second switch device, coupled to a second voltage signal, for providing the second voltage signal to the output node, according to the second clock signal, when the first switch device de-activates the output signal, wherein a level of the first voltage signal is lower than a level of the second voltage signal.