Patent ID: 7986160

Claim:
A programmable logic device (PLD), comprising: at least one intellectual property (IP) block of the programmable logic device (PLD) whose performance is adjusted to meet at least one first performance characteristic, wherein the performance of the at least one intellectual property (IP) block is adjusted by changing a supply level of the at least one intellectual property (IP) block and by adjusting at least one body bias level of the intellectual property (IP) block; and at least one input/output (I/O) block of the programmable logic device (PLD) whose performance is adjusted to meet at least one second performance characteristic, wherein the performance of the at least one input/output (I/O) block is adjusted by changing a supply level of the at least one input/output (I/O) block and by adjusting at least one body bias level of the input/output (I/O) block.