Patent ID: 8467214

Claim:
A semiconductor device comprising: a plurality of memory cells including a first memory cell and a second memory cell; a first word line for a first port electrically connected to the first memory cell; a second word line for a second port electrically connected to the first memory cell; a third word line for the second port electrically connected to the second memory cell; a fourth word line for the first port electrically connected to the second memory cell; a first bit line for the first port electrically connected to the first memory cell and the second memory cell; a second bit line for the second port electrically connected to the first memory cell and the second memory cell; a first access transistor of the first memory cell electrically connected to the first word line and the first bit line; and a second access transistor of the first memory cell electrically connected to the second word line and the second bit line, wherein a gate of the first access transistor is formed over a semiconductor substrate, wherein the first bit line and the second bit line are formed over the gate of the first access transistor, wherein the first to fourth word lines are formed over the first and second bit lines, wherein the second word line is arranged between the first word line and the third word line, and wherein the third word line is arranged between the second word line and the fourth word line.