Patent ID: 7532446

Claim:
An electro static discharge (ESD) protection circuit, comprising: a first power line; a second power line; a pair of p-n junction diodes coupled between the first power line and the second power line, wherein the pair of p-n junction diodes has a signal input end arranged to receive an input signal; and an ESD clamp circuit coupled between the first power line and the second power line, the ESD clamp circuit comprising: a transistor having a drain electrically connected to the first power line, a source and a substrate electrically connected to the second power line, and a gate, wherein the drain of the transistor has no silicide block disposed thereon, the drain of the transistor has a silicide layer disposed thereon, and the silicide layer remains intact after disposed on the drain of the transistor; and a coupling capacitor coupled between the first power line and the gate of the transistor.