Patent ID: 8598925

Claim:
A frequency verification circuit comprising: an input port for receiving an input signal; a phase frequency difference detector for determining a difference in phase and frequency between the input signal and a feedback signal and for providing a control signal based on the detected difference; a voltage controlled crystal oscillator for producing an output signal based on the control signal; a feedback loop including a feedback divider for frequency dividing the output signal by a factor R to produce the feedback signal, the feedback divider being programmable to a plurality of values of the factor R to correspond to a plurality of different test frequencies; a frequency verification unit for verifying that the input signal is substantially at a respective test frequency based on whether the output signal is within a pre-assigned frequency accuracy range; and a resolution bandwidth control circuit (RBCC) coupled between the phase frequency difference detector and the voltage controlled crystal oscillator for scaling the control signal by a scaling factor and for providing an offset to the control signal to adjust the range of locking frequencies; wherein for a given combination of values of N and R, the output signal settles within the pre-assigned frequency accuracy range when the input signal is at a frequency within a range of locking frequencies; and wherein the scaling factor has a magnitude of less than unity to reduce the range of locking frequencies.