Patent ID: 7590295

Claim:
A data processor on a chip for use with a memory and for encoding a first series of image data and decoding a second series of encoded image data for multi-streams, the data processor comprising: a central processing unit; a direct memory access controller, a first port for inputting the first series of image data; a second port for inputting the second series of encoded image data; an interface for data read/write operation from and to a memory area of the memory; an encoding/decoding circuit which selectively performs encoding of the first series of image data written into the memory area and decoding of the second series of encoded image data; and a plurality of registers which provide an instruction of processing to the encoding/decoding circuit, wherein the encoding/decoding circuit performs encoding of the first series of image data and decoding of the second series of encoded image data on a time division basis in each series in accordance with the instruction from the plurality of registers.