Patent ID: 7124336

Claim:
A method of using a computer system to perform a defect analysis of memory modules, the method which comprises: a) providing the computer system with at least one data defect memory, at: least one address defect memory, and a test program; b) providing a memory module including a memory space with a plurality of memory cells for storing information items, a plurality of physical data lines, the data lines being numbered by consecutive numbers, the data lines being connected to the memory cells for transferring information items written to and read from the memory cells, and a plurality of address lines for addressing the plurality of the memory cells; c) dividing the memory cells into a plurality of parts of the memory space, each memory cell of one part of the memory space being uniquely determined by an address, one address determining one memory cell in each of one of the plurality of the parts of the memory space; d) connecting all memory cells of one part of the memory space to one data line; e) forming the data defect memory as a list for storing the numbers of data lines that are connected to defective ones of the plurality of the memory cells; f) forming the address defect memory as a mapping of the memory space or of an area of the memory space and initially emptying the address defect memory, wherein the address defect memory having a storage capacity being less than the memory module; g) connecting the computer system to the memory module; h) writing information items to the plurality of the memory cells and subsequently reading-out information items contained in the plurality of the memory cells; i) comparing the written information items with the read information items to determine if there are deviations; j) continuing with steps k) to o) if at least one deviation was detected, otherwise ending the method; k) storing, into the data defect memory, numbers of ones of the plurality of the data lines that are connected to ones of the plurality of the memory cells in which the deviations were determined in step j); l) repeatedly writing information items to the plurality of the memory cells and subsequently reading-out information items contained in the plurality of the memory cells; m) comparing the written information items used in step l) with the information items obtained in step l) to determine if there are deviations; n) storing, in the address defect memory, a property information item as to whether the memory cell is defect-free or defective for each of the memory dells checked in step in); and o) determining addresses of defective memory cells in the memory space from the address defect memory and determining ones of the plurality of the data lines that are connected to defective ones of the plurality of the memory cells from information items in the data defect memory.