Patent ID: 7177276

Claim:
An apparatus for buffering packets, each packet having a header portion, an optional corresponding tail portion, and a class of service indicator, the apparatus comprising: a buffer manager including: a buffer circuit for receiving packets from at least one of a pipelined switch and a switch fabric; a queue manager coupled to the buffer circuit and operable to direct packets to an address in the buffer circuit and enqueue the packets using the class of service indicator and a plurality of queues; a rate shaping circuit coupled to the queue manager, the rate shaping circuit maintaining a plurality of token buckets wherein each of the plurality of token buckets corresponds to a shaping queue, wherein the rate shaping circuit is operable to receive information from the queue manager indicating that a shaping queue is not empty, and combine the information from the queue manager with at least one bucket status value to determine from which of the plurality of queues a packet should be sent; and a dequeue circuit coupled to the queue manager and the buffer circuit, wherein the dequeue circuit uses the class of service indicator to dequeue the at least one of the packets to one of a second pipelined switch and the switch fabric.