Patent ID: 8359502

Claim:
A system on a chip comprising: A. a communications link including a serial test data in lead and a serial test data out lead; B. a port coupled to the communications link including the serial test data in lead and the serial test data out lead, and having a chip serial test data in lead, a chip serial test data out lead, and a select output lead; C. a first component separate from the port, the first component including an embedded TAP controller, the first component having a test data input coupled to the chip serial test data in lead, a component serial test data output lead, and an override output lead; D. override selection logic having an input connected to the select output lead, an input connected to the override output lead, and a master override output lead; E. multiplexer circuitry having a first input coupled to the chip serial test data in lead, a second input coupled to the component serial test data output, an output, and a control input; and F. gating circuitry having a first input connected to the select output lead, a second input connected to the override output lead, an input connected to the master override output lead, and an output connected to the control input of the multiplexer circuitry.