Patent ID: 7141473

Claim:
A method of fabricating a self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell, comprising: forming an insulating layer pattern having a substantially rectangular shape with two opposing sidewalls on a semiconductor substrate; forming an ONO layer including a lower oxide layer, a nitride layer and an upper oxide layer on the semiconductor substrate and the insulating layer pattern, the ONO layer having a uniform thickness; forming self-aligned etching spacers on both sidewalls of the insulating layer pattern; etching portions of the upper oxide layer and the nitride layer of the ONO layer on the insulating layer pattern using the self-aligned etching spacers as an etch mask; removing the self-aligned etching spacers; removing the upper oxide layer exposed by the removing of the self-aligned etching spacers and the lower oxide layer of the ONO layer on the semiconductor substrate; forming an oxide layer on a resultant structure on the semiconductor substrate; and forming a word line for a gate of the SONOS cell using the sidewalls of the insulating layer pattern as a sidewall for the word line.