Patent ID: 7368952

Claim:
An output buffer circuit comprising: an input terminal for receiving a input signal; a first output buffer section including complementary semiconductors and outputting a first output signal corresponding to said input signal; a second output buffer section including complementary semiconductors and connected in parallel with said first output buffer section, wherein said second output buffer section starts to output a second output signal corresponding to said input signal after said first output signal corresponding to said input signal reaches a reference voltage Von to decide whether an output voltage of said output buffer circuit is on-state or off-state; a first predriver section receiving said input signal and applying a first gate voltage to a control terminal of said first output buffer section; and a second predriver section receiving said input signal and applying a second gate voltage to a control terminal of said second output buffer section, wherein said first gate voltage crosses through a voltage level of a threshold voltage of said first output buffer section in response to a voltage change of said input signal before said output voltage of said output buffer circuit reaches said reference voltage Von in response to the voltage change of said input signal, and said second gate voltage crosses through a voltage level of a threshold voltage of said second output buffer section in response to the voltage change of said input signal after said output voltage of said output buffer circuit reaches said reference voltage Von in response to the voltage change of said input signal.