Patent ID: 7040946

Claim:
A method of manufacturing a plasma display panel including: a front substrate; a rear substrate arranged by a predetermined interval from the front substrate; a plurality of sustain electrodes arranged in parallel with each other on the front substrate; a plurality of data electrodes arranged in a direction perpendicular to the plurality of sustain electrodes on the rear substrate; and a plurality of barrier ribs arranged at a constant interval between the front substrate and the rear substrate to partition discharge cells; the method comprising: (a) forming a plurality of transparent electrodes in parallel with each other on the front substrate; (b) coating a black paste on a surface of the front substrate on which the plurality of transparent electrodes are formed, and drying the coated black paste; (c) exposing an area where a black layer is formed on an area extending from the transparent electrode in one discharge cell to a transparent electrode in an adjacent discharge cell via a non-discharge area between the discharge cells by using a first photomask; (d) coating a bus electrode paste on the exposed black layer and drying the coated bus electrode paste; (e) exposing an area where a bus electrode is formed on an area extending from a part of the black layer on the transparent electrode in the one discharge cell to a part of the black layer on the non-discharge area between the discharge cells with a portion of the bus electrode contacting the black layer formed on the non-discharge area having a width ranging from (⅛)L to (⅝)L, where L represents a width of the bus electrode, the exposing of the area where the bus electrode is formed being performed using a second photomask; (f) developing and annealing the exposed front substrate to form the black layer and the bus electrode; and (g) coating a dielectric paste on the surface of the front substrate on which the black layer and the bus electrode is formed, and drying the coated dielectric paste.