Patent ID: 7512848

Claim:
A clock and data recovery circuit comprises: a latch operably coupled to latch bits of a digital stream of data based on a recovered clock to produce latched bits; a detection module operably coupled to produce a phase representative pulse stream based on the latched bits; a clock recovery module operably coupled to produce the recovered clock based on the phase representative pulse stream; and a compensating module operably coupled to adjust biasing of the latch based on operating parameter changes of the clock and data recovery circuit, wherein the compensating module includes a property variation sensing module operably coupled to sense temperature and process variations of components of the clock and data recovery circuit to produce a temperature and process compensation signal; a supply voltage sensing module operably coupled to sense variations of the supply voltage of the clock and data recovery circuit to produce a supply voltage compensation signal; and a summing module coupled to sum the temperature and process compensation signal and the supply voltage compensation signal to produce the adjusting bias current.