Patent ID: 8455319

Claim:
A manufacturing method of vertical transistor for random-access memory, comprising: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure around the active region; etching the central portion of the active region; forming a gate dielectric layer and a positioning gate on the etched portion of the active region; forming a word line in contact with the positioning gate and substantially perpendicular thereto in the etching direction; forming spacing layers on the outer surfaces of the word line; respectively forming an n-type region and a p-type region for the active region on opposite sides of the word line by ion implantation; coveringly disposing an insulating layer on the formed structure with an insulating layer; removing the insulating layer partially to form a source line pattern by a self-align contact (SAC) process; forming two floating bodies by epitaxial deposition and implanting with ions to form an n-type floating body on the n-type region of the active region and a p-type floating body on the p-type region of the active region; covering the formed structure with an insulating layer; removing the insulating layer corresponding to the n-type floating body by the self-align contact process; forming a source line perpendicular to the word line and connecting to the n-type floating body; covering the formed structure with an insulating layer and removing the insulating layer corresponding to the p-type floating body by the self-align contact process; and forming a bit line perpendicular to the source line and connecting to the p-type floating body.