Patent ID: 7672164

Claim:
A semiconductor integrated circuit device comprising: a first memory cell array which includes memory cells arranged in a matrix, each memory cell including a first and a second select transistor and a plurality of first memory cell transistors which current paths are connected in series between the first and second select transistors, each of the first memory cell transistors having a first stacked gate including a first floating gate formed on a semiconductor substrate with a first gate insulating film interposed therebetween and a first control gate formed on the first floating gate with a first inter-gate insulating film interposed therebetween; a first row decoder which includes a first MOS transistor and which applies a positive voltage to the gate of the first memory cell transistor in a write operation and applies 0V to the gate of the first memory cell transistor in an erase operation; a second memory cell array which includes memory cells arranged in a matrix, each memory cell including a third select transistor and a second memory cell transistor which has a current path connected to a current path of the third transistor in series, each of the second memory cell transistors having a second stacked gate including a second floating gate formed on the semiconductor substrate with a second gate insulating film interposed therebetween and a second control gate formed on the second floating gate with a second inter-gate insulating film interposed therebetween; and a second row decoder which includes a second MOS transistor and which applies a positive voltage to the gate of the second memory cell transistor and a negative voltage to the gate of the third select transistor in the write operation and applies a negative voltage to the gate of the second memory cell transistor in the erase operation, each of the first and second MOS transistors having a gate insulating film of the same film thickness.