Patent ID: 8510496

Claim:
A storage system for storing data on a low-latency random read memory (LLRRM) device, the storage system comprising: the LLRRM device comprising a plurality of memory banks having an overall LLRRM address range, each memory bank having an associated LLRRM address range, each memory bank being simultaneously and independently accessible for accessing data stored on the memory bank; a storage operating system engine configured for: allocating a plurality of request-queuing data structures comprising a plurality of read-queuing data structures for storing only read requests and a single write-queuing data structure for storing only write requests, each read-queuing data structure being assigned to a memory bank in the plurality of memory banks and being associated with the LLRRM address range of the assigned memory bank, the single write-queuing data structure being assigned to the plurality of memory banks and being associated with the overall LLRRM address range of the plurality of memory banks; receiving a plurality of access requests at requested LLRRM addresses in the LLRRM device, each access request comprising a read or write request type; for each received access request, selecting a request-queuing data structure for storing the received access request based on the requested LLRRM address and the request type, wherein a read-queuing data structure is selected for storing only read requests for its associated LLRRM address range and the single write-queuing data structure is selected for storing only write requests for the overall LLRRM address range; and sending, to the LLRRM device, access requests from the plurality of request-queuing data structures by sending read requests from the plurality of read-queuing data structures and sending at least one write request from the single write-queuing data structure.