Patent ID: 8134400

Claim:
A semiconductor circuit having a first potential as a first reference potential and a second potential as a second reference potential, the first potential being different from the second potential, for driving and controlling a semiconductor switching device that is driven with the second potential, the semiconductor circuit comprising: a level shift circuit having an input section coupled to a plurality of output sections at a first node and a second node to output through each output section a main command signal including one of a pulse-shaped ON command signal and a pulse-shaped OFF command signal relative to the second potential as the second reference potential, in response to an input of an activation signal including one of a pulse-shaped ON signal and a pulse-shaped OFF signal relative to the first potential as the first reference potential and that renders the semiconductor switching device into one of a conductive state and a non-conductive state; and a latch circuit that outputs a maintaining signal, in response to the main command signals output by the level shift circuit, to maintain the semiconductor switching device in one of the conductive state and the non-conductive state, wherein each output section is coupled between a third potential and one respective node of the nodes, and includes a level shift signal suppressor that, when one of the pulse-shaped ON command signal and the phase-shaped OFF command signal is generated at a first one of the plurality of output sections of the level shift circuit, prevents the other one of the pulse-shaped ON command signal and the pulse-shaped OFF command signal from being generated at a second one of the plurality of output sections, the level shift signal suppressors including a first switch having a first terminal, a second terminal, and a third terminal, and a second switch having a fourth terminal, a fifth terminal, and a sixth terminal, the first terminal and the fourth terminal being directly connected to the third potential, and the third terminal and the sixth terminal being directly connected to the respective node of the nodes, and wherein the level shift suppressors further include a first resistive element having a first end directly connected to the fifth terminal of the second switch and a second end directly connected to the third terminal of the first switch, and a second resistive element having a third end directly connected to the second terminal of the first switch and a fourth end directly connected to the sixth terminal of the second switch.