Patent ID: 7197042

Claim:
A router, comprising: a) a routing layer, said routing layer including a plurality of I/O ports for exchanging data with components external to said router; b) a switching layer to switch data packets between I/O ports of said routing layer, said switching layer including an array of cells in communication with said routing layer for permitting exchange of data packets between said array of cells and said routing layer; c) each cell including a memory for receiving a data packet from said routing layer: d) said routing layer including a controller to control release of a data packet toward a cell of said array at least in part on a basis of a degree of occupancy of the memory in said cell; wherein said routing layer further includes a memory for storing data packets for release to said switching layer, said controller controlling release of data packets from the memory of said routing layer; wherein the memory of said routing layer includes an area for storing data indicative of a degree of occupancy of the memory of said cell; wherein said controller is in communication with said memory to obtain access to the data indicative of a degree of occupancy of the memory of said cell, said controller controlling release of data packets from the memory of said routing layer at least in part on a basis of the data indicative of a degree of occupancy of the memory of said cell; wherein the memory of said routing layer includes a plurality of areas associated with respective cells of said array, each area operative to store data indicative of a degree of occupancy of the memory of a corresponding cell.