Patent ID: 7164288

Claim:
An electronic circuit with an array of programmable logic cells, each of the cells comprising: an input circuit with a plurality of logic inputs; an output circuit; a plurality of programmable logic units, coupled in parallel between the input circuit and the output circuit, the logic cell being configurable between a random logic mode and a multi-bit operand processing mode; wherein at least one of the programmable logic units comprises: a configurable look-up table circuit, having inputs coupled to receive the logic input signals from the input circuit and having an output; a controllable inverter/non-inverter circuit, having an input connected to the output of the look-up table circuit, and being controllable by an input carry signal; a first output node connected to receive the output of the inverter/non-inverter circuit, and coupled to the output circuit for providing a multi-bit operand processing mode output signal; and a second output node connected to receive the output of the look-up table circuit, for providing a random logic mode output signal.