Patent ID: 7154797

Claim:
A signal transmission system comprising: a write amplifier; a sense amplifier connected to the write amplifier via a data bus; and a semiconductor memory device for writing data from the write amplifier to the sense amplifier, the semiconductor memory device comprising a signal transmission line for transmitting data without requiring precharging for every bit, wherein when writing, at least during a portion of a period when a select signal for connecting said data bus to said sense amplifier is being supplied a bit line connected to said sense amplifier for amplification is disconnected from said sense amplifier, thereby allowing information on said data bus to be transferred at high speed into said sense amplifier, wherein said signal transmission line comprises a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of said plurality of switchable signal transmission lines; a readout circuit for eliminating an intersymbol interference component is connected to said signal transmission line; and an intersymbol interference component elimination circuit for reducing noise introduced when said signal transmission line is switched between said plurality of switchable signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when said signal transmission line is switched, wherein said at least one target unit is said sense amplifier for reading data out of a memory cell, and said readout circuit is a data bus amplifier having an intersymbol interference component elimination function.