Patent ID: 7636000

Claim:
A phase locked loop; comprising: a phase-frequency detector configured to compare phases of an input signal and a feedback signal to generate first and second control signals; and a loop filter including a pull-up resistor, a pull-down resistor and a capacitance unit, the capacitance unit being coupled to a coupling node between the pull-up resistor and the pull-down resistor, the loop filter configured to receive a first reference voltage to charge the capacitance unit through a path formed by the pull-up resistor to the capacitance unit, configured to receive a second reference voltage to discharge the capacitance unit through a path formed by the pull-down resistor to the capacitance unit, and configured to output a control voltage generated based on a charge amount of the charged capacitance unit, the first reference voltage being provided when the first control signal is inputted to the loop filter from the phase-frequency detector, the second reference voltage being provided when the second control signal is inputted to the loop filter from the phase-frequency detector, the second reference voltage being less than the first reference voltage, wherein the loop filter further comprises: a pull-up switch configured to be turned on based on the first control signal to provide the first reference voltage to the path formed by the pull-up resistor to the capacitance unit to charge the capacitance unit; and a pull-down switch configured to be turned on based on the second control signal to provide the second reference voltage to the path formed by the pull-down resistor to the capacitance unit to discharge the capacitance unit, and wherein the pull-up switch comprises; a pull-up p-channel metal oxide semiconductor (PMOS) transistor configured to be turned on based on a first inverted control signal that is an inverted signal of the first control signal; and a pull-up n-channel metal oxide semiconductor (NMOS) transistor having a drain coupled to a source of the pull-up PMOS transistor and a source coupled to a drain of the pull-up PMOS transistor, and configured to be turned on based on the first control signal.