Patent ID: 8107301

Claim:
A flash memory system comprising: a first memory which has at least a plurality of flash memory cells, each cell having a word line, connected in series, a first selection transistor having a first select gate line connected to one end of the plurality of memory cells and a second selection transistor having a second select gate line connected to another end of the plurality of memory cells; and a memory controller including: an interface configured to be connectable to an electric device and transfer first data to or from the first memory and a command from the device; a second memory which temporarily holds second data; and a processor unit configured to control writing the first data in the first memory, reading the first data from the first memory, temporarily holding the second data in the second memory, and writing, in the first memory, the second data held in the second memory, wherein when writing the second data, the processor unit does not select the word lines adjacent to the first select gate line and the second select gate line, and selects the word line not adjacent to the first select gate line and the second select gate line.