Patent ID: 7483299

Claim:
A semiconductor memory device, comprising: a substrate having a first conductivity type; a first region provided in the substrate, the first region having a second conductivity type; a second region provided in the substrate spaced from the first region, the second region having the second conductivity type; a channel region provided in the substrate and extending between the first and second regions; a first insulative layer including a first material provided on the channel region; a second insulative layer including a second material provided on the first insulative layer, the second insulative layer being configured to store a first charge in a first portion corresponding to a first bit and a second charge in a second portion corresponding to a second bit; a third insulative layer provided on the second insulative layer; a first conductive layer provided on the third insulative layer; a fourth insulative layer provided on the first conductive layer; and a second conductive layer provided on the fourth insulative layer.