Patent ID: 7062732

Claim:
A method of generating a pattern for a semiconductor device comprising: a layout pattern forming step of designing and arranging a layout pattern of a function element according to function information of a semiconductor chip; a space area detecting step of detecting a space area which has a portion overlapping a layout pattern of at least one power supply wiring in a different layer and in which no layout pattern exists in the same layer of the space area; a judging step of judging whether or not an MOS capacitor cell, the insulating film of which is a gate oxide film, can be arranged in the space area; a step of arranging the MOS capacitor cell in the space judged that the MOS capacitor cell can be arranged; and a wiring arrangement step of forming a wiring so that a gate conductor of the MOS capacitor cell can be connected to a first electric potential and a substrate can be connected to a second electric potential.