Patent ID: 7183825

Claim:
A circuit comprising a state-retentive flip-flop, the flip-flop comprising: input and output nodes; two latches, a master latch and a slave latch, each of the latches including a circuit element coupled in series with the input and output nodes, a first one of the latches being configured to retain a state of the flip-flop during a power managed mode in which power is decoupled from a second one of the latches; a switch controller coupled to receive a clock signal and a power gate indicator signal, the switch controller generating a first set of switch control values dependent upon the clock signal when the power gate indicator signal has a first value and generating a second set of switch control values independent of the clock signal when the power gate indicator signal has a second value; a first switch coupled between the input node and the master latch; and a second switch coupled between the master latch and the slave latch, wherein the switch controller is coupled to provide switch control signals to the first and second switches; and wherein: the master latch includes cross-coupled invertors and a third switch, one of the invertors and the third switch being coupled to the first switch, the third switch being coupled to receive a switch control signal from the switch controller; and the slave latch includes cross-coupled invertors and a fourth switch, one of the invertors of the slave latch and the fourth switch being coupled to the second switch, each of the invertors of the slave latch being coupled to the output node, the fourth switch being coupled to receive a switch control signal from the switch controller, wherein an input of the slave latch located between the second switch and the one of the invertors of the slave latch is not provided as feedback to the master latch during the power managed mode.