Patent ID: 7348640

Claim:
A memory comprising: a memory cell array region including a plurality of memory cells arranged in the form of a matrix a first selection transistor and a second selection transistor provided for the respective ones of said plurality of memory cells; a first impurity region functioning as an electrode partially constituting each said memory cell while functioning also as one of source/drain regions of said first selection transistor and said second selection transistor; a second impurity region functioning as the other one of said source/drain regions of said first selection transistor and said second selection transistor; and a word line provided on said memory cell array region along said first impurity region, wherein said first selection transistor and said second selection transistor share said second impurity region, a first gate electrode of said first selection transistor and a second gate electrode of said second selection transistor are provided integrally with each other by the same said word line and arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on a region formed with said memory cells and to intersect with said first impurity region on regions formed with said first selection transistor and said second selection transistor in plan view, and said first selection transistor and said second selection transistor divide said first impurity region.