Patent ID: 8621127

Claim:
A semiconductor device comprising: a plurality of processors formed over a single chip and including a plurality of a first type of processors disposed in a first layout region of the single chip in plan view and a plurality of a second type of processors disposed separately from the plurality of the first, type of processors in a second layout region of the single chip in plan view, each said first type of processor having a first architecture, and each said second type of processor having a second architecture which is different from the first architecture of said first type of processor; a first bus which is disposed in the first layout region of the single chip and to which each of the plurality of the first type of processors is coupled; a second bus which is disposed in the first layout region of the single chip and to which each of the plurality of the second type of processors is coupled; a first external bus interface to which the first bus is coupled; a second external bus interface to which the second bus is coupled; a plurality of first voltage supply lines arranged along one direction in the first layout region of the single chip in plan view with a space of a first width between adjacent ones of said first voltage supply lines, each said first voltage supply line having a second width in said one direction; and a plurality of second voltage supply lines arranged along said one direction in the second layout region of the single chip in plan view with a space of a third width, which is larger than the first width, between adjacent ones of said second voltage supply lines, each said second voltage supply line having a fourth width, which is smaller than the second width, in said one direction, wherein, in plan view, the first external bus interface is disposed at a first edge of the single chip and the second external bus interface is disposed at a second edge of the single chip different from the first edge, wherein the plurality of the first type of processors and the plurality of the second type of processors are controlled using separate clocks which differ in frequency or phase, wherein the first external bus interface is coupled to a first external bus and the second external bus interface is coupled to a second external bus, wherein the plurality of the first type of processors are configured to access the first external bus via the first bus and the first external bus interface and to access the second external bus via the first bus, the second bus, and the second external bus interface, and wherein the plurality of the second type of processors are configured to access the second external bus via the second bus and the second external bus interface.