Patent ID: 8269534

Claim:
A delay locked loop (DLL) circuit comprising: a delay circuit; a phase adjusting circuit configured to receive a clock signal output from the delay circuit, pass the clock signal through a N-divider and a replica path to create a N-divided delay signal, and detect phase information about an external clock signal in response to a rising edge and a falling edge of the N-divided delay signal, wherein N denotes a natural number; a first phase detector configured to detect the phase information about the external clock signal in response to the rising edge of the N-divided delay signal; a second phase detector configured to detect the phase information about the external clock signal in response to the falling edge of the N-divided signal; and a selector configured to output either an output signal of the list phase detector or an output signal of the second phase detector as a result of the detections, wherein; the N-divider is configured to divide a frequency of the clock signal by N to output a N-divided signal, and the delay circuit is configured to output the clock signal by adjusting a phase of the external clock signal in response to a result of the detection.