Patent ID: 7511552

Claim:
A system, comprising: a first circuit to operate based on a first voltage of a first power supply; a second circuit to operate based on a second voltage of a second power supply; a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply; a first set of sequentially coupled pull-up and pull-down sub-circuits of the level shifter circuit cross coupled to a second set of sequentially coupled pull-up and pull-down sub-circuits of the level shifter circuit to generate a positive feedback loop; an output node of the level shifter circuit coupled to a common node between the pull-up and the pull-down sub-circuits of the first set of sequentially coupled pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor having a gate contact coupled to an input of the second set of pull-up and pull-down sub-circuits, a source contact coupled to an input of the output inverter and a drain contact coupled to the second voltage; and a pull-down NMOS transistor having a gate contact coupled to the input of the second set of pull-up and pull-down sub-circuits, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.