Patent ID: 8533559

Claim:
A semiconductor recording device incorporating a multi-level nonvolatile memory storing a plurality of bits per memory cell and having physical blocks composed of a plurality of pages, wherein a plurality of said physical blocks are configured as one group, comprising: a first error correcting code (ECC) generator for adding an ECC parity extracted at a predetermined interval in inputted data and for generating a first ECC; a data distributor for distributing the first ECC generated by said first ECC generator to different physical blocks in the group in a predetermined size; a data writer for writing data distributed by said data distributor to the respective physical blocks of a group; a writing error detector for detecting, when writing to said nonvolatile memory in a page of the physical block, a writing error; an error flag generator for generating an error flag showing a possibility of the writing error with respect to a page of a cell that stores a plurality of bits, wherein respective bits of a page in which an error is detected by said writing error detector share a common cell of said nonvolatile memory; a data reader for reading data of a page in which the error flag is generated by said error flag generator and all data configuring the first ECC from the respective physical blocks; and a data recovering part for recovering data of a cell sharing page specified by said error flag generator from the data read by said data reader and writing the recovered data to a page of a physical block in which data is not previously written.