Patent ID: 8669637

Claim:
A method of manufacturing an integrated passive device system comprising: forming a first dielectric layer in direct contact with a semiconductor substrate; depositing a metal capacitor layer having a first segment and a second segment, each segment in direct contact with the first dielectric layer; depositing a silicide layer having a first portion and a second portion over the first dielectric layer and the metal capacitor layer, wherein: the first portion is in direct contact with the first dielectric layer between the first segment and the second segment, and the second portion is in direct contact with the second segment and the first dielectric layer, the second portion completely covering the second segment; forming a second dielectric layer having a first section and a second section over the metal capacitor layer, wherein: the first section is in direct contact with the first portion, the first section partially covering the first portion, and the second section is in direct contact with the second portion and the first dielectric layer, the second section partially covering the second portion; depositing a conductive layer over the second dielectric layer including: forming a top plate from the conductive layer for forming an integrated capacitor, forming a terminal for the integrated capacitor, forming a contact for an integrated resistor, forming a bridge for an integrated inductor, and forming an analog circuit by interconnecting the integrated capacitor, the integrated resistor, and the integrated inductor; applying a barrier layer over the conductive layer; and depositing a copper layer over the barrier layer.