Patent ID: 7068049

Claim:
A method of measuring a DUT comprising the steps of: providing a vector network analyzer having at least two measurement ports, measuring a reflection characteristic of a high reflect calibration standard at each measurement port, measuring forward and reverse reflection and transmission characteristics of a line calibration standard, measuring forward and reverse reflection and transmission characteristics of a source terminated thru calibration standard, measuring forward and reverse reflection and transmission characteristics of a locally terminated thru calibration standard, calculating error coefficients for said at least two measurement ports based upon results in said steps of measuring, calculating a shifted electrical length attributable to said calibration standards based upon results in said steps of measuring, connecting the DUT to the measurement ports, measuring s-parameters at the measurement ports, correcting for systematic errors in said s-parameters based upon said error coefficients to yield a corrected S-parameter matrix, and shifting a reference plane for each element of said corrected S-parameter matrix to coincide with a measurement reference plane wherein a shifted electrical length between said indirect pairs is calculated using load match and source match error coefficient terms, and Γ SA_portn Γ LA_portm = S 21 ⁢ _thru ⁢ _nm ⁢ S 12 ⁢ _thru ⁢ _nm wherein S 21 — thru — nm is equal to S 12 — thru — mn and an argument of both solutions for S 21 — thru — nm is fit to a straight line, the solution having a y-intercept closest to zero being a correct solution and a resulting argument of the correct solution being the electrical delay.