Patent ID: 7523230

Claim:
A controller for a memory device, the controller operatively connected to a plurality of memory channels, all or a subset of which are populated, comprising: a first memory to store a routine configured to determine a first number of memory channels available to the controller and determine a second number of the first number of memory channels which are populated, wherein a memory channel is populated if it includes at least one memory device component; logic operable to calculate an optimum burst length, the optimum burst length being a minimum burst length required to minimize a number of read or write operations performed on the memory device, wherein the logic is configured to calculate the optimum burst length based on the first number and the second number, wherein the optimum burst length is equal to the first number divided by the second number, and further multiplied by a constant, wherein an optimum burst length corresponding to all available memory channels being populated is smaller than an optimum burst length corresponding to a subset of the available memory channels being populated; a control register configured to receive and store the optimum burst length; and a second memory to store a state machine operable to perform read or write operations on the memory device using the optimum burst length as a data length for the read or write operations.