Patent ID: 6953973

Claim:
A self-aligned trench isolation method, comprising: forming a first gate pattern on a first region of a semiconductor substrate, the first gate pattern having a first gate insulating layer pattern, a first lower gate conductive layer pattern and a gate etching stopper layer pattern that are sequentially stacked; forming a second gate pattern on a second region spaced apart from the first region to define a border region between the first and second regions, the second gate pattern being formed to have a second gate insulating layer pattern and a second lower gate conductive layer pattern which are sequentially stacked; removing the gate etching stopper layer pattern to expose the first lower gate conductive layer pattern; forming first and second trench mask patterns on predetermined regions of the first and second lower gate conductive layer patterns, respectively; etching the first and second lower gate conductive layer patterns and the first and second gate insulating layer patterns using the first and second trench mask patterns as etching masks to form first and second lower gate electrode patterns below the first and second trench mask patterns, respectively, the semiconductor substrate in the border region being etched during the etching process of the first and second lower gate conductive layer patterns to generate a groove region having a predetermined depth in the border region; and etching the semiconductor substrate using the first and second trench mask patterns as etching masks to form trench regions, the trench region in the border region being formed to be deeper than the trench regions in the first and second regions.