Patent ID: 8390062

Claim:
A vertical channel transistor array comprising: a plurality of semiconductor pillars disposed in a semiconductor substrate and arranged in a row/column array, wherein each of the semiconductor pillars forms an active region of the vertical channel transistor array; a plurality of embedded bit lines filled in a plurality of trenches in the semiconductor substrate, which are arranged in parallel in the semiconductor substrate and extended along a column direction; a plurality of bit line contacts, each of the bit line contacts being disposed on a side surface of one of the embedded bit lines and contacted with a side surface of a semiconductor pillar, wherein the embedded bit lines are electrically connected to the semiconductor pillars located in a same column through the bit line contacts; a plurality of embedded word lines filled in a plurality of trenches in the semiconductor substrate, which are arranged in parallel above the embedded bit lines and extended along a row direction, wherein the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars; and a current leakage isolation structure disposed at terminals of the embedded bit lines to prevent current leakage between adjacent bit line contacts.