Patent ID: 8037390

Claim:
A memory system comprising: a memory controller connected to a memory via a channel; wherein the memory controller comprises a command/address transmitting block generating a command packet and error detection/correction (EDC) data associated with a command indicated by the command packet, and communicating the command packet and the EDC data to the memory via the channel, wherein the memory comprises; a memory core; a receiver block comprising a packet receiver receiving the command packet and the EDC data, and generating an internal command, internal EDC data, and an internal address; a decoding/execution block decoding and executing the command in parallel with executing an EDC operation related to EDC data, wherein execution of an operation indicated by the command is immediate and without regard to completion of the EDC operation unless the command is a write command, but if the command is a write command delaying execution of the operation until completion of the EDC operation; an error decoder receiving the internal EDC data, the internal command and the internal address, and generating an error signal; a command decoder receiving the internal command and generating a plurality of control signals including a write enable signal applied to the memory core; and a write signal transfer block receiving the write enable signal and the error signal and generating a final write enable signal initiating a write operation in the memory core in response to the error signal.