Patent ID: 6972454

Claim:
A circuit structure, comprising: a semiconductor substrate having thereon circuitry including high and low voltage transistors; and a matrix of non volatile memory cells organized in rows and columns integrated on the semiconductor substrate, each memory cell having a floating gate transistor and a selection transistor, said rows being interrupted by at least a couple of byte selection transistors, said transistors being manufactured in respective active areas delimited by portions of an insulating layer, said circuit structure having a first and a second multilayer band formed on said semiconductor substrate, each band having a first gate oxide layer, a first polysilicon layer, a second dielectric layer and a second polysilicon layer, said first band defining the gate regions of said byte selection transistor and of said selection transistor in correspondence with said respective active areas and having a portion extending on a portion of the insulating layer adjacent to said byte selection transistor, said second band defining the gate regions of said floating gate transistor, wherein said portion of said first band is provided with an opening, formed in said second dielectric layer and in said second polysilicon layer, filled at least partially by a conductive layer said portion of said first band having a greater width at the location of said opening than the width at the location of said active areas.