Patent ID: 7898095

Claim:
A stacking substrate comprising: a wafer having top and bottom surfaces, said wafer being divided vertically into a plurality of layers including an integrated circuit layer extending into said wafer by a first distance from said top surface of said wafer and having integrated circuit elements constructed therein and a buffer layer adjacent to said bottom surface, said buffer layer being devoid of integrated circuit elements, said buffer layer being separated from said top surface of said wafer by a distance greater than or equal to said first distance; and an alignment fiducial mark extending from said top surface of said wafer into said wafer by a second distance that is greater than said first distance, said alignment fiducial mark comprising a plurality of trenches arranged in a pattern that comprises a fiducial mark for aligning a mask used to create a pattern on a backside of said wafer after said wafer has been thinned by removing said buffer layer, said backside being exposed by said thinning, wherein said integrated circuit layer is divided into die areas containing integrated circuit elements and areas lacking integrated circuit elements, said areas lacking integrated circuit elements being positioned between said die areas, and wherein said fiducial mark is located in one of said areas between said die areas and wherein said fiducial mark is not electrically connected to any of said integrated circuit elements.