Patent ID: 7334210

Claim:
A semiconductor integrated circuit designed in a cell-based scheme, comprising: a plurality of cells placed so as to be aligned at top in a plurality of strip areas provided in parallel with each other; and a plurality of wirings connecting among the cells, wherein the cells include cells on a clock path and a cell for performing a logical operation, and a cell-placement prohibiting area is set for each of all or part of the cells on the clock path so as to center on the cell on the clock path, and the cell for performing the logical operation is placed in a portion of the strip areas except the cell-placement prohibiting areas, wherein a capacitive cell is placed in at least one of the cell-placement prohibiting areas, wherein a cell-placement prohibiting area placed so as to center on a cell in an n-th strip area forms an overlapping area with an (n−1)-th strip area and an (n+1)-th strip area, and wherein the capacitive cell is placed in the overlapping area.