Patent ID: 8762919

Claim:
A computer implemented method for placement of random logic macros of an electronic circuit design, wherein said macros comprise any one of a fixed outline shape or a modifiable outline shape, the method comprising: modifying, by a computer, an outline of a modifiable outline shape macro based on criteria consisting of any one of a macro port weight value, a macro port ordering; a macro rapport constraint or a macro logic depth, the modifiable outline shape macro having ports defined at outermost edges of the modifiable outline shape macro; placing the modified modifiable outline shape macro at a location on an integrated circuit; binning, based on cones of influence of input ports to output ports, logic of the modifiable outline shape macro into two or more rectangles, each rectangle comprising circuits having logic depth less than a logic depth assigned to the rectangle; and arranging the two or more rectangles to form the modified outline shale macro.