Patent ID: 8611845

Claim:
A power sampler circuit that allows true detection of power levels in a circuit with an arbitrarily settable coupling factor comprising: a combination of a very small value series resistor and four large value parallel resistors arranged two in series with each other are placed between a source and a load, samples the voltage across the small series resistor so that the resultant voltage can be connected to a balanced detector log video amplifier with minimal parasitic effects arising out of the resistive elements, wherein the small series resistor is a small fraction of the source and lad impedance values at the frequencies of operation, wherein the large parallel resistors are many times larger than the source and load impedances at the frequencies of operation, wherein the large parallel resistors can be chosen to be equal to each other in order to provide symmetry and perfect balance and parasitic effect minimization, or varied to provide the ability to feed arbitrary detection devices with arbitrary impedances or provide acceptable levels of directionality if needed by a particular system, wherein the output of the power sampler circuit is connected to a balanced Detector Log Video Amplifier to provide a detected output that is directly proportional in dB to the circuit power level at the sampling point.