Patent ID: 8321820

Claim:
A method to compensate optical proximity correction, adapted for a photolithography process and comprising: providing an integrated circuit layout, wherein the integrated circuit layout comprises a plurality of active regions and a shallow trench isolation region, and the integrated circuit layout further comprises a plurality of ion implant regions overlapped with the shallow trench isolation region and at least a part of the active regions; acquiring at least a photoresist line width compensation region from a photoresist covering region outside the ion implant regions according to the integrated circuit layout, wherein the photoresist line width compensation region each is disposed in the shallow trench isolation region; correcting the integrated circuit layout according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region, and a distance between the side of the photoresist line width compensation region and the active region facing the side of the photoresist line width compensation region; and transferring the corrected integrated circuit layout to a photomask.