Patent ID: 8200735

Claim:
A data processing system includes a multi-core processor with a plurality of processing elements each having a processor and a local memory, said data processing system comprising: a system memory for storing a value matrix in which non-zero elements of an input matrix are arranged, and a position matrix including elements each indicating positions of said non-zero elements of said input matrix; a first processing element having a first local memory for storing a first sub-vector that is a part of said input vector; a second processing element having a second local memory for storing a second sub-vector that is another part of said input vector; a first readout unit configured to read out matrix elements sequentially one by one from said value matrix and from said position matrix stored in said system memory, and to store said read out matrix elements in said first local memory as newly-read matrix elements; a first arithmetic unit in said first processing element configured to multiply two matrix elements every time a matrix element is read out by said first readout unit, wherein one of said two elements is a vector element in said first sub-vector that corresponds to the position of a non-zero element indicated by each of said matrix elements read out from said position matrix in said first local memory, and the other of said two elements is a non-zero element read out from said value matrix in said first local memory; a second readout unit configured to read out a matrix element of said value matrix and said position matrix from said first local memory, and to store said matrix element in a second local memory as a newly-read matrix element every time an arithmetic operation is performed by said first arithmetic unit; a second arithmetic unit in said second processing element configured to multiply two elements every time a matrix element is read by said second readout unit, wherein one of said two elements is a vector element in said second sub-vector that corresponds to a position of a non-zero element indicated by each of said matrix elements read from said position matrix in said second local memory, and the other of said two elements being a non-zero element read from said value matrix in said second local memory; and an output unit in said second processing unit configured to generate each element of a vector to indicate a product of said input matrix and said input vector based on results of said arithmetic operations performed by said first and second arithmetic units, and to store said element in said system memory.