Patent ID: 8124488

Claim:
A method of fabricating a memory, comprising: providing a substrate comprising a memory region and a periphery region, a plurality of first gates formed on the substrate in the memory region, a plurality of second gates formed on the substrate in the periphery region, and a first spacer formed on a sidewall of each of the first gates and the second gates, wherein a plurality of openings is disposed between the first gates in the memory region; forming a first material layer on the substrate in the memory region, the first material layer covering the first gates in the memory region and filling the openings; performing a process to the periphery region; partially removing the first material layer to form a first pattern in each of the openings; forming a second material layer on the substrate, the second material layer covering the periphery region and the memory region and exposing tops of the first patterns; removing the first patterns to form a plurality of contact openings in the second material layer; and forming a contact plug in each of the contact openings.