Patent ID: 8241961

Claim:
A method for manufacturing a hetero-bonded wafer comprising: (a) providing a first wafer and a second wafer having substantially different thermal expansion coefficients from one another; (b) forming bonding means and electrical interconnection means on at least one bonding surface of the first wafer and the second wafer; (c) forming grooves having a depth shallower than a thickness of the first wafer in the bonding surface along dicing lines of the first wafer, thereby dividing the bonding surface of the first wafer into a plurality of small segments having a size defined by the grooves; (d) aligning and bonding the first wafer and the second wafer together as a bonded wafer pair at a first bonding temperature of less than 200° C. to avoid arising thermal stress while providing intermediate bonding of the bonded wafer pair; (e) thinning a back side of the bonded first wafer such that at least a portion of the grooves are exposed, thereby fragmenting the bonded first wafer into a plurality of small segments while the small segments remain bonded to the second wafer; and (f) rebonding the bonded wafer pair at an elevated temperature of at least greater than the first bonding temperature.