Patent ID: 7859916

Claim:
An input buffer comprising: a first amplifier circuit having an output node, the first amplifier circuit coupled to receive a first input signal and a second input signal, the first amplifier circuit operable to generate an output signal in response to the first input signal transitioning, the first amplifier circuit being capacitively coupled to receive a portion of the first input signal relative to the transition of the first input signal in a manner such that the rate at which the first amplifier circuit generates the output signal increases; and a second amplifier circuit being coupled in parallel to the first amplifier circuit and coupled to the output node, the second amplifier circuit being configured complementary respective to the first amplifier circuit and further coupled to receive the first input signal and the second input signal, the second amplifier circuit operable to generate the output signal in response to the first input signal transitioning, the second amplifier circuit being capacitively coupled to receive a portion of the first input signal relative to the transitioning of the first input signal in a manner such that the rate at which the second amplifier circuit generates the output signal increases.