Patent ID: 8028207

Claim:
A system comprising: a computer motherboard comprising at least two memory slots wherein each of the at least two memory slots is configured to be uniquely identified with respect to other memory slots; a system memory comprising two or more memories wherein each one of the at least two memory slots is configured to hold a respective one of the two or more memories; a communications port on the computer motherboard that is configured to transmit a message without using the system memory; a nonvolatile memory containing a BIOS comprising a plurality of executable modules that are configured to be used to boot the system; a memory test module that is one of the plurality of executable modules and a messaging module that is one of the plurality of executable modules wherein the memory test module is configured to automatically perform a DQS calibration test at BIOS initialization on each of the two or more memories and create a bad memory identifier specifying which of the at least two memory slots holds a bad memory that failed the DQS calibration test, and wherein the messaging module is configured to report the bad memory identifier, without requiring that the system memory be functional.