Patent ID: 8549228

Claim:
A processor comprises: a processing unit that has a first storage unit; a second storage unit that holds part of the data held by the first storage unit; a third storage unit that receives from the processing unit a first request for reading out data from the second storage unit and including first attribute information for obtaining a first logical value and a second request for reading out data from the second storage unit and including second attribute information for obtaining a second logical value different from the first logical value and that holds the first request until receiving a completion notification of the first request or holds the second request until receiving a completion notification of the second request, the first and second attribute information including LRU (Least recently used) information with sector IDs; and a control unit that receives a prefetch request as the second request following the first request from the third storage unit and, replaces the first attribute information of the first request by the second attribute information when data of the addresses corresponding to the first and second request are not in the second storage unit, and supplies the completion notification for the second request to the first storage unit.