Patent ID: 6944044

Claim:
Method for reading out a state from a ferroelectric transistor of a memory cell which is arranged in a memory matrix with a plurality of further memory cells with further ferroelectric transistors, the method comprising: reading the state is out from the ferroelectric transistor; driving at least one further ferroelectric transistor in the memory matrix during the read-out of the state in such a way that it is operated in its depletion region; and operating the further ferroelectric transistor in the depletion region by the further ferroelectric transistor being driven in such a way that the following holds true: V FB −F ( P FE )≦ V GS ≦V th −F ( P FE ), where V FB designates the flat-band voltage of the further ferroelectric transistor; V GS designates the gate-source voltage of the further ferroelectric transistor; V th designates the threshold voltage of the further ferroelectric transistor; and F(P FE ) designates a function of the ferroelectric polarization P FE of the further ferroelectric transistor.