Patent ID: 8639883

Claim:
A cache, comprising: a buffer that: buffers data to be cached from a processor, and buffers data to be destaged from cache to a storage subsystem; and at least one flash memory device coupled to the buffer, the at least one flash memory device: comprising a plurality of logical partitions, wherein each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of pages, and caches the data to be cached from the buffer, wherein the cached data are accessible by the processor from the buffer and a location of the cached data within the plurality of logical partitions is accessible by the processor; wherein data to be destaged to the storage subsystem are read by the buffer from a single logical partition of the plurality of logical partitions until at least all modified data in the single logical partition have been read; and wherein when the at least all modified data in the single logical partition have been read by the buffer, the single logical partition is made available for erasing data destaged to the storage system and writing new data to be cached.