Patent ID: 7603605

Claim:
A method of controlling an integrated circuit including a test memory array having a plurality of memory elements storing respective bit values, said method comprising the steps of: during a testing phase: (i) performing a first read, using a sense amplifier controlled by a speculative timing signal, of a bit value stored within a memory element of said test memory array and outputting a speculative value; (ii) performing a second read, using a sense amplifier controlled by a safe timing signal, of said bit value stored within said memory element and outputting a safe value; (iii) comparing said speculative value and said safe value with a difference between said speculative value and said safe value indicating a read failure due to said speculative timing signal controlling said first sense amplifier to read said bit value too soon; and (iv) repeating said first read and said second read for a plurality of different memory elements within said test memory array and for a plurality of different timings of said speculative timing signal so as to obtain as test results a measure of read failure rate as a function of timing of said speculative timing signal; setting a programmable sense amplifier timing parameter of one or more further memory arrays within said integrated circuit in dependence upon said measure; and during an operational phase, operating said one or more further memory arrays using said programmable sense amplifier timing parameter.