Patent ID: 8593865

Claim:
A nonvolatile memory device, comprising: a memory cell array comprising a plurality of memory blocks; an address decoder configured to select one of the memory blocks in response to an input address and to generate a first control signal and a second control signal; a plurality of metal lines connected with the memory blocks and extending along a first direction; a plurality of pass transistors configured to connect the address decoder with a first subset of the metal lines connected with the selected memory block in response to the first control signal; and a plurality of ground transistors configured to supply a low voltage to a second subset of the metal lines connected with unselected memory blocks in response to the second control signal, wherein the ground transistors have channels that extend along a second direction perpendicular to the first direction, wherein the pass transistors are configured to connect the address decoder with a plurality of word lines connected with the selected memory block and to float a plurality of word lines connected with unselected memory blocks, in response to the first control signal.