Patent ID: 7664315

Claim:
An integrated image processor implemented on a substrate comprising: an input interface configured to receive pixel data from one or more images; and a pixel handling processor disposed on the substrate configured to convert the pixel data from the input interface into depth pixel data; and a foreground detector processor disposed on the substrate configured to classify pixels from the pixel handling processor as background or not background, wherein the output of the foreground detector processor comprises one bit per pixel indicating whether the pixel is classified as background or not background, and wherein a background pixel comprises a pixel that is determined to be relatively stable using a model of the pixel's behavior over time, and wherein the pixel handling processor and the foreground detector are arranged in a low latency pipelined architecture such that each are operating on pixel data from the one or more input images at the same time, and wherein the foreground detector processor includes storage for the model of each pixel's behavior over time, wherein the pixel handling processor only requires a subset of its input image to produce an output depth pixel data, and wherein the foreground detector only requires a subset of an input range image to classify a pixel as foreground or background.