Patent ID: 7122438

Claim:
A method of manufacturing a semiconductor memory, comprising: providing a semiconductor substrate of a first conductive type, forming a first semiconductor layer of a second conductive type above the semiconductor substrate, and forming a second semiconductor layer of the second conductive type over said first semiconductor layer, said second semiconductor layer having a lower concentration than that of said first semiconductor layer, forming grooves, which are trenched down to said semiconductor substrate in predetermined regions, thereby forming adjacent semiconductor pillars in between said grooves; forming a plate electrode of a capacitor by embedding a conductor within said grooves extending into a region of said first semiconductor layer and with a capacitor insulation film formed therebetween, forming a word line, which is also a gate electrode of an insulated gate static induction transistor, by embedding conductor in a region above said plate electrode including a region adjacent to said first semiconductor layer and said second semiconductor layer with an insulation film formed therebetween, forming a drain region of said insulated gate static induction transistor comprising a semiconductor region of the second conductive type of said semiconductor pillar, said semiconductor drain region having a higher concentration than that of said second semiconductor layer, and forming an interlayer insulation film as an upper layer above the drain region and word line, and forming a bit line connected to said drain region over said interlayer insulation film.