Patent ID: 8638123

Claim:
An adder comprising: a sum circuit electrically connected to a first power supply line and a second power supply line; a first input terminal electrically connected to the sum circuit; a second input terminal electrically connected to the sum circuit; a third input terminal electrically connected to the sum circuit; and a first output terminal electrically connected to the sum circuit; wherein the sum circuit comprises: a first transistor, one of a source and a drain of the first transistor is electrically connected to the first power supply line and the other of the source and the drain of the first transistor is electrically connected to the second power supply line; and a second transistor comprising a channel formation region comprising an oxide semiconductor layer, one of a source and a drain of the second transistor is electrically connected to the third input terminal and the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and wherein the sum circuit is configured to output a high-potential signal from the first output terminal in accordance with an input of a high-potential signal to any one of the first input terminal, the second input terminal, and the third input terminal or high-potential signals to the first input terminal, the second input terminal, and the third input terminal.