Patent ID: 8615684

Claim:
A computer system comprising: a processor executing a stored program, the processor providing for an execution of instructions on the processor, the stored program executing on the processor to: (a) perform functions of a first application program employing at least a subset of the instructions; (b) perform a calculation employing the subset of the instructions, the calculation provoking an error state of the processor when any of the subset of the instructions is not operating correctly, the calculation further entering a predetermined delay loop when the results of a given instruction in the calculation are incorrect; wherein the processor includes a timer triggering an error state at a conclusion of a predetermined time and wherein the calculation is performed repeatedly at a period less than the predetermined time and wherein the processor resets the timer using at least one instruction in the subset of instructions only when the result of the calculation matches a correct output value and wherein the correct output value provides an address of a memory mapped reset of the timer used by the processor to reset the timer.