Patent ID: 8127214

Claim:
A unified decoder comprising: a first group of trellis processors to perform processing associated with states of a decoding trellis, said first group of trellis processors to calculate path metrics when said unified decoder is performing convolutional code decoding and to calculate alpha (forward) metrics when said unified decoder is performing Turbo code decoding and low density parity check (LDPC) code decoding; a second group of trellis processors to perform processing associated with states of a decoding trellis, said second group of trellis processors to calculate path metrics when said unified decoder is performing convolutional code decoding and to calculate beta (backward) metrics when said unified decoder is performing Turbo code decoding and LDPC code decoding; a number of reliability calculators to calculate output reliabilities, using alpha and beta metrics, when said unified decoder is performing Turbo code decoding and LDPC code decoding; a normalization unit to normalize metrics generated by said trellis processors; a first alpha-beta swap unit to controllably distribute normalized metrics to trellis processors in said first group for use in processing a next trellis stage; and a second alpha-beta swap unit to controllably distribute normalized metrics to trellis processors in said second group for use in processing a next trellis stage.