Patent ID: 6848068

Claim:
An apparatus comprising: a plurality of configuration pins configured to receive a plurality of configuration signals generated external to said apparatus; an input pin for data; and a circuit comprising: a first logic gate configured to generate a first identification signal from said configuration signals; a first multiplexer having (i) a first input directly connected to said first logic gate to multiplex said first identification signal to a first multiplexer output, (ii) a second input for receiving a serial signal and (iii) a third input for receiving a control signal that controls selection between said first input and said second input; and a shift register comprising a plurality of memory elements, wherein (i) said shift register is couplable to said input pin for shifting in said data and (ii) a first of said memory elements has a first input directly connected to said first multiplexer output such that said first identification signal forms a first portion of a device identification for said apparatus.