Patent ID: 8502282

Claim:
A device comprising: a substrate having first and second major surfaces; and first and second junction field-effect transistors on the first major surface of the substrate, each of the first and second junction field-effect transistors comprising: a drain layer of an n-type semiconductor material; one or more drift layers of an n-type semiconductor material disposed on the drain layer with portions of the drain layer not covered by the n-type semiconductor material of the one or more drift layers, the one or more drift layers having a lower conductivity than the drain layer; a plurality of raised regions arranged as longitudinally-extending fingers on the one or more drift layers, each raised region comprising a channel region of an n-type semiconductor material on the one or more drift layers and a source region of an n-type semiconductor material on the channel region, the semiconductor material of the source region having a higher conductivity than that of the channel region; a plurality of gate regions of a p-type semiconductor material on a portion of the one or more drift layers, each of the gate regions laterally adjacent a respective of the raised regions and displaced laterally to be uncovered by a respective of the source regions, each of the gate regions forming a rectifying junction with n-type material of the one or more drift layers and a respective of the channel regions; and ohmic contacts on the gate and source regions and on exposed portions of the drain layer.