Patent ID: 7821856

Claim:
A memory device, comprising: a memory cell; and an evaluation circuit coupled with: a reference line having a first part coupled via a first switch to a remaining part of the reference line; and the memory cell via a bit line having a first part coupled via a second switch with a remaining part of the bit line, the remaining part of the bit line being connected with the memory cell; wherein the evaluation circuit is: configured to amplify a difference between electric potentials on the bit line and the reference line, directly connected to: (i) the first part of the bit line, (ii) the remaining part of the bit line, (iii) the first part of the reference line, and (iv) the remaining part of the reference line, a sense amplifier or a read amplifier configured to amplify a potential difference between bit line and the reference line by amplifying their respective electric potentials to two pre-determined potential values in multiple steps, comprising: a first step in which the first part of the bit line and the remaining part of the bit line are not connected via the second switch and the first part of the reference line and the remaining part of the reference line are not connected via the first switch, wherein the difference of the potentials of the first part of the bit line and the first part of the reference line are amplified depending on the different potentials on the remaining part of the bit line and the remaining part of the reference line, a second step in which the first part of the bit line is connected via the second switch with the remaining part of the bit line and the first part of the reference line is connected to the reference line via the first switch, wherein the potential difference of the bit line and the reference bit line is further amplified.