Patent ID: 8085070

Claim:
A timing circuit comprising: a CPU phase-locked loop (PLL) which provides a CPU clock signal with an overclocking step resolution that is not a multiple of the CPU output frequency and is implemented in circuitry according to the following equation: ((N actual *ref_clk)/P)/N where N actual is an actual CPU frequency output by the CPU PLL, ref_clk is a reference clock received by the CPU PLL, P is a dividing value used by a P-divider, and N is a dividing value used by a fractional N-divider; and a phase selection circuit that provides control signals to the fractional N-divider in response to input signals; wherein the fractional N-divider is coupled to receive the VCO clock signal and provides a feedback clock; wherein the P-divider provides the CPU clock signal based on the VCO clock signal; wherein the CPU PLL receives the reference clock and the feedback clock and outputs a VCO clock signal in response to a comparison between the reference clock and the feedback clock; and wherein the value P of the P-divider and the input signals to the phase selection circuit are chosen so that the step resolution is fixed while the VCO clock signal has a frequency less than a set frequency.