Patent ID: 7605069

Claim:
A method for fabricating a semiconductor device comprising: forming a gate insulation layer over a substrate; sequentially forming a polysilicon layer, a silicide layer and a hard mask layer over the gate insulation layer; selectively patterning the hard mask layer; etching the silicide layer using the patterned hard mask layer as a mask such that the silicide layer has a cross-sectional etch profile that is negatively sloped; etching the polysilicon layer using the patterned hard mask layer as a mask to form a gate; and performing a re-oxidation process to oxidize exposed sidewalls of the polysilicon layer and the silicide layer, wherein the etching of the silicide layer includes: performing a main etching process until the polysilicon layer is exposed; and over etching the silicide layer when the polysilicon layer is exposed so that the silicide layer has the negatively sloped etch profile in the form of an undercut.