Patent ID: 8156312

Claim:
A processor chip for reconfigurable data processing, comprising: a plurality of data buses adapted to transmit data; and a plurality of configurable cell units interconnected by the plurality of data buses and adapted to process the data transmitted by the plurality of data buses, at least some of the configurable cell units being configurable data processing cells, each of the configurable data processing cells including: at least three physical hardware registers an arithmetic-logic unit configured to perform mathematical and logical functions on at least one operand, the arithmetic-logic unit being at least capable of processing a multiplication, and at least one result of the arithmetic-logic unit being at least 5-bits wide; an interconnection unit adapted to interconnect the configurable data processing cell with other configurable cells; and an interface that receives a configuration data word that defines at least one of the function and the interconnection of the cell; wherein: at least two of the at least three physical hardware registers are operand registers in which at least two operands are storable, and at least one other of the at least three physical hardware registers is a result register for storing a result of the arithmetic-logic unit; the configuration data word includes a plurality of bits being transmittable simultaneously in parallel; each of the configurable data processing cells is configurable at run time in its function and interconnection on an individual basis independent of, without disturbing, and without affecting in their configuration and operation, others of the data processing cells; and the arithmetic-logic unit is adapted for, in a single clock cycle: obtaining the at least two operands from the at least two operand registers; performing a function on the obtained at least two operands; and storing a result of the function in the at least one result register.