Patent ID: 7884004

Claim:
A method of fabricating a device, comprising the steps of: patterning a first pad, a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer; contacting the nanowires and pads with an inert gas at a pressure, temperature and for a duration sufficient to cause silicon to migrate from the nanowires to the pads; coating the nanowires with a dielectric; forming a gate surrounding the nanowires, such that the gate is separated from the nanowires by the dielectric; forming spacers adjacent to the gate, wherein the device comprises a field-effect transistor (FET) and wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET; and forming an epitaxial layer that covers the source and drain regions.