Patent ID: 8305506

Claim:
A pixel set, comprising: two scan lines parallel to each other; a data line intersected with the two scan lines; two pixels located between the two scan lines, respectively located at two opposite sides of the data line, and respective electrically connected to the two scan lines, wherein each of the pixels comprising: an active device disposed adjacent to the data line, and the active device comprising: a gate electrically connected to a corresponding one of the scan lines; a source electrically connected to the data line; a drain and the source located at two opposite sides of the gate; a pixel electrode electrically connected to the drain; a storage capacitance electrode at least partially overlapped with the pixel electrode, the storage capacitance electrode comprising a branch located at a side of the pixel electrode away from the data line, and the branch having a concavity located at a side of the branch adjacent to the data line; and a drain compensating pattern connected to the drain, at least a portion of the drain compensating pattern located inside the concavity, and the branch not overlapped with the drain compensating pattern at a side of the concavity away from the gate, wherein the branch is substantially aligned with an edge of the drain compensating pattern at a side of the concavity adjacent to the gate.