Patent ID: 8035157

Claim:
A flash memory device comprising: a semiconductor substrate; a first wall-shaped body connected to the semiconductor substrate and protruding from the semiconductor substrate in a wall shape; an isolation insulating layer made of an insulating material and formed between the first wall-shaped body and a second wall-shaped body adjacent to the first wall-shaped body so as to electrically isolate devices which are to be formed in the first wall-shaped body and the second wall-shaped body; an interlayer insulating layer formed on an exposed upper surface and side walls of the first wall-shaped body which are exposed by etching the isolation insulating layer by a predetermined depth from the upper surface of the first wall-shaped body; and a control electrode formed on the interlayer insulating layer in a direction perpendicular to the first wall-shaped body, wherein the interlayer insulating layer comprises: a tunneling insulating layer formed on the exposed upper surface and side walls of the first wall-shaped body; a charge storage node formed on the tunneling insulating layer to store charges; a control insulating layer formed on the charge storage node, wherein the control insulating layer is formed between the charge storage node and the control electrode, and wherein the flash memory device includes neither a source nor a drain, and is operated as a cell device by a fringing field generated by a voltage applied to the control electrode.