Patent ID: 7915122

Claim:
A method of forming a self-aligned logic cell, the method comprising the sequential steps of: forming an electrically conductive bottom electrode, forming a carbon nanotube layer over the bottom electrode and having electrical continuity with the bottom electrode, forming an electrically conductive clamp layer over the nanotube layer and having electrical continuity with the nanotube layer, where the clamp layer substantially completely covers the nanotube layer, thereby protecting the nanotube layer, forming an electrically nonconductive dielectric layer over the clamp layer, etching the dielectric layer with a first etchant that does not substantially etch the clamp layer, where the clamp layer provides an etch stop to the first etchant and protects the nanotube layer from the first etchant, leaving a remainder of the dielectric layer overlying the bottom electrode, etching the clamp layer with an isotropic second etchant that does not substantially etch the dielectric layer and the nanotube layer, and which etches the clamp layer underneath a peripheral edge of the dielectric layer to a substantially uniform and desired degree, thereby creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the overlap of the dielectric layer, forming an electrically conductive spacer layer over at least the nanotube layer that does not substantially underlie the dielectric layer, the spacer layer having electrical continuity with the nanotube layer, etching the spacer layer to remove all of the spacer layer except a ring portion circumferentially disposed around the peripheral edge of the dielectric layer and overlying a portion of the nanotube layer, and etching the nanotube layer to remove all of the nanotube layer except those portions of the nanotube layer that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.