Patent ID: 7526589

Claim:
A system to reset an Inter-Integrated Circuit (I2C) bus slave, the system comprising: an I2C bus master that communicates over a data line and a clock line and comprising a hang detection module that detects a hung line selected from the data line and the clock line; a negative voltage generator that drives the data line to a specified negative voltage for a specified time interval in response to the detected hung line; a clamping diode that limits the specified negative voltage to greater than a specified limit; the I2C bus slave that communicates with the I2C bus master over the data line and the clock line and comprising a voltage detector module that detects the specified negative voltage on the data line; a timer module that detects the specified time interval of the specified negative voltage; and a reset module that resets the I2C bus slave in response to the timer module detecting the specified interval of the specified negative voltage.