Patent ID: 6897672

Claim:
A semiconductor die testing system comprising: a probe card for use as an interface for a testing computer for testing at least one semiconductor die having at least one bond pad including: a substrate having a first surface and a second surface forming a surface of the probe card during the testing of at least one semiconductor die using a testing computer; a plurality of conductive traces disposed adjacent at least one of the first surface and the second surface, at least one conductive trace for carrying current during the testing of at least one semiconductor die using a testing computer; a plurality of probe elements in electrical communication with the plurality of conductive traces, at least one probe element of the plurality of probe elements for contacting the at least one bond pad of the semiconductor die during testing; and a plurality of fuses disposed adjacent the at least one of the first surface and the second surface, the plurality of fuses in electrical communication with the plurality of conductive traces for conducting current below a predetermined maximum level and for preventing conducting current when the current is above a predetermined maximum level during the testing of the semiconductor die; and semiconductor device testing apparatus linkable with the probe card, the semiconductor device testing apparatus configured for sending test signals through the probe card.