Patent ID: 7645656

Claim:
A method of fabricating a field effect transistor (“FET”), comprising: patterning a gate polycrystalline semiconductor layer overlying a single crystal semiconductor region of a substrate having a first composition to form a gate polyconductor (“PC”); forming sacrificial spacers overlying sidewalls of said PC; recessing portions of said single crystal semiconductor region in locations adjacent to said sacrificial spacers; epitaxially growing regions consisting essentially of a single crystal semiconductor alloy in said locations, said semiconductor alloy regions having a second composition different from said first composition, such that said sacrificial spacers at least partly determine first spacings between said semiconductor alloy regions and said PC; removing said sacrificial spacers; and completing said FET, wherein said recessing portions of said single crystal semiconductor region includes performing ion implantation in said portions and subsequently etching said implanted portions preferentially relative to portions of said single crystal semiconductor region which are not implanted by said implantation.