Patent ID: 7117320

Claim:
A computer program product stored on a computer readable storage medium for maintaining data access during failure of a first controller in a multiple controller storage subsystem, the multiple controller storage subsystem having an array of data storage devices and at least one other controller for managing the data storage, comprising computer readable program code for performing: in a non-testing mode, the first controller detecting an error in the first controller and thereby initiating a process to maintain data access during failure of the first controller, the process to maintain data access during failure of the first controller comprising: the first controller instructing the at least one other controller to save the at least one other controller's internal state information; saving internal state information of the first controller by the first controller; the first controller resetting itself after the saving of its internal state information; pausing operation of the at least one other controller; and the at least one other controller saving its internal state information at the time of pausing, in parallel with the first controller's saving of its internal state information; and continuing operation of the at least one other controller, wherein only the first controller resets during the process to maintain data access during failure of the first controller, wherein the first and the at least one other controller make the array of data storage devices appear to a host computer as a single high capacity storage device, wherein the internal state information of the first and the at least one other controller is saved to permit diagnosis of the failure of the first controller, wherein a flag is set when internal status data save operation is occurring to prevent another internal status data save operation from being invoked, wherein the flag is set to prevent the another internal status data save operation from being invoked before the greater time period of a set timeout period and the time period to write the internal status data to a memory, wherein the storage subsystem comprises a Fibre Channel Arbitrated Loop system and the first controller and the at least one other controller comprise host bus adapters.