Patent ID: 6990558

Claim:
A microprocessor, comprising: a cache memory, wherein said cache memory comprises an N-way set associative cache memory; an address input to said N-way set associative cache memory, for selecting an N-way set in said cache memory; a prefetch buffer, coupled to said cache memory, for receiving a prefetched cache line from a system memory; control logic, coupled to said prefetch buffer, for selectively retiring said prefetched cache line into said cache memory based on accesses to said prefetched cache line contemporaneous with prefetching said prefetched cache line into said prefetch buffer; a counter, coupled to said control logic, for counting a number of times said prefetched cache line in said prefetch buffer is accessed, wherein said control logic selectively retires said prefetched cache line into said cache memory based on said accesses to said prefetched cache line indicated by said number stored in said counter; and N counters, coupled to said control logic, each for counting a number of times a corresponding one of said N ways of said selected set is accessed after said prefetched cache line is prefetched.