Patent ID: 8019975

Claim:
A superscalar microprocessor capable of executing one or more instructions out-of-order with respect to an ordering defined by a program order, the microprocessor comprising: (a) an instruction fetch unit configured to provide a plurality of instructions to an instruction buffer; (b) an execution unit, coupled to the instruction fetch unit, configured to execute the plurality of instructions from the instruction buffer in an out-of-order fashion, the execution unit including a register file that is distinct from the instruction buffer, the register file having a plurality of temporary buffers to store result data from out-of-order instruction execution and a plurality of real entries to store results of retired instructions, the execution unit further including a load store unit adapted to make load requests and store requests to a memory system, the load store unit adapted to make at least one load request out of the program order so the one load request is made before a memory request, wherein the one load request corresponds to a first instruction from the plurality of instructions and the memory request corresponds to a second instruction from the plurality of instructions, wherein the second instruction precedes the first instruction in the program order, the load store unit including: (i) an address path adapted to manage load and store addresses and to provide the load and store addresses to the memory system the address path including an address buffer configured to buffer the load and store addresses, the address buffer being distinct from the register file; (ii) load dependency detection circuitry, wherein the load store unit does not make a particular load request when the load dependency detection circuitry detects an address collision or write pending for that particular load request; and (iii) a data path adapted to transfer data from the memory system to the register file of the execution unit in response to load requests, the data path configured to align data returned from the memory system to thereby permit data falling on a word boundary to be returned from the memory system to the execution unit in correct alignment, wherein the superscalar microprocessor initiates execution of more than one of the plurality of instructions from the instruction buffer in a clock cycle.