Patent ID: 7958340

Claim:
A method of software pipelining on a network on chip (‘NOC’), the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising: implementing a software pipeline on the NOC, including segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID; executing each stage of the software pipeline on a thread of execution on an IP block; monitoring software pipeline performance in real time; wherein monitoring software pipeline performance in real time further comprises monitoring software pipeline performance during predefined monitoring periods, including acquiring, by a data acquisition function of a thread on an IP block in the software pipeline, performance information from the IP block hardware during each monitoring period, and providing by the thread the performance information to a monitor function in a host interface processor during each monitoring period and wherein monitoring software pipeline performance in real time includes monitoring inter-thread communications rates among threads running instances of stages of the software pipeline; and reconfiguring the software pipeline, dynamically, in real time, and in dependence upon the monitored software pipeline performance.