Patent ID: 8405145

Claim:
A semiconductor device comprising: (a) a semiconductor substrate of a first conductivity type having a main surface and a back surface, the main surface including a chip outermost region, a gate wire extension region arranged in a side direction of the main surface from the chip outermost region, an inactive cell region arranged in a side direction of the main surface from the gate wire extension region and an active cell region arranged in a side direction of the main surface from the inactive cell region; (b) a gate trench formed in the inactive cell region and in the active cell region; (c) a gate insulating film formed over an inner wall and a bottom portion of the gate trench; (d) a gate electrode formed so as to fill the gate trench and electrically connected to a gate wire formed over the gate wire extension region; (e) a source region, of the first conductivity type, formed in the active cell region so as to be adjacent to the gate electrode; (f) a body region, of a second conductivity type different from the first conductivity type, formed in the active cell region so as to be deeper than a depth of the source region; (g) a drain region of the first conductivity type formed in the back surface; and (h) a first well region, of the second conductivity type, formed in the inactive cell region so as to be deeper than a depth of the body region and than a depth of the gate electrode, wherein, in the inactive cell region, the body region is formed in the first well region, and wherein the gate wire is integrally formed with the gate electrode.