Patent ID: 8898374

Claim:
A flash memory device, coupled to a host for storing data, comprising: a flash memory, comprising: a single level memory module, comprising a first data bus and at least one single level cell (SLC) flash memory, wherein each memory cell of the SLC flash memory stores one bit of data; a multi level memory module, comprising a second data bus and at least one multi level cell (MLC) flash memory, wherein each memory cell of the MLC flash memory stores more than one bit of data, and the first data bus is coupled to the second data bus; and a controller, for managing data access of the flash memory, receiving the data to be stored in the flash memory from the host and transmitting the data read out from the flash memory to the host, wherein during a write operation, the controller receives the data from the host, and writes the data into the SLC flash memory of the single level memory module of the flash memory according to a first data order, and wherein the single level memory module transmits the data stored in the SLC flash memory to the multi level memory module according to a second data order through the first and second data buses coupled therebetween without passing the data through the controller, and during a read operation for reading the data, the controller further reads the data from the multi level memory module according to the first data order, wherein the first data order is different from the second data order, and wherein the controller further comprises an error correction code encoder/decoder for encoding the data to be stored into the flash memory and decoding the data read out from the flash memory, wherein during a decoding process, when a number of error bits detected in a sub-page of a physical page is determined to have exceeded a correctable error bit number, the error correction code encoder/decoder further derives one or more memory cells of the physical page that has/have the possibility of having the error bit(s) occurring therein, predicts original content stored in the one or more memory cells according to the content stored in adjacent memory cell(s), and performs error correction code decoding of the physical page again according to the predicted original content, wherein the one or more memory cells of the physical page that has/have the possibility of having the error bit(s) occurring therein is/are derived when there is a memory cell that is programmed to a logical state that has great influence on the other stored logical states exists in adjacent physical page(s).