Patent ID: 8023342

Claim:
A device comprising: a memory; and a memory controller comprising: a preamble detection circuit comprising: a first multiplexer, and a second multiplexer to provide a first signal indicating detection of a beginning of a read cycle from the memory; control logic to select outputs of the first multiplexer and the second multiplexer, where the control logic is to determine the outputs to select for the first multiplexer and the second multiplexer during a training cycle in which a strobe signal is sampled over a plurality of data read cycles, and in which, during different ones of the plurality of data read cycles, different combinations of the outputs of the first multiplexer and the second multiplexer are selected, and where the control logic is to perform the training cycle when the device is initially powered-up or reset; and a first gate connected to output the strobe signal or block the strobe signal based on the first signal.