Patent ID: 7622971

Claim:
A delay locked loop circuit comprising: a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal; a control voltage generator configured to output a control voltage based on the comparison signal; a voltage controlled delay line comprising a plurality of delay elements and configured to delay the reference clock signal based on the control voltage and to output the output clock signal; and a control voltage initializer which includes a first set of delay elements and a second set of delay elements, and which is configured to generate first and second digital codes based on characteristics of the first and second sets of delay elements, and to generate an initial control voltage based on the first and second digital codes, wherein the characteristics of the first set of delay elements are based on a first constant delay voltage which delays the reference clock signal for a first delay amount, and the characteristics of the second set of delay elements are based on a second constant delay voltage which delays the reference clock signal for a second delay amount.