Patent ID: 7802038

Claim:
A data processing system, comprising: a system bus; a first bus master coupled to the system bus; a second bus master coupled to the system bus; and a resource coupled to the system bus and useable by the first bus master and the second bus master, wherein the resource comprises: endpoint storage circuitry comprising a plurality of endpoints, wherein each of the plurality of endpoints is allocatable to at least one of the first bus master and the second bus master, and wherein allocatability of each of the plurality of endpoints is programmable, and wherein the resource further comprises: a controller, coupled to the endpoint storage circuitry, the controller comprising: interrupt steering resisters; and interrupt steering logic, wherein the interrupt steering logic routes interrupts to a corresponding one of the first bus master and the second bus master based on steering information provided by the interrupt steering registers, and wherein the plurality of endpoints are allocated based on the interrupt steering registers, steering logic for establishing a communication path between the resource and at least one of the first and second bus masters, wherein the communication path is determined by the programmable circuit in the resource, and wherein no additional steering logic is required in the communication path between the resource and the at least one of the first and second bus masters; and a conductor for transferring an additional signal, separate from the system bus, between the resource and the at least one of the first and second bus masters via the communication path.