Patent ID: 8395454

Claim:
A circuit comprising: a first ring oscillator configured to generate a first periodic signal; a second ring oscillator configured to generate a second periodic signal; and a selection unit coupled to receive the first periodic signal and the second periodic signal, wherein the selection unit is configured to convey a first clock edge into each of the first and second ring oscillators responsive to a most recently received rising edge from one of the first and second periodic signals, and wherein the selection unit is further configured to convey a second clock edge into each of the first and second ring oscillators responsive to a most recently received falling edge from one of the first and second periodic signals, wherein the first and second clock edges are opposite in direction wherein the selection unit includes: a first logic gate coupled to receive, as inputs, the first and second periodic signals; a second logic gate coupled to receive, as inputs, the first and second periodic signals; a set-reset (SR) flop having a set input coupled to receive an output from the first logic gate and a reset input coupled to receive an output from the second logic gate, and an output coupled to convey the first and second clock edges into each of the first and second ring oscillators.