Patent ID: 7296179

Claim:
A multi-node computer system comprising: a local node, the local node comprising at least one local sub-node, the at least one local sub-node including a first local sub-node, the first local sub-node comprising: a local dynamic memory, the local dynamic memory being a volatile system memory used by a processor in the first local sub-node; a scalability port including a write-through transmit buffer associated with the local dynamic memory; and a first scalability chipset comprising a first memory controller that directs a write of data to the local dynamic memory simultaneous with a back-up write of the data to the write-through transmitting buffer; a remote node, the remote node comprising at least one remote sub-node, the at least one remote sub-node including a first remote sub-node, the first remote sub-node comprising: a back-up memory for the local dynamic memory of the first local sub-node, the back-up memory being distinct form local system memory of the first remote sub-node; a receiving interface buffer for receiving, from the write-though transmit buffer associated with the local dynamic memory of the first sub-node, data written to the local dynamic memory of the first sub-node; and a second scalability chipset comprising a second memory controller that directs a write to the back-up memory of data received at the receiving interface buffer; and an input/output controller in the second scalability chipset that assigns a location identity of the first local sub-node to a replacement sub-node only if the first local sub-node is removed from the multi-node computer system, the location identity based on a memory map included in the data stored in the back-up memory in the first remote sub-node.