Patent ID: 8612913

Claim:
A method, performed by a computing device, to determine a propagation delay of a selected net of a plurality of nets in a circuit design, the method comprising: identifying the selected net, the selected net includes a plurality of characteristics corresponding to the selected net; performing a first simulation of the selected net using the plurality of characteristics to estimate a propagation delay per unit length, wherein the performing of the first simulation includes, creating a test circuit using the plurality of characteristics of the selected net, and simulating the test circuit to estimate the propagation delay per unit length for the selected net without calculating propagation delays for other possible nets of the plurality of nets; computing the propagation delay for the selected net using a result of the first simulation; and providing for display of the propagation delay of the selected net in timing units, wherein a timing ruler displays the propagation delay of the selected net and enables a user to manipulate one or more of the plurality of characteristics of the selected net and to adjust the propagation delay of the selected net during circuit design.