Patent ID: 7015103

Claim:
A method for fabricating a vertical transistor comprising: forming a first junction area in a semiconductor substrate; forming a polysilicon layer on an epitaxial layer in the substrate; forming a second junction area in the polysilicon layer; forming a plug junction area in the polysilicon layer, the plug junction area electrically connected with the first junction area; forming a trench by selectively etching and removing the polysilicon layer to expose the first junction area; sequentially depositing a gate insulating layer and a conductive layer for a first gate electrode on the trench and the polysilicon layer; forming the first gate electrode by selectively patterning the conductive layer; forming an insulating interlayer on an entire surface of the substrate including the first gate electrode; forming via-holes for exposing predetermined portions of the first junction area, the first gate electrode, and the plug junction area; and forming source/drain electrodes and a second gate electrode respectively connected with the first junction area, the first gate electrode, and the plug junction area by forming a metal layer within the via-holes.