Patent ID: 7885254

Claim:
A delay insensitive data transfer apparatus, comprising: N number of first encoders configured to receive and encode an input request signal and data signals inputted from a data transmitter into current-level signals; N number of first decoders configured to recover the current-level signals inputted from the first encoders into voltage-level signals; a second encoder configured to receive the request signal through a request signal input terminal and a data signal input terminal and output a current-level signal; a second decoder configured to output a completion signal when the current-level signal from the second encoder has a level of 2I; and a request signal processor configured to output a latch enable signal for latching N-bit data signals when the completion signal is inputted from the second decoder, where the first encoders output a current having a level of 0 indicating a space state according to the request signal inputted from the data transmitter, output a current having a level of I when the data signal is 0 in such a state that the request signal inputted from the data transmitter is in an activated state, and output a current having a level of 2I when the data signal is 1.