Patent ID: 7339943

Claim:
An apparatus, comprising: a plurality of queuing paths, each of said queuing paths further comprising an input queue, an intermediate queue and an output queue, said input queue having an output coupled to an input of said intermediate queue and an input of said output queue, said intermediate queue having an output coupled to said input of said output queue, said intermediate queue to receive data units from said input queue if a state of said input queue has reached a threshold, said output queue to receive data units from said intermediate queue if said intermediate queue has data units, said output queue to receive data units from said input queue if said intermediate queue does not have data units, wherein the input queue, the intermediate queue and the output queue are coupled to corresponding controllers, each of the corresponding controllers having arbiters for controlling bus usage for respective queues; and an input controller in data communication with both said intermediate queue and said output queue, an intermediate controller in data communication with said intermediate queue, with said input controller configured to make a determination that a buffer's worth of information is available in said intermediate queue and the presence of sufficient memory space in said output queue to store said buffer's worth of information, with said intermediate controller configured to transfer said buffer's worth of information to said output queue in response to said determination.