Patent ID: 8390743

Claim:
A video system comprising: a plurality of video sources corresponding to a plurality of input channels, the plurality of video sources configured to generate a plurality of video signals related to a plurality of video frames; a display including a plurality of display locations; a memory including a plurality of memory locations configured for storing the plurality of video frames, each of the memory locations corresponding to one of the plurality of display locations within the display; and a controller connected to the plurality of video sources, the display, and the memory, the controller configured to receive the plurality of video frames, the controller including a write control module including a write pointer, the write control module configured to write a first video frame to the memory, a second video frame to the memory, and a third video frame to the memory, a read control module including a read pointer, the read control module configured to read at least one of the first video frame, the second video frame, and the third video frame from the memory, and a frame rate control module configured to control writing operations of the write control module and reading operations of the read control module based on a read memory location of the read pointer with respect to a write memory location of the write pointer, wherein the frame rate control module synchronizes the read pointer with the write pointer to maintain the read memory location of the read pointer a set number of frames behind the write memory location of the write pointer, wherein the at least one of the first video frame, the second video frame, and the third video frame read from the memory by the read control module is displayed in a corresponding one of the plurality of display locations within the display.