Patent ID: 8204704

Claim:
A MOS capacitance test structure comprising: a first semiconducting device comprising a first plurality of MOS transistors, each transistor of the first plurality of MOS transistors having a gate electrically connected to a first node, and a source and a drain both electrically connected to a second node; and a second semiconducting device, comprising a second plurality of MOS transistors of the same transistor type as the first plurality of MOS transistors, each transistor of the second plurality of MOS transistors having a gate electrically connected to a third node, and a source and a drain both electrically connected to a fourth node, wherein: a sum of the lengths of each transistor of the first plurality of MOS transistors is substantially the same as the sum of the widths of each transistor of the second plurality of MOS transistors, so that a surface area difference S equiv between the first and second semiconducting device is nonzero, as determined in accordance with the following relationship: S equiv =Σ( L i ×W i )−Σ( L′ i ×W′ i ), where: L i , W i respectively denote the length and the width of a transistor T i of the first semiconducting device; L′ i , W′ i respectively denote the length and the width of a transistor T′ i of the second semiconducting device; and x indicates multiplication.