Patent ID: 8039889

Claim:
A non-volatile memory device, comprising: a semiconductor substrate including a first section having a substantially planar first top surface, a second section having a substantially planar second top surface that is closer to a bottom surface of the substrate than is the first top surface, and a sidewall extending between the first and second top surfaces; a charge storage pattern on the first and second top surfaces of the substrate and extending along the sidewall therebetween; a source region in the first section of the substrate extending from the first top surface into the second section of the substrate and having a stepped portion defined by the sidewall and the second top surface; and a drain region in the second section of the substrate extending from the second top surface toward the bottom surface of the substrate, wherein the source region and the drain region are asymmetrical in cross-section, wherein the drain region has a substantially planar surface facing an overall bottom surface of the charge storage pattern and a different upper surface from the source region, wherein an entirety of the drain region is confined below the substantially planar second top surface of the second section of the substrate, and wherein the source region extends toward the bottom surface of the substrate beyond the drain region.