Patent ID: 7045903

Claim:
A semiconductor device comprising: a semiconductor substrate; an active circuit fabricated on said substrate and comprised of an integrated power transistor, said circuit having at least one metallization layer forming a plurality of first and second electrodes of said transistor; a first bus connecting all of said first electrodes, and a second bus connecting all of said second electrodes, each bus connected to said respective electrode by metal-filled vias, whereby said buses are positioned directly over said transistor; a mechanically strong, electrically insulating film overlaying said circuit, said transistor, and said buses; a plurality of contact pads distributed over each of said buses, each of said pads having a stack of stress-absorbing metal layers, the outermost layer being metallurgically attachable, and a connection to the underlying bus through openings in said insulating film, said openings positioned substantially vertically over at least one of said vias; and at least one connecting member attached to said contact pads, whereby the electrical current path and resistance from said member to said electrodes are minimized, improving the electrical characteristics of said power transistor.