Patent ID: 6927440

Claim:
An interconnection wiring system containing at least one capacitor comprising: a substrate having a planar upper surface of insulating and conductive regions therein, a first level of interconnection wiring interconnecting said conductive regions, a first dielectric layer formed over said first level of interconnection wiring, said first dielectric layer having an upper surface and having visa therein filled with conductive material to said upper surface and in contact with regions of said first level of interconnection wiring, wherein at least one of said vias having dimensions to form said lower electrode of a capacitor and each via, including said lower electrode of said capacitor, has an upper surface that is coplanar to said upper surface of said first dielectric layer, a second dielectric layer formed over said lower electrode and extending beyond the perimeter of said lower electrode, and a second level of interconnection wiring interconnecting the vias filled with conductive material and formed over the second dielectric layer to form said top electrode of said capacitor.