Patent ID: 8288206

Claim:
A method of making a circuit structure comprising: forming from a semiconductor wafer or portion thereof a first unitary substrate with a first surface; forming from a semiconductor wafer or portion thereof a second unitary substrate with a first surface and a second surface, wherein the second surface is opposite said first surface of the second unitary substrate; forming a dielectric layer over the first surface of at least one of the first and second unitary substrates, the dielectric layer having a stress of 5Ã—10 8 dynes/cm 2 or less; bonding the first surface of the first unitary substrate to one of the first surface and the second surface of the second unitary substrate; thinning the second unitary substrate to form the second surface; and, forming at least one vertical interconnection, wherein the at least one vertical interconnection extends vertically through the second unitary substrate, and forming a dielectric material having a stress of about 5Ã—10 8 dynes/cm 2 or less isolating the vertical interconnection from said second unitary substrate.