Patent ID: 7808270

Claim:
A semiconductor device with an output circuit, the output circuit comprising: a terminal; a plurality of first unit buffers coupled to the terminal, each of the first unit buffers having an adjustable impedance and driving, when activated, the terminal to one of first and second logic levels with an adjusted impedance; a first control circuit adjusting an impedance of each of the first unit buffers to represent the adjusted impedance; a second control circuit activating selected one or ones of the first unit buffers, the selected one or ones of the first unit buffers cooperating with each other to drive the terminal to one of the first and second logic levels, and a plurality of second unit buffers coupled to the terminal, each of the second unit buffers having an adjustable impedance and driving, when activated, the terminal to one of the first and second logic levels with an adjusted impedance, wherein: the first control circuit further adjusts an impedance of each of the second unit buffers to represent the adjusted impedance, and the output circuit includes a first operation mode in which selected one or ones of the second unit buffers are activated in addition to the selected one or ones of the first unit buffers by the second control circuit to drive the terminal to one of the first and second logic levels through the selected ones of the first and second unit buffers and a second operation mode in which each of the first unit buffers is deactivated and selected one or ones of the second unit buffers serve to represent an impedance at the terminal.