Patent ID: 8680520

Claim:
A semiconductor device comprising: a source line; a bit line; a signal line; and a word line, wherein a plurality of memory cells are connected in parallel between the source line and the bit line, wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor, wherein the first transistor is provided in a substrate containing a semiconductor material, wherein the second transistor comprises an oxide semiconductor layer, wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another, wherein the source line and one of the first source electrode and the first drain electrode are electrically connected to each other, wherein the bit line and the other of the first source electrode and the first drain electrode are electrically connected to each other, and wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.