Patent ID: 7349937

Claim:
An incrementer, comprising: a 4-bit zero detection unit, wherein said 4-bit detection unit groups every 4 bits of an operand, starting from the least significant bit (LSB), determines whether each 4-bit group includes a first logic state, and outputs a second logic state as first logic state inclusion information for each 4-bit group if the 4-bit group includes the first logic state and outputs the first logic state as first logic state inclusion information for each 4-bit group if the 4-bit group does not include the first logic state; a flag information generation unit, wherein said flag information generation unit outputs flag information for each 4-bit group by generating the first logic state for the first group with the second logic state, starting from the LSB of the first logic state inclusion information for each 4-bit group, and for the following lower order groups, and by generating the second logic state for higher order groups preceding the first group with the second logic state; a 4-bit increment unit, wherein said 4-bit increment unit receives the operand and performs an increment on each 4-bit group; and an increment output unit, wherein said increment output unit performs a logical combination on the operand, the first logic state inclusion information for each 4-bit group, the flag information for each 4-bit group, and an increment value for each 4-bit group, and generates a whole increment value by outputting 4 bits of the first logic state for each 4-bit group, 4 bits of the operand for each 4-bit group, or 4 bits of the increment value for each 4-bit group.