Patent ID: 8669596

Claim:
A semiconductor device, comprising: a first active region; a second active region; an isolation region between the first active region and the second active region; a plurality of first gate patterns that extend in a first direction and are arranged with intervals in a second direction orthogonal to the first direction; and a plurality of second gate patterns that extend in the first direction and are arranged with intervals in the second direction, wherein: ends of the plurality of first gate patterns are aligned to and face ends of the plurality of second gate patterns, respectively, the ends of the plurality of first gate patterns are arranged in a staggered manner in the second direction, and the ends of the plurality of second gate patterns are arranged in a staggered manner in the second direction, the plurality of first gate patterns include a first gate pattern and the plurality of second gate patterns include a second gate pattern, the first gate pattern and the second gate pattern being aligned in the first direction so that an end of the first gate pattern faces an end of the second gate pattern, the first gate pattern is disposed on the first active region and the isolation region, and the second gate pattern is disposed on the second active region and the isolation region, a length in the first direction of the first gate pattern on the isolation region is longer than a length in the first direction of the second gate pattern on the isolation region, and an end portion of the first gate pattern disposed on the isolation region is thinner, in the second direction, than an end portion of the second gate pattern disposed on the isolation region.