Patent ID: 7911857

Claim:
A device comprising: a memory configured to store data; and a memory controller connected to the memory via a plurality of data lines, for receiving data signals, and a strobe line, for receiving a strobe signal used to control reading of the data lines, the memory controller including a preamble detection circuit to receive the strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of a read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal, a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and control logic to set an amount of the selectable delay period for the preamble detection circuit, where the control logic is to determine the amount of the selectable delay period during a training cycle in which the strobe signal is sampled over a plurality of data read cycles, and in which, during different ones of the plurality of data read cycles, the selectable delay period is set to different values, and where the control logic is to perform the training cycle when the device is initially powered-up or reset.