Patent ID: 8304824

Claim:
A semiconductor device comprising: an isolation layer for defining a plurality of active areas of a substrate, wherein the isolation layer is disposed on the substrate; a plurality of buried word lines having upper surfaces lower than the upper surfaces of the active areas, being surrounded by the active areas, and extending in a first direction parallel to a main surface of the substrate; a gate dielectric film interposed between the buried word lines and the active areas; and a plurality of buried bit lines having upper surfaces lower than the upper surfaces of the plurality of buried word lines, being parallel to the main surface of the substrate, and extending in a second direction that differs from the first direction, wherein the isolation layer has a network structure comprising a plurality of first isolation portions and a plurality of second isolation portions, the plurality of first isolation portions extending in the second direction and the plurality of second isolation portions crossing the plurality of first isolation portions and extending in the first direction, and the distance from the upper surfaces of the active areas to the lower surfaces of the first isolation portions is greater than the distance from the upper surfaces of the active areas to the lower surfaces of the second isolation portions.