Patent ID: 7227211

Claim:
A semiconductor integrated circuit, comprising: a plurality of logic cells for constituting a logic, each logic cell comprising a MOS transistor which has source and drain regions of a second conductivity type formed on a surface of a first substrate region of a first conductivity type, and a MOS transistor which has source and drain regions of the first conductivity type formed on a surface of a second substrate region of the second conductivity type respectively; a first power supply interconnection for supplying a first power supply potential to said plurality of logic cells; a second power supply interconnection for supplying a second power supply potential to said plurality of logic cells; and a decoupling capacitor, disposed between said first power supply interconnection and said second power supply interconnection for preventing supply voltage drop of said plurality of logic cells, comprising a MOS transistor which has source and drain regions of the second conductivity type formed on a surface of a third substrate region of the first conductivity type and a gate region, wherein: said first power supply potential is supplied to the source and drain regions of said MOS transistor of said decoupling capacitor and said second power supply potential is supplied to the gate region of said MOS transistor of said decoupling capacitor, an interconnection for providing a potential to said third substrate region of said decoupling capacitor and an interconnection for providing a potential to the source and drain regions of said MOS transistor of said decoupling capacitor are electrically isolated and potentials of said third substrate region and said source and drain regions of said MOS transistor of said decoupling capacitor are controlled independently, an interconnection for providing a potential to said first substrate region of said logic cells and an interconnection for providing a potential to the source region of said MOS transistor which has source and drain regions of the second conductive type of said logic cells are electrically isolated, and the potential provided to said third substrate region of said decoupling capacitor and the potential provided to said first substrate region of said logic cells are controlled independently.