Patent ID: 7447606

Claim:
A method for separating integrated circuit (IC) variables comprising the steps of: testing an IC wafer fabricated with a particular process and having a plurality of channel length groups of field effect transistor (FET) devices wherein each group is fabricated to have a different effective channel length (Leff); measuring a threshold voltage (VT) of a statistically large number of the FET devices in each of the channel length groups at a first drain-to-source-voltage (VDS) and at a second VDS greater than the first VDS; calculating a mean value of VT for the FET devices corresponding to each of the plurality of channel length groups at the first and second VDS; calculating total variances of VT of the FET devices from the channel length groups measured at the first VDS and the second VDS; calculating a slope coefficient λ relating VT to Leff as a ratio with a numerator equal to a difference in the means of VT of the FET devices from two channel length groups and a denominator equal to a difference in channel lengths of the two channel length groups; calculating, for the particular process, a variance of Leff as a ratio with a numerator equal to a difference between the square of coefficient λ determined at the second VDS and the square of coefficient λ determined at the first VDS and a denominator equal to a difference between the total variance of VT at the second VDS and the total variance of VT at the first VDS; and calculating, for the particular process, a variance of VT with respect to dopant levels as a difference between the total variance of VT calculated at the first VDS value and a product of the square of the slope coefficient λ determined at the first VDS value times the variance of Leff.