Patent ID: 8648626

Claim:
A clock generator, comprising: a first accumulator, comprising a first input terminal, a second input terminal, a first control terminal, a first sum output terminal and a first overflow output terminal, wherein the second input terminal is coupled to the first sum output terminal; an oscillating signal generating circuit, generating a first oscillating signal and adjusting a frequency of the first oscillating signal according to a first overflow output signal of the first overflow output terminal of the first accumulator, wherein the oscillating signal generating circuit comprises at least one current source, and the frequency of the first oscillating signal is adjusted by increasing or decreasing at least one current provided by the at least one current source according to the first overflow output signal; and a frequency adjustment circuit, generating a frequency control value according to the first oscillating signal and a reference oscillating signal, and comprising: a frequency comparator, comparing frequencies of the first oscillating signal and the reference oscillating signal, and generating a frequency comparison result; and a second accumulator, comprising a third input terminal, a fourth input terminal, a second control terminal and a second sum output terminal, wherein the fourth input terminal is coupled to the second sum output terminal, the frequency comparison result is received at the third input terminal, the second control terminal is coupled to the reference oscillating signal so that the second accumulator accordingly accumulates the frequency comparison result, and provides the frequency control value at the second sum output terminal, wherein the frequency control value is received at the first input terminal of the first accumulator, and the first oscillating signal is received at the first control terminal so that the first accumulator accordingly accumulates the frequency control value to generate the first overflow output signal.