Patent ID: 8217820

Claim:
A signal processing circuit comprising: a. a converting circuit configured to receive an input analog signal and to output a pulse width modulated signal corresponding to the analog signal; b. a delay line coupled to the converting circuit to receive the pulse width modulated signal, wherein the delay line comprises one or more delay line taps, each delay line tap configured to output a delayed version of the pulse width modulated signal; c. a scaling circuit coupled to the converting circuit and to the one or more delay line taps, where the scaling circuit is configured to scale the pulse width modulated signal and each of the one or more delayed versions of the pulse width modulated signal, thereby forming multiple scaled pulse width modulated signals; and d. a summing and integration circuit coupled to the scaling circuit, wherein the summing and integration circuit is configured to receive the multiple scaled pulse width modulated signals, to sum the multiple scaled pulse width modulated signals into a multiple-level pulse width modulated signal, and to convert the multiple-level pulse width modulated signal to an output analog signal.