Patent ID: 8902676

Claim:
A semiconductor memory comprising a memory array having memory cells coupled to wordlines and bitlines, each wordline having a left end extending out a left side of the memory array and an opposing right end extending out a right side of the memory array, a first wordline in every two adjacent wordlines having its left end connected to a left row driver located on the left side of the memory array and having its right end connected to a right clamp circuit located on the right side of the memory array, and a second wordline in every two adjacent wordlines having its right end connected to a right row driver located on the right side of the memory array and having its left end connected to a left clamp circuit located on the left side of the memory array, wherein the right clamp circuits are configured to selectively connect the first wordlines to a reference potential based on a right control signal, and wherein the left clamp circuits are configured to selectively connect the second wordlines to the reference potential based on a left control signal.