Patent ID: 8332698

Claim:
A method for performing a scan operation on a scan flop having a scan input and a scan output, and comprising a first latch and a second latch, the method comprising: during each clock cycle of a specified number of clock cycles of a first clock signal, wherein the clock cycle has a low phase and a high phase: when a scan control signal is in a first state for at least the duration of the high phase of the clock cycle, or for at least the duration of the low phase of the clock cycle, or for the duration of the clock cycle: capturing scan data through the scan input of the scan flop via a first multiplexer into the first latch during the low phase of the clock cycle, wherein the scan flop is coupled to provide test stimulus data to internal logic circuitry of an integrated circuit (IC), the internal logic circuitry being configured to perform one or more logic functions; and shifting the captured scan data from the first latch into the second latch during the high phase of the clock cycle; when the scan control signal is in a second state for at least the duration of the high phase of the clock cycle, capturing input data through a data input of the scan flop via a second multiplexer into the second latch according to a second clock signal; and when the scan control signal is in the second state for at least the duration of the low phase of the clock cycle: capturing the input data through the data input of the scan flop via the first multiplexer into the first latch during the low phase of the clock cycle; and shifting the captured input data from the first latch into the second latch according to the second clock signal.