Patent ID: 7415685

Claim:
A method of verifying a power off effect of a design entity of a digital system, the method comprising: in a hardware definition language, specifying a device model at a register transfer level (RTL), the device model describing function blocks for performing predetermined functions using a plurality of power sources having different voltage levels, and including a model for a case where all of the plurality of power sources are supplied and a model for a case where one or more of the plurality of power sources are blocked to the device model; specifying a test input signal model at the RTL describing a test input signal to be input to the device model to verify a case where all of the plurality of power sources are supplied to the device model and a case where one or more of the plurality of power sources are blocked to the device model; and specifying a test output signal model at the RTL describing a test output signal to be output from the device model, including data anticipated to be output in response to the test input signal where all of the plurality of power sources are supplied to the device model and data anticipated to be output in response to the test input signal where one or more of the plurality of power sources are blocked.