Patent ID: 7542532

Claim:
An I/O interface circuit comprising: a clock generation circuit generating a first clock signal; a jitter generator generating jitter in the first clock signal based on a setting signal, which sets a present condition of the jitter; a data transmission circuit transmitting data in sync with the first clock signal including the jitter; a data reception circuit receiving the transmitted data, wherein the clock generation circuit also supplies a second clock signal to the data reception circuit; wherein the data transmission circuit comprises: a pattern generation circuit generating a data pattern for a jitter resistance test, and transmission circuitry allowing the data pattern generated by the pattern generation circuit to be transmitted in sync with the first clock signal, and wherein the data reception circuit comprises: reception circuitry allowing the data pattern transmitted by the transmission circuitry to be received in sync with the second clock signal, and a pattern comparison circuit comparing the data pattern received by the reception circuitry with an expectation value to output a comparison result, and a jitter generator control circuit controlling the jitter generator to vary an amount of modulation or the frequency of the jitter in accordance with the comparison result delivered by the pattern comparison circuit and a measurement procedure for the jitter resistance test.