Patent ID: 7669092

Claim:
An apparatus comprising: a memory device configurable as a plurality of erase block groups including a base erase block group, wherein each of the plurality of erase block groups comprises a plurality of erase blocks, each of the plurality of erase blocks identified by a matching unique erase block number that is unique within the plurality of erase blocks within the erase block group and that is matching across the plurality of erase block groups; and a mapping table coupled to the plurality of erase block groups, the mapping table to store at least one group address number corresponding to one of the matching unique plurality of erase block numbers identifying a non-defective erase block in the base erase block group, and corresponding to several of the matching unique plurality of erase block numbers identifying a single non-defective erase block in each of the plurality of erase block groups other than the base erase block group, wherein at least one of the several includes one of the matching unique plurality of erase block numbers identifying a defective erase block in the base erase block group, and wherein not all of the erase blocks corresponding to the group address number have a same matching unique erase block number.