Patent ID: 7982640

Claim:
A digital signal transmitting apparatus comprising: an encoder which converts parallel input signals of a plurality of channels into serial data in a manner synchronized with a first clock signal; and a decoder which converts the serial data into parallel output signals of the plurality of channels in a manner synchronized with a second clock signal operating in a manner asynchronous with the first clock signal, wherein the serial data has a different period and a different duty factor corresponding to each combination of the logical values of the parallel input signals of the plurality of channels, the number of times of the logical value of the serial data shifting from a high level to a low level or shifting from a low level to a high level in a length of time of one period of the serial data is one, and the decoder includes: a counter which counts whether the logical value of the serial data is a high level or a low level at a point in time when the second clock signal rises or falls; and a discriminator which converts the serial data into the parallel output signals of the plurality of channels based on the count result of the counter corresponding to one period or a plurality of periods of the serial data.