Patent ID: 7414281

Claim:
A flash memory cell comprising: a substrate comprising a source and a drain; a silicon dioxide layer adjoining said substrate; a dielectric layer adjoining said silicon dioxide layer, said dielectric layer comprising a dielectric material having a dielectric constant greater than that of silicon dioxide, wherein said dielectric material comprises a metal oxide; a polysilicon floating gate adjoining said dielectric layer; an oxide-nitride-oxide (ONO) layer adjoining said floating gate; and a control gate adjoining said ONO layer, wherein said substrate, said silicon dioxide layer, said dielectric layer, said floating gate, said ONO layer and said control gate are arranged in a laminate structure, wherein said silicon dioxide layer is sandwiched between said substrate and said dielectric layer, wherein said dielectric layer is sandwiched between said silicon dioxide layer and said floating gate, and wherein said ONO layer is sandwiched between said floating gate and said control gate.