Patent ID: 7982244

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a first block having a plurality of first memory cells provided on the semiconductor substrate and a plurality of first select transistors provided on the semiconductor substrate and serially connected to ends of current paths of the first memory cells; a second block having a plurality of second memory cells provided on the semiconductor substrate and a plurality of second select transistors provided on the semiconductor substrate and serially connected to ends of current paths of the second memory cells, the second block being arranged adjacent to the first block in a first direction, one of the second select transistors being arranged to face one of the first select transistors and commonly having a diffusion region with the first select transistor; a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction perpendicular to the first direction; and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.