Patent ID: 7202117

Claim:
A method of making a double-gated transistor, comprising: forming a patterned pre-transistor stack with stack sidewalls, wherein the pre-transistor stack is disposed on an insulating layer, the pre-transistor stack including a first semiconductor layer overlying the insulating layer, a second semiconductor layer overlying the first semiconductor layer, and an oxidation resistant layer overlying the second semiconductor layer; forming sidewall insulators on first semiconductor layer sidewall portions and second semiconductor layer sidewall portions of the stack sidewalls, wherein the sidewall insulators of the first semiconductor layer portions comprise a thickness greater than a thickness of the sidewall insulators of the second semiconductor layer portions; removing the sidewall insulators on the second semiconductor layer portions, wherein removing the sidewall insulators exposes corresponding sidewall portions of the second semiconductor layer; forming in-situ doped epitaxial source/drain regions, wherein forming the in-situ doped epitaxial source/drain regions includes originating an epitaxial growth of a single crystal semiconductor material at the exposed sidewall portions of the second semiconductor layer; removing the oxidation resistant layer of the patterned, pre-transistor stack, wherein removing the oxidation resistant layer exposes a first gate location portion of the second semiconductor layer; forming an insulating liner overlying portions of exposed in-situ doped epitaxial source/drain regions and the exposed first gate location portion of the second semiconductor layer; removing a portion of the insulating liner overlying the exposed first gate location portion of the second semiconductor layer; patterning the patterned pre-transistor stack and the in-situ doped epitaxial source/drain regions into a transistor region along a corresponding width dimension of the transistor and exposing the first semiconductor layer at opposite ends of the transistor region; removing the first semiconductor layer to create an opening, wherein the opening exposes a second gate location portion of the second semiconductor layer; forming a gate dielectric on the second semiconductor layer, the gate dielectric overlying at least the first and second gate location portions of the second semiconductor layer; and forming a gate electrode on the gate dielectric overlying at least the first and second gate location portions of the second semiconductor layer.