Patent ID: 6978359

Claim:
A microprocessor comprising: a register file including a plurality of registers, the register file configured to store data to be used for operations; a first source register configured to store a first register value; a second source register configured to store a second register value; a data memory configured to store data; an execution unit configured to execute a first load instruction that has a field specifying a first register in the register file, a field specifying a second register in the register file, and a field specifying a first immediate value, load first data, to the first register, from the data memory based on a value in the second register and the first immediate value, execute a second load instruction that has a field specifying a third register in the register file, a field specifying the second register, and a field specifying a second immediate value, load second data, to the third register, from the data memory based on a value in the second register and the second immediate value, execute a set SAR byte instruction that has a field specifying the second register and a field specifying a third immediate value that is the lower two bits of the first immediate value, and calculate a shift amount based on a value stored in the second register and the third immediate value; a shift amount register configured to store the calculated shift amount; and a shift unit configured to load the first data to the first source register and the second data to the second source register, concatenate the first and the second data in the first and the second source register, and shift the concatenated result by the shift amount stored in the shift amount register.