Patent ID: 7582529

Claim:
A method of making non-volatile memory, comprising: forming a first layer of charge storage material at a peripheral circuitry region of a substrate and a memory array region of the substrate; forming a second layer of charge storage material at the peripheral circuitry region and the memory array region; etching the first layer at the array region to form a first set of strips of charge storage material elongated in a first direction with spaces therebetween in a second direction substantially perpendicular to the first direction; etching the second layer at the array region to form a second set of strips of charge storage material elongated in the first direction with spaces therebetween in the second direction; forming a third set of strips of conductive material elongated in the first direction and at least partially occupying the spaces between adjacent strips of the second layer of charge storage material; etching the first set of strips, the second set of strips and the third set of strips along their lengths in the first direction thereby forming a set of first charge storage regions from each strip of the first set, a set of second charge storage regions from each strip of the second set and a set of control gates from each strip of the third set; etching the first layer of charge storage material and the second layer of charge storage material at the peripheral circuitry region to define a dimension of a gate region for a transistor after etching the sets of strips at the memory array region, the gate region including a portion of the first layer of charge storage material and a portion of the second layer of charge storage material.