Patent ID: 8105877

Claim:
A method of fabricating a stacked type chip package structure, the method comprising: providing a first wafer, wherein the first wafer has a plurality of first chip units, and a plurality of first bumps are disposed on each of the first chip units; cutting the first wafer, such that each of the first chip units forms a first chip, respectively; providing a second wafer that has a plurality of second chip units; respectively bonding the first chips to the second chip units of the second wafer, such that each of the first chips is electrically connected to the corresponding second chip unit through the first bumps; filling between each of the first chips and the corresponding second chip unit with a first underfill, such that the first underfill encapsulates the first bumps; polishing back surfaces of the first chips to remove a portion of each of the first chips; forming a plurality of second bumps on a surface of each of the second chip units after polishing the back surfaces of the first chips, wherein said surface of each of the second chip units accommodates the first chip; cutting the second wafer, such that each of the second chip units respectively forms a second chip, wherein each of the second chips, the first chip, the first bumps, and the first underfill constitute a package structure; disposing the package structure above a corresponding substrate in a reverse manner and bonding the package structure to the corresponding substrate, such that the second chip of the package structure is electrically connected to the corresponding substrate through the second bumps; and filling between the second chip and the corresponding substrate with a second underfill, so as to encapsulate the second bumps, the first chip, and the first underfill.