Patent ID: 7089371

Claim:
A microprocessor apparatus, providing for allocation and initialization of a block of data from memory, the apparatus comprising: translation logic, configured to translate a block allocate and initialize instruction into a micro instruction sequence that directs a microprocessor to prefetch a specified number of cache lines in an exclusive state and to initialize said specified number of said cache lines to aspecified value, wherein said block allocate and initialize instruction is encoded to direct said microprocessor to prefetch said specified number of cache lines in said exclusive state and to initialize said specified number of cache lines to said specified value; and execution logic, coupled to said translation logic, configured to receive said micro instruction sequence, and configured to issue transactions over a memory bus that requests said specified number of said cache lines in said exclusive state, and configured to initialize said specified number of cache lines to said specified value, wherein the allocation and initialization of said specified number of cache lines occurs in parallel with execution of other instructions in a program flow of an application program.