Patent ID: 8264048

Claim:
An apparatus, comprising: a semiconductor substrate; at least one multi-gate fin coupled with the semiconductor substrate, the at least one multi-gate fin comprising a first side, a second side, a third side and a fourth side, the fourth side of the at least one multi-gate fin being adjacent to the semiconductor substrate, the multi-gate fin further comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions; a gate electrode coupled to a gate dielectric, the gate electrode comprising a first portion comprising a first thickness and a second portion comprising a second thickness, the second thickness being greater than the first thickness, the first and second thicknesses extending between the source and drain regions, the first portion of the gate electrode comprising surfaces that correspond to a first part of the first, second and third sides of the at least one multi-gate fin and the second portion of the gate electrode comprising surfaces that correspond to a second and a third part of the first, second and third sides of the at least one multi-gate fin, the first part of the first, second and third sides of the at least one multi-gate fin being disposed between the second and third parts of the first, second and third sides of the at least one multi-gate fin, and a cross-section of the gate electrode along the multi-gate fin having a substantially T-shaped structure; and the gate dielectric being coupled to the first, second and third parts of the first, second and third sides of the gate region of the multi-gate fin and the gate electrode between the gate region of the multi-gate fin and the gate electrode, the gate dielectric being coupled to the surfaces of the first portion of the gate electrode corresponding to the first, second and third sides of the gate region of the at least one multi-gate fin, and to the surfaces of the second portion of the gate electrode corresponding to the first, second and third sides of the gate region of the at least one multi-gate fin.