Patent ID: 6881999

Claim:
A semiconductor device comprising: a bottom plate electrode disposed on a predetermined region of a semiconductor substrate; an upper plate electrode overlapped with the bottom plate electrode such that a first portion of the bottom plate electrode protrudes laterally from under the upper plate electrode; a capacitor dielectric layer interposed between the bottom plate electrode and the upper plate electrode, the capacitor dielectric layer comprising a middle dielectric layer interposed between the bottom plate electrode and the upper plate electrode; an interlayer dielectric layer formed on the upper plate electrode and the bottom plate electrode; and an upper dielectric layer conformally interposed between the upper plate electrode and the dielectric layer; a bottom electrode plug and an upper electrode plug which are connected to the bottom plate electrode and the upper plate electrode, respectively, through the interlayer dielectric layer, the bottom electrode plug also penetrating the middle dielectric layer to contact the first portion of the bottom plate electrode protruding laterally from under the upper plate electrode, and the upper electrode plug also penetrating the upper dielectric layer to contact the upper plate electrode, wherein the upper plate electrode and the bottom plate electrode are formed of a metal compound.