Patent ID: 8396937

Claim:
A system comprising: a first node comprising a first wiretap circuitry and a first memory, wherein the first memory comprises a primary portion; a second node comprising a second memory, wherein the second memory comprises a replica portion configured to persistently maintain an up to date copy of all data stored in said primary portion, wherein the second node is coupled to the first node via an interconnect; wherein the first wiretap circuitry is configured to: detect all memory accesses which cause changes to data stored in the primary portion; and convey identifying data which identifies said changes to the second node; wherein the second node, in response to receiving the identifying data, is configured to: modify data stored in the replica portion to reflect said changes, thereby maintaining an up to date copy of data stored in the primary portion; and update an undo log in the second memory to reflect said modification to the replica portion; wherein in response to detecting a transaction commit operation, the first wiretap circuitry is further configured to: convey a first indication to a processing unit in the first node which causes the processing unit to evict all modified data within one or more caches within the processing unit, wherein the modified data represents data not stored in the primary portion or the replica portion, wherein in response to the eviction of the modified data, the data stored in the primary portion is updated with the modified data; and receive and convey the modified data to the second node, in response to the eviction of the modified data, wherein the replica portion is updated with the modified data; and wherein the first indication further causes read only data within the one or more caches to be invalidated, wherein the read only data is a copy of data stored in the primary portion and corresponds to memory accesses which do not cause changes to data stored in the primary portion.