Patent ID: 7751243

Claim:
A semiconductor memory device comprising: memory cell transistors which are formed on a semiconductor layer, each of the memory cell transistors having a stacked gate including a charge accumulation layer and a control gate, the memory cell transistors being capable of retaining “0” data or “1” data based on whether or not a charge is injected into the charge accumulation layer; a memory cell group in which current passages of the memory cell transistors are connected in series; a selection transistor which has a current passage connected in series to one of the memory cell transistors located closest to a drain side in the memory cell group; a memory cell array in which the memory cell group and the selection transistor are arranged; a bit line which is connected to a drain of the memory cell transistor through the current passage of the selection transistor; a page buffer which is adopted to apply a first voltage to the bit line connected to the memory cell transistor in which the “0” data is to be programmed and apply a second voltage larger than the first voltage to the bit line connected to the memory cell transistor in which the “1” data is to be programmed, when the selection transistor is turned on, in a write operation of the data, the page buffer being adopted to put the bit line into electrically floating state after the first voltage and the second voltage are applied; a word line which is connected to the control gate of the memory cell transistor; and a row decoder which is adopted to apply a positive third voltage to the semiconductor layer, select the word line connected to the memory cell transistor to be programmed, and apply a program voltage to the selected word line when the bit line is in the electrically floating state.