Patent ID: 7437540

Claim:
A single chip architecture for a digital signal processor (DSP) capable of performing operations on floating-point data in a complex domain, said single chip architecture comprising: a program memory coupled to a local sequencer having an instruction decoder, a condition generator, a status register, and a program counter, said program memory further coupled to a data/program bus multiplexer; a very large instruction word (VLIW) DSP core coupled to said program memory, and to said local sequencer, said VLIW DSP core having a multiple address generation unit coupled to an address register file and a data register file, said data register file coupled to said multiple address generation unit, to said address register file, and to an operator block, said operator block coupled to said address register file, and to said multiple address generation unit, said operator block having a first operator block portion and a second operator block portion coupled to each other, each of said first and said second operator block portions having a first and a second floating point/integer multiplier, a floating point/integer complex adder, and a floating point/integer adder, said first and said second floating point/integer multipliers coupled to said floating point/integer complex adder, said floating point/integer adder coupled to said complex adder and to said data register file, said floating point/integer complex adder having a first adder portion and a second adder portion; a direct memory access (DMA) controller coupled to said local sequencer and said data/program bus multiplexer; a microprocessor interface coupled to a shared memory, said shared memory further coupled to a data memory; and a data buffer coupled to said data/program bus multiplexer, to said data memory, to said VLIW DSP core, and to said shared memory, wherein said single chip architecture is formed on a single integrated circuit chip.