Patent ID: 7193430

Claim:
A semiconductor integrated circuit device with a filter circuit serving for eliminating a glitch contained in a logic signal supplied to the device, wherein said filter circuit comprises: a first delay circuit activated within a certain period after each rising edge timing of input logic signals to delay the rising edge; a second delay circuit activated within a certain period after each falling edge timing of said input logic signals to delay the falling edge; and an output driver controlled by outputs of said first and second delay circuits to output delayed logic signals to an output node in response to said input logic signals, wherein said first and second delay circuits each comprise a current-mirror differential amplifier configured to be activated within a certain period after each rising edge timing of one of two species of signals with complementary levels generated based on said input logic signal, a first inverter to which one of said two species of signals with complementary levels generated based on said input logic signals are input, said first inverter having a current source transistor driven by a reference voltage to limit output discharge current of said first inverter, and a capacitor coupled to an output of said first inverter, wherein said current-mirror differential amplifier is configured to be activated within a certain period after each rising edge timing of said one of two species of signals for detecting an output voltage of said first inverter in comparison with said reference voltage.