Patent ID: 7893725

Claim:
A phase detector circuit for providing non-overlapping charge up and charge down control signals having first and second logic levels, comprising: a first detecting circuit for driving a first control signal to the first logic level when a reference clock signal is detected and to the second logic level when a feedback clock signal is detected, the first detecting circuit providing a second control signal complementary to the first control signal; a second detecting circuit for driving a third control signal to the first logic level when the reference clock signal is detected and to the second logic level when a phase shifted clock signal is detected; a logic circuit for receiving the first control signal, the second control signal and the third control signal, the logic circuit driving the charge down signal and the charge up signal at the first logic level while the first control signal is at the first logic level, the second control signal is at the second logic level, and the third control signal is at the first logic level, the logic circuit driving the charge down signal and the charge up signal at the second logic level in response to the first control signal at the second logic level and the second control signal being at the first logic level, the charge up signal being driven at the first logic level in response to the third control signal at the second logic level while the second control signal is at the first logic level.