Patent ID: 8624325

Claim:
A semiconductor device, comprising: a semiconductor substrate having a first region and a second region; a first gate structure belonging to a pMOS device on the first region and comprising: a first interface layer, a first gate dielectric layer, and a first work function metal gate layer formed on the first region of the substrate, wherein the gate dielectric layer of the first gate structure comprises a high-k dielectric; a second gate structure belonging to an nMOS device on the second region and comprising a second interface layer, a second gate dielectric layer, and a second work function metal gate layer formed on the second region of the substrate, wherein the gate dielectric layer of the second gate structure comprises a high-k dielectric; wherein the thickness of said first and second interface layers is in the range of about 0.2-1 nm; a multi-layer first sidewall spacer on sidewalls of the first gate structure, wherein a layer of the multi-layer first sidewall spacer adjacent to the first gate structure is formed by at least one element selected from a group consisting of SiON x , HfO 2 , Al 2 O 3 , Y 2 O 3 , and any combination thereof, and has a thickness in the range of about 2-3 nm; and a multi-layer second sidewall spacer on sidewalls of the second gate structure, wherein a layer of the multi-layer second sidewall spacer adjacent to the second gate structure is formed by at least one element selected from a group consisting of AlN x , Hf 3 N 4 , Ta 3 N 5 , and any combination thereof, and has a thickness in the range of about 10-15 nm; wherein every oxide layer within said first and second multi-layer sidewall spacers is I-shaped.