Patent ID: 7675808

Claim:
A semiconductor device comprising: a memory; a memory input bus signal line through which a signal is input to the memory; and a memory output bus signal line through which a signal from the memory is output, wherein the memory comprises: a first memory block, a second memory block, a third memory block and a fourth memory block each of which comprises a plurality of memory cells; a control circuit comprising an operation control circuit, an input signal control circuit, and an output signal control circuit, wherein the operation control circuit selects one of the memory blocks to be operated, wherein the input signal control circuit generates a signal input to the one of the memory blocks, wherein the output signal control circuit selects an output from the one of the memory blocks and outputs a signal based on the obtained signal from the one of the memory blocks, wherein the second memory block is placed to be axisymmetric to the first memory block with respect to a vertical axis and is placed to be axisymmetric to the fourth memory block with respect to a horizontal axis, wherein the third memory block is placed to be axisymmetric to the fourth memory block with respect to a vertical axis and is placed to be axisymmetric to the first memory block with respect to a horizontal axis, and wherein the first memory block is placed to be axisymmetric to the third memory block with respect to a horizontal axis.