Patent ID: 7558901

Claim:
A buffering apparatus comprising: an asynchronous data bus write unit which, when control information indicating a request for writing in a buffer connected to an asynchronous data bus not synchronized with a processor is provided by a multiplexer connected to the processor, receives third data from the multiplexer, stores the third data, and transfers the stored third data to a second memory through the asynchronous data bus; and an asynchronous data bus read unit which, when control information indicating a request for reading from the buffer is provided by the multiplexer, receives fourth data from the second memory through the asynchronous data bus, stores the fourth data, and transfers the stored fourth data to the multiplexer, wherein the multiplexer receives first data from the processor and transfers the received first data to a first memory through a synchronous data bus synchronized with the processor, or receives second data from the first memory through the synchronous data bus and transfers the received second data to the processor.