Patent ID: 8588023

Claim:
A semiconductor device comprising: a plurality of memory banks, each of the memory banks being selected when a corresponding one of bank signals takes an active level, each of the memory banks comprising: a main power source line; a plurality of circuit areas each comprising a logic circuit and a switch circuit coupled between the main power source line and the logic circuit, each of the circuit areas being selected when an associated one of area selective signals takes an active level; and a plurality of gate circuits supplied at first input nodes thereof in common with the corresponding one of the bank selective signals, each of the gate circuits including a second input node supplied with an associated one of the area selective signals and an output node coupled to an associated one of the switch circuits, each of the gate circuits turning ON an associated one of the switch circuits when both of the corresponding one of the bank selective signals and the associated one of the area selective signals take the active level and turning OFF the associated one of the switch circuits when at least one of the corresponding one of the bank selective signals and the associated one of the area selective signals takes an inactive level.