Patent ID: 7924073

Claim:
A semiconductor memory device comprising: a first voltage detecting unit configured to detect a voltage level of a back-bias voltage terminal based on a first target level to output a first detection signal; a second voltage detecting unit configured to detect the voltage level of the back-bias voltage terminal based on a second target level to output a second detection signal, wherein the second target level is lower than the first target level; an oscillator configured to generate an oscillation signal, which is oscillated at a predetermined frequency, in response to the first detection signal; a charge pumping unit configured to drive the back-bias voltage terminal by performing a charge pumping operation in response to the oscillation signal; and a voltage level control unit configured to control a back-bias voltage of the back-bias voltage terminal to be between the first target level and the second target level in response to the first detection signal and the second detection signal by switching on a connection between the back-bias voltage terminal and a ground voltage.