Patent ID: 8010957

Claim:
A computer implemented method for reducing redundant read-modify-write code sequences in non-vectorizable code, the computer implemented method comprising: receiving, by a compiler, a portion of code wherein the portion of code comprises a loop and includes non-vectorizable operations that affect multiple sub-parts of a storage location, wherein the non-vectorizable operations include operations that use non-alphanumeric irregular subscripts; determining, by the compiler, that multiple sub-parts of the storage location are modified by successive iterations of the loop; prior to identifying a series of instruction sequences within the portion of code, unrolling, by the compiler, the loop to generate the series of instruction sequences such that a number of sub-parts of the storage location affected by the series of instruction sequences corresponds to a length of a register, wherein the series of instruction sequences includes one write portion of a redundant read-modify-write code sequence for each iteration of an unrolled loop corresponding to the length of the register so that a final result is stored only once for each iteration of the unrolled loop corresponding to the length of the register; identifying the series of instruction sequences within the portion of code, wherein the series of instruction sequences performs at least one non-vectorizable operation on a number of sub-parts of the storage location, wherein the number of sub-parts of the storage location corresponds to the length of the register; replacing, by the compiler, loads in the series of instruction sequences with uses of the register; and introducing, by the compiler, one write portion of the redundant read-modify-write code sequence for the series of instruction sequences.