Patent ID: 8263454

Claim:
A method of fabricating an MML semiconductor device, the method comprising: forming gates on a substrate including a memory region and a logic region; forming a source region and a drain region on respective sides of the gates in the substrate; forming a first interlayer dielectric (ILD) layer which covers the gates; forming first via plugs which vertically penetrate the first ILD layer, and are selectively connected to the source region and the drain region, forming a second ILD layer on the first via plugs and the first ILD layer; forming capacitors which vertically penetrate the second ILD layer, selectively connected to the first via plugs, and including a bottom electrode, a capacitor dielectric layer, and a top electrode, wherein the part of the top electrode and the capacitor dielectric layer are extended on the second ILD layer; selectively forming planarization resistance patterns on the second ILD layer in the logic region while simultaneously forming the capacitors in the memory region; forming a third ILD layer on the capacitors and the planarization resistance patterns; entirely planarizing the third ILD layer; forming second via plugs which vertically penetrate the third ILD layer and the second ILD layer, and are selectively connected to the first via plugs; and forming a third via plug which vertically penetrates the third ILD layer, and is connected to the top electrode of the capacitors.