Patent ID: 8037438

Claim:
A method for determining a plurality of buffer insertion locations in a net for an integrated circuit design, comprising: calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for an addition of a wire segment to the first sub-tree, comprising: calculating a first RC influence for adding the wire segment to the first sub-tree in a first buffering option; and calculating a second RC influence in parallel with the first RC influence for adding the wire segment to the first sub-tree in a second buffering option different from the first buffering option; updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types, comprising: calculating in parallel a first set of buffer RC influences for the first sub-tree as configured in the first buffering option, each of the first set of buffer RC influences corresponding to one of the plurality of buffer types; storing the first set of buffer RC influences to a buffer RC influence holder; calculating in parallel a second set of buffer RC influences for the first sub-tree as configured in the second buffering option, each of the second set of buffer RC influences corresponding to one of the plurality of buffer types; and updating the buffer RC influence holder when a required arrival time in the second set of buffer RC influences is greater than a corresponding required arrival time stored in the buffer RC influence holder; and using a computer or processor to merge the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel.