Patent ID: 7159197

Claim:
A method for performing a layout beautification operation on an integrated circuit (IC) layout comprising a plurality of polygons, the method comprising applying a first action to a first portion of the IC layout responsive to determining that a first shape associated with the first action matches the first portion of the IC layout, the first shape comprising at least a first edge and a second edge related according to a defined property, the first shape being configured to match a first type of layout imperfection, the second edge being contiguous with and substantially perpendicular to the first edge, and wherein the first shape further comprises: a third edge, the third edge being contiguous with and substantially perpendicular to the second edge; a fourth edge, the fourth edge being contiguous with and substantially perpendicular to the third edge; and a fifth edge, the fifth edge being contiguous with and substantially perpendicular to the fourth edge, wherein none of the first edge, the second edge, the third edge, the fourth edge, and the fifth edge are substantially side-by-side with each other wherein the first action includes applying at least one of an absolute correction, an adaptive correction, and a replacement correction to the first portion of the IC layout.