Patent ID: 7631241

Claim:
An apparatus for decoding low density parity check (LDPC) codes, comprising: a plurality of variable node processors each, as part of a decoding process, reading data stored in a unit memory of a memory module in a column direction wherein the unit memory corresponds to the variable node that is being processed and a check node connected to the variable node, computing a probability value of the variable node that is being processed, and storing the computed probability value in the unit memory in the column direction; a plurality of check node processors each, as part of the decoding process, reading data stored in a unit memory of the memory module in a row direction wherein the unit memory corresponds to a check node that is being processed and a variable node connected to the check node, computing a probability value of the check node, and storing the computed probability value in the unit memory of the memory module in the row direction; a parity checker connected to the plurality of available check node processors for, as part of the decoding process, receiving data from one of the plurality of check node processors and performing a parity check operation, and determining if the decoding process is successful based on a result of the parity check operation; the memory module for, as part of the decoding process, storing a hard decision bit and a soft metric value in an identical memory address in a unit memory of the memory module if the decoding process is determined as unsuccessful based on the result of the parity check operation, the memory module being divided into a plurality of unit memories in rows according to a required number of check nodes and in columns according to a required number of variable nodes, each unit memory corresponding to a pair of a check node and a variable node and being accessible by one of the plurality of check node processors in a row direction and by one of the plurality of variable node processors in a column direction, wherein the one check node processor is allocated to process the check node and the one variable node processor is allocated to process the variable node; and a memory access control module for, as part of the decoding process, outputting an address of a specific unit memory of the plurality of unit memories and controlling an operation for enabling access to the specific unit memory.