Patent ID: 7076722

Claim:
A semiconductor memory device, comprising: a plurality of memory cell areas, each of which includes a plurality of memory cells arrayed in a matrix and has a data I/O portion; a plurality of buffers, each of which is coupled to said data I/O portion at a corresponding memory cell area to temporarily store data to be written into said memory cell area and data read out from said memory cell area; a plurality of I/O terminals, each of which is configured to receive said data to be written into corresponding ones of said memory cell areas and output said data read out from said memory cell areas; and an error correction circuit located between said plurality of I/O terminals and said plurality of buffers, said error correction circuit includes a coder configured to generate check bits for error correcting and to append said check bits to said data to be written into said memory cell areas and a decoder configured to process for error correcting said data read out from said memory cell areas with said generated check bits, said error correction circuit operates to allocate a set of check bits to MÃ—N data bits (N denotes an integer of two or more) to execute at least one of coding and decoding by parallel processing N-bit data, where N denotes the number of bits in a unit of data to be written into and read out from each memory cell area.