Patent ID: 7984404

Claim:
A black box timing modeling method for a digital circuit comprising synchronous elements including latches, the method comprising: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous element with respect to an input connected to the synchronous element and forming the setup time arc using the extracted setup time, in a processor of a computer system; and characterizing a clock-to-output delay arc by providing information on an output departure time from an output based on a rising or falling edge of a clock of a closest synchronous element connected to the output, at least partially based on the setup time arc and forming the clock-to-output delay arc, in the processor; and performing a preprocessing operation in the processor, wherein the preprocessing operation comprises: performing static timing analysis on the circuit; and obtaining a weighted graph by converting synchronous elements and main input-outputs into nodes, when an electrical signal can be transmitted between the synchronous elements or the input-outputs, converting link relationships between the synchronous elements or the input-outputs into directed edges according to the directions of signal transmission, and determining weights of the directed edges as delays for the signal transmission.