Patent ID: 7242634

Claim:
An integrated circuit having a word-line driver adapted to receive a set of decoded bits (e.g., D 0 , D 1 , D 74 , D 118 ) and control a set of word-lines (e.g., WL 0 , WL 1 ), the word-line driver comprising: a first set of circuitry (e.g., 602 – 608 ) adapted to receive and process a first subset of one or more decoded bits (e.g., D 74 , D 118 ) and connected to a first node (e.g., W) in the word-line driver; and a second set of circuitry (e.g., 614 – 628 ) connected to the first node and adapted to receive and process a second subset of decoded bits (e.g., D 0 , D 1 ) to control the set of word-lines, wherein, for each word-line (e.g., WL 0 ), the second set of circuitry comprises a corresponding feed-back latch (e.g., 622 , 626 , 628 ) controlled by a corresponding decoded bit (e.g., D 0 ) and adapted to drive the corresponding word-line low if the corresponding decoded bit indicates that the corresponding word-line is not selected.