Patent ID: 8452830

Claim:
A CORDIC processor having: a sequencer generating a mode output having values which include ROTATE or VECTOR, and a stage number output generating a value k; a register memory having a plurality of register locations selected by said sequencer; at least one re-use stage having an X input and Y input coupled to a register memory location addressed by said sequencer, a sign input and a sign output coupled to a bit slice memory, an X output and Y output coupled to a register memory location addressed by said sequencer, a mode control input coupled to said sequencer mode output, and a stage number input coupled to said sequencer stage number output, each said re-use stage having: a first shifter generating an output by shifting said Y input k times; a second shifter generating an output by shifting said X input k times; a multiplexer having an output coupled to said bit slice memory when said mode control input is ROTATE and to the sign of said Y input when said mode input is VECTOR, said sign of said Y input also forming said sign output; a first multiplier forming the product of said first shifter output and said multiplexer output; a second multiplier forming the product of said second shifter output and an inverted said multiplexer output; a first adder forming said X output from the sum of said first multiplier output and said X input; a second adder forming said Y output from the sum of said second multiplier output and said Y input.