Patent ID: 8154275

Claim:
An integrated circuit comprising: one or more sense amplifier modules, each including: one or more sense amplifier circuits; a voltage generator unit configured to selectably supply a differential voltage of a plurality of differential voltages to at least some of the one or more sense amplifier circuits; wherein each sense amplifier circuit is configured to generate an output value that is dependent upon the applied differential voltage in response to receiving an enable signal; and detection logic coupled to each of the sense amplifier circuits and configured to detect an output value of each of the one or more sense amplifier circuits; wherein the detection logic includes one or more latch circuits, each configured to latch and output the output value of a corresponding one of the one or more sense amplifier circuits; wherein the detection logic includes one or more flip-flop circuits, each coupled to a corresponding one of the latch circuits, wherein each flip-flop circuit is configured to capture and output a digital value that corresponds to the output value; and wherein the one or more flip-flop circuits are coupled together in a scan chain such that an output of a first flip-flop is coupled to a scan data input of a next flip-flop and an output of the last flip-flop in the scan chain is coupled to a scan data output of the integrated circuit, and wherein in response to an assertion of a scan enable signal and a number of clock signal pulses, the captured digital values may be sequentially shifted out to the scan data output.