Patent ID: 7745930

Claim:
A semiconductor device package comprising: a power semiconductor device having a first major surface, a second major surface, a first edge extending along a first direction, and a second edge extending along a second direction, said first edge being opposite said second edge; a first elongated runner over said first major surface of said power semiconductor device and extending along said first direction; a second elongated runner over said first major surface of said power semiconductor device and extending along said second direction; a plurality of first power electrodes and a plurality of second power electrodes on said first major surface of said power semiconductor device, said first power electrodes being electrically connected to said first elongated runner and said second power electrodes being electrically connected to said second elongated runner, said first power electrodes and said second power electrodes being disposed between said first elongated runner and said second elongated runner; a substrate having a first major surface and a second major surface, said second major surface of said power semiconductor device being thermally coupled to said first major surface of said substrate; a first conductive pad and a second conductive pad disposed on said first major surface of said substrate, said first conductive pad extending along said first edge of said power semiconductor device and said second conductive pad extending along said second edge of said power semiconductor device; a plurality of spaced first wirebonds connected to said first elongated runner and said first conductive pad; a plurality of spaced second wirebonds connected to said second elongated runner and said second conductive pad; a first external lead electrically and mechanically coupled to said first conductive pad by a conductive adhesive; a second external lead electrically and mechanically coupled to said second conductive pad by a conductive adhesive; and a molded housing enclosing at least said power semiconductor device and at least a portion of said first major surface of said substrate.