Patent ID: 7153743

Claim:
A method for fabricating a non-volatile memory device, comprising: preparing a semiconductor substrate having a trench filled with an isolation film; forming a tunnel oxide film, a first conductive layer, an Oxide-Nitride-Oxide (ONO) layer, and a second conductive layer on the semiconductor substrate in succession; forming a protection layer on the second conductive layer wherein forming the protection layer comprises a silicide process; etching the first conductive layer, the ONO layer, the second conductive layer, and the protection layer, to form gate stacks on opposed sides of the isolation film, the gate stacks exposing a portion of the isolation film between the opposed sides, each gate stack comprising a floating gate pattern, an ONO pattern, a control gate pattern, and a protection pattern, and having a first portion over the isolation film in the trench and a second portion over the tunnel oxide film on the substrate; forming a photoresist pattern for a self aligned source (SAS) over the semiconductor substrate in such a way that a part of the silicide top surface of the protection pattern and the exposed portion of the isolation film remain uncovered therewith; etching the exposed portion of the isolation film using the photoresist pattern and the part of the protection pattern as an etching mask; and injecting impurity ions into a bottom of the trench, to form a source diffusion layer.