Patent ID: 7960788

Claim:
A semiconductor structure comprising: a semiconductor substrate; a first asymmetric MOS transistor comprising: a first gate dielectric on the semiconductor substrate; a first gate electrode on the first gate dielectric; a first source extension region in the semiconductor substrate, wherein the first source extension region extends under the first gate electrode; and a first source region adjoining the first source extension region, wherein the first source region is spaced apart further from the first gate dielectric than the first source extension region is spaced from the first gate dielectric; a second asymmetric MOS transistor comprising: a second gate dielectric on the semiconductor substrate; a second gate electrode on the second gate dielectric, wherein a distance between the first and the second gate electrodes is less than about two times a height of the first and the second gate electrodes; a second source extension region in the semiconductor substrate, wherein the second source extension region extends under the second gate electrode; a second source region adjoining the second source extension region, wherein the second source region is spaced apart further from the second gate dielectric than the second source extension region is spaced from the second gate dielectric; and a common drain region between and adjacent to the first and the second gate dielectrics, wherein the first and the second asymmetric MOS transistors are substantially free from drain extension regions, and wherein the common drain region extends to substantially a same depth into the semiconductor substrate as the first and the second source regions.