Patent ID: 7049649

Claim:
A semiconductor memory device comprising: a device layer including; a semiconductor layer having a first diffused region and a second diffused region formed therein and having substantially flat surfaces, said semiconductor layer defining a first side and a second side; a transistor having a gate electrode formed only on said first side of the semiconductor layer and between the first and the second diffused regions with an insulation film interposed therebetween; and a capacitor formed only on said first side of the semiconductor layer and having a storage electrode connected to the first diffused region; a bit line formed on said second side of the semiconductor layer, and extended in a direction normal to the gate electrode; and a support substrate formed on said first side of the semiconductor layer for supporting the device layer, the semiconductor layer including a first region which is extended in the direction of extension of the bit line and includes the first diffused region and the second diffused region, and a second region which is adjacent to the first region on a side of a direction of extension of the gate electrode and includes a third diffused region, the second diffused region in the first region and the third diffused legion in the second region being formed spaced from each other; a first contact hole being formed in the first region for connecting the first diffused regions to the capacitor; and a second contact hole being formed in the second region for connecting the bit line with the third diffused region.