Patent ID: 7573770

Claim:
An integrated circuit comprising: one or more data I/O blocks, at least one data I/O block adapted to receive an incoming bit stream from an external device; a clock I/O block adapted to receive an incoming clock signal from the external device, wherein the incoming clock signal is asynchronous with a local reference clock signal of the integrated circuit; one or more FIFOs, at least one FIFO connected to receive a corresponding incoming bit stream from a corresponding data I/O block; and a FIFO controller adapted to control operations of the one or more FIFOs, such that: bits from the corresponding data I/O block are written into the at least one FIFO using a FIFO write clock that is based on the incoming clock signal; and bits are read out from the at least one FIFO using a FIFO read clock that is based on the local reference clock signal.