Patent ID: 6861877

Claim:
A circuit to independently control rise and fall delay edge timing of a signal, said circuit comprising: a first delay element and a second delay element wherein each of said delay elements has input and output and wherein each of said inputs is coupled to a common, input signal; an AND function having two inputs and one output wherein one of said inputs is coupled to said input signal and another of said inputs is coupled to said first delay element output and wherein said AND function output comprises a rise-delayed signal having a controlled rising edge delay between a rising edge of said input signal and a rising edge of said rise-delay signal; an OR function having two inputs and one output wherein one of said inputs is coupled to said input signal and another of said inputs is coupled to said second delay element output, wherein said OR function output comprises a fall-delayed signal having a controlled falling edge delay between a falling edge of said input signal and a falling edge of said fall-delay signal; and a means to combine said rise-delayed signal and said fall-delayed signal into a common, delayed output signal wherein said means of combining comprises a latch having set, reset, and output, and wherein said rise-delayed signal is coupled to set, said fall-delayed signal is coupled to reset, and said common, delayed output signal is coupled to output.