Patent ID: 8595557

Claim:
A method for verifying the accuracy of logical-to-physical mapping software designed for testing memory devices, said method comprising: providing a built-in self test (BIST) fail control function to generate multiple simulated memory fails at various predetermined memory locations within a memory array of a memory device; testing said memory array via a memory tester; generating a bit fail map by said logical-to-physical mapping software based on all memory fails indicated by said memory tester, wherein said bit fail map indicates physical locations of all fail memory locations derived by said logical-to-physical mapping software; and comparing said fail memory locations derived by said logical-to-physical mapping software to said various predetermined memory locations to verify the accuracy of said logical-to-physical mapping software, and concluding said logical-to-physical mapping software as defective when said fail memory locations derived by said logical-to-physical mapping software do not match up with said various predetermined memory locations.