Patent ID: 8133784

Claim:
A method of fabricating a non-volatile memory device having a vertical structure, comprising: alternately stacking a plurality of sacrificial films and a plurality of insulation films on a semiconductor substrate; removing a part of the plurality of sacrificial films and the plurality of insulation films to form a plurality of first openings that expose a plurality of first portions of the semiconductor substrate; forming a plurality of channel layers in the plurality of first openings so as to cover the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings; forming a plurality of insulation pillars on the plurality of channel layers so as to fill the plurality of first openings; removing a part of the plurality of sacrificial films and the plurality of insulation films to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate; removing the plurality of sacrificial films exposed by the plurality of second openings to form a plurality of side openings that expose parts of the plurality of channel layers; forming a plurality of gate dielectric films on surfaces of the plurality of side openings; forming a plurality of gate electrodes on the plurality of gate dielectric films such that the plurality of side openings are filled; and ion-injecting impurities into the plurality of second portions of the semiconductor substrate to form a plurality of common conjunction regions.