Patent ID: 6996795

Claim:
A structure, comprising; an FPGA (Field-Programmable Gate Array) including a plurality of FPGA elements, each of the FPGA elements comprising an FPGA CLB (Configurable Logic Block), wherein each FPGA element in the FPGA is assigned an address and is configured to provide its address, wherein a first subset of the FPGA elements is configured to form a first functional block, wherein the first functional block comprises a mapped location register residing in one or more FPGA CLBs of the first functional block, wherein the mapped location register stores the address of a current location FPGA element, the current location FPGA element being in the first functional block and the address of the current location FPGA element being specified as the location of the first functional block, wherein the first functional block further comprises a mapped movement register residing in one or more FPGA CLBs of the first functional block, and wherein the mapped movement register stores the direction and distance of a next step of the movement of the first functional block.