Patent ID: 8347034

Claim:
A computer cache for a processor memory, the computer cache comprising: a data random-access memory (RAM) comprising a plurality of cache lines, wherein each of the cache lines is configured to store a segment of the processor memory; a tag RAM comprising a plurality of address tags that correspond to respective ones of the cache lines; a valid RAM comprising a plurality of validity values that correspond to the respective ones of the cache lines, the valid RAM configured to receive a clear signal and a conditional clear signal, wherein data within the valid RAM is stored separately from i) data within the tag RAM and ii) data within the data RAM, and wherein the valid RAM is selectively independently clearable relative to the tag RAM based on whether the valid RAM receives the clear signal or the conditional clear signal; and a hit module configured to determine, based on the data within the valid RAM and the data within the tag RAM, whether valid data is stored in the computer.