Patent ID: 8081512

Claim:
A non-volatile semiconductor memory device comprising: a non-volatile memory including a plurality of blocks each including a plurality of memory cells, each of the memory cells having a stacked gate structure in which a first insulation film, a charge storage layer, a second insulation film, and a gate electrode are sequentially stacked; a bit line electrically connected to one end of a current path of the memory cell; a source line electrically connected to the other end of the current path of the memory cell; a word line electrically connected to the gate electrode; a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell; a row decoder electrically connected to the word line and configured to apply a read voltage on the word line by which the memory cell is set to an ON state; and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded, wherein the sense amplifier circuit charges the bit line in a degradation judgment of the memory cell, the controller judges that the memory cell has been degraded if a voltage of the bit line discharged by the memory cell is higher than a predetermined level after elapse of a judgment time, and the judgment time is set shorter than a time to judge data stored in a memory cell of the plurality of memory cells in data reading.