Patent ID: 8502384

Claim:
A semiconductor device comprising: a first level wiring structure formed over a substrate, the first level wiring structure including first and second wiring patterns disposed with a first gap therebetween, two or more first dummy patterns arranged in the first gap between the first and second wiring patterns and a first insulating layer covering the first and second wiring patterns and the first dummy patterns; and a second level wiring structure formed on the first level wiring structure, the second level wiring structure including third and fourth wiring patterns disposed with a second gap therebetween that is less than the first gap, one or more second dummy patterns arranged in the second gap between the third and fourth wiring patterns and a second insulating layer covering the third and fourth wiring patterns and second dummy patterns; the second dummy patterns being smaller in number than the first dummy patterns and each second dummy pattern being vertically aligned in central axis with an associated one of the first dummy patterns.