Patent ID: 7045421

Claim:
A method of making a bit selectable device having nanotube memory elements, comprising: providing a structure having at least two transistors, each with a drain and a source with a defined channel region therebetween, each transistor further including a gate over said channel; forming a trench between one of the source and drain of a first transistor and one of the source and drain of a second transistor; forming an electrical communication path in the trench between one of the source and drain of a first transistor and one of the source and drain of a second transistor; providing a defined pattern of nanotube fabric over at least a horizontal portion of the structure and extending into the trench; providing an electrode in the trench; suspending defined pattern of nanotube fabric so that at least a portion is vertically suspended in spaced relation to the vertical walls of the trench and positioned so that the vertically suspended defined pattern of nanotube fabric is electromechanically deflectable into electrical communication with one of the drain and source of a first transistor and one of the source and drain of a second transistor.