Patent ID: 7953999

Claim:
A bridge circuit comprising: a first interface block configured to interface with a first bus; a second interface block configured to interface with a second bus: a clock detection block configured to receive and decode a register value corresponding to a frequency-divided clock signal and generate a state control signal based on the decoded register value, wherein the clock detection block comprises: a clock decoder block configured to decode the register value corresponding to the frequency-divided clock signal and output the decoded register value; a clock counter block coupled to the clock decoder block and configured to receive the decoded register value, count a main clock signal, and output an indicator flag bit when the decoded register value is the same as a main clock signal count value obtained as a result of counting the main clock signal; and a clock comparison block coupled to the clock decoder block and the clock counter block, and configured to receive and compare the decoded register value and the main clock signal count value and output a state flag bit based on a result of the comparison; and a state machine coupled to the first interface block, the second interface block and the clock detection block, the state machine configured to receive first control signals via the first interface block and generate second control signals having a clock frequency corresponding to the register value based on the state control signal.