Patent ID: 7904846

Claim:
A computer-implemented method, to generate in memory, goals for functional verification of a design of a circuit, the method comprising: receiving a plurality of constraints on a plurality of signals input to the circuit during simulation of the design; wherein each signal in said plurality of signals is declared as having a random attribute in an object of a class defined in a hardware verification language; a programmed computer automatically applying at least a predetermined rule comprising a constraint template to at least one constraint in said plurality of constraints, and based on an expression in said at least one constraint to identify a goal template of a new goal to be met by said functional verification during said simulation; and automatically creating said new goal in a memory of said programmed computer, by instantiation of said goal template with information from said at least one constraint; wherein said new goal identifies a signal in said plurality of signals by a name and a target value for said signal, and defines a counter for said signal.