Patent ID: 7928514

Claim:
A complementary metal oxide semiconductor (CMOS) structure comprising: a semiconductor substrate having a first device region comprising n-type semiconductor devices and a second device region comprising p-type semiconductor device, wherein said first device region comprises at least one first gate stack comprising a first high-k gate dielectric and a first fully silicided gate electrode that are in direct contact, and wherein said second device region comprises at least one second gate stack comprising a second high-k gate dielectric, an insulating interlayer atop said high-k gate dielectric, and a second fully silicided gate electrode atop said insulating interlayer, wherein said insulating interlayer is selected from the group consisting of aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), boron nitride (BN), boron oxynitride (BO x N y ), gallium nitride (GaN), gallium oxynitride (GaON), indium nitride (InN), indium oxynitride (InON) and combinations thereof, wherein said insulating interlayer stabilizes said p-type semiconductor devices threshold voltage and flatband voltage without shifting said n-type semiconductor devices threshold voltage and flatband voltage.