Patent ID: 8802548

Claim:
A fabrication method for a semiconductor device, the fabrication method comprising: forming a high resistance first base layer of a first conductivity type; forming a drain layer of the first conductivity type on a back side surface of the first base layer; forming a second base layer of a second conductivity type on a surface of the first base layer; forming a source layer of the first conductivity type on a surface of the second base layer; forming a gate insulating film on a surface of the source layer and the surface of the second base layer; forming a gate electrode on the gate insulating film; forming a column layer of the second conductivity type in the first base layer below both the second base layer and the source layer by opposing the drain layer, the column layer extending in a first direction vertical to a principal surface of the drain layer, a first length of the column layer in the first direction being larger than a second length thereof in a second direction parallel to the principal surface of the drain layer, the column layer and the first base layer being repeatedly alternately-arranged in the second direction; forming a drain electrode in the drain layer, forming a source electrode on both the source layer and the second base layer; and performing a heavy particle irradiation to the column layer so as to form a trap level locally below the second base layer.