Patent ID: 8181002

Claim:
A method for merging checkpoints on a processor, comprising: executing instructions speculatively during a speculative-execution episode; generating a first checkpoint and a second checkpoint during the speculative-execution episode, wherein the second checkpoint is generated after the first checkpoint, and wherein the first checkpoint and the second checkpoint store separate architectural states of the processor; wherein generating each of the first checkpoint and the second checkpoint comprises: determining that the checkpoint is mergeable based on a category of the checkpoint, and marking the checkpoint as mergeable; and merging the first checkpoint with the second checkpoint during the speculative-execution episode to create a single replacement checkpoint that includes a combined architectural state generated by combining an architectural state stored in the first checkpoint with an architectural state stored in the second checkpoint; wherein merging the first and second checkpoints comprises combining both the data stored in register file copies associated with the checkpoints and not-there bits corresponding to the register file copies so that the most recently written data and not-there bits are retained in the replacement checkpoint.