Patent ID: 8521933

Claim:
A circuit for performing round robin arbitration for a plurality of requestors, comprising: a mask reset subcircuit including: N AND gates, each AND gate of the N AND gates associated with one of the N requestors, each AND gate of the N AND gates including: a first input communicatively coupled to receive a mask signal, and a second input communicatively coupled to a request line of one of the N requestors; a N-input OR gate, each input of the OR gate communicatively coupled to an output of one of the N AND gates of the mask reset subcircuit; and a multiplexer for selecting from at least two N-bit inputs to provide a selected output, the selected output including a single bit for each of the N requestors, the multiplexer including: a first multiplexer input, each bit of the first multiplexer input communicatively coupled to an output of the N AND gates of the mask reset subcircuit, a second multiplexer input communicatively coupled to a reset signal, and a control input communicatively coupled to the OR output; and a mask generation subcircuit including; N AND gates, each AND gate of the N AND gates associated with one of the N requestors, each AND gate of the N AND gates including: a first input communicatively coupled to a single bit of the selected output, and a second input communicatively coupled to a request line of one of the N requestors; a priority arbiter subcircuit for providing a grant signal assigning priority to one of the N requestors and the mask signal, the priority arbiter subcircuit coupled to receive an output of the N AND gates of the mask generation sub circuit as an input; and flip-flops communicatively coupled to the priority arbiter subcircuit for storing the mask signal to provide to the first input, the N flip-flops including a single flip-flop for each of N requestors, each flip-flop included in the N flip-flops including a flip-flop output.