Patent ID: 8466514

Claim:
A semiconductor power device integrated with Gate-Source Electrostatic Discharge (ESD) clamp diodes formed on a semiconductor silicon layer, comprising a plurality of transistor cells in an active area, and multiple back to back Zener diodes with alternating doped regions of a first conductivity type next to a second conductivity type in said Gate-Source ESD clamp diodes, wherein: said semiconductor power device further comprises: a plurality of first type trenched gates surrounded by source regions of said first conductivity type encompassed in body regions of said second conductivity type; a plurality of trenched source-body contacts opened through said source regions and extending into said body regions, filled with a contact metal plug therein and connected to a front metal serving as a source metal pad; said Gate-Source ESD clamp diodes further comprises: a gate metal pad connected to at least one gate metal runner surrounding a peripheral region of said semiconductor power device; said source metal pad connected to at least one source metal runner disposed between said gate metal pad and said gate metal runner, and separated from said gate metal pad and said gate metal runner by a metal gap, wherein said source metal runner does not have said first type trenched gates underneath; a first type Gate-Source ESD clamp diode connected between said gate metal pad and said source metal pad; a second type Gate-Source ESD clamp diode connected between said gate metal pad and said source metal runner; a third type Gate-Source ESD clamp diode connected between said source metal pad and said gate metal runner; and a fourth type Gate-Source ESD clamp diode connected between said source metal runner and said gate metal runner.