Patent ID: 8129770

Claim:
A semiconductor device, comprising: a semiconductor substrate having a main surface and an active region surrounded with an element isolation structure on said main surface; a transistor having first and second impurity diffusion regions formed on a surface of said active region and a gate electrode layer serving as a word line, located between said first and second impurity diffusion regions and extending across said active region; sidewall insulating films formed on sidewalls of said gate electrode layer; and first and second plug conductive layers each electrically connected to each of said first and second impurity diffusion regions and covering a whole portion of both said first and second impurity diffusion regions not covered with said gate electrode layer and said sidewall insulation films in plane view; a capacitor electrically connected to said first plug conductive layer; and a bit line electrically connected to said second plug conductive layer and extended perpendicular to said word line, wherein an extending direction of said active region forms an oblique angle with both that of said word line and that of said bit line, and at least one of said first and second plug conductive layers has a pair of sides that are parallel to the longitudinal direction of said active region in plane view.