Patent ID: 7302552

Claim:
Apparatus for processing data, said apparatus comprising: an instruction memory operable to store program instructions and readable in fixed length memory accesses; an instruction decoder operable to decode one or more instruction fields within a program instruction to generate at least control signals; and a plurality of data path elements responsive to said controls signals independently to perform in parallel respective data processing operations specified by said program instruction, at least some program instructions decoded by said instruction decoder allowing control signals for respective data path elements to be independently specified; wherein said instruction decoder is operable such that a given data processing operation to be performed by a data path element can be specified using differently encoded instruction fields in different program instructions; wherein said program instructions are divided into a plurality of instruction sets and said instruction decoder is responsive to at least an instruction set identifying field within each program instruction to control which bits within said program instruction correspond to instruction fields for which data path elements, and wherein said program instructions have a variable program instruction length and said instruction decoder is responsive to said instruction set identifier to determine program instruction length of a program instruction, wherein a fixed length memory access contains at least portions of a plurality of program instructions, the apparatus further comprising: a rotator and a program counter incrementer operable to align program instructions within said memory accesses to a predetermined position for supply to said instruction decoder and wherein said rotator is responsive to said instruction set identifiers to determine what rotation to apply to align said program instructions.