Patent ID: 8543792

Claim:
A computing device comprising: a computing device-readable medium to store an address translation data structure; and a memory management unit, communicatively coupled to the computing device-readable medium, including: a cache to store one or more address mappings of the address translation data structure; and a paging module, communicatively coupled to the cache, to coalesce a plurality of address mappings stored in the address translation data structure between a virtual memory space and a physical memory space when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages, wherein; a first bit of a contiguous attribute, associated with a coalesced mapping, specifies a type of encoding; a plurality of other bits of the contiguous attribute specifies an actual number of contiguous pages when the first bit is set to a first state; and the plurality of other bits of the contiguous attribute specifies a power of two representation of the number of contiguous pages when the first bit is set to a second state.