Patent ID: 7773426

Claim:
A semiconductor device comprising: a central processing unit; a nonvolatile memory unit comprising memory cells; and a bus coupled to the central processing unit and the nonvolatile memory unit, wherein the central processing unit issues an erase instruction to the nonvolatile memory unit via the bus, and wherein, based on the erase instruction, the nonvolatile memory unit performs an erase operation to: (i) supply an erase voltage to ones of the memory cells; (ii) check whether statuses of the memory cells exceed, in an erase direction, a pre-write-back level, the pre-write-back level being at a level before a deplete level defining entry into a negative voltage status in the erase direction; (iii) supply a voltage to respective ones of the memory cells having statuses which exceed the pre-write-back level in the erase direction; and (iv) check whether the statuses of the memory cells exceed, in the erase direction, a write-back level, which is before the pre-write-back level in the erase direction.