Patent ID: 7808510

Claim:
An image processing apparatus comprising: a first image processor for performing multi-level dithering based on a two-dimensional dither matrix to reduce the bit-plane number of a raster image as an original image; a memory for storing image data of the raster image whose bit-plane number has been reduced by the first image processor; and a second image processor for performing bit addition for the image data read out from the memory to increase the bit-plane number thereof; wherein: the first image processor applies to the multi-level dithering a summation matrix of a threshold matrix and an offset matrix as offset values for minimizing the difference between the signal value of the original image and the average of all the dither values of the raster image whose bit-plane number has been increased; and the threshold matrix is obtained by changing matrix values of the two-dimensional dither matrix corresponding to matrix values of the offset matrix not being “0” to values other than their original values, respectively, wherein the two-dimensional dither matrix comprises four areas, wherein each of the four areas comprises n sub-areas each assigned one of n unique dither values ranging from a minimum to a maximum value, wherein n equals 2 raised to the power of a bit-plane number, the bit-plane number being an original bit-plane number of the raster image minus a reduced bit-plane number of the raster image, wherein the offset matrix comprises 2×n “0” values corresponding to the sub-areas of two of the four areas of the two-dimensional dither matrix and 2×n non-zero values corresponding to the remaining sub-areas of the two-dimensional dither matrix, wherein the non-zero values are equal to a specified value.