Patent ID: 7917799

Claim:
A method of digital frequency clocking in a processor core, comprising the steps of: providing at least one-processor core, said at least one processor core having a clocking subsystem for generating an output clock signal at a variable frequency; loading onto said at least one processor core digital frequency control data, including a given frequency value, for the processor core; and said at least one processor core, i) receiving and storing the digital frequency control data, including said given frequency value, loaded onto said processor core, and ii) using said stored digital frequency control data, including said given frequency value, to set the frequency of the output clock signal of the clocking subsystem of the processor core; and wherein: the providing step includes the step of providing a plurality of processor cores, each of the processor cores having a respective clocking subsystem for generating an output clock signal at a variable frequency; the loading step includes the step of loading onto each of the processor cores, individual digital frequency control data for the respective processor core; the receiving step includes the step of, each of the processor cores receiving the digital frequency control data sent to said each processor core; and the using step includes the step of, each of the processor cores using the digital frequency control data received by said each processor core to set the frequency of the output clock signal of the clocking subsystem of said each processor core.