Patent ID: 8787032

Claim:
A microelectronic assembly, comprising: a dielectric element having a first surface, a second surface, first and second apertures extending between the first and second surfaces and defining a central region of the first surface between the first and second apertures, the first surface of the dielectric element having a first peripheral edge and a first peripheral region between the first aperture and the first edge, the dielectric element further having electrically conductive elements thereon including central terminals exposed at the central region and peripheral terminals exposed at the peripheral region; a first microelectronic element having a rear surface and a front surface facing the second surface of the dielectric element, the first microelectronic element having a plurality of contacts exposed at the front surface thereof; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at the front surface thereof projecting beyond an edge of the first microelectronic element, each of the first and second microelectronic elements including a memory storage element; leads extending from the contacts of the first and second microelectronic elements to the central and peripheral terminals, at least first and second leads thereof electrically interconnecting a first central terminal of the central terminals with each of the first and second microelectronic elements, wherein the first and second leads are usable to carry at least one of a signal or a reference potential between the first central terminal and each of the first and second microelectronic elements, and the first and second leads are usable to carry an address signal usable to address memory storage elements in each of the first and second microelectronic elements; and a third lead electrically interconnecting a first peripheral terminal of the peripheral terminals with at least one of the contacts of the first microelectronic element, the third lead usable to carry a first data signal between the first peripheral terminal and the first microelectronic element.