Patent ID: 7247934

Claim:
A multi-chip semiconductor package, comprising: a substrate having an upper surface and a lower surface opposed to the upper surface; at least one first chip having an active surface and a non-active surface, wherein the active surface of the first chip is mounted on and electrically connected to the upper surface of the substrate via a plurality of solder bumps; a preformed package structure comprising a lead frame, at least one second chip mounted on and electrically connected to the lead frame, and a first encapsulation body for encapsulating the second chip and a portion of the lead frame, with outer leads of the lead frame being exposed from the first encapsulation body and mounted on the upper surface of the substrate, wherein the first encapsulation body, the exposed outer leads and the substrate form a space where the first chip is received, and a gap is present between the non-active surface of the first chip and the first encapsulation body; and a second encapsulation body formed on the upper surface of the substrate, for encapsulating the first chip, the solder bumps and the preformed package structure, wherein the gap between the non-active surface of the first chip and the first encapsulation body is filled with a single-layered thermally conductive adhesive disposed between and directly connected to the lead frame and the first chip.