Patent ID: 6924203

Claim:
A method for fabricating a heterojunction bipolar transistor (HBT) device on a wafer substrate having a major flat, the method comprising: providing a subcollector layer over the wafer substrate, a phosphorous based collector layer over the subcollector layer, a base layer over the phosphorous based collector layer, and an emitter layer over the base layer; removing portions of the emitter layer to form an emitter; depositing a base metal to form a base contact and a connecting bridge, the connecting bridge being oriented at about one of a 001, 010, 00{overscore (1)}, and 0{overscore (1)}0 direction with respect to the major flat of the wafer; etching portions of the base layer to form a first base mesa below the base contacts, a second base mesa below the emitter, and a remaining portion of the base material between the first base mesa and the second base mesa, the connecting bridge overlying the remaining portion of base material and connecting the second base mesa to the base contact; and performing a collector etch to form at least one collector region, the collector etch undercutting the conductive bridge and the remaining portion of the base material to remove collector material from underneath the bridge and the remaining portion of the base material and to form an opening underneath the bridge and the remaining portion of the base material.