Patent ID: 7999618

Claim:
A circuit comprising: a first input port and a second input port; an output port; a supply voltage rail and a ground rail; a PNP drive transistor comprising an emitter connected to the supply voltage rail, a base connected to the first input port, and a collector connected to the output port; a NPN drive transistor comprising an emitter connected to the ground rail, a base connected to the second input port; and a collector connected to the output port; a first PNP transistor comprising an emitter connected to the supply voltage rail, a base, and a collector connected to the first input port; a second PNP transistor comprising an emitter connected to the first input port, a base, and a collector connected to the second input port; a first NPN transistor comprising an emitter connected to the ground rail, a base, and a collector connected to the second input port; a second NPN transistor comprising an emitter connected to the second input port, a base, and a collector connected to the first input port; a third PNP transistor comprising an emitter connected to the supply voltage rail, a base connected to the base of the first PNP transistor, and a collector; a fourth PNP transistor comprising an emitter connected to the base of the first PNP transistor, a base connected to the base of the second PNP transistor, and a collector connected to the second input port; a first follower coupled to the third and fourth PNP transistors, the collector of the third PNP transistor having a collector voltage and the base of the fourth PNP transistor having a base voltage, so that the base voltage of the fourth PNP transistor follows the collector voltage of the third PNP transistor; a third NPN transistor comprising an emitter connected to the ground rail, a base connected to the base of the first NPN transistor, and a collector; a fourth NPN transistor comprising an emitter connected to the base of the first NPN transistor, a base connected to the base of the second NPN transistor, and a collector connected to the first input port; and a second follower coupled to the third and fourth NPN transistors, the collector of the third NPN transistor having a collector voltage and the base of the fourth NPN transistor having a base voltage, so that the base voltage of the fourth NPN transistor follows the collector voltage of the third NPN transistor.