Patent ID: 7659586

Claim:
A four-transistor Schmitt trigger inverter, the Schmitt trigger inverter comprising: a NMOS dual-gate thin-film transistor (DG-TFT) having a top gate, a back gate, and source/drain regions; a PMOS DG-TFT having a top gate, a back gate, and S/D regions; an NMOS TFT having a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region, and a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate; and, a PMOS TFT having a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region; wherein the DG-TFTs have channels with channel widths underlying the top gates, and dielectric thickness between the channels and the bottom gates; and wherein the Schmitt trigger inverter further comprises a circuit first switch point responsive to the DG-TFT channel widths, and a circuit second switch point, lower than the first switch point, responsive to the dielectric thickness between the channels and the bottom gates.