Patent ID: 6873188

Claim:
A logic device comprising: a dynamic logic circuit generating a first logic output on a dynamic node, said dynamic node precharged to a first logic value during a first phase of a clock signal and evaluated to a second logic value during a second phase of said clock signal, said second logic value corresponding to a Boolean function of one or more input signals, said second logic value generated at a first common node exclusively coupled to said dynamic node in response to a corresponding one of a plurality of first select signals, and wherein said first common node is precharged to said first logic value with said precharge of said dynamic node; and a static logic circuit receiving said first logic output and generating a second logic output at a first output node having said second logic value during said second phase of said clock signal and maintaining said second logic value during said first phase of said clock signal, wherein said static logic circuit generates a second logic output at a second output node having a third logic value during said second phase of said clock signal and maintaining said third logic value during said first phase of said clock signal, said third logic value corresponding to a complement of said second logic value, and wherein said static logic circuit comprises a static complementary logic gate having an input node coupled to said dynamic node, an output node coupled to said first output node, a power supply node coupled to a power supply voltage and a ground node coupled to a first common node of parallel coupled first and second N-channel field effect transistor (NFETs), a second common node of said parallel coupled first and second NFETs coupled to a second power supply voltage, a gate of said first NFET coupled to said clock signal and a gate of said second NFET coupled to said second output node.