Patent ID: 6922361

Claim:
A non-volatile memory device comprising: a pair of bit lines; a pair of word lines; and a unit cell connected between the pair of bit lines comprising a pair of transistors each having two terminals, one terminal of each of the pair of transistors being connected to one of the pair of word lines, and the other terminal of each of the pair of transistors being connected to one of the pair of bit lines, wherein: a first transistor of the pair of transistors functions as a cell transistors, and a second transistor of the pair of transistors functions as a selection transistor so that each of the pair of transistor stores one-bit data independently from the other; the bit line and the word line connected to the first transistor receive first and second high voltages, respectively, and the word line and the bit connected to the second transistor receive a low voltage and a grounded voltage, respectively, when data is programed to the first transistor; the bit line and the word line connected to the first transistor receive the first high voltage and a grounded voltage, respectively, and the bit line and the word line connected to the second transistor receive the low voltage when data is erased from the first transistor; the bit line and the word line connected to the first transistor receive a grounded voltage and a readout voltage, respectively, and the bit line and the word line connected to the second transistor receive the readout voltage and low voltage, respectively, when data is read from the first transistor; the first transistor functions as a cell transistor and the second transistor functions as a selection transistor; the first voltage is 8 to 10 V; the second high voltage is 9 to 12 V; the low voltage is 4 to 5 V; and the readout voltage has a value between a threshold voltage for programming data and a threshold voltage for erasing data.