Patent ID: 7680116

Claim:
A header processing engine for network packets comprising: an input memory to store incoming header information of a packet; a processing unit to generate header information for the packet by operating on the header information stored in the input memory, the processing unit including a first processing component to generate layer 2 (L2) header information for the packet and a second processing component implemented in parallel with the first processing component and to generate layer 3 (L3) header information for the packet; an instruction memory operatively coupled to the first processing component, the instruction memory to provide the first processing component with programming instructions relating to the processing of the L2 header information; and a second instruction memory operatively coupled to the second processing component, the second instruction memory to provide the second processing component with programming instructions relating to the processing of the L3 header information, where the second processing component includes a plurality of execution sections implemented in parallel with one another, each of the plurality of execution sections operating based on a portion of each instruction from the second instruction memory.