Patent ID: 8090931

Claim:
A microprocessor, having a macroarchitecture with a macroinstruction set and a microarchitecture with a microinstruction set, the microprocessor comprising: an x86 EFLAGS register; an instruction translator, configured to translate an x86 push flags (PUSHF) macroinstruction into first, second, and third microinstructions, wherein the PUSHF macroinstruction is an instruction in the macroinstruction set that instructs the microprocessor to push the value of the x86 EFLAGS register of the microprocessor to a memory location specified by a stack pointer register of the microprocessor, wherein the first microinstruction moves the x86 EFLAGS register value into a temporary register of the microprocessor, wherein the second microinstruction masks off bits in the temporary register, and the third microinstruction is a fused store push microinstruction that pre-updates a register specified by a destination field and stores the masked-off value in the temporary register to the memory location, wherein the first, second, and third microinstructions are instructions in the microinstruction set; a hardware reorder buffer (ROB), having a plurality of entries, configured to receive from the instruction translator the fused store push microinstruction into exactly one of the plurality of entries; and an instruction dispatcher, configured to dispatch for execution a store address microinstruction and a store data microinstruction to different respective execution units of the microprocessor, in response to receiving the fused store push microinstruction, wherein neither the store address microinstruction nor the store data microinstruction occupy any of the plurality of ROB entries; wherein the ROB is further configured to retire the fused store push microinstruction after being notified that both the store address microinstruction and the store data microinstruction have been executed.