Patent ID: 7197679

Claim:
A method for testing an integrated semiconductor memory, comprising: providing an integrated semiconductor memory including memory cells each operable to store a data item, the integrated memory cell being operable synchronously with a clock signal in a normal operating state and being operable synchronously or asynchronously with the clock signal in a test operating state; writing a data item into at least one of the memory cells in the normal operating state; switching the integrated semiconductor memory from the normal operating state to the test operating state by actuating a control circuit via a first signal combination including control signals, address signals and data signals; enabling a selection transistor for the at least one of the memory cells in a first test cycle by actuating the control circuit via a state change in one of the control signals, the state change being asynchronous with the clock signal; and reading the memory content of the at least one of the memory cells in a second test cycle in response to the control circuit being actuated by a second signal combination formed from the control signals.