Patent ID: 8551822

Claim:
A method for manufacturing an array substrate in a four mask process, comprising steps in the following sequence: (a) providing a substrate; (b) forming a patterned first metal layer on the surface of the substrate, by a first mask process; (c) forming a first insulation layer and a semiconductor layer in sequence to cover the substrate and the first metal layer, and patterning the semiconductor layer by photolithography to form plural transistor switch areas and etching the semiconductor layer in every transistor switch area by photolithography to form a channel region, by a second mask process; (d) forming a transparent conductive layer and a second metal layer in sequence over the substrate and in the channel region to cover the first insulating layer and the semiconductor layer; (e) forming a photoresist on the surface of the second metal layer, and performing exposure and development to make the photoresist have at least two thicknesses; (f) wet etching the second metal layer uncovered by the photoresist, the transparent conductive layer uncovered by the photoresist, and the photoresist to form a source and a drain in every transistor switch area, and etching the semiconductor layer in every transistor switch area to reveal the channel region, by a third mask process, and (g) forming a patterned second insulation layer on the surfaces of the transistor switch areas and the first insulation layer, by a fourth mask process on the array substrate; wherein the transistor switch areas comprise the second metal layer, and the source and the drain are not conducted to each other.