Patent ID: 6934198

Claim:
An integrated circuit comprising: a block random access memory (“BRAM”) embedded in the integrated circuit; a first embedded counter configured to operate in a first clock domain; a second embedded counter configured to operate in a second clock domain; a first binary adder coupled to a first selected offset value and to a first pointer address from the embedded first counter to provide a first sum of the first selected offset value and the first pointer address; a first binary-to-gray code converter coupled to the first sum and providing a first gray code value; a second binary-to-gray code converter coupled to a second pointer address from the second embedded counter and providing a second gray code value; a first comparator coupled to the first gray code value and the second gray code value and providing a first comparator output if the first gray code value equals the second gray code value; and a first logic block coupled to the first comparator output and generating a first status flag in the second clock domain.