Patent ID: 7991819

Claim:
A method in logic circuitry for performing binary coded decimal addition of two operands and an input carry, the method comprising: grouping said operands into blocks of contiguous bits; computing for each said block from said operands, by a first stage of the logic circuitry, an intermediate sum vector, an intermediate carry vector, a propagate function and a generate function; computing carries, by a second stage of the logic circuitry, including an output carry, from said input carry and the respective propagate functions and generate functions; logically adjusting the respective intermediate sum vectors by a third stage of the logic circuitry to provide adjusted sum vectors, wherein the adjusting is responsive to pre-correction factors, wherein each of the pre-correction factors depends upon a respective intermediate carry vector, at least two of said carries and said input carry; and providing a set of result bits representing a sum for the two operands, the set of result bits including the adjusted sum vectors, so that time required to perform binary coded decimal addition in the logic circuitry is reduced.