Patent ID: 7376812

Claim:
A microprocessor, comprising: an instruction fetch unit that is adapted to successively fetch first and second instructions from adjacent locations in a common program memory, wherein the first instruction is one of a non-VLIW instruction with an instruction length corresponding to a first number of bits and a VLIW instruction with an instruction length corresponding to a second number of bits, the VLIW instruction comprising a plurality of instruction slots, each slot specifying an independent operation, and wherein the second instruction is the other of the non-VLIW instruction and the VLIW instruction, and wherein the first number of bits and second number of bits are different, and wherein a total number of bits contained in the adjacent memory locations in the common program memory is substantially equal to the sum of the first and second number of bits; an instruction decode unit that is adapted to decode both the fetched non-VLIW instruction and the fetched VLIW instruction, wherein the instruction decode unit examines the first number of bits to decode the fetched non-VLIW instruction, and wherein the instruction decode unit examines the second different number of bits to decode the fetched VLIW instruction; a core processor that executes the fetched non-VLIW instruction; and a co-processor that executes the fetched VLIW instruction, wherein a determination of whether to decode and execute the fetched first and second instructions as non-VLIW and VLIW instructions is based on contents of the fetched first and second instructions.