Patent ID: 7451413

Claim:
A method for automatically minimizing leakage current in a circuit design comprising: a) analyzing post layout delay information of a circuit that meets timing limits, wherein the circuit comprises a first type of cells, the first type of cells each having a first threshold voltage and a first leakage current; b) after analyzing post layout delay information, selecting a non-speed-critical path in the circuit; and c) modifying a dopant implant level of at least one transistor in at least one cell along the selected non-speed-critical path to change the first threshold voltage of the transistor to a second threshold voltage and the first leakage current of the transistor to a second leakage current, wherein a magnitude of the first threshold voltage is less than a magnitude of the second threshold voltage, wherein the first leakage current is greater than the second leakage current, and wherein a total leakage current of the circuit is reduced.