Patent ID: 7709827

Claim:
A vertically integrated field-effect transistor comprising: a first electrically conductive layer; a middle layer, formed partially from dielectric material, on the first electrically conductive layer; a second electrically conductive layer on the middle layer; and a nanostructure grown up in a via hole from the bottom of the via hole introduced into the middle layer such that the grown nanostructure does not contact adjacent sidewalls of the via hole, the nanostructure further comprising a first end portion that is coupled to the first electrically conductive layer and a second end portion that is coupled to the second electrically conductive layer; wherein the first end portion of the nanostructure forms a first source/drain region and the second end portion of the nanostructure forms a second source/drain region of the field-effect transistor; wherein the middle layer, between two adjacent dielectric sublayers, has a third electrically conductive layer, the thickness of which is less than the thickness of at least one of the dielectric sublayers; wherein a thin ring structure formed by oxidizing the third electrically conductive layer resulting in an oxidized layer as the gate-insulating region of the field-effect transistor arranged in the third electrically conductive layer, which forms the gate electrode of the field-effect transistor, along the via hole that has been introduced therein.