Patent ID: 8065574

Claim:
A programmable logic device comprising: configuration memory including a configuration memory cell adapted to function as random access memory (RAM), the configuration memory cell having a first port for writing configuration data to the configuration memory cell and a second port for writing RAM data to the configuration memory cell; soft error detection (SED) logic adapted to check for an error in data stored by the configuration memory including the configuration memory cell adapted to function as RAM by calculating a present data value for the configuration memory for comparison with a pre-calculated data value for the configuration memory; and a fuse configurable in a first logic state to enable the SED logic to read RAM data stored in the configuration memory cell through the first port and configurable in a second logic state to prevent the SED logic from reading the RAM data stored in the configuration memory cell, wherein the SED logic can be tested for correct operation by configuring the fuse to enable the SED logic to include the RAM data in calculating a present data value for the configuration memory for comparison with a pre-calculated data value for the configuration memory that does not include the RAM data.