Patent ID: 8635503

Claim:
A scan flip-flop comprising: a regular data input and regular data output both configured to couple to internal circuitry; a scan data input configured to couple to a scan data output of another scan flip-flop; a scan data output configured to couple to a scan data input of another scan flip-flop; a scan enable input configured to receive a scan control signal; a clock input configured to receive a main clock signal, wherein the clock input is configured to route the clock signal to a first input of a clock gating circuit and to a delay path coupled to a second input of the clock gating circuit; and a first latch configured to: capture a value appearing at the regular data input during a capture cycle according to a pulse triggered by a rising edge of the main clock signal, when the scan control signal received by the scan flip-flop is toggled during a low phase of the main clock signal to enter the capture cycle, wherein a width of the pulse is determined by a delay it takes for the clock signal to propagate through the delay path; and provide the captured input data at the regular data output and the scan data output.