Patent ID: 8106504

Claim:
A semiconductor device package structure, comprising: a first die with a through silicon via (TSV) open from a back side of said first die to expose bonding pads; a build up layer coupled between said bonding pads to terminal metal pads by said TSV; a substrate with a second die embedded inside and a top circuit wiring and a bottom circuit wiring on a top and a bottom side of said substrate respectively; a conductive through hole structure coupled between said terminal metal pads to said top circuit wiring and said bottom circuit wiring; and a top build up layer formed on said second die and said substrate, wherein said top build up layer includes a first dielectric layer, a redistribution layer (RDL), a via coupled to metal pads of said second die and said RDL, and a second dielectric layer on said first dielectric layer to cover said RDL.