Patent ID: 8670383

Claim:
An apparatus implemented in at least one of a memory or a processing device, comprising: an engine configured to be coupled to at least one ingress queue and at least one output queue, the engine configured to assign a target delivery time (TDT) to a first packet having a destination, a TDT to a second packet having the destination of the first packet, and a TDT to a third packet having a destination, the first packet, the second packet, and the third packet being in the at least one ingress queue, if a duration of time, between the TDT of the first packet and the TDT of the third packet, exists such that aggregating and sending the first packet and the second packet results in (1) the first packet being sent before the TDT of the first packet and (2) the third packet being sent before the TDT of the third packet: the engine configured to (1) aggregate the first packet and the second packet to produce an aggregated packet, (2) enqueue the aggregated packet on the at least one egress queue, and (3) enqueue the third packet, after the aggregated packet, on the at least one egress queue.