Patent ID: 8575703

Claim:
A semiconductor device layout comprising: a first transistor formed in a first region; a second transistor formed in a second region; a third transistor formed in a third region; a fourth transistor formed in a fourth region; a first active region pattern including an active region of the first transistor; a second active region pattern including an active region of the second transistor; a third active region pattern including an active region of the third transistor; and a fourth active region pattern including an active region of the fourth transistor; wherein the first transistor and the second transistor have the same channel length and the same channel width, the first transistor and the second transistor are paired transistors, the third transistor and the fourth transistor have the same channel length and the same channel width, the third transistor and the fourth transistor are paired transistors, the first active region pattern and the second active region pattern are the same, the third active region pattern and the fourth active region pattern are the same, the active regions of the third and fourth transistors have a longer length in a channel length direction than that of the active regions of the first and second transistors, and the third and the fourth regions have a narrower width in the channel length direction than that of the first and the second regions.