Patent ID: 8443102

Claim:
A packet processor, comprising: a memory storing microcode that specifies respective sets for a plurality of types of a plurality of packets, and the respective set for each type of the plurality of types specifies at least one of a plurality of fields of the type; and a programmable compute pipeline coupled to the memory for sequentially processing the plurality of packets, wherein: the programmable compute pipeline includes a sequence of a plurality of stages, and the sequence begins with an initial stage of the plurality of stages; the initial stage includes an operand selector that extracts a data vector from each packet of the plurality of packets, and the operand selector is programmable to extract the data vector that includes the at least one field specified in the respective set for the type of the packet; each stage other than the initial stage inputs a first version of the data vector and each stage outputs a second version of the data vector, each stage other than the initial stage generating the second version of the data vector that replaces a part of the first version of the data vector with at least one result that the stage computes from the part, wherein for the initial stage, the second version is the data vector from the operand selector, and for each stage other than the initial stage, the first version is the second version from a preceding stage of the plurality of stages in the programmable compute pipeline; and the operand selector of the initial stage is programmable to extract from each packet of the plurality of packets a plurality of portions of the packet and to combine the portions into the data vector, and for each of the types of the plurality of packets, the portions are programmable to include the at least one field that is input by the programmable compute pipeline for sequentially processing the plurality of packets.