Patent ID: 8120397

Claim:
A delay locked loop (DLL) apparatus, comprising: a delay means configured to generate respective rising and falling clocks by delaying a reference clock, synchronize the rising clock replica-delayed with the reference clock, and synchronize the falling clock with the rising clock synchronized by the reference clock; a replica delay unit configured to delay the rising clock to provide the replica-delayed rising clock; a control means configured to control the synchronization of the rising clock by comparing the phases of the reference clock and the replica-delayed rising clock, and control the synchronization of the falling clock by comparing the phases of the rising clock synchronized by the reference clock and the falling clock; and a DCC output unit configured to output an output pulse by transmitting the rising clock of the delay means to the replica delay unit and adjust the pulse width of the rising and falling clocks synchronized with each other in the delay means, wherein the control means comprises: a first phase detector detecting the phase difference between the reference clock and the replica-delayed rising clock to provide a first detecting signal to an update mode generator; a second phase detector detecting the phase difference between the rising and falling clocks to provide a second detecting signal to the update mode generator; and the update mode generator providing an update mode signal as the first detection signal, the second detection signal and an enhanced detection signal.