Patent ID: 7420388

Claim:
A power gated semiconductor integrated circuit comprising: logic circuit to be power gated, said logic circuit having a virtual power rail; header device disposed between said virtual power rail and a power rail for reducing power consumption of said logic circuit; and virtual rail voltage clamp disposed electrically in parallel with said header device for limiting the voltage at the virtual power rail, wherein said virtual rail voltage clamp comprises: P max-VC PFETs, where P max-VC is a maximum number of PFETs needed for said virtual power rail to be substantially at a voltage value V clamp , where V clamp is a desired steady state voltage at the virtual power rail in a power saving state; and P max-VC latches, each latch coupled to and controlling a respective one of said P max-VC PFETs; and wherein said header device comprises: (P f -P max-VC ) PFETS, where (P f -P max-VC ) is a number of PFETs required to produce a certain amount of leakage reduction in said logic circuit.