Patent ID: 8127261

Claim:
A method for defining an environment for formal verification, comprising the steps of: operating a computer system to present a graphical user interface on a display thereof, and executing a design analysis program therein to extract a plurality of design inputs from a specification of a hardware design-under-test; reading into the computer system respective behavior options for the design inputs from a configuration file; displaying the design inputs and respective behavior options thereof on the graphical user interface; establishing a behavioral assignment by designating interactively with the graphical user interface at least a portion of the respective behavior options for application to the design inputs; responsively to the behavioral assignment, generating environment code that is descriptive of the design inputs and designated respective behavior options thereof; and applying the environment code in a verification tool for verification of the design-under-test; and wherein displaying the design inputs and respective behavior options comprises displaying a first list comprising ones of the design inputs upon which the step of establishing a behavioral assignment has not been performed and a second list comprising others of the design inputs for which establishing a behavioral assignment has been performed.