Patent ID: 7462912

Claim:
A semiconductor memory device comprising: a cell array region including a contact layer that directly contacts with source/drain regions of a semiconductor substrate and a plurality of cell capacitors that are electrically connected to the contact layer; a peripheral circuit region in which at least one power decoupling capacitor is formed on the semiconductor substrate, wherein the power decoupling capacitor includes a plurality of capacitor arrays, each of the capacitor arrays including a plurality of capacitors; a plurality of first conductive layers formed at the same level over the semiconductor substrate, wherein the plurality of first conductive layers include a bottom electrode of the cell capacitor and a bottom electrode of the power decoupling capacitor; a second conductive layer for connecting predetermined capacitor arrays among the plurality of capacitor arrays in parallel in the peripheral circuit region, wherein the second conductive layer includes a top electrode of the cell capacitor and a top electrode of the power decoupling capacitor; an interconnection layer formed over the second conductive layer, wherein the interconnection layer is electrically connected to the second conductive layer; and a third conductive layer formed under the first conductive layer in the peripheral circuit region, for connecting predetermined capacitors among the plurality of capacitors in parallel, wherein the third conductive layer and the contact layer in the cell array region are made of the same material and are formed at the same level over the semiconductor substrate.