Patent ID: 8006073

Claim:
A system comprising: a scheduler comprising a first buffer including a first plurality of entries allocated for use by a first thread and a second buffer including a second plurality of entries allocated for use by a second thread; an execution unit; and an instruction fetch unit, wherein the instruction fetch unit is configured to: identify a state associated with buffers in the scheduler; dispatch decoded instructions of the first thread to the first buffer, in response to detecting the state indicates a non-combined state; and temporarily dispatch decoded instructions of the first thread to the second buffer as long as the first thread is assigned by an operating system to receive instructions and the state indicates a combined state, wherein the state indicates the combined state responsive to detecting: there is no available entry of the first plurality of entries in the first buffer; there is an available entry of the second plurality of entries in the second buffer; and the second thread is not assigned by an operating system to receive instructions.