Patent ID: 7594162

Claim:
A Viterbi decoder comprising: a state metric unit receiving branch metrics and generating hard decisions, said state metric unit including a plurality of selectively operable add, compare and select units coupled in cascade, at least one add, compare and select unit having a corresponding pretraceback unit including a first part selecting either a top rail input or a bottom rail input for a top rail output dependent upon a first control signal and a second part selecting either a top rail input of a bottom rail input for a bottom rail output dependent upon a second control signal, each pretraceback unit having a force decision bit input requiring selection of a top rail input for a top rail output and selection of a bottom for a bottom rail output; a hard decision memory connected to said state metric unit and storing said hard decisions; and a traceback unit connected to said hard decision memory, said traceback unit recalling hard decisions from said hard decision memory and forming decoded bits, said traceback unit including a state index shift register generating part of an address for said hard decision memory and a selection signal for selecting a part of data recalled from said hard decision memory, said traceback unit generating an initial address for said hard decision memory corresponding to a last operable add, compare and select unit.