Patent ID: 8504320

Claim:
A differential SR (Set-Reset) flip-flop configured to receive a set signal and a reset signal, and to generate a differential signal pair, the differential SR flip-flop comprising: a first SR flip-flop configured to receive a signal that corresponds to the set signal and a signal that corresponds to the reset signal, and to generate a non-inverted output signal and an inverted output signal; a second SR flip-flop configured to receive a signal that corresponds to the set signal and a signal that corresponds to the reset signal, and to generate a non-inverted output signal and an inverted output signal; and an averaging circuit configured to average a first signal that corresponds to one output signal of the first SR flip-flop and a second signal that corresponds to one output signal of the second SR flip-flop so as to generate a first output signal, and to average a third signal that corresponds to the other output signal of the first SR flip-flop and a fourth signal that corresponds to the other output signal of the second SR flip-flop so as to generate a second output signal, wherein a signal that corresponds to the first output signal and a signal that corresponds to the second output signal are output as the differential output pair.