Patent ID: 7041592

Claim:
A method for forming a metal interconnection layer of a semiconductor device, the method comprising: (a) sequentially forming a first interlayer insulating film, a first material film including a material having a high selectivity to a medium used for removing a photoresist film, and a second material film, on a semiconductor substrate in which a conductive layer is formed; (b) forming the photoresist film on the second material film having a pattern exposing a portion of the second material film; (c) forming a via hole by etching the second material film, the first material film, and the first interlayer insulating film, using the photoresist film as an etch mask; (d) transforming a portion of the first material film exposed to the via hole by reacting with the medium used for removing the photoresist film and removing the photoresist film substantially simultaneously; (e) forming an opening in the first material film wider than the via hole by removing a transformed portion of the first material film selectively; (f) removing the remaining second material film; (g) depositing a metal material to fill the via hole and the opening; and (h) forming a via contact by planarizing the semiconductor device to the first interlayer insulating film.