Patent ID: 7948311

Claim:
A power series predistorter comprising: a delay path for delaying a signal; a distortion generation path having an N-th order distortion generator and a vector adjuster; a divider for dividing an input signal between the delay path and the distortion generation path; a combiner for combining the output of the delay path and the output of the distortion generation path; and a controller for controlling the vector adjuster; N being an odd number not smaller than 3; the controller comprising: a setting unit for specifying the phase or amplitude value of the output of the vector adjuster; a distortion component measurement unit for measuring a distortion component; a minimum condition calculation unit for obtaining a phase or amplitude value that minimizes the distortion component, by using the magnitude of the distortion components corresponding to three or more phase or amplitude values specified for sampling by the setting unit; and a recording unit for recording three or more predetermined phase or amplitude values to be specified for sampling.