Patent ID: 7573337

Claim:
A code NCO for generating a code enable signal for code phase observation, comprising: a first multiplexer which is configured to receive two relatively prime integers, and to feed either of the two integers as a first integer output in accordance with a select signal; an adder which is configured to add the first integer output from the first multiplexer and an integer output from a register in order to feed a second integer output; a second multiplexer which is configured to receive the second integer output from the adder and a code phase adjustment value, and to feed either of them as a third integer output based on an adjustment signal; the register which is configured to latch and to feed the third integer output from the second multiplexer as a fourth integer output in accordance with a sampling clock signal; and a select signal generator which is configured to output the select signal when the select signal generator detects that the fourth integer output from the register is a predetermined integer value which is previously set, wherein the select signal is the code enable signal and, wherein the select signal generator is a comparator which is configured to compare the fourth integer output from the register with a threshold determined from the two integers in order to output the select signal.