Patent ID: 7633126

Claim:
A semiconductor device comprising: a first gate electrode formed over a semiconductor substrate in a first region and a second region; an impurity-diffused region formed in said first region in the surficial portion of said semiconductor substrate at one side of said first gate electrode; a first shared contact formed in said first region electrically connecting said first gate electrode and said impurity-diffused region; a first sidewall formed in said first region and said second region, on the side face on said one side of said first gate electrode; a first source/drain extension region formed in said second region and in the surficial portion of said semiconductor substrate in a self-aligned manner with respect to said first gate electrode; and a first source/drain region formed in said second region and in a self-aligned manner with respect to said first sidewall, and having an impurity concentration higher than that of said first source/drain extension region, wherein a portion of said first gate electrode and said impurity-diffused region are disposed as being apart from each other in said first region, an element-isolating insulating film is formed over the entire surface of said semiconductor substrate between said first gate electrode and said impurity-diffused region, and the distance between said first gate electrode and said impurity-diffused region is substantially equal to the width of said first sidewall.