Patent ID: 7619255

Claim:
A semiconductor device comprising: a polycrystalline silicon thin film having a source region and a drain region at its both ends, which is formed on an insulating substrate with a frontend insulating film interposed between said polycrystalline silicon thin film and said insulating substrate; and a gate electrode formed on said polycrystalline silicon thin film with a gate insulating film interposed between said gate electrode and said polycrystalline silicon thin film, wherein said gate electrode comprises a layer-stacked wiring comprising: a microcrystalline silicon thin film; and a metal thin film formed on said microcrystalline silicon thin film, wherein crystal grains making up a crystal structure of said microcrystalline silicon thin film, each having a length of said microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of said microcrystalline silicon thin film amount to 15% or less of total number of said crystal grains.