Patent ID: 7385437

Claim:
A tunable current reference circuit, said circuit comprising: a current source circuit coupled to a power supply voltage, said current source circuit providing a stable current reference output regardless of fluctuations in said power supply voltage; a start up stage, a current source stage, a differential amplifier and feedback stage, a failsafe stage, and an output stage; said start up stage for causing said current source stage, said differential amplifier and feedback stage, and said failsafe stage to operate at a non-ground operating voltage; a plurality of digitally selectable inputs coupled to said current source circuit for selectively adjusting a value of said current reference output; said current source circuit including an externally biased current mirror that outputs a first current and a second current; said externally biased current mirror biased by a differential amplifier and feedback circuit, which is external to said externally biased current mirror; inputs into said differential amplifier and feedback circuit being a first voltage and a second voltage, which are proportional to said first current and second current, respectively; said differential amplifier and feedback circuit keeping said first current and said second current equal; said current source circuit including a current trim circuit; said current mirror including a first leg and a second leg; said current trim circuit including said plurality of selectable inputs; said current trim circuit coupled to said second leg; each one of said plurality of selectable inputs including a different resistor; said current reference output derived from a threshold voltage of a CMOS transistor that is included in said first leg; said start up stage including first, second, third, and fourth transistors; wherein a source of said first transistor is coupled to said power supply voltage, a gate of said first transistor receives as an input a test signal, a drain of said first transistor is coupled to a source of said second transistor, a gate and drain of said second transistor are coupled together and to a drain of said CMOS transistor and drain and gate of said third transistor, a source of said third transistor is coupled to a drain and gate of said fourth transistor, and a source of said fourth transistor is coupled to ground; and said stable current reference output proportional to said first current and said second current.