Patent ID: 7853777

Claim:
An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads, the apparatus comprising: a plurality of hardware thread contexts, each of said plurality of hardware thread contexts comprising a program counter register; an instruction scheduler configured to select an instruction from one of the plurality of threads for execution by an execution unit, the instruction scheduler having a plurality of storage elements, each associated with a respective one of the plurality of threads, wherein one of said plurality of storage elements for each thread comprises a first value indicating a stalling event for the respective thread and a second value indicating the stalling event has terminated; a plurality of hardware buffers configured to indefinitely store fetched instructions of the plurality of threads after being dispatched to the execution unit, each one of said plurality of hardware buffers associated with a respective first indicator configured to indicate if the respective hardware buffer is allocated for use by one of the plurality of hardware thread contexts and, if so, by which one of the plurality of hardware thread contexts is the hardware buffer so allocated; a second indicator configured to indicate from which of said plurality of hardware thread contexts said instruction scheduler is enabled to dispatch instructions to the execution unit for execution, wherein the second indicator uses the first or second value in each of the plurality of storage elements to determine the indication; one or more first inputs, one of said one or more first inputs configured to indicate that one or more already-dispatched instructions of said one of the plurality of threads in said one of said plurality of hardware buffers have been flushed from the execution unit in response to detecting a stalling event that requires the execution unit to stall execution of at least one of said one or more already-dispatched instructions of said one of the plurality of threads; and control logic, coupled to said plurality of hardware buffers and said one or more first inputs, configured to indicate flushed instructions are no longer already-dispatched, thereby enabling the multithreading processor to re-dispatch said flushed instructions to the execution unit from said one of said plurality of hardware buffers to avoid re-fetching said flushed instructions; wherein the execution unit is configured to stall, rather than flush said one or more already-dispatched instructions, in response to detecting said stalling event when said second indicator indicates that one of said plurality of hardware thread contexts is the only hardware thread context from which said instruction scheduler is enabled to dispatch said instructions to the execution unit for execution.