Patent ID: 8860464

Claim:
A circuit comprising: a dynamic input PFET connected to a power source and a zero keeper output, wherein the dynamic input PFET is configured to couple the power source to the zero keeper output based on a dynamic input; a clock input NFET connected to the zero keeper output and a pull-down node, wherein the clock input NFET is configured to couple the zero keeper output to the pull-down node based on a clock input; a dynamic input NFET connected to the pull-down node and a reference voltage, wherein the dynamic input NFET is configured to couple the pull-down node to the reference voltage based on the dynamic input; a feedback PFET and a clock input PFET connected in series between the power source and the zero keeper output, wherein the feedback PFET is selectively enabled based on a feedback signal and the clock input PFET is selectively enabled based on the clock input; and a feedback NFET connected to the zero keeper output and the pull-down node, wherein the feedback NFET is configured to couple the zero keeper output to the pull-down node based on the feedback signal; and a NOR gate configured to output the feedback signal based on the zero keeper output and a bypass input.