Patent ID: 8587078

Claim:
An integrated circuit, comprising: a silicon substrate with a logical circuit region and a micro electromechanical system (MEMS) region; a metal oxide semiconductor device disposed on the logical circuit region of the silicon substrate; an interconnecting structure disposed above the silicon substrate and electrically connected with the metal oxide semiconductor device, the interconnecting structure comprises a plurality of dielectric layers, wherein each dielectric layer filled with the at least a conductive material; and a MEMS diaphragm disposed between any two adjacent dielectric layers located on the MEMS region, wherein the dielectric layer under the MEMS diaphragm has a plurality of first openings exposing corresponding conductive materials, the MEMS diaphragm comprising: a bottom insulating layer covering sidewalls of the first opening and having at least a first trench; a first electrode layer disposed on the bottom insulating layer and filling into the first trench to electrically connect with the corresponding conductive materials; and a top insulating layer disposed on the first electrode layer.