Patent ID: 7561469

Claim:
A method of programming memory cells of a non-volatile NAND architecture memory array, comprising: applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string that is selected for programming in the NAND architecture non-volatile memory array; selecting one or more intermediate pass voltages between the program voltage and a pass voltage; applying each of the one or more intermediate pass voltages to a word line of a first set of one or more word lines, wherein the first set of one or more word lines are physically adjacent the selected word line; applying the pass voltage to each word line of a second set of one or more word lines, wherein the second set of one or more word lines comprises any word line located between the first set of one or more word lines and an end of the memory string that is physically adjacent a word line of the first set of one or more word lines; and applying a voltage selected to be between a ground and the pass voltage to each remaining unselected word line of the string that does not belong to the first set of one or more word lines or the second set of one or more word lines.