Patent ID: 8254070

Claim:
A vehicle on-board electric power system comprising: at least one field-effect-controlled power transistor configured to apply a vehicle on-board electric power system supply voltage V BB to a load, the load comprising a vehicle electronic system, the at least one field-effect-controlled power transistor having a drain-source breakdown voltage V DS with a positive temperature coefficient TK DS ; a logic circuit configured to actuate the at least one field-effect-controlled power transistor such that the at least one field-effect-controlled power transistor applies the vehicle on-board electric power system supply voltage V BB to the load; a clamping member configured to provide a clamping voltage V CLAMP to the at least one field-effect-controlled power transistor, the clamping voltage configured to protect against overvoltages V o occurring in the vehicle on-board electric power system, wherein the clamping voltage V CLAMP has a positive temperature coefficient TK CLAMP ≈TK DS , and the clamping voltage V CLAMP is lower than or equal to an anticipated maximum overvoltage V Omax in the vehicle on-board electric power system, wherein an inherent parasitic clamping structure of the at least one field-effect-controlled power transistor which is based on an avalanche breakdown is provided as the clamping member, and wherein the clamping voltage V CLAMP is implemented in the form of an avalanche voltage, so that the at least one field-effect-controlled power transistor has a positive temperature coefficient TK DS =TK CLAMP for the avalanche voltage in order to protect it against overloading, and wherein the avalanche voltage for triggering the avalanche breakdown of the inherent parasitic clamping structure in the at least one field-effect-controlled power transistor is lower than or equal to the anticipated maximum overvoltage V Omax in the vehicle on-board electric power system to be protected, so that an overload current is discharged both through the at least one field-effect-controlled power transistor with the inherent parasitic clamping structure and through the load which is coupled to the at least one field-effect-controlled power transistor.