Patent ID: 8402169

Claim:
An information processing system comprising: a plurality of information processing apparatuses that are connected via a network, each information processing apparatus including a first and second device that are interconnected via a system bus conforming to the Peripheral Component Interconnect (PCI) Express bus standard, the first device being a network module having a network communication function and the second device including a functional device that performs a predetermined function and connects to the system bus via an interface device that uses a local interface to exchange information with said functional device and uses an interface conforming to said system bus to exchange information with said system bus, one of the plurality of the information processing apparatuses inputting an external timing signal and functioning as a timing master, and the other information processing apparatuses functioning as timing slaves, wherein said network module in said timing master generates time synchronization information in the form of a packet and time synchronization information in the form of a command in accordance with said external timing signal and transmits said command to the second device connected to said system bus of said timing master and transmits said packet to said timing slaves via said network, each said network module in each said timing slave receives said packet from said timing master, converts said packet to said command, and transmits said command to the second device connected to said system bus of said respective timing slave, and each said interface device includes a message bus target section that communicates over a message bus of said local interface using a first format conforming to said message bus, a data bus access section that communicates over a data bus of said local interface using a second format conforming to said data bus different than the first format, and a system bus converter that converts messages written to said message bus target section and data written to said data bus access section to at least one transaction layer packet conforming to the Peripheral Component Interconnect (PCI) Express bus standard to said system bus, converts messages received from said system bus to the first format for communication over said message bus, and converts data received from said system bus to the second format for communication over said data bus, wherein the message bus of said local interface is supplied with an interrupt signal received from an interrupt line to instruct the functional device to read from the message bus.