Patent ID: 6934204

Claim:
A semiconductor device having a normal mode and a test mode as operating modes, comprising: a terminal; an internal circuit for receiving a signal from said terminal; a test mode detection circuit for detecting that a voltage of said terminal is a test setting voltage higher than a power-supply voltage supplied to said semiconductor device; a switch circuit provided between said terminal and said test mode detection circuit and rendered conductive when an input voltage of said terminal reaches a prescribed voltage higher than said power-supply voltage, for transmitting a signal according to the input voltage of said terminal to said test mode detection circuit; a first interconnection line having a first capacitance, and connecting said terminal and said switch circuit to each other to transmit the input voltage of said terminal to said switch circuit; and a second interconnection line having a second capacitance larger than said first capacitance, and connecting said switch circuit and said test mode detection circuit to each other to transmit the voltage from said switch circuit to said test mode circuit.