Patent ID: 8129251

Claim:
A method for manufacturing a semiconductor device, the method comprising: forming a storage electrode contact plug surrounded by an interlayer insulating film; forming an etching barrier film over the interlayer insulating film; forming an un-doped polysilicon layer over the etching barrier film; forming a doped polysilicon layer over the un-doped polysilicon layer; etching a portion of the doped polysilicon layer, the un-doped polysilicon layer and the etching barrier film to define a storage electrode region and to expose a top surface of the storage electrode contact plug; performing a Meta-stable Poly Silicon (MPS) process so that each of exposed sidewalls of the un-doped polysilicon layer is formed to be concavo-concave; forming a metal storage electrode layer on the semiconductor substrate, the exposed sidewalls of the un-doped polysilicon layer and the doped polysilicon layer, wherein the metal storage electrode layer is directly contacted the exposed sidewalls of the un-doped polysilicon layer and the doped polysilicon layer; performing a chemical mechanical polishing (CMP) process on the metal storage electrode layer until a top surface of the doped polysilicon layer is exposed, wherein the remaining metal storage electrode layer forms a storage electrode and directly connected to the storage electrode contact plug; removing the remaining of the doped polysilicon layer and the un-doped polysilicon layer; forming a dielectric layer on the storage electrode and the etching barrier film; and forming a metal top electrode layer on the dielectric layer.