Patent ID: 8351269

Claim:
A non-volatile memory device having addressable pages of memory cells on associated wordlines, comprising: a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits; a state machine for controlling memory operations including: a read operation on a designated group of pages; sensing and latching a page of data in each of a series of reading cycles, wherein said sensing and latching in a current reading cycle is directed to a current page of data on a current wordline and is responsive to prerequisite data from an adjacent wordline so as to correct for any perturbation effects therefrom; said sensing and latching arranged to, in the current reading cycle, other than the first reading cycles, sense and latch the current page while outputting a previous page sensed and latched in a just passed reading cycle; preemptively sensing and latching the prerequisite data for the current page prior to the current reading cycle; and wherein said preemptively sensing and latching is arranged to, while the previous page is output, preemptively sense and latch the prerequisite data for the current page prior to the current reading cycle and to preemptively sense and latch the prerequisite data for a next page that is to be read while the previous page is output.