Patent ID: 8595518

Claim:
A semiconductor integrated circuit comprising a plurality of internal circuits, and having a normal operation mode, in which a major core circuit among the plurality of internal circuits performs an operation based on a system clock, and a stand-by mode, in which an operating voltage of the core circuit is decreased to a stand-by voltage that is lower than the operating voltage in the normal operation mode, the semiconductor integrated circuit further comprising: a mode switching circuit of the core circuit for switching an operation mode of the core circuit between the normal operation mode and the stand-by mode; and a stand-by canceling circuit of the core circuit for instructing the mode switching circuit to cancel the stand-by mode, wherein: the mode switching circuit and the stand-by canceling circuit are configured to operate in asynchronism with the system clock, and wherein a threshold voltage for operation of the mode switching circuit and a threshold voltage for operation of the stand-by canceling circuit are less than the stand-by voltage; and in the stand-by mode, the operating voltage of the core circuit is decreased to the stand-by voltage which is less than a minimum voltage for core circuit operation based on the system clock.