Patent ID: 7760575

Claim:
A static random access memory (SRAM) operable with a first voltage and a second voltage, said SRAM comprising: a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line; and a control circuit connected between said source line and said second voltage, wherein said control circuit is selectively operable in a working mode in which said source line is connected to said second voltage such that data in said plurality of SRAM cells can be accessed, a sleep mode in which said source line is connected to a third voltage that is between said first voltage and said second voltage such that data is retained while leakage within said SRAM is decreased, and a shutdown mode in which said source line is isolated from said second voltage and said third voltage and is allowed to float to a level that is substantially equal to said first voltage.