Patent ID: 8599059

Claim:
A successive approximation register analog-digital converter (SAR ADC), converting an analog input signal into a digital output signal having N bits counting from a most significant bit to a least significant bit, comprising: a comparator, comprising a positive input terminal coupled to a positive component of the analog input signal and a negative input terminal coupled to a negative component of the analog input signal; a first capacitor digital to analog converter (CDAC), comprising N capacitors C 1,1 ˜C 1,N , wherein each of capacitors C 1,1 ˜C 1,N−1 has a first terminal connected to the positive input terminal and a second terminal switchably connected to a first reference voltage or a second reference voltage, and the capacitor C 1,N is connected between the positive input terminal and the second reference voltage; a second capacitor digital to analog converter (CDAC), comprising N capacitors C 2,1 ˜C 2,N , wherein each of capacitors C 2,1 ˜C 2,N−1 has a first terminal connected to the negative input terminal of the comparator and a second terminal switchably connected to the first reference voltage or the second reference voltage, and the capacitor C 2,N is connected between the negative input terminal and the second reference voltage; and a logic circuit, connected to the comparator wherein for at least one i-th bit cycle of N bit cycle except a least significant bit cycle, the comparator compares a voltage of the positive input terminal with a voltage of the negative input terminal and outputs a first output signal to the logic circuit, the logic circuit determines whether the second terminal of the capacitor C 1,i+1 or C 2,i+1 is to be switched according to the first output signal, after the second terminal of the capacitor C 1,i+1 or C 2,i+1 is switched, the comparator compares the voltage of the positive input terminal with the voltage of the negative input terminal and outputs a second output signal to the logic circuit, and the logic circuit determines whether the second terminal of the capacitor C 1,i is to be switched and whether the second terminal of the capacitor C 2,i is to be switched according to the first and the second output signal.