Patent ID: 7215018

Claim:
A high density low parasitic stacked die BGA or LGA component assembly comprising: a stack of semiconductor or integrated circuit dies mounted on a substrate and laminated to each other; each die having a conformal, insulating coating having openings above specific connection locations at an edge of a top surface of the die as required by a specific component design; the dies laminated on top of each other with an electrically insulating polymer or epoxy preform; the stack being electrically connected vertically; a vertical conductor comprised of a conductive polymer or conductive epoxy; electrical connections including one or more metallic conducting elements bonded to pad locations on the surface of each die and extending, both physically and elctrically from the pad into the vertical conductor so that one end of the metallic conducting element is embedded within the conductive polymer; the mounting and connection of the stack of semiconductor die on the substrate so that the vertical conductors are electrically and physically connected to electrical connection lands on the top surface of the substrate; the mounting of the stack of semiconductor die to the substrate including an under-fill adhesive material between a lowest die in the stack and the top surface of the substrate; the under-fill material extending past the edge of the bottom die and forming a fillet between the side of the die stack and the surface of the substrate; the substrate having one or more conducting layers for connecting the die stack's vertical conductors to the top side of the substrate and to connection points such as solder balls on the bottom surface of the substrate.