Patent ID: 6900625

Claim:
A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a voltage converter for converting a first voltage to an output voltage, the output voltage having a lower voltage than the first voltage and used internally to the memory device, the voltage converter comprising: a voltage conversion circuit having an input node to which the first voltage is provided, an output node at which the output voltage is provided, and a control node to which a control signal having a control voltage is provided, the voltage conversion circuit generating an output voltage having a voltage relative to the first voltage based on the voltage of the control signal; and a feedback circuit having it sense node coupled to the output node, a supply node coupled to the input node, and a feedback node coupled to the control node, the feedback circuit generating a feedback signal at the feedback node to compensate for a decrease in the output voltage in response to the voltage of the output voltage falling below a trigger voltage.