Patent ID: 8086830

Claim:
An arithmetic processing apparatus which processes multiple data in parallel in accordance with a single instruction, said arithmetic processing apparatus comprising: a plurality of processing elements operable to perform a common arithmetic operation based on an evaluation result of an instruction stored in an instruction register; and a condition flag arithmetic operator operable to selectively perform one of a logical operation and a comparison operation on a condition flag stored in each of said plurality of processing elements, and to transfer an operation result to each of said plurality of processing elements, wherein each of said plurality of processing elements updates the condition flag based on the operation result, the operation result being common to said plurality of processing elements, a condition flag mask register having a bit width including a same number of bits as a number of said plurality of processing elements, each bit corresponding one-to-one to each of said plurality of processing elements; and a condition flag converter operable to convert a value of the condition flag from a processing element, the value corresponding to a bit value of said condition flag mask register, into a first logical value, when the logical operation performed by said condition flag arithmetic operator is an OR operation, and to convert a value of the condition flag from said processing element, the value corresponding to a bit value of said condition flag mask register, into a second logical value, when the logical operation performed by said condition flag arithmetic operator is an AND operation.