Patent ID: 8058902

Claim:
A circuit for aligning input signals, the circuit comprising: a clock generating circuit that is responsive to a first signal and a second signal to generate a clock signal, the first signal is associated with a first input signal of the input signals and the second signal is associated with a second input signal of the input signals; a first flip flop, coupled to the clock generating circuit, that is responsive to a first type of edge of the clock signal to output the first signal; a second flip flop, coupled to the clock generating circuit, that is responsive to the first type of edge of the clock signal to output the second signal; a finite state machine (FSM) that is coupled to the clock generating circuit, the first flip flop and the second flip flop, and that is responsive to a second type of edge of the clock signal to detect early arrival of one of the first signal and the second signal with respect to each other, and generate a first control signal that is indicative of delay to be added to the first input signal if early arrival of the first signal is detected and a second control signal that is indicative of delay to be added to the second input signal if early arrival of the second signal is detected; a first programmable delay element coupled to the FSM to delay the first input signal, based on the first control signal, if early arrival of the first signal is detected; and a second programmable delay element coupled to the FSM to delay the second input signal, based on the second control signal, if early arrival of the second signal is detected.