Patent ID: 8557721

Claim:
In an overall multi-step technique for processing a semiconductor wafer which includes a pair of opposing major surfaces, a method that is performed as part of annealing said wafer in a process chamber as an intermediate part of the overall multi-step technique, said method comprising: applying a stress control layer to at least a portion of at least one of the major surfaces of said wafer; exposing said wafer to a pulse of energy having a duration of less than 100 milliseconds at any given exposed location on the wafer to anneal the wafer in order to change at least one characteristic of the wafer to a modified characteristic, and where said exposing subjects the wafer to a thermal profile having at least a first elevated temperature event such that the wafer would respond to the energy source with a given stress behavior without the stress control layer and the wafer exhibits a modified stress behavior as a result of the presence of the stress control layer such that survivability of the wafer is enhanced responsive to said exposing; and removing said stress control layer at least sufficiently for subjecting the wafer to a subsequent step.