Patent ID: 8693604

Claim:
A receiving apparatus, comprising: a first receiving circuit connected with a first transmitting circuit through a first transmission line; and a second receiving circuit connected with a second transmitting circuit which is different from the first transmitting circuit through a second transmission line which is different from the first transmission line, wherein the first receiving circuit comprises: a Clock Data Recovery that generates a first clock based on a signal from the first transmission line; a first demodulation section that demodulates the signal from the first transmission line based on the timing of the first clock; a multiphase clock generation section that generates a plurality of multiphase clocks having phases different from phases of the first clock; and a clock distribution circuit that selects one clock from the plurality of the multiphase clocks generated by the multiphase clock generation section based on a phase controlling signal and outputs it to the second receiving circuit, wherein the second receiving circuit comprises a second demodulation section that demodulates a signal from the second transmission line based on the timing of the clock outputted by the clock distribution circuit, and a phase comparison section that compares a phase of the clock outputted by the clock distribution circuit with a phase of the signal from the second transmission line and outputs the comparison result as the phase controlling signal to the first receiving circuit.