Patent ID: 8129709

Claim:
A semiconductor device comprising: an active region comprising a first diffusion region, a second diffusion region, a third diffusion portion, a first channel region between the first and second diffusion regions and a second channel region between the second and third diffusion regions, the first, second and third diffusion regions and the first and second channel regions being arranged in line in a first direction; a first word line elongated in a second direction that is oblique to the first direction to cross the first channel with an intervention of a first gate insulating film therebetween; a second word line elongated in the second direction to cross the second channel region with an intervention of a second gate insulating film therebetween; a first insulating layer formed to cover the active region and the first and second word lines; a reference line formed over the first insulating layer and elongated in the second direction to cross the second diffusion region with an intervention of a part of the first insulating layer; a first contact plug formed in the part of the first insulating layer to connect the second diffusion region electrically to the reference line; a second insulating layer formed to cover the first insulating layer and the reference potential line; second and third contact plugs selectively formed in the first and second insulating layers to be in electrical contact respectively with the first and third diffusion regions; a third insulating layer formed over the second insulating layer and the second and third contact plugs; a bit line formed over the third insulating layer and elongated in a third direction that is substantially perpendicular to the second direction to cross the first and second word lines and the reference line; a first information storage element formed between the second and third insulating layers, the first information storage element being in electrical contact with the second contact plug and being elongated toward the bit line in a fourth direction that is different from the first direction; a fourth contact plug selectively formed in the third insulating layer to contact the first information storage element electrically to a first portion of the bit line; a second information storage element formed between the second and third insulating layers separately from the first information storage element, the second information storage element being in electrical contact with the third contact plug and being elongated toward the bit line; and a fifth contact plug selectively formed in the third insulating layer to contact the second information storage element electrically to a second portion of the bit line, the second portion of the bit line being apart from the first portion of the bit line.