Patent ID: 7546442

Claim:
A method for performing arithmetic in a memory to memory architecture in an embedded processor executing a 32-bit fixed length instruction set, the method comprising: receiving a 32-bit fixed length instruction, the instruction encoding a source address in a memory using 11 bits, a source address in a register file using 5 bits, a destination address in the memory using 11 bits, a mathematical operation to be performed and first operand size associated with a first operand on which the mathematical operation is to be performed using 5 bits; and responsive to receiving the fixed length instruction: accessing, from the source address in the memory, the first operand on which the mathematical operation is to be performed, without loading the first operand into a register, wherein the accessing the first operand further comprises calculating the source address in the memory from data in the 11 bits of the 32-bit instruction encoding a source address in memory; accessing, from the source address in the register file, a second operand on which the mathematical operation is to be performed; performing the mathematical operation on the first operand and the second operand to obtain a result; and storing the result in the destination address in the memory, wherein the destination address in the memory is different from the source address in the memory.