Patent ID: 7836418

Claim:
A method for generating a new set of timing assertions associated with a design of a circuit, comprising: generating a hierarchical netlist of the design using a design tool executing on a computer, wherein the design includes a plurality of macros; designating one of the plurality of macros as a current macro for processing; designating one of a plurality of pins of the current macro as a current pin for processing; determining a worst timing path that passes through the current pin; determining a slack of the worst timing path; determining a subset of macros of the plurality of macros, wherein the subset of macros includes ones of the plurality of macros that are associated with and on the worst timing path; determining a respective apportionment parameter for each respective macro of the subset of macros, wherein the respective apportionment parameter for each said respective macro comprises a sum of gate widths of all gates contained within said respective macro; determining a distribution of the slack amongst each said respective macro of the subset of macros based upon the respective apportionment parameter associated with each said respective macro; adjusting timing assertions for each said respective macro of the subset of macros based upon the determined distribution of the slack, wherein the timing assertions define arrival times or departure times of a signal; generating a new set of timing assertions for all of the plurality of macros of the design based upon the adjusting the timing assertions; and re-designing the circuit based on the generated new set of timing assertions, wherein the re-designing comprises altering physical aspects of the plurality of macros of the circuit based on the hierarchical netlist and the generated new set of timing assertions.