Patent ID: 8503234

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix, which include a plurality of selecting transistors and a plurality of memory cell transistors, each of the plurality of memory cell transistors being connected in series to respective one of the plurality of selecting transistors; a first bit line connecting to drains of a first set of the plurality of the selecting transistors arranged in a first column; a second bit line connecting to drains of a second set of the plurality of the selecting transistors arranged in a second column; a first plurality of word lines coupled to a first row decoder controlling a first potential of the first plurality of word lines, the first plurality of word lines includes: (i) a first word line connecting to gate electrodes of a first set of the plurality of memory cell transistors arranged in a first row and (ii) a second word line connecting to gate electrodes of a second set of the plurality of memory cell transistors arranged in a second row; a second plurality of word lines coupled to a second row decoder controlling a second potential of the second plurality of word lines, the second plurality of word lines includes: (i) a third word line connecting to gate electrodes of a third set of the plurality of selecting transistors arranged in a third row and (ii) a fourth word line connecting to gate electrodes of a fourth set of the plurality of selecting transistors arranged in a fourth row; a plurality of source lines coupled to a third row decoder controlling a third potential of the plurality of source lines, the plurality of source lines include: (i) a first source line connecting to sources of the first set of the plurality of memory cell transistors arranged in the first row and (ii) a second source line connecting to sources of the second set of the plurality of memory cell transistors arranged m the second row; a column decoder coupled to the first and second bit lines and controlling a potential of said bit lines, wherein the column decoder includes a low withstand voltage transistor having a gate insulation film whose thickness is thinner than a thickness of a gate insulating film of a transistor included in either the first row decoder or the third row decoder, the second row decoder includes a low withstand voltage transistor having a gate insulation film whose thickness is thinner than the thickness of the gate insulating film of the transistor included in either the first row decoder or the third row decoder and wherein information is written into a selected one of the memory cells by applying a first voltage which gradually rises selectively to one of the first word lines by the voltage application circuit; and applying a second voltage to one of the source lines by the second row decoder.