Patent ID: 7944241

Claim:
A clock switch circuit for selectively generating a clock output signal from a selected one of at least two clock input signals, said clock switch circuit comprising: a select circuit comprising an input for receiving a selection signal for selecting one of the at least two clock input signals and at least two outputs for outputting at least two delayed enabling signals and at least two enabling signals; at least two enable circuits, each of said enable circuits comprising an input for receiving one of the at least two clock input signals, an input for receiving one of said delayed enabling signals, an input for receiving one of said enabling signals and an output for outputting an internal clock signal; and a gate to receive the internal clock signals output by the at least two enable circuits and to output said clock output signal corresponding to the selected one of the at least two clock input signals, wherein said clock output signal is fed back to said select circuit so as to generate said at least two delayed enabling signals and said at least two enabling signals on the basis of said clock output signal, wherein said select circuit generates said at least two enabling signals on the basis of said selection signal, and wherein each of said at least two enable circuits comprises a gate for generating an internal enabling signal on the basis of said enabling signal and said delayed enabling signal.