Patent ID: 7972521

Claim:
A method of making a wafer level chip scale package comprising the steps of: forming a semiconductor wafer containing a plurality of circuits in a plurality of layers at each of a plurality of different chip areas, wherein the semiconductor wafer includes for each of the plurality of different chip areas a plurality of conductive bond pads connected to conductive wires; creating a compressive stress within a passivation layer that is applied directly on the plurality of conductive bond pads and the conductive wires, the compressive stress being created using an insulating material for the passivation layer, which insulating material is applied in a highly compressive manner relative to the plurality of layers, thereby causing a completed passivation layer to maintain the compressive stress therein, such that the compressive stress will substantially minimize cracks within the passivation layer during subsequent processing; removing contact areas from portions of the passivation layer to expose certain ones of the plurality of conductive bond pads, wherein the compressive stress within remaining portions of the passivation layer is maintained after the step of removing contact areas is completed; applying an underbump material over each of the exposed conductive bond pads; placing a conductive bump over the underbump material associated with each of the certain ones of the plurality of conductive bond pads and attaching it to the underbump material using a thermal flow cycle; and dicing the wafer to obtain a plurality of bumped die, wherein the compressive stress of the completed passivation layer in an area surrounding each of the plurality of conductive bond pads is maintained after the step of dicing the wafer is completed.