Patent ID: 7417907

Claim:
A memory chip having a data input, a data output, circuitries for resolving collisions of memory addresses of a memory array having a bit line, said chip comprising: circuitry for comparing a read memory address with a write memory address; a sense amplifier coupled to a comparator output of said circuitry and having a sense input coupled to said bit line and a sense output to selectively place data on said bit line at said data output; and bypass circuitry coupled to said comparator output, with said bypass circuitry and said sense amplifier coupled together to selectively prevent data on said bit line from being present on said sense output while allowing write data to be written to said memory array and present on a data output, during a common clock cycle, in response to said read and write memory addresses matching, the bypass circuitry including an AND gate having a first input in electrical communication with an output of said sense amplifier and a second input in electrical communication with an output of a NAND gate with said NAND gate having a first input in electrical communication with said comparator output and a second input in electrical communication with an output of an inverter, said inverter having an input in coupled to a data input.