Patent ID: 7443247

Claim:
A circuit arrangement for detection of a locking condition for a phase locked loop, comprising: a phase locked loop which comprises a phase detector configured to produce a phase signal at an output; a charge pump coupled at one input to the output of the phase detector; and an oscillator coupled at one input to an output of the charge pump and at an output to a first input of the phase detector, and configured to emit an oscillator signal at the output; a counter, which comprises an input configured to receive an input signal derived from the phase signal; a clock input coupled to the output of the oscillator; and an output connection configured to emit an output signal from the counter as a function of a value which represents the pulse length of the phase signal; and an evaluation apparatus which comprises a first input connection coupled to the output connection of the counter, and configured to form a first difference between a first pulse length of a first pulse and a second pulse length of a second pulse which follows the first pulse, and compare the first difference with an adjustable limit value D, and further form at least one further difference between the first pulse length and at least one further pulse length of at least one further pulse which follows the second pulse in time, and further compare at least a further difference with the adjustable limit value D, and further configured to emit an output signal from the evaluation apparatus with a value or state which represents a locked state of the phase locked loop, if the first difference and the at least one further difference are less than the adjustable limit value D.