Patent ID: 7518411

Claim:
A receiving apparatus comprising: a first input buffer that senses and amplifies a voltage difference between a data signal that is input through a positive input terminal and a reference voltage that is input through a negative input terminal; a second input buffer that senses and amplifies a voltage difference between the reference voltage that is input through a positive input terminal and the data signal that is input through a negative input terminal; and a phase detector that detects a phase difference between first and second selection signals that are respectively output from the first input buffer and the second input buffer, wherein the first input buffer comprises: a first input receiving unit that comprises a first input transistor and a second input transistor, wherein the data signal is applied to a gate of the first input transistor and the reference voltage is applied to a gate of the second input transistor; a first sense amplifier that senses and amplifies the voltage difference between a voltage of a first terminal of the first input transistor and a voltage of a first terminal of the second input transistor; a first current offset controlling unit that controls an offset of an electric current that flows through a second terminal of the second input transistor, and wherein the gate of the first input transistor is the positive input terminal of the first input buffer and the gate of the second input transistor is the negative input terminal of the first input buffer.