Patent ID: 8776004

Claim:
A method for improving accuracy of a static timing analysis of a logic design comprising: a) applying a reverse merge to a reverse merge point of a selected circuit within said logic design by using a computer, said circuit having a plurality of inputs; b) identifying a controlling input of said selected circuit controlling an arrival time of an output of said selected circuit; and c) identifying a non-controlling input of said selected circuit that does not control said arrival time at said output of said circuit; d) determining an arrival time difference by subtracting an arrival time of said controlling input of said circuit from an arrival time of said non-controlling input of said circuit; and e) determining for said non-controlling input of said circuit at least one timing value based on said arrival time difference, f) performing design optimization on non-controlling input shifts said input arrival time (AT) value to reduce said reverse merge margin (RMM) metric wherein reaching a zero RMM value indicates that said optimization shifts said AT of said non-controlling input to convert it to a controlling input.