Patent ID: 7650448

Claim:
A Field Programmable Gate Array (FPGA) based configurable data processing integrated circuit, comprising: a high level configuration load unit; a plurality of configurable cells arranged in a two dimensional array; configurable individual lines interconnecting the configurable cells within the array; and at least one interface unit that: at least one of is coupled to and combines the individual lines and thereby defines a device internal bus system; comprises a self-contained external bus interfacing to at least one of external memories and external peripherals; is implemented as a dedicated hardwired interface unit separate from the plurality of configurable cells; is configurable by at least one of the high level configuration load unit and at least some of the plurality of configurable cells, and while the FPGA operates at runtime; and at least one of: (i) receives processing data, the processing data to be processed by the FPGA according to a configuration defined by configuration data; and (ii) transmits data processed by the FPGA, the processing by the FPGA being in accordance with the configuration defined by the configuration data.