Patent ID: 7724485

Claim:
An electrostatic discharge (ESD) protection circuit, comprising: a first supply node; a second supply node; a first N-channel field effect transistor (NFET) having a gate; a second NFET having a gate, wherein the second NFET is coupled in series with the first NFET such that during an electrostatic discharge (ESD) event an ESD current flows from the first supply node, through the first NFET, through the second NFET, and to the second supply node; and an ESD detection circuit that during the ESD event couples the gates of first and second NFETs to the first supply node, wherein the ESD detection circuit comprises: an RC circuit that is coupled to the first supply node and to a third supply node such that during the ESD event the RC circuit conducts current from the first supply node and to a trigger node, and from the trigger node and to the third supply node; an inverter having an input lead that is coupled to the trigger node, wherein the inverter has a first supply voltage lead and a second supply voltage lead, the first supply voltage lead of the inverter being coupled to the first supply node, the second supply voltage lead of the inverter being coupled to the third supply node, wherein the third supply node is not directly connected to the gate of the second NFET; and a P-channel field effect transistor (PFET) having a gate, a source, and a drain, wherein the source is coupled to the trigger node, wherein the drain is coupled to the third supply node, and wherein the gate is coupled to the gate of the second NFET.