Patent ID: 8487707

Claim:
A frequency synthesizer, comprising: a PLL, comprising: an oscillator, for generating an oscillator signal; and a first frequency divider, for dividing a frequency of the oscillator signal to generate a first frequency-divided signal; a switching unit, for switching the PLL to either an open loop status or a closed loop status, wherein a control signal of the oscillator is substantially constant when the PLL is in the open loop status; a second frequency divider, for dividing a frequency of a reference clock to generate a second frequency-divided signal; a counter, for counting according to the first frequency-divided signal and the second frequency-divided signal to generate a counter value when the PLL is in the open loop status; a comparator, for comparing the counter value with a predetermined value to generate a comparing result; and a determining unit, for adjusting an oscillator frequency of the oscillator according to the comparing result; wherein the predetermined value is 2 N in binary form, and N is a positive integer; wherein the comparator comprises: a first logic circuit, for comparing at least one most significant bit (MSB) of the predetermined value and at least one MSB of the counter value; and a second logic circuit, for checking the rest bits of the counter value, wherein the first logic circuit and the second logic circuit are logic circuits of different types.