Patent ID: 8889552

Claim:
A method of manufacturing a semiconductor device, the method comprising: providing a substrate having PMOS and NMOS transistor regions; forming a first metal gate electrode on the substrate in the PMOS transistor region; forming a second metal gate electrode on the substrate in the NMOS transistor region; forming a first metal gate electrode capping layer on the first metal gate electrode and a second metal gate electrode capping layer on the second metal gate electrode; forming a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode; forming a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode; forming a first metal silicide seed layer on the first epitaxial layer and on the first metal gate electrode capping layer; forming a first metal silicide capping layer on the first metal silicide seed layer; forming a second metal silicide seed layer on the second epitaxial layer and on the first metal silicide capping layer; performing a heat-treatment process to form first and second metal silicide layers on the first and second epitaxial layers respectively; removing the first metal silicide seed layer, the first metal silicide capping layer, and the second metal silicide seed layer; forming an interlayer dielectric layer on the PMOS and NMOS transistor regions; forming a first contact plug passing through the interlayer dielectric layer and electrically connected to the first metal silicide layer; forming a second contact plug passing through the interlayer dielectric layer and electrically connected to the second metal silicide layer; and wherein the first metal silicide layer has at least one metal element different from that in the second metal silicide layer.