Patent ID: 7339840

Claim:
A memory system comprising: a memory controller; and at least one memory module on which a number of semiconductor memory chips and connecting lines are arranged in a specified topology, the connecting lines comprising first connecting lines together forming a common transfer channel for a protocol based transfer of data, address and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, wherein the protocol-based data, address and command signals are in common transmitted through the same first connecting lines, and second connecting lines routed separately and in addition to the first connecting lines from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data, address and command signal streams, the at least one memory chip having data processing and re-drive functions respectively, arranged for data, address and command signal processing and for carrying out signal re-drive at least for the data address, and command signals to at least one succeeding semiconductor memory chip being connected adjacent to the at least one memory chip on the memory module by the first connecting lines and/or to the memory controller by the first connecting lines, and the data processing and re-drive commands of the at least one memory chip are respectively further arranged to be activated by the select information as transferred to carry out respective one of data processing and signal re-drive.