Patent ID: 8811079

Claim:
A semiconductor memory device comprising a non-volatile memory area, a volatile memory area, and a controller, the non-volatile memory area comprising: a plurality of first memory cells electrically connected in series, the plurality of first memory cells stacked above a substrate; a first select transistor connected to one end of the plurality of first memory cells, the first select transistor being connected to a first bit line; and a second select transistor connected to the other end of the plurality of first memory cells, the second select transistor being connected to a first source line, the volatile memory area comprising: a plurality of second memory cells electrically connected in series, the plurality of second memory cells stacked above the substrate; a third select transistor connected to one end of the plurality of second memory cells, the third select transistor being connected to a second bit line; and a fourth select transistor connected to the other end of the plurality of second memory cells, the fourth select transistor being unconnected to a second source line, the controller being configured to supply a first voltage to all gates of the second memory cells, the first voltage being capable of turning on the plurality of second memory cells.