Patent ID: 8910022

Claim:
A computing device comprises: a central processing unit (CPU) that includes: a data dispersed storage error coding (DSEC) module operable to: DSEC decode one or more sets of encoded ingress data slices to recapture ingress data; and DSEC encode egress data to produce one or more sets of encoded egress data slices; an instruction DSEC module operable to DSEC decode one or more sets of encoded instruction slices to recapture an instruction; an arithmetic logic unit (ALU) operable to, at least one of: execute the instruction on the ingress data; and execute the instruction to produce the egress data; and a memory system module operable to: coordinate retrieval of the one or more sets of encoded ingress data slices from memory; coordinate retrieval of the one or more sets of encoded instruction slices from the memory; and coordinate storage of the one or more sets of encoded egress data slices in the memory.