Patent ID: 8203215

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface, and four side surfaces; and wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body, wherein: the main body includes: a main part that includes a plurality of layer portions stacked and has a top surface and a bottom surface; and a plurality of terminals that are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the plurality of wires; each of the plurality of layer portions includes a semiconductor chip and a plurality of electrodes, the plurality of electrodes being electrically connected to the plurality of wires; the plurality of electrodes include a plurality of first electrodes that are intended to establish electrical connection to the semiconductor chip, and a plurality of second electrodes that are not in contact with the semiconductor chip; and in at least one of the plurality of layer portions, the plurality of first electrodes are in contact with and electrically connected to the semiconductor chip.