Patent ID: 7295457

Claim:
An integrated circuit (IC) chip, wherein said IC is a CMOS IC array, said IC comprising: a base voltage source connected to a base supply line and supplying a base voltage; a plurality of logic paths, ones of said plurality of logic paths being identified as critical paths, field effect transistors (FETs) in said critical paths having a stated base design characteristic, circuits in said critical paths being connected to said base supply line; an increased voltage source connected to an increased supply line and supplying an increased voltage, said increased voltage being above said base voltage; ones of said plurality of logic paths not being identified as one of said critical paths, circuits in said ones having tailored said FETs and connected to said increased supply line, said tailored FETs exhibiting less leakage at said base voltage than FETs having said stated base design characteristic, wherein said stated base characteristic is a base threshold voltage (V T ) and said tailored FETs have an increased threshold voltage (V T+ ) that is greater than said base V T and, said increased voltage (V dd+ ) exceeds said base voltage (V dd ) at least by the difference between the base V T and said increased V T+ , i.e., V dd+ −V dd >|V T+ −V T |, and wherein said tailored FETs exhibit less leakage at said increased voltage than FETs having said stated base design characteristic at said base voltage; and an array of storage cells and support circuits for said array, said storage cells and support circuits including tailored FETs and connected to said increased supply line, wherein said array is a static random access memory (SRAM) array, said support circuits comprising: a word line decoder selecting a row of cells in said array, a plurality of word line drivers, each driving a selected said row, a bit decoder selecting a column of said cells in said array, at least one sense amplifier sensing data stored in a selected one of said cells, at least one input/output (I/O) driver, each said I/O driver passing written data to a selected said column and redriving sensed said data, local clock logic providing local timing for each cell access, and glue logic for controlling accesses to said SRAM.