Patent ID: 6853215

Claim:
A double data rate compatible input/output (I/O) element circuit for an I/O terminal of logic array comprising: a first input register having an input for receiving a signal at the I/O terminal and an output for registering the I/O terminal signal upon a first edge in an input clock signal, the output of the first input register being connectable to the logic array, a first output register having an input for receiving a first output signal from the logic array and an output for registering the first output signal upon a first edge in an output clock signal, a second output register having an input for, in at least one mode of operation, receiving a second output signal from the logic array and an output for registering the second output signal upon a first edge in the output clock signal, a multiplexer having a first input connected to the output of the first output register, a second input connected to the output of the second output register, an address input configurable to receive the output clock signal, and an output connectable to the I/O terminal.