Patent ID: 8890567

Claim:
A method of testing an integrated circuit (IC), the method comprising: programming a resistive element in the IC at an intermediate ON state, wherein in addition to the intermediate ON state, the resistive element has another ON state, further wherein at the intermediate ON state, the resistive element has a resistance that is at least 10 times greater than a resistance of the resistive element at the another ON state; and applying test data to the resistive element, wherein the programming comprises programming an array of resistive elements that includes the resistive element, wherein the array of resistive elements includes N columns and M rows, wherein N and M are each integers greater than one, further wherein the programming includes programming resistive elements in one column of the plurality of columns, wherein the programming the resistive elements in the one column includes, for each resistive element in the one column to be programmed in the intermediate ON state, applying a normal voltage difference across programming terminals of the each resistive element for an intermediate time period, wherein the normal voltage difference is a voltage difference applied across programming terminals of the each resistive element for a normal time period to program the each resistive element in the another ON state, and further wherein the intermediate time period is shorter than the normal time period.