Patent ID: 7615783

Claim:
A thin film transistor array substrate comprising: an insulating substrate; a first signal line formed on the insulating substrate; a first insulating layer formed on the first signal line; a semiconductor pattern formed on the first insulating layer; a second signal line formed on the semiconductor pattern and crossing over the first signal line; a thin film transistor including a gate electrode, a source electrode, and a drain electrode, the gate electrode connected to the first signal line and the source electrode connected to the second signal lines; a second insulating layer formed on the thin film transistor having a first contact hole exposing the drain electrode; and a first pixel electrode formed on the second insulating layer and connected to the drain electrode through the first contact hole, wherein the first insulating layer includes a first layer having a dielectric constant of about 4 or less, and a second layer being a silicon nitride layer, the second insulating layer has a thickness of equal to or thinner than 500 Å, the first layer of the first insulating layer is formed of a-Si:C:O, and the semiconductor pattern is formed of amorphous silicon.