Patent ID: 8569847

Claim:
A nonvolatile semiconductor memory device having a select gate switch transistor, a memory cell, and a select gate transistor provided next to the memory cell, the select gate switch transistor comprising: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; and a first source/drain region and a second source/drain region formed in the semiconductor substrate so as to face each other, wherein the first source/drain region includes a first n-type impurity layer and a second n-type impurity layer having a higher impurity concentration and a shallower depth than the first n-type impurity layer, the second source/drain region includes a third n-type impurity layer having a lower impurity concentration and a shallower depth than the first n-type impurity layer and a fourth n-type impurity layer having a higher impurity concentration and a deeper depth than the third n-type impurity layer, the second source/drain region is connected to a gate electrode of the select gate transistor via a wiring, and a closest distance between the gate electrode of the select gate switch transistor and the fourth n-type impurity layer is more than a closest distance between the gate electrode of the select gate switch transistor and the second n-type impurity layer.