Patent ID: 7825714

Claim:
An apparatus for decreasing offsets between currents in a differential signaling system, the circuit comprising: a first circuit configured to sense an offset between a first differential current signal and a second differential current signal; said first differential current signal and said second differential current signal comprising a differential signaling pair; a second circuit configured to generate an adjustment current signal based upon the offset between the first differential current signal and the second differential current signal; wherein the adjustment current signal is generated to decrease the offset between the first differential current signal and the second differential current signal by being combined with the first differential current signal; a matched transistor pair including a first sense transistor and a second sense transistor; a first inverter circuit coupled to the drain of the first sense transistor; and a bias circuit coupled to the drain of the second sense transistor, the bias circuit configured to bias the first and second sense transistors such that the drain voltage of the second sense transistor matches the threshold of the first inverter.