Patent ID: 8513718

Claim:
A transistor device comprising: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor, the channel region having an upper pillar with substantially vertical sidewalls directly beneath the gate dielectric, and recessed regions of the semiconductor substrate defined below the upper pillar, the recessed regions having a semicircular profile defined entirely between the substantially vertical sidewalls of the upper pillar; a stressed material embedded in the recessed regions such that a first surface of the stressed material is substantially vertical and in alignment with the substantially vertical sidewalls of the upper pillar, and a second surface of the stressed material conforms to the semicircular profile of the recessed regions; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material, the source and drain regions having substantially vertical sidewalls that abut the substantially vertical sidewalls of the upper pillar and the substantially vertical first surface of the stressed material.