Patent ID: 7590677

Claim:
A method of operating a 32-bit processor to perform sum of 64-bit numbers in a 64-bit processor environment, the method comprising: performing a first sum of numbers operation on a least significant portion of a first number and least significant portions of a plurality of numbers by: a) adding the least significant portion of the first number to a least significant portion of another number from the plurality of numbers, wherein the sum is stored in a first storage location, wherein the first storage location is a register; b) incrementing an overflow counter if a carry is generated by adding the least significant portions of the two numbers, wherein the overflow counter is stored in a status register; c) adding a least significant portion of a next number from the plurality of numbers to the sum stored in the first storage location, wherein the resulting sum is stored back into the first storage location; d) incrementing the overflow counter if a carry is generated by adding the least significant portion of the next number to the sum in the first storage location; e) performing steps c) and d) until each of the least significant portions of the plurality of numbers has been added; f) moving the sum in the first storage location into a second storage location, wherein the second storage location is one or more registers or one or more memory locations; and performing a second sum of numbers operation on a most significant portion of the first number and most significant portions of the plurality of numbers.