Patent ID: 7232732

Claim:
A method of fabricating an electronic device comprising: forming a film stack residing on a topmost surface of a substrate, the film stack comprising a pad oxide layer disposed on said substrate, a first nitride layer disposed on said pad oxide layer, a first polysilicon layer disposed on said first nitride layer, a second nitride layer disposed on said first polysilicon layer, and an isolation oxide layer formed on said second nitride layer; forming a window region by etching a portion of said film stack; forming a slot region for a doped polycrystalline semiconductor plug material within an outer periphery of said etched window region; filling said slot region with said doped polycrystalline semiconductor plug material; depositing a dielectric separation layer over said doped polycrystalline semiconductor plug material and on an uppermost surface of said film stack; depositing a spacer over said dielectric separation layer; etching said spacer and said dielectric separation layer to form a dielectric boot shape on a lower edge of said dielectric separation layer, said lower edge being a portion of said dielectric separation layer proximal to said substrate; and redistributing a dopant from said doped polycrystalline semiconductor plug material into said substrate.