Patent ID: 8407509

Claim:
A method for compensating for variations in timing of data sent on data bit lines relative to a strobe clock sent on a strobe clock line, wherein the data bit lines and the strobe clock line form a link coupling a memory to a processing circuit and wherein the processing circuit comprises a processor and selectable discrete time delays insertable between the processor and link and wherein the strobe clock and the data are sent concurrently over the link from the memory to the processor, the method comprising: sending a request for selected data bit patterns to be sent from the memory to the processing circuit on the data bit lines, the request being sent from the processing circuit to the memory; receiving at the processing circuit a set of strobe clocks and the selected data bit patterns, the set of strobe clocks being sent on the strobe clock line and each strobe clock in the set of strobe clocks is sent concurrently from the memory with one of the selected data bit patterns, wherein the selected data bit patterns comprise two alternately received maximum delay data bit patterns that are a one's complement of each other and are common for all of the data bit lines and two alternately received minimum delay data bit patterns for each one of the data bit lines, the two minimum delay data bit patterns being a one's complement of each other; identifying a discrete minimum time offset value and a discrete maximum time offset value for test data in the selected data bit patterns for each one of the data bit lines, wherein the discrete minimum time offset value is a minimum timing adjustment required to allow the processor to receive the test data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the test data in a steady-state condition during a data valid window of the strobe clock, and wherein the discrete minimum time offset value and discrete maximum time offset value identify a valid range when each one of the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock; selecting a discrete mid range offset value for each one of the data bit lines, the discrete mid range offset value being determined from the discrete minimum time offset value and a discrete maximum time offset value; and aligning the discrete mid range offset value of each of the data bit lines by selective inclusion or removal of at least one of the discrete time delays between the processor and link so that the discrete mid range offset value of each of the data bit lines has a common mid range value.