Patent ID: 7924622

Claim:
An integrated circuit flash memory device comprising: an array of regular flash memory cells; an array of dummy flash memory cells; and an erase controller that is configured to concurrently apply predetermined different first and second bias voltages to the dummy flash memory cells and to the regular flash memory cells, respectively, during an erase operation of the integrated circuit flash memory device such that a potential difference between gates of the dummy flash memory cells and a well of the integrated circuit flash memory device is less than a potential difference between gates of the regular flash memory cells and the well of the integrated circuit flash memory device during the erase operation, wherein the erase controller is configured to concurrently apply a first predetermined positive bias voltage to the dummy flash memory cells and a second predetermined positive bias voltage that is less than the first predetermined positive bias voltage to the regular flash memory cells during the erase operation, while applying a positive well voltage to the well of the integrated circuit flash memory device.