Patent ID: 7164290

Claim:
A logic head, comprising: 3-input look-up tables, multiplexers, XOR gates, registers, two output ports, a carry-in port, and a carry-out port, wherein at least one multiplexer is a standard multiplexer and one is hard-wired, and wherein the logic head can be configured to function as a 2-bit full-adder/subtractor, a counter, an accumulator, a 4-to-1 multiplexer, two 2-to-1 multiplexers, a 4-input look-up table, two 3-input look-up tables, two 2-input look-up table, one 3-input and one 2-input look-up table, two 2-, two 3-, or a 6-input AND gate, two 2-, two 3-, or a 6-input OR gate, or any combination of the said AND and OR gates, and wherein a plurality of logic heads can be configured and connected to implement sum-of-products or product-of-sums of a plurality of variable size minterms and maxterms, and arithmetic functions.