Patent ID: 7906818

Claim:
A memory array, comprising: a first pair of electrically isolated activation lines formed on opposing sides of one or more conductive pillars; a second pair of electrically isolated activation lines formed on opposing sides of the one or more conductive pillars; and a plurality of charge storage nodes, wherein each charge storage node is interposed between a respective one of the conductive pillars and respective one of the activation lines; wherein a memory cell formed at an intersection of a first one of the first pair of activation lines and a given one of the conductive pillars, and a memory cell formed at an intersection of a first one of the second pair of activation lines and the given one of the conductive pillars, form at least a portion of a first serially-coupled string of memory cells; wherein a memory cell formed at an intersection of a second one of the first pair of activation lines and the given one of the conductive pillars, and a memory cell formed at an intersection of a second one of the second pair of activation lines and the given one of the conductive pillars, form at least a portion of a second serially- coupled string of memory cells; and wherein the first one of the first pair of activation lines and the first one of the second pair of activation lines are formed on the same side of the given one of the conductive pillars.