Patent ID: 7617472

Claim:
Buffer circuitry for an integrated circuit, comprising: a regional buffer coupled to a regional signal distribution network limited to a region of the integrated circuit, the regional buffer including: a first multiplexer stage configured for selecting a first input signal as output; a programmable divider stage coupled to receive the first input signal selected from the first multiplexer stage and configured to divide the first input signal selected to provide a first frequency divided signal; a first buffer stage coupled to receive the first frequency divided signal from the programmable divider stage and configured to buffer the first frequency divided signal to provide a first buffered signal; a first vertical regional clock signal line of the regional signal distribution network coupled to the first buffer stage to receive the first buffered signal from the first buffer stage; a second multiplexer stage coupled to the first buffer stage to receive the first buffered signal and configured for selecting the first buffered signal as output; a second buffer stage coupled to the second multiplexer stage to receive the first buffered signal selected from the second multiplexer stage and configured to re-buffer the first buffered signal to provide a first re-buffered signal; and a first branch regional clock signal line of the regional signal distribution network coupled to the second buffer stage to receive the first re-buffered signal.