Patent ID: 7613904

Claim:
A bifurcated scheduler for dispatching instructions in a multithreading processor configured to concurrently execute a plurality of threads, the scheduler comprising: first scheduler logic, configured to issue instructions of the plurality of threads to at least one execution unit of the processor; second scheduler logic, for enforcing a scheduling policy of the plurality of threads, wherein said second scheduler logic comprises a plurality of customer-modifiable registers; and an interface, coupling said second scheduler logic to the first scheduler logic and to said at least one execution unit, said interface comprising: first signal lines, for said first scheduler logic to receive from said second scheduler logic a priority for each of the plurality of threads, wherein said first scheduler logic issues said instructions to said at least one execution unit based on said priorities; and second signal lines, for said second scheduler logic to receive instruction execution information for each of the plurality of threads, wherein said second scheduler logic updates said priorities based on said instruction execution information, wherein said execution information indicates when said at least one execution unit executes an instruction for each of the plurality of threads.