Patent ID: 7627736

Claim:
A controller which is configured to control an array of processing elements, each of which includes a processing unit and an internal memory unit, the controller comprising: a retrieval unit configured to retrieve instructions items for each of a plurality instruction streams, each instruction stream having a plurality of instruction items; a combining unit configured to combine the plurality of instruction streams into a serial instruction stream; an instruction distributor configured to distribute the serial instruction stream to an array of processing elements, wherein the instruction distributor is configured to distribute selectively the serial instruction stream to either an array controller which controls data processing of the array of processing elements, or to a channel controller which controls transfer of data to and from the processing elements; a plurality of instruction stream processors, one for each instruction stream, for controlling the respective instruction streams; a semaphore controller for controlling synchronisation between instruction streams; a status block for providing status information regarding each of the instruction streams; and a scheduler connected to receive status information, and configured to determine which of the instruction streams is to be active.