Patent ID: 7046058

Claim:
A delay-locked loop (DLL) circuit, comprising: a phase interpolator circuit that receives a reference clock signal and generates a finely variably delayed clock signal therefrom responsive to a first control signal; a variable delay circuit that receives the finely variably delayed clock signal and generates a coarsely variably delayed output clock signal therefrom responsive to a second control signal; and a phase control circuit that generates the first and second control signals responsive to the output clock signal and the reference clock signal, the phase control circuit comprising: a phase detector that generates an error signal responsive to a comparison of the reference clock signal to the output clock signal; and a delay control circuit that generates the first and second control signals responsive to the error signal, the delay control circuit comprising: a fine control counter circuit that increments and decrements a fine control count signal responsive to the error signal and that generates a count limit indicator signal responsive to the fine control count signal reaching one of a maximum or minimum count; and a coarse control counter circuit that increments and decrements a coarse control count signal responsive to the error signal subject to the count limit indicator signal, wherein the phase interpolator circuit is responsive to the fine control count signal; and wherein the variable delay circuit is responsive to the coarse control count signal.