Patent ID: 7620780

Claim:
An electronic system, comprising: a plurality of processors, at least one of the plurality of processors configured as a parent processor, and at least two of the plurality of processors configured as child processors of the parent processor, wherein the parent processor is configured to determine an address translation pattern for each of the child processors and respective sets of data to be processed by the child processors; a data cache coupled to the parent processor; at least two dual port memories respectively associated with the at least two child processors, each dual port memory having a first port coupled to the data cache, and a second port coupled to the associated child processor; and a parent cache controller coupled to the parent processor, to the data cache, and to the first port of each dual port memory, the parent cache controller configured to read, in response to a memory request from a child processor and the address translation pattern from the parent processor, a set of data from non-contiguous addresses of the data cache according to the address translation pattern, and write the set of data to contiguous addresses of the dual port memory associated with the requesting child processor.