Patent ID: 7196941

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs; a predetennined number of write line pairs; a predetermined number of read line pairs; at least one data input pad; at least one data output pad; a data input circuit between the at least one data input pad and the predetermined number of write line pairs for transmitting first data which is applied through the at least one data input pad to the predetermined number of write line pairs as second data during a write operation; a plurality of write column selection gates for receiving the first data from the data input circuit and transmitting the second data between the plurality of bit line pairs and the predetermined number of write line pairs in response to a write column selection signal during the write operation; a plurality of read column selection gates for transmitting third data between the plurality of bit line pairs and the predetermined number of read line pairs in response to a read column selection signal during a read operation; and a data output circuit between the at least one data output pad and the predetermined number of read line pairs for outputting the third data as fourth data during the read operation, wherein the fourth data is output through the at least one data output pad, and wherein the first data is input through the at least one data input pad during the write operation and the fourth data is output through the at least one data output pad during the read operation simultaneously.