Patent ID: 7039566

Claim:
A method of estimating a hot carrier lifetime of a MOS transistor, comprising: a) applying plural DC stresses of plural drain voltages, of plural gate voltages and of plural substrate voltages V bs including V bs =0 to plural MOS transistors, b) measuring respective drain currents I d , respective substrate currents I sub and respective lifetimes τ under the applied DC stresses, where the lifetimes τ is defined as a stress time required for a variation rate of drain currents to reach a predetermined value, c) extracting hot carrier lifetime parameter mb and ‘a’ from the measured values of the lifetimes τ, the drain currents I d , the substrate currents I sub and the substrate voltages V bs in a hot carrier lifetime model expressed by: 1/τ=1/τ 0 +1/τ b τ b ∝I sub −mb ·I d mb−2 ·exp( a/|V bs |) where τ 0 denotes a lifetime at the time the substrate voltage V bs =0, τ b denotes a quantity of deterioration of a lifetime at the time the substrate voltage |V bs |>0, and the model parameters mb and ‘a’ represent hot carrier degradation caused by re-bonding between a secondary hot carrier occurring due to application of the substrate voltage and the primary hot carrier, the model parameter mb being defined by the following formula mb =(Φ h /λ h )/(Φ ei /λ e )+2 where Φ b denotes a critical energy of holes to generate damage, Φ ei denotes an impact ionization energy of electrons, and λ h and λ e denote respectively mean free paths of holes and electrons, d) estimating a hot carrier lifetime under a drain current I d , a substrate currents I sub , and the substrate voltages V bs in actual use by using the hot carrier lifetime model, the lifetime τ 0 , and the model parameters mb and ‘a’.