Patent ID: 8032711

Claim:
An integrated circuit comprising: a first die to be stacked with a second die, wherein a through-silicon die-to-die via is coupled between the first die and the second die, the first die having: a static random access memory (SRAM); a bus; and a plurality of processor cores coupled to one another by the bus, the plurality of processor cores to further couple to a dynamic random access memory (DRAM) of the second die via the bus and the through-silicon die-to-die via, wherein the bus to experience a level of usage by the plurality of processors, the plurality of processor cores having a first processor core including: an L1 cache; instruction processing logic to generate a prefetch hint associated with a first load instruction, wherein the instruction processing logic to generate the prefetch hint in response to detecting an instruction pointer history, the prefetch hint representing a level of confidence that two or more load instructions subsequent to the first load instruction are likely to request data from a same cache page, the instruction processing logic further to send the prefetch hint in response to a miss of the L1 cache; and prefetch logic coupled to the instruction processing logic, the prefetch logic to compare to one another the level of confidence represented in the prefetch hint and an indication of the level of usage experienced by the bus, the prefetch logic further to determine, based on the comparing, whether or not to prefetch data, and where the prefetch logic determines to prefetch data, the prefetch logic further to transfer two or more cache lines from an open page in the DRAM to the SRAM, wherein data of the two or more cache lines is transferred by way of the through-silicon die-to-die via and the bus, wherein the DRAM provides a level of cache and the SRAM provides a next higher level of cache.