Patent ID: 7242734

Claim:
A frame boundary discriminator comprising: a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame; a second input for receiving synchronized input frame pulses subject to jitter; an output frame pulse generator controlled by said high speed master clock signal to generate output frame pulses; and a control circuit for comparing the timing of said synchronized input frame pulses with said master clock pulses and adjusting the timing of said output frame pulses to smooth out jitter in said input frame pulses; wherein said output frame pulse generator is a master counter clocked by said high speed master clock pulses that generates said output frame pulses on reaching a predetermined count; wherein said control circuit adjusts the count of said master counter to adjust the timing of said output frame pulses; and wherein there are normally n high speed clock pulses within a frame, where n is a predetermined number, said master counter counts modulo n, said control circuit is configured to assert a first control signal when an input frame pulse arrives at a counter value representing an out-of sync condition, and wherein said counter is configured to adjust its count value to a first predetermined initial value when an input frame pulse arrives while said first control signal is asserted.