Patent ID: 8793419

Claim:
A method, comprising: communicating with a second controller from a first controller via an interface; and communicating with storage from the first controller via the interface, wherein: the first controller is configured to be a master on the interface; the second controller and the storage are configured to be targets on the interface; the second controller is configured to be in a first write mode, wherein in response to receiving a write instruction, the second controller is configured to: determine whether a write address associated with the write instruction is within a range of predefined addresses; and in the event it is determined that the write address is within the range of predefined addresses, store data associated with the write instruction in a second storage managed by the second controller even if a chip select signal associated with the interface indicates that the second controller is not selected; and the storage is configured to be in a second write mode, wherein in response to receiving the same write instruction as the second controller, the storage is configured to: determine whether the chip select signal indicates that the storage is selected; and in the event it is determined that the chip select signal indicates that the storage is selected, store the data associated with the write instruction in the storage, such that in the event (1) the write address is within the range of predefined addresses and (2) the chip select signal indicates that the storage is selected, the data associated with the write instruction is stored in both the storage and the second storage.