Patent ID: 8548788

Claim:
A method comprising: generating a single finite element mesh for predicting performance of an integrated circuit design; identifying a plurality of sample points for conducting a variability study on at least one parameter associated with said integrated circuit design, said sample points being selected to predict performance of said integrated circuit design when subject to variations in said at least one parameter due to variations in manufacturing processes to be used to manufacture said integrated circuit design; generating a parameterized netlist corresponding to each of said sample points; running a technology computer aided design simulation for each of said parameterized netlists, using said single finite element mesh for each of said parameterized netlists, wherein said single finite element mesh remains unchanged for different parameters of each of said parameterized netlists, until convergence is achieved, to obtain, for each of said parameterized netlists, at least one metric indicative of said performance of said integrated circuit design; and developing a predicted design yield for said integrated circuit design, based on said at least one metric determined for each of said parameterized netlists.