Patent ID: 7646041

Claim:
A flash memory device comprising: a local bit line connected to a bit line on a semiconductor substrate having a first conductive type; a semiconductor fin protruding from the semiconductor substrate to extend in one direction; a local source line connected to a common source line intersecting the bit line; a plurality of memory cells connected in parallel to the local bit line and the local source line, wherein the local bit line and the local source line are vertically spaced apart from each other in the semiconductor fin to define respective vertical channels and comprise a first doped layer and a second doped layer, respectively, the first and second doping layers having a second conductive type wherein the doped layers of the local bit line and the local source line extend along the direction in an upper portion or a lower portion of the semiconductor fin; a first select transistor connecting the bit line with the local bit line; a second select transistor connecting the common source line with the local source line; a drain select line and a source select line connected to the first select transistor and the second select transistor, respectively, and arranged to intersect the bit line; and a plurality of word lines connected to the memory cells to intersect the bit line, between the drain select line and the source select line; wherein the semiconductor fin has a top surface and a side surface, and the word lines, the drain select line, and the source select line extend over the top surface and the side surface of the semiconductor fin to intersect the direction.