Patent ID: 7142017

Claim:
An input/output buffer, comprising: an input/output pad operable to receive an input signal and transmit an output signal; an output driver coupled to the input/output pad; an input path comprising an input transistor coupled to the input/output pad operable to pass an input signal received at the input/output pad to a core circuit coupled to the input/output buffer; an output path coupled to the output driver operable to pass an output signal received from the core circuit to the input/output pad; a feedback path coupled to the input transistor in the input path and operable to cut off the output path during input mode when the feedback path is enabled; and a biasing circuit coupled to selected transistors in the output path, feedback path and output driver, wherein the feedback path comprises: a feedback transistor coupled to the input transistor operable to disable the feedback path during output mode; and a pair of serially-coupled transistors coupled to a pass gate in the output path and the feedback transistor and operable to control the pass gate in response to the input signal.