Patent ID: 8488370

Claim:
A method of operating a memory cell, the method comprising: reading the memory cell by determining a threshold voltage difference between: a first threshold voltage of a first transistor; and a second threshold voltage of a second transistor; and writing to the memory cell by degrading one of: the first threshold voltage of the first transistor; or the second threshold voltage of the second transistor; wherein: the memory cell comprises: the first transistor comprising the first threshold voltage and a first control terminal; and the second transistor comprising the second threshold voltage and a second control terminal; the first and second transistors are cross-coupled together; the threshold voltage difference corresponds to a logic state of the memory cell; the first and second transistors comprise thin film transistors; and the first and second threshold voltages are degradable relative to each other to alter the threshold voltage difference between the first and second threshold voltages and to alter the logic state of the memory cell.