Patent ID: 8295088

Claim:
A method of operating a non-volatile memory, comprising: placing a bit line precharge voltage on a first and second bit lines, wherein the first and second bit lines are from differing array banks of a non-volatile memory array, where the non-volatile memory array contains a plurality of non-volatile memory cells coupled into a plurality of array banks; placing a read voltage on a control gate of a selected non-volatile memory cell of a first NAND string containing two or more non-volatile memory cells coupled in series; placing a first pass voltage on control gates of one or more unselected non-volatile memory cells of the first NAND string; coupling the first NAND string to a source line and the first bit line; placing the read voltage on a control gate of a reference non-volatile memory cell of a reference NAND string containing two or more non-volatile memory cells coupled in series; placing a second pass voltage on control gates of one or more unselected non-volatile memory cells of the reference NAND string, wherein the second pass voltage is different than the first pass voltage; coupling the reference NAND string to a source line and the second bit line; and sensing the difference between a voltage level of the first bit line and a voltage level of the second bit line to determine a threshold voltage level of the selected non-volatile memory cell; wherein placing a second pass voltage on control gates of one or more unselected non-volatile memory cells of the reference NAND string comprises placing a voltage on control gates of one or more unselected non-volatile memory cells of the reference NAND string that is greater than the first pass voltage during an erase verify operation of the selected non-volatile memory cell.