Patent ID: 8451152

Claim:
An apparatus comprising: a plurality of pipelined analog-to-digital converters (ADCs), wherein each pipelined ADC is adapted to receive an analog input signal, and wherein each pipelined ADC has a transfer function that is adjustable, and wherein each pipelined ADC includes a compensator; and an adjustment circuit that is coupled to each pipelined ADC, wherein the adjustment circuit adjusts the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity, and wherein the adjustment circuit estimates a inter-stage error that includes at least one inter-stage gain error and a digital-to-analog converter (DAC) gain error, and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error; and a plurality of stages that are coupled to one another in a sequence; and a backend sub-ADC that is coupled to a last stage of the sequence.