Patent ID: 7884019

Claim:
A method of forming a dual-damascene structure in the manufacture of an integrated circuit, comprising: providing a conductor in a low-k dielectric layer; forming a dielectric barrier layer over the conductor and low-k dielectric layer as a via etch-stop layer; forming a low-k interlevel dielectric layer over the dielectric barrier layer; forming a lower hardmask layer over the interlevel dielectric layer; forming an upper hardmask layer over the lower hardmask layer, the lower hardmask layer being more etch selective than the upper hardmask layer; forming an antireflective coating over the upper hardmask layer; forming and patterning a first resist layer over the antireflective coating layer, the patterning defining a via opening etch profile; etching the antireflective coating and upper hardmask layers through the via opening etch profile of the patterned first resist layer to define a via opening down to the lower hardmask layer; removing the patterned first resist layer and antireflective coating after forming the via opening down to the lower hardmask layer; forming an underlayer over the lower hardmask layer and within the via opening after removing the first resist layer and antireflective coating; forming a spin-on glass layer over the underlayer; forming and patterning a second resist layer over the spin-on glass layer, the patterning defining a trench opening etch profile over the via opening; etching the spin-on glass layer, the underlayer, the lower hardmask layer, and the interlevel dielectric layer through the trench opening etch profile of the patterned second resist layer to form a trench opening; the etch operating on the via opening in the upper hardmask layer to extend the via opening below the trench opening; removing the patterned second resist layer, the spin-on glass layer, and the underlayer after forming the trench opening; removing the upper hardmask layer and further etching the interlevel dielectric layer through the lower hardmask layer to deepen the trench opening within the interlevel dielectric layer and to further extend the via opening down to the dielectric barrier layer; and removing the lower hardmask layer and etching the dielectric barrier layer through the extended via opening, to further extend the via opening down to the conductor.