Patent ID: 7565595

Claim:
A convolutional interleaving and de-interleaving circuit, comprising: an initial address generator, which provides a plurality of initial addresses, receives an initial control signal and an accumulating address, and outputs one of said initial addresses and said accumulating address according to said initial control signal; a first address generator, which receives a first control signal and an output from said initial address generator, registers an output of said initial address generator and outputs a first address according to said first control signal; a second address generator, which provides a plurality of basic addresses, receives a second control signal, and outputs a signal as a second address from one of said basic addresses according to said second control signal; an address mixer, which receives said first address and said second address, synthesizes these two addresses to a third address; an adder, which receives said first address, accumulates a preset value to said first address as said accumulating address; a memory, which receives an input data and said third address, to access said input data according to said third address; and a controller, which receives said accumulating address to control said memory for accessing said input data according to said accumulating address, and outputs said initial control signal, said first control signal and said second control signal.