Patent ID: 8583872

Claim:
A cache memory including a plurality of cache blocks in each of a plurality of cache ways, the cache memory comprising: a sector ID memory that stores a plurality of sector IDs of the plurality of cache blocks each corresponding to each of the plurality of cache ways, the sector ID being used for replacing each of the plurality of cache ways; a plurality of way number registers that are each provided for each of the sector IDs, and each hold a maximum way number specifying a maximum number of the cache ways assignable to each of the sector IDs; a comparison unit that compares a number of cache ways having one of the plurality of the sector IDs corresponding to a sector ID attached in a memory access request and the held maximum way number corresponding to the sector ID attached in the memory access request; a selector that selects a replacing sector ID based on a comparison result of the comparison unit; a determination unit that determines one or more replacement way candidates to be replaced from the plurality of cache ways based on the selected replacing sector ID and a plurality of sector IDs stored in the sector ID memory corresponding to a request address included in the memory access request when a cache miss occurs in the cache memory; a selection unit that selects a replacement way from the determined one or more replacement way candidates; and an update unit that updates the stored sector ID based on each of the cache ways in the cache block specified by the memory access request, according to the sector ID attached to the memory access request.