Patent ID: 7723723

Claim:
A memory comprising: a first conductive type first impurity region formed on the main surface of a semiconductor substrate constituting a first electrode of a diode included in a memory cell and a word line; a plurality of second conductive type second impurity regions formed on the surface of said first impurity region at a prescribed interval, each constituting a second electrode of said diode; a bit line formed on said semiconductor substrate and connected to said second impurity regions; and a wire provided above said bit line and including a plurality of contact portions connected to said first impurity region constituting said word line, wherein said plurality of contact portions are formed at a first interval apart from each other, said memory cell does not include a transistor but includes a diode, and said memory cell includes a first memory cell provided with said second impurity region and a second memory cell not provided with said second impurity region, and data of said memory cell is determined to be a first data in case of said first memory cell provided with said second impurity region and is determined to be a second data different from said first data in case of said second memory cell not provided with said second impurity region.