Patent ID: 7702820

Claim:
A hardware accelerator, disposed in a data transmission system, for controlling data to be transmitted from one of a bus controller and a storage device controller to the other of the storage device controller and the bus controller, the hardware accelerator comprising: a decoding unit for decoding a command packet into a control command and judging whether the control command is correct; a descriptor updating unit for updating a descriptor in the bus controller in response to the control command, and thus determining a transfer direction and a transfer length of the bus controller and the storage device controller; an access control unit for controlling the storage device controller to perform a handshake with the bus controller, controlling the data to be transmitted from one of the storage device controller and the bus controller to the other of the storage device controller and the bus controller, and judging whether the data is completely transmitted; a status packet updating unit for generating a status packet and outputting the status packet to the bus controller; and a finite state machine for driving the descriptor updating unit to update the descriptor, driving the access control unit to transfer the data and controlling the status packet updating unit to generate the status packet and output the status packet to the bus controller when the control command is correct, when the descriptor is completely updated and when the data is completely transmitted, respectively.