Patent ID: 7489043

Claim:
A semiconductor chip package comprising: a first semiconductor chip including: a frame section having a top face and a bottom face, a movable structure having a movable section formed in said frame section, a plurality of first electrode pads arranged on said top face side of said frame section, a first sealing section formed on the top face of said frame section and having a closed loop shape surrounding said movable structure, and a thin plate member provided on said first sealing section for sealing said movable structure; a second semiconductor chip having a first surface, a second surface, and a plurality of second electrode pads arranged on said first surface, the first surface being in parallel to the second surface; a lead frame including a chip mount section that has a front face and a back face, and a plurality of leads provided away from an edge of said chip mounting section, said first and second semiconductor chips being mounted on said front face of said chip mounting section; first bonding wires for connecting said plurality of first electrode pads to said plurality of second electrode pads respectively; second bonding wires for connecting said plurality of second electrode pads to said plurality of leads respectively; and a second sealing section for covering and sealing said first semiconductor chip, said second semiconductor chip, said first sealing section, said chip mounting section, said first bonding wires and said second bonding wires, with a part of said plurality of leads being exposed.