Patent ID: 7934139

Claim:
An LDPC decoder for decoding a data matrix having information in bit nodes of rows of the data matrix and check nodes in columns of the data matrix, the LDPC decoder comprising: an input buffer configured to receive the data stream from a Viterbi decoder, a pipeline configured to receive the data stream from the input buffer and provide the data stream in a lockstep pipeline to a plurality of bit units, the plurality of bit units configured to calculate data on bit nodes and provide the data stream to a direct interleaver, the direct interleaver configured to provide data to a plurality of par units, the plurality of par units configured to calculate data on check nodes, and provide data to a reverse interleaver, the reverse interleaver configured to provide data back to the plurality of bit units, the plurality of par units further configured to provide encoded data to an output buffer, the output buffer configured to receive the encoded data from the par units, and a controller configured to coordinate data flow within the LDPC decoder.