Patent ID: 6978343

Claim:
A content addressable memory (CAM) device comprising: a plurality of CAM cells; a plurality of row parity storage elements to store row parity values that correspond to contents of respective rows of the CAM cells; a plurality of column parity storage elements to store column parity values that correspond to contents of respective columns of the CAM cells; and a write circuit to provide an input value to a selected row of the CAM cells, the write circuit including a row parity generator to generate an updated row parity value based on the input value, wherein the write circuit is adapted to provide the updated row parity value to one of the row parity storage elements that corresponds to the selected row of the CAM cells, and wherein the write circuit is adapted to provide the updated row parity value to the one of the row parity storage elements concurrently with providing the input value to the selected row of the CAM cells.