Patent ID: 7755428

Claim:
An amplifying circuit, comprising: an output stage circuit provided with a first output transistor for controlling a conducting current based on a first control signal and a second output transistor for controlling a conducting current based on a second control signal, the transistors causing the output stage circuit to operate as a class AB push-pull circuit; and a pre-stage circuit, in which the first control signal and the second control signal are generated in accordance with an input signal; wherein, the first control signal causes the first output transistor to operate in class AB mode in a first ON period set in accordance with a positive signal period in which the input signal is positive, and places the first output transistor in a cutoff state in a first OFF period set in accordance with a negative signal period in which the input signal is negative; and the second control signal causes the second output transistor to operate in class AB mode in a second ON period set in accordance with the negative signal period, and places the second output transistor into a cutoff state in a second OFF period set in accordance with the positive signal period, the pre-stage circuit comprising: a first control circuit for generating, based on the input signal, a first original control signal, which makes the first output transistor operate in class AB mode, the first control circuit being capable of impressing the first original control signal as a control signal on the first output transistor; a second control circuit for generating, based on the input signal, a second original control signal, which makes the second output transistor operate in class AB mode, the second control circuit being capable of impressing the second original control signal as a control signal on the second output transistor; a second output transistor cutoff circuit for operating in the second OFF period based on the first original control signal, and for setting the control signal impressed on the second output transistor to a cutoff voltage; and a first output transistor cutoff circuit for operating in the first OFF period based on the second original control signal, and for setting the control signal impressed on the first output transistor to a cutoff voltage.