Patent ID: 7808285

Claim:
A driving circuit for a capacitive load which comprises a common electrode and first and second discrete electrodes, comprising: a node coupled to a voltage source for receiving power therefrom; a first switch comprising an input terminal connected to the node and an output terminal, the first switch having a controlling terminal configured to receive a first PWM signal; a second switch comprising an input terminal connected to the output terminal of the first switch, a second node between the output terminal of the first switch and the input terminal of the second switch being configured to connect to the first electrode of the capacitive load, and an output terminal connected to ground, the second switch having a controlling terminal configured to receive a second PWM signal; a third switch comprising an input terminal connected to the node and an output terminal, the third switch having a controlling terminal configured to receive a third PWM signal; a fourth switch comprising an input terminal connected to the output terminal of the third switch, a third node between the output terminal of the third switch and the input terminal of the fourth switch being configured to connect to the second electrode of the capacitive load, and an output terminal connected to ground, the fourth switch having a controlling terminal configured to receive a fourth PWM signal; and a dividing circuit connected between the node and ground, the dividing circuit comprising a first capacitor and a second capacitor connected in series between the node and ground, a connection between said first and second capacitors being an output terminal configured to be connected to the common electrode of the capacitive load which results in the voltage of the common electrode being greater than the voltage of ground.