Patent ID: 7666743

Claim:
A method of fabricating semiconductor devices, the method comprising: forming an isolation layer in a semiconductor substrate, the isolation layer defining an active region of the semiconductor substrate; forming a gate trench including an active trench crossing over the active region and a field trench extending from the active trench to the isolation layer, wherein the active trench includes an upper active trench and a lower active trench below the upper active trench and having a greater width than a width of the upper active trench and wherein the field trench has a bottom surface that is lower than a bottom surface of the lower active trench, wherein a width of the lower active trench is greater than a width of the field trench; and forming a gate electrode filling the gate trench and covering sidewalls of the active region below the active trench, wherein the gate electrode includes an upper active gate electrode to fill the upper active trench, a lower active gate electrode to fill the lower active trench, and a field gate electrode to fill the field trench, wherein a width of the lower active gate electrode is greater than a width of the field gate electrode; wherein the forming of the lower active trench comprises: isotropically etching a portion of the active region, thereby forming the lower active trench having a greater width than the width of the upper active trench and the lower active trench having the bottom surface that is higher than the bottom surface of the field trench.