Patent ID: 7134063

Claim:
An on-chip ROM test apparatus which internally tests a ROM integrated into a semiconductor chip, the on-chip ROM test apparatus comprising: a test control signal generator which, in a test operation, generates a ROM clock signal to operate the ROM and test control signals including a ROM address to access the ROM using external test signals, the test signals including a test mode signal that sets an operational mode of the ROM to a test mode, a test clock signal which generates a clock for testing the ROM, and a test reset signal for initialization; a comparator which compares ROM data that is preprogrammed in the ROM prior to the test operation, and read from the ROM in response to the ROM address with external reference data received by the comparator having a same number of bits as the ROM data, and outputs a comparison result; and a test result accumulator which, in response to the comparison result of the comparator, stores information related to whether an error is present in the RQM data, as a test result, and externally outputs the test result.