Patent ID: 8344491

Claim:
A semiconductor package, comprising: a substrate; a stacked plurality of multi-die building blocks including a first multi-die building block and a second multi-die building block, the first and second multi-die building blocks being stacked and adjacent to each other, each of the first and second multi-die building blocks comprising: a flex tape having a first surface and a second surface, each surface comprising a plurality of electrical traces; a first die coupled, through a first plurality of interconnects, to the plurality of electrical traces of the first surface of the flex tape; and a second die coupled, through a second plurality of interconnects, to the plurality of electrical traces of the second surface of the flex tape, wherein the plurality of electrical traces of the first and second surfaces of the flex tape each include continuous conductive lines that run parallel to a direction of each of the first and second plurality of interconnects; and a molding disposed above the substrate and encapsulating the stacked plurality of multi-die building blocks, wherein an end of the flex tape of each of the first and second multi-die building blocks is coupled to a first surface of the substrate.