Patent ID: 7733718

Claim:
A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line, the DRAM comprising: a plurality of source lines and word lines arranged in a row direction; a plurality of bit lines arranged in a column direction; a plurality of clamp bit lines and reference bit lines arranged in the column direction; a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed; a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the clamp bit line are crossed; a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the reference bit line are crossed; and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.