Patent ID: 8358533

Claim:
A phase-change memory device, comprising: a unit cell including a phase-change resistor; a sense amplifier configured to apply a sensing signal to the unit cell; and a switching unit configured to operate in a standby mode or a read mode according to a global line signal and control whether or not the sensing signal passes through the unit cell according to a state of an active signal in the standby mode, wherein the switching unit comprises: a first switch element configured to operate according to the global line signal, a first terminal of the first switch element being coupled to the unit cell, and a second terminal of the first switch element being coupled to a ground terminal; and a second switch element configured to operate according to a local line signal, a first terminal of the second switch element being coupled to the second terminal of the first switch element, and a second terminal of the second switch element being coupled to the ground terminal, and wherein the switching unit is configured to not allow the sensing signal to pass when the active signal is deactivated and the first switch element is turned off in the standby mode.