Patent ID: 7844937

Claim:
A processor-implemented method for making a semiconductor device having at least one test logic block and at least one functional logic block, the method comprising: retrieving hardware description for the at least one test logic block and mapping the hardware description for the at least one test logic block to logic gates based on user constraints to generate at least one synthesized test logic block; retrieving hardware description for the at least one functional logic block and mapping the hardware description for the at least one functional logic block to logic gates based on user constraints to generate at least one synthesized functional logic block; and merging the at least one synthesized test logic block with the at least one synthesized functional logic block to generate at least one merged synthesized logic block, when the at least one functional logic block meets at least one criterion for selection as a candidate for merger with the at least one test logic block and using the at least merged synthesized logic block in manufacturing the semiconductor device, wherein determining whether the at least one functional logic block meets the at least one criterion for selection as a candidate for merger with the at least one test logic block comprises determining whether a number of sequential elements of the at least one functional logic block is within a predetermined threshold of a number of sequential elements of the at least one test logic block.