Patent ID: 7145409

Claim:
A quadrature VCO (voltage controlled oscillator) comprising a first delay cell for outputting a first in-phase signal and a second in-phase signal with a different phase from the first in-phase signal, and a second delay cell for outputting a first quadrature-phase signal and a second quadrature-phase signal with a different phase from the first quadrature-phase signal, wherein the first delay cell comprises: a first transistor including a gate, a source, a drain for outputting the first in-phase signal, and a back gate for receiving the first quadrature-phase signal; a second transistor including a gate, a source, a drain for outputting the second in-phase signal, and a back gate for receiving the second quadrature-phase signal, the second transistor being cross-coupled to the first transistor; a first LC resonance circuit coupled between the drains of the first transistor and the second transistor and a first power source; a first current source coupled between a node of the sources of the first transistor and the second transistor and a second power source; a first capacitor connected to the back gate of the first transistor and receiving the first quadrature-phase signal; and a second capacitor connected to the back gate of the second transistor and receiving the second quadrature-phase signal, and the second delay cell comprises: a third transistor including a gate, a source, a drain for outputting the first quadrature-phase signal, and a back gate for receiving the second in-phase signal; a fourth transistor including a gate, a source, a drain for outputting the second quadrature-phase signal, and a back gate for receiving the first in-phase signal, the fourth transistor being cross-coupled to the third transistor; a second LC resonance circuit coupled between the drains of the third transistor and the fourth transistor and the first power source; a second current source coupled between a node of the sources of the third transistor and the fourth transistor and the second power source; a third capacitor connected to the back gate of the third transistor and receiving the second in-phase signal; and a fourth capacitor connected to the back gate of the fourth transistor and receiving the first in-phase signal.