Patent ID: 7355274

Claim:
A package comprising: a lower unit package; an upper unit package; each of the upper and the lower unit packages including: a circuit substrate core having a lower surface and an upper surface, each of the lower surface and the upper surface having a solder mask thereon, wire bonding pads provided directly on the lower surface of the substrate core and chip bonding pads provided directly on the upper surface of the substrate core, an IC chip provided on the lower surface of the circuit substrate, the IC chip having an active surface with wire lands and bump lands, chip bumps provided on the bump lands, and bonding wires connecting the wire bonding pads to the wire lands; a second circuit substrate having a lower surface and an upper surface, the second circuit substrate having solder bump pads provided on the lower surface and chip bonding pads provided on the upper surface, the chip bumps of the upper unit package being connected to the chip bonding pads of the lower unit package and the chip bumps of the lower unit package being connected to the chip bonding pads of the second circuit substrate; and external connection terminals provided on the solder bump pads of the second circuit substrate.