Patent ID: 7687395

Claim:
A method for fabricating a semiconductor structure comprising: forming a dielectric liner having a conformal thickness atop a semiconductor structure, said semiconductor structure including a device region and a contact region formed over a substrate; forming a passivation layer atop said dielectric liner; forming upon the passivation layer a mask layer having a first aperture of a first width formed therein; extending the first aperture into the passivation layer stopping on the dielectric liner, while using the mask layer as a first etch mask; forming a reacted material layer upon a sidewall surface and a top surface of the mask layer to form a second aperture having a narrower width than the first aperture, said forming the reacted material layer comprises: forming a reactive material layer upon the mask layer and into the first aperture that is present in the passivation layer; reacting by thermal activation the reactive material layer with the mask layer to form a partially reacted reactive material layer; and stripping unreacted portions of the partially reacted reactive material layer to form the reacted material layer upon the sidewall surface and the top surface of the mask layer; etching the dielectric liner using the reacted material layer as an etch mask to extend the second aperture into the dielectric liner until the contact region is exposed to provide a via with a stepped sidewall; and forming a conductive material within the via having the stepped sidewall.