Patent ID: 7466156

Claim:
A circuit, comprising: a control circuit configured to generate at least a first and second signal in response to a test enable signal; a differential driver circuit coupled to said control circuit, having a differential input node and a differential output node and configured to receive a differential input signal at said differential input node, amplify said differential input signal and transmit a differential output signal onto said differential output node in response said first signal, said differential driver circuit further comprising: a plurality of finite-impulse-response (FIR) latches coupled to said differential input node and configured to store said differential input signal; a plurality of preamplifier circuits coupled to said FIR latches and configured to amplify said differential input signal, wherein said preamplifier circuits are enabled in response to said first signal; a driver output stage coupled to said preamplifier circuits and configured to transmit said differential output signal; and a current digital-to-analog (DAC) circuit coupled to said driver output stage and configured to set drive strength of said driver output stage in response to a plurality of current digital-to-analog converter (IDAC) control signals; a programmable termination impedance circuit coupled to said control circuit and said differential output node, configured to generate a differential termination impedance at said differential output node in response to said second signal; and a differential receiver circuit coupled to said control circuit and said differential output node, configured to receive said differential output signal, convert said differential output signal to a single ended signal and transmit said single ended signal in response to said test enable signal.