Patent ID: 7606055

Claim:
A memory cell for an integrated circuit, comprising: a memory element for storing a logic state, the memory element having a first terminal and a second terminal, wherein the second terminal of the memory element is connected to a bit line; a first access transistor having first and second channel terminals, wherein a first channel terminal of the first transistor is coupled to the first terminal of the memory element, and wherein the second terminal of the first access transistor is connected to a reference potential; and a second access transistor having first and second channel terminals, wherein a first channel terminal of the second transistor is coupled to the first terminal of the memory element, and wherein the second terminal of the second access transistor is connected to the reference potential, wherein the first channel terminals of the first and second access transistors comprise a common diffusion region in a substrate, and wherein the first and second access transistors are independently selectable by respective first and second word lines.