Patent ID: 6902976

Claim:
A method of manufacturing a nonvolatile semiconductor memory having a memory cell area in which memory cell transistors are formed and a peripheral circuit area in which peripheral transistors are formed, comprising: forming a first insulating film over the entire surface of a semiconductor substrate; forming a first electrode layer over the entire surface of the first insulating film; selectively removing the first electrode layer, the first insulating film and the semiconductor substrate; forming device isolation regions to self-align to the first electrode layer; etching the device isolation regions until the top of the device isolation regions in the memory cell area reaches a level midway between the surface of the first electrode layer and the surface of the first insulating film; forming a second insulating film over the entire surface of the semiconductor substrate; removing a portion of the second insulating film over each of the peripheral transistors of the peripheral circuit area to form an opening that exposes a portion of the first electrode layer; forming a second electrode layer over the entire surface of the semiconductor substrate; forming a gate masking pattern on the second electrode layer; patterning the second electrode layer using the gate masking pattern as a mask; selectively etching away the second insulating film using the gate masking pattern as a mask; etching the device isolation regions in the memory cell area until their top reaches the same level as the top of the first insulating film; etching the device isolation regions in the peripheral circuit area until their top reaches a level midway between the surface of the first electrode layer and the surface of the first insulating film; and selectively etching away the first electrode layer using the gate masking pattern as a mask.