Patent ID: 8174071

Claim:
A MOS transistor disposed in a semiconductor substrate, the transistor comprising: a source region of a first conductivity type disposed in a first surface portion of the substrate; a drain region of the first conductivity type disposed in a second surface portion of the substrate; a channel region of a second conductivity type opposite the first conductivity type disposed in a third surface portion of the substrate between the source region and the drain region; a gate dielectric layer disposed over the channel region; an extension dielectric region laterally adjacent to and between the gate dielectric layer and the drain region; a drain extension region of the first conductivity type surrounding the drain region and the lower portion of the extension dielectric region; and a gate electrode having a first portion on the gate dielectric layer and a second portion on the upper surface of the extension dielectric region, wherein the second portion includes a convex projection into the upper surface of the extension dielectric region such that the extension dielectric region has a greater thickness on either side of the projection than below the projection, the projection being over the drain extension region and the second portion having a planar top surface that extends across the entire top of the projection.