Patent ID: 8044695

Claim:
A semiconductor integrated circuit comprising: a data input terminal; a data output terminal; a master latch circuit having an input terminal connected to the data input terminal, a first data retaining terminal to retain logic of data inputted through the data input terminal, and a second data retaining terminal to retain inverted logic of the logic retained in the first data retaining terminal; a slave latch circuit having an input connected to an output terminal of the master latch circuit, an output terminal connected to the data output terminal, a third data retaining terminal to retain logic of the data inputted from the master latch circuit, and a fourth data retaining terminal to retain inverted logic of the logic retained in the third data retaining terminal; a clock signal generating circuit that generates and outputs a first clock signal to control operation of the master latch circuit and a second clock signal to control operation of the slave latch circuit; a first switching circuit connected between the first data retaining terminal and the third data retaining terminal; a controller that controls the clock signal generating circuit and the first switching circuit, said controller configured to control the clock signal generating circuit control to output the first clock signal and the second clock signal with a timing so that the logic of the data retained in the first data retaining terminal becomes identical to the logic of the data retained in the third data retaining terminal, and then to turn on the first switching circuit; and a second switching circuit connected between the second data retaining terminal and the fourth data retaining terminal, and controlled by the controller, wherein the controller is configured to control the clock signal generating circuit control to output the first clock signal and the second clock signal with a timing so that the logic of the data retained in the first data retaining terminal becomes identical to the logic of the data retained in the third data retaining terminal, and simultaneously, the logic of the data retained in the second data retaining terminal becomes identical to the logic of the data retained in the fourth data retaining terminal, and the controller then turns on the first switching circuit and the second switching circuit.