Patent ID: 7391076

Claim:
A semiconductor device comprising: a semiconductor substrate provided with an isolation trench filled with an isolation film; and a plurality of non-volatile memory cells provided on the semiconductor substrate, each of the plurality of non-volatile memory cells comprising: a tunnel insulating film provided on the semiconductor substrate; a floating gate electrode provided on the tunnel insulating film, a width of the floating gate electrode changing in a height direction of the non-volatile memory cells in a channel width direction, and being thinnest between a region above a bottom surface of the floating gate electrode and a region below an upper surface thereof, a control gate electrode above the floating gate electrode; and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode, wherein the plurality of non-volatile memory cells includes a first non-volatile memory cell including a first floating gate electrode and a second non-volatile memory cell, adjacent to the first non-volatile memory cell, including a second floating gate electrode, the isolation film covers lower side portions of the first and second floating gate electrodes in the channel width direction and the isolation film includes a top surface which is higher than a surface of the semiconductor substrate, and the first and second floating gate electrodes include portions whose widths in the channel width direction increase toward downward from a first position where the top surface of the isolation film contacts the first floating gate electrode and a second position where the top surface of the isolation film contacts the second floating gate electrode.