Patent ID: 8051323

Claim:
A data processing apparatus comprising: a plurality of processors configured to perform processing operations; a plurality of auxiliary circuits configured to provide auxiliary functions for said plurality of processors; and comparison circuitry configured to compare processing results of different processors of said plurality of processors; wherein: said plurality of processors have: (i) a locked mode of operation in which each of said plurality of processors separately performs a common processing operation to generate respective processing results, said respective processing results of different processors being compared by said comparison circuitry to identify incorrect operation; and (ii) a split mode of operation in which each of said plurality of processors performs a different processing operation to generate respective different processing results; in said split mode, each of said plurality of auxiliary circuits separately provides auxiliary functions for a corresponding one of said plurality of processors; and in said locked mode, a shared one of said plurality of auxiliary circuits provides auxiliary functions for all of said plurality of processors.