Patent ID: 7430697

Claim:
A method of testing circuits in a programmable logic device comprising a plurality of configurable logic blocks, each configurable logic block having a plurality of logic circuits which may be selectively configured as one of a shift register functioning as a source of test data or a lookup table functioning as a load receiving test data and programmable interconnect elements connecting said plurality of logic circuits, said method comprising the steps of: configuring a configurable logic block of said programmable logic device with a test signal source comprising a first logic circuit functioning as a shift register, said first logic circuit outputting test data comprising address data; configuring said configurable logic block with a second logic circuit functioning as a lookup table; storing data in said first logic circuit functioning as a shift register; routing an output of said first logic circuit of said test signal source to an input of said second logic circuit using programmable interconnect elements of said configurable logic block; coupling said address data from said first logic circuit to an input of said second logic circuit, said address data comprising data of a plurality of combinations of input bits for accessing said lookup table; monitoring an output of said second logic circuit for each combination of said plurality of combinations of input bits; and determining if said second logic circuit is defective in response to monitoring said output of said second logic circuit.