Patent ID: 7791126

Claim:
A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity having a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device comprising: a plurality of active areas formed on the semiconductor substrate and spaced equidistant from each other; said non-volatile memory cells integrated in said plurality of active areas, each non-volatile memory cell comprising a source region, a drain region, and a floating gate electrode coupled to a control gate electrode, a group of said memory cells sharing a common source line of a second type of conductivity integrated in said semiconductor substrate; an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with said common source line, the implanted region short circuiting a drain region with a source region in one of the at least one of the plurality of active areas; and at least one source contact aligned and in electric contact with said implanted region.