Patent ID: 7138309

Claim:
A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compression strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, comprising: preparing a wafer, including preparing a silicon substrate for a CMOS device fabrication; depositing, patterning and etching a first insulating layer on the silicon substrate; depositing, patterning and etching a second insulating layer on the first insulating layer; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H 2 + ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer; smoothing the wafer by CMP; growing a layer of silicon; finishing a gate module; depositing a layer of SiO 2 over the NMOS active area; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compression strained; and completing the CMOS device.