Patent ID: 8330200

Claim:
A vertical semiconductor device comprising: a body layer formed in an epitaxial layer wherein the epitaxial layer is of a first semiconductor type and the body layer is of a second semiconductor type; a gate electrode formed in a trench in the body and epitaxial layer; a source region formed in the body layer next to the gate electrode wherein the source region is of the first semiconductor type; a gate insulator disposed along a sidewall and bottom of the gate electrode, wherein the gate insulator is disposed between the gate electrode and the top source region, between the gate electrode and the body and between the gate electrode and the epitaxial layer; a nitride cap insulator disposed on top of the gate electrode, wherein the cap insulator does not extend beyond sides of the gate electrode; a polysilicon spacer disposed along a sidewall of the source region and a sidewall of the cap insulator wherein the polysilicon spacer is of the first semiconductor type, wherein a top surface of the top source is level with a top surface of a surrounding portion of the body layer and wherein the polysilicon spacer has conductive sidewalls that are exposed to a metal layer; and a body contact region containing dopants of the second semiconductor type formed within the body layer, wherein the body contact region is self-aligned to edges of the polysilicon spacer and the source region.