Patent ID: 8549054

Claim:
An arithmetic processing apparatus for performing addition of absolute values of a first bit string having a first bit width and a second bit string having a second bit width larger than the first bit width, the arithmetic processing apparatus comprising: a dividing unit that divides the second bit string into a low-order bit part having a bit width equal to the first bit width and a high-order bit part which is higher than the low-order bit part; a first arithmetic unit that performs arithmetic operations for a carry to and a borrow from the high-order bit part; a second arithmetic unit that performs addition of absolute values of the low-order bit part and the first bit string; and a selecting unit that selects an output of the first arithmetic unit from among an arithmetic operation result with a carry, an arithmetic operation result with a borrow, and the high-order bit part itself, according to information about the high-order bit part, sign information of the first bit string and the second bit string, and an intermediate result of the addition of the absolute values by the second arithmetic unit.