Patent ID: 8155469

Claim:
A filter circuit comprising: a plurality of adders/subtractors that perform at least addition/subtraction; and a plurality of shifters that perform multiplication/division by a power of two through a shift operation, at least one adder/subtractor and at least one shifter configured to obtain a first calculation result representing a pixel value of a target pixel included in image data multiplied by a first filter coefficient; at least one adder/subtractor configured to obtain a second calculation result representing pixel values of a plurality of peripheral pixels adjacent to the target pixel with each of the pixel values being multiplied by a second filter coefficient; at least one adder configured to obtain a third calculation result by adding the first and second calculation results; and at least one shifter configured to divide the third calculation result by a power of two which is equivalent to a sum of the first and second filter coefficients, so as to output the division result, wherein the filter circuit is configured so that the first and second filter coefficients can be selected to have varying values, and the filter circuit is configured to use five or fewer adders/subtractors to calculate the first, second and third calculation results, the number of adders/subtractors used depending on the values of the first and second filter coefficients.