Patent ID: 8812819

Claim:
Circuitry for reordering at least three successive sets of data items in a radix 4n2m fast Fourier transform (“FFT”) operation comprising: circuitry for producing at least three successive sets of addresses in synchronism with the at least three successive sets of data items, wherein: the data items in each successive set of the data items are produced one after another in succession, the addresses in each successive set of the addresses are produced one after another in succession in synchronism with production of an associated one of the data items, and the order of pairs of adjacent bits in each address in each successive set of the addresses is reversed as compared to the order of the said pairs of adjacent bits in a corresponding address in an immediately preceding one of the sets of addresses; memory circuitry; circuitry for applying each successive set of the data items to a data input port of the memory circuitry; and circuitry for applying each successive set of the addresses to read and write address ports of the memory circuitry so that the data items of each successive set of the data items are stored in the memory circuitry as data items of an immediately preceding set of the data items are read out from a data output port of the memory circuitry.