Patent ID: 7817769

Claim:
A circuit, comprising: a ring oscillator circuit having a plurality of delay elements, the ring oscillator circuit to generate a clock signal frequency by multiplying a reference signal by a specified amount; and provide a clock at the generated clock signal frequency to one or more other circuits in a computer system; a checker circuit to compare a count of clock signal oscillations observed per complete loop of the ring oscillator circuit to a reference count, and to set a flag signal if the clock signal oscillation count is above a high threshold amount or below a low threshold amount, wherein if the flag signal is set, the ring oscillator to tune to a predetermined clock signal frequency; a divider circuit to divide the predetermined clock signal frequency by a predetermined amount to generate an alternate clock signal that approximates the reference signal frequency; and provide the alternate clock signal to one or more other circuits in a computer system that would otherwise receive the reference signal; wherein, if the alternate clock signal is provided, the checker circuit to recompare the loop count to the reference count at set time intervals to determine if the reference signal has resumed operation within the threshold amounts; and wherein, if the reference signal has resumed operation within the threshold amounts, the ring oscillator circuit to resume providing the reference signal to the one or more circuits in the system that were receiving the alternate clock signal.