Patent ID: 7054958

Claim:
A data processing system comprising: a plurality of digital signal processor subsystems, each subsystem including: a digital signal processor, and a memory unit; a peripheral direct memory access unit coupled to the memory unit of each subsystem, the peripheral direct access memory having a plurality of memory subunits, each memory subunit receiving signal groups from at least one of the processor subsystems; and a high level data link controller, the high level data link controller including: FIFO memory unit, the FIFO memory unit storing sequences of signals groups, and a processor, the processor reading a sequence of signal groups from a the FIFO memory unit and transmitting the sequence of signal groups as a signal packet, the processor unit providing an ABORT signal to the processor generating a packet currently being transmitted by the processor when the next sequential signal group is not available in the FIFO memory unit a timely fashion for transmission with the packet.