Patent ID: 7681022

Claim:
A data processing system comprising: a pipelined processor, the pipelined processor including: a general purpose register file; and control logic configured to generate a pseudo-instruction in response to an interrupt request, wherein the pseudo-instruction is configured to cause an interrupt return address to be written to the general purpose register file, the interrupt return address associated with a forwardmost instruction in a pipeline; wherein the pseudo-instruction is further configured to be inserted into a pipeline of the pipelined processor and travel down the pipeline in a substantially similar manner to other instructions that are inserted into the pipeline; wherein the pipeline comprises a plurality of stages including: a decode stage, wherein the decode stage is configured to decode the pseudo-instruction; and a write back stage, wherein the write back stage is configured to write results associated with the pseudo-instruction to the general purpose register file, the results including the interrupt return address associated with the forwardmost instruction.