Patent ID: 7721070

Claim:
A computer system comprising: a memory; a superscalar microprocessor; and a bus coupled between the memory and the superscalar microprocessor, wherein the superscalar microprocessor comprises an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order, and an instruction execution unit configured to concurrently receive a set of from one to a maximum number (N) of instructions from the instruction fetch unit, the instruction execution unit including an instruction buffer configured to store instruction information for each instruction received from the instruction fetch unit, wherein the instruction buffer has sufficient capacity to store the instruction information for at least twice the number N of instructions, a register file comprising a plurality of temporary buffers and a plurality of retired registers, wherein the temporary buffers are arranged in a plurality of groups of temporary buffers, each group of temporary buffers including N of the temporary buffers, renaming logic configured to concurrently establish an association between each instruction in a set of instructions concurrently received from the instruction fetch unit and a respective one of the temporary buffers in a selected one of the groups of temporary buffers, wherein a position of each instruction within the set of instructions determines which one of the temporary buffers in the selected group of temporary buffers is associated with that instruction, a plurality of functional units configured to execute instructions, thereby generating result data, an issue control circuit configured to concurrently issue more than one of the instructions for which instruction information is stored in the instruction buffer to the functional units for execution, the issue control circuit being further configured to issue at least some of the instructions out of the sequential program order, a plurality of data routing paths coupled between the functional units and the register file and configured to transfer result data from more than one of the functional units to the temporary buffers concurrently, and retirement control logic coupled to the register file and configured to retire instructions according to the sequential program order, wherein the retirement control logic is further configured to concurrently retire all of the instructions in a set of instructions after all of the instructions in that set of instructions have completed.