Patent ID: 7663953

Claim:
A DRAM circuit comprising: at least one memory cell comprising a capacitor and a transistor coupled to the capacitor, the at least one memory cell coupled to a bit line; and at least one sense amplifier comprising a pre-charge circuit and a back-to-back inverter coupled to the bit line during normal operation of the DRAM circuit and during a read or refresh operation, the back-to-back inverter having at least one PMOS transistor and at least one NMOS transistor, wherein a source of the at least one PMOS transistor is configured to be coupled to a first voltage source set at a voltage higher than ground through a first MOS transistor, and a source of the at least one NMOS transistor is coupled to second and third MOS transistors, the second MOS transistor is operable to connect the source of the at least one NMOS transistor to a second voltage source set at ground during normal operation of the DRAM circuit, the third MOS transistor is operable to connect the source of the at least one NMOS transistor to a third voltage source set at a negative voltage relative to the second voltage source during the read or refresh operation of the DRAM circuit.