Patent ID: 6850092

Claim:
A FIFO circuit which interfaces the transmission of data items between a sender subsystem operating under a first time domain and a receiver subsystem operating under a second time domain, wherein the first time domain and the second time domain are different and at least one of the time domains operates according to a clock signal, the FIFO circuit comprising: a put interface configured to operate according to the first time domain comprising a put data bus to transmit a data item from the sender subsystem and a put data request input to receive a put request from the sender subsystem to enqueue the data item from the put data bus; a get interface configured to operate according to the second time domain comprising a get data bus to transmit the data item to the receiver subsystem and a get data request input to receive a get request from the sender subsystem to dequeue the data item to the get data bus; and an array of cells, each cell comprising: a register configured to receive the data item from the put data bus and to transmit the data item to the get data bus; a state indicator providing an indication of the state of the cell; a put component configured to operate according to the first time domain to receive a put token from a first adjacent cell, to latch the data item received from the put data bus to the register based on the put request, the put token, and the state of the cell, and to pass the put token to a second adjacent cell; and a get component configured to operate according to the second time domain to receive the get token from the first adjacent cell, to dequeue the data item from the register to the get data bus based on the get request, the get token, and the state of the cell, and pass the get token to the second adjacent cell.