Patent ID: 8539413

Claim:
A method for adjusting circuit clock operating frequency using skew timing analysis, comprising: generating, by a system including a processor, a clock signal with a first operating frequency; determining a first slack time of a first gate signal input of a first gate with respect to the clock signal, wherein the first gate comprises a first signal input to accept a test signal, a first clock input to accept the clock signal, and a first signal output connected to an input of a first circuit element; in response to a determination that the first slack time is negative relative to the clock signal applied to the first clock input of the first gate, adding a first delay to the clock signal applied to the first clock input to yield a first clock signal provided to the first gate to create a first gate signal input positive slack time for the first gate; determining a second slack time of a second gate signal input of a second gate with respect to the clock signal subsequent to the adding the first delay, wherein the second gate comprises a second signal input connected to an output of the first circuit element, a second clock input to accept the clock signal, and a second signal output; and in response to a determination that the second slack time is negative relative to the clock signal applied to the second clock input and that the second gate is not an interface port, adding a second delay to the clock signal applied to the second clock input to yield a second clock signal provided to the second gate to create a second gate signal input positive slack time for the second gate; and in response to a determination that the second slack time is negative relative to the clock signal applied to the second clock input and that the second gate is an interface port, advancing the first clock signal based on a value of the second slack time.