Patent ID: 8838775

Claim:
An apparatus, comprising: a processor; and a memory including computer program code, where the memory and computer program code are configured to, with the processor, cause the apparatus at least to: implement a control mechanism for a packet data system, said control mechanism comprising a control entity configured to detect a defined period of inactivity on a packet data context for carrying packet data and to trigger a packet data convergence protocol clearance procedure for releasing packet data resources associated with the packet data context in response to the detection of the defined period of inactivity, wherein the control entity comprises at least one first timer configured to detect an end of a data packet flow on at least one logical channel, and a packet data convergence protocol entity configured to start at least one second timer, wherein the at least one second timer is configured to start in response to an indication by the at least one first timer, and wherein the indication comprises logical channel identification of the at least one logical channel, wherein based on an expiration of the at least one second timer, the packet data convergence protocol entity is configured to initiate the packet data convergence protocol clearance procedure for releasing packet data resources associated with the logical channel identification, and wherein the at least one first timer is restarted in response to detection of activity on the packet data context.