Patent ID: 7363178

Claim:
A method of determining duty cycle information for an electronic circuit, the method comprising: sending, by a clock signal generator, a clock signal to the electronic circuit, the electronic circuit including a clock distribution network that distributes the clock signal to a plurality of locations across the clock distribution network; operating, by a relative duty cycle measurement circuit, in a benchmark mode to determine benchmark duty cycle information with respect to the clock signal at a location external to the clock distribution network, thus designating an external clock signal; operating, by the relative duty cycle measurement circuit, in a relative mode to determine relative duty cycle information of the clock signal at one of the plurality of locations in the clock distribution network relative to the benchmark duty cycle information, thus designating an internal clock signal; selecting as an input signal, by a multiplexer, the external clock signal when the relative duty cycle measurement circuit operates in the benchmark mode; selecting as an input signal, by the multiplexer, the internal clock signal when the relative duty cycle measurement circuit operates in the relative mode; and supplying, by the multiplexer while in the benchmark mode, the external clock signal to a programmable pulse shaper circuit that alters the duty cycle of the external clock signal by a number of increments and that supplies a modified external clock signal to a test divider, the number of increments being increased until the test divider exhibits failure, the test divider providing a test divider output signal.