Patent ID: 7061933

Claim:
A bus circuit, comprising: a plurality of bus nodes; a plurality of transceiver circuits outputting and receiving data signals and control signals characterizing the data signals; said transceiver circuits having connecting lines connecting each of said transceiver circuits to a respective one of said bus nodes, and wherein the respective said bus nodes are in turn connected to a further transceiver circuit or a further bus node; each of said bus nodes having data signal input lines for receiving data signals and associated control signal input lines for receiving control signals characterizing a data signal from one of a respective transceiver circuit or a respective one of said bus nodes; data signal output lines for outputting data signals and associated control signal output lines for outputting control signals characterizing a data signal to a respectively connected transceiver circuit or a respective one of said bus nodes; a first circuit for forwarding a received data signal to a respectively connected transceiver circuit or a bus node if an associated control signal is received on the associated control signal input line at the same time as the data signal; and a second circuit for forwarding a received control signal to all connected transceiver circuits or bus nodes except to said transceiver circuit or bus node from which the control signal has been received.