Patent ID: 7666697

Claim:
A method of manufacturing a thin film transistor (TFT) substrate, the method comprising: forming a first metal layer made of at least one low resistance material selected from the group consisting of aluminum (Al), aluminum neodymium (AlNd), copper (Cu), and silver (Ag); forming a second metal layer comprising chromium (Cr) on the first metal layer; forming a third metal layer comprising chromium nitride (CrNx) on the second metal layer; forming an etch mask on the third metal layer, wet etching the third and second metal layers using the etch mask and then wet etching the first metal layer using the etch mask, and forming a third metal layer pattern, a second metal layer pattern and a first metal layer pattern, respectively; and selectively re-wet etching the second and third metal layer patterns using the etch mask to make widths of the second and third metal layer patterns smaller than a width of the first metal layer pattern, and completing a gate wire comprising the three metal layers, wherein the gate wire includes a gate line, a gate electrode, and a gate line pad having an auxiliary gate line pad physically contacting the top of the gate line pad.