Patent ID: 8429214

Claim:
A programmable integrated circuit comprising: a plurality of configurable floating point units for performing floating point calculations, the plurality of configurable floating point units having a first configurable floating point unit and a second configurable floating point unit, the first configurable floating point unit performing a first floating point calculation, the second configurable floating point unit performing a second floating point calculation, the first configurable floating point unit being coupled to a second configurable floating point unit; a first logic and routing block having a plurality of dedicated logic cells, each dedicated logic cell having a first logic and routing cell and a second logic and routing cell; one or more first dedicated lines connecting from a first logic and routing cell in a first dedicated logic cell of the first logic and routing block to a first plurality of inputs in the first configurable floating point unit in the plurality of configurable floating point units; and one or more second dedicated lines connecting from a first plurality of outputs in the first configurable floating point unit in the plurality of configurable floating point units to the first logic and routing cell in the first dedicated logic cell of the first logic and routing block.