Patent ID: 6879202

Claim:
A programmable logic device (PLD), comprising: a system clock input pad providing a system clock input signal; a system clock buffer having an input terminal coupled to the system clock input pad and further having an output terminal; a central node coupled to the output terminal of the system clock buffer; a plurality of secondary clock buffers each having an input terminal coupled to the central node and each further having an output terminal; a plurality of programmable logic blocks divided into sets, each set including a plurality of programmable logic blocks, each set having an associated secondary clock buffer, each programmable logic block having an input clock terminal; and a plurality of synthesizer circuits, each synthesizer circuit having an associated programmable logic block, each synthesizer circuit being coupled between the input clock terminal of the associated programmable logic block and the output terminal of the associated secondary clock buffer, wherein each synthesizer circuit comprises means for selectively decoupling the input clock terminal of the associated programmable logic block from the output terminal of the associated secondary clock buffer and providing a steady-state signal to the input clock terminal of the associated programmable logic block.