Patent ID: 7315154

Claim:
A voltage regulator comprising: an output MOS transistor connected between a voltage source and an output terminal; a voltage dividing circuit disposed between the output terminal and GND; a reference voltage circuit; an error amplifier that receives a reference voltage from the reference voltage circuit and a division voltage from the voltage dividing circuit; and a current limiting circuit disposed between the voltage source and the output terminal, the current limiting circuit comprising a first MOS transistor connected to the voltage source and controlled based on an output signal from the error amplifier, a current source circuit disposed between the first MOS transistor and the output terminal, a resistor connected to the voltage source, a second MOS transistor controlled based on a voltage that causes a current to flow through the first MOS transistor, and a third MOS transistor connected between the voltage source and an output terminal of the error amplifier and controlled based on a voltage that causes a current to flow through the resistor; wherein when a current caused to flow through the first MOS transistor reaches a predetermined current, the current limiting circuit controls the output MOS transistor to limit a current outputted through the output terminal, and wherein the current source circuit comprises: a constant current circuit connected to the voltage source; a first N-channel MOS transistor connected to the constant current circuit; a second N-channel MOS transistor and a third N-channel MOS transistor disposed in current mirror relation to the first N-channel MOS transistor; a first P-channel MOS transistor connected between the voltage source and the second N-channel MOS transistor; a second P-channel MOS transistor disposed in current mirror relation to the first P-channel MOS transistor; a fourth N-channel MOS transistor connected between the second P-channel MOS transistor and the third N-channel MOS transistor; and a fifth N-channel MOS transistor connected between the output terminal and the first MOS transistor and disposed in current mirror relation to the fourth N-channel MOS transistor.