Patent ID: 7674673

Claim:
A manufacturing method of a semiconductor device, comprising the steps of: forming a stacked pattern of successively stacked gate electrode layer and insulating layer including silicon nitride so as to extend across an active region surrounded with an element isolation structure in a direction not perpendicular to an extending direction of said active region but in an oblique direction; forming a pair of impurity diffusion regions on a surface of said active region, said gate electrode layer being located between the impurity diffusion regions; forming a silicon nitride film so as to cover a transistor having said gate electrode layer and said pair of impurity diffusion regions, forming a silicon oxide film to cover said transistor having said gate electrode layer and said pair of impurity diffusion regions; forming a band-shaped opening pattern extended in said extending direction of said active region and having a width greater than said active region in said silicon oxide film in a region above a whole of said active region to expose an upper surface of said silicon nitride film from said opening pattern; removing said silicon oxide film of a sidewall of said opening pattern so as to increase a width of said opening pattern, exposing each of said pair of impurity diffusion regions by removing said silicon nitride film exposed in said opening pattern, embedding a conductive layer in said opening pattern; and removing said conductive layer and said silicon oxide film until an upper surface of said insulating layer is exposed to form first and second plug conductive layers each electrically connected to each of said pair of impurity diffusion regions and to make an upper surface of each of said first and second plug conductive layers and an upper surface of said insulating layer form substantially an identical plane.