Patent ID: 8797810

Claim:
A semiconductor integrated circuit, comprising: a memory cell array ( 11 ) including: a pair of bit lines (DT/DB); a plurality of word lines (WLn), and a plurality of memory cells (MCn), each of the plurality of memory cells including a gate transistor (TTr) whose gate is connected to one of the plurality of word lines (WLn) and to one of the bit lines (DT/DB), and a plurality of driving circuits (DRV), each of the plurality of driving circuits being provided to drive the associated one of the plurality of word lines (WLn) and including a drive transistor (DMP/DMN) that has a gate oxide film thicker than a gate oxide film of the gate transistor (TTr), wherein a range of voltage between the gate and back-gate of the gate transistor (TTr) is larger than a voltage range of the bit lines (DT), wherein the plurality of driving circuits comprise a plurality of first driving circuits ( 10 ) that are formed in a first region and a plurality of second driving circuits ( 20 ) that are formed in a second region, and wherein the memory cell array ( 11 ) is provided between the first and the second region.