Patent ID: 7863192

Claim:
A method of fabricating an integrated circuit, comprising: providing a p-type doped polysilicon gate structure and an n-type doped polysilicon gate structure on a semiconductor body; implanting the p-type doped polysilicon gate structure with an n-type dopant species to form a counter-doped region in a top portion of the p-type doped polysilicon gate structure, the counter-doped region extending less than 10% into the p-type doped polysilicon gate structure; following the counter-doping, immersing the semiconductor body in an activation solution to simultaneously form catalytic seeds in the n-type doped polysilicon gate structure and in the counter-doped region of the p-type doped polysilicon gate structure; following the catalytic seed formation, immersing the semiconductor body in a metal solution to simultaneously and selectively electrolessly metal plate the n-type and p-type doped polysilicon gate structures; and performing a thermal process to cause the n-type and p-type doped polysilicon gate structures to react with the plated metal to convert the polysilicon into metal silicide.