Patent ID: 8569135

Claim:
A method of forming a semiconductor structure comprising: forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity; forming a gate dielectric layer in said gate cavity; forming at least one planar work function material portion having a topmost surface that is recessed from a topmost surface of said planarization dielectric layer on said gate dielectric layer in said gate cavity, wherein each of said at least one planar work function material portion is formed by anisotropically depositing a work function metal material layer that provides vertical portions of the work function metal material layer having a lesser thickness than a horizontal portion of the work function metal material layer so that said horizontal portion of said work function metal material layer has a thickness that is at least three times a thickness of said vertical portion of said work function metal material layer, wherein forming the at least one planar work function material portion further includes removing said vertical portions of said work function metal material layer with an isotropic etch so the horizontal portion of the work function metal material layer remains to provide the at least one planar work function material portion; and filling said gate cavity with a metal layer contacting said at least one planar work function material portion.