Patent ID: 8116119

Claim:
A static random access memory, comprising: a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines; and a write replica circuit generating a signal when data has been written to the write replica circuit, wherein a wordline of the memory array is turned off responsive to the signal, wherein the write replica circuit comprises: an additional column comprising a dual port dummy memory cell comprising a first port having first and second bitlines and a second port having first and second bitlines; wherein writes to the dual port dummy memory cell are performed on the first port and alternate between the first and the second bitlines of the first port on consecutive cycles; and write detection circuitry coupled to the dual port dummy memory cell and configured to detect when data has been written to the dual port dummy memory cell on either of the first or the second bitlines of the second port and responsively generate the signal.