Patent ID: 7701256

Claim:
A signal conditioning circuit for a latching comparator, the circuit comprising first and second transistors in which the first and second transistors are field effect transistors each having a drain, a source and a gate, and the sources of the first and second transistors are connected to one of a current source and a current sink, and the drain of each of the first and second transistors is connected, either directly or via at least one cascode device, to an active load, and to a first or second output node, respectively, and the active loads comprise respective third and fourth transistors, the third transistor being in series connection between the first output node and a common node, and the fourth transistor being in series connection between the second output node and the common node, and the third and fourth transistors are in a diode connected configuration and a further transistor is arranged to be operable to provide a low impedance path between the first and second output nodes, and the signal conditioning circuit is configured to act as an integrator, and where a rate of change of voltage at the output nodes in response to a fixed voltage difference between the gates of the first and second transistors is substantially constant from when the further transistor is opened until a latching comparator responsive to the signal conditioning circuit is strobed.