Patent ID: 8105900

Claim:
A manufacturing method of a non-volatile memory, comprising the steps of: providing a substrate; forming a plurality of strip-shaped isolation structures in the substrate to define a plurality of active regions in parallel with the isolation structures and both extended in a first direction, wherein the adjacent active regions are separated from each other by one of the isolation structures; forming a first memory array on the substrate, the first memory array comprising: a plurality of memory cell columns, each of the memory cell columns comprising: a plurality of memory cells connected in series with one another and disposed on the substrate in the active regions; a source/drain region, disposed in the substrate and outside the memory cells; and a plurality of select transistors disposed between the source/drain region and the memory cells to connect the memory cells to the source/drain region in series; a plurality of control gate lines extending across the memory cell columns and extended in a second direction intersecting the first direction, the control gate lines respectively connecting the memory cells in the second direction in series; and a plurality of first select gate lines extending across the active regions and respectively connecting the select transistors in the second direction in series; and forming a plurality of first contacts on the substrate at a side of the first memory array, the first contacts being arranged along the second direction and each of the first contacts extending across one of the isolation structures and connecting the source/drain regions in every two of the adjacent active regions in the substrate.