Patent ID: 7133317

Claim:
A programming method for first and second memory cells each having a body, a first current terminal and a second current terminal in the body, a gate terminal, a top dielectric, a charge trapping structure having parts corresponding to the first and second current terminals, and a bottom dielectric, wherein the gates of the first and second memory cells are coupled to a same word line, the first current terminals of the first and second memory cells are coupled to a same bit line, and the second current terminals of the first and second memory cells are coupled to different bit lines, the method comprising: in response to a program command to add charge to the charge trapping structure of at least the first and second memory cells: applying a first voltage to the same word line sufficient to move energetic charge from the body of memory cells across the bottom dielectric into the charge trapping structure; applying a second voltage to the same bit line to induce the energetic charge in the body of memory cells having at least a sufficient voltage difference between the first current terminal and the second current terminal; and applying a voltage setting to the different bit lines to cause at least the sufficient voltage difference between the first current terminal and the second current terminal to induce the energetic charge in the bodies of the first and second memory cells.