Patent ID: 8759203

Claim:
A method of forming an integrated circuit structure, the method comprising: forming an insulation layer over at least a portion of a substrate, wherein the insulation layer comprises a plurality of portions separated from each other by a plurality of regions that are level with the plurality of portions of the insulation layer; forming a plurality of semiconductor pillars higher than a top surface of the insulation layer, wherein each of the plurality of semiconductor pillars overlaps one of the plurality of regions, wherein the plurality of semiconductor pillars is allocated in a periodic pattern, and wherein the step of forming the plurality of semiconductor pillars comprises: forming recesses in the insulation layer, wherein the recesses are in the plurality of regions; epitaxially growing semiconductor re-growth regions in the recesses; performing a planarization to remove excess portions of the semiconductor re-growth regions; and lowering the top surface of the insulation layer to a level lower than top surfaces of the semiconductor re-growth regions; and epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.