Patent ID: 7839313

Claim:
An apparatus comprising: a clock signal generator, for generating a plurality, M, of clock signals at a frequency f and a period T; each of the M clock signals having a different one of a selected plurality, M, of clock phases a plurality, M, of Analog to Digital Converters (ADCs) coupled to the clock signal generator, the ADCs for converting an input signal to a set of ADC outputs as M digital values in response to a respective one of the M clock signals, each of the ADCs having an offset correction input, a gain correction input, and a phase correction input; an adaptive processor, coupled to receive the M digital values, the adaptive processor estimating one or more correction signals for at least one of offset, gain, and phase error in at least one of the MADCs, the adaptive processor determining the correction signals by: determining M accumulated values, X k , for k=1 to M, by individual accumulation of the M digital values over a predetermined number of ADC output samples; determining a reference value, X mean , from a combination of the M accumulated values; providing an adjusted set of set of digital values, E offset k, for k=1 to M, from the M accumulated values, X k , and the reference value X mean ; from the adjusted set of digital values, determining at least one of an offset, gain and phase correction value corresponding to one or more estimated correction signals to be applied to correct at least one of offset, gain, and phase error of at least one of the ADCs; the estimated correction signals connected to at least one of the offset, gain, and/or correction inputs of the ADCs; and a multiplexer, for interleaving the M digital values output by the ADCs to form a digital representation of the input signal.