Patent ID: 8493788

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells which are arranged at intersections between a plurality of bit lines and a plurality of word lines; a column decoder configured to apply a program voltage to the memory cells via the bit lines; and a control circuit configured to control the memory cell array and the column decoder, wherein the control circuit is configured to load program data from outside; to execute a first data program in a first even-numbered bit line; to execute a second data program in a first odd-numbered bit line; to execute a verify read of the programmed bit lines; to determine whether a value of the verify read is programmed up to a predetermined threshold value; and to change, in a case where the value of the verify read fails to be programmed to the predetermined threshold value, an order of the first and second data programs, to execute the second data program in the first odd-numbered bit line, and then to execute the first data program in the first even-numbered bit line.