Patent ID: 7554470

Claim:
A pipeline analog-to-digital converter (ADC), comprising: a pipeline converting circuit including a plurality of one-bit stages, the pipeline converting circuit being configured to convert an analog input signal into a first digital signal having a plurality of bits; and a digital calibrating circuit configured to extract calibration coefficients for the one-bit stages, and configured to calibrate a feedback signal based on the calibration coefficients and the first digital signal to generate a second digital signal having a plurality of bits, wherein the digital calibrating circuit comprises: a basic digital calibrating circuit configured to perform a basic calibration on the first digital signal to generate a third digital signal; a calibration control circuit configured to generate a reference clock signal, a first calibration control signal having a plurality of bits, and a second calibration control signal having a plurality of bits in response to a first clock signal and a first flag signal; a calibration-coefficient extracting circuit configured to extract a plurality of first calibration coefficients for the first digital signal in response to the reference clock signal, the first calibration control signal, the second calibration control signal and the feedback signal; a calibration output circuit configured to generate a second calibration coefficient having a plurality of bits based on each bit of the first digital signal and the first calibration coefficients; and an adder configured to perform an add operation on the third digital signal and the second calibration coefficient to generate the second digital signal.