Patent ID: 7042250

Claim:
A synchronizer circuit synchronizing an input clock signal with a sampling clock signal to generate a synchronized signal, said synchronizer comprises: a sampling module sampling a logical value received on a first node at time points specified by one of a first edge type and a second edge type of said sampling clock signal and providing corresponding sampled values as said synchronized signal; and an adaptive module generating said logical value at said first node, said adaptive module comprising: a first circuit inverting a logic value present on a second node and providing an inverted logic value on said second node upon an occurrence of a first edge type in said input clock signal after a first logical level on said first node is provided as said synchronized signal; a second circuit inverting a logic value present on a third node and providing an inverted logic value on said third node upon an occurrence of a second edge type in said input clock signal after a second logical level on said first node is provided as said synchronized signal; and a XOR gate generating said logical value at said first node by performing an XOR operation of bits received on said second node and said third node respectively.