Patent ID: 7085915

Claim:
A method for implementing prefetching of instructions for a processor executing a non-procedural program, said method comprising: prefetching instructions into a cache from memory which are sequential instructions from where the processor is currently executing in a sequence of instructions of said non-procedural program; and wherein when said prefetching encounters an update prefetch stream instruction, said prefetching comprises executing said update prefetch stream instruction to load a block of address pairs into a set associative array of x,y address pairs in a prefetch buffer associated with prefetch logic performing the prefetching, the block of address pairs comprising multiple x,y address pairs, and subsequent thereto, changing a current prefetch address to a new memory prefetch address for prefetching of at least one non-sequential instruction from memory for loading into the cache, said changing comprising comparing a current prefetch address with each x address of the set of associative array of x,y address pairs, and if a match is found, changing to a new memory prefetch address y paired with the matching x address.