Patent ID: 7050920

Claim:
A method for testing a semiconductor device including first and second power source lines, a plurality of output circuits, and a plurality of output terminals each disposed for one of said output circuits, each of said output circuits including a combination of first and second transistors connected together in series via a first node and between said first power source line and said second power source line, said first node being connected to a corresponding one of said output terminals, said method comprising: controlling said output circuits to turn ON said first and second transistors of a first output circuit among said plurality of output circuits, to turn ON one of said first transistor and said second transistor of a second output circuit among said plurality of output circuits, and to turn OFF another of said first transistor and said second transistor of said second output circuit; measuring a potential difference between said output terminal of said first output circuit and said output terminal of said second output circuit and a penetrating current flowing through said first and second transistors of said first output circuit; and calculating a characteristic of one of said first transistor and said second transistor of said first output circuit, based on said potential difference and said penetrating current and which of said first transistor and said second transistor of said second output circuit is ON.