Patent ID: 8618495

Claim:
A circuit for pulse pile-up rejection, comprising: a sensor configured to output a signal; a charge amplifier configured to receive the signal, amplify the signal and output the amplified signal; a filter configured to receive the amplified signal, filter the amplified signal, and output the filtered signal; a discriminator configured to receive a threshold, receive the filtered signal, and output a threshold-crossing time value if the filtered signal exceeds the threshold; a time-to-amplitude converter configured to receive the threshold-crossing time value, receive a trim value, and output an adjustable value, wherein the adjustable value is provided according to a delay value and the threshold-crossing time value, and the delay value is provided according to the trim value; comparison logic configured to receive a peak-occurrence time value of the filtered signal, receive the adjustable value, compare the peak-occurrence time value with the adjustable value, and output a reset signal if the peak-occurrence time value is greater than the adjustable value; and a peak detector configured to receive the filtered signal, measure a pulse amplitude of the filtered signal, determine the peak-occurrence time value of the filtered signal, output the peak-occurrence time value of the filtered signal, output the pulse amplitude if no reset signal is received, and perform pulse rejection if a reset signal is received.