Patent ID: 7834459

Claim:
A semiconductor device comprising: at least first, second and third interconnection layers sequentially stacked without intervention of a via layer, wherein the second interconnection layer includes one or more second interconnections and includes a via, the via connecting first and third interconnections respectively provided in the first and third interconnection layers underlying and overlying the second interconnection layer; the second interconnection layer includes an insulation film into which the one or more second interconnections penetrate; and the via penetrates the insulation film without connecting with the one or more second interconnections; the insulation film has a via hole and interconnection grooves formed therein, the via including a conductor filled in the via hole, the second interconnections including conductors filled in the interconnection grooves; the via hole has a diameter; and the interconnection grooves each have a width and a length that are greater than the diameter of the via hole.