Patent ID: 7613956

Claim:
A microcomputer comprising: a CPU which sequentially executes a program; an internal memory connected to said CPU via an internal bus; a debug support unit, which monitors an internal state in response to an externally provided command; a monitor memory, which stores data stored in said internal memory, for being accessed by said debug support unit; and a monitor memory control unit, connected to said internal bus, which at a concurrent copy mode performs a control to connect the internal bus to the monitor memory and concurrently write, to said monitor memory, data which is written to said internal memory in response to an access from said CPU, and which at a monitor mode performs a control to connect the debug support unit to the monitor memory, wherein at the monitor mode, said CPU continues to access the internal memory via the internal bus, while the monitor memory control unit performs a control to read data in said monitor memory and transfers the read data to said debug support unit.