Patent ID: 7584330

Claim:
A method for maintaining coherent data in a multiprocessor system having a plurality of processors coupled to a memory segment, where each processor has a private cache, the method comprising: tracking data entering and exiting a first processor so as to derive a status of the data in a private cache associated with the first processor; storing the status in an external tag memory associated with the first processor, the external tag memory non-hardwired to the private cache associated with the first processor; receiving a data request from a second processor, the data request requesting data associated with a memory location in the memory segment; determining if the tag memory associated with the first processor indicates that the requested data is held within the private cache associated with the first processor; snooping the first processor if the tag memory associated with the first processor indicates that the requested data is held within the private cache associated with the first processor; re-posting the data request if the private cache associated with the first processor indicates it no longer holds the requested data, and setting the tag status for the requested data so as to indicate that the private cache associated with the first processor no longer holds the requested data; storing data evicted by the first processor in an external cache associated with the first processor; storing the status of data evicted by the first processor in the external tag memory associated with the first processor; posting a transaction of the requested data from the external cache if the status indicates that the first processor has evicted the requested data, that the requested data was modified, and that the first processor has not re-requested the data; and posting a transaction of the requested data from the external cache if the status indicates that the first processor has evicted the requested data and that the requested data was not modified.