Patent ID: 7954080

Claim:
A wafer comprising: at least one die comprising a plurality of devices; and at least one test structure for de-embedding at least one of the plurality of devices, wherein the at least one test structure further comprises: a first dummy component comprising a first transmission line; a second dummy component comprising a second transmission line, wherein the second dummy component is coupled with the first dummy component and the second transmission line is co-linear with the first transmission line; and at least one test pad electrically connected to an end of the first transmission line and at least one test pad electrically connected to an end of the second transmission line, the at least one test pad electrically connected to the end of the first transmission line being adjacent to the at least one test pad electrically connected to the end of the second transmission line, wherein the first transmission line is positioned only within the first dummy component and the second transmission line is positioned only within the second dummy component.