Patent ID: 8592892

Claim:
A nonvolatile semiconductor memory device comprising a memory element, the memory element including: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a tunnel insulating film formed on a region in the semiconductor layer located between the source region and the drain region, and having a stack structure formed with a first insulating layer, a second insulating layer, and a third insulating layer in this order, the first insulating layer including an electron trapping site, the second insulating layer not including the electron trapping site, the third insulating layer including the electron trapping site, and the electron trapping site being located in a position lower than a conduction band minimum of the first through third insulating layers while being located in a position higher than the conduction band minimum of a material forming the semiconductor layer, the conduction band minimum of the tunnel insulating film being constant in a film thickness direction across the first, second, and third insulating layers; a charge storage film formed on the tunnel insulating film; an insulating film formed on the charge storage film; and a control gate electrode formed on the insulating film.