Patent ID: RE41670

Claim:
An integrated circuit SRAM cell, comprising: a substrate which includes at least one substantially monolithic body of semiconductor material; a first patterned thin-film layer comprising polysilicon; a second patterned thin-film layer comprising polysilicon and overlying said first thin-film layer, said second layer being doped to provide high conductivity; a patterned interlevel dielectric overlying portions of said first and second thin-film layers, said interlevel dielectric including multiple independently planarized layers of dielectric material therein, said multiple independently planarized layers including a lower portion of a spin-on glass a middle portion of a dielectric material which is not spin-on glass, and an upper portion of spin-on glass; a third patterned thin-film layer comprising substantially undoped polysilicon having a very high resistivity; wherein said first patterned thin-film layer is configured to provide transistor gates, and said first and second thin-film layers are interconnected to provide an array of latches, and said third thin-film layer overlies said patterned interlevel dielectric and is interconnected through contact holes with said first and second layers to provide resistive loads for each said latch.