Patent ID: 8895368

Claim:
A method for manufacturing a chip package structure, the method comprising: providing a carrier, the carrier having a metal layer; forming a patterned photoresist layer on the metal layer, the patterned photoresist layer having a plurality of first openings exposing a portion of the metal layer; forming a plurality of connection terminals in the first openings, respectively, the connection terminals being connected to the metal layer; placing a chip on the carrier and connecting a plurality of first pads of the chip to the connection terminals through a plurality of connection conductors; removing the patterned photoresist layer after the chip is placed on the carrier; forming a encapsulant on the carrier, the encapsulant encapsulating the chip, the connection conductors, and the metal layer; removing the carrier and the metal layer to expose the connection terminals; and forming a redistribution layer after removing the metal layer, wherein the redistribution layer covers a portion of the encapsulant and is electrically connected to the connection terminals.