Patent ID: 7459790

Claim:
A chip structure comprising: a silicon substrate; a first repeater in and on said silicon substrate; a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first interconnecting structure connected to said first repeater, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric body over said silicon substrate, wherein said first interconnecting structure is in said dielectric body, and wherein said dielectric body comprises a dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said dielectric body, wherein said passivation layer comprises a nitride layer; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; and a second metallization structure over said passivation layer and over said first via, wherein said second metallization structure is connected to said first repeater through, in sequence, said first via and said first interconnecting structure.