Patent ID: 8302051

Claim:
A parasitic element extracting system comprising: a classifying section configured to classify each of interconnection layers of a layout structure of a semiconductor device into one of an upper interconnection layer and an lower interconnection layer based on a predetermined criterion; a marker producing section configured to generate a marker to indicate a via-contact connecting said upper interconnection layers and said lower interconnection layers; an upper layer parasitic element list producing section configured to generate an upper layer parasitic element list by extracting parasitic elements in said upper interconnection layers based on a first criterion; a lower layer parasitic element list producing section configured to generate a lower layer parasitic element list by extracting parasitic elements in said lower interconnection layers based on a second criterion which is different from said first criterion; and a parasitic element list producing section configured to generate a parasitic element list of said layout by combining said upper layer parasitic element list and said lower layer parasitic element list by using said marker.