Patent ID: 6839863

Claim:
An input data processing circuit adapted to receive input data sets from first and second upper circuits that are asynchronous with each other and that generate first and second clocks, respectively, said input data processing circuit comprising: a first FIFO buffer adapted to receive and temporally store input data sets from the first upper circuit in compliance with the first clock; a first counter adapted to count the number of edges of the first clock, so as to generate a first completion signal and to restart the counting every time the number of edges of the first clock is equal to a predetermined number; a second FIFO buffer adapted to receive and temporally store input data sets from the second upper circuit in compliance with the second clock; a second counter adapted to count the number of edges of the second clock, so as to generate a second completion signal and to restart the counting every time the number of edges of the second clock is equal to the predetermined number; a phase detector adapted to detect a clock phase difference between the first and second clocks on the basis of the first and second completion signals; and a readout circuitry adapted to select one of the first and second FIFO buffers if the clock phase difference is greater than a predetermined time corresponding to a half of data length of the predetermined number of the input data sets, the selected FIFO buffer having a faster clock by the clock phase difference than another clock between the first and second clocks, so as to read out of the selected FIFO buffer the predetermined number of the input data sets.