Patent ID: 8051222

Claim:
A packet processor for accepting consecutively received original packets from a first interface and transferring them to a second interface using a superframe, said second interface having an interrupt, the packet processor having: a memory coupled to a processor and DMA engine; a timer which is initialized upon start of a superframe; whereby for each incoming packet, said packet is transferred from said first interface to said memory by either said DMA engine or said processor, and where a packet descriptor for said packet is created, said packet descriptor having, in sequence: a first value set to the number of packets in the superframe; a first part comprising: a consecutive sequence of length values, each of said length values corresponding to the length of an original packet of said consecutively received original packets, each said consecutively received original packets having an original packet header and an original packet payload which is unmodified from said first interface original packet; a second part comprising said unmodified original packets concatenated into a contiguous block, the number of said unmodified original packets corresponding to said first value and the length and order of each said unmodified original packet corresponding to said first part sequence of length values; such that when either said superframe timer expires, the number of packets in said superframe exceeds a threshold, or the size of said superframe exceeds a threshold, said interrupt is asserted and said superframe is transferred to said second interface during a single transfer event.