Patent ID: 8895432

Claim:
A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM, comprising: a) blanket depositing an inorganic hard masking material which serves as both an electrical insulator and a barrier layer over a silicon substrate surface; b) patterning said inorganic hard masking material in a manner which permits etching of feature sizes in the range from 5 nm to 16 nm; c) pattern etching a plurality of trenches into said silicon substrate; d) filling said trenches with a dielectric material; e) planarizing an upper surface of filled trenches, stopping on an upper surface of said hard masking material; f) etching said dielectric material present within said trenches, to leave a dielectric layer having a controlled thickness at a bottom of each trench; g) depositing a protective hard masking material layer on surfaces of a structure created in step f); followed by h) anisotropically etching said protective hard masking material layer to remove the portion of said layer present at the bottom of said trenches; i) isotropically etching additional dielectric material off the upper surface of the dielectric material at the bottom of said trenches, and simultaneously a side wall surface of silicon columns present between said trenches, to create a gap of exposed silicon surface on said silicon column sidewalls, between the bottom edge of said hard masking material and the upper surface of said dielectric layer at a bottom of said trenches; j) inserting a dopant into said exposed silicon surfaces; k) rapid thermal annealing at a temperature ranging from about 950° C. to about 1,000° C.; l) cleaning residual off the exposed silicon surfaces and adjacent surfaces; m) applying a metal layer selected from the group consisting of Co, Pt, Ni—Pt, Ti, Er, and combinations thereof, over said exposed silicon surfaces using CVD or ALD; n) applying a metal-comprising barrier layer over said metal layer using ALD; o) forming a metal silicide using at least one rapid thermal annealing of said metal layer at a temperature ranging from about 300° C. to about 850° C.; and p) stripping of residual metal-comprising materials from said metal silicide and other adjacent surfaces.