Patent ID: 8605777

Claim:
A circuit for recognizing a beginning and a data rate of data, the circuit comprising: at least two data rate detecting circuits for comparing at least two alignment patterns corresponding to different data rates with data simultaneously to recognize the data rate of the data; and a post processing circuit coupled to the at least two data rate detecting circuits for recognizing the beginning of the data according to an alignment pattern corresponding to the data when the data rate of the data is recognized; wherein when the at least two data rate detecting circuits does not recognize the data rate is a first data rate or a second data rate within a predetermined time, the at least two data rate detecting circuits detects whether the data rate is a third data rate and a fourth data rate; wherein the first data rate and the second data rate are two adjacent rates of a data rate specification between a host and a device, and the third data rate and the fourth data rate are another two adjacent rates of the data rate specification.