Patent ID: 8726132

Claim:
A system configured to validate a data packet protected by a data packet checksum in a network processor supporting a first network protocol and a second network protocol utilizing shared hardware for packets for either network protocol comprising: a network processor; a parser running on the network processor; the parser configured to receive a data packet in a stream of data packets; the parser configured to determine a network packet protocol for the data packet; a first logic block with a first register for holding a first partial packet length; a second logic block with a second register for holding a second partial packet length; a third logic block with a third register for holding a first checksum computed from fields common to either network protocol; the parser configured such that responsive to the parser identifying the network packet protocol as the first network protocol, to send a first set of fields extracted from the packet for adjusting length found in the first network protocol and not in the second network protocol and the first logic block configured to update the first register with a first partial packet length; the parser configured such that responsive to the parser identifying the network packet protocol as the second network protocol, to send a second set of fields extracted from the packet for adjusting length found in the second network protocol and not the first network protocol to a second logic block configured to update the second register with a second partial packet length; the parser configured to send a third set of fields independent of the network protocol to a third logic block configured to update the third register with a first checksum; a function configured to produce a second checksum by combining values from the first register, the second register, and the third register; and the system configured to validate the data packet by comparing the data packet checksum to the second checksum.