Patent ID: 8405139

Claim:
A semiconductor device comprising: a semiconductor layer; a first memory transistor; and a peripheral circuit transistor, wherein the first memory transistor comprises: a first insulating film formed on the semiconductor layer in a memory cell region; a first electrode layer formed on the first insulating film; a first element isolating insulator formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, a top face of the first element isolating insulator being lower than a top face of the first electrode layer; a second insulating film formed on the first electrode layer and the first element isolating insulator; and a second electrode layer formed on the second insulating film; and the peripheral circuit transistor comprises: a third insulating film formed on the semiconductor layer in a peripheral circuit region; a third electrode layer formed on the third insulating film; a second element isolating insulator formed to extend through the third electrode layer and the third insulating film to reach an inner region of the semiconductor layer; a fourth insulating film formed on the third electrode layer, the fourth insulating film including a first open portion exposing a surface of the third electrode layer; and a fourth electrode layer formed above the fourth insulating film and on the exposed surface of the third electrode layer, the fourth electrode layer being electrically connected to the third electrode layer via the first open portion, wherein a height between a surface of the semiconductor layer beneth the first insulating film and the top face of the first element isolating insulator is shorter than a height between the surface of the semiconductor layer beneath the third insulating film and a top face of the second element isolating insulator.