Patent ID: 7203198

Claim:
An asynchronous transfer mode switch, comprising: a plurality of input/output ports for receiving and transmitting ATM cells; a cell header filter for decoding ATM cell headers to determine each cell's ATM channel; at least one processor for manipulating each ATM cell in response to the ATM channel identified by the cell header filter and outputting each of the manipulated ATM cells on one of the input/output ports; and at least one memory structure associated with the at least one processor for storing ATM cell data prior to transmission on one of the input/output ports, wherein each available ATM channel is represented by a flow data structure in the at least one memory structure, the flow data structure including a plurality of state variables associated with the ATM channel and further including memory addresses for a cell reception handler routine and a cell transmission handler routine, wherein the plurality of state variables include at least one variable selected from the group consisting of the following information: static parameters such as the ATM channel's output port, priority and cell header rewriting rules, a memory address to a queue of buffered cells awaiting transmission; the ATM channel's early packet discard/partial packet discard state, and channel statistics such as a count of cells passing through the channel.