Patent ID: 8765559

Claim:
A method of forming a semiconductor device, the method comprising: forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, said first and second gate electrode structures comprising a dielectric cap layer; forming a protective spacer commonly on sidewalls of said first and second gate electrode structures; forming a strain-inducing semiconductor material in said first active region in the presence of said first gate electrode structure while covering said second active region and said second gate electrode structure; after forming said strain-inducing semiconductor material, forming drain and source extension regions in at least said second active region; forming an etch stop layer above said first and second active regions after forming said strain-inducing semiconductor material; forming a fill material above said first and second active regions so as to laterally enclose said first and second gate electrode structures and expose said dielectric cap layers; removing said dielectric cap layers; and forming drain and source regions in said first and second active regions.