Patent ID: 7564392

Claim:
A decoder circuit having a plurality of grayscale voltage input terminals for receiving respective grayscale voltages, a plurality of digital signal input terminals receiving respective bit signals, and an output terminal, comprising: a first selection circuit having a plurality of metal-oxide-semiconductor transistors of a first channel type, each having a gate to which one of the bit signals is applied, and a source to which one of the grayscale voltages is applied; and a second selection circuit having a plurality of metal-oxide-semiconductor transistors of a second channel type each having a gate to which one of the bit signals is applied, and a source to which one of the grayscale voltages is applied, wherein the gray scale voltages include positive grayscale voltages higher than a common voltage, and negative grayscale voltages lower than the common voltage; and the grayscale voltages applied to the first selection circuit and the grayscale voltages applied to the second selection circuit are of the same polarity.