Patent ID: 7644252

Claim:
A multiprocessor system comprising: a plurality of microprocessors configured to operate a plurality of operating systems, respectively; a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors; a user defined configuration management table, whereby the plurality of memory spaces are respectively allocated to the plurality of microprocessors by a user; and wherein each of the plurality of microprocessors further comprise: a translation look-aside buffer (TLB) configured to store a copy of at least a part of data stored in the allocated memory spaces corresponding to the TLB, the copy including a relation of virtual addresses of a virtual address space to corresponding physical address in the memory space; and a page table register configured to refer to the TLB in response to an execution virtual address, generated based on an application program executed by the microprocessor, to determine an execution physical address corresponding to the execution virtual address, and when the TLB contains an execution physical address corresponding to the execution virtual address, the microprocessor accesses the memory space based on the execution physical address corresponding to the execution virtual address; and when said TLB does not contain an execution physical address corresponding to the execution virtual address, the microprocessor refers directly to a page table in the associated memory space, the page table being configured to store the relation of execution virtual addresses to the execution physical addresses; and the microprocessor accesses the memory space based on the execution physical address related to the execution virtual address in the page table.