Patent ID: RE39799

Claim:
A memory cell array, comprising: a substrate having a main face; a first insulating layer configured on said main face of said substrate, said first insulating layer formed with a trench having a bottom and edges; a first line configured in said trench of said first insulation layer; a second line; a memory element configured at a point of intersection between said first line and said second line, said memory element being switched between said first line and said second line; a first yoke disposed adjacent said bottom and said edges of said trench of said first insulation layer, said first yoke configured such that a magnetic flux through said first yoke is essentially closed in said memory element, said first yoke including a magetizable magnetizable material with a relative permeability of at least 10; and a line selected from the group consisting of said first line and said second line being supplied with current during a write access and being partially surrounded by said first yoke.