Patent ID: 8176221

Claim:
A DMA controller comprising: a counter configured to measure a time period; a counter comparator coupled to receive an output of said counter; a peripheral device read unit, coupled to receive an output of said counter comparator and coupled to a plurality of peripheral devices, configured to read states of the plurality of peripheral devices to acquire the states of the plurality of peripheral devices; a state comparator coupled to receive an output of said peripheral device read unit; a transfer unit coupled to receive an output of said state comparator and configured to execute a DMA transfer; and a register configured to store contents to operate the counter, the counter comparator, the peripheral device read unit, the state comparator, and the transfer unit to execute the DMA transfer, wherein, the counter comparator is configured to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations based upon the time period measured by the counter and the contents set in the register, wherein, at said timing, the peripheral device read unit is configured to read the states of the plurality of peripheral devices based upon the contents set in the register, and the state comparator is configured to determine whether to start the DMA transfer by the transfer unit based upon the states of the plurality of peripheral devices and a start condition of the DMA transfer set in the register, and wherein, when the state comparator determines to start the DMA transfer, the transfer unit is configured to execute data transfer between the peripheral devices.