Patent ID: 8117403

Claim:
A multithreaded microprocessor comprising: a microprocessor forming a Central Electric Complex (CEC) of a computer system having a plurality of cores each having a hardware transactional memory for supporting a plurality of hardware threads for supporting hardware transactional memory operations and for detecting conflicts between storage accesses of transactions running on multiple threads of execution in a multithreaded operation, as well as for supporting normal operations with instruction execution pipelines, said computing system having an operation control means for transforming the computer system to use assist thread operations by initializing one or more assist threads in said multithreaded operation and preparing the computing system for the execution of transactions using a storage element for storing an address history table (AHT) to the hardware register file of the multithreaded microprocessor having entries for a storage access written in a hardware register array for said AHT by load store units of said microprocessor, said computer system having a plurality of interfaces for command and control information written into the AHT from said instruction execution pipelines and having a general purpose register coupled to at least one assist thread interface that carries command, control, address and data information for copying and moving entries in said AHT to parallelize the execution of a transaction of the transaction data of a first thread to allow the first thread of execution to continue to a next instruction while utilizing a data buffer for communication between the first thread of execution and all assist threads; wherein an AHT entry contains an “Entry Type” field, an Access Type field, an “Address” field, a “Thread ID” field, and a “Response” field, and wherein Entry Type fields of AHT entries contain specialized commands and Address Record entries, and the Access Type field will contain an indication of whether the address was from a store type access or a load type access, the “Address” field contains the real address of the storage access, the “Thread ID” field indicates the thread of execution that is processing an AIG and which caused the entry in the AHT to be created, and the “Response” field is used to associate hardware responses to AHT entries where responses may indicate that steps required during the processing of addresses stored in the AHT have been completed.