Patent ID: 7135401

Claim:
A method of forming an electrical connection for a semiconductor construction, comprising: providing a semiconductor substrate having a conductive line thereover and having one or more diffusion regions therein and adjacent the conductive line, the line extending along a first axis; forming a patterned layer over said one or more diffusion regions, the patterned layer having a plurality of openings extending therein, at least some of the openings being along a row extending along a second axis substantially parallel to the first axis and being directly over at least one of said one or more diffusion regions; forming an electrically insulative material over the patterned layer; exposing the electrically insulative material to an etch which forms a trench extending through the electrically insulative material to the patterned layer, to two or more of the plurality of openings, and which extends at least some of the openings along said row toward the at least one of said one or more diffusion regions, the etch being selective for removing the electrically insulative material relative to the patterned layer, at least a portion of the trench being directly over the openings and extending along the second axis; and forming an electrically conductive material within the openings and within the trench, the electrically conductive material being in electrical connection with the at least one of said one or more diffusion regions.