Patent ID: 7060565

Claim:
A method for fabricating an integrated circuit comprising a nonvolatile memory cell comprising a first conductive gate and two conductive floating gates, wherein the floating gates overlie a channel region of the memory cell, wherein the channel region is part of a semiconductor region having a top surface, and each floating gate overlies a respective first surface portion of the top surface of said semiconductor region, each first surface portion being defined as an entire surface portion lying under the respective floating gate, the method comprising: (1) providing a first gate surface which is a surface of the first conductive gate; (2) forming a first dielectric on the first gate surface and a second dielectric on the entire first surface portions, the entire first surface portions having a first conductivity type, wherein at least a portion of the first dielectric and at least a portion of the second dielectric are formed simultaneously; and (3) forming the floating gates on the second dielectric; wherein the first dielectric is used to insulate the first gate from the floating gates and/or from another element of the integrated circuit; wherein the first gate is a select gate; the method further comprising forming two control gates for the memory cell, the control gates being insulated from the select gate by the first dielectric; wherein the floating gates are adjacent to respective first portions of the first gate and the control gates are adjacent to respective second portions of the first gate, the second portions having positive lengths in a vertical cross section.