Patent ID: 7863746

Claim:
A semiconductor device, comprising: a semiconductor substrate; an integrated circuit on the semiconductor substrate, the integrated circuit including a logic device having: an N-channel MOS transistor having an N-type source region and an N-type drain region formed in the semiconductor substrate; and a P-channel MOS transistor having a P-type source region and a P-type drain region formed in the semiconductor substrate; an insulation layer covering the integrated circuit; and a plurality of metal line patterns on the insulating layer, wherein: first and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit, at least one of the first and second metal line patterns is a ground line or a power supply line, and the first metal line pattern is electrically connected to the N-type source region of the N-channel MOS transistor, and the second metal line pattern is electrically connected to the P-type source region of the P-channel MOS transistor.