Patent ID: 7872355

Claim:
A semiconductor integrated circuit comprising: a power pad disposed on a chip; and a circuit group connected to said power pad through a power wiring structure, wherein said power wiring structure includes: a plurality of first power wirings and a plurality of second power wirings that are disposed in different wiring layers and overlap with each other at a plurality of intersections; and vias connecting said plurality of first power wirings and said plurality of second power wirings, wherein said circuit group includes a first functional block placed on a first region, and said vias are not placed at a part of said plurality of intersections within a second region located between said first region and said power pad, wherein said power pad is disposed at a periphery of said chip, wherein said plurality of first power wirings are disposed along a first direction, said plurality of second power wirings are disposed along a second direction orthogonal to said first direction, and said chip has a zonal region extending from an edge of said first region to a side of said chip along said first direction or said second direction, and wherein said vias are not placed at a part of said plurality of intersections within said zonal region.