Patent ID: 7356106

Claim:
A clock and data recovery circuit for recovering a clock signal from a non-return to zero data signal and re-timing the data signal, the clock and data recovery circuit comprising: a phase detector for receiving the non-return to zero data signal and detecting phase difference between the non-return to zero data signal and a first reference phase signal for providing a phase detector output signal; a quadrature phase detector for receiving the non-return to zero data signal and detecting phase difference between the non-return to zero data signal and a second reference phase signal for providing a quadrature phase detector output signal; a frequency detector coupled to the phase detector and the quadrature phase detector for detecting frequency difference between the phase detector output signal and the quadrature phase detector output signal for providing a frequency detector output signal; a summer coupled to the phase detector and the frequency detector for summing the phase detector output signal and the frequency detector output signal for providing a summer output signal; a voltage-controlled oscillator for receiving a direct current signal and providing a recovered clock signal; a polyphase filter coupled respectively to the voltage-controlled oscillator for receiving the clock signal therefrom, the phase detector for providing the first phase reference signal thereto, and the quadrature phase detector signal for providing the second reference phase signal thereto; and a re-timer for receiving the non-return to zero data signal and being coupled to the polyphase filter for receiving the first reference phase signal for providing a re-timed data signal, wherein the clock and data recovery circuit is on-chip and the polyphase filter converts the clock signal into the first reference phase signal and the second reference phase signal.