Patent ID: 7409659

Claim:
An apparatus comprising an integrated circuit comprising a digital circuit comprising: a first net; a second net, wherein the second net induces a crosstalk glitch in the first net; and a first static latch wherein the first static latch is connected to the first net, whereby crosstalk glitch in the first net is reduced, wherein the first static latch comprises: a first inverter having (i) an input node connected to the first net and (ii) an output node; a second inverter in series with the first inverter and having (iii) an input node connected to the output node of first inverter and (iv) an output node connected to the first net; and a third inverter comprising a first p-type transistor, a second p-type transistor, a first n-type transistor, and a second n-type transistor, wherein: the first p-type transistor is connected in series with the second p-type transistor to the output node of the first inverter and the input node of the second inverter; the first n-type transistor is connected in series with the second n-type transistor to the output node of the first inverter and the input node of the second inverter; gates of the first p-type transistor and the first n-type transistor are directly connected to the output node of the second inverter; and gates of the second p-type transistor and the second n-type transistor are directly connected to the input node of the first inverter.