Patent ID: 7087484

Claim:
A method for fabricating trench capacitors for memory cells having at least one selection transistor for integrated semiconductor memories, which comprises the steps of: providing a semiconductor substrate of a first conductivity type; producing a horizontal mask on the semiconductor substrate, the horizontal mask to be used for producing trenches; carrying out an anisotropic etching step after a completion of the horizontal mask, thereby producing upper trench regions in the semiconductor substrate; covering sidewalls of the upper trench regions with vertical masks; etching the semiconductor substrate selectively with respect to the horizontal mask and the vertical masks, for producing lower trench regions; doping surfaces of the lower trench regions with a material of a second conductivity type resulting in first electrodes being produced on surfaces of the lower trench regions; applying a dielectric to the first electrodes; removing the vertical masks; applying second electrodes to the dielectric resulting in the trench capacitors being formed in the lower trench regions; etching the semiconductor substrate in the upper trench regions after an application of the second electrodes; producing an insulator on a region etched in each of the upper trench regions; and producing electrically conductive connections each connecting a respective one of the second electrodes to a respective selection transistor.