Patent ID: 7376002

Claim:
A semiconductor memory device having a memory cell region in which a statistic memory cell is formed, comprising: a first inverter formed of a first driver transistor of a first conductive type and a first load transistor of a second conductive type; a second inverter formed of a second driver transistor of the first conductive type and a second load transistor of the second conductive type, wherein an output terminal of said first inverter and an input terminal of said second inverter being electrically connected to each other, thereby forming a first storage node, and an output terminal of said second inverter and an input terminal of said first inverter being electrically connected to each other, thereby forming a second storage node; a first access transistor of the first conductive type having the other conductive end electrically connected to said first storage node, a gate electrically connected to a word line for writing, and one conductive end electrically connected to a bit line for writing; a second access transistor of the first conductive type having one conductive end electrically connected to said second storage node and a gate electrically connected to the bit line for writing; a first transistor of the first conductive type having a gate electrically connected to the word line for writing, the other conductive end grounded, and one conductive end electrically connected to the other conductive end of said second access transistor; a second transistor of the first conductive type having a gate electrically connected to said second storage node and the other conductive end grounded; and a third transistor of the first conductive type having one conductive end electrically connected to a bit line for reading, a gate electrically connected to a word line for reading, and the other conductive end electrically connected to one conductive end of said second transistor; wherein said first access transistor, said second access transistor and said first transistor being disposed on one side of a region in which said first and second load transistors are formed, said second transistor and said third transistor being disposed on the other side of the region in which said first and second load transistors are formed, and gates of all of transistors disposed in said memory cell region extend in the same direction.