Patent ID: 7800936

Claim:
A memory comprising: an array of memory cells arranged in N rows of memory cells and M columns of memory cells; M write select lines coupling to corresponding columns of memory cells; N write data lines coupling to corresponding rows of memory cells; a write address decoder adapted to enable a selected one of the write select lines in response to a write address; and N gating circuits, each gating circuit adapted to selectively assert a data signal or an inhibit signal to a corresponding one of the write data lines in response to a corresponding write select signal; wherein each data signal has a value, and wherein at least one of the memory cells is adapted, when a corresponding write select line is enabled, to store the data signal value when the data signal is present on a corresponding write data line and to retain the data stored therein when the inhibit signal is present on the corresponding write data line, and wherein each of the write data lines comprises a pair of conductors, each gating circuit being adapted to assert one of two logic values on each conductor of the pair of conductors of a corresponding write data line to form logic value combinations thereon, the data signal on a write data line being at least one of a first group of the logic value combinations, and the inhibit signal on the write data line being at least one of a second group of the logic value combinations, the first group of the logic value combinations being different from the second group of the logic value combinations.