Patent ID: 7889007

Claim:
An integrated circuit comprising: a main circuit comprising: a first transistor electrically coupled to a first inductor to receive and amplify a first input of a differential input signal; a second transistor electrically coupled to the first transistor, the second transistor generating a first intermediate signal and providing a first output of a differential output signal; a third transistor electrically coupled to the second transistor and operative to receive the first intermediate signal and generate distortion components used to cancel a distortion component generated by the first transistor; a fourth transistor electrically coupled to a second inductor to receive and amplify a second input of the differential input signal; a fifth transistor electrically coupled to the fourth transistor, the fifth transistor generating a second intermediate signal and providing a second output of the differential output signal; and a sixth transistor electrically coupled to the fifth transistor and operative to receive the second intermediate signal and generate distortion components used to cancel a distortion component generated by the fourth transistor, wherein the gain of the first transistor, second transistor and third transistor combination and the fourth transistor, fifth transistor and sixth transistor combination is given substantially by: g 1 ⁢ Σ = g 1 · ( 1 - α β ) g 1Σ is the overall gain with distortion cancellation (1−α/β),α is the ratio of the transconductance of the first transistor to the transconductance of the second transistor and the ratio of the transconductance of the fourth transistor and the fifth transistor,β is the ratio of the transconductance of the first transistor and the third transistor and the ratio of the transconductance of the fourth transistor and the sixth transistor.