Patent ID: 8281106

Claim:
A processor, comprising: at least one execution unit that executes instructions of compiled program code, the compiled program code including the instructions and an operand data structure; at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit; an instruction sequencing unit that fetches instructions for execution by the at least one execution unit; data storage that buffers the operand data structure of the compiled program code, wherein the operand data structure describes a plurality of sequentially processed computation blocks of the compiled program code not executed by the at least one execution unit, wherein the operand data structure specifies for a first computation block among the plurality of computation blocks a first relationship between addresses of sequential accesses within a first address region and specifies for a second computation block among the plurality of computation blocks a different second relationship between addresses of sequential accesses within a second address region; and a programmable address generation accelerator programmed by the operand data structure of the compiled program code, wherein the address generation accelerator, for the first computation block, computes and outputs, for servicing by a memory hierarchy including at least one memory external to the processor, a first address of a first memory access in the first address region by reference to the first relationship specified by the operand data structure and that, for the second computation block, thereafter computes and outputs, for servicing by the memory hierarchy, a second address of a second memory access in the second address region by reference to the second relationship specified by the operand data structure.