Patent ID: 7633342

Claim:
An amplifier circuit with a linear adjustable gain, comprising: a first gain transistor including a gate end, a first end, and a second end; a second gain transistor including a gate end, a first end, and a second end; a current mirror circuit being capable of receiving a control current as an input and outputting a first reference current to the first gain transistor for controlling voltage difference between the gate end and the first end of the first gain transistor, the current mirror circuit further being capable of outputting a second reference current to the second gain transistor for controlling voltage difference between the gate end and the first end of the second gain transistor; a first cascode transistor including a first end and a second end, the first cascode transistor being capable of generating a first output current at the second end, the first cascode transistor being connected at the first end to the second end of the first gain transistor; and a second cascode transistor including a first end and a second end, the second cascode transistor being capable of generating a second output current at the second end, the second cascode transistor being connected at the first end to the second end of the second gain transistor; wherein the first output current and the second output current being in function of the control current according to the linear adjustable gain; wherein the current mirror circuit further comprises: a first mirror transistor including a gate end, a first end, and a second end; a second mirror transistor including a gate end, a first end, and a second end; and a third mirror transistor including a gate end, a first end, and a second end, wherein the gate end of the first mirror transistor being coupled to the gate end of the first gain transistor, the gate end of the second gain transistor, and the first end of the third mirror transistor. the second end of the first mirror transistor being coupled to the first end of the second mirror transistor, and the gate end of the third mirror transistor being coupled to the second end of the second mirror transistor.