Patent ID: 7634744

Claim:
A semiconductor memory device comprising: plural memory cell transistor pairs; plural metal lines supplied with a predetermined power supply potential; and plural memory cell read data lines, wherein: the memory cell transistor pairs are arranged in a row-column array, two memory cell transistors constituting each memory cell transistor pair of the plural memory cell transistor pairs share a common source diffusion region, and the source diffusion region of the two memory cell transistors constituting each memory cell transistor pair of the plural memory cell transistor pairs is separated from another source diffusion region of another two memory cell transistors constituting another memory cell transistor pair of the plural memory cell transistor pairs, the source diffusion regions of the memory cell transistor pairs in the same row are connected by one common metal line of the plural metal lines, a first metal wiring layer, which is a lowest layer, is used as the plural metal lines supplied with the predetermined power supply potential, and the plural memory cell read data lines are provided in such a manner that one of the memory cell read data lines is provided for each column of the array, and a second metal wiring layer or an even upper wiring layer is used as the plural memory cell read data lines.