Patent ID: 7698675

Claim:
A method of designing a semiconductor device, comprising: preparing, by a computer processor, a plurality of cells, each of the cells being configured by splitting a pattern layout of each cell into at least a first side region on a first side of each cell and a second side region on a second side of each cell and by further splitting each of the first and second side regions into first, second and third sub-regions, the first, second and third sub-regions being labeled by respective pin names; placing, by the computer processor, based on circuit information in which an output of a first cell is connected to an input of a second cell, the first cell and the second cell of the cells adjacently to each other such that the pin names of the first and third sub-regions of the second side region of the first cell are identical respectively to the pin names of the first and third sub-regions of the first side region of the second cell and the pin name of the second sub-region of the second side region of the first cell and the pin name of the second sub-region of the first side region of the second cell are respectively the output of the first cell and the input of the second cell; and sharing, by the computer processor, the first, second and third sub-regions of the second side region of the first cell respectively with the fist, second and third sub-regions of the first side region of the second cell.