Patent ID: 7902595

Claim:
A power IC device, comprising: a surface channel MOS transistor and a p-channel trench power MOS transistor formed in a single chip, the chip having a surface with a planar direction not less than −8° and not more than +8° off a silicon crystal (110) face, wherein: the p-channel trench power MOS transistor includes a rectangular parallelepiped trench formed vertically from the surface of the chip and substantially parallel to the crystal <100> direction of the chip so that at least two of side walls of the trench have a planar direction not less than −8° and not more than +8° off the silicon crystal (110) face, a gate region formed in the trench, a trench power MOS transistor inversion channel region formed on a side wall part of the trench, a source region provided in a surface layer of the chip above the trench power MOS transistor inversion channel region, the source region being insulated from the gate region by a gate insulating film, and a drain region provided in a back surface layer of the chip below the trench power MOS transistor inversion channel region; wherein the trench power MOS transistor inversion channel region is structurally configured such that a current from the source region to the drain region flows in a direction not less than −8° and not more than +8° off a silicon crystal <110> direction normal to the silicon crystal (110) face, and the surface channel MOS transistor includes a surface channel MOS transistor inversion channel region structurally configured so that an inversion channel current flows in a surface part of the chip parallel to the surface of the chip.