Patent ID: 7284218

Claim:
A method for inplace symbolic simulation of a multi-clock-domain design circuit over multiple cycles, the design comprising a plurality of clocks, the method comprising the steps of: a. determining a phase-list for each edge, the phase-list for an edge representing all the phases on which the signal value of the edge can change; b. determining a plurality of ticks associated with each edge of the circuit, the ticks associated with an edge representing all the active clock triggers associated with that edge for the multiple cycles of the clocks over which the circuit is being simulated; c. generating a plurality of slots associated with each edge, all slots associated with an edge representing the value of the edge for different tick values; d. generating a relationship between slots of the multiple edges; and e. outputting the simulated circuit to a database, the simulated circuit being represented by the relationship generated between the slots of the multiple edges.