Patent ID: 8264061

Claim:
A memory device comprising: an array of chalcogenide memory cells; a conductive substrate comprising an X-Y grid of electrodes on which the array of chalcogenide memory cells are formed; each memory cell comprising; a) a lower electrode formed in a window formed in a layer of insulating material, wherein the lower electrode material of the chalcogenide memory cells is selected from the group consisting of Ti, TiN, and TiC x N y , the window having insulator spacers formed therein defining a dimension of the memory cell lower electrode; b) a chalcogenide material formed over the lower electrode; and c) an upper electrode formed over the chalcogenide material and an insulator formed over the memory cell; the upper electrode in electrical contact with an upper X-Y grid of conductors; diodes in series with the chalcogenide memory cells; wherein the upper and lower X-Y grid of conductors are configured for addressing the memory cells; and wherein the diodes provide for read/write operations of the memory cells.