Patent ID: 8902658

Claim:
A method of operating a three dimensional nonvolatile memory formed in two or more physical levels of memory cells disposed above a silicon substrate, comprising: operating a plane of the three dimensional nonvolatile memory according to a default erase scheme for erase operations during a first period of operation of the three dimensional nonvolatile memory array, the plane including a group of blocks connected by a common set of bit lines; subsequently determining that two or more blocks of the plane are not adequately erased using the default erase scheme; in response to the determining, measuring bit line voltage during an erase operation using the default erase scheme to identify a difference between measured bit line voltage and a target bit line voltage; in response to identifying that the difference exceeds a threshold amount, replacing the default set of erase parameters with a modified set of erase parameters for the plane, the modified set of erase parameters including at least one select voltage that is not fixed, the at least one select voltage being modulated according to a measured bit line voltage; and subsequently operating the plane of the three dimensional nonvolatile memory using the modified set of erase parameters throughout a second period of operation of the nonvolatile memory.