Patent ID: 7830191

Claim:
A Vernier delay circuit that provides different multiple-stage delays to a first signal and a second signal, comprising: a first delay circuit configured such that a plurality of first variable delay elements, each operative to provide a delay determined by a bias signal to an input signal, are connected to form multiple stages, the circuit providing a delay of a first predetermined amount to the first signal in each stage comprising the first variable delay element, and outputting a plurality of first delayed signals delayed by different amounts; a second delay circuit configured such that a plurality of second variable delay elements, each operative to provide a delay determined by a bias signal to an input signal, are connected to form multiple stages, the circuit providing a delay of a second predetermined amount to the second signal in each stage comprising the second variable delay element, and outputting a plurality of second delayed signals delayed by different amounts; a ring oscillator operative to oscillate at a frequency determined by a bias signal; a bias signal adjusting unit operative to adjust the bias signal for the ring oscillator using feedback so that an oscillation frequency of the ring oscillator matches a reference frequency; and an individual bias circuit operative to produce a plurality of bias signals that should be provided to the plurality of second variable delay elements individually, wherein at least the bias signal produced by the bias signal adjusting unit is provided to the plurality of first variable delay elements, and each of the plurality of second variable delay elements is provided with a composite bias signal derived from superimposing the individual bias signal produced by the individual bias circuit, on the bias signal produced by the bias signal adjusting unit.