Patent ID: 6988173

Claim:
A shared memory symmetrical processing system having a bus coherency protocol for a non SCI (scalable coherency interface) comprising: a first ring and a second ring for interconnecting a plurality of nodes, wherein said plurality of nodes comprises at least one of a processor, cache memory, a plurality of I/O adapters, main memory, and a system control element wherein nodal communications are routed; and wherein said first and second rings simultaneously facilitate coherent bus transactions and data bus transactions wherein said coherent bus transactions include a first message comprising a snoop broadcast and early responses, and a second message comprising a final response; and wherein said data bus transactions provide cache or memory data on one and only one of said first ring or second ring such that all data transactions always traverse the fastest path; and wherein said cache data return is processed concurrently with early response and always before formulation of final response, and wherein said memory data is processed upon final response and wherein said coherent bus transactions support a plurality of cache ownership states; and wherein separate bus transactions are permitted to traverse both rings independently of each other such that a first bus transaction may circulate around said first ring; and wherein a second unrelated bus transaction may circulate around said second ring thereby permitting a plurality of bus transactions to be active, including a plurality of coherency bus transactions, while system level coherency for all ring operations is concurrently managed, and said system control element comprises a plurality of controllers for employing said bus protocol; and wherein said system level coherency is established through the use of bus transactions which comprise a first message part launched simultaneously down both rings and a second message part which is returned to the requesting node on both rings; and wherein said first message contains snoop broadcast and partial coherency status formulated via the ordered merging of incoming ring responses with local node response; and wherein said second message part contains a complete coherency status for all nodes thereby eliminating the need to initiate separate final response or acknowledgement transactions and wherein said controllers on each node are required to assert an early response as part of said bus coherency protocol.