Patent ID: 7642186

Claim:
A method of forming a metal line of a semiconductor device, the method comprising: forming an interlayer dielectric layer on a semiconductor substrate including a lower line; forming a via hole in the interlayer dielectric layer; forming a diffusion barrier layer on the interlayer dielectric layer including in the via hole; forming a first copper seed layer and a first copper plating layer on the diffusion barrier layer such that at least part of the first copper seed layer and at least part of the first copper plating layer are in the via hole; etching the first copper seed layer and the first copper plating layer to form a first copper plating structure in the via hole; forming a second copper seed layer and a second copper plating layer on the first copper plating structure such that at least part of the second copper seed layer and at least part of the second copper plating layer are in the via hole: planarizing the semiconductor substrate to expose the interlayer dielectric layer, whereby a copper metal line is provided in the via hole.