Patent ID: 7181551

Claim:
A double-data rate (DDR) bus system for use in a host-daughtercard interface that is pin compatible with a legacy interface used to interface a legacy daughtercard with the host, with legacy interface including a parallel port utilized by the host to write values to registers on the daughtercards, with the parallel port utilizing a subset of pins on a host-daughtercard connector, with the bus system comprising: a daughtercard termination logic block, coupled to the subset of pins previously used for the parallel port that redefines the subset of pins as a set of receive pins, a receive control pin, a receive clock pin, a set of transmit pins, a control pin, and a transmit clock pin; a host termination logic block, coupled to the subset of pins previously used for the parallel port that redefines the subset of pins as a set of receive pins, a receive control pin, a receive clock pin, a set of transmit pins, a transmit control pin, and a transmit clock pin; where the daughtercard termination logic implements DMA transfers between memory or registers on the daughtercard and host memory, and where packet data is transferred using generic data frames, where control is asserted utilizing control frames, and where a control signal is asserted on the control pin to indicate control frames; where the host termination logic utilizes read and write frames to implement the function of the legacy parallel port to read and write data to daughtercard registers, where packet data is transferred using generic data frames, where DMA data is transferred using DMA data frames, where control is asserted utilizing control frames, and where a control signal is asserted on the control pin to indicate control frames.