Patent ID: 7231625

Claim:
A method of placing cells in an integrated circuit layout pattern, the method comprising: receiving a base layer layout pattern defining an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells, and wherein each decoupling capacitor cell has a width which is greater than that of a single base cell location and which is abstracted from the base layer layout pattern; receiving a cell library defining a plurality of cells, including a macro cell having open rows consistent with rows in the base layer layout pattern that are reserved for the decoupling capacitor cells, wherein the width of each decoupling capacitor cell is abstracted from the macro cell; and placing cells from the cell library, including the macro cell, within a design layout pattern relative to the base layer layout pattern, wherein an area consumed by the macro cell within the design layout pattern is independent of the width of the decoupling capacitor cells.