Patent ID: 8909908

Claim:
A pipelined out-of-order execution in-order retire microprocessor, comprising: a cache memory; a branch predictor, configured to predict a target address of a branch instruction; a fetch unit, coupled to the branch predictor, configured to fetch instructions at the predicted target address; and an execution unit, coupled to the fetch unit, configured to: resolve a target address of the branch instruction and detect that the predicted and resolved target addresses are different; determine whether there is an unretired load instruction that missed in the cache memory and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired load instruction that missed in the cache memory and that is older in program order than the branch instruction; and refrain from executing the branch instruction, if there is an unretired load instruction older than the branch instruction in program order and that missed in the cache memory; wherein the microprocessor further comprises a pipeline having a top portion, wherein the top portion includes the cache memory, the branch predictor and the fetch unit and excludes the execution unit; wherein the microprocessor is configured to: refrain from retiring the mispredicted branch instruction as resolved; and replay the load instruction and the branch instruction without re-fetching them from the cache memory and without re-processing them in the top portion of the pipeline.