Patent ID: 7242609

Claim:
An SRAM memory system, comprising: at least one memory cell having a true node operatively coupled to a bit line and a complementary node operatively coupled to a complementary bit line; and at least one write pre-charge circuit operable to charge the bit line and the complementary bit line to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the at least one memory cell, wherein the at least one write pre-charge circuit: includes at least one NMOS field effect transistor coupled from Vdd to the bit line and at least one NMOS field effect transistor coupled from Vdd to the complementary bit line, and is operable to charge the bit line to about Vdd-Vth and to charge the complementary bit line to about Vdd-Vth, where Vth is approximately a threshold voltage of the NMOS field effect transistors.