Patent ID: 8539202

Claim:
An apparatus comprising: a front end to receive an instruction indicating a source and a destination, the source having a first plurality of packed floating point values, the first plurality of the packed floating point values including a first floating point value, a second floating point value, and a third floating point value, the second floating point value between the first floating point value and the third floating point value; and an execution core coupled with the front end, the execution core to store a result corresponding to the instruction in the destination, the result including a second plurality of packed floating point values, the second plurality of the packed floating point values including is fourth floating point value that is equal to the first floating point value, a fifth floating point value, that is equal to the first floating point value, a sixth floating point value that is equal to the third floating point value, and a seventh floating point value that is equal to the third floating point value, wherein the fourth and fifth floating point values being equal to the first floating point value is fixed by a type of the instruction.