Patent ID: 6967882

Claim:
A semiconductor memory comprising: a plurality of cell arrays each having static memory cells; bit lines and word lines wired on said cell arrays, respectively, and connected to said static memory cells; a read circuit connected in common to the bit lines of different ones of said cell arrays, and determining a logical value of data read out onto any of the bit lines of said cell arrays; a common read data line connected to an output of said read circuit; an error correcting circuit connected to said common read data line, correcting an error in the data read out onto said common read data line and outputting the data as corrected data; a common write data line for transmitting the corrected data therethrough; write switches connecting said common write data line to a corresponding bit line in order to write back the corrected data to one of said memory cells from which the corrected data has been originally read out; and a first operation control circuit continuing to activate a corresponding word line during a read cycle over a period from a read period in which the data is read out from the one of said memory cells to a writeback period in which the corrected data is written back to the one of said memory cells.