Patent ID: 7564722

Claim:
A processor-based system, comprising: core logic coupled to a processor bus, the core logic including a dynamic random access memory (“DRAM”) memory buffer controller; a dynamic random access memory (“DRAM”) module including a memory buffer coupled to a plurality of dynamic random access memory devices, the memory buffer being coupled to the memory buffer controller though a memory bus; a non-volatile memory module having a non-volatile memory buffer coupled to the memory bus and at least one non-volatile memory device coupled to the non-volatile memory buffer, the non-volatile memory buffer comprising: a downstream link interface coupled to receive DRAM memory requests from the DRAM memory buffer controller through a downstream portion of the memory bus; an upstream link interface coupled to transmit read data to the DRAM memory buffer controller though an upstream portion of the memory bus; a non-volatile memory device interface coupled to the at least one non-volatile memory device; a DRAM-to-non-volatile memory converter operable to convert the DRAM memory requests to non-volatile memory requests and to apply the non-volatile memory requests to the non-volatile memory device interface; and a memory transfer state machine coupled to at least one of the DRAM-to-non-volatile memory converter and the non-volatile memory device interface, the memory transfer state machine being operable to control the timing at which signals corresponding to the non-volatile memory requests are applied to the at least one non-volatile memory device from the non-volatile memory device interface; and a processor coupled to a processor bus, the processor bus coupling the DRAM module and the non-volatile memory module to the core logic in sequential order so that one of the modules is connected directly to the core logic and the others of the modules are connected to the core logic through another of the other modules.