Patent ID: 7160799

Claim:
A process for manufacturing an integrated circuit, the process comprising: providing a substrate comprising a dielectric layer over a conductive material; depositing a hardmask over the dielectric layer; applying a first photoresist over the hardmask and photodefining at least one first elongated opening; etching the hardmask and partially etching the dielectric to deepen the at least one first elongated opening to form a trench the trench having a bottom in the dielectric layer wherein the hardmask is not in contact with the bottom of the trench removing the first photoresist; applying a second photoresist and photodefining at least one second elongated opening transverse to the at least one trench so as to expose a portion of the dielectric defined by an intersection of the first and second openings; etching the exposed dielectric from the bottom of the at least one trench down to the underlying conductive material.