Patent ID: 7663592

Claim:
A system for driving a display comprising: a signal driving circuit, comprising: a plurality of shift registers connected in series, each comprising a first control terminal, a second control terminal, an input terminal and an output terminal, each being controlled by a first clock signal and a second clock signal and outputting corresponding driving pulses in turn according to a start pulse; wherein the output terminal of an Nth of the shift registers is coupled to the input terminal of an N+1 th of the shift registers, the output terminal of the N+1 th shift register is coupled to the second control terminal of the N th shift register, and the first control terminals of the N th and the N+ 1 th shift registers are coupled to the first clock signal and the second clock signal, respectively; and a pulse generation unit comprising an input terminal coupled to a corresponding of the driving pulses from a last of the shift registers, a first control terminal coupled to the first clock signal, and a second control terminal coupled to the second clock signal, wherein the pulse generation unit outputs a disable pulse to disable the last of shift registers according to the received driving pulse and the first clock signal received by the first control terminal, and is disabled according to the second clock signal received by the second control terminal; wherein the pulse generation unit is coupled to the last of the shift registers, comprising: a first transistor, having a first terminal coupled to a power voltage, a control terminal coupled to the second control terminal of the last of the shift registers, and a second terminal; a second transistor, having a first terminal coupled to the second terminal of the first transistor, a control terminal coupled to the second clock signal, and a second terminal coupled to a node; a third transistor, having a first terminal coupled to the node, a control terminal coupled to a ground voltage, and a second terminal; a forth transistor, having a first terminal coupled to the second terminal of the third transistor, a control terminal coupled to the output terminal of the last of the shift registers, and a second terminal coupled to the output terminal of the last of the shift registers; a fifth transistor, having a first terminal coupled to the second control terminal of the last of the shift registers, a control terminal coupled to the first clock signal, and a second terminal; and a sixth transistor, having a first terminal coupled to the second terminal of the fifth transistor, a control terminal coupled to the node, and a second terminal coupled to the ground voltage.