Patent ID: 6900110

Claim:
A method for fabricating an integrated circuit package comprising: providing an integrated circuit wafer, said integrated circuit wafer including a plurality of individual integrated circuit dice, said integrated circuit wafer further having a top surface including a plurality of bond pads which connect to said individual integrated circuit dice and a bottom surface opposite said top surface; depositing a sacrificial layer over said integrated circuit wafer, said sacrificial layer having vias aligned over said bond pads; forming compliant leads over said bond pads, each of said compliant leads being conductively coupled to a one of said bond pads through one of said vias; removing said sacrificial layer, said removing forming an air gap having a vertical distance between said integrated circuit wafer and said compliant leads; and singulating said integrated circuit wafer into individual integrated circuit packages, wherein forming compliant leads over said sacrificial layer further includes depositing a conductive layer over said sacrificial layer including said bond pads; depositing a resilient layer over said conductive layer; forming vias in said resilient layer, said vias being formed in said resilient layer a horizontal distance from each of said bond pads to which each of said compliant leads is conductively coupled said conductive layer being exposed within said vias; forming contact bumps on said conductive layer through said vias, said contact bumps being conductively coupled with said conductive layer; removing portions of said resilient layer to form the resilient layer of said compliant leads; and removing portions of said conductive layer to form the conductive layer of said compliant leads.