Patent ID: 7586951

Claim:
A method for generating an idle packet comprising: generating the idle packet formed of a plurality of words each formed of a plurality of bits, based at least in part on the idle packet having the same binary bit value in each of the plurality of words and conforming to a predetermined error correction code for each respective lane of a plurality of lanes of a link coupled between a first integrated device and a second integrated device, wherein the link is of a cache-coherent, link-based interconnect scheme; transmitting the idle packet from a physical layer of a transmitter of the first integrated device along the link; receiving the idle packet in a physical layer of a receiver of the second integrated device; identifying the idle packet with a first row of the plurality of words designated as a header; and powering down or clock gating a predetermined portion of the transmitter for at least the duration of the idle packet responsive to identifying the idle packet, wherein the predetermined portion of the transmitter includes a transmitter equalizer (TX EQ) and a predriver circuitry.