Patent ID: 8079010

Claim:
A wiring information generating apparatus that connects a plurality of logic element devices arranged on a substrate of a semiconductor logic circuit, the wiring information generating apparatus comprising: an input unit that inputs a wiring layer number indicating a wiring layer in which wiring is to be carried out, a via layer number indicating a next via layer to connect the wiring layer with other wiring layer, and spacing information based on wiring rules; a storage unit that stores a terminal figure table providing a terminal figure of a logic element device, a logic element device wire protected area table providing logic element device wire protected areas inside the logic element device, and a wire protected area table providing wire protected area information for the semiconductor logic circuit; a wire protected area creation unit that creates wire protected area information for the semiconductor logic circuit by adding to the wire protected area table an area of a terminal figure and a logic element device wire protected area that are obtained by searching the terminal figure table and the logic element device wire protected area table based on the input wiring layer number and/or via layer number, acquiring first wire layer-via layer spacing information indicating spacing between one of a plurality of wiring layers and one of a plurality of via layers based on the wiring layer number and/or via layer number, and adding the first wire layer-via layer spacing information to the wire protected area table; and a wiring information generating unit that generates wiring information in a wiring layer based on connection information and arrangement information of the semiconductor logic circuit, and the wire protected area information.