Patent ID: 8200877

Claim:
Device for processing a stream of data words received from a data source at one input, wherein the data words are buffered in a first FIFO memory, further comprising an interface for outputting the data words in completion packets of a defined format, and comprising a processor for generating request packets for controlling an external device via the interface, wherein the request packets are buffered in a second FIFO memory, wherein said completion packets and request packets are transferred to the interface via the same data lines, further comprising a multiplexer unit, that mixes completion packets and request packets for output via the interface in a manner according to a priority scheme, where a currently being transferred completion packet with a preset completion packet length is continued to be sent until the last byte of the currently being transferred completion packet is sent and a request packet ready to be sent is transferred with high priority over the bus, thereby interrupting the transfer of further completion packets ready to be sent for the time needed to send the request packet ready to be sent.