Patent ID: 8345493

Claim:
A semiconductor memory device comprising: a first normal cell array comprising normal cells connected to odd word lines and bit lines and normal cells connected to even word lines and bit lines bar; a second normal cell array comprising normal cells connected to the odd word lines and the bit lines bar and normal cells connected to the even word lines and the bit lines; a first redundancy cell array comprising redundancy cells connected to the odd word lines and the bit lines and redundancy cells connected to the even word lines and the bit lines bar; a second redundancy cell array comprising redundancy cells connected to the odd word lines and the bit lines bar and redundancy cells connected to the even word lines and the bit lines; a repair detection unit configured to detect a repair operation of the second normal cell array through the first redundancy cell array or a repair operation of the first normal cell array through the second redundancy cell array; and a repair inversion unit configured to selectively repair the odd and even word lines of each of the first and second normal cell arrays with the odd and even word lines of the first redundancy cell array in response to an output signal of the repair detection unit when the normal cell array is selected for being repaired with the first redundancy cell array, wherein the repair inversion unit is further configured to selectively repair the odd and even word lines of each of the second and first normal cell arrays with the odd and even word lines of the second redundancy cell array in response to an output signal of the repair detection unit when the normal cell array is selected for being repaired with the second redundancy cell array.