Patent ID: 7990795

Claim:
A system comprising: storage circuitry which stores an address for each of one or more rows of a DRAM that do not meet a data retention criteria at a low power refresh rate, wherein the one or more rows of the DRAM do meet a data retention criteria at a standard refresh rate which is greater than the low power refresh rate; a counter which counts received refresh requests for the DRAM; refresh control circuitry coupled to the storage circuitry and the counter, wherein the refresh control circuitry, in response to a refresh request for the DRAM and based on a count value of the counter, performs a refresh of the DRAM or accesses the storage circuitry to perform a refresh of the one or more rows of the DRAM identified in the storage circuitry; and built-in self test (BIST) circuitry, which performs data retention testing on the DRAM to identify the one or more rows of the DRAM that do not meet the data retention criteria at the low power refresh rate, wherein the data retention testing is in response to start-up of the DRAM.