Patent ID: 7512030

Claim:
An integrated circuit comprising a memory configured to provide a low power WRITE mode of operation having a reduced IDDQ relative to the IDDQ of a full active mode, the integrated circuit comprising: an SRAM memory array; mode control circuitry coupled to the array and configured to alter one or more supply voltage levels to the SRAM array based on a mode of operation; and control inputs coupled to the mode control circuitry for selecting one of the low power write mode, and the full active mode of operation; wherein the mode control circuitry is configured to receive the control inputs in order to select the one of the low power WRITE mode, and the full active mode of operation based on the control inputs, and to alter the one or more supply voltage levels for the SRAM array based on the selected mode of operation; and wherein the mode control circuitry for the SRAM memory array comprises a cycle timing circuit configured to regulate the timing of the modes of operation.