Patent ID: 7755948

Claim:
A memory comprising: an array of memory cells arranged in N columns of memory cells and M rows of memory cells; M select lines coupling to corresponding rows of memory cells; N bit lines coupling to corresponding columns of memory cells, wherein M and N are positive integers; an address decoder adapted to enable a selected one of the M select lines in response to an address; and N sense amplifiers coupled to corresponding ones of the bit lines; wherein at least one of the sense amplifier comprises: a first precharge transistor adapted to couple the corresponding one of the bit lines to a power supply node in response to a first signal; an amplifier, having an output and an input, the input coupling to the corresponding bit line; a first transistor, responsive to the output of the amplifier, adapted to couple the input of the amplifier to an intermediate node; and a second transistor adapted to selectively couple the intermediate node to the power supply node in response to a signal dependent on one of process speed of the memory or temperature of the memory.