Patent ID: 8611174

Claim:
A semiconductor memory device comprising: a first memory cell array having a plurality of memory blocks, each memory block having a plurality of columns and being corresponding respectively to one of a plurality of data terminals, and the memory blocks being arranged side by side in the column-wise direction; a second memory cell array having a plurality of memory blocks and a plurality of data terminals of which arrangement is same as the first memory cell array; and an output circuit which selectively outputs data received from the memory blocks in a first set, or data received from the memory blocks in a second set, depending on addresses to be accessed, wherein the output circuit comprises: a first logical product operation circuit which receives the data from the memory blocks in the first set, and receives a selection signal depending on an address to be accessed; a second logical product operation circuit which receives the data from the memory blocks in the second set, and receives the inverted selection signal; and a logical sum operation circuit which receives an output of the first logical product operation circuit and an output of the second logical product operation circuit, and wherein addresses are assigned by classifying the memory blocks into the first set and the second set, the first set including the even-number-th memory blocks in the first memory cell array and the odd-number-th memory blocks in the second memory cell array, and the second set including the odd-number-th memory blocks in the first memory cell array and the even-number-th memory blocks in the second memory cell array.