Patent ID: 7502433

Claim:
A source synchronous interface for a receiver module, comprising: a first input cell including a first delay chain and a first register block, the first input cell coupled to receive a forwarded clock signal; a second input cell including a second delay chain and a second register block, the second input cell coupled to receive a data signal associated with the forwarded clock signal, output from the second delay chain coupled to a data input of the second register block; the first input cell coupled to the second input cell; in a first modality, output of the first delay chain provided as a first clock input to the first register block and the second register block and as a data input to the first register block; a receiver local clock signal provided as a second clock input to the first register block and the second register block; in a second modality, the output of the first delay chain provided as the first clock input and the second clock input to the second register block; wherein the first modality is for interfacing to a synchronous memory; wherein the second modality is for interfacing to one of a network system and a telecommunications system; and wherein in the second modality, the first register block is unused.