Patent ID: 7679146

Claim:
A semiconductor device comprising: a region of semiconductor material having a first major surface; a body region formed in the region of semiconductor material; a source region formed in the body region; a trench gate structure including a gate conductive layer separated from sidewalls of the trench gate structure by a gate dielectric layer, wherein the body region and source region are in proximity to the trench gate structure, and wherein the trench gate structure is configured to control a channel in the body region when the semiconductor device is in operation; a sub-surface trench compensation region formed in the region of semiconductor material and recessed below the first major surface, wherein the subsurface trench compensation region is adjacent a lower surface of the trench gate structure, and wherein the subsurface trench compensation region comprises a plurality of opposite conductivity type semiconductor layers, and wherein sidewalls of the subsurface trench compensation region adjoin the region of semiconductor material without an intervening dielectric layer; and a channel connecting region formed in the region of semiconductor material interposed between the body region and the subsurface trench compensation region and configured to electrically couple the channel to at least one of the plurality of opposite conductivity type semiconductor layers, wherein the channel connecting region and the source region comprise a first conductivity type, and wherein the channel connecting region overlies at least a portion of the plurality of opposite conductivity type semiconductor layers.