Patent ID: 7936206

Claim:
A capacitive voltage divider having an input and an output, the capacitive voltage divider comprising: a) a first metal-oxide-semiconductor field-effect transistor (MOSFET) having a bulk, drain and source and having the source and bulk electrically connected to the capacitive voltage divider output; b) a first capacitor having a first terminal coupled to the drain of the first MOSFET and a second terminal coupled to the input of the capacitive voltage divider; c) a first circuit coupled to the drain of the first MOSFET, the first circuit configured to apply a reverse bias to a first junction diode internal to the first MOSFET when the first MOSFET is off, the first junction diode being formed between the drain and the bulk of the first MOSFET; d) a second MOSFET having a bulk, drain and source and having the source and bulk electrically connected to a low potential reference level; e) a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to the source of the first MOSFET and the second terminal of the second capacitor coupled to the drain of the second MOSFET; and f) a second circuit, configured to reverse bias a second junction diode between the drain and bulk of the second MOSFET when the second MOSFET is off.