Patent ID: 8865576

Claim:
A method of producing a transistor comprising: providing a substrate including a gate positioned in contact with the substrate, the gate including a reentrant profile; depositing and patterning an electrically insulating material layer so that the electrically insulating material layer contacts a first portion of the gate and does not contact the substrate; conformally depositing a gate dielectric material layer so that the gate dielectric material layer contacts the electrically insulating material layer, contacts a second portion of the gate within the reentrant profile, and contacts at least a portion of the substrate; conformally coating the gate dielectric material layer with a semiconductor material layer; and forming a first electrode and a second electrode on the semiconductor material layer from distinct discontinuous portions of an electrically conductive material layer by directionally depositing the electrically conductive material layer on the semiconductor material layer; wherein the electrically insulating material layer and a portion of the gate dielectric material layer are both located between the first portion of the gate and the first electrode to space the first portion of the gate apart from the first electrode, and wherein a different portion of the gate dielectric material layer, but not the electrically insulating material layer, is located between the gate and the second electrode.