Patent ID: 8537605

Claim:
A nonvolatile semiconductor memory device comprising: a substrate provided with a plurality of transistors including first main electrodes, second main electrodes, and control electrodes; a first interlayer insulating layer formed over the substrate to cover the plurality of transistors; a plurality of first contact plugs formed to penetrate the first interlayer insulating layer and to be electrically connected to the first main electrodes of the plurality of transistors, respectively; a plurality of resistance variable layers formed to respectively correspond to the plurality of first contact plugs with a one-to-one relationship with the plurality of first contact plugs and to cover at least portions of upper end surfaces of the plurality of first contact plugs, respectively; and a first wire formed on the plurality of resistance variable layers to extend in a first direction; wherein when the first direction is a forward and rearward direction, and a direction which is perpendicular to the first direction and parallel to a main surface of the substrate is a rightward and leftward direction, an end surface of each of the resistance variable layers in the forward and rearward direction is not coplanar with an end surface of the first wire, a left end surface of the first wire is coplanar with a left end surface of each of the resistance variable layers, and a right end surface of the first wire is coplanar with a right end surface of each of the resistance variable layers.