Patent ID: 6853217

Claim:
A semiconductor integrated circuit device, comprising: a first potential point having a first potential; a second potential point having a second potential; a level-up level conversion circuit including: first and second field-effect transistors of first conductivity type arranged to receive complementary input signals, wherein sources of the first and second field-effect transistors are coupled to the second potential point; and third and fourth field-effect transistors of second conductivity type, wherein a source of the third field-effect transistor is coupled to the first potential point, a drain of the third field-effect transistor is coupled to a drain of the first field-effect transistor, a gate of the third field-effect transistor is coupled to a drain of the second field-effect transistor, a source of the fourth field-effect transistor is coupled to the first potential point, a drain of the fourth field-effect transistor is coupled to a drain of the second field-effect transistor and a gate of the fourth field-effect transistor is coupled to a drain of the first field-effect transistor; and a current source to limit a current flowing through the level-up level conversion circuit.