Patent ID: 8295120

Claim:
A system comprising: a processor; a memory controller coupled to said processor; a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller, at least one of said DRAM chips comprising a clock synchronization circuit operative to receive a reference clock signal and to output a synchronized clock output signal; a plurality of signal buses coupling said processor to said memory controller and said memory controller to said DRAM chips; and a signal line coupling said memory controller to said clock synchronization circuit, said signal line conveying signals from said memory controller to said clock synchronization circuit to turn on and off the clock synchronization circuit according to control logic, wherein the control logic is operative to turn on the clock synchronization circuit at least partially in response to the first data read command and is further operative to keep the clock synchronization circuit turned on after reading the first data if the second command is received before the first data is ready to be read wherein the control logic extends the time that the clock synchronization circuit remains on by the column address store (CAS) latency period after the READ command.