Patent ID: 7026686

Claim:
A memory device comprising: a first conductive region; a second conductive region; and an insulating barrier for directly tunneling charge carriers between the first and second conductive regions for at least one of programming and erasing the memory device, the insulating barrier comprising: a first portion contacting the first conductive region; and a second portion contacting the first portion and extending towards the second conductive region, wherein the first portion of the insulating barrier is substantially thinner than the second portion of the insulating barrier, the first portion comprising one or more dielectric materials and the second portion also comprising one or more dielectric materials, the one or more dielectric materials of the second portion being different than the one or more dielectric materials of the first portion, and wherein the one or more dielectric materials of the first portion, the one or more dielectric materials of the second portion, a thickness of the first portion and a thickness of the second portions are chosen such that, upon applying an electric field suitable for directly tunneling charge carriers through the insulating barrier, a strength of the electric field over the first portion is greater than a strength of the electric field over the second portion and an energy level for directly tunneling charge carriers through the second portion is approximately equal to or less than an energy level for conduction of carriers in the first conductive region.