Patent ID: 8769338

Claim:
A device, comprising: a non-volatile memory; a state device configured to maintain operational states of the device; and a save-restore processor coupled to the state device and the non-volatile memory, wherein the save-restore processor is configured to: configure the state device with initialization parameters retrieved from the non-volatile memory when the device is turned on, retrieve an operational state of the state device before a start of a low power mode, store the retrieved operational state of the state device in the non-volatile memory, retrieve the operational state of the state device in the non-volatile memory at the end of the low power mode, restore the state device to the operational state at the end of the low power mode based, at least in part, on the retrieved operational state of the state device, and access a save-restore parameter table including at least one save-restore parameter for the state device, wherein the save-restore parameter includes a bus address increment parameter, wherein the bus address increment parameter indicates a bus address for the save-restore processor to bypass when storing or retrieving the operational state of the device.