Patent ID: 7617463

Claim:
A method for supplying a power to a semiconductor integrated circuit in a test comprising: preparing the semiconductor integrated circuit having a flip chip structure in the test, finding, by using a computer, a required minimum number of power supply ports for use in the test based on power consumption information and deciding the required minimum number of power bumps out of a plurality of power bumps as the power supply ports for use in the test; wherein among the plural power bumps located on a chip of the semiconductor integrated circuit, one or more of the plural power bumps being determined as the power supply ports for use in the test are brought into contact with power supply test terminals of a test jig, and the remaining power bumps are not brought into contact with the power supply test terminals of the test jig during the test, and repeating a step of detecting a voltage drop violation and a current density violation until neither violation is detected, using a power mesh analysis wherein the step comprises: deciding as the power supply ports for use in the test, a power bump corresponding to a place where the voltage drop violation occurs when the voltage drop violation is detected by the power mesh analysis and modifying a layout of a place where the current density violation occurs when the current density violation is detected by the power mesh analysis.