Patent ID: 7575968

Claim:
A method for fabricating a semiconductor structure, comprising: bonding a first semiconductor layer having a first crystal orientation directly to a second semiconductor layer having a second crystal orientation that is different from the first crystal orientation; selectively removing a portion of the second semiconductor layer to expose the first semiconductor layer in a first predetermined region and to leave a remaining portion of the second semiconductor layer in a second predetermined region; forming a dielectric layer to completely cover the exposed first semiconductor layer and the remaining portion of the second semiconductor layer with a dielectric layer, where the dielectric layer has an upper surface and a bottom surface; forming first and second trench openings in the dielectric layer, wherein the first trench opening exposes a portion of the first semiconductor layer in the first predetermined region and the second trench opening exposes a portion of the second semiconductor layer in the second predetermined region, and wherein the first and second trench openings each have a first dimension at the upper surface and a second dimension at the bottom surface that is smaller than the first dimension; and filling at least part of the first and second trench openings by epitaxially growing semiconductor material from the exposed portion of the first semiconductor layer and the exposed portion of the second semiconductor layer so that the first trench opening is filled at least in part with a first epi layer that has a third crystal orientation that is the same as the first crystal orientation and so that the second trench opening is filled at least in part with a second epi layer that has a fourth crystal orientation that is the same as the second crystal orientation.