Patent ID: 7939893

Claim:
A semiconductor device comprising: a semiconductor substrate having a principal surface; an isolation trench formed on the principal surface of said semiconductor substrate, said isolation trench defining first and second active regions and having a portion with an aspect ratio of 1 or larger; an isolation region including a field region and made of an insulator embedded in said isolation trench; a gate insulating film formed on surfaces of said first and second active regions; a first gate electrode formed on said gate insulating film, said first gate electrode traversing said first active region and containing phosphorus at a high concentration; a second gate electrode formed on said gate insulating film, said second gate electrode traversing said second active region and containing p-type impurities; a p-type resistor element formed on said field region and made of a same layer as a layer of said second gate electrode; a salicide block layer formed on a partial surface of said resistor element; side wall spacers formed on side walls of said first and second gate electrodes; first source/drain regions formed in said first active region outside the side wall spacers and containing phosphorus at a high concentration; second source/drain regions formed in said second active region outside the side wall spacers and containing p-type impurities; and salicide layers formed on surfaces of said resistor element not covered by the salicide block layer, at least partial surfaces of said first and second source/drain regions, and at least partial surfaces of said first and second gate electrodes.