Patent ID: 7253658

Claim:
An integrated circuit comprising an array of programmable tiles arranged in rows and columns, each programmable tile comprising: a general interconnect structure comprising horizontal interconnect lines traversing the tile in a first direction substantially parallel to the rows of programmable tiles and vertical interconnect lines traversing the tile in a second direction substantially parallel to the columns of programmable tiles; a plurality of input multiplexers, each input multiplexer having a plurality of input terminals coupled to the general interconnect structure and further having an output terminal; and a lookup table having a plurality of input terminals and a plurality of output terminals, each input terminal being coupled to the output terminal of an associated one of the input multiplexers, at least one of the output terminals being coupled to at least one of the horizontal interconnect lines and to at least one of the vertical interconnect lines in the general interconnect structure, wherein none of the programmable tiles in the array includes an output multiplexer structure coupled between the output terminals of the lookup table and the general interconnect structure.