Patent ID: 7068550

Claim:
A prefetch-type FCRAM having an improved data write control circuit in a semiconductor memory device including a memory cell array, a plurality of address pins, and a plurality of data pins, the prefetch-type FCRAM comprising: a command decoder which outputs control commands including first and second write commands in response to predetermined external input signals; a row decoder which decodes a row address signal input by the address pins and activates a wordline of the memory cell array corresponding to the decoded row address signal; a column decoder which decodes a column address signal input by the address pins and activates a column select line of the memory cell array corresponding to the decoded column address signal; a data input buffer which receives input data from the plurality of data pins and outputs the input data in synchronization with a predetermined clock signal; a data output buffer which outputs output data read from the memory cell array to the plurality of data pins; and a valid write window buffer which outputs a data masking control signal that controls the masking of input data in response to a combined address signal input by the address pins, wherein the column decoder disables a column select line where data to be masked among the input data will be input in response to the data masking control signal.