Patent ID: 8093638

Claim:
An electronic system comprising: a memory having a memory array, the memory array including a transistor having a gate coupled to a dielectric film, the dielectric film located on a body region on a silicon based substrate between a first source/drain region and a second source/drain region, the dielectric film on and contacting an interface region that is on and contacting the body region, the interface region including a lanthanide silicate, the lanthanide silicate consisting essentially of a lanthanide, silicon, and oxygen, the dielectric film containing a first lanthanide oxide and a second lanthanide oxide, wherein the first and second lanthanide oxides are different lanthanide oxides, the first lanthanide oxide includes a lanthanide not included in the second lanthanide oxide, the lanthanide not included in the second lanthanide oxide being the lanthanide of the lanthanide silicate, the dielectric film having: a crystalline layer of the first lanthanide oxide disposed on and in contact with the lanthanide silicate; and the second lanthanide oxide disposed on and in contact with the crystalline layer of the first lanthanide oxide.