Patent ID: 7852116

Claim:
An integrated circuit comprising: A. a semiconductor substrate; B. functional circuitry formed on the substrate for performing normal operating functions of the integrated circuit; C. an output terminal formed on the substrate; D. a test data path formed on the substrate; E. memory circuitry formed on the substrate and having an input and an output; F. test control circuitry formed on the substrate and having a first input coupled with the functional circuitry, a second input coupled with the test data path, a third input, and an output connected with the memory circuitry input; and G. latching output buffer circuitry formed on the substrate and connected between the memory circuitry output and the output terminal, the buffer circuitry including a switch and an output buffer connected in series between the memory circuitry and output terminal and including an input buffer connected in parallel with the output buffer, the input buffer being electrically weaker than the output buffer, the output buffer and input buffer forming a latch circuit, the latching output buffer circuitry including a feedback lead having one end connected between the switch and the output buffer and the other end connected to the third input of the test control circuitry.