Patent ID: 7696557

Claim:
An electronic system, comprising: a processor; and a non-volatile memory device coupled to the processor, wherein the non-volatile memory device comprises: an array of non-volatile floating-gate memory cells arranged in rows and columns; and control circuitry for controlling access to the array of memory cells; wherein the array of memory cells comprises: a first column of memory cells having a first source/drain region and a second source/drain region laterally spaced apart in a first well associated with the first column, wherein the first well associated with the first column has a first conductivity type and the first and second source/drain regions have a second conductivity type opposite the first conductivity type; and a second column of memory cells having a first source/drain region and a second source/drain region laterally spaced apart in a first well associated with the second column, wherein the first well associated with the second column has the first conductivity type and the first and second source/drain regions have the second conductivity type opposite the first conductivity type; wherein the first column of memory cells and the second column of memory cells are isolated from each other by an interposing dielectric material and by an underlying second well having the second conductivity type; wherein the first and second source/drain regions of the first column of memory cells are each a continuous structure that spans the first column of memory cells; and wherein the first and second source/drain regions of the second column of memory cells are each a continuous structure that spans the second column of memory cells.