Patent ID: 7865851

Claim:
A computer implemented method for determining parasitic capacitances of layout data representing an integrated circuit design comprising: accessing by the computer an integrated circuit design, the integrated circuit design comprising a first fill net, a second fill net, and a signal net; extracting capacitances of the signal net; extracting coupling capacitances between the first fill net and the signal net; determining an effective capacitance of the first fill net by approximating a coupling capacitance between the first fill net and the second fill net; decoupling the first fill net from the second fill net according to a predetermined extraction approximation level selected by a user; and determining an effective total capacitance of the signal net, wherein the determined effective total capacitance of the signal net is based at least in part upon the extracted capacitances of the signal net, the extracted coupling capacitances between the first fill net and the signal net, and the determined effective capacitances of the first fill net.