Patent ID: 7065732

Claim:
A method for applying partitioning logic to partially optimized programmable logic arrays comprising: determining an optimum splitting variable for dividing a programmable logic array (PLA) into at least two sub-PLAs by avoiding unbalanced columns in an AND plane of a set of equations representing the PLA; and selecting a column with smallest overhead in the AND plane of the set of equations representing the PLA, each sub-PLA of said at least two sub-PLAs having an AND plane and an OR plane, a first sub-PLA of said at least two sub-PLAs includes products in which said splitting variable is in complemented form, a second sub-PLA of said at least two sub-PLAs includes products in which said splitting variable is in uncomplemented form, said splitting variable corresponding to a specific input, output and product in the set of equations representing the PLA; dividing the set of equations representing the PLA into a first set of equations representing the first sub-PLA and a second set of equations representing the second sub-PLA based on the splitting variable; determining a topological circuit representation of the equations representing the first sub-PLA and the equations representing the second sub-PLA; applying gating logic to the topological circuit representation of the equations representing the first sub-PLA and the equations representing the second sub-PLA; and controlling power consumption in the topological circuit representation of the equations representing the first sub-PLA and the equations representing the second sub-PLA so only one of the topological circuit representation of the first sub-PLA and the second sub-PLA contributes to power consumption, wherein an OR plane of the topological circuit representation of the first sub-PLA is interleaved with an OR plane of the topological circuit representation of the second sub-PLA.