Patent ID: 8638144

Claim:
A system including circuitry that controls clock signals, the circuitry comprising: digital phase detection circuitry that uses a phase detect window to detect an input signal phase of a first clock and an output signal phase of a second clock; digital delay control circuitry configured to, via a first adjustment mode, adjust a delay channel until the output signal phase is within a first phase detection window of the input signal phase; analog phase detection circuitry that detects the input signal phase and the output signal phase; and analog delay control circuitry configured to, via a second adjustment mode, adjust the delay channel until the output signal phase is equal to the input signal phase, in response to which the circuitry transitions from an unlocked state to a locked state; wherein the circuitry has a configuration that prevents transition back to the unlocked state due to jitter or noise; wherein the first phase detection window has a duration of between about 50 to about 900 picoseconds.