Patent ID: 7247552

Claim:
An integrated circuit, comprising: a substrate having active circuitry; a bond pad over the substrate; a force region at least under the bond pad characterized by being susceptible to defects due stress applied to the bond pad; a stack of interconnect layers, wherein each interconnect layer has a portion in the force region; and a plurality of interlayer dielectrics separating the interconnect layers of the stack of interconnect layers and having at least one via for interconnecting two of the interconnect layers of the stack of interconnect layers; wherein at least one interconnect layer of the stack of interconnect layers comprises a functional metal line underlying the bond pad that is not electrically connected to the bond pad and is used for wiring or interconnect to the active circuitry, the at least one interconnect layer of the stack of interconnect layers further comprising dummy metal lines in the portion that is in the force region to obtain a predetermined metal density in the portion that is in the force region.