Patent ID: 8225257

Claim:
A method for reducing path delay sensitivity to temperature variation in a circuit, the method comprising the steps of providing a system comprising a tangible, computer-readable recordable storage medium, embodying in a non-transitory manlier first, second, and third computer instructions; identifying at least one path between an input and an output of the circuit that introduces to a signal passing therebetween a largest delay front the input of the circuit to the output of the circuit, the path including a plurality of circuit cells coupled between an input and an output of the path, by executing said first computer instructions on at least one hardware processor; determining a temperature slope coefficient of the path, by executing said second computer instructions on at least one hardware processor; when the slope coefficient is negative, increasing the slope coefficient by controlling at least one characteristic of at least one of the cells in the path, by executing said third computer instructions on at least one hardware processor; and when the slope coefficient is positive, decreasing the slope coefficient by controlling at least one characteristic of at least one of the cells in the path, by executing said third computer instructions on at least one hardware processor.