Patent ID: 7349450

Claim:
A bit stream demultiplexer having a switchable master slave relationship comprising: a first demultiplexing integrated circuit that receives at least one input signal and outputs a plurality of first bit streams at a first bit rate; a second demultiplexing integrated circuit that receives the plurality of first bit streams and outputs a plurality of second bit streams at a second bit rate, wherein the plurality of second bit streams are greater in number than the plurality of first bit streams, and wherein the first bit rate is greater than the second bit rate; and a clock circuit, wherein the clock circuit generates a clock signal for the first demultiplexing integrated circuit based upon a reference clock signal when the second demultiplexing integrated circuit operates in a master mode, and wherein the clock circuit generates the clock signal based upon an external clock signal received from the first demultiplexing integrated circuit when the second demultiplexing integrated circuit operates in a slave mode.