Patent ID: 7757137

Claim:
A scan-chain for use in LSSD or GSD-based VLSI circuit designs, the scan chain comprising: at least two flip-flops configured to operate in normal mode operation, in scan mode operation and in low leakage power mode operation, where each flip-flop includes a data input a data output, a clock input, a scan-in input and a scan-out output; and a input vector control (IVC) circuit electrically connected between the scan-out output of one of the at least two of flip-flops and the scan-in input of a next flip-flop within a scan chain, the IVC circuit comprising: a mode control element to receive the scan-out output of one of the at least two flip-flops and forcing said scan-out output in one of normal mode, low power leakage mode and initialization mode, wherein the one flip-flop scan-out output is set to a data output value upon exit from low power leakage mode that is equivalent to the flip-flop is set to at initialization during normal mode operation.