Patent ID: 6838924

Claim:
A circuit comprising: a first level shifting stage for shifting an input signal having an input voltage range to an intermediate signal having an intermediate voltage range; and a second level shifting stage for shifting the intermediate signal to an output signal having an output voltage range; wherein the second level shifting stage comprises a high voltage transistor that tolerates a greater voltage difference than transistors of the first level shifting stage; and wherein the first level shifting stage comprises: first and second PMOS transistors, wherein a gate of the first PMOS transistor is coupled to a drain of the second PMOS transistor, and wherein a sate of the second PMOS transistor is coupled to a drain of the first PMOS transistor; a first NMOS transistor, wherein a drain of the first NMOS transistor is coupled to the drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to the drain of the second PMOS transistor.