Patent ID: 8482112

Claim:
A semiconductor package, comprising: a lead frame; a first die pad; a first die disposed on the first die pad; a second die pad, wherein the second die pad is situated apart from the first die pad; a second die disposed on the second die pad; a bonding ring, wherein at least a portion of the bonding ring is situated between the first die pad and the second die pad; a first wire bond coupled with the bonding ring and a bond pad of the first die; a second wire bond coupled with the bonding ring and a bond pad of the second die; an encapsulant surrounding the die pads, the dice, the bonding ring, the wire bonds, and at least a portion of the lead frame; a third wire bond coupled with the first die pad and a first voltage source; and a fourth wire bond coupled with the second die pad and a second voltage source, wherein the semiconductor package is configured to operate the first die pad at a first potential and operate the second die pad at a second potential, wherein the first voltage source is configured to affect the first potential, wherein the second voltage source is configured to affect the second potential.