Patent ID: 7952947

Claim:
A semiconductor memory device comprising: a sense amplifying circuit connected to a bit line to sense and amplify data carried on the bit line; a bit line select unit selectively connecting the bit line and the sense amplifying circuit according to a bit line select control signal; a column select unit selectively connecting the sense amplifying circuit and a data bus according to a column select control signal; and a precharge unit precharging a voltage on the bit line between the sense amplifying circuit and the bit line select unit in response to a precharge command, wherein in a state in which the bit line and the sense amplifying circuit are disconnected by the bit line select unit, and the sense amplifying circuit and the data bus are connected by the column select unit, a pull-up activating terminal and a pull-down activating terminal of the sense amplifying circuit is controllably set to an inactive state, and the bit line and the sense amplifying circuit are connected by the bit line select unit during a restore section which is performed before an operation corresponding to a command following a read command is performed.