Patent ID: 8010772

Claim:
Apparatus for processing data, said apparatus comprising: a memory addressable with a memory address having a value within a memory address space, said memory address space having at least a first domain and a second domain, a domain comprising a set of memory addresses; instruction fetching circuitry coupled to said memory and operable to fetch a sequence of program instructions using respective memory addresses within said memory address space; instruction access control circuitry coupled to said instruction fetching circuitry and responsive to a fetch of a first instruction associated with a first memory address within said first domain followed by a fetch of a second instruction associated with a second memory address within said second domain: (i) to determine from an instruction code of said second instruction if said second instruction is a permitted branch target instruction that is permitted to execute when commencing executing instructions associated with said second domain after accessing instruction associated with said first domain; and (ii) if said second instruction is not a permitted instruction, then to trigger an access violation response; wherein: said memory address space comprises a plurality of domains, each having respective programmable capabilities associated therewith indicating which of the domain transitions into the other domains are or are not to be subject to permitted instruction checking, wherein said apparatus uses a plurality of program instruction sets, each program instruction set has at least one permitted branch target instruction and said instruction access control circuitry determines whether said second instruction is one of said at least one permitted branch target instructions for the instruction set that contains said second instruction.