Patent ID: 7348241

Claim:
A method of fabricating a cell structure of an EPROM device comprising: defining a gate stack region and a floating gate transistor region on a semiconductor substrate; sequentially forming a first floating gate, an insulating pattern including a nitride layer, and a control gate in the gate stack region, and sequentially stacking a gate insulating layer, a second floating gate connected to the first floating gate, and an insulating pattern in the floating gate transistor region completely covering a top surface of the second floating gate such that both sidewalls of the insulating pattern are substantially aligned with both side walls of the second floating gate; forming a source/drain by implanting impurity ions into the semiconductor substrate so as to be aligned to both sidewalls of the second floating gate; forming nitride spacers on both sidewalls of the first floating gate, the control gate, and the second floating gate; and forming a window for exposing the top surface of the first floating gate by etching the insulating pattern formed on the first floating gate.