Patent ID: 7873925

Claim:
A method for computing a margin for at-speed testing of a design for an integrated circuit chip, the method comprising: computing a statistical chip slack for the chip, wherein the chip slack is computed using statistical timing of the chip; computing a statistical test slack for the chip, wherein the test slack is computed using statistical timing of a tested portion of the chip; and computing the margin from the chip slack and the test slack, wherein computing the margin comprises: expressing the chip slack in terms of the test slack; calculating the margin such that when the test slack is greater than the margin, the chip slack is greater than zero with a required confidence; and maximizing a total fraction of chips put into circulation such that a number of bad chips put into circulation is less than or equal to a required quality level, wherein the margin represents a set of test slacks between zero and a number greater than zero, such that a number of chips falling within the margin include: a first set of chips for which the chip slack is less than zero and the test slack is lower than the number greater than zero and a second set of chips for which the chip slack is greater than zero and the test slack is lower than the number greater than zero, and wherein the first set of chips and the second set of chips are not put into circulation, wherein at least one of: said computing the statistical chip slack, said computing the statistical test slack, and said computing the margin is performed using a processor.