Patent ID: 7440353

Claim:
A DRAM memory device on an integrated circuit (IC), which comprises: a memory array including a plurality of first DRAM cells connected to a first word line circuit and a bit line circuit or bit line bar circuit; a plurality of second DRAM cells are connected to the bit line circuit or bit line bar circuit and a second word line circuit; a plurality of reference DRAM cells connected to a reference word line circuit and the bit line circuit or bit line bar circuit; a first power supply for supplying a voltage to the DRAM cells, the bit line circuit, and the first word line; a second power supply for supplying a reference voltage to the reference DRAM cells and the bit line bar circuit wherein the reference bit line voltage is different from the bit line voltage; control logic communicating with the DRAM memory device and the IC for providing normal DRAM cycle operation and initiating a body refresh cycle, and during the body refresh cycle the control logic generates a word line signal, a bit line control signal, a bit line bar control signal, and a reference word line signal; a sense amplifier circuit which amplifies the signal voltage at the bit line circuit and the bit line bar circuit; and the control logic being configured to generate the body refresh cycle periodically wherein the voltage supplied to the first word line is deactivated while the bit line and bit line bar voltages continue and the control logic is configured to re-activate the first word line voltage, and the word line signal is deactivated for two clock cycles such that the first cycle refreshes the bit line circuit and the second cycle refreshes the bit line bar circuit.