Patent ID: 7269089

Claim:
A memory block comprising: first and second n-bit memory blocks, each of the first and second n-bit memory blocks including bit lines, the bit lines of the first n-bit memory block being connected to the bit lines of the second n-bit memory block by pass gates, wherein the pass gates are enabled when the memory block is programmed to operate as a 2×n-bit memory block and the pass gates are disabled when the memory block is programmed to operate as two n-bit memory blocks; and a first set of write drivers and a first set of sense amplifiers associated with a first bit line of the memory block and a second set of write drivers and a second set of sense amplifiers associated with a second bit line of the memory block; wherein the memory block supports true dual port and simple dual port modes when the memory block is programmed to operate as the 2×n-bit memory block.