Patent ID: 7786803

Claim:
An apparatus for amplifying a signal, the apparatus comprising: a differential input circuit with at least a first transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the first transistor is coupled to a terminal for an inverting input and a second transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the second transistor is coupled to a terminal for a non-inverting input, wherein the source terminal of the first transistor and the source terminal of the second transistor are coupled to each other; a plurality of transistors coupled to the differential input circuit, wherein the plurality of transistors are configured to generate a first current for an output node and a second current for a cascode current mirror circuit, the plurality of transistors comprising: a third transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal is coupled to a first voltage reference for biasing, wherein the source terminal is coupled to the drain terminal of the second transistor, and wherein the drain terminal is coupled to the cascode current mirror circuit; a fourth transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal is coupled to the first voltage reference for biasing, wherein the source terminal is coupled to the drain terminal of the first transistor, and wherein the drain terminal is coupled to the cascode current mirror circuit and to the output node; a fifth transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal is coupled to the first voltage reference for biasing, wherein the source terminal is coupled to a second voltage reference for power, and wherein the drain terminal is coupled to the source terminal of the third transistor and to the drain terminal of second transistor; and a sixth transistor having a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal is coupled to the first voltage reference for biasing, wherein the source terminal is coupled to the second voltage reference for power, and wherein the drain terminal is coupled to the source terminal of the fourth transistor and to the drain terminal of first transistor; wherein the third and fourth transistors have a voltage threshold that is lower than a voltage threshold of the fifth and sixth transistors; and the cascode current mirror circuit coupled to the plurality of transistors and to the output node, wherein the cascode current mirror circuit is configured to pass the second current of the plurality of transistors, wherein the cascode current mirror circuit is configured to generate a mirrored current of the second current for the output node.