Patent ID: 7203809

Claim:
A semiconductor memory device adapted to be coupled with a processing unit comprising: a memory cell array which includes a plurality of memory cells; a self-excited oscillator which generates a timing signal; a plurality of address terminals which are to be coupled with a processing unit and which receive a plurality of address signals from the processing unit for selecting one of the plurality of memory cells; a plurality of data terminals which are to be coupled with the processing unit and which output a plurality of data signals from the plurality of memory cells to the processing unit; first terminals which are to be coupled with the processing unit and which receive first signals from the processing unit which demand outputting the plurality of data signals from the semiconductor memory device; and a second terminal which is to be coupled with the processing unit and which outputs the timing signal to the processing unit; wherein the processing unit is operated on an operation clock signal synchronously and generates the first signals in synchronism with the operation clock signal; wherein the timing signal is asynchronous with the first signals and the operation clock signal, and wherein the semiconductor memory device outputs the plurality of data signals in synchronism with the timing signal.