Patent ID: 7894927

Claim:
A method for using a Multi-Layer/Multi-Input/Multi-Output (MLMIMO) model comprising: receiving a first set of patterned wafers and associated wafer data, each patterned wafer having a first patterned soft-mask layer and a plurality of additional layers, the first patterned soft-mask layer including a plurality of metal-gate-related soft-mask features and at least one first periodic evaluation structure, the wafer data including real-time integrated metrology (IM) data for the at least one first periodic evaluation structure in the first patterned soft-mask layer; establishing a first Multi-Layer-Multi-Step (MLMS) processing sequence, wherein the first MLMS processing sequence comprises a first set of Poly-Etch procedures and is configured to establish a first gate-width control pattern in a first set of the additional layers using the first patterned soft-mask layer; creating a second set of patterned wafers using the first MLMS processing sequence; creating first simulation data for the first MLMS processing sequence using a first Multi-Layer/Multi-Input/Multi-Output (MLMIMO) model for the first MLMS processing sequence, wherein the first MLMIMO model includes a first number (N a ) of first Controlled Variables (CV 1a , CV 2a , . . . CV Na ), a first number (M a ) of first Manipulated Variables (MV 1a , MV 2a , . . . MV Ma ), and a first number (L a ) of first Disturbance Variables (DV 1a , DV 2a , . . . DV La ), wherein (L a , M a , and N a ) are integers greater than one; establishing a second MLMS processing sequence, wherein the second MLMS processing sequence is configured to create a first controlled pattern of metal-gate structures by patterning a second set of the additional layers using the first gate-width control pattern; creating a third set of patterned wafers using the second MLMS processing sequence; creating second simulation data for the second MLMS processing sequence using a second MLMIMO model for the second MLMS processing sequence, wherein the second MLMIMO model includes a second number (N b ) of second Controlled Variables (CV 1b , CV 2b , . . . CV Nb ), a second number (M b ) of second Manipulated Variables (MV 1b , MV 2b , . . . MV Mb ), and a second number (L b ) of second Disturbance Variables (DV 1b , DV 2b , . . . DV Lb ), wherein (L b , M b , and N b ) are integers greater than one; obtaining evaluation data for at least one of the third set of patterned wafers; identifying the third set of patterned wafers as verified wafers when the evaluation data is less than a first metal-gate limit; and performing a corrective action when the evaluation data is not less than the first metal-gate limit.