Patent ID: 7671618

Claim:
An integrated circuit comprising: a chain of analog stages sharing a signal path by each analog stage having a signal input and a signal output, the signal output of a predecessor analog stage in the chain being coupled to the signal input of a successor analog stage in the chain; powering means for powering the analog stages, the powering means comprising a power supply infrastructure and a biasing infrastructure, each analog stage being coupled to a branch of the power supply infrastructure and a branch of the biasing infrastructure; and a test arrangement for testing the analog stages the test arrangement comprising: test data input means, each analog stage having its signal input configurably coupled to the test data input means; test data output means each analog stage having its signal output configurably coupled to the test data output means; selection means located in the powering means for selectively decoupling an analog stage from the powering means; and control means for controlling the selection means and the configurable coupling of an analog stage to the test data input means and the test data output means.