Patent ID: 8381153

Claim:
An integrated circuit (IC) design method comprising: receiving an IC design layout having a main feature; applying a design rule check main feature dissection to the main feature of the IC design layout and generating design rule check sub-portions of the main feature; modifying the design rule check sub-portions of the main feature of the IC design layout according to a design rule check; assigning at least one target to the main feature, the target representing a spatial relationship relative to the main feature; applying a mask rule check main feature dissection to the design rule check sub-portions of the main feature of the IC design layout and generating mask rule check sub-portions of the main feature; identifying at least one of the mask rule check sub-portions as a target mask rule check sub-portion when the at least one target is on or within a border of the at least one of the mask rule check-sub portions and identifying at least another one of the mask rule check sub-portions as a non-target mask rule check sub-portion when the at least one target is not on or within a border of the at least another one of the mask rule check sub-portions; performing an optical proximity correction (OPC) to the mask rule check sub-portions; modifying one of the mask rule check sub-portions based on the OPC; and performing a mask rule check (MRC) to only those mask rule check sub-portions identified as non-target mask rule check sub-portions; modifying only those mask rule check sub-portions identified as non-target mask rule check sub-portions based on the MRC; and after the modifying only those mask rule check sub-portions identified as non-target mask rule check sub-portions based on the MRC, providing the IC design layout in a format accessible by a mask making tool.