Patent ID: 7715221

Claim:
An apparatus for implementing domino static random access memory (SRAM) leakage current reduction comprising: a local SRAM cell group including a predefined number of SRAM cells; said SRAM cells including true and complement bit lines and said true and complement bit lines of said SRAM cells being continuous across said local SRAM cell group; SRAM sleep logic coupled to a plurality of local SRAM cell groups; said SRAM sleep logic receiving a sleep input and said SRAM sleep logic lowering a power supply potential feeding said SRAM cells when said sleep input transitions high; a local evaluation circuit coupled to said true and complement bit lines of a pair of said local SRAM cell groups; said local evaluation circuit receiving precharge signals; and said local evaluation circuit providing an output connected to a global dot line, said global dot line providing a dynamic net used to connect said local evaluation circuit for a given bit; said precharge signals being turned off when said sleep input transitions high; and a write driver providing write data inputs of a data true and a data complement to said local evaluation circuit; said write driver receiving said sleep input; and both said data true and the data complement of said write driver being forced to a respective selected level when said sleep input transitions high to discharge said true and complement bit lines and said global dot line.