Patent ID: 7683696

Claim:
An output buffer disposed between a supply voltage terminal and a ground terminal, the output buffer comprising: a plurality of transistors coupled to an output pad and configured to electrically couple the output pad to the ground terminal; a plurality of well-bias selectors each coupled to an associated one of a plurality of floating wells, the plurality of well-bias selectors configured to select and provide a respective reverse well-bias voltage to the associated one of the plurality of floating wells; and a plurality of voltage dividers each coupled to an associated one of the plurality of well-bias selectors and configured to generate a respective well-bias-reference voltage, wherein the plurality of transistors comprises a first transistor, a second transistor, and a third transistor, wherein the first transistor has a first current carrying terminal coupled to the output pad, a gate terminal coupled to a first node, a second current carrying terminal coupled to a second node, and a body terminal coupled to a first floating well, wherein the second transistor has a first current carrying terminal coupled to the second node, and a gate terminal coupled to the supply voltage, wherein the third transistor has a first current terminal coupled to the second current carrying terminal of the second transistor, a second current carrying terminal coupled to the ground terminal, and a gate terminal receiving an input voltage, wherein body terminals of the second transistor and the third transistor are coupled to the ground terminal.