Patent ID: 7428680

Claim:
An integrated circuit comprising at least one memory comprising cells and a memory built in self test (MBIST) circuit that is programmable by programming instructions following the manufacture of the integrated circuit so as to apply test data for at least one memory test algorithm of the memory to test the memory, the at least one memory test algorithm being determined by the programming of the MBIST circuit, the MBIST circuit comprising: an instruction memory adapted to receive programming instructions; an instruction decoder adapted to receive and decode programming instructions; an address generator responsive to the decoded programming instructions to determine addressing of cells of the memory to which test data is to be applied to perform the at least one testing algorithm, the address generator being responsive to the decoded programming instructions to address cells of the memory so as to perform at least one memory test algorithm having at least one nested loop; a data generator adapted to apply test data to the addressed cells of the memory in accordance with the decoded programming instructions and to provide an output of expected responses from the addressed cells to the applied test data, the memory producing a test results output from the addressed cells in response to the applied test data; and an output analyzer operable to compare expected responses from one or more cells of the memory to the applied test data with the corresponding test results for such one or more cells to the applied test data.