Patent ID: 8547170

Claim:
An integrator circuit device comprising: an amplifier for receiving a signal from a transducer at an input; an integration capacitor between the input and an output of the amplifier and configured to integrate the signal from the transducer to provide a readout; a first switch operatively coupled between the transducer and the input of the amplifier, and configured to selectively stop integration of the signal from the transducer; and a second switch operatively coupled between the transducer and a bias voltage source, and configured to selectively apply the bias voltage to the transducer when the first switch is open, wherein the bias voltage maintains substantially the same voltage across the transducer as when the transducer is connected to the amplifier by the first switch; wherein the first and second switches are configured to provide for a range gating scheme having a fixed gate time within a frame time of searching for said signal, wherein the gate time can be shifted in time between resets of the integration capacitor by subintervals of the fixed gate time.