Patent ID: 7646232

Claim:
A signal adjusting circuit, comprising: a first operational unit, for receiving a digital signal and a first gain value and performing an operation to the digital signal and the first gain value to obtain a first adjusting signal; a second operational unit, for receiving the digital signal and a second gain value and performing an operation to the digital signal and the second gain value to obtain a second adjusting signal; an auto-gain controller (AGC), coupled to the first operational unit, for detecting the first adjusting signal, and generating a third gain value according to the first adjusting signal; a first clamp circuit, coupled between the AGC and the first operational unit, for receiving the third gain value and restricting the third gain value between a first upper limit and a first lower limit, for generating the first gain value and providing the first gain value to the first operational unit; and a second clamp circuit, coupled between the AGC and the second operational unit, for receiving the third gain value and restricting the third gain value between a second upper limit and a second lower limit, for generating the second gain value and providing the second gain value to the second operational unit.