Patent ID: 8901571

Claim:
A semiconductor device comprising: an N-type semiconductor layer made of SiC; a P-type region selectively formed on a surface layer portion of the N-type semiconductor layer; an N-type region formed on a surface layer portion of the P-type region at an interval from a peripheral edge of the P-type region; a gate insulating film formed on the N-type semiconductor layer; and a gate electrode formed on the gate insulating film and opposed to a portion between the peripheral edge of the P-type region and the N-type region, wherein a P-type impurity concentration in a portion of the P-type region having a depth of not more than 100 nm with reference to a center of the gate insulating film in a thickness direction is not more than 1×10 18 cm −3 , and the gate electrode is made of polysilicon doped with a P-type impurity.