Patent ID: 6909314

Claim:
A flip-flop circuit comprising: a master latch gate for receiving an input signal and for outputting the input signal under control of a clock signal and an inverted clock signal; a master latch for receiving the signal output by the master latch gate and for latching the signal output by the master latch gate under control of the clock signal and the inverted clock signal; a slave latch gate for receiving the signal latched by the master latch and for outputting the signal latched by the master latch under control of the clock signal and the inverted clock signal; a slave latch for receiving the signal output by the slave latch gate and for latching the signal output by the slave latch gate under control of a slave latch control signal and an inverted slave latch control signal; and a comparator for receiving the signal latched by the master latch, an inverted signal latched by the master latch, the signal latched by the slave latch and an inverted signal latched by the slave latch, and for generating the slave latch control signal and the inverted slave latch control signal.