Patent ID: 8624767

Claim:
An electronic device for analog-to-digital conversion according to Delta-Sigma modulation comprising at least a first switched capacitor integration stage, a second switched capacitor integration stage and a single-bit comparator, wherein the first switched capacitor integration stage is implemented in a fully differential architecture and comprises: an operational amplifier, a plurality of sets of input sampling capacitors for sampling an analog input voltage and a plurality of sets of reference feedback capacitors for sampling a feedback reference voltage, and wherein the first integration stage is further configured to sample the analog input voltage on a first set of input capacitors out of the plurality of sets of input capacitors during a first portion of a clock cycle and on a second set out of the plurality of sets of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a first set of reference feedback capacitors out of the plurality of sets of reference feedback capacitors during the first portion of the clock cycle and on a second set of reference feedback capacitors out of the plurality of sets of reference feedback capacitors during the second portion of the clock cycle and wherein the first set of reference feedback capacitors and the second set of reference feedback capacitors are randomly selected out of the plurality of sets of reference feedback capacitors from clock cycle to clock cycle.