Patent ID: RE43204

Claim:
A data transmission process with auto-synchronized correcting code, comprising: defining a timing of bits of the data, to be transmitted, by a clock signal and forming synchronization management signals comprising: a symbol clock signal m number of times less fast than the clock signal, where m is an integer, and m bits constituting an information symbol, a symbol synchronization signal capable of designating the first symbol of a packet, and a data acquisition interruption signal intervening every K number of symbols, where K is a pre-set integer; inserting a header before a first group of K symbols and inserting a second group of R symbols after said first group, the second group of R symbols comprising a correcting code corresponding to the K symbols of the first group, R being a pre-set integer dependent on a correcting code type used, the first and second groups of(R+K) symbols forming a packet, and the header being a header specific to this packet, under control of the data acquisition interrupting signal; and modulating and transmitting each packet with its header; demodulating the signal received and extracting the clock signal; implementing a header search process in the demodulated signal and, when the header is detected, inhibiting the header search process and generating a symbol synchronization symbol; processing the received packet so as to correct any erroneous symbols of the first group by the correcting code of the second group and reactivating the header search process after each packet processing, under the control of the symbol clock and symbol synchronization signals; and retrieving, from the corrected symbols, the transmitted data.