Patent ID: 7688930

Claim:
A circuit, comprising: a phase-locked loop (PLL) circuit; an electrical fuse (eFuse) array coupled to the PLL circuit; a control unit coupled to the eFuse array, wherein the control unit comprises a power-on reset (POR) engine and an eFuse controller coupled to the POR engine; and a latch coupled to the control unit, wherein: the control unit has logic that provides control signals to the eFuse array to cause the eFuse array to provide configuration data to the PLL circuit to thereby configure the PLL circuit to operate with a particular set of characteristics specified by the configuration data, the PLL circuit remains operational after configuring by the configuration data and operates on an input signal based on the particular set of characteristics specified by the configuration data provided by the eFuse array to generate an output signal, the POR engine includes logic that, in response to receiving a reset signal, sends a control signal to the eFuse controller to sense data values from eFuses in the eFuse array to thereby generate sensed data, the sensed data from the eFuses in the eFuse array are provided to the latch, and the latch provides the sensed data to the PLL circuit.