Patent ID: 7443203

Claim:
An impedance adjustment circuit comprising: a simulation circuit simulating a buffer circuit of an integrated circuit device, said simulation circuit having an input that receives a control signal that controls a resistance of the buffer circuit and an output that outputs a simulation result; a comparison circuit having three differential circuits that each compare a same reference electric potential to a same electric potential that corresponds to the simulation result and a majority circuit that provides a comparison result by selecting the majority from among individual comparison results produced by said three differential circuits; and a control circuit with an output that outputs the control signal to said simulation circuit and to the buffer circuit based on the comparison result, wherein said majority circuit has first to third 2-input AND gates, and a 3-input AND gate; the output of first said differential circuit being input to one of the input terminals of said first 2-input AND gate, and the output of second said differential circuit being input to the other input terminal; the output of said first differential circuit being input to one of the input terminals of said second 2-input AND gate, and the output of third said differential circuit being input to the other input terminal; the output of said third differential circuit being input to one of the input terminals of said third 2-input AND gate, and the output of said second differential circuit being input to the other input terminal; and the outputs of said first to third 2-input AND gates being input to the input terminals, respectively, of said 3-input AND gate.