Patent ID: 7078332

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate including conductive regions in a cell region and a gate electrode and conductive regions in a peripheral region; forming a first interlayer insulation film and a first etch barrier film on the semiconductor substrate; forming a plurality of contact holes at once by patterning the first interlayer insulation film and the first etch barrier film to expose the conductive regions in the cell region and the gate electrode and the conductive regions in the peripheral region; performing an ion implantation to increase an impurity concentration of the conductive regions in the cell region and the gate electrode and the conductive regions in the peripheral region; filling a first metal material in the plurality of contact holes and forming a plurality of contact plugs; forming a second interlayer insulation film, a second etch barrier film and a third interlayer insulation film over a resulting structure including the plurality of contact plugs; forming a plurality of metal lines by filling a second metal material, wherein the plurality of metal lines pass through the third interlayer insulation film, the second etch barrier film and the second interlayer insulation film and contact the plurality of contact plugs; forming a fourth interlayer insulation film over a resulting structure including the plurality of metal lines and the third interlayer insulation film; forming a plurality of metal line contact holes by patterning the fourth interlayer insulation film; and forming a plurality of metal line contact plugs in the plurality of metal line contact holes by filling a third metal material in the metal line contact holes.