Patent ID: 7103110

Claim:
A dual phase pulse modulation (DPPM) encoder circuit, comprising: input means for receiving data words; means for subdividing data words into an ordered sequence of groups of M data bits each; means, coupled to receive successive M-bit groups from the subdividing means, for specifying successive time durations corresponding to the received groups, each of a possible 2 M data values of an M-bit group corresponding to a unique one of 2 M distinct time durations, wherein the means for specifying successive time durations comprises a state machine configured to output a control signal onto a control bus that indicates selected signal pulse transition times relative to a transition of a system clock, said state machine being responsive to each successive received group of M data bits for incrementing the selected signal pulse transition times by an amount of the time duration corresponding to that received group; and signal generating means, configured to be controlled by said means for specifying successive time durations, for producing alternately high and low signal pulses having pulse durations that substantially match the specified time durations.