Patent ID: 7679105

Claim:
A hetero-junction bipolar transistor comprising: a semi-insulating compound substrate; a sub-collector layer formed on the semi-insulating compound substrate; a pair of collector electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the sub-collector layer; a collector layer and a base layer disposed between the collector electrodes; a pair of base electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the base layer; an emitter layer stack disposed between the base electrodes; and an emitter electrode that is formed on the emitter layer stack, wherein the emitter electrode comprises a lower portion and an upper portion which is disposed on the lower portion and the width of the upper portion is wider than the width of the lower portion and the width of the lower portion of the line width of the emitter electrode is wider than the width of the emitter layer stack, and wherein both sidewalls of the emitter electrode are respectively aligned with inner walls of the pair of base electrodes, and sidewalls of the collector layer and the base layer are located between outer sidewalls of the pair of base electrodes.