Patent ID: 7215102

Claim:
A multi-phase power converter architecture comprising: a plurality of N+1 regulators, where N is greater than or equal to one, including a first regulator and N additional regulators coupled in a cascaded configuration; said first regulator including a programmable delay circuit coupled to receive a clock signal from a controller circuit, said programmable delay circuit providing a digital start output signal to a next downstream regulator after a predetermined delay; and a pulse width modulator (PWM) control circuit that controls a PWM output in accordance with said clock signal and a prescribed output condition; a respective one of said N additional regulators including a programmable delay circuit coupled to receive a digital start output signal from a next upstream regulator, said delay circuit providing a digital start output signal to a next downstream regulator after a predetermined delay; and a PWM control circuit that controls a PWM output in accordance with said digital start signal and a prescribed output condition; a plurality of N+1 switching circuits, each having an input coupled to a PWM output of one of said plurality of regulators, an output for driving a common DC output voltage, and a sense output provided to a PWM control circuit of said one of said plurality of regulators; and a controller that senses said DC output voltage and provides a compensation signal to said PWM control circuits of said plurality of regulators, and which supplies said clock signal to said first regulator.