Patent ID: 7532661

Claim:
A circuit for a wireless receiver to despread a 128-length hierarchical sequence, the circuit comprising: a first despreader operable using one of a 16-length sequence and an 8-length sequence to despread a received signal, the received signal defined as a fixed frequency interleaved transmission having one of a first preamble, a second preamble, and a third preamble, the 16-length sequence selected from a group consisting of, for the received signal containing the first preamble, a first 16-length sequence proportional to a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 1 1 1 −1 1 1 1 −1 1 −1 1 1 −1 1 −1 −1 and, for the received signal containing the second preamble, a second 16-length sequence proportional to d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 d 16 1 1 −1 1 −1 1 −1 1 1 −1 1 1 1 1 −1 −1 and, for the received signal containing the third preamble, a third 16-length sequence proportional to g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 g 10 g 11 g 12 g 13 g 14 g 15 g 16 1 1 −1 −1 −1 −1 1 −1 −1 1 −1 1 −1 1 −1 −1 and, wherein the 8-length sequence selected from a group consisting of, for the received signal containing the first preamble, a first 8-length sequence proportional to b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 1 1 1 −1 −1 −1 1 −1 and, for the received signal containing the second preamble, a second 8-length sequence proportional to e 1 e 2 e 3 e 4 e 5 e 6 e 7 e 8 1 −1 1 1 1 −1 −1 −1 and, for the received signal containing the second preamble, a second 8-length sequence proportional to h 1 h 2 h 3 h 4 h 5 h 6 h 7 h 8 1 1 1 −1 −1 −1 1 −1 a second despreader using the other of the 16-length sequence and the 8-length sequence to despread the output of the first despreader to form the 128-length hierarchical sequence.