Patent ID: 7986554

Claim:
A method of operating a non-volatile memory device having an array of memory cells formed along wordlines and read and write circuits for operating on addressable pages of memory cells on a given wordline in parallel, wherein each memory cell is capable of storing three or more bits and the write circuitry can store a corresponding number of logical pages on a given physical page along a wordline, the method comprising: concurrently writing in a multi-state write more than one, but less than all, of the logical pages that a physical page can store in a first programming operation on a first wordline; subsequently concurrently writing in a multi-state write more than one, but less than all, of the logical pages that a physical page can store in a first programming operation on a second wordline adjacent to the first wordline; and subsequently writing at least one logical page in a second programming operation on the first wordline.