Patent ID: 7451369

Claim:
An integrated circuit (IC), comprising: a plurality of logic elements arranged in rows and columns, each of the logic elements comprising at least one data storage element; a data distribution system coupling the data storage elements together in series to form a boundary scan chain, wherein the boundary scan chain traverses in order a first data storage element through a last data storage element in a first column, followed in order by a first data storage element through a last data storage element in a second column; and a clock distribution system coupled to each of the data storage elements in the boundary scan chain, wherein the clock distribution system is coupled to provide a boundary scan clock signal to the first data storage element in the second column prior to providing the boundary scan clock signal to the first data storage element in the first column, and wherein, for each column, the clock distribution system is further coupled to provide the boundary scan clock signal to the first data storage element in the column prior to providing the boundary scan clock signal to the last data storage element in the column.