Patent ID: 8155211

Claim:
A transcoder comprising: a memory having multiple sets of runs buffered therein, and multiple sets of levels buffered therein, wherein the multiple sets of runs and multiple sets of levels define multiple sets of run-level pairs of a given frame of a stream of frames; a processor in communication with the memory, the processor adapted to process in the run-level domain the multiple sets of run-level pairs of the given frame using at least the sets of runs, and, for a given set run-level pairs of the multiple sets of run-level pairs, to selectively zero levels of the given set of run-level pairs using the frequencies of the levels of the given set of run-level pairs; and a vector length encoder in communication with the processor, the vector length encoder adapted to receive the processed multiple sets of run-level pairs of an inter-coded frame and encode the multiple sets of run-level pairs into bits for a second bit stream, wherein the bit size of the given frame in the second bit stream is smaller than the bit size of the given frame in the first bit stream, wherein the bit size of the given frame corresponds to a total number of bits in the given frame.