Patent ID: 7563664

Claim:
A method of manufacturing a semiconductor memory device comprising: forming a first insulating film on a semiconductor substrate having a memory cell region of a NAND type flash memory and a peripheral circuit region; forming a first electrode material layer on the first insulating film; forming an element separating region in the first electrode material layer, the first insulating film and the semiconductor substrate, the element separating region being formed of an element separating insulating film; forming a second insulating film on the first electrode material layer in the memory cell region; forming a second electrode material layer on the second insulating film and the first electrode material layer; selectively removing the first and second electrode material layers and the second insulating film to form first gate electrodes having first and second conductive layers in the memory cell region and second gate electrodes having third and fourth conductive layers in the peripheral circuit region, the first and third conductive layers being formed of the first electrode material layer, and the second and fourth conductive layers being formed of the second electrode material layer; forming first diffusion layers between the first gate electrodes in the semiconductor substrate, each of the first diffusion layers being common to the first gate electrodes adjacent thereto; forming third insulating films on the first diffusion layers and fourth insulating films on side surfaces of the second gate electrodes, the first diffusion layers being covered with the third insulating films, the third insulating film completely filling a clearance between the first gate electrodes; forming second diffusion layers between the second gate electrodes in the semiconductor substrate; removing the first insulating film on the second diffusion layers and a boundary region between the memory cell region and the peripheral circuit region to separate the first insulating film in the memory cell region from the first insulating film in the peripheral circuit region in a direction of a channel length, the first insulating film in the memory cell region continuing in the direction of the channel length, and the first insulating film in the peripheral circuit region being divided where each of the second gate electrodes is formed in the direction of the channel length; and forming first, second and third silicide films only on the second conductive layer, the fourth conductive layer and the second diffusion layers, respectively.