Patent ID: 7005698

Claim:
A split gate flash memory cell, comprising: a substrate having a trench; a conductive line disposed in a lower portion of the trench and insulated from the substrate serving as a source line; a source region formed in the substrate adjacent to an upper portion of the conductive line; an insulating layer disposed on the conductive line; a conductive spacer disposed on an upper sidewall portion of the trench serving as a floating gate, protruding and insulated from the substrate; a first insulating stud disposed on the insulating layer, with the top thereof higher than that of the conductive spacer; a first conductive layer disposed over the substrate adjacent to the conductive spacer, serving as a control gate, the first conductive layer insulated from the conductive spacer and the substrate, respectively; a first insulating spacer disposed on the sidewall of the insulating stud to cover the first conductive layer; and a drain region formed in the substrate adjacent to the first conductive layer.