Patent ID: 8659947

Claim:
A nonvolatile semiconductor memory device, comprising: a plurality of memory units each including a plurality of memory transistors, a first transistor, and a second transistor, the plurality of memory units including a first memory unit and a second memory unit; a first line electrically connected to a first end of the first memory unit and a first end of the second memory unit; a second line electrically connected to a second end of the first memory unit, the second line being connected to the first transistor in the first memory unit; and a controller configured to perform a program operation, the program operation including a first phase, a second phase, and a third phase, the controller configured in the first phase to apply a first pass voltage to gates of a selected memory transistor and unselected memory transistors in the first memory unit, to apply a first voltage to a gate of the first transistor, and to apply a second voltage lower than the first voltage to the second line, the controller configured in the second phase to apply a third voltage to a gate of the second transistor, to apply a fourth voltage to the first line, the third voltage being higher than the fourth voltage, and to apply the first pass voltage to gates of the selected memory transistor and the unselected memory transistors in the first memory unit, the controller in the third phase configured to apply the first pass voltage to gate of the unselected memory transistors in the first memory unit, to apply a program voltage to gate of the selected memory transistor in the first memory unit, to apply the third voltage to the gate of the second transistor, and to apply the fourth voltage to the first line.