Patent ID: 8817549

Claim:
A semiconductor memory device comprising: a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed as a density of 2^K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, an entire density of the memory regions corresponding to an interim density, wherein the memory regions include: a first memory region having a plurality of first volatile memory cells that are formed as a density of 2^M bits, where M is an integer greater than or equal to 0, and a plurality of first I/O terminals for inputting and outputting data of the first volatile memory cells; and a second memory region having a plurality of second volatile memory cells that are formed as a density of 2^N bits, where N is an integer greater than or equal to 0 and N is different from M, and a plurality of second I/O terminals for inputting and outputting data of the second volatile memory cells, wherein a number of the first I/O terminals and/or a number of the second I/O terminals can be expressed as 2^L, where L is an integer greater than or equal to 0, respectively; and at least one peripheral region configured to control a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on an externally input command and address.