Patent ID: 7024503

Claim:
A link bus between control chipsets comprising; a first address/data (AD) bus for transmitting addresses and data unidirectionally in a first unidirectional mode and in both directions in a first bidirectional mode; a second address/data bus for transmitting addresses and data unidirectionally in a second unidirectional mode and in both directions in a second bidirectional mode; a first control chip coupled to said first address/data bus and said second address/data bus, said first control chip controlling transmission on only said first address/data bus in said first unidirectional mode and controlling transmission on both said first address/data bus in said first bidirectional mode; a second control chip coupled to said second address/data bus and said first address/data bus, said second control chip controlling transmission on only said second address/data bus in said second unidirectional mode and controlling transmission on both said second address/data bus and said first address/data bus in said second bidirectional mode; a first command signal line for transmitting a first request signal to said second control chip from said first control chip, wherein said first control chip undergoes a transition from said first unidirectional mode to said first bidirectional mode only upon said second control chip receiving said first request signal while not transmitting on said second address/data bus; and a second command signal line for transmitting a second request signal from said second control chip to said first control chip, wherein said second control chip undergoes a transition from said second unidirectional mode to said second bidirectional mode only upon said first control chip receiving said second request signal while not transmitting on said first address/data bus.