Patent ID: 7791128

Claim:
A non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a floating gate stack and a control gate; the semiconductor channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the floating gate stack being positioned in contact with one sidewall portion of the fin-shaped semiconductor channel region and between the source and drain regions, and being substantially perpendicular to the length direction (X) of the fin-shaped semiconductor channel region; the control gate being in contact with the floating gate stack, wherein an access gate is provided adjacent to the other sidewall portion of the fin-shaped semiconductor channel region and separated therefrom by only an intermediate gate oxide layer, and wherein the floating gate stack comprises a set of layers which are parallel to the plane of the sidewall portion of the fin-shaped semiconductor channel region.