Patent ID: 7276416

Claim:
A method of forming a vertical transistor, comprising: providing material over a monocrystalline surface and including an opening in the material extending to the monocrystalline surface; epitaxially growing a first silicon-comprising layer from the monocrystalline surface within the opening; after growing the first silicon-comprising layer, widening the opening effective to expose an additional monocrystalline surface; epitaxially growing a second silicon-comprising layer from the additional monocrystalline surface within the widened opening and from the first silicon-comprising layer; forming a gate dielectric layer of the vertical transistor over the second silicon-comprising layer, and a gate of the vertical transistor over the gate dielectric layer; and providing the second silicon-comprising layer to comprise at least a part of both a channel region of the vertical transistor and a source/drain region of the vertical transistor.