Patent ID: 8230247

Claim:
A platform system comprising: a processor in a sleep state, the processor coupled to a platform control hub, an external voltage regulator and an environment controller; components in the processor powered by a sustain power plane including: a cache memory in which a processor context is stored, a wake logic for handling processor wakeup and context restore, an I/O interface between the processor and the platform control hub, external voltage regulator and environment controller, and an electrostatic discharge clamp; wherein the processor enters a connected standby sleep state upon: receiving a timer signal from the wake logic via the I/O interface; gating a clock operating in the processor; powering the cache memory in which the processor context is stored with a dedicated power plane separate from the sustain power plane; powering down the remaining components powered by the sustain power plane and powering down the sustain power plane; redirecting wakeup sources for handling processor wakeup and context restore to the platform control hub; and transferring architectural functions of the processor to the platform control hub, including operation of a time stamp counter.