Patent ID: 7859026

Claim:
A semiconductor memory device comprising: a semiconductor substrate having a surface; a trench etched into the body of the substrate extending away from the surface and having a first wall and a second wall extending into the body of the substrate and having a bottom at the extremity of the first wall and the second wall within the semiconductor substrate; a first drain region and a second drain region formed in the semiconductor substrate along the first wall and a third drain region and a fourth drain region formed in the semiconductor substrate along the second wall, each drain region extending from proximate the surface toward the bottom wherein the first, second, third and forth drain regions are formed along the first and second walls in the length direction of the trench; a first source region formed in the semiconductor substrate along the first wall between and spaced apart from the first drain region and the second drain region and a second source region formed in the semiconductor substrate along the second wall between and spaced apart from the third drain region and the fourth drain region, each source region extending from proximate the surface toward the bottom; a first channel region formed in the semiconductor substrate along the first wall between the first drain and the first source, a second channel region formed in the semiconductor substrate along the first wall between the first source and the second drain, a third channel region formed in the semiconductor substrate along the second wall between the third drain region and the second source, and a fourth channel region formed in the semiconductor substrate along the second wall between the second source region and the fourth drain; a first gate electrode overlying the first channel, a second gate electrode overlying the second channel, a third gate electrode overlying the third channel, and a fourth gate electrode overlying the fourth channel; a first word line coupled to the first gate electrode and the second gate electrode and a second word line coupled to the third gate electrode and the fourth gate electrode; a first bit line coupled to the first drain region and the third drain region and a second bit line coupled to the second drain region and the fourth drain region; a first isolation oxide grown at the bottom of the trench; and a second isolation oxide grown on the first wall between the first channel and the second channel and a third isolation oxide grown on the second wall between the third channel and the fourth channel.