Patent ID: 8762651

Claim:
A method of maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer comprising a plurality of compute nodes, each compute node comprising at least one processor operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among the compute nodes, each cache controller coupled for data communications to cache controllers on other compute nodes, the method comprising: based on a cache miss of a cache line on a first one of the compute nodes, broadcasting by the first compute node to other compute nodes a request for the cache line; based on receiving the broadcast request, determining whether at least two of the other compute nodes has a correct copy of the cache line in the same cache line state, and based on two of the other compute nodes having a correct copy of the cache line in the same cache line state: selecting, by the at least two of the other compute nodes, in dependence upon an identifier of the each node having a correct copy of the cache line in the same cache line state which of the compute nodes is to transmit the correct copy of the cache line to the first node, the identifier comprises an integer value unique to each node, each node retains at least one identifier value that identifies a node previously selected to be a node to transmit a correct copy of a cache line, wherein selecting which of the compute nodes is to transmit the correct copy of the cache line to the first node includes selecting in dependence upon the integer values and the retained identifier value which compute node is to transmit the correct copy; and transmitting from the selected compute node to the first node the correct copy of the cache line.