Patent ID: 7454601

Claim:
A method for providing an instruction, the method comprising: decoding an instruction with a decoder in a processor device as an N-wide add-compare-select instruction, said decoding operation comprises decoding said N-wide add-compare-select instruction as a quad add-compare-select instruction, said quad add-compare-select instruction having a plurality of operands; selecting a plurality of branch metrics; combining the plurality of branch metrics with a plurality of source operands wherein one of said plurality of branch metrics is combined with at least two source operands of said instruction; outputting a pair of maximum values of values from said combining operation; and updating a plurality of control registers, if requested by said N-wide add-compare-select instruction wherein said updating operation comprises: rotating an operand selection register (OSR) four bits to the right; and rotating a polarity setting register (PSR) two bits to the right.