Patent ID: 7522686

Claim:
A burst mode clock data recovery circuit for extracting clock information and data information from transmitted data to process data synchronized with clock, the circuit comprising: a bit-rate corrector generating an inversed signal at every half cycle of the clock when transition of input data is generated according to a voltage controlled oscillator (“VCO”) control voltage and a digital code; a first gated-voltage control oscillator generating an output clock according to the inversed signal, the VCO control voltage and the digital code; and a bit-rate detector generating the digital code according to the VCO control voltage and the inversed signal, wherein the inversed signal maintains a logic-high value when the voltage value of the input data is continuously a DC voltage, wherein a delay time of a delay circuit contained in the first gate-voltage control oscillator and the bit-rate corrector is adjusted based on the VCO control voltage and the digital code, and wherein the VCO control voltage is applied by a phase lock loop (“PLL”) which locks a predetermined reference frequency signal.