Patent ID: 8530301

Claim:
A method of protecting an integrated circuit from an electrostatic discharge (ESD) event, said integrated circuit comprising a functional circuit and an ESD protection cell connected to a terminal of said functional circuit, said functional circuit and said ESD circuit formed in or on a substrate having a p type layer; said protection cell comprising an Nwell formed in said p type layer, a p doped region formed in said Nwell defining with said Nwell an Nwell diode comprising an anode and a cathode, and a DeNMOS transistor formed in or on said p type layer comprising an n type source, an n type drain formed within said Nwell and a channel region comprising said Nwell and a p type region between said source and said drain, wherein said terminal is coupled to said p doped region defining said Nwell diode and said Nwell diode is connected in series with a current path from said drain to said source of said DeNMOS transistor; and said method comprising: said terminal and said p doped region of said Nwell diode receiving an electrostatic discharge during said ESD event; and said Nwell diode generating an ESD discharge current responsive to said ESD event, wherein a current related to said ESD discharge current flows into said p type layer raising a local potential of said p type layer proximate to said protection cell.