Patent ID: 7462558

Claim:
A method for fabricating a circuit component, comprising: providing a wafer comprising a silicon substrate, a MOS transistor in or on said silicon substrate, a metallization structure over said silicon substrate, wherein said metallization structure comprises a first thin-film circuit layer and a second thin-film circuit layer over said first thin-film circuit layer, a dielectric layer between said first and second thin-film circuit layers, and a passivation layer over said metallization structure and over said dielectric layer; forming a polymer layer on said passivation layer and over said wafer, wherein said polymer layer has a thickness between 2 and 50 micrometers and greater than that of said passivation layer; sputtering a titanium-containing layer on said polymer layer and over said wafer; sputtering a first gold layer on said titanium-containing layer and over said wafer; forming a first photoresist layer on said first gold layer and over said wafer, wherein a first opening in said first photoresist layer exposes said first gold layer; electroplating a second gold layer over said wafer and on said first gold layer exposed by said first opening; forming a second photoresist layer on said second gold layer and over said wafer, wherein a second opening in said second photoresist layer exposes said second gold layer; electroplating a third gold layer over said wafer and on said second gold layer exposed by said second opening; removing said second photoresist layer; removing said first photoresist layer; and after said electroplating said third gold layer, removing said first gold layer not under said second gold layer and removing said titanium-containing layer not under said second gold layer.