Patent ID: 7521976

Claim:
A prescaler circuit comprising: a latch comprising: a first clocked differential pair comprising input terminals coupled to a data input of the latch, a first output terminal coupled to a first output of the latch, and a second output terminal coupled to a second output of the latch; a second clocked differential pair with a first input terminal coupled to the second output of the latch, a second input terminal coupled to the first output of the latch; a first output terminal coupled to the first output of the latch, and a second output terminal coupled to the second output of the latch; a first shunt peaked active load circuit coupled to the first output of the latch; a second shunt peaked active load circuit connected to the second output of the latch; a replica bias circuit to control a voltage of the shunt peaked active loads, wherein the replica bias circuit comprises a transistor stack to replicate a voltage drop across the shunt peaked active loads of the latch, wherein the shunt peaked active loads comprise a resistor and a transistor; and wherein the replica bias circuit is configured to generate a voltage at the resistors that is higher than a supply voltage of the latch; and a filter network coupled between the replica bias circuit and the resistors.