Patent ID: 8633874

Claim:
A display device, comprising: luminescence pixels arranged in rows and columns; gate lines and reset lines, each of the gate lines and each of the reset lines corresponding to one of the rows of the luminescence pixels; and signal lines, each corresponding to one of the columns of the luminescence pixels, wherein each of the luminescence pixels includes: a switching transistor including one of a switching source and a switching drain connected to a corresponding signal line of the signal lines, and a switching gate connected to a corresponding gate line of the gate lines; a luminescence element for producing luminescence according to a flow of current; a drive transistor including a drive gate connected to an other of the switching source and the switching drain, one of a drive source and a drive drain being connected to the luminescence element for supplying current to the luminescence element, an other of the drive source and the drive drain being connected to a power source during supply of current to the luminescence element; a reset transistor including a reset gate connected to a corresponding reset line of the reset lines, one of a reset source and a reset drain connected to the one of the drive source and the drive drain, and an other of the reset source and the reset drain connected to the corresponding gate line; and a capacitor including a first terminal connected to the drive gate, and a second terminal connected to the one of the drive source and the drive drain, the display device further comprises: a controller configured to: supply an ON signal and an OFF signal to each of the switching transistor and the reset transistor to switch ON and OFF each of the switching transistor and the reset transistor; supply the ON signal to the corresponding gate line to which the other of the reset source and the reset drain is connected to place the corresponding gate line in a first active state in which the switching transistor is switched ON, while supplying the OFF signal to the corresponding reset line to place the corresponding reset line in a first inactive state in which the reset transistor is switched OFF, to set a predetermined reference voltage to the first terminal of the capacitor via the corresponding signal line; and after the predetermined reference voltage is set to the first terminal of the capacitor, supply the OFF signal to the corresponding gate line to place the corresponding gate line in a second inactive state in which the switching transistor is switched OFF, while supplying the ON signal to the corresponding reset line to place the corresponding reset line in a second active state in which the reset transistor is switched ON, to set the second terminal of the capacitor to a low level voltage.