Patent ID: 7190174

Claim:
A timing clock calibration method for use in a test apparatus including: a timing clock generating section for generating a timing clock indicative of a timing at which a test signal is to be fed to a device under test; a shift clock generating section for generating a shift clock used for calibrating the timing clock generating section by using a phase synchronization circuit; and a timing clock and shift clock phase comparing section for comparing a phase of the shift clock generated by the shift clock generating section and a phase of the timing clock generated by the timing clock generating section, for calibrating the timing clock generating section comprising: a shift clock calibration step for, while changing a shift amount of an edge of the shift clock, detecting an edge of the timing clock more than once by using the shift clock to calibrate the shift amount of the edge of the shift clock by the shift clock generating section by using a period of the timing clock as a reference; a shift clock shifting step in which the shift clock generating section calibrated in the shift clock calibration step shifts and generates the edge of the shift clock by a predetermined shift amount; and a timing clock calibration step for, while changing a delay amount of the timing clock, detecting the edge of the shift clock shifted by the predetermined shift amount in the shift clock shifting step by using the timing clock to calibrate a required delay amount for delaying the timing clock by time corresponding to the predetermined shift amount.