Patent ID: 6887761

Claim:
A method for fabricating a vertical semiconductor structure, the method comprising the steps of: providing a semiconductor substrate comprising a semiconductor material; forming a deep trench in the semiconductor substrate; depositing a first gate dielectric layer on a side wall of the deep trench; filling the deep trench with a filling material; forming a first source/drain region and a second source/drain region around and along the depth of the deep trench; forming first and second shallow trench isolation regions sandwiching the deep trench in an active region, the first and second shallow trench isolation regions abutting the active region via first and second abutting surfaces, respectively, wherein the first and second abutting surfaces are parallel to each other and are perpendicular to an orientation plane of the semiconductor material of the substrate; removing the first gate dielectric layer so as to expose the semiconductor material in the deep trench to the atmosphere; chemically etching the exposed semiconductor material in the deep trench; depositing a second gate dielectric layer on a side wall of the deep trench; and forming a gate terminal for the vertical semiconductor structure in the deep trench.