Patent ID: 8378414

Claim:
An integrated circuit (IC) device, comprising: a substrate; a fin on an uppermost portion of the substrate, the fin comprising a crystalline semiconducting material extending upwards by a first height from the uppermost portion of the substrate, the fin having a given width and length, the fin further comprising: a source region, the source region being doped with a first dopant which supports a first type of majority carrier; a drain region, the drain region being doped with a second dopant which supports the first type of majority carrier; a channel region, the channel region being interposed between the source region and the drain region, wherein the channel region and the source region and the drain region are aligned alone a line substantially parallel to a { 100 } plane of the crystalline semiconducting material of the fin; and a gate region, the gate region being formed on at least three sides of the channel region, the gate region being separated from the channel region by a thin dielectric layer, the gate region being doped with a dopant which supports a second type of majority carrier; and an etched dielectric fill layer disposed on both sides of the fin along the length of the fin, the etched dielectric fill layer extending by a second height from the uppermost portion of the substrate, the second height being shorter than the first height, wherein the gate region is formed over the channel region and the etched dielectric fill layer.