Patent ID: 7232725

Claim:
A method of fabricating a split gate memory device, comprising: forming a gate insulating layer on a substrate; forming a floating gate layer on the gate insulating layer; patterning a predetermined region of the floating gate layer to form a floating gate pattern; forming a capping insulating layer on portions of the floating gate pattern; forming a tunnel insulating layer and a control gate layer on the capping insulating layer; etching the control gate layer and the tunnel insulating layer until the capping insulating layer is exposed to form a pair of control gates with the tunnel insulating layer interposed between the control gates and both sidewalls of the floating gate pattern and the capping insulating layer; selectively etching the exposed capping insulating layer, the floating gate pattern, and the gate insulating layer until a portion of the substrate is exposed, thereby forming a pair of floating gates; forming a common source region by implanting ions into the exposed portion of the substrate; and forming drain regions by implanting ions into a portion of the substrate adjoining the control gates.