Patent ID: 7883952

Claim:
A method comprising: forming a gate on a semiconductor substrate; and then sequentially stacking a first dielectric film and a second dielectric film on the semiconductor substrate; and then forming a first spacer comprising a first dielectric film pattern and a second dielectric film pattern on sidewalls of the gate by performing a first etching process; and then forming source and drain areas in the semiconductor substrate; and then removing the second dielectric film; and then sequentially stacking a third dielectric film and a fourth dielectric film on the semiconductor substrate; and then forming a second spacer comprising the first dielectric pattern and a third dielectric pattern on the sidewalls of the gate by performing a second etching process, wherein forming the second spacer comprises performing the second etching process removing a portion of the third dielectric film and the entire fourth dielectric film; and then forming an interlayer dielectric film on the semiconductor substrate including the gate and the first spacer.