Patent ID: 8797200

Claim:
A delta-sigma analog-to-digital converter for generating a digital signal as a function of a first analog signal and a clock signal having a first phase and a second phase, the converter comprising: a first branch operative to apply input resistance to a second analog input signal; a feedback branch operative to feed back a third analog reference signal, the feedback branch including a digital-to-analog converter configured to generate the third analog reference signal as a function of the digital signal; a loop filter configured to generate an integrated signal as a function of the first analog signal, the loop filter being coupled to a branch point of the first branch and the feedback branch, for receiving the first analog signal; and a quantizer configured to generate the digital signal as a function of the integrated signal, the quantizer being coupled to the loop filter for receiving the integrated signal and coupled to the feedback branch for delivering the digital signal to the digital-to-analog converter; and a switch arranged on the first branch between the input resistance and the branch point, the switch being timely correlated with an output switch of the digital-to-analog converter in order for the delta-sigma analog-to-digital converter to switch between at least two configurations, comprising: a first configuration in which the input resistance is connected and the output of the digital-to-analog converter is disconnected during the first phase of clock signal; and a second configuration in which the input resistance is disconnected and the output of the digital-to-analog converter is connected during the second phase of clock signal, the first analog signal being equal to either the second analog input signal during the first phase of clock signal or the third analog reference signal during the second phase of clock signal; wherein the input resistance is fixed at an electrical resistance value which depends on a ratio between a duration of the first phase and a duration of the second phase of the clock signal, such that a shorter duration of the first phase yields a lower electrical resistance value.