Patent ID: 7434007

Claim:
A data processing apparatus comprising: a processing unit operable to issue an access request seeking access to a data value; a hierarchy of cache memories operable to store data values for access by the processing unit, the hierarchy of cache memories comprising at least an n-th level cache memory and an n+1-th level cache memory which at least in part employ exclusive behaviour with respect to each other; each cache memory comprising a plurality of cache lines, at least one dirty value being associated with each cache line, each dirty value being settable to indicate that at least one data value held in the associated cache line is more up-to-date than a corresponding data value stored in a main memory; when employing exclusive behaviour the n-th level cache memory being operable, on eviction of a cache line from the n-th level cache memory to the n+1-th level cache memory, to additionally pass an indication of the at least one associated dirty value from the n-th level cache memory to the n+1-th level cache memory, for use in selecting the at least one dirty value associated with the cache line in the n+1-th level cache memory that is to store the data values of the cache line evicted from the n-th level cache memory thereby facilitating a reduction in evictions from the n+1-th level cache memory.