Patent ID: 7314805

Claim:
A method of fabricating a semiconductor device, comprising steps of: (a) forming a gate electrode of an n-channel MISFET over a main surface of a first semiconductor region of p-type conductivity formed in a semiconductor body and a gate electrode of a p-channel MISFET over a main surface of a second semiconductor region of n-type conductivity formed in said semiconductor body; (b) after said step (a), implanting ions in said first semiconductor region to form a third semiconductor region of n-type conductivity; (c) after said step (a), implanting ions in said second semiconductor region to form a fourth semiconductor region of p-type conductivity; (d) after said steps (b) and (c), forming side wall spacers on side surfaces of said gate electrodes; (e) after said step (d), implanting ions in said first semiconductor region to form a fifth semiconductor region of n-type conductivity; (f) after said step (d), implanting ions in said first semiconductor region to form a sixth semiconductor region of n-type conductivity; (g) after said step (d), implanting ions in said second semiconductor region to form a seventh semiconductor region of p-type conductivity; (h) after said step (d), implanting ions in said second semiconductor region to form an eighth semiconductor region of p-type conductivity; and (i) after said steps (e), (f), (g) and (h), forming a cobalt silicide layer in said fifth semiconductor region and a cobalt silicide layer in said seventh semiconductor region, wherein a dose amount in said step (e) is greater than a dose amount in said step (f) such that an impurity concentration of said fifth semiconductor region is greater than an impurity concentration of said sixth semiconductor region, wherein a dose amount in said step (g) is greater than a dose amount in said step (h) such that an impurity concentration of said seventh semiconductor region is greater than an impurity concentration of said eighth semiconductor region, wherein a depth of said sixth semiconductor region is greater than a depth of said fifth semiconductor region, wherein a depth of said eighth semiconductor region is greater than a depth of said seventh semiconductor region, wherein said gate electrode of said n-channel MISFET is a N-type gate electrode, and wherein said gate electrode of said p-channel MISFET is a P-type gate electrode.