Patent ID: 8799584

Claim:
A method for implementing multi-processor memory coherency, comprising: receiving, by a Level-2 (L2) cache of a first cluster, a control signal of the first cluster for reading first data; reading the first data in a Level-1 (L1) cache of a second cluster through an Accelerator Coherency Port (ACP) of the L1 cache of the second cluster if the first data is currently maintained by the second cluster, wherein the L2 cache of the first cluster is connected to the ACP of the L1 cache of the second cluster; and providing the first data read to the first cluster for processing, obtaining a result of the first data processed by the first cluster; and one of: writing the result of the first data processed by the first cluster into one of the L1 cache or L2 cache of the second cluster through the ACP of the L1 cache of the second cluster; or buffering the result of the first data processed by the first cluster into the L2 cache of the first cluster; wherein: receiving the control signal of the first cluster for reading the first data comprises: receiving the control signal of the first cluster for reading the first data, wherein an operation attribute of the control signal is “non-cacheable”; and reading the first data in the L1 cache of the second cluster through the ACP of the L1 cache of the second cluster comprises: sending a control signal for reading the first data to the L1 cache of the second cluster through the ACP of the L1 cache of the second cluster, wherein the operation attribute of the control signal is “cacheable”; and reading the first data in the L1 cache of the second cluster.