Patent ID: 8119426

Claim:
A method of manufacturing a semiconductor device comprising the steps of: (a) preparing a first semiconductor substrate; (b) forming a plurality of first chips by arranging a predetermined number of ultrasonic transducer cell blocks on a front surface of the first semiconductor substrate in a first direction and in a second direction orthogonally crossing the first direction; arranging in each said block a predetermined number of said ultrasonic transducer cells, each having an upper electrode and a lower electrode, in the first direction and in the second direction in said block; electrically connecting the upper electrodes of said predetermined number of ultrasonic transducer cells arranged in the first direction in said block; electrically connecting the lower electrodes of said predetermined number of ultrasonic transducer cells arranged in the second direction in said block; and for each of the blocks, exposing a through electrode that is electrically connected with the lower electrode and that is on a rear surface of the first semiconductor substrate; (c) testing said plurality of first chips to determine which of the first chips are non-defective first chips; (d) singulating the first semiconductor substrate; into the plurality of first chips by dicing the first semiconductor substrate; (e) preparing a second semiconductor substrate; (f) forming a plurality of second chips, in which a wiring layer is formed, on a front surface of the second semiconductor substrate, wherein each of the first chips has a first area that is smaller than second area of each of the second chips; (g) testing said plurality of second chips to determine which of the chips are non-defective second chips; (h) singulating the second semiconductor substrate into the plurality of second chips by dicing the second semiconductor substrate; and (i) stacking said non-defective first chips on the front surface of one of said non-defective second chips to electrically connect the through electrode exposed on each of the rear surfaces of the non-defective first chips with the wiring layer formed on the front surface of said one non-defective second chip.