Patent ID: 7282403

Claim:
A method for fabricating a gate structure for an integrated circuit on a substrate, the substrate having a PFET region and an NFET region, the method comprising the steps of: forming a gate dielectric on the substrate; forming a metal nitride layer overlying the gate dielectric and in contact therewith, said metal nitride layer being characterized as MNx, where M is one of W, Re, Zr, and Hf; covering the metal nitride layer with a hardmask layer in one of the PFET region and the NFET region; adjusting the nitrogen content of the metal nitride layer in the region not covered by the hardmask layer; forming a PFET gate structure in the PFET region; and forming an NFET gate structure in the NFET region, wherein the hardmask layer is a polysilicon layer, and said polysilicon layer is effective to render the gate structure formed in the region having the hardmask layer substantially stable with respect to temperature at temperatures up to about 1000° C.