Patent ID: 7010475

Claim:
A method, comprising: (a) providing an integrated circuit development library characterizing several different logic device cells, the library specifying a number of different timing relationships for each of the logic device cells; (b) determining a number of derating values for characterizing derated performance of each of the logic device cells, each of the derating values being determined by evaluating a different one of the timing relationships for each of the logic device cell descriptions at a derating condition with a first simulator; and (c) calculating a number of derating factors, the derating factors each being determined from a different subset of the derated condition values, the derating factors being applicable to estimate derated performance of an integrated circuit developed from the library with a second simulator, the calculating of the number of derating factors including: establishing a number of best cast multiplier arrays and a number of worst case multiplier arrays; and screening each of the best case multiplier arrays and each of the worst case multiplier arrays.