Patent ID: 7496707

Claim:
A data processing system comprising: a processor coupled to a system bus; a computer expansion bus controller coupled to the system bus and which supports a peripheral component interconnect (PCI) enabled fabric for routing data packets to and from the system bus and devices coupled to the PCI enabled fabric, wherein said computer expansion bus controller is a PCI Express bus controller and includes: at least one PCI queue having one or more queue entries that that are dynamically configurable to accommodate a plurality of different sized data packets scheduled to be transferred through the PCI fabric; and a PCI Express firmware that includes dynamic queue modification (DQM) logic, which dynamically modifies a size of said one or more queue entries to accommodate an existing type, number and size of data packets that are being scheduled for transfer through the PCI fabric, wherein said DQM logic further comprises: logic for establishing thresholds associated with each size of data packets for triggering when to modify the size of the queue entries to that corresponding to the particular size of data packets, wherein said threshold establishes a number above which the number of outstanding data rackets of the corresponding size should be reduced; logic for comparing a current number of outstanding data packets of each size against the threshold corresponding to that size data packet; and logic for resetting a counter when the counter reaches a preset limit; logic for tracking a percentage of transactions within each of said pre-specified ranges of transaction sizes that is currently outstanding and waiting to be transferred within the PCI fabric, wherein when a percentage of existing transactions passes a preset threshold, said DQM logic triggers said dynamic configuration of the queue entries to support a transfer of more transactions within that range of specific transaction size; logic for consolidating and expanding queue entries within the queue based on the tracked percentage of transactions within each of the pre-specified ranges of transaction sizes; and logic for adjusting the rate at which a size of a queue entry is modified based on an analysis of the current traffic relative to a pre-established equilibrium point that balances (a) efficient transfer of a number of larger data rackets with (b) limiting a number of each size of data packets outstanding to below the preset thresholds of the specific size of data packets one or more performance counters, which take on one of several predefined characteristics based on the number of outstanding transactions (NTR), wherein said counters are utilized to track a number of received transactions in each of multiple pre-specified ranges of transaction size.