Patent ID: 7154548

Claim:
A semiconductor imaging chip comprising: an array of active pixel sensors arranged in rows and columns, each of said active pixels sensors having a respective active pixel sensor signal value and an active pixel sensor reset value; an output terminal; and a plurality of multiplexed column buffers, each of said plurality of multiplexed column buffers having a respective first plurality of input terminals coupled to a respective first plurality of said columns, a first of said plurality of multiplexed column buffers comprising: first, second, third and fourth memory elements; said first memory element adapted to store an active pixel sensor signal value for a first column of said array; said second memory element adapted to store an active pixel sensor reset value for said first column of said array; said third memory element adapted to store an active pixel sensor signal value for a second column of said array; said fourth memory element adapted to and an active pixel sensor reset value for said second column of said array; a differential gain amplifier having respective first and second input terminals and a respective output terminal; said first input terminal of said differential gain amplifier being selectively coupled to one of said first and third memory elements; said second input terminal of said differential gain amplifier being selectively coupled to one of said second and fourth memory elements; and the output terminal of said differential gain amplifier being selectively coupled to said output terminal of said semiconductor imaging chip, wherein each of said plurality of multiplexed column buffers further comprises: a multiplexed bus driver amplifier having respective input and output terminals; fifth and sixth memory elements; said fifth memory element being selectively coupled to said output terminal of said differential gain amplifier to store a corrected APS pixel signal value output for said first column of said array; said sixth memory element being selectively coupled to said output terminal of said differential gain amplifier to store a corrected APS pixel signal value output for said second column of said array; said input terminal of said multiplexed bus driver amplifier being sequentially coupled to said fifth memory and said sixth memory clement so as to sequentially output a corrected APS pixel signal value for said first column of said array followed by a corrected APS pixel signal value for said second column of said array.