Patent ID: 8748798

Claim:
A comparator circuit comprising: a first stage to sample an input signal, the first stage including first gain circuitry to provide at a first node a first intermediate signal based on a reference signal and the input signal; a second stage including: a capacitor to store charge based on the first intermediate signal; switch circuitry between the first node and the capacitor, the switch circuitry to switchedly couple the first node to the capacitor based on a switch control signal; second gain circuitry coupled to the capacitor via a second node, the second gain circuitry to provide at a third node a second intermediate signal based on the stored charge of the capacitor; a third stage including combinatorial logic coupled to the third node, the combinatorial logic to receive an output enable control signal and to provide at a fourth node an output signal based on the second intermediate signal and the output enable control signal, the output signal representing a comparison of the reference signal and the input signal; and feedback circuitry coupled between the second node and the fourth node, the feedback circuitry to receive the output enable control signal and, in response to the output enable control signal, to control a voltage of the second node based on the output signal.