Patent ID: 6880153

Claim:
A computer for performing correctness checks opportunistically, the computer comprising: first logic, the first logic receiving a first set of instructions and generating an initial instruction schedule from the first set of instructions, the first set of instructions including one or more instructions associated with a correctness check function; second logic, the second logic evaluating the initial instruction schedule to determine whether the initial instruction schedule includes spare instruction slots into which said one or more instructions associated with the correctness check function can be inserted; third logic, the third logic determining a number of additional instruction slots that may be added to the initial instruction schedule without exceeding a run-time performance cost tolerance level; and fourth logic, the fourth logic inserting said one or more instructions associated with the correctness check function into the spare instruction slots when enough spare instruction slots exist in the initial instruction schedule for accommodating said one or more instructions in a final schedule of instructions, wherein when enough spare instruction slots do not exist in the initial instruction schedule to accommodate said one or more instructions, the fourth logic determines whether the number of additional instruction slots is large enough to accommodate said one or more instructions, when the fourth logic determines that the number of additional instruction slots is large enough to accommodate said one or more instructions, the fourth logic inserts said one or more instructions into the additional instruction slots.