Patent ID: 7457939

Claim:
A processing system, comprising: a processing unit; and a plurality of sub-processing units for processing programs and data, each of the sub-processing units including a dedicated local memory for storing selected programs and data, the dedicated local memory including a plurality of addressable memory locations and a plurality of additional memory segments, each of the additional memory segments being directly associated with a respective one of the plurality of addressable memory locations and being operable to store a busy identifier therein, and at least one of the sub-processing units being operable to communicate with the processing unit; wherein the dedicated local memory of each respective sub-processing unit is not a cache memory and does not support cache coherency, and wherein each busy identifier is employed by the processing system to synchronize data reading and writing between the respective addressable memory location and an external memory, each busy identifier identifying a first condition wherein the respective addressable memory location is usable for writing any data or a second condition wherein the respective addressable memory location is usable for writing only specific data retrievable from the external memory.