Patent ID: 7296173

Claim:
A semiconductor integrated circuit comprising: a clock input terminal; a data input terminal; an internal clock generating circuit for generating an internal clock signal from a clock signal which is input to said clock input terminal; a latch circuit for latching a data signal input to said data input terminal synchronously with said internal clock signal; and means for preventing a timing margin, at a time of latching the data signal synchronously with said internal clock signal, from being decreased in a case wherein a duty ratio of the clock signal input to the clock input terminal is different than 50%, said means comprising the internal clock generating circuit including: a first variable delay circuit for receiving said clock signal and outputting said internal clock signal; a second variable delay circuit for delaying said clock signal or an inversion signal of said clock signal; a third variable delay circuit for delaying an output signal of said second variable delay circuit; a first frequency divider for dividing the frequency of an output signal of said third variable delay circuit; a second frequency divider for dividing the frequency of said clock signal or the inversion signal of said clock signal; a phase comparator for comparing the phase of a first frequency divided signal output from the first frequency divider with the phase of a second frequency divided signal output from the second frequency divider; and a delay control circuit for outputting a delay control signal for controlling said first, second, and third variable delay circuits on the basis of an output signal of said phase comparator, wherein said first, second, and third variable delay circuits have the same configuration, wherein said first frequency divider generates a first frequency divided signal that is synchronized with the (i−j)th switch timing of said clock signal (where i denotes an integer of 1 or larger and j denotes an integer of 0 or larger), wherein said second frequency divider generates a second frequency divided signal that is synchronized with the (i+1+ j)th switch timing of said clock signal, wherein said phase comparator compares the phase of said first frequency divided signal with the phase of said second frequency divided signal to obtain a phase difference, and wherein said delay control circuit controls the delay times of said first, second, and third variable delay circuits so that said phase difference becomes zero.