Patent ID: 7254073

Claim:
A memory device, comprising: an array of resistive memory cells, the resistive memory cells being arranged in columns and rows, the resistive memory cells each being connected to a word line, to a bit line, and to a reference electrode, the word lines being assigned to the rows and the bit lines being assigned to the columns, wherein a resistive state of the resistive memory cells corresponds to a logical state of the resistive memory cells; an evaluation device coupled to the bit lines for evaluating the resistive state of at least one of the resistive memory cells during a reading operation, the respective resistive memory cell being selected by addressing the word line to which the resistive memory cell is connected; and a charging device coupled to the bit lines, the charging device charging the bit lines to a pre-determined pre-reading bit line potential before carrying out a reading operation, the charging device comprising a further row of resistive memory cells, each memory cell being connected to a respective bit line.