Patent ID: 7859047

Claim:
A field effect transistor (FET) comprising: a plurality of trenches extending into a semiconductor region; a shield electrode in a lower portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric; an inter-electrode dielectric (IED) over the shield electrode in each trench; a body region extending between each pair of adjacent trenches; a gate electrode recessed in an upper portion of each trench over the IED, the gate electrode being insulated from corresponding body regions by a gate dielectric; source regions in each body region adjacent to the trenches, the source regions having a conductivity type opposite to that of the body regions; a first interconnect layer contacting the source and body regions; and a dielectric material insulating each gate electrode and the second interconnect layer from one another, wherein the plurality of trenches extend in an active region of the FET, the shield electrode and gate electrode extending out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer, and the electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region.