Patent ID: 7784003

Claim:
A computerized method of reducing a number of paths to be analyzed for a plurality of timing tests in a multi-corner static path-based timing analysis, the method comprising: using one or more computers to perform the steps of: performing a first timing analysis on a plurality of paths to determine an starting corner path slack for each of the plurality of timing tests for each path of the plurality of paths; identifying a first set of racing path pairs of the plurality of paths that have a starting corner path slack that does not pass an initial threshold; determining an estimated upper slack variation for one or more racing path pair of the first set by utilizing a corresponding non-common path delay of the one or more racing path pair, wherein the non-common path delay is a delay related to a portion of a path not shared by both paths of a racing path pair; applying the estimated upper slack variation for each of the racing path pairs of the first set to a corresponding starting corner path slack; bypassing full multi-corner path based static timing analysis for any racing path pair for which the result of said applying step is greater than or equal to a signoff slack; performing full multi-corner path based static timing analysis on each racing path pair for which the result of said applying step is less than the signoff slack; and outputting an indication of timing verification for one or more paths of an integrated circuit design.