Patent ID: 6924192

Claim:
A semiconductor device manufacturing method comprising the steps of: (a) forming a first insulating film on a semiconductor substrate having a memory region where a memory device is to be formed and a logic region where a logic device is to be formed; (b) forming, in said first insulating film, a first contact plug electrically connected to said semiconductor substrate in said memory region and having its top surface exposed from said first insulating film, and a second contact plug electrically connected to said semiconductor substrate in said logic region and having its top surface exposed from said first insulating film; said first contact plug formed in said step (b) having a first conductive film and a first conductive barrier layer formed on a top end of said first contact plug; (c) forming an MIM (Metal-Insulator-Metal) capacitor in contact with said first conductive barrier layer and forming a second insulating film, covering said MIM capacitor, on a top surface of the structure obtained by said step (b); and (d) after said step (c), forming in said second insulating film a third contact plug in contact with said second contact plug; said MIM capacitor formed in said step (c) having a lower electrode in contact with said first conductive barrier layer, an upper electrode, and a dielectric film interposed therebetween.