Patent ID: 7943996

Claim:
A semiconductor device comprising: a first completely-depleted type SOI/MOS transistor provided on a first embedded oxide film formed on a semiconductor substrate; and a second completely-depleted type SOI/MOS transistor provided on the first embedded oxide film (TB), wherein the first completely-depleted type SOI/MOS transistor comprises (pMOS) a first semiconductor layer selectively formed on the first embedded oxide film via a second embedded oxide film; a first source region and a first drain region having a first conductive type formed on the first semiconductor layer and having a same thickness as that of the first semiconductor layer; a first channel region having a second conductive type opposite to the first conductive type formed between the first source region and the first drain region having the first conductive type; a first gate formed on a first main surface of the first channel region; a second gate comprising a conductive layer having the second conductive type formed on the first embedded oxide film in contact with a bottom of the second embedded oxide film; a first insulating separating layer formed on the first embedded oxide film so as to surround the first semiconductor layer; a first diffusion layer having the second conductive type selectively formed on the second gate; and a second insulating separating layer formed on the second gate in contact with the second embedded oxide film so as to separate the first diffusion layer and the first semiconductor layer, wherein the second completely-depleted type SOl/MOS transistor comprises a second semiconductor layer selectively formed on the first embedded oxide film via a third embedded oxide film; a second source region and a second drain region having a second conductive type formed on the second semiconductor layer and having a same thickness as that of the second semiconductor layer; a second channel region having the first conductive type formed between the second source region and the second drain region having the second conductive type; a third gate formed on a first main surface of the second channel region; a fourth gate comprising a conductive layer having the first conductive type formed on the first embedded oxide film in contact with a bottom of the third embedded oxide film); a third insulating separating layer formed on the first embedded oxide film so as to surround the second semiconductor layer; a second diffusion layer having the first conductive type selectively formed on the fourth gate; and a fourth insulating separating layer formed on the fourth gate in contact with the third embedded oxide film so as to separate the second diffusion layer and the second semiconductor layer, wherein each of the second and the fourth insulating separating layers is a trench type insulation region with a depth smaller than that of the first and the third insulating separating layer, respectively.