Patent ID: 7663948

Claim:
A semiconductor memory device, comprising: a memory cell array having a plurality of word lines, a plurality of bit line pairs crossing the word lines, and a plurality of memory cells placed at positions of the crossing; a redundant memory cell array for replacing a failure bit in the memory cell array; a plurality of sense amplifier circuits which are placed between adjacent memory cell arrays and are shared by a bit line pair of each column of the adjacent memory cell arrays on both sides; bit line transfer circuits formed between the sense amplifier circuit and the bit line pairs on both sides sharing the sense amplifier circuit respectively, each of which connects a selected bit line pair to the sense amplifier circuit; and current interrupting circuits formed between the sense amplifier circuit and the bit line pairs on both sides sharing the sense amplifier circuit respectively, wherein in a column replaced with a column in the redundant memory cell array, the current interrupting circuit in the column is set to an interrupting state.