Patent ID: 8116357

Claim:
A method for power management in a transceiver circuit, the method comprising: transmitting, from a transmitter subcircuit of the transceiver circuit, a first pulse pattern during a powered-down mode of the transceiver circuit to indicate a status of the transceiver circuit and, wherein a first clock management scheme is employed to regulate the power consumption of the transceiver circuit while in powered-down mode, wherein said first pulse pattern differs from a second pulse pattern that is transmitted from the transmitter subcircuit to indicate that the transceiver is in a power-on mode; receiving data signals by a receiver subcircuit having a media independent interface for receiving the data signals, wherein said media independent interface remains powered-on during the powered-down mode of the transceiver circuit; powering the transmitter subcircuit with a first power supply; powering the receiver subcircuit with a second power supply; and changing a clock management scheme employed by the transceiver circuit based upon a desired operating mode of the transceiver circuit from a plurality of operational modes of the transceiver circuit, wherein the plurality of operational modes of the transceiver circuit includes the powered-down mode of the transceiver circuit.