Patent ID: 7564309

Claim:
A circuit, comprising: a bipolar differential pair coupled with a supply voltage (V CC ) and comprising a first transistor and a second transistor wherein collector currents of said first and second transistor are not required to be equal to collector currents of other transistors in said circuit; and an input bias current cancellation circuit coupled with said bipolar differential pair and comprising a third transistor, wherein said third transistor has a collector-emitter voltage V CE , wherein further said bipolar differential pair is operable to receive an input voltage greater than V CC −2V CE without causing said third transistor to operate in the saturation region, and wherein said input bias current cancellation circuit further comprises: a current source for generating a first current that is proportional to a second current, wherein said second current drives said bipolar differential pair; a fourth transistor coupled with said current source, wherein said current source drives said first transistor; a base current sensing circuit coupled with said fourth transistor and for sensing a base current of said fourth transistor; and a current mirror coupled with said base current sensing circuit and said bipolar differential pair, said current mirror for mirroring said base current of said fourth transistor to bases of said bipolar differential pair.