Patent ID: 8035133

Claim:
A semiconductor device, comprising: a gate electrode level region that forms part of a gate electrode level of the semiconductor device, the gate electrode level region including a plurality of linear conductive segments defined to extend lengthwise in a first direction so as to extend parallel to each other, wherein the plurality of linear conductive segments form: a gate electrode of a first transistor of a first transistor type, a gate electrode of a second transistor of the first transistor type, a gate electrode of a third transistor of the first transistor type, a gate electrode of a fourth transistor of the first transistor type, a gate electrode of a first transistor of a second transistor type, a gate electrode of a second transistor of the second transistor type, a gate electrode of a third transistor of the second transistor type, and a gate electrode of a fourth transistor of the second transistor type, wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type by a first linear-shaped conductive segment within the gate electrode level region, and wherein the gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type by a second linear-shaped conductive segment within the gate electrode level region, and wherein both gate electrodes of the third and fourth transistors of the first transistor type are collectively positioned between the gate electrodes of the first and second transistors of the first transistor type, and wherein the gate electrodes of the first, second, third, and fourth transistors of the first transistor type are positioned in a side-by-side manner according to a substantially equal centerline-to-centerline spacing as measured in a second direction perpendicular to the first direction, and wherein both gate electrodes of the third and fourth transistors of the second transistor type are collectively positioned between the gate electrodes of the first and second transistors of the second transistor type, and wherein the gate electrodes of the first, second, third, and fourth transistors of the second transistor type are positioned in a side-by-side manner according to the substantially equal centerline-to-centerline spacing as measured in the second direction perpendicular to the first direction.