Patent ID: 8102353

Claim:
A display device comprising: a display area having a plurality of sub pixels; and a driving circuit formed at the periphery of the display area; wherein the driving circuit includes: a first scanning circuit which performs scanning in a first direction; and a latch circuit which latches display data inputted from external based on a scanning output outputted from the first scanning circuit; wherein the driving circuit includes a timing correction circuit which corrects a timing of level change of the scanning output outputted from the first scanning circuit based on a display data synchronization clock inputted from external; wherein a first transmission line extends to the latch circuit and applies the display data, a second transmission line extends to the timing correction circuit and applies the display data synchronization clock, and a third transmission line different from the second transmission line extends to the timing correction circuit and applies the scanning output; wherein the latch circuit latches display data by means of a corrected scanning output outputted from the timing correction circuit; wherein the second transmission line is not connected with the first scanning circuit; wherein the first transmission line and the second transmission line are adjacently arranged, and wherein at least a same quantity of inverter circuits are inserted in the second transmission line as the first transmission line.