Patent ID: 8248287

Claim:
An apparatus comprising: a plurality of input differential pairs, each pair comprising first and second transistors and having an initial transconductance, said first and second transistors of each input differential pair coupled at a source node; switches coupled to gates of a first portion of said first transistors, said switches operable, in response to digital input data, to couple said gates to a high input voltage node or to a low input voltage node; a first attenuation network coupled to the first transistor in each of a first portion of said input differential pairs, said first attenuation network operable to attenuate the initial transconductance of said first transistors in said first portion of input differential pairs to produce a binary-weighted effective transconductance; and a second attenuation network coupled to the second transistor in each of said first portion of input differential pairs, said second attenuation network operable to attenuate the initial transconductance of said second transistors in said first portion of input differential pairs to produce a binary-weighted effective transconductance; wherein a number of input differential pairs in said plurality of input differential pairs is one more than a number of bits of digital input data received by said apparatus.