Patent ID: 7326620

Claim:
A method of manufacturing a semiconductor device comprising a dual gate field effect transistor, comprising: providing a semiconductor body of silicon with a surface, a source region and a drain region of a first conductivity type, a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region; forming a first gate within a first trench, separated from the channel region by a first gate dielectric and situated on one side of the channel region; forming a second gate within a second trench, separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, wherein both gates are formed within a third trench formed in the semiconductor body, wherein the channel region is formed by the part of the semiconductor body between the first and second trench, and wherein the source and drain regions are formed by implantation at the surface of the semiconductor body.