Patent ID: 7305540

Claim:
An apparatus, in an integrated circuit (IC) of a data processing system having at least one host processor and host memory, comprising: a chip interconnect; a host interface coupled to the chip interconnect for interfacing the IC with the at least one host processor external to the IC; a memory interface coupled to the chip interconnect for accessing a memory external to the IC, the memory interface including a non-coherent interface for interfacing the IC with the host memory external to the IC, the memory interface including a coherent interface for interfacing the IC with a cache memory external to the IC via the at least one host processor; a memory controller coupled to the chip interconnect for controlling the host memory comprising DRAM memory via the memory interface, the memory controller to determine whether to access the memory through the coherent interface or the non-coherent interface; a scalar processing unit coupled to the chip interconnect, the scalar processing unit executing instructions to perform scalar data processing; a vector processing unit coupled to the chip interconnect, the vector processing unit executing instructions to perform vector data processing; and an input and output (I/O) interface coupled to the chip interconnect for interfacing the IC with an I/O controller of the data processing system, the I/O controller being external to the IC for controlling I/O devices of the data processing system, wherein the chip interconnect, the memory controller, the scalar processing unit, the vector processing unit, the I/O interface, the host interface, and the memory interface are implemented within the IC which is a single chipset interfacing the at least one host processor and the host memory with other components of the data processing system, including the I/O controller and the I/O devices.