Patent ID: 7696092

Claim:
A method of fabricating an integrated circuit, the method comprising: depositing an etch stop layer over a first conductive layer, wherein the etch stop layer is in direct contact with the first conductive layer; depositing an insulating layer after the etch stop layer is deposited over the etch stop layer; forming a barrier layer extending along lateral side walls and a bottom of a via aperture, the via aperture being configured to receive a via material that electrically connects the first conductive layer and a second conductive layer; and depositing a copper alloy via material in the via aperture on the barrier layer to form a via, the copper alloy material including Zinc (Zn) or Silver (Ag) and at least one element for increasing grain size including Calcium (Ca) or Chromium (Cr), wherein the resistance of the via filled with the copper alloy via material is between 1.8 and 2.2 μΩcm less than the resistance of a via filled with copper, wherein depositing the copper alloy via material includes using an electroplating solution including organic additives to reduce voids in the via, wherein the organic additives are at least one of polypropylene glycols, polyethylene glycols and mercaptan disulfides.