Patent ID: 8290115

Claim:
A driver, comprising: odd-numbered stages configured to be directly driven by exactly two clock signals, wherein the two clock signals include a first clock signal and a second clock signal; and even-numbered stages configured to be directly driven by exactly two clock signals, wherein the two clock signals include the second clock signal and a third clock signal, wherein each of the odd-numbered and even-numbered stages includes a first driver, a second driver, and a third driver, and is coupled to a corresponding emission control line, wherein the first driver of a first stage is configured to receive a first start pulse and output a first output signal of the first stage, the second driver of the first stage is configured to receive a second start pulse and output a second output signal of the second stage, and the third driver of the first stage is configured to receive the first output signal of the first stage and the second output signal of the second stage, and output an emission control signal to be transmitted to an emission control line coupled to the first stage, and wherein the first driver of each stage except the first stage is configured to receive a first output signal of a previous stage and output a first output signal of each stage, the second driver of each stage except the first stage is configured to receive a second output signal of the previous stage and output a second output signal of each stage, and the third driver of each stage except the first stage is configured to receive the first output signal and the second output signal and output an emission control signal to be transmitted to a emission control line coupled to each stage.