Patent ID: 6925026

Claim:
A semiconductor device including a clock generating circuit, a data holding circuit for holding data at a timing of a clock signal from the clock generating circuit, and a logic circuit, comprising: a first power line connected to the logic circuit, in which supply and shutdown of a first power supply voltage are controlled; a second power line connected to the clock generating circuit and the data holding circuit, in which supply of a second power supply voltage is controlled; and a switch that is connected between the first power line and the second power line and is turned on or off in accordance with a switching control signal, wherein during normal operation, the switch is on to connect the second power line to the first power line, and the clock generating circuit and the data holding circuit are operated with the first power supply voltage, when data holding is required at a time of power shutdown, the switch is turned off to disconnect the second power line from the first power line, and the supply of the first power supply voltage to the first power line is stopped, and the clock generating circuit and the data holding circuit are operated with the second power supply voltage, and wherein both of the first power supply voltage and the second power supply voltage are supplied to the clock generating circuit and the data holding circuit at a time of power rising.