Patent ID: 7439167

Claim:
A method for manufacturing a nonvolatile semiconductor memory device comprising: forming a plurality of stacked gate structures, each of which including a first polysilicon layer formed on a silicon substrate via a gate insulator, an inter-gate insulator formed on the first polysilicon layer, a second polysilicon layer formed on the inter-gate insulator, and a cap layer formed on the second polysilicon, respectively; forming an interlayer insulator between the stacked gate structures, the interlayer insulator covering upper surfaces of the cap layers; planarizing the interlayer insulator by using the cap layers as a stopper so that an upper surface of the interlayer insulator is higher than upper surfaces of the second polysilicon layers; removing the cap layers to expose the second polysilicon layers so that grooves are formed at upper portions of the second polysilicon layers of the interlayer insulator; forming a conductive material, including a metal, on the interlayer insulator to fill the grooves; and planarizing the conductive material by using the interlayer insulator as a stopper so that conductive material layers are formed on the second polysilicon layers.