Patent ID: 8407555

Claim:
An apparatus, comprising: an input for receiving an LDPC (Low Density Parity Check) coded signal; and an LDPC decoder for employing an LDPC matrix for decoding the LDPC coded signal to make an estimate of an information bit encoded therein; and wherein: the LDPC matrix, composed of a plurality of sub-matrices each having a common size, being partitioned into a left hand side matrix and a right hand side matrix; and each sub-matrix within the right hand side matrix being an all zero-valued sub-matrix except those sub-matrices identified in (a) and (b): (a) each sub-matrix located on a diagonal of the right hand side matrix being a respective one of a first plurality of CSI (Cyclic Shifted Identity) sub-matrices, the diagonal extending from an upper left most sub-matrix of the right hand side matrix to a lower right hand sub-matrix of the of the right hand side matrix; and (b) each sub-matrix being located below the diagonal of the right hand side matrix also being a respective one of a second plurality of CSI sub-matrices.