Patent ID: 8132040

Claim:
An integrated circuit comprising: at least a first channel and a second channel adapted to provide a corresponding first channel output signal and second channel output signal; a delay element disposed within at least one of the channels; and a control circuit adapted to receive the first channel output signal and the second channel output signal and to detect a phase difference between the first channel output signal and the second channel output signal, the control circuit further adapted to control the delay element based on the phase difference to reduce skew between the first channel output signal and the second channel output signal, wherein the control circuit includes: a phase detector adapted to receive the first channel output signal and the second channel output signal and provide a phase detector output signal; a first counter adapted to receive the phase detector output signal and provide a first counter output signal based on the phase detector output signal; and a second counter adapted to receive the first counter output signal and provide a second counter output signal to control the delay element based on the first counter output signal to reduce skew between the first channel output signal and the second channel output signal.