Patent ID: 8304910

Claim:
A semiconductor device comprising: a semiconductor substrate having a memory cell region and a peripheral region, the peripheral region being formed in a same plane as the memory cell region and in a different place from the memory cell region; an interlayer insulating film that is formed on the semiconductor substrate; a plurality of first interconnections that are formed above the memory cell region on the interlayer insulating film while complying with a first design rule, the plurality of first interconnections running along a specific direction; a plurality of second interconnections that are formed above the peripheral region on the interlayer insulating film while complying with a second design rule identical to the first design rule, the plurality of second interconnections running along the specific direction; and a connection member that is formed above the peripheral region in the interlayer insulating film, the connection member forming an interconnection pattern extending in a direction other than the specific direction and electrically connecting at least two second interconnections.