Patent ID: 7615405

Claim:
A method of fabricating an electronic device, comprising: Placing a placement guide over a top surface of a module substrate, a bottom surface of said placement guide facing a top surface of said module substrate, said placement guide having one or more guide openings, said guide openings extending from a top surface of said placement guide to said bottom surface of said placement guide; aligning said placement guide to at least one integrated circuit chip position of one or more integrated circuit chip positions on said module substrate; fixing said aligned placement guide to said module substrate; placing one or more integrated circuit chips in corresponding guide openings of said one or more guide openings, bottom surfaces of said one or more integrated circuit chips facing said top surface of said module substrate, each integrated circuit chip of said one or more integrated circuit chips having first distances between sidewalls of said placement guide openings and corresponding sidewalls of each integrated circuit chip of said one or more integrated circuit chips, said first distances constraining electrically conductive bonding structures on bottom surfaces of each integrated circuit chip of said one or more integrated circuit chips to contact corresponding electrically conductive module substrate contact pads on said top surface of said module substrate; bonding said bonding structures to said module substrate contact pads, said bonding structures and said module substrate contact pads in direct physical and electrical contact after said bonding; and wherein a distance between at least one sidewall of each of said one or more placement guide openings and at least one opposing sidewall of corresponding placed integrated circuit chips is equal to less than one half a distance between centers of a pair of adjacent module substrate contact pads of said module substrate contact pads at each of said corresponding integrated circuit chip positions.