Patent ID: 8143919

Claim:
A semiconductor device comprising: a memory comprising a NOR cell, the NOR cell comprising: a first input side NOT gate; a second input side NOT gate; a NAND gate having a first input terminal connected to the first input side NOT gate and a second input terminal connected to the second input side NOT gate; and an output side NOT gate having a third input terminal connected to an output terminal of the NAND gate, wherein a first channel width of a first transistor in the first input side NOT gate is smaller than a third channel width of a third transistor in the output side NOT gate, wherein a second channel width of a second transistor in the second input side NOT gate is smaller than the third channel width of the third transistor in the output side NOT gate, and wherein each of the first transistor, the second transistor and the third transistor comprises a semiconductor layer on an insulating layer, the semiconductor layer comprising a channel region.