Patent ID: 7382662

Claim:
A method of device operation of a twin MONOS memory comprising: polysilicon word gates having polysilicon control gates on sidewalls of said word gates having an L-shaped oxide-nitride-oxide (ONO) layer between said polysilicon word gates and said polysilicon control gates and underlying said control gates wherein said nitride portion of said ONO layer underlying said control gates provides memory storage; wherein said method of device operation comprises: performing one hot hole erasure after every n cycles of channel hot electron (CHE) programming and Fowler-Nordheim (F-N) erasure wherein electrons injected by said CHE programming are not perfectly erased by said F-N erasure and remaining said electrons are accumulated with said cycles and wherein said hot holes are generated by band to band transition by applying a negative bias on said word gate and are injected into said nitride portion of said ONO layer not only directly under one of said control gates but also at a corner of said L-shaped ONO layer wherein said hot holes neutralize accumulated said electrons within said nitride portion of said ONO layer at said corner of said L-shaped ONO layer.