Patent ID: 7389317

Claim:
A data processing apparatus comprising: a first input bus of N bits; a second input bus of N bits; a multiplier having a first input of L bits connected to a first set of L bits of said first input bus, L being less than N, a second input of L bits connected to a second set of L bits of said second input bus, and a product output of 2L bits producing a product of data that was supplied to said first and second inputs; a left shifter having an input connected to the product output of said multiplier, a shift amount input and an output connected to said output bus, said left shifter left shifting said input by said shift amount, discarding said shift amount of most significant bits of said input; and an output bus of N bits coupled to said output of said left shifter, said output bus including a first portion corresponding to a most significant set of L bits of said product output of 2L bits and a second portion of M bits, where said second portion of M bits does not include a least significant set of L bits of said product, and where N=L+M and M≧L.