Patent ID: 7495960

Claim:
An array of flash memory cells arranged in a plurality of rows and a plurality of columns, the array comprising: a first sector comprising a plurality of rows, each row being connected to a control-gate line; a first row comprising a row of flash memory cells in the first sector; a first control-gate line connecting control-gates of flash memory cells in the first row; a second row of flash memory cells in the first sector, the flash memory cells in the second row sharing a common source-line with the flash memory cells of the first row and each of the flash memory cells of the second row sharing a same bit-line with a respective one of the flash memory cells of the first row, the bit-lines forming the plurality of columns of the array of flash memory cells; a second control-gate line connecting control-gates of flash memory cells in the second row, wherein the first and the second control-gate lines are disconnected from each other; a second sector comprising a plurality of rows of flash memory cells, each row being connected to a respective control-gate line; a first positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a respective control-gate line in the second sector; a second positive HV driver connected to the second control-gate line in the first sector and a respective control-gate line in the second sector; a first negative HV driver coupled to all of the rows in the first sector; and a second negative HV driver coupled to all of the rows in the second sector.