Patent ID: 8438208

Claim:
A processor, comprising: an instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); and an instruction execution unit comprising a hardware multiplier datapath circuit, wherein the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M, and wherein the instruction execution unit is configured to receive instructions for execution from the instruction fetch unit; wherein in response to receiving a single instance of a large-operand multiplication instruction defined within the ISA, wherein at least one of the operands of the large-operand multiplication instruction includes more than the maximum number of bits M, the instruction execution unit is configured to multiply operands of the large-operand multiplication instruction within the hardware multiplier datapath circuit to determine a result of the large-operand multiplication instruction without execution of programmer-selected instructions within said ISA other than the large-operand multiplication instruction.