Patent ID: 7447974

Claim:
A memory controller, comprising: a refresh shadow counter that is operable to output a row address; a least one inverter coupled to receive at least one of bit of the row address from the refresh shadow counter, the at least one inverter being operable to invert the at least one bit of the row address from the refresh counter to provide at least one inverted bit; a failing address comparator storing row addresses corresponding to rows of memory cells in a memory device that may contain at least one operational memory cell that is prone to error, the failing address comparator being coupled to the refresh shadow counter and to an output of the inverter to receive the row address from the refresh shadow counter and the at least one inverted bit, the failing address comparator being operable to substitute the at least one inverted bit for at least one corresponding bit in the row address from the refresh shadow counter to provide a comparison row address and to compare the comparison row address to the stored row address and to generate an indicating signal responsive to a predetermined relationship between the comparison row address and one of the stored row addresses; and a memory control circuit coupled to receive the indicating signal from the failing address comparator, the memory control circuit being operable to output the stored row address having the predetermined relationship with the comparison row address, the memory control circuit further being operable to output refresh command signals responsive to the indicating signal.