Patent ID: 8874879

Claim:
A vector processing circuit comprising: a vector register file including a plurality of array elements; a command issuance control circuit configured to issue commands including a preceding command and a subsequent command following the preceding command; and a plurality of pipeline arithmetic units each configured to perform, in response to one of the commands, arithmetic processing of data stored in the array elements indicated as a source by the one of the commands in parts through a plurality of cycles and to store a result of the arithmetic processing in the array elements indicated as a destination by the one of the commands in parts through a plurality of cycles, wherein the command issuance control circuit is further configured to perform operations to: change data sizes of the array elements in accordance with a data word length of each command; determine, when a data word length of the preceding command is longer than a data word length of the subsequent command, whether a first register interference and a second register interference exist, the first register interference corresponding to a register interference between a first array element to be processed at a non-head cycle of the preceding command and a second array element to be processed at a head cycle of the subsequent command, the second register interference corresponding to a register interference between a third array element to be processed at a head cycle of the preceding command and the second array element, to adjust an issuance timing of the subsequent command based on a determination result of the first register interference and the second register interference; and determine, when the data word length of the preceding command is equal to the data word length of the subsequent command, whether the second register interference exists to adjust an issuance timing of the subsequent command based on the determination result of the second register interference.