Patent ID: 7930668

Claim:
A processor-implemented method of placing and routing a logic design, the logic design including a plurality of logic elements and a plurality of nets connecting the logic elements, the processor-implemented method comprising: on one or more programmed processors, performing operations including: generating a first placement and a partial routing of the logic elements and the nets of the logic design, leaving a portion of the nets unsuccessfully routed; associating an area with each of the logic elements, including associating an initial area with each of the logic elements and expanding into expanded areas, the initial areas of the logic elements that are connected by the nets that are unsuccessfully routed; wherein the expanding includes expanding the initial area of the logic element having a plurality of pins to a size that is a function of a number of the pins which are connected to the nets that are unsuccessfully routed; unplacing the logic elements that are connected by the unsuccessfully routed nets; from a linear system, determining positions for the unplaced logic elements that reduce a total length of the nets connecting the unplaced logic elements and inhibit overlap of the expanded areas of the unplaced logic elements; generating a second placement of the logic elements in response to the positions for the unplaced logic elements; and generating a complete routing of all of the nets for connecting the second placement of the logic elements; and outputting a specification of the second placement and the complete routing.