Patent ID: 7102601

Claim:
A pixel module for use in a large-area display, in particular as part of a cluster ( 118 ) of a plurality of sequentially interconnected similar pixel modules ( 120 ) and driven by a central controller ( 116 ), comprising one or more pixel elements ( 122 ), characterized in that it further comprises a serial video data bus input (SERIAL IN) and one or more command input lines (CMD's In) electrically connected to inputs of a latch ( 210 ) having parallel inputs and outputs and which is clocked with a data clock input (DATA CLK); a current driver device for driving said one or more pixels ( 122 ) which is electrically connected to the outputs of latch ( 210 ) and to the data clock input (DATA CLK) and which includes a serial output port (SERIAL OUT) for transmitting the serial data to the next pixel module ( 120 ) in sequence; a first inverter ( 214 ), the output of which (DATA CLK “not”) can be used to drive the data clock input (DATA CLK) of the next pixel module ( 120 ) in sequence; a grayscale clock (GS CLK) input which is electrically connected to the current driver device ( 210 ) and to an output (GS CLK) to drive the gray scale input of the next pixel module ( 120 ); an address input (ODD/EVEN) which is electrically connected to a second inverter ( 216 ), the output of which (ODD/EVEN “not” ) can drive the address input (ODD/EVEN) of the next pixel module ( 120 ); an EEPROM ( 218 ) that is electrically connected to an input port ( 2 C BUS) for communication with said central controller ( 116 ), which input port is also connected to an output port ( 2 C) for connection with the next pixel module ( 120 ); and a power supply ( 220 ) input and output.