Patent ID: 7396695

Claim:
A thin film transistor array panel comprising: an insulating substrate; a first signal line formed on the insulating substrate; a first insulating layer formed on the first signal line; a second signal line formed on the first insulating layer and intersecting the first signal line; a thin film transistor electrically connected to the first and the second signal lines; a second insulating layer formed on the thin film transistor and having a first contact hole exposing an electrode of the thin film transistor; and a pixel electrode formed on the second insulating layer and connected to the electrode of the thin film transistor through the first contact hole, wherein at least one of the first and the second signal lines comprises double layers of an adhesion layer and an Ag containing layer, wherein the Ag containing layer is located on the adhesion layer, and the adhesion layer having thickness of equal to or less than 500 Å.