Patent ID: 7262502

Claim:
A phase-change random access memory device comprising: a first insulation layer formed on a semiconductor substrate including a predetermined bottom structure and having first contact holes for exposing a predetermined portion of the semiconductor substrate; conductive plugs for filling the first contact holes; a second insulation layer formed on the first insulation layer including the conductive plugs, the second insulation layer having a second contact hole for exposing a predetermined portion of the semiconductor substrate formed between the conductive plugs; a bit line formed on the second insulation layer such that the second contact hole is filled with the bit line; third and fourth insulation layers and a nitride layer, which are sequentially formed on the second insulation layer including the bit line and formed with third contact holes for exposing the conductive plugs; bottom electrodes for filling the third contact holes; an opening section formed in the nitride layer and the fourth insulation layer in order to expose a predetermined portion of the third insulation layer formed between the bottom electrodes; a cavity section connected with the opening section so as to expose a part of a sidewall of each of the bottom electrodes; a phase-change layer pattern connected to one side of each of the bottom electrodes while filling the opening section and the cavity section; and a top electrode formed on the phase-change layer pattern.