Patent ID: 6903980

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array which includes nonvolatile memory cells; and a control circuit which responds to a first command by performing a first batch erasure with respect to a selected group of said memory cells, and responds to a second command by performing a second batch erasure with respect to the selected group of said memory cells, said first batch erasure including preprogramming, erasure, and over-erasure correction in this sequence, and said second batch erasure including over-erasure correction, preprogramming, erasure, and over-erasure correction in this sequence, wherein said first batch erasure and said second batch erasure are independent of each other, and one of said first batch erasure and said second batch erasure is performed independently of the other batch erasure in response to a corresponding one of the first command and the second command entered into the device.