Patent ID: 8005650

Claim:
A method for generating a two-dimensional (2D) flattened nailboard representation of a wiring harness in a three-dimensional (3D) computer-aided design (CAD) model, comprising: identifying a wire-loop in the wiring harness, wherein the wire-loop includes a plurality of exposed wires connecting a first segment and a second segment of the wiring harness, and wherein the first segment and the second segment represent a portion of the wiring harness where the plurality of exposed wires are routed along a common path; identifying a shortest wire within the plurality of exposed wires; determining a position for the first segment and the second segment in the nailboard representation based on the length of the shortest wire, wherein a distance between the first segment and the second segment is equal to the length of the shortest wire; adding the first segment and the second segment to the nailboard representation at the determined positions; adding each of the plurality of exposed wires of the wire loop to the nailboard representation as a contiguous sequence of linear segments, wherein the length of the contiguous sequence of linear segments for each of the plurality of exposed wires in the nailboard representation equals a length of a corresponding wire in the wiring harness; and storing the nailboard representation of the wiring harness in the 3D CAD model.