Patent ID: 7869275

Claim:
An integrated circuit comprising: a plurality of tiles, wherein each tile comprises a memory structure, wherein each memory structure comprises a non-volatile cell, a volatile cell, and a first multiplexer, wherein the non-volatile cell has a floating gate and can be programmed to store either a first state or a second state, wherein the volatile cell can be set to store either a first state or a second state, and wherein the first multiplexer has a first data input lead coupled to the volatile cell and a data output lead coupled to the non-volatile cell; and a programming voltage conductor that is coupled to the non-volatile cell of each memory structure in each of the plurality of tiles, wherein if a memory structure is set into a program mode and a programming pulse signal is supplied to the memory structure via the programming voltage conductor then the non-volatile cell will be programmed to store the state of the volatile cell if the state of the volatile cell and the state of the non-volatile cell differ, whereas if the state of volatile cell and the non-volatile cell do not differ then the non-volatile cell is not programmed to change state.