Patent ID: 7816935

Claim:
A test apparatus that tests a device under test, comprising: a first pipeline that sequentially propagates pieces of pattern data included in a first test pattern, according to a first test period, and outputs the propagated data to the device under test; a second pipeline that sequentially propagates pieces of pattern data included in a second test pattern, according to a second test period that is different from the first test period, and outputs the propagated data to the device under test; a timing control section that controls at least one of a timing at which the first pipeline begins propagating predetermined first pattern data and a timing at which the second pipeline begins propagating predetermined second pattern data, based on the first test period and the second test period; and a judging section that judges pass/fail of the device under test based on a signal output by the device under test, wherein the timing control section controls at least one of the timing at which the first pipeline begins to propagate the first pattern data and the timing at which the second pipeline begins to propagate the second pattern data, further based on the number of stages of circuits in the first pipeline and the number of stages of circuits in the second pipeline.