Patent ID: 7589992

Claim:
A semiconductor device, comprising: a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively; and a plurality of NOR gates including at least two third pull-up transistor and third pull-down transistor and generating an output signal having a high level if all of at least two input signals have a low level, respectively wherein the at least one first pull-up transistor and first pull-down transistor, the at least two second pull-up transistor and second pull-down transistor, and the at least two third pull-up transistor and third pull-down transistor are stacked and arranged on at least two layers.