Patent ID: 7523364

Claim:
A method of utilizing double Dynamic Random Access Memory (DRAM) bit steering for multiple error corrections, wherein the method is performed within a Central Processing Unit (CPU) that is coupled to a memory subsystem and a memory controller, the method comprising: identifying a defective portion of a memory sub-module in a memory module; subsequently discontinuing storing of data to the defective portion of the memory sub-module; subsequently storing data that was originally stored in the defective portion of the memory sub-module in a non-defective portion of another memory sub-module, wherein the another memory sub-module is a spare Dynamic Random Access Memory (DRAM) in the memory module; writing a unit of data to a primary memory sub-module in the memory module, the unit of data having a first data subunit and a second data subunit, the primary memory sub-module having a first partition and a second partition, wherein the first data subunit is written to the first partition and the second data subunit is written to the second partition, wherein the first data subunit is composed of contiguous bits, and wherein the second data subunit is composed of contiguous bits; reading the unit of data out of the primary memory sub-module; upon detecting an error in reading the unit of data, determining that the error was in the first data subunit; sending a first bit steer signal, to a memory controller, describing the error as being in the first data subunit; correcting the read unit of data to create a corrected unit of data; and writing the corrected unit of data back to the memory module by: writing the first data subunit to a spare memory sub-module in the memory module, and writing the second data subunit to the primary memory sub-module; in response to receiving a read request for the corrected unit of data, selectively sending the first data subunit from the spare memory sub-module to the memory controller; and selectively sending the second data subunit from the primary memory sub-module to the memory controller, wherein the selectively sending step is performed by a Multiplexer (MUX) that is under the control of a second bit steer signal that is stored in the memory controller, wherein the primary memory sub-module and the spare memory sub-module each have a first partition and a second partition, and wherein the second data subunit is stored in a primary memory sub-module's second partition, and wherein the first data subunit is selectively stored to either a first or second partition of the spare memory sub-module, and wherein the spare DRAM has a granularity that allows the spare DRAM to accept repaired data from multiple repair actions that resulted in multiple data steers, and wherein all subsequent reads and writes for data originally stored in the defective portion of the memory sub-module are made to the first data subunit of the unit of data, and wherein the second data subunit is reserved for storage of new data.