Patent ID: 7746117

Claim:
A complementary energy path adiabatic logic, comprising: a power clock network comprising at least one stage including a P-type MOS transistor member, an N-type MOS transistor member, a first P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor, and a second P-type MOS transistor; an evaluation network comprising at least one stage including a P-type MOS transistor element and an N-type MOS transistor element, with the evaluation network being connected to an output of the at least one stage of the power clock network; a power clock connected to inputs of the first P-type MOS transistor and the second N-type MOS transistor; and an inverted complementary power clock connected to inputs of the second P-type MOS transistor and the first N-type MOS transistor, wherein an output of the first P-type MOS transistor is connected to an output of the second P-type MOS transistor, an output of the first N-type MOS transistor is connected to an output of the second N-type MOS transistor, the output of the first P-type MOS transistor is connected to a last stage of the at least one stage of the power clock network, and the output of the first N-type MOS transistor is connected to the last stage of the at least one stage of the power clock network; and wherein the evaluation network evaluates the output of the at least one stage of the power clock network as the power clock and the inverted complimentary power clock operate.