Patent ID: 6965526

Claim:
An electrically erasable and programmable memory comprising: a memory array organized in sectors, each sector comprising memory cells linked to bit lines and to word lines, the memory cells linked to a same word line forming one page of the memory array, the memory cells linked to a same bit line being subjected to an electrical stress cycle upon each programming operation of another memory cell linked to the same bit line; at least one counter for controlling and for refreshing pages of the memory array, comprising data forming tokens usable once before the counter is erased, each token corresponding by its rank in the counter to at least one address of a page to be controlled; and control and refresh means for managing the counter and arranged for controlling and, if necessary, refreshing pages designated by the counter, characterized in that: each sector includes a control and refresh counter that is integrated into the sector and memory cells linked to the bit lines of the sector; and the control and refresh means are arranged for erasing a counter after reaching a maximum counting value that is chosen so that, when this maximum counting value is reached, memory cells of the counter have undergone a number of electrical stress cycles that is at the most equal to a determined number.