Patent ID: 7489581

Claim:
A semiconductor memory, comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of word lines corresponding to the rows of memory cells, each of the word lines being connected to memory cells of a corresponding one of the rows; a plurality of bit line pairs corresponding to the columns of memory cells, each of the bit line pairs being connected to memory cells of a corresponding one of the columns; a plurality of high-data retaining supply line pairs corresponding to the columns of memory cells; a plurality of write circuits each of which drives a corresponding one of bit lines of the plurality of bit line pairs; and a plurality of high-data retaining supply circuits each connected to a corresponding one of high-data retaining supply lines of the plurality of high-data retaining supply line pairs, wherein each of the plurality of memory cells include a first inverter connected to one of high-data retaining supply lines which constitute one of the high-data retaining supply line pairs corresponding to the memory cell, a second inverter connected to the other one of the high-data retaining supply lines which constitute the corresponding high-data retaining supply line pair, an input and output of the second inverter being connected to an output and input of the first inverter, respectively, a first access transistor connected between one of bit lines which constitute one of the bit line pairs corresponding to the memory cell and the output of the first inverter and connected to one of the word lines corresponding to the memory cell, and a second access transistor connected between the other one of the bit lines which constitute the corresponding bit line pair and the output of the second inverter and connected to the word line to which the first access transistor is connected, and a selected one of the high-data retaining supply circuits receives a signal determined according to an input data signal and address signal without the intervention of any of the bit lines which constitute the bit line pairs to drive one of the high-data retaining supply lines connected to the selected high-data retaining supply circuit such that the driven high-data retaining supply line has a potential corresponding to the received signal.