Patent ID: 8438519

Claim:
A method of manufacturing an integrated circuit, comprising: specifying a design layout for said integrated circuit, said design layout including proposed dimensions of a plurality of vias and leads in or on one or more interlayer dielectrics of said integrated circuit, and locations of via nodes formed by intersection of said vias and said leads; and performing an electromigration reliability rule-check for at least one of said via nodes by using a computer, including: calculating a net modified effective current density of said via node, including determining a sum of modified effective current densities for individual leads that are coupled to said via node, wherein: said leads configured to transfer electrons away from said via node are assigned one of a positive or negative polarity of said modified effective current density, said leads configured to transfer electrons towards said via node are assigned the other of the positive or negative polarity of said modified effective current density, and said modified effective current density for each individual lead has a value that is substantially equal to a product of a current density passed through the individual lead multiplied by a relative importance factor determined by one or more of: a) a branch interaction effect, which includes a modification of a current density value of a lead (J lead ) related to electromagnetic (“EM”) reliability due to the presence of barriers in the lead's current path; b) a width effect, wherein the relative importance factor of the width effect equals the width of the individual lead divided by the width of the narrowest lead of the via node, and c) a length effect, based on properties of the individual lead to generate a modified effective current density; said length effect assigned a value ranging from greater than zero to one, based on one of three different rules: long, short, and mixed length of the individual lead as compared to a threshold length of back stress effects to occur; comparing said calculated net modified effective current density to a target effective current density for said via node, and changing said design layout such that said calculated net effective current density is within said target effective current density, if said comparing reveals that said calculated net modified effective current density is outside of said target effective current density for said via node wherein said modified effective current density for at least one of said leads is equal to a simulated current density multiplied by a branch interaction factor having a value ranging from greater than zero to one, and wherein said branch interaction factor is equal to one when said lead is located in an uppermost interlayer dielectric layer of said integrated circuit, and said branch interaction factor is between one and zero when said lead is located in an underlying interlayer dielectric layer of said integrated circuit and said lead intersects with a bottom diffusion barrier layer of an overlying via.