Patent ID: 8549262

Claim:
A computer system, comprising: a register file for storing and retrieving operands addressed by register addresses; an execution unit for executing instructions, the execution unit configured to receive a source operand from the register file and write a result back into the register file; an address sequence detection logic configured to receive and store a first least significant portion of a first register address from a first instruction, and to receive a second least significant portion of a second register address from a second instruction, and to detect whether the address sequence detection logic has received a particular sequence of least significant portions of register addresses, and to generate a speculative most significant portion of the second register address and concatenate it with the second least significant portion of the second register address to yield the full second register address, and to provide the second full register address to the register file; the first instruction and the second instruction having unique opcodes to be used by the address sequence detection logic during sequence detection; and an instruction decode logic configured to decode instructions and provide the first least significant portion of the first register address from the first instruction and the second least significant portion of the second register address from the second instruction to the register address sequence detection logic.