Patent ID: 7646631

Claim:
A memory device comprising: access circuitry comprising an isolation device, the access circuitry having a thermal impedance; a bit line structure comprising a bit line, the bit line structure having a thermal impedance; a memory member comprising a memory material having at least two solid phases; a first interface structure coupling the memory member to the access circuitry and having a first thermal impedance; a second interface structure coupling the memory member to the bit line structure and having a second thermal impedance; and bias circuitry for applying a reset pulse to the access circuitry and to the bit line structure, the reset pulse having a pulse length; wherein the thermal impedance of the access circuitry and the thermal impedance of the bit line structure are such that the temperature of the access circuitry and the temperature of the bit line structure remain relatively constant during the pulse length of the reset pulse, and the first and second thermal impedances are essentially equal such that applying the reset pulse results in a phase transition of an active region of the memory member spaced away from both the first and second interface structures.