Patent ID: 7224757

Claim:
A comparator having a signal input and a signal output, said comparator comprising: a first latch connected to the signal input, said first latch being adapted to be enabled to produce a first latch output signal in response to a signal on the signal input by a given clock signal having a given phase and a given cycle period T c ; delay means providing a delay T E such that T c /2>T E >0; a second latch connected to said first latch and adapted to be enabled to produce a second latch output signal in response to a second latch input signal produced using said first latch output signal by a first delayed clock signal having a first lag time T L ; and a third latch adapted to be enabled to supply a third latch signal to the signal output in response to said second latch output signal by a second delayed clock signal, said second delayed clock signal having a second lag time T S , said second delayed clock signal being provided to the third latch in cooperation with the delay means, such that T S =T c /2+T E .