Patent ID: 7485930

Claim:
A low capacitance device structure with associated parasitic bipolar transistor on a substrate for the purpose of providing four-way electrostatic voltage discharge protection to a plurality of active semiconductor devices connected to an I/O logic circuit line and including ESD protection of a power bus system comprising: isolation elements defining an active circuit area; a first and second FET gate element upon said substrate surface; a plurality of first, second and third doped regions of opposite dopant than said substrate, wherein said plurality of first doped regions form a source element and a drain element for said first FET gate element forming a first NFET device and said plurality of second doped regions form a source region and a drain region for said second FET gate element forming a second NFET device; a plurality of fourth and fifth doped regions within said substrate of similar dopant as said substrate; an electrical connection system for said first, second, third, fourth and fifth doped regions; a surface passivation layer for said ESD protection device.