Patent ID: 7723806

Claim:
A memory cell, comprising: a substrate comprising two cross-coupled inverters and first and second pass-gate transistors formed therein, the inverters having a data storage node and a complementary date storage node coupled to first terminals of the first and second pass-gate transistors; a bit line and a complementary bit line disposed over the substrate and electrically connected to second terminals of the first and second pass-gate transistors respectively; two first power lines covering the bit line and the complementary bit line respectively, wherein longitudinal axes of the first power lines, the bit line and the complementary bit line are parallel to each other; and two third power lines, having a longitudinal axis perpendicular to the longitudinal axes of the bit line and the complementary bit line, wherein the third power lines are disposed under the first power lines and the first power lines and the third power lines are electrically connected to a fixed power voltage to form a power grid.