Patent ID: 7539847

Claim:
A processor system comprising: a main processor having an instruction fetch unit fetching an instruction to be executed from an instruction memory, an instruction decode unit decoding an instruction to be executed; and an instruction execution unit executing an basic instruction to be executed in said main processor side, said main processor performing a pipeline processing by using said instruction fetch unit, said instruction decode unit, and said instruction execution unit; and a coprocessor coupled to said main processor and having another instruction execution unit executing an extended instruction to be executed in said coprocessor side, the number of stages of said another instruction execution unit being larger than the number of stages of said execution unit in said main processor when an frequency flag indicates that a high speed clock signal is provided to said processor system, wherein said main processor ceases said pipe line processing for a preliminarily determined period without responding to a wait signal from said coprocessor, when said frequency flag indicates that a high speed clock signal is provided to said processor system and said instruction decode unit decodes said extended instruction.