Patent ID: 8760181

Claim:
A semiconductor system for identifying stacked chips, comprising: a first semiconductor chip configured to generate a plurality of counter codes by using an internal clock or an external input clock and to transmit slave address signals and the plurality of counter codes through a through-chip via; and a plurality of second semiconductor chips each configured to be given corresponding identifications (IDs) by separately latching a corresponding one of the plurality of counter codes transmitted from the first semiconductor chip, to compare the latched counter codes with the slave address signals, and to communicate data with the first semiconductor chip through the through-chip via according to the comparison result, wherein the first semiconductor chip comprises: a slave controlling unit configured to generate the slave address signals by buffering/latching an address signal and a command signal in response to the external input clock: an external clock generating unit configured to generate an external clock in response to the external input clock; an internal clock generating unit configured to generate an internal clock in response to the external input clock; a clock controlling unit configured to select one of the external clock and the internal clock, and to output the selected clock; a clock driving unit configured to generate a driving clock for identifying the plurality of second semiconductor chips in response to the output clock of the clock controlling unit; and a command controlling unit configured to generate a latch enable signal for identifying the plurality of second semiconductor chips in response to the driving clock and an enable signal, and to provide the latch enable signal to the clock driving unit and the plurality of second semiconductor chips.