Patent ID: 7290127

Claim:
A system comprising: a peripheral controller comprising a core processing circuit, an internal data bus coupled to the core processing circuit, registers formed in one of a cache memory array associated with the core processing circuit and a memory coupled to the core processing circuit through the internal data bus, and at least one address translation unit coupled to the internal data bus; and a host processing system coupled to the core processing circuit through an external data bus, the host processing system comprising: a host bridge coupled to the external data bus; logic to maintain the core processing circuit in a reset state during power up of the core processing circuit; logic to initiate one or more write bus transactions at the address translation unit to load a reset vector to one or more of the registers at a boot address associated with the core processing circuit while the core processing circuit is in the reset state, the reset vector comprising one or more instructions to fetch additional instructions to initialize the core processing circuit upon release from the reset state; a system memory coupled to the host bridge; logic to set the address translation unit to enable at least one outbound transaction to address at least one location in the system memory to fetch instructions from the system memory in response to requests from the core processing circuit, wherein the reset vector comprises at least one instruction to fetch data from the system memory via the host bridge, the address translation unit being configured to convert an internal data bus address associated with the outbound transaction to an external data bus address and configured to forward the outbound transaction from the internal data bus coupled to the core processing circuit to the external data bus coupled to the system memory via the host bridge; and logic to initiate one or more read bus transactions at the address translation unit addressed to the system memory in response to execution of the reset vector upon release from the reset state.