Patent ID: 7425483

Claim:
A method of fabricating a semiconductor structure comprising: providing a substrate by a layer transfer process, said substrate comprising an upper semiconductor material of a first crystallographic orientation and a lower semiconductor material of a second crystallographic orientation separated by a buried insulating layer, said first crystallographic orientation is different from said second crystallographic orientation; protecting a portion of said substrate to define a first semiconductor region, while leaving another portion of the substrate unprotected and defining a second semiconductor region; first etching said unprotected portion of the substrate to expose a surface of said buried insulating layer utilizing a first mask that defines an active area within the second semiconductor region, wherein said first etching selectively removes at least said first semiconductor material from said second semiconductor region, stopping atop said buried insulating layer; second etching said exposed surface of said buried insulating layer to expose said lower semiconductor material utilizing a second mask that has at least one opening that provides a window that is smaller in size than the active area; epitaxially growing a semiconductor material within said second semiconductor region on said exposed lower semiconductor material, said regrown semiconductor material having said second crystallographic orientation, wherein during initial stages of said epitaxially growing process a counter-doped region is formed within said at least one opening, said counter-doped region comprising an upper P-type doped region, a middle N-type doped region, and a lower P-type doped region, wherein said upper P-type doped region has a higher concentration of P-type dopant than the lower P-type doped region; forming an isolation region separating said first semiconductor region form said second semiconductor region; and forming at least one field effect transistor in each of said semiconductor regions, wherein said counter-doped region is formed at a source area of an overlying nFET or a drain area of an overlying pFET.