Patent ID: 8530302

Claim:
A method for manufacturing a CMOS FET, comprising: 1) forming a first interfacial SiO 2 layer having a thickness of about 4-12 angstroms on a semiconductor substrate; 2) forming a first Hf-based high-K gate dielectric, and performing a thermal annealing at a temperature of about 400-1050° C. for about 4-120s in N 2 ; 3) depositing a first metal gate on the first Hf-based high-K gate dielectric, forming a first hard mask of amorphous silicon on the first metal gate, patterning the first hard mask of amorphous silicon by lithography and etching the first hard mask, and selectively etching off the portions of the first metal gate and the first Hf-based high-K gate dielectric that are not covered by the first hard mask in sequence; 4) forming a second interfacial SiO 2 layer having a thickness of about 4-12 angstroms on the semiconductor substrate, forming a second Hf-based high-K gate dielectric, and performing a thermal annealing at a temperature of about 400-600° C. for about 4-120s in N 2 ; 5) depositing a second metal gate on the second Hf-based high-K gate dielectric, forming a second hard mask of amorphous silicon on the second metal gate, patterning the second hard mask of amorphous silicon by lithography and etching, etching the portions of the stack of the second metal gate and the second Hf-based high-K gate dielectric that are not covered by the second hard mask of amorphous silicon in sequence to expose the first hard mask of amorphous silicon on the first metal gate, and removing the first hard mask of amorphous silicon and the second hard mask of amorphous silicon simultaneously by wet etching using an aqueous solution of NH 4 OH; 6) forming a polysilicon layer and a third hard mask, and performing lithography and etching to form a gate stack; and 7) after cleaning, depositing and etching a dielectric layer to form first spacers, performing a conventional ion implantation with a large tilt angle and a low energy, depositing and etching a dielectric layer to form second spacers, performing an ion implantation for source/drain and an activation annealing to form source/drain regions, and providing contact and metallization by silicides.