Patent ID: 8294721

Claim:
A processor for three dimensional computer graphics that comprises: a control unit, pluralities of execute units and lines, wherein the control unit comprises a decoder, a program interface, and n units of process controllers, the n being an integer that is greater than or equal to 2, wherein the decoder decodes one or pluralities of orders simultaneously and outputs orders that the decoder decodes to the program interface wherein the program interface outputs the orders that the decoder decodes to the n units of process controllers, wherein each of the process controllers outputs a control signal that corresponds to any one of the pluralities of execute units based on the orders that the decoder decodes, wherein each of the pluralities of execute units comprises a processing part, a register, and a data pass control part for executing 2 or more orders simultaneously, wherein the processing part comprises pluralities of processing circuits, each of the pluralities of processing circuits comprises a multiplexer and an adder, wherein the register comprises pluralities of register areas divided based on pluralities of register addresses, wherein each of the pluralities of register areas corresponds to any one of the n units of process controllers, wherein the lines connect the control unit and the pluralities of execute units, wherein the control signal comprises information on a register address for designating a register area at which a transaction is executed, and information on processing which is executed at the processing part, wherein the execute units decide the register area based on the register address which is included in the control signal, and decides the processing circuits, in the processing part that are used at one clock based on the information on processing included in the control signal, and wherein the data pass control part determines a processing circuit which is used at the one clock by using information regarding the processing circuit which is used at the one clock thereby preventing two or more processing circuits to process more than two orders at the one clock.