Patent ID: 7936010

Claim:
A power MOS transistor of the planar type, comprising: a semiconductor body having a first and a second surface, body regions of a first conductivity type and a first dopant concentration formed in the first surface; a highly doped source region of a second conductivity type having a first dopant concentration, provided at the first surface; a contact arrangement provided at the first surface, the contact arrangement comprising a gate electrode over an insulating layer on the first surface and source electrode, directly over the first surface and in contact with the source region; at least two deep, lightly doped well regions of the first conductivity type having a second dopant concentration, and having a minimum lateral distance therebetween; a highly doped drain contact layer of the second conductivity type and a second dopant concentration provided in or on the second surface of the semiconductor body; and an electrode provided on the free surface of the drain contact layer; wherein underneath and between the deep well regions of the first conductivity type a lightly doped drift and buffer layer of the second conductivity type and a third dopant concentration is provided, wherein the drift and buffer layer has a minimum vertical extension between the drain contact layer and the bottom of the deepest well region which is at least equal to the minimum lateral distance between the deep well regions wherein the vertical extension of the drift and buffer layer amounts to at least twice the minimum lateral distance between the deep well regions; and wherein the vertical extension of the drift and buffer layer between the drain contact layer and the bottom of the deepest well region is determined such that a total amount of its dopants per unit area is larger than a breakdown charge amount.