Patent ID: 8786014

Claim:
A vertical channel transistor array, comprising: a plurality of semiconductor pillars disposed in a semiconductor substrate and arranged in a column and row array, an active area of a vertical channel transistor being defined by the semiconductor pillars; a plurality of embedded bit lines disposed in parallel in the semiconductor substrate and extended in a column direction, the embedded bit lines being electrically connected to the semiconductor pillars in the same column; and a plurality of embedded word lines disposed in parallel above the embedded bit lines and extended in a row direction, the embedded word lines and the semiconductor pillars in the same row being connected and spaced by a gate dielectric layer, wherein each of the embedded word lines is connected to first sides of the semiconductor pillars in the same row, not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides; and only one embedded word lines is correspondingly connected to the semiconductor pillars arranged in one row.