Patent ID: 7362156

Claim:
A phase adjustment circuit that receives a first pair of clock signals and outputs a second pair of clock signals with phases satisfying a predetermined condition to a central processing unit, comprising: a clock proliferator that receives a first clock signal and generates a plurality of clock signals therefrom; a clock selector that receives said plurality of clock signals from the clock proliferator, selects one of the received plurality of clock signals in accordance with a selection signal, and outputs a selected clock signal; and a phase difference detector that receives the selected clock signal and a second clock signal differing in frequency from the first clock signal and the selected clock signal, determines whether the phase of the second clock signal and the phase of the selected clock signal satisfy the predetermined condition, and outputs a detection signal indicating whether the predetermined condition is satisfied; the first clock signal and the second clock signal constituting the first pair of clock signals; the second clock signal and the selected clock signal constituting the second pair of clock signals; wherein the selected clock signal has a lower frequency than the second clock signal, and the predetermined condition specifies that all rising and falling edges of the selected clock signal occur while the second clock signal is high.