Patent ID: 8621149

Claim:
An apparatus comprising: an instruction translation lookaside buffer (ITLB) to translate virtual addresses to physical addresses; and an instruction cache having: a data array that includes a plurality of sets each comprising a corresponding plurality of ways, each of the ways to store a corresponding executable instruction and a privilege level indicator of the corresponding executable instruction; a first logic, distinct from the ITLB, to select a first set from the plurality of sets based on address information associated with a read request received from a core for a first executable instruction; a second logic, distinct from the first logic and from the ITLB, to mask access to each way of the first set that stores a corresponding privilege level indicator that does not match a processor privilege level and to include in a first subset of the first set each way of the first set that stores a corresponding privilege level indicator that matches the processor privilege level, wherein the ways of the first subset are accessible; and a third logic, distinct from the first logic, the second logic, and the ITLB, to select a first way of the first subset that stores the first executable instruction associated with the read request and to enable access by the core to the first executable instruction stored in the first way, wherein selection of the first way is based at least in part on physical tag information associated with the read request.