Patent ID: 7649748

Claim:
A multilayer printed wiring board comprising: a built-up portion in which a plurality of wiring patterns stacked with insulating layers therebetween are electrically connected to each other through via holes provided in the insulating layers; a mounting portion on which a semiconductor device electrically connected to the wiring patterns can be mounted and which includes first pads each connected to one of a ground electrode and a power supply electrode of the semiconductor device, and second pads each connected to the other of the ground electrode and the power supply electrode of the semiconductor device; and a layered capacitor portion which is provided between the mounting portion and the built-up portion, which includes a ceramic high-dielectric layer, a first layered electrode, and a second layered electrode, the first layered electrode and the second layered electrode sandwiching the high-dielectric layer and having different electric potentials, and in which the first layered electrode is electrically connected to the first pads so as to have the same electric potential as the first pads and the second layered electrode is electrically connected to the second pads so as to have the same electric potential as the second pads, wherein the ratio of the number of first rod-shaped conductors, each of which constitutes at least a part of a conducting path that electrically connects the first pads to a ground line or a power supply line of the wiring patterns and which passes through the second layered electrode in a non-contact manner, to the number of the first pads is in the range of 0.05 to 0.7, and the ratio of the number of second rod-shaped conductors, each of which constitutes at least a part of a conducting path that electrically connects the second pads to the power supply line or the ground line of the wiring patterns and which passes through the first layered electrode in a non-contact manner, to the number of the second pads is in the range of 0.05 to 0.7.