Patent ID: 7818706

Claim:
A semiconductor integrated circuit device including a plurality of macro cells in a chip, said semiconductor integrated circuit device comprising: a VDD ring-shaped conductor; a GND ring-shaped conductor, wherein the VDD and GND ring-shaped conductors are electrically connected to VDD and GND connections of the macro cells that lie outside the VDD and GND ring-shaped conductors, and wherein the GND and VDD ring-shaped conductors define as a mid part of the chip a portion of the chip that lies inside both the GND and VDD ring-shaped conductors; a clock input terminal in the mid part of the chip constructed and arranged to receive a clock signal from outside of the device; and a clock signal generating circuit in the mid part of the chip that is electrically connected to said clock input terminal, the clock signal generating circuit being constructed and arranged to supply an internal clock signal, based on said clock signal, to at least a fraction of said plural macro cells that lie outside of the GND and VDD ring-shaped conductors.