Patent ID: 7197725

Claim:
A semiconductor integrated circuit comprising: a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, wherein the clock control portion outputs the output clock signal of a predetermined number of pulses to the internal circuit when a certain time period has passed from a time when the output command signal is received, and the clock control portion stops the output clock signal automatically after outputting the output clock signal of the predetermined number of pulses, wherein the clock control portion selectively outputs the generated clock signal from the clock generation portion or an external clock signal from the outside of the semiconductor integrated circuit according to a clock switching signal, and wherein the generated clock signal from the clock generation portion is used for a normal operation mode of a scan test and the external clock signal is used for a shift operation mode.