Patent ID: 7880514

Claim:
An output buffer, adapted to a source driver, comprising: a first differential input stage, having a first terminal for receiving a first input signal, and a second input terminal for receiving a second input signal, wherein a first current and a second current are respectively induced in the first differential input stage according to the first input signal and the second input signal; a primary output stage, comprising: a first output stage, coupled to the first differential input stage for providing at least one first level voltage according to the first input signal and the second input signal, the first output stage comprising: a level adjustment circuit, generating the first level voltage according to a first level current mirrored from the first current or the second current; and a bias providing circuit, providing a first biased voltage to control the level adjustment circuit based on the second current; and a second output stage, driving an output terminal of the output buffer coupled to the first terminal of the first differential input stage to a target level under the control of the first level voltage; and a secondary output stage, comprising: a comparator, coupled to the first differential input stage for comparing the first current with the second current, and thereby generating a control voltage, the comparator further comprising: a first comparing circuit, coupled to the first differential input stage for comparing the first current with the second current, and thereby generating a first control voltage to control a third output stage; and a second comparing circuit, coupled to the first differential input stage for comparing the first current with the second current, and thereby generating a second control voltage to control the third output stage, wherein the first comparing circuit and the second comparing circuit have different driving abilities, and the first control voltage and the second control voltage have a voltage offset; and the third output stage, driving the output terminal of the output buffer to the target level under the control of the control voltage.