Patent ID: 8039298

Claim:
A method of forming a phase changeable memory cell array region, comprising: forming a lower interlayer insulating layer on a semiconductor substrate; forming a plurality of conductive plugs through the lower interlayer insulating layer; forming a phase changeable material pattern on the lower interlayer insulating layer, the phase changeable material pattern covering at least two of the plurality conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions; forming an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer; forming conductive patterns through the upper interlayer insulating layer; and electrically connecting the conductive patterns to a plurality of predetermined regions in the plurality of first regions.