Patent ID: 7111214

Claim:
A method of testing a programmable logic device (PLD), the PLD including a plurality of lookup tables (LUTs) and an associated carry chain, each LUT having K inputs, where K is an integer, the carry chain comprising a chain of carry multiplexers and providing a carry chain output signal, wherein each carry multiplexer in the carry chain is controlled by an output signal from one of the LUTs, the method comprising: a) storing a first bit pattern in each LUT; b) configuring the carry chain to perform a wide AND function of the output signals of the LUTs; c) cycling, after configuring the carry chain to perform a wide AND function, the K inputs of each LUT through all possible input combinations while comparing the carry chain output signal to an expected value and reporting the PLD faulty if the carry chain output signal differs from the expected value; d) configuring the carry chain to perform a wide OR function; e) cycling, after configuring the carry chain to perform a wide OR function, the K LUT inputs of each LUT through all possible input combinations while comparing the carry chain output signal to an expected value and reporting the PLD faulty if the carry chain output signal differs from the expected value; f) storing a second bit pattern in each LUT, wherein the second bit pattern is the complement of the first bit pattern; and g) repeating steps (b) through (e).