Patent ID: 7973371

Claim:
A semiconductor integrated circuit device including static random access memory (SRAM) cells, each comprising: a first p-well region in which a first transfer transistor and a first driver transistor are formed; a second p-well region in which a second transfer transistor and a second driver transistor are formed; an n-well region which is located between the first p-well region and the second p-well region, and in which a first load transistor and a second load transistor are formed, the first load transistor being connected between a power supply potential interconnection and the first driver transistor, and the second load transistor being connected between the power supply potential interconnection and the second driver transistor; a first tap p-diffused layer for supplying a potential to the first p-well region; and a second tap p-diffused layer for supplying the potential to the second p-well region, wherein the first and second tap p-diff-used layers are arranged substantially symmetrical with respect to a center of a layout of the SRAM cell, and the first and second tap p-diffused layers are connected to each other with a first metal interconnection, at least a part of which passes over the n-well region in the SRAM cell.