Patent ID: 7840874

Claim:
A processor comprising: a first processor core including logic operative to retrieve and store instructions and data from a system memory and logic operative to execute the instructions to process the data; a first cache memory connected with the first processor core and with the system memory and operative to store a copy of at least a subset of the instructions and the data, wherein the first cache memory includes a plurality of cache lines, each cache line including at least a tag data field operative to store tag data, a cache data field operative to store a portion of the subset of the instructions and data, and a tag error data field operative to store an error detection and/or correction code for at least a portion of the cache line including the tag data field; and a cache controller including cache tag comparison logic operative to determine if at least one selected cache line matches a cache request received from the first processor core, wherein the cache tag comparison logic comprises: a cache tag comparator unit operative to compare a first tag data in the tag data field of the selected cache line with a request tag associated with the cache request and to output a provisional cache hit or provisional cache miss signal; an error code processing logic operative to evaluate at least the first tag data and a first error detection and/or correction code in the tag error data field of the selected cache line to output an error signal in response to the presence of at least one bit error in at least a portion of the selected cache line including the first tag data; and tag comparison logic connected with the cache tag comparator unit and the error code processing logic and operative to output a cache hit signal in response to the provisional cache hit signal and the absence of the error signal and to output the cache miss signal in response to the error signal.