Patent ID: 7558933

Claim:
A method of accessing synchronous dynamic random access memory (SDRAM), comprising: receiving an SDRAM command and a column address for a data read or write of a burst of data units, from a memory accessing device, each data unit in said burst having an expected bit size; receiving a first clock signal at a first clock rate; generating n SDRAM commands from said received SDRAM command and n column memory addresses from said received column address, wherein n>1; generating from said first clock signal a second clock signal at a second clock rate equal to n times said first clock rate; generating and sequentially accessing said synchronous dynamic random access memory using said n SDRAM commands at said second clock rate, to read or write n bursts of data at said n column memory addresses, wherein each of said n bursts of data has a bit size equal to 1/nth said expected bit size; and further comprising receiving a row address, and presenting said row address to said synchronous dynamic random access memory between two of said n column addresses.