Patent ID: 8354750

Claim:
A semiconductor device, comprising: a semiconductor substrate; a bonding pad on the semiconductor substrate; a stress buffer structure partially covering the bonding pad while exposing a portion of the bonding pad, said stress buffer structure comprising a stepwise wall that extends, in steps, upwardly from the exposed portion of the bonding pad; and an under-bump metallurgy (UBM) layer on the exposed portion of the bonding pad and on the stepwise wall, said UBM layer conforming in shape to said stepwise wall; wherein the stepwise wall comprises an upper step and a lower step; a height of the upper step is equal to or higher than a height of the lower step; said stress buffer structure comprises a passivation layer comprising a first stepwise wall; and a stress buffer polymer layer on the passivation layer and comprising a second stepwise wall conforming in shape to said first stepwise wall; the bonding pad comprises a third stepwise wall, and the first and second stepwise walls conform in shape to said third stepwise wall.