Patent ID: 6936893

Claim:
A power semiconductor device comprising: a semiconductor active layer; a first base layer of a first conductivity type disposed in the active layer; a plurality of trenches disposed in a surface of the active layer at intervals to partition a main cell and a dummy cell, and to reach the first base layer; a collector layer of a second conductivity type disposed on the first base layer, at a position remote from the trenches; a second base layer of the second conductivity type disposed in the main cell and on the first base layer; an emitter layer of the first conductivity type disposed on the second base layer; a buffer layer of the second conductivity type disposed in the dummy cell and on the first base layer; a gate electrode disposed in each trench to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer; a collector electrode disposed on the collector layer; an emitter electrode disposed on the second base layer and the emitter layer; and a partition structure disposed in the surface of the active layer to electrically isolate the buffer layer from the emitter electrode, wherein the partition structure comprises dummy cell end walls, which bridge ends of the trenches one on either end of the dummy cell and cooperate with the trenches to surround the dummy cell.