Patent ID: 7096296

Claim:
A method comprising: receiving input/output (I/O) completions from a plurality of data paths, the plurality of data paths including first processor data paths for I/O completions resulting from I/O requests initiated by a first processor, and a write data path for I/O completions resulting from I/O requests initiated by a second processor; storing the I/O completions in a plurality of registers, each register being configured to store an I/O completion from one of the plurality of data paths; transferring the I/O completions from the plurality of registers to a plurality of logical blocks of a random access memory, each logical block being configured to store I/O completions from one of the plurality of data paths, wherein each respective register and each respective logical block are associated with a respective predetermined one of the plurality of data paths; and processing the I/O completions stored in the plurality of logical blocks using the first processor, including the I/O completions resulting from the I/O requests initiated by the second processor.