Patent ID: 8796076

Claim:
A fabrication method of providing stacked semiconductor devices from a semiconductor wafer having multiple chip areas and dicing areas, comprising the steps of: forming a surface protection and adhesive layer onto a circuit side of the semiconductor wafer; forming an opening through the surface protection and adhesive layer to expose respective electrode pads on the circuit side of the multiple chip areas and the dicing areas; partitioning the semiconductor wafer into a plurality of individual chips that include first and second semiconductor chips; positioning a non-circuit side of the semiconductor wafer on a support sheet; holding a first semiconductor chip on a suction collet and removing the first semiconductor chip from the support sheet, positioning the first semiconductor chip on an adhesive layer of a receiving substrate, and heating the receiving substrate to bond the first semiconductor chip to the receiving substrate; and holding a second semiconductor chip on the suction collet and removing the second semiconductor chip from the support sheet, positioning the second semiconductor chip directly on the surface protection and adhesive layer of the first semiconductor chip, and bonding the first semiconductor chip to the second semiconductor chip, wherein the suction collet has a suction side with lower adhesion to the surface protection and adhesive layer than that between the first semiconductor chip and the second semiconductor chip.