Patent ID: 7459931

Claim:
A programmable logic device comprising: a plurality of logic blocks; a plurality of registers, wherein the logic blocks and the registers are within a user programmable logic area; a plurality of input/output blocks, wherein the plurality of input/output blocks include boundary scan cells adapted to precondition the registers with desired signal values, prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration of the programmable logic device, such that the registers provide the desired data values after the reconfiguration; configuration memory cells adapted to store first configuration data for configuration of the logic blocks and the input/output blocks of the programmable logic device; a volatile memory block adapted to store data within the programmable logic device; and a circuit adapted to preserve the data for the volatile memory during the reconfiguration of the programmable logic device, wherein the circuit comprises: a non-volatile memory block adapted to store data transferred from the volatile memory block prior to the reconfiguration and return the data to the volatile memory block prior to entering user mode after the reconfiguration, wherein the non-volatile memory block is further adapted to store second configuration data and transfer the second configuration data to the configuration memory cells for the reconfiguration of the programmable logic device; and a control circuit adapted to control transfer of the data between the non-volatile memory block and the volatile memory block and further adapted to control transfer of the second configuration data to the configuration memory cells.