Patent ID: 7803660

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a wiring board having a plurality of product regions, and a plurality of semiconductor chips mounted on the plurality of product regions, respectively, wherein each of the plurality of product regions has a main surface, a plurality of first conductor patterns formed on the main surface, a first insulating layer formed over the plurality of first conductor patterns such that a part of each of the plurality of first conductor patterns is exposed from the first insulating layer, a back surface opposing to the main surface, a plurality of second conductor patterns formed on the back surface, and a second insulating layer formed over the plurality of second conductor patterns such that a part of each of the plurality of second conductor patterns is exposed from the second insulating layer, wherein the plurality of first conductor patterns are electrically connected with the plurality of second conductor patterns via a plurality of through holes, respectively, and wherein the first and second insulating layers are comprised of a film type material, respectively; (b) disposing the wiring board on a main surface of a lower die such that all of the plurality of semiconductor chips are arranged inside of a cavity formed on a main surface of an upper die in a plane view, wherein the main surface of the upper die is facing in a direction opposite to that of the main surface of the lower die, wherein the cavity has pairs of first edges, and pairs of second edges intersecting with the first edges, wherein a plurality of gate portions are formed along one of the first edges such that each of the plurality of gate portions connects with the cavity, wherein a plurality of first holes are formed on the main surface of the lower die such that the plurality of first holes are arranged along the first edges of the cavity in a plane view, wherein a pitch of the plurality of first holes is narrower than that of the plurality of product regions, and wherein the number of the plurality of first holes arranged along the one of the first edges is less than that of the plurality of first holes arranged along another of the first edges; (c) clamping a peripheral portion of the wiring board by the upper die and the lower die, wherein the peripheral portion of the wiring board is outside of the plurality of product regions in a plane view; (d) injecting molding resin into the cavity via the plurality of gate portions; (e) opening the upper die and the lower die, and removing the wiring board from between the upper die and the lower die; and (f) cutting a plurality of dicing areas between the plurality of product regions of the wiring board.