Patent ID: 7509613

Claim:
An integrated circuit comprising: a plurality of rows of cells, each row of cells comprising: a plurality of logic cells each having a conductive trace positioned at a first predetermined distance relative to a common border of the logic cell and laid out along a predetermined direction, the logic cells being laid out abutting each other such that the conductive traces form a power rail along a length of the logic cells; a switch cell comprising: a first conductive trace abutting the power rail; a second conductive trace spatially separated from the first conductive trace, and wherein the second conductive trace being laid out also at the first predetermined distance relative to the common border; and a transistor providing a selectably enabled conduction path between the first conductive trace and the second conductive trace; and a tap cell positioned within a second predetermined distance from the switch cell and the logic cells, so as to provide a substrate connection to a power supply or ground rail; and wherein the power rails of the rows of cells are interconnected by conductive traces running in a direction orthogonal to the predetermined direction, and wherein the tap cells of the rows of cells are aligned to provide portions of the conductive traces interconnecting the power rails.