Patent ID: 8169837

Claim:
A semiconductor memory device, comprising: a bit line equalizing signal generating unit, configured to drive an output terminal with a first supply voltage during a first activation period at the beginning of a period where a bit line equalizing signal is enabled, and to drive the output terminal with a second supply voltage higher than the first supply voltage during a second activation period following the first activation period, thereby outputting the bit line equalizing signal; and a bit line equalizing unit configured to equalize a bit line pair in response to the bit line equalizing signal, wherein the bit line equalizing signal generating unit includes: a pulse signal generating unit configured to generate a pulse signal pulsing in a certain period by delaying an enable signal that is enabled corresponding to an active period, wherein the certain period corresponds to the second activation period; a drive controlling unit configured to generate a first pull-up drive signal that is enabled during the first activation period, a second pull-up drive signal that is enabled during the second activation period, and a pull-down drive signal that is enabled during an inactivation period of the bit line equalizing signal in response to the pulse signal and the enable signal; and a driving unit configured to drive the output terminal in response to the first and second pull-up drive signals and the pull-down drive signal, wherein the enable signal is enabled in response to an active signal and is disabled in response to a precharge signal.