Patent ID: 7177893

Claim:
A circuit for determining a result (s k+2 ) of an operation of a type s k + 2 = ( s k ⁢ + ∘ ⁢ a k ) ⁢ + ∘ ⁢ a k + 1 , where s k , a k , and a k+1 respectively are first, second, and third operands represented in a form of signed fractional numbers coded over n bits, the circuit comprising: first means for determining a positive and negative parts of the third operand (a k+1 ); second means for calculating a first sum (s) equal to the sum of the first, second, and third operands (s k , a k , a k+1 ), a second sum (s′) equal to a sum of the negative part of the third operand and of a maximum signed fractional number coded over n bits, and a third sum (s″) equal to the sum of the positive part of the third operand and of a minimum fractional signed number coded over n bits; third means for calculating a first (S′) and a second (S″) indicators, the first indicator (S′) being equal to a first value if s k +a k +a k+1 >max n+a − k+1 and equal to a second value otherwise, the second indicator (S″) being equal to a third value if s k +a k +a k+1 <min n+a + k+1 and equal to a fourth value otherwise, max n being a value of the maximum fractional signed number coded over n bits, min n being a value of the minimum fractional signed number coded over n bits, a + k+1 being the positive part of the third operand (a k+1 ) and a − k+1 being the negative part of the third operand (a k+1 ); and fourth means for providing the first sum if the first indicator is equal to said first value, providing the second sum if the second indicator is equal to said third value, and providing the third sum in the other cases.