Patent ID: 8856478

Claim:
An arithmetic processing unit connected to a main memory, comprising: a cache memory comprising hardware and having a plurality of cache lines in which part of data held in the main memory is held, the cache memory being a store-in cache; a tag memory comprising hardware and that holds, in the plurality of cache lines, a tag address used to search for the data held in the plurality of cache lines and a flag indicating validity of the data held in the plurality of cache lines; an instruction control unit that issues a cache line fill instruction before (i) issuing a store instruction for initializing a predetermined area in the main memory or (ii) issuing a store instruction for copying data in a predetermined area in the main memory to another area in the main memory; an instruction execution unit that executes the cache line fill instruction on a cache line corresponding to a specified address corresponding to the predetermined area of the main memory and that executes a store instruction on the specified address; a cache memory control unit that, (a) when the instruction execution unit executes the cache line fill instruction and the specified address is not cached in the cache memory, registers all zero data in a cache line of the cache memory which has a tag address corresponding to the specified address and validates a flag in the cache line having the tag address corresponding to the specified address, (b) when the instruction execution unit executes the cache line fill instruction and the specified address is cached in the cache memory, does not register all zero data nor validate the flag; (c) holds the specified address until registration of the all zero data in the cache line having the tag address corresponding to the specified address and validation of the flag in the cache line having the tag address corresponding to the specified address are completed; (d) inhibits execution of a memory access instruction on the specified address executed by the instruction execution unit while the specified address is held, and (e) releases inhibition of the execution of the memory access instruction on the specified address executed by the instruction execution unit after the completion of the registration of the all zero data and the validation of the flag, wherein the instruction execution unit executes the store instruction after the cache memory control unit releases the inhibition of the execution of the memory access instruction on the specified address.