Patent ID: 7668037

Claim:
A storage circuit, comprising: a plurality of identical storage cells forming an array having rows and columns, wherein the storage cells in the columns are connected by bitlines, wherein at least one bitline corresponding to each column is connected to a corresponding one of a plurality of column read circuits for providing a read output signal for each column, and each row has a corresponding wordline select input connected to the storage cells in a corresponding row; a pre-charge circuit for pre-charging the bitlines in response to a de-asserted state of a local clock signal; wordline control logic for activating the wordline select input of a selected row in response to an asserted state of the local clock signal; and a programmable clock control logic for generating the local clock signal from a global clock signal and including at least one delay circuit having an adjustable delay, wherein a timing of the local clock signal is adjusted in conformity with at least one control value, whereby operational timing margins of the array of identical storage cells is adjustable.