Patent ID: 7561462

Claim:
A DRAM circuit, comprising: a plurality of memory cells arranged in arrays and coupled to word lines and to local bit lines, each memory cell comprising a storage capacitor, each memory cell coupled to one word line and one local bit line of a pair of the local bit lines, the local bit lines being arranged in pairs of local bit lines and complementary local bit lines; sense amplifiers each having a pair of differential sense nodes, each sense amplifier physically connected to a pair of the local bit lines with a first sense node coupled to a bit line and a second sense node coupled to the respective complementary local bit line, for sensing a differential voltage placed on the local bit lines by a memory cell and for amplifying the differential voltage to a larger differential voltage; equalizer circuits coupled to each pair of local bit lines and operable to couple a predetermined voltage onto the bit lines and to couple the bit lines together responsive to a control signal; read select circuits coupled to each pair of local bit lines and each operable to couple the respective local bit line and the respective complementary local bit line to a global bit line and a complementary global bit line, responsive to a read select signal; and write select circuits physically connecting each pair of local bit lines to the global bit line and to the complementary global bit line responsive to a write select signal.