Patent ID: 8101986

Claim:
A DRAM-incorporated semiconductor device comprising: a semiconductor substrate comprising a DRAM portion and a logic portion thereon; a first transistor formed in said DRAM portion and comprising source and drain regions and a metal silicide layer comprising one of cobalt silicide and nickel silicide formed on said source and drain regions; a second transistor having a conductivity type which is the same as a conductivity type of the first transistor, and formed in said logic portion and comprising source and drain regions, said metal silicide layer being formed on said source and drain regions of said second transistor; a third transistor formed in said logic portion and having a conductivity type which is different than the conductivity type of the first and second transistors, and comprising source and drain regions, said metal silicide layer being formed on said source and drain regions of said third transistor; an interlayer film covering said DRAM portion and logic portion of said semiconductor substrate; a capacitor formed on said interlayer film in said DRAM portion and comprising a lower electrode; and plural contact plugs comprising a metal, said plural contact plugs being formed in said interlayer film in said DRAM portion and said logic portion, wherein said source and drain regions of said first, second and third transistors comprise first and second diffusion regions, said second diffusion region comprising a lightly-doped region and said first diffusion region comprising a highly-doped region having an impurity density which is greater than an impurity density of said second diffusion region, wherein said metal silicide layer is formed on a substantially entire surface of said highly-doped region of said source and drain regions of said transistors in the DRAM and logic portions, an interface between said metal silicide layer and said substantially entire surface of said highly-doped region of said source and drain regions in said DRAM and logic portions being located under a main surface of said substrate, and wherein said plural contact plugs are in physical contact with said metal silicide layer on said highly-doped region of said source and drain regions of said first, second and third transistors in said DRAM portion and said logic portion, and with said lower electrode of said capacitor, an interface between said plural contact plugs and said metal silicide layer being formed at said main surface in said DRAM portion and said logic portion.