Patent ID: 8514612

Claim:
A semiconductor memory device comprising: a memory cell array with a plurality of memory cells arranged in a matrix and each having a first port and a second port; a first bit line coupled to the first port; a second bit line coupled to the second port; a first write driver operable to apply voltage corresponding to first write data to the first bit line when activated; and a first write assist driver operable to apply voltage corresponding to the first write data to the second bit line when activated, wherein a row of the memory cell array for a first access is specified by a first row address through the first port, wherein a row of the memory cell array for a second access is specified by a second row address through the second port, and wherein the first write assist driver is activated at least on condition that the first write driver is activated and that the first row address is coincident with the second row address; the semiconductor memory device further comprising: a second write driver operable to apply voltage corresponding to second write data to the second bit line when activated; and a second write assist driver operable to apply voltage corresponding to the second write data to the first bit line when activated, wherein the second write assist driver is activated at least on condition that the second write driver is activated and that the first row address is coincident with the second row address; the semiconductor device further comprising: a first internal clock generator operable to generate a first internal clock signal which is activated for a predetermined period, in response to a first clock signal for the first access from the exterior; a second internal clock generator operable to generate a second internal clock signal which is activated for a predetermined period, in response to a second clock signal for the second access from the exterior; a first internal row address latch operable to latch, on the basis of the first internal clock signal, a signal for specifying a first row address inputted from the exterior, and operable to generate a first internal row address signal; a second internal row address latch operable to latch, on the basis of the second internal clock signal, a signal for specifying a second row address inputted from the exterior, and operable to generate a second internal row address signal; and a row address coincidence detection circuit operable to detect whether a row address specified by the first internal row address signal is coincident with a row address specified by the second internal row address signal.