Patent ID: 7321504

Claim:
A memory array coupled to an input line and further coupled to an output line, the memory array comprising: a plurality of digit lines; a plurality of memory cells coupled to the plurality digit lines, each memory cell having a latch having an inverter and a tri-state inverter, the inverter having an input coupled to an output of the tri-state inverter and further having an output coupled to an input of the tri-state inverter and the tri-state inverter having an enable node to which a read signal is applied and configured to generate an output signal that is the complement of an input signal in response to an active read signal, each memory cell further having an access transistor having a first node coupled to the output of the tri-state inverter and having a second node coupled to a respective digit line, the access transistor further having a gate at which an access signal is applied and configured to couple the first and second nodes in response to an active access signal; and a plurality of amplifier circuits having a digit node coupled to a respective one of the plurality of digit lines, an input node coupled to the input line, and an output node coupled to the output line, each amplifier circuit having a first pair of series coupled tri-state inverters coupled between the input line and the respective digit line and a second pair of series coupled tri-state inverters coupled between the respective digit line and the output line, each amplifier circuit configured to capture write data coupled to the input line prior to writing the write data to at least one memory cell coupled to the respective digit line and further configured to capture read data coupled to the respective the digit line prior to coupling the read data to the output line.