Patent ID: 7009897

Claim:
A semiconductor memory device comprising: a control circuit controlling a normal operation and a test operation of said semiconductor memory device; a memory cell array having a plurality of memory cells arranged in rows and columns; a plurality of bit line pairs provided to correspond to said columns of said memory cell array; a plurality of data line pairs each provided to correspond to a predetermined number of said plurality of bit line pairs; a write circuit operative in said normal operation in response to data provided external to said semiconductor memory device to be written, to drive a level in potential of said data line pair; a test potential drive circuit controlled in said test operation by said control circuit to drive a level in potential of said data line pair instead of said write circuit; and a column select circuit operative in said normal operation in response to an address signal and controlled in said test operation by said control circuit to select said column of said memory cells and transmitting said level in potential of said data line pair to said bit line pair corresponding to said selected column of said memory cells.