Patent ID: 7003643

Claim:
A burst mode counter for use with a 2-bit prefetch memory device having an odd memory array designated by an odd column address and an even memory array designated by an even column address, the burst mode counter comprising: a pre-settable column address counter changing count responsive to a clock signal, the counter having a starting count input receiving all but the least significant bit of a starting column address from which the counter increments or decrements, the counter further including a counter control input terminal receiving a counter control signal having a first value causing the counter to increment responsive to the clock signal or a second value causing the counter to decrement responsive to the clock signal; and a counter control circuit receiving a mode signal having a first value indicative of a serial mode of operation and a second value indicative of an interleave mode of operation, the counter control circuit further receiving the least significant bit (“LSB”) and the next to least significant bit (“NLSB”) of the starting column address, the counter control circuit being operable to decode a value of “1” for the LSB and the first value of the mode signal and to generate the second value of the counter control signal responsive thereto, to decode a value of “1” for the NLSB and the second value of the mode signal and to generate the second value of the counter control signal responsive thereto, and to generate the first value of the counter control signal responsive to decoding other values of the LSB, NLSB and the mode signal.