Patent ID: 7281094

Claim:
A processor comprising: one or more processing units, each processing unit configured to process data within the processor; a temporary storage unit in communication with the one or more processing units, the temporary storage unit comprising: a plurality of input flip-flops configured to receive data from the one or more processing units; a multi-port register file having one or more write ports and two or more read ports; and a plurality of output flip-flops configured to transmit data to the one or more processing units; wherein each of the one or more write ports of the multi-port register file comprises multiple pairs of write bitlines in communication with the plurality of input flip-flops, and each of the two or more read ports of the multi-port register file comprises multiple read bitlines in communication with the plurality of output flip-flops; and wherein the multi-port register file comprises an array of bitcells, each bitcell having a balanced configuration in which an equal number of read bitlines are connected on each side of a signal driving circuit, and each of the pairs of write bitlines comprises a first write bitline connected to a first side of the signal driving circuit and a second write bitline connected to a second side of the signal driving circuit, the signal driving circuit comprising parallel branches of oppositely-directed drivers.