Patent ID: 7084682

Claim:
A delay-locked loop circuit comprising: a phase frequency detector configured to receive an input clock signal, a feedback signal and an initialization signal, and configured to generate an up signal and a down signal according to a phase difference and a frequency difference between the input clock signal and the feedback signal, upon control of the initialization signal; a charge pump configured to receive the up signal, the down signal and a coarse lock detection signal, and configured to generate a current signal that varies with states of the up signal, the down signal and the coarse lock detection signal; a loop filter configured to receive the current signal from the charge pump circuit, and configured to filter the current signal through a low-pass filter to generate a dc voltage signal; a voltage controlled delay line configured to receive the input clock signal and the dc voltage signal, and configured to generate the feedback signal and control signals in response to the dc voltage signal, the feedback signal being obtained by delaying the input clock signal by a predetermined period, and the control signals having different phase; and a coarse lock detector configured to receive the control signals from the voltage controlled delay line and configured to generate the initialization signal and the coarse lock detection signal to control the phase frequency detector and the charge pump circuit so that Td is adjustable within a range of Tin/2<Td<2×Tin when Td is smaller than Tin/2 or greater than twice Tin, wherein Tin represents a period of the input clock signal and Td represents a delay time thereof.