Patent ID: 7917730

Claim:
A multi-chip processor apparatus, comprising: a first substrate; a plurality of processor chips situated on the first substrate, at least one of the plurality of processor chips including: a plurality of compute elements situated on a second substrate attached to the first substrate; a plurality of off-chip I/O interfaces distributed along a perimeter of the second substrate; a primary interconnect trunk, situated along a first axis of the second substrate and coupled to the compute elements, that communicates information to and from the compute elements; a secondary interconnect trunk, situated along a second axis of the second substrate and intersecting the primary interconnect trunk to form an intersection with the primary interconnect trunk, the secondary interconnect trunk communicating information to and from the plurality of off-chip I/O interfaces to enable off-chip communication, the second axis being substantially perpendicular to the first axis; and a bus control element, situated at the intersection of the primary and secondary interconnect trunks, the bus control element including a primary trunk interface that couples to the primary interconnect trunk at the intersection to enable the bus control element to control on-chip communication among the compute elements via coherency signals on the primary interconnect trunk, the bus control element including a secondary trunk interface that couples to the secondary interconnect trunk at the intersection to enable the bus control element to control off-chip communication via coherency signals on the secondary interconnect trunk.