Patent ID: 7061046

Claim:
A semiconductor memory device comprising: a semiconductor body provided with a basic doping and having a main surface; an array of bitline conductor tracks arranged over said main surface, said bitline conductor tracks being arranged parallel to one another and electrically insulated from said semiconductor body; an array of wordlines arranged over said main surface, said wordlines being arranged above said bitline conductor tracks parallel to one another in a direction across said bitline conductor tracks and being electrically insulated from said bitline conductor tracks and from said semiconductor body; a memory layer sequence being arranged at least in regions that are adjacent to one of said wordlines and one of said bitline conductor tracks, wherein said memory layer sequence is formed as sidewall spacers at lateral sides of said bitline conductor tracks, each spacer being arranged between one of said bitline conductor tracks and an adjacent lower part of one of said wordlines which forms a gate electrode; regions located within said semiconductor body beneath said bitline conductor tracks and provided for induced bitlines to be generated by an electric potential that is applied to said bitline conductor tracks; and doped regions provided underneath at least one end of each of said bitline conductor tracks and electrically connected to an addressing circuit.