Patent ID: 7448011

Claim:
A layout method of a semiconductor integrated circuit, where cells are arranged on a substrate, comprising: an arrangement process for arranging the cells on the substrate based on cell layout information which is composed of a plurality of same logic cells with similar driving capability, same-sized cell frame and terminals at same positions; a wiring process for generating wiring to connect between arranged cells; an extraction process for extracting wiring resistance and/or wiring capacitance of a path between the cells based on wiring layout information obtained in the wiring process; a timing examination process for examining timing of the path between the cells based on the values of the wiring resistance and/or wiring capacitance; and a cell replacement process for replacing cells, corresponding to a path determined to be an error in the timing examination process, with other same logic cells comprising terminals at the same positions as those in a cell frame with the same size, and different driving capability, and wherein other cells are arranged in a redundant region in a cell frame of a cell with low driving capability among a plurality of the cells with the same logic and similar driving capability.