Patent ID: 7282959

Claim:
A CMOS circuit comprising: a P-type four-terminal double-insulated-gate field-effect transistor comprising a first source region, a first drain region, and a first channel region provided between the first source region and the first drain region; a first silicon layer including first and second portions, in which the first channel region are sandwiched between the first and second portions; a first gate oxide film provided on the first portion of the first silicon layer; a first gate electrode provided on the first gate oxide film; a second gate oxide film provided on the second portion of the first silicon layer; and a second gate electrode provided on the second gate oxide film; and an N-type four-terminal double-insulated-gate field-effect transistor comprising a second source region, a second drain region, and a second channel region provided between the second source region and the second drain region; a second silicon layer including third and fourth portions, in which the second channel region are sandwiched between the third and fourth portions; a third gate oxide film provided on the third portion of the second silicon layer; a third gate electrode provided on the third gate oxide film; a fourth gate oxide film provided on the fourth portion of the second silicon layer; and a fourth gate electrode provided on the fourth gate oxide film wherein the first and second gate electrodes of the P-type four-terminal double-insulated-gate field-effect transistor are connected to each other and are connected to the third gate electrode of the N-type four-terminal double-insulated-gate field-effect transistor, in order to form an input terminal of the CMOS circuit, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the fourth gate electrode of the N-type four-terminal double-insulated-gate field-effect transistor.