Patent ID: 7039781

Claim:
A flash memory system comprising: (A) a flash memory comprising more than one physical block including more than one page, each page having (a) a fixed memory capacity and (b) three states, namely, blank, enabled, and disabled states; (B) an address conversion section for converting a logical address entered from the outside into one of the corresponding physical addresses of said pages; (C) a read section for reading data from said enabled page; (D) a write section for writing data onto each of said blank pages; (E) an erase section for collectively erasing data in each of said physical blocks; (F) a page-disabling section for disabling said enabled pages; and (G) a merge control section for, when said write section writes new data, (a) counting the number of said physical blocks including only said blank pages (which are hereafter referred to as blank physical blocks); (b) selecting a source among said physical blocks in the case of the number of said blank physical blocks smaller than a first threshold value; (c) selecting, as a source page, said enabled page belonging to said source physical block and substantially as many as said pages on which said new data is written; (d) copying data on said source page onto said blank page using said read and write sections; (e) disabling said source page using said page-disabling section; (f) selecting said physical block including none of said enabled pages as a erasing target physical block; and (g) performing erasing of data using said erase section for the erasing target physical block, only in the case of said erasing target physical block selected.