Patent ID: 7317650

Claim:
A semiconductor memory comprising: a plurality of memory cells; a bit line connected to said memory cells; a sense amplifier connected to said bit line; a partial area composed of a first memory cell of said memory cells; an operation control circuit for operating any of said memory cells selected in accordance with an address signal, during normal operation mode in which a read operation and a write operation are performed, and for keeping latching data retained by said first memory cell into said sense amplifier, during low power consumption mode in which data only in said first memory cell is retained; a plurality of word lines connected to said memory cells, respectively, said word lines being selected in accordance with said address signal, wherein said operation control circuit further comprises: a word line control circuit for selecting any of said word lines in accordance with said address signal during said normal operation mode, and for enabling selection of a partial word line which is one of said word lines and disabling selection of the other word lines during said low power consumption mode, said partial word line being connected to said first memory cell; and a sense amplifier control circuit for keeping activating said sense amplifier during said low power consumption mode; and further wherein said word line control circuit keeps selecting said partial word line during said low power consumption mode; and a booster for supplying a boost voltage to said work lines, wherein at the start of said low power consumption mode, said booster stops its boosting operation after said sense amplifier latches data.