Patent ID: 8552956

Claim:
A liquid crystal display comprising: a control board including a clock generator generating a first input clock signal and then a second input clock signal, and a level shifter shifting the first and second input clock signals and generating clock signals whose voltages decrease stepwise from a gate high voltage, to a modulation voltage that is lower than the gate high voltage, to a gate low voltage that is lower than the modulation voltage; and a liquid crystal panel that includes data lines, gate lines intersecting the data lines, TFTs provided at intersections of the data lines and the gate lines, and a gate shift register sequentially supplying a gate pulse to the gate lines in response to the clock signals input from the level shifter, wherein the level shifter comprises: a shift register configured to shift the first and second input clock signals; and a modulation control circuit configured to generate the clock signal which is supplied to the gate shift register, wherein the clock signal is generated as the gate high voltage in synchronization with a rising edge of the first input clock signal, the gate high voltage of the clock signal is lowered to the modulation voltage in synchronization with a rising edge of the second input clock signal, and the modulation voltage of the clock signal is lowered to the gate low voltage in synchronization with a falling edge of the first input clock signal and a falling edge of the second input clock signal, and wherein a pulse width of the first input clock signal is set to be greater than that of the second input clock signal.