Patent ID: 8829573

Claim:
A semiconductor device with minimized current flow differences comprising: a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, wherein the second layer is on top of the first layer; a plurality of mesas formed in the semiconductor layer stack; and a plurality of gates formed in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, wherein the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device; wherein the plurality of gates are formed via dopant implantation of the semiconductor layer stack, the dopant implantation of the semiconductor layer stack occurs while the plurality of mesas have a plurality of masks thereon that are each wider than each mesa, the masks cover and protect the plurality of mesas from the dopant implantation, and the spacing of the gates between each other is increased by masking an area greater in width than the plurality of mesas and narrowing the area available for the dopant implantation, whereby the plurality of gates are formed with increased spacing between each of the gates; and wherein the plurality of mesas formed in the semiconductor layer stack are free of implanted dopants prior to, during, and subsequent to the dopant implantation.