Patent ID: 6891273

Claim:
A semiconductor package, comprising: a substrate having a front surface and a back surface opposite to the front surface, the front surface being formed with a chip attach area and a plurality of bond fingers around the chip attach area; at least one chip mounted on the chip attach area, the chip having an active surface and a non-active surface, wherein the active surface of the chip is formed with a plurality of electric contacts each of which corresponds to one of the bond fingers; a dielectric layer applied over the front surface of the substrate for covering the active surface of the chip and the front surface of the substrate, with the electric contacts and bond fingers being exposed to outside of the dielectric layer; a plurality of conductive traces formed on the dielectric layer for electrically connecting the electric contacts to the bond fingers; an insulating layer for covering the electric contacts, conductive traces, and bond fingers; and a plurality of solder balls implanted on the back surface of the substrate for electrically connecting the chip to an external device.