Patent ID: 7516173

Claim:
A method of operation of a multi-bit adder, comprising: selectively propagating, generating, or killing carry-in bits along a carry chain; summing equivalent bit positions of a first operand, a second operand, and the carry-in bits to obtain a first portion of a multi-bit resultant, the first portion including an intermediate bit position and less significant bit positions than the intermediate bit position; generating control signals based on the first and second operands; logically XORing the intermediate bit position of the carry-in bits with the control signals to determine a second portion of the multi-bit resultant if the intermediate bit position does not generate a carry-out, the second portion including more significant bit positions than the intermediate bit position; and summing equivalent bit positions of the first operand, the second operand, and the carry-in bits to obtain the second portion of the multi-bit resultant, if the intermediate bit position does generate the carry-out.