Patent ID: 8032720

Claim:
A memory access controlling apparatus for monitoring an access of a memory to generate a target watch signal, the apparatus comprising: at least one monitoring circuit, corresponding to an address of the memory and holding an access setting value, wherein the monitoring circuit monitors the access of the memory according to the access setting value to generate a watch signal; a setting unit, holding a setting value for triggering an exception, the setting value for triggering the exception being related to a condition for triggering the exception while the memory is accessed; and an output circuit, coupled to the monitoring circuit and the setting unit, for generating the target watch signal according to the watch signal and the setting value; wherein the access setting value comprises at least a specific memory range and at least a specific access operation for the memory, and the specific memory range overlaps other specific memory ranges; and wherein when the setting value is a first logic value, the condition for triggering the exception is met when access of the memory complies with an access range and an access operation setting value for triggering the exception; when the setting value is a second logic value, the condition for triggering the exception is met when the access of the memory does not comply with the access range or the access operation setting value.