Patent ID: 7971042

Claim:
A microprocessor architecture having decoupled fetch-execution cycles for at least two instruction pipelines, comprising: a main instruction pipeline operating at a first clock frequency; and an extended instruction pipeline, wherein the main instruction pipeline is configured to issue: a begin record instruction to the extended instruction pipeline, causing the extended instruction pipeline to begin recording a sequence of instructions issued by the main instruction pipeline; and a single instruction comprising a starting address of the sequence of recorded instructions to the extended instruction pipeline, causing the extended instruction pipeline to execute the sequence of recorded instructions; wherein the single instruction or the begin record instruction causes the extended instruction pipeline to switch to an autonomous mode of operation from a main instruction pipeline controlled mode of operation, wherein operating in the autonomous mode of operation comprises fetching and executing instructions from the sequence of recorded instructions independent from the main instruction pipeline, through a front end portion of the extended instruction pipeline, the front end portion of the extended instruction pipeline operating at a second clock frequency that is different from the first clock frequency, thereby decoupling the fetch-execution cycles of the main instruction pipeline from the extended instruction pipeline.