Patent ID: 7205198

Claim:
A method of manufacturing an array of non-volatile memory cells in a substantially single crystalline semiconductive substrate material of a first conductivity type, wherein said array of non-volatile memory cells has a plurality of non-volatile memory cells arranged in a plurality of rows and columns in said semiconductive substrate material with each cell for storing a plurality of bits, said method comprising: forming spaced apart isolation regions on said semiconductive substrate that are substantially parallel to one another and extend in said column direction, with an active region between each pair of adjacent isolation regions, wherein said semiconductive substrate has a surface; forming a plurality of memory cells in each of the active regions, wherein each memory cell for the storage of a plurality of bits, wherein the formation of each of the memory cells includes: forming a first and a second spaced apart trenches into the surface of the substrate, each of said first and second trenches having a sidewall and a bottom wall; forming a first region and a second region in said bottom wall of said first and second trenches, respectively, with said first region and said second region being of a second conductivity type, different from said first conductivity type, with a channel region for the conduction of charges connecting said first region and said second region; said channel region, having a first portion, a second portion and a third portion; forming a dielectric on said channel region; forming a first floating gate on said dielectric, in said first trench spaced apart from said sidewall of said first trench and from said first portion of said channel region; said first portion of said channel region adjacent to said first region, said first floating gate for the storage of at least one of said plurality of bits; forming a second floating gate on said dielectric, in said second trench spaced apart from said sidewall of said second trench and from said second portion of said channel region; said second portion of said channel region adjacent to said second region, said second floating gate for the storage of at least another of said plurality of bits; forming a gate electrode on said dielectric, spaced apart from said third portion of said channel region, said third portion of said channel region between said first portion and said second portion; forming a first gate electrode in said first trench, said first gate electrode insulated from said first region and capacitively coupled to said first floating gate; and forming a second gate electrode in said second trench, said second gate electrode insulated from said second region and capacitively coupled to said second floating gate.