Patent ID: 7620804

Claim:
A pipelined central processing unit (CPU) architecture, comprising: a local memory configured to store a sequence of instructions including a first instruction, immediately followed by a branch instruction, immediately followed by a second instruction, and a branch target instruction that is specified by the branch instruction; and a CPU coupled to the local memory and including a first pipeline with multiple pipeline stages and a second pipeline with multiple pipeline stages, the first pipeline configured to: fetch the first instruction, the branch instruction, and the branch target instruction, decode the first instruction, the branch instruction, and the branch target instruction, execute the first instruction and the branch instruction, wherein execution of the branch instruction produces a branch instruction result that is either a hit or a miss, and execute the branch target instruction only when the branch instruction result is a hit, and the second pipeline configured to: fetch the second instruction, decode the second instruction, and execute the second instruction only when the branch instruction result is a miss and discard the second instruction when the branch instruction result is a hit, wherein the second pipeline is further configured to decode the second instruction one clock cycle after the branch target instruction is decoded by the first pipeline and one clock cycle after the branch instruction is executed.