Patent ID: 8859373

Claim:
A manufacturing method of a high voltage device, comprising: providing a substrate, wherein the substrate has an upper surface; forming a drift region below the upper surface, and forming a mitigation region below the drift region, wherein the drift region and the mitigation region are defined by one same lithography mask; forming a gate on the upper surface of the substrate after the drift region and the mitigation region are formed; and forming a source and a drain at both sides of the gate below the upper surface respectively, which are separated by the gate, wherein the drain and the gate are separated by the drift region; wherein the drift region, the mitigation region, the source and the drain have a same conductive type, and the drift region has a side closer to the source than other portions of the drift region, wherein a vertical distance between a lowest surface of this side of the drift region and the mitigation region is one to five times of a depth of the drift region, and wherein the mitigation region does not extend underneath the source.