Patent ID: 7724575

Claim:
A non-volatile memory device, comprising: a memory cell array which includes a plurality of non-volatile memory cells; an input data bus which inputs data to be programmed into the non-volatile memory cells of the memory cell array; an output data bus which is separate from the input data bus and which outputs data read from the non-volatile memory cells of the memory cell array; a latch circuit for temporarily storing data read from and programmed into the non-volatile memory cells of the memory cell array; an internal data output line connected to the output data bus; a latch input path, connected to the input data bus, which sets the latch circuit when data is to be programmed into the non-volatile memory cells of the memory cell array, wherein the latch input path is electrically isolated from the internal data output line; and an output drive circuit, connected to the latch circuit and the internal data output line, which transfers read data temporarily stored in the latch circuit to the internal data output line.