Patent ID: 7488682

Claim:
A method of fabricating an interconnect structure comprising: providing an interconnect structure of a dual damascene-type that comprises a lower dielectric material having at least one conductive interconnect located within an interconnect area of said lower dielectric material and at least one other conductive interconnect located within a lithographically defined feature within a resistor area of said lower dielectric material; selectively removing a portion of a conductive material of the at least one other conductive interconnect from the resistor area, while leaving a diffusion baffler material on wall portions of said lithographically defined feature within said resistor area and at least another portion of the conductive material within a lower portion of the lithographically defined feature, said diffusion barrier material forming a resistive element in the resistor area; depositing an upper dielectric material on said lower dielectric material in both said interconnect area and said resistor area, said upper dielectric material fills said lithographically defined feature within said resistor area and is located atop a surface of said at least another portion of the conductive material within the lower portion of the lithographically defined feature in the resistor area; and forming an upper conductive interconnect including another diffusion barrier material in said upper dielectric material in both said interconnect area and said resistor area.