Patent ID: 7981782

Claim:
A method of fabricating a semiconductor device having a well of a first conductive type arranged in a semiconductor substrate, first kind of transistors and second kind of transistors arranged in the well and spaced apart from a boundary of the well to a different space, wherein the first and second kind of transistors are connected to a pair of bit lines and operate symmetrically, the method comprising: forming a photoresist pattern that exposes a region of a semiconductor substrate, wherein the photoresist pattern has a thickness from 0.5 μm to 5.0 μm; and implanting dopant ions into a portion of the exposed region of the semiconductor substrate that directly borders the photoresist pattern at a tilt angle selected to account for the presence of the photoresist pattern, the tilt angle selected from a range of approximately 4.4° to 6.9° such that a portion of the dopant ions collides with a side wall of the photoresist pattern that directly borders the portion of the expose region and the portion of the exposed region is implanted with the dopant ions without causing channeling in the semiconductor substrate.