Patent ID: 7072825

Claim:
A method for processing a hardware description language (HDL) testbench describing an electronic device under best (DUT), describing a time-varying behavior of a plurality of test signals, and identifying a plurality of probe points within the DUT, to determine how response signals appearing at the identified probe points would behave if the test signals were to be applied as inputs to the DUT, the method comprising the steps of: a. providing a plurality of first emulation resources for emulating portions of the DUT, wherein each first emulation resource produces output signals in response to input signals with logical relationships between each first emulation resource's input and output signals being controlled by programming data supplied as input to that first emulation resource; b. providing first signal paths between the first emulation resources so that they can transmit output signals to and receive input signals from one another; c. providing a packet routing network for conveying packets; d. connecting a first transaction device to the packet routing network and to each of the first emulation resources, wherein each first emulation resource has associated therewith a unique network address; and e. transmitting a packet to the first transaction device via the packet routing network, wherein the packet includes a network address identifying one of the first emulation resources, a command, and data, and wherein the first transaction device responds to the command by communicating with the identified first emulation resource via at least one of its input and output signals.