Patent ID: 6933597

Claim:
A stacked multi-chip module comprising: a first semiconductor die having an active surface with a plurality of I/O pads; a second active semiconductor die; a spacer having at least one passive device thereon, the spacer being situated between the first and second semiconductor die to provide a stacked chip arrangement and wherein the passive device is electrically coupled to at least one of the semiconductor die and the spacer is attached to the active surface of the first semiconductor die in a manner that leaves at least some of the I/O pads exposed; a carrier selected from the group consisting of a lead frame and a substrate, the carrier including electrically conductive contacts that are electrically coupled to the stacked chip arrangement, wherein the carrier is arranged to support the stacked arrangement; and a body that encloses the spacer, at least portions of the first and second semiconductor die and portions of the carrier while leaving the contacts exposed to facilitate electrical connection to external devices.