Patent ID: 7516365

Claim:
A computer-implemented method for implementing a split hardware transaction, comprising: initiating execution of an atomic block of code comprising two or more segments of code, wherein each segment comprises code to implement one or more memory accesses targeted to a shared memory space; for each segment of the atomic block, executing the segment as a hardware transaction, wherein in said executing the segment, executing any write accesses targeted to the shared memory space comprises writing values to a local memory space rather than to the shared memory space; subsequent to executing all of the two or more segments, determining if all values read by the atomic block of code are consistent with a current state of the shared memory space; and in response to determining that all values read by the atomic block are consistent with the current state of the shared memory space, committing results of the execution of the atomic block in the shared memory space, wherein in said committing results, atomicity is guaranteed across the atomic block; wherein said determining and said committing are performed by a single hardware transaction.