Patent ID: 7234004

Claim:
An apparatus for operating an I/O adapter in a computer system comprising at least one central processing unit (CPU) having a cache memory, wherein the CPU and the I/O adapter are connected through a connection network to a main memory containing program instructions and data, the I/O adapter receives I/O requests from the CPU and comprises doorbell register controlled by the CPU to allow the I/O adapter access to the main memory for performing read or write operations, the I/O adapter comprising: at least one I/O request mailbox for receiving I/O requests and data from the CPU; at least one I/O request queue storage, the I/O request storage connected to the I/O request mailbox, the I/O request storage storing a plurality of I/O requests and related data received by the I/O request mailbox; a credit register which, the credit register connected to the I/O request mailbox, the credit register storing a filling state of the I/O request queue storage; and wherein the connection network is designed and operated to: (a) transfer the contents of the credit register to the CPU for performing a check of the filling state of the I/O request queue storage, (b) transfer an I/O request and related data to a selected I/O request mailbox of the I/O adapter, and (c) activate the doorbell register for signalling to the I/O adapter to process the I/O request including access to the main memory by the I/O adapter if required.