Patent ID: 8023553

Claim:
A spread-spectrum clock signal generator circuit comprising: a delay circuit configured to receive a clock signal and provide a plurality of delayed clock signals based thereon; a pseudo-random clock selection signal generator configured to generate delayed clock selection signals responsive to the clock signal; and a multiplexer circuit coupled to the pseudo-random clock selection signal generator and the delay circuit and configured to pseudo-randomly select among the plurality of delayed clock signals; and a plurality of sequential devices coupled to the plurality of delayed clock signals and configured to sample an input signal at different time intervals responsive to the plurality of delayed clock signals to provide a sampled input signal to the multiplexer circuit, wherein the delay circuit comprises: a plurality of inverter stages coupled in serial with one another and including respective outputs to provide a respective delayed clock signal output; a plurality of pull-up loads coupled to respective inverter stages; and a plurality of pull-down loads coupled to the respective inverter stages.