Patent ID: 8051248

Claim:
A processor comprising: an execution core configured to execute instructions, wherein the execution core is configured to generate memory read and write operations responsive to instruction execution, and wherein the execution core is configured to generate transactional read and write operations responsive to executing transactional instructions; a level 1 (L1) data cache coupled to the execution core and configured to store data; a transient/transactional cache coupled to the execution core, wherein the transient/transactional cache is configured to cache memory data accessed responsive to memory read and write operations to identify potentially transient data and to prevent the identified transient data from being stored in the L1 data cache, and wherein the transient/transactional cache is configured to cache transaction data accessed responsive to transactional read and write operations to track transactions, and wherein each entry in the transient/transactional cache is usable for transaction data and for transient data at different points in time; and a tag memory corresponding to the transient/transactional cache, wherein the tag memory comprises a tag for each entry in the transient/transactional cache, and wherein the tag memory further comprises a cache state corresponding to each entry, and wherein the cache state indicates whether or not the data in the entry has been modified with respect to memory, and wherein the tag includes transaction tracking data and transient tracking data, and wherein the transaction tracking data comprises a transaction indication that identifies the entry as storing transaction data, and wherein the transaction tracking data comprises an updated indication that indicates whether or not the transaction data has been updated by one or more transactional write operations, wherein the updated indication is separate from the cache state.