Patent ID: 8020022

Claim:
A memory control circuit having a write leveling function and controlling read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection, the memory control circuit comprising: for each of the plurality of memories: a first variable delay unit delaying, in a write operation, a data strobe signal output to the memory by a first delay time that is set by utilizing the write leveling function; and a second variable delay unit delaying, in a read operation, a data signal input from the memory by a second delay time that is set based on the first delay time, wherein the first variable delay unit is constituted by a digital delay circuit which is made up of a plurality of unit circuits connected in series and which delays the data signal output to the memory by the first delay time by passing the data signal through a predetermined number of the unit circuits; and the second variable delay unit is constituted by the digital delay circuit which is made up of the plurality of unit circuits connected in series and which delays the data signal input from the memory by the second delay time by passing the data signal through a predetermined number of the unit circuits.