Patent ID: 6909144

Claim:
A semiconductor device including a MIS transistor comprising: a semiconductor substrate; a gate dielectric film provided above the semiconductor substrate; a gate electrode provided above the gate dielectric film; and a sidewall dielectric film provided on a side of the gate electrode; first impurity regions of a first conductive type, the first impurity regions constituting LDD regions; second impurity regions including an impurity of the first conductive type, the second impurity constituting source and drain regions; third impurity regions of the first conductive type below the first impurity regions; and fourth impurity regions of a second conductivity type provided adjacent to the third impurity regions, wherein the fourth impurity regions terminate at a lower edge of the first impurity regions, and wherein the third impurity regions are formed opposing to each other with a channel region being interposed therebetween, and a distance between the third impurity regions is greater than a distance between the first impurity regions.