Patent ID: 8659116

Claim:
An isolated lateral depletion-mode MOSFET formed in a semiconductor substrate of a first conductivity type, the isolated depletion-mode transistor comprising: a floor isolation region submerged in the substrate, the floor isolation region being of a second conductivity type opposite to the first conductivity type; a trench extending downward from a surface of the substrate, the trench having a bottom located in the floor isolation region, the trench and the floor isolation region together enclosing an isolated pocket of the substrate, a dielectric material lining the walls of the trench, a central portion of the trench containing a conductive material, the conductive material being in contact with the floor isolation region so as to provide an electrical connection to the floor isolation region; a MOSFET including a gate located atop a gate dielectric layer over the surface of the substrate in the isolated pocket, a channel region of the first conductivity type located at the surface of the substrate in the isolated pocket below at least a portion of the gate, the gate being electrically insulated from the channel region, and a source region of the second conductivity type at the surface of the substrate in the isolated pocket; a drift region of the second conductivity type located between the channel region and a drain region; and a submerged region of the first conductivity type disposed in the isolated pocket and extending laterally under the source region and the channel region and terminating at a location under the drift region, the submerged region of first conductivity type being electrically tied to the surface of the substrate by a contact region of the first conductivity type.