Patent ID: 6943084

Claim:
A method for manufacturing a semiconductor device on a SOI, the method comprising: (a) preparing a semiconductor wafer including a monocrystalline silicon layer formed on an insulating layer; (b) forming a device region by forming an isolation insulating layer on the monocrystalline silicon layer; (c) forming a gate dielectric layer in the device region and forming a gate conductive layer on the gate dielectric layer; (d) forming a gate pattern in the gate conductive layer; (e) forming insulating layer spacers at the sidewalls of the gate pattern; and (f) forming a source junction and a drain junction at either side of the gate pattern to be asymmetrical with respect to the gate pattern, wherein the drain junction is formed to a depth deeper than a depth of the source junction, wherein step (f) comprises: covering a drain region and implanting junction ions only into a source region to form the source junction, and covering the source region and implanting junction ions only into the drain region with an energy higher than the energy applied to implant ions into the source region to form the drain junction; and the ions implanted to form the reinforced drain junction are of the same conductivity type as the ions implanted to form the drain junction and the concentration of the reinforced drain junction ions is lower than the concentration of the drain junction ions.