Patent ID: 7693701

Claim:
A design structure embodied in a machine readable medium for designing, manufacturing, or testing a multiplexer (MUX) circuit, the design structure comprising: a logic gate; a plurality of pull-up transistors coupled in series between a reference voltage and an input of said logic gate; a plurality of current control elements with outputs coupled to said plurality of pull-up transistors and said input of said logic gate; a plurality of input signals coupled to respective inputs of said plurality of current control elements, wherein said plurality of input signals comprise a plurality of select signals and a plurality of corresponding data signals; wherein when a select signal exceeds a threshold value, the select signal deactivates a pull-up transistor and enables a data signal that corresponds to said select signal to provide input to said logic gate; and wherein when said select signal does not exceed said threshold value, the select signal activates said pull-up transistor and prevents said data signal from providing input to said logic gate.