Patent ID: 7369450

Claim:
A memory comprising: a plurality of memory cells, each of the plurality of memory cells coupled to a bitline of a plurality of bitlines and to a wordline of a plurality of word lines; and a sense amplifier for being selectively coupled to one of the plurality of bitlines, the sense amplifier comprising: a first precharge circuit for precharging a selected bitline to a first predetermined voltage in response to a first precharge signal; a current-to-voltage converter having a current input coupled to the selected bitline, and a voltage output, wherein the current input node is coupled to a sensed bitcell current path included within the current-to-voltage converter, wherein the sensed bitcell current path operates in parallel with the first precharge circuit, and wherein the first precharge circuit is not within the sensed bitcell current path; a latch circuit having a storage node coupled to the voltage output of the current-to-voltage converter; and a second precharge circuit for precharging the storage node of the latch circuit to a second predetermined voltage in response to a second precharge signal.