Patent ID: 7046493

Claim:
A input/output buffer protection circuit, comprising: an I/O pad; an I/O buffer, comprising a first PMOS transistor and a first NMOS transistor; an n-well control circuit coupled to an n-well of the first PMOS transistor and the I/O pad for raising the n-well of the first PMOS transistor to a input voltage level when the input voltage is greater than a source voltage; a gate control circuit coupled to a gate terminal of the first PMOS transistor and the n-well control circuit for raising the gate terminal of the PMOS transistor to the input voltage level when the input voltage is greater than the source voltage, the gate control circuit comprises a transistor for passing a control voltage to the gate of the PMOS transistor in output mode; and wherein the n-well control circuit comprising a protection component, providing a voltage drop down path from the gate of the transistor to the I/O pad and block the I/O pad signal flow back to the gate of the transistor.