Patent ID: 7573746

Claim:
An integrated circuit device capable of storing volatile data on common nodes in memory cells of a non-volatile memory cell array comprising: a non-volatile memory cell array comprising: column lines; row lines; and a plurality of memory cells arranged in rows and columns and coupled to the row lines and the column lines, each memory cell comprising a non-volatile device and a pull-up device connected at a common node; a means for setting the non-volatile devices of each of the memory cells to a desired state; a means for loading volatile data onto column lines of the non-volatile memory cell array; a means for biasing non-volatile devices in the memory cells of the non-volatile memory cell array to store volatile data from said column lines on the common nodes in the memory cells of the non-volatile memory cell array; and a means for biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state; wherein said means for biasing non-volatile devices in the memory cells of the non-volatile memory cell array is directed towards a second set of rows of the non-volatile memory cell array.