Patent ID: 7851857

Claim:
A lateral double diffusion MOS transistor device, comprising: a semiconductor substrate formed of a material having first conductivity type impurities; a first semiconductor region of a material having second conductivity type impurities formed over the semiconductor substrate; a first well region of a material having first conductivity type impurities formed adjacent to the first semiconductor region; a first source region of a material having second conductivity type impurities formed in a predetermined upper region of the first well region; a drain region of a material having second conductivity type impurities formed in a predetermined upper region of the first semiconductor region, the drain region being spaced a predetermined distance from the first well region; a gate electrode formed over a gate insulating layer and substantially adjacent to the source region, thereby defining a first channel region inside the first well region; and a current routing structure of material having first conductivity type impurities formed in the first semiconductor region, comprising a buried RESURF layer in ohmic contact with a second well region formed in a predetermined upper region of the first semiconductor region, where the second well region is completely covered by the gate electrode and where the current routing structure is spaced apart from the first well region and from the drain region on at least a side of the drain region to delineate separate current paths from the source region and through the first semiconductor region.