Patent ID: 8893122

Claim:
A computer comprising: an I/O control device controlling an I/O device; a logical partition in which an OS (Operating System) operates; a main storage device having a first logical storage area, which is assigned to the logical partition and stores data; a CPU, which is assigned to the logical partition as a logical CPU; a hypervisor assigning resources including the main storage device, the CPU, and the I/O device to the logical partition so that the logical partition occupies the I/O device, data being transmitted from the I/O device to the first logical storage area without interruption of the hypervisor; and a logging circuit which is a different entity from the hypervisor, and which has a plurality of entries, wherein the hypervisor is configured to send an instruction to the logging circuit and execute a first movement in which first data stored in the first logical storage area assigned to the logical partition is migrated to a second logical storage area assigned to another logical partition controlled by another hypervisor in another computer, wherein the logging circuit operates in parallel to the first movement to record an address and a size of second data in one of the plurality of entries per transmission of the second data, the address denoting storing positions of the second data in the first logical storage area, wherein during the first movement, the second data, which is transmitted from the I/O device to the first logical storage area after sending the instruction, replaces a part of the first data in the first logical storage area, and wherein the hypervisor is configured to: stop the logical CPU assigned to the logical partition during a second movement when a number of recorded entries, each including the address and the size, does not exceed a predetermined number, execute the second movement in which the second data, which is stored in the first logical storage area and is denoted by the address and the size recorded in at least one of the plurality of entries, is moved to the second logical storage area, the logging circuit continuing to record the address and size of the second data transmitted from the I/O device in one of the plurality of entries per transmission of the second data, and resend the instruction to the logging circuit and restart the logical CPU to retry the first movement when the number of recorded entries exceeds the predetermined number.