Patent ID: 7185301

Claim:
A method for implementing a source synchronous interface in a platform using generic source synchronous interfaces, comprising steps of: placing at least one IO buffer in a slice of a platform; diffusing at least one generic source synchronous interface bit slice in said slice of said platform, each of said at least one generic source synchronous interface bit slice including at least one balanced flip-flop, at least one balanced multiplexer, and being matched to one of said at least one IO buffer; diffusing a generic source synchronous interface clock management system for calibrating and controlling delays through clock trees, said generic source synchronous interface clock management system including at least one frame delay element in said slice of said platform; defining supplementary transistor fabric circuitry in said platform to complete said generic source synchronous interface clock management system; and configuring metal layers of said platform to provide interconnect for said at least one generic source synchronous interface bit slice, said at least one IO buffer, and said generic source synchronous interface clock management system to perform at least one of a receiving side (RX) and transmitting side (TX) implementation of a source synchronous interface in said platform.