Patent ID: 8860230

Claim:
A semiconductor comprising a substrate; a plurality of wiring layers and dielectric layers formed on the substrate, the dielectric layers separating adjacent ones of the plurality of wiring layers, and the wiring layers implementing a circuit; a first passivation layer formed on the plurality of wiring layers; a first contact pad formed in the passivation layer and electrically coupled to the circuit; a wire formed on the passivation layer and connected to the first contact pad; a through silicon via (TSV) formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer, the TSV electrically connected to the wire formed on the passivation layer, and the TSV being electrically isolated from the wiring layers except for the connection provided by the wire formed on the passivation layer and the first contact pad formed in the passivation layer; a second contact pad electrically coupled to the TSV from contacting the TSV at a bottom region of the substrate; and wherein the first contact pad and the second contact pad are electrically isolated from one another except for the connection provided by the metal wire and the TSV.