Patent ID: 8560810

Claim:
A microprocessor, comprising: a first instruction translator, configured to translate an instruction of an instruction set architecture of the microprocessor, wherein the instruction may specify a first form that instructs the microprocessor to write a result of the instruction to a destination register or a second form that instructs the microprocessor to write the result to memory, wherein the first instruction translator is further configured to generate, in response to encountering an instance of the instruction, an indication of whether the instance is of the first form or the second form; a microcode memory, configured to store a tail instruction as part of a microcode routine invoked by the first instruction translator in response to encountering the instance of the instruction; and a second instruction translator, configured to receive the tail instruction from the microcode memory and the indication, wherein if the indication specifies the first form the second instruction translator responsively translates the tail instruction into a first micro-operation that when executed by the microprocessor, causes the microprocessor to write the result to the destination register, wherein if the indication specifies the second form the second instruction translator responsively translates the tail instruction into a second micro-operation that when executed by the microprocessor, causes the microprocessor to complete a write of the result to memory.