Patent ID: 6919739

Claim:
A logic circuit comprising: a dynamic logic portion for evaluating a Boolean function of a plurality of data input signals, wherein a logic signal on a dynamic node asserted in response to a first logic state of a clock signal comprises either a logic true or a logic false Boolean combination of the plurality of the data input signals and the dynamic node is pre-charged to a first logic state corresponding to the logic false Boolean combination when the clock signal has a second logic state; a static portion having a pull-down input, a data input coupled to the dynamic node, a data output node generating a latched data output signal in response to the logic signal and the clock signal, and an inverted data output node generating a latched inverted data output signal as the logic inversion of the latched data output signal, wherein the inverted data output node is set to a logic zero when the pull-down input is a logic one and the inverted data output node is held at a logic zero when the data output signal is a logic one; and a feedforward pulse circuit having a first input coupled to the dynamic node, a second input coupled to the inverted data output node, and a pulse node coupled to the pull-down input and generating a feedforward pulse, wherein the feedforward pulse is a logic one when the dynamic node is a logic zero and the inverted data output signal is a logic one.