Patent ID: 7603641

Claim:
A method of creating a floor plan design for a circuit, comprising: a routing optimization computer receiving an initial floor plan design specifying a plurality of blocks and one or more PG wires routed among the blocks; receiving design constraints associated with the initial floor plan design; identifying problems in the PG wires; modifying the PG wires to correct the problems, and comply with the received design constraints; and producing a modified floor plan design specifying the modified PG wires, wherein the modifying the PG wires comprises: identifying a pin connected to one of the PG wires and having a worst IR-drop voltage value; determining a shortest path through the PG wires that connects the pin to a corresponding voltage source; and increasing a size of each PG wire in the shortest path until the IR-drop voltage value for the pin is less than or equal to a specified IR-drop threshold voltage value.