Patent ID: 7353316

Claim:
A memory system, comprising: a plurality of memory modules, each of the memory modules comprising: a substrate having a first connector and a second connector; a plurality of memory devices mounted on the substrate; and a memory hub mounted on the substrate and coupled to the plurality of memory devices, the memory hub comprising: a first plurality of bit-lane terminals; a second plurality of bit-lane terminals; at least one memory device interface; a switch coupled to the bit-lane terminals in the first and second plurality and to the at least one memory device interface, the switch including a switching circuit that is operable to couple at least some of the bit-lane terminals in the first plurality to either a respective one of the bit-lane terminals in the second plurality or at least one other bit-lane terminal in the second plurality, the switching circuit further being operable to couple at least some of the bit-lane terminals in the first plurality to the at least one memory device interface; a memory hub controller having a plurality of bit-lane terminals; and a plurality of bit-lanes connecting the bit-lane terminals of the memory hub controller to the bit-lanes in the first plurality of bit-lanes of the memory hub in one of the memory modules, the first plurality of bit-lane terminals of the memory hubs in the other memory modules being connected by respective bit-lanes to respective bit-lane terminals in the second plurality of bit-lanes terminals of the memory hub in another of the memory modules.