Patent ID: 7984363

Claim:
An integrated circuit device comprising: a plurality of memory circuits which store data; a plurality of code generating circuits which are provided for the memory circuits, respectively, to generate an error correction code to correct an error bit of each data stored in the memory circuits; at least one code storage memory which is shared by the memory circuits to store code data obtained by the error correction code; at least one decoding circuit which is provided for each of the memory circuits to detect the error bit based on the code data stored in the code storage memory; at least one memory hibernation state control circuit to bring each of the memory circuits into a hibernation state in response to an external command; a state controller which controls the memory hibernation state control circuit and indicates an interrupt in a memory circuit in a hibernation state; and a plurality of correction circuits which are provided for the memory circuits, respectively, to correct the error bit detected by the decoding circuit by the interrupt in the memory circuit in the hibernation state in accordance with an indication of the state controller.