Patent ID: 8420489

Claim:
A method of manufacturing a semiconductor device, the method comprising: a) providing a substrate; b) forming a source region, a drain region, a gate stack, sidewall spacers and an interlayer dielectric layer on the substrate, wherein the gate stack is disposed between the source region and the drain region on the substrate, the sidewall spacers are formed on the side surfaces of the gate stack, the interlayer dielectric layer covers the source region and the drain region, and the gate stack comprises a gate dielectric layer and a dummy gate; c) removing the dummy gate to expose the gate dielectric layer, so as to form an opening; d) performing reverse Halo implantation to the device to form a reverse Halo implantation region on the substrate via the opening, wherein for a n-type semiconductor device, the implantation dopants are n-type, and for a p-type semiconductor device, the implantation dopants are p-type ; e) activating the dopants in the reverse Halo implantation region by annealing; and f) performing subsequent device processing.