Patent ID: 7983637

Claim:
An amplifier comprising: an input terminal configured to have an input signal of a center frequency f 0 input thereto; a dividing unit that is connected to the input terminal and divides the input signal; first through ith (i being an even number of 2 or greater) blocks that are connected in parallel to the dividing unit, respectively, and have the divided input signal transmitted thereto; a combining unit that is connected to the first through ith blocks and combines signals transmitted through the first through ith blocks; and an output terminal that is connected to the combining unit and outputs the signals combined by the combining unit, the nth block (n being an integer between 1 and i) including a nth former-stage resonator having a fundamental resonant frequency f n , a nth amplifying unit configured to amplify a signal transmitted through the nth former-stage resonator, a nth latter-stage resonator having the fundamental resonant frequency f n , and a nth phase adjusting unit, the signal transmitted through the nth amplifying unit being transmitted through the nth latter-stage resonator, the fundamental resonant frequency f m (m being an integer between 1 and i−1) satisfying the relationship, f m ≦f (m+1) , the nth latter-stage resonator being one of a jth latter-stage resonator (j being i/2 integers selected from 1 to i) having a harmonic resonant frequency f aj lower than 2f 1 , and a kth latter-stage resonator (k being i/2 integers selected from 1 to i, except for j) having a harmonic resonant frequency f bk higher than 2f i , a kth latter-stage resonator having a harmonic resonant frequency f bk exists that satisfies the relationship of (f aj +f bk )/2=2f 0 for each jth latter-stage resonator, the mth phase adjusting unit (m being an integer between 1 and i−1) being configured to reverse a phase of a phase difference between a signal of the fundamental resonant frequency f m passing through the mth block and a signal of the fundamental resonant frequency f (m+1) passing through the (m+1)th block, the nth phase adjusting unit (n being an integer between 1 and i) being configured to maintain all phase differences among signals of 2f n passing through the nth block in the coordinate-phase.