Patent ID: 7486553

Claim:
A nonvolatile storage device comprising: a plurality of bit lines arranged in a column direction on a substrate; a plurality of word lines arranged in a row direction on the substrate; a memory cell array having a plurality of memory cells each of which is arranged at each of intersections of the bit line and the word line, where a store state of each of the memory cells changes according to an electric signal relatively applied to the word line and the bit line; a word line selection unit having a needle relatively movable with respect to the substrate which comes into contact with one word line of the plurality of word lines, setting the word line in contact with the needle to a selection state; and a sense amplifier detecting through the bit line the store state of the memory cell to be connected to the word line which is set to the selection state by the word line selection unit; wherein the memory cells constituted memory cell units arranged in an array, each of the memory cell units including: a plurality of memory cells comprising a plurality of field effect transistors to be coupled in series so that an adjacent source and drain are shared with each other; and selection transistors provided on both ends of a column of the memory cells coupled in series.