Patent ID: 8853002

Claim:
A method, comprising: receiving an integrated circuit die having a plurality of conductive terminals extending from a surface of the integrated circuit die, the plurality of conductive terminals disposed on bond pads and providing electrical connection to one or more devices within the integrated circuit die; forming solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface of the substrate for receiving the integrated circuit die and a protected region outside the die attach region, the substrate having a plurality of conductive traces formed in the die attach region and the conductive traces corresponding to the conductive terminals; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals relative to the protected region of the substrate to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die.