Patent ID: 7786780

Claim:
Apparatus for producing a clock signal, comprising: an input for receiving a clock signal indicating one of a number of logic states; a first device for producing a first signal from the clock signal, whereby the first signal has a duty cycle less than a duty cycle of the clock signal; a clock signal modifier for producing a modified clock signal from the clock signal; a second device for producing a second signal from the modified clock signal, whereby the second signal has a duty cycle less than the duty cycle of the clock signal; and a signal combiner for combining the first and second signals to produce a combined signal, whereby the combined signal has a frequency higher than a frequency of the clock signal, wherein at least one of the first and second devices comprises: a capacitor; a first current source for one of charging and discharging the capacitor over a first time period determined from the clock signal; a second current source for one of discharging and charging the capacitor over a first portion of a second time period determined from the clock signal; a detector for detecting when the voltage across the capacitor is substantially a first voltage and controlling the second current source for a second portion of the second time period to substantially maintain the voltage across the capacitor, wherein the detector comprises a comparator for comparing the voltage across the capacitor with a reference voltage; and a device output comprising an output from the comparator for at least one of the first signal and the second signal such that the at least one of the first signal and the second signal indicates when the voltage across the capacitor is one of above and below the first voltage.