Patent ID: 8263466

Claim:
A complementary process for forming field-effect transistors (FETs), comprising forming n-channel FETs having respective semiconductor channels in a tensile stress state and p-channel FETs having respective semiconductor channels in a compressive stress state, each of the respective n-channel transistors having a metal source/drain with a workfunction less than an affinity of a semiconductor that makes up the semiconductor channel of the respective n-channel transistor and each of the p-channel transistors having a respective metal source/drain with a workfunction greater than an ionization potential of a semiconductor that makes up the semiconductor channel of the respective p-channel transistor, wherein in each transistor instance, during the formation process, stress is induced in respective semiconductor channels of each respective n-channel or p-channel transistor by a strained capping metal which caps the metal source/drain of the respective n-channel or p-channel transistor and induces stress in each respective semiconductor channel.