Patent ID: 8014215

Claim:
A method, in a cache access memory, for gating a read access of any row in the cache access memory that has been invalidated, the method comprising: sending, by an address decoder in the cache access memory, a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access; determining, by the non-gated wordline driver, whether the memory access is a write access or a read access; responsive to the non-gated wordline driver determining the memory access as being the read access, outputting, by the non-gated wordline driver, the data stored in a valid bit memory cell to the gated wordline driver; determining, by the gated wordline driver, whether the memory access is the write access or the read access; responsive to the gated wordline driver determining the memory access as being the read access, determining, by the gated wordline driver, whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data; and responsive to the data being invalid, denying, by the gated wordline driver, an output of the data in a row of memory cells associated with the gated wordline driver.