Patent ID: 8924897

Claim:
A mask pattern design method, executed on an electronic processor, comprising the steps of: dividing, via the electronic processor, design layout data for patterns into a plurality of regions and extracting regions in which transfer dimensions obtained from a transfer simulation of pattern data exceed a predetermined allowance range; extracting, via the electronic processor, patterns that have the regions in which transfer dimensions obtained from the transfer simulation of said pattern data exceed the predetermined allowance range, and acquiring coordinates of the extracted patterns and difference amounts from the predetermined allowance range; performing, via the electronic processor, process window analysis based on simulation regions in which the coordinates of the extracted patterns are centered in the simulation regions, respectively, the process window analysis including a plurality of transfer conditions that are respectively applied, and computing transfer dimensions obtained from a transfer simulation with respect to each of the plurality of transfer conditions; extracting, via the electronic processor, process windows based on at least one transfer condition from the plurality of transfer conditions in which a transfer dimension obtained from the transfer simulation exceeds a predetermined allowance range; computing yield loss, via the electronic processor, from an occurrence probability regarding the transfer condition in relation to the extracted process windows of the extracted patterns; comparing, via the electronic processor, the yield loss to a target value; and determining, via the electronic processor, device alignment specifications based on said comparison, wherein, when the extracted patterns exceed a predetermined number of patterns and prior to performing the process window analysis, then the method includes selecting a predetermined number of extracted patterns with extracted regions having the greatest difference amounts from the predetermined allowance range as the extracted patterns in which the process window analysis is to be performed.