Patent ID: 7555576

Claim:
A digital signal processing system comprising a programmable processor and a peripheral device coupled to the programmable processor, wherein the processor is arranged to communicate with the peripheral device using a read operation and a write operation, respectively, on a single data element, comprising a burst generation device arranged to group a plurality of read operations or a plurality of write operations in a single burst read operation or a single burst write operation, respectively, the burst generation device comprising: a collector circuit arranged to receive the read and write operations from the programmable processor, and to generate dedicated tokens, based on information derived from the read and write operations, triggering a release of the single burst read operation or the single burst write operation, respectively; a first FIFO buffer for storing the dedicated tokens; a second FIFO buffer for storing information derived from the read and write operations, respectively; and a release circuit arranged to initiate the release of the single burst write operation or the single burst read operation, respectively, from the second FIFO buffer, under the control of a dedicated token received from the first FIFO buffer.