Patent ID: 7634695

Claim:
A test apparatus for testing a memory under test, the memory under test including therein (i) a plurality of blocks each of which has a plurality of columns and (ii) one or more repairing columns each of which is provided so as to collectively replace columns each of which is included in one of the plurality of blocks and associated with the same column position, the test apparatus comprising: a testing section that tests each of the plurality of blocks provided in the memory under test, and outputs information indicating whether a test target block is defective in units of the columns; a flag memory that stores thereon, in association with each of the plurality of columns in the test target block, a flag that indicates whether a corresponding one of the plurality of columns in the test target block is defective; a counter memory that stores thereon, in association with each of the plurality of columns, the number of defective blocks which is the number of blocks that have defects at a column position associated with a corresponding one of the plurality of columns; a failure writing section that receives, from the testing section, a test result of a test target column in the test target block, and writes a flag indicating that the test target column is defective into the flag memory under a condition that at least one of the following conditions is satisfied: when the received test result indicates that the test target column is defective; and when a flag that is stored on the flag memory in association with the test target column indicates that the test target column is defective; a counting section that receives, from the testing section, the test result of the test target column, and increments the number of defective blocks which is stored on the counter memory in association with the test target column under a condition that the received test result indicates that the test target column is defective and the flag indicating that the test target column is defective is not stored on the flag memory in association with the test target column; and a selecting section that selects columns to be replaced with the repairing columns based on the number of defective blocks which is stored on the counter memory in association with each of the plurality of columns.