Patent ID: 8108060

Claim:
A method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”), the method comprising: performing a key process on a sample number of wafers of a lot of wafers, the key process represented by a first function f(x); performing a key inline measurement related to the key process to produce metrology data for the wafers, wherein the key inline measurement comprises a wafer measurement performed during wafer processing; predicting WAT data from the metrology data using an inline-to-WAT model, wherein the inline-to-WAT model is designed to represent a relationship between the metrology data and the predicted WAT data; determining a final WAT represented by a second function g(y); and using the predicted WAT data to tune a WAT APC process for controlling a tuning process according to a first model defined as (g(f(x))) −1 and a process APC process according to a second model defined as (f(x)+g(y)) −1 .