Patent ID: 7888228

Claim:
A method of manufacturing an integrated circuit comprising a memory device, the method comprising: forming a solid electrolyte layer comprising a first solid electrolyte layer area having a substantially first thickness and a second solid electrolyte layer area having a substantially second thickness, the second thickness being lower than the first thickness, wherein the solid electrolyte layer comprises a solid electrolyte layer composite structure comprising a first solid electrolyte layer, a second solid electrolyte layer disposed above the first solid electrolyte layer, and an intermediate layer sandwiched between the first solid electrolyte layer and the second solid electrolyte layer; forming a conductive layer on or above top surfaces of the first solid electrolyte layer area and the second solid electrolyte layer area; planarizing a top surface of the conductive layer such that the solid electrolyte layer is exposed within the first solid electrolyte layer area but is covered by the conductive layer within the second solid electrolyte layer area; and patterning the exposed solid electrolyte layer within the first solid electrolyte layer area.