Patent ID: 8630336

Claim:
An integrated circuit comprising: a two phase partial response equalizer circuit; the two phase partial response equalizer circuit having a first sampler circuit to sample an input signal to generate a first sampled signal in response to a first sampling clock having a first phase, and a second sampler circuit to sample the input signal to generate a second sampled signal in response to a second sampling clock having a second phase; the two phase partial response equalizer circuit having a first feedback path to control partial response selection by the first sampler circuit in dependence on the second sampled signal and a second feedback path to control partial response selection by the second sampler circuit in dependence on the first sampled signal; a latch in the first feedback path, the second feedback path not having a latch; and circuitry to generate a latch clock for the latch in the first feedback path to be phase offset from each of the first sampling clock and the second sampling clock.