Patent ID: 8020068

Claim:
In a memory system comprising a memory controller and a memory, a method comprising: communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory; decoding the command and executing an EDC operation related to the EDC data in parallel, wherein decoding the command comprises receiving a command packet in a packet receiver and in response generating an internal command, internal EDC data, and an internal address; and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation, wherein executing the EDC operation comprises: applying the internal EDC data, the internal command, and the internal address to an error detector; generating an error signal in the error detector in relation to the internal command, internal address, and the internal EDC data; and applying the error signal to a write enable signal transfer block.