Patent ID: 7514325

Claim:
A method of fabricating a fin-field effect transistor (Fin-FET) having a gate all around (GAA) structure, the method comprising: selectively etching a semiconductor substrate to form a pair of support pillars protruding from a body of the semiconductor substrate and a fin protruding from the body, wherein ends of the fin are connected to and supported by the pair of support pillars; forming a device insulation layer on the body to expose top portions of the pair of support pillars and the fin; forming a spacer insulation layer on side walls of the exposed top portions of the pair of support pillars and the fin; etching the device insulation layer to a desired thickness using the spacer insulation layer as an etching mask to expose intermediate portions of the pair of support pillars and the fin; forming a tunnel through the fin by removing the exposed intermediate portion of the fin; forming a gate insulation layer on a surface of an upper portion of the fin spaced apart from the body by the tunnel; and forming a gate electrode on the device insulation layer, the gate electrode surrounding a part of the upper portion of the fin.