Patent ID: 8917549

Claim:
A NOR flash memory array structure, comprising: a substrate; and a two dimensional memory array structure formed on the substrate and comprising: a plurality of memory cell columns arranged in parallel in a first direction, two adjacent memory cell columns isolated from each other and each memory cell column including a plurality of memory cells, wherein each memory cell comprises: a channel region located on the substrate, a gate structure located on the channel region and formed by a tunneling oxide layer, a silicon nitride layer, a barrier oxide layer and a polysilicon gate layer stacked sequentially, a source region located in the substrate and at a first edge of the gate structure, and a drain region located in the substrate and at a second edge of the gate structure; a plurality of word lines arranged in parallel in a second direction and each configured to connect the gate structures of the memory cells in a same row; a source line for connecting the source regions of all the memory cells; and a plurality of bit lines arranged in parallel in the first direction and each configured to connect the drain regions of the memory cells in a same column, the plurality of bit lines crossing the plurality of word lines and the source line, wherein the substrate is a p-type semiconductor substrate, and each memory cell comprises: a p-well formed in the p-type semiconductor substrate, and the channel region formed on the p-well and non-uniformly doped in a horizontal direction with p+/n−/p+, p+/p−/p+, or p+/depletion region/p+.