Patent ID: 7098710

Claim:
A delay locked loop comprising: a primary delay line comprising a plurality of series-connected delay elements, wherein each of the delay elements has an adjustable delay; a delay control circuit coupled to the primary delay line; at least one configuration memory cell coupled to the delay control circuit; wherein the delay control circuit adjusts delay of the delay elements of the primary delay line in response to the at least one configuration memory cell; a voltage distribution line, wherein each of the delay elements operates in response to a voltage on the voltage distribution line; a first voltage terminal for receiving a first voltage; a second voltage terminal for receiving a second voltage, wherein the first voltage is greater than the second voltage; wherein the delay control circuit selectively couples the first voltage terminal or the second voltage terminal to the voltage distribution line responsive to the at least one configuration memory cell; a clock input terminal for receiving an input clock signal, wherein the clock input terminal is coupled to an input terminal of the primary delay line; a first multiplexer coupled to receive delayed versions of the input clock signal from the delay elements of the primary delay line; and a delay selection circuit coupled to control the first multiplexer in response to the input clock signal and a distributed version of the input clock signal; wherein the first voltage terminal is coupled to the voltage distribution line for operating the delay locked loop in a high frequency mode when the at least one configuration memory cell stores a first data value; and wherein the second voltage terminal is coupled to the voltage distribution line for operating the delay locked loop in a low frequency mode when the at least one configuration memory cell stores a second data value.