Patent ID: 8885383

Claim:
A flash memory, comprising: a core array storing data; a peripheral circuit accessing the data stored in the core array to generate read data; an off-chip driver (OCD) processing the read data to generate output data; an interconnect structure electrically connected to the core array, the peripheral circuit and the OCD, and comprising a first conductive layer, a second conductive layer and a third conductive layer, wherein the first, second and third conductive layers are electrically connected to one another; and an uppermost conductive layer formed over the interconnect structure, electrically connected to the interconnect structure, and comprising: a first power pad electrically connected to a power pin via a first bonding wire to receive an operation voltage; and a plurality of first power tracks electrically connected between the first power pad and the interconnect structure to transmit the operation voltage to at least one of the core array, the peripheral circuit and the OCD.