Patent ID: 7076699

Claim:
A method for testing semiconductor devices, comprising steps of: generating memory repair data for a wafer die by writing at least one predetermined digital bit pattern into a memory on the wafer die, reading the at least one predetermined digital bit pattern back out of the memory, comparing the at least one predetermined digital bit pattern read out from the memory against the at least one predetermined digital bit pattern written into the memory, and storing results of the comparison as the memory repair data, wherein the writing and reading are performed a plurality of times, each time with a different voltage and clock frequency combination being applied to the wafer die; permanently programming the memory repair data into the wafer die; assembling the wafer die into a packaged semiconductor device; and testing the packaged semiconductor device by causing the memory repair data programmed within the packaged semiconductor device to be transferred into the memory a plurality of times, each time with a different voltage and clock frequency combination being applied to the packaged semiconductor device.