Patent ID: 7541668

Claim:
A packaged semiconductor comprising: a plurality of first conductive leads, each including first and second pillar-shaped portions and a top plate covering the tops of the first and second pillar-shaped portions, which are spaced apart from one another and arranged such that the second pillar-shaped portions face inward, wherein the lateral length of the top plate is greater than the corresponding lateral length of one of the first and second pillar shaped portions; a semiconductor chip having a top surface on which a plurality of bonding pads are disposed and edge portions attached onto edges of top plates of the first conductive leads; a plurality of first conductive wires connecting at least some of the bonding pads on the semiconductor chip with corresponding ones of the first conductive leads; a molding material encapsulating the semiconductor chip and the first conductive wires and parts of the first conductive leads so as to expose at least bottom surfaces of the first and second pillar-shaped portions of the first conductive leads the packaged semiconductor further comprising: a plurality of second conductive leads, each including respective first, second, and third pillar-shaped portions and a top plate covering the first, second, and third pillar-shaped portions, which are spaced apart from and arranged alternately with the first conductive; and a plurality of second conductive wires connecting at least some of the bonding pads on the semiconductor chip with corresponding ones of the second conductive leads; wherein the molding material further encapsulates portions of the second conductive leads so as to expose the bottom surfaces of plurality of second conductive leads, wherein the edge portions of the semiconductor chip are attached onto edge portions of the top plates of the second conductive leads.