Patent ID: 7148543

Claim:
A semiconductor chip, comprising: a base substrate; a bulk device region having a bulk growth layer on a part of the base substrate, the bulk device region having a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer; a pn junction formed in the bulk device region and positioned above an interface between the base substrate and the bulk growth layer; an SOI device region having a buried insulator on the other part of the base substrate and an SOI layer on the buried insulator, the SOI device region having a second device-fabrication surface in which an SOI device is positioned on the SOI layer, the first and second device-fabrication surface being positioned at a substantially uniform level; a first isolation formed in the bulk device region so as to separate the bulk device, and a second isolation in the SOI device region so as to separate the SOI device, the first and second isolations being substantially the same depth and having a depth reaching the buried insulator; a boundary layer located at a boundary between the bulk device region and the SOI device region; and a dummy trench in the bulk device region between the bulk device and the SOI device.