Patent ID: 8296746

Claim:
An optimum code generation method in which, for a computer configured of plural processors which share a main memory or a cache memory, for a purpose of increasing execution efficiency of the plural processors while reducing data transfer amount from the main memory to the plural processors, optimum parallel codes processed by the plural processors are generated from a source code, wherein the computer system performs: a first step of analyzing process contents of the source code, and analyzing an operation amount and an operation sequence dependence relation of the plural processors, reusability of data of the cache memory, and a load data amount and a store data amount between the main memory or the cache memory and the plural processors; a second step of retaining the number of plural processors, access time of the main memory or access time of the cache memory, the number of registers, a capacity of the cache memory, a synchronization acquisition method among the plural processors and time required for synchronization, inputted by a user as performances of the computer; a third step of calculating the reusability of data in the cache memory based on a comparison between a data access interval from a point of first use to a point of reuse and a capacity of the cache memory; and a fourth step of dividing the process contents of the source code for the plural processors, and while estimating execution cycle time in the case where the divided source codes are executed by the plural processors on the basis of the first step and the second step, generating parallel codes with which the execution cycle time becomes shortest based on the calculated reusability of data in the cache memory.