Patent ID: 8441266

Claim:
A sensing circuit comprising: first and second PMOS transistors, each having a source, a drain and a gate, first and second NMOS transistors, each having a source, a drain and a gate, the first PMOS transistor and the first NMOS transistor being connected in series between a first input and a first node with the gates of the first PMOS transistor and the first NMOS transistor connected together, the second PMOS transistor and the second NMOS transistor being connected in series between a second input and the first node with the gates of the second PMOS transistor and the second NMOS transistor being connected together, a first output connected to a second node between the first PMOS transistor and the first NMOS transistor and to the gates of the second PMOS transistor and the second NMOS transistor, a second output connected to a third node between the second PMOS transistor and the second NMOS transistor and to the gates of the first PMOS transistor and the first NMOS transistor, a fuse connected between a power supply and the first input; a reference resistance connected between the power supply and the second input, whereby voltages on the first and second outputs indicate whether the resistance of the fuse is greater than or lesser than the reference resistance; and a control circuit comprising third and fourth NMOS transistors, each having a source, a drain and a gate, the source and drain of the third NMOS transistor connected between the fuse and the first input and the source and drain of the fourth NMOS transistor connected between the reference resistance and the second input.