Patent ID: 8209497

Claim:
A multi-port memory, comprising: a memory array made of a plurality of memory cells arranged at intersection points between a plurality of bit lines and a plurality of word lines, the memory array being divided into n (an integer of 2 or greater) memory banks; m (an integer of 2 or greater) input/output ports, each independently performing inputs and outputs of a command, an address, and data to and from each of the memory banks; and a route switching circuit that sets signals for the command, address, and data between the memory banks and the input/output ports, the route switching circuit controlling a connection state of signal lines between the plurality of input/output ports and the plurality of memory banks, wherein the route switching circuit further comprises a broadcast switch portion, the broadcast switch portion comprising: a broadcast data line; first switches each provided for each of the memory banks for connecting the broadcast data line with an input and output line of each of the memory banks; and second switches each provided for each of the input/output ports for connecting the broadcast data line with an input and output circuit of each of the input/output ports, wherein, on receiving a command denoting a control of setting a route for a broadcast data transfer, which is a transfer of the same data from any of the input/output ports to p (an integer of 2≦p≦n) of the memory banks, the first switches corresponding to the plurality of memory banks are put in an ON state, one of the second switches corresponding to the input/output port selected for performing data input is put in an ON state, and the other of the second switches are put in an OFF state.