Patent ID: 8283701

Claim:
An integrated circuit device, comprising: a plurality of dynamic array sections each formed within a respective outer peripheral boundary defined by four or more outer peripheral boundary segments, wherein each of the plurality of dynamic array sections includes a respective gate electrode level that forms a portion of an overall gate electrode level of the integrated circuit device, wherein each of the plurality of dynamic array sections includes three or more linear conductive segments formed within its gate electrode level, wherein the three or more linear conductive segments are formed in a parallel manner to extend lengthwise in a first direction, wherein at least one of the three or more linear conductive segments formed within the gate electrode level of a given dynamic array section is a non-gate linear conductive segment that does not form a gate electrode of a transistor, wherein the plurality of dynamic array sections includes a first adjoining pair of dynamic array sections positioned to have co-located portions of outer peripheral boundary segments extending in the first direction, wherein each of the first adjoining pair of dynamic array sections is defined such that a respective gate electrode level manufacturing assurance halo portion extends in a second direction perpendicular to the first direction and away from its co-located portion of outer peripheral boundary segment toward the other of the first adjoining pair of dynamic array sections, and wherein the non-gate linear conductive segment within the gate electrode level of either of the first adjoining pair of dynamic array sections spans the co-located portion of outer peripheral boundary segment toward the other of the first adjoining pair of dynamic array sections and is contained within the gate electrode level manufacturing assurance halo portions of the first adjoining pair of dynamic array sections.