Patent ID: 8819610

Claim:
An integrated circuit layout, comprising: a P-type active region and an N-type active region; a plurality of trunks, each trunk of the plurality of trunks is formed substantially side-by-side and is substantially in parallel with each other; a first metal connection; and a second metal connection, wherein the first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region; the second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region; an axis of the first metal connection is substantially in parallel with an axis of the second metal connection; each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection; each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection; and a first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.