Patent ID: 7102935

Claim:
A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged corresponding to said rows, and a plurality of bit line pairs arranged corresponding to said columns; a plurality of column selection lines provided corresponding to said columns; an address buffer receiving an address signal indicating selection from said rows and columns; a row decoder controlling a voltage of said plurality of word lines in accordance with said address signal received by said address buffer; a column decoder controlling a voltage of said plurality of column selection lines in accordance with said address signal received by said address buffer; a plurality of sense amplifiers provided corresponding to said plurality of bit line pairs and each amplifying a voltage difference on corresponding one of said bit line pairs; a data line pair provided in common to said plurality of bit lines; a plurality of column selection gates provided corresponding to said columns and each connecting corresponding one of said bit line pairs to said data line pair in accordance with a voltage of corresponding one of said column selection lines; a first power supply system supplying an operating power supply voltage for said column decoder; a second power supply system supplying an operating power supply voltage for said memory cell array and said plurality of sense amplifiers; and a third power supply system supplying an operating power supply voltage for a peripheral circuit including said address buffer, wherein said column decoder includes a plurality of column selection line drivers provided corresponding to said plurality of column selection lines, each of said plurality of column selection line drivers has a switching element connected between a first power supply node receiving a first voltage from said first power supply system and a first internal node, and turned on during operation of said column decoder and turned off during stand-by in response to a control signal, a first connection control portion provided between said first internal node and a second internal node and connecting said second internal node to said first internal node in accordance with a result of selection of corresponding column of said columns, and a second connection control portion provided between a second power supply node supplying a second voltage different from said first voltage and said second internal node, said second connection control portion operates, in a manner complementary to said first connection control portion, so as to connect said second internal node to said second power supply node in accordance with the result of selection of said corresponding column, and each of said plurality of column selection line drivers further includes a drive portion driving corresponding one of said column selection lines to one of said first and second voltages in accordance with a voltage of said second internal node.