Patent ID: 7804118

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; a first MISFET arranged at an analog circuit forming region of the main surface, wherein the first MISFET includes a source region and a drain region each formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode; a second MISFET arranged at a logic circuit forming region of the main surface, wherein the second MISFET includes a source region and a drain region each formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode; a first capacitor element having a lower electrode, a first insulating film formed on the lower electrode, and a higher electrode formed on the first insulating film, such that the higher electrode is formed over the semiconductor substrate; a second insulating film formed over the first MISFET, the second MISFET and the first capacitor element; and a second capacitor element arranged at the analog circuit forming region and formed over the second insulating film, wherein the second capacitor element has a lower electrode formed over the second insulating film, a third insulating film formed on the lower electrode, and a higher electrode formed on the third insulating film.