Patent ID: 8498144

Claim:
A semiconductor storage device, comprising: a first memory cell configured to a first selection transistor and a first resistance change element of which a resistance value changes according to a flowing current; a second memory cell configured to a second selection transistor and a second resistance change element of which a resistance value changes according to a flowing current; a first bit line connected to a first end of the first memory cell; a second bit line connected to a second end of the first memory cell and a second end of the second memory cell; a third bit line connected to a first end of the second memory cell; a word line electrically connected to a control terminal of the first and second selection transistor; a row decoder electrically connected to a word line and which controls a voltage of the word line; a write circuit electrically connected to the first bit line, the second bit line, and the third bit line, and which controls a voltage of the bit lines respectively; a plurality of switch circuits electrically connected between the write circuit and the memory cells; wherein, when a write operation is executed, the row decoder controls the voltage applied to the word line to turn on the first selection transistors after the first memory cell connects the write circuit and the second memory cell disconnects the write circuit on the basis of the switch circuits.