Patent ID: 7620133

Claim:
A method for generating an output signal in a digital-to-phase converter (DPC), the DPC including a frequency source for generating a clock signal and a delay line configured to receive the clock signal and to generate a plurality of phase-shifted clock signals at a plurality of corresponding output taps on the delay line, the method comprising the steps of: receiving a control signal that identifies a first output tap on the delay line; based on the control signal, selecting at least two output taps on the delay line for receiving at least two different phase-shifted clock signals, wherein the at least two selected output taps comprise the first output tap and a second output tap that is offset from the first output tap by a predetermined number of output taps, and wherein a first phase-shifted clock signal is received from the first output tap and a second phase-shifted clock signal is received from the second output tap; and generating an output signal using the control signal and the at least two received phase-shifted clock signals that is substantially a desired output signal, wherein generating the output signal further comprises: generating a windowing signal based on the control signal and the second phase-shifted clock signal; and combining the windowing signal with the first phase-shifted clock signal to generate the output signal.