Patent ID: 7989142

Claim:
A method for fabricating a thin film transistor (TFT) array substrate, the method comprising: providing an insulating substrate; coating a gate metal layer on the substrate; forming a plurality of gate electrodes using a first photo-mask process; forming a gate insulating layer, a semiconducting layer, and a source/drain metal layer on the substrate having the gate electrodes; forming a plurality of source electrodes and a plurality of drain electrodes using a second photo-mask process, each of pairs of one source electrode and one drain electrode defining a channel therebetween; forming a passivation layer and a photo-resist layer on the gate insulating layer, the source electrodes and the drain electrodes; exposing the photo-resist layer using a third photo-mask process, thereby forming a photo-resist pattern, the photo-resist pattern exposing portions of the passivation layer, wherein each exposed portion of the passivation layer is above both a respective drain electrode and a portion of the gate insulating layer adjacent to the drain electrode; etching away the exposed portions of the passivation layer, thereby forming a patterned passivation layer, the patterned passivation layer being on the semiconducting layer, the gate insulating layer and the source electrodes and leaving the drain electrodes and the portions of the gate insulating layer exposed; forming a transparent conductive metal layer on the photo-resist pattern, the drain electrodes and the gate insulating layer; and forming a plurality of pixel electrodes through removing the photo-resist pattern and the transparent conductive metal layer on the photo-resist pattern.