Patent ID: 7668023

Claim:
A program operation method of a memory device including a plurality of MLCs respectively connected to a plurality of bit line pairs and a plurality of word lines, the method comprising: decoding an address signal in response to a program instruction to select the word line and bit line according to the decoding result and provide a control signal to page buffers connected to the selected bit line; inputting a lower program data to a LSB latch unit through a MSB latch unit of a page buffer in response to the control signal; programming a lower program data into a MLC connected to the selected word line and bit line; inputting an upper program data to the MSB latch unit of the page buffer; performing a first verification step of transferring the upper program data input to the MSB latch unit to a lower program latch unit and allowing the MSB latch unit to read and verify data of the selected MLC; performing a second verification step of transferring an upper program data to the MSB latch unit after the first verification to allow the LSB latch unit to read and verify data of the selected MLC, the upper program data being data stored in the LSB latch unit; and programming the upper program data stored in the MSB latch unit into the selected MLC according to the first and second verification results.