Patent ID: 7385860

Claim:
A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function, each pipelatch comprising: a data switching section for receiving N bits data and switching an output path of the N bits data depending upon a starting column address applied by a read command and a data output mode; a first data selection section for receiving one half of the N bits data outputted from the data switching section and sequentially outputting the one half of the N bits data in response to a first control signal; a second data selection section for receiving the other half of the N bits data outputted from the data switching section which remains by excluding the one half applied to the first data selection section and sequentially outputting the other half of the N bits data in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.