Patent ID: 8255672

Claim:
A processor comprising: a plurality of registers; an instruction readout circuit configured to read out an instruction from a memory; an instruction decode circuit configured to decode the instruction read out from the memory by the instruction readout circuit; an instruction generation circuit configured to generate instructions, each for saving data of a respective one of the plurality of registers into a predetermined storage area, if the instruction read out from the memory by the instruction readout circuit and decoded by the instruction decode circuit is an instruction causing the data stored in each of the plurality of registers to be saved; an address calculation circuit; and a data memory interface; the instruction decode circuit being further configured to decode the instructions generated by the instruction generation circuit; the address calculation circuit being configured to calculate an address within the predetermined storage area based on a decode result of the instruction decode circuit; the data memory interface being configured to access the predetermined storage area based on the address calculated by the address calculation circuit.