Patent ID: 7558114

Claim:
A flash memory device comprising: a memory cell array having a first region and a second region, each including memory cells arranged in a plurality of rows and columns and storing an identical number of bits per memory cell; an address storage circuit adapted to store address information defining the second region; a row decoder circuit adapted to select one of the first and second regions in response to an external address; a voltage generator circuit generating a read voltage provided to a row of the first or second region selected by the row decoder circuit during a read operation; a detector circuit adapted to detect whether the selected region is included in the second region based on the address information stored in the address storage circuit and on external address information; and a control logic adapted to control the voltage generator circuit in response to an output of the detector circuit during the read operation, wherein the control logic controls the voltage generator circuit so that a read voltage provided to a row of the second region is lower than a read voltage provided to a row of the first region.