Patent ID: 8242008

Claim:
A method of forming integrated circuitry, comprising: forming a tunnel dielectric material across a memory array region of a semiconductor wafer, and across a peripheral region that is adjacent to the memory array region; the tunnel dielectric material being over a first material across the peripheral region and being directly against semiconductor material of the wafer across the memory array region; forming metallic nanoparticles across the memory array and peripheral regions; the metallic nanoparticles being directly against the tunnel dielectric material across the memory array region and across the peripheral region; the metallic nanoparticles across the peripheral region being excess metallic nanoparticles; forming a stack over the metallic nanoparticles, the stack including two or more different materials, and being across the memory array and peripheral regions; covering a portion of the stack across the memory array region with a protective mask while leaving a portion of the stack across the peripheral region unprotected; removing the unprotected portion of the stack to expose the excess metallic nanoparticles; some of the excess metallic nanoparticles spreading across the protective mask over the memory array region while others of the excess metallic nanoparticles remain over the peripheral region; exposing the semiconductor wafer to a composition suitable to weaken adhesion between the excess nanoparticles and both the protective mask and the tunnel dielectric material; and while exposing the semiconductor wafer to said composition, spinning the semiconductor wafer to apply forces to the excess metallic nanoparticles and thereby sweep at least some of the excess metallic nanoparticles off from the semiconductor wafer.