Patent ID: 8027203

Claim:
A pipe latch circuit of semiconductor memory device, comprising: a first latch circuit for latching pre-fetched plural bits of input data from global input/output lines; a first multiplexing circuit comprising a first multiplexer for receiving only even-ordered bits of the pre-fetched plural bits outputted from the first latch circuit and selecting one of the even-ordered bits in response to a first selection control signal, and a second multiplexer for receiving only odd-ordered bits of the pre-fetched plural bits outputted from the first latch circuit and selecting one of the odd-ordered bits in response to a second selection control signal; a second multiplexing circuit for setting a sequence of output data from the first multiplexing circuit in response to a third selection control signal; and a second latch circuit comprising a third latch for latching a first output data from the second multiplexing circuit in response to a first output latch control signal and a fourth latch for latching a second output data from the second multiplexing circuit in response to a second output latch control signal.