Patent ID: 7551513

Claim:
A semiconductor memory device having a structure that sub memory cell arrays share a sense amplifier, the sub memory cell array having a plurality of unit memory cells arrayed in a matrix type, the device comprising: a bit line isolation part, which is controlled by an isolation signal and is disposed adjacent to the sense amplifier, to isolate the sense amplifier from one of sub memory cell arrays sharing the sense amplifier; multiple sub word line drivers, which are allocated and respectively correspond to the sub memory cell arrays that share the sense amplifier; and a sub word line driver control signal generator for receiving a sub word line decoding signal to select a corresponding sub word line of a selected sub memory cell array, and the isolation signal, and so activating one of the sub word line drivers corresponding to a sub memory cell array coupled with the sense amplifier, and for deactivating the rest of the sub word line drivers, wherein the sub word line driver control signal generator is formed at a conjunction region adjacent to a region where the sense amplifier is formed, comprises a boosted voltage supply part for outputting a boosted voltage having a level higher than a power source voltage when the sub word line decoding signal has a high level, and further comprises a first sub word line drive control signal output part, in which: a second isolation signal among the isolation signals is applied to a gate terminal of a first P-type metal oxide semiconductor (MOS) transistor, the second isolation signal being for isolating between a sub memory cell array sharing the sense amplifier and the sense amplifier, an output voltage of the boosted voltage supply part is applied to a source terminal of the first P-type MOS transistor, a drain terminal of the first P-type MOS transistor is connected to a drain terminal of a first N-type MOS transistor, an inversion signal of the sub word line decoding signal is applied to a gate terminal of the first N-type MOS transistor, a ground voltage is applied to a source terminal of the first N-type MOS transistor, and a voltage of a first node between the drain terminal of the first P-type MOS transistor and the drain terminal of the first N-type MOS transistor is outputted.