Patent ID: 8077494

Claim:
An apparatus, comprising: a memory cell array including a plurality of subarrays; a word line arranged in the memory cell array; a main bit line arranged to intersect with the word line; sub bit lines respectively arranged in each of the subarrays and configured to be coupled to the main bit line; a first transistor arranged between sub bit lines of nonselected subarrays to couple the sub bit lines of the nonselected subarrays to each other, wherein the first transistor has a first source/drain terminal directly connected to a first sub bit line of a first of the nonselected subarrays and has a second source/drain terminal directly connected to a second sub bit line of a second of the nonselected subarrays; and a second transistor configured to couple the sub bit line of one of the nonselected subarrays to a first fixed potential.