Patent ID: 8039340

Claim:
A method of forming a plurality of field effect transistors, comprising: forming a plurality of spaced lines over semiconductive material of a semiconductor substrate; forming pairs of first and second anisotropically etched sidewall spacers on opposing sides of the spaced lines, individual of the lines having greater maximum width than minimum width of space between immediately adjacent of the first and second spacers between immediately adjacent of the lines; removing the spaced lines from between the first and second spacers to form a mask comprising alternating first and second mask openings, the first mask openings being located where the spaced lines were located and being wider than the second mask openings, the respective first openings having laterally innermost edges defined by laterally innermost edges of the first and second spacers, the respective second openings having laterally innermost edges defined by laterally outermost edges of the first and second spacers; using the mask, etching both inter-transistor trenches and intra-transistor trenches simultaneously into the semiconductive material, the inter-transistor trenches being formed through the first mask openings, the intra-transistor trenches being formed through the second mask openings, the inter-transistor trenches being etched wider and deeper within the semiconductive material than are the intra-transistor trenches; providing a pair of source/drain regions within the semiconductive material on opposing sides of individual of the intra-transistor trenches between immediately adjacent of the inter-transistor trenches; providing a channel region within the semiconductive material elevationally inward of the pair of source/drain regions between immediately adjacent of the inter-transistor trenches; and providing a gate operably proximate the channel region.