Patent ID: 7957195

Claim:
A semiconductor device comprising: a nonvolatile memory including: a plurality of 1-bit twin cells, each having electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to a difference of their threshold voltages, a plurality of word lines coupled to the plurality of 1-bit twin cells so that one word line is coupled to select terminals of the first and second storage devices constituting one of the plurality of 1-bit twin cells, a plurality of bit lines coupled to the plurality of 1-bit twin cells so that a first pair of bit lines is coupled to the first and second storage devices of a first 1-bit twin cell of the plurality of 1-bit twin cells and another bit line coupled to the first or second storage devices of a second 1-bit twin cell is arranged between the first pair of bit lines coupled to the first and second storage devices of the first 1-bit twin cell of the plurality of 1-bit twin cells, and a first read circuit including a first sense amplifier coupled to the first pair of bit lines coupled to the first and second storage devices of the first 1-bit twin cell of the plurality of 1-bit twin cells and for differentially amplifying complementary data output from the first and second storage devices of one of the plurality of 1-bit twin cells selected for read.