Patent ID: 7737495

Claim:
A semiconductor device comprising: a semiconductor substrate containing silicon; an N channel MIS transistor and a P channel MIS transistor therein; a first inter-layer film having a tensile stress on said N channel MIS transistor; a second inter-layer film, having a non-zero compressive stress, directly on said first inter-layer film and said P channel MIS transistor; a layer insulation film on said first inter-layer film having tensile stress and said second inter-layer film having a non-zero compressive stress; and a contact hole formed in said layer insulation film, wherein, said compressive stress in said second inter-layer film is relaxed on the upper side of said first inter-layer film, said first inter-layer film has a thickness of 50 to 100 nm, said second inter-layer film has a thickness of 50 to 100 nm, said compressive stress in said second inter-layer film is relaxed on the upper side of said first inter-layer film by a dose of silicon ion implantation effective to convert the silicon in said semiconductor substrate into its amorphous state.