Patent ID: 7364977

Claim:
A method of fabricating a heterojunction bipolar transistor, comprising: sequentially forming a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a substrate; forming an emitter electrode on a first region of the emitter cap layer; selectively etching the emitter cap layer and the emitter layer, to expose a portion of the base layer; forming a base electrode on a second region of the exposed portion of the base layer; selectively etching the base layer and the collector layer, to expose a portion of the sub-collector layer; forming a collector electrode on a third region of the exposed portion of the sub-collector layer; forming a first dielectric layer on the overall surface of the substrate; selectively etching the first dielectric layer and the sub-collector layer, to define an isolation region; forming a second dielectric layer on the overall surface of the substrate; selectively etching the second dielectric layer, to form via holes on the emitter, base, and collector electrodes, respectively; and forming a gap under the second dielectric layer by removing at least a portion of the first dielectric layer through the via holes.