Patent ID: 7968412

Claim:
A process for manufacturing a vertical MISFET device comprising: in a semiconductor wafer, forming a semiconductor layer having a first type of conductivity and a first level of doping; in the semiconductor layer, making at least a first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity; forming an enriched region in the semiconductor layer between the first body region and the second body region, the enriched region having the first type of conductivity and a second level of doping, higher than the first level of doping; forming a gate electrode extending over the enriched region, over part of the first body region and over part of the second body region; and forming a dielectric gate structure between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first body region and the second body region; wherein forming the enriched region comprises: forming a first conductive layer on the semiconductor layer; forming an enrichment opening in the first conductive layer; and introducing a dopant species into the semiconductor layer through the enrichment opening; and in that forming a dielectric gate structure comprises filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.