Patent ID: 8889510

Claim:
A method of forming a surrounding stacked gate fin FET nonvolatile memory structure, the method comprising: providing a silicon-on-insulator substrate of a first conductivity type; patterning a fin active region on a predetermined region of the silicon-on-insulator substrate, the fin active region projecting from a surface of the substrate; forming a tunnel oxide layer on the fin active region; depositing a first gate electrode on the tunnel oxide layer and upper surface of the substrate; forming a dielectric composite layer on the first gate electrode; depositing a second gate electrode on the dielectric composite layer; patterning the first and second gate electrodes so as to define a surrounding stacked gate area; forming a spacer layer on a sidewall of the stacked gate electrodes; forming elevated source/drain regions in the fin active region on both sides of the second gate electrode; and planarizing the elevated source/drain regions so that a top surface of the planarized source/drain regions is substantially coplanar with a top surface of the second gate electrode.