Patent ID: 8237504

Claim:
A method of fabricating a solid state power amplifier (SSPA) having variable output power, comprising: coupling a first transistor device to a second transistor device; biasing a drain input of the first transistor device with a first transistor drain bias voltage and biasing a gate input of the first transistor device with a first transistor gate bias voltage; biasing a drain input of the second transistor device with a second transistor drain bias voltage and biasing a gate input of the second transistor device with a second transistor gate bias voltage, the second transistor drain bias voltage being a different value than the first transistor drain bias voltage, thereby varying a drain to source current of each of the first and second transistor devices to enable the SSPA to maintain consistent power added efficiency (PAE) and consistent linearity over a range of output power levels; and maintaining a PAE of at least 38% over the range of output power levels, the range of output power levels being at least 5 dB.