Patent ID: 7397683

Claim:
An associative memory comprising: a) m associative-memory words (m and n are positive integers) including: n-th data cells which store m storage data with n bit length; n-th mask cells which store mask information which indicates a mask valid/invalid state of a corresponding bit representative of whether or not each bit of the storage data should be excluded from a search object; n-th comparators which compare for each word an input data and the storage data and outputs for a word having a matched result of the comparison a coincidence signal onto a match line; and n-th logical gates which perform a logical operation of data on the match line and the storage data for each bit sequence and outputs onto a matched data intermediate logical line a first logical value in the case that both of the data are in a valid state, or outputs a second value indicative of an opened state in the other cases; b) a latch circuit which stores n-bit intermediate matched data output onto the matched data intermediate logical line; c) a selector circuit which selectively supplies the associative memory word with either of search data or the intermediate matched data as the input data; and d) a controller which controls the comparator so as to perform a comparison taking the mask information into account when the search data is selected as the input data, and not taking the mask information into account when the intermediate matched data is selected.