Patent ID: 8436801

Claim:
A level shift circuit, suitable for receiving a plurality of input clock pulse signals and a charge sharing signal and for performing a charge sharing operation on each of the input clock pulse signals to generate a plurality of output clock pulse signals, the level shift circuit comprising: a control logic circuit, configured for receiving the input clock pulse signals and the charge sharing signal and for acquiring voltage level information of each of the input clock pulse signals and voltage level information of the charge sharing signal; a plurality of level shift output buffers, each of the level shift output buffers having an input terminal and an output terminal, the input terminals of the level shift output buffers being electrically coupled to the control logic circuit, each of the level shift output buffers being configured for amplifying a corresponding one of the input clock pulse signals and determining whether to output the output clock pulse signal according to the voltage level information of the charge sharing signal acquired by the control logic circuit; and a plurality of charge sharing circuits, each of the charge sharing circuits being electrically coupled between a predetermined voltage level and the output terminal of a corresponding one of the level shift output buffers, each of the charge sharing circuits determining whether to be turned on according to the voltage level information of a corresponding one of the input clock pulse signals and the charge sharing signal acquired by the control logic circuit, when one of the charge sharing circuits is turned on, the predetermined voltage level and the output terminal of a corresponding one of the level shift output buffers are electrically coupled to each other only, so as to perform the charge sharing operation.