Patent ID: 8482080

Claim:
An integrated circuit, comprising: a PMOS transistor, further including: a PMOS nitrogen containing barrier layer formed on a top surface of a PMOS gate dielectric layer; a PMOS low oxygen metal layer with a work function greater than 5 electron volts and an oxygen concentration less than 2 percent, formed on a top surface of said PMOS nitrogen containing barrier layer; a PMOS oxygen rich metal layer with a work function greater than 5 electron volts and an oxygen concentration greater then 10 percent, formed on a top surface of said PMOS low oxygen metal layer; and a PMOS top metal layer with a work function greater than 5 electron volts, formed on a top surface of said PMOS oxygen rich metal layer; and an n-channel metal oxide semiconductor (NMOS) transistor, further including a metal gate layer with a work function less than 5 electron volts and an oxygen concentration less than 2 percent, formed on a top surface of an NMOS gate dielectric layer.