Patent ID: 8879579

Claim:
A communication adapter comprising: a buffer configured to store a first sub-unit and a second sub-unit of a message; transmitting process logic operatively connected to the buffer, comprising: a collect buffer unit module configured to receive, from a transmitting device, a request to send the message; a virtual kick module configured to temporarily store the request once the request is entirely received; a queue pair fetch module configured to obtain, from the transmitting device, a queue pair status information corresponding to the request; a direct memory access (DMA) module configured to obtain the message from a location in memory of the transmitting device, wherein the location is specified in the request, a sub-unit builder module configured to: modify a maximum transfer unit (MTU) to obtain a modified MTU; divide the message to obtain the first sub-unit based on the modified MTU; iteratively increase the MTU for transmitting a plurality of intermediate sub-units of the message until an MTU limit is reached to obtain a plurality of iteratively increased MTUs; and divide the message to obtain the plurality of intermediate sub-units using the plurality of iteratively increased MTUs; and a port configured to: transmit, to a receiving system, the first sub-unit of the message using the modified MTU; transmit, to the receiving system, the plurality of intermediate sub-units of the message, wherein the plurality of intermediate sub-units are transmitted after the first sub-unit and before the second sub-unit; and transmit, to the receiving system, the second sub-unit to the receiving system using a full path MTU.