Patent ID: 8610486

Claim:
A current-mode analog computational circuit, comprising: a first multiplier circuit, wherein a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) are configured to operate in a sub-threshold region to form at least one translinear loop, the first multiplier circuit configured to generate a first circuit output current related to a plurality of AC input currents, a plurality of DC input currents, and at least one DC biasing input current; a current inversion circuit, wherein a portion of the plurality of AC input currents are inverted to generate a plurality of inverted AC input currents; a second multiplier circuit, wherein a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) are configured to operate in a sub-threshold region to form at least one translinear loop, the second multiplier circuit configured to generate a second circuit output current related to the plurality of inverted AC input currents, the plurality of DC input currents, and the at least one DC biasing input current; and wherein the current-mode analog computational circuit generates a resulting output current comprising the first circuit output current and the second circuit output current, the resulting output current corresponding to a function output current, the function output current corresponding to at least one of a multiplying function output current, a squaring function output current, a divider function output current, and an inverse function output current, the function output current being related to the plurality AC input currents, the plurality of DC input currents, and the at least one DC biasing input current.