Patent ID: 7466577

Claim:
A semiconductor storage device comprising: a base substrate having a command/address external terminal group to which command signals, address signals, and a clock signal are supplied, a data input/output external terminal group for inputting and outputting data signals, and a single chip select external terminal; a plurality of memory chips that are stacked on the base substrate and are each individually capable of reading and writing operations; and an interface chip having an interface function, wherein a plurality of terminals constituting said command/address external terminal group, a plurality of terminals constituting said data input/output external terminal group, and said single chip select external terminal are connected to the interface chip; and the interface chip further has at least a chip select signal generation circuit that can individually activate said plurality of memory chips based on said address signals supplied via said command/address external terminal group and latched in synchronism with the clock signal, and based on said chip select signal supplied via said chip select external terminal and latched in synchronism with the clock signal.