Patent ID: 7849450

Claim:
A device comprising: a processor adapted to, first restore a state of a preceding checkpoint relative to a current simulation position, the current simulation position being a point of interest in a simulation, simulate the entire simulation forward from the preceding checkpoint by replaying recorded events and noting breakpoints or watch points regardless of breakpoints or watch points encountered while simulating from the preceding checkpoint to the current simulation position, the recorded events including non-deterministic events, and the simulating forward from the preceding checkpoint to the current simulation position having a same instruction flow as an initial simulation, second restore the state of a last occurring breakpoint or watch point preceding the current simulation position, after reaching the current simulation position, load the state of an earlier checkpoint; and repeat the first restoring, the simulating, the noting, the second restoring, and the loading, if no breakpoint or watch point occurred between the preceding checkpoint and the current simulation position to form an iterative process in which successively earlier checkpoints are restored, the earlier checkpoint being prior to the preceding checkpoint in the simulation.