Patent ID: 7584314

Claim:
An apparatus comprising: circuitry operable to receive serial data over a transmission medium and convert the serial data into a parallel format for transmission in a first mode, the circuitry also configured to receive parallel data and convert the parallel data into a serial format for transmission over the transmission medium in a second mode; and a controller configured to selectively configure the circuitry to operate in the first mode or the second mode; wherein the circuitry comprises: an equalizer configured to (i) equalize the serial data from the transmission medium to produce equalized serial data and (ii) output the equalized serial data: a parallel-to-serial converter configured to (i) convert the parallel data into the serial format to produce serialized data and (ii) output the serialized data: a multiplexer having a first input coupled to an output of the equalizer and a second input coupled to an output of the parallel-to-serial converter, the multiplexer configured to output a serial data signal comprising one of the equalized serial data and the serialized data depending on whether the circuitry is configured to operate in the first mode or the second mode; a reclocker having an input coupled to an output of the multiplexer, the reclocker configured to (i) reclock the serial data signal provided by the multiplexer to produce a reclocked serial data signal and (ii) provide the reclocked serial data signal to a cable driver, the cable driver configured to transmit the reclocked serial data signal over the transmission medium; a serial-to-parallel converter configured to (i) convert the reclocked serial data signal into the parallel format to produce parallelized data and (ii) output the parallelized data: and a clock multiplier/divider configured as a clock divider in the first mode and a clock multiplier in the second mode, the clock divider configured to divide a first clock signal received from the reclocker and to output the divided first clock signal in the first mode, the clock multiplier configured to multiply a second clock signal and to output the multiplied second clock signal to the parallel-to-serial converter in the second mode.