Patent ID: 8058691

Claim:
A semiconductor device, comprising: a first transistor of a first transistor type defined by a first gate electrode and a first diffusion region of a first diffusion type electrically connected to a common diffusion node; a first transistor of a second transistor type defined by a second gate electrode and a first diffusion region of a second diffusion type electrically connected to the common diffusion node; a second transistor of the first transistor type defined by a third gate electrode and a second diffusion region of the first diffusion type electrically connected to the common diffusion node; a second transistor of the second transistor type defined by a fourth gate electrode and a second diffusion region of the second diffusion type electrically connected to the common diffusion node, wherein the first and fourth gate electrodes are electrically connected to each other, wherein the second and third gate electrodes are electrically connected to each other, wherein the first gate electrode is a portion of a first linear-shaped gate level feature, wherein the second gate electrode is a portion of a second linear-shaped gate level feature, wherein the third gate electrode is a portion of a third linear-shaped gate level feature, wherein the fourth gate electrode is a portion of a fourth linear-shaped gate level feature, wherein each of the first, second, third, and fourth linear-shaped gate level features extends lengthwise in a first direction and is physically separate from another gate level feature, and wherein the first and second diffusion regions of the first diffusion type are physically separated from each of the first and second diffusion regions of the second diffusion type.