Patent ID: 6985027

Claim:
A semiconductor integrated circuit comprising: a power supply voltage step down circuit which is supplied with a power supply voltage and which outputs an internal power supply voltage lower than the power supply voltage to an internal power supply line; and a MOS circuit group including one or more MOS transistors which are supplied with the internal power supply voltage from the internal power supply line to operate, wherein the power supply voltage step down circuit estimates an amount of gate leakage currents flowing in the MOS circuit group and lowers the internal power supply voltage as the estimated amount of the gate leakage currents becomes large, wherein the power supply voltage step down circuit comprises: a reference voltage generating circuit which generates a reference voltage which is varied according to the estimated amount of the gate leakage currents; and a control circuit which performs feedback control in order that the voltage of the internal power supply line is eciual to the reference voltage, wherein the reference voltage generating circuit comprises a dummy MOS transistor of which a source and of which a drain are connected to each other, and the reference voltage generating circuit varies the reference voltage according to an amount of a gate leakage current flowing from a gate of the dummy MOS transistor to the source and the drain of the dummy MOS transistor, and wherein the reference voltage generating circuit comprises: a first resistance element, one end of which is connected to the gate of the dummy MOS transistor, wherein a node between the one end of the first resistance element and the gate of the dummy MOS transistor serves as an output node which outputs the reference voltage; a second resistance element, one end of which is connected to the other end of the first resistance element; a third resistance element, one end of which is connected to the other end of the second resistance element, and the other end of which is connected to the source and the drain of the dummy MOS transistor, wherein a node between the one end of the third resistance element and the other end of the second resistance element serves as a comparative node which outputs a comparative voltage; and a comparative supply circuit which compares the reference voltage of the output node with the comparative voltage of the comparative node and which supplies a voltage to the other end of the first resistance element and the one end of the second resistance element in order that the reference voltage is equal to the comparative voltage.