Patent ID: 8917228

Claim:
A liquid crystal display apparatus, comprising: a liquid crystal display panel comprising a plurality of liquid crystal capacitors, a plurality of pixel units, an upper alignment film layer and a lower alignment film layer, wherein the liquid crystal impedance is larger than or equal to 10 13 ohm/cm, and an alignment-film impedance of the liquid crystal display panel is larger than or equal to ten times of the liquid crystal impedance; and a driving circuit comprising a display refresh rate, the driving circuit being configured for casting the image information on the liquid crystal display panel; a plurality of pixel driving circuits, disposed corresponding to the pixel units, the pixel driving circuits comprising a plurality of storage capacitors, wherein the storage capacitors respectively correspond to the liquid crystal capacitors, a capacitance of the storage capacitors is larger than or equal to ten times of that of the liquid crystal capacitors, wherein each of the driving circuits comprises two or more thin film transistor switches, a dual-gate thin film transistor or a lightly doped drain thin film transistor corresponding to each pixel unit, and an off-state leakage current of the driving circuit is less than or equal to 10 −12 ampere, wherein each of the plurality of pixel units of the liquid crystal display panel at least corresponds to one of the liquid crystal capacitors and one of the storage capacitors, each pixel unit comprises a first electrode layer, a second electrode layer and a third electrode layer sequentially disposed on a lower substrate, the second electrode layer comprises an extension layer of a drain layer, the third electrode layer comprises a pixel electrode layer, dielectric layer materials are respectively disposed between the first electrode layer and the second electrode layer, and between the second electrode layer and the third electrode layer, the first electrode layer comprises a gate layer and/or a common electrode conductive layer, and the extension layer of the drain layer is connected with the pixel electrode layer, and/or the common electrode conductive layer is electrically connected with a common transparent electrode layer of a upper substrate, wherein the liquid crystal capacitor is formed between the common transparent electrode layer and the pixel electrode layer of the lower substrate, and the storage capacitor is disposed between the common electrode conductive layer of the first electrode layer and the extension layer of the second electrode layer, and/or between the common electrode conductive layer of the first electrode layer and the pixel electrode layer, and/or between the gate layer of the first electrode layer and the pixel electrode layer.