Patent ID: 8538718

Claim:
A method of grouping clock domains for testing an integrated circuit, the method being implemented using a computer device comprising a processor and comprising: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the plurality of domain groups in decreasing order of size; and creating a plurality of parts by performing one of the following for each respective one of the plurality of domain groups in the decreasing order of size: (i) adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source; and (ii) creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.