Patent ID: 7635643

Claim:
In the manufacturing method of an integrated circuit chip in which the chip is physically and electrically connected to a substrate of a carrier package by area-array Pb-free solder bumps on the face of the chip, comprising the steps of: fabricating the circuitry including metallization within the chip; depositing an insulating layer of a thick layer and three thinner layers under the thick layer on the upper surface of the chip; using a dual damascene process, after depositing said insulating layer, to etch in the insulating layer a lower smaller cavity aligned with and extending to the metallization within the chip and an upper larger cavity for a capture pad; continue using the dual damascene process to fill the lower and upper cavities with ball limiting metallization to form a capture pad for a solder bump and a via to the metallization within the chip; depositing Pb-free solder on the capture pad; and reflowing the Pb-free solder to form a solder bump.