Patent ID: 7592247

Claim:
A method for forming a semiconductor device, comprising: forming first and second active device regions in a semiconductor substrate, wherein said first and second active device regions are isolated from each other by an isolation region therebetween, said first active device region including a first pull-down transistor of a SRAM cell and said second active device region including a first pull-up transistor of said SRAM cell; and forming a first sub-lithographic interconnect structure that has a width ranging from about 20 nm to about 40 nm for cross connecting the first pull-down transistor to said second pull-up transistor, said forming the first sub-lithographic interconnect structure including: forming an inter-level dielectric (ILD) layer over the first and second active device regions; forming a lithographically patterned mask layer over the ILD layer, wherein said lithographically patterned mask layer defines a first lithographic mask opening having a width ranging from about 60 nm to about 100 nm; applying a layer of a block copolymer comprising polystyrene-block-polymethylmethacrylate (PS-b-PMMA) having a PS:PMMA weight ratio from about 60:40 to about 40:60 over the lithographically patterned mask layer, wherein said block copolymer comprises at least first and second polymeric block components that are immiscible with each other; annealing the block copolymer layer to form a single unit polymer block having a sub-lithographic width ranging from about 20 nm to about 40 nm inside the first lithographic mask opening, wherein the single unit polymer block comprises the second polymeric block component and is embedded in a polymeric matrix that comprises the first polymeric block component; selectively removing the second polymeric block component relative to the first polymeric block component to form a first sub-lithographic opening having a width ranging from about 20 nm to about 120 nm in the polymeric matrix inside the first lithographic mask opening; and patterning the ILD layer using the first sub-lithographic opening and filling the first sub-lithographic opening with a conductive material.