Patent ID: 7594126

Claim:
A method for controlling a power supply voltage comprising: converting the power supply voltage supplied to a processor from a first level to an idle level in an idle mode; operating the processor at a low operation speed in comparison with an operation speed in a first mode until the power supply voltage is increased to the first level, wherein operating the processor at the low operation speed includes providing a clock signal having a low frequency as compared to a frequency in the first mode and having a high frequency as compared to a frequency in the idle mode, to the processor until the power supply voltage supplied to the processor is increased to the first level, wherein operating the processor in the low operation speed comprises: dividing a clock signal inputted from outside the processor by a given divisor until the power supply voltage supplied to the processor is increased to the first level; wherein a clock and power control block includes a plurality of dividers for dividing the first clock signal by the given divisor, and, providing a divided clock signal to the processor.