Patent ID: 7971038

Claim:
A pipeline comprising: a stage; a next stage; at least one data transfer line for transmitting data from the stage to the next stage; a request line for transmitting a request signal from the stage to the next stage indicating that the at least one data transfer line holds valid data; and an acknowledgement line for transmitting an acknowledgement signal from the next stage to the stage indicating that the next stage is occupied; and a controller in the stages, the controllers being arranged to cooperate: (i) to wait for both of two data-transfer conditions to be true with either both the request signal and the acknowledgement signal asserted, or neither the request and acknowledgement signal asserted, wherein the first data-transfer condition is that the data transfer line holds valid data and the second data-transfer condition is that the next stage is empty; (ii) to transfer data down the data transfer line from the stage to the next stage with the request signal asserted and the acknowledgement signal de-asserted, and then to assert the acknowledgement signal; (iii) with the request signal asserted and the acknowledgement signal asserted, to de-assert the request signal; and (iv) to wait for one of the two data-transfer conditions to be satisfied with the acknowledgement signal asserted and the request signal de-asserted; wherein the stages include: a latch register; a data input for accepting a data item from the immediately preceding stage into the latch register; a data output for outputting a data item to the next stage from the latch register; an acknowledgement input for accepting an acknowledgement signal from the next stage confirming that a data item has been received; a request input for accepting a request signal from the previous stage indicating that the previous stage is ready to transmit a data item; and a combined request and acknowledgement output arranged to output a combined request signal to the request input of the next stage and an acknowledgement signal to the acknowledgement input of the previous stage to acknowledge receipt of a data item from the previous stage and to request transmission of the data item to the next stage; wherein the controller includes: a first latch having set and reset states; and a second latch having set and reset states; wherein the controller is arranged: to reset the first latch when a condition applies that the request signal on the request input is asserted and the combined request and acknowledgement signal on the combined request and acknowledgement output is de-asserted; to set the second latch when the acknowledgement signal received on the acknowledgement input from the next stage is not asserted and the condition applies; to set the first latch when the second latch is set and the combined request and acknowledgement signal is not asserted; and to reset the second latch when the combined request and acknowledgement signal is not asserted.