Patent ID: 6970798

Claim:
A method for testing an electrical device under test (â€œDUTâ€) having address and data input pins coupled to respective channel cards in a test head for writing data to memory cells of the DUT, wherein specified tests define test patterns and for such a pattern test vectors define data for associated sets of address bits, the method comprising the steps of: generating pin vectors for respective ones of the channel cards and DUT pins by a pin vector generator process of a computer system program, wherein generating such a pin vector includes selecting, from the test vectors, bits for the pin vector's respective one of the address or data pins such that the pin vector has a sequence of bits for driving its DUT pin to a sequence of states; generating DUT vectors for specifying timing and voltage for the tests, wherein ones of the DUT vectors apply to numerous ones of the DUT pins and numerous ones of the tests; compressing the pin vectors; forming packets, wherein such a packet contains one of the compressed pin vectors, an address for the pin vector's associated channel card and a pointer to one or more of the DUT vectors; and sending the packets and the DUT vectors to the respective channel cards via a pipeline, wherein the pipeline includes a data bus from a main frame to the test head and the sending of the pin vectors includes: transmitting the packets over the data bus, wherein the data bus is numerous bits wide and bits of such a packet are transmitted in parallel on numerous bits of the data bus; and controlling timing of the transmitting by optical control signals transmitted from the main frame to the test head over an optical control bus, wherein the optical control signals include a high frequency reference clock.