Patent ID: 7776759

Claim:
A method for forming an integrated circuit including a mold layer having an opening having a diameter of less than 500 nanometers, comprising: providing a substrate having a substrate surface with a first area section and a second area section; growing a vertical template pillar composed of a self-assembling stencil material in the first area section; forming the mold layer onto the second area section after the growth of the template pillar; and removing the template pillar after the application of the mold layer, the opening being formed in the mold layer over the first area section of the substrate; wherein the growth of the template pillar comprises: providing a catalyst cluster composed of a catalyst material on the first area section, the catalyst material being able to form a liquid alloy with the stencil material, upon the cooling of which liquid alloy the stencil material crystallizes out in pure form; melting of the catalyst material, the liquid alloy being formed from the stencil material and the catalyst material; supplying the stencil material, the liquid alloy being supersaturated with the stencil material and the stencil material growing on the first area section as a nanowire; and removing the catalyst material prior to the removal of the template pillar.