Patent ID: RE39690

Claim:
An integrated circuit manufactured by the method comprising the acts of: (a.) providing a partially fabricated integrated circuit structure; (b.) applying and curing spin-on glass, to form a first dielectric layer; (c.) depositing dielectric material, to form a second dielectric layer over said first dielectric layer; (d.) applying and curing spin-on glass, to form a third dielectric layer, to produce a stack including said third dielectric layer over said first and second dielectric layers; (e.) performing a global etchback to substantially remove portions of said dielectric stack from high points of said partially fabricated structure, wherein at least a portion of said third dielectric layer remains after said global etchback; (f.) deposition of an interlevel dielectric at least over said remaining third dielectric layer; (g.) etching holes in said interlevel dielectric in predetermined locations; and (h.) depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.