Patent ID: 8037340

Claim:
An apparatus for micro-tuning an effective clock frequency of a core in a microprocessor, comprising: a microprocessor including at least one core, said at least one core comprising logic that is configured to transition between states; a clock signal coupled to said microprocessor, said clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period, said predetermined clock period being an inverse of said predetermined clock frequency; and at least one sensor coupled to said at least one core in said microprocessor, said at least one sensor being configured to generate a sensor output signal for detecting at least one level of voltage drop in said at least one core when said logic within said at least one core is transitioning between states, said at least one sensor being configured to determine whether or not said sensor output signal generated is detected within said predetermined clock period, wherein if said sensor output signal generated is not detected within said predetermined clock period, said at least one sensor dynamically adjusts said predetermined clock period of said clock signal to allow said at least one core more time to complete said transitioning between states by temporarily delaying a rising edge of said clock signal to increase said predetermined clock period, and wherein if said sensor output signal generated is detected before a clock falling edge of said clock signal, said at least one sensor does not trigger adjustment of said predetermined clock period at said clock falling edge of said clock signal, wherein said effective clock frequency of said at least one core in said microprocessor remains unadjusted, and wherein dynamically adjusting said predetermined clock period effectively changes an effective clock frequency of said at least one core in said microprocessor.