Patent ID: 8413026

Claim:
A method of performing forward error correction with configurable latency, comprising: (a) a plurality of data input to a transmission system, wherein said data includes a target bit error rate; (b) a configurable size buffer with a plurality of buffer locations, wherein a forward error correction code corrects said data as said data is transmitted through said buffer; (c) an error monitor to evaluate an actual bit error rate of said data output from said configurable size buffer; and (d) a configurable latency algorithm, wherein said algorithm begins by utilizing the maximum number of available buffer locations to achieve said target bit error rate, and said algorithm then reduces the size of said buffer by y buffer locations when errors are corrected without the utilization of each of said buffer locations, whereby said algorithm may continue to successively reduce the size of said buffer until the minimum number of said buffer locations are utilized to achieve said target bit error rate or, where said buffer locations have been reduced such that said buffer size is too small and said target bit error rate cannot be achieved, said algorithm may increase the size of said buffer until the minimum number of said buffer locations are utilized to achieve said target bit error rate.