Patent ID: 7328420

Claim:
A computer-implemented method for using a computer-aided design tool to provide assistance to a circuit designer, comprising: with at least one computer aided design tool, receiving design data and constraint data for a circuit design and producing a corresponding output, wherein producing the output includes producing report data on a given implementation of the circuit design in an integrated circuit; processing the report data and the constraint data with an optimization assistance tool, wherein processing the report data and the constraint data comprises identifying potential problems and presenting at least one selectable option to the circuit designer that allows the circuit designer to automatically launch the computer aided design tool to modify the constraint data to address the potential problems, wherein the constraint data includes placement constraints for a programmable logic device that identify which circuit nodes are located in certain regions of programmable logic when the circuit design is implemented in a particular type of programmable logic device integrated circuit; displaying a selectable option for the circuit designer with the optimization assistance tool that the circuit designer selects to automatically launch a programmable logic device placement constraints editor; and displaying a screen for the circuit designer with the programmable logic device placement constraints editor that the circuit designer uses to make adjustments to the placement constraints.