Patent ID: 7015737

Claim:
A delay locked loop, comprising: an input buffer for buffering a clock signal; a first switching circuit for transferring a clock signal outputted from the input buffer in response to a control signal; a frequency doubler for increasing a frequency of the clock signal transferred from the first switching circuit; a variable delay line for delaying the clock signal outputted from the frequency doubler or from the first switching circuit; a second switching circuit for transferring the clock signal from the variable delay line in response to the control signal; a frequency divider for decreasing the frequency of the clock signal outputted from the second switching circuit; an output buffer for buffering the clock signal outputted from the second switching circuit or from the frequency divider; a replica for delaying the clock signal outputted from the variable delay line; a phase detector for detecting a phase difference between the clock signal outputted from the replica and the clock signal outputted from the frequency doubler or from the first switching circuit; and a control circuit for determining a delay amount of the variable delay line according to an output signal of the phase detector.