Patent ID: 8707094

Claim:
A circuit arrangement, comprising: a plurality of redundant execution pipelines disposed in at least one processing core on at least one integrated device; issue logic coupled to the plurality of redundant execution pipelines, the issue logic configured to concurrently issue a plurality of non-stability critical instructions to the plurality of redundant execution pipelines such that the plurality of non-stability critical instructions are executed in parallel by the plurality of redundant execution pipelines, the issue logic further configured to concurrently issue a plurality of instances of a stability critical instruction to multiple redundant execution pipelines from the plurality of redundant execution pipelines such that the multiple instances of the stability critical instruction are executed in parallel by the multiple redundant execution pipelines; and fault detection logic coupled to the multiple redundant execution pipelines and configured to determine a fault during execution of at least one instance of the stability critical instruction; wherein the issue logic is configured to determine that the stability critical instruction is stability critical, wherein the issue logic is configured to determine that the stability critical instruction is stability critical by checking a mode indicator associated with the stability critical instruction, wherein the issue logic is configured to issue instructions from a plurality of threads, and wherein the mode indicator is associated with a thread associated with the stability critical instruction.