Patent ID: 8314641

Claim:
A delay lock loop comprising: a fine delay block comprising: a plurality of fine shift registers configured to receive a first enable signal from a fine delay control and configured to produce a second enable signal; and a plurality of fine delay units configured to receive the second enable signal and produce a fine delay unit output comprising a shifted input signal, wherein each of the plurality of fine delay units is configured to shift a signal by a first time delay; and a coarse delay block comprising: a coarse delay shift register configured to be controlled by the fine delay block and produce a third enable signal; and a plurality of coarse delay units configured to receive the third enable signal and wherein each of the plurality of coarse delay units is configured to shift a signal by a second time delay, wherein the second time delay is greater than the first time delay, wherein the coarse delay block comprises an inverter, the inverter having a single input and being configured to control shifting a signal in the coarse delay block, wherein in the event that the fine delay block shifts the input signal by the second time delay, the fine delay block is reset.