Patent ID: 8530960

Claim:
A semiconductor device comprising a static memory cell having six MOS transistors arranged on a substrate, the six MOS transistors including first and second NMOS access transistors for accessing a memory, third and fourth NMOS driver transistors for driving a storage node that holds data of the memory cell, and first and second PMOS load transistors that supply charges for holding the data of the memory cell, each of the first and second NMOS access transistors for accessing the memory having a first diffusion layer, a pillar-shaped semiconductor layer, and a second diffusion layer arranged vertically with respect to the substrate in a hierarchical manner so that the pillar-shaped semiconductor layer resides between the first diffusion layer and the second diffusion layer, the pillar-shaped semiconductor layer having a gate on a side wall thereof, each of the third and fourth NMOS driver transistors for driving the storage node that holds the data of the memory cell having a third diffusion layer, a pillar-shaped semiconductor layer, and a fourth diffusion layer arranged vertically with respect to the substrate in a hierarchical manner so that the pillar-shaped semiconductor layer resides between the third diffusion layer and the fourth diffusion layer, the pillar-shaped semiconductor layer having a gate on a side wall thereof, each of the first and second PMOS load transistors that supply the charges for holding the data of the memory cell having a fifth diffusion layer, a pillar-shaped semiconductor layer, and a sixth diffusion layer arranged vertically with respect to the substrate in a hierarchical manner so that the pillar-shaped semiconductor layer resides between the fifth diffusion layer and the sixth diffusion layer, the pillar-shaped semiconductor layer having a gate on a side wall thereof, wherein the first diffusion layers, the third diffusion layers, and the fifth diffusion layers electrically insulated from the substrate, and wherein a length between an upper end of the third diffusion layer and a lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors is shorter than a length between an upper end of the first diffusion layer and a lower end of the second diffusion layer of each of the first and second NMOS access transistors, and a length between the upper end of the third diffusion layer of each of the third and fourth NMOS driver transistors and a lower end of the gate is different from a length between the lower end of the fourth diffusion layer of each of the third and fourth NMOS driver transistors and an upper end of the gate.