Patent ID: 7941603

Claim:
An advanced processor, comprising: a plurality of processor cores each having a data cache; a data switch interconnect coupled with the data cache of each of the plurality of processor cores, in which the data switch interconnect passes information or data among the plurality of processor cores; means for implementing flow control to manage transmitting data by at least one processor core of the plurality of processor cores based at least in part upon a characteristic of the at least one processor core that performs the action of transmitting the data, wherein the characteristic is used to permit and to stop the at least one processor core from performing the action of transmitting the data and a level 2 cache coupled to the data switch interconnect which allows sharing of dirty cache lines across the plurality of processor cores, wherein the data switch interconnect includes a ring arrangement with a plurality of ring elements that are coupled to a respective data cache of the plurality of processor cores and a respective portion of the level 2 cache rather than directly coupled to an instruction cache of at least one of the plurality of processor cores.