Patent ID: 7041544

Claim:
A method for fabricating a semiconductor integrated circuit of a CMOS structure comprising: a first static random access memory (SRAM) operating at a first frequency, power to the first SRAM being shut off as required; a first logic circuit accessing the first SRAM; a second SRAM operating at a second frequency lower than the first frequency, power to the second SRAM being kept supplied during the shutoff of power to the first SRAM; and a second logic circuit accessing the second SRAM, the first SRAM including a first SRAM cell array and a first peripheral circuit for mediating access to the first SRAM cell array, the second SRAM including a second SRAM cell array and a second peripheral circuit for mediating access to the second SRAM cell array, the method comprising the steps of: setting the average channel width of MOS transistors constituting each of the first and second SRAM cell arrays at a half or less of the average channel width of MOS transistors constituting each of the first and second peripheral circuits and the first and second logic circuits; performing ion implantation so that the MOS transistors of the first and second SRAM cell arrays, the first peripheral circuit and the first logic circuit have a uniform channel impurity concentration; and performing additional ion implantation for channel regions of the MOS transistors of the second SRAM cell array so that the channel impurity concentration of the MOS transistors of the second SRAM cell array is higher than the channel impurity concentration of the MOS transistors of the first SRAM cell array, the first peripheral circuit and the first logic circuit, to thereby allow the MOS transistors of the first SRAM cell array to have a threshold voltage lower than the MOS transistors of the second SRAM cell array as for at least either N-channel MOS transistors or P-channel MOS transistors.