Patent ID: 7523259

Claim:
A high-speed read cache memory, comprising: a memory array comprising word lines each including a plurality of memory latches structured to save a datum comprising a source datum and a tag associated with the source datum; and a cache managing circuit for managing the cache memory, comprising a hard-wired logic asynchronous circuit for reading the memory array, without address decoder, the asynchronous circuit having no clock and being arranged for receiving a reference tag at input, for simultaneously comparing all the tags present in the memory array relative to the reference tag and then, if a tag is identical to the reference tag, asynchronously selecting the source datum associated with the identical tag and asynchronously supplying the source datum to an output of the cache managing circuit, wherein “asynchronously” means “without being clocked”, wherein the asynchronous circuit includes: a plurality of hard-wired comparators corresponding respectively with the memory latches of the memory array, each hard-wired comparator being structured to simultaneously compare the reference tag with the tag saved in the corresponding memory latch and output a match signal if the reference tag matches the tag saved in the corresponding memory latch, and a plurality of selectors corresponding respectively with the hard-wired comparators, each selector being structured to, if the match signal is received, select and output the source datum associated with the matching tag.