Patent ID: 8298927

Claim:
A method of adjusting an effective work function of a metal nitride gate of an NMOS device, comprising: step 1) forming an interfacial oxide layer of SiOx or SiON after formation of a device isolation, wherein the interfacial oxide layer of SiOx or SiON is formed by rapid thermal oxidation at a temperature of 600-900° C. for 20-120 s; step 2) forming a high dielectric constant gate dielectric film by a PVD process, wherein by means of magnetic-controlled reactive sputtering, a HfLaON film is deposited as a gate dielectric by alternately sputtering a Hf—La target and a Hf target, or a HfSiON film as a gate dielectric is deposited by alternately sputtering a Hf target and a Si target; step 3) performing rapid thermal annealing at a temperature of 600-1050° C. for 10-120 seconds after deposition of the high dielectric constant gate dielectric film; step 4) forming a metal nitride gate electrode by a PVD process, wherein a metal nitride gate is sputtered and deposited by magnetic-controlled reactive sputtering; step 5) doping the metal nitride gate by implanting N-type metal ions into the metal nitride gate electrode, but not into the high dielectric constant gate dielectric film; step 6) etching to form a pattern of the metal nitride gate electrode; step 7) performing thermal annealing at a temperature of 350-1050° C. so that metal ions are driven to and accumulate at an interface between the metal nitride gate electrode and the high dielectric constant gate dielectric film and at an interface between the high dielectric constant gate dielectric film and the interfacial oxide layer, wherein the metal ions at the interface between the metal nitride gate electrode and the high dielectric constant gate dielectric film modify properties of the metal nitride gate so as to tune the effective work function, and the metal ions at the interface between the high dielectric constant gate dielectric film and the interfacial oxide layer to orm dipoles by interface reaction so as to further tune the effective work function; step 8) forming a back ohmic contact by a PVD process, wherein an Al—Si film is deposited at a back side of the NMOS device by direct current sputtering; and step 9) alloying, in N 2 or (N 2 +10% H 2 ) in an oven at a temperature of 380-450° C. for 30-60 minutes.