Patent ID: 8850175

Claim:
A resetting method for a real time clock of a computer apparatus, the resetting method comprising: generating a judging result by determining whether the computer apparatus is in an S 5 state and determining whether a plurality of pre-determined keys are simultaneously pressed; pulling down a resume reset signal according to the judging result and correspondingly pulling down an operating voltage; pulling down an S 5 enabling signal after pulling down the operating voltage for a pre-determined delay time; and generating a real time clock reset signal for resetting the real time clock after pulling down the S 5 enabling signal, when the judging result is negative and the computer apparatus is in an operation state, writing a real time clock reset command into an embedded controller of the computer apparatus by providing a writing interface, and generating the real time clock reset signal for resetting the real time clock by the embedded controller according to the real time clock reset command.