Patent ID: 6956426

Claim:
An integrated high-voltage switching circuit comprising: a switch having ON and OFF states and having a parasitic gate capacitance, said switch comprising a pair of DMOS transistors integrated back to back and having a shared gate terminal, the drains of said DMOS transistors being connected to the input and output terminals of said switch respectively; and a turn-on circuit comprising a PMOS transistor having its drain connected to said shared gate terminal of said switch via a first diode, having its source connected to a first global switch gate bias voltage terminal from which said PMOS transistor draws current, and having its gate electrically coupled to a first switch gate control terminal that receives a first switch gate control voltage input, wherein said switch transitions from the OFF state to the ON state in response to a first transition of said first switch gate control voltage input that causes said PMOS transistor to turn on, and said switch remains in said ON state in response to a second transition of said first switch gate control voltage input that causes said PMOS transistor to turn off.