Patent ID: 7259098

Claim:
A method for fabricating a semiconductor device comprising: forming a first gate electrode including a dielectric layer, a first conducting layer formed on the dielectric layer, and a first insulating layer formed on the conducting layer on a substrate, the first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode comprising a gate oxide layer and a second conducting layer on the substrate, the second gate electrode functioning as a normal gate electrode; performing a first ion implantation process using at least one of the first spacers as a mask to form a shallow junction region for a source/drain region; forming second spacers on a sidewall of the first spacer and on sidewalls of the second gate electrode; and performing a second ion implantation process using at least one of the second spacers as a mask to form a deep junction region for the source/drain region.