Patent ID: 8045335

Claim:
A semiconductor device comprising: a first assembly including: a first semiconductor chip, a high-voltage bus bar that is bonded to one surface of the first semiconductor chip and that has a high-voltage terminal, a first metal wiring board that is connected to another surface of the first semiconductor chip using a bonding wire, and a third metal wiring board that is linked to the first metal wiring board, is separated by a prescribed interval from the bonding wire connected to the other surface of the first semiconductor chip, and is positioned parallel to the high-voltage bus bar; a second assembly including: a second semiconductor chip, a low-voltage bus bar that is connected to one surface of the second semiconductor chip using a bonding wire and that has a low-voltage terminal, a second metal wiring board that is bonded to another surface of the second semiconductor chip, and a fourth metal wiring board that is linked by being bent from an end portion of the second metal wiring board, is separated by a prescribed interval from the bonding wire connected to the second semiconductor chip, and is positioned parallel to the second metal wiring board; and an output bus bar having an output terminal extending from each end portion of the third metal wiring board and of the fourth metal wiring board, wherein the first assembly and the second assembly are positioned in separated, layered structures, and the output bus bar is positioned between the layered structures.