Patent ID: 6938252

Claim:
A method for scheduling threads in a multi-processor computer system having an operating system at least one cache, comprising the steps of: storing in a first data structure thread ids for at least some of the threads associated with a context switch performed by the operating system, each of the thread ids uniquely identifying one of the threads; storing in a second data structure a plurality of entries for a plurality of groups of contiguous cache lines, each of the plurality of entries arranged such that a thread id in the first data structure is capable of being associated with at least one of the contiguous cache lines in at least one of the plurality of groups of contiguous cache lines, the thread identified by the thread id having accessed the at least one of the contiguous cache lines in the at least one of the plurality of groups of contiguous cache lines; adding a group to the plurality of groups of contiguous cache lines when a contiguous cache line in the group is accessed by a given thread; removing a group from the plurality of groups of contiguous cache lines when all contiguous cache lines in the group are flushed; mining for patterns in the plurality of entries in the second data structure to locate multiples of a same thread id that repeat with respect to at least two of the plurality of groups of contiguous cache lines; and scheduling on a same processing unit the threads identified by the located multiples of the same thread id and any other threads identified by any other thread ids associated with the at least two of the plurality of groups of contiguous cache lines.