Patent ID: 7937650

Claim:
A maximum likelihood decoder comprising: a branch metric calculator configured to calculate a branch metric; an addition-comparison-selection circuit configured to perform addition, comparison, and selection of an output from the branch metric calculator and a path metric in order to update the path metric, and to output a selection signal for identifying a selection result; a path memory configured to store a time variation of the selection signal; and a path determination module configured to determine a path as a decoding signal based on the time variation of the selection signal stored in the path memory, wherein at least one of the branch metric calculator, the addition-comparison-selection circuit, and the path memory is able to be switched between a radix-2 mode in which an operation is performed at a channel rate frequency and a radix-4 mode in which an operation is performed at a specific frequency lower than the channel rate frequency, the number of operations per a time in the radix-4 mode is twice the number of operations per the time in the radix-2 mode, and the specific frequency is half the channel rate frequency.