Patent ID: 7294936

Claim:
A semiconductor device comprising: a first semiconductor chip including a plurality of memory elements and a second semiconductor chip including a central processing unit (CPU) block stacked, wherein said first semiconductor chip includes a first electrode portion for connecting to an external electrode through wiring, a second electrode portion having micro bumps for connecting said CPU block in said second semiconductor chip to said first electrode portion, and a third electrode portion having micro bumps for providing a data connection from said memory block in said first semiconductor chip to said CPU block in said second semiconductor chip; and said second semiconductor chip includes a fourth electrode portion having micro bumps for connecting to the second electrode portion in said first semiconductor chip, and a fifth electrode portion having micro bumps for connecting to the third electrode portion in said first semiconductor chip, wherein the second electrode portion in said first semiconductor chip and the fourth electrode portion in said second semiconductor chip are arranged in a vicinity of a peripheral portion on each chip and the third electrode portion in said first semiconductor chip and the fifth electrode portion in said second semiconductor chip are arranged in a vicinity of a center portion on each chip.