Patent ID: 8569803

Claim:
An electrical interconnect structure having thin film transistors comprising: a first dielectric containing a plurality of conductors wherein some of said conductors form conducting lines and/or vias, and other conductors form a gate electrode of said thin film transistors; an insulating material atop said gate electrode; a semiconductor having spaced-apart doped source and drain regions with a channel disposed therebetween atop said insulating material, wherein said semiconductor is a polycrystalline semiconductor formed at temperatures below 450° C.; and a second dielectric having a plurality of conductors where some conductors form conducting lines and/or vias, and other conductors form contacts to said source and drain regions of said thin film transistors wherein said electrical interconnect structure includes n-type thin film transistors in one set of interconnect levels and p-type thin film transistors in a second set of interconnect levels, wherein said n-type transistors are formed with CdSe as the semiconductor material and said p-type transistors are formed with polycrystalline Ge as the semiconductor material.