Patent ID: 7900127

Claim:
An apparatus, comprising: an input that receives an LDPC (Low Density Parity Check) coded signal; and an LDPC decoder that employs an LDPC matrix to decode the LDPC coded signal to make an estimate of an information bit encoded therein; and wherein: the LDPC matrix, composed of a plurality of sub-matrices each having a common size, is partitioned into a left hand side matrix and a right hand side matrix; each sub-matrix column of the left hand side matrix includes at least a first predetermined number of all zero-valued sub-matrices; each sub-matrix column of the left hand side matrix includes at most a second predetermined number of CSI (Cyclic Shifted Identity) sub-matrices; and each sub-matrix within the right hand side matrix is an all zero-valued sub-matrix except those sub-matrices identified below in (a) and (b): (a) each sub-matrix located on a diagonal of the right hand side matrix is a CSI (Cyclic Shifted Identity) sub-matrix; and (b) in every row between a second row, which is below and adjacent to a top row, and a bottom row of the right hand side matrix, inclusive, each sub-matrix located on a left hand side of and adjacent to a sub-matrix located on the diagonal of the right hand side matrix is also a CSI sub-matrix.