Patent ID: 8385110

Claim:
A semiconductor memory device comprising: a storage block having a storage region configured to store data, wherein the storage region is enabled to allow data to be written therein if an unlock status is associated with the storage region and disabled to prevent data from being written therein if a lock status is associated with the storage region, when a program command is input; and a controller configured to prevent the lock status from being changed to the unlock status,. wherein the storage block includes: a one time programmable (OTP) register configured to store the data, the storage region being the OTP register; and an OTP lock register configured to store information indicating the lock/unlock status of the OTP register, and wherein the controller includes: an address comparator configured to compare an external input address with an address of the OTP lock register, and output a comparison signal; a program pulse generating unit configured to output a reset pulse and a set pulse in response to the comparison signal; and a read signal generating unit configured to output a read control signal in response to the comparison signal.