Patent ID: 7049797

Claim:
A semiconductor integrated circuit device comprising: a first voltage generating circuit generating a first voltage; a first reference voltage generating circuit to form a first reference voltage by use of an amplifying circuit by receiving the first voltage provided by said first voltage generating circuit and adjusting the voltage gain with a resistance circuit and a switch controlled by a first trimming switch setting signal; a first output buffer which is activated by a first control signal to form an internal voltage corresponding to said first reference voltage; a second reference voltage generating circuit to form a second reference voltage by adjusting the combination of threshold voltages of MOSFETs, using a plurality of MOSFETs and a switch controlled by a second trimming switch setting signal; a second output buffer activated with a second control signal to form an internal voltage corresponding to said second reference voltage; and an internal circuit to receive the internal voltage supplied from said first output buffer or said second output buffer activated by said first control signal and said second control signal, respectively; wherein said internal circuit is set to the active condition by said first control signal when the internal voltage is supplied from said first output buffer and to the standby condition by said second control signal when the internal voltage is supplied from said second output buffer.