Patent ID: 7031422

Claim:
A shift register comprising: a plurality of pulse generation portions for generating a series of pulse signals in response to a level change of inputted clock signals, the plurality of pulse generation portions including a predetermined pulse generation portion which outputs a pulse signal out of the series of pulse signals, an earlier pulse generation portion which outputs a pulse signal out of the series of pulse signals earlier than the predetermined pulse generation portion, and a later pulse generation portion which outputs a pulse signal out of the series of pulse signals later than the predetermined pulse generation portion; a first clock supply circuit for supplying the clock signal to the predetermined pulse generation portion; a second clock supply circuit for supplying the clock signal to the earlier pulse generation portion; a third clock supply circuit for supplying the clock signal to the later pulse generation portion; and a status signal generation circuit for outputting a status signal to both of the second clock supply circuit and the third clock supply circuit via a common output portion, the status signal showing a status that the predetermined pulse generation portion generated a pulse signal out of the series of pulse signals.