Patent ID: 7830694

Claim:
A first memory level comprising a first plurality of memory cells, each of the first plurality of memory cells comprising a vertically oriented p-i-n diode in the form of a pillar, each vertically oriented p-i-n diode comprising a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region; wherein the first plurality of memory cells comprises programmed cells and unprogrammed cells; wherein programmed cells comprise at least half of the first plurality of memory cells, wherein current flowing through the p-i-n diodes of at least 99 percent of the programmed cells when a voltage between about 1.5 volts and about 3.0 volts is applied between the bottom heavily doped p-type region and the top heavily doped n-type region is at least 1.5 microamps, and wherein the first plurality of memory cells includes every memory cell in the first memory level.