Patent ID: 7650554

Claim:
A method for performing a test of a high-speed integrated circuit with at least one functional unit and a built-in self test capability by a low-speed test system, wherein the method comprises the steps of: a) transforming an external clock signal from the low-speed test system into a faster internal clock signal within the high-speed integrated circuit; b) generating a test pattern according to a predetermined scheme; c) applying the test pattern to the functional unit; d) comparing a response from the functional unit with an expected test pattern; e) if the response differs from the expected test pattern, then generating an internal failure signal; f) generating a predetermined number of time slots if several failures occur; g) repeating the test several times if several failures occur, wherein every repetition corresponds with one selected time slot; and h) extending the internal failure signal to a length, which may be recognized by the test system.