Patent ID: 7060556

Claim:
A method of fabricating a multi-capacitor drain extended transistor device comprising: forming isolation structures on a semiconductor substrate; forming n-well regions within a PMOS region and p-well regions within an NMOS region; forming a first dielectric layer over the device; forming a first gate layer on the first dielectric layer; patterning the first dielectric layer and the first gate layer to form first capacitor structures; forming lightly doped n-type drain extension regions within the p-well regions; forming lightly doped p-type drain extension regions within the n-well regions; forming n-type source regions within the p-well regions and n-type drain regions within the lightly doped n-type extension regions; forming p-type source regions within the n-well regions and p-type drain regions within the lightly doped p-type extension regions; forming a second dielectric layer over the device; forming a second gate layer on the second dielectric layer; and patterning the second dielectric layer and the second gate layer to form second capacitor structures.