Patent ID: 7995639

Claim:
A method of controlling the output of a pulse width modulated inverter comprising at least one H-bridge circuit having a first and second switching elements in a first leg of the H-bridge circuit and a third and fourth switching elements in a second leg of the H-bridge circuit, an anti-parallel diode connected across each one of the first, second, third and fourth switching elements, the first and third switching elements connected to a positive bus of the pulse width modulated inverter and the second and fourth switching elements connected to a negative bus of the pulse width modulated inverter, a first load terminal at a common connection between the first and second switching elements and a second load terminal at a common connection between the third and fourth switching elements, each of the first, second, third and fourth switching elements having an allowed switching rate, the output of the inverter connected to a load connected between the first and second load terminals, the load comprising a substantially resistive, single phase load, the method comprising the steps of controlling current to the load by the first and fourth switching elements during the positive half cycle of the output waveform, and controlling current to the load by the second and third switching elements during the negative half cycle of the output waveform, to establish the flow of an ac current through the load, an improvement comprising, turning on the first and fourth switching elements during the positive half cycle while the second and third switching elements are turned off and alternatively pulsing the first switching element off and on for at least one first pulse period, at least once during the positive half cycle while the fourth switching element is turned on, and alternatively pulsing the fourth switching element off and on for at least one second pulse period, at least once during the positive half cycle while the first switching element is turned on, and turning on the second and third switching elements during the negative half cycle while the first and fourth switching elements are turned off and alternatively pulsing the third switching element off and on for at least one third pulse period, at least once during the negative half cycle while the second switching element is turned on, and alternatively pulsing the second switching element off and on for at least one fourth pulse period, at least once during the negative half cycle while the third switching element is turned on.