Patent ID: 7650524

Claim:
A circuit for storing a signal value, said circuit comprising: a clock signal input for receiving a clock signal; a plurality of latches clocked by said clock signal, said plurality of latches comprising at least one storage latch and at least one further latch; at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of said at least one storage latch, said at least one tristateable device being configured to selectively isolate said input of said at least one storage latch in response to a predetermined clock signal value; wherein power supply to said circuit is arranged such that in response to a sleep signal: a voltage difference across at least a portion of said circuit is reduced such that said portion of said circuit is powered down, said portion of said circuit including said at least one further latch; a voltage difference across said at least one storage latch is maintained; and a clock signal received by said tristateable device is held at said predetermined value such that said input of said storage latch is isolated.