Patent ID: 7719813

Claim:
A substrate-triggered ESD protection circuit, comprising: a first resistor; a first transistor, wherein a gate terminal of the first transistor is connected to a power terminal through the first resistor, a source terminal of the first transistor is connected to the power terminal through a second resistor, a drain terminal of the first transistor is connected to a pad, and a bulk terminal of the first transistor is connected to the power terminal directly or through the second resistor, the first transistor is configured for being served as a substrate-biasing circuit without a capacitor formed between the gate terminal and the drain terminal thereof; and a second transistor, wherein a gate terminal of the second transistor is connected to the gate terminal of the first transistor and also connected to the power terminal through the first resistor, source/drain terminals of the second transistor are respectively connected to the power terminal and the pad, a bulk terminal of the second transistor is connected to the source terminal of the first transistor and is also connected to the power terminal through the second resistor, the second transistor is configured for being served as an ESD protection element; when a ESD voltage zaps the pad, a RC constant is maintained based on the first resistor, a first parasitic capacitor between the gate terminal and the drain terminal of the first transistor and a second parasitic capacitor between the gate terminal and the drain terminal of the second transistor for the substrate-triggered effect of the ESD protection circuit.