Patent ID: 8295107

Claim:
A method of operation within an integrated circuit memory device, the method comprising: asserting a plurality of control signals in response to a first transition of a memory access initiation signal to effect a first memory read operation, including asserting a first control signal, a second control signal, a third control signal and a fourth control signal after respective delays relative to the first transition of the memory access initiation signal; storing a first address within a first address register in response to the assertion of the first control signal; transferring the first address from the first address register to a second address register in response to the assertion of the second control signal; providing the first address from the second address register to a memory core to enable the memory core to provide first read data corresponding to the first address; storing the first read data from the memory core within a read register in response to the assertion of the third control signal; and enabling an output driver to output the first read data onto an external signaling path in response to the assertion of the fourth control signal.