Patent ID: 7482268

Claim:
A method for forming an integrated circuit chip, comprising: providing a silicon substrate, multiple MOS devices in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure is connected to said multiple MOS devices, and a passivation layer over said first metallization structure, wherein a first opening in said passivation layer exposes a first contact point of said first metallization structure, and a second opening in said passivation layer exposes a second contact point of said first metallization structure; and forming a second metallization structure on said passivation layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, and wherein said forming said second metallization structure comprises forming a titanium-containing layer, forming a first copper layer on said titanium-containing layer, forming a photoresist layer on said first copper layer, an opening in said photoresist layer exposing said first copper layer, electroplating a second copper layer on said first copper layer exposed by said opening in said photoresist layer, removing said photoresist layer, removing said first copper layer not under said second copper layer, and removing said titanium-containing layer not under said second copper layer by a wet etching process, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said second copper layer is between 0.03 and 2 micrometers.