Patent ID: 8804424

Claim:
A memory comprising: a three transistor memory cell device coupled to a first data line; a plurality of strings of memory cells; a plurality of second data lines, the second data lines of the plurality of second data lines respectively coupled to the strings of memory cells of the plurality of strings of memory cells; sense circuitry coupled between at least one of the plurality of second data lines and the first data line; a first enable/disable transistor coupled between the three transistor memory cell device and the sense circuitry and configured to couple the first data line to the sense circuitry; and a plurality of second enable/disable transistors, each of the plurality of second enable/disable transistors configured to couple a respective one of the plurality of second data lines to the sense circuitry; wherein the plurality of second enable/disable transistors are configured so that all of the plurality of second enable/disable transistors are disabled when the first enable/disable transistor is enabled.