Patent ID: 8145059

Claim:
A topology for a 40 G optical transceiver component having output jitter less than a SONET limit, comprising: an electrical signal interface stage; a data timing and reformatting stage; an optical fiber interface stage; a 40 Gbps serial data line connecting said electrical signal interface stage and said data timing and reformatting stage; a clock line connecting said electrical signal interface stage and said data timing and reformatting stage, wherein said clock line is adapted to carry a clock signal having an amount of clock signal jitter; and a signal line connecting said data timing and reformatting stage and said optical fiber interface stage, wherein said data timing and reformatting stage limits an amount of jitter coupled between said electrical signal interface stage and said optical fiber interface stage to an amount approximately equal to said amount of clock jitter on said clock line, said data timing and reformatting stage comprises a retimer adapted to reduce an amount of jitter in said signal line to an amount of jitter approximately equal to said amount of clock signal jitter, and said retimer is adapted to reduce an amount of jitter greater than the SONET limit on said 40 Gbps serial data line to said amount of jitter approximately equal to said amount of clock signal jitter.