Patent ID: 8359517

Claim:
A memory device, comprising: an array of memory cells; a read data path configured to couple read data from selected memory cells to a plurality of data bus terminals; a write data path configured to couple write data from the plurality of data bus terminals to selected memory cells; refresh circuitry configured to refresh memory cells in the array storing data of a first type at a first rate in a reduced power refresh mode, the refresh circuitry further configured to refresh memory cells in the array storing data of a second type at a second rate that is faster than the first rate in the reduced power refresh mode; control logic configured to cause the write data to be coupled from the data bus terminals to the array of memory cells and to cause the read data to be coupled from the array of memory cells to the data bus terminals; and an error checking and correcting system coupled to the array of memory cells and configured to correct data retention errors that arise in the memory cells storing data of the first type.