Patent ID: 7476983

Claim:
A layout structure of pads formed on a semiconductor device and used for at least one of testing and wire bonding of the semiconductor device, a first subset of the pads being non-wire-bonding pads that are used for testing of the device and not for wire bonding of the device, a second subset of the pads being wire-bonding pads that are used for wire bonding of the device, wherein the non-wire-bonding pads each has a first surface area that is less than a second surface area of each of the wire-bonding pads, wherein at least one of the wire-bonding pads is of a step type, wherein at least one of the step type wire-bonding pads includes a test region used during testing of the semiconductor device and a wire bonding region used during wire bonding of the semiconductor device, wherein the non-wire-bonding pads and the test region of the at least one of the step type wire-bonding pads are positioned on an axis, wherein the wire bonding region has a width in the direction of the axis that is the same as a width of the test region on the axis, and wherein the wire bonding region is offset relative to the test region such that the wire bonding region of the at least one of the step type wire-bonding pads is closer to an adjacent non-wire-bonding pad on the axis than the test region of the at least one of the step type wire-bonding pads on the axis.