Patent ID: 7499341

Claim:
A semiconductor memory device, comprising: a memory cell array configured to generate read data having a plurality of bits; and an output circuit configured to sequentially output the bits of the read data in response to a clock signal in a normal mode, and configured to selectively output the bits of the read data by latching bits to be tested among the bits of the read data and by electrically disconnecting output paths of bits not to be tested among the bits of the read data in response to a plurality of switch control signals in a test mode to expand a valid data window of an output data, wherein the output circuit comprises: a first switching circuit configured to selectively output the bits of the read data in response to a first switch control signal and a second switch control signal; a first selecting circuit configured to selectively latch bits of an output of the first switching circuit to generate first selection data; a second switching circuit configured to selectively output bits of the first selection data in response to a third switch control signal and a fourth switch control signal; and a second selecting circuit configured to selectively latch bits of an output of the second switching circuit to generate second selection data.