Patent ID: 7855110

Claim:
A method, comprising: (a) forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of said gate dielectric layer; (b) forming a source extension ion implanted region and a drain extension ion implanted region in said silicon region of said substrate on opposite sides of said gate electrode and forming a source ion implanted region and a drain ion implanted region in said silicon region of said substrate on opposite sides of said gate electrode, after (b), (c) performing a thermal activation anneal to form, from said ion implanted regions, a source and a drain separated by a channel region under said gate electrode, said source having a source extension extending under said gate electrode and said drain having a drain extension extending under said gate electrode, said source, source extension, drain and drain extension doped a first dopant type; after (c), (d) forming a source delta region contained entirely within said source, a region of said source extension intervening between said source delta region and said channel region and forming a drain delta region contained entirely within said drain, a region of said drain extension intervening between said drain delta region and said channel region, said delta source region and said delta drain region doped a second dopant type, said second dopant type opposite from said first dopant type; and wherein (d) includes: forming first sidewall spacers on sidewalls of said gate electrode and then performing a counter dopant ion implant of said second dopant type into said source and said drain where said source, source extension, drain and drain extension are not protected by said gate electrode and said first sidewall spacers, said counter ion implant extending into said source extension and said drain extension; forming second sidewall spacers on said first sidewall spacers and then performing a counter-counter dopant ion implant of said first dopant type into said source, source extension, drain and drain extension, said counter-counter ion implant extending into said source extension and said drain extension where said source, source extension, drain and drain extension are not protected by said gate electrode and said first sidewall spacers and said second sidewall spacers; and performing a diffusionless activation anneal to activate dopants implanted by said counter and counter-counter dopant ion implants.