Patent ID: 7558938

Claim:
A memory controller for controlling burst mode memory access operations to a memory via an off-chip bus, said memory operating in a burst mode to support burst mode memory access operations having a burst length BL, said memory controller comprising: address mapping logic operable to map an N-bit logical memory address LAi, where N>i≧0, received by said memory controller and specifying a start address of a burst mode memory access of burst length BL, to an M-bit encoded memory address EAj, where M>j≧0, to be output to said memory upon said off-chip bus; wherein said address mapping logic forms said encoded memory address by mapping a portion, LAk, of said logical memory address LAi, where p and X are integers given by p>log 2 BL, X<N, X≧k≧p and BL>1, to a portion of said encoded memory address EAq, such that (i) LAi=EAj for i=j and i<p, and (ii) a sequence of adjacent values for said portion of said logical memory address LAk maps to a sequence of adjacent values for said portion of said encoded memory address EAq having a reduced average Hamming distance therebetween, whereby a burst mode transfer to adjacent logical memory addresses having a common value of said portion of said logical memory address LAk will result in accesses to memory locations in said memory having adjacent encoded memory addresses.