Patent ID: 7412477

Claim:
A phase adjustment circuit, comprising: a delay line, the delay line having taps for providing progressively delayed samples of an input signal; selection circuitry coupled to receive the progressively delayed samples and to receive control signaling to select two samples of the progressively delayed samples; and an interpolator, consisting essentially of passive elements, coupled to receive the two samples selected and configured to provide a phase-adjusted signal, the phase-adjusted signal being an interpolation of the two samples selected, wherein the interpolator comprises: respective impedances coupled together at a common node for outputting the phase-adjusted signal wherein an impedance of the respective impedances is selected from a group consisting of a resistor, an inductor, a capacitor and any combination thereof; independent impedances coupled to respective output nodes for providing respective interpolations of the two samples selected; and a set of impedances coupled to the output nodes and to a common node, the common node for outputting a respective interpolation of the two samples selected.