Patent ID: 7383147

Claim:
A method of parametric testing of semiconductor wafers, comprising: loading a first semiconductor wafer onto a probing machine having a probe head; loading a first map selected from a plurality of map sets, the first map operable for directing a first sequence of prober movements to perform parametric tests at each location in the first map; loading a second map selected from the plurality of map sets, the second map operable for directing a second sequence of prober movements to perform parametric tests at each location in the first map; loading a parametric test defect threshold determined from historical data of testing other wafers; moving the probe head in the first sequence of prober movements specified in the first map; probing test pins with the probe head to perform tests on the wafer at each location in the first probing sequence; recording test results of each test at each respective location; halting the prober when the test results indicate the defect threshold has been exceeded; switching from the first map to the second map; moving the probe head in the second sequence of prober movements specified in the second map; and recording test results of each test at each respective location.