Patent ID: 8729975

Claim:
A circuit for implementing differential resonant clocking with DC blocking comprising: an on-chip inductor; a series connected on-chip capacitor connected to said on-chip inductor; said on-chip inductor together with said on-chip capacitor connected between a pair of differential active clock load nodes forming a resonant tank circuit; said on-chip inductor having a selected value based upon a value of a load capacitor of the differential active clock load nodes to determine a resonant frequency; said on-chip capacitor having a selected value greater than the value of said load capacitor; said on-chip capacitor providing an input and output blocking capacitor at DC to provide a DC testable resonant tank circuit between differential clock inputs and said pair of differential active clock load nodes with said on-chip capacitor providing DC isolation; energy of said resonant tank circuit formed by said on-chip inductor and said on-chip capacitor mitigating supply noise sensitivity; and magnetic coupling between said pair of differential active clock load nodes of a true clock signal to a compliment clock signal mitigating duty cycle distortion in the differential resonant clocking circuit.