Patent ID: 7622313

Claim:
A method of assembling of an electronic device, comprising: testing a first wafer comprising a plurality of first sets of dies to identify the location of functional first sets of dies within the first wafer; dividing the first wafer into a plurality of first sets of multiple-die panels, wherein each panel includes an M×N array of the first die wherein each panel of the first set of multiple-die panels includes a plurality of first sets of dies; categorizing the plurality of first sets of multiple-die panels into a first plurality of bins based on a predetermined yield pattern associated with the first wafer; bonding the first set of multiple-die panels to panel sites of a second wafer to form a panel stack, wherein the panel sites include an M×N array of second sets of dies, wherein bonding includes testing and categorizing the panel sites of the second wafer into a second plurality of bins based on the predetermined yield pattern associated with the first wafer and wherein the bonding step further includes bonding the first set of multiple-die panels to the panel sites of the second wafer selectively to minimize functional mismatches; and sawing the panel stack into a set of electronic devices, each electronic device comprising a first die bonded to a second die.