Patent ID: 8261218

Claim:
A system for determining clock-path delay adjustments, said system comprising: a memory configured to store information; and a processor coupled to said memory and configured to: determine whether a first clock-path delay is adjustable independently of a second clock-path delay, wherein the first clock path delay is associated with a delay of a signal from a clock source to a first storage node, and the second clock path delay is associated with a delay of a signal from the clock source to a second storage node; determine an adjustment to apply to the first clock-path delay to improve data path timing if the first clock-path delay is adjustable independently of the second clock-path delay; and if the first clock-path delay is not adjustable independently of the second clock-path delay, determining a group of storage nodes with clock path delays that are dependent on one another, the group including the first and second storage nodes, and determining an adjustment to apply to a third clock-path delay if the first clock-path delay is not adjustable independently of the second clock-path delay, wherein the third clock path delay is associated with a delay of a signal from the clock source to the group of storage nodes.