Patent ID: 8238184

Claim:
A sense amplifier for sensing data stored in a memory cell of a memory, the sense amplifier comprising: a sensing node; a reference node; a first bias circuit, coupled to the sensing node, enabled in response to an enabled level of a first control signal for biasing the sensing node to a first voltage in response to the first control signal; a second bias circuit, coupled to the reference node, enabled in response to the enabled level of the first control signal for biasing the reference node to the first voltage in response to the first control signal; a third bias circuit, coupled to the sensing node, enabled in response to an enabled level of a second control signal for biasing the sensing node to a second voltage in response to the second control signal; a fourth bias circuit, coupled to the reference node, enabled in response to the enabled level of the second control signal for biasing the reference node to the second voltage in response to the second control signal; a first transmission circuit, coupled to the sensing node, for discharging the sensing node via the memory cell; a second transmission circuit, coupled to the reference node, for discharging the reference node via a reference memory cell; and a latch circuit enabled in response to an enabled level of a third control signal for amplifying a voltage difference between the sensing node and the reference node, wherein the first and second transmission circuits respectively comprise a first transistor having a first source/drain coupled to the sensing node, a second source/drain for receiving the cell current and a gate for receiving an enabled signal; and a second transistor having a first source/drain coupled to the reference node, a second source/drain for receiving the reference current and a gate for receiving the enabled signal, wherein the second voltage biases the first and second transistors to operate in saturation regions.