Patent ID: 7418780

Claim:
A method for forming stacked via-holes in a multilayer printed circuit board, comprising the steps of: providing a base circuit board having conductive traces; attaching a first copper-coated-substrate having a first substrate and a first copper layer thereon and a second copper-coated-substrate having a second substrate and a second copper layer thereon onto the base circuit board in a manner such that the first substrate is brought into contact with the base circuit board and the second substrate is brought into contact with the first copper layer; forming at least one first window in the second copper layer thereby yielding a residual second copper layer; forming a protective layer on the residual second copper layer; making at least one first hole in the second substrate through the at least one first window using a first laser treatment; forming at least one second window in the first copper layer through the at least first hole; removing the protective layer; making at least one second hole in the first substrate through the at least one second window using a second laser treatment, thus allowing the at least first window, the at least first hole, the at least second window and the at least second hole to cooperatively form at least one part-finished stacked via-hole; and plating a metal layer on an inner surface of the at least one part-finished stacked via-hole thereby forming at least one stacked via-hole.