Patent ID: 7875499

Claim:
A manufacturing method of an electronic apparatus comprising a plurality of semiconductor apparatuses, a wiring substrate on which the plurality of semiconductor apparatuses are stacked, and a sealing resin with which the plurality of semiconductor apparatuses stacked on the wiring substrate are sealed, comprising: a semiconductor apparatus formation step of forming the plurality of semiconductor apparatuses; a good item semiconductor apparatus acquisition step of making an action check of the plurality of semiconductor apparatuses and acquiring a plurality of semiconductor apparatuses judged as good items; a semiconductor apparatus stacking step of stepwise stacking the plurality of semiconductor apparatuses judged as the good items on the wiring substrate; an electrical connection step of making electrical connection between the wiring substrate and the plurality of semiconductor apparatuses judged as the good items after the semiconductor apparatus stacking step; and a sealing resin formation step of sealing the plurality of semiconductor apparatuses judged as the good items with the sealing resin after the electrical connection step, wherein the semiconductor apparatus formation step includes a step of forming semiconductor chips having electrode pads on semiconductor apparatus formation regions of a semiconductor substrate, a step of forming internal connection terminals on the electrode pads, a step of forming a resin layer on the semiconductor substrate so as to cover the internal connection terminals, a step of forming a metal layer on the resin layer, a step of pressing the metal layer to compress the resin layer and to deform the internal connection terminals so that an upper surface of the resin layer is substantially flush with and exposes upper surfaces of the internal connection terminals, a step of crimping the metal layer on the internal connection terminals by heating, and a step of forming a wiring pattern having a connection part, to which a metal wire is connected, and an inspection pad for making an action check of the semiconductor apparatus, the inspection pad placed in a position spaced from the connection part, and a dummy pattern at the same time by patterning the metal layer by etching after crimping.