Patent ID: 8053322

Claim:
A method of fabricating an integrated circuit device including a plurality of Metal Oxide Semiconductor (MOS) transistors, comprising: providing a substrate having a silicon comprising surface; forming a plurality of dielectric filled trench isolation regions in said substrate, wherein said silicon comprising surface forms trench isolation active area edges along its periphery with said trench isolation regions; depositing an epitaxial silicon comprising layer, said epitaxial comprising silicon layer being deposited over said silicon comprising surface and including depositing silicon extending laterally for a distance over at least one of said trench isolation active area edges onto at least one of said trench isolation regions; oxidizing said epitaxial comprising silicon layer to convert at least a thickness portion of said epitaxial comprising silicon layer into a thermally grown silicon oxide layer, wherein said thermally grown silicon oxide layer extends laterally over said at least one of said trench isolation active area edges and provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors; and forming a patterned gate electrode layer over said at least said portion of said gate dielectric layer, wherein said patterned gate electrode layer extends laterally over said at least one of said trench isolation active area edges.