Patent ID: 8564061

Claim:
A power semiconductor device comprising: a semiconductor substrate having a first isolation layer on a surface thereof, and first and second metallization regions on a surface of said first isolation layer, said first and second metallization regions contacting first and second doped regions through first and second plugs, respectively, and comprising Al, AlSi, AlSiCu or Cu, the semiconductor substrate comprising a trench and a doped semiconductor zone, the trench and the doped semiconductor zone each being provided in said semiconductor substrate below said first isolation layer and between said first and second doped regions, a conductive layer of polysilicon formed within said trench between said first and second doped regions, said conductive layer of polysilicon being electrically isolated from the semiconductor substrate by a second isolation layer, said second isolation layer being provided between said doped semiconductor zone and said conductive layer of polysilicon, and at least one elongate plug structure extending vertically from said conductive layer of polysilicon through said first isolation layer which cover the surface of the semiconductor substrate to a level of the surface of said first isolation layer, extending in a direction laterally from said conductive layer of polysilicon through said second isolation layer to said doped semiconductor zone as an electrical line which carries a lateral current flow within the semiconductor device between the doped semiconductor zone and the conductive layer of polysilicon in the trench, wherein the at least one elongate plug structure comprises a continuous laterally oriented trench filled with polysilicon or tungsten making contact with the doped semiconductor zone, said continuous laterally oriented trench reaching from the level of the surface of said first isolation layer into said conductive layer of polysilicon and into said doped semiconductor zone.