Patent ID: 7045453

Claim:
An etch back and gap fill method for fabricating an interconnect structure in an integrated circuit comprising the steps of: a) Depositing a support dielectric on a supporting surface; b) Forming a set of interconnect apertures in said support dielectric, at least some of which apertures have a lower surface separated by a vertical distance from said supporting surface; c) Forming a set of wiring features by filling said set of interconnect apertures with an electrically conductive interconnect material and planarizing such that the top surface of said wiring features are substantially coplanar with the top surface of said support dielectric, whereby at least some of said wiring features are supported by a supporting portion of said support dielectric below said lower surface; d) Etching said support dielectric with a directional etch using said wiring features as a mask, such that the support dielectric is only left in the structure in said supporting portions underneath said wiring features; e) depositing a gap fill dielectric material over said set of wiring features such that the gaps between said set of wiring features are filled with said gap fill dielectric; and f) Planarizing said gap fill dielectric until the top surface of said set of wiring features is substantially coplanar with the top surface of said gap fill dielectric.