Patent ID: 8205181

Claim:
A circuit analysis tool, enabled with software instructions stored in a non-transitory computer-readable medium and executed by a processor, for minimizing circuit crosstalk, the instructions comprising: providing a first circuit connected to an output node having a last gate with a plurality of inputs and an output; calculating a first circuit victim net delay range having a minimum delay (Vmin) and a maximum delay (Vmax); providing a second circuit having an output connected to the output node to supply an aggressor net delay range (A 1 ) having a minimum delay (A 1 min ) and a maximum delay (A 1 max ), where the aggressor net delay range at least partially overlaps the victim net delay range; without increasing the value of Vmax, shrinking the first circuit victim net delay range; and, minimizing crosstalk between the first and second circuits without an increase in first circuit maximum signal delay.