Patent ID: 8266417

Claim:
A digital processing device, comprising: n processors, n being a natural number of 2 or greater, the n processors including a main processor, and n-1 application processors, wherein each of the n-1 application processors is coupled to the main processor through an independent control bus and performs an operation according to a control signal inputted through the control bus from the main processor; and a shared memory, coupled to each of the n processors through independent buses and having a boot section allotted, the boot section being for writing a boot program code to be used for booting of at least one processor, wherein the shared memory further comprises: n access ports, providing an access path for each of the n processors; m dedicated sections, each of which is pre-allotted to be accessible by a predetermined processor only, m being a natural number of 2 or greater; at least one common section, independently accessible and usable by the n processors during a different period of time; and an internal controller, generating access status information related to whether a processor of the n processors is accessing the common section and outputting the access status information to a corresponding processor, and wherein a processor writes the boot program code in the common section, and then another processor corresponding to the boot program code reads the boot program code from the commons section and then writes the written boot program code in the boot section.