Patent ID: 7982219

Claim:
A pixel array, comprising: a plurality of scan lines; a plurality of data lines intersecting the scan lines; a plurality of pixels connected to the scan lines and the data lines, each of the pixels arranged in an n th row comprising: a first sub-pixel comprising a first transistor and a first pixel electrode, wherein a first gate of the first transistor is connected to an (n−1) th scan line, and a first drain of the first transistor is connected to the first pixel electrode a second sub-pixel comprising a second transistor and a second pixel electrode, wherein a second gate of the second transistor is connected to an n th scan line, and a second drain of the second transistor is connected to the second pixel electrode and a first source of the first transistor; and a third sub-pixel comprising a third transistor and a third pixel electrode, wherein a third gate of the third transistor is connected to an (n+1) th scan line, a third drain of the third transistor is connected to the third pixel electrode and a second source of the second transistor, and a third source of the third transistor is connected to one of the data lines.