Patent ID: 7187591

Claim:
A memory device including a coupled controller for controlling writing to, reading from and erasure of the memory array, the memory device comprising: a plurality of electrically erasable odd memory sub-blocks and a corresponding plurality of electrically erasable even memory sub-blocks, the odd memory sub-blocks and even memory sub-blocks being logically paired to form memory blocks within the memory array, each of the odd memory sub-blocks and even memory sub-blocks including odd memory wordlines and even memory wordlines, respectively; and the controller including an odd wordline erase voltage and an even wordline erase voltage, the odd wordline erase voltage and the even wordline erase voltage being separately settable and separately adjustable with respect to each other and a function to determine odd/even wordline erasure offset, the controller being operable responsive to determination of odd/even wordline erasure offset to adjust one or both of the odd wordline erase voltage and the even wordline erase voltage to affect a change in the odd/even wordline erasure offset.