Patent ID: 7982511

Claim:
A delay locked loop (DLL) circuit comprising: a phase conversion control unit configured to receive a phase comparison signal, to latch an initial value of the phase comparison signal, to output the latched signal as a phase conversion control signal; a phase converting unit having one input terminal, configured to receive a delay clock through the input terminal and to output the delay clock as a controlled delay clock when a phase of a feedback clock leads a phase of a reference clock or to invert and output the delay clock as the controlled delay clock when the phase of the reference clock leads the phase of the feedback clock, in response to the phase conversion control signal; a delay compensating unit configured to delay the controlled delay clock and generate a feedback clock in order to compensate for the delay time given by delay elements provided on a transmission path of the delay clock to a data output buffer; a clock buffer configured to convert an amplitude of an external clock to generate the reference clock; a delay unit configured to delay the reference clock in a push or pull manner in response to input of a delay control signal to generate the delay clock; a phase comparing unit configured to compare the reference clock with the feedback clock to generate the phase comparison signal; and a delay control unit configured to generate the delay control signal in response to the phase comparison signal, wherein the phase comparison signal includes information about a phase difference between a reference clock and the feedback clock.