Patent ID: 7450530

Claim:
A cross link multiplexer bus, comprising: a plurality of cross link multiplexers, said plurality of cross link multiplexers having a destination port configured to receive a signal and an origin port configured to produce said signal; and a plurality of interconnects, wherein a set of interconnects of said plurality of interconnects is coupled between a pair of adjacent cross link multiplexers of said plurality of cross link multiplexers; wherein: said signal is configured to be represented as a series of characters, and a character of said series of characters is configured to be represented as a first data bit, a second data bit, and a first control bit; a first interconnect of said set of interconnects is configured to convey said first data bit, a second interconnect of said set of interconnects is configured to convey said second data bit, and a third interconnect of said set of interconnects is configured to convey said first control bit; said first interconnect, said second interconnect, and said third interconnect are configured in a manner to reduce cross-talk; said third interconnect is positioned substantially between said first interconnect and said second interconnect; said series of characters is further configured to be represented as a third data bit, a fourth data bit, and a second control bit; a fourth interconnect of said set of interconnects is configured to convey said third data bit, a fifth interconnect of said set of interconnects is configured to convey said fourth data bit, and a sixth interconnect of said set of interconnects is configured to convey said second control bit; and said sixth interconnect is positioned substantially between said fourth interconnect and said fifth interconnect.