Patent ID: 7821309

Claim:
A delay locked loop circuit comprising: a first delay line configured to delay a received external clock signal for a fine delay time and then output a first internal clock signal a second delay line configured to delay a second clock signal for a coarse delay time and then output a second internal clock signal; and a phase detection and control unit configured to detect a difference between the phases of the external clock signal and the second internal clock signal, and to control the fine delay time and the coarse delay time, wherein the first delay line and the second delay line are sequentially arranged, and the second clock signal is generated using the first internal clock signal, wherein a type of a delay cell of the first delay line is different from a type of a delay cell of the second delay line, wherein the type of delay cell is defined by an amount of delay time produced by the delay cell, and wherein the first delay line comprises: a first delay circuit including n delay cells connected in series; and a phase mixer configured to select at least one of the external clock signal and first through nth finely delayed signals and then output a signal generated by using the selected signal as the first internal clock signal, in response to information regarding the detected phase difference and an output of the phase detection and control unit.