Patent ID: 6914825

Claim:
An electrically programmable logic device, comprising: a P substrate; an N well formed in the P substrate; a PMOS select transistor formed on the N well, wherein the PMOS select transistor comprises a select gate biased to a word line voltage, a first P + source region biased to a source line voltage, and a first P + drain region; and a PMOS floating gate transistor formed on the N well and being serially electrically connected to the PMOS select transistor, wherein the PMOS floating gate transistor comprises a P type doped floating gate that does not capacitively couple to any control gate over or under the P type doped floating gate, a second P + source region electrically connected to the first P + drain region of the PMOS select transistor, and a second P + drain region biased to a bit line voltage, and wherein the second P + source region and the second P + drain region define a floating gate P-channel.