Patent ID: 8639863

Claim:
A memory apparatus comprising: a baseboard printed circuit board including a host edge connector adapted to couple the baseboard to a host system; a master controller including a host bus channel coupled to the host edge connector and a plurality of memory bus channels; a plurality of slave controllers coupled to the master controller, the plurality of slave controllers adapted to provide transparent access to non-volatile memory; a first plurality of daughter-card sockets respectively coupled to the plurality of memory bus channels, the first plurality of sockets adapted to receive a plurality of daughter-memory-cards; one or more first replaceable daughter-memory-cards removeably plugged into the first plurality of daughter-card sockets, each of the first replaceable daughter-memory-cards including a plurality of packaged non-volatile memory mounted to the replaceable daughter-memory-card; and a non-volatile card configuration device coupled to the master controller; and wherein the master controller natively controls the non-volatile memory to obtain predictable bandwidth and latency performance with the non-volatile memory mounted to the replaceable daughter-memory-cards.