Patent ID: 7906976

Claim:
A switched capacitor measurement circuit for measuring the capacitance of an input capacitor (CIN) with a parallel parasitic resistor (RPAR), comprising: a switching arrangement (S 1 , S 2 . . . S 5 ), a reference capacitor (CREF); a steered current sink (IDAC) and an operational amplifier (OP) with an output; a non-inverting input connected to a reference voltage source (VREF) and an inverting input connected to a first terminal of the input capacitor (CIN), said switching arrangement selectively connecting: in a reset mode, a second terminal of said input capacitor (CIN) with the reference voltage source (VREF), the inverting input of the operational amplifier (OP) with the output of the operational amplifier, and the reference capacitor (CREF) between the reference voltage source (VREF) and the inverting input of the operational amplifier (OP); in a gain mode, the second terminal of said input capacitor (CIN) with a supply voltage (VDD), the reference capacitor (CREF) between the inverting input and the output of the operational amplifier (OP), and the steered current sink (IDAC) with an interconnection node between the input capacitor (CIN) and the reference capacitor (CREF); wherein the current sink (IDAC) is steered by a control loop to compensate for a charge current due to the parasitic resistor (RPAR).