Patent ID: 8138020

Claim:
A method of producing wafer level interconnect decals, said method comprising the steps of: (a) providing a plurality of superimposed apertured decals, said plurality of decals including an upper layer having tapered feature holes, a center layer having through features holes in alignment with said tapered feature holes in alignment with the through feature holes in a bottom layer located on an opposite side of said center layer; (b) forming vacuum holes in said center layer in alignment with vacuum holes in said bottom layer arranged about the peripheries of said layers for maintaining said layers in aligned relationship; (c) positioning a carrier beneath said bottom layer, said carrier having vacuum holes located in alignment with the vacuum holes in said bottom and center layers; (d) imparting a vacuum to said vacuum holes to maintain said carrier and decal layers in a clamped position; (e) filling the feature holes in said decal layers with molten solder and cooling said solder; (f) peeling said upper layer from said center layer and applying an adhesive layer to the exposed surface of said center layer encompassing projecting solder portions; and (g) mounting a wafer on said exposed surface in contact with said adhesive and solder portions.