Patent ID: 8225174

Claim:
A message-passing decoding device for decoding quasi cyclic low-density parity-check codes having a parity-check matrix that includes a same-size cyclic permutation matrix or zero matrix as a block, with decoding parallel processing degree S within the block, the device comprising: a reception value aligning device which keeps reception value data received from communication paths of equal to or less than S-number from a head of the block, adds (S−(Z mod S))-number pieces of data from the head of the block to an end of the reception value data of the block to be a multiple of S when size Z of the block is not a multiple of S, and writes the obtained data to a reception value memory; a column processing module configured with S-number of column processing devices for generating messages by performing column processing of the message-passing decoding; a row processing module configured with S-number of row processing devices for generating messages by performing row processing of the message-passing decoding; a message memory which stores the messages, and inputs/outputs S-number of messages as one record; and a message aligning device which performs cyclic permutation corresponding to an offset value of the block in a unit of the record between the message memory and the column processing module or the row processing module, adds (S−(Z mod S))-number of messages from the head of an output of the block to an end of an output message of the block to be a multiple of S when Z is not a multiple of S, and outputs the output message to the message memory.