Patent ID: 7921321

Claim:
A circuit for automatically aligning a clock signal relative to a data signal comprising: at least one data terminal for receiving at least one digital data signal, the at least one digital data signal having a data cycle, wherein one transition per data cycle may occur; at least one clock terminal for receiving an input clock; a transition detector circuit connected to the at least one data terminal, the transition detector circuit being configured to provide a transition detect signal in response to a data signal received at the at least one data terminal transitioning states; a clock shifting circuit connected to the transition detector circuit, the clock shifting circuit being configured to generate a register load clock signal having a period equal to a period of the input clock, a triggering edge of the register load clock signal occurring some time after receiving the transition detect signal but before an end of a data cycle in which the transition occurred; and at least one input register clocked by the register load clock signal, wherein an input of the at least one input register is connected to the at least one data terminal, such that the at least one input register is clocked to store a data signal after the transition detect signal has been generated.