Patent ID: 7700948

Claim:
A thin film transistor array panel comprising: an insulating substrate; a gate wire formed on the insulating substrate and including a plurality of gate lines and a plurality of gate electrodes; a storage electrode wire formed on the insulating substrate and including a plurality of storage electrode lines and a plurality of storage electrodes; a gate insulating layer formed on the gate wire; a semiconductor layer formed on the gate insulating layer; a data wire formed on the gate insulating layer and including a plurality of data lines insulated from and crossing over the gate lines, a plurality of source electrodes contacting the semiconductor layer at least in part, a plurality of drain electrodes facing the source electrodes and contacting the semiconductor layer at least in part; a passivation layer formed on the data wire; a plurality of pixel electrodes formed on the passivation layer and electrically connected to the drain electrodes; an active area for displaying images and comprising the plurality of pixel electrodes, a portion of the gate wire, a portion of the storage wire and a portion of the data wire; a peripheral area surrounding the active area; a first common bar electrically connected to a plurality of storage wire and formed in a first portion of the peripheral area; and a second common bar electrically connected to the plurality of stroage wire and formed in a second portion of the peripheral area, wherein the widths of the first and second common bars are different, and the first and second portions of the peripheral areas are on opposite sides of the active area.