Patent ID: 8188514

Claim:
A transistor, comprising: a p-type region; a channel region being in direct contact with an upper surface of the p-type region, wherein the channel region is n-type or i-type and comprises a first channel region and a second channel region; a barrier region forming a hetero-junction with an upper surface of the first channel region; an insulation film being in direct contact with an upper surface of the second channel region and an upper surface of the barrier region; a gate electrode facing the second channel region and the barrier region via the insulation film; a drift region being in direct contact with one end of the channel region, wherein the drift region is n-type; and a source region being in direct contact with other end of the channel region, wherein the source region is n-type and the density of the n-type impurities in the source region is higher than that of the channel region, wherein the first channel region and the second channel region are arranged in series in a current pathway between the drift region and the source region.