Patent ID: 7643368

Claim:
A power control circuit providing power to an output terminal supplying a logic block within a semiconductor integrated circuit, and comprising: a power gating circuit providing a main power voltage to the output terminal during a normal operating mode and providing a retention voltage to the output terminal during a data retention mode characterized by the absence of the main power voltage from the logic block, wherein the retention voltage is minimally sufficient to retain data stored in the logic block during the data retention mode; a data retention circuit generating the retention voltage and applying the retention voltage to the output terminal; and a controller responsive to an externally provided command to control operation of the power gating circuit and the data retention circuit, wherein the controller generates a first control signal applied to the power gating circuit and a second control signal applied to the data retention circuit, such that in response to the first control signal the power gating circuit passes an externally provided main power voltage to the output terminal during the normal operating mode, and in response to the second control signal the data retention circuit generates and provides the retention voltage to the output terminal during the data retention mode.