Patent ID: 8892821

Claim:
A data processing system, comprising: a system memory; an interconnect; a plurality of processing cores that initiate memory access requests on the interconnect; a plurality of a cache memories, each coupled to a respective one of the plurality of processing cores and to the interconnect, wherein the plurality of cache memories temporarily hold cache lines of data identified by addresses of storage locations in the system memory and certain of the plurality of cache memories service memory access requests received via the interconnect that target those addresses; a memory controller, coupled to said interconnect and to the system memory, that controls access to the system memory; response logic that, responsive to receipt of a plurality of coherence responses from the cache memories and the memory controller to a memory access request of one of the plurality of plurality of processing cores broadcast via the interconnect, generates and broadcasts to the plurality of cache memories and to the memory controller a coherency message that designates the system memory or one of the plurality of cache memories as responsible for servicing the memory access request; and a memory speculation mechanism disposed within the memory controller that indicates whether or not the memory controller is to perform speculative access to the system memory based upon historical information regarding whether prior memory access requests were serviced by the memory controller accessing the system memory or by the plurality of cache memories accessing their cache lines; wherein said memory controller, responsive to receipt of the memory access request via the interconnect, said memory access request specifying a target system memory address: responsive to speculative access being indicated by the memory speculation mechanism for the memory access request, speculatively initiates access to the system memory to service the memory access request in advance of receipt by the memory controller of the coherency message from the response logic indicating whether or not said memory access request is to be serviced by the memory controller accessing said system memory; and responsive to speculative access not being indicated by the memory speculation mechanism for the memory access request, initiates non-speculative access to the system memory to service the memory access request only in response to the coherency message from the response logic designating the memory controller as responsible for servicing the memory access request by accessing the system memory.