Patent ID: 7611945

Claim:
A method for forming a capacitor structure for a dynamic random access memory device, the method comprising: forming a device layer overlying a semiconductor substrate; forming a first interlayer dielectric overlying the device layer; forming a via structure within the first interlayer dielectric layer; forming a first oxide layer overlying the first interlayer dielectric layer; forming a stop layer overlying the first oxide layer; forming a second oxide layer overlying the first stop layer; forming a trench region through a portion of the second oxide layer, through a portion of the stop layer, and a portion of the first oxide layer; forming a bottom electrode structure to line the trench region, the bottom electrode structure including an inner region, the bottom electrode structure being coupled to the via structure; protecting the bottom electrode structure with a masking layer, the masking layer filling an entirety of the trench region and overlying the second oxide layer; selectively removing the second oxide layer to the stop layer, the stop layer acting as an etch stop, to expose an outer region of the bottom electrode structure, while maintaining the masking layer within the trench region; forming a capacitor dielectric layer overlying the outer region of the bottom electrode structure and overlying the inner region of the bottom electrode structure; and forming an upper capacitor plate overlying the capacitor dielectric layer to form a capacitor structure.