Patent ID: 8269938

Claim:
A method of fabricating a fringe field switching mode liquid crystal display device comprising: forming a common electrode material and a gate metal on a board in sequence; etching the common electrode material and the gate metal at the same time through a first mask process; forming a gate insulating layer, an active layer and a source/drain metal on the board in sequence; forming a channel in a thin-film transistor (TFT) part, exposing a part of the common electrode material to form an opening by etching a part of the gate metal in a pixel area part through a diffraction exposure, exposing the common electrode material by etching the gate insulating layer, the active layer and the source/drain metal in a gate pad part, and forming a data pad part stacked by the active layer and the source/drain metal by performing a second mask process using a diffraction mask, wherein the gate metal remaining on the common electrode material in the pixel area part operates as a common signal line, and the source/drain metal, the active layer and the gate insulating layer remain on the common signal line, wherein widths of the source/drain metal, the active layer and the gate insulating layer are less than a width of the common signal line; forming a passivation layer on substantially an entire surface of the board, and forming a contact hole on a drain electrode of the TFT part, etching predetermined regions of the source/drain metal and the active layer on the common signal line at a center of the pixel area part to form a floating source/drain metal and opening the gate pad part and the data pad part through a third mask process; forming a pixel electrode metal over the board; and forming a pixel electrode on a predetermined region contacting the drain electrode in the TFT part and a predetermined region having the opening in the pixel area part, a pixel electrode metal pattern contacted to the opened regions of the gate pad part and the data pad part by etching the pixel electrode metal through a fourth mask process, wherein a portion of a gate metal formed on the TFT part operates as a gate line and a gate electrode, and a portion of the gate metal of the gate pad part operates as a bottom electrode of a gate pad, wherein the common electrode material is disposed at the whole region of the pixel area, wherein the gate metal remaining on the common electrode material is located at the center of the pixel area and is paralleled to the gate line, and wherein the center of the etched pixel area part is connected to the floating source/drain metal by depositing the pixel electrode.