Patent ID: 7733168

Claim:
A fully differential comparator comprising: a first to a fourth sampling switch which receive a switch control signal indicating a reset period and a comparison period and are in a conduction state during the reset period, wherein the reset period and the comparison period do not overlap each other; a first to a fourth sampling capacitance to one ends of which a first to a fourth input voltage are separately applied via the first to fourth sampling switches, respectively, during the reset period; a differential amplifier having a first input terminal to which the other ends of any two of the first to fourth sampling capacitances are connected in common, and a second input terminal to which the other ends of the other two sampling capacitances are connected in common; a first charge redistribution switch which causes, during the comparison period, one end connected to any of the first to fourth sampling switches of one of the two sampling capacitances connected to the first input terminal and one end connected to any of the first to fourth sampling switches of one of the two sampling capacitances connected to the second input terminal, to be in a conduction state; and a second charge redistribution switch which causes, during the comparison period, one end connected to any of the first to fourth sampling switches of the other of the two sampling capacitances connected to the first input terminal and one end connected to any of the first to fourth sampling switches of the other of the two sampling capacitances connected to the second input terminal, to be in a conduction state, wherein the differential amplifier outputs, during the comparison period, a first output signal and a second output signal, depending on a difference between a voltage level of the first input terminal of the differential amplifier and a voltage level of the second input terminal of the differential amplifier.