Patent ID: 8176254

Claim:
A method of data processing in a processing system that includes a processor core, an upper level cache memory, a lower level cache memory, and a memory storage, the method comprising: in response to the processor core executing a data cache block touch (DCBT) instruction, identifying a cache block that may be accessed; and in response to the DCBT instruction: determining an effective address in memory storage that contains the cache block; determining from a code value of a cache block hint included within the DCBT instruction one of (a) that a program may soon access the cache block addressed in the DCBT instruction and (b) that the program may soon access only a portion of the cache block addressed by the DCBT instruction; and prefetching the entire cache block to an entry in the lower level cache memory in response to the code value being a first value identifying that the program may soon access the cache block.