Patent ID: 8307265

Claim:
A system comprising: a backplane comprising at least two lanes, wherein each lane comprises at least two pairs of differential traces on a printed circuit board and a connector coupled to transmit signals to each of the pairs, wherein each of the lanes is to transmit electrical signals, wherein electrical characteristics of each of the lanes is to comply in part with clause 72 of IEEE 802.3ap (2007); at least two receivers; at least two transmitters; and logic to form a signal, wherein to form a signal, the logic is to combine contents of signals received by the receivers from the lanes, wherein each of the at least two transmitters is associated with a receiver, the backplane is to communicatively couple a transmitter to an associated receiver using a lane, each transmitter is to transmit signals to an associated receiver, each transmitter comprises: forward error correction (FEC) encoder logic to encode signals with forward error correction, and FEC decoder logic to decode received signals and to indicate error more often than every eighth sync bit, and an aggregate transmission rate of the signals transmitted over the multiple lanes is approximately a number of lanes times a transmission rate of 10GBASE-KR in IEEE 802.3ap (2007).