Patent ID: 7266664

Claim:
A memory device, comprising: a nonvolatile memory connected to a first memory bus and capable of storing data received thereby through said first memory bus; a volatile memory connected to a second memory bus and capable of being random-accessed through said second memory bus; and a controller having a first internal terminal connected to said first memory bus, a second internal terminal connected to said second memory bus, and an external terminal connected to an external bus, said controller transferring data between said nonvolatile memory and said volatile memory through said first and second internal terminals, said controller including a register capable of storing a source address, a destination address, and a size of data to be transferred, wherein; when the data transfer is not performed, said controller controls to access from an exterior to said volatile memory through said external terminal and said second internal terminal, in accordance with an instruction through said external bus, and said controller performs error detection and/or correction processing in said data transfer.