Patent ID: 7647485

Claim:
A data processing system for debugging at least one of operation description source code and object code that cause, for each operating cycle, successive transitions of operation states of a plurality of stages of a parallel arithmetic device, said parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix, and said parallel arithmetic device having a function to temporarily halt said state transitions; said data processing system comprising: an operation execution means for causing said parallel arithmetic device to execute said state transitions in accordance with said object code; a device halt means for temporarily halting said state transitions for each of said operating cycle of said parallel arithmetic device; a result output means for supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted; a resume input means for supplying as input a command to resume said state transitions; and an operation resumption means for causing said operation execution means to resume said state transitions upon the input of said resume command.