Patent ID: 8688879

Claim:
A processing device, comprising: a first processor associated with a RISC instruction set, the first processor including an instruction decode stage for decoding instructions that are extensions of the RISC instruction set; a second processor comprising a plurality of macro functions, the second processor receiving the decoded instructions from the instruction decode stage of the first processor, wherein the macro functions of the second processor are controlled by the decoded instructions; a memory array having a plurality of memory banks adapted to store data; and a memory interface, said memory interface having a plurality of first ports adapted for data communication with said memory array, and a plurality of second ports adapted for data communication with said macro functions of said second processor; wherein the macro functions of the second processor access the data stored in the memory array via the memory interface responsive to receiving the instructions decoded in the instruction decode stage of the first processor, at least two of the macro functions accessing a same memory bank of the plurality of memory banks via a respective first port associated with the same memory bank and respective second ports associated with the at least two macro functions.