Patent ID: 7425477

Claim:
A manufacturing method of a thin film transistor, comprising: forming a buffer layer on a substrate; forming a first poly-silicon island and a second poly-silicon island on the buffer layer; forming a gate-insulating layer on the substrate, the gate-insulating layer covering the first poly-silicon island and the second poly-silicon island; forming a first gate on the gate-insulating layer which is above the first poly-silicon island and a second gate on the gate-insulating layer which is above the second poly-silicon island; forming a sacrificed layer on the substrate, the sacrificed layer covering the first gate and the second gate; forming a photo-resist layer on the sacrificed layer which is above the second poly-silicon island; removing the sacrificed layer which is above the first poly-silicon island by using the photo-resist layer as a mask; performing a first ion implantation process for forming a first source/drain within the first poly-silicon island below two sides of the first gate, and wherein, a first channel region is formed between the first source/drain; performing a second ion implantation process for forming a second source/drain within the second poly-silicon island below two sides of the second gate, and wherein, a second channel region is formed between the second source/drain, and simultaneously, the second ion implantation process is performed to implant ions into the buffer layer below two sides of the first gate; removing the sacrificed layer; and performing a lightly-doped ion implantation process for forming a lightly doped drain between the second source/drain and the second channel region.