Patent ID: 8461034

Claim:
A method comprising: providing a semiconductor substrate having a gate region and a non-active region defined therein; depositing a first gate layer on the semiconductor substrate, the first gate layer substantially covering the gate region and the non-active region; implanting a stress-inducing material into only the gate region and portions of the first gate layer on the gate region following the depositing the first gate layer, wherein the implanting forms a stress including gate layer substantially on the gate region; depositing a second gate layer on the semiconductor substrate after the implanting the stress-inducing material; annealing the semiconductor substrate after the depositing of the second gate layer, wherein the annealing creates a stress in the gate region; and forming a gate structure including a gate electrode, the gate structure formed directly above the gate region and including the first gate layer and the second gate layer, wherein the forming the gate structure includes etching the first gate layer and the second gate layer after the implanting the stress-inducing material.