Patent ID: 7596013

Claim:
A semiconductor integrated circuit comprising: a CMOS embedded SRAM included inside a chip; memory cells of the CMOS embedded SRAM, each having a pair of driver NMOSs, a pair of load PMOSs, and a pair of transfer NMOSs; a embedded SRAM control switch which supplies a PMOS body bias voltage and an NMOS body bias voltage to N wells for a plurality of PMOSs of the CMOS embedded SRAM and P wells for a plurality of NMOSs thereof in any active mode of at least an information holding operation, a write operation and a read operation respectively; and embedded SRAM control memories which store embedded SRAM control information indicative of whether the PMOS body bias voltage and the NMOS body bias voltage are respectively supplied to the N wells for the PMOSs of the CMOS embedded SRAM and the P wells for the NMOSs thereof through the embedded SRAM control switch.