Patent ID: 8427351

Claim:
A digital-to-analog conversion device comprising: a variable delay buffer circuit receiving a digital signal to be converted containing a plurality of bits ordered from MSB (Most Significant Bit) to LSB (Least Significant Bit), said variable delay buffer circuit outputting for each bit a first complementary digital signal set, said first complementary digital signal sets for the bits being delayed one with respect to the other according to the order thereof between the MSB and LSB; a plurality of synchronization circuits respectively receiving said first complementary digital signal sets and a clock signal, using said clock signal as a timing reference of said first complementary digital signal sets, and outputting a plurality of variably delayed second complementary digital signal sets corresponding to said first complementary digital signal sets; and a digital-to-analog conversion unit receiving said second complementary digital signal sets and converting said second complementary digital sets into an analog signal.