Patent ID: 7411809

Claim:
A ferroelectric memory comprising: a block in which a plurality of unit cells each formed by connecting two electrodes of a ferroelectric capacitor to a source and drain of a first MOS transistor are connected in series; word lines each connected to a gate of the first MOS transistor; a word line driver which selectively drives the word lines on the basis of a row address signal; a plate line connected to one terminal of the block; a plate line driver which drives the plate line; a bit line connected to the other terminal of the block via a second MOS transistor for block selection; a column decoder which selects the bit line on the basis of a column address signal; and a driver/controller configured to apply a potential difference between the plate line and the bit line while said plurality of word lines are kept off, the driver/controller generating and outputting a driving signal for the plate line by receiving a driving potential in a normal mode of the plate line and a testing plate line potential from the plate line driver, and generating and outputting a driving signal for the bit line by receiving a testing bit line potential from the column decoder.