Patent ID: 8230142

Claim:
A device, comprising: a memory core having a shared buffer; an arbitration module for receiving a destination ready signal from a processing source of a plurality of processing sources; a first pipeline stage for storing at least one piece of data read from said shared buffer; a second pipeline stage, different from said first pipeline stage, for storing at least one valid signal that causes said at least one piece of data to be read from said shared buffer and passed to said first pipeline stage; and a counter for storing a value, wherein said value represents a number of pieces of data read from said shared buffer, but not delivered to said processing source, wherein said value is determined in accordance with: if one piece of data exits said shared buffer, but one piece of data does not exit said memory core, then said value is incremented; if one piece of data exits said memory core, but one piece of data does not exit said shared buffer, then said value is decremented; if one piece of data exits said memory core, and one piece of data exits said shared buffer, then said value remains the same; and if no data moves from said memory core and said shared buffer, then said value remains the same.