Patent ID: 8060669

Claim:
A memory controller for a flash memory device that includes a flash memory, the memory controller comprising: a buffer memory configured to store data to be written in the flash memory device; a buffer memory interface configured to control read and write operations of the buffer memory; and an automatic command processing unit configured to receive a data command generated by a host hardware device, wherein the data command includes write information, wherein the automatic command processing unit controls the buffer memory interface to determine that input data that is not previously stored in the buffer memory and that is to be written in the flash memory is consecutive to previous data stored in the buffer memory and that is to be written in the flash memory and stores the input data that is to be written in the flash memory consecutive to the previous data that is to be written in the flash memory that is stored in the buffer memory, wherein the automatic command processing unit controls the buffer memory interface to determine, responsive to receipt of input data, that input data that is to be written in the flash memory is not consecutive to previous data that is to be written in the flash memory and that is stored in the buffer memory and stores the input data that is to be written in the flash memory in a random location in the buffer memory, wherein the automatic command processing unit comprises a cache table configured to store logical address-physical address mapping information corresponding to data stored in the buffer memory; and wherein the automatic command processing unit is configured to determine, responsive to the mapping information, whether input data is consecutive to the previous data stored in the buffer memory.