Patent ID: 7884465

Claim:
A semiconductor package comprising: a semiconductor chip being an active device, the semiconductor chip having a plurality of bonding pads formed on a top surface and a plurality of first via holes and at least one second via hole formed on edges thereof; a passive element comprising a dielectric material formed within each of the plurality of first via holes such that a top surface and a bottom surface of the dielectric material formed within each of the first via holes are recessed from a top surface and a bottom surface of the semiconductor chip, respectively, wherein a thickness the dielectric material formed within each of the plurality of first via holes is the same or different; a via wiring formed within the second via hole; a first wiring formed on the top surface of the semiconductor chip and on the top surface of the dielectric material formed within each of the first via holes so as to connect to the bonding pad on the top surface of the semiconductor chip at one end and connect to the dielectric material formed within each of the plurality of first via holes and the via wiring on top surfaces thereof; a second wiring formed on the bottom surface of the semiconductor chip and on the bottom surface of the dielectric material formed within each of the first via holes so as to connect to the dielectric material formed within each of the plurality of first via holes and the via wiring on bottom surfaces thereof; a first passivation film formed in such a way to expose one portion of the first wiring on a top surface of the semiconductor chip and to expose the via wiring; and a second passivation film formed in such a way to expose one portion of the second wiring on a bottom surface of the semiconductor chip and the via wiring.