Patent ID: 7822924

Claim:
In a computer system, a method comprising: caching instructions in a cache associated with a first processing unit of a plurality of processing units of the computer system from a page of primary code stored in a memory storage unit, the caching comprising modifying an entry of a table in the memory storage unit indicating which processing units of the plurality of processing units have currently cached instructions from the page of primary code; checking in a first message queue of the first processing unit for a first notification message received from a second processing unit of the plurality of processing units indicating potential storing to the page of primary code by the second processing unit, and responsive to the first notification message being present in the first message queue, invalidating cached instructions from the page of primary code in the cache associated with the first processing unit; and executing by the first processing unit cached instructions, wherein the executing comprises fetching from the cache a next instruction to be executed and checking whether the next instruction is a store instruction that modifies one or more instructions of the page of primary code, and responsive to the checking indicating that the next instruction is a store instruction, referencing the entry of the table in the memory storage unit to ascertain which processing units of the plurality of processing units have currently cached instructions from the page of primary code and forwarding a second notification message to at least one of the processing units having currently cached instructions from the page of primary code reporting a modification by the first processing unit to the page of primary code, thereby facilitating cache coherency across the plurality of processing units without requiring a cache coherency search of a cache associated with another processing unit of the plurality of processing units.