Patent ID: 6867087

Claim:
In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depiction near the gate oxide, comprising: a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site; b) forming an undoped polysilicon layer over said gate oxide layer; c) masking said pMOS site, forming an a-Si layer over said nMOS site by implanting a first heavy ion into selected from the group consisting of Ge and Si, a top portion of said undoped polysilicon to form said a-Si layer over a remaining layer of undoped polysilicon between said gate oxide layer and said a-Si layer, and implanting arsenic solely into said a-Si layer; d) masking said nMOS site formed by step c), forming an a-Si layer over said pMOS site by implanting a second heavy ion selected from the group consisting of Ge and Si, into a top portion of said undoped polysilicon to form said a-Si layer over a remaining layer of undoped polysilicon between said gate oxide layer and said a-Si layer, and implanting boron solely into said a-Si regions; e) laser annealing said nMOS and pMOS sites for a period of time between about 40 ns and 80 ns, and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; and f) affecting cooling after laser annealing to convert a-Si into polysilicon without gate oxide damage.