Patent ID: 8166441

Claim:
A processor-based method of designing a logic circuit based on one of the functions of the form: f n =x 1 ( x 2 & ( x 3 ( x 4 & . . . x n . . . ))), and f′ n =x 1 & ( x 2 ( x 3 & ( x 4 . . . x n . . . ))), comprising the steps of: a. selecting N as the number of variables of the logic circuit, b. testing N against a threshold, c. for values of N less than the threshold, using a first algorithm to design the logic circuit using the processor, where the first algorithm is a heuristic optimization of a base algorithm; adapted for reduced accuracy and enhanced speed of computation, and d. for values of N greater than the threshold, using a second algorithm to design the logic circuit using the processor, where the second algorithm is an n-restricted algorithm that uses, in all arrays of the base algorithm, only elements that have n-good binary expansions, loops of the base algorithm having a form of for(i=0; i<NN; i++) are replaced with for(i=0; i<NN; i=next after i number with n-good expansion), conditions of the base algorithm having a form of if(depth[k]>d) are replaced with if(k is n-good) if(depth[k]>d), and the second algorithm operates with the logic circuits such that passports of all subfunctions are n-good, and e. the base algorithm is characterized by a search of all possible combinations of the logic circuit, and a selection of the logic circuit having a lowest depth.