Patent ID: 7797649

Claim:
A computer implemented method of estimating an interconnect line length cost to connect circuit elements of a net in an integrated circuit (“IC”) layout, the net representing interconnections between a set of circuit elements in the IC layout, the method comprising: using a processor configured for: identifying a plurality of circuit elements for the net, wherein at least one diagonal routing direction is available to route at least one of the interconnections between at least two of the plurality of circuit elements; determining a bounding box that encompasses the plurality of circuit elements of the net, wherein at least a part of boundaries of the bounding box is determined by a continuous formulation rather than by a point-by-point comparison of coordinates for locations of a plurality of points to route for the plurality of circuit elements; and using the bounding box to estimate the interconnect line length cost to connect the plurality of circuit elements of the net; and using a computer readable storage medium or a computer storage device for storing at least the bounding box or using a display apparatus configured for displaying the bounding box.