Patent ID: 7423900

Claim:
An SRAM memory system, comprising: a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines); at least one interface circuit operable to mirror logic values of at least one of the bit lines to a global bit line; and at least one pre-charge circuit operable to drive the global bit line to a pre-charge logic value in response to a clock signal, wherein the at least one interface circuit includes: a first transistor having a high current terminal that switches the global bit line to a reference potential in response to a control signal on a control terminal thereof; a combinational logic circuit including at least one logic gate operable to provide the control signal to the first transistor as a function of the bit line; a second transistor having a high current terminal that shunts the control signal from the control terminal of the first transistor to a reference potential such that the interface circuit is prohibited from mirroring the logic value of the bit line to the global bit line in response to a write signal indicative of a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.