Patent ID: 6905897

Claim:
A wafer acceptance testing (WAT) method for monitoring gate conductor-deep trench (GC-DT) misalignment, comprising the steps of: providing a test key structure comprising a deep trench capacitor structure biased to a first voltage (V DT ) embedded in a substrate, an active area being defined on the substrate, wherein the deep trench capacitor structure is electrically connected to an out diffusion in the active area and is isolated by shallow trench isolation (STI), and the deep trench capacitor structure comprises an interdigitated GC-T electrode layout and a GC-B electrode layout, wherein the GC-T electrode layout is biased to a second voltage (V GC-T ), and the GC-B electrode layout is biased to a third voltage (V GC-B ), and wherein the GC-T electrode layout comprises a plurality of first GC fingers, the GC-B electrode layout comprises a plurality of second GC fingers; measuring a capacitance of a first capacitor C 1 , wherein the GC-T electrode layout serves as a first electrode of the first capacitor C 1 and the out diffusion serves as a second electrode of the first capacitor C 1 ; measuring a capacitance of a second capacitor C 2 , wherein the GC-B electrode layout serves as a first electrode of the second capacitor C 2 and the out diffusion serves as a second electrode of the second capacitor C 2 ; and comparing the capacitance of the first capacitor C 1 with the capacitance of the second capacitor C 2 , wherein if C 1 ≠C 2 , GC-DT misalignment occurs.