Patent ID: 8232823

Claim:
An integrated circuit (IC) comprising: a memory comprising a plurality of programmable fuses; a control block coupled to the plurality of programmable fuses, wherein a value stored by the plurality of programmable fuses is operable to control operation of the control block, the value representing a delay between a clock signal and a data signal; a first tuning circuit coupled to the control block, wherein the first tuning circuit is operable to receive a delay value from the control block, wherein the first tuning circuit is configured to shift a received clock signal according to the delay value to generate a shifted clock signal, the first tuning circuit comprising a plurality of logic cells arranged serially, wherein the received clock signal traverses one of a first signal path or a second signal path within each logic cell of the plurality of logic cells, each logic cell including a multiplexer operable to select one of the first signal path or the second signal path; and a selection circuit coupled between the control block and the first tuning circuit, wherein the selection circuit is operable to select a test signal in a first mode of the IC and an output of the control block in a second mode of the IC, wherein utilization of the test signal in the first mode outputs the value for storage in the memory, and wherein the value read from the memory by the control block is selected in the second mode of the IC.