Patent ID: 7352026

Claim:
An electrically erasable and programmable read only memory (EEPROM) cell comprising: a substrate including a first region, in which a first EEPROM device having a first select transistor and a first memory transistor is disposed, and a second region, in which a second EEPROM device having a second select transistor and a second memory transistor is disposed; a first drain region and a first floating region, which are disposed apart from each other in the first region of the substrate; a second drain region and a second floating region, which are disposed apart from each other in the second region of the substrate; and a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region, which are disposed between the first region and the second region of the substrate, wherein the first impurity region completely surrounds the second impurity region and the third impurity region in horizontal and vertical directions and a junction depth of the first impurity region is greater than a junction depth of the fourth impurity region, the second impurity region surrounds the third impurity region in the horizontal direction, and the junction depth of the third impurity region is greater than the junction depth of the second impurity region; and wherein the fourth impurity region is formed using a dopant of a different conductivity type from those of the first, second, and third impurity regions.