Patent ID: 6924810

Claim:
A processor comprising: central processing unit operable to execute one or more instructions; a graphics unit operable to process graphics data; a cache operable to be shared by the central processing unit and the graphics unit, the cache comprising a dynamically configurable portion, in which at least a portion of the graphics data is stored by at least one of the central processing unit and the graphics unit, and a controller operable to control access to the cache by the central processing unit and the graphics unit; wherein the controller is operable to allow access to the cache in one of a plurality of modes, each mode allowing different access to the shared cache where a first mode allows the central processing unit and the graphics unit to replace data in any region of the shared cache; and a second mode allows the central processing unit to replace data in any region of the shared cache and that allows the graphics unit to replace data in a subset of the regions of the shared cache.