Patent ID: 6888250

Claim:
A semiconductor device comprising: a first wiring layer defining a first direction and first virtual linear lines extending in a direction that traverses the direction; a plurality of dummy wiring layers provided in an identical level as the first wiring layer; and at least one restriction region; wherein the first direction and the first virtual linear lines define an angle of 2 to 40 degrees; wherein the first wiring layer further defines a second direction perpendicular to the first direction and second virtual linear lines extending in a direction that traverses the second direction; wherein the second virtual linear lines and the second direction define an angle of 2 to 40 degrees, and wherein the plurality of dummy wiring layers are disposed on the second virtual linear lines; wherein adjacent ones of the dummy wiring layers that are disposed in the first direction are spaced a first distance from one another, the first distance being about a half of a side of each of the dummy wiring layers; wherein adjacent ones of the dummy wiring layers that are disposed in the first direction are offset by a second distance from one another in the second direction, the second distance being about a half of side of each of the dummy wiring layers; and wherein the dummy wiring layers are entirely excluded from the restriction region and are spaced apart from a boundary of the restriction region.