Patent ID: 7320043

Claim:
A system for communicating digital computer data over extended distances comprising: a processor coupled to a first communication link and generating digital data for communication on the first communication link, wherein the data are communicated according to a standard digital communication format, and wherein the data generated by the processor include information providing video data for use by a video monitor; a first logic device receiving the digital data generated by the processor and communicated on the first link, the first logic device converting the received digital data into a second digital communication format different from the standard digital communication format, and coupling the converted data to a second communication link different from the first communication link; a second logic device coupled to the second communication link and receiving the converted data from the first logic device, the second logic device converting the data from the second link into a third digital communication format and coupling the data in the third digital communication format to a third communication link different from the first and second communication links, wherein at least one component of the first logic device is separated from at least one component of the second logic device by at least one clock domain barrier; a video processing circuit coupled to the third communication link and receiving therefrom at least the information providing video data generated by the processor, the video processing circuit providing the video data in a format suitable for use by the video monitor and transmitting the video data to the video monitor, wherein said second logic device is constructed and adapted to deliver sideband signals to said first logic device, said sideband signals including (i) an acknowledgement (ACK) signal indicative of successful buffering by said second logic device of data received from said first logic device, and (ii) a negative acknowledgement (NACK) signal indicative of unsuccessful buffering by said second logic device of uncorrupted data received from said first logic device, said unsuccessful buffering being caused by a full buffer at said second logic device, wherein said second logic device is further constructed and adapted to not send two successive NACK signals without at least one intervening ACK signal indicative of successful buffering of valid data at said second logic device.