Patent ID: 7378309

Claim:
A method of fabricating local interconnect on a silicon-germanium 3D CMOS comprising: fabricating an active silicon CMOS device, having a gate, on a silicon substrate; depositing an insulator layer on the silicon substrate; opening a seed window through the insulator layer to the silicon substrate and to the gate of the silicon CMOS device; depositing a germanium thin film on the insulator layer, wherein the germanium fills the windows forming a contact between the germanium thin film and the silicon substrate, and between the germanium thin film and the silicon CMOS device; patterning and etching the germanium thin film; encapsulating the germanium thin film in a dielectric material; rapid thermal annealing the wafer and the layers formed thereon at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition; cooling to solidify the germanium as single crystal germanium and as polycrystalline germanium; fabricating a germanium CMOS on the single crystal germanium thin film; and using germanium taken from the forms of germanium consisting of single crystal germanium and polycrystalline germanium to from local interconnects between the silicon CMOS and the germanium CMOS.