Patent ID: 7752373

Claim:
A device to control memory operation, the device comprising: a first memory controller; a state machine embedded in the first memory controller, the state machine operable to request control of at least one pin shareable between a non-volatile memory device and a dynamic random access memory device, wherein the state machine enters a first state in response to a pin access signal, enters a second state in response to a completion event, enters a third state in response to a clock change request signal, and enters a fourth state in response to a clock adjust complete signal; a second memory controller having a communication path to the state machine and having selective control of the at least one shareable pin, the second memory controller responsive to a signal from the state machine to release control of the at least one shareable pin; and a clock to generate a first clock signal at a first clock frequency to be applied to the first memory controller and to the second memory controller when the first memory controller performs a memory operation, the clock to generate a second clock signal at a second clock frequency to be applied to the first memory controller and to the second memory controller when the second memory controller performs a memory operation.