Patent ID: 8351255

Claim:
A semiconductor device having a plurality of nonvolatile memory cells, each said memory cell including a control gate formed in a semiconductor substrate and a floating gate formed over the semiconductor substrate, the semiconductor device comprising: a groove formed in the semiconductor substrate; a first insulating film embedded in the groove; a first active region, a second active region, a third active region and dummy regions formed in the semiconductor substrate and defined by the groove; a capacitor element formed in the first active region and including the control gate and a first portion of the floating gate; an element to read data formed in the second active region and including a second portion of the floating gate; and an element to program data formed in the third active region and including a third portion of the floating gate, wherein a plan area of the first portion of the floating gate is greater than respective plan areas of the second and third portions, and wherein, in a plan view, a part of the dummy active regions are arranged between the first active region and the second active region.