Patent ID: 8232843

Claim:
A system, comprising: a plurality of cross-coupled all digital phase locked loop (ADPLL) circuits, each ADPLL circuit structured to output a clock signal, and each ADPLL circuit including: an oscillator having an input terminal and an output terminal, the oscillator having a matrix structure formed of a plurality of oscillator cells, each oscillator cell having a central oscillator and a plurality of ring oscillators that are each coupled to the central oscillator and coupled in series to one another, the oscillator configured to output the clock signal on the output terminal of the oscillator; and a phase frequency detector having an input terminal coupled to the output terminal of the oscillator of the ADPLL circuit, the phase frequency detector structured to receive the clock signals from the ADPLL circuits and having an output terminal coupled to the input terminal of the oscillator of the ADPLL circuit, the phase frequency detector structured to align a phase of the clock signal received from the oscillator of the ADPLL circuit to a phase of the clock signals received from the other ADPLL circuits.