Patent ID: 7127659

Claim:
An apparatus for performing Low Density Parity Check (LDPC) decoding operations, comprising: a check node processor module including: i) check node state memory including a plurality of message state memory storage elements for a plurality of check nodes, each check node state storage element corresponding to a single check node and including a first and a second location for storing for storing first and second message magnitude values corresponding to messages directed to the check node to which said check node state memory corresponds, each node state storage element further including a sign memory location for storing an accumulated sign value corresponding to the check node to which the check node state storage element corresponds; ii) a check node processor element for updating state stored in said check node state memory based on the content of a received variable node to check node state message; and iii) a control module coupled to said check node state memory for controlling said check node state memory to output check node state, corresponding to the same check node as a variable to check node message to be processed, said check node state being output from the one of said check node state storage elements which corresponds to the same node as said variable to check node message to be processed.