Patent ID: 8078890

Claim:
A computing system, comprising: a processor; memory; an operating system, wherein: the operating system includes a power management component that is operable to place the memory of the computer system in multiple memory performance states of operation, the multiple memory performance states of operation differ from one another according to the amount of power consumed by memory in each state of operation, the operating system includes a supported states routine that produces an output identifying the multiple memory performance states of operation supported by the computing system, the operating system includes a capabilities routine that produces an output identifying a set of the multiple memory performance states of operation supported by the computing system that are available for use, the operating system is operable to limit the memory to the set of multiple memory performance states identified by the output of the capabilities routine, and the operating system is further operable to cause a transition from a first of the multiple memory performance states of operation to a second of the multiple memory performance states of operation, wherein if the transition from the first of the multiple memory performance states of operation to the second of the multiple memory performance states of operation is unsuccessful after a predetermined number of attempts, the operating system returns to the first of the multiple memory performance states of operation.