Patent ID: 7624260

Claim:
A processing system comprising: a processor responsive to a reset signal for directing initial execution of a program at a reset vector; self-refreshing random access memory accessible by the processor; read only memory storing an operating system image file, an initial program loader beginning at the reset vector, and startup code loaded into the self-refreshing random access memory in response to execution of the initial program loader; a power control system responsive to power commands and/or power control signals to direct the system into a low-power mode and to wake-up the system from the low-power mode, where the processor and self-refreshing random access memory are each directed into a low-power consumption state during the low-power mode, and where the power control system generates the reset signal to the processor to direct the system to wake-up from the low-power mode, where the processor and self-refreshing random access memory are directed out of their respective low-power states to an operating power consumption state when the system wakes-up from the low-power mode; where either the initial program loader or the startup code selectively performs a full boot copy of the operating system image file from the read only memory to the self-refreshing random access memory in response to an initial power-up of the system, or a fast boot copy of only predetermined portions of the operating system image file from the read only memory to the self-refreshing random access memory when waking-up from the low-power mode.