Patent ID: 8188798

Claim:
A dithering clock generator comprising: an oscillator that generates a clock having a frequency that varies with dithering to reduce Electro-Magnetic Interference (EMI); a control circuit, receiving the clock, for generating a digital count value that varies over time in response to the clock; a digital-to-analog converter (DAC) receiving the digital count value from the control circuit, the DAC generating a DAC voltage having a first voltage swing; a subtractor, receiving the DAC voltage, for scaling down the first voltage swing of the DAC voltage to generate a limit voltage having a second voltage swing, the second voltage swing being less than the first voltage swing; and a first comparator, receiving the limit voltage from the subtractor, for dithering the oscillator by adjusting timing of edges of the clock, whereby the first voltage swing of the DAC is reduced by the subtractor before dithering the oscillator.