Patent ID: 7078289

Claim:
A method for fabricating a trench capacitor of DRAM devices, comprising: providing a substrate having a deep trench etched therein; doping the deep trench to form a buried plate electrode in the substrate adjacent to a lower portion of the deep trench; forming a node dielectric layer on interior surface of the deep trench; depositing a first polysilicon layer in the deep trench; recessing the first polysilicon layer to a first depth d 1 in the deep trench, a top surface of the recessed first polysilicon layer and the node dielectric layer constituting a first recess; depositing a silicon spacer layer in the first recess; anistropic etching the silicon spacer layer and the first polysilicon layer inside the deep trench to a second depth d 2 , wherein the remaining silicon spacer layer becomes a spacer; removing the node dielectric layer that is not covered by the spacer and the first polysilicon layer, thereby exposing a silicon surface at a neck portion of the deep trench, wherein the node dielectric layer is divided into an upper dielectric section and a lower dielectric section that serves as a capacitor dielectric of the trench capacitor; oxidizing the spacer, the silicon surface at the neck portion of the deep trench and an upper portion of the first polysilicon layer, thereby forming a silicon oxide layer; and etching away the silicon oxide layer.