Patent ID: 7718525

Claim:
A method of forming a metal interconnect, the method comprising: providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric, wherein the planarizing layer forming includes: forming a non-photoactive polymer layer; and forming a low temperature oxide (LTO) layer over the non-photoactive polymer layer; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.