Patent ID: 6940138

Claim:
A semiconductor device, comprising: a supporting substrate having insulation at least at a surface thereof; a semiconductor layer fanned on the surface of the supporting substrate; a transistor element fanned in the semiconductor layer, the transistor element comprising a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an insulating layer formed on the channel region, and an electrode formed on the insulating layer; the transistor element including: a first semiconductor region of the first conductive type and a second semiconductor region of the first conductive type; the second semiconductor region being provided on the surface of the supporting substrate at least at one end, in a channel width direction, of at least one of the source region and the drain region, the second semiconductor region following the at least one end in a channel length direction; the electrode is non-overlapping with the second semiconductor region in plan view; the first semiconductor region being provided on the surface of the supporting substrate so as to be sandwiched by the second semiconductor region and one of the source region and the drain region, following the second semiconductor region; the second semiconductor region having an impurity concentration which is higher than that in the channel region, and the first semiconductor region being a semiconductor of the first conductive type, and having an impurity concentration which is higher than that in the channel region, and the first semiconductor region having an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region.