Patent ID: 8053681

Claim:
An Integrated Circuit (IC) package comprising: a multi-layered PCB having a plurality of insulating layers and a plurality of conductive pattern layers stacked in an alternate and repetitive manner, and a plurality of via-holes formed through said plurality of the insulating layers for an electrical connection between the layers; and an IC chip disposed in a core insulating layer of said plurality of the insulating layers to be embedded in said multi-layered PCB and including a plurality of input/output pads thereof, wherein the input/output pads disposed at an outermost area of said IC chip among said plurality of the input/output pads are coupled to outer terminals by connection members without passing through said via-hole, and wherein the remaining input/output pads except for the input/output pads disposed at the outermost area of said IC chip are coupled to the outer terminals through said via-hole.