Patent ID: 7321634

Claim:
A sigma-delta modulation method, comprising: partitioning a digital input signal comprising (M+L)-bit words into a less-significant bit signal and a more-significant bit signal wherein the partitioning comprises partitioning the digital input signal into the more-significant bit signal comprising M-bit words and the partitioning comprises partitioning the digital input signal into the less-significant bit signal comprising L-bit words; performing a lower-order modulation of the less-significant bit signal to generate an intermediate output signal, the intermediate output signal comprises P-bit words, where P is less than L; appending the intermediate output signal to the more-significant bit signal as less significant bits to form an intermediate input signal; and performing a higher-order modulation of the intermediate output signal using a (M+P)-bit third order delta-sigma modulator to generate a digital output signal, the higher-order modulation of an order higher than the lower-order modulation.