Patent ID: 7433656

Claim:
An integrated circuit device, comprising: logic circuitry for performing a specified function; and a multi-stage amplifier operably disposed to amplify continuous waveform signals for subsequent processing by the logic circuitry, comprising: a first amplification stage operably disposed to receive an input signal wherein the first amplification stage is operable to produce an intermediate stage output signal; a second amplification stage operably disposed to receive the intermediate stage output signal, wherein the second amplification stage is operable to produce an amplified output signal; a loading stage operably disposed to receive the intermediate stage output signal and operable to conduct a common mode portion of the intermediate stage output signal to a circuit common; and a degeneration block operably disposed between circuit common and the loading stage wherein the degeneration block is operable to reduce flicker noise generated by at least one of the loading stage, the first amplification stage and the second amplification stage, wherein the degeneration block further includes: at least one active MOSFET operably biased in a linear region to provide a specified resistive value and coupled to receive and conduct the common mode portion of the intermediate stage output signal based upon a gate terminal bias signal; a degeneration block amplifier for generating a replica device bias signal; and a replica device operable to set the gate terminal bias signal for the at least one active MOSFET based upon the replica device bias signal.