Patent ID: 8350373

Claim:
A chip stacked structure, comprising: a first chip, having at least one first chip groove and at least one first chip upper metal pad, the at least one first chip groove being formed on a side surface of the first chip and the at least one first chip upper metal pad being formed on an upper surface of the first chip and connected to an upper opening of the at least one first chip groove; and a second chip, stacked on the first chip, having at least one second chip groove formed on a side surface of the second chip, and the second chip having at least one second chip lower metal pad formed on a lower surface of the second chip and connected to a lower opening of the at least one second chip groove, wherein the at least one first chip upper metal pad and the at least one second chip lower metal pad are disposed face to face; wherein at least one the first chip groove is disposed corresponding to the at least one second chip groove so as to form at least one connection groove, and at least one conductive film is formed on the at least one connection groove and the at least one first chip upper metal pad so as to connect the first chip and the second chip.