Patent ID: 7525778

Claim:
A semiconductor integrated circuit comprising: first and second input terminals; a first transistor configured to conduct in response to a first input signal being supplied to a gate of the first transistor through the first input terminal; a second transistor configured to conduct in response to a second input signal being supplied to a gate of the second transistor through the second input terminal; a first protection element coupled between a gate of the first transistor and the ground or between a gate of the first transistor and a power source line so as to discharge minus or plus charge generated during manufacturing of the semiconductor integrated circuit to the ground or the power source line by operating at a lower voltage than a PN junction breakdown voltage, the first protection element including a plurality of gate-drain connected MOS transistors coupled as a cascade; and a second protection element coupled between a gate of the second transistor and the ground or between a gate of the second transistor and a power source line so as to discharge minus or plus charge generated during manufacturing of the semiconductor integrated circuit to the ground or the source line by operating at a lower voltage than a PN junction breakdown voltage, the second protection element including a plurality of gate-drain connected MOS transistors coupled as a cascade, wherein a source and drain of the respective first and second transistors are coupled to one of the ground and the power source, respectively, and the drain and source of the respective first and second transistors are coupled to the other of the ground and the power source, respectively, so as to constitute a differential amplifier, and wherein each of the first and second input terminals is coupled to the gate of the respective first and second transistors and each of the respective first and second protection elements through a wiring layer adjoined to the ground or the power source line.