Patent ID: 7277312

Claim:
An integrated semiconductor memory comprising: a plurality of nonvolatile memory cells; and a plurality of first lines and second lines that can be electrically biased for the purpose of programming and erasing the memory cells; wherein each memory cell is coupled to a respective first line and a respective second line and includes a layer stack that has a solid electrolyte and that is arranged between the respective first line and the respective second line; wherein the layer stacks in the memory cells are in a form such that their resistance can be altered by the level of a voltage applied between the respective first line and the respective second line and assumes a first value at a sufficiently high positive voltage and a different, second value at a sufficiently high negative voltage; wherein the first lines and the second lines can be actuated such that electrical potentials on the first lines and on the second lines are changed, for the purpose of selectively erasing a selected memory cell selectively in relation to all the other memory cells in the arrangement of memory cells, such that, respectively, that first line to which the selected memory cell is coupled is biased with a first potential selectively in relation to all the other first lines, and that second line to which the selected memory cell is coupled is biased with a second potential selectively in relation to all the other second lines, and all the other first lines are biased with a third potential and all the other second lines are biased with a fourth potential; wherein a potential difference between the first potential and the second potential is greater than a limit value for an erasure voltage, above which limit value any memory cell in the arrangement is reliably erased; and wherein the third and the fourth potential are proportioned such that, during the selective erasure of the selected memory cell, voltages applied to the other memory cells are so low that erasure operations and programming operations in the other memory cells are prevented.