Patent ID: 8119495

Claim:
A method of manufacturing a semiconductor device comprising steps of: (a) forming a first insulating film over a semiconductor substrate; (b) after the step (a), forming a first conductive film over the first insulating film; (c) after the step (b), forming a mask layer over the first conductive film; (d) after the step (c), patterning the first insulating film, the first conductive film and the mask layer; (e) after the step (d), forming grooves in the semiconductor substrate by using the patterned mask layer, thereby an active region, a plurality of first dummy regions and a plurality of second dummy regions are formed in the semiconductor substrate; (f) after the step (e), forming element isolation regions by embedding second insulating films into the grooves; (g) after the step (f), removing the patterned mask layer; and (h) after the step (g), forming a second conductive film over the first conductive film, wherein, in the active region, the first and second conductive films constitute a gate electrode of a MISFET, wherein, in the active region, the first insulating film constitutes a gate insulating film of the MISFET, wherein a planar size of each of the first dummy regions is larger than a planar size of each of the second dummy regions, and wherein each of the first dummy regions is arranged with same pitch, wherein each of the second dummy regions is arranged with same pitch, and wherein the second dummy regions are arranged next to the first dummy regions, and are arranged between the active region and the first dummy regions.