Patent ID: 7465624

Claim:
A method of manufacturing a semiconductor device, comprising: forming an electrode pattern made of at least one element selected from silicon and germanium on a gate insulating film in an n-MOS region and a p-MOS region of a semiconductor substrate; masking the n-MOS region including the first electrode pattern with a first insulating film pattern; forming a first metal film made of Pd, Pt, Rh, Ir, or their alloys all over the surface; forming a gate electrode consisting of a reactant between the first metal and at least one element selected from silicon and germanium by heating to react the first metal film with the electrode pattern in the p-MOS region contacting with the first metal film; forming an oxide film of at least one element selected from silicon and germanium on the surface of the gate electrode by oxidation; dissolving away a non-reacting first metal film with an acid solution in which the first metal is soluble; removing the first insulating film pattern; masking the p-MOS region including the electrode pattern with a second insulating film pattern; forming a second metal film made of Er, Y, Gd, Tm, Dy, Ce, or their alloys all over the surface; forming a gate electrode consisting of a reactant between the second metal and at least one element selected from silicon and germanium by heating to react the second metal film with the electrode pattern in the n-MOS region contacting with the second metal film; and dissolving away a non-reacting second metal film with an acid solution in which the second metal is soluble.