Patent ID: 7747667

Claim:
A data processing apparatus, responsive to an input value, for generating an initial estimate of a result value that would be produced by performing a reciprocal operation on said input value regardless of whether said input value is a fixed point value or a floating point value, the data processing apparatus comprising: a register file comprised of a plurality of registers for storing data, said data including data indicative of said input value; processing circuitry configured to access said register file and to execute a sequence of instructions to perform data processing operations on said data, at least one of the instructions being an estimate instruction identifying said input value by reference to said input value indicative data, and identifying whether said input value is a fixed point value or a floating point value; a lookup table for storing table output bit patterns corresponding to modified input values within a predetermined range of values; formatting circuitry, responsive to said estimate instruction, for generating a modified input value within said predetermined range of values, the generating differing dependent on whether said input value is a fixed point value or a floating point value such that if said input value is a fixed point value, a predetermined subset of bits of said modified input value are selected as at least part of a table input value, whereas if said input value is a floating point value, a predetermined subset of bits from a fraction portion of said modified input value are selected as at least part of the table input value; said processing circuitry further, in response to said table input value, for accessing said lookup table to obtain the corresponding table output bit pattern, the corresponding table output bit pattern obtained in response to said table input value being the same regardless of whether said input value is a fixed point value or a floating point value; and said processing circuitry further, in response to said corresponding table output bit pattern, for calculating said initial estimate, said calculating step differing dependent on whether said input value is a fixed point value or a floating point value, such that if said input value is a fixed point value, said table output bit pattern forms at least a part of a bit pattern of said initial estimate, whereas if said input value is a floating point value, said table output bit pattern forms at least a part of a bit pattern of the fraction portion of said initial estimate; said processing circuitry being configured to store said initial estimate in a register of said register file.