Patent ID: 8521934

Claim:
A host controller for a bus, the host controller comprising: a plurality of functional modules interconnected to manage transfer of data between a host bus and a root hub configured to communicate with one or more USB device endpoints on the bus, the plurality of functional modules comprising a DMA engine to transfer one or more data payloads between the host bus and the root hub, a transfer manager configured to determine what control data and/or data payloads should be transferred, and a scheduler to schedule actions performed by the transfer manager; and a plurality of control memories, each control memory associated with one or more of the functional modules, each control memory storing state and/or data information fields to be accessed by its one or more associated functional modules, the plurality of control memories being distinct and independently accessible from one another, the plurality of control memories comprising a control memory for the transfer manager being configured to store all fields used by the transfer manager so that the transfer manager can access its control memory without contention from other functional modules.