Patent ID: 7791577

Claim:
A liquid crystal display device comprising a plurality of pixels that are arranged in columns and rows so as to form a matrix pattern, each said pixel including a liquid crystal layer and a plurality of electrodes for applying a voltage to the liquid crystal layer, wherein each said pixel includes a first subpixel and a second subpixel, having liquid crystal layers to which mutually different voltages are applicable, the first subpixel having higher luminance than the second subpixel at a particular gray scale, and wherein each of the first and second subpixels includes a liquid crystal capacitor formed by a counter electrode and a subpixel electrode that faces the counter electrode through the liquid crystal layer, and a storage capacitor formed by a storage capacitor electrode that is electrically connected to the subpixel electrode, an insulating layer, and a storage capacitor counter electrode that is opposed to the storage capacitor electrode with the insulating layer interposed between them; and wherein the counter electrode is a single electrode provided in common for the first and second subpixels, while the storage capacitor counter electrodes of the first and second subpixels are electrically independent of each other, and wherein the storage capacitor counter electrode of the first subpixel of an arbitrary one of the pixels and the storage capacitor counter electrode of the second subpixel of a pixel that is adjacent to the arbitrary pixel in a column direction are also electrically independent of each other, wherein the device further includes a plurality of electrically independent storage capacitor trunks, and wherein each said storage capacitor trunk is electrically connected to the respective storage capacitor counter electrodes of either the first subpixels or the second subpixels of the pixels through storage capacitor lines, and wherein a storage capacitor counter voltage supplied through each said storage capacitor trunk has a first period (A) with a first waveform and a second period (B) with a second waveform within one vertical scanning period (V-Total) of an input video signal, the sum of the first and second periods being equal to one vertical scanning period (V-Total=A+B), and wherein the first waveform oscillates between first and second voltage levels in a first cycle time P A , which is an integral number of times as long as, and at least twice as long as, one horizontal scanning period (H), and wherein the second waveform is defined such that the effective value of the storage capacitor counter voltage has a predetermined constant value every predetermined number of consecutive vertical scanning periods, the number being equal to or smaller than 20.