Patent ID: 8630317

Claim:
An integrated circuit device comprising: a transmitter circuit operable to transmit a timing signal over a first wire to a dynamic random access memory (DRAM), where the DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value; and a receiver circuit operable to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire, where the transmitter circuit: in a first mode, repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values, in connection with a write operation to the DRAM.