Patent ID: 7676783

Claim:
An apparatus for performing in-memory computation for stateful, transaction-oriented applications, the said apparatus comprising: a multi-level array of storage cells, the storage cells configurable for a read access from one of a plurality of access data paths, the plurality of access data paths being configurable for a write access from one of the plurality of access data paths, the multi-level array being configurable into logical partitions with arbitrary starting addresses; a compute element in communication with the multi-level array over the plurality of access data paths, the compute element configured to issue a plurality of memory accesses to the multi-level array through the plurality of access data paths; and a pre-decode stage, the pre-decode stage including, a control store code memory having a fixed instruction length program code, the instruction length program code read from the control store and pre-decoded for generating opcode, extension address and operand offsets, wherein the operand offsets are summed with a plurality of architectural pointer registers to generate physical addresses for a subsequent operations.