Patent ID: 7078951

Claim:
A system for generating an output signal that has a predetermined phase relative to a periodic input clock signal, comprising: a measurement delay line including a plurality of delay circuits coupled in series with each other from an initial delay circuit that is coupled to receive a first input signal to a final delay circuit, the first input signal having transitions corresponding to predetermined transitions of the input clock signal, the delay circuits propagating the first input signal through the delay circuits from the initial delay circuit toward the final delay circuit, the delay circuits being divided into subsets of delay circuits coupled in series with each other, the subset containing a delay circuit to which a transition of the first input signal has propagated when a subsequent transition of the first input signal is received generating a control signal; a plurality of latches each of which corresponds to a respective one of the subsets of the delay circuits in the measurement delay line, each of the latches having a set input that is coupled to receive the control signal from the corresponding set of delay circuits, the control signal being operable to set the latch; and a signal generating delay line having a plurality of delay circuits coupled in series with each other, the number of delay circuits in the signal generating delay line being a sub-multiple of the number of delay circuits in the measurement delay line, the delay circuits in the signal generating delay line being divided into subsets of delay circuits that are coupled in series with each other, the signal generating delay line receiving a second input signal having transitions corresponding to predetermined transitions of the input clock signal, the number of delay circuits in the signal generating delay line through which the second input signal propagates to generate an output signal being controlled by the set latch so that the percentage of delay circuits in the signal generating delay line through which the second input signal propagates is substantially the same as the percentage of delay circuits in the measurement delay line through which the first input signal propagates.