Patent ID: 7016229

Claim:
A page buffer for an NAND flash memory, comprising: a first latch connected to a first node for storing and loading data; a second latch for storing data stored on a cell depending on a bit line selection signal; a setting means connected between the first node and a power so that the data stored on the first latch is set to a high level for inhibiting the cell from programming; a first switching means for transferring the data stored on the second latch to a data line depending on a page buffer data output signal; a discharging means for discharging charges on the data line; a second switching means for connecting the data line discharged by the discharging means to the first node depending on a data control signal so that the data stored on the first latch is changed to a low level for programming the cell; and a data transferring means for transferring the data of the first latch to the second latch.