Patent ID: 8179733

Claim:
A double data ratio synchronous type dynamic random access memory, comprising: a semiconductor chip having a clock generating circuit that generates clock signals, and an internal circuit whose operation is controlled by clock signals from the clock generating circuit, wherein the internal circuit includes: a plurality of word lines; a plurality of data lines; a plurality of dynamic type memory cells which are coupled to the plurality of word lines and the plurality of data lines; a plurality of sense amplifiers each of which is coupled to the plurality of data lines; a data signal output circuit which is coupled to the plurality of sense amplifiers and outputs data signals to outside of the double data ratio synchronous type dynamic random access memory from the plurality of dynamic type memory cells in synchronism with rising and falling of clock signals generated by the clock generating circuit; and a data strobe signal output circuit which is operated in response to clock signals from the clock generating circuit and which is synchronized with data signals from the data signal output circuit, wherein the semiconductor chip includes: a first pad for supplying a power source voltage to the delay circuit; a second pad for supplying a ground level voltage to the delay circuit; a third pad which is different from the first pad for supplying the power source voltage to the data signal output circuit; and a fourth pad which is different from the second pad for supplying the ground level voltage to the data signal output circuit, wherein the double data ratio synchronous type dynamic random access memory includes: a first terminal which is coupled to the first pad; a second terminal which is coupled to the second pad; a third terminal which is coupled to the third pad and which is different from the first terminal; and a fourth terminal which is coupled to the fourth pad and which is different from the second terminal.