Patent ID: 7843750

Claim:
A semiconductor memory device, comprising: a first sub memory cell array including a plurality of first memory cells connected between a plurality of first word lines and a plurality of bit lines, the plurality of first memory cells each including at least one transistor having a vertical channel structure; a second sub memory cell array including a plurality of second memory cells connected between a plurality of second word lines and a plurality of inverted bit lines, the plurality of second memory cells each including at least one transistor having a vertical channel structure; and a precharge portion disposed at both sides of each bit line and each inverted bit line and precharging each bit line and each inverted bit line to a precharge voltage level at both sides thereof in response to a precharge control signal, wherein each of the plurality of bit lines and the plurality of inverted bit lines is extended in a bit line direction, and the first memory cell array and the second memory cell array are arranged in the bit line direction, wherein the precharge portion includes first and second precharge blocks disposed at first and second sides of a first bit line of the plurality of bit lines, respectively, wherein the first and second precharge blocks precharge the first bit line to a precharge voltage level at the first and second sides of the first bit line, respectively, in response to the precharge control signal, and third and fourth precharge blocks disposed at first and second sides of a first inverted bit line of the plurality of inverted bit lines, respectively, wherein the third and fourth precharge blocks precharge the first inverted bit line to the precharge voltage level at the first and second sides of the first inverted bit line, respectively, in response to the precharge control signal.