Patent ID: 8327074

Claim:
A method of data processing in a multi-processor data processing system including a processor core supported by a store-though upper level cache, the data processing system further including a store-in lower level cache and a system memory, said method comprising: the processor core executing a load-reserve instruction to determine a load target address of a load-reserve operation; responsive to the load target address hitting in the store-through upper level cache, temporarily buffering in the processor core the load target address; if a storage-modifying operation is received by the processor core that conflicts with the buffered load target address of the load-reserve operation, setting a flag to a particular state; and in response to execution of a store-conditional instruction by the processor core, transmitting an associated store-conditional operation to the store-in lower level cache with a fail indication if the flag is set to the particular state so that the lower level cache will fail the store-conditional operation.