Patent ID: 6874013

Claim:
A data processing arrangement comprising: a first processor for providing successive sets of input data; a second processor for receiving successive sets of output data; a memory system including a plurality of memory circuits where all of the plurality of memory circuits are accessible by the first processor for writing and all of the plurality of memory circuits are accessible by the second processor for reading; a master controller for setting up the plurality of memory circuits of said memory system using control commands associated with a set of input data and a set of output data; and a control unit including at least two counters that can be externally loaded with variable, non-zero values, respectively, by signals from the first and second processors, the control unit, on the basis of the control commands and the signals, controls access to the memory system by the first and second processor in an asynchronous manner; wherein at least one of the first processor and the second processor accesses the memory circuits through a crossbar.