Patent ID: 7811890

Claim:
A method of manufacturing a vertical channel transistor structure, comprising: (a) providing a substrate; (b) forming a first layer of cap material on the substrate and a second layer of cap material over the first layer of cap material; (c) etching the second layer of cap material to form a patterned cap layer; (d) trimming the patterned cap layer to form a second patterned cap layer of the cap material, the second patterned cap layer having a width less than that of the patterned cap layer; (e) etching the first layer of cap material and the substrate using the second patterned cap layer as a mask to form a semiconductor fin-shaped structure protruding from the substrate, the semiconductor fin-shaped structure comprising two vertical surfaces; (f) forming a multilayer charge trapping layer, including a first dielectric layer in contact with upper portions of the two vertical surfaces of the semiconductor fin-shaped structure, a dielectric charge trapping layer on the first dielectric layer, and a second dielectric layer on the dielectric charge trapping layer, the second patterned cap layer being between the multilayer charge trapping layer and the semiconductor fin shaped structure; (g) forming a control gate material layer on the multilayer charge trapping layer; (h) etching the control gate material layer to form at least a gate positioned on the two vertical surfaces of the semiconductor fin-shaped structure; and (i) implanting ions in the semiconductor fin-shaped structure on two sides of the gate to form at least a source/drain.