Patent ID: 7088605

Claim:
A FeRAM device, comprising: a memory array including a plurality of segmented BL/PL arrays, each segmented BL/PL array defining an I/O; and a plurality of charge transfer sense amplifiers, each charge transfer sense amplifier being associated with each I/O, each charge transfer sense amplifier further including a cross coupled latch that is connected between a memory cell access portion and a reference voltage generation portion of the charge transfer sense amplifier, wherein the reference voltage generation portion includes a reference bitline (Crb) that is coupled to a pair of dummy capacitance cells for generating a mid-voltage, each of the dummy capacitance cells is configured to be charged to an opposite polarized state, and the reference bitline (Crb) is further coupled to two parallel capacitors (2Cs), the pair of dummy capacitance cells, and the two parallel capacitors (2Cs) enabling the generation of a mid-voltage at a reference voltage (Vr).