Patent ID: 8054103

Claim:
A digital circuit comprising: a first logic gate to receive an enable signal and a select signal, and to generate a first logic output, the first logic output being generated as a logical combination of the enable signal and the select signal; a second logic gate to receive the enable signal and a logical complement of the select signal, and to generate a second logic output, the second logic output being generated as a logical combination of the enable signal and a logical complement of the select signal; and an output block to receive a first input signal, a second input signal, the first logic output and the second logic output, the output block to provide the first input signal as an output if the first logic output is at a first logic level and the second logic output is at a second logic level, the second input signal as the output if the first logic output is at the second logic level and the second logic output is at the first logic level, and to disable provision of either the first input signal or the second input signal as the output if each of the first logic output and the second logic output is at the second logic level, wherein the output block, in response to a change in the value of the first logic output from the first logic level to the second logic level at a first time instance, disables the first input signal from being provided as the output at a second time instance synchronous with an active edge of the first input signal, and wherein the output block, in response to a change in the value of the second logic output from the second logic level to the first logic level at a third time instance, provides the second input signal as the output at a fourth time instance synchronous with an active edge of the second input signal.