Patent ID: 7812407

Claim:
A memory device comprising: an upper row of upper memory cells, each of the upper memory cells having a first N-type active region, a second N-type active region, and a P-type active region interposed between the first N-type active region and the second N-type active region of the upper memory cell; a lower row of lower memory cells, each of the lower memory cells having a first N-type active region, a second N-type active region, and a P-type active region interposed between the first N-type active region and the second N-type active region of the lower memory cell; and a row of strapping cells, each of the strapping cells interposed between respective ones of the upper memory cells and the lower memory cells, each of the strapping cells comprising a first P-type strap, a second P-type strap, and an N-type strap; wherein the first P-type strap is interposed between the first N-type active region of the upper memory cell and the first N-type active region of the lower memory cell; wherein the second P-type strap is interposed between the second N-type active region of the upper memory cell and the second N-type active region of the lower memory cell; wherein the N-type strap is interposed between the P-type active region of the upper memory cell and the P-type active region of the lower memory cell; and wherein the N-type strap has an N-type active region, a first P-type active region, and a second P-type active region, the N-type active region of the N-type strap being interposed between the first P-type active region and the second P-type active region of the N-type strap, the first P-type active region of the N-type strap being a continuous active region with the P-type active region of the upper memory cell, and the second P-type active region of the N-type strap being a continuous active region with the P-type active region of the lower memory cell.