Patent ID: 8547148

Claim:
A semiconductor device comprising: a phase locked loop circuit including a voltage controlled oscillator having capacitors at oscillation nodes and consecutively controlled by an applied voltage; and a digital compensation circuit which variably controls the capacitors at the oscillation nodes of the voltage controlled oscillator in accordance with an input phase difference, wherein, during a normal operation mode of the phase locked loop circuit, the voltage controlled oscillator is dynamically calibrated based on a first signal having a first sensitivity generated by the phase locked loop circuit in response to the input phase difference, and a second signal having a second sensitivity generated by the digital compensation circuit in response to the input phase difference wherein the digital compensation circuit includes at least one or more digital phase comparators and at least one or more digital filters as an equivalent circuit of an analog control unit of the phase locked loop circuit, and changes the capacitors connected to the oscillation nodes of the voltage controlled oscillator whose VCO gain is determined by an applied voltage, and wherein the digital phase comparator includes at least one or more phase comparator units each having different input sensitivities for a reference clock and a divided clock and connected in parallel, and outputs an UP signal and a DOWN signal at respectively different sensitivities.