Patent ID: 8732443

Claim:
A first program processing device connected to a second program processing device provided externally to the first program processing device, comprising: a CPU structured to carry out predetermined processing according to a program; an internal memory structured to store the program and data generated by the CPU by carrying out the program, and a data acquiring circuit structured to acquire the program from a program memory to write into the internal memory before the CPU is activated; a control terminal connected to the data acquiring circuit structured to control whether or not to activate the data acquiring circuit based on a signal supplied from the outside of the first program processing device; a debug processing circuit structured to monitor at least one variable contained in the program to carry out a process in accordance with a result obtained in monitoring; wherein the signal provided from outside of the first program processing device is directly input to the data acquiring circuit without being input to the CPU; the data acquiring circuit is structured to write the program into the internal memory after the signal supplied from the outside is inputted in the control terminal and when the CPU is not yet executing any instructions; wherein the CPU is initialized and the program processing device activates the data acquiring circuit to load the program over a data transmission line and subsequently activates the initialized CPU in response to a first state of the control terminal, and subsequently initializes the CPU without activating the data acquiring circuit and activates the subsequently initialized CPU in response to a second state of the control terminal; and wherein the CPU, the internal memory, the data acquiring circuit, and the debug processing circuit are integrally mounted on a same semiconductor substrate.