Patent ID: 7187709

Claim:
An integrated circuit comprising: a plurality of configuration memory cells; programmable fabric circuitry coupled to the plurality of configuration memory cells, wherein the plurality of configuration memory cells are programmable to implement a circuit in the programmable fabric circuitry; a plurality of transceivers containing respective components having selectable values, said components being configured by said plurality of configuration memory cells, wherein one of said components is a loss of synchronization detector; wherein each configurable transceiver includes a configurable serializer and a configurable deserializer coupled to at least one of the configuration memory cells, wherein each serializer is configurable to transmit data at a selected bit rate, and each deserializer is configurable to receive data at the selected bit rate; wherein each transceiver has an input port that receives differential input signals and an output port that outputs differential output signals; and a plurality of signal paths coupling each configurable transceiver to a circuit implemented in the programmable fabric circuitry, at least a portion of each of said signal paths passing through said programmable fabric circuitry.