Patent ID: 7348828

Claim:
A voltage supplier of a semiconductor memory device, comprising: an internal voltage detection means for detecting a voltage level of an internal voltage and outputting a detection signal; a clock oscillation means for outputting a charge pumping clock signal by selecting one of a first clock signal that oscillates based on the detection signal and a second clock signal in response to a control signal generated by an active command, a read/write command or an auto refresh command; an internal voltage control means for supplying the second clock signal and the control signal to the clock oscillation means so that the clock oscillation means selectively operates in accordance with one of a data access mode and a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal, wherein the internal voltage control means includes: a frequency divider for dividing an external clock signal by a predetermined period corresponding to current consumed during the data access mode; a control signal generator for outputting the control signal in response to the active command, the read/write command and the auto refresh command; a clock signal output unit for outputting the external clock signal divided by the frequency divider as the second clock signal, which is activated by the control signal; and a transfer gate for transferring the external clock signal to the clock signal output unit, which is selectively enabled with the frequency divider.