Patent ID: 8498155

Claim:
A nonvolatile semiconductor memory device comprising: a substrate; device regions formed in the substrate to extend in a first direction which is parallel to a surface of the substrate; a memory cell array region including a plurality of memory cells disposed on the device regions; bit lines disposed above the substrate to extend in the first direction; a sense amplifier circuit electrically connected to the bit lines at ends of the bit lines on one side; and bit line contacts disposed on the device regions to electrically connect the device regions to the bit lines, wherein the memory cell array region includes first to N-th regions where N is an integer of two or more, a K-th region is located at a greater distance from the sense amplifier circuit than a (K−1)-th region, where K is an arbitrary integer of 2 to N, contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−1)-th region, and a width of each device region is constant in the memory cell array region.