Patent ID: 7920415

Claim:
A memory device comprising: a memory cell comprising phase change material; and bias circuitry adapted to apply a bias arrangement to the memory cell for storing a data value; wherein the bias arrangement comprises a first pulse pair if the data value is a first data value, the first pulse pair comprising a first pulse to cause a transition of an active region into an amorphous phase, and a second pulse to cause a transition of a first portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the first data value; wherein the bias arrangement comprises a second pulse pair if the data value is a second data value, the second pulse pair comprising a third pulse to cause a transition of the active region into the amorphous phase, and a fourth pulse to cause a transition of a second portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the second data value.