Patent ID: 7864601

Claim:
A semiconductor memory device, comprising: a preliminary signal generator configured to output a preliminary pipe-in signal, wherein the preliminary pipe-in signal is enabled when a read command is applied; a delay unit configured to delay the preliminary pipe-in signal and output the delayed preliminary pipe-in signal to match timing with output data; and a pipe-in signal generator configured to generate a plurality of pipe-in signals, wherein the pipe-in-signals are each enabled between a respective first enable point and a respective next enable point of the delayed preliminary pipe-in signal, wherein the pipe-in signal generator comprises: a plurality of shift registers each configured to transfer a signal stored therein to a next shift register in response to the delayed preliminary pipe-in signal; and a feedback shift register configured to feed back an output signal of the next to the last shift register in sequence among the plurality of shift registers to a first shift register in sequence of the plurality of shift registers. wherein signals stored in the plurality of shift registers are output as the plurality of pipe-in signals, and the plurality of shift registers are initialized by an initial value that is different than an initial value of the feedback shift register.