Patent ID: 7346760

Claim:
A data processing apparatus comprising: an instruction memory in which an instruction is stored; a data memory in which data is stored; an instruction decoder decoding a fetched instruction; a memory operation unit coupled to said instruction memory, said data memory and said instruction decoder, fetching an instruction stored in said instruction memory, and accessing said data memory according to a decode result of said instruction decoder; and an integer operation unit carrying out an integer operation according to a decode result of said instruction decoder, said instruction memory including a plurality of instruction memory banks, said memory operation unit generating a pipeline cycle corresponding to selection of an instruction memory bank to be accessed in a following pipeline cycle and a pipeline cycle corresponding to an access to an instruction memory bank without any accesses to other instruction memory banks to carry out low power consumption pipeline processing when a plurality of instructions are fetched from the plurality of instruction memory banks, wherein said instruction memory further includes a high speed instruction memory, and said memory operation unit generates a pipeline cycle corresponding to instruction readout to carry out a pipeline process when fetching an instruction from said high speed instruction memory, and performs a pipeline control having a same throughput and a different latency compared to the access to said instruction memory when accessing to said high speed instruction memory, said data memory includes a plurality of data memory banks, said memory operation unit generates a pipeline cycle corresponding to selection of a data memory bank and a pipeline cycle corresponding to data access to carry out a pipeline process when accessing said plurality of data memory banks, said data memory further includes a second bank select circuit decoding an address including a high order address to generate chip select signals of said plurality of data memory banks in order to divide said plurality of data memory banks into two different regions, and said second bank select circuit decodes an address including a low order address to generate chip select signals of said plurality of data memory banks so that a different data memory bank in said plurality of data memory banks is accessed when data at continuous addresses in said two different regions are accessed.