Patent ID: 7847288

Claim:
A semiconductor wafer comprising: a substrate; a plurality of integrated circuit chips formed on the substrate; a scribe line separating at least a first group of chips and a second group of chips; a test pattern formed on a portion of the scribe line, the test pattern comprising: an active portion of substrate region; a first contact structure coupled to a first portion of the active area, the first contact structure including a first landing plug structure coupled to a first metal line structure; a second contact structure coupled to a second portion of the active area, the second contact structure including a second landing plug structure coupled to a second metal line structure, and the second contact structure being adjacent to the first contact structure; at least two or more of MOS devices formed between the first contact structure and the second contact structure; a first MOS device from the at least two or more of MOS devices is coupled to the first diffusion; and an Nth MOS device from the at least two or more of MOS devices is coupled to the second diffusion, wherein N is an integer greater than 1; whereupon the first contact structure and the second contact structure are adapted to provide a resistance measurement value between the first contact structure and the second contact structure.