Patent ID: 8250421

Claim:
A clock controller circuit comprising: A. a clock input lead; B. a first flip-flop having a non-inverting clock input connected to the clock input lead, an input, a non-inverting output, and an inverting output connected to the input; C. a second flip-flop having an inverting clock input connected to the clock input lead, an input connected to the non-inverting output of the first flip-flop, and a non-inverting output; D. a first gate having a first input connected to the non-inverting output of the first flip-flop, a second inverting input connected to the clock input lead, and an output; and E. a second gate having a first input connected to the non-inverting output of the second flip-flop, a second non-inverting input connected to the clock input lead, and an output.