Patent ID: 8880856

Claim:
A device comprising: a processor including a conditional arithmetic logic unit and a main arithmetic logic unit, the processor to: determine a microinstruction to be used to process data received by the device, the conditional arithmetic logic unit to: select, based on the microinstruction, a first set of first input buses from a plurality of first input buses to determine a first input, select, based on the microinstruction, a second input bus from a plurality of second input buses to determine a second input, perform, based on the microinstruction, a first arithmetic logic operation on the first input and the second input to generate a first result and a condition code, the condition code indicating whether the first result satisfies a condition associated with the first arithmetic logic operation, and output the first result and the condition code to the main arithmetic logic unit via a third input bus, of a plurality of third input buses; and the main arithmetic logic unit to: select, based on the microinstruction, the third input bus, from the plurality of third input buses, to determine the first result as comprising a third input, select, based on the microinstruction, a second set of the first input buses from the plurality of first input buses to determine a fourth input, determine, based on the microinstruction, a second arithmetic logic operation; perform the second arithmetic logic operation on the third input and the fourth input to generate a second result, and output, based on the microinstruction and the condition code, the second result, the data received by the device being processed based on the second result.