Patent ID: 6995795

Claim:
A method for reducing dark current within an interline CCD image sensor comprising the steps of: providing the interline CCD image sensor with a matrix of pixels arranged in a plurality of rows and columns with a vertical shift register allocated for each of the columns and at least one horizontal shift register operatively coupled to the vertical shift registers, wherein each of the columns of pixels are formed with the vertical shift registers having a plurality of phases allocated for each of the pixels and a plurality of gate electrodes of the vertical shift register for each of the pixels, and clocking means for causing the transfer of charge from the pixels to the vertical shift registers and through the horizontal shift register; applying, at a first time period, a first set of voltages to the phases of the gate electrodes of the vertical shift registers sufficient to accumulate holes substantially at a surface of the image sensor in the vertical shift register, beneath each gate electrode; applying, at a second time period, a second voltage to a first set of the gate electrodes while simultaneously applying a more positive voltage to a second set of gate electrodes, the second voltage being of sufficient potential so holes that were accumulated beneath the second set of gate electrodes during the first time are collected and stored beneath the first set of gate electrodes during the second time period; applying, at a third time period, a third voltage to the second set of gate electrodes while simultaneously applying a more positive voltage to the first set of gate electrodes, such that the previously accumulated holes beneath the first set of gate electrodes are transferred beneath the second set of gate electrodes; returning the first and second sets of gate electrode voltages to their levels at the first time period; and applying an additional positive voltage pulse to a first set of gate electrodes during a period of more positive voltage.