Patent ID: 7871924

Claim:
A semiconductor manufacture method comprising steps of: (a) forming a first interlayer insulating film made of insulating material over an underlying substrate; (b) forming a via hole through the first interlayer insulating film; (c) filling a conductive plug made of copper or alloy containing mainly copper in the via hole by a plating method; (d) forming a second interlayer insulating film made of insulating material over the first interlayer insulating film with the conductive plug being filled in; (e) forming a wiring groove in the second interlayer insulating film, the wiring groove exposing an upper surface of the conductive plug; and (f) filling a wiring made of copper or alloy containing mainly copper in the wiring groove by a plating method using plating solution different from plating solution to be used at the step (c) in a total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine.