Patent ID: 7737483

Claim:
A nonvolatile memory array comprising: a string of floating gate memory cells extending between a first doped region of a substrate and a second doped region of the substrate; a dielectric material over the substrate including a plurality of layers, a first layer of the dielectric material has a top surface and bottom surface; a first contact including a first portion of a first material and a second portion of a second material that is different than the first material, the first portion has a bottom surface that is aligned with the bottom surface of the first layer of the dielectric material, the second portion has a top surface that is aligned with the top surface of the first layer of the dielectric material, the first portion in contact with the first doped region of the substrate, the second portion overlying the first portion, the first contact is a bitline contact, the second portion is self-aligned to the first portion; a second contact including a third portion of the first material and a fourth portion of the second material, the third portion in contact with the second doped region of the substrate, the third portion has a bottom surface that is aligned with the bottom surface of the dielectric material, the fourth portion has a top surface that is aligned with the top surface of the dielectric material, the fourth portion overlying the third portion; and a common source line above the second contact, the second contact electrically connects to the common source line.