Patent ID: 7741196

Claim:
A method of manufacturing a semiconductor wafer for dicing, the method comprising: providing the semiconductor wafer including a substrate having a plurality of upper layers and a plurality of die areas, wherein adjacent die areas are separated by a path for a dicing tool; fabricating, within each path, a pair of spaced apart lines, each of the spaced apart lines defines a dicing edge of the path and comprises a plurality of trenches having ends, wherein the trenches are arranged end to end such that apexes of longitudinally aligned trenches point towards each other, and wherein a horizontal cross-section of each end of consecutive trenches has an acuate shape that promotes propagation of cracks therebetween during dicing, and wherein each trench extends between a top surface of the semiconductor wafer and the substrate; and filling each trench with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.