Patent ID: 7795910

Claim:
A field-programmable gate-array (FPGA) comprising: a first memory cell having (i) a plurality of states, (ii) a first end, and (iii) a second end; a first configurable logic block (CLB) having an output directly coupled to the first end of the first memory cell; a second memory cell having (i) a plurality of states, (ii) a first end, and (iii) a second end; and a second CLB having an input directly coupled to the first end of the second memory cell, wherein the output of the first CLB communicates with the input of the second CLB via (i) a second end of the first memory cell and (ii) the second end of the second memory cell based on (i) the state of the first memory cell and (ii) a state of the second memory cell, and wherein each of the first memory cell and the second memory cells includes a single-transistor memory cell of nonvolatile memory.