Patent ID: 7394886

Claim:
A semiconductor device with a latency counter, the latency counter configured to hold an internal command for a predetermined period in accordance with a predetermined latency by using an internal clock signal to produce a latency timeout signal, the latency counter comprising: a single cyclic signal generator configured to cyclically produce 0-th to n-th base signals based on the internal clock signal; and a command delay circuit comprising 0-th to n-th latch elements and configured to latch the internal command by means of a p-th latch element (p is an integer; 0≦p≦n) in response to a q-th base signal (q is an integer; 0≦q≦n) and to output the latched internal command corresponding to the latency timeout signal therefrom in response to a r-th base signal (r is an integer; 0≦r≦n), where r=q+s if q+s≦n while r=q+s−(n+1) if q+s>n, s being a natural number equal to or less than n.