Patent ID: 8664980

Claim:
Frequency synthesizer for generating a low noise and low jitter time base of a reference signal s ref with a frequency f ref , wherein the time base comprises a first output signal s 1 with a frequency f 1 and a second output signal s 2 with a frequency f 2 , comprising: a first fractional divider with the division factor T 1 for generating the first output signal s 1 from the reference signal S ref , a second fractional divider with the division factor T 2 for generating the second output signal s 2 from the reference signal s ref , and a controller for periodically-clocked switching of the first fractional divider between division factors T 1 and T 1 +1 using the first output signal s 1 and for periodically-clocked switching of the second fractional divider between division factors T 2 and T 2 +1 using the second output signal s 2 wherein a first incrementer having a preset increment I 1 and a preset end value E 1 controls the first fractional divider and wherein a second incrementer having a preset increment I 2 and a present end value E 2 controls the second fractional divider, wherein each of the incrementers is clocked from the output signal s 1 , s 2 of each fractional divider, wherein, when the respective end value E 1 , E 2 has been reached, an end signal e is output and the incrementers are reset to a carryover value as a new starting value and the end signal e is switched between the division factors of the fractional dividers so that the switching sequence of the end signal e is periodic with the output signal s 1 , s 2 of the fractional divider.