Patent ID: 7233176

Claim:
A CMOS input buffer supporting multiple I/O standards, comprising: a pair of NMOS and PMOS differential receivers each having a first input connected to the input pad and a second input connected to a reference voltage, the PMOS and NMOS differential receivers configured to support general purpose standards and to support high speed standards; a first multiplexer connected to a control terminal of a current sink of the NMOS differential receiver and having a first input connected to the positive supply terminal; a second multiplexer connected to the control terminal of the current source of the PMOS differential receiver and having a first input connected to a negative supply terminal or ground; an inverter connected to a combined output of said PMOS differential receiver and the NMOS differential receivers and having an output connected to a second input of the first and second multiplexer; and a configuration storage bit circuit coupled to the first and second multiplexer for selecting the inputs of the first and second multiplexer.