Patent ID: 8329526

Claim:
A method, comprising: forming a gate electrode structure of a transistor above a semiconductor region of a semiconductor device, said gate electrode structure comprising a gate insulation layer comprising a high-k dielectric material, a metal-containing cap material formed on said gate insulation layer, an electrode material formed above said cap material, a dielectric cap layer formed above said electrode material and a sidewall spacer structure; forming a sacrificial fill material above said semiconductor region and covering said gate electrode structure; removing a portion of said sacrificial fill material so as to expose at least a top surface of said dielectric cap layer and a side surface of said sidewall spacer structure; removing said dielectric cap layer from above said electrode material in the presence of a remaining portion of said sacrificial fill material; removing said sacrificial fill material; forming drain and source regions in said semiconductor region after removing said sacrificial fill material; and forming a strain-inducing dielectric material above said drain and source regions and said gate electrode structure.