Patent ID: 8912589

Claim:
An apparatus comprising: a stack comprising a number of levels of semiconductor material and a number of levels of dielectric material, each of the levels of semiconductor material being doped on at least one respective sidewall of the semiconductor material, a substantial remainder of each of the levels of semiconductor material being doped with a material having a predominant charge carrier that is opposite that of the dopant used on the at least one respective sidewall, each of the levels of semiconductor material being separated from a respective adjacent one of the levels of semiconductor material by at least a respective one of the levels of dielectric material, adjacent ones of the levels of semiconductor material being coupled together by a pillar of semiconductor material, at least one end of the stack being formed into a staircase structure with overlying levels of the stack on the at least one end being stepped back from underlying ones of the number of levels of semiconductor material thereby forming the staircase structure, the at least one respective sidewalls each being coupled to a separate respective sidewall contact line at an appropriate level of the staircase structure, the remainder of each of the levels of semiconductor material being coupled to a separate respective body contact line at an appropriate level of the staircase structure, a respective string of memory cells being formed along each of the levels of semiconductor material.