Patent ID: 7663956

Claim:
A semiconductor memory device which performs a refresh operation sequentially for a word line to be selected based on a row address when receiving a refresh request at a predetermined interval, comprising: a memory cell array divided into M (M is an integer greater than or equal to 2) banks; a refresh address counter for sequentially outputting a count value corresponding to the word line to be refreshed in response to the refresh request; and a row address converter for supplying row addresses different from one another in at least two banks among the M banks by converting the count value, wherein in at least one of a plurality of refresh cycles, a predetermined word line of each of the M banks and another word line of at least one of the banks which are less than M are refreshed, those word lines are refreshed by the refresh address counter and the row address converter, and a total number P of selected word lines to be refreshed satisfies a relation M<P<2M.