Patent ID: 7281074

Claim:
A data processing system, comprising: a processor; a memory coupled to the processor selected from a group consisting of a DRAM (dynamic RAM) and SRAM (static RAM); and a universal serial bus (USB) controller coupled to the processor and the memory, the USB controller including a local memory to cache at least one activity descriptor of at least a portion of a periodic schedule having a plurality of frames stored in the memory, the USB controller deferring to service an active USB device described by one of the activity descriptors until a corresponding frame is scheduled to be serviced subsequently, using an associated activity descriptor cached in the local memory, wherein the activity descriptors include at least one interrupt descriptor having information required by the USB controller to generate an interrupt transfer for the corresponding active USB device, and wherein the USB controller further comprises an interrupt state register to asynchronously store an activity state of at least a portion of one or more USB devices indicating whether a USB device has an interrupt pending.