Patent ID: 8652956

Claim:
A method of forming gate electrode structures, the method comprising: forming a gate layer stack above a first active region and a second active region; processing said gate layer stack so as to obtain a greater height of said gate layer stack selectively above said first active region; patterning said processed gate layer stack to form a first gate electrode structure above said first active region and a second gate electrode structure above said second region; forming an interlayer dielectric material above said first and second active regions; planarizing said interlayer dielectric material so as to remove a first sub-layer of said interlayer dielectric material from above said first active region and preserve a portion of said first sub-layer above said second active region; forming a first gate opening by removing at least a portion of said first gate electrode structure; filling said first gate opening with a first electrode material, said first electrode material comprising a first work function adjusting species; after filling said first gate opening, forming a second gate opening by removing at least a portion of said second gate electrode structure; and filling said second gate opening with a second electrode material, said second electrode material and comprising a second work function adjusting species that differs from said first work function adjusting species.