Patent ID: 7450453

Claim:
A semiconductor memory device, comprising: an amplifying unit for amplifying a voltage difference between a bit line pair; a power supply driver for supplying a power to the amplifying unit in response to a second driving signal; a control unit for generating a first driving signal of the power supply driver in response to an amplifying unit enable signal; a selection signal generation unit for generating a plurality of selection signals for determining a turning-on transition speed of the power supply driver; a power supply driver driving unit for generating the second driving signal according to the first driving signal and the plurality of selection signals; wherein the power supply driver driving unit includes; a plurality of logic combination units, each logic combination unit performing a logic operation with a corresponding selection signal and the first driving signal; and a power driving unit for receiving the first driving signal to drive an output node, wherein the selection signal generation unit includes: a test mode enable signal generation unit for generating a test mode enable signal in order to perform a test operation; a fuse unit for generating a fuse signal according to cutting or not cutting of a fuse; and an output unit for activating the plurality of selection signals when at least one of the test mode enable signal and the fuse signal is activated.