Patent ID: 8259520

Claim:
An apparatus, comprising: a back-end-of-the-line (BEOL) primary memory array including a plurality of BEOL memory cells configured to change resistivity; a BEOL secondary memory array including another plurality of BEOL memory cells configured to change resistivity; and a front-end-of-the-line (FEOL) restoration module electrically coupled with the primary memory array and the secondary memory array, the restoration module being configured to replace a defective BEOL memory cell positioned in the primary memory array with a BEOL memory cell positioned in the secondary memory array, wherein the restoration module is configured to identify a defective BEOL column that is associated with the defective BEOL memory cell, and use another BEOL column that is associated with the BEOL memory cell, wherein the defective BEOL column and the another BEOL column reside on different memory planes.