Patent ID: 7400547

Claim:
A semiconductor integrated circuit, comprising: a sense amplifier which senses and outputs data read out from memory cells connected to word lines and bit lines, the sense amplifier outputting data in accordance with a potential difference between the potential on the bit line and the potential on a reference bit line; and a read-out control circuit which has a standby state consuming minimum necessary power and a read state reading out the memory cells, and controls read-out of the memory cells; wherein the read-out control circuit includes: a bit line switching circuit which switches whether or not to transmit a potential on the bit line to an input terminal of the sense amplifier; a first switching control circuit which controls the bit line switching circuit to prevent the potential on the bit line from being transmitted to the input terminal of the sense amplifier during a period of the standby state and a predetermined period after the standby state is released; and a second switching control circuit which controls the bit line switching circuit to prevent the potential on the reference bit line from being transmitted to the corresponding input terminal of the sense amplifier during the period of the standby state and a predetermined period after the standby state is released.