Patent ID: 8773881

Claim:
A method of forming a memory device, the method comprising: providing a substrate; forming a source layer on the substrate; forming a channel layer over the source layer, the channel layer having a doping type different from a doping type of the source layer; forming a drain layer over the channel layer, the drain layer having a doping type different from a doping type of the channel layer; and patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6 F 2 , wherein patterning the source, channel, and drain layers comprises: forming a plurality of generally parallel isolation trenches intersecting the source, channel, and drain layers; depositing a dielectric material into the plurality of isolation trenches; and planarizing the dielectric material such that a top surface of the dielectric material is substantially coplanar with a top surface of the drain layer.