Patent ID: 8059473

Claim:
A non-volatile memory device comprising: a device isolation layer formed to define a plurality of active regions on a semiconductor substrate; a gate insulation layer formed on the respective active regions; a floating gate formed on the respective gate insulation layers; a sensing line formed on the gate insulation layer and the floating gate to cross over the active regions; a wordline formed on a sidewall of the floating gate and the gate insulation layer to cross over the active regions, the wordline being opposite to the sensing line, wherein the sensing line comprises a top sensing line crossing over the floating gate and a sidewall sensing line crossing over the sidewall of the floating gate and the gate insulation layer opposite to the wordline; an intergate dielectric interposed between the sensing line and the floating gate; a tunnel insulation layer interposed between the wordline and the floating gate; and a spacer insulation pattern interposed between the top sensing line and the sidewall sensing line and between the top sensing line and the wordline.