Patent ID: 7623393

Claim:
A semiconductor memory apparatus comprising: a reference voltage generator that generates a reference voltage; a bank activating signal generator that outputs zeroth to N-th bank activating signals for activating a plurality of banks, where N is a natural number that is equal to or greater than 1; a driving controller that decodes the zeroth to N-th bank activating signals to output zeroth to N-th driving control signals; and an internal voltage generator that generates an internal voltage in response to the reference voltage and the driving control signals, wherein the internal voltage generator includes a plurality of internal voltage generating units and respective ones of the internal voltage generating units are configured to correspond to respective ones of the banks, wherein, when at least one of the zeroth to N-th bank activating signals is activated, at least one of the zeroth to N-th driving control signals is activated, wherein an activated bank receives the internal voltages from the internal voltage unit of the corresponding activated bank and one of the internal voltage units of the non-selected banks.