Patent ID: 7636267

Claim:
A semiconductor memory device employing shared type sense amplifiers, the semiconductor memory device comprising a control circuit for placing in a high impedance state a first bit line connected to a first sense amplifier arranged on a first side of a selected memory array, during placing in a low impedance state a second bit line connected to a second sense amplifier arranged on a second side of the selected memory array opposing the first side, wherein the first bit line and the second bit line are arranged adjacent to each other and cell data is written into memory cells so that the first and second bit lines assume opposite logic levels, and wherein, in a state where cell data is amplified by the first and second sense amplifiers, a first transfer gate arranged between the first sense amplifier and the first bit line is turned OFF while a second transfer gate arranged between the second sense amplifier and the second bit line is turned ON, then cell data is read from the memory cells and a bit line to bit line short is detected by detecting an inversion of a written logic level.