Patent ID: 7084452

Claim:
A semiconductor device with an OTP ROM formed over a semiconductor substrate including a memory cell area and a peripheral circuit area, the semiconductor device comprising: a MOS transistor having a floating gate electrode, the MOS transistor being disposed at the memory cell area; a peripheral capacitor disposed in the peripheral circuit area and including a lower capacitor electrode, a dielectric film, and an upper capacitor electrode which are stacked in the order named; an OTP ROM capacitor having a lower electrode, an upper intermetal dielectric, and an upper electrode which are stacked in the order named, the OTP ROM capacitor being disposed over the MOS transistor; and a floating gate plug connecting the floating gate electrode with the lower electrode, a lower intermetal dielectric formed below the upper intermetal dielectric, wherein the lower intermetal dielectric has an OTP ROM opening exposing the top surface of the lower electrode and a capacitor opening exposing the top surface of lower capacitor electrode, wherein the floating gate electrode, the floating gate plug, and the lower electrode constitute a conductive structure which is electrically insulated from surrounding components, wherein the upper electrode is formed in the OTP ROM opening and the upper capacitor electrode is formed in the capacitor opening.