Patent ID: 8525843

Claim:
A circuit, comprising: an input terminal configured to receive an incoming fragment; a depth test buffer configured to store a current depth value; a control circuit coupled to the depth test buffer and configured to enable and disable the depth test buffer; a depth test stage coupled to said depth test buffer and configured to compare the current depth value with a depth value associated with the incoming fragment and to define a resulting fragment; a test stage structured to receive and test the resulting fragment from the depth test stage and to generate a retained fragment; a further depth test stage configured to perform a further depth test on the retained fragment upon disabling of the depth test buffer by the control circuit when testing is taking place on a previous fragment having planar coordinates the same as planar coordinates of the incoming fragment; and a buffer writing stage coupled to the further depth test stage and configured to update the current depth value with a depth value of the retained fragment received from the further depth test stage.