Patent ID: 8302059

Claim:
A non-transitory computer-readable medium that stores computer code arranged to, when executed on a computer, implement a method of designing a power switch block for an integrated circuit layout in a predefined integrated circuit technology, the power switch block including a segment having a plurality of spaced parallel conductors each having a predefined height in said technology, a stack of a first power switch of a first conductivity type and a pair of drivers for respectively driving the first power switch and a second power switch, said drivers having predefined dimensions in said technology including a predefined driver height and a predefined driver width, and the second power switch of a second conductivity type, the method comprising: providing respective predefined width/length ratios for said power switches; determining a total height of the segment from the sum of the predefined heights of the spaced parallel conductors and respective spacings between said spaced parallel conductors, determining the height of a first transistor from the difference between a total height and the predefined driver height; determining a width of the first transistor from the combined predefined widths of the pair of drivers; optimizing the first power switch layout within its determined height and width based on its predefined width/length ratio; and optimizing the second power switch layout based on its predefined width/height ratio.