Patent ID: 7034590

Claim:
A delay locked loop (DLL) circuit, comprising: a phase detector comprising a first detector that compares an external clock signal with a first feedback signal to generate a first detection signal corresponding to a phase difference between the external clock signal and the first feedback signal, and a second detector that compares the external clock signal with a second feedback signal to generate a second detection signal corresponding to a phase difference between the external clock signal and the second feedback signal, wherein the phase detector further comprises a delay unit that receives as input the first feedback signal and delays the first feedback signal to generate the second feedback signal as a delayed version of the first feedback signal; a delay controller that generates a first delay control signal or a second delay control signal, based on the first and second detection signals output from the phase detector; a coarse-lock unit that delays the external clock signal by a first phase delay in response to the first delay control signal; and a fine-lock unit that delays the external clock signal by a second phase delay, which is smaller than the first phase delay, in response to the second delay control signal.