Patent ID: 8566773

Claim:
A computer-implemented method comprising: retrieving a circuit board file that identifies a plurality of power plane thru pin locations and one or more power plane layers; selecting one of the plurality of power plane thru pin locations and one of the one or more power plane layers; identifying one or more electrical properties corresponding to an electronic component assigned to the selected power plane thru pin location; computing, by one or more processors, a conductive material exclusion amount based upon the one or more identified electrical properties, wherein the conductive material exclusion amount indicates an amount of area on the selected power plane layer to exclude substantially conductive material; creating, by one or more of the processors, a thermal relief pattern based upon the computed conductive material exclusion amount, wherein the thermal relief pattern identifies one or more conductive material voids on the selected power plane layer to exclude the substantially conductive material in proximity to the selected power point thru pin location; and adjusting the thermal relief pattern in response to determining that one or more of the conductive material voids affects one or more data signals that propagate along one or more signal tracks in proximity to the selected power plane thru pin location.