Patent ID: 7528627

Claim:
For an integrated circuit (IC), a shifter circuit for receiving an n-bit data set and outputting the n-bit data set shifted an amount of zero through m bits, wherein n and m are integer values and m is less than n, the shifter comprising: a plurality of multiplexers comprising input, output, and select terminal sets, each particular multiplexer shifting a different bit of the n-bit data by m bits when the particular multiplexer (i) receives a different ordering of the n-bit data set at the input terminal set of the particular multiplexer, (ii) receives a set of control signals at the select terminal set of the particular multiplexer, wherein the set of control signals comprises at least one user signal generated within the IC, and (iii) outputs a particular input of the ordered n-bit input data set based on the set of control signals at the output terminal set of the multiplexer; wherein the outputs of the plurality of multiplexers represent the n-bit data shifted by m bits.