Patent ID: 7844797

Claim:
A computer system for executing a plurality of instructions having a program order, the computer system comprising: a memory subsystem; and a superscalar microprocessor, comprising: a register file including a plurality of temporary buffers and a plurality of real registers; a superscalar control block configured to determine whether an instruction from the plurality of instructions is ready to issue and to issue instructions that are ready to issue, the superscalar control block being further configured to issue instructions without regard to the program order and to issue more than one instruction per clock cycle; a plurality of functional units, each of the functional units being configured to execute an operation corresponding to an issued instruction, the plurality of functional units including at least one functional unit that is further configured to provide result data for an executed operation to one of the temporary buffers of the register file, the plurality of functional units further including an address generation unit configured to generate a memory address for a memory instruction included in the plurality of instructions, wherein the superscalar control block is configured to issue at least one memory instruction to the address generation unit out of the program order; retirement logic configured to move the result data from the temporary buffers of the register file to the real registers of the register file, thereby retiring instructions, the retirement logic being further configured to retire, in accordance with the program order, more than one instruction per clock cycle; and a load store unit configured to receive memory addresses generated by the address generation address generation unit and to execute memory operations to the memory subsystem corresponding to the memory instructions, thereby transferring data between the register file and the memory subsystem, wherein executing a memory operation includes making at least one memory request, the load store unit being further configured to make at least one load request out of the program order so that the at least one load request is made before a first memory request, wherein the first memory request corresponds to a first memory instruction of the plurality of instructions and the at least one load request corresponds to a second memory instruction of the plurality of instructions, wherein the first memory instruction precedes the second memory instruction in the program order, the load store unit including: an address path including a plurality of address registers configured to store memory addresses generated by the address generation unit, the address path being further configured to provide a memory address from one of the address registers to the memory subsystem during a memory operation; and a data path configured to receive load data from the memory subsystem and to transfer the received load data to the register file during a load operation.