Patent ID: 6967370

Claim:
An integrated semiconductor circuit, comprising: plurality of memory cells each memory cell having a selection transistor and a storage capacitor, each memory cell being driven electrically by bit lines and word lines; and a plurality of electrical contact structures being arranged at the level of the word lines, the contact structures electrically connecting the bit lines to the selection transistors of the memory cells the contact structures leading past the word lines and being insulated from the word lines by lateral insulations, and in each case two, mutually adjacent bit lines being connected to a common signal amplifier, wherein additional contact structures are provided, the additional contact structures leading past the word lines, the additional contact structures representing dummy contacts, in which case, for each contact structure which proceeds from a bit line leads past a word line, and connects the bit line to a memory cell, a dummy contact, which proceeds from the adjacent bit line connected to the signal amplifier and leads past the same word line as the respective contact structure is provided.