Patent ID: 8885792

Claim:
A shift register, comprising: a first thin film transistor, having a gate connected to a first clock signal input, and a source connected to a signal input; a second thin film transistor, having a gate connected to a drain of the first thin film transistor, a drain connected to a signal output, and a source connected to a second clock signal input, wherein a clock signal input from the second clock signal input and a clock signal input from the first clock signal input are inverted to each other; a third thin film transistor, having a gate connected to the drain of the first thin film transistor, a source connected to a high voltage signal input, and a drain connected to a reset voltage controlling unit; a fourth thin film transistor, having a gate connected to a connection point of the drain of the third thin film transistor and the reset voltage controlling unit, a source connected to the high voltage signal input, and a drain connected to the signal output; a first capacitor, being connected between the signal output and the gate of the second thin film transistor; and the reset voltage controlling unit, being connected to a low voltage signal input, the gate of the fourth thin film transistor and the drain of the third thin film transistor, controlling the gate voltage of the fourth thin film transistor, so that the gate voltage of the fourth thin film transistor is pulled down to a low level corresponding to a voltage input from the low voltage signal input when the signal input from the first clock signal input is at low level, the signal input from the second clock signal input is at high level and the signal input from the signal input is at high level, and wherein the reset voltage controlling unit comprises: a fifth thin film transistor, having a gate connected to a charge pump unit, a source connected to the drain of the third thin film transistor and the gate of the fourth thin film transistor respectively, a drain connected to the low voltage signal input; and the charge pump unit, being connected to the gate of the fifth thin film transistor and the low voltage signal input, dropping the gate voltage of the fifth thin film transistor to such a voltage during a predetermined period, said voltage enables the gate voltage of the fourth thin film transistor to be pulled down by the fifth thin film transistor to a low level corresponding to a voltage input from the low voltage signal input when the signal input from the first clock signal input is at low level, the signal input from the second clock signal input is at high level and the signal input from the signal input is at high level.