Patent ID: 8437262

Claim:
A non-transitory memory storage device for storing instructions, the instructions comprising: one or more instructions which, when executed by a processor, cause the processor to detect a fault condition for a link aggregation group (LAG) link included in a plurality of links of a LAG; one or more instructions which, when executed by the processor, cause the processor to receive, during a particular period of time, network data for the LAG; one or more instructions which, when executed by the processor, cause the processor to distribute respective portions of the network data to the plurality of links, a particular portion of the network data being distributed to the LAG link; one or more instructions which, when executed by the processor, cause the processor to delay, based on detecting the fault condition and until after the particular period of time, transmission, by the LAG link, of the particular portion of the network data, other links, of the plurality of links in the LAG, transmitting other respective portions of the received network data during the particular period of time, the one or more instructions to delay transmission, by the LAG link, of the particular portion of the network data including: one or more instructions to enable, after detecting the fault condition, a hold-down timer to disallow traffic onto the LAG link for a hold-down time, one or more instructions to determine, during the hold-down time, that the fault condition is caused by the LAG link, and one or more instructions to enable, after the hold-down time and based on determining that the fault condition is caused by the LAG link, a hold-up timer to delay transmission, by the LAG link, of the particular portion of the network data until after the particular period of time; and one or more instructions which, when executed by the processor, cause the processor to perform maintenance on the LAG link during the particular period of time.