Patent ID: 7711010

Claim:
A phase-locked loop for maintaining system synchronization between a transmitter and a receiver in a wireless communications system of packet transmission, said phase-locked loop comprising: an oscillator having an oscillation frequency controlled by a control signal for generating a clock for receiver system operation; a first counter operative directly in response to the clock for receiver system operation for autonomously counting the clock recursively at a period of incoming system timing information estimated to generate a first count value every period of the incoming system timing information; a second counter for counting a circuit clock of the receiver distinct from the clock for system operation to generate a second count value, the second count value being reset in response to the first count value; a holding circuit for holding the second count values corresponding to at least two packet intervals and detecting the system timing information transmitted from the transmitter; a difference circuit for comparing a temporally previous second count value held by said holding circuit with a temporally posterior second count value; an adder/subtractor for subtracting from or adding to an output of said difference circuit a value equivalent to an estimated period of incoming system timing information which is estimated with the circuit clock taken into account if the output of said difference circuit is, respectively, larger or smaller than a value expected with the system synchronization taken into account; a phase difference detector for changing the value obtained by said adder/subtractor to zero to output the resulting zero if the value obtained by said adder/subtractor is larger than a reference value expected with the system synchronization taken into account, and otherwise directly outputting the value obtained by said adder/subtractor; and an integrator for integrating an output of said phase difference detector, on acquisition of the system timing information from the transmitter to apply a result of integration to said oscillator as the control signal, whereby the system synchronization of the receiver with the transmitter is substantially maintained through packet dropout.