Patent ID: 7822591

Claim:
A logic circuit model implemented by a computer as a logic circuit model conversion apparatus comprising: a first analysis unit which analyzes the logic circuit model in which a logic circuit of a register transfer level has been coded and outputs simultaneous blocks executed at the same time and an analysis result; a creating unit which creates a common execution frequency group that is a set of codes whose execution frequency becomes common, based on the simultaneous blocks and the analysis result; a second analysis unit which analyzes the common execution frequency group and creates a formula of a general term of a numeric sequence, to derive a predetermined value of each register, wherein values of the register at a plurality of times are regarded as the numeric sequence; a third analysis unit which analyzes a mutual relationship between the common execution frequency groups and derives an execution frequency of each common execution frequency group up to a predetermined time; and a deriving unit which derives a value of each of the registers at the predetermined time from the formula of the general term and the execution frequency, wherein the simultaneous blocks are created by sequentially segmenting all codes for every code equivalent to WAIT and DELAY.