Patent ID: 7570715

Claim:
A digital signal receiving circuit, comprising: a peak detector which maintains a peak level by following a rise in potential of an input signal and resets the peak level being maintained when a first reset signal is provided; a bottom detector which maintains a bottom level by following a drop in potential of the input signal and resets the bottom level being maintained when a second reset signal is provided; a delayed peak detector which maintains a delayed peak level by following the rise in potential of the input signal at timing lagged behind the peak detector; a delayed bottom detector which maintains a delayed bottom level by following the drop in potential of the input signal at timing lagged behind the bottom detector; a peak difference detector which outputs a peak difference by detecting a difference between the peak level and the delayed peak level; a bottom difference detector which outputs a bottom difference by detecting a difference between the bottom level and the delayed bottom level; a reset portion which outputs the second reset signal when a level difference between the peak level and the bottom level is larger than a predetermined value set corresponding to the amplitude of the input signal and the peak difference exceeds a pre-set allowable peak difference, and outputs the first reset signal when the level difference is larger than the predetermined value and the bottom difference exceeds a pre-set allowable bottom difference; and a comparator which regenerates a digital baseband signal by comparing the input signal with reference potential obtained from the peak level and the bottom level.