Patent ID: 8344429

Claim:
A memory cell array comprising: gate lines disposed over a substrate, the gate lines are disposed about parallel to each other and disposed in a same plane parallel to the substrate, the gate lines are spaced apart by a first minimum distance, wherein the gate lines are coupled to control gates of memory cells of the memory cell array; first metal lines disposed in a first metal level, the first metal lines coupled to a first set of the gate lines, the first metal lines spaced apart by a second minimum distance, wherein each of the first metal lines is coupled with the first set of the gate lines in at least two locations laterally separated along the length of the first set of the gate lines; and second metal lines disposed in a second metal level, the second metal lines coupled to a second set of the gate lines, the second metal lines spaced apart by a third minimum distance, wherein the first minimum distance is smaller than the second or third minimum distance, and wherein the gate lines are oriented along a same horizontal direction as the first metal lines and the second metal lines, the horizontal direction being a direction parallel to a major surface of the substrate.