Patent ID: 7240255

Claim:
A system for testing memory arrays in circuit blocks on an integrated circuit, each of said memory arrays having an array address, said system including: a serial bus having a series of stages, one stage being associated with each of said circuit blocks, design for test assist logic (DAL) associated with each of said circuit blocks, said DAL being connected to the associated stage of said serial bus, and being associated with the memory arrays in the circuit block with which said DAL is associated, a BIST controller connected to a first stage of said serial bus, said BIST controller issuing array addresses and associated test commands on said serial bus, a comparator connected to the final stage of said serial bus, and control circuitry in each DAL, said control circuitry being adapted: to recognize the array address of the associated memory arrays, to execute test commands associated with the recognized address to test the associated arrays, the data resulting from said tests being gated to said serial bus together with commands for transmission to said comparator, said comparator adapted to compare said data from said arrays, to expected values of said data to determine if said arrays are operating satisfactorily.