Patent ID: 7368969

Claim:
A level shift circuit comprising: a shift circuit for receiving an input signal and level-shifting the voltage of the input signal to generate a level-shifted signal, the shift circuit including; first and second transistors having the same polarity, wherein the sources of the first and second transistors are connected to a first power supply having a first voltage, the gate of the first transistor being connected to the drain of the second transistor, and the gate of the second transistor being connected to the drain of the first transistor; third and fourth transistors having a polarity opposite of the polarity of the first or second transistor, wherein the sources of the third and fourth transistors are connected to a second power supply having a second voltage that is lower than the first voltage; a fifth transistor connected between the first transistor and the third transistor and having the same polarity as the third transistor; a sixth transistor connected between the second transistor and the fourth transistor and having the same polarity as the fourth transistor; a voltage generation circuit having a node provided between the first power supply and a third power supply having a third voltage lower than the first voltage and higher than the second voltage and connected to the gates of the fifth transistor and the sixth transistor for generating a gate control voltage, which is provided to the gates of the fifth transistor and the sixth transistor based on the first voltage, wherein the voltage generation circuit has a first terminal, which is connected to the first power supply, and a second terminal, which is connected to the third power supply, and wherein the voltage generation circuit divides the differential voltage between the first voltage and the third voltage and adds the third voltage to the divided voltage to generate the gate control voltage at the node; and an input circuit connected between the second power supply and the third power supply for receiving and providing the input signal to the gate of the fourth transistor and for receiving the input signal and inverting the input signal to provide an inverted input signal to the gate of the third transistor.