Patent ID: 8230447

Claim:
A computer hardware system implementing an enhanced staged event-driven architecture (SEDA) comprising: at least one hardware processor implementing a global thread pool; and a plurality of event-driven stages coupled to the global thread pool, each stage including an event queue configured to enqueue a plurality of events; an event handler programmed to process events in said event queue; a logical thread pool coupled to said event handler; and, a resource manager coupled to said logical thread pool and said event queue and programmed to measure a number of events enqueued in said event queue, determine whether all threads in said thread pool are busy, allocate additional threads from the global thread pool to said logical thread pool where the number of events enqueued in said event queue exceeds a threshold value and where all threads in said thread pool are busy, and delay repeating the measurement of the number of events enqueued in said event queue until all threads are busy, wherein the plurality of event-driven stages include a callable stage in which a maximum and minimum number of threads in said logical thread pool is set to zero.