Patent ID: 7340631

Claim:
A sync generation circuit for a synchronizer pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M ≧1, comprising: a sync circuit portion, responsive to a valid edge signal indicative of coincident edges between said first and second clock signals, operable to generate based upon said ratio a start sync signal substantially centered around said coincident edges; a first sync generator, responsive to said start sync signal, operable to generate first synchronization pulses in said first clock domain, wherein a first synchronization pulse is generated when said first and second clock signals have coincident edges and further wherein said first synchronization pulses are provided to a first clock synchronizer controller; and a second sync generator, responsive to said start sync signal, operable to generate second synchronization pulses in said second clock domain, wherein a second synchronization pulse is generated when said first and second clock signals have coincident edges and further wherein said second synchronization pulses are provided to a second clock synchronizer controller.