Patent ID: 7304538

Claim:
An amplifier, comprising: a driving stage including first pmos and nmos transistors coupled together; an output stage connected to the driving stage and including second pmos and nmos transistors coupled together; and a quiescent current control stage connected to the driving stage and including third pmos and nmos transistors coupled together and a fourth pmos and nmos transistors coupled together; wherein a topology of the coupled third pmos and nmos transistors substantially matches a topology of the coupled first pmos and nmos transistors; and wherein gates of the second pmos and nmos transistors are respectively coupled to sources of the first pmos and nmos transistors; and wherein (i) a source of the third pmos is connected to a drain of the third nmos, (ii) a drain of the fourth pmos is connected to a gate of the third pmos, (iii) a gate of the fourth pmos is connected to a source of the third pmos and to a drain of the third nmos, (iv) a drain of the fourth nmos is directly connected to a gate of the first nmos, and (v) a gate of the fourth nmos is connected to a source of the third nmos.