Patent ID: 7276759

Claim:
An electrically erasable programmable memory device, comprising: a first semiconductor layer doped with a first dopant in at a first concentration; a second semiconductor layer, adjacent the first semiconductor layer, doped with a second dopant that has an opposite electrical characteristic than the first dopant, the second semiconductor layer having a top side; a first diffusion region and a second diffusion region embedded in the top side of the second semiconductor layer and defining a channel region therebetween, each diffusion region being doped with the first dopant in at a second concentration greater than the first concentration; a floating gate, comprising a conductive material, disposed adjacent the first diffusion region and above the first channel region and separated therefrom by a first insulator region, the floating gate being capable of storing electrical charge; and a control gate, comprising a conductive material, disposed laterally adjacent the floating gate and separated therefrom by a first vertical insulator layer, wherein the control gate is adjacent the second diffusion region and above the first channel region and separated therefrom by a second insulator region, and wherein the control gate and the floating gate share a planarized top surface.