Patent ID: 7312598

Claim:
A regulator for regulating an output voltage, comprising: an input circuit that is arranged to receive at least an input voltage and a reference voltage; an error amplifier that further includes: a first stage that includes two PMOS transistors and two NMOS transistors that are separately arranged as differential pairs, wherein the input voltage and the reference voltage are comparable by at least these two differential pairs, and wherein the NMOS transistor differential pair is disabled if a low load current state is sensed at an output terminal; a second stage that includes a PMOS transistor and an NMOS transistor arranged in a push pull configuration to provide the output voltage based on the comparison of the input voltage and the reference voltage, wherein the PMOS transistor differential pair is arranged to provide the comparison of the input voltage and the reference voltage to the second stage during at least a portion of the time that the NMOS transistor differential pair is disabled; and a phase compensator that includes at least one resistive-capacitive (RC) network that compensates at least the output voltage for phase shift, wherein each component of the phase compensator is disposed within the regulator; and an output circuit that is coupled to the output terminal to provide the output voltage to a load.