Patent ID: 7826286

Claim:
A semiconductor device comprising: a memory cell array having a plurality of word lines, a plurality of bit lines and a plurality of memory cells each of which is located at an intersection between one of the word lines and one of the bit lines, wherein the bit lines includes a redundant bit line; a row decoder connected to the word lines, the row decoder selecting one of the word lines in response to a row address, the row address decoder selecting the redundant word line when a first replacement signal is received thereto; a column decoder connected to the bit lines, the column decoder selecting one of the bit lines in response to a column address, the column address decoder selecting the redundant bit line when a second replacement signal is received thereto; a row address redundancy circuit storing a redundant row address, the row address redundancy circuit providing the first replacement signal when the redundant row address corresponds to an address received thereto; a column address redundancy circuit storing a redundant column address, the column address redundancy circuit providing the second replacement signal when the redundant column address corresponds to an address received thereto; a first mode setting circuit connected to the row address redundancy circuit and the row decoder for receiving a mode signal having a normal mode and a test mode, the first mode setting circuit outputting the first replacement signal received from the row address redundancy circuit to the row decoder when the mode signal is in the normal mode, and prohibiting of the first replacement signal received from the row address redundancy circuit to be outputted to the row decoder when the mode signal is in the test mode; and a second mode setting circuit connected to the column address redundancy circuit and the column decoder for receiving the mode signal, the second mode setting circuit outputting the second replacement signal received from the column address redundancy circuit to the column decoder when the mode signal is the normal mode, and prohibiting the second replacement signal received from the column address redundancy circuit to be outputted to the column decoder when the mode signal is in the test mode.