Patent ID: 7799643

Claim:
A method of fabricating a semiconductor device, comprising: forming a lower insulating layer on a semiconductor substrate; forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns; forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer; forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns; etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate; and forming a plurality of contact plugs in respective ones of the plurality of contact holes, wherein the second mask pattern is spaced apart from the plurality of mask patterns.