Patent ID: 8866277

Claim:
A package substrate comprising: a first conductive layer having plural first terminal pattern portions connected to a semiconductor part loaded on a first principal surface through plural first external connection conductors, wherein the first conductive layer is disposed on the first principal surface; a second conductive layer having plural second terminal patterns connected to a system substrate mounted on a second principal surface opposite to the first principal surface through a second external connection conductor, wherein the second conductive layer is disposed on the second principal surface; an intermediate conductive layer formed between the first conductive layer and the second conductive layer; a first interlayer insulating layer disposed between the first conductive layer and the intermediate conductive layer; a second interlayer insulating layer disposed between the second conductive layer and the intermediate conductive layer; and a first plurality of interlayer connection conductors disposed in the first interlayer insulating layer such that the first plurality of interlayer connection conductors pierce through the first interlayer insulating layer; a second plurality of interlayer connection conductors disposed in the second interlayer insulating layer such that the second plurality of interlayer connection conductors pierce through the second interlayer insulating layer, wherein the first plurality of interlayer connection conductors and the second plurality of interlayer connection conductors electrically connect the first conductive layer and the second conductive layer, and wherein a first portion of the first plurality of interlayer connection conductors having high resistance are positioned corresponding to a central portion area of a loading area on which the semiconductor part is loaded and between a second portion of the first plurality of interlayer connection conductors having low resistance positioned corresponding to the peripheral area outside the central portion area, and wherein the first terminal pattern portions, the first external connection conductors, the first plurality of interlayer connection conductors, the second plurality of interlayer connection conductors, the second terminal pattern portions, and the second external connection conductor are electrically connected forming plural current paths connecting the semiconductor part and the system substrate, and wherein current paths positioned corresponding to a central portion area of a loading area on which the semiconductor part is loaded have high resistance and current paths positioned corresponding to a peripheral area outside the central portion area have low resistance.