Patent ID: 6969880

Claim:
A capacitive structure, comprising: a semiconductor base region having an upper surface; a well formed within the semiconductor base region and adjacent the upper surface; a first dielectric layer adjacent at least a portion of the upper surface; a polysilicon layer adjacent the first dielectric layer, wherein the well, the first dielectric layer, and the first polysilicon layer form a first capacitor and are aligned along a planar dimension; a first conductive layer positioned with at least a portion overlying at least a portion of the polysilicon layer and electrically connected to said polysilicon layer; a second dielectric layer adjacent the first conductive layer; a second conductive layer adjacent the second dielectric layer with a first electrical connection to said well, wherein the first conductive layer, the second dielectric layer, and the second conductive layer form a second capacitor and are aligned along the planar dimension; and said first electrical connection further comprising: a first metal layer comprising a first region and a second region electrically separate from the first region, wherein the first region is adjacent the second conductive layer; a second metal layer at a distance greater than a distance between the upper surface and the first region of the first metal layer; a second electrical connection between the first region of the first metal layer and the second metal layer; a third electrical connection between the second metal layer and the second region of the first metal layer; and a fourth electrical connection between the second region of the first metal layer and the well.