Patent ID: 8828833

Claim:
A method of forming a p-channel metal-oxide-semiconductor (PMOS) transistor, comprising: providing in-process silicon germanium (SiGe) cavity data for at least one measured cavity parameter for a SiGe cavity formation process, said SiGe cavity formation process including cavity etching a structure including a gate stack having a gate electrode on a gate dielectric on a substrate, a sidewall spacer on a sidewall of said gate stack, and a hardmask layer on said gate electrode and lateral to said gate stack, said cavity etching including: a plurality of dry etch steps including (i) a first anisotropic dry etch for etching through said hardmask layer lateral to said gate stack and beginning etching of a recessed cavity in said substrate, (ii) a dry lateral etch, and (iii) a second anisotropic dry etch, and a wet crystallographic etch to complete formation of said recessed cavity; calculating a customized time for a selected dry etch step from said plurality of dry etch steps based on said in-process SiGe cavity data, and using said customized time for said selected dry etch step to cavity etch at least one substrate having said structure thereon in a lot of substrates or to cavity etch a run including a plurality of said substrates.