Patent ID: 8705606

Claim:
An integrated circuit operable to couple to a conductive path to receive therefrom an input signal that conveys bits of a digital sequence, the conductive path characterized by line attenuation that attenuates a high frequency of logic level transition of the bits relative to a low frequency of logic level transition of the bits, the integrated circuit comprising: receive equalization circuitry to equalize the input signal to counteract the line attenuation; sampler circuitry to sample the equalized input signal to identify logic states of respective bits of the digital sequence; and adaptation circuitry to detect, based on transitions in the logic states identified by the sampler circuitry, a presence of a specified pattern in the input signal associated with logic state transition in bits of the digital sequence, monitor at least one characteristic of the input signal, and responsive to detection of the specified pattern in the transitions in the logic states and the at least one characteristic, automatically adjust a level of equalization applied by the receive equalization circuitry.