Patent ID: 7208780

Claim:
A semiconductor storage device comprising: a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first conduction type both formed in the first semiconductor layer, and having a body of a second conduction type formed in the first semiconductor layer between the source region and the drain region, said memory cells being capable of storing data by accumulating or releasing electric charge in or from their respective body regions; memory cell lines each including a plurality of said memory cells aligned in the channel in a lengthwise direction; a memory cell array including a plurality of said memory cell lines aligned in the channel in a widthwise direction; isolation regions individually surrounding each of the memory cells; bit lines provided for each of the memory cell lines and extending along with the memory cell lines, respectively; word lines provided on the body regions and insulated from said body regions, said word lines extending in the channel in the widthwise direction; and sense amplifiers located between adjacent memory cell arrays and located at opposite ends of a memory array group including a plurality of the memory cell arrays, one of the sense amplifiers being connected to a bit line pair which is composed of two bit lines in a certain memory cell array, one of the two bit lines transmitting reference data used to sense data on another of the two bit lines.