Patent ID: 7002370

Claim:
A multiplexer circuit in a programmable logic device, said multiplier circuit having a circuit output and comprising: N data inputs, where N≧6; C control inputs; and L look-up tables, each having only one table output, wherein: L=0.5(N+MOD(N,2)); C=L+1; each of L−2 of said L look-up tables has, as an input, a table output of another one of said L look-up tables, and has its table output directed only to an input of another one of said L look-up tables; one of said L look-up tables other than said L−2 look-up tables has its table output directed only to an input of one of said L−2 look-up tables; and another one of said L look-up tables, other than said L−2 look-up tables and said one of said L look-up tables, has as an input the table output of one of said L−2 look-up tables, the output of said another one of said L look-up tables being said circuit output.