Patent ID: 7360195

Claim:
An Field Programmable Gate Array (FPGA) having an extension for coupling a first level of interconnect conductors in said FPGA to an expressway level of interconnect conductors in said FPGA comprising: a first logic module in said FPGA having n inputs and m outputs; a first switching matrix in said FPGA having n inputs and m outputs, said n inputs of said switching matrix coupled to said n inputs and m outputs of said logic module and a matrix of switches coupled between said n inputs and m outputs of said first logic module and said first switching matrix; a second logic module in said FPGA having n inputs and m outputs; a second switching matrix having n inputs and m outputs, said n inputs of said second switching matrix coupled to said n inputs and m outputs of said second logic module and a matrix of switches coupled between said n inputs and m outputs of said second logic module and said second switching matrix; said m outputs of first switching matrix having a plurality of output lines and said m outputs of said second switching matrix having a plurality of output lines, said output lines of said first switching matrix running parallel to said output lines of said second switching matrix in a crossover region; a set of expressway conductors crossing through said crossover region, said expressway conductors forming intersections with said output lines of said first and second switching matrices; and programmable interconnects disposed at said intersections formed by said expressway conductors and said output lines of said first and said second switching matrices.