Patent ID: 7338892

Claim:
A manufacturing process of a circuit carrier, comprising: providing a core layer having a hole, wherein the core layer has a first surface and a second surface; embedding a passive component in the hole; and alternately forming a plurality of dielectric layers and a plurality of circuit layers on the first surface and the second surface of the core layer, and forming a plurality of first conductive vias in the dielectric layers, wherein at least one of the circuit layers is electrically connected to the passive component through the first conductive vias, wherein a method of forming the circuit layer on the core layer comprises: alternately forming at least one first circuit layer and a part of the dielectric layers on the first surface of the core layer, wherein the passive component is electrically connected to the first circuit layer through the first conductive vias; and alternately forming at least one second circuit layer and other part of the dielectric layers on the second surface of the core layer, wherein a method of forming the first circuit layer on the first surface of the core layer comprises: laminating a first conductive layer and a first dielectric layer onto the first surface of the core layer, wherein the first dielectric layer is disposed between the first conductive layer and the core layer; forming a plurality of first blind holes in the first dielectric layer performing an electroplating process to form the first conductive vias; and patterning the first conductive layer to form the first circuit layer.