Patent ID: 8078907

Claim:
A method of responding to errors in a high performance computing system that has a control processor executing an operating system, a plurality of computing processors for executing computational tasks within the operating system, and a memory that the control processor and the plurality of computing processors share, the method comprising: the operating system forming a first plurality of computing processors that cooperate to execute a first task within the operating system, and a second, non-overlapping plurality of computing processors that cooperate to execute a second task within the operating system, wherein the control processor is not assigned to the first or second plurality; determining, by a first computing processor in the first plurality, whether the first computing processor has encountered a problem; the operating system deactivating the first computing processor after the problem has occurred; and in response to the first computing processor determining that it has encountered the problem, the operating system using the shared memory to form a third plurality of computing processors that cooperate to continue executing the first task after the problem has occurred.