Patent ID: 8093940

Claim:
A method of biasing transistor switches in a high power switch, the method comprising: providing on-state Vgsd (gate to source/drain bias voltage) at an on-state Vgsd level to a first transistor switch of said transistor switches for biasing the first transistor switch in an on state; and providing off-state Vgsd at an off-state Vgsd level to a second transistor switch of said transistor switches for biasing the second transistor switch in an off state, wherein a magnitude of the off-state Vgsd level is less than a magnitude of the on-state Vgsd level by only an amount sufficient for at least one of: bringing spurious harmonic emissions of said second transistor switch when biased to the off state below a pre-identified upper limit of acceptable spurious harmonic emissions from the second transistor switch in the off state; and bringing a linearity of the high power switch above a pre-identified lower limit of acceptable linearity for the high power switch.