Patent ID: 7924087

Claim:
A reference buffer circuit, comprising: a buffering stage, coupled to a first supply voltage and providing a high tracking voltage and a low tracking voltage respectively based on a high input voltage and a low input voltage; a first driving stage, coupled to a second supply voltage and driven by the high tracking voltage and the low tracking voltage to output a first high output voltage and a first low output voltage; a second driving stage, coupled to a third supply voltage and driven by the high tracking voltage and the low tracking voltage to output a second high output voltage and a second low output voltage; and a compensation unit, wherein the buffering stage comprises: a first NMOS transistor with its drain coupled to the first supply voltage; a first operational amplifier, having a first input end for receiving the high input voltage, a second input end coupled to a source of the first NMOS transistor, and an output end coupled to a gate of the first NMOS transistor for outputting the high tracking voltage; a first PMOS transistor with its drain coupled to a signal ground; and a second operational amplifier, having a first input end for receiving the low input voltage, a second input end coupled to a source of the first PMOS transistor, and an output end coupled to a gate of the first PMOS transistor for outputting the low tracking voltage; wherein a body of the first PMOS transistor is tied to a first bias voltage lower than the first supply voltage, and wherein the first driving stage comprises a second PMOS transistor with a body tied to a second bias voltage lower than the second supply voltage, the second driving stage comprises a third PMOS transistor with a body tied to a third bias voltage lower than the third supply voltage, and the compensation unit calibrates mismatch between the first and second driving stages by modifying the third bias voltage.