Patent ID: 8767450

Claim:
A memory system comprising: a memory cell array having a plurality of memory sectors, each of the plurality of memory sectors including a plurality of phase change memory cells; a refresh register configured to store location information for a refreshed memory sector among the plurality of memory sectors included in the memory cell array; and a controller configured to write data in the memory cell array in response to a writing signal, the controller being further configured to refresh a memory sector among the plurality of memory sectors in response to each writing signal, the memory sector among the plurality of memory sectors being a target sector subsequent to the refreshed memory sector, and being determined based on the stored location information for the refreshed memory sector; wherein when N phase change memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N, and N is a positive integer, and the refresh register is configured to store location information for only a single, most recently refreshed memory sector.