Patent ID: 7811927

Claim:
A method comprising: forming an interlayer dielectric layer over a semiconductor substrate; forming a dielectric layer over the interlayer dielectric layer; forming trenches by etching the dielectric layer and the interlayer dielectric layer; forming a barrier metal over the interlayer dielectric layer including the trenches; disposing a metal material over the barrier metal and the trenches; performing a first planarization process on the metal material using the dielectric layer as a first planarization stop layer, wherein residuals of the metal material and a portion of the barrier metal below the residuals remain over the dielectric layer between the trenches after the first planarization process; performing a wet etch process on the semiconductor substrate subjected to the first planarization process, thereby removing the dielectric layer and forming a space between the semiconductor substrate and the portion of the barrier metal; and performing a second planarization process on a surface of the interlayer dielectric layer subjected to the wet etch process, thereby removing the residuals of the metal material and the portion of the barrier metal.