Patent ID: 7011929

Claim:
A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths comprising the steps of: providing a plurality of gate structures formed overlying a substrate and comprising at least two dielectric layers formed substantially conformally to cover the gate structures; exposing a first selected portion of the plurality according to a first photoresist patterning process; then anisotropically etching through a thickness portion comprising at least an uppermost dielectric layer to form a first sidewall spacer width; then exposing a first subsequent selected portion of the plurality according to a first subsequent photoresist patterning process; then isotropically etching through at least a thickness portion of the uppermost dielectric layer; then exposing a second subsequent selected portion of the plurality according to a second subsequent photoresist patterning process; and, then anisotropically etching through at least a thickness portion of a dielectric layer underlying the uppermost dielectric layer to form a subsequent sidewall spacer width different from the first sidewall spacer width.