Patent ID: 8442154

Claim:
An architecture for a channel-sensitive power control, the architecture comprising: a receiver front end operable to receive and process an incoming signal from a communication channel in a plurality of circuits to generate a digital signal, thereby enabling an estimation of a communication channel quality, signal characteristics and an error rate; a signal strength detector operable to receive one or more signals from the plurality of circuits, the signal strength detector being operable to sense a signal strength of each of the one or more signals to generate signal strength information; and a receiver back end operable to estimate one or more receive signal factors based on the signal strength information, and operable to map the one or more receive signal factors to control signals for optimizing power consumption of receiver front end, the receiver back end comprising: a blocker discriminator operable to estimate a frequency location of an interfering signal and an amplitude of the interfering signal; a channel estimator operable to estimate a Doppler frequency of the incoming signal; a mode detector operable to detect a modulation order and a type of coding scheme of the incoming signal; a signal to noise ratio (SNR) estimator operable to estimate a signal to noise ratio; and a controller operable to: map the signal mode, the frequency of an interfering signal and the amplitude of the interfering signal to a required linearity and synthesizer performance; map the signal mode and the channel quality to a channel estimation performance; and a map the signal to noise ratio, the signal strength information and the signal mode to a required sensitivity.