Patent ID: 7451334

Claim:
A method for operating a pipeline module circuit structure with reduced power consumption, wherein said pipeline module circuit structure comprises a plurality of pipeline stages, each connected to adjacent pipeline stages through a bus, a clock generator, and a plurality of clock controllers, each clock controller being installed in a corresponding pipeline stage, said method comprising: providing a clock control bus interposed between each pair of adjacent clock controllers for bidirectional communications between said clock controllers installed in said adjacent pipeline stages; selectively transmitting a clock control signal between said clock controller of a present pipeline stage and a following adjacent pipeline stage through a corresponding clock control bus, a clock frequency of said following adjacent pipeline stage being set to an operating state responsive to said present pipeline stage being about to finish a job; and transmitting a clock control signal to said clock controller of a preceding pipeline stage through a corresponding clock control bus to set the clock frequency of said preceding pipeline stage to be an idle state responsive to said present pipeline stage receiving data and starting to operate.