Patent ID: 7719056

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a source and a drain formed in a surface region of the semiconductor substrate; a support column provided below the source and intervening between the source and the semiconductor substrate; a floating body provided between the source and the drain and accumulating or releasing charges to store data; a gate insulating film provided on the floating body; a gate electrode provided on the gate insulating film; a plate electrode provided below the drain and the floating body, and electrically isolated from the floating body and the semiconductor substrate, a source line electrically connected to the source; a bit line electrically connected to the drain; a source line contact connecting between the source line and the source; a bit line contact connecting between the bit line and the drain, wherein the drain and the floating body are electrically isolated from the semiconductor substrate by the plate electrode; and the plate electrode is provided under a whole of the drain and a whole of the floating body, but not provided under the source.