Patent ID: 6984892

Claim:
A semiconductor device, comprising: a substrate having transistor devices and a passivation layer disposed over a dielectric layer that is defined over the transistor devices; a plurality of copper interconnect metallization lines and conductive vias defined in each of a plurality of interconnect levels of the semiconductor device, the plurality of copper interconnect metallization lines and conductive vias being isolated from each other by a porous dielectric material; and a plurality of supporting stubs, each of the plurality of supporting stubs configured to form a supporting column that is disposed over a surface of the passivation layer and extends through the plurality of interconnect levels of the semiconductor device, the plurality of supporting stubs not being electrically interconnected to the plurality of copper interconnect metallization lines and conductive vias so that the supporting column maintains structural contact with the passivation layer to avoid electrical contact with the plurality of copper interconnect metallization lines and conductive vias, the plurality of supporting stubs further being configured so as to not provide electrical connection between the plurality of interconnect levels of the semiconductor device.