Patent ID: 7281116

Claim:
A multiprocessor computer system comprising: n processor including first and second processors, n being a counting number greater than 2; n TLB's associated with respective ones of said processors; and m<n memory locations for storing TLB-shootdown data, where m is counting number greater than or equal to two, each of said locations being addressable by at least one of said processors, at least one of said locations being addressable by at least two of said processors, said locations including first and second locations so that, in the event said second processor issues a second TLB-shootdown request for at least one TLB shootdown at the same time or after said first processor issues a first TLB-shootdown request for at least one TLB shootdown but before said first request is fulfilled, said first location stores TLB-shootdown data specified by said first processor while said second location stores TLB-shootdown data specified by said second processor.