Patent ID: 8443243

Claim:
A semiconductor integrated circuit device comprising: a pulse-forming circuit; a clock control circuit; a first clock generation circuit; a deserializer; an error detector; a phase detector; and a second clock generation circuit; wherein the pulse-forming circuit generates an offset pulse signal for incrementing a clock phase of a clock generated by the first clock generation circuit or an offset pulse signal for decrementing the clock phase; wherein the clock control circuit holds a clock phase updated by the offset pulse signal and outputs phase information indicating the clock phase; wherein the first clock generation circuit generates a recovery clock as a clock with a clock phase indicated by the phase information; wherein the deserializer converts serial data into parallel data using the recovery clock; wherein the error detector compares reference data, which is received through an accompanying clock lane, and the parallel data and decides whether or not the reference data and the parallel data coincide; wherein the phase detector compares a phase of serial data transmitted through the accompanying clock lane and a phase of a recovery clock generated by the second clock generation circuit, and if the recovery clock phase of the second clock generation circuit is delayed, it generates a phase delay signal for incrementing the clock phase of a recovery clock generated by the second clock generation circuit and if the recovery clock phase of the second clock generation circuit is advanced, it generates a phase advance signal for decrementing the clock phase of a recovery clock generated by the second clock generation circuit; and wherein the clock control circuit updates the clock phase held by it using the phase delay signal or the phase advance signal before receiving the offset pulse signal.