Patent ID: 8131788

Claim:
A circuit configured to perform a sum of absolute differences operation, comprising: difference units; the difference units coupled to receive pairs of inputs and configured to respectively provide carry information and a result information; a first summation block coupled to receive the carry information from each of the difference units; the first summation block configured to output a sum responsive to number of negative differences indicated by the carry information obtained from each of the difference units; a second summation block coupled to receive the result information; the second summation block configured to add the result information to provide a partial sum of absolute differences; a first accumulator coupled to receive the sum; the first accumulator configured to accumulate the sum output from the first summation block for n clock cycles, for n a positive integer greater than one, to provide a first accumulation; a second accumulator coupled to receive the partial sum of absolute differences; the second accumulator configured to accumulate the partial sum of absolute differences for the n clock cycles to provide a second accumulation; the second accumulator coupled to the first accumulator, which is configured to provide the first accumulation to the second accumulator for an n+1 clock cycle; the second accumulator configured to add the first accumulation to the second accumulation to obtain a sum of absolute differences result.