Patent ID: 7466199

Claim:
An amplifier circuit for amplifying an input signal (inp-inn) and transmitting the amplified signal as an output signal (outp-outn), comprising: a first supply terminal ( 12 ) and a second supply terminal ( 14 ) for supplying the circuit with a first supply potential (Vdd) and a second supply potential (vss) respectively, at least one current path which runs from the first supply terminal ( 12 ) via a first biased transistor (P 1 a , P 1 b ), a first circuit node (K 1 a , K 1 b ), an input transistor (Q 1 a , Q 1 b ), a second circuit node (K 2 a , K 2 b ) and a second biased transistor (N 1 a , N 1 b ) to the second supply terminal ( 14 ), wherein a control terminal of the input transistor is loaded with the input signal (inp-inn), and wherein the second circuit node (K 2 a , K 2 b ) forms a pick-up in a resistor chain (R 2 a , R 1 , R 2 b ) at whose ends the output signal (outp-outn) is supplied as a voltage drop, and a feedback stage for enabling the current to flow through the resistor chain (R 2 a , R 1 , R 2 b ) dependent on the input signal (inp-inn) so that the current flowing through the input transistor (Q 1 a , Q 1 b ) is essentially independent of the input signal (inp-inn), where the feedback stage has a pair of transistors (P 3 a , N 3 a , P 3 b , N 3 b ) coupled for complementary operation with an intermediate output node (K 3 a , K 3 b ) for transmitting the current, characterized in that the two complementarily coupled transistors (P 3 a , N 3 a , P 3 b , N 3 b ) of the feedback stage are designed as FETs, and in that the first circuit node (K 1 a , K 1 b ) is connected on the one hand via a third biased transistor (N 2 a , N 2 b ) to the second supply terminal ( 14 ), and on the other to a gate terminal of one (N 3 a , N 3 b ) of the two complementarily coupled transistors (P 3 a , N 3 a , P 3 b , N 3 b ).