Patent ID: 7719894

Claim:
A method of programming selected memory cells of a NAND memory device while protecting deselected memory cells from being programmed, the NAND memory device comprising an array of memory cells arranged as a plurality of bitlines, the method comprising: programming a first set of bitlines that includes every other bitline of the plurality of bitlines by biasing first bitlines that include memory cells not to be programmed at a first voltage, each biased first bitline being inhibited from receiving program pulses, the first bitlines being part of the first set of bitlines, wherein said biasing of the first bitlines is done by coupling the first bitlines to respective page buffers; biasing each bitline of a second set of bitlines that is adjacent to one of the first bitlines at a second voltage to boost the first voltage above a supply voltage of the NAND memory device, the second set of bitlines including all bitlines of the plurality of bitlines that are not included in the first set of bitlines, wherein biasing each bitlines of the second set of bitlines is done by coupling each of the bitlines of the second set to a line that is independent of a respective page buffer; biasing, at a reference potential, second bitlines of the first set of bitlines that include memory cells to be programmed to let the second bitlines receive program pulses; and issuing the program pulses to the first set of bitlines; and programming the second set of bitlines, after said programming of the first set of bitlines.