Patent ID: 6838343

Claim:
A method of fabricating a self-aligned split gate flash cell, comprising: forming a deep well of a first conductivity type in a substrate; forming a shallow well of a second conductivity type in the deep well; forming a gate oxide layer on the substrate; forming a control gate on the gate oxide layer, wherein a capping layer is disposed on the control gate, and the capping layer and the control gate form a stacked structure; forming a tunnel oxide layer on sidewalls of the control gate and the substrate; forming a conformal conducting layer covering the capping layer and the substrate; etching back the conformal conducting layer to form a conductivity spacer on the tunnel oxide located on sidewalls of the capping layer and the control gate; removing the conductivity spacer on one side of the control gate to leave the conductivity spacer on the other side serving as a floating gate; forming a drain and a common source beneath each side of the stacked structure in the substrate, wherein the depth of the drain and the common source are larger than the depth of the shallow well of the second conductivity type; and forming a pocket well of the second conductivity type in the substrate around the drain.