Patent ID: 8330225

Claim:
An n-type metal oxide semiconductor (NMOS) transistor, comprising: a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region of a semiconductor substrate; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source/drain region comprising a first silicon layer having a lattice adjusting element and a plurality of second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer, wherein the concentration of the n-type dopant either increases from a bottom layer of the plurality of second silicon layers to a top layer of the plurality of second silicon layers, or wherein the concentration of the lattice adjusting element decreases from a bottom layer of the plurality of second silicon layers to a top layer of the plurality of second silicon layers.