Patent ID: 7467341

Claim:
A semiconductor apparatus comprising: a stack of semiconductor circuit chip assemblies of a same sort which are each configured by disposing a boundary scan controller in a semiconductor circuit chip, wherein the boundary scan controller is configured to control a shift register circuit that include boundary scan cells respectively disposed between external signal input terminals and input terminals of an internal logic circuit and between external signal output terminals and output terminals of the internal logic circuit which are connected in series, the boundary scan controller comprising: a clock input part configured to provide input/output timings; a test mode input part configured to provide a predetermined operation instruction; a data input part configured to input identification data and test data of the semiconductor circuit chip; a storage section configured to store the identification data therein; a controller configured to execute the predetermined operation instruction so as to store the identification data in the storage section and configured to perform a circuit test with the test data so as to obtain test result data; a data output section configured to output the test result data obtained by the controller, the data output section always carrying out the output; a fixed-data holding section configured to hold predetermined fixed data therein; a comparator configured to make a comparison as to whether or not the identification data and the fixed data are in agreement, and output comparison result information; and a data derivation section coupled to the data output section to receive the test result data that is outputted from the data output section, the data derivation section being configured to derive data corresponding to the test result data on the basis of the comparison result information.