Patent ID: 7915718

Claim:
An article for use in mounting at least one flip-chip semiconductor die having a plurality of conductive bumps projecting therefrom, comprising: an interposer substrate having a first surface and a second surface and comprising at least one dielectric member supporting at least one conductive layer secured thereto, the at least one conductive layer comprising a plurality of substantially linear conductive traces arranged in four groups of traces, each group comprising at least two conductive traces oriented substantially perpendicular to a side of a die attach site on at least one of the first surface and the second surface, the interposer substrate including a plurality of recesses in at least one of the first and second surfaces extending through a thickness of the at least one dielectric member to expose portions of the conductive traces of the plurality, the plurality of recesses arranged in a first recess pattern extending peripherally about the die attach site for receiving conductive bumps of a flip-chip semiconductor die in a first bump pattern and a second recess pattern extending peripherally about the die attach site and substantially co-centered with the first recess pattern about the die attach site on the interposer substrate for receiving conductive bumps of a flip-chip semiconductor die in a second, different bump pattern, each of the first recess pattern and the second recess pattern configured to receive conductive bumps of a flip-chip semiconductor die while the interposer substrate is in a substantially planar configuration; and recesses of the first recess pattern exposing a first portion and a longitudinally spaced second portion of conductive traces of the plurality and recesses of the second recess pattern exposing a first portion and a longitudinally spaced second portion of other, different conductive traces of the plurality, wherein each conductive trace having first and second portions exposed by recesses of the first recess pattern is laterally adjacent at least one mutually parallel conductive trace having first and second portions exposed by recesses of the second recess pattern, and wherein each recess of the first recess pattern exposing a first portion or a second portion of a conductive trace is longitudinally staggered and laterally offset with respect to each recess of the second recess pattern exposing a first portion or a second portion of the at least one laterally adjacent conductive trace, each exposed portion of a conductive trace being longitudinally staggered with respect to any exposed portion of a laterally adjacent conductive trace.