Patent ID: 7444556

Claim:
A method of operating an interleaver circuit having N shift lines, each of the N shift lines having a shift line input node, a shift line output node, and one or more bit storage elements operating to perform a bit shifting operation between a respective shift line input node and a respective shift line output node, the method comprising: storing don't-care bits in each of the bit storage elements; isolating the N shift line output nodes from an interleaver output node; receiving a stream of new data bits at an interleaver input node; and sequentially connecting the interleaver input node to respective shift line input nodes to shift the stream of new data bits into the bit storage elements of corresponding shift lines in an interleaved fashion, wherein one of the don't-care bits is shifted out of each of the bit storage elements in corresponding shift lines as each of the new data bits are shifted in, wherein a last of the don't-care bits in each shift line is shifted out of respective bit storage elements during N consecutively-received data bits in the received stream of new data bits, and wherein at least two of the N shift lines have a different number of the bit storage elements.