Patent ID: 8247283

Claim:
A method for manufacturing a complementary type semiconductor device comprising: (a) forming gate electrodes in a PMOS region and an NMOS region on a silicon substrate, through a gate insulating film; (b) forming an insulating layer including a silicon nitride film and a silicon oxide film formed thereon on the silicon substrate, covering the gate electrodes, and further forming a sacrificial layer on the insulating layer; (c) anisotropically etching the sacrificial film to leave the sacrificial film only on side walls of the gate electrode in a side wall spacer shape; (d) covering the NMOS region with a mask, further anisotropically etching the insulating film to pattern the insulating layer by using the sacrificial film as an etching mask to expose silicon surface in the PMOS region; (e) removing the mask covering the NMOS region, etching regions of the silicon substrate with exposed silicon surface in the PMOS region to form recesses, and removing the sacrificial film while leaving the silicon oxide film which has been covered with the sacrificial film; (f) epitaxially growing Si—Ge-containing crystal in the recesses; (g) anisotropically etching the silicon nitride film not covered with the silicon oxide film in the NMOS region; (h) forming a silicon nitride film having tensile stress above the NMOS region; and (i) forming another silicon nitride film having compressive stress above the PMOS region.