Patent ID: 8866308

Claim:
A system comprising; a System on Chip (SOC) die having a first die edge and first die surface, the SOC die comprising: a first die high density interconnect located adjacent to the first die edge on the first die surface, the first die high density interconnect having a first bump pitch; and a first die connection region located on the first die surface, the first die connection region having a second bump pitch; and a memory die having a second die edge and a second die surface, the memory die comprising: a second die high density interconnect located adjacent to the second die edge on the second die surface, the second die high density interconnect having the first bump pitch; and a second die connection region located on the second die surface, the second die connection region having a third bump pitch; and a bridge having a plurality of high density interconnects having the first bump pitch, one of the plurality of high density interconnects connected to the first die high density interconnect and another of the plurality of high density interconnects connected to the second die high density interconnect.