Patent ID: 8643525

Claim:
An apparatus, comprising: an input code decomposer capable of determining whether a received input code is a positive or a negative value and a magnitude m of the input code, at least one positive element selector; and at least one negative element selector, if the received input code comprises a positive value, the at least one positive element selector being capable of being responsive to the input code decomposer to select m+r eligible candidate circuit elements from a plurality of circuit elements in which r comprises a number of rotational elements, each circuit element being capable of being configured as a positive circuit element or a negative circuit element, each eligible candidate circuit element comprising a circuit element that was not selected for an immediately preceding received N-bit input code and that has a corresponding minimum usage count value, the selected m+r circuit elements intended to be positive output circuit elements, and the at least one negative element selector being capable of being responsive to the input code decomposer to select r remaining eligible candidate circuit elements from the plurality of circuit elements, the remaining eligible candidate circuit elements comprising a circuit element that was not selected for an immediately preceding received N-bit input code, has a corresponding minimum usage count value, and was not one of the selected m+r circuit elements, the selected r circuit elements intended to be negative output circuit elements, and if the received input code comprises a negative value, the at least one negative element selector being capable of being responsive to the input code decomposer to select m+r eligible candidate circuit elements from a plurality of circuit elements in which r comprises a number of rotational elements, each eligible candidate circuit element comprising a circuit element that was not selected for an immediately preceding received N-bit input code and that has a corresponding minimum usage count value, the selected m+r circuit elements intended to be negative output circuit elements, and the at least one positive element selector being capable of being responsive to the input code decomposer to select r remaining eligible candidate circuit elements from the plurality of circuit elements, the remaining eligible candidate circuit elements comprising a circuit element that was not selected for an immediately preceding received N-bit input code, has a corresponding minimum usage count value, and was not one of the selected m+r circuit elements, the selected r circuit elements intended to be positive output circuit elements.