Patent ID: 7978543

Claim:
A semiconductor device comprising: first and second input/output terminals; a first input/output line connected to said first input/output terminal; a second input/output line connected to said second input/output terminal; and a first by-path route connected between said first input/output line and said second input/output line, wherein when in normal operation mode, said first by-path route is in a non-conductive state, and when in a test mode, said first by-path route is set into a conductive state so that a first data inputted to said first input/output terminal is outputted as a first input data to said second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.