Patent ID: 8211793

Claim:
A method of fabricating a structure in a semiconductor device, comprising: forming a lower metal interconnection; forming a lower insulating layer defining a lower contact hole on the lower metal interconnection, the lower insulating layer exposing a portion of a surface of the lower metal interconnection; forming an upper insulating layer defining an upper contact hole wider than the lower contact hole on the lower metal interconnection, the upper insulating layer fully exposing the lower contact hole and a portion of a top surface of the lower insulating layer, the portion of the top surface of the lower insulating layer being around the lower contact hole, wherein a depth of the lower contact hole is shallower than a depth of the upper contact hole; forming a contact spacer disposed on sidewalls of the lower contact hole and the upper contact hole, wherein the contact spacer exposes a portion of the lower metal interconnection and covers an entire surface of the portion of the top surface of the lower insulating layer exposed by the upper insulating layer to smooth an inner shape formed by a step difference of the lower contact hole and the upper contact hole; forming a barrier pattern on the exposed surface of the lower metal interconnection, the contact spacer and a portion of a top surface of the upper insulating layer; forming a lower contact directly on the barrier pattern, wherein the lower contact fills the lower contact hole; forming an upper contact directly on the barrier pattern, wherein the upper contact fills the upper contact hole; and forming an upper metal interconnection directly on the upper contact and the barrier pattern on the portion of the top surface of the upper insulating layer.