Patent ID: 8799743

Claim:
An apparatus comprising: a first semiconductor memory unit including a first physical memory location having memory cells configured to store data having a first value; a second semiconductor memory unit including a second physical memory location having memory cells configured to store error correction information to recover the data, the error correction information having a value based on at least the first value, wherein at least one of the first and second semiconductor memory units includes dice arranged in a stack, the first semiconductor memory unit configured to store a new data in the first physical memory location to replace the data in the first physical memory location, and the second semiconductor memory unit configured to update the value of the error correction information after the data is replaced by the new data; and lines to transfer address between a controller and the first and second semiconductor memory units, wherein the first semiconductor memory unit is selected to store the data based on a value of a first group of bits of the address, and the second semiconductor memory unit is selected to store the error correction information based on a value of a second group of bits of the address.