Patent ID: 6900079

Claim:
A method of forming a semiconductor device package, comprising: providing a semiconductor substrate having an active surface including at least one layer of integrated circuitry thereon, the active surface defining a plurality of individual die locations thereon, and a plurality of bond pads associated with each of the plurality of individual die locations; forming intermediate conductive elements over the plurality of bond pads to project a height above the active surface; forming a pattern of mutually transverse channels in the active surface to a depth below the at least one layer of integrated circuitry, the mutually transverse channels circumscribing a semiconductor device location comprised of at least one individual die and exposing peripheral edges of the at least one layer of integrated circuitry; applying an encapsulant material at least over the active surface and into the mutually transverse channels to a depth exceeding the height of projection of the intermediate conductive elements; removing a depth of the encapsulant material sufficient to expose a portion of each of the intermediate conductive elements; and placing the semiconductor substrate with the intermediate conductive elements in alignment with conductive bumps protruding from a carrier substrate; and electrically connecting the intermediate conductive elements and the conductive bumps.