Patent ID: 7507657

Claim:
A method for fabricating a plurality of storage node contacts in a semiconductor device, comprising the steps of: forming a first inter-layer insulation layer on a semi-finished substrate; forming a plurality of bit line patterns including a hard mask nitride layer on the inter-layer insulation layer; forming a plurality of nitride based bit line spacers in contact with both lateral sides of the plurality of bit line patterns; forming a second inter-layer insulation layer filling gaps between the plurality of bit line patterns; planarizing the second inter-layer insulation layer by performing a first chemical mechanical polishing process to the second inter-layer insulation layer two times until the polishing is stopped on surfaces of the plurality of bit line patterns; forming a plurality of storage node contact holes opening a surface of the substrate between the plurality of bit line patterns by selectively etching the first and the second inter-layer insulation layers; forming a conductive layer filling the plurality of storage node contact holes; forming a plurality of storage node contacts by performing an etch back to the conductive layer; and additionally performing a second chemical mechanical polishing process to the second inter-layer insulation layer to remove the plurality of cruspidal patterns generated during performing the etch back to the conductive layer by using a slurry having a polishing speed identical with surrounding materials of the cruspidal patterns, wherein a pH of the slurry used for the second chemical mechanical polishing process ranges from approximately 2 to approximately 11.