Patent ID: 7466581

Claim:
An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns, wherein the array comprises: a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column, wherein the plurality of VSS lines comprises: a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other; and a power circuit comprising: a first output connected to the first VSS line; and a second output connected to the second VSS line, wherein the power circuit is configured to output a first voltage to the first output, and a second voltage to the second output, and wherein the first voltage is different from the second voltage.