Patent ID: 8228749

Claim:
A method of evaluating an operating margin in a memory, the memory comprising a plurality of memory cells, arranged in rows and columns, the memory cells in each column associated with a pair of complementary bit lines, the memory cells in each row associated with a word line, each memory cell comprised of cross-coupled inverters defining a pair of storage nodes, and a pair of pass transistors for coupling the storage nodes to the bit lines of its column responsive to an active level on its associated word line; wherein the method comprises: writing opposite data states to a first memory cell and at least one memory cell other than the first memory cell in a selected column; then precharging the bit lines of the selected column to a precharge voltage; then floating the bit lines of the selected column; during the floating step, driving a plurality of pulses of an active level to a word line associated with one of the at least one other memory cells; after the driving step and during the floating step, driving the word line associated with the first memory cell to an active level; then precharging the bit lines of the selected column; and then reading the state of the first memory cell.