Patent ID: 8250126

Claim:
An apparatus that estimates a location of a leading zero or a leading one in a result of an addition of floating-point numbers A and B, comprising: a set of half-adder circuits, wherein each half-adder circuit is associated with a separate bit position i in floating-point numbers A and B and wherein each half-adder circuit computes a sum (S) for the associated bit position of A and B and a carry (K) for a next bit position of A and B; and a set of estimation circuits coupled to the set of half-adder circuits, wherein the set of estimation circuits computes an estimate for the location of the leading zero or the leading one in the result from the K and S computed by each half-adder circuit, wherein each half-adder circuit comprises an XOR gate to calculate S i =A i XOR B i and an AND gate to calculate K i−1 =A i AND B i , for each separate bit position i in A and B; and wherein all the estimation circuits comprise one of: a first circuit that comprises an XOR gate to calculate T i−1 =S i−1 XOR K i−1 , an OR gate to calculate NOT(Z i )=S i OR K i , and an XOR gate to calculate R i =T i−1 XOR NOT(Z i ) for each separate bit position i in A and B, wherein, when the estimation circuits comprise the first circuit, if the result is positive, a first occurrence from left to right of R i =1 provides a value of i such that the leading one is at location i or i−1 in the result, and if the result is negative, the first occurrence from left to right of R i =1 provides the value of i such that the leading zero is at location i or i+1 in the result; a second circuit that comprises an XOR gate to calculate T i−1 =XOR K i−1 , a NOR gate to calculate Z i =NOT(S i OR K i ), and an XNOR gate to calculate R i =NOT(T i −1 XOR Z i ), for each separate bit position i in A and B, wherein, when the estimation circuits comprise the second circuit, if the result is positive, a first occurrence from left to right of R i =1 provides a value of i such that the leading one is at location i or i−1 in the result, and if the result is negative, the first occurrence from left to right of R i =1 provides the value of i such that the leading zero is at location i or i+1 in the result; or a third circuit that comprises an AND gate to calculate K i =A i+1 AND B i+1 , an XOR gate to calculate T i =S i XOR K i , a NOR gate to calculate Z i =NOT(S i OR K i ), a NOR gate to calculate LZ i =NOT(T i−1 OR Z i ), an AND gate to calculate LO i =T i−2 AND Z i−1 , and an OR gate to calculate R i =LO i OR LZ i , for each separate bit position i in A and B, wherein, when the estimation circuits comprise the third circuit, for a positive result or negative result that has been complemented, a first occurrence from left to right of R i =1 provides a value of i such that the leading one is at location i or i−1 in the result.