Patent ID: 8411521

Claim:
A testing system, comprising: testing circuitry for generating test signals; a test signal output circuit coupled to the testing circuitry, the test signal output circuit being operable to transmit the test signals from the testing system, the test signal output circuit comprising: a plurality of data latches, each of the data latches having a clock input, a data input, and a test signal output, each of the data latches being operable to receive at its data input a respective bit of test data from the testing circuitry; a signal distribution tree having an input node coupled to receive a first digital signal and a plurality of output nodes each of which is coupled to the clock input of a respective one of the data latches; a phase interpolator between the input node and each of the output nodes of the signal distribution tree; and a delay line between the input node and at least one of the output nodes of the signal distribution tree.