Patent ID: 7187608

Claim:
A memory system comprising a main memory which must be refreshed to maintain data and which is divided into blocks, a cache memory which must be refreshed to maintain data and which stores information corresponding to selected blocks of in said main memory, said cache memory having indicator bits to indicate if particular information is valid information, refresh circuitry to periodically refresh said main memory and said cache memory, said refresh circuitry having a refresh start signal, input-output circuitry to generate read signals requesting information from a target memory block in said memory system, control circuitry operative when said refresh start signal is enabled, a read signal is received, said cache memory is not storing the target block of said read signal, and the data in said cache is not valid data of a different block other than said target block, for (a) delaying the refresh of said target block, (b) reading said requested information from said main memory and transferring the target memory block of said read operation to said cache memory, and after (a) and (b) refreshing said target memory block and said different, whereby said read and refresh takes place without a write-back from said cache to said main memory when said cache memory is not storing the target block of said read signal, and the data in said cache is not valid data of a different block other than said target block.