Patent ID: 7881150

Claim:
A circuit configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals, comprising row address signals, column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit comprising: a logic element; a register; a phase-lock loop device configured to be operationally coupled to the plurality of DDR memory devices, the logic element, and the register, wherein the circuit is configurable to be responsive to the set of input signals by selectively isolating one or more loads of the DDR memory devices from the computer system, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices, wherein the system memory domain has a first memory density per rank and the physical memory domain has a second memory density per rank less than the first memory density per rank.