Patent ID: 8024506

Claim:
A computer program embodied in a non-transitory, computer-readable medium, the computer program being executable in a physical computer system in which multiple devices have concurrent memory access, the computer program comprising: a software-based instruction processor for enabling the execution of instructions as if the instructions were executed on a virtualized computer system, the physical computer system having a virtual memory system used by a physical processor in the physical computer system, the processing of each of a plurality of the instructions requiring multiple memory accesses to access code and data related to the instructions, where each of a plurality of the multiple memory accesses requires a memory mapping from a virtual address to a physical address in accordance with the virtual memory system, the virtual memory system comprising a translation lookaside buffer (TLB) and at least one set of one or more page tables used by the physical processor for obtaining memory mappings; and a plurality of mapping-data storage locations, distinct from the TLB and the page tables used by the physical processor for obtaining memory mappings, for storing memory mappings between virtual addresses and physical addresses during the software-based processing of the instructions, wherein, during the processing of each instruction processed by the software-based instruction processor, for each memory access that requires a memory mapping, the instruction processor attempts to establish the required memory mapping by determining whether the mapping-data storage locations contain an entry that matches a virtual address of the required memory mapping and, if the instruction processor finds a matching entry in the mapping-data storage locations, the instruction processor uses a stored memory mapping from the matching entry, instead of using a memory mapping established according to the virtual memory system, and if the instruction processor does not find a matching entry in the mapping-data storage locations, the instruction processor attempts to establish the required memory mapping according to the virtual memory system and, if the required memory mapping is established, adding an entry to the mapping-data storage locations indicating the established memory mapping and retaining the entry until the software-based processing of the instruction is substantially completed, so that, during the software-based processing of instructions, for at least one instruction that requires multiple memory accesses for a virtual address, a memory mapping is found in the page tables of the virtual memory system for a first memory access mapping the virtual address to a physical address, but a memory mapping is found in the mapping-data storage locations for at least one subsequent memory access mapping the virtual address to the same physical address, instead of attempting to establish the required memory mapping according to the page tables of the virtual memory system.