Patent ID: 8722532

Claim:
A method for manufacturing a semiconductor device, comprising: a metal pattern formation process of forming a metal pattern having a pattern along a first wiring over a semiconductor substrate; a first via pattern formation process of partially etching the metal pattern, and thereby forming the first wiring, and a first via in contact with the first wiring at the bottom surface thereof; and a first insulation layer formation process of forming a first insulation layer in contact with at least the top surface of the first wiring and the side surface of the first via over the semiconductor substrate, wherein the metal pattern formation process includes: forming a metal layer over the semiconductor substrate; sequentially forming a first mask layer, and a second mask layer formed of a different material from that of the first mask layer over the metal layer; a first wiring mask formation process of patterning the first mask layer and the second mask layer, and forming a first wiring mask having the shape of the first wiring in plan view; a first via mask formation process of, after the first wiring mask formation process, patterning the second mask layer, and forming a first via mask having at least a part of the shape of the first via in plan view; and etching the metal layer with the first wiring mask as a mask, and thereby forming the metal pattern, and wherein the first via pattern formation process includes: etching the first wiring mask with the first via mask as a mask in plan view; and with the first via mask, and the first mask layer patterned into the same shape as that of the first via mask in plan view as a mask, partially etching the metal pattern, and thereby forming the first via.