Patent ID: 8188523

Claim:
An insulated gate field effect transistor having a gate electrode on a substrate with a gate insulating film interposed between said substrate and said gate electrode, and having a source region and a drain region formed in said substrate on both sides of said gate electrode, said insulated gate field effect transistor comprising: a first diffusion layer of a first conduction type formed in said substrate at a position deeper than said source region and said drain region; and a second diffusion layer of the first conduction type having a higher concentration of an impurity than that of said first diffusion layer and formed in said substrate at a position deeper than said first diffusion layer, the second diffusion layer being separated from the first diffusion layer by an intervening layer having a conduction type that is different than the first conduction type, wherein the depths of the first diffusion layer peak position of impurity and second diffusion layer peak position of impurity are selected such that a neutral potential state is positioned in the substrate at a depth lower than the second diffusion layer to reduce charge movement.