Patent ID: 8225261

Claim:
A method for defining a vertical connection layout for a circuit, comprising: defining a first virtual grate as a set of parallel virtual lines extending across a layout area in a first direction, wherein the virtual lines of the first virtual grate correspond to placement locations for layout features in a lower chip level; defining a second virtual grate as a set of parallel virtual lines extending across the layout area in a second direction substantially perpendicular to the first direction, wherein the virtual lines of the second virtual grate correspond to placement locations for layout features in a higher chip level, wherein each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid; operating a computer to place vertical connection structures at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels, wherein the computer is operated to place the vertical connection structures so as to minimize a number of different vertical connection structure edge-to-edge spacing sizes between neighboring vertical connection structures across the vertical connection placement grid; and operating the computer to record the placements of the vertical connection structures in a layout file on a computer readable storage medium.