Patent ID: 8648429

Claim:
A semiconductor device comprising: a substrate including at least a first conductive terminal disposed at a first surface of the substrate and a second conductive terminal disposed at the first surface of the substrate; at least a first set of two or more chips and a second set of one or more chips; the first set of two or more chips comprising: a plurality of semiconductor chips including at least a first chip stacked on a second chip, the first chip including at least a first conductive terminal disposed at a first surface of the first chip; the second set of one or more chips comprising: one or more semiconductor chips including at least a third chip, the third chip including at least a first conductive terminal disposed at a first surface of the third chip; a first node including the first conductive terminal of the first chip, the first conductive terminal of the substrate, and a bonding wire disposed between the two conductive terminals; a first through via passing through at least part of the first chip and electrically connected to the first node and the second chip; a second node including the first conductive terminal of the third chip, the second conductive terminal of the substrate, and a first conductive contact disposed between the two conductive terminals, wherein the first set of chips and second set of chips are mounted on the substrate such that the first set of chips is stacked on the second set of chips, wherein the first conductive terminal of the substrate is a chip select terminal dedicated to the first set of two or more chips and for selecting the first set of two or more chips, and wherein the second conductive terminal of the substrate is a control signal terminal, data terminal, or power terminal, shared among the first set of chips and the second set of chips.