Patent ID: 7525869

Claim:
A method for operating a decoder circuit, said method comprising: conveying on a first bias node a first selected voltage for a first mode of operation and a second selected voltage for a second mode of operation, said first bias node traversing and associated with a plurality of decoder output driver circuits; conveying on a second bias node a first unselected voltage for the first mode of operation and a second unselected voltage for the second mode of operation, said second bias node traversing and associated with the plurality of decoder output driver circuits; coupling a decoder output node, when selected, to the first bias node by way of a first coupling circuit of a respective decoder output driver circuit; coupling, by way of a second coupling circuit in series with a third coupling circuit of a respective decoder output driver circuit, the decoder output node, when unselected in the first mode of operation, to the first unselected voltage conveyed on the second bias node and, when unselected in the second mode of operation, to the second unselected voltage conveyed on the second bias node; and limiting the respective voltage across each of said second and third coupling circuits when the decoder output node is selected in each of the first and second modes of operation, to a value less than the difference between the first selected voltage and the first unselected voltage in the first mode of operation, and to a value less than the difference between the second selected voltage and the second unselected voltage in the second mode of operation.