Patent ID: 7960212

Claim:
A method for fabricating a circuit component, comprising: providing a silicon wafer, multiple active devices in or on a surface of said silicon wafer, a protective layer over said silicon wafer, and a metal contact point at a bottom of an opening in said protective layer, wherein said opening in said protective layer is over said metal contact point; forming a seed layer over said protective layer and over said metal contact point; forming a photoresist layer on said seed layer, wherein an opening in said photoresist layer exposes a region of said seed layer; after said forming said photoresist layer, forming a first solder layer over said region; after said forming said first solder layer, removing said photoresist layer; after said removing said photoresist layer, removing said seed layer not under said first solder layer; and after said removing said seed layer, mounting a passive device over said silicon wafer and joining said passive device with said first solder layer.