Patent ID: 8356163

Claim:
A SIMD microprocessor comprising: plural processor elements each having n arithmetic circuits and n registers configured to temporarily store data pieces to be input to the n arithmetic circuits, n being a natural number equal to or greater than 2, and a control circuit configured to determine an arrangement order of the plural processor elements and an arrangement order of the n arithmetic circuits in the plural processor elements and determine whether to use the n arithmetic circuits in each of the plural processor elements as a single arithmetic circuit or as n arithmetic circuits; wherein each of the plural processor elements further includes: n shifter pairs each including a PE (processor element) shifter in series with and directly connected to a bit shifter, the PE shifter being configured to select and transfer plural data pieces that are input from other plural processor elements, the bit shifter being configured to perform a bit shift operation on the data pieces temporarily stored in the registers; and n shift data selection circuits configured to select a subset of data pieces from the data pieces in the bit shifter of the n shifter pairs, perform bit extension on the subset of data pieces, and transfer the subset of data pieces to the n arithmetic circuits.