Patent ID: 7045830

Claim:
A high voltage diode formed integrally with a power integrated circuit on a substrate of a first conductivity type, comprising: an isolation layer of a second conductivity type opposite said first conductivity type formed in said substrate; an epitaxial layer of said first conductivity type formed on said substrate; an HV well of said second conductivity type formed within said epitaxial layer; an anode including a pair of spaced apart gates formed over said HV well, said gates having gate electrodes with sidewall spacers, lightly-doped tub wells of said first conductivity type formed in said HV well between said gates and extending partially under a corresponding one of said gate electrodes, a pair of spaced apart heavily-doped wells of said second conductivity type formed in said HV well, each said heavily-doped well of said second conductivity type formed in self alignment with an inner edge of a corresponding one of said gate electrodes, a heavily-doped well of said first conductivity type formed between said gates and in self alignment with said sidewall spacers, said pair of heavily-doped wells of said second conductivity type and said heavily-doped well of said first conductivity type being electrically interconnected to each other and to said insulated gates; and a cathode including a pair of heavily-doped first wells of said second polarity type formed in said HV well, each said first well being spaced apart from an outer edge of a corresponding one of said gates, a second heavily-doped well of said first polarity type formed adjacent to each said first well on a side thereof furthest from the corresponding gate, and a third heavily-doped well of said second polarity type formed adjacent to each said first well on a side thereof nearest the corresponding gate, said first, second and third wells being electrically interconnected with each other.