Patent ID: 8391483

Claim:
A digital apparatus, comprising: a table circuit configured to store a table that includes a plurality of key values, a plurality of program identification values, and a plurality of packet header values, the program identification values being positioned at varied locations in the packet header values, respectively; a mask value storing circuit unitary with the table circuit and configured to store a plurality of mask values associated respectively with the key values and associated respectively with the packet header values, each mask value including a same number of bits as each packet header value, and each mask value including first bit values at first bit locations corresponding to the location of the program identification values in the associated packet header value and including second bit values elsewhere, wherein the second bit values are different than the first bit values; a combining circuit coupled to the mask storing circuit and configured to: receive an input value corresponding to one of the packet header values and having a bit sequence corresponding to one of the program identification values at a location in the input value, combine the input value and one of the mask values, and provide a combined value having the first bit values at bit locations corresponding to the first bit locations of the one of the mask values and having the second bit values elsewhere; a comparing circuit coupled to the table circuit and the combining circuit and configured to compare the combined value and the program identification value associated with the one of the mask values and, (i) when they are not equal, cause the combining circuit to combine the input value with another one of the mask values, and (ii) when they are equal, output an enable signal to cause generation of an output value that is the key value associated with the one of the mask values.