Patent ID: 7416925

Claim:
A method of manufacturing a semiconductor device, comprising: forming a fin structure, the fin structure including first and second side surfaces; forming a dielectric layer on the first and second side surfaces of the fin structure; depositing a gate material layer over at least the fin structure; planarizing the gate material layer to expose an upper surface of the fin structure; etching the gate material layer to form a first gate electrode and a second gate electrode, the second gate electrode being formed on an opposite side of the fin structure than the first gate electrode; etching the gate material layer to recess the first gate electrode and the second gate electrode from the fin structure; depositing a second dielectric layer over the fin structure and the first and second gate electrodes; etching the second dielectric layer to create an opening to expose at least a portion of the fin structure; and performing a selective epitaxial growth process to form a silicon layer to fill the opening.