Patent ID: 8154053

Claim:
An integrated circuit comprising: a plurality of layers disposed vertically with respect to each other, wherein each layer comprises a respective plurality of ports; a pair of main input ports configured on a first layer of the plurality of layers; and a pair of main output ports configured on the first layer; wherein the respective plurality of ports of each layer are programmable to establish: a first conductive path between one of the pair of main inputs ports and either one of the pair of main output ports, for conducting electrical signals between the one of the pair of main input ports and the either one of the pair of main output ports; and a second conductive path between a remaining one of the pair of main inputs ports and a remaining one of the pair of main output ports, for conducting electrical signals between the remaining one of the pair of main input ports and the remaining one of the pair of main output ports; wherein the first conductive path and the second conductive path both pass through each layer.