Patent ID: 8780102

Claim:
A display device comprising: a display unit comprising a plurality of scan lines and a plurality of threshold voltage compensation lines for respectively transmitting a plurality of scan signals and a plurality of threshold voltage compensation signals, a plurality of data lines for transmitting a plurality of data signals, and a plurality of pixels coupled to a plurality of light emission control lines for transmitting a plurality of light emission control signals; a scan driver for transmitting the plurality of scan signals and the plurality of threshold voltage compensation signals; a data driver for transmitting the plurality of data signals; and a light emission control driver for transmitting the plurality of light emission control signals, wherein each pixel of the plurality of pixels comprises: an organic light emitting diode (OLED); a driving transistor for transmitting a driving current to the OLED according to one of the data signals; a first transistor for transmitting the one of the data signals to the driving transistor according to one of the scan signals during a frame; and a first capacitor comprising a first terminal coupled to the first transistor and a second terminal coupled to a gate electrode of the driving transistor, wherein the driving transistor is further configured to be diode-connected according to one of the threshold voltage compensation signals during a threshold voltage compensation period to compensate for a threshold voltage of the driving transistor, and the one of the threshold voltage compensation signals comprises at least two pulses during the frame, and wherein the scan driver is further for: receiving a start signal comprising a pulse pattern for generating the at least two pulses, a first clock signal, a second clock signal having a phase difference of a half cycle from the first clock signal, a first initialization signal generated concurrently with the second clock signal, and a second initialization signal generated concurrently with the first clock signal; and sequentially shifting the start signal by a first period to generate the plurality of threshold voltage compensation signals.