Patent ID: 7662651

Claim:
A method of manufacturing a thin film transistor (TFT) array panel on a substrate, comprising: forming a plurality of gate lines on the substrate; forming a plurality of gate electrodes by a photolithography process; forming a gate insulating layer on the substrate and the gate electrodes; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a desired active area by a photolithography process; forming a conductive layer on the gate insulating layer and the ohmic contact layer; forming a plurality of drain electrodes, data lines having a plurality of source electrodes, and a plurality of conductive patterns, wherein the drain electrodes extend parallel with and adjacent to the data lines and are directly connected to the conductive patterns, and wherein the conductive patterns overlap an adjacent gate line; forming an insulating layer on all of the data lines, the drain electrodes, the source electrodes, the gate insulating layer, and the conductive patterns, the insulating layer having a contact hole, and forming a plurality of pixel electrodes on the insulating layer, the pixel electrodes being electrically connected to the conductive patterns through the contact hole.