Patent ID: 7313041

Claim:
A memory device, comprising: a first sense supply node driven to a first voltage during a first portion of a sense operation and to a second voltage during a second portion of the sense operation, the second voltage being a low power supply voltage, the first voltage being lower in potential than the second voltage; a sense amplifier circuit, comprising a first transistor of a first conductivity type having a gate coupled to a first sense node, a source coupled to the first sense supply node, and a drain coupled to a second sense node, and a second transistor of the first conductivity type having a gate coupled to the drain of the first transistor, a source coupled to the first sense supply node and a drain coupled to the gate of the first transistor; and a first supply circuit that couples the first sense supply node to a first voltage power supply and subsequently couples the first sense supply node to a second voltage power supply in response to a plurality of first control signals.