Patent ID: 7573772

Claim:
A semiconductor memory device, comprising: a plurality of input/output ports having respective independent operations of a first mode and a second mode, wherein a period of a self-refresh mode through one of the plurality of input/output ports in the second mode is changed in response to the first mode of operation through another input/output port; and a refresh period control circuit, wherein the self-refresh period is controlled to be shorter in the second mode than in the first mode, and wherein the refresh period control circuit comprises: an active mode sensing unit for sensing a start of the active mode of the first input/output port and generating a first pulse, and sensing a completion of the active mode and generating a second pulse; a refresh period conversion signal generator for generating a refresh period conversion signal enabled by the first pulse and disabled by the second pulse output from the active mode sensing unit; and a refresh period controller for controlling the self-refresh period in a self-refresh performed through the second input/output port in response to the refresh period conversion signal.