Patent ID: 8560784

Claim:
A memory control device which is coupled to a processor and a storage device having first memory bank and a second memory bank corresponding to the first memory bank, and which issues a memory access request received from the processor to the storage device, the memory control device comprising: a first request storage unit configured to hold a first memory access request to the first memory bank; a second request storage unit configured to hold a second memory access request to the second memory bank; a decode unit configured to allocate, to the first request storage unit or the second request storage unit, each of the first memory access request and the second memory access request received from the processor based on a bank address included in the each of the first memory access request and the second memory access request; a selection unit connected to the first request storage unit and the second request storage unit and configured to select and output the first memory access request held in the first request storage unit or the second memory access request held in the second request storage unit as a selected memory access request based on a selection signal; a first determination circuit configured to output a first determination result as to whether the first memory access request held in the first request storage unit can be issued to the first memory bank depending on a relationship with a first issued memory access request already issued to the first memory bank; a second determination circuit configured to output a second determination result as to whether the second memory access request held in the second request storage unit can be issued to the second memory bank depending on a relationship with a second issued memory access request already issued to the second memory bank; a third determination circuit configured to output a third determination result as to whether the selected memory access request can be issued to the storage device depending on a relationship with an issued memory access request already issued to the storage device; and a priority control circuit connected to the first determination circuit and the second determination circuit, configured to output the selection signal according to priorities held by a priority control register, and configured to update the priorities held by the priority control register according to the first determination result through the third determination result.