Patent ID: 7173468

Claim:
A delay line for delaying an electrical signal propagating from an input to an output, comprising: means for creating an inverted version and a non-inverted version of the electrical signal to be delayed; a delay chain comprising a plurality N of series-connected delay stages including a first delay stage, an Nth delay stage, and one or more intermediate delay stages connected between the first and Nth delay stages, each of the intermediate delay stages and the Nth delay stage receiving one of an output of a previous stage and an injected signal, wherein said injected signal comprises one of the inverted version and the non-inverted version of the electrical signal to be delayed, and wherein the delayed output signal is extracted from the Nth delay stage; and means coupled to the delay chain for providing the injected signal into a selected delay stage of the plurality N of series-connected delay stages in response to a tap address value, wherein each delay stage is a NAND gate delay stage for accepting one of the output of the previous stage and the injected signal, wherein the delayed output signal is extracted from the last NAND gate delay stage.