Patent ID: 8502603

Claim:
A circuit, comprising: a differential input stage including a first input transistor configured to receive a first input signal, a second input transistor configured to receive a second input signal and a first tail current source coupled to supply a first current to the first and second input transistors at a first common connection node, said differential input stage having a pair of outputs; a pair of cascode transistors having conduction terminals respectively coupled to the pair of outputs of the differential input stage; a replica differential input stage including a third input transistor configured to receive said first input signal, a fourth input transistor configured to receive said second input signal and a second tail current source coupled to supply a second current to the third and fourth input transistors at a second common connection node, the third and fourth input transistors having a third common connection node configured to output a third current; and a bias generator circuit adapted to generate a bias voltage for application to control nodes of the pair of cascode transistors which is dependent on the third current.