Patent ID: 8124453

Claim:
A method for configuring an electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module for packaging at least a top integrated circuit (IC) chip and a bottom IC chip therein respectively, with each of the top and bottom IC chips having a flat-surface electrode, wherein the method comprising: fabricating a top and a bottom laminated board by forming via connectors and distributing conductive traces on multiple layers of said laminated boards for connecting to selected via connectors and forming and patterning on each of said laminated board a metal plate; a solder mask covering an extensive area of a bottom surface of said laminated board; face-to-face soldering the flat-surface electrode of each of said top and bottom IC chips to the metal plates on the bottom surface of said laminated board with a top surface of said bottom laminated board having electrical contact pads matching with electrode footprints of said top packaging module to surface mount said top packaging module directly onto said bottom laminated board; and connecting a first set of top-tall solder balls of a first ball grid array (BGA) of said top packaging module to said flat surface electrode of said top IC chip through the solder mask disposed on said bottom surface of said upper laminated board by forming said top-tall solder balls to extend downwardly from said bottom surface of said upper laminated board to contact the electrical contact pads disposed on said top surface of said lower laminated board to stack vertically thereon.