Patent ID: 8326364

Claim:
An apparatus comprising: a transmit comma detect circuit that is clocked by first clock signal; a receive comma detect circuit that is clocked by the first clock signal; and a stopwatch counter having: a transmit latching circuit having: a first transmit latching path that is clocked by negative edges of a second clock signal and that is coupled to the transmit comma detect circuit, wherein the frequency of the second clock signal is greater than the frequency of the first clock signal; a second transmit latching path that is clocked by positive edges of the second clock signal and that is coupled to the transmit comma detect circuit; and a first flip-flop having an input terminal, a clock terminal, and an output terminal, wherein the input terminal of the first flip-flop is coupled to the first transmit latching path, and wherein the clock terminal of the first flip-flop is coupled to the second transmit latching path; a receive latching circuit having: a first receive latching path that is clocked by the negative edges of the second clock signal and that is coupled to the receive comma detect circuit; a second receive latching path that is clocked by the positive edges of the second clock signal and that is coupled to the receive comma detect circuit; and a second flip-flop having an input terminal, a clock terminal, and an output terminal, wherein the input terminal of the first flip-flop is coupled to the first receive latching path, and wherein the clock terminal of the first flip-flop is coupled to the second receive latching path; and a counter state machine that is coupled to the second transmit latching path, the second receive latching path, the first flip-flop, and the second flip-flop.