Patent ID: 7141511

Claim:
A method for fabricating a device comprising: forming a plurality of wordlines over an array portion and a peripheral portion of a substrate; forming a plurality of spacers, each of the plurality of spacers being adjacent to one of the plurality of wordlines; depositing a dielectric etch stop layer over each of the plurality of spacers, the plurality of wordlines, the array portion and the peripheral portion of the substrate; depositing a photoresist layer over the dielectric etch stop layer; etching the photoresist layer and the dielectric etch stop layer to expose the substrate in the peripheral portion adjacent to at least one of the plurality of wordlines in the peripheral portion; doping a plurality of active areas in the peripheral portion adjacent to the at least one of the plurality of wordlines; depositing a plurality of conductive plugs between at least a portion of the plurality of spacers in the array portion; depositing a dielectric layer over at least a portion of the dielectric etch stop layer and the peripheral portion; etching into the dielectric layer with an etchant to expose at least one of at least one of the plurality of active areas in the peripheral portion and at least one of the plurality of wordlines in the peripheral portion and at least one of the plurality of conductive plugs in the array portion, wherein the etchant is more selective to the dielectric layer than the dielectric etch stop layer; and depositing a buried digit layer over each of the dielectric etch stop layer, the dielectric layer, the at least one of the at least one of the plurality of active areas in the peripheral portion and the at least one of the plurality of wordlines in the peripheral portion and the at least one of the plurality of conductive plugs in the array portion to form a local interconnect between the array portion and the peripheral portion.