Patent ID: 8018238

Claim:
A capacitance measurement system comprising: (a) a successive approximation register analog-to-digital conversion circuit (SAR ADC) including 1. a comparator, 2. a divider/feedback CDAC (capacitor digital-to-converter) including a plurality of weighted CDAC capacitors each having a first terminal coupled to a corresponding one of a plurality of conductors, respectively, and each having a second terminal coupled by a first conductor to a first input of the comparator, 3. SAR logic and switch circuitry which produces a digital output on a digital bus, an output of the comparator being coupled to an input of the SAR logic and switch circuitry, the SAR logic and switch circuitry being coupled to control the plurality of conductors during a SAR conversion, and 4. a first switch having a first terminal coupled the first input of the comparator; and (b) an active network for coupling a capacitor to be measured to the SAR ADC, the active network including 1. a measurement conductor coupled to a first terminal of the capacitor to be measured, 2. an amplifier for performing the function of aiding charge redistribution among the capacitance to be measured and the CDAC capacitors during a measurement phase, the amplifier having a first input coupled to a second terminal of the first switch, a second input coupled to a first reference voltage and an output coupled to an amplifier output conductor, and 3. a first switching circuit for coupling the amplifier output conductor to the plurality of conductors during the measurement phase.