Patent ID: 7143500

Claim:
A method of forming a probe card for use in the testing of a semiconductor device comprising: providing a substrate having a first surface, a second surface, and an aperture therethrough; disposing a plurality of conductive traces adjacent at least one of the first surface and the second surface; providing a plurality of probe elements in electrical communication with the plurality of conductive traces, at least a first one of the plurality of probe elements configured for supplying a test signal, and at least a second one of the plurity of probe elements configured for receiving a test signal, the plurality of probe elements having a portion thereof located on the first surface of the substrate, having a portion thereof extending through the aperture in the substrate, and having a portion thereof located on the second surface of the substrate; and providing a plurality of fuse elements in respective electrical communication with at least some of the plurality of conductive traces, at least some of the plurality of fuse elements disposed immediately adjacent at least one of the first surface and the second surface, the at least some of the plurality of fuse elements comprising at least two types of fuses of an active fuse element, a passive fuse element, a self-resetting fuse element, a repairable fuse element, and a replaceable fuse element, each fuse element of the plurality of fuse elements for limiting the current level thereof to one of an absolute maximum current level for the probe card without substantial damage thereto and an absolute current level for use in the testing of a semiconductor device without substantial damage thereto.