Patent ID: 8179739

Claim:
A semiconductor device comprising: a plurality of word lines; a plurality of bit-lines intersecting the plurality of word lines; a plurality of memory cells arranged at intersection points of the plurality of word lines and the plurality of bit-lines; a block of word drivers for controlling the plurality of word lines; a sense amplifier for discriminating read signals generated in the plurality of bit-lines; a first voltage supply line arranged in parallel with the plurality of bit-lines; a first plurality of buffer cells which are arranged at intersection points of the plurality of word lines and the first voltage supply line and are not connected to the first voltage supply line; a second voltage supply line arranged in parallel with the plurality of word lines; and a second plurality of buffer cells which are arranged at intersection points of the plurality of bit-lines and the second voltage supply line and are not connected to the plurality of bit-lines, wherein the first plurality of buffer cells are arranged between the block of word drivers and the plurality of memory cells, the second plurality of buffer cells are arranged between the sense amplifier and the plurality of memory cells, and each of the plurality of memory cells includes a first resistive storage element and a first select transistor.