Patent ID: 6977966

Claim:
A method of transmitting and recovering a stream of coded data bits without establishing a timing or phase lock, comprising the steps of: generating a stream of data bits at a selected frequency, each bit of said stream of data bits having one portion at a first voltage level and another portion at a second voltage level; generating a stream of clocking pulses at a second frequency, which second frequency is a multiple of said selected frequency; coding said stream of data bits by setting said one portion of each bit to a reference voltage level; continuously switching said another portion of each bit between said reference voltage level and another voltage level different than said reference voltage level at said second frequency; transmitting said coded data stream from a first location to another location; receiving said coded data stream and providing said coded data stream to a delay circuit and a combining circuit; delaying said coded data stream at said delay circuitry for a period of time substantially equal to one-half cycle of said second clocking frequency and providing said delayed coded data stream to said combining circuit; and combining said coded data stream and said delayed coded data stream to recover said stream of data bits at said selected frequency.