Patent ID: 8114744

Claim:
A method of fabricating an integrated circuit including a plurality of MOS transistors, comprising: providing a substrate having a silicon comprising surface; forming a plurality of dielectric filled trench isolation regions in said substrate, wherein said silicon comprising surface forms trench isolation active area edges along its periphery with said trench isolation regions; depositing a first silicon comprising layer, said first silicon comprising layer extending from a surface of said trench isolation regions over said trench isolation active area edges to said silicon comprising surface; oxidizing said first silicon comprising layer to completely convert said first silicon comprising layer to a silicon oxide layer, wherein said silicon oxide layer provides at least a portion of a gate dielectric for at least one of said plurality of MOS transistors; and forming a patterned gate electrode layer over said gate dielectric, wherein said patterned gate electrode layer extends over at least one of said trench isolation active area edges to said silicon comprising surface.