Patent ID: 6924561

Claim:
A memory device, comprising: a first pair of fins comprising a first fin and a second fin formed substantially parallel to one another, the first fin and second fin having a first width and being located a distance from one another that is approximately twice the first width; a second pair of fins comprising a third fin and a fourth fin formed substantially parallel to one another, the third fin and fourth fin having the first width and being located a distance from one another that is approximately twice the first width, wherein the second fin and the third fin are formed substantially parallel to one another and located a distance from one another that is approximately four times the first width; a source region formed at one end of each of the fins; a drain region formed at an opposite end of each of the fins; a gate formed over the first fin and the second fin; a wordline formed over each of the fins; and a bitline contact formed adjacent at least one of the fins.