Patent ID: 8533248

Claim:
A processing unit, comprising: a floating point multiply-add circuit that receives three inputs, which are rs 1 , rs 2 and rs 3 , and executes floating point multiply-add operation; a resistor file that the floating point multiply-add circuit uses; an OR circuit that computes OR of the most significant bit of output of the floating point multiply-add circuit and the least significant bit rs 2 [0] of the input rs 2 , and outputs a signal indicating a type of expansion function of Taylor series expansion; a selector that selects either the input rs 1 or the value “1.0”; and an EOR circuit that computes EOR of a bit rs 2 [1] that is one bit higher than the least significant bit of the input rs 2 and the most significant bit of the selector, and outputs a sign bit of the expansion function.