Patent ID: 7848171

Claim:
A semiconductor memory device comprising: a cell array having a plurality of memory cells arranged in a matrix; a plurality of word lines configured to correspond to each row of the cell array, and each connected to the memory cell; a plurality of bit lines configured to correspond to each column of the cell array, and each connected to the memory cell; a plurality of switching circuits provided to correspond to each bit line, each one terminal of the switching circuits being connected to the corresponding bit line; and a leakage current compensating circuit having an output node connected in common to another terminal of the switching circuits, the switching circuits being each controlled so that only a circuit connected to a bit line of a selected column in the cell array conducts, wherein the leakage current compensating circuit comprises a plurality of MOSFETs, each of the MOSFETs has the same conductivity type as a MOSFET directly connected to the bit line and included in each of the memory cells, each of the MOSFETs of the leakage current compensating circuit has a current path and a gate electrode, one end of the current path is connected to the other terminal of the switching circuits, the gate electrode is connected to a first voltage node and another end of the current path is connected to a second voltage node, and each of the MOSFETs is biased to turn off.