Patent ID: 7290023

Claim:
A floating point unit (FPU), comprising: an exponent logic (EL), comprising: an exponent operand selection logic configured to receive a first exponent signal Ea, a second exponent signal Eb, and a third exponent signal Ec, and to generate first intermediate signal Ex, second intermediate signal Ey, and third intermediate signal Ez based on signals Ea, Eb, and Ec; a 3:2 compressor configured to receive the signals Ex, Ey, and Ez, and to generate a carry signal and a sum signal based on the signals Ex, Ey, and Ez; and a 3-way compound adder configured to receive the carry signal, the sum signal, and the signal Ez, and to generate a first EL output signal S0, a second EL output signal S1, and a third EL output signal S2 based on the received carry signal, sum signal and signal Ez; wherein the signal S0 represents an exponent value “e”, the signal S1 represent the exponent value “e+1”, and the signal S2 represents the exponent value “e+2”; an exponent adjust and rounding logic (EAD) coupled to the EL and to a result generator, the EAD configured to receive the signals S0, S1, and S2, an inverted anticipated leading zero shift signal (!LZA), a corrected leading zero shift signal (LZA_CORR), and a special case signal, the EAD configured to: generate a first output signal E2A based on the received S1 and !LZA signals; generate a second output signal E2B based on the received S2 and !LZA signals; generate a results select signal based on the received signals S0, S1, S2, !LZA, LZA_CORR and the special case signal; and transmit the results select signal, and the signals E2A and E2B to the result generator.