Patent ID: 8332802

Claim:
A method for optimizing power consumption and timing in an integrated circuit design, the method performed by a programmed computer in conjunction with a timing tool and an integrated circuit model defined by a placement and routing tool, the method comprising: receiving configuration information including an integrated circuit model generated by a placement and routing tool, path specific variables, and a first run-time option associated with a timing path group; preserving timing critical hold paths by identifying cells in the hold timing paths and storing an identifier for the cells in a hold cells storage element; performing, using said programmed computer, a leakage power optimization analysis on the integrated circuit model that is responsive to a slow corner timing database and timing constraints for a slow corner, the leakage power optimization analysis configurable in accordance with the path specific variables and including a routine that repairs register transition violations, wherein the leakage power optimization analysis is performed on a select number of paths before an adjusted timing slack value is determined and wherein cells are addressed in response to a number of failing timing paths associated with a cell, the leakage optimization analysis storing cell instances and types in a second storage element; receiving information from the second storage element and swapping cells with specified cell types; updating a timing database in response to modified cells; identifying and storing register transition violations in a third storage element; and generating information in a router compatible format that identifies a desired modification of the integrated circuit design, wherein identified hold timing failures on input/output paths are addressed by inserting a circuit element at the top level of the integrated circuit model.