Patent ID: 8495540

Claim:
A computer-implemented method to simulate an electronic design layout, the method comprising: selecting one of a plurality of signal conductors included in the electronic design layout, the electronic design layout including the plurality of signal conductors and a plurality of metal fills that are void from carrying an electrical signal, wherein a plurality of metal fill grid points are positioned on each of the plurality of metal fills; assigning, by one or more processing devices, a first potential to the selected signal conductor and assigning a second potential to one or more non-selected signal conductors, the first potential different than the second potential; selecting, by one or more of the processing devices, one of the plurality of metal fills and generating a zero charge equation for the selected metal fill, the zero charge equation establishing that a total charge residing on the selected metal fill is equal to zero; including the zero charge equation in a system of equations, the system of equations including a plurality of grid point potential equations; assigning a metal fill grid point potential variable to one of the plurality of metal fill grid points positioned on the selected metal fill; including the metal fill grid point potential variable in one of the plurality of grid point potential equations corresponding to a neighboring metal fill grid point adjacent to the selected metal fill; solving the system of equations using a processor, resulting in one or more solutions; computing capacitance values for the plurality of signal conductors based upon the one or more solutions; and simulating the electronic design layout using the computed capacitance values; wherein the selected signal conductor is located on a first substrate layer, the selected metal fill is located on a second substrate layer, and one of the non-selected signal conductors are located on a third substrate layer, wherein the second substrate layer is located between the first substrate layer and the third substrate layer.