Patent ID: 8201003

Claim:
A circuit of an electronic device, comprising: a Southbridge chip comprising a power good pin, a signal on the power good pin of the chip related to a computer power up/down sequence of the electronic device; a first switching transistor circuit with an input terminal to receive a power good signal, and an output terminal connected to the power good pin of the Southbridge chip of the electronic device; and a second switching transistor circuit with an input terminal to receive a S3 sleep signal, and an output terminal connected to the power good pin of the Southbridge chip; wherein during the computer power down sequence of the electronic device, the S3 sleep signal falls low before the power good signal, and the S3 sleep signal is active and fed to the power good pin of the Southbridge chip, thereby decreasing a delay time of the power good signal fed to the Southbridge chip and confirming the power down sequence is correct.