Patent ID: 7193887

Claim:
A static ram cell comprising: a pair of cross-coupled transistors each having a gate node and a channel between a source node and drain node, a first transistor of the pair having the drain node connected to the gate node of a second transistor of the pair, and the second transistor of the pair having the drain node connected to the gate node of the first transistor of the pair, the source node of the first transistor of the pair being a true bit line and the source node of the second transistor of the pair being a complement bit line; and a pair of diode-connected transistors, each having a gate node and a channel between a source node and drain node, wherein the channel of a first of the pair of diode-connected transistors is connected between the drain of the first of the cross-coupled transistors and a word line, and wherein the channel of a second of the pair of diode-connected transistors is connected between the drain of the second of the cross-coupled transistors and the word line.