Patent ID: 7978550

Claim:
A semiconductor memory comprising: a plurality of regular memory cells; a first redundant memory cell which is arranged at one end of a region of the regular memory cells; a second redundant memory cell which is arranged at the other end of the region of the regular memory cells; a first redundancy program circuit corresponding to the first redundant memory cell, wherein first defect position information indicating a position of a first defective regular memory cell is programmed into the first redundancy program circuit; a second redundancy program circuit corresponding to the second redundant memory cell, wherein second defect position information indicating a position of a second defective regular memory cell is programmed into the second redundancy program circuit; a redundancy switch circuit which couples signal lines to the regular memory cell, the first redundant memory cell, and the second redundant memory cell in response to the first defect position information and the second defect position information; and a redundancy signal switch circuit which replaces the first defect position information and the second defect position information with each other when the second defective regular memory cell is located between the first defective regular memory cell and the first redundant memory cell.