Patent ID: 7191314

Claim:
A reconfigurable control structure for CPUs, comprising: a first control unit with a first instruction set of basic instructions associated therewith, wherein the first control unit is configured as a finite state machine that is able to assume an inoperative state and at least one active state for execution of a respective instruction comprised in the first instruction set; a second control unit, with a second instruction set of selectively modifiable instructions associated therewith, wherein the second control unit is configured as a finite state machine that is able to assume an inoperative state and at least one active state for execution of a respective instruction comprised in the second instruction set; a programming element associated with said second control unit for rendering said second instruction set selectively modifiable; at least one circuit element for supplying instruction codes to be executed to said first control unit and to said second control unit, so that each instruction can be executed under the control of at least one between said first control unit and said second control unit according to whether each instruction is comprised within at least one between said first instruction set and said second instruction set, wherein the at least one circuit element is configured for sending the instruction codes to be executed in an undifferentiated way to the first control unit and the second control unit; a selector module configured for recognizing whether the instruction to be executed each time supplied by the at least one circuit element belongs to the first instruction set or to the second instruction set, wherein the control units have respective state outputs for outputting state information and respective state inputs for receiving state information; a single state register having an output connected to the state inputs of the control units; and a multiplexer having first and second inputs coupled respectively to the state outputs of the control units, the multiplexer driven by the selector module and configured for sending the state register a state signal identifying which of the first and second control units generates the control signals for the instructions to be executed.