Patent ID: 7711328

Claim:
A method of sampling a frequency difference in an integrated circuit, said method comprising the steps of: receiving a first clock signal in a first clock domain; comparing a count of said first clock signal in said first clock domain to a predetermined value N; converting a result of said comparison to a second clock domain; generating a sample signal used to load a counter for generating a count of a second clock signal in said second clock domain with said predetermined value N; coupling said sample signal to an enable input of an output register operating in said second clock domain; latching, to said output register in response to said sample signal, a count associated with a difference between a count of said first clock signal and a count of said second clock signal in said second clock domain using said result of said comparison converted to said second clock domain; and generating an error signal representing said difference between said count of said first clock signal and said count of said second clock in said second clock domain.