Patent ID: 8804817

Claim:
A digital television (DTV) transmitting system for processing broadcast data, the DTV transmitting system comprising: a randomizer circuitry for randomizing enhanced data; a Reed-Solomon (RS) frame encoder circuitry for generating an RS frame by RS encoding an RS frame payload with an RS code of (187+P, 187) and Cyclic Redundancy Check (CRC)-encoding the RS-encoded RS frame payload, wherein the RS frame comprises (187×N) bytes including the randomized enhanced data output from the randomizer, P bytes of RS parity data added at a bottom of each column of the (187×N) bytes and 2 bytes of CRC data added at a right end of each row of the ((187+P)×N) bytes, wherein P and N are greater than 1; a block processor circuitry for encoding the data in the RS frame output from the RS frame encoder at a coding rate of 1/N1, wherein N1 is an integer greater than 1; a group formatter circuitry for mapping a portion of the data encoded at the coding rate of 1/N1 by the block processor to a data group, wherein the group formatter adds known data sequences, main data place holders, moving picture experts group (MPEG) header place holders, and RS parity data place holders to the data group, and wherein at least two of the known data sequences are spaced 16 segments apart; a deinterleaver circuitry for deinterleaving data of the data group output from the group formatter; a packet formatter circuitry for removing the main data place holders and the RS parity data place holders in the deinterleaved data group output from the deinterleaver and replacing the MPEG header place holders in the deinterleaved data group output from the deinterleaver with MPEG headers having a packet identifier, in order to output enhanced data packets; an RS encoder circuitry for inserting first RS parity data into the enhanced data packets output from the packet formatter; an interleaver circuitry for interleaving data of the enhanced data packets including the first RS parity data output from the RS encoder; a trellis encoder circuitry for trellis-encoding the interleaved data output from the interleaver, the trellis encoder including at least one memory that is initialized by initialization data at each start of the known data sequences; and a compatible processor for calculating second RS parity data based on the initialization data output from the trellis encoder, to replace replacing corresponding first RS parity data of the first RS parity data with the calculated second RS parity data and outputting the second RS parity data replacing the corresponding first RS parity data to the trellis encoder.