Patent ID: 7521987

Claim:
An output voltage select circuit, comprising: a control circuit coupled to receive mode select signaling and configured to provide a first control signal, a second control signal, and a third control signal responsive at least in part to the mode select signaling; a first level shifter coupled to receive the first control signal; a second level shifter coupled to receive the second control signal; a first P-channel transistor coupled to receive the first control signal at a gate node thereof and coupled to a first supply voltage at a source node thereof; a second P-channel transistor coupled to receive the second control signal at a gate node thereof and coupled to a second supply voltage at a source node thereof; the first supply voltage and the second supply voltage during a non-power-on-reset operative condition having a first voltage level and a second voltage level which are operationally different from one another; a third P-channel transistor having a source node coupled to a drain node of the first P-channel transistor; a drain node of the third P-channel transistor coupled to an output node; a gate node of the third P-channel transistor coupled to receive an output from the first level shifter; a fourth P-channel transistor having a source node coupled to a drain node of the second P-channel transistor; a drain node of the fourth P-channel transistor coupled to the output node; a gate node of the fourth P-channel transistor coupled to receive an output from the first level shifter; an N-channel transistor coupled to receive the third control signal at a gate node thereof; a source node of the N-channel transistor coupled to a ground, the ground being at a third voltage level; a drain of the N-channel transistor coupled to the output node; output voltage at the output node selectable as between the first voltage level, the second voltage level, and the third voltage level responsive to the first control signal, the second control signal, and the third control signal, respectively, during the non-power-on-reset operative condition; only one of the first control signal, the second control signal, and the third control signal being asserted at a time during the non-power-on-reset operative condition; and the output node being electrically decoupled from the first supply voltage, the second supply voltage, and the ground during a power-on-reset operative condition responsive to a power-on reset signal.