Patent ID: 7096344

Claim:
A parallel processor for processing a plurality of operation instructions in one cycle in parallel, comprising: a first operation processor; and at least one second operation processor which runs by an extended instruction supplied from the first operation processor, wherein the extended instruction includes a first code for the first operation processor and a second code for the second operation processor, the first operation processor including, a control unit for, in case that an operation mode indicating whether or not the second operation processor should be run in parallel to carry out an operation instruction is a first operation mode, in accordance with the operation mode, supplying the first operation processor with an instruction sequence that defines an operation of the first operation processor, and for generating a control signal to halt an operation of the second operation processor and supplying the control signal to the second operation processor, and an instruction execution unit for switching the operation mode in accordance with an input decoded instruction, wherein the operation mode has a first operation mode in which the first operation processor alone is operated, and a second instruction mode in which both of the first operation processor and the second operation processor are operated, and the extended instruction comprises only the first code in the first operation mode.