Patent ID: 8493124

Claim:
A level shifter, comprising: a first NMOS transistor, a source of the first NMOS transistor arranged to be coupled to a low power supply voltage; a second NMOS transistor; a voltage input node arranged to receive an input signal and coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor, wherein the input signal has a voltage level up to a first power supply voltage; a first PMOS transistor configured to selectively turn completely off, a source of the first PMOS transistor arranged to be coupled to a second power supply voltage that is higher than the first power supply voltage, a gate of the first PMOS transistor arranged to be coupled to a drain of the second NMOS transistor; a voltage output node arranged to supply an output signal and to be coupled between the first PMOS transistor and the first NMOS transistor; a second PMOS transistor, a source of the second PMOS transistor arranged to be coupled to the second power supply voltage and a drain of the second PMOS transistor arranged to be coupled to a drain of the second NMOS transistor; and a third PMOS transistor arranged to be coupled to the first PMOS transistor, wherein a gate of the third PMOS transistor is coupled to the voltage input node, wherein the first NMOS transistor is arranged to pull down the output signal to a low logic level when the input signal is a first logic level, and the second NMOS transistor is arranged to enable the first PMOS transistor to pull up the output signal to a high logic level at the second power supply voltage when the input signal is a second logic level.