Patent ID: 7917753

Claim:
A system, comprising: a processor configured to operate at a plurality of security levels comprising a first security level and a second security level; a memory system coupled to the processor, the memory system stores a first program that executes on the processor at the first security level, and further stores a second program that executes on the processor at the second security level; and a register configured to store an entry point address to the first program, wherein an instruction that executes on the processor at the second security level is blocked from writing values to the register; wherein a transfer of control from the second program to the first program is executed if the register provides the entry point address to the first program; wherein the transfer of control from the second program to the first program is blocked if the entry point address to the first program is not provided by the register; and wherein an exception is signaled to the processor indicative of a security violation when the transfer of control from the second program to the first program is not provided by the register, and wherein an exception handler, executed by the processor in response to the exception, blocks the transfer of control.