Patent ID: 8239807

Claim:
A method for generating a standard cell layout pattern for standard cell placement in an integrated circuit, comprising: identifying one or more congestion zones in a congestion map, wherein the congestion map is generated by an Electronic Design Automation (EDA) tool and includes a plurality of bounding boxes, and wherein the EDA tool generates routing tracks data corresponding to each bounding box; calculating values of an average vertical congestion (H) and an average horizontal congestion (V) corresponding to each of the identified congestion zones using the routing tracks data; calculating a value of a modified standard cell density for at least one of the identified congestion zones using the values of the average vertical congestion (V), the average horizontal congestion (H), and an unmodified standard cell density (D 0 ), wherein calculation of the modified standard cell density (D mod ) is mathematically represented as D mod =D 0 /H×V, and wherein the unmodified standard cell density is generated by the EDA application; calculating dimensions of a layout pattern unit, wherein the layout pattern unit comprises a keep-out region and a placement region, wherein one or more standard cells are placed in the placement region, and wherein the keep-out region comprises one or more routing tracks; and arranging one or more layout pattern units to form the standard cell layout pattern, wherein at least one routing track in a keep-out region of a first layout pattern unit overlaps with at least one routing track in a keep-out region of a second layout pattern unit.