Patent ID: 7848581

Claim:
A circuit comprising: a decoder coupled to a data input, the decoder configured to decompress data provided by the data input and provide a sequence of blocks of decompressed data; a horizontal resize unit coupled to the decoder, the horizontal resize unit resizing each block of decompressed data in sequence along a horizontal axis, thereby creating a sequence of horizontally resized blocks of decompressed data; and a vertical resize unit coupled to the horizontal resize unit, the vertical resize unit resizing the sequence of horizontally resized blocks along a vertical axis, thereby creating a sequence of horizontally and vertically resized blocks of decompressed data; a memory coupled to the vertical resize unit, the memory to store the sequence of horizontally and vertically resized blocks of decompressed data; and a reorder data unit coupled to the memory, the reorder data unit configured to rearrange the sequence of horizontally and vertically resized blocks of decompressed data into a format suitable for display.