Patent ID: 8319673

Claim:
An analog-to-digital converter system comprising: a generator circuit configured to generate a digital dither code selected from a sequence of digital dither codes that is at least pseudo random; a first circuit for offsetting a sampled analog voltage using the digital dither code; a first analog-to-digital converter configured to provide a first digital code representing the sampled analog voltage with an offset induced by the digital dither code; a combiner configured to combine the first digital code and the digital dither code to substantially cancel the offsetting of the sampled analog voltage, the combiner providing a first numerical representation of the sampled analog voltage with respect to a reference voltage range; and a digital circuit configured to scale and truncate the first numerical representation to derive a second numerical representation of the sampled analog voltage with respect to a full-scale range of the analog-to-digital converter system, wherein a width of the reference voltage range is greater than a width of the full-scale range, and wherein a least significant bit size of the first numerical representation is smaller than a least significant bit size of the second numerical representation.