Patent ID: 7479698

Claim:
A bonding pad structure disposed in a semiconductor device, the semiconductor device having a substrate, the bonding pad structure comprising: a connection structure, for allowing a direct connection from a bonding wire; and an induction structure, coupled with the connection structure, for lowering an effective capacitance C eff between the bonding wire and the substrate, the induction structure comprising at least a metal layer; wherein the effective capacitance C eff satisfies a formula as below: C eff = 1 1 C pad + 1 C para - 1 ω 2 ⁢ L wherein C pad is an effective capacitance between the bonding wire and the metal layer, L is an effective inductance between the metal layer and the substrate, C para is a parasitic capacitance within the induction structure, and ω is a signal frequency; C eff is smaller than C pad in a specific frequency range, and C eff is substantially equal to zero under a condition of ω=1/√{square root over (LC para )}.