Patent ID: 7991101

Claim:
A communication device that is operable to generate a plurality of synchronized clock signals, comprising: an input that is operable to receive a master clock signal; a plurality of phase rotators that includes a first phase rotator and a second phase rotator, wherein: the master clock signal is provided to each phase rotator of the plurality of phases rotators; the first phase rotator is operable to perform a first phase rotation of the master clock signal thereby generating a first phase rotated clock signal; and the second phase rotator is operable to perform a second phase rotation of the master clock signal thereby generating a second phase rotated clock signal; and a plurality of dividers, wherein: a first divider of the plurality of dividers is operable to process the first phase rotated clock signal and an asynchronous master reset signal thereby generating a first synchronized clock signal of the plurality of synchronized clock signals and a set signal; and a second divider of the plurality of dividers is operable to process the second phase rotated clock signal and the set signal thereby generating a second synchronized clock signal of the plurality of synchronized clock signals.