Patent ID: 7195976

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate with first conductor patterns formed over a memory cell forming region and a peripheral circuit region of said semiconductor substrate and with grooves formed in self-alignment with said first conductor patterns in said memory cell forming region and in said peripheral circuit region, such that said grooves extend in said semiconductor substrate and such that a groove, of said grooves, in said peripheral circuit region defines an active region of an MISFET in said peripheral circuit region; (b) filling a first insulating film in said grooves; (c) forming a second conductor pattern over said first conductor patterns and said first insulating film; (d) forming a second insulating film over said second conductor pattern; (e) forming a conductive film over said second insulating film; and (f) patterning said conductive film, said second conductor pattern and said first conductor patterns in said peripheral circuit region and in said memory cell forming region, wherein, in said step (f), the conductive film, of said memory cell forming region, is patterned to form a control gate electrode of a memory cell, wherein, in said step (f), said second conductor pattern and said first conductor pattern of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and wherein, in said step (f), at least said second conductor pattern and the first conductor pattern of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.