Patent ID: 7573970

Claim:
A prescaler comprising: a buffer including a first amplification circuit which amplifies an input signal and generates an output signal, with the first amplification circuit having a variable drive capacity, and a feedback circuit which feeds back the output signal of the first amplification circuit to the first amplification circuit, with the feedback circuit having a variable resistance; and a frequency divider which divides the output signal by a predetermined frequency dividing ratio to generate a divisional signal; the first amplification circuit including: a plurality of inverter circuits each having an input terminal and an output terminal, with the inverter circuits having different drive capacities; and a selection circuit coupled to the inverter circuits and the feedback circuit; wherein the selection circuit includes: a first switch circuit, coupled to the input terminal of each of the inverter circuits, for selecting one of the inverter circuits in response to a control signal, with the inverter circuits including one or more inverter circuits coupled to ground via the first switch circuit and the inverter circuit selected by the first switch circuit; and a second switch circuit, coupled to the output terminal of each of the inverter circuits, for coupling the inverter circuit selected by the first switch circuit to the feedback circuit in response to the control signal and discoupling the one or more inverter circuits from the feedback circuit.