Patent ID: 8008719

Claim:
A device, comprising: a transistor having a gate, a drain region, and a source region where the drain and the source region are of a first conductivity type; a trench in proximity to the drain region of the device where the trench has a sidewall and a major surface; a first dielectric layer overlying the sidewall and the major surface of the trench; and a first conductive layer overlying the sidewall of the trench where the first conductive layer does not overlie a majority of the major surface of the trench; a second dielectric layer overlying the first conductive layer; a second conductive layer overlying the second dielectric layer; wherein the first dielectric layer and the second dielectric layer comprise silicon dioxide; and further comprising a third dielectric layer overlying a portion of the first dielectric layer and underlying a portion of the first conductive layer, and a fourth dielectric layer overlying a portion of the second conductive layer and underlying a portion of the second dielectric layer.