Patent ID: 8489944

Claim:
An integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a point-to-point channel, the integrated circuit comprising: an inbound redrive circuit to receive and redrive signals on an inbound path of the point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the point-to-point channel; an outbound redrive circuit to receive and redrive signals on an outbound path of the point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the point-to-point channel; logic coupled with the outbound path of the point-to-point channel, the logic to calibrate a newly appended memory agent responsive, at least in part, to receiving a command; and a double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit.