Patent ID: 8329510

Claim:
A method of making a semiconductor chip assembly, comprising: providing a post, a base, an ESD protection layer, a metal layer, an adhesive and a conductive layer, wherein the post is adjacent to the base, extends above the base in an upward direction, extends into an opening in the adhesive and is aligned with an aperture in the conductive layer, the base extends below the post in a downward direction opposite the upward direction and extends laterally from the post in lateral directions orthogonal to the upward and downward directions, the ESD protection layer is a thermally conductive, electrically insulative material that contacts and is sandwiched between the base and the metal layer, extends below the base and extends laterally beyond the post, the metal layer extends below the ESD protection layer and extends laterally beyond the post, the adhesive is mounted on and extends above the base, is sandwiched between the base and the conductive layer and is non-solidified, and the conductive layer is mounted on and extends above the adhesive; then flowing the adhesive into and upward in a gap located in the aperture between the post and the conductive layer; solidifying the adhesive; then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, wherein providing the pad includes: grinding the post, the adhesive and the conductive layer such that the post, the adhesive and the conductive layer are laterally aligned with one another at a top lateral surface that faces in the upward direction; and then removing selected portions of the conductive layer using an etch mask that defines the pad; providing a heat spreader that includes the post, the base, the ESD protection layer and an underlayer that includes at least a portion of the metal layer; then mounting a semiconductor device on the post, wherein the semiconductor device overlaps the post, the base, the ESD protection layer and the underlayer, the semiconductor device, the post and the base are electrically isolated from the underlayer and the underlayer covers the post in the downward direction; electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and thermally connecting the semiconductor device to the post, thereby thermally connecting the semiconductor device to the underlayer.