Patent ID: 7825479

Claim:
A semiconductor structure comprising: a gate dielectric located on a semiconductor layer and comprising a first gate dielectric portion, a second gate dielectric portion laterally abutting said first gate dielectric portion, and a third gate dielectric portion laterally abutting said second gate dielectric portion and spaced from said first gate dielectric portion by said first gate dielectric portion, wherein said first gate dielectric portion has a first horizontal top surface and a first horizontal bottom surface separated by a constant distance of a first thickness, said second gate dielectric portion has a second horizontal top surface and a second horizontal bottom surface separated by another constant distance of a second thickness, said third gate dielectric portion has a third horizontal top surface and a third horizontal bottom surface separated by a constant distance of a third thickness, and said first thickness is greater than said second thickness and said third thickness is greater than said second thickness; a gate electrode vertically abutting said first horizontal top surface of said first gate dielectric portion and said second horizontal top surface of said second gate dielectric portion; a source region directly contacting an edge of said first gate dielectric portion; and a drain region directly contacting an edge of said third gate dielectric portion; wherein said first horizontal bottom surface of said second gate dielectric portion is vertically offset and lower within the substrate from said horizontal bottom portion of said first and third gate dielectric portions and the said first and third gate dielectric portions have horizontal bottom surfaces on the major plane of the semiconductor substrate.