Patent ID: 7397104

Claim:
A semiconductor integrated circuit device comprising: an active region having a substantially elliptical shape having a long axis and a short axis, a semiconductor element formed in said active region, a gate electrode which extends in a direction which is parallel to said short axis of said active region and across said active region, and a shallow groove isolation surrounding said active region, wherein a peripheral portion of said active region is shaped in a form of a section that is rounded by round processing using a sidewall spacer as a mask. wherein a sum of a size of the short axis of said active region and a width of said shallow groove isolation, in said direction which is parallel to the short axis of said active region, constitutes a minimum pitch, wherein one-half of said minimum pitch is a minimum processing size determined according to a resolution limit of a photolithographic process used to form the semiconductor integrated circuit device, and wherein the size of the short axis of said active region after removal of said sidewall spacer is set larger than one-half of said minimum pitch.