Patent ID: 8593178

Claim:
A CMOS logic circuit, comprising: a resistive element connected to a first voltage line at a first end thereof and is characterized by an impedance being nonlinear with an applied voltage; a first inverter circuit having a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, the first MOS transistor being connected to a second end of the resistive element at a first end thereof, to a first output terminal at a second end thereof, and to an input terminal at a gate thereof, and the second MOS transistor being connected to the second end of the first MOS transistor at a first end thereof, to a second voltage line at a second end thereof, and to the gate of the first MOS transistor at a gate thereof; a second inverter circuit having a third MOS transistor of the first conductivity type and a fourth MOS transistor of the second conductivity type, the third MOS transistor being connected to the first voltage line at a first end thereof, to a second output terminal at a second end thereof, and to the first output terminal at a gate thereof, and the fourth MOS transistor being connected to the second end of the third MOS transistor at a first end thereof, to the second voltage line at a second end thereof, and to the gate of the third MOS transistor at a gate thereof; a fifth MOS transistor of the first conductivity type, which is connected in parallel with the resistive element and a control terminal is connected to the second end of the third MOS transistor; and a sixth MOS transistor of the first conductivity type, which is connected in parallel with the resistive element and a control terminal is connected to the second end of the third MOS transistor, wherein, when the fifth MOS transistor is turned off, the first MOS transistor is configured to be turned off and a voltage potential at the first output terminal lowers, and the fourth MOS transistor is configured to be turned off by lowering the voltage potential at the first output terminal.