Patent ID: 7688646

Claim:
A nonvolatile latch circuit, comprising: an input control unit controlling data according to a power on reset signal, in response to a data transition detection signal, and in response to a delay signal, and storing and latching the data as a non-volatile state according to a control signal; a data control unit selecting one of an output and an input data of the input control unit according to the control signal, and outputting the delay signal synchronized with a clock enable signal; a storage control unit outputting the control signal according to the power on reset signal and in response to the data transition detection signal; a clock control unit outputting the clock enable signal in response to a clock, in response to a pull down enable signal, and in response to a pull up enable signal; a data transition detecting unit outputting the data transition detection signal by detecting whether the delay signal transitions; and a data output unit selectively outputting the output data according to the delay signal and in response to the latch output enable signal.