Patent ID: 7910434

Claim:
A method of forming an array of non-volatile memory cells on a semiconductor substrate surface, comprising: forming a plurality of shallow trench isolation structures that extend in a first direction; forming a plurality of first conductive portions that extend in the first direction, the forming a plurality of first conductive portions includes: forming a layer of conductive material over the plurality of shallow trench isolation structures; forming a first slot over an individual one of the plurality of shallow trench isolation structures, a plurality of first slots are formed; and removing a portion of the layer of conductive material below each of the plurality of slots; forming a plurality of second conductive portions, forming an individual one of the second conductive portions includes: forming a second slot over an individual one of the first conductive portions, the second slot being narrower than the individual first conductive portion in a second direction that is perpendicular to the first direction; and forming the individual second conductive portion in the second slot over the individual first conductive portion, the individual second conductive portion in electrical contact with the individual first conductive portion; and forming a plurality of floating gates by etching the first conductive portions and the second conductive portions.