Patent ID: 7679977

Claim:
A semiconductor memory device comprising a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, said memory cell array including plural pages of the memory cells, and plural registers, including a temporal register, a trimming register, and an address register, wherein the device has such a test mode that includes a page searching sequence for searching and identifying the fast page that can be written in the fastest write speed among pages in the memory cell array and which determines a value of a program voltage Vpgm that is applied to the memory cells at the beginning of a data write operation in relation to the identified fast page; wherein said page searching sequence comprises, externally setting a preliminary write voltage initial value in the temporal register, writing data in multiple blocks in the memory cell array with write voltages sequentially stepped-up from the preliminary write voltage initial value until at least one bit is verified to be written for each page, transferring a write voltage currently stored in the temporal register to the trimming register as a write voltage initial value after write-verifying each page when it is lower than that stored in the trimming register, and registering a page address of the fast page defined by the write voltage initial value stored in the trimming register in the address register.