Patent ID: 7804721

Claim:
An apparatus comprising: a memory configured to store a plurality of data items, wherein each data item has a type which is one of a plurality of types of data items, and wherein the memory is divided into a plurality of sections, wherein each section corresponds to a respective type of the plurality of types and is configured to store data items of the respective type; write control logic coupled to the memory and configured to operate in a write clock domain, wherein the write control logic is configured to maintain a plurality of first write pointers, wherein each of the plurality of first write pointers corresponds to the respective type of the plurality of types and identifies a location in the memory; read control logic coupled to the memory and configured to operate in the read clock domain, wherein the read control logic is configured to maintain a plurality of second write pointers, wherein each of the plurality of second write pointers corresponds to the respective type of the plurality of types and identifies a location in the memory; a first-in, first-out buffer (FIFO) coupled to the write control logic and the read control logic, wherein the write control logic is configured to pass a write event indicating a write of an input data item in the memory to the read control logic through the FIFO.