Patent ID: 8525317

Claim:
An integrated chip package, comprising: a plurality of semiconductor chips, wherein each of the plurality of semiconductor chips comprises (i) a first surface, and (ii) first conductive bumps; an intermediate substrate configured to electrically connect to the first surfaces of the plurality of semiconductor chips via the first conductive bumps of the plurality of semiconductor chips, wherein the intermediate substrate is configured to convert flip chip mounting of the plurality of semiconductor chips to wire bond mounting of the plurality of semiconductor chips, the intermediate substrate includes (i) only non-active devices, (ii) a first layer, and (iii) a plurality of wires, and the first layer of the intermediate substrate is configured to connect a first plurality of the first conductive bumps of the plurality of semiconductor chips to a first wire of the plurality of wires, wherein the first wire of the plurality of wires is at (i) a voltage potential of a power supply, or (ii) a ground potential; and a package substrate comprising (i) a first surface configured to electrically connect to the intermediate substrate via the plurality of wires, (ii) second conductive bumps, and (iii) a second surface electrically connected to a printed circuit board via the second conductive bumps.