Patent ID: 7394830

Claim:
A synchronization circuit, comprising: a local timestamp counter configured to generate a local timestamp value; a processing circuit to receive externally generated synchronization pulses and to receive a predicted master time stamp value associated with a future one of the externally generated synchronization pulses, wherein the processing circuit receives the predicted master timestamp value asynchronously in Internet Protocol (IP) packets received over an IP connection, the processing circuit to identify the local timestamp value and synchronize the local timestamp value upon receipt of the future one of the externally generated synchronization pulses; and one or more line cards in a same Cable Modem Termination System (CMTS) chassis that each have local timestamp counters that is adjusted according to the received predicted master timestamp value and local timestamp value at the future received synchronization pulse and wherein the processing circuit identifies an error condition according to a number of times the local timestamp counter is synchronized with the received predicted master timestamp value.