Patent ID: 7318144

Claim:
A packet processing system comprising: a processor; a co-processor separated from said processor by a boundary; and an interface coupled with said processor and said co-processor and operative to bridge said boundary, said interface including: a memory coupled with said processor and said co-processor, said memory having at least two read/write ports for reading and writing data to said memory, wherein each of said ports is capable of providing random access to said memory, wherein said processor is coupled with one of said at least two ports and said co-processor is coupled with the other of said at least two ports; and control logic coupled with said at least two read/write ports; wherein said processor stores data intended for said co-processor to said memory and reads data stored by said co-processor from said memory independent of said co-processor; said co-processor stores data intended for said processor to said memory and reads data stored by said processor from said memory independent of said processor; and said control logic operative to facilitate the reading of said stored data by said processor and said co-processor.