Patent ID: 7777542

Claim:
A semiconductor memory device, comprising: a clock buffer for generating an internal clock and a reference clock by buffering an external clock; a first delay circuit for delaying a rising edge of the reference clock and generating a first delay locked clock; a second delay circuit for delaying a falling edge of the reference clock and generating a second delay locked clock; delay replica unit for delaying the first and second delay locked clocks for a modeled delay amount in order to output a feedback rising clock and a feedback falling clock; a phase comparison unit for comparing a phase of the reference clock with phases of the feedback rising and falling clocks and generating a plurality of phase control signals; a mode generation unit for receiving the plurality of phase control signals and generating a locked state signal and a fast mode signal; and a control unit for selectively resetting the first and the second delay circuits according to a first and second delay state signals, the locked state signal, and the fast mode signal, wherein the first and the second delay state signals are outputted from the first and second delay circuits, respectively, and activated when a larger delay amount than a maximum delay amount of the first and the second delay circuits is required or a smaller delay amount than a minimum delay amount of the first and the second delay circuits is required.