Patent ID: 7188060

Claim:
A computer-implemented method for emulating a high-precision, high-accuracy clock using a first clock and a second clock, comprising: periodically storing, relative to a checkpoint period lasting for a selected number of cycles of the second clock, a checkpoint time indicating a number of elapsed cycles of the second clock at the end of the period and a checkpoint cycle count indicating a number of elapsed cycles of the first clock at the end of the period, wherein the first clock operates with a greater rate of oscillation and lesser accuracy than the second clock; calculating a first-clock-delta value as a difference between a current count of elapsed cycles of the first clock and a most recently stored checkpoint cycle count of the first clock; converting the first-clock-delta value to units compatible with a most recently stored checkpoint time of the second clock; and; determining a current time as a sum of the most recently stored checkpoint time and the first-clock-delta value; periodically calculating, according to the checkpoint period, a reference cycle rate of the first clock relative to the rate of oscillation of the second clock and using the reference cycle rate in converting the first-clock-delta value to units compatible with the most recently stored checkpoint time of the second clock; finding a current rate of oscillation of the first clock relative to the rate of oscillation of the second clock; and in response to an absolute value of a difference between the current rate of oscillation of the first clock and the reference cycle rate being less than a selected first threshold, changing the reference cycle rate by one-eighth the difference between the current rate of oscillation of the first clock and the reference cycle rate.