Patent ID: 7634039

Claim:
A delay-locked loop, comprising: a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output; a charge pump system operatively coupled with the phase detector and including: a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output; a delay regulator coupled to the delay line and adapted to supply a current-dependent regulated supply voltage to power semiconductor devices of the delay line; and a current compensation circuit coupled to the delay regulator and configured to operate in one of an activated state, in which the current compensation circuit draws current from the delay regulator, and a deactivated state, in which the current compensation circuit draws substantially no current from the delay regulator.