Patent ID: 7371602

Claim:
A method of manufacturing a semiconductor package structure, said method comprising: providing a wafer that defines an active surface and a back surface opposite to the active surface and has a plurality of chips and a plurality of scribe lines formed between adjacent ones of the chips, wherein each said chip has a plurality of bonding pads and an optical component disposed on the active surface, with the optical component being electrically connected to the chip; forming a plurality of holes on the active surface of the wafer, wherein each of the holes extends across one of the scribe lines between an adjacent pair of the chips; forming a conductive material within the holes to form a plurality of via holes electrically connected to the pad extension traces, respectively; attaching a lid to the active surface of the wafer; forming a plurality of metal traces on the back surface of the wafer, wherein the metal traces are electrically connected to the via holes and define a plurality of solder pads thereon, respectively; and cutting the wafer along the scribe lines to form individual semiconductor package structures, wherein each of the via holes is cut into two halves as a result of said cutting.