Patent ID: 8143812

Claim:
An apparatus comprising: a plurality of terminals; a clamp circuit including: a voltage divider; a voltage regulator; an inverter having a power terminal, an input terminal, and an output terminal, wherein the power input terminal is coupled to the voltage regulator, and receives an actuation signal at its input terminal; a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the voltage regulator, and wherein the control electrode of the first transistor is coupled to the output terminal of the inverter, and the second passive electrode of the first transistor is coupled to a bias node; and a plurality of cascode circuits, wherein each terminal is coupled to at least one cascode circuit, and wherein each cascode circuit is coupled to the bias node; a back-to-back switch is coupled between the voltage divider and the bias node; a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the second transistor is coupled to at least one of the cascode circuits, and wherein the control electrode of the second transistor receives a first enable signal; a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the third transistor is coupled to at least one of the cascode circuits, and wherein the control electrode of the third transistor receives a second enable signal; and a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fourth transistor is coupled to the second passive electrodes of the second and third transistors, and wherein the control electrode of the fourth transistor receives a bias voltage.