Patent ID: 7439127

Claim:
A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of: etching an opening through the layer of insulator to expose a portion of the first semiconductor layer; depositing a first layer of metal overlying the second semiconductor layer and into the opening and contacting the exposed portion of the first semiconductor layer; depositing a dielectric layer comprising Ba 1-x Ca x Ti 1-y Zr y O 3 overlying the first layer of metal; depositing a second layer of metal overlying the dielectric layer; annealing the dielectric layer at a temperature in excess of 450° C.; removing a portion of the first layer of metal, the dielectric layer, and the second layer of metal overlying the second semiconductor layer to expose a surface of the second semiconductor layer; forming a layer of gate insulator at the surface of the second semiconductor layer; and depositing and patterning a layer of gate electrode material to form a gate electrode overlying the layer of gate insulator.