Patent ID: 8338877

Claim:
A nonvolatile memory device, comprising: a semiconductor substrate having a plurality of first regions and a plurality of second regions extending in a first direction, wherein the plurality of first regions and the plurality of second regions are alternately disposed in the semiconductor substrate along a second direction crossing the first direction; a plurality of buried doped lines each in one of the first regions and extending in the first direction, wherein the buried doped lines are doped with a dopant of a first conductivity type; a plurality of bulk regions doped with a dopant of a second conductivity type and a plurality of device isolation patterns disposed along the second direction, wherein the plurality of bulk regions and the plurality of device isolation patterns are in the plurality of second regions; a plurality of word lines crossing the plurality of buried doped lines and the plurality of bulk regions, wherein the plurality of word lines are parallel to one another; and a plurality of contact structures connected to the plurality of buried doped lines, wherein the plurality of contact structures are disposed between the plurality of device isolation patterns, wherein the plurality of word lines directly adjacent to the plurality of contact structures include gate electrodes, and side walls of the device isolation patterns disposed in the first direction overlap with the gate electrodes, and wherein a bottom surface of the plurality of device isolation patterns is lower than a top surface of the semiconductor substrate.