Patent ID: 8498154

Claim:
A system, comprising: a plurality of memory cells, wherein each of the plurality of memory cells is configured to store a plurality of bits and has one of a plurality of states represented by values of the plurality of bits, wherein the plurality of bits includes a least significant bit and a most significant bit, wherein the least significant bits of the plurality of memory cells are arranged along a first page, and wherein the most significant bits of the plurality of memory cells are arranged along a second page; a state set module configured to generate a first state set and a second state set, wherein the first state set includes the plurality of states arranged in a first sequence, wherein the second state set includes the plurality of states arranged in a second sequence, wherein the least significant bits in the first state set include a first number of transitions when the plurality of states in the first state set is accessed in the first sequence, wherein the most significant bits in the first state set include a second number of transitions when the plurality of states in the first state set is accessed in the first sequence, wherein the least significant bits in the second state set include the second number of transitions when the plurality of states in the second state set is accessed in the second sequence, and wherein the most significant bits in the second state set include the first number of transitions when the plurality of states in the second state set is accessed in the second sequence; and a write module configured to receive a plurality of sets of bits for writing to the plurality of memory cells, wherein each set of the plurality of sets of bits includes a least significant bit for writing to the first page and a most significant bit for writing to the second page, select a first state from the first state set corresponding to a first set of the plurality of sets of bits, select a second state from the second state set corresponding to a second set of the plurality of sets of bits, write the first state to a first memory cell of the plurality of memory cells, and write the second state to a second memory cell of the plurality of memory cells.