Patent ID: 7507628

Claim:
A method of manufacturing a non-volatile memory device, the method comprising: forming a first hard mask layer on a semiconductor substrate; etching a region of the first hard mask layer and the semiconductor substrate using a photoresist layer pattern as an etching mask to form a trench; removing the first hard mask layer; forming a first insulating layer on the semiconductor substrate including the trench; forming a first conductive layer on the semiconductor substrate including the first insulating layer to fill the trench with the conductive layer; forming a second hard mask layer on the first conductive layer; etching a region of the second hard mask layer and the first conductive layer using a photoresist layer pattern as an etching mask to form a conductive layer for a floating gate and a gap-fill conductive layer in the trench, the gap-fill conductive layer having a height that is lower than that of the semiconductor substrate; removing the second hard mask layer except a lower nitride layer; forming a second insulating layer on the conductive layer for the floating gate including the gap-fill conductive layer and the residual nitride layer; forming a third insulating layer on the semiconductor substrate including the second insulating layer; polishing the third insulating layer until a lower nitride layer of the second hard mask layer is exposed; etching a portion of the third insulating layer and the second insulating layer to form an isolation structure through which a portion of a wall of the conductive layer for the floating gate is exposed; and forming a dielectric layer and a second conductive layer on the conductive layer for the floating gate.