Patent ID: 8021945

Claim:
A method of fabricating a semiconductor chip including a trench capacitor, comprising: a) etching a monocrystalline semiconductor region in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material of the semiconductor region, the trench having an initial lateral dimension in a first direction transverse to the vertical direction; b) etching the semiconductor material exposed at the surface of the trench in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface; c) elevating a temperature of the substrate to drive a dopant from a dopant-containing liner lining the surface of the trench into the semiconductor region adjacent to the surface and to oxidize at least a portion of the semiconductor material exposed at the wall; d) removing the dopant-containing liner and at least some of the oxidized portion of the semiconductor material to expose a wall of an enlarged trench within the semiconductor region, the enlarged trench having an enlarged lateral dimension relative to the initial lateral dimension, having roughness in accordance with the multiplicity of crystal facets and having smoothed edges corresponding to boundaries between the crystal facets; and e) forming a node dielectric layer adjacent to the surface of the enlarged trench and a layer of conductive material adjacent to the node dielectric layer so as to form a trench capacitor along the wall of the enlarged trench.