Patent ID: 8541771

Claim:
A semiconductor device comprising: a pre-seeding layer comprising a first material and a second material distinct from the first material, the first material having properties that facilitate pre-seeding and the second material having properties that facilitate masking; a nucleation layer on the pre-seeding layer; a plurality of nitride semiconductor layers on the nucleation layer, at least one masking layer between the plurality of nitride semiconductor layers; and at least one inter layer between the plurality of nitride semiconductor layers, the at least one inter layer being on the at least one masking layer, the at least one inter layer configured to compensate for a tensile stress, wherein the at least one inter layer comprises a material selected from the group consisting of Al x0 In y0 Ga 1-x0-y0 N (0≦x0, y0≦1, x0+y0≦1), step graded Al x In y Ga 1-x-y N (0≦x, y≦1, x+y≦1), and Al x1 In y1 Ga 1-x1-y1 N/Al x2 In y2 Ga 1-x2-y2 N (0≦x1, x2, y1, y2≦1, x1≠x2 or y1≠y2) superlattice.