Patent ID: 6865721

Claim:
A method of optimizing determination of pins for a plurality of blocks of a physical design, comprising: a) determining a plurality of ports that need to couple to other ports in other blocks, wherein each block includes one or more cells, and wherein each port represents one of a location where a signal enters said cells and a location where a signal exits said cells; b) at a top-level, placing each one of said plurality of ports in a general random location within each corresponding block since actual locations of said ports within each corresponding block requires a block-level placement; c) at said top-level, routing said ports using a routing wire; d) at said top-level, generating each pin for each block at a position where said routing wire crosses a shared boundary between two blocks, wherein each pin represents one of a location where a signal enters said blocks and a location where a signal exits said blocks; and e) removing one or more excess pins from said plurality of blocks based on criteria.