Patent ID: 6958679

Claim:
A binary hysteresis comparator circuit, comprising: first and second multi-bit circuit input terminals; a circuit output terminal; an A-equals-B comparator having a multi-bit A input terminal coupled to the first circuit input terminal, a multi-bit B input terminal coupled to the second circuit input terminal, and an output terminal; an A-greater-than-B comparator having a multi-bit A input terminal coupled to the first circuit input terminal, a multi-bit B input terminal, and an output terminal; an A-less-than-B comparator having a multi-bit A input terminal coupled to the first circuit input terminal, a multi-bit B input terminal, and an output terminal; a logic gate having a first input terminal coupled to the output terminal of the A-greater-than-B comparator, a second input terminal coupled to the output terminal of the A-less-than-B comparator, and an output terminal; a first multiplexer circuit having a first data input terminal coupled to the output terminal of the A-equals-B comparator, a second data input terminal coupled to the output terminal of the logic gate, a select terminal, and an output terminal; a memory element having a data input terminal coupled to the output terminal of the first multiplexer circuit, and further having a data output terminal coupled to the circuit output terminal and to the select terminal of the first multiplexer circuit; and a first hysteresis circuit coupled between the second circuit input terminal and the B input terminal of one of the A-greater-than-B comparator and the A-less-than-B comparator.