Patent ID: 8759901

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor layer with a main surface, a laminated structure portion having a plurality of control gate electrodes and a plurality of first insulating films alternately laminated on the main surface of the semiconductor layer, wherein a groove that exposes the main surface of the semiconductor layer at a bottom of the groove is formed to penetrate a portion of the laminated structure portion, a second insulating layer formed to line an inner wall of the groove, a charge storage layer formed on the second insulating layer, a third insulating layer formed on the charge storage layer and to leave a space in the groove, and a semiconductor region formed on the third insulating layer to fill the space in the groove and to reach the bottom of the groove, wherein at least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and the second insulating layer. wherein the second insulating layer has a laminated structure of an insulating film and the inelastic scattering film, and the inelastic scattering film is one of a hafnium oxide film containing hafnium and oxygen and a silicon film containing at least one of nitrogen and oxygen.