Patent ID: 7242096

Claim:
A semiconductor device having a wiring structure formed by a dual damascene method, the wiring structure comprising: a lower buried-wiring layer; an interlayer insulating film provided on the lower buried-wiring layer; an inter-wiring insulating film provided on the interlayer insulating film; and an upper buried-wiring layer buried in wiring grooves provided in the inter-wiring insulating film, the upper buried-wiring layer being electrically connected to the lower buried- wiring layer through contact plugs passing through the interlayer insulating film; wherein the interlayer insulating film is a first carbon-containing silicon oxide film (SiOC film); and the inter-wiring insulating film comprises a laminated insulating film including an organic low dielectric constant insulating film, and a multi-layer second carbon-containing silicon oxide film provided on the low dielectric constant insulating film and having a plurality of layers with different carbon contents, the carbon content of the top layer of the second carbon-containing silicon oxide film being lower than that of the first carbon-containing silicon oxide film.