Patent ID: 8270194

Claim:
A plurality of memory circuits, each of which is connected to a respective one of a plurality of integrated circuits (“ICs”), each of the ICs being connected to at least one of the other ICs by inter-IC connections so that an IC exchanges memory circuit data with another IC via the inter-IC connections, each of the ICs including memory manager circuitry comprising: a logic block manager for maintaining a unique global identification (“ID”) for each block of data contained in any portion of any of the memory circuits, the global ID including a node ID identifying the IC that is connected to the memory circuit containing that block and a logical block number for that block; a translator for maintaining a mapping between (1) the logical block number of each block contained in the memory circuit connected to the IC that includes that translator, and (2) a physical portion ID of a portion of that memory circuit that contains that block; and a driver for receiving the physical portion ID from the translator of the IC that includes that driver and accessing the portion of the memory connected to that IC that is identified by that physical portion ID.