Patent ID: 8472265

Claim:
A repairing method for a memory circuit, wherein the memory circuit comprises a plurality of columns with memory cells and at least one repairing circuit, the columns with memory cells comprise a plurality of normal CSLs with normal memory cells, and a first and second spare column selected lines (SCSLs) with redundant memory cells, wherein the first and second SCSLs are expanded from a redundant column selected line (RCSL), each of the SCSL is divided into several partial SCSLs (P-SCSLs) in different row addresses, the repairing method comprising: forming a first region having X rows of the memory cells, and a second region having Y rows of the memory cells, wherein X and Y are positive integer larger than 0, and the RCSL is divided into a first and second partial redundant column selected lines (P-RCSLs) respectively corresponding to the first and second region and having several P-SCSLs in the different row addresses; determining whether Z faulty memory cells are located in the first or second regions is determined, wherein Z is a positive integer larger than 0; if the Z faulty memory cells are located in the first region, the repairing circuit replaces the normal memory cells on the normal CSLs corresponding to a required column address by the redundant memory cells on the first P-RCSL, wherein the required column address is a column address which has the Z faulty memory cells; and if the Z faulty memory cells are located in the second region, the repairing circuit replaces the normal memory cells on the normal CSLs corresponding to the required column address by the redundant memory cells on the second P-RCSL.