Patent ID: 7902066

Claim:
A method of fabricating an integrated circuit comprising: providing a semiconductor substrate prepared with a transistor; forming an interconnecting dielectric layer (ICD) including first and second dielectric layers on the substrate, wherein the first dielectric layer is an interlevel dielectric (ILD) and the second dielectric layer comprises an intermetal dielectric (IMD); forming a hard mask over the second dielectric layer; patterning the hard mask to form a contact opening; etching the ICD layer using the hard mask as an etch mask to form a via of a dual damascene contact opening, wherein the first dielectric layer is partially etched to leave a dielectric plug in the via to cover a contact region of the transistor; forming a sacrificial layer over the substrate which fills the via and covers a surface of the hard mask; repatterning the hard mask to form a trench opening; patterning the ICD layer to form a trench of the dual damascene contact opening and to expose the contact region of the transistor; and forming a metal interconnect in the dual damascene structure.