Patent ID: 8627156

Claim:
A method for testing a device under test (DUT), the method comprising: receiving a signal transmitted by the DUT, wherein the signal includes first portions that include scrambled bits produced from a selected bit pattern and a selected scrambling algorithm, and further includes second portions that include unscrambled bits, the first portions and second portions being interspersed within the signal; detecting received scrambled bits within the received signal; generating a test bit sequence using the selected scrambling algorithm and the selected bit pattern, including generating a bit for the test bit sequence for each of the received scrambled bits within the received signal, and not generating a bit for the test bit sequence for each of the received unscrambled bits within the received signal; comparing the received scrambled bits to the test bit sequence to determine a bit error rate of the received signal; and operating a test linear feedback shift register (LFSR) according to the selected scrambling algorithm and the selected bit pattern to generate the test bit sequence, wherein the unscrambled bits include bits indicating that the test LFSR should be resynchronized to the received scrambled bits, and the method further comprises detecting the unscrambled bits indicating that the test LFSR should be resynchronized to the received scrambled bits and in response thereto, resynchronizing the test LFSR to the received scrambled bits.