Patent ID: 8664067

Claim:
A method of fabricating an MOS transistor, the method comprising: providing a substrate with a body region that is doped with first dopants of a first conductivity type; and implanting second dopants of the first conductivity type into the body region, the second dopants being implanted through a source region, a gate, and a drain region of the transistor to form a doping profile that selectively increases dopant concentration in the body region, the doping profile having a shallow portion that increases dopant concentration of the body region under the gate and having a deep portion that increases the dopant concentration of the body region under the source region and the drain region, the shallow portion being closer to a surface of the body region relative to the deep portion, wherein the doping profile and the source and drain regions are formed in-situ using a same lithography mask that locates the doping profile in the body region and locates the source and drain regions.