Patent ID: 7235444

Claim:
A method for fabricating the non-volatile memory structure, comprising: providing a substrate with a first dielectric layer, a first conductive layer, and a second dielectric layer sequentially formed thereon; removing a part of the second dielectric layer to form a first opening with both ends having a select gate region respectively, wherein the two select gate regions are spaced apart from each other by a distance, and are respectively constituted by a region with the second dielectric layer and a region without the second dielectric layer; forming a second conductive layer on the substrate to cover the second dielectric layer, wherein the second conductive layer has a tapered corner in each of the select gate regions; forming a cap layer on the second conductive layer; patterning the cap layer, the second conductive layer, the second dielectric layer, and the first conductive layer at one side of the adjacent select gate regions to form a plurality of gate structures; sequentially removing the cap layer, the second conductive layer, and the first conductive layer between the two adjacent select gate regions, so as to form a select gate structure in each of the select gate regions; and forming a doped region in the substrate between the gate structures, between the select gate structures, and between the gate structures and the select gate structures, respectively.