Patent ID: 7676588

Claim:
A system for converting network communications data between multiple communications protocols, the system comprising: a high speed interconnect; a plurality of programmable processors, each processor having multiple hardwired thread units, each said hardwired thread unit being capable of fully executing programs, wherein the hardwired thread units are operable for performing communications protocol conversion of data frames; and means for implementing a multi-token counter protocol for pipelining communications between a source processor element and a destination processor element through said high-speed interconnect, a source processor element being a processor and a destination processor element being a processor or a processor memory, a round trip latency between a request sent by a source to a destination and receipt by the source of an acknowledgment from the destination over the high speed interconnect is two or more of a clock cycle of said system for at least one pipelined pair of processor elements, wherein the plurality of programmable processors perform data frame routing to another processor if a work queue of a processor receiving the data frame is above a threshold and if a work queue of the another processor is below a threshold; wherein the round trip latency between the source and the destination, measured in clock cycles, is equal to or less than a set number, and said means for implementing the multi-token counter protocol further comprising: means for allocating to each source, said set number of buffers at the destination; means for providing each source with a token for each buffer location at the destination; and a token counter at each source, a value of said token counter being set to the number of said allocated buffers that is empty.