Patent ID: 7302655

Claim:
A method for verifying a circuit design comprising: providing the circuit design having a first input port and a second port and an output port; assigning a first fractional value with a first denominator (a 1 ) to said first input port of the circuit design, said first denominator being a first integer not equal to either 2 or 1; assigning a second fractional value with a second denominator (a 2 ) to said second input port of the circuit design, said second denominator being a second integer calculated according to a 2 =(a 1 −1) 2 +1; calculating an output value of the circuit design based on said first fractional value and said second fractional value to said output port at a Boolean gate, said calculating being in a step-by-step manner; checking to determine if said output value of the circuit design is equal to a predetermined value; and determining a correctness of the circuit design based the checked determination of whether said output value is equal to the predetermined value.