Patent ID: 8877642

Claim:
A method comprising: fabricating of one or more semiconductor devices with critical gate dimension control, the fabricating comprising: providing a multilayer stack structure over a gate dielectric layer, the multilayer stack structure comprising a gate material disposed above the gate dielectric; etching through the multilayer stack structure, with critical dimension control, to define multiple gate lines extending above the substrate, the etching including etching through the gate material to the gate dielectric layer, exposing a portion of the gate dielectric layer; providing a conformal protective layer wrapping over the multiple gate lines defined with critical dimensional control, and covering the exposed portion of the gate dielectric layer; after providing the conformal protective layer, defining one or more cut openings over the conformal protective layer and one or more gate lines of the multiple gate lines, and cutting, in part, through the conformal protective layer and the one or more gate lines, the cutting defining one or more cuts in the one or more gate lines and facilitating defining multiple gate structures of the one or more semiconductor devices, wherein the conformal protective layer protects the multiple gate lines outside the one or more cut openings; and removing the conformal protective layer from the multiple gate lines and the multiple gate structures of the one or more semiconductor devices.