Patent ID: 6950362

Claim:
A semiconductor memory device, comprising: a memory array including a plurality of memory cells and a plurality of dummy cells; a row decoder connected to the memory array; a dummy control circuit connected to the memory array; a column selector connected to the memory array; an amplifier circuit connected to the column selector; a dummy column selector connected to the memory array; and an amplifier control circuit connected to the dummy column selector and the amplifier circuit, wherein the plurality of dummy cells are arranged as a first dummy column including a first group of the dummy cells placed in a column at a position close to the row decoder in a row direction and a second dummy column including a second group of the dummy cells placed in a column at a position farthest from the row decoder in a row direction, with the plurality of memory cells interposed between the first dummy column and the second dummy column, the dummy control circuit activates the first dummy column and the second dummy column through a first dummy word line and a second dummy word line, respectively the dummy column selector selects either one of a signal on a first dummy bit line connected to the first dummy column and a signal on a second dummy bit line connected to the second dummy column; and the amplifier control circuit generates an amplifier startup signal with respect to the amplifier circuit, based on a signal from the dummy column selector.