Patent ID: 8341489

Claim:
An apparatus, comprising: a first APP (a posteriori probability) daisy chain that is operative to output a first plurality of APP values; a second APP daisy chain that is operative to output a second plurality of APP values; a first plurality of check modules that is operative to employ first selected APP values, that are selected from the first plurality of APP values and the second plurality of APP values, to update a first plurality of check edge messages that corresponds to a first plurality of rows in a first sub-matrix row of a LDPC (Low Density Parity Check) matrix thereby generating a second plurality of check edge messages; a second plurality of check modules that is operative to employ second selected APP values, that are selected from the first plurality of APP values and the second plurality of APP values, to update a third plurality of check edge messages that corresponds to a second plurality of rows in a second sub-matrix row of the LDPC matrix thereby generating a fourth plurality of check edge messages; and wherein: the first plurality of APP values is updated using the second plurality of check edge messages thereby generating a third plurality of APP values; the second plurality of APP values is updated using the fourth plurality of check edge messages thereby generating a fourth plurality of APP values; and the apparatus employs the third plurality of APP values and the fourth plurality of APP values to make an estimate of an information bit encoded within an LDPC coded signal.