Patent ID: 7458058

Claim:
A method for verifying a process margin for a mask pattern, comprising: receiving a mask pattern for patterning one or more features associated with a semiconductor wafer, the mask pattern modified according to a wafer pattern model, the water pattern model operable to estimate a wafer pattern resulting from the mask pattern, the mask pattern comprising one or more portions; and repeating the following for each portion of the one or more portions of the mask pattern: selecting a plurality of intermediate stage models to apply to the portion, an intermediate stage model operable to estimate an intermediate stage of the wafer pattern; and verifying a process margin of the portion by repeating the following for each intermediate stage model of the plurality of intermediate stage models: selecting one or more tests of the intermediate stage model to perform on the portion; and performing the one or more tests on the portion to verify the process margin, wherein selecting the plurality of intermediate stage models further comprises: selecting and applying a first intermediate stage model; establishing a previous result from a previously applied first intermediate stage model; and selecting a second intermediate stage model based on the previous result.