Patent ID: 7473926

Claim:
A method of fabricating an array substrate for a liquid crystal display device, comprising: preparing a substrate defining a display area and a non-display area; forming first and second semiconductor layers in the non-display area and third and fourth semiconductor layers in the display area and a first storage electrode on the fourth semiconductor layer through a first mask process; forming a first gate electrode on a central portion of the first semiconductor layer and first and second metal patterns covering the second and the third semiconductor layers and the first storage electrode through a second mask process; doping end portions of the first semiconductor layer exposed by the first gate electrode with high concentration p-type impurities (p+); forming second and third gate electrodes on central portions of the second and third semiconductor layers, respectively, and a second storage electrode over the first storage electrode through a third mask process; doping end portions of the second semiconductor layer exposed by the second gate electrode with high concentration n-type impurities (n+) and doping end portions of the third semiconductor layer exposed by the third gate electrode with low concentration n-type impurities (n−); forming an interlayer insulating layer on the second and third gate electrodes and a first metal electrode through a fourth mask process, the interlayer insulating layer exposing respective doped portions of the first, second and third semiconductor layers; forming first source and first drain electrodes connected to the doped portions of the first semiconductor layer, second source and second drain electrodes connected to the doped portions of the second semiconductor layer, third source and third drain electrodes connected to the doped portions of the third semiconductor layers and a third storage electrode over the second electrode capacitor through a fifth mask process; forming a passivation layer on the first, second and third source and the first, second and third drain electrodes through a sixth mask process, the passivation layer having a contact hole that exposes a portion of one of the third storage electrode and the third drain electrode; and forming a pixel electrode on the passivation layer through a seventh mask process, the pixel electrode connected to one of the third storage electrode and the third drain electrode via the contact hole.