Patent ID: 7177227

Claim:
An integrated circuit comprising: a memory array disposed above a dielectric layer, said memory array comprising a plurality of memory blocks, said memory array further comprising a plurality of array lines, each respective array line traversing horizontally across a respective memory block; a plurality of array line driver circuits disposed beneath the dielectric layer, each array line driver circuit comprising a first driver transistor of a first conductivity type coupled to drive a respective array line; and a plurality of connection areas disposed between adjacent memory blocks, each connection area comprising a respective conductive path from a respective array line associated with an adjacent memory block to a respective electrode on a lower interconnection level, said respective electrode being coupled to a respective array line driver circuit; wherein half of the array line driver circuits associated with a given connection area are disposed at least partially beneath the memory block to one side of the given connection area, and the other half of the array line driver circuits associated with the given connection area are disposed at least partially beneath the memory block to the other side of the given connection area.