Patent ID: 7260669

Claim:
A semiconductor integrated circuit device comprising: a CPU related to a first memory space; a peripheral LSI related to a second memory space; a CPU bus connected between the CPU and the peripheral LSI and related to the first memory space; and an I/O bus connected to the peripheral LSI and related to the second memory space; wherein the peripheral LSI comprises: an address translation circuit; a nonvolatile memory to store address information indicating a relationship between an address of the first memory space and an address of the second memory space; a CODEC circuit to compress and uncompress video data; a first protocol decode and generation circuit connecting to a first bus connected to the first memory space; and a second protocol decode and generation circuit connecting to a second bus connected to the second memory space; wherein the address translation circuit is connected to the first and second protocol decode and generation circuits and comprises: a register, and an address calculation circuit, wherein, when the semiconductor integrated circuit device is initialized, the register reads the address information from the nonvolatile memory; wherein, when the CPU acts as a bus master to access the second memory space, the first protocol decode and generation circuit receives a first address in the first memory space and sends the first address to the address calculation circuit, the address calculation circuit translates the first address into a second address in the second memory space from the address information stored in the register, and the address calculation circuit sends the second address to the second protocol decode and generation circuit; wherein, when the peripheral LSI acts as a bus master to access the first memory space, the second protocol decode and generation circuit receives a third address in the second memory space and sends the third address to the address calculation circuit, the address calculation circuit translates the third address into a fourth address in the first memory space from the address information stored in the register, and the address calculation circuit sends the fourth address to the first protocol decode and generation circuit; wherein the CODEC circuit in the peripheral LSI receives compressed first video data from the CPU bus, uncompresses the compressed first video data into uncompressed first video data, and transfers the uncompressed first video data to the I/O bus; wherein the CODEC circuit in the peripheral LSI receives second video data from the I/O bus, compresses the second video data into compressed second video data, and transfers the compressed second video data to the CPU bus; and wherein the semiconductor integrated circuit device further comprises: a first memory; a second memory; a flash memory; and an LCD controller; wherein the first memory and the flash memory are connected to the CPU bus; and wherein the second memory and the LCD controller are connected to a camera.