Patent ID: 8015518

Claim:
A non-transitory machine readable storage medium for designing, manufacturing, or testing a design, said non-transitory machine readable storage medium embodying a design structure, said design structure comprising a first data representing a first electrostatic discharge (ESD) protection circuit and a second data representing a second ESD protection circuit, wherein said first electrostatic discharge (ESD) protection circuit and said second ESD protection circuit are connected in a parallel connection between a signal path and ground; wherein said first data includes a third data representing a cascaded plurality of primary bipolar transistors of one transistor type including first through n-th primary bipolar transistors, wherein n is a positive integer equal to or greater than 2, wherein said transistor type is selected from an npn type and a pnp type, wherein a base of said first primary bipolar transistor is connected to ground, wherein an emitter of said n-th primary bipolar transistor is connected to said signal path, and wherein a base of an i-th primary bipolar transistor is connected to an emitter of an (i−1)-th primary bipolar transistor and not connected to any power supply node for each integer i labeling said cascaded plurality of primary bipolar transistors and having a value between and including 2 and n, and wherein all collectors of said cascaded plurality of primary bipolar transistors are electrically tied; and wherein said second data includes a fourth data representing a cascaded plurality of complementary bipolar transistors of said transistor type including first through m-th complementary bipolar transistors, wherein m is a positive integer equal to or greater than 2, wherein a base of said first complementary bipolar transistor is connected to said signal path, wherein an emitter of said m-th complementary bipolar transistor is connected to said ground, and wherein a base of a k-th complementary bipolar transistor is connected to an emitter of a (k−1)-th complementary bipolar transistor and not connected to any power supply node for each integer k labeling said cascaded plurality of complementary bipolar transistors and having a value between and including 2 and m, and wherein all collectors of said cascaded plurality of complementary bipolar transistors are electrically tied.