Patent ID: 8686752

Claim:
A circuit, comprising: a logic stage that includes a current limiter comprising a D-mode feedback transistor having a source, a drain, a gate and a gate-source junction, the current limiter further comprising a component that generates a voltage drop and a feedback loop connecting the source of the D-mode feedback transistor to the gate of the D-mode feedback transistor via the component that generates the voltage drop; an inverter stage coupled to the logic stage and including a further current limiter comprising a further D-mode feedback transistor having a source, a drain, a gate and a gate-source junction, the further current limiter further comprising a further component that generates a voltage drop, and a further feedback loop connecting the source of the further D-mode feedback transistor to the gate of the further D-mode feedback transistor via the further component that generates the voltage drop; and a driver stage coupled to the inverter stage and comprising E-mode transistors having a source, a drain and a gate, the E-mode transistors being connected in a totem pole.