Patent ID: 8268076

Claim:
A process for manufacturing a semiconductor wafer, the process comprising the following steps in the order given: a) providing a monocrystalline substrate wafer ( 1 ), b) epitaxially depositing a monocrystalline first oxide layer ( 3 ) on at least one surface of the substrate wafer ( 1 ) to form a layered wafer, the first oxide layer ( 3 ) having a cubic Ia-3 crystal structure, a composition of (M 1 2 O 3 ) 1-x (M 2 2 O 3 ) x wherein each of M 1 and M 2 is a metal and wherein 0≦x ≦1, and a lattice constant which differs from the lattice constant of the material of the substrate wafer by 0% to 5%, c) epitaxially depositing a monocrystalline second oxide layer ( 4 ) on the surface of the first oxide layer ( 3 ) having a cubic Ia-3 crystal structure, the second oxide layer ( 4 ) having a cubic Ia-3 crystal structure, a composition of (M 3 2 O 3 ) 1-y (M 4 2 O 3 ) y wherein each of M 3 and M 4 is a metal and wherein 0≦y≦1, y starting with a value y 1 at the boundary to the first oxide layer ( 3 ) having a cubic Ia-3 crystal structure, and varying y across the thickness of the second oxide layer ( 4 ) in order to achieve a variation in the lattice constant of the material of the second oxide layer ( 4 ) across its thickness, and ending with a value y 2 at the surface of the second oxide layer ( 4 ), the value y 1 being selected such that the lattice constant of the second oxide layer ( 4 ) at its boundary to the first oxide layer ( 3 ) having a cubic Ia-3 crystal structure differs from the lattice constant of the material of the first oxide layer ( 3 ) having a cubic Ia-3 crystal structure by 0% to 2% and e) thermally treating the resulting layered wafer under an atmosphere comprising oxygen with a partial pressure of 10 −6 mbar to 1 bar at a temperature of 200 to 1000° C. for 10 to 100 minutes, thereby forming a first amorphous intermediate layer ( 2 ) at the boundary between the substrate wafer ( 1 ) and the first oxide layer ( 3 ) having a cubic Ia-3 crystal structure.