Patent ID: 8716091

Claim:
A method for fabricating an upside-down p-FET on a donor substrate as part of an integrated circuit device, said method comprising: providing the donor substrate comprising a silicon substrate, a buried oxide, and a single-crystal silicon-on-insulator layer; forming a gate over a channel region in the donor substrate, said gate comprising a thin gate dielectric layer over the silicon-on-insulator layer and a gate conductor line over said thin gate dielectric layer; providing spacers adjoining the gate conductor line; fully etching a plurality of source and drain regions in the donor substrate by: etching the silicon-on-insulator layer through the buried oxide and partially etching the silicon substrate; and forming a trench with crystal plane sidewalls; forming self-terminating e-SiGe source and drain regions by refilling the trench with epitaxial SiGe, wherein said e-SiGe source and drain regions are self-terminating to prevent excess film growth, such that a surface of said e-SiGe source and drain regions is left non-reactive at exposure; capping the e-SiGe source and drain regions with self-aligning silicide/germanide; providing a first stress liner deposited over the gate and the e-SiGe source and drain regions; depositing a planarized dielectric over the first stress liner; inverting the donor substrate; bonding the donor substrate to a host wafer; and selectively exposing the buried oxide and the e-SiGe source and drain regions by removing the donor substrate.