Patent ID: 6982923

Claim:
A semiconductor memory device comprising: a plurality of memory cell arrays, each of which include a plurality of memory cells in a matrix; a mode control unit which outputs a delay control signal; an instruction execution unit which accesses to said plurality of memory cells based on an address and an address buffer control signal supplied externally, said instruction execution unit accesses to said memory cell array based on said address, said address buffer control signal and said command signal; and a command control unit which outputs said address buffer control signal to said instruction execution unit based on a command supplied externally and said delay control signal, said command control unit comprises a command decoder circuit which comprises: a control unit which inputs said command supplied externally, and outputs said command signal in synchronization with a first clock signal and outputs said address buffer control signal in synchronization with a second clock signal; a delay circuit which outputs said address buffer control signal delayed; and a multiplexer circuit which selects and outputs one of said address buffer control signal and said address buffer signal delayed by said delay circuit based on said delay control circuit and said command signal to said order execution unit, wherein said command control unit outputs said address buffer signal in synchronization with a clock signal when said delay control signal is in an inactive state and said command is a write command or a read command in an ordinary operation mode, and when said delay control signal is in an active state and said command is said write command in a write instruction delay operation mode, wherein said command control unit outputs said address buffer signal delayed compared with said clock signal when said delay control signal is in the active state and said command is said read command in a read instruction delay operation mode, and wherein said command control unit outputs a command signal of the active state in synchronization with said clock signal to said instruction execution unit when said command is said write command and outputs a command signal of the inactive state in synchronization with said clock signal to said instruction execution unit when said command is said read command.