Patent ID: 7471727

Claim:
An integrated serial data decoder without a capacitor, comprising: a clock generator generating a clock signal; a channel decoder, receiving a demodulated serial data and converting the demodulated serial data into parallel data periodically and repeatedly, wherein a structure of the demodulated serial data includes a data-transmission section and a frame-ending section, periods of the respective demodulated serial data in data-transmission section are equal to each other and all less than a predetermined period of time N, while the time of the frame-ending section is longer than the predetermined period of time N; a frame detector receiving the clock signal and detecting the period of the respective demodulated serial data, when no demodulated serial data is detected and the period of the respective demodulated serial data is found to be equal to the predetermined period of time N, generating a reset signal and starting another round of serial data transmission; the channel decoder receiving the demodulated serial data and comprising a plurality of shift registers, a plurality of inverters and a plurality of AND gates, wherein after the demodulated serial data is inputted to the plurality of shift registers, the outputs of two consecutive shift registers are taken out, and then, after passing through an first inverter and an first AND gate, a set of parallel data is generated, outputs of the last two shift registers are passed through an second inverter and an second AND gate to take out a time period of B 4 R of the frame-ending section before the reset signal R, and then the channel decoder is reset by the reset signal, wherein the time of a high logical level of the last AND gate is equal to the time period B 4 R.