Patent ID: 7816951

Claim:
An analog sampling network ( 100 ) including a sampling capacitor (C S ) for sampling an analog input voltage (V IN ), the sampling capacitor being coupled between a bottom plate sampling switch (M B ) and a top plate sampling switch (M T ) implemented as respective first and second NMOS transistors, the bottom plate sampling switch having source and drain terminals coupled respectively to the analog input voltage and one plate of the sampling capacitor, the top plate sampling switch having source and drain terminals coupled respectively to the other plate of the sampling capacitor and a first reference voltage (V REFI ), the analog sampling network comprising: a top plate boosting circuit ( 150 ) providing a boosted gate voltage (V TOP ) to a gate terminal of the top plate sampling switch during a sampling phase of the analog sampling network, the boosted gate voltage being the sum of a first voltage and a second voltage (V MAX ), wherein the first voltage has a value approximately equal to the first reference voltage and the first voltage tracks fabrication process, temperature, power supply voltage and biasing condition variations, and the second voltage is a maximum operating voltage from the gate to drain or gate to source terminal for a fabrication process used to fabricate the second MOS transistor.