Patent ID: 7791971

Claim:
A semiconductor memory device comprising: a first cell array including cells ( 0 , 0 ) to (N,M) arranged in a matrix pattern of (N+1) rows and (M+1) columns, the first cell array having: a second cell array including cells ( 0 , 0 ) to (N,H) arranged in a matrix pattern of (N+1) rows and (H+1) columns; a third cell array including cells ( 0 ,K) to (N,M) arranged in a matrix pattern of (N+1) rows and (M-K+1) columns; (M+1) pairs of bit lines, each of which is provided to connect (N+1) cells arrayed in a column direction in the first cell array; (N+1) word lines, each of which is provided to connect (M+1) cells arrayed in a row direction in the first cell array; (N+1) row decoders, each of which is connected to an end of a corresponding one of the word lines; and a first replica circuit adjusting sense timing of the second cell array, the first replica circuit being provided between the row decoders and the second cell array and having: a first dummy array including dummy cells (D, 0 ) to (D,H) arrayed in the row direction and dummy cells ( 0 , 0 ) to (N, 0 ) arrayed in the column direction; a dummy word line to which the dummy cells (D, 0 ) to (D,H) are connected; a dummy row decoder connected to an end of the dummy word line; a first dummy local bit line and first dummy global bit line to which the dummy cells ( 0 , 0 ) to (N, 0 ) are connected; a second replica circuit adjusting sense timing of the third cell array, the second replica circuit being provided between the second cell array and the third cell array and having: a second dummy array including dummy cells (D,J) to (D,M) arrayed in the row direction and dummy cells ( 0 ,J) to (N,J) arrayed in the column direction; and a second dummy local bit line and second dummy global bit line to which the dummy cells ( 0 ,J) to (N,J) are connected, wherein the dummy word line is connected to the dummy cells (D,J) to (D,M).