Patent ID: 7772613

Claim:
A semiconductor device comprising: a low-resistance semiconductor substrate of a first conductivity type to be a drain layer; a first main electrode connected to a back surface of the low-resistance semiconductor substrate; a first epitaxial layer of the first conductivity type formed on the low-resistance semiconductor substrate and having a high resistance; a second epitaxial layer of the first conductivity type formed on the first epitaxial layer and having a lower resistance than the first epitaxial layer; a plurality of first trenches formed in the second epitaxial layer; a low-resistance source region of the first conductivity type formed in a region sandwiched between the first trenches on a surface of the second epitaxial layer; a second main electrode formed on the low-resistance source region and electrically connected to the low-resistance source region; a low-resistance gate region of a second conductivity type formed on a sidewall and a bottom portion of the first trench; a third main electrode formed on the low-resistance gate region and electrically connected to the low-resistance gate region; and a high-resistance termination region of the second conductivity type formed to surround an active region including the first trench, the low-resistance source region, and the low-resistance gate region, wherein a channel region sandwiched between the low-resistance gate regions and formed of the second epitaxial layer has a channel width being constant in a first region that is relatively close to the low-resistance source region, and the channel width being wider toward the first epitaxial layer side in a second region that is relatively close to the first epitaxial layer, and a boundary between the first epitaxial layer and the second epitaxial layer is positioned within the second region and closer to a surface side of the high-resistance termination region than a pn junction position of a bottom portion of the high-resistance termination region.