Patent ID: 7646635

Claim:
A data reading circuit of a magnetic memory, applicable for reading data of a magnetic memory, wherein the magnetic memory is disposed at a junction between a first wire and a second wire, and has a magnetic tunnel junction (MTJ) element, the MTJ element at least includes a synthetic anti-ferromagnetic free layer, a tunnel barrier layer, and a synthetic anti-ferromagnetic pinned layer, and memorized data is represented through a different resistance achieved depending upon the fact that magnetic moment configurations of the two ferromagnetic layers for sandwiching the tunnel barrier layer are in anti-parallel or parallel arrangement, and an initial configuration is shown at an initial time, the data reading circuit comprising: a first transistor; a second transistor, connected to the first transistor in series; a third transistor; a fourth transistor, connected to the third transistor in series; a first transmission gate, electrically connected to the first transistor; a second transmission gate, electrically connected to the first and the third transistors; a comparison circuit, having two input ends electrically connected to the first transistor respectively; and a storage capacitor, having one end electrically connected to the first transistor and the other end connected to a power node; wherein the second transmission gate is turned on in response to a second start signal, then the first transmission gate is turned on in response to a first start signal to balance a voltage level, and then the first transmission gate is turned off, and finally the comparison circuit compares voltages at the two input ends, so as to output logic 0 or logic 1.