Patent ID: 7888971

Claim:
A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain including a plurality of logic gates driven by a transmitter clock and a plurality of outputs for transmitting data, the receiver clock domain including a plurality of logic gates driven by a receiver clock, a plurality of inputs coupled to the outputs of the transmitter domain for receiving transmitted data, and a combinational logic coupled to at least one of the logic gates of the receiver domain, the system comprising: a detector for receiving data to be transmitted from the transmitter clock domain, and for detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock; and an identification unit for identifying whether or not any fluctuation of the data determined by the detector is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of the logic gates of the receiver clock domain to the combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic.