Patent ID: 6851086

Claim:
A high-speed pipelined forward error correcting (FEC) encoder, for encoding k bit blocks of data into n bit blocks, each of said n bit blocks comprising one of said k bit blocks of data and (n−k) parity bits, said encoder comprising Q latches, wherein Q≧3; Q−1 combinational logic circuits, each of said combinational logic circuits interconnected between two of said latches, to receive an input of at least k bits from an upstream one of said latches, and provide an output of n bits to a downstream one of said latches, each output comprising (n−k) output bits representing said (n−k) parity bits in various stages of computation, each of said combinational logic circuits arranged to compute said (n−k) output bits in accordance with a defined generator polynomial, with said defined generator polynomial being identical for each of said combinational logic circuits.