Patent ID: 8909831

Claim:
A system coupled to memory packages and a memory controller, comprising: a first logic device connected to the memory controller via first lines extending from the first logic device to the memory controller, wherein the first logic device includes a first buffer and configured to: communicate with a first set of the memory packages with a first protocol over a first interface; communicate with the memory controller with a second protocol; perform a first protocol conversion between the first and the second protocol to transmit commands, addresses and data between the memory controller and the first set of memory packages; storing commands and data in the first buffer from the memory controller while the first interface is busy transferring data from a previous read or write command; and in response to the first interface becoming available, fetching commands and data from the first buffer to process; and a second logic device connected to the memory controller via second lines extending from the first logic device to the memory controller, wherein the second logic device includes a second buffer, and configured to: communicate with a second set of the memory packages with the first protocol over a second interface; communicate with the memory controller with the second protocol; perform a second protocol conversion between the first and the second protocol to transmit commands, addresses and data between the memory controller and the second set of memory packages; storing commands and data received from the memory controller before passing to the second set of memory packages over the second interface; and storing commands and data received from one of the second set of memory packages before passing to the memory controller, wherein the first and second lines further comprise additional lines for power-down control, JTAG control, and distributing a reference clock signal.