Patent ID: 7844873

Claim:
A fault location estimation system that is implemented by a data processing device and that estimates fault location in a logic circuit, said system comprising: means that classifies locations with a high fault possibility into groups based on error-observation node information acquired from a test result of the logic circuit and that performs fault simulation for confirming and estimating a plurality of fault locations; output means that outputs single-fault estimation results and multiple-fault estimation results, that is, a number of fault candidate groups corresponding to a number of multiple actual faults, fault candidate groups corresponding to each of actual faults, fault candidates included in a fault candidate group, and a fault type of each fault candidate; single-fault-assumed diagnostic means that narrows fault locations in the logic circuit assuming a single fault by referencing logic circuit configuration information and signal line expected values stored in a logic circuit information storage unit and that stores fault candidates in the logic circuit, types of the faults, and detected error-observation nodes at which an error arrives from the fault candidates, which are a result of narrowing the fault locations, into a single-fault diagnosis result storage unit; error-observation node basis classification means that classifies error propagating fault candidates into groups according to the error-observation nodes using the fault candidates and the error-observation nodes stored in said single-fault diagnosis result storage unit and stores the groups in a fault candidate classification storage unit as fault candidate groups; inclusion fault candidate group selection means that acquires a relation between each fault candidate group and a fault output by referencing the logic circuit configuration information and the fault candidate groups stored in said fault candidate classification storage unit, calculates an inclusion relation among the fault candidate groups, and extracts common candidates; and inter-pattern overlapping means that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the fault candidates in said single-fault diagnosis result storage unit and the fault candidate groups in said fault candidate classification storage unit, stores the calculated combinations in a combination storage unit and, if there are common fault candidates in the calculated fault candidate groups, extracts the common fault candidates and re-registers the common fault candidates in said fault candidate classification storage unit as a new fault candidate group.