Patent ID: 7863135

Claim:
A method of manufacturing a semiconductor device having a non-volatile memory cell in a first region of a semiconductor substrate and a first MISFET in a second region of the semiconductor substrate, comprising steps of: (a) forming a first conductive film over the semiconductor substrate of the first and second regions; (b) after the step (a), by patterning the first conductive film, forming a control gate electrode of the non-volatile memory cell in the first region and forming a gate electrode of the first MISFET in the second region at the same time; (c) after the step (b), forming a charge accumulation layer over the semiconductor substrate of the first and second regions in order to cover the control gate electrode and the gate electrode of the first MISFET; (d) after the step (c), forming a second conductive film over the charge accumulation layer; (e) after the step (d), by anisotropically etching the second conductive film, forming memory gate electrodes over side surfaces of the control gate electrode and over side surfaces of the gate electrode of the first MISFET; (f) after the step (e), removing a memory gate electrode formed over one side surface of the control gate electrode and the memory gate electrode formed over the side surfaces of the gate electrode of the first MISFET, such that a memory gate electrode formed over the other side surface of the control gate electrode is kept; and (g) after the step (f), removing the charge accumulation layer formed over the one side surface of the control gate electrode and the charge accumulation layer formed over the side surfaces of the gate electrode of the first MISFET.