Patent ID: 8621300

Claim:
A process of operating a state machine, comprising: A. moving the state machine to a reset state with an enable signal of one state; B. moving the state machine from the reset state to an idle state with a protocol signal and a clock signal; C. moving the state machine from the idle state to a select test control register state with a protocol signal and a clock signal; D. moving the state machine from the select test control register state to a shift test control register state with a protocol signal and a clock signal; E. moving data into a test control register by maintaining the state machine in the shift test control register state with a protocol signal and a clock signal; F. moving the state machine from the shift test control register state to an update test control register state with a protocol signal and a clock signal; and G. moving the state machine from the update test control register state to the idle state with a protocol signal and a clock signal.