Patent ID: 7807513

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: forming an interlayer dielectric in a cell region and a peripheral region of a substrate; defining bit line contact holes on the interlayer dielectric in such a way as to expose portions of the substrate in the cell region; filling the bit line contact holes by forming a first polysilcion layer on the interlayer dielectric; forming a second polysilicon layer on the first polysilicon layer, the second polysilicon layer having a slower oxidation speed than the first polysilicon layer; removing the second polysilicon layer, the first polysilicon is layer and the interlayer dielectric that are formed in the peripheral region; and oxidating the second polysilicon layer formed in the cell region and a surface of the substrate in the peripheral region, thereby forming an oxide layer in the cell region and a gate oxide layer on the surface of the substrate in the peripheral region.