Patent ID: 7239178

Claim:
A voltage level translation circuit comprising: a resistive element configured to be coupled to a power supply voltage; a pulse generator responsive to an input signal having a first amplitude swing range, the pulse generator coupled to the resistive element; and a drive stage coupled to the resistive element and the pulse generator, the drive stage configured to produce an output signal having a second amplitude swing range, the second amplitude swing range different than the first amplitude swing range; and a latch configured to hold the output signal at a high level in response to a low to high transition of the input signal; the latch comprising: a first P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET), the first PMOSFET having a source coupled to the power supply voltage and a drain coupled to the output signal; and an inverter, the inverter coupled between the output signal and a gate of the first PMOSFET transistor, the pulse generator responsive to an output of the inverter.