Patent ID: 8170205

Claim:
An apparatus providing secured information reading from and writing to an external connected memory, comprising: a control unit connected to the external memory, the control unit includes: a CPU generating an access signal for writing data to or reading data from the external memory, an encryption/decryption controller being responsive to the access signal generated for writing to encrypt an address designated by the CPU to generate encrypted write address and encrypted write data, and the encryption/decryption controller being responsive to the access signal generated for reading an encrypted address designated by the CPU to generate an encrypted read address and to decrypted the encrypted data read from the external memory to generate plaintext data, an external controller configured to write the encrypted data in a position designated by the encrypted write address generated by the encryption/decryption controller and configured to read the encrypted data from a position designated by the encrypted read address generated by the encryption/decryption controller and supplies the same to the encryption/decryption controller for its decryption, and an internal bus connecting the CPU, the encryption decryption controller and the external controller and providing a bus for control and data signals, wherein upon encryption of data by the encryption/decryption controller, XORing (exclusive-ORing) of plaintext data corresponding to one block and a leading address of the block is computed and ECB mode encryption for each block cipher is effected on the result of computation thereof, and wherein upon decryption of data by the encryption/decryption controller, ECB mode decryption for each block cipher is effected on one block of the encrypted data and XORing of the result of decryption thereof and a leading address of the block is computed, thereby obtained plaintext data.