Patent ID: 8754484

Claim:
An integrated circuit, comprising: a substrate comprising a semiconductor; field oxide disposed at a top surface of said substrate, said field oxide surrounding a collector active area of a bipolar transistor; a collector layer of said bipolar transistor in said substrate, disposed at a top surface of said substrate, said collector layer having a first conductivity type; an MOS transistor, including: an MOS gate disposed on a gate dielectric layer, said MOS gate having a second conductivity type opposite from said first conductivity type; and source/drain regions disposed in said substrate adjacent to said MOS gate sidewalls, said source/drain regions having said second conductivity type; and said bipolar transistor including: a base layer of semiconductor material disposed on said collector active area and overlapping said field oxide adjacent to said collector active area, said base layer having said second conductivity type, said base layer having a polycrystalline region over said field oxide and a single crystalline region on said collector active area; a base-collector junction of said bipolar transistor extending into said substrate less than one-third of a depth of said field oxide; and an emitter on said single crystalline region of said base layer, said emitter having said first conductivity type; such that a vertically cumulative doping density, in units of cm −2 , of said polycrystalline region of said base layer is between 80 percent and 125 percent of a vertically cumulative doping density, also in units of cm −2 , of said MOS gate.