Patent ID: 8214598

Claim:
A method for flushing a plurality of cache lines of a processor comprising: receiving a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed, wherein the single instruction implicitly provides a starting address of the cache lines to be flushed; in response to the single instruction, flushing the plurality of cache lines of the processor by, loading a first register with at least a portion of the starting address of the cache lines to be flushed, loading a second register with a counter value that represents a number of cache lines to be flushed, flushing a first cache line associated with the starting address of the cache lines to be flushed, decrementing the counter value stored in the second register, updating the first register to contain a least a portion of a next address of a second cache line to be flushed, and flushing the second cache line.