Patent ID: 7737743

Claim:
An apparatus including integer-N phase-locked loop (PLL) circuitry, to provide an oscillator signal with a frequency that is N-times the frequency of a reference signal, comprising: sampling phase detection circuitry responsive to said reference signal and said oscillation signal by sampling said oscillation signal in accordance with said reference signal and providing a phase detection signal related to a phase difference between said reference signal and said oscillation signal; signal combining circuitry coupled to said sampling phase detection circuitry and responsive to said phase detection signal and a frequency detection signal by providing an oscillator control signal; oscillator circuitry coupled to said signal combining circuitry and said sampling phase detection circuitry, and responsive to said oscillator control signal by providing said oscillation signal at a frequency that is N-times said frequency of said reference signal; and divide-by-N frequency lock circuitry, including divide-by-N circuitry, coupled to said oscillator circuitry and responsive to said reference signal and said oscillation signal by providing said frequency detection signal related to a frequency difference between said reference signal and said oscillation signal divided by N; wherein, when said divide-by-N frequency lock circuitry establishes a frequency lock between said reference signal and said oscillation signal divided by N, said oscillation control signal and said oscillation signal are controlled by said sampling phase detection circuitry and phase detection signal.