Patent ID: 7259423

Claim:
A non-volatile memory cell comprising: a control gate pattern disposed over a semiconductor substrate and comprising a tunnel insulation pattern, a trap insulation pattern, a blocking insulation pattern and a control gate electrode, which are stacked; a selection gate electrode disposed over the semiconductor substrate at one side and extending over substantially the entire top portion of the control gate pattern; a gate insulation pattern interposed between the selection gate electrode and the semiconductor substrate, and between the selection gate electrode and the control gate pattern, wherein the gate insulation pattern covers the entire sidewall of the selection gate electrode proximal to the control gate pattern; a cell channel region comprising a first channel region defined in the semiconductor substrate under the control gate pattern and a second channel region defined in the semiconductor substrate under the selection gate electrode; drain/source regions formed in the semiconductor substrate at respective sides of the cell channel region; and a metal silicide layer formed over a predetermined region of a sidewall of the selection gate electrode, an exposed sidewall of the control gate electrode and a surface of the drain/source regions.