Patent ID: 7495279

Claim:
A semiconductor device, comprising: a silicon-on-insulator (SOI) substrate, the SOI substrate including a substrate, a buried insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the buried insulating layer; a plurality of isolation regions disposed in the layer of semiconductor material, wherein each isolation region extends completely through the layer of semiconductor material; and a plurality of flash memory cells formed on the SOI substrate, each flash memory cell having a source and drain in a body portion, the plurality of flash memory cells being arranged in an array of rows and columns, each column of flash memory cells being formed in a continuous region of the semiconductor layer and being separated from adjacent columns of flash memory cells by one of said isolation region such that the body portion of each flash memory cell in a column is electrically coupled to the body portions of each other flash memory cell in that column but is electrically isolated from the body portions of each flash memory cell in other columns; and an electrical connection to the body portions of said flash memory cells in each one of said column of said memory cell, said electrical connection being independent and separate such that the body portions of said memory cells in a column can be biased with respect to both said source and said drain and to a voltage level that is different from the body portions of flash memory cells in other columns.