Patent ID: 7271615

Claim:
A method of reducing leakage current in an array of circuits, each circuit having an active mode and an inactive mode, each circuit including a set of at least one NMOS transistor, each NMOS transistor in the set having its source connected to a common source node, each NMOS transistor in the set having a gate driven to a ground voltage VSS if its circuit is in the inactive mode, each NMOS transistor in the set being sized so as to conduct a first leakage current if its circuit is in the inactive mode, its source pulled to VSS, and its drain pulled to a power supply voltage VDD, the method comprising: if all the circuits in the array are in the inactive mode, switching on a first transistor coupled between the common source node and a ground terminal, the first transistor being sized such that the common source node thereby floats higher in potential than VSS to thereby drive the NMOS transistors to conduct a second leakage current that is less than the first leakage current.