Patent ID: 7764086

Claim:
A buffer circuit including at least one buffer interface stage, the buffer interface stage comprising: a first inverter having an input node coupled to first input terminal of the buffer circuit and an output node coupled to an output terminal of the buffer circuit; a second inverter having an input node coupled to a second input terminal of the buffer circuit and an output node; a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter; a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal; a fifth inverter having an input node and an output node coupled to the output terminal; a first resistive element coupled between the output terminal and the input node of the fifth inverter; a sixth inverter having an input node and an output node coupled to the output node of the second inverter; and a second resistive element coupled between the output node of the second inverter and the input node of the sixth inverter.