Patent ID: 8677176

Claim:
An apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device, the apparatus comprising: a first link connecting a first PCIE bridge with a first IO device, the first link being used for exchanging a first set of bussed bits between the first PCIE bridge and the first IO device over the first link using a first set of lanes of the first PCIE bridge, at least a second link connecting a second PCIE bridge with a second IO device, wherein the first and the second PCIE bridges are housed in a PCIE root complex, wherein the first PCIE bridge swaps from using the first set of lanes to using a second set of lanes of the first PCIE bridge at a PCIE bridge end in response to detecting a failure in the first link, for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes; and at least a switch at an IO end for switching from using the first set of lanes to using the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.