Patent ID: 8032717

Claim:
A memory control apparatus connected to a main memory storing data and a plurality of processors including a cache memory holding a part of the data stored in main memory and executing a data response process for a read request from any one of the plurality of processors, comprising: retention tags that hold separate data information indicating that data stored in the main memory is not held in any cache memory of the processors connected to the memory control apparatus; a data tag that hold tag information indicating that data stored in the main memory is held in any one of the cache memory of the processors; and a controller that transfers the read request from any one of the plurality of processors to the main memory when the retention tag is indicating that the data of the read request stored in the main memory is not held in any cache memory of the processors, or transfers the read request from any one of the plurality of processors to the cache memory when the data tag is indicating that the data of the read request is held in the cache memory.