Patent ID: 7886059

Claim:
An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a software application residing in the memory and executed by the at least one processor; a plurality of sockets residing in the memory and executed by the at least one processor, each socket receiving a plurality of messages that each include a sequence number generated by the software application and a logical connection identifier generated by the software application; and an asynchronous I/O sequenced completion port residing in the memory and executed by the at least one processor, the asynchronous I/O sequenced completion port defining a plurality of logical connections, wherein at least one of the plurality of logical connections include a plurality of the sockets, the asynchronous I/O sequenced completion port comprising: a sorted staging queue corresponding to each logical connection that reads the plurality of messages and that orders the plurality of messages for a corresponding logical connection according to their respective sequence number and logical connection identifier; wherein the asynchronous I/O sequenced completion port receives the ordered messages from each sorted staging queue, and delivers the ordered messages to the software application.