Patent ID: 8184680

Claim:
A data transceiver system, comprising: a data transmitter configured to output a reference clock signal and a plurality of data signals; and a data receiver configured to receive the reference clock signal and the plurality of data signals, determine whether a data frame has been locked, and output a lock signal according to the determination in a data frame lock operation, wherein one of the data transmitter and the data receiver comprises a plurality of delay units, each delay unit configured to delay a corresponding data signal among the plurality of data signals by a time in response to a corresponding delay code among a plurality of delay codes and to output the delayed data signal; an error detector configured to receive the plurality of delay codes, determine whether an error has occurred, and output an error signal according to the determination in the data frame lock operation; and a delay controller configured to set initial values of the plurality of delay codes to a predetermined value, vary and output each of the plurality of delay codes in response to the lock signal, and vary and output at least one of the plurality of delay codes in response to the error signal in the data frame lock operation.