Patent ID: 8335953

Claim:
A test access port comprising: A. a test clock input lead and a test mode select input lead; B. a test access port controller having a test clock input connected to the test clock input lead, a test mode select input connected to the test mode select input lead, a Clock-DR output, and a Pause-DR output; C. an instruction register having a first output and a second output; D. a first logic gate having an input connected to the first output of the instruction register, a second input connected to the Clock-DR output, and an output; E. a second logic gate having an input connected to the second output of the instruction register, a second input connected to the Pause-DR output, a third input connected to the test clock input lead, and an output; and F. a third logic gate having an input connected to the output of the first logic gate, another input connected to the output of the second logic gate, and a scan clock output.