Patent ID: 7863126

Claim:
A method for fabricating a CMOS structure, comprising: blanket disposing a gate insulator layer for an NFET device and for a PFET device, wherein said gate insulator layer comprises a high-k dielectric; in said NFET device, implementing an NFET gate conductor layer overlaying said gate insulator layer; blanket disposing an Al layer over said NFET gate conductor layer and over said high-k dielectric of said gate insulator layer in said PFET device; blanket disposing a shared gate metal layer over said Al layer, and insuring that prior to disposing of said shared gate metal layer said Al layer is free of oxygen; and exposing said PFET device to thermal annealing, wherein said high-k dielectric oxidizes said Al layer, thereby turning said Al layer into a PFET interfacial control layer.