Patent ID: 8339877

Claim:
A semiconductor memory device, comprising: a data input/output unit configured to receive an input data signal and output a write data driving signal, and to receive a read data driving signal and output an output data signal; a variable delay unit configured to generate a write data signal by variably delaying the write data driving signal depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and to generate a read data driving signal by variably delaying a read data signal depending on whether the semiconductor memory device is in the data training mode and the normal operating mode; and a data trainer configured to receive the write data signal, compare the write data signal with a stored write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern when activated in the data training mode, wherein the variable delay unit generates the write data signal by delaying the write data driving signal by a first delay and generates the read data driving signal by delaying the read data signal by a second delay during the data training mode operation, and generates the write data signal and the read data driving signal without delaying the write data driving signal and the read data signal during the normal operating mode.