Patent ID: 7768853

Claim:
A semiconductor memory device comprising: a substrate on which first and second memory-cell array regions and first and second sense-circuit regions are defined, the first memory-cell array region being disposed on a first side of the substrate, the second memory-cell array region being disposed on a second side of the substrate, the first and second sense-circuit regions being disposed between the first and second memory-cell array regions, the first sense-circuit region being disposed on the first side, and the second sense-circuit region being disposed on the second side; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and configured to selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and configured to selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.