Patent ID: 7626271

Claim:
A semiconductor device comprising: a semiconductor chip having a first main surface with an electrode pad in an exposed state and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-distribution wiring layer including a wiring pattern, said wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape in a plan view relative to the first main surface and connected to another end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface, said bottom surface having a contour crossing an upper contour of the post electrode mounting portion at at least two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode, wherein the recessed polygonal shape is a six-corner star.