Patent ID: 7286627

Claim:
A shift register circuit with high stability, the shift register circuit comprising a plurality of stages, each of said stages cascaded to the succeeding stage in sequence and transmitting an output signal, an input signal inputted to an input terminal of the first stage, an input signal of each of other stages being an output signal of previous stage, and the shift register circuit provided with first and second clock signals in an inverse condition, each of stages comprising: a shift register circuit unit and a supplementary unit for electrically connecting to an output node of the shift register circuit unit, whereby the output signal of the output node is fed back to the shift register circuit unit and acts as a control signal, the control signal controls the shift register circuit unit; wherein the supplementary unit comprises: a first supplementary thin film transistor (TFT) with a gate electrode electrically connected to a first derivative node of the shift register circuit unit, a drain electrode electrically connected to the output node, and a source electrode electrically connected to a supply voltage with low voltage level; a second supplementary TFT with a gate electrode electrically connected to a second derivative node of the shift register circuit unit, a drain electrode electrically connected to the output node, and a source electrode electrically connected to a supply voltage with low voltage level; and a third supplementary TFT with a gate electrode electrically connected to the second derivative node of the shift register circuit unit, a drain electrode electrically connected to the first derivative node of the shift register circuit unit, and a source electrode electrically connected to a supply voltage with low voltage level.