Patent ID: 7064029

Claim:
A method of producing a semiconductor memory device provided with at least an access transistor having a gate and a pair of impurity diffusion layers, and at least a memory capacitor having a storage node electrode and a cell plate electrode, the electrodes being connected to each other by capacitive coupling through a dielectric film, the method comprising: forming a first insulating film that covers the access transistor; forming a hole by patterning the first insulating film to expose a portion of a surface of one of the pair of the impurity diffusion layers through the hole; forming a second insulating film that covers an inner side wall of the hole; forming an intermediate conductive film electrically connected to at least one of the pair of impurity diffusion layers; forming a first conductive film on the first insulating film so that the hole is filled with the first conductive film on the second insulating film and the intermediate conductive film; ensuring that the first conductive film remains in the hole by removing only a portion of the first conductive film on the first insulating film so that an upper surface of the second insulating film is exposed; forming the storage node electrode by removing the second insulating film to form a space between the first conductive film and the inner wall of the hole, wherein the first conductive film and intermediate conductive film remain in the hole so that the storage node electrode is formed in a shape of a column surrounded by the space on at least one of the pair of the impurity diffusion layers in the hole in a circular conic that becomes larger close to an upper surface, and wherein the upper surface of the column does not extend above an upper surface of the first insulating film; forming the dielectric film comprising a ferroelectric material to cover a surface of the storage node electrode; forming a second conductive film on the first insulating film so that the space in the hole is filled with the second conductive film; and forming a cell plate electrode on the first insulating film so that the cell plate electrode covers the storage node electrode and the dielectric film by patterning the second conductive film.