Patent ID: 8339831

Claim:
A one-time-programmable memory device comprising: a one-time-programmable memory cell array comprising a plurality of memory cells, wherein each memory cell of the plurality of memory cells arranged at an intersection of a bit line and a word line comprises: a first gate formed on a surface of the substrate utilizing a first conductivity type; a second gate formed on the surface of the substrate; a first diffusion region of a second conductivity type different than the first conductivity type formed on a side of the first gate; a second diffusion region of the second conductivity type formed on another side of the second gate opposite to the first diffusion region; and a middle diffusion region of the second conductivity type formed between the first gate and the second gate; a boost capacitor; and a programming verification circuit coupled to each memory cell of the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming; wherein the second diffusion region merges with the middle diffusion region under the second gate, the first diffusion region is separate from the middle diffusion region, and each boost capacitor isolates leakage current of a corresponding programmed memory cell.