Patent ID: 8471744

Claim:
A chopper-stabilized sigma-delta modulator comprising: an analog input; a first sample, hold, and integrate block that receives the analog input and receives a differential feedback signal, the first sample, hold, and integrate block having a first sampling capacitor and first phase switches and a first differential output; a first op amp having a first op amp differential input and a first op amp differential output; a first chopper multiplier, coupled between the first differential output and the first op amp differential input, the first chopper multiplier passing the first differential output through to the first op amp differential input in response to a first chopper clock, the first chopper multiplier swapping differential signals from the first differential output to drive the first op amp differential input in response to a second chopper clock; a second chopper multiplier, coupled between the first op amp differential output and an intermediate differential signal, the second chopper multiplier passing the first op amp differential output through to the intermediate differential signal in response to the second chopper clock, the second chopper multiplier swapping differential signals from the first op amp differential output to drive the intermediate differential signal in response to the second chopper clock; a second sample, hold, and integrate block that receives the intermediate differential signal and receives the differential feedback signal, the second sample, hold, and integrate block having a second sampling capacitor and second phase switches and a second differential output; a second op amp receiving the second differential output and generating a second op amp differential output; a quantizer that converts the second op amp differential output to a binary bit to generate the differential feedback signal as an output of the chopper-stabilized sigma-delta modulator; a first phase clock that is applied to the first phase switches and to the second phase switches; a second phase clock that is applied to the first phase switches and to the second phase switches; and a clock generator that generates the first chopper clock and the second chopper clock as non-overlapping clocks having a second frequency, and that generates the first phase clock and the second phase clock as non-overlapping clocks having a first frequency that is a multiple of the second frequency, the clock generator generating edges of the first and second chopper clocks to occur before edges of the first phase clock and the second phase clock, when the first phase clock, the second phase clock, the first chopper clock, and the second chopper clock all change at a beginning of a chopper clock period, whereby chopper clock edges are generated before phase clock edges in the chopper clock period.