Patent ID: 6864727

Claim:
A clock doubling and polarity control circuit having an input signal and an output signal, the circuit comprising: a multiplexer having a select input for selecting between inverting and non-inverting paths for the clack doubling and polarity control circuit input signal; a polarity selector having: a selectable path for providing a logic high polarity select output signal for controlling the multiplexer; a selectable path for providing a logic low polarity select output signal for controlling the multiplexer; and a selectable path for providing a polarity select output signal for controlling the multiplexer that is a function of the clock doubling and polarity control circuit input signal; wherein the polarity select output signal is coupled to the multiplexer select input; and wherein one of the selectable paths for providing the logic high and logic low polarity select output signals causes the clock doubling and polarity control circuit output signal to be equal to the clock doubling and polarity control circuit input signal, another of the selectable paths for providing the logic high and logic low polarity select output signals causes the clock doubling and polarity control circuit output signal to be inverted from the clock doubling and polarity control circuit input signal, and the selectable path for providing the polarity select output signal that is a function of the clock doubling and polarity control circuit input signal causes the clock doubling and polarity control circuit output signal to switch shortly after the clock doubling and polarity control circuit input signal switches and then to return to its former state a delay time after the clock doubling and polarity control circuit input signal switches, thereby functioning as a pulse generator.