Patent ID: 7200026

Claim:
A ferroelectric memory device comprising: a constant voltage source generating a predetermined voltage selectively supplied to the bit line; a ferroelectric capacitor having a first end electrically coupled to a bit line and a second end electrically coupled to a plate line, the ferroelectric capacitor having a capacitance that varies based on data stored in the ferroelectric capacitor and the predetermined voltage; a resistor formed between the bit line and the constant voltage source having a first end electrically coupled in series with a first transistor and a second end electrically coupled to the bit line, the first transistor formed between the bit line and the constant voltage source and having a gate electrically coupled to a read signal that controls whether the predetermined voltage is provided to the bit line via the resistor during a predetermined period; a second transistor between the ferroelectric capacitor and the bit line having a first end electrically coupled to the bit line, a second end electrically coupled to the ferroelectric capacitor, and a gate electrically coupled to a word line, ; and a third transistor having a first end electrically coupled to the bit line, a second end electrically coupled to a pre-charge voltage source, and a gate electrically coupled to a potential charge signal, the pre-charge voltage source selectively charges the bit line to a pre-charge voltage based on the potential charge signal.