Patent ID: 6992509

Claim:
A sample/hold circuit, comprising: an amplifier having an output for providing an output of said sample/hold circuit; a first capacitor for sampling a value of an input signal during a first sampling phase of a sample clock; a second capacitor for sampling a value of said input signal during a second sampling phase of said sample clock; and a switching circuit for alternatively selecting one of said first capacitor and said second capacitor for coupling to said input signal during each phase of said sample clock, wherein another one of said first capacitor and said second capacitor not selected for coupling to said input signal is coupled between said output of said amplifier and an input of said amplifier for holding a value at an output of said amplifier sampled during a previous phase of said sample clock, whereby each of said first capacitor and said second capacitor alternates between sampling said input signal and holding said value in a mutually-exclusive manner, whereby transitions in said output of said amplifier are reduced between sampling intervals of said sample/hold; wherein said sample/hold circuit further comprises at least one input bootstrap clock circuit coupled to said switching circuit for generating a control signal having an on-state control voltage derived in conformity with a voltage level of said input signal, whereby the on-state of a control voltage input of at least one switch that couples said first capacitor to said input signal is maintained at a substantially constant level with respect to said input signal.