Patent ID: 7333379

Claim:
A circuit adjusting method, comprising: providing a digital circuit, which includes: (a) a reading circuit, which includes a first transistor and a second transistor, wherein the first and second transistors comprise: (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively, (b) a control circuit, which is electrically coupled to the first and second transistor bodies, respectively, and (c) a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit; using the testing circuit to determine, for a first balanced determination round, whether strengths of the first and second transistors are different; and in response to the testing circuit determining that the strengths of the first and second transistors are different, using the testing circuit to cause the control circuit to adjust the voltage of the first transistor body for a first time, wherein the control circuit comprises a multiplexer, wherein the multiplexer includes a first multiplexer output node and a second multiplexer output node, wherein the first multiplexer output node is electrically coupled to the first transistor body, and wherein the second multiplexer output node is electrically coupled to the second transistor body.