Patent ID: 7679199

Claim:
A semiconductor apparatus comprising: a first semiconductor chip; a second semiconductor chip that is laminated on said first semiconductor chip; a plurality of first electrode pads formed on said first semiconductor chip; a plurality of second electrode pads formed on said second semiconductor chip; a first wiring that is coupled to two first electrode pads, which are selected from said plurality of first electrode pads, and formed along the outer periphery of said first semiconductor chip; a second wiring that is coupled to two second electrode pads, which are selected from the plurality of second electrode pads, and formed along the outer periphery of said second semiconductor chip; and a third wiring that is coupled to both one of said plurality of first electrode pads being coupled to one end of said first wiring and one of said plurality of second electrode pads being coupled to one end of said second wiring, and couples said first wiring and said second wiring in series.