Patent ID: 7694253

Claim:
A computer-implemented method for automatically generating a deterministic input sequence for a circuit design using mutant-based verification, comprising: electronically receiving a description of the circuit design; electronically determining, using a computer, a target value for a control signal in the description; electronically determining a mutant value for the control signal; electronically determining if an input sequence for the circuit design exists that stimulates the control signal to the target value and causes the effects of the target value and the effects of the mutant value to reach an observation point in the circuit design such that the effects of the target value and the effects of the mutant value differ at the observation point, by: electronically generating a target prospect state which represents an activated state of the circuit design that satisfies the target value for the control signal, wherein a prospect state which represents a state of the circuit design includes a first constraint-dependency graph that defines a set of constraints to be satisfied simultaneously and includes a second constraint-dependency graph that defines the set of conditional values that allow the set of constraints to be satisfied simultaneously; and electronically determining an input sequence by electronically analyzing a set of prospect states to find a first path of prospect states from the activated state to a reset state of the circuit design and to find a second path of prospect states from the activated state to the observation point; if so, electronically simulating operation of the circuit design using the input sequence; and during simulation, electronically generating a first set of signal values affected by the target value for the control signal and a second set of signal values affected by the mutant value for the control signal.