Patent ID: 8307323

Claim:
A method for analog placement and global routing considering wiring symmetry, which is executed in a computer to perform a layout for an analog circuit described by a netlist having a set of devices and wires connected thereon, the method comprising the steps of: (A) inputting the netlist, using the computer, each device of the netlist having a design constraint, each design constraint corresponding to a priority; (B) establishing a hierarchical constraint tree based on the design constraint and corresponding priority of each device; (C) performing a sorting on the devices based on the priorities; (D) performing a placement on each device according to the hierarchical constraint tree, wherein possible shapes of each device are represented by a shape curve; (E) calculating a corresponding cost function for each placement of the device, and selecting an optimum placement of the device according to the cost functions; (F) establishing a rectilinear Steiner minimal tree (RSMT) for each wire; and (G) performing an analog routing.