Patent ID: 7526632

Claim:
A processing node for executing extended instructions in a reconfigurable data path processor, the processing node comprising: a modular processing element including a reconfigurable circuit configured to perform a computation associated with an extended instruction, the modular processing element configured to define state data associated with the extended instruction; a set of multifunctional memories including a first multifunctional memory and a second multifunctional memory, the reconfigurable circuit configured to define an index into the set of multifunctional memories; and a data flow director configured to selectably couple via a reconfigurable path the first multifunctional memory and the second multifunctional memory to the modular processing element, the state data being transferred from the modular processing element to at least one of the first multifunctional memory or the second multifunctional memory via the reconfigurable path and based on the index, at least one of the first multifunctional memory or the second multifunctional memory being configured to operate as a Boolean function memory during a first period of time and configured to operate as a read/write scratch pad memory during a second period of time different from the first period of time, the data flow director configured to simultaneously route data from the first multifunctional memory and route data into the second multifunctional memory while the computation is being performed.