Patent ID: 6954832

Claim:
An interleaver memory structure for facilitating the decoding of a plurality of encoded symbols, the interleaver memory structure comprising: during a first clock cycle: a first interleaver pattern memory receives a first sequential read address; a second interleaver pattern memory receives a first sequential write address; during a second clock cycle: the first interleaver pattern memory receives a second sequential write address; the second interleaver pattern memory receives a second sequential read address; a first read address is received from the first interleaver pattern memory for use by a first interleaver memory; a first write address is received from the second interleaver pattern memory for use by a second interleaver memory; during a third clock cycle: the first interleaver pattern memory receives a third sequential read address; the second interleaver pattern memory receives a third sequential write address; a second write address is received from the first interleaver pattern memory for use by the first interleaver memory; a second read address is received from the second interleaver pattern memory for use by the second interleaver memory; a first data is read from the first interleaver memory; a second data is written to the second interleaver memory; and wherein each of the first interleaver pattern memory, the second interleaver pattern memory, the first interleaver memory, and the second interleaver memory are implemented using single port memory structures.