Patent ID: 6924525

Claim:
A semiconductor integrated circuit device comprising: first MISFETs formed in a first region, each of said first MISFETs at least having a source region and a drain region; second MISFETs formed in a second region, each of said second MISFETs at least having a source region and a drain region; at least one bit line formed over said first region; at least one word line formed in said first region; at least one capacitor element formed over one of said bit lines, wherein each of said first MISFETs is included in an individual one of plural memory cells, each of said memory cells being coupled to a respective word line, a respective bit line and said capacitor element corresponding thereto; a first insulating film interposed between said first and second MISFETs and said at least one bit line; a second insulating film formed over said first insulating film, said second insulating film being interposed between said at least one bit line and said at least one capacitor element; and a wiring layer formed over said second insulating film, wherein each of said at least one bit line is connected to one of said source and drain regions of ones of said first MISFETs corresponding thereto via one of first plugs formed in said first insulating film, wherein each of said at least one capacitor element is connected to the other of said source and drain regions of ones of said first MISFETs corresponding thereto via a corresponding second plug formed in said second insulating film and another of said first plugs, wherein said wiring layer is connected to said source and drain regions of ones of said second MISFETs via respective ones of third plugs formed in said first and second insulating film, and wherein said second plug is formed of a built-up film.