Patent ID: 8661320

Claim:
A system for memory error correction, comprising: a data word having one or more bit errors; m sets of virtual data words wherein each data word of each of m sets of virtual data words shares a single bit with a previous virtual data word of a previous set of virtual data words; and a check bit portion associated with the data word and a virtual check bit portion associated with each virtual data word wherein the check bit portion and the virtual check bit portions are each operable to detect or correct one or more bit errors in the respective data word and the virtual data word, wherein the system is configured for determining whether each virtual word in the m th set of virtual data words includes no more than a single bit error and is responsive to determining that each virtual data word in the m th set of virtual data words includes no more than a single bit error, correcting the single bit error using the virtual check bit associated with that virtual data word thereby correcting one or more bit errors in the m th −1 virtual data word.