Patent ID: 8717795

Claim:
A semiconductor device comprising: first and second ports arranged in a first direction; first and second data lines extending in a second direction that is substantially orthogonal to the first direction between the first and second ports; a first circuit arranged between the first and second ports and including a plurality of sub circuits connected in series between the first port and the first data line, the plurality of sub circuits of the first circuit including at least a first sub circuit; a second circuit arranged between the first and second ports and including a plurality of sub circuits connected in series between the second port and the second data line, the plurality of sub circuits of the second circuit including at least a second sub circuit; a control line extending in the second direction between the first and second ports and transmitting a timing signal to control the first and second sub circuits in common; a first branch line branched from the control line and extending in the first direction to supply the timing signal to the first sub circuit; and a second branch line branched from the control line and extending in the first direction to supply the timing signal to the second sub circuit, wherein a first coordinate that is an intermediate coordinate between the first and second sub circuits in the first direction is different from a second coordinate that is an intermediate coordinate between the first and second ports in the first direction, and the first and second branch lines have substantially the same length in the first direction.