Patent ID: 7235413

Claim:
A fabrication method of semiconductor integrated circuit devices, comprising the steps of: (a) preparing a semiconductor wafer which is partitioned into a plurality of chip areas, a semiconductor integrated circuit being formed in each of said plurality of chip areas, and over whose main face a plurality of first electrodes electrically connected to said semiconductor integrated circuits are formed; (b) preparing a first card which holds a first sheet having a wiring electrically connected to a plurality of contact terminals for establishing contact with said plurality of first electrodes and said plurality of contact terminals so that tips of said plurality of contact terminals protrude toward the main face of said semiconductor wafer; and (c) electrically inspecting said semiconductor integrated circuits by bringing said plurality of contact terminals into contact with said plurality of first electrodes, wherein said tips of said plurality of contact terminals are arranged over a first face of said first sheet, and a plurality of second electrodes formed from part of said wiring are arranged over a second face of said first sheet, reverse to said first face, wherein said first card has a first substrate electrically connected to said plurality of second electrodes and suppressing mechanisms for suppressing said plurality of contact terminals toward said plurality of first electrodes, wherein said first substrate has a first circuit and over its main face a plurality of third electrodes electrically connected to said first circuit are formed, wherein said plurality of third electrodes are electrically connected to the respectively matching ones of said plurality of second electrodes via first wires, wherein the number of said first wires electrically connected between said second electrodes and said third electrodes through which relatively large currents flow is relatively greater than the number of said first wires electrically connected between said second electrodes and said third electrodes through which relatively small currents flow, wherein said suppressing mechanisms are arranged above said plurality of contact terminals over said second face of said first sheet, and wherein one of said suppressing mechanisms suppresses one or more of said contact terminals.