Patent ID: 8661308

Claim:
A method for fast cyclic redundancy check encoding, comprising the following steps that are executed by a base band chip: mapping a Cyclic Redundancy Check (CRC) encoding generator polynomial to generate an (r+1)-order transfer matrix J, wherein r is a highest degree of the generator polynomial and r is a natural number; deleting a first row and a first column of said (r+1)-order transfer matrix J to obtain an r-order transfer matrix T; forming an r×1 column matrix S by first columns of 2 nd to r+1 th rows of said (r+1)-order transfer matrix J; obtaining a zero input transfer matrix P and a zero state transfer matrix Ω of CRC encoding according to the obtained r-order transfer matrix T and r×1 column matrix S; adding dummy bits before an input bit stream, wherein the number of bits of the input bit stream after adding the dummy bits is an integral multiple of a parallel operation bit width N, and N is a positive integer more than 1; obtaining a CRC encoding check sequence of the input bit stream according to the obtained zero input transfer matrix P, the zero state transfer matrix Ω and the input bit stream after adding the dummy bits.