Patent ID: 6849499

Claim:
A method of forming a novel flash memory cell comprising the steps of: providing a substrate having active regions defined by shallow trench isolation regions in said substrate; forming a gate oxide layer over said substrate; forming a silicon (Si) layer over said gate oxide layer; forming a first nitride layer over said Si layer; forming a tapered opening in said first nitride layer along a first axis of said substrate over said STI regions to form a first hardmask over said Si layer; using said first hardmask to etch underlying said Si layer to expose STI regions and form a fist edge of a Si floating gate; removing said first nitride layer; forming a second nitride layer over said Si layer; forming a second opening in said second nitride layer along a second axis of said substrate to form a second hardmask exposing portions of said Si layer in said second openings; using said second hardmask to form an oxide cap over said Si layer exposed in said second openings; removing said second nitride layer; etching said Si layer adjacent said oxide cap to form a second edge to complete the forming of said Si floating gate; forming an intergate oxide layer over said Si floating gate; forming an Si control gate over said intergate oxide layer; forming an intergate oxide layer over said oxide cap; and forming a control gate over said intergate oxide layer.