Patent ID: 8907710

Claim:
A digitally controlled delay device, comprising: a delay generating device, wherein a propagation delay of the delay generating device is controlled by limiting an operating current of the delay generating device, wherein the operating current is limited by a tail transistor controlled by its gate voltage; a controller for controlling the gate voltage of the tail transistor, the controller including: a bank of digitally controlled MOSFET transistors having a common drain connection and a common source connection, each of the digitally controlled MOSFET transistors in the bank having a first polarity, and the tail transistor having a second polarity opposite the first polarity; wherein each of the MOSFET transistors in the bank is configured to be individually selectively controlled; wherein each of the MOSFET transistors in the bank is configured to be controlled in diode mode by driving a voltage on the gate of each of the MOSFET transistors to either of two power supply rail voltages; wherein the controller is configured to apply a common gate-source voltage to each selected digitally controlled MOSFET transistor in the bank causing a first current to flow through the bank, establishing a resulting voltage at the common source connection of the bank; and apply the resulting voltage as the gate voltage of the tail transistor causing a second current to flow through the tail transistor, so that the ratio of the second current to the first current is defined by the selected digitally controlled MOSFET transistors in the bank operating in diode mode; and a digital control adapted to selectively switch each of the digitally controlled MOSFET transistors of the bank to off or to diode mode.