Patent ID: 7627836

Claim:
A method for optimizing an integrated circuit chip comprising: identifying timing sensitive devices that are within a critical timing path of said integrated circuit chip; generating by using optical proximity correction (OPC) techniques that run on a computer system, an additional mask for a lithography overexposure of a subsection of said integrated circuit chip to shorten gate lengths of each of said timing sensitive devices without shortening gate lengths of devices that are not within the critical timing path by forming a selective trim in a similar direction as said lithography overexposure; and generating a first set of timing rules for said integrated circuit chip including said timing sensitive devices; comparing said first set of timing rules to predetermined product requirements; shortening each of said gate lengths of said timing sensitive devices an incremental amount if said predetermined product requirements are not met by said first set of timing rules; regenerating a subsequent set of timing rules based on the shortening of each of said gate lengths of said timing sensitive devices; and repeating steps of comparing said subsequent set of timing rules to predetermined product requirements and regenerating timing rules and shortening said gate lengths until said predetermined product requirements are met.