Patent ID: 7721069

Claim:
A heterogeneous, scalable processor, said processor comprising: a first heterogeneous programmable integrated circuit sub-processor configured for 16, 24, 32 and 64-bit processing; and a second heterogeneous programmable integrated circuit sub-processor configured for 8, 4 and 1-bit processing, wherein at least one of the first and second sub-processors includes one or more macro-functional units (MFUs) corresponding to a programmable subset of one or more commonly occurring operations of target applications, wherein each of the MFUs include a local memory therein for local computation, and are configured for rearrangement of data values to and from the local memory, and wherein each of the first and second sub-processors can only execute one function or stream of data at a time, and include a built in control block dedicated to controlling and synchronizing an order of function execution.