Patent ID: 7030439

Claim:
A DRAM memory cell comprising: an interlayer dielectric disposed on a semiconductor substrate; storage node contact plugs disposed on the semiconductor substrate that are rectangular from a plan view perspective, a long axis of the rectangular storage node contact plugs extending in a direction parallel to a bit line, the storage node contact plugs having sidewalls in contact with the interlayer dielectric, the storage node contact plugs having a first cross-section in the direction parallel to the bit line, the first cross-section substantially Y-shaped in a region where the sidewalls contact the interlayer dielectric; and storage node electrodes disposed on the interlayer dielectric and in contact with the storage node contact plugs, the storage node electrodes contacting their respective storage node contact plugs at locations that are substantially offset, in the direction parallel to the bit line, from a center of the storage node contact plug.