Patent ID: 7444499

Claim:
A method, comprising: generating an extended instruction trace representative of M distinct threads of instruction execution from an instruction trace representative of N distinct threads of instruction execution, wherein N is an integer greater than or equal to 1, and wherein M is an integer greater than N; wherein each of said N distinct threads of said instruction trace includes memory references to respective memory addresses, and wherein generating said extended instruction trace from said instruction trace comprises: replicating said N distinct threads to generate said M distinct threads; assigning a respective unique identifier to each of said M distinct threads; and for at least some of said memory references included in a given one of said M distinct threads, hashing a first portion of each of said respective memory addresses dependent upon said respective unique identifier of said given one of said M distinct threads, wherein said first portion of each of said respective memory addresses corresponds to at least part of an index of a memory structure shared by at least two of said M distinct threads.