Patent ID: 8212151

Claim:
A wiring substrate comprising: an insulating layer; a wiring formed on the insulating layer; and a solder resist layer formed on the insulating layer so as to cover at least a portion of the wiring, the solder resist layer being constituted by a plurality of layers, wherein each one of the plurality of layers contains fillers, the fillers in one layer being of different maximum grain diameter than those of the other layers, a layer thickness of an innermost layer for constituting the plurality of layers is thicker than a layer thickness of the wiring, a maximum grain diameter of the filler contained in the innermost layer is smaller than a shortest interval between adjacent lines of the wiring, and the maximum grain diameter of the filler contained in the innermost layer is smaller than the maximum grain diameter of the filler contained in the other layers, and the maximum grain diameter of the filler in at least one of the plurality of layers other than the innermost layer is larger than a shortest interval between adjacent lines of the wiring.