Patent ID: 7135903

Claim:
An apparatus comprising: a plurality of differential amplifiers each having inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines; and a biasing circuit switchably coupled to each of the differential amplifiers, the biasing circuit including a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of differential amplifiers in the plurality of differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of differential amplifiers in the plurality of differential amplifiers, wherein each transistor of the first plurality of biasing transistors is responsive to a respective bit of a first digital control value to select between a first and a second mode of operation of a selected one of the first set of differential amplifiers, wherein the first mode of operation enables a current flow within the selected one of the first set of differential amplifiers, and wherein the second mode of operation disables a current flow within the selected one of the first set of differential amplifiers.