Patent ID: 7842558

Claim:
A method comprising: patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask; providing at least one gate layer in a logic portion of the semiconductor substrate and at least one sacrificial layer in the array portion of the semiconductor substrate; after patterning the first plurality of semiconductor structures, patterning a plurality of gate structures from the gate layer over the logic portion of the semiconductor substrate using a second photolithographic mask; patterning the sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask, wherein patterning the plurality of gate structures and patterning the sacrificial layer are performed simultaneously; using the patterned sacrificial layer to define a hard mask over the array portion of the semiconductor substrate, wherein a hard mask material is deposited between features of the patterned sacrificial layer; and subsequently removing all of the patterned sacrificial layer.