Patent ID: 8595389

Claim:
A distributed performance counter device, comprising: a plurality of first performance counter modules coupled to a plurality of processing cores, the plurality of first performance counter modules operable to collect performance data associated with the plurality of processing cores respectively; a plurality of second performance counter modules coupled to a plurality of L2 cache units, the plurality of second performance counter modules operable to collect performance data associated with the plurality of L2 cache units respectively; and a central performance counter module operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, wherein the central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules are connected by a daisy chain connection, and the plurality of first performance counter modules, and the plurality of second performance counter modules place respective count data on the daisy chain connection every predetermined cycle for transferring the count data to the central performance counter module for central storage, the central performance counter module aggregating the respective count data into higher resolution count for each of the first performance counter modules and the second performance counter modules, the predetermined cycle determined based on at least a number of performance counters per each of the first performance counter modules and the second performance counter modules, a number of the first performance counter modules and the second performance counter modules connected on the daisy chain connection, and a number of bits that can be transferred at one time on the daisy chain connection, wherein the central storage of the central performance counter module is configured to operate in multiple modes, the multiple modes comprising at least a distributed mode, in which each of the first performance counter modules and the second performance counter modules provides counts to the central storage, and a detailed mode, in which a single processing core or a single L2 cache unit provides counts to the central storage, wherein the central performance counter module injects framing information on the daisy chain connection for each of the first performance counter modules and the second performance counter modules to use in placing the count data on the daisy chain connection, wherein the central performance counter module further places a near-overflow interrupt on the daisy chain connection for one or more of the first performance counter modules and the second performance counter modules to receive and handle.