Patent ID: 7149992

Claim:
A method of resolving timing violations in a network of components and interconnects for a physical design of an integrated circuit, the method comprising: performing a timing analysis on the network, one or more components or interconnects of the network, each having a particular amount of timing violation potential; and performing a selective in-place optimization by identifying components or interconnects of the network that have the highest amount of timing violation potential and executing an in place optimization according to the identified components or interconnects; wherein the step of performing a selective in-place optimization includes: obtaining user-provided criteria, the criteria including cell delay, transition times, net cap and interconnect delays; generating, in a set of reports, timing, transition, cap violation data, rc information and critical nets for the entire design; scanning the generated reports; performing logic operations to generate a selection list of selected components or nets or both with the greatest amount of timing violation potential based on the user-provided criteria and removing clock nets from the selection list; and performing an in-place optimization with only the selected components on nets or both.