Patent ID: 7200057

Claim:
Apparatus for testing a static random access memory (SRAM) cell for the presence of a weak defect, the SRAM cell having an initial logic state and comprising a flip-flop circuit connected between two bit lines (BL, BLB) and coupled to a word line (WL), the apparatus comprising: a) means for pre-charging at least one of said bit lines (BL, BLB) to a predetermined level; b) means for enabling said word line (WL); and c) means for determining, after said word line (WL) has been enabled, the logic state of the SRAM cell to determine if the logic state has changed from said initial logic state; characterized in that the apparatus further comprises means for programming a trip voltage based on specific cell criterion and/or characteristics, and means for driving, after said word line (WL) has been enabled and before said logic state is determined, at least one of said bit lines (BL, BLB), or a node voltage proportional thereto, to said trip voltage.