Patent ID: 7419876

Claim:
A method for manufacturing non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry, the manufacturing method comprising the following steps: forming a plurality of gates of the matrix memory cells, each gate including a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer; forming a plurality of gates of transistors of said circuitry each gate of said circuitry transistors including a first dielectric layer and a first conductive layer, coating, with at least one protection dielectric layer, said gates of the matrix and of the circuitry; coating, with a first coating layer, said gates of the matrix and of the circuitry, said first coating layer being highly selective with respect to said protection dielectric layer; forming an intermediate dielectric layer on the first coating layer; forming a second coating layer on said intermediate dielectric layer, said second coating layer being highly selective with respect to said intermediate dielectric layer; carrying out a first blanket etching step of the second coating layer, selective with respect to the intermediate dielectric layer, to form first coating spacers on the intermediate dielectric layer respectively aligned with side walls of said gates of the memory cells and second coating spacers on the intermediate dielectric layer respectively aligned with side walls of said gates of the circuitry; shielding said gates of said transistors of the circuitry with a photo-lithographic mask; carrying out a selective removal step of the second coating layer in areas left exposed by the photo-lithographic mask to completely remove said first coating spacers of the matrix; removing said mask; carrying out a blanket etching step of the intermediate dielectric layer until said first coating layer, covering an upper portion of said gates, is uncovered so as to form first dielectric spacers in the matrix and second dielectric spacers in the circuitry; carrying out an etching step in plasma of the coating layers and of the second coating spacers, until the dielectric layers covering the gates on top are uncovered; carrying out HDD implants in the circuitry; carrying out a blanket etching step of the protection dielectric layer until upper portions of said gates are uncovered and the second dielectric spacers are removed and thus uncovering second coating spacers on the side walls of said gates of the memory cells and third coating spacers on the side walls of said gates of the circuitry, said third coating spacers being wider than said second coating spacers.