Patent ID: 8003532

Claim:
A method of backside metal processes for a semiconductor wafer with electronic devices fabricated thereon comprising steps of: fabricating backside via holes on a wafer backside using lithography techniques follows by etching process to etch through the wafer to a surface metal layer; coating a thin metal layer or a thin metal alloy layer as a metal seed layer on a rear surface of the wafer and on an inner sidewalls of the backside via holes using an electroless plating method, wherein said electroless plating method for coating the thin metal layer or the thin metal alloy layer as the metal seed layer is performed by immersing the semiconductor wafer in a plating solution containing sources of metals, followed by reaction of an additive agent, which makes metallic ions in the plating solution metalized to a thin film on the backside of the semiconductor wafer, wherein said metal seed layer coated by the electroless plating method has a preferred thickness in a range of 20-500 nm; and depositing a backside metal layer directly on the metal seed layer after the coating of the metal seed layer to make good electrical contact between the surface metal layer and the backside metal layer via the backside via holes.