Patent ID: 6856536

Claim:
A non-volatile RAM memory array comprising: a plurality of memory cells formed on a semiconductor substrate, each cell capable of being selected through a select line and a data line, whereby the select line and the data line are perpendicular to each other, and having a transistor that controls current flow through the memory cell depending on the voltage of the select line; a multi-resistive state material that changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the multi-resistive state material; changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the multi-resistive state material, the second voltage pulse across the multi-resistive state material being of opposite polarity to the first voltage pulse; and maintains the resistive state even if power ceases to be supplied to the memory cell; wherein the resistive state of the memory cell determines the information stored in the memory cell; and wherein the first voltage pulse and the second voltage pulse have magnitudes between 1 and 10 volts and ate generated from a voltage supply (V CC ) that has been converted to by at least two on-chip voltage converters.