Patent ID: 7596849

Claim:
A method of assembling a wafer-level package filter, the method comprising: providing a capping substrate; constructing a capping circuit on the capping substrate; providing a carrier wafer and a device wafer having compatible coefficients of thermal expansion such that a thermal mismatch is prevented during elevated temperatures of a wafer bonding process, the device wafer having a device circuit on a surface thereof; forming a device metalization layer on the surface of the device wafer, wherein the device metallization layer includes an active die filter area including the device filter; applying an adhesive seal on the device metalization layer for placing the active die filter area and thus the filter device within a cavity; removably attaching the capping substrate to a surface of the carrier wafer; aligning the carrier wafer with the device wafer; bonding the carrier wafer to the device wafer by attaching the capping substrate having the capping circuit thereon to the adhesive seal for securing the capping substrate to the device wafer having the device metallization layer thereon; releasing the bonded capping substrate and the device wafer from the carrier wafer; applying a dielectric layer over the capping substrate while maintaining exposure to the capping circuit; and applying an I/O metallization layer for joining an I/O connection of the capping circuit with an I/O connection of the device wafer and thus electrically connecting the capping circuit to the device filter.