Patent ID: 7385864

Claim:
A set of test structures used for on-chip assessment of the static noise margin of a memory cell of an integrated circuit device, comprising: first and second test structures, individually comprising: a memory cell, having one or more half-bits; and left and right half-bit test structures, comprising hard-wired connections between select nodes of each memory cell half-bit and one or more voltage supplies applied to the respective half-bit test structures; wherein the left and right half-bits of the first test structure are configured for measuring respective left and right standby SNM values at an output node using supply voltages applied to the first test structure during on-chip assessment of the static noise margin of the memory cell; and wherein the left and right half-bits of the second test structure are configured for measuring respective left and right cell ratio values at an output node using supply voltages applied to the second test structure during on-chip assessment of the static noise margin of the memory cell of the device.