Patent ID: RE40311

Claim:
An electrically erasable and programmable zero-power memory cell comprising: a first variable voltage generator; a second variable voltage generator; a P-channel sense transistor having a source coupled to said first variable voltage generator; an N-channel sense transistor having a source coupled to said second variable voltage generator; wherein a drain of said P-channel sense transistor is coupled to a drain of said N-channel sense transistor to form an output of the memory cell; and wherein a gate of said P-channel sense transistor is coupled to a gate of said N-channel sense transistor to form a floating gate of the memory cell; a write transistor having a source coupled to a WBL (write bit line) and having a gate coupled to a WL (write line); a tunneling capacitor coupled between said floating gate of the memory cell and a drain of said write transistor; and a coupling capacitor coupled between a CG (control gate) node and said floating gate of the memory cell; wherein said CG (control gate) node is biased with a positive voltage during an erase operation and wherein said WBL (write bit line) and said WL (write line) are biased to turn on said write transistor such that a negative voltage forms on said floating gate of the memory cell by charge tunneling through said tunneling capacitor to turn on said P-channel sense transistor for forming a logical high state at said output of said memory cell during said erase operation; and wherein said CG (control gate) node is biased with a ground or negative voltage during a program operation and wherein said WBL (write bit line) and said WL (write line) are biased to turn on said write transistor such that a positive voltage forms on said floating gate of the memory cell by charge tunneling through said tunneling capacitor to turn on said N-channel sense transistor for forming a logical low state at said output of said memory cell during said program operation; and wherein each of said first and second variable voltage generators applies a positive voltage at said respective source of each of said P-channel and N-channel sense transistors during said erase operation.