Patent ID: 6927131

Claim:
A method of forming a nonvolatile memory device, comprising: forming a first oxide layer on a substrate; forming a nitride layer on the first oxide layer; forming a second oxide layer on the nitride layer; patterning the second oxide layer so as to expose the nitride layer; forming a first polysilicon layer on the second oxide layer and the exposed portion of the nitride layer; etching the first polysilicon layer and the nitride layer so as to expose the second oxide layer and the first oxide layer and to form polysilicon spacers on the nitride layer; etching the polysilicon spacers so as to expose portions of the nitride layer, the exposed portions of the nitride layer comprising charge trapping layers; etching the exposed portion of the first oxide layer to expose a portion of the substrate; forming a third oxide layer on the exposed portion of the substrate, the exposed portions of the nitride layer, and the second oxide layer; forming a second polysilicon layer on the third oxide layer; and planarizing the second polysilicon layer so as to expose the second oxide layer, the second polysilicon layer comprising a gate electrode that overlaps portions of the charge trapping layers, the third oxide layer comprising a gate insulating layer.