Patent ID: 8461892

Claim:
An interpolation circuit, comprising a bias generating module, a load module, a first clock control module connected with said bias generating module and said load module, a second clock control module connected with said bias generating module and said load module, and an output module, wherein said load module comprises a current source sub-module and a load resistance sub-module, said first clock control module comprises a first input sub-module, a first source terminal negative feedback sub-module, a first multiplex switch sub-module and a first multiplex current sink sub-module, said second clock control module and said first clock control module are symmetrical in structure, said bias generating module comprises a first field effect transistor (FET), a second FET connected with said first FET, a third FET connected with said second FET, and a bias current terminal connected with said first FET, said current source sub-module comprises a fourth FET, and a fifth FET connected with said fourth FET, said load resistance sub-module comprises a first resistor connected with said fourth FET, and a second resistor connected with said fifth FET, said first input sub-circuit comprises a sixth FET, and a seventh FET connected with said sixth FET, said first source terminal negative feedback sub-module comprises a third resistor connected between said sixth FET and said seventh FET, and a first capacitor connected in parallel with said third resistor, said first multiplex switch sub-module comprises a first group of switches, and a second group of switches connected in parallel with said first group of switches, and said first multiplex current sink sub-module comprises a first group of FETs connected with said first group of switches, and a second group of FETs connected with said second group of switches.