Patent ID: 7153747

Claim:
A process for producing a transistor of MOS type, comprising the following stages: a) providing a substrate comprising a thin layer of silicon ( 26 ), integral with an insulating support ( 14 ), and covered with a superficial layer ( 28 ) of a semi-conductor material, wherein said providing a substrate further includes, forming, on a first substrate, the superficial layer ( 28 ) made of a material having a unit cell parameter close to silicon, forming, by epitaxy, a thin layer of silicon ( 26 ) on the superficial layer, and transferring the thin silicon layer and at least one part of the superficial layer on the insulating support ( 14 ), by making the thin layer of silicon ( 26 ) integral with said insulating support ( 14 ), b) local etching of the superficial layer ( 28 ) to expose the silicon layer in at least one channel region, c) formation of an insulated gate ( 50 ) above the silicon layer ( 26 ) in the channel region, and formation of a source and a drain ( 42 , 44 ) on either side of the channel region, the source and drain extending in the layer of silicon and in the superficial layer.