Patent ID: 7927994

Claim:
A process of fabricating an array of non-volatile memory cells comprising: forming a plurality of first region and second region spaced apart therefrom of a second conductivity type in a substrate of a first conductivity type; forming stacked pairs of control gates and floating gates above the substrate on opposite sides of the first region, with each stacked pair having a control gate position above a floating gate, positioned above the substrate, with each of the floating gate and control gate having a length measured in a direction from the first region to the second region, and with the control gate having a length less than the length of the floating gate with each floating gate closest to the first region having an exposed portion not covered above by the control gate, and having a tip, with a tunneling barrier covering said tip; forming an erase gate above the first region on the substrate between a stacked pair of control gate and floating gate, with said erase gate having two portions: a first portion between the exposed portions of the floating gates and insulated therefrom, and having a first end closest to the floating gate; and a second portion electrically connected to the first portion, said second portion above the exposed portion of the floating gate and insulated therefrom by said tunneling barrier, shielding the tunneling barrier from the control gate, wherein said second portion of the erase gate separated from the floating gate by a first length measured in a direction substantially perpendicular to the length direction; said second portion having a first end closest to the control gate, said second portion of the erase gate having a second length measured from the first end of the second portion of the erase gate to a vertical line aligned with the first end of the first portion of the erase gate in a direction substantially parallel to the length direction; wherein said ratio of the second length to the first length is between approximately 1.0 and 2.5; forming select gates above the substrate and between the stacked pair of control gate and floating gate and the second region.