Patent ID: 8797196

Claim:
A pipeline analog-to-digital converter comprising: a plurality of calibrated stages, each of the plurality of calibrated stages comprising: an amplifier generating an output representing an amplified difference between a first voltage at an input of the amplifier and a second voltage at another input of the amplifier, and a dither capacitor having a first terminal coupled to the input of the amplifier and a second terminal coupled to: a first reference voltage responsive to a voltage received by the calibrated stage being within a first range, a second reference voltage lower than the first reference voltage responsive to the received voltage being within a second range, and the first reference voltage or the second reference voltage depending on a bit value of a Pseudo-Random Binary Sequence (PRBS) responsive to the received voltage being within a third range; and a correction circuit coupled to the plurality of calibrated stages and configured to: adjust a calibration coefficient of a calibrated stage responsive to the second terminal of the dither capacitor included in the calibrated stage being coupled to the first reference voltage or the second reference voltage dependent on the bit value and remnants of the PRBS remaining after attempting to subtract the PRBS from bits generated by one or more stages and a flash analog-to-digital converter included in the pipeline analog-to-digital converter, and compensate for a gain error of the calibrated stage based on the adjusted calibration coefficient.