Patent ID: 6961273

Claim:
A random access memory circuit, comprising: a plurality (k) of banks, each bank having a multiplicity of memory cells and a selection device configured to simultaneously select one or more groups of n memory cells of the respective bank, depending on a cell address information item applied, for one of a write operation and a read operation; a bidirectional data port having n transfer channels for receiving and transmitting n data bits in parallel, the bidirectional data port selectably connected to a plurality of bank buses which are connected respectively to the plurality of banks; and a test auxiliary device comprising: a bus parallel switching device for simultaneously connecting the plurality of bank buses to the data port; a selection parallel switching device for simultaneously activating the selection devices of the plurality of banks; a test control circuit, in response to a test mode setting signal, for activating the bus parallel switching device only during the write operation, decoupling the plurality of bank buses from the data port during the read operation and activating the selection parallel switching device during the write operation and during the read operation; and for each bank, a dedicated evaluation device for comparing n read data of the currently selected group of n memory cells of the respective bank and providing a result information item comprising m bits where 1≦m≦n/k, wherein each result information item indicates whether an assigned subset from m subsets of the n read data corresponds to a part of the reference information item which is assigned to the respective subset, wherein each evaluation device comprises m comparators.