Patent ID: 8089808

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array of a plurality of memory cells arranged in a matrix, each memory cell including a selecting transistor and a memory cell transistor connected to the selecting transistor; a bit line commonly connecting drains of a plurality of said selecting transistors arranged in two adjacent columns; a first word line commonly connecting control gates of a plurality of said selecting transistors arranged in a row; a second word line commonly connecting select gates of a plurality of said selecting transistors arranged in a row; a source line commonly connecting sources of a plurality of said memory cell transistors arranged in two adjacent columns; a first column decoder connected to a plurality of said bit lines and a plurality of said source lines and controlling potentials of said plurality of bit lines and said plurality of source lines; a first row decoder connected to a plurality of said first word lines and controlling potentials of said plurality of first word lines; a second row decoder connected to a plurality of said second word lines and controlling potentials of said plurality of second word lines; and a second column decoder connected to a plurality of said source lines and controlling potentials of said plurality of source lines, the first column decoder being formed of a circuit whose withstand voltage is lower than a withstand voltage of a circuit within the first row decoder and the second column decoder, and the second row decoder being formed of a circuit whose withstand voltage is lower than a withstand voltage of a circuit within the first row decoder and the second column decoder.