Patent ID: 7064999

Claim:
A digital memory circuit, comprising: at least two pairs of adjacent banks having in each case a multiplicity of memory cells in each of said banks, said memory cells forming a matrix-type configuration of rows and columns and receiving and addressed by bank address signals, row address signals and column address signals; only two bundles of in each case n/2 read/write data lines connected to each pair of said adjacent banks, said two bundles of n/2 read/write data lines including a first bundle connected to a first half of a first bank and to a second half of a second bank and a second bundle connected to a second half of said first bank and to a first half of said second bank, said bundles of said n/2 read/write data lines coupled to said columns of different halves of a bank in order to be able to write in or read out at each bank half simultaneously n/2 data bits at n/2 simultaneously addressed columns; a bundle of n/2 input/output lines for inputting and outputting n/2 data bits in parallel form; a control device receiving and responding to the bank address signals, the row address signals, the column address signals and a clock signal for producing data transfer paths between simultaneously addressed memory cells and assigned ones of said n/2 read/write data lines during a respective period of the clock signal; and a changeover device controlled in a manner dependent on the clock signal to connect said n/2 input/output lines to said n/2 read/write data lines coupled to said first half of an addressed bank during a first half-period of the clock signal and to said n/2 read/write data lines coupled to said second half of said addressed bank during a subsequent second half-period of the clock signal, said changeover device being changed over between different switching states to connect said n/2 input/output lines either to said first bundle or to said second bundle of n/2 said read/write data lines of at least a bank pair containing said addressed bank.