Patent ID: 8285941

Claim:
A system for enhancing timeliness of cache memory prefetching in a processing system, the system comprising: a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses, the stride size is less than a cache line size; a confidence counter; prefetching selection logic; a separate eager prefetching control logic hardware in communication with the prefetching selection logic; a standard stride prefetching control logic hardware in communication with the prefeteching selection logic, the system performing: adjusting the confidence counter based on the stride pattern detector detecting the stride pattern; comparing the confidence counter to a confidence threshold; and requesting, using the separate eager prefetching control logic, a cache prefetch of a cache line x and cache line x+1 based on the confidence counter reaching the confidence threshold; performing the cache prefetch of the cache line x using the standard stride prefetching logic hardware, based on each of 1) the confidence counter reaching the confidence threshold, and 2) determining that a ratio of stride length to cache line size is less than a predefined stride ratio threshold and a demand access location is not within a predefined length from a transition to another cache line; and performing the cache prefetch of the cache line x and cache line x+1 using the separate eager prefetching control logic hardware based on each of 3) the confidence counter reaching the confidence threshold, and 4) determining that a ratio of stride length to cache line size meets or exceeds the predefined stride ratio threshold.