Patent ID: 7518698

Claim:
A thin film transistor array substrate, comprising: a gate pattern having a gate electrode, a gate line connected to the gate electrode, and a gate pad connected to the gate line; a source/drain pattern having a source electrode, a drain electrode, a data line connected to the source electrode, and a data pad connected to the data line; a gate insulating pattern formed along a matrix pattern including the gate pattern and the source/drain pattern except for a pixel area; a semiconductor pattern formed on the gate insulating pattern and partially removed to expose the gate insulating pattern at a remaining area except for an area where a channel of a thin film transistor and the source/drain pattern are formed; and a transparent electrode pattern having a pixel electrode formed at the pixel area and connected to the drain electrode, a gate pad protective electrode directly connected to the whole surface of the gate pad on the gate pad, and a data pad protective electrode directly connected to the whole surface of the data pad on the data pad, wherein the gate insulating pattern, the semiconductor pattern and the source/drain pattern have continuous edges.