Patent ID: 8134232

Claim:
A packaged integrated circuit, having: an integrated circuit disposed on a package substrate, an encapsulant disposed around the integrated circuit, the encapsulant having a first thermal transfer rate, a heat sink disposed at least partially within the encapsulant and having at least a portion of one surface of the heat sink exposed outside of the encapsulant, the heat sink having a second thermal transfer rate, the integrated circuit having an uppermost passivation layer that does not extend off of the integrated circuit, where the passivation layer is not electrically conductive and has a third thermal transfer rate, the passivation layer having a port disposed therein, the port extending completely through the passivation layer to expose an underlying layer through the passivation layer, and a thermal pathway disposed at least partially within the port, the thermal pathway making thermal contact to both the underlying layer and the heat sink, the thermal pathway having a fourth thermal transfer rate, where the fourth thermal transfer rate is greater than either of the first thermal transfer rate and the third thermal transfer rate.