Patent ID: 7211498

Claim:
A method of manufacturing isolation layers having different depths in a flash memory including a cell region and a peripheral circuit region, the method comprising: forming a first mask material layer on a semiconductor substrate in order to mask only the cell region; forming a second mask material layer on an entire surface of the substrate at the cell region whereon the first mask material layer is formed and the peripheral circuit region whereon the first mask material layer is not formed; simultaneously forming a trench having a first depth in the cell region and a trench having a second depth in the peripheral circuit region by etching the second mask material layer and the substrate in the cell region and the peripheral circuit region, the second depth being greater than the first depth; filling an insulation layer into the entire surface of the substrate including trenches; planarizing the insulation material layer and the second mask material layer to a degree that the first mask material layer is exposed; and respectively forming a shallow trench isolation (STI) layer in both the cell region and the peripheral circuit region by removing the first and second mask material layers, wherein the second mask material layer is formed to have a height difference between the cell region and the peripheral circuit region.