Patent ID: 8159898

Claim:
A semiconductor memory device comprising: first and second bank groups with a plurality of memory banks; and a peripheral circuit region disposed between the first bank group and the second bank group to transfer signal between the first and second bank groups and a pad, wherein the peripheral circuit region separates the first bank group and the second bank group, wherein each of the first and second bank groups includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region corresponding to the first memory bank; a second row control circuit region corresponding to a second memory bank; a second column control circuit region corresponding to a second memory bank and disposed adjacent to the first column control circuit region; a third row control circuit region corresponding to a third memory bank and disposed adjacent to the first row control circuit region; a third column control circuit region corresponding to the third memory bank; a fourth row control circuit region corresponding to a fourth memory bank and disposed adjacent to the second row control circuit region; and a fourth column control circuit region corresponding to the fourth memory bank and disposed adjacent to the third column control circuit region, wherein two adjacent column control circuit regions are arranged in parallel without a peripheral circuit region therebetween, wherein two adjacent row control circuit regions are arranged in parallel without the peripheral circuit region therebetween.