Patent ID: 7236594

Claim:
A pseudo random generator comprising a shift register comprising: first flip flop (F 0 ); further flip-flops (F 1 . . . Fn); each flip-flop (Fx) having a D input, a non-inverting output, an inverting output, and a common clock (f clk ) input; and the first flip-flop (F 0 ) having a set input, each of the non-inverting outputs being connected via a NOR gate ( 10 ) to the set input of the first flip-flop (F 0 ) and each of the non-inverting outputs of the flip-flops (F 0 . . . Fn) being connected to the input of the first flip-flop (F 0 ) via an XOR gate ( 11 ), further comprising at least one additional logic gate ( 13 , 14 , 15 ; 17 , 18 , 19 ) connected to at least one additional non-serial flip-flop ( 14 ; 18 ); wherein the at least one additional logic gate ( 13 , 14 , 15 ; 17 , 18 , 19 ) includes gates connected to the outputs of the flip-flops (F 0 . . . Fn) to toggle between the inverting and the non-inverting outputs of the nth flip-flop; and wherein the at least one additional logic gate ( 13 , 14 , 15 ; 17 , 18 , 19 ) further includes an AND gate ( 13 ) with one input connected to the common clock (f clk ) and another input connected to the output of the NOR gate ( 12 ) and an output of the AND gate ( 13 ) being connected to a clock input of the at least one additional non-serial flip-flop ( 14 ) which has its inverting output connected to its D input and its non-inverting output connected to one input of an XOR gate ( 15 ).