Patent ID: 7521759

Claim:
A semiconductor structure comprising: (1) a semiconductor substrate having a channel region, and a first integrated impurity diffusion region including a first electric field reduction region that is formed adjacent to said channel region, said semiconductor substrate including a plurality of further impurity diffusion regions that are separated from each other; (2) a first insulating film formed on said semiconductor substrate; (3) a first electrode structure having: (i) a first region formed above said channel region; and (ii) a second region that is formed adjacent to said first region and above said first electric field reduction region to be self-aligned with said first electric field reduction region, said second region comprising: (a) one or more openings formed above said plurality of further impurity diffusion regions and comprised of a one-dimensional array of a plurality of slits that are separated from each other and longitudinally formed in a first direction parallel to the plane of said semiconductor substrate, said one-dimensional array being comprised of a one-line array formed along a second direction that is parallel to said plane of said semiconductor substrate and different from said first direction; and (b) a first opening surrounding portion that surrounds said one or more openings, and which comprises a plurality of stripe shape portions longitudinally formed in said first direction and a discrete portion separated from said first region and said one or more stripe shape portions, and formed in a more distant position from said first region in comparison to the place in which said one or more stripe shape portions are formed, at least one of said plurality of stripe shape portions being electrically connected to said first region; (4) a second insulating film formed on said first electrode structure and said first insulating film; and (5) a first wiring layer that is formed on said second insulating film and above said discrete portion.