Patent ID: 8836686

Claim:
A display device comprising: a plurality of pixels; first to m-th scan lines (m is a natural number) electrically connected to n pixels in respective first to m-th rows, among the plurality of pixels; and first to m-th pulse output circuits electrically connected to the respective first to m-th scan lines, wherein the k-th pulse output circuit (k is a natural number greater than or equal to 2 and less than m) includes: a first transistor having one of a source and a drain electrically connected to a first wiring for supplying a clock signal, and the other of the source and the drain electrically connected to the (k+1)th pulse output circuit, a second transistor having one of a source and a drain electrically connected to a second wiring for supplying the clock signal or a first fixed potential, and the other of the source and the drain electrically connected to the k-th scan line, and a control circuit configured to control a potential of a gate of the first transistor and a potential of a gate of the second transistor in accordance with a signal input from the (k−1)th pulse output circuit, wherein the control circuit includes a third transistor having one of a source and a drain electrically connected to the gate of the first transistor, and the other of the source and the drain electrically connected to the gate of the second transistor.