Patent ID: 7107489

Claim:
A data processing system, comprising: a central processing unit coupled to a bus for receiving instructions including a first debug instruction; and a debug circuit, comprising: registers for being loaded with set-up data, wherein the set-up data comprises breakpoint addresses and counter preload values; trigger circuitry coupled to the registers and the central processing unit, counter circuitry coupled to the registers and the central processing unit, and combining logic coupled to the registers and to the trigger circuitry; wherein the counter circuitry is configurable to either count triggers from breakpoint matches or count clock periods; wherein the central processing unit is characterized as providing a debug communication signal in response to the first debug instruction to at least one of the trigger circuitry, the counter circuitry, and the combining logic; and wherein the combining logic is for using information from the registers to direct the combining of information from the debug communication signal, the trigger circuitry, and the counter circuitry to generate valid triggers.