Patent ID: 7385256

Claim:
An integrated circuit including a field effect transistor structure comprising: an active area formed by a section of a monocrystalline semiconductor substrate, the active area comprising a channel region between a source region and a drain region; wherein, in a conducting state of the field effect transistor structure, a drain current flows essentially in a direction of a channel axis and parallel to a structure surface of the semiconductor substrate; a first and second insulator structures each positioned adjacent the active area along interfaces between the active area and the respective insulator structure on opposite sides of the active area; and a third and fourth insulator structures positioned adjacent the active area on opposite sides of the active area, the third and fourth insulator structures delimiting the active area transversally relative to the first and second insulator structures; wherein each of the first and second insulator structures includes a base section substantially free from compressive stress and comprising at least one dielectric material, wherein at least one of the first and second insulator structures includes a buffer layer formed between the base section and the active area, the buffer layer exerting a compressive stress on the active area; and wherein each of the third and fourth insulator structures includes a base section substantially free from compressive stress and comprising at least one dielectric material, and is mechanically unstressed or is configured to exert a tensile stress on the active area.