Patent ID: 8483281

Claim:
A system comprising: memory configured to store an order-N transform T; and one or more hardware processors communicatively coupled with the memory, the one or more hardware processors configured to receive a video signal, execute a retrieving unit configured to retrieve from the memory the order-N transform T, where N is an integer, execute a generating unit configured to generate the order-2N transform W from the retrieved order-N transform T by rules of w u,2i =(1/√2) t u,i and w u,2i+1 =(1/√2) t u,i for i= 0,1 , . . . ,N− 1;and 1) w u + 8 , j = ( - 1 ) Int ⁡ ( j + 1 2 ) 2 ⁢ t u + 8 , Int ⁡ ( j / 2 ) ⁢ ⁢ for ⁢ ⁢ j = 0 , 1 , … ⁢ , 2 ⁢ N - 1 2 ) where t u,i is the (u, i)th element of the transform T, Int ⁡ ( j + 1 2 ) represents the integral part of j + 1 2 , and u=0, 1, . . . , N−1; and w u,2i and w u,2i+1 are elements of a first N rows of the transform W, and w u+8,j is elements of a last N rows of the transform W, process the received video signal using the generated order-2N transform W, and output the processed video signal.