Patent ID: 8476740

Claim:
A semiconductor wafer surface protection sheet comprising: a base layer having a tensile elasticity at 25° C., E(25), of 1 GPa or more; a resin layer A that satisfies the condition E A (60)/E A (25)<0.1, where E A (25) is a tensile elasticity at 25° C. and E A (60) is a tensile elasticity at 60° C., the E A (60) ranging from 0.005 MPa to 1 MPa; and a resin layer B having a tensile elasticity at 60° C., E B (60), of 1 MPa or more and having a thickness of 0.1 μm to less than 100 μm, the E B (60) being larger than the E A (60) of the resin layer A, wherein the resin layer A is disposed between the base layer and the resin layer B.