Patent ID: 7863138

Claim:
A method of fabricating a microelectronic device, the method comprising: forming a coupling layer on a semiconductor substrate, the coupling layer comprising a different material than the substrate; forming a mask pattern having a trench extending therethrough on the coupling layer to expose a surface of the coupling layer, wherein opposing sidewalls of the trench in the mask pattern and the exposed surface of the coupling layer therebetween form a groove structure defining a nano line arrangement region having a predetermined width and a predetermined length greater than the width; forming a linking layer in the trench on the surface of the coupling layer, wherein the linking layer comprises a different material than the coupling layer and is configured to couple at least one nano line to the surface of the coupling layer; and forming the at least one nano line on the linking layer in the nano line arrangement region extending substantially along the length thereof, wherein the at least one nano line is coupled to the surface of the coupling layer in the groove structure by the linking layer to define a nano line structure.