Patent ID: 7552273

Claim:
A memory circuit, comprising: a plurality of memory areas, the order of which depends on respectively associated logical addresses, and which each has an associated control value; a container containing information indicating which memory areas are used; and a controller, designed to perform the following steps during writing into a target memory area of the plurality of memory areas: assigning a value corresponding to the control value associated with the lowest used memory area to the control value associated with the target memory area, when a used memory area exists, and assigning an arbitrary or predetermined value when no used memory area exists; and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewriting a content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changing the control value of the next memory area, when such a next memory area exists, and rewriting the content of the lowest memory area and changing the control value associated with the same, when the next memory area, whose control value has the predetermined relation to the control value of the lowest area, does not exist.