Patent ID: 8798386

Claim:
A method for processing images, the method comprising: in a chip comprising an image sensor pipeline (ISP), said ISP comprising one or more control logic circuits and one or more image processing modules, wherein said ISP, said one or more control logic circuits, and said one or more image processing modules are integrated on a single substrate of said chip: communicating, to said one or more processing modules via said one or more control logic circuits, corresponding configuration parameters that are associated with each one of a plurality of data tiles comprising an image, as each data tile progresses through said ISP; and processing said each one of said plurality of data tiles by said one or more image processing modules concurrently, wherein each image processing module of said one or more image processing modules performs a different function, and wherein said each image processing module processes said each one of said plurality of data tiles by utilizing said corresponding configuration parameters associated with said each one of said plurality of data tiles.