Patent ID: 8541261

Claim:
A method of manufacturing a semiconductor device comprising the steps of: (a) providing a first wiring substrate including a first upper surface, a plurality of first bonding leads formed on the first upper surface, a plurality of first lands formed on the first upper surface and arranged closer to a peripheral portion of the first upper surface than the first bonding leads, a first lower surface opposite the first upper surface, and a plurality of second lands formed on the first lower surface, the first lands being electrically connected with the first bonding leads, respectively; (b) disposing a plurality of electrodes over the first lands of the first wiring substrate, respectively, and mounting a first semiconductor chip over the first upper surface of the first wiring substrate, each of the electrodes being comprised of a solder material, the first semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a back surface opposite the main surface; (c) electrically connecting the pads of the first semiconductor chip with the first bonding leads of the first wiring substrate via a plurality of conductive members, respectively; (d) sealing the first semiconductor chip and the electrodes with resin forming a sealing body; (e) after the step (d), removing a portion of the sealing body such that a part of each of the electrodes is exposed from an upper surface of the sealing body; (f) after the step (e), performing a heat treatment without stacking another member on the electrodes such that the part of each of the electrodes is caused to protrude from the upper surface of the sealing body; and (g) after the step (f), stacking a second wiring substrate over the upper surface of the sealing body and electrically connecting a plurality of third lands of the second wiring substrate with the first lands of the first wiring substrate via the electrodes, respectively, wherein the second wiring substrate includes a second main surface, a plurality of fourth lands formed on the second main surface, a second back surface opposite the second main surface, and the third lands formed on the second back surface, and the third lands are electrically connected with the fourth lands, respectively.