Patent ID: 7279887

Claim:
A method of testing integrated circuits during an assembly process, said method comprising: accessing a first integrated circuit from inventory; accessing a second integrated circuit from inventory; coupling said first integrated circuit to a socket on a first circuit board for first system-level testing, wherein said first circuit board is selected according to a first type of product and application; coupling said second integrated circuit to a socket on a second circuit board for second system-level testing, wherein said second circuit board is selected according to a second type of product and application that is different from said first type; performing said first system-level testing of said first integrated circuit coupled to said first circuit board prior to placement and permanent attachment of said first integrated circuit onto a third circuit board that is configured according to said first type of product and application, wherein said first system-level testing is specific to said first type of product and application; and performing said second system-level testing of said second integrated circuit coupled to said second circuit board prior to placement and permanent attachment of said second integrated circuit onto a fourth circuit board that is configured according to said second type of product and application, wherein said second system-level testing is specific to said second type of product and application.