Patent ID: 7809009

Claim:
An apparatus for switching packets, each packet having a header portion and a corresponding tail portion, the apparatus comprising: a plurality of packet header buffers (PHBs); and a plurality of header processing pipelines, wherein each of the plurality of header processing pipelines comprises a plurality of pipeline stage circuits connected in a sequence, wherein the plurality of pipeline stage circuits comprises at least a fetch stage circuit and a gather stage circuit, each stage circuit of the plurality of pipeline stage circuits is configured to pass data to a next circuit, the fetch stage circuit is configured to receive the header portion and store the header portion in one of the plurality of PHBs, and the gather stage circuit is configured to output a modified header portion, a pipeline stage circuit of the plurality of pipeline stage circuits is configured to copy data from a first PHB of the plurality of PHBs to a second PHB of the plurality of PHBs, each of a first plurality of the plurality of pipeline stage circuits are configured to access the first PHB, and the plurality of header processing pipelines are configured to concurrently process header portions in each header processing pipeline.