Patent ID: 8305825

Claim:
A timing control circuit for controlling a signal timing in an associated circuit, the timing control circuit comprising: a first circuit node; a second circuit node; a control input for receiving a control value; and at least three current control units coupled in parallel between said first circuit node and said second circuit node, said current control units being responsive to a timing trigger event to pass a current, said signal timing of said associated circuit being dependent on a magnitude of said current; wherein: said current control units each have an active mode and an inactive mode, said magnitude of said current being dependent on how many of said current control units are in said active mode at the time of said timing trigger event; said current control units comprise a plurality of groups of current control units, at least two of said groups having different numbers of current control units, at least one of said groups comprising more than one current control unit; said control value comprises a plurality of bits corresponding to said plurality of groups of current control units; and current control units within a same group are responsive to a change in a bit of said control value corresponding to that group to switch together between said active mode and said inactive mode, such that said magnitude of said current is dependent on which of said groups of current control units are in said active mode at the time of said timing trigger event.