Patent ID: 7501669

Claim:
A transistor, comprising: a plurality of active semiconductor layers on a substrate; a source contact in electrical contact with said plurality of active layers; a drain contact also in electrical contact with said plurality of active layers with space between said source and drain contacts on the topmost of said plurality of active layers; a gate in electrical contact with said topmost of said plurality of active layers, between said source and drain contacts; a spacer layer on and covering substantially all of the surface of the topmost of said plurality of active layers, between said gate and said source and drain contacts, wherein said gate is not covered by said spacer layer and wherein said spacer layer comprises a plurality of spacer layers in a step arrangement between said gate and said drain contact; and a field plate on said spacer layer integrated with said gate, wherein said field plate is on said spacer layer step arrangement, said field plate comprising a plurality of field plate portions, each of which has a different distance between it and the topmost of said plurality of active layers.