Patent ID: 8127118

Claim:
A system for collecting performance data in a processor, the system comprising: a plurality of trace arrays and trace muxes; a trace read control unit in communication with the plurality of trace arrays and trace muxes via a read control bus; and a trace collect unit, the system configured to perform a method comprising: sending trace read bits and an address to the plurality of trace arrays and trace muxes, the sending from the trace read control unit and each trace read bit associated with one of the plurality of trace arrays and trace muxes; receiving a trace read bit and the address at each of the trace arrays and trace muxes; forwarding, at each of the trace arrays and trace muxes, trace data stored at the address and the received trace read bit to the trace collect unit that is in indirect communication with the trace read control unit; reading, at the trace collect unit, the trace data received from a trace array and trace muxes, the reading responsive to contents of the trace read bit associated with the trace array and trace muxes; and one of incrementing and decrementing the address and repeating the sending, receiving, forwarding, and reading until the trace data is collected.