Patent ID: 8508987

Claim:
A semiconductor device comprising: a memory cell array having a plurality of normal magnetic memory cells disposed in rows and columns, and a plurality of reference cells aligned with said normal magnetic memory cells in a direction of one of a row of the normal magnetic memory cells and a column of the normal magnetic memory cells for generating a reference current in reading data from the normal magnetic memory cell; and a plurality of first writing magnetic field supply lines arranged corresponding to one of said rows and said columns of the normal magnetic memory cells, and inducing and applying, in data writing, a data writing magnetic field by a current to corresponding ones of the normal magnetic memory cells and the reference cells, each said first writing magnetic field supply line having a clad interconnect structure for said normal magnetic memory cells other than the reference cell of one of a corresponding one of the row and the column and a partially clad or unclad interconnect structure for the reference cell of said corresponding one, said clad interconnect structure being a structure in which a conductor is covered with a high permeability film except a surface of said conductor facing corresponding normal cells, said partially clad or unclad interconnect structure being a structure in which a surface of said conductor facing corresponding reference cell and at least one additional surface of said conductor are non-covered with said high permeability film.