Patent ID: 7325152

Claim:
A synchronous signal generator comprising: a first and second clocked counting and delay circuit; wherein each of the first and second clock counting and delay circuits are configured for generating and outputting a first and second load signal, and a FIFO read clock signal, each synchronous and in phase with a periodic basic clock signal input into it, at an adjustable and basic clock pulse-synchronous time point after a reset signal that is synchronized with the basic clock signal; wherein the first counting and delay circuit counts, based on the basic clock pulse, in an edge-triggered fashion a number of clock pulse periods of the basic clock signal from the time point of reception of the synchronized reset signal, generates an initial load signal upon reaching a counting value, and outputs the initial load signal delayed by half a period of the basic clock signal as the first load signal and delayed by a full period of the basic clock signal as the second load signal; and wherein the second counting and delay circuit delays, based on the basic clock signal, in an edge-triggered fashion the FIFO read clock signal by an integral multiple of half of the clock period of the basic clock signal from the time of reception of the synchronized reset signal and outputs it phase-locked to the first and second load signal.