Patent ID: 8598032

Claim:
A method, for use with a three-dimensional stacked IC device having a stack of contact levels at an interconnect region, for creating interconnect contact regions aligned with and exposing landing areas at the contact levels, the method comprising: using a set of N etch masks for creating up to and including 2 N levels of interconnect contact regions at the stack of the contact levels, each mask comprising mask and etch regions, N being an integer equal to at least 2, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N; removing at least a portion of any upper layer overlying the stack of the contact levels at the interconnect region; etching the interconnect region N times using said masks in a chosen order to create contact openings extending from a surface layer to each contact level, the contact openings being aligned with and providing access to the landing areas at each of the 2 N contact levels; and the etching step comprising etching through 2 x−1 contact levels for each mask of sequence number x; whereby electrical conductors can be formed through the contact openings to contact the landing areas at the contact levels.