Patent ID: 7645634

Claim:
A method for making a stacked package module, comprising providing a first chip scale package including at least one first package die affixed to and electrically interconnected with a die attach side of a first package substrate, the first CSP being molded and without solder balls; providing a singulated second package including at least one second package die affixed to and electrically interconnected with a die attach side of a second package substrate, the second package being molded and without solder balls; affixing the second package onto a land side of the first package substrate, employing an adhesive between a surface of a molding of the second package and the land side of the first package substrate; forming wire bond interconnections between the land side of the second package substrate and sites in a marginal area of the land side of the first package substrate; and performing an operation to enclose the marginal areas of the land side of the first substrate, the z-interconnection wire bonds and wire loops, the edges of the second package, and the marginal area on the land side of the second package, leaving exposed an area of the land side of the second substrate located within a marginal area.