Patent ID: 8805916

Claim:
A digital signal processing (“DSP”) circuit block comprising: first and second N-bit multiplier circuits; first shifter circuitry for shifting outputs of the first multiplier circuit by a selectable one of (1) zero bit positions and (2) N bit positions toward greater arithmetic significance; first compressor circuitry for additively combining outputs of the first shifter circuitry and the second multiplier circuit; circuitry for selectively routing outputs of the first compressor circuitry to first and second other DSP circuit blocks that are on respective opposite sides of the DSP circuit block; second shifter circuitry for shifting outputs of the first compressor circuitry by a selectable one of (1) zero bit positions, (2) N bit positions toward greater arithmetic significance, and (3) N bit positions toward lesser arithmetic significance; and second compressor circuitry for additively combining outputs of the second shifter circuitry and any outputs received from the first compressor circuitry in either of the first and second other DSP circuit blocks.