Patent ID: 7937256

Claim:
A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit, comprising: (a) determining a plurality of vectors for a plurality of arcs, each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate; (b) selecting a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs; (c) performing circuit pruning for each of the plurality of substantially distinct vectors taking each one substantially distinct vector at a time, the circuit pruning includes identifying an active circuit for each vector, the active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors; (d) performing circuit simulations limited to a plurality of transistors in the active circuit; (e) repeating (c) and (d) for remaining ones of the plurality of substantially distinct vectors; and (f) storing results of the circuit simulations on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors, wherein a sensitivity analysis further includes performing a response surface method (RSM), the RSM including: identifying a plurality of transistors in the active circuit that exhibit a linear and small electrical influence of a process parameter variation, the electrical influence being measured by applying the process parameter variation to the circuit and analyzing a change in the electrical influence of each of the plurality of transistors, the small and linear electrical influence is characterized by a substantially linear change in the electrical influence and a magnitude of the electrical influence below a selectable threshold; and modeling a surface response for each of the plurality of transistors using a sparse table and a interpolation process to reduce a number of circuit simulations, the sparse table includes a subset of values of an RSM simulation table of delays, the RSM simulation table of delays includes a plurality of input slew and output load values.