Patent ID: 7814448

Claim:
A method, performed on a computer system, for parameterized statistical static timing analysis of a digital circuit, the method comprising: using the computer system to perform the following: developing a variational waveform model that approximates all possible waveforms that may occur at nodes of the digital circuit for all possible combinations of values of process and environmental parameters used to represent sources of variation that may effect the digital circuit, wherein the variational waveform model is a random function that models the process and environmental parameters as random variables, wherein all of the possible waveforms are constructed from a nominal waveform containing nominal values of the process and environmental parameters, the nominal waveform having a shape that can change to any of the all possible waveforms as a function of the process and environmental parameters, the change in shape of the nominal waveform to any of the all possible waveforms is facilitated by a plurality of waveform transformation operators parameterized by the process and environmental parameters, wherein the nominal waveform and the parameterized plurality of waveform transformation operators describe all of the possible waveforms that may occur at the nodes of the digital circuit for all of the possible combinations of values of the process and environmental parameters propagating the variational waveform model comprising the nominal waveform and the parameterized plurality of waveform transformation operators that describe all of the possible waveforms that may occur at the nodes of the digital circuit for all of the possible combinations of values of the process and environmental parameters through a timing arc from at least one input to at least one output of the digital circuit; and determining circuit timing characteristics as the variational waveform model comprising the nominal waveform and the parameterized plurality of waveform transformation operators is propagated through the timing arc from at least one input to at least one output of the digital circuit, wherein the determined circuit timing characteristics are based on statistical properties of variations of the process and environmental parameters that may effect the digital circuit.