Patent ID: 7061051

Claim:
A semiconductor device electrostatic discharge protection structure on a substrate comprising: a first doped region of opposite dopant than said substrate extending down from the surface of said substrate; a first isolation element at the surface region first lateral boundary between said first doped region and said substrate; a heavily doped second region with associated electrical contact area within said first doped region of similar dopant to said first doped region; a heavily doped third region with associated electrical contact area within said first doped region of opposite dopant to said first doped region; a heavily doped fourth region with associated electrical contact area within said substrate of opposite doping than said substrate; a heavily doped fifth region with associated electrical contact area within said substrate of similar dopant to said substrate; a heavily doped sixth region of same dopant as said doped second region located at the surface region second lateral boundary of said first doped region and said substrate; a second isolation element adjacent to said fifth doped region and on opposite side from said fourth doped region; a first gate element overlying said surface region between said fourth doped region and said sixth doped region; a first insulation element layer on said substrate surface except on electrical contact areas; a first electrical conduction element connecting said second and third doped regions to a first voltage source; a second electrical conduction element connecting said fourth and fifth doped regions and said first gate element and to a second voltage source; and a top passivation layer overlaying said device surface.