Patent ID: 6989557

Claim:
A bipolar junction transistor, comprising: a substrate; at least a deep isolation trench formed in the substrate and at least a channel stop region formed in the bottom of the deep isolation trench; a dielectric layer formed on the substrate; an opening formed in the dielectric layer to expose a portion of the substrate; a selective implant collector region formed in the substrate and beneath the opening; a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening; an intrinsic base doped region positioned in a bottom of the opening and within the self-aligned base region defined by the heavily doped polysilicon layer; a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening; and an emitter conductivity layer being filled within the self-aligned emitter region, and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.