Patent ID: 7321949

Claim:
A memory device including self-ID information, the memory device comprising: a plurality of banks, wherein each bank includes; a predecoder for receiving and decoding an address signal, an information storage unit for storing information related to the memory device in such a manner that the information storage unit outputs the information related to the memory device by receiving an output signal of the predecoder, an input/output line driver for receiving the information outputted from the information storage unit, a data output driver for receiving an output signal of the an input/output line driver, and a data pad for receiving an output signal of the data output driver; wherein the information storage unit includes a first transistor connected between supply voltage and a first node and N fuse units connected between the first node and a ground, and wherein a control signal is applied to a gate of the first transistor in order to transfer the supply voltage to the first node, and wherein data stored in each fuse unit are outputted according to the output signal of the predecoder; and wherein each fuse unit includes a fuse connected between the first node and a second node and a second transistor connected between the second node and the ground, a gate of the second transistor receives an output signal of the predecoder, the information storage unit outputs a high-level signal if the fuse is a cut-off state when the second transistor is turned on by means of the output signal of the predecoder, and the information storage unit outputs a low-level signal if the fuse is not the cut-off state when the second transistor is turned on by means of the output signal of the predecoder.