Patent ID: 8309419

Claim:
A method for forming a semiconductor structure, comprising: providing a first semiconductor layer comprising a PMOS device area and an NMOS device area; forming a high-k gate dielectric layer over the first semiconductor layer in the PMOS and NMOS device areas; forming a first capping oxide layer on the high-k gate dielectric layer in at least the NMOS device area, where the first capping oxide layer comprises a first dopant species for doping the high-k gate dielectric layer in the NMOS device area; forming a second capping oxide layer on the high-k gate dielectric layer in at least the PMOS device area, where the second capping oxide layer comprises a second dopant species for doping the high-k gate dielectric layer in the PMOS device area; diffusing the first and second dopant species into the high-k gate dielectric layer in the PMOS and NMOS device areas, respectively, thereby forming a first fixed charge region in the PMOS device area of the high-k gate dielectric area and a second fixed charge region in the NMOS device area of the high-k gate dielectric area; forming a metal-based gate layer over the high-k gate dielectric layer in the PMOS and NMOS device areas; depositing a semiconductor gate layer over the first metal-based gate layer in the PMOS and NMOS device areas; and selectively etching the semiconductor gate layer and the metal-based gate layer to form NMOS and PMOS gate electrodes for NMOS and PMOS devices in the NMOS and PMOS device areas.