Patent ID: 7297596

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming an isolation layer pattern exposing upper faces of active regions and a dummy region, the active regions and the dummy region being disposed at an upper portion of a semiconductor substrate, the dummy region extending in a first direction; forming first grooves at an upper portion of the dummy region, the first grooves extending in a second direction substantially perpendicular to the first direction; forming second grooves at upper portions of the active regions, the second grooves extending in the second direction; forming third grooves under the first grooves, the third grooves extending in the second direction, the third grooves being communicated with the first grooves; forming fourth grooves under the second grooves, the fourth grooves extending in the second direction, the fourth grooves being communicated with the second grooves; forming gate oxide layers on faces of the dummy region and the active regions; forming a gate electrode layer, the gate electrode layer including a first portion and a second portion, the first portion being disposed on the isolation layer pattern and the gate oxide layers to fill the first and second grooves, the second portion disposed on the isolation layer pattern and the gate oxide layers to fill the third and fourth grooves, the second portion having a void; forming mask layer patterns extending in the second direction on the gate electrode layer; etching the gate electrode layer and the gate oxide layers by using the mask layer patterns as an etch mask to form gate electrodes and gate oxide layer patterns, respectively; and doping impurities into portions of the dummy regions and the active regions, the portions being exposed by the gate oxide layer patterns.