Patent ID: 7848166

Claim:
A memory circuit comprising: at least one memory cell for storing a charge representative of a datum, the memory cell coupled to a word line signal and a local bit line signal and outputting a small voltage on the local bit line signal responsive to a voltage on the word line signal; a sense amplifier circuit coupled to the local bit line signal and another complementary bit line signal for receiving a small signal differential voltage between the local bit line signal and the complementary bit line signal and having a latch for receiving the small signal differential voltage, the sense amplifier circuit having outputs coupled to the local bit line signal and the complementary bit line signal, and the sense amplifier circuit receiving an enable control signal; an equalization circuit coupled to both the local bit line signal and the complementary bit line signal to provide a positive supply voltage responsive to an equalization signal; and a voltage regulator circuit selectively coupled to one of the local bit line signal and the complementary bit line signal responsive to a control signal and outputting a positive reference voltage on the selected one of the local bit line signal and the complementary bit line signal that is less than the positive supply voltage by a predetermined amount.