Patent ID: 7425851

Claim:
A method for determining a phase error in response to a first signal and a second signal, said method comprising the steps of: generating a first reoccurring trigger event in response to the first signal, generating a second reoccurring trigger event in response to the second signal, incrementing a first phase value by a first predetermined increment value when the first trigger event occurs to obtain a first accumulated phase value represented by a binary number, incrementing a second phase value by a second predetermined increment value when the second trigger event occurs to obtain a second accumulated phase value represented by a binary number, and calculating or determining said phase error based on obtained first and second accumulated phase values, said phase error being represented by a binary number or one or more analogue signals, said method further comprising the steps of resetting the most significant bit of the first accumulated phase value and the most significant bit of the second accumulated phase value when the most significant bit of both said first accumulated phase value and said second accumulated phase value are simultaneously 1.