Patent ID: 7170106

Claim:
A power semiconductor device comprising: a first base layer of a first conductivity type; a collector layer of a second conductivity type disposed on the first base layer; a plurality of trenches disposed in the first base layer at intervals to partition a main cell and a dummy cell, at a position remote from the collector layer; a second base layer of the second conductivity type disposed on the first base layer in the main cell; an emitter layer of the first conductivity type disposed on the second base layer; a buffer layer of the second conductivity type disposed on the first base layer in the dummy cell; a gate electrode disposed in a trench of the plurality of trenches, adjacent to the main cell, to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer; a collector electrode disposed on the collector layer; an emitter electrode disposed on the second base layer and the emitter layer; and a buffer resistor inserted between the buffer layer and the emitter electrode, wherein the main cell forms a current passage narrow enough to provide, in an on-state of the device, an increase in resistance against flow of carriers of the second conductivity type from the first base layer into the emitter electrode through the second base layer, thereby improving injection efficiency of carriers of the first conductivity type from the emitter layer into the first base layer, and the buffer resistor has a resistance value smaller than that with which gate-emitter voltage is increased by gate negative capacity, in a period of time for an applied voltage between gate and emitter to charge capacity between gate and collector, in process of turn-on of the device.