Patent ID: 7190050

Claim:
An integrated circuit (IC) comprising a first plurality of transistors, wherein each of the first plurality of transistors comprises: a source; a drain; a channel region between the source and the drain; and a gate over the channel region, wherein the channel region comprises a set of semiconductor segments connecting the source and the drain, and wherein a centerline of a first one of the set of semiconductor segments in each of the plurality of transistors is aligned with a first common centerline, wherein each of the first plurality of transistors further comprises: a set of gate dielectrics, each of the set of gate dielectrics covering a top surface of one of the set of semiconductor segments; and a gate over the set of semiconductor segments, wherein the gate is separated from the set of semiconductor segments by the set of gate dielectrics, wherein each of the set of gate dielectrics in each of the first plurality of transistors extends down both sides of one of the set of semiconductor segments in the each of the first plurality of transistors by a first distance, and wherein the gate in each of the first plurality of transistors extends down both sides of each of the set of semiconductor segments in the each of the first plurality of transistors by the first distance, wherein the each of the set of semiconductor segments in the each of the first plurality of transistors includes a sub-surface heavily doped region, wherein the sub-surface heavily doped region in the each of the set of semiconductor segments in the each of the first plurality of transistors reaches at least 50% of maximum dopant concentration at the first distance below the top surface of the each of the set of semiconductor segments.