Patent ID: 8732548

Claim:
A processor comprising: an execution unit to perform a sequence of operations for a Cyclic Redundancy Check (CRC) instruction that identifies a first operand and a second operand, the sequence of operations to perform a CRC operation on a 2n-bit data block of the second operand using one of a plurality of different n-bit polynomials of the first operand to cause the execution unit to: expand an n-bit polynomial to provide a pre-computed polynomial K; and perform a sequence of micro-operations on the 2n-bit data block using the n-bit polynomial, a current n-bit residue of the first operand and the pre-computed polynomial K to provide an n-bit residue for the 2n-bit data block, including a shuffle by selection of an n-bit portion from the first operand and an n-bit portion from the second operand to store in a destination location.