Patent ID: 7583119

Claim:
A delay locked loop comprising: a coarse delay line configured to receive an output signal, to sequentially delay the output signal by a delay time, and to transmit a plurality of delayed output signals; a phase selector configured to select two delayed output signals from the plurality of delayed output signals; a phase blender configured to phase-blend the two delayed output signals; a phase detector configured to compare a clock signal to the phase-blended signal, and to generate a detection signal corresponding to a phase difference between the clock signal and the phase-blended signal; an auxiliary phase shifter configured to receive the clock signal, to delay the clock signal by a predefined time, to select between the delayed clock signal and the received clock signal, and to transmit the selected clock signal as the received output signal; and a control circuit configured to control the auxiliary phase shifter, the phase selector, and the phase blender responsive to the detection signal.