Patent ID: 8499206

Claim:
A memory system, comprising: at least one memory device configured to receive a clock signal and an operating voltage to operate; and a memory controller including an error detection circuit having an error counter to determine a bit error rate (BER) based on the number of bit errors occurring in data transmitted between the memory controller and the at least one memory device, and configured to output a first control signal to change a frequency of the clock signal when a determined BER exceeds a first reference BER, wherin the first reference BER is equal to or less than a maximum permissible BER designated for the system, wherein the memory controller is further configured to output a second control signal for raising a voltage level of the operating voltage when the measured BER exceeds the first reference BER, wherein the operating voltage has a level of a reference voltage when the system normally operates, and has a first voltage level higher than the level of the reference voltage in response to the second control signal, and wherein the memory controller is further configured to output a third control signal that causes the operating voltage to have a second voltage level lower than the first voltage level and higher than the level of the reference voltage when the operating voltage has the first voltage level and the measured BER is a second reference BER less than the first reference BER.