Patent ID: 7451248

Claim:
A method for invalidating cache lines during a direct memory access (DMA) Write operation by a peripheral device in a multiprocessor system, said method comprising: issuing a multi-cache line DMA request by a peripheral device associated with a multiprocessor system, wherein said multiprocessor system includes a plurality of processors, each of said processors having a cache memory; snooping said multi-cache line DMA request by said cache memories; determining whether or not any of said cache memories includes a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed; in response to a determination that one of said cache memories includes a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed, consecutively invalidating a plurality of cache lines within said one of said cache memories; and in response to a determination that none of said cache memories includes a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed, generating a separate coherence response by each portion of each of said cache memories.