Patent ID: 7702975

Claim:
A method comprising: testing, using a logic built-in self test device (LBIST) of an integrated circuit structure, logic blocks of said integrated circuit structure to determine a logic block functionality of each of said logic blocks; testing, using an array built-in self test device (ABIST) of said integrated circuit structure, an array of memory elements of said integrated circuit structure to determine a memory element functionality of each of said memory elements; storing, in a first register operatively connected to said ABIST, said memory element functionality; storing, in a second register operatively connected to said ABIST, an identifier for failing memory elements; enabling, using a first comparator operatively connected to said second register, a redundant memory element to operate in place of said failing memory elements; storing, in a third register operatively connected to said LBIST, said logic block functionality; storing, in a fourth register operatively connected to said LBIST, an identifier for failing logic blocks; enabling, using a second comparator operatively connected to said fourth register, a redundant logic block to operate in place of said failing logic blocks; and repairing, using a single controller operatively connected to said first register said second register said third register said fourth register said logic blocks and said memory elements, said failing logic blocks using said redundant logic block, and said failing memory elements using said redundant memory element.