Patent ID: 8014416

Claim:
An apparatus comprising: a processor; a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data; a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP), wherein low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the HRP comprises an outer code circuit, an outer interleaver circuit, M inner encoders, where M is larger than 1 and the outer interleaver comprises a block interleaver that maps consecutive bytes of an outer code codeword to a different inner code, and maps the same byte in the outer code codeword to consecutive bits for the inner code; and wherein the LRP is operable to generate a LRP data packet for acknowledgement of HRP packets.