Patent ID: 7189616

Claim:
A method for manufacturing a semiconductor memory device comprising: depositing an interlayer insulating film on a semiconductor substrate provided with contact plugs; patterning a mask pattern on the interlayer insulating film, the mask pattern having a layout in which a plurality of hole patterns having the same shape are arranged in a stagger manner so that side edges of the adjacent hole patterns are only partially opposite to each other; forming holes for storage nodes in the interlayer insulating film by etching with the mask pattern; forming the storage nodes in the holes so as to be connected electrically to the contact plugs; forming a capacitor insulating film on the storage nodes; and forming a plate electrode on the capacitor insulating film, wherein the length of a portion where the opposing capacitors are overlapperd in the mask layout is set so that the value of the parasitic capacitance between adjacent cell capacitors is not more than 10% of the set cell capacitance value.