Patent ID: 8456203

Claim:
A multiphase clock generation circuit comprising: a first frequency divider to generate a first intermediate clock and a second intermediate clock in synchronization with a reference clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock in synchronization with the first intermediate clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock in synchronization with the second intermediate clock; a selector, provided between the first frequency divider and the third frequency divider, to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between an output clock of the first group and an output clock of the second group when the switching signal indicates a first mode; and a re-reset circuit to output the switching signal to the selector based on the error in asynchronous with the reference clock.