Patent ID: 7154978

Claim:
A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal and having a plurality of primary output taps; a secondary delay circuit having a plurality of secondary output taps, the secondary delay circuit further having an input that receives a signal from a selected one of the primary output taps; and an output control circuit that selects one or more taps from either the primary delay line or the secondary delay circuit as an output, wherein the output control circuit selects taps based upon an algorithm that: computes a ratio K.C of the clock signal's frequency to a desired output frequency where C is a fractional part and K is an integer part of the ratio; and identifies a sequence of taps constituting a repeating tap cycle at approximately equally spaced delay increments, wherein a j th tap address C j is defined by C j =C j−1 +C.