Patent ID: 7838373

Claim:
A process comprising: forming a gate stack above a semiconductive body, wherein the semiconductive body includes a source region doping, a shallow tip source doping, a drain region doping, and a shallow tip drain doping, the gate stack including a gate stack upper surface and first and second sidewalls; forming a first spacer at the first and second sidewalls; forming first and second stacked trench source and drain contacts respectively spaced apart and adjacent the first and second sidewalls; planarizing the gate stack and the first spacer and the first and second stacked trench source and drain contacts; after planarizing the gate stack and the first spacer and the first and second stacked trench source and drain contacts, removing the first spacer to leave a spacer void; filling the spacer void with a replacement spacer, wherein the replacement spacer has a different dielectric constant than the first spacer, and wherein capacitance between the gate stack and the stacked trench source and drain contacts, and between the gate stack and the tip doping, is lower than previously between the gate stack, the first spacer, and the adjacent stacked trench contacts and tip doping.