Patent ID: 7941644

Claim:
A circuit, comprising: first and second execution units; instruction buffer logic configured to supply instructions from a plurality of threads for the first and second execution units; a multithreaded issue unit coupled to the instruction buffer logic and the first and second execution units, the multithreaded issue unit including first and second issue select logic respectively configured to output instructions from the plurality of threads to the first and second execution units; first and second multiplexers coupled to the first issue select logic, the first and second multiplexers respectively associated with first and second threads from among the plurality of threads, each of the first and second multiplexers including an output in communication with the first issue select logic and first and second inputs, wherein the first input of each of the first and second multiplexers is coupled to the instruction buffer logic to receive instructions therefrom; and a sequencer coupled to the second inputs of the first and second multiplexers, the sequencer configured to, in response to a filtering instruction associated with the first thread and output by the instruction buffer logic, control the first multiplexer to select the second input to block instructions associated with the first thread and received from the instruction buffer logic from execution by the first execution unit, and sequentially output a plurality of instructions associated with a filtering operation to the second input of the first multiplexer while the second input of the first multiplexer is selected such that the plurality of instructions associated with the filtering operation are executed by the first execution unit; wherein the first issue select logic is configured to output instructions associated with the second thread and provided by the issue select logic via the first input of the second multiplexer for execution by the first execution unit while instructions associated with the first thread are blocked from execution by the first execution unit, and wherein the second issue select logic is configured to output instructions supplied thereto by the instruction buffer logic for execution by the second execution unit while instructions associated with the first thread are blocked from execution by the first execution unit.