Patent ID: 8330630

Claim:
A circuit arrangement comprising: a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signal, a second signal generator configured to generate a second pulse signal, wherein a delay between a rising edge of the first pulse signal and a rising edge of the second pulse signal is proportional to one of a phase difference and a frequency difference between the first input signal and the second input signal, a first converter configured to convert the first pulse signal to a first digital number proportional to a width of the first pulse signal, and a second converter configured to convert the second pulse signal to a second digital number proportional to a width of the second pulse signal, wherein at least one of the first converter and the second converter comprises a cascade of at least two converter stages, wherein each converter stage of the at least two converter stages is configured to propagate and shrink the respective pulse signal.