Patent ID: 6908817

Claim:
A method of making an array of non-volatile memory cells on a semiconductor substrate surface, comprising: forming an array of floating gate first elements across the substrate surface with a gate dielectric layer therebetween, the floating gate first elements individually having a dimension in at least one direction across the substrate according to a minimum process element size, depositing dielectric material over the floating gates first elements, forming slots in the dielectric material above the floating gate first elements, wherein the slots have a dimension in said at least one direction across the substrate that is less than the minimum process element size, forming floating gate second elements within said slots in a manner to contact corresponding ones of the first elements at bottoms of the slots, thereafter removing the dielectric material, thereby to expose surfaces of the first and second floating gate elements, forming a dielectric layer on the exposed floating gate element surfaces, and forming conductive gates extending across the floating gates in said at least one direction and in contact with the dielectric layer.