Patent ID: 7167034

Claim:
A clock phase corrector for use in a receiver receiving a transmitted signal having a predetermined transmission rate for correcting a phase of a data sampling clock signal, comprising: a timing control circuit for generating a plurality of sampling clock signals, and selecting one of the sampling clock signals as the data sampling clock signal, the plurality of sampling clock signals having a period corresponding to the transmission rate and a phase different from each other; an over-sampling circuit operative in response to the plurality of sampling clock signals for sampling the received signal, said over-sampling circuit comprising a plurality of shift registers, each of which corresponds to one of the plurality of sampling clock signals and stores a signal sampled in response to the one sampling clock signal; a gate circuit operative in response to the data sampling clock signal for sampling the received signal to output data resultant from sampling; a storage circuit for storing the data output from said gate circuit; a calculator for comparing the stored data with the sampled signals respectively stored in the plurality of shift registers to determine a number of inconsistent bits between the stored data and the sampled signals; and a comparator for comparing the number of inconsistent bits with a predetermined error acceptance number, and determining a period of time in which the number of inconsistent bits is smaller than the predetermined error acceptance number; said timing control circuit determining a center of the period of time, and selecting one of the plurality of sampling clock signals which corresponds to the center as the data sampling clock signal.