Patent ID: 7484140

Claim:
A method for testing a plurality of integrated circuit memories, each of the integrated circuit memories having a plurality of memory cells that require periodic refreshing to maintain stored data, the method comprising the steps of: providing a semiconductor wafer having the plurality of the integrated circuit memories, each of the plurality of integrated circuit memories having a refresh counter for providing a refresh timing signal to a refresh control circuit to control a refresh rate of the plurality of memory cells; providing a programmable fuse circuit coupled to the refresh control circuit on each of the plurality of integrated circuit memories; providing a built-in self test (BIST) circuit on each of the plurality of integrated circuit memories for scanning test data into and out of the plurality of memory cells on each of the plurality of integrated circuit memories; providing a plurality of wafer test pads coupled to the BIST circuits on the semiconductor wafer; contacting the wafer test pads with wafer probe needles; measuring a charge retention ability of the plurality of memory cells on each of the plurality of integrated circuit memories; analyzing the charge retention ability of the plurality of memory cells on each of the plurality of integrated circuit memories to determine a plurality of refresh rates, a refresh rate corresponding to each of the plurality of integrated circuit memories; and programming each of the programmable fuse circuits of the plurality of integrated circuit memories with its corresponding refresh rate.