Patent ID: 7165198

Claim:
A logic circuit for testing an integrated circuit at a plurality of locations within the integrated circuit with a plurality of test modes, the logic circuit comprising a sequence of test-mode storage devices, each of which has an input and an output, the sequence including at least: a first test-mode storage device for storing a first test mode, the first test-mode storage device being disposed at a first location selected from the plurality of locations, and being configured to perform a shift operation by providing the first test-mode at its output; a second test-mode storage device for storing a second test-mode, the second test-mode storage device being disposed at a second location selected from the plurality of locations, having its input connected to the output of the first test-mode storage device, and being configured to perform the shift operation by receiving, at its input, the first test mode and providing, at its output, the second test-mode.