Patent ID: 8437441

Claim:
A phase locked loop comprising: a voltage controlled oscillator operable so as to generate an output signal corresponding to a reference signal in response to a control voltage signal received thereby; a variable frequency divider coupled to said voltage controlled oscillator for receiving the output signal therefrom and operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal; a phase/frequency detector coupled to said variable frequency divider, detecting the divided feedback signal from said variable frequency divider and the reference signal, and outputting a phase detecting output indicating phases of the divided feedback signal and the reference signal; a charge pump coupled to said phase/frequency detector for receiving the phase detecting output therefrom, and outputting a current signal in response to the phase detecting output received thereby; a filter coupled between said charge pump and said voltage controlled oscillator, receiving the current signal from said charge pump, and outputting the control voltage signal in response to the current signal received thereby; and a phase error comparator coupled to said phase/frequency detector and said variable frequency divider, receiving the phase detecting output from said phase/frequency detector, and outputting a digital output in accordance with the phase detecting output received thereby, the digital output indicating whether the divided feedback signal lags or leads the reference signal, and further indicating a phase difference between the divided feedback signal and the reference signal; wherein said variable frequency divider receives the digital output from said phase error comparator, and determines a value of the variable divisor in accordance with the digital output received thereby so that the phase difference between the divided feedback signal and the reference signal is reduced.