Patent ID: 7411246

Claim:
An electrically programmable and erasable memory device comprising: a substrate of semiconductor material having a first conductivity type and a surface; first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween having a first portion and a second portion; an electrically conductive floating gate having first and second elongated portions joined together at proximal ends thereof in a non-linear manner, wherein the floating gate first portion extends along and is insulated from the channel region second portion for controlling a conductivity of the channel region second portion, and wherein the floating gate second portion is positioned for capacitive coupling with the first region; an electrically conductive control gate disposed adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion; and a block of conductive material disposed over and electrically connected to the first region, wherein the floating gate second portion extends along and is insulated from a surface of the conductive material block; wherein the control gate includes a first portion disposed adjacent to and insulated from a distal end of the floating gate first portion, and a second portion disposed adjacent to and insulated from the channel region first portion; and wherein the control gate further includes a third portion that is disposed over and insulated from a distal end of the floating gate second portion.