Patent ID: 8922183

Claim:
A switch-mode power supply (SMPS), comprising: at least one power switch coupled to a voltage source; a power inductor coupled to the at least one power switch; a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage output of the SMPS; at least one driver coupled to the at least one power switch; a pulse width modulation (PWM) generator having at least one output coupled to and controlling the at least one driver, the at least one output of the PWM generator providing at least one PWM signal comprising a plurality of pulses; a digital processor having a memory; a first operational transconductance amplifier (OTA) having a first input coupled to a reference voltage, a second input coupled to the regulated voltage output of the SMPS, and a current input for controlling a transconductance thereof; a first current digital-to-analog converter (IDAC) having an analog output coupled to the current input of the first OTA, a current reference input coupled to a current reference, and digital inputs coupled to the digital processor for controlling a current value from the output thereof; a second operational transconductance amplifier (OTA) having a first input coupled to an output thereof, a second input coupled to a common of the regulated voltage output of the SMPS, and a current input for controlling a transconductance thereof; a second current digital-to-analog converter (IDAC) having an analog output coupled to the current input of the second OTA, a current reference input coupled to the current reference, and digital inputs coupled to the digital processor for controlling a current value from the output thereof; a first capacitor connected between the outputs of the first and second OTAs; and a second capacitor connected between the output of the first OTA and the common of the regulated voltage output of the SMPS; wherein the digital processor optimizes analog negative feedback operation of the SMPS by changing the transconductances of the first and second OTAs through the first and second IDACs.