Patent ID: 7858524

Claim:
A semiconductor device manufacturing method comprising: forming a gate insulation film on a semiconductor substrate; depositing a gate electrode material on the gate insulation film; depositing a mask material on the gate electrode material; shaping the mask material into a gate electrode pattern; processing the gate electrode material into the gate electrode pattern using the shaped mask material as a mask; forming a spacer on the side surface of the processed gate electrode material; depositing an interlayer insulation film on the gate electrode material and on the semiconductor substrate; polishing the interlayer insulation film until the upper surface of the mask material is exposed; exposing the upper surface of the gate electrode material in a p-type MISFET forming-region by selectively removing the mask material in the p-type MISFET forming-region; depositing a first metal film on the gate electrode material in the p-type MISFET forming-region; siliciding the whole of the gate electrode material in the p-type MISFET forming-region by reacting the gate electrode material with the first metal film (a first silicidation); exposing the upper surface of the gate electrode material in an n-type MISFET forming-region by removing the mask material in the n-type MISFET forming-region; depositing a second metal film on the respective gate electrode materials of the p-type MISFET and the n-type MISFET, a material of the second metal film being the same as the material of the first metal film; and siliciding the whole of the respective gate electrode materials in the p-type MISFET and the n-type MISFET by reacting the respective gate electrode materials with the second metal film (a second silicidation).