Patent ID: 7213226

Claim:
A method of correcting a finish pattern dimension by using OPC when a wafer design pattern is formed on a wafer, comprising: selecting and determining a first design pattern included in the wafer design pattern; acquiring a measurement value of a first finish pattern dimension when the first design pattern is formed on the wafer; determining a first calculation model by using the first finish pattern dimension; selecting and determining a second design pattern from the wafer design pattern except for the first design pattern; performing a first simulation by using the first calculation model, and calculating a second finish pattern dimension when the second design pattern is formed on the wafer; determining a second calculation model for performing a second simulation which is faster than the first simulation, by using the first finish pattern dimension and the second finish pattern dimension; and performing the second simulation by using the second calculation model, and calculating a third finish pattern dimension of a third design pattern of the wafer design pattern except for the first and second design patterns.