Patent ID: 7831818

Claim:
A processing device comprising: a first timer; an exception controller configured to provide a first exception indicator representative of a first exception; an instruction pipeline configured to execute an interrupt handler routine in response to the first exception indicator; a timer controller configured to selectively enable/disable the first timer in response to a termination of execution of the interrupt handler routine; and a timer control criteria storage component configured to store a configuration data for the first timer, the configuration data indicating a corresponding timer configuration for the first timer for each of a plurality of exception characteristics, the first exception having a select exception characteristic of the plurality of exception characteristics, and the configuration data including a first configuration data representing whether the first timer is to be enabled for each of the plurality of exception characteristics and a second configuration data representing whether the first timer is to be disabled for each of the plurality of exception characteristics; and wherein the timer controller is configured to selectively enable/disable the first timer by: determining a timer configuration for the first timer corresponding to the select exception characteristic from the configuration data; and selectively enabling/disabling the first timer based on the timer configuration.