Patent ID: 8493125

Claim:
A level shift circuit comprising: a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential; a latch circuit that operates on a power supply of a second potential which is higher than the first potential, the latch circuit having one end thereof connected to an output end of the CMOS inverter circuit and outputting from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal; and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit; wherein the power supply circuit functions to limit the power supply when the input pulse signal assumes at least a ground level, wherein the power supply circuit includes a reverse current blocking circuit that operates to block current from flowing from a power supply terminal of the CMOS inverter circuit to a power supply side of the CMOS inverter circuit when the input pulse signal assumes the ground level.