Patent ID: 7644480

Claim:
A method for manufacturing a multilayer chip capacitor, comprising the steps of: forming screen patterns on a plurality of mother green sheets such that a widthwise margin is not formed on the mother green sheets, the screen patterns on each mother green sheet are spaced apart from each other in the width direction and the longitudinal direction, and a width of each screen pattern on each mother green sheet is greater than a spacing between the adjacent screen patterns; forming first internal electrode patterns and second internal electrode patterns on the plurality of mother green sheets by use of the screen patterns; forming a stack of the mother green sheets by stacking the plurality of mother green sheets having the internal electrode patterns formed thereon; forming a capacitor body having a plurality of first and second internal electrodes, each of the first and second internal electrodes comprising a main electrode portion and a lead portion, wherein the main electrode portion is formed by cutting the stack of the mother green sheets along cutting lines arranged in the longitudinal direction and has a width corresponding to the width of the screen patterns after the cutting, and the lead portion is formed by cutting the stack of the mother green sheet along cutting lines arranged in the width direction and corresponds to the spacing between the adjacent screen patterns; forming chip-protecting side members on both sides of the capacitor body such that the chip-protecting side members contact both sides of the internal electrodes, respectively; and forming a pair of terminal electrodes on the outer surface of the capacitor body such that the terminal electrodes are connected to the internal electrodes through the lead portions.