Patent ID: 7493481

Claim:
A data processing apparatus comprising: a template storage unit storing a template having a plurality of entries, each template entry corresponding to an internal field of a data structure, each template entry specifying a memory address offset of a word relative to a base address of the data structure, and an internal field bitspan within the word, the field bitspan defining a field start position and a field length, the field bitspan being bounded by at least one intra-byte bit not forming a byte boundary; a base register storing the base address of the data structure; a target register; a control unit connected to the template storage unit and an instruction memory, comprising logic configured to receive from the instruction memory a machine language memory access instruction including an identifier of the base register and an identifier of a target template entry, the target template entry corresponding to a target field of the data structure, and transmit to the template storage unit the identifier of the target template entry; an internal-field address arithmetic logic unit connected to the base register, the template storage unit, and a data memory, comprising logic configured to receive the base memory address from the base register; receive a target memory address offset for the target field from the template storage unit, determine an address of the target field by adding the base memory address and target memory address offset; and transmit to the data memory a memory access command identifying the target memory address offset; and an intra-word processing arithmetic logic unit connected to the target register and the data memory, comprising logic configured to perform an intra-word content modification operation as at least part of a content of the word is transferred between the data memory and the target register.