Patent ID: 7880243

Claim:
A circuit structure, comprising: at least one NFET device, said NFET device comprises an n-channel hosted in a Si based material, and an NFET gate stack overlapping said n-channel, wherein said NFET gate stack has a length which is shorter than about 60 nm and comprises a first layer of a gate metal, wherein said gate metal has about a quarter-gap work function; at least one PFET device, said PFET device comprises a p-channel hosted in said Si based material, and a PFET gate stack overlapping said p-channel, wherein said PFET gate stack has a length which is shorter than about 60 nm and comprises a second layer of said gate metal; wherein said NFET device further comprises an NFET gate insulator, wherein said NFET gate insulator comprises a first high-k layer, wherein said first high-k layer directly interfaces with said first layer of said gate metal; wherein said PFET device further comprises a PFET gate insulator, wherein said PFET gate insulator comprises a second high-k layer, wherein said second high-k layer directly interfaces with said second layer of said gate metal; and wherein said first high-k layer has a first concentration of charges and said second high-k layer has a second concentration of charges, wherein said second concentration is more negative than said first concentration, whereby indicating a history of oxygen exposure of said second high-k layer, and wherein absolute values of the saturation thresholds of said NFET and said PFET devices are between about 0.5 V and 0.75 V.