Patent ID: 6867436

Claim:
A flip chip, comprising: a transient voltage suppression device including a semiconductor die, the semiconductor die including (a) a semiconductor substrate diffused with a first material to give the substrate a first conductivity type, the substrate having a substrate surface; (b) a buried layer selectively formed in the substrate surface and diffused with a second material to give the buried layer the opposite conductivity type as the substrate; (c) an epitaxial layer formed on the substrate surface and on the buried layer, the epitaxial layer having the opposite conductivity type as the substrate, the epitaxial layer having an epitaxial surface distal from the substrate surface, the epitaxial layer having a higher resistivity than the resistivity of the buried layer; (d) a first diffused region selectively formed on the epitaxial surface, the first diffused region having the same conductivity type as the epitaxial layer, the first diffused region having a first surface distal from the substrate surface; (e) a second diffused region selectively formed on the first surface, the second diffused region having a second surface distal from the substrate surface, the second diffused region having the opposite conductivity type as the first diffused region, the first diffused region and the second diffused region forming a first semiconductor junction; and (f) a third diffused region selectively formed on the epitaxial surface remote from the first diffused region, the third diffused region having a third surface distal from the substrate surface, the third diffused region having the opposite conductivity type as the epitaxial layer, the epitaxial layer and the third diffused region forming a second semiconductor junction, the second surface and the third surface providing first and second external electrical contacts for the transient voltage suppression device; and (g) a first aluminum region disposed on the second surface and a second aluminum region disposed on the third surface, including two solder bump pads at the first aluminum region and two solder bump pads at the second aluminum region, in which the two solder bump pads at the first aluminum region are electrically coupled to the second diffused region and the two solder bump pads at the second aluminum region are electrically coupled to the third diffused region, wherein the first semiconductor junction operates in a reverse avalanche mode while the second semiconductor junction operates in a forward conducting mode during a transient over-voltage event, and a transient current is shunted through the buried layer during the transient over-voltage event.