Patent ID: 7548126

Claim:
A phase locked loop circuit comprising: a phase comparator for comparing a phase of a feedback signal with that of a reference clock signal; a charge pump connected to said phase comparator for producing an analog signal corresponding to a pulse width of an output signal from said phase comparator; a loop filter connected to said charge pump for smoothing the analog signal to produce a frequency control signal; a voltage controlled oscillator connected to said loop filter for producing an output clock signal according to oscillating characteristic value based at least in part on the frequency control signal; a frequency divider connected between said voltage controlled oscillator and said phase comparator for dividing the output clock signal to supply a divided signal as the feedback signal to said phase comparator; a gain controller connected to said voltage controlled oscillator that produces a switching signal, said voltage controlled oscillator increasing the oscillating frequency characteristic value stepwise by means of controlling a delay value of a delay circuit included therein according to a stepwise increase in the switching signal, a time of the switching signal being based on an elapsed timing from initialization of the phase locked loop circuit.