Patent ID: 7606336

Claim:
An analog Viterbi decoder, comprising: a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells that are vertically arranged so as to correspond to respective nodes on a trellis diagram, each of the plurality of decoding units decoding analog input data using an analog signal processing cell having a circulation type connection structure in which a last processing part is connected to a first processing part; a control unit that performs in parallel a sequential designation of the plurality of processing parts with respect to the plurality of decoding units in accordance with an external input clock signal; an analog data storage unit including a plurality of capacitors connected in parallel with the plurality of processing parts that are provided in the plurality of decoding units; and a first switch unit that stores analog input data in a specific capacitor of the analog data storage unit that is controlled by the control unit, wherein the plurality of decoding units comprises a first decoding unit and a second decoding unit, and wherein the sequential designation of the plurality of processing parts with respect to the plurality of decoding units comprises designating the first decoding unit to start decoding a specified bit of the analog input data using the first processing part of the first decoding unit, and designating the second decoding unit to start decoding a next bit of the analog input data using a second processing part of the second decoding unit, said first and second processing parts being among the plurality of processing parts.