Patent ID: 7250657

Claim:
A layout structure of a static random access memory (SRAM) cell array having one or more SRAM cells, each of which has a pair of cross-coupled inverters and a pair of passing gate transistors coupled to the inverters for controlling outputs thereof, the layout structure comprising: at least one SRAM cell area in which the inverters and the passing gate transistors are constructed, having a longitudinal side substantially longer than a transverse side thereof; at least one oxide defined (OD) area formed on an insulating layer, extending across at least two neighboring SRAM cell areas for construction of the passing gate transistor and a pull-down transistor within the inverter thereon; and at least one strapping cell area interposed between the SRAM cell areas for connecting the OD area to a fixed potential, thereby preventing bodies of the passing gate transistor and the pull-down transistor from floating.