Patent ID: 8409975

Claim:
A method for decreasing polysilicon gate resistance in a carbon co-implantation process, comprising: depositing a first salicide block layer on a formed gate of a MOS device, then etching said first salicide block layer to form a first spacer on a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment to make heavily doped boron atoms in the polysilicon gate diffused sufficiently during the thermal annealing treatment, so as to decrease resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon ion co-implantation process at the same time, so as to form ultra-shallow junctions at interfaces in the MOS device between a substrate and a source region and between the substrate and a drain region below the gate, after performing the P-type heavily doped boron implantation process and the thermal annealing treatment; re-depositing a second salicide block layer on the gate, then etching the second salicide block layer to form a second spacer; performing a self-alignment silicide process, to form a self-aligned silicide on surface of the MOS device.