Patent ID: 8898430

Claim:
A data processing apparatus comprising: a processor for processing a stream of instructions; a hierarchical memory system comprising a cache, a memory and cache management circuitry; said processor identifying storage locations using virtual addresses and said memory system storing data using physical addresses, said memory being configured to store tables comprising virtual to physical address translations, said cache being to configured to store a subset of said virtual to physical address translations, said cache management circuitry being configured to control transactions received from said processor requesting virtual address to physical address translations; wherein said data processing apparatus is configured to identify where a faulting transaction has occurred during execution of a context and whether said faulting transaction has a transaction stall or transaction terminate fault; said cache management circuitry is configured: to respond to identification of said faulting transaction and to said faulting transaction having a transaction terminate fault to invalidate all address translations in said cache that relate to said context of said faulting transaction such that a valid bit associated with each entry in said cache is set to invalid for said address translations, invalid entries being available for update and not forming part of any lookup in said cache; and to respond to identification of said faulting transaction and to said faulting transaction having a transaction stall fault to set a stall indicator associated with all address translations in said cache that relate to said context of said faulting transaction.