Patent ID: 7645670

Claim:
A method for fabricating a nonvolatile memory device, the method comprising: forming a tunneling insulation layer, a first conductive layer for forming a floating gate, and a hard mask over a substrate; etching a portion of the hard mask, the first conductive layer, the tunneling insulation layer, and the substrate to form a trench; forming an isolation structure to fill in the trench; removing the etched hard mask such that an upper portion of the isolation structure protrudes above the etched first conductive layer; forming a dielectric layer over the etched first conductive layer; forming a second conductive layer for forming a control gate over the isolation structure and the dielectric layer; and polishing the second conductive layer to align an upper surface of the second conductive layer using an upper surface of the isolation structure, wherein polishing the second conductive layer comprises: polishing the second conductive layer using a first polish selectivity ratio between the isolation structure and the second conductive layer while using the isolation structure as a polish stop layer; and polishing the isolation structure and the remaining second conductive layer using a second polish selectivity ratio which is lower than the first polish selectivity ratio.