Patent ID: 8854896

Claim:
A nonvolatile semiconductor memory device, comprising: multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of serially connected memory cells; a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings; a back gate line connected to the control gates of the back gate transistors; and a voltage generating circuit configured to generate first, second, and third control voltages of different voltage levels, the first voltage having a higher voltage level than the second control voltage and the second control voltage having a higher voltage level than the third control voltage; and a control circuit configured to control application of control voltages to the word lines and the back gate line, wherein when a word line connected to the control gates of the memory cells in the first and second groups that are adjacent to the back gate transistor is a selected word line, the first control voltage is applied to the selected word line and the second control voltage is applied to the back gate line, and when a word line connected to the control gates of the memory cells in the first and second groups that are that are not adjacent to the back gate transistor is a selected word line, the first control voltage is applied to the selected word line and a control voltage that is less than or equal to the third control voltage is applied to the back gate line.