Patent ID: 7145832

Claim:
A semiconductor memory device comprising: a plurality of dynamic type memory cells having storage data refreshed; read circuitry responsive to a read instructing signal applied externally to the memory device, for performing a reading operation of reading out data of the memory cell externally to the memory device; refresh control circuitry including a timer circuit for generating a refresh request signal requesting refreshing of the data of the memory cells based on an oscillation signal from an oscillator provided within the memory device, for causing the refreshing to be performed after completion of the reading operation when the refresh request signal is activated during the reading operation; and shifter circuitry for causing the reading operation according to the read instructing signal currently and externally applied to be performed after elapse of a completion time for completing a previous reading operation performed in accordance with the read instructing signal previously and externally applied when the read instructing signal currently and externally applied is received at a shorter period of time than a restore time of a memory cell in the previous reading operation, said restore time being required for reading data and restoring a state of the read out memory cell to an initial state.