Patent ID: 6989562

Claim:
A semiconductor device including a plurality of non-volatile memory cells arrayed in rows and columns, the semiconductor device comprising: (a) a semiconductor substrate comprising a first region of a first conductivity type; (b) a plurality of parallel pairs of parallel implant region lines of a second conductivity type in the first region, wherein each of the columns of the non-volatile memory cells overlaps a respective one of the pairs of the implant regions lines, respective subportions of one of the implant region lines of the pair comprise respective source regions for the respective memory cells of the respective column, respective subportions of the other implant region line of the pair comprise respective drain regions for the respective memory cells of the column, and respective subportions of the first region between the respective source and drain regions of the respective memory cells comprises respective channel regions of the respective memory cells of the column; (c) one or more dielectric region lines in the first region and parallel to the implant region lines, wherein at least one of the dielectric region lines is between adjacent said pairs of the implant region lines; (d) a tunnel dielectric layer formed in a vicinity of the source region of each of the non-volatile memory cells, wherein the tunnel dielectric layer is in contact with the respective source region; (e) a plurality of regions of a first polysilicon layer, wherein each said non-volatile memory cell has one of the first polysilicon layer regions over the source region and over and in contact with the tunnel dielectric layer, the first polysilicon region being a floating gate that terminates over the channel region without extending to the drain region of the memory cell; (f) a plurality of lines of a second polysilicon layer each extending perpendicularly to the implant region lines, wherein each said second polysilicon layer line integrally overlies all of the memory cells of a row and the dielectric region line between adjacent memory cells of the row, and a respective subportion of the second polysilicon layer line is a control gate of each said memory cell of the row; and (g) at each of the non-volatile memory cells, a dielectric layer separating the second polysilicon layer line from the region of, first region surface over the channel region, and the drain region.