Patent ID: 8093932

Claim:
A power-on reset signal generation circuit of a semiconductor memory apparatus, comprising: an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal, wherein the level detection voltage dividing unit comprises: a band gap voltage level detector configured to detect the level of the band gap voltage and generate a band gap detection signal; a voltage transfer switching section configured to output the external voltage as a transfer voltage in response to the band gap detection signal; and a voltage dividing section configured to divide the transfer voltage and generate the division voltage, wherein the band gap voltage level detector comprises: a voltage dropping part configured to drop the level of the band gap voltage and generate a drop voltage; a level detecting part configured to generate a drop detection signal in response to a level of the drop voltage; and a driving part configured to drive the drop detection signal and output it as the band gap detection signal; and wherein the level detecting part is configured to be applied with the band gap voltage to its positive power supply terminal and enable the drop detection signal when the drop voltage is higher than a target level.