Patent ID: 8466911

Claim:
A low voltage differential signal (LVDS) output stage, comprising: a display signal digital circuit, generating a display signal and a display clock signal synchronous to each other according to a first clock signal having a first frequency; a data parallel-to-serial (P2S) circuit, sampling the display signal according to a second clock signal having a second frequency, so as to generate a serial data signal and a serial clock signal, wherein the first frequency of the first clock signal and the second frequency of the second clock signal have a multiplication relationship, the data P2S circuit comprises an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second clock signal; and a transmitting circuit, connected to the data P2S circuit, for outputting the serial data signal and the serial clock signal to serve as outputs of the LVDS output stage, wherein the adjustment structure comprises a pipeline delay stage, receiving the second clock signal and the display clock signal, and sampling the display clock signal according to the second clock signal, so as to generate a quantified signal; a determining circuit, connected to the pipeline delay stage, for determining a positive edge section of the display clock signal to determine a phase difference between the load signal and the display clock signal, so as to adjust a shift signal; and a frequency divider, receiving a signal, outputting the serial clock signal after performing a frequency dividing operation, and outputting a load signal, wherein the signal is generated according to the second clock signal and the shift signal.