Patent ID: 7630251

Claim:
A semiconductor memory device comprising: a memory cell array with NAND cell units arranged therein, the NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit to a bit line and a source line, respectively, and dummy cells disposed between the select gate transistors and the memory cells neighbored to them, wherein the dummy cells are set in a threshold voltage distribution higher than the erased threshold voltage of the memory cell by combination of a first program state and a second program state, the first program state being for boosting the threshold voltage of the dummy cells with a program voltage applied while the second program state being for suppressing an increase of the threshold voltage of the dummy cells in comparison with the first program state after reaching a certain threshold level, wherein the dummy cell is programmed in the first program state with the program voltage applied thereto under the condition that a first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the first program state, and wherein the dummy cell is programmed in the second program state with the program voltage applied thereto under the condition that a second bit line control voltage higher than the first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the second program state.