Patent ID: 8065648

Claim:
A processor-implemented method of modeling an integrated circuit in a computer aided design (CAD) system, comprising: generating a device model of the integrated circuit in at least one first computer file, the device model having a component hierarchy; defining a common delay identifier for component instances in the component hierarchy of the device model; generating a value model for the device model in at least one second computer file; defining delay values for the common delay identifier in the value model, at least a portion of the delay values being qualified based on location in the component hierarchy of at least one of the component instances; and wherein the defining delay values comprises: generating qualified delay identifiers, each of the qualified delay identifiers including the common delay identifier and indicia of location in the component hierarchy; assigning one of the delay values to each of the qualified delay identifiers; and outputting the delay values, wherein the generating a device model, the defining the common delay identifier, the generating the value model, the defining delay values, and the outputting are performed by the processor.