Patent ID: 7642836

Claim:
An integrated circuit comprising: two power supply terminals configured to power the integrated circuit, said power supply terminals including a V dd positive supply terminal and a V SS ground terminal together defining a range of logic levels; a logic component, said logic component being a selected one of a logic gate and a storage cell, and said logic component including a sleep transistor in series with an electrical connection to one of said power supply terminals; a voltage generator configured to selectively generate a voltage outside said range of logic levels; circuitry configured to apply said voltage outside the range of logic levels to said sleep transistor to minimize leakage current through the sleep transistor during a power down mode and to apply another voltage outside the range of logic levels to said sleep transistor when in a mode other than said power down mode; and a voltage regulator configured to control said voltage generator to adequately minimize leakage current through said sleep transistor during said power down mode.