Patent ID: 8352924

Claim:
A method for multi-core instruction-set simulation, comprising: converting a binary program of a target frame into an intermediate code; analyzing a control flow instruction of said intermediate code to establish a control flow graph of said binary program; estimating execution time of each basic block in said control flow graph; estimating relative time of each read or write memory instruction; for each basic block, identifying each said read or write memory instruction that is the earliest possible instruction to be met after finishing execution of each said basic block as a sync point; for each sync point, removing said sync point if a register for pointing address of each said read or write memory instructions is a stack pointer register or a frame pointer register, inserting a first sync handler if the sync point is a write instruction or inserting a second sync handler if the sync point is a read memory instruction; and using said intermediate code, said read or write memory instruction which is the earliest possible instruction to be met after finishing execution of each said basic block, said sync point, and said sync handler to generate native codes for simulating said binary program.