Patent ID: 7920796

Claim:
A parallel precoder and alignment circuit, comprising: precoding circuitry configured to process a first and second high-speed data stream; a first field programmable gate array comprising a first high-speed input/output interface configured to: receive the first high-speed data stream; process the first high-speed data stream to a lower rate; transmit the first high-speed data stream to the precoding circuitry; receive the processed first high-speed data stream; and transmit the processed first high-speed data stream to a first multiplexer; a second field programmable gate array comprising a second high-speed input/output interface configured to: receive the second high-speed data stream; process the second high-speed data stream to a lower rate; transmit the second high-speed data stream to the precoding circuitry; receive the processed second high-speed data stream; and transmit the processed second high-speed data stream to a second multiplexer; a clock unit configured to provide timing to the precoding circuitry, the first field programmable gate array, and the second field programmable gate array; and an alignment circuit configured to receive the precoded first and second high-speed data streams from the precoding circuitry; wherein the alignment circuit is configured to phase lock the first and second high-speed data streams.