Patent ID: 8723289

Claim:
An interconnection wiring structure of a semiconductor device, comprising: first and second bit line contacts penetrating through a first interlayer insulation layer on a semiconductor substrate and aligned with a cell region and a peripheral region of the semiconductor substrate, respectively; first and second bit lines overlaid with the first and second bit line contacts, respectively; a plurality of storage node contacts, where each storage node contact is arranged between first bit lines and penetrates the first interlayer insulation layer; a plurality of trench spacers, where each trench spacer is situated between a bit line and a storage node contact and extends on a side face of the bit line contact; a second interlayer insulation layer situated to isolate the storage node contacts; a third interlayer insulation layer for isolating the second bit lines; a capacitor having a storage node connected to the storage node contact; a fourth interlayer insulation layer for covering the capacitor and the third interlayer insulation layer; and an interconnection contact penetrating through the fourth and third interlayer insulation layers on the peripheral region of the semiconductor substrate and aligned with a second bit line.