Patent ID: 7234089

Claim:
Circuitry for testing and implementing a distributed tristate bus arrangement, the distributed tristate bus arrangement including: a data bus; a first block having at least a first tristate cell including: a first enable input for receiving a first enable signal; a first data input for receiving data; a first data output in communication with the data bus; first cascade circuitry having a first cascade input for accepting a first test signal, the first cascade circuitry also accepting the first enable signal; a cascade output; and first test enabling circuitry for testing the first tristate cell when in a testing mode; a second block having at least a second tristate cell including: a second enable input for receiving a second enable signal; a second data input for receiving data; a second data output in communication with the data bus; second cascade circuitry having a second cascade input for accepting a second test signal, the second cascade circuitry also accepting the second enable signal; a cascade input operatively connected to the cascade output of the first cascade circuitry; and second test enabling circuitry for testing the second tristate cell when in a testing mode; the circuitry being configured to operate in the testing mode when a test enable signal is operative, and wherein if the first enable signal is supplied to the first enable input and the test enable signal is operative, the first cascade circuitry outputs a cascade out signal to the second cascade input via the cascade output thus causing the second cascade circuitry to disable the enable input of the second tristate cell, thereby to prevent contention on the data bus during scan testing.