Patent ID: 8493774

Claim:
A circuit structure for performing a logic function within a memory, comprising: a first transistor that receives a read word line signal, wherein, upon receiving the read word line signal, the first transistor provides a path from a second transistor to a read bit-line and a path from a third transistor to the read bit-line; the second transistor that, in response to a first memory cell within the memory storing a first value, turns on and provides a first path to ground thereby causing a first output value to be output on the read bit-line; the third transistor that, in response to a second memory cell physically adjacent to the first memory cell within the memory storing a second value, turns on and provides a second path to ground thereby causing a second output value to be output on the read bit-line; and in response to the first memory cell and the second memory cell each storing a third value, the second transistor and the third transistor both turn off thereby preventing a path to ground such that a third output value is output on the read bit-line.