Patent ID: 8527834

Claim:
An information processing device for implementing error control including at least one of error detection and error correction, the device comprising: an information bit sequence acquiring unit for acquiring an information bit sequence; an encoder for generating a redundant bit sequence enabling execution of error control of the entire information bit sequence, the redundant bit sequence including a first bit sequence that consists of at least one bit that functions as a parity bit for one of a plurality of divided information bit sequences produced by dividing the information bit sequence, the redundant bit sequence being generated through a single encoding by a predetermined code based on the information bit sequence, and for generating a codeword that includes the information bit sequence and the redundant bit sequence; and a transfer unit for dividing the codeword into a plurality of successive unit transfers and transferring each of said unit transfers to a transfer destination, wherein each of said unit transfers includes a divided information bit sequence and a bit functioning as the parity bit for a division of the information bit sequence; and wherein the transfer unit transfers one of said unit transfers to one transfer destination and transfers another one of said unit transfers to another transfer destination.