Patent ID: 7130003

Claim:
A thin film transistor (TFT) array substrate, comprising: a substrate; a gate wiring pattern formed on the substrate and comprising a plurality of gate lines and a plurality of gate electrodes; a common wiring pattern formed on the substrate and comprising a plurality of common signal lines and a plurality of common electrodes; a plurality of redundant lines formed on the substrate, the plurality of redundant lines disposed on the same layer as the plurality of gate lines; a gate insulating layer covering the gate lines and the common electrode lines and having a plurality of contact holes exposing the redundant lines; a semiconductor layer formed on the gate insulating layer; a data wiring pattern comprising a plurality of data lines, a plurality of source electrodes and a plurality of drain electrodes, the data lines being connected to the redundant lines; and a plurality of pixel electrodes connected to the drain electrodes and proceeding parallel to the common electrodes.