Patent ID: 8094483

Claim:
A semiconductor device comprising: a first read/write amplifier; a second read/write amplifier; a first group of bit lines belonging to the first read/write amplifier; a second group of bit lines belonging to the second read/write amplifier and mixed with the first group of bit lines; a selection circuit designating one of the first group of bit lines and one of the second group of bit lines respectively to a first selected bit line and a second selected bit line in parallel to each other while designating remaining ones of the first group of bit lines and remaining ones of the second group of bit lines respectively to first non-selected bit lines and second non-selected bit lines, and a control circuit supplying a reference potential to at least one of the first non-selected bit lines, which is adjacent to the first selected bit line, and to at least one of the second non-selected bit lines, which is adjacent to the second selected bit line, and bringing at least one of remaining ones of the first and second non-selected bit lines into a floating state.