Patent ID: 8413016

Claim:
A nonvolatile memory controller comprising: an error-correcting code generator that generates an error-correcting code when data is written into a nonvolatile memory; an error detection and correction portion that detects an error in data including the error-correcting code and corrects the error when data is read from the nonvolatile memory; a nonvolatile buffer memory that temporarily stores data to be written into the nonvolatile memory and data read from the nonvolatile memory; a scrambler that scrambles data to be written with a scramble pattern generated by a scramble pattern generator when the data to be written is transferred between the nonvolatile memory and the buffer memory; and a control portion that controls each of the error-correcting code generator, the error detection and correction portion, the nonvolatile buffer memory and the scrambler, wherein when data is written into each write unit of the nonvolatile memory, the control portion controls so that the scrambled data to be written, a written flag serving as a bit pattern that differs from write unit to write unit, and the error-correcting code generated by the error-correcting code generator based on the scrambled data to be written and the written flag are written, and when data of each write unit is read from the nonvolatile memory, the control portion decides whether data is normal or anomalous by judging whether a written flag area of the data after an error is corrected by the error detection and correction portion has the bit pattern corresponding to the data of each write unit read from the nonvolatile memory.