Patent ID: 7289593

Claim:
A shift register comprising: an input terminal and an output terminal; first and second clock terminals to which first and second clock signals are input, respectively, said first and second clock signals being shifted in phase from each other; first, second and third voltage terminals to which first, second and third voltages are applied, respectively; a first transistor connected between said output terminal and said first clock terminal; a second transistor connected between said output terminal and said first voltage terminal; a first node to which a control electrode of said first transistor is connected; a second node to which a control electrode of said second transistor is connected; and a driving section for applying said first voltage to said first node and a voltage corresponding to said third voltage to said second node in synchronization with said second clock signal, while applying a voltage corresponding to said second voltage to said first node and said first voltage to said second node in response to an input signal input to said input terminal, wherein said driving section includes a compensation circuit for charging said second node to a level at which a conducting state of said second transistor is kept in synchronization with said first clock signal during a period in which said second transistor is in the conducting state.