Patent ID: 7382667

Claim:
A computer system, comprising: an integrated circuit processor having a plurality of externally accessible terminals coupled to a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and an integrated circuit memory device having a plurality of externally accessible terminals coupled to the processor bus of the integrated circuit processor; and an active termination circuit coupled to a first plurality of the externally accessible terminals, the active termination circuit comprising: a respective first controllable impedance device coupled between a first supply voltage and each of the externally accessible terminals in the first plurality, the impedance of the first controllable impedance device being controlled by an impedance control signal; a second controllable impedance device coupled between a second supply voltage and a feedback node, the second controllable impedance device being a different controllable impedance device from the first controllable impedance devices, and the feedback node being different from the externally accessible terminals in the first plurality, the impedance of the second controllable impedance device being controlled by the impedance control signal; a predetermined resistance coupled between the feedback node and a third supply voltage, the second controllable impedance device and the predetermined resistance forming a voltage divider between the second and third supply voltages to produce a feedback voltage at the feedback node; and a circuit generating the impedance control signal as a function of the feedback voltage so that magnitude of the feedback voltage is substantially constant.