Patent ID: 7247902

Claim:
A semiconductor device comprising: (a) a semiconductor memory composed of a memory cell portion and a peripheral circuit portion and formed on a semiconductor substrate, (b) a plurality of word lines and a plurality of bit lines disposed in a matrix form in the memory cell portion; (c) a logic circuit on the semiconductor substrate; (d) a capacitive element in the memory cell portion comprising an upper electrode and a memory node electrode; (e) a first metal layer comprising a buried metal layer embedded within a connecting hole passing through first and second insulating films; (f) a first metal wiring layer connected to the first metal layer; (g) first and second insulating layers sandwiching the first metal wiring layer from above and below, the first metal wiring layer being formed on and in contact with the first insulating layer and the second insulating layer covering the first metal wiring layer, the first metal wiring layer being connected to a diffusion layer via the first metal layer, the logic circuit being connected to one or both of the diffusion layer formed in the semiconductor substrate and a lower-layer wiring on the semiconductor substrate, the diffusion layer extending obliquely across adjacent word lines; (h) a second metal layer comprising a buried metal layer embedded within a connecting hole passing through a portion of the second insulating and connected to the first metal wiring layer; (i) a second metal wiring layer that is formed on an insulating layer located above the capacitive element in such a way as to be connected to the second metal layer; and (j) a dielectric layer being formed in the interior of a groove and on an insulating layer, the groove being formed in the first and second insulating layers and in the memory cell portion, a comb-like plate electrode covering the dielectric layer, the plate electrode does not extend beyond the capacitive element, the plate electrode being formed on the second insulating layer, wherein, the capacitive element being formed in the groove and extending through the first and second insulating layers, and a top portion of the second insulating layer being in the same horizontal plane as an upper surface of the memory node electrode.