Patent ID: 8730992

Claim:
A system for transmitting network packets, comprising: an information module, receiving and recording media information of a plurality of multimedia streams provided by a first media server and a second media server, wherein the media information comprises a frame rate and a frame size of each of the multimedia streams; a scheduling module, calculating a guaranteed bit rate of each of the multimedia streams according to the frame rate and the frame size, rearranging isochronous packets of the multimedia streams in first time slots of a plurality of clock cycles according to the guaranteed bit rates so that the transmission of the isochronous packets satisfies the guaranteed bit rates of all of the multimedia streams, determining a transmitting sequence of the isochronous packets in each of the clock cycles according to the guaranteed bit rate of each of the multimedia streams such that each of the clock cycles includes the isochronous packets provided by both of the first media server and the second media server, and using a linked list to link the isochronous packets provided by the first media server in each of the clock cycles according to the transmitting sequence, wherein a length of each of the clock cycles is a predetermined length, a length of the first time slot and the predetermined length are in a predetermined ratio; and a forwarding module, transmitting all the packets of a current one of the clock cycles provided by the first media server to a network according to the transmitting sequence at every a time interval of the predetermined length, wherein the isochronous packets provided by the first media server transmitted in each even one of the clock cycles are more than the isochronous packets provided by the first media server transmitted in each odd one of the clock cycles, and the isochronous packets provided by the second media server transmitted in each odd one of the clock cycles are more than the isochronous packets provided by the second media server transmitted in each even one of the clock cycles.