Patent ID: 8341332

Claim:
A multi-level-control multi-flash device comprising: a smart storage switch which comprises: an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned single-chip flash-memory device to generate a logical block address (LBA), the virtual storage processor performing a first level of mapping wherein the virtual storage processor is able to map the host address to any single-chip flash-memory device as the assigned single-chip flash-memory device; a virtual storage bridge between the smart storage transaction manager and a LBA bus; a volatile memory buffer, coupled to the virtual storage processor, for temporarily storing the host data in a volatile memory that loses data when power is disconnected; a plurality of single-chip flash-memory devices that include the assigned single-chip flash-memory device, wherein a single-chip flash-memory device comprises: a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; a lower-level volatile memory buffer, in the NVM controller, for temporarily storing the host data in a local volatile memory that loses data when power is disconnected; a second-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA); and non-volatile memory blocks, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the second-level mapper in the NVM controller; whereby address mapping is performed at two levels to access the non-volatile memory blocks.