Patent ID: 8560797

Claim:
An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising: an interface to transmit: over a first plurality of wires, to the DRAM: a first code to indicate that first data is to be written to the DRAM, wherein the first code is to be registered by the DRAM at one or more edges of an external clock signal received by the DRAM; a column address to indicate a column location of a memory core in the DRAM where the first data is to be written, wherein the column address is to be registered by the DRAM at one or more edges of the external clock signal; a second code to indicate whether mask information for the first data will be sent to the DRAM, the second code being sent over a subset of wires of the first plurality of wires, wherein: the mask information indicates whether certain portions of the first data is to be transmitted to the DRAM; and if the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent over the subset of wires after the second code is sent over the subset of wires, wherein the mask information is to be registered by the DRAM at one or more edges of the external clock signal; and over a second plurality of wires separate from the first plurality of wires, to the DRAM, the first data.