Patent ID: 8652882

Claim:
A chip packaging method, comprising the steps of: patterning a first surface of a metal plate to form a plurality of leadframes, each leadframe comprising a recess and two lead groups disposed on opposite sides of the recess, wherein each lead group comprises a plurality of terminal pads arranged in at least two rows spaced apart from each other in a direction away from the recess, and a plurality of leads each including a first end portion adjacent to the recess and a second end portion connecting to a corresponding one of the terminal pads; forming a dielectric layer between the terminal pads and the leads, wherein the recess and the first end portions of the leads are exposed from the dielectric layer; removing a second surface of the metal plate opposite to the first surface until a central void region is formed at the recess and the plurality of terminal pads and the plurality of leads are isolated from one another; attaching a first chip to one of the plurality of leadframes, the leadframe comprising a first surface and a second surface respectively corresponding to the first and second surfaces of the metal plate, the first chip having an active surface, a rear surface opposite the active surface, and a plurality of bond pads disposed on the active surface, wherein the active surface of the first chip is attached to the second surface of the leadframe with the bond pads corresponding to the central void region; and electrically connecting the bond pads of each of the first chips to the first surface of the leadframe at the first end portions of the corresponding leads with a plurality of first bonding wires through the central void region.