Patent ID: 7236032

Claim:
A circuit, comprising: a state retention circuit to receive a mode selection signal and having a first output to output a first output signal and a second output to output a second output signal, with said first output signal comprising an inverse of said second output signal; a first inverter to receive said first output signal and having a third output to output a third output signal; a second inverter to receive a first input signal and having a fourth output to output a fourth output signal; and first, second and third transistors, said first transistor having a gate coupled to a gate for said second transistor, said commonly coupled gates of said first and second transistors to receive a second input signal, said first transistor further having a drain coupled to said first output and a source coupled to said fourth output, with said second transistor having a drain coupled to said second output and a source coupled to a drain for said third transistor, said third transistor having a gate coupled to said fourth output.