Patent ID: 6958632

Claim:
A circuit comprising: a signal input coupled to receive a signal; a buffer circuit coupled to receive the signal and to generate a buffer circuit output; and a voltage following circuit comprising a first amplifier coupled to a first transistor and a second amplifier coupled to a second transistor, the voltage following circuit coupled to receive the signal and to generate a voltage following output wherein the buffer circuit output and the voltage following circuit output are coupled to a circuit output node, wherein the first amplifier comprises a positive input, a negative input and an output, and the first transistor comprises an NMOS transistor including a gate, a source and a drain, the positive input of the first amplifier being coupled to receive the signal, the negative input of the first amplifier being coupled to the source of the NMOS transistor, the output of the first amplifier being coupled to the gate of the NMOS transistor, the drain of the NMOS transistor being coupled to a positive supply voltage, and the source of the NMOS transistor being coupled to the circuit output node, and wherein the second amplifier comprises a positive input, a negative input and an output, and the second transistor comprises a PMOS transistor, including a gate, a source and a drain, the positive input of the second amplifier being coupled to receive the signal, the negative input of the second amplifier being coupled to the source of the PMOS transistor, the output of the second amplifier being coupled to the gate of the PMOS transistor, the drain of the PMOS transistor being coupled to a supply voltage less than the positive supply voltage, and the source of the PMOS transistor being coupled to the circuit output node.