Patent ID: 7750691

Claim:
A clock driver circuit comprising: a first upper transistor and a first lower transistor providing a first set of complementary transistors; a second upper transistor and a second lower transistor providing a second set of complementary transistors; a first voltage supply node coupled to both an electrode of the first upper transistor and an electrode of the second upper transistor; a second voltage supply node coupled to both an electrode of the first lower transistor and an electrode of the second lower transistor; a first coupling transistor selectively coupling another electrode of the first upper transistor to another electrode of the second lower transistor; a second coupling transistor selectively coupling another electrode of the second upper transistor to another electrode of the first lower transistor; two first series connected capacitors coupling the another electrode of the first upper transistor to the another electrode of the first lower transistor; two second identical series connected capacitors coupling the another electrode of the second upper transistor to the another electrode of the second lower transistor; an in-phase clock signal output provided by a node intermediate the two second series connected capacitors; an anti-phase clock signal output provided by a node intermediate the two first series connected capacitors; an in-phase clock signal input coupled to control inputs of the first upper transistor, the first coupling transistor and the first lower transistor; and an anti-phase clock signal input coupled to control inputs of the second upper transistor, the second coupling transistor and the second lower transistor.