Patent ID: 6897793

Claim:
An encoder configured to receive a data word sequence of N-bit data words and to generate a code word sequence of M-bit code words by encoding the data words, where M>N, said encoder including: candidate code word generation circuitry configured to generate an M-bit, transition-minimized, candidate code word in response to each N-bit data word of the data word sequence; and logic circuitry coupled to the candidate code word generation circuitry and configured to generate the code word sequence, including by determining whether a current candidate code word concatenated with at least one previously generated bit of the code word sequence includes a run of length in excess of a predetermined value, where the current candidate code word is one said candidate code word, to include the current candidate code word in the code word sequence in response to determining that the current candidate code word concatenated with said at least one previously generated bit of the code word sequence includes no run of length in excess of the predetermined value, and to include an M-bit substitute code word that corresponds to the current candidate code word in the code word sequence rather than the current candidate code word in response to determining that the current candidate code word concatenated with the at least one previously generated bit of the code word sequence includes a run of length in excess of the predetermined value, whereby the code word sequence is a run length limited code word sequence including no run of length in excess of the predetermined value.