Patent ID: 6891542

Claim:
An image processing integrated circuit, comprising: a CPU configured to supply an image data, frame information of the image data and a first write destination address indicating an address to which the image data is written; a latch circuit configured to receive the frame information from the CPU; an address scrambler configured to allocate second write destination addresses based on the first write destination address supplied from the CPU and the frame information supplied from the latch circuit; a RAM configured to store the image data supplied from the CPU according to the second write destination address supplied from the address scrambler; and a DA converter configured to perform the digital-analog conversion for the image data supplied from the RAM and to supply a first read destination address corresponding to the first write destination address one to one, to the address scrambler after the conversion, wherein the address scrambler allocates the second write destination addresses by taking the frame information as an upper bit, and the first write destination address as a lower bit.