Patent ID: 6845443

Claim:
A method for processing data in a processor having a processor core for processing a command in a pipeline form, a program counter for storing a memory address of a command to be fetched, decoded and executed by the processor core; a program counter generation logic for increasing a program counter value and outputting it to the program counter; and a memory for storing a program including a repeat block, comprising the steps of: (i) setting a repeat count value; (ii) executing a repeat block command to set a repeat ending address and a repeat starting address, and decoding a first command of the repeat block and fetching a second command of the repeat block; (iii) comparing the repeat ending address and a memory address of the second command to identify whether they are identical to each other; (iv) checking whether the first command is a command for nonlinearly changing an executing order of a program only if the repeat ending address and the memory address of the second command are identical to each other.