Patent ID: 7078787

Claim:
A method comprising: selecting a varactor that comprises (a) a plate region and a body region of a semiconductor body, (b) a plate electrode and a body electrode respectively connected to the plate and body regions, (c) a gate dielectric layer situated over the semiconductor body and contacting the body region, and (d) a gate electrode situated over the gate dielectric layer at least where the gate dielectric layer contacts material of the body region, the plate and body regions being of opposite conductivity types, meeting each other to form a p-n junction, and extending to a primary surface of the semiconductor body, the plate region occupying a lateral plate area along the primary surface, the varactor having a minimum capacitance dependent on the plate area, an inversion layer that meets the plate region occurring in the body region and occupying a lateral inversion area along the primary surface, the inversion area reaching a maximum value when the inversion layer is fully present, the varactor having a maximum capacitance dependent on the maximum inversion area in combination with the plate area, the plate electrode being at a plate-to-body voltage relative to the body electrode, the gate electrode being at a gate-to-body voltage relative to the body electrode, the inversion layer comprising multiple variably appearing inversion portions respectively characterized by corresponding different zero-point threshold voltages of like sign, each inversion portion appearing/disappearing when the gate-to-body voltage passes through the corresponding zero-point threshold voltage with the plate-to-body voltage at zero, each inversion portion meeting the plate region or/and being continuous with the another inversion portion whose zero-point threshold voltage is of lower magnitude than the zero-point threshold voltage of that inversion portion; and adjusting the plate and maximum inversion areas to control the maximum and minimum capacitances of the varactor.