Patent ID: 8217380

Claim:
A memory cell comprising: a substrate comprised of silicon; an insulating region comprising insulating material above the substrate; a base layer comprised of a first semiconductor material below at least a part of the insulating region and at the top of the substrate; an emitter layer comprised of a second semiconductor material above the base layer and contained within the insulating region, the second semiconductor material being substantially polycrystalline silicon; a plug comprised of conductive material above the emitter layer such that the emitter layer is positioned between the plug and the base layer, the plug contained within the insulating region; a phase change element comprised of phase change material above the plug and contained within the insulating region; and a top electrode layer comprised of conductive material above the phase change element and contained within the insulating region; wherein the substrate forms a collector of a bipolar junction transistor (BJT), the BJT including the base layer forming a base of the BJT and the emitter layer forming an emitter of the BJT.