Patent ID: 7928888

Claim:
A pipeline time-to-digital converter (TDC), comprising: a plurality of TDC cells, connected in series, and each of the TDC cells comprising: a delay unit, receiving a first clock signal and a first reference signal output from a previous stage TDC cell, generating a plurality of sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and sampling the first clock signal to obtain a plurality of sampling values according to the sampling phases; an output unit, coupled to the delay unit, for receiving the sampling values, and calculating the sampling values to output a conversion value; and a determination unit, coupled to the delay unit, for receiving the sampling values and the sampling phases, selecting a sampling phase corresponding to the trigger edge of the first clock signal from the sampling phases to serve as a second reference signal, generating a pulse according to the trigger edge of the first clock signal to serve as a second clock signal, and outputting the second reference signal and the second clock signal to a next stage TDC cell.