Patent ID: 7088148

Claim:
A sample and hold circuit comprising: first means for receiving an input current, said first means including a first transistor wherein the input current is received via the base of the first transistor; second means for sampling and for holding said input current, said second means switching from a sampling mode for sample said input current to a holding mode for holding said input current in response to a control signal, said second means including a second transistor; and third means for stabilizing said input current as said second means switches from a sampling mode to a hold mode thereof in response to said control signal, said third means including a third transistor, a fourth transistor, and a fifth transistor, wherein the base of the third transistor receives the input current, wherein the emitters of the third transistor and the first transistor are operatively coupled to the collectors of the fourth transistor and the fifth transistor, respectively, and wherein the emitters of the fourth transistors and the fifth transistor are commonly coupled to a current source, and wherein, during the switching of a sample mode to a hold mode by said second means, said third means stabilizes the input current by charging the base current of the third transistor while the base current of the first transistor is discharging.