Patent ID: 7154129

Claim:
A semi-conductor system with a p-n junction diode formed as a chip having an edge area, the system comprising: a first layer of a first conductivity type, wherein an outer edge of the first layer defines an outer edge of the edge area of the diode; and a second layer of a second conductivity type that is contrary to the first conductivity type, wherein the second layer is juxtaposed with the first layer, wherein: the second layer includes at least a first sublayer and a second sublayer, the first sublayer includes a first dopant concentration, the second sublayer includes a second dopant concentration, the second dopant concentration is less than the first dopant concentration, the first sublayer and the second sublayer form a p-n junction with the first layer, the p-n junction of the first layer with the first sublayer is provided exclusively in an interior of the diode, the p-n junction between the first layer and the second sublayer is provided in the edge area of the diode, and for each cross-section of the chip taken along a plane extending parallel to a planar surface of the chip, the first sublayer is diffused in as a patterned sublayer doped with the second conductivity type, wherein the first conductivity type is p and the second conductivity type is n, and the first sublayer lies only in the inner part of each of the cross-section, whereby a p-n junction between the first sublayer having the higher first dopant concentration of n conductivity type and the first layer of the p conductivity type lies only in the inner part of the chip, and wherein the first sublayer includes a pedestal portion.