Patent ID: 8407528

Claim:
An electronic circuit comprising: a first processor operable to perform processing operations; a first trace buffer coupled to said first processor; a first triggering circuit coupled to said first processor, said first triggering circuit operable to detect a specified sequence of particular processing operations in said first processor; a second processor; a second trace buffer coupled to said second processor; a second triggering circuit coupled to said second processor, said second triggering circuit operable to detect at least one other processing operation in said second processor; and a cross trace circuit having a trace output and having inputs coupled to said first triggering circuit and to said second triggering circuit, said cross trace circuit configurably operable to respond to a sequence including both a detection of the sequence of particular processing operations of said first processor by said first triggering circuit and a detection of the at least one other processing operation of said second processor by said second triggering circuit, to couple at least one of said first trace buffer and said second trace buffer to said trace output, wherein said first and second triggering circuits and said cross trace circuit each include a configurable state machine circuit.