Patent ID: 7727817

Claim:
A method of packaging a semiconductor integrated circuit, comprising: providing a lead frame array having a front surface and a back surface opposite to said front surface, each lead frame in said lead frame array including leads and die pads, and on the front surface of said lead frame array, semiconductor chips are attached to corresponding die pads respectively, and pads on said semiconductor chips and corresponding leads of said lead frame are connected by wires; attaching a tape to the back surface of said lead frame array; holding said lead frame array between an upper mold chase and a lower mold chase of a mold, with the back surface of said lead frame array upward, said upper mold chase and said lower mold chase forming an upper cavity and a lower cavity with respect to said lead frame array respectively; injecting a mold compound into said upper cavity and said lower cavity respectively, wherein with respect to clearances between the leads, between the die pads and/or between the leads and the die pads, the mold compound injected into said upper cavity covers the portion of said tape over said clearances before the mold compound injected into said lower cavity fills said clearances, so that said tape is depressed; curing the mould compound after the mold is filled with the mould compound, then removing the mold; and removing said tape from the back surface of said lead frame array.