Patent ID: 7982266

Claim:
A dielectrically isolated semiconductor device comprising: a semiconductor substrate; a first insulation film formed on one side of the semiconductor substrate; and a first doped semiconductor layer formed on the first insulation film; wherein: the first doped semiconductor layer is deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, the first doped semiconductor layer includes an active device region in which an element is formed and an element isolating region which encloses the active device region, the element isolating region is provided with a plurality of trenches coming into contact with the first insulation film and structured to form a two-dimensional closed loop, and each of the trenches is filled with second doped layers, doped with n-type impurities and doped more heavily than the first doped semiconductor layer, and second insulation films each adjacent to one of the second doped layers, wherein the element isolating layer has an n-multiple structure including the plurality of trenches, and further comprising polycrystalline semiconductor layers, the second insulation layers adjacent to each side of the polycrystalline semiconductor layer, and the second doped layers, respectively, adjacent to each side of the second insulation layers, said adjacent layers comprising n-multiple polycrystalline silicon layers, 2n-multiple second insulation layers and (n+1)-multiple second doped layers.