Patent ID: 7388399

Claim:
A source of an alternating voltage for biasing a keeper, the alternating voltage alternating between a first supply voltage and a second supply voltage, the source comprising: an output connected to the keeper; an input for receiving a clock; a first supply voltage circuit connected between the first supply voltage and the output to supply the first supply voltage to the output; a second supply voltage circuit connected between the second supply voltage and the output to supply the second supply voltage to the output; a first transistor, connected to the clock without inversion, for selectively activating the first supply voltage circuit in accordance with the clock; an inverter, connected to the clock, for outputting an inverted clock; a second transistor, connected to the inverter, for selectively activating the second supply voltage circuit in accordance with the inverted clock; a first node; a second node; and a third node, wherein: the first transistor is connected between the first node and ground and is gated by the clock; the second transistor is connected between the second node and ground and is gated by the inverted clock; the first circuit comprises a third transistor connected between the first supply voltage and the third node and a fourth transistor connected between the second supply voltage and the second node, the third and fourth transistors being gated in accordance with a signal from the first node; the second circuit comprises a fifth transistor connected between the second supply voltage and the first node and a sixth transistor connected between the second supply voltage and the third node, the fifth and sixth transistors being gated in accordance with a signal from the second node; and the output is connected between the third node and the keeper.