Patent ID: 6859378

Claim:
A multiple match gate, comprising: a first pull-down path defined by a first NMOS transistor having a gate terminal that is configured to receive a not any match signal NAM0 and a second NMOS transistor having a gate terminal that is configured to receive a not multiple match signal NMM1; a second pull-down path defined by third NMOS transistor having a gate terminal that is configured to receive a not any match signal NAM1 and a fourth NMOS transistor having a gate terminal that is configured to receive a not multiple match signal NMM0; a first pull-up path defined by a first PMOS transistor having a gate terminal that is configured to receive the not multiple match signal NMM0; a second pull-up path defined by a second PMOS transistor having a gate terminal that is configured to receive the not multiple match signal NMM1; a third pull-up path defined by a third PMOS transistor having a gate terminal that is configured to receive the not any match signal NAM0 and a fourth PMOS transistor having a gate terminal that is configured to receive the not any match signal NAM1; and a multiple match flag (MMF) terminal that is electrically connected to said first and second pull-down paths and said first, second and third pull-up paths so that the following boolean expression is satisfied: MMF=NOT (( NMM 0 ×NAM 1)+( NAM 0 ×NMM 1)).