Patent ID: 8314885

Claim:
An image-clock adjusting circuit, comprising: a phase comparator receiving a power source signal and a vertical synchronous signal and comparing a phase of the power source signal with that of the vertical synchronous signal for producing at least a phase comparison signal; a clock controller receiving the phase comparison signal, the vertical synchronous signal and a main clock signal, producing a pixel clock signal, and intermittently adjusting a clock width of the pixel clock signal to produce an adjusted pixel clock signal; and a timing generator receiving the pixel clock signal and adjusting the vertical synchronous signal into an adjusted vertical synchronous signal being nearly in phase with the power source signal, wherein: the main clock signal has a first transition edge, a second transition edge lagged behind the first transition edge by a first integer of transition edges, and a third transition edge lagged behind the second transition edge by a second integer of at least one transition edge, wherein the first integer is different from the second integer; the adjusted pixel clock signal has a first cycle and a second cycle adjacent to the first cycle; the first cycle has a first width corresponding to a width between the first and the second transition edges; and the second cycle has a second width corresponding to a width between the second and the third transition edges.