Patent ID: 7197439

Claim:
A method for modeling a semiconductor device process, comprising: (a) setting data of an SiO 2 layer; (b) setting data of an Si layer brought in contact with said SiO 2 layer; (c) setting a plurality of cells in said Si layer, and setting an amount of an impurity included in each of said cells; (d) setting an amount per unit time by which said impurity included in each of said cells moves to another cell; (e) setting data by which a cell in a vicinity of an interface of said SiO 2 layer and said Si layer is set as an impurity pileup portion; (f) setting data of a position of a source or a drain in said Si layer; and (g) calculating the amount of said impurity included in each of said cells for each unit time after processing said steps (a) through (f), wherein an amount of said impurity in each of said cells moving to said impurity pileup portion from each of said cells is determined as an impurity density as a function of a distance r 1 to said impurity pileup portion from each of said cells, and a function of a distance r 2 to said source or said drain from each of said cells, wherein the function of the distance r 1 is exp(− r 1/λ1), wherein the function of the distance r 2 is exp(− r 2/λ2), and wherein λ 1 , λ 2 are source and drain process dependent parameters, wherein λ 1 =2.0 μm and λ 2 =0.5 μm.