Patent ID: 8385130

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a row and a column, the memory cell array includes a plurality of pages and each page contains the memory cells arranged in the row; a plurality of data storage circuits connected to the memory cell array, each of the data storage circuits configured to store at least one data; and a control circuit configured to control the operation of the data storage circuits, wherein the control circuit writes data to the memory cell when data stored in the data storage circuit is a first logic level and, does not write data to the memory cell when the data stored in the data storage circuit is a second logic level, and wherein when a page copying operation is performed, the control circuit reads data from the memory cell and stores the data to the data storage circuit, the data of the data storage circuit is the first logic level when data has been written to the memory cell in the write operation and, the data of the data storage circuit is the second logic level when data has not been written to the memory cell in the write operation.