Patent ID: 7687336

Claim:
A method of forming a high voltage MOSFET for an integrated circuit, the method comprising: forming a relatively thin layer of dielectric on a surface of a substrate; depositing a gate material layer on the relatively thin layer of dielectric; removing portions of the gate material layer to form first and second gate material regions of predetermined lateral lengths; introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, wherein the top gate is formed adjacent the surface of the substrate and laterally between the first and second gate material regions; introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein the second gate material region is positioned laterally between the drain region and the top gate; and wherein the spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.