Patent ID: 8114708

Claim:
A method of forming an embedded chip package comprising: providing an initial polymer laminate layer; patterning the initial polymer laminate layer to include a plurality of vias and a plurality of metal interconnects, such that each of the plurality of metal interconnects extends down through a respective via; laminating a plurality of additional polymer laminate layers to the initial polymer laminate layer to form a laminate stack; patterning each of the additional polymer laminate layers to include a plurality of vias and a plurality of metal interconnects; cutting a die opening through the laminate stack; adhering the laminate stack to a base unpatterned polymer laminate layer; adhering a die to the base unpatterned polymer laminate layer, the die positioned within the die opening of the laminate stack; and patterning the base unpatterned polymer laminate layer to include a plurality of vias and a plurality of metal interconnects, so as to electrically connect the base unpatterned polymer laminate layer to the die and to the laminate stack.