Patent ID: 8416115

Claim:
A successive approximation register-analog digital converter comprising: an input terminal to which an input voltage is applied; a reference terminal to which a reference voltage is applied; a first capacitor set comprising a first capacitor and a second capacitor, the first capacitor having a first capacitance, the second capacitor having a second capacitance being double a sum of the first capacitance and a parasitic capacitance being parasitic in the first capacitor set; a second capacitor set comprising the first capacitor and the second capacitor; a dummy capacitor having a third capacitance being less than the second capacitance and located between the second capacitor of the second capacitor set and a ground; a comparator configured to compare an output voltage corresponding to charges charged in the first capacitor of the first capacitor set and the second capacitor of the first capacitor set with a ground voltage, and output a digital output code in accordance with a difference between the output voltage and the ground voltage; a plurality of switches, each of the switches being connected to the first capacitor of the first capacitor set, the first capacitor of the second capacitor set, and the reference terminal; and a logic circuit configured to turn on and turn off the switches based on the digital output code to control the output voltage, wherein the input terminal is located between the first capacitor of the first capacitor set and the second capacitor of the first capacitor set, and the second capacitor of the first capacitor set is located between the first capacitor of the second capacitor set and the second capacitor of the second capacitor set.