Patent ID: 8809828

Claim:
A phase change memory cell in a semiconductor wafer, the semiconductor wafer including a first metalization layer (Metal 1), the phase change memory cell comprising: an insulating substrate defining a non-sublithographic via, the non-sublithographic via located on the first metalization layer and including a bottom and a sidewall; intermediate insulating material positioned below the insulating substrate, the intermediate insulating material defining a sublithographic aperture passing through the bottom of the non-sublithographic via; a bottom electrode positioned within the sublithographic aperture, the bottom electrode composed of conductive non-phase change material; phase change material positioned within the non-sublithographic via and electrically coupled to the bottom electrode; and a liner positioned along the sidewall of the non-sublithographic via and electrically coupled to the phase change material, the liner composed of the conductive non-phase change material.