Patent ID: 7122429

Claim:
A method of manufacturing a semiconductor memory having a memory cell array region and peripheral circuit region, comprising: forming a first insulating film on a semiconductor substrate in the memory cell array region and peripheral circuit region; forming, on the first insulating film, a conductive layer which at least partially includes a silicon layer, and a second insulating film; forming a gate electrode by patterning the conductive layer and second insulating film into a gate electrode shape; forming a first oxide film by annealing side surfaces of the conductive layer included in the gate electrode and a surface of the semiconductor substrate in an oxidizing ambient; forming a first nitride film on an entire surface; patterning the first nitride film such that the first nitride film is removed from the memory cell array region and left behind in the peripheral circuit region; forming a second oxide film by annealing side surfaces of the conductive layer included in the gate electrode and a surface of the semiconductor substrate in the memory cell array region in an oxidizing ambient, while the peripheral circuit region is covered with the first nitride film the second oxide film having a film thickness smaller than that of said first oxide film; etching the first nitride film remaining in the peripheral circuit region to leave the first nitride film behind on side surfaces of the gate electrode in the peripheral circuit region; forming a second nitride film on an entire surface the second nitride film having a film thickness larger than that of said first nitride film; and etching the second nitride film to leave the second nitride film behind on the side surfaces of the gate electrodes in the memory cell array region and peripheral circuit region.