Patent ID: 7913143

Claim:
A test quality evaluating and improving system for a semiconductor integrated circuit, comprising: a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with the undetected fault as a weight of the undetected fault which cannot be detected by a test pattern for testing the faults; a test quality measure calculating section which multiplies the weight of the undetected fault, the failure mode-fault model correlation factor for correlating the failure mode of the layout element and the fault model, and the failure occurrence rate of each layout element, and outputs an obtained product as a failure remaining rate of the test pattern; a determining section which determines whether the failure remaining rate is not larger than a target value; and a test point inserting section which inserts, when the determining section determines that the failure remaining rate is larger than the target value, a test point into a logical net of the circuit to be tested, the test point being inserted to preferentially detect an undetected fault having a large weight based on the weighted fault dictionary.