Patent ID: 7544566

Claim:
A self-aligned method for manufacturing an electrically alterable memory device on a semiconductor layer having a top side, comprising the steps of: growing an insulating layer on the top side of the semiconductor layer; depositing a first conductive layer on the insulating layer, the first conductive layer having a top side; forming a plurality of trench isolation regions along a first direction, a trench isolation region extending downwardly into the semiconductor layer; depositing a layer of a sacrificial material on the top side of the first conductive layer, the layer of the sacrificial material having a top side; etching the layer of the sacrificial material to form a plurality of isolation channels along a second direction, two adjacent isolation channels delimiting a block of the sacrificial material, the block of the sacrificial material having two lateral sides, a top, and a bottom; forming two gate masks along two lateral sides of the block of the sacrificial material, one gate mask on each lateral side; etching the first conductive layer to extend the plurality of isolation channels to the insulating layer, two adjacent isolation channels delimiting a block of the first conductive layer, the block of the first conductive layer being located under the block of the sacrificial material; etching the block of the sacrificial material to form a control channel; etching the block of the first conductive layer to form two lateral blocks of the first conductive layer under two gate masks, the two lateral blocks include a first lateral block and a second lateral block; and filling the control channel with a second conductive layer.