Patent ID: 8169022

Claim:
A semiconductor device comprising: an n-type semiconductor substrate; a drift layer of n-type semiconductor material on the substrate; a plurality of gate regions of p-type semiconductor material each having a graded dopant concentration on the drift layer, the gate regions having a lower surface adjacent the drift layer, an upper surface opposite the lower surface and sidewalls, wherein the dopant concentration in a lower portion of the gate regions adjacent the lower surface is less than the dopant concentration in an upper portion of the gate regions adjacent the upper surface; a channel layer of n-type semiconductor material on and between the plurality of gate regions in a central portion of the device, wherein the channel layer of n-type semiconductor material covers the plurality of regions of p-type semiconductor material in the central portion of the device, and wherein one or more gate regions are not covered by the channel layer in an inner peripheral portion of the device; a source layer of n-type semiconductor material on the channel layer; a first ohmic contact on the source layer; a second ohmic contact on one or more of the exposed gate regions in the peripheral portion of the device; a third ohmic contact on the substrate opposite the drift layer; and a metal layer on each of the first, second and third ohmic contacts.