Patent ID: 7324402

Claim:
A flash memory comprising: a plurality of global bit lines comprising a first global bit line; and a plurality of memory blocks each comprising: a plurality of local bit lines, the local bit lines comprising a first local bit line and a second local bit line; a plurality of memory units arranged in an array, each of the memory units comprising a first memory cell coupled to a first end, a second memory cell coupled to a second end, and a select switch coupled to a select line, the first memory cell, and the second memory cell, wherein the memory units comprise a plurality of first memory units, the first end of each of the first memory units being coupled to the first local bit line, and the second end of each of the first plurality memory units being coupled to the second local bit line; and a plurality of switches, the switches comprising a first switch, a second switch, a third switch and a fourth switch; wherein the first global bit line is coupled to the first local bit line through the first switch and coupled to the second local bit line through the second switch; the third switch is coupled between a first voltage source and the first local bit line; and the fourth switch is coupled between a second voltage source and the second local bit line.