Patent ID: 7271989

Claim:
Integrated circuit electrostatic discharge (ESD) protection circuitry on an integrated circuit for preventing current from flowing through a given circuit during an ESD event, wherein the integrated circuit has a first pin and a second pin, comprising: an ESD margin circuit connected between the first pin and the given circuit, wherein the given circuit is connected between the ESD margin circuit and the second pin; and a power ESD device connected between the first and second pins, wherein the power ESD device limits voltage levels between the first pin and second pin to a maximum voltage and draws current to protect the given circuit during the ESD event and wherein the ESD margin circuit ensures that no current flows through the given circuit even when the maximum voltage is across the first and second pins, wherein the given circuit comprises at least one fuse and wherein the ESD margin circuit comprises a p-channel metal-oxide-semiconductor transistor having a gate, a drain, a substrate terminal, and a source, wherein the gate is biased at a predetermined voltage level, the drain and substrate terminal are connected to the first pin, and the source is connected to the fuse.