Patent ID: 7671406

Claim:
A semiconductor device, comprising: a substrate; a non-volatile memory cell located in a first region of the substrate, the non-volatile memory cell including a first gate, an intergate dielectric located on the first gate, a second gate located on the intergate dielectric, sidewall spacers located on sidewalls of the second gate, and an insulation charge retention layer covering the second gate, the sidewall spacers and a portion of the intergate dielectric; and a logic transistor disposed on a second area of the substrate, said logic transistor including a logic gate disposed on a gate insulation layer, and a silicide layer, and wherein said insulation charge retention layer is a multi-layer film which terminates outside the second area of the substrate, and wherein a width of the second gate is less than a width of the first gate, wherein the second gate and the sidewall spacers are disposed on only a portion of the intergate dielectric such that another portion of the intergate dielectric is left exposed by the second gate and the sidewall spacers, and wherein the insulation charge retention layer directly contacts an upper surface of the second gate and the exposed portion of the intergate dielectric.