Patent ID: 7928786

Claim:
A clock buffer circuit of a semiconductor device comprising: a first clock buffer configured to receive and buffer a normal-phase clock signal; a second clock buffer configured to receive and buffer a reverse-phase clock signal; a first logic circuit for performing a logic operation with respect to an output signal from the first clock buffer; a second logic circuit for performing a logic operation with respect to an output signal from the second clock buffer; a first driver for performing a pull-up or pull-down driving operation in response to an output signal from the first logic circuit and an inverted version of an output signal from the second logic circuit; a second driver for performing the pull-up or pull-down driving operation in response to an inverted version of the output signal from the first logic circuit and the output signal from the second logic circuit; a first output unit for outputting an output signal from the first driver; and a second output unit for outputting an output signal from the second driver.