Patent ID: 8370708

Claim:
A data error measuring circuit for a semiconductor memory apparatus comprising: a data error correction unit configured to compare first and second data with first and second parity data and to generate first and second corrected data, respectively; a data selection unit configured to output the first and second data or the first and second corrected data as first and second selected data in response to a test selection signal; and a test result output unit configured to compare bits of the first and second selected data with bits of the first and second parity data in response to the test selection signal to output a test result signal, the test result output unit including: a first comparison section configured to detect an error in the first selected data and the first parity data in response to the test selection signal, and output the detection result as a first comparison signal; a second comparison section configured to detect an error in the second selected data and the second parity data in response to the test selection signal, and output the detection result as a second comparison signal; and a test result output section configured to output the test result signal in response to the first comparison signal and the second comparison signal when a read command is input.