Patent ID: 8176399

Claim:
A data processing system, the system comprising: A first detector, wherein the first detector is configured to perform a data detection iteration on an input data set; a short burst error detector, wherein the short burst error detector is configured for receiving an output from the first detector to generate a flag identifying a short burst error in the input data set, wherein the flag is configured produce a short burst error scaled output from the first detector; a second detector, wherein the second detector is configured to perform a second data detection iteration on the input data set; a decoder, wherein the decoder is configured to receive a derivation of an output from the second detector and a derivation of either an output from the first detector or the short burst error scaled output from the first detector, and wherein the output of the decoder includes both a hard output and a soft output; a queuing buffer, wherein the queuing buffer stores the soft output of the decoder corresponding to the input data set; wherein the first detector is configured to perform the first data detection iteration on the input data set using the output of the decoder only if the output of the decoder faired to converge, and wherein the first data detection iteration is subsequent to the second data detection iteration; wherein the short burst error detector is configured for receiving both the output from the first detector corresponding to the input data set and the output of the decoder corresponding to the input data set via the queuing buffer to generate a flag identifying a short burst error in the input data set; and an output data buffer, wherein the output data buffer stores the hard output whenever the output of the decoder converges.