Patent ID: 8531886

Claim:
A memory comprising: a NAND string including a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line using a bias arrangement having a first stage and a second stage, the biasing arrangement including: during the first stage, blocking flow of carriers between a first semiconductor body region on a first side of a selected cell in the NAND string and a second semiconductor body region on a second side of the selected cell in the NAND string; during the first stage, isolating the first semiconductor body region and applying a pass voltage pulse on word lines in the plurality of word lines on the first side of the selected cell to boost by capacitive coupling the first semiconductor body region to a boosted voltage level; during the first stage and the second stage, biasing the second semiconductor body region to a reference voltage level; during the first stage and the second stage, applying a program potential greater than a hot carrier injection barrier level to the selected cell; and during the second stage, enabling flow of carriers from the second semiconductor body region to the selected cell to cause generation of hot carriers.