Patent ID: 7873688

Claim:
A summation processing method for floating point data for computing a sum of three or more floating point data in arrival sequence by a reduction mechanism, comprising: establishing storage locations for first and second floating point data groups having mantissa and exponent sections, the exponent sections of the first and second floating point data groups having significant bits with a highest value and a second highest value, respectively; shifting, by a data conversion circuit, a mantissa of received floating point data according to values of insignificant bits of an exponent section of the received floating point data, to create a mantissa section of the received floating point data with an expanded data width; inputting the mantissa section with the expanded data width to a comparison circuit and to a first arithmetic circuit and a second arithmetic circuit; comparing, by the comparison circuit, the significant bits of the exponent section of the received floating point data with the significant bits of the exponent sections of the first and second floating point data groups; setting, by the comparison circuit, the stored exponent sections of the first and second floating point data groups according to the comparison result of said comparison circuit; dynamically computing, by the first arithmetic circuit, a first sum of the mantissa sections of the first floating point data group and the mantissa section of the received floating point data when the received floating point data belongs to the first floating point data group according to a comparison result of said comparison circuit; dynamically computing, by the second arithmetic circuit, a second sum of the mantissa sections of the second floating point data group and the mantissa section of the received floating point data when the received floating point data belongs to the second floating point data group according to a comparison result of said comparison circuit; shifting, by said data conversion circuit, the second sum according to the values of the insignificant bits of the exponent sections of the second floating point data group after all floating point data has arrived, to produce a shifted sum; and adding, by the processor said data conversion circuit, the first sum of the mantissa sections of the first floating point data group and the shifted sum of the mantissa sections of the second floating point data group by a data conversion circuit.