Patent ID: 6980019

Claim:
An output buffer apparatus comprising: first and second power supply terminals; an output terminal; a main-buffer circuit including a plurality of first transistors which are connected between said first power supply terminal and said output terminal and a plurality of second transistors which are connected between said second power supply terminal and said output terminal; a pre-buffer circuit including a plurality of first pre-drivers one of said first pre-drivers driving one of said first transistors in accordance with a data and a plurality of second pre-drivers one of said second pre-drivers driving one of said second transistors in accordance with said data signal; a plurality of first sequential circuits which receive a first impedance adjusting signal in synchronization with said data signal to turn ON one of said first pre-drivers; and a plurality of second sequential circuits which receive a second impedance adjusting signal in synchronization with said data signal to turn ON one of said second pre-drivers.