Patent ID: 7341909

Claim:
A method of forming a semiconductor construction, comprising: providing a substrate having a defined memory array region; the substrate comprising, within the memory array region, a plurality of storage node contacts covered by an electrically insulative material; forming trenches within the electrically insulative material; the trenches having faceted upper portions with facets of the faceted portions sloping upwardly and outwardly relative to interior regions of the trenches; the faceted upper portions having uppermost and outermost facet edges; the uppermost and outermost facet edges of adjacent trenches being spaced from one another by intervening regions of the electrically insulative material; forming electrically conductive bitline material to be within the trenches and over the faceted upper portions, but to be not over the intervening regions of the electrically insulative material; using the electrically conductive bitline material as a mask during an etch through the intervening regions of the electrically insulative material to the storage node contacts; the etch through the intervening regions forming openings that extend to the storage node contacts; and forming electrically conductive interconnect material to be within the openings and electrically coupled to the storage node contacts.