Patent ID: 7218677

Claim:
A variable-length encoding apparatus encoding two data groups in parallel, comprising: an input unit adapted to input a first VALID signal and a second VALID signal for every clock cycle, wherein the first VALID signal indicates whether or not a first data group is input and the second VALID signal indicates whether or not a second data group is input; a first encoding unit adapted to generate, when the first VALID signal indicates that the first data group is input, first variable-length encoding data by applying variable-length encoding to the first data group, and output the generated first variable-length encoding data and a number of bits of the first variable-length encoding data; a second encoding unit adapted to generate, when the second VALID signal indicates that the second data group is input, second variable-length encoding data by applying variable-length encoding to the second data group, and output the generated second variable-length encoding data and a number of bits of the second variable-length encoding data; a shift unit adapted to shift the second variable-length encoding data by the number of bits of the first variable-length encoding data; and a concatenation unit adapted to concatenate the first variable-length encoding data and the second variable-length encoding data by executing a logical OR of the first variable-length encoding data and the shifted second variable-length encoding data, wherein said concatenation unit outputs only the first variable-length encoding data without executing the concatenating processing, when the second VALID signal indicates that the second data group is not input.