Patent ID: 7007056

Claim:
A memory address generating method comprising: a plurality of butterfly input samples are concurrently read from the same corresponding number of sample memory banks, a butterfly calculation is performed by using the plurality of butterfly input samples, and a memory bank index and an address control signal required for a series of Fast Fourier Transform (FFT) processes for storing the results at the same position as that of the input samples, are calculated within a fixed small delay time by using a differential parity counter, wherein the differential parity counter comprises: a multiplexer unit for calculating a parity change value for every clock cycle of a data counter; a NOT gate for inverting an output signal of the multiplexer unit; an AND gate unit for calculating a count of the data counter and outputting a signal to control the multiplexer unit; a flip-flop for storing a current parity value (pr); and an XOR gate for XORing the current parity value and a parity chance value (q 0 ) outputted from the NOT gate to calculate the next parity value (in_pr), and storing the next parity value (in_pr) in the flip-flop.