Patent ID: 8108819

Claim:
A computer implemented method for object placement in a design of an integrated circuit having cells, the cells including electronic components, wires, and pins defined for interconnections, the computer implemented method comprising: receiving an initial placement representing cells in the integrated circuit design corresponding to the design; estimating a characteristic of the initial placement, the characteristic weighted by one of (i) wiring congestion in an area of the initial placement, and (ii) pin density in an area of the initial placement; performing, at an application executing in a data processing system, a transformation on a part of the initial placement to form a transformed placement, the part including the area of the initial placement, the transformation improving the characteristic in the transformed placement as compared to the characteristic in the initial placement, the transformation including one of (i) resizing an object in the area to form a resized object such that the resized object is moved out of the area, and (ii) increasing a cost associated with a wire in the area such that another wire of a comparatively lower cost is moved out of the area; determining whether the characteristic has improved by at least a threshold value in the transformed placement by re-estimating the characteristic in the transformed placement; and producing a final placement corresponding to the transformed placement responsive to an improvement in the characteristic by at least the threshold value, the final placement representing a new design of the integrated circuit.