Patent ID: 8835988

Claim:
A hybrid integrated circuit comprising: a semiconductor substrate layer; wherein said semiconductor substrate layer has a (100) orientation; at least a first semiconductor region formed in a first portion of said semiconductor substrate layer; at least a CMOS integrated circuit formed at least partially in said first semiconductor region; a semiconductor trench formed in a second portion of said semiconductor substrate layer; a buffer layer formed above at least a portion of a bottom side of said semiconductor trench; at least a second semiconductor region in said semiconductor trench formed above said buffer layer; wherein said second semiconductor region is comprising at least a first and a second compound semiconductor layers; wherein said second semiconductor region is formed above and in physical contact with said buffer layer; wherein said first compound semiconductor layer forms an hetero-junction with said second compound semiconductor layer; wherein the energy gap of said first compound semiconductor layer is greater than the energy gap of said second compound semiconductor layer; at least a semiconductor hetero-structure transistor device formed in said second semiconductor region; wherein said first semiconductor region is made of a semiconductor material comprising elements of the IV group of the periodic table; wherein an upper and a lower surface of said buffer layer have substantially the same shape; wherein said buffer layer is interposed between said second semiconductor region and the bottom side of said semiconductor trench so as to physically separate said second semiconductor region and said semiconductor device from the bottom side of said semiconductor trench; wherein said buffer layer is made of a material belonging to the group comprising AlN, Ge, SiGe and ZnO; wherein at least one of said at least one semiconductor device comprises at least one of the materials belonging to the group comprising polar and non-polar III-V compounds semiconductors, polar and non-polar II-VI compounds semiconductors materials, and wherein said CMOS integrated circuit is at least partially covered with a protective layer; and wherein at least one of said at least one semiconductor hetero-structure transistor device is a power transistor, and said CMOS integrated circuit comprises a control CMOS circuit of said power transistor.