Patent ID: 8304810

Claim:
A semiconductor device, comprising: a silicon substrate; a p-type MISFET having a first source region, a first drain region and a first channel region which is arranged between the first source region and the first drain region; and an n-type MISFET having a second source region, a second drain region and a second channel region which is arranged between the second source region and the second drain region, wherein the silicon substrate is selectively etched, wherein at least one said selectively etched portion is filled up with an SiGe layer, wherein the first drain region and the second source region are formed in the SiGe layers, respectively, wherein a silicon film is formed on a top surface of the SiGe layer, wherein the first channel region and the second channel region are formed in the silicon substrate and are disposed on a sidewall of the SiGe layer, respectively, wherein a compressive stress is applied to the first channel region to increase a drain current of the p-type MISFET, and wherein a tensile stress is applied to the second channel region in order to increase a drain current of the n-type MISFET.