Patent ID: 8466027

Claim:
A method comprising: providing a semiconductor substrate; forming a fin structure extending upwardly from the substrate, the fin structure having spaced source and drain regions therein; forming a gate structure engaging the fin structure between the source and drain regions, the gate structure having a dummy gate electrode therein; depositing a first inter-level dielectric (ILD) layer over the gate structure and fin structure; removing the dummy gate electrode to form a trench in the gate structure; depositing a metal layer into the trench to form a metal gate electrode therein; removing a top portion of the metal gate electrode to form an opening in the gate structure; forming a hard mask layer in the opening; removing the first ILD layer to expose the source and drain regions in the fin structure; forming silicide layers on the respective source and drain regions in the fin structure; removing the hard mask layer; and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.