Patent ID: 7566597

Claim:
A manufacturing method for a thin film transistor array substrate comprising: providing a substrate, wherein a plurality of pixel regions are defined on the substrate; forming a plurality of scan lines and a plurality of gates on the substrate; forming a gate insulating layer covering the scan lines and the gates on the substrate; forming and patterning a semiconductor layer on the gate insulating layer to form a patterned leaning layer and form island structures above the gates; forming a plurality of sources and a plurality of drains in both sides of the island structures above the gates and forming a plurality of data lines, wherein the patterned leaning layer is correspondingly disposed under the data lines and the patterned leaning layer comprises a plurality of non-continuous patterns disposed under each of the data lines and exposing portions of the gate insulating layer under the data lines, so as to make a part of each data line directly attach to the gate insulating layer underneath; forming a passivation layer and forming a plurality of openings in the passivation layer in order to expose the sources and drains; and forming pixel electrodes on the passivation layer in the pixel regions respectively, wherein each of the pixel electrodes is electrically connected with the corresponding source and drain via the corresponding opening.