Patent ID: 7154144

Claim:
A self aligned inner gate reccss channel in a semiconductor substrate, comprising: a. a recess trench formed in an active region of the substrate; b. a gate dielectric layer formed on a bottom portion of the recess trench; c. recess inner sidewall spacers formed on sidewalls of the recess trench; d. a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate; e. a gate mask formed on the gate layer; f. gate sidewall spacers formed on the protruding upper portion of gate and the gate mask; and g. a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers, the recess inner sidewall spacers extending below an upper surface of the substrate a majority of a distance that the source/drain region extends below the upper surface and only a portion of a distance that the gate extends below the upper surface, and being sandwiched between the source/drain region and the gate.