Patent ID: 7665003

Claim:
A device comprising: a computer readable memory having a first input and a first output; a first register for storing data, the first register having a second input and a second output, the second output coupled to the first input of the computer readable memory; a second register for storing data, the second register having a third input and a third output, the third input coupled to the first output of the computer readable memory; logic responsive to the second output of the first register and the third output of the second register for dynamically switching between selection of the second output of the first register and the third output of the second register; and a first multiplexer having a fourth output, the fourth output coupled to the second input of the first register, wherein a first input of the first multiplexer receives data during a write operation, a second input of the first multiplexer receives data during a test mode write operation, and a third input of the first multiplexer is coupled to the first output of the computer readable memory.