Patent ID: 8656232

Claim:
An apparatus for testing a semiconductor integrated circuit, the apparatus comprising: a pattern data generating unit that generates test pattern data for testing a write operation in a memory of the semiconductor integrated circuit, in which a write address for the semiconductor integrated circuit is indicated in the test pattern data; and a write unit that writes the test pattern data into a storage area of the semiconductor integrated circuit, wherein the pattern data generating unit includes an input unit that inputs test target information designating the semiconductor integrated circuit as a test target, and stores the test target information in a storage area of the apparatus; an operation-target-bit acquiring unit that acquires operation target bit information corresponding to the test target information stored in the storage area of the apparatus from a definition table, the definition table associating LSI-identifying information that identifies the semiconductor integrated circuit with bit-specifying information that specifies an operation target bit of the memory; and a merge unit that merges an operation condition for the operation target bit information, which is acquired from an operation condition table that sets the operation condition for all of the bits of the memory, with a non-operation condition table that contains address information of all of the bits and in which a non-operation condition is set for all of the bits.