Patent ID: 7825888

Claim:
A shift register circuit comprising: a first clock terminal and first and second output terminals; a first transistor for supplying a first clock signal inputted to said first clock terminal to said first output terminal; a second transistor for discharging said first output terminal; a third transistor for supplying said first clock signal to said second output terminal; a fourth transistor for discharging said second output terminal; a first driving circuit connected to a control electrode of said first transistor, for driving said first transistor; a second driving circuit connected to a control electrode of said third transistor, for driving said third transistor; said first driving circuit and said second driving circuit perform charge/discharge of said control electrode of said first transistor and charge/discharge of said control electrode of said third transistor, respectively, at the same timing; said first driving circuit includes a sixth transistor coupled to said control electrode of said first transistor and discharges said control electrode of said first transistor; said second driving circuit includes an eighth transistor coupled to the control electrode of said third transistor and discharges said control electrode of said third transistor; and a control electrode of said sixth transistor is connected to a control electrode of said eighth transistor.