Patent ID: 8686417

Claim:
A semiconductor device comprising: a gate electrode layer over a substrate; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer comprising indium; a source electrode layer over the oxide semiconductor layer; and a drain electrode layer over the oxide semiconductor layer, wherein an upper surface of the oxide semiconductor layer between the source electrode layer and the drain electrode layer is etched so that a portion of the oxide semiconductor layer is thinner than portions of the oxide semiconductor layer below the source electrode layer and the drain electrode layer, wherein edge portions of the oxide semiconductor layer are step-like and comprise first edges and second edges, wherein the first edges of the oxide semiconductor layer are aligned with outer side edges of the source electrode layer and the drain electrode layer, wherein the second edges of the oxide semiconductor layer extend beyond the outer side edges of the source electrode layer and the drain electrode layer, wherein the second edges of the oxide semiconductor layer have curved surfaces, wherein the gate electrode layer comprises a stack of a first layer comprising Ti and a second layer comprising Cu, wherein the gate insulating layer comprises a stack of a silicon nitride layer and a first silicon oxide layer, and wherein the silicon nitride layer covers the second layer.