Patent ID: 8115529

Claim:
A device comprising: a first control circuit receiving a first signal in response to a first clock and generating a second signal; and a second control circuit receiving the second signal in response to a second clock which leads in phase from the first clock, outputting a third signal to an output node thereof and including a divider which has a variable divide ratio, the second control circuit controlling an output timing at which the second control circuit outputs the third signal in response to the variable divide ratio, wherein the second control circuit includes a first synchronization unit coupled between the first control circuit and the output node, and the synchronization unit comprises a first latch circuit receiving the second signal at a first receiving timing and a second latch circuit connected in series to the first latch circuit and outputting the third signal to the output node at a first output timing, wherein the divider supplies the first latch circuit and the second latch circuit with a first timing signal and a second timing signal, respectively, and the first timing signal and the second timing signal correspondingly define the first receiving timing and the first output timing, wherein the second control circuit includes a first delay circuit, and wherein the divider divides the second clock by the variable divide ratio so as to generate a first divided clock, and the divider supplies the first divided clock to the first delay circuit such that the first delay circuit generates the first timing signal in response to the first divided clock and supplies the first timing signal to the first latch circuit.