Patent ID: 7062635

Claim:
A processor operable in response to an instruction set comprising a plurality of instructions, the processor comprising: a functional unit comprising an integer number S of sub-units; wherein each of the sub-units is operable to execute during an execution cycle at least one of the instructions in the instruction set in response to at least two data arguments; and wherein S is greater than one; circuitry for providing an updated value of the at least two data arguments to less than all S of the sub-units for a single execution cycle; wherein the circuitry for providing an undated value comprises: a plurality of data inputs, each of the data inputs for receiving a respective data value; a plurality of output latches, wherein one of the output latches is for providing an updated value of one of the at least two data arguments for a single execution cycle; a first plurality of pass gates, each pass gate of the first plurality of pass gates coupled between a respective one of the first plurality of data inputs and an output node; and a second plurality of pass gates, each pass gate of the second plurality of pass gates coupled between the output node and an input of a respective one of the plurality of latches; circuitry for enabling only one pass gate of the first plurality of pass gates for a given single execution cycle; and circuitry for enabling only one pass gate of the second plurality of pass gates for the given single execution cycle.