Patent ID: 8435851

Claim:
A method for implementing stacked vertical transistors in a back-end-of-line (BEOL) structure on a semiconductor System on Chip (SoC) comprising: forming a pair of stacked vertical field effect transistors (FETs) by polycrystalline depositions in a stack between planes of a respective global signal routing wire in the back-end-of-line (BEOL) structure; said polycrystalline depositions of each of said pair of stacked vertical FETs including sequential source deposition, channel deposition and drain deposition; and forming a wire via defining a gate node of each of said pair of stacked vertical FETs by forming an etched hole through said source deposition, channel deposition and drain deposition, and an ohmic contact, and a dielectric layer to a signal wire in the BEOL stack; depositing a thin dielectric in said etched opening, and removing said thin dielectric from a bottom of said etched opening, and depositing a metal in said etched opening.