Patent ID: 7092276

Claim:
In a memory device, a memory cell group for storing a plurality of data bits, comprising: a plurality of ferroelectric memory cells connected in series with one another and accessible using a single bitline, the ferroelectric memory cells individually comprising a transistor and a ferroelectric capacitor for storing a data bit associated with a corresponding data word, wherein a single ferroelectric memory cell of the plurality of ferroelectric memory cells is connected to the bitline, and wherein the plurality of ferroelectric memory cells comprises a first ferroelectric memory cell, a last ferroelectric memory cell, and at least one intermediate ferroelectric memory cell, the first, last, and intermediate ferroelectric memory cells being connected in series with one another with the at least one intermediate ferroelectric memory cell being connected between the first and last ferroelectric memory cells, and wherein the last ferroelectric memory cell is connected to the bitline, and wherein the first ferroelectric memory cell comprises a first ferroelectric capacitor connected between a first source/drain terminal of a corresponding first transistor and a first plateline corresponding to a first data word, the first transistor comprising a second source/drain terminal connected to an intermediate ferroelectric memory cell and a gate terminal connected to a first wordline corresponding to a first data word; wherein each intermediate ferroelectric memory cell comprises an intermediate ferroelectric capacitor connected between a first source/drain terminal of a corresponding intermediate transistor and an intermediate plateline corresponding to an intermediate data word, the intermediate transistor comprising a second source/drain terminal connected to a subsequent ferroelectric memory cell and a gate terminal connected to an intermediate wordline corresponding to an intermediate data word; and wherein the last ferroelectric memory cell comprises a last ferroelectric capacitor connected between a first source/drain terminal of a corresponding last transistor and a last plateline corresponding to a last data word, the last transistor comprising a second source/drain terminal connected to a subsequent ferroelectric memory cell and a gate terminal connected to the bitline.