Patent ID: 8174865

Claim:
A memory device comprising: a plurality of memory bit lines that are connected to a plurality of memory cells, the memory bit lines having a first pattern and a second pattern, the first pattern having a first critical dimension (CD) distribution, the second pattern having a second CD distribution that is different from the first CD distribution; a plurality of reference bit lines connected to a plurality of reference cells, the reference bit lines having the first pattern and the second pattern; and a reference bit line selection circuit that is configured to provide a reference signal by selecting a reference bit line having a same pattern as a selected memory bit line connected to a memory cell to be read when a read operation is performed, wherein the reference bit line selection circuit includes a plurality of transistors that selectively activate the reference bit line having the same pattern as the selected memory bit line connected to the memory cell to be read, in response to a bit line selection signal when the read operation is performed.