Patent ID: 7657667

Claim:
A system to provide software program control of cache management, comprising: a control processor; one or more asymmetric processors; a shared system memory; one or more local memories, wherein each of the one or more local memories is associated with a respective one of the one or more asymmetric processors; a direct memory access (DMA) controller coupled to the control processor and the one or more asymmetric processors, configured to execute DMA commands for moving data between the shared system memory and the one or more local memories; and a DMA cache coupled to the DMA controller configured to cache data being moved between the shared system memory and the one or more local memories; wherein the control processor is configured to generate DMA cache management commands for the management of the DMA cache; wherein the DMA cache management commands comprise at least one of a data cache range touch command that indicates to the DMA controller that the control processor will probably issue a get command for a specified address range, a data cache range touch for store command that indicates to the DMA controller that the control processor will probably issue a put command for a specified address range, a data cache range set to zero command that sets a range of storage specified by an effective address and transfer size to zero, a data cache range store command that indicates a data block specified by an effective address and transfer size to be written to the shared system memory if the data block is considered modified, and a data cache range flush command that indicates a data block specified by an effective address and transfer size to be written to the shared system memory and invalidated in caches of all processors if memory coherency is required and the data block is modified.