Patent ID: 7522457

Claim:
A non-volatile memory system, comprising: a set of non-volatile storage elements; and one or more managing circuits in communication with the set of non-volatile storage elements, the one or more managing circuits perform one or more erase operations on the set of non-volatile storage elements, the one or more erase operations include applying a first erase voltage pulse to the set, applying a second erase voltage pulse to the set after verifying that one or more non-volatile storage elements of the set are not sufficiently erased subsequent to application of the first erase voltage pulse, and applying a third erase voltage pulse to the set of non-volatile storage elements after verifying that one or more non-volatile storage elements of the set are not sufficiently erased subsequent to application of the second erase voltage pulse, the second erase voltage pulse having an equal or lesser magnitude than the first erase voltage pulse and the third erase voltage pulse having a greater magnitude than the second erase voltage pulse.