Patent ID: 8436411

Claim:
A non-volatile memory, comprising: a substrate, having at least two isolation structures therein and an active region between the isolation structures; two control gates, respectively disposed on the isolation structures, wherein the two control gates are disposed within each one single memory cell; a floating gate corresponding to the two control gates, the floating gate being disposed on the substrate and comprising three portions, wherein one of the three portions covers a portion of the active region and two of the three portions locate above and cover the two control gates respectively, an entire overlapped area of each of the two control gates and the floating gate is completely located on the corresponding one of the at least two isolation structures; a first dielectric layer, disposed between each of the two control gates and the floating gate; a second dielectric layer, disposed on the substrate, the second dielectric layer being contacted with and located between the substrate in the active region and the floating gate; and two heavily doped regions, respectively disposed in the substrate beside the floating gate.