Patent ID: 7193643

Claim:
An electronic circuit for correcting scan non-linearity of a raster output scanner comprising: a control circuit for modulating a clock frequency to match a scan linearity error profile wherein said control circuit synchronizes itself with a clock signal using a counter/subtractor phase detector to match a phase and frequency of an internal clock to a phase and frequency of a master clock; said control circuit counting a number of input pulses and using this count to address a lookup table and to control a plurality of latches; said control circuit providing an output value, defined by said input pulse count multiplied by 8 and an error correction signal from said lookup table; said output value compared to a current count from a VCO pulse counter using a digital subtractor, a digital phase detector capable of detecting error in phase and frequency of both input and output clocks; and a counter in the control circuit and an output pulse counter together with the subtractor making up said digital phase detector; said counters running at a higher speed in order to detect phase differences between said clocks.