Patent ID: 8488388

Claim:
A method of programming a non-volatile memory cell having a single crystalline substrate of a first conductivity type and having a top surface, with a first region of a second conductivity type in said substrate along the top surface, and a second region of the second conductivity type, in said substrate along the top surface, spaced apart from the first region, with a channel region between the first region and the second region; a word line gate is positioned over a first portion of the channel region, spaced apart from the channel region by a first insulating layer; a floating gate is positioned over another portion of the channel region, adjacent to and separated from the word line gate, wherein the floating gate is separated from the channel region by a second insulating layer; a coupling gate is positioned over the floating gate and insulated therefrom by a third insulating layer; and an erase gate is positioned adjacent to the floating gate and on a side opposite to the word line gate; said erase gate positioned over the second region and is insulated therefrom; said method comprising: applying a first positive voltage to the word line gate to turn on the portion of the channel region beneath the word line gate; applying a voltage differential between the first region and the second region; applying a second positive voltage to the coupling gate, substantially at the same time as the first positive voltage, to cause hot electrons to be injected to the floating gate from the channel region; applying a third positive voltage to the erase gate after a period of delay after the start of the first and second positive voltages and a voltage differential between the first region and the second region, to cause electrons to be injected to the floating gate.