Patent ID: 8244515

Claim:
A design structure embodied in a nontransitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a pipeline electronic processor device including a plurality of pipeline stages, the plurality of pipeline stages including first and second pipeline stages that each include logic elements that may be clock-gated, each pipeline stage supplying information to a downstream pipeline stage, wherein selected logic elements are clock-gated based on simulation results of a simulation of the pipeline electronic processor device, the simulation specifying the selected logic elements that may be clock-gated under predetermined conditions to achieve power conservation in an information handling system (IHS), the simulation including looking upstream and downstream in the plurality of pipeline stages to determine the selected logic elements that may provide clock gating opportunities, each clock gating opportunity corresponding to a respective clock gating opportunity type, wherein the simulation provides simulation results and further wherein the simulation includes weighting the selected logic elements according to their respective clock gating opportunity types, thus indicating their respective power savings potential when clock gated, thus providing weighted results included in the simulation results.