Patent ID: 8314455

Claim:
A non-volatile semiconductor storage device comprising: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors are formed, the transistors configuring peripheral circuits to control the memory cells, the memory cell area comprising: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to the semiconductor substrate, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers, the property-varying layer further including a first insulation layer, a second insulation layer, and a third insulation layer sandwiched between the first and second insulation layers, the third insulation layer being formed of a material different from those of the first and second insulation layers, the peripheral circuit area comprising: a plurality of dummy wiring layers each formed on a same plane as each of the plurality of conductive layers and electrically separated from the conductive layers, wherein the plurality of dummy wiring layers have an opening, planar-type transistors are formed on the semiconductor substrate in the peripheral circuit area, and a contact is formed to penetrate the opening of the plurality of dummy wiring layers to be connected to the planar-type transistors.