Patent ID: 7638868

Claim:
A microelectronic package comprising: a lower unit including a lower unit substrate having conductive features and a top and bottom surface, said lower unit including one or more lower unit chips overlying said top surface of said lower unit substrate that are electrically connected to said conductive features of said lower unit substrate, said one or more lower unit chips including top surfaces remote from said lower unit substrate and edge surfaces extending away from said top surfaces; and an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces, said upper unit further including one or more upper unit chips overlying said top surface of said upper unit substrate and electrically connected to said conductive features of said upper unit substrate by connections extending within said hole, said upper unit substrate being disposed over said lower unit chips, said hole and said connections of said upper unit being offset in a first horizontal direction from said lower unit chips, said connections being offset in said first horizontal direction such that at least one edge surface of at least one of said lower unit chips is adjacent to said connections in said first horizontal direction.