Patent ID: 7271080

Claim:
A method of fabricating an electrically erasable programmable read only memory (EEPROM) cell, comprising the steps of: forming an isolation layer on a semiconductor substrate to define an active region; forming a gate oxide layer on the active region; forming a mask pattern on the gate oxide layer, the mask pattern having an opening that exposes a portion of the gate oxide layer; implanting impurity ions into the active region using the mask pattern as an ion implantation mask, thereby forming a buried N+ region in the active region; forming a spacer pattern on a sidewall of the opening to define a tunnel region surrounded by the spacer pattern; etching the gate oxide layer in the tunnel region using the mask pattern and the spacer pattern as etching masks, thereby exposing the buried N+ region; removing the mask pattern and the spacer pattern; forming a tunnel oxide layer on the buried N+ region in the tunnel region; and simultaneously forming a memory gate over the buried N+ region and a selection gate spaced apart from the memory gate.