Patent ID: 7921148

Claim:
A cell for an arithmetic logic unit comprising a mirror adder circuit modified to perform additional arithmetic or logic functions without additional transistors excluding input or output inverters, comprising: a first masked input a*; a second masked input b*; a third masked input ci*, wherein the third masked input ci* is a masked carry input, a mask bit k p , or an inverted mask bit k p ; a first control input xe 0 and a second control input xe 1 ; and a first circuit comprising a first plurality of transistors, wherein inputs of the first plurality of transistors are connected to the first masked input a*, the second masked input b*, and the third masked input ci*, and the first plurality of transistors having a first output co*_n, the first output co*_n being a masked inverted carry-out bit; a second circuit comprising a second plurality of transistors, wherein inputs of the second plurality of transistors are connected to the first masked input a*, the second masked input b*, the first output co*_n, the first control input xe 0 , and the second control input xe 1 , and the second plurality of transistors having a second output s*_n; the second output s*_n having a first value, when the first control input xe 0 , the second control input xe 1 , and the third masked input ci* are equal to the masked carry input, the first value being an inverted masked sum bit s*_n of a masked addition of the first masked input a*, the second masked input b*, and the third masked input ci*; the second output s*_n having a second value when the first control input xe 0 , the second control input xe 1 , and the third masked input ci* are equal to the mask bit k p , the second value being an inverted masked XOR output of the first masked input a* and the second masked input b*, the second output s*_n having a third value when the first control input xe 0 , the second control input xe 1 , and the third masked input ci* are equal to the inverted mask bit k p , the third value being an inverted masked XNOR output of the first masked input a* and the second masked input b*; and the second output s*_n having a fourth value when the values at the first control input xe 0 and the second control input xe 1 are independent of the value at the third masked input ci*, the fourth value being an inverted masked NAND or NOR output of the first masked input a* and the second masked input b*.