Patent ID: 7737026

Claim:
A method of forming an interconnection in a semiconductor, the method comprising: forming a first liner on the sidewalls and bottom region of a via formed in a dielectric layer of the semiconductor; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the top of the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner on the sidewalls of the upper region of the via and on the upper surface of the tungsten filler; selectively removing the second liner from the upper surface of the tungsten filler; forming a copper seed layer on top of the tungsten filler and along the sidewalls of the upper region of the via; depositing a copper filler on top of the copper seed layer; and performing chemical mechanical planarization (CMP) to smooth out and remove the second liner and copper filler from the top of the semiconductor's exposed surface.