Patent ID: 8125550

Claim:
A complementary metal-oxide semiconductor (CMOS) image sensor comprising: a pixel array comprising a plurality of pixel sensors arranged as a matrix, each of the plurality of pixel sensors utilized for sensing incident light and outputting a reset signal and a light-sensing signal in order; and a plurality of correlation double sampling (CDS) circuits, individually coupled to a column of the pixel array, for sampling the reset signal and the light-sensing signal outputted by the column, each of the plurality of CDS circuits comprising: a signal input terminal for receiving the reset signal and the light-sensing signal; a first sampling capacitor having a first terminal and a second terminal, the second terminal directly retrieving a reference voltage from a reference voltage terminal; a second sampling capacitor having a first terminal and a second terminal, the second terminal directly retrieving the reference voltage from the reference voltage terminal; a first switch, coupled between the signal input terminal and the first terminal of the first sampling capacitor, for providing electrical connection between the signal input terminal and the first sampling capacitor during a first phase to enable the first sampling capacitor to sample a voltage of the reset signal; a second switch, coupled between the signal input terminal and the first terminal of the second sampling capacitor, for providing electrical connection between the signal input terminal and the second sampling capacitor during a second phase to enable the second sampling capacitor to sample a voltage of the light-sensing signal; a third switch, being turned on during a third phase to provide electrical connection between the first terminal of the first sampling capacitor and a first signal output terminal to enable the first sampling capacitor to output the sampled voltage to the first signal output terminal through the turned-on third switch; and a fourth switch, being turned on during the third phase to provide electrical connection between the first terminal of the second sampling capacitor and a second signal output terminal to enable the second sampling capacitor to output the sampled voltage to the second signal output terminal through the turned-on fourth switch; wherein the first signal output terminal and the second signal output terminal are differential input terminals of a rear-stage buffer amplifier.