Patent ID: 7673208

Claim:
An integrated circuit chip, comprising: a test input configured to receive test data; an expectation input configured to receive expected result data; at least two circuitry cores, each core having a core test input and a core test output, each core being configured to receive test data from the test input at its core test input, to generate test result data according to the received test data, and further configured to provide the generated test result data at its core test output; comparator circuitry configured to compare for each core the test result data from the core test outputs and the received expected result data to generate for each core comparison result data indicating whether or not there is a mismatch between the test result data and the expected result data; and a diagnosis data unit configured to store diagnosis data in the case of an indicated mismatch for a certain core, the diagnosis data including an indication of mismatch-causing test data and corresponding comparison result data of said concerned core, wherein the indication of mismatch-causing test data comprises an indication of a test pattern from which a mismatch-causing output pattern originates.