Patent ID: 8017520

Claim:
A method for fabricating an integrated circuit, comprising: constructing an active circuit on a semiconductor platform; depositing a metal layer, at least partially, above the active circuit; and forming a bond pad, at least partially, above the metal layer; wherein the metal layer defines a frame with an outer periphery and an inner periphery; wherein the active circuit includes a plurality of transistors, and an entirety of at least one of the transistors is disposed directly below the bond pad, and the frame ensures that at least one bond is capable of being placed over the at least one transistor without damage thereto during a bonding process; wherein the bond pad is only disposed above an outer periphery of an input/output (I/O) bus of the active circuit; wherein an interconnect metal layer of the metal layer is electrically coupled to a plurality of underlying metal layers by way of vias, the plurality of underlying metal layers disposed at least in part below the active circuit; wherein the interconnect metal layer interconnects the bond pad with the plurality of underlying metal layers; wherein the interconnect metal layer of the metal layer defines an island, the island including a plurality of openings, the openings defining a plurality of substantially linear first portions and a plurality of substantially linear second portions which intersect, where interconnect vias formed in rows along a length of at least the first portions provide communication between the interconnect metal layer and the bond pad; wherein the openings are adapted for facilitating an interlock between the interconnect metal layer of the metal layer and an inter-metal dielectric layer disposed between the metal layer and the bond pad.