Patent ID: 7716458

Claim:
An integrated circuit, comprising: a processor; an arithmetic logic circuit group including a plurality of operation units inclusive of two or more arithmetic logic units, and including connection channels connecting between said operation units in a reconfigurable manner, said arithmetic logic circuit group not being a Field Programmable Gate Array; parameter-based dedicated hardware configured to execute predetermined data processing and changing a process specification thereof by parameter setting, the parameter setting indicating at least one of a number of data and accuracy of the data processing; an intermodule interface connecting said processor, said arithmetic logic circuit group, and said parameter-based dedicated hardware to each other; a reconfigurable gate array connected to the intermodule interface and allowing logic change at a gate level; and wherein the processor has a first granularity the arithmetic logic circuit group has a second granularity lower than the first granularity and higher than a gate-level granularity of the reconfigurable gate array; and data transfer among the plurality of operation units is conducted within the arithmetic logic circuit group, so that an operation processing speed of the operation units is not limited by a data transfer rate of the intermodule interface, wherein the parameter-based dedicated hardware comprises: a data input and output buffer connected to the intermodule interface; a dedicated hardware engine connected to said data input and output buffer and executing a specific process; and a controller controlling an operation and a process specification of said dedicated hardware based on parameters; a temporary data storing buffer configured to temporarily store and maintain an intermediate result of the specific process when the specific process is executed by the dedicated hardware engine; a parameter holding register configured to supply the parameters to the controller; and a clock controller configured to generate and supply a clock signal to the controller, the data input and output buffer, the dedicated hardware engine, and the temporary data storing buffer, wherein the plurality of operation units include different types of operation units, and the arithmetic logic circuit group further includes: a configuration memory configured to store processing information regarding each of the plurality of the units and coupling information between the plurality of the units; and a controller controlling the plurality of the units based on the processing information and the coupling information, and wherein the arithmetic logic circuit group includes a plurality of stages of operation unit arrays, each of the plurality of stages including a register, selectors, and plural operation units, wherein the later a given stage in the plurality of stages, fewer number of operation units are included in the given stage.