Patent ID: 8704566

Claim:
A phase locked loop (PLL) circuit, comprising: a phase and frequency detector (PFD), which compares a reference clock signal and a first feedback clock signal to determine a phase difference and a frequency difference between the reference and first feedback clock signals, which generates a first control signal that indicates a frequency difference between the reference and first feedback clock signals, and which generates a second control signal that indicates a phase difference between the reference and first feedback clock signals; a digitally controlled oscillator (DCO) that generates an output signal having a target frequency; a digital integrating control path that is responsive to the first control signal output from the PFD to generate a first. DCO control signal to adjust a frequency of the output signal of the DCO to the target frequency; an analog proportional control path that is responsive to the second control signal output from the PFD to generate a second DCO control signal to adjust a phase of the output signal of the DCO when the frequency of the output signal of the DCO is similar to or the same as the target frequency; and a feedback circuit to generate the first feedback clock signal based on the output signal from the DCO.