Patent ID: 8039931

Claim:
An integrated power semiconductor component comprising: a semiconductor material region or a basic semiconductor structure with a surface region; at least one semiconductor circuit region provided in the semiconductor material region or in the basic semiconductor structure, in which, for a contact-connection of the semiconductor circuit region, in the surface region of the semiconductor material region or of the basic semiconductor structure and electrically connected thereto via contact locations therein, contacts are provided with or from a portion of a topmost metallization layer; and an embedding material layer for embedding the semiconductor material region or the basic semiconductor structure with the contact locations and the contacts, in which, below the embedding material layer, a protection and sealing material region is provided laterally beyond the contact locations and the contacts; wherein the topmost metallization layer being formed in a manner extended laterally also beyond the contact locations and the contacts in such a way, wherein the topmost metallization layer laterally almost completely extends over and covers the directly underlying structures of the integrated power semiconductor component, wherein the protection and sealing material region is formed directly by the topmost metallization layer whilst avoiding customary and additional electrically insulating protection and sealing stack layers, wherein the embedding material layer and the topmost metallization layer are formed above the surface region of the semiconductor material region or the basic semiconductor structure, wherein the topmost metallization layer is formed adjacent to the embedding material layer, and wherein on the power semiconductor component the topmost metallization layer is formed by sputtering, vapour deposition, electroplating, autogenous electroplating or CVD.