Patent ID: 8381155

Claim:
A method of generating a set of valid vertical interconnect positions for a multiple layer integrated circuit, wherein said multiple layer integrated circuit comprises: multiple layers stacked vertically above one another; a bonding interface between a pair of layers in said multiple layers, wherein said bonding interface is formed by coupling of a pair of conductive bond patterns formed on facing surfaces of said pair of layers, each pattern of said pair of conductive bond patterns comprising an arrangement of conductive bonding elements, said method comprising the steps of: defining a candidate transformation origin within a horizontal plane defined by said bonding interface; defining a sub-region within said arrangement of conductive bonding elements, wherein said sub-region tessellates across said arrangement of conductive bonding elements; applying a predetermined transformation in said horizontal plane with respect to said candidate transformation origin to said arrangement of conductive bonding elements within said sub-region to generate a transformed arrangement of conductive bonding elements; determining validity of said candidate transformation origin in dependence on coincidence of at least a subset of said arrangement of conductive bonding elements with said transformed arrangement of conductive bonding elements; selecting a valid transformation origin in dependence on an outcome of said step of determining validity of said candidate transformation origin; defining said set of valid vertical interconnect positions associated with said valid transformation origin where said arrangement of conductive bonding elements coincides with said transformed arrangement of conductive bonding elements; and outputting said set of valid vertical interconnect positions.