Patent ID: 8486818

Claim:
A method of forming a semiconductor device, comprising: forming and patterning a plurality of layers on a semiconductor substrate to form a patterned structure; simultaneously forming isolation trenches and buried gate trenches in the semiconductor substrate by selectively removing portions of the patterned structure, the isolation trenches defining active regions of the semiconductor substrate; forming a conductive pattern in the isolation trenches and the buried gate trenches; and forming a capping layer on the conductive patterns in the isolation trenches and the buried gate trenches, wherein forming and patterning the plurality of layers to form the patterned structure includes: forming a first insulation layer on the semiconductor substrate; forming a patterning layer on the first insulation layer; forming a pattern by patterning the patterning layer to expose portions of the first insulation layer and define trenches in the pattern; forming a first layer on the portions of the first insulation layer exposed by the pattern to partially fill the trenches defined by the pattern; forming a second layer on the first insulation layer, the second layer filling the partially filled trenches defined by the pattern; performing a planarization process to expose upper surfaces of the pattern, the first layer, and the second layer; removing the pattern to expose sidewalls of the first layer; forming spacers on the sidewalls of the first layer; and removing a portion of the first insulation layer to expose portions of the semiconductor substrate.