Patent ID: 8044498

Claim:
A semiconductor package comprising: a package substrate; a first semiconductor bare chip mounted on a surface of the package substrate; an interposer arranged parallel to the package substrate, the interposer having an upper surface and a lower surface; a second semiconductor bare chip mounted on the lower surface of the interposer, the second semiconductor bare chip opposing to the first semiconductor bare chip; a plurality of first electrodes formed on the lower surface of the interposer, and electrically connected to the second semiconductor bare chip respectively; a plurality of second electrodes formed on the upper surface of the interposer and arranged in substantially matrix with a pitch greater than an electrode pitch of the second semiconductor bare chip; and a plurality of third electrodes formed on the upper surface of the interposer and arranged in line with a pitch smaller than the pitch of the plurality of second electrodes, and arranged along at least one side of the interposer; wherein, the package substrate and one of the plurality of third electrodes are electrically connected; and one of the plurality of the first electrodes, one of the plurality of second electrodes and one of the plurality of third electrodes are electrically connected together.