Patent ID: 7083495

Claim:
An advanced process control (APC) method for a target layer polish process in a polish tool that minimizes within wafer and wafer to wafer sheet resistance (Rs) variations in a plurality of wafers having a metal layer formed on a barrier layer within an opening in a dielectric layer, said metal layer has a thickness, width, and cross-sectional area, comprising: providing a plurality of wafers each having a metal layer that has been formed on a barrier layer within an opening in a dielectric layer by a sequence of processing steps; determining a relationship between the cross-sectional area of said metal layer and Rs; determining a total Rs (Rs TOTAL ) for the metal layer on each of said plurality of wafers before said target layer polish process; determining a target layer polish thickness target for said metal layer on each of said plurality of wafers; and calculating a target layer polish time for each of said plurality of wafers in the target layer polish process.