Patent ID: 6975978

Claim:
A fault simulation method for a semiconductor IC, said method comprising the steps of: generating a test pattern sequence composed of two or more test patterns for input to said semiconductor IC; performing a logic simulation of the operation of said semiconductor IC in the case of applying thereto each or said two or more test patterns of said test pattern sequence, and calculating a logic signal value sequence in each signal line in said semiconductor IC; and generating a list of faults for each logic gate in said semiconductor IC, which are detectable by a transient power supply current testing using said test pattern sequence, through the use of said logic signal value sequence in said each signal line calculated by said logic simulation, wherein the list of faults is generated by checking, for said each logic gate, whether a logic signal value sequence in an output signal line of said each logic gate has been changed, and if so, generating said fault list in which an identifier of a test pattern sequence having changed said logic signal value sequence and said logic gate are registered in correspondence with each other.