Patent ID: 7567464

Claim:
A non-volatile memory device, comprising: a network of non-volatile memory cells each comprising a floating-gate transistor, said network of cells for storing data in the form of a set of data words; a read circuit which performs a first and second read of the memory cells to generate corresponding first and second read currents; a comparison circuit which compares the first read current with a first threshold value enabling a discrimination between a high logical level and a low logical level, compares the second read current with at least one second charge loss detection threshold value greater than the first threshold value, and compares words resulting from the first and second carried out reads to detect loss of charges; and a reprogramming circuit which reprograms those cells for which a loss of charges has been detected so as to restore the level of stored charges; wherein the charge loss detection threshold value is a read current value between a programmed cell current value and a nominal read current value.