Patent ID: 8468379

Claim:
A solid-state data-storage device that stores data in response to data accesses under the control of a memory control circuit, the device comprising: a primary solid-state non-volatile memory circuit configured and arranged to maintain data integrity in the absence of primary operating power, the primary solid-state memory circuit including a plurality of non-volatile memory chips that require a programming-voltage level to write data thereto, and a shared power resource for delivering voltage to each chip of the plurality of memory chips; a primary power supply input providing primary power having a primary voltage level that is lower than the programming-voltage level; a voltage-boost circuit configured to receive the primary power and to generate a boost voltage level from the primary power, the boost voltage level being higher than the primary voltage level, and provide the boost voltage level to the shared power resource; a solid-state volatile memory circuit, under the control of the memory control circuit, susceptible to loss of data stored within in response to the voltage of the primary operating power dropping below a voltage threshold level; and a backup power-supplying circuit, including an energy-storage component, designed to hold sufficient energy to provide substantially all of the primary operating power to the memory circuits upon loss of externally-supplied power during a minimum time period sufficient to permit transfer of data from the volatile memory circuit to the solid-state non-volatile memory circuit in order to maintain the data integrity of the data storage device.