Patent ID: 7825000

Claim:
A method of forming a magnetic memory device including a Magnetic Tunnel Junction (MTJ) device in a product array region juxtaposed with a kerf region with alignment marks therein comprising the following steps: then forming a via level InterLayer Dielectric (ILD) layer over a substrate; forming a kerf region recess extending down into said substrate; then filling said kerf region recess with an alignment base layer; then forming a bottom stack conductor layer with a to surface, an MTJ stack layer, and a conductive hard mask layer over said alignment base layer and said ILD layer; then forming an alignment mask over said device with a window therethrough exposing said hard mask layer in said kerf region; then etching away said hard mask layer and said MTJ stack layer in said kerf region exposing said to surface of said bottom stack conductor in said kerf region thereby separating said MTJ stack layer in said product array region from said kerf region; forming a planarizing coating over said device; then forming a Lithographic Patterning Level (JA) level mask with openings over said planarizing coating in said kerf region with no opening over said MJT stack layer in said product array region aside from said kerf region; and then etching through said pattern openings in said JA level mask to form MJT elements from said MJT stack in said product array region below said JA level mask and to form alignment marks in said kerf region below said JA level mask extending through said bottom conductor layer and extending down into said device below said top surface of said VA ILD layer.