Patent ID: 7650200

Claim:
A method of creating a Site-Dependent (S-D) evaluation library comprising: receiving a plurality of S-D wafers by one or more S-D transfer subsystems in a processing system, the one or more S-D transfer subsystems being coupled to one or more S-D subsystems, each S-D wafer having wafer data associated therewith, wherein the wafer data includes historical and/or real-time data; establishing wafer state data for each S-D wafer, wherein the wafer state data comprises a number of required creation sites and a number of required evaluation sites for each S-D wafer; establishing a library-creation processing sequence for creating a library of S-D evaluation data, the library-creation processing sequence being created using the wafer state data, wherein the library-creation processing sequence comprises a S-D transfer procedure, a S-D creation procedure, or a S-D evaluation procedure, or any combination thereof; determining a first number of S-D process wafers to be processed using a first library-creation processing sequence, a first S-D creation procedure and a first S-D evaluation procedure being determined using the first library-creation processing sequence; establishing first operational states for a plurality of S-D processing elements in one or more processing subsystems; determining a first number of available processing elements using the first operational states for one or more of the S-D processing elements; establishing a first S-D transfer sequence using the wafer data, the wafer state data, the first number of S-D process wafers, or the first number of available processing elements, or any combination thereof; transferring the first number of S-D process wafers to the first number of available processing elements therein the one or more processing subsystems using the first S-D transfer sequence when the first number of S-D process wafers is less than or equal to the first number of available processing elements, and applying a first corrective action when the first number of S-D process wafers is greater than the first number of available processing elements.