Patent ID: 7307311

Claim:
A semiconductor structure comprising a substrate having an active region of a first conductive type including a channel region and a non-channel region surrounding the channel region, at least a first trench and a second trench disposed in the active region, the structure comprising: a thin insulating layer disposed over said first and second trenches partially filling said first and second trenches and being conformal to said first and second trenches; a gate electrode comprising a first conductive vertical portion, a second conductive vertical portion and a horizontal conductive portion, wherein the conductive first vertical portion is embedded inside the first trench over said thin insulating layer such that said insulating layer and said first conductive vertical portion within the first trench completely fills the first trench, the second conductive vertical portion is embedded inside the second trench over said thin insulating layer such that said insulating layer and said second conductive vertical portion within the second trench completely fills the second trench, and the horizontal conductive portion is disposed over the substrate and connects said first and second conductive vertical portions together; and a pair of shallow doped regions within the substrate disposed adjacent to and on two opposite sides of each of the first and second conductive vertical portions and the conductive horizontal portion; and a pair of deep doped regions extending respectively from the first pair of shallow doped regions to regions within the substrate deeper than the first and second trenches, wherein the pair of shallow doped regions form shallow source/drain regions with a shallow channel region therebetween below the conductive horizontal portion; and, wherein the pair of deep doped regions form deep source/drain regions with two deep channel regions therebetween below the first and second trenches, respectively.