Patent ID: 7122414

Claim:
A method of forming a gate stack in an integrated circuit comprising: depositing a dielectric layer over a substrate comprising a first region and a second region by an atomic layer deposition process; depositing a barrier layer directly over the dielectric layer by an atomic layer deposition process such that it overlies both the first and second regions; and forming a first gate electrode layer over the first region of the substrate and a second gate electrode layer over the second region, wherein the first and second gate electrode layers comprise materials selected from the group consisting of polysilicon, Ti, Ni, Co, TiN, TiAl x N y , TaN, TaAl x N y , Ru, RuO 2 , Ir, IrO 2 , HfN, WN x C y , HfAl x N y and HfSi x N y ; and forming a first and second gate electrode comprising the first and second gate electrode layers respectively, wherein the barrier layer influences the work function of at least one of the first and second gate electrodes.