Patent ID: 7750721

Claim:
A low power bias circuit, comprising: a peaking current mirror circuit configured to receive a start current and to provide a mirror current; and a temperature compensating current mirror coupled to the peaking current mirror circuit and configured to provide a reference current, wherein the temperature compensating current mirror comprises: an input configured to receive the mirror current, a first bipolar transistor having a base terminal, an emitter terminal and a collector terminal, a second bipolar transistor having a base terminal, an emitter terminal and a collector terminal, and an output configured to provide the reference current, wherein the input is directly connected to the base terminal of the second bipolar transistor and the collector terminal of the first bipolar transistor, and is connected via a first resistor to the base terminal of the first bipolar transistor, wherein the output is connected to the collector terminal of the second bipolar transistor, and wherein a reference node providing a reference voltage is connected via a second resistor to the base terminal of the first bipolar transistor, directly to the emitter terminal of the first bipolar transistor and via a third resistor to the emitter terminal of the second bipolar transistor.