Patent ID: 8151134

Claim:
A serial peripheral interface (SPI) master device, the SPI master device in communication with at least one SPI slave device, the SPI master device comprising: a first clock generator operable to generate a first clock signal; a slave selection unit operable to generate a slave selection signal for each of the at least one SPI slave device to determine whether each of the at least one SPI slave device is selected; a clock frequency divider operable to divide a clock frequency of the first clock signal by two to generate a serial clock signal for the at least one SPI slave device; a first clock counter operable to count clock cycles of the first clock signal; a first output logic unit operable to generate one or more read/write instructions, and transfer the one or more read/write instructions, one or more destination addresses and data to be written to the selected SPI slave device according to the first clock signal and a count value of the first clock signal; and a first input logic unit operable to receive data from the selected SPI slave device according to the first clock signal and the count value of the first clock signal.