Patent ID: 7961007

Claim:
A receiver circuit comprising: an input stage coupled to receive a first input signal and a second input signal, wherein the input stage is configured to generate an output indicating whether or not the first input signal is greater than the second input signal; a first current source coupled to the input stage and configured to supply current to the input stage; a second current source coupled in parallel with the first current source and having an enable input, wherein the second current source is configured to supply current to the input stage responsive to an assertion of the enable input; and a bias circuit coupled to the first current source and the second current source, wherein the bias circuit is configured to provide a bias voltage to the first current source and the second current source to control a first amount of current supplied by the first current source and a second amount of current supplied by the second current source, wherein the bias circuit is coupled to receive a second enable signal and to generate the bias voltage responsive to an assertion of the second enable signal; and wherein each of the first current source and the second current source includes a first transistor having a gate terminal coupled to receive the bias voltage, and wherein the second current source comprises a second transistor coupled in series with the first transistor, wherein a gate of the second transistor is coupled to receive the enable signal to the second current source, and wherein the first current source comprises a corresponding transistor to the second transistor, the corresponding transistor coupled in series with the first transistor of the first current source and having a gate terminal coupled to a power supply voltage.