Patent ID: 7123100

Claim:
An oscillating circuit comprising: a phase comparator receiving a reference signal and a divided clock signal, the phase comparator outputting a comparing signal in response to a phase difference between the reference signal and the divided clock signal; a filter circuit connected to receive the comparing signal, the filter circuit passing a first signal having a first frequency within a first frequency range; a clock generator connected to the filter circuit, the clock generator providing an output clock signal in response to the first signal passed through the filter circuit; and a divider circuit connected to the phase comparator and the clock generator, the divider circuit comprising a ring counter that generates a plurality of internal signals responsive to receipt of the output clock signal and that outputs the divided clock signal responsive to the plurality of internal signals, wherein the divided clock signal has a second frequency that is outside the first frequency range, the plurality of internal signals have frequency that is outside the first frequency range and the divider circuit generates signals all of which have the second frequency.