Patent ID: 7727889

Claim:
A method for forming a fine pattern, the method comprising: forming a target layer to be patterned over a semiconductor substrate; forming a polysilicon layer over the target layer; forming partitions on the polysilicon layer with amorphous carbon layer patterns; forming a spacer to the sidewall of the partitions; selectively removing the partitions; dividing the spacer into bar patterns by selectively removing an end portion of the spacer; forming pad mask patterns connected to end portions of the bar patterns on a portion of the polysilicon layer beside the divided bar patterns; forming polysilicon layer patterns by selectively etching portions of the polysilicon layer exposed by the divided bar patterns and the pad mask patterns; and forming target layer patterns by selectively etching portions of the target layer exposed by the polysilicon layer patterns, wherein the bar patterns are formed for patterning gate lines and the pad mask patterns are formed for patterning contact pads, wherein the pad mask pattern is wider than the bar patterns.