Patent ID: 8923032

Claim:
A crosspoint nonvolatile memory device, comprising: a plurality of word lines parallel to each other on a first plane; a plurality of bit lines parallel to each other on a second plane parallel to the first plane, the bit lines three-dimensionally crossing the word lines; a crosspoint memory cell array in which memory cells are arrayed in rows and columns, the memory cells being arranged at respective three-dimensional crosspoints between the word lines and the bit lines, and each of the memory cells including a variable resistance element that is reversibly changed between a first resistance state and a second resistance state that has a higher resistance value than a resistance value of the first resistance state, when receiving an electrical signal; a word line selector that selects a world line from the word lines; a bit line selector that selects a bit line from the bit lines; a writing circuit that applies a forming pulse for forming to a predetermined memory cell among the memory cells, the predetermined memory cell being selected by selecting the bit line by the bit line selector and selecting the word line by the word line selector; a sense amplification circuit electrically connected to the bit line; and a control circuit that controls the sense amplification circuit and the writing circuit, wherein, in an initial state after manufacturing the variable resistance element, the variable resistance element is in a third resistance state that has a higher resistance value than the resistance value of the second resistance state, and after forming is performed, a resistance state of the variable resistance element is changed from the initial state to a state where the resistance state is reversibly changeable between the first resistance state and the second resistance state, the sense amplification circuit includes a current source that selectively switches a load current among load currents having different current amounts and supplies the load current to the bit line selected by the bit line selector, and the sense amplification circuit outputting a first logical value when a current amount of the load current flowing into the bit line selected by the bit line selector is more than a reference current amount, and outputting a second logical value when the current amount is less than the reference current amount, and when the predetermined memory cell is selected, before the application of the forming pulse to the predetermined memory cell, (i) the control circuit adjusts the current amount of the load current supplied from the current source to a predetermined current amount that causes the sense amplification circuit to output the second logical value, and (ii) after the adjustment, the control circuit (ii-1) controls the current source to supply the load current having the predetermined current amount, and (ii-2) controls the writing unit to keep applying the forming pulse to the predetermined memory cell until the sense amplification circuit outputs the first logical value.