Patent ID: 8020130

Claim:
A timing analysis apparatus arranged to analyze an operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, the analysis apparatus comprising: a controller arranged to obtain a noisewave form of a power supply noise of the semiconductor integrated circuit, the noisewave form being at least one of a power supply voltage and a ground voltage of a power supply for the semiconductor integrated circuit, decomposing decompose the noise waveform to obtain one or more frequency components of the noise waveform, classify the frequency components into low-frequency components having frequencies lower than a predetermined threshold frequency and high-frequency components having frequencies higher than the threshold frequency, calculate a static delay time of each of the logic gates due to the low-frequency components, calculate a dynamic delay time of each of the logic gates due to the high-frequency components, and determine a delay time of each of the logic gates by synthesizing the calculated static and dynamic delay times.