Patent ID: 7026241

Claim:
A method of manufacturing a semiconductor device, comprising: forming a plurality of element regions defined by an element separation region in a semiconductor substrate and forming an element in each of said element regions; forming sequentially a first barrier insulation film, an interlayer insulation film, and a second barrier insulation film on the semiconductor substrate having the element formed thereon; etching from the second barrier insulation film to a predetermined depth of the interlayer insulation film to form a plurality of wiring grooves aligned with said plurality of element regions; forming a resist pattern having a linear or wave shaped opening that crosses said plurality of wiring grooves; etching the interlayer insulation film and the first barrier insulation film while using the resist pattern and the second barrier insulation film as masks, to form a contact hole on each of said element regions; embedding a conductor plug in the contact hole; removing the second barrier insulation film; and embedding a wiring layer which is connected to the conductor plug in the wiring groove of the interlayer insulation film.