Patent ID: 8173544

Claim:
A method for fabricating an integrated circuit, comprising the steps of: providing a substrate having a semiconductor surface; and for at least one masking level of said integrated circuit, providing a mask pattern for said masking level partitioned into a first mask and at least one second mask, said first mask providing features in a first grid pattern and said at least one second mask providing features in a said second grid pattern, wherein said first and second grid patterns have respective features that interleave with one another over at least one multi-transistor area of said mask level; applying a first photoresist film onto said surface of said substrate; printing said first grid pattern in said first photoresist film using said first mask; applying a second photoresist film onto said substrate; printing said second grid pattern in said second photoresist film using said second mask; and etching to transfer said printed first and said second grid patterns from said first and second photoresist films to form said interleaved features in said surface of said substrate.