Patent ID: 7681064

Claim:
A time of day (TOD)-clock steering apparatus for a computer system having a physical clock providing a time base for executing operations that is stepping to a common oscillator, said apparatus comprising: a memory storage device; a processor in communications with the memory storage device, wherein the apparatus is configured to perform a method comprising: computing a TOD-clock offset value (d) to be added to a physical clock value (Tr) to obtain a logical TOD clock value (Tb), said logical TOD clock value being adjustable without adjusting a stepping rate of said oscillator, wherein said TOD-clock offset value (d) is computed according to: d=b+ ( Tr−s ) ×r where (b) is a base offset value aligned wit bits of (Tr), (s) is a current start time value aligned with bits of (Tr), and, (r) is a current steering rate value, said s, b and r values defining a TOD-clock steering adjustment value.