Patent ID: 7484076

Claim:
A method for performing instructions using multiple execution units in a graphics processing unit comprising: issuing an instruction for P executions of the instruction wherein each execution uses different data, P being a positive integer, the instruction being issued based on a first clock having a first clock rate; operating Q execution units to achieve the P executions of the instruction, Q being a positive integer less than P and greater than one, each of the execution units being operated based on a second clock having a second clock rate higher than the first clock rate of the first clock; and wherein the second clock rate of the second clock is equal to the first clock rate of the first clock multiplied by the ratio P/Q, and wherein if the multiple execution units comprises a total number of execution units greater than Q, an active device mask is used to identify a subset of Q execution units of the multiple execution units that are to be used to achieve the P executions of the instruction.