Patent ID: 8458287

Claim:
One or more device memories storing computer-executable instructions that, when executed, cause one or more processors to perform acts comprising: selecting, by one or more processors configured with executable instructions, a first plurality of nodes of at least one data center to store a data file as a first set of erasure coded fragments; storing the data file as the first set of erasure coded fragments in the first plurality of nodes of the at least one data center; monitoring, during a first time period, a first access frequency of the data file that is stored as the first set of erasure coded fragments; determining that the first access frequency of the data file meets or exceeds a first predetermined frequency threshold during the first time period or after the first time period expires; reconstructing the data file from at least a portion of the first set of erasure coded fragments after determining that the first access frequency of the data file meets or exceeds the first predetermined frequency threshold; storing the reconstructed data file in a storage node; monitoring, during a second time period, a second access frequency of the reconstructed data file that is stored in the storage node; determining that the second access frequency of the reconstructed data file is below a second predetermined frequency threshold during the second time period or after the second time period expires; selecting a second plurality of nodes to store the reconstructed data file as a second set of erasure coded fragments, wherein the second plurality of nodes is different than the first plurality of nodes; and storing the reconstructed data file as the second set of erasure coded fragments in the second plurality of nodes after determining that the second access frequency of the reconstructed data file is below the second predetermined frequency threshold.