Patent ID: 7190612

Claim:
A magnetic memory comprising: a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a magnetic storage element capable of being programmed by a write current driven through the magnetic storage element; a bit line corresponding to the plurality of magnetic storage cells; a plurality of word lines, each of the plurality of word lines corresponding to a magnetic storage cell of the plurality of magnetic storage cells and for allowing current to flow through the magnetic storage cell; bit line read/write logic corresponding to the bit line, the bit line read/write logic including a plurality of NAND gates and a plurality of inverters coupled to the plurality of NAND gates, wherein the plurality of NAND gates includes a first NAND gate having a first output, a second NAND gate having a second output, and a third NAND gate having a third output, and wherein the plurality of inverters further includes a first inverter having a first input coupled to the first output, a second inverter having a second input coupled to the second output, and a third inverter having a third input coupled to the third output; and a plurality of switches for the bit line, the plurality of switches being controlled by the bit line read/write logic to selectively provide a read current or the write current to the plurality of magnetic storage elements; wherein the plurality of switches further includes a first switch controlled by the second NAND gate, a second switch controlled by the third inverter, a third switch controlled by the first inverter, a fourth switch controlled by the third NAND gate, and a fifth switch controlled by the second inverter, the first switch, the second switch, the third switch, the fourth switch, and the fifth switch configured to selectively provide the write current through the plurality of magnetic storage cells.