Patent ID: 7202722

Claim:
Apparatus having circuitry for changing duty cycle of a first differential clock signal having first and second signal components, the apparatus comprising: a buffer circuit adapted to add offset voltage between the first and second signal components; and a feedback loop coupled to the buffer circuit and adapted to configure the buffer circuit to generate the offset voltage, which adjusts the duty cycle of the first differential clock signal, wherein: the buffer circuit is adapted to add the offset voltage to generate a second differential clock signal, wherein the first differential signal has a first duty-cycle value and the second differential clock signal has a second duty-cycle value; the feedback loop is adapted to (i) process the second differential clock signal to evaluate deviation of the second duty-cycle value from a desired duty-cycle value and (ii) based on the evaluation, configure the buffer circuit to generate the offset voltage to change the second duty-cycle value; the feedback loop comprises a digital logic circuit coupled to analog circuitry; the analog circuitry is adapted to process the second differential clock signal and provide to the digital logic circuit a measure of deviation of the second duty-cycle value from the desired value; based on the provided measure, the digital logic circuit is adapted to configure the buffer circuit to generate the offset voltage; and the digital logic circuit is further adapted to provide control signals to the analog circuitry for the processing of the second differential signal.