Patent ID: 7465969

Claim:
A bipolar transistor comprising: a first semiconductor layer; a collector layer formed in an upper surface region of the first semiconductor layer and containing an impurity of a first conductive type; two isolation layers formed of an insulating film so that the isolation layers are spaced apart from each other and the collector layer is located therebetween; a second semiconductor layer grown on the first semiconductor layer and the isolation layers, having a different band gap from that of the first semiconductor layer and containing an impurity of a second conductive type; a third semiconductor layer formed on the second semiconductor layer and having a different band gap from that of the second semiconductor layer; an insulating film formed on the third semiconductor layer and including an emitter opening portion; and an emitter electrode formed of a polycrystalline semiconductor containing an impurity of the first conductive type so as to fill the emitter opening portion, wherein a region of the third semiconductor layer which is in contact with the emitter electrode is an emitter layer containing an impurity of the first conductive type, wherein a region of the second semiconductor layer interposed between the emitter layer and the collector layer is an intrinsic base layer containing an impurity of the second conductive type, wherein regions of the second and third semiconductor layers each surrounding the intrinsic base layer together form an external base layer containing an impurity of the second conductive type, wherein the external base layer is provided so as to extend between the isolation layers and has a silicide layer in a surface portion, wherein the emitter electrode has a thickness with which ions of the second-conductive-type impurity implanted into the emitter electrode to form the external base layer are diffused so that the concentration of the impurity is a low level in a lower portion of the emitter electrode, and wherein the insulating film comes in contact with the upper surface of the third semiconductor layer.