Patent ID: 7917729

Claim:
A system-on-chip (SoC) processor Integrated Circuit (IC) architecture comprising: a first processor core for controlling SoC processing functions among a plurality of SoC component devices, said first processor core having an associated memory; an SoC local system bus device for enabling communications among said SoC component devices and said associated memory, one SoC component device comprising a single self-contained multiprocessor subsystem core comprising: a plurality of sub-system processing cores, each core having a processor, each sub-system processor of said plurality operable for providing concurrently running thread operations dedicated to processing a specific network signal processing task according to a network communications protocol, a shared local memory; a switch fabric means connecting each sub-system processing core and said shared memory within said self-contained_multiprocessor subsystem core; and, a network protocol hardware assist device connected to said switch fabric means, said hardware assist device for receiving packets of a particular network communications protocol and forwarding said packets to a sub-system processing core via said switch fabric means; and, a bus bridge device connecting said SoC local system bus device and said switch fabric means, said bus bridge device adapting data for communication between a SoC component device via said SoC local system bus device and to a sub-system processing core via said switch fabric means.