Patent ID: 8443256

Claim:
A method of creating a CRC (Cyclic Redundancy Check) code for a data message, comprising: placing an initial portion of the data message on a bus of width W bits consisting of an integral number N of segments of width S such that the initial portion of the message fills n complete segments, where n≦N; placing a known bit pattern on any segments preceding a start of the message as determined by a start indicator; computing a first intermediate CRC code for said n segments of the initial portion by applying the W bits of the bus forming an input word to a CRC full processing circuit using a compensating constant to compensate for any known bit pattern preceding the initial portion of the message; placing any subsequent portions of said message width W on said bus during subsequent bus cycles, in each case computing a new first intermediate CRC code on the W bits of the bus as input words using the current first intermediate CRC code as a seed input; placing a final portion of said message as determined by an end indicator on said bus, wherein said final portion has a width w bits, where w≦W, and wherein said final portion at least completely occupies s segments, where s<S; computing a second intermediate CRC code using said s segments as input in a segment processing circuit and using said current first intermediate CRC code as a seed input; and computing a final CRC code using any remaining bytes as input in a byte processing circuit and using said second intermediate CRC as a seed input.