Patent ID: 7094644

Claim:
A method for manufacturing a flash memory cell by using a trench method, comprising the steps of: forming a pair of trenches spaced from each other in a silicon substrate; forming spaced trench isolations by filling the trenches to form recessed trench isolations; recessing facing portions of the trench isolations; etching a portion of the silicon substrate between the recessed trench isolations; depositing a tunnel oxide film on the portion of the silicon substrate, between the recessed trench isolations; forming a floating gate on the tunnel oxide film, extending to cover the recessed portion of the trench isolations; forming an oxide-nitride-oxide (ONO) layer to cover the floating gate; and forming a control gate on the ONO layer; wherein a coupling ratio between the floating gate and the control gate depends on recessed widths and depths into the trench isolations.