Patent ID: 6893934

Claim:
A method for fabricating a semiconductor device, comprising the steps of: (a) epitaxially growing a p-type second single-crystal semiconductor layer functioning as a base layer on an n-type first single-crystal semiconductor layer functioning as a collector layer on a substrate; (b) epitaxially growing a third single-crystal semiconductor layer on the second single-crystal semiconductor layer; (c) depositing an emitter lead electrode by sequentially laminating an n − polysilicon layer and an n + polysilicon layer, the n − polysilicon layer containing phosphorus in a concentration equal to or lower than a concentration permitting phosphorus to be diffused into the third single-crystal semiconductor layer in a concentration as high as the solid-solubility limit for the third single-crystal semiconductor layer, and the n + polysilicon layer containing phosphorus in a concentration higher than that in the n − polysilicon layer; and (d) performing heat treatment for diffusing phosphorus in the n − polysilicon layer so that the upper portion of the third single-crystal semiconductor layer is doped with phosphorus in a concentration equal to or lower than the solid-solubility limit, to form an emitter.