Patent ID: 8205067

Claim:
A method for context switching between a first thread and a second thread, comprising: invoking an exception handler in response to an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, wherein the exception handler is configured to: execute one or more instructions removing access to at least a portion of a processor cache of a processor, wherein the portion of the processor cache contains cached information for the first thread using a first address translation, thereby preventing the second thread using a second address translation from accessing the cached information in the processor cache; and branch to at least one of the first thread and the second thread; wherein the processor is configured to, only in response to the instructions executed by the exception handler, remove access to the processor cache by the first thread and second thread to maintain coherency between the first thread and the second thread, wherein the processor is further configured to store an indication that the cached information for the first thread uses instruction-maintained coherency and not processor-maintained coherency.