Patent ID: 7890908

Claim:
A computer-implemented method for verifying mask pattern data, the method comprising steps performed by a computer of: preparing, by the computer, design circuit data for a design circuit which realizes a desired circuit operation; preparing, by the computer, design circuit pattern data for a design circuit pattern which has geometrical features to realize the design circuit and which is formed on a semiconductor substrate; preparing, by the computer, mask pattern data for a mask pattern used to etch a film through the mask pattern to produce the design circuit pattern on the substrate; acquiring, by the computer, a circuit pattern which is expected to be formed after the layer is etched through the mask pattern; producing, by the computer, circuit data which describes a circuit realized by at least a part of the circuit pattern to be verified and including one of an electrical element, an electrical connection, or a combination thereof; and detecting, by the computer, a circuit mismatch part where the circuit data does not match at least a part of the design circuit data, wherein the circuit mismatch part corresponds to a difference, in at least one of a type of an electrical element or a type of an electrical connection between electrical nodes, between the circuit data and the part of the design circuit data which corresponds to the part of the circuit pattern to be verified.