Patent ID: 8010724

Claim:
An I2C/SMBus compatible device comprising: an integrated circuit having; first and second power input terminals, the second power input terminal for connecting to a higher voltage than the first power input terminal; a first integrated circuit portion forming a slave section powered by a voltage from the first terminal and a voltage derived from the voltage on the second terminal, the slave section having an SDA S data line and an SCL S clock line for receiving and sending data and clock signals respectively; a second integrated circuit portion forming a master section powered by a voltage from the second terminal and a voltage derived from the slave section power by a charge pump, the master section having an SDA M data line and an SCL M clock line for receiving and sending data and clock signals respectively; the first integrated circuit portion and the second integrated circuit portion being coupled by level shift circuitry for passing clock and data signals between the master and slave sections; whereby a plurality of the devices may be electrically stacked with each successive device having its first terminal coupled to the second terminal of the prior device in the stack.