Patent ID: 7251305

Claim:
An integrated circuit, comprising: a clock path for carrying a clock signal; a power supply path adapted to receive power from a power supply; a delay locked loop connected to the power supply path, comprising: a voltage-controlled delay line for generating a delayed clock signal dependent on an input thereto; a phase detector for detecting a phase difference between the clock signal and the delayed clock signal; and a bias-generator arranged to output a voltage to the input of the voltage-controlled delay line responsive to the phase detector; an adjustment circuit operatively connected to the input of the voltage-controlled delay line, wherein the adjustment circuit is responsive to control information to adjust the voltage output by the bias-generator, wherein the control information comprises a binary word; and a storage device adapted to store the control information to which the adjustment circuit is responsive. wherein the adjustment circuit comprises a first switch to provide current flow between a first voltage provided by the power supply path and the input of the voltage-controlled delay line, and a second switch to provide current flow between a second voltage provided by the power supply path and the input of the voltage-controlled delay line.