Patent ID: 7064018

Claim:
A method of forming a semiconductor device, comprising: fabricating digital circuits comprising a programmable logic circuit on a substrate; selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program said programmable logic circuit; and fabricating an interconnect and routing structure substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern; wherein the conductive pattern fabrication option utilizes a logic process sequence and the selective memory circuit fabrication option utilizes a thin-film transistor (TFT) process sequence inserted to said logic process sequence, wherein the logic process sequence further comprises: forming a P-type substrate; creating a twin well; developing a shallow trench isolation; performing a sacrificial oxide; generating a PMOS Vt mask and implant; generating a NMOS Vt mask and implant; developing gate oxidation; depositing gate poly (GP); applying the GP mask and etch; applying an LDN mask and implant; applying an LDP mask and implant; depositing a spacer oxide and etching the spacer oxide; depositing Nickel; performing RTA anneal—Ni salicidation (S/DIG regions & interconnect) etching to remove unreacted Nickel; depositing ILD oxide and performing CMP; applying a Cl mask and etch; forming a W plug and performing CMIP; depositing Ml; applying a Ml mask & etch; and performing back end metallization.