Patent ID: 7302557

Claim:
A processor comprising: a functional unit adapted to execute an instruction issued to it from a dispatch stage; and a buffer in the dispatch stage coupled to the functional unit adapted to receive from a fetch stage and store a plurality of the instructions before issue to the functional unit and further adapted to store scheduling information associated with the instructions, wherein the stored plurality of the instructions comprise a set of instructions from a loop body, and wherein the stored scheduling information defines, for each processor cycle in the loop, whether and which of the stored instructions are to be executed in that processor cycle, such that for a first processor execution cycle, the stored scheduling information is used to determine a first one of the stored instructions to be selected and issued to the functional unit from the buffer, and such that for a second different processor execution cycle, the stored scheduling information is used to determine a second one of the stored instructions to be selected and issued to the functional unit from the buffer.