Patent ID: 8776000

Claim:
A method of implementing timing engineering change order (ECO) in a circuit that includes a plurality of gates and that is provided with a plurality of spare cells, comprising the steps of: (A) performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit, each timing violating path including a sequence of the gates such that from each of its gates there is a wire connecting to the next gate in the sequence, and having negative edge slacks, which are slacks of edges that represent wires between the gates; (B) decomposing each of the at least one timing violating path into at least one violating path segment having the same edge slack; (C) determining, for the circuit, a smooth curve from each of the at least one timing violating path, and determining a plurality of reference points that are evenly distributed along the smooth curve and that correspond respectively to the gates on the timing violating path; (D) computing, for the circuit, a fixability parameter of each of the gates on the violating path segment, wherein the fixability parameter is associated with a smoothness parameter of the respective gate, and the smoothness parameter is associated with a distance between the respective gate and the corresponding reference point; (E) extracting at least one gate from the gates on the violating path segment, according to the fixability parameters of the gates on the violating path segment, to serve as at least one extracted gate; (F) selecting one of the spare cells that is adapted for improving slack of a corresponding one of the at least one extracted gate as a selected spare cell, and disposing the selected spare cell on the violating path segment; and (G) rewiring the circuit so as to apply the selected spare cell.