Patent ID: 8020038

Claim:
A processor, comprising: a processor core having an execution unit configured to execute instructions and to attempt to perform at least one operation in executing one of the instructions, the processor core configured to detect a processor error associated with the at least one operation, receive power supplied by a power signal from a power source, and receive a clock signal from a clock; memory configured to store data indicative of an allowable operating range of operating points for the processor core; and a controller configured to control the power source to control an amount of power supplied by the power signal and control the clock to control a frequency of the clock signal provided to the processor core based on the data to maintain the allowable operating range and configured to control the power source to reduce the amount of power supplied by the power signal and control the clock to reduce the frequency of the clock signal provided to the processor core to thereby change an operating point of the processor core in response to a detection of the processor error such that the processor core operates at a new operating point, wherein the processor core is configured to retry the at least one operation while the processor core is operating at the new operating point, wherein the processor is configured to update the data based on detection of one or more processor errors.