Patent ID: 7171611

Claim:
An apparatus for determining at least one of an access time and a minimally allowable cycle time of a memory, the apparatus comprising: programmable delay means having an input terminal for receiving a timing signal and having an output terminal providing a delayed timing signal generated by delaying the timing signal for a programmed delay; sample-and-hold means having a control terminal for receiving the delayed timing signal, at least one input terminal for sampling data output from the memory in response to the delayed timing signal and at least one output terminal for providing sampled output data; a comparator, coupled to the sample-and-hold means, for comparing the sampled output data to reference values; and a test status generator coupled to the comparator, the test status generator providing a test status depending on results of a plurality of comparisons between the sampled output data and reference values, wherein the apparatus and the memory are embedded in an integrated circuit chip and wherein data output from memory is stimulated by the timing signal supplied to a control terminal of the memory.