Patent ID: 7349233

Claim:
A chip comprising: at least four groups of memory banks; at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the groups of memory banks; at least four groups of multiplexers wherein each of the groups of multiplexers corresponds to a different one of the groups of memory banks, wherein each of the group of multiplexers includes at least one multiplexer circuitry to perform a read operation by providing read data from at least one of the banks of each of the groups of memory banks through its corresponding group of multiplexers to its corresponding group of output conductors, wherein the memory banks, groups of output conductors, and circuitry to perform a read operation are each part of the chip; and a set of transmitters corresponding to each group of output conductors, and wherein there are a particular number of lines between the banks and the corresponding multiplexers and fewer lines between each of the multiplexers and the corresponding groups of output conductors.