Patent ID: 7937530

Claim:
A method of accessing a processor cache, the method comprising: executing an access instruction in a processor core of the processor, wherein the access instruction provides an untranslated effective address corresponding to data to be accessed by the access instruction; determining whether the level one cache includes the data to be accessed by the access instruction, comprising: determining whether the first directory of the level one cache includes an entry for a first portion of the effective address; and upon determining that the first directory for the level one cache includes the entry for the first portion of the effective address, determining whether a second directory of the level one cache includes an entry for a second portion of the effective address; providing the data to be accessed by the access instruction from the level one cache upon determining that the level one cache includes the data; and transmitting a request to a level two cache of the processor core to retrieve the data to be accessed by the access instruction upon determining that the level one cache does not include the data, wherein the effective address is translated to a real address via a translation lookaside buffer.