Patent ID: 8344780

Claim:
A flip-flop circuit comprising: a dynamic input unit configured to precharge an evaluation node to a power supply voltage in a first phase of a clock signal, configured to selectively discharge the evaluation node based on input data in a second phase of the clock signal, and configured to compensate for voltage drop of the evaluation node in response to a first control clock signal; and a control clock generator configured to generate the first control clock signal and a second control clock signal based on at least the clock signal, wherein the dynamic input unit comprises: an evaluation unit that includes a plurality of transistors and the evaluation node, each of the transistors receiving each of the clock signal, the second control clock signal and the input data; a keeper circuit, connected to the evaluation node, configured to maintain voltage level of the evaluation node in response to the second control clock signal; and a compensation circuit, connected to the evaluation node, configured to compensate for voltage drop of the evaluation node in response to the first control clock signal, wherein the compensation circuit comprises a PMOS capacitor which has a gate receiving the first control clock signal and a source and a drain which are connected to the evaluation node.