Patent ID: 7929549

Claim:
A memory subsystem comprising: a master controller including a pseudo random bit sequence (PRBS) generator having a plurality of output taps and an exclusive-OR (XOR) unit, wherein each output tap of the PRBS generator provides a different bit sequence; and a memory device coupled to the master controller via a plurality of single ended bidirectional data paths, wherein each data path conveys a respective plurality of data bits; wherein the master controller is configured to scramble each respective plurality of data bits using the PRBS generator and the XOR unit prior to writing each respective plurality of data bits to the memory device; wherein for each of the plurality of single ended bidirectional data paths, the master controller is configured to perform an XOR operation between each bit of the respective plurality of data bits and each bit provided by a respective output tap of the PRBS generator prior to conveyance on a corresponding data path of the plurality of single ended bidirectional data paths; and wherein the memory device further includes a control register including a plurality of bit positions, each having a default logic sense definition, wherein the bit position default logic sense definition of one or more bit positions are adaptively modified such that a logic value of one is sensed as an asserted bit prior to modification, and sensed as a deasserted bit after modification dependent upon a value to be stored within the control register.