Patent ID: 8488382

Claim:
A 3D stacked non-volatile memory device, comprising: a substrate; a stacked non-volatile memory cell array carried by the substrate, and comprising a plurality of sets of memory strings, and each memory string comprises a plurality of memory cells between a drain end of the memory string and a source end of the memory string; a plurality of bit lines, where, for each set of memory strings, a respective bit line of the plurality of bit lines is connected to the drain end of each memory string in the set of memory strings; at least one source line connected to the source end of at least one memory string in each of the sets of memory strings; and at least one control circuit in communication with the stacked non-volatile memory cell array, the plurality of bit lines and the at least one source line, the at least one control circuit: (a) to perform one erase-verify iteration in an erase operation for the plurality of sets of memory strings: applies an erase voltage to each bit line of the plurality of bit lines, then determines whether at least one of the sets of memory strings reaches a set erase-verify condition, the at least one of the sets of memory strings is connected to at least one of the bit lines, and (b) to perform a next erase-verify iteration in the erase operation: (i) if the at least one of the sets of memory strings reaches the set erase-verify condition, applies an erase voltage to remaining bit lines of the plurality of bit lines, other than the at least one of the bit lines, and applies an erase-inhibit voltage to the at least one of the bit lines, and (ii) if the at least one of the sets of memory strings does not reach the set erase-verify condition, applies an erase voltage to each bit line of the plurality of bit lines.