Patent ID: 8400830

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a first sub-bank in which a plurality of nonvolatile memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line and a second sub-bank having the same configuration as that of the first sub-bank; a write/read control unit that performs write or read control for a target memory cell corresponding to a designated address; a decoder unit that applies a voltage to the bit line and the word line based on an instruction from the write/read control unit to apply a write voltage or a read voltage to the target memory cell; a read circuit that reads written data from the target memory cell to which the read voltage is applied; and a comparing unit that compares a plurality of data to be input, wherein, when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank, the decoder unit executes, at the same time, a first operation in which a read voltage is applied to a first target memory cell in the first sub-bank, and a second operation in which a write voltage is applied to a second target memory cell only when a comparison result between the written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell by the comparing unit represents mismatching.