Patent ID: 7613908

Claim:
An apparatus, comprising: a processor having a pipelined architecture and including: a first unit to enable a reorder buffer (ROB) to selectively disable a lock after identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, the LAO being a load and store intent (LSI) operation, and the first unit to identify the LSI as the CS entry point, to mark the LSI as a predicted CS entry point, to set a transaction active flag to indicate that a transaction to be performed in the CS is active, and to selectively set a hardware lock disabling (HLD) flag to indicate that lock disabling is in progress; a second unit to store an address associated with the LAO and a value associated with the LAO, where, at a time associated with dispatching the LSI, the second unit is to prevent the LSI from issuing a read for ownership (RFO), to store in a first register an address associated with a store address (STA) micro-operation (uop) associated with the LSI, and to store in a second register a value associated with a store data (STD) micro-operation associated with the LSI; a third unit to selectively retire the LAO, where the third unit is to cause the ROB to retire the LSI upon determining that the LSI is ready to retire and that no lock release instruction (LRI) related to the LSI has been dispatched, the third unit to clear the HLD prediction flag associated with the LSI to indicate that this LSI should not be disabled in the future, and the third unit to clear the HLD flag to indicate that HLD is no longer in progress; a fourth unit to cause the ROB to selectively disable the lock, where the fourth unit is, upon determining that the LSI is ready to retire and that an LRI related to the LSI has been dispatched, to cause the ROB to not retire the LSI, to cause the ROB to not retire the LRI, to cause the ROB to selectively stall retirement of instructions in the CS, and then, upon determining that all instructions in the CS are ready to retire and that all memory accesses associated with instructions in the CS are completed, to bulk retire instructions in the CS and to set the HLD prediction to indicate that the LSI should be disabled in the future; a fifth unit to selectively cause the ROB to commit an instruction in the CS; a sixth unit to identify a store instruction whose store address matches the address associated with the LAO; and a seventh unit to snoop a buffer and, based, at least in part, on the snooping, to selectively abort a transaction associated with the CS.