Patent ID: 7940110

Claim:
A switch circuit comprising: a first NMOS transistor having a source to drain path coupled between a first data node and a first intermediate node, and a gate terminal coupled to receive a nominally fixed voltage during normal operation; a second NMOS transistor having a source to drain path drain terminal coupled between the intermediate node and a second data node, and a gate terminal coupled to receive an enable signal, wherein the second NMOS is configured to activate when the enable signal is asserted; a third NMOS transistor having a source to drain path coupled between the first data node and a second intermediate node, and a gate terminal coupled to receive the nominally fixed voltage during normal operation; a first PMOS transistor having a source to drain path coupled between the first intermediate node and the second data node, and a gate terminal coupled to receive a complement of the enable signal, wherein the first PMOS transistor is configured to activate responsive to assertion of the enable signal; a second PMOS transistor having a source to drain path coupled between the gate terminal of the first NMOS transistor and the first intermediate node, and a gate terminal coupled to receive the enable signal; and a third PMOS transistor having a source to drain path coupled between the gate terminal of the third NMOS transistor and the second intermediate node, and a gate terminal coupled to receive the enable signal, wherein the second and third PMOS transistors are configured to activate responsive to a de-assertion of the enable signal.