Patent ID: 8232206

Claim:
A semiconductor processing method, comprising: providing a monocrystalline silicon substrate, the substrate supporting a digit line and a spacer structure, the digit line comprising a region and the spacer structure comprising another region; the digit line region having an upper surface and the spacer structure region having another upper surface, the digit line region upper surface being about the same elevational height over the substrate as the spacer structure region upper surface, the substrate comprising a first electrically insulative material over the digit line region and a second electrically insulative material over the spacer structure region; the substrate supporting a capacitor; the capacitor having a pair of electrodes spaced from one another by a dielectric material; the spacer structure not being either of the capacitor electrodes; forming openings through the first and second electrically insulative materials, the opening through the first electrically insulative material being a first opening and extending to the upper surface of the digit line region, the opening through the second electrically insulative material being a second opening and extending to the upper surface of the spacer structure region, the second opening having a periphery which includes an electrically conductive portion of one of the capacitor electrodes; and electroless plating an electrically conductive material within the first and second openings, the electroless plating initiating from the upper surfaces of the digit line region and spacer structure region, the electroless-plated material forming an electrical contact to the digit line in the first opening and forming an electrical contact to the capacitor electrode along the periphery of the second opening.