Patent ID: 8546220

Claim:
A method for fabricating buried bit lines, comprising the steps of: Step S 1 : defining a plurality of parallel masked regions and a plurality of first etched regions on a surface of a substrate, wherein each of the plurality of first etched regions is formed between any two neighboring masked regions, and wherein each of the plurality of masked regions is formed at a width greater than that of each of the plurality of first etched regions; Step S 2 : etching the substrate where the plurality of first etched regions are formed to form a plurality of first trenches corresponding to the plurality of first etched regions and a plurality of first pillars corresponding to the plurality of masked regions; Step S 3 : implanting first conductive ions into two sidewalls of each of the plurality of first trenches to form two bit lines respectively on two sidewalls of each of the plurality of first pillars; Step S 4 : filling a packing material into the plurality of first trenches; Step S 5 : respectively forming a plurality of second etched regions on the plurality of first pillars to parallel to the plurality of first etched regions without contacting the packing material; and Step S 6 : etching the plurality of second etched regions to form a plurality of second trenches and a plurality of second pillars, and wherein the plurality of second pillars are corresponding to the bit lines.