Patent ID: 8396912

Claim:
An infinite impulse response resonator digital filter, comprising: a) a first register, having a first input, having a second input, having a third input, having a fourth input, having a fifth input, having a first output, having a second output, having a third output, having a fourth output, and having a fifth output; b) a multiplexer/demultiplexer, having a first input connected to said first output of said first register, having a second input connected to said second output of said first register, having a third input connected to said third output of said first register, having a fourth input connected to said fourth output of said first register, having a fifth input connected to said fifth output of said first register, having a sixth input, having a seventh input, having a clock input, having a first output connected to said first input of said first register, having a second output connected to said second input of said first register, having a third output connected to said third input of said first register, having a fourth output connected to said fourth input of said first register, having a fifth output connected to said fifth input of said first register, having a sixth output, having a seventh output, and having an eighth output; c) a first multiplier, having a first input connected to said sixth output of said multiplexer/demultiplexer, having a second input, and having an output; d) a second multiplier, having a first input connected to said seventh output of said multiplexer/demultiplexer, having a second input, and having an output; e) a third multiplier, having a first input, having a second input, having an output connected to said sixth input of said multiplexer/demultiplexer; f) an adder, having a first input connected to said output of said first multiplier, having a second input connected to said output of said second multiplier, having a third input connected to said output of said third multiplier, and having an output; g) a subtractor, having a first input connected to said output of said adder, having a second input connected to said eighth output of said multiplexer/demultiplexer, having an output connected to said seventh input of said multiplexer/demultiplexer; and h) a second register, having a first input, having a first output connected to said first input of said third multiplier, having a second output connected to said second input of said second multiplier, having a third output connected to said second input of said first multiplier, and a fourth output.