Patent ID: 8749300

Claim:
A DC voltage conversion circuit of a liquid crystal display apparatus, comprising: a main pumping circuit including a plurality of thin film transistors and configured to output voltage for driving a liquid crystal display apparatus when the plurality of thin film transistors are alternately turned on or off; and a switch control signal generator configured to control voltages applied to gates of the plurality of thin film transistors by inversion of a clock signal, wherein each thin film transistor is turned on when positive gate-source voltage is applied thereto, and turned off when negative gate-source voltage is applied thereto, wherein the main pumping circuit includes: a first thin film transistor in which second power supply voltage is applied to a source, a first node is connected to a gate, and a second node is connected to a drain; a second thin film transistor in which the second power supply voltage is applied to a source, a third node is connected to a gate, and a fourth node is connected to a drain; a third thin film transistor in which the second node is connected to a source, the third node is connected to a gate, and a fifth node is connected to a drain; a fourth thin film transistor in which the fourth node is connected to a source, the first node is connected to a gate, and a sixth node is connected to a drain; a fifth thin film transistor in which the fifth node is connected to a source, a seventh node is connected to a gate, and an eighth node is connected to a drain; a sixth thin film transistor in which the sixth node is connected to a source, a ninth node is connected to a gate, and a tenth node is connected to a drain; a seventh thin film transistor in which the eighth node is connected to a source, an eleventh node is connected to a gate, and an output node is connected to a drain; and an eighth thin film transistor in which the tenth node is connected to a source, a twelfth node is connected to a gate, and the output node is connected to a drain, and wherein a first clock signal is inputted to the second node, the sixth node and the eighth node, a second clock signal is inputted to the fourth node, the fifth node and the tenth node, a third clock signal is inputted to the third node, the ninth node and the eleventh node, and a fourth clock signal is inputted to the first node, the seventh node and the twelfth node.