Patent ID: 7851929

Claim:
A semiconductor device having a wafer level chip size package (WL-CSP) structure, comprising: a semiconductor substrate having an integrated circuit formed thereon; a plurality of electrode pads formed on the semiconductor substrate, being intended for input and output of signals between the integrated circuit and an external circuit; at least one rewiring layer which includes rewiring formed adjacent to the plurality of electrode pads so as to be integral with the semiconductor substrate; and a plurality of external electrodes which is formed on the rewiring layer so as to be integral with the semiconductor substrate, the plurality of external electrodes being connected to the plurality of electrode pads via the rewiring, the external electrodes making connection terminals for the external circuit, 2N−2 of the plurality of external electrodes, N being a positive integer; and 2N−2 of the plurality of the electrode pads; wherein the 2N−2 of the plurality of external electrodes are arranged in a first group of external electrodes and a second group of external electrodes; the first group of external electrodes comprises N external electrode arranged along an edge of the semiconductor substrate; the second group of external electrodes comprises N−2 external electrodes arranged inside the first group of external electrodes; and the 2N−2 of the plurality of electrodes pads are arranged between the first group of external electrodes and the second group of external electrodes, and each of the 2N−2 of the plurality of electrode pads is connected to an external electrode included of either the first group of external electrodes or the second group of external electrodes via the rewiring.