Patent ID: 7669014

Claim:
A transpose memory circuit, comprising: a number of dual port memory blocks each having a plurality of storage cells each configured for storing at least one data word, wherein the dual port memory blocks represents a storage array for storing at least one input matrix and outputting at least one input matrix in transposed form; a data input configured to receive data words on each cycle; a data output configured to output data words on each cycle; a read address logic configured to generate read addresses to address one cell of each dual port memory block to be read out on each cycle; and a write address logic configured to generate write addresses to address one cell of each dual port memory block to be written on each cycle; wherein in each cycle, one storage cell of each dual port memory block is addressed by the read address logic, which data words stored in the addressed storage cells are read out from one dual port memory block and outputted through the data output; wherein in each cycle, one storage cell of each dual port memory block is addressed by the write address logic, which storage cells have been read out in a preceding cycle and into which storage cells data words received through the data input are written; wherein the transpose memory circuit is configured to receive the input matrix and to output the input matrix in transposed form in subsequent cycles without any dead cycles interposed between them.