Patent ID: 6850103

Claim:
A CMOS data latch circuit having low leakage current drain comprising: a data input; a first clocked transfer gate including transistors with nominal gate length having an input connected to said data input of the data latch circuit and an output connected to an output of the data latch circuit, said first clocked transfer gate clocked by a functional clock signal and an inverse functional clock signal; a second clocked transfer gate including transistors with long gates longer than said nominal gate length having an input connected to said output of said first clocked transfer gate and an output, said second clocked transfer gate clocked by a sleep signal and an inverse sleep signal; a first CMOS latch inverter having an input connected to said output of said second clocked transfer gate and an output, said first CMOS latch inverter including a serial connection of a PMOS long gate transistor and a NMOS long gate transistor connected between a power supply and ground; and a second CMOS latch inverter having an input connected to said output of said first CMOS latch inverter and an output connected to said input of said first CMOS latch inverter, said second CMOS latch inverter including a serial connection between said power supply and ground of a PMOS long gate transistor having a source-drain path connected between said power supply and a first intermediate node and a gate connected to said output of said first CMOS latch inverter, a PMOS nominal gate transistor having a source-drain path connected between said first intermediate node and said output and a gate receiving said functional clock signal, a NMOS nominal gate transistor having a source-drain path connected between said output and a second intermediate node and a gate receiving said inverse functional clock signal, and a NMOS long gate transistor having a source-drain path connected between said second intermediate node and ground and a gate connected to said output of said first CMOS latch inverter.