Patent ID: 7009433

Claim:
A programmable logic device comprising: a master delay-locked loop adapted to receive a reference clock signal and provide a digital control signal, wherein the master delay-locked loop comprises; a series of delay cells adapted to receive the reference clock signal and provide delayed versions of the reference clock signal; a first multiplexer adapted to select either the reference clock signal or one of the delayed versions of the reference clock signal and provide a first output signal; a second multiplexer adapted to select either the reference clock signal or the first output signal and provide a clock output signal from the master delay-locked loop; a third multiplexer adapted to select either the reference clock signal or the first output signal and provide a second output signal; a fourth multiplexer adapted to select either the reference clock signal or a feedback signal received by the master delay-locked loop and provide a third output signal; and a control logic circuit adapted to receive the second output signal and the third output signal and generate the digital control signal; a plurality of signal paths; and a plurality of slave delay cells disposed respectively within the plurality of signal paths and adapted to receive the digital control signal and provide a signal delay based on the digital control signal.