Patent ID: 8072833

Claim:
A semiconductor memory device comprising: a first write bit line; a second write bit line; a write word line; a first read bit line; a read word line; and a memory cell array comprising a plurality of memory cells in a matrix; wherein the memory cells comprising: a first inverter comprising a first PMOS transistor and a first NMOS transistor; a second inverter comprising a second PMOS transistor, and a second NMOS transistor, and comprising an input terminal and an output terminal connected to an output terminal and an input terminal of the first inverter, respectively; a first write transfer transistor connected between a first write bit line and the output terminal of the first inverter, and comprising a gate connected to a write word line; a second write transfer transistor connected between a second write bit line and the output terminal of the second inverter, and comprising a gate connected to the write word line; a first read driver transistor comprising a gate connected to the input terminal of either the first inverter or the second inverter; and a first read transfer transistor connected to a first read bit line through the first read driver transistor, and comprising a gate connected to a read word line, the first read transfer transistor shared by at least two of the memory cells in the memory cell array.