Patent ID: 8667438

Claim:
A modified latching circuit in which component sizes of an initial latching circuit design are altered to achieve reduced sequential overhead comprising: said initial latching circuit design having a first set of combinational logic that has a first set of device widths that exhibit: first large rising data setup times that are not the same as first large falling data setup times; a first rising clock to Q delay for said first rising data setup time that is not the same as a first falling clock to Q delay for said first falling data setup time; said modified latching circuit having a second set of combinational logic in which device widths of said second set of combinational logic are modified to exhibit: second rising data setup times that are substantially equal to second falling data setup times; a second rising clock to Q delay for said second rising data setup times that is substantially equal to a second falling clock to Q delay for said second falling data setup times; wherein said second rising data setup times and said second falling data setup times being substantially equal, and second rising clock to Q delay and said second falling clock to Q delay being substantially equal achieves said reduced sequential overhead.