Patent ID: 8866830

Claim:
An integrated circuit, comprising: a memory controller comprising: a) a memory interface having a data bus; b) a first datapath between said memory interface and a cache unit that is coupled to multiple processors; c) a second datapath between said memory interface and a graphics controller; d) logic circuitry to: i) treat said data bus as part of a single data channel for a first memory accessing process whose data content is passed over said first datapath; ii) treat different parts of said data bus as respective parts of multiple data channels for a second memory accessing process whose data content is passed over said second datapath, each of said multiple data channels having a smaller physical data bus width than said single data channel; iii) generate additional addressing information for said second memory accessing process as compared to said first memory accessing process, wherein said additional addressing information appears on any of i) through iv) below: i) additional addressing lines that emanate from said memory interface and that are dedicated for said second memory accessing process but not said first memory accessing process; ii) unused ECC lines of said single data channel; iii) address lines that are unused when a column address strobe is asserted; iv) unused ECC pins of a memory module coupled to said memory interface.