Patent ID: 7327613

Claim:
An input circuit for a memory device, comprising: 2N data buffers for receiving data applied from an outside; N input multiplexers; and 2N data bus writers; wherein a pair of data buffers among the 2N data buffers are connected to one of the N input multiplexers, respectively; the respective input multiplexer is connected to a pair of data bus writers among the 2N data bus writers; and a certain pair of the i-th and (i+1)-th data buffers among the 2N data buffers correspond to the k-th input multiplexer and the k-th input multiplexer corresponds to the i-th and (i+1)-th data bus writers; and wherein (a) if first data and second data are outputted from the i-th and (i+1)-th data buffers, the k-th input multiplexer transfers the first data to the i-th data bus writer, and the second data to the (i+1)-th data bus writer; and (b) if a third data is outputted from only one of the i-th and (i+1)-th data buffers, the k-th input multiplexer selectively transfers the third data to one of the i-th and (i+1)-th data bus writers, and the k-th input multiplexer operates so that a transfer path of the third data is determined by a one-clock-delayed block column address in comparison to a column address inputted by a write command.