Patent ID: 8341575

Claim:
A circuit design device designing a circuit that includes a plurality of paths subjected to a restriction regarding the relative amounts of their delay times, termed “relative delay restriction” hereinafter, the circuit design device comprising: a statistical timing analysis unit that derives a probability distribution of delay times of each path included in the circuit; a relative delay restriction fulfillment rate calculation unit that derives a fulfillment rate of the relative delay restriction by integrating a region of a joint distribution of the probability distributions of delay times of a pair of paths, termed “restricted path pair” hereinafter, subjected to the relative delay restriction, wherein the region satisfies the relative delay restriction; a path delay probability distribution changing unit that changes the probability distribution of delay times of each path of the restricted path pair to a changed probability distribution when the fulfillment rate does not reach a predetermined rate; and a logic circuit structure changing unit that changes the structure of the circuit with reference to the changed probability distribution.