Patent ID: 6914828

Claim:
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix, a read circuit for reading out simultaneously data of 2 N (N≧2) memory cells in said plurality of memory cells based on an externally applied column address for output onto 2 N data bus pairs; and an output circuit for sequentially setting in order the data of said 2 N data bus pairs in K (2≦K≦N) stages based on said externally applied column address, wherein said read circuit simultaneously reads out data of memory cells specified by column addresses all having common upper bits but the least significant N bits, said common upper bits being identical to all upper bits but the least significant N bits of said externally applied column address, and said output circuit comprises a plurality of switch circuits corresponding to each said stage, said plurality of switch circuits setting in order the data of said 2 N data bus pairs in said stages based on a value of 1 or a plurality of bits for each said stage among the least significant N bits of said externally applied column address.