Patent ID: 7176729

Claim:
A semiconductor integrated circuit comprising: an output circuit comprising plural output MOSFETs connected in parallel, said output MOSFETs connected in parallel being divided into plural groups and said plural groups being respectively divided into plural subgroups; a first control means that, from among the plural output MOSFETs, selects the number of output MOSFETS to be turned ON to control output impedance and forms selection signals; a second control means that controls a slew rate by controlling a drive signal of the output MOSFETs that are turned ON and forms timing signals; and plural output prebuffers each of which is coupled to each of said output MOSFETs; wherein said plural output prebuffers receives each of said selection signals, said timing signals and data signals to be outputted and drives each of said plural output MOSFETs, and wherein said first control means controls output impedance and said second control means controls a slew rate and wherein said first control means and said second control means perform their respective control independently.