Patent ID: 7349405

Claim:
A packet scheduling apparatus, comprising: an input device for receiving incoming data packets belonging to at least one session; a bank of memories comprising memory sets for storing the incoming data packets, the memory sets having a nominal service-interval in which time a data packet is to be transmitted, the nominal service-interval of one memory set being faster than the nominal service-interval of another memory set; an output device for transmitting the stored data packets; a processing element linked to the input device, the output device and the bank of memories for scheduling sessions for being serviced until the nominal service-interval of any other of the memory sets where there is at least one data packet to be sent, is exceeded; a timing unit for measuring the service-interval in accordance with virtual time, which virtual time is incremented in accordance with the time for transmission of the latest packet sent; each memory set having a current session list memory and at least one new session list memory for holding data packets; input means for inputting arriving data packets into the memory sets, data packets having a required service-interval; a timing unit for holding a virtual time value; means for swapping the content of the new session list memories into the current session list memories at integer values of the virtual time value, for memory sets which may receive service at that virtual time value, if the current session list memory for that memory set is empty, and a MissedSwaps counter for that memory set to be increased if the current session list memory for that memory set was not empty; means for transmitting data packet from a current session list memory; and a scheduler for scheduling transmission of a next data packet from that memory set based on the required service-interval of the previous data packet and a service interval it was actually given, and on the value of the MissedSwaps counter.