Patent ID: 7634709

Claim:
Apparatus for detecting and correcting errors in a 128 bit word stored in multiple 4-bit RAMs of a RAM memory, said apparatus comprising: a check bit generator to generate 16 check bits from said 128 bit data word, said check bits to detect all double-bit errors that occur in said word, to detect multi-bit uncorrectable errors occurring in said word, and to detect and correct all possible combinations of familial errors occurring in bits of said word stored in any one of said 4-bit RAMs; a check bit regenerator to regenerate 16 check bits from said 128 bit data word after said data word is retrieved from said RAM memory; a syndrome generator for generating 16 syndrome bits based on a comparison between said generated check bits and said re-generated check-bits, said syndrome bits to determine whether any errors that are detectable by said check bits have occurred.