Patent ID: 8426275

Claim:
A fabrication method of a trenched power MOSFET, at least comprising steps of: forming a pattern layer having a first opening on a substrate; removing a portion of the substrate by using the pattern layer as a mask, so as to form a gate trench in the substrate; expanding a width of the gate trench; after the step of expanding the width of the gate trench, forming a gate oxide layer on an inner surface of the gate trench; after the step of forming the gate oxide layer, removing a portion of the gate oxide layer on a bottom of the gate trench by using the pattern layer as a mask, so as to form a second opening exposing the substrate and located in the gate oxide layer, wherein a width of the expanded gate trench is greater than a width of the second opening; forming a thick oxide layer in the second opening; forming two first heavily doped regions at two sides of the thick oxide layer; forming a gate polysilicon structure in the gate trench; forming a body layer to surround the gate trench; and forming two source doped regions at two sides of the gate trench.