Patent ID: 8443230

Claim:
A method for redundant operation of a plurality of processors, the plurality of processors including at least a first processor and a second processor, the method comprising: executing a same set of instructions in parallel on the first and second processors, each of the first and second processors coupled to a respective first and second status registers; polling only the first status register for indication of a first transaction for a peripheral device being issued from execution of an instruction by the first processor; and in response to the first status register indicating the first access transaction, performing steps including: suspending operation of the first processor; polling the second status register for indication of a second access transaction being issued from execution of the instruction by the second processor; in response to the second status register indicating the second transaction and in response to the first access transaction being a write transaction, waiting to issue the write transaction to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction; and in response to the second status register indicating the second transaction and in response to the first access transaction being a read transaction, waiting to issue the read transaction to the peripheral device until the second processor executes the instruction.