Patent ID: 6849535

Claim:
A manufacturing method of a semiconductor integrated circuit device, comprising the steps of: (a) forming a first interconnection groove in a first interlayer insulating film over a first main surface of a wafer; (b) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection groove; (c) forming a first interconnection metal film containing copper as a main component over the first barrier metal film both outside and inside the first interconnection groove so as to fill the first interconnection groove; (d) removing the first interconnection metal film outside the first interconnection groove by first chemical mechanical polishing using a first polishing slurry; (e) after step (d), removing the first barrier metal film outside the first interconnection groove by second chemical mechanical polishing using a second polishing slurry different from the first polishing slurry in composition; (f) after step (e), performing ammonia plasma treatment to upper surfaces of both the first interlayer insulating film and the first interconnection metal film; and (g) after step (f), forming a copper diffusion barrier insulating film on the treated upper surfaces by plasma CVD.