Patent ID: 6924527

Claim:
A non-volatile memory cell, comprising: a semiconductor substrate; a well region implanted with a first-type dopant formed in the semiconductor substrate; a first doped region implanted with a second-type dopant formed in the semiconductor substrate; a second doped region, formed spaced-apart from the first doped region, implanted with the second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, wherein the well region, the second doped region, and the third region are arranged to form a parasitic transistor; a first dielectric layer disposed over the semiconductor substrate; a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region; a second dielectric layer disposed over the floating gate; and a control gate disposed over the first dielectric layer and the second dielectric layer.