Patent ID: 8320440

Claim:
An equalizer circuit configured to receive amplitude data A[N] which represents the amplitude level of an N-th (N is a nonnegative integer) signal to be transmitted via a transmission line and timing data T[N] which represents the cycle of the signal, and to perform waveform shaping, comprising: M (M is an integer) calculation units; and a first adder configured to add output data of the M calculation units and the amplitude data A[N] so as to generate equalized amplitude data, wherein a step response waveform R STEP (t) for the transmission line is approximated by Expression R STEP (t)=S STEP(t) ·( 1−Σ j=1:M f j (t)) using M functions f j (t) (1≦j≦M) and a step waveform S STEP (t) with time t as an argument, and wherein a representative value of the function f j (t) in a range between T 1 and T 2 is represented by a function g j (T 1 , T 2 ), and wherein the j-th (1≦j≦M) calculation unit calculates output data D j [N] represented by Expression D j [N]=Σ n=0:N [(A[n]−A[n−1])·g j (t N −t n , t N+1 −t n )].