Patent ID: 8516164

Claim:
A data storage system comprising: a controller for implementing an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, said controller comprising a plurality of hardware engines; a processor; a control store configured to store a plurality of control blocks; each control block designed to control a hardware operation in one of the plurality of hardware engines; a global work queue including a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations and to minimize hardware and firmware interaction, said global work queue having a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines; said control blocks arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and said control blocks arranged in an event queue to provide completion results to the processor; said control blocks being selectively linked to a plurality of other control blocks, providing parallel dispatch of controls applied to respective hardware engines running on different steps for the same function; and a work queue manager coupled to said queue input of said global work queue, said work queue manager configured to build a respective predefined chain controlling the hardware operations for a predefined hardware function.