Patent ID: 8443262

Claim:
An apparatus, comprising: an error detection system (EDS) that detects an error event in a volatile memory, wherein the error event involves at least one bit in the volatile memory changing states erroneously; a scrub logic to scrub the volatile memory to correct an error in the volatile memory; and a scrub rate adaptive logic (SRAL) to selectively control a memory scrub frequency associated with the scrub logic by comparing a number of error events detected by the EDS during an error checking interval (ECI) to a plurality of error count thresholds, wherein each of the plurality of error count thresholds is associated with a respective scrub frequency change, and wherein the SRAL varies the memory scrub frequency based on a rate derived from at least one of the respective scrub frequency changes associated with at least one of the plurality of error count thresholds satisfied by the number of error events, wherein the SRAL adjusts at least one of (i) the ECI and (ii) one or more of the plurality of error count thresholds upon determining one of the plurality of error count thresholds is exceeded.