Patent ID: 7856072

Claim:
A semiconductor device comprising: an input node supplied with a data signal; a detection circuit comparing the data signal with a reference voltage to generate a detection signal that takes a first logic level when a level of the data signal is within a first level region that is larger in absolute value than a level of the reference voltage and a second logic level that is smaller in absolute value than the level of the reference voltage; and a control circuit checking the detection signal each time a clock signal is supplied to the control circuit and changing, in response to a change in logic level of the detection signal caused by a change in the level of the data signal in a first direction from one of the first and second level regions to the other of the first and second level regions, the level of the reference voltage in a second direction opposite to the first direction such that the one of the first and second level regions is made narrow and the other of the first and second level regions is made wide.