Patent ID: 7974262

Claim:
A telecommunications network participant, comprising an analog to digital converter arranged to digitise, as a series of samples, a received signal containing a succession of symbols, and a digital signal processor arranged to measure time misalignment between the symbols and the samples and arranged to apply a fractional delay to the positions of the samples to reduce the misalignment, wherein the received signal has a format such that the symbols are arranged in bursts and the digital signal processor is arranged to deduce for each of one or more bursts a respective timing error and is arranged to apply a fractional delay to suppress the timing error or errors, wherein the received signal has a format in which the bursts are grouped into a repeated time frame, the time frame containing a number of time slots, each time slot containing a burst and, for each of a plurality of said time slots, the digital signal processor is arranged to deduce a timing error for each of one or more bursts in the respective slot and to apply a fractional delay to suppress the timing error or errors of the respective slot, and wherein for each of a plurality of said time slots, the digital signal processor is arranged to deduce a timing error for each of several bursts in the respective slot, to combine the errors to produce a resultant error for the respective slot and to apply a fractional delay to suppress the resultant error of the respective slot.