Patent ID: 6845035

Claim:
A semiconductor memory device comprising: a memory cell array formed of a plurality of memory cells arranged in rows and columns, and each provided with first and second transistors having gate electrodes and impurity regions forming sources/drains as well as one capacitor, bit lines corresponding to said plurality of columns and word lines corresponding to said plurality of rows; and a sense amplifier connected to said bit lines and used for amplifying a signal for normal access to said memory cells and refresh, wherein said first transistor is arranged as a transistor for normal access to be used for the normal access and not to be used for the refresh access, said second transistor is arranged as a transistor for refresh to be used for the refresh access and not to be used for the normal access, and said semiconductor memory device employs a background refresh system for automatically refreshing said memory cell regardless of presence and absence of a refresh signal when said access sense amplifier is operating.