Patent ID: 8837248

Claim:
A memory controller, comprising: a host interface, configured to couple to a host system; a memory interface, configured to couple to a non-volatile memory module, wherein the non-volatile memory module includes a plurality of physical blocks and the physical block is grouped into at least a data area and a spare area; a memory management circuit, coupled to the host interface and the memory interface; and a buffer memory, coupled to the memory management circuit and configured to temporarily store data from the host system; wherein the memory management circuit is configured to get a physical block from the spare area and write the data stored temporarily in the buffer memory into the gotten physical block after receiving a signal, wherein the signal is a detection signal indicating that the input voltage is smaller continuously than a predetermined voltage for a predetermined period, a detection signal indicating that an inactive status of the connector, or a suspend mode signal, a warm reset signal or a hot-reset signal from the host system.