Patent ID: 7948258

Claim:
A semiconductor arrangement comprising: a semiconductor body having a semiconductor layer with a first and at least one second conducting terminal areas, each formed in two parts, and with first and second test terminal areas; first and at least one second contact areas, located on the semiconductor body and each formed in two parts, a first part of the first conducting terminal area being connected with a first part of the first contact area, a second part of the first conducting terminal area being connected with a second part of the first contact area, a first part of the at least one second conducting terminal area being connected with a first part of the at least one second contact area, a second part of the at least one second conducting terminal area being connected with a second part of the at least one second contact area, and a first and a second test contact area connected with the respective first and second test terminal areas; a first terminal, arranged on the semiconductor body in contact with both parts of the first contact area formed in two parts, and at least one second terminal arranged on the semiconductor body in contact with both parts of the at least one second contact area formed in two parts; and first and second test terminals, arranged on the semiconductor body, the first test terminal being connected with the first test contact area and the second test terminal being connected with the second test contact area; wherein the semiconductor arrangement is configured to measure a low resistance between the first terminal and the at least one second terminal.