Patent ID: 8248094

Claim:
A test structure for gathering switching history effect statistics for semiconductor devices, the test structure comprising: a waveform generator circuit configured to selectively generate a first test waveform representative of a first type (1SW) transistor switching event, and a second test waveform representative of a second type (2SW) transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to both the DUT and the variable delay chain; wherein the history element circuit is configured to determine a fractional change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator included within a delay calibration unit; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip on which the waveform generator circuit, the history element circuit and the delay calibration unit are formed.