Patent ID: 7050467

Claim:
A digital-to-phase converter, comprising: a delay line having a plurality of delay taps; a multiplexor coupled to the delay line, the multiplexor having a plurality (N) of input ports for receiving the plurality of delay taps and an output port for providing an output signal and an input port for receiving an n-bit binary word (IN); a synchronization circuit having a first input port for receiving the output signal from the multiplexor and a second input port for receiving a trigger signal, the synchronization circuit further having an output port for providing an output signal only when the synchronization circuit is gated by the trigger signal (TRIG); and a reference clock providing a reference signal (REF) to the delay line and the synchronization circuit, wherein the reference signal (REF) is a pulse train having rising and falling edges and the synchronization circuit forms an aperture region when IN<=N/2 that begins on the first rising edge of the reference signal (REF) after the first rising edge of the trigger signal (TRIG) signal and remains active for a predetermined period thereafter.