Patent ID: 7687331

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a lower transistor on a semiconductor substrate; forming a lower interlevel insulation film on the semiconductor substrate, the lower interlevel insulation film covering the lower transistor; forming an upper transistor on the lower interlevel insulation film over the lower transistor, wherein forming the upper transistor comprises; patterning the lower interlevel insulation film to form an epitaxial contact hole partially exposing the semiconductor substrate; growing an epitaxial layer having a crystalline structure in the epitaxial contact hole from the exposed semiconductor substrate; forming an amorphous silicon layer on the lower interlevel insulation film; converting the amorphous silicon layer into the same crystalline structure as the epitaxial layer to form a body pattern; forming source and drain regions for the upper transistor in the body pattern; and forming a gate electrode on the body pattern; forming an upper interlevel insulation film on the lower interlevel insulation film, the upper interlevel insulation film covering the upper transistor; forming a first contact plug connected to a source or drain region of the upper transistor and penetrating the upper interlevel insulation film; and forming a second contact plug connected to a drain or source of the lower transistor and penetrating the upper and lower interlevel insulation films and electrically connected to the first contact plug.