Patent ID: 7596680

Claim:
A method comprising: encoding ordered tuples of register specifiers of addressable registers for specifying a plurality of fields of an instruction of fixed length, wherein each ordered tuple comprises all the register specifiers in the instruction; loading into an indirection table a plurality of entries that encode register patterns for registers used by the instruction, each entry specifying one of the ordered tuples of register specifiers, wherein an amount of the addressable registers is specified by a width of each field of the entry in the indirection table; fetching the instruction from memory for processing, wherein said instruction is fetched in an architected instruction width specified by an instruction set architecture; determining whether the instruction is to be processed in compatibility mode or in extended mode; if the instruction is to be processed in compatibility mode, extending the register specifiers to implementation width by padding the registers with zeroes to the left; if the instruction is to be processed in extended mode: extracting a first field of the instruction as specified by the instruction set architecture; using the first field to index into the indirection table; and obtaining the register specifiers from the indirection table entry, wherein the register specifiers from the indirection table entry are extended to implementation width; merging an appropriate number of extended register specifiers with remaining components of the instruction into an expanded instruction for further instruction processing; and providing the extended register specifiers for subsequent processing of the expanded instruction.