Patent ID: 7710764

Claim:
A semiconductor device, comprising: a word line; a plurality of data line pairs across the word line; a plurality of P-type wells and a plurality of N-type wells, the P-type wells and the N-type wells being alternately formed in a direction in which the word line extends; a plurality of SRAM memory cells each connected with the word line and a corresponding one of the plurality data line pairs, and each having a plurality of MOS transistors which are formed in two of the plurality of P-type wells and one of the plurality of N-type wells, each of the plurality of the P-type wells being shared with two adjacent memory cells among the plurality of SRAM memory cells; a Y switch circuit connected with the plurality of data line pairs; an error correction circuit receiving data selected by the Y switch circuit, wherein the adjacent two memory cells among the plurality of SRAM memory cells are selected by the Y switch circuit at a time different from each other and data read out from the adjacent two memory cells among the plurality of SRAM memory cells are inputted to the error correction circuit at a time different from each other.