Patent ID: 6901567

Claim:
A method of performing timing-driven layout of a circuit, comprising the steps of: (a) generating an initial layout result through placement of functional blocks of the circuit and routing of wiring lines for the blocks; (b) calculating wiring capacitance values of the respective blocks using the initial layout result; (c) calculating fan-out capacitance limitation values of the respective blocks using the wiring capacitance values of the blocks calculated in the step (b); each of the fan-out capacitance limitation values representing a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value; (d) forming a replaceable block library of replaceable functional blocks while taking their fan-out capacitance limitation values generated in the step (c) into consideration; the replaceable blocks being divided into different block types each having a same function generated by different circuit configurations; each of the block types having different propagation delay values and different driving capabilities; (e) comparing a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result; (f) defining the blocks whose driving capabilities do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and (g) replacing each of the timing-error blocks with a corresponding one of the replaceable blocks having the same function to change its circuit configuration without changing its function, thereby decreasing its propagation delay.