Patent ID: 6857107

Claim:
A layout method for an LSI having a plurality of cells, comprising: performing automated arrangement of cells on a chip on the basis of a netlist, which has a plurality of cells and connection data therefor, and cell timing conditions data; generating wiring connecting said cells with alleviating conditions for short circuits between wiring; optimizing a timing of the cells in accordance with the signal propagation time of the wiring connecting said automatically arranged cells; seeking a congestion rate of said wiring, and detecting regions for which the congestion rate is higher than a reference level; performing rearrangement processing of said cells in a small associated region for which the congestion rate is higher than the reference level, said chip being divided into a plurality of small associated regions; and generating wiring connecting the cells, after said cell rearrangement processing, such that short circuits between wiring are forbidden, wherein, after performing rearrangement processing of the cells in the small associated region for which the congestion rate is higher than the reference level, wiring congestion rate analysis is performed once again, and in a case wherein the congestion rate does not exceed the reference level, the generating wiring connecting the cells is performed such that short circuits between wiring are forbidden, and wherein, in a case in which there is a region for which the congestion rate exceeds the reference level, a size of said small associated region increased to perform the cell rearrangement processing once again.