Patent ID: 7944261

Claim:
Apparatus for detecting loss of a feedback clock signal input to a clock circuit comprising: a clock divider configured to produce a divided feedback clock signal from the feedback clock signal, the feedback clock signal being derived from a reference clock signal by a digital clock manager (DCM) and delayed by a clock network coupled to the DCM; a first pair of flip-flops configured to store samples of the divided feedback clock signal on consecutive active edges of the reference clock signal; a second pair of flip-flops configured to store samples of the divided feedback clock signal on consecutive active edges of an inversion of the reference clock signal; and a detection circuit configured to detect whether each of the first pair of flip-flops and each of the second pair of flip-flops store the same value, wherein the detection circuit reports the loss of the feedback clock signal if the samples in the first pair of flip-flops are the same value and the samples in the second pair of flip-flops are the same value; wherein a frequency of the feedback clock signal is either the same as a frequency of the reference clock signal or a multiple of the frequency of the reference clock signal, and wherein the clock divider divides the feedback clock signal by a factor of at least two.