Patent ID: 7888226

Claim:
A method of fabricating a power semiconductor device comprising a first region in which a transistor is formed, a third region in which a control element is formed, and a second region arranged between the first region and the third region to electrically separate the transistor from the control element, the method comprising: forming a first mask layer pattern covering a partial surface of the second region adjacent to the third region on a substrate of a first conductive type; implanting impurity ions of a second conductive type on the substrate with a first ion implantation process using the first mask layer pattern as an ion implantation mask; forming a highly-doped buried layer of a second conductive type arranged in the first region and the third region and extending to the second region from the first region by removing the first mask layer pattern and diffusing the implanted impurity ions; forming a second mask layer pattern to expose a surface of the first region and a surface of a portion where the highly-doped buried layer is not formed in the second region, on the substrate; implanting impurity ions of a first conductive type on the substrate with the second ion implantation process using the second mask layer pattern as an ion implantation mask; forming a first highly-doped bottom layer of a first conductive type arranged in the first region and the third region and extending to the second reigon from the first region by removing the first mask layer pattern and diffusing the implanted impurity ions and a second highly-doped bottom layer of the first conductive type separated from the highly-doped buried layer in the second region; and forming a semiconductor region on the substrate.