Patent ID: 6934214

Claim:
A semiconductor memory device comprising: a memory bank area including a plurality of memory array areas arranged in a first direction, a plurality of sense amplifier areas arranged alternately relative to the plurality of memory array areas, and a plurality of first local input/output lines provided corresponding to the plurality of first sense amplifier areas and extending in a second direction intersecting the first direction; a plurality of first sub-amplifiers arranged along the memory bank area in the first direction, each of the plurality of first sub-amplifiers being connected to a corresponding one of the plurality of the first local input/output lines; and a first main input/output line including a first line extending in the first direction and a second line extending in the second direction and directly connected to the first line, wherein each of the plurality of memory array areas has a plurality of dynamic memory cells provided at intersections between a plurality of word lines and a plurality of data lines, wherein the first line is connected to the plurality of first sub-amplifiers, and wherein the second line passes through at least one of the plurality of memory array areas.