Patent ID: 7067366

Claim:
A method of fabricating first and second field effect transistors (FETs) of an integrated circuit such that said first FET has different spacings between the gate and the source and drain regions thereof than said second FET, comprising: forming a first gate stack and a second gate stack overlying a main surface of a substrate; forming first spacers and second spacers on each of said first and second gate stacks, each of said first spacers having an “L” shape, each said first spacer including a vertically extending portion oriented in a vertical direction generally perpendicular to said main surface, and a horizontally extending portion oriented in a horizontal direction parallel to said main surface, said horizontally extending portion having an edge horizontally displaced from a wall of said vertically extending portion, each of said second spacers extending along said walls of said vertically extending portions, said second spacers overlying said horizontally extending portions of said first spacers; implanting source and drain regions of said first FET aligned to said edges of said horizontally extending portions of said first spacers of said first gate stack; removing said second spacers and said horizontally extending portions of said first spacers by an anisotropic vertical etch process after forming said source and drain regions of said first FET; and implanting source and drain regions of said second FET in said substrate aligned to said walls of said vertically extending portions of said first spacers of said second gate stack after removing said horizontally extending portions.