Patent ID: 7510963

Claim:
A method for manufacturing a semiconductor device, the method comprising: forming a gate electrode on a semiconductor substrate; forming an interlevel dielectric (ILD) layer on the semiconductor substrate; forming a first stud hole in the ILD layer on a first side of the gate electrode, the first stud hole having a width at an entrance part adjacent to the surface of the ILD layer larger than a width at a contacting part adjacent to the semiconductor substrate; forming a second stud hole in the ILD layer on a second side of the gate electrode that is opposite the first side of the gate electrode, the second stud hole spaced apart from the first stud hole in the ILD layer, the width at the entrance part of the first stud hole on the first side of the gate electrode being larger than a width at an entrance part of the second stud hole at the second side of the gate electrode; forming first and second contact studs on the first and second sides of the gate electrode, respectively, by filling the first stud hole and the second stud hole with a conductive material, wherein forming the first stud hole and forming the second stud hole comprises: forming a plurality of first holes by etching a portion of the ILD layer to a shallower depth than that of the ILD layer; and forming a plurality of second holes for etching part of the ILD layer positioned under the first hole selected from the plurality of first holes and a portion of the ILD layer on which the plurality of first holes are not formed and exposing the semiconductor substrate; forming a conductive landing pad having a lower surface of a width larger than a width of a top of the second contact stud that is in direct physical contact with the ILD layer, and that is in contact with the second contact stud.