Patent ID: 8339869

Claim:
A semiconductor device comprising: a first circuit operated in synchronization with a first clock signal; a second circuit operated in synchronization with a second clock signal of lower frequency than the first clock signal, and including a register; a third circuit operable to receive data from the register of the second circuit; and a bridge circuit operable to control timing of an access from the first circuit to the second circuit, and operable to provide signals to the third circuit in response to the access from the first circuit, wherein the third circuit provides the data from the register to the bridge circuit in synchronization with the first clock signal in response to the signals from the bridge circuit, wherein the first circuit is a central processing unit, the second circuit is a peripheral circuit, and the third circuit is a timing control circuit, wherein the register of the second circuit is operable to have information for determining a cause of interrupt, and wherein the third circuit provides the information in the register to the bridge circuit in synchronization with the first clock signal, in response to the signals from the bridge circuit after the first circuit detects an interrupt.