Patent ID: 7163891

Claim:
A method of forming a semiconductor structure having an array portion and a peripheral support portion, said method comprising: providing a silicon substrate; oxidizing the substrate to form a gate oxide layer; depositing a gate conductor layer over the gate oxide layer; depositing a gate cap insulator over the gate conductor layer; etching at least one gate stack from the gate conductor and gate cap insulator, said gate stack having a top and sidewalls; depositing a gate spacer layer and etching gate spacers along said sidewalls of the gate stack; implanting at least one source and drain through said gate oxide layer into said substrate; depositing a first dielectric layer on the silicon substrate; depositing a second dielectric layer over the first dielectric layer; forming at least one borderless array contact opening and at least one peripheral contact-to-diffusion opening simultaneously using a selective etching process, using a first etching mask; forming at least one contact to the gate using an etching process nonselective to the gate cap and the gate spacers, using a second etching mask; depositing a metallization mask over the second dielectric layer and patterning the metallization mask; etching metallization lines into the second dielectric layer and stripping the metallization mask; depositing a conductive layer over the metallization lines, said conductive layer filling said gate array contact, said peripheral contact-to-diffusion, and said gate contact; and planarizing the conductive layer.