Patent ID: 7657774

Claim:
An electronic system, comprising: at least one substrate comprising at most two conductive layers spaced from each other by a dielectric layer; an execution engine electrically coupled to a first conductor extending partially across one of the two conductive layers, wherein the execution engine is adapted to receive a first clock signal which cycles at a first clock rate; a memory controller electrically coupled to a second conductor extending partially across one of the two conductive layers, wherein the memory controller is adapted to receive one of the first clock signal or a second clock signal which cycles at a second clock rate less than the first clock rate; and wherein the execution engine comprises: a configuration register adapted to store a logic value; a multiplexer coupled to receive the first clock signal and the second clock signal; and a latch having an input coupled to the configuration register and an output coupled to a select input of the multiplexer for selecting the second clock signal in lieu of a first clock signal depending on a logic voltage value stored within the configuration register, wherein the multiplexer is adapted to provide to the memory controller a selected clock signal that is one of the first clock signal and the second clock signal.