Patent ID: 8225051

Claim:
A data processing apparatus for performing write and read operations simultaneously, comprising: a memory that includes and second memory blocks, the first memory block having a first user data area, a first setting data area storing a first flag data, and the second memory block having a second user data area, a second setting data area storing a second flag data, respectively; and a memory controller that compares between the first and second flag data to determine one of the first and second memory blocks for a write operation, wherein in a first state, the memory controller performs the write operation to write a first data to the second user data area and updates the second flag data to a first value, wherein in a second state following the first state, the memory controller performs the write operation to write a second data to the first user data area and updates the first flag data to the first value, wherein in a third state following the second state, the memory controller performs the write operation to write a third data to the second user data area based on a result of the comparing between the first and second flag data, and updates the second flag data to a second value, wherein in a fourth state following the third state, the memory controller performs the write operation to write a fourth data to the first user data area based on a result of the comparing between the first and second flag data, and updates the first flag data to the second value, and wherein in a fifth state following the fourth state, the memory controller performs the write operation to write a fifth data to the second user data area based on a result of the comparing between the first and second flag data, and updates the second flag data to the first value.