Patent ID: 7577882

Claim:
A semiconductor integrated circuit comprising: a plurality of memory macros and a redundant memory macro for repairing the plurality of memory macros, each of the plurality of memory macros comprising: a memory cell array connected to word lines and bit lines; and a redundant circuit that has means for replacing a defective bit line of the memory cell array by an adjacent normal bit line or a redundant bit line and outputs defect information to a redundant signal line; the redundant memory macro comprising: a redundant memory cell array connected to redundant word lines and the redundant bit line; and a word line connection circuit that transmits a signal of a word line corresponding to a memory macro to be repaired to a corresponding one of the redundant word lines with timing adjustment via a gate circuit, based on the defect information of the redundant signal line, so as to block a signal of a word line corresponding to a normal memory macro with the gate circuit; wherein the plurality of memory macros have a different number of word lines from each other, and a word line that is not used in the redundant memory macro is connected to a ground potential.