Patent ID: 8343812

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a lower insulation layer on a lower substrate; disposing an upper substrate on the lower insulation layer so that a bottom surface of the upper substrate contacts the lower insulation layer; forming a groove penetrating the upper substrate and into the lower insulation layer, the groove having a bottom surface that is lower than an interface between the upper substrate and the lower insulation layer and is higher than a bottom surface of the lower insulation layer; forming a contact device in at least a portion of the groove extending over the lower insulation layer; forming an upper insulation layer to cover the interface exposed in the groove, and to cover a top surface of the upper substrate opposite to the bottom surface of the upper substrate, wherein the top surface of the upper substrate directly contacts the upper insulation layer; forming a lower memory cell unit at the lower substrate; forming an upper memory cell unit at the upper substrate; wherein the upper insulation layer is disposed on the upper substrate and the upper memory cell unit to fill a bit line groove, wherein the lower memory cell unit is a lower NAND flash memory cell unit including a lower NAND string, and wherein the upper memory cell unit is an upper NAND flash memory cell unit including an upper NAND string; forming a first node groove and a second node groove, the first node groove penetrating the upper substrate between a bit line contact plug and the uppper NAND string to extend into the lower insulation layer, the second node groove penetrating the upper substrate adjacent to the upper NAND string and the opposite to the first node groove to extend into the lower insulation layer, the first and second node grooves each having a bottom surface lower than the interface; forming a first node plug and a second node plug, the first node plug penetrating the upper insulation layer in the first node groove to extend into the lower insulation layer and to be electrically connected to the lower substrate adjacent to a selection transistor and opposite to the bit line contact plug, the second node plug penetrating the upper insulation layer in the second node groove to extend into the lower insulation layer and to be electrically connected to the lower substrate between a ground selection transistor and the lower NAND string; and forming a first connector and a second connector, the first connector penetrating the upper insulation layer to electrically connect the upper substrate between the first node plug and the upper NAND string with the first node plug, the second connector penetrating the upper insulation layer to electrically connect the upper substrate between the second node plug and the upper NAND sting with the second node plug, wherein the first and second node grooves and the bit line groove are simultaneously formed.