Patent ID: 8482327

Claim:
A delay-locked loop circuit comprising: a voltage-controlled delay line configured to generate a plurality of delayed clock signals based on an input clock signal, a lock signal and a voltage control signal, the plurality of delayed clock signals being sequentially delayed from one another to produce an earliest delayed clock signal to a latest delayed clock signal, the voltage-controlled delay line including an anti-jitter delay circuit and a plurality of delay circuits, the anti-jitter delay circuit configured to output the earliest delayed clock signal, and the plurality of delay circuits coupled in series and configured to output a remainder of the plurality of delayed clock signals; a phase frequency detection circuit configured to generate an up signal and a down signal based on the earliest delayed clock signal and the latest delayed clock signal; a filter configured to generate the voltage control signal in response to the up signal and the down signal; and a lock detection circuit configured to generate the lock signal in response to the up signal and the down signal.