Patent ID: 6970392

Claim:
An apparatus comprising: a first set state machine configured to generate a first set-output signal that is either at a first logic state or at a second logic state in response to (i) a first read clock, (ii) a first write clock, (iii) a first programmable almost full look-ahead signal and (iv) a first control signal; a second set state machine configured to generate a second set-output signal that is either at said first logic state or at said second logic state in response to (i) a second read clock, (ii) a second write clock, (iii) a second programmable almost full look-ahead signal and (iv) a second control signal; a synchronizer configured to generate a synchronized output signal in response to said second set-output signal and a reset signal; a latch configured to generate (i) a first latch output signal in response to said first set-output signal and said synchronized output signal and (ii) a second latch output signal as a complement of said first latch-output signal, said first latch output signal representing an almost full output flag that is at said first logic state when a FIFO (First In First Out) memory block is almost full, and is at said second logic state when said FIFO is not almost full; a first logic block configured to generate said first control signal in response to said second latch output signal; and a second logic block configured to generate (i) said reset signal and (ii) said second control signal in response to said first latch output signal.