Patent ID: 6869834

Claim:
A method of forming at least one low temperature polysilicon thin film transistor (LTPS TFT) on an insulating substrate, the method comprising: forming at least one polysilicon layer (poly-Si layer) on a surface of the insulating substrate, a source region, a drain region, and a channel region of the low temperature polysilicon thin film transistor being comprised on a surface of the polysilicon layer; performing a first plasma enhanced chemical vapor deposition (PECVD) process and a second plasma enhanced chemical vapor deposition process to sequentially form a tetra-ethyl-ortho-silicate based silicon oxide layer (TEOS-based SiO x layer, where x≈2) and a silicon nitride layer (SiN x layer, where 1.0<x<1.6) on the channel region, the tetra-ethyl-ortho-silicate based silicon oxide layer situated on the surface of the polysilicon layer and the silicon nitride layer form a composite gate insulating layer; and forming a gate electrode on the composite gate insulating layer.