Patent ID: 8051301

Claim:
A memory management unit for managing a memory storing data arranged within a plurality of memory pages, the memory management unit comprising: a security check unit coupled to receive a linear address generated during execution of a current instruction, wherein the linear address has a corresponding physical address residing within a selected memory page, and wherein the security check unit is configured to use the linear address to access a paged memory data structure located in the memory to obtain a set of first security attributes of the selected memory page, wherein the set of first security attributes is used to determine whether the current instruction is authorized to access the selected memory page, and wherein the security check unit is configured to use the linear address to access at least one security attribute data structure located in the memory to obtain a second security attribute of the selected memory page, to compare a numerical value conveyed by a security attribute of the current instruction to a numerical value conveyed by the second security attribute of the selected memory page, and to produce an output signal dependent upon a result of the comparison; and wherein the memory management unit is configured to access the selected memory page dependent upon the output signal.