Patent ID: 8101511

Claim:
A method of manufacturing an integrated circuit including a junction barrier Schottky diode, the method including: forming a P-type anode region in a surface of an N-type well; forming a first mask with an opening exposing an N-type Schottky region of the surface of the well and adjoining portion of the anode region; applying a first material and forming a first silicide layer of the first material with the exposed portions of the Schottky and anode regions; forming a second mask with an opening exposing a portion of the anode region not having the first silicide layer; applying a second material different from the first material and forming a second silicide layer of the second material with the exposed portion of the anode region; and forming an ohmic contact to the second silicide layer on the anode region, and an ohmic contact to the well wherein the first and second silicide layers are formed spaced entirely from each other on the surface.