Patent ID: 8077526

Claim:
An integrated circuit device having configurable resources, the integrated circuit device configured as a memory controller that includes a plurality of bi-directional pins, an input buffer circuit that is operable to receive SSTL-compliant input and an output buffer that is operable to generate SSTL-compliant output, wherein the input buffer circuit includes a first single-ended buffer coupled to a first voltage level and to a ground voltage, the first single-ended buffer having an input coupled to one of the bi-directional pins and having an output coupled to control logic of the memory controller, wherein the input buffer circuit further comprises at least one additional buffer comprising an input coupled to one of the bi-directional pins, wherein the at least one additional buffer selectively couples the input to the control logic according to whether a power connection of the at least one additional buffer is connected to a voltage level sufficient for the at least one additional buffer to be operable.