Patent ID: 8028260

Claim:
A method for determining critical timing paths in an integrated circuit (IC), the method comprising: generating a most critical path to each node of a timing graph of nodes in the IC, wherein the generating does not include generating paths other than the most critical path; identifying the most critical path to a node of a destination register; invoking a next critical path function for the destination register to calculate a next critical path to the destination register, wherein the next critical path function recursively calls the next critical path function on one fan-in node of the node invoked in the next critical path function, the one fan-in node corresponding to a fan-in node which last contributed to the most critical path; selecting a next most critical path to the destination register from all paths to the destination register upon completion of invoking the next critical path function for the destination register; and repeating the invoking and the selecting until a predetermined number of most critical paths have been selected for the destination register, wherein at least one method operation is performed by a processor.