Patent ID: 7986575

Claim:
A semiconductor memory device comprising: a memory cell array having memory cells arranged at intersections of a plurality of first wirings and a plurality of second wirings, a rectifying element and a variable resistive element being connected in series in the memory cell, the variable resistive element having at least a first resistance value and a second resistance value that is higher than the first resistance value, each of the memory cells including the rectifying element and the variable resistive element connected in a fixed manner irrespective of whether the variable resistive element is the first resistance value or the second resistance value; and a control circuit selectively driving the first wirings and the second wirings, the control circuit being capable of performing a short-circuit failure countermeasure program operation in which the variable resistive element of the memory cell whose rectifying element is in a short-circuit failure state is programmed from the first resistance value to the second resistance value, and the short-circuit failure countermeasure program operation is configured such that a first voltage is applied to either the first wirings or the second wirings while applying a second voltage to the other, the second voltage being lower than the first voltage and having the same polarity of the first voltage, or being ground voltage.