Patent ID: 7863670

Claim:
A semiconductor device, comprising: a first MISFET including a first gate formed over a principal surface of a semiconductor substrate through a first gate insulating film; a second MISFET including a second gate which is thicker than the first gate, formed over the principal surface of the semiconductor substrate through a second gate insulating film which is thicker than the first gate insulating film; and a memory cell including a control gate formed over the principal surface of the semiconductor substrate through a third gate insulating film, a charge storage layer having one part thereof formed at one sidewall of the control gate and another part thereof formed over the principal surface of the semiconductor substrate, and a memory gate which is electrically separated from the control gate through the one part of the charge storage layer, as well as electrically separated from the semiconductor substrate through the other part of the charge storage layer, forming a split gate together with the control gate, wherein the third gate insulating film is thinner than the second gate insulating film, the control gate is thicker than the first gate and the ratio of height of the memory gate with respect to the gate length of the memory gate is larger than 1, wherein the control gate and the second gate are formed in a multilayer structure including a first electrode material film and a second electrode material film formed over the first electrode material film, and wherein the first gate is a single layer structure including a first electrode material film of the control gate.