Patent ID: 7804091

Claim:
A thin-film transistor array comprising: an electrically insulating substrate; a plurality of thin-film transistors arranged in a matrix on said electrically insulating substrate, and each including a channel, a source, and a drain each comprised of an oxide-semiconductor film; a pixel electrode integrally formed with said drain; a source signal line through which a source signal is transmitted to a group of thin-film transistors among said plurality of thin-film transistors; a gate signal line through which a gate signal is transmitted to a group of thin-film transistors among said plurality of thin-film transistors; a gate insulating layer formed above the gate signal line, the gate insulating layer having a gate terminal contact hole; a source terminal formed at an end of said source signal line; and a gate terminal formed in said gate terminal contact hole in contact with said gate signal line at an end of said gate signal line, said source terminal and said gate terminal being formed in the same layer of oxide-semiconductor film as a layer in which said channel, drain and source are formed, said source terminal and said gate terminal having the same electric conductivity as that of said pixel electrode.