Patent ID: 7237165

Claim:
A processor based built-in self test system contained in an integrated circuit chip having an embedded DRAM, said embedded DRAM including a multiplicity of DRAM blocks, said test system comprising: means for generating a test data pattern; means for writing said test data pattern into each DRAM block simultaneously; means for reading out sequentially from a first DRAM block to a last DRAM block of said multiplicity of DRAM blocks a resultant data pattern from each said DRAM block of said multiplicity of DRAM blocks after a predetermined period of time has elapsed from said writing of said test data into each said DRAM block of said multiplicity of DRAM blocks, said means for reading further including means for completing the reading of any previous DRAM block of said multiplicity of DRAM blocks before the reading of a subsequent DRAM block of said multiplicity of DRAM blocks; means for storing scan out data for each said DRAM block, said scan out data comprising said resultant data pattern or information based on said resultant data pattern of each said DRAM block; and means for scanning out said scan out data, said means for scanning including means for completing scanning out of any previous scan out data for a previous DRAM block of said multiplicity of DRAM blocks before scanning in of scan out data for a subsequent DRAM block of said multiplicity of DRAM blocks.