Patent ID: 7075151

Claim:
A semiconductor memory device, comprising: a substrate; a first semiconductor layer of a first conduction type having a single crystalline structure isolated from said substrate by an insulator layer; a plurality of memory transistors, each having a gate electrode connected to a word line, a pair of impurity regions of a second conduction type serving as a drain region and a source region formed in said first semiconductor layer, and a channel body of said first conduction type formed in said first semiconductor layer between said impurity regions, said memory transistors being operative to store data as a state of majority carriers accumulated in said channel body: a plurality of device isolation regions formed to isolate memory transistors having gate electrodes commonly connected to the same word line from each other among said plurality of memory transistors; and a plurality of impurity region isolation regions formed to isolate adjacent drain regions from each other and adjacent source regions from each other, said impurity region isolation region having a smaller width than that of said device isolation region.