Patent ID: 7136318

Claim:
A semiconductor memory device, comprising: a memory array including plural memory cells; a sense amplifier circuit which amplifies data read from one memory cell of said memory array to a bit line; a replica circuit which includes plural stages of replica cells having the same elements as said plural memory cells and connected with a common replica bit line, and which outputs to said common replica bit line a signal which is at a level which corresponds to the number of said plural stages of replica cells; a dummy cell which is connected as a load with said common replica bit line; and a sense amplifier control circuit which receives said signal on said replica bit line and controls the timing of a signal which starts up said sense amplifier circuit, wherein said dummy cell includes a series circuit which is formed by at least two OFF-state transistors, one end of said series circuit which is formed by said at least two OFF-state transistors is connected with a constant voltage source, and the other end of said series circuit is connected with said common replica bit line.