Patent ID: 8093919

Claim:
A test circuit that applies a data pattern applied to a chip provided in a BOST (Built Out Self Test) to a planarity of chips to be measured and compares output data from said chips to be measured to output data from said chip in said BOST to determine whether or not they coincide, said test circuit comprising: a BOST having said chip mounted; first transfer circuits that receive a data pattern applied to said chip to be measured from a previous stage and that transfer said data pattern to a next stage; and second transfer circuits that receive an expectation value pattern for said chip to be measured from a previous stage and that transfer said expectation value pattern to a next stage, wherein an output of said chip to be measured is compared to a corresponding expectation value pattern by a comparator provided corresponding to said chip to be measured; a pattern supplied to said chip in said BOST is used as said data pattern; and an output pattern from said chip in said BOST is used as said expectation value pattern, said first transfer circuits successively transferring a data pattern applied to said chip in said BOST in response to a clock signal, said data pattern applied to said chip in said BOST being applied to one chip to be measured out of said plurality of chips to be measured and a data pattern from a corresponding stage of said first transfer circuits being applied to each of other chips to be measured, said second transfer circuits successively transferring output data from said chip in said BOST as said expectation value pattern in response to a clock signal, said test circuit further comprising: one comparator comparing output data from said one chip to be measured to said output data from said chip in said BOST to determine whether or not they coincide is provided; other comparators, each corresponding to each of said other chips to be measured, that compares output data of each of said other chips to be measured to an expectation value pattern from a corresponding stage of said second transfer circuits to determine whether or not they coincide is provided; and a clock distributing circuit that receives a clock signal supplied to said chip in said BOST and that supplies said clock signal to said plurality of chips to be measured, said first transfer circuits, and said second transfer circuits; wherein timing relationship between a clock signal and a data pattern applied to a chip to be measured is unified between said plurality of chips to be measured.