Patent ID: 7203798

Claim:
A data memory cache unit which is used between an arithmetic unit and a main memory unit accessed by the arithmetic unit, comprising: a data holding section which includes a plurality of data areas for holding data, the data held in each of the plurality of data areas being read from and written in the main memory unit at one time, each of the plurality of data areas being divided into a plurality of small areas, and the data held in each of the plurality of small areas being read from and written in the arithmetic unit at one time; and a control section in which, if there is a consecutive-writing demand from the arithmetic unit for writing of data into consecutive addresses of the main memory unit and if a cache miss takes place in an object data area which is the data area that corresponds to an address outputted by the arithmetic unit, then the object data area is opened, and thereafter, if an object small area which is the small area that corresponds to the address outputted by the arithmetic unit in the object data area is adjacent to a data area boundary which is the boundary of the object data area located in the direction where the consecutive writing is earlier executed with respect to the order of addresses, then refill of data is not executed into the object data area from the main memory unit, and the data outputted by the arithmetic unit is written into the object small area, and if the object small area is not adjacent to the data area boundary, then refill of data is executed into the object data area from the main memory unit, and the data outputted by the arithmetic unit is written into the object small area.