Patent ID: 7227919

Claim:
A circuit for comparing an unknown first clock signal and a known second clock signal, the circuit comprising: an input section, clocked by the unknown first clock signal, that produces a slower first clock signal; a plurality of logic chains, wherein a first logic chain of said plurality of logic chains comprises: a first logic unit clocked by the unknown first clock signal and storing the slower first clock signal; two or more logic units, coupled to the first logic unit, that are clocked by the known second clock signal; an edge detector, coupled to the last of the two or more logic units and the second to last of the two or more logic units, that detects an edge transition; wherein each of the plurality of logic chains, other than said first logic chain, comprises: a first logic unit clocked by the unknown first clock signal and storing an output signal from the first logic unit of the preceding logic chain; two or more logic units, coupled to the first logic unit, that are clocked by the known second clock signal; and an edge detector, coupled to the last of the two or more logic units and the second to last of the two or more logic units, that detects an edge transition; an alias-detection circuit, coupled to the edge detectors, that determines a logic to be output in accordance with an alias value and the known second clock.