Patent ID: 7840861

Claim:
A method for scan-based testing of a plurality of circuits using a test clock control structure comprising: performing with a first programmable test clock controller of the test clock control structure an intra-domain test in a first subset of clock domains of the plurality of circuits, the intra-domain test including shifting a first dynamic fault detection test pattern in a first scan chain portion, the shifting in the first scan chain portion being done according to a first portion of control information shifted in a first control chain; performing with a second programmable test clock controller of the test clock control structure an inter-domain test in a second subset of clock domains of the plurality of circuits from a first clock domain to a second clock domain, the inter-domain test including shifting a second dynamic fault detection test pattern in a second scan chain portion in parallel with the shifting of the first dynamic fault detection test pattern in the first scan chain portion, the shifting in the second scan chain portion being done according to a second portion of control information shifted in a second control chain; and generating a first clock rate for the first clock domain and a second clock rate for the second clock domain, the first clock rate and the second clock rate being generated using a common functional clock to establish a timing reference point for the inter-domain test; wherein the first dynamic fault detection test pattern and the second dynamic fault detection test pattern include a last-shift-launch test pattern and a broadside test pattern, and wherein the first programmable test clock controller and the second programmable test clock controller shift, respectively, the first portion of control information and the second portion of control information.