Patent ID: 7795914

Claim:
A circuit comprising: a first tri-state gate circuit, a second tri-state gate circuit, and a third tri-state gate circuit; a first fence circuit and a second fence circuit; a first input signal, a second input signal, an activate signal, and an output signal; wherein the first, second, and third tri-state gate circuits each comprise: a first stage, said first stage comprising a data input and a control input, wherein said first stage comprises an AND gate, an inverter, and an OR gate, the AND gate having a first input and a second input and an output, and the OR gate having a first input and a second input and an output, the inverter configured to output a signal into the second input of the OR gate; a second stage, said second stage comprising a PMOS transistor and an NMOS transistor, wherein the output of the OR gate is configured to provide an input to the gate of the PMOS transistor, and wherein the output of the AND gate is configured to provide an input to the gate of the NMOS transistor, wherein the PMOS transistor is electrically connected to a positive voltage source, and wherein the NMOS transistor is electrically connected to ground, and wherein the PMOS transistor and NMOS transistor are configured in series thereby forming a junction between the PMOS transistor and the NMOS transistor, and a second stage output signal originates from the junction of the PMOS transistor and the NMOS transistor; and a third stage, said third stage comprising a dual input logic gate, the dual input logic gate having a first input and a second input, and a single third stage output signal; and wherein the first input signal is connected to the first tri-state gate circuit, the second input signal is connected to the second tri-state gate circuit; and wherein the output of the first tri-state gate circuit is connected to the first fence circuit, the second tri-state gate circuit, and the third tri-state gate circuit; and wherein the output of the second tri-state gate circuit is connected to the third tri-state gate circuit; and wherein the output of the third tri-state gate circuit is connected to the second fence circuit; and wherein the activate signal is connected to each tri-state gate circuit and each fence circuit.