Patent ID: 8397201

Claim:
A method of simulating an electrostatic discharge (ESD) circuit layout, comprising a computer processor for performing the following steps: providing a netlist that describes connectivity among components in an electronic circuit; pre-simulating the netlist for modeling of circuit operation; generating a circuit layout corresponding to the electronic circuit according to a result of the pre-simulation, the generated circuit layout including an ESD circuit layout and a plurality of back-end layers for connecting individual components of the electronic circuit; extracting parasitic according to the generated circuit layout; providing an ESD waveform for simulating the ESD circuit layout; and post-simulating the ESD circuit layout according to the ESD waveform and a result of the parasitic extraction; wherein the back-end layers are subjected to the post-simulation and the post-simulation step comprises: coupling one of a plurality of pads of the electronic circuit with the ESD waveform and grounding another of the pads, thereby forming an ESD path; reporting currents passing through the corresponding back-end layers, respectively; comparing the reported current with a corresponding given rated current; and highlighting the back-end layer that has the reported current equal or greater than the corresponding rated current.