Patent ID: 7129749

Claim:
A programmable logic device (PLD), comprising a plurality of configurable logic blocks (CLBs) inter-connectable through a programmable routing structure, wherein: the routing structure includes a plurality of lines programmably interconnected via one or more configurable circuit elements; each configurable circuit element is adapted to be controlled by one or more memory cells; at least one of the memory cells is coupled to (i) refresh circuitry adapted to refresh information stored in said memory cell and (ii) a corresponding configurable circuit element via a buffer adapted to isolate voltage fluctuations in the at least one memory cell from the configurable circuit element; two or more of the memory cells are organized in one or more rows and one or more columns, wherein each of said two or more of the memory cells is coupled to a word line and a bit line; and the refresh circuitry comprises: a selector circuit coupled to the two or more of the memory cells via one or more word lines, said selector circuit adapted to receive a first row-address signal; and a bank of amplifiers coupled to the two or more of the memory cells via one or more bit lines, wherein, for each bit line, the bank of amplifiers is adapted to (A) sense a voltage level on the bit line and (B) apply a write or refresh voltage to the bit line.