Patent ID: 7110293

Claim:
A non-volatile SRAM including a plurality of unit memory cells arranged in an array, wherein each of the plurality of unit memory cells comprises: an SRAM unit including first and second transistors which are cross-coupled to each other, a data true node to which a control electrode of the first transistor and a drain electrode of the second transistor are connected, and a data complement node to which a control electrode of the second transistor and a drain electrode of the first transistor are connected; and a non-volatile memory unit including: (a) first and second pass transistors connected to the data true node and the data complement nod; respectively, the first and second pass transistors being switched in response to supply of power to the SRAM unit and having threshold voltages higher than a threshold voltage of the first transistor, and (b) first and second non-volatile memory elements connected to the first and second pass transistors, respectively, to store data from the data true node and data from the data complement node, respectively, in response to supply of power to the SRAM unit, wherein a first well in which the non-volatilc memory unit is formed is electrically isolated from a second well in which the SRAM unit is formed.