Patent ID: 7285990

Claim:
A buffer circuit comprising: an input terminal operable to receive an input signal; an output terminal at which an output signal for the buffer circuit is provided; a first transistor having a gate, a source, and a drain, wherein the source of the first transistor is connected to the input terminal; a second transistor having a gate, a source, and a drain, wherein the gate of the first transistor is connected to the drain and the gate of the second transistor, wherein the source of the second transistor is connected to the output terminal; a third transistor having a gate, a source, and a drain, wherein the gate of the third transistor is connected to the drain of the first transistor, wherein the source of the third transistor is connected to the output terminal and to the source of the second transistor; a first current source connected to the drain of the first transistor; and a second current source connected to the drain of the second transistor.