Patent ID: 7971116

Claim:
A semiconductor device comprising: a BIST (Built in Self Test) that includes a plurality of scan flip-flops which are able to be serially connected and are respectively set to any value of 0 and 1 by a scan-shift operation; a data address signal generation circuit unit that generates a data signal based on a set value of a first scan flip-flop in said BIST, and that generates an address signal based on a set value of a second scan flip-flop in said BIST; a write/read signal generation circuit unit that generates a signal controlling writing to and reading from an electronically writable and readable memory, and supplies the generated signal to said memory; and a test signal control circuit unit that controls said data address signal generation circuit unit and said write/read signal generation circuit unit, based on a control signal received, and that selects, as a data signal and/or an address signal to be supplied to said memory, a data signal and/or an address signal from said data address signal generation circuit unit.