Patent ID: 7498887

Claim:
A high frequency digital oscillator synchronized to a low frequency oscillator signal s in having a frequency f in and gated by the rising edge of signal s in , the oscillator comprising: a) a ring oscillator having an odd number of digital gates and an adjustable feedback loop, the ring oscillator having a signal s osc with a frequency f osc , and the ring oscillator comprising: i) a starting ring oscillator frequency approximately equal to a multiple 2 n (where n=1, 2, 3, etc.) of the synchronizing frequency f in of signal s in ; ii) an ability to fine adjust its frequency f osc so that it becomes an equal multiple 2 n of the synchronizing signal frequency f in ; iii) an output whose rising edge of signal s osc when first triggered by signal s in is in phase with the rising edge of said trigger; iv) control signal means to trigger the ring oscillator with every rising edge of s in ; v) control signal means to sustain oscillations of the ring oscillator for a minimum of a single period signal of s in ; and vi) means for maintaining the ring oscillator output s osc at a low level before the first rising edge of s in occurs and retaining s osc to said low level until the next rising edge of signal s in , b) a multiplicity of signals s x2 , s X4 , s X8 , etc., derived by digitally dividing signal s osc and said signals having periods equal to 2, 4, 8, etc. times the period of the oscillator signal s osc ; c) means for selecting the one signal s xsel of said multiplicity of signals whose period is approximately equal to the period p in of signal s in ; d) means for measuring the integral number k of periods p osc that fit within one period p in ; e) means of determining the delta Δ=p in −k*p osc ; and f) means for using the resulting delta Δ to adjust the frequency of f osc so that period p in =the period of s xsel =p sxel , wherein the means for measuring the incoming clock P in period further comprises a counter that measures the largest integral number of unadjusted ring oscillator periods P osc that fit within the P in said counter being stepped by every rising edge of signal S ase′ , and wherein the means for counting periods P osc and generating a counter signal S cntr further comprises a counter circuit, and wherein the means for changing a loop delay d loop between the output of the ring oscillator and its input further comprises a delay adder which adds the delay Δ to d loop , thus generating the d crs coarse delay signal, and wherein the means for measuring the delay Δ comprises a counter, and further comprises a multiplicity of time delay circuits disposed in series and each having a precise time delay period t d which is activated during the duration of time Δ.