Patent ID: 8094500

Claim:
A nonvolatile memory, comprising: an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together; said array being partitioned into a first group of blocks and a second group of blocks; a group of read/write circuits for reading or programming in the memory array a corresponding page of memory cells in parallel; said first group of blocks having first-group pages that are each once programmable in between erasure, and the memory cells in the first-group page each storing one or more bit of data; said second group of blocks having second-group pages that are each multi-time programmable with a partial page being once programmable each time, and the memory cells in the second-group page each storing one bit of data; and a controller for controlling writing data in a fragment of one or more partial page selectively either to the first group of blocks in granularity of a page or to the second group of blocks in granularity of one or more partial page, the selection to write to either first or second group being a function of predefined attributes of the data and predefined states of said first group of blocks and said second group of blocks.