Patent ID: 7294886

Claim:
A power semiconductor device comprising: a semiconductor substrate made of Si of a first conductivity type; a first semiconductor layer made of Si of the first conductivity type and formed on an upper surface of the semiconductor substrate; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type which are made of Si and alternately and laterally arranged on the first semiconductor layer; a first main electrode electrically in contact with a lower surface of the semiconductor substrate; a fourth semiconductor layer made of Si of the second conductivity type selectively formed in surface regions of the second and third semiconductor layers; a fifth semiconductor layer made of Si of the first conductivity type selectively formed in a surface region of the fourth semiconductor layer; a second main electrode formed in contact with surfaces of the fourth and fifth semiconductor layers; and a control electrode formed on surfaces of the second, fourth and fifth semiconductor layers, wherein an impurity concentration of the first semiconductor layer is lower than an impurity concentration of the semiconductor substrate and an impurity concentration of the second semiconductor layer; the power semiconductor device is configured to be adopted to a given breakdown voltage VB (V); a thickness t of the first semiconductor layer and a thickness d of the second semiconductor layer have values satisfying a layer thickness ratio A defined by an expression: 0 <A =t/ ( t+d )<0.72; and a relationship among t, VB (V), and A: t <2.53×10 −6 ×( A×VB ) 7/6 (cm), is satisfied based on the given breakdown voltage VB (V).