Patent ID: 7629642

Claim:
A semiconductor device comprising: a semiconductor region having a source region, a drain region, and a channel region provided between the source region and the drain region; a first tunnel insulation film formed on the channel region; a barrier layer formed on the first tunnel insulation film and having an energy barrier; a second tunnel insulation film formed on the barrier layer; a charge storage portion formed on the second tunnel insulation film and comprising an insulation film expressed by Si Y (SiO 2 ) X (Si 3 N 4 ) 1-X M Z (where, M denotes an element other than Si, O, and N, and 0≦X≦1, Y>0, and Z≦0); and a control electrode formed on the charge storage portion and controlling a height of the energy barrier, wherein the X, Y and Z satisfy the following relationship: [2×2 X /(4−2 X )+(4−4 X )/(4−2 X )]×[ Y /( Y +7−4 X+Z )]≧0.016.