Patent ID: 8723325

Claim:
A method of forming an integrated circuit structure, comprising: forming a first metal layer over a first insulating layer of a substrate; forming a continuous second patterned insulating layer over the substrate, the second patterned insulating layer having a damascene opening therein exposing a portion of the first metal layer, the damascene opening having a second insulating layer portion formed therein, the second insulating layer portion having a width between a first side portion and a second side portion, the first side portion and second side portion being parallel, the second insulating layer portion also having a top side portion extending from the first side portion to the second side portion, the top side portion having a continuous length equal to the width of the second insulating layer portion, the damascene opening having a trench opening and a via opening of a dual damascene structure and the second insulating layer portion extending through the via opening into the trench opening causing the top side portion to be above the trench opening; filling the damascene opening with a second metal layer to embed the second insulating layer portion in the second metal layer; and forming a passivation layer above the second patterned insulating layer and the second metal layer, wherein the passivation layer partially covers the second metal layer.