Patent ID: 7319349

Claim:
A semiconductor integrated circuit comprising: external clock terminals receiving a plurality of external clocks having phases shifted in sequence, respectively; a phase adjustment unit adjusting the phases of said external clocks to generate a plurality of internal clocks with a same phase difference between every adjacent transition edges thereof; a clock composite unit synthesizing the internal clocks to generate a composite clock having a frequency higher than that of the external clocks; and an internal circuit operating in synchronization with the composite clock, wherein: said phase adjustment unit includes: a plurality of sub phase adjustment units corresponding to the external clocks, respectively, each having first and second variable delay circuits, a phase comparator, and first and second delay control circuits; and an average calculation unit calculating an average delay time which is an average of delay times of said second variable delay circuits in all of said sub phase adjustment units, and wherein in each of said sub phase adjustment units: said first variable delay circuit delays a corresponding external clock in phase to generate the internal clock; said second variable delay circuit delays the internal clock in phase to generate a comparison clock; said phase comparator compares phases of the comparison clock and one of the internal clocks generated from one of the external clocks having a transition edge adjacent to that of another one of the external clocks and delaying in phase from the another one of the external clocks which corresponds to the comparison clock; said second delay control circuit adiusts the delay time of said second variable delay circuit in accordance with a result of the comparison by said phase comparator in order to make the comparison clock and the internal clock compared by said phase comparator coincide in phase with each other; and said first delay control circuit increases the delay time of said first variable delay circuit when the delay time of said second variable delay circuit is longer than the average delay time, and decreases the delay time of said first variable delay circuit when the delay time of said second variable delay circuit is shorter than the average delay time.