Patent ID: 7439089

Claim:
A method of forming an array substrate for a liquid crystal display device, comprising: forming a gate line on the substrate along a first direction, a gate pad at one end of the gate line, and a gate electrode extending from the gate line; forming a first gate insulating layer on the substrate to cover the gate line, the gate pad, and the gate electrode; forming an active layer of unintentionally doped amorphous silicon and an ohmic contact layer of intentionally doped amorphous silicon layer sequentially on the first gate insulating layer over the gate electrode; forming a data line, a data pad, a source electrode, and a drain electrode, the data line disposed extending along a second direction to perpendicularly cross the gate line to define a pixel region, the data pad disposed at one end of the data line, the source electrode extending from the data line on a first portion of the ohmic contact layer, and the drain electrode spaced apart from the source electrode on a second portion of the ohmic contact layer to form a thin film transistor; forming a second insulating layer over an entire surface of the substrate to cover the thin film transistor; forming a black matrix on the second insulating layer to cover the thin film transistor, the gate line, and the data line except a portion of the drain electrode; forming a third insulating layer over the entire surface of the substrate to cover the black matrix; patterning the first, second, and third insulating layers to form first, second and third contact holes, the first contact hole exposing the portion of the drain electrode, the second contact hole exposing a portion of the gate pad, and the third contact hole exposing a portion of the data pad; forming a first transparent conductive layer over the entire surface of the substrate to cover the patterned third insulating layer and contact the exposed portions of the drain electrode, gate pad and data pad; forming a buffer layer on the first transparent conductive layer; forming a color filter on the buffer layer within the pixel region; etching portions of the buffer layer exposed by the color filter to reveal portions of the first transparent conductive layer; forming a second transparent conductive layer over the entire surface of the substrate to cover the color filter and the revealed portions of the first transparent conductive layer; and patterning the first and second transparent conductive layers to form first and second pixel electrodes, a gate pad terminal, and a data pad terminal.