Patent ID: 7650413

Claim:
A switch for managing shared memory resources in a high-speed switching environment, the switch comprising: a plurality of input ports and a plurality of output ports; a switch core comprising a data memory, the switch core accessible by the plurality of input ports and the plurality of output ports of the switch, the data memory logically divided into a plurality of blocks that correspond to a plurality of credits; a central agent operable to: maintain a pool of available credits that comprises one or more of the credits; and allocate a credit to an input port from the pool of credits, the allocated credit indicating that the corresponding one of the blocks is available to the input port; wherein the plurality of input ports are each operable to: track allocated credits received from the central agent; receive a packet; determine whether enough of the allocated credits are available to write the packet to the data memory; and if enough of the allocated credits are available, write the packet to one or more blocks corresponding to one or more of the allocated credits that are available; and wherein the plurality of output ports are each operable to: read from a block; and return the credit corresponding to the read block to the pool of credits.