Patent ID: 7539467

Claim:
An integrated circuit, comprising: first and second power supply nodes; an enable input terminal that is physically accessible externally of the integrated circuit; a plurality of further input terminals that are physically accessible externally of the integrated circuit; a plurality of input circuits respectively coupled to said plurality of further input terminals, each of said input circuits coupled to said enable input terminal and said first and second power supply nodes, each of said input circuits including a current path from said first power supply node to said second power supply node; functional circuitry that can perform a desired operation, said functional circuitry coupled to said input circuits and to said enable input terminal; said enable input terminal receiving an enable signal which is activated when said functional circuitry is to be enabled to perform said desired operation and which is deactivated when said functional circuitry is to be disabled from performing said desired operation; and each of said input circuits breaking said current path thereof in response to deactivation of said enable signal, wherein each said input circuit includes first and second transistors, and third and fourth series-connected transistors, said third and fourth series-connected transistors connected in series between said first and second transistors.