Patent ID: 8502289

Claim:
A double gate transistor, comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including first and second parallel side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on the first side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the second side surface of said middle portion, characterized in that: said middle portion has a width larger than the width of the two end portions for forming source and drain regions, said middle portion has a length larger than the length of at least one of the first gate and the second gate, and a height of said first gate and a height of said second gate are both the same as a height of said middle portion, wherein the length runs along channel direction, the height runs along a direction perpendicular to the substrate surface, and the width runs along a direction perpendicular to the length and the height.