Patent ID: 8569134

Claim:
A method to fabricate a closed cell trench MOSFET structure, comprising the steps of: providing a drain region of a first conductivity type; forming a first doped region of a second conductivity type on the drain region; forming a trench within the first doped region, the trench having at least two stripe regions and a cross region, and a bottom of the trench being located in the drain region; forming a gate dielectric layer lining inner surfaces of the trench; forming a first polysilicon layer in the trench, the first polysilicon layer substantially filling the stripe regions but leaving a concave at a middle of the cross region; etching the first polysilicon layer to from a window to expose a bottom of the cross region; forming a second doped region of the second conductivity type adjacent to the bottom of the cross region through the etched first polysilicon layer; and forming a second polysilicon layer to fill the window.