Patent ID: 7821039

Claim:
An integrated circuit structure comprising: a p-type metal-oxide-semiconductor (PMOS) transistor comprising: a first gate electrode; a first source region adjacent the first gate electrode; and a first drain region adjacent to, and on an opposite side of, the first gate electrode than the first source region; an n-type metal-oxide-semiconductor (NMOS) transistor comprising: a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region adjacent the first gate electrode; and a second drain region adjacent to, and on an opposite side of, the second gate electrode than the second source region, wherein no additional transistors are formed between the PMOS and the NMOS transistors; a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip, wherein the interconnection port is on an outer side of a MOS pair region comprising the PMOS transistor, the NMOS transistor, and the region between the PMOS and the NMOS transistors, and wherein the portion of the gate electrode strip in the MOS pair region is substantially straight.