Patent ID: 8261025

Claim:
A method of sharing memory in a software pipeline, the method implemented on a network on chip (‘NOC’), the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block operatively coupled to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising: segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage executing in a thread of execution on an IP block; and allocating, by at least one of the stages, memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated, wherein data elements for determining when the shared memory can be deallocated further comprise a table comprising at least one row for each path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is in use by a stage in a path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is no longer required for use by a stage in the path of execution in the pipeline; determining, by at least one stage in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.