Patent ID: 8791443

Claim:
A variable resistive memory device, comprising: a semiconductor substrate in which line regions and space regions substantially having the same line widths are alternatively defined in a first direction and a second direction perpendicular to the first direction and junction regions are formed portions thereof corresponding to line regions of the first direction; first word lines formed on the semiconductor substrate and arranged in space regions of the first direction with the substantially same line widths; second word lines formed on the semiconductor substrate and arranged in the line regions of the first direction with the substantially same line widths; an interline insulating layer formed to surround sides and bottoms of the first word lines; a plurality of bit lines formed on the first and second word lines and arranged in line regions of the second direction to cross the first and second word lines; and a plurality of memory cells formed at intersections of the pluralities of first and second word lines and the plurality of bit lines.