Patent ID: 8402418

Claim:
A method for designing clock resource distribution in an application specific integrated circuit (ASIC) comprising: defining, in an ASIC design floor plan comprising a plurality of partitions, a grid of clock routing points comprising a plurality of clock routing points; overlaying the grid of clock routing points over a design according to the ASIC design floor plan; determining if a clock routing point of the grid of clock routing points is obstructed by a plurality of blockages comprised in the ASIC design floor plan; adjusting positioning of the grid of clock routing points to accommodate the plurality of blockages comprised in the design; pushing a plurality of clock routing macros into the plurality of partitions according to the grid of clock routing points; and automatically generating a clock signal distribution path comprising a plurality of adjacent clock routing macros of the plurality of clock routing macros between a clock source and a logic unit disposed in the plurality of partitions, wherein the defining, the overlaying, the determining, the adjusting, the pushing, and the generating are performed in an application executed by a processor of a computer system.