Patent ID: 7699996

Claim:
A structure fabrication method, comprising: providing a structure which includes: a wafer a gate electrode layer on the wafer; a memory layer on the gate electrode layer, and a sidewall image transfer (SIT) layer on the memory layer; patterning the SIT layer, resulting in a SIT region, wherein said patterning comprises a lithographic process; directionally etching the memory layer with the SIT region as a mask, resulting in a first memory region; and retreating a first side wall of the SIT region a retreating distance D in a reference direction as measured from a planar side wall of the first memory region, resulting in a SIT portion comprising the first side wall, wherein the first side wall is parallel to a planar side wall, wherein the retreating distance D is less than a critical dimension CD associated with the lithographic process, wherein the first memory region includes a first dimension W 2 and a second dimension W 3 in the reference direction as measured from the planar side wall, wherein after said retreating has been performed, the reference direction is directed from the planar side wall to a plane comprising the first side wall and is perpendicular to the planar side wall, and wherein CD<W 2 <2D<W 3 .