Patent ID: 7130210

Claim:
A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising: providing one or more unprogrammed multi-level flash memory bits to be programmed; performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage; and generating a dynamic fast-bit drain voltage for each of the program levels on the wordline; wherein generating the dynamic fast-bit drain voltage comprises: selecting groups of sample bits from the wordline associated with each program level; selecting a starting drain voltage for each program level from the lowest allowable drain voltage for each program level; applying program pulses to a first group of sample bits associated with a first program level; increasing one of the drain voltage, a gate voltage, and a combination of the drain and gate voltages of the first group of sample bits; determining a first drain voltage at which a fast-bit of the group of sample bits is programmed or a maximum drain voltage level is attained; and reselecting another group of sample bits associated with a program level, applying program pulses, increasing one of the drain and gate voltages until a fast-bit drain voltage is determined for each group of sample bits associated with a respective program level.