Patent ID: 7553728

Claim:
A method for manufacturing a non-volatile semiconductor memory comprising: forming a second semiconductor layer on a first semiconductor layer having a first conductivity type; forming a third semiconductor layer having a second conductivity type on the second semiconductor layer; forming a gate insulating film on the third semiconductor layer; depositing a first conductive layer on the gate insulating film; depositing an insulating film on the first conductive layer; depositing a second conductive layer on the insulating film; forming a groove penetrating the second conductive layer, the insulating layer and the first conductive layer so as to define a control gate electrode, an inter-electrode insulating film under the control gate electrode and a floating gate electrode under the inter-electrode insulating film; and forming a memory cell transistor comprising a source region having the second conductivity type, a drain region having the second conductivity type and a channel region having the second conductivity type in the third semiconductor layer by ion implantation to the third semiconductor layer through the groove.