Patent ID: 6880120

Claim:
A hardware verification method comprising: obtaining a set of packets to be driven by a device under test; obtaining a set of timing and relation criteria which determines a sequence in which the packets should be driven by the device under test, wherein obtaining the set of timing and relation criteria is dependent on at least one of when a packet should be transmitted, how long it should take to transmit the packet, and a relation of the packet to other packets; starting multiple drive loops, each drive loop picking up a packet and forcing the device under test to drive the packet in accordance with the determined sequence; starting multiple expect loops, each expect loop being configured to expect a packet driven by the device under test within a specified time period and picking up the expected packet if the expected packet arrives within the specified time period; for each drive loop, confirming that the timing and relation criteria are satisfied prior to allowing the drive loop to force the device under test; and for each expect loop, checking if the expected packet arrives within a specified time period and raising an error flag if the expected packet does not arrive within the specified time period.