Patent ID: 7830190

Claim:
A data latch circuit comprising: a first data latch unit, for latching a first input data according to a first clock signal and outputting a first output data; a second data latch unit, coupled to the first data latch unit, for latching the first output data according to a second clock signal and outputting a second output data; a third data latch unit, coupled to the second data latch unit, for latching the second output data according to a third clock signal and outputting an output data; and a phase selector, coupled to the second data latch unit, for generating the second clock signal to the second data latch unit according to a phase relation between the first clock signal and the third clock signal, the phase selector comprising: a phase detector, receiving the first clock signal and the third clock signal, for detecting the phase relation between the first clock signal and the third clock signal to generate a detection signal; a phase adjustment unit, receiving the third clock signal, for generating a fourth clock signal according to the third clock signal, wherein there is a phase difference between the fourth clock signal and the third clock signal; a decision unit, coupled to the phase detector, for generating a decision signal according to the detection signal; and a select unit, coupled to the phase adjustment unit, for selectively outputting the third clock signal or the fourth clock signal as the second clock signal according to the decision signal.