Patent ID: 7443171

Claim:
A method for detecting current leakage between deep trench capacitors in DRAM devices, comprising: providing a wafer with at least one scribe line and at least one memory region; forming a plurality of memory cells in the memory region and at least one test device in the scribe line region simultaneously, wherein each memory cell has a deep trench capacitor and a corresponding transistor, the test device comprises a plurality of bit line regions each including: a first trench capacitor pair having a first deep trench capacitor and a second deep trench capacitor; a first transistor having a first terminal electrically coupled to the first deep trench capacitor and a control terminal electrically coupled to a first word line; a second transistor having a first terminal electrically coupled to the second deep trench capacitor and a control terminal electrically coupled to a second word line; a first bit line electrically coupled to the first transistor; and a second bit line electrically coupled to the second transistor, wherein the first bit lines in the bit line regions are connected, the second bit lines in the bit line regions are connected, the first and second bit lines are separated and the first and second word lines are perpendicular to the bit line regions; turning the first and second transistors on; and determining whether there is current leakage between the first and second deep trench capacitors of the test device according to whether the first and second bit lines are electrically coupled to each other, wherein the current leakage between first and second bit lines of the test device indicates that current leakage is present between the deep trench capacitors in the memory region.