Patent ID: 6917387

Claim:
An arrangement for time-correct combination of a first, continuous digital data stream (V 1 ), comprising a sync signal (S), with a second, discontinuous digital data stream (V 2 ), the arrangement comprising: a first delay member ( 2 ) delaying the first data stream (V 1 ) by a first predetermined period of time, a second delay member ( 3 ) delaying the sync signal (S) of the first data stream (V 1 ) by a second predetermined period of time, a memory ( 4 ) in which the second data stream (V 2 ) is written in accordance with a write pointer (WP) and from which it is read in accordance with a read pointer (RP), the write pointer (WP) being reset by each pulse of the undelayed sync signal (S; WPR) of the first data stream (V 1 ), and the read pointer (RP) being reset by each pulse (RPR) of the sync signal of the first data stream (V 1 ) delayed by means of the second delay member ( 3 ), i.e. set at the start of the memory ( 4 ), and means ( 6 ) for combining or processing the output data streams of the first delay member ( 2 ) and the memory ( 4 ), wherein the first period of time is chosen to be such that the output data streams of the first delay member ( 2 ) and the memory ( 4 ) occur at the means ( 6 ) for combining or processing in a desired temporal relation to each other, and wherein the second period of time is chosen to be such that the read pointer (RP) does not catch up with the write pointer (WP) during the process of reading from the memory ( 4 ), also when taking the discontinuities occurring in the second data stream (V 2 ) into account.