Patent ID: 8164969

Claim:
An integrated circuit hybrid logic block comprising: A controlled power supply line (CVDD); Another controlled power supply line (CVss); A substrate power supply line (BP); Another substrate power supply line (BN); A plurality of hybrid circuit gates, wherein each hybrid circuit gate comprises at least one p-channel Metal-Oxide-Semiconductor (MOS) transistor with source terminal connected to CVDD and substrate terminal connected to BP, and at least one n-channel MOS transistor with source terminal connected to CVss and substrate terminal connected to BN; A power line control circuit for switching the voltages on the power supply line(s) between active mode and hybrid power saving mode; Wherein the steady-state voltage on CVDD at hybrid power saving mode is lower than the voltage on BP by at least a quarter of the voltage on CVDD at active mode minus the voltage on CVss at active mode, and the steady-state voltage on CVss at hybrid power saving mode is higher than the voltage on BN by at least a quarter of the voltage on CVDD at active mode minus the voltage on CVss at active mode.