Patent ID: 8310063

Claim:
A semiconductor package structure, comprising: a substrate, having a carrying surface and a bottom surface opposite to the carrying surface; a first chip, disposed above the carrying surface of the substrate, wherein the first chip has a first surface and a second surface opposite to the first surface, the second surface faces the substrate, the first chip has a plurality of through silicon vias (TSVs) and a plurality of first pads and a plurality of second pads on the first surface, and the first pads are electrically connected to the corresponding TSVs; a plurality of first conductive bumps, disposed between the first chip and the substrate, wherein the TSVs of the first chip are respectively electrically connected to the substrate through the first conductive bumps; a second chip, disposed above the first chip, and exposing a portion of the first surface; a plurality of second conductive bumps, respectively disposed on the first pads, wherein the second chip is electrically connected to the corresponding TSVs through the second conductive bumps; an interposer, disposed above the first chip and within the portion of the first surface, wherein a top surface of the interposer is substantially aligned with a top surface of the second chip; and a plurality of third conductive bumps, respectively disposed on the second pads, wherein the interposer is bonded to the second pads through the third conductive bumps.