Patent ID: 6969662

Claim:
A method of controlling a memory device including at least one transistor to constitute a memory cell, wherein the transistor is adapted to maintain a first data state and a second data state, and wherein the transistor includes: a source region formed adjacent to the body region, a drain region formed adjacent to the body region, a body region disposed between the source region and the drain region wherein the body region is electrically floating, and a gate disposed over the body region, the method comprising: applying a first voltage to the gate of the transistor; applying a second voltage to the drain region of the transistor; removing the second voltage from the drain region; removing the first voltage from the gate wherein the first voltage is removed from the gate after removing the second voltage from the drain region; and storing a first charge in the body region in response to removing the second voltage from the drain region or the first voltage from the gate, wherein the first charge is representative of the first data state.