Patent ID: 8331524

Claim:
A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: an input unit, electrically connected to a previous shift register stage of the shift register stages, for receiving a previous gate signal of the gate signals and for outputting a driving control voltage in response to the previous gate signal; a pull-up unit, electrically connected to the input unit and an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals in response to the driving control voltage and a first clock signal, wherein the Nth gate line is employed to deliver the Nth gate signal; a pull-down circuit, electrically connected to the input unit and the pull-up unit, for pulling down the driving control voltage and the Nth gate signal; and a waveform-shaping unit, electrically connected to the input unit and the Nth gate line, for performing a waveform-shaping operation on the Nth gate signal in response to a high auxiliary signal and the driving control voltage, wherein while the first clock signal remains high, the high auxiliary signal changes from being high in a first state to being low in a second state.