Patent ID: 7185299

Claim:
A processor-implemented method of placing a design in a programmable logic device (PLD), the method comprising: placing design elements at respective locations on the PLD in a memory-based representation of the PLD; determining a set of a plurality of possible routes between at least one first point and at least one second point of placed elements; finding one most likely route of the plurality of possible routes; wherein the one most likely route is found based on a timing constraint associated with a connection between the first and second points, a numbers of nets in an area covering the possible routes, and fanout of a net including the connection between the first point and the second point; determining a delay associated with the most likely route; reporting the delay associated with the most likely route as the estimated routing delay of the connection between the first and second points; wherein the determining of the plurality of possible routes, finding the one most likely route, determining the delay, and reporting the delay are performed during placement optimization, and the most likely route is not assigned as a route of the design during placement optimization; and in response to the estimated routing delay failing to satisfy a requirement, changing placement locations of one or more elements of the design, and repeating the steps of determining the plurality of possible routes, finding the one most likely route, determining the delay, and reporting the delay during placement optimization.