Patent ID: 8059442

Claim:
An apparatus comprising: a read only memory having an array of bit-lines, an array of word-lines and a plurality of bit-cells, wherein: a bit-cell in the plurality of bit-cells is coupled to a word-line and a plurality of bit-lines in the array of bit-lines, the bit-cell being configured to store a plurality of bits that is associated with the plurality of bit-lines that are coupled to the bit-cell; and a first plurality of bit-lines in the array of bit-lines is configured to share a bit-cell coupled to the first plurality of bit-lines with a second plurality of bit-lines coupled to a bit-cell adjacent to the bit-cell that is coupled to the first plurality of bit-lines, the sharing forming a shared arrangement of bit-lines such that each shared arrangement is structured to store a plurality of bits per bit-cell, the plurality of bits stored per bit-cell being based on a number of the bit-lines forming each shared arrangement.