Patent ID: 7916534

Claim:
A semiconductor memory device comprising: a memory cell array which includes a first region that has a plurality of predetermined first block regions in the memory cell array and has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of predetermined second block regions in the memory cell array and has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number); a data storage circuit which includes a plurality of data caches; and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n (k divided by n) number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region, wherein the data storage circuit further includes: an amplifier circuit which amplifies the data from the data caches; and a latch circuit which temporarily stores data to be transferred from a data input/output terminal to the data caches, or from the data caches to the data input/output terminal.