Patent ID: 7142026

Claim:
A delay locked loop (DLL) capable of correcting a duty ratio of a clock signal comprising: a clock buffer for receiving an external clock signal and an inverted external clock signal to generate a rising edge clock signal by buffering the external clock signal and the inverted external clock signal; a delay means for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal and a second internal clock signal and generating a first delay locking signal and a second delay locking signal based on the first comparison signal; a duty correction means for receiving the first and the second internal clock signals and the first and the second delay locking signals to generate a mixed clock signal which is duty corrected by mixing phases of the first and the second internal clock signals applying a first weight and a second weight to the first and the second internal clock signals respectively; a delay model unit for delaying the mixed clock signal for a predetermined delay time to generate a feed-backed clock signal; and a first phase detector for receiving the external clock signal and the feed-backed clock signal to generate the first comparison signal by comparing phases of the external clock signal and the feed-backed clock signal.