Patent ID: 7397273

Claim:
A logic isolation circuit, comprising: a first buffer circuit configured for being switched between a first voltage transferable state and a first voltage non-transferable state; a first latch circuit configured for being switched between a first reset state and a first non-reset state, the first reset state for setting the first latch circuit to a first reset condition; a first input/output node coupled to receive a first logic level voltage; a second buffer circuit configured for being switched between a second voltage transferable state and a second voltage non-transferable state; a second latch circuit configured for being switched between a second reset state and a second non-reset state, the second reset state for setting the second latch circuit to a second reset condition; a second input/output node coupled to receive a second logic level voltage; the first logic level voltage and the second logic level voltage both being for a same logic state; the first buffer circuit coupled to the first input/output node and the second input/output node; the second buffer circuit coupled to the first input/output node and the second input/output node; the first latch circuit coupled to the first buffer circuit, the second latch circuit, the first input/output node, and the second input output node; the second latch circuit coupled to the second buffer circuit, the first latch circuit, the first input/output node, and the second input output node; the first buffer circuit configured to provide a first override voltage to the first input/output node when in the first voltage transferable state, the first override voltage for overriding the first logic level voltage; and the first buffer circuit configured to not provide the first override voltage to the first input/output node when in the first voltage non-transferable state.