Patent ID: 8363468

Claim:
A memory system comprising: a memory device including: a memory cell array which includes a first region that has a plurality of memory cells each capable of storing 2 n -bit data (n is 0 or a natural number) whose one end of a current path is connected to a bit line, and a second region that has a plurality of memory cells each capable of storing 2 k -bit data (k>n: k is 0 or a natural number) whose one end of a current path is connected to the bit line; a data storage circuit which includes a plurality of data caches and is connected to the bit line; and a first control circuit which controls the memory cell array and the data storage circuit in such a manner that the 2 k -bit data read from the 2 k /2 n (2 k divided by 2 n ) number of memory cells in the first region are stored into the data storage circuit and the 2 k -bit data are stored into the memory cells in the second region, and a controller including: a second control circuit which controls the first control circuit, wherein the data storage circuit further includes: an amplifier circuit which amplifies the data from the data caches; and a latch circuit which temporarily stores data to be transferred from a data input/output terminal to the data caches, or from the data caches to the data input/output terminal.