Patent ID: 8072799

Claim:
A semiconductor integrated circuit device provided with an SRAM memory comprising: an SRAM memory cell array including a plurality of SRAM memory cells arranged in a plurality of rows and a plurality of columns; the SRAM memory cell including a first CMOS inverter, a second CMOS inverter, a first N-channel MOS transistor coupled to an output node of the first CMOS inverter, a second N-channel MOS transistor coupled to an output node of the second CMOS inverter, the first CMOS inverter including a first P-channel MOS transistor and the second CMOS inverter including a second P-channel MOS transistor; a plurality of word lines coupled to the first and second N-channel MOS transistors corresponding to the SRAM memory cells of the rows; a plurality of first bit lines coupled to the first N-channel MOS transistors corresponding to the SRAM memory cells of the columns, the first bit lines extended to a first side and a second side opposing the first side of the SRAM memory cell array; a plurality of second bit lines coupled to the second N-channel MOS transistors corresponding to the SRAM memory cells of the columns, the second bit lines extended to the first side and the second side; a power supply line that supplies a power voltage; a plurality of power transistors coupled to the power supply line and the power transistors arranged corresponding to the SRAM memory cells of the columns; a plurality of memory cell power supply lines coupled to corresponding ones of the power transistors and the memory cell power supply lines arranged along the first and second bit lines, and the memory cell power supply lines coupled to sources of the first and second P-channel MOS transistors in the SRAM memory cells corresponding to the columns; a write driver that writes data to the SRAM memory cell; a plurality of column selection switches coupled to corresponding ones of the first bit lines and the second bit lines, the column selection switches being arranged proximate the first side; a signal line to control the power transistor; and an output logic circuit to output a signal to the signal line, wherein a first distance between the output logic circuit and the the column selection switch corresponding to a column of the memory cell array is shorter than a second distance between the output logic circuit and the memory cell in the column allocated at the second side of the memory cell array, and wherein an on-resistance of the power transistor coupled to a write operation memory cell is higher than an on-resistance of the power transistor coupled to a read operation memory cell.