Patent ID: 8376237

Claim:
A method comprising: biasing an EEPROM array that includes a plurality of memory cells arranged in rows and columns, each of said memory cells having a first current-conduction terminal coupled to a bitline of said EEPROM array through a first switch and a control terminal coupled to a gate-control line of said memory array through a second switch, wherein a control terminal of the first switch is coupled to a first wordline and a control terminal of the second switch is coupled to a second wordline, the biasing including: selecting at least one memory cell for a memory operation, the memory operation being a programming operation or an erasing operation, the selecting including: biasing the first wordline and the second wordline with voltages generated starting from an internal supply voltage, the biasing including biasing said first wordline and said second wordline with voltages different from one another and having values that are higher than said internal supply voltage and are a function of the memory operation for each of said operations of programming and erasing, said values being chosen in such a way as to limit electrical stresses in said EEPROM array.