Patent ID: 7394294

Claim:
A complementary pass-transistor logic comprising: input nodes to which one or more pairs of first complementary input signals are provided; a pair of intermediate nodes for outputting first and second complementary intermediate signals; a logic network which is connected between the input nodes and the intermediate nodes and comprised of N-channel MOS transistors whose conduction states are controlled by one or more pairs of second complementary input signals, the logic network outputting a logical operation result of the first complementary input signals and the second complementary input signals to the intermediate nodes as the intermediate signals; and first and second inverters for inverting the intermediate signals to produce complementary output signals, wherein the N-channel MOS transistors of the logic network are configured as depletion type N-channel MOS transistors, wherein the first inverter is comprised of a first enhancement-type N-channel MOS transistor which is connected between a ground potential and a first output node and whose conduction state is controlled by the first intermediate signal and a first depletion-type N-channel MOS transistor which is connected between the first output node and a supply potential and whose conduction state is controlled by the second intermediate signal, and wherein the second inverter is comprised of a second enhancement-type N-channel MOS transistor which is connected between the ground potential and a second output node and whose conduction state is controlled by the second intermediate signal, and a second depletion-type N-channel MOS transistor which is connected between the second output node and the supply potential and whose conduction state is controlled by the first intermediate signal.