Patent ID: 7612413

Claim:
A semiconductor device comprising: a substrate; an n-type semiconductor region formed on the substrate; a p-type semiconductor region formed on the substrate so as to be insulated and separated from the n type semiconductor region; a p-channel metal insulator semiconductor (MIS) transistor formed on the n-type semiconductor region, the p-channel MIS transistor comprising: a first gate dielectric film formed on the n-type semiconductor region; a first lower gate electrode made of an alloy of Ta and C and formed on the first gate dielectric film; and a first upper gate electrode including silicon and formed on the first lower gate electrode; and an n-channel MIS transistor formed on the p type semiconductor region, the n-channel MIS transistor comprising: a second gate dielectric film formed on the p type semiconductor region; a second lower gate electrode made of an alloy of Ta and C and formed on the second gate dielectric film; and a second upper gate electrode including silicon and formed on the second lower gate electrode, and a mole ratio of C to Ta (C/Ta) in the first lower gate electrode and the second lower gate electrode being from 2 to 4, and the alloy of Ta and C in each of the first lower gate electrode and the second lower gate electrodes being amorphous.