Patent ID: 7450049

Claim:
A digitization apparatus comprising: a pulse delay circuit constituted by a plurality of pulse delay units connected in series or in ring form, each of said pulse delay units having a delay time depending on a voltage level of an analog input signal applied thereto as a drive voltage thereof, said pulse delay circuit allowing a pulse signal to travel through said pulse delay units while being successively delayed by said delay time; a higher coding circuit generating, upon receiving a measurement signal indicating a measurement timing from outside, digitized data representing the number of said pulse delay units which said pulse signal has passed; a reverse timing extraction circuit extracting a timing, as a reverse timing signal, at which any one of said pulse delay units has reversed in output level for the first time after said measurement timing; a first delay line constituted by a plurality of first delay units connected in series or in ring form, each of said first delay units having a first delay time, said first delay line allowing said reverse timing signal to travel through said first delay units while being successively delayed by said first delay time; a second delay line constituted by a plurality of second delay units connected in series or in ring form, each of said second delay units having a second delay time larger than said first delay time by 1/M (M being an integer not smaller than 2) of said delay time of said pulse delay units, said first delay line allowing said reverse timing signal to travel through said second delay units while being successively delayed by said second delay time; and a lower coding circuit generating digitized data representing a time difference between said measurement timing and said reverse timing on the basis of the number of said first delay units which said reverse timing signal has passed when said number of said first delay units has overtaken the number of said second delay units which said measurement signal has passed; said digitization apparatus outputting data formed by said digitized data generated by said higher coding circuit as higher bits thereof, and said digitized data generated by said lower coding circuit as lower bits thereof.