Patent ID: 6939762

Claim:
A method for manufacturing a semiconductor device, the semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate, the method comprising the steps of: (a) simultaneously forming a well and an impurity region that is used to electrically connect a lower electrode of the capacitor element and another semiconductor element, wherein the well is located in the semiconductor substrate in the DRAM region, and the impurity region is located in the semiconductor substrate in the analog element region; (b) simultaneously forming a storage node of the cell capacitor and the lower electrode of the capacitor element; (c) simultaneously forming a dielectric layer of the cell capacitor and a dielectric layer of the capacitor element; and (d) simultaneously forming a cell plate of the cell capacitor and an upper electrode of the capacitor element.