Patent ID: 8151008

Claim:
A direct memory access (DMA) engine processing transfer requests of a data processing system, comprising: a command processor adapted to receive and interpret transfer requests of the data processing system; a transaction dispatcher having read, read response, write engines adapted to handle command and data octet transfers through a set of FIFO registers to and from a DRAM controller and a global bus interface in accord with transfer requests interpreted by the command processor; and a channel scanner having a deadline engine and a transaction controller, the deadline engine adapted to determine a transfer urgency, and the transaction controller adapted to schedule among multiple transfer requests interpreted by the command processor based on the determined transfer urgency of the respective transfer requests so as to control the engines of the transaction dispatcher, wherein the transfer urgency is based on both a transfer deadline and a transfer priority, such that higher priority transfers have higher urgency, and equal priority transfers with earlier deadlines have higher urgency, and wherein the transfer priority is based on a hardness representing a penalty for missing a deadline and is also assigned to zero-deadline transfer requests wherein there is a penalty no matter how early the transfer completes.