Patent ID: 7414906

Claim:
A memory component, comprising: a plurality of bit lines arranged in a plurality of columns; a plurality of word lines arranged in a plurality of rows substantially perpendicularly to the plurality of columns; a plurality of memory cells are disposed at respective intersections of each bit line and each word line; and a plurality of sense amplifiers arranged in a plurality of rows, wherein the sense amplifiers of each row are arranged into groups of adjacent sense amplifiers which are connected to respective adjacent bit lines, wherein each group comprises at least three adjacent sense amplifiers and a corresponding number of adjacent bit lines, and wherein there are no intervening bit lines at any point between the adjacent bit lines along their respective lengths; and wherein the bit lines between a first and second adjacent rows of sense amplifiers are arranged into groups, each group comprising at least three adjacent bit lines, and connected in an interleaved arrangement, wherein the groups of bit lines are connected in an alternating manner to respective adjacent sense amplifiers of the first row and respective adjacent sense amplifiers of the second row.