Patent ID: 8013378

Claim:
A semiconductor memory device, comprising a memory cell array, wherein the memory cell array includes in a region defined by an element isolation region in a substrate: a plurality of bit line diffusion layers extending in a column direction in the substrate to form sub bit lines, the plurality of bit line diffusion layers are not coupled to one another; a plurality of word lines extending in a row direction over the substrate so as to cross the plurality of bit line diffusion layers; a plurality of memory cells each formed by a pair of bit line diffusion layers located adjacent to each other, a word line crossing a region interposed between the pair of bit line diffusion layers, and a gate insulating film formed between the substrate and the word line, and each sharing one of the plurality of bit line diffusion layers with an adjacent memory cell; a plurality of selection word lines extending in the row direction; a plurality of main bit lines extending in the column direction; and a plurality of selection transistors each having its gate connected to one of the plurality of selection word lines, its source connected to one of the plurality of bit line diffusion layers, and its drain connected to one of the plurality of main bit lines, for selecting any of the plurality of memory cells, wherein the plurality of memory cells are memory cell groups arranged in the column direction, each memory cell group consisting of (8×N) (where N is a natural number) memory cells arranged in the row direction as a unit to be used as a storage region, the element isolation region is provided between adjacent ones of the plurality of memory cells, and within one of the plurality of memory cells: the number of the plurality of selection word lines is at least eight, the number of selection transistors corresponding to at least N is connected to each of the plurality of selection word lines, and at least one selection transistor in addition to (8×N) selection transistors are connected in total to the plurality of selection word lines, the (8×N) selection transistors of the plurality of selection transistors are formed by (4×N) pairs of selection transistors having their respective gates connected to different selection word lines and having a common drain, the plurality of main bit lines includes at least one main bit line in addition to (4×N) main bit lines connected to the common drain of the pair of selection transistors, and each bit line diffusion layer of the plurality of memory cells is connected to the source of a corresponding one of the plurality of selection transistors.