Patent ID: 7465622

Claim:
A method for fabricating a vertical channel transistor device comprising: forming a pad layer on a semiconductor substrate; forming an opening in the pad layer and the semiconductor substrate; forming a first doped silicon layer inside the opening, wherein the first doped silicon layer has a first conductivity type; forming a second doped silicon layer on the first doped silicon layer, wherein the second doped silicon layer has a second conductivity type and a top surface lower than a top surface of the pad layer; forming a first spacer on the pad layer and partially exposing the second doped silicon layer; removing the exposed second doped silicon layer and a portion of the first doped silicon layer to partially expose the semiconductor substrate; forming a second spacer covering the first spacer, the second doped silicon layer, and the first doped silicon layer; forming a third doped silicon layer on the exposed semiconductor substrate, wherein the third doped silicon layer has the second conductivity type; partially removing the second spacer to partially expose the second doped silicon layer; forming a fourth doped silicon layer on the third doped silicon layer and connecting with the second doped silicon layer in the opening, wherein the fourth doped silicon layer has the second conductivity type; forming a fifth doped silicon layer on the fourth doped silicon layer in the opening, wherein the fifth doped silicon layer has the first conductivity type; removing the pad layer; performing an ion implantation process to form a drain extension in the semiconductor substrate; forming a gate dielectric layer on a sidewall of the second doped silicon layer; and forming a sidewall gate covering the gate dielectric layer and on a sidewall of the first spacer such that the vertical channel transistor device is fabricated.