Patent ID: 8644089

Claim:
A semiconductor memory device that selects a half page based on a particular bit of a row address, comprising: an input unit configured to receive the particular bit of the row address in response to a bank active pulse and a row address enable pulse; a control signal generation unit configured to output a mode control signal in response to a signal related to a mode for selecting a whole page; first and second mode control units configured to transfer a first output signal and a second output signal of the input unit that correspond to the particular bit of the row address and an inverse signal thereof, respectively, in response to the mode control signal; a row precharge pulse generation unit configured to generate a row precharge pulse that is enabled in an initial period of a precharge duration in response to the mode control signal and a row active signal; a first driving unit configured to pull-up/pull-down drive an output terminal that corresponds to a first pre-decoding signal in response to the row precharge pulse and an output signal of the first mode control unit; a second driving unit configured to pull-up/pull-down drive an output terminal that corresponds to a second pre-decoding signal in response to the row precharge pulse and an output signal of the second mode control unit; and first and second latch units configured to latch output signals of the first driving unit and the second driving unit, respectively.