Patent ID: 7723219

Claim:
A process for fabricating a semiconductor device, comprising: forming a gate dielectric layer on a silicon substrate; forming a polycrystalline silicon gate layer on the gate dielectric layer; defining gate electrodes in said polycrystalline silicon gate layer; holding the silicon substrate on a support surface in a reactor chamber; introducing into the chamber a first process gas comprising more than 50% of helium and less than 50% of a dopant hydride gas, at a first flow rate; introducing into the chamber Argon gas at a second flow rate that is within a factor of 10 of said first flow rate; applying RF plasma source power to a toroidal plasma source of the chamber to generate a plasma from said first process gas and Argon gas; and coupling sufficient RF bias power to said wafer to generate a bias voltage on said wafer corresponding to a desired ion implantation depth profile; wherein said applying RF plasma source power comprises coupling RF source power to the interior of each of a pair of mutually transverse external reentrant conduits of said chamber.