Patent ID: 8438453

Claim:
A non-volatile memory (NVM) device, comprising: an interface configured to receive a read command and a read status request from a host controller; a number of concurrently addressable memory units each containing a number of blocks, wherein each concurrently addressable unit is configured to be simultaneously readable with respect to the other concurrently addressable memory units, and wherein the read command specifies one or more blocks of one or more of the concurrently addressable memory units from which to read data; a controller coupled to the interface and the number of concurrently addressable memory units, the controller configured to: read data from the one or more blocks of the one or more concurrently addressable memory units specified by the read command; error correct a portion of the data; make the error corrected portion of the data available for transferring to the host controller prior to making another portion of the data available for transfer; and respond to the read status request with information indicating that the error corrected portion of the data is available for transfer.