Patent ID: 8652915

Claim:
A method of fabricating a semiconductor device comprising: forming a gate electrode on a substrate; forming a spacer on sidewalls of the gate electrode; etching a predetermined portion of the substrate exposed by the spacer and the gate electrode to form a first preliminary trench; forming a sacrificial layer on a bottom surface of the first preliminary trench that exposes a sidewall of the first preliminary trench; laterally etching the sidewall of the first preliminary trench to form a second preliminary trench; removing the sacrificial layer; etching the second preliminary trench to form a trench; and forming a SiGe epitaxial layer in the trench, wherein the trench has a hexagonal profile; wherein etching the second preliminary trench is performed by crystallographic anisotropic etching based on wet etching; wherein KOH, NaOH, NH 4 OH, or tetramethyl ammonium hydroxide (TMAH) is used as an etching solution in the crystallographic anisotropic etching based on wet etching; wherein laterally etching the sidewall of the first preliminary trench comprises laterally etching the sidewall of the first preliminary trench exposes a predetermined portion of a bottom surface of the spacer beneath the substrate; and wherein a location on a sidewall of the second preliminary trench defining a maximum width thereof is closer to a top surface of the substrate than a location on the sidewall of the first preliminary trench defining a maximum width thereof.