Patent ID: 7984233

Claim:
A mass storage system, comprising: an array of non-volatile charge storage semiconductor memory cells organized into blocks that individually have a capacity of storing multiple units of received data that individually include at least 512 bytes of data, the memory cells of the individual blocks being concurrently erased prior to any new data being written therein, and a controller connected with the memory cell array and adapted to receive data of individual files having a logical address including a unique file identification and offsets of data within an identified file to program the received data at physical addresses within the blocks of memory cells, and which further operates to maintain a plurality of records of the programmed data for the individual files that identify groups of variable amounts of data making up the identified file, data within the groups individually having both contiguous logical offset addresses and contiguous physical addresses, wherein each individual record of the plurality of records include the file identification, at least a logical offset address of data within the identified file and a corresponding physical address of the data within the group, and the controller further operates to program in a single one of the blocks of memory cells at least two of the groups of data from the identified file, wherein the at least two of the groups of data have a discontinuity of offset addresses between the at least two of the groups of data and contiguous physical addresses between the at least two of the groups of data, the mass storage system directly translates file identifiers and offsets received from a host into physical addresses of blocks and pages of memory cells in which data of the individual files are written without the use of any intermediate logical address conversion.