Patent ID: 7327594

Claim:
A read-only memory (ROM) array comprising a matrix of ROM cells arranged in rows and in columns, the cells of a same row being connected to a word line dedicated to said row, and comprising: two metallization levels, lower and upper respectively, overlaid above the cell matrix; and two bit lines being respectively arranged in the two levels above each cell of the cell matrix, and being oriented substantially parallel to the direction of the columns, the bit lines of the memory array being paired so that a signal for reading a binary value stored in a cell connected to a bit line belonging to a pair is detected by comparing it with a signal reference level supplied by the other bit line of said pair, the matrix being divided into segments each comprising a given number of successive rows, and wherein at least some of the bit lines are also arranged into groups of four bit lines overlaid two on two in the lower and upper metallization levels above two columns of cells in a first segment of the matrix, so that the configuration of the bit lines of at least one of said groups in a second matrix segment adjacent said first segment corresponds to a circular permutation of said bit lines with respect to the configuration in the first segment of the matrix, at least one bit line of said group passing from one level of metallization to the other between said first and second segments of the matrix, and at least one bit line from said group being situated above two different columns in said first and second segments of the matrix.