Patent ID: 7755949

Claim:
A self timed compiler memory array, comprising: a memory array including a plurality of bitlines (BLs) and a plurality of wordlines (WLs); a peripheral logic coupled to the memory array via the BLs; a control block coupled to the peripheral logic for initiating an internal clock during the start of a read cycle; a tracking circuit including a dummy bitline (DBL) and an associated dummy wordline (DWL); and a precharge circuit coupled to the BLs and the DBL, wherein the DWL and the WL goes high upon the internal clock going high, which in turn triggers the DBL and the BLs to go low, wherein the tracking circuit generates a reset BL signal upon the DWL going high and DBL going low, wherein the generated reset BL signal stops the DBL from going further low and triggers the precharge circuit to precharge the DBL to go high, and wherein the reset BL signal starts an internal cycle reset signal which in turn resets the internal clock and enables precharging of BLs.