Patent ID: 8008132

Claim:
A method of fabricating a leadframe package including a leadframe and a semiconductor die, the leadframe including a die paddle supporting the semiconductor die and the semiconductor die including die bond pads along at least two sides, the method comprising the steps of: (a) defining a plurality of electrical terminals around a periphery of the leadframe, the electrical terminals being exposed at a bottom surface of the leadframe package for connection to a host printed circuit board; (b) defining one or more electrically conductive islands on the leadframe at least in part between the electrical terminals and the die paddle and formed at least in part by half-etching an area adjacent the islands on the leadframe, the islands being exposed at the bottom surface of the leadframe package for connection to the host printed circuit board, and one island of the one or more electrically conductive islands connected to at least one other terminal of the plurality of electrical terminals or another island of the one or more electrically conductive islands; and (c) wirebonding the die bond pads to the electrical terminals defined in said step (a) and the one or more electrically conductive islands defined in said step (b).