Patent ID: 8032734

Claim:
A hardware processor, comprising: an execution unit that executes instructions out of program order; a coprocessor that executes instructions in program order; and a coprocessor interface unit, coupled between the execution unit and the coprocessor, the coprocessor interface unit including a coprocessor load data queue that stores data received from the execution unit until an instruction that operates upon the data is present within the coprocessor, wherein the data may be written to the coprocessor load data queue out of program order, and wherein the coprocessor load data queue comprises a plurality of entries, and each entry has a plurality of associated status values including a valid bit that is set upon allocation, a ready bit that is set upon the date being written into the coprocessor load data queue, a committed bit that is set upon a load instruction graduating, and an issued bit that is set when an in-order instruction queue issues a corresponding instruction to the coprocessor.