Patent ID: 6858492

Claim:
A method for fabricating a semiconductor memory device including a semiconductor region having a surface, source and drain regions within the semiconductor region, and gates between the source and drain regions with gate oxide regions below the gates, intermediate regions disposed between the source and drain regions and above the gate oxide regions and the gates, a first passivation region on the surface of the semiconductor region, and capacitor devices having electrode devices and plugs, the electrode devices being connected with the source and drain regions via the plugs through the first passivation region, the method which comprises: forming on the semiconductor region having the source and drain regions, the gate oxide regions, and the gates, a passivation region including at least the first passivation region; forming in the passivation region above the gates and the gate oxide regions, at first locations, first cutouts, the first cutouts not extending to the gates and yielding three-dimensional protruding structures of the passivation region for forming the plugs to be formed at second locations above the source and drain regions; forming the capacitor devices between the three-dimensional structures of the passivation region; forming contacts of the capacitor devices and of the electrode devices with the source and drain regions by forming the plugs after forming the capacitor devices by selectively forming second cutouts in the passivation region at the second locations of the pasivation region, the second cutouts extending to the source and drain regions, and by filling the second cutouts with an electrical conducting material.