Patent ID: 8509004

Claim:
A nonvolatile logic circuit comprising: a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively; an inverter configured to invert an input data and to output an inverted input data; a first transmission unit configured to transmit the input data to the first latch node when a read enable signal is not activated; and a second transmission unit configured to transmit the inverted input data to the second latch node when the read enable signal is not activated, wherein a write operation is performed on the first and second nonvolatile memory cells by supplying current to the first and second nonvolatile memory cells in different directions when a write enable signal is activated, the direction of flow of current being determined based on a logic value of data stored on the respective first and second latch nodes, and a logic value stored in the first nonvolatile memory cell is different from a logic value stored in the second nonvolatile memory cell.