Patent ID: 7543209

Claim:
A method of characterizing jitter sensitivity of a clock and data recovery (CDR) circuit connected in series with a deserializer (DES) circuit within a serializer/deserializer (SERDES) circuit having built-in self-test (BIST) capabilities, the method comprising: generating a serial data stream by the serializer (SER) circuit that is continuously applied to the CDR circuit and the DES circuit; inserting a first start-of-frame pattern in the serial data stream; adding a pre-determined perturbation delay to said serial data stream to produce a perturbed serial data stream; applying the perturbed serial data stream instead of the serial data stream to the CDR circuit and the DES circuit: inserting a second start-of frame pattern in the perturbed serial data stream; and determining whether the DES circuit has detected whether said second start-of-frame pattern has the same bit alignment as the first start-of frame pattern.