Patent ID: 7138673

Claim:
A semiconductor package comprising: a planar mounting element; a semiconductor chip having a bottom surface on which a first electrode is formed, and a top surface on which a second electrode and a third electrode are formed, said semiconductor chip being mounted on said planar mounting element such that the first electrode of said bottom surface is in electrical contact with said planar mounting element; a first lead element having a first inner portion and a first outer portion, said first inner portion extending from said planar mounting element and electrically connected to said first electrode via said planar mounting element; a second lead element having a second inner portion and a second outer portion, said second inner portion being bonded and electrically connected to said second electrode; a third lead element having a third inner portion and a third outer portion, said third inner portion being positioned above and spaced apart from said top surface of said semiconductor chip; a bonding wire element electrically connecting between said third inner portion and said third electrode; and an enveloper encapsulating said planar mounting element, said semiconductor chip, said bonding wire element, and said first, second and third inner portions of said first, second and third lead elements.