Patent ID: 6842388

Claim:
A semiconductor memory device comprising: a plurality of memory cells; bit line pairs to which the memory cells are connected; a plurality of precharge circuits for precharging the bit line pairs to a first voltage that is different from a mean value between a high level and a low level, in accordance with a first control signal; a bit line precharge power line for supplying the first voltage for precharging to the precharge circuits; a first capacitor; a charging circuit for charging the first capacitor; a transfer gate circuit for controlling connection and disconnection between the first capacitor and the bit line precharge power line; and a first control circuit for controlling the charging circuit and the transfer gate circuit; wherein the first control circuit, in accordance with a second control signal, controls the transfer gate circuit so that during precharging of the bit line pairs, the first capacitor and the bit line precharge power line are connected.