Patent ID: 7924640

Claim:
A test method comprising: providing an integrated circuit, wherein said integrated circuit comprises a first memory base cell, wherein said first memory base cell comprises a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, wherein said set of other nodes comprises a first data node for accessing said first storage node set, a first access control node for controlling the access of said first storage node set, a first supply node for supplying said first storage node set, and a second supply node for supplying said second storage node set, wherein said first and second supply nodes are of the same sinking or sourcing type; conducting a circuit element test on a circuit element in said set of circuit elements, wherein in said circuit element test said first and second supply nodes are not connected together, each terminal of said circuit element is directly forced with an electrical quantity, and an electrical quantity is directly measured from a terminal of said circuit element; and conducting a static noise margin test on said first memory base cell, wherein in said static noise margin test said first and second supply nodes are not connected together, wherein said static noise margin test comprises a first inverter transfer curve test and a second inverter transfer curve test, wherein in said first inverter transfer curve test all nodes in said second storage node set are connected together, a voltage is directly forced to all nodes in said first storage node set, and a voltage is directly measured from a node in said second storage node, and wherein in said second inverter transfer curve test all nodes in said first storage node set are connected together, a voltage is directly forced to all nodes in said second storage node set, and a voltage is directly measured from a node in said first storage node set.