Patent ID: 7190623

Claim:
A memory cell comprising: an N-type well; three P-type doped regions formed on the N-type well; a dielectric layer comprising silicon dioxide, formed on the N-type well and between first and second doped regions of the three P-type doped regions; a first gate formed on the dielectric layer; a charge storage structure formed on the N-type well and between the second and third doped regions of the three P-type doped regions, wherein the charge storage structure stores charges and thereby changes a threshold voltage required for conducting a P-type channel between the second and third doped regions, the charge storage structure comprising: a first silicon dioxide layer formed on the N-type well; a charge storage layer formed on the first silicon dioxide layer and comprising silicon nitride (Si 3 N 4 ) or silicon oxynitride (Si x N y O z ); and a second silicon dioxide layer formed on the charge storage layer; and a second gate formed on the charge storage structure.