Patent ID: 8537859

Claim:
A system, comprising: a processor; a reassembly buffer that receives mini-packets; and at least one data structure that comprises bits that correspond to: an entry for each mini-packet received in the reassembly buffer, each entry comprising a present bit having a value to indicate whether a corresponding mini-packet is present in the reassembly buffer and a final mini-packet bit to indicate whether the corresponding mini-packet is the final mini-packet in a series of mini-packets; and a present sense bit, wherein said present sense bit is to indicate a current meaning of the value of the present bit; wherein the processor is to use said bits to determine whether all of the mini-packets belonging to said series of mini-packets are present in the reassembly buffer; and wherein, as a result of said determination, the processor is to read said series of mini-packets from the reassembly buffer and invert the present sense bit.