Patent ID: 7397409

Claim:
A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure, comprising: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages for receiving analog signals, converting them into digital signals, and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of the first to K-th stages for converting differences between digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected with an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein N is an integer greater than or equal to 1 and K is an integer greater than or equal to 2.