Patent ID: 7062081

Claim:
A method for analyzing defects in electronic circuit patterns, comprising: a step for inspecting a first object to detect defects during a production process and obtaining position information of said defects; a step for detecting images of said defects using said position information of said defects obtained; a step for performing an electronic test on said first object after said production process is completed to detect faults in said first object and obtain position information of said faults; a step for comparing said position information of said defects with said position information of said faults and extracting defects having common position information between said defects and said faults; a step for classifying images of extracted defects into critical defect images and non-critical defect images based on a pre-stored classification rule which defines critical and non-critical defects by referring to images of defects, position information of said defects and results of performing the electronic test to each other; a step for displaying images of classified defects on a screen by discriminating between said critical defect images and said non-critical defect images; a step for modifying said pre-stored classification rule by correcting classification of classified defect images displayed on the screen; a step for inspecting a second object during the production process to detect defects and obtain information of said defects including position information and image of said defects; a step for classifying images of said defects detected on said second object into critical defects and non-critical defects by using a modified classification rule; and a step for outputting information on said classified defect images of said second object.