Patent ID: 7124389

Claim:
A semiconductor device, comprising: a substrate; a first interlayer insulating layer on the substrate; a first metal wiring on the first interlayer insulating layer, the first metal wiring having a width of W, extending in a first direction, and having a first end portion; a second interlayer insulating layer covering the first metal layer and the first interlayer insulating layer; a second metal wiring on the second interlayer insulating layer, the second metal wiring extending in a diagonal direction forming a predetermined angle with the first metal wiring, having a second end portion positioned above first end portion of the first metal wiring, and having a width wider than width W of the first metal wiring; and a VIA contact passing through the second interlayer insulating layer and connecting the first end portion of the first metal wiring and the second end portion of the second metal wiring; wherein the cross-sectional shape of the VIA contact is an oval shape where the ratio of the minor axis and the major axis is at least two; and falls completely inside the end portion of the first metal wiring and the second end portion of the second metal wiring.