Patent ID: 8473827

Claim:
An encoder comprising: a coding section that generates coded sequence s that satisfies equation 1-1, equation 1-2 and equation 1-3 for information bit sequence u; and a setting section that sets a y-th puncturing pattern which corresponds to the number of columns z ranging from z×y+1 columns (y is an integer between 0 and (n b −1)) to z×(y+1) columns, and which has a cycle of divisors of the number of columns z, wherein, in the coded sequence s made up of z×n b bits from a first bit to a z×n b -th hit, bits to be removed are determined from a z×y+1-th bit to a z×(y+1)-th bit, based on the y-th puncturing pattern, the bits determined to be removed are removed from the z×n b bits making up the coded sequence s to form a transmission information bit sequence, and the transmission information bit sequence is outputted: [1] GH T =0 (Equation 1-1) s T =Gu T (Equation 1-2) Hs= 0 (Equation 1-3) where H is a parity check matrix of an low density parity check code of (z×mb) rows and (z×nb) columns configured by arranging submatrixes of z rows and z columns in nib rows and nb columns, G is a generator matrix holding a relationship of equation 1-1 with parity check matrix H of the low density parity check code and the coded sequence s is a coded sequence made up of z×nb bits.