Patent ID: 8250231

Claim:
A method to reduce buffer capacity in a processor comprising a processing pipeline and at least one interface for data packets, wherein the processing pipeline comprises of a plurality of processing elements and a plurality of processing element buffers, wherein each corresponding processing element buffer precedes each corresponding processing element, comprising the steps of: giving the data packets admittance to the processor through the at least one interface; storing the data packets in at least one input buffer; using a packet rate shaper outside of the pipeline to control flow of the data packets to the pipeline in dependence of cost information per packet, wherein the flow of the data packets is controlled before the data packets enter the pipeline, wherein the controlling of the flow of the data packets in dependence of the cost information is based on capacity constraints in the processing pipeline; giving a first data packet admittance to the pipeline; giving a second data packet admittance to the pipeline in dependence on the cost information per packet, wherein the cost information per packet is dependent upon an expected time period of residence of the first data packet in at least a part of the pipeline, and wherein cost information dependent upon an expected time period of residence of the second data packet in at least a part of the pipeline differs from said cost information dependent upon the expected time period of residence of the first data packet in at least a part of the pipeline; storing the data packets in the plurality of processing element buffers; processing the data packets in the plurality of processing elements; storing the data packets in at least one output buffer in the processor; and transmitting the data packets through at least one output port in the processor.