Patent ID: 7587690

Claim:
A method for performing coverage analysis of a design, comprising: receiving a list of critical paths and one or more constraint information; identifying gate-level critical path coverage based at least in part upon gate-level information and the one or more constraint information; pruning the identified gate-level critical path coverage from the list of critical paths based at least in part upon identified coverage for the gate-level information; identifying RTL-level critical path coverage based at least in part upon RTL-level information; pruning the identified RTL-level critical path coverage from the list of critical paths based at least in part upon identified coverage for the RTL-level information; determining, by using a processor, a global coverage for the design based at least in part upon the pruned list of critical paths; and storing the global coverage for the design in a volatile or non-volatile computer readable medium or displaying the global coverage for the design on a display device.