Patent ID: 8588012

Claim:
A method of controlling memory devices including first and second memory devices disposed on a first memory module and coupled in common to a signaling link, the method comprising: enabling the first memory device to switchably couple a first termination load to the signaling link; enabling the second memory device to switchably couple a second termination load to the signaling link concurrently with enabling the first memory device to switchably couple the first termination load to the signaling link; outputting a first memory write command via one or more command signaling links coupled in common to the first and second memory devices; outputting a write data value via the signaling link during an interval in which the first and second memory devices are enabled to couple the first and second termination loads to the signaling link; and concurrently with enabling the first and second memory devices to couple the first and second termination loads to the signaling link, outputting first a d second chip-select signals in respective states to enable the first memory device, but not the second memory device, to store the write data value in response to the first memory write command.