Patent ID: 8314495

Claim:
A semiconductor device comprising: a wiring substrate including a core substrate having first and second surfaces opposed to each other, and first and second build-up substrates on the first and second surfaces of the core substrate, respectively, the core substrate comprising a first insulating layer, first wiring layers on the first surface and second wiring layers on the second surface, the first wiring layers on the first surface and the second wiring layers on the second surface being electrically connected to each other through first through holes in the first insulating layer of the core substrate, respectively, the first build-up substrate comprising a second insulating layer and third wiring layers, the third wiring layers of the first build-up substrate being electrically connected to the first wiring layers on the first surface of the core substrate through second through holes in the second insulating layer of the first build-up substrate, respectively, and the second build-up substrate comprising a third insulating layer and fourth wiring layers, the fourth wiring layers of the second build-up substrate being electrically connected to the second wiring layers on the second surface of the core substrate through third through holes in the third insulating layer of the second build-up substrate, respectively; a semiconductor chip comprising a substrate which has third and fourth surfaces opposite to each other, semiconductor elements on the third surface, a silicon oxide film covering the semiconductor elements, an inter layer insulating film over the silicon oxide film, pad electrodes over the inter layer insulating film and internal wiring layers electrically connecting the semiconductor elements with the pad electrodes, the inter layer insulating film having an electrical constant lower than that of the silicon oxide film, the semiconductor chip being on the first build-up substrate such that the third surface of the substrate faces the first build-up substrate and the semiconductor elements are electrically connected with the third wiring layers of the first build-up substrate via first bump electrodes disposed between the pad electrodes of the semiconductor chip and the first build-up substrate; a resin layer between the semiconductor chip and the first build-up substrate and between the first bump electrodes; and second bump electrodes on the second build-up substrate and electrically connected with the fourth wiring layers of the second build-up substrate, wherein the first insulating layer of the core substrate, and the second and third insulating layers of the first and second build-up substrates, contain glass cloths, respectively.