Patent ID: 8019979

Claim:
An apparatus for implementing a branch intensive algorithm, comprising: a processor comprising: a plurality of ALUs; a plurality of result registers, each result register being responsive to outputs of the plurality of ALUs; wherein the plurality of result registers each have a guard input that is responsive to a selection signal enabling the plurality of ALUs to write contents at a proper result register; a lookup table dynamically programmed with logic to implement a plurality of upcoming logic equations, the lookup table being responsive to outputs of the plurality of ALUs; wherein the lookup table outputs the selection signal(s) based upon outputs from the plurality of ALUs and the programmed logic for implementing the plurality of upcoming logic equations; wherein the branch intensive algorithm is selected from the group consisting of JPEG 2000, VC-3, VC-2, MC-FRC, De-Interlacing, Noise Reduction, and Detail Enhancement.