Patent ID: 8719489

Claim:
A system, comprising: a processor that supports timing and data flow from a FLASH memory device to a volatile memory, wherein the volatile memory is a random access memory; a controller that regulates read and write access to the FLASH memory device employed for a random access memory application and determines that a sector of the FLASH memory device is heavily used, wherein the controller is an application specific integrated circuit configured to occupy and communicate with an expansion memory slot of a computer, and wherein the FLASH memory is utilized as a main memory for the memory system; a free list component that analyzes the volatile memory and identifies a free area of the volatile memory that is not in use by an application; a wear leveling component that moves data from a heavily used sector of the FLASH memory device to the free area of the volatile memory and wherein memory operations associated with the sector of the FLASH memory device are executed in the volatile memory: and a dynamic random access memory (DRAM) buffer component that operates with the control to smooth data storage requirements across the FLASH memory device.