Patent ID: 7849255

Claim:
A memory comprising: at least one array of memory elements; a partition of the at least one array into a plurality of sub-arrays of the memory elements; an array configuration circuit for selectively placing the at least one array in one of two operating configurations, the two operating configurations including: a first operating configuration, in which the memory elements of the at least one array are coupled one to another to form a monodimensional sequentially-accessible memory, and a second operating configuration, in which the memory elements in each sub-array are coupled to one another so as to form an independent monodimensional sequentially-accessible memory block, the memory blocks of each sub-array being isolated from the memory blocks of the other sub-arrays, and a data content of any memory element of the sub-array being rotatable by shifts through the memory elements of the sub-array; a sub-array selector, responsive to a first memory address, for selecting one among the plurality of sub-arrays according to the first memory address, the sub-array selector enabling access to the selected sub-array; a memory element access circuit, responsive to a second memory address, for enabling access to a prescribed memory element in the selected sub-array after a prescribed number of shifts, depending on the second memory address, of the data content of the memory elements in the selected sub-array; wherein the first operating configuration is a data storage configuration in which the memory is placed when data are to be stored therein; and wherein the second operating configuration is a data retrieval configuration in which the memory is placed when data are to be retrieved therefrom.