Patent ID: 8546274

Claim:
A method, comprising: conformally forming a first stress-inducing layer above a first transistor and a second transistor formed above a substrate, said first stress-inducing layer generating a first type of stress; forming a first dielectric layer above said first stress-inducing layer, said first dielectric layer having an internal stress level less than a stress level of said first stress-inducing layer; selectively removing said first stress-inducing layer and said first dielectric layer from above said first transistor, a portion of said first dielectric layer remaining above said second transistor; forming a second stress-inducing layer above said first transistor and said portion of said first dielectric layer, said second stress-inducing layer inducing a second type of stress different from said first type of stress; selectively removing said second stress-inducing layer from above said second transistor using said portion of said first dielectric layer as an etch stop material; forming a second dielectric layer directly on said second stress-inducing layer above said first transistor and directly on said portion of said first dielectric layer remaining above said second transistor; forming a third stress-inducing layer directly on second dielectric layer and above said first and second transistors, said third stress-inducing layer inducing said second type of stress; and forming an interlayer dielectric layer above said third stress-inducing layer.