Patent ID: 8798222

Claim:
A method for linearizing a phase interpolator, comprising: obtaining a mapping of up to 2 N desired phase values to a corresponding M bit value, wherein a subset of said M bit values are mapped to a corresponding N bit value; identifying an M bit value corresponding to a desired phase value; determining an N bit value that is mapped to said identified M bit value, where M is a value greater than N; applying said determined N bit value to a selector indexed by said N bit value to obtain said identified M bit value; and applying said identified M bit value to said phase interpolator to obtain said desired one of said 2 N desired phase values wherein said phase interpolator is an over-sampled phase interpolator; wherein said obtaining step further comprises the step of evaluating a plurality of phases of an interpolated clock signal generated by said phase interpolator as a function of a plurality of applied interpolation control codes.