Patent ID: 7928491

Claim:
A semiconductor memory device, comprising: a substrate; a memory cell transistor of a split-gate type formed on said substrate, said memory cell transistor having a source/drain region, a floating gate and a control gate, and is configured to store data and generate a read current; a MIS (Metal Insulator Semiconductor) reference transistor formed on said substrate, said reference transistor having a source/drain region and a first single gate and is configured to generate a reference current; a sense amplifier connected to said source/drain region of said memory cell transistor and to said source/drain region of said reference transistor, said sense amplifier being configured to compare said read current generated by said memory cell transistor with said reference current generated by said reference transistor to read said data stored in said memory cell transistor; a conductive layer formed above said reference transistor; a MIS (Metal Insulator Semiconductor) logic transistor used in a logic circuit, said logic transistor having a second single gate whose material and thickness are the same as those of said conductive layer; a first insulating film formed between said first single gate and said substrate; a second insulating film formed between said conductive layer and said first single gate; a third insulating film formed between said second single gate and said substrate; and a contact configured to penetrate through said second insulating film, and connected to said first single gate, wherein said first single gate operates as a gate electrode of said reference transistor.