Patent ID: 8436455

Claim:
A stacked structure of semiconductor packages, comprising: an upper semiconductor package; a lower semiconductor package; and a plurality of inter-package connectors located between the upper semiconductor package and the lower semiconductor package, wherein the upper semiconductor package includes: an upper package substrate; a plurality of upper semiconductor chips stacked on the upper package substrate; and one or more conductive upper connection lands formed on a bottom surface of the upper package substrate, wherein the lower semiconductor package includes: a lower package substrate; a plurality of lower semiconductor chips stacked on the lower package substrate; and at least one lower through-silicon vias vertically penetrating one or more of the lower semiconductor chips, and wherein each of the plurality of inter-package connectors is electrically connected to at least one of the plurality of upper connection lands, and wherein the upper semiconductor package, the lower semiconductor package, and the plurality of inter-package connectors are part of a control unit, an input unit, an output unit, or a storage unit that are included in an electronic system.