Patent ID: 8564112

Claim:
A semiconductor device comprising: a first semiconductor chip including a first power MOSFET, a second power MOSFET, a first diode for detecting the heat generation for the first power MOSFET, and a second diode for detecting the heat generation for the second power MOSFET, the semiconductor chip having a main surface over which a first electrode pad electrically connected to the first power MOSFET, a second electrode pad electrically connected to the second power MOSFET, and a third electrode pad for electrically connecting to a control circuit for controlling the first semiconductor chip are formed, a first side of the main surface extending along a first direction, a second side of the main surface facing the first side and extending along the first direction, a third side of the main surface intersecting with the first and second sides and extending along a second direction perpendicular to the first direction, and a fourth side of the main surface intersecting with the first and second sides, facing the third side, and extending along the second direction; a first chip mounting portion over which the first semiconductor chip is mounted; a first lead electrically connecting the first electrode pad of the first semiconductor chip; a second lead electrically connecting the second electrode pad of the first semiconductor chip; and a sealing body sealing the first semiconductor chip and a part of each of the first and second leads, wherein, in a plan view, the first and second leads are arranged such that the first and second leads are more proximate to the third side than the fourth side of the first semiconductor chip and extend along the first direction, wherein, in the plan view, the first diode is arranged such that the first diode is more proximate to the first and fourth sides than the second and third sides of the first semiconductor chip, wherein, in the plan view, the second diode is arranged such that the second diode is more proximate to the second and fourth sides than the first and third sides of the first semiconductor chip, wherein, in the plan view, the first electrode pad is arranged such that the first electrode pad is more proximate to the first and third sides than the second and fourth sides of the first semiconductor chip, wherein, in the plan view, the second electrode pad is arranged such that the second electrode pad is more proximate to the second and third sides than the first and fourth sides of the first semiconductor chip, and wherein, in the plan view, the third electrode pad is arranged such that the third pad is more proximate to the fourth side than the third side and positioned between the first and second diodes of the first semiconductor chip.