Patent ID: 7096246

Claim:
An arithmetic unit for multiplying a first quantity X by a second quantity Y, said arithmetic unit comprising: a Booth coder having a plurality of inputs for receiving a plurality of bits of the second quantity and a plurality of outputs for providing Booth coded outputs; circuitry connected to either at least one of said inputs for receiving one of said plurality of bits of the second quantity or to said outputs for providing Booth coded outputs; said circuitry comprising a further input to receive a signal indicating if a multiply accumulate or multiply subtract function is to be performed, said circuitry arranged to modify at least one output of the coder if necessary in accordance with said signal, whereby the output of said Booth coder unit is a Booth coded signal modified if necessary to take into account the function to be performed wherein said coder is arranged to provide a SNGL output, an NZP output and an NZN output; wherein said unit is capable of performing the calculations X multiplied by Y and X multiplied by Y, the output of the Booth coder being the same for both of said calculations; and a Booth decoder arranged to separate a partial product from said Booth coded signal and said first quantity.