Patent ID: 7473568

Claim:
A memory-module manufacturing method comprising: receiving partially-tested memory chips, wherein the partially-tested memory chips are packaged dice that have not been fully tested to detect all defects; soldering the partially-tested memory chips onto module substrates to create assembled memory modules; inserting the assembled memory modules into module sockets on memory-module burn-in boards; placing the memory-module burn-in boards into a burn-in oven; stressing the assembled memory modules and the partially-tested memory chips soldered to the module substrates of the assembled memory modules by heating the assembled memory modules in the burn-in oven for a burn-in period of time; removing the memory-module burn-in boards from the burn-in oven after the burn-in period of time and extracting the assembled memory modules from the memory-module burn-in boards as burned-in memory modules; and fully testing the burned-in memory modules by applying extensive test patterns to the burned-in memory modules; wherein the extensive test patterns test for possible defects that were not detected in the partially-tested memory chips; whereby partially-tested memory chips are soldered into assembled memory modules that are burned-in and fully tested.