Patent ID: 7421633

Claim:
An integrated circuit, comprising: A. test access port circuitry having a TDI input lead, a TMS input lead, a TCK input lead, and a TDO output lead; and C. controller circuitry having a TMS/TDI input lead, a clock input lead, and a TDO output lead, the controller circuitry being connected to the test access port circuitry by a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead of the test access port circuitry and to the TDO output lead of the controller circuitry, the controller circuitry including: i. serial input parallel output circuitry having a serial input connected to the TMS/TDI input lead, a clock input connected with the clock input lead, a TDI output, and a TMS output; ii. a TDI update register having an input connected to the TDI output of the serial input parallel output circuitry and an output connected to the TDI output lead; and iii. a TMS update register having an input connected to the TMS output of the serial input parallel output circuitry and an output connected to the TMS output lead.