Patent ID: 7704791

Claim:
A method for forming an electronic assembly, comprising: forming a plurality of integrated circuits on a wafer; forming a layer of aluminum on a side of the wafer opposing the integrated circuits; forming a layer of porous aluminum oxide on the layer of aluminum, the layer of porous aluminum oxide having a side and a plurality of pores, the pores having a barrier layer of aluminum oxide at an end adjacent to the layer of aluminum, the pores covering at least 5% of a surface area of the side; thinning the barrier layer of aluminum oxide at the end of the pores; depositing nickel catalysts into the pores; growing carbon nanotubes in the pores, the carbon nanotubes having a cylindrical shape with diameters between 10 and 1000 angstroms and heights between 1 and 10 microns; forming a layer of indium on a side of the layer of aluminum oxide opposing the layer of aluminum; and separating the wafer into microelectronic dies.