Patent ID: 8533416

Claim:
A memory system comprising: a plurality of stacked memory devices; a logic die coupled to the plurality of stacked memory devices, wherein the logic die is configured to receive strobe signals for respective ones of the plurality of stacked memory devices and provide the strobe signals to the respective ones of the plurality of stacked memory devices with a respective delay, wherein the respective delay is based at least in part on a parameter of the respective one of the plurality of stacked memory devices, wherein the logic die is further configured to receive data from the respective ones of the plurality of stacked memory devices, wherein the data is provided by the respective ones of the plurality of stacked memory devices responsive to the strobe signals, and wherein a time between receipt of a strobe signal at the logic die and receipt of responsive data from the respective one of the plurality of memory devices at the logic die is substantially the same for each of the plurality of stacked memory devices.