Patent ID: 7859045

Claim:
A semiconductor device, comprising: a semiconductor substrate; a plurality of stripe-shaped active regions which are defined in the semiconductor substrate and are arranged in parallel with each other, each of the active regions being arranged at a distance from each other; a device isolation insulating film which is formed on the semiconductor substrate and surrounds the active regions; a flash memory cell including a tunnel insulating film, a floating gate, an intermediate insulating film, and a control gate which are formed on the active region in this order; island-like lower conductor patterns made of the same material as the floating gate, where the lower conductor patterns being formed on the device isolation insulating film at an end of the active regions, and each of the lower conductor patterns being corresponding to each of the active regions; a segment of the intermediate insulating film which covers each of the lower conductor patterns and is shared by the lower conductor patterns; a dummy conductor pattern which is formed on the segment of the intermediate insulating film and is shared by the lower conductor patterns, the dummy conductor pattern being made of the same material as the control gate; and a fence of the intermediate insulating film which are formed on the device isolation insulating film and extends from a side surface of the floating gate to a side surface of the lower conductor pattern along the active region, wherein a part of the lower conductor pattern is rounded per a planar view.