Patent ID: 7636835

Claim:
An integrated circuit, comprising: a plurality of tiles, each tile comprising a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to one or more of the switches of other tiles; wherein switches in the plurality of tiles provide at least one network among all of the tiles in the integrated circuit; a plurality of interface modules each including circuitry to transfer data to and from a device external to the tiles, with each interface module further including a finite state machine configured to receive control messages from a device or from a tile, and configured to parse a control message from a device and construct a message destined for one or more tiles or another device in response to the parsed control message, a buffering module configured to store data arriving from a device or data to be provided to a device, and a multiplexer configured to select the buffering module or the finite state machine as a source of data or control messages for delivery to a destination in the at least one network; and sub-port routing circuitry in communication with the tiles and coupled to a port of a first switch of at least one tile on the periphery of all of the tiles in the at least one network, the sub-port routing circuitry disposed to route data between the port of the first switch and a plurality of sub-ports coupled to different respective interface modules, with the sub-port routing circuitry being configured to scan the sub-ports at startup to determine a map of sub-port locations for each device coupled to a sub-port using sub-port identifiers for the sub-ports that each uniquely identifies a device, to enable multiple devices coupled to respective interface modules to share the same direct connection between the sub-port routing circuitry and input and output ports of a switch for communicating with the plurality of tiles, and to route messages associated with different respective sub-port identifiers to the same output port of a switch of a tile on the periphery of the network among all of the tiles in the integrated circuit.