Patent ID: 7071485

Claim:
A semiconductor integrated circuit device having a plurality of memory cells formed on a semiconductor substrate, each made up by electrically connecting a resistor element in series with a field effect transistor comprising: a plurality of first electrodes each connected to the field effect transistor which is included in a corresponding one of the plurality of memory cells; a stacked layer film formed of a phase change material layer and a second electrode, deposited in that order, and connected to the plurality of first electrodes in common; and a power source terminal connected to the second electrode layer, wherein the phase change material layer is made of one phase change material layer or plural phase change material layers with resistance values changing by heating treatments, wherein the resistor element is a part of the stacked layer film, wherein a surface area of each of the plurality of first electrodes is smaller than a surface area of the stacked layer film, and wherein a phase change region is formed in a contact part between one of the plurality of first electrodes and the stacked layer.