Patent ID: 8703552

Claim:
A method of fabricating a device comprising: providing a substrate having a first semiconductor layer that is separated from a second semiconductor layer by an insulating layer present therebetween, in which the substrate includes at memory region and a logic region; forming trench capacitors in each of the logic region and the memory region, wherein each of the trench capacitors are produced using a same process and extend from a surface of the first semiconductor layer through the insulating layer into the second semiconductor layer, and in which each of the trench capacitors includes a first and second electrode separated by a node dielectric; forming isolation regions in the first semiconductor layer, in which the isolation regions formed in the memory region are positioned to provide at least one first semiconductor island in contact with the first electrode of at least one of the trench capacitors and the isolation regions formed in the logic region provide at least one second semiconductor island that is separated from the trench capacitors; and forming a first transistor on the at least one first semiconductor island and a second transistor on the at least one second semiconductor island, wherein the first transistor is in electrical communication with the at least one trench capacitor having the first electrode that is in contact with the first semiconductor island.