Patent ID: 8760922

Claim:
A mass storage memory device comprising: a plurality of multi-chip memory packages; one or more interfaces through which the plurality of multi-chip memory packages may communicate with a central host controller, and wherein each multi-chip memory package comprises: a plurality of memory dies, wherein a first portion of the plurality of memory dies is configured as a first type of non-volatile storage and a second portion of the plurality of memory dies is configured as a second type of non-volatile storage; and a local processor in communication with the plurality of memory dies, the local processor configured to: receive data in a pre-determined logical block address range from the central host controller; determine a storage criteria for the received data; and based on the determined storage criteria, select between one of the first portion or the second portion of memory dies for storing the received data; and store the received data in the selected one of the first or second portions of memory dies, wherein the storage criteria comprises an access frequency associated with the received data.