Patent ID: 8707133

Claim:
An interface device configured to interface between a processing device and a memory device, the interface device comprising; an error correcting code (ECC) encoder, the ECC encoder calculating at least one ECC bit and providing the at least one ECC bit to the processing device based at least in part on data provided by the memory device, the processing device comprising an ECC-based memory interface port, thereby eliminating a need to store the at least one ECC bit in the memory device; a parity encoder, the parity encoder providing at least one parity bit to the memory device based on data provided by the processing device while ignoring at least one ECC bit provided by said processing device; and a parity decoder, the parity decoder selectively modifying the at least one ECC bit provided to the processing device based on the data provided by the memory device and at least one parity bit provided by the memory device, the parity decoder inverting a plurality of ECC bits to the processing device in response to the data provided by the memory device and the at least one parity bit provided by the memory device indicating an error associated with the data provided by the memory device.