Patent ID: 8671381

Claim:
A computer-implemented method for optimizing a number of dies that can be fabricated on a wafer, the computer-implemented method comprising: receiving input variables comprising: a minimum die width (x min ), a minimum die height (y min ), a target aspect ratio, a target die area (A target ), a wafer area (A w ), an edge band width (w eb ), and a scribe width (w s ); executing a die number optimization (DNO) routine to determine a maximum number of dies (N max ) for the target die area (A target ), wherein the DNO routine comprises: iteratively checking each die shape in a first list of die shapes to determine which ones of the die shapes have a maximum number of dies (N max ) for the target die area (A target ), and generating an initial result list of die shapes that have the maximum number of dies (N max ) for the target die area (A target ); executing a die size optimization (DSO) routine to determine (1) a list of die shapes having a maximum die area (A max ) corresponding to the maximum number of dies (N max ), (2) a first list of optimized die shapes that have a maximum area utilization (AU) for a decreased target die area (A target ), and (3) a second list of optimized die shapes that have a minimum area utilization (AU) for an increased target die area (A target ); outputting a candidate list comprising a plurality of entries including die shapes from the initial result list that have the maximum number of dies (N max ) for the target die area (A target ), die shapes from the list of die shapes having the maximum die area (A max ) corresponding to the maximum number of dies (N max ), the optimized die shapes from the first list of optimized die shapes, and the optimized die shapes from the second list of optimized die shapes; and selecting one of the entries from the candidate list that will result in the maximum number of dies (N max ) on the wafer.