Patent ID: 7080222

Claim:
A memory device comprising: a memory array; a first signal path via which a first set of signals communicating memory address, write data, and control information are input to the memory device and via which a second set of signals communicating read data information are output from the memory device; a second signal path via which a third set of signals communicating the memory address, the write data, and the control information are output from the memory device without communicating through the memory array and via which a fourth set of signals communicating the read data information are input to the memory device without communicating through the memory array; a logic circuit for controlling data storage and retrieval to and from the memory array, wherein the logic circuit comprises: means for communicating to the memory array the memory address information that is input to the memory device; means for communicating via the second signal path the memory address information that is input to the memory device; means for communicating via the second path the write data that is input to the memory device; means for selecting a source of write data for the memory array from between the write data that is input to the memory device and the read data information that is input to the memory device; means for selecting a source of read data information, which is output from the memory device, from between the memory array and the read data information that is input to the memory device; and means for outputting a write-enable control signal via the second path; the memory array and logic circuit both integrated within the memory device and the first and second signal paths comprising external interfaces on the memory device, and data bits representing the memory address information are directly communicated from the first signal path to the second signal path without communicating through the logic circuit; and a backup-address register specifying a range of memory addresses for which assertion of the write-enable control signal occurs.