Patent ID: 8298930

Claim:
A method of making a semiconductor structure, comprising: forming an upper level wiring layer composed of an electrical insulator material; forming a wire in the upper level wiring layer; forming a plurality of capping layers on the wire and the upper level wiring layer; forming a passivation layer on the plurality of capping layers; forming a first barrier layer metallurgy (BLM) layer on and contacting a bond pad in a chip, wherein the bond pad is formed in the passivation layer, over the wire, and extending through the plurality of capping layers toward the wire; forming a second BLM layer on and contacting the first BLM layer; forming a solder material on and contacting the second BLM layer, wherein the first and second BLM layers extend laterally outward relative to side edges of the solder material; removing portions of the second BLM layer such that the second BLM layer is aligned with the side edges of the solder material; patterning the first BLM layer, wherein the patterning forms an undercut beneath the solder material; forming a repair material in the undercut and on the solder material; removing the repair material from the solder material; and reflowing the solder material.