Patent ID: 8098110

Claim:
A phase locked loop (PLL) apparatus comprising: an oscillator configured to generate an oscillator signal; a variable capacitance device connected to the oscillator and having a tuning capacitance responsive to a tuning signal to alter a frequency of the oscillator signal; a selectable capacitance arrangement, comprising a plurality of selectable capacitance devices, connected to the oscillator and responsive to a plurality of corresponding control signals such that each selectable capacitance device has a first capacitance at a corresponding control signal first value and a second capacitance at a corresponding control signal second value; a capacitance controller configured to determine, using a lookup table, a desired capacitance to maintain a tuning signal voltage range, and select either the first capacitance or the second capacitance of at least one of the selectable capacitance devices by providing the corresponding control signal that has the control signal first value to select the first capacitance and having the control signal second value to select the second capacitance, such that the selectable capacitance arrangement provides the desired capacitance; and a voltage rate of change limiting device (VRCLD) configured to limit a rate of change in the voltage that is applied to a corresponding control input at each of the selectable capacitance devices, wherein the VRCLD comprises a charge pump and a filter.