Patent ID: 7656340

Claim:
A pipelined analog to digital converter circuit, the circuit comprising: a first comparator, wherein the first comparator is operable to compare an analog input to a first voltage reference upon assertion of the first clock; a second comparator, wherein the second comparator is operable to compare the analog input to a second voltage reference upon assertion of the second clock; a multiplexer tree, wherein the multiplexer tree includes at least a first tier multiplexer and a second tier multiplexer, wherein the first tier multiplexer receives an output of the first comparator and an output of the second comparator, wherein the second tier multiplexer receives an output derived from the first tier multiplexer, and wherein the second tier multiplexer provides an output bit; a bit enable set, wherein the bit enable set receives the output bit; and wherein the bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer.