Patent ID: 7864915

Claim:
A method for generating a digital representation of a number of elapsed cycles of an input signal, the method comprising: sampling a first D signal on a triggering event of the input signal to generate a first Q signal and a first complementary Q signal, the first complementary Q signal being coupled to the first D signal; sampling a second D signal on a triggering event of the first complementary Q signal to generate a second Q signal and a second complementary Q signal, the second complementary Q signal being coupled to the second D signal; sampling the first Q signal on a triggering event of a reference signal to generate a first bit of the digital representation of the number of elapsed cycles of the input signal; and sampling the second Q signal on a triggering event of a first delayed version of the reference signal to generate a second bit of the digital representation of the number of elapsed cycles of the input signal, wherein the input signal is an output signal of a digitally-controlled oscillator (DCO) in a digital phase-locked loop, the number of elapsed cycles representing the integer portion of an accumulated phase of the DCO output signal.