Patent ID: 6927494

Claim:
An integrated circuit, the improvement comprising an electrically conductive local interconnect formed according to the following method: depositing a first layer of conductive material on a substrate, wherein the first layer of conductive material has a relatively low bulk electrical resistance, patterning the first layer of conductive material to form a first conductive circuit layer on the substrate, the first conductive circuit layer having first conductive elements, depositing a first layer of insulating material on top of the first conductive circuit layer, patterning the first layer of insulating material to selectively expose local interconnection points on at least two of the first conductive elements in the first conductive circuit layer, wherein the local interconnection points are within a predetermined distance of each other, depositing a second layer of conductive material over the patterned first layer of insulating material, wherein the second layer of conductive material has a relatively high bulk electrical resistance, and patterning the second layer of conductive material to form the electrically conductive local interconnect between the at least two of the first conductive elements in the first conductive circuit layer, and to also form portions of macro elements, which macro elements are designed to function with relatively high bulk electrical resistance of the second layer of conductive material.