Patent ID: 6912598

Claim:
An electrically alterable semiconductor nonvolatile memory, comprising: first and second memory banks; an alteration control circuit coupled to the memory banks and structured to control alteration of information stored in the memory banks; a read control circuit coupled to the memory banks and structured to control reading of information stored in the memory banks; a first scanning circuit coupled to the first memory bank, the alteration control circuit, and the read control circuit and structured to select a plurality of memory locations in the first memory bank based on a received first address signal; a second scanning circuit coupled to the second memory bank, the alteration control circuit, and the read control circuit and structured to select a plurality of memory locations in the second memory bank based on a received second address signal; and a memory control circuit coupled to the alteration and read control circuits and structured to cause the read control circuit to read information in parallel from plural memory locations from one of the memory banks simultaneously with the alteration control circuit altering information stored in the other one of the memory banks.