Patent ID: 8044906

Claim:
A display device comprising: a pixel portion provided over a glass substrate; a gate line driving circuit provided over the glass substrate; and a signal line driving circuit, wherein the pixel portion includes a display element, wherein the gate line driving circuit outputs a selection signal to the pixel portion, wherein the signal line driving circuit outputs a video signal to the pixel portion, wherein the gate line driving circuit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a fifth thin film transistor which are n-channel type and include amorphous semiconductor, wherein a first signal is inputted into one of a source or drain of the first thin film transistor, wherein the one of the source or drain of the first thin film transistor is directly connected to a gate of the first thin film transistor, wherein the other of the source or drain of the first thin film transistor is directly connected to one of a source or drain of the second thin film transistor, wherein a second signal is inputted into a gate of the second thin film transistor, wherein the other of the source or drain of the second thin film transistor is directly connected to a first wiring, wherein a gate of the third thin film transistor is directly connected to the other of the source or drain of the first thin film transistor, wherein one of a source or drain of the third thin film transistor is directly connected to a second wiring, wherein the other of the source or drain of the third thin film transistor is directly connected to one of a source or drain of the fourth thin film transistor, wherein the other of the source or drain of the third thin film transistor is directly connected to a first output terminal, wherein a third signal is inputted into a gate of the fourth thin film transistor, wherein the other of the source or drain of the fourth thin film transistor is directly connected to the first wiring, wherein a gate of the fifth thin film transistor is directly connected to the gate of the third thin film transistor, wherein one of the source or drain of the fifth thin film transistor is directly connected to the second wiring, and wherein the other of the source or drain of the fifth thin film transistor is directly connected to a second output terminal.