Patent ID: 7941643

Claim:
An apparatus comprising: an execution block to execute instructions; a fetch block coupled to the execution block, the fetch block including at least a first program counter and a second program counter correspondingly allocatable to a first instruction execution thread and a second instruction execution thread, the fetch block to at least interleavingly fetch and issue instructions of the first instruction execution thread and the second instruction execution thread for execution by the execution block; and interrupt circuitry coupled to the fetch block, the interrupt circuitry to initiate an interrupt of behalf of the first instruction execution thread, wherein the fetch block is further configured to receive the interrupt for the first instruction execution thread while fetching and issuing instructions of the second instruction execution thread, fetch and issue, (i) in response to receiving the interrupt for the first instruction execution thread and (ii) prior to processing the received interrupt for the first instruction execution thread, at least one instruction of the first instruction execution thread to determine a point of execution of the first instruction execution thread, process the received interrupt for the first instruction execution thread subsequent to fetching and issuing the at least one instruction of the first instruction execution thread, and switch to fetch and issue instructions of the first instruction execution thread in response to processing the received interrupt.