Patent ID: 7370303

Claim:
A method for determining the arrangement of contact areas on an active top side of a semiconductor chip arranged in or on a housing, the method being performed on a computer system, comprising: reading semiconductor chip data into the computer system, the semiconductor chip data comprising geometrical properties of the semiconductor chip and information about a number of contact areas to be arranged at each edge of the semiconductor chip; reading contact area data into the computer system, the contact area data comprising geometrical and electrical properties of contact areas to be arranged on the active top side of the semiconductor chip; reading housing data into the computer system, the housing data comprising geometrical and electrical properties of the housing and also of contact pads arranged on a top side of the housing; reading production data into the computer system, the production data defining the arrangement of the semiconductor chip in relation to the housing; generating a model of an electronic device, which comprises the housing and the semiconductor chip arranged with its passive rear side on the top side of the housing, from the semiconductor chip data, contact area data, housing data and production data; arranging the contact areas in the model of the electronic device in edge regions on the active top side of the semiconductor chip wherein in the case of contact areas arranged at a respective semiconductor chip edge, distances of identical magnitude in each case are provided between adjacent contact areas and/or between the respective outermost contact areas per semiconductor chip edge and the adjoining semiconductor chip edges; and providing the contact area arrangement data for subsequent fabrication and/or design processes of the semiconductor chip and/or of the housing and/or of the electronic device.