Patent ID: 8614907

Claim:
A controller, comprising: a first external terminal configured to correspond to a system clock to which a semiconductor memory device receives, the system clock having a first frequency or a second frequency; a second external terminal configured to supply a command to the semiconductor memory device; a third external terminal configured to communicate a data with the semiconductor memory device; a fourth external terminal configured to transmit a data strobe signal having a preamble and a toggle transition following to the preamble, the preamble corresponding to a start timing of communicating the data and the toggle transition corresponding to communicating the data between the controller and the semiconductor memory device; and a fifth external terminal configured to be capable of outputting an information specifying a length of the preamble to the semiconductor memory device, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.