Patent ID: 7730290

Claim:
A load/store unit, comprising: pipeline logic configured to implement an instruction execution pipeline comprising a plurality of ordered stages carried out in sequence; a load miss queue comprising a plurality of entries for storing load instructions and corresponding addresses; a comparator coupled to receive a first address portion and a second address portion, wherein the first address portion comprises a portion of an address of a first load instruction in a particular stage of the execution pipeline, and wherein the second address portion comprises a portion of an address of a second load instruction, the comparator being configured to produce an output signal indicative of whether the first address portion is equal to the second address portion; logic coupled to receive the output signal of the comparator and configured to produce a match signal dependent upon the output signal of the comparator; and control logic coupled to receive the match signal and a hit signal indicative of whether the first load instruction specifies needed data found in the cache memory, and configured to ignore the hit signal dependent upon the match signal, thereby causing the first load instruction to be stored in the load miss queue.