Patent ID: 6894340

Claim:
A process for fabricating a non-volatile memory cell, comprising: forming a source region and a drain region on a semiconductor substrate; forming a charge trapping layer at least partially between said source and drain regions for trapping and retaining charge in a trapping region of said charge trapping layer and between said drain and source regions; forming a gate on at least a portion of said charge trapping layer, said gate having an edge discharge portion being horizontally offset from one of said source and drain regions for inducing said charge with said one of said source and drain regions; forming a first spacer on a first sidewall of said gate extending from said first sidewall of said gate toward one of said source and drain regions, said first spacer overlying a portion of said charge trapping layer; and forming a second spacer on a second sidewall of said gate extending from said second sidewall of said gate toward the other one of said source and drain regions, said first and second spacers and said gate extending between said source and drain regions.