Patent ID: 8637366

Claim:
A method for forming a memory cell, the method comprising: forming a first elongate conductor having a top layer; forming a vertical polycrystalline or amorphous pillar, the pillar consisting essentially of semiconductor material and comprising a bottom heavily doped region of a first conductivity type, a center lightly doped or intrinsic region disposed on the bottom heavily doped region, and a top heavily doped region of a second conductivity type disposed on the center lightly doped or intrinsic region, the pillar formed over and in electrical contact with the first conductor; and forming a second conductor over the pillar, the second conductor having a bottom layer, wherein the pillar is in electrical contact with the second conductor, wherein: the top layer of the first elongate conductor does not comprise semiconductor material, the bottom layer of the second conductor does not comprise semiconductor material, the memory cell does not include a dielectric rupture antifuse, the pillar comprises a silicon-germanium alloy, and the bottom heavily doped region and the top heavily doped region have a higher ratio of silicon to germanium than does the center lightly doped or intrinsic region.