Patent ID: 7750411

Claim:
A semiconductor integrated circuit device, comprising: a semiconductor substrate; an N-channel low-voltage MOS transistor disposed on the semiconductor substrate having a first gate insulating film, a first gate electrode, and a first source/drain region formed of a first N-type high impurity concentration region and a first N-type low impurity concentration region for alleviating an electric field intensity, wherein the first N-type high impurity concentration region has an impurity concentration higher than that of the thirst N-type low impurity concentration region; and an N-channel high-voltage MOS transistor disposed on the semiconductor substrate having a second gate insulating film, a second gate electrode, a second source/drain region formed of a second N-type high impurity concentration region and a second N-type low impurity concentration region for alleviating an electric field intensity, and an insulating film formed on the second low impurity concentration region, the insulating film being thicker than the second gate insulating film, wherein the second N-type high impurity concentration region has an impurity concentration higher than that of the second N-type low impurity concentration region, wherein the first N-type high impurity concentration region is doped with a first impurity and the second N-type high impurity concentration region is doped with a second impurity whose diffusion coefficient is larger than that of the first impurity wherein in the N-channel high-voltage MOS transistor, the second N-type high impurity concentration region and the second N-type low impurity concentration region at least partially overlap with each other at a depth deeper than the thick insulating film.