Patent ID: 8120887

Claim:
A transient voltage suppressing (TVS) circuit comprising: a triggering MOS transistor connected between an emitter and a collector of a first bipolar-junction transistor (BJT) coupled in parallel to a second BJT to function as a main clamp circuit of said TVS circuit; said triggering MOS transistor is formed in a semiconductor substrate of a first conductivity with a source and drain region of a second conductivity type disposed immediately below a top surface of said semiconductor substrate on two opposite sides of a lateral gate on the top surface of said semiconductor substrate within a doped well of the first conductivity type; and a first doped connection region of said second conductivity type extended downwardly from said source region encompassed in and extended through said well of said first conductivity type to a lower portion above a bottom surface of said substrate of said first conductivity constituting a doped connection to an emitter of said first BJT connected in parallel to said triggering MOS transistor.