Patent ID: 6891752

Claim:
A method for controlling gate voltage during an erase of a flash memory device comprising a plurality of memory sectors, the method comprising: a) selecting a portion of said plurality of memory sectors ( 810 ); b) selecting an unerased subset of said portion of said plurality of memory sectors ( 815 ); c) applying an erase pulse having a gate erase voltage to the subset of memory sectors ( 820 ); d) selecting a memory sector from the subset and erase verifying the selected sector ( 825 ); e) if the selected sector is not erased, applying a monotonically increasing function to said gate erase voltage ( 830 ); f) repeating c) through e) until said subset of memory sectors is erased; g) repeating steps b) through f) until said portion of said plurality of memory sectors is erased; h) resetting said gate erase voltage ( 840 ); and: i) repeating steps a) through h) until said plurality of memory sectors is erased ( 850 ).