Patent ID: 7545192

Claim:
A clock stop detector for a memory for detecting a clock signal being not active for a predetermined period of time, the clock stop detector comprising: a clock signal input; an inverted clock signal input; a first switch that is electrically coupled to the inverted clock signal input and closes in response to a first logic level of an inverted clock signal to charge a capacitor; a second switch that is electrically coupled to the inverted clock signal input and closes in response to a second logic level of the inverted clock signal to discharge the capacitor; and a logic circuit having a first input that is directly electrically coupled to the clock signal input and receives the clock signal and a second input that is electrically coupled to the capacitor and receives a charge signal based on a charge on the capacitor, and an output that outputs a control signal indicating when clock signal was not active for a period of time exceeding the predetermined period of time, wherein the capacitor is charged to the second logic level when the inverted clock signal is at the first logic level, and wherein the capacitor is discharged to the first logic level when the inverted clock signal is at the second logic level for a period of time exceeding the predetermined period of time.