Patent ID: 7257797

Claim:
A method of routing at least two interconnects of an integrated circuit comprising: identifying a first set of at least two pins to couple; calculating a route area, the route area extending a distance in a first direction to comprise positions in the first direction of the at least two pins; routing a first spine interconnect extending in the first direction at least a length from a first pin to a second pin in the first direction; determining a position in a second direction, orthogonal to the first direction, for the first spine interconnect to reduce an average length of the plurality of stitching interconnects; routing a plurality of stitching interconnects in the second direction to couple the first pin and second pin to the first spine interconnect, wherein a position in the second direction of the first spine interconnect is based on a weighted average of positions in the second direction of the first set of at least two pins; identifying a second set of at least two pins to couple, wherein the second set comprises at least a third pin and a fourth pin; in the route area, routing a second spine interconnect extending in the first direction at least a length from the third pin to the fourth pin the first direction; determining a position in a second direction, orthogonal to the first direction, for the second spine interconnect to reduce an average length of the plurality of stitching interconnects; routing a plurality of stitching interconnects in the second direction to couple the third pin and fourth pin to the second spine interconnect, wherein a position in the second direction of the second spine interconnect is based on a weighted average of positions in the second direction of the second set of at least two pins; placing a first shield on a first side of the first spine interconnect; and placing a second shield interconnect adjacent to the first spine interconnect, between the first spine interconnect and the second spine interconnect.