Patent ID: 7316968

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a stacked structure comprising a first semiconductor layer on a substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer and a fourth semiconductor layer on the third semiconductor layer; forming a hard mask pattern on a portion of the fourth semiconductor layer; partially etching the first, second, third and fourth semiconductor layers; trimming the etched first, second, third and fourth semiconductor layers to form an active pattern having a front side, a first sidewall, a second sidewall, a rear side and a top surface, wherein the active pattern extends above an upper surface of the substrate and wherein the first and second sidewalls are substantially vertical; growing a semiconductor layer on the first and second sidewalls of the active pattern to form a pair of source/drain regions; selectively etching portions of the first and third semiconductor layers to form a pair of tunnels in the active pattern that each extend from the front side of the active pattern to the rear side of the active pattern; and forming a conductive gate on the top surface of the active pattern and in the tunnels; wherein trimming the etched first, second, third and fourth semiconductor layers comprises trimming the etched first, second, third and fourth semiconductor layers to have a width that is less than the width of a lower surface of the hard mask pattern.