Patent ID: 7192864

Claim:
A method of fabricating interconnection lines for a semiconductor device, comprising: forming a conductive layer on a semiconductor substrate; forming an etch stop layer on the conductive layer; forming an interlayer insulating layer on the etch stop layer; forming a via hole through the interlayer insulating layer to expose the etch stop layer; forming a via filling material on the interlayer insulating layer to fill the via hole; forming a photoresist pattern on the via filling material; anisotropically etching the via filling material and the interlayer insulating layer using the photoresist pattern as an etch mask to form a trench connected to the via hole; removing the photoresist pattern using an ashing process, wherein the ashing process converts a surface portion of the via filling material to a carbon depletion region; performing a first wet etch process using a first wet etch solution to remove the carbon depletion region; performing a second wet etch process using a solution of dimethyl acetamide, different from the first wet etch solution to remove a residual portion of the via filling material filling the via hole; and forming a conductive layer pattern to fill the via hole and the trench with a conductive material.