Patent ID: 7687360

Claim:
A method for fabricating a semiconductor memory device, the method comprising the steps of: fabricating a plurality of spaced-apart charge-trapping stacks overlying a silicon substrate; forming a plurality of bit line regions in the silicon substrate between the spaced-apart charge-trapping stacks; fabricating a plurality of insulating elements overlying the exposed bit line regions and between the spaced-apart charge-trapping stacks; etching a portion of each of the plurality of spaced-apart charge trapping stacks to form two complementary charge storage nodes from each of the charge trapping stacks and to expose a portion of the silicon substrate between the two complementary charge storage nodes; growing silicon on the exposed portions of the silicon substrate by a process of selective epitaxial growth; oxidizing at least a portion of the epitaxially grown silicon, and at least a portion of the silicon substrate underlying the epitaxially grown silicon; and fabricating a control gate layer overlying the complementary charge storage nodes and the oxidized epitaxially grown silicon.