Patent ID: 8051228

Claim:
A processor, comprising: a plurality of input/output interface controllers; a plurality of processing cores; and a plurality of physical interface macros, wherein each of the plurality of physical interface macros supports heterogeneous electrical properties to provide one of a plurality of input/output interface controllers, wherein each of the plurality of physical interface macros comprises a mode signal to select an input/output interface controller from the plurality of input/output interface controllers; and wherein each of the plurality of physical interface macros comprises: a universal receiver physical interface macro, wherein the universal receiver physical interface macro comprises: a termination box that receives a differential signal from chip input/output pins; a preamplifier that receives a differential output signal from the termination box; a sampler flip-flop that receives a differential output signal from the preamplifier; a first-in-first-out buffer that receives an output signal from the sampler flip-flop and provides a variable programmable width output based on a speed of a respective selected input/output interface controller to a controller input/output interface; and a clock generator that provides a clock signal to the sampler flip-flop and provides a divided clock signal to the first-in-first-out buffer.