Patent ID: 8886897

Claim:
A memory system comprising: a first chip including a NAND type flash memory and a second chip including a NOR type flash memory; a controller configured to output controller output signals to access the chips; a memory controller configured to convert the controller output signals into memory input signals according to operation specifications for accessing the respective chips, and configured to convert memory output signals output from the chips into controller input signals receivable to the controller; and a common bus configured to connect the first chip, the second chip and the memory controller to transmit the memory input signals and the memory output signals corresponding to a data signal and a control signal, wherein the memory controller includes: an operation memory unit configured to store the operation specifications of the memories, an input/output controlling unit configure to input the controller output signals from the controller and configured to output the controller input signals to the controller, and configured to input the memory output signals from the chips and configured to output the memory input signals to the chips, a conversion control unit configured to operate the input/output controlling unit in accordance with information from the operation storing unit, and a signal holding unit configured to hold the memory output signals output from the chips, and temporarily configured to hold the controller output signals for operating one of the chips during the controller operation of another one of the chips, in which the conversion control unit instructs the signal holding unit to temporarily hold the memory output signals from the chips when the controller is busy, and instructs the signal holding unit to output the memory output signals held in the signal holding unit to the controller when the controller is ready.