Patent ID: 8106423

Claim:
A partially completed semiconductor integrated circuit device comprising: a semiconductor substrate; a dielectric layer overlying the semiconductor substrate; a gate structure including edges; a substantially pure silicon dioxide mask structure overlying a top surface region of the gate structure, the substantially pure silicon dioxide mask structure having an etching selectivity to silicon of greater than 1:30; a thickness ranging from about 400 Angstroms to about 600 Angstroms of the substantially pure silicon dioxide mask structure; a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the edges of the gate structure; a silicon germanium fill material in an etched source region and an etched drain region, the etched source region and the etched drain region being coupled to the gate structure; and a strained channel region between a filled source region and a filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region.