Patent ID: 7821814

Claim:
A semiconductor integrated circuit device comprising: first and second bit lines; a memory array including a plurality of memory cells each of the plurality of memory cells having a first driver MOSFET having a source coupled to a first node, a drain coupled to a second node, and a gate coupled to a third node, a first load MOSFET having a source coupled to a fourth node, a drain coupled to the second node, and a gate coupled to the third node, a second driver MOSFET having a source coupled to the first node, a drain coupled to the third node, and a gate coupled to the second node, a second load MOSFET having a source coupled to the fourth node, a drain coupled to the third node, and a gate coupled to the second node, a first transfer MOSFET having a source/drain path coupled between the first bit line and the second node, and a second transfer MOSFET having a source/drain path coupled between the second bit line and the third node; first switch MOSFETs having a source coupled to a first voltage and a drain coupled to the sources of the first and second driver MOSFETS of the plurality of memory cells and a gate coupled to a control signal; a first area in which the first driver MOSFETs and the first transfer MOSFETs are formed in a column and the second driver MOSFETs and the second transfer MOSFETs are formed in the column; and a second area, in which the first switch MOSFETs are formed, and which is adjacent to the first area, diffusion layers including the source or the drain of said first and second driver MOSFETs, said first and second transfer MOSFETs and said first switch MOSFET, and gates including gates of said first and second driver MOSFETs, said first and second transfer MOSFETs and said first switch MOSFET that are alternately formed and are continuously formed through the first and second areas, wherein each of the first driver MOSFETs, the first transfer MOSFETs, the second driver MOSFETs, and the second transfer MOSFETs is composed of the diffusion layers formed in the first area and the gates formed in the first area, and wherein each of the first switch MOSFETs is made up of the diffusion layers formed in the second area and the gate formed in the second area