Patent ID: 8331513

Claim:
A clock data restoration device which restores a clock signal and data on the basis of an inputted digital signal, comprising: an equalizer which adjusts the level of a high frequency component of the inputted digital signal and outputs the adjusted digital signal; a sampler which receives an input of a clock signal CK and a clock signal CKX which have a same cycle T, and an input of the digital signal outputted by said equalizer, and which samples, holds, and outputs a value D(n) of said digital signal at a time t C indicated by said clock signal CK, and samples, holds, and outputs a value DX(n) of said digital signal at a time t X indicated by said clock signal CKX, in each n-th period T(n) of the cycle; a clock generator which, in each period T(n), adjusts the cycle T or a phase on the basis of the value D(n) and the value DX(n) outputted by said sampler, in such a manner that a phase difference between said clock signal CK and said digital signal decreases, and outputs to said sampler said clock signal CK and said clock signal CKX satisfying a relationship t X −t C =T/2; and an equalizer controller which, in each period T(n), controls a level adjustment amount of the high frequency component of said digital signal by said equalizer, on the basis of the value D(n) and the value DX(n) outputted by said sampler; wherein t C <t X and n is an integer.