Patent ID: 8053347

Claim:
A method of manufacturing a semiconductor device, comprising: forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate conductive pattern; forming an insulating layer pattern between the gate structures at least partially exposing a top surface of the hard mask pattern; forming a trench that exposes at least a top surface of the gate conductive pattern by selectively removing the hard mask pattern; and forming a silicide layer on the exposed gate conductive pattern, wherein forming the insulating layer pattern includes: forming an insulating layer on the substrate including the gate structures; and at least partially exposing the top surface of the hard mask pattern by etching the insulating layer such that a portion of the insulating layer covering a first gate structure and a portion of the insulating later covering another gate structure adjacent to the first gate structure connect at a connecting point, and the connecting point is disposed at a position lower than the top surface of the hard mask pattern, and wherein the connecting point is disposed at a position higher than a bottom surface of the gate structures such that the insulating layer defines a void formed between the gate structures.