Patent ID: 7716616

Claim:
A computer-implemented method of improving a probability of an integrated circuit (IC) design meeting timing requirements, the method comprising the steps of: on a computer system including a processing unit, a) using a slack determinator stored in memory, determining a reference slack using a reference run, and using a sensitivity calculator, determining a sensitivity of slack to a variation in at least one parameter for each of a plurality of timing endpoints of the design; b) using a failure coefficient calculator stored in memory, calculating a failure coefficient from the reference slack and the sensitivity of slack for each of the timing endpoints; c) using a threshold tester stored in memory, determining whether each timing endpoint fails a threshold test; d) using a prioritizer stored in memory, prioritizing any timing endpoints that fail the threshold test according to respective failure coefficients; and e) using a modifier stored in memory, modifying the design to improve a slack of at least one of the timing endpoints.