Patent ID: 7915932

Claim:
A semiconductor integrated circuit comprising: a first signal delay circuit including a first discharge element having one end connected to a first node and configured to be switched between a conductive state and a nonconductive state by a first control signal to discharge the first node, a first precharge element connected between the first node and a power supply and configured to precharge the first node with a leakage current, and a first signal output circuit configured to compare a potential of the first node with a reference potential to output a first signal; a second signal delay circuit including a second discharge element having one end connected to a second node and configured to be switched between a conductive state and a nonconductive state by a second control signal to discharge the second node, a second precharge element connected between the second node and a power supply and configured to precharge the second node with a leakage current, and a second signal output circuit configured to compare a potential of the second node with a reference potential to output a second signal; a pulse signal generating circuit configured to generate a pulse signal having a pulse width determined by the first and second signals; a first delay circuit configured to delay the pulse signal to output the first control signal; and a second delay circuit configured to delay an inverted signal of the pulse signal to output the second control signal, the first signal delay circuit being configured to discharge the first node via the first discharge element, while the second signal delay circuit precharges the second node via the second precharge element and outputs the second signal; and the second signal delay circuit being configured to discharge the second node via the second discharge element, while the first signal delay circuit precharges the first node via the first precharge element and outputs the first signal.