Patent ID: 7580295

Claim:
A semiconductor memory device, comprising: a memory cell array comprising a plurality of first-type memory cells; an interface module receiving a second-type command signal, a second-type address signal, and a second-type data signal associated with a different semiconductor memory device comprising a plurality of second-type memory cells, and respectively converting the second-type command signal, the second-type address signal, and the second-type data signal into a first-type command signal, a first-type address signal, and a first-type data signal suitable for operating the memory cell array, wherein the interface module comprises a mode selector providing an interface mode signal corresponding to the second-type command signal; a command converter converting the second-type command signal into a first-type command signal comprising first through third control signals in response to the interface mode signal; an address-data demultiplexer selectively demultiplexing the second-type address signal and the second-type data signal in response to the first control signal; an address buffer converting the second-type address signal into the first-type address signal by buffering the second-type address signal in response to the second control signal; and a data buffer converting the second-type data signal into the first-type data signal by buffering the second-type data signal in response to the third control signal; and a write/read circuit module writing data to or reading data from the memory cell array using the first-type command signal, the first-type address signal, and the first-type data signal.