Patent ID: 7355578

Claim:
A semiconductor integrated device comprising a ROM decoder of n bits for selecting one gradation voltage out of gradation voltages of the n-th power of 2 gradation in connection with data signals of n bits (n represents an integer of 2 or more) representing a gradation level, said ROM decoder having n pairs of confronting gate wires each into which the data signal is input with the non-inverted state on one of the pair and with the inverted state on another of the pair, wherein pairs of the n-th power of 2 each of which comprises an enhancement type transistor and a depletion type transistor kept under ON-state are arranged at predetermined positions one side by one side at the pair of the confronting gate wires, and with respect to each of the pair of the confronting gate wires, the width of the gate wire that contains the upper portion of the depletion type transistor and extends from the depletion type transistor to the enhancement type transistor adjacent to the depletion type transistor is reduced with respect to the width of the gate wire than contains the upper portion of the adjacent enhancement type transistor so that recess portions are formed inside the confronting gate wires with the width of the gate wire that contains the upper portion of the depletion type transistor being narrower than the width of the gate wire than contains the upper portion of the adjacent enhancement type transistor.