Patent ID: 8327304

Claim:
A computer-implemented method of partitioning a circuit design for hardware-accelerated functional verification, comprising: a description of the circuit design which includes a plurality of nodes interconnected to form a plurality of nets, by executing first program instructions in a computer system; constructing a directed hypergraph with vertices representing the nodes and edges representing the nets, one of the vertices in each edge being a source, by executing second program instructions in the computer system; computing a slack for each edge based on the edge's source, by executing third program instructions in the computer system, wherein said computing includes determining an early rank of the edge's source by performing a forward topological traversal of the circuit design to the edge's source, determining a late rank of the edge's source by performing a backward topological traversal of the circuit design to the edge's source, and computing the slack as the difference of the early and late ranks; assigning each edge a weight which is a function of the edge's slack, by executing fourth program instructions in the computer system; partitioning the hypergraph to create a vertex partitionment which optimizes a total weighted cut of the edges using the edge weights, by executing fifth program instructions in the computer system; and mapping the vertex partitionment to a partitionment of the nodes, by executing sixth program instructions in the computer system.