Patent ID: 7526709

Claim:
A memory device integrated circuit, comprising: a plurality of banks of content addressable memory cells; and a plurality of refresh and error detection and correction circuits, each refresh and error detection and correction circuit being associated with and connected to a respective bank, each refresh and error detection and correction circuit being adapted to test memory cells in its associated bank for errors, detect errors within the cells and correct any detected errors during a refresh operation of the integrated circuit, wherein each refresh and error detection and correction circuit is adapted to correct multiple-bit errors in a memory cell detected as having a multiple-bit error, and each refresh and error detection and correction circuit comprises: a bank of shadow memory, the bank of shadow memory containing a copy of data stored within an associated bank of content addressable memory cells; an address generator adapted to generate a test address for a memory cell to be tested, the address generator being connected to the associated bank of content addressable memory cells; a state machine connected to the address generator, the state machine adapted to output a signal to the address generator when it is time to generate the test address; a first test circuit being connected to the shadow memory bank, the test circuit adapted to input a content of the shadow memory corresponding to the memory cell to be tested, determine whether the input content of the shadow memory contains an error, and output a first signal if it is determined that the input content of the shadow memory contains the error; a second test circuit being connected to the associated bank of content addressable memory cells, the second test circuit adapted to input a content of the associated bank corresponding to the memory cell to be tested, determine whether the input content of the associated bank of content addressable memory cells contains an error, and output a second signal if it is determined that the input content of the associated bank of content addressable memory cells contains the error; and a control circuit adapted to input the first and second signals and determine whether there is an error in the associated bank of content addressable memory cells and the shadow memory based on the first and second signals.