Patent ID: 8510702

Claim:
A computer-implemented method of defining the physical routing of interconnections in the layout of an integrated circuit, comprising the steps of: identifying a plurality of interconnections between nodes of first and second blocks in the integrated circuit layout as a first bus comprised of a plurality of wires; receiving drawing inputs from a user corresponding to physical routing of a representative wire in the first bus; displaying the physical routing of the representative wire at a graphics display of a computer system; storing, in a memory of the computer system, routing data comprising the location of each of one or more segments of the representative wire in the integrated circuit layout, and property data, for each segment, comprising a plurality of properties corresponding to the physical arrangement of the plurality of wires in the first bus; deriving routing data comprising the physical routing of one or more segments of each of a plurality of wires in the first bus in the integrated circuit layout, from the routing data and the associated property data of the representative wire; and then displaying, at the graphics display, the physical routing of the plurality of wires in the first bus.