Patent ID: 7120042

Claim:
A ferroelectric memory device, comprising: a first bit line; a second bit line; a plurality of first memory cells each of which is connected to the first bit line, wherein each of the first memory cells includes one transistor and one ferroelectric capacitor; a plurality of second memory cells each of which is connected to the second bit line, wherein each of the second memory cells includes one transistor and one ferroelectric capacitor; a plurality of word lines each of which is connected to a respective one of the first and second memory cells; a plurality of plate lines each of which is commonly connected to respective pairs of the first and second memory cells; a plurality of judgement memory cells each of which is connected between the first bit line and the second bit line, wherein each of the judgement memory cells includes two transistors and two ferroelectric capacitors; and a plurality of judgement word line pairs each of which is connected to a respective one of the judgement memory cells, and wherein the judgement word lines of a respective ijudgement word line pair are supplied with a common voltage level.