Patent ID: 8245084

Claim:
A computer-implemented method in a computer system for identifying a subset of a workload, which includes a plurality of dynamic instructions, to use as a trace, the computer-implemented method comprising: dividing the plurality of dynamic instructions into a plurality of intervals, all of the plurality of intervals including all of the plurality of dynamic instructions and each one of a plurality of different subsets including a different subset of the plurality of intervals; executing, on a processor unit hardware, the workload in real-time using a particular dataset, the processor unit hardware including at least one microprocessor and at least one cache; monitoring the real-time execution of the workload to obtain information about how the processor unit hardware executes the workload when the workload is being executed using the particular dataset to form actual performance information; determining a total number of cycles per instruction and a total cache miss rate for the workload after the processor unit hardware has finished executing the workload in real-time using the particular dataset; determining a number of cycles per instruction and a cache miss rate for each interval included in the different subset of the plurality of intervals; determining a weighted cycles per instruction error using the total number of cycles per instruction and the number of cycles per instruction for each interval included in the different subset of the plurality of intervals; determining a weighted cache miss rate error using the total cache miss rate and the cache miss rate for each interval included in the different subset of the plurality of intervals; determining a total error by adding together the weighted cycles per instruction and weighted cache miss rate for each interval included within each of the plurality of different subsets; and selecting one of the plurality of different subsets that has a smallest total error to use as the trace.