Patent ID: 8404533

Claim:
A method for fabricating a metal gate transistor, comprising: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer directly contacting the gate insulating layer, a polysilicon layer on the etching stop layer, and a hard mask on the polysilicon layer; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; forming a conductive layer in the opening for forming a gate.