Patent ID: 8145815

Claim:
A data processing system comprising: a plurality of bus master groups, each including at least one bus master having a priority level for carrying out a preassigned processing operation; a plurality of first buses, each being disposed in correspondence with each bus master group in an arrangement wherein information from each bus master group is fed via each first bus; a plurality of first bus controllers, each being disposed in correspondence with each first bus in an arrangement wherein, through arbitration of access requests from each bus master group corresponding thereto in accordance with priority level information, each first bus controller feeds a priority communication signal indicating a priority level of each access-request-permitted bus master; a second bus disposed in common to the first buses; and a second bus controller disposed in common to the first buses and in correspondence with the second bus in an arrangement wherein, through arbitration of the access requests from each first bus in accordance with each priority communication signal fed under control of each first bus controller, the second bus controller feeds a priority communication signal indicating a priority level of each access-request-permitted bus master to a subordinate hierarchical circuit via the second bus, and wherein the second bus controller feeds transfer information from the access-request-permitted bus master to the subordinate hierarchical circuit via the second bus.