Patent ID: 7432162

Claim:
A method for fabricating a semiconductor device comprising: (a) forming device isolation structures in a semiconductor substrate having a pad insulating film; (b) selectively etching the pad insulating film by a recess gate mask to expose the semiconductor substrate of a recess region; (c) forming spacer at a sidewall of the recess region; (d) etching a predetermined thickness of the semiconductor substrate exposed at the lower part of the recess region using the spacer as an etching mask to form a first recess; (e) removing the spacer to expose its underlying semiconductor substrate; (f) etching a predetermined thickness of the semiconductor substrate exposed at the step (e) to form a second recess, wherein a stepped recess channel region including vertical silicon-on-insulator (SOI) channel structures is formed at the lower part of the second recess, wherein the vertical SOI channel structures are formed at sidewalls of the device isolation structures in a longitudinal direction of a gate region; (g) removing the pad insulating film to expose the semiconductor substrate including the stepped recess channel region; (h) forming a gate insulating film over the semiconductor substrate exposed at the step (g); and (i) forming a gate structure over the gate insulating film of the gate region, wherein the gate structure includes a stacked structure of a gate electrode filling the stepped recess channel region and a gate hard mask layer pattern.