Patent ID: 7457180

Claim:
A memory array comprising a plurality of memory cells, each cell comprising: a first MOSFET having a single gate and a first voltage according to a first threshold voltage, the first MOSFET not having a floating gate; a second MOSFET having a single gate and a second voltage according to a second threshold voltage different than the first threshold voltage, the second MOSFET not having a floating gate; and an element for determining a voltage difference between the first voltage and the second voltage to establish a logic state stored in the memory cell in response to a difference in the threshold voltage of the first and the second MOSFETS, wherein the first and the second MOSFETS each further comprise a gate oxide underneath the associated single gate and overlying a silicon surface, and wherein interface-trapped charges comprising hydrogen are present at an interface between the gate oxide and the silicon surface of each of the first and the second MOSFETS, and wherein the difference between the first and the second threshold voltages is responsive to a difference in the interface-trapped charges comprising hydrogen.