Patent ID: 8036021

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged at intersections of bit line pairs and word lines, wherein each of said memory cells includes a transistor having one main electrode connected to one bit line of said bit line pair, said transistor being formed on a substrate, a node electrode for data-storage connected to the other main electrode of said transistor, said node electrode being formed above the transistor via an interlayer insulator, said interlayer insulator formed between multilayered wirings, a shield electrode with a closed loop shape surrounding said node electrode in a horizontal plane parallel to the substrate via said interlayer insulator, and a capacitor including said interlayer insulator between said node electrode and another electrode, said capacitor being configured to store data in said node electrode, wherein said transistor has a gate connected to said word line, wherein said bit line pair is connected to an identical sense amp, wherein said bit line pair, said word line, said node electrode and said shield electrode are electrically isolated from one another with the interlayer insulator interposed there between.