Patent ID: 7042875

Claim:
A switching system, comprising: a clock signal having a rising edge and a falling edge; 2 K data inputs and 2 K data select signals; K layers of switches, wherein each j th layer is configured to receive 2 K(j−1) data inputs and propagate 2 K−j of the 2 K−(j−1) data inputs, wherein each j th layer is further configured to receive 2 K−(j−1 ) data select signals and propagate 2 K−j of the 2 K(j−1) data select signals, wherein each layer comprises 2 K−j switches, wherein each of the 2 K−j switches comprises: a logical OR gate configured to receive at least two select signals and generate a data valid signal; a multiplexer (MUX) configured to receive at least two data input signals and one of the at least two select signals, the MUX further configured to generate a data output; a first flip flop configured to receive the data valid signal and release the data valid signal in response to the rising edge of the clock signal; and a second flip flop configured to receive the data output and release the data output in response to the rising edge of the clock signal.