Patent ID: 8121286

Claim:
A method comprising: configuring at least one processor to perform functions comprising: organizing a plurality of columns of input bytes; generating an initial matrix comprising a plurality of columns of bytes; mixing a first column of input bytes into the initial matrix to create an intermediate matrix; for each of the subsequent columns of input bytes; mixing the column of input bytes into the intermediate matrix; performing a first mixing operation on the intermediate matrix to produce a new intermediate matrix, wherein the first mixing operation acts in such a way that, in order for the first mixing operation to generate a predetermined combination of zero columns for the new intermediate matrix, a predetermined number of the columns of the intermediate matrix, as they existed before the first mixing operation, must be non-zero; using the new intermediate matrix as the intermediate matrix; upon mixing of all of the input columns into the intermediate matrix, performing a second mixing operation on the intermediate matrix; and selecting as an output a subset of columns of the intermediate matrix.