Patent ID: 8912854

Claim:
A circuit, comprising: a first node; a second node; an inductor coupled to the first node and the second node; a first capacitive network coupled to the first node and second node, wherein the first capacitive network is designed to allow the circuit to obtain an approximate target frequency of oscillation; a compensating capacitive network coupled to the first node and the second node, wherein the compensating capacitive network is designed to compensate for a change in frequency of oscillation of the circuit caused by a supply voltage dependence of the circuit; a second capacitive network coupled to the first node and the second node, wherein the second capacitive network allows the circuit to obtain a desired frequency of oscillation; a filter coupled to the second capacitive network, wherein the filter supplies a voltage to the second capacitive network; a transconductor coupled to the first node and the second node, wherein the transconductor is designed to compensate for a change in the frequency of oscillation in the circuit; and a sub-circuit coupled to the compensating capacitive network, wherein the sub-circuit generates and supplies voltage to the compensating capacitive network sufficient to allow the compensating capacitive network to compensate for a reduction in frequency of oscillation of the circuit, and wherein the sub-circuit includes at least one field-effect transistor gate-coupled to a node via another node, wherein the sub-circuit comprises: a first resistor coupled to a supply voltage; a second resistor coupled to the first resistor via a first node; a first field-effect transistor gate-coupled to the first node via a second node, wherein the first field-effect transistor is source-coupled to the supply voltage, and wherein the first field-effect transistor is drain-coupled to a third resistor via a third node; a second field-effect transistor gate-coupled to the third node via a fourth node, wherein the first field-effect transistor is source-coupled to the supply voltage, and wherein the second field-effect transistor is drain-coupled to a fourth resistor via a fifth node; a third field-effect transistor gate-coupled to the fifth node via a sixth node, wherein the third field-effect transistor is source-coupled to the supply voltage, and wherein the third field-effect transistor is drain-coupled to a fifth resistor via a seventh node; wherein the second resistor, third resistor, fourth resistor, and fifth resistor are ground coupled; and wherein the sub-circuit to the compensating capacitive network via an eighth node.