Patent ID: 8288278

Claim:
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having an active region, and an integrated circuit situated at part of the active region; forming at least one electrically conductive pad layer on the substrate; patterning each said electrically conductive pad layer to form a pad on the semiconductor substrate in a pad region and in at least a portion of a through electrode region, wherein the pad region encompasses the part of the active region where the integrated circuit is situated, and the patterning of each said at least one electrically conductive pad layer simultaneously forms a gap through the pad layer in the through electrode region, whereby the pad delimits an opening therethrough in the through electrode region; forming a hole in the semiconductor substrate under the opening extending through the pad in the through electrode region; forming a through electrode that fills the hole; and polishing the semiconductor substrate, at the back of the substrate, until a lower portion of the through electrode is exposed, whereby the through electrode passes through the substrate, wherein a plurality of the electrically conductive pad layers are formed one atop the other on the substrate, whereby the pad has a multi-layered structure.