Patent ID: 6897699

Claim:
A clock distribution network comprising: a. a clock source terminal adapted to receive a clock signal having a clock frequency and a clock period; b. a clock tree having: i. a root node connected to the clock source terminal; ii. a plurality of clock destination nodes; and iii. at least one dynamically adjustable clock buffer disposed between the root node and at least one of the plurality of destination nodes, the clock buffer including at least one buffer-control terminal; and c. a control circuit having: i. a control-circuit clock terminal coupled to the clock source terminal and adapted to receive the clock signal; and ii. a clock-adjustment port coupled to the buffer-control terminal and adapted to issue a buffer-control signal; d. wherein the dynamically adjustable clock buffer exhibits a delay responsive to the buffer-control signal; and e. wherein the control circuit varies the buffer-control signal to maintain the delay of the adjustable clock buffer in proportion to the clock period.