Patent ID: 7890233

Claim:
A microcontroller comprising: a first data processing unit operated in synchronization with a first clock signal; a circuit unit operated in synchronization with the first clock signal based on a control of the first data processing unit; a second data processing unit performing the same data processing as the first data processing unit in synchronization with a second clock signal having the same cycle and different phase from the first clock signal; a first interface circuit having a plurality of flip flops for holding a first signal outputted from the first data processing unit to the circuit unit; a comparator which compares a second signal outputted from the second data processing unit in response to an output of the first signal by the first data processing unit and the signal held in the first interface circuit in synchronization with the second clock signal; and a second interface circuit having a plurality of flip flops for holding a third signal supplied from the circuit unit to the first data processing unit and outputting the same to the second data processing unit, wherein the plurality of flip flops in the first and second interface circuits include those using the first clock signal for defining a latch timing and those using the second clock signal for the same.