Patent ID: 7484192

Claim:
A method, in a data processing system, for modeling metastability in an integrated circuit device simulation, comprising: identifying an asynchronous boundary in an integrated circuit device model; inserting at least one metastability decay latch element into the integrated circuit model within a range of elements of the asynchronous boundary, wherein the metastability decay latch models a decay of a metastable value of the latch when an indeterminate value is latched into the metastability decay latch; and simulating an operation of the integrated circuit device using the integrated circuit device model with the inserted at least one metastability decay latch, wherein inserting at least one metastability decay latch element into the integrated circuit model comprises: enumerating latch elements of the integrated circuit model along each path from the asynchronous boundary such that each latch element within the predetermined range has an associated enumerated depth value; identifying latch elements having an associated enumerated depth value that is less than or equal to a threshold depth value, thereby identifying candidate latch elements; and replacing the candidate latch elements with metastability decay latch elements.