Patent ID: 7632726

Claim:
A method for fabricating a field effect transistor device, said method comprising: providing a substrate; depositing a plurality of semiconductor device layers on the substrate; depositing a plurality of dielectric passivation layers on the semiconductor layers, wherein at least two of the passivation layers are made of a different dielectric material; depositing a source terminal on the semiconductor device layers; depositing a drain terminal on the semiconductor device layers; etching through at least one of the passivation layers to provide a gate terminal recess; and depositing a gate terminal within the gate terminal recess so that at least one of the passivation layers still remains between the gate terminal and the semiconductor device layers and so that the thickness of the passivation layers between the source terminal and the gate terminal and the drain terminal and the gate terminal is greater than the thickness of the one or more passivation layers between the gate terminal and the semiconductor device layers so that passivation layers are provided at sides of the gate terminal.