Patent ID: 8130871

Claim:
An integrated circuit comprising: a radio receiver module to receive a radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and to convert a selected one of the plurality of channel signals into an output signal; a channel selector module to produce a control signal; a programmable decimation filter, responsive to the control signal, to down-sample the output signal to produce a down-sampled digital signal at a frequency that is a non-integer multiple of a carrier frequency of the selected one of the plurality of channel signals; an interface clock generator, responsive to the control signal, to generate a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals wherein the first interface clock frequency, and integer multiples of the first interface clock frequency, are non-integer multiples of the carrier frequency of the selected one of the plurality of channel signals; and a driver module, operably coupled to the interface clock generator, to drive a device interface to couple a device to the radio receiver module based on the first interface clock; wherein the device interface is a bidirectional interface that is configured to exchange control data between the radio receiver module and the device.