Patent ID: 7903015

Claim:
A cascaded circuit for reducing noise, the cascaded circuit comprising: a first cascade circuit comprising: a first noise-shaping circuit; a first PCM-to-PWM converter; an first 1-bit P-tap AFIR filter DAC, where P is an integer value; wherein the first noise-shaping circuit shifts a portion of quantization noise in a PCM M-bit digital word from an in-band frequency range to an out-of-band frequency range; wherein a sampling frequency of the PCM M-bit digital word is Fs; wherein the first noise-shaping circuit converts the PCM M-bit digital word to a first PCM N-bit word, where M and N are integer values and M is greater than N; wherein a sampling frequency of the first PCM N-bit word is Fs; wherein the first PCM N-bit word is converted to a first PWM 1-bit word sampled at a frequency of (2 N )*Fs; wherein the first 1-bit P-tap AFIR filter DAC converts the first PWM 1-bit word to a first analog signal.