Patent ID: 6989566

Claim:
A high-breakdown-voltage semiconductor device, comprising: a semiconductor substrate whose conductivity is of a first type; a semiconductor region whose conductivity is of a second type, formed on the substrate; a doped contact region whose conductivity is of the second type, formed in the semiconductor region; a doped isolating region whose conductivity is of the first type, formed within the semiconductor region to be spaced apart from and surround the doped contact region; a field insulating film deposited over the semiconductor region located between the doped isolating and doped contact regions; a metal electrode electrically connected to the doped contact region; a plurality of plate electrodes electrically floating over the field insulating film, formed spaced apart from and, viewed normal to the substrate, surrounding the doped contact region; and an interlayer dielectric film formed over the field insulating film and the plurality of plate electrodes; wherein the metal electrode includes a plurality of sections, each of which serves as a loop-shaped metal electrodes, and a connection portion that connects each loop-shaped metal electrode to the doped contact region, while each of the plurality of plate electrodes is directly covered only by each associated loop-shaped metal electrode with the interlayer dielectric film interposed therebetween, and the loop-shaped metal electrode is capacitively coupled with the associated one of the plate electrodes, and a CMOS circuit, and either a resistor, a capacitor, or both, are provided in the second-conductivity-type semiconductor region surrounded by the second-conductivity-type doped contact region.