Patent ID: 8390118

Claim:
A semiconductor package having electrical connecting structures, comprising: a conductive layer having a die pad and a plurality of traces disposed at a periphery of the die pad, wherein the traces each comprise a trace body, a finger pad formed at an end of the trace body and positioned proximate to the die pad, and a trace end formed at another other end of the trace body and positioned distal to the die pad; a chip mounted on the die pad; a plurality of bonding wires for electrically connecting the chip and the finger pads; an encapsulant for encapsulating the chip and the bonding wires, wherein the encapsulant has a plurality of cavities for embedding the die pad and the traces of the conductive layer therein, the cavities being of a depth greater than a thickness of the conductive layer and allowing at least a portion of surfaces of the die pad and the traces of the conductive layer to be exposed therefrom; a solder mask layer formed on the at least a portion of surfaces of the die pad and traces of the conductive layer and a bottom surface of the encapsulant and having a plurality of openings formed therein for exposing the trace ends; and a plurality of solder balls formed in the openings of the solder mask layer so as to be electrically connected to the trace ends, respectively.