Patent ID: 8863064

Claim:
A computer-implemented method for designing an integrated circuit, comprising: obtaining design layout data for a base integrated circuit with at least one SRAM cell to be converted to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer; and performing, via a processor, the steps of: dividing NMOS active area patterns in the design layout into at least one enhanced body effect (EBE) NMOS active area layout with the NMOS active area patterns for the at least one SRAM cell and at least one non-EBE NMOS active layout with other ones of the NMOS active area patterns; dividing PMOS active area patterns in the design layout into at least one EBE PMOS active area layout with the PMOS active area patterns for the at least one SRAM cell and at least one non-EBE PMOS active layout with other ones of the PMOS active area patterns; adjusting a size of the NMOS active area patterns in the EBE NMOS active area layout to reduce a width of at least pull-down devices in the at least one SRAM cell; and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.