Patent ID: 8171258

Claim:
A processor comprising: an address generation unit coupled to receive operands of a memory operation and configured to generate a first sum corresponding to an index into a memory array, the address generation unit generating the first sum from bits of the operands that are in bit positions that correspond to the index and excluding other bits of the operands, and using an implicit carry-in to the least significant bit of the index of zero, and wherein the address generation unit is further configured to generate an actual carry-in; a decode block coupled to receive the first sum and the actual carry-in from the address generation unit, wherein the decode block is configured to generate a set of word lines for the memory array responsive to the first sum and the carry-in, wherein the decode block is configured to decode the first sum to generate an initial set of decoded signals, and wherein the decode block is further configured to select between the initial set and a second set of decoded signals comprising the initial set rotated by one position responsive to the actual carry-in.