Patent ID: 7776695

Claim:
A method for making a semiconductor device structure, comprising: forming on a substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; after said forming, then forming additional spacers on only the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure, including: disposing a first dielectric layer over the silicided first gate with first spacers, the silicided second gate with second spacers, silicided respective source and drain regions, and the isolation region, and covering the first dielectric layer disposed over the silicided first gate with first spacers, the silicided respective source and drain regions adjacent to the first gate, and a portion of the isolation region, and then removing the first dielectric layer from portions of the structure not covered by said covering step so that the silicide on the first gate is lower than portions of the first dielectric layer; and then disposing a stress layer over the entire intermediate structure.