Patent ID: 8021986

Claim:
A method for producing a transistor with metallic source and drain including at least the steps of: a) producing, on one face of a first dielectric material-based layer, at least one stack comprising at least one portion of at least one semiconductor material designed to form a channel of the transistor, a gate dielectric arranged against the portion of semiconductor material and a gate arranged against the gate dielectric, b) producing, on the face of the first dielectric material-based layer, at least two portions of a material capable of being selectively etched relative to at least one second dielectric material and arranged at the locations of the source and drain of the transistor, the volume of each of said two portions of material corresponding at least to the volume of the source or of the drain of the transistor, c) producing a second dielectric material-based layer covering at least the stack and said two portions of material, d) producing at least two holes in the second dielectric material-based layer, each hole forming an access to one of said two portions of material, e) etching said two portions of material, forming two cavities whereof the volumes correspond to the volumes of the source and of the drain of the transistor, f) depositing at least one metallic material in said two cavities, forming at least the metallic source and drain of the transistor, and also including, between steps a) and b), a step of depositing, on the stack, against the lateral sides of the stack and against the face of the first dielectric material-based layer, a layer composed of a material capable of forming a barrier to a diffusion of corrosive elements released during a metal deposition, said two portions of material being produced, during step b), against the layer composed of the material capable of forming a diffusion barrier.