Patent ID: 7134060

Claim:
A semiconductor integrated circuit, comprising: a phase control circuit to which a first clock signal is inputted, and which shifts a phase of the first clock signal based on a phase control signal and outputs the resultant signal as a second clock signal; a first flip-flop to which one of the first clock signal and the second clock signal is inputted as a first operation clock signal, and which operates in synchronization with an edge of the inputted first operation clock signal and outputs evaluation data; a circuit under test to which the evaluation data is inputted, and which performs a predetermined process based on the evaluation data and outputs a result of the process as output data; and a second flip-flop to which the other of the first clock signal and the second clock signal is inputted as a second operation clock signal and the output data is inputted, and which operates in synchronization with an edge of the inputted second operation clock signal and outputs the output data inputted from the circuit under test.