Patent ID: 7547946

Claim:
A semiconductor device comprising a plurality of first transistors and a plurality of second transistors; each of said plurality of first transistors including a first source/drain region, a second source/drain region located opposite to said first source/drain region across a first gate region, a third source/drain region located opposite to said second source/drain region across a second gate region and electrically connected to said first source/drain region, and a first gate electrode provided in each of said first and second gate regions; and each of said plurality of second transistors including said third source/drain region, a fourth source/drain region located opposite to said third source/drain region across a third gate region, a fifth source/drain region located opposite to said fourth source/drain region across a fourth gate region and electrically connected to said first and third source/drain regions, and a second gate electrode provided in each of said third and fourth gate regions, and means for controlling said second gate electrode independently of said first gate electrode; wherein said first and second transistors are alternately arranged; and said first source/drain region of said first transistor and said fifth source/drain region of said second transistor adjacent to said first transistor on the side of said first source/drain region are shared by said first and second transistors.