Patent ID: 8914620

Claim:
A computer-implemented method, comprising: attempting to execute a section of code as a transaction using a hardware transactional memory system; the hardware transactional memory system detecting that the transaction aborted or will abort; and in response to said detecting: the hardware transactional memory system sending an indication of said detecting to a software contention management mechanism, wherein the software contention management mechanism is configured to reduce transaction abort rates, and wherein to reduce transaction abort rates the software contention management mechanism is configured to: determine an amount by which to delay an attempt to execute a critical section of code, wherein the determined amount by which to delay the attempt to execute the critical section of code is configurable; or limit the number of threads permitted to elide a lock over a given critical section of code at any one time; in response to receiving the indication, the software contention management mechanism determining a mode of execution to be used in one or more subsequent attempts to execute the section of code, wherein determining the mode of execution comprises determining whether to use a speculative transaction mode supported by the hardware transactional memory system or a non-speculative mode supported by the hardware transactional memory system; the software contention management mechanism communicating the determined mode of execution to the hardware transactional memory system; and the hardware transactional memory system attempting to execute the section of code using the determined mode of execution.