Patent ID: 7285490

Claim:
A method for production of an integrated circuit arrangement comprising the following steps: forming a dielectric layer on an electrode layer including at least one electrode, wherein the dielectric layer has a thickness of less than 150 nm and is in contact with the at least one electrode; applying at least one hard mask layer to the dielectric layer, wherein the at least one hard mask layer is configured to define a contact or via; applying a resist layer to the hard mask layer; structuring the hard mask layer using the resist layer, wherein the dielectric layer is not completely structured, and wherein a contact hole or a via is not completely opened; removing residues of the resist layer; after removing the residues of the resist layer, completing the structuring of the dielectric layer using the hard mask layer, and completely opening the contact hole or the via and exposing the at least one electrode in the electrode layer; and removing the hard mask layer, wherein the hard mask layer comprises an electrically insulating layer.