Patent ID: 8484642

Claim:
An apparatus comprising: at least one first process to be executed, at least in part, by circuitry, the at least one first process to select, at least in part, from a plurality of processor cores, one or more processor cores to execute, at least in part, at least one second process, the at least one first process to select, at least in part, the one or more processor cores based at least in part upon whether at least one inter-dependency exists, at least in part, between the at least one second process and at least one third process also to be executed by the one or more processor cores, the at least one first process to assign, at least in part, the at least one second process to the one or more processor cores after at least one operating system process has assigned, at least in part, the at least one second process to at least one processor core in the plurality of processor cores; wherein: the plurality of processor cores comprise a plurality of processor core sets, each respective processor core set including one or more respective processor cores and being associated with a single respective central processing unit socket; the at least one first process is to determine, at least in part, one or more respective sets of processes that exhibit one or more respective inter-dependencies; the at least one first process is to assign the one or more respective sets of processes that exhibit the one or more respective inter-dependencies to one or more respective processor core sets for execution; the at least one first process is to assign the one or more respective sets of processes to the one or more respective processor core sets after the at least one operating system process has assigned, at least in part, the one or more respective sets of processes to the at least one processor core in the plurality of processor cores; and assignment by the at least one first process of the one or more respective sets of processes to the one or more respective processor core sets is based, at least in part, upon one or more of: respective loadings of the respective processor core sets; respective amounts of memory available to respective processor core sets; and one or more central processing unit socket affinities to be applied, at least in part, to the one or more respective sets of processes.