Patent ID: 7838343

Claim:
A metal oxide semiconductor power transistor fabrication method comprising the steps of: (a) forming a field oxide layer on a substrate; (b) defining a guard portion and an auxiliary structure in the field oxide layer by using a first mask, wherein the auxiliary structure having a plurality of spaces with a predetermined line-width being defined therein; (c) forming a gate oxide layer on the substrate; (d) forming a gate electrode layer on the gate oxide layer and covering the auxiliary structure; (e) forming a dielectric layer on the gate electrode layer; (f) defining a gate electrode and a contact window by using a second mask, wherein the contact window is located above the auxiliary structure; (g) removing the gate electrode layer and the dielectric layer through the second mask by etching, wherein a portion of the gate electrode layer is remained in the spaces defined in the auxiliary structure; (h) forming a plurality of well regions and a plurality of source/drain regions in the substrate; (i) forming a metal layer on the source/drain regions and the contact window; and (j) removing a portion of the metal layer to form a source/drain pad and a gate pad by using a third mask.