Patent ID: 8175205

Claim:
A semiconductor circuit device comprising: a reception circuit receiving a reception data signal and outputting a data signal; a flip-flop circuit receiving the data signal from the reception circuit in synchronization with a clock signal, and a clock data recovery circuit receiving the signal from the reception circuit and outputting the clock signal to the flip-flop circuit, said clock data recovery circuit including: a first detection portion detecting a phase difference between said data signal and said clock signal; a variable delay portion varying a delay of a clock in accordance with a control code; and a code changing portion changing a value of said control code, said code changing portion including: a second detection portion detecting a value of a control code corresponding to a delay equal to one period of said clock signal, a storage portion storing the value of the control code detected by said second detection portion, and an operation portion adding or subtracting at a time the value stored in said storage portion to or from the control code when a delay amount of said variable delay portion exceeds one period of the clock in synchronizing said clock signal with said data signal while changing said control code in accordance with a detection result by said first detection portion.