Patent ID: 8255644

Claim:
In a memory system comprising a plurality of hardware engines, the hardware engines coupled to (i) at least one unidirectional ring bus, and (ii) a plurality of addressable memory arrays, a method of accessing data in the arrays, the method comprising the steps of: sending, by a source one of the plurality of hardware engines, a task message over the at least one unidirectional ring bus to an adjacent hardware engine coupled to the ring bus, the task message having a corresponding one or more destination hardware engines; iteratively: checking, by the adjacent hardware engine, whether the hardware engine is a destination hardware engine for the task message and, if not, passing the task message unchanged to a next adjacent hardware engine coupled to the ring bus, thereby passing the task message from the source hardware engine to each corresponding destination engine on the ring bus; reading, from the received task message by the corresponding one or more destination hardware engines, a logical address of data in the addressable memory array to be accessed; computing, by the destination hardware engine, a hash value based on at least a part of the logical address; selecting one of the plurality of addressable memory arrays based on the hash value; and accessing the data in the selected addressable memory array using a physical address based on at least part of the logical address not used to compute the hash value.