Patent ID: 8321771

Claim:
A soft output Viterbi algorithm (SOVA) system for generating error events for decoded bits, the system comprising: an add-compare-select (ACS) circuit that determines a winning path through a trellis, generates decoded information based on the winning path, and computes path metric differences from the trellis based on the winning path; a trace-back circuit that generates a plurality of error event masks based on the decoded information and the path metric differences; an error event metric circuit that calculates an error event metric for each of the plurality of error event masks based on the path metric differences; a selection circuit that selects one or more error event masks based on the error event metrics of the plurality of error event masks; and an error event optimizer circuit that reduces a bit-length of the selected one or more error event masks and reduces a bit-length of the error event metrics of the selected one or more error event masks.