Patent ID: 7863136

Claim:
A method of manufacturing an integrated circuit including a field effect transistor, the method comprising: forming a fin of a semiconductor material, wherein the fin extends between a first and a second substrate portion which face each other on opposing first sides of the fin and wherein two first grooves face each other on opposing second sides of the fin; forming a first spacer structure encompassing a first portion of the fin, wherein the first portion directly adjoins to the first substrate portion; and forming a gate electrode adjacent to the first spacer structure and encompassing a further portion of the fin, wherein forming the fin comprises: forming a lamella of the semiconductor material and two insulator structures on opposing sides of the lamella, the lamella comprising the first substrate portion; forming a hard mask that covers the first substrate portion and an adjoining first portion of a central lamella portion; forming the first grooves in the insulator structures to expose sidewalls of a second portion of the central lamella portion using the hard mask as an etch mask; and etching isotropically the semiconductor material to form the fin from the central lamella portion, wherein divots are formed below the hard mask.