Patent ID: 7324421

Claim:
An apparatus for data bit align, comprising: a pipeline sample word aligner for a time frame alignment of a clock sample word with a time frame alignment of a data sample word; a multiplexer that receives the data sample word, the data sample word including a plurality of data bits, as data input and that receives the clock sample word from the pipeline sample word aligner, the clock sample word including a plurality of clock bits wherein a bit state of one of the plurality of clock bits represents a clock edge, as select input, wherein the multiplexer selects a data bit from the plurality of data bits in the data sample word based on a position of the clock edge in the clock sample word, the data sample word and the clock sample word are of same size and if the clock sample word includes the clock edge, the selected data bit is a bit in the data sample word corresponding to a bit representing the clock edge in the clock sample word, and if the clock sample word does not include the clock edge, the selected data bit is NULL.