Patent ID: 8525721

Claim:
A redundant signed digit (RSD) analog to digital converter (ADC) for receiving a high power supply voltage and a low power supply voltage, comprising: doubling means for receiving an input signal to be converted to a digital signal and doubling the input signal to provide a doubled input signal using an amplifier and a first capacitor, wherein the first capacitor has a capacitance of a first magnitude; a VR circuit for continued processing of the doubled input signal to provide a 2VR signal; and a Vref circuit that provides a first RSD residue signal that is equal to a sum of a reference Vref and the 2VR signal, wherein the reference Vref is defined as a voltage having a fixed value less than high power supply voltage and greater than half way between the low power supply voltage and the high power supply voltage, wherein the first RSD residue signal is produced using the amplifier, a second capacitor, and the high power supply voltage, wherein the second capacitor has a capacitance equal to half that of the first capacitor, and the Vref circuit further comprises a third capacitor, wherein the third capacitor has a capacitance equal to half that of the first capacitor and is used in producing the first RSD residue signal.