Patent ID: 8383490

Claim:
A method of forming a semiconductor structure comprising: forming a shallow trench isolation structure in a substrate, wherein said shallow trench isolation structure has a top surface that is recessed below a top surface of a top semiconductor layer of said substrate; forming a semiconductor device on said top semiconductor layer of said substrate; forming a dielectric material portion having a first planar top surface and including a first dielectric material on said top surface of said shallow trench isolation structure; forming a contiguous dielectric layer including a second dielectric material that is different from said first dielectric material on said dielectric material portion; planarizing said contiguous dielectric layer, wherein a second planar top surface extending over said first planar top surface and said semiconductor device is formed on said contiguous dielectric layer; forming a contact-level dielectric layer located over said contiguous dielectric layer; and forming at least one contact via structure through said contact-level dielectric layer and said contiguous dielectric layer and directly on a component of said semiconductor device located above said top surface of said top semiconductor layer.