Patent ID: 8094686

Claim:
A packet delay variation simulation system comprising: a packet generator configured to generate a plurality of signals indicative of packets; a packet delay variation generator configured to receive the signals from the packet generator and delay the signals; a packet delay analyzer configured to receive the delayed signals from the packet delay variation generator and signals from the packet generator and generate a profile of the delayed signals, thereby constructing a total delay model for a multi-switch network, wherein the packet delay variation generator comprises one or more packet delay distribution modules each comprising: a deterministic delay process packet delay input; and a statistical delay process packet delay input; wherein the one or more packet delay variation generators are configured to determine a packet delay distribution for the signals; a packet delay distribution compiler configured to determine a total packet delay variation based on the packet delay distributions determined at the one or more packet delay distribution modules; and a packet delay scheduler configured to receive the total packet delay variation from the packet delay distribution compiler and signals from the packet generator and determine a probability density function profile of the signals.