Patent ID: 8437175

Claim:
A method of operating a semiconductor memory that includes a plurality of memory cells, each memory cell coupled to a respective bit-line, the method comprising: reading a first memory cell of the memory, the reading comprising: selecting a first bit-line that is associated with the first memory cell, the selecting comprising activating a first switch thereby coupling the first bit-line to a first intermediate node; activating a second switch thereby coupling the first intermediate node to a second intermediate node; and coupling the second intermediate node to an input of a sense amplifier; writing to a second memory cell of the memory, the writing comprising: selecting a second bit-line that is associated with the second memory cell, the selecting comprising activating a fourth switch thereby coupling the second bit-line to the first intermediate node; coupling the second intermediate node to a reference voltage; coupling a write voltage to a third intermediate node, the third intermediate node being coupled to a third switch; when a first state is to be applied to the second bit-line, activating the second switch thereby coupling the reference voltage to the first intermediate node; and when a second state is to be applied to the second bit-line, activating the third switch thereby coupling the write voltage to the first intermediate node, wherein the write voltage is different from the reference voltage.