Patent ID: 7859320

Claim:
A level shifter for converting an input signal into an output signal, comprising: an input buffer coupled between a first voltage source and a ground source for receiving the input signal; an output buffer coupled to a second voltage source and the ground source for outputting the output signal; a level adjusting unit electrically coupled between the input buffer and the output buffer and coupled to the ground source and the second voltage source for shifting a voltage level of the input signal from the input buffer according to a voltage level of the second voltage source; an initial voltage generator electrically coupled to the level adjusting unit and coupled to the first voltage source and the second voltage source, the initial voltage generator being configured to provide an initial voltage for the level adjusting unit in response to activation of the second voltage source and non-activation of the first voltage source; and an isolation device electrically coupled to the input buffer and coupled to the first voltage source and the second voltage source, the isolation device being configured to block charges from the second voltage source from infusing into the input buffer in response to activation of the second voltage source and non-activation of the first voltage source; wherein the isolation device includes: a control voltage generator for generating a control voltage based on voltages originating from the second voltage source; and a switch element disposed between the second voltage source and the input buffer for optionally cutting off the electric connection between the second voltage source and the input buffer according to the control voltage; and wherein the control voltage generator includes: a first P-type transistor having a source and a gate thereof coupled to the second voltage source and the first voltage source, respectively; a first N-type transistor having a drain and a gate thereof coupled to the drain of the first P-type transistor, and a source thereof coupled to the control voltage; and a second N-type transistor having a source thereof coupled to the ground source, and a drain and a gate thereof respectively coupled to the source and of the first N-type transistor and the first voltage source.