Patent ID: 8693230

Claim:
A semiconductor device comprising: a plurality of core chips stacked to each other, each of the core chips including a memory cell array, a data terminal, and an output circuit that outputs read data that is read out from the memory cell array to the data terminal; and an interface chip that controls the core chips, wherein the data terminals of the core chips are commonly connected to each other so as to form a data path common to the core chips, the output circuits are activated in response to a first read clock signal supplied from the interface chip, and the interface chip receives the read data through the data path, wherein each of the data terminals includes a first penetration electrode that is provided through an associated one of the core chips, and the first penetration electrodes are arranged in the same planar position as viewed from a stacking direction and are short-circuited to each other, and wherein each of the core chips further includes an input circuit that latches the read data that is read out from the memory cell array, the output circuit outputs the read data latched by the input circuit to the first penetration electrode, and the input circuit latches the read data in response to a second read clock signal generated in the core chip.