Patent ID: 7880235

Claim:
A semiconductor integrated circuit device, comprising: an SOI substrate comprising an insulating film laminated on a semiconductor support substrate and a semiconductor thin film laminated on the insulating film; a first N-channel MOS transistor disposed on a surface of the semiconductor thin film; a first P-channel MOS transistor disposed on the surface of the semiconductor thin film, the first P-channel MOS transistor being isolated from the first N-channel MOS transistor by a field insulating film; a resistor formed on the field insulating film, the resistor and the semiconductor thin film being formed of single-crystal silicon; and a second N-channel MOS transistor serving as an electrostatic discharge (ESD) protection element disposed on a surface of the semiconductor support substrate that is exposed by removing a part of the semiconductor thin film and a part of the insulating film, the second N-channel MOS transistor having a gate electrode, a source region, a drain region surrounding the source region through the gate electrode to maintain a constant distance between the drain region and the source region, and an impurity diffusion layer disposed in an outer periphery of the drain region and spaced apart a preselected distance from the drain region.