Patent ID: 8255639

Claim:
A logically partitioned computer system comprising: a plurality of processors; a memory coupled to the plurality of processors having memory for a plurality of logical partitions designated by a hypervisor; a memory block with data in a first logical partition of virtual memory allocated to a memory chip; a memory error detection mechanism that determines a number of correctable errors above a predetermined threshold occur when accessing the memory block; a memory relocation mechanism incorporated into the hypervisor that transparently relocates the data of the memory block with correctable errors to a newly allocated memory block by moving the data of the memory block to an alternate physical memory location transparently to the first logical partition such that the first logical partition including an operating system on the first logical partition has no knowledge that a physical memory location of the memory block in the virtual memory has changed; and wherein the memory block is a logical memory block (LMB) of a dedicated memory logical partition and wherein the memory relocation mechanism places processors of the first logical partition having the memory block with correctable errors in a virtual partition memory (VPM) mode where the memory relocation mechanism has control of all memory storage through a page table.