Patent ID: 8667437

Claim:
A method of converting a programmable logic device (PLD) circuit design to a standard cell circuit design, the method comprising: unmapping a physically mapped PLD circuit design to a gate level netlist; wherein the unmapping comprises decomposing logic blocks of the circuit design into logic gates, a logic block comprises a single lookup table or a complex logic block, and a complex logic block comprises a plurality of programmable circuit elements of the PLD; annotating a group of the logic gates, into which at least one logic block has been decomposed, with a description of a particular function implemented by configuration of the programmable circuit elements of the at least one logic block; mapping, using a processor, logic gates of the netlist to functionally equivalent standard cells; wherein the mapping includes using the description of the particular function to map the group of logic gates of the at least one logic block to a suitable standard cell that implements the particular function; including the standard cells within the standard cell circuit design; automatically generating design constraints for the standard cell circuit design according to the PLD circuit design; and outputting the design constraints for the standard cell circuit design.