Patent ID: 7830696

Claim:
A ferroelectric semiconductor storage device comprising: a first block having odd numbers of ferroelectric memory cells connected in series, each of the odd numbers of ferroelectric memory cells including a first ferroelectric capacitor and a first transistor, a first drain/source terminal of the transistor being connected to one terminal of the first ferroelectric capacitor, and a second drain/source terminal of the first transistor being connected to the other terminal of the first ferroelectric capacitor; a second block having odd numbers of ferroelectric memory cells connected in series, each of the odd numbers of ferroelectric memory cells including a second ferroelectric capacitor and a second transistor, a first drain/source terminal of the second transistor being connected to one terminal of the second ferroelectric capacitor, and a second drain/source terminal of the second transistor being connected to the other terminal of the second ferroelectric capacitor; a plate line extending from a connection between one end of the first block and one end of the second block, each of the one ends connected to each other; a word line connected to each of the first and second transistors; a first selection transistor connected to the other end of the first block; a second selection transistor connected to the other end of the second block; and a bit line connected to each of the first selection transistor and the second selection transistor, the first block and the second block together form one block, and the number of the ferroelectric memory cells in the one block being power-of-two natural number.