Patent ID: 8683303

Claim:
An apparatus comprising: a check engine; and a bit engine configured to operate cooperatively with the check engine to perform a plurality of decoding iterations to decode an low density parity check (LDPC) coded signal to make at least one estimate of at least one information bit encoded therein such that the check engine to employ respective bit edge messages generated or updated by the bit engine and the bit engine to employ respective check edge messages generated or updated by the check engine, wherein: during a first subset of the plurality of decoding iterations, at least one of: the check engine configured to modify at least one of the respective bit edge messages based on a first at least one parameter modification to generate at least one modified bit edge message for use to generate or update at least one of the respective check edge messages; and the bit engine configured to modify at least one of the respective check edge messages based on a second at least one parameter modification to generate at least one modified check edge message for use to generate or update at least one of the respective bit edge messages; and during a second subset of the plurality of decoding iterations, at least one of: the check engine configured to modify at least one of the respective bit edge messages based on a third at least one parameter modification to generate at least one modified bit edge message for use to generate or update at least one of the respective check edge messages; and the bit engine configured to modify at least one of the respective check edge messages based on a fourth at least one parameter modification to generate at least one modified check edge message for use to generate or update at least one of the respective bit edge messages.