Patent ID: 6849890

Claim:
A semiconductor memory device comprising: a semiconductor substrate having a first conductivity type; a trench capacitor provided in the semiconductor substrate and having a charge accumulation region; a gate electrode provided on the semiconductor substrate via a gate insulating film; a gate side wall insulating film provided on a side surface of the gate electrode; drain and source regions provided in the semiconductor substrate and having a second conductivity type; an isolation insulating film provided adjacent to the trench capacitor in the semiconductor substrate to cover an upper surface of the charge accumulation region; a buried strap region having the second conductivity type, the buried strap region being provided to electrically connect an upper portion of the charge accumulation region to the source region in the semiconductor substrate; a first pocket implantation region having the first conductivity type, the first pocket implantation region being provided below the source region and being spaced apart from the strap region; and a second pocket implantation region having the first conductivity type, the second pocket implantation region being provided below the drain region.