Patent ID: 8062966

Claim:
A method of fabricating an integrated circuit, including PMOS and NMOS replacement gate structures in a semiconductor device, the method comprising: forming disposable gate structures over a gate dielectric in PMOS and NMOS regions of a semiconductor body; forming a BTBAS layer over the disposable gate structures; planarizing the BTBAS layer to expose a top portion of the disposable gate structures; removing the disposable gate structures in the NMOS region to expose the gate dielectric in the NMOS region; forming an NMOS metal capping layer over the gate dielectric in the NMOS region; forming an NMOS first metal layer over the NMOS metal capping layer in the NMOS region; forming a conductive first gap fill layer over the NMOS first metal layer in the NMOS region; removing the disposable gate structure in the PMOS region to expose the gate dielectric in the PMOS region; forming a PMOS second metal layer over the gate dielectric in the PMOS region; and forming a conductive second gap fill layer over the PMOS second metal layer in PMOS region.