Patent ID: 7902875

Claim:
A memory circuit, comprising: an output circuit comprising: a driver; and a pre-driver coupled to the driver and having a drive strength; and a slew rate controller configured to adjust the drive strength of the pre-driver, the slew rate controller comprising: a regulator, the regulator comprising a voltage regulator; a divider, the regulator and divider being configured to form part of a feedback loop, the divider comprising a voltage divider network, wherein the voltage divider network comprises: a transistor array, the transistor array comprising a parallel coupled array of series coupled select transistors and load transistors; a reference resistance; and a calibrator coupled between the regulator and the divider, the calibrator being configured to transmit control signals to the select transistors, the calibrator also coupled to the pre-driver, the calibrator is configured to receive an output voltage of the divider, wherein the output voltage is determined by a sum of channel currents of the transistor array and the output voltage is based on the states of the control signals received by the select transistors, the voltage regulator configured to transmit a reference voltage to the calibrator using a supply voltage, wherein the pre-driver comprises: a pull-up pre-driver coupled to the regulator; and a pull-down pre-driver coupled to the regulator, wherein the pull-up pre-driver comprises m p-channel select transistors, m n-channel select transistors, m p-channel load transistors and m n-channel load transistors coupled in a series configuration to form m inverter pairs coupled in parallel.