Patent ID: 8543964

Claim:
A method for optimizing connection constraints in an integrated circuit (IC) design, comprising: determining a target timing path associated with a first of a plurality of sub-connections of the integrated circuit, wherein the first of the plurality of sub-connections is associated with a current connection constraint set; determining a timing probability value associated with the first of the plurality of sub-connections based, at least in part, on the target timing path associated with the first of the plurality of sub-connections, wherein the timing probability value indicates a probability that timing closure is satisfied on the target timing path associated with the first of the plurality of sub-connections; determining a route probability value associated with the first of the plurality of sub-connections based, at least in part, on the target timing path associated with the first of the plurality of sub-connections, wherein the route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion; identifying a connection constraint model to which the first of the plurality of sub-connections corresponds based, at least in part, on the timing probability value associated with the first of the plurality of sub-connections and the route probability value associated with the first of the plurality of sub-connections; and modifying, by a processor, the current connection constraint associated with the first of the plurality of sub-connections in accordance with the connection constraint model to which the first of the plurality of sub-connections corresponds.