Patent ID: 8150946

Claim:
A system, comprising: a processor node comprising a processor and a network interface; a plurality of memory nodes, wherein each memory node comprises a memory and a network interface; a communication network configured to interconnect said processor node and said plurality of memory nodes via said network interfaces according to a network topology, wherein each of said memory nodes is removed from said processor node by a respective number of network hops according to said network topology; wherein said processor node is configured to: broadcast a packet comprising a memory request to a first subset of said plurality of memory nodes, wherein each memory node of said first subset of memory nodes is removed from said processor node by no more than a given number of network hops; determine whether one or more of said first subset of memory nodes has sent a reply to said processor node indicating that it can satisfy said memory request; and in response to determining that no memory node of said first subset of memory nodes has sent a reply to said processor node indicating that it can satisfy said memory request: increase said given number of network hops; and broadcast a packet comprising said memory request to a second subset of said plurality of memory nodes, wherein each memory node of said second subset of memory nodes is removed from said processor node by no more than said increased given number of network hops.