Patent ID: 7231510

Claim:
For use in a processor having an at least four-wide instruction issue architecture, a mechanism for pipeline processing multiply-accumulate instructions with out-of-order completion, comprising: instruction grouping logic implementing instruction grouping rules; a multiply-accumulate unit (MAC) having an initial multiply stage and a subsequent accumulate stage; and out-of-order completion logic, associated with said MAC, that causes interim results produced by said multiply stage to be stored when said accumulate stage is unavailable and allows younger instructions to complete before said multiply-accumulate instructions, said multiply-accumulate instructions being grouped based on said rules, wherein said rules comprise: a rule of never grouping an instruction that depends on a result of an older instruction, with the following exceptions: except wherein said instruction is a younger instruction and is a store or push operation, and wherein said older instruction is not a MAC instruction, or except wherein said younger instruction is a multiply accumulate operation and said older instruction updates said accumulate stage.