Patent ID: 7613062

Claim:
A semiconductor memory device comprising: a first data line and a second data line connected to each of a plurality of sense amplifiers; and a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory element and first and second selection transistors, wherein: the memory element includes a semiconductor element of metal oxide semiconductor (MOS) structure, and data is programmed when an insulating film is broken down by application of a voltage; the first selection transistor connects the memory element to the first data line in order to program data; the second selection transistor connects the memory element to the second data line in order to program data and sense the programmed data, the second selection transistor having a gate-electrode width that is smaller than that of the first selection transistor; and each of the memory cells further includes a first electric-field mitigating transistor connected between the memory element and the first and second selection transistors, a third selection transistor connected between the first selection transistor and the first data line, and a second electric-field mitigating transistor connected between the second selection transistor and the first electric-field mitigating transistor.