Patent ID: 7844654

Claim:
An arithmetic unit of arbitrary precision, comprising: a main processing unit splitting up first and second arbitrary-precision values into a number m of N-bit operands respectively in the-least-significant-bit-first order and consecutively outputting a series of a pair of first and second N-bit operands, wherein N is a natural number, wherein m is an integer greater than 0, wherein the first arbitrary-precision value is P-bits in length and the second arbitrary-precision value is Q-bits in length satisfying P<Q, wherein “0” is set to bits in higher order than a most significant bit (MSB) of the first arbitrary-precision value such that the lengths of the first and second arbitrary-precision values are equal, and wherein “0” is set to bits in higher order than a MSB in the mth N-bit operand of each respective arbitrary-precision value; and an N-bit arithmetic unit computing with the first and second N-bit operands fed from the main processing unit, while autonomously requesting, without clocking, the main processing unit to supply a next pair of the first and second N-bit operands each time the computation completes and autonomously feeding, without clocking, a carry generated by the computation to the next pair of the first and second N-bit operands until a null operator is provided to the N-bit arithmetic unit, the N-bit arithmetic unit including an asynchronous circuit driven by a handshaking scheme, and at least one of input/output signals being encoded by a dual-rail encoding scheme, and the at least one of input/output signals encoded by the dual-rail encoding scheme representing one of four operator values, wherein the four operator values consist of the null operator, an addition operator, a subtraction operator, and an inhibit operator.