Patent ID: 7202692

Claim:
A semiconductor chip comprising: a plurality of pads; a plurality of interface circuits connected with said plurality of pads, respectively, each of said plurality of interface circuits comprising a protection circuit connected to a respective one of said plurality of pads and an input circuit connected to said protection circuit; an internal circuit connected to the respective said input circuit of each of said plurality of interface circuits; and a transfer circuit connecting said plurality of interface circuits with each other in response to a test mode signal, said transfer circuit being connected to a first node between said protection circuit and said input circuit of a first one of said plurality of interface circuits and to a second node between said protection circuit and said input circuit of a second one of said plurality of interface circuits, wherein one of said plurality of pads is a selected pad when said pad is probed, and at least one remaining pad is a non-selected pad, one of said plurality of interface circuits corresponding to said selected pad is a selected interface circuit, and at least one remaining interface circuit is a non-selected interface circuit, and said internal circuit is tested by using said selected pad, said selected interface circuit, said transfer circuit, and said non-selected interface circuit without using said non-selected pad.