Patent ID: 8345468

Claim:
A capacity and density enhancing circuit for a sub-threshold memory cell, comprising: a first enhanced transistor, a second enhanced transistor, a first shielded transmission gate, a second shielded transmission gate, a first logical storage capacitor, and a second logical storage capacitor, wherein, a source end of the first enhanced transistor is connected with a source end of the second enhanced transistor and is connected to a supply voltage, a drain end of the first enhanced transistor is connected with an input/output end of the first shielded transmission gate and serves as one end of a bit line of a memory cell array, a drain end of the second enhanced transistor is connected with an input/output end of the second shielded transmission gate and serves as a NOT end of the bit line of the memory cell array, a body end of the first enhanced transistor is connected with a local grid end, a grid end of the first enhanced transistor is connected with one end of the first logical storage capacitor and is connected to the output/input end of the first shielded transmission gate, another end of the first logical storage capacitor is grounded, a body end of the second enhanced transistor is connected with the local grid end, a grid end of the second enhanced transistor is connected with one end of the second logical storage capacitor and connected to the output/input end of the second shielded transmission gate, another end of the second logical storage capacitor is grounded, a control end of the first shielded transmission gate and second shielded transmission gate is used for input of an enhanced control signal, a complementary control end of the first shielded transmission gate and second shielded transmission gate is used for a NOT input of the enhanced control signal.