Patent ID: 7203082

Claim:
A dual match line circuit, comprising: a hit match line coupled to a first plurality of load devices; a miss match line coupled to discharge through a second plurality of load devices, wherein each of said second plurality of load devices is activated for discharging by a respective miss signal; a positive feedback circuit coupled to said miss match line and configured to accelerate discharge of said miss match line in response to activation of one or more of said second plurality of load devices; and precharge logic configured to precharge each of said hit match line, said miss match line and an evaluate node to an asserted state; wherein said hit match line and said miss match line are coupled to said evaluate node via respective terminals of a coupling device; wherein said hit match line is additionally coupled to a discharge path that is activated for discharging by at least a hit signal; wherein said hit match line and said miss match line are electrically isolated from one another, such that when one or more of said respective miss signals are asserted, current from said hit match line does not discharge through said miss match line.