Patent ID: 7173464

Claim:
A duty adjustment circuit comprising: a frequency divider for dividing a frequency of an input clock signal by 2 n (where n is a natural number greater than 1) to provide a frequency-divided clock signal, the frequency divider having an input and an output; and n stages of frequency doublers connected to the output of the frequency divider, said n stages of frequency doublers being arranged in a cascade connection, for adjusting the frequency-divided clock signal to a clock signal having a same frequency as the input clock signal, with a duty ratio adjusted to a prescribed value, wherein each said frequency doubler includes: a variable delay portion, which delays an introduced signal from said frequency divider or said frequency doubler of a previous stage among said n stages, by an amount of time according to a control signal thereby providing a delayed signal; a frequency doubler portion, which calculates an exclusive logical sum of said introduced signal and the delayed signal to generate and output a frequency-doubled signal to said frequency doubler of a next stage among said n stages; an average value detection portion, which detects an average voltage of said frequency-doubled signal; and, a comparison control portion, which compares said average voltage with a reference voltage, adjusts said control signal such that the average voltage becomes equal to the reference voltage, and applies the adjusted control signal to said variable delay portion.