Patent ID: 8250337

Claim:
An array processor apparatus comprising: at least one opcode control element configured to generate a first opcode portion and a second opcode portion in accordance with a received opcode to obtain elements of a matrix to transmit a result to an owner resource; a plurality of multiplexers configured to selectively output data to a plurality of multipliers in response to the first opcode portion, the plurality of multipliers configured to operate on the data received from the plurality of multiplexers; a plurality of arithmetic logic units (ALUs) configured to operate on data received from the plurality of multipliers, the data being received in response to the second opcode portion, wherein the plurality of multiplexers, the plurality of multipliers and the plurality of ALUs form two parallel processing paths, each parallel processing path being configured to perform a set of matrix operations according to the opcode received by the at least one opcode control element, and wherein the second opcode portion includes a multi-bit sequence that controls whether the plurality of ALUs output a value corresponding to an idle operation or a value corresponding to one of a plurality of different multiply operations; and a register that outputs at least a third opcode portion of the received opcode to indicate whether or not the value output by the plurality of ALUs corresponds to a completed valid operation.