Patent ID: 7589708

Claim:
A method of driving a shift register that has r (r is a natural number equal to or larger than 3) stages, each of the r stages comprising first and second clocked inverters that each outputs a signal in sync with a clock pulse and an inverted clock pulse obtained by inverting a polarity of the clock pulse, wherein an output terminal of the first clocked inverter is connected to an output terminal of the second clocked inverter, wherein the second clocked inverter receives a signal obtained by inverting the polarity of an output signal of the first clocked inverter, wherein an amplitude voltage of the clock pulse and inverted clock pulse is smaller than a power supply voltage which is corresponding to the electric potential difference between a first power supply electric potential and a second power supply electric potential that are given to the first clocked inverter and second clocked inverter, the method comprising: in the j-th (j is a natural number equal to or larger than 2and equal to or smaller than r) stage, giving the first power supply electric potential of the first clocked inverter to the output terminal of the first clocked inverter through a first n-channel TFT and a second n-channel TFT connected in series to the first n-channel TFT; inputting a signal obtained by inverting the polarity of a signal outputted from the first clocked inverter of the (j−1)-th stage to a gate electrode of the first n-channel TFT, wherein, in the second stage, a gate electrode of the second n-channel TFT receives a signal which is obtained by inverting the polarity of a signal outputted from the first clocked inverter of the first stage and which is delayed, and in the k-th (k is a natural number equal to or larger than 3and equal to or smaller than r) stage, inputting a signal outputted from the first clocked inverter of the (k−2)-th stage to a gate electrode of the second n-channel TFT.