Patent ID: 7129562

Claim:
A layout architecture for an integrated circuit comprising: an array of standard cell logic cells formed at least partially in a substrate and occupying a first plurality of adjacent parallel tracks; a first metal layer; a second metal layer wherein the first metal layer is disposed between the second metal layer and the substrate; a plurality of first conductors extending across the logic cells on the second metal layer, each of said first conductors being coupled to a power supply, each conductor having a first side and a second side, wherein adjacent ones of the first conductors are coupled to different supply voltages; and a plurality of second conductors in the second metal layer, each within a logic cell, each not coupled to a power supply; wherein each of the plurality of second conductors occupies one track selected from the first plurality of adjacent parallel tracks and wherein irrespective of whether each of the plurality of first conductors occupies one track selected from the first plurality of adjacent parallel tracks or occupies a second plurality of mutually adjacent tracks selected from the first plurality of adjacent parallel tracks, none of the first and second plurality of conductor mutually contact.