Patent ID: 7461287

Claim:
A method of inter-chip communication comprising the steps of: launching a first clock signal from a first chip; launching a first data signal from the first chip, wherein the first data signal comprises a plurality of first data beats; launching a second data signal from the first chip, wherein the second data signal comprises a plurality of second data beats, wherein the plurality of first data beats are sent substantially concurrently with corresponding beats of the plurality of second data beats; receiving the first clock signal to result in a received first clock signal; receiving the first data signal to result in a received first data signal; receiving the second data signal to result in a received second data signal; delaying the received first data signal by less than a bit time by using at least a first variable delay line to align one or more of the centers of the plurality of first data beats with a first closest edge, wherein the first closest edge is related to an edge of the received first clock signal resulting in a delayed, received first signal; delaying the received second data signal by less than the bit time by using at least a second variable delay line to align one or more of the centers of the plurality of the second data beats with a second closest edge, wherein the second closest edge is related to another edge of the received first clock signal, wherein delaying the received second signal results in a delayed, received second signal; determining a first needed delay time for further delaying the delayed, received first data signal; and further delaying the delayed, received first data signal by the first needed delay time using latches.