Patent ID: 7447973

Claim:
A system for detecting and making a record of dynamic random access memory cells that are operational but prone to errors during refresh of the memory cells, the system comprising: an ECC generator coupled to receive write data and to generate respective ECC syndrome bits corresponding to the write data; an ECC checker coupled to receive read data along with corresponding stored ECC syndrome bits, the ECC checker being operable to detect if the read data are in error based on the ECC syndrome bits corresponding to the read data, the ECC checker being operable to output an error signal responsive to detecting a read data error; a failing address register; a memory control circuit coupled to receive the error signal from the ECC checker, the memory control circuit being operable to cause the storage in the failing address register of a row address corresponding to a row of memory cells from which the read data resulting in the read data error are being read; a refresh shadow counter that is operable to output a row address; a least one inverter coupled to receive at least one of bit of the row address from the refresh shadow counter, the at least one inverter being operable to invert the at least one bit of the row address from the refresh counter to provide at least one inverted bit; a failing address comparator coupled to the failing address register, the refresh shadow counter and the inverter to receive the row address from the refresh shadow counter and the at least one inverted bit, the failing address comparator being operable to substitute the at least one inverted bit for at least one corresponding bit in the row address from the refresh shadow counter to provide a comparison row address and to compare the comparison row address to the row addresses stored in the failing address register and to generate an indicating signal responsive to a predetermined relationship between the comparison row address and one of the row addresses stored in the failing address register; and a refresh circuit coupled to the failing address comparator operable responsive to the indicating signal to refresh a row of memory cells corresponding to the row address stored in the failing address register having the predetermined relationship with the comparison row address.