Patent ID: 8659949

Claim:
A three-dimensional (3D) memory structure, comprising: a plurality of stacked structures vertically formed on a substrate, each stacked structure comprising: a bottom gate, wherein the bottom gates of the stacked structures are electrically connected to each other; a plurality of gates and a plurality of gate insulators alternately stacked on the bottom gate; and two selection lines formed above the gates and spaced apart form each other, and the selection lines being independently controlled, wherein the gate insulator fills between the selection lines, between the gate and the selection lines and forms on top of the selection lines for insulation; a plurality of charge trapping multilayers, formed outsides of the stacked structures and extending to the bottom gates; a plurality of ultra-thin channels formed outsides of the charge trapping multilayers and lined between the adjacent stacked structures; and a dielectric layer, formed between the ultra-thin channels and between the stacked structures.