Patent ID: 8476728

Claim:
A parasitic PIN device in a BiCMOS process, formed on a P-type silicon substrate, an active region being isolated by shallow trench isolation oxide layers, wherein the parasitic PIN device comprises: an N-type region, comprising N-type pseudo buried layers formed at the bottom of the shallow trench isolation oxide layers and extending into the active region, the N-type region being picked up by forming contact holes in the shallow trench isolation oxide layers and filling the contact holes with metal; an I-type region, comprising an N-type collector implantation region formed in the active region, the N-type collector implantation region contacting with the N-type region that extends into the active region; a P-type region, comprising an intrinsic base epitaxial layer formed on a surface of the active region and an extrinsic base implantation region formed in the intrinsic base epitaxial layer by extrinsic base implantation, the P-type region contacting with the I-type region, wherein the P-type region is picked up by forming a metal contact thereon.