Patent ID: 8812822

Claim:
A design structure embodied in a non-transitory machine readable storage device for at least one of designing, manufacturing, and testing a design, the design structure comprising: an integrated circuit device comprising: a cascaded delayed execution pipeline unit having two or more execution pipelines that begin execution of instructions in a common issue group in a delayed manner relative to each other; circuitry configured to: receive an issue group of instructions; determine whether the issue group includes a load instruction; upon determining that the issue group includes a load instruction, schedule the load instruction to be executed in a first pipeline of the two or more execution pipelines, and schedule each remaining instruction in the issue group to be executed in remaining pipelines of the two or more pipelines, wherein execution of the load instruction in the first pipeline begins prior to beginning execution of the remaining instructions in the remaining pipelines; issue the issue group to the cascaded delayed execution pipeline unit; and upon determining that the load instruction results in a cache miss in a level one cache: request target data for the load instruction from a level two cache; and schedule the load instruction to be executed in a second pipeline of the two or more execution pipelines, and schedule each remaining instruction in the issue group to be executed in remaining pipelines of the two or more pipelines, wherein execution of the load instruction in the second pipeline begins after beginning execution of one or more remaining instructions in one or more remaining pipelines.