Patent ID: 8823064

Claim:
A FET device, comprising: a wafer; active areas formed in the wafer; gate stacks on the wafer present over one or more of the active areas, wherein the gate stacks have an irregular gate-to-gate spacing in that the gate-to-gate spacing between a given two of the gate stacks next to one another on the wafer is selectively configured to be greater than the gate-to-gate spacing of the gate stacks on the wafer to either side of the given two gate stacks, wherein by way of the irregular gate-to-gate spacing: i) for at least a given one of the active areas in which an asymmetrical transistor is present a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area, and ii) for at least another given one of the active areas in which a symmetrical transistor is present a gate-to-gate spacing on a source side of the other given active area is equal to a gate-to-gate spacing on a drain side of the other given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area, wherein the gate-to-gate spacing employed on the source side of the given active area is dependent on an angle of the angled implant in the source side of the given active area in that the gate-to-gate spacing on the source side of the given active area is chosen such that none of the gate stacks on the wafer shield the angled implant in the source side of the given active area, and wherein the gate stacks on the wafer all have a same height, and wherein a greater gate-to-gate spacing on the source side of the given active area is employed to permit a greater asymmetry of the angled implant in the source side of the given active area.