Patent ID: 7256722

Claim:
A D/A converter, comprising: M number of D/A converter sections in which 2 N − 1 current cells, each current cell outputs a current corresponding to 1 LSB of N-bit input data upon activation are allocated by substantially the same number of the current cells, the D/A converter outputting an added value of currents output from activated current cells in respective D/A converter sections or outputting a voltage obtained by subjecting to voltage conversion the added value of the currents; a reference current generating section for supplying each of the D/A converter sections with a reference current; and a decoder for activating at least one current cell in D/A converter section, from the first to M-th D/A converter sections in sequence in a cyclic manner when a value of the N-bit input data is increased, and deactivating at least one activated current cell in D/A converter section from the M-th to first D/A converter sections in sequence in a cyclic manner when the value of the N-bit input data is decreased, wherein a maximum value of the number of the current cells to be continuously activated or continuously deactivated in the respective D/A converter sections is limited to a number smaller than the number of all the current cells in the respective D/A converter sections.