Patent ID: 7100066

Claim:
A clock distribution device in a compact peripheral component interconnect (PCI) based multi-processing system comprising: a clock transmission device configured to transmit at least one clock between a first and second slot; and a clock driver configured to check whether the first slot is a system slot, the clock driver to generate a plurality of generated clocks, the clock driver to supply one of the generated clocks to the second slot, and to utilize one of the generated clocks for internal use if the first slot is the system slot, and the clock driver to block the generated clocks and to output a clock supplied from a system slot as a clock to be used internally if the first slot is not a system slots, wherein the clock driver comprises: a clock generator configured to generate a first clock signal, a clock distributor configured to distribute the first clock signal supplied from the clock generator into a plurality of second clock signals and output the plurality of second clock signals, a plurality of variable delay lines configured to delay and transmit the plurality of second clock signals though the plurality of variable delay lines of which a delay length may vary, a first buffer configured to switch at least one output of the plurality of second clocks to the second slot, a second buffer configured to store and output one of the plurality of second clock signals as a delay line for internal use, a multiplexer configured to select one of the plurality of second clock signals supplied from the second buffer and at least one clock supplied from an external system slot and the multiplexer to output the selected clock to be used internally within a multiplexer board, and a clock driver configuration logic configured to determine whether a clock driver board is mounted on a system board based upon an address signal and a slot enumeration signal of a higher-rank slot and the clock driver configuration logic to control operations of the variable delay lines, the first and second buffer, and the multiplexer.