Patent ID: 8423721

Claim:
A method of operating a data processing system, the method comprising: detecting bus transactions on a system interconnect of a data processing system, the data processing system including at least two masters; for each bus transaction detected on the system interconnect: performing a cache coherency operation for the bus transaction in response to determining that the bus transaction is a single beat write transaction from any master of the at least two masters, wherein the performing the cache coherency operation includes searching at least one cache of the data processing system to determine whether the at least one cache contains data associated with a memory address of the bus transaction; not performing cache coherency operations in any cache of the data processing system for the bus transaction in response to determining that the bus transaction is a read transaction; and not performing cache coherency operations in any cache of the data processing system for the bus transaction in response to determining that the bus transaction is a multiple beat write transaction from any master of the at least two masters.