Patent ID: 7634029

Claim:
A symbol timing recovery apparatus used with a Vestigial Side Band VSB)-type receiver, the apparatus comprising: an analog-to-digital converter (ADC) to receive a signal which is modulated by a vestigial side band (VSB) scheme and to digitalize the received signal using a predetermined sampling clock; a multiplier to transit the digitalized VSB signal to a baseband; a spectrum inverter to invert a spectrum by exchanging upper and lower frequency bands of the baseband VSB signal received from the multiplier; a lower band edge component maximization (BECM) to perform a BECM algorithm with respect to the inverted baseband VSB signal, thereby generating lower error information which is the information on the error between a symbol phase of the received VSB-modulated signal and a preset reference symbol phase; a loop filter to filter the lower error information of the lower BECM to output a lower band signal; and a numerically controlled oscillator (NCO) to change a predetermined sampling clock according to the lower band signal from the loop filter.