Patent ID: 7321961

Claim:
A system comprising: a memory; a memory controller with collision avoidance logic effective to: provide a new command load value that corresponds to a first activate command; and identify a command cycle to allow a second activate command based upon the new command load value, wherein the identified command cycle occurs only on an even command cycle relative to the first activate command at a point in time prior to the completion of a last column command corresponding to the first activate command; wherein the collision avoidance logic includes activate allowed logic that allows a second activate command during the identified command cycle, the identified command cycle occurring at the point in time prior to the completion of a last column command corresponding to the first activate command; and wherein the memory controller is further effective to issue a column command only on odd command cycles relative to the first activate command, wherein the even command cycles and the odd command cycles occur at points in time prior to the completion of the last column command corresponding to the first activate command.