Patent ID: 7339231

Claim:
A semiconductor device having a memory array in which a plurality of nonvolatile memory cells are arranged in a two-dimensional grid pattern, the memory array comprising: a first nonvolatile memory cell having a first charge storage layer, and a second nonvolatile memory cell having a second charge storage layer, said first and second nonvolatile memory cells being disposed adjacent to each other at symmetrical positions along a first direction; a source line electrically connected to a source of the first nonvolatile memory cell and a source of the second nonvolatile memory cell; a first bit line electrically connected to a drain of the first nonvolatile memory cell; a second bit line electrically connected to a drain of the second nonvolatile memory cell and having no direct electrical connection to the first bit line; a first gate of the first nonvolatile memory cell extending along a second direction perpendicular to the first direction; and a second gate of the second nonvolatile memory cell extending along the second direction.