Patent ID: 7442611

Claim:
A method of fabricating a semiconductor device structure, comprising: a) forming a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate; b) forming a first stressed film having a compressive stress over the PFET and the NFET; c) forming an intermediate layer overlying the first stressed film over the PFET but not overlying the NFET; d) applying a mask to cover the PFET while exposing the NFET; e) ion implanting a portion of the first stressed film overlying the NFET to form and implanted portion, the mask protecting another portion of the first stressed film overlying the PFET from the ion implantation; f) annealing the substrate, whereby the portion or the first stressed film protected by the mask during step (e) applies a compressive stress to the conduction channel of the PFET at a first magnitude and the magnitude of the stress applied to the conduction channel of the NFET by the implanted portion of the first stressed film is much reduced from the first magnitude—by; and g) forming a second stressed film overlying the intermediate layer over the PFET, the second stressed film overlying the implanted portion of the first stressed film over the NFET and the second stressed film applying a tensile stress to the conduction channel of the NFET.