Patent ID: 7671405

Claim:
A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising: forming two adjacent symmetric dual bit memory cells; each comprising a charge trapping dielectric layer configured to store two bits of data therein, and defining a first bitline opening there between wherein each of the memory cells are symmetrical about a centerline perpendicular to and passing through the charge trapping dielectric layer wherein two bits can be stored within the charge trapping dielectric layer with a bit stored on either side of the centerline approximately equidistant from each other; forming first polysilicon layer features over the charge trapping dielectric layer; performing a first bitline implant into the first bitline opening to establish a buried first bitline within the substrate; forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define a second bitline opening between the adjacent memory cells; performing a deep arsenic implant into the second bitline opening to establish a second bitline within the substrate that is smaller than the first bit line; and performing back end processing.