Patent ID: 8005881

Claim:
A rank order filter, comprising: a delay line coupled to receive pixel information; and a filter core coupled to receive at least a portion of the pixel information, the filter core including: a first stage of registers for registering data; the first stage of registers configured as a first shift register for shifting the data in the filter core; a comparator stage coupled to receive output from the first stage of registers and configured to compare a newly registered portion of the data registered in the first stage of registers with each previously registered portion of the data registered in the first stage of registers to provide comparison results; a second stage of registers coupled for receiving and configured for registering the comparison results; a third stage of registers coupled for receiving the comparison results; a first register portion of the third stage of registers configured to invert the comparison results, to register the comparison results inverted as first Most Significant Bits, and to include a first Least Significant Bit as a self-compare bit; the first register portion configured for providing a first output including the first Most Significant Bits and the first Least Significant Bit; a second register portion of the third stage of registers coupled to the first register portion of the third stage of registers as a shift register; the first register portion coupled to the second register portion to shift first Least Significant Bits of the first register portion into the second register portion as second Most Significant Bits; the first Least Significant Bits including the first Least Significant Bit; the second register portion coupled to receive a comparison result of the comparison results as a second Least Significant Bit to provide a second output; the second register portion configured for providing the second output including the second Most Significant Bits and the second Least Significant Bit; a conversion stage coupled to receive a rank value, the first output, and the second output; the conversion stage configured to bit sum each of the first output and the second output for respectively generating a first value and a second value; the conversion stage configured to compare each of the first value and the second value to the rank value for generating a one-hot result; the conversion stage configured to convert the one-hot result to an associated address; the address being associated with a portion of the data in the filter core associated with the one-hot result; and the delay line coupled to receive the address for accessing the pixel information associated with the one-hot result.