Patent ID: 7020033

Claim:
A semiconductor memory apparatus comprising a memory unit having unit blocks each including: a memory core including a plurality of memory cells laid out to form a cell matrix; and redundant lines including redundant memory cells each used for repairing an abnormal memory cell generated in any of said memory cores, wherein: said unit blocks are further laid out to form a block matrix or a plurality of block matrixes, and every plurality of said unit blocks forms a two-dimensional group oriented in a first direction (row or column direction) and a second direction (column or row direction); and said redundant lines are shared by said unit blocks pertaining to said two-dimensional group in both said first and second directions; self-test means mounted in the same chip as said memory unit to serve as embedded self-test means for evaluating said memory cells in order to determine whether said memory cells are good or defective; and self-repair means mounted in said same chip as said memory unit to serve as embedded self-repair means for: selecting only a minimum number of address pairs among address pairs received from said self-test means as address pairs each comprising a first-direction address (row or column address) and second-direction address (column or row address) of an abnormal memory cell; storing said selected minimum number of address pairs in storage means provided for each of said unit blocks as address pairs required for determining a redundant line to be used for repairing an abnormal memory cell; and finding a redundant line to be used for repairing an abnormal memory cell for each of said unit blocks pertaining to said two-dimensional group on the basis of address pairs stored in said storage means.