Patent ID: 8031541

Claim:
A read only memory comprising: a first transistor comprising a gate, a drain, and a source, the gate of the first transistor directly connected to a word line to provide a read signal, the drain of the first transistor directly connected to a main bit line through a second transistor, and the source of the first transistor is electrically grounded; the second transistor comprising a gate, a drain and a source, the gate of the second transistor is directly connected to a first decoding circuit, the drain of the second transistor is directly connected to the main bit line, and the source of the second transistor is directly connected to a power supply; a first reference bit line directly connected to a drain of a third transistor, wherein gate of the third transistor is directly connected to a second decoding circuit to generate a stop read signal; a second reference bit line directly connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal; and a reference word line directly connected to a gate of a fourth transistor.