Patent ID: 8872531

Claim:
A semiconductor device, comprising: a test pattern storage unit storing at least one pattern information; a command distributor configured to receive a serial command that is synchronized with a first clock signal and convert the serial command into a parallel command; a command decoder configured to receive the parallel command and generate a pattern sequence based on the parallel command, the command decoder configured to generate the pattern sequence by combining the parallel command and the at least one pattern information stored in the test pattern storage unit; and a signal generator configured to receive the pattern sequence and generate operating signals synchronized with a second clock signal, wherein the signal generator outputs the operating signals in parallel synchronized with the second clock signal and wherein a frequency of the first clock signal is less than a frequency of the second clock signal, and wherein the parallel command includes a request signal and a parameter signal, and the test pattern storage unit receives the request signal and transmits the pattern information corresponding to the request signal to the command decoder, and the command decoder includes a synthesis unit generating the pattern sequence by increasing or decreasing the parameter signal according to the pattern information, the parameter signal indicative of an address of a device under test to be tested.