Patent ID: 6856574

Claim:
A semiconductor memory device comprising: a memory-cell array comprising a plurality of memory cells laid out therein as memory cells each capable of storing data; a read circuit used in a data read operation to read out data from said memory-cell array; a write circuit used in a data write operation to write data into said memory-cell array; a read clock generation circuit for generating a read clock signal to be supplied to said read circuit in said data read operation to read out data from said memory-cell array; a write clock generation circuit for generating a write clock signal to be supplied to said write circuit in said data write operation to write data into said memory-cell array; a read pulse-width adjustment circuit provided in said read clock generation circuit for adjusting the pulse width of said read clock signal generated by said read clock generation circuit; and a write pulse-width adjustment circuit provided in said write clock generation circuit for adjusting the pulse width of said write clock signal generated by said write clock generation circuit, wherein said pulse width of said read clock signal and said pulse width of said write clock signal are adjusted individually.