Patent ID: 8549366

Claim:
A memory refreshing circuit that refreshes a memory at a refresh cycle, comprising: a normal patrol controller that controls a normal patrol operation that patrols entire address of the memory; an additional patrol controller that controls an additional patrol operation that patrols, when a first error in the memory is detected during the normal patrol operation performed by the normal patrol controller, an error occurring address at which the first error has occurred; an error monitor that measures, when a second error is detected at the error occurring address during the additional patrol operation performed by the additional patrol controller, an error frequency representing information of error occurred at the error occurring address; and a refresh cycle adjustment controller that adjust the refresh cycle in accordance with the error frequency measured by the error monitor, wherein the refresh cycle adjustment controller stepwisely shortens the refresh cycle when the error frequency measured by the error monitor increases, and the refresh cycle adjustment controller stepwisely lengthens the refresh cycle when the error frequency measured by the error monitor decreases.