Patent ID: 8686566

Claim:
A coreless, pin-grid array substrate, comprising: a die side and a land side; a pin-grid array (PGA) signal pin disposed integral with the land side, wherein the PGA signal pin is in direct contact with a first via disposed in a first interlayer and also in direct contact with a first-level trace in contact with the first interlayer; a PGA power-ground pin disposed integral with the land side, wherein the PGA power-ground pin is in direct contact with a first via disposed in the first interlayer and also in direct contact with a first-level trace in contact with the first interlayer; a subsequent interlayer disposed adjacent the die side, wherein electrical connections from the PGA signal pin and the PGA power-ground pin are coupled through the subsequent interlayer; a subsequent trace is in contact with the subsequent interlayer; a plurality of intermediate interlayers disposed between the first interlayer and subsequent interlayer; and a signal plurality of intermediate vias that electrically couple the PGA signal pin to the die side; and a power-ground plurality of intermediate vias that electrically couple the PGA power-ground pin to the die side.