Patent ID: 6862703

Claim:
An apparatus responsive to input control data and commands for performing a test on a memory array having rows and columns of memory cells and for generating output data characterizing test results, wherein each memory cell resides in one row and in one column, wherein each row has a separate row address, wherein each column has a separate column address, and wherein each memory cell has a separate address formed by a unique combination of row and column addresses of the row and column in which the memory cell resides, the apparatus comprising: a memory tester for testing each memory cell and producing fail data indicating whether the memory cell is defective; and a plurality of counters, wherein each counter corresponds to an area of the memory array including only memory cells having addresses formed by any combination of row and column addresses within a particular row address range and a particular column address range separately specified for each counter by the input control data, and wherein each counter monitors the fail data produced by the memory tester to determine which memory cells are defective and generates a count of a number of defective memory cells residing within its corresponding area, such that counts produced by the counters characterize the test results.