Patent ID: 8803413

Claim:
A symmetric quadrupole structured field emission display without spacer, comprising two parallel substrates which are adapted in the size, wherein a number of longitudinal strips of anode electrode are settled on the underside of the upper substrate side by side, the bus electrodes are settled on the anode along the longitudinal centerline, phosphor layer and anode dielectric layer are settled on the anode and bus electrode along the longitudinal alternating, comb-like dielectric layer is settled on the underside of the upper substrate, the comb-like dielectric layer is composed of lateral connection belts that are arranged in the flanking on the upper substrate and a number of longitudinal working belts that are arranged side by side on one side of the lateral connection belts, the longitudinal work belts and the anodes are parallel, and are arranged on the upper substrate where are not covered by the anode, longitudinal strip-like gate A 1 and A 2 are arranged on both sides of each longitudinal work belts, with the bus electrode as symmetry center, interdigital gate electrodes are located on both sides of each anode, dielectric layer for gate protection is arranged on the gate A 1 and A 2 , and on the longitudinal work belts that are not covered by the gate A 1 and A 2 ; a number of horizontal strip-like cathodes are arranged on the upper side of the under substrate side by side, resistor layer for current limiting B 1 , dielectric layer for cathode protection C 1 , resistor layer for current limiting B 2 and the dielectric layer for cathode protection C 2 are arranged on each cathode along the horizontal alternating, electron emission layer D 1 and D 2 are arranged on resistor layer for current limiting B 1 and B 2 , a number of longitudinal strip-like auxiliary electrodes are arranged side by side and alternating perpendicular on the top of the cathode, each intersect of the auxiliary electrode and cathode is isolated by the dielectric layer for cathode protection C 2 ; dielectric layer for isolation is arranged between the upper and under substrates, the two ends of the dielectric layer for isolation are both connected respectively to the dielectric layer for gate protection and dielectric layer for cathode protection C 1 .