Patent ID: RE45051

Claim:
A memory device comprising: a memory cell array including a plurality of multi-level cells (MLCs) respectively connected to a plurality of bit line pairs and a plurality of word lines; a plurality of page buffer circuits comprising a plurality of latch circuits disposed corresponding to the a plurality of bit line pairs, respectively, wherein each of the page buffer circuits comprises latch circuits and each of the latch circuits outputs a data to be programmed into one of the MLCs connected to a pair bit line of a corresponding bit lines line pair at the time of a program operation , and stores data read from one of the MLCs connected to the pair bit line of the corresponding bit lines line pair , and wherein a first latch circuit included in the plurality of the latch circuits is connected to a data I/O line while a second latch circuit included in the plurality of the latch circuits is not connected to the data I/O line and the second latch circuit stores and outputs an input data received through the first latch circuit; and a plurality of Y gate circuits connected to the plurality of page buffer circuits, respectively, and further connected to the data I/O line, wherein each of the Y gate circuits outputs a program data, which is received through the data I/O line, to the first latch circuit in response to one of I/O control signals at the time of a program operation, and outputs a read data, which is received from the first latch circuit, to the data I/O line at the time of a read operation.