Patent ID: 8767471

Claim:
A system comprising: a controllable delay circuit configured to receive a read strobe signal from a flash memory device and to delay the read strobe signal; a data latch, coupled to the controllable delay circuit, configured to receive the delayed read strobe signal, and to capture data from the flash memory device using the delayed read strobe signal; and a calibration circuit coupled to the controllable delay circuit, configured to: instruct the controllable delay circuit to delay the read strobe signal at one of a plurality of delay settings, receive data captured at the data latch using the read strobe signal delayed at the one of the plurality of delay settings, select an adjustment factor from the plurality of delay settings, based on an accuracy of the data captured at the data latch, using a multi-scale approach, for delaying the read strobe signal, wherein the multi-scale approach is designed to determine the adjustment factor iteratively by, at each iteration, fine-tuning an intermediate adjustment factor determined at a previous iteration, and instruct the controllable delay circuit to delay the read strobe signal by the adjustment factor so that the data latch captures sufficiently accurate data during subsequent memory read operations.