Patent ID: 6862675

Claim:
A microprocessor to which a plurality of memory units including a first memory unit and a second memory unit and having physical addresses different from each other are externally connected, said microprocessor comprising: a first address conversion unit which carries out a first address conversion by assigning a first physical address of said first memory unit to a first logical address of a load module stored in said first memory unit, wherein said load module includes an instruction code and numerical data; a copying unit which copies said instruction code from said load module stored in said first memory unit to said second memory unit; and a second address conversion unit which carries out a second address conversion different from the first address conversion by assigning a second physical address of said second memory unit to a second logical address of the instruction code copied to said second memory unit, wherein said first address conversion unit comprises a first comparator that compares a requested logical address with said first logical address, and said second address conversion unit comprises a second comparator that compares said requested logical address with said second logical address.