Patent ID: 8024591

Claim:
A method of reducing power consumption in an integrated circuit comprising at least one processor core, the method comprising: providing a device to control the supply of power to at least one of the processor cores, respectively; providing a memory for saving state data of the at least one processor core; and providing a controller to control transfer of state data between the at least one processor core and the memory such that the at least one processor core can be de-powered and restarted under control of the controller and can be returned to its state as recorded prior to de-powering, wherein the controller comprises a hardware portion and a software portion, and the software portion is arranged to control transfer of state data between the memory and the at least one processor core, and the hardware portion is arranged to control the supply of power to the at least one processor core, wherein both the software portion and the hardware portion are masters for controlling the supply of power of power, and during the process of powering down a processor core the software portion places the processor core that is to be de-powered into a predetermined state once the software portion has caused sufficient state data to be saved, and the hardware portion is responsive to the predetermined state to remove cause removal the supply of power from the processor core.