Patent ID: 7002214

Claim:
A method of manufacture of a Super Steep Retrograde Well (SSRW) FET (Field Effect Transistor) device comprising: forming an SOI layer on a substrate; thinning said SOI layer to form an ultra-thin SOI layer; forming an isolation trench separating said SOI layer into an N well and a P well including ground plane regions in said N well and in said P well, each of said N well and said P well having a top surface; doping said N well and said P well formed in said SOI layer with N-type and P-type dopant respectively; forming an epitaxial semiconductor layer on said top surfaces of said N well and said P well; forming gate electrode stacks above said epitaxial semiconductor layer with channel regions therebelow; and forming FET source regions and drain regions in said epitaxial layer and in both said N well and said P well.