Patent ID: 7020763

Claim:
A processing core comprising: R-number processing pipelines each comprising N-number of processing paths, wherein each of said R-number of processing pipelines are synchronized to operate as a single very long instruction word (VLIW) processing core, said VLIW processing core being configured to process R×N-number of VLIW sub-instructions in parallel; wherein each of said R-number of processing pipelines comprises S-number of register files, such that said processing core comprises R×S-number of register files; and wherein each of said register files comprises Q-number of M-bit wide registers, and wherein said Q-number of registers within each of said register files are either private or global registers, and wherein when a value is written to one of said Q-number of said registers which is a global register within one of said register files, said value is propagated to a corresponding global register in the other of said register files, and wherein when a value is written to one of said Q-number of said registers which is a private register within one of said register files, said value is not propagated to a corresponding register in the other of said register files; and wherein a Q-bit special register stores bits indicating whether registers in the register files are private registers or global registers, each bit in the Q-bit special register corresponding to one of the registers in the register files.