Patent ID: 8111740

Claim:
A method for computing a configuration of a time-domain equalizer, comprising: determining, using at least one processor, a number (M OPT ) of multipliers, wherein M OPT = ⌊ max ⁡ ( T 0 N , T 1 2 ⁢ N , T 2 4 ⁢ N , T 3 16 ⁢ N ) ⌋ wherein └.┘ means roundup to the closest integer, wherein T 0 being the taps required by the 30 a profile of a very fast digital subscriber line 2 standard (VDSL2), T 1 being the taps required by the 12 a , 12 b , 17 a profile of VDSL2, T 2 being the taps required by the 8 a , 8 b , 8 c , 8 d profile of VDSL2, T 3 being the taps required by an asymmetric digital subscriber line 2+ standard (ADSL2+) downstream; and the factor N≧1 and being chosen as an integer, wherein each of the M OPT multipliers carries out a multiplication operation at every system clock cycle, and wherein, for a data delay-line d(k), k=0, 1, . . . , M OPT ×l−1 and coefficients c(k), k=0, 1, . . . , M OPT ×l−1 being split into 1 segments of M OPT each, the computation of the time-domain equalizer (TEQ) is: TEQ = ∑ k = 0 M OPT ⨯ l - 1 ⁢ ⁢ d ⁡ ( k ) ⁢ c ⁡ ( k ) = ∑ k 2 = 0 l - 1 ⁢ ⁢ ∑ k 1 = 0 M OPT - 1 ⁢ ⁢ d ⁡ ( k 2 ⁢ l + k 1 ) ⁢ c ⁡ ( k 2 ⁢ l + k 1 ) .