Patent ID: 7277342

Claim:
A semiconductor memory, comprising: a memory cell array including memory cells arranged in a matrix configuration; read word lines connected to rows of the memory cell array on a one-to-one basis, the read word lines transmitting a read control signal to the memory cells; read lines connected to columns of the memory cell array on a one-to-one basis, the read lines transmitting information output from the memory cells; a dummy cell array including a plurality of dummy memory cells for storing given information; a dummy read line to which the plurality of dummy memory cells are commonly connected; a dummy read line precharge circuit for precharging the dummy read line with charges; and a discharge circuit for discharging the charges of the dummy read line precharged by the dummy read line precharge circuit, wherein the dummy memory cells change the load capacitance of the dummy read line according to information stored therein, and reading of information from the memory cells is controlled according to a change in potential of the dummy read line due to the discharge of the discharge circuit.