Patent ID: 8623760

Claim:
A method of forming an integrated circuit, the method comprising: forming a first recess in a dielectric layer, the first recess extending from a top surface of the dielectric layer into the dielectric layer; forming a diffusion barrier layer in the first recess, the diffusion barrier layer comprising portions covering sidewalls of the first recess; forming a conductive line over the diffusion barrier layer in the first recess, and once the conductive line is formed, the diffusion barrier layer does not cover the top surface of the dielectric layer; recessing a top surface of the conductive line, the recessing being performed at least in part by removing a portion of an oxide layer from the top surface of the conductive line, the recessing forming a second recess; reducing, after the recessing, remaining portions of the oxide layer on the top surface of the conductive line to a conductive material; and selectively depositing a metal cap on the conductive line within the second recess and only within a region directly over the conductive line, wherein the metal cap has a top surface higher or lower than a top edge of at least one of the portions of the diffusion barrier layer covering the sidewalls of the first recess.