Patent ID: 8124880

Claim:
A method of manufacturing a circuit board, the method comprising: forming a conductive relievo pattern on a seed layer stacked on a carrier, the conductive relievo pattern comprising a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern; stacking and pressing together the carrier and an insulator, the carrier positioned such that a surface of the carrier having the conductive relievo pattern formed thereon faces the insulator; transcribing the conductive relievo pattern onto the insulator by removing the carrier; forming a conduction pattern on a surface of the insulator having the conductive relievo pattern transcribed thereon, the conduction pattern comprising a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern; removing the first plating layer, the seed layer, the first metal layer and the second metal layer; and forming a height difference between an upper surface of the first circuit pattern buried in the insulator and a lower surface of the second circuit pattern formed on the insulator.