Patent ID: 8492883

Claim:
A semiconductor package comprising: a die pad including: a die mounting region; a peripheral region circumscribing a cavity with a cavity bottom, the peripheral region including a sloped exterior facing surface and a sloped interior facing surface, wherein: the cavity bottom includes the die mounting region and a recess contiguously circumscribing the die mounting region; the recess is formed at a junction of the sloped interior facing surface and the die mounting region such that the sloped interior facing surface and a surface of the recess correspond to a continuous, curved surface; and the sloped exterior facing surface includes an upper sloped surface, a lower sloped surface, and an apex at a junction of the upper sloped surface and the lower sloped surface; a plurality of leads disposed around the die pad, wherein each of the plurality of leads includes an upper sloped portion and a lower sloped portion; and a first semiconductor chip disposed on the die mounting region and electrically coupled to the plurality of leads; and a package body formed over the first semiconductor chip and the plurality of leads so that the package body substantially fills the cavity and substantially covers the upper sloped portions of the die pad and the plurality of leads, and the lower sloped portions of the die pad and the plurality of leads at least partially extend outwardly from a lower surface of the package body.