Patent ID: 8244930

Claim:
A method for synchronizing memories on a first node and a second node, the first node comprising a direct memory access (DMA) engine for transferring data from the first node to the second node over a communication link between the first and the second nodes, the second node comprising a processor complex and independent memory controllers, the method comprising: the DMA engine reading a control block for a data transfer from a sequence of control blocks; in response to the control block, the DMA engine sending data specified by the control block over the communication link to the second node; when the control block does not specify synchronization between the memories on the first and the second nodes: the DMA engine sending an end of transfer (EOT) message after a last datum of the control block and incrementing a counter for EOT messages to the second node; and after sending the EOT message, the DMA engine processing any subsequent control block; and when the control block specifies synchronization between the memories on the first and the second nodes: the DMA engine determining if the counter is at zero so there is no unacknowledged EOT message; when the counter is at zero, the DMA engine sending an EOT message with a synchronization flag after the last datum and incrementing the counter; and after sending the EOT message with the synchronization flag, the DMA engine determining if the counter is again at zero so the EOT message with the synchronization flag has been acknowledged; when the counter is again at zero, the DMA engine processing any subsequent control block.