Patent ID: 8026170

Claim:
A method of forming an integrated circuit, comprising: forming a resist layer over a substrate surface; pressing a template into the resist layer to form a first trench that is elongated in a direction parallel to the substrate surface, the first trench having a first depth in the resist layer, and a second trench that is elongated in a direction parallel to the substrate surface, the second trench having a second depth in the resist layer, the first depth is different than the second depth; subsequently removing the template from the resist layer to expose the first trench and the second trench; depositing a layer of conductive material to fill the first trench and the second trench; and planarizing the conductive material to remove excess conductive material, leaving a first portion of the conductive material in the first trench and a second portion of the conductive material in the second trench to form a continuous conductive horizontal line, the first portion of material having a first resistance per unit length along the continuous conductive horizontal line and the second portion of material having a second resistance per unit length along the continuous conductive horizontal line.