Patent ID: 7381642

Claim:
A method for forming a wirebond and a post-passivation metallization system for an integrated circuit, comprising: providing a silicon substrate, a MOS device in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said dielectric layer; forming a first polymer layer on said passivation layer, wherein said forming said first polymer layer comprises depositing a photosensitive polymer on said passivation layer; forming a second metallization structure over said first polymer layer, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, and wherein said forming said second metallization structure comprises forming a first adhesion/barrier layer over said first polymer layer, forming a first gold layer on said first adhesion/barrier layer, performing a photolithography process to form a photoresist layer on said first gold layer, an opening in said photoresist layer exposing said first gold layer, wherein said photoresist layer has a thickness between 2 and 100 micrometers and wherein said performing said photolithography process comprises using a 1X stepper or aligner, electroplating a second gold layer having a thickness between 2 and 100 micrometers on said first gold layer exposed by said opening in said photoresist layer, removing said photoresist layer, removing said first gold layer not under said second gold layer, and removing said first adhesion/barrier layer not under said second gold layer; and wirebonding to a contact point of said second metallization structure, wherein said contact point is directly over said polymer layer and directly over said MOS device.