Patent ID: 6897108

Claim:
A method for fabricating a vertical transistor DRAM device, comprising: providing a semiconductor substrate comprising a vertical transistor memory array region, a support region, and a transition region between the vertical transistor memory array region and the support region, wherein the vertical transistor memory array region comprises a plurality of vertical transistor memory cells and a plurality of array active areas, the support region comprises a plurality of support active areas isolated from each other by shallow trench isolation regions, and wherein a first pad oxide and a first pad nitride are formed on each of the array active areas, and a second pad oxide and second pad nitride are formed on each of the support active areas; depositing a protective dielectric layer over the semiconductor substrate; coating and patterning an etch array (EA) photoresist layer on the protective dielectric layer, so that the EA photoresist layer is masking the support region and a portion of the transition region; using the EA photoresist layer as an etching mask and etching the protective dielectric layer to expose the first pad nitride in the vertical transistor memory array region; stripping the EA photoresist layer; using the protective dielectric layer to protect the second pad nitride in the support region and removing the first pad nitride in the vertical transistor memory array region to form recesses on the array active areas; forming spacers on walls of the recesses on the array active areas; depositing a dielectric layer covering the protective dielectric layer on the support region, the vertical transistor memory array region, and the transition region, and the dielectric layer filling the recesses; and performing a chemical mechanical polishing (CMP) process to polish the dielectric layer and the protective layer on the support region using the second pad nitride as a polishing stop layer.