Patent ID: 7002967

Claim:
A multi-protocol processor comprising: a system I/O interface to facilitate a selected one or more of physical input of egress data and physical output of ingress data, including selective facilitation of physical input/output of framed egress/ingress data being transmitted/received in accordance with a selected one of a first and a second frame based protocols, responsive to a data flow type specification specifying a data flow in accordance with said selected one of said first and second frame based protocols; a first control block coupled to the system I/O interface to perform data link sub-layer frame processing on framed egress data inputted through said system I/O interface, framed ingress data to be outputted through said system I/O interface, or both, when the data flow type specification specifies said selected one of said first and second frame based protocols; a first coder coupled to the first control block to perform physical sub-layer encoding and decoding of said framed egress/ingress data, when the data flow type specification specifies said selected one of said first and second frame based protocols; a second control block coupled to the first coder to perform physical sub-layer path processing on said framed egress/ingress data, when the data flow specification specifies said second frame based protocol as the selected one of said first and second frame based protocols; a third control block coupled to the second control block to perform physical sub-layer section and line processing on the framed egress/ingress data, when the data flow type specification specifies said second frame based protocol as the selected one of said first and second frame based protocols; and a network interface coupled to the first coder and the third control block to selectively facilitate physical output/input of said framed egress/ingress data when the data flow type specification specifies said selected one of said first and second frame based protocols.