Patent ID: 8610174

Claim:
A transistor comprising: a semiconductor substrate; a trench isolation regions in said substrate; a sub-collector region in said substrate positioned laterally adjacent to said trench isolation region such that top surfaces of said trench isolation region and said sub-collector region are essentially co-planar; a first dielectric layer on said substrate immediately adjacent to said top surfaces of said sub-collector region and said trench isolation region; a second dielectric layer on said first dielectric layer, said second dielectric layer comprising a different dielectric material than said first dielectric layer; a trench extending vertically through said second dielectric layer and said first dielectric layer to said substrate, said trench having a lower portion with a first width within said first dielectric layer and an upper portion with a second width that is less than said first width within said second dielectric layer; a raised collector pedestal on said substrate, said raised collector pedestal comprising a semiconductor layer filling said lower portion and said upper portion of said trench; and an intrinsic base layer on said second dielectric layer and said semiconductor layer.