Patent ID: 6977831

Claim:
A content addressable memory cell, comprising: a first memory cell for storing data, the first memory cell comprising an inverter circuit and a first and a second access transistors electrically connected to a first word line; a first bit line pair electrically connected to the first memory cell for transferring data to and from the first memory cell; a comparator unit electrically connected to the first memory cell; and an adjusting line electrically connected to the comparator unit, wherein the comparator unit comprises: a first circuit part and a second circuit part, each circuit part having a first circuit branch and a second circuit branch, the first circuit part comprising a first plurality of transistors of a first conduction type and the second circuit part comprising a second plurality of transistors of a second conduction type, each circuit branch of the first circuit part having a first end connected to a supply voltage potential and a second end electrically connected to the adjusting line via a first node, each circuit branch of the second circuit part being electrically connected by a first end to the adjusting line via the first node, wherein the first circuit part comprises: in the first circuit branch, a first transistor connected in series with a second transistor, the first transistor being electrically connected via a respective gate terminal to a first output of the first memory cell; and in the second circuit branch, a third transistor connected in series with a fourth transistor, the third transistor being electrically connected via a respective gate terminal to a second output of the first memory cell, and wherein the second circuit part comprises: in the first circuit branch, a fifth transistor connected in series with a sixth transistor, the sixth transistor being electrically connected via a respective gate terminal to the second output of the first memory cell; and in the second circuit branch, a seventh transistor connected in series with an eighth transistor, the eighth transistor being electrically connected via a respective gate terminal to the first output of the first memory cell; and wherein the second transistor and the fifth transistor are electrically connected via respective gate terminals to a first bit line of the first bit line pair and wherein the fourth transistor and the seventh transistor are electrically connected via respective gate terminals to a second bit line of the first bit line pair.