Patent ID: 7903160

Claim:
A data transfer circuit comprising: a plurality of data transfer lines each used for transferring data; a plurality of data outputting sections each used for detecting said data transferred by one of said data transfer lines and acquiring said detected data synchronously with a data acquiring clock signal; a plurality of data holding sections laid out to form a parallel circuit, each used for holding data according to an input level and each used for transferring said held data to a data transfer line included in said data transfer lines as a data transfer line associated with said held data in response to a select signal; a data-acquiring-clock supplying section configured to supply said data acquiring clock signal to each of said data outputting sections; a clock supplying section configured to generate at least a master clock signal; and a column scan section configured to generate said select signal synchronously with a driving-clock signal and outputting said select signal to each of said data holding sections, wherein: said data transfer lines are laid out in a direction, in which said data holding sections are laid out to form said parallel circuit, and connected to their respective data outputting sections also laid out in the same direction; said column scan section employs: a plurality of select-signal generation sections laid out in said direction, in which said data holding sections are laid out to form said parallel circuit, each used for generating said select signal synchronously with said received driving-clock signal and each used for outputting said select signal to a data holding section included in said data holding sections as a data holding section corresponding to said select signal; and a driving-clock propagation line for propagating said master clock signal and supplying said master clock signal to each of said select-signal generation sections as said driving-clock signal; and said data-acquiring-clock supplying section supplies said master clock signal or a clock signal taking said master clock signal as a reference signal to each of said data outputting sections as said data acquiring clock signal.