Patent ID: 7200712

Claim:
An associative memory system, which outputs an address output signal identifying a network address of a transfer destination with an input of an n-bit (n is an integer equal to or greater than 1) search data, comprising: i) p (p is an integer equal to or greater than 2) primary searching associative memories for storing m (m is an integer equal to or greater than 2) pieces of structured data including primary storage data whose single word is n bits in length and mask information, comparing said search data with said primary storage data for each single word with consideration given to corresponding said mask information, carrying out a logical operation among said primary storage data, each of which is matched with said search data, and outputting an operation result as n-bit intermediate data; ii) an intermediate data operating unit for selecting intermediate data with a least number of invalid state bits out of p pieces of said intermediate data and outputting the intermediate data as n-bit optimized intermediate data; iii) p secondary searching associative memories for storing m pieces of secondary storage data whose single word is n bits in length corresponding to said primary storage data, comparing said optimized intermediate data with said secondary storage data for each single word, and allocating a valid state for matched data or an invalid state for unmatched data to m match lines corresponding to each word; and iv) an address signal generating unit for generating an address output signal for searching for a state of m×p said match lines and identifying the network address of the transfer destination from said secondary storage data corresponding to the match lines allocated to the valid state.