Patent ID: 7618857

Claim:
A method for reducing STI (shallow trench isolation) processing induced stress on a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication of a MOSFET (metal-oxide-semiconductor field-effect transistors), comprising: providing at least one well including dopants of a first conductivity in an upper layer of the substrate; providing at least two STIs in the upper layer of the substrate having one well therebetween; depositing a first dielectric layer on a top surface of the upper layer of the substrate covering the STIs, the first dielectric layer comprising an oxide material; depositing a second dielectric layer over the first dielectric layer, said second dielectric layer comprising a nitride material; annealing the substrate including the at least one well in the upper layer of the substrate using temperatures greater than about 1000° C. to activate the dopants in the at least one well resulting in less stress in the STIs due to the second dielectric layer of nitride material; stripping the first and second dielectric layers off the top surface of the substrate to provide STIs having been exposed to reduced stress from the annealing step; forming and patterning a gate structure including a conductive material layer and a dielectric layer over a silicon region on the top surface of the substrate; and forming a reoxide layer over the gate structure using a low temperature oxide process.