Patent ID: 7821300

Claim:
A system, comprising: a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family, and to produce a second CML signal of the first CML logic family based on the first CML signal and the first bias signal; a first coupling capacitor module coupled to the first CML buffer and configured to receive the second CML signal and to produce a third CML signal based on the second CML signal; a second CML buffer configured to receive a second bias signal and the third CML signal, and to produce a fourth CML signal of a second CML logic family; a feedback module coupled to the second CML buffer and configured to receive the fourth CML signal and produce a fifth CML signal; wherein the second CML buffer is configured to produce the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal; and wherein the feedback module further comprises: a first resistor comprising an input and an output, wherein the input of the first resistor couples to a high output of the fourth CML signal; a second resistor comprising and input and an output, wherein the output of the second resistor couples to the output of the first resistor, and the input of the second resistor couples to a low signal of the fourth CML signal; a third resistor comprising an input and an output, wherein the input of the third resistor couples to the output of the first resistor and the output of the second resistor, and the output of the third resistor couples to a high signal of the third CML signal; and a fourth resistor comprising an input and an output, wherein the input of the fourth resistor couples to the output of the first resistor and the output of the second resistor, and the output of the fourth resistor couples to a low signal of the third CML signal.