Patent ID: 7406569

Claim:
A cache memory for use in storage and retrieval of sequential and non-sequential instructions contained within a program stream for execution by a processor, comprising: a tag array arranged in a plurality of rows and a plurality of cache ways having a plurality of storage locations located at each intersection of one of said plurality of rows and one of said plurality of cache ways, each of said storage locations from the plurality of storage locations for storing a tag address; a data array arranged in a plurality of rows and a plurality of cache ways having a plurality of storage locations located at each intersection of one of said plurality of rows and one of said plurality of cache ways, each of said storage locations from the plurality of storage locations for storing data bytes relating to instructions; a first cache way prediction array having a plurality of storage locations arranged in a plurality of rows, each storage location from the plurality for storing a first set of cache way prediction bits; a second cache way prediction array having a plurality of storage locations arranged in a plurality of rows, each storage location from the plurality for storing a second set of cache way prediction bits; a decision circuit for receiving an instruction from the program stream, the decision circuit for determining whether the instruction is one of a sequential and non sequential type and for enabling one of the first cache way prediction array and the second cache way prediction array, respectively, in dependence thereon, said enabled prediction array accessed at a request address to retrieve one of the first set of cache way prediction bits and the second set of cache way prediction bits, respectively, for enabling a cache way within the tag array and data array in dependence upon the retrieved prediction bits to facilitate retrieval of the tag address and the data bytes from the tag array and data array, respectively, within the enabled cache way; and a program counter for use by the processor in execution of the instructions within the program stream and wherein the request address is derived from the program counter; wherein the decision circuit comprises circuitry for enabling the first cache way prediction array and disabling the second cache way prediction array when the instruction indexed by the program counter is other than a branch instruction.