Patent ID: 8045675

Claim:
A bi-directional shift register for outputting N output signals along a first shifting direction or outputting the N output signals along a second shifting direction, wherein the bi-directional shift register comprises N stages, N is a natural number greater than 1, and an mth stage circuit among the N stages comprises: a first node having a first control signal; an output end for outputting an output signal of the mth stage; a first input circuit coupled to the output end of an (m−1)th stage to receive the output signal of the (m−1)th stage, wherein the first input circuit receives the output signal of the (m−1)th stage as a control signal and a power signal to accordingly generate an enabled first driving signal to the first node in a first period; a second input circuit coupled to the output end of an (m+1)th stage to receive the output signal of the (m+1)th stage, wherein the second input circuit receives the output signal of the (m+1)th stage as a control signal and a power signal to accordingly generate an enabled second driving signal to the first node in a third period; and a shift register unit controlled by the first control signal corresponding to one of the enabled first driving signal and the enabled second driving signal to accordingly generate the enabled output signal of the mth stage in a second period, wherein m is a natural number smaller than or equal to N; wherein the shift register unit comprises: a control circuit controlled by the output signal of an (m+2) th stage, the output signal of an (m−2) th stage and a second control signal for controlling the first control signal to have a disabling level in the third period; a coupling circuit controlled by a rising edge of a first pulse signal for controlling the first control signal to have a capacitor coupling level in the second period; a bias circuit controlled by the first control signal for controlling the second control signal to have a disabling level in the first and the second period and controlling the second control signal to have an enabling level in the third period; and an output stage circuit controlled by the first control signal at the high voltage capacitor coupling level for enabling the output signal of the mth stage in the second period and controlled by the second control signal for disabling the output signal of the mth stage in the third period.