Patent ID: 7579852

Claim:
A wafer translator, comprising: a substrate having a wafer-side and an inquiry-side; a plurality of contact structures disposed on the wafer-side of the substrate; a first plurality of vias, disposed in a regular pattern, the first plurality of vias providing an electrical pathway between the wafer-side and the inquiry-side; and a first inquiry-side conductor pattern disposed on the inquiry-side, the first inquiry-side conductor pattern including a central contact region and a plurality of coplanar conductive link portions extending therefrom, each of the links having a component placement pad portion at a coplanar distal end thereof, and further including a plurality of unlinked component placement pads disposed adjacent corresponding ones of the linked component placement pad portions; wherein the first inquiry-side conductor pattern is repeated at least twice on the inquiry-side; wherein each of the unlinked component placement pads is electrically isolated from any central contact region; and wherein each of the plurality of contact structures is coupled to a corresponding one of the first plurality of vias.