Patent ID: 6897714

Claim:
A reference voltage generating circuit comprising: a first circuit having a pair of first MOS transistors of an N-channel type connected together to form a current mirror circuit, a drain of the output-side first MOS transistor serving as a current output end, a source of the output-side first MOS transistor being connected through a resistor to a plurality of parallel-connected diodes, a drain and a gate of the input-side first MOS transistor serving as a current input end; first, second, and third terminals; a second MOS transistor of a P-channel type having a drain thereof connected to the current output end and having a source thereof connected to the first terminal; a third MOS transistor of a P-channel type having a drain thereof connected to the current input end and having a source thereof connected to the second terminal; an operational amplifier having a first input terminal thereof connected to the current output end, having a second input terminal thereof connected to the current input end, and having an output terminal thereof connected to gates of the second and third MOS transistors, the operational amplifier operating so as to keep a voltage at the current output end equal to a voltage at the current input end; a fourth MOS transistor of a P-channel type having a source thereof connected to the third terminal and having a gate thereof connected to the gates of the second and third MOS transistors; a voltage extraction circuit connected to a drain of the fourth MOS transistor; a reference voltage extraction terminal connected to a node between the fourth MOS transistor and the voltage extraction circuit; and a current mirror circuit composed of fifth, sixth, and seventh MOS transistors of a P-channel type having sources thereof connected to a supply voltage line, wherein the first terminal is connected to a drain and a gate of the fifth MOS transistor and to gates of the sixth and seventh MOS transistors, the second terminal is connected to a drain of the sixth MOS transistor, and the third terminal is connected to a drain of the seventh MOS transistor.