Patent ID: 8716117

Claim:
A method of forming a semiconductor device, comprising: forming gate electrodes on a semiconductor substrate and forming spacers on first and second side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes, wherein each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes, wherein forming the capping patterns comprises: forming a first insulating layer disposed between the spacers; forming a second insulating layer covering the first insulating layer and the gate electrodes, forming first mask patterns having first openings on the second insulating layer, wherein the first mask patterns are formed with a width greater than the width of the gate electrodes, forming second mask patterns on the first mask patterns, the second mask patterns having second openings, the second openings being greater in width than the first openings and exposing the first openings, and etching the first insulating layer using the first and second mask patterns as a mask to expose an upper surface of the semiconductor substrate, and wherein the metal contact is formed to be electrically connected with the semiconductor substrate, and wherein, after removing the second mask patterns, forming the metal contact comprises forming a metal layer filling a space between the gate electrodes, and recessing some of the metal layer and the first mask patterns exposing top surfaces of the capping patterns.