Patent ID: 7519800

Claim:
A heterogeneous computer system comprising: a plurality of interconnected cells, each of the cells further comprising: at least one primary processor, a memory, and at least one type register readable by at least one processor selected from the group consisting of the primary processor and an optional management processor of the cell, the type register comprising instruction set architecture type information associated with the primary processor of the cell; wherein the primary processor of a first cell is of a first instruction set architecture type, and the primary processor of a second cell is of a second instruction set architecture type, wherein the second instruction set architecture type is incompatible with the first instruction set architecture type; wherein the system is capable of being partitioned into a plurality of partitions, wherein each partition comprises at least one of the cells and is capable of executing an operating system, and wherein at least one of the partitions comprises more than one of the cells; and wherein the system further comprises firmware capable of using the instruction set architecture type information in the type register of each of the plurality of cells during system startup to ensure that all said primary processors of each of the plurality of partitions have compatible instruction set architecture types.