Patent ID: 8058084

Claim:
A method of fabricating a pixel structure, comprising: sequentially forming a first metal layer, a first dielectric layer, and a first silicon layer on a substrate; patterning the first metal layer, the first dielectric layer, and the first silicon layer to form an active stack and a capacitive stack respectively on an active area and a capacitive area of the substrate and to form a capacitive line connecting the capacitive stack, wherein the patterned first metal layer, the patterned first dielectric layer and the patterned first silicon layer have a substantially identical pattern; sequentially forming a gate dielectric layer and a second metal layer on the substrate, the active stack, the capacitive stack, and the capacitive line stack; patterning the second metal layer to form a gate on the active stack and a scan line connecting the gate; heavily doping the silicon layer of the active stack, the capacitive stack and the capacitive line stack by using the gate and the scan line as a mask to form heavily doped regions, wherein the heavily doped regions on both terminals of the silicon layer in the active stack are respectively source and drain, and wherein the first metal layer and the heavily doped regions are respectively a first electrode and a second electrode of a storage capacitor; forming a second dielectric layer on the gate dielectric layer, the gate, and the scan line; patterning the second dielectric layer to form a first opening, a second opening and a third opening to respectively expose the drain, the source and the second electrode; forming a third metal layer over the second dielectric layer and in the first, the second and the third openings; patterning the third metal layer to form a data line, a first conductive line connecting the data line and the source, and a second conductive line connecting the drain and the second electrode; forming a planar layer on the second dielectric layer, the data line, the first conductive line and the second conductive line; patterning the planar layer to form a fourth opening to expose the second conductive line; forming a transparent conductive layer on the planar layer and in the fourth opening; and patterning the transparent conductive layer to form a pixel electrode connecting the second conductive line.