Patent ID: 7659189

Claim:
A method for forming a fully silicided gate electrode in a semiconductor device, comprising: providing a semiconductor substrate having thereon a gate oxide layer; depositing a polysilicon layer on the gate oxide layer; performing a blanket ion implantation process to implant dopant species into the polysilicon layer to a first depth; forming a gate hard mask on the polysilicon layer, wherein the gate hard mask defines gate pattern; etching the polysilicon layer and the gate oxide layer to form a gate structure composed of the gate oxide layer, the polysilicon layer and the gate hard mask; forming spacers on respective sidewalls of the gate structure; forming source/drain in the semiconductor substrate next to the spacers and activating the source/drain; depositing a first metal layer overlying the source/drain, the spacers, and the gate hard mask; reacting the first metal layer with the source/drain to form source/drain salicide; removing the unreacted first metal layer; depositing an inter-layer dielectric (ILD) layer overlying the gate structure and the source/drain salicide; chemical mechanical polishing the ILD layer and the gate hard mask to expose the polysilicon layer; and depositing a second metal layer overlying the remaining ILD layer and the exposed polysilicon layer; and reacting the second metal layer with the exposed polysilicon layer to form fully silicided (FUSI) gate electrode and a composite thin film containing the dopant species interposed between the FUSI gate electrode and the gate oxide layer.