Patent ID: 8369976

Claim:
A method for increasing overall yield in semiconductor manufacturing comprising: processing wafers or wafer lots with a first tool from a first group of tools; recording process variation data for each tool of the first group of tools; recording process variation data for each tool of a second group of tools; comparing the recorded process variation data for the first tool to the recorded process variation data for each tool of the second group of tools; determining a second tool from the second group of tools that at least partially neutralizes or compensates for the recorded process variation for the first tool; routing the wafers or wafer lots from the first tool to the determined second tool after processing the wafers or wafer lots with the first tool based on the comparing the recorded process variation for the first tool to the recorded process variation data for each tool of the second group of tools; and updating the routing as new process variation data is received, wherein: the first group of tools is a plurality of upstream tools and the second group of tools is a plurality of downstream tools; the determining where to send the wafers or wafer lots comprises: comparing process variation data for the plurality of upstream tools to process variation data for the plurality of downstream tools; selecting one of the tools of the plurality of downstream tools based, at least in part, on whether the one of the tools comes closest to neutralizing or compensating for processing variation of at least one tool of the plurality of upstream tools; and the wafers or wafer lots are routed to the selected one of the tools of the plurality of downstream tools based on the determination; and the recording comprises grading based on a mean value of a qualification or device measurement result.