Patent ID: 8307167

Claim:
An integrated memory control apparatus, for controlling signals transmitted between a memory and a control chip, and between the memory and a micro-processor unit, the integrated memory control apparatus comprising: a first interface decoder, coupled to the control chip through a first interface, configured to decode received signals; a second interface decoder, coupled to the micro-processor unit through a general transmission interface, configured to decode the received signals; and an interface controller, coupled to the first interface decoder and the second interface decoder, and coupled to the memory through a second interface, wherein the control chip requests a reading cycle for reading data, comprising a plurality of address bits, from the memory through the first interface decoder when the micro-processor unit is reading data from the memory, and then the second interface bridges the address bits sent from the first interface decoder under control of the interface controller, wherein the first interface decoder has a higher priority of accessing the second interface than that of the second interface decoder, and wherein time points for bridged address bits on the second interface is operated to correspondingly fall behind time points for the address bits on the first interface in the reading cycle under control of the interface controller.