Patent ID: 8309462

Claim:
A photolithographic method for fabricating a pattern in a semiconductor device, comprising: depositing a first conformal spacer layer on a patterned, first sacrificial layer above a second sacrificial layer; forming sidewall spacers of the patterned, first sacrificial layer, from the first conformal spacer layer; etching to remove the first patterned sacrificial layer, causing the sidewall spacers to become a first set of freestanding structures; depositing photoresist; transferring a pattern formed by the first set of freestanding structures and the photoresist to the second sacrificial layer, resulting in a patterned, second sacrificial layer having at least first and second portions; depositing a second spacer layer on the patterned, second sacrificial layer; etching the second spacer layer to provide a sidewall spacer of the first portion of the second sacrificial layer, a sidewall spacer of the second portion of the second sacrificial layer, and a spanning region of the second spacer layer which spans between the first portion of the second sacrificial layer and the second portion of the second sacrificial layer; etching away the first portion of the second sacrificial layer, causing the sidewall spacer of the first portion of the second sacrificial layer to become an additional freestanding structure, and forming a gap between the additional freestanding structure and the spanning region of the second spacer layer; and transferring a pattern formed by the additional freestanding structure and a combination of the spanning region of the second spacer layer, the second portion of the second sacrificial layer and the sidewall spacer of the second portion of the second sacrificial layer, to a wiring layer, the additional freestanding structure defines a width of a line in the wiring layer, and the combination defines a hook-up pad in the wiring layer.