Patent ID: 7908500

Claim:
A microcontroller unit, comprising: a processing unit having normal power mode of operation and a low power mode of operation and having: digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values; a plurality of retention flip-flops associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation, wherein each of the plurality of retention flip flops further comprises: a master latch circuit comprised of thin oxide transistors for latching the digital circuit values in the normal power mode of operation; a driver circuit comprised of the thin oxide transistors for driving an output of the retention flip-flops in the normal power mode of operation; and a slave latch circuit for latching the digital circuit values in the low power mode of operation, the slave latch circuit including both the thin oxide transistors and thick oxide transistors, the thick oxide transistors for latching the digital circuit values in the low power mode of operation and both the thick oxide transistors and the thin oxide transistor for use in latching the digital circuit values in the normal power mode of operation.