Patent ID: 7053433

Claim:
An array of ferroelectric field effect transistors (FETs), the array comprising: (a) a first conductivity type semiconductor region; (b) at least one second conductivity type source region, each source region within the first conductivity type semiconductor region; (c) at least one second conductivity type drain region, each drain region within the first conductivity type semiconductor region, paired with and spaced apart from one of the source regions; (d) a first dielectric layer at least covering the first conductivity type semiconductor region between each source region and drain region pair, the first dielectric layer continuous across the array; (e) a ferroelectric layer against the first dielectric layer, opposite each source region and drain region pair; (f) a second dielectric layer having opposing sides, one of the opposing sides facing the ferroelectric layer, the second dielectric layer together with the first dielectric layer encapsulating the ferroelectric layer, the second dielectric layer continuous across the array and extending beyond the ferroelectric layer; and (g) at least one gate electrode layer formed against the side of the second dielectric layer that is opposite the side of the second dielectric layer facing the ferroelectric layer, wherein the at least one gate electrode layer, in combination with a polarization state of the ferroelectric layer, controls the current flow between the source and drain regions.