Patent ID: 7551014

Claim:
An integrated circuit comprising: an output cell, the output cell including: a first selection circuit that has a first input coupled with a first data line and that has an output coupled with a first single-ended driver; a second selection circuit that has a first input coupled with a second data line and that has an output coupled with an input of the second single-ended driver; a phase splitter that has: an input coupled with the first data line; a first output coupled with a second input of the first selection circuit; and a second output coupled with a second input of the second selection circuit, wherein the first output transmits a first signal that is an inverse of a second signal transmitted from the second output; a first single-ended driver having an input coupled with an output of the first selection circuit and having an output coupled with a first output pin; and a second single-ended driver having an input coupled with an output of the second selection circuit and having an output coupled with a second output pin; and an output timing cell including: a first timing device having an output coupled with the first input of the first selection circuit; a second timing device having an output coupled with the first input of the second selection circuit; a third data line coupled with an input of the first timing device; a fourth data line coupled with an input of the second timing device; a third selection circuit having: a first input coupled with the output of the first timing device; a second input coupled with the third data line; and an output coupled with the first input of the first selection circuit; and a fourth selection circuit having: a first input coupled with the output of the second timing device; a second input coupled with the fourth data line; and an output coupled with the first input of the second selection circuit.