Patent ID: 7334150

Claim:
A memory module, comprising: a plurality of memory chips arranged on the memory module; a plurality of bus signal lines operable to supply an incoming clock signal and incoming command and address signals to at least the memory chips; a clock signal regeneration circuit configured to generate a plurality of copies of the incoming clock signal and to supply the copies of the incoming clock signal to the memory chips, the copies of the incoming clock signal having a same frequency as the incoming clock signal; and a register circuit arrange on the memory module in a common chip packing with the clock regeneration circuit and configured to receive one of the copies of the incoming clock signal from the clock regeneration circuit, the register circuit being further configured to temporarily store the incoming command and address signals and to generate a plurality of copies of the incoming command and address signals and supply the copies of the incoming command and address signals to the memory chips, the copies of the incoming command and address signals having a same frequency as the incoming command and address signals.