Patent ID: 7010074

Claim:
An oversampling clock recovery method comprising the steps of: generating non-uniform multi-phase clock signals having a non-uniform interval, said non-uniform multi-phase clock signals comprising three or more phase clock signals for one bit of an input data; controlling a phase of said non-uniform multi-phase clock signals so that a phase of one of two edges in two-phase clock signals having a relative narrower interval among said non-uniform multi-phase clock signals is locked with a phase of a transition point of said input data; digitally controlling, by using selection circuits and delay locked loops each comprising a plurality of delay buffers, phases of two or more sets of uniform multi-phase clock signals having a uniform interval at a resolution less than a propagation delay of a delay buffer in said delay locked loops; keeping, by said digital control, a phase difference between a set of uniform multi-phase clock signals and another set of uniform multi-phase clock signals to a phase difference shorter than said propagation delay, and using a combination of said two or more sets of uniform multi-phase clock signals as said non-uniform multi-phase clock signals.