Patent ID: 7808320

Claim:
A buffer amplifier having a first input terminal, a second input terminal, and an output terminal coupled back to the second input terminal, providing a buffered output signal at the output terminal as according to an input signal applied to the first input terminal, comprising: an input stage circuit coupled between the input terminals and the output terminal for generating four control signals in response to the input signal when the logic level of the buffered output signal is at a logic level opposite to that of the input signal; an output stage circuit coupled to the input stage circuit, having a first output transistor and a second output transistor of a first type and a third output transistor and fourth output transistor of a second type, wherein the first and second output transistor comprise sources coupled together to receive a first supply voltage, gates respectively coupled to receive a first control signal and a second control signal, and drains coupled together at the output terminal, and wherein the third and fourth output transistor comprise sources coupled together to receive a second supply voltage, gates respectively coupled to receive a third control signal and a fourth control signal, and drains coupled together at the output terminal; and a bias circuit coupled between the input stage circuit and the output stage circuit, having a plurality of current mirror circuits for determining the first, second, third, and fourth control signal.