Patent ID: 8285908

Claim:
A bus bridge, comprising: multiple ordered bus interfaces, wherein each ordered bus interface is coupled to an ordered bus; and a flow control logic circuit, coupled to the out-of-order bus and the multiple ordered bus interfaces, for controlling a flow of transaction requests between the out-of-order bus and each of the ordered bus interfaces; wherein the flow control logic circuit includes: an updating circuit, for updating dependency resolution attributes and data readiness attributes associated with transaction requests; a shared memory unit, for storing the dependency resolution attributes, the data readiness attributes and the transaction requests, wherein the transaction requests are destined to the ordered buses; and a managing circuit, coupled to the shared memory unit and to the multiple ordered bus interfaces, for determining a readiness of each transaction request based on a dependency resolution attribute and a data readiness attribute associated with the transaction request, and for managing a dequeueing of ready transaction requests to the ordered bus interfaces based on an availability of the ordered bus interfaces.