Patent ID: 8397049

Claim:
A memory management unit (MMU) comprising: a translation lookaside buffer (TLB) configured to store a plurality of virtual to physical address translations that have previously been used to translate virtual addresses received by the MMU; a buffer configured to store a block of data that includes a plurality of page table entries including a first page table entry previously read during a translation of a virtual address that missed in the TLB, and wherein the block of data was read in response to the virtual address that missed in the TLB and at least one of the plurality of page table entries was returned to the MMU along with the first page table entry as read data in response to a read request issued by the MMU to read the first page table entry, and wherein the at least one of the plurality of page table entries is not part of a translation for the virtual address that missed in the TLB, and wherein the buffer is configured to store only blocks of data that include page table entries, and wherein each page table entry maps a virtual page corresponding to the page table entry to a physical page defined by the page table entry; and a table walk unit coupled to the TLB and to the buffer, wherein the table walk unit is coupled to receive a first virtual address of a first TLB miss in the TLB, and wherein the table walk unit is configured to check the buffer for a second page table entry corresponding to the first virtual address prior to initiating a memory read for the translation.