Patent ID: 6981168

Claim:
A clock data recovery system for generating a clock signal according to an incoming data signal stream, comprising a clock generator having a control signal input and having a clock signal output, for generating a clock signal, said clock signal having one or more of the frequency and phase of which is dependent upon said signal input, a phase detector with a clock signal input, a data signal input for an incoming data signal stream, and a phase difference signal output, wherein said phase difference signal is related to a phase difference between said generated clock signal and said incoming data signal stream, and a loop controller with a control signal output delivering said control signal, which is dependent on said phase difference signal; a bit transition detector and a density calculator to determine a bit transition rate of the incoming data signal stream; wherein said loop controller has a variable gain that is dependent upon the bit transition rate of said incoming data signal stream such that a residual error of a feedback-based control loop formed by the clock generator, the phase detector and the loop controller is limited to 1/(1+A), where A is an open-loop gain of the control loop and wherein said control signal is dependent on said variable gain.