Patent ID: 7262983

Claim:
A multi-chip module comprising: a memory chip formed on a first semiconductor substrate, the memory chip comprising a memory cell array comprising a word line, a plurality of first bit lines across the word line, a plurality of second bit lines across the word line, a first flag bit line across the word line, a second flag bit line across the word line, a plurality of first memory cells arranged at intersections of the word line and the plurality of first bit lines, a plurality of second memory cells arranged at intersections of the word line and the plurality of second bit lines, a first flag memory cell arranged at intersections of the word line and the first flag bit line, and a second flag memory cell arranged at intersections of the word line and the second flag bit line, a plurality of first sense amplifiers, each of the first sense amplifiers being coupled with corresponding one of the plurality of first bit lines, a plurality of second sense amplifiers, each of the second sense amplifiers being coupled with corresponding one of the plurality of second bit lines, a first flag sense amplifier coupled to the first flag bit line, and a second flag sense amplifier coupled to the second flag bit line; and a logic chip formed on a second semiconductor substrate and coupled with the memory chip, wherein the memory cell array is arranged between the plurality of first sense amplifiers and the plurality of second sense amplifiers, wherein data amplified by the plurality of first sense amplifiers and data amplified by the plurality of second amplifiers are independently encoded, wherein the first flag memory cell stores information that relates to encoding of data stored in the plurality of first memory cells, wherein the second flag memory cell stores information that relates to encoding of data stored in the plurality of second memory cells, and wherein the memory chip and the logic chip are mounted on a first substrate.