Patent ID: 8154085

Claim:
A non-volatile semiconductor memory comprising: a plurality of memory cell transistors provided in a memory cell transistor region, and a plurality of resistors provided in a resistor region positioned around a periphery of the memory cell transistor region, each memory cell transistor having: source/drain diffusion layers provided in a semiconductor substrate; a first gate insulating film located on the semiconductor substrate between the source/drain diffusion layers; a floating gate electrode layer located on the first gate insulating film; a first inter-gate insulating film located on the floating gate electrode layer; a control gate electrode layer located on the first inter-gate insulating film; and a first low-resistance layer located on the control gate electrode layer, each resistor having: a second gate insulating film located on the semiconductor substrate; a first electrode layer located directly on the second gate insulating film; a second inter-gate insulating film located on the first electrode layer; a second electrode layer located on the second inter-gate insulating film and isolated from the first electrode layer electrically; a mask film located on the second electrode layer; a second low-resistance layer located on the second electrode layer adjacent to the mask film, the second low-resistance layer comprising at least two parts being located on the second electrode layer, wherein the parts of the second low-resistance layer are electrically separated from each other; a first interlayer insulating film covering the memory cell transistor and the resistor; a second interlayer insulating film located on the first and second low-resistance layer, the first interlayer insulating film, and the mask film; and contact plugs located within the second interlayer insulating film, separate and distinct from the second low-resistance layer, and connected to the second low-resistance layer, a width of each contact plug being different from a width of a respective part of the second low-resistance layer, wherein the second electrode layer is extended from one part of the second low-resistance layer to an other part of the second low-resistance layer.