Patent ID: 8604526

Claim:
A semiconductor device comprising: (a) a semiconductor substrate; (b) a gate insulation film formed over the semiconductor substrate; (c) a gate electrode formed over the gate insulation film; (d) a source region formed in the semiconductor substrate so as to align with the gate electrode; (e) a drain region formed in the semiconductor substrate so as to align with the gate electrode; (f) a first insulation film formed over the gate electrode; (g) a first plug penetrating the first insulation film and electrically connected to the source region; (h) a second plug penetrating the first insulation film and electrically connected to the drain region; (i) a first wire formed over the first insulation film and electrically connected to the first plug; (j) a second wire formed over the first insulation film and electrically connected to the second plug, the second wire being formed at the same layer as the first wire; (k) a second insulation film formed over the first insulating film, the first wire, and the second wire; (l) a third plug penetrating the second insulation film and electrically connected to the first wire; (m) a fourth plug penetrating the second insulation film and electrically connected to the second wire; (n) a third wire formed over the second insulation film and electrically connected to the third plug; and (o) a fourth wire formed over the second insulation film and electrically connected to the fourth plug, the fourth wire being formed at the same layer as the third wire, wherein the gate electrode and the first wire are arranged not to be overlapped with each other in planar view, and the gate electrode and the second wire are arranged not to be overlapped with each other in planar view, and wherein the gate electrode and an edge of the third wire are arranged to be overlapped with each other in planar view, and the gate electrode and an edge of the fourth wire are arranged to be overlapped with each other in planar view.