Patent ID: 7195929

Claim:
A method for fabricating an MRAM, comprising: (1) forming a transistor on a semiconductor substrate; (2) forming a first interlayer dielectric on the semiconductor substrate to cover the transistor; (3) forming a first data line on the first interlayer dielectric; (4) forming a second interlayer dielectric on the first interlayer dielectric to cover the first data line; (5) forming a pad conductive layer on a portion of the second interlayer dielectric to be coupled to a drain region of the transistor, wherein the pad conductive layer is formed to be symmetric about the drain region; (6) forming a first MTJ cell and a second MTJ cell spaced apart from the first MTJ cell on the pad conductive layer; (7) forming a third interlayer dielectric on the second interlayer dielectric to cover the pad conductive layer, the first MTJ cell, and the second MTJ cell; and (8) forming a first bit line coupled to the first MTJ cell and a second bit line coupled to the second MTJ cell on the third interlayer dielectric.