Patent ID: 6839783

Claim:
A state machine input/output circuit responsive to a clock signal having cyclically repeating rising edges and falling edges, for providing data to an output port, comprising: a memory having a plurality of storage elements, each storage element being adapted to store a bit and provide the bit as an output of said memory; a first multiplexer having a multiplexer output, having a plurality of inputs receiving the outputs of said memory, and having a control input for selecting, in response to a control signal, an input for connection to said multiplexer output; a control signal generator connected to the control input of the first multiplexer for generating a control signal to control said first multiplexer to select said first multiplexer inputs for connection to said first multiplexer output; and a clock edge selector circuit connected to said first multiplexer for providing, in response to an edge select signal, the output of said first multiplexer to said output port selectably on either said rising edges or said falling edges of said clock signal.