Patent ID: 7167991

Claim:
A leakage current reducing method of an LSI for reducing leakage current in an LSI chip divided into two parts; namely a main power supply region including circuits operated by receiving power from a main power source, and a backup power supply region including circuits operated by receiving power from a backup power source, said LSI chip having a scanning control circuit and a power supply cut-off controller built-in to the LSI chip, said method comprising the steps of: connecting memory units in each of the circuits provided in the main power supply region through a scan path; starting a scanning operation, when the LSI chip is placed in an operation standby state, through the scan path, and reading information held in the memory units of each of the circuits provided in the main power supply region based upon a scan mode signal and a scanning clock pulse; and saving the information thus read by the scanning operation in a built-in storage section provided in the backup power supply region.