Patent ID: 7023944

Claim:
A circuit for glitch-free changing of clocks having different phases, wherein the circuit receives M clocks labeled by 1˜M and at least one data stream, in which the M clocks have the same frequency and are different in phase sequentially, and one of the M clocks (labeled by N, 1≦N≦M) is selected to be a system clock, the circuit comprising: a phase detector for detecting the phases of the data stream and the system clock, and generating a phase-up signal and a phase-down signal accordingly; a flag signal generator coupled to the phase detector for receiving the phase-up signal and the phase-down signal, and then generating M flag signals, wherein only one of the M flag signals is enabled at the same time; a select signal generator coupled to the flag signal generator, for receiving the M flag signals and the M clocks to correspondingly generate M select signals; means for enabling the select signal corresponding to the enabled flag signal; and an output stage coupled to the select signal generator, for receiving the M select signals and the M clocks, and then outputting the system clock, wherein the outputted system clock corresponds to one of the M clocks selected by the enabled select signal; wherein when the phase of the data stream lags behind the phase of the system clock, the phase-up signal is enabled, then a flag signal N+1 corresponding to a clock N+1 is enabled, a select signal N+1 corresponding to the flag signal N+1 is enabled, and the clock N+1 is set as the system clock; and wherein when the phase of the data stream leads the phase of the system clock, the phase-down signal is enabled, then a flag signal N−1 corresponding to a clock N−1 is enabled, a select signal N−1 corresponding to the flag signal N−1 is enabled, and the clock N−1 is set as the system clock.