Patent ID: 8483428

Claim:
A digital image processing apparatus to process video data information of a captured input digital image comprising: a first programmable register to store a first value that corresponds to a first width of a first quadrangle digital image, wherein the first quadrangle digital image comprises a first portion of the captured input digital image; a second programmable register to store a second value that corresponds to a first height of the first quadrangle digital image, wherein the first width corresponds to a first number of pixels in the horizontal direction and the first height corresponds to a first number of lines in the vertical direction; a third programmable register to store a third value that corresponds to a first location information of the first quadrangle digital image, wherein the first location information comprises information that corresponds to a first memory location of a memory device; a first logic circuitry coupled to the memory device, a first buffer, and to the first, second, and third programmable registers, and is configured to: (i) retrieve from the memory device a first video data information that corresponds to at least a portion of the first quadrangle digital image, in accordance with a first video format and the first, second, and third values, (ii) generate on-the-fly a second video data information that corresponds to at least one pixel of one of a first top margin and a first bottom margin, and (iii) store the first and second video data information using the first buffer; a second logic circuitry coupled to the first buffer and a second buffer, and is configured to (i) process in the vertical direction the first and second video data information, and (ii) output the vertically processed video data information to the second buffer; a third logic circuitry coupled to the second buffer and a fourth logic circuitry, and is configured to: (i) retrieve from the second buffer the vertically processed video data information, (ii) generate on-the-fly a third video data information that corresponds to at least one pixel of one of a first right margin and a first left margin, (iii) process in the horizontal direction the retrieved vertically processed video data information and the third video data information, and (iv) stream the vertically and horizontally processed video data information to the fourth logic circuitry; and the fourth logic circuitry coupled to a fifth logic circuitry, the first and second programmable registers, and is configured to: (i) receive the vertically and horizontally processed video data information, (ii) generate a first data enable signal that is synchronized to the received vertically and horizontally processed video data information, and (iii) output the vertically and horizontally processed video data information and the first data enable signal to the fifth logic circuitry.