Patent ID: 7260790

Claim:
A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; constructing a Vornoi diagram for a particular fault mechanism based on a layout of device shapes in said initial integrated circuit design; associating variables with the positions of edges of said device shapes in said integrated circuit design; associating cost functions of said variables with spacing between said edges in said integrated circuit design; defining said cost functions in terms of critical area contributions of linear bisectors between said edges of said device shapes, wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges of said device shapes, and wherein a critical area contribution of a given linear bisector is proportional to a cross product of an x-y difference vector between normal vectors of planes of Vornoi cells which meet at said given linear bisector and an x-y difference vector representing a length of said given linear bisector such that said critical area contribution of said given linear bisector is a function of said variables; and, optimizing said positions and length of said edges of said device shapes in said integrated circuit design to reduce critical area contribution cost in a first direction across said integrated circuit design to produce a revised integrated circuit.