Patent ID: 8490101

Claim:
A method for thread scheduling on a chip multithreading processor (CMP), comprising: identifying an L2 cache hit threshold for an L2 cache of the CMP; estimating an aggregate L2 cache hit rate for a group of threads comprising a first plurality of threads and a second plurality of threads, wherein the first plurality of threads have a first plurality of cache memory space requirements (CMSR) corresponding to cache localities of the first plurality of threads, and wherein the second plurality of threads have a second plurality of CMSR corresponding to cache localities of the second plurality of threads; comparing the aggregate L2 cache hit rate with the L2 cache hit threshold; scheduling the group of threads in response to the L2 cache hit rate exceeding the L2 cache hit threshold, wherein scheduling the group comprises: comparing the first plurality of CMSR with a pre-defined threshold; assigning, in response to the first plurality of CMSR exceeding the pre-defined threshold, the first plurality of threads to a first processing core of the CMP; comparing the second plurality of CMSR with the pre-defined threshold; and assigning, in response to the second plurality of CMSR being less than the pre-defined threshold, the second plurality of threads to a second processing core of the CMP.