Patent ID: 8508024

Claim:
A chip package structure adapted to be disposed on a carrier, the chip package structure comprising: a package substrate comprising: a laminated layer having a first surface and a second surface opposite to each other; a patterned conductive layer disposed on the first surface of the laminated layer and comprising at least one inner pad; a solder-mask layer disposed on the first surface of the laminated layer and having at least one opening from which the inner pad is exposed; at least one outer pad disposed on the solder-mask layer and within the opening, wherein the outer pad is connected with the inner pad exposed from the opening, and the at least one outer pad is adapt to be connected with at least one solder ball of the chip package structure to connect the chip package structure and an electronic component; and a padding pattern disposed on the solder-mask layer, wherein a height of the padding pattern relative to the first surface of the laminated layer is greater than a height of the outer pad relative to the first surface of the laminated layer, the outer pad does not contact the carrier when the package substrate is disposed on the carrier with the padding pattern, and the padding pattern does not contact the electronic component when the package substrate is connected with the electronic component via the solder ball; and a chip disposed on the package substrate, the chip located on the second surface of the laminated layer and electrically connected to the package substrate.