Patent ID: 6995050

Claim:
A method of fabricating a thin film transistor, requiring only four photolithography steps, comprising: providing a substrate; forming a semiconductive layer on the substrate; patterning the semiconductive layer to form a semiconductor island, wherein the semiconductor island comprises a channel region and predetermined source and drain regions adjacent to the channel region; forming a gate insulating layer and a first conductive layer sequentially on the substrate and the semiconductor island; patterning the first conductive layer to simultaneously form a gate electrode on the gate insulating layer above the channel region and source/drain electrodes on the respective gate insulating layer adjacent to the semiconductor island; using the gate electrode as a mask to perform a self-aligned ion implantation on the predetermined source and drain regions to form source/drain regions; forming a dielectric layer on the gate insulating layer, the gate electrode, and the source and drain electrodes; patterning the dielectric layer to form a plurality of contact holes via the dielectric layer and the gate insulating layer exposing part of the surface of source/drain regions and electrodes; and forming a patterned second conductive layer on predetermined parts of the dielectric layer to electrically connect the source and drain regions to the source and drain electrodes through the contact holes.