Patent ID: 7904874

Claim:
A design method for an opposite-phase clock tree with an opposite-phase scheme, the opposite-phase clock tree including a clock source for providing a clock signal, the design method comprising the steps of: providing a circuit layout including a plurality of flip-flops, the plurality of flip-flops initially being positive-triggered flip-flops; dividing the plurality of flip-flops of the circuit layout into a positive-phase set and a negative-phase set; replacing the flip-flops of the negative-phase set by negative-triggered flip-flops; and designing a positive-phase clock tree and a negative-phase clock tree by using a design utility, both of the positive-phase clock tree and the negative-phase clock tree using the same clock signal; wherein the positive-phase clock tree is connected to each of the positive-triggered flip-flops, and the negative-phase clock tree is connected to each of the negative-triggered flip-flops, and both the positive-triggered flip-flops and the negative-triggered flip-flops are configured to be triggered at a same timing point.