Patent ID: 7142462

Claim:
An apparatus comprising a receiving device of a semiconductor memory unit which comprises: a plurality of pre-amplifiers; and a plurality of samplers, wherein input ports of the samplers are connected to respective output ports of the pre-amplifiers, and the respective samplers sample data signals input into the input ports of the plurality of samplers in response to corresponding clock signals wherein the input ports of samplers of a first group among the plurality of samplers are each connected to the output ports of a corresponding first pre-amplifier among the plurality of pre-amplifiers, wherein the input ports of samplers of a second group among the plurality of samplers are each connected to the output ports of a corresponding second pre-amplifier among the plurality of pre-amplifiers, and wherein each of the samplers of the first and second group samples data signals input into the input ports thereof in response to a corresponding clock signal, and wherein each of the samplers of a first group and the second group sample the data signals in response to corresponding clock signals having different phases, wherein each of the clock signals input into the samplers of the first group has a phase corresponding to the edge of the data signals and is aligned with the data signals, and wherein each of the clock signals input mo the samplers of the second group has a phase corresponding to a predetermined point between edges of the data signals and is used for extracting the data signals.