Patent ID: 6914291

Claim:
A self-aligned floating-gate structure, comprising: a semiconductor substrate of a first conductivity type; a plurality of shallow-trench-isolation (STI) regions and a plurality of active regions being formed alternately on said semiconductor substrate, wherein each of the plurality of active regions comprises a first conductive layer over a tunneling-dielectric layer being formed over said semiconductor substrate and each of the plurality of STI regions comprises an etched-back field-oxide layer and a pair of extended second conductive layers being formed on side and top portions of said etched-back field-oxide layer; a thin sidewall conductive spacer being formed over each sidewall of said extended second conductive layers to form a plurality of self-aligned floating-gate layers; an intergate-dielectric layer being formed over a surface formed by the plurality of self-aligned floating-gate layers and said etched-back field-oxide layer between nearby self-aligned floating-gate layers; a planarized third conductive layer being formed over said intergate-dielectric layer; and a capping conductive layer being formed over said planarized third conductive layer.