Patent ID: 8274844

Claim:
A semiconductor device comprising: a semiconductor substrate, first and second data input/output terminals provided on the semiconductor substrate, first and second memory circuit units provided on the semiconductor substrate, the first memory circuit unit being activated in response to a first selection signal so that the first memory circuit unit inputs/outputs data from/to the first data input/output terminal and does not input/output data from/to the second data input/output terminal, the second memory circuit unit being activated in response to a second selection signal so that the second memory circuit unit inputs/outputs data from/to the second data input/output terminal and does not input/output data from/to the first data input/output terminal, a command terminal provided in common to the first and second memory circuit units, wherein the first and second memory circuit units respectively comprise first and second command latch circuits that latch a command signal supplied via the command terminal or latch a signal obtained by decoding the command signal, a latch operation performed by the first command latch circuit is permitted when the first selection signal is activated, and a latch operation performed by the second command latch circuit is permitted when the second selection signal is activated.