Patent ID: 7627071

Claim:
A timing synchronization module, for controlling the output of a media signal, the timing synchronization module comprising; a phase locked loop (PLL), for receiving an output-end clock signal, wherein when the PLL receives the output-end clock signal for the first time, the PLL generates a reception-end clock signal according to the output-end clock signal; a synchronization processing unit, for receiving a procedure clock signal and the output-end clock signal; and a decoder buffer, wherein the output-end clock signal has M pulses after the reception-end clock signal is generated, the reception-end clock signal has N pulses as generated, wherein M and N are positive integers, and when a difference value between M and N is smaller than a first preset value and larger than a second preset value, the synchronization processing unit adjusts the volume of the decoder buffer so that the media signal corresponding to the procedure clock signal is stored temporarily in the decoder buffer, and adjusts the speed of playing the media signal; wherein when the difference value is larger than the first preset value, the synchronization processing unit removes the media signal corresponding to the procedure clock signal, and the PLL generates the reception-end clock signal again according to the output-end clock signal; wherein when the difference value is smaller than the second preset value, the PLL outputs the reception-end clock signal, and the synchronization processing unit controls the playing of the media signal according to the reception-end clock signal and the procedure clock signal.