Patent ID: 7368964

Claim:
A delay locked loop (DLL) comprising: a clock buffer for receiving an external clock and buffering an internal clock; an enable clock generator for generating a 1-period enable clock or a 2-period enable clock based on a command signal generated for performing a predefined operation; and a clock divider for dividing the internal clock to generate a divided clock, the divided clock being controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock, wherein the enable clock generator includes: a 1-period enable clock generating unit for logically combining a first group of CAS latency command signals to generate the 1-period enable clock; and a 2-period enable clock generating unit for logically combining a second group of CAS latency command signals to generate the 2-period enable clock, the second group of the CAS latency command signals having a value greater than the first group of the CAS latency command signals.