Patent ID: 8464029

Claim:
An out-of-order execution hardware microprocessor for reducing a likelihood of having to replay a load instruction due to a store collision, the microprocessor comprising: a first queue of entries; a second queue of entries; and a register alias table (RAT), coupled to the first and second queues of entries, the RAT configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order, the RAT further configured to: allocate an entry of the first queue and populate the allocated entry with an instruction pointer of the load instruction, when the RAT determines that the load instruction must be replayed; allocate an entry of the second queue, when the RAT encounters a store instruction, and populate the allocated entry of the second queue with a dependency that identifies an instruction upon which the store instruction depends for its data; and cause a subsequent instance of the load instruction to share the dependency that identifies the instruction upon which the store instruction of one of the second queue entries depends for its data, when the RAT encounters the subsequent instance of the load instruction and determines that its instruction pointer matches the instruction pointer of an entry of the first queue.