Patent ID: 8174293

Claim:
A time to digital converter comprising: a delay circuit having a plurality of delay stages configured to delay an input clock signal in multiple stages, at least one of the plurality of delay stages being a variable delay stage; a plurality of flip flops that are provided in a number same as a number of the plurality of delay stages of the delay circuit and that are configured to capture outputs of the plurality of delay stages corresponding thereto in parallel in response to input of a reference signal which is different from the input clock signal in phase; an edge detecting circuit configured to detect one or both of rising edges and falling edges of respective outputs of the plurality of flip flops; a counter circuit configured to count a number of edges detected by the edge detecting circuit; a control circuit configured to control a delay amount of the variable delay stage according to the number of edges counted by the counter circuit; and a digital-code generating circuit configured to convert, based on a detection output of the edge detecting circuit, a decimal fraction phase difference between a period of the input clock signal and the reference signal into a digital code.