Patent ID: 7191421

Claim:
An integrated circuit design apparatus providing an integrated circuit design, comprising: a block placement processing unit performing processing of creation of a lower-rank mounting block in a higher-rank mounting block, each mounting block containing logic circuit cells, and performing processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block, wherein the virtual placement regions are created in an initial design stage before completing logic circuit cell placement design; a functional block assignment processing unit performing processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit; and an evaluation processing unit providing a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, so that the condition of the assigned functional blocks is evaluated by a designer without moving the logic circuit cells in each virtual placement region wherein the evaluation processing unit, further: provides the designer with the display of a path delay in order to determine whether the path delay is larger than a reference value, and when the path delay is larger than the reference value, provides the designer with an adjustment function to adjust the path delay.