Patent ID: 8356125

Claim:
A device, comprising: a first memory stage storing only a plurality of pointer values associated with a plurality of buffers, wherein said plurality of buffers is associated with a plurality of logical channels, and wherein a logical channel select signal identifying one of the plurality of logical channels is used as an access address to said first memory stage to look up one of the plurality of pointer values; a second memory stage comprising a block memory including the plurality of buffers, wherein an access address to said second memory stage is formed from a concatenation of the logical channel select signal and the one of said plurality of pointer values from the first memory stage; and a single read and write pointer incrementer circuitry that increments or decrements each of the plurality of pointer values stored in the first memory stage, wherein only the access address formed from the concatenation of the logical channel select signal and the one of said plurality of pointer values is used to access the second memory stage.