Patent ID: 7022563

Claim:
A method of manufacturing a semiconductor integrated circuit device, comprising steps of: forming a first groove, a second groove and a third groove in an interlayer insulating film; burying a conductive film in said first, said second and said third groove to form a first conductive pattern in said first groove, a second conductive pattern in said second groove and a third conductive pattern in said third groove, wherein a first MISFET and a second MISFET constitute a memory cell, wherein said interlayer insulating film is formed to cover said first MISFET, said second MISFET and a capacitor element forming region, wherein said first conductive pattern is electrically connected to a drain region of said first MISFET and a gate electrode of said second MISFET, wherein said second conductive pattern is electrically connected to a drain region of said second MISFET and a gate electrode of said MISFET, wherein said third conductive pattern is serving as an electrode of a first capacitor element; forming an insulating film over said first, said second and said third conductive pattern; forming an opening over said first conductive pattern; forming a fourth conductive pattern and a fifth conductive pattern such that said third conductive pattern is formed over said first conductive pattern so as to electrically connect to said first conductive pattern through said opening and such that that said fourth conductive pattern extends over said second conductive pattern, wherein said fifth conductive pattern extends over said third conductive pattern through said insulating film and serves as an another electrode of said first capacitor element, wherein a second capacitor element is comprised of said third conductive pattern, said second conductive pattern and said insulating film.