Patent ID: 7480786

Claim:
A method of using a dedicated processor embedded in a Programmable Logic Device (PLD) to emulate a target processor, the dedicated processor supporting a first instruction set and conforming to a first bus protocol, the target processor supporting a target instruction set and conforming to a target bus protocol, the method comprising: configuring first programmable resources of the PLD to implement a first bus interface unit, the first bus interface unit having a first port coupled to the dedicated processor and conforming to the first bus protocol, and further having a second port conforming to the target bus protocol; and executing in the dedicated processor an emulation program that emulates the target instruction set while executing instructions from the first instruction set, the emulation program interacting with the first bus interface unit via the first port, wherein the target instruction set is different from the first instruction set, and wherein the target bus protocol is different from the first bus protocol.