Patent ID: 8604548

Claim:
A semiconductor device, comprising: a substrate of a first conductivity type, comprising a first region and a second region; a first fin, disposed on the first region of the substrate, and comprising a first middle portion of the first conductivity type and two first end portions of a second conductivity type; a first gate, disposed on the substrate and covering the first middle portion of the first fin; a first doped region of the first conductivity type, configured in the first middle portion of the first fin and underlying the first gate, wherein the first doped region has an impurity concentration higher than an impurity concentration of the substrate; a second fin, disposed on the second region of the substrate, and comprising a second middle portion of the first conductivity type and two second end portions of the second conductivity type; a second gate, disposed on the substrate and covering the second middle portion of the second fin; and at least one second doped region of the first conductivity type or of the second conductivity type, configured in the second fin, wherein when the second doped region is of the first conductivity type, the second doped region is configured in the second middle portion of the second fin underlying the second gate, and has an impurity concentration substantially equal to or lower than the impurity concentration of the substrate, and when the second doped region is of the second conductivity type, the second doped region is configured in the two second end portions of the second fin adjoining the substrate, and has an impurity concentration lower than an impurity concentration of other parts of the two second end portions.