Patent ID: 7689821

Claim:
A processor comprising: an interface comprising a plurality of signal lines; and interface circuitry coupled to the interface and operative to receive clock signals for respective interface clock domains of the processor; said interface circuitry comprising a plurality of sampling registers; said sampling registers being associated with respective ones of the interface clock domains of the processor and being clocked by respective ones of the clock signals; said interface circuitry being configurable in a plurality of different configurations, each providing a different association between designated subsets of the signal lines and the clock domains of the processor; wherein in a first configuration of the plurality of configurations a given one of the signal lines is sampled using a first one of the clock signals having a first clock rate associated with a first one of the interface clock domains; wherein in a second configuration of the plurality of configurations the given one of the signal lines is sampled using a second one of the clock signals having a second clock rate associated with a second one of the interface clock domains, the second clock rate being different than the first clock rate; and wherein the signal lines in a first one of the subsets are each coupled to inputs of multiple ones of the sampling registers in a corresponding first group of the sampling registers.