Patent ID: 8335117

Claim:
A memory device comprising a first wire, a second wire, memory cells, driving control sections, sense amplifiers, and inhibit control sections, wherein: each of said memory cells includes a variable-resistance storage element recording a data storage state and an access transistor connected in series to said variable-resistance storage element between said first and second wires; each of said driving control sections applies a write pulse or an erase pulse between said first and second wires in a data write operation or a data erase operation respectively and consecutively executes a direct verify sub-operation by causing a cell current to flow between said first and second wires through said memory cell; each of said sense amplifiers senses an electric-potential change occurring on said first wire in accordance with control executed by said driving control sections on said direct verify sub-operation; and each of said inhibit control sections determines whether or not to inhibit a sense node of said sense amplifiers from electrically changing at the next sensing time on the basis of an electric potential appearing at said sense node at the present sensing time, wherein each of said inhibit control sections include: a latch circuit connected to said sense node of said sense amplifiers to serve as a latch circuit configured to store binary-value information having a binary value representing a voltage sensing result indicating a sufficient or insufficient transition of said data storage state; and a switch for executing control to connect said sense node of said sense amplifiers to said first wire or disconnect said sense node from said first wire in accordance with said binary-value information stored in said latch circuit, wherein: each of said sense amplifiers is used in both a normal read operation and said direct verify sub-operation; and each of said inhibit control sections has a latch-input control section connected between said sense node of said sense amplifiers and said latch circuit to serve as a latch-input control section which operates to allow said binary-value information stored in said latch circuit to be updated in accordance with a voltage appearing at said sense node in said direct verify sub-operation and inhibits said binary-value information stored in said latch circuit from being updated from a value corresponding to sustainment of a turned-on state of said switch in said normal read operation.