Patent ID: 8713083

Claim:
An apparatus for generating a delayed analog signal corresponding to processed digital data that has a user-controlled delay relative to an analog signal corresponding to source digital data, comprising: a first data generator for generating an n-bit stream of first the source digital data using a first clock; a clock processor structured to generate a modified clock from the first clock; a digital convolution processor having a data input for accepting the n-bit stream of the source digital data from the first data generator, having a first clock input for accepting the first clock, having a second clock input for accepting the modified clock, and the digital processor structured to generate, by a convolution function, a second n-bit stream of digital data at a frequency related to a ratio of the first clock and the modified clock; and a digital-to-analog converter accepting the second n-bit stream of second digital data and structured to generate the delayed analog signal from the second n-bit stream of second digital data that is related to the n-bit stream of first digital data.