Patent ID: 7577193

Claim:
An apparatus comprising: an equalizer; a phase detector including an input to receive from the equalizer an input signal with a plurality of consecutive data bits including a first data bit, a second data bit, and a third data bit, a clock input to receive a clock signal, a data output to provide an output signal based on the input signal and the clock signal, and a feedback output to provide a feedback information based on the input signal; and an equalization feedback loop to adjust the equalizer based on the feedback information to influence the output signal, wherein the equalization feedback loop includes an equalization adjustment circuit configured to adjust the equalizer in a first direction or a second direction based on a bit value of each of the first, second, and third data bits, and based on a bit value of a transition bit, and wherein the equalization adjustment circuit includes a decision controller configured to adjust the equalizer in the first direction to reduce jitter in the output signal when the bit value of the first data bit and the bit value of the second data bit are equal, when the bit value of the second data bit and the bit value of the third data bit are different, and when the bit value of the transition bit is equal to a first value.