Patent ID: 8564345

Claim:
A system, comprising: a digitally controllable delay line, including a plurality of first delay elements, each to provide a first amount of delay, and a plurality of second delay elements, each to provide a second amount of delay that is greater than the first amount of delay; and a digital controller including a first counter to enable a number n of the first delay elements and a second counter to enable a number m of the second delay elements, wherein the first and second counters are configured to perform base-P positional notation counting with n as a least significant count position and m as a most significant count position; wherein the digital controller is configured to calibrate n and m to control a delay of the delay line relative to a reference clock in increments of the first amount of delay; and wherein the digital controller includes a third counter to enable P first delay elements during a calibration of P, and is configured to increment the third counter during the calibration of P until a delay imparted to the reference clock by enabled first delay elements is equal to a delay imparted to the reference clock by one of the second delay elements.