Patent ID: 7853635

Claim:
A system for binary multiplication in a superscalar processor comprising: a first pipeline including: a first register; a second register; a third register; an execution unit including a bit logic unit and a binary adder in communication with the first register, the second register, and a first multiplexer; the first multiplexer also in communication with the third register; a first rotator in communication with the first register and the execution unit; and a leading zero detection register in communication with the execution unit and the second register; a second pipeline comprising: a fourth register; a fifth register; a sixth register; a second execution unit including another bit logic unit and another binary adder in communication with the fourth register, the fifth register, and a second multiplexer; the second multiplexer also in communication with the sixth register; a rotator in communication with the fourth register and the execution unit; and a leading zero detection register in communication with the second execution unit and the fifth register; a third pipeline comprising: a seventh register; an eighth register; a ninth register; a binary multiplier in communication with the seventh register and the eighth register; a general register for storage and retrieval of data; an operand buffer for obtaining a first operand and a second operand; and a communication bus for communication among at least two of the first pipeline, the second pipeline, the third pipeline, the general register and the operand buffer.