Patent ID: 8378346

Claim:
A semiconductor wafer configured for wafer level testing, comprising: a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges; separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other; a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group; interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line wherein said internal portion includes crossing connections coupled between respective pairs of the interconnection pads.