Patent ID: 8406702

Claim:
A clock signal generating arrangement for a communication device for generating a system clock signal at an output for use as a timing reference, the clock signal generating arrangement comprising: a reference clock generator for generating a reference clock signal; a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal; a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for a time accumulated error in the reference clock signal; and a clock signal selector coupled to the reference clock generator, the main clock generator and the clock adjust circuit, the clock signal selector to: when the communication device is in an idle mode of operation: provide the reference clock signal as the system clock signal until a time accumulated error in the reference clock signal reaches a first predetermined threshold, and provide the compensated reference clock signal as the system clock signal when the first predetermined threshold is reached and until the time accumulated error in the reference clock signal reaches a second predetermined threshold; and when the communication device is operating in an active mode, provide the main clock signal as the system clock signal.