Patent ID: 7463530

Claim:
An operating method of a memory cell, the operating method comprising: providing a memory cell, the memory cell comprising: a substrate, having two source/drain regions being separated by a channel region disposed under a surface of the substrate; an insulating layer, disposed on the channel region; a charge storage layer, disposed on the insulating layer; a multi-layer tunneling dielectric structure, disposed on the charge storage layer; and a gate, disposed on the multi-layer tunneling dielectric structure; performing a first operation, supplying a negative bias to the gate and setting the source/drain regions to be floating, grounded, or 0V, injecting electrons from the gate of the memory cell into the charge storage layer through the multi-layer tunneling dielectric structure by −FN tunneling so as to increase the threshold voltage of the memory cell; and performing a second operation, supplying a positive bias to the gate and setting the source/drain regions to be floating, grounded, or 0V, injecting holes from the gate of the memory cell to the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so as to decrease the threshold voltage of the memory cell.