Patent ID: 7615415

Claim:
A method of fabricating a vertical stack type multi-chip package comprising: mounting a first semiconductor chip on an organic substrate; performing a first wire bonding to connect a circuit pattern on the organic substrate with the first semiconductor chip using a first bonding wire; disposing a nonconductive encapsulant on the organic substrate to cover the first semiconductor chip and the first bonding wire; positioning a metal stiffener over the organic substrate, wherein the metal stiffener comprises a conductive post extending through the nonconductive encapsulant and contacting a solder bump disposed on the organic substrate and electrically connected to ground; applying heat to the metal stiffener to electrically connect the conductive post with the solder bump, and simultaneously harden the nonconductive encapsulant; after the conductive post is electrically connected to the solder bump and the nonconductive encapsulant is hardened, mounting a second semiconductor chip on the metal stiffener; sealing the first semiconductor chip, the metal stiffener, the second semiconductor chip, and the nonconductive encapsulant using a mold resin.