Patent ID: 8615694

Claim:
An integrated circuit interposer comprising: A. a substrate having a first side and an opposed second side; B. first functional input pads formed on the first side of the substrate; C. first functional output pads formed on the second side of the substrate and coupled to the first functional input pads; D. second functional input pads formed on the second side of the substrate; E. second functional output pads formed on the first side of the substrate and coupled to the second functional input pads; F. a test data input pad, a test clock input pad, a test mode select input pad, and a test data output pad formed on the first side of the substrate; G. a test access port controller, formed on the substrate, coupled to the test clock input pad and the test mode select input pad, and having a control output bus; and H. boundary register circuitry, formed on the substrate, having a control input connected to the control output bus of the test access port controller, and the boundary register circuitry selectively coupling the first functional input pads to the first functional output pads and selectively coupling the second functional input pads to the second functional output pads.