Patent ID: 7644339

Claim:
A decoder that is operable to perform overlapping sub-matrix based decoding of an LDPC (Low Density Parity Check) coded signal, the decoder comprising: a bit engine; a check engine; and wherein: during a first time, the bit engine is operable to update bit edge messages corresponding to a first sub-matrix of an LDPC matrix; during a second time: the check engine is operable to update check edge messages corresponding to the first sub-matrix of the LDPC matrix using the updated bit edge messages corresponding to the first sub-matrix; and the bit engine is operable to update bit edge messages corresponding to a second sub-matrix of the LDPC matrix; during a third time: the check engine is operable to update check edge messages corresponding to the second sub-matrix using the updated bit edge messages corresponding to the second sub-matrix; and the bit engine is operable to update bit edge messages corresponding to a third sub-matrix of the LDPC matrix; and the decoder is operable to employ most recently updated bit edge messages corresponding to at least one of the first sub-matrix, the second sub-matrix, and the third sub-matrix to make a best estimate of an information bit within the LDPC coded signal.