Patent ID: 7363468

Claim:
A method for a load address dependency mechanism in a high frequency, low power processor comprising an instruction unit and an execution unit, the method comprising: receiving, by the execution unit from the instruction unit, a load instruction corresponding to a memory address; wherein the execution unit comprises a miss queue and an instruction execution module (IEM); determining, by the execution unit, whether there is at least one unexecuted preceding instruction corresponding to the memory address in the IEM; in the event there is at least one unexecuted preceding instruction corresponding to the memory address in the IEM, indicating, by the execution unit to the instruction unit, a local cache miss corresponding to the load instruction; storing the load instruction in the miss queue; tagging the load instruction as a local miss; determining whether every one of the at least one unexecuted preceding instructions have been executed; and in the event every one of the at least one unexecuted preceding instructions have been executed, storing the load instruction in the IEM for execution.