Patent ID: 8717838

Claim:
A memory module comprising: at least a memory block that includes: a memory array having regular columns and at least one redundant column, the regular columns and the redundant column extending in a bit-line direction, and being ordered in a word-line direction; and a shift wrapper that interfaces between block inputs/outputs and the regular and redundant columns, the shift wrapper configured to shift a mapping between the block inputs/outputs and the regular and redundant columns to bypass a defective column that has at least one defective cell, and engage the redundant column, while maintaining the order in the word-line direction, and the shift wrapper including: a plurality of input switches respectively coupled to the regular and redundant columns, an input switch coupled to a non-defective column and configured to selectively couple a block input to the non-defective column, and a plurality of output switches respectively coupled to the block outputs, an output switch coupled to a block output and configured to selectively couple a non-defective column to the block output.