Patent ID: 8501553

Claim:
A method for manufacturing an array substrate comprising the following steps of: providing a substrate; forming a first conductive layer on the substrate, wherein the first conductive layer contains a molybdenum nitride; forming a second conductive layer on the first conductive layer, wherein the second conductive layer is an alloy layer, the alloy layer comprising a copper content of more than 95% by weight, and the alloy layer further comprises at least one of titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), neodymium (Nd), indium (In) or aluminum (Al); patterning the first and second conductive layers so as to form at least one gate line and gate electrode; forming a gate insulating layer on the gate line, gate electrode and the substrate; forming a first semiconductor layer on the gate insulating layer; forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer contains a N-type dopant; patterning the first and second semiconductor layers; and forming at least one source electrode and drain electrode on the patterned second semiconductor layer, and simultaneously forming at least one data line on the gate insulating layer.