Patent ID: 8198139

Claim:
A power device package comprising: a first substrate comprising a first surface and a second surface opposite to each other, and a first wiring pattern formed on the first surface; one or more power semiconductor chips mounted on the first surface of the first substrate and electrically connected to the first wiring pattern; a second substrate vertically spaced apart from the first substrate and comprising a second wiring pattern; one or more first control semiconductor chips mounted on the second substrate and electrically connected to the second wiring pattern; one or more insulating support members supporting the second substrate so that the second substrate is spaced apart from the first substrate, wherein each insulating support member is disposed between the first substrate and the second substrate and abuts each of the first substrate and the second substrate, and wherein each insulating support member is spaced apart from each of the one or more power semiconductor chips and each of the one or more first control semiconductor chips; a lead frame electrically connected to the first wiring pattern and the second wiring pattern; and a sealing member sealing the first substrate, the power semiconductor chips, the second substrate, the first control semiconductor chips, the one or more insulating support members, and at least a part of the lead frame so as to expose the second surface of the first substrate.