Patent ID: 8539596

Claim:
A method for hindering detection of information unintentionally leaked from a secret held in a memory unit, the method comprising: receiving a triggering event, the triggering event comprising one of: receiving a reset signal at one of: an integrated circuit comprising the memory unit; the memory unit; an element on an integrated circuit comprising the memory unit; a memory unit controller; and a memory unit interface; powering up of at least one of: an integrated circuit comprising the memory unit; the memory unit; an element on an integrated circuit comprising the memory unit; a memory unit controller; and a memory unit interface; and detecting at least one interface signal input to the memory unit; waiting for at least a first amount of time to pass after said receipt of the triggering event, the memory unit being in a non-operational state managed, at least, by lowering a voltage level applied to the memory unit during the at least a first amount of time; after the at least a first amount of time has passed, changing at least one first condition under which the memory unit operates, thereby causing the memory unit to enter an operational state; waiting for a second amount of time to pass after said changing at least one first condition; and changing, after said second amount of time, at least one second condition under which the memory unit operates, thereby causing the memory unit to enter the non-operational state, wherein access to said secret information is enabled only during said second amount of time, and detection of secret information unintentionally leaked is limited during said first amount of time.