Patent ID: 8450775

Claim:
A semiconductor device comprising: a substrate having a gate structure and sidewall spacers disposed adjacent to sidewalls of the gate structure; source/drain extension (SDE) regions disposed under the sidewall spacers; source/drain (S/D) recesses in a region of the substrate adjacent to the gate structure, wherein the S/D recesses each includes a first side adjacent to the gate structure and aligns with an outer edge of the sidewall spacer, a second side opposing the first side and a bottom below a bottom of the SDE regions, wherein the bottom and the first side adjacent to the gate structure of the S/D recesses form an angled corner; an epitaxial buffer layer lining the first side and bottom of the S/D recesses and includes a rounded corner over the angled corner; and a stressor layer in the S/D recesses with the rounded corner.