Patent ID: 7310262

Claim:
A storage device comprising: a ferroelectric memory cell array including a plurality of memory cells, each having a selection transistor connected to a bit line and selected and driven by a word line and a ferroelectric capacitor having a first electrode connected to the selection transistor and having a second electrode connected to a plate line and storing two values according to polarization states of a ferroelectric film; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part configured to control a data access, wherein the control part accesses the data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, with data being continuously input or output and transferred by repeatedly executing the second processing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing.