Patent ID: 7176491

Claim:
A semiconductor device comprising a semiconductor element having a semiconductor layer, an insulation film, and an electrode formed on a predetermined substrate, wherein said semiconductor element comprises a first element including a first impurity region formed at said semiconductor layer, and having a predetermined impurity concentration, a second impurity region formed at said semiconductor layer with a distance from said first impurity region, and having a predetermined impurity concentration, a channel region functioning as a channel having a predetermined channel length, formed at a region of said semiconductor layer between said first impurity region and said second impurity region with respective distances from said first impurity region and said second impurity region, a third impurity region formed in contact with said channel region at a region of said semiconductor layer between said first impurity region and said channel region, and having an impurity concentration lower than the impurity concentration of said first impurity region, and a fourth impurity region formed in contact with said channel region at a region of said semiconductor layer between said second impurity region and said channel region, and having an impurity concentration lower than the impurity concentration of said second impurity region, wherein, in said first element, said electrode has one side and another side opposite to each other, and is formed overlapping with and facing said channel region, a portion of said third impurity region, and a portion of said fourth impurity region, said insulation film is formed between said semiconductor layer and said electrode so as to come into contact with each of said semiconductor layer and said electrode, and a first length, in a direction of the channel length, of an overlapping region between said electrode and said third impurity region, starting from where a plane including said one side intersects said semiconductor layer up to said channel region, is set shorter than a second length, in the direction of the channel length, of an overlapping region between said electrode and said fourth impurity region, starting from where a plane including said another side intersects said semiconductor layer up to said channel region.