Patent ID: 7773185

Claim:
A thin film transistor (TFT) array panel, comprising: a substrate; an n−1th and an nth gate line formed on the substrate; a data line intersected with the n−1th gate line; a first TFT including at least a portion of the n−1th gate line; a second TFT including at least a portion of the n−1th gate line; a first sub pixel electrode electrically connected to the first TFT; a second sub pixel electrode electrically connected to the second TFT; a first source electrode overlapped with at least one portion of the nth gate line and electrically connected to the second sub pixel electrode; a first drain electrode overlapped with at least one portion of the nth gate line and facing the first source electrode; a second source electrode overlapped with at least one portion of the nth gate line; a second drain electrode facing the second source electrode; a third sub pixel electrode electrically connected to the second drain electrode; and a fourth sub pixel electrode capacitively coupled with the third sub pixel electrode.