Patent ID: 8026545

Claim:
An EEPROM comprising: a semiconductor layer of a first conductive type; a first insulating film formed on the semiconductor layer; an element isolation portion formed selectively in a top surface of the semiconductor layer and surrounding an active region; a first impurity region of a second conductive type formed in a top layer portion of the semiconductor layer in the active region; a second impurity region of the second conductive type formed at an interval from the first impurity region in a top layer portion of the semiconductor layer in the active region; a select gate formed on the first insulating film and opposing a region between the first impurity region and the second impurity region; a third impurity region of the second conductive type formed at an interval from the second impurity region in a top layer portion of the semiconductor layer in the active region; a first floating gate formed on the first insulating film and opposing a region between the second impurity region and the third impurity region; a second insulating film formed on the first floating gate; a first control gate formed on the second insulating film; a fourth impurity region of the second conductive type formed at an interval from the third impurity region in a top layer portion of the semiconductor layer in the active region; a second floating gate formed on the first insulating film and opposing a region between the third impurity region and the fourth impurity region; a third insulating film formed on the second floating gate; a second control gate formed on the third insulating film; a first tunnel window formed by decreasing a thickness of a part of a portion of the first insulating film in contact with the first floating gate; a fifth impurity region of the second conductive type formed in a portion of the top layer portion of the semiconductor layer opposing the first tunnel window and connected to the second impurity region; a second tunnel window formed by decreasing a thickness of a part of a portion of the first insulating film in contact with the second floating gate; and a sixth impurity region of the second conductive type formed in a portion of the top layer portion of the semiconductor layer opposing the second tunnel window and connected to the second impurity region.