Patent ID: 8010746

Claim:
A data processing apparatus for processing data by causing a plurality of function blocks to share a single shared memory, said data processing apparatus comprising: a memory controller configured to cause said plurality of function blocks to write and read data to/and from said shared memory in response to requests from any one of said function blocks; a cache memory; and a companding section configured to compress the data to be written to said cache memory while expanding the data read therefrom; wherein said memory controller checks to determine which of a plurality of areas in said shared memory a write and/or read request from any one of said function blocks corresponds to, if said write and/or read request from one of said function blocks is found corresponding to a cache area of said shared memory, then said memory controller causes the data to be written and/or read to and/or from said shared memory and said cache memory in such a manner that the data is subjected to a caching process involving the use of said cache memory, if said write and/or read request from one of said function blocks is found corresponding to a compressed cache area of said shared memory, then said memory controller causes the data to be written and/or read to and/or from said shared memory and said shared cache memory in such a manner that the data is compressed by said companding section before being subjected to a caching process involving the use of said cache memory, and if said write and/or read request from one of said function blocks is found corresponding to a non-cache area of said shared memory, then said memory controller stops the use of said cache memory while causing the data to be written and/or read to/and from said shared memory, if said write and/or read request from one of said function blocks is found corresponding to said cache area of said shared memory, then said memory controller under control of a host controller causes the data to be written and/or read to and/or from said shared memory and said cache memory in such a manner that said caching process is stopped or that the data is compressed by said companding section before being subjected to said caching process involving the use of said cache memory; and/or if said write and/or read request from one of said function blocks is found corresponding to said compressed cache area of said shared memory, then said memory controller under control of said host controller causes the data to be written and/or read to and/or from said shared memory and said shared cache memory in such a manner that the data is not compressed by said companding section before being subjected to said caching process or that the use of said cache memory is stopped.