Patent ID: 8242850

Claim:
A frequency synthesizer comprising: an input for receiving a clock reference signal at a first input frequency; a multi-modulus divider for dividing the input frequency to provide an intermediate signal with an adjusted frequency; a numerically controlled oscillator comprising an accumulator receiving an accumulator increment value for providing a phase value and a latch circuit that receives and is clocked by the intermediate signal with the adjusted frequency wherein the numerically controlled oscillator outputs a delay value and an overflow signal each comprised of one or more bits wherein said overflow signal is provided to said multi-modulus divider to select between at least a first divider ratio and a second divider ratio; a pseudo-random noise generator that generates a pseudo-random sequence for input into the accumulator wherein the pseudo-random noise generator is a zero-mean pseudo-random noise generator or a non-zero-mean pseudo-random noise generator; and a programmable delay generator comprising a delay control circuit that receives at least said overflow value and said delay value and calculates a delay time for application to each pulse in the intermediate signal with the adjusted frequency to provide an output signal with a final adjusted frequency (f out ).