Patent ID: 7323911

Claim:
A differential sense amplifier comprising: a switch circuit having a transistor (M 3 ) with a first conduction terminal, a control terminal, and a second conduction terminal and a transistor (M 4 ) having a first conduction terminal, a control terminal, and a second conduction terminal, the control terminal of the M 3 transistor connected to the control terminal of the M 4 transistor; a clock signal connected between the control terminal of the M 3 transistor and the control terminal of the M 4 transistor, the clock signal having a first signal level and a second signal level, the differential sense amplifier configuring as a preamplifier when the clock signal is set to the first signal level, the differential sense amplifier configuring as a latch circuit when the clock signal is set to the second signal level; a first resistive element coupling the first conduction terminal of the M 3 transistor to a first bias voltage; a second resistive element coupling the first conduction terminal of the M 4 transistor to the first bias voltage; and a latch circuit including: a transistor (M 7 ) having a first conduction terminal, a gate terminal and a second conduction terminal, the first conduction terminal of the M 7 transistor connected to the first bias voltage; and a transistor (M 8 ) having a first conduction terminal, a gate terminal and a second conduction terminal, the first conduction terminal of the M 8 transistor connected to the first bias voltage, the gate terminal of the M 8 transistor directly connected to the second conduction terminal of the M 4 transistor and the second conduction terminal of the M 7 transistor, the second terminal of the M 8 transistor directly connected to the second conduction terminal of the M 3 transistor and the gate terminal of the M 7 transistor.