Patent ID: 7330062

Claim:
A semiconductor chip comprising: a first unit coupled to receive at least a first input clock signal and a second input clock signal, and output a first output clock signal; a second unit coupled to receive the first input clock signal and the second input clock signal, and output a second output clock signal that has periodically the first logic level and the second logic level; a first transfer gate which receives a first data, and transmits the first data to a data bus in response to a first logic level of the first output clock signal; a second transfer gate which receives a second data, and transmits the second data to the data bus in response to the first logic level of the second output clock signal; wherein the first unit changes the first output clock signal from a second logic level to the first logic level when a change of the first input clock signal from the second logic level to the first logic level is detected, and the second unit changes the second output clock signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.