Patent ID: 7734894

Claim:
An integrated circuit, comprising: a plurality of tiles, each tile comprising a processor configured to issue multiple instructions in the same clock cycle, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and at least a first tile further comprises a protected resource, a first memory associated with the protected resource storing a value representing a minimum protection level authorized to access the protected resource, and a second memory associated with the portion of the first tile configured to access the protected resource storing a value representing a current protection level associated with the portion of the first tile configured to access the protected resource, and the first tile is configured to generate a fault if a portion of the first tile configured to access the protected resource is associated with a protection level different from one or more protection levels authorized to access the protected resource, with the processor in the first tile configured to delay committing data associated with a first instruction or a subsequent instruction to the switch of the first tile until an operation accessing the protected resource associated with the first instruction or a previous instruction is determined to be executable without generating a fault in response to accessing the protected resource, with the first memory configured to replace an old value stored in the first memory with a new value provided by a process running on the processor in the first tile, with the process running on the processor in the first tile configured to provide a new value that represents a new minimum protection level less than or equal to the current protection level stored in the second memory if the current protection level stored in the second memory is greater than or equal to the old minimum protection level represented by the old value stored in the first memory, and with the first tile configured to generate an interrupt if the process running on the processor in the first tile attempts to provide a new value that represents a new minimum protection level greater than the current protection level stored in the second memory.