Patent ID: 8413086

Claim:
A method for synthesis of an adaptable logic function, the method comprising: selecting from an HDL library a first hardware description language (HDL) module (Module1) with a first propagation delay parameter; selecting from the HDL library a second HDL module (Module2) with a buffer propagation delay parameter; replacing the first propagation delay parameter of Module1 with a second propagation delay parameter set to equalize a difference between worst case timing path delays of a first class instruction execution path and a second class instruction execution path, and wherein said replacing accounts for the buffer propagation delay parameter of Module2; instantiating Module1 in the first class instruction execution path to create a first execution path; instantiating Module2 in the second class instruction execution path to create a second execution path; and synthesizing the adaptable logic function using a computer to generate synthesized logic with a period of a clock of the adaptable logic function set to a worst case timing path delay of the second execution path, wherein worst case timing path delays are determined from a worst case timing path analysis.