Patent ID: 7187618

Claim:
A data communication circuit of a synchronous dynamic random access memory (SDRAM), wherein, the SDRAM comprises a plurality of data pins, for receiving or outputting a data, and the SDRAM further comprises an upper data mask (UDQM) pin and a lower data mask (LDQM) pin, the data communication circuit comprising: a data input circuit, coupled to the data pins through a plurality of data lines, a number of the data lines is less than a number of the data pins, wherein the data input circuit receives a first part of the data from a part of the data pins during a period of a preset clock signal and the data pins receives a second part of the data from another part of the data pins during a next period of the preset clock signal; a data output circuit, coupled to the data pins through the data lines, for the data output circuit outputting the first part of the data to the part of the data pins during the period of the preset clock signal, and outputting the second part of the data to another part of the data pins during the next period of the preset clock signal; and a mask signal generating circuit, coupled to the UDQM pin and the LDQM pin, for enabling the UDQM pin or the LDQM pin depending upon whether the data output circuit outputs/receives the first part or the second part of the data.