Patent ID: 7638359

Claim:
A method for manufacturing a memory cell, comprising: forming a lower layer of dielectric material on a substrate; forming an upper layer of dielectric material on the lower layer; forming an opening through the upper and lower layers to expose a surface of the substrate, the opening comprising a first, upper opening segment formed within the upper layer, a second, lower opening segment formed within the lower layer, the first and second opening segments having first and second widths, the upper layer having an overhanging portion extending into the opening so that the first width is less than the second width; depositing a fill material by a process in the opening, causing formation of a void centered within the opening, and having a width determined by the difference between the first and second widths; anisotropically etching the fill material to open the void and then continuing to anisotropically etch the fill material to expose the substrate in an area having a width substantially equal to the width of the void, and stopping the etching to leave a sidewall of fill material on the sides of the opening in the second opening segment; forming an electrode aligned with the sidewall of fill material; and forming a layer of programmable resistive material on the electrode.