Patent ID: 8513105

Claim:
A method of fabricating an integrated circuit at a semiconducting surface of a body, comprising: forming a plurality of isolation structures at the surface to define first and second active regions of a first conductivity type at the surface, the first and second active regions separated from one another by a first isolation structure; forming a plurality of gate level structures comprising a plurality of gate electrodes disposed parallel to one another at locations overlying the first and second active regions, and disposed at substantially a constant pitch relative to one another; forming a first mask layer over the surface, the first mask layer exposing the first active region at the location of a first gate electrode nearest the first isolation structure, and covering at least a portion of the second active region, the first mask layer having a thickness below a maximum height; implanting dopant ions into the first active region at an angle from the vertical less than a maximum angle; and then removing the first mask layer; wherein the first gate electrode is parallel to a second gate electrode overlying the second active region at a location nearest the first isolation structure, and said plurality of gate structures further comprises a single gate structure disposed overlying the first isolation structure between the first and second active regions, so that the first gate electrode is the nearest gate electrode in the first active area to the single gate structure overlying the first isolation structure, and the second gate electrode is the nearest gate electrode in the second active area to the single gate structure overlying the first isolation structure, and the single gate structure overlying the first isolation structure is at substantially the constant pitch relative to the first gate electrode and the second gate electrode.