Patent ID: 6970362

Claim:
An interposer to couple a die to a substrate and comprising: a plurality of power and ground vias in a core region of the interposer; a plurality of signal vias in a peripheral region of the interposer; an embedded capacitor having first and second terminals; a first surface including a first plurality of power lands coupled to the first terminal through first ones of the plurality of power vias, and a first plurality of ground lands coupled to the second terminal through first ones of the plurality of ground vias; and a second surface including a second plurality of power lands coupled to the first terminal through second ones of the plurality of power vias, and a second plurality of ground lands coupled to the second terminal through second ones of the plurality of ground vias; wherein the first plurality of power lands and the first plurality of ground lands are positioned to be coupled to corresponding power and ground nodes of the die through controlled collapse chip connect solder bumps; wherein the first surface comprises a first plurality of signal lands coupled to the plurality of signal vias and positioned to be coupled to corresponding signal nodes of the die; and wherein the second surface comprises a second plurality of signal lands coupled to the plurality of signal vias and positioned to be coupled to corresponding signal nodes of the substrate.