Patent ID: 7505303

Claim:
A method for disturbing a first tri-gate structure in an erased condition while a second tri-gate structure remains programmed in a non-volatile SRAM cell having a volatile portion and a non-volatile portion, each tri-gate structure in said non-volatile portion having a recall transistor, a store transistor and a SONOS transistor, said volatile portion having an SRAM cell comprising a word line, a node supplying power to said SRAM cell and a bit line pair with a first bit line and a second bit line, said method comprising: erasing said first and second SONOS transistors associated with said non-volatile portion of said SRAM cell; programming said first and second SONOS transistors so that said first tri-gate having said first SONOS transistor is configured in an erased condition and said second tri-gate structure having said second SONOS transistor is configured in a programmed condition; isolating said volatile portion from said non-volatile portion by turning off a first store transistor in said first tri-gate structure and turning off a second store transistor in said second tri-gate structure; applying a programming pulse and a programming voltage to said first and second SONOS transistors in said first and second tri-gate structures; applying a voltage to each recall transistor in said first and second tri-gate structure sufficient to turn each recall transistor on; and ramping a supply voltage to said first and second tri-gate structure from a first voltage to approximately ground, wherein said second tri-gate structure remains in said programmed condition and wherein said first tri-gate structure transition from said erased condition to a programmed condition.