Patent ID: 7047434

Claim:
A data transfer control device for performing data transfer over a bus by using a first transfer mode which is high-speed mode or a second transfer mode which is low-speed mode, the data transfer control device comprising: a clock generation circuit comprising a first PLL (phase locked loop)which generates a first clock and a second PLL which generates a second clock; and a clock control circuit which controls the first and second PLLs comprised within the clock generation circuit, wherein the clock control circuit disables autonomous operation of the first PLL, which generates the first clock used for the first transfer mode when the transfer mode has been switched from the first transfer mode to the second transfer mode; wherein the data transfer control device detects whether or not a port connected to a bus supports the first transfer mode, in a state of operation in accordance with the first clock generated by the first PLL, and, when the data transfer control device detects that the first transfer mode is not supported by the port, the clock control circuit disables autonomous operation of the first PLL based on a selection signal from a later-stage data processing circuit; and wherein the clock control circuit disables autonomous operation of the first PLL at a timing between a first timing at which the data transfer control device can not detect a chirp from the port connected to the bus and a second timing at which data transfer control device starts transferring packets through the bus after an end of reset sequence.