Patent ID: 8867286

Claim:
A repairable multi-layer memory chip stack, comprising: a plurality of memory chips, coupled to an address bus and a data bus, and each of the memory chips comprising: a control unit, receiving an identification (ID) code to correspondingly generate an activation signal; a decoding unit, coupled to the address bus for receiving a memory address, and generating a decoded address and a decoded redundant address; a memory array module, coupled to the decoding unit for receiving the decoded address, and coupled to the control unit for receiving the activation signal, wherein the memory array module determines whether to allow the data bus to access data in the memory array module corresponding the memory address according to the activation signal and the decoded address; and a redundant repair unit, coupled to the decoding unit, wherein the redundant repair unit comprises at least one set of a redundant repair element, and each set of the redundant repair element comprises a valid field, a chip ID field, a faulty address field and a redundant memory, the redundant memory of one set of redundant repair elements in the redundant repair unit is coupled to the data bus when value of the valid field of the redundant repair element is a valid state, value of the chip ID field of the redundant repair element matches the ID code, and value of the faulty address field of the redundant repair element matches the memory address.