Patent ID: 7062005

Claim:
A system for synchronising slave and master timing, comprising: a phase adjust circuit for receiving and delaying an arbitrary clock signal by an adjustable amount and outputting a delayed clock signal related to said slave timing; and a master phase detector and lock circuit for comparing relative phases of said master and slave timing and in response generating and applying delay adjust signals to said phase adjust circuit at a dynamically adjusted rate which is related to said relative phases in order to synchronise said slave and master timing and is thereafter reduced to a minimum rate required to maintain synchronisation of said slave and master timing; wherein said master phase detector includes circuitry for generating said delay adjust signals in the form of up count signals for incrementally increasing said adjustable amount of delay in the event said slave timing leads said master timing, and down count signals for incrementally decreasing said adjustable amount of delay in the event said slave timing lags said master timing.