Patent ID: 7209405

Claim:
A memory system, comprising: a memory controller having a plurality of output terminals and a plurality of input terminals; at least one memory device having a plurality of output terminals and a plurality of input terminals, the at least one memory device comprising: a plurality of banks of memory cells operable to store write data responsive to a write command and output read data responsive to a read command; at least one pair of internal write data buses each of which couples the input terminals of the memory device to each of the banks of memory cells; at least one pair of internal read data buses each of which couples the output terminals of the memory device to each of the banks of memory cells, the internal read data buses being isolated from the internal write data buses; a write data selection circuit coupled to the internal write data buses and each of the banks, the write data selection circuit being operable to selectively couple each of the internal write data buses to any of the banks; a read data selection circuit coupled to the internal read data buses and each of the banks, the read data selection circuit being operable to selectively couple any of the banks to each of the internal read data buses; an addressing circuit operable to select one of the banks for a read or write memory access and to select a row and column of memory cells in the selected bank; and a command decoder operable to receive and decode memory commands and to generate control signals corresponding to the memory commands, at least some of the control signals controlling with write data selection circuit to cause write data to be coupled from the input terminals of the memory device to a selected bank through either of the internal write data buses and at least some of the control signals controlling the read data selection circuit to cause read data to be coupled from a selected bank to the input terminals of the memory device through either of the internal read data buses; a downstream bus coupling the output terminals of the memory controller to the input terminals of the memory device, the downstream bus being isolated from the input terminals of the memory controller and the output terminals of the memory device; and an upstream bus coupling the output terminals of the memory device to the input terminals of the memory controller, the upstream bus being isolated from the output terminals of the memory controller and the input terminals of the memory device.