Patent ID: 8775995

Claim:
A method of a chip-level implementation process, comprising: filling un-wired tracks of each core logic in a chip with grounded metal; filling un-wired tracks of a chip-level routing layer adjacent to an outermost layer of the each core logic with the grounded metal in a direction orthogonal to a preferred direction of the un-wired tracks in the outermost layer of the each core logic; constraining the grounded metal of the chip-level routing layer to be within a planar area of a core window along the chip-level routing layer that exactly corresponds in size to a planar area along the outermost layer of the each core logic comprising the grounded metal thereof; and generating, through a processor, a core timing model of the each core logic in the chip following the filling of the un-wired tracks of the each core logic and the un-wired tracks of the chip-level routing layer and the constraining of the grounded metal of the chip-level routing layer.