Patent ID: 8390347

Claim:
A phase locked loop for generating an oscillator signal, comprising: a phase to digital converter for receiving a reference clock and a feedback clock, and generating a digital output signal of a phase difference between the reference clock and the feedback clock, wherein the phase to digital converter operates on a first edge of the reference clock, and wherein the phase difference digital output signal includes a sign bit and a magnitude portion; a digital filter, connected to the phase to digital converter, for receiving the phase difference digital output signal and generating an oscillator control signal, wherein the digital filter operates on a second edge of the reference clock that is different from the first edge; a controlled oscillator, connected to the digital filter, for generating the oscillator signal, wherein a frequency of the oscillator signal is controlled using the oscillator control signal; and a loop divider, connected to the controlled oscillator, for receiving and dividing the oscillator signal to generate the feedback clock, wherein the phase to digital converter provides the phase difference digital output signal in a single clock period of the reference clock, and wherein the phase to digital converter comprises: a phase frequency detector (PFD) for determining the sign bit, wherein the PFD comprises: a shorter reset pulse circuit including: a first latch for generating an UP_SIGN signal, a second latch for generating a DOWN_SIGN signal, a third latch that receives the UP_SIGN signal and the DOWN_SIGN signal and generates the sign bit, and a first logic gate that receives the UP_SIGN signal and the DOWN_SIGN signal and generates a first latch reset signal that is provided to the reset inputs of the first and second latches; and a longer reset pulse circuit including: a fourth latch for generating an UP signal, a fifth latch for generating a DOWN signal, a second logic gate that receives the UP signal and the DOWN signal, a first plurality of series connected buffers, the first buffer of the series connected to an output of the second logic gate, and the last buffer of the series connected buffers generating a second latch reset signal that is provided to the reset inputs of the fourth and fifth latches, a first NOT gate having an input connected to the output of the second logic gate and generating a latch coarse counter signal, and a second NOT gate having an input connected to the output of the last buffer of the first plurality of series connected buffers and generating a latch count signal; and a time to digital converter (TDC) for generating the magnitude portion of the phase difference digital output signal.