Patent ID: 6872996

Claim:
A memory array, comprising: a plurality of stacked cells, each cell including: a MOS transistor formed in an active region of a substrate of semiconductor material, the MOS transistor having first and second conduction regions and a control electrode; a capacitor formed directly above the first conduction region of the MOS transistor of the cell and having first and second plates separated by a dielectric material region; and an electrical connector contacting a bottom of said first plate of the capacitor of the cell and connecting said first conductive region of the MOS transistor of the cell to said first plate of the capacitor of the cell; a plurality of bit lines connected to said second conductive regions of said MOS transistors of respective cells of the plurality of stacked cells; a plurality of word lines connected to said control electrodes of respective said MOS transistors of the plurality of stacked cells; a plurality of plate lines connected to said second plate of respective said capacitors, said plate lines running perpendicular to said bit lines and parallel to said word lines; wherein a pair of cells adjacent to each other in a direction parallel to said bit lines share a same dielectric material region and a same third conductive region, forming said second plates of said capacitors of said pair of cells.