Patent ID: 6937081

Claim:
A delay producing method which uses first-stage to N th stage delay elements connected in series to each other and which, when a clock signal is inputted to a first delay stage node of said first-stage delay element, said delay producing method produces the clock signal through the first delay stage node and delayed signals outputted through second to (N+1) th delay stage nodes of the second through the N th delay elements, respectively, said delay producing method for producing an even clock signal and an odd clock signal comprising: using a first-stage selector and second-stage to (N+1) th stage selectors arranged in one-to-one correspondence with said first delay stage node to (N+1) th delay stage nodes, and each of the first through the (N+1) th stage selectors outputting one selected from two inputs; using, as one of inputs given to each of said first-stage selector to (N+1) th stage selector, an input given to a corresponding one of said first delay stage node to the (N+1) th delay stage nodes; using, as the other of inputs given to each of said first-stage selector and the second-stage to (N+1) th stage selectors, an output from (n+2) th one of the third through (N+1) stage selectors, where n is a variable between 1 and (N−1): outputting said even clock signal from said first-stage selector; and outputting said odd clock signal from said second-stage selector.