Patent ID: 8645631

Claim:
A microprocessor, comprising: a first-level cache memory; a second-level cache memory; and a data prefetcher, configured to: maintain a largest address and a smallest address, wherein the largest address specifies a highest address within a memory block of memory accesses presented to the second-level cache memory, wherein the smallest address specifies a lowest address within the memory block of the memory accesses; maintain a count of changes to the largest address at a count of changes to the smallest address, wherein when the control logic changes the largest address the control logic updates the count of changes to the largest address, wherein when the control logic changes the smallest address the control logic updates the count of changes to the smallest address; detect a predominant direction and pattern of the memory accesses presented to the second-level cache memory and prefetch cache lines into the second-level cache memory based on the predominant direction and pattern, wherein the predominant direction is detected on the counts; receive from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line; determine one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction; and cause the one or more cache lines to be prefetched into the first-level cache memory.