Patent ID: 8352706

Claim:
A memory system managing address translation table, the memory system comprising: a volatile first storing unit; a nonvolatile second storing unit; and a controller configured to perform data transfer between a host apparatus and the second storing unit, wherein the first storing unit is capable of storing a master table that includes: a first address translation table for managing forward lookup information that correlates a logical address specified from the host apparatus with a storing position in the second storing unit, and a second address translation table for managing reverse lookup information that correlates the storing position in the second storing unit with the logical address specified from the host apparatus, and the controller includes a log control unit configured to, when an event occurs so that themaster table needs to be updated, store difference information before and after update of any one of the first address translation table and the second address translation table as a log in the first storing unit, a log reflecting unit configured to, when a first condition is satisfied, store the log stored in the first storing unit in the second storing unit and incorporate the log stored in the first storing unit into the master table to update both of the first address translation table and the second address translation table, and a read and write control unit configured to control the data transfer by using the log stored in the first storing unit and the master table.