Patent ID: 7577833

Claim:
An IPSec Core for executing IPSec processing, which comprises: an Encryption Engine for encrypting part of formed packet data for outbound service or decrypting part of decapsulated packet data for the inbound service; an Authentication Engine for authenticating the packet data or the processed packet data; a Device unit for providing miscellaneous calculations to process the packet data or the processed packet data; two modules, each of the module comprising: a buffer for storing the packet data or the processed packet data; a BUS for transferring the packet data or the processed packet data in the IPSec Core; a multiplexer for selecting path for the packet data or the processed data to be transferred into the buffer from the Encryption Engine, the Authentication Engine, the Device unit, the buffer or the external source; an Output FIFO for outputting the processed packet data; and a Control Unit for controlling the IPSec processes, wherein the Control Unit further comprises: two sequence controllers for controlling at least one processing sequence of the packet data or the processed packet data; an Input controller for controlling the packet data, the processed packet data or the SA data being inputted to the IPSec Core; a Pre_Operation controller for forming an IPSec Packet, part of that packet is used for crypto operation including the encryption, the authentication, or both the encryption and the authentication; an Encryption controller for controlling the packet data or the processed packet data transferring to/from the Encryption Engine; an Authentication controller for controlling the packet data or the processed packet data transferring to/from the Authentication Engine; a Post_Operation controller for dealing with the processed packet data after the crypto operation; and an Output controller for outputting the processed packet data.