Patent ID: 8154927

Claim:
A nonvolatile memory device comprising: a memory cell array comprising a first dummy memory cell connected to a first dummy wordline, a second dummy memory cell connected to a second dummy wordline, a NAND string comprising a plurality of memory cells connected in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell, a plurality of wordlines connected to the plurality of memory cells, a string selection line connected to the string selection transistor, and a ground selection line connected to the ground selection transistor; a row selection circuit coupled to the memory cell array through the string selection line, the ground selection line and the plurality of wordlines, and configured to provide wordline voltages to the plurality of wordlines based on an address signal; and a voltage generator configured to generate the wordline voltages; wherein, during a read-out operation mode of the nonvolatile memory device, a first dummy read-out voltage is applied to the first dummy wordline, a second dummy read-out voltage is applied to the second dummy wordline, and a read-out voltage is applied to unselected wordlines connected to unselected memory cells in the NAND string, the first and second dummy read-out voltages having respective first and second voltage levels and the read-out voltage having a third voltage level greater than the first and second voltage levels.