Patent ID: 7471553

Claim:
A phase change memory device, comprising: a memory cell comprising a phase change material; a write driver adapted to supply a program current to the memory cell during a programming interval; and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval, wherein the pump circuit is activated prior to the programming interval in response to an external control signal, wherein the pump circuit comprises an auxiliary pump which is activated prior to the programming interval, a main pump which is activated during the programming interval, and a pump controller adapted to control activation of the auxiliary pump and the main pump in response to the external control signal, wherein both the auxiliary pump and the main pump are activated during the programming interval, wherein the external control signal comprises a write enable signal and a chip enable signal, wherein the pump controller activates the auxiliary pump in response to enablement of the write enable signal, and activates the main pump in response to enablement of the chip enable signal, wherein the pump controller comprises a first pulse generating circuit adapted to generate a first pulse signal in response to enablement of the write enable signal, a second pulse generating circuit adapted to generate a second pulse signal in response to enablement of the chip enable signal, a first latch circuit adapted to activate the auxiliary pump in response to the first pulse signal, and a second latch circuit adapted to activate the main pump in response to the second pulse signal, wherein the pump controller further includes a third pulse generating circuit adapted to generate a third pulse signal in response to enablement of the write enable signal, and wherein the first and second latch circuits deactivate the main pump and the auxiliary pump in response to the third pulse signal.