Patent ID: 7371635

Claim:
A method of manufacturing a semiconductor device comprising: forming a transistor having a source region, a drain region, and a control electrode; covering said transistor with a first insulating layer; forming first through third openings in said first insulating layer to expose respectively said source region, said drain region, and said control electrode; burying respectively first through third conductive materials in said first through third openings; forming a ferroelectric capacitor by laminating a first electrode, a ferroelectric film, and a second electrode on said first insulating layer; covering said ferroelectric capacitor with a second insulating layer; forming a moisture diffusion protective film on said second insulating layer; forming a fourth opening to expose said third conductive material through said second insulating layer and said moisture diffusion protective film; forming a fifth opening to expose said second electrode of the ferroelectric capacitor through said second insulating layer and said moisture diffusion protective film; and forming a first wiring layer on said moisture diffusion protective film, the first wiring layer having an electrical connection with said control electrode through said fourth opening and via said third conductive material and having an electrical connection with said second electrode of the ferroelectric capacitor through said fifth opening, wherein said forming the first wiring layer occurs after said forming the moisture diffusion protective film.