Patent ID: 8117581

Claim:
An integrated circuit comprising: a power grid channel formed between at least two power grids; a plurality of dcaps including a first dcap included in a dcap cell, the dcap cell including built-in power tracks, each one of the built-in power tracks being connected to a corresponding one of the at least two power grids, wherein the built-in power tracks are formed in an adjacent metal layer to the metal layer including the power grids, and wherein the built-in power tracks are formed in an m1 metal layer of the integrated circuit and the power grids are formed in an m2 metal layer of the integrated circuit; and a plurality of dcap-eligible areas, each of the dcap-eligible areas including a plurality of rows, each one of the plurality of rows having a height substantially equal to a height of the dcap cell and wherein each one of the plurality of rows is divided into a plurality of equal shaped areas having a shape substantially equal to a shape of the dcap cell, wherein at least a portion of the plurality of dcaps are located within the power grid channel.