Patent ID: 7283943

Claim:
A method of generating circuit cell models for powergrid analysis, the method comprising: obtaining a first model of a circuit cell to be modeled for semiconductor powergrid analysis, the first model including: a plurality of ports; one or more transistors; and a resistive-capacitive (RC) network having a plurality of internal nodes, the RC network being coupled to the plurality of ports and the one or more transistors; determining respective first capacitance distribution coefficients for respective internal nodes of the plurality of internal nodes, each first capacitance distribution coefficient associating a portion of a capacitance value at a corresponding internal node with a first port of the plurality of ports; back-calculating the voltage at the respective internal nodes based, at least in part, on the respective capacitance distribution coefficients; modeling a resistance of the RC network as a resistive network; modeling the capacitance of the RC network as a plurality of capacitors, each capacitor coupled to a corresponding port of the plurality of ports, wherein the value of the modeled capacitor coupled to the first port is determined by the sum of the capacitance value portions associated with the first port; and providing a powergrid analysis for the circuit cell.