Patent ID: 8729545

Claim:
A semiconductor device comprising: a first memory cell comprising: a first transistor; a second transistor; and a first capacitor comprising one electrode electrically connected to one of a source and a drain of the first transistor and a gate of the second transistor; a second memory cell comprising: a third transistor; a fourth transistor; and a second capacitor comprising an electrode electrically connected to one of a source and a drain of the third transistor and a gate of the fourth transistor; and a circuit, wherein: the first transistor comprises a semiconductor layer containing an oxide semiconductor; the third transistor comprises a semiconductor layer containing an oxide semiconductor; a gate of the first transistor and a gate of the third transistor are electrically connected to a first line; the other electrode of the first capacitor is electrically connected to a second line; the other electrode of the second capacitor is electrically connected to a third line; one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor; and the other of the source and the drain of the fourth transistor is electrically connected to the circuit.