Patent ID: 8593314

Claim:
An A/D conversion circuit comprising: a comparison unit which performs a comparison operation in successive approximation; and a control circuit which has a successive approximation register storing successive approximation data updated by the successive approximation, wherein the control circuit outputs correction data for correcting non-linearity between an input signal and output data of the A/D conversion circuit to the comparison unit, based on one or plural bits of the successive approximation data, and the comparison unit corrects the non-linearity based on the correction data, and wherein the comparison unit includes: a main D/A conversion circuit which performs D/A conversion of the successive approximation data and outputs a main D/A output signal corresponding to the successive approximation data, and a sub D/A conversion circuit which corrects non-linearity between the successive approximation data and the main D/A output signal, based on the correction data from the control circuit, a comparison circuit with an input terminal thereof connected to a first node, the main D/A conversion circuit includes: a first capacitor provided between the first node and a second node, a first D/A conversion circuit which is connected to the first node and performs D/A conversion based on high-order bits of the successive approximation data, and a second D/A conversion circuit which is connected to the second node and performs D/A conversion based on low-order bits of the successive approximation data, and the sub D/A conversion circuit includes: a second capacitor provided between the first node and a third node, and a trimming D/A conversion circuit which is connected to the third node and performs D/A conversion of the correction data based on one or plural bits of the low-order bits.