Patent ID: 8692592

Claim:
An apparatus comprising: a plurality of clock input ports that are each adapted to receive at least one of a plurality of clock signals; a scan input port adapted to receive scan data signals; data input ports adapted to receive functional data signals; and an enable signal port adapted to receive an enable signal; a pass gate enable signal port that is adapted to receive a pass gate enable signal; a multiplexer including: a first inverter that is coupled to at least one of the data input ports; a second inverter that is coupled to at least one of the data input ports; a first pass gate that is coupled to the first inverter; a second pass gate that is coupled to the second inverter; and a NOR gate that is coupled to the pass gate enable port, the enable port, and at least one of the clock input ports so as to activate or deactivate at least one of the first or second pass gates; a third inverter that is coupled to the scan input port; and a third pass gate that is coupled to the third inverter, at least one of the clock input ports, the first pass gate, and the second pass gate.