Patent ID: 7435636

Claim:
A method for fabricating a gallium arsenide MOSFET device, the method comprising: forming a dummy gate over a gallium arsenide substrate; implanting source-drain extensions into the substrate adjacent the dummy gate; forming dummy oxide spacers along the sidewalls of the dummy gate and over a portion of the source-drain extensions; implanting and annealing source-drain regions adjacent the source-drain extensions; forming insulating spacers on the sides of the dummy oxide spacers; defining the source-drain regions with a photoresist layer; forming a conductive layer over the photoresist layer; lifting off the photoresist layer and annealing the conductive layer to form contacts to the source-drain regions; removing the dummy gate and the dummy oxide spacers to form a gate opening; depositing in-situ a passivation layer in the gate opening; oxidizing the surface of the passivation layer to create an oxide layer; depositing ex-situ a dielectric layer over the oxide layer; and depositing a gate metal over the dielectric layer to form a gate stack in the gate opening.