Patent ID: 6928073

Claim:
An integrated circuit comprising: a. plurality of functional modules formed within said integrated circuit interconnected via a packet router formed within said integrated circuit, each functional module having packet handling circuitry for generating and receiving packets conveyed by the packet router; wherein at least a first set of said functional modules, acting as initiator modules, have packet handling circuitry which includes request packet generation circuitry for generating request packets for implementing transactions, each request packet including a destination indicator identifying a destination of the packet and an operation field denoting the function to be implemented by the request packet, wherein the operation field comprises eight bits of which a single packet type bit denotes the type of the packet, four operation family bits denote the unction to be implemented by the packet and three operation qualifier bits act to qualify the function, and wherein a second set of the functional modules, acting as target modules, each have packet handling circuitry which includes packet receiver logic for receiving said request packets and for generating respective response packets, wherein the single packet type bit distinguishes between request packets and response packets.