Patent ID: 7414258

Claim:
A memory device, comprising: a first pan-shaped electrode having a first side wall structure with a top side and a width at the top side; a second pan-shaped electrode having a second side wall structure with a top side and a width at the top side; an insulating wall between the first side wall structure and the second side wall structure, the insulating wall having a thickness between the first and second side wall structures near the top side of the first side wall structure and the top side of the second side wall structure; and a bridge across the insulating wall, the top side of the first side wall structure, and the top side of the second side wall structure, the bridge having a first side and a second side and contacting the top sides of first and second side wall structures on the first side, and defining an inter-electrode current path through the bridge between the first and second side wall structures across the insulating wall, the inter-electrode current path having a path length defined by the thickness of the insulating wall, wherein the bridge comprises programmable resistive material.