Patent ID: 8681535

Claim:
A nonvolatile latch circuit comprising: a first input signal terminal; a second input signal terminal; a first logic gate electrically coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal; a second logic gate electrically coupled to the high voltage source at a first source terminal and to the low voltage source at a second source terminal, the first and second logic gates are electrically cross-coupled to each other, and a first nonvolatile memory element electrically coupled to an output terminal of the first logic gate at a first end and to an intermediate voltage source at a second end, wherein a logic state of the first nonvolatile memory element is controlled by a bidirectional current running between the first and second ends of the first nonvolatile memory element, and wherein an electrical potential of the intermediate voltage source is fixed and higher than that of the low voltage source but lower than that of the high voltage source.