Patent ID: 7554851

Claim:
A reset method of a non-volatile memory comprising a plurality of cells on a substrate of a first conductivity type, each cell comprising a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in the portion of the substrate, the method utilizing a double-side bias band-to-band tunneling hot hole (DSB- BTBTHH) effect and comprising: applying a first voltage to the substrate and a second voltage to both of the S/D regions of each cell, wherein a difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes; and controlling a gate voltage applied to the control gate of each cell and a period of applying the voltages such that threshold voltages of all the memory cells converge in a tolerable range between a programming threshold voltage at a high threshold voltage (high-Vt) state or a low threshold voltage (low-Vt) state and an erasing threshold voltage at the corresponding low threshold voltage (low-Vt) state or a corresponding high threshold voltage (high-Vt) state.