Patent ID: 7999594

Claim:
A semiconductor integrated circuit that includes a plurality of areas including a first area group and a second area group, each of the first area group and the second area group generates phase clocks in accordance with an external clock and a first control signal or a second control signal and performs a first process and a second process assigned to each of the phase clocks, the semiconductor integrated circuit comprising: a control signal distributing unit that adjusts the first and second control signals so that a timing at which the first control signal output to the first area group is turned on or off and a timing at which the second control signal output to the second area group is turned on or off are opposite to each other and distributes the adjusted first and second control signals to the first area group and the second area group, respectively, wherein the first area group and the second area group perform the first process for a time period for which the first control signal or the second control signal is ON and perform the second process for a time period for which the first control signal or the second control signal is OFF, power consumption of the first process being not less than a predetermined value, power consumption of the second process being less than the predetermined value.