Patent ID: 6928499

Claim:
A microcomputer comprising: a central processing unit for outputting a plurality of bus control signals; an external area judging unit for judging according to one bus control signal output from the central processing unit whether access of the central processing unit to an external storing unit is set or access of the central processing unit to a peripheral unit is set and outputting a bus selection signal according to a judgment result; and a bus control unit, in which a bus interface having both a bus timing for the external storing unit and a bus timing for the peripheral unit is disposed, for sending the bus control signals output from the central processing unit to the external storing unit as a plurality of external bus signals based on the bus timing for the external storing unit, in a case where the bus selection signal output from the external area judging unit indicates the access to the external storing unit, to make the central processing unit gain access to the external storing unit, and sending the bus control signals output from the central processing unit to the peripheral unit as a plurality of external bus signals based on the bus timing for the peripheral unit, in a case where the bus selection signal output from the external area judging unit indicates the access to the peripheral unit, to make the central processing unit gain access to the peripheral unit.