Patent ID: 7586347

Claim:
A clock generator comprising a phase-lock loop configured to generate an output clock signal based on a reference clock signal, the phase-lock loop comprising: a charge pump configured to generate a first signal for adjusting a frequency of the phase-lock loop based on a charge current; a low-pass filter coupled to the charge pump, the low-pass filter configured to generate a second signal and a bias voltage by filtering the first signal; a voltage-controlled oscillator coupled to the low pass filter and configured to generate the output clock signal having a frequency based on the second signal; and a self-bias circuit coupled to the low pass filter and coupled to the charge pump, the self-bias circuit configured to generate the charge current based on the bias voltage for controlling a bandwidth of the phase-lock loop, the self-bias circuit comprising: a transistor circuit comprising a plurality of transistors configured to generate a first voltage; a first resistor configured to generate a first current based on the first voltage; a first current mirror configured to generate a second current based on the first current; a second resistor configured to generate a third current comprising the second current and a fourth current; and a second current mirror configured to generate the charge current based on the fourth current and the bias voltage.