Patent ID: 7505344

Claim:
In a memory array having at least two memory planes of memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell within a memory plane coupled between a word line and a bit line associated with the memory plane and having first and second nominal current levels in accordance with its data state when forward biased, a method of sensing the data state of a selected memory cell comprising the steps of: driving a selected word line from an unselected word line bias voltage to a selected word line bias voltage; driving a selected bit line from an unselected bit line bias voltage to a selected bit line bias voltage; sensing current flow on the selected bit line while the selected bit line remains substantially at the selected bit line bias voltage to determine which of the first or second nominal current levels flows through the selected memory cell; wherein the sensing current flow step comprises: subtracting a reference current having a magnitude between the first and second nominal current levels from the bit line current, resulting in a net bit line current; and sensing whether the net bit line current is positive or negative.