Patent ID: 7978552

Claim:
A semiconductor memory device comprising: a plurality of bit lines; a plurality of word lines crossing the bit lines; a plurality of memory cells corresponding to intersections of the bit lines with the word lines, the memory cells being configured to store data depending on carriers stored in electrically floating bodies; a source line corresponding to first and second word lines adjacent to each other and connected to memory cells connected to the first and the second word lines; a plurality of sense amplifiers connected to the bit lines and configured to detect data stored in the memory cells or to write data in the memory cells; a source line driver configured to drive the source line; and a word line driver configured to drive the first word line or the second word line, wherein during a first write operation in which first logical data is written in all memory cells connected to the first word line, the word line driver applies a voltage to the first word line in such a manner that channels are formed in the memory cells connected to the first word line, the source line driver shifts a voltage of a selected source line corresponding to the first word line in a direction away from the voltage of the first word line, and the word line driver shifts a voltage of the second word line in a same direction as a transition direction of voltage of the selected source line, and during a second write operation in which second logical data is written in a selected memory cell of the memory cells connected to the first word line, the source line driver and the word line driver respectively shift voltages of the selected source line and the second word line in a direction approaching the voltage of the first word line.