Patent ID: 7319630

Claim:
An integrated circuit for storage of data comprising: an array of nonvolatile memory cells; a plurality of latch circuits coupled to the array of nonvolatile memory cells, the plurality of latch circuits connected in parallel between an upper supply line and a lower supply line, an individual one of the plurality of latch circuits including a pull-up circuit block connected to the upper supply line and a pull-down circuit block connected to the lower supply line; a first current limiter circuit connected to the upper supply line; a first current source connected to the first current limiter circuit, the first current limiter circuit interposed between the first current source and the upper supply line to limit a first current from the first current source to the upper supply line; a second current limiter circuit connected to the lower supply line; and a second current source connected to the second current limiter circuit, the second current limiter circuit interposed between the second current source and the lower supply line to limit a second current from the second current source to the lower supply line.