Patent ID: 8164357

Claim:
A circuit comprising: a comparator device having a comparator configured for generating a digital signal; and a protection circuit including: a signal-generating circuit configured to generate an output signal that is structured to switch from a first logic state to a second logic state upon detection of a switching of a logic state of the digital signal; a state-change detection circuit configured to detect the change from the first logic state to the second logic state of the output signal; and a switching-inhibition circuit configured to inhibit switching of the output signal for a time interval after the change from the first logic state to the second logic state, the switching-inhibition circuit including: a delay circuit configured to receive the digital signal and to generate a verification signal delayed with respect to the digital signal; a comparison circuit configured to compare the output signal with the verification signal and to generate an inhibition-control signal that enables a further change of logic state of the output signal only after detection of a switching of logic state of the verification signal; and a memory configured to maintain the output signal in the second logic state during the time interval, the memory including a flip-flop of a D type and having an enable input terminal configured to receive the control signal, a data input terminal configured to receive the digital signal, and an output terminal configured to generate the output signal; and the comparator device including an XOR logic gate having a first input terminal connected to an output of the delay circuit, a second input terminal connected to the output of the flip-flop, and an output connected to the enable input of the flip-flop.