Patent ID: 8542041

Claim:
A semiconductor device, comprising: a first voltage detection circuit an of a power supply voltage and generates a first signal; a second voltage detection circuit that detects a decrease of the power supply voltage and generates a second signal; and a power supply voltage detection signal output circuit that outputs a power supply voltage detection signal based on the first signal and the second signal, wherein the second voltage detection circuit includes: a first transistor including one end which receives the power supply voltage from a first power supply line, a gate which receives the power supply voltage from the first power supply line, and other end coupled to a first node; a second transistor including a gate which receives a first bias voltage via a second node, one end coupled to the first node, and other end coupled to a third node; a third transistor including one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node; a first bias voltage generation circuit that supplies the first bias voltage to the second node; a second bias voltage generation circuit that supplies a second bias voltage to the fourth node; and a first capacitor coupled to the first node and configured to be charged from the power supply voltage through the first transistor, wherein when the power supply voltage decreases, the first and second bias voltage generation circuits decrease the first and second bias voltages, the second transistor is turned on, the third transistor is turned off, an electric charge of the first capacitor moves to the third node, and the third node outputs the second signal.