Patent ID: 8533378

Claim:
An information processing device comprising: a first data transfer circuit; a second data transfer circuit, wherein the first data transfer circuit is connected to the second data transfer circuit via a first bus and a second bus; and a plurality of control circuits that are connected to the first data transfer circuit or the second data transfer circuit, a control circuit transferring data to another control circuit, wherein the first data transfer circuit includes: a first reception unit that receives, from a control circuit connected to the first data transfer circuit, first data to be transmitted to all the control circuits connected to the second data transfer circuit, and queues the received first data; a second reception unit that receives, from a control circuit connected to the first data transfer circuit, second data to be transmitted to one of the control circuits connected to the second data transfer circuit, and queues the received second data; a first bus output unit that transmits the first data to the second data transfer circuit via a first selection unit and the first bus; a second bus output unit that transmits the second data to the second data transfer circuit via the second bus; a selector control unit that controls a second selection unit to allow the second data to be transmitted to the second data transfer circuit via a third bus output unit, the first selection unit and the first bus, based on a usage rate of the second bus and an amount of the first data queued in the first reception unit; a first bus input unit that receives third data to be transmitted to all the control circuits connected to the first data transfer circuit or forth data to be transmitted to one of the control circuits connected to the first data transfer circuit from a control circuit connected to the second data transfer circuit via the first bus; and a second bus input unit that receives the fourth data via the second bus.