Patent ID: 7899641

Claim:
A testable electronic circuit, comprising a plurality of data terminals; a functional circuit; a plurality of groups of flip-flops, coupled to the data terminals and to the functional circuit, and each having a clock input for clocking the flip-flops of the group, each group being switchable between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit and/or receive signals from the functional circuit respectively; a test control circuit that is switchable between a functional mode, a test shift mode and a test normal mode, the test control circuit being coupled to the groups of flip-flops to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode; and a clock multiplexing circuit comprising: a first clock input to receive an external test clock signal for use in the test shift mode; second clock inputs coupled to the data terminals to receive clock signals for use in the test normal mode; third clock inputs to receive internal clock signals for use in the functional mode; and outputs coupled to the clock inputs of the groups of flip-flops; wherein the test control circuit is coupled to control the clock multiplexing circuit dependent on the mode assumed by the test control circuit for selection of the test clock signal from the first clock input in the test shift mode, selection of the clock signals from the second clock inputs in the test normal mode, and selection of the internal clock signals from the third clock inputs in the functional mode; and wherein the clock multiplexing circuit is arranged to substitute the second clock signals from respective ones of the data terminals temporarily at the clock inputs of respective ones of the groups in the test normal mode.