Patent ID: 7965482

Claim:
An ESD protection circuit comprising: a plurality of logic gates connected between a first power supply input to which a first potential is applied and a second power supply input to which a second potential lower than the first potential is applied, wherein in the plurality of logic gates, output terminals of each of the logic gates at a front stage is connected to an input terminal of each of the logic gate at a rear stage in rear of the front stage, if a protection potential between the first potential and the second potential is applied to a connection node connecting the output terminal to the input terminal when the plurality of logic gates respond to an ESD surge, a breakthrough current is carried to the plurality of logic gates from the first potential toward the second potential, and if the first potential and the second potential are applied to the first power supply input and the second power supply input, respectively, logic values of the plurality of logic gates are kept in a constant state.