Patent ID: 7785961

Claim:
A method of forming a DRAM array, comprising the steps of: providing a silicon substrate comprising a substrate material of a first conductivity type; forming a first silicon layer of a second conductivity type on the substrate; forming a second silicon layer of a first conductivity type on the first silicon layer; forming a third silicon layer of a second conductivity type on the second silicon layer; defining a first set of trenches in the substrate and extending through the first, second, and third silicon layers and into the substrate material; filling the first set of trenches with oxide; defining a second set of trenches in the substrate which extend through the first, second, and third silicon layers to the level of the substrate material in a direction orthogonal to the first set of trenches to form vertical stacks of said first, second, and third silicon layers, said vertical stacks having a first and a second vertical side; forming an isolation layer between the vertical stacks and the substrate; electrically connecting the first side of the vertical stacks with individual capacitor structures; forming word lines in contact with the second side of the vertical stacks and in the second set of trenches so as to form vertical transistors spanning a surface area over the substrate of no greater than 4F 2 , where F is the minimum lithographic feature size; and forming bit lines on top of the third silicon layer of the vertical transistors.