Patent ID: 8451654

Claim:
A semiconductor memory device comprising: a memory cell including: a latch circuit comprising a first inverter circuit and a second inverter circuit, where an output of the first inverter circuit is connected to an input of the second inverter circuit, and an output of the second inverter circuit is connected to an input of the first inverter circuit; and a read circuit configured to read from the latch circuit, wherein: the first inverter circuit includes a first PMOS transistor and a first NMOS transistor, the second inverter circuit includes a second PMOS transistor and a second NMOS transistor, at least one of a source and a drain of the first NMOS transistor is cut off and a first voltage is supplied to a source of the first PMOS transistor in the first inverter circuit, and at least one of a source and a drain of the second PMOS transistor is cut off and a second voltage lower than the first voltage is supplied to a source of the second NMOS transistor in the second inverter circuit.