Patent ID: 8207795

Claim:
A delay cell for use in a ring oscillator, comprising: a differential amplifier, for generating a differential output at the output ends, comprising: a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal; a differential pair, comprising a first current source, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; wherein: the first current source is coupled between a voltage supply and the third PMOS transistor source; the gate of the third PMOS transistor is inputted with an inverted voltage controlling signal; the drain of the third PMOS transistor is coupled to the source of the first PMOS transistor and the source of the second PMOS transistor; the gate of the first PMOS transistor is the positive input terminal; the gate of the second PMOS transistor is the negative input terminal; and the drain of the first PMOS transistor is the positive output terminal, and the drain of the second PMOS transistor is the negative output terminal; a switched capacitance bank, coupled to the differential amplifier, for providing capacitance according to a capacitance controlling signal; and a Kvco equalizer, coupled to the differential amplifier, for generating an adjustable current at the output ends of the differential amplifier according to a current controlling signal, comprising: an adjustable current source comprising: a fixed current providing path, implementing a fixed current transistor resistor which causes the fixed current providing path to provide a fixed current; and a plurality of controlled current paths coupled between a voltage supply and a node, each controlled current path implementing a corresponding resistor and transistor switch for selectively conducting the controlled current paths between the voltage supply and the node; and a fourth PMOS transistor; a fifth PMOS transistor; and a sixth PMOS transistor; wherein: the source of the sixth PMOS transistor is coupled to the node; the gate of the sixth PMOS transistor is inputted with a voltage controlling signal; the drain of the sixth PMOS transistor is coupled to the source of the fourth PMOS transistor and the source of the fifth PMOS transistor; the gate of the fourth PMOS transistor is coupled to the drain of the fifth PMOS transistor drain and the negative output terminal; and the gate of the fifth PMOS transistor is coupled to the drain of the fourth PMOS transistor and the positive output terminal; wherein the current controlling signal controls the transistor switches to further control the output current magnitude of the adjustable current source; wherein the current control signal associates with the capacitance control signal and the Kvco values are equalized on a plurality of frequency bands.