Patent ID: 7706114

Claim:
An ESD avoiding circuit for avoiding passing an electrostatic discharge voltage induced on a connection pad to an internal circuit comprising: a first transistor having a source coupled to the connection pad, a drain coupled to the internal circuit, a gate, and a channel well; and an ESD detector coupled to the first transistor for providing a control signal to the gate of the first transistor, the ESD detector comprising: a second transistor having a source coupled to the connection pad, a channel well coupled to the source, a gate coupled to the internal circuit, and a drain coupled to the gate of the first transistor; a third transistor having a source coupled to a ground terminal, a channel well coupled to the source, a gate coupled to the internal circuit, and a drain coupled to the gate of the first transistor; and a fourth transistor having a source coupled to the ground terminal, a channel well coupled to the source, a gate coupled to a power terminal, and a drain coupled to the gate of the first transistor.