Patent ID: 7573481

Claim:
A digital data processing system comprising: a. an array of processing elements; having addressable data storage means; adapted to process bit plane data; b. an allocation table comprising storage means for storing physical addresses; c. means for conveying an image descriptor comprising a virtual address attribute and a size attribute, the virtual address and size attributes specifying the range of the allocation table positions, wherein the physical addresses of the bit planes comprising an image are stored; and d. a sequencer configured to control processing of bit planes in the processor array, the sequencer generating at least one microinstruction in response to at least one image descriptor, the image descriptor representing a processor array image operand, the at least one microinstruction comprising one microinstruction for each bit plane of the image operand, each of the microinstructions comprising a physical address, wherein the physical address is generated by reading the allocation table at a generated virtual address, the generated virtual address being computed by increasing the virtual address attribute of the image descriptor by a count of 1 for each generated microinstruction.