Patent ID: 7436728

Claim:
A method of fast random access management of a DRAM memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying an address of the bank concerned by a current request; comparing the address of the bank concerned by a current request with addresses of N−1 banks previously requested, N being an integral number of cycles necessary to execute a request; if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, suspending and storing the current request until the previous request involving the same bank is executed, otherwise, executing the current request; refreshing the memory periodically line by line and bank by bank; comparing the address of the bank to be refreshed with addresses of N−1 ongoing requests and of N following requests; delaying the refreshing if the address of the bank to be refreshed corresponds to one of the bank addresses of 2N−1 requests; and resuming the refreshing and interrupting a succession of requests after a determined number of refresh cycle interruptions have occurred.