Patent ID: 7650550

Claim:
A method comprising: receiving a first signal at a first combinational logic path of an integrated circuit, the first signal transitioning at a first time; providing a second signal from the first combinational logic path, the second signal transitioning at a second time in response to the first signal transitioning at the first time; latching a first latch value based on the second signal in response to a clock signal changing state at a third time; delaying the clock signal to create a delayed clock signal; latching a second latch value based on the second signal in response to the delayed clock signal changing state at a fourth time, the delayed clock signal changing state in response to the clock signal changing state at the third time; and determining an over-temperature condition at the integrated circuit in response to the first latch value having a different logic value than the second latch value, and asserting an error signal in response to determining an over-temperature condition.