Patent ID: 8855186

Claim:
A system for optimizing equalization of a high-speed data link with a processor comprising: means for generating minimum (x min ) and maximum voltage (x max ) array input values derived from a sampled input signal x; means for generating minimum and maximum voltage array output values representing a plurality of eye heights based on generated voltage array input values associated with a specified horizontal position of the unit interval and based on a single feedback coefficient value; means for identifying a maximum voltage value y max representing a maximum eye height based on the generated voltage array output values; means for identifying one or more optimum feedback coefficient values, d right and d left , based on the identified maximum voltage value; and means for generating a non-linear, equalized output signal based on the one or more identified optimum feedback coefficient values; wherein y max =0.5( x bit11 min +x bit01 min −x bit10 max −x bit00 max )−( d right −d left ).