Patent ID: 7282983

Claim:
A calculating unit, comprising: a dual rail input stage for receiving at least one input operand and for outputting the input operand in a non-inverted form at a first output of the dual rail input stage and the input operand in an inverted form at a second output of the dual rail input stage in a data mode, wherein the input stage is further implemented to bring the first and the second outputs to the same potential in a preparation mode; a switching stage which is implemented to switch through a calculating potential to an output of the switching stage according to a calculating regulation for an output bit depending on the at least one input operand, wherein the calculating potential at the output represents one of the output bit and an inverted version of the output bit; a dual rail output stage having an input connected to the output of the switching stage and having a first output and a second output, wherein in a data mode the output bit is applied to the first output of the output stage, wherein in the data mode an inverted version of the output bit is applied to the second output of the output stage, and wherein in a preparation mode, the first output and the second output of the output stage are adapted to be brought to the same preparation potential, wherein the preparation potential is different from the calculating potential, wherein the switching stage includes at least one internal node, which is in the preparation mode neither coupled to a potential on the first or the second input of the input stage nor to a potential on the input of the output stage; and a node potential circuit for coupling the internal node in the preparation mode to a reference potential and for decoupling the internal node in the data mode from the reference potential.