Patent ID: 7197677

Claim:
A system, comprising: a bus; a first random access memory (RAM); a first memory testing engine (MTE) to execute test operations on the first random access memory; a first bus controller for the bus, and in which the first memory testing engine is integrated to have a first memory interface which is shared with the first memory testing engine to access the first RAM; a second RAM; a second MTE to execute test operations on the second RAM; a second bus controller for the bus, and in which the second MTE is integrated to have a second memory interface which is shared with the second MTE to access the second RAM; and a processor; wherein each bus controller is to provide the processor access to random access memory via its respective memory interface, and the processor is to control the each memory testing engine via the bus and the respective bus controller and wherein each memory testing engine uses data, address and control pathways used by its respective bus controller so that if normal data traffic from the processor is being passed to a memory module by the respective bus controller, its integrated memory testing engine cannot run a test function.