Patent ID: 8040710

Claim:
A semiconductor memory arrangement comprising: a circuit board having at least a first layer and a second layer, said circuit board has a first end and a second end and a first surface and a second surface; a plurality of memory units; a first control device and a second control device adapted to receive command and address signals; a first bus system disposed in said first layer of said circuit board and coupled to said first control device and to a first group of memory units of said plurality of memory units to transmit said command and address signals to said first group of memory units; and a second bus system disposed in said second layer of said circuit board and coupled to said second control device and to a second group of memory units of said plurality of memory units to transmit said command and address signals to said second group of memory units, wherein the first bus system is electrically separate from the second bus system, wherein said first group of memory units is disposed on said first surface of said circuit board and between said first end of said circuit board and said first control device; wherein said second group of memory units is disposed on said second surface of said circuit board and between said first end of said circuit board and said second control device, and wherein each of said memory units includes a plurality of memory chips, said first control device adapted to receive a first device select signal and a second device select signal and to transmit said first device select signal to a subset of each of said plurality of memory chips of said first group of memory units and to transmit said second device select signal to another subset of each of said plurality of memory chips of said first group of memory units.