Patent ID: 7757221

Claim:
A computer implemented method comprising: translating a source binary application, generated for a source instruction set architecture (ISA), into a sequential intermediate representation (IR) of the source binary application; identifying each exception instruction within the source ISA binary application; identifying a predetermined reaching instruction within the sequential IR of the source ISA binary application for each of the identified exception instructions; identifying one or more irreversible instructions within the source ISA binary application; generating an irreversible instruction (II) data structure; storing an identification assigned to each of the one or more irreversible instructions identified from the source binary application within the II data structure; selecting a recovery point instruction as a source instruction immediately following the identified irreversible instruction; storing an address of the source instruction immediately following the identified irreversible instruction within the II data structure to form exception recovery information for the identified exception instructions; modifying the sequential IR to incorporate the exception recovery information for the identified exception instructions, identified from the source ISA binary application, to form a modified, non-sequential IR; and optimizing the modified, non-sequential IR to form an optimized, translated binary application for a target ISA that incorporates the exception recovery information to enable exception recovery.