Patent ID: 7403418

Claim:
An array of non-volatile memory cells comprising: a semiconductor substrate of a first conductivity type; a first group of non-volatile memory cells, each cell comprising: a first region of a second conductivity type in said substrate; a second region of the second conductivity type in said substrate, spaced apart from said first region, thereby defining a channel region therebetween; a floating gate insulated from a portion of the channel region for controlling the conduction of current in the portion of the channel region; a control gate adjacent to and spaced apart from the floating gate, and capacitively coupled thereto for receiving charges therefrom during an erase operation; a first word line electrically connecting all the control gates of all the cells in the same row in the first group; a second group of non-volatile memory cells, each cell comprising: a first region of a second conductivity type in said substrate; a second region of the second conductivity type in said substrate, spaced apart from said first region, thereby defining a channel region therebetween; a floating gate insulated from a portion of the channel region for controlling the conduction of current in the portion of the channel region; a control gate adjacent to and spaced apart from the floating gate, capacitively coupled thereto for receiving charges therefrom during an erase operation; a second word line electrically connecting all the control gates of all the cells in the same row in the second group; said first word line forming a capacitor with said second word line; a first switch connected to said first word line for electrically connecting said first word line to a first voltage source; a second switch connected to said second word line for electrically connecting said second word line to a second voltage source; and a sequencing circuit for activating said first switch connecting said first word line, as the selected word line for the erase operation to the memory cells connected thereto, to said first voltage source, while maintaining said second switch in a position to disconnect the second word line from said second voltage source; and for activating said second switch connecting said second word line to said second voltage source, while maintaining said first switch in a position to disconnect the first word line from said first voltage source; wherein the alternate switching of said first switch and said second switch boosts the voltage on said first word line during the erase operation.