Patent ID: 8212624

Claim:
A reference frequency generation circuit which generates a reference clock, the circuit comprising: an oscillator circuit configured to alternately perform, in response to a transition of a signal level of the reference clock, an operation to increase a signal level of a first oscillation signal and reduce a signal level of a second oscillation signal, and an operation to increase the signal level of the second oscillation signal and reduce the signal level of the first oscillation signal; an oscillation control circuit configured to cause, when detecting that the signal level of the first oscillation signal has reached a comparison voltage, the signal level of the reference clock to transition to a first logic level, and cause, when detecting that the signal level of the second oscillation signal has reached the comparison voltage, the signal level of the reference clock to transition to a second logic level; and a reference control circuit configured to increase or reduce the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.