Patent ID: 7427567

Claim:
A method of manufacturing an integrated circuit comprising copper metallization that has been planarized, said method comprising: (a) providing a first chemical mechanical polishing slurry wherein said first slurry has a removal rate ratio of copper to barrier material of about 10:1; (b) chemical mechanical polishing a semiconductor wafer surface with said first slurry; (c) providing a second chemical mechanical polishing slurry having a pH in a range from about 2 to about 5, and an oxidizing agent to corrosion inhibitor weight ratio less than one, wherein said second slurry has a removal rate ratio of copper to barrier material of about 1:1 and a removal rate ratio of copper to dielectric of about 6:1; and (d) chemical mechanical polishing said semiconductor wafer surface with a second slurry, wherein the corrosion inhibitor of the second chemical mechanical polishing slurry comprises an agent selected from the group consisting of glycine, oxalic acid, malonic acid, succinic acid, nitrilotriacetic acid, and iminodiacetic acid.