Patent ID: 8391367

Claim:
An apparatus comprising: a transform circuit configured to (i) generate and store in a memory one or more first coefficients in response to a sample signal when in a first mode and (ii) generate said sample signal in response to said first coefficients retrieved from said memory when in a second mode; a first coder circuit configured to (i) generate a first bitstream signal in response to one or more second coefficients retrieved from said memory when in said first mode and (ii) generate said second coefficients to be stored in said memory in response to said first bitstream signal when in said second mode; and a second coder circuit configured to (i) generate a second bitstream signal in response to one or more third coefficients retrieved from said memory when in said first mode and (ii) generate said third coefficients to be stored in said memory in response to said second bitstream signal when in said second mode, wherein said memory circuit is (i) coupled to said transform circuit, said first coder circuit and said second coder circuit, (ii) configured to store said first coefficients, said second coefficients, and said third coefficients, and (iii) configured to allow said transform circuit, said first coder circuit, and said second coder circuit to operate independently.