Patent ID: 7122855

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a trench formed in the semiconductor substrate; a diffusion layer for a first electrode, formed in the semiconductor substrate so as to be in contact with an inner surface of the trench; a capacitor insulating film formed on the first electrode exposed as the inner surface of the trench; a conductive layer for a second electrode, formed on the capacitor insulating film so as to bury a lower portion of the trench; a first insulating film formed on the second electrode and along a side surface of the trench; a first conductive layer formed on a side surface of the first insulating film and on the second electrode so as to bury an intermediate portion of the trench; a first contact layer formed on the first insulating film and on the first conductive layer so as to bury an upper portion of the trench, the first contact layer being formed of a conductive material; a second contact layer formed on an upper surface of the semiconductor substrate and on the first contact layer, the second contact layer being formed of a conductive material; and a transistor having a source and a drain formed in the semiconductor substrate, the source or the drain being in contact with the first and second contact layers.