Patent ID: 8299629

Claim:
A wafer-bump structure including: a wafer-state semiconductor die including: at least one die pad embedded therein; and a passivation layer formed on the wafer-state semiconductor die and the die pad, wherein the passivation layer includes an aperture for allowing access to a portion of the die pad; a pre-treatment layer formed on the portion of the die pad not covered by the passivation layer; a first electrodeless nickel/immersion gold laminate formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer; and at least one pillar bump including: a conductive metal layer formed on the first electrodeless nickel/immersion gold laminate and another annular portion of the passivation layer around the first electrodeless nickel/immersion gold laminate; and a second electrodeless nickel/immersion gold laminate formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.