Patent ID: 8076962

Claim:
A frequency synthesis system with self-calibrated loop stability and bandwidth, comprising: a detector, for receiving an input signal and a feedback signal to produce a detection signal based on a logic level difference between the input signal and the feedback signal; a charge pump, connected to the detector, for producing a control signal based on the detection signal and a compensation current; a filter, connected to the charge pump, for producing a tuning signal and a source current based on the control signal; a bias circuit, connected to the filter, for producing a first bias signal and a second bias signal based on the tuning signal; a controllable oscillator, connected to the bias circuit, for producing a differential output signal with a selected specific frequency based on the first bias signal and the second bias signal; a differential-to-single converter, connected to the controllable oscillator, for converting the differential output signal into an output signal; a programmable frequency divider, connected to the differential-to-single converter, for producing the feedback signal based on the output signal; a current mirror circuit, for receiving the source current to produce a mirror current; a compensation circuit, for producing the compensation current based on the mirror current so as to compensate a variation of a damping factor and a bandwidth-to-reference frequency ratio.