Patent ID: 8433952

Claim:
A memory access control device comprising: a memory; a memory control unit configured to perform access control of said memory; and a software execution unit configured to execute software that manages said memory and said memory control unit, wherein said memory control unit comprises: a data transmission unit configured to perform multicast transfer that reads a data from said memory and transmits said read data to data transfer destinations through a network; a data reception unit configured to receive multicast transfer data from said network; a reception data counter configured to indicate a number of multicast transfer data received by said data reception unit; and an error information register configured to store error information that is added by said network to multicast transfer data received by said data reception unit, wherein said software execution unit of a transmitting side instructs said memory control unit of the transmitting side to perform a plurality of multicast transfers and then reads respective reception data counters of said data transfer destinations being a receiving side for each checkpoint in sequence of said software to determine completion of said plurality of multicast transfers, and wherein said software execution unit of the transmitting side reads respective error information registers of said data transfer destinations being the receiving side for each checkpoint in sequence of said software to determine success and failure of said plurality of multicast transfers.