Patent ID: 7436410

Claim:
A system for configuring a chip to perform certain operations, comprising: a central processing unit; a graphics controller in communication with the central processing unit, wherein the graphics controller includes, a non-volatile memory storing a look up table, the look up table populated with look up table sequences, the look up table sequences including both an address portion and a data portion, wherein one of the look up table sequences includes a data portion representing a phase locked loop frequency; a register port capable of receiving a look up table (LUT) value; LUT circuitry in communication with the register port, wherein the LUT circuitry retrieves a corresponding LUT sequence from the LUT based on the LUT value provided by the register port; a memory having a portion set aside for storing additional look up table sequences generated from one of the look up table sequences in the non-volatile memory; and a register block designated to be programmed with an appropriate value determined by the LUT sequence.