Patent ID: 7842521

Claim:
A method for automatically patterning the surfaces of a plurality of wafers comprising: preparing a first wafer for patterning; measuring said first wafer to determine the characteristics of said first wafer in a region proximate the first wafer's edge; characterizing portions of said region proximate the first wafer's edge as either useful or not useful based upon said measuring; producing a first pattern layout of pattern features which includes features in portions of said region proximate the first wafer's edge characterized as useful and which does not include features in portions of said region proximate the first wafer's edge characterized as not useful; patterning said first wafer based on said first pattern layout; preparing a second wafer for patterning; measuring said second wafer to determine the characteristics of said second wafer in a region proximate the second wafer's edge; characterizing portions of said region proximate the second wafer's edge as either useful or not useful based upon said measuring; producing a second pattern layout of pattern features which includes features in portions of said region proximate the second wafer's edge characterized as useful and which does not include features in portions of said region proximate the second wafer's edge characterized as not useful; patterning said second wafer based on said second pattern layout; wherein said first pattern and said second pattern are different.