Patent ID: 7145831

Claim:
A data synchronization arrangement for exchanging clocked data between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift, comprising: a register arrangement comprising a predetermined number of parallel registers, each register having a data input, a write clock input, a read clock input and a data output, a write select multiplexer having an input receiving a write clock signal from a first clock domain, one clock output for each of said parallel registers and connected to a write clock input of a respective register, and one write select input for each clock output, a read select multiplexer having an input receiving a read clock signal from a second clock domain, one clock output for each of said parallel registers and connected to a read clock input of a respective register, and one read select input for each clock output, a write select shift register with a number of stages corresponding to the predetermined number of registers and an output stage looped back to an input stage, each stage having an output connected to a respective one of the write select inputs of the write select multiplexer, the write select shift register being clocked with the write clock signal, a read select shift register with a number of stages corresponding to the predetermined number of registers and an output stage looped back to an input stage, each stage having an output connected to a respective one of the read select inputs of the read select multiplexer, the read select shift register being clocked with the read clock signal, and a reset circuit for initializing each shift register with a bit pattern that contains only one high value, the bit patterns in the shift registers having a constant relative offset; a data input stream synchronized with the clock of the first clock domain being applied to the data inputs of the registers and a data output stream synchronized with the clock of the second clock domain being taken from the data outputs of the registers.