Patent ID: 7109082

Claim:
A flash memory cell, comprising: a first conductive type substrate; a plurality of device isolation structures disposed in the first conductive type substrate to define a plurality of active regions; a second conductive type well disposed in the first conductive type substrate; a patterned film layer disposed on the first conductive type substrate, wherein the patterned film layer has a plurality of openings that exposes a portion of the first conductive type substrate within the active regions; a plurality of floating gates disposed inside the openings and extended over a portion of the device isolation structures, wherein the floating gate has a thickness greater than that of the patterned film layer; a tunneling dielectric layer disposed between the floating gates and the first conductive type substrate; a plurality of control gates disposed over the floating gates; an inter-gate dielectric layer disposed between the floating gates and the control gates; and a first conductive type doped region disposed in the first conductive type substrate within the active region on each side of the control gates.