Patent ID: 7577225

Claim:
An integrated circuit including a digital phase-locked loop (PLL) circuit, comprising: a digital phase detector having a phase detector output and configured to generate a first multi-bit output via the phase detector output, the first multi-bit output representing a phase difference between a reference clock signal and a plurality of clock phase inputs; a digital frequency detector having a frequency detector output and configured to generate a second multi-bit output via the frequency detector output, the second multi-bit output representing a frequency difference between the reference clock signal and a current operating frequency of a digitally-controlled oscillator (DCO); a digital loop filter coupled to the digital phase detector via the phase detector output and coupled to the digital frequency detector via the frequency detector output, the loop filter having a loop filter output and generating a third multi-bit output via the loop filter output, the third multi-bit output being based on the first multi-bit output from the digital phase detector and the second multi-bit output from the digital frequency detector; and the digitally-controlled oscillator (DCO) coupled to the digital loop filter via the loop filter output, the digital phase detector and the digital frequency detector, wherein the third multi-bit output from the digital loop filter is input to the DCO as a multi-bit control word, wherein the DCO has a first feedback path coupled to the digital phase detector and a second feedback path coupled to the digital frequency detector, wherein the DCO outputs the plurality of clock phase inputs to the digital phase detector via the first feedback path based on the multi-bit control word, and wherein the DCO provides the current operating frequency of the DCO to the digital frequency detector via the second feedback path based on the multi-bit control word.