Patent ID: 7595671

Claim:
A Phase Locked Loop (PLL) circuit, comprising: a phase comparing circuit comparing a phase of a reference clock signal with a phase of a feedback clock signal to output a voltage-up signal and a voltage-down signal based on a phase difference between the reference clock signal and the feedback clock signal; a first charge pump circuit generating a first current based on the voltage-up signal and the voltage-down signal; a dummy signal generating circuit outputting a dummy signal having substantially a same pulse width as a pulse width of one of the voltage-up signal and the voltage-down signal in sync with the voltage-up signal or the voltage-down signal; a second charge pump circuit generating a second current based on the dummy signal; and a voltage-controlled oscillator controlling an output clock frequency based on a differential voltage between a first voltage generated in accordance with the first current and a second voltage generated in accordance with the second current.