Patent ID: 7237175

Claim:
A memory circuit comprising: a memory cell array having a plurality of memory cells which are arranged in said memory cell array, error correcting means for correcting an error in each of (m+n) bit data when a read or write operation is carried out for said (m+n) bit data in which parity bits of n bits are added to data of m bits, where m represents a positive integer which is not less than two, and n represents a positive integer which is not less than one, wherein said memory cell array is divided into a plurality of memory units each of which has bits of a predetermined number K that are arranged along a direction of a word line, where K represents a positive integer which is not less than two; each bit of said (m+n) bit data being written in each of said memory units along said word line and separated from each other along said word line by an interval of said predetermined number K, when said (m+n) bit data is written in said memory cell array; and said error correcting means carrying out an error correction for said (m+n) bit data whose parity and data bits are written in said memory units, respectively, wherein said predetermined number K represents a worst value between error bits which cause a data error and is given by a relationship of K>Q/(Cs×Vcc), where Cs (farads) represents a capacitance in a latch node of each memory cell, Vcc (volts) representing an operating voltage of each memory cell, and −Q (coulombs) representing a charge of an electron in a pair of electron and hole produced by particles which causes said memory circuit a multi-bit soft error in which a plurality of bit errors generates locally and simultaneously.