Patent ID: 7830195

Claim:
A method of generating clock signals for a level-sensitive scan design latch, comprising the actions of: a. transmitting at least one test input signal to a plurality of splitter leaves; b. once the at least one test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root; and c. at the plurality of splitter leaves, logically combining the at least one test input signal with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal, the logically combining action including: i. applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; ii. logically combining the delayed oscillator clock signal with at least a second signal so as to generate the first latch clock signal; and iii. logically combining the shaped oscillator clock signal with at least one third signal so as to generate the second latch clock signal.