Patent ID: 7442601

Claim:
A method for fabricating a stress enhanced CMOS circuit comprising the steps of: forming a first NMOS transistor and a second NMOS transistor; forming a PMOS transistor adjacent the first NMOS transistor in a channel width direction and adjacent the second NMOS transistor in a channel length direction, the PMOS transistor and the first NMOS transistor separated by an isolation region therebetween; depositing and patterning a dummy region positioned between the second NMOS transistor and the PMOS transistor; depositing a compressive stress liner overlying the first NMOS transistor, the PMOS transistor, and the isolation region; etching the compressive stress liner to remove the compressive stress liner from the first NMOS transistor and from a portion of the isolation region; depositing a tensile stress liner overlying the first NMOS transistor, the PMOS transistor, and the isolation region; and selectively etching the tensile stress liner to: remove a portion of the tensile stress liner overlying the compressive stress liner, and leave the tensile stress liner overlying the first NMOS transistor, the isolation region, a portion of the compressive stress liner and a portion of the PMOS transistor.