Patent ID: 8686387

Claim:
A method for manufacturing a semiconductor memory device including a cell array layer having a first wiring, a memory cell laminated on the first wiring, and a second wiring formed to intersect the first wiring on the memory cell, the memory cell including a current control device, a variable resistance device and a metal layer for silicide arranged therebetween, the method comprising: forming a first wiring layer for forming the first wiring; sequentially forming a semiconductor layer for forming the current control device on the first wiring layer, the metal layer for silicide, and a variable resistance device layer for forming the variable resistance device; selectively removing the variable resistance device layer and the metal layer for silicide through first etching until it reaches the semiconductor layer, leaving a part for forming the memory cell; forming a first protective layer to cover at least a side surface of the metal layer for silicide exposed by the first etching; selectively removing the semiconductor layer which has not been removed by the first etching through second etching, leaving a part for forming the memory cell; and forming a second protective layer to cover the variable resistance device layer, the metal layer for silicide, and the semiconductor layer.