Patent ID: 7925798

Claim:
A device comprising: a processor implemented on a chip; an on-chip internal segment memory accessible by the protocol processor; an off-chip external segment memory; a data transfer channel between the internal segment memory and the external segment memory; an off-chip external table memory configured for segment allocation management of the external segment memory; an on-chip internal table memory configured for segment allocation management of the external segment memory; an address transfer channel between the external table memory and the internal table memory; an address transfer management unit operative to transfer segment addresses of memory segments of the external segment memory from the external table memory into the internal table memory and/or to transfer segment addresses of memory segments of the external segment memory from the internal table memory into the external table memory; an input data processing unit for mapping incoming PDUs into an internal data format comprising a first data segment and a second data segment; and an output data processing unit for reassembling first and second data segments of the internal data format into PDUs to be output; wherein the address transfer management unit is configured to: monitor the fill level of the internal table memory; and to initiate a transfer of one or more addresses from the external table memory to the internal table memory if the fill level is lower than a lower threshold value and/or to initiate a transfer of one or more addresses from the internal table memory to the external table memory if the fill level is higher than an upper threshold value, wherein the upper threshold value is greater than the lower threshold value.