Patent ID: 7268419

Claim:
An apparatus for reducing voltage noise for an integrated circuit (IC) device, comprising: an interposer configured to be sandwiched between the IC device and a circuit board; wherein the interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device; and a plurality of bypass capacitors integrated into the interposer and coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device, wherein plates of the plurality of bypass capacitors extend downward from the top surface of the interposer in a direction that is normal to the top surface of the interposer; wherein the interposer is configured to be sandwiched between a package for the IC device and the circuit board; wherein the IC device is bonded to the top surface of the package; and wherein the bottom surface of the package is bonded to the top surface of the interposer.