Patent ID: 7956856

Claim:
A method for generating a display stream for output to a display device comprising: receiving a plurality of link data and a link clock at a video receiver in a packet based video link; writing the plurality of link data into a link data buffer, the plurality of link data being free from timing control; generating a display device clock from the link clock or a reference clock; reading the plurality of link data out of the link data buffer for output to a display device such that a display device timing specification is met and throughput of the link data buffer is balanced, comprising: calculating a normalized link data buffer read period and a normalized display line period; calculating a line threshold, calculating a frame threshold, and calculating a synchronization threshold; and generating a link data buffer read signal based on the line threshold, the frame threshold, the synchronization threshold, the normalized link data buffer read period, the normalized display line period, and a number of entries in the link data buffer available for reading.