Patent ID: 8735220

Claim:
A method for fabricating a re-built wafer comprising chips having connection pads, the method comprising: fabricating a first wafer of chips, producing, on the first wafer, a stack of at least one layer of redistribution of pads of the chips on conductive tracks joining the pads to an exposed side periphery of the chips and designed for interconnection of the chips, the stack being designated a main RDL layer, cutting the first wafer to obtain individual chips, each individual chip including its main RDL layer, transferring the individual chips with their main RDL layer to a sufficiently rigid support to remain flat during the following steps, the rigid support including an adhesive layer, the main RDL layer being over the adhesive layer, depositing a resin over the individual chips to encapsulate the individual chips, polymerizing the resin, removing the rigid support, and depositing a single redistribution layer designated a mini RDL layer to connect the conductive tracks of the main RDL layer to interconnection contacts through apertures made in the adhesive layer, such that the re-built wafer comprises the polymerized resin and the chips with their main RDL layer and their mini RDL layer.