Patent ID: 7930663

Claim:
A design structure embodied in a machine readable medium, said machine readable medium readable by an electronic design automation tool, and said machine readable medium including instructions for execution by the electronic design automation tool in a design process for producing the design structure, the design structure comprising an integrated circuit (IC) that includes circuitry for measuring accurately at least one of set-up time and hold time of a flip-flop included in the IC at a physical location of said flip-flop, the circuitry comprising: a first delay element driven by a first clock and configured to supply a minimal delay or default delay value to a clock input of a first flip-flop having a data value D applied at an input thereof; a second delay element having a selectable delay and configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output Q 0 of the first flip-flop is coupled into the second flip-flop; and a third delay element having a selectable delay and coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output Q 1 of the second flip-flop is coupled to an input of the third flip-flop; wherein the second delayed version of the first clock drives the third flip-flop to monitor delay of the second flip-flop, and wherein possible “pass set-up” state, and “pass hold” state output determined for the second flip-flop based on a final test state of the second and third flip-flops.