Patent ID: 7205185

Claim:
A method of forming a double-gate transistor comprising the steps of: providing a semiconductor wafer having a substrate and a device layer, a back gate dielectric layer adjacent to and below said device layer, a back gate electrode between said back gate dielectric layer and said substrate, a front gate dielectric on said device layer and a front gate electrode layer on said front gate dielectric layer; depositing at least one transfer layer on said front gate electrode layer, patterning said at least one transfer layer with a gate pattern and forming a first gate in said front gate electrode layer using said transfer layer as a mask; forming at least one vertical spacer layer adjacent to opposite sides of said front gate; etching said device layer using said at least one spacer layer as a mask to form a transistor body disposed on said back gate dielectric layer; oxidizing said back gate electrode such that oxide is formed below said transistor body and on either side of a central portion of said back gate electrode, thereby forming said back gate self-aligned with said front gate; and forming source and drain electrodes on opposite sides of said transistor body.