Patent ID: 6881666

Claim:
A method of fabricating a semiconductor device, including at least the steps of: (a) forming a via-hole or trench throughout an electrically insulating layer; (b) forming a wiring material layer on said electrically insulating layer such that said via-hole or trench is filled with said wiring material layer; (c) annealing said wiring material layer; (d) compulsorily cooling said wiring material layer down to a temperature equal to or lower than a predetermined temperature, wherein said predetermined temperature is selected from the group consisting of equal to or about −75 degrees centigrade, equal to or about −100 degrees centigrade, and equal to or about −196 degrees centigrade; and (e) applying chemical mechanical polishing (CMP) to said wiring material layer such that said wiring material layer exists only in said via-hole or trench, wherein said step (c) is carried out prior to said step (e), and said step (d) is carried out after said step (c).