Patent ID: 7030466

Claim:
A semiconductor wafer including an integrated chip scale package to be used for integrated circuits, the wafer comprising: a top surface and a bottom surface; and wherein the semiconductor wafer is an unprocessed wafer having no active circuit layers or interconnect layers present on said top surface or said bottom surface of the semiconductor wafer; a plurality of vias formed in the unprocessed semiconductor wafer, each via having a via top portion beginning at said top surface of the unprocessed semiconductor wafer and extending through to a via bottom portion on said bottom surface of the unprocessed semiconductor wafer; wherein at least some of said plurality of vias include an input/output (I/O) interconnect structure physically and electrically coupled to said via bottom portion, and said I/O interconnect structure is located within an area on the bottom surface of the unprocessed wafer; and wherein the I/O interconnect structure is adapted such that an active circuit which is fabricated on the unprocessed semiconductor wafer as part of an integrated circuit at a later time than the I/O interconnect structure can be electrically connected to another integrated circuit without requiring further packaging operations to form pads or bumps for connecting I/O signals of such active circuit to such another integrated circuit.