Patent ID: 7045893

Claim:
A semiconductor package comprising: a semiconductor die comprising a first surface having an approximately planar shape and a second surface formed in opposition to the first surface and having a plurality of bond pads, each bond pad comprising a first bond pad formed at a center of the bond pad and a second bond pad spaced from the first bond pad by a predetermined distance while at least partially surrounding the first bond pad; a substrate comprising a first surface having an approximately planar shape and a second surface formed in opposition to the first surface, the first surface of the substrate being formed with a plurality of electrically conductive patterns having shapes corresponding to shapes of the bond pads; a plurality of posts comprising a first post formed on the first bond pad and a second post formed on the second bond pad; and an internal insulative layer formed between the first post and the second post of the plurality of posts, the insulative layer having a height approximately equal to a height of the first post, wherein; the plurality of posts comprising a first post formed on the first bond pad and a second post formed on the second bond pad are bonded to the electrically conductive patterns of the substrate so as to electrically connect the substrate to the semiconductor die.