Patent ID: 8026754

Claim:
An electronic circuit comprising: a precharge circuit configured to precharge a first node in response to an occurrence of a first phase of a timing signal; a discharge circuit configured to conditionally discharge the first node in response to an occurrence of a second phase of the timing signal depending upon a data input signal; a voltage retention circuit configured to store a retained logic value that depends upon a logic value present at the first node during at least a portion of the second phase of the timing signal, wherein the voltage retention circuit includes a latch circuit and a delay circuit coupled between the first node and an input of the latch circuit; and an output circuit configured to generate an output signal that depends upon the data input signal, wherein the output circuit is configured to drive the output signal in a first logic state when the first node is discharged regardless of the retained logic value, and wherein the output circuit is configured to drive the output signal in a logic state that depends upon the retained logic value when the first node is charged; wherein the output circuit includes a NAND gate having a first input coupled to the first node and a second input coupled to receive the retained logic value from the voltage retention circuit.