Patent ID: 8437424

Claim:
An apparatus comprising: a feedback pipeline; a buffer pipeline that is coupled to the feedback circuit; a digital predistortion (DPD) circuit that is configured to receive an input signal and that is configured to generate a predistorted signal from the input signal and predistortion coefficients; an equalizer that is coupled to the DPD circuit; a mixer that is coupled to the equalizer; a digital-to-analog converter (DAC) interface that is coupled to the mixer; a delay element that is configured to receive an amplified signal and that is configured to provide a delayed output signal; a delay estimator that is configured to receive the delayed output signal and the predistorted signal and that is configured to generate a delay estimation by determining a peak value from a polynomial curve fit of values from a cross-correlation function of the delayed output signal, wherein the values of the cross-correlation function are greater than a predetermined threshold; and a DPD adapter that is configured to receive the delay estimation and that is configured to generate the predistortion coefficients.