Patent ID: 7825027

Claim:
A method for manufacturing a memory device comprising: forming, above a base substrate, a plurality of ferroelectric capacitors in a ferroelectric memory array region to provide the ferroelectric memory array region with a high density of ferroelectric capacitors relative to a logic circuit region; forming a wiring layer above the base substrate in the logic circuit region, the logic circuit region entirely surrounding the ferroelectric memory array region when viewed in plan; forming an interlayer dielectric layer that entirely covers the ferroelectric memory array region and the logic circuit region, a height of the interlayer dielectric layer relative to the base substrate in the ferroelectric memory array region being greater than a height of the interlayer dielectric layer relative to the base substrate in the logic circuit region due to the high density of ferroelectric capacitors; etching the interlayer dielectric layer formed at least in the ferroelectric memory array region to form a concave section that lowers the height of the interlayer dielectric layer in the ferroelectric memory array region to proximate the height of the interlayer dielectric layer in the logic circuit region; polishing the interlayer dielectric layer by a CMP (chemical mechanical polishing) method so that the height of the interlayer dielectric layer in the ferroelectric memory array region is equal to the height of the interlayer dielectric layer in the logic circuit region; etching the interlayer dielectric layer above the ferroelectric capacitors and the wiring layer to form contact holes; and forming contact sections in the contact holes.