Patent ID: 7787474

Claim:
A method for performing deep packet processing by at least one processor on an input variable word bit chain, said method comprising steps of: creating by said processor a state table in a memory having state table entries—based on at least one initial state, and a final state, each state table entry defining a state-transition rule comprising a s-bit current state, a n-bit word of the input variable word bit chain and a s-bit next state; converting the state table entries into a reduced state table having a reduced number of state-transition rule entries, each entry of the reduced state table containing the s-bit next state and a ternary match condition expressed as a s+n-bit test value and a s+n-bit test mask to be applied to the s-bit current state and the n-bit word of the input variable word bit chain in combination; ordering the entries of the reduced state table, in a prioritized order, with most frequently used state-transition rules having the highest priority; initializing the s-bit current state as being the initial state and a first word of the input variable word bit chain being a current input word; testing the s-bit current state and the current input word in combination, against the test value, using the test mask, in all the entries of the reduced state table until a match is identified for at least one entry; if multiple entries match, selecting one entry with the highest priority; if the next state read in the state-transition rule of the identified matched entry is not a final state, defining a next word of the input variable word bit chain as being the current input word and the next state being the s-bit current state; and repeating the testing, selecting and defining steps until a final state is found.