Patent ID: 7606692

Claim:
A method for analyzing a circuit design in preparation for a simulation, comprising the steps of: (A) marking in a memory each of a plurality of modules between a target module of said modules and a top module of said modules inclusively in a hierarchy of said circuit design as a first type by traversing upward in said hierarchy starting from said target module; (B) marking in said memory each of said modules as a second type where a parent module of said modules is marked as said first type by traversing downward in said hierarchy starting from said top module; (C) marking in said memory each of said modules as a third type where said parent module is marked as one of (i) said second type and (ii) said third type by traversing downward in said hierarchy starting from said top module; and (D) generating a netlist of said circuit design in said memory, wherein (i) said first type designates said simulation in a full form, (ii) said second type designates said simulation in a black-box form and (iii) said third type designates a non-simulation form.