Patent ID: 8498145

Claim:
A semiconductor storage device comprising: a plurality of bit lines; a plurality of word lines; and a plurality of memory cells, each memory cell including a memory element configured to store data based on a difference between resistance values of the memory element, and the plurality of memory cells connected between a first and a second bit line, wherein the plurality of memory cells arranged in a direction of the bit lines constitute columns, the second bit line is shared by two columns adjacent to each other, a first set of memory cells in a first pair of columns sharing the second bit line are arranged to be shifted in the direction of the bit lines by a half-pitch of a second set of memory cells in a second pair of columns adjacent to the first pair of columns, a dummy cell arranged between the two adjacent paired columns, and having an equal distance from the adjacent memory elements; and a row decoder configured to: drive the first set of memory cells in the first pair of columns by applying a voltage to two adjacent paired word lines WLk and WLk+1, where k is an integer, and drive the second set of memory cells in the second pair of columns by applying the voltage to two adjacent and paired word lines WLk+1 and WLk+2; wherein each of the plurality of memory cells includes a plurality of selection transistors for each of the memory elements, the selection transistors connected in parallel between the memory element corresponding to the selection transistors and the first bit line, and wherein gates of the transistors are connected to different word lines, respectively.