Patent ID: 6838335

Claim:
A method for fabricating a vertical transistor, which comprises the steps of: providing a monocrystalline semiconductor substrate having at least one trench formed therein with a lower section and an upper section, at least the lower section of the trench being lined with a storage dielectric and filled with at least one conductive material; forming an auxiliary insulation layer on the conductive material; depositing an epitaxial semiconductor layer on uncovered sidewalls of the upper section of the trench; removing the auxiliary insulation layer; conformally depositing a nitride layer, the nitride layer being so thin that it only partially impairs a current flow; filling the trench with a doped further conductive material for producing an electrical connection between the conductive material situated in the lower section and a lower partial section of the epitaxial semiconductor layer, the lower partial section of the epitaxial semiconductor layer being doped by indiffusion of dopants from the further conductive material to form a first doping region; forming a gate dielectric on uncovered regions of the epitaxial semiconductor layer; forming a gate electrode on the gate dielectric; and forming a second doping region in an upper partial section of the epitaxial semiconductor layer.