Patent ID: 8559233

Claim:
A semiconductor memory device, comprising: a memory cell array configured to comprise even cell strings coupled to respective even bit lines and odd cell strings coupled to respective odd bit lines; even page buffers coupled to even memory cells of the memory cell array through the respective even bit lines; odd page buffers coupled to odd memory cells of the memory cell array through the respective odd bit lines; first BL selectors, each configured to couple each of the even bit lines to the respective even page buffers in order to store data in the even memory cells or read data stored in the even memory cells, and to couple each of the even page buffers to respective odd bit lines so that the even and odd page buffers precharge the odd bit lines in a precharge operation for the odd bit lines; and second BL selectors, each configured to couple each of the odd bit lines to the respective odd page buffers in order to store data in the odd memory cells or read data stored in the odd memory cells, and to couple each of the odd page buffers to respective even bit lines so that the even and odd page buffers precharge the even bit lines in a precharge operation for the even bit lines.