Patent ID: 8748281

Claim:
A method, comprising: forming a gate electrode structure of a transistor above a semiconductor region of a semiconductor device, said gate electrode structure comprising a gate insulation layer comprising a high-k gate dielectric material, a metal-containing cap material formed on said gate insulation layer, an electrode material formed above said cap material and a dielectric cap layer comprised of silicon dioxide formed above said electrode material; forming a first spacer structure comprised of silicon nitride on sidewalls of said gate electrode structure; performing a first implantation process to form drain and source extension regions by using at least a portion of said gate electrode structure and said first spacer structure as a first implantation mask; after performing said first implantation process, reducing a size of said first spacer structure; after reducing said size of said first spacer structure removing said dielectric cap layer by using said reduced-size first spacer structure as an etch stop material; after removing said dielectric cap layer, forming a second spacer structure on said reduced-size first spacer structure; and performing a second implantation process to form drain and source regions by using said second spacer structure as a second implantation mask.