Patent ID: RE40904

Claim:
An apparatus for generating target addresses within a circular buffer extending in a memory between bounds defined by a base address and an end address, the base address being any predetermined location in the memory, responsive to the next previous address , I, accessed within said circular buffer , I, and a specified offset, M, comprising: a first register for storing the previous address accessed within said buffer, I; a second register means for storing information which defines the position and size of said circular buffer in memory , said second register means comprising an L register for storing the length of the circular buffer, L, and a B register for storing the base address of the circular buffer, B ; a third register for storing a specific offset value, M a first logic circuit for generating an absolute address by calculating the value of I+M , wherein M is positive and said first logic circuit comprises an adder having a first input connected to accept the output of said first register, a second input connected to accept the output of said third register and an output which provides the sum of the values applied to first and second inputs ; a second logic circuit for generating a wrapped address by modifying the value I+M by the length of the buffer , said second logic circuit comprising a subtracter having a first input coupled to the output of said L register, a second input coupled to the output of said adder and an output which is the difference between the inputs, I+M−L ; a comparator for comparing one of the absolute address and wrapped address with a boundary of said circular buffer to determine whether one of said absolute address and said wrapped address is between the bounds of the circular buffer , said comparator having a first input coupled to the output of said subtracter, I+M−L, a second input coupled to the output of said B register, B, and an output which in a first state when said first input is greater than or equal to said second input and in a second state otherwise ; and means for loading said first register with the one of the absolute address and the wrapped address which is within the bounds of the circular buffer , said means for loading comprising a multiplexer having a first input coupled to the output of said adder, I+M, a second input coupled to the output of said subtractor, I+M−L, and a third input coupled to the output of said comparator and having an output coupled to the input of said I register, said output being the value at said first input responsive to said comparator output being in said second state and being the value at said second input responsive to said comparator output being in said first state .