Patent ID: 7774529

Claim:
A bus communication apparatus, comprising: a shared memory; a memory control unit operable to (a) arbitrate a plurality of commands, each of the plurality of commands instructing access to the shared memory, so as to give an access right to one of the plurality of commands, (b) output an arbitration completion signal showing that arbitration, with respect to the one command given the access right, is complete, (c) access the shared memory, based on the one command given the access right, and (d) when the accessing of the shared memory based on the one command given the access right is complete, output an access completion signal showing a completion of the accessing of the shared memory; a communication origin master operable to output a write command instructing a writing of target data to the shared memory, programmably select one of the arbitration completion signal and the access completion signal, and, based on the selected one of the arbitration completion signal and the access completion signal, output a permission signal showing that issuing of a command is permitted; and a communication destination master operable to output, based on the permission signal, a read command instructing a reading of the target data from the shared memory, wherein the communication origin master, in addition to outputting the write command, outputs a generation instruction signal instructing the read command to be generated, and after providing a time delay after the output of the generation instruction signal, outputs the permission signal showing that issuing of the read command is permitted, and wherein the communication destination master generates the read command, based on the generation instruction signal, and outputs the generated read command, based on the permission signal.