Patent ID: 7560800

Claim:
A die seal structure formed on a semiconductor substrate comprising: a junction diode formed within the semiconductor substrate, the junction diode including a doped region that is doped with the opposite type of dopant as the semiconductor substrate; a first metal layer, a first portion of the first metal layer extending over the junction diode and extending around integrated circuit devices formed on the semiconductor substrate; a first contact that extends around the integrated circuit devices, the first contact coupled to the first portion of the first metal layer, the first contact extending between the first portion of the first metal layer and the top surface of the semiconductor substrate, and only electrically coupling to the semiconductor substrate through the doped region of the junction diode; a second contact that extends around the first contact, the second contact coupled to the first portion of the first metal layer and extending between the first portion of the first metal layer and the top surface of the semiconductor substrate, the first portion of the first metal layer extending laterally between the first contact and the second contact, the second contact only electrically coupling to the semiconductor substrate through the doped region of the junction diode; a plurality of additional metal layers, a first portion of each of the plurality of additional metal layers extending over the first portion of the first metal layer and extending around the integrated circuit devices, each first portion of an additional metal layer electrically isolated from other portions of each of the plurality of additional metal layers; a first plurality of vias, each of the first plurality of vias extending between adjoining metal layers of the first metal layer and the plurality of additional metal layers, the first plurality of vias positioned such that they directly overlie the first contact; and a second plurality of vias, each of the second plurality of vias extending between adjoining metal layers of the first metal layer and the plurality of additional metal layers, the second plurality of vias positioned such that they directly overlie the second contact, each first portion of an additional metal layer only electrically coupled to the semiconductor substrate through the junction diode.