Patent ID: 6838320

Claim:
A method of manufacturing a semiconductor integrated circuit device having first MISFETs and second MISFETs formed over a semiconductor substrate, comprising the steps of: (a) providing the semiconductor substrate including a first area and a second area; (b) forming a first gate electrode of the first MISFET and a second gate electrode of the second MISFET in the first area and the second area respectively; (c) forming a first semiconductor region and a second semiconductor region of the first MISFET in the first area; (d) forming a third semiconductor region and a fourth semiconductor region of the second MISFET in the second area; (e) forming a first insulating film over the first gate electrode, the first and second semiconductor regions, the second gate electrode, and the third and fourth semiconductor regions; (f) removing the first insulating film over the third and fourth semiconductor regions, leaving the first insulating film in the first area; (g) after the step (f), forming a metal film over the first insulating film in the first area and on the third and fourth semiconductor regions; (h) performing a thermal treatment to form silicide films of the metal film on the third and fourth semiconductor regions, and not on the first and second semiconductor regions; (i) after the step (h), removing a part of the metal film which is not silicided in the step (h); (j) after the step (i), forming an interlayer insulating film over the first area and the second area; (k) etching the interlayer insulating film to form a first contact hole and a second contact hole in a self-alignment manner with the adjacent first gate electrodes in the first area; and (i) forming a first conductive film and a second conductive film in the first contact hole and the second contact hole respectively, electrically connected to the first and second semiconductor regions respectively.