Patent ID: 8525255

Claim:
A semiconductor power device comprising: a plurality of power transistor cells disposed in an active area near a top surface of an epitaxial layer of first conductivity type grown on a semiconductor substrate of said first conductivity type wherein each of said transistor cells is surrounded by trenched gates; multiple trenched floating gates disposed in a termination area surrounding said active area and each of said trenched floating gates having a floating voltage wherein said trenched floating gates further penetrating through a body region and extending into said epitaxial layer; said trenched gates and said multiple trenched floating gates comprising a conductive material padded by a gate insulation layer filled in trenches, wherein said gate insulation layer having a thick bottom oxide on bottom surface of said trenches with a thickness greater than sidewall oxide along sidewall of said trenches; said body region of a second conductivity type formed in both said active cell area and said termination area disposed immediately adjacent to said trenched floating gates; said trenched gates further extended to wider trenched gates in a gate contact area having a greater trench width than said trench gates in said active cell area for electrically connecting to a gate metal; and a source region of said first conductivity type disposed only in said power transistor cells in said active area but not in said termination area comprising said multiple trenched floating gates and no source regions disposed in said epitaxial layer regions adjacent to said wider trenched gate in said gate contact area.