Patent ID: 7622979

Claim:
A method for operating a timing-constrained circuit, comprising: generating a first signal comprising a first delay from a reference edge under a first operating condition and a second delay from the reference edge under a second operating condition; generating a second signal comprising a third delay from the reference edge under the first operating condition and a fourth delay from the reference edge under the second operating condition; identifying an existence of the first operating condition; selecting the first signal as a timing signal for the timing-constrained circuit in response to identifying the first operating condition; identifying an existence of the second operating condition after identifying an existence of the first operating condition; selecting the second signal as the timing signal for the timing-constrained circuit in response to identifying the second operating condition; identifying an existence of the first operating condition after identifying an existence of the second operating condition; and selecting the first signal as the timing signal for the timing-constrained circuit in response to identifying the first operating condition, after identifying the second operating condition.