Patent ID: 8513131

Claim:
A method of forming an integrated circuit (IC), the method comprising: forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers, wherein forming the first and second plurality of spacers on a substrate comprises: forming a plurality of mandrels on the substrate; depositing a spacer material over the mandrels; depositing a hardmask over the spacer material; removing a first portion of the hardmask from a first area of the spacer material corresponding to the first plurality of spacers; etching the spacer material from which the first portion of the hardmask is removed for a first etch time to form the first plurality of spacers; removing a second portion of the hardmask from a second area of the spacer material corresponding to the second plurality of spacers; etching the spacer material from which the second portion of the hardmask a removed for a second etch time to form the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.