Patent ID: 8772102

Claim:
A method, comprising: forming sacrificial gate structures for first and second spaced-apart transistors above a semiconducting substrate; forming an etch stop layer above said substrate and said sacrificial gate structures for said transistors; performing at least one angled ion implant process to implant at least one etch-inhibiting species into less than an entirety of said etch stop layer; after performing said at least one angled ion implant process, forming a layer of insulating material above said etch stop layer; performing at least one chemical mechanical polishing process to expose at least a portion of each of said sacrificial gate structures; performing at least one first etching process to remove said sacrificial gate structures and thereby define a plurality of gate cavities; forming a replacement gate structure in each of said cavities; forming a hard mask layer above said replacement gate structures and said layer of insulating material; performing a second etching process on said hard mask layer to define a patterned hard mask layer, wherein an entire upper surface of said hard mask layer is exposed to said second etching process; performing at least one third etching process through said patterned hard mask layer to define an opening in said layer of insulating material and thereby expose a portion of said etch stop layer; performing a fourth etching process on said exposed portion of said etch stop layer to define a contact opening therethrough that exposes a doped region formed in said substrate; and forming a conductive contact in said opening that is conductively coupled to said doped region.