Patent ID: 8645896

Claim:
A method for an integrated circuit (IC) design facility to transfer design and layout format to an external facility, for failure analysis or circuit edit of an IC chip, comprising the steps of: creating a GDS-based failure analysis (FA)-specific or circuit edit (CE)-specific physical target file by using a computer, said FA-specific or circuit edit-specific physical target file including minimum design-specific information required to enable effective failure analysis or circuit edit; configuring said GDS-based physical target file to enable said external facility to overlay said GDS-based physical target file on GDS mask data for said IC chip; and providing said GDS-based physical target file to said external facility; wherein said GDS-based physical target file is created by querying a cross-mapping database generated from LEF/DEF files; and wherein said LEF/DEF conversion to a cross-mapping database is done for DEF components only, omitting nets and special nets.