Patent ID: 8601288

Claim:
An interconnect for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, comprising: a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; individual domain controllers, comprising hardware logic of the power manager, to transition components in an appropriate domain in the integrated circuit into and out of a desired power consuming mode, and cooperates with a software based power management component including an operating system; wherein the power manager has its own 1) dedicated CPU, 2) dedicated state machine or 3) any combination of the two to execute power management instructions; wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute the power management instructions; and wherein each domain controller is configured with conflict resolution logic on how to control the desired power consuming mode of its domain that includes a shared resource by the IP cores of the integrated circuit when one or more power management policies being implemented overlap to control the power consuming mode of the shared resource.