Patent ID: 7535759

Claim:
A flash memory system comprising: a processor for generating density configuration bits for the memory system, the processor configured to generate the density configuration bits in response to reading data that indicate a function of the memory and not a particular memory density and the processor further configured to access a table in memory that stores the density configuration with an associated function of the memory; and a plurality of flash memory dies coupled to the processor, each die having selectable density configurations and comprising: a flash memory array comprising a plurality of memory cells that are organized into predetermined sets of memory cells, each memory cell capable of storing a selectable quantity of data bits; control circuitry, coupled to the memory array and the processor, that configures the density configurations for the predetermined sets of memory cells in response to the density configuration bits and the table; a non-volatile configuration register, coupled to the control circuitry, for storing the density configuration bits; and a volatile configuration register, coupled to the non-volatile configuration register, that receives the density configuration bits from the non-volatile configuration register.