Patent ID: 6960492

Claim:
A method of manufacturing a semiconductor device having a number of wiring layers, comprising: forming an underlayer, the underlayer including a substrate, at least one underlayer wiring layer having a wire portion formed in an upper wiring trench and a plug portion formed in a lower via hole continuous with the upper wiring trench formed in an interlayer insulation film provided on the substrate, and a first attachment surface in which an upper surface of the wire portion of the underlayer wiring layer is exposed; forming at least one upper structure, the upper structure including at least one upper wiring layer having a wire portion formed in an upper wiring trench and a plug portion formed in a lower via hole continuous with the upper wiring trench formed in an interlayer insulation film and a second attachment surface in which a lower surface of the plug portion of the upper wiring layer is exposed; and linearly arranging the exposed lower surface of the plug portion of the upper structure and the exposed upper surface of the wire portion of the underlayer and attaching the first and second attachment surfaces to each other.