Patent ID: 8921175

Claim:
A process of forming an electronic device including a nonvolatile memory cell comprising: forming a field isolation region within a substrate to define first, second, and third active regions, wherein the first, second, and third active regions are spaced apart from one another; forming a floating gate electrode over the substrate and a part of the field isolation region, wherein the floating gate includes: a first portion disposed over the first active region; a second portion disposed over the second active region; and a third portion disposed over the third active region; forming an access gate electrode over the third active region, wherein the access gate electrode and the floating gate electrode are spaced apart from each other; forming an intermediate doped region within the second active region and adjacent to the floating gate electrode, wherein the intermediate doped region has a first conductivity type; forming a first heavily doped region within the second active region, wherein the first heavily doped region has the first conductivity type and a dopant concentration that is higher than the dopant concentration of the first intermediate doped region; and forming a second heavily doped region within the second active region, wherein the second heavily doped region has a second conductivity type opposite the first conductivity type, and a dopant concentration that is higher than the dopant concentration of the first intermediate doped region, wherein forming the intermediate doped region and the first and second heavily doped regions are performed such that, from a top view, the first heavily doped region is disposed between the intermediate doped region and the second heavily doped region.