Patent ID: 7534667

Claim:
A method of fabricating a transistor structure, comprising the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of said substrate by a buried dielectric layer; (b) first implanting said SOI layer to achieve a predetermined dopant concentration at an interface of said SOI layer to said buried dielectric layer; (c) second implanting said SOI layer to achieve predetermined dopant concentrations in a polycrystalline semiconductor gate conductor (“poly gate”) and in source and drain regions disposed adjacent to said poly gate, wherein a maximum depth of said first implanting is greater than a maximum depth of said second implanting; and (d) said first and second implanting are conducted by performing said first implanting using said poly gate as a mask while a dielectric cap masks said poly gate from said first implanting, and then removing said dielectric cap prior to performing said second implanting step.