Patent ID: 7930688

Claim:
A system for scheduling multiple groups of instructions in a computer program for execution on a processor in said system, said processor being schedulable using a looped schedule, comprising: (a) means for identifying independent, and identical groups of instructions in said computer program; (b) means for counting a number of said groups of instructions identified in (a); (c) means for identifying a minimum number of cycles in which scheduling is completed on said processor in said looped schedule; (d) means for calculating, in dependence upon the number of said groups of instructions counted in (b) and said minimum number of cycles identified in (c), a starting cycle location in said looped schedule for each of said groups of instructions; wherein (a) comprises means for identifying independent identical sub-graphs in a data dependency graph (DDG) corresponding to said computer program, said sub-graphs corresponding to said groups of instructions; wherein (b) comprises means for counting the number of independent, identical sub-graphs of a given type; wherein in (c) said minimum number of cycles in which scheduling is completed on said processor is calculated based on the number of independent, identical sub-graphs of the given type counted in (b), and based on maximum usage of operational performance characteristics of said processor, wherein the system further comprises: means for assigning the sub-graphs of the given type a count number, beginning with 0, and calculating said starting cycle location for each said sub-graph dependent upon the following function: ceil((this sub-graph's count number)*(initiation interval)/(total number of sub-graphs of this type)); where “ceil(n)” rounds the value ‘n’ up to the nearest integer, and said initiation interval is the minimum number of cycles in which scheduling is completed on said processor in said looped schedule, as calculated in (d).