Patent ID: 7675109

Claim:
A vertical channel transistor device comprising: a semiconductor substrate having a main surface, and the main surface having a cavity therein; a drain having a first conductivity type formed inside the cavity; a vertical silicon channel having a second conductivity type grown on the drain and extending from the main surface of the semiconductor substrate, wherein the vertical silicon channel comprises a top surface, a first vertical surface, and a second vertical surface opposite to the first vertical surface; a first spacer stacked on the top surface of the vertical silicon channel; a gate dielectric layer covering the first vertical surface of the vertical silicon channel; a gate formed on the gate dielectric layer and bordering the first spacer; a second spacer covering the drain and the second surface of the vertical silicon channel, wherein the second spacer exposes a portion of the second vertical surface; a silicon layer having the second conductivity type grown inside the cavity and covering the second spacer, and bordering the exposed portion of the second vertical surface; a source having the first conductivity type grown on the silicon layer; and an insulation top layer covering the source.