Patent ID: 8358261

Claim:
A liquid crystal display (LCD) device, comprising a LCD panel, said LCD panel comprising: a plurality of scan lines; a gate driving circuit; and a clock circuit, said clock circuit comprising: a clock generator for generating a clock signal having a first high voltage level and a first low voltage level; and an adjusting circuit, coupled to said clock generator, for receiving said clock signal and generating an adjusted clock signal, said adjusted clock signal having the same period as said clock signal and having a second high voltage level and a second low voltage level; wherein said clock signal has a first transition period from said first low voltage level to said first high voltage level, said adjusted clock signal has a second transition period from said second low voltage level to said second high voltage level, and said first transition period is shorter than said second transition period; wherein said gate driving circuit, coupled to said clock circuit, receives said adjusted clock signal as a gate driving signal in order to drive said scan lines; wherein said adjusting circuit comprises: a divider; and a CMOS inverter, said CMOS inverter comprising: a PMOS, a source of said PMOS receiving a high level signal carrying said second high voltage level; and a NMOS, a source of said NMOS receiving a low level signal carrying said second low voltage level; wherein said divider is connected to the gate of said PMOS, said clock signal is divided by said divider and is received by said divider and said gate of said NMOS to form gate-source voltages (Vgs) on said NMOS and said PMOS, and said adjusted clock signal is outputted from drains of said NMOS and said PMOS.