Patent ID: 7426630

Claim:
A processor comprising: a register file having a swap interface to switch register windows in the register file; register management logic coupled to the register file, wherein the register management logic is configured to control the swap interface in response to window swap operations; and at least two sources of window swap operations, each of the at least two sources coupled to the register management logic, wherein the at least two sources and the register management logic are configured to cooperate according to an arbitration scheme to arbitrate between conflicting window swap operations to be performed using the swap interface, wherein the register management logic is configured to perform, on the swap interface, the window swap operation that wins the arbitration, and wherein a first source of the at least two sources comprises an execution unit configured to execute an instruction that causes at least two window swap operations if the instruction experiences an exception and wherein one of the at least two window swap operations is arbitrated using the arbitration scheme.