Patent ID: 7391232

Claim:
An apparatus for selectively extending lifetime reliability of digital logic devices, comprising: complementary metal oxide semiconductor (CMOS) circuitry configured between a logic high supply rail and a logic low supply rail; a first switching device coupled between one of the logic high supply rail and the logic low supply rail and a first virtual supply rail coupled to the CMOS circuitry, and a second switching device coupled between the first virtual supply rail and the other of the logic high supply rail and the logic low supply rail; wherein, in a normal mode of operation, the first switching device is rendered conductive and the second switching device is rendered nonconductive so as to supply the full voltage value between the logic high supply rail and the logic low supply rail to the CMOS circuitry, and wherein, in an intense recovery mode of operation, the first switching device is rendered nonconductive so as to isolate the first virtual supply rail from the one of the logic high supply rail and the logic low supply rail, and the second switching device is rendered conductive so as to equalize the voltage on the virtual supply rail and the other of the logic high supply rail and the logic low supply rail; and at least one device within the CMOS circuitry configured, in the intense recovery mode of operation, to provide one of the logic high voltage and the logic low voltage to a gate terminal of a first field effect transistor (FET) within the CMOS circuitry, with a source terminal of the first FET coupled to the virtual supply rail, such that the first FET is subjected to a full rail reverse bias condition.