Patent ID: 7605875

Claim:
A thin film transistor array panel, comprising: a gate wire including a plurality of gate lines, a plurality of gate electrodes, and a plurality of gate pads and formed on an insulating substrate; a gate insulating layer covering the gate wire; a semiconductor layer formed on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer; a data wire formed on the ohmic contact layer, wherein the data wire includes a plurality of data lines intersecting the gate lines, a plurality of source electrodes connected to the data lines and extending onto the gate electrodes, a plurality of drain electrodes located opposite the source electrodes with the gate electrodes therebetween and a plurality of data pads; a protection layer formed on the data wire and the semiconductor layer, and having a plurality of first contact holes exposing the drain electrodes; and a plurality of pixel electrodes connected to the drain electrodes through the first contact holes formed directly over a storage wire formed on the substrate, wherein the ohmic contact layer extends substantially along the data lines, the gate wire has a taper structure, and the protection layer covers the semiconductor layer between the source electrode and the drain electrode, and each of the pixel electrodes overlaps its own gate line.