Patent ID: 7408216

Claim:
A memory device comprising: a plurality of memory cells, each of the plurality of memory cells, including, a vertical transistor including a first source/drain region, a body region, and a second source/drain region, wherein an entire of the first source/drain region, an entire of the body region, and an entire of the second source/drain region form a pillar and are vertically aligned in the pillar; a trench capacitor having a first capacitor plate coupled to the second source/drain region without an intervening conductor, and a second capacitor plate formed in a trench, the first capacitor plate having an etch-roughened surface, the second capacitor plate surrounding at least a portion of the first capacitor plate; and an insulator separating the second capacitor plate from the etch-roughened surface of the first capacitor plate, wherein the vertical transistor further includes a gate directly above the second capacitor plate and adjacent to the body region.