Patent ID: 7673204

Claim:
A method using non-linear data compression in generating a set of test vectors for use in scan testing an integrated circuit, wherein said method comprises the steps of: initially designing, by a tester, said set of test vectors; selecting one of multiple available coding schemes for each test vector, wherein at least two of the coding schemes selected for encoding are different from one another, and wherein one of the available coding schemes represents non-encoded data; generating, by a random pattern generator, data blocks, each corresponding to one of said test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern to represent the coding scheme of said given test vector, and at least one of said corresponding data blocks has a bit length that is less then the bit length of said given test vector; routing each of said data blocks to a plurality of decoders, wherein each decoder is adapted to recognize only one of said coding schemes by detecting the bit pattern representing a given coding scheme; and decoding, by the decoder recognizing the coding scheme of the data block, the bit pattern of the data block and generating said test vector corresponding to the data block, for use in scan testing the integrated circuit.