Patent ID: 7720186

Claim:
A system comprising: A. a serial data input lead; B. a serial data output lead; C. a first set of first circuits, each first circuit having a serial data input, a serial data output, a clock input, and a mode select input, each first circuit including state circuitry responsive to signals received on the clock input and mode select input for the first circuit to remain in an idle state where no data communication occurs and to enter a communication state where data is communicated between the serial data input and serial data output, with the serial data input, or with the serial data output, the first set of first circuits being connected together in series through their serial data outputs and serial data inputs, the serial data input of the first circuit in the first set being connected with the serial data input lead, and the serial data output of the last circuit in the first set being connected with the serial data output lead, the clock inputs of all the first circuits in the first set being connected together, and the test mode select inputs of all the first circuits in the first set being connected together; D. a second set of second circuits, each second circuit having a serial data input, a serial data output, a clock input, and a mode select input, each second circuit including state circuitry responsive to signals received on the clock input and mode select input for the second circuit to remain in an idle state where no data communication occurs and to enter a communication state where data is communicated between the serial data input and serial data output, with the serial data input, or with the serial data output, the second set of second circuits being connected together in series through their serial data outputs and serial data inputs, the serial data input of the first circuit in the second set being connected with the serial data input lead, and the serial data output of the last circuit in the second set being connected with the serial data output lead, the clock inputs of all the second circuits in the second set being connected together, and the test mode select inputs of all the second circuits in the second set being connected together; D. a test clock and test mode select lead connected with the test clock inputs of all the first set of first circuits and with the test mode select inputs of all the second set of second circuits; and E. a test mode select and test clock lead connected with the test clock inputs of all the second set of second circuits and with the test mode select inputs of all the first set of first circuits.