Patent ID: 7694099

Claim:
A memory controller having an interface for providing a connection to a plurality of memory devices, at least one of said plurality of memory devices supporting burst mode data transfers, said memory controller comprising data interface circuitry coupled to a plurality of separate data buses to communicate data signals between said memory controller and a respective one of said memory devices, each of said data buses providing a dedicated data signal path to a different one of said memory devices; address interface circuitry coupled to a common address bus to communicate address signals to each of said memory devices on a shared address signal path, address signals which are directed to different ones of said memory devices being time division multiplexed together on said common address bus; and device selecting circuitry coupled to one or more device selecting lines to communicate one or more device selecting signals synchronised with said time division multiplexing of said common address bus to select that memory device to which address signals currently asserted on said common address bus are directed, wherein said memory controller is arranged to sequentially receive a plurality of burst of data, and said data interface circuitry is arranged to concurrently communicate data signals of different ones of said plurality of bursts of data from said memory controller to said plurality of memory devices using said plurality of separate data buses, address signals corresponding to concurrently communicated data signals are communicated successively to said respective memory devices over said time division multiplexed common address bus.