Patent ID: 7349285

Claim:
A system comprising: a first processor issuing a first memory access request; a second processor issuing a second memory access request; and a dual port memory comprising: a first port and a second port respectively receiving said first memory access request and said second memory access request, wherein said first memory access request and said second memory access request are processed in a single memory cycle; a single port memory core; a port handler interfacing with said single port memory core to perform said first memory access request and then said second memory access request, wherein said port handler comprises: a first multiplexer coupling a first access address and then a second access address to said single port memory, wherein said first access address and said second access address respectively specify locations in said single port memory core where a corresponding memory access request is to be performed; a first flip-flop latching said second access address, wherein an output of said first flip- flop is connected as one input of said first multiplexer; and wherein said first flip-flop latches said second access address in response to a memory clock signal at a first logic level and an enable signal indicating that said second memory access request is available on said second port.