Patent ID: 8188529

Claim:
A semiconductor device, comprising: a memory cell region; a peripheral circuit region; a boundary region formed in a boundary between the memory cell region and the peripheral circuit region; and an interlayer insulating film formed across the peripheral circuit region and the boundary region, wherein the memory cell region comprises: a concave lower electrode formed so as to extend upwardly from below plane-A having level equal to an upper surface of the interlayer insulating film and protruding by a height of H above the plane-A; and a foundation layer having a thickness of H formed at least in part on the plane-A other than the part thereof taken up by the lower electrode, the boundary region comprises: one concave lower conductive region formed so as to extend upwardly from below plane-A having level equal to the upper surface of the interlayer insulating film and protruding by a height of H above the plane-A; and the foundation layer having a thickness of H formed on the upper surface of the interlayer insulating film, and the memory cell region and the boundary region comprise: a dielectric film formed so as to cover surfaces of the lower electrode, the lower conductive region and the foundation layer; and an upper conductive region including a conductive layer formed so as to have contact with an uppermost surface of a portion of the dielectric film over the plane-A and the interlayer insulating film, and a convex portion branching off from the conductive layer and disposed facing to the lower electrode and the lower conductive region with an intervention of the dielectric film therebetween.