Patent ID: 7769943

Claim:
In a non-volatile memory integrated circuit, a method for executing test instructions from on-chip testing circuitry including a microcontroller including; providing, in a first mode of operation, instructions to be executed by the microcontroller from an instruction set disposed in an on-chip ROM; providing, in a second mode of operation, instructions to be executed by the microcontroller from an off-chip source; and switching between the first mode of operation and the second mode of operation in response to commands provided from off chip, wherein providing, in a second mode of operation, instructions to be executed by the microcontroller from an off-chip source includes loading instructions to be executed by the microcontroller from an off-chip source to a group of t-latches disposed on the integrated circuit, wherein switching between the first mode of operation and the second mode of operation comprises providing the instructions to be executed by the microcontroller from an on-chip switch instruction circuit coupled to the ROM and to the group of t-latches, and wherein a number of instructions greater than the number of t-latches is provided from off chip by providing the instructions in groups of n instructions, the nth instruction in each group being a WAIT instruction that pauses the microcontroller while a next group of instructions is loaded into the group of t-latches.