Patent ID: 8326938

Claim:
An apparatus, comprising: a first memory configured to store a first one or more packet descriptors and a second one or more packet descriptors; a second memory configured to store one or more packets for transmission via a communication link; a third memory configured to store one or more packets for transmission via the communication link; a first direct memory access engine configured to determine when the first one or more packet descriptors have been written, by a host, to the first memory, read the first one or more packet descriptors from the first memory in response to determining that the first one or more packet descriptors have been written to the first memory by the host, determine, using the first one or more packet descriptors, a first one or more respective locations of a first one or more packets in a host memory, the first one or more packets corresponding to a first queue, and initiate a direct memory access transfer of the first one or more packets from the first one or more respective locations of the first one or more packets in the host memory to the second memory; and a second direct memory access engine configured to determine when the second one or more packet descriptors have been written, by the host, to the first memory, read the second one or more packet descriptors from the first memory in response to determining that the second one or more packet descriptors have been written to the first memory by the host, determine, using the second one or more packet descriptors, a second one or more respective locations of a second one or more packets in the host memory, the second one or more packets corresponding to a second queue, and initiate a direct memory access transfer of the second one or more packets from the second one or more respective locations of the second one or more packets in the host memory to the third memory.