Patent ID: 7977797

Claim:
An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit; a contact region coupled to said substrate, said contact region provides an electrical path to and from said substrate; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region; and a multiple etch stop insulation layer coupled to said contact region, wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region, and wherein said multiple etch stop insulation layer includes: a first etch stop layer directly on said substrate in said contact region; a first sub interlevel dielectric layer over said first etch stop layer; a second etch stop layer over said first sub interlevel dielectric layer, wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer; and a second sub interlevel dielectric layer over said second etch stop layer.