Patent ID: 8401103

Claim:
A parallel decoder for decoding an input electrical signal created by encoding a data signal having a bit rate with a spreading code having a chip rate, the decoder comprising: a control signal generator for generating, from the input electrical signal, a first clock signal having a frequency equal to half the chip rate, a second clock signal having a frequency equal to half the chip rate, and a third clock signal having a frequency equal to the bit rate; and a decoding section for generating a decoded signal from the input electrical signal and outputting the decoded signal, the decoding section including: a splitter for splitting the input electrical signal into a first electrical signal and a second electrical signal, the first electrical signal and the second electrical signal having the same waveform and the same phase, a first matched filter operating in synchronization with the first clock signal to receive the first electrical signal and to generate a first correlated signal from the first electrical signal, a second matched filter operating in synchronization with the second clock signal to receive the second electrical signal and to generate a second correlated signal from the second electrical signal, and a decision section operating in synchronization with the third clock signal to generate the decoded signal from the first correlated signal and the second correlated signal.