Patent ID: 7684264

Claim:
A method comprising: powering an integrated circuit including a first random access memory (RAM) array and a second RAM array, the second RAM array including memory cells that are redundant to memory cells of the first RAM array, wherein the first RAM array includes a first plurality of memory cells and the second RAM array includes a second plurality of memory cells, wherein the memory cells of the first plurality are of a first designed cell circuit topology and the memory cells of the second plurality are of a second designed cell circuit topology, wherein the first designed cell circuit topology is different from the second designed cell circuit topology, wherein the first designed cell circuit topology includes the cells of the first plurality being powered by a first power supply voltage and the second designed cell circuit topology includes memory cells of the second plurality being powered by a second power supply voltage, wherein the second power supply voltage is greater than the first rower supply voltage, wherein the second designed cell circuit topology includes a same number of transistors as the first designed cell circuit topology; and selectively accessing the second RAM array when accessing the first RAM array to store data to the second RAM array.