Patent ID: 7499331

Claim:
A semiconductor memory device comprising: a memory cell including a floating body in an electrically floating state and storing therein data according to a number of a plurality of majority carriers accumulated in the floating body; a dummy cell generating a reference signal based on which the data stored in the memory cell is detected; a word line connected to a gate of the memory cell; a dummy word line connected to a gate of the dummy cell; a bit line connected to a source or a drain of the memory cell and a source or a drain of the dummy cell; a diffused layer adjacent to the source or the drain of the dummy cell, the diffused layer being equal in conduction type to the floating body of the dummy cell; a counter counting a number of times of activating the dummy word line; and a charge supplying line driving the bipolar transistor by applying a voltage to the diffused layer and supplying the majority carriers to the floating body of the dummy cell when the number of times of activating the dummy word line reaches a predetermined value, wherein the floating body of the dummy cell, the source or the drain of the dummy cell, and the diffused layer constitute a bipolar transistor.