Patent ID: 8148759

Claim:
A semiconductor memory cell, comprising: an Independently-Double-Gated (IDG) Hysteresis Field Effect Transistor (HyFET) configured as a memory cell to store data and to provide non-destructive readout of the data stored in the IDG HyFET transistor, wherein the IDG HyFET includes a substrate, a substrate dielectric disposed on the substrate, a bottom gate disposed on the substrate dielectric, a source disposed above the substrate dielectric and having a source extension extending from a main body of the source, a drain disposed above the substrate dielectric and having a drain extension extending from a main body of the drain, a channel disposed on the bottom gate and coupled to and disposed between the source and the drain, the channel creating a junction contact with the bottom gate to form a JFET, a hysteresis-producing material disposed above the channel, a top gate disposed above the hysteresis-producing material, wherein the top gate completes a Metal—Hysteresis-producing material—Semiconductor structure to form a Hysteresis FET (HyFET), a first local interconnect coupled to the top gate, a second local interconnect insulated from the first local interconnect and coupled to the bottom gate, a first insulating spacer disposed between the top gate and the source and proximate to the source extension, and a second insulating spacer disposed between the top gate and the drain and proximate to the drain extension, and wherein a first control signal line is coupled to the top gate, and wherein the bottom gate is controlled by a means of threshold control to dynamically adjust a threshold of the channel to provide non-destructive readout of the data, and wherein the means of threshold control adjusts the threshold of the channel to a default value during a write operation, reduces the threshold of the channel during a read operation, and maintains the threshold of the channel at a high value except during a write or a read operation.