Patent ID: 8099451

Claim:
A method to output a result of a logical operation with two operands for an instruction identifying the logical operation in an arithmetic/logic unit of a processor, comprising: receiving, by a generate function circuit and a propagate function circuit of the arithmetic/logic unit, the two operands; computing, by the generate function circuit, a generate function result; computing, by the propagate function circuit, a propagate function result, wherein the generate function result is a logical AND and the propagate function result is a logical OR of the two operands or the generate function result is a logical NAND and the propagate function result is a logical NOR of the two operands; and computing the result of the logical operation to output the result, wherein computing the result comprises: shifting, by a rotator, the generate function result by zero to output the generate function result if the instruction identifies a logical AND or NAND operation; and computing, by the execution macro circuitry, a logical NAND or a logical AND of the generate function result and the propagate function result to produce a logical XOR of the two operands if the instruction identifies a logical XOR or EQV operation.