Patent ID: 8173498

Claim:
A method for manufacturing an array substrate, comprising: providing a substrate; forming a first patterned conductive layer on the substrate to define a gate line, a gate electrode, and a first segment of a data line having a terminal of a first data line contact pad; forming a first insulation layer on the first patterned conductive layer; forming a patterned semiconductor channel layer on the gate electrode; removing a part of the first insulation layer to expose a part of the first data line contact pad; forming a second patterned conductive layer to simultaneously define source/drain electrodes on the patterned semiconductor channel layer and a second segment of the data line having a terminal of a second data line contact pad, wherein the second segment of the data line intersects the gate line, and the first insulation layer is disposed between the second segment of the data line and the gate line in an overlapping area of the second segment of the data line and the gate line; forming a second insulation layer covering the second patterned conductive layer; forming a third patterned conductive layer on the first and second segments of the data line, wherein the first and second insulation layers are disposed between the first segment of the data line and the third patterned conductive layer; forming a third insulation layer covering the third patterned conductive layer, the second segment of the data line, the source/drain electrodes, and the second insulation layer; removing a part of the second and third insulation layers on the drain electrode to form a via hole for exposing a part of the drain electrode; and forming a pixel electrode covering the third insulation layer, wherein the pixel electrode electrically connects to the exposed part of the drain electrode through the via hole, wherein a part of the pixel electrode overlaps the third patterned conductive layer.