Patent ID: 7932764

Claim:
A delay circuit, comprising: an inverting receiver, consisting of one inverter, the inverter having one resistive element, the inverting receiver having an input node for directly receiving an input signal and an output node, the resistive element being coupled to the output node of the inverting receiver and an internal node in the inverting receiver; a capacitive element, having: a first terminal, coupled to the output node of the inverting receiver; and a second terminal coupled to a ground; a first transistor, having: a first terminal, coupled to the output node of the inverting receiver; a control terminal, coupled to the ground; and a second terminal; a second transistor, having: a control terminal, directly receiving the input signal; a first terminal coupled to the ground; and a second terminal, coupled to the second terminal of the first transistor, wherein the second transistor is a NMOS transistor; and an output inverter, having an input node coupled to the second terminal of the first transistor and an output node for outputting an output signal of the delay circuit; wherein the first transistor compensates delay of the inverting receiver as temperature varies; and the second transistor is used for generating a rail to rail signal on the second terminal of the first transistor.