Patent ID: 7743298

Claim:
A method comprising: scanning a first test vector sequentially into a plurality of scan registers serially coupled together, each of the plurality of scan registers including a master latch to store data, a scan latch and a functional latch having inputs coupled together to an output of the master latch, the scan latch to receive and to store the data from the master latch in response to enabling a scan mode, and the functional latch to receive and to store the data from the master latch in response to disabling the scan mode; wherein the scanning of the first test vector sequentially into the plurality of scan registers includes enabling the scan mode to scan the first test vector into the plurality of scan registers; and applying the first test vector via the plurality of scan registers to a combinational logic circuit coupled to the functional latch of one or more of the plurality of scan registers, wherein the applying of the first test vector to the combinational logic circuit includes disabling the scan mode to update an output of the functional latch of each of the plurality of scan registers with the first test vector.