Patent ID: 7161207

Claim:
A computer system comprising: (A) a CPU (central processor unit); (B) a memory arrangement comprising: (i) a side-wall memory array including a plurality of side-wall memory transistors and sets of bitlines, each side-wall memory transistor having a side-wall portion; (ii) a charge pump for providing a voltage to accumulate negative charges in the side-wall portion of each side-wall memory transistor during a programming operation; (iii) a plurality of switching circuits each coupled to the charge pump for receiving the voltage provided by the charge pump and for transferring the voltage to selected sets of the sets of bitlines of the side-wall memory array; and (iv) logic circuitry for enabling the plurality of switching circuits in a selected sequential order; and (C) a system bus for transferring data and addresses between the CPU and the memory arrangement, wherein each of the side-wall memory transistors comprises: only a single gate electrode formed on a semiconductor layer with a gate insulating film formed on the semiconductor layer; a channel region formed below the gate electrode; a pair of diffusion regions formed on the both sides of the channel region and having a conductive type opposite to that of the channel region; and a pair of memory functional elements formed on both sides of the gate electrode and having a function of retaining charges wherein a writing or erasing operation to a selected one of either of the memory functional elements formed on both sides of the gate electrode can be executed independently from the other unselected memory functional element by controlling each voltage applied to the diffusion regions and the gate electrode, and wherein an overlap amount between the memory functional element and the diffusion region is 10 nm or more.