Patent ID: 8709956

Claim:
A method for fabricating a memory cell comprising: depositing a stack of layers for a memory device including a top electrode, a memory element and a bottom electrode; patterning the stack of layers for a memory device to expose sidewalls of the layers; depositing a first layer of dielectric material over the memory device and onto the sidewalls; forming a sidewall protection sleeve and exposing an upper surface of the top electrode by vertically etching the first layer of dielectric material to remove substantially all of the first layer of dielectric material except for the sidewall protection sleeve of dielectric material that conforms to a shape of the sidewalls of the memory device and covers the sidewalls of the memory element and the bottom electrode; depositing a bottom etch-stop layer of a dielectric material over the memory device and the sidewall protection sleeve of dielectric material; depositing a top etch-stop layer of a dielectric material over the bottom etch-stop layer; depositing an inter-layer dielectric layer over the top etch-stop layer; forming a via for a metal bit line interconnect by etching away a selected portion of the inter-layer dielectric layer, the top etch-stop layer and the bottom etch-stop layer to expose an upper surface of the top electrode and at least a portion of the sleeve of dielectric material; and forming a metal bit line interconnect in contact with the top electrode and the sleeve of dielectric material.