Patent ID: 7634622

Claim:
A bank-access scheduler comprising: a plurality of requester inputs for carrying requests for memory access to a shared memory from a plurality of requestors; a plurality of bank interfaces to the shared memory, each bank interface for accessing a bank of the shared memory, wherein banks are interleaved with a bank granularity; a plurality of request selectors coupled to the plurality of bank interfaces, each request selector for selecting a selected requester from the plurality of requester inputs to the request selector; and staggering means for staggering connection of the plurality of request inputs to the plurality of bank interfaces wherein each request input is connected to a different bank interface in the plurality of bank interfaces for each time-slot in a sequence of time-slots; wherein the plurality of requesters comprises: a packet interface for requesting writing of incoming packets from an external network to the shared memory; a plurality of multi-processor tribes, each multi-processor tribe comprising a plurality of processors, each processor for operating on a packet written to the shared memory by the packet interface; wherein an incoming packet from the packet interface is written to a next-available bank in the shared memory; wherein a first bank in the shared memory is a page-start bank for storing a start of an aligned page; wherein an offset bank in the shared memory does not contain the start of the aligned page; wherein the aligned page starts at an address having all zero address bits for address bits having a significance less than a size of the aligned page; wherein the next-available bank is an offset bank when the incoming packet arrives when the first bank is not immediately available to be written by the packet interface; whereby requests are connected to banks of the shared memory in a staggered fashion and whereby incoming packets are able to be written to the offset bank as the next-available bank.