Patent ID: 7024644

Claim:
A method for estimating resistances of conductors to reside on layers of an integrated circuit (IC) to be fabricated in accordance with layout data indicating nominal dimensions of each conductor and indicating that conductors on each layer are to be centered at indicated positions along parallel grid lines G=1 through GMAX(L), wherein GMAX(L) for each layer L is an integer greater than 1, and wherein when the IC is fabricated, actual dimensions of each conductor residing on any grid line on any layer are functions of its nominal dimension and of the nominal dimensions and relative position of any adjacent conductor residing on any adjacent grid line of the same layer, the method comprising the steps of: a. processing the layout data to generate a separate database D(L) for each layer L of the IC, wherein each database D(L) includes a separate table T(L,G) corresponding to each grid line G of layer L, wherein each table T(L,G) of each database D(L) includes a separate table entry corresponding to each conductor to reside along the G th grid line the L th layer, wherein each table entry contains information indicating its corresponding conductor's nominal dimensions and its position along the grid line on which it is to reside; and b. separately processing the database D(L) for each L th layer to estimate resistance of each conductor that is to reside along any grid line on the L th layer as a function of the nominal dimensions and relative positions of that conductor and of any adjacent conductor that is to reside along an adjacent grid line of the same layer, wherein step b comprises the substeps of, for each value of L: b1. estimating actual dimensions of conductor sections to reside on a side of grid line G=1 most remote from grid line G=2 of layer L as functions of nominal conductor dimensions and of positions indicated by entries of table T(L, 1 ); b2. for each value of G from G to GMAX(L)−1, estimating actual dimensions of conductor sections to reside between grid lines G and G+1 of layer L as functions of nominal conductor dimensions and positions indicated by entries of tables T(L,G) and T(L,G+1), and estimating resistance of each conductor along grid line G as a function of estimated actual dimensions of its sections residing on both sides of grid line G; and b3. estimating actual dimensions and positions of sections of conductors residing on a side of grid line GMAX(L) most remote from grid line GMAX(L)−1 as functions of nominal conductor dimensions and positions indicated by entries of table T(L,GMAX(L)), and estimating resistance of each conductor to reside along grid line GMAX(L) as a function of estimated actual dimensions of its sections.