Patent ID: 8026553

Claim:
A semiconductor memory device comprising: a supporting substrate; a semiconductor layer provided above the supporting substrate, and extending in a first direction; a source layer provided in the semiconductor layer; a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer in the semiconductor layer, the body being in an electrically floating state, electric charges being accumulated in or emitted from the body to store data; a bit line connected to the drain layer, and extending in the first direction; a first gate dielectric film provided on a first side surface of the body; a first gate electrode provided on the first side surface of the body via the first gate dielectric film; a first gate line extending in the first direction, connected to a bottom of the first gate electrode, and formed integrally with the first gate electrode using same material; a second gate dielectric film provided on a second side surface of the body, the second side surface being opposite to the first side surface; a second gate electrode provided on the second side surface of the body via the second gate dielectric film, the second gate electrode extending upward above a top surface of the body and isolated from the first gate electrode; and a second gate line extending above the body in a second direction crossing the first direction, connected to an upper portion of the second gate electrode, and formed integrally with the second gate electrode using same material.