Patent ID: 8848110

Claim:
A receiver circuit comprising: an analog front-end including an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal, the analog front-end updating gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal, wherein each of the plurality of adjustable gain stages comprises: a filter including a filter input and a filter output; and an adjustable gain amplifier including an amplifier input coupled to the filter output, an amplifier control input, and an amplifier output; a control bus coupled to the digital processing unit; and synchronization logic including a first synchronization input coupled to the control bus to receive the gain adjustment signal, a second input coupled to the digital processing unit to receive the timing signal, and a control output coupled to the amplifier to apply the gain adjustment signal in response to the timing signal; and a digital processing unit coupled to the analog front-end and configured to produce at least one output signal derived from the digital IF signal, the digital processing unit including a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating of gains of each of the plurality of adjustable gain stages.