Patent ID: 8441378

Claim:
A pipeline analog-to-digital converter (ADC), comprising: a plurality of pipeline element circuits, each pipeline element circuit corresponding to a given bit of the pipeline ADC and comprising an amplifier circuit switchably configured to operate in first A and second B capacitor configurations corresponding, respectively, to a first A capacitor and a second B capacitor, a first pipeline element circuit comprising a calibration sample-and-hold circuit operably connected thereto, the first pipeline element circuit being configured to digitize analog A and B capacitor mismatch error calibration voltages generated by the first pipeline element circuit and by the remainder of the pipeline element circuits when the pipeline ADC is operating in a capacitor mismatch calibration phase, the first pipeline element circuit further being configured to provide as outputs therefrom digital representations corresponding to the A and B capacitor mismatch error calibration voltages for each of the plurality of pipeline element circuits during the capacitor mismatch calibration phase; an output shift register and summing circuit configured to receive and process the digital representations to provide capacitor mismatch error correction codes corresponding to each bit and pipeline element circuit, and a memory one of forming a portion of and not forming a portion of the pipeline ADC configured to receive and store therein the capacitor mismatch error correction codes corresponding to each bit and pipeline element circuit of the pipeline ADC; wherein the capacitor mismatch error correction codes are applied to each bit weight of the pipeline ADC after conversion of analog signals input to the pipeline ADC has been completed.