Patent ID: 8760945

Claim:
A method of communication with a memory device, comprising: sending a calibration command over a command/address bus; sending a sequence of n first test signals over the command/address bus, wherein n is an integer equal to 2 or more; sending a clock signal over a first clock line with each of the n first test signals, each of the n first test signals being sent at a respective first to nth phase with respect to the clock signal, each of the first to nth phases being different from one another; receiving a sequence of n second test signals over a data bus respectively derived from the sequence of n first test signals sent over the command/address bus; comparing the n first test signals to the n second test signals; and determining a preferred phase of third signals to be sent over the command/address bus with respect to the clock signal in response to the comparing the n first test signals to the received n second test signals.