Patent ID: 7195961

Claim:
A method for manufacturing an integrated circuit on and in an SOI semiconductor wafer having a front and a back, wherein first structures having active devices in an upper semiconductor layer ( 12 ) and second structures ( 13 a , 13 a ′, 13 c ) of devices within the substrate ( 13 ) are connected by electric connection ( 20 , 22 ) formed through an insulating layer ( 11 ), the method comprising the following steps: performing an ion implantation ( 30 , 31 ) with highly energetic ions in certain areas ( 13 ′, 13 ″) from the front through the upper semiconductor layer ( 12 ), through the insulating layer ( 11 ) and into the substrate ( 13 ); performing a temperature treatment for activating the ions implanted into the substrate ( 13 ) in accordance with an implanted ion species, wherein the implanted ions are activated in a plurality of steps with different temperatures; forming the first structures ( 30 , 40 , 50 , 60 ) at least partially in the upper semiconductor layer as a single crystalline layer ( 12 ); forming at least one of a plurality of vias in the insulating layer ( 11 ); filling ( 20 , 22 ) the at least one via ( 19 , 21 ) in the insulating layer with a metallic material to provide a metallic filling; forming-in the area of the first structures ( 40 , 50 , 60 ) insulated with respect to each other-metal conductors to electrically connect the first structures of the front with the second structure within the substrate ( 13 ) via the at least on metal filling in the at least one via.