Patent ID: 8686495

Claim:
A power semiconductor device, comprising: a first semiconductor layer; a second semiconductor layer of a first conductivity type formed on the first semiconductor layer; a plurality of third semiconductor layers of a second conductivity type formed in the second semiconductor layer and arranged at a predetermined interval along a direction perpendicular to the stacking direction of the first and the second semiconductor layers; a fourth semiconductor layer of the second conductivity type formed on the second semiconductor layer; fifth semiconductor layers of the first conductivity type formed on the fourth semiconductor layer; a plurality of gate electrodes, at least a part of which are formed above the second semiconductor layer and a part of each gate electrode is arranged between the two of the third semiconductor layers adjacent to each other; a plurality of first electrodes, each of which is formed below one of the gate electrodes; a second electrode electrically connected to the first semiconductor layer; and a third electrode electrically connected to the fifth semiconductor layer; wherein at least one of the first electrodes is electrically connected to one of the gate electrodes, and at least another one of the first electrodes is electrically connected to the third electrode.