Patent ID: 7642147

Claim:
A method, comprising: (a) forming a first gate stack on a first region of a substrate and a second gate stack on second region of said substrate; after (a), (b) forming dielectric first spacers on sidewalls of said first gate stack and forming dielectric second spacers on sidewalls of said second gate stack; after (b), (c) forming a continuous conformal dielectric stress layer on said first and second spacers and on surfaces of said first and second gate stacks and over said substrate where said first and second gate stacks and said substrate are not covered by said first or second spacers; after (c), (d) forming a continuous conformal dielectric capping layer on said stress layer; after (d), (e) removing said capping layer from said stress layer in said second region; after (e), (f) forming a dielectric sacrificial layer on said capping layer and on said stress layer where said stress layer is not covered by said capping layer; and after (f), (g) removing said sacrificial layer, said stress layer from said second region and said second spacers in a etch process by etching said sacrificial layer until said stress layer is exposed in said second region, thereafter simultaneously etching said sacrificial layer and said stress layer in said second region until said second spacers are exposed and thereafter simultaneously etching said sacrificial layer, said stress layer in said second region and said second spacers until said sacrificial layer is removed, said stress layer is removed from said second region and said second spacers are removed.