Patent ID: 7460403

Claim:
A flash memory device comprising: a memory cell array including at least one NAND string, each of the at least one NAND string including a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor, the string selection transistor being configured to control an electrical connection between a first of the at least one NAND string and a corresponding first bit line based on a string selection voltage and whether a memory cell selected during a read operation is programmed or non-programmed; a row selection circuit coupled to the memory cell array through a string selection line, a ground selection line and a plurality of word lines, the row selection circuit being configured to select a first of the plurality of word lines based on a row address signal and a read voltage, the first word line being coupled to a first memory cell; and a voltage generation circuit configured to generate the string selection voltage and the read voltage.