Patent ID: 7727877

Claim:
A method of manufacturing a wafer level package, the method comprising: coating an insulation layer over one side of a semiconductor chip such that an electrode pad is open, the semiconductor chip having the electrode pad formed on one side; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern by selective electroplating with the seed layer as an electrode, the rewiring pattern being electrically connected with the electrode pad; forming a first metal pillar and a second metal pillar on the first metal pillar by selective electroplating with the seed layer as an electrode, the first metal pillar and the second metal pillar being electrically connected with the rewiring pattern; removing portions of the seed layer open to the exterior; then reflowing the second metal pillar; molding the semiconductor chip with epoxy; and opening a portion of the reflowed second metal pillar by performing plasma etching on the molded epoxy.