Patent ID: 7627057

Claim:
A receiver for receiving a communications signal to produce two output signals in quadrature relation to one another, comprising: a low-noise amplifier; a first switching transistor and a second switching transistor being connected to the low-noise amplifier; a local oscillator; an adjustable phase shift network having a first delay line and a second delay line, each delay line having its input connected to the local oscillator, the first delay line and the second delay line respectively deriving a first reference signal and a second reference signal having a 90° phase difference therebetween; means for, using the first and second reference signals, performing frequency downconversion of the communications signal outputted from the low-noise amplifier and outputting the two output signals from the first and second switching transistors; and a phase error detection network for forming an error signal derived of the product of the two output signals, wherein said adjustable phase shift network adjusts a relative delay between the first reference signal and the second reference signal using the error signal, wherein the means for performing frequency downconversion comprises a first drive transistor and a second drive transistor, wherein an output of the first delay line is coupled to a gate of the first drive transistor via a first inductor, and a drain of the first drive transistor is coupled to a gate of the first switching transistor, wherein an output of the second delay line is coupled to a gate of the second drive transistor via a second inductor, and a drain of the second drive transistor is coupled to a gate of the second switching transistor, wherein, each of the drains of the first and second drive transistors is coupled to a first rail voltage which is greater than the threshold voltage of the switching transistor, and each of sources of the drive transistors is coupled to a second rail voltage which is less than the threshold voltage, wherein, each of the outputs from the first and second delay lines, supplies a sinusoidal signal to the gate of the respective drive transistor causing, an input capacitance of the respective drive transistor to resonate with an inductance, and causing each drive transistor to alternate between two states including one state in which the drive transistor causes the first rail voltage to be applied to its respective switching transistor through a resistor to turn the switching transistor on, and another state in which each drive transistor causes the second rail voltage to be applied to its respective switching transistor to turn the switching transistor off.