Patent ID: 7899858

Claim:
A filter circuit which inputs first data therein, filters the first data and outputs the so-processed first data as second data, comprising: a first delayer which operates at a timing of a predetermined clock and delays the first data inputted to the filter circuit by one clock; a first subtracter to which the second data is fed back and which calculates a first difference value as an absolute value of a difference between the second data and the first data inputted to the filter circuit; a second subtracter to which the second data is fed back and which calculates a second difference value as an absolute value of a difference between the second data and the first data delayed by the first delayer; a comparator which compares the first difference value and the second difference value; a selector which selects and outputs the first data inputted to the filter circuit, based on the result of comparison by the comparator when the first difference value is smaller than the second difference value, and selects and outputs the first data delayed by the first delayer when the first difference value is greater than or equal to the second difference value; and a second delayer which operates at the timing of the predetermined clock and outputs the second data as data obtained by delaying the output data of the selector by one clock.