Patent ID: 6903990

Claim:
A semiconductor memory device, comprising: a memory cell array of dynamic memory cells; an external access timing signal generation module that outputs an external access timing signal used as a reference for an access operation from an external device, the external access timing signal becomes active according to a change of an external address received from the external device; an address latch signal generation module that outputs an address latch signal indicating a latch timing of the external address, the address latch signal becomes active according to a timing of an inactivation of the external access timing signal; a refresh control module that: generates a refresh timing signal used as a reference for an execution timing of a refresh operation to the memory cell array; generates a refresh arbiter signal which: becomes active according to a timing of an activation of the external access timing signal; and does not become active if the external access timing signal becomes active because of a change of an external address during a period in which the address latch signal is active; and generates a refresh execution timing signal which becomes active according to an activation of the refresh arbiter signal after an activation of the refresh timing signal; and an external access control module that outputs an external access execution timing signal which indicates an execution timing of the access operation to the memory cell array, wherein the external access execution timing signal: becomes active according to at least a timing of activation of the address latch signal; and then becomes inactive according to a timing of activation of the external access timing signal and wherein: an active period of the address latch signal is set to be substantially identical to an activation period which is required for one word line to be activated for access to a memory cell corresponding to the external address received from the external device, the one word line being selected from a plurality of word lines included in the memory cell array, and an active period of the external access timing signal is set to be substantially identical to a pre-charge period which is required before starting of activation of any word line selected from the plurality of word lines after starting of inactivation of one word line selected from the plurality of word lines.