Patent ID: 7517707

Claim:
A manufacturing method of a semiconductor integrated circuit device, comprising: (a) preparing a semiconductor wafer which has been divided in two or more chip regions each having a semiconductor integrated circuit formed thereover, and has, formed over a main surface of the wafer, two or more electrodes to be electrically connected to the semiconductor integrated circuit; (b) preparing a probe card which has two or more contact terminals which contact the two or more electrodes; and (c) conducting electrical testing of the semiconductor integrated circuit, tips of the two or more contact terminals being contacted to the two or more electrodes, wherein the step (b) comprises the steps of: (b1) preparing, as opposed to a wiring substrate in which a first wiring is formed, a first sheet having the two or more contact terminals to contact the two or more electrodes; second wirings electrically connected to the two or more contact terminals and the first wiring; and a metal wiring for a shield formed along a signal wire which is easy to be influenced by a noise among the second wirings; and (b2) after the step (b1), attaching the first sheet over the wiring substrate in a state that a domain in which the two or more contact terminals are formed of the first sheet, are pressed from a back of the first sheet.