Patent ID: 6956425

Claim:
An FET switch having a clamp circuit comprising: an FET switching transistor; a surge detector coupled between a conductive path of the FET switching transistor and a gate thereof, the surge detector having means for enabling the measurement of BVdss of the FET switching transistor; a first biasing circuit coupled to the gate of the FET switching transistor providing a first biasing current to the gate; a second biasing current coupled to the gate of the FET switching transistor providing a second biasing current to the gate, the second biasing current being less than the first biasing current; and a biasing switching circuit coupled to the first biasing circuit to disconnect the flow of the first biasing current when a voltage surge is detected by the surge detector, whereby the surge detector can turn on the FET switching transistor to clamp the surge voltage below the BVdss thereof.