Patent ID: 8130586

Claim:
A dynamic random access memory chip formed on a silicon substrate which performs a read operation or a write operation when a plurality of control signals are supplied from an external of the dynamic random access memory chip, comprising: a memory core with a plurality of memory cells; an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line; a command decoder that receives the plurality of control signals and generates an internal command signal; and a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation on all of the plurality of memory cells is not performed, wherein the internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the dynamic random access memory chip, and wherein the internal voltage generator includes a reference voltage generator, a detector and a booster circuit.