Patent ID: 7511582

Claim:
A high speed bit stream data conversion circuit comprising: a first data conversion circuit that receives at least one first bit stream at a first bit rate and a corresponding first bit stream data clock and that produces at least one second bit streams at a second bit rate, wherein the number and bit rate of the at least one first bit stream and the at least one second bit stream differ; and a clock circuit that produces a Reference Clock Signal based on a plurality of inputs that include the first bit stream data clock, wherein the Reference Clock Signal is used to latch the at least one first bit stream, wherein the clock circuit comprises: a phase locked loop (PLL) having a phase detector that receives the first bit stream data clock and a loop output, a charge pump, a loop filter, a Voltage Controlled Oscillator (VCO), and a divider, wherein the VCO comprises a pair of cross-coupled transistors, an inductor coupled to the cross-coupled transistors, and a filtering circuit having a capacitor and a variable resistor.