Patent ID: 7386696

Claim:
A semiconductor memory module arranged on one module board, the memory module comprising: a plurality of memory chips arranged in one or more memory chip rows and an even number of buffer chips for receiving and driving to the memory chips clock signals, command and address signals and for receiving and driving data signals from and to the memory chips via a module-internal bus including signal line types of clock, address, command and data signal lines, said buffer chips forming an interface between the module-internal bus and a module-external primary memory bus; wherein all memory chips are arranged on the module board in at least one memory chip group; wherein each memory chip group comprises the same number of memory chips in at least one of said memory chip rows; wherein a first and second of said buffer chips are respectively arranged on the end sides of each memory chip row; wherein the memory chips of the at least one memory chip row are connected to both said first and second buffer chips at least by one of said signal line types and to exactly one of said buffer chips by the remaining signal line types; control means for controlling data write and read operation to and from the memory chips in order to drive the clock signals and command and address signals in the respectively same direction as the flow direction of write data signals and read data signals via the module-internal bus; and wherein the arrangement of the buffer chips and the memory chips within each memory chip row and the control of the control means effect that the sum of electrical signal propagation times for the clock, command and address signals via their lines from one of said first and second buffer chips to a respective one of the memory chips of said at least one memory chip row plus the electrical signal propagation times for the data signals from the same one memory chip to the other of said first and second buffer chips during a read operation is the same for all memory chips of said at least one memory chip row.