Patent ID: 7952404

Claim:
A method for determining a number of steps of a fine delay line (FDL) which are substantially equivalent to a step of a coarse delay line (CDL), the method comprising steps of: providing a clock signal; delaying the clock signal by a first delay substantially equivalent to a predetermined delay plus an adjustable number of steps of the FDL to provide a first delayed clock signal; delaying the clock signal by a second delay substantially equivalent to the predetermined delay plus a step of the CDL to provide a second delayed clock signal; and adjusting the number of adjustable steps of the FDL so that the first delay is substantially equal to the second delay to provide the number of steps of the FDL that are substantially equivalent to the step of the CDL, wherein the step of delaying the clock signal by the first delay comprises steps of: delaying the clock signal by a delay substantially equal to an intrinsic delay of the CDL; and further delaying the clock signal by a delay substantially equal to an intrinsic delay of the FDL plus the adjustable number of steps of the FDL.