Patent ID: 8039893

Claim:
A semiconductor device comprising a CMOS inverter coupling circuit that couples n (n is two or above) CMOS inverters with each other, each of the n CMOS inverters having: a first MOS transistor for a first conductivity type channel, which has a structure where a first drain, a first gate, and a first source are arranged in a vertical direction with respect to a substrate and the first gate surrounds an island-shaped semiconductor layer; a second MOS transistor for a second conductivity type channel different from the first conductivity type channel, which has a structure where a second drain, a second gate, and a second source are arranged in a vertical direction with respect to the substrate and the second gate surrounds an island-shaped semiconductor layer; an input terminal of the CMOS inverter arranged so as to connect the first gate of the first MOS transistor with the second gate of the second MOS transistor; an output terminal of the CMOS inverter arranged so as to connect a drain diffusion layer of the first MOS transistor with a drain diffusion layer of the second MOS transistor in an island-shaped semiconductor lower layer; a power supply wiring line for the first MOS transistor, which is arranged on a source diffusion layer of the first MOS transistor; a power supply wiring line for the second MOS transistor, which is arranged on a source diffusion layer of the second MOS transistor, wherein the semiconductor device further has a coupling portion that is used to connect the output terminal of an n−1th CMOS inverter with the input terminal of an nth CMOS inverter when arranging each of the n CMOS inverters with respect to the substrate, and tops of both of the coupling portion and the first gate are located to vertically overlap and align with at least a part of the power supply wiring line, and a dielectric film is formed on entire top surfaces of the first gate and the coupling portion.