Patent ID: 7200710

Claim:
An integrated circuit buffer device comprising: a receiver circuit to receive control information and address information; a first interface portion to provide at least a first control signal that specifies a write operation to a first memory device, the at least a first control signal corresponding to the control information; a second interface portion to provide a first address to the first memory device, the first address corresponding to the address information, the first address to specify a memory location for the write operation to the first memory device; a third interface portion to provide a first signal to the first memory device, the first signal to synchronize communication of the at least a first control signal from the integrated circuit buffer device to the first memory device; a fourth interface portion to provide at least a second control signal that specifies a write operation to a second memory device, the at least a second control signal corresponding to the control information; a fifth interface portion to provide a second address to the second memory device, the second address corresponding to the address information, the second address to specify a memory location for the write operation to the second memory device; and a sixth interface portion to provide a second signal to the second memory device, the second signal to synchronize communication of the at least a second control signal from the integrated circuit buffer device to the second memory device.