Patent ID: 8391105

Claim:
A circuit comprising: an oscillator circuit configured to provide an internal oscillator signal, the internal oscillator signal comprising internal reference pulse edges substantially at an internal reference frequency; a frequency counter configured to receive an external reference signal that comprises periodic pulse edges and the internal oscillator signal, the frequency counter further configured to output a count value that represents a number of internal reference pulse edges counted between two external reference signal periodic pulse edges; a correction signal generator configured to receive the count value, the correction signal generator outputs an oscillator fast signal when the count value is equal to a predetermined first number and outputs an oscillator slow signal when the count value is equal to a predetermined second number, the predetermined first number being greater than the predetermined second number; a variable divide-by circuit configured to receive the oscillator fast signal, the oscillator slow signal and the internal oscillator signal, the variable divide-by circuit is configured to provide a conditioned output having an output frequency equal to the internal reference frequency divided by a first number when in receipt of the oscillator fast signal, equal to the internal reference frequency divided by a second number when in receipt of the oscillator slow signal, or equal to the internal oscillator reference frequency divided by a third number.