Patent ID: 7167532

Claim:
A method of determining oversampling timing from a reference clock source for an input symbol stream, said method comprising the steps of: enabling reference clock cycles periodically an integer number of times during each symbol period, each reference clock cycle enabled resulting in a sampling instance; enabling reference clock cycles zero or more additional times each symbol period to produce a minimum number of sampling instances per symbol period; delaying sampling instances zero or more compensation reference clock cycles during each averaging period consisting of one or more symbol periods; and wherein the timing of said sampling instances is controlled in accordance with the following A · P = ( ( 1 f REF · chip_step ) · N + SBR ) · A + K · 1 f REF wherein A is the averaging period representing the minimum number that can be represented by an integer number of periods of said reference clock, fREF is the reference clock frequency, P is the symbol clock period, N is the number of chip steps in a symbol period, SBR is the symbol boundary remainder, and K is the number of compensation reference clock cycles to be added over the averaging period.