Patent ID: 7081388

Claim:
A method for fabricating a power semiconductor device, comprising the steps of: forming a first mask layer over a surface of a semiconductor body of a first conductivity; patterning said first mask layer with a plurality of first openings, wherein each of said plurality of first openings extends towards the surface of said semiconductor body; defining trenches in said semiconductor body by etching said semiconductor body through said first openings; forming a gate electrode in each of said trenches; forming an insulation plug atop each of said gate electrodes, each plug extending above the surface of said semiconductor body and into a respective first opening in said mask layer; forming spacers along sidewalls of each of said insulation plugs, wherein said spacers define second openings to the surface of said semiconductor body; and using said spacers to form regions of a second conductivity along the surface of said semiconductor body and aligned to adjacent trenches.