Patent ID: 8813000

Claim:
A computer system comprising a processor for executing program instructions coupled to a memory for storing the program instructions, wherein the program instructions are program instructions for execution by a processor for designing layers of a substrate for mounting and interconnecting a semiconductor die, and wherein the program instructions comprise: program instructions for identifying locations of signal bearing vias from among a pattern of large-diameter conductive vias extending from a top side to a bottom side of a core comprising a dielectric layer; program instructions for identifying signal bearing conductive path profiles for critical signals routed above or below ends of the signal-bearing vias; and program instructions for generating a first mask design for a transmission line reference plane metal layer including voids around the profile of the signal-bearing vias so that capacitive coupling between the ends of the signal-bearing vias and the transmission line reference plane metal layer is substantially reduced, and wherein for signal bearing conductive path profiles identified by the second identifying, including a conductive stripe through the corresponding void.