Patent ID: 7376016

Claim:
In a non-volatile semiconductor memory device having a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing information by variation in threshold voltage, a plurality of word lines associated with said plurality of rows, respectively, a plurality of bit lines associated with said plurality of columns, respectively, and a plurality of sense latches associated with said plurality of bit lines, respectively, a method of writing information to each of said plurality of memory cells, comprising the steps of: (1) causing each sense latch corresponding to a memory cell of a plurality of memory cells associated with one selected word line that is subjected to a write to latch a first signal, and causing each sense latch associated with a memory cell that is not subjected to said write to latch a second signal; (2) performing said write to and verifying each of said plurality of memory cells associated with said selected word line that is associated with said sense latch latching said first signal, and causing each sense latch associated with said memory cell said write to which is completed to latch said second signal; and (3) re-verifying said memory cell subjected to said write, and causing each sense latch associated with said memory cell such detected that said write therein is insufficiently done to latch said first signal, wherein in re-verifying said memory cell subjected to said write, each bit line associated with said memory cell that is not subjected to said write is previously discharged.