Patent ID: 8102289

Claim:
A semiconductor integrated circuit device in which an A/D converter comprising M unitary A/D conversion units different in phase and equal in sampling rate, where M is an integer equal to or larger than 2, the A/D conversion units being connected in parallel to each other, the A/D converter having a sampling rate M times as high as that of the unitary A/D conversion unit, is formed on a single semiconductor substrate together with a clock source, wherein in the A/D converter, a reference A/D conversion unit having a lower sampling rate and a higher resolution than the unitary A/D conversion units is connected in parallel to the M unitary A/D conversion units, when the sampling rate of the A/D converter is N times as high as the sampling rate of the reference A/D conversion unit, where N is an integer equal to or larger than 2, M and N are relatively prime to each other, and the A/D converter has a function of performing calibration for each of the M unitary A/D conversion units based on an output of the reference A/D conversion unit, each of the unitary A/D conversion units and the reference A/D conversion unit are arranged so that a space where none of each of the unitary A/D conversion units and the reference A/D conversion unit are arranged is minimized, and there is a combination of the unitary A/D conversion units and the reference A/D conversion unit whose distances from the clock source are different from each other.