Patent ID: 8633603

Claim:
A semiconductor device comprising: a semiconductor substrate including an alignment mark formation region and an integrated circuit formation region; a plurality of element isolations formed in the semiconductor substrate; a MISFET formed in the integrated circuit formation region and having a gate electrode; a plurality of second patterns formed in the alignment mark formation region; a first interlayer insulating film formed over the semiconductor substrate so as to cover the MISFET and the second patterns; a first wiring formed over the first insulating film of the integrated circuit formation region and electrically connected to the MISFET; a plurality of first patterns formed over the first insulating film of the alignment mark formation region; a second interlayer insulating film formed over the first interlayer insulating film so as to cover the first wiring and the first patterns; an uppermost wiring formed over the second insulating film of the integrated circuit formation region and electrically connected to the first wiring; and an alignment mark formed over the second insulating film of the alignment mark formation region, wherein the alignment mark is formed at the same layer as the uppermost wiring, wherein the second patterns are formed at the same layer as the gate electrode, wherein the first patterns are formed at the same layer as the first wiring, wherein the alignment mark formation is a region on which the MISFET is not formed, and wherein the first and second patterns are not electrically connected to the MISFET.