Patent ID: 6867139

Claim:
A method of manufacturing a semiconductor device comprising: forming a lower layer wiring; forming an inter-layer insulating film to cover therewith said lower layer wiring; a via-hole forming step for forming a via-hole in said inter-layer insulating film to expose said lower layer wiring at a bottom of said via-hole; a barrier film forming step for forming a barrier film throughout a surface including said via-hole; a conductive film forming step for forming a conductive film on said barrier film; a first polishing step for polishing and removing said conductive film on said barrier film until said barrier film is exposed by a chemical mechanical polishing method using a first polishing liquid to achieve said conductive film having a higher polishing rate than said barrier film; a second polishing step for removing said barrier film on said inter-layer insulating film by a chemical mechanical polishing method using a second polishing liquid to achieve said conductive film having a lower polishing rate than said barrier film, to leave said conductive film as non-removed only in said via-hole via said barrier film, thus forming a via-plug; and forming an upper layer wiring on said inter-layer insulating film after performing said second polishing step, thus single-damascene-interconnecting said lower layer wiring and said upper layer wiring through said via-plug.