Patent ID: 7855912

Claim:
A control apparatus for operation of a dual-sided charge-trapping nonvolatile memory cell for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of said dual-sided charge-trapping nonvolatile memory cell, said control apparatus comprising: a programming circuit comprising: a word line program voltage source that provides a negative medium large program voltage for generating a voltage field between a control gate of said dual-sided charge-trapping nonvolatile memory cell and a channel region of said dual-sided charge-trapping nonvolatile memory cell to extracted hot carriers from said channel region to be injected into a first and second charge trapping region of said dual-sided charge-trapping nonvolatile memory cell; a first bit line program voltage source that provides one of a plurality of threshold adjustment voltages representing a portion of said multiple digital data bits to a first drain/source of said dual-sided charge-trapping nonvolatile memory cell to set a first level of said hot carrier charge representing said portion of said multiple digital data bits to said first charge trapping region; and a second bit line program voltage source that provides a second of said plurality of threshold adjustment voltages representing another portion of said multiple digital data bits to a second drain/source of said dual-sided charge-trapping nonvolatile memory cell to set a second level of said hot carrier charge representing said portion of said multiple digital data bits to said second charge trapping region; wherein the first bit line program voltage source provides said one of said plurality of threshold adjustment voltages to said first drain/source of said dual-sided charge-trapping nonvolatile memory cell and said second bit line program voltage source to a ground reference voltage level to program said first drain/source to inject charge to said first charge trapping region; and wherein prior to injecting charge to said first charge trapping region, the second bit line program voltage source provides said second of said plurality of threshold adjustment voltages to said second drain/source of said dual-sided charge-trapping nonvolatile memory cell and said first bit line program voltage source to a ground reference voltage level to program said first drain/source to inject charge to said second charge trapping region.