Patent ID: 7111224

Claim:
A method for continuously correcting errors in memory cells of a FPGA, said memory cells being arranged in rows and columns, said method comprising the steps of: storing predetermined sets of error correction bits in a plurality of memory locations, each of said predetermined sets being associated with one of said columns of memory cells; retrieving data stored in a column of said memory cells on said FPGA; delivering said data to an error correction code circuit on said FPGA; calculating by said error correction code circuit a set of error correction bits associated with said data; comparing said set of error correction bits associated with said data with a predetermined set of error correction bits stored in said plurality of memory locations corresponding to said column in said retrieving step; if said set of error correction bits associated with said data is different from said corresponding predetermined set of error correction bits, correcting said data using said corresponding predetermined set of error correction bits; incrementing to a next column of memory cells; and continuously repeating said retrieving, delivering, calculating, comparing, correcting and incrementing steps so that errors in each of said columns are repeatedly corrected.