Patent ID: 6906944

Claim:
A ferroelectric memory comprising: a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks; a first power switch of normally closed type connected to an external power terminal; a power line, one end thereof being connected to said first power switch and the other end thereof being grounded via a first power capacitor; a boost power circuit connected to said power line and provided in each said block of said memory cell array to generate a boost voltage required for operation of the memory; a second power switch of normally open type connected in parallel to said boost power circuit and provided in each said block of said memory cell array; a voltage detector circuit for detecting a drop of voltage level of said power line; and a switch control circuit for turning on said second power switches in said blocks of said memory cell array excluding the second power switch in a currently selected block in response to said voltage detector circuit.