Patent ID: 8653653

Claim:
A flash memory package, comprising: a plurality of flash memory semiconductor die; a plurality of stacked tape substrate layers, each stacked tape substrate layer including a flash memory semiconductor die of the plurality of semiconductor die, the plurality of stacked tape substrate layers including patterns of electrical traces, an electrical trace of a pattern of electrical traces in a tape substrate layer aligning with a corresponding trace in each other tape substrate layer, the corresponding electrical traces in each stacked tape substrate layer being electrical coupled; a group of n traces of the pattern of electrical traces in each tape substrate layer, where n is greater than or equal to the number of flash memory semiconductor die in the plurality of flash memory semiconductor die, each group of n traces in each tape substrate layer having a layout defined by one or more severed traces, the layout of one or more severed traces being different with respect to which trace is severed for each group of n traces in each tape substrate layer; and a pair of lids for encasing the plurality of stacked tape substrate layers and group of n traces, the pair of lids encasing the substrate layers and traces without molding compound.