Patent ID: 8558596

Claim:
A phase interpolation circuit, comprising: a waveform shaping unit configured to receive a first phase offset input clock signal pair or a second phase offset input clock signal pair, to adaptively waveform-shape the first or second phase offset input clock signal pair, and to output first and second buffered clock signals having a rising time and a falling time each of more than about a quarter of T, where T is a period of the first and second offset input clock signals, wherein the waveform shaping unit includes a current mode logic buffer in which an output resistance value is adaptively changed according to a frequency of the first or second phase offset input clock signal pair, and a skewed feedback loop that maintains a voltage swing level of the first and second buffered clock signals at a constant level regardless of frequency, the skewed feedback loop including: a skewed current mode logic buffer configured to receive the first and second buffered clock signals and to generate feedback first and second clock signals that are skew-controlled., a converter configured to receive the feedback first and second clock signals and to output a single clock pulse having a duty cycle corresponding thereto, and a control logic unit configured to adaptively change the output resistance value of the current mode logic buffer in response to the single clock pulse; and a phase interpolator configured to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal.