Patent ID: 8340152

Claim:
An apparatus comprising: a spread spectrum clock source configured to output a spread spectrum clock signal modulated by a modulation signal and further output the modulation signal; and a logic unit comprising a phase locked loop configured to receive the spread spectrum clock signal and the modulation signal and further configured to generate a logic unit clock signal using the spread spectrum clock signal and the modulation signal to control a frequency of the logic unit clock signal; the phase locked loop comprises: a voltage controlled oscillator that drives the logic unit clock signal; a phase detector configured to output a signal responsive to a phase difference between the logic unit clock signal and the spread spectrum clock signal; and an adder circuit configured to use the modulation signal and the output of the phase detector to control the frequency of the logic unit clock signal; and wherein the adder circuit combines the modulation signal with the output of the phase detector to control the frequency of the logic unit clock signal to be less than proportional to a frequency of the spread spectrum clock signal.