Patent ID: 8732687

Claim:
A program memory space arrangement method of arranging a plurality of functions of a program that is made up of said plurality of functions in a memory space of a processor system that is equipped with an instruction cache, said method comprising: each having a size equal to the instruction cache line size of a target processor, tracing call relations of said instruction code blocks at a time of execution of said program to create flow information of nodes, identification name of each node being expressed by a name of a function to which each instruction code block belongs and an order of the instruction code block from top of the function, said flow information representing in a time series the call relations among instruction code blocks at the time of execution of said program; based on said flow information of nodes, for each node in each function, finding, as neighborhood weight of each instruction code block that belongs to a function that differs from the function to which the instruction code block of the node in question belongs, information for which the frequency of appearance of each node that belongs to a function that differs from the function to which the instruction code block of the node in question belongs in the neighborhood of the node in question in said flow information is taken into consideration; and based on said neighborhood weight information, arranging said plurality of functions in the memory space such that the number of conflicts of said instruction cache is reduced.