Patent ID: 7113436

Claim:
A circuit for use in a semiconductor memory, the device comprising: a direct sense AMP circuit for transmitting read data loaded in a bit line pair including first and second bit lines to a data input/output line pair including first and second data input/output lines in response to a read command signal; an input/output gate circuit for transmitting the read data loaded in the bit line pair to the data input/output line pair and for transmitting write data loaded in the data input/output line pair to the bit line pair, in response to a read/write signal; wherein an operation control unit for generating the read command signal and the read/write signal to turn ON both the direct sense AMP circuit and the input/output gate circuit in response to a column address signal and a write command in a data read operation, and for generating the read command signal and the read/write signal to turn ON the input/output gate circuit and to turn OFF the direct sense AMP circuit in a data write operation.