Patent ID: 7427791

Claim:
A semiconductor integrated circuit device comprising: a main circuit comprising first MOS transistors whose currents flow between first nodes of the first MOS transistors and second nodes of the first MOS transistors; a first power line coupled to the second nodes of the first MOS transistors; a second MOS transistor whose source/drain path is connected between the first power line and a third node; and a second power line coupled to the third node, wherein a thickness of a gate insulation film of the second MOS transistor is thicker than those of the first MOS transistors, wherein an amplitude of a voltage impressed to the gate of the second MOS transistor is larger than those of voltages impressed to gates of the first MOS transistors, wherein a first voltage is supplied from the second power line to the second nodes of the first MOS transistors via the second MOS transistor and the first power line.