Patent ID: 8179359

Claim:
A buffer circuit comprising an input end for receiving an input signal voltage and an output end for outputting a data signal voltage, the buffer circuit comprising: a driving circuit comprising a control end; a biasing circuit for biasing output of the driving circuit at a reference voltage; a first switch coupled to the control end of the driving circuit and turning on in response to a first switching signal; a second switch coupled between a first node and a second node and turning on in response to the first switching signal; a third switch coupled between the input end and the second node and turning on in response to a second switching signal; a fourth switch coupled between the first node and a third node and turning on in response to the second switching signal; a fifth switch coupled between the input end and the third node and turning on in response to a third switching signal; a sixth switch coupled between the first node end and the output end and turning on in response to the third switching signal; a first capacitor coupled between the control end of the driving circuit and the second node; and a second capacitor coupled between the control end of the driving circuit and the third node, wherein the biasing circuit comprises an NMOS element comprising a drain coupled to the first node and a gate, a seventh switch coupled between the reference voltage and the gate of the NMOS element and turning on in response to a fourth switching signal, and a PMOS element comprising a gate coupled to the fourth switching signal and a drain coupled to the gate of the NMOS element.