Patent ID: 8748959

Claim:
A semiconductor memory device comprising: a plurality of memory cells arranged in an array of rows and columns, each memory cell having: a first region electrically connected to a source line; a second region electrically connected to a bit line; and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region; a first barrier wall continuously extending in a first orientation of the array directly adjacent to a first side of the first region of the plurality of memory cells; and a second barrier wall extending in a second orientation of the array directly adjacent to a second side of the first region of the plurality of memory cells; wherein the second barrier wall intersects with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells; wherein the bit line is electrically connected to respective second regions of immediately adjacent memory cells.