Patent ID: 8362815

Claim:
A fractional-N digital phase locked loop configured to receive a reference clock signal and a channel control word, and to generate an output clock signal, the fractional-N digital phase locked loop comprising: an adjustable delay component configured to receive the reference clock signal, apply a time delay to the received reference clock signal in accordance with a time delay control signal, and provide a delayed reference clock signal; a timing component configured to process the delayed reference clock signal and the output clock signal, and generate a first control signal representative of a phase of the output clock signal; a reference accumulator configured to receive the channel command word and generate a second control signal representative of a phase of an intended output clock signal, and the time delay control signal such that the delayed reference clock signal is delayed by a period of time representative of a first portion of the phase of the intended output clock signal; a controller configured to process the first and second control signals, and generate a digitally controlled oscillator (DCO) control signal for setting a DCO frequency in accordance with the first and second control signals; and a DCO configured to generate the output clock signal in accordance with the generated DCO control signal.