Patent ID: 7451412

Claim:
A method for speeding up timing analysis by reusing delays computed for isomorphic subcircuits, comprising: receiving a circuit block to be analyzed, wherein the circuit block is in the form of a netlist; subdividing the circuit block into a set of subcircuits; partitioning the set of subcircuits into equivalence classes, wherein each equivalence class contains subcircuits which are topologically isomorphic to each other as determined using graph isomorphism techniques; and performing a timing analysis for the circuit block by tracing paths through a timing graph for the circuit block, wherein the timing graph is an abstraction of a netlist with vertices representing specific electrical nodes in the circuit block and directed edges representing delays between the specific electrical nodes; wherein whenever a delay is required for a sub circuit during the timing analysis, the method further comprises, determining if a corresponding delay has been already computed for the equivalence class associated with the subcircuit, if so, reusing the delay, and if not, computing the delay for the subcircuit, and associating the computed delay with the equivalence class so that the computed delay can be reused for isomorphic subcircuits.