Patent ID: 7152150

Claim:
A semiconductor memory device, comprising: a memory core circuit; a command circuit which receives commands from an exterior of the device at intervals at least as long as a minimum command cycle; and a timing generator configured to request a read access to said memory core circuit immediately after inputting of a read command if a command supplied from the exterior to said command circuit is the read command, to perform a read operation on said memory core circuit immediately after the request of the read access if there is no currently performed operation in said memory core circuit, to delay performing the read operation on said memory core circuit despite the request of the read access if there is a currently performed operation in said memory core circuit, to request a write access to said memory core circuit after data is fixed prior to an end of a command cycle during which a write command corresponding to said write access is entered from the exterior to said command circuit, to perform a write operation on said memory core circuit immediately after the request of the write access if there is no currently performed operation in said memory core circuit, and to check whether said memory core circuit is currently operating and thus busy, so as to control in response to the check an order in which a plurality of accesses to the memory core circuit are performed if the plurality of accesses conflict with each other with regard to access to said memory core circuit.