Patent ID: 7978111

Claim:
A circuit comprising: a fractional-delay element circuit that receives an input signal S 0 and outputs a first time-shifted version (S 1 ) of the input signal, and that outputs a second time-shifted version (S 2 ) of the input signal, wherein S 2 is time-shifted with respect to S 1 by a fixed fractional amount of a propagation delay through a delay element; a first delay line timestamp circuit (DLTC) that receives S 1 , wherein the first DLTC includes a first delay line through which S 1 propagates; and a second DLTC that receives S 2 , wherein the second DLTC includes a second delay line through which S 2 propagates, wherein the delay element is an inverter, wherein the first delay line is a delay line of inverters, and wherein the second delay line is a delay line of inverters.