Patent ID: 8710641

Claim:
A combination of a main package and an additional package for use to construct a composite layered chip package including the main package and the additional package stacked on each other, wherein: the main package includes a plurality of semiconductor chips that are stacked, and a plurality of first terminals that are associated with different ones of the semiconductor chips; the additional package includes an additional semiconductor chip to substitute for one of the plurality of semiconductor chips in the main package, and at least one second terminal electrically connected to the additional semiconductor chip; the main package and the additional package are arrangeable in any of a plurality of relative positional relationships with each other; the plurality of first terminals and the at least one second terminal are shaped and arranged so that at least one pair of first and second terminals in which the first and second terminals are in contact with each other is formed in each of the plurality of relative positional relationships; a combination of the first and second terminals making up the at least one pair of first and second terminals is different among the plurality of relative positional relationships; and the main package and the additional package are arranged in one of the plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip.