Patent ID: 7242252

Claim:
A circuit comprising: a first transistor having a drain node coupled to a power supply node, and a gate node coupled to receive a bias voltage; a bias network to modify the bias voltage as a voltage on the power supply node changes to maintain a substantially constant drain current in the first transistor, wherein the bias network comprises a first current source and a sensing transistor having a source node coupled to the current source to provide a substantially constant drain current to the sensing transistor, having a drain node coupled to the power supply node, and having a gate node coupled to influence the bias voltage on the gate node of the first transistor; a buffer transistor having a gate node coupled to the gate node of the sensing transistor, and having a source node coupled to provide the bias voltage to the gate node of the first transistor; and a feedback amplifier coupled between the source node of the buffer transistor and the gate node of the first transistor.