Patent ID: 7050515

Claim:
A control word generator, comprising: a power estimate input for receiving a power signal expressed in dB; a threshold register for storing a number equal to the inverse of a desired nomimal power, expressed in dB, said register having an output; a first multiplier having a first input coupled to said power estimate input and having a second input coupled to said output of said threshold register and having an output at which an error signal appears, and having an input to receive a refresh clock signal, and functioning to multiply the values at said first and second inputs each time a refresh clock signal makes one cycle; a resolution clock having an output at which a clock signal appears which cycles at a rate 2n times the rate of said refresh clock; an upper limit register having a data output and a data input and having a reset input for storing a number equal to an upper limit of dynamic range, expressed in dB, and having means for controlling when data at said input is stored in said upper limit register; a step size register having a data output and a data input for storing a number equal to the desired resolution or step size by which the value stored in said upper limit register is to be decremented and having means for controlling when data at said input is stored in said upper limit register; a second multiplier having a first input coupled to said data output of said upper limit register, and having a second input coupled to said output of said step size register, and having a clock input coupled to said output of said resolution clock and having an output coupled to said data input of said upper limit register; a reset input coupled to said reset input of said upper limit register; a comparator having a first data input coupled to said data output of said upper limit register and having a second input coupled to said output of said first multiplier to receive said error signal and having an output at which a signal appears which is logic one when the output of said upper limit register is greater than said error signal and is logic zero when the output of said upper limit register is less than said error signal; a counter having a gating input coupled to said output of said comparator and having a clock input coupled to said output of said resolution clock and having a reset input coupled to said reset input, and having a control word output and functioning to increment on each clock cycle of said resolution clock so long at the value output from said comparator is logic 1.