Patent ID: 8431463

Claim:
A method of forming an integrated circuit, comprising: forming a top level of interconnect metallization; forming a capacitor, including top and bottom electrodes separated by a capacitor dielectric, over the top level of interconnect metallization; forming a layer of passivating dielectric material over the top electrode of the capacitor; and forming: a) an electrical contact to the top electrode, including forming a capacitor via through the layer of passivating dielectric material, concurrently with: b) a bond pad via through the layer of passivating dielectric material, wherein i) the capacitor via is etched during the forming at a slower rate than the bond pad, wherein the capacitor via has a smaller region in the integrated circuit than the bond pad, and ii) an etching of the capacitor via with an etching of the bond pad during the forming is completed for both the capacitor and the bond pad in a single etch; depositing metal in the capacitor via concurrently with forming bond pad metal in a bond pad metallization process, wherein the bond pad metal conductively connects the top electrode of the capacitor to the top level of interconnect metallization.