Patent ID: 8013374

Claim:
A semiconductor memory device comprising: a substrate including a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis, wherein the length is greater than the width, wherein the plurality of active regions are provided in a plurality of columns of active regions in the direction of the second axis; a plurality of wordline pairs on the substrate, wherein each wordline pair crosses active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair; and a plurality of bitlines on the substrate crossing the plurality of wordline pairs, wherein each bitline is electrically coupled to a respective drain portion of an active region of each column, wherein each bitline is arranged between the respective drain portion and another drain portion of an adjacent active region of the same column, wherein one of the plurality of bitlines includes first and second portions crossing respective first and second columns of the active regions, and wherein the first and second portions of the bitline are parallel in the direction of the first axis and offset in the direction of the second axis.