Patent ID: 8281113

Claim:
An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor, comprising: a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing said operation of said prescribed bit length into N equal parts in a bit length direction (a divisor N is an integer not smaller than 2); a plurality of pipeline registers provided so as to separate said pipeline stages from each other, wherein each of said pipeline registers operates in such a manner so as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output; and a clock control unit comprising: a clock inverter which supplies a clock signal to each of said sub-arithmetic-logic units and each of said pipeline registers, and a mode switching signal generator which supplies a mode switching signal to each of said pipeline registers; wherein said divisor N is changed dynamically so as to change the number of parallel execution of said operation dynamically.