Patent ID: 7378879

Claim:
An integrated circuit comprising: an X:Y decoder adapted to receive X input signals (e.g., D, E, and F) and provide Y decoded signals, wherein Y is less than 2 X , the decoder including logic gates adapted to partially decode the X input signals based on true (e.g., D, E, and F) and complement (e.g., D′, EF′, and F′) values of the input signals, wherein X is three and each such logic gate is adapted to receive fewer than X true values of the input signals and includes an AND gate adapted to receive one true value of an input signal and two complement values of input signals; and a multiplexer adapted to receive a plurality of multiplexer input signals and the Y decoded signals and provide a multiplexer output signal, wherein the Y decoded signals determine which one of the multiplexer input signals to provide as the multiplexer output signal.