Patent ID: 8090899

Claim:
A solid state drive comprising: a first flash memory device logically divided into a first plurality of blocks, each of the first plurality of blocks being logically divided into addressable pages; a second flash memory device logically divided into a second plurality of blocks, each of the second plurality of blocks being logically divided into addressable pages; a memory controller coupled to the first flash memory device and the second flash memory device, the memory controller configured to logically associate a first block of the first plurality of blocks with a second block of the second plurality of blocks to form a first zip code, the first zip code associated with a first erase counter, and configured to logically associate a first source block of the first plurality of blocks with a second source block of the second plurality of blocks to form a second zip code, the second zip code associated with a second erase counter; a processor coupled to the memory controller and operable to execute instructions; and a computer-readable memory having instructions stored thereon that are executable by the processor in order to cause the processor to perform a wear-leveling operation, by: determining that the first block and the second block in the first zip code have been erased; based at least in part on the determination, incrementing the first erase counter associated with the first zip code; after incrementing the first erase counter, determining that the second erase counter associated with the second zip code is low relative to at least one other erase counter; and based at least in part on determining that the second erase counter is low, writing data from the first source block and the second source block in the second zip code to a first target block of the first plurality of blocks and a second target block of the second plurality of blocks as part of the wear-leveling operation.