Patent ID: 7139266

Claim:
A method for configuring an equivalent 2 n ×2 n k-stage bit-permuting network based on a given 2 n ×2 n k-stage bit-permuting network having a representation [σ 0 :σ 1 :σ 2 : . . . :σ k−1 :σ k ] n , the method comprising: specifying a permutation κ on integers from 1 to n that preserves n, and implementing the equivalent network as [σ 0 :σ 1 : . . . :σ j−1 κ:κ −1 σ j : . . . :σ k ] n , j=1, 2 . . . or k, where: n equals the number of bits in the network address labels; k equals the number of stages of the network; [σ 0 :σ 1 :σ 2 : . . . :σ k−1 :σ k ] n is the permutation of the address bits between each of the k stages of the network; and κ j−1 is an additional permutation of the address bits between the j−1 stage and the jth stage.