Patent ID: 7961027

Claim:
An apparatus, comprising: a clock integrated circuit, comprising: a latch generating a clock signal output of the clock integrated circuit, the latch including cross-coupled gates, such that outputs of the cross-coupled gates in the latch are coupled to inputs of different cross-coupled gates in the latch; timing circuitry coupled to an output of the latch, an output of the timing circuitry alternating between a first reference signal and a second reference signal at a rate determined by a time constant having temperature dependence, the output of the timing circuitry determining timing of the clock signal output; inverter circuitry comparing an output of the timing circuitry against a temperature compensated trigger point of the inverter circuitry, such that the timing of the clock signal output of the clock integrated circuit resists variation with temperature, an output of the inverter circuitry coupled to an input of the latch.