Patent ID: 6924552

Claim:
A multilayered integrated circuit comprising: an upper conductive layer having upper conductive lines for carrying electrical signals among components of the integrated circuit; a lower conductive layer having lower conductive lines for carrying electrical signals among components of the integrated circuit; and an intermediate layer having conductive via holes electrically connecting the upper conductive lines with the lower conductive lines, wherein at least one line among either the upper conductive lines or the lower conductive lines is an extraneous conductive line; at least one via hole among the conductive via holes is an extraneous via hole; the at least one extraneous conductive line is made of a material which is the same as the material of the upper and lower conductive lines; and the at least one extraneous conductive line and extraneous via hole form an extraneous path, not connected to the operational functionality of the circuit, in order to confuse a reverse engineer.