Patent ID: 8549212

Claim:
A flash storage device, comprising: a flash memory, comprising a plurality of blocks, wherein each of the blocks comprises a plurality of pages for storing data, and each of the pages has a physical address; a controller, dividing a plurality of logical addresses into a plurality of logical address ranges, recording a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, storing each of the partial link tables in a page of the flash memory, combining the partial link tables to obtain a link table, converting logical addresses sent by a host to physical addresses according to the link table, and maintaining an index table for recording a mapping relationship between the partial link tables and physical addresses of pages storing the partial link tables, wherein when the controller receives write data to be written to a target logical address from the host, the controller determines whether the target logical address falls in a logical address range of a target partial link table corresponding to a previous write data.