Patent ID: 7879516

Claim:
A manufacturing method of a semiconductor integrated circuit device, comprising the steps of: (a) forming a to-be-treated undercoat film over a first main surface of each of first and second wafers; (b) forming a photoresist film over the to-be-treated undercoat film formed over the first main surface of each of the first and second wafers; (c) exposing and developing the photoresist film formed over the first main surface of the first wafer by a reduced projection exposure apparatus to form a line and space pattern through the photoresist film; (d) measuring the line and space pattern formed over the first main surface of the first wafer optically by scatterometry to acquire parameters on a two-dimensional shape of a section of the line and space pattern; (e) estimating a focus condition on the basis of the parameters; (f) on the basis of the estimated focus condition, correcting a focus setting included among exposure conditions in the reduced projection exposure apparatus; and (g) on the basis of the corrected exposure condition, exposing and developing the photoresist film formed over the first main surface of the second wafer by the reduced projection exposure apparatus to form a circuit pattern through the photoresist film, wherein the estimation in step (e) comprises performing a calculation using the parameters acquired in step (d) and using a conjectural expression obtained by multivariate regression analysis of a partial least squares (PLS) method.