Patent ID: 8310488

Claim:
A computer graphics apparatus, comprising: a) a central processing unit (CPU), wherein the CPU is configured to produce graphics input in a format having an architecture-neutral display list for a sequence of frames; b) a memory coupled to the central processing unit; c) first and second graphics processing units (GPU) coupled to the central processing unit, wherein the first GPU is architecturally dissimilar from the second GPU; and d) a just-in-time compiler coupled to the CPU and the first and second GPU configured to translate instructions in the architecture neutral display list into an architecture specific format for an active GPU of the first and second GPU, wherein the just-in-time compiler is configured to: i) monitor a power consumption of the active GPU, and ii) determine whether to switch between the active GPU and an inactive GPU of the first and second GPU based on the power consumption of the active GPU, iii) perform a context switch between the active GPU and the inactive GPU, wherein the active GPU becomes inactive and the inactive GPU becomes active to process a next frame of the sequence of frames, and iv) turn off the one of the first and second GPU that is inactive after the context switch.