Patent ID: 7325182

Claim:
A method for testing electrical modules, comprising: applying a test pattern of input signals to each module; applying the same test pattern to a reference module, wherein the reference module is of the same design and technology as the electrical modules being tested; wherein each electrical module and the reference module are digital data memories each containing a multiplicity of addressable memory cells and having data ports to input data bits to be stored in a write mode and to output stored data bits in a read mode; wherein each data port in the electrical modules and in the reference module comprises a bidirectional port arranged between an assigned external data terminal and an assigned internal data line, the bi-directional port comprising: a reception transfer channel that can be switched on selectively for data bits to be written; a transmission transfer channel that can be switched on selectively for reading-out data bits; and a switching device provided for each data port in each electrical module, wherein the switching device, in a first switching state, switches on the reception transfer channel and inhibits the transmission transfer channel and, in a second switching state, switches on the transmission transfer channel and inhibits the reception transfer channel, wherein the switching device is changeable into a third state in which the reception transfer channel and the transmission transfer channel remain interrupted, the internal data line remain connected to the actual response input of the assigned comparator and the external data terminal remain connected to the desired response input of the assigned comparator; wherein the test pattern comprises data bits that are applied together with a write command and with addressing signals to the electrical modules and to the reference module to write the data bits to addressed memory cells of both the reference module and the electrical modules; wherein the test patterns are applied utilizing a common test control unit, which, for writing in the data bits of the test pattern, applies the same pattern of write addressing signals for the selection of the memory cells to each electrical module and to the reference module, and for reading from the memory cells filled with the data bits of the test pattern, applies the same pattern of read addressing signals to each electrical module and to the reference module; comparing, utilizing a comparison device, actual responses of each module to the test pattern with desired responses to the test pattern provided by the reference module, wherein the comparing produces a comparison result, wherein the comparison device includes a comparator for each data port of the electrical module, wherein the comparator compares a signal appearing at a relevant data port of the respective electrical module as actual response with the desired response at the corresponding data port of the reference module; and evaluating the comparison result to produce a test assessment.