Patent ID: 7463094

Claim:
A linearized Class AB biased differential circuit comprising: an input matched transistor pair consisting of a first type one transistor and a second type one transistor; and a first current mirror composed of a second type two transistor of a unity size having said collector and base connected to base of third type two transistor of a size N having emitter of the second type two transistor connected to the emitter the third type two transistor; and a second current mirror composed of a fifth type two transistor of unity size having said collector and base connected to base of fourth type two transistor of size N having emitter of the fifth type two transistor connected to the emitter the fourth type two transistor; and a first diode consisting of a first type two transistor of a M size having said collector and base connected; and a second diode consisting of a sixth type two transistor of M size having said collector and base connected; and a matched pair of current sources consisting of a first current source and a second current source; and respective emitter of said first type one transistor is coupled to emitter of first diode and emitters of second current mirror; and respective emitter of said second type one transistor is coupled to emitter of second diode and emitters of first current mirror; and respective collector and base of said first diode and common bases of said first current mirror are connected to first current; and respective collector and base of said second diode and common bases of said second current mirror are connected to second current; and respective bases of said first type one transistor and second type one transistor are connect to a first and second input terminals; and respective collectors of said first type one transistor and second type one transistor are connect to a first and second output terminals; and respective collectors of said third type two and fourth type two transistor are connect to a third and fourth output terminals; and such that the said size N defines a maximum output current gain relative to the matched current sources; and a ratio of said size M to said size N defines a DC output current relative to the matched current sources.