Patent ID: 8605019

Claim:
A display device comprising: a plurality of pixels; first storage capacitor bus lines each driven by a first driving signal; second storage capacitor bus lines each driven by a second driving signal, each of the first driving signal and the second driving signal have a waveform in which, for each frame period, a polarity is reversed with respect to that of a reference potential for each set of a plurality of horizontal periods and a phase of the first driving signal is shifted from that of the second driving signal, data signals written to respective ones of the plurality of pixels are reversed in polarity for each set of consecutive horizontal periods within each frame and the plurality of pixels are such that the data signals which are reversed in polarity for the each frame are written respectively in the plurality of pixels; and correcting means for correcting a gray scale of display data of each of the data signals to be written in respective first pixels and supplying the display data to a display driver, when (i) each set of the plurality of horizontal periods during which the polarity of each of the first driving signal and the second driving signal is constant is one cyclic term, (ii) a first cyclic term of each of the first driving signal and the second driving signal in the each frame is a cyclic term of the frame, during which the data signals are first written respectively in the plurality of pixels which correspond to the respective first storage capacitor bus lines or the respective second storage capacitor bus lines, (iii) the first driving signal has a first polarity during a B-th horizontal period in an A-th cyclic period of the first driving signal, (iv) the B-th horizontal period in the A-th cyclic period of the first driving signal is allocated for writing of the data signals in the respective first pixels which correspond to the respective first storage capacitor bus lines driven by the first driving signal, (v) the second driving signal has the first polarity during the B-th horizontal period in the A-th cyclic period of the second driving signal, and (vi) the B-th horizontal period in the A-th cyclic period of the second driving signal is not allocated for writing of the data signals in any pixels of the plurality of pixels which correspond to the respective second storage capacitor bus lines driven by the second driving signal.