Patent ID: 8897037

Claim:
A system for discharging a capacitor of a power conversion system, the system comprising: a first capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal being connected to a first input terminal, the second capacitor terminal being connected to a second input terminal; a second capacitor including a third capacitor terminal and a fourth capacitor terminal, the fourth capacitor terminal being biased to a predetermined voltage; a first diode including a first anode and a first cathode, the first anode being connected to the first input terminal; a second diode including a second anode and a second cathode, the second anode being connected to the second input terminal; and a system controller including a first controller terminal, a second controller terminal, a third controller terminal, and a fourth controller terminal, the first controller terminal being connected to the first cathode and the second cathode, the second controller terminal being connected to the second input terminal, the third controller terminal being biased to the predetermined voltage, the fourth controller terminal being connected to the third capacitor terminal; wherein: the system controller further includes a detection component, a transistor, and an under-voltage-lockout component; the detection component is configured to receive a first input voltage from the second input terminal through the second controller terminal, receive a first signal from the under-voltage-lockout component, generate a second signal based on at least information associated with the first input voltage and the first signal, and send the second signal to the first transistor, the second signal being at a logic high level if the first input voltage is lower than a first threshold voltage in magnitude and the first signal is at the logic high level; the transistor includes a first transistor terminal, a second transistor terminal, and a third transistor terminal, the first transistor terminal being configured to receive the second signal from the detection component, the second transistor terminal being connected to the third controller terminal; and the under-voltage-lockout component is configured to receive a second input voltage from the third capacitor terminal through the fourth controller terminal and generate the first signal based on at least information associated with the second input voltage, the second signal being at the logic high level if the second input voltage is higher than a second threshold voltage in magnitude.