Patent ID: 7688237

Claim:
A flash analog-to-digital converter (ADC), comprising: a plurality of slices, wherein a slice of the plurality of slices includes: a digital to analog converter (DAC), comprising: a plurality of signal generating elements; a comparator configured to receive first and second inputs and to output a comparator signal indicative of a difference between the first and second inputs; and a digital processing unit (DPU) coupled to the comparator and the DAC, the DPU being configured to determine an offset of the comparator based on the comparator signal by summing a plurality of samples of the comparator signal to determine a sum and determining whether an absolute value of the sum is greater than half a number of samples in the plurality of samples, and selectively activate or deactivate one or more signal generating elements of the plurality of signal generating elements to generate a correction signal that corrects an offset of the comparator; wherein if the absolute value is greater than half the number of samples, the DPU deactivates the one or more signal generating elements, wherein if the absolute value is less than half the number of samples, the DPU activates the one or more signal generating elements, and wherein the comparator is configured to receive the correction signal.