Patent ID: 7229881

Claim:
A method for manufacturing DRAM of semiconductor device, the method comprising the steps of: providing a semiconductor substrate having a first region, a second region, and a channel region disposed in the first region and the second region, the first region including a cell region and the second region including a pMOS region and an nMOS region; sequentially forming a lower gate oxide film, an intermediate gate insulating film including an electron/hole trap and a buffer oxide film; at least removing the buffer oxide film and the intermediate gate insulating film in the nMOS region of the second region to expose a portion of the lower gate oxide film in the second region; at least removing a predetermined thickness of the buffer oxide film and the entire exposed lower gate oxide film in the second region; forming an upper gate oxide film on the intermediate gate insulating film and at least on the semiconductor substrate in the nMOS region of the pMOS region and the nMOS region; forming a stacked structure of a gate conductive layer and a CVD insulating film; and patterning the stacked structure to form the gate electrode pattern.