Patent ID: 7994621

Claim:
A stacked semiconductor package, comprising: a substrate having connection pads and a chip selection pad disposed adjacently to the connection pads; a semiconductor chip module including a plurality of semiconductor chips, each semiconductor chip including: data bonding pads; a chip selection bonding pad; data redistribution units electrically connected to the data bonding pads; and a plurality of through electrodes that pass through corresponding data bonding pads and pass through the semiconductor chip, some of the through electrodes electrically connecting the data bonding pads to the data redistribution units, wherein the semiconductor chips being stacked so as to expose the chip selection bonding pad, wherein data redistribution units and data through electrodes that are arranged on step surfaces of the semiconductor chips; and a conductive wire electrically connecting the chip selection pad to the chip selection bonding pad, wherein an address signal, a power signal, a data signal and a control signal are input to the data redistribution unit, and wherein the chip selection pad includes a ground voltage pad applied with a ground voltage (Vss) and a power voltage pad applied with a power voltage (Vcc).