Patent ID: 7935564

Claim:
A method for forming a memory cell structure, the method comprising: forming at least one bottom insulating layer over a substrate, the bottom insulating layer comprised of a first insulating material; forming at least one intermediate insulating layer over the substrate, the intermediate insulating layer comprised of a second insulating material, the second insulating material being separately removable from the first insulating material; forming at least one top insulating layer over the substrate, the top insulating layer comprised of a third insulating material, the third insulating material being separately removable from the second insulating material; forming a via in the top insulating layer and the intermediate insulating layer; forming an undercut in the intermediate insulating layer such that the top insulating layer overhangs the intermediate insulating layer within the via; forming a step spacer of a spacer material in the via such that a cavity is created over the bottom insulating layer, the cavity dimension being independent of the diameter of the via, the step spacer surrounding a passage, the passage extending to the bottom insulating layer; etching the bottom insulating layer such that the passage is extended through the bottom insulating layer; removing the step spacer; forming a bottom electrode ring filling the passage in the bottom insulating layer completely, the bottom electrode ring comprised of an outer conductive material and an inner insulating material; forming a phase change layer comprised of a phase change material over the bottom electrode ring; and forming a top electrode layer comprised of a conductive material above the phase change material.