Patent ID: 7818360

Claim:
A processor for performing a Fast Fourier Transform (FFT) and/or an Inverse Fast Fourier Transform (IFFT) of a complex input signal having a real component and an imaginary component, the processor comprising: a first stage for passing the input signal to a second stage when a Fast Fourier Transform procedure is to be performed and for swapping the real and imaginary components of the complex input signal before passing the signal to a second stage if an Inverse Fast Fourier Transform procedure is to be performed; the first stage having an input and an output; the second stage comprising a first radix-4 butterfly element and a second radix-4 butterfly element; the output of the first stage being connectable to an input of the second stage; a third stage for switching between a first operating mode and a second operating mode, the second operating mode being for processing a complex conjugate symmetrical input signal; a fourth stage comprising a plurality of processing units to provide a processed signal comprising a real component and an imaginary component, one or more of said processing units comprising a radix-2 pipelined Fast Fourier Transform (FFT) processor; a fifth stage for switching with the third stage between the first operating mode and the second operating mode; the fifth stage having an input couplable to an output of the fourth stage and an output; a sixth stage for passing the signal received from the output of the fifth stage if a Fast Fourier Transform procedure is performed and for swapping the real and imaginary components of the signal received from the output of the fifth stage before passing the signal to an output of the sixth stage if an Inverse Fast Fourier Transform procedure is performed; wherein: a first input to the third stage being couplable to an output of the first butterfly element; a first output to the third stage being couplable to a first input of one or more of the plurality of processing units; and a second input to one or more of the plurality of processing units being couplable through the third stage to an output of the second butterfly element; the first and second radix-4 butterfly elements being arranged to perform a butterfly operation on the complex input signal to generate and deliver one or more components of a processed signal to the fourth stage through the third stage; the fourth stage being arranged to process the processed signal received from the third stage according to a Fast Fourier Transform (FFT) processing procedure to produce an output signal.