Patent ID: 7417327

Claim:
An IC (integrated circuit) chip package comprising: a substrate comprising: a top surface; a bottom surface; a receiving chamber defined therein, having an opening at the top surface; a plurality of solder pads arranged around the top surface; a plurality of solder pads arranged around the bottom surface, respectively corresponding to the solder pads arranged around the top surface; and a plurality of vias defined therein, the vias having conductive material electrically connecting the top solder pads with the bottom solder pads; a chip mounted in the receiving chamber of the substrate, the chip comprising a plurality of solder pads arranged around a top surface thereof; a plurality of bonding wires respectively electrically connecting the top solder pads of the substrate and the solder pads of the chip, and areas where the bonding wires connect with the top solder pads of the substrate and the solder pads of the chip are covered with an adhesive; and a cover fastened to the top surface of the substrate and covering the opening, the cover having a smaller profile than that of the substrate, a peripheral area of the top surface being not covered by the cover.