Patent ID: 8614449

Claim:
A method comprising: providing a wafer assembly comprising a plurality of semiconductor dies formed on a carrier substrate, the dies separated by street areas formed between the dies and having an n-doped layer coupled to the carrier substrate, and a p-doped layer disposed above the n-doped layer; filling in at least a portion of the street areas with a first electrically non-conductive material; forming a metal plate above the plurality of semiconductor dies such that the first non-conductive material sustains the metal plate, at least during formation, at or above the maximum height of the p-doped layer for the plurality of semiconductor dies; removing the carrier substrate from the wafer assembly; forming, for each of the dies, an electrode adjacent a surface of the n-doped layer exposed by removal of the carrier substrate, such that a part of the surface of the n-doped layer is not covered by the electrode; adding a second non-conductive material to a portion of the part of the surface of the n-doped layer, wherein the second non-conductive material is non-reflective; and dicing the wafer assembly to separate the plurality of semiconductor dies such that the first and second non-conductive materials remain with the separated semiconductor dies after dicing.