Patent ID: 6845348

Claim:
A method of calculating a switching threshold delay and a slope delay for a gate input signal of a cell comprising steps of: (a) initializing estimates of a first effective capacitance Ceff1, of a second effective capacitance Ceff2, of a switching threshold delay to, and of a slope delay deltat for a gate input signal of a cell; (b) solving ramp response equations for a capacitive load and a driver resistance to calculate solutions for t0 and deltat as a function of the first effective capacitance Ceff1 for a rising or falling transition voltage of the gate input signal and as a function of the second effective capacitance Ceff2 for fifty percent of a final transition voltage of the gate input signal; (c) if the calculated solutions for t0 and deltat have converged to the estimates of t0 and deltat within a desired accuracy, then continuing from step (e), else continuing from step (d); (d) replacing the estimates of t0 and deltat with the calculated solutions for t0 and deltat, respectively, and continuing from step (b); and (e) generating as output the calculated solutions for the switching threshold delay t0 and the slope delay deltat for the gate input signal of the cell.