Patent ID: 8349737

Claim:
A method of manufacturing an array substrate, the method comprising: using a first and a second mask, performing: forming a gate electrode and a gate line on a substrate; forming a gate insulating layer on the gate electrode and the gate line; forming an active layer and an ohmic contact layer on the gate insulating layer; forming source and drain electrodes on the ohmic contact layer and a data line on the gate insulating layer, the data line crossing the gate line to define a pixel region; using a third mask, performing: forming an insulating layer on substantially an entire surface of the substrate including the source and drain electrodes and the data line; forming a photoresist pattern having an angled corner on the insulating layer; forming a passivation layer by selectively removing the insulating layer using the photoresist pattern as an etching mask; forming a first transparent conductive layer on the photoresist pattern and a second transparent conductive layer on a remaining surface of the substrate, wherein the first transparent conductive layer and the second transparent conductive layer are electrically disconnected from each other; heat-treating the substrate including the first transparent conductive layer having the photoresist pattern underlying and the second transparent conductive layer on the remaining surface of the substrate, wherein the photoresist pattern forms a rounded corner after heat treating; and forming a pixel electrode by removing the photoresist pattern and the first transparent conductive layer on the photoresist pattern, wherein the photoresist pattern is deformed by a thermal expansion due to the heat-treating, and cracks are formed in the first transparent conductive layer, and wherein the photoresist pattern and the first transparent conductive layer on the photoresist pattern are removed by exposing the heat-treated substrate to a stripper material, and wherein the photoresist pattern is exposed through the cracks, and the stripper material permeates into the photoresist pattern through the cracks, and wherein the insulating layer is over-etched, and surrounding edges of the passivation layer are disposed inside surrounding edges of the photoresist pattern, and wherein the second transparent conductive layer is disconnected from the first transparent conductive layer around the surrounding edges of the passivation layer and the surrounding edges of the photoresist pattern, and wherein forming the gate insulating layer includes patterning the gate insulating layer; and wherein patterning the gate insulating layer, forming the active layer and the ohmic contact layer, and forming the source and drain electrodes are performed through a same mask process as one another using the first and second masks.