Patent ID: 7989809

Claim:
A thin film transistor array panel, comprising: a plurality of gate lines; a plurality of data lines intersecting the gate lines; a plurality of switching elements connected to the gate lines and the data lines; a plurality of pixel electrodes connected to the switching elements; an interlayer insulating layer formed between the gate lines and the data lines; a passivation layer covering the gate lines, the data lines, and the switching elements, the passivation layer having a plurality of first contact holes exposing portions of the data lines, wherein the switching elements and the pixel electrodes are connected through the first contact holes; a plurality of contact assistants formed on the passivation layer and connected to the data lines through a plurality of second contact holes in the passivation layer; and a plurality of auxiliary lines connected to the data lines through a plurality of third contact holes in the interlayer insulating layer, wherein the third contact holes do not overlap the second contact holes and are completely covered by the passivation layer.