Patent ID: 8427833

Claim:
A three-dimensional very-large-scale integration (VLSI) device, comprising; a processor layer coupled, via a first set coupling devices, to at least one signaling and input/output (I/O) layer; and a power delivery layer coupled, via a second set of coupling devices, to the processor layer, wherein: the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias (TLVs), each TLV in the plurality of TLVs is coupled to one of the plurality of conductors or the one or more ground planes while not being coupled to other ones of the plurality of TLVs, and the at least one signaling and input/output(I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.