Patent ID: 8189402

Claim:
A sensing circuit for a memory cell supplied with low power, comprising: a sensing stage, comprising: a first P-type MOSFET having a gate connected to a memory cell for receiving an output current of the memory cell; a first N-type MOSFET having a drain connected to a drain of the first P-type MOSFET, and having a source connected to ground; and a second P-type MOSFET having a drain connected to a source of the first P-type MOSFET, having a gate connected to an output terminal of the inverter, and having a source connected to a supplied voltage; an inverter having an input terminal connected to the drain of the first N-type MOSFET; and a reference transistor having a gate connected to a reference signal, and having a drain connected to the gate of the first P-type MOSFET; wherein a voltage at the output terminal of the inverter is used for indicating a program state or an erase state of the memory cell; wherein a current flowing through the first N-type MOSFET is compared with a current flowing through the first P-type MOSFET; wherein a current of the reference transistor is compared with a current generated from the memory cell.