Patent ID: 7266740

Claim:
A method of testing a digital frequency synthesizer (DFS) circuit in a programmable integrated circuit, the DFS circuit having a programmable multiplier M and a programmable divider D, M and D being integers, the method comprising: allocating an array with a size determined by minimum and maximum values specified for M divided by D (M/D) and by a specified resolution for M/D, wherein M, D, and M/D define an MD area to be tested, the MD area including a plurality of MD pairs for which M, D, and M/D fall within ranges defined by the specified minimum and maximum values; selecting an MD pair in the MD area; calculating an M/D ratio for the selected MD pair; idealizing the calculated M/D ratio based on the specified resolution; storing the selected MD pair in an array location specified by the idealized M/D ratio; and repeating the selecting, calculating, idealizing, and storing for each additional MD pair in the MD area.