Patent ID: 8762631

Claim:
A memory system comprising: a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a data erasing unit; and a controller configured to: receive a logical address in association with a read request; retrieve a first information associated with a physical address of the nonvolatile memory by searching a first address management table with the logical address; readout data from at least one of the plurality of pages indicated by the first information; retrieve a second information associated with the logical address by searching a second address management table with the physical address; select at least one first block in the plurality of blocks by using the second address management table, and copy valid data from the at least one first block to a second block, of the plurality of blocks, wherein an amount of the valid data in the at least one first block does not exceed a threshold and the valid data is managed with a first management unit smaller than a size of one block; and link the second address management table with the first address management table by using a pointer to the logical address in the first address management table.