Patent ID: 6927453

Claim:
A metal-oxide-semiconductor (MOS) device, comprising: a semiconductor layer of a first conductivity type; a source region of a second conductivity type formed in the semiconductor layer; a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region; a gate formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions; a buried lightly-doped drain (LDD) region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being formed below at least a portion of the drain region and extending laterally from the drain region to below at least a portion of the gate; and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer, the second LDD region being self-aligned with a first alignment structure formed substantially concurrently with the gate in a same processing step, the second LDD region being spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.