Patent ID: 7394721

Claim:
A microprocessor, comprising: a memory controller configured to communicate with external memory over a bi-directional bus; read capture logic configured to propagate a transition of a read enable signal generated by the memory controller in response to a read command issued by the memory controller, the read capture logic causing a delay in the transition of the read enable signal, the delay in the transition of the read enable signal accommodating different latencies associated with strobe signals from the external memory received over the bi-directional bus, wherein the transition of the read enable signal indicates valid data is available for sampling over the bi-directional bus; and data read out multiplexor select logic generating a select signal configured to select data from a storage element in the read capture logic having valid captured data, the select signal further configured to enable transmission of the data from the storage element having valid data through a multiplexor while preventing transmission of data from other storage elements through the multiplexor, the data read out multiplexor select logic including circuitry configured to generate a signal to the memory controller, the signal indicating valid data is available for transmission from a memory module to a L2 cache.