Patent ID: 7889564

Claim:
A semiconductor memory device, comprising: a memory cell array including, a memory cell array block having a plurality of memory cells connected between a plurality of word lines, a plurality of source lines and a plurality of bit lines and having floating body transistors, and a plurality of sense amplifiers connected to the plurality bit lines, each of the plurality of sense amplifiers being configured to amplify a signal of the corresponding bit line and output the amplified signal to a data input/output line, apply, based on a restore signal, a first voltage to a corresponding bit line to restore a first data value in a selected memory cell of the plurality of memory cells if a state of the data input/output line is a state corresponding to the first data value and apply a second voltage based on the restore signal to the corresponding bit line to prevent a second data value from being restored in the selected memory cell if the state of the data input/output line is a state corresponding to the second data value.