Patent ID: 7889593

Claim:
A command latch operable to latch command data using a command clock signal, where the command data and the command clock signal are delayed relative to each other, the command latch comprising: a latch circuit configured to receive the command data and receive a selected internal clock signal appropriate to latch the command data, the latch circuit operable to latch the command data in accordance with the selected internal clock signal; a clock generator configured to receive a master clock signal based on the command clock signal, the clock generator operable to generate a plurality of internal clock signals, including the selected internal clock signal and a reference clock signal, each internal clock signal having a different phase relative to the command clock signal and the reference clock signal having a phase relative to the command clock signal, the clock generator further configured to receive a select signal, the clock generator operable to couple the selected internal clock signal to the latch circuit responsive to the select signal wherein the clock generator comprises: a first locked loop operable to lock the phase between a first one of the plurality of internal clock signals and the reference clock signal; and a second locked loop operable to lock the phase between the master clock signal and the reference clock signal; a select circuit coupled to the latch circuit and the clock generator, the select circuit operable to identify the selected internal clock signal from the plurality of internal clock signals and generate the select signal for the clock generator.