Patent ID: 7195984

Claim:
A method for forming an integrated circuit, comprising: providing a semiconductor substrate with an upper surface; forming an n-type collector region contained in said semiconductor substrate; forming a p-type collector region contained in said semiconductor substrate and separated from said n-type collector region; forming a p-type base region contained in said n-type collector region; forming an-type base region contained in said p-type collector region; forming an n-type emitter region with an upper surface contained in said p-type base region; forming a p-type emitter region with an upper surface contained in said n-type base region; forming a first interfacial oxide layer with an upper surface formed on said upper surface of said n-type emitter region; forming a second interfacial oxide layer with an upper surface formed on said upper surface of said p-type emitter region; forming a p-type-emitter layer on said upper surface of said second interfacial oxide layer wherein said p-type polysilicon emitter layer does not contain fluorine; and forming an n-type polysilicon emitter layer on said upper surface of said first interfacial oxide layer wherein said n-type polysilicon emitter contains fluorine.