Patent ID: 7374986

Claim:
A method of fabricating a field effect transistor (FET), comprising: forming a channel forming preparation layer on the semiconductor substrate, the channel forming preparation layer including a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer sequentially stacked on the semiconductor substrate; forming a hard mask layer on the channel forming preparation layer; patterning the hard mask layer and the channel forming preparation layer to define an active region of the semiconductor substrate; patterning the hard mask layer to narrow the hard mask layer, thereby exposing an edge portion of an upper surface of the channel forming preparation layer; forming a first dielectric layer on the semiconductor substrate to cover the narrowed hard mask layer and the channel forming preparation layer, then planarizing the first dielectric layer to expose the narrowed hard mask layer; patterning the first dielectric layer and a portion of the narrowed hard mask layer to remove a portion of the narrowed hard mask layer, thereby forming a dummy gate pattern and exposing a portion of the channel forming preparation layer; selectively etching the exposed portion of the channel forming preparation layer adjacent to the dummy gate pattern to expose the semiconductor substrate; selectively growing an epitaxial layer on the exposed semiconductor substrate to form source and drain patterns adjacent to the channel forming preparation layer; forming a second dielectric layer on the semiconductor substrate including the dummy gate and the source and drain patterns and then planarizing the second dielectric layer to expose the dummy gate pattern; selectively etching the remaining hard mask layer to remove the remaining hard mask layer, thereby exposing a portion of the channel forming preparation layer and then etching the exposed portion of the channel forming preparation layer to expose the semiconductor substrate; removing the second dielectric layer and an upper portion of the first dielectric layer to expose sidewalls of the channel forming preparation layer remaining on the semiconductor substrate; selectively etching the channel forming preparation layer to remove the first and second sacrificial layers, thereby forming a plurality of wire channels from the first and second channel layers; forming a gate dielectric layer on the semiconductor substrate to surround each of the plurality of wire channels; forming a gate electrode on the gate dielectric layer to form a gate surrounding each of the plurality of wire channels.