Patent ID: 8782479

Claim:
An on-chip test architecture comprising: a scan chain for connecting to internal logic; a receiving boundary scan flop for receiving post-bond scan input; a sending boundary scan flop for receiving and outputting post-bond scan output; a plurality of gated scan flops, each gated scan flop of the plurality of gated scan flops being connected to a corresponding through silicon via (TSV), wherein the plurality of gated scan flops comprises: a sending gated scan flop for receiving pre-bond scan output and outputting the pre-bond scan output through its connected TSV, and a receiving gated scan flop for receiving a pre-bond scan input through its connected TSV; a first multiplexer (MUX) selectively connecting the receiving gated scan flop to an input of the scan chain; and a second MUX selectively connecting an output of the scan chain to the sending gated scan flop.