Patent ID: 8765553

Claim:
A method of making a nonvolatile memory cell array integrated circuit, comprising: forming a plurality of columns of nonvolatile memory cells in the array, each column of the plurality of columns including a plurality of nonvolatile memory cells arranged in a series, including: prior to forming a recess, scaling a first gate length by forming a dielectric layer and removing parts of the dielectric layer; forming a charge storage structure and one or more dielectric structures for each nonvolatile memory cell in the array in the recess, wherein the charge storage structure stores charge to control a logical state stored by the nonvolatile memory cell integrated circuit, and the one or more dielectric structures are 1) at least partly between the charge storage structure and a channel region and 2) at least partly between the charge storage structure and a source of gate voltage; and forming a conductive layer providing the gate voltage; forming bit lines providing drain voltage and source voltage to each column of nonvolatile memory cells in the array, such that a subset of nonvolatile memory cells in each column are electrically connected to a bit line via other nonvolatile memory cells in the series; wherein, for each nonvolatile memory cell of the array, an interface separates part of the one or more dielectric structures from the channel region, and a first end of the interface ends at an intermediate depth of a first bit line and a second end of the interface ends at an intermediate depth of a second bit line.