Patent ID: 7970959

Claim:
A DMA transfer system, comprising: a DMA controller having at least one CPU channel and at least one extension channel coupled to a system bus, the DMA controller configured to perform a DMA transfer via the system bus according to a DMA transfer setting of said at least one channel; a CPU coupled to the system bus; and a Direct Memory Access Controller (DMAC) control unit coupled to the DMA controller, wherein the DMAC control unit includes: a plurality of virtual channels configured to have respective DMA transfer settings made thereto; a virtual channel arbiter configured to select one of the plurality of virtual channels; and a DMA setting circuit configured to read a first DMA transfer setting of the selected virtual channel to write the first DMA transfer setting to said at least one extension channel of the DMA controller, wherein each of said at least one CPU channel and said at least one extension channel includes: a DMA control circuit configured to serve as a bus master of the system bus; and a channel register, wherein the plurality of virtual channels of the DMAC control unit includes respective virtual channel registers, wherein the first DMA transfer setting is first stored in a virtual channel register of the selected virtual channel via the system bus, and is next set for actual channel configuration from the virtual channel register of the selected virtual channel to the channel register of said at least one extension channel, followed by being utilized to perform a DMA transfer, wherein a second DMA transfer setting is first set for actual channel configuration to the channel register of said at least one CPU channel via the system bus, and is next utilized to perform a DMA transfer, and wherein paths for making DMA transfer settings include a first path and a second path, the first DMA transfer setting being made to said at least one extension channel via the first path, the second DMA transfer setting being made to said at least one CPU channel via the second path, the first path including the system bus and the virtual channel registers, the second path including the system bus, the first path and the second path being different from each other and overlapping each other only on the system bus.