Patent ID: 8031620

Claim:
A method for real time simultaneous monitoring of a logical circuit, the method comprising: requesting first status information for a first logical connection at a host end of a logical circuit, the first logical connection being between the host end and an input to a network; requesting second status information for a second logical connection at a terminal end of the logical circuit, the second logical connection being between the terminal end and an output of the network; identifying a status of a third logical connection between the input of the network and the output of the network, the logical circuit including the first logical connection, the second logical connection, and the third logical connection; identifying a logical identifier that identifies the logical circuit at the first logical connection, at the second logical connection, and at the third logical connection based on the first status information and the second status information, the logical identifier being the same at the first logical connection, the second logical connection, and the third logical connection; and displaying whether the logical circuit has failed based on the first and second status information and based on the status of the third logical connection between the input of the network and the output of the network.