Patent ID: 7228370

Claim:
A data output device of a semiconductor device, comprising: a first comparator for comparing first output data with arbitrary output data latched at a previous data processing step on a bit-by-bit basis and outputting a first pre-flag signal which is enabled or disabled according to the number of bits of the first output data having made level transitions; a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second pre-flag signal which is enabled or disabled according to the number of bits of the second output data having made level transitions; a first logic unit for performing a logic operation with respect to the first pre-flag signal and an arbitrary data inversion flag signal latched at the previous data processing step and outputting a first data inversion flag signal; a second logic unit for performing a logic operation with respect to the second pre-flag signal and the first data inversion flag signal and outputting a second data inversion flag signal; a first output unit for inverting or non-inverting and outputting a plurality of bits contained in the first output data in response to the first data inversion flag signal; a second output unit for inverting or non-inverting and outputting a plurality of bits contained in the second output data in response to the second data inversion flag signal; and an output data initializer for, when a no-operation period is generated in a series of data output operations, initializing the arbitrary output data and supplying the resulting data to the first comparator.