Patent ID: 8228282

Claim:
A gate driving circuit in which plural stages are connected one after another to each other to sequentially output a gate signal, each of the stages comprising: a pull-up transistor which pulls up a present gate signal output through an output terminal to a gate-on voltage, a control electrode of the pull-up transistor connected to a Q-node; a buffer transistor which receives a previous output signal from a previous stage to turn on the pull-up transistor, an output electrode of the buffer transistor connected to the Q-node; a discharge transistor which receives a next output signal from a next stage to turn off the pull-up transistor, an input electrode of the discharge transistor connected to the Q-node; and a pull-down transistor which receives the next output signal from the next stage to pull down the present gate signal to a gate-off voltage, the pull-down transistor connected to the output terminal, and wherein a ratio of W/L of the buffer transistor to a capacitance connected to the Q-node is about two times or greater than a ratio of W/L of the pull-up transistor to a capacitance connected to an output electrode of the pull-up transistor.