Patent ID: 7093153

Claim:
A data processing system comprising: a system bus; a plurality of devices coupled to said system bus including at least one bus master which is capable of performing accesses on said system bus, said at least one bus master comprising a central processing unit (CPU) core capable of executing a plurality of instructions including a wait instruction that places said CPU core into a wait mode; a bus monitor circuit coupled to said at least one bus master, having an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on said system bus; and a clock generator having an output coupled to at least one of said plurality of devices for providing a bus clock signal having a first frequency when said bus idle signal is inactive, said clock generator identifying a condition to lower a frequency of said bus clock signal, and switching said bus clock signal from said first frequency to a second frequency lower than said first frequency, responsive to both said bus idle signal being active, and said CPU core being in said wait mode.