Patent ID: 7764564

Claim:
A semiconductor device comprising: a memory chip including a plurality of banks; a logic chip which transmits a write command and write data to the memory chip, and transmits a read command to the memory chip and receives read data from the memory chip; and data buses, provided corresponding to the banks, for transmitting and receiving the write data and the read data between the banks and the logic chip, wherein the logic chip includes: a writing data bus for transmitting the write data to the memory chip via one of the data buses; a reading data bus for receiving the read data from the memory chip via one of the data buses; and a switch for, corresponding to a write command or a read command issued to one of the banks, connecting the writing data bus or the reading data bus to a data bus connected to the bank, wherein a plurality of memory chips are stacked, and banks in different memory chips share a data bus, wherein the logic chip makes a writing latency from a time of issuing the write command to one of the banks up to a time of transmitting the write data to the data bus and a reading latency from a time of issuing the read command up to a time that the bank transmits the read data to the data bus equal, to thereby issue the read command and the write command in continuing clock cycles.