Patent ID: 7406590

Claim:
A method for processing variable width instructions in a pipelined processor, comprising: decoding instructions to identify a loop setup instruction having a loop setup instruction address to determine a loop top offset indicative of a loop top instruction address of a loop top instruction and a loop bottom offset indicative of a loop bottom instruction address of a loop bottom instruction; decoding variable width instructions following the loop setup instruction to detect the loop bottom instruction, a width of each of the variable width instructions being determined during decoding; decoding a current instruction of the variable width instructions, the current instruction having a current instruction address and a current instruction width; fetching a next instruction of the variable width instructions; determining if the next instruction to be decoded is the loop bottom instruction based, at least in part, on the current instruction address, the current instruction width, the loop setup instruction address and the loop bottom offset, the determination being made prior to decoding the next instruction; and providing the loop top instruction address to an instruction fetch stage of the pipelined processor if it is determined that the next instruction is the loop bottom instruction.