Patent ID: 7785973

Claim:
A process of forming an electronic device comprising: forming a semiconductor layer over a substrate having a primary surface, wherein the semiconductor layer has a first conductivity type; selectively doping a region of the semiconductor layer to form a first doped region having a second conductivity type opposite that of the first conductivity type; and patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region; wherein: selectively doping the region of the semiconductor layer comprises selectively doping another region of the semiconductor layer to form a second doped region having the second conductivity type; and patterning the semiconductor layer to form the gate electrode is performed such that the gate electrode further includes a third portion, wherein the third portion includes a portion of the second doped region, and the second portion of the gate electrode is disposed between the first and third portions of the gate electrode; forming a first patterned mask layer over the semiconductor layer before selectively doping the semiconductor layer; and wherein selectively doping the semiconductor layer comprises ion implanting the semiconductor layer, wherein ions during ion implanting are directed towards the semiconductor layer at an angle greater than 8° from a direction perpendicular to the primary surface.