Patent ID: 8431460

Claim:
A method for fabricating a semiconductor, wherein the method comprising: providing a silicon substrate; forming a gate structure on a surface of the silicon substrate; forming a first silicon nitride layer over the gate structure and the substrate; and removing a portion of the first silicon nitride layer and a portion of the silicon substrate to form a first recess but keeping a remaining portion of the first silicon nitride layer on the gate structure; forming and a patterned second silicon nitride layer to blanket over the remaining portion of the first silicon nitride layer and a portion of sidewalls of the first recess adjacent to the gate structure; using the patterned second silicon nitride layer as a mask to remove a portion of the silicon substrate exposed from the first recess to form a second recess substrate; and filling a heteroatom-containing epitaxial material into the first recess and the second recess to form a heteroatom-containing epitaxial structure.