Patent ID: 8683292

Claim:
A method comprising: encoding, by a processor of a first device, one or more blocks of information bits of a first source bit stream based on a predetermined structured parity check matrix of an LDPC code to generate a first LDPC encoded bit stream, wherein the parity check matrix is represented by stored information configured in a tabular format of rows and columns, wherein each row represents occurrences of one values within a respective column of the parity check matrix; scrambling the first LDPC encoded bit stream according to a scrambling signature based on a first initial vector, wherein the scrambling of the first LDPC encoded bit stream is configured for distinguishing the first LDPC encoded bit stream of the first device from a second scrambled bit stream of a second device to facilitate a multiple access scheme; wherein the LDPC encoding of the blocks of information bits (each block being of a size of k ldpc information bits, and each resulting encoded block being of a size of n ldpc code bits including parity bits p i , i=0, 1, 2, . . . , n ldpc −k ldpc −1), comprises: initializing parity bit accumulators a 0 =a 1 = . . . =a n ldpc −k ldpc −1 =0; for a one of the blocks of information bits, divided into j sequential groups (each of a size of M information bits), and for j=1, 2, 3, . . . k ldpc /M: (1) accumulating a first information bit of a j th group in certain of the parity bit accumulators reflected by accumulator addresses based on a j th row of the stored tabular information; and (2) accumulating the remaining (M−1) information bits of the j th group in certain of the parity bit accumulators reflected by accumulator addresses according to {x+m mod M*q} mod (n ldpc −k ldpc ), wherein x denotes an address of the parity bit accumulator corresponding to the first bit of the group, and q=(n ldpc −k ldpc )/M; and after all of the information bits of the one block are accumulated, sequentially performing operations (with respect to the parity bit accumulators) according to a i =a i ⊕a i−1 , i=1, 2, . . . (n ldpc −k ldpc −1), where the additions are in Galois Field (GF) 2; and wherein the parity bits p i , i=0, 1, . . . (n ldpc −k ldpc −1) are respectively reflected by the resulting parity bit accumulators a i , i=0, 1, . . . (n ldpc −k ldpc −1).