Patent ID: 7177203

Claim:
A data readout circuit which is configured to read memory data from a resistance change memory disposed at a point where a bit line and a word line intersect by setting a potential of the bit line to a predetermined bias potential and detecting a current value flowing in the resistance change memory, the data readout circuit comprising: a capacitance device connected to the bit line via a switching device; and a current supply circuit connected to both ends of the switching device to provide a current to the bit line such that the potential of the bit line is equal to a potential of the capacitance device, wherein, after a predetermined amount of electric charge is accumulated in the capacitance device while the switching device is in a disconnected state, the switching device is placed in a connected state and the electric charge accumulated in the capacitance device is distributed between a capacitance of the capacitance device and a capacitance of the bit line so as to set the potential of the capacitance device to the bias potential, and after the switching device is made to a disconnected state and the potential of the bit line is increased to a predetermined potential in advance, memory data is read from the resistance change memory by increasing the potential of the bit line to the bias potential using the current supply circuit.