Patent ID: 7352219

Claim:
A duty cycle corrector comprising: a restore circuit configured to receive a differential input clock and a differential feedback clock each having crossings of a first type and a second type and to provide a differential output clock having crossing of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential feedback clock crossings of the first type; a delay element configured to delay the differential output clock by a delay time to provide the differential feedback clock; and an adjuster circuit configured to receive the differential input and differential feedback clocks and to adjust the delay time so as to maintain a duty cycle of the differential output clock substantially at a desired duty cycle; and wherein the restore circuit comprises: a first operational amplifier receiving the differential input clock and providing a first output having a first state in response to differential input clock crossings of the first type and having a second state in response to differential input clock crossings of the second type; a second operational amplifier receiving the differential feedback clock and providing a second output having the first state in response to differential feedback crossings of the second type and having the second state in response to differential feedback crossings of the first type; and a signal generator providing the differential output clock based on the states of the first and second outputs.