Patent ID: 8742594

Claim:
An integrated circuit (IC) die, comprising: a metal crackstop comprising a plurality of alternating patterned metal layers and metal via bars extending continuously from a topmost silicon (Si) layer through a plurality of dielectric layers to a topmost patterned metal layer, which is co-planar with a topmost dielectric layer in a peripheral crackstop region of said IC die; a passivation layer on said topmost patterned metal layer of said metal crackstop and portions of said topmost dielectric layer in said peripheral crackstop region and in a central active device region of said IC die; an offset-trench crackstop comprising an air gap that extends through said passivation layer to a top surface of said topmost dielectric layer of said peripheral crackstop region, said air gap exposing a portion of said topmost dielectric layer in said peripheral crackstop region, not exposing any of said topmost patterned metal layer of said metal crackstop, and being interposed between said metal crackstop of said crackstop region and said central active device region of said IC die; and a via hole, formed in said passivation layer of said central active device region, that exposes a bonding pad on a portion of said topmost patterned metal layer in said central active device region.