Patent ID: 7781814

Claim:
A semiconductor integrated circuit device comprising: a logic circuit including a first MOS transistor, which is a first conductivity type, supplied with an operating voltage through first and second power lines; a second MOS transistor, which is the first conductivity type, having a source/drain path between the first and second power lines, a thickness of a gate insulation film of the second MOS transistor being larger than a thickness of a gate insulation film of the first MOS transistor; a hold circuit coupled between the first and second power lines and holding an output information from the logic circuit; and a third MOS transistor coupled between an output of the logic circuit and the hold circuit, a thickness of a gate insulation film of the third MOS transistor being larger than the thickness of the gate insulation film of the first MOS transistor, wherein a source of the first MOS transistor is coupled to the second power line through the source/drain path of the second MOS transistor, wherein the third MOS transistor is in an OFF state when the second MOS transistor is in an OFF state, and wherein the hold circuit is supplied with the operating voltage even though the second and third MOS transistors are in the OFF state.