Patent ID: 8411016

Claim:
A display device, comprising: (1) display elements two-dimensionally disposed in a matrix; (2) M scanning lines, initialization control lines, and display control lines extending in a first direction, where M is an integer corresponding to the number of rows or columns of display elements; (3) data lines extending in a second direction different from the first direction; and (4) a scanning drive circuit; the scanning drive circuit including: (A) a shift register portion including P shift registers SR i , the shift register portion being configured to successively shift a start pulse inputted thereto, and to thereby output a plurality of register output signals ST i from the shift registers SR i , respectively, where P is an integer greater than 2 and i=1, 2, . . . , P, and (B) a logical circuit portion including a plurality of logical circuits L (i,j) , the logical circuit portion being configured to operate based on the register output signals ST i outputted from the shift register portion, and Q kinds of enable signals, where Q is an integer greater than or equal to 2, and j=1, 2, . . . , Q, wherein: each of the logical circuits L (i,j) corresponds to one of the shift registers SR i , each of the logical circuits L (i=n,j) outputs a signal SCL k , where k=1, 2, . . . , M, based on inputs comprising: (a) a register input signal ST i=n that is output by the shift register SR i=n that corresponds to the logical circuits L (i=n,j) and that is received as an input by the shift register SR i=n+1 that corresponds to the respective logical circuit L (i=n+1,j) , (b) the register output signal ST i=n+1 that is output from the shift register SR i=n+1 that corresponds to the respective logical circuit L (i=n+1,j) , and (c) at least one enable signal, a scan signal is supplied to a given display element through an m-th scanning line, the scan signal corresponding to the signal SCL k=m output by one of the logic circuits L (i,j) , where m=1, 2, . . . , M, a control signal C m is supplied to the given display element through an m-th display control line, the control signal C m corresponding to a register output signal ST i that is also input into one of the logic circuits L (i,j) , and a scan signal corresponding to the signal SCL k=m−1 output from one of the logic circuits L (i,j) and supplied to the (m−1)-th scanning line is also supplied as an initialization signal AZ m to the given display element through an m-th initialization control line.