Patent ID: 8502302

Claim:
A semiconductor device, comprising: a) a plurality of trenches on a substrate including one or more active gate trenches located in an active area and one or more gate runner/termination trenches and shield electrode pickup trenches located in a termination area outside the active area containing the active gate trenches, the gate runner/termination trenches including one or more trenches that define a mesa located in the termination area outside the active area containing the active gate trenches, wherein the one or more trenches that define the mesa have asymmetrical sidewall thicknesses; b) a first conductive region formed in the plurality of trenches; c) an intermediate dielectric region and a termination protection region formed in at least a portion of the one or more trenches that define the mesa; d) a second conductive region formed in at least a portion of the one or more trenches that define the mesa, wherein the second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region; and e) a first electrical contact to the second conductive regions, a second electrical contact to the first conductive region in the shield electrode pickup trenches located in the termination area, and one or more Schottky diodes formed within the mesa.