Patent ID: 8129267

Claim:
A structure, comprising: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to said substrate to a uppermost interlevel dielectric layer furthest from said substrate, each interlevel dielectric layer of said set of interlevel dielectric layers including electrically conductive wires, top surfaces of said wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive terminal pad contacting a wire pad of said uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of said terminal pad; an organic sealing layer between said plating base layer and said uppermost interlevel dielectric layer, said terminal pad exposed in an opening in said organic sealing layer; said plating base layer overlapping all edges of said organic sealing layer proximate to said terminal pad; and a copper block on said plating base layer.