Patent ID: 8054930

Claim:
A circuit for clock recovery from a specified datastream, the circuit comprising: a reference extraction unit for extracting from the specified datastream time references defining a reference time base; and a digital Phase Locked Loop coupled to the reference extraction unit, the digital Phase Locked Loop including: a first programmable counter operating as a digitally controlled oscillator for generating an output time base; a second programmable counter operating as a loop divider for generating a loop time base; and a dedicated processor capable of executing a program, the program comprising: a first software module for operating as a phase comparator and comparing values of the loop time base and the reference time base and generating a loop error; and a second software module for operating as a loop filter and producing an adapted increment value for the first programmable counter from the loop error, the adapted increment value being coupled to an increment value input of the first programmable counter, wherein the first software module performs, each time one of the time references is extracted from the specified datastream, a partial calculation of the type: k n × P Q ⁡ [ P ] where P and Q are relatively prime integers, k n =k n +1 with k 0 =1, and the result is taken modulo P.