Patent ID: 8924619

Claim:
A system comprising: a plurality of processors, each of the plurality of processors comprising a plurality of respective communication first-in first-out buffers (FIFOs), said plurality of respective communication FIFOs comprising one or more respective hardware unit input FIFOs, one or more respective hardware unit output FIFOs, and a plurality of respective processor output FIFOs, wherein (i) each of the processors has an instruction set including at least one message sending instruction which, when executed, sends a message via at least one of the plurality of respective communication FIFOs and (ii) each of the processors is enabled to send messages to others of the processors via the respective processor output FIFOs; a message fabric coupling the processors via at least some of the plurality of respective communication FIFOs; and a plurality of hardware units, each of the processors associated with a respective one or more of the hardware units and coupled to each of the associated hardware units via one of the respective hardware unit input FIFOs and via one of the respective hardware unit output FIFOs, wherein the respective hardware units associated with each of the processors are enabled to send messages to the associated processor via the respective hardware unit input FIFOs.