Patent ID: 7484135

Claim:
A semiconductor device having an access time validity test mode, comprising: a circuit block to which an input signal is input at a timing in accordance with an input clock, and which outputs an output signal having a value corresponding to said input signal; a first signal path for guiding a test input signal, which has been supplied to a first pad, to a signal input terminal of said circuit block; a second signal path for guiding a test clock, which has been supplied to a second pad, to a clock input terminal of said circuit block; a third signal path for guiding a test output signal, which has been output from a signal output terminal of said circuit block, to a third pad via a dummy latch; and a fourth signal path for guiding the test output signal, which has been output from the signal output terminal of said circuit block, to a fourth pad, wherein the dummy latch is constituted so as to latch the test output signal at substantially a same operating speed as an operational latch for latching an output signal of said circuit block during a normal operation, and wherein said third signal path is formed so that a wiring delay time from the signal output terminal of said circuit block to the dummy latch is substantially equal to a wiring delay time from the signal output terminal of said circuit block to the operational latch.