Patent ID: 7088281

Claim:
A circuit for analog-to-digital conversion, comprising: a fine channel circuit that includes folding stages; a coarse channel circuit; and a coarse channel calibration circuit that is coupled to the coarse channel circuit, wherein the coarse channel calibration circuit includes: a counter circuit that is coupled to the coarse channel circuit; and a parameter adjustment circuit that is coupled to the counter circuit and the coarse channel circuit, wherein the coarse channel circuit is configured to provide a feedback signal, the counter circuit is configured to: receive the feedback signal, and provide a count signal in response to the feedback signal, and wherein the parameter adjustment circuit is configured to: receive the count signal, and adjust a parameter of the coarse channel circuit in response to the count signal, and wherein the counter circuit is configured to, if latched: increment a count value that is associated with the count signal if the comparator output corresponds to a first logic level, and decrement the count value if the comparator output corresponds to a second logic level.