Patent ID: 7198992

Claim:
A method of manufacturing a semiconductor device comprising the steps of: forming a first semiconductor island and a second semiconductor island over a substrate; forming a gate insulating film on the first semiconductor island and the second semiconductor island; forming first and second gate electrodes over the first semiconductor island and a third gate electrode over the second semiconductor island each comprising a first conductive layer and a second conductive layer, wherein ends of the second conductive layer are tapered; doping first impurity elements to the first semiconductor island and the second semiconductor island using the first and second gate electrodes and the third gate electrode as masks in a self-alignment manner; forming a first resist mask so as to cover the first gate electrode and a portion of the first semiconductor island doped with the first impurity elements, and a second resist mask so as to cover the second gate electrode and another portion of the first semiconductor island doped with the first impurity elements; and doping second impurity elements to the first semiconductor island doped with the first impurity elements and the second semiconductor island doped with the first impurity elements using the first and second resist masks and the third gate electrode as masks, wherein the second semiconductor island is doped in a self-alignment manner.