Patent ID: 8713084

Claim:
A method of verifying a result of a floating point division operation, the method comprising: performing, by a division circuit, a floating point division operation for a dividend and a divisor to produce a final result of the floating point division operation, the final result including a quotient; providing the final result from the division circuit to a processor; after receiving the final result from the division circuit, calculating, by the processor, a remainder from the quotient produced by the floating point division operation; performing, by the processor, a comparison of a magnitude of a least significant bit (LSB) of the dividend and a magnitude of a most significant bit (MSB) of the remainder calculated based on the final result, the comparison including determining whether the magnitude of the MSB of the remainder is less than or equal to twice the magnitude of the LSB of the dividend; and determining whether the final result is correct based on the comparison.