Patent ID: 8595726

Claim:
A parallel processing apparatus comprising: a memory; a control unit that determines whether one or more threads can access one or more control blocks of a first container that exists in a direction in which at least one of the one or more threads perform a task; a container generating unit that generates a second container that comprises one or more control blocks based on a result of the determination; and a container management unit that connects the one or more control blocks of the first container or the one or more control blocks of the first container and the one or more control block of the second container and control blocks in which the one or more threads perform tasks, in a ring shape, wherein each of the first and the second containers has a pointer that indicates a next container connected to the each of the first and the second containers, and a reuse count, the reuse count being a number of threads that have completed tasks in all of the one or more control blocks of the each of the first and the second containers, and wherein the pointer and the reuse count are parameters.