Patent ID: 8492263

Claim:
A method for manufacturing a semiconductor device comprising: forming one or more re-distribution layers (RDLs) on a first surface of a semiconductor wafer, wherein the one or more RDLs do not extend beyond the first surface of the semiconductor wafer; forming one or more electrode posts on respective ones of the RDLs, wherein each of said one or more electrode posts comprises an array of two or more columns, said one or more electrode posts electrically connected to a wiring layer of said semiconductor substrate; depositing a buffer layer over said first surface, said buffer layer encapsulating said array and being in physical contact with a conductive portion of at least one of said RDLs; removing portions of said buffer layer, the removing portions of said buffer layer resulting in a top surface of said one or more electrode posts being at a depth below a top of remaining portions of said buffer layer; depositing a conductive capping layer over said top surface and into the opening, wherein said conductive capping layer is below said top of said remaining portions of said buffer layer; and placing a solder ball onto each of said conductive capping layers, wherein a solder joint between said solder ball and said conductive capping layer resides below said top of said remaining portions of said buffer layer, and wherein the solder ball remains outside of a region between the columns of the one or more electrode posts.