Patent ID: 7006159

Claim:
A circuit arrangement, comprising: at least one adapter circuit ( 10 ), which amplifies an analog input signal of a low current (Ii) by an amplification factor (n) into an analog output signal of a higher current (Io), the at least one adapter circuit further comprising: an input ( 12 ), which corresponds to a range of low voltages (Ui); an output ( 18 ), which corresponds to a range of higher voltages (Uo); at least one npn transistor current mirror ( 14 ); and at least one pnp transistor current mirror ( 16 ) arranged in series with the npn transistor current mirror ( 14 ), and connected to at least one high voltage source ( 30 ), wherein the at least one pnp transistor current mirror comprises a plurality of pnp transistors connected in parallel on its output side and amplifies the input signal, which is received from the at least one npn transistor current mirror.