Patent ID: 8065130

Claim:
A design tool for designing a message processing system for implementation using an integrated circuit, comprising: an input section for inputting a specification of processing operations and memory attributes of said message processing system; an application programming interface (API) database coupled to the input section, the API database including a first set of primitives executable to define memory components, a second set of primitives executable to define threads of a processing component, and a third set of primitives executable to define a function block; a first database for storing a message processing architecture having a memory component and a processing component; a second database for storing an integrated circuit architecture; and a computer configured with program code that implements a message processing section, comprising: a first portion for generating an instance of said memory component and an instance of said processing component to produce a logical view of said message processing system; wherein the first portion, responsive to execution of primitives of the first set specified in the specification, generates the instance of the memory component; wherein the first portion, responsive to execution of primitives of the second set specified in the specification, generates a plurality of threads of the processing component; wherein each thread includes start, stop, suspend, and clock input terminals for controlling operation thereof, is-finished and is-suspended output terminals, and start control, stop control, and suspend control output buses; wherein at least one of the is-finished and is-suspended output terminals and start control, stop control, and suspend control output buses is coupled to one or more of the input terminals of one or more others of the plurality of threads; the is-finished and is-suspended output terminals for conveying status information related to each thread; the start control, stop control, and suspend control output buses for controlling operation of the one or more others of the plurality of threads; wherein the first portion, responsive to execution of primitive of the third set specified in the specification, generates an instance of a function block; and a second portion for implementing said memory component instance and said processing component instance in terms of said integrated circuit architecture to produce a physical view of said message processing system.