Patent ID: 8239802

Claim:
A computer implemented method for semiconductor device mask manufacturing, the method comprising: providing a mask manufacturing unit comprising a CAD unit configured to design mask patterns based on design data and to generate lithography data for a mask set used to produce a semiconductor device; providing a) design information on interconnected components of said semiconductor device in a netlist and b) design information on bump cells that includes information on inserting dummy vias within at least some of said bump cells, to said CAD unit; after said providing, directing said CAD unit to perform floorplanning, placement and routing of said interconnected components, and placement and routing of said bump cells based on said design information on bump cells; and said CAD unit executing at least said floorplanning; said placement and routing of said bump cells including insertion of said dummy vias; and said placement and routing of said interconnected components of said device, wherein at least said placement of said bump cells and said insertion of said dummy vias, is executed prior to said routing of said interconnected components of said device, and said dummy vias are disposed underneath UBM (under bump metallization) of at least one of said bump cells.