Patent ID: 8207599

Claim:
A semiconductor device package comprising: at least one semiconductor die, comprising: an upper major surface; a lower major surface opposite the upper major surface; and at least one lateral side extending between the upper major surface and the lower major surface, wherein the at least one semiconductor die lies in a major plane at least generally parallel to at least one of the upper major surface and the lower major surface; a lead frame associated with the at least one semiconductor die, comprising: a plurality of lead fingers; and at least one member proximate the at least one semiconductor die having a portion thereof configured in a substantially non-parallel orientation relative to the major plane of the at least one semiconductor die for impeding flow of molten dielectric packaging material around the at least one lateral side of the at least one semiconductor die in a molding process; and a molded dielectric packaging material at least partially encapsulating the lead frame, including the portion of the at least one member, and at least partially encapsulating the at least one semiconductor die.