Patent ID: 8741710

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a gate oxide layer on a substrate and a gate electrode on the gate oxide layer, and forming a first spacer on opposite side walls of the gate electrode and a second spacer on each first spacer, and a low-concentration source/drain region arranged with the first spacer and a high-concentration source/drain region arranged with the second spacer; forming a silicide layer on the gate electrode and the high-concentration source/drain region; performing a preliminary plasma process on an interface between the gate oxide layer and the substrate after forming the silicide layer; forming an etch stop layer on a surface of the substrate; performing a plasma process on the interface between the gate oxide layer and the substrate after forming the etch stop layer; forming an interlayer dielectric layer on the etch stop layer; forming a contact hole which penetrates through the etch stop layer and the interlayer dielectric layer; performing a subsequent plasma process on the interface between the gate oxide layer and the substrate after forming the interlayer dielectric layer; and forming a bottom metal line on the interlayer dielectric layer, wherein the preliminary plasma process, the plasma process, and the subsequent plasma process are performed using a non-silane treatment gas including deuterium, and wherein the subsequent plasma process causes deuterium from a non-silane treatment gas in the contact hole to diffuse therefrom into the interface between the substrate and the gate oxide layer.