Patent ID: 7986572

Claim:
A method of writing magnetic random access memory elements requiring high: programming currents, comprising: providing a plurality of memory cells arranged in an array of m rows and n columns, wherein each memory cell has a magnetic memory element, each said magnetic memory element having a first terminal and a second terminal, and a cell transistor, each said cell transistor having a first source/drain terminal connected to said second terminal of said magnetic memory element, a gate, and a second source/drain terminal, and wherein said memory cell stores a 1 by causing a first current to flow from said cell transistor into said magnetic memory element and stores a 0 by causing a second current to flow from said magnetic memory element into said cell transistor; providing a BLT line and a BLC line for each column of said array; providing a word line for each row of said array; connecting said first terminal of said magnetic memory elements in those said magnetic memory cells in each of said n columns to one of said BLC lines; connecting said second source/drain terminal, of each of said cell transistors in those said magnetic memory cells in each of said n columns to one of said BLT lines; connecting said gate of each of said cell transistors in those said magnetic memory cells in each of said m rows to one of said word lines; selecting one of said rows of said array; and writing a 1 or a 0 in selected magnetic memory cells in said selected row of said array by applying a first voltage to said word line for that said row, a second voltage to those BLC lines and a third voltage to those BLT lines connected to those magnetic memory cells in which a 1 is to be written, a fourth voltage to those BLC lines and a fifth voltage to those BLT lines connected to those magnetic memory cells in which a 0 is to be written, and a sixth voltage to the remaining word lines in said array wherein said sixth voltage is less than said first voltage.