Patent ID: 8283933

Claim:
An integrated circuit configured for built in self-test (BiST) jitter measurement, comprising: a time-to-voltage converter, wherein the time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input for the built in self-test jitter measurement; feedback circuitry for the time-to-voltage converter, wherein the feedback circuitry provides a ramp slope for the time-to-voltage converter, and wherein the feedback circuitry adjusts a gate bias for a transistor in the time to voltage converter to provide a linearly increasing voltage ramp; a calibration controller, wherein the calibration controller provides control signals to the time-to-voltage converter for process-independent calibration as part of the built in self-test jitter measurement; and a sample-and-hold (S/H) circuit, wherein the S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.