Patent ID: 8493129

Claim:
A power-factor correction circuit, comprising: a first switching device comprising a first channel; an inductive load; a capacitor; and a second switching device comprising a second channel; wherein the first switching device is connected to a node between the inductive load and a floating gate drive circuit, the second switching device is configured to be connected to the floating gate drive circuit, and the second switching device is between the inductive load and the capacitor; and the power-factor correction circuit is configured such that in a first mode of operation the second switching device blocks a voltage applied across the second switching device in a first direction, in a second mode of operation a substantial current flows through the second channel when a voltage is applied across the second switching device in a second direction and a gate of the second switching device is biased below a threshold voltage of the second switching device, and in a third mode of operation a substantial current flows through the second channel when a voltage is applied across the second switching device in the second direction and the gate of the second switching device is biased above the threshold voltage of the second switching device.