Patent ID: 7482288

Claim:
A method for producing a semiconductor product, forming semiconductor product components in a semiconductor product region of a substrate; forming a layer made of low-k material subsequently on the substrate; forming electrically conductive interconnects in or on the layer made of low-k material for the purpose of electrically connecting the semiconductor product components, the layer being provided in a wiring plane of the semiconductor product for the electrical insulation of the interconnects from one another; subjecting the layer made of low-k material to a spatially delimited treatment, within a grid cap region of the substrate, situated outside the semiconductor product region, and further within at least one crossover region of the interconnect, such that a dielectric constant value of the layer is increased in the crossover region, whereby an interconnect-to-interconnect capacitance is formed as a grid cap capacitance from the interconnects arranged in the crossover region; wherein the dielectric constant of the low-k material remains unchanged in the semiconductor product region.