Patent ID: 7274136

Claim:
A flat panel display arranged in a matrix of N rows and M columns comprising: a first surface containing an anode thereon, said anode comprising: a plurality of electrically conductive areas each associated with a row (N) and a column (M) defining a pixel location; a phosphor layer associated with each of said areas; a TFT circuit operable to apply a predetermined voltage to an associated one of the conductive areas, said TFT circuit, comprising: first and second electrically cascaded transistors; and a capacitor electrically connected between an output of said first transistor and an output of said second transistor, wherein the capacitor and output of the second transistor are electrically coupled to the associated conductive area; and a cold cathode, deposited on a second surface, facing said first surface, comprising: a conducting layer disposed on said second surface; and an emitter material disposed on said conducting layer operable to emit electrons when an associated threshold voltage is exceeded.