Patent ID: 7115459

Claim:
A method of fabricating a silicon germanium (SiGe) Bi-CMOS device having a heterojunction bipolar transistor and a CMOS (Complementary Metal Oxide Semiconductor) transistor, the method comprising the steps of: forming a sub-collector region in a substrate of a bipolar transistor region, and forming well regions in the substrate of a CMOS transistor region, respectively; growing silicon epitaxial layers on the substrate of the sub-collector region and the well regions; forming a collector and a collector plug in the silicon epitaxial layers of the bipolar transistor region, respectively, and implanting ions for controlling a threshold voltage into the silicon epitaxial layers of the CMOS transistor region; forming a gate oxide layer on the substrate of the CMOS transistor region, and forming a first epitaxial layer on the collector and the gate oxide layer; forming an emitter on the first epitaxial layer of the collector, and forming a gate on the gate oxide layer; implanting impurity ions into the first epitaxial layer at both sides of the gate to form a LDD (Lightly Doped Drain) region, and implanting impurity ions into the collector at both sides of the emitter to form an external base layer; forming spacers at both sidewalls of the emitter and the gate, respectively, and forming a second epitaxial layer on the first epitaxial layer, the emitter, the collector plug, the gate, and the LDD region; forming a source and a drain in the second epitaxial layer at both sides of the gate; and depositing and heat treating a nickel (Ni) layer on an entire surface of the resultant structure to form a nickel silicide layer on the second epitaxial layer, the emitter, the collector plug, the gate, and the source and drain, and removing the nickel (Ni) layer remaining without reaction.