Patent ID: 7154183

Claim:
A semiconductor device, having multilevel interconnection comprising: a subject level interconnect; a subject interlevel insulator disposed on the subject level interconnect; a connecting via-plug buried in the subject interlevel insulator, the bottom surface of the connecting via-plug is in contact with the subject level interconnect; a dummy via-plug buried in the subject interlevel insulator, the top surface of the dummy via-plug is electrically open; and an upper level interconnect of the subject level interconnect, disposed at the top surface of the subject interlevel insulator, being in contact with the top surface of the connecting via-plug, wherein, when viewed on an imaginary wiring grid implemented by a plurality of first lines and a plurality of second lines intersecting with the first lines: the subject level interconnect extends along one of the first lines; the upper level interconnect extends along one of the second lines; and the connecting and dummy via-plugs are arranged on intersecting points between the first lines and the second lines.