Patent ID: 7067875

Claim:
A semiconductor integrated circuit device comprising electrically writable nonvolatile memory elements each including, in a semiconductor region: a source region; a drain region; a channel formation region interposed between said source region and said drain region; and a control gate electrode, wherein two of said channel formation regions are disposed independently over respective opposing side surfaces of each of rectangular-parallelepiped semiconductor pillars, said drain region connected to said two channel formation regions is formed in an upper portion of said rectangular-parallelepiped semiconductor pillar, each of a plurality of insulator pillars is disposed between adjacent ones of said semiconductor pillars to form a row such that said channel forming regions are not faced toward side surfaces of said insulators pillars, a first insulating film is provided between each of said channel formation regions and said control gate electrode, a nonconductive charge trap film is provided over said first insulating film, and a second insulating film is provided over said nonconductive charge trap film.