Patent ID: 7760552

Claim:
A verify method of a semiconductor device including a NAND cell having a first and second nonvolatile memory elements connected in series, comprising: setting potential of a control gate of the first nonvolatile memory element to be a first potential and potential of a control gate of the second nonvolatile memory element to be a second potential, for erasing a data stored in the first nonvolatile memory element; and setting potential of a control gate of the first nonvolatile memory element to be a third potential and potential of a control gate of the second nonvolatile memory element to be the second potential, for reading a data stored in the first nonvolatile memory element after erasing a data stored in the first nonvolatile memory element, wherein each of the first and second nonvolatile memo elements has a semiconductor layer including a channel forming region and a floating gate, and wherein the floating gate is formed from a semiconductor material having a smaller energy gap than the semiconductor layer.