Patent ID: 8759806

Claim:
A semiconductor memory device comprising memory cells, each of the memory cells comprising a variable resistance element and a switching element connected in series, the variable resistance element comprising a variable resistance layer configured to change in resistance value thereof between a first-resistance state and a second-resistance state having a resistance value higher than that of the first-resistance state, and a buffer layer formed in contact with one end of the variable resistance layer, the variable resistance layer including a transition metal oxide, a ratio of transition metal and oxygen of the transition metal oxide varying between 1:1 and 1:2 along a first direction directed from a first region having said ratio of 1:2 to a second region having said ratio of 1:1, a concentration of the transition metal along the first direction and a concentration of the oxygen along the first direction decrease in said second region where the ratio of transition metal and oxygen of the transition metal oxide is 1:1, wherein the variable resistance layer includes silicon, a ratio of silicon to the transition metal oxide configuring the variable resistance layer monotonically increases along the first direction.