Patent ID: 7151712

Claim:
A row decoder with low gate induce drain leakage current (GIDL) suitable for a memory apparatus, comprising: a first PMOS transistor, in which a first source/drain is electrically coupled to a word line driving voltage, and a gate receives a selection signal; a first NMOS transistor, in which a first source/drain and a gate are electrically coupled to a second source/drain and the gate of the first PMOS transistor respectively, and a second source/drain is electrically coupled to a base of the first NMOS transistor and a first DC bias; a local voltage generator for generating a voltage signal; and a base control circuit electrically coupled to a base of the first PMOS transistor for selectively coupling the base of the first PMOS transistor to a second DC bias, a third DC bias, or floating according to the voltage signal, wherein the third DC bias is greater than the first DC bias and less than the second DC bias.