Patent ID: 7984275

Claim:
A computer implemented method for discovering topology information comprising nesting information of processors (CPUs) of a guest configuration in a logically partitioned computer system, the method comprising: fetching, by a processor of the guest configuration a STORE SYSTEM INFORMATION instruction for execution, the STORE SYSTEM INFORMATION instruction defined for a computer architecture; executing the STORE SYSTEM INFORMATION instruction, wherein the STORE SYSTEM INFORMATION instruction comprises an opcode field and a base register field, the base register field for identifying a location in memory of a system information block (SYSIB), the execution comprising: based on a topology information request of the STORE SYSTEM INFORMATION instruction, obtaining topology information of the guest configuration wherein the topology information is configured to include a length of the SYSIB, and nesting information, the nesting information comprising topology list entries (TLEs) for each nesting level (NL), each TLE comprising a nesting level (NL) indicator, wherein CPUs are specified by CPU TLEs having NL=‘0’ and a hierarchy of nesting structures are specified by container TLEs having NL>‘0’; and storing the topology information in the SYSIB at the location in memory.