Patent ID: 7802211

Claim:
A method for providing an alternative reference description for the use in verification of digital circuits by using a computer, wherein in the verification a digital circuit to be verified is compared with a reference description of the digital circuit, in order to recognize errors in the digital circuit using an equivalence test, wherein for at least one specific circuit structure described by a reference description of the digital circuit a plurality of different pre-defined implementation alternatives is known, the method comprising the computer implemented steps of: (a) determining, for each one of the at least one specific circuit structure first implementation alternative out of the plurality of the different pre-defined implementation alternatives, such that the first implementation alternative has the greatest degree of structural equivalence with the digital circuit to be verified compared to other implementation alternatives out of the plurality of the different pre-defined implementation alternatives and whereby each one of the plurality of the different pre-defined implementation alternatives is simulated respectively, using random pattern simulation, and compared with a corresponding simulation of the digital circuit, in order to determine the first implementation alternative having the highest degree of structural equivalence with the digital circuit, the implementation alternative out of the plurality of the different pre-defined implementation alternatives, which, under the random pattern simulation, has the largest number of equivalent design points with the digital circuit, (b) replacing in the reference description of the digital circuit, the description of the individual circuit structures by the first implementation alternative determined for the respective circuit structure in step (a) having the highest degree of structural equivalence in each case to obtain the alternative reference description, and (c) outputting the alternative reference description for use as a reference description in the verification of the digital circuit, wherein the at least one specific circuit structure, for which in step (a) the first implementation alternative with the highest degree of structural equivalence is determined in each case, are multiplier structures for realizing integral multiplication functions.