Patent ID: 7157949

Claim:
A delay locked loop capable of preventing false lock, the delay locked loop comprising: a false-lock detector including: a first phase detector electrically coupled to a first clock signal and a second clock signal for comparing phases of the first clock signal and the second clock signal to produce a phase difference signal; an average circuit electrically coupled to the first phase detector for generating an average signal corresponding to an average of the phase difference signal; and a comparator circuit electrically coupled to the average circuit for comparing the average signal with at least one reference signal to produce an upward adjustment signal or a downward adjustment signal; a delay line electrically coupled to an incoming clock signal and a control node for using at least one delay lag of the delay line to delay the incoming clock signal and produce at least one delay clock according to a control signal on the control node, and a charge pump electrically coupled to the false-lock detector and the control node for adjusting the control voltage on the control node according to the upward adjustment signal or the downward adjustment signal; at least one reference signal generator for generating the at least one reference signal according to a low level and a high level of the phase difference signal.