Patent ID: 7996592

Claim:
A system comprising: a plurality of memory resources; a plurality of peripheral resources; a plurality of processors; a memory controller coupled to said plurality of processors and said plurality of memory resources, wherein said memory controller comprises a first resource controller operable to control access by said plurality of processors to said plurality of memory resources using a hardware semaphore unit, wherein said first resource controller is further operable to implement respective buses for coupling said plurality of processors to said plurality of memory resources, wherein said memory controller is further operable to enable each processor of said plurality of processors to simultaneously access a respective portion of a memory resource of said plurality of memory resources, and wherein said memory controller is further operable to enable each of said plurality of processors to have priority access to a respective instruction memory of a plurality of instruction memories; and a peripheral controller coupled to said plurality of processors and said plurality of peripheral resources, wherein said peripheral controller comprises a second resource controller operable to control access by said plurality of processors to said plurality of peripheral resources using said hardware semaphore unit, and wherein said second resource controller is further operable to implement respective buses for coupling said plurality of processors to said plurality of peripheral resources.