Patent ID: 7640520

Claim:
A method for processing an integrated circuit, the method comprising: providing a first integrated circuit representation having a first circuit layout scale, wherein the first integrated circuit representation comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; generating a second integrated circuit representation having a second circuit layout scale smaller than the first circuit layout scale, wherein the step of generating the second integrated circuit representation comprises: shrinking the shrinkable circuit to the second circuit layout scale, wherein the step of shrinking the shrinkable circuit comprises: generating a first phantom from the shrinkable circuit; shrinking the first IP layout to generate a third IP layout having the second circuit layout scale; and merging the third IP layout with a final top layout under the second circuit layout scale; merging the second IP layout with the shrinkable circuit of the second circuit layout scale to generate a final integrated circuit representation wherein the step of merging the second IP layout comprises: generating a second phantom from the non-shrinkable circuit; blowing-up the second phantom to generate a third phantom; placing and routing the first and the third phantoms to generate a top-level layout; shrinking the top-level layout to the second circuit layout scale to generate a final top-level layout; and merging the second IP layout with the final top-level layout; and implementing the final integrated circuit representation on a chip.