Patent ID: 8363453

Claim:
A device, comprising: a memory array comprising a plurality of static random access memory (SRAM) cells arranged in rows and columns, a plurality of true bit lines each connected to a column of the memory array and a plurality of complement bit lines each forming a differential pair with, and in the same column as one of the plurality of true bit lines; and a write assist circuit connected to each of the differential pair of bit lines in each of the plurality of SRAM cells of the memory array, the write assist circuit comprising: a negative boost node; a discharge device coupled to ground and the negative boost node, the discharge device configured to receive a first control signal; a boost capacitor coupled to the negative boost node, the boost capacitor configured to receive a second control signal; a plurality of bit line control devices configured to control a write data line for writing a bit line in a write cycle, each of the plurality of bit line control devices comprising a transistor coupled to the negative boost node, wherein a gate-source terminal of each transistor of the plurality of bit line control devices is connected to the negative boost node; and a bit line control selection device coupled to the plurality of bit line control devices and the negative boost node, the bit line control selection device configured to select one of the plurality of bit line control devices during the write cycle, wherein all of a charge on the negative boost node is directed to only the selected one of the plurality of bit line control devices, wherein the gate-source terminals of each of the transistors of the unselected plurality of bit line control devices are shorted to receive negative voltage from the negative boost node, feeding the negative voltage to the gate, preventing the charge on the negative boost node from taking a path to the unselected plurality of bit line control devices and causing activation thereof.