Patent ID: 7951648

Claim:
A process comprising forming a first electrical interconnect structure on a surface of a semiconductor chip to produce an electrically connectable semiconductor structure; said electrically connectable semiconductor structure comprising at least one singulated semiconductor chip; said singulated chip including an alignment pattern; applying a curable underfill coating to said surface of said singulated semiconductor chip and b-staging said curable underfill coating to produce a coated semiconductor chip; scanning and storing said alignment pattern in a scanning device prior to or after application of or b-staging said curable underfill coating to thereby produce a scanned and stored alignment pattern; delivering said scanned and stored alignment pattern into an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with said first electrical interconnect structure; placing said coated semiconductor chip in said alignment and joining device; activating said scanned and stored alignment pattern in said alignment and joining device to position said coated semiconductor chip so that said first electrical interconnect structure is aligned to make electrical contact with said second electrical interconnect structure; activating said alignment and joining device to join said coated semiconductor chip to said substrate so that said first electrical interconnect structure is in electrical contact with said second electrical interconnect structure.