Patent ID: 7302657

Claim:
A method of modifying a design of a synchronous digital circuit comprising a plurality of clocked storage devices and a plurality of combinational logic elements defining combinational paths between at least some of the clocked storage devices, each combinational path from an output of a first one of the clocked storage devices to an input of a second one of the clocked storage devices having a minimum delay value and a maximum delay value, such that the actual delay of the path assumes a value between the minimum delay value and the maximum delay value, the method comprising the steps of: identifying among the combinational paths a combinational path having a greatest difference between the maximum delay value and the minimum delay value, and reducing the difference between the maximum delay value and the minimum delay value by increasing the minimum delay value for the combinational path having the greatest difference, wherein the greatest difference in case of parallel paths is calculated as a difference between the highest maximum delay value and the lowest minimum delay value of the parallel paths, the maximum delay value for a sequential path is calculated as a sum of the maximum delay values for the paths comprised in the sequential path, and the minimum delay value for a sequential path is calculated as a sum of the minimum delay values for the paths comprised in the sequential path.