Patent ID: 7250330

Claim:
A method of making an electronic package, said method comprising the steps of: providing a substrate having a first surface; providing said first surface with a layer of modified polyphenyline ether dielectric material; forming a plurality of apertures in said modified polyphenylene ether dielectric material; at least partially filling said apertures with a conductive material to form a pattern of conductive pads; positioning solder on selected ones of said pattern of conductive pads for attachment to a chip; heating to reflow said solder after positioning said solder to form a solder bump on said selected ones of said pattern of conductive pads; positioning a portion of solder flux material on each said solder bump to form a plurality of solder bumps with flux; providing a semiconductor chip having a first and second surface; thinning said semiconductor chip by mechanical grinding, chemical polishing, or chemical-mechanical polishing said first surface to a polished first surface that provides a chip thickness of less than 8 mils; forming a pattern of conductive elements on said second surface of said semiconductor chip substantially similar to said pattern of conductive pads on said first surface of said substrate; positioning on said substrate the said semiconductor chip so that said polished first surface that provides a chip having a thickness of less than 8 mils is facing upwardly and is exposed and so that selected ones of said conductive elements on said second surface of said chip are located on respective ones of said plurality of solder bumps with flux; heating said substrate with chip positioned thereon and said polished surface exposed a second time to reflow each of said solder bumps of said plurality of solder bumps with flux to provide an electrical couple between said semiconductor chip and said substrate; and positioning an encapsulant material on said electrical couple between said semiconductor chip and said substrate.