Patent ID: 8595661

Claim:
An integrated circuit, comprising: a substrate; a first block including a set of semiconductor fins in a first region of the substrate, the first block including outer fins on opposing outside edges of the first block, and inner fins between the outer fins, the first block being arranged for devices having channels with a first conductivity type; a second block including a set of semiconductor fins in a second region of the substrate, the second block including outer fins on opposing outside edges of the first block, and inner fins between the outer fins, the second block being arranged for devices having channels with a second conductivity type; a patterned gate conductor layer including a plurality of gate traces in the first and second blocks; at least one patterned conductor layer over the gate conductor layer; one or more power traces arranged overlying the set of semiconductor fins in each of the first and second blocks; and a plurality of inter-layer connectors that connect semiconductor fins, gate traces, traces in the at least one patterned conductor layer, and the one or more power traces.