Patent ID: 7343479

Claim:
A method for implementing two types of architectures on a chip, comprising: receiving instructions from a fetch engine, determining whether each instruction is a macroinstruction or a microinstruction, if the instruction is a macroinstruction, sending the macroinstruction to an emulation engine, decomposing the macroinstruction into one or more microinstructions, formatting, by a bundler, the microinstructions into bundles as preferred by the native microarchitecture, dispatching a bundle in parallel to an execution engine via a multiplexer, and dispatching additional information to the execution engine, wherein the additional information is contained in bits of the bundle otherwise not required for emulation of the macroinstruction, and if the instruction is microinstruction, dispatching the microinstruction to the execution engine via the multiplexer; selecting either the microinstruction from the fetch engine or the bundle from the emulation engine, by using the multiplexer; dispatching the selected microinstruction/bundle to the execution engine; and wherein the bundler receives at least one sequence of instructions (“XUOPs”), determines how many XUOPs are received, and when more than one XUOP is received, determines whether the XUOPs must be issued in parallel.