Patent ID: 8051391

Claim:
A method for forming an integrated circuit device, comprising: using a layout program running on a computer, generating a mask layout design of geometrical shapes that correspond to target features of a circuit design to be formed in or on a substrate; making a mask having mask features corresponding to the mask layout of geometric shapes directed by the layout program; and forming features of the integrated circuit device according to the mask features by imaging the mask features by directing a beam through the mask in a lithography process onto a semiconductor substrate that is at least partially covered with a resist; wherein generating the mask layout design includes: placing a first shape associated with a first target feature at a first location corresponding to a first intersection point of a grid having a plurality of grid units with grid side dimensions defined by a given targeted minimum pitch P min established for the target feature; determining a first pitch restriction area within which another feature may be placed only at a location corresponding to an intersection point of a first local area portion of the grid having N×N grid units less four corner units with N>1 and centered on the first intersection point; placing a second shape associated with a second target feature at a second location different from the first location, either at any location outside the first pitch restriction area or at any location within the pitch restriction area corresponding to a second intersection point within the first local area portion of the grid.