Patent ID: 7366007

Claim:
A semiconductor memory device having a plurality of memory cells disposed in grid form, a word line for activating each of the memory cells, and a pair of bit lines connected to each of the memory cells, the semiconductor memory device comprising: a write circuit comprising two N-type transistors respectively having sources connected to ground potential, wherein one of the N-type transistors has a drain connected to one of the pair of bit lines and the other of the N-type transistors has a drain connected to the other of the pair of bit lines; and a column selecting and data input circuit for generating a logical product of inverted data of data to be written and a write column selecting signal, inputting the logical product to a gate of the one of the N-type transistors, generating a logical product of the data to be written and the write column selecting signal, and inputting the logical product of the data to be written and the write column selecting signal to a gate of the other of the N-type transistors.