Patent ID: 8410554

Claim:
A structure, comprising: a high-leakage dielectric formed in a divot on each of sides of a segmented field effect transistor (FET) comprised of active silicon islands and gate electrodes thereon; a low-leakage dielectric on and in contact with a surface of the active silicon islands, adjacent the high-leakage dielectric, a top surface of the high-leakage dielectric being at a coplanar level as a top surface of the active silicon islands; and a gate electrode material between a portion of a shallow trench isolation material and the high-leakage dielectric; wherein: the high-leakage dielectric is a low-k dielectric; the low-leakage dielectric is a high-k dielectric material; the gate electrode material is formed directly in contact with the high-leakage dielectric; top surfaces of the gate electrode material and the shallow trench isolation material are formed at the coplanar level as the top surfaces of the high-leakage dielectric and the active silicon islands; and the low-leakage dielectric is formed directly in contact with the high-leakage dielectric; the high-leakage dielectric, the low-leakage dielectric, the gate electrode material, and the shallow trench isolation material are formed completely above a buried oxide (BOX) layer; the gate electrode material is formed directly in contact with the shallow trench isolation material; and the gate electrodes are formed directly in contact with the shallow trench isolation material.