Patent ID: 8050104

Claim:
A non-volatile memory device comprising: a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, and at least one bit line bias block connected to a plurality of bit lines and configured to precharge the plurality of bit lines, wherein each of the memory blocks comprises a plurality of cell strings each connected to a corresponding one of the plurality of bit lines, the at least one bit line bias block comprises a plurality of bias strings each connected to a corresponding one of the plurality of bit lines, and each one of the plurality of bias strings has the same structure as each one of the plurality of cell strings, and the plurality of bias strings is controlled to precharge the plurality of bit lines different from the plurality of cell strings; a page buffer configured to precharge the plurality of bit lines and sense data stored in at least one memory block via the plurality of bit lines; and a controller configured to control the at least one bit line bias block and the page buffer to simultaneously precharge the plurality of bit lines.