Patent ID: 7463502

Claim:
A method for reading and erasing a memory device, the memory device including a plurality of bit lines formed on a substrate and arranged substantially in a first plane and extending substantially in a first direction, a plurality of layers, each layer having an array of ferroelectric capacitor memory cells, each layer being substantially parallel to the first plane, a plurality of tree structures arranged into a plurality of rows, at least one tree structure corresponding to each bit line and having a trunk portion and at least one branch portion, each branch portion of a tree structure corresponding to at least one layer, the trunk portion of each tree structure extending from the corresponding bit line, each branch portion of a tree structure extending from the trunk portion of the tree structure, and each tree structure corresponding to a plurality of layers, and a plurality of plate line groups, each plate line group including a plurality of plate lines and corresponding to at least one layer, each respective plate line group overlapping branch portions of each tree structure in at least one row of tree structures at a plurality of intersection regions, a ferroelectric capacitor memory cell being located at each intersection region in a layer, the method comprising: allowing each tree structure in at least one row to electrically float near a first predetermined voltage; applying a second predetermined voltage V to a selected plate line; detecting a potential of each tree structure in the at least one row; determining whether each detected potential corresponds to a 0 or a 1 for each memory cell at the intersections of the selected plate line and the tree structures in the at least one row; applying the first predetermined voltage to every tree structure in the at least one row; and applying the first predetermined voltage to the selected plate line.