Patent ID: 6927463

Claim:
A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; one or more shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type formed in each of the one or more shallow well regions; corresponding to each shallow well region, a channel region, formed between the source region and the drain region of that shallow well region; a gate insulating film formed on the channel region of that shallow well region; and a gate electrode formed on the gate insulating film of that shallow well region, wherein each of the one or more shallow well regions is electrically separated from adjacent ones of the one or more adjacent shallow well regions by a groove type element separation structure, corresponding to each groove type element separation structure, an impurity diffusion region, having a same conductivity type as the deep well region, is provided on a bottom of that groove type element separation structure and reaches the deep well region, and for each shallow well region, a difference of a potential formed between that shallow well region and the source region for that shallow well region and a difference of a potential formed between that shallow well region and the drain region for that shallow well region is set so as to be smaller than a built-in potential of a pn junction formed between that shallow well region and the source region for that shallow well region and the built-in potential of a pn junction formed between that shallow well region and the drain region for that shallow well region, respectively, during operation.