Patent ID: 7088623

Claim:
A non-volatile memory cell structure, said non-volatile memory cell structure comprising: an N-type well region in a substrate, a channel region between a P-type source region and a P-type drain region, wherein the conductivity type of said P-type is opposite to the conductivity type of said N-type; a first insulator layer on the surface of said N-type well region; a floating gate overlying said first insulator layer; a second insulator layer on said floating gate; and a control gate on said second insulator layer, wherein said non-volatile memory cell is erased by applying an erase voltage to said P-type drain region, a supply voltage to said control gate, and said erase voltage to said N-type well region, wherein a bit line bias of said non-volatile memory cell is positive, and said supply voltage is applied to said control gate that is higher than a threshold voltage of said non-volatile memory cell to perform an erasing operation.