Patent ID: 6873707

Claim:
A method for accelerating the generation of control signals in a microcode controller system including a microcode controller, a microcode memory, a level-sensitive address latch and a level sensitive code word latch, the method comprising: opening the address latch during one of a high level and a low level of a clock cycle to store therein an address decoded by the microcode controller, while simultaneously closing the code word latch during the second half of a clock cycle; presenting the address stored in the address latch to the microcode memory to read out a code word therefrom; opening the code word latch during the respective other of the high level and the low level of a clock cycle to store the code word read out from the microcode memory to the code word latch, while simultaneously closing the address latch; and presenting the code word stored in the code word latch to the microcode controller for generation of output control signals and decoding at least one address.