Patent ID: 7386649

Claim:
A memory system, comprising: a plurality of memory requestors; a first rank of memory modules coupled to the memory requestors, each of the memory modules in the first rank being coupled to a plurality of the memory requestors, each of the memory modules comprising: a plurality of memory devices; and a memory hub comprising: a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices; a first plurality of link interfaces, each of the link interfaces being coupled to a respective one of the memory requestors; and a cross bar switch having a first plurality of switch ports, a second plurality of switch ports, and a plurality of memory ports, each of the switch ports being coupled to a respective one of the link interfaces, and each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the link interfaces to any one of the memory controllers; and a second plurality of link interfaces each of which is coupled to a respective one of the switch ports in the second plurality of switch ports; a second rank of memory modules each of which is coupled to a respective one of the second link interfaces in each of the memory modules in the first rank, each of the memory modules in the second rank comprising: a plurality of memory devices; and a memory hub comprising: a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices; a first plurality of link interfaces, each of the link interfaces being coupled to a respective one of the second link interfaces; and a cross bar switch having a first plurality of switch ports and a plurality of memory ports, each of the switch ports being coupled to a respective one of the link interfaces in the first plurality, each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the link interfaces in the first plurality to any one of the memory controllers.