Patent ID: 7297577

Claim:
A method of making an SOI device with increased channel width in a full-depletion SRAM, comprising the steps of: applying a first layer of an oxide to an SOI substrate; applying a first layer of polysilicon to the first layer of oxide; patterning and etching the first layer of polysilicon to create a first predetermined area substantially corresponding to a SRAM cell area; patterning and etching the first layer of an oxide to correspond to a logic area; performing shallow trench silicon RIE at the SRAM cell area; depositing a first layer of a nitride over the SRAM cell area and the logic area; performing RIE over the logic area; depositing a second layer of an oxide over the SRAM cell area and the logic area; etching back the second layer of an oxide over the SRAM cell area, between a plurality of device areas in the logic area, and between the SRAM cell area and the adjacent device area; removing the exposed oxide over the SRAM cell area and around the sides of each of the plurality of devices; performing silicon RIE between the plurality of device areas in the logic area and between the SRAM cell area and the adjacent device area; depositing a second layer of a nitride over the SRAM cell area and the logic area; performing a first chemical mechanical polishing step to remove all the deposited second layer of a nitride down to about a top edge of the remaining first polysilicon layer; removing the first polysilicon layer; removing the exposed silicon oxide layer; epitaxially growing a first layer of silicon into the voids created by the steps of removing the first polysilicon layer and removing the exposed silicon oxide layer; performing a second chemical mechanical polishing step to remove all the deposited first layer of a silicon down to about the same level as the first chemical mechanical polishing step; removing the second nitride layer; depositing a third oxide layer over the SRAM cell area and over a portion of each of the plurality of device areas; depositing a gate electrode substantially over the third oxide layer; depositing a spacer layer adjacent the gate electrode and third oxide layer; depositing a silicide layer on the exposed first epitaxial silicon layer and over a portion of the gate electrode; and depositing contacts, each of said contacts in electrical connection with one of the silicide layers.