Patent ID: 8612915

Claim:
A cell leakage reduction system communicatively coupled to a library system configured to store one or more cells, the cell leakage system comprising: a processor; an interface module configured to receive a cell from the library system, wherein the cell comprises information describing one or more transistors and how the one or more transistors are coupled; a path module executing on the processor and configured to identify each rail-to-rail path in the cell; a transistor set module executing on the processor and configured to select one or more of the one or more transistors of the cell that are coupled to a rail of the cell and, if removed, no rail-to-rail path would exist in the cell, wherein the selected transistors are a minimum number of transistors that if removed result in no rail-to-rail path exists in the cell; and a layout modification module executing on the processor and configured to transform the cell by upsizing a gate length of each transistor of the selected transistors to create a low-leakage version of the cell and store the low-leakage version of the cell in a memory coupled to the layout modification module, wherein the layout modification module is further configured to determine if there are additional transistors within the cell that can be upsized where the additional transistors are not within the selected transistors and upsize the selected transistors if upsizing the selected transistors does not change a delay of the cell to be above a delay budget or does not change an area of the cell to be above an area budget.