Patent ID: 8248879

Claim:
A semiconductor device comprising: a plurality of memory cells each of which is required with a refresh of information every predetermined time interval; a first power supply line; a second power supply line having a potential lower than that of said first power supply line; a first circuit connected between said first and second power supply lines, said first circuit being operable at potentials of said first and said second power supply lines and accessing said plurality of memory cells; third and fourth power supply lines supplying said first and said second power supply lines with potentials, respectively, which are necessary for said first circuit to operate in an active mode; a first switch connected between said first and said third power supply lines, said first switch electrically controlling a potential required to operate said first circuit in the active mode by a first control signal; a second switch connected between said second and said fourth power supply lines, said second switch electrically controlling a potential required to operate said first circuit in the active mode by the first control signal; and a refresh control circuit generating a refresh request signal every the predetermined time interval to refresh information of said memory cells through said first circuit, wherein said refresh control circuit time-sequentially generates an internal active signal at N times in connection with said refresh request signal once and maintains an activation of said first control signal during a first time interval which is a duration in connection with said internal active signals at the N times without making a change to a logic value of said first control signal, where N represents a first integer which is not less than two, wherein said first circuit is put into a state to enable to operate in said active mode by the potentials supplied from said third and said fourth power supply lines in a response to the first control signal which is activated for said first time interval, and said first circuit time-sequentially refreshes information in said plurality of memory cells in a response to the internal active signals at the N times, wherein said first and said second switches stop supply of potentials required to operate said first circuit in the active mode during a duration other than said first time interval.