Patent ID: 7114069

Claim:
A reconfigurable processor circuit, comprising: an array of configurable circuit blocks; a control processor that configures a function of a plurality of the configurable circuit blocks; a delay locked loop multiple frequency generator that receives a reference clock as an input and generates a plurality of clock signals as outputs, each clock signal being configured in frequency by the control processor, the delay locked loop multiple frequency generator comprising: a delay line with a plurality of tap outputs from each of a plurality of delay elements; a phase detector that compares the reference clock with an output of the delay line and produces an output related to a result of the comparison; a low pass filter receiving the phase detector output as an input and producing a filtered output that controls a delay of the delay line; a plurality multiplexers each receiving the plurality of outputs from the delay line and producing one of the plurality of clock signals as an output; and a tap selection processor, responsive to the control processor, that configures each multiplexer to select a set of tap outputs that produces a specified clock signal at the output of each of the associated multiplexers; whereby, the clock signal at the output of any of the multiplexers can be changed by reconfiguration of the associated multiplexer by the tap selection processor without incurring a period of instability; a timing control circuit that receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the allocating and routing are carried out under program control.