Patent ID: 7473961

Claim:
A non-volatile memory device comprising: a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed; a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer that is adjacent to the semiconductor substrate and a charge trapping layer that is adjacent to the electron tunneling layer; and an electron back-tunneling prevention layer, which is adjacent to a bottom surface of the gate electrode and is interposed between the gate electrode and the charge trapping layer, wherein an electron flow path is formed between at least one of: (1) a region proximal to the source region, the electron tunneling layer, and the charge trapping layer, and (ii) a region proximal to the drain region, the electron tunneling layer, and the charge trapping layer, such that electrons are injected into the charge trapping layer, the electron back-tunneling prevention layer prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and wherein the electron back-tunneling prevention layer is formed of a metal having a higher work function than the gate electrode.