Patent ID: 6918025

Claim:
An integrated circuit comprising: A. a substrate of semiconductor material; B. processor circuits formed on the substrate, the processor circuits including address leads on the substrate, the address leads carrying address signals defining an addressable memory space, the addressable memory space being divided into at least two segments, and the processor circuits including data leads, separate from the address leads and also located on the substrate, the data leads coupled to addressable memory locations in the addressable memory space; and C. wait state register circuits formed on the substrate, the wait state register circuits including at least two registers each containing memory wait state information, one register for each segment of the addressable memory space, each of the at least two registers of the wait state register circuits is coupled to the address leads and is separately addressable by addresses on the address leads, each of the registers of the wait state register circuits being coupled to the data leads to receive the memory wait state information in the form of data signals from the data leads, and the memory wait state information in each register defining a number of memory wait states for each segment.