Patent ID: 8108657

Claim:
A computing system comprising: a processor; a floating point unit and an integer unit within said processor; a translator unit arranged to receive subject code instructions including at least one instruction relating to a floating point operation, and in response to generate corresponding target code for execution on said processor; a floating point status unit within the translator arranged to generate floating point status information according to the received subject code instructions, wherein the translator unit is arranged to maintain, as part of a subject register bank a representation of a subject floating point unit stack referred to by received subject code instructions, and wherein the floating point status unit is arranged to monitor the content of the representation of the subject floating point unit stack to generate floating point status information; and a floating point control unit within the translator unit arranged to receive the floating point status information from the floating point status unit, and in response to control the translator unit to generate either: target code for performing the floating point operations on the floating point unit; or target code for performing the floating point operations using a combination of the integer unit and the floating point unit.