Patent ID: 8013426

Claim:
A transistor structure comprising: a semiconductor substrate having a gate-side surface; a gate disposed on the gate-side surface, the gate extending above the gate-side surface by a first height; a spacer adjacent to a sidewall of the gate; a semiconductor extension disposed on the gate-side surface and extending above the gate-side surface by a second height larger than the first height, the semiconductor extension including a diffusion region having a diffusion surface located at the second height; a contact element electrically coupled to the diffusion surface; and planarized etch stop layer having a top surface co-planar with the diffusion surface and disposed directly adjacent to the semiconductor extension, the diffusion region, the spacer, a top surface of the gate and the gate-side surface to form a planarized etch stop layer above the spacer, the top surface of the gate and the gate-side surface, wherein the contact element is disposed on and in direct contact with the diffusion surface and wherein the etch stop layer is positioned between the contact element and the top surface of the gate.