Patent ID: 7745343

Claim:
A method for fabricating a semiconductor device with a fuse element, comprising: providing a semiconductor structure having a first device region and a second device region; forming a fuse element over the semiconductor structure in the first device region; forming a first interlayer dielectric layer, conformably covering the fuse element and the semiconductor structure; forming an etching stop layer, conformably covering the first interlayer dielectric layer; forming a second interlayer dielectric layer, blanketly covering the etching stop layer, wherein the second interlayer dielectric layer is formed with a planar top surface; forming a bond pad over the second interlayer dielectric layer in the second device region; forming a passivation layer, conformably covering the bond pad and the second interlayer dielectric layer; performing a first etching process to pattern the passivation layer, respectively forming a first opening in the first device region and a second opening in the second device region, wherein the first opening is substantially located over the fuse element and exposes a portion of the second interlayer dielectric layer, and the second opening is substantially located over the bond pad and partially exposes a portion of the bond pad; performing a second etching process, removing the portion of the second interlayer dielectric layer exposed by the first opening and exposing a top surface and partial sidewalls of the etching stop layer formed over the fuse element; and performing a third etching process, removing the portion of the second interlayer dielectric layer, the etching stop layer, and a portion of the first interlayer dielectric layer exposed by the first opening such that another passivation layer conformably covering the fuse element and the semiconductor structure adjacent to the fuse element is left.