Patent ID: 7123038

Claim:
A method for performing voltage sampling over an extended voltage range on a semiconductor chip, comprising: sampling an input voltage at a node within the semiconductor chip through a first sampling pathway using nMOS pass gates which latch the input voltage to produce a first output signal, wherein the first output signal tracks the input voltage from ground up to a cut-off voltage for the NMOS pass gates; sampling the input voltage through a second sampling pathway using NMOS pass gates which latch the input voltage to produce a second output signal, wherein prior to the NMOS pass gates along the second sampling pathway, the input voltage passes through a source-follower gate, which translates the input voltage down, so that the second output signal tracks the input voltage from a turn-on voltage of the source-follower gate up to Vdd; combining the first and second output signals to produce a combined output signal, which tracks the input voltage over the extended voltage range from ground to V dd ; and performing a calibration operation by: passing an external calibration voltage through a first calibration pathway, which is similar to the first sampling pathway to produce a first calibration output signal, passing the external calibration voltage through a second calibration pathway, which is similar to the second sampling pathway, to produce a second calibration output signal, and measuring the first and second calibration output signals and using the resulting measurements to calibrate subsequent voltage measurements.