Patent ID: 7245544

Claim:
An integrated semiconductor memory device that can be operated in a normal operating state and in a test operating state, the integrated semiconductor memory device comprising: at least one control circuit to control the integrated semiconductor memory device in the normal operating state and in the test operating state; a plurality of data connections; a plurality of memory cells; and a plurality of sense amplifiers that are combined in groups, wherein each sense amplifier is connectable to a respective memory cell in order to access the respective memory cell, each sense amplifier is configured to be activated in order to access the respective memory cell, and each sense amplifier in the activated state is connected to a respective data connection; wherein: the control circuit is configured such that, in the normal operating state of the integrated semiconductor memory device, when one of the memory cells is accessed, the control circuit activates a respective first sense amplifier that is connected to the one of the memory cells, and further activates a selected number of additional sense amplifiers that are combined in the same group with the first sense amplifier; and the control circuit is further configured such that, in the test operating state of the integrated semiconductor memory device, when the one of the memory cells is accessed, the control circuit activates the first sense amplifier.