Patent ID: 8428907

Claim:
A jitter calculating method performed by a processing device executing software code configured to cause the processing device to perform one or more operations of the method, the method comprising: obtaining circuit data indicating a circuit from a storage device; setting a path of a signal, which extends from an initial point through a plurality of cells to an end point, to be an analysis target path based on said circuit data; calculating power supply voltages respectively supplied to said plurality of cells as supply voltages based on said circuit data; generating cell delay data by calculating cell delay amounts indicating how long delay times of said signal are in each of said plurality of cells; and calculating jitter values in said end point based on said cell delay data, wherein said plurality of cells include: an upper stage cell; and a lower stage cell connected to a lower stage of said upper stage cell, said supply voltages include: a first supply voltage supplied to said upper stage cell; and a second supply voltage supplied to said lower stage cell, said signal is supplied as a first input signal to said upper stage cell, said signal is outputted as a first output signal from said upper stage cell, said signal is supplied as a second input signal to said lower stage cell, said signal is outputted as a second output signal from said lower stage cell, and said generating said cell delay data includes: calculating, based on a first input transition time as a transition time of said first input signal and said first supply voltage, first cell delay amounts indicating delay times of said signal in said upper stage cell and a first output transition time as a transition time of said first output signal; setting said first output transition time to be a second input transition time as a transition time of said second input signal; and calculating, based on said second input transition time and said second supply voltage, second cell delay amounts indicating delay times of said signal in said lower stage cell and a second output transition time as a transition time of said second output signal.