Patent ID: 7911845

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses, wherein the memory cell array has a plurality of pages, each page is defined as a simultaneously written range in the memory cell array, each page has a first area, the address of which is expressed by a power of 2, and an additional second area different from the first area, each of the areas is to be data loaded, and wherein the multiple selection mode of the address decode circuit is set with regard to write data loading only in the first area.