Patent ID: 8316211

Claim:
A processor comprising: privileged mode logic to transfer control of the processor among a plurality of virtual machines; an interface to perform a transaction to fetch information from a memory; memory management logic to translate an untranslated address to a memory address, including: a storage location to store a first address of a first data structure for the first translation stage of a plurality of translation stages; the plurality of translation stages, each translation stage having translation logic to find an entry in a corresponding data structure based on a corresponding portion of the untranslated address, each entry to store one of a second address of a second data structure for the first translation stage, an address of a data structure for a successive translation stage, and the memory address; determination logic to determine whether an entry is storing a second address of a second data structure for the first translation stage; and a translation lookaside buffer to store translations, each translation lookaside buffer entry including one of a plurality of address source identifiers, each address source identifier to identify a unique micro-context from a plurality of micro-contexts, each address source identifier based on one of a plurality of virtual partition identifiers, at least two of the plurality of virtual partition identifiers associated with one of the plurality of virtual machines, wherein a first portion of the at least two virtual partition identifiers is assigned by a control program; and virtual partition identifier generation logic to generate a second portion of the at least two virtual partition identifiers, the second portion of the first of the at least two virtual partition identifiers based on the first address and the second portion of the second of the at least two virtual partition identifiers based on the second address.