Patent ID: 8228069

Claim:
A test apparatus fabricated on a semiconductor substrate, comprising: a plurality of pairs of test gate lines on the semiconductor substrate, one of each of the pairs of test gate lines being adjacent to the other; a plurality of pairs of test shared contacts on the semiconductor substrate, one shared contact of each of the pairs of test shared contacts being adjacent to the other shared contact of the pair, wherein the test shared contacts of the each plurality of pairs of test shared contacts are on respective end portions of the respective pairs of test gate lines; a first test structure which comprises a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to each of the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test shared contact; and a second test structure which comprises a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test shared contact.