Patent ID: 8874837

Claim:
An integrated circuit comprising: a programmable circuitry operable according to a first clock frequency and configured by loading configuration data to extract search keys from packets; a first block random access memory comprising: a first random access memory (RAM) element having a first data port; and a first memory processor coupled to the first data port of the RAM element through a hardwired connection and coupled to the programmable circuitry; wherein the first memory processor is operable according to a second clock frequency that is higher than the first clock frequency; and wherein the first memory processor is hardwired and performs operations solely in the first RAM element; a second block random access memory comprising: a second RAM element having a second data port; and a second memory processor coupled to the second data port of the second RAM element through a hardwired connection and serially connected to the first memory processor through a hardwired connection; wherein the second memory processor and the data port of the second RAM element operate at the second clock frequency; and wherein the second memory processor performs operations solely in the second RAM element; wherein each of the first memory processor and the second memory processor is operable to perform a comparison operation using data read from the first RAM element and the second RAM element respectively; wherein the hardwired connection between the first memory processor and the second memory processor passes data read from the first RAM element from the first memory processor to the second memory processor; wherein each of the first block RAM and the second block RAM operate upon a portion of a search key obtained from the programmable circuitry; and wherein each hardwired connection is functional within the integrated circuit without loading the configuration data.