Patent ID: 7331005

Claim:
A testing circuit for testing a device, comprising: a test clock input for receiving a test clock signal from an external test apparatus; a test data input for receiving a first test data signal from the external test apparatus; wherein the test clock signal and the test data signal have an initial phase difference upon being received at the test clock input and test data input, respectively; a input data storage element connected to the test data input and configured for storing test data represented by the first test data signal; wherein the input data storage element comprises a clock input for receiving the test clock signal and an output for outputting, according to the test clock signal, a second test data signal representative of the test data; a test data output connected to the output of the input data storage element and configured for outputting the second test data signal to the device; and a test clock output configured to output the test clock signal to the device; a first variable delay element configured for adjusting the phase difference between the second test data signal and the test clock signal from the initial phase difference to a first adjusted phase difference between the first test data signal and the test clock signal; wherein the first variable delay element is adjustable, whereby a delay caused by the first variable delay element can be varied according to a controlled input signal.