Patent ID: 7865804

Claim:
A device for detecting at least one error in a memory, the device comprising: a primary memory comprising N number of primary memory banks, primary memory data being stored at predetermined locations in each of the N number of primary memory banks, wherein a predetermined location in a first primary memory bank corresponds to the same location in each of the other Nâˆ’1 primary memory banks; a first error detection unit configured to receive the primary memory data from the primary memory and generate first primary memory error data, each error value of the first primary memory error data being determined using a set of data that includes one bit from each of the N number of primary memory banks such that the first primary memory error data includes a number of bits equal to a total number of bits in the primary memory divided by N number of primary memory banks, the bits of the set of data located at corresponding predetermined locations in the primary memory banks; a primary error memory configured to store the first primary memory error data; a second error detection unit configured to receive the primary memory data from the primary memory and generate second primary memory error data; and an error data comparator configured to compare the first primary memory error data with the second primary memory error data to detect the at least one error in the primary memory.