Patent ID: 7774535

Claim:
A memory system comprising: a first memory device including a plurality of first data pins and configured to receive write data from a controller and transmit read data to the controller via at least one of the plurality of first data pins, said at least one of the plurality of first data pins being point-to-point-connected to at least one data pin of the controller; a second memory device including a plurality of second data pins and configured to receive write data from the controller and transmit read data to the controller via at least one of the plurality of second data pins, said at least one of the plurality of second data pins being point-to-point-connected to at least another one data pin of the controller; and a redelivery module within the first memory device, configured to receive an address and a command from the controller via a predetermined signal line and to redeliver the received address and command to the second memory device via at least a remaining one of the plurality of first data pins.