Patent ID: 8301716

Claim:
An interface for a multi-processor gateway apparatus comprising: a first processor of the multi-processor gateway apparatus; and a second processor of the multi-processor gateway apparatus, wherein the second processor comprises an API layer, wherein the first processor is configured with executable software instructions that cause the first processor to perform operations comprising: serving a user interface to a user device connected to the multi-processor gateway apparatus via a path, wherein the user interface presents selectable functions to be performed by the multi-processor gateway apparatus; receiving an instruction from the user device to perform a selected function; determining whether the selected function is to be performed by the first processor or the second processor; and when the selected function is to be performed by the first processor: executing the instruction; and sending a result of the execution of the instruction by the first processor to the user device via the path; when the selected function is to be performed by the second processor: issuing an inter process communication call to the API layer of a second processor, wherein the second processor is configured with executable software instructions that cause the second processor to perform operations comprising executing the instruction; receiving from the API layer of the second processor a result of the execution of the instruction by the second processor; and sending the result of the execution of the instruction by the second processor to the first processor, wherein the first processor sends the results of the execution of the instruction by the second processor to the user device via the path.