Patent ID: 8862901

Claim:
A memory subsystem adapted to load and store data at memory addresses thereof, the memory subsystem being functionally connected to a processor, the memory subsystem being adapted to pull low a write enable signal to store data in the memory subsystem and to pull high the write enable signal to load data in the memory subsystem, the memory subsystem comprising: an address encryption system having first and second address scramblers, the first and second address scramblers configured to convert logical memory addresses generated by the processor into physical memory addresses at which the data are stored in the memory subsystem, the first and second address scramblers being configured to convert logical memory addresses into physical memory addresses according to different algorithms, wherein the address encryption system converts logical memory addresses into physical memory addresses with the first address scrambler in the event of a WRITE operation, wherein if the write enable signal is pulled high in the event of a READ operation the address encryption system converts logical memory address into physical memory address with the second address scrambler; and a local hardware device supplying a key to the memory subsystem, wherein in the event of a READ operation supplying of the key causes the address encryption system to switch from the second address scrambler to the first address scrambler and convert the logical memory addresses into physical memory addresses with the first address scrambler instead of the second address scrambler, wherein if the key is not supplied, the data retrieved by the processor in a READ operation is sought from incorrect physical memory addresses according to the algorithm of the second address scrambler resulting in retrieval of invalid or useless data.