Patent ID: 7383399

Claim:
A memory buffer comprising: a first port to couple the memory buffer with an upstream memory agent via a memory channel, the first port having a first transmit link interface and a first receive link interface; a second port coupled to the first port via redrive logic, the second port to couple the memory buffer with a downstream memory agent via the memory channel, the second port having a second transmit link interface and a second receive link interface, wherein the redrive logic is to sample information received on the first port and to redrive the information to the downstream memory agent via the second port; a memory interface coupled with the first port and the second port, the memory interface to provide an interface between the memory buffer and one or more dynamic random access memory devices (DRAMs); an input buffer to receive data from the one or more DRAMs via the memory interface; a compression engine coupled with the input buffer, the compression engine to receive the data from the input buffer and to provide compressed data to a cache; the cache to store at least a portion of the compressed data; and an output buffer coupled with the compression engine, the output buffer to provide the compressed data to the one or more DRAMs via the memory interface, wherein the memory buffer and the one or more DRAMs are located on a common module, and further wherein the compression engine compresses data without sending compressed data over the memory channel, and wherein the memory buffer is to isolate the DRAMs from the memory channel.