Patent ID: 7200235

Claim:
A programmable logic device comprising: a configuration memory; programmable logic circuitry coupled to the configuration memory; programmable routing circuitry coupled to the configuration memory and configured to inter-couple the programmable logic circuitry; an access port adapted to receive a plurality of decryption keys; a key memory adapted to store the plurality of decryption keys, wherein the key memory includes storage for respective write-protect values and read-protect values in association with the decryption keys; error checking circuitry connected to the key memory and adapted to verify each decryption key and generated a signal indicative to correctness of the decryption key; a password memory adapted to store a first password; and a configuration circuit arrangement coupled to the configuration memory, to the key memory, and to the password memory, the configuration circuit arrangement adapted to decrypt portions of an input configuration bitstream with respective ones of the plurality of decryption keys and respectively associated count values that indicate numbers of bytes in the portions of the input configuration bitstream, the input configuration bitstream including encrypted configuration data and an encrypted second password, and the configuration circuit arrangement further adapted to write decrypted configuration data to the configuration memory in response to the first and second passwords being equal, and disable writing of decrypted configuration data to the configuration memory in response to the first and second passwords being unequal.