Patent ID: 8861291

Claim:
A signal delay circuit, comprising: an input inverter, for receiving an input signal and outputting an inverted input signal; a first inverter, having a input terminal and an output terminal, the input terminal of the inverter is coupled to the input inverter for receiving the inverted input signal; a first capacitor, coupled to an output terminal of the first inverter; a first transistor, having a first terminal, a second terminal and a control terminal, the second terminal of the first transistor being coupled to the output terminal of the first inverter and the first terminal of the first transistor being coupled to a first reference voltage; a second inverter, an input terminal of the second inverter being coupled to the output terminal of the first inverter and an output terminal of the second inverter being coupled to the control terminal of the first transistor; and an output inverter, an input terminal of the output inverter being coupled to the output terminal of the second inverter and a delayed output signal being generated at an output terminal of the output inverter.