Patent ID: 7203875

Claim:
A test system for providing formatted signals, the test system comprising: a timing generation circuit operative to provide timing information signals on a single CMOS Integrated Circuit (IC); and a formatter in communication with said timing generation circuit, said formatter comprising: a drive circuit, said drive circuit comprising: a plurality of event logic interfaces, each event logic interface capable of decoding signals received from said timing generation circuit; a plurality of delay line elements (DLEs), each DLE in communication with a corresponding event logic interface and capable of generating timing markers corresponding to signals received from an event logic interface; and a drive logic in communication with said plurality of DLEs and operative to produce formatted levels in response to timing markers received from said plurality of DLEs; and wherein variation of drain to source voltage of said plurality of DLEs are compensated such that the drain to source voltage variation below a specified percentage is maintained and such that said formatter provides a specified number of transitions per second and a specified edge placement resolution and accuracy.