Patent ID: 8654577

Claim:
An SMT MRAM memory device comprising: array of rows and columns of SMT MRAM cells wherein Each of the columns of SMT MRAM cells is associated with one of its adjacent columns of SMT MRAM cells; a plurality of true data bit lines, wherein each of the true data bit lines is connected to each of the SMT MRAM cells of one of the columns of SMT MRAM cells; a plurality of complement data bit lines, wherein each complement data bit line is associated with one of the true data bit lines and connected each of the SMT MRAM cells connected to its associated true data bit line; a plurality of true data bit line shunting switch devices, wherein at least one true data bit line shunting switch devices is connected between the true data bit line and the complement data bit line of the connected columns of SMT MRAM cells for selectively connecting one of the true data bit lines to its associated complement data bit line of a non-selected column in parallel to effectively to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.