Patent ID: 7859509

Claim:
A semiconductor integrated circuit device comprising: a shift register including a plurality of cascaded flip-flops adapted to generate shift pulse signals in response to a start signal; and a logic circuit adapted to receive a pulse signal at its input end and supply said pulse signal from its plurality of output ends to said flip-flops, said pulse signal at each of the plurality of output ends being allowed and prohibited by a corresponding one of said shift pulse signals, wherein said logic circuit comprises a plurality of cascaded logic gates whose output ends serve as the plurality of output ends of said logic circuit, each of said logic gates performing a logic operation upon said pulse signal and a predetermined one of said shift pulse signals to allow and prohibit said pulse signal at a corresponding one of the plurality of output ends of said logic circuit, wherein leading edges of said shift pulse signals coincide with each other, and trailing edges of said shift pulse signals are shifted from each other, such that said pulse signal at the plurality of output ends of said logic circuit are sequentially allowed or prohibited, and wherein said logic circuit comprises: a pre-stage logic circuit being adapted to receive said pulse signal at its input end and supply said pulse signal from its plurality of output ends to a pre-stage half of said flip-flops, said pulse signal at each of the plurality of output ends of said pre-stage logic circuit being allowed and prohibited by a corresponding one of said shift pulse signals of the pre-stage half of said flip-flops, wherein, after said pulse signal at each of the plurality of output ends of said pre-stage logic circuit is allowed by the leading edges of said shift pulse signals of the pre-stage half of said flip-flops, said pulse signal is prohibited sequentially from a final one of the plurality of output ends of said pre-stage logic circuit to a first one of the plurality of output ends of said pre-stage logic circuit by the trailing edges of said shift pulse signals of the pre-stage half of said flip-flops; and a post-stage logic circuit being adapted to receive said pulse signal at its input end and supply said pulse signal from its plurality of output ends to a post-stage half of said flip-flops, said pulse signal at each of the plurality of output ends of said post-stage logic circuit being allowed and prohibited by a corresponding one of said shift pulse signals of the post-stage half of said flip-flops, wherein, after said pulse signal at each of the plurality of output ends of said post-stage logic circuit is allowed by the leading edges of said shift pulse signals of the post-stage half of said flip-flops, said pulse signal is prohibited sequentially from a final one of the plurality of output ends of said post-stage logic circuit to a first one of the plurality of output ends of said post-stage logic circuit by the trailing edges of said shift pulse signals of the post-stage half of said flip-flops.