Patent ID: 7308592

Claim:
A method for switching on-the-fly from a first primary clock signal source to a second secondary stand-by clock signal source synchronous to said first one, in a multi-node computer system, having a clock signal source each including an oscillator device, a synthesizer/phase locked-loop (PLL) circuit a plurality of N nodes each including a separate clock distribution chip, which is free of PLL circuits, a dedicated Dynamic Clock Switching Circuit (DCSC) connecting said clock signal sources and a respective said plurality of N clock distribution chips by means of a respective wiring provided for the switching process, said method comprising the steps of: supplying a plurality of N clock signal distribution chips with said two separate clock signals; controlling a phase of said two clock signals such that the signal edge of the secondary clock signal P 2 _ 10 arrives earlier than the corresponding signal edge of said primary clock signal P 2 _ 00 at each clock signal distribution chip; fine-tuning a delay for said secondary clock signal at the input terminal of each of said clock distribution chips such that the phase of said secondary signal is late-shifted relative to phase of the primary signal by a predetermined phase difference; and selecting during normal operation the earlier phase clock signal, and in case the primary clock signal fails, selecting the remaining phase-shifted secondary signal for distribution to the processor chips.