Patent ID: 8413011

Claim:
A 1-bit error correction method comprising: calculating a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes; determining whether a peak number of unsatisfied check nodes calculated with respect to the respective variable nodes exceeds a predetermined value; performing error decoding of a bit corresponding to a variable node with respect to which the peak number of unsatisfied check nodes has been calculated when the peak number of unsatisfied check nodes exceeds the predetermined value; detecting a position of a first or last one of the variable nodes connected to the unsatisfied check nodes when the peak number of unsatisfied check nodes does not exceed the predetermined value; and estimating that an error has occurred at a variable node positioned “k” places after the first variable node among the variable nodes connected to the unsatisfied check nodes, or estimating that an error has occurred at a variable node positioned “k” places before the last variable node among the variable nodes connected to the unsatisfied check nodes, where “k” denotes a message size in a parity-check matrix.