Patent ID: 8683255

Claim:
A circuit for controllably delaying an input signal, the circuit comprising: a first delay unit and a second delay unit, the input signal being switched to the first delay unit which is configured to delay the input signal by k cycles of a first clock signal so as to generate a value x t — k , and transfer the input signal to the second delay unit, wherein the second delay unit comprises a converter and a second shift register, the converter being connected to the second shift register by n leads, wherein the value x t — k and a value x t — k−1 are present at the converter, x t — k−1 being the input signal delayed by k−1 cycles of the first clock signal, wherein the converter is configured such that the value x t — k−1 is present on leads 1 to m and the value x t — k is present on leads m+1 to n, where 1≦m≦n−1, or such that the value x t — k−1 or x t — k is present at all leads 1 to n, and wherein the second shift register is configured to successively output values present on leads 1 to n as an output signal of the circuit.