Patent ID: 7666733

Claim:
A fabrication process for a vertical MOS transistor comprising: forming a source in or on a semiconductor substrate; forming a channel above the source, the channel made of a semiconductor material; forming a drain above the channel; forming, above the drain, an electrically insulating assembly including electrically insulating zones on either side of the drain; forming, in the semiconductor material, two recesses on either side of the electrically insulating assembly, respective sidewalls of the two recesses closest to the electrically insulating assembly being positioned beneath the electrically insulating assembly and on either side of the channel to form cavities; forming first electrically insulating layers beneath the two recesses; forming second electrically insulating layers on said first electrically insulating layers and on the sidewalls of the two recesses; forming a gate, on either side of the electrically insulating assembly, reaching into the cavities; forming a hole extending as far as the drain through the electrically insulating assembly; and forming a drain pre-contact in the hole.