Patent ID: 7247933

Claim:
A semiconductor die assembly ( 200 , 300 , 400 ), comprising: a plurality of die packages ( 100 ), each including: a lead frame ( 10 ) having a plurality of leads ( 11 ) surrounding a central region ( 12 ), each of the leads ( 11 ) having a first surface ( 14 ) and a down set portion ( 101 ) extending from the first surface ( 14 ), a semiconductor die ( 30 ) disposed in the central region ( 12 ) and electrically connected to the leads ( 11 ), the semiconductor die ( 30 ) having a first surface ( 34 ) formed thereon, the first surface ( 34 ) of the semiconductor die ( 30 ) being substantially coplanar with the first surface ( 14 ) formed on each of the leads ( 11 ), and an encapsulant ( 50 ) disposed in the central region ( 12 ) and covering the semiconductor die ( 30 ) and a portion of the leads ( 11 ), the first surface ( 14 ) of the leads ( 11 ) and the first surface ( 34 ) of the semiconductor die ( 30 ) being exposed from the encapsulant ( 50 ), and the first surface ( 34 ) of the semiconductor die ( 30 ) and the down set portions ( 101 ) of the leads ( 11 ) forming a cavity ( 102 ); wherein the plurality of die packages ( 100 ) are stacked such that at least a portion of the encapsulant ( 50 ) is disposed in the cavity ( 102 ) of a next higher die package ( 100 ) in the stack.