Patent ID: 7423924

Claim:
A semiconductor memory device comprising: a shared sense amplifier portion; a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion; a pair of transfer gates disposed on the opposite sides of the shared sense amplifier portion and between the pair of memory cell portions and the shared sense amplifier portion; and bit lines which constitute a plurality of bit line pairs and which connect the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, wherein the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides, and wherein the shared sense amplifier portion comprises a first shared sense amplifier with the bit lines in the bit line pair of the plurality of bit line pairs twisted and a second shared sense amplifier with the bit lines in a different bit line pair of the plurality of bit line pairs untwisted, the first and the second shared sense amplifiers being alternately arranged.