Patent ID: 8372705

Claim:
A method for forming n and p field effect transistors comprising: selecting a substrate having p and n regions for forming n and p field effect transistors respectively therein, forming a first gate dielectric and a first poly silicon gate electrode having sidewalls there over on at least one p region, forming a second gate dielectric and a second poly silicon gate electrode having sidewalls there over on at least one n region, forming a first mask over said second gate dielectric, said second poly silicon gate electrode and said n region, forming a tensely stressed film over said first poly silicon gate electrode, etching said tensely stressed film to provide a tensely stressed spacer on said sidewalls of said first poly silicon gate electrode, forming an n type halo region in said p region on opposite sides of said first poly silicon gate electrode, forming an n type source and drain extension in said p region overlapping said n type halo regions on opposite sides of said first poly silicon gate electrode, removing said first hard mask, forming a second mask over said p region, n type source and drain extensions, n type halo regions, tensely stressed spacers, and first poly silicon gate electrode, forming a compressively stressed film over said second poly silicon gate electrode, etching said compressively stressed film to provide a compressively stressed spacer on said sidewalls of said second poly silicon gate electrode, forming a p type halo region in said n region on opposite sides of said second poly silicon gate electrode, forming a p type source and drain extension in said n region overlapping said p type halo regions on opposite sides of said second poly silicon gate electrode, and removing said second mask.