Patent ID: 8726130

Claim:
An output buffer circuit for a non-volatile memory, said non-volatile memory for storing a plurality of data bits and a plurality of error correction check (“ECC”) bits associated with said plurality of data bits, said output buffer circuit comprising: an error check circuit for receiving the plurality of data bits and the plurality of ECC bits from the non-volatile memory to determine if the plurality of data bits need to be corrected, said error check circuit for supplying said plurality of data bits at an output, and for generating a correction signal; an error correction circuit for receiving the plurality of data bits and the plurality of ECC bits from the error check circuit and for generating a plurality of corrected data bits in response to the correction signal; a first storage circuit; a second storage circuit; a third storage circuit; and a switch circuit configurable to concurrently: transfer a first set of data from the non-volatile memory to the first storage circuit, transfer a second set of data from the error correction circuit to the second storage circuit, and transfer a third set of data from the third storage circuit as the output of said output buffer circuit; wherein said error check circuit is configurable for controlling the operation of the switch circuit.