Patent ID: 8786346

Claim:
A phase interpolator, comprising: a first, a second, a third, and a fourth differential pair each including a first and a second transistor having sources coupled with each other to form a source coupled node, each of the differential pairs further including a stabilizing capacitor connected between the source coupled node and a reference voltage; a plurality of current sources; and a group of switches having a plurality of connection patterns to switch connections between the source coupled nodes of the differential pairs and the plurality of current sources so that (i) a first operating current is supplied to the source coupled node of a first selected one of the first and second differential pairs and (ii) a second operating current is supplied to the source coupled node of a second selected one of the third and fourth differential pairs, wherein: gates of the first and second transistors in the first differential pair receive a first input signal having a first phase and a second input signal having a second phase opposite to the first phase, respectively; gates of the first and second transistors in the second differential pair receive the second input signal and the first input signal, respectively; gates of the first and second transistors in the third differential pair receive a third input signal having a third phase between the first and second phases and a fourth input signal having a fourth phase opposite to the third phase, respectively; gates of the first and second transistors in the fourth differential pair receive the fourth input signal and the third input signal, respectively; and drains of the first transistors in the differential pairs are commonly connected to a first load resistor to form a first output node and drains of the second transistors in the differential pairs are commonly connected to a second load resistor to form a second output node so that a differential output signal is output from the first and second output nodes.