Patent ID: 7879675

Claim:
A method of forming a transistor comprising: forming a gate electrode having a pair of laterally opposite sidewalls on a gate dielectric layer formed on a semiconductor layer; forming a pair of source/drain extensions in said semiconductor layer on opposite sides of said gate electrode; forming a pair of sidewall spacers adjacent to said sidewalls of said gate electrode and on said source/drain extensions; forming a pair of source/drain contact regions in said semiconductor layer on opposite sides of said sidewall spacers; forming an interlayer dielectric adjacent to said sidewall spacers and over said source/drain contact regions; etching a pair of contact openings through said interlayer dielectric to expose a portion of said source/drain contact regions; etching away a portion of said source/drain contact regions to form a pair of etched-out source/drain contact regions, each etched-out source/drain contact region having an opening into said semiconductor layer, wherein each opening into said semiconductor layer is larger than each of the pair of contact openings formed through said interlayer dielectric; and depositing a metal film into said contact openings and into said etched-out source/drain contact regions.