Patent ID: 7227234

Claim:
An integrated circuit comprising: a substrate having a substrate surface; at least one field-effect transistor (FET) including: a first gate structure formed over the substrate surface and having opposing side walls, first oxide layers respectively formed on the sidewalls of the first gate structure, sidewall spacers respectively formed on the first oxide layers, and first source and drain regions formed in the substrate, each of the first source and drain regions including an associated junction positioned under the first gate structure; at least one non-volatile memory (NVM) cell including: a second gate structure formed over the substrate surface and having opposing side walls, second oxide layers respectively formed on the sidewalls of the second gate structure, charge storage structures respectively formed on the second oxide layers, and second source and drain regions formed in the substrate, each of the second source and drain regions including a junction located under the charge storage structures; and pocket implants formed in the substrate, each pocket implant extending from the substrate surface under the second gate structure to the junction of an associated one of the second source region and the second drain region, wherein the pocket implant comprises a dopant of a first type, and the second source and drain regions comprise a dopant of a second conductivity type, a first gate oxide layer located between the first gate structure and a surface of the substrate; and a second gate oxide layer located between the second gate structure and the surface of the substrate, third oxide layers located between each of the sidewall spacers and a surface of the substrate; and fourth oxide layers located between each of the charge storage structures and the surface of the substrate, wherein each of the first oxide layers has a first thickness and each of the second oxide layers have a second thickness that is equal to or less than the first thickness, wherein the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness that is equal to or less than the first thickness, wherein the sidewall spacers of the FET and the charge storage structures of the NVM cell comprise a dielectric material with local storage nodes capable of storing static electric charge, wherein the third oxide layers have a first thickness and the fourth oxide layers have a second thickness that is equal to or less than the first thickness, wherein lower surfaces of the sidewall spacers have first widths, and lower surfaces of the charge storage structures have second widths that is substantially equal to the first widths, wherein the first and third oxide layers comprise TEOS oxide having a thickness of approximately 200 A, wherein the second and fourth oxide layers comprise thermal oxide having a thickness in the range of 30 to 200 A, and wherein the first widths of the sidewall spacers and the second widths of the charge storage structures are in the range of 400 to 1000 A.