Patent ID: 6941426

Claim:
A caching system, comprising: a tail FIFO having a tail input to receive incoming frames containing varying amounts of data and a tail output to output the incoming frames a memory having a memory input and a memory output, the memory input is coupled to the tail output and the memory is operable to store data from the tail output, and wherein the memory is operable to output the stored data at the memory output; a multiplexer having first and second multiplexer inputs coupled to the tail output and the memory output, respectively, the multiplexer having a control input to select one of the multiplexer inputs to couple to a multiplexer output; a head FIFO having a head input coupled to the multiplexer output to receive data from the multiplexer output, and a head output to output frames of the received data; and a controller coupled to the tail FIFO, the head FIFO, and the memory and operable to transfer a dynamically selected number of blocks of data from the incoming frames having a dynamically selected block size from the tail FIFO to the memory and from the memory to the head FIFO, wherein the selected block size and the selected number of blocks together provide maximum memory transfer efficiency level.