Patent ID: 7394419

Claim:
A decoding circuit for decoding multibit digital data having a plurality of bits, and generating an electric signal indicating a result of decoding, comprising: a first bit group decoding circuit provided corresponding to a first bit group having at least one bit of said multibit digital data, and decoding the at least one bit of said first bit group for selecting and producing output candidates corresponding to a decoding result from a plurality of output candidates arranged along a first direction, said first bit group decoding circuit including a plurality of first sub-decoding circuits, one arranged for each group of a predetermined number of output candidates, each commonly receiving the bit of said first bit group for selecting one output candidate from a corresponding group of output candidates, said multibit digital data being divided into a plurality of bit groups at least one of which includes a plurality of bits, said plurality of bit groups including said first bit group, bit group decoding circuits being arranged corresponding to the respective bit groups, said bit group decoding circuits including said first bit group decoding circuit, and each of said first sub-decoding circuits including a plurality of unit decoders, each provided for different output candidates, arranged in parallel along a second direction; and a last bit group decoding circuit provided corresponding to a last bit group of said plurality of bit groups, and commonly receiving and decoding a bit of said last bit group, said last bit group decoding circuit including a plurality of last sub-decoding circuits each arranged corresponding to each respective output of the bit group decoding circuit at a preceding stage, for selecting a corresponding output from outputs of the bit group decoding circuit at the preceding stage in accordance with the bit of said last bit group for transmitting a selected corresponding output to an output signal line.