Patent ID: 7688087

Claim:
A test apparatus comprising a tester and a test interface, the tester provided with at least a logical signal generation circuit and at least a clock pulse signal generation circuit, the logical signals and clock pulse signals being connected with the plurality of pin electronic channels through a plurality of metal wires, the characterized in that the test interface comprises: at least an electronic connection device, each of which is for electrically connecting to a device under test (DUT); a plurality of mixed signal generation circuits disposed on the test interface; and a plurality of pin electronic channels is disposed on the test interface for electrically connecting each of electronic connection devices with the plurality of mixed signal generation circuits, wherein said clock pulse signal is generated from a clock pulse generation circuit based on a test program and at least said logical signal generation circuit and at least said clock pulse generation circuit are electrically connected with said plurality of pin electronic channels via the plurality of mixed signal generation circuits.