Patent ID: 7929263

Claim:
A circuit comprising: an electrostatic discharge (ESD) protected circuit that is coupled between a direct current (DC) supply voltage and an electrical ground; and a latching ESD protection circuit that is coupled between the DC supply voltage and the electrical ground and comprising a feedback loop, the latching ESD protection circuit being adapted to: generate a latch enable signal independently of the feedback loop, wherein in response to an amplitude of a voltage between the DC supply voltage and the electrical ground exceeds a high threshold, the latch enable signal is in a disable state after a first time period and the feedback loop turns off in response to the disable state of the latch enable signal; providing a high impedance between the DC supply voltage and the electrical ground during a high impedance state; providing a low impedance between the DC supply voltage and the electrical ground during a low impedance state; transitioning from the high impedance state to the low impedance state wherein the feedback loop latches the latching ESD protection circuit in the low impedance state when the amplitude of the voltage between the DC supply voltage and the electrical ground exceeds the high threshold; and transitioning from the low impedance state to the high impedance state by unlatching the ESD protection circuit wherein the feedback loop is off when the first time period is exceeded, wherein the latching ESD protection circuit protects the ESD protected circuit from damage due to ESD events.