Patent ID: 6844619

Claim:
A semiconductor device comprising: a first semiconductor chip which has a first surface; an external connecting terminal which is formed on said first surface, said external connecting terminal having a primary height with respect to said first surface; a second semiconductor chip which is mounted on said first surface through a bump, said second semiconductor chip having a secondary height with respect to said first surface; a rewiring which electrically connects said first semiconductor chip, said second semiconductor chip, and said external connecting terminal with each other and which is located on said first surface; an insulating layer which is overlaid on said rewiring and which has predetermined opening portions in a first region for forming said external connecting terminal and in a second region for mounting said second semiconductor chip, respectively; and bedding electrodes which are formed in said predetermined opening portions respectively, said external connecting terminal comprising BGA and being positioned on said bedding electrode in said first region, said second semiconductor chip being flip chip bonded to said bedding electrode in said second region through said bump, wherein said second semiconductor chip is thin whereby said secondary height is smaller than said primary height.