Patent ID: 7930162

Claim:
An integrated circuit configured for hardware co-simulation comprising: a command processor; a replay buffer coupled to the command processor and storing at least one command template, wherein each command template specifies an incomplete command; a command first-in-first out (FIFO) memory storing complementary data for completion of the command template; and a multiplexer coupled to the command processor, the replay buffer, and the command FIFO, wherein the multiplexer, under control of the command processor, selectively provides data from the replay buffer or the command FIFO to the command processor, wherein the command processor, responsive to a replay command read during a hardware co-simulation session, enters a replay mode, obtains the command template from the replay buffer, obtains the complementary data from the FIFO memory according to a symbol read from the command template, and forms a complete command by joining the command template with the complementary data.