Patent ID: 8332797

Claim:
A method comprising: receiving an integrated circuit (IC) design layout with a plurality of defined pixel-units, wherein a first pixel unit from the plurality of defined pixel-units includes a semiconductor structure; simulating, by a computer, a thermal effect to the IC design layout for each pixel-unit; generating a thermal effect map of the IC design layout for each pixel-unit; determining a target absorption value for the IC design layout based on the thermal effect map; identifying placement for thermal dummy cells to be added to the IC design layout based on the determined target absorption value; determining that the identified placement for a first thermal dummy cell from the thermal dummy cells overlaps with the semiconductor structure of the first pixel unit; modifying the first thermal dummy cell such that the first dummy cell does not overlap the semiconductor structure of the first pixel unit when inserted into the IC design; inserting the thermal dummy cells, including the modified first thermal dummy cell, the IC design layout based on the determined target absorption value; and wherein a thermal dummy cell is inserted into each pixel-unit to get close to the absorption target value for each pixel-unit to thereby get close to a uniform absorption value across the IC design layout.