Patent ID: 7444456

Claim:
An architecture for a programmable integrated circuit including: a first group of logic function modules associated with a first group of FPGA routing conductors; a second group of logic function modules spaced apart from said first group of logic function modules and associated with a second group of FPGA routing conductors; a plurality of dedicated SRAM blocks, each SRAM block having address busses, data busses and control lines; a plurality of pass-through interconnect conductors spanning each SRAM block, each of said plurality of said pass-through interconnect conductors having a first end and a second end; a first plurality of user-programmable interconnect elements coupled between first ends of the pass-through interconnect conductors and ones of the first group of FPGA routing conductors; a second plurality of user-programmable interconnect elements coupled between second ends of the pass-through interconnect conductors and ones of the second group of FPGA routing conductors; a multi-conductor address bus disposed in one of said plurality of dedicated SRAM blocks forming first intersections with said plurality of pass-through interconnect conductors; a multi-conductor data bus disposed in one of said plurality of dedicated SRAM blocks forming second intersections with said plurality of pass-through interconnect conductors; a multi-conductor group of control signal lines disposed in one of said plurality of dedicated SRAM blocks forming third interconnect intersections with said plurality of pass-through interconnect conductors; and user-programmable interconnect elements disposed at selected ones of said first, second and third intersections.