Patent ID: 7787560

Claim:
An apparatus to communicate with a smart antenna having a symbol period T comprising: a counter receiving a clock signal and operable to count said clock signal, said clock signal having a frequency high enough to provide plural clock pulses during each symbol period T; a memory mapped register storing data operable to be loaded via a memory mapped write operation; a comparator connected to said counter and said memory mapped register operable to generate a match signal when said count of said count equals said data stored in said memory mapped register; a flip-flop having a trigger input receiving said match signal of said comparator operable to toggle upon receiving said match signal and an output for transmission to the smart antenna; a microprocessor control unit operable to write data into said memory mapped register via a memory map write operation, said microprocessor control unit operable to: transmit a first digital signal by writing first constant data equal to about on third of the number of clock pulses in the symbol period T into said memory mapped register, waiting for said match signal and thereafter writing second constant data equal to about on two thirds of the number of clock pulses in the symbol period T into said memory mapped register and waiting for said match signal, and transmit a second digital signal opposite to said first digital signal by writing said second constant into said memory mapped register, waiting for said match signal and thereafter writing first constant data into said memory mapped register and waiting for said match signal.