Patent ID: 7461117

Claim:
A method for processing a fused multiple add instruction in a floating point unit in a data processing system with denormal multiplicand and addend operands having one addend operand and two multiplicand operands, the floating point unit comprising shift amount logic, alignment logic, multiply logic, adder logic and normalization logic, an alignment shift amount based on the exponents of the operands being computed by the shift amount logic, a fraction of the addend operand being aligned according to the alignment shift amount by an alignment logic, fractions of the multiplicand operands being multiplied by the multiply logic; outputs of the alignment logic and the multiply logic being added by the adder logic; an output of the adder logic being normalized by the normalization logic, the method comprising the steps of: calculating a number of leading zeros of the fraction of the addend operand by leading zero logic; computing select signals by compare logic based on the number of leading zeros and the alignment shift amount, which select signals indicate whether most significant bits of the alignment logic output have all the same value in order to control the carry logic of the adder logic and control a stage of the normalization logic; dividing the output of the alignment logic into a lower part and a higher part, the adder logic being divided in an adder unit and an incrementer unit, the lower part being added by the adder unit to the product of the multiplier logic, the incrementer unit adding a carry-out of the adder unit to the higher part of the output of the alignment logic, the adder unit comprises an end-around-carry logic, the end-around-carry logic being activated by the select signals of the compare logic, the adder logic output being divided into a lower and a higher part, the higher part being computed by the incrementer unit and the lower part being computed by the adder unit and the select signals of the compare logic being used to shift out the higher part of the adder logic output in the normalization logic; indicating by the select signals of the compare logic whether all bits of the higher part of the alignment logic output have the same value; and computing the carry output of the adder logic using the select signals of the compare logic and the carry output of the adder unit.