Patent ID: 7203883

Claim:
An integrated circuit, which operates in a normal operating state and in a test operating state, comprising: an output terminal (VOUT) for applying a reference potential (GND); a current pulse circuit (SIS) with an input terminal (ETML 1 ) for applying an input signal (Smeas); and an interconnect (L) for carrying a current (I), wherein the current pulse circuit (SIS) is connected to the output terminal (VOUT) via the interconnect (L), the current pulse circuit is designed, on the output side, to generate a first current pulse (Iref) with a first, predetermined time duration (tref) in a first test cycle (TZ 1 ) of the test operating state and a second current pulse (Imeas) with a second, time duration (tmeas) in a second test cycle (TZ 2 ) of the test operating state, the second time duration (tmeas) being dependent on the temporal profile of the input signal (Smeas), and in the normal operating state, a first current (I 1 ) flows on the interconnect (L) and, in the test operating state, a second current (I 2 ) flows during the first test cycle (TZ 1 ) and a third current (I 3 ) flows during the succeeding second test cycle (TZ 2 ), the second current (I 2 ) including a superposition of the first current (I 1 ) and the first current pulse (Iref) and the third current (I 3 ) including a superposition of the first current (I 1 ) and the second current pulse (Imeas).