Patent ID: 8140870

Claim:
A circuit, comprising: a control circuit configured to generate a first control signal for application to a first control terminal and generate a second control signal for application to a second control terminal, the control circuit comprising: a first delay timer configured to be triggered by a first event signal to count, a second delay timer configured to be triggered by a second event signal to count; a first comparator configured to compare the count of the first delay timer to a first threshold and cause a state change of the first control signal; a second comparator configured to compare the count of the second delay timer to a second threshold and cause an opposite state change of the first control signal; a third comparator configured to compare the count of the first delay timer to a third threshold and cause a state change of the second control signal; and a fourth comparator configured to compare the count of the second delay timer to a fourth threshold and cause an opposite state change of the second control signal.