Patent ID: 8321823

Claim:
A computer-implemented method for generating a synthesizable hardware description language file for a datapath for performing a permutation, the method comprising: receiving, with a computer system, the permutation on 2 n data words, n>1, and a positive integer value k, 1≦k≦n−1, wherein the permutation is given by an invertible n×n bit matrix P, 2 k is the streaming width for the datapath, such that the datapath receives 2 k data words at regular intervals; computing, with the computer system, n×n bit matrices N and M, wherein P=NM and rank(M 1 )=rank(N 1 ′)=k, wherein M 1 is the bottommost rightmost k×k submatrix of M and N 1 ′ is the bottommost rightmost k×k submatrix of N −1 ; generating, with the computer system, one or more synthesizable hardware description language files for the datapath, wherein the datapath comprises a write-stage connection network, a plurality of memory banks connected to the write-stage connection network, and a read-stage connection network connected to the plurality of memory banks, wherein the write-stage connection network writes the 2 k data words received at every interval to the memory banks according to the matrix M, and wherein the read-stage connection network reads data words from the memory banks each interval according to the matrix N and wherein the datapath is capable of accepting the first 2 k datawords of the next 2 n datawords to be permuted in the interval immediately following accepting the last 2 k datawords of the preceding 2 n datawords; and storing the one or more synthesizable hardware description language files in a computer file.