Patent ID: 7715269

Claim:
A semiconductor memory device comprising: first and second memory groups; first and second input/output (I/O) ports; a region configurator that sets first and second share regions in the first and second memory groups respectively, the region configurator setting first and second individual regions in the first and second memory groups respectively, the first and second share regions having common addresses to each other, the first and second individual regions having different addresses from each other, the region configurator making the first and second memory groups correspond to the first and second input/output (I/O) ports, respectively; a selector that connects each of the first and second memory groups to either one of the first and second input/output (I/O) ports; and an access controller that sets the selector to write a set of data, which has been supplied from either one of the first and second input/output (I/O) ports, in both the first and second share regions so that both the first and second share regions store the same set of data, wherein the access controller sets the selector to read out the same set of data from the first and second share regions respectively to the first and second input/output (I/O) ports, simultaneously with each other.