Patent ID: 7386084

Claim:
A system for pattern-independent phase alignment and adjustment in a clock and data recovery circuit, the system comprising: a data XOR gate coupled to a differential input data signal, said data XOR gate having a single output coupled to a bias voltage through a first variable resistor; a reference XOR gate coupled to a latched differential input signal, said reference XOR gate having a single output coupled to said bias voltage through a second variable resistor; and at least one latch coupled to at least one differential input of said data XOR gate and said reference XOR gate, wherein at least one of the following is adjusted: a resistance ratio of said first variable resistor and said second variable resistor so that current pulses at an output of said data XOR gate and current pulses at an output of said reference XOR gate are equal for a desired phase relationship between a clock signal and a data signal; and a current flowing through said first variable resistor so that no current flows at said single output of said data XOR gate when there are no transitions occurring at an input of said data XOR gate and a current flowing through said second variable resistor so that no current flows at said single output of said reference XOR gate when there are no transitions occurring at an input of said reference XOR gate.