Patent ID: 7102209

Claim:
A substrate panel for use in semiconductor packaging, comprising: a lead-frame panel, including an array of device areas, each device area having a die attach pad encircled by & plurality of conductive features, each conductive feature defined by an innermost contact portion, an outermost landing portion, and a connecting lead segment, wherein the innermost contact portion lies proximal to the die attach pad and extends through the lead-frame panel to expose a bottom surface on the bottom of the lead-frame panel and said conductive feature having the outermost landing portion located near an edge of the device area and further away from the die attach pad than the innermost contact portion, the outermost landing portion including a wirebonding surface and having a connecting lead segment that extends between the innermost contact portion and the outermost landing portion wherein the connecting lead segment is thinner than the innermost contact portion that extends through the lead-frame panel; and a dielectric material that fills spaces between adjacent conductive features and that fills spaces underneath the connecting lead segments, wherein a top surface of the dielectric material is substantially coplanar with the top surface of the lead-frame panel and the wire bonding surfaces, and the bottom surface of the dielectric material is substantially coplanar with the bottom surface of the lead-frame panel and said exposed bottom surface of said innermost contact portions, thereby forming lead-frame panel having substantially planar top and bottom surfaces.