Patent ID: 7777272

Claim:
A non-volatile memory device comprising: a first doped layer of a first conductivity type disposed on a substrate; a semiconductor pillar of a second conductivity type opposite to the first conductivity type, wherein the semiconductor pillar extends upward from the first doped layer; a first control gate electrode disposed along a first sidewall of the semiconductor pillar; a second control gate electrode disposed along a second sidewall of the semiconductor pillar and separated from the first control gate electrode; and a second doped layer of the first conductivity type overlying the semiconductor pillar; a first charge storage layer interposed between the semiconductor pillar and the first control gate electrode; and a second charge storage layer interposed between the semiconductor pillar and the second control gate electrode, wherein: a width of the second doped layer is greater than a width of the semiconductor pillar, and a peripheral portion of the second doped layer protrudes past the first and second sidewalls of the semiconductor pillar, the first charge storage layer is conformally formed along a bottom surface of the peripheral portion of the second doped layer, the first sidewall of the semiconductor pillar, and the upper surface of the substrate, the second charge storage layer is conformally formed along a bottom surface of the peripheral portion of the second doped layer, the second sidewall of the semiconductor pillar, and the upper surface of the substrate, at least a portion of each of the first and second control gate electrodes is within an area, as viewed from a top down perspective, of the second doped layer, the first charge storage layer extends over and under respective top and bottom surfaces of the first control gate electrode, and the second charge storage layer extends over and under respective top and bottom surfaces of the second control gate electrode.