Patent ID: 7594055

Claim:
A computer memory system for storing and retrieving data, the system comprising: a memory bus; a main memory controller in communication with the memory bus for generating, receiving, and responding to memory access requests; one or more memory devices characterized by memory device protocols and signaling requirements for command, address, data, voltage and timing operational specifications; and one or more hub devices in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data, wherein the main memory controller and the hub devices communicate via the memory bus in messages in a message format and protocol for indicating memory read, memory write, memory system power management and control that is independent of the memory device protocols and signaling requirements, and the hub devices further comprise device timing and command ordering logic to pre-condition the one or more memory devices in preparation for completing the memory access requests and compile a sequence of memory commands associated with the memory access requests.