Patent ID: 7245525

Claim:
A memory arrangement comprising: a first memory cell comprising a first thyristor having a cathode and a first access transistor having a first end connected to the cathode of the first thyristor; a second memory cell comprising a second thyristor having a cathode and a second access transistor having a first end connected to the cathode of the second thyristor; the second access transistor having a second end connected to a second end of the first access transistor; a first diode having an anode and a cathode, the anode of the first diode being connected to the cathode of the first thyristor and the cathode of the first diode being at a first voltage level at a first time period and a second voltage level at a second time period, with the first voltage level being higher than the second voltage level; and a second diode having an anode and a cathode, the anode of the second diode being connected to the cathode of the second thyristor and the cathode of the second diode being at substantially the first voltage level at the first time period and substantially the second voltage level at the second time period.