Patent ID: 7734980

Claim:
An apparatus comprising: a memory content error detector coupled with a buffered memory module channel to receive data from the buffered memory module, to apply an error detection code to the received data on each bit-lane of the buffered memory module channel, and to detect an error on a bit-lane, the memory content error detector having an M-bit cyclic redundancy check (CRC) component and an N-bit CRC component, wherein the N-bit CRC component is to be selected if at least one bit-lane fails, and wherein the buffered memory module channel includes at least one additional bit-lane to convey CRC information without having to append CRC characters to the data; the memory content error detector to detect errors in the received data, to correct errors in the received data if it is determined that the error is correctable and that there is no error on a bit-lane, and to indicate whether data received from the buffered memory module channel contains a correctable error; and a retry engine coupled with the memory content error detector, the retry engine capable of signaling a data retry on the buffered memory module channel if at least one bit-lane of the buffered memory module channel fails and the memory content error detector indicates a correctable error.