Patent ID: 8340240

Claim:
A shift register comprising a plurality of serially-coupled shift register units, an Nth stage shift register unit among the plurality of shift register units comprising: an input end for receiving an input voltage; an output end for outputting an output voltage; a first node; a pull-up driving circuit for transmitting the input voltage to the first node; a pull-up circuit for providing the output voltage according to a first clock signal and the input voltage; a second node; a buffer circuit for providing a start pulse signal at the second node according to the first clock signal and the input voltage; a first pull-down circuit for providing a first voltage at the first node or at the output end according to a second clock signal, comprising: a first switch including: a first end coupled to the first node; a second end coupled to the output end; and a control end; a second switch including: a first end coupled to the output end; a second end for receiving the first voltage; and a control end coupled to the control end of the first switch; a third switch including: a first end coupled to the control end of the first switch; a second end for receiving the first voltage; and a control end coupled to the first node; a fourth switch including: a first end for receiving the second clock signal; a second end coupled to the control end of the first switch; and a control end coupled to the first end of the fourth switch; and a fifth switch including: a first end coupled to the second node; a second end for receiving the first voltage; and a control end coupled to the control end of the first switch; a second pull-down circuit for providing a second voltage at the first node or at the output end according to a third clock signal, comprising: a sixth switch including: a first end coupled to the first node; a second end coupled to the output end; and a control end; a seventh switch including: a first end coupled to the output end; a second end for receiving the second voltage; and a control end coupled to the control end of the sixth switch; an eighth switch including: a first end coupled to the control end of the sixth switch; a second end for receiving the second voltage; and a control end coupled to the first node; a ninth switch including: a first end for receiving the third clock signal; a second end coupled to the control end of the sixth switch; and a control end coupled to the first end of the ninth switch; wherein a frequency of the first clock signal is higher than a frequency of the second or the third clock signal; and a tenth switch including: a first end coupled to the second node; a second end for receiving the second voltage; and a control end coupled to the control end of the sixth switch; and a third pull-down circuit for providing a third voltage at the first node or at the output end according to a feedback voltage.