Patent ID: 7496876

Claim:
A method for generating integrated functional testcases for multiple boolean algorithms from a single generic testcase template for verifying a mask build layout integrated circuit design, comprising: (a) creating a generic testcase template with dummy levels containing test shapes using an integrated circuit design layout editor, the test shapes defined within a plurality of user-entered mask levels; (b) grouping the test shapes within each mask level of the template based on common shapes interactions used in mask build operations; (c) selecting a subset of the mask levels from the template for use in a testcase, the testcase subsequently deployed in a mask build development environment to verify the mask build layout integrated circuit design; (d) developing testcase generation code containing instructions to copy and rename the selected mask levels into desired input levels of the testcase to verify the mask build layout integrated circuit design, wherein the testcase generation code comprises mask build language; (e) executing the generated testcase generation code with a shapes processing engine to generate mask build shapes within the testcase; (f) modifying the testcase generation code to change the mask levels and test distinct mask build layout integrated circuit design; and (g) adding shape interactions for new mask level builds into the generic testcase template and repeating steps (c)-(f) to generate new mask build shapes with the testcase to test additional mask build layout integrated circuit design.