Patent ID: 7285815

Claim:
A non-volatile memory device, comprising: a device isolation layer for defining a plurality of active regions in a semiconductor substrate; a pair of control gate patterns extending across the active regions; a pair of selection gate patterns extending across the active regions between the pair of control gate patterns; floating gate patterns formed at an intersection region where the control gate patterns extend across the active regions; and lower gate patterns each formed at an intersection region where the selection gate patterns extend across the active regions; inter-gate dielectric patterns each disposed between corresponding one of the control gate patterns and corresponding one of the floating gate patterns; and dummy dielectric patterns each disposed between corresponding one of the selection gate patterns and corresponding one of the lower gate patterns, each of the sidewall of the dummy dielectric patterns self-aligned with one sidewall of the selection gate pattern and overlapping a predetermined width of the selection gate pattern, each of said sidewall of the dummy dielectric pattern facing corresponding one of the pair of control gate patterns.