Patent ID: 7873789

Claim:
A system controller for controlling, in a multiprocessor system, a request issued by a CPU, the system controller comprising: a CPU-issued request queue having plural entries for retaining the request issued by the CPU; an input-request retaining section for retaining a latest request other than a cache replace request issued by the CPU and retained by the CPU-issued request queue; and a retry determination section for determining whether a new request issued by the CPU is to be retried, wherein the CPU-issued request queue includes a circuit that outputs a signal indicating necessity of retry when any one of the entries retains an address, a specific part of which matches a specific part of an address of the new request issued by the CPU, the input-request retaining section includes a circuit that outputs a signal for controlling not to retry when the new request is a cache replace request and the specific part of the address of the new request matches the specific part of the address of the request retained by the input-request retaining section and other parts of the address of the new request do not match the other part of the address of the request retained by the input-request retaining section, and the retry determination section determines, when the CPU-issued request queue outputs the signal indicating necessity of retry and the input-request retaining section does not output the signal for controlling not to retry, the new request to be retried and, otherwise, causes the CPU-issued request queue to retain the new request without determining the new request to be retried.