Patent ID: 8174901

Claim:
A semiconductor integrated circuit device comprising: a plurality of nonvolatile memory cells, each including: a read select gate terminal; a write gate terminal; a data input/output terminal; and a power supply terminal; a plurality of sub-arrays, each including: read gate lines to which the write gate terminals of said nonvolatile memory cells are commonly coupled; read gate line driving circuits which drive said read gate lines; read select gate lines to which the read select gate terminals of said nonvolatile memory cells are commonly coupled; power supply lines to which the power supply terminals of said nonvolatile memory cells are commonly coupled; and data lines each of which is coupled to said data input/output terminals; a memory array including: the sub-arrays; write gate line driving circuits which are provided in common to the read select gate lines included in each of said sub-arrays; power supply line driving circuits which are commonly coupled to said power supply terminals included in each of said sub-arrays; and read gate line transfer circuits which are commonly coupled to said read gate line driving circuits; a write data transfer circuit whose components are coupled respectively to said data lines included in said sub-arrays and transfers data to be written into at least one of said nonvolatile memory cells when writing data into said nonvolatile memory cells; a data line selecting circuit whose components are coupled respectively to said data lines included in said sub-arrays and selects a data line when reading data from at least one of said nonvolatile memory cells; and an amplifier circuit which is commonly coupled to the components of said data line select circuit and amplifies a data signal appearing on the data line selected by said data line selecting circuit.