Patent ID: 6996016

Claim:
A method of operating a double data rate memory device, comprising: providing a bi-directional line in a system bus of the memory device to transmit a WAIT_DQS signal, the WAIT_DQS signal comprising functionality of (i) a WAIT signal indicating when valid data is present on a data bus in Read cycle and when a memory is ready to accept data in Write cycle, and (ii) a data strobe (DQS) signal serving as a timing signal for valid data; and propagating the WAIT_DQS signal in a bi-directional line in a system bus of the memory device, wherein the bi-directional line is coupled to the memory and a system controller, and wherein the WAIT_DQS signal has a WAIT state until completion of a refresh operation, in the event that a read cycle collides with an execution of the refresh operation.