Patent ID: 8314632

Claim:
A monolithic integrated circuit having a low power standby mode (LPSM) as well as a normal operating mode (NM) and comprising: a core logic section that is operable at, and configured to receive, a predefined normal-mode, power voltage and is also operable at, and configured to receive, a substantially lower and predefined, standby mode power voltage, the core logic section being able to use first digital signaling levels when operating under the normal-mode power voltage and to use different second digital signaling levels when operating under the standby mode power voltage, the core logic section having a core logic ground bus relative to which the normal-mode power voltage and the standby mode power voltage are applied; a digital signal outputting section that is operable at a predefined I/O power voltage different from the predefined normal-mode power voltage and different from the predefined standby mode power voltage, the signal outputting section being able to use third digital signaling levels for outputting digital data signals to circuitry outside the monolithic integrated circuit; a transition logic section that is operatively interposed between the core logic section and the signal outputting section and that is configured to provide signal level shifting as between each of the first and second digital signaling levels used by the core logic section and different I/O signaling levels used by the digital signal outputting section, the transition logic section being coupled to receive a same respective one of the normal-mode power voltage and the standby mode power voltage as is received by the core logic section respectively during the normal operating mode (NM) and the low power standby mode (LPSM); and a negative voltage supply; wherein the transition logic section includes a special ground bus (GNDx) that is coupled so as to be automatically coupled to the core logic ground bus when the monolithic integrated circuit is in said normal operating mode (NM) and to be automatically coupled to the negative voltage supply when the monolithic integrated circuit is in said low power standby mode (LPSM).