Patent ID: 7569446

Claim:
A method, comprising: depositing an oxide layer over a portion of a metal layer over an nFET region of a CMOS structure; etching the metal layer over a pFET region of the CMOS structure; etching the oxide layer over the nFET region; forming gate structures over the nFET region and pFET region; forming an STI region between the nFET region and the pFET region, wherein the etching the portion of the metal layer and the oxide layer exposes a portion of the metal layer over the STI region while leaving the oxide layer abutting against the metal layer over a portion of the STI region, wherein the portion of the metal layer over the STI region protects the STI from formation of stringers during the formation of the gate structures, the oxide layer is self aligned over the nFET region, the depositing of the oxide layer includes depositing the oxide layer over the pFET region, and further comprising planarizing the oxide layer to such an extent that the metal layer is exposed over the pFET region and the oxide layer abuts a portion of the metal layer over an STI region, the depositing of the oxide layer abuts against a raised portion of the metal layer eliminating a gap or overlay region over an STI region, and the metal layer is TiN which is exposed over the pFET region.