Patent ID: 7075829

Claim:
An electronic system, comprising: a processor; and a memory device coupled to processor, wherein the memory device includes a programmable decoder comprising: a number of address lines; a number of output lines; wherein the address lines, and the output lines form an array; a number of logic cells formed at the intersections of output lines and address lines, wherein each of the logic cells includes a vertical non-volatile memory cell including: a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates, wherein the number of control gates are separated from the number of floating gates by a low tunnel barrier intergate insulator; a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first source/drain regions of column adjacent pillars in the array.