Patent ID: 8331162

Claim:
A semiconductor memory device comprising: a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell; a first low bit line connected to the at least one first memory cell; a first low complementary bit line connected to the at least one second memory cell; a first switch unit having a first terminal connected to the first low bit line, the first switch unit being configured to be switched on or off based on a first switch control signal; a second switch unit having a first terminal connected to the first low complementary bit line, the second switch unit being configured to be switched on or off based on a second switch control signal; a first global bit line connected to a second terminal of the first switch unit; a first global complementary bit line connected to a second terminal of the second switch unit; a plurality of sensing amplifying units including at least one sensing amplifying unit connected to the first global bit line and the first global complementary bit line; and a first isolation switch unit connected between the first global bit line and the at least one sensing amplifying unit, the first isolation switch also being connected between the first global complementary bit line and the at least one sensing amplifying unit, the first isolation switch unit being configured to be switched on or off based on a first isolation switch control signal, wherein the first global bit line and the first global complementary bit line are connected to the same memory cell array.