Patent ID: 8612504

Claim:
A processing system, comprising: a first memory having first and second sections and a second memory having third and fourth sections; an encoder configured to encode data alternatively in each of the first and second memory sections of the first memory and to encode data alternatively in each of the third and fourth memory sections of the second memory, wherein the encoder encodes the first and second memory sections of the first memory before encoding the third and fourth memory sections of the second memory, wherein the encoder reads a first data from the first memory section of the first memory, processes the first data, and writes the first data back to the first memory section of the first memory as a first encoded data, and the encoder reads a second data from the second memory section of the first memory, processes the second data, and writes the second data back to the second memory section of the first memory as a second encoded data; an IFFT configured to process the first and second encoded data alternatively in each of the first and second memory sections of the first memory and to process a third and fourth encoded data alternatively in each of the third and fourth memory sections of the second memory, wherein the IFFT processes the first and second sections of the first memory before processing the third and fourth sections of the second memory, wherein the IFFT reads the first encoded data from the first memory section of the first memory, processes the first encoded data, and writes the first encoded data back to the first memory section of the first memory as a first IFFT processed data, and the IFFT reads a second encoded data from the second memory section of the first memory, processes the second encoded data, and writes the second encoded data back to the second memory section of the first memory as a second IFFT processed data; and a post-processor configured to process the first and second IFFT processed data in each of the first and second memory sections of the first memory while the IFFT is processing the third and fourth encoded data alternatively in each of the third and fourth memory sections of the second memory, the post-processor configured to operate simultaneous with, and at a different clock speed than, the encoder or the IFFT without disrupting the encoder or the IFFT, wherein the post-processor reads the first and second IFFT processed data from the first and second memory sections of the first memory and processes the first and second IFFT processed data.