Patent ID: 7161439

Claim:
A circuit comprising: a ring oscillator delay stage, the delay stage comprising: a first transistor, a gate of the first transistor to receive a first input signal; a second transistor, a gate of the second transistor to receive a second input signal, and a source of the second transistor coupled to a source of the first transistor; and an active inductor comprising a first resistive element coupled to a gate of a third transistor, the source of the third transistor coupled to a drain of the first transistor, wherein a first node located at a drain of the third transistor provides a first output clock signal, wherein a second node located at the coupling of the source of the third transistor and the drain of the first transistor provides a second signal, and wherein a third node located at a drain of the second transistor provides a third signal, and a second ring oscillator delay stage, the second delay stage comprising: a fourth transistor, a gate of the fourth transistor coupled to the first node and to receive the second signal; a fifth transistor, a gate of the fifth transistor coupled to the drain of the second transistor and to receive the third signal, and a source of the fifth transistor coupled to a source of the fourth transistor; and a second active inductor comprising a second resistive element coupled to a gate of a sixth transistor, the source of the sixth transistor coupled to a drain of the fourth transistor, wherein a fourth node located at a drain of the sixth transistor provides a second output clock signal, wherein a fifth node located at the coupling of the source of the sixth transistor and the drain of the fourth transistor provides a fourth signal to a next ring oscillator delay stage, and wherein a sixth node located at the drain of the second transistor provides a fifth signal to the next ring oscillator delay stage.