Patent ID: 7391070

Claim:
A memory device construction, comprising: a semiconductor substrate; a gate material positioned over at least a portion of the substrate, the gate material defining a lattice having an array of openings therein; a pair of elevationally-elongated source/drain regions on the substrate and extending through the openings in the lattice of gate material, such that the source/drain regions are at least partially surrounded by the gate material in at least two orthogonal dimensions, one of the source/drain regions being a first source/drain region and consisting essentially of conductively-doped epitaxial silicon, the other source/drain region being a second source/drain region and consisting essentially of conductively-doped silicon which is not epitaxial, the first and second source/drain regions being gatedly connected to one another through the gate material; a memory storage device electrically connected to either the first source/drain region or the second source/drain region; and a digit line electrically connected to whichever of the first and second source/drain regions is not electrically connected to the memory storage device.