Patent ID: 8564966

Claim:
An apparatus comprising: one or more processors; a printed circuit board in operative connection with the one or more processors; and a plurality of unit arrangements disposed on the printed circuit board, the a plurality of unit arrangements each comprising: two capacitor pairs, the two capacitor pairs comprising: two capacitors situated on the printed circuit board along a first axis bisecting the two capacitors length-wise; and two other capacitors situated on the printed circuit board along a second axis bisecting the two other capacitors length-wise; wherein a terminal of a capacitor situated along the first axis is disposed near a terminal of a capacitor situated along the second axis; wherein the first axis and the second axis intersect substantially at a right angle; and wherein, in a unit arrangement, the distance between a terminal of a capacitor situated along the first axis and a terminal of a capacitor situated along the second axis is less than the length of a capacitor; wherein a first set of unit arrangements is disposed on the printed circuit board along a first arrangement axis; wherein a second set of unit arrangements is disposed on the printed circuit board along a second arrangement axis; and wherein the first arrangement axis is parallel to the second arrangement axis.