Patent ID: 8629500

Claim:
An integrated circuit comprising: a first field effect transistor, the first field effect transistor comprising: a first connection region disposed in a semiconductor body, the first connection region being doped with a first doping type; a first channel region arranged adjacent the first connection region; a second connection region disposed in the semiconductor body, the second connection region being doped with a second doping type, the second doping type being different than the first doping type; a first insulation region disposed over the semiconductor body overlying at least a portion of the first connection region and the second connection region; a first control region adjacent the first insulation region; and a second field effect transistor, the second field effect transistor comprising: a third connection region and a fourth connection region, the third connection region and the fourth connection region being doped with the same doping type; a second channel region arranged between the third connection region and the fourth connection region; a second insulation region overlying the second channel region; and a second control region adjacent the second insulation region, wherein the first, second, third and fourth connection regions are located in separate regions, wherein the first insulation region has an equivalent silicon dioxide thickness that is at least 50 percent greater than the equivalent silicon dioxide thickness of the second insulation region.