Patent ID: 8154069

Claim:
A nonvolatile semiconductor memory including a memory cell transistor and a selection gate transistor, comprising: a semiconductor substrate including a first upper surface having a pair of element isolation regions and an active region located between the element isolation regions, the element isolation regions and active region extending to a first direction, respectively; a selection gate line formed above the semiconductor substrate, the selection gate line extending to a second direction which is perpendicular to the first direction; a word line formed above the semiconductor substrate, the word line extending to the second direction; a lower gate electrode of the selection gate transistor located between the selection gate line and the active region, the lower gate electrode having a second upper surface; a floating gate electrode of the memory cell transistor located between the word line and the active region, the floating gate electrode including a third upper surface; insulators formed in the element isolation regions, each of the insulators including a fourth upper surface located below the selection gate line and a fifth upper surface located below the word lines, a height of the fifth upper surface being lower than a height of the third upper surface of the floating gate electrode and a height of the fourth upper surface being the same as a height of the second upper surface of the lower gate electrode related to the first upper surface of the semiconductor substrate; a first inter-layer insulating film formed between the selection gate line and the lower gate electrode, the first inter-layer insulating film including a first opening to connect the selection gate line with the lower gate electrode and a first lower surface contacting with the second upper surface of the lower gate electrode; and a second inter-layer insulating film formed between the word line and the floating gate electrode, and between the selection gate line and the first inter-gate insulating film, the second inter-layer insulating film including a sixth upper surface directly contacting with the word line, a seventh upper surface contacting with the selection gate line, a second lower surface directly contacting with the third upper surface of the floating gate electrode and a third lower surface contacting with the first inter-layer insulating film, wherein the second inter-layer insulating film includes a second opening corresponding to the first opening so as to connect the selection gate line with the lower gate electrode, and the first and second inter-layer insulating films and selection gate line of the selection gate transistor have the same width in the first direction as the lower gate electrode.