Patent ID: 8219960

Claim:
A method for configuring at least one portion of programmable logic in an integrated circuit device to implement a plurality of instances of a relocatable circuit, comprising: for each of the instances of the relocatable circuit, assigning a respective portion of an address space of a processor to the instance of the relocatable circuit, wherein the processor accesses the address space with read and write transactions issued on an interface bus; for each of the instances of the relocatable circuit, configuring a respective interface circuit for translating the transactions accessing the respective portion of the address space into a fixed address space of the relocatable circuit: wherein the relocatable circuit is independent of the respective portions of the address space assigned to the instances of the relocatable circuit; for each of the instances of the relocatable circuit, selecting a respective one of a plurality of regions within an array of programmable logic and interconnect resources of the integrated circuit device; wherein each region is configurable to implement an instance of the relocatable circuit; and configuring the programmable logic and interconnect resources to implement the instances of the relocatable circuit and to couple each of the instances to the interface bus of the processor via the respective interface circuit; wherein the configuring includes the processor configuring the programmable logic and interconnect resources in the respective regions to implement the instances from a single copy of configuration data for implementing the relocatable circuit.