Patent ID: 7949086

Claim:
A shift register comprising: a plurality of register units cascaded-connected with each other, each register unit for outputting an output signal at an output end based on a first clock signal, a second signal, a third clock signal, and a driving signal from a previous stage register unit, each register unit comprising: a pull-up circuit coupled to the first clock signal, for providing the output signal; a pull-up driving circuit coupled to the pull-up circuit, being turned on in response to the driving signal from the previous stage register unit, and the second clock signal, and being turned off in response to the third clock signal; a pull-down circuit, for providing a supply voltage; and a pull-down driving circuit coupled to the pull-up driving circuit, for turning on the pull-down circuit in response to the first clock signal, and for turning off the pull-down circuit in response to the third clock signal or output of the pull-up driving circuit.