Patent ID: 7514288

Claim:
A method for manufacturing a memory device, comprising: forming an electrode layer having a top surface, the electrode layer comprising two first electrodes, a shared second electrode arranged between the two first electrodes, and insulating members separating the shared second electrode from the two first electrodes, and wherein the two first electrodes, the shared second electrode, and the insulating members extend to the top surface of the electrode layer, and the insulating members have respective widths between the shared second electrode and the two first electrodes at the top surface; and forming a first and a second bridge of memory material on the top surface of the electrode layer across respective insulating members, the first and second bridges respectively comprising a patch of memory material contacting a corresponding first electrode and the shared second electrode to define an inter-electrode current path through the respective bridge between the corresponding first electrode and the shared second electrode having a path length defined by the width of the corresponding insulating member, wherein the memory material has at least two solid phases.