Patent ID: 7459949

Claim:
A method for providing charge up and charge down control signals having active and inactive logic levels to a charge pump in a delay-locked loop, the charge pump charging a capacitance in response to the active logic level of the charge up signal, and discharging the capacitance in response to the active logic level of the charge down signal, the method comprising: in response to detection of a first edge of a reference clock signal, changing the inactive logic level of the charge down signal to the active logic level; in response to detection of an edge of a feedback clock signal within less than 180 degrees from said first edge, changing the inactive logic level of the charge up signal to the active logic level, and changing the active logic level of the charge down signal to the inactive logic level; and in response to detection that an edge of an additional reference signal at a point in time about midway between said first edge and a subsequent edge of said reference clock signal has past, changing the active logic level of the charge up signal to the inactive logic level, while maintaining the charge down signal at the inactive logic level.