Patent ID: 7164300

Claim:
A power-low reset circuit, receiving a reset signal outputted from a power-on reset circuit and a stored voltage of a capacitive device in the power-on reset circuit for providing an electrical path through the capacitive device in the power-on reset circuit to initiate charging/discharging for restoring to an initial status of the capacitive device when a power source voltage drops under a predetermined level, wherein the power-on reset circuit generates a reset signal at an initial moment of turning on the power source, the power-low reset circuit comprising: a first transistor, comprising a first gate electrode a first source/drain and a second source/drain, wherein the first gate electrode is adopted to receive the reset signal and the first source/drain is adopted to receive the stored voltage; a second transistor, comprising a second gate electrode, a third source/drain and a fourth source/drain, wherein the second gate electrode is adopted for receiving the power source voltage, wherein the third source/drain is coupled to the second source/drain of the first transistor, and wherein a second source/drain voltage is a control voltage; a control switch, comprising a first connection terminal and a second connection terminal, wherein the first connection terminal is adopted for receiving the stored voltage and the second connection terminal is coupled to a fixed voltage, and wherein the control switch determines whether or not the first connection terminal and the second connection terminal are connected together in accordance with the control voltage; and a clamping circuit, comprising a first terminal coupled to the fourth source/drain of the second transistor and the second terminal is coupled to the fixed voltage.