Patent ID: 7583219

Claim:
A method of controlling a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA), the method comprising the steps of: (a) simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal by being triggered by a QS signal within a first Q 2 clock pulse and respectively generating a first sampling value and a second sampling value while still within the first Q 2 clock pulse; (b) holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code by being triggered by a QL signal within the first Q 2 clock pulse; and (c) generating, at the residual signal generator, a residual signal using the corresponding first sampling value digital code and using the second sampling value in response to a Q 1 clock pulse subsequent to the first Q 2 clock pulse.