Patent ID: 7478355

Claim:
A method for implementing circuit layouts in a chip, comprising: forming a plurality of sub-circuit cells with the same layout in different positions of the chip, where each sub-circuit cell comprising a plurality of sub-circuit blocks and a transmission terminal, each sub-circuit block comprises at least two N-type MOS transistors or P-type MOS transistors which have doped regions with different areas, wherein the sub-circuit cells in different positions are for implementing input/output (I/O) circuit with different I/O functions; when the sub-circuit cells in different positions require different circuit functions, performing a layout programming in at least a connection layer so that different layouts are formed in different positions of the connection layer corresponding to the sub-circuit cells, wherein each layout in the connection layer corresponding to each sub-circuit cell creates a connection between some of the sub-circuit blocks within each corresponding sub-circuit cell by selectively connecting the sub-circuit blocks within each corresponding sub-circuit cell so that the sub-circuit cells in different positions implement different circuit functions.