Patent ID: 8810291

Claim:
A phase-locked loop (PLL), comprising: a voltage-controlled oscillator (VCO), configured to generate an output clock signal; a frequency down conversion circuit, electrically coupled to the VCO, configured to receive the output clock signal and an auxiliary clock signal, and to mix the output clock signal and the auxiliary clock signal so as to generate a feedback clock signal, wherein the frequency down conversion circuit comprises: a received signal strength indicator (RSSI), configured to detect the strength of the feedback clock signal; and a controller, electrically coupled to the RSSI, wherein, when the strength of the feedback clock signal is smaller than a predetermined threshold, the controller adjust the frequency of the output clock signal according to RSSI; a phase-frequency detector (PFD), electrically coupled to the frequency down conversion circuit, configured to receive the feedback clock signal and a reference clock signal, and to compare the frequencies and the phases of the feedback clock signal and a reference clock signal to generate an adjusting signal; and an adjusting circuit, electrically coupled to the PFD and the VCO, configured to receive the adjusting signal, and to adjust the frequency of the output clock signal generated by the VCO according to the adjusting signal.