Patent ID: 8773909

Claim:
A method of operating a memory system, the memory system including an array of non-volatile memory cells arranged into a NAND type of architecture, including a plurality NAND strings and a plurality word lines spanning the NAND strings, each of the word lines connected to a corresponding one of the memory cells thereof, the method comprising: receiving a search data pattern; splitting the search data pattern into a plurality of sub-patterns including at least first and second sub-patterns respectively corresponding to first and second sets of non-adjacent ones of the word lines; performing a first determination comprising: biasing the corresponding first set of the word lines according to the first sub-pattern; and concurrently determining those of the NAND strings that conduct in response to the corresponding first set of the word lines biased according to the first sub-pattern being applied thereto; performing a second determination comprising: biasing the corresponding second set of the word lines according to the second sub-pattern; and concurrently determining those of the NAND strings that conduct in response to the corresponding second set of the word lines biased according to the second sub-pattern being applied thereto; and subsequently combining results of the first and second determinations to determine those of the NAND strings that conduct in response to the word lines biased according to the first and second sub-patterns being applied thereto.