Patent ID: 8304309

Claim:
A method of forming a memory, the method comprising: forming a floating gate of a memory cell and a first portion of a control gate of a select gate substantially concurrently from a common first conductor; forming a dielectric over the floating gate of the memory cell and over the first portion of the control gate of the select gate; forming a control gate of the memory cell over the dielectric from a second conductor; after forming the control gate of the memory cell, forming a second portion of the control gate of the select gate over the dielectric from a third conductor so that the second portion of the control gate of the select gate passes through the dielectric and contacts the first portion of the control gate of the select gate; and forming a contact from the third conductor in contact with a source/drain region that is connected to the select gate substantially concurrently with forming the second portion of the control gate of the select gate from the third conductor.