Patent ID: 7825480

Claim:
A semiconductor device comprising: a MISFET disposed in a MISFET-forming region of a semiconductor substrate, the MISFET comprising a drain region, a channel-forming region, a source region, a gate insulating film, and a gate electrode; a doped semiconductor region disposed in a circumferential region of the semiconductor substrate, the doped semiconductor region surrounding the MISFET-forming region in plan view and being electrically coupled to the drain region; a first insulating film disposed over the semiconductor substrate; a conductive film disposed over the first insulating film and coupled to the gate electrode, the first insulating film and the conductive film being located 3 between the channel-forming region and the doped semiconductor region in plan view; a second insulating film disposed over the gate electrode and the conductive film; a source electrode terminal disposed over the second insulating film and electrically coupled to the source region; a gate electrode terminal disposed over the second insulating film and electrically coupled to the gate electrode; and a circumferential electrode terminal disposed over the second insulating film and electrically coupled to the doped semiconductor region, the circumferential electrode terminal surrounding the source electrode terminal in plan view, wherein the circumferential electrode terminal partially overlaps with the conductive film in plan view.