Patent ID: 7822168

Claim:
A frequency divider comprising: first to fifth flip-flops, each of the first to fifth flip-flops receiving a common clock signal, each of the first to fifth flip-flops sampling and outputting an input signal in response to a predetermined edge (termed an effective edge) of a rising edge and a falling edge of the clock signal, an output signal of the first flip-flop being supplied to an input of the second flip-flop; a first logic gate receiving an output signal of the second flip-flop and a first control signal as inputs, the first logic gate outputting the output signal of the second flip-flop when the first control signal is of a first value and outputting a predetermined value when the first control signal is of a second value, an output signal of the first logic gate being supplied to an input of the third flip-flop; a second logic gate receiving the output signal of the first flip-flop and a second control signal as inputs, the second logic gate outputting the output signal of the first flip-flop when the second control signal is of the first value and outputting a predetermined value when the second control signal is of the second value, an output signal of the second logic gate being supplied to an input of the fourth flip-flop; and a third logic gate receiving an output signal of the third flip-flop and an output signal of the fourth flip-flop as inputs, the third logic gate outputting an output signal of a first value when both inputs thereof are of a second value, an output signal of the third logic gate being supplied to an input of the fifth flip-flop, an output signal of the fifth flip-flop being fed back to an input of the first flip-flop.