Patent ID: 8043911

Claim:
A method of forming a semiconductor construction, comprising: forming a silicon-containing layer over a semiconductor substrate; the silicon-containing layer being n-type doped across a first region of the semiconductor substrate, and being p-type doped across a second region of the semiconductor substrate; forming multiple materials over the silicon-containing layer and across the first and second regions of the semiconductor substrate; etching through the multiple materials, and only partially into the silicon-containing layer to form a first partial gate structure over the first region and to form a second partial gate structure over the second region; the first and second partial gate structures having sidewalls comprising the multiple materials and comprising an etched portion of the silicon-containing layer; the etching partially into the silicon-containing layer being conducted with first etching conditions that are substantially non-selective between n-type doped silicon and p-type doped silicon; forming spacers along the sidewalls of the first and second partial gate structures; and after forming the spacers, etching through a remaining portion of the silicon-containing layer to form first and second transistor gates from the first and second partial gate structures; the etching through the remaining portion of the silicon-containing layer being conducted with second etching conditions that have higher selectivity than the first etching conditions between n-type doped silicon and p-type doped silicon.