Patent ID: 7418582

Claim:
A method for optimizing a register file hierarchy for a mode of operation in a multithreaded processor, the method comprising: providing a register file hierarchy with a plurality of register file cells, the register file cells corresponding to threads of the multithreaded processor; associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode; and, flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode; wherein the register file cells include in registers, local registers and out registers for a currently active register window, the register file hierarchy overlaps out registers of the currently active register window with in registers of a next register window, the in and out registers in each overlapping pair are backed up by the same memory cells, and the memory cells backing up the plurality of register file cells are not accessed when the processor is operating in a single threaded mode.