Patent ID: 7404056

Claim:
A method for managing state information in a processor, the method comprising: providing a lookup table including a number of memory circuits (“N M ”), each memory circuit having a plurality of entries, wherein entries in different ones of the memory circuits are accessible in parallel; storing a number of items of state information (“N S ”) belonging to a first state version in a first group of entries selected from the entries in the N M memory circuits; receiving an updated value for a first one of the N S items of state information while the first state version is in use by at least one thread executing in the processor, the first one of the N S items being stored in an entry in a first one of the N M memory circuits; creating a virtual copy of each of the N S items of state information in a second group of entries selected from the entries in the N M memory circuits, thereby transferring the first state version to the second group of entries; replacing the virtual copy of the first one of the N S items of state information in the second group of entries with a real copy of the first one of the N S items from the first group of entries; and replacing the first one of the N S items in the first group of entries with the updated value, thereby storing a second state version in the first group of entries.