Patent ID: 8629029

Claim:
A method of manufacturing a vertical SOI bipolar junction transistor comprises steps of: (a) according to priority growing a body region, a buried oxide layer and a top silicon film from down to up forming an SOI substrate; (b) forming an active region in the top silicon film via shallow trench isolation process of integrated circuit; (c) forming a collector region and a base region in the active region by ion implantation; (d) preparing a poly silicon layer on the top silicon film by chemical vapor deposition, and creating a mask; (e) forming a pattern in positive photoresist via the mask and doping the poly silicon layer twice by ion implantation, then forming an another pattern in negative photoresist via the mask so as to create two poly silicon structures which are a poly silicon emitter and a poly silicon base electrode respectively; (f) annealing, so as to drive impurities diffusing from the poly silicon emitter to the base region to form a shallow emitter junction; (g) creating a side-wall spacer to isolate the poly silicon emitter and the poly silicon base electrode.