Patent ID: 8896565

Claim:
An in-cell touch panel, comprising: (a) a plurality of pixels spatially arranged in a matrix; (b) a plurality of scanning lines, each scanning line electrically coupled to a corresponding pixel row of the pixel matrix; (c) at least one touch sensing device electrically coupled between two neighboring scanning lines and associated with a pixel therebetween; and (d) at least one reverse amplification circuit comprising: (i) a first thin-film transistor (TFT) having a gate electrically coupled to the at least one touch sensing device, a source and a drain configured to receive a first bias voltage, Vdh; (ii) a second TFT having a gate electrically coupled to the at least one touch sensing device, a source configured to receive a second bias voltage, Vdl, and a drain electrically coupled to the source of the first TFT; (iii) an amplification TFT having a gate electrically coupled to both the source of the first TFT and the drain of the second TFT, a source and a drain configured to receive a power supply voltage, VDD; and (iv) a selection TFT having a gate electrically coupled to one of the two neighboring scanning lines, a source electrically coupled to a signal readout line and a drain electrically coupled to the source of the amplification TFT, wherein the at least one touch sensing device is configured such that when a touch occurs, it causes a gate voltage level of one of the first TFT and the second TFT to increase and the gate voltage level of the other to decrease; and wherein Vdh>Vdl, and wherein the at least one touch sensing device is characterized with a first charge sharing circuit and a second charge sharing circuit, each charge sharing circuit comprising: a first transistor, T 1 , having a gate electrically coupled to the first one of the two neighboring scanning lines, a source configured to receive one of the first and second bias voltages Vdh and Vdl, and a drain electrically coupled to a first node, respectively; a second transistor, T 2 , having a gate electrically coupled to the second one of the two neighboring scanning lines, a source electrically coupled to the first node, and a drain electrically coupled to a second node, respectively; a third transistor, T 3 , having a gate electrically coupled to the first one of the two neighboring scanning lines, a source electrically coupled to the second node, and a drain configured to receive the other of the first and second bias voltages Vdh and Vdl, respectively; a touch sensing capacitor, Clc, electrically coupled between the first node and a common voltage, Vcom; and a reference capacitor Cref electrically coupled between the second node and a reference voltage, VSS.