Patent ID: 7288809

Claim:
A flash memory array comprising: a plurality of floating gates arrayed in rows and columns, said floating gates formed at least in part within a silicon substrate; a control gate coupling floating gates and functioning as a word line; and a plurality of bit lines, each bit line of said plurality of bit lines essentially perpendicular to said word line, wherein all parts of said bit lines are completely buried within said substrate and all surfaces of said bit lines are completely surrounded by said substrate, said each bit line having an L-shaped cross-section comprising a first portion and a second portion that is essentially at a right angle to said first portion, wherein a first portion of a first bit line is essentially parallel to a first portion of a second bit line, wherein said first portion of said first bit line and said first portion of said second bit line lie in different planes, and wherein further a second portion of said first bit line and a second portion of said second bit line lie in essentially the same plane.