Patent ID: 7073105

Claim:
An array built-in, on-chip self test system for testing a memory array having data input ports, data output ports, and address ports, comprising in combination: a data control subsystem for generating and applying deterministic data patterns to the data input ports of said memory array; an address control subsystem for generating addresses for application to said memory array in coordination with said data control subsystem, said address control subsystem comprising, in combination: a. a count controller for the sequence counters, b. a count rate controller divider to control the number of cycles per address, c. an address increment/address decrement controller, and d. an address controller with X-OR gates receiving inputs from the address increment/decrement control and a gated control source register with multiple enable signals, to provide granular control of addresses, and e. X-OR gate outputting an address bit to the memory array; and a comparator for comparison of data inputted to said data input ports of said memory array from said data control subsystem with data outputted from said data output ports of said memory array.