Patent ID: 6847573

Claim:
A synchronous SRAM-compatible memory having a DRAM array with a plurality of DRAM cells arranged in a matrix from defined by rows and columns, and interfacing with an external system for providing a row address and a column address, the DRAM cells requiring a refresh operation at selected intervals to maintain data stored therein, comprising: a data input/output unit for controlling input and output of data to/from the DRAM array; an address input unit for inputting a row address and a column address of a current frame in synchronization with an external clock signal when an effective address signal is activated; a burst address generating unit for generating a burst address sequentially varying with respect to the column address in synchronization with the external clock signal; a state control unit for generating a burst enable signal that enables the burst address generating unit, controlling the data input/output unit, and generating a wait indication signal of a first logic state while an access operation of a previous frame is performed with respect to the DRAM array, the access operation of the previous frame including a write access operation or a refresh operation before the effective address signal of the current frame is activated; a refresh timer for generating a refresh request signal activated at selected intervals; and a refresh control unit for controlling the refresh operation with respect to the DRAM array in response to the refresh request signal, the refresh operation being performed after completion of a burst access operation ongoing with respect to the DRAM memory array.