Patent ID: 7109554

Claim:
A thin film semiconductor device comprising: an N-channel MOS transistor comprising a first region of a polycrystalline silicon layer which is formed on an insulation substrate and into which a first conductivity type of an impurity is implanted, said first region of said polycrystalline silicon layer serving as an activation layer; and a P-channel MOS transistor comprising a second region of said polycrystalline silicon layer which is formed on said insulation substrate and into which a second conductivity type of an impurity is implanted, said second region of said polycrystalline silicon layer serving as an activation layer; wherein a first gate electrode is formed via a first gate insulating film on said polycrystalline silicon layer in said N-channel MOS transistor, said first gate electrode comprising an N-type of polysilicon; wherein a second gate electrode is formed via said second gate insulating film on said polycrystalline silicon layer in said P-channel MOS transistor, said second gate electrode comprising a P-type of polysilicon; and wherein said polycrystalline layer is formed such that a thickness thereof is smaller than a virtual width of a depletion layer at a time of forming channel inversion, the virtual width of the depletion layer being equal to a distance to which the depletion layer can reach, assuming that said polycrystalline silicon has an adequate thickness.