Patent ID: 7865164

Claim:
A mixing apparatus comprising: a mixing core comprising one or more mixing core outputs, the mixing core being configured to receive one or more phases of a radio frequency (RF) signal at RF frequency, receive one or more phases of a local oscillator (LO) signal, mix the RF signal with the LO signal to obtain an intermediate frequency (IF) signal at IF frequency, the IF signal being the RF signal downconverted using the LO signal, and output the one or more phases of the IF signal through the one or more mixing core outputs, one phase of the IF signal per mixing core output; a current buffer comprising one or more current buffer inputs and one or more current buffer outputs, one current buffer input per phase of the IF signal, one current buffer output per phase of the IF signal, each current buffer input presenting no more than a first input impedance, each current buffer output presenting at least a first output impedance, the first output impedance being greater than the first input impedance; and a transimpedance amplifier (TIA) comprising one or more TIA inputs and one or more TIA outputs, one TIA input per phase of the IF signal, one TIA output per phase of the IF signal, wherein: for each phase of the IF signal, the mixing core output corresponding to said each phase of the IF signal is coupled to the current buffer input corresponding to said each phase of the IF signal, the current buffer output corresponding to said each phase of the IF signal is coupled to the TIA input corresponding to said each phase of the IF signal, so that said each phase of the IF signal output by the mixing core is buffered in the current buffer and processed in the transimpedance amplifier; the one or more phases of the IF signal comprise at least a first IF phase and a second IF phase, the current buffer comprises a first Complimentary Metal Oxide Semiconductor (CMOS) common-gate device between the current buffer input corresponding to the first IF phase and the current buffer output corresponding to the first IF phase, the current buffer further comprises a second CMOS common-gate device between the current buffer input corresponding to the second IF phase and the current buffer output corresponding to the second IF phase; the first CMOS common-gate device comprises a first bulk node, a first source node, a first gate node, and a first drain node; the second CMOS common-gate device comprises a second bulk node, a second source node, a second gate node, and a second drain node; the first bulk node is connected to the second source node; and the second bulk node is coupled to the first source node.