Patent ID: 7336533

Claim:
An electronic device comprising: a full pass gate controllable by a write control line and a complimentary write control line, the full pass gate comprising: a first semiconductor transistor comprising a first electrode coupled to a first node of the bit cell, a second electrode coupled to a write bit line, and control electrode coupled to the write control line; and a second semiconductor transistor comprising a first electrode coupled to the first node of the bit cell, a second electrode coupled to the write bit line, and a control electrode coupled to the complementary write control line; a bit cell operably coupled to the full pass gate comprising a first node configured to receive a signal via the full pass gate and store the signal during a write phase to a write control signal; and a read control line separate from the write control line, configured to control a read phase wherein the signal is read from the bit cell during the read phase; and wherein a voltage drop across the first semiconductor transistor is less than one-half of voltage threshold of a transistor of the pass gate when the first semiconductor transistor is forward biased.