Patent ID: 7312126

Claim:
A process for producing a layer arrangement, comprising the steps of: forming a porous silicon layer as a sacrificial layer on an auxiliary substrate; forming a first semiconductor layer on the sacrificial layer; forming a first electrically insulating layer on the first semiconductor layer; forming an electrically conductive layer on the first electrically insulating layer, wherein the electrically conductive layer is laterally patterned; wherein the first electrically insulating layer, the sacrificial layer, and the first semiconductor layer are jointly patterned laterally using the laterally patterned electrically conductive layer as a mask; forming a semiconductor structure adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer; securing a substrate over the patterned electrically conductive layer; removing material of the auxiliary substrate, so that the sacrificial layer is uncovered; selectively removing the sacrificial layer, so as to form a trench; and forming a second electrically insulating layer in the trench, and forming an electrically conductive structure on this second electrically insulating layer.