Patent ID: 7256143

Claim:
A semiconductor device comprising: a plurality of conductive patterns, each conductive pattern including a conductive layer and a capping layer stacked on an insulating layer disposed on a semiconductor substrate; a first interlayer insulating layer filling at least one space between at least two adjacent conductive patterns and having a height whereby when disposed on the insulating layer, a top surface of the first interlayer insulating layer is lower than a top surface of the capping layer and higher than a top surface of the conductive layer; a first spacer disposed on the first interlayer insulating layer and surrounding an outer surface of the capping layer; a second interlayer insulating layer covering the first interlayer insulating layer, the capping layer, and the first spacer and having a planarized top surface; and a contact plug passing through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer, wherein the contact plug is positioned between the at least two conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.