Patent ID: 8030134

Claim:
A stacked semiconductor assembly comprising: a first die having a first surface bounded by a periphery around bond pads at the first surface; wires spaced apart and extending generally in parallel bonded to and extending from the bond pads outwardly past the periphery, the wires extending to a maximum height h above the first die; a package, comprising a package die mounted over and electrically interconnected with a die attach surface of a package substrate, the package having an electrically non-conductive second surface positioned opposite the die attach surface; the first die and the package defining a first region therebetween; a wire span portion of the first region formed by said wires comprising a set of generally parallel wires includes said wires parallel with and adjacent to the second surface of the package in the wire span portion of the first region, the wires configured to act as a sieve for spacer elements within a flowable adhesive in the wire span portion; an adhesive/spacer structure within the first region, the adhesive/spacer structure contacting the first and second surfaces and adhering the first die and the package to one another, the adhesive/spacer structure comprising the spacer elements sized for preventing incursion between the parallel wires with the spacer elements within the flowable adhesive, the adhesive/spacer structure extending around at least two sides of the wire span portion; and a molding compound.