Patent ID: 8242818

Claim:
A frequency synthesizer, comprising: a first phase-locked loop having a first loop bandwidth, the first phase-locked loop configured to receive a source signal having a tunable frequency f IN and to generate a reference signal having a frequency f REF that is M times the tunable frequency f IN of the source signal; and a second phase-locked loop having a second loop bandwidth and being in communication with the first phase-locked loop to receive the reference signal, the second phase-locked loop generating an output signal having a frequency f OUT that is N times the frequency f REF of the reference signal, wherein the first loop bandwidth is less than the second loop bandwidth, the second phase lock loop comprising: a phase-frequency detector to receive the reference signal and a divided output signal, and to generate a control signal responsive to a difference in the frequency f REF of the reference signal and a frequency f OUT N of the divided output signal wherein N is a divider value; a charge pump in communication with the phase-frequency detector and configured to generate a voltage signal responsive to the control signal; a filter in communication with the charge pump to filter the voltage signal according to the second loop bandwidth; and a main voltage controlled oscillator (VCO) in communication with the filter, the main VCO generating the output signal in response to the filtered voltage signal, wherein the frequency f OUT of the output signal is responsive to a difference in the frequency f REF of the reference signal and the frequency f OUT N of the divided output signal and wherein the main VCO comprises a first path having a first VCO in serial communication with a first prescaler and a second path having a second VCO in serial communication with a second prescaler, the first and second VCOs having different operating frequency ranges and the first and second prescalers each having at least one divider value, wherein the frequency f OUT of the output signal is determined by a selection of one of the paths and a divider value for the prescaler in the selected path.