Patent ID: 8514632

Claim:
A semiconductor memory, comprising: a plurality of nonvolatile memory cells being arranged in a matrix and including memory transistors which are electrically rewritable and selection transistors coupled to the respective memory transistors; a plurality of control gate lines each coupled to a row of the memory cells aligned in a first direction; a plurality of selection gate lines each coupled to the row of the memory cells aligned in the first direction; a plurality of source lines each coupled to the row of the memory cells aligned in the first direction; a plurality of bit lines each coupled to a column of the selection transistors aligned in a second direction intersecting the first direction; a control gate line driver setting one of the control gate lines coupled to the row of the memory cells including a program memory cell where data are programmed to a first high level voltage, and setting at least one of the remaining control gate lines coupled to the row of non-program memory cells where data are not programmed to a low level voltage, at a time of program operation; a selection gate line driver setting one of the selection gate lines coupled to the row of the memory cells including the program memory cell to a second high level voltage, and setting at least one of the remaining selection gate lines coupled to the row of the non-program memory cells to a low level voltage, at the time of program operation; a bit line control unit setting one of the bit lines coupled to the selection transistors of the column of the memory cells including the program memory cell to a low level voltage, and setting at least one of the remaining bit lines coupled to the selection transistors of the column of the non-program memory cells to a floating state, at the time of program operation; and a plurality of source line drivers coupled to each of the source lines and each including a first transistor coupling one of the source lines to a high level voltage line having a third high level voltage and a second transistor coupling the one of the source lines to a low level voltage line; one of the source line drivers corresponding to the row of the memory cells including the program memory cell turns-on the first transistor and turns-off the second transistor, at the time of program operation; and at least one of the remaining source line drivers corresponding to the row of the non-program memory cells turns-off the first and the second transistors, at the time of the program operation.