Patent ID: 6944253

Claim:
A circuit for generating a cipher stream, the circuit comprising: a first and a second plurality of linear feedback shift registers (LFSR), each LFSR of the first of the second plurality of LFSR having an initial value of not all zero bits; a first of the second plurality of LFSR having a clock signal as a clock input and others of the second plurality of LFSR each having an output of a previous one of the second plurality of LFSR as a clock input; a first of the first plurality of LFSR having the clock signal combined with an output of the first of the second plurality of LFSR as a clock input and others of the first plurality of LFSR each having an output of a corresponding one of the others of the second plurality of LSFR combined with an output of a previous one of the first plurality of LFSR as a clock input; and an output of a last of the first plurality of LFSR and an output of a last of the second plurality of LFSR being combined to produce the cipher stream.