Patent ID: 7679118

Claim:
A memory cell, comprising: a pillar of semiconductor material extending from a general plane of a substrate, the pillar including a plurality of sides; a first source/drain region formed in the substrate and coupled to a bit line implanted in the substrate, wherein the bit line is at least partially offset from the pillar in a direction lateral to the bit line, wherein at least a portion of the bit line extends beyond an outer edge of one side of the pillar, and wherein at least a portion of another side of the pillar extends beyond an edge of the bit line; an access transistor including a body region and a second source/drain region both formed within the pillar, the access transistor further including the first source/drain region; and a first gate on a first side of the pillar and an independent second gate on a second side of the pillar, the first and second gates being differently activated by separate and different activation voltages.