Patent ID: 7558134

Claim:
A semiconductor memory device comprising: a memory-cell array including memory cells laid out to form an array; a read bit line shared by a plurality of said specific memory cells arranged in one direction in said memory-cell array and connected to a data output node of each of said specific memory cells; a write bit line shared by a plurality of said specific memory cells and connected to a data input node of each of said specific memory cells; a sense amplifier configured to sense a difference in electric potential between said read bit line and said write bit line; a first sense line connected to one of said input terminals of said sense amplifier; a second sense line connected to the other input terminal of said sense amplifier; a first bit line switch configured to control electrical connection and disconnection between said first sense line and said read bit line; and a second bit line switch configured to control electrical connection and disconnection between said second sense line and said write bit line.