Patent ID: 7705457

Claim:
A wafer level semiconductor package, comprising: a semiconductor chip having a circuit part; a bonding pad group disposed at the semiconductor chip, the bonding pad group including a power pad electrically connected to the circuit part, wherein the power pad provides power to the semiconductor chip; an internal circuit pattern disposed in the semiconductor chip at a position outside of the position occupied by the bonding pad group and providing power to the circuit part; an additional power pad disposed in the semiconductor chip at a position outside of the position occupied by the bonding pad group, the additional power pad being electrically connected to and providing power to the circuit part; an insulation layer pattern disposed over the semiconductor chip, the insulation layer having openings exposing the power pad, the internal circuit pattern, and the additional power pad; and a redistribution disposed over the insulation layer pattern and extending laterally so as to provide an electrical connection between at least two of the power pad, the internal circuit pattern, and the additional power pad.