Patent ID: 8849643

Claim:
A method for statistically evaluating a design of an integrated circuit, the method comprising: simulating the integrated circuit; and generating a lookup table for use in the simulating, the lookup table comprising one or more blocks, wherein each of the one or more blocks specifies a device element for an associated bias voltage, wherein the generating comprises generating only those of the one or more blocks that specify the device element for the bias voltage that is required during the simulating, wherein the generating comprises: identifying a first one of the one or more blocks that contains a bias point associated with the bias voltage that is required during the simulating; creating a spline function in accordance with data contained in the first one of the one or more blocks, when the spline function has not been previously created; and performing a spline evaluation in accordance with the spline function, wherein at least one of: the simulating or the generating is performed using a processor.