Patent ID: 7808471

Claim:
A scan driving circuit, comprising: an input terminal to receive an input signal or a voltage output from a previous stage; a first clock terminal and a second clock terminal to receive first and second clock signals having phases inverted to each other and partially overlap at a high level, respectively; and a plurality of stages having output terminals to output scan signals having a low level in sequence, leaving an interval between the scan signals equivalent to a time the first and second clock signals overlap at the high level, wherein an output terminal of each stage is maintained to have a non-floating state regardless of whether the stage outputs the scan signal, and wherein each stage includes: a first transistor receiving the voltage output from the previous stage or an initial input signal, and having a gate terminal connected to the first clock terminal, a second transistor having a gate terminal connected to an output terminal of the first transistor, the second transistor having input and output terminals connected to the second clock terminal and an output line, a third transistor having a gate terminal connected to the first clock terminal, the third transistor having an output connected to a first node and an input connected to a second power source or to the first clock terminal, a fourth transistor having a gate terminal connected to the output terminal of the first transistor, the fourth transistor having input and output terminals connected to the first clock terminal and the first node, and a fifth transistor having a gate terminal connected to the first node, the fifth transistor having input and output terminals connected to a first power source and the output line.