Patent ID: 6970966

Claim:
An interface between a microprocessor, or a local bus, and user macro-cells, being a macro-cell a self-consistent and pre-verified set of logic elements, generally designed with Hardware Description Languages, and transposed into silicon devices, the interface including a unique module connected between an external bus corresponding to the bus of said microprocessor, or being the local bus, and the remaining part of the interface, via an internal bus of the interface, said remaining part of the interface including peripheral resources, connected to the internal bus, named hereinafter common bus, and controlled by the unique module, named hereinafter main module, for the execution of read/write commands of the microprocessor towards a selected peripheral resource, wherein said peripheral resources are clustered in standardizable peripheral modules located externally to the interfaced macro-cells and connected to the macro-cells through point-to-point buses, being each peripheral module in its turn constituted of a pre-defined set of hardware and firmware resources comprehensive of the most popular needs in interfacing user macro-cells, including: configuration registers, command registers, status registers, not prefetchable registers for trapping events signalled by macro-cells, event counter registers, register synchronizers, dual port memories and FIFO either synchronous or asynchronous with respect to the clock that synchronizes the macro-cells.