Patent ID: 8484599

Claim:
A method for performing parasitic extraction, the method comprising: identifying a via array in a physical layout, wherein the via array is coupled between a first layer and second layer; and in response to determining that the via array is a single row or column via array having at least four vias, a computer performing the following operations: identifying a first via and a last via in the via array, merging a set of vias between the first via and the last via into a center via, wherein said merging involves replacing a first set of contacts associated with the set of vias in the first layer with a first node of the center via, and replacing a second set of contacts associated with the set of vias in the second layer with a second node of the center via, and extracting a first via resistance, a last via resistance, and a center via resistance for the first via, the last via, and the center via, respectively.