Patent ID: 7171638

Claim:
A method comprising steps of: (a) receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die; (b) generating a test matrix from the quiescent current measurements for each die in the sample lot; (c) computing a de-mixing matrix from independent component analysis that models passing die in the sample lot; (d) generating a matrix of sources as a product of the test matrix and the de-mixing matrix; (e) normalizing the matrix of sources to zero mean and unit variance; (f) selecting a statistical limit of the passing die in the sample lot from each of the sources in the normalized matrix of sources to determine a maximum and a minimum quiescent current value limit for each of the sources; (g) generating as output the maximum and the minimum quiescent current value limit for each of the sources; and (h) screening defective die that lie outside the maximum and the minimum quiescent current value limit for each of the sources.