Patent ID: 6950922

Claim:
A data extraction method in a digital signal processor, wherein the digital signal processor includes a source register and a destination register, and extracting data from the source register and storing the extracted data in the destination register using a position value, the position value representing the reference position of data extraction, and an offset value, the offset value representing the size of data to be extracted, the data extraction method comprising: (a) storing the data of an M-th memory block in a memory having a plurality of N-bit memory blocks, into an upper portion of the source register, and storing the data of an (M+1)th memory block into a lower portion of the source register, wherein M and N are natural numbers; (b) extracting data of the size corresponding to the offset value, from the position corresponding to the position value in the source register, storing the extracted data in the destination register, and summing the position value and the offset value to obtain a new position value; (c) determining whether the new position value is greater than a predetermined modulo value, generating a flag signal in a first logic level if the new position value is smaller than the modulo value, and generating a flag signal in a second logic level if the new position value is greater than the modulo value; (d) repeating steps (b) and (c) using the new position value if the flag signal has a first logic level, and storing the data of the lower portion of the source register in the upper portion of the source register if the flag signal is in a second logic level; and (e) storing the data of an (M+2)th memory block of the memory in the lower portion of the source register in response to the flag signal in the second logic level, setting a next position value by the difference between the new position value and the modulo value, and going back to step (b).