Patent ID: 8860148

Claim:
A semiconductor structure, comprising: a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate, wherein the STI feature includes a first portion disposed in the first region and having a first thickness T 1 and a second portion disposed in the second region and having a second thickness T 2 greater than the first thickness T 1 , the first portion of the STI feature being recessed from the second portion of the STI feature; a plurality of fin active regions on the semiconductor substrate; a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region and a portion of the second portion of the STI feature in the second region; a plurality of dielectric features underlying the conductive features and separating the conductive feature from the fin active regions; a first transistor disposed in the first region, wherein the first transistor comprises a first gate stack having a first one of the dielectric features and a first one of the conductive features overlying the first one of the dielectric features; and a second transistor disposed in the second region, wherein the second transistor comprises a second gate stack having a second one of the dielectric features and a second one of the conductive features overlying the second one of the dielectric features, wherein the first one of the dielectric features has a first dielectric thickness, and the second one of the dielectric features has a second dielectric thickness different from the first dielectric thickness.