Patent ID: 7329548

Claim:
A method of fabricating a conductive metal oxide gate ferroelectric memory transistor comprising: preparing a substrate; forming an oxide layer on the substrate; removing the oxide layer in a gate area to expose a gate area; depositing an indium oxide layer on the oxide layer and on the exposed gate area to a thickness of between about 10 nm to 100 nm by DC sputtering using an indium target at a DC sputtering power of between about 200 W to 300 W, at an oxygen partial pressure of between about 20% to 60%, at a substrate temperature of between about 100° C. to 200° C., and annealing the substrate and indium oxide layer at a temperature of between about 400° C. to 800° C. for between about five minutes to two hours; depositing a titanium layer on the indium oxide layer; patterning and etching the titanium layer and the indium oxide layer to remove the titanium layer and the indium oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing a top electrode; patterning and etching the top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.