Patent ID: 8400834

Claim:
A system, comprising: an interface on a NAND Flash memory controller configured to perform an erase operation on a NAND Flash memory chip including to a first cell on the NAND Flash memory chip, wherein: the first cell is configured to store a first number of bits; the NAND Flash memory chip further includes a second cell which is configured to store the first number of bits; and the first cell and the second cell are in a same block on the NAND Flash memory chip; and a processor on the NAND Flash memory controller configured to: determine whether the erase operation performed on the NAND Flash memory chip is successful, including by determining whether (1) the first cell and the second cell are both successfully erased, (2) one of the first cell and the second cell is successfully erased and the other one is unsuccessfully erased or (3) the first cell and the second cell are both unsuccessfully erased, wherein: in the event it is determined that (1) the first cell and the second cell are both successfully erased or (2) one of the first cell and the second cell is successfully erased and the other one is unsuccessfully erased, it is determined that the erase operation performed on the NAND Flash memory chip is successful; and in the event it is determined that (3) the first cell and the second cell are both unsuccessfully erased, it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful; and in the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful: reduce the number of bits stored by the first cell from the first number of bits to a second number of bits, wherein the second number of bits is strictly less than the first number of bits; and reduce the number of bits stored by the second cell from the first number of bits to the second number of bits.