Patent ID: 7343575

Claim:
A method for performing functional verification on an original circuit design, the method comprising: generating a series of phase-adjusted register state vectors for a set of original registers in the original circuit design, the series of phase-adjusted register state vectors including a different phase-adjusted state register vector for each of a first quantity of phases for the original circuit design; unwinding the original circuit design to generate an unwound design; imposing the state bit values from the series of phase-adjusted register state vectors on the unwound design; generating a phase-abstracted design by performing logic rewriting on the unwound design to propagate the state bit values through the unwound design; and performing functional verification on the phase-abstracted design, wherein unwinding the original circuit design comprises: duplicating the original circuit design by the first quantity to generate a plurality of duplicate logic sets; and connecting the plurality of duplicate logic sets in series by replacing registers in adjacent duplicate logic sets with direct connections to adjacent duplicate logic sets.