Patent ID: 8603906

Claim:
A method of forming a three-dimensional semiconductor memory device comprising: preparing a substrate comprising a pair of sub-cell regions and a strapping region between the pair of sub-cell regions; alternately forming sacrificial layers and dielectric layers on the substrate; patterning the dielectric layers and the sacrificial layers within the strapping region to form substantially symmetrical terraced structures in the strapping regions; forming a capping insulating layer covering the terraced structures of the sacrificial layers and dielectric layers; removing the sacrificial layers having the terraced structures to form empty regions; forming sub-gates in the empty regions, respectively, the sub-gates including a plurality of sub-gates stacked on the substrate in each of the pair of sub-cell regions, and each of the sub-gates including an extension extending laterally into the strapping region; and forming strapping lines electrically connected to the extensions of the stacked sub-gates, respectively; wherein each of the strapping lines is electrically connected to the extensions of sub-gates located at the same level and disposed in the pair of sub-cell regions, respectively; and wherein the strapping lines are not electrically connected to a top surface of the substrate in the strapping region.