Patent ID: 7940595

Claim:
A power up detection system comprising: a first row of memory cells storing a first predetermined data word, each memory cell of the first row of memory cells being connected to corresponding bitlines; a second row of memory cells storing a second predetermined data word, each memory cell of the second row of memory cells being connected to the corresponding bitlines, and the second predetermined data word being a single bit shifted first predetermined data word; sense amplifiers coupled to the corresponding bitlines for sensing a first read word from the first row of memory cells in a first read operation and for sensing a second read word from the second row of memory cells in a second read operation; a serial data register for receiving the first read word into first latches and for shifting the first read word into second latches in the first read operation, the serial data register receiving the second read word into the first latches; and a data comparison logic for comparing data between the first latches and the second latches, and for providing a signal indicating matching data between the first latches and the second latches.