Patent ID: 7902899

Claim:
An apparatus for generating a reference clock for a DLL circuit, the apparatus comprising: a buffering unit configured to buffer a positive external clock and a negative external clock to generate a first reference clock and a second reference clock independent to each other, to invert the second reference clock to generate a negative second reference clock, and to output the first reference clock and the negative second reference clock independent to each other; and a duty cycle compensating unit configured to receive the first reference clock and the negative second reference clock and mix the first reference clock and the negative second reference clock to generate a reference clock, wherein the buffering unit is configured to receive the positive external clock and the negative external clock and output the first reference clock that has a same phase as a phase of the positive external clock, and receive the positive external clock and the negative external clock and output the second reference clock that has a same phase as a phase of the negative external clock.