Patent ID: 7936630

Claim:
A memory arrangement comprising: a memory block comprising a plurality of memory cells, each memory cell operable to store one of a plurality of different levels of charge; a channel; and a controller coupled to the memory block via the channel, the controller to write (i) a first reference signal threshold into a first memory cell of the plurality of memory cells and (ii) a second reference signal threshold into a second memory cell of the plurality of memory cells, the first reference signal threshold corresponding a first level of charge of the plurality of different levels of charge, the second reference signal threshold corresponding a second level of charge of the plurality of different levels of charge, the second level of charge being different than the first level of charge, wherein each of the first level of charge and the second level of charge for calibrating the channel during read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.