Patent ID: 8792274

Claim:
A system comprising: an array of a plurality of cells; a first module configured to read a state of a cell of the plurality of cells in the array to detect a first plurality of bits of data stored in the cell of the plurality of cells; a second module configured to generate a plurality of signal inputs, wherein the plurality of signal inputs indicate a second plurality of bits of data to be stored in the cell of the plurality of cells; and a third module configured to, subsequent to the first module reading the state of the cell of the plurality of cells, determine a value of a least significant bit of the second plurality of bits, based on the value of the least significant bit of the second plurality of bits, set a first transistor in a first state to enable an output of a first logic device to match the least significant bit, perform a first operation, via the first logic device, on (i) a first bit of the first plurality of bits of data stored in the cell of the plurality of cells, and (ii) a first signal input of the plurality of signal inputs, determine a value of a most significant bit of the second plurality of bits, based on the most significant bit of the second plurality of bits, set a second transistor in a second state to enable an output of a second logic device to match the most significant bit, and perform a second operation, via the second logic device, on (i) a second bit of the first plurality of bits of data stored in the cell of the plurality of cells, and (ii) a second signal input of the plurality of signal inputs, wherein the first module is configured to, based on results of the first operation and the second operation, perform a first erase operation on the cell of the plurality of cells or perform a first program operation on the cell of the plurality of cells to match the state of the cell of the plurality of cells to the second plurality of bits of data.