Patent ID: 6996736

Claim:
A clock network for an integrated circuit comprising: a first set of lines configured to distribute clock signals to a first section of the integrated circuit; a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit; a third set of lines configured to distribute clock signals to both the first and second sections of the integrated circuit, wherein the third set of lines connects with the second set of lines in the second section of the integrated circuit; at least one line disposed in the first section connected directly to an input/output (I/O) of the integrated circuit, wherein the at least one line is configured to distribute a clock signal received from the I/O to the first section; and at least one line disposed in the second section connected directly to an I/O of the integrated circuit, wherein the at least one line is configured to distribute a clock signal received from the I/O to the second section.