Patent ID: 8219782

Claim:
An address generator, comprising: a first processing unit coupled to a second processing unit, wherein the first processing unit is configured to generate a stage output and the second processing unit is configured to generate an address output; the first processing unit comprising: a first adder, the output of which is connected to a first input of a subtractor, the output of which is the stage output, and the stage output is fed back to the first adder, and either a null value or a block size K is selectively forwarded to a second input of the subtractor, and wherein the stage output is in a first range from −K to −1 for a block size K; and the second processing unit comprising: a second adder, the output of which is connected to a first input of a third adder, the output of which is the address output, wherein the second processing unit receives the stage output from the first processing unit and generates the address output, and wherein the address output is fed back to the second adder, and either a null value or a block size K is selectively forwarded to a second input of the third adder, and wherein the address output is in a second range from 0 to K−1.