Patent ID: 8780093

Claim:
A display comprising: a first timing controller comprising a first transmitter connected to a first bus, for sending first pixel data through the first bus at a first clock rate; a second timing controller comprising a second transmitter connected to a second bus at the first clock rate, for sending second pixel data through the second bus, wherein each of the first pixel data and the second pixel data corresponds to a pixel value of a pixel of the display, and each of the first pixel data and the second pixel data comprises a plurality of bits; and a source driver comprising a receiver and plural channels, the receiver being connected to the first bus and the second bus, for receiving the first pixel data and the second pixel data, and reorganizing the first pixel data and the second pixel data to generate third pixel data, based on a bus mode, for the channels, wherein while the bus mode is a third mode, the receiver is configured to reorganize the first pixel data and the second pixel data by alternatively selecting two successively transmitted first pixel data of the first pixel data sent through the first bus and selecting two successively transmitted second pixel data of the second pixel data sent through the second bus to be outputted as the third pixel data, wherein the two successively transmitted first pixel data are followed by the two successively transmitted second pixel data, and the receiver outputs the third pixel data at a second clock rate twice the first clock rate.