Patent ID: 7761673

Claim:
A computer system for compiler assisted victim cache bypassing, the system comprising: a processor; a main cache operatively coupled to the processor a victim cache operatively coupled to the processor and configured to receive instructions evicted from the main cache due to at least one of a conflict and a capacity miss, wherein the processor is configured for: identifying a cache line as a candidate for victim cache bypassing; conveying a bypassing-the-victim-cache information to a hardware by one of the following: adding a special bit to load/store instructions, indicating whether or not the corresponding line should bypass the victim cache, wherein the special bit can be saved in a main cache tag array or a special table that stores the address of lines that bypass the victim cache; encoding the special bit is encoded into page table entries and passing the special bit from an effective-to-physical address translation hardware to main cache; conveying bypassing-the-victim-cache information to hardware by extending a prefetch engine to explicitly request the main cache to flush lines that identified by the compiler that have no temporal locality; and conveying bypassing-the-victim-cache information to the hardware via a small bypass table attached to main cache, the bypass table including a starting address and a length of memory regions that should bypass the victim cache, wherein a special LS (Load-Store) instruction is implemented to write the starting address and the length of each of the regions of the memory to the bypass table before the region is accessed; and checking a state of the cache line to determine a modified state of the cache line, wherein the cache line is identified for victim cache bypassing if the cache line that has no reuse within a loop or loop nest and there is no immediate loop reuse or there is a substantial across loop reuse distance so that it will be replaced from both main and victim cache before being reused, wherein the loop reuse is at least one of temporal reuse in which there are multiple accesses to a same memory location, and spatial reuse in which there are accesses to nearby memory locations that share at least one of a cache lines and a block of memory at a level of a memory hierarchy.