Patent ID: 6928024

Claim:
A RAM memory circuit, comprising: at least one memory bank divided into q≧2 areas and having a multiplicity of memory cells in a matrix of rows and columns, a set of said columns of each area being subdivided into p≧2 disjoint subsets each defining a segment; a dedicated area bus for each area a and a bundle of m≧1 master data lines for each said segment of each area, said bundle branching from the respective said area bus and being connectible via a line network, controlled by address information, to individually addressed groups of m memory cells each within a respective said segment; a data port and an area multiplexer for cyclically connecting said area buses to said data port, said data port having m external terminals for inputting and outputting the data groups to be written in or read out at the addressed said memory cell groups; delay or holding devices for simultaneously providing in each case q successive data groups on said q area buses; a control device having a control input for receiving a clock signal and being configured to control a write and read operation under an influence of the clock signal and applied address information and command information; a data latch coupled to each said master data line bundle for holding a data group respectively appearing at said master data line bundle; and an isolating switch between each master data line bundle and the assigned said area bus, said isolating switch being connected to and controlled by said control device, for temporarily decoupling said master data line bundle from the respective said area bus.