Patent ID: 7512200

Claim:
A digital system comprising: a master circuit, which includes a circuit to detect clock delay, receives a system reset signal, and generates output data, an output clock signal with which the output data is synchronized, and a reset control signal which responds to the system reset signal; and a slave circuit in signal communication with the master circuit, where the slave circuit is reset in response to the reset control signal using the system reset signal that is generated outside of the master circuit and the slave circuit, receives the output clock signal and the output data, and sends to the master circuit an input clock signal as a feedback signal of the output clock signal and input data that is synchronized with the input clock signal, wherein the circuit to detect clock delay generates the reset control signal in response to the system reset signal or an internal reset signal, detects a delay between the output clock signal and the input clock signal, and loads and unloads the input data in response to a variable initialization parameter corresponding to the detected delay.