Patent ID: 7678713

Claim:
A method for manufacturing an integrated circuit, comprising: providing a substrate having an active die area and a bond pad area; forming transistor structures over the active die area of the substrate; forming at least one dielectric layer having a dielectric constant lower than that of silicon dioxide over the transistor structures in the active die area and over the substrate in the bond pad area, the at least one dielectric layer having a hardness and a modulus of elasticity; masking off at least a portion of the at least one dielectric layer over the transistor structures in the active die area, while exposing at least a portion of the at least one dielectric layer over the substrate in the bond pad area; and subjecting the masked off and exposed portions of the at least one dielectric layer to an energy beam treatment to cause the hardness or modulus of elasticity of the exposed portion to increase in value, while maintaining the dielectric constant lower than that of silicon dioxide in the masked off portion.