Patent ID: 8395198

Claim:
A semiconductor device comprising: a semiconductor substrate including first, second and third portions; the first and second portions being partitioned by a cell gate trench having a bottom surface, a first side surface located on the first portion side, and a second side surface located on the second portion side, the first and third portions being partitioned by a first field-shield gate trench exposing a third side surface located on the first portion side and a fourth side surface located on the third portion side, and a distance between the third and fourth surfaces being narrower than a distance between the first and second surfaces, a first upper diffusion layer that is provided on an upper part of the first portion of the semiconductor substrate; a second upper diffusion layer that is provided on an upper part of the second portion of the semiconductor substrate; a third upper diffusion layer that is provided on an upper part of the third portion of the semiconductor substrate; a lower diffusion layer that is provided in the bottom surface of the cell gate trench; a first and a second storage element that are electrically connected to the first and second upper diffusion layers, respectively; a bit line that is electrically connected to the lower diffusion layer; a first and a second cell gate electrode that cover the first and second side surfaces, respectively, via a gate insulating film; and a first field-shield gate electrode that is embedded in the first field-shield gate trench via a gate insulating film.