Patent ID: 8030971

Claim:
A logic gate comprising: at least first and second input terminals; an output terminal; a voltage supply terminal; a ground terminal; a first portion, said first portion comprising at least one multi-gate field effect transistor (FET) of a first type, said first type being one of a p-type and an n-type, wherein one of said at least one multi-gate FET of said first type has at least a first gate electrically interconnected to said first input terminal and a second gate electrically interconnected to said second input terminal, said first portion being configured to electrically interconnect said output terminal with one of said voltage supply terminal and said ground terminal upon activation via at least one of said first and second input terminals; and a second portion, said second portion in turn comprising at least one multi-gate FET of a second type, said second type being one of said p-type and said n-type and being different than said first type, said at least one multi-gate FET of said second type having at least a first gate electrically interconnected to said first input terminal and a second gate electrically interconnected to said second input terminal, said at least one multi-gate FET of said second type forming at least a part of a path between said output terminal and another one of said voltage supply terminal and said ground terminal, wherein said part of said path is configured to conduct, in a logical sense, only upon activation of both said first and second gates via both said first and second input terminals.