Patent ID: 8669552

Claim:
A thin film transistor, comprising: a gate electrode disposed above a substrate; a gate dielectric layer disposed over the gate electrode; a channel semiconductor layer disposed over the gate dielectric layer; a first electrode disposed over the channel semiconductor layer and at least partially defining a via; a second electrode disposed over the channel semiconductor layer, within the via and extending over at least a portion of the first electrode; a first dielectric layer disposed over the first electrode; a second dielectric layer disposed over the first dielectric layer, wherein the first electrode, the first dielectric layer and the second dielectric layer are shaped to have a via formed therethrough to expose the channel semiconductor layer, wherein the via is bordered by edges of the first electrode, the first dielectric layer, the second dielectric layer and the channel semiconductor layer; a spacer layer disposed on the edges of the first electrode, the first dielectric layer, the second dielectric layer and the exposed channel semiconductor layer; a first control semiconductor layer disposed over the channel semiconductor layer and the spacer layer; and a second control semiconductor layer disposed over the first control semiconductor layer.