Patent ID: 7601570

Claim:
A method for producing a microelectronic device, comprising one or more Si 1−z Ge z based semiconductor wire(s) (with 0<z≦1), said method comprising: a) thermal oxidation of at least a portion of a Si 1−x Ge x -based semiconductor layer (with 0<x<1) resting on a support, so as to form at least one Si 1−y Ge y -based semiconductor zone (with 0<y<1 and x<y), and b) lateral thermal oxidation of the sides of one or more so-called semiconductor “connection” blocks from said Si 1−y Ge y -based semiconductor zone and connecting a semiconductor block intended to form a transistor source region and another block intended to form a transistor drain region so as to reduce the semiconductor connection blocks in at least one direction parallel to the main plane of the support and to form one or more Si 1−z Ge z -based semiconductor wire(s) (with 0<y<1 and y<z).