Patent ID: 7984393

Claim:
A method for fabricating an integrated circuit device, the method comprising: providing a substrate; forming a layer on the substrate; applying a first photoresist over the layer; exposing the first photoresist to radiation through a first photomask and developing the first photoresist to form a first pattern; etching to transfer the first pattern into the layer; removing the first photoresist; applying a second photoresist over the layer; exposing the second photoresist to radiation through a second photomask and developing the second photoresist to form a second pattern; etching to transfer the second pattern into the layer; and removing the second photoresist; wherein the first pattern corresponds to drawn design pattern data describing device circuit features and dummy features, the device circuit features having first target patterns and the dummy features having second target patterns; and wherein the second pattern corresponds to a trim pattern for modifying the drawn design pattern data and corresponding first pattern, to extend a dimension of at least one first target pattern to provide at least one circuit feature having a third target pattern with the extended dimension and to reduce a dimension of at least one second target pattern to provide at least one dummy feature having a fourth target pattern with the reduced dimension.