Patent ID: 7925843

Claim:
A memory controller for writing data continuously to a first and a second block provided by dividing a memory region of a nonvolatile memory, and for reading the data therefrom, comprising: a first writer writing data to the first block of said memory while a power source voltage is maintained at a constant level; a second writer writing the same data to the second block of said same memory as the data written to the first block, while the power source voltage is maintained at the constant level, after completion of the writing by the first writer and a lapse of a predetermined waiting time, the waiting time being longer than a period of time in which the power source voltage drops from a guaranteed writing level down to a disabled writing level disabling the writing of data to the memory region; and a check code generator generating error detection check codes upon writing of data to each of the first and the second blocks, the first and the second writers writing the check codes to each of the first and the second blocks.