Patent ID: 6870200

Claim:
An insulated gate type semiconductor device comprising: a first base layer of a first conductive type having first and second surfaces; a second base layer of a second conductive type formed in the first surface region of the first base layer; a plurality of trenches formed over a range from the surface of the second base layer to the first base layer, and dividing the second base layer into a plurality of base regions; a plurality of trench gate electrodes formed in the plurality of trenches via a gate insulator; an emitter layer of a first conductive type formed in a surface region of at least one base region intermittently selected from the plurality of base regions positioned between the plurality of trenches, and contacting with the selected trench; a collector layer of a second conductive type formed above the second surface of the first base layer; a first main electrode formed to contact with each of at least one base region and the emitter layer; a second main electrode electrically connected to the collector layer; a plurality of dummy trenches formed over a range from the surface of the base region of the plurality of base regions where the emitter layer is not formed to the first base layer at a position near to each of the plurality of trenches; and a first diffusion region of a second conductive type formed in the first base layer and contacting a bottom portion of each trench and a dummy-trench-side side portion of each trench.