Patent ID: 8285936

Claim:
A data processing apparatus comprising: data processing circuitry for processing data; a memory for storing data for use by said data processing circuitry; a cache memory comprising a plurality of cache segments and configured to store cached data from said memory; power supply circuitry for selectively supplying each of said cache segments with power; an eviction selection mechanism for selecting evictable cached data for eviction from said cache memory; a cache compacting mechanism configured to perform cache compaction by evicting said evictable cached data from said cache memory and storing non-evictable cached data in fewer cache segments than were used to store said cached data prior to eviction of said evictable cached data; and power control circuitry configured to control said power supply circuitry to place in a power saving state at least one of said cache segments that, following eviction of said evictable cached data by said cache compacting mechanism, are not required to store cached data.