Patent ID: 7405981

Claim:
An electric circuit for inverting a data bit of a data burst read out from a memory module, comprising: a buffer for buffering a data burst being comprised of at least two data words, each comprising a specific number of data bits; a decoder device comprised of at least two parallel-connected decoders, each comparing bitwise and simultaneously an associated present data word of said data words buffered in said buffer with a reference data word and generating an inversion flag, if the number of different data bits of said data word present at said decoder and said reference data word exceeds half said specific number; said reference data word being a data word of said data words buffered in said buffer and neighbouring said present data word; a correction device for generating a corrected inversion flag for a specific decoder of said decoders by inverting or not inverting said inversion flag of said specific decoder dependent on said inversion flag generated by said specific decoder and said inversion flags generated by the remaining decoders of said decoders; and an inversion device comprised of a plurality of inverters, each inverting or not inverting said present word of an associated of said decoders dependent on said corrected inversion flag of said associated decoder.