Patent ID: 7964961

Claim:
A chip package comprising: a substrate comprising multiple insulating layers and multiple metal circuit layers between said multiple insulating layers; a flexible film over a top surface of said substrate, wherein said flexible film comprises a first polymer layer over said top surface of said substrate, a first metal trace on a top surface of said first polymer layer, a second metal trace on said top surface of said first polymer layer, and a second polymer layer on said first and second metal traces and on said top surface of said first polymer layer; a first tin-containing joint at said top surface of said substrate and between said first metal trace and a first metal pad of said substrate, wherein said first metal trace is connected to said first metal pad through said first tin-containing joint; a second tin-containing joint at said top surface of said substrate and between said second metal trace and a second metal pad of said substrate, wherein said second metal trace is connected to said second metal pad through said second tin-containing joint; a semiconductor chip vertically over said top surface of said substrate; a first metal bump between said semiconductor chip and said first metal trace, wherein said semiconductor chip is connected to said first metal trace through said first metal bump; and a second metal bump between said semiconductor chip and said second metal trace, wherein said semiconductor chip is connected to said second metal trace through said second metal bump, wherein a pitch between said first and second metal bumps is less than 35 micrometers.