Patent ID: 8497179

Claim:
A method of fabricating p-type metal oxide semiconductor (PMOS) transistor devices on a common substrate, the method comprising: obtaining a layout of PMOS transistor devices, the layout designating a plurality of PMOS device structures, and each of the plurality of PMOS device structures having a respective region of active semiconductor material and at least one gate finger associated therewith; obtaining a minimum gate count for application of stressor regions; identifying, from the plurality of PMOS device structures, a first set of PMOS device structures, where each PMOS device structure in the first set of PMOS device structures has a plurality of gate fingers that is greater than or equal to the minimum gate count; identifying, from the plurality of PMOS device structures, a second set of PMOS device structures, where each PMOS device structure in the second set of PMOS device structures has a number of gate fingers that is less than the minimum gate count; fabricating the first set of PMOS device structures on the common substrate using compressive stressor regions, and such that the gate fingers for the first set of PMOS device structures are formed overlying a first continuous region of active semiconductor material; and fabricating the second set of PMOS device structures on the common substrate without using compressive stressor regions, and such that the gate fingers for the second set of PMOS device structures are formed overlying a second continuous region of active semiconductor material, wherein the first continuous region of active semiconductor material and the second continuous region of active semiconductor material are separated and insulated from each other.