Patent ID: 7162657

Claim:
A semiconductor device, comprising: a first circuit being activated for a first predetermined preset period when one of a first control signal generated based on a first transition of an input clock signal and a second control signal generated based on a second transition of said input clock signal of a cycle next following said first transition of said input clock signal is activated; a second circuit being activated for a second predetermined preset period when a third control signal generated based on said first transition of said input clock signal is activated, said second circuit operating responsive to an output result of said first circuit; a third circuit being activated for a third predetermined preset period when a fourth control signal generated based on said second transition of said input clock signal is activated, said third circuit operating responsive to an output result of said first circuit; a sequence of operations by said first and second circuits, sequentially activated in accordance with said third control signal generated from said first transition of said input clock signal, constituting a first operating cycle; a sequence of operations by said first and third circuits, sequentially activated in accordance with said fourth control signal generated from said second transition of said input clock signal, constituting a second operating cycle; a circuit for performing control so that said first operating cycle and said second operating cycle are carried out alternately; and a circuit for controlling timing of said third control signal relevant to activation of said second circuit in said first operating cycle and timing of said second control signal relevant to activation of said first circuit in said second operating cycle so that a portion of the operation of said second circuit in said first operating cycle is temporally overlapped with the operation of said first circuit in said second operating cycle.