Patent ID: 8633525

Claim:
An integrated circuit structure, comprising: an active region; a dielectric overlying the active region and having a contact opening therethrough; a tungsten contact within the contact opening; a tungsten metal region overlying the contact and a portion of the dielectric; an interlevel dielectric overlying the tungsten metal region and the dielectric and having an opening therethrough; a tungsten via within the opening through the interlevel dielectric; a tungsten capacitive electrode overlying the tungsten via and a portion of the interlevel dielectric, wherein the capacitive electrode is electrically connected to the active region by the contact, the metal region, and the via; an oxide over the capacitive electrode and portions of the interlevel dielectric adjacent the capacitive electrode; a passivation layer including a silicon nitride layer and a silicon carbide layer over the oxide and over the capacitive electrode; and electrostatic discharge (ESD) protection within the passivation layer, wherein the capacitive electrode and each conductive region between the capacitive electrode and the active region are formed of a conductive material having a hardness at least as great as a hardness of the passivation layer.