Patent ID: 7319344

Claim:
An apparatus comprising: a logic circuit having a plurality of inputs; a plurality of passgates, wherein each of the plurality of passgates has an output directly connected to one of the plurality of inputs; at least one pulse generator configured to generate a pair of control signals to the plurality of passgates, wherein the pulse generator is configured to generate pulses on the pair of control signals to open the plurality of passgates; and a plurality of latch elements, wherein each of the plurality of latch elements is connected to a respective input of the plurality of inputs and is configured to latch the signal on the respective input when the plurality of passgates are open and to retain the signal on the respective input when the plurality of passgates are closed, and wherein each latch element of the plurality of latch elements comprises a pair of cross coupled inverters connected between two nodes, wherein a first node of the two nodes is connected to the respective input, and wherein the first node is driven by a first inverter of the pair, and wherein the first inverter is coupled to receive the pair of control signals and is configured to inhibit driving the first node when the plurality of passgates open.