Patent ID: 8199618

Claim:
A buffer control system for generating a buffered signal having a reduced buffer delay time between playback of tracks, the buffer control system comprising: a controller module for providing an end target according to a desired track, and further for selecting and reading a servo data signal corresponding to the desired track, and for updating the selection of the servo data signal according to a next desired track upon assertion of an end match signal; a compare circuit coupled to the servo data signal and the controller module, for comparing a timestamp of the servo data signal to the end target, and asserting the end match signal when the timestamp of the servo data signal matches the end target; and a data buffering unit coupled to the servo data signal and the compare module, for storing the servo data signal as stored data to fill a capacity of an internal memory while the compare circuit simultaneously compares the timestamp of the servo data signal to the end target regardless of a current capacity of the internal memory, and streaming out the buffered signal from the stored data in the internal memory when the capacity has reached a predetermined level.