Patent ID: 7236026

Claim:
A circuit for generating a clock signal which is frequency aligned with a reference clock signal, said circuit comprising: a controllable oscillator outputting said generated clock signal; a phase detector coupled to receive said reference clock signal and said generated clock signal; a frequency alignment circuit coupled to receive a reference pulse train based upon said reference clock signal and a generated pulse train based upon said generated clock signal, said frequency alignment circuit generating an average frequency alignment signal based upon a comparison of the phase of said generated pulse train and a selected phase of said reference pulse train comprising one of a first pulse of the reference clock signal and a second pulse of the reference clock signal which is out of phase by predetermined number of periods of the generated clock signal; and an oscillator control circuit selectively coupled to receive an output of said phase detector based upon said average frequency alignment signal, said oscillator control circuit generating an oscillator control signal for controlling the frequency of said generated clock signal.