Patent ID: 8647912

Claim:
A method for manufacturing a solar cell including: a substrate made of a crystalline semiconductor and having a first principle plane and a second principle plane, an intrinsic semiconductor layer made of an amorphous semiconductor, and a first semiconductor layer and a second semiconductor layer each made of an amorphous semiconductor, in which one of the first semiconductor layer and the second semiconductor layer is of the same conductivity type as the substrate, and the other is of the conductivity type opposite from the substrate, the method comprising: step S 1 of forming the intrinsic semiconductor layer on each of the first principle plane and the second principle plane of the substrate by catalytic chemical vapor deposition; and step S 2 of forming any one of the first semiconductor layer and the second semiconductor layer on at least one of the intrinsic semiconductor layers respectively formed on both the principle planes of the substrate, wherein in the step S 1 , catalyzers that decompose raw gas when being heated by receiving an electric current include a first catalyzer and a second catalyzer, and the first catalyzer is disposed at a position facing the first principle plane in the step S 1 , and the second catalyzer is disposed at a position facing the second principle plane in the step S 1 , and wherein: a plurality of the first catalyzers is arranged at first intervals, and a plurality of the second catalyzers is arranged at second intervals; the step S 1 includes step A of forming the intrinsic semiconductor layer on the first principle plane and step B of forming the intrinsic semiconductor layer on the second principle plane; in the step A, a first substrate is conveyed to a position located in one of the first intervals and facing the first catalyzer, so that the intrinsic semiconductor layer is formed on the first principle plane of the first substrate, and a second substrate is conveyed to a position located in an adiacent one of the first intervals and facing the first catalyzer which the first substrate faces, so that the intrinsic semiconductor layer is formed on the first principle plane of the second substrate; and in the step B, the first substrate is conveyed to a position located between one second catalyzer and another second catalyzer adiacent to the one second catalyzer, and facing the one second catalyzer, so that the intrinsic semiconductor layer is formed on the second principle plane of the first substrate, and the second substrate is conveyed to a position located between the one second catalyzer and the other second catalyzer, and facing the other second catalyzer, so that the intrinsic semiconductor layer is formed on the second principle plane of the second substrate.