Patent ID: 7791166

Claim:
A structure, comprising: (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface; (b) N semiconductor regions on the substrate, N being a positive integer, wherein the N semiconductor regions comprise dopants; (c) P semiconductor regions on the substrate, P being a positive integer, wherein the P semiconductor regions do not comprise dopants; and (d) M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer, wherein the M interconnect layers include an inductor, wherein all of the N semiconductor regions in the reference direction do not overlap the inductor, wherein all of the P semiconductor regions in the reference direction overlap the inductor, and wherein a plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.