Patent ID: 7490224

Claim:
A computer-implemented method comprising: initializing each of a plurality of counters, each counter corresponding to one of a plurality of instructions, to an initialization value when the instructions are issued from a first issue queue to a plurality of units, wherein one of the units is a second issue queue, and wherein the initialization value for each counter is set to a commit point for its corresponding instruction, wherein the commit point for each instruction is a number of instruction cycles after which the instruction can not be flushed; issuing the plurality of instructions issued to the second issue queue to a plurality of execution unit pipelines, each of the execution unit pipelines being connected to an execution unit; after the initializing, decrementing the counters corresponding to the instructions during each of a plurality of instruction cycles until the instructions are executed by one of the execution units; identifying an “n+1” exception corresponding to one of the instructions that has been issued to one of the plurality of units; in response to identifying the “n+1” exception, performing the following: flushing instructions from the execution unit pipelines with counters greater than one, wherein instructions from the execution unit pipelines with counters equal to zero are not flushed; reading an age attribute associated with instructions with counters equal to one, wherein each instruction with a counter equal to one has an associated age attribute; and in response to reading the age attributes, flushing one or more instructions with counters equal to one from the execution unit pipelines based upon the instructions' age attributes.