Patent ID: 8447915

Claim:
A flash memory device comprising: multiple flash memory chips including multiple physical blocks, each of the multiple physical blocks being an erase unit and including multiple physical pages, each of the multiple physical pages being a read/write unit; and a controller that allocates a physical block from among the multiple physical blocks to a certain logical block among multiple logical blocks that constitute a logical block space to a computer, wherein the controller: (A) manages an erase count for each physical block and the erase frequency of each logical block, and when the erase processing is carried out for the one or more physical blocks, updates the erase count for those one or more physical blocks, and the erase frequency of the logical block allocated to the physical blocks; and (B) allocates a physical block whose erase count is lower than a threshold to logical blocks whose erase frequency is greater than or equal to an erase frequency threshold, wherein the controller executes reclamation processing when the size of a free space of one or more target blocks is smaller than the size of data that is a write command target, wherein the one or more target blocks are one or more physical blocks to which the write destination logical block is allocated, wherein the write destination logical block is a logical block having an address specified in a write command from the host, and in the reclamation processing, the controller: (a) determines whether the erase frequency of the write destination logical block is greater than or equal to the erase frequency threshold, and whether the erase count of the target block is greater than or equal to an erase count threshold; (b) if the result of the determination in (a) is positive, selects one or more free blocks as an allocation destination of the write destination logical block from among multiple free blocks that are physical blocks having an erase count that is lower than the erase count threshold, and if the result of the determination in (a) is negative, the controller selects, from among the multiple free blocks, a free block having erase count corresponding to a level of erase count which is the same as, or as close as possible to, a level of erase count to which erase count of the target block belongs; (c) copies the latest data for each storage area within the target block to the free block selected in (b), and allocates the write destination logical block to the copy destination free block; (d) carries out the erase processing for the target block, and in accordance with this operation, updates erase count of the target block and updates the erase frequency of the write destination logical block; (e) manages the target block as a free block; (f) increases erase count threshold if erase count threshold is equal to or less than an average value of erase count of the multiple physical blocks; and (g) updates the erase frequency threshold to the average value of the erase frequencies of the multiple logical blocks.