Patent ID: 7002218

Claim:
An ESD-protection structure, comprising: an integrated circuit having a lighter doped p-silicon well (P− well), wherein the P− well is coupled to a common power supply rail; a lighter doped n-silicon well (N− well) in the P− well; a plurality of heavier doped p-silicon diffusions (P+ diffusions) in the N− well; a first heavier doped n-silicon diffusion (N+ diffusion) in the N− well, wherein the first N+ diffusion surrounds the plurality of P+ diffusions and overlaps the N− well into the P− well; a second heavier doped n-silicon diffusion (N+ diffusion) in the P− well, wherein the second N+ diffusion surrounds the first N+ diffusion; a bond pad connected to the plurality of P+ diffusions; and a connection to the second N+ diffusion.