Patent ID: 7301193

Claim:
A floating gate memory cell situated on a substrate, said floating gate memory cell comprising: a stacked gate structure situated on said substrate, said stacked gate structure being situated over a channel region in said substrate; a recess formed in said substrate adjacent to said stacked gate structure, said recess having a sidewall, a bottom, and a depth; a source of said floating gate memory cell situated adjacent to said sidewall of said recess and under said stacked gate structure; a Vss connection region situated under said bottom of said recess and under said source, said Vss connection region being connected to said source, said Vss connection region being a heavily doped region to reduce a Vss resistance; wherein said Vss connection region being situated under said bottom of said recess causes said source to have a reduced lateral diffusion in said channel region, thereby preventing an increase in a drain induced barrier lowering.