Patent ID: 6970047

Claim:
A clock generator, comprising: (a) a phase detector; (b) a counter; (c) clock-generation circuitry; and (d) a programmable lock detection and correction (PLDC) circuit, wherein: the clock-generation circuitry is adapted to generate a plurality of clock signals having different relative phases based on a count value received from the counter; the counter is adapted to accumulate digital control signals received from the phase detector in order to generate the count value; the phase detector is adapted to compare a reference clock signal to a feedback signal derived from one of the clock signals generated by the clock-generation circuitry in order to generate the digital control signals for the counter; the PLDC circuit receives an input control signal specifying one of a plurality of different possible input control values, each input control value corresponding to one of a plurality of different possible programmable accuracy levels; and the PLDC circuit is adapted to determine (1) whether operations of the clock generator have settled to a stable operating point to within the programmable accuracy level corresponding to the input control value specified by the input control signal and (2) whether the stable operating point corresponds to a proper lock state for the clock generator.