Patent ID: 8130183

Claim:
A scan driver, comprising: a plurality of stages coupled to each other in series, each of the stages configured to receive a clock signal, a clock bar signal, and an input signal, wherein each stage includes a first circuit that is configured to: store a first voltage and a second voltage in response to the input signal and one of the clock signal or the clock bar signal, the first voltage and the second voltage each corresponding to a voltage of the input signal, and provide a first output signal that corresponds to the second voltage in response to the second voltage and the other of the clock signal or the clock bar signal, the first circuit in a first stage including: a first capacitor having a first electrode coupled to a first node and having a second electrode coupled to a second node; a first transistor configured to transfer a drive power of a power supply to the first node, the first transistor receiving the clock signal or the clock bar signal at a gate thereof; and a third transistor configured to transfer the voltage of the input signal to the second node, the third transistor receiving the clock signal or the clock bar signal a gate thereof, wherein: the first circuit in the first stage further includes a second transistor, the first transistor is configured to transfer the drive power to the first node in response to the clock signal, the second transistor is configured to control a voltage of the first node in response to a voltage of the second node, the third transistor is configured to transfer the voltage of the input signal to the second node in response to the clock signal, the first capacitor is configured to store a voltage corresponding to the drive power and the input signal voltage, and a voltage of the first output signal corresponds to the voltage of the first node.