Patent ID: 8310855

Claim:
A device comprising: a control chip which is communicable with first and second groups each of which is composed of a predetermined number of I/O bits; and a first set of controlled chips and a second set of controlled chips that are controlled by the control chip and that correspond to the first and the second groups, respectively; wherein each of the controlled chips comprises: penetrating through substrate vias which have penetrating through interconnections penetrating through from a front surface to a back surface of each controlled chip and electrodes to be connected to the penetrating through interconnections of each controlled chip and to be connected to other penetrating through substrate vias of other ones of the controlled chips; wherein the control chip comprises nodes which are to be connected to penetrating through substrate vias of the controlled chips; wherein each of the controlled chips of the first and the second sets is connected to each other through the penetrating through substrate vias of each controlled chip while either one of the controlled chips of the first and the second sets is mounted on the control chip, whereby the control chip and the controlled chips are stacked to each other to form a stacked structure; wherein the control chip performs communication control of each controlled chip of the first and the second sets at the same access cycle and, thereby, communicates with a plurality of the controlled chips with the predetermined I/O bits; wherein the respective controlled chips of the first set each comprise: first ones of the penetrating through substrate vias which are used for performing communication between the control chip and the controlled chips of the first set and second ones of the penetrating through substrate vias which are used for performing communication between the control chip and the controlled chips of the second set; wherein the respective controlled chips of the second set each comprise: third ones of the penetrating through substrate vias which are used for performing communication between the control chip and the controlled chips of the second set and fourth ones of the penetrating through substrate vias which are used for performing communication between the control chip and the controlled chips of the first set; wherein the first ones of the penetrating through substrate vias and the fourth ones of the penetrating through substrate vias are connected to each other and are connected to first ones of the nodes of the control chip corresponding to the first I/O group, to thereby structure a first interconnection; wherein the second ones of the penetrating through substrate vias and the third ones of the penetrating through substrate vias are connected to each other and are connected to second ones of the nodes of the control chip corresponding to the second I/O group, to thereby structure a second interconnection; and wherein the first interconnection and the second interconnection are substantially equal in length to each other within the stacked structure.