Patent ID: 8455925

Claim:
A semiconductor device, comprising: a substrate including a memory circuit area and a logic circuit area; a memory capacitor element formed in the memory circuit area; a multilayer local interconnect layer formed in the memory circuit area by stacking N insulator layers where each insulator layer has an interconnect and a contact or via; and a multilayer local interconnect layer formed in the logic circuit area by stacking M insulator layers where each insulator layer has an interconnect and a contact or via such that the interconnect has a minimum pitch comparable to a minimum pitch in an interconnect of an insulating layer closest to the substrate, wherein M and N are natural numbers, wherein M>N, M−N≧2, and N≧2, and wherein the memory capacitor element is formed in a multilayer local interconnect layer comprised of (M−N) layers so that a height of the memory capacitor element substantially equals a height of the (M−N) layers.