Patent ID: 7220649

Claim:
A method of manufacturing a semiconductor device containing a MOS transistor on a semiconductor substrate comprising: forming a gate insulation film on a surface of an active area in a surface of said semiconductor substrate, the active area having a first conduction type, the active area further having a central area over which a gate electrode of the MOS transistor is formed, and an outside area outside of the central area; removing a portion of said gate insulation film so that an opening that exposes the outside area of the active area is formed; forming the gate electrode of the MOS transistor on said gate insulation film left on the central part of the active area; implanting first impurities of a second conduction type using said gate electrode as a mask with a first energy level that permits a penetration of ions of said first impurities through said gate insulation film so that a deep grade layer of the MOS transistor is formed in the surface of the active area, the deep grade layer extending from a gate edge right under an edge of the gate electrode to the outside area of said active area; implanting second impurities of the second conduction type into a part in said opening so that a drain layer of the MOS transistor is formed in the deep grade layer, the drain layer being doped heavier compared with said deep grade layer, the drain layer extending outwardly from a first edge which is positioned away from said gate edge; and implanting third impurities of said second conduction type into said opening with a second energy level that does not permit a penetration of ions of said third impurities through said gate insulation film so that a shallow grade layer of the MOS transistor is formed at least in a portion of the deep grade layer adjacent to the first edge of the drain layer, the shallow grade layer being lightly doped compared with said drain layer.