Patent ID: 7897466

Claim:
A method for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor provided on a same semiconductor substrate, the method comprising: forming a first gate electrode of the high breakdown voltage transistor and a second gate electrode of the low breakdown voltage transistor on a transistor formation area of the substrate, as well as a dummy gate electrode on a dummy pattern formation area of the substrate; forming an interlayer insulation film on the substrate so as to cover the first and the second gate electrodes and the dummy gate electrode; and forming a first contact hole on the first gate electrode, a second contact hole on the second gate electrode, and a dummy contact hole on the dummy gate electrode, respectively, by partially dry etching the interlayer insulation film, wherein in the formation of the contact holes, a top surface of the dummy gate electrode is exposed at a bottom of the dummy contact hole before a top surface of the first gate electrode is exposed at a bottom of the first contact hole; forming a first element-isolation film on the transistor formation area of the semiconductor substrate; forming a second element-isolation film on the transistor formation area of the substrate in such a manner that a height from a to surface of the substrate to a top surface of the second element-isolation film is lower than a height from the substrate top surface to a top surface of the first element-isolation film; and forming a dummy element-isolation film on the dummy pattern formation area of the substrate in such a manner that a height from the substrate top surface to a top surface of the dummy element-isolation film is equal to or higher than the height from the substrate top surface to the top surface of the first element-isolation film, wherein in the formation of the gate electrodes, the first gate electrode, the second gate electrode, and the dummy gate electrode, respectively, are extended onto the first element-isolation film, the second element-isolation film, and the dummy element-isolation film, respectively, and wherein in the formation of the contact holes, portions of the interlayer insulation film positioned immediately above the first element-isolation film and immediately above the dummy element-isolation film are etched in a same processing step to form the first contact hole and the dummy contact hole, respectively.