Patent ID: 7233000

Claim:
A silicon processing method, comprising: (a) providing a silicon substrate comprising a top side, a bottom side, and a bulk region; (b) forming an ohmic contact anode on the bottom side of the silicon substrate; (c) forming a masking layer comprising a bilayer of silicon dioxide and polycrystalline silicon on the top side of the silicon substrate and then patterning the masking layer, thereby exposing a portion of the top side of the silicon substrate; (d) forming a sealed microchannel by performing an electrochemical process the electrochemical process comprising: (i) anodizing with a first current density below the critical value for electropolishing, thereby forming a porous silicon capping layer in the exposed portion of the top side of the silicon substrate, and then (ii) anodizing with a second current density above the critical value for electropolishing, thereby dissolving a portion of the silicon substrate and forming a microchannel below the porous silicon capping layer; (e) after step (d), depositing a thin dielectric isolation layer on the top side of the silicon substrate; (f) performing a first deposition process, comprising: (i) depositing a first polysilicon layer on the thin dielectric isolation layer; (ii) patterning the first polysilicon layer to form a heater located above the porous silicon capping layer and a first branch of thermocouples located partially above the porous silicon capping layer and partially above the bulk region of the silicon substrate; and, (iii) doping the first polysilicon layer with a p-type dopant; (g) performing a second deposition process, comprising: (i) depositing an aluminum layer on the thin dielectric isolation layer; and, (ii) patterning the aluminum layer to form a second branch of thermocouples, interconnections, and metal pads, wherein the interconnections and the metal pads are in separate electrical contact with the heater, the first branch of thermocouples, and the second branch of thermocouples; (h) depositing a passivation layer above the top side of the semiconductor substrate, wherein the passivation layer is selected from the group consisting of an insulating layer, a silicon oxide layer, a silicon nitride layer, and a polyimide layer.