Patent ID: 8615633

Claim:
A method to maintain cache coherency within a multi-core processor, the method comprising: identifying a first cache entry to be evicted from a first cache, the first cache entry comprising a block of data and a first tag indicating an owned state; in response to identifying the first cache entry to be evicted from the first cache, broadcasting an owner eviction message for the first cache entry from the first cache; identifying a second cache entry in a second cache, the second cache entry comprising the block of data and a second tag indicating a shared state; detecting the broadcasted owner eviction message for the first cache entry from the first cache with the second cache; in response to the second cache detecting the broadcasted owner eviction message for the first cache entry from the first cache, broadcasting an ownership acceptance message for the second cache entry from the second cache; detecting the broadcasted ownership acceptance message for the second cache entry from the second cache with the first cache; and in response to the first cache detecting the broadcasted ownership acceptance message for the second cache entry from the second cache, transforming the second tag in the second cache entry from the shared state to the owned state.