Patent ID: 8390969

Claim:
A ESD protection structure coupled between an I/O pad and a GND pad, the structure comprising: a JFET having a drain terminal, a gate terminal, and a source terminal, and having a drain-to-source break down voltage Vbr 2 , and having a drain-to-source saturation current of Isat, wherein the drain terminal is coupled to the I/O pad, and the gate and source terminals are coupled together, and wherein the JFET is activated, a JFET drain-to-source current is generated; a diode having a cathode terminal and an anode terminal, and having a break down voltage Vbr 1 , wherein the cathode terminal is coupled to the gate of the JFET; a transistor having a collector terminal, a base terminal, and an emitter terminal, wherein the collector terminal is coupled to the source terminal of the JFET, the base terminal is coupled to the anode terminal of the diode, and the emitter terminal is coupled to the GND pad, and wherein the transistor is activated, a voltage Vbe is developed between the base and emitter terminals; a resistor coupled between the base terminal of the transistor and the GND pad; and wherein a voltage that is less than the sum of the Vbr 1 , Vbe, and Vbr 2 voltages is applied between the I/O pad and the GND pad, the JFET drain-to-source current is limited to a maximum current level of Isat.