Patent ID: 8482083

Claim:
A semiconductor integrated circuit device comprising: a first bit line extended along a first direction; a second bit line extended along the first direction; a word line extended along a second direction, the second direction being perpendicular to the first direction; a first P-type well extended along the first direction; a second P-type well extended along the first direction; an N-type well extended along the first direction, and provided between the first P-type well and the second P-type well; and a memory cell having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal of the second inverter being coupled to an output terminal of the first inverter and with an output terminal of the second inverter being coupled to an input terminal of the first inverter, a third N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the second inverter and the second bit line, a gate electrode of the third N-channel MOS transistor and a gate electrode of the fourth N-channel MOS transistor both being coupled to the word line; wherein the first N-channel MOS transistor and the third N-channel MOS transistor in the memory cell are located at the first P-type well, wherein the first P-channel MOS transistor and the second P-channel MOS transistor in the memory cell are located at the N-type well, wherein the second N-channel MOS transistor and the third N-channel MOS transistor in the memory cell are located at the second P-type well, wherein a first wiring layer includes a first portion serving as a gate electrode of the first N-channel MOS transistor and a second portion serving as a gate electrode of the first P-channel MOS transistor of the memory cell, wherein a second wiring layer includes a third portion serving as a gate electrode of the second N-channel MOS transistor and a fourth portion serving as a gate electrode of the second P-channel MOS transistor of the memory cell, wherein a third wiring layer includes a fifth portion serving as the gate electrode of the third N-channel MOS transistor of the memory cell, wherein a fourth wiring layer includes a sixth portion serving as the gate electrode of the fourth N-channel MOS transistor of the memory cell, and wherein an entirety of each of the first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer in plan view is substantially rectangular.