Patent ID: 7317339

Claim:
A non-inverting domino register, comprising: a domino stage, for evaluating a logic function based on at least one input data signal and a pulsed clock signal, said pulsed clock signal lagging a symmetric clock signal, wherein said domino stage pre-charges a pre-charged node high when said symmetric clock signal is low and opens an evaluation window when said pulsed clock signal goes high, and pulls said pre-charged node low if it evaluates, and keeps said pre-charged node high if it fails to evaluate; a write stage, coupled to said domino stage and responsive to said pulsed and symmetric clock signals, which pulls a first preliminary output node high if said pre-charged node goes low, and which pulls said first preliminary output node low when said pre-charged node and symmetric clock signal are high; an inverter, having an input coupled to said first preliminary output node and an output coupled to a second preliminary output node; a high keeper path, which keeps said first preliminary output node high when enabled, wherein said higher keeper path is enabled when said symmetric clock signal and said second preliminary output node are both low and which is otherwise disabled; a low keeper path, which keeps said first preliminary output node low when enabled, wherein said low keeper path is enabled when said second preliminary output node and said pre-charged node are both high and which is otherwise disabled; and an output stage, which provides an output signal based on states of said pre-charged node and said second preliminary output node.