Patent ID: 8560923

Claim:
A semiconductor memory device comprising: a memory cell array that includes a plurality of memory cells in a row direction and in a column direction, each of the memory cells including a variable resistive element having electrodes on both ends of a variable resistor, and a current limiting element connected to the electrode on one end of the variable resistive element, wherein a resistance state of the variable resistive element specified by a resistance characteristic between both ends is changed among two or more different resistance states due to application of an electric stress between both ends, and one of the resistance states after the change is used for storing information; and a control circuit that controls a coding action in which an error correction coding is performed to a plurality of information bits so as to generate coded data having a bit length longer than that of the plurality of information bits, a first writing action in which a writing voltage pulse having a first polarity is applied to the electrodes at both ends of the variable resistive element in the selected memory cell corresponding to a bit of a first logical value of the coded data so as to change the variable resistive element to a first resistance state, a second writing action in which a writing voltage pulse having a second polarity, which is opposite to the first polarity, is applied to the electrodes at both ends of the variable resistive element in the selected memory cell corresponding to a bit of a second logical value of the coded data so as to change the variable resistive element to a second resistance state, a reading action in which a reading voltage pulse having the first polarity is applied to the electrodes at both ends of the variable resistive element in the plurality of selected memory cells corresponding to the coded data so as to read the resistance state of the selected memory cells as the coded data, and a decoding action in which an error in the coded data read by the reading action is detected and corrected, and the coded data is decoded, wherein when an error in the coded data read in the decoding action is detected, the control circuit controls a correcting action, in which the memory cells corresponding to an error position of the error are selected, and the second writing action is executed to all of the memory cells corresponding to the error position, to the coded data stored in the memory cell array.