Patent ID: 6879019

Claim:
A combination wafer, comprising: a substrate; a plurality of electronic elements formed in or on the substrate; a first set of alternating dielectric layers and layers of metal lines on the substrate, the first set having a first guard ring trench therein with a first width; a first guard ring layer formed on surfaces of the first guard ring trench; a second set of alternating dielectric layers and layers of metal lines on the first set, the second set having a second guard ring trench therein, above the first guard ring trench and having a second width which is wider than the first width; a second guard ring layer formed on surfaces of the second guard ring trench; a third set of alternating dielectric layers and layers of metal lines on the second set, the third set having a third guard ring trench therein, above the second guard ring trench and having a third width which is wider than the second width; and a third guard ring layer formed on surfaces of the third guard ring trench.