Patent ID: 8625376

Claim:
A semiconductor memory device, comprising: a first plane and a second plane each comprising a plurality of memory cells; a first page buffer group comprising a plurality of page buffers for temporarily storing data to be stored in the memory cells of the first plane and data read from the memory cells of the first plane; a second page buffer group comprising a plurality of page buffers for temporarily storing data to be stored in the memory cells of the second plane and data read from the memory cells of the second plane; a data transfer circuit configured to transfer first data, outputted from the first page buffer group, to the second page buffer group to store the first data, stored in the memory cells of the first plane, in the second plane and to transfer second data, outputted from the second page buffer group, to the first page buffer group to store the second data, stored in the memory cells of the second plane, in the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed; a column selector configured to select which page buffers of the first and the second page buffer groups to output in response to a column address signal, wherein the column selector comprises a column address counter configured to increase the column address when outputting the data stored in the first or the second page buffer group to the data transfer circuit.