Patent ID: 6921687

Claim:
A method of fabricating a semiconductor element, comprising the steps of: selectively forming a second base layer of a second conductivity type in one surface region of a first base layer of a first conductivity type, said second base layer having an impurity concentration profile such that the point of the highest impurity concentration is positioned in a region close to the junction between the second base layer and the first base layer; selectively forming an emitter layer or source layer of the first conductivity type in a surface region of said second base layer; forming a gate electrode on the surface of that region of said second base layer which is positioned between said emitter layer or source layer and said first base layer with a gate insulating film interposed between said gate electrode and said second base layer; selectively forming a collector layer or drain layer in the other surface region of said first base layer or in one surface region of said first base layer; and forming a first main electrode in contact with said collector layer or drain layer and a second main electrode in contact with said emitter layer or source layer and said second base layer.