Patent ID: 7649483

Claim:
A circuit comprising: T sets of digital to analog converters (DACs), each including: N current sources, wherein an output signal comprises a sum of outputs of said N current sources; and M delay elements, wherein an input of a first one of said M delay elements and a control input of a first one of said N current sources receive a respective one of a plurality of decoded signals, wherein an input of other ones of said M delay elements communicates with an output of preceding respective ones of said M delay elements, respectively, and wherein outputs of said other ones of said M delay elements control corresponding control inputs of said other ones of said N current sources; T sets of first converters each having a feedback node, an output and an input that communicates with said output signal of a respective one of said T sets of DACs; T second converters having inputs that communicate with respective ones of said feedback nodes of each of said T sets of first converters; and a summer that generates a difference signal that is based on said outputs of said T sets of first converters and outputs of said T second converters.