Patent ID: 7977976

Claim:
A method for preventing a logically undefined state from propagating when synchronizing data from a first clock domain to a second clock domain, the method comprising: storing data corresponding to previous input data sampled in the second clock domain, the previous input data originating from the first clock domain; sampling input data in the second clock domain, the input data originating from the first clock domain and corresponding to present input data; and updating output data stored in a latch, comprising: writing the sampled input data into the latch to change the output data if the sampled input data represents a defined logic state different from the stored data; leaving the output data unchanged if the stored data is not different from the sampled input data; and writing update data representing a defined logic state into the latch if the sampled input data represents an undefined logic state, to prevent the output data in the latch from changing to an undefined logic state.