Patent ID: 7586134

Claim:
A semiconductor device, comprising: a semiconductor substrate; an element isolation structure having an isolation trench formed in an element isolation region in said semiconductor substrate with an insulator and in which an upper portion of the insulator protrudes from a surface of said semiconductor substrate; a gate electrode in an electrode shape formed over an element active region demarcated by said element isolation structure of said semiconductor substrate with a gate insulating film therebetween; a pair of impurity diffusion regions formed in a surface layer of said semiconductor substrate adjacent to both sides of said gate electrode in the element active region; a conductive layer comprising a conductive material with an adhesive layer, formed in a region between said element isolation structure and said gate electrode and over the element active region in such a manner as to be electrically insulated from said gate electrode and electrically connected with said impurity diffusion region; and a channel dose layer having an upper surface planar with uppermost surfaces of said pair of impurity diffusion regions, wherein a top surface of said element isolation structure and said conductive layer are planar to form a flat surface; said conductive material is at least one material selected from the group consisting of tungsten and titanium nitride; and an upper surface of said gate electrode is a concave surface, and middle portion of the upper surface is lower than that of the top surface of said element isolation structure.