Patent ID: 7197594

Claim:
A control circuit for storing bits of a data block on a Non-Volatile Memory (“NVM”) array, said circuit comprising: a bit scrambling block adapted to rearrange the bit of the data block according to a spreading pattern; an Error Correction Coding (“ECC”) block adapted to generate an ECC based on either the original data block or on the rearranged data block; an NVM storing circuit adapted to store in said NVM array the ECC and the block of bits from which the ECC was not derived; a reading circuit adapted to read a stored block of bits from the NVM array; wherein said bit scrambling block is adapted to scramble the read data block if the block was stored unscrambled; and wherein the ECC block is adapted to manipulate the scrambled block according to an ECC which is based on a scrambled version of the original data block prior to being stored on the NVM.