Patent ID: 7790529

Claim:
A method of forming a memory array, comprising: forming a first dielectric material over a first semiconductor material; patterning the first dielectric material to form openings extending through the first dielectric material to the first semiconductor material; after patterning the first dielectric material, forming second semiconductor material over the patterned first dielectric material and within the openings and in direct contact with the first semiconductor material; patterning the second semiconductor material into a plurality of active regions, the active regions being over and in one-to-one correspondence with the openings; forming second dielectric material over the active regions and in direct contact with the first dielectric material; patterning the second dielectric material to form openings extending through the second dielectric material to the first dielectric material; forming first conductive lines within the openings that extend through the second dielectric material, wherein each of the conductive lines is over at least a portion of the first dielectric material; implanting conductivity-enhancing dopant into the second semiconductor material of the active regions to form conductively-doped regions within the active regions, each of the plurality of active regions having at least two of the conductively-doped regions; forming capacitors, wherein a storage node of at least one of the capacitors is electrically connected with at least one of the conductively-doped regions of at least one of the plurality of active regions; and forming second conductive lines, wherein at least one of the second conductive lines is electrically coupled with an other one of the at least two conductively-doped regions of the at least one of the plurality of active regions.