Patent ID: 8487360

Claim:
A semiconductor memory device comprising: a substrate of a first impurity type; a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type; a second well region of the first impurity type in the substrate; a patterned first dielectric layer on the substrate extending over the first and second well regions; a patterned first gate structure on the patterned first dielectric layer, the patterned first gate structure including a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, the first section and the second section intersecting each other in a cross pattern; a patterned second dielectric layer on the patterned first gate structure; a patterned second gate structure on the patterned second dielectric layer, the patterned second gate structure including at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure; and pocket regions in the second well region at both sides of the patterned first gate structure.