Patent ID: 8675812

Claim:
A control circuit enabling a serial-in-parallel-out shift register to report receipt of a serial data transmission of valid predetermined length and to further report receipt of serial data transmissions of erroneous length, with both valid and erroneous length transmissions being reported without use of a counter, the serial-in-parallel-out shift register comprising a plurality of sequentially daisy-chained flip-flops, with a data output of all but a last flip-flop being coupled to a data input of a successive flip-flop, the serial-in-parallel-out shift register including a first flip-flop and a last flip-flop, each shift register flip-flop having a common clock input, a common reset input, and a data output, the control circuit comprising: a first control flip-flop, coupled to the serial-in-parallel-out shift register in an initial daisy chained position, the first control flip-flop having a data transmission receiving input, a data output coupled to a data input of first shift register flip-flop, and a preset input coupled to the common reset input of the serial-in-parallel-out shift register, establishing an End of Transmission Marker within the first control flip-flop when the common reset input is actuated, the End of Transmission Marker being clocked through sequential daisy-chained flip-flops of the serial-in-parallel-out shift register as additional bits of the serial data transmission are received; a second control flip-flop, having an input coupled to a data output of a first selected flip-flop within the serial-in-parallel-out shift register, the first selected flip-flop having a position corresponding to a first predetermined serial transmission length, the second control flip-flop being set to a first logic state upon actuation of the common reset input of the serial-in-parallel-out shift register, and being set to and maintaining a second logic state upon clocked passage of the End of Transmission Marker from the data output of the selected flip-flop of the serial-in-parallel-out shift register to the second control flip-flop, thereby indicating a receipt of too many bits of serial data beyond the predetermined serial transmission length; and an indicator unit coupled to the data output of the selected flip-flop of the serial-in-parallel-out shift register and to the second control flip-flop, the indicator unit outputting a signal indicative of a transmission of valid length when both the End of Transmission Marker is output from the last flip-flop of the serial-in-parallel-out shift register and the second control flip-flop is not set to the second logic state.