Patent ID: 7808847

Claim:
A repairable pseudo-dual port static random access memory, comprising: a memory cell array comprising a plurality of memory cell blocks and a redundant block, wherein each of the memory cell blocks is divided into a plurality of memory cell sub-blocks, and a size of the redundant block is the same as a size of the memory cell sub-blocks; an address decoding circuit, comprising: a row address decoding circuit for turning on a specific row of the memory cell array according to the specific row specified by a row address; a first column address decoding circuit, having an N-bit connection bus, for electrically connecting N first specific columns of the memory cell array to the N-bit connection bus of the first column address decoding circuit according to the N first specific columns specified by a first column address signal, wherein N is a natural number; and a second column address decoding circuit, having an M-bit connection bus, for electrically connecting M second specific columns of the memory cell array to the M-bit connection bus of the second column address decoding circuit according to the M second specific columns specified by a second column address signal, wherein M is a natural number and greater than N; a first input-output port having an N-bit bus; a second input-output port having an M-bit bus; a first select circuit coupled to the N-bit connection bus of the first column address decoding circuit and the N-bit bus of the first input-output port, wherein when a first specific column specified by the first column address signal is in a failed memory cell sub-block, the first select circuit selects a first corresponding column of the redundant block, and connects the first corresponding column of the redundant block to the N-bit bus of the first input-output port, wherein a relative address of the first corresponding column is the same as an address of the first specific column in the failed memory cell sub-block; and a second select circuit coupled to the M-bit connection bus of the second column address decoding circuit and the M-bit bus of the second input-output port, wherein when a second specific column specified by the second column address signal is in the failed memory cell sub-block, the second select circuit selects a second corresponding column of the redundant block, and couples the second corresponding column of the redundant block to the M-bit bus of the second input-output port, wherein a relative address of the second corresponding column is the same as an address of the second specific column in the failed memory cell sub-block.