Patent ID: 8438441

Claim:
A test access port circuit formed on an integrated circuit comprising: A. an instruction register having a serial input connected to a first test data input terminal, having a serial output, having a control input, and having control outputs including a port enable control output; B. data registers, each data register having a serial input connected to the first test data input terminal, having a serial output, and having a control input connected to a control output of the instruction register; C. a state machine having inputs connected to a test clock input terminal and a test mode select input terminal and having control outputs including a control output coupled to the instruction register; D. a first multiplexer having data inputs, a data output, and a control input connected to a control output of the instruction register, each data input being connected to a serial output of one of the data registers; E. a second multiplexer having first and second data inputs, a control input, and an output, the first data input being connected to the output of the first multiplexer, the second data input being connected to the serial output of the instruction register, the data output being connected to a first test data output terminal, and the control input being connected to one of the control outputs of the state machine; and F. a third multiplexer having first and second data inputs, a control input, and an output, the first data input being connected to the output of the second multiplexer, the second data input being connected to a second test data input terminal, the data output being connected to a second test data output terminal, and the control input being connected to one of the control outputs of the instruction register.