Patent ID: 8741720

Claim:
A method of forming a system-on-a-chip, comprising: providing a substrate having a first portion and a second portion, wherein the first portion is well-free and the second portion includes a well region of a first conductivity type; forming a first gate stack above the first portion of the substrate and a second gate stack above the well region of the second portion of the substrate; forming a mask layer above the second portion of the substrate but not above the first portion of the substrate; implanting dopant impurity atoms of a second conductivity type, opposite the first conductivity type, into the first portion of the substrate to form tip regions on either side of the first gate stack, wherein the first gate stack blocks the implanting of dopant impurity atoms of the second conductivity type in the first portion of the substrate directly below the first gate stack during the formation of the tip regions, and wherein the mask layer blocks the implanting of dopant impurity atoms of the second conductivity type in the second portion of the substrate during the formation of the tip regions in the first portion of the substrate; and implanting dopant impurity atoms of the first conductivity type into the first portion of the substrate to form halo regions adjacent the tip regions and to form a threshold voltage implant region in the first portion of the substrate directly below the first gate stack, wherein implanting the dopant impurity atoms of the first conductivity type to form halo and threshold voltage implant regions includes penetrating the first gate stack, and wherein the mask layer blocks the implanting of dopant impurity atoms of the first conductivity type in the second portion of the substrate during the formation of the halo and threshold voltage implant regions in the first portion of the substrate.