Patent ID: 8767478

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array including an electrically rewritable non-volatile memory cell arranged therein; and a control unit configured to perform controlling of repeating an erase operation to apply an erase pulse voltage to the memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed, the control unit configured to, when controlling of repeating the erase operation, the erase verify operation and the step-up operation is performed, generate a first erase pulse voltage in a first one of the erase operations as an initial pulse voltage, and thereafter generate a second erase pulse voltage in a second one of the erase operations subsequent to the first one of the erase operations, the control unit configured to control the erase pulse voltage such that: the second erase pulse voltage has a voltage value at a saturation state larger than that of the first erase pulse voltage, and the first erase pulse voltage is longer than the second erase pulse voltage with respect to a width of a blunted wave-shape portion thereof, the blunted wave-shape portion being continuous to the voltage value at the saturation state, and the control unit configured to control a voltage of the first erase pulse voltage such that a voltage wave shape of the first erase pulse voltage when a vertical axis thereof denotes a voltage and a lateral axis denotes time has a gradient that a gradient at a first point of time is not larger than a gradient at a second point of time before the first point of time through the width of the blunted wave-shape portion, the blunted wave-shape portion being continuous to the voltage value at the saturation state of the first erase pulse voltage.