Patent ID: 7242052

Claim:
A non-volatile memory device, comprising: a substrate; a stacked structure, disposed over the substrate, the stacked structure comprising a gate dielectric layer and a control gate on the gate dielectric layer; a charge storage layer, covering a top and a sidewall of the stacked structure; a first dielectric layer, disposed between the top of the stacked structure and the charge storage layer; a second dielectric layer, disposed between the sidewall of the stacked structure and the charge storage layer; a third dielectric layer, disposed between the charge storage layer and the substrate; a pair of auxiliary gates, denoted as a first auxiliary gate and a second auxiliary gate, disposed over the substrate at both sides of the stacked structure and separating from the charge storage layer by a gap; and a fourth dielectric layer, disposed between each of the auxiliary gates and the substrate; wherein a material for the charge storage layer comprises polysilicon, silicon nitride or dielectric material with high dielectric constant.