Patent ID: 8159302

Claim:
A differential amplifier circuit comprising: a P-type differential input unit having a non-inverted input end adapted for receiving a first input voltage, and an inverted input end adapted for receiving a second input voltage, said P-type differential input unit outputting a first output in response to the first and second input voltages; an N-type differential input unit having a non-inverted input end adapted for receiving the first input voltage, and an inverted input end adapted for receiving the second input voltage, said N-type differential input unit outputting a second output in response to the first and second input voltages; a P-type current mirror circuit coupled to said N-type differential input unit for receiving the second output therefrom, and driven by the second output to generate a first control output; an N-type current mirror circuit coupled to said P-type differential input unit for receiving the first output therefrom, and driven by the first output to generate a second control output; an output unit coupled to said P-type and N-type current mirror circuits for receiving the first and second control outputs therefrom, and outputting an output voltage in response to the first and second control outputs from said P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series, said first P-type transistor having a control end coupled to a common node between said first and second P-type transistors, said second P-type transistor having a control end receiving the first control output from said P-type current mirror circuit such that said second P-type transistor is driven by the first control output from said P-type current mirror circuit; and a second sub-current source including first and second N-type transistors connected in series, said first N-type transistor having a control end coupled to a common node between said first and second N-type transistors, said second N-type transistor having a control end receiving the second control output from said N-type current mirror circuit such that said second N-type transistor is driven by the second control output from said N-type current mirror circuit.