Patent ID: 6934824

Claim:
A dual-port memory controller for enabling a plurality of processors to access a memory area to read/write data, comprising: at least one data controller individually inputting data to or outputting data from the processors; a memory controller outputting at least one signal to accept or not accept data access requests from other processors after finishing a data access operation for one processor; and at least one delay unit delaying only the signal outputted from the memory controller to one or more other processors, wherein the delaying unit includes a clock oscillator generating a clock signal of a predetermined frequency, and flip-flops receiving the clock signal and delaying the signal, wherein the delaying until operates such that a delay time of said signal varies if the clock frequency of the clock oscillator varies and delays the signal for a predetermined period of time so as to stably read/write the data, and wherein the delay time becomes longer if the clock frequency becomes higher.