Patent ID: 7995753

Claim:
An apparatus for performing parallel operations, the apparatus comprising: a first memory for receiving an input stream; a first algorithm operating on the input stream using a first key to produce a first result and operating in parallel on the same input stream using a second key different than the first key to produce a second result; a second algorithm operating in parallel with the first algorithm on the same input stream using the first key to produce a third result different than the first result and operating on the same input stream in parallel using the second key to produce a fourth result different than the second result; a first validator coupled with the memory and configured for determining whether a one of the first or second result is valid; a second validator coupled with the memory and configured for determining whether a one of the third or fourth result is valid; and, a control device operatively coupled with the first and second validators, the control device being configured for selecting, based on signals received from the first and second validators, either the first algorithm and switching the determined valid one of the first or second results to an output of the control device or the second algorithm and switching the determined valid one of the third or fourth results to the output of the control device.