Patent ID: 8898768

Claim:
A computer or microchip, comprising: a central controller of the computer or microchip, including a master controlling device or a master control unit, having a connection by a secure control bus with the other parts of the computer or microchip, including at least a volatile random access memory (RAM) located in a portion of the computer or microchip that has a connection for a network; the secure control bus is isolated from any input from the network; the secure control bus has a configuration by which it provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM); the direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM); and the direct preemptive control also includes control of the connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and at least one microprocessor that has a connection for the network.