Patent ID: 7426625

Claim:
A method of supporting memory addresses with holes, the method comprising the computer implemented steps of: virtualizing a first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning to produce a first logical address range; virtualizing a second physical address range allocated for system memory for the operating system to produce a second logical address range, wherein the first physical address range and the second physical address range are non-contiguous and the first logical address range and the second logical address range are contiguous; virtualizing a memory mapped input/output physical address range that is intermediate the first physical address range and the second physical address range to produce a third logical address range, wherein a lowermost logical address of the third logical address range exceeds a respective uppermost logical address of the first and second logical address ranges; wherein the steps of virtualizing the first physical address range, the second physical address range, and the memory mapped input/output physical address range comprise maintaining a mapping table that defines physical addresses and corresponding logical addresses; and wherein maintaining the mapping table further comprises maintaining the mapping table in a physical address space allocated to one of the first and second physical address ranges, and wherein the physical address space is unavailable to the operating system accessing the first and second physical address ranges.