Patent ID: 7511360

Claim:
An integrated circuit, comprising: a plurality of N channel transistors comprising features formed in first active portions of a semiconductor layer and first gate structures overlying the semiconductor layer, wherein the first gate structures have portions outside the first active portions; a plurality of P channel transistors comprising features formed in second active portions of the semiconductor layer and second gate structures overlying the semiconductor layer wherein the second gate structures have portions outside the second active region; compressive stressors over the P channel transistors and having portions outside the second active regions; tensile stressors over the N channel transistors and having portions outside the first active portions, whereby boundaries are present at interfaces between the tensile and compressive stressors; and contacts to the first and second gate structures wherein each contact extends through a compressive stressor or a tensile stressor, and wherein substantially all of the contacts to the first and second gate structures of the integrated circuit are at least a predetermined distance from the boundaries.