Patent ID: 8006156

Claim:
A method of generating test conditions for detecting delay faults in a semiconductor integrated circuit that operates at a system timing, the method comprising: generating a test pattern to be used in a test of a logic circuit in the semiconductor integrated circuit, the logic circuit including a plurality of signal paths having respective delay times through a combinational logic circuit between respective pluralities of start-side flip-flops and end-side flip-flops, the test pattern including a transition of a logical value of input data to be supplied to a first one of the start-side flip-flops that produces an expected transition of a logical value of output data supplied to a first one of the end-side flip-flops; determining a minimum slack margin as a difference between the system timing and one of i) a longest one of the delay times of a first group of the signal paths from respective ones of the start-side flip-flops to the first one of the end-side flip-flops and ii) a longest one of the delay times of a second group of the signal paths from the first one of the start-side flip-flops to respective ones of the end-side flip-flops; setting a test timing faster than the system timing; simulating an operation of the logic circuit at the test timing using the test pattern and the delay times of the signal paths corrected by adding the minimum slack margin; and storing the test pattern and the test timing in a test condition database including, when the simulating indicates that the output data after the expected transition is not acquired in the first one of the end-side flip-flops at the test timing, further storing mask data that masks data held in the first one of the end-side flip-flops in the test using the test pattern and the test timing in the test condition database.