Patent ID: 6915399

Claim:
A memory controller, comprising: a) a host side region to be clocked by a first clock, said host side region comprising: (i) a queue to queue command packet chunks; (ii) a plurality of memory command packet chunk output lanes stemming from steering circuitry, said steering circuitry to guide specific command packet chunks received from said queue to specific command packet chunk output lanes, said queue having an output for each output lane, said steering circuitry further comprising: a) a first multiplexer having a first input to receive a first packet chunk from a queue output, said first multiplexer having a second input coupled to a latch circuitry output, said latch circuitry downstream from said queue output to hold a second packet chunk from said queue output; b) a second multiplexer having a plurality of inputs, one of said inputs coupled to said first multiplexer's output, other inputs of said second multiplexer downstream from outputs of said queue other than said queue output; and, b) a memory side region to be clocked by a second clock, said memory side region comprising: inputs coupled to said memory command packet chunk output lanes.