Patent ID: 8185571

Claim:
A microprocessor comprising: a decoder to receive a multiply-add instruction; a register file to initially store, in a first register, a first packed data having a first plurality of packed data elements including at least four initial data elements; said register file also to store, in a second register, a second packed data having a second plurality of packed data elements including at least four initial data elements, wherein each initial data element in said first plurality of data elements corresponds to an initial data element in said second plurality of data elements, in a respective position; a circuit coupled to said register file and said decoder, said circuit in response to the multiply-add instruction to, multiply together only said corresponding initial data elements in said first and second packed data to generate corresponding intermediate data elements, said intermediate data elements being paired into a plurality of sets, arithmetically combine the intermediate data elements in each of said plurality of sets to generate a plurality of result data elements respectively representing the addition of paired intermediate data elements, wherein each of said plurality of result data elements provides a higher precision than said initial data elements, and store as a result of executing the multiply-add instruction said plurality of result data elements in the first register of said register file as a third packed data, wherein each element in the third packed data is the result of a multiply-add operation on two pairs of corresponding initial data elements.