Patent ID: 8736334

Claim:
A current mode logic latch, comprising: a sample stage comprising: a first sample stage transistor coupled at its gate terminal to a first input terminal of the current mode logic latch; a second sample stage transistor coupled at its gate terminal to a second input terminal of the current mode logic latch, the first input terminal and the second input terminal comprising a differential voltage input; a first resistor coupled between a drain terminal of the first sample stage transistor and a high potential voltage source; a second resistor coupled between a drain terminal of the second sample stage transistor and the high potential voltage source; a first sample stage current source coupled to a source terminal of the first sample stage transistor; a second sample stage current source coupled to a source terminal of the second sample stage transistor; and a sample stage switch coupled between the source terminal of the first sample stage transistor and the source terminal of the second sample stage transistor; and a hold stage comprising: a first hold stage transistor coupled at its drain terminal to the drain terminal of the first sample stage transistor; a second hold stage transistor coupled at its drain terminal to the drain terminal of the second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor; a first hold stage current source coupled to a source terminal of the first hold stage transistor; a second hold stage current source coupled to a source terminal of the second hold stage transistor; and a hold stage switch coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.