Patent ID: 7920118

Claim:
A scan driving circuit comprising: a plurality of stages each configured to receive two of three clocks, to receive an input signal through an input terminal, to delay the input signal, and to output an output signal through an output terminal, wherein the input terminal of each of the plurality of stages is connected to the output terminal of a previous one of the stages, wherein each of the plurality of stages comprises: a switch for providing the input signal of the input terminal to a first node according to a first clock among the three clocks; a first clock terminal for receiving the first clock; a switch section for coupling a first voltage source to the output terminal according to the first clock and the input signal, the switch section comprising: a first transistor comprising a gate connected to the first clock terminal, a drain connected to a second voltage source, and a source connected to a second node; a second transistor comprising a gate connected to the first node, a source connected to the first clock terminal, and a drain connected to the second node; and a third transistor comprising a gate connected to the second node, a source connected to the first voltage source, and a drain connected to the output terminal; and a storage section for maintaining a voltage of the output terminal for a predetermined time, and for providing a voltage of a second clock from among the three clocks to the output terminal according to the input signal.