Patent ID: 7269240

Claim:
A network interface circuit for communicating with a plurality of access points, the network interface circuit comprising: a first signal circuit for generating a first signal according to a first clock; a second signal circuit for generating a second signal according to a second clock; a first transmission port and a second transmission port for respectively transmitting the first and second signals to the plurality of access points; and a clock generator for generating the first and second clocks, a predetermined phase difference existing between the first clock and the second clock and the first clock and the second clock having the same frequency, wherein the clock generator comprises: a phase detector for detecting a frequency error or a phase error between a reference clock and an oscillating clock and generating a corresponding error signal; a charge pump electrically connected to the phase detector for generating a control signal according to the error signal; and a ring-disposed oscillator electrically connected to the charge pump for adjusting the frequency of the oscillating clock according to the control signal, the ring-disposed oscillator comprising a plurality of inverters, each inverter capable of inverting signals output from another inverter and delaying the signals by a time period to generate corresponding output signals, the ring-disposed oscillator capable of adjusting delaying time periods of the inverters and selecting an output signal output from one of the inverters as the oscillating clock, the plurality of inverters comprising a first inverter delaying signals by a first time period and a second inverter delaying signals by a second time period different from the first time period, wherein the first clock and the second clocks are selected as outputs of different inverters in the ring-disposed oscillator.