Patent ID: 8165164

Claim:
A mapping circuit for the mapping of input words of a first length into output words of a second length, comprising: a plurality of sample registers forming a shift register chain such that a first sample register in the chain is adapted to store an input word corresponding to a current cycle of a clock and successive sample registers in the plurality are adapted to store input words corresponding to successive preceding cycles of the clock; a plurality of multiplexers adapted to select bits from input words stored by the plurality of sample registers, the multiplexers corresponding to bit positions in output words such that each bit in the output words is selected by a corresponding multiplexer, wherein the selection by the multiplexers is configured by address signals; an output word register coupled to the multiplexers for storing the selected bits of input words to provide output words; and a memory for storing the address signals for the multiplexers, wherein: the address signals in the memory are arranged into a set of control words such that the selection by the multiplexers is configured by the control words; the output words are arranged into frames and each frame has the same number of output words as the number of control words in the set of control words; and the mapping circuit is configured to select control words from the set responsive to the clock.