Patent ID: 8253229

Claim:
A stacked layer type semiconductor package including a plurality of stacked semiconductor packages, each of the semiconductor packages comprising: a semiconductor chip; a substrate having a first surface provided with a concave portion in which the semiconductor chip is mounted in a face down condition, and a second surface opposite the first surface, the concave portion including a bottom surface and a sidewall surface extending from the bottom surface to the first surface of the substrate; and a wiring line structure constructed in such a manner that the wiring line structure externally connects to the semiconductor chip at least just above and just under the semiconductor chip, wherein the wiring line structure includes: a first pattern wiring line formed on the first surface of the substrate, the sidewall surface of the concave portion from the first surface of the substrate to the bottom surface of the concave portion, and the bottom surface of the concave portion, and connected with the semiconductor chip, a first insulating layer formed on the first surface of the substrate covering the concave portion and the semiconductor chip, a second insulating layer formed on the second surface of the substrate, and a second pattern wiring line formed on the second insulating layer and connected with the first pattern wiring line, and a third pattern wiring line formed on the first insulating layer and connected with the first pattern wiring line.