Patent ID: 7639046

Claim:
A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, said method comprising the steps of: deriving a local clock activation signal from an external clock activation signal which external clock activation signal if high specifies that a corresponding data signal is valid and has to be propagated through the synchronous circuit and if low specifies that a corresponding data signal is invalid and clock gating has to be performed, wherein said local clock activation signal changes its value every cycle the external clock activation signal is high; propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit; wherein the step of propagating the data signal and the local clock activation signal from a particular stage to a succeeding stage does not require using a first clock domain for a data register and a second clock domain for a control register; and wherein the derivation of the local clock activation signal from the external clock activation signal is performed in a first stage of the synchronous circuit, wherein a propagation of the local clock activation signal and of the data signal at the first stage is controlled by the external clock activation signal.