Patent ID: 8515374

Claim:
A PLL circuit comprising: a digitally controlled oscillator for oscillating at a frequency according to a set digital value; a phase detector for generating a phase error value by detecting an error between an output phase of the digitally controlled oscillator and a reference phase based on a set frequency control digital value; a loop filter for generating a first digital tuning value by multiplying a phase error value output from the phase detector by a predetermined loop gain; an oscillator gain normalization unit which generates a second digital tuning value set in the digitally controlled oscillator, by multiplying the first digital tuning value output from the loop filter by a predetermined reference frequency and dividing the value by a set gain of the digitally controlled oscillator; an oscillator gain estimation unit which estimates the gain of the digitally controlled oscillator, on the basis of the second digital tuning value output from the oscillator gain normalization unit; and a mode switch unit which switches the value of the loop gain set in the loop filter in a stepwise manner during tuning, wherein in a certain mode, the oscillator gain estimation unit estimates the gain of the digitally controlled oscillator from a ratio between a change of a frequency of the output signal of the digitally controlled oscillator and a change of the second digital tuning value obtained by changing the frequency control digital value, and the oscillator gain estimation unit estimates a gain of the digitally controlled oscillator in another mode, on the basis of a device parameter of the digitally controlled oscillator and the gain of the digitally controlled oscillator estimated in the certain mode.