Patent ID: 7863183

Claim:
A method comprising: providing a semiconductor device that comprises a last level copper interconnect embedded in a last level dielectric layer, said last level copper interconnect is a fat wire; forming an interfacial conductive cap structure that selectively covers the last level copper interconnect, wherein said interfacial conductive cap structure comprises CoWP, NiMoP, NiMoB, NiReP, NiWP, or combinations thereof; forming a first dielectric cap layer over the interfacial conductive cap structure and the last level dielectric layer, wherein the first dielectric cap layer comprises silicon nitride and has a thickness ranging from about 100 â„« to about 300 â„«; forming at least three additional dielectric cap layers over the first dielectric cap layer, which includes a silicon dioxide layer, a silicon nitride layer, and a photosensitive polyimide layer; forming a via through the first dielectric cap layer and the at least three additional dielectric cap layers to expose the interfacial conductive cap structure, wherein the via is formed by first selectively removing a portion of the at least three additional dielectric cap layers to expose the first dielectric cap layer, and then selectively removing the exposed portion of the first dielectric cap layer, stopping at the interfacial conductive cap structure; forming at least one ball-limiting metallurgy (BLM) layer in the via over the interfacial conductive cap structure; and forming at least one controlled-collapse chip connection (C4) over the at least one BLM layer.