Patent ID: 7867791

Claim:
A manufacturing method of a semiconductor device comprising: forming a first semiconductor layer, a second semiconductor layer and a third semiconductor layer; forming a gate insulating layer over the first semiconductor layer, the second semiconductor layer and the third semiconductor layer; forming a first conductive film over the gate insulating layer; forming a second conductive film over the first conductive film; forming, over the second conductive film and by using an exposure mask that transmits light at a plurality of intensities, a first mask layer overlapped with the first semiconductor layer, a second mask layer overlapped with the second semiconductor layer, and a third mask layer overlapped with the third semiconductor layer; etching the first conductive film and the second conductive film by using the first mask layer to form a first gate electrode layer and a second gate electrode layer; etching the first conductive film and the second conductive film by using the second mask layer to form a third gate electrode layer and a fourth gate electrode layer; etching the first conductive film and the second conductive film by using the third mask layer to form a first conductive layer and a second conductive layer; adding an impurity element imparting one conductivity type to the first semiconductor layer by using the first gate electrode layer and the second gate electrode layer as masks, to the second semiconductor layer by using the third gate electrode layer and the fourth gate electrode layer as masks, and to the third semiconductor layer by using the first conductive layer and the second conductive layer as masks, thereby forming in the first semiconductor layer a first high concentration impurity region and a first low concentration impurity region which is overlapped with the first gate electrode layer, forming in the second semiconductor layer a second high concentration impurity region, and forming in the third semiconductor layer a third high concentration impurity region and a third low concentration impurity region which is overlapped with the first conductive layer; forming a fourth mask layer over the second semiconductor layer, the third gate electrode layer, and the fourth gate electrode layer; forming a fifth mask layer over the third semiconductor layer, the first conductive layer and the second conductive layer; and removing a part of the first gate electrode layer overlapped with the first low concentration impurity region without removing a portion of the third gate electrode layer and the first conductive layer by using the fourth and fifth mask layers, and the second gate electrode layer as masks, wherein a capacitor is formed by the first conductive layer, the third low concentration impurity region and the gate insulating layer, and wherein the second conductive layer has a narrower width than the second gate electrode layer and the fourth gate electrode layer.