Patent ID: 7154793

Claim:
An integrated memory, comprising: a plurality of memory cells arranged in a memory cell array along word lines for selection of the memory cells and bit lines for reading out or writing data signals of the memory cells; a plurality of switches, one of the bit lines being connected to a data line by a respective one of the switches; a plurality of colunm select lines, one of the column select lines being connected to a plurality of the switches for driving the switches in an activated state in order to connect a number of bit lines to a same number of data lines; an access controller being connected to the column select lines and operable in a test operating mode such that a plurality of the column select lines can be activated in the event of a memory cell access; a plurality of sense amplifiers for evaluating and amplifying the data signals of the memory cells, the sense amplifiers each being connected to a respective bit line and arranged in a sense amplifier strip that subdivides the bit lines into two partial regions; and a plurality of isolation switches for respectively coupling the partial regions of one of the bit lines to the sense amplifiers of the sense amplifier strip, the isolation switches being driven by the access controller such that the partial regions of one of the bit lines can be connected to a respective sense amplifier of the sense amplifier strip.