Patent ID: 7023255

Claim:
A digital latch with a data jitter free clock load, comprising: a latch circuit having first and second data inputs, first and second data outputs, and a clock signal input, said latch circuit having a first load value relative to a clock driver when data at said first and second data inputs is non-changing, said latch circuit having a second load value relative to a clock driver when data at said first and second data inputs is changing; and a load compensation circuit, operatively connected to said first and second data inputs of said latch circuit and to said first and second data outputs of said latch circuit, said load compensation circuit providing a first compensation load value upon the clock driver when data at said first and second data inputs is non-changing and said load compensation circuit providing a second compensation load value relative upon the clock driver when data at said first and second data inputs is changing such that a sum of said first load value and said first compensation load value equals a sum of said second load value and said second compensation load value.