Patent ID: 7965561

Claim:
A memory device comprising: a plurality of memory cells, said memory cells being grouped in at least two memory sectors, a plurality of memory cell address signal lines respectively coupled to the memory cells; a first decoding circuit coupled to an address bus to receive address codes of the memory cells from the address bus and, in response thereto, to assert a plurality of decoding and selecting signals common to said at least two memory sectors; a plurality of second decoding circuits respectively coupled to said at least two memory sectors, each second decoding circuit also being coupled to the first decoding circuit to receive said plurality of decoding and selecting signals and to generate driving signals for driving said memory cell address signal lines depending on said decoding and selecting signals; and a plurality of voltage boosting blocks coupled to said first decoding circuit and to said plurality of second decoding circuits for receiving said plurality of decoding and selecting signals and shifting the plurality of decoding and selecting signals in voltage to a shifted-voltage level to generate respective shifted decoding and selecting signals common to the at least two memory sectors, and to provide the shifted decoding and selecting signals to the plurality of second decoding circuits to generate the driving signals.