Patent ID: 8241928

Claim:
A method for measuring a charge status for a test structure formed on a silicon substrate that results from a semiconductor processing step, the test structure having a gate electrode, a charge-trapping layer, and a diffusion region, the charge-trapping layer disposed between the silicon substrate and the gate electrode and directly contacting the gate electrode and silicon substrate, the method comprising: subjecting the test structure to the semiconductor processing step causing the charge trapping layer to accumulate charge during the semiconductor processing step; grounding the substrate; and applying bias voltages to the test structure, the bias voltages configured to generate a gate induced drain leakage current in the test structure, the gate induced drain leakage current related to the charge accumulated in the charge trapping layer of the test structure during the semiconductor processing step, wherein applying bias voltages comprises applying a first bias voltage to the gate electrode and a second bias voltage to the diffusion region, the first and second bias voltages having different polarities.