Patent ID: 8592280

Claim:
A field effect transistor device, comprising: a source region; a drain region; a patterned fin lithography hardmask overlaying a plurality of fins which connect the source region and the drain region, the fins having a pitch of between about 40 nanometers and about 200 nanometers and each of the fins having a width of between about ten nanometers and about 40 nanometers, and wherein each of the fins has a height variation of less than or equal to about five nanometers with the height variation in a given one of the fins being measured as a difference between a highest height value and a lowest height value throughout the given fin; and a gate stack over at least a portion of the fins, wherein the source region and the drain region are self-aligned with the gate stack, and wherein a gap is present between one or more of the source and drain regions and the gate stack.