Patent ID: 6930903

Claim:
A memory module comprising: a printed circuit board having a first lateral portion and a second lateral portion; a plurality of identical integrated circuits mounted in a first row and a second row onto at least one surface of the printed circuit board; a control logic bus connected to the plurality of identical integrated circuits, the control logic bus comprising a first set of address signal paths and a second set of address signal paths; and a first register and a second register connected to the control logic bus, the first register accessing a first range and a second range of data bits, the second register accessing a third range and a fourth range of data bits, the first range and the second range of data bits being first and second non-contiguous subsets of a data word, and the third range and the fourth range of data bits being third and fourth non-contiguous subsets of the data word, wherein the first set of address signal paths connect the first register to the integrated circuits of the first row and the second row on the first lateral portion and the second set of address signal paths connect the second register to the integrated circuits of the first row and the second row on the second lateral portion.