Patent ID: 7919843

Claim:
A semiconductor device comprising: a semiconductor substrate; an electrode pad; a semiconductor integrated circuit formed on the semiconductor substrate; an internal connection terminal arranged on the electrode pad and having a flat upper surface; an insulation layer formed on the surface of the semiconductor integrated circuit where the electrode pad is formed so as to expose the flat surface of the internal connection terminal; a wiring pattern formed on an upper surface of the insulation layer and the upper surface of the internal connection terminal, the wiring pattern electrically connected to the internal connection terminal; an external connection terminal arranged on a portion of an upper surface of the wiring pattern; and a solder resist for protecting the wiring pattern, wherein the solder resist is arranged to cover the upper surface of the wiring pattern which does not include the portion on which the external connection terminal is arranged and the solder resist is arranged to cover the side surface of the wiring pattern, and the area of the solder resist in plan view when the upper surface of the insulation layer is viewed from above is substantially the same as the area of the wiring pattern in plan view when the upper surface of the insulation layer is viewed from above.