Patent ID: 8803301

Claim:
A semiconductor package comprising: a substrate; at least a first semiconductor chip disposed on the substrate; at least a first communication terminal disposed on the substrate, the first communication terminal being electrically connected to the first semiconductor chip and to an external source; at least a first inducing terminal disposed on the substrate, the first inducing terminal being electrically connected to the semiconductor chip and to a ground; an external covering enclosing at least a portion of the first semiconductor chip, an external surface of the external covering being exposed to the outside of the semiconductor package; a static electricity blocking layer disposed between the external covering and the first inducing terminal and between the external covering and the first communication terminal, the static electricity blocking layer configured to prevent a conductive pathway from being formed between the external covering and the first communication terminal; and at least a first opening formed in the static electricity blocking layer, wherein the external covering is configured to be electrically connected to the first inducing terminal via the first opening.