Patent ID: 8066891

Claim:
A process for producing an electronic circuit component comprising the steps of: providing a laminate having a layer construction of first conductive inorganic material layer-insulating layer-second conductive inorganic material layer or a layer construction of conductive inorganic material layer-insulating layer, the insulating layer comprising a laminate of two or more wet etchable insulating unit layers, at the interface between at least one of the conductive inorganic material layers and the insulating layer, surface irregularities of the conductive inorganic material layer having been transferred onto the surface of the insulating layer, the average height of the surface irregularities transferred onto the insulating layer being less than the thickness of the outermost insulating unit layer in the insulating layer, the average height of profile irregularities being expressed in terms of mean roughness Rz specified in JIS (Japanese Industrial Standards) C 6515, the thickness of the insulating unit layer being 1.1 to 3 times Rz; and wet etching the laminate to produce the electronic circuit component.