Patent ID: 7943530

Claim:
A method of forming a semiconductor structure, the method comprising: patterning a first semiconductor structure including a first semiconductor link portion, wherein said first semiconductor structure has a first pair of sidewalls that are separated by a first width w 1 and has a first surface orientation having a first oxidation rate in an oxidizing ambient; patterning a second semiconductor structure including a second semiconductor link portion, wherein said second semiconductor link portion has a second pair of sidewalls that are separated by a second width w 2 and has a second surface orientation having a second oxidation rate in said oxidizing ambient; forming a first semiconductor nanowire having a third width w 3 by thinning said first semiconductor link portion at said first oxidation rate; and forming a second semiconductor nanowire having a fourth width w 4 by thinning said second semiconductor link portion at said second oxidation rate, wherein said third width w 3 and said fourth width w 4 are sublithographic dimensions.