Patent ID: 6895423

Claim:
An apparatus for performing a product-sum operation by multiplying and adding floating point number data representing a floating point number using a bit string, comprising: a multiplication unit performing a multiplication on the floating point number data; an addition unit performing an addition on the floating point number data; a rounding unit performing a rounding process on the floating point number data obtained as a result of the addition performed by said addition unit; a result storage unit storing a result of the product-sum operation by adding third data which is floating point number data to a product of first data and second data which are floating point number data; a multiplication control unit allowing said multiplication unit to compute multiplication result data which is a result of the multiplication of the first data and the second data; a first addition control unit allowing said addition unit to compute first addition result data obtained by adding the third data to less significant digit multiplication result data having a fixed-point part formed by a bit string representing the less significant digits in two divisions obtained by dividing a bit string representing the fixed-point part of the multiplication result data into more significant digits and less significant digits; and a second addition control unit allowing said addition unit to compute second addition result data obtained by adding more significant digit multiplication result data having a fixed-point part formed by a bit string representing more significant digits to the first addition result data, wherein said result storage unit stores first product-sum operation result data which is floating point number data obtained by said rounding unit performing a rounding process on the second addition result data.