Patent ID: 7411255

Claim:
A semiconductor device comprising: a substrate; a plurality of diffusion regions formed in the substrate, the plurality of diffusion regions includes a first diffusion region, a second diffusion region, and a third diffusion region; a plurality of gate structures formed over the substrate, the plurality of gate structures includes a first gate structure formed over a channel region between the first and second diffusion regions, and a second gate structure formed over a channel region between the second and third diffusion regions, wherein the first gate structure and the first and second diffusion regions form at least a portion of a first memory cell with the first diffusion region formed at least a portion of a storage node of the first memory cell, and wherein the second gate structure and the second and third diffusion regions form at least a portion of a second memory cell; a diffusion barrier including an alumina layer formed on the gate structures, wherein the alumina layer remains in the semiconductor device after the semiconductor device is formed, wherein a first portion of the alumina layer completely covers a top surface of the first gate structure and completely covers a top surface of the second gate structure, wherein a second portion of the alumina layer is below the top surface of at least one of the first and second gate structures, wherein the diffusion barrier layer includes a first insulating layer and a second insulating layer, wherein the alumina layer is between the first and second insulating layers, wherein each of the first and second insulating layers includes a first portion above the top surface of each of the first and second gate structures, and wherein each of the first and second insulating layers includes a second portion below the top surface of at least one of the first and second gate structures; and a doped glass layer formed on the diffusion barrier.