Patent ID: 7586350

Claim:
A semiconductor memory device, comprising: a power-up signal generating unit for generating a power-up signal; an internal reset signal generating unit for generating an internal reset signal based on a pad signal inputted from an arbitrary external pin during a test mode; an internal logic initializing signal generating unit for generating an internal logic initializing signal based on the power-up signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initializing signal; wherein the semiconductor memory device excludes a dedicated external reset pin, the internal logic initializing signal generating unit outputs the internal logic initializing signal activated when any one of the power-up signal and the internal reset signal is activated, and the internal logic initializing signal generating unit includes, a first transfer gate for transferring the power-lip signal in response to an inverted test mode signal, a second transfer gate for transferring the internal reset signal in response to the test mode signal, a latch unit for latching a signal at a common output node of the first and second transfer gates, and an inverter for inverting an output of the latch unit to output the internal logic initializing signal.