Patent ID: 7284212

Claim:
A method of reducing computational resources in characterizing a parameter for a combination of an input pin and an output pin of a cell, said cell being contained in a library used in the design of an integrated circuit, said method comprises: determining a worst case vector, wherein said worst case vector represents a set of input bits, with each of said input bits being applied to a corresponding one of a set of input pins wherein the corresponding one is other than said input pin of said combination, wherein said worst case vector would cause propagation of most noise from said input pin to said output pin among vectors which would cause a bit value transition on said output pin if the input bit value is changed on said input pin; computing a plurality of data values for said parameter when said worst case vector is applied to said set of input pins, wherein said plurality of data values are used in an analysis of said integrated circuit irrespective of which of said vectors is applied to said set of input pins; and wherein said parameter comprises noise immunity, wherein a failure result is deemed to be obtained for an input glitch of a first height and a first width if the height of an output glitch corresponding to said input glitch exceeds a first threshold voltage, and a success result is deemed to be obtained otherwise, said method further comprises generating a noise immunity curve (NIC) corresponding to only said worst case vector, wherein said NIC contains a plurality of immunity transition points, wherein each of said plurality of immunity transition points indicates a minimum value for one dimension of said input glitch required for said failure result for each of a value of the other dimension.