Patent ID: 8536951

Claim:
An apparatus comprising: a buffering stage that receives an enable signal and an input signal and that provides an output signal, wherein the buffering stage includes: an input stage that is activated and deactivated by the enable signal; a buffering substage that includes a buffering transistor that is coupled to the input stage, wherein the buffering transistor is formed on a substrate, and wherein the buffering transistor has a channel with a doping concentration that is approximately the same as the substrate; and a current control circuit that is coupled to the buffering substage; and a bandgap stage that is coupled to the current control circuit and that is activated and deactivated by the enable signal, wherein the buffering transistor further comprises a plurality of NMOS buffering transistors, and wherein the buffering substage further comprises a plurality of branches that are in parallel with one another, and wherein each branch includes at least one of the plurality of NMOS buffering transistors, and wherein each branch includes: a PMOS transistor that receives the enable signal at its gate and that is coupled to the drain of its NMOS buffering transistor at its drain; a resistor that is coupled to the source of its NMOS buffering transistor; and an NMOS transistor that is coupled to the source of its NMOS buffering transistor at its drain.