Patent ID: 7733683

Claim:
A semiconductor memory device comprising: at least one plate line; bit lines, each of the bit lines having a first portion and a second portion; memory cells, each of the memory cells being coupled between one of the first portions of the bit lines and the at least one plate line, each of the memory cells including a ferroelectric capacitor and a cell transistor; word lines, each of the word lines being connected to ones of the gates of the cell transistors; sense amplifiers to amplify and hold data, each of the sense amplifiers being connected to at least one of the second portions of the bit lines; bit-line selecting transistors, each of the bit-line selecting transistors being connected between one of the memory cells and one of the first portions of the bit lines; and separating transistors, each of the separating transistors having a source, a drain, and a gate, one of the source and the drain being connected to the first portion of a corresponding one of the bit lines, the other of the source and the drain being connected to the second portion of the corresponding one of the bit lines, and the gate being connected to a separation control line to provide a separation control signal, wherein the semiconductor memory device performs dropping a voltage of the separation control signal from a third voltage to a fourth voltage, after a voltage of the at least one plate line rises from a first voltage to a second voltage; subsequently, raising the voltage of the separation control signal from the fourth voltage to a fifth voltage lower than the third voltage; dropping the voltage of the at least one plate line from the second voltage to the first voltage, after the rise of the voltage of the separation control signal from the fourth voltage to the fifth voltage; and subsequently, raising the voltage of the separation control signal from the fifth voltage to the third voltage.