Patent ID: 7609581

Claim:
A semiconductor memory device comprising: a memory cell array provided in a cell array area and including a plurality of memory cells, each memory cell being of a static type and formed of MIS transistors; a source potential line which applies a source potential to the memory cells; a switching element group including a plurality of switching elements and provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a power supply potential line, when the memory cells are in an operation mode, and electrically disconnecting the source potential line from a ground potential line, when the memory cells are in a sleep mode; a first N-type MIS transistor connected between the source potential line and the power supply potential line, and fixing the source potential when the memory cells are in the sleep mode; and a bias generation circuit provided in a peripheral circuit area outside the cell array area, and supplying a first bias potential to a gate terminal included in the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.