Patent ID: 8207784

Claim:
A leakage control circuit for a logic gate, comprising: a logic gate comprising a first N-type metal-oxide semiconductor (NMOS) transistor and a first P-type metal-oxide semiconductor (PMOS) transistor, each transistor having a body terminal, a drain terminal, a source terminal, and a gate terminal, and where at least the gate terminal of the first PMOS transistor and the gate terminal of the NMOS transistor are connected; and a control circuit coupled to said logic gate via any of said first NMOS transistor and said PMOS transistor, said control circuit comprising: a first metal-oxide semiconductor (MOS) transistor having a drain terminal connected to the body terminal of any of said first NMOS transistor and said first PMOS transistor to bring said body terminal to a first reference potential, and a gate terminal of said first MOS transistor connected to the drain terminal of any of said first NMOS transistor and said first PMOS transistor, wherein a body terminal of the first MOS transistor is grounded; and a second MOS transistor having a source terminal connected to said body terminal of any of said first NMOS transistor and said first PMOS transistor to bring said body terminal to a second reference potential, and a gate terminal of said second MOS transistor connected to the gate terminal of any of said first NMOS transistor and said first PMOS transistor, said second reference potential provided by a positive body bias voltage supply connected to a drain terminal of the second MOS transistor and having a potential higher than a common ground for said NMOS transistor or a bias voltage supply having a potential lower than a common supply voltage of said PMOS transistor that provides a bias voltage to establish a predetermined current enhancement ratio (CER), wherein a body terminal of the second MOS transistor is grounded.