Patent ID: 8101472

Claim:
A method for manufacturing a thin film transistor substrate comprising thin film transistors, each of the thin film transistors comprising: a semiconductor film portion formed on an insulating substrate; a gate insulating film portion laminated on the semiconductor film portion; a gate made of a metal film portion formed on the gate insulating film portion; and a channel formed in a region covered by the gate, which is formed of the semiconductor film portion, the thin film transistor substrate comprising: an n-type thin film transistor having regions of the semiconductor film portion, which are not covered by the gate and to which n-type impurities are doped, the regions becoming a source and a drain; a p-type thin film transistor having regions of the semiconductor film portion, which are not covered by the gate and to which p-type impurities are doped, the regions becoming a source and a drain; and a capacitor including: a lower capacitor electrode formed in a region of another semiconductor film portion, to which the n-type impurities are doped, the another semiconductor film portion being formed on the same layer as the semiconductor film portion; an upper capacitor electrode made of a metal film portion; and another insulating film portion formed on the same layer as the gate insulating film portion to be interposed between the lower capacitor electrode and the upper capacitor electrode, the method comprising: processing the gate of the n-type thin film transistor, the gate of the p-type thin film transistor, and the upper capacitor electrode by using a first mask and a second mask; and changing impurity concentrations of semiconductor film portions located in regions which become the channel of the n-type thin film transistor, the source and the drain of the n-type thin film transistor, the channel of the p-type thin film transistor, the source and the drain of the p-type thin film transistor, and the lower capacitor electrode, by using only a pattern of the first mask and a pattern of the second mask, the first mask being a half-tone mask having a transparent region, an opaque region, and a semitransparent region, the second mask having a transparent region and an opaque region, wherein boundaries between the channel of the n-type thin film transistor and the source and the drain of the n-type thin film transistor, and boundaries between the channel of the p-type thin film transistor and the source and the drain of the p-type thin film transistor are defined by boundaries other than a boundary between the opaque region and the semitransparent region of the half-tone mask or a boundary between the opaque region and the transparent region of the half-tone mask.