Patent ID: 8184474

Claim:
An integrated circuit, comprising: an array of SRAM cells, each said SRAM cell comprising: a Vdd node; a PMOS bit-side load transistor; said bit-side load transistor further including a gate node, a source node and a drain node, wherein said source node of said bit-side load transistor is connected to said Vdd node; a bit-side data node, wherein said bit-side data node is connected to said drain node of said bit-side load transistor; an NMOS bit-side driver transistor, said bit-side driver transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-side driver transistor is connected to said bit-side data node; a Vss node, wherein said Vss node is connected to said source node of said bit-side driver transistor; a PMOS bit-bar-side load transistor; said bit-bar-side load transistor further including a gate node, a source node and a drain node, wherein said source node of said bit-bar-side load transistor is connected to said Vdd node and said gate node of said bit-bar-side load transistor is connected to said bit-side data node; a bit-bar-side data node, wherein said bit-bar-side data node is connected to said drain node of said bit-bar-side load transistor, to said gate node of said bit-side load transistor and to said gate node of said bit-side driver transistor; an NMOS bit-bar-side driver transistor, said bit-bar-side driver transistor further including a gate node, a source node and a drain node, wherein said drain node of said bit-bar-side driver transistor is connected to said bit-bar-side data node, said source node of said bit-bar-side driver transistor is connected to said Vss node, and said gate node of said bit-bar-side driver transistor is connected to said bit-side data node; a bit-side passgate transistor, said bit-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, wherein said gate node of said bit-side passgate transistor is connected to a word line, said first source/drain node of said bit-side passgate transistor is connected to said bit-side data node and said second source/drain node of said bit-side passgate transistor is connected to a bit data line; a bit-bar-side passgate transistor, said bit-bar-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, wherein said gate node of said bit-bar-side passgate transistor is connected to said word line, said first source/drain node of said bit-bar-side passgate transistor is connected to said bit-bar-side data node and said second source/drain node of said bit-bar-side passgate transistor is connected to a bit-bar data line; and an auxiliary transistor, said auxiliary transistor further including a gate node, a source node and a drain node, wherein said gate node of said auxiliary transistor is connected to said bit-bar-side data node, and said drain node of said auxiliary transistor is connected to said bit-side data node.