Patent ID: 8214554

Claim:
A data transfer circuit comprising: a controller that transfers data stored in a memory to a communication path; a first storage area for storing first pointer information used for reading, from the memory, first data generated in synchronization with a cycle for transferring data to the communication path; and a second storage area for storing second pointer information used for reading, from the memory, second data generated out of synchronization with the cycle for transferring data, wherein the controller is configured to: store, in one cycle for transferring data, the first and second pointer information read from the memory respectively in the first and second storage areas, and sequentially transfer to the communication path the first and second data read from the memory by referring to the first and second pointer information; update, if transfer by a data length indicated in the second pointer information has not been completed upon the transfer of the second data, the data length to a data length of the remaining data, and update an address indicated in the second pointer information to an address on the memory of the remaining data; and read, in the next cycle for transferring data, the remaining data from the memory by referring to the second pointer information, and transfer the remaining data to the communication path.