Patent ID: 7386706

Claim:
A data processing system comprising: (a) a bus coupling components in the data processing system; (b) an external memory coupled to the bus; (c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising: a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a register file coupled to the data path and containing a plurality of registers; and an execution unit coupled to the data path, the execution unit configurable to perform a group instruction that operates on a plurality of data elements in partitioned fields of a register to produce a catenated result, the execution unit further configurable to execute: (i) an aligned instruction operable to copy first data according to an aligned memory address, the first data having a data width, the data width specified as a fixed value by the aligned instruction, the aligned memory address being one of a plurality of memory addresses regularly spaced at alignment boundaries separated by the data width; and (ii) an unaligned instruction operable to copy second data according to an unaligned memory address, the second data having the data width, the data width specified as a fixed value by the unaligned instruction, the second data being permitted to cross an alignment boundary of the data width, the unaligned memory address being a memory address that is not constrained to be one of the plurality of memory addresses regularly spaced at alignment boundaries separated by the data width.