Patent ID: 7519927

Claim:
A computer implemented method for an integrated circuit design tool to form interconnect wiring in an integrated circuit design, the method comprising: providing as input a clock netlist of a clock distribution network which comprises a list of logic books forming the clock distribution network and which specifies interconnections between test clock pins, launch clock pins and capture clock pins of source and sink logic books; providing as input a placement information that specifies a physical location assigned to each logic book of the clock netlist in a layout of a top-level circuit; for each logic book in the clock distribution network, adding a temporary clock pin at a point in a block level layout of that logic book, which is equidistant from the launch and capture clock pins of that logic book; forming a physical interconnect between the temporary pins of a source logic book and sink logic book using one or more five parallel track wire segments, wherein for each five parallel track wire segment forming an interconnect, a center track is specified as a test clock signal wire, a first pair of adjacent tracks on a first side of the center track is specified as launch clock wire and a second pair of adjacent tracks on a second side of the center track specified as a capture clock wire, wherein the launch and capture clock wires each comprise (i) a signal wire track disposed on opposing sides of the center test clock signal wire to act a shield between the launch and capture clock signal wire tracks, and (ii) an empty track or shielding wire track disposed adjacent the clock signal wire track that serves to isolate or shield the launch and capture clock signal wires; for each logic book, forming single wire connections between the test, launch and capture of that logic book and open ends of the test, launch and capture signal wires at the temporary pin; and removing the temporary pins in the block level layout of each logic book in the clock distribution network.