Patent ID: 7015095

Claim:
A method for fabricating a semiconductor memory having charge trapping memory cells, the method comprising: forming isolation regions in a semiconductor body; forming channel regions of memory transistors in the semiconductor body; forming a dielectric storage layer sequence over the channel regions, the dielectric storage layer sequence comprising a first boundary layer, a storage layer and a second boundary layer; applying a first electrically conductive material over the semiconductor body; patterning the first electrically conductive material to form word lines that run parallel at a distance from one another; forming source/drain regions by introducing dopant in the semiconductor body adjacent the word lines; introducing a second electrically conductive material between ones of the word lines; and partially removing the second electrically conductive material using a mask in such a way that residual portions of the second electrically conductive material fills a section of a the space between two word lines and produces an electrical contact with at least one of the source/drain regions.