Patent ID: 8593189

Claim:
A multi-phase time-to-digital converter (TDC) for a phase locked loop (PLL), comprising: a first phase finder configured to generate a first fractional phase signal of a multi-phase variable clock (CKV) signal based on at least one of the multi-phase CKV signal or a reference frequency (FREF) signal, the multi-phase CKV signal associated with one or more clock signals and one or more corresponding phases; a phase predictor configured to generate at least one of: a phase select (QSEL) signal associated with a fractional frequency command word (FCW) signal based on at least one of a FCW signal or a phase reference (PHR) signal; or a multi-phase CKV select (CKVSEL) signal corresponding to a clock signal of the one or more clock signals and a phase of the one or more corresponding phases based on at least one of the multi-phase CKV signal or the QSEL signal; a second phase finder configured to generate a second fractional phase signal of the multi-phase CKV signal based on at least one of the CKVSEL signal or the QSEL signal; and a phase switch configured to select at least one of the first fractional phase signal or the second fractional phase signal based on a phase error (PHE) signal.