Patent ID: 7493478

Claim:
A method of managing state information in a processor, the method comprising: storing soft state information that is non-critical for executing a process in the processor within the processor as the process is executing; in response to receiving a process interrupt at the processor, storing at least a portion of the soft state information to a memory that is coupled to the processor, wherein the process interrupt is caused by an event outside the processor; in response to the processor completing a handling of the process interrupt, restoring the soft state information from the memory back into the processor, wherein the process is able to resume running immediately upon a loading of a hard architected state for the process; storing within the processor a hard architected state, wherein the hard architected state is information within the processor that is architecturally required for the processor to execute the process from a present point in the process, and wherein the information comprises information that is stored in a Link and Count Register (LCR), wherein the LCR contains a count register, a link register and rename registers that enable a Branch Execution Unit (BEU) to resolve conditional branches to obtain a path address for the process; storing a shadow copy of the hard architected state within the processor, and in response to receiving a process interrupt at the processor, storing the shadow copy of the hard architected state in the memory: and modifying the hard architected state without regard to completion of the storing of the shadow copy in the memory.