Patent ID: 8374842

Claim:
A device emulation support apparatus communicably connected via a bus to a Central Processing Unit (CPU) for performing an emulation process by generating an exception, comprising: a hardware monitoring address storing section for storing an address corresponding to a peripheral device to be emulated as an address to be monitored; an access monitoring section for monitoring an access to the peripheral device from the CPU and obtaining access information including an address conforming to the address stored in the monitoring address storing section from an access signal including the access information with the address corresponding to the peripheral device to be accessed and output from the CPU to the peripheral device; an access storing section for storing the access information obtained by the access monitoring section; a read data storing section for temporarily storing data to be read from the peripheral device when the access is a read access indicating data reading; an exception generating section for transmitting an exception generation notification to the CPU to cause the CPU to generate an exception; an access judging section for receiving the access information obtained by the access monitoring section, comparing the received access information with last access information stored in the access storing section, storing the received access information in the access storing section, and requesting the exception generating section to transmit the exception generation notification to the CPU, when the received access information is different from the last access information while excluding the last access information stored in the access storing section from being further compared when the received access information is the same as the last access information; and an access completing section for outputting the data stored in the read data storing section to the CPU and instructing the CPU to complete the read access when the access monitored by the access monitoring section is the read access while instructing the CPU to complete a write access indicating data writing when the access monitored by the access monitoring section is the write access.