Patent ID: 8686977

Claim:
A timing controller for a display apparatus, the controller comprising: a data mapper structured and configured to receive, at a first rate that is defined by a first clock (CK 1 ) having a first frequency, a plurality of first image data words having a configuration of M-bits per word, wherein the first image data words are supplied to the data mapper in synchronization with the first clock (CK 1 ), the data mapper being further structured and configured to convert the received first image data words into a corresponding plurality of second image data words having a different configuration of P-bits per word so that the plurality of second image data words match a bandwidth of a prespecified memory, the data mapper being further structured and configured to output the second image data words to the prespecified memory that is structured and configured to input storable data words having the P-bits per word configuration and to store the received second image data words at a rate defined by a second clock (CK 2 ) operating at a second frequency different than the first frequency of the first clock (CK 1 ), wherein a relation between the second frequency and the first frequency depends at least on P; and a data remapper connected, structured, and configured to read from the prespecified memory ones of the second image data words that have been stored in the prespecified memory, wherein reading by the data remapper occurs in synchronization with the second clock (CK 2 ), and wherein the data remapper is further structured and configured to reconvert the second image data words into corresponding third image data words having a configuration of M-bits per word.