Patent ID: 7313027

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of blocks each including a plurality of electrically reprogrammable nonvolatile memory cells; a first circuit for selecting one from said plurality of blocks, said first circuit having a plurality of transistors connected to word lines connected to some of said nonvolatile memory cells; and a second circuit for generating a first voltage V 1 , a second voltage V 2 and a third voltage V 3 (V 3 <V 2 <V 1 ), said first voltage V 1 being applied to a source or drain of one of said transistors connected to a selected word line at a timing of programming, said second voltage V 2 being applied to sources or drains of some of said transistors connected to non-selected word lines at the timing of programming, and said third voltage V 3 being applied to a source or a drain of one of said transistors connected to at least one of said non-selected word lines at the timing of programming, said third voltage V 3 being higher than a well or substrate voltage of said plurality of transistors.