Patent ID: 8735273

Claim:
A method comprising: forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate; forming a first opening in the passivation layer, wherein a portion of the metal pad is exposed through the first opening; forming a seed layer over the passivation layer, wherein the seed layer is electrically coupled to the metal pad; forming a first mask over the seed layer, wherein the first mask comprises a second opening, with the second opening being directly over at least a portion of the metal pad; forming a post-passivation interconnect (PPI) over the seed layer and in the second opening; forming a second mask over the first mask; forming a third opening in the second mask, wherein the third opening is misaligned from the first opening; forming at least a portion of a metal bump in the third opening; and after the step of forming the portion of the metal bump, removing the first and the second masks.