Patent ID: 8502229

Claim:
An array substrate, comprising: a substrate having a pixel region; a gate electrode on the substrate; a gate insulating layer on the gate electrode; an oxide semiconductor layer on the gate insulating layer; an auxiliary pattern on the oxide semiconductor layer, the auxiliary pattern having a same shape as the oxide semiconductor layer; source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, said exposed portion of the auxiliary pattern covering an entire channel region of the oxide semiconductor layer and including a metal oxide; a data line over the gate insulating layer, the data line connected to the source electrode; a passivation layer on the source and drain electrodes and the data line, the passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the drain contact hole.