Patent ID: 8145881

Claim:
A data processing device comprising: a multidimensional array of data processing coarse grained logic elements (PAEs) that are operated at a first clock rate and that communicate with at least one of (a) one another and (b) other elements via at least one of (i) busses and (ii) communication lines operated at a second clock rate; wherein: the first clock rate is higher than the second; the coarse grained logic elements comprise storage means for storing data needed to be processed; the array is controlled to perform data-flow data processing; the data-flow data processing has a main data flow direction; said coarse grained logic elements include at least one coarse grained hardware logic element adapted to effect data processing while allowing data to flow in said main data flow direction; the at least one coarse grained logic element includes a coarse grained logic element that includes a first ALU having an upstream input side and a data downstream output side and a second ALU that provides for data flow in a direction reverse from that of the first ALU; and an instruction set for the first ALU is a subset of an instruction set for the second ALU.