Patent ID: 8754467

Claim:
A semiconductor device, comprising: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures, wherein the element isolation insulating layer includes at least one of SiO 2 , SiN, and SiON; wherein the upper insulating layer is an oxide containing Al, La, and Si; wherein a ratio N Si /N La of the number N Si of Si to the number N La of La is equal to or lower than a ratio with which permittivity of the upper insulating layer matches that of Al 2 O 3 ; wherein a ratio N Al /N La of the number N Al of Al to the number N La of La is equal to or higher than 0.0625 and is equal to or lower than 96; wherein a ratio N Si /(N La +N Al ) of the number N Si of Si to the sum of the numbers N La and N Al of La and Al contained in the upper insulating layer is equal to or higher than 0.6; and wherein respective lengths L charge , L top , and L gate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “L charge <L top and L gate <L top ”.