Patent ID: 8446017

Claim:
A wafer level package comprising a first semiconductor die having metal pillars, a second semiconductor die connected to the first semiconductor die, an encapsulant covering the first semiconductor die and the second semiconductor die, a plurality of redistribution layers that extend over both an upper surface of the second semiconductor die and an upper surface of the encapsulant and are electrically connected to the metal pillars, and a plurality of solder balls connected to the redistribution layers, wherein the first semiconductor die has a plurality of bond pads and one or more of the metal pillars is directly formed on a respective one of the bond pads, and the encapsulant directly encapsulates one of the one or more metal pillars, wherein upper surfaces of the metal pillars, the second semiconductor die and the encapsulant are coplanar, and wherein a passivation layer is formed on an upper surface of the second semiconductor die and an upper surface of the encapsulant, and the passivation layer is positioned beneath the redistribution layers.