Patent ID: 6853226

Claim:
A register controlled delayed lock loop for use in a semiconductor memory device, comprising: a delay line having a plurality of delay cell units for delaying a non-delayed input clock signal; a delay model, which receives the signal outputted from the delay line, for reflecting a delay condition for an actual clock signal path of the non-delayed input clock signal passing through the delay line; a delay means for delaying an output signal of the delay model for a predetermined time; an acceleration mode delay controller for controlling the delay value in an acceleration mode according to operation frequently information; a first phase comparator for comparing a phase of the output signal provided from the delay model with that of the non-delayed input clock signal; a second phase comparator for comparing a phase of the output signal of the delay means with that of the non-delayed input clock signal; a mode decision means for determining a continuous execution or termination of the acceleration mode in response to output signals of the first and second phase comparators; a shift register control means for outputting a left shift signal, a right shift signal and an acceleration shift signal in response to output signals of the first phase comparator and the mode decision means; and a shift register for controlling a delay value of the delay line in response to output signals of the shift register control means and the acceleration mode delay controller.