Patent ID: 8393526

Claim:
A method for wafer level packaging of electronic devices, comprising: melting solder for a solder jet; depositing the melted solder from the solder jet in a pattern on a substrate of a first component of a wafer level package electronic device, the pattern comprising a plurality of individual dots of melted solder; depositing additional melted solder from the solder jet to form columns of solder dots at three or more points on the substrate of the first component for providing a vacuum conductance gap between the first component of the electronic device and the second component of the electronic device; aligning a second component of the electronic device with the pattern deposited on the first component of the electronic device such that the second component is elevated from the first component and a portion of the pattern by the columns of solder formed with the additional melted solder; re-melting the solder deposited in the pattern and in the columns on the first component of the electronic device; and while the solder is re-melting, compressing the first component of the electronic device and the second component of the electronic device wherein reflow of the solder deposited in the columns and in the pattern and bonding of the first and second components occur simultaneously to join the second component to the portion of the pattern.