Patent ID: 8829961

Claim:
A clock generator comprising: a delay circuit configured to have 2N delay stages, in which a delay time from a first delay stage of the 2N delay stages to a last delay stage of the 2N delay stages is set to a length of a time of one cycle of an input clock input to the delay circuit, N being an integer; a first phase detector configured to detect a first phase difference between the input clock to the first delay stage and an output clock from the last delay stage; a first charge pump configured to generate a first current according to the first phase difference; a first loop filter configured to adjust an amount of delay applied to each of the 2N delay stages, based on a first voltage obtained by integrating the first current; a second phase detector configured to detect a second phase difference between the input clock to the first delay stage and an output clock from an Nth delay stage; a second charge pump configured to generate a second current according to the second phase difference; and a second loop filter configured to adjust a duty ratio of an output clock from each of the 2N delay stages, based on a second voltage obtained by integrating the second current.