Patent ID: 8750430

Claim:
A data receiver circuit to convert serial data into parallel data in accordance with a data rate signal and output the parallel data, the data receiver circuit comprising: a clock generator to generate a reference clock based on an input clock; a data latch to latch the serial data and output first serial data in accordance with the reference clock; a first data output section to convert the first serial data into first parallel data with a first reference clock when the data rate signal indicates a first data rate is equal to a data rate of the reference clock; and a second data output section to convert the first serial data into second parallel data with a second reference clock when the data rate signal indicates a second data rate slower than the data rate of the reference clock, the second data output section includes; a first demultiplexer to convert the first serial data into third parallel data, an edge detector to detect a change point of the third parallel data, and output change point information indicating the change point; a counter to determine a selection bit from among each of the third parallel data in accordance with the change point information, and output selection bit information indicating the selection bit; a selector to extract 1-bit data from among the third parallel data in accordance with the selection bit information and outputting the extracted 1-bit data, and a second demultiplexer section to rearrange the output 1-bit data into the second parallel data, and output the second parallel data as 4-bit parallel data.