Patent ID: 7898009

Claim:
A semiconductor memory cell, comprising: a substrate; a substrate dielectric disposed on the substrate; an Independently-Double-Gated (IDG) Hysteresis Field Effect Transistor (HyFET); and an Independently-Double-Gated (IDG) Field Effect Transistor (FET), wherein the IDG HyFET includes a bottom gate disposed on the substrate dielectric, a source disposed above the substrate dielectric and having a source extension extending from a main body of the source, a drain disposed above the substrate dielectric and having a drain extension extending from a main body of the drain, a channel disposed on the bottom gate and coupled to and disposed between the source and the drain, the channel creating a junction contact with the bottom gate to form a JFET, a hysteresis-producing material disposed above the channel, a top gate disposed above the hysteresis-producing material, wherein the top gate completes a Metal—Hysteresis-producing material—Semiconductor structure to form a Hysteresis FET (HyFET), a first local interconnect coupled to the top gate, a second local interconnect insulated from the first local interconnect and coupled to the bottom gate, a first insulating spacer disposed between the top gate and the source and proximate to the source extension, and a second insulating spacer disposed between the top gate and the drain and proximate to the drain extension; and a first control signal line coupled to the top gate, and wherein the IDG FET includes a bottom gate disposed on the substrate dielectric, a source disposed above the substrate dielectric and having a source extension extending from a main body of the source, a drain disposed above the substrate dielectric and having a drain extension extending from a main body of the drain, a channel confined by being coupled between the source extension and the drain extension, the channel making a junction contact to the bottom gate to form a JFET, a top gate disposed above the channel, a first local interconnect of the IDG FET coupled to the top gate, a first insulating spacer disposed between the top gate and the source and proximate to the source extension, a second insulating spacer disposed between the top gate and the drain and proximate to the drain extension, and a second local interconnect of the IDG FET insulated from the first local interconnect of the IDG FET and coupled to the bottom gate, and wherein the drain of the IDG FET is coupled to a first data signal line, the source of the IDG FET is coupled to the drain of the IDG HyFET, and the top gate of the IDG FET is coupled to a second control signal line.