Patent ID: 7089137

Claim:
A test platform for testing latch-up phenomenon of a chip comprising: a memory; a parameter measurement unit (PMU) for providing a current source to the chip and measuring the current between a power end and a ground end of the chip; a latch-up test program stored in the memory comprising: a path setup program code for obtaining a test program of the chip; a pin setup program code for obtaining a pin of the chip by the test program of the chip; an initial setup program code for setting the input pin of the chip with an initial value; a current measuring setup program code for driving the PMU to measure the current between the power end and the ground end of the chip to see if the current exceeds a first predetermined value; and a current providing setup program code for driving the PMU to provide a test current to the pin of the chip; and a processor for executing programs stored in the memory, controlling the PMU to increase the test current between the power end and the ground end of the chip until the test current exceeds a predetermined value, and determining that the chip passes the latch-up test if the test current exceeds the second predetermined value and the current between the power end and the ground end of the chip does not exceed the first predetermined value.