Patent ID: 8304830

Claim:
A semiconductor structure comprising: a substrate formed of a first conductivity type; an epitaxial layer formed over the substrate; a first well region of a second conductivity type formed in the epitaxial layer; a second well region of the second conductivity type formed in the epitaxial layer and spaced apart from the first well region; a third well region of the first conductivity type formed between the first well region and the second well region; a field region of the first conductivity type formed in a surface of the third well region and spaced apart from the first well region and the second well region; and a drain region of the first conductivity type formed in a surface of and extending into the field region; a buried region of the second conductivity type formed in the epitaxial layer and extending into the substrate, wherein: the first well region extends from a surface of the epitaxial layer to an upper extent of the buried region, the first well region overlying a portion of the buried region and extending laterally beyond the buried region; the second well region extends from the surface of the epitaxial layer to the upper extent of the buried region, the second well region overlying a portion of the buried region and extending laterally beyond the buried region; and the field region is spaced apart from the buried region; a first insulation region overlying a portion of the second well region, a portion of the third well, and a portion of the field region; and a gate electrode formed on the first insulation region above the portion of the second well region and extending over a portion of the third well region.