Patent ID: 7279755

Claim:
A six-transistor static random access memory cell, comprising: a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source; a second inverter cross-coupled with the first inverter, having a second pull-up transistor and a second pull-down transistor serially coupled between the supply source and the complementary supply source; and first pass-gate and second pass-gate transistors coupled to the first and second inverters, respectively, wherein the first pass-gate transistor and the first pull-up transistor are respectively constructed on a first P-type well and a first N-type well adjacent to one another, which are overlaid by a first N-type doped region and a second P-type doped region of substantially the same width and in substantial alignment with one another, respectively.