Patent ID: 7303965

Claim:
A method for producing a MIS transistor comprising a semiconductor substrate, impurity diffusion regions formed on the substrate serving as source/drain regions, and a gate electrode provided above a channel region between the source/drain regions, said method comprising: selectively forming a first film on said semiconductor substrate; etching said semiconductor substrate to form a first groove by using said first film as a mask; forming a second film in said first groove and thereafter removing said first film; diffusing an impurity onto a surface of said semiconductor substrate using said second film as a mask to form the impurity diffusion regions including a part thereof extending below the first groove; forming an insulator film on said impurity diffusion regions and thereafter removing said second film to form a second groove on the semiconductor substrate so that a top surface of each of the impurity diffusion regions of the semiconductor substrate is higher than a bottom surface of the second groove; forming a gate insulator film in said second groove and controlling a thickness of the gate insulator film so that a top surface of said gate insulator film is higher than the top surface of each of said impurity diffusion regions; and forming a gate electrode on the top surface of said gate insulator film.