Patent ID: 8068072

Claim:
A data driver, comprising: a shift register circuit configured to receive a first clock signal, a second clock signal, and a start signal, and to sequentially provide a sampling signal; a conversion circuit configured to receive the first clock signal, the second clock signal, and the sampling signal, and to sequentially provide a conversion signal; a sampling latch circuit configured to receive the sampling signal from the shift register circuit and receive the conversion signal from the conversion circuit, and to store data according to the sampling signal and the conversion signal; and a holding latch circuit configured to receive the data from the sampling latch circuit in response to first and second enable signals, and to provide a first data signal or a second data signal to data lines corresponding to the received data, wherein: the shift register circuit includes a plurality of shift registers, the sampling latch circuit includes a plurality of sampling latches, and the holding latch circuit includes a plurality of holding latches, each of the shift registers, the sampling latches, and the holding latches including a same first circuit, the first circuit includes a capacitor and first, second, third, fourth and fifth transistors, a first electrode of the first transistor is connected to an external input, a gate electrode of the first transistor is connected to a second input, and a second electrode of the first transistor is connected to a first node, a gate electrode of the second transistor is connected to the first node, a first electrode of the second transistor is connected to a first input, and a second electrode of the second transistor is connected to an output, a first electrode of the third transistor is connected to a second node, a gate electrode of the fourth transistor is connected to the first node, a first electrode of the fourth transistor is connected to the second input, and a second electrode of the fourth transistor is connected to the second node, a gate electrode of the fifth transistor is connected to the second node, a first electrode of the fifth transistor is connected to a third power supply, and a second electrode of the fifth transistor is connected to the output, and a first electrode of the capacitor is connected to the gate electrode of the second transistor, and a second electrode of the capacitor is connected to the second electrode of the second transistor.