Patent ID: 6891741

Claim:
A ferroelectric memory device comprising: a memory cell array, in which memory cells are arranged, in a matrix, which comprises first signal electrodes, second signal electrodes arranged in a direction which intersects with the first signal electrodes, and a ferroelectric layer disposed at least in intersecting regions in which the first signal electrodes intersect with the second signal electrodes, wherein information is written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in one of the memory cells, a predetermined voltage is applied to an unselected memory cell when information is written, wherein information is read from a selected memory cell by applying a read voltage between one of the first signal electrodes and one of the second signal electrodes in one of the memory cells, a predetermined voltage is applied to an unselected memory cell when information is read, and wherein, provided that the maximum absolute value of a voltage applied between one of the first signal electrodes and one of the second signal electrodes is Vs, a polarization value P of a ferroelectric capacitor comprising one of the first signal electrodes, one of the second signal electrodes, and the ferroelectric layer is within the range of: 0.1 P (+ Vs )< P (−⅓ Vs ) when the applied voltage is changed from +Vs to −⅓ Vs, and 0.1 P (− Vs )> P (+⅓ Vs ) when the applied voltage is changed from −Vs to +⅓ Vs.