Patent ID: 8490111

Claim:
A digital logic system for communications among a set of processing tasks of a software program, the system comprising: a memory segment for each task of said set, to allow the tasks to communicate with each other while running in parallel on an array of processing cores; hardware logic for at least one task of the set to write its inter-task communication information to a memory segment of another task of the set; and hardware logic for at least one task of the set to read its inter-task communication information from its own memory segment, wherein the hardware logic for at least one task of the set to write its inter-task communication information comprises at least one multiplexer specific to a given task of the set, with said multiplexer configured to connect write access buses from the processing cores on which the tasks of the program are running to the memory segment of the given task; and wherein the hardware logic for at least one task of the set to read its inter-task communication information comprise at least one multiplexer specific to a given core of the array, with said multiplexer configured to connect read access buses from memory segments of tasks of the set to the given core of the array.