Patent ID: 7263151

Claim:
In a receiver that includes a clock recovery circuit for extracting a recovered clock signal from an incoming data signal, a loss-of-signal detector comprising: a delay circuit coupled to receive the incoming data signal and configured to shift a phase of the incoming data signal by a predetermined delay ΔT to generate a delayed data signal; a flip-flop coupled to receive the recovered clock signal at one input and the delayed data signal at a second input; an integrator coupled to an output of the flip-flop, wherein the integrator is configured to integrate a plurality of error signals generated by the flip-flop for an integration period, τint, and to generate a bit error rate sign, V BER ; a switch coupled to the integrator and configured to reset the integrator; and a comparator having a first input coupled to an output of the integrator and a second input coupled to a threshold voltage, wherein the comparator is configured to compare V BER to a threshold level and to generate a loss-of-signal indicator when V BER exceeds the threshold level, wherein, the delay circuit is configured to shift the phase of the incoming data signal in a manner that is symmetrical with respect to a sampling edge of the clock signal; wherein the flip-flop is configured to generate an error signal when a transition of the delayed data signal falls outside the range (T/2)±ΔT, where T is the period of the recovered clock signal, and wherein the comparator comprises a hysteresis whereby the loss-of-signal indicator is asserted when V BER exceeds a first threshold Vt 1 , and is not cleared until V BER drops below a second threshold Vt 2 that is lower than the first threshold Vt 1 .