Patent ID: 8071407

Claim:
A method of fabricating an active device array substrate, comprising: providing a substrate; forming a patterned first metal layer on the substrate, wherein the patterned first metal layer includes a plurality of gate lines, a plurality of gates and a plurality of gate pads, and the gate lines are connected with the gates and the gate pads; forming a first insulating layer on the substrate and the patterned first metal layer; forming a patterned semiconductor layer on parts of the first insulating layer; forming a patterned metal multilayer on the first insulating layer and the patterned semiconductor layer, wherein the patterned metal multilayer includes a plurality of data lines, a plurality of drains, a plurality of storage electrodes, a plurality of sources and a plurality of data pads, and the data lines are connected with the sources and the data pads, and wherein the sources and the drains are respectively configured above the gates, each of the drains and each of the storage electrodes respectively have a drain opening and a storage electrode opening, and the drain openings and the storage electrode openings expose parts of the patterned semiconductor layer; forming a completely covering second insulating layer; patterning the second insulating layer and the first insulating layer to expose parts of the drain openings, parts of the storage electrode openings, parts of the data lines, parts of the data pads, parts of the gate lines, and parts of the gate pads; performing an etching process to selectively remove the exposed parts of the patterned metal multilayer; and forming a patterned conducting layer, wherein the patterned conducting layer includes a plurality of pixel electrodes electrically connected to the drains individually.