Patent ID: 8063693

Claim:
A charge pump latch circuit comprising: at least one first charge pump stage and at least one second charge pump stage interconnected by an intermediate circuit node, the first charge pump stage comprising at least a first transistor, and the second charge pump stage comprising at least a second transistor; a stabilization stage connected to the intermediate circuit node, to a control terminal of the first transistor of the first charge pump stage, and to a control terminal of the second transistor of the second charge pump stage, the stabilization stage including at least one first pair of first and second enable terminals and at least one second pair of first and second enable terminals; and a phase generator that includes at least one pair of input terminals receiving first and second input signals, a first pair of output terminals connected to the first pair of enable terminals of the stabilization stage to supply the first pair of enable terminals with first and second distinct phase signals, and a second pair of output terminals connected to the second pair of enable terminals of the stabilization stage, wherein the phase generator further includes digital level shifter circuits connected to the second pair of output terminals of the phase generator, the digital level shifter circuits shifting the levels of the first and second distinct phase signals so as to supply the second pair of enable terminals of the stabilization stage with first and second shifted phase signals that are negated and suitably level shifted with respect to the first and second distinct phase signals supplied to the first pair of enable terminals of the stabilization stage, and the digital level shifter circuits each comprise an output circuit portion comprising a transistor having a control terminal that receives one of the first and second input signals, a first terminal that receives one of the first and second distinct phase signals, and a second terminal that supplies one of the first and second shifted phase signals that is negated and suitably level shifted with respect to the one distinct phase signal.