Patent ID: 8013631

Claim:
A complementary metal oxide semiconductor (CMOS) input buffer circuit for converting a signal lower than CMOS level that is input to an input terminal into a CMOS level signal and outputting the converted CMOS level signal to an output terminal, the CMOS input buffer circuit comprising: a power supply terminal (VDD) and a reference terminal (GND) that are each supplied with a CMOS level voltage; a first depletion type NMOS transistor including: a drain connected to the power supply terminal (VDD); and a gate connected to the output terminal; a first PMOS transistor including: a source connected to a source of the first depletion type NMOS transistor; a drain connected to the output terminal; and a gate connected to the input terminal; and an NMOS transistor including: a source connected to the reference terminal (GND); a gate connected to the input terminal; and a drain connected to the output terminal a reference voltage circuit for outputting a reference voltage from a reference voltage output terminal thereof; a second PMOS transistor including: a drain connected to the output terminal; and a gate connected to the input terminal; and a second depletion type NMOS transistor including: a drain connected to the power supply terminal (VDD); a source connected to a source of the second PMOS transistor; and a gate connected to the reference voltage output terminal.