Patent ID: 8619746

Claim:
An apparatus comprising: at least one processor; a memory coupled to the at least one processor; the at least one processor configured to: identify, for identifying a set of selected channel taps, at least one index of a plurality of channel taps in a channel impulse response estimate based on a scattered pilot having a pilot symbol on each of a plurality of interlaces corresponding to a first plurality of carriers; determine gains of the selected channel taps based on a continual pilot having a pilot symbol on each of a second plurality of carriers, wherein the selected channel taps are a predetermined number of strongest channel taps; derive a channel frequency response estimate based on the gains of the selected channel taps; perform data detection with the channel frequency response estimate; and combine, in a frequency domain, the plurality of interlaces corresponding to the first plurality of carriers carrying the scattered pilot, wherein the combining comprises: receiving pilot symbols on the plurality of interlaces corresponding to the first plurality of carriers carrying the scattered pilot in a plurality of symbol periods, combining the received pilot symbols in frequency domain in accordance with a plurality of coefficients, and deriving the channel impulse response estimate based on the combined pilot symbols, wherein the coefficients determine weights applied to the plurality of interlaces for combining.