Patent ID: 8046538

Claim:
A hierarchical memory system comprising: a cache coupled to one or more processing cores, wherein the cache is configured to convey a request for a first sub-block within a first cache line comprising a plurality of sub-blocks of data; a lower-level memory configured to store a cache line which is evicted from the cache; wherein, in response to receiving said request, the lower-level memory is further configured to: access a mask corresponding to the first cache line; identify one or more sub-blocks within the first cache line which are predicted by the mask to be accessed; and transfer to the cache only the first sub-block and said one or more sub-blocks; wherein the cache, in response to detecting an access to a second cache line within the cache, is further configured to: identify a particular sub-block of the second cache line which is addressed by the access; and store an indication in an entry in a first mask which corresponds to the particular sub-block, wherein the first mask comprises a separate entry for each of the sub-blocks within the second cache line, said indication comprising a prediction that the sub-block is likely to be accessed while the second cache line is present in the cache; wherein in response to determining a selected cache line stored within the cache is to be evicted, the cache is further configured to access a selected word mask corresponding to the selected cache line prior to evicting the selected cache line, and then transfer to the lower-level memory only those sub-blocks of the selected cache line which are identified by the selected word mask as being predicted likely to be accessed.