Patent ID: 7966529

Claim:
A system for testing a plurality of memory blocks in a System on Chip (SOC) having at least two Test Access Ports (TAPs), the two TAPs including a user TAP and an Electronic Design Automation (EDA) tool TAP, wherein the EDA tool TAP is used to access and test the memory blocks of the SOC, and wherein the user TAP and the EDA tool TAP are accessed using one set of JTAG pins including a TDI, TCK, TMS and TRST pin, the system comprising: a glue logic block that selects the user TAP at an outset of a testing phase and after programming the user TAP selects the EDA tool TAP to provide test data received via the TDI pin to the plurality of memory blocks during testing of the plurality of memory blocks; a secured logic block in communication with the user TAP by way of the glue logic block that generates a TAP selection signal, wherein the TAP selection signal is gated with the TMS pin in order to control selection of the user TAP and the EDA tool TAP and thereby prevent non-privileged access to the plurality of memory blocks via the EDA tool tap; a memory testing module in communication with the EDA tool TAP by way of the glue logic block for facilitating testing of the plurality of memory blocks when the EDA tool TAP is selected, wherein the memory testing module receives test data from the EDA tool TAP; and a fuse logic block, including at least one fuse, connected to the secured logic block, wherein blowing the at least one fuse prevents the secured logic block from asserting the TAP selection signal, thereby disabling access to the EDA tool TAP so that the memory blocks can no longer be accessed via the EDA tool TAP.