Patent ID: 8806116

Claim:
A memory module comprising: a printed circuit board (PCB) with an edge connector; an address controller integrated circuit coupled to the PCB and the edge connector, the address controller integrated circuit to determine if an address is associated with a compound memory request for the memory module, wherein a compound memory request includes an aggregation of a plurality of memory accesses; and a plurality of memory slices, each memory slice of the plurality of memory slices including a plurality of read-writeable non-volatile memory integrated circuits coupled to the PCB; and a slave memory controller integrated circuit coupled to the PCB and the edge connector, the slave memory controller integrated circuit further coupled between the address controller integrated circuit and the plurality of read-writeable non-volatile memory integrated circuits, the slave memory controller integrated circuit to receive a memory slice request from the address controller integrated circuit in response to the compound memory request, the slave memory controller integrated circuit to selectively activate one or more of the plurality of read-writeable non-volatile memory integrated circuits in the respective memory slice in response to an address received from the address controller integrated circuit, and the slave memory controller integrated circuit further to selectively read from or write data into selected memory locations in the one or more of the plurality of read-writeable non-volatile memory integrated circuits in response to the memory slice request.