Patent ID: 7099174

Claim:
A method of operating an integrated circuit memory device, said method comprising: providing a layer of metalized traces including a plurality of I/O traces; including within said layer of metalized traces a plurality of non-I/O traces, and disposing at least one non-I/O trace between every two I/O traces; introducing a plurality of I/O signals, each of said I/O signals exhibiting a transient portion and a non-transient portion, onto said plurality of I/O traces respectively; introducing a plurality of non-I/O signals, each of said non-I/O signals exhibiting a transient portion and a non-transient portion, onto said plurality of non-I/O traces respectively; and applying said I/O signals and said non-I/O signals such that said I/O signal transient portions occur only during non-transient portions of said non-I/O signals.