Patent ID: 8407652

Claim:
A computer-implemented method of optimizing an integrated circuit design, the method comprising: executing a parent process and a plurality of child processes on at least one processor; in the parent process, generating a set of objects from the integrated circuit design upon which to perform a transform; in each child process of the plurality of child processes: performing the transform on each object of a subset of objects from the set of objects, including determining, for each object of the subset of objects, whether such object is a candidate object for which performance of the transform has been successful; and notifying the parent process of any candidate object from the subset of objects for which performance of the transform has been determined to be successful; and in the parent process, performing the transform on each candidate object of which the parent process is notified by the plurality of child processes; wherein the parent process and each child process of the plurality of child processes uses an independent copy of the integrated circuit design, wherein performing the transform in the parent process includes performing the transform using the independent copy of the integrated circuit design for the parent process, wherein performing the transform in each child process includes performing the transform using the independent copy of the integrated circuit design for such child process such that performing the transform in each child process does not alter the independent copy of the integrated circuit design for the parent process; wherein the method further comprises, in the parent process, forking the plurality of child processes, and wherein forking the plurality of child processes generates the independent copy of the integrated circuit design for each child process of the plurality of child processes from the independent copy of the integrated circuit design for the parent process.