Patent ID: 8364738

Claim:
A method of performing multiplication operations of a first size in a programmable logic device having a specialized functional block configured to (1) perform multiplication operations of at least one other size, and (2) add together results of said multiplication operations of said at least one other size, wherein (a) each said at least one other size is different from said first size, and (b) said at least one other size includes a second size different from said first size, said method comprising: decomposing said multiplication operation of said first size into a plurality of multiplication operations, said plurality of multiplication operations including a multiplication operation of said second size and at least one other multiplication operation; performing said multiplication operation of said second size in said specialized functional block; performing said at least one other multiplication operation in programmable logic of said programmable logic device; and using said specialized functional block to add together results of said multiplication operation performed in said specialized functional block and said at least one other multiplication operation performed in said programmable logic of said programmable logic device.