Patent ID: 8804438

Claim:
A memory device, comprising: a memory array that includes a plurality of bit line columns connected to a corresponding plurality of bit lines, wherein each bit line column includes a plurality of bit cells, and wherein the plurality of bit cells are connected to a corresponding plurality of word lines; a row address decoder for generating a word line enable signal for selecting at least one word line and at least one bit line for discharging; a plurality of sense amplifiers connected to and for sensing the plurality of bit lines; a reference column comprising a read reference bit line for vertical tracking of the selected at least one bit line using a first pre-defined loopback during a read operation and a write reference bit line for vertical tracking of the selected at least one bit line using a second pre-defined loopback during a write operation; and a control circuit, including: a pre-charge generator for generating a pre-charge signal to pre-charge the read reference bit line for the read operation, the write reference bit line for the write operation, and the selected at least one bit line; a clock generator for generating an internal clock signal for the row address decoder and a sense clock signal for enabling discharge of the read reference bit line during the read operation and the write reference bit line during the write operation, wherein the sense clock signal vertically tracks the internal clock signal to the row address decoder using a third pre-defined loopback; and a sense signal generator for generating a sense enable signal for activating a sense amplifier of the plurality of sense amplifiers corresponding to the selected at least one bit line for performing the read operation when the read reference bit line is discharged, wherein the sense enable signal horizontally tracks the selected at least one word line using a sense line, and wherein widths of the sense line and the at least one word line are substantially the same.