Patent ID: 7532501

Claim:
A memory cell, comprising: a plurality of back-gated n-type field effect transistors (nFETs); and a plurality of double-gated p-type field effect transistors (pFETs) operatively coupled to said plurality of nFETs, wherein said plurality of back-gated nFETs comprises a first nFET having a finFET structure and a second nFET having a finFET structure, a back-gate of said second nFET being coupled to a back-gate of said first nFET, and wherein said back-gate of said first nFET and said back-gate of said second nFET are coupled to a body bias generator for supplying a back-gate bias to said first and second nFETs, said back-gate bias being at least equal to Vdd for said memory cell in active mode and being not greater than ground in a standby mode.