Patent ID: 8493799

Claim:
A semiconductor memory device comprising: a command/address input buffer that receives a command/address signal and a command/address reference voltage signal, wherein the command/address input buffer is configured to amplify a difference between the command/address signal and the command/address reference voltage signal, and is further configured to output the amplified difference between the command/address signal and the command/address reference voltage signal; and a chip selection input buffer that receives a chip selection signal and a chip selection reference voltage signal, wherein the chip selection input buffer is configured to amplify a difference between the chip selection signal and the chip selection reference voltage signal, and is further configured to output the amplified difference between the chip selection signal and the chip selection reference voltage signal, wherein the command/address signal is transmitted via a command/address bus commonly connected to a plurality of semiconductor memory devices and the chip selection signal is transmitted via a chip selection bus connected to a subset of the plurality of semiconductor memory devices, and wherein a voltage level of the command/address reference voltage signal is different from a voltage level of the chip selection reference voltage signal.