Patent ID: 7362554

Claim:
An electrostatic discharge (ESD) protection device for protecting an integrated circuit with associated terminals, each having a functional relationship to the operation of the integrated circuit, the integrated circuit having an output driver with a p-channel transistor and n-transistor pair connected between one of the terminals configured as a power supply terminal and one of the terminals configured as a ground terminal for driving an associated one of the terminals configured as an input/output pad, comprising: an ESD event detector for detecting an ESD event on one of the terminals; a drive circuit for driving the n-channel and p-channel drive transistors in response to receiving a logic control signal to either drive the pad from the supply terminal or to sink the input/output pad to ground, wherein said drive circuit comprises a non overlap generator for receiving first and second inputs and driving the n-channel and p-channel transistors such that changing of a logic input state is facilitated by changing the one of the n-channel and p-channel transistors currently in a conducting state to a non conducting state prior to changing the other of the n-channel and p-channel transistors in the non conducting state to a conducting state; and ESD protection logic circuitry to cause both said p-channel and n-channel transistors to turn on when said ESD event detector detects an ESD event, said ESD protection logic circuitry disposed forward of and separate from said drive circuit such that said ESD protection logic circuitry operates independent of the state of said drive circuit.