Patent ID: 8009495

Claim:
A method, comprising: receiving, by a memory device including a plurality of memory cells and a plurality of bit lines associated with the plurality of memory cells, a first command to perform a first operation on a first subset of the plurality of memory cells; initiating, in response to receipt of the first command, a selective precharge operation, wherein the selective precharge operation results in a precharged state of a subset of the plurality of bit lines coupled to the first subset of the plurality of memory cells, and wherein the subset of the plurality of bit lines includes fewer bit lines than the plurality of bit lines; receiving, by the memory device, a second command to perform a second operation on a second subset of the plurality of memory cells, wherein the second subset of the plurality of memory cells differs from the first subset of the plurality of memory cells, and wherein the second subset of the plurality of memory cells is coupled to the subset of the plurality of bit lines; and performing, in response to said receiving a second command, the second operation on the second subset of the plurality of memory cells, wherein the second operation occurs during a time that the subset of the plurality of bit lines remains in the precharged state that results from the selective precharge operation initiated in response to receipt of the first command.