Patent ID: 7919358

Claim:
A multi-chips stacked package method comprising: providing a lead frame, and the lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads, and the plurality of inner leads includes a plurality of first paralleled inner leads and a plurality of second paralleled inner leads, and the ends of the plurality of first paralleled inner leads and the ends of the plurality of second paralleled inner leads are opposite to each other with an interval, the plurality of first paralleled inner leads and the plurality of second paralleled inner leads respectively includes a thermal fin closed to a central region thereof, wherein the width of the thermal fin is wider than the plurality of first paralleled inner leads and the plurality of second paralleled inner leads and the thermal fin is able to form a fan-shape closed to the plurality of first paralleled inner leads and the plurality of second paralleled inner leads respectively; providing a first chip, and the first chip includes an active surface, and a plurality of first pads are disposed near the central region of the active surface and exposed at the interval between the plurality of first paralleled inner leads and the plurality of second paralleled inner leads; fixing the first chip, the first chip is fixed on the reverse surface of the lead frame and the active surface of the first chip includes a plurality of first pads closed to the central region, the first pads are exposed in the interval between the first inner leads and the second inner leads; forming a plurality of first metal wires, and the first pads of the first chips are electrically connected to the plurality of first paralleled inner leads and the plurality of second paralleled inner leads by the first metal wires; forming a plurality of metal spacers, and at least one pair of the metal spacers are formed on the thermal fin of the lead frame during forming said plurality of first metal wires; fixing a second chip, and the second pads on the active surface of the second chip are electrically connected to the top surface of the plurality of first paralleled inner leads and the plurality of second paralleled inner leads; forming a plurality of second metal wires, and the second pads on the active surface of the second chip are electrically connected to the top surface of the plurality of first paralleled inner leads and the plurality of second paralleled inner leads; and flowing a molding to form an encapsulated material to cover the first chip, the first metal wires, the second chip, the second metal wires, the plurality of first paralleled inner leads and the plurality of second paralleled inner leads and the outer leads being exposed.