Patent ID: 7064586

Claim:
A buffer circuit, comprising: a differential amplifier, the differential amplifier having an output, a first input coupled to a reference voltage, a second input coupled to an input voltage, and a current source, the differential amplifier generating a signal at the output in response to a difference between the reference voltage and the input voltage; a reference voltage monitoring circuit, the reference voltage monitoring circuit having an input coupled to the reference voltage and an output, the reference voltage monitoring circuit generating a signal at the output in response to a change in the reference voltage; and a buffering inverter, the buffering inverter having an input connected to the output of the differential amplifier, the buffering inverter generating an output in response to the output of the differential amplifier and the output of the reference voltage monitoring circuit, wherein the buffering inverter includes first and second buffering inverter transistors, a drain of the first buffering inverter transistor being connected to a drain of a second buffering inverter transistor, a source of the first buffering inverter transistor being connected to the output of the reference voltage monitoring circuit, a source of the second buffering inverter transistor being connected to ground; wherein the reference voltage monitoring circuit includes first and second monitoring circuit transistors and a second current source, a drain of the first monitoring circuit transistor being connected to a drain of the second monitoring circuit transistor, a gate and a drain of the first monitoring circuit transistor being connected to each other, a gate of the second voltage monitoring circuit transistor being connected to the reference voltage, a source of the second voltage monitoring circuit transistor being connected to the second current source; and wherein the output of the reference voltage monitoring circuit is coupled to the buffering inverter so as to vary a logic threshold voltage of the buffering inverter to minimize an effect of a variation in the value of the reference voltage on signal propagation delay times.