Patent ID: 8289040

Claim:
A wafer unit for testing that is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing comprising: a connecting wafer provided to face the wafer to be tested, the connecting wafer including a plurality of test pads for sending or receiving test signals to or from the wafer to be tested, each test pad adapted to be electrically connected to a corresponding one of the plurality of chips to be tested; a temperature distribution adjusting section adapted to adjust a temperature distribution of the wafer to be tested, the temperature distribution adjusting section including a plurality of individual temperature adjusting sections, each of the individual temperature adjusting sections including a heater adapted to heat a corresponding one of the plurality of chips to be tested; and a plurality of test circuits adapted to test a corresponding one of the plurality of chips to be tested, via a corresponding one of the plurality of test pads, wherein the plurality of test pads and the plurality of heaters are provided on a surface of the connecting wafer that faces the wafer to be tested, and each of the individual temperature adjusting sections is adapted to control its heater based on a current flowing through a corresponding one of the plurality of test circuits.