Patent ID: 6956777

Claim:
A semiconductor memory device equipped with a first operation mode that conducts an access operation when a first address is designated as object of access at every address access and a second operation mode that conducts an access operation in asynchronous with the first operation mode when a second address is designated as object of access at every address access in accordance with a predetermined procedure, wherein the semiconductor memory device comprises: an address storing section for storing the second address to be designated in next time of the second operation mode in accordance with a control signal generated in advance of the next time of the second operation mode, the address storing section being connected to an internal address bus; a redundancy-judgment-result storing section for storing a redundancy judgment result of the second address to be designated in the next time of the second operation mode in accordance with the control signal generated in advance of the next time of the second operation mode, the redundancy-judgment-result storing section being connected to a redundancy-judgment-result bus; a first switching section for selecting the internal address bus or the address storing section when the access operation is made in the first operation mode or the second operation mode; and a second switching section for selecting the redundancy-judgment-result bus or the redundancy-judgment-result storing section when the access operation is made in the first operation mode or the second operation mode.