Patent ID: 8812931

Claim:
A memory system comprising: a first memory for storing data; an ECC (error correction code) unit for detecting errors in data retrieved from the first memory and for producing corrected values for some of the data retrieved from the first memory; an error further processing arrangement to process the errors in data detected by the ECC unit, the error further processing arrangement including: a second memory for recording data relating to the errors, wherein data relating to an error detected by the ECC unit is to comprise an address in the first memory of data, wherein retrieval of the data generated the error detected by the ECC, together with information enabling the error to be corrected, the information is based upon a corrected value produced by the ECC unit, and the information is recorded in response to the detection of the error by the ECC unit; and a table lookup unit connected to the ECC unit and the second memory, wherein the ECC unit is to transmit to the table lookup unit addresses of the errors detected by the ECC unit and the table lookup unit is to access the second memory based upon the transmitted addresses.