Patent ID: 8211773

Claim:
A method of fabricating an integrated circuit having an SRAM memory cell, comprising the steps of: forming a gate structure for an access transistor of said SRAM memory cell over a semiconductor body; forming a first source/drain region on a bitline side of said gate structure and a second source/drain region on a storage node side of the gate structure; implanting a dopant into a pocket region on the storage node side of the access transistor while at least partially blocking the dopant implantation into the pocket region on the bitline side of the access transistor, thereby forming said pocket region having an asymmetrical shape; connecting said first source/drain region to a bitline; and connecting said second source/drain region to a storage node; forming an implant mask over the semiconductor body prior to said step of implanting a dopant; using said implant mask, forming a first lightly doped source/drain region on the bitline side and a second lightly doped source/drain region on the storage side; and removing said implant mask after said step of implanting a dopant.