Patent ID: 8650519

Claim:
A method comprising: receiving a timing analysis report generated from a timing analysis of an integrated circuit (IC) design, wherein the timing analysis report includes timing information corresponding to an arrival time of signals conveyed on signal paths in the IC design; generating one or more event monitors based upon the timing information in the timing analysis report, wherein each event monitor determines whether a specified event occurred during a simulation of the IC design; a processor simulating the IC design using one or more simulation test patterns on a simulation test bench, wherein the one or more simulation test patterns are provided by a test generator; recording results from the one or more event monitors; manipulating the test generator based upon the results to change the simulation test patterns during subsequent simulations; wherein manipulating the test generator includes adjusting the test generator output to preferentially generate test patterns that sensitize logic within the IC design that is being monitored by one or more of the event monitors.