Patent ID: 7782672

Claim:
A semiconductor memory device, comprising: a memory array having a U-shaped configuration in the two-dimensional directions; an analog/logic region arranged in a hollow portion formed by the arrangement of said memory array; and a power supply pad arranged in contact with said analog/logic region and out of contact with said memory array; and a data pad arranged in line with a side of said semiconductor memory device and in contact with said hollow portion, wherein said memory array is non-volatile, and has a plurality of banks, at least one of said plurality of banks includes a first region having normal block regions and a spare block region arranged in rows and columns, each normal block region being as a unit of batch erase, and said spare block region substituting said normal block region when said normal block region is defective, and a second region having a boot block region that is a unit of batch erase smaller than said normal block region.