Patent ID: 7050341

Claim:
A diagonal matrix delay formed on a monolithic substrate for delaying an input signal, comprising: a plurality of rows of delay buffers in serial communication with the input signal, wherein a last delay buffer in a row is in communication with a first delay buffer of a next row; a plurality of tri-state buffers, wherein each tri-state buffer is responsive to an output of an associated delay buffer and to a column selection signal, and wherein outputs of tri-state buffers associated with delay buffers in each row are coupled together to form an output of each row; a plurality of column selection lines, wherein each column selection line supplies column selection signals to the corresponding tri-state buffers associated with each of the plurality of rows of delay buffers, wherein tri-state buffers selected by a column selection line are offset between contiguous rows by at least one column, and wherein a change in selection between contiguous rows of delay buffers requires an absence of change between corresponding columns of tri-state buffers; and a plurality of row-selection tri-state buffers, wherein each of the plurality of row-selection tri-state buffers is responsive to a row selection signal and to the coupled output of tri-state buffers in each row, and wherein outputs of the plurality of row-selection tri-state buffers are coupled together to provide an incrementally-delayed input signal from a selected row as an output signal of the diagonal matrix delay.