Patent ID: 8713264

Claim:
A data processing circuit, comprising: a plurality of queues, each queue configured to queue memory access requests issued by each of a plurality of agents; an arbiter configured to select one of the plurality of queues at a selection time based on a relative priority assigned to each of the plurality of the queues, the arbiter comprising a time selection input; a request concentrator coupled to the plurality of queues and configured to forward a memory access request in the selected queue; a request handler coupled to the request concentrator and comprising memory on which to perform a read or write operation according to the forwarded memory access request, the request handler configured to send a signal indicative of the selection time to the time selection input of the arbiter; and wherein each queue comprises: an input interface coupled to each of the plurality of agents; a buffer coupled to the input interface to receive and store memory access request; a priority changing request detector having an input coupled to the input interface to detect and store an indication of a priority changing request and to prevent storing of the priority changing request in the buffer; and an output interface between the buffer and the request concentrator.