Patent ID: 7855862

Claim:
An integrated circuit including ESD protection, comprising: a conductive signal pad configured to provide an electrical signal connection point to the integrated circuit from an external source; a protected circuit electrically connected to the conductive signal pad by a source-drain path of an ESD protection p-channel insulated gate field effect transistor (PFET), and connected to a high voltage power supply node and a low voltage power supply node that supply power for the protected circuit; the ESD protection PFET includes a gate connected to the low voltage power supply node that supplies power for the protected circuit, the PFET including a p-type source region and a p-type drain region both formed in an n-type well region formed in a larger p-type region; an n-type guard ring formed in the n-type well region of the ESD protection PFET and surrounding the p-type source region and the p-type drain region, the n-type guard ring having a higher doping concentration than the n-type well region; the n-type well region directly connected by the n-type guard ring to the high voltage power supply node that supplies power for the protected circuit, such that in response to one type of ESD event a forward current flow path is provided by a pn junction between the p-type source region and the n-type guard ring to the high voltage power supply node that supplies power for the protected circuit; and, a p-type guard ring in the larger p-type region and surrounding the n-type well region of the ESD protection PFET, the p-type guard ring having a higher doping concentration than the larger p-type region, the p-type guard ring electrically connected to the low voltage power supply node that supplies power for the protected circuit.