Patent ID: 7404161

Claim:
A method for maintaining a reference netlist representation in a top level integrated circuit design comprising: providing a reference Register Transfer Logic (RTL) design representation of the integrated circuit design; generating the reference netlist representation of the integrated circuit design; generating a physical layout design of the integrated circuit design based upon the reference netlist representation of the integrated circuit design; updating the reference netlist representation of the integrated circuit design to reflect changes to the physical layout design; verifying equivalency between the reference RTL design and the physical layout design of the integrated circuit design, wherein verifying equivalency further comprises: comparing the physical layout design to the reference netlist representation; comparing the reference RTL design to the reference netlist representation; and maintaining equivalency between the reference RTL design and the physical layout design of the integrated circuit design using the reference netlist representation of the integrated circuit design, wherein maintaining equivalency includes updating the reference RTL design representation to reflect a subset of changes to the physical layout design using the reference netlist representation of the integrated circuit design.