Patent ID: 7323407

Claim:
A method of fabricating dual damascene interconnections suitable for a microelectronic device, said method comprising the sequential steps of: (a) forming a low-k interlayer dielectric layer having a low dielectric constant on a substrate; (b) forming a via within the interlayer dielectric layer; (c) filling the via with a hydrogen silsesquioxane (HSQ)-based filler expressed by the following general chemical formula: (RSiO 3/2 ) x (HSiO 3/2 ) y, wherein x and y satisfy the relationships x+y=1 and 0<x<y<1, and also wherein R is selected from the group consisting of C4-C24 alkyl groups, C4-C24 alkenyl groups, C4-C24 alkoxy groups, C8-C24 alkenoxy groups, substituted C4-C24 hydrocarbon groups, and substituted C1-C4 hydrocarbon groups; (d) partially etching the filler filling the via and the interlayer dielectric layer to form a trench which is connected to the via in the region where the dual damascene interconnections are to be formed; (e) removing the filler remaining in the via; and (f) filling the trench and the via with an interconnection material to complete the dual damascene interconnections.