Patent ID: 7675369

Claim:
A method for controlling a frequency output of a phase locked loop (PLL), said method comprising: providing digital control words to the PLL to discretely change at least one dividing factor within the PLL; applying a time-varying control voltage directly to a voltage controlled oscillator with a method comprising: applying random digital data to a digital to analog converter directly from a signal generator; and using an output of the digital to analog converter as the control voltage for the voltage controlled oscillator; applying an output of the voltage controlled oscillator to the PLL as a reference frequency; and outputting a signal from the PLL, the signal varied in frequency based on one or more of the time-varying control voltage and the at least one dividing factor, wherein the PLL comprises: a first divider configured to divide the reference frequency by a first factor; and a second divider configured to divide at least a portion of the outputted signal fed back to the PLL by a second factor.