Patent ID: 7000212

Claim:
A field programmable gate array (FPGA) comprising: (a) a plurality of nodes; (b) a plurality of general interconnect lines that can be used to transmit interconnect-conveyed signals from respective source nodes to corresponding destination nodes, wherein said general interconnect lines include: (b.1) a first plurality of first span length lines each respectively spanning a first span length and each having a first number of tap points, where the first span length is at least that spanning three of said processing/routing nodes and the tap points in said first number of tap points respectively couple to the at least three of the nodes spanned by the respective first span length line; and (b.2) a second plurality of second span length lines each respectively spanning a second span length and each having a second number of tap points, where the second span length is greater than the first span length so that each respective, second span length line spans more nodes than the number of nodes spanned by the first span length lines, and where the tap points in said second number of tap points respectively couple to less than all the nodes spanned by the respective second span length line.