Patent ID: 6885606

Claim:
A synchronous semiconductor memory device comprising: a plurality of memory banks each of which includes a plurality of memory cells connected to a plurality of word lines and which read data from the memory cells and write data into the memory cells; a command decoder circuit which receives a command input in synchronization with an external clock signal, detects whether the command is a read command or a write command, and, when detecting a read command or a write command, outputs a first control signal that enables a read operation or a write operation in the plurality of memory banks; a plurality of bank select circuits which are provided for the plurality of memory banks in a one-to-one correspondence, receive the first control signal, activate a second control signal to activate each of the memory banks according to the first control signal, and output the second control signal to the plurality of memory banks; and a plurality of bank timer circuits which are connected to the plurality of bank select circuits in a one-to-one correspondence, and, after the second control signal is activated, deactivate the activated second control signal in synchronization with an internal clock signal synchronizing with the external clock signal, and perform control in such a manner that the timing with which the second control signal is deactivated in a test mode differs from that in a normal mode.