Patent ID: 7786505

Claim:
A thyristor-based memory cell, comprising: a thyristor-based storage element, the thyristor-based storage element having a first gate electrode formed over a first gate dielectric, the first gate electrode having a first sidewall, the first gate dielectric formed over a base region of the thyristor-based storage element, the base region located in a silicon layer; a transistor coupled to the thyristor-based storage element via a cathode region, the cathode region located in the silicon layer, the transistor having a second gate electrode formed over a second gate dielectric, the second gate electrode having a second sidewall, the second gate dielectric formed over a body region of the transistor, the body region located in the silicon layer; a spacer formed at least in part along the second sidewall of the second gate electrode facing the first sidewall of the first gate electrode; a shallow implant region formed in the silicon layer responsive at least in part to the spacer, the spacer offsetting the shallow implant region from the second sidewall, a portion of the shallow implant region being for an extension region; in addition to being the cathode region for the thyristor-based storage element, the cathode region being for a source/drain type region of the transistor, wherein the cathode region includes the source/drain type region and another portion of the shallow implant region, the source/drain type region not including the extension region; and the first gate dielectric and the second gate dielectric formed at least in part by deposition of a dielectric material, the spacer formation being performed separately from formation of the first gate dielectric and the second gate dielectric; wherein a portion of the spacer is formed by oxidation of a portion of the second gate electrode along the second sidewall thereof; wherein the spacer extends under the second gate electrode responsive to the oxidation of the portion of the second gate electrode along the second sidewall thereof; wherein the spacer extends to an upper surface of the silicon layer; wherein a dielectric constant of the dielectric material is in a range of approximately 4 to 10; and wherein a dielectric material is selected from an oxynitride and an aluminum oxide.