Patent ID: 7293155

Claim:
An apparatus comprising: a first memory address generator to receive a first memory command signal and to retrieve a first set of memory data from a first memory according to the first memory command signal; a bypass storage unit to receive the first set of memory data from the first memory address generator and provide access to the first set of memory data by a second memory address generator; a first bypass control circuit to reroute the first set of memory data directly to the bypass storage unit, instead of to a processing element, while a first bypass signal is activated; and a second bypass control circuit to reroute a read operation by the second memory address generator to read the first set of memory data directly from the bypass storage unit, instead of reading data provided from a processing element, while a second bypass signal is activated, wherein the second memory address generator comprises circuitry to retrieve a second set of memory data from a second memory according to a second memory command signal generated from the first set of memory data.