Patent ID: 7958319

Claim:
A system comprising: a processor comprising: a plurality of processing elements, a first cache line, a second cache line, a hardware field including a transaction storage cell adapted to be associated with the first cache line in hardware, to hold an accessed value to indicate the first cache line has been previously accessed during a pendency of a transaction, and to hold an un-accessed value to indicate the first cache line has not been accessed during the pendency of the transaction; and an execution unit adapted to execute the transaction, and a system memory coupled to the processor, the system memory being adapted to hold data at a first home location, a software maintained lock at a second home location, and code, which when executed by the processor, causes the processor to check the software maintained lock to be held in the second cache line, which is to represent a lock value for the data to be held in the first cache line before a first transactional access from the transaction to the first cache line is performed in response to the hardware field not the un-accessed value; and to allow a second transactional access from the transaction to the data to be held in the first cache line without checking the software maintained lock to be held in the second cache line in response to the hardware field holding the accessed value.