Patent ID: 7652932

Claim:
An indication circuit in a memory system within which a clock signal and a complement of the clock signal are generated, the clock signal of the type in which a series of regular pulses in voltage level of the clock signal are preceded by a preamble period having a beginning and an end, a transition in the clock signal from an indeterminate logic level to a selected one of a high logic level and a low logic level occurring at the beginning of the preamble period, a transition in the complement of the clock signal from the indeterminate logic level to the other of the logic levels occurring at the beginning of the preamble period, the circuit comprising: a first comparator having first and second inputs, said first comparator for detecting, when said clock signal and a first reference voltage are received at said first and second inputs of the first comparator respectively, a change in polarity of a voltage difference between the voltage of said clock signal and said first reference voltage; a second comparator having first and second inputs, said second comparator for detecting, when said complement of the clock signal and a second reference voltage are received at said first and second inputs of the second comparator respectively, a change in polarity of a voltage difference between the voltage of the complement of the clock signal and said second reference voltage; and logic circuitry for generating indication, by way of an output signal of said logic circuitry transitioning to an active logic level, that said beginning of the preamble period has occurred, said indication generated when the transitions in the clock signals are detected, wherein the output signal is asserted when at the active logic level.