Patent ID: 7002836

Claim:
A method of operating a ferroelectric-type nonvolatile semiconductor memory comprising a memory unit having; (A) a bit line, (B) a transistor for selection, wherein the transistor is an MIS-type FET or an MOS-type FET; (C) a sub-memory unit composed of memory cells that are M (M≧2) in number, (D) plate lines that are M in number, and (E) a sense amplifier connected to the bit line, wherein each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, the first electrodes of the memory cells constituting the sub-memory unit are in common with the sub-memory unit, said common first electrode is connected to the bit line through the transistor for selection, and each second electrode is connected to each plate line, said method comprising reading out data stored in the memory cell at a designated address externally designated, latching said data in the sense amplifier, and then outputting said data latched in the sense amplifier, said ferroelectric-type nonvolatile semiconductor memory further comprising: a designated-plate-line address register for storing a plate-line address externally designated, and a plate-line-address counter for consecutively incrementing a plate-line address which designates the plate line, and wherein the ferroelectric-type nonvolatile semiconductor memory further comprises a comparator that is connected to the designated plate-line address register and the plate-line address counter and is for comparing a value of a designated plate-line address stored in the designated-plate-line address register and a value of a plate-line address in the plate-line address counter.