Patent ID: 7842995

Claim:
A multi-bit non-volatile memory device comprising: a substrate including a body and at least one pair of fins, each of the at least one pair of fins including a first fin and a second fin extending above the body; a first insulation layer formed on the body between the first fin and the second fin; a plurality of pairs of control gate electrodes extending across the first insulation layer and the at least one pair of fins and partly covering upper portions of outer walls of the at least one pair of fins, each of the control gate electrodes being insulated from the substrate, and each pair of control gate electrodes being arranged adjacent to another pair of control gate electrodes; a plurality of storage nodes formed between the control gate electrodes and the at least one pair of fins and insulated from the substrate; and a plurality of pairs of contact plugs, each pair of the plurality of contact plugs contacting sidewalls of a corresponding one of a pair of control gate electrodes; wherein the plurality of pairs of contact plugs are arranged in a zigzag pattern so that pairs of contact plugs contacting control gate electrodes in a first pair of control gate electrodes are arranged at the same side of the substrate, but the pair of contact plugs contacting adjacent pairs of control gate electrodes are arranged at an opposite side of the substrate, and a first distance between each adjacent pair of control gate electrodes is greater than a second distance between the control gate electrodes in each pair.