Patent ID: 8885472

Claim:
A switch having a maximum ingress rate, the switch comprising: a first set of ingress packet-processing (PP) units; a first set of egress PP units having a maximum dequeue rate; a second set of ingress PP units; a second set of egress PP units having the maximum dequeue rate; and a memory management unit (MMU), comprising: pre-enqueue work queues configured to store packet descriptors associated with data packets, the pre-enqueue work queues comprising: a first set of pre-enqueue work queues, each being communicatively coupled to a corresponding one of the first set of ingress PP units; a second set of pre-enqueue work queues, each being communicatively coupled to a corresponding one of the second set of ingress PP units; and an arbiter configured to select a packet descriptor from one of the pre-enqueue work queues and enqueue, at each of a plurality of clock cycles, a data packet associated with the packet descriptor to one of the second set of egress PP units at an enqueing rate that is less than the maximum ingress rate and greater than the maximum dequeue rate.