Patent ID: 7518396

Claim:
A programmable logic device, comprising: a first configuration data router coupled to receive a first plurality of configuration data frames; a second configuration data router, the second configuration data router being at least partially defined in response to the first plurality of configuration data frames and comprising a plurality of input/output devices coupled to receive the second plurality of configuration data frames, the second plurality of configuration data frames being externally transmitted to the programmable logic device, wherein the plurality of input/output devices includes a plurality of banks of input/output blocks; a configuration memory space coupled to the second configuration data router and adapted to receive a second plurality of configuration data frames to define a reconfigurable module within the programmable logic device, the configuration memory space including, a plurality of frame data registers, each frame data register being adapted to simultaneously receive one configuration data frame of the second plurality of configuration data frames; and a plurality of memory cell frame sets, each memory cell frame set being coupled to one of the plurality of frame data registers to simultaneous receive one configuration data frame of the second plurality of configuration data frames to define a portion of the reconfigurable module.