Patent ID: 7873932

Claim:
A method for analyzing physical properties of a component mounting board, whereon a component is mounted to a surface of a multilayer wiring board, the method comprising: generating electronic single layer models of layers of a multilayer wiring board which layers are internally divided into three-dimensional elements by a first set of element division lines, and including exclusive information about each such layer, on a basis of an external geometry of the multilayer wiring board and wiring patterns of the layers; generating an electronic multilayer substrate shell model in which the single layer models of the layers are stacked in the geometry of the multilayer wiring board using thickness information for each of the layers of the multilayer wiring board; generating an electronic multilayer component shell model based on a bonding position of a component to the surface of the multilayer wiring board divided into two-dimensional elements by a second set of element division lines; electronically generating a mounting position of a component of a multilayer substrate shell model by redividing the three-dimensional elements defined by the first set of element division lines used in generating the multilayer component shell model; forming an electronic analysis model of a mounting board with a component thereon, by connecting a neutral substrate plane computed from the redivided multilayer substrate shell model and a neutral component plane computed from the multilayer component shell model with a bonding element representing a component mounted on such a board; and computing deformation of such a model mounting board by applying stress conditions to the analysis model.