Patent ID: 8624375

Claim:
A semiconductor package comprising: a plurality of semiconductor chips stacked while each having an arrangement of chip selection vias; a first connection unit provided between a first semiconductor chip and a second semiconductor chip stacked adjacent to each other, and configured to mutually connect some of the chip selection vias of the first and second semiconductor chips and disconnect the others of the chip selection vias of the first and second semiconductor chips; and a second connection unit provided between the first semiconductor chip and a third semiconductor chip stacked under the first semiconductor chip, and configured to connect chip selection vias of the first and third chip selection vias in inverse order of arrangement, wherein, when the chip selection vias comprises first, second, third and fourth vias sequentially arranged in one direction, the second connection unit mutually connects the first via of the first semiconductor chip and the fourth via of the third semiconductor chip, and mutually connects the second via of the first semiconductor chip and the third via of the third semiconductor chip.