Patent ID: 7292595

Claim:
Input buffer packet switching equipment, comprising: M input line buffers that store cells inputted from M input lines temporarily in a state that one of said M input line buffers stores cells inputted from corresponding one of said M input lines, in this the M is an integer being 2 or more; an M×N crossbar switch, which provides N output lines for switching cells outputted from said M input line buffers based on a cross point on/off control signal, in this N is an integer being 2 or more; N output line sections, which are provided for each of said N output lines of said M×N crossbar switch, for outputting cells applied switching at said M×N crossbar switch to N external output lines; and an arbiter that outputs a connection permission signal to one of said M input line buffers based on connection request signals outputted from said M input line buffers, and also outputs said cross point on/off control signal to said M×N crossbar switch, and outputs said connection permission signal at a designated slower timing interval than a normal timing interval to one input line buffer that outputs cells to an external output line whose output line rate is slower than a corresponding input line rate, wherein said designated slower timing interval is a constant periodic rate which is slower than said corresponding input line rate, said designated slower timing interval is set so that arrival of cells at said output line sections is at a rate not greater than said output line rate, and buffer overflow and output overflow are prevented.