Patent ID: 7049226

Claim:
A method of forming a metal interconnect on a semiconductor substrate, comprising; cleaning features formed in a dielectric layer and exposing a conductive material underlying the dielectric layer by generating a plasma in a remote plasma source, delivering radicals from the plasma to a first process chamber which contains the substrate, and contacting the features formed in the dielectric layer with the radicals prior to a barrier layer deposition; depositing a tantalum nitride layer by atomic layer deposition within the features at a pressure between 1 and 10 Torr at a temperature between 200 and 300° C. in a second process chamber; depositing a tantalum layer by physical vapor deposition over the tantalum nitride layer in a third process chamber; plasma etching the tantalum layer and the tantalum nitride in a fourth process chamber to remove at least a portion of the tantalum layer and the tantalum nitride layer at the bottom of the feature to reveal the conductive material; optionally depositing additional tantalum or copper by physical vapor deposition on the tantalum layer; and depositing a seed layer over the conductive material and the tantalum layer in a fifth processing chamber, wherein the first processing chamber, the second processing chamber, the third processing chamber, the fourth processing chamber, and the fifth processing chamber are located in an integrated tool.