Patent ID: 7338845

Claim:
A method of fabricating a LTPS-TFT, comprising: forming a gate on a substrate; forming a gate dielectric layer on the substrate and the gate; forming a first amorphous silicon layer, a patterned insulating layer and a second amorphous layer over the gate sequentially, wherein the patterned insulating layer is formed on a portion of the first amorphous silicon layer and over the gate, and the second amorphous silicon layer is formed on the first amorphous and the patterned insulating layer; patterning the first amorphous silicon layer and the second amorphous silicon layer to form a first patterned amorphous layer and a second patterned amorphous layer to expose a portion of the gate dielectric layer, wherein the second patterned amorphous silicon layer exposes a portion of the patterned insulating layer; melting and then recrystalizing a portion of the first patterned amorphous silicon layer to form a polysilicon channel region over the gate, wherein the first patterned amorphous silicon layer under an overlap of the second patterned amorphous silicon layer and the patterned insulating layer becomes an amorphous silicon hot carrier restrain region; and forming a source/drain layer on the second patterned amorphous silicon layer and the exposed portion of the patterned insulating layer.