Patent ID: 7301803

Claim:
An integrated circuit device comprising: a memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor comprises: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region; and wherein the memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor; data writing circuitry, coupled to the memory cell, to write a data state into the memory cell; and data sensing circuitry, coupled to the memory cell, to sense the data state of the memory cell; wherein, in response to write control signals applied to the electrically floating body transistor, the electrically floating body transistor stores a charge which is representative of the data state of the memory cell in the body region of the electrically floating body transistor; and wherein, in response to read control signals applied to the electrically floating body transistor, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the data sensing circuitry determines the data state of the memory cell substantially based on the bipolar transistor current of the electrically floating body transistor.