Patent ID: 8356186

Claim:
A decryption system for reducing processing latency of stored, encrypted instructions, said system comprising: a storage device configured to store a plurality of sets of encrypted processor instructions, wherein each set of encrypted processor instructions was encrypted using a corresponding encryption key; a processor configured to switch between a plurality of partitions, generate a switch command upon switching between the plurality of partitions, generate a read command upon switching between the plurality of partitions, and execute decrypted code; a controller, operatively coupled to the processor, wherein the controller is configured to receive switch commands from the processor, generate bus switch commands, and provide sequential key parameters to a key generator, where each key parameter corresponds to an encryption key previously used for encrypting processor instructions, where the encryption key is comprised of a plurality of encryption key characters; the key generator, operatively coupled to the controller, wherein the key generator is configured to receive the plurality of sequential key parameters from the controller, generate a plurality of decryption keys, where each decryption key corresponds to a key parameter and is comprised of a plurality of decryption key characters, where each decryption key character corresponds to an encryption key character, and load each decryption key into a memory bank via a first bus switch; a plurality of memory banks, each memory bank operatively coupled to both the key generator through the first bus switch and a combiner through a second bus switch, where each memory bank is alternately loaded with one decryption key from the key generator; the first bus switch, operatively coupled to the controller, wherein the first bus switch is configured to receive a first bus switch command from the controller, and change position from one memory bank to another memory bank in response to the first bus switch command to facilitate a loading of a decryption key into the latter memory bank by the key generator; the second bus switch, operatively coupled to the controller, wherein the second bus switch is configured to receive a second bus switch command from the controller, and change position from one memory bank to another memory bank in response to the second bus switch command to facilitate a retrieval of at least one decryption key character from the latter memory bank by the combiner; and the combiner, operatively coupled to the second bus switch, the storage device, and the processor, wherein the combiner is configured to perform a decryption process on the encrypted code of each instruction of a set of encrypted processor instructions, whereby the resulting decrypted code is executed immediately by the processor after being decrypted.