Patent ID: 7783935

Claim:
A bit error rate reduction buffer comprising: a data recovery circuit, the data recovery circuit having differential bit pair inputs and differential bit pair outputs; a plurality of FIFOs, the plurality of FIFOs having differential bit pair inputs and a parallel output; a synchronizer, the synchronizer having a parallel input and a parallel output; a serializer, the serializer having a parallel input and differential bit pair outputs; wherein the differential bit pair outputs of the data recovery circuit are connected to the differential bit pair inputs of the plurality of FIFOs; wherein the parallel output of the plurality of FIFOs is connected to the parallel input of the synchronizer; wherein the parallel output of the synchronizer is connected to the parallel input of the serializer; such that the differential bit pair inputs of the data recovery circuit are driven by a first high speed serial (HSS) link; such that the different bit pair outputs of the serializer drive a second HSS link.