Patent ID: 6870787

Claim:
A configuration for checking an address generator of a test apparatus of an integrated circuit, comprising: an address bus having lines; a set of first switching devices connected to said lines and to the address generator, the address generator having a given number of address outputs connected by said set of first switching devices to said lines of said address bus for outputting first address values, generated in the address generator, onto said address bus; a set of second switching devices connected to said lines; at least one access point; and a memory apparatus with a plurality of memory elements equal to the given number of address outputs of the address generator and connected to said set of second switching devices, said memory apparatus receiving an external address signal for storing second address values, and the second address values stored in said memory apparatus being output from said memory elements of said memory apparatus onto said lines of said address bus through said set of second switching devices, said memory apparatus storing values of address signals present on said lines of said address bus, said memory apparatus connected to said access point and the values stored being output by said memory apparatus to said access point.