Patent ID: 7564287

Claim:
An input buffer protection circuit comprising: a first NMOS transistor with a source, drain and gate coupled to an input terminal of the input buffer, a pad and a chip peripheral positive power supply voltage (VDDP), respectively; and a first PMOS transistor with a source, drain and gate coupled to the pad, the input terminal of the input buffer and a first terminal of a biasing circuit, respectively, wherein the biasing circuit further comprises: a second terminal coupled to the pad and generates at the first terminal a voltage lower than the pad's input signal voltage (VPAD) to turn on the PMOS transistor when the VPAD is lower than or equal to the VDDP, or a voltage substantial equals to the VPAD to turn off the PMOS transistor when the VPAD is higher than the VDDP; a third terminal coupled to the input terminal of the input buffer; a second NMOS transistor with a source, drain and gate coupled to the first terminal, the third terminal and the VDDP, respectively; and a second PMOS transistor with a source, drain and gate coupled to the second terminal, the first terminal and the VDDP, respectively.