Patent ID: 8921194

Claim:
A method of fabricating a lateral PNP bipolar junction transistor, the method comprising: forming a sacrificial base pedestal on a top surface of a first device region at an intended location for a first base contact; forming spacers on sidewalls of the sacrificial base pedestal; selectively forming a layer of a p-type semiconductor material on a first portion and a second portion of the top surface of the first device region to form an emitter and a collector that each have an epitaxial relationship with the first device region; and forming the first base contact at the intended location on the top surface of the first device region that is aligned with a base comprised of an n-type semiconductor material within the first device region, wherein the emitter and the collector are raised relative to the top surface of the first device region, the spacers self-align the emitter and the collector with the first base contact during the selective formation of the layer, and the first base contact and the base are positioned laterally between the emitter and the collector.