Patent ID: 7544984

Claim:
A memory device, comprising: at least one gettering region formed in a semiconductor substrate, the gettering region including a predetermined arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate, wherein: the predetermined arrangement of precisely-formed voids are formed using a surface transformation process to transform holes or trenches formed with predetermined dimensions and spacing through a surface of a material with a defined melting temperature to form the plurality of precisely formed voids within the material; and the predetermined arrangement of the plurality of precisely-formed voids includes voids with a predetermined size, shape and spacing controlled by the predetermined dimensions and spacing of the trenches or holes; a memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells; a plurality of word lines, each word line being connected to a row of memory cells; a plurality of bit lines, each bit line being connected to a column of memory cells; and control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations.