Patent ID: 8338956

Claim:
A semiconductor device, comprising: a substrate having a first contact region and a second contact region; a foundation layer provided in the second contact region to form a difference in levels between the second contact region and the first contact region; a lower layer side stacked body provided in the first contact region and the second contact region to cover the foundation layer, the lower layer side stacked body including a plurality of conductive layers stacked alternately with a plurality of insulating layers, an upper level portion of the lower layer side stacked body stacked on the foundation layer being patterned into a stairstep configuration; an upper layer side stacked body provided on a lower level portion of the lower layer side stacked body stacked in the first contact region, the upper layer side stacked body including a plurality of conductive layers stacked alternately with a plurality of insulating layers, the upper layer side stacked body being patterned into a stairstep configuration; an inter-layer insulating layer covering portions of the lower layer side stacked body and the upper layer side stacked body patterned into the stairstep configurations; and a plurality of contact electrodes provided respectively in a plurality of contact holes punched through the inter-layer insulating layer to reach the conductive layers of the portions of the lower layer side stacked body and the upper layer side stacked body patterned into the stairstep configurations.