Patent ID: 8580622

Claim:
A method of forming a non-volatile programmable memory device situated on a substrate comprising: forming a floating gate for the non-volatile programmable memory device from a first layer, wherein said first layer is shared by the non-volatile programmable memory device and at least one other device situated on the substrate and associated with at least one of a logic gate or a volatile memory; and forming a drain region comprised of a first drain region and at least one separate second drain region, first and second channel regions respectively for coupling the first drain region and the at least one separate second drain region to a same source region, wherein the first and second channel regions are for conducting current between the same source region and respectively the first drain region and the at least one separate second drain region, such that (i) an amount of capacitive coupling between said gate and said drain region is determined by an amount that portions of said gate overlap said first drain region and said at least one second drain region, and (ii) a voltage applied to at least one of said first drain region or said at least one second drain region can be imparted to the gate through the capacitive coupling between said gate and said drain region to program said programmable memory device to a selected one of at least three logic states.