Patent ID: 7433235

Claim:
A non-volatile semiconductor memory device comprising: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a charge pump and voltage regulator configured to supply a substantially constant read voltage; a string select line driver circuit configured to drive the string select line with a first reduced voltage comprising: a first voltage drop circuit configured to reduce the read voltage during a read operation; and a first high voltage switch configured to output the first reduced voltage in response to a read enable signal; and a ground select line driver circuit configured to drive the ground select line with a second reduced voltage comprising: a second voltage drop circuit configured to reduce the read voltage during the read operation; and a second high voltage switch configured to output the second reduced voltage in response to the read enable signal.