Patent ID: 8214774

Claim:
A method for making changes to a design layout of a System-on-Chip (SoC) integrated circuit device, the method comprising: providing a design instrumentation with debug infrastructure logic on the design layout of the SoC integrated circuit device based upon an initial design file, the debug infrastructure logic based upon filler cells in at least spare regions of the initial design file and logic cells in the initial design file; executing a synthesis of the initial design file; executing a Place & Route of the design layout by replacing the filler cells with mask programmable Engineering Change Order (ECO) base cells configured as filler cells; implementing functional changes on the SoC integrated circuit device via a software reconfiguration capability of the debug infrastructure logic based upon logic blocks obtained by performing at least one of substituting at least one mask programmable ECO base cell configured as a functional logic cell for at least one of the logic cells, and using the logic cells; executing a modification of the design instrumentation, and executing a synthesis of the modification applied to the debug infrastructure logic; and executing on the SoC integrated circuit device an ECO process by replacing at least one of the mask programmable ECO base cells configured as the filler cells and placed during the Place & Route execution with the at least one mask programmable ECO base cell configured as the functional cell.