Patent ID: 7560971

Claim:
A level shift circuit comprising: a first transistor having a gate, a source, and a drain, wherein the gate is coupled to a first input, the source is coupled to a first voltage supply, and the drain is coupled to a first output; a second transistor having a gate, a source, and a drain, wherein the gate is coupled to a second input, the source is coupled to the first voltage supply, and the drain is coupled to a second output, and wherein the second input has an inverted logic state of the first input; a third transistor having a gate, a source, and a drain, wherein the gate is coupled to the second output and the drain is coupled to the first output; a fourth transistor having a gate, a source, and a drain, wherein the gate is coupled to the first output, the source is coupled to a second voltage supply, and the drain is coupled to the second output; and a first control circuit comprising: a first control inverter having an input and an output, wherein the input is coupled to a non-inverted version of a third voltage supply; a first control transistor having a gate, a source, and a drain, wherein the gate is coupled to an output of the first control inverter, the source is coupled to the first voltage supply, and the drain is coupled to the first output; and a second control transistor having a gate, a source, and a drain, wherein the gate is coupled to the output of the first control inverter, the source is coupled to the second voltage supply, and the drain is coupled to the source of the third transistor.