Patent ID: 8553654

Claim:
A method for triggered expression evaluation that obtains an evaluation result responsive to a change to an input value of an expression graph having a plurality of internal and external nodes, the method implemented by one or more processing circuits of a computing device and comprising: scheduling reception of a trigger by one of the internal nodes based on a priority of the internal node, such that the internal node will only receive the trigger after internal nodes having a higher priority have received their respective triggers; and based on the scheduled reception, evaluating the plurality of internal and external nodes in the expression graph to obtain the evaluation result; wherein each external node comprises an input value and provides a trigger output to at least one of the internal nodes upon a change of its input value; wherein each internal node comprises an expression on one or more operands, each of the one or more operands comprising a trigger from one of the internal or external nodes; and wherein the priority of a given internal node is a function of a quantity of internal nodes operatively connected between the given internal node and a most distant external node operatively connected thereto.