Patent ID: 8093697

Claim:
A microelectronic package comprising: a substrate having a first surface and a second surface remote from the first surface, the first surface including a first region and a second region; a microelectronic element overlying the first region; first conductive elements projecting above the second region, first and second elements of said first conductive elements having substantially planar top surfaces remote from said first surface of said substrate and being electrically connected through said substrate to said microelectronic element for carrying a first signal electric potential on said first of said first conductive elements and for simultaneously carrying a second electric potential on said second of said first conductive elements, said second electric potential being different from said first signal electric potential; second conductive elements projecting from the second surface, said second conductive elements being electrically interconnected with said microelectronic element; and a molded encapsulant layer overlying the first and second regions of said first surface and at least a portion of said microelectronic element and contacting and surrounding at least portions of said first conductive elements, said encapsulant layer extending a first height above the first region and having a substantially planar major surface at a second height above the second region, the first height being different from the second height, wherein the substantially planar top surfaces are uncovered by said encapsulant layer and substantially parallel to said major surface of said encapsulant layer.