Patent ID: 7915134

Claim:
A method of forming an integrated MIM capacitor, comprising the steps of: providing a semiconductor substrate having a top surface; forming a lower capacitor plate and a High K (HiK) dielectric layer ( 160 ) consisting of a material selected from the group consisting of Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , and Al 2 O 3 ; by the step comprising: (i) forming a doped well ( 35 ) in said surface of said semiconductor substrate; (a) then forming a silicide region ( 141 B) in said surface of said doped well ( 35 ) followed by forming said High K (HiK) dielectric layer ( 160 / 40 ) on said surface of said silicide region ( 141 B); or (b) then forming said HiK dielectric layer ( 160 ) on said surface of said doped well ( 35 ); or (ii) forming a Shallow Trench Isolation (STI) region ( 33 ) in said semiconductor substrate below said surface of said semiconductor substrate followed by forming a conductor layer ( 38 P) overlying said STI region ( 33 ), and then followed by forming said HiK dielectric layer ( 40 ) over said conductor layer ( 38 P); and then forming a second capacitor plate 142 over said HiK dielectric layer ( 40 ) above said lower capacitor plate.