Patent ID: 7184512

Claim:
A phase locked loop circuit, comprising: a variable frequency oscillator; a signal generation circuit for generating, on the basis of an oscillation frequency signal of said oscillator, a first signal having the same phase as said oscillation frequency signal has, a second signal having a phase delayed by a first phase amount relative to the phase of said first signal and a third signal having a phase delayed by a second phase amount relative to the phase of said first signal, said second phase amount being larger than said first phase amount; a phase detection circuit for comparing the phase of said third signal generated in said signal generation circuit with a phase of an input signal, and outputting one of a first phase control signal to advance the phase of the oscillation frequency signal from said variable frequency oscillator and a second phase control signal to delay the phase of the oscillation frequency signal on the basis of the result of comparison; and a frequency detection circuit for sampling said first and second signals generated in said signal generation circuit in synchronism with said input signal, and outputting one of a first frequency control signal to set a frequency of the oscillation frequency signal of said variable frequency oscillator higher and a second frequency control signal to set the frequency of said variable frequency oscillator lower, when a combination of logic values of sampled two signals is of a specific pattern; wherein said signal generation circuit is configured to set said second phase amount at a phase amount that makes a change point of said third signal be positioned within said specific pattern.