Patent ID: 7352632

Claim:
A non-volatile semiconductor memory device comprising: a selection transistor constituted of an MOS transistor having a gate electrode; a bit line connected to one end of the selection transistor; a word line connected to the gate electrode of the selection transistor; and a cell transistor having a control gate electrode which is not electrically connected anywhere so as to be in a floating potential state, one end of the cell transistor being connected to the other end of the selection transistor, the cell transistor being constituted of a MOS transistor having the same polarity as the selection transistor; and a source line connected to the other end of the cell transistor, wherein in erasing data stored in the cell transistor, the source line is provided with a first voltage, the word line is supplied with a second voltage, and the bit line is supplied with a third voltage, and each of the first and second voltages is a voltage of positive polarity, and the third voltage is a ground voltage.