Patent ID: 7779314

Claim:
A system for transmitting test data in a chip, wherein the chip is connected to a high speed bus and a low speed bus, comprising: a core circuit mastering the encoding/decoding operations of data; and a high-speed bus interface circuit connected between the core circuit and the high speed bus comprising: a transmission circuit connected to the core circuit for implementing a transmission mechanism of the high-speed bus interface circuit; and a receiving circuit connected to the core circuit for implementing a receiving mechanism of the high-speed bus interface circuit; wherein when transmitting the test data in the chip: an inner loop path in the high-speed bus interface circuit is established, and the transmission mechanism transmits the testing data to the receiving mechanism via the inner loop path; a multiplex module selects the testing signal from the transmission circuit to be transmitted to the receiving circuit via the inner loop path; when normal operating the chip, the multiplex module selects data from the high-speed bus to be received by the receiving circuit; wherein the data comprises a command address data (CAD) signal, a control signal and a clock signal; and the multiplex module comprises a first multiplexer for selecting the CAD signal; a second multiplexer for selecting the control signal; and a third multiplexer for selecting the clock signal.