Patent ID: 8024393

Claim:
A hardware processor, comprising: a load-store unit configured to provide data to other units of the processor, and to receive data from other units of the processor; an integer execution unit to configured to perform integer operations; and a floating point execution unit to configured to perform floating point operations, the floating point unit, comprising: a multiplier unit configured to accept a first operand having a mantissa and a second operand having a mantissa, wherein the multiplier unit is further configured to: multiply the first and second operands to produce a product value having a mantissa, and round the product value to produce a multiplier output value having an internal format that includes a mantissa, the mantissa having more than one bit to the left of the binary point, wherein at least one of the more than one bits to the left of the binary point has a value of one (1); an adder unit configured to add the multiplier output value and a third operand to form a sum value; and an instruction fetch unit configured to fetch instructions for processing by the integer execution unit and the floating point execution unit.