Patent ID: 8014418

Claim:
An apparatus comprising a scheduler, and a content addressable memory coupled to the scheduler, wherein the scheduler is to generate a plurality of content addressable memory entries comprising bits, which represent a group of available and non-available time slots, wherein size of each of the plurality of content addressable memory entries is determined based on a size (M) of an aggregation unit, which is a portion of a total number of time slots (N) in a first time horizon, wherein the scheduler is to generate a first key in response to receiving a first burst data unit, wherein the scheduler is to determine a set of earliest available time slots based on a matching the first key with the plurality of content addressable memory entries, wherein the scheduler is to allocate the first burst data unit to the set of earliest available time slots, and wherein the content addressable memory is to compare the first key with the plurality of content addressable memory entries.