Patent ID: 8432208

Claim:
A pulse width modulation (PWM) generator ( 302 ) for generating a phase shifted PWM signal ( 350 ) that is synchronized with a master time base ( 300 ) and maintains PWM data-set coherency, comprising: a duty cycle register ( 310 ) storing a duty cycle value; a duty cycle counter ( 314 ) having a clock input coupled to a clock generating a plurality of clock pulses and incrementing a duty cycle count value for each of the plurality of clock pulses received; a duty cycle comparator ( 312 ) coupled to the duty cycle register ( 310 ) and the duty cycle counter ( 314 ), wherein the duty cycle comparator ( 312 ) compares the duty cycle count value to the duty cycle value and generates a PWM signal ( 350 ) when the duty cycle count value is less than or equal to the duty cycle value; a phase offset register ( 316 ) storing a phase offset value and coupled to the duty cycle counter ( 314 ), wherein the phase offset value is loaded into the duty cycle counter ( 314 ) to become a new duty cycle count value when a PWM cycle start signal ( 348 ) is asserted from a master time base ( 300 ); a duty cycle buffer register ( 320 ) coupled to the duty cycle register ( 310 ), wherein the duty cycle buffer register ( 320 ) stores a new duty cycle value; a phase offset buffer register ( 318 ) coupled to the phase offset register ( 316 ), wherein the phase offset buffer register ( 318 ) stores a new phase offset value; and logic for generating a new data-set signal ( 332 ) just before starting a next PWM cycle; wherein the new duty cycle value replaces the duty cycle value and the new phase offset value replaces the phase offset value when the new data-set signal ( 332 ) is asserted.