Patent ID: 7061265

Claim:
A reduced leakage logic circuit having a logic input and a logic output comprising: a low leakage logic path having an input coupled to the logic input, a first logic node, a second logic node, and a holding output coupled to the logic output; a first high leakage logic path having a first power-gated stage with an input coupled to the first logic node and an output coupled to a first stage node and a first logic stage having an input coupled to the first stage node, a control input coupled to the second logic node and an output coupled to a second stage node, wherein a first voltage potential is coupled to the first power-gated stage in response to a first logic state coupled from the logic output and decoupled from the first power-gated stage in response to a second logic state of the logic output to propagate a collapsing logic state from the first stage node to the second stage node; and a first driver stage having an input coupled to the second stage node and an output that enhances a current drive capability of the logic output during the second logic state generated in response to an asserted second logic state at the second logic node and an asserted second logic state at the first stage node, wherein a collapsing first logic state on the second stage node disables the first driver stage a delayed time period after an assertion of the second logic state on the logic output.