Patent ID: 8609495

Claim:
A method of fabricating a semiconductor device, comprising: forming first and second fin structures in first and second regions of a substrate, respectively; forming first and second gate structures over the first and second fin structures, respectively, the first and second gate structures including first and second polysilicon (poly) gates, respectively; forming an inter-level dielectric (ILD) over the substrate; performing a chemical mechanical polishing (CMP) on the ILD to expose the first and second poly gates; forming a protection layer to protect the first poly gate of the first gate structure; removing the second poly gate of the second gate structure thereby forming a first trench; removing the protection layer; after removing the second poly gate of the second gate structure thereby forming the first trench, partially removing the first poly gate of the first gate structure thereby forming a second trench; after partially removing the first poly gate of the first gate structure thereby forming the second trench, forming a work function metal layer partially filling the first and second trenches; forming a fill metal layer filling a remainder of the first and second trenches; and removing the metal layers outside the first and second trenches.