Patent ID: 8576608

Claim:
A memory apparatus comprising: a plurality of memory cells, each of the plurality of memory cells including a first resistance change element; and a read-out circuit including a reference memory cell, the read-out circuit configured to compare a resistance state of a memory cell selected from among the plurality of memory cells to a resistance state of the reference memory cell to perform a read-out of the selected memory cell, wherein, the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage in a high resistance state is smaller than a resistance value of the first resistance change element with respect to the applied voltage in the high resistance state, the second resistance change element and the first resistance change element have substantially same resistance change characteristics, and the second resistance change element in the reference cell is formed of a plurality of resistance change elements connected to each other in parallel, and two or more of the plurality of resistance change elements are selected in a read-out operation.