Patent ID: 8330163

Claim:
An active device array mother substrate, comprising: a substrate, having a plurality of panel regions, a circuit region connected to the plurality of panel regions, a first cutting line, and a second cutting line, wherein the second cutting line aligns with an edge of the panel regions and the first cutting line is located in the circuit region between an edge of the substrate and the second cutting line; a plurality of pixel arrays, wherein each pixel array is disposed within each panel region and has a plurality of active devices arranged in an array, and the plurality of active devices comprises: a semiconductor layer, disposed on the substrate, the semiconductor layer comprising a polysilicon structure having a doped source region, a doped drain region and a channel region between the doped source region and the doped drain region; a gate insulation layer, covering the semiconductor layer; a gate electrode layer, disposed on the gate insulation layer above the semiconductor layer; a first dielectric layer, covering the gate electrode layer, wherein the first dielectric layer and the gate insulation layer have a plurality of openings exposing a portion of the semiconductor layer; and a source conductor and a drain conductor, disposed on the first dielectric layer and electrically connected to the semiconductor layer, wherein the source conductor and the drain conductor pass through the first dielectric layer and the gate insulation layer to be in contact with the doped source region and the doped drain region respectively; and a polymer-stabilized alignment curing circuit, disposed on the circuit region, wherein the polymer-stabilized alignment curing circuit comprises: a plurality of curing pads, disposed between the edge of the substrate and the first cutting line; and a plurality of curing lines, having an upper conductive layer connected to the corresponding curing pads and the corresponding pixel array and the first dielectric layer being located between the substrate and the upper conductive layer, wherein the upper conductive layer is in a same layer as the source conductor and the drain conductor.