Patent ID: 7057419

Claim:
A phase sync circuit which extracts a clock signal from an input data signal in a random NRZ format, said phase sync circuit comprising: a phase comparison circuit which makes a comparison between the phase of said clock signal corresponding to an output from said phase sync circuit and the phase of said data signal input to said phase sync circuit; a frequency comparison circuit to which said clock signal, another clock signal having a phase delayed by an approximately ¼ period from said clock signal and said data signal are input, and which makes a comparison between the frequencies of said data signal and said clock signal or said another clock signal; a low-pass filter to which the result of comparison in said phase comparison circuit and the result of comparison in said frequency comparison circuit are input, and which extracts and outputs a direct-current component; a voltage controlled oscillation circuit to which an output signal from said low-pass filter is input, and which outputs said clock signal; and a phase shifter to which said clock signal is input, and which outputs said another clock signal, wherein said frequency comparison circuit has: a sampling block including sampling circuits in two systems which respectively sample said clock signal and said another clock signal by said data signal to separately generate output signals; a waveform shaping block in which waveform shaping is performed on each of the output signals from the sampling circuits in the two systems in said sampling block to make pulses due to jitter contained in said data signal disappear and separately generate output signals; and a phase comparison block in which an advance or a delay of the phase between the output signals from the waveform shaping block is determined.