Patent ID: 8452945

Claim:
A microprocessor comprising: registers, each of said registers having plural locations at different positions within that register; an instruction decoder for decoding instructions, said instructions including first and second indirect-indexing instructions, said first indirect-indexing instruction specifying a first index register of said registers, a first result register of said registers, and a first position of said positions, said second indirect-indexing instruction specifying a second index register of said registers, a second result register of said registers, and a second position of said positions, said second position being different from said first position; and an execution unit for executing said first indirect-indexing instruction so as to write a first result at said first position within said first result register, said first result being at least in part a function of data stored at a first data-storage location at a third position within a first data-storage register of said registers, said first data-storage register and said third position being determined by a first index stored at said first position within said first index register, and said second indirect-indexing instruction so as to write a second result at said second position within said second result register, said second result being at least in part a function of data stored at a second data-storage location at a fourth position within a second data-storage register of said registers, said second data-storage register and said fourth position being determined by a second index stored at said second position within said second index register.