Patent ID: 8661382

Claim:
A computer implemented method for soft error modeling of circuits, the method comprising: receiving a soft error (SE) specification and design information from a design entry, wherein said SE specification comprises expected SE behavior of a node; creating a logical simulation model based on said SE specification and said design information; and performing a logical verification based on said logical simulation model to produce a first result, wherein performing said logical verification comprises: selecting a first node for injection; injecting an SE into said first node to produce a first result; and based on said first result differing from said expected SE behavior in said SE specification, providing said first result to said design entry; creating a netlist based on said SE specification and said design information, wherein said netlist comprises a specification-based-logic-derating derived from said SE specification; and performing a physical design verification based on said netlist, a logic derating, and clock information, said performing a physical design verification comprising calculating node failure-in-time (FIT) based on said specification-based-logic-derating.