Patent ID: 6906575

Claim:
A semiconductor circuit comprising: a first voltage relaxation circuit coupled between first and second nodes, the first node receiving a first potential; a second voltage relaxation circuit coupled between third and fourth nodes, the third node receiving said first potential; a first charge pump circuit with an outout thereof coupled to the second node; a second charge pump circuit with an output thereof coupled to the fourth node; a third charge pump circuit with an output thereof coupled to the first charge pump; a fourth charge pump circuit with an output thereof coupled to the second charge pump; a first rectifier MOSFET with a source-drain path thereof coupled between the second node and a fifth node; and a second rectifier MOSFET with a source-drain path thereof coupled between the fourth node and said fifth node, wherein the first charge pump circuit outputs a first signal which varies between a high level and a low level alternately and periodically, wherein the second charge pump circuit outputs a second signal which varies between a high level and a low level alternately and periodically, the high level of the second signal being equal to the high level of the first signal, wherein the third charge pump circuit outputs a third signal which varies between a high level and a low level alternately and periodically, the high level of the third signal being lower than the high level of the first signal, wherein the fourth charge pump circuit outputs a fourth signal which varies between a high level and a low level alternately and periodically, the high level of the fourth signal being equal to the high level of the third signal, wherein the first voltage relaxation circuit comprises first and second MOSFETs having their source-drain paths coupled in series between the first and second nodes, and wherein the second voltage relaxation circuit comprises third and fourth MOSFETs having their source-drain paths coupled in series between the third and fourth nodes.