Patent ID: 8736045

Claim:
A wafer level packaged circuit device, comprising: a device wafer bonded to a cap wafer; the device wafer including a polyimide layer formed in a first region of a substrate of the device wafer, and a first solder metal stack layer formed on the polyimide layer, wherein the polyimide layer is a same polyimide layer that is also used in the formation of an integrated circuit on the device wafer, and the first solder metal stack layer is also a same first solder metal stack layer used to form a sealing ring for the device wafer; the cap wafer including an antireflective coating layer formed in a second region of a substrate of the cap wafer, and a second solder metal stack layer formed on the antireflective coating layer, wherein the antireflective coating layer is a same antireflective coating layer that is also formed on a cavity portion of the cap wafer, and the second solder metal stack layer is also a same second solder metal stack layer used to form a sealing ring for the cap wafer; and an integrated bond gap control structure (BGCS) disposed between the device wafer and the cap wafer, the integrated BGCS comprising the polyimide layer, the first solder metal stack layer, the second solder metal stack layer, and the antireflective coating layer.