Patent ID: 8013655

Claim:
An apparatus comprising: an input stage having a first branch and a second branch; a first flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first flip-flop that is coupled to the first branch, and wherein the second input terminal of the first flip-flop is coupled to the second branch, and wherein the first flip-flop operates in a first voltage domain; a level shifter that is coupled to the output terminal of the first flip-flop, wherein the level shifter operates in a second voltage domain, and wherein the level shifter includes: a reset stage having a first capacitor that is coupled to the output terminal of the first flip-flop; a set stage having a second capacitor that is coupled to the output terminal of the first flip-flop; and a second flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second flip-flop is coupled to the reset stage, and wherein the second input terminal of the second flip-flop is coupled to the set stage; and a logic circuit that is coupled to the output terminal of the second flip-flop, the first branch, and the second branch, and that receives an input signal.