Patent ID: 7725855

Claim:
A method of improving timing of a circuit design for a programmable integrated circuit, the method comprising: within a graph representation of the circuit design comprising nodes representing components and edges representing wires, identifying a timing critical wire of the circuit design, wherein the timing critical wire has a negative slack; determining from the graph, by a computer, a fanout free cone, according to the timing critical wire, that comprises a plurality of nodes linked by edges, wherein each of a plurality of leaf nodes external to the fanout free cone directly links to at least one node within the fanout free cone through an edge and, wherein the timing critical wire directly links a selected leaf node of the plurality of leaf nodes, denoted as a critical leaf node, with a node of the fanout free cone; selecting, by the computer, at least one leaf node set comprising a plurality of leaf nodes that are symmetric, wherein each leaf node set comprises the critical leaf node and at least one non-critical leaf node; swapping, by the computer, at least two wires linking leaf nodes, selected only from the leaf node set in the circuit design, to nodes within the fanout free cone; and storing the circuit design within memory.