Patent ID: 7344923

Claim:
A method for fabricating an NROM semiconductor memory device, said method having the steps of: (a) providing a plurality of u-shaped MOSFETs—which are spaced apart from one another and have a multilayer dielectric, which is suitable for charge trapping—along rows in a first direction and along columns in a second direction in trenches of a semiconductor substrate by carrying out the following steps: (a1) using a hard mask to form the trenches as longitudinal trenches corresponding to respective columns of u-shaped MOSFETs; (a2) forming the multilayer dielectric on the trenches walls; (a3) filling the trenches partially with a gate electrode material; (a4) closing the trenches with an insulation cover which is flush with the surface of the hard mask; (a5) removing the insulation cover, the gate electrode material and the multilayer dielectric from the trench walls and isolation regions are formed in order to separate the individual u-shaped MOSFETs along the columns; (b) providing source/drain regions between the u-shaped MOSFETs in interspaces between the rows which run parallel to the columns; (c) providing isolation trenches in the source/drain regions between the u-shaped MOSFETs of adjacent columns as far as a particular depth in the semiconductor substrate, said isolation trenches cutting the source/drain regions into respective bit lines; (d) filling the isolation trenches with an insulation material; and (e) providing word lines for connecting respective rows of u-shaped MOSFETs.