Patent ID: 7054211

Claim:
A semiconductor memory storage comprising: a memory cell array with a plurality of memory cells arranged in a matrix; a plurality of word line drivers connected through word lines to a plurality of the memory cells arranged in a row in said memory cell array for activating said word lines in accordance with the result of decoding an address signal; a sense amplifier for detecting the activated state of said memory cells; and a word line responsive sense amplifier control circuit connected to said word lines for activating said sense amplifier upon activation of said word lines, wherein said word line responsive sense amplifier control circuit includes: a discharge switching element inserted between a dummy bit line and the ground potential; a plurality of word line responsive switching elements connected to said word lines for transmitting the activation signal of said word lines to said discharge switching element; and a logic gate for outputting an enable signal to said sense amplifier in response to the discharge of said dummy bit line.