Patent ID: 7480607

Claim:
A digital circuit simulation method, comprising: providing a digital circuit design which includes (a) a first source latch, (b) a destination latch, (c) a logic cone, (d) a first WAM (Wired Asynchronous Model) circuit electrically coupling an output of the first source latch to a first input of the logic cone, (e) a WAGG (Wired Asynchronous Glitch Generator) circuit electrically coupling an output of the logic cone to an input of the first source latch, wherein the first source latch operates according to a first clock signal, wherein the first WAM circuit and the destination latch operate according to a second clock signal which is asynchronous to the first clock signal, and wherein there exist at least two different signal paths from the first input of the logic cone through the logic cone to the output of the logic cone; performing a zero-delay simulation of the digital circuit design, wherein said performing the zero-delay simulation comprises in response to a first condition of (a) the first WAM circuit entering an uncertainty state in which the first WAM circuit generates a random value of 1 or 0 at the first input of the logic cone, (b) the logic cone being vulnerable to a positive glitch, and (c) the output of the logic cone being at logic 0, causing the WAGG circuit to generate a random value of 0 or 1 at the input of the destination latch; and in response to the WAGG circuit generating the random value of 0 or 1 at the input of the destination latch, determining that there is an uncertainty in term of value at the input of the destination latch.