Patent ID: 7145829

Claim:
A random access memory system comprising: an array of dual-port dynamic memory cells having a storage node connected to a first pass transistor that is controlled by a write word line and further connected to a write bitline, said storage node further being connected to the gate of a first read transistor that is connected in series between a voltage supply and a read pass transistor, said read pass transistor being further connected to a read bitline and having a gate controlled by a read word line; and support circuits for said array, including refresh means for refreshing cells in said array comprising a counter for specifying a next row to be refreshed and a storage buffer for storing the contents of a last row to be read, in which the stored contents of an (n−1)th row of the array are written back from the storage buffer into the cells of the (n−1)th row of the array after a refresh latency period and during the same clock cycle that the contents of the nth row are written into the storage buffer.