Patent ID: 8601246

Claim:
A method comprising: receiving a first instruction, said first instruction comprising an opcode field, a first field to indicate a first operand in one of a register and memory and having a first plurality of data elements including a first operand first data element and a first operand second data element, and a second field to indicate a second operand in one of a register and memory and having a second plurality of data elements including a second operand first data element and a second operand second data element, each of the first operand first data element, the first operand second data element, the second operand first data element, and the second operand second data element having a length of N bits indicated by a third field of the first instruction, the third field of the instruction capable of indicating a plurality of different lengths for the data elements, wherein the third field includes a plurality of bits that are separate from a plurality of bits of the opcode field, and wherein the length of the N bits is selected from 16-bits and 32-bits; and storing a first resultant data in a destination register in response to said first instruction, said first resultant data including half of the data elements from the first plurality of data elements and from the second plurality of data elements, said first resultant data including the first operand first data element, the second operand first data element, the first operand second data element, and the second operand second data element, in which data elements from the first and second operands are interleaved in the first resultant data, wherein the destination register has a same size as each of the first and second source operands, and wherein the destination register is part of a set of registers that are used to store both packed data and floating point data.