Patent ID: 8394700

Claim:
A process of forming an electronic device, the process comprising: providing a substrate that includes a conductive region that is below and spaced apart from a primary surface of the substrate; forming a first gate structure overlying a first body region at a location where a first memory cell of a nonvolatile memory array is being formed, wherein the first body region is between the first gate structure and the conductive region, and the first body region overlies the conductive region; forming a second gate structure overlying a second body region at a location where a second memory cell of the nonvolatile memory array is being formed, wherein the second body region is between the second gate structure and the conductive region, and the second body region overlies the conductive region; and forming first and second drain regions over and electrically connected to the conductive region, wherein the first drain region is part of the first memory cell, and the second drain region is part of the second memory cell, wherein a combination of the first and second drain regions and the conductive region is part of a common drain region for the first and second memory cells.