Patent ID: 8637844

Claim:
A memory device comprising: a plurality of conductive portions located on an upper surface of a substrate, wherein an isolation region is present between each neighboring conductive portion of said plurality of conductive portions; a first insulating layer located above said plurality of conductive portions, each isolation region and said substrate; wherein at least one via is present in said first insulating layer that extends to an upper surface of one conductive portion of said plurality of conductive portions; a Si diode having a single crystal crystalline structure present in said at least one via and in contact with an upper surface of said one conductive portion, wherein said Si diode comprises a first dopant region and a second dopant region, wherein said first dopant region has an electrical conductivity different than said second dopant region; a silicide contact located above said Si diode and present in said at least one via; a second insulating layer located on a surface of said first insulating layer, wherein said second insulating layer includes at least one opening in communication with said at least one via in said first insulating layer, wherein said at least one opening has a width greater than a width of said at least one via; a spacer located on each vertical sidewall of said second insulating layer and in said at least one opening, wherein sidewall edges of the spacer in contact with each vertical sidewall of the second insulating layer extend beyond sidewall edges of said silicide contact and sidewall edges of said Si diode in said at least one via; a phase change electrode located on a surface of said silicide contact and between each spacer present in said at least one opening; and a phase change material located on a surface of said phase change material, a surface of each spacer and extending onto a surface of said second insulating layer.