Patent ID: 7787284

Claim:
A multi-supply static random access memory (SRAM) supplied by a base supply voltage (V dd ), portions of said multi-supply SRAM being supplied by an increased supply voltage (V dd+ ), said increased supply supplying a voltage above said base supply, said multi supply SRAM including an array of SRAM cells, each of said SRAM cells comprising: a pair of cross-coupled inverters connected between an increased supply line (V dd+ ) line and a supply return line, each of said cross coupled inverters comprising: a first tailored field effect transistor (FET) of a first conduction type, said tailored FET exhibiting less leakage at said base voltage than base devices having a stated base design characteristic, said first tailored FET connected drain to source between a storage node and a return voltage, and a FET of a second conduction type connected drain to source between said storage node and said V dd+ line, said storage node of the other of said pair of cross-coupled inverters connected to a control terminal of both said first tailored FET and said FET of said second conduction type; and a pair of tailored FET pass gates of said first conduction type, each connected between one said storage node and one of a pair of complementary bit lines.