Patent ID: 8122279

Claim:
A system comprising: a plurality of digital circuit components; a bidirectional ring bus which includes a plurality of latches, wherein each of the latches is coupled to a corresponding one of the digital circuit components to enable the digital circuit components to transmit and receive data on the bus; and a timing system which is configured to generate a plurality of clock signals, wherein each of the clock signals is phase-shifted with respect to the remainder of the clock signals, and to provide each of the clock signals to a different one of the digital circuit components; wherein each of the latches is clocked based on the clock signal provided to the digital circuit component associated with the latch; wherein the system comprises a multiprocessor and the digital circuit components comprise processor cores, wherein each of the processor cores includes a controller that receives the clock signal associated with the processor core, wherein the controller is coupled to the latch associated with the processor core; and wherein the bidirectional ring bus has a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction; further comprising an arbiter coupled to each of the processor cores and configured to control data transfers on the bidirectional ring bus, wherein the arbiter is configured to provide the clock signals to the processor cores in a manner that causes non-adiacent ones of the processor cores to be fired consecutively, and wherein the arbiter is coupled to each controller and is configured to cause each controller to selectively modify the received clock signal and to provide the modified clock signal to the associated latch.