Patent ID: 7727841

Claim:
A method of manufacturing a semiconductor device with dual gates, comprising: providing a semiconductor substrate having a first region on which a MOS transistor of a first conductivity type will be formed and a second region on which a MOS transistor of a second conductivity type will be formed; forming a dielectric layer, a first metallic conductive layer and a second metallic conductive layer on the first and second regions; etching the second metallic conductive layer formed on the first metallic conductive layer of the second region, thereby a metal pattern is formed on the first metallic conductive layer of the first region; etching the first metallic conductive layer formed on the dielectric layer of second region using the metal pattern as an etching mask; forming a polysilicon layer on the dielectric layer of the second region and the metal pattern of the first region; forming a first gate electrode by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region, the first gate electrode including a lower metallic conductive pattern, an upper metallic conductive pattern, and a polysilicon pattern; and forming a second gate electrode by etching portions of the polysilicon layer formed directly on the dielectric layer of the second region.