Patent ID: 7190610

Claim:
A computer system comprising a memory array formed on a substrate assembly comprising at least one semiconductor layer, said memory array comprising a plurality of memory cells arranged in rows and columns, each of said memory cells comprising: a first semiconductor structure and a second semiconductor structure formed within said at least one semiconductor layer, said first and second semiconductor structures being coupled to a first voltage input through respective first and third contacts formed within said first and second semiconductor structures; a first pull-up transistor formed in said first semiconductor structure, said first pull-up transistor comprising a first gate, a first source and a first drain, said first source being coupled to said first semiconductor structure such that said first source is coupled to said first voltage input through a combined parasitic resistance of said first semiconductor structure; a first pull-down transistor formed in said at least one semiconductor layer, said first pull-down transistor comprising a second gate coupled to said first gate, a second source coupled to a second voltage input, and a second drain coupled to said first drain; a second pull-up transistor formed in said second semiconductor structure, said second pull-up transistor comprising a third gate, a third source and a third drain, said third source being coupled to said second semiconductor structure such that said third source is coupled to said first voltage input through a combined parasitic resistance of said second semiconductor structure; a second pull-down transistor formed in said at least one semiconductor layer, said second pull-down transistor comprising a fourth gate coupled to said third gate, a fourth source coupled to said second voltage input, and a fourth drain coupled to said third drain; a first access transistor formed in said at least one semiconductor layer having a first terminal coupled to said first and second drains, a second terminal coupled to a first column line and a first access gate coupled to a row line; and a second access transistor formed in said at least one semiconductor layer having a third terminal coupled to said third and fourth drains, a fourth terminal coupled to a second column line and a first access gate coupled to a row line, wherein a memory decoder is coupled to said plurality of memory cells for accessing each of said plurality of memory cells via said respective ones of a plurality of said row lines and respective ones of a plurality of said first and second column lines, and a microprocessor is in communication with each of said plurality of memory cells via said memory decoder.