Patent ID: 8134813

Claim:
An integrated circuit (“IC”) having an input/output (“I/O”) circuit comprising: an input pin; a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) having a first NMOS source and a first NMOS drain incorporating a silicide block electrically coupling the first NMOS FET to the input pin; a first P-channel metal-oxide semiconductor (“PMOS”) FET having a first PMOS drain directly connected to the input pin, a first PMOS source electrically coupled to a positive voltage supply, and a PMOS N-well electrically coupled to the input pin through an electro-static discharge (“ESD”) well bias circuit providing an ESD well bias voltage; and an NMOS low-voltage differential signal (“LVDS”) driver having a second drain of a second NMOS FET directly connected to the input pin, the second NMOS FET fabricated within a first P-tap guard ring electrically coupled to ground, an N-well guard ring coupled to the ESD well bias voltage surrounding the first P-tap guard ring, and a second source of the second NMOS FET being electrically coupled to a third drain of a third NMOS FET fabricated within a second P-tap guard ring electrically coupled to ground and surrounding the third NMOS FET; wherein the first NMOS FET has a first NMOS breakdown voltage, the second NMOS FET has a second NMOS breakdown voltage greater than the first NMOS breakdown voltage, and the first PMOS FET has a first PMOS breakdown voltage greater than the first NMOS breakdown voltage.