Patent ID: 7783690

Claim:
An electronic computing circuit for implementing a permutation operation for a plurality of M input bits, said circuit comprising: a) two separate input register sets for receiving said plurality of M input bits, where the two input register sets includes a first input register set and a second input register set which are arranged at opposite sides of a macro crossbar circuit arranged in a polygonal form on a chip; b) an output register set arranged in a central region of said polygonal form; c) a first multiplexer set connected to the first input register set for selecting bits there from, wherein said first multiplexer set extends from a respective first outer region of said polygonal form to the central region of said polygonal form, d) a second multiplexer set connected to the second input register set for selecting bits there from, wherein said second multiplexer set extends from a respective second outer region of said polygonal form to the central region of said polygonal form; and e) a third multiplexer, with inputs connected to the outputs of said first and second multiplexer sets for selecting bits therefrom, wherein an output of said third multiplexer is connected to said output register set.