Patent ID: 7692448

Claim:
A system for organizing reprogrammable three dimensional (3D) field programmable gate arrays (FPGAs), comprising: a set of arrays of logic and memory components on two or more layers of a hybrid multilayer logic device; a set of SRAM tiles on the outer edge of each layer; a set of logic block arrays on tiles in the interior of each layer arranged in symmetrical rows connected by interconnects and TSVs; a set of switch matrices on tiles in the interior of each layer to connect the logic block arrays and the memory components with interconnects and TSVs; a set of look up tables (LUTs) on memory tiles for access to arithmetic data; movable interconnects within the logic block arrays that change position when activated by at least one switch matrix from one ASIC position to another ASIC position; and a set of TSVs that connect the tiles of one layer to the tiles of an adjacent layer.