Patent ID: 7296251

Claim:
A method of partitioning and floorplanning a chip represented by a netlist that includes macros to minimize power dissipated by the chip, the method comprising the steps of: a) generating physically implementable voltage island partitions that includes creating an internal model to capture physically implementable voltage island partitions compatibilities in terms of voltage levels between the voltage island partitions that make up the netlist; b) executing a chip level floorplanning of the physically implementable voltage island partitions that were generated to place compatible physically implementable voltage island partitions in close proximity of each other; c) placing macros within a physically implementable voltage island partition while minimizing unused space within the voltage island partitions; d) extending the voltage island floorplanning to include the remainder of the chip; and e) performing a timing analysis to validate the extended floorplan, wherein said physically implementable voltage island partitions provide the chip with a floorplan that minimizes the power dissipated, and wherein said physically implementable voltage island partitions are provided by a graph model, said graph model being a Voltage Island Compatibility Graph (VICG) based on a complete undirected graph G(Π, A), said Π representing voltage island vertices in VICG, and A representing arcs of said VICG.