Patent ID: 7301194

Claim:
A nonvolatile memory cell comprising: an inverter comprising a first transistor formed in a first well region and a second transistor formed in a second well region, wherein an input of the inverter comprises a floating gate formed in a first polysilicon layer above the first well region and the second well region; a control gate for controlling charge on the input of the inverter, wherein the control gate is formed in a second polysilicon layer in a region between the first well region of the first transistor and the second well region of the second transistor, and wherein the first and second polysilicon layers are separated by an oxide layer, and the second polysilicon layer is above the first polysilicon layer; and a tunnel capacitor comprising a tunnel implant well and the floating gate, wherein the control gate overlaps the floating gate over an area occupied by the tunnel implant well of the tunnel capacitor to increase the coupling of the tunnel capacitor to the control gate.