Patent ID: 8451648

Claim:
A resistance-change memory comprising: first and second control lines; a memory element which is connected between the first and second control lines and in which its variable resistance state corresponds to data to be stored therein; a pulse generation circuit which generates a first pulse, a second pulse, a third pulse, and a fourth pulse, the first pulse having a first amplitude which changes the resistance state of the memory element from a high- to a low-resistance state, the second pulse having a second amplitude which changes the resistance state of the memory element from a low- to a high-resistance state, the third pulse having a third amplitude smaller than the first amplitude to read data in the memory element, the fourth pulse having a fourth amplitude between the first amplitude and the third amplitude; and a control circuit which controls the operations of the memory element and the pulse generation circuit, wherein the control circuit supplies the fourth pulse to the memory element after supplying the first pulse to the memory element.