Patent ID: 7468536

Claim:
A transistor comprising: a substrate; a plurality of transistor segments organized into a plurality of sections, each transistor segment having a length and a width, the transistor segments of each section being arranged in a side-by-side relationship along the width, the sections being arranged in rows and columns, the sections of each row being arranged such that section-to-section the length of the transistor segments is alternately aligned in first and second lateral directions, the first lateral direction being substantially orthogonal to the second lateral direction, each transistor segment including: a pillar of a semiconductor material, the pillar having a source region disposed at or near a top surface of the substrate; first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar; first and second field plates respectively disposed in the first and second dielectric regions; first and second gate members respectively disposed in the first and second dielectric regions at or near a top of the pillar; and a first metal layer that includes a source bus coupled to the source region of each transistor segment, and a gate bus coupled to the first and second gate members of each transistor segment.