Patent ID: 8705262

Claim:
A memory device comprising: a first surface including a first plurality of contact pads arranged in a pattern; a second surface including a second plurality of contact pads arranged in the pattern, wherein each contact pad of the second plurality of contact pads is electrically coupled to the corresponding contact pad using a via; wherein at least some of the first and the second plurality of contact pads are further coupled to data signals of the memory device for connection to a memory bus; wherein the memory device is configured to be stacked in vertical alignment and electrical connection upon a second memory device having a same pattern of contact pads as the memory device using a first orientation and a second orientation; wherein in response to the memory device being oriented in the first orientation, each data signal of the memory bus is shared between the memory device and the second memory device; and wherein in response to the memory device being oriented in the second orientation, each of the memory device and the second memory device has exclusive access to respective ones of the data signals of the memory bus.