Patent ID: 7937630

Claim:
A semiconductor memory having an operation mode externally settable, the memory comprising: a plurality of registers for holding operation mode information for the semiconductor memory; a register control circuit for updating the operation mode information for each of the plurality of registers on a time division basis at the time of detecting write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order; a command generation section for generating the write commands, the read commands, or a test start command by which write operation or read operation does not occur in response to a control signal externally inputted and for regenerating the test start command every update of the plurality of registers; and a data pad compression circuit for changing the operation mode information to be written to the plurality of registers by using test data inputted to part of data pads, after inverting the test data or in the test data's original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent.