Patent ID: 8129797

Claim:
Embedded DRAM MOSFETs comprising: an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD 1 ) upon which is deposited a TiN conductive layer, upon which is deposited a polysilicon layer (Poly); a logic PFET having a second gate stack comprising the high-K dielectric layer upon which is deposited the first metal oxide layer (CD 1 ) upon which is deposited the TiN conductive layer, upon which is deposited the polysilicon layer (Poly); and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the TiN conductive layer, upon which is deposited the polysilicon layer (Poly), without the first metal oxide layer (CD 1 ) between the high-K dielectric layer and the conductive TiN layer.