Patent ID: 7907446

Claim:
A semiconductor memory device comprising: a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction crossing the first direction; a plurality of cell blocks respectively including a plurality of memory cells provided to correspond to crosspoints in a form of a lattice constituted by the word lines and the bit lines; sense amplifiers provided to correspond to each of the bit lines, the sense amplifiers detecting data stored in the memory cells; bit line drivers connected to the bit lines; and word line drivers connected to the word lines, wherein in a first write sequence for writing data received from outside to a first cell block among the cell blocks, the word line drivers and the bit line drivers intermittently write the data to every other memory cell arranged in an extending direction of the word lines and an extending direction of the bit lines, respectively, in the first cell block, memory cells adjacent to a column direction or a row direction of the memory cells in which data is written are in an erased state, in a second write sequence for writing the data written in the first cell block to a second cell block among the cell blocks, the word line drivers and the bit line drivers write the data to all memory cells connected to word lines selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detect the data in the memory cells connected to the two word lines.