Patent ID: 7446592

Claim:
A compensation circuit for compensating for process, voltage and temperature (PVT) variations in an integrated circuit, the integrated circuit including a plurality of logic modules, the plurality of logic modules including a plurality of P-type metal oxide semiconductor (PMOS) transistors and a plurality of N-type metal oxide semiconductor (NMOS) transistors, the compensation circuit comprising: a first frequency generator including a set of PMOS transistors for generating a first digital signal; a first counter coupled to the first frequency generator for counting a number of pulses of the first digital signal in a clock cycle of a reference digital input signal, and generating a first calibration signal, wherein the first calibration signal is used to compensate for the PVT variations in the plurality of PMOS transistors; and a second functional module including a set of NMOS transistors for generating a second calibration signal, wherein the second calibration signal is used to compensate for the PVT variations in the plurality of NMOS transistors.