Patent ID: 7902012

Claim:
A method of preparing an inverter made of lateral channel field effect transistors comprising the steps of ( FIG. 6 ): forming a first transistor comprising the steps of: forming a silicon layer 31 on a first single crystalline substrate 30 , doping said silicon layer 31 p-type, forming strained Si 1-y C y epitaxial region 32 and 33 over said p-type silicon layer 31 , doping the above strained Si 1-y C y layer 32 , 33 n-type to a concentration level greater than 1E19 cm −3 , forming a thin silicon layer 34 over the above n-type strained Si 1-y C y epitaxial layer 32 , 33 , and p-type silicon 31 , forming a dielectric layer 50 serving as device isolation, forming a thin dielectric layer 35 over the above silicon layer 34 , forming a conducting layer 36 over the above dielectric layer 35 , forming a gate stack 888 comprising both the above dielectric layer 35 and the conducting layer 36 which overlaps the silicon layer 31 and the part of the strained Si 1-y C y 32 , 33 , forming a blanket dielectric layer 37 over and above the gate stack 888 , forming a dielectric layer 38 on the sidewall of the gate stack 888 , forming a second transistor comprising the steps of: forming a silicon layer 131 on a first single crystalline substrate 30 , doping said silicon layer 131 -n-type, forming compressively strained Si 1-x Ge x epitaxial region 132 and 133 in said p-type silicon layer 31 , doping the above strained Si 1-x Ge x layer 132 and 133 p-type to a concentration level greater than 1E19 cm −3 , forming a thin silicon or a compressively strained Si 1-w Ge w layer 134 over the above p-type strained Si 1-x Ge x epitaxial layer 132 , 133 and n-type silicon 131 , forming a thin dielectric layer 135 over the above layer 134 , and forming a conducting layer 136 over the above dielectric layer 135 , forming a gate stack comprising both the above dielectric layer 135 and the conducting layer 136 , which overlaps the silicon layer 131 part of region 132 , 133 .