Patent ID: 6933790

Claim:
A PLL circuit for receiving either one of first and second reference signals to generate a clock signal synchronized with one of the first and second reference signals, wherein the first reference signal is generated by superimposing a first wobble signal having a first cycle on a land pre-pit signal, and the second reference signal is generated from a second wobble signal having a second cycle shorter than the first cycle, the PLL circuit comprising: a voltage-controlled oscillator for generating the clock signal in accordance with control voltages; a first loop, connected to the voltage-controlled oscillator, for controlling at least one of a frequency and a phase of the clock signal in accordance with one of the first wobble signal and the second wobble signal; a second loop, connected to the voltage-controlled oscillator, for controlling at least one of the frequency and the phase of the clock signal in accordance with the land pre-pit signal, wherein the first and second loops are validated when the PLL circuit is provided with the first reference signal, and the first loop is validated and the second loop is invalidated when the PLL circuit is provided with the second reference signal.