Patent ID: 7272703

Claim:
An embedded-DRAM processor comprising: a DRAM array comprising a plurality of random access memory cells arranged in rows and columns; at least two register files, said register files each comprising a plurality of individually accessible registers, said registers being loadable in parallel via a parallel access port and being individually addressable via a second port; a data path comprising a mask and switch unit, said data path being capable of coupling at least a portion of a selected row of said DRAM array to the parallel access port corresponding to one of said register files; a set of functional units coupled to said register files and at least two of said functional units being able to individually and parallely access ones of said registers in response to respective first and second parallely executed instructions of a first set of instructions drawn from an instruction stream; and a data assembly unit responsive to a second set of instructions drawn from said instruction stream at least partly in response to a data assembly program, said second set of instructions comprising: a command to cause the contents of a selected subset of registers in a selected register file to be loaded in parallel from selected columns of a selected DRAM row; and a command to cause the contents of a selected subset of registers in a selected register file to be stored in parallel to selected columns of a selected DRAM row; whereby said data assembly unit applies a mask to said mask and switch unit in order to specify the selected subset of registers and the selected columns; and wherein said functional units collectively execute said first set of instructions at least partly in response to an operational program, and in parallel with the functional units, said data assembly unit executes said second set of instructions, and said data assembly unit is operative to cause data to be moved into and out of said register files in support of said functional units.