Patent ID: 7940132

Claim:
A clock system comprises: a phase locked loop (PLL) coupled to produce a number n of phase-offset output oscillations each having a first frequency f, wherein each of the n output oscillations has a different phase offset which is a multiple m of (2fn) −1 in which n is an integer greater than 1 and in which m is an integer which ranges from 0 to n−1; a phase divider coupled to generate a clock signal from a combination of more than one of the n phase-offset output oscillations based on a phase divider control signal, wherein said phase divider selects corresponding edge transition from each of said more than one of the n phase-offset output oscillations in which the clock signal has a second frequency which is different from the first frequency; and a control module coupled to generate the phase divider control signal based on a desired setting for the clock signal.