Patent ID: 8748227

Claim:
A method of fabricating a chip package, comprising: joining a top surface of a substrate and a bottom side of a die, wherein a first opening through said substrate is under said bottom side of said die, wherein said die comprises a first conductive layer, a second conductive layer and a passivation layer at said bottom side of said die, wherein a second opening in said passivation layer is under a first contact point of said first conductive layer, and said first contact point is at a top of said second opening, wherein said second conductive layer is coupled to said first contact point through said second opening, wherein said second conductive layer has a second contact point over said first opening; after said joining said top surface of said substrate and said bottom side of said die, forming a conductive interconnect coupled to said second contact point though said first opening; and after said joining said top surface of said substrate and said bottom side of said die, forming a molding material on a sidewall of said die and en-over said top surface of said substrate.