Patent ID: 8872272

Claim:
A method for fabricating a stress enhanced CMOS circuit comprising the steps of: forming a first plurality of MOS transistors at a first pitch, wherein forming the first plurality of MOS transistors comprises forming a first plurality of gate electrode structures and a first plurality of sidewall spacer structures disposed on vertical sidewalls of the first plurality of gate electrode structures; forming a second plurality of MOS transistors at a second pitch, wherein the second pitch is larger than the first pitch, wherein forming the second plurality of MOS transistors comprises forming a second plurality of gate electrode structures and a second plurality of sidewall spacer structures disposed on vertical sidewalls of the second plurality of gate electrode structures; and depositing a single stress liner overlying the first and second plurality of MOS transistors, including over the first plurality of gate electrode structures, the first plurality of sidewall spacer structures, the second plurality of gate electrode structures, and the second plurality of sidewall spacer structures, wherein the single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit, wherein: the single stress liner is either a tensile stress liner or a compressive stress liner, and further wherein: if the single stress liner is a tensile stress liner, then the first plurality of MOS transistors are all p-type transistors and the second plurality of MOS transistors are all n-type transistors, and if the single stress liner is a compressive stress liner, then the first plurality of MOS transistors are all n-type transistors and the second plurality of MOS transistors are all p-type transistors.