Patent ID: 7045391

Claim:
A manufacturing method of a multi-chips bumpless assembly package, comprising: providing a plurality of first chips with a first encapsulation encompassed, wherein the first chips have first bonding pads and the first bonding pads are exposed out of the first encapsulation; providing a patterned first dielectric layer with a plurality of first vias over the first chips and the first encapsulation, wherein the first bonding pads are exposed out of the patterned first dielectric layer through the first vias; providing a patterned first conductive layer located over the patterned first dielectric layer and connected to the first bonding pads through the first vias; providing an insulation layer located over the patterned first conductive layer and the patterned first dielectric layer; providing a plurality of second chips with a second encapsulation encompassed to be disposed on the insulation layer, wherein the second chips have second bonding pads and the second bonding pads are exposed out of the second encapsulation; forming a plurality of through holes, wherein the through holes penetrate the second encapsulation and the insulation layer and expose portions of the patterned first conductive layer; providing a conductive material filled in the through holes; disposing a conductive trace on the second chips and the second encapsulation, wherein the conductive trace connects the conductive material and one of the second bonding pads; providing a patterned second dielectric layer with a plurality of second vias over the second chips, the second encapsulation and the conductive trace, wherein portions of the second bonding pads are exposed out of the patterned second dielectric layer through the second vias; providing a patterned second conductive layer located above the second chips, the second encapsulation and the patterned second dielectric layer, wherein the patterned second conductive layer connects to the portions of the second bonding pads; providing a patterned third dielectric layer with a plurality of third vias over the patterned second conductive layer and the patterned second dielectric layer, wherein portions of the patterned second patterned conductive layer are exposed out of the patterned third dielectric layer through the third vias; and forming a plurality of bumps in the third vias, wherein the bumps are connected to the patterned second conductive layer.