Patent ID: 7259607

Claim:
An integrated semiconductor device, comprising: a clock generator circuit driven by an external clock signal that assumes an external clock level signal, wherein the clock generator circuit generates an internal clock signal with a first level in response to the external clock signal level lying above a sensitivity level of the clock generator circuit for at least the duration of a sensitivity time of the clock generator circuit, and generates the internal clock signal with a second level in response to the external clock signal level lying below the sensitivity level for at least the duration of the sensitivity time of the clock generator circuit, the clock generator circuit including a first clock circuit and a second clock circuit, the first clock circuit having a shorter sensitivity time than the second clock circuit; and a control circuit driven by an external control signal and controlling the clock generator circuit such that the control circuit selects the sensitivity time of the clock generator circuit in response to the state of the external control signal, wherein the clock generator circuit generates the internal clock signal via one of the first and second clock circuits in dependence on the sensitivity time selected by the control circuit.