Patent ID: 8059423

Claim:
A printed circuit board comprising: a first dielectric layer having a first surface and an opposite second surface; a first conductive layer coupled to the first surface of the first dielectric layer; a second conductive layer coupled to the second surface of the first dielectric layer; and a localized distributive non-discrete capacitive element adjacent the first conductive layer, the localized distributive non-discrete capacitive element comprising: a first conductive element defined by an area of the first conductive layer; a second conductive element located in the exterior area below the device, the second conductive element defined by an isolation gap on the first conductive layer, the second conductive element separate but adjacent to the first conductive element and electrically isolated from the first conductive layer; a dielectric element positioned over the first conductive element; a third conductive element positioned over the dielectric element and shaped as the perimeter band, the third conductive element extending across the isolation gap,-coupled to the second conductive element and surrounding ball grid array anti-pad pattern for the device to be decoupled; and one or more electrically conductive vias coupling the second conductive element and the second conductive layer; and wherein the capacitive element is defined by a perimeter band that surrounds and approximately coincides with an outer perimeter for a device to be decoupled by the localized distributive non-discrete capacitive element, the perimeter band defining an interior open area, traversing the thickness of the printed circuit board, and an exterior area located opposite the interior open area, the interior open area devoid of any capacitive elements.