Patent ID: 8160828

Claim:
A computer-implemented method of verifying design validity of an electronic circuit board on which a semiconductor device is mounted, the computer-implemented method comprising: obtaining a reflected voltage at the semiconductor device with respect to a voltage inputted to the semiconductor device from the electronic circuit board side; and making a judgment as to whether or not the reflected voltage is within a tolerance range of power supply variation that assures operation of the semiconductor device to perform verification of design validity, wherein, assuming that n (n is a prescribed positive integer) semiconductor devices are mounted on the electronic circuit board, a voltage Vin[i] inputted to the semiconductor device from the electronic circuit board is given by Vin [ i ]= VDD−Zlsi [ i ]× VDD /( Zlsi [ i ]+ Z 11[ i ]) where Zlsi[i] is an input impedance characteristic of an i-th (i=1 to n) of the semiconductor devices, Z 11 [i] is a reflected impedance characteristic which is viewed from a position at which the i-th semiconductor device is mounted and which is a characteristic with the i-th semiconductor device omitted from the electronic circuit board, and VDD is a power supply voltage; and the reflected voltage Vr[i] is obtained from Vr [ i ]= V in[ i ]×( Zlsi [ i ]+ Z 11[i])/( Zlsi [ i ]− Z 11[i]); and a judgment is made as to whether or not a condition that an absolute value |Vr[i]| of the reflected voltage Vr[i] is less than or equal to a power supply variation tolerance range ΔV, | Vr [ i ]|≦Δ V is satisfied.