Patent ID: 8797304

Claim:
A display device comprising: a pixel portion including at least a first region and a second region; a first gate driver; a second gate driver; a first source driver; and a second source driver, wherein the first region comprises a plurality of first pixels, each of the plurality of first pixels comprising: a first display portion comprising a first transistor, a first capacitor element and a first display element; and a first reading portion comprising a second transistor and a first photoelectric conversion element, wherein the second region comprises a plurality of second pixels, each of the plurality of second pixels comprising: a second display portion comprising a third transistor, a second capacitor element and a second display element; and a second reading portion comprising a fourth transistor and a second photoelectric conversion element, wherein the first gate driver is electrically connected to a gate of the first transistor and a gate of the third transistor, wherein the second gate driver is electrically connected to the gate of the first transistor and the gate of the third transistor, wherein the first source driver is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, wherein the second source driver is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor element and the first display element, wherein the other of the source and the drain of the third transistor is electrically connected to the second capacitor element and the second display element, wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the third transistor, wherein the gate of the second transistor is electrically connected to the first photoelectric conversion element, and wherein the gate of the fourth transistor is electrically connected to the second photoelectric conversion element.