Patent ID: 8183149

Claim:
A method of fabricating a semiconductor device having transistor devices formed on a semiconductor substrate, and having an upper metal layer that provides electrical contacts for the transistor devices, the method comprising: forming a diffusion barrier layer overlying the upper metal layer; depositing a lower layer of graded material overlying the diffusion barrier layer by transitioning from a first chemical precursor gas flow to a second chemical precursor gas flow in a common deposition chamber; depositing a layer of dielectric material overlying the lower layer of graded material by using the second chemical precursor gas flow in the common deposition chamber; and depositing an upper layer of graded material overlying the layer of dielectric material by terminating the second chemical precursor gas flow in the common deposition chamber in a transient manner, depositing the lower layer of graded material, depositing the layer of dielectric material, and depositing the upper layer of graded material being performed in-situ within the common deposition chamber.