Patent ID: 8395204

Claim:
A power semiconductor device, comprising: an element unit comprising a vertical-type MOSFET, the vertical-type MOSFET comprising, a first semiconductor layer with a first conductivity type, a second semiconductor layer with the first conductivity type provided on a first main surface of the first semiconductor layer, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, a third semiconductor layer with a second conductivity type provided on a surface of the second semiconductor layer, a fourth semiconductor layer with a first conductivity type selectively provided on a surface of the third semiconductor layer, a fifth semiconductor layer with the second conductivity type selectively provided on the surface of the third semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, each trench penetrating the third semiconductor layer from a surface of the fourth semiconductor layer or a surface of the fifth semiconductor layer reaching the second semiconductor layer, the adjacent trenches being provided with a first interval in between, a first embedded conductive layer embedded at a bottom of the trench via the insulator, a second embedded conductive layer embedded at an upper portion of the first embedded conductive layer via the insulator, an interlayer insulator provided on the second embedded conductive layer, a first main electrode provided on a second main surface of the first semiconductor layer opposed to the first main surface, the first main electrode electrically connecting to the first semiconductor layer, a second main electrode provided on the a fourth semiconductor layer, the fifth semiconductor layer and the interlayer insulator, the second main electrode electrically connecting to the fourth semiconductor layer and the fifth semiconductor layer; and a diode unit adjacent to the element unit comprising, the first semiconductor layer, the second insulator semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, the insulator covering the inner surfaces of the plurality of the trenches, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval, the first embedded conductive layer, the second embedded conductive layer, the interlayer insulator, the first main electrode, and the second main electrode.