Patent ID: 7557414

Claim:
A semiconductor device, comprising: a semiconductor substrate; an element isolation; a first MIS transistor on the semiconductor substrate; and an insulating film which has tensile stress and which is formed on the semiconductor substrate so as to cover the first MIS transistor, wherein the first MIS transistor includes: a p-type semiconductor layer defined by the element isolation in the semiconductor substrate; a first gate insulating film formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulating film, the first gate electrode having a first portion disposed on the p-type semiconductor layer and a second portion disposed on the element isolation so as to lie astride the p-type semiconductor layer; a first sidewall insulating film formed at each side face of the second portion of the first gate electrode on the element isolation and including at least a first sidewall; an n-type extension diffusion layer formed outwards from the first portion of the first gate electrode in the p-type semiconductor layer; and an n-type impurity diffusion layer formed in a region of the p-type semiconductor layer which is adjacent to the n-type extension diffusion layer, wherein the first sidewall insulating film is not formed at each side face of the first portion of the first gate electrode on the p-type semiconductor layer.