Patent ID: 7822955

Claim:
A data processing apparatus, comprising: a data processing unit for executing a sequence of instructions for performing at least one arithmetic operation and at least one logical operation; a plurality of registers for storing data words for access by the data processing unit when executing said sequence of instructions; the data processing unit, responsive to an endian reverse instruction within said sequence specifying a source register and a destination register in said plurality of registers, for applying an endian reverse operation to an input data word Rm stored in said source register, the input data word comprising a plurality of data values, wherein said endian reverse operation yields a result data word Rd for storing in said destination register, the result data word given by: treating the input data word as consisting of a plurality of input sections, the result data word having a corresponding plurality of result sections, at least one input section comprising a plurality of data values; and for at least one of the input sections comprising a plurality of data values, performing an independent swap operation on the data values within that input section to form the result data word Rd in which the corresponding result section has its data values swapped with respect to that input section.