Patent ID: 6888410

Claim:
A power amplifier having low gate oxide stress, the power amplifier comprises: input transistor having a gate, a drain, and a source, wherein the source of the input transistor is coupled to a supply voltage return and the gate of the input transistor operably coupled to receive an outbound radio frequency (RF) signal; input bias circuit operably coupled to provide an enabling bias voltage to the gate of the input transistor during transmit mode and to provide a disabling bias voltage to the gate of the input transistor during power down mode; output transistor having a gate, a drain, and a source, wherein the drain of the output transistor is coupled to provide an output of the power amplifier, the source of the output transistor is coupled to the drain of the input transistor; and power down circuit operably coupled to provide an output enabling bias voltage to the gate of the output transistor during the transmit mode and to provide an output disabling bias voltage to the gate of the output transistor during the power down mode, wherein the output disabling bias voltage is of a value to distribute gate oxide stress between the input transistor and the output transistor.