Patent ID: 7094694

Claim:
A method for manufacturing a semiconductor device, comprising: forming a gate electrode on a first region of a semiconductor substrate; forming a silicide blocking layer on the substrate and the gate electrode; partially removing the silicide blocking layer to form a first gate spacer on sidewalls of the gate electrode on the first region and a silicide blocking layer pattern on a second region; implanting dopants lightly into the substrate using the silicide blocking layer, the gate electrode, and the first gate spacer as a first implantation mask to form a lightly doped source/drain region on the first region; forming a second gate spacer on sidewalls of the first gate spacer; implanting dopants heavily into the substrate using the silicide blocking layer, the gate electrode, the first gate spacer, and the second gate spacer as a second implantation mask to form a heavily doped source/drain region on the first region; and forming a silicide layer on the gate electrode and the heavily doped source/drain region in the first region.