Patent ID: 7237140

Claim:
A fault tolerant computing system comprising: a plurality of processing nodes interconnected by a communication channel, each of said processing nodes having an identical application program; control means for respectively setting said processing nodes in uniquely different configurations and operating said processing nodes in parallel to execute the application programs in environments corresponding to said uniquely different configurations; and distributing means for distributing request messages respectively to said processing nodes, so that said request messages are individually processed by said application programs to produce a plurality of response messages, wherein the configurations of said processing nodes are sufficiently different from each other that software faults are not simultaneously activated by said processing nodes, wherein each of said configurations comprises hardware configuration, software configuration, external device configuration and program startup configuration, and wherein said hardware configuration data includes parameters indicating main memory size, virtual memory size, memory access timing, processor operating speed, bus transmission speed, bus width, number of processors, read cache memory size, write cache memory size, cache's valid/invalid status, and types of processors and memories, and wherein each of said processing nodes differs from every other processing nodes in one of said parameters of hardware configuration data.