Patent ID: 8575652

Claim:
A semiconductor device comprising: a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate insulator formed on a surface of the channel region; a gate electrode formed on the gate insulator; source/drain diffusion layers formed on both sides of the channel region, the source/drain diffusion layers being made of semiconductor including Boron (B) as an impurity and a concentration of B in the source/drain diffusion layers being more than 10 20 /cm 3 ; an n-type semiconductor region in the semiconductor substrate containing Ge; and an element containing region containing S, the element containing region being formed in the semiconductor region and the element containing region being deeper than a junction depth of the source/drain diffusion layers, wherein the channel region, the gate insulator, the gate electrode and the source/drain diffusion layers forms a p-MISFET, at least part of both of the source/drain diffusion layers are formed in the semiconductor region, pn junctions are formed between the source/drain diffusion layers and the element containing region, a concentration of S is not more than 1×10 19 atoms/cm 3 in at least part of the channel region located immediately below the gate insulator, a concentration of S is not lower than 1×10 16 atoms/cm 3 in the element containing region, the channel region contains Ge, and a Ge concentration of the n-type semiconductor region is not lower than 87 atomic percent.