Patent ID: 8238142

Claim:
A semiconductor device including a static type memory cells having first and second load transistors, first and second drive transistors, first and second access transistors and first and second transistors, comprising: first to fifth impurity regions of a first conductive type in a first well of a second conductive type, sixth to tenth impurity regions of the first conductive type in a second well of the second conductive type; eleventh to fourteenth impurity regions of the second conductive type in a third well of the first conductive type, wherein the third well is arranged between the first and second wells; a first gate layer having a first portion arranged over a portion between the first and second impurity regions to provide the first drive transistor, and a second portion arranged over a portion between the eleventh and twelfth impurity regions to provide the first load transistor, wherein the first gate layer is shared for gate electrodes of the first drive transistor and the first load transistor; a second gate layer having a third portion arranged over a portion between the sixth and seventh impurity regions to provide the second drive transistor, a fourth portion arranged over a portion between the thirteenth and fourteenth impurity regions to provide the second load transistor, and a fifth portion arranged over a portion between eighth and ninth impurity regions to provide the first transistor, wherein the second gate layer is shared for gate electrodes of the second drive transistor, the second load transistor and the first transistor; a third gate layer having a sixth portion arranged over a portion between the second and third impurity regions to provide the first access transistor, and a seventh portion arranged over a portion between fourth and fifth impurity regions to provide the second access transistor, wherein the third gate layer is shared for gate electrodes of the first and second access transistors; a fourth gate layer having a eighth portion arranged over a portion between the ninth and tenth impurity regions to provide the second transistor, the fourth gate layer functioning as a gate electrode of the second transistor; an electrical connection of the first gate layer to the fifth and thirteenth impurity regions; an electrical connection of the second gate layer to the eleventh impurity region; an electrical connection of the eleventh impurity region to the second impurity region to provide a first storage node of the static type memory cell; an electrical connection of the thirteenth impurity region to the seventh impurity region to provide a second storage node of the static type memory cell; a first word line electrically connected to the third gate layer; a second word line electrically connected to the fourth gate electrode; a first bit line electrically connected to the third impurity region; a second bit line electrically connected to the fourth impurity region, and a third bit line electrically connected to the tenth impurity region.