Patent ID: 7424416

Claim:
A system comprising: a simulation node configured to simulate a first portion of a system under test in a series of simulation timesteps, wherein each simulation timestep includes a zero time phase simulation and real time phase simulation, wherein during the zero time phase simulation, a state of a simulation of the first portion of the system under test is frozen while input signals of the simulation of the first portion are changed and output signals of the simulation of the first portion are sampled, and wherein during the real time phase simulation, the state of the simulation of the first portion of the system under test is iteratively changed in response to sampling output signals of the simulation of the first portion and driving input signals of the simulation of the first portion, and wherein the simulation node is configured to generate a first completion message in response to completing the zero time phase simulation; a hardware emulation node comprising a field programmable gate array (FPGA) device configured to emulate a second portion of the system under test in a series of emulation timesteps, wherein each emulation timestep includes a zero time phase emulation and real time phase emulation, wherein during the zero time phase emulation, a state of an emulation of the second portion of the system under test is frozen while input signals of the emulation of the second portion are changed and output signals of the emulation of the second portion are sampled, and wherein during the real time phase emulation, the state of the emulation of the second portion of the system under test is iteratively changed in response to sampling output signals of the emulation of the second portion and driving input signals of the emulation of the second portion, and wherein the emulation node is configured to generate a second completion message in response to completing the zero time phase emulation; and a control node configured to cause the simulation node to initiate the real time phase simulation in response to receiving both the first completion message and the second completion message, and wherein the control node is further configured to cause the hardware emulation node to initiate the real time phase emulation in response to receiving both the first completion message and the second completion message.