Patent ID: 8661227

Claim:
A processor, comprising: an instruction fetch unit; an issue queue coupled to the instruction fetch unit that receives instructions dispatched from the instruction fetch unit; an execution unit, coupled to the issue queue, that executes instructions issued from the issue queue, wherein the instructions executed by the execution unit reference a plurality of architected logical registers; a multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency, wherein each of the first and second level register files individually includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of hardware threads; and a mapper including: a first data structure including a plurality of entries each assigning an identifier of a physical register in the first-level register file to a respective one of a plurality of instructions undergoing execution, wherein the first data structure is a shared data structure concurrently containing entries for instructions in multiple of the plurality of hardware threads; and a second data structure that records variable assignments between the plurality of architected logical registers and physical registers in the first level register file; wherein the mapper, at dispatch from the instruction fetch unit to the issue queue of an instruction specifying a source logical register among the plurality of architected logical registers, initiates a swap of a first operand that is associated with the source logical register and that is in the second level register file with a second operand held in the first level register file and updates the second data structure accordingly; wherein the issue queue, in response to a signal from the mapper indicating the first operand is present in the first level register file, issues the instruction to the execution unit for execution.