Patent ID: 7759992

Claim:
A clock distribution circuit, comprising: a drive power boost signal generator which outputs a drive power boost signal; and a current mode logic (CML) circuit which outputs a first signal combined with a second signal when the drive power boost signal indicates an active state and outputs the first signal when the drive power boost signal indicates an inactive state, wherein the CML circuit comprises: a normal operation circuit which outputs the first signal according to an input signal regardless of a state which the drive power boost signal indicates; and a boost circuit which outputs the second signal according to the input signal when the drive power boost signal indicates the active state but does not output the second signal when the drive power boost signal indicates the inactive state, and wherein: the drive power boost signal generator outputs a drive power boost signal indicating an active state for a period after the normal operation circuit changes to an operation state from a stop state, and outputs a drive power boost signal indicating an inactive state after the period.