Patent ID: 8441416

Claim:
An active matrix electroluminescent display apparatus comprising: first and second electroluminescent devices; a first transistor connected to the first electroluminescent device; a second transistor positioned adjacent to the first transistor and connected to the second electroluminescent device; a first data line; a second data line; a third transistor electrically connected to the first transistor and the first data line; a fourth transistor electrically connected to the second transistor and the second data line; first and second substantially parallel power lines positioned adjacent to one another between the first and second transistors to substantially prevent a short-circuit between the power lines and the first and second data lines, wherein the first power line is configured to provide current to the first electroluminescent device through the first transistor and the second power line is configured to provide current to the second electroluminescent device through the second transistor; a first capacitor connected to the first transistor and to the first power line, wherein the first capacitor comprises first and second electrodes, and wherein a first protrusion from the first power line toward the first data line forms the first electrode of the first capacitor and overlaps the second electrode of the first capacitor, wherein the second electrode of the first capacitor overlaps the first power line only at the first protrusion; and a second capacitor connected to the second transistor and to the second power line, wherein the second capacitor comprises first and second electrodes, and wherein a second protrusion from the second power line toward the second data line forms the first electrode of the second capacitor and overlaps the second electrode of the second capacitor, wherein the second electrode of the second capacitor overlaps the second power line only at the second protrusion, wherein the first data line is positioned opposite to a side of the first transistor where the first power line is positioned, and the second data line is positioned opposite to a side of the second transistor where the second power line is positioned.