Patent ID: 7136068

Claim:
A computer system, comprising: a bus; a central processing unit coupled to said bus; and a graphics accelerator coupled to said bus, said graphics accelerator including a texture cache system, said texture cache system including a texture cache memory that stores texels to be used by a texel value generating circuit, a cache controller that performs a replacement policy determination for texel data to be stored in said texture cache memory, and a direct memory access engine that retrieves texel data from memory, wherein said cache controller includes a first set of flags and a second set of flags, each of the first set of flags and the second set of flaps having a bit position for each of a plurality of cache lines in the cache memory, wherein the cache controller is configured to set a bit position in the first set of flags for each cache line that will be used to render a first triangle, wherein the cache controller is further configured to set a bit position in the second set of flags for each cache line that will be used to render a second triangle, and wherein the cache controller is configured to only replace texels in cache lines for which neither the bit position associated with the first set of flags nor the bit position associated with the second set of flags has been set.