Patent ID: 7847385

Claim:
A stacked die structure comprising: a lower die having: a semiconductor material; a number of contact regions formed in the semiconductor material; and a metal interconnect structure that touches the semiconductor material and the contact regions to define an electrical circuit, the metal interconnect structure having a non-conductive region, a number of copper lines, and a number of copper pads, the non-conductive region having a top surface, the copper pads and copper lines touching the top surface of the non-conductive region, the number of copper lines having a number of top surfaces, the number of copper lines and the number of copper pads having top surfaces that lie substantially in a common horizontal plane; a non-conductive layer that touches the top surface of the non-conductive region and the top surfaces of the copper lines, the non-conductive layer lying laterally between and touching adjacent copper lines, no portion of the non-conductive layer lying over a copper pad of the number of copper pads; and an upper die attached to the non-conductive layer.