Patent ID: 8593205

Claim:
An output buffer circuit comprising: a first output circuit that outputs a first signal having a voltage level of a first high potential power supply or a low potential power supply, wherein the first output circuit includes a first output transistor at a high potential side, and the first output transistor includes a gate and a back gate; a second output circuit that outputs a second signal having a voltage level of a second high potential power supply, which is lower than the first high potential power supply, or the low potential power supply, wherein an output terminal of the second output circuit is coupled to an output terminal of the first output circuit and includes a second output transistor at a high potential side, and the second output transistor includes a gate and a back gate; and a control circuit that sets the gate and back gate of at least one of the first output transistor and the second output transistor to the voltage level of the second high potential power supply when the first high potential power supply is deactivated and the second high potential power supply is activated.