Patent ID: 6918011

Claim:
A cache memory comprising: a data memory for storing pieces of cached data in a plurality of data blocks respectively; a tag memory for storing both address information specifying an address of a main memory corresponding to an address of each data block of the data memory and valid information indicating validity of the cache data of the data block of the data memory in a tag block of an address; an area specifying unit for storing area information specifying an invalidating area of the main memory; a judging unit for receiving the pieces of address information read out from all tag blocks of the tag memory one after another, and judging according to the pieces of address information and the area information stored by the area specifying unit whether or not each data block of the data memory corresponds to the invalidating area of the main memory; and an access control unit for controlling the tag memory to replace the valid information, which is stored in a specific tag block of the tag memory corresponding to a specific data block of the data memory, with valid information indicating invalidity in a case where the judging unit judges that the specific data block of the data memory corresponds to the invalidating area of the main memory.