Patent ID: 8203562

Claim:
An integrated circuit, comprising: a three-dimensional graphics processor having a first level of precision, the three-dimensional graphics processor: being a first preferred processor for performing graphics processing operations; including dedicated graphics hardware for at least a first subset of the graphics processing operations; and having a limited capability to perform one or more moving picture expert group (MPEG) operations; a programmable video processor having a second level of precision less than the first level of precision, the programmable video processor: being a second preferred processor for performing video processing operations including the one or more MPEG operations; and configured to perform one or more of a second subset of the graphics processing operations not requiring the dedicated graphics hardware; a host interface to receive instructions from a host; a scheduler to schedule operations on the three-dimensional graphics processor and the programmable video processor; in a default first mode of operation, the scheduler preferentially assigning the second subset of the graphics processing operations to the three-dimensional graphics processor and the one or more MPEG operations to the programmable video processor; the scheduler having: a second mode of operation in which it assigns at least one of the second subset of the graphics processing operations to the programmable video processor; and a third mode of operation in which it assigns the one or more MPEG operations to the three-dimensional graphics processor.