Patent ID: 7295481

Claim:
A method for accessing memory cells within a memory array operated with a precharge mechanism, in which differential read and write access operations are performed by activating a true bitline and a complement bitline, the method comprising: combining a first precharge control signal with a read cycle (n+1) control signal to determine whether a next memory access operation occurring in a clock cycle subsequent to an access operation occurring in a current clock cycle is a read access operation or a write access operation wherein the read cycle (n+1) control signal is asserted according to an operating mode of the memory array, such that a write access operation occurring over a plurality of system clock cycles results in a continuous assertion of the next read cycle (n+1) control signal until the write access operation is complete; and performing a precharge of the true and complement bitlines only when a read access operation follows the access operation occurring in the current clock cycle.