Patent ID: 8134487

Claim:
An asynchronous analog to digital convertor for converting an analog input signal into a digital output, the analog to digital convertor comprising: a clock input operable to receive an external clock signal having a clock period; a comparator operable to compare the analog input signal to a reference signal; a digital to analog converter operable to generate the reference signal corresponding to a state of a successive approximation register; and a control block connected to the comparator and to the digital to analog converter, wherein the control block is operable to generate and receive a sequence of control signals according to a successive approximation algorithm, to perform a plurality of comparisons, and to update the state of the successive approximation register thereby generating the digital output, wherein the control block comprises a plurality of identical bit-slices connected in a chain, the chain comprising a most significant bit slice (MSB-slice) and a least significant bit-slice (LSB-slice) that are interconnected by a plurality of intermediate bit-slices, wherein the bit-slices are arranged to be activated one after the other, and wherein the MSB-slice is arranged to be activated by the external clock signal, and the LSB-slice and intermediate bit-slices are arranged to be activated by a previous bit-slice; each bit-slice comprises a state machine arranged to control the comparator to compare the analog input signal to the reference voltage, and to store the result of the comparison as a bit value in the successive approximation register, wherein each bit-slice is arranged to set the next bit of the successive approximation register and to activate the next bit-slice; and each bit-slice comprises dynamic logic with parasitic capacitors arranged for storing each state of the state machine, wherein the dynamic logic is controlled by asynchronous signals.