Patent ID: 7145383

Claim:
A semiconductor integrated circuit device, comprising: a circuit block including a first MOS transistor; a second MOS transistor; and a third MOS transistor, a drive power of the second MOS transistor being smaller than a drive power of the third MOS transistor, wherein source-drain paths of the each of the second MOS transistor and the third MOS transistor are provided between a node to which a supply voltage of the circuit block is supplied and a power supply line of the circuit block; wherein the second and third MOS transistors are controlled to be in an ON state in a first state and the second and the third MOS transistors are controlled to be in an OFF state in a second state; and wherein in a transition state from the second state to the first state, the second MOS transistor is controlled to be in the ON state before the third MOS transistor starts to be controlled to become the ON state.