Patent ID: 8466013

Claim:
A method for manufacturing a semiconductor structure, comprising: a) providing an SOI substrate, and forming a gate structure ( 200 ) on the SOI substrate; b) etching an SOI layer ( 100 ) and a BOX layer ( 110 ) of the SOI substrate on both sides of the gate structure ( 200 ) to form trenches ( 140 ) which expose the BOX layer ( 110 ) and partially extend into the BOX layer ( 110 ); c) forming metal sidewall spacers ( 160 ) on sidewalls of the trenches ( 140 ), wherein the metal sidewall spacers ( 160 ) are in contact with the SOI layer ( 100 ) under the gate structure ( 200 ); d) forming an insulating layer ( 150 ) to partially fill the trenches ( 140 ), and forming a dielectric layer ( 300 ) to cover the gate structure ( 200 ) and the insulating layer ( 150 ); e) etching the dielectric layer ( 300 ) to form first contact through holes ( 310 ) which at least partially expose the insulating layer ( 150 ), and etching the insulating layer ( 150 ) from the first contact through holes ( 310 ) to form second contact through holes ( 320 ) which at least partially expose the metal sidewall spacer ( 160 ); and f) filling the first contact through holes ( 310 ) and the second contact through holes ( 320 ) to form contact vias ( 330 ), which are in contact with the metal sidewall spacers ( 160 ).