Patent ID: 7180331

Claim:
An apparatus having an input mode and coupled between first and second supply potentials, the apparatus comprising: an input/output node to receive an input signal; a PMOS pull-up transistor having gate, source, drain and body terminals, and fabricated in an nwell, the source terminal coupled to the first supply potential and the drain terminal coupled to the input/output node; an NMOS pull-down transistor having source and drain terminals, the source terminal coupled to the second supply potential and the drain terminal coupled to the input/output node; a gate bias control transistor having gate, source, and drain terminals, the source terminal coupled to the input node, the drain coupled to the gate of the PMOS pull-up transistor, and the gate terminal coupled to the first supply potential and configured to couple the gate of the PMOS pull-up transistor to the input/output node an response to the input signal having a potential greater than approximately the first supply potential; a passgate having an NMOS passgate transistor and a PMOS passgate transistor, the NMOS passgate transistor and the PMOS passgate transistor each having source and drain terminals, the source terminals of each passgate transistor coupled to each other and to a circuit node with a potential configured to be approximately equal to the first supply potential during the input mode, and the drain terminals coupled to each other and to the gate of the PMOS pull-up transistor and configured to couple the gate of the PMOS pull-up transistor to the first supply potential in response to the input signal having a potential approximately equal to or less than the first supply potential; and a well bias control circuit having an nwell terminal coupled to the nwell of the PMOS pull-up transistor and to a well drive transistor coupled between the first supply potential and the nwell terminal, the well drive transistor configured to couple the nwell terminal to the first supply potential in response to the input signal having a potential approximately equal to or less than the first supply potential, the well bias control circuit further comprising a gate pull-up transistor coupled between the input/output node and the gate terminal of the PMOS passgate transistor.