Patent ID: 7353364

Claim:
A processor, comprising: instruction fetch logic configured to issue instructions; a first functional unit configured to execute instructions issued from said instruction fetch logic; and a second functional unit configured to execute operations in response to instructions issued by said instruction fetch logic without receiving and decoding instructions corresponding to said operations from said instruction fetch logic, wherein said operations execute asynchronously with respect to instructions issued from said instruction fetch logic; wherein during the course of executing at least one of said operations, said second functional unit is further configured to issue one or more additional operations to said first functional unit for execution, wherein said one or more additional operations are issued asynchronously with respect to said instructions issued to said first functional unit, and wherein no program counter value visible by said instruction fetch logic is associated with said one or more operations issued to said first functional unit by said second functional unit; wherein said second functional unit is configured to provide one or more operands corresponding to a given one of said one or more additional operations to said first functional unit; wherein said first functional unit comprises temporary result storage configured to store a result of said given additional operation while said first functional unit executes a given instruction issued from said instruction fetch logic; and wherein said first functional unit is further configured to use said stored result as an operand of an operation issued subsequently to said given additional operation.