Patent ID: 8874933

Claim:
A microprocessor, comprising: an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA1 states including a first SHA1 state, a second SHA1 state, a third SHA1 state, and a fourth SHA1 state, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state; and an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the four SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand, wherein the first storage location stores SHA1 states A, B, C, and D corresponding to the first SHA1 state, the second SHA1 state, the third SHA1 state, and the fourth SHA1 state, respectively, wherein the fifth SHA1 state is SHA1 state E, wherein a result of the at least four rounds of SHA1 round operations is stored in the first storage location indicated by the first operand, and wherein the result represents new SHA1 states A, B, C, and D as inputs for a next round of SHA1 round operations.