Patent ID: 7653677

Claim:
A digital logic circuit, comprising: at least one stage, each stage of said at least one stage including: sum logic configured to generate a first sum signal from a first set of three input signals that includes a bit from each of three words; combinatorial logic having a carry generation portion configured to generate a first carry signal from a second set of three input signals and a sum generation portion configured to generate a second sum signal from said first sum signal and said first carry signal, said second set of three input signals including a less significant bit from each word of said three words than said first set of three input signals; and carry chain logic configured to process said first sum signal, said second sum signal, and a carry-in signal to generate a carry-out signal and a third sum signal, wherein said carry generation portion of said combinatorial logic comprises: a first AND gate having a first pair of input terminals configured to receive a first pair of signals in said second set of three input signals and a first output terminal; a second AND gate having a second pair of input terminals configured to receive a second pair of signals in said second set of three input signals and a second output terminal; a third AND gate having a third pair of input terminals configured to receive a third pair of signals in said second set of three input signals and a third output terminal; and an OR gate having three input terminals respectively coupled to said first output terminal, said second output terminal, and said third output terminal, said OR gate including a fourth output terminal for providing said first carry signal.