Patent ID: 8324057

Claim:
A method for making a microelectronic device with at least one symmetrical double-gate transistor, and at least one asymmetrical double-gate transistor, the method comprising: forming plural structures on a substrate including at least a first gate block configured to form a first gate of a double-gate transistor, and at least a second gate block configured to form the second gate of the double-gate transistor, the first gate block and the second gate block being located on opposite sides of at least one semiconducting area and separated from the semiconducting area by a first gate dielectric zone and a second gate dielectric zone respectively; doping at least one or plural semiconducting zones of the second gate block of at least one given structure for the at least one asymmetrical double-gate transistor among the structures, using at least a first implantation selective relative to the first gate block, the first implantation being done at a non-zero angle from a normal to a principal plane of the substrate passing through the semiconducting area, the first gate block not being implanted; protecting at least one particular structure for the at least one symmetrical double-gate transistor among the structures formed in the forming during the doping by at least one protection layer; forming the at least one symmetrical double-gate transistor at the at least one particular structure for the at least one symmetrical double-gate transistor; and forming the at least one asymmetrical double-gate transistor at the at least one give structure for the at least one asymmetrical double-gate transistor.