Patent ID: 8769511

Claim:
A target platform including a CPU comprising: a virtual machine monitor configured to monitor execution frequency on the CPU of an anchor node targeted by a back branching control node and to record next executed virtual machine code instructions corresponding to a linear instruction sequence of a selected cycle when execution of the anchor node exceeds a predetermined frequency, the linear instruction sequence traversing a portion of a loop from the anchor node to the back branching control node targeting the anchor node, the loop including a method call and at least one conditional branching instruction between the anchor node and the back branching control node targeting the anchor node, and the linear instruction sequence including only an executed portion of a method invoked using the method call; a compiler, cooperating with the virtual machine monitor, configured to compile the virtual machine code instructions for the next executed virtual machine code instructions corresponding to the linear instruction sequence of the selected cycle into a compiled code segment of native machine code executable on the target platform, and without compiling unexecuted portions of the method invoked using the method call; and wherein the virtual machine monitor is further configured to cause execution of the compiled code segment of native machine code on the CPU in lieu of further execution of the virtual machine code corresponding to the linear instruction sequence of the selected cycle.