Patent ID: 8877547

Claim:
A method of fabricating a thin film transistor, comprising: forming a gate electrode on a substrate; depositing a gate insulating layer on the gate electrode and the substrate at a temperature of equal to or less than 200° C.; forming source and drain electrodes on the gate insulating layer spaced apart from each other by depositing indium-tin-oxide (ITO) on the gate insulating layer at a temperature less than 200° C., the source and drain electrodes including source and drain layers formed of the ITO doped with at least one Group III element; forming smooth surfaces of the source and drain layers by heat-treating the source and drain electrodes at a temperature of less than 200° C.; and after the step of forming the smooth surfaces of the source and drain layers, forming an organic semiconductor layer on the gate insulating layer to contact the source and drain layers that are formed of the ITO doped with at least one Group III element and have the smooth surfaces, wherein an upper surface of the gate insulating layer is even so that the source and drain electrodes do not have steps in a cross section but are smooth and even, wherein the forming of the organic semiconductor layer includes evaporating the organic semiconductor layer at a temperature of less than 200° C. and depositing the evaporated organic semiconductor material on the substrate having the source and drain electrodes by using a shadow mask, and wherein the heat treating of the source and drain electrodes is performed to recover and smooth at least one roughened doped ITO surface of the source and drain electrodes from the depositing of the ITO.