Patent ID: 6862707

Claim:
A turbo code encoder for encoding at least one input set of N ordered permutation integers I(k), where k=1 to N, comprising: a first encoder with memory size m, having a first input, coupled to a first source and a common source, and a multi-state register having 2 m states, for receiving said input bit set as said first source and encoding said input bit set to provide an encoded input bit set at a first output; a hybrid S-random interleaver for receiving said input bit set and reordering the bits within said input bit set to provide a reordered input bit set, where S is an arbitrary predetermined value; a second encoder with memory size m, having a second input, coupled to a second source and said common source, and a multi-state register having 2 m states, for receiving said reordered input bit set as said second source and encoding said reordered input bit set to provide a reordered encoded input bit set at a second output; and a switch, for switching said first encoder from said first source to said common source and for switching said second encoder from said second source to said common source; whereby said first output provides said common source; whereby said interleaver reorders said integers such that once reordered, the value for |I(k)−I(k−nL)| is not evenly divisible by L, where L=2 m −1, and n is a positive integer subject to k−nL≧0 and nL≦S.