Patent ID: 8510357

Claim:
A method of operating an integrated circuit that includes a plurality of subregions of logic module circuitry, each of the subregions being capable of producing (1) a redundant form sum bit signal from addition of a respective group of three input bit signals, and (2) a redundant form carry bit signal from said addition, and each of the subregions including ripple carry adder circuitry for producing a ripple carry bit signal, only a subset of said subregions being used for addition of input bit signals to produce redundant form sum bit signals of input bit signals up to a predetermined threshold arithmetic significance, the method comprising: setting all of the subregions that can produce ripple carry bit signals having arithmetic significance greater than the threshold to propagate the ripple carry bit signal from the subregion having the threshold arithmetic significance; and re-applying to the subregion that can produce the ripple carry bit signal having greatest arithmetic significance the input bit signals having the threshold arithmetic significance.