Patent ID: 7220652

Claim:
A method of manufacturing a metal-insulator-metal capacitor device, comprising: forming an at least one lower insulating layer on a lower metal interconnecting layer; forming a first trench in the at least one lower insulating layer, exposing the lower metal interconnecting layer; sequentially depositing a lower barrier metal layer, a capacitor dielectric film, and the upper barrier metal layer in the first trench and over the at least one lower insulating layer; forming a first conductive film on the upper barrier layer; planarizing the first conductive film to the at least one lower insulating layer; forming a first via and a second trench in the at least one lower insulating layer, thereby exposing the lower metal interconnecting layer; forming a second conductive film, filling the first via and the second trench; and planarizing the second conductive film to the at least one lower insulating layer; wherein said method further comprises, after planarizing the second conductive film; forming an at least one upper insulating layer on the at least one lower insulating layer; forming a second via in the at least one upper insulating layer, exposing the first conductive film; and forming a third via in the at least one insulating layer, exposing the second conductive film, wherein the second via and the third via have substantially the same depths.