Patent ID: 8872351

Claim:
A semiconductor device, comprising: a substrate including a via hole therethrough; a through electrode filling the via hole; a via-insulating layer disposed between the through electrode and the substrate; and a buffer layer disposed between the through electrode and the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer and the buffer layer includes tetraethylorthosilicate (TEOS) oxide; low-k dielectric containing a SiO-based material, in which C, CH, CH 2 , or CH 3 or any combination thereof is added as a ligand; or a porous layer of the low-k dielectrics; or any combination thereof, wherein the low-k dielectric comprises octamethylcyclotetrasiloxane (OMCTS), dimethyldimethoxysilane (DMDMOS), tetramethylcyclotetrasiloxane (TMCTS), diethoxymethylsilane (DEMS), or AURORA™ (ethyl 2-chloro-3-[2-chloro-4-fluoro-5-[4-(difluoromethyl)-4,5-dihydro-3-methyl-5-oxo-1H-1,2,4-triazol-1-yl]phenyl]propanoat), or any combination thereof, and the porous layer comprises an insulating layer including the low-k dielectric, oxygen (O 2 ), and at least one of α-terpinene (ATRP) and bicycloheptadiene (BCHD).