Patent ID: 8426912

Claim:
A semiconductor device comprising: a semiconductor layer of a first conductivity type; a body region of a second conductivity type formed in a surface layer portion of the semiconductor layer; a trench dug from the surface of the semiconductor layer to penetrate the body region; a source region of a first conductivity type formed on a side portion of the trench in a surface layer portion of the body region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode embedded in the trench through the gate insulating film and so formed that a bottom surface of the gate electrode is in contact with the bottom surface of the trench via the gate insulating film, and a top surface of the gate electrode is lower by one stage than the surface of the source region; a peripheral wall film formed on a peripheral edge portion of the top surface of the gate electrode to be opposed to an upper end portion of the side surface of the trench, to cover said peripheral edge portion and to expose remaining portion of the top surface of the gate electrode; an element isolation portion formed on the surface of the semiconductor layer for isolating a first element forming region and a second element forming region from each other, wherein the body region is formed in the first element forming region; and a planar gate MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) formed in the second element forming region.