Patent ID: 8890225

Claim:
A non-volatile memory (NVM) device, comprising: a semiconductor substrate having a first region and a second region approximate the first region; a data-storing structure formed in the first region and designed operable to retain charges, wherein the data-storing structure includes: a first doped well of a first-type dopant disposed in the semiconductor substrate, a first gate dielectric feature disposed on the first doped well, and a first gate electrode disposed on the first gate dielectric feature and configured to be floating; and a capacitor formed in the second region and coupled with the data-storing structure for data operations, wherein the capacitor includes: a second doped well of the first-type dopant disposed in the semiconductor substrate, a second gate dielectric feature disposed on the second doped well, and a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode; and a third doped well of a second-type dopant opposite from the first-type dopant, wherein the third doped well is disposed in the semiconductor substrate within the second region and is underlying the second doped well.