Patent ID: 7064996

Claim:
A method for refreshing a dynamic memory cell in a memory circuit, the memory cell being arranged at a word line and a bit line of a bit line pair, comprising: during read-out of the memory cell, activating the word line and amplifying, with a sense amplifier, a charge difference brought about thereby on the bit lines to generate a high charge potential and a low charge potential; after the readout, charging the potentials of the bit lines to a first center potential; during refresh of the memory cell, activating the word line and amplifying, with the sense amplifier, the charge potentials of the bit lines, depending on charge information of the memory cell, to generate a high refresh potential and a low refresh potential; and after the refresh, charging the potentials of the bit lines to a second center potential, wherein the potential difference between the high refresh potential to which the sense amplifier drives the bit lines during refresh and the second center potential is greater than the potential difference between the high charge potential to which the sense amplifier drives the bit lines during readout and the first center potential.