Patent ID: 8024387

Claim:
A computer-readable medium storing computer-executable instructions for performing the following: obtaining a first layout of a linear finite state machine, the first layout of the linear finite state machine including a plurality of serially coupled memory elements and one or more first layout feedback connections, each of the one or more first layout feedback connections coupling an output of a respective one of the memory elements to inputs of one or more respective other ones of the memory elements, wherein the one or more feedback connections couple the output of a respective one of the memory elements to the inputs of the one or more respective other ones of the memory elements via respective logic gates; and performing one or more transformations of the one or more feedback connections to transform the first layout of the linear finite state machine into a second layout of the linear finite state machine, the combined length of the one or more transformed feedback connections in the second layout of the linear finite state machine being less than the combined length of the feedback connections in the first layout of the linear finite state machine, the second layout of the linear finite state machine further being capable of providing a same output sequence as the first layout of the linear finite state machine.