Patent ID: 8143948

Claim:
A circuit comprising: a supply voltage rail; a first input port and a second input port; a first output port and a second output port; a first input NPN transistor comprising a base connected to the first input port, a collector connected to the supply voltage rail, and an emitter; a first input PNP transistor comprising a base connected to the first input port, a collector connected to the second output port, and an emitter; a second input NPN transistor comprising a base connected to the second input port, a collector connected to the supply voltage rail, and an emitter; a second input PNP transistor comprising a base connected to the second input port, a collector connected to the first output port, and an emitter; a first PNP transistor comprising an emitter connected to the emitter of the first input NPN transistor, a base, and a collector connected to the first output port; a second PNP transistor comprising an emitter connected to the emitter of the second input NPN transistor, a base connected to the base of the first PNP transistor, and a collector connected to the second output port; a third PNP transistor comprising an emitter connected to the emitter of the first input NPN transistor, a base connected to the base of the first PNP transistor, and a collector connected to the base of the third PNP transistor; and a fourth PNP transistor comprising an emitter connected to the emitter of the second input NPN transistor, a base connected to the base of the first PNP transistor, and a collector connected to the collector of the third PNP transistor.