Patent ID: 7419896

Claim:
A method for forming a landing plug contact in a semiconductor device, comprising the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation layer until the gate hard mask is exposed; forming an etch barrier layer on the inter-layer insulation layer; etching a predetermined portion of the inter-layer insulation layer by using the etch barrier layer as an etch barrier to form a plurality of contact holes; forming a polysilicon layer for forming the landing plug contacts until the polysilicon layer fills the contact holes; removing surface roughness created during the formation of the polysilicon layer by a first etch-back process which ends before the gate hard mask is exposed, wherein the first etch-back process is carried out under a first recipe that gives an isotropic dry etching of the polysilicon layer; and planarizing the polysilicon layer by a second etch-back process until the gate hard mask is exposed, wherein the second etch-back process is carried out under a second recipe that gives an anisotropic dry etching of the polysilicon layer, wherein the recipe for the first etch-back process uses a mixed gas of CF 4 gas and O 2 gas.