Patent ID: 7490226

Claim:
In a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages from an initial stage to a final write back stage, a method comprising the steps of: issuing a first instruction to move through said sequence of execution stages, said first instruction being directed to a specified one of said registers; issuing a second instruction to move through at least some of said execution stages, said second instruction being issued after said first instruction has issued, but before said first instruction reaches said final write back stage, said second instruction being likewise directed to said specified register and comprising either a store instruction or a load instruction, selectively; providing a vector component that is limited to a single R bit and a single W bit that respectively correspond to said specified register; using only said R bit of said vector component to ensure that said second instruction does not read data from said specified register before said first instruction reaches said final write back stage, when said second instruction comprises a store instruction; and using only said W bit of said vector component to ensure that said second instruction does not write data to said specified register before said first instruction reaches said final write back stage, when said second instruction comprises a load instruction.