Patent ID: 8513067

Claim:
A fabrication method for a surrounding gate silicon nanowire transistor with air as spacers, characterized in that, the transistor is fabricated on a SOI substrate, and the method comprises the following steps: performing an isolation process on the SOI substrate; depositing a material A having a relatively high etching selectivity ratio with respect to Si on the SOI substrate, the SOI substrate including Silicon; performing photolithography on material A to define a Fin hard mask, the performing photolithography creating a pattern of photoresist; etching the material A and transferring the pattern of photoresist onto the material A to form the Fin hard mask; performing source and drain implantation on the SOI substrate; performing photolithography to define a channel region and source/drain large regions on the silicon of the SOI substrate; etching the silicon by using the pattern of photoresist and the Fin hard mask of the material A as barriers, so as to form the Fin and the large source/drains within the silicon; removing the hard mask of the material A from the Si on the SOI substrate; performing oxidization of the silicon on the SOI substrate to form a nanowire; etching the the oxidized silicon through isotropic wet etching to form a floating nanowire; forming a gate oxide layer on a gate of the Si on the SOI substrate; depositing a polysilicon on the silicon of the SOI substrate, including on the large source/drain; performing polysilicon implantation; performing annealing to activate dopants of the polysilicon; etching the polysilicon until a polysilicon thickness of the polysilicon on the source/drain is around 30 to 50 nm; depositing SiN on to the polysilicon; performing photolithography to define a gate pattern on the SiN; etching the SiN and the polysilicon and transferring a second pattern of the photoresist onto the polysilicon to form the gate pattern; etching the polysilicon through isotropic dry etching or isotropic wet etching, to separate the gate and the source/drain with a space in between filled with air; depositing SiO 2 on to the SiN and polysilicon to form air sidewalls; performing annealing to densify the SiO 2 layer; using CMOS backend processes to complete the device fabrication.