Patent ID: 8448114

Claim:
A method for balancing rising and falling edges of a signal of an integrated circuit design stored in a memory using an electronic design automation (EDA) tool executing on a processor, wherein the integrated circuit design includes at least one logic path for transmitting the signal to at least one port having a pre-defined geometry, the method comprising: defining a virtual cell having a geometry that is the same as the pre-defined geometry of the at least one port; defining first and second input pins of the virtual cell for detecting rising and falling edges of the signal respectively, such that the first and second input pins and corresponding pins of the at least one port have the same pin geometries; accessing the integrated circuit design stored in the memory and overlapping the virtual cell with the at least one port of the integrated circuit design such that the first and second input pins are connected to a corresponding network of the at least one port; and configuring the first and second input pins as sinks, whereby the EDA tool executing on the processor identifies the first and second input pins and corresponding pins of the at least one port as parallel sinks, thereby balancing the rising and falling edges of the signal.