Patent ID: 8904221

Claim:
A data processing system comprising: a first processor, the first processor operating in a first clock domain with a first clock signal; a memory, the memory operating in a second clock domain with a second clock signal; a storage device; first synchronization circuitry comprising a first storage element and a second storage element, the first storage element sampling a signal emanating from the second clock domain, and the second storage element sampling an output of the first storage element, the first storage element and the second storage element being triggered by inverse transitions in the first clock signal; and second synchronization circuitry comprising a third storage element and a fourth storage element, the third storage element sampling a signal emanating from the first clock domain, and the fourth storage element sampling an output of the third storage element, the third storage element and the fourth storage element being triggered by inverse transitions in the second clock signal; wherein the data processing system is operative to cause the first processor to transfer a memory address to the storage device, to cause the memory address to be transferred from the storage device to the memory at least in part in response to a signal from the second synchronization circuitry, and to cause data associated with the memory address in the memory to be transferred to the first processor at least in part in response to a signal from the first synchronization circuitry.