Patent ID: 8065589

Claim:
A semiconductor memory device comprising: a memory cell array from which all bits of a data signal having a first number of the bits composed of a main data signal and an error detection/correction code data signal are simultaneously read; a sense amplifier for amplifying the read data signal; a selection unit for selecting a data signal having a second number of bits forming a part of the data signal amplified by the sense amplifier; and an error detection/correction unit for performing error detection and correction based on at least a part of the selected data signal having the second number of bits; an amplification unit for amplifying the data signal having the second number of bits selected by the selection unit; and an amplified data signal selection unit for selecting a data signal having a third number of bits forming a part of the amplified signal having the second number of bits, wherein: the selection by the selection unit is performed based on a row address, and the selection by the amplified data signal selection unit is performed based on either one of the row address and a column address.