Patent ID: 6959064

Claim:
A multimode clock recovery circuit for use in the provision of constant bit rate services in a cell relay network, comprising: a digital phase locked loop including a digital controlled oscillator for generating an output signal, a loop filter responsive to a phase signal to control said digital controlled oscillator, and a phase detector having multiple inputs for receiving different types of input signal; said phase detector comparing an input signal applied to any of said multiple inputs with said output signal to develop said phase signal; a local Synchronous Residual Time Stamps (SRTS) generator for generating time stamps from said output signal connected to one of said multiple inputs of said phase detector; said phase detector in a SRTS mode developing said phase signal from said locally generated time stamps and time stamps received over said cell relay network; another of said multiple inputs of said phase detector being adapted to receive a line rate clock signal; said phase detector in a line rate mode developing said phase signal from said line rate clock signal and said output signal; and a receive buffer for receiving incoming cells that in an adaptive mode develops said phase signal from a state of said receive buffer and applies said phase signal developed by said receive buffer to said loop filter to control said digital controlled oscillator.