Patent ID: 7853743

Claim:
A processor comprising: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein each of the plurality of processors includes a priority managing register for managing its status as to whether interrupts are disabled and a priority of a process which it is executing irrespective of whether it is executing a task or interrupt process, and the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, after determining that all of the plurality of processors are disabled for interrupts, the requested interrupt process is stored in an area of a ready queue based on a priority associated with the requested interrupt process, or after determining that at least one of the processors are not disabled for interrupts, then determining that at least one of the plurality of processors not disabled for interrupts is executing a process with a lower priority than a priority of the interrupt process, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the schedule.