Patent ID: 7388248

Claim:
A memory device comprising: a plurality of memory cells each including a capacitive structure having a first electrode, a dielectric layer comprising a first material formed over the first electrode, wherein the dielectric layer has at least one type of charge trap sites formed within the dielectric layer, the at least one type of charge trap sites increasing the dielectric relaxation current in the capacitive structure when a predetermined write voltage is applied to fill the at least one type of charge trap sites with charge, a second electrode formed over the dielectric layer, and an access device for selectively applying the predetermined write voltage to the capacitive structure and for selectively reading out a time-decaying amount of the dielectric relaxation current from the capacitive structure at a predetermined time after the predetermined write voltage is applied, whereby, when the at least one type of charge trap sites are filled, the capacitive structure generates the time-decaying amount of dielectric relaxation current at the predetermined time, and whereby the time decaying amount of dielectric relaxation current represents a logic state of data stored by said capacitor; and a circuit for controlling a reading out the dielectric relaxation current from the capacitive structures of the memory cells at the predetermined time.