Patent ID: 7028151

Claim:
An information processing device for, when an input address causes a cache miss, storing and reading the input address including first and second fields on a FIFO basis to provide the input address to a main memory control circuit, the device comprising: a first register file including a plurality of first registers for storing, in each first register, a first address consisting of the first and second fields, a valid flag indicating whether the first address is valid or invalid, and wait state information; a second register file including a plurality of second registers, corresponding to the respective plurality of first registers, for storing, in each second register, a second address consisting of the second field, and a valid flag indicating whether the second address is valid or invalid; a comparison circuit for comparing a value of the first field of the input address and a value of the first field of each of the plurality of first registers; and a control circuit for: allowing the input address to be stored in one of the first registers whose valid flag indicates an invalid state, and changing this valid flag to indicate a valid state, or, if a comparison result by the comparison circuit between one of the first registers whose valid flag indicates a valid state and the input address indicates a matching, then allowing the second field of the input address to be stored in corresponding one of the second registers whose valid flag indicates an invalid state, and changing this valid flag to indicate a valid state; and selectively allowing contents of one of the first registers whose valid flag indicates a valid state to be read; if the valid flag of corresponding one of the second registers indicates an invalid state, then changing this valid flag to indicate an invalid state, or else, allowing a value of the second field of this one of the second registers to be shifted to the second field of the corresponding one of the first registers, and changing the valid flag of this one of the second registers to indicate an invalid state.