Patent ID: 8095733

Claim:
A data processing system, comprising: an interconnect fabric; a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs); a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region, wherein the plurality of processing units includes at least first, second and third processing units and each of the plurality of processing units includes: a processor core; and a cache memory coupled to the processor core, said cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory; wherein the cache controller of the first processing unit, responsive to a memory access request from the processor core of the first processing unit that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of all of the first, second and third processing units to one of the second and third processing units via an election held over the interconnect fabric.