Patent ID: 6874047

Claim:
A system for transferring data between a plurality of devices coupled to a bus, at least one of the plurality of devices being operative at a plurality of clock rates, comprising: a bus including a data line operative to carry data and a clock line operative to carry a clock signal; and first and second devices operatively coupled to the bus, at least the second device including at least one data register, wherein the first and second devices are operative at a first clock rate, and the second device is further operative at a second reduced clock rate, the second reduced clock rate being less than the first clock rate, wherein at least the first device is operative to transmit data over the data line, and wherein the second device is operative to receive at least a portion of the data transmitted over the data line, to store the at least a portion of the data in the data register, and, in the event the first device is operating at the first clock rate and the second device is operating at the second reduced clock rate, to drive the clock line to a predetermined logic level while the data is stored in the data register, thereby enabling data transfer between the first device and the second device over the bus while the second device operates at the second reduced clock rate.