Patent ID: 7579902

Claim:
A charge pump circuit for generating a plurality of voltages in excess of a supply voltage and including: a first group of cascaded charge-pump stages each having an input and an output, the input of a first one of the first group of cascaded charge pump stages being driven from the supply voltage, the input of each successive one of the first group of cascaded charge pump stages being driven from the output of the preceding stage of the first group of cascaded charge pump stages; a first output stage having an input driven from the output of a last one of the first group of cascaded charge pump stages and an output coupled to a first voltage node; a second group of cascaded charge-pump stages each having an input and an output, the input of a first one of the second group of cascaded charge pump stages being driven from the output of the last one of the first group of cascaded charge pump stages, the input of each successive one of the second group of cascaded charge-pump stages being driven from the output of the preceding stage of the second group of cascaded charge-pump stages; a second output stage having an input driven from the output of a last one of the second group of cascaded charge pump stages and an output coupled to a second voltage node; a clock generator coupling a single set of clock signals to the charge pump stages in the first and second groups, and the first and second output stages, the clock generator having a disable input; a first switch coupled between the first output stage and the first output node and having a control element; a second switch coupled between the second output stage and the second output node and having a control element; a first comparator coupled to a reference voltage and to the first output node through a voltage divider, the first comparator having an output coupled to the control element of the first switch; a second comparator coupled to a reference voltage and to the second output node through a voltage divider, the second comparator having an output coupled to the control element of the second switch; and an AND gate having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output coupled to the disable input of the clock generator.