Patent ID: 7704802

Claim:
A method of forming an integrated circuit wafer structure having a programmable, random logic array, comprising the steps: providing a substrate; forming a semiconductor layer above the substrate, including the steps of i) forming a first region of a first semiconductor type, ii) forming an array of spaced apart second regions of a second semiconductor type, and iii) forming a plurality of space-charge regions, wherein each of the space charge regions extends around a respective one of said second regions and separates said one of the second regions from the first region of the semiconductor layer, and wherein the step of forming an array of spaced apart second regions includes the step of forming each of the second regions contiguous with and surrounded by a respective one of the space-charge regions; and positioning a first set of contacts above and in physical and electrical contact with a respective one area of said first region of the semiconductor layer; and positioning a second set of contacts above and in physical and electrical contact with a respective one of said second regions; wherein said first and second sets of contacts facilitate connecting together the said areas of the first region and said second regions of the semiconductor layer in various, programmable ways.