Patent ID: 8225245

Claim:
A method of merging gated-clock domains in a semiconductor design comprising: selecting, by a computer processor, a set of initial clock gating functions comprising a plurality of clock gating functions, wherein each clock gating function comprises a support set of variables; defining, by the computer processor, a plurality of subsets of clock gating functions, each subset comprising a plurality of clock gating functions from the set of initial clock gating functions; defining a set of super clock gating functions; defining a set of final clock gating functions; for each subset of clock gating functions: producing a set of quantified functions by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset; when the set of quantified function are equal, selecting any one of the quantified functions as a super clock gating function; adding the super clock gating function to the set of super clock gating functions; when the set of super clock gating function contains at least one super clock gating function: sorting the set of super clock gating functions according to a criterion; selecting the super clock gating function that best achieves the criterion; adding the selected super clock gating function to the set of final clock gating functions; removing the selected super clock gating function from the set of super gating functions; modifying the remaining super clock gating functions from the set of super clock gating functions by preventing flip-flops gated by the selected super clock gating function from being gated by the remaining super clock gating functions; and outputting a gate-level netlist that comprises the set of final clock gating functions.