Patent ID: 8443422

Claim:
An apparatus, comprising: an interconnect coupled and shared amongst a plurality of target intellectual property blocks including a first target intellectual property block, and a plurality of initiator intellectual property blocks including a first initiator intellectual property block, where the first target intellectual property block is configured to service and respond to transactions from the first initiator intellectual property block over the interconnect, wherein the interconnect has an associated protection mechanism with protection logic configured to restrict access for the transactions to the first target intellectual property block based on criteria including access permissions associated with a protection region for the first target intellectual property block, where the access permissions associated with the protection region at least include who is the source requesting access to the first target intellectual property block and the type of access being requested, where the interconnect is configured to route the transactions between the first initiator intellectual property block and the first target intellectual property block, where the protection logic is configurable to set the access permissions for two or more protection regions in the integrated circuit, where each protection region is associated with address spacing in the integrated circuit, where the protection mechanism compares to determine when attributes of the transaction satisfy the access permissions of a given protection region, where the protection mechanism is a firewall that is programmable to prevent unauthorized access to or from the two or more protection regions, and where at least the protection mechanism, the interconnect, the first initiator intellectual property block and the first target intellectual property block are located on and part of a System on a Chip.