Patent ID: 8138048

Claim:
A method of producing a semiconductor device constructed using a MOS transistor which has a structure where a source region and a drain region are formed, respectively, in one and a remaining one of an upper portion and an underneath portion of a pillar-shaped semiconductor layer formed on a silicon substrate, and a gate electrode is formed to surround the pillar-shaped semiconductor layer, the method being characterized by comprising the steps of: etching a silicon substrate to form a pillar-shaped semiconductor layer; forming a gate dielectric film at least on a surface of a sidewall of the pillar-shaped semiconductor layer; forming a gate conductive film on a surface of the gate dielectric film; etching each of the gate dielectric film and the gate conductive film to form a gate electrode; forming a first dielectric film on the sidewall of the upper portion of the pillar-shaped semiconductor layer to prevent siliciding the sidewall of the upper portion of the pillar-shaped semiconductor layer when a silicide layer is formed on an exposed portion of each of the source and drain regions formed in the upper and underneath portions of the pillar-shaped semiconductor layer; forming a silicide layer on the exposed portion of each of the diffusion layers formed in the upper and underneath portions of the pillar-shaped semiconductor layer; after completion of the formation of the silicide layer, removing the first dielectric film; forming a second dielectric film on the pillar-shaped semiconductor layer and the gate electrode to serve as a contact stopper; and forming a third dielectric film on the second dielectric film to serve as an interlayer film.