Patent ID: 8349709

Claim:
A method of forming a semiconductor device, comprising: forming a wiring layer in a semiconductor chip forming area of a semiconductor wafer, the wiring layer extending in a first direction from a top view; forming a plurality of first dummy patterns which are placed between the wiring layer and a scribed area of the semiconductor wafer and arranged in the first direction, the plurality of first dummy patterns being placed apart from the wiring layer with a first distance in a second direction perpendicular to the first direction, the plurality of first dummy patterns having a same layer level as that of the wiring layer; forming a second dummy pattern in the semiconductor chip forming area between the wiring layer and the plurality of first dummy patterns, the second dummy pattern continuously extending in the first direction so that the second dummy pattern intervenes between the wiring layer and each of the first dummy patterns in the second direction, the second dummy pattern being placed apart from the wiring layer with a second distance and apart from the first dummy patterns with a third distance in the second direction, the second dummy pattern having a same layer level as that of the wiring layer; and dividing the semiconductor chip forming area along the scribed area.