Patent ID: 7284216

Claim:
A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout, comprising: a database for storing information on the circuit traces; a computer connected to the database, for calculating and verifying signal propagation delays of the circuit traces, the computer comprising: a setting module for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding whether to calculate a propagation delay of a lead wire connected with the trace, the lead wire being part of a package encapsulating electronic components on the PCB; a selecting module for selecting a segment from a segment set of the trace thereby yielding a selected segment; a calculating module for calculating a length of the selected segment by utilizing a calculating function according to a type of the selected segment, calculating a propagation delay of the selected segment according to the length thereof, calculating a propagation delay of the trace by summing the propagation delays of all segments of the trace, calculating a propagation delay of the lead wire of the package connected with the trace, and calculating a total propagation delay by summing the propagation delays of the trace and the lead wire; and a determining module for determining whether all segments in the segment set have been calculated, determining whether to calculate the propagation delay of the lead wire connected with the trace according to the selection made, and determining whether the total propagation delay lies in a range between the minimum propagation delay and the maximum propagation delay.