Patent ID: 7396722

Claim:
A method for manufacturing a memory device, comprising: forming a bulk substrate; forming an oxide layer disposed outwardly from the bulk substrate; forming at least one field oxide region in the oxide layer; forming a first lightly doped region in the bulk substrate; forming a second lightly doped region in the bulk substrate; forming a gate oxide region in the oxide layer; forming a polysilicon layer disposed outwardly from the oxide layer; forming a first active region in the first lightly doped region; forming a second active region in the second lightly doped region; forming a third active region in the bulk substrate; and patterning the polysilicon layer to form a floating gate layer, the floating gate layer having a first end positioned over the first and third active regions, a second end positioned over the second active region, and an intermediate portion joining the first and second ends, the memory device formed without a separate erase region.