Patent ID: 7312621

Claim:
A semiconductor test unit comprising: a test circuit for inputting/outputting a test signal to/from an examined electronic product; a test signal wiring electrically connected to the test circuit; a contact board electrically connected to an electrode of the examined electronic product and provided with a conductive via to which the test signal is transmitted, the contact board being made of an insulative porous material with air permeability and having top and bottom faces and a deformation suppression portion on the top face, the deformation suppression portion making the whole contact board have a thermal expansion coefficient within a range of ±6 ppm/K relative to that of the examined electronic product so that thermal expansion is suppressed; a multilayer circuit board electrically connected to the conductive via and the test signal wiring, located below the bottom face of the contact board, and made of an insulative air-permeable material; and a vacuum attachment mechanism for attaching the examined electronic product, the contact board, and the multilayer circuit board thereto by vacuum, thereby holding the same.