Patent ID: 8546224

Claim:
A method for forming a twin bit cell structure for a flash memory device, the method comprising: providing a semiconductor substrate including a surface region; forming a gate dielectric layer overlying the surface region; forming a polysilicon gate structure overlying the gate dielectric layer; forming first and second undercut regions underneath the polysilicon gate structure in a portion of the gate dielectric layer; exposing the semiconductor substrate, the gate dielectric layer, the undercut regions, and the polysilicon gate structure to an oxidizing environment to cause a formation of a first silicon oxide layer overlying a top surface, side surfaces, and bottom surfaces facing the undercut regions of the polysilicon gate structure and a formation of a second silicon oxide layer overlying a portion of the surface region of the semiconductor substrate; depositing an aluminum oxide material over the first and second silicon oxide layers and filling the undercut regions; selectively etching a portion of the aluminum oxide material while maintaining the aluminum oxide material in an insert region in a portion of each of the undercut regions; and forming a sidewall structure, wherein the sidewall structure is formed so as to contact side and bottom surfaces of the first silicon oxide layer, to contact exposed surfaces of the aluminum oxide material in the undercut regions, and to contact an exposed surface portion of the second oxide layer.