Patent ID: 8112577

Claim:
An apparatus for storing information, comprising: a plurality of groups of addressable memory locations, with each memory location of said addressable memory locations being configured to be read from in response to a read command corresponding to said memory location, and written to in response to a write command corresponding to said memory location; and with each group of the plurality of groups of addressable memory locations being selectable for causing one or more memory cells within said group to be refreshed; one or more interfaces configured for receiving an operation code and operation parameters of a plurality of commands to be performed and for receiving data, with the plurality of commands including: said read command, said write command, and a refresh command; control logic configured: to read from one or more memory locations in the plurality of groups of addressable memory locations in response to a received read command specifying a read operation code and said one or more memory locations, to write received data to one or more memory locations in the plurality of groups of addressable memory locations in response to a received write command specifying a write operation code and said one or more memory locations, and to refresh one or more memory cells in the plurality of groups of addressable memory locations in one or more but less than all of the plurality of groups of addressable memory locations in response to a received refresh command specifying a refresh operation code and said one or more but less than all of the plurality of groups of addressable memory locations; wherein the apparatus is configured to receive the refresh command at least partially overlapping in time with receiving a read or write command.