Patent ID: 8098787

Claim:
A method comprising: locking a clock signal to a reference clock signal; generating a first frequency signal based on the reference clock signal; converting a first serial data stream associated with the first frequency signal into a first parallel data stream associated with a second frequency signal; converting a second serial data stream associated with the first frequency signal into a second parallel data stream associated with the second frequency signal; comparing a position of a beginning event bit in the first parallel data stream with a position of an ending event bit in the second parallel data stream, wherein the comparing comprises: sequentially checking bits from the first parallel data stream until the beginning event bit is found; determining a first position in the second parallel data stream that is contemporaneous to the beginning event bit; sequentially checking bits from the second parallel data stream starting at the first position until the ending event bit is found; and identifying a number of bits between the first position and the ending event bit; and identifying quantized time between the beginning event bit and the ending event bit in response to the comparing.