Patent ID: 7348675

Claim:
An integrated circuit comprising: a first dielectric layer; a first via of the first dielectric layer; a first conductive pad disposed on the first dielectric layer or in the first via of the first dielectric layer; a second dielectric layer having a thickness and defining a second via and a third via, the second and third vias extending through the thickness of the second dielectric layer, the second via in communication with the first conductive pad, and the third via disposed coaxially to the first via and electrically insulated from the first conductive pad; a carbon nanotube semiconductor material disposed in the second via and through the thickness of the second dielectric layer, and correspondingly in communication with the first conductive pad; a conductive material disposed in the third via and through the thickness of the second dielectric layer, the conductive material electrically insulated from the carbon nanotube semiconductor material to form a ring gate electrode; and a third dielectric layer disposed over the second dielectric layer and including a second conductive pad in communication with a selected one of the carbon nanotube semiconductor material in the second via and the conductive material.