Patent ID: 8681528

Claim:
A nonvolatile memory comprising a first one-bit memory cell, wherein the first one-bit memory cell is formed on a substrate, and the first one-bit memory cell comprises: a first bit line; and N storage units, wherein each of the N storage units comprises a first doped region, a second doped region and a third doped region, which are formed in a surface of the substrate, wherein a first gate structure is disposed over a first channel region between the first doped region and the second doped region, and a second gate structure is disposed over a second channel region between the second doped region and the third doped region, wherein the first doped region of the first storage unit is connected to the first bit line, the first gate structure of the first storage unit is connected to a first control signal line, and the second gate structure of the first storage unit is connected to a first anti-fuse signal line, wherein the first doped region of the m-th storage unit is connected to the third doped region of the (m−1)-th storage unit, the first gate structure of the m-th storage unit is connected to an m-th control signal line, and the second gate structure of the m-th storage unit is connected to an m-th anti-fuse signal line, wherein m is an integer larger than or equal to 2 and smaller than or equal to N.