Patent ID: 7053670

Claim:
A semiconductor integrated circuit device, comprising: a first line to supply a first power supply potential; a second line to supply a second power supply potential; and an input circuit connected between the first line and the second line, wherein the input circuit comprises: a pair of input terminals; a pair of first capacitance elements connected to the pair of input terminals; a pair of first differential MOS transistors provided with a pair of gate electrodes connected to the pair of input terminals through the pair of first capacitance elements respectively, and with a pair of source electrodes connected to each other to form a common source, and with a pair of drain electrodes; a pair of load elements connected between each of the pair of drain electrodes of the first differential MOS transistors and the first line; a current source connected between the common source of the first differential MOS transistors and the second line; a pair of second differential MOS transistors provided with a pair of gate electrodes connected to the pair of input terminals respectively, with a pair of source electrodes connected to each other to form a common source, and with a pair of drain electrodes, wherein the pair of load elements are connected between each of the pair of drain electrodes of the second differential MOS transistors and the first line, and wherein the current source is connected between the common source of the second differential MOS transistors and the second line.