Patent ID: 7625782

Claim:
A method of manufacturing an array substrate comprising: forming a first test line, a second test line, and a gate line extending along a first direction; forming a shorting bar extending along the first direction, a first source line extending from the shorting bar along a second direction disposed substantially perpendicular to the first direction, a first drain electrode of a first switching device that is separated from the first source line, a second source line extending along the second direction such that the second source line is separated from the shorting bar, and a second drain electrode of a second switching device that is separated from the second source line, the first source line being electrically connected to the a first switching device and the second source line being electrically connected to the second switching device; and forming a first bridge pattern electrically coupling the first test line to the first source line, a second bridge pattern electrically coupling the second test line to the second source line, a first pixel electrode layer electrically connecting the first switching device, and a second pixel electrode layer electrically connecting to the second switching device.