Patent ID: 7588961

Claim:
A method for manufacturing semiconductor devices comprising: forming a hetero semiconductor region on a surface of a semiconductor substrate by creating a plurality of layers on the surface of the semiconductor substrate to form the hetero semiconductor region; introducing an impurity of a first conducting type to a first portion of the hetero semiconductor region to form a first hetero semiconductor portion by introducing the impurity of the first conductive type to at least the bottom layer of the hetero semiconductor region, the first hetero semiconductor portion including a first hetero bonded interface between the semiconductor substrate and the first hetero semiconductor region; introducing an impurity of a second conducting type to a second portion of the hetero semiconductor region to form a second hetero semiconductor portion by introducing the impurity of the second conducting type to at least the bottom layer such that the second hetero semiconductor portion is between the first hetero semiconductor portion and the gate electrode, the second hetero semiconductor portion including a second hetero bonded interface between the semiconductor substrate and the second hetero semiconductor portion; forming a gate electrode adjacent to the second hetero bonded interface; coupling a source electrode to the first hetero semiconductor portion and the second hetero semiconductor portion; and coupling a drain electrode to the semiconductor substrate.