Patent ID: 7220983

Claim:
A method of manufacturing a memory device, including: forming a multi-layer stack on a surface of a substrate, the multi-layer stack including a first conductive layer, a layer or layers of material selected for formation of a selection device and an insulation layer; etching trenches through the insulation layer to the layer or layers of material selected for formation of a selection device; forming sidewall spacer electrodes of a conductive material along opposing sides of the trenches, over the layer or layers of material selected for formation of a selection device; etching gaps into the multi-layer stack to define a first plurality of lines extending in a first direction, wherein the gaps between the first plurality of lines extend through the multi-layer stack on the substrate and separate the sidewall spacers on the opposing sides of the trenches; filing the gaps with an insulating material; forming a layer or layers of material selected for formation of a phase change memory element over the sidewall spacer electrodes; forming a second conductive layer over the layer or layers of phase change material; and etching additional gaps into the multi-layer stack and through the layer or layers of phase change material and the second conductive layer, to define a second plurality of lines extending in a second direction so that the first and second pluralities of lines intersect, wherein the additional gaps extend through the multi-layer stack to the first conductive layer, and self-aligned stacks including remaining portions of the layer or layers of material selected for formation of a selection device, the sidewall spacer electrodes, and the layer or layers of material selected for formation of a phase change memory element, extending between lines in the first plurality of lines formed by the first conductive layer and lines in the second plurality of lines formed by the second conductive layer.