Patent ID: 8022546

Claim:
A semiconductor chip comprising: a silicon substrate; a transistor in or on said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride; a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer is over said first contact point, wherein said first polymer layer has a thickness between 2 and 50 micrometers; a third metal layer on said first polymer layer and on said first contact point, wherein said third metal layer comprises a titanium-containing layer with a thickness between 0.01 and 3 micrometers on said first polymer layer and on said first contact point, a gold seed layer with a thickness between 0.05 and 3 micrometers on said titanium-containing layer, and an electroplated gold layer with a thickness between 2 and 100 micrometers on said gold seed layer; and a second polymer layer on said third metal layer and on said first polymer layer.