Patent ID: 8402183

Claim:
A method for coordinating control settings for an automated input/output (I/O) processor, said method comprising: identifying at least one mode based on a behavior of a fast path engine associated with a storage controller in order to determine at least one combination with respect to a plurality of control bits associated with said fast path engine, wherein said at least one mode is assigned as a state with respect to a state machine; configuring said state with respect to said state machine to comprise at least one of the following types of states; an ineligible state wherein said ineligible state further comprises configuring said fast path engine and a core unit associated with said storage controller to accept a fast path I/O in order to thereafter permit said firmware to issue a device I/O to said core unit; an active state; a postponing state; a postponed state; an interleaving state; a managing state; a disabled state; a managed state; and a resuming state; determining an I/O path exception and an error condition that cause a transition between said state with respect to a firmware associated with said storage controller in order to thereafter assign said transition from one state to another state; and configuring a generic logic template to govern said transition in order to thereafter execute said logic when an event occurs thereby triggering multiple state transitions with respect to said plurality of control bits associated with said fast path engine.