Patent ID: 7900057

Claim:
A cryptographic Serial ATA (SATA) apparatus, comprising: a SATA protocol stack for communicating with an interface of a device; a cryptographic engine operatively coupled to the SATA protocol stack for encrypting or decrypting at least a subset of data FISes (Frame Information Structures) communicated to or from the SATA protocol stack; and a main controller implemented at least partially in hardware, the main controller configured to cause: the SATA protocol stack to send at least first payload of a first data FIS to the cryptographic engine responsive to the first data FIS associated with a pre-defined category of command set; the cryptographic engine to decrypt at least a portion of the first payload received from the SATA protocol stack; and the SATA protocol stack to process a Register-Device to Host FIS without decryption responsive to receiving the Register-Device to Host FIS from the interface of the device.