Patent ID: 7590910

Claim:
An integrated circuit comprising: A. a test data input lead, a test data output lead, a test clock input lead, and a test mode select input lead; B. plural TAP circuits, each having a test data input, a test data output, a test clock input, and a test mode select input; C. a TAP linking module selectively connecting the test data input lead, the test data output lead, the test clock input lead, and the test mode select input lead to each of the TAP circuits, the TAP linking module including: i. a first multiplexer having plural data inputs, each data input being connected to the test data output of one TAP circuit, control inputs, and a data output; ii. a second multiplexer having plural data inputs, a control input and an output connected to the test data output lead, one data input being connected to the data output of the first multiplexer; iii. an augmentation instruction shift register having a data input connected to the data output of the first multiplexer, a data output connected to another data input of the second multiplexer, control inputs, and scan code outputs; and iv. decode circuits having control outputs connected to the control inputs of the first multiplexer, the second multiplexer, and the augmentation instruction shift register, and scan code inputs connected to the scan code outputs of the augmentation instruction shift register.