Patent ID: 7948254

Claim:
An apparatus including a digital communications test system for testing a plurality of devices under test (DUTs), comprising: a plurality of DUT electrodes to couple to a plurality of DUTs, convey a plurality of DUT transmission signals from said plurality of DUTs, and convey a plurality of DUT reception signals to said plurality of DUTs; a plurality of signal combining and dividing circuits to couple to a plurality of vector signal analyzers (VSAs) and a plurality of vector signal generators (VSGs), wherein each one of said plurality of signal combining and dividing circuits is adapted to combine at least first and second ones of said plurality of DUT transmission signals for a respective one of said plurality of VSAs, and divide a signal from a respective one of said plurality of VSGs to provide at least first and second ones of said plurality of DUT reception signals; and a plurality of signal conveyance control circuits coupled between said plurality of DUT electrodes and said plurality of signal combining and dividing circuits, and responsive to one or more conveyance control signals by conveying one or more selected ones of said plurality of DUT transmission signals from one or more of said plurality of DUT electrodes to one or more of said plurality of signal combining and dividing circuits, and conveying one or more of said plurality of DUT reception signals from one or more of said plurality of signal combining and dividing circuits to one or more of said plurality of DUT electrodes.