Patent ID: 8525820

Claim:
A driving circuit comprising: a gate driver; and a power supply to generate a power supply voltage, the power supply voltage is a high level when power is on and the power supply voltage is a low level when power is off, wherein the power supply voltage enable and disable the gate driver to be driven, wherein the gate driver outputs one of a gate driving signal or a discharge signal according to level of the power supply voltage, wherein the gate driving signal includes a scan signal having a gate high voltage and a gate low voltage, wherein the discharge signal is a voltage with a level equal to level of the gate high voltage, is generated when the power supply voltage is the low level and is supplied to gate lines of a liquid crystal panel to discharge a residual voltage of the liquid crystal panel, wherein the gate driver comprises: a plurality of shift registers, each connecting an output terminal thereof to a corresponding the gate line of the liquid crystal panel, a plurality of logic controllers, each connecting to an input terminal of a first corresponding shift register to generate a control signal having at least two states and the output terminal of a second corresponding shift register, wherein each of the logic controllers receive the power supply voltage and one of a gate start pulse signal or an output signal of the previous shift register, wherein the logic controller generates the control signal with a high level during a predetermined time when the power supply voltage is the low level, wherein the gate driver outputs the discharge signal when the power supply voltage is the low level and supplies the discharge signal to the gate lines.