Patent ID: 8482331

Claim:
An open loop type delay locked loop comprising: a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal; a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse; a clock control unit configured to adjust a toggling period of a clock signal in response to a control signal; and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value, wherein the delay amount pulse generation unit comprise: a replica delay oscillator section configured to output a replica oscillation signal having a pulse width corresponding to a modeled delay amount in response to a reset signal; a clock transfer section configured to receive the clock signal and output the received clock signal in response to the reset signal; and a pulse generation section configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking the clock signal in response to the replica oscillation signal and an output of the clock transfer section.