Patent ID: 8111536

Claim:
A semiconductor memory device comprising: a memory cell array having memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series, the resistance element being configured to be capable of having at least a first resistance value and a second resistance value higher than the first resistance value; a wiring pullout portion prepared for pulling out the first wirings and the second wirings; a contact arrangement portion formed to arrange a plurality of contacts on a plane, the contacts being connected to the first wirings or the second wirings; and a probe that can move along the plane to electrically contact with either of the contacts; a plurality of the memory cell arrays being laminated on the semiconductor substrate, the wiring pullout portion being configured to pull out odd-numbered ones of the first wirings or the second wirings from the first side of the memory cell array, and pull out even-numbered ones of the first wirings or the second wirings from the second side of the memory cell array, the second side being the opposite of the first side, and the contact arrangement portion comprising a first contact arrangement portion provided at the first side and formed to arrange a plurality of contacts electrically connected to odd-numbered ones of the first wirings or the second wirings on a plane, and a second contact arrangement portion provided at the second side and formed to arrange a plurality of contacts electrically connected to even-numbered ones of the first wirings or the second wirings on a plane.