Patent ID: 7429536

Claim:
A method of forming isolated features in an integrated circuit comprising: providing a substrate overlaid by multiple layers of masking material; creating a first series of selectively definable lines in a first layer of masking material; reducing the pitch of the first series of selectively definable lines using a spacer material to create a first arrangement of masking features having a smaller pitch than the first series of selectively definable lines, the first arrangement of masking features comprising pitch-reduced masking lines separated by pitch-reduced spaces, the first arrangement corresponding to a first pattern; creating a second series of selectively definable lines in a second layer of masking material, the second series of selectively definable lines not parallel to the first series of selectively definable lines; reducing the pitch of the second series of selectively definable lines using a spacer material to create a second arrangement of masking features having a smaller pitch than the second series of selectively definable lines, the second arrangement of masking features comprising pitch-reduced masking lines separated by pitch-reduced spaces, the second arrangement corresponding to a second pattern; etching the substrate in a third pattern derived by superimposing the first and second patterns to create isolated features comprising holes; filling the holes with conductive material until the conductive material overflows; and etching the overflow of conductive material with chemical mechanical planarization to create isolated contacts.