Patent ID: 7259074

Claim:
A trench isolation method in a flash memory device, comprising the steps of: forming a mask layer pattern on a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon; forming a trench in the semiconductor substrate corresponding to the device isolation area; removing an exposed portion of the insulating layer pattern enough to expose a first portion of the semiconductor substrate in the active area adjacent to the trench; forming a sidewall oxide layer on an inside of the trench and the first exposed portion of the semiconductor substrate; filling up a trench with a third insulation layer to cover the sidewall oxide layer; removing the mask layer pattern to expose a second portion of the semiconductor substrate; and forming a tunnel oxide layer on the exposed second portion of the semiconductor substrate by laterally removing a portion of the first insulation layer to have a thickness less than a thickness of the sidewall oxide layer.