Patent ID: 8865593

Claim:
A fabrication method comprising: providing a semiconductor substrate for fabricating an NMOS transistor; using a tellurium-doped target metal material to form a tellurium-containing metal layer; forming a metal layer including a double-layered structure on the semiconductor substrate, wherein the metal layer is formed by: forming a first metal layer on the semiconductor substrate by a first physical vapor deposition using a first target material containing tellurium, and forming a second metal layer over the first metal layer by a second physical vapor deposition, wherein the second metal layer is the tellurium-containing metal layer comprising a tellurium-containing titanium nitride layer; and heating the metal layer by a rapid thermal annealing process at a temperature ranging from about 200° C. to about 500° C. for a time length ranging from about 20 seconds to about 60 seconds, such that the first metal layer is silicidized at an interface with the semiconductor substrate and such that, during the heating, atoms of tellurium element in the second metal layer are diffused from the second metal layer to the silicidized interface to form a metal silicide layer on the semiconductor substrate, wherein the metal silicide layer includes at least the tellurium element.