Patent ID: 7345945

Claim:
A memory device having a circuit for controlling memory cells, the circuit comprising: a plurality (m) of sub word line driver circuits that are connected to a main word line and that are adapted to provide a sub word line enable signal to a selected one of m sub word lines in response to a main word line enable signal asserted on the main word line; a plurality (m×n) of local word line driver circuits, n of which are connected in parallel to each of the m sub word lines and that are adapted to provide a local word line enable signal to a selected one of m×n local word lines, in response to the sub word line enable signal so as to operate a plurality (l) of memory cells connected to the selected local word line; and a plurality (p) of plate line driver circuits, that are respectively connected in parallel, to the main word line, and that are adapted to provide a plate line enable signal to a plate line that is connected to at least n×l memory cells, in response to the main word line enable signal, the n×l memory cells being controlled by n local word line driver circuits connected to t selected sub word line, wherein the main word line enable signal, the sub word line enable signal and the local word line enable signal have a first voltage level at a power supply voltage VPP, wherein the first voltage level is higher by a determined amount than a second voltage level VDD, and the main word line enable signal has a ground voltage level.