Patent ID: 6965910

Claim:
A calculating unit, comprising: a first adder block with a first plurality of single adders and a pass determinator for determining, whether a carry passes fully through the first adder block; a second adder block downstream of the first adder block with a second plurality of single adders and a second pass determinator for determining, whether a carry passes fully through the second adder block; a third adder block downstream of the second adder block with a third plurality of single adders and a third pass determinator for determining, whether a carry passes fully through the third adder block; a clock generator for generating a clock, with which the first, the second and the third adder blocks are fed with input values to be added, wherein in a case where the first, the second and the third pass determinators determine that a carry does not pass fully through any of the adder blocks, the clock has a clock period, which is at least high enough that the carry passes almost fully through one of the adder blocks, and passes through at least part of the upstream adder block; and a controller for controlling the clock generator, so that in a case, where the first, the second or the third pass determinators determine that a carry passes fully through a respective adder block, the clock has a clock period which is sufficient that the carry passes fully through the respective adder block, passes almost fully through the adder block downstream of the respective adder block and passes through at least part of the adder block upstream of the respective adder block, and which is less than the time, which is necessary for the carry to pass through all of the adder blocks; and in a case where the first, the second or the third pass determinators determine that a carry passes fully through two adjacent adder blocks, the clock has a clock period, which is at least high enough that the carry fully passes through the two adjacent adder blocks, passes almost fully through the adder block downstream the adjacent adder blocks, and passes at least through part of the adder block upstream of the adjacent adder blocks.