Patent ID: 8257986

Claim:
A method for forming a testing wiring structure of a thin film transistor (TFT) array motherboard, comprising: step 1 of depositing a gate metallic layer on a base substrate and patterning the gate metallic layer so as to form gate lines in a pixel region and a gate layer metallic testing wiring in a testing wiring region, the gate layer metallic testing wiring being connected with a portion of the gate lines; step 2 of depositing an insulating layer on the base substrate after step 1; step 3 of forming an active layer in the pixel region on the base substrate after step 2, wherein the active layer is etched away so as not to be left in the testing wiring region; step 4 of depositing a source/drain metallic layer on the base substrate after step 3 and patterning the source/drain metallic layer so as to form a drain layer metallic testing wiring, the drain layer metallic testing wiring being connected with remaining portion of the gate lines and intersecting the gate layer metallic testing wiring; step 5 of depositing a passivation layer on the base substrate after step 4 and patterning the passivation layer so as to form via holes in the passivation layer for connection; step 6 of depositing a pixel electrode layer on the base substrate after step 5 and patterning the pixel electrode layer so as to form a pixel electrode in the pixel region and to form a pixel electrode layer testing wiring intersecting the gate layer metallic testing wiring, both ends of the pixel electrode layer metallic testing wiring being connected through the via holes in the passivation layer to the drain layer metal in the drain layer metallic testing wiring.