Patent ID: 8659334

Claim:
A method for tuning an integrated circuit (IC), comprising: determining a plurality of actual delay values for a plurality of paths in the IC; determining a plurality of estimated delay values from a simulation of the IC; determining a deviation between the plurality of estimated delay values and the actual delay values, and wherein the actual delay values include a delay between a clock signal and a data signal; determining whether one of the plurality of estimated delay values determined from simulation is greater than a corresponding one of the plurality of actual delay values; determining that a clock path is undercompensated as a result of determining that the one of the plurality of estimated delay values obtained from simulation is greater than the corresponding one of the plurality of actual delay values; and configuring a tuning circuit in the IC based on the deviation to adjust the clock path, wherein the configuring comprises selecting a test signal in a first mode of the IC, the selecting the test signal operable to output the deviation for storage in a memory, and wherein the configuring further comprises selecting an output of the memory in a second mode of the IC.