Patent ID: 7586329

Claim:
A circuit comprising: a first differential side and a second differential side for receiving an input signal pair at an input node pair to generate an output signal pair at an output node pair; a reset network for resetting the first differential side to a first voltage and for resetting the second differential side to a second voltage; and a capacitive network including a first capacitor node pair coupled to the output node pair and a second capacitor node pair coupled to the reset network, wherein the capacitive network includes: a first capacitor coupled between a first output node of the output node pair and a first node of the second capacitor node pair; a second capacitor coupled between a second output node of the output node pair and a second node of the second capacitor node pair; a third capacitor between the first output node and the second node of the second capacitor node pair; and a fourth capacitor between the second output node and the first node of the second capacitor node pair.