Patent ID: 8426894

Claim:
A pixel structure, comprising: a scan line having a first scan metal layer and a second scan metal layer; a data line interlaced with the scan line to form an interlacing region, wherein the data line comprises a first data metal segment and a second data metal layer, the first data metal segment and the interlacing region are spaced at a first distance, and the second data metal layer is disposed on the first data metal segment and across the interlacing region; an active element electrically coupled to the scan line and the data line, comprising: a gate electrode electrically connected to the scan line; an insulating layer partially formed on the gate electrode; a channel layer formed on the insulating layer above the gate electrode; and a source and a drain formed on the channel layer, wherein the source is coupled to the data line; a first passivation layer and a second passivation layer covering the active element, wherein a first contact hole exposing a region of the drain is formed between the first passivation layer and the second passivation layer, the first passivation layer and the second passivation layer cover sidewalls of the drain, and the region of the drain exposed by the first contact hole is not connected with the sidewalls of the drain ; and a pixel electrode disposed across the second passivation layer and coupled to the drain via the first contact hole.