Patent ID: 8165262

Claim:
A shift register comprising a plurality of shift register units coupled in series, each shift register unit comprising: an input end for receiving an input voltage; an output end for outputting an output voltage; a first node; a second node; an input circuit for controlling a signal transmission path between a first clock signal and the first node according to a voltage level of the input voltage; a pull-up circuit for providing the output voltage by controlling a signal transmission path between a second clock signal and the output node according to a voltage level of the first node, wherein the first and second clock signals periodically switch between a high voltage level and a low voltage level, and have opposite polarities in a same period; and a pull-down circuit comprising: a pull-down unit for maintaining the voltage level of the first node or the output end according to a voltage level of the second node, the pull-down unit comprising: a switch including: a first end coupled to the first node; a second end for receiving a second bias voltage; and a control end coupled to the second node; and a control unit for maintaining the voltage level of the second node according to a first bias voltage and the voltage level of the first node.