Patent ID: 7875526

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: forming bit lines in a cell array region, a core region, and a peripheral region of a semiconductor substrate; forming a first interlayer dielectric over the semiconductor substrate including the bit lines; forming storage node contact plugs in the first interlayer dielectric of the cell array region, and forming blocking patterns in the first interlayer dielectric around the bit lines of the core region and the peripheral region; forming a mold insulation layer on the first interlayer dielectric including the storage node contact plugs and the blocking patterns; forming capacitors in the mold insulation layer of the cell array region to come into contact with the storage node contact plugs; forming a second interlayer dielectric on the mold insulation layer including the capacitors; etching the second interlayer dielectric to define contact holes exposing the capacitors of the cell array region, and etching the second interlayer dielectric, the mold insulation layer, and the first dielectric layer to define contact holes exposing the bit lines of the core region and the peripheral region; and forming metal contact plugs in the contact holes exposing the capacitors and the contact holes exposing the bit lines.