Patent ID: 7307455

Claim:
A buffer comprising: a first capacitor comprising first and second capacitor terminals, the first capacitor being configured to receive an analog voltage on the first capacitor terminal, wherein the analog voltage is an input to the buffer; a first inverter having a first input terminal and a first output terminal, the first input terminal being connected to the second capacitor terminal of the first capacitor; a second capacitor having a third capacitor terminal connected to the first output terminal of the first inverter, and a fourth capacitor terminal; a second inverter having a second input terminal and a second output terminal, the second input terminal being connected to the fourth capacitor terminal of the second capacitor; a third capacitor having a fifth capacitor terminal connected to the second output terminal of the second inverter, and a sixth capacitor terminal; a first transistor connected to the sixth capacitor terminal of the third capacitor, the first transistor being configured to control a flow of a current from a first power source to a data line such that a buffer voltage is supplied to the data line, wherein the first transistor is configured to control the current in response to a voltage supplied from the third capacitor; and a second transistor connected to the data line and to the first terminal of the first capacitor.