Patent ID: 7666774

Claim:
A method for fabricating a CMOS structure comprising: forming over a first semiconductor substrate region having a first polarity within a semiconductor substrate a first gate dielectric and an overlying first gate electrode comprising a first metal containing material layer and a first silicon containing material layer located upon the first metal containing material layer; forming over a laterally separated second semiconductor substrate region having a second polarity different than the first polarity within the semiconductor substrate a second gate dielectric and an overlying second gate electrode laterally separated from the first gate electrode and comprising a second metal containing material layer of a composition that is different than the first metal containing material layer and a second silicon containing material layer located upon the second metal containing material layer, wherein the forming the first gate electrode and the forming the second gate electrode use a first precursor layer from which the first metal containing material layer is patterned and a second precursor layer from which the second metal containing material layer is patterned, the patterned first metal containing material layer and the patterned second metal containing material layer being separated by a gap over at least one of the first semiconductor substrate region and the second semiconductor substrate region; and forming into the first semiconductor substrate region and the second semiconductor substrate region a first pair of source/drain regions separated by the first gate electrode and a second pair of source/drain regions separated by the second gate electrode, where the first silicon containing material layer has a composition different than the first semiconductor substrate region and the second silicon containing material layer has a composition different than the second semiconductor substrate region.