Patent ID: 7405976

Claim:
A nonvolatile semiconductor memory that performs write/erase operation in units of data block containing a plurality of data segments, comprising: a memory cell array including a plurality of nonvolatile memory cells; a flag storage storing a flag provided for each address and indicating success/failure of the write/erase operation in association with each address of the plurality of data segments contained in the data block; an address selector selecting the address where the write/erase operation has failed according to the stored flag; a writing/erasing section performing the write/erase operation of the data segments on the nonvolatile memory cell located in the selected address; a verify section performing verify operation to verify success/failure of the data write/erase operation on the nonvolatile memory cell located in the selected address; and a flag update section updating the flag according to a result of the verify operation, wherein the address selector includes a next execution address calculator that checks a plurality of flags stored in the flag storage at substantially the same time in each data write/erase operation or verify operation and selects an address of a set flag from the plurality of flags, and wherein the next execution address calculator includes a first and a second next execution address calculator and a first determinator determining one from addresses selected by the first and the second next execution address calculators, the first next execution address calculator checking a plurality of flags corresponding to addresses of a first range and the second next execution address calculator checking a plurality of flags corresponding to addresses of a second range.