Patent ID: 7330381

Claim:
A memory integrated into a chip, comprising: a serial input/output; an integrated memory array; means for storing a most significant address allocated to the memory within an extended memory array addressable with an extended address comprising a least significant address and a most significant address; an extended address counter to store an extended address received at the serial input/output of the memory, and to apply the least significant address to the integrated memory array; means for comparing the most significant address of the extended address with the most significant address allocated to the memory; a central processing unit to execute a continuous read command, arranged to continuously read the integrated memory array and continuously increment or decrement the extended address counter during execution of the continuous read command, including when the most significant address of the extended address is different from the most significant address allocated to the memory, until execution of the continuous read command stops; and means for preventing data read from the integrated memory array from being applied to the serial input/output of the memory when the most significant address of the extended address is different from the most significant address allocated to the memory.