Patent ID: 8122195

Claim:
A computer program product for executing a prefetch data machine instruction, the computer program product comprising: a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit of a processor for performing a method comprising: the processor fetching the prefetch data machine instruction, the prefetch data machine instruction comprising an opcode field and a signed immediate field; and the processor executing the fetched prefetch data machine instruction adapted to either prefetch data to the cache or change access ownership of a cache line in the cache, the executing comprising: determining whether to perform a data prefetch cache action or a cache line ownership operation, the data prefetch cache action for prefetching a cache line of data from memory to the cache, the cache line ownership operation for changing cache access ownership of a line of data in the cache; determining an address of an operand in memory, wherein the address of the operand in memory is related to a memory address of the prefetch instruction being executed, wherein the determining the address comprises adding a halfword aligned sign extended value of the signed immediate field of the instruction to a program address of the prefetch data instruction being executed; and responsive to determining to perform the cache line ownership operation, performing a determined cache action on a cache line in the cache, the cache line associated with the determined address of the operand, the cache action comprising: responsive to the determined cache action being a release store access ownership action, changing access ownership of the cache line to a fetch access ownership, the store access ownership indicating that the processor intends to store to the cache line, the fetch access ownership indicating that the processor intends to fetch data from the cache line; and responsive to the determined cache action being a release fetch access ownership action, releasing access ownership, the released access ownership indicating that the processor does not intend to access to the cache line.