Patent ID: 8405148

Claim:
An integrated circuit structure having an LDMOS transistor and a CMOS transistor, comprising: a p-type substrate having a surface; an n-well implanted in the substrate, the n-well providing a CMOS n-well; a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region; and an LDMOS transistor including an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.