Patent ID: 7426668

Claim:
A method for testing at least one memory included in an integrated circuit using a test algorithm comprising one or more test steps described by algorithm instructions and configuration instructions, the method comprising: receiving the configuration and algorithm instructions delivered to an instruction memory of a memory testing portion of the integrated circuit; evaluating the received configuration instructions; determining that all algorithm instructions for one of the test steps have been received; evaluating the algorithm instructions for said one of the test steps following the determination that all of the algorithm instructions for said one of the test steps have been received, wherein the evaluating the algorithm instructions comprises addressing at least selected cells within the memory to which test data is to be applied to test the cells according to the at least one test algorithm, the act of addressing the selected cells being accomplished so as to address cells at the functional operating speed of the memory at least during certain memory access operations within the one of the one or more test steps; applying test data to the addressed cells; and analyzing output results read from the at least selected cells to which test data is applied to determine whether the test results match expected test results from the selected cells in response to the applied test data.