Patent ID: 7898308

Claim:
A memory device, comprising: a memory cell array configured to store data written to the array; and a clock signal generator circuit, comprising: a delay-locked loop (DLL) having a DLL adjustable delay and a phase detector, the DLL adjustable delay configured to provide a delayed clock signal in response to an input clock signal, the phase detector configured to compare first and second signals and to adjust the delay of the DLL adjustable delay based on the phase of the first and second signals, the delayed clock signal being used to provide a feedback clock signal; and a trimming circuit having first and second adjustable delay circuits and configured to delay the input clock signal and the feedback clock signal, respectively, by respective first and second adjustable delays to provide the first and second signals, respectively, to the phase detector, one of the first and second adjustable delay circuits being set at the intrinsic delay of the respective delay circuit and the other of the first and second adjustable delay circuits being set at a delay that is less than the maximum delay of the respective delay circuit.