Patent ID: 7268378

Claim:
A JFET comprising: a gate definition spacer adjacent to a corresponding trench wall surface, wherein said corresponding trench wall surface defines one side of a trench previously formed in a substrate, said trench comprising a bottom surface adjacent to said substrate, wherein said corresponding trench wall surface forms a boundary between said gate definition spacer and a source region adjacent to said gate definition spacer; and an implanted gate region formed below said bottom surface of said trench, wherein said implanted gate region comprises at least one rounded p-n junction interface formed at a corner of said implanted gate region due to annealing, wherein said implanted gate region extends laterally such that at least a segment of the rounded p-n junction interface closest to the trench wall surface is substantially co-planar with said corresponding trench wall surface and a channel width of a channel region for said JFET is approximately equal to a width of said source region between trench walls of said JFET.