Patent ID: 8324740

Claim:
A semiconductor device comprising: a semiconductor chip having electrode pads formed on a main surface; and a multilayer wiring board including a core substrate and wiring layers formed on a chip side of the core substrate, each of the wiring layers including a circuit pattern and an insulating layer, the multilayer wiring board having connection pads formed on a front surface, each of the connecting pads facing a corresponding one of the electrode pads; wherein the electrode pads include: first electrode pads including electrode pads respectively disposed in the vicinity of corners of the main surface of the semiconductor chip; and second electrode pads other than the first electrode pads, the connection pads include: first connection pads connected to the first electrode pads via bumps; and second connection pads connected to the second electrode pads via bumps, the multilayer wiring board includes: a first insulating region for supporting the first connection pads; and a second insulating region for supporting the second connection pads, the first insulating region is made of a thermoplastic resin and the second insulating region is made of a thermosetting resin, the wiring layers include: a first insulating layer constituting the first insulating region; and a second insulating layer constituting the second insulating region, and the first insulating layer is stacked on the second insulating layer, and a thickness of the first insulating layer is at least 1.5 times a thickness of a circuit pattern formed immediately beneath the first insulating layer in the multilayer wiring board, and is not more than one-half of a height of the bumps formed between the second electrode pads and the second connection pads.