Patent ID: 7263025

Claim:
A semiconductor memory device, comprising: an input buffer unit configured to buffer addresses, command signals, a clock signal and a clock enable signal which are externally input; a clock enable latch configured to latch the buffered clock enable signal and to generate an internal clock enable signal; a control signal generator configured to generate a first control signal for controlling the reception of the addresses and the command signals from the outside and a second control signal for controlling the generation of an internal clock signal, using the internal clock enable signal and the buffered clock signal; an internal clock generator configured to generate the internal clock signal using the buffered clock signal in response to the second control signal; and a latch unit configured to receive the buffered addresses and the command signals in synchronization with the internal clock signal and to generate internal addresses and the command signals, wherein the input buffer unit buffers the first control signal, while buffering the addresses and the command signals received from the outside in response to the first control signal, and the control signal generator generates the first control signal using the buffered clock enable signal, and generates the second control signal by allowing the first control signal and the buffered first control signal to be synchronized to the buffered clock signal.