Patent ID: 7049178

Claim:
A method for fabricating a semiconductor package, comprising: forming a plated copper pattern formed plate by: forming a first plated copper layer on upper and lower surfaces of a first insulation substrate; forming a pattern on first plated copper formed at the upper and lower surfaces of the first insulation substrate; and forming an opening by removing a central portion of the first insulation substrate with the first plated copper pattern formed thereon; forming an inner circuit pattern formed plate by: forming a second plated copper pattern on an upper surface or a lower surface of a second insulation substrate; forming a third plated copper layer on a second plated copper; and forming an opening by removing a central portion of the second insulation substrate with the second plated copper pattern and the third plated copper formed thereon; forming a lower circuit pattern formed by: forming a fourth plated copper pattern on an upper surface or a lower surface of a third insulation substrate; forming a fifth plated copper layer on the fourth plated copper; forming an opening by removing a central portion of the third insulation substrate with the fourth plated copper pattern and the fifth plated copper formed thereon; forming a bonding pad by forming a first nickel/gold plating layer around the opening of the inner circuit pattern formed plate and the lower circuit pattern formed plate; forming a laminated body by laminating the plated copper pattern formed plate onto the inner circuit pattern formed plate and the inner circuit pattern formed plate onto the lower circuit pattern formed plate using bonding sheets and sequentially attaching the formed plates; forming a through bore in the laminated body; forming a sixth plated copper layer on an inner circumferential surface of the through bore, the surface of the laminated body and the first nickel/gold plating layer; removing the sixth plated copper layer formed on the first nickel/gold plating layer of the laminated body; forming an outer circuit pattern by patterning a plated copper formed with the sixth plated copper layer formed thereon; and forming a second nickel/gold plating layer on the first nickel/gold plating layer of the laminated body and at a predetermined portion of the outer circuit pattern formed at an upper surface of the laminated body to form a bonding pad and a ball pad, respectively.