Patent ID: 7180106

Claim:
A semiconductor device comprising: a semiconductor substrate having an upper main surface and a lower main surface, said semiconductor substrate including: a drain layer of a first conductivity type formed in said upper main surface, a main base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface, an underpad base region of a second conductivity type selectively formed in said drain layer to be shallower than said drain layer and exposed to said upper main surface, said underpad base region being not coupled to said main base region and being deeper than a deepest portion of said main base region, and a source region of a first conductivity type selectively formed in said main base region to be shallower than said main base region and exposed to said upper main surface; a first main electrode connected to said main base region and said source region and not connected to said underpad base region; a gate electrode opposed to a channel region in said main base region interposed between said drain layer and said source region with a gate insulating film provided therebetween; a conductive gate pad opposed to an exposed surface of said underpad base region in said upper main surface with an insulating layer interposed therebetween and said conductive gate pad is connected to said gate electrode; and a second main electrode connected to said lower main surface.