Patent ID: 7460405

Claim:
A method for controlling a nonvolatile memory device, said nonvolatile memory device comprising: a semiconductor substrate; and a memory cell including: first and second impurity-diffused regions provided separately and spaced from each other at the surface of said semiconductor substrate; first to Nth control gates, where N is an even number of not smaller than four, being disposed in parallel with each other between said first impurity-diffused region and said second impurity-diffused region in this order on said semiconductor substrate; and first to Nth memory regions, respectively being provided between said semiconductor substrate and said first to said Nth control gates, said method comprising: (a) classifying said first to Nth control gates into a first control gate group composed of first to N/2th control gates arranged in a side of said first impurity-diffused region and a second control gate group composed of (N/2+1)th to Nth control gates arranged in a side of said second impurity-diffused region, and then applying a first higher voltage to said first impurity-diffused region and applying a first lower voltage to said second impurity-diffused region when a target control gate corresponding to a target memory region for injecting an electron is included in said first control gate group, and applying a second lower voltage to said first impurity-diffused region and applying a second higher voltage to said second impurity-diffused region when said target control gate is included in said second control gate group; and (b) applying a third higher voltage to said target control gate, while the condition of applying said voltages to said first and said second impurity-diffused regions is maintained, so that electron is injected to said target memory region that is corresponding to said target control gate, said third higher voltage being higher than voltages applied to other control gates.