Patent ID: 8198110

Claim:
A method of manufacturing a liquid crystal display (LCD) device comprising: forming an array of transistors in communication with a plurality of gate address lines and drain address lines on a substrate, the gate and drain address lines crossing each other to define a plurality of pixel regions; forming an insulating layer over the gate and drain address lines, the insulating layer having a thickness greater than about 1.0 μm and a dielectric constant less than about 5.0; forming a plurality of contact holes in the insulating layer; forming a plurality of pixel electrodes over the insulating layer in the pixel regions, each pixel electrode overlapping the gate and drain address lines and being electrically connected to one of the transistors through one of the contact holes in the insulating layer; forming a storage capacitor having a first electrode formed of one of the gate address lines and a second electrode formed at the same time as the drain address lines, the second electrode provided within one of the gate address lines and connected to the pixel electrode through another contact hole in the insulating layer, wherein an aperture ratio of the pixel regions is greater than about 65%, wherein a parasitic capacitance in areas where the pixel electrode overlap the gate and drain address lines is no greater than 0.01 pF, when a pitch of the pixel regions is about 150 μm.