Patent ID: 7457920

Claim:
A method of cache eviction for a multiple core central processing unit, said method comprising the steps of: said multiple core central processing unit sharing a last-level cache; loading a first cache line to a first cache; a first core among said multiple core central processing unit requesting a load in said first cache; wherein said first core has an identification number; marking said first cache line with said identification number of said first core; a cache load tracker keeping track of counts of cache lines loaded into said first cache for each individual core among said multiple core central processing unit; when a count of said first core's cache lines loaded into said first cache exceeds a first threshold, reducing all said counts of cache lines loaded into said first cache for each individual core, proportionally, such that said cache load tracker is not overflowed; said cache load tracker further measuring load rate and miss rate for each individual core; said cache load tracker recording said load rate and said miss rate on separate memory locations; said cache load tracker taking a running average over a first predetermined number of most recent misses; storing said identification number of said first core in a second predetermined number of first-in-first-out queues of first memory locations; when said first cache is full and all said counts of cache lines loaded into said first cache for each individual core are equal, evicting a least-recently-used cache line corresponding to any core not responsible for said load in said first cache; when said count of said first core's cache lines loaded into said first cache exceeds a second threshold or said miss rate for said first core exceeds a third threshold, evicting a least-recently-used cache line corresponding to a core with the largest said count of cache lines loaded into said first cache; and when said count of said first core's cache lines loaded into said first cache does not exceed said second threshold and said miss rate for said first core does not exceed said third threshold, evicting a least-recently-used cache line corresponding to a core with the lowest load rate.