Patent ID: 7143341

Claim:
A method of concurrent engineering, comprising the steps of: establishing a baseline electronic design; sending copies of the baseline electronic design to different design groups; modifying more than one of the baseline electronic designs sent to the design groups with engineering changes; and synchronizing the modified baselined electronic designs to produce a synchronized design; wherein: said synchronization comprises at least one of, determining if new Id is present in a design connectivity database DESCONN and not present in a layout connectivity database LAYCONN, and then processing a new object corresponding to the new Id added by a front end design tool, determining if a front end design tool created Id is present in LAYCONN and not present in DESCONN, and then processing an object deleted by the front end design tool, determining if a front end Id is present in each of LAYCONN, DESCONN, and in an occurrence delete section of LAYCONN, and then processing an object deleted by a layout tool, determining if a layout Id is present in an occurrence add section of LAYCONN, and then processing a new object added by the layout tool, determining if a layout id is present in an occurrence delete section of DESCONN and in the occurrence add section of LAYCONN, and then processing the Id added by the layout tool and then deleted by the front end tool, determining is a same instance id but different cell id is present in DESCONN, and then processing a modify/replace performed by the front end design tool, and determining each of a new pin net connection id in LAYCONN, a corresponding pin net connection id in the occurrence section of LAYCONN, a new pin net connection id in DESCONN corresponding to the pin net connection id in the occurrence section of LAYCONN, and then processing a simultaneous change of connectivity to a pin by the front end design tool and a back end design tool.