Patent ID: 8017457

Claim:
A method of manufacturing a semiconductor memory device comprising: forming a first selection transistor and a second selection transistor; forming a variable resistance element by sequentially laminating a first electrode that is connected to the first selection transistor, a variable resistance layer that contacts the first electrode, and a second electrode that contacts the variable resistance layer; and forming a capacitance element by sequentially laminating a third electrode that is connected to the second selection transistor, a dielectric layer that contacts the third electrode and consists of the same material as the variable resistance layer, and a fourth electrode that contacts the dielectric layer; wherein either one of the first electrode or the second electrode is formed with the same material as the third electrode and the fourth electrode, while the other one of the first electrode or the second electrode is formed with a different material than the third electrode and the fourth electrode, and the semiconductor memory device is formed on a same semiconductor substrate with a non-volatile semiconductor memory element and a volatile semiconductor memory element, the non-volatile semiconductor memory element including the first selection transistor and the variable resistance element that is connected to the first selection transistor, and the volatile semiconductor memory element including the second selection transistor and the capacitance element that is connected to the second selection transistor.