Patent ID: 7930465

Claim:
A semiconductor memory device comprising: at least one mode register set (MRS) input pad; at least one data input pad; and an operation mode determining circuit configured to generate an operation mode determining signal based on an MRS command input through the MRS input pad and a plurality of data signals input to the operation mode determining circuit through the at least one data input pad, wherein when the input MRS command corresponds to a predetermined MRS command and the plurality of input data signals include a predetermined combination, the operation mode determining circuit generates the operation mode determining signal for determining an operation mode of the semiconductor memory device that represents a number of memory cells simultaneously selected by a single address, the operation mode being determined by connecting predetermined data input pads in a specific state during mounting of the semiconductor memory device on a module PCB, an independent and variable number of the number of memory cells are simultaneously selected according to the operation mode, and the semiconductor memory device includes 2N number of data input pads (where N is a positive integer), and the operation mode of the semiconductor memory device is one of x1 to x2M operation modes (where M is a positive integer less than or equal to N).