Patent ID: 7990199

Claim:
A clock gater, comprising: a first circuit configured to receive a clock signal, the first circuit including a first subcircuit and a second subcircuit; and a latch configured to receive the clock signal, the latch being connected to the first circuit at each of a first node and a second node, the latch including a third subcircuit and a fourth subcircuit, wherein the first subcircuit and the third subcircuit are configured to pull the first node and the second node, respectively, to a common precharge voltage in response to a first state of the clock signal in order to pass the clock signal, and the second subcircuit and the fourth subcircuit are configured to pull the first node and the second node, respectively, to complementary voltages in response to a second state of the clock signal in order to pass the clock signal, the second state of the clock signal being different from the first state of the clock signal.