Patent ID: 7518945

Claim:
A control method for a read operation of a page buffer circuit of a flash memory device, comprising: selecting a bit line from a predetermined number of bit lines that are coupled to a sense node using a bit line select circuit of a given page buffer coupled to the predetermined number of bit lines and coupled to a Y-gate to connect the selected bit line to a sensing node, wherein the predetermined number of bit lines is four, the given page buffer being one of a plurality of page buffers and the Y-gate being one of a plurality of Y-gates, a total number of page buffers not being equal to a total number of the bit lines; separating the remaining bit lines other than the selected bit line from the sensing node using the bit line select circuit to apply a bit line bias voltage to the remaining bit lines; sensing a voltage of the sensing node using a sensing circuit of each of the plurality of page buffers to generate sensing data, the voltage corresponding to read data from the selected bit line; latching and inversing the sensing data using a latch circuit of each of the plurality of page buffers and outputting the latched inversed data; and outputting the latched inversed data to one of the Y-gates in response to an I/O control signal using a switch of each of the plurality of page buffers, wherein each of the predetermined bit lines is coupled to one of the plurality of page buffers through the corresponding switch.