Patent ID: 8514653

Claim:
A multi-layered memory device, comprising: at least one active circuit including a decoder; and at least one memory unit, each of the at least one memory unit being connected to at least one decoder, the at least one memory unit being separate from the at least one active circuit, and the at least one active circuit being arranged above or below the at least one memory unit, wherein the decoder includes a row decoder and a column decoder, the column decoder including a first column decoder circuit arranged at a first side of the at least one active circuit and a second column decoder circuit arranged at a second side of the at least one active circuit, and the row decoder including a first row decoder circuit arranged at a third side of the at least one active circuit and a second row decoder circuit arranged at a fourth side of the at least one active circuit, wherein the first and second sides are opposite to each other, and the third and fourth sides are opposite to each other.