Patent ID: 7736965

Claim:
A method of making a FinFET device structure, comprising: providing a semiconductor-on-insulator (SOI) substrate having a semiconductor layer on an insulating layer on a base layer; forming a cap layer on the SOI substrate; forming, on the insulating layer, first and second semiconductor fins with a first cap layer on the first fin and a second cap layer on the second fin; providing a first high-k dielectric layer across the first and the second cap layers and the first and second fins; providing a first metal layer onto the first high-k dielectric layer; providing a first semiconductor layer onto the first metal layer; removing the first semiconductor layer, the first metal layer, and the first high-k dielectric layer from the second cap layer, the second fin and from regions adjacent to the second fin; providing a second high-k dielectric layer onto the second cap layer, the second fin and a portion of the first metal layer; providing a second metal layer onto the second high-k dielectric layer, the second metal layer having a composition different than the first metal layer; providing a second semiconductor layer onto the second metal layer in a region above the second cap layer and into the regions adjacent to the second fin; removing the second semiconductor layer from the second metal layer in the region above the second cap layer, from adjoining regions and from the regions adjacent to the second fin; removing the second metal layer and the second high-k dielectric layer from a region above the first cap layer and from adjoining regions above the first semiconductor layer; removing the first metal layer, the first high-k dielectric layer, the first semiconductor layer, the second metal layer, the second high-k dielectric layer and the second semiconductor layer from regions above a plane containing top surfaces of the first and the second cap layers; forming first and second gates; forming respective source and drain regions within portions of the first and the second fins adjacent to the first and second gates, and then removing portions of the first and the second semiconductor layers, the first and the second high-k dielectric layers and the first and the second metal layers from a medial region between the first and the second fins.