Patent ID: 7129952

Claim:
A core logic chip, which works with a CPU and a main graphics accelerator in a computer system, comprising: a host controller electrically connected to said CPU for receiving a command from said CPU; an auxiliary graphing engine electrically connected to said host controller for receiving and processing said command; a transmission controller electrically connected to said auxiliary graphing engine for transmitting said command that is processed and outputted by said auxiliary graphing engine to said main graphics accelerator to be further processed; and wherein said auxiliary graphing engine, which is a 3D engine, includes: a demultiplexer receiving a graphing command from said host controller in response to a control signal; a transform and lighting unit receiving said graphing command from said demultiplexer and performing a converting and brightness-controlling operation in response to said graphing command; and a multiplexer selecting a signal from one of both, said demultiplexer and said transform and lighting unit, to be outputted to said transmission controller.