Patent ID: 8710566

Claim:
A semiconductor memory device comprising: a substrate comprising a diffusion layer; an array of dummy pillars formed on the diffusion layer and arranged in rows and columns, each of the dummy pillars extending upward from the diffusion layer and having a dummy upper region, a dummy middle region, and a dummy lower region, wherein each of the dummy upper region, the dummy middle region, and the dummy lower region are formed with a semiconductor material that is doped with a common first dopant type such that the dummy upper region is electrically connected with the diffusion layer through the dummy middle region and the dummy lower region via the semiconductor material that is doped with the common first dopant type, wherein the dummy upper region is further electrically connected to a metal strapping of the semiconductor memory device via a plug contact and a metal coupling, wherein the metal strapping extends parallel to a bit line that is parallel to the diffusion layer; wherein the columns of dummy pillars extend in a direction parallel to the bit line; a pillar substrate contact formed on the substrate, wherein the pillar substrate contact is doped with a second dopant type that is opposite to the first dopant type; and an array of active pillars formed on the diffusion layer and arranged in rows and columns, each of the active pillars extending upward from the diffusion layer and having an active first region, an active second region, and an active third region, and each of the active pillars being electrically connected with the diffusion layer; wherein the array of dummy pillars provide all electrical connections between the metal strapping and the diffusion layer within and around the array of active pillars.