Patent ID: 8230315

Claim:
An encoding apparatus comprising: a systematic encoder for encoding input data to generate information bits and parity bits, the information bits representing the input data, the parity bits providing redundancy for error correction; an information bit storage unit for storing the information bits generated by the systematic encoder; a parity bit storage unit for storing the parity bits generated by the systematic encoder; a bit transmission controller for controlling selective output of bits stored in the information bit storage unit and the parity bit storage unit; and a bit transmitter for transmitting the bits output from the information bit storage unit and the parity bit storage unit to a decoding apparatus under control of the bit transmission controller wherein the bit transmission controller causes at least two information bits generated consecutively by the systematic encoder to be output from the information storage unit for transmission to the decoding apparatus; wherein the bit transmission controller causes at least two information bits generated consecutively by the systematic encoder to be output from the information storage unit for transmission to the decoding apparatus; and wherein the bit transmission controller also causes parity bits generated simultaneously with the at least two information bits generated consecutively by the systematic encoder to be output from the information storage unit for transmission to the decoding apparatus.