Patent ID: 6851046

Claim:
A system for performing ternary branch instructions, comprising: an instruction word associated with branch conditions; a first branch target address encoded in the instruction word, the first branch target address having a first branch instruction set; a second branch target address encoded in the instruction word, the second branch target address having a second branch instruction set; a third branch target address encoded in the instruction word, the third branch target address having a third branch instruction set; a recombine target address encoded in the instruction word, the recombine target address having a recombine instruction set; and a processor configured to receive the instruction word, the processor further configured to evaluate the branch conditions associated with the instruction word and process a branch jump instruction, the processor further configured to select one of the branch target addresses in response to the branch jump condition, the processor further configured to jump to the selected branch target address and execute the branch instruction set at the selected branch target address, the processor further configured to implicitly jump to a recombine target address and execute the recombine instruction set after executing the selected branch instruction set.