Patent ID: 7535039

Claim:
A monolithic dual gate transistor structure, comprising: a semiconductor structure having defined therein first and second serial arranged, vertically aligned static induction transistors; said structure having a first pillar of width w and having first and second laterally extending shoulder portions at the base thereof; said structure having a second pillar of width W, where W>w, extending down from said first and second laterally extending shoulder portions and having third and fourth laterally extending shoulder portions at the base thereof; said first and second laterally extending shoulder portions having sections of a first gate; and said third and fourth laterally extending shoulder portions having sections of a second gate; and a plurality of contacts at various locations on said semiconductor structure for obtaining static induction transistor operation, wherein; said first static induction transistor is a normally off static induction transistor and said second static induction transistor is a normally on static induction transistor, wherein; said semiconductor structure includes a substrate having a plurality of epitaxial layers of predetermined conductivity types thereon; a top one of said layers defining a source for said normally off static induction transistor; said source being located at the top of said first pillar; a next adjacent said layer defining a channel region for said normally off static induction transistor; a next adjacent said layer defining a drift region for said normally off static induction transistor; a next adjacent said layer defining a source for said normally on static induction transistor; a next adjacent said layer defining a channel region for said normally on static induction transistor; and a next adjacent said layer defining a drift region for said normally off static induction transistor.