Patent ID: 7848132

Claim:
A memory device, comprising: a memory cell connecting to a local bit line, wherein the memory cell is composed of a pass transistor connecting to the local bit line and a storage node, and a ferroelectric capacitor connecting to the storage node and a plate line, for configuring a ferroelectric random access memory; a tunable gain amp serving as a local sense amp, wherein the tunable gain amp includes a local reset transistor for resetting the local bit line, a local pre-amp transistor whose source is connected to a local amp voltage for tuning gain and whose gate is connected to the local bit line for reading the memory cell, a local pre-set transistor for pre-setting a local pre-amp node which is connected to a drain of the local pre-amp transistor, a local main-amp transistor for reading the local pre-amp node, a local amp enable transistor connecting to the local main-amp transistor serially for enabling, and a local transfer gate for transferring a write data from a global bit line to the local bit line; a global sense amp connecting to the global bit line, wherein the global sense amp includes a read circuit, a latch circuit, a write circuit, and at least a select circuit, such that the read circuit reads the global bit line through the select circuit when reading, the latch circuit receives and stores an output from the read circuit or a pair of write data buses, and the write circuit receives an output from the latch circuit and drives the global bit line through the select circuit when writing; a local amp voltage generator for generating the local amp voltage which is tunable; a delay circuit as a locking signal generator for generating a delayed signal which disables a global amp enable transistor of the read circuit when reading, wherein the delayed signal is generated by an output from the latch circuit.