Patent ID: 7454646

Claim:
A device comprising: a clock divider and generator circuit configured to divide an input signal and to generate three clock signals, wherein the three clock signals comprise: a first clock signal having a rising edge and a falling edge; a second clock signal having a rising edge and a falling edge, wherein the rising edge of the second clock signal occurs concurrently with the falling edge of the first clock signal; and a third clock signal having a rising edge and a falling edge, wherein the rising edge of the third clock signal occurs concurrently with the falling edge of the second clock signal; a clock selection circuit coupled to an output of the clock divider circuit and configured to receive the three clock signals and to select one of the clock signals based on the phase relationship with the input signal; a delay-lock loop coupled to an output of the clock selection circuit configured to place the selected clock signal in phase with the input signal; and a feedback model circuit configured to provide a feedback signal to the clock selection circuit.