Patent ID: 7450648

Claim:
A ΔΣ modulator for applying ΔΣ modulation to a multi-bit signal comprising: order variation means adapted to vary effective orders increasing due to connection with a plurality of integrators, an effective order of said effective orders being a number of said integrators participating in the modulation of an input to said ΔΣ modulator; a first integrator of said plurality of said integrators, said first integrator including first fraction elimination means, a first integrator adder, and a first integrator delay circuit, said first fraction elimination means being adapted to eliminate a fraction remaining in said first integrator, said first integrator adder being adapted to receive an output from said first fraction elimination means, and said first integrator delay circuit being adapted to delay an output from said first integrator adder, said delayed output from said first integrator adder being provided to said first fraction elimination means; a first one of a plurality of multipliers adapted to generate a first multiplication output by multiplying said delayed output from said first integrator adder with a first control factor supplied from said order variation means; a second one of said plurality of multipliers adapted to generate a second multiplication output by multiplying said input with a second control factor supplied from said order variation means; a second integrator of said plurality of said integrators, said second integrator including second fraction elimination means, a second integrator adder, and a second integrator delay circuit, said second fraction elimination means being adapted to eliminate a fraction remaining in said second integrator, said second integrator adder being adapted to receive an output from said second fraction elimination means, and a second integrator delay circuit being adapted to delay an output from said second integrator adder, said delayed output from said second integrator adder being provided to said second fraction elimination means; a third one of said plurality of multipliers adapted to generate a third multiplication output by multiplying said delayed output from said second integrator adder with a third control factor supplied from said order variation means; and a fourth one of said plurality of multipliers adapted to generate a fourth multiplication output by multiplying said input with a fourth control factor supplied from said order variation means.