Patent ID: 8525557

Claim:
A selection circuit comprising: a plurality of selectable input circuits, each including enable elements arranged such that any one of the plurality of selectable input circuits is operable to be enabled independently of other input circuits of the plurality of input circuits; an output circuit comprising first and second output transistors; and an output enable circuit coupled between the output circuit and the plurality of input circuits such that the output enable circuit is operable to provide a switching current pathway through an enabled input circuit for charging and discharging voltage at a gate of a transistor of the output circuit; wherein a selectable input circuit of the plurality of selectable input circuits comprises: a stacked PMOS transistor pair and a stacked NMOS transistor pair; wherein: a gate of a first transistor in the stacked PMOS transistor pair and a gate of a first transistor in the stacked NMOS transistor pair are directly connected for receiving an input signal; the enable elements comprise a second transistor in the stacked PMOS transistor pair and a second transistor in the stacked NMOS transistor pair; a drain of a transistor in the stacked PMOS transistor pair and a gate of one of the first and second output transistors are directly connected; and a drain of a transistor in the stacked NMOS transistor pair and a gate of another of the first and second output transistors are directly connected.