Patent ID: 8195883

Claim:
A processor, comprising: a plurality of hardware processor cores, each comprising a respective higher-level cache; a hardware lower-level cache comprising a plurality of tag units each comprising a plurality of controllers, wherein each controller corresponds to a respective one of a plurality of cache banks configured to store data, and wherein the controllers are concurrently operable to access their respective cache banks; an interconnect network configured to convey data between the processor cores and the lower-level cache; wherein the controllers included in a given one of the tag units are configured to share access to an interconnect egress port coupled to the interconnect network and to generate multiple concurrent requests to convey data via the shared interconnect egress port, wherein each of the requests is destined for a corresponding one of the processor cores, and wherein a datapath width of the interconnect egress port is less than a combined width of the multiple concurrent requests; wherein the given tag unit is configured to arbitrate among the controllers for access to the shared interconnect egress port, such that the multiple concurrent requests are transmitted to corresponding cores serially rather than concurrently.