Patent ID: 7983066

Claim:
A passive matrix-addressable memory apparatus comprising: a plurality of first electrode lines horizontally arranged with respect to each other; a plurality of second electrode lines disposed crossing the plurality of first electrode lines to be horizontally arranged with respect to each other; a memory unit formed between the plurality of first electrode lines and the plurality of second electrode lines, and containing an electrically polarizable material exhibiting hysteresis; and a switch unit, wherein the switch unit comprises: first electrodes of a cantilever structure respectively formed between the memory unit and the plurality of first electrode lines to be electrically connected to the plurality of first electrode lines; and second electrodes electrically connected to the memory unit to be spaced apart from the first electrodes to face the first electrodes, the first electrodes and the second electrodes are electrically connected to each other when a voltage applied between the first electrodes and the second electrodes is equal to or greater than a predetermined voltage.