Patent ID: 7138714

Claim:
An integrated circuit comprising: a metal wiring level comprising metal lines within an intralevel dielectric, said metal lines having a first portion with a first width and a notch portion having a second width, wherein said first width is greater than said second width, and wherein said metal lines are separated from said intralevel dielectric by a metal diffusion barrier that is located underneath the metal lines and along sidewalls of the metal lines; and an interconnect wiring level atop said metal wiring level comprising a via interconnect within an interlevel dielectric, wherein said via interconnect is separated from said interlevel dielectric and in electrical contact to said metal lines of said metal wiring level through a via diffusion barrier that is located underneath the via interconnect and along sidewalls of thy via interconnect, wherein said via diffusion barrier contacts said metal diffusion barrier within said notch portion of said metal lines to form a continuous diffusion barrier between the via interconnect and the notch portion of the metal lines.