Patent ID: 7951665

Claim:
A method of manufacturing a semiconductor device, comprising: forming first and second connection plugs at a substantially identical level over a semiconductor substrate; forming a lower electrode covering an upper surface of the first connection plug and an electrode covering an upper surface of the second connection plug, the electrode being disposed apart from the lower electrode; forming a first insulation film covering the lower electrode and the electrode; selectively removing the first insulation film to expose a portion over a surface of the lower electrode, thereby forming a concave portion with an upper surface of the lower electrode being as a bottom surface, and with a lateral side of the first insulation film being as a side wall; forming a capacitor dielectric film for covering the upper surface of the lower electrode, the side wall of the first insulation film, and an upper surface of the first insulation film, from the bottom of the concave portion to an outside of the concave portion over the first insulation film formed with the concave portion; forming an upper electrode opposed to the lower electrode and in contact with the capacitor dielectric film so as to fill an inside of the concave portion; removing the first insulation film over the electrode selectively to form a connection hole after the forming the upper electrode; and forming a first conduction film so as to fill the connection hole and removing the first conduction film disposed to an outside of the connection hole, thereby forming a third connection plug to be connected with the second connection plug via the electrode.