Patent ID: 8090932

Claim:
A system-on-chip comprising: a processor; a control module; and a communication bus configured to provide a communication link between the processor and the control module, wherein the communication bus comprises a first plurality of data registers configured to store data, a plurality of address registers configured to respectively store addresses corresponding to selected ones of the first plurality of data registers, a second plurality of data registers configured to, while the processor is not reading data from the first plurality of data registers, respectively receive data from the selected ones of the first plurality of data registers, and a first selection module configured to, in response to a request for data from the processor corresponding to a first address, provide the data from one of the second plurality of data registers to the processor in response to the first address matching one of the addresses stored in the plurality of address registers, otherwise provide the data from one of the first plurality of data registers to the processor in response to the first address not matching one of the addresses stored in the plurality of address registers.