Patent ID: 7747971

Claim:
An integrated circuit design method for use with a circuit design that saves logical state during power shut off operation, wherein the circuit design includes state saving circuitry that has static retention behavior during power shut off operation circuit, wherein the state saving circuit includes: a first second state retention element that is powered off during power off operation of the state saving circuit; a second state retention element that is powered on during power off operation of the state saving circuit; and multiplex circuitry; wherein the first and second state retention elements and the multiplex circuitry are operatively coupled to cause, the first state retention element to save state during normal power on operation of the state saving circuit, and the second state retention element to save state of the first state retention element during power shut off operation of the state saving circuit, the method comprising: using a computer system to create in a storage device a model of the state saving circuit that includes a single edge triggered state saving element to correspond to the first and second state saving elements; creating in the storage device clock gate logic that suspends saving of new states by the single state saving element upon occurrence of a first state retention signal value in preparation for power shut off; providing in the storage device an indeterminate value signal having a value indicative of an unreliable saved state; creating in the storage device second selection logic responsive to a power control signal to provide an output selected between data output of the single state saving element and the provided indeterminate signal value; and creating in the storage device first selection logic responsive to the power control signal to select between the output of the second selection logic and a data signal and to provide the selected signal to a data input of the state saving element.