Patent ID: 8502593

Claim:
A circuit for debouncing an input signal having at least a first state and a second state, comprising: a first counter configured to respond to a clock signal while the input signal is in the first state, and that is maintained at a first reset value while the input signal is in the second state, the first counter producing a first output; a second counter configured to respond to the clock signal while the input signal is in the second state, and that is maintained at a second reset value while the input signal is in the first state, the second counter producing a second output; a first comparator configared to produce a third output indicative of whether the first output matches a first predetermined value; a second comparator configured to produce a fourth output indicative of whether the second output matches a second predetermined value; and a latch configured to produce a fifth output that is set to the first state when the first output matches the first predetermined value, and that is set to the second state when the second output matches the second predetermined value.