Patent ID: 7776711

Claim:
A method for manufacturing a transistor of a semiconductor memory device, comprising: forming a hard mask layer pattern on a semiconductor substrate over a plurality of active regions; forming a plurality of device isolation trenches in a device isolation region of the semiconductor substrate by using the hard mask layer pattern as an etching mask; forming a trench device isolation layer by filling up the device isolation trenches with an insulation layer; etching a part of the trench device isolation layer by a predetermined depth by use of a first mask layer pattern, to form a plurality of first and second trench device isolation layers arranged alternately with each other, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height; removing the hard mask layer pattern; etching the active regions by a predetermined depth by use of a second mask layer pattern, to form a recess region in each of the active regions, the recess region having a stepped profile at a boundary portion thereof and a height higher than that of the second trench device isolation layers to form an upwardly protruded portion between two adjacent second trench device isolation layers; and forming a plurality gate insulation layers and plurality of gate stacks on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.