Patent ID: 8171270

Claim:
A processor comprising: an event monitoring logic to monitor and signal an occurrence of one or more events corresponding to architecturally defined scenarios in one channel of one or more channels, wherein the one or more channels are to correspond to a set of architecture state; a first storage unit to store data corresponding an event comprising a channel identifier and a scenario identifier; a first logic circuitry to update the first storage unit in response to data stored in the channel; and a second logic circuitry to cause invocation of a yield event routine, based on a service routine data block (SRDB) stored in a second storage unit, in response to the occurrence of the event, the second storage unit coupled to the processor and to store the SRDB accessed by a service routine base pointer (SRDS) and a service routine offset value (SRDBP) obtained from the channel, wherein the SRDB is to comprise: a service routine stack pointer (SRSP) and a service routine stack segment (SRSS) to identify a yield event stack to switch stacks across context switches without a need for saving and restoring the SRDB; and a service routine instruction pointer (SRIP) and a service routine code segment (SRCS) to identify the yield event routine to transfer control across context switches without a need for saving and restoring the SRDB.