Patent ID: 7299443

Claim:
A method for designing a wiring connecting section of a first wiring and a second wiring formed in mutually different wiring layers above a semiconductor substrate, said method comprising: a stack via number determination step for determining the number of stack vias required for connecting said first wiring and said second wiring based on an amount of a current flowing between said first wiring and said second wiring; a virtual wiring number determination step for determining the number of virtual wirings based on the number of said stack vias; a virtual wiring arrangement step for arranging a plurality of said virtual wirings in a forming region of said second wiring above said first wiring; a stack via creation step for creating a plurality of said stack vias in portions where said first wiring and said plurality of virtual wirings cross with each other; a virtual wiring deletion step for deleting said virtual wirings; and a second wiring creation step for creating said second wiring.