Patent ID: 7716542

Claim:
A memory built-in self-test circuit, comprising: an instruction decoder for receiving a control signal; and a built-in self-test controller, coupled with the instruction decoder for receiving the control signal; wherein if the control signal is in a self-test mode, the instruction decoder decodes a self-test instruction sent from an auto-testing equipment and the built-in self-test controller tests a memory according to the decoded result of the self-test instruction; if the control signal is in an output mode, the instruction decoder suspends its operation and the built-in self-test controller outputs the testing record of the memory; if the control signal is in a normal mode, the instruction decoder suspends its operation and the built-in self-test controller delivers a testing signal generated by an external functional circuit to the memory, wherein the functional circuit controls a reading operation or a writing operation of the memory with the testing signal.