Patent ID: 7421050

Claim:
A clock and data recovery circuit for recovery of an inputted analog signal, said circuit comprising: at least two data detectors to receive in parallel said inputted analog signal, each of said detectors to detect samples of the analog signal and to produce a data detector output; a phase detector for each of said data detectors, said phase detector to receive as input the data detector output and to produce a phase detector output; a first stage decimation filter for combining said phase detector outputs; a first stage downsampling circuit to downsample the output of the first stage decimation filter; a series of at least one additional stage decimation filter in combination with an additional downsampling circuit to further downsample the output of the first stage downsampling circuit; a digital loop filter to filter the output of said series to produce a filtered signal; a phase selection circuit to use the filtered signal to produce at least two recovered sampling clock signals where each said recovered sampling clock signal is inputted to only one data detector.