Patent ID: 7483334

Claim:
An input signal path for a memory receiving commands and addresses through input-output signal lines, comprising: a command path having a data latch coupled to the input signal lines, the data latch of the command path configured to latch input signals responsive to a command latch signal; an address path having a plurality of data latches coupled to the input signal lines, the data latches of the address path configured to latch external input signals applied to the input-output signal lines responsive to a respective address latch signal; and clock logic coupled to the data latches of the command and address paths, the clock logic configured to generate the command latch signal for the data latch of the command path to latch commands from the input signals and further configured to generate respective address latch signals for the data latches of the address path to interleave latching of addresses from the external input signals applied to the input-output signal lines.