Patent ID: 7408206

Claim:
An integrated circuit chip, comprising: an silicon on insulator substrate comprising a bulk silicon substrate, a buried oxide layer on a top surface of said bulk silicon substrate, and a silicon layer on a top surface of said buried oxide layer, said buried oxide layer electrically isolating said silicon layer from said bulk silicon substrate; a region of shallow trench isolation formed in said silicon layer and extending from said top surface of said buried oxide layer to a top surface of said silicon layer; a charge dissipation guard ring comprising a continuous polysilicon ring disposed adjacent to sides of said integrated circuit chip and at least a continuous band of a metal contact ring aligned over and in direct physical and electrical contact with a corresponding continuous band of a top surface of said polysilicon ring, of said metal contact ring in said polysilicon ring extending from a top surface of said region of shallow trench isolation, through said shallow trench isolation and through said buried oxide layer in direct physical and electrical contact with said bulk silicon substrate, said polysilicon ring electrically isolated from said silicon layer by said region of shallow trench isolation; and one or more charge dissipation pedestals, each charge dissipation pedestal of said one or more charge dissipation pedestals comprising a stack of wire segments from a lowermost to a higher most wire segment of each wiring level of said integrated circuit chip, a lowermost wire segment of said stack of wire segments in direct physical and electrical contact with said metal contact ring, each wire segment of said stack of wire segments in direct physical and electrical contact with a lower and a higher wire segment.