Patent ID: 7340563

Claim:
A data transmission device comprising: a local memory including a driver, a memory cache table composed of a DRAM memory, a standard 2.5″ hard disk, an FPGA or ASIC for managing the memory in the memory cache table, a control CPU for controlling the FPGA or ASIC, said control CPU being controlled by the driver, a disk interface for connecting to an external computer, and a backup battery, all of the local memory, the memory cache table, the standard 2.5″ hard disk, the control CPU, the FPGA or ASIC, the disk interface, and the backup battery being packed as a unit in the same external configuration and size as a standard 3.5″ hard disk, wherein the FPGA or ASIC works with the driver via the CPU to sample an access frequency per unit time of date accessed by the connected external computer, then automatically learns importance of the accessed data based on the sampled frequency, and save data having high importance in the memory cache table in real time so as to allow for high-speed, efficient access to the data from the external computer.