Patent ID: 8344436

Claim:
A semiconductor construction, comprising: a semiconductor material having a base and a plurality of pedestals extending upwardly from the base, the pedestals comprising active regions joining the base through narrow stems; a dielectric material over the base; the dielectric material being between the active regions and the base, and having openings therein through which the stems pass; wordlines extending across the active regions, the wordlines being paired across the individual of the active regions, segments of the wordlines over the active regions corresponding to transistor gates, both individual transistor gates of the paired transistor gates having portions directly over the dielectric material and having other portions directly over the openings; conductively-doped source/drain regions within the active regions, three source/drain regions being within individual active regions, one of the three source/drain regions of an individual active region being a shared source/drain region between the paired wordlines associated with the individual active region, the remaining two of the three source/drain regions being outer source/drain regions on opposing sides of the wordlines from the shared source/drain region; capacitors in electrical connection with the outer source/drain regions; and bitlines in electrical connection with the shared source/drain regions.