Patent ID: 7394707

Claim:
An apparatus comprising: a first circuit having a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals, wherein each of said plurality of first multiplexers presents an output to each of said one or more second multiplexers; a second circuit configured to generate a second intermediate enable signal in response to (i) said first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal; and a third circuit configured to generate a third intermediate enable signal in response to (i) said second intermediate enable signal, (ii) a control input signal and (iii) a third select signal, wherein said third intermediate enable signal is configured to control a read operation of a memory.