Patent ID: 7647566

Claim:
A method for designing an integrated circuit chip being executed in a computer system, the method comprising the steps of: obtaining circuit layout data of the integrated circuit chip by the computer system; finding a first via for electrically connecting two metal layers to each other by the computer system; creating a new second via adjacent to the first via in the circuit layout data, the second via electrically connecting the two metal layers to each other; creating a third via, a fourth via, and a fifth via, which are adjacent to the first via, in the circuit layout data, wherein the second via faces the fourth via, and the third via faces the fifth via; judging whether each of the second to fifth vias changes an original circuit connection relationship of the integrated circuit chip by the computer system; keeping each of the second to fifth vias, which does not change the original circuit connection relationship, in the circuit layout data at the computer system; and deleting each of the second to fifth vias, which changes the original circuit connection relationship, from the circuit layout data by the computer system.