Patent ID: 8645959

Claim:
An apparatus comprising: a single register to store a plurality of bits corresponding to any of a plurality of processing elements, any of the plurality of bits in the register to be accessible by any of the plurality of processing elements directly, wherein a start message is to be sent to all of the plurality of processing elements for which a bit has been assigned in the register, wherein the start message is to indicate a position of the bit in the register to which the plurality of the processing elements with an assigned bit correspond and wherein the start message is to indicate to each of the plurality of processing elements, with an assigned bit in the register, to start its respective task, wherein a completion message is to be transmitted in response to completion of one or more of a plurality of tasks and the plurality of processing elements are to update one or more of the plurality of bits based on the position of the bit indicated by the start message and after completing one or more of the plurality of tasks, wherein the plurality of processing elements are to be assigned the plurality of tasks concurrently and cannot be assigned subsequent tasks until the last of the plurality of processing elements have updated the plurality of bits.