Patent ID: 7932736

Claim:
An integrated circuit comprising: a plurality of input/output (I/O) circuits; a plurality of pads, each pad coupled to a corresponding one of the plurality of I/O circuits; a plurality of test access circuits each coupled to a corresponding one of the plurality of pads and to a corresponding one of the plurality of I/O circuits; a common connection node coupled to each of the plurality of test access circuits, wherein the common connection node, plurality of test access circuits and plurality of pads are configured so there is a test access circuit between each pad and the common connection node, and two access circuits and the common connection node between each one of the plurality of pads and every other one of the plurality of pads; and a controller coupled to each of the plurality of test access circuits, the controller configured to send control signals to each of the plurality of test access circuits to selectively enable one or more of the test access circuits, wherein the controller is configured to generate the control signals in a manner that individually enables test access circuits to connect the corresponding I/O circuit to a test signal applied to one of the plurality of pads (primary pad), thereby enabling testing each of the plurality of I/O circuits by directly probing only the primary pad and not directly applying a test probe to any of the other of the plurality of pads (secondary pads).