Patent ID: 8046503

Claim:
A Direct Memory Access (DMA) controller of a system on chip, comprising: a first interface structured to interface with a local memory of the system on chip, the first interface coupled to the local memory to pass first data to and from the local memory, said first data associated with an indication to the local memory of an address in the local memory; a second interface structured to interface with a central processing unit of the system on chip, said DMA controller operable to perform, in response to a command from the central processing unit, operations for writing and reading second data in the local memory via the first interface; a third interface structured to interface with a data processing module of the system on chip, said third interface being at least one of: operable to transmit to the data processing module third data read via the first interface in the local memory, the transmission from said third interface based at least in part on receipt of at least one first command from the central processing unit, and the transmission not being associated with a prior indication to the data processing module, by the DMA controller, of a first storage address of said third data; and operable to receive fourth data from the data processing module and further operable to transmit to the local memory via the first interface the received fourth data, said reception of the fourth data based at least in part on receipt of at least one second command from the central processing unit, and the reception not being associated with a prior indication to the data processing module, by the DMA controller, of a second storage address of said fourth data; and a fourth interface structured to interface with a memory external to the system on chip, the DMA controller operable to perform operations to write and read fifth data in the external memory via the fourth interface.