Patent ID: 7030317

Claim:
An electronic assembly with stacked integrated circuit (IC) die, comprising: a base substrate including an electrically conductive first trace and an electrically conductive second trace formed on a first surface of the base substrate; a first IC die having a first side and a second side opposite the first side, wherein the first side of the first IC die includes an electrically conductive first contact and the second side of the first IC die includes an electrically conductive second contact, and wherein the second contact of the first IC die is coupled to the second trace; a second IC die having a first side and a second side opposite the first side, wherein the first side of the second IC die includes another electrically conductive first contact and the second side of the second IC die includes another electrically conductive second contact; a signal routing first interconnect partially positioned between the first and second IC dies; and a signal routing second interconnect partially positioned adjacent the first side of the second IC die, wherein the first interconnect couples the first contact of the first IC die to the first trace and the second contact of the second IC die to the second trace, and wherein the first and second interconnects in combination couple the first contact of the second IC die to the first trace.