Patent ID: 7202521

Claim:
A silicon-oxide-nitride-oxide-silicon (SONOS) memory device, comprising: a semiconductor layer including source and drain regions and a channel region; an upper stack structure directly disposed on a first side of the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device; and a lower stack structure directly disposed on a second side of the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device, wherein: the upper stack structure includes an upper tunneling layer, an upper memory node layer, an upper insulating layer, and an upper gate electrode that are sequentially stacked on each other over the channel region of the semiconductor layer, the lower stack structure includes a lower tunneling layer, a lower memory node layer, a lower insulating layer, and a lower gate electrode that are sequentially and directly stacked on each other over the channel region of the semiconductor layer, and the first side is opposite to the second side of the semiconductor layer.