Patent ID: 7489001

Claim:
A semiconductor device comprising: a memory array having a plurality of magnetic memory cells arranged in a matrix, in which each of said magnetic memory cells includes a storage section whose resistance values are changed in accordance with the level of storage data that is written in response to an applied magnetic field generated by first and second data write current; a plurality of first write current lines arranged along a first direction and passing said first data write current therethrough; a plurality of second write current lines arranged along a second direction crossing said first direction and passing said second data write current therethrough; a write current supply circuit disposed at one end of said plurality of first write current lines, wherein the other end of said plurality of first write current lines is electrically connected to a predetermined voltage that is different from a current source voltage of said write current supply circuit in a connected region arranged across the memory array from said write current supply circuit, and each of said first write current lines is configured to externally apply a magnetic field induced by said first data write current to a magnetic tunnel junction of each magnetic memory cell.