Patent ID: 8912821

Claim:
A logic cell, comprising: (a) a spin diode having a non-magnetic semiconductor layer and a magnetic semiconductor layer disposed on the non-magnetic semiconductor layer, wherein the spin diode is configured such that under a forward bias, when a magnetic field applied to the spin diode is less than a threshold value, the spin diode is in a conductive state in which electric current flows through the spin diode, and when the magnetic field applied to the spin diode is greater than the threshold value, the spin diode is in a resistive state in which the electric current flowing through the spin diode is substantially reduced; (b) a voltage supply wire oriented along a first direction parallel to the magnetic semiconductor layer of the spin diode and positioned on the magnetic semiconductor layer for connecting the magnetic semiconductor layer to a voltage supply V DD ; (c) a first control wire for receiving a first input current and a second control wire for receiving a second input current, wherein the first control wire and the second control wire are oriented in parallel along the first direction and positioned on two sides of the spin diode and the voltage supply wire, such that when the first input current flows through the first control wire, the first input current induces a first magnetic field B 1 greater than the threshold value in the spin diode, and when the second input current flows through the second control wire, the second input current induces a second magnetic field B 2 greater than the threshold value in the spin diode; and (d) an output wire oriented along the first direction and positioned on the non-magnetic semiconductor layer of the spin diode for outputting a logic “0” or “1” responsive to the first input current and the second input current.