Patent ID: 7839197

Claim:
A level shift circuit, comprising: an input stage having two nodes, responsive to an input signal to turn on a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon in a transition state, and lower the current in a steady state to reduce power consumption; and an output stage coupled to the first and second nodes, operative to assert an output signal according to the voltages on the first and second nodes; wherein the input stage includes: a first switch operative to electrically connect the second node to a first voltage source when the voltage on the first node is at a first level, and disconnect the second node from the first voltage source when the voltage on the first node is at a second level; a second switch operative to electrically connect the first node to the first voltage source when the voltage on the second node is at the first level, and disconnect the first node from the first voltage source when the voltage on the second node is at the second level; a third switch operative to electrically connect the first node to a second voltage source and thereby turn on a first current as the large current when the input signal is at a third level, and disconnect the first node from the second voltage source when the input voltage is at a fourth level; a fourth switch operative to electrically connect the second node to the second voltage source and thereby turn on a second current as the large current when the input signal is at the fourth level, and disconnect the second node from the second voltage source when the input voltage is at the third level; and a current control circuit operative to lower the first current or the second current in the steady state, the current control circuit including: a first capacitor connected between the third switch and the second voltage source, being quickly charged by the first current when the input signal transits to the third level; a first small current source connected in parallel with the first capacitor, to limit the first current to be small when the first capacitor is saturated and to discharge the first capacitor when the input signal transits to the fourth level; a second capacitor connected between the fourth switch and the second voltage source, being quickly charged by the second current when the input signal transits to the fourth level; and a second small current source connected in parallel with the second capacitor, to limit the second current to be small when the second capacitor is saturated and to discharge the second capacitor when the input signal transits to the third level.