Patent ID: 7792232

Claim:
An apparatus comprising: a sampler, using a plurality of sampling clocks, to sample a first set of data of an incoming data signal to determine a first phase shift indicator and to sample a second set of data of the incoming data signal to determine a second phase shift indicator, wherein the first set of data is a data bit-(N) and a data bit-(N+1), and the second set of data is a data bit-(N+1) and a data bit-(N+2); a data recovery circuit (DRC), and not an alignment circuit and a proportional filter circuit, the DRC including control logic to determine a phase control signal based on the first and the second phase shift indicators alone and not in combination with a separate reference clock, wherein the DRC operates at about a rate half of the incoming data signal; and a phase interpolator to receive the phase control signal and adjust a phase of the sampling clocks, wherein the phase interpolator provides the plurality of sampling clocks.