Patent ID: 7838944

Claim:
A plurality of non-volatile programmable memory cells formed in a semiconductor substrate of a first conductivity type and comprising: a plurality of non-volatile MOS transistors of a second conductivity type formed in a first semiconductor region of the first conductivity type and coupled between a common first power supply potential and an individual output node; a plurality of volatile MOS transistors of the first conductivity type formed in a semiconductor region of the second conductivity type, each volatile MOS transistor of the first conductivity type coupled between a different one of the individual output nodes and a common second power supply potential; and a plurality of volatile MOS switch transistors of the second conductivity type formed in a second semiconductor region of the first conductivity type, each of the plurality of MOS switch transistors coupled to a different one of the individual output nodes; wherein the first and second semiconductor regions of the first conductivity type are electrically isolated from one another.