Patent ID: 8464032

Claim:
A microprocessor integrated circuit, comprising: first and second processors, wherein the first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor; and microcode, wherein the second processor is configured to execute the microcode in response to a reset of the second processor, wherein the microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor, wherein the microcode is configured to selectively output the debug information on a first or second external bus based on a flag, wherein the first external bus is an architectural bus of the second processor to which a memory external to the microprocessor integrated circuit is coupled, wherein the second external bus is coupled to the first processor, wherein the second external bus is non-architectural to the second processor and is distinct from the architectural bus of the second processor.