Patent ID: 8214170

Claim:
A method for test pattern compression, comprising: generating a first test pattern, by a hardware test pattern module, the first test pattern comprising a plurality of bits, multiple bits of the plurality of bits having an associated unique bit position and a bit value, wherein the bit value comprises one of a high value, a low value, and a don't-care value; identifying, by a hardware bit identification module, bits comprising a don't-care bit value in the first test pattern; replacing, by a test pattern module, the identified bit values in the first test pattern with random bit values, comprising either the high value or the low value, to generate a second test pattern; determining a fault coverage level of the second test pattern; in the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, determining, by a fault simulation module, whether one or more of the bit positions in the second test pattern corresponding to the replaced identified bit values detected at least one fault; and for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, exchanging, by the test pattern module, the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern.