Patent ID: 7167967

Claim:
A memory module standardized and connectable to a computer body generating a predetermined number of address signals, a plurality of select signals representing a select or unselected state of each of memory spaces having a capacity corresponding to the predetermined number of the address signals, a pulse-shaped clock signal, and a plurality of clock enable signals representing a valid or invalid state of an input of the clock signal for each of the plurality of the memory spaces, the memory module comprising: a memory receiving a memory select signal representing a select or unselected state and a plurality of address signals greater than the predetermined number of the address signals, and permitting data corresponding the plurality of the address signals to be accessible when the memory select signal represents a selected state; the memory receiving the clock signal and a memory clock enable signal representing a valid or invalid state of an input of the clock signal, and operating according to the clock signal when the clock enable signal is valid; a memory circuit receiving the predetermined number of the address signals and a plurality of select signals from the computer body, generating the memory select signal and an additional address signal added to the predetermined number of the address signals according to the inputted select signals, and providing the generated memory select signal, the generated additional address signal, and the predetermined number of the inputted address signals to the memory to permit the computer body to access data corresponding thereto; and the memory circuit receiving the clock signal and the plurality of the clock enable signals, generating the memory clock enable signal according to the plurality of the inputted clock enable signals, and providing the memory clock enable signal and the inputted clock signal to the memory.