Patent ID: 8041894

Claim:
A multi-level cache hierarchy, comprising: a set of L1 caches associated with one or more processor cores; and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores, wherein each of the set of L1 caches is virtual-address-indexed having a corresponding directory virtual-address-indexed and real-address-tagged, and wherein each of the set of L2 caches is real-address-indexed having a corresponding directory that is real-address-indexed and real-address tagged, wherein the L1 directory includes control bits for valid and exclusive, and the L2 directory includes exactly one value of synonym bits that applies to the set of L1 caches underneath a L2 cache having the L2 directory, and wherein the L2 directory includes L2 control bits for valid and exclusive, and for each L1 cache of the set of L1 caches underneath L2 cache, L1 control bits for valid and exclusive, wherein the L1 exclusive bits are for L1 caches that are directly stored-to, wherein the valid and exclusive bits are configured to maintain mp coherency.