Patent ID: 8341486

Claim:
An apparatus comprising: an integrated circuit (IC) receiver comprising: an iterative decoder including: a plurality of variable node processors each to receive a channel input and at least one of a plurality of check node values and to calculate a variable node value; a shuffle unit coupled to receive a variable node value from each of the plurality of variable node processors and to provide the variable node value to at least one of a plurality of check node processors coupled to the shuffle unit; the plurality of check node processors each to receive at least one variable node value and to calculate a check node value including a parity value and a magnitude value, wherein each of the plurality of check node processors is to provide a first output having a first value if the parity value is of a false parity; an adder coupled to the plurality of check node processors to receive the first output from each of the plurality of check node processors and to generate a false parity sum; and a controller coupled to the adder to receive the false parity sum and to control iterative decoding on a current block of the channel input based at least in part on the false parity sum.