Patent ID: 6867461

Claim:
An ESD protection circuit applied to an IC with power-down-mode operation, comprising: an input circuit, which comprises: an input pad; an input PMOS, wherein the drain of said input PMOS is connected to said input pad; an input NMOS, wherein the drain of said input NMOS is connected to said input pad; and a first internal circuit connected to said input pad through at least one resistor; an output circuit, which comprises: an output pad; an output PMOS, wherein the drain of said output PMOS is connected to said output pad; an output NMOS, wherein the drain of said output NMOS is connected to said output pad; and a second internal circuit connected to the gate of said PMOS and the gate of said NMOS; a VDD power line connected and providing VDD voltage to said first internal circuit and said second internal circuits; a VSS power line connected and providing VSS voltage to said first internal circuit and said second internal circuits, said VSS power line still connected to the source and the gate of said input NMOS and the source of said output NMOS; an ESD bus line connected to the source and the gate of said input PMOS; a first ESD clamp circuit connected between said VSS power line and said ESD bus line; a second clamp circuit connected between said VDD power line and said VSS power line; a first diode forward connected between said VDD power line and said ESD bus line to avoid leakage current induced from said input pad to said VDD power line, and to avoid positive voltage at said input pad charging to said VDD power line through said input PMOS; a second diode forward connected between said VDD power line and the source of said output PMOS to avoid leakage current induced from said output pad to said VDD power line, and to avoid positive voltage at said output pad charging to said VDD power line through said output PMOS; and a third diode, wherein the negative terminal of said third diode is connected to said ESD bus line and the coupled node connected to the positive terminal of said third diode is selected from said output pad and the source of said output PMOS.