Patent ID: 7847573

Claim:
A test apparatus for testing a device under test, comprising: a plurality of signal supply sections that output test signals at different timing from each other; a connection section that connects lines of individual wiring transmitting the test signals respectively outputted from the signal supply sections with each other, connects the connected lines of individual wiring to an input terminal of the device under test, and inputs the test signals to the input terminal after superposing the test signals; a plurality of waveform shapers provided for the signal supply sections respectively, each of the waveform shapers generating a test signal to be supplied to a corresponding one of the signal supply sections, based on given pattern data; and a plurality of pattern generating sections provided for the waveform shapers respectively, each of the pattern generating sections supplying the pattern data to a corresponding one of the waveform shapers, wherein each of the pattern generating sections includes a plurality of pattern generating circuits that generate the pattern data to be given to a corresponding one of the waveform shapers by an interleave technique.