Patent ID: 7880506

Claim:
A logic circuit latch for switching between a transparent state in which a logical output of the latch follows a logical input signal and a closed state in which the logical output is latched, the latch comprising: an input stage for receiving the logical input signal; and a pair of differential amplifiers, each having an input operatively coupled to the input stage of the latch, and at least one of the differential amplifiers having an output arranged to supply the logical output of the latch; wherein each of the differential amplifiers comprises a transistor connected as a load, and an output of each of the differential amplifiers is coupled to bias the load transistor of the other differential amplifier; so as, if the latch switches from the transparent state to the closed state while the logical input signal is transitioning between logical levels, to drive up the logical output of the latch if the logical input signal transitions from a first to a second logical level, and to drive down the logical output of the latch if the input signal transitions from the second to the first logical level.