Patent ID: 8492854

Claim:
A structure comprising: at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack, the gate stack and raised source drain structures being disposed on a surface of a semiconductor material; a layer of field dielectric overlying the gate stack and raised source drain structures; and first contact metal and second contact metal extending through the layer of field dielectric, the first contact metal terminating in a first trench formed through a top surface of a first raised source drain structure, the second contact metal terminating in a second trench formed through a top surface of a second raised source drain structure, each trench comprising silicide formed on sidewalls and a bottom surface of at least a portion of the trench and each trench extending completely through a respective one of the raised source drain structures; where the contact metal is comprised of a metal selected to exhibit one of tensile stress or compressive stress; and where the layer of field dielectric is comprised of a material selected to exhibit tensile stress when the selected contact metal exhibits tensile stress, and where the layer of field dielectric is comprised of a material selected to exhibit compressive stress when the contact metal exhibits compressive stress.