Patent ID: 7373630

Claim:
A method of designing a structured ASIC to be functionally equivalent to a programmed FPGA comprising: producing a design for the programmed FPGA, said programmed FPGA design including a plurality of programmed look-up tables; converting the design to a structured ASIC design by using a respective, functionally equivalent, structured ASIC library cell for each of said programmed look-up tables; identifying a critical path in the structured ASIC design; for an input to a cell in the critical path, which input affects an output of said cell that is also in the critical path, searching for a physical input of the cell that is faster to affect said output of said cell than an initial physical input assignment of that input; and when a faster physical input is found, then transferring the input from the initial physical input assignment to the faster physical input when the transferring can be done without loss of functional equivalence between the cell and the programmed look-up table that was converted to the cell in the converting.