Patent ID: 7847369

Claim:
A semiconductor device comprising: a semiconductor die including at least one transistor having a gate, a drain region, a source region, and a channel region, wherein the gate comprises a layer of electrically conductive material and wherein the gate length of the transistor is approximately equal to a deposition thickness of the layer of electrically conductive material; an active area in the semiconductor die, wherein the channel region of the at least one transistor is in the active area; and a dielectric platform surrounding the active area, wherein the semiconductor dielectric platform is greater than about ten microns wide and at least about four microns deep; wherein the semiconductor die includes an epitaxial layer in which the active area is located, the semiconductor die includes a heavily doped region beneath the active area, and the semiconductor dielectric platform extends at least about four microns from a surface of the epitaxial layer through the epitaxial layer into said heavily doped region; wherein the epitaxial layer is located adjacent an upper surface of the semiconductor die and the semiconductor dielectric platform comprises a region having a plurality of cavities defining a matrix of vertical structures, the vertical structures being dielectric material, innermost ones of the vertical structures having inner walls of dielectric material bounding outer portions of the active area; wherein the active area includes an array of transistor cells including the at least one transistor; each cell of the array of transistor cells having a source region, a gate and a drain region; the drain regions of each cell of the array of transistor cells are coupled together, the transistor cells being connected in parallel to perform an equivalent function of a single active area; and further comprising a metal gate interconnection coupled to the gates of the cells, said gate interconnection overlying the semiconductor dielectric platform, a metal source interconnection coupled to the source regions of the cells, said source interconnection being located on the upper surface of the semiconductor die, and a metal drain interconnection coupled to the drain regions of the cells, said drain interconnection being located on a lower surface of the semiconductor die; wherein the source interconnection comprises a generally planar source metallization layer overlying the active area, and metal posts coupled at their lower ends to the source regions of the cells, upper portions of the posts being coupled to the metallization layer to thereby electrically connect all of the source regions of the cells in parallel.