Patent ID: 8120413

Claim:
A charge pump circuit, comprising: a switch unit adapted to transmit charges from an input of the charge pump circuit to an output of the charge pump circuit and comprising a first NMOS transistor and at least two in-series coupled PMOS transistors, wherein an output terminal of the first NMOS transistor is coupled with an input terminal of the first PMOS transistor, an input terminal of the first NMOS transistor is the input of the charge pump circuit, and an output terminal of the last PMOS transistor is the output of the charge pump circuit; a transmission unit comprising at least two stages of transmission sub-units coupled in series, wherein the first stage of transmission sub-unit is adapted to control turn-on or cut-off of the first NMOS transistor and the first PMOS transistor in the switch unit, and other stages of transmission sub-units are sequentially in one-to-one correspondence with the other PMOS transistors in the switch unit and control turn-on or cut-off of the corresponding PMOS transistor, wherein each stage of transmission sub-unit comprises a first input, a second input, a third input and an output; in the first stage of transmission sub-unit, the first input is coupled with the input terminal of the first PMOS transistor and the output terminal of the first NMOS transistor in the switch unit, the second input is coupled with the output terminal of the first PMOS transistor in the switch unit, the third input is coupled with a first clock signal, and the output is coupled with the gate of the first NMOS transistor and the gate of the first PMOS transistor in the switch unit; and in the other stages of transmission sub-units, the first input is coupled with the input terminal of the corresponding PMOS transistor in the switch unit, the second input is coupled with the output terminal of the corresponding PMOS transistor in the switch unit, the third input is coupled with the first input of the preceding stage of transmission sub-unit, and the output is coupled with the gate of the corresponding PMOS transistor in the switch unit; and at least two stages of charging units adapted to store charges to boost a transmission voltage, wherein each stage of charging unit is in one-to-one correspondence with the corresponding PMOS transistor in the switch unit.