Patent ID: 6987496

Claim:
An electronic device comprising a plurality of pixels, each of the pixels having: a source signal line; n (where n is a natural number, n≧2) gate signal lines used for write-in; n gate signal lines used for read-out; n transistors used for write-in; n transistors used for read-out; n×m volatile memory circuits for storing m frame portions (where m is a natural number, m≧1) of an n-bit digital image signal; n×k non-volatile memory circuits for storing k frame portions (where k is a natural number, k≧1) of the n-bit digital image signal; 2n volatile memory circuit selection portions; 2n non-volatile memory circuit selection portions; an electric current supply line; an EL driver transistor; and an EL element; wherein: gate electrodes of the n write-in transistors are each electrically connected to any one of the n write-in gate signal lines, with each of said gate electrodes connected to a different write-in gate signal line; input electrodes of the n write-in transistors are each electrically connected to the source signal line; output electrodes of the n write-in transistors are each electrically connected to the volatile memory circuits through any one of the volatile memory circuit selection portions, with each of said output electrodes being connected through a different volatile memory circuit selection portion; the output electrodes of the n write-in transistors are each electrically connected to the non-volatile memory circuits through any one of the non-volatile memory circuit selection portions, with each of said output electrodes being connected through a different non-volatile memory circuit selection portion; gate electrodes of the n read-out transistors are each electrically connected to any one of the n read-out gate signal lines, with each of said gate electrodes connected to a different read-out gate signal line; the input electrodes of the n read-out transistors are each electrically connected to the volatile memory circuits through any one of the volatile memory circuit selection portions, with each of said input electrodes being connected through a different volatile memory circuit selection portion; the input electrodes of the n read-out transistors are each electrically connected to the non-volatile memory circuits through any one of the non-volatile memory circuit selection portions, with each of said input electrodes being connected through a different non-volatile memory circuit selection portion; the output electrodes of the n read-out transistors are each electrically connected to a gate electrode of the EL driver transistor; an input electrode of the EL driver transistor is electrically connected to the electric current supply line; and an output electrode of the EL driver transistor is electrically connected to one electrode of the EL element.