Patent ID: 8232629

Claim:
A semiconductor device comprising: a first semiconductor chip including a power transistor, the first semiconductor chip having an output electrode electrically connected to the power transistor; a second semiconductor chip including a driver circuit to drive the power transistor, the second semiconductor chip having a plurality of terminals electrically connected to the driver circuit; a first die pad over which the first semiconductor chip is mounted, the first die pad having a top surface, a bottom surface opposite the top surface, and a side surface between the top and bottom surfaces of the first die pad, and the first semiconductor chip being mounted over the top surface of the first die pad; a second die pad over which the second semiconductor chip is mounted, the second die pad having a top surface, a bottom surface opposite the top surface, and a side surface between the top and bottom surfaces of the second die pad, and the second semiconductor chip being mounted over the top surface of the second die pad; a sealing body which covers a portion of the first die pad, a portion of the second die pad, the first semiconductor chip, and the second semiconductor chip, the sealing body having a first side surface, a second side surface opposite the first side surface, a top surface, and a bottom surface opposite the top surface, the first and second side surfaces of the sealing body being between the top and bottom surfaces of the sealing body, and the bottom surfaces of the first die pad and the second die pad being exposed from the bottom surface of the sealing body; a plurality of output pins electrically connected to the output electrode of the first semiconductor chip; and a plurality of control pins electrically connected to corresponding ones of the plurality of terminals of the second semiconductor chip, wherein the bottom surfaces of the first die pad and the second die pad are surfaces for mounting the semiconductor device, wherein a first portion of the side surface of the first die pad faces a first portion of the side surface of the second die pad, wherein the first portions of the side surfaces of the first and second die pads are arranged between the plurality of the output pins and control pins, wherein the plurality of output pins have free end portions projected from the first side surface of the sealing body, wherein the plurality of control pins have free end portions projected from the second side surface of the sealing body, wherein the sealing body further has a third side surface and a fourth side surface opposite the third side surface, the third and fourth side surfaces of the sealing body respectively intersecting the first side surface of the sealing body, and wherein portions of the first die pad project from the third and fourth side surfaces of the sealing body, and top surfaces of said projecting portions of the first die pad are exposed from the sealing body in plan view.