Patent ID: 7804086

Claim:
A phase change memory device comprising: a silicon substrate having a cell region and a peripheral region; a first insulation layer formed in the cell region of the silicon substrate, wherein a hole is defined in the first insulation layer; a cell switching element formed within the hole, wherein the height of the cell switching element is less than the height of the first insulation layer; a heat sink formed within the hole and on the cell switching element, wherein a portion of the heat sink projects out of the hole in the first insulation layer; a gate formed in the peripheral region of the silicon substrate, the gate having a stack structure comprising a gate insulation layer, a first gate conductive layer, a second gate conductive layer, and a hard mask layer; a second insulation layer formed over the surface of the silicon substrate in the peripheral region and the cell region, wherein a contact hole is formed in the second insulation layer to expose the heat sink, and wherein the second insulation layer is formed such that the hard mask layer of the gate is exposed by the second insulation layer; a heater formed in the contact hole; and a stack pattern formed on the heater, the stacked pattern comprising a phase change layer and a top electrode.