Patent ID: 8361844

Claim:
A method, comprising: forming a gate electrode structure of a transistor above a semiconductor layer, said gate electrode structure comprising an electrode portion formed on a gate insulation layer and an implantation blocking portion formed on said electrode portion, said implantation blocking portion comprising an upper surface; forming drain and source regions in said semiconductor layer by ion implantation using said gate electrode structure as an implantation mask to substantially prevent penetration of ions into a channel region of said transistor; performing a deposition process to form a planarization material adjacent to said gate electrode structure, wherein said deposition process is performed so that said planarization material substantially surrounds said gate electrode structure and wherein an as-deposited upper surface of said planarization material does not cover said upper surface of said implantation blocking portion; removing at least said implantation blocking portion to expose said electrode portion; and after removing at least said implantation blocking portion, removing said planarization material and forming an interlayer dielectric material adjacent to and above said electrode portion.