Patent ID: 7451371

Claim:
A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly during scan-test, where N >1, each clock domain having one or more capture clocks and one or more scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode; said method comprising the steps of: (a) generating and loading N predetermined stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly, by applying first selected shift clock pulses to all said scan cells in said scan mode for loading or shifting-in said N predetermined stimuli to all said scan cells, during a shift operation; (b) applying an ordered sequence of clock pulses to all said scan cells within said N clock domains during a capture operation, the ordered sequence of clock pulses comprising at least a second selected shift clock pulse and a capture clock pulse from two or more selected capture clocks, for controlling two or more clock domains, in a sequential order, wherein one said selected capture clock must contain at least one said second selected shift clock pulse and the other said selected capture clock must contain at least one said capture clock pulse, and when detecting or locating selected delay faults within a clock domain, said selected capture clock controlling the clock domain selectively contains at least two consecutive capture clock pulses or a second selected shift clock pulse followed by at least one capture clock pulse to launch the transition and capture the output response; and (c) comparing N output responses directly with their expected output responses for all said scan cells within said N clock domains and indicating errors immediately, by applying said first selected shift clock pulses to all said scan cells in said scan mode for comparing or shifting-out said N output responses for comparison with said expected output responses, during a compare operation.