Patent ID: 8130578

Claim:
A semiconductor memory device, comprising: first and second bit line pairs, each of which includes first and second bit lines; a first sense amplifier configured to sense and amplify a data supplied from the first bit line pair; a second sense amplifier configured to sense and amplify a data supplied from the second bit line pair; a first precharge unit configured to precharge the first bit lines of the first and second bit line pairs in response to a bit line equalizing signal; a second precharge unit configured to precharge the second bit lines of the first and second bit line pairs in response to the bit line equalizing signal; a first equalization unit configured to equalize voltage levels of the first and second bit lines of the first bit line pair in response to the bit line equalizing signal: and a second equalization unit configured to equalize voltage levels of the first and second bit lines of the second bit line pair in response to the bit line equalizing signal, wherein the first and second bit lines are disposed in opposite directions based on each corresponding sense amplifiers.