Patent ID: 8274468

Claim:
A flat panel display comprising: a display panel; a first signal driver configured to receive a first group video data and drive a first group signal line of the display panel in accordance with the first group video data; a second signal driver configured to receive a second group video data and drive a second group signal line of the display panel in accordance with the second group video data; a first data line; a second data line; a controller configured to control a timing of sending the first group video data to the first signal driver via the first data line, and a timing of sending the second group video data to the second signal driver via the second data line; a delay time generating section configured to shift a relative timing between a timing at which the first signal driver receives the first group video data and a timing at which the second signal driver receives the second video data by a determined time, wherein the delay time generating section comprises a plurality of first-in-first out (FIFO) memories, wherein the plurality of FIFO memories includes a first FIFO memory comprising a plurality of flip-flop circuits that latch the video data, and wherein the first FIFO memory further comprises a read multiplexer that selects a flip-flop circuit of the plurality of flip-flop circuits to output the video data.