Patent ID: 7790336

Claim:
A method for joining a plurality of reticles for use in producing a semiconductor layout pattern, so that said reticles will collectively map a circuit arrangement on a semiconductor substrate whilst providing a plurality of matching patterns that are each geometrically linked to a respective particular reticle and through detecting pairwise correspondence among said matching patterns ascertaining likewise correspondence among the associated reticles, said method being characterized by having bulk sub-reticles and peripheral sub-reticles, and associating a first matching pattern to a peripheral sub-reticle that abuts a bulk sub-reticle and a second matching pattern to the bulk sub-reticle at such distance therefrom that fitting of the peripheral sub-reticle between the second matching pattern and the bulk sub-reticle allows matching of the first and second matching patterns, and wherein respective bulk sub-reticles are used to constitute an array of sub-reticles.