Patent ID: 8001437

Claim:
A test pattern generation method for avoiding false testing in two-pattern testing for a semiconductor integrated circuit, comprising: applying test patterns to a semiconductor integrated circuit having a logic portion comprising a combinational portion with a plurality of gates, each test pattern being a combination of logic values of “0” and “1;” measuring responses at the rated functional speed of the semiconductor integrated circuit; comparing the measured responses with expected responses to the test patterns; determining if the combinational portion is defective; generating a two-pattern test set, the test patterns comprising an initialization pattern for initializing gate states and a launch pattern for causing logic bit transitions with respect to the initialization pattern, wherein some logic bits for detecting defects in the combinational portion are specified and remaining bits are unspecified bits; obtaining signal paths formed in the combinational portion by the application of the test patterns based on given information on the combinational portion, arranging the paths in descending order of path lengths; selecting a plurality of the paths within a preset path length range as critical paths; identifying critical gates the critical gates including the gates on each of the critical paths, the critical gates existing in a predetermined gate distance from each of the critical paths; obtaining a critical capture transition (CCT) metric for the critical gates; and assigning a logic value to each unspecified bit in the test patterns so that the critical capture transition (CCT) metric is reduced.