Patent ID: 6859072

Claim:
A method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier comprising: providing a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier, said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprising: a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal; a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal; at least one first clocked half-rail differential logic circuit with single-rail logic and sense amplifier data input terminal; and at least one first clocked half-rail differential logic circuit with single-rail logic and sense amplifier data output terminal; providing a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier, said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprising: a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal; a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal; at least one second clocked half-rail differential logic circuit with single-rail logic and sense amplifier data input terminal; and at least one second clocked half-rail differential logic circuit with single-rail logic and sense amplifier data output terminal; coupling a first clock signal to said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal; coupling a second clock signal to said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal; coupling said at least one first clocked half-rail differential logic circuit with single-rail logic and sense amplifier data output terminal to said at least one second clocked half-rail differential logic circuit with single-rail logic and sense amplifier data input terminal; and delaying said first clock signal by a predetermined delay time to create said second clock signal.