Patent ID: 7473975

Claim:
A semiconductor device structure comprising: a frilly silicided metal gate of a first thickness and abutting source and drain regions with surface metal silicide layers of a second thickness, wherein said second thickness is less than the first thickness; and one or more spacers abutting the filly silicided metal gate, wherein the one or more spacers are located directly on only a portion of an upper surface of the surface metal silicide layers that is adjacent to the frilly silicided metal gate, the one or more spacers present on the portion of the upper surface of the metal silicide layer that is adjacent to the fully silicided metal gate is protecting an interface between the surface metal silicide layers and the abutting source and drain regions to the fully silicided metal gate, wherein the surface metal silicide layers of the abutting source and drain regions comprise a first metal silicide material, and wherein said fully silicided metal gate comprises a second, different metal silicide material.