Patent ID: 7065757

Claim:
A compiler used by a computer architecture to compile a family of related functions, comprising: a member recognize configured to recognize a member function from said family of related functions, wherein each member function of the family of member functions is a mathematical function operable to be executed using a set of instructions and a portion of the set of instructions for each member function are identical; a family start caller configured to make a family-start function call for said family of related functions, wherein the family-start function call is a call to a family-start function performing the identical set of instructions for each member function; a member finish caller to make a member-finish function call for said member function, wherein the member-finish function call is a call to a member-finish function performing instructions unique to the member function; and an optimizer configured to optimize said family-start function call; wherein the optimized family-start function call causes execution of the portion of the set of instructions that are identical for each member function to occur prior to execution of instructions for each of a plurality of member-finish functions to reduce a number of instructions executed by the computer architecture in computing more than one member function from said family of related functions.