Patent ID: 8704299

Claim:
A semiconductor device comprising: a plurality of first element isolation regions provided in a semiconductor substrate to extend in a first direction and each defining an active region having a plurality of element formation regions; a gate electrode trench provided in a surface layer of the semiconductor substrate to extend in a second direction intersecting with the first element isolation regions and the active regions, and having first and second side faces facing each other and a bottom; a fin formed such that a part of the active region protrudes from the bottom of the gate electrode trench by forming the gate electrode trench such that a first trench section thereof formed in the active region has a smaller depth than a second trench section thereof formed in the first element isolation region, and the depth of the part of the first trench facing the second trench section is substantially the same as that of the second trench section; a gate insulating film covering the surfaces of the gate electrode trench and the fin; a gate electrode formed to stride over the fin via the gate insulating film by being embedded in a lower part of the gate electrode trench; a first impurity diffusion region formed in the semiconductor substrate so as to cover the top of the gate insulating film arranged on the first side face; and a second impurity diffusion region formed in the semiconductor substrate so as to cover the gate insulating film formed on the second side face except a lower end thereof, wherein the gate insulating film has a relationship represented by t 1 <t 2 between its thickness t 1 on the first and second side faces of the gate electrode trench and its thickness t 2 at the top of the fin.