Patent ID: 7714552

Claim:
An electronic device having an LDO regulator for varying loads, the LDO regulator comprising: a primary supply node (AVDD) adapted to be coupled to a primary voltage supply; an output node (V OUT ) providing a secondary supply voltage and a load current (I LOAD ); a bias current source (I B1 ) generating a bias current; and a gain stage (GS) including a first MOS transistor (MN 1 ) coupled to said bias current source and biased in weak inversion, and a current mirror coupled to said first MOS transistor (MN 1 ) to mirror a drain current through said first MOS transistor to said output node; wherein a gate-source voltage of said first MOS transistor (MN 1 ) increases in response to a decreasing secondary supply voltage level at said output node (V OUT ) to thereby increase the available load current (I LOAD ).