Patent ID: 7268827

Claim:
A timing signal transferring circuit coupled between a first video signal processing circuit and a second video signal processing circuit wherein the first video signal processing circuit has a first system clock and the second video signal processing circuit has a second system clock and the first system clock has a different frequency than the second system clock, comprising: an input terminal coupled to receive a first timing signal from the first video signal processing circuit that is essentially synchronous with the first system clock and is set to the vicinity of a center of a screen by a video signal; an output terminal coupled to provide a second timing signal to the second video signal processing circuit that is essentially synchronous with the second system clock and generated on the basis of the first tinting signal; a synchronization protecting circuit that subjects the first timing signal transferred from the first video signal processing circuit to synchronous protection with the second system dock as an operation clock; and a timing signal generating circuit that generates a second timing signal essentially synchronous with the second s stem clock on the basis of the first timing signal and the second system clock to transfer the second timing signal to the second video signal processing circuit.