Patent ID: 8830784

Claim:
A semiconductor memory, comprising: a word line driver including a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source; and a negative voltage generator configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line, wherein the negative voltage generator includes a timing device having an input coupled to a first node that is coupled to the input of the first inverter and having an output coupled to a second node; a first transistor having a are coupled to the second node a source coupled to the second voltage supply, and a drain coupled to a third node; and a capacitor coupled to the second node and to the third node and configured to generate the negative voltage in response to the control signal.