Patent ID: 7414448

Claim:
A duty cycle correction circuit, comprising: a tuned circuit for receiving an input clock and a reference voltage, and generating a periodic low level pulse according to said input clock, tuning said periodic low level pulse depending on said reference voltage, generating an output clock from the output end of said tuned circuit by extending the state of the low level of said periodic low level pulse; a delay circuit connected to the output end of said tuned circuit for receiving said output clock, and generating a first delay clock and a second delay clock, wherein both of clocks are complementary signals with each other; and a phase lock loop connected to said delay circuit for receiving said first delay clock and said second delay clock, and measuring the state time of the high level and low level of said first delay clock and said second delay clock, generating said reference voltage and feeding it back to said tuned circuit, said phase lock loop including: a phase comparator for receiving said first delay clock and said second delay clock to measure the state time of high level and low level of said first delay clock and said second delay clock, said phase comparator including a plurality of transistors, a first capacitor, and a second capacitor; a low pass filter including a resistance and a third capacitor, said third capacitor providing said reference voltage, and said low pass filter being connected to said first capacitor; and, an operational amplifier, the positive input thereof for receiving said reference voltage, the negative input thereof being coupled to an output thereof to form a voltage follower, and said output being connected to said second capacitor, wherein said second capacitor provides the same value of voltage as said reference voltage.