Patent ID: 8108197

Claim:
A method for testing an implemented coherency algorithm of a multi processor environment on a single processor model, said method comprising: providing a simulated multi processor environment including a random stimulation driver, a private cache hierarchy in communication with said random stimulation driver, and a nest in communication with said private cache hierarchy; implementing a coherency algorithm on said simulated multi processor environment by: generating a reference model configured to operate on every cacheline that populates said private cache hierarchy and to keep a set of two time stamps on said every cacheline, said set of two time stamps including a construction date representing a first global time when new data arrives at said private cache hierarchy and an expiration date representing a second global time when said private cache hierarchy is hit by a cross invalidation, stimulating said private cache hierarchy with interface events including at least one of simulated requests from said random simulation driver and cross invalidations from said nest, and augmenting data in a plurality of cachelines in said private cache hierarchy with said set of two time stamps by operating said reference model, wherein each time stamp is set based on occurrence of said interface events; and determining presence of an error in said implemented coherency algorithm when said private cache hierarchy ever returns data to said random simulation driver with an expiration date that is older than a latest construction date of all data used before.