Patent ID: 7253053

Claim:
A method of forming a PMOS device and an NMOS device, comprising: providing a substrate comprising a PMOS gate region and an NMOS gate region; forming a gate dielectric layer over the PMOS and NMOS gate regions of the substrate; forming a thick metal-containing material to be over the PMOS gate region and not over the NMOS gate region, the thick metal-containing material being formed to a thickness of greater than 20 Å; forming a thin metal-containing material to be over the PMOS and NMOS gate regions, the thin metal-containing material being formed to a thickness of less than or equal to about 20 Å and being formed over the thick metal-containing material over the PMOS gate region; forming a layer of conductively-doped silicon extending across the PMOS and NMOS gate region and over the thin metal-containing material; incorporating the thick metal-containing material, Thin metal-containing material and conductively-dope silicon into a PMOS transistor gate stack aver the PMOS gate region; and incorporating the thin metal-containing material and conductively-doped silicon into an NMOS transistor gate stack over the NMOS gate region.