Patent ID: 7956397

Claim:
A semiconductor device comprising: a first well region which is formed at a surface portion of a semiconductor substrate; a first element isolating region which is formed along an edge of the first well region; a gate insulating film which is formed on the first well region; a second element isolating region which is formed at a surface portion of the first well region and below an edge of the gate insulating film, an entirety of the second element isolating region being located inside the first well region; a first diffusion layer which is formed at a surface portion of the first well region between the first element isolating region and the second element isolating region and to which a first voltage is applied; and a gate electrode which is formed on the gate insulating film and has a polarity different from a polarity of the first well region and the first diffusion layer, and to which a second voltage is applied, wherein a capacitance is formed between the region within the first well region surrounded by the second element isolating region and the gate electrode.