Patent ID: 8093131

Claim:
A method of manufacturing a semiconductor device, comprising: forming a first base region of a second conductivity type on a surface of a semiconductor layer; forming below said first base region a second base region having a lower concentration and a larger depth of an impurity of the second conductivity type than said first base region; forming a buffer region of the second conductivity type in said semiconductor layer apart from said second base region; sequentially forming a gate insulating film and a gate electrode on said first base region; forming an emitter region of a first conductivity type on a surface of said first base region; and forming a collector region of the first conductivity type on a surface of said buffer layer wherein the end portions of said first base region and said gate electrode overlap each other and a length in a lateral direction from a point where an impurity concentration of the second conductivity type in said first base region becomes maximum under said emitter region and at an end of said gate electrode to a boundary between said first base region and said semiconductor layer is not smaller than a length in the vertical direction from said point to the underside of said first base region.