Patent ID: 7496726

Claim:
A method for controlling contention between conflicting transactions in a transactional memory system, comprising: receiving a request to access a cache line; determining if the cache line is already in use by an existing transaction in a cache state that is incompatible with the request; and if so, determining if the request is from a processor which is in a polite mode or an insistent mode; and if the processor is in a polite mode, determining whether the request has been denied a predetermined number of times; and if so, switching the processor from the polite mode to the insistent mode; if not, determining whether a transaction timer has expired, wherein the transaction timer specifies a predetermined time since the start of the existing transaction during which the processor will deny requests to access cache lines which are marked as transactional; and if not, denying the request to access the cache line if the cache line is marked as transactional; if the processor is in the insistent mode, granting the request to access the cache line.