Patent ID: 7916758

Claim:
A precise-clock synchronization method, comprising: obtaining a time stamp, wherein the time stamp comprises at least an original time stamp about the time when a master clock side transmits a synchronous (Sync) packet and a relative arrival time stamp about the time when a slave clock side receives the Sync packet; synchronizing the clock frequency at the slave clock side with the clock frequency at the master clock side, if the clock frequency at the slave clock side and the clock frequency at the master clock side are asynchronous; transmitting a delay request (Delay_Req) packet, and receiving a delay response (Delay_Resp) packet returned by the master clock side after it receives the Delay_Req packet; obtaining the time stamp including the original time stamp, the relative arrival time stamp and an absolute arrival time stamp of the Sync packet, a Delay_Resp time stamp, and a Delay_Req time stamp; calculating a time offset according to the original time stamp, the absolute arrival time stamp, the Delay_Resp time stamp, and the Delay_Req time stamp; and synchronizing the clock time at the slave clock side with the clock time at the master clock side by using the time offset, wherein synchronizing the clock frequency at the slave clock side with the clock frequency at the master clock side comprises: calculating a relative delay between the relative arrival time stamp and the original time stamp; setting a first statistics period having a minimum relative delay selected from a plurality of calculated relative delays; setting a second statistics period, and monitoring a changing trend of the minimum relative delay within the second statistics period; and determining whether the clock frequency at the slave clock side and the clock frequency at the master clock side are synchronous or not according to the changing trend of the minimum relative delay.