Patent ID: 7334207

Claim:
An apparatus comprising: a plurality of input cells on a single integrated circuit package each configured to provide (i) one or more gate voltage signals and (ii) one or more supply voltage signals; two or more local tie up cells each configured to provide electrostatic discharge (ESD) protection to one or more first standard cells, wherein each of said local tie up cells are coupled to (i) said one or more first standard cells and (ii) each of said gate voltage signals, wherein (i) each of said local tie up cells when coupled to said one or more first standard cells form a tie up net and (ii) each of said tie up nets are positioned a predetermined distance from each other; and two or more local tie down cells each configured to provide ESD protection to one or more second standard cells, wherein each of said local tie down cells are coupled to (i) said one or more second standard cells and (ii) each of said supply voltage signals.