Patent ID: 7057231

Claim:
An integrated circuit comprising a first nonvolatile memory cell, the integrated circuit comprising: a semiconductor substrate having a top surface and a trench formed in the top surface; a dielectric on a surface of the trench; a conductive floating gate at least partially located in the trench; wherein the first nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate, and comprises a second FET for controlling access to the first FET; wherein the substrate comprises: a first semiconductor region of a first conductivity type adjacent to the trench and providing a first source/drain region for the first FET; a second semiconductor region of a second conductivity type adjacent to the trench above the first semiconductor region and providing a channel region for the first FET; a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the trench above the second semiconductor region and provides a second source/drain region for the first FET, wherein the third semiconductor region also provides a source/drain region for the second FET; a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET; wherein the integrated circuit further comprises a conductive member having a portion overlying the trench, wherein the conductive member provides a gate for the second FET, wherein the gate for the second FET is adjacent to the channel region of the second FET.