Patent ID: 8136102

Claim:
A computer-implemented method, configured to be performed at a parallel-processing computer system with first and second processing elements, each having a different instruction set architecture, comprising: at run-time, while the application is executing, receiving one or more operation requests from an application; preparing an intermediate representation for the operation requests; dynamically preparing a set of compute kernels for the intermediate representation, by: compiling one or more compute kernels for a previously uncompiled first portion of the intermediate representation for execution on the first processing element; searching a set of previously compiled compute kernels to determine whether a second portion of the intermediate representation has been previously compiled; and selecting one or more previously compiled compute kernels for execution on the second processing element, the selected compute kernels having been compiled for execution on the second processing element; and dynamically executing the set of compute kernels on the first and second processing elements, wherein the first and second processing elements are selected from a group consisting of: single-core central processing units, multi-core central processing units, graphics processing units, single-core co-processors and multi-core co-processors.