Patent ID: 8421159

Claim:
A logic gate structure comprising: a substrate; a plurality of transistors fabricated on the substrate, where the plurality of transistors comprises a first transistor, a second transistor and a third transistor that are serially connected with the first transistor coupled to the second transistor which is coupled to the third transistor, where a first end of the first transistor is coupled to an output and a second end of the first transistor is coupled to a first end of the second transistor, where a first end of the third transistor is coupled to a second end of the second transistor and a second end of the third transistor is coupled to ground, where the plurality of transistors further comprises a fourth transistor, a fifth transistor and a sixth transistor that are connected in parallel, where a first end of the fourth transistor, a first end of the fifth transistor and a first end of the sixth transistor are coupled to at least one voltage source, where a second end of the fourth transistor, a second end of the fifth transistor and a second end of the sixth transistor are coupled to the output; a plurality of first raised source/drain structures coupled to the fourth transistor, the fifth transistor, the sixth transistor, the first end of the first transistor and the second end of the third transistor, where the plurality of first raised source/drain structures has a first length; and a plurality of second raised source/drain structures coupled to the first end of the second transistor and the second end of the second transistor, where the plurality of second raised source/drain structures has a second length, where the second length is less than the first length.