Patent ID: 8099704

Claim:
A method to improve performance in an integrated circuit (IC), comprising: performing a timing analysis for a circuit design of the IC, wherein modules in the circuit design are applied a first voltage bias by default; identifying a critical path in the timing analysis, wherein a signal propagating through the critical path does not meet timing requirements for the circuit design; determining a module of the IC in the critical path; selecting a tapping point from a plurality of serially coupled resistors to determine a second voltage bias at an output, wherein the tapping point is coupled to a first voltage source, wherein the plurality of serially coupled resistors are coupled between the output and a second voltage source; and applying the second voltage bias to the selected module, the second voltage bias being greater than the first voltage bias, wherein a delay through the selected module when applying the second voltage bias is smaller than when the first voltage bias is applied to the selected module, wherein at least one method operation is executed through a processor.