Patent ID: 8686889

Claim:
A system for signal processing comprising: a cyclic analog to digital converter (ADC) structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase; the second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (Nâˆ’3) most significant bits (MSBs) of N bits of data are generated; and a third stage configured to generate a three least significant bits (LSBs) of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage.