Patent ID: 8290092

Claim:
A digital demodulating apparatus, comprising: a numerically controlled oscillator (NCO) generating a first sequence signal according to an input sequence signal and a timing error sequence signal; an equalizer unit equalizing the first sequence signal to generate an equalized sequence signal; a decoder decoding the equalized sequence signal to generate an output sequence signal; a timing error detector generating the timing error sequence signal according to the first sequence signal and one of the equalized sequence signal and the output sequence signal; and a buffer buffering the first sequence signal so as to generate a compensated first sequence signal, wherein the timing error detector generates the timing error sequence signal according to the compensated first sequence signal and one of the equalized sequence signal and the output sequence signal, wherein the timing error detector generates the timing error sequence signal further according to a previous compensated first sequence signal and one of a previous output sequence signal and a previous equalized sequence signal, and wherein the timing error sequence signal is generated according to the following formula: e ( n )= a ( n âˆ’1) y ( n )âˆ’ a ( n ) y ( n âˆ’1), wherein e(n) is the timing error sequence signal, a(n) is the output sequence signal, a(nâˆ’1) is the previous output sequence signal prior to a(n), y(n) is the compensated first sequence signal, and y(nâˆ’1) is the previous compensated first sequence signal prior to y(n).