Patent ID: 8769355

Claim:
A data processing system, comprising: a first processor; a second processor, the second processor having a cache; a built-in self-test (BIST) controller coupled to the cache of the second processor, wherein the BIST controller comprises: an address generator configured to generate memory addresses for the cache of the second processor; a data pattern generator configured to generate data patterns for storage into the cache; control circuitry configured to store data generated by the data pattern generator at memory addresses of the cache generated by the address generator and to load data from the cache; a data compare unit coupled to the control circuitry configured to determine if data values read from the cache match expected data values; a random value generator coupled to the address generator; and storage circuitry configured to store a random BIST enable (RBE) indicator, wherein, the first data processor is configured to assert the RBE indicator upon initiating execution of a secure code sequence, and the control circuitry is configured to, in response to assertion of the RBE indicator by the first processor, perform memory accesses to memory addresses of the cache generated by the address generator in response to the random value generator.