Patent ID: 8848726

Claim:
An on-chip information processing system comprising: an input port configured to receive packets of a first packet-type, wherein packets are received at a data rate of at least 1 gigabit per second, wherein the received packets of the first packet-type are in accordance with a protocol for wired local-area-networking (LAN) technologies, wherein packets of the first packet-type include an address of a first address-type; an address resolution module configured to resolve addresses of the first address-type from received packets of the first packet-type, wherein the address resolution module is configured to receive packets from the input port; a packet dicer module configured to dice received packets of the first packet-type into one or more packets of a second packet-type, wherein individual packets of the second packet-type range between 64 bits and 2048 bits, wherein packets of the second packet-type include packet headers and zero or one packet payloads, wherein individual ones of the packet headers include an address of a second address-type; an output port configured to transmit packets of the first packet-type off the on-chip system at a data rate of at least 1 gigabit per second; a packet assembler module configured to assemble packets of the first packet-type from one or more packets of the second packet-type for transmission through the output port; two or more high-speed serial input ports configured to receive packets of the second packet-type at a data rate of at least 100 Mbits per second; two or more secondary address resolution modules configured to resolve addresses of the second address-type from packets of the second packet-type, wherein an individual secondary address resolution module is configured to receive packets of the second packet-type from an individual high-speed serial input port; one or more high-speed serial output ports configured to transmit packets of the second packet-type off the on-chip system at a data rate of at least 100 Mbits per second; and a router module configured to receive packets of the second packet-type from a set of packet sources and transmit packets of the second packet-type to a set of packet destinations, wherein the set of packet sources includes the packet dicer module and two or more high-speed serial input ports, wherein the set of packet destinations includes the packet assembler module and two or more high-speed serial output ports.