Patent ID: 8335120

Claim:
A semiconductor memory device comprising: a first plurality of memory circuits that connect to a first bit line, a second bit line, and a word line, and that hold information; a first pre-charge control circuit that connects to a first pre-charge control line, the first bit line, and the second bit line and that pre-charges the first bit line and the second bit line based on an input from the first pre-charge control line; and a read control circuit having a first transistor that has a source terminal connected to a power supply and a gate terminal connected to a read-column selection line; a second transistor that has a source terminal connected to a drain terminal of the first transistor, a gate terminal connected to the first bit line, and a drain terminal connected to a global-bit-line driver control line and that charges the global-bit-line driver control line based on an input from the read-column selection line and a potential level of the first bit line; a third transistor that has a drain terminal connected to the global-bit-line driver control line, a gate terminal connected to the read-column selection line, and a source terminal grounded and that pre-discharges the global-bit-line driver control line based on a column selection signal; and a fourth transistor that has a drain terminal connected to a third bit line, a gate terminal connected to the global-bit-line driver control line, and a source terminal grounded, and wherein the fourth transistor is brought into conduction based on an input from the charged global-bit-line driver control line, a column having the first bit line and the second bit line is thus selected, and the information held in a memory circuit connecting to a driven word line among the first plurality of memory circuits is output to the third bit line.