Patent ID: 7442998

Claim:
A non-volatile memory, comprising: a substrate; a plurality of first memory units disposed on the substrate, wherein the first memory units are separated from one another by a gap and each first memory unit comprises a first composite layer, a first gate and a cap layer sequentially formed over the substrate; a plurality of second memory units disposed in the gaps between the first memory units, wherein each second memory unit comprises a second composite layer and a second gate sequentially formed over the substrate and the second memory units together with the first memory units form a memory cell column; a plurality of insulating spacers disposed between the first memory units and the second memory units; a source region and a drain region disposed in the substrate on the respective sides of the memory cell column; a first inter-layer insulating layer disposed on the substrate; a source line disposed in the first inter-layer insulating layer for connecting with the source region; a plurality of metallic lines disposed in the first inter-layer insulating layer aligned in a direction perpendicular to the memory cell column for connecting with the second gate of the second memory cell units; a second inter-layer insulating layer disposed on the first inter-layer insulating layer; and a bit line disposed on the second inter-layer insulating layer for connecting electrically with the drain region through a conductive plug.