Patent ID: 7053675

Claim:
A processor clock control device operable to control switching between clock signals input to a processor, said processor clock control device comprising: at least two clock signal inputs each operable to receive a clock signal, said clock signals comprising a first and a second clock signal; a sensor operable to sense said first and said second clock signals; a clock signal output operable to output a clock signal for input to a processor; and a clock switching signal input for receiving a switching signal operable to control switching of said clock signal output from said first clock signal to said second clock signal; wherein: said processor clock control device is operable on receipt of said switching signal to sense said first clock signal and if said first clock signal is at a second level when said switching signal is received, said processor clock control device is operable to hold said clock signal output at said second level, and then to sense said second clock signal and when said second clock signal transitions from a first level to said second level to output said second clock signal.