Patent ID: 7242737

Claim:
A system for aligning data transferred across circuit boundaries having different clock domains, wherein a first clock signal operates in a first clock domain and a second clock signal operates in a second clock domain, said first and second clock signals of the same frequency but operating out of phase, said system comprising: a buffer circuit comprising latch means receiving data clocked in said first clock domain and latching said received data in said second clock domain by one of a first edge of said second clock signal, or a second opposite edge of said second clock signal; and, a control circuit means for receiving said first and second clock signals and determining a phase relationship therebetween, said control circuit generating a control signal based on said determined phase relationship, said control signal implemented for selecting one of said first edge of said second clock signal, or said second opposite edge of said second clock signal, for said latch means latching action in said second clock domain, wherein reliable data transfer operation is provided for all possible phase relationships of said first and second clock signals.