Patent ID: 8320201

Claim:
A precharge circuit for precharging a bit line of a semiconductor memory device, the precharge circuit comprising: a plurality of series connected inverters for generating a latch signal; a first feedback inverter having an input connected to a last inverter of the plurality of series connected inverters and an output connected to an input of the last inverter of the plurality of series connected inverters; a first reset transistor connected between the output of said last inverter and a first supply voltage, and having a gate that receives a reset clock signal; a first transistor having a gate that receives the latch signal; a second transistor connected between the first transistor and a second supply voltage; a second reset transistor connected between the first transistor and the first supply voltage, and having a gate that receives the reset clock signal; a common precharge inverter having an input connected to a first node between the first transistor and the second reset transistor, and an output that provides a common precharge signal; a second feedback inverter having an input connected to the output of the common precharge inverter and an output connected to the first node; a third feedback inverter having an input connected to the output of the common precharge inverter and an output connected to a gate of the second transistor; a logic gate having a first input connected to the output of the common precharge inverter for receiving the common precharge signal, and an output that provides a precharge pulse; a first precharge clock inverter having an input connected to the output of the common precharge inverter for receiving the common precharge signal, and an output that provides a precharge clock signal; a second precharge clock inverter having an input connected to the output of the first precharge clock inverter; a fifth transistor having a gate connected to an output of the second precharge clock inverter, and a source connected to the first power supply; a sixth transistor having a gate connected to a reference bit line of the semiconductor memory, and a drain connected to a drain of the fifth transistor; a seventh transistor having a drain connected to a drain of the fifth transistor; and a programmable delay circuit that has an input connected to the drain of the fifth transistor and an output connected to a second input of the logic gate.