Patent ID: 8166358

Claim:
An integrated circuit comprising: A. a test data in lead; B. a test clock in lead; C. a test mode select in lead; D. a test data out lead; E. an instruction register coupled with the test data in lead and the test data out lead, the instruction register having a control input and a control output; F. a data register coupled with the test data in lead and the test data out lead, the data register having a control input coupled to the control output of the instruction register; and G. addressable port circuitry including state machine circuitry coupled with the test mode select in lead and the test clock in lead, the addressable port circuitry having a control output coupled with the instruction register and the data register, the addressable port circuitry including addressing circuitry coupled to the test data in lead, the test clock in lead, and the test mode select in lead, and gating circuitry coupled with the addressing circuitry and selectively connecting the test mode select in lead with the state machine circuitry.