Patent ID: 8271932

Claim:
A computer-implemented method for verifying a RAIM/ECC design using a hierarchical error injection scheme, the method comprising: selecting marks for generating an error mask, the marks corresponding to at least one of: a marked channel and at least one marked chip; selecting a fixed bit flip mask based on the selected marks; determining that errors should be injected into the at least one of the marked channel and the at least one marked chip; randomly injecting, by a computer, errors into the at least one of the marked channel and the at least one marked chip based on the determining that the errors should be injected into the at least one of the marked channel and the at least one marked chip, the injecting based on at least one of the fixed bit flip mask and a random bit flip mask; determining that errors should be injected into an unmarked chip; and based on the determining that errors should be injected into an unmarked chip: selecting an unmarked channel; selecting an unmarked chip from the unmarked channel; and selecting the random bit flip mask or the fixed bit flip mask for the selected unmarked chip.