Patent ID: 7928555

Claim:
A stacked semiconductor package comprising: a wiring substrate; a first semiconductor chip disposed on the wiring substrate and wire-bonded to the wiring substrate; an interposer chip disposed on the first semiconductor chip and wire-bonded to the wiring substrate, the interposer chip including a diode and a bonding pad being electrically connected; and a second semiconductor chip disposed on the interposer chip and wire-bonded to the interposer chip, the second semiconductor chip being electrically connected to the wiring substrate through the interposer chip, wherein the diode is connected to a grounding pad or a grounding line of the interposer chip and the diode includes, a P well formed below the bonding pad and the grounding pad in the interposer chip, the P well being electrically connected to the grounding pad, and an N+ well formed below the bonding pad in the P well, the N+ well being electrically connected to the bonding pad.