Patent ID: 8227869

Claim:
A semiconductor device comprising: a substrate; a PMOS transistor comprising: a first gate over the substrate; a first source region adjacent to the first gate; a first drain region adjacent to, and on an opposite side of the first gate than, the first source region; and a first stressor layer over the first gate, the first source region, and the first drain region, wherein the first stressor layer has a compressive stress, and wherein the first stressor layer has the shape of a polygon when viewed from a top down perspective, the top down perspective being defined as from a perspective orthogonal to a major surface of the substrate, and wherein the polygon includes a recess defined in its periphery, and an NMOS transistor adjacent the PMOS transistor, the NMOS transistor comprising: a second gate over the substrate; a second source region adjacent to the second gate; a second drain region adjacent to, and on an opposite side of the second gate than, the second source region; and a second stressor layer over the second gate, the second source region, and the second drain region, wherein the second stressor layer has a tensile stress, and wherein the second stressor layer has the shape of a polygon when viewed from the top down perspective, and wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer.