Patent ID: 7114008

Claim:
An architecture for intercepting and processing packets transmitted from a source to a destination over a network, the architecture comprising: a packet interceptor coupled with said network and operative to selectively intercept said packets prior to receipt by said destination based on a first criteria; at least one primary processor coupled with said packet interceptor and operative to perform stateless processing tasks on said intercepted packets, said stateless processing tasks comprising tasks which are not directly dependent on a previously intercepted packet, said at least one primary processor including: at least two stateless packet processors coupled in parallel, said processing of said intercepted packets being distributed among said at least two stateless packet processors; at least one secondary processor coupled with said at least one primary processor and operative to perform stateful processing tasks on said statelessly processed intercepted packets, said stateful processing tasks comprising tasks which are based at least on a previously intercepted packet, said at least one secondary processor including: at least two stateful packet processors coupled in series with each other, each of said at least two stateful packet processors operative to perform a portion of said stateful processing tasks on said statelessly processed intercepted packets, a last one in said series of said at least two stateful packet processors being coupled with said network and operative to selectively release said statefully processed and statelessly processed intercepted packet back to said network.