Patent ID: 6930559

Claim:
An oscillation state discrimination circuit adapted to an oscillation circuit, comprising: a PLL circuit for producing a clock signal whose frequency is a multiple of a frequency of an oscillation signal, which is output from the oscillation circuit performing oscillation, wherein the PLL circuit controls the clock signal in phase to be synchronized with the oscillation signal; and a discrimination circuit for discriminating whether or not the PLL circuit is placed in a phase-locked state on the basis of a phase relationship between the oscillation signal and the clock signal, thus discriminating whether or not oscillation of the oscillation circuit is stabilized, wherein the PLL circuit produces the clock signal by increasing the frequency of the oscillation signal with a multiple N (where N is a natural number not less than 2), and wherein the discrimination circuit discriminates whether or not the PLL circuit is placed in a phase-locked state on the basis of a regularity among phase relationships each detected between the oscillation signal and the clock signal with respect to each of N bits.