Patent ID: 6845436

Claim:
A memory system comprising: a memory controller; a first memory device; a first data bus for transporting data between the memory controller and the first memory device; a first clock bus, carrying a first clock signal, for facilitating a transfer of the data from the memory controller to the first memory device; and a second clock bus, carrying a second clock signal, facilitating a transfer of the data from the first memory device to the memory controller, wherein the first and second clock buses are separate buses, wherein the first and second clock signals are separately generated, wherein the first clock signal synchronizes a receipt of the data by the first memory device with sending of the data by the memory controller as the data is being transported via the first data bus, wherein the second clock signal synchronizes a receipt of the data by the memory controller with sending of the data by the first memory device as the data is being transported via the first data bus, wherein the first clock signal synchronizes a receiving latch in the first memory device with a sending latch in the memory controller.