Patent ID: 8067789

Claim:
A semiconductor integrated circuit device, comprising: a semiconductor substrate having a main surface which has an edge; a plurality of I/O cells disposed in a row extending along the edge of the main surface, each of the plurality of I/O cells including a first MOS transistor and a second MOS transistor, in which a shortest distance between the first MOS transistor and the edge of the main surface is smaller than that between the second MOS transistor and the edge of the main surface; a bonding pad disposed over the main surface, the bonding pad being overlapped with the first MOS transistor and the second MOS transistor of each of the plurality of I/O cells in plan view; a first wire disposed under the bonding pad, the bonding pad being overlapped with the first wire in plan view; a first conductive plug disposed between the bonding pad and the first wire, the first conductive plug connecting the bonding pad and the first wire; a second wire disposed under the bonding pad, the bonding pad being overlapped with the second wire in plan view; a second conductive plug disposed between the bonding pad and the second wire, the second conductive plug connecting the bonding pad and the second wire; and a plurality of interconnect layers between the plurality of I/O cells and the bonding pad, wherein a first power wire and a second power wire are formed of the interconnect layers while excluding an interconnect layer directly under the bonding pad, wherein the bonding pad is electrically coupled to the first MOS transistor and to the second MOS transistor via the first and second wires, respectively, wherein the first conductive plug and the first wire are located between the first MOS transistor and the edge of the main surface in plan view, and wherein the second conductive plug and the second wire are further than the second MOS transistor from the edge of the main surface in plan view.