Patent ID: 8255443

Claim:
A circuit arrangement, comprising: a plurality of linear feedback shift registers (LFSR's), each configured to generate a pseudorandom number responsive to a seed value; a plurality of operand multiplexers, each operand multiplexer corresponding to one of the plurality of LFSR's and including a first input configured to receive an operand and a second input coupled to the corresponding LFSR to receive the pseudorandom number generated thereby; a mode control special purpose register (SPR) coupled to the plurality of operand multiplexers to output the first or second input of each operand multiplexer responsive to a value stored in the mode control SPR; a pipelined execution unit including a plurality of operand inputs, each operand input in communication with and corresponding to one of the plurality of operand multiplexers, wherein the pipelined execution unit is configured to execute a mode control instruction that stores a value in the mode control SPR to configure each operand multiplexer to output the first or second input thereof, and wherein the pipelined execution unit is further configured to perform an arithmetic operation during execution of an arithmetic instruction that identifies a plurality of operands by, for each operand input corresponding to an operand multiplexer configured to output the second input by the mode control SPR, using an operand identified by the arithmetic instruction as the seed value for the corresponding LFSR and using the pseudorandom number generated thereby as an input value for the arithmetic operation, and for each operand input corresponding to an operand multiplexer configured to output the first input by the mode control SPR, using an operand identified by the arithmetic instruction as an input value for the arithmetic operation, and wherein the pipelined execution unit is configured to execute the arithmetic instruction such that each pseudorandom number used as an input value for the arithmetic operation is generated during the same pass of the pipelined execution unit during which the arithmetic operation is performed.