Patent ID: 8713080

Claim:
A compression circuit comprising: a) a data memory for storing a data structure comprising individual data values, b) a bit map memory for storing a map, the map storing bits representing the locations of individual zero data values and locations of individual nonzero values within the data structure, wherein a bit is set to zero when an entry in the data structure corresponding to the bit is zero and the bit is set to one when the entry in the data structure corresponding to the bit is non-zero, and c) a data output, wherein the circuit is configured to retrieve non-zero data from the data structure in the data memory using the map and provide the retrieved data itself as a compressed data structure in combination with data representing the map on the data output; and wherein the data output further comprising an arrangement of adders, each adder accepting an input from the bit map memory, and a plurality of comparators, each comparator comparing two integer inputs, the first input of each comparator being an output from a corresponding adder in the arrangement of adders and the second input to each comparator is a sequencing signal.