Patent ID: 7601632

Claim:
A method of forming a metal line of a semiconductor device, comprising the steps of: forming a first interlayer insulating layer over a semiconductor substrate, and etching a specific region of the first interlayer insulating layer to form contact holes having sidewalls and a bottom region; forming a liner metal layer on surface of the first interlayer insulating layer and the contact holes; forming a first conductive layer on the surface of the first interlayer insulating layer including the contact holes; performing an annealing process so that the first conductive layer flows downward into the contact holes, thus coating the lower sidewalls and bottom region of the contact holes with the first conductive layer, thereby forming a first annealed conductive layer; removing the liner metal layer formed on the first interlayer insulating layer; filling a second conductive layer in the contact holes on the first annealed conductive layer; forming a third conductive layer on the surface of the first interlayer insulating layer and the second conductive layer; and patterning the third conductive layer to form a metal line.