Patent ID: 7790527

Claim:
A method of manufacturing a high-voltage transistor, comprising: providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer; wherein a portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V; wherein forming one or more portions of the transistor node including a diffusion region of the transistor in the SOI layer includes: forming an insulating spacer on a portion of the diffusion region; and implanting dopant into the substrate such that a resistance of a portion of the diffusion region covered by the spacer is higher than a portion of the diffusion region exposed by the spacer.