Patent ID: 6842845

Claim:
A signal processor comprising: at least one core processor to process data samples of a digital input signal using a digital signal processing algorithm, the at least one core processor including, a plurality of signal processing units to execute the digital signal processing algorithm and to process in parallel the data samples of the digital input signal, the plurality of signal processing units to generate a digital output signal in response to the data samples of the digital input signal and the digital signal processing algorithm, and a reduced instruction set computer (RISC) processor to control the plurality of signal processing units in processing the data samples of the digital input signal, wherein, the plurality of signal processing units comprises four signal processing units and the digital signal processing algorithm is a non-vectorized equation in the form of YOUTn=((((AC+ L a 0 X 0 )+ L a 1 X 1 )+ L a 2 X 2 )+ L a 3 X 3 ) where “+ L ” refers to a limiting of the addition to a range of values between a positive saturation value and a negative saturation value of a saturated multiplication and accumulation technique and AC is an accumulated value of a prior processing cycle.