Patent ID: 7562184

Claim:
A DRAM controller for controlling a plurality of DRAMs capable of burst transfers and having command-issuing interval restriction of a predetermined number of cycles, the plurality of DRAMs being independent from each other and each comprising a plurality of memory banks, comprising: a plurality of signal lines capable of connecting the plurality of DRAMs; and an interface unit which assigns to the DRAMs a frame-buffer area including a plurality of two-dimensionally arranged drawing blocks, and accesses the DRAMs in accordance with graphics processing, wherein the interface unit: assigns different ones of the DRAMs to neighboring ones of the drawing blocks at least in part of the frame-buffer area, issues, when performing a processing across the neighboring drawing blocks to which the different DRAMs are assigned, active commands alternately in consecutive cycles or simultaneously to each of the different DRAMs, and includes a burst transfer control unit for outputting individual signals to the DRAMs in order for stopping burst transfer of at least one of the plurality of DRAMs independently during burst transfer by another DRAMA, wherein at least one of the plurality of signal lines is shared by the plurality of DRAMs and the at least one of the signal lines shared by the plurality of DRAMs includes data signal lines for transmitting data signals.