Patent ID: 7259979

Claim:
A TCAM cell architecture comprising: a pair of memory elements connected to an associated read/write bit line and a read/write bit complement line for storing a data bit and a complement data bit; and a pair of compare circuits connected to an associated search bit line and a search bit complement line, and connected to the associated pair of memory elements that compares the stored data bit with a received compare data bit and drives a mismatch signal onto an associated match line ML when the stored data bit is not equal to the compare data bit, wherein each of the pair of memory elements are connected using substantially vertical interconnections that are disposed in active NMOS layers and active PMOS layers and further connected using substantially horizontal interconnections that are disposed in selective metal layers, wherein the pair of memory elements and the associated read/write bit line and the read/write bit complement line are connected using substantially horizontal interconnections that are disposed in a poly layer and a metal layer; wherein each of the pair of memory elements are connected such that they are stacked vertically to provide a shared read/write bit line resulting in a reduced number of bit lines, reduced width of TCAM cell, reduction of silicon area, and improved performance, and wherein each of the pair of compare circuits includes a pair of compare NMOS transistors, and wherein each pair of NMOS compare transistors is connected using substantially vertical interconnections that are disposed in active NMOS layer.