Patent ID: 6869872

Claim:
A method of manufacturing a semiconductor memory device, comprising the steps of: a) forming gate electrodes on a substrate having a cell region and a periphery region; b) forming a first insulating layer over the substrate, the first insulating layer covering the gate electrodes; c) forming first metal contact holes and stud holes in the first insulating layer, wherein the stud holes are aligned with corresponding one of the first metal contact holes; d) forming metal contact studs and first metal contact portions in the stud holes and the first metal contact holes, respectively; e) forming a second insulating layer on the first insulating layer and on the metal contact studs; f) forming bit line contact holes passing through the first and second insulating layers; g) forming bit line contacts in the bit line contact holes; and h) forming bit lines on the second insulating layer, wherein the metal contact studs are formed having a width that is greater than a space between adjacent bit lines.