Patent ID: 7603402

Claim:
A recording medium for storing a program executable by a common-memory scalar parallel-processing computer for implementing a parallel matrix processing method in matrix processing, which includes LU (Lower-Upper) factorization, said program comprising: a processing for acquiring information about a band coefficient matrix; a processing for performing in parallel a LU decomposition on column blocks by allocating column blocks comprising a plurality of columns in the acquired band matrix information to the processors, respectively, and for storing the LU decomposition results in a working area on a plurality of memory modules; a processing for canceling a row permutation performed as the result of a pivoting selection on the left side of each column corresponding to the LU decomposition result, and for copying back the cancelled data result to a band matrix storage array area in a compressed form on the memory modules; a processing for computing a maximum value of the length of the row that requires a permutation on the basis of the LU decomposition result of the column blocks, and for determining whether the maximum value exceeds a capacity of the band matrix storage array area in the compressed form or not, and for saving excess data beyond the capacity in the memory modules when it is determined that the maximum value exceeds the capacity of the band matrix storage array area; a processing for making each processor update the band matrix in parallel by using the LU decomposition result of the column block stored in the working area; and a processing for returning the data saved in the memory modules to the band matrix update result, wherein at least one of the processing is carried out by the common-memory scalar parallel-processing computer having a plurality of processors, first caches respectively included in the processors, secondary caches corresponding respectively to the processors, an interconnection network connecting the processors via the secondary caches, and the memory modules which the processors access via the interconnection network.