Patent ID: 8558602

Claim:
A semiconductor integrated circuit comprising: a first level shifter that includes: a first transistor of a first channel type having a source terminal connected to a power source voltage supply node of a first power source system, a second transistor of the first channel type having a source terminal connected to the power source voltage supply node of the first power source system, a drain terminal connected to a gate terminal of the first transistor and a gate terminal connected to a drain terminal of the first transistor, a third transistor of a second channel type having a drain terminal connected to the drain terminal of the first transistor, a source terminal connected to a ground voltage supply node and a gate terminal to which a first signal of a second power source system is input, and a fourth transistor of the second channel type having a drain terminal connected to the drain terminal of the second transistor, a source terminal connected to the ground voltage supply node and a gate terminal to which an inversion signal of the first signal is input, and a second level shifter that includes: a fifth transistor of the first channel type having a source terminal connected to the power source voltage supply node of the first power source system, a sixth transistor of the first channel type having a source terminal connected to the power source voltage supply node of the first power source system, a drain terminal connected to a gate terminal of the fifth transistor and a gate terminal connected to a drain terminal of the fifth transistor, a seventh transistor of a second channel type having a drain terminal connected to the drain terminal of the fifth transistor, a source terminal connected to the ground voltage supply node and a gate terminal to which a second signal of the second power source system is input, and an eighth transistor of the second channel type having a drain terminal connected to the drain terminal of the sixth transistor, a source terminal connected to the ground voltage supply node and a gate terminal to which a signal of a common drain terminal of the drain terminal of the second transistor and the drain terminal of the fourth transistor is input.