Patent ID: 7589014

Claim:
A method of producing a semiconductor device including a plurality of wiring layers, comprising: forming a first interlayer-insulating film; forming a plurality of first grooves for wiring layers in the first interlayer-insulating film; forming a first wiring layer by filling metallic films in the grooves for wirings; polishing and removing upper surfaces of the first wiring layer and the first interlayer-insulating film to flatten the upper surfaces thereof; forming a second interlayer-insulating film on flattened upper surfaces of the first wiring layer and the first interlayer-insulating film; performing dehydrating polymerization to the second interlayer-insulating film; simultaneously forming a first contact hole and a second groove for wiring in the second interlayer-insulating film after the dehydrating polymerization; forming a second wiring layer including a wiring and plug by filling metallic films in the second groove for wiring; polishing and removing upper surfaces of the second wiring layer and the second interlayer-insulating film to flatten the upper surfaces thereof; and forming a porous insulating film by performing solvent evaporation at a predetermined temperature to the second interlayer-insulating film and the second wiring layer after flattening the upper surfaces thereof so as to generate pores in only the second interlayer-insulating film.