Patent ID: 8742850

Claim:
A method of on-chip gain calibration for a semiconductor die, the method comprising: providing, by a resistance element on the semiconductor die, a first signal to an amplifier circuit on the semiconductor die, wherein the amplifier circuit comprises a plurality of amplifiers, wherein each amplifier of the plurality of amplifiers has a respective gain; based upon the first signal, providing, by the amplifier circuit on the semiconductor die, a second signal to a voltage sampling circuit on the semiconductor die; based upon the second signal, providing, by the voltage sampling circuit on the semiconductor die, a digital signal to an automatic gain control circuit on the semiconductor die; based upon the first signal, determining, by the voltage sampling circuit on the semiconductor die, a resistance value of the resistance element; based upon the digital signal, providing, by the automatic gain control circuit on the semiconductor die, a gain control signal to the amplifier circuit on the semiconductor die; and based upon the gain control signal, controlling, by the amplifier circuit on the semiconductor die, the respective gain of the plurality of amplifiers of the amplifier circuit, wherein controlling, by the amplifier circuit on the semiconductor die, the respective gain of the plurality of amplifiers of the amplifier circuit is further based upon the resistance value.