Patent ID: 7688669

Claim:
A circuit, comprising: a memory circuit receiving a high supply voltage and a low supply voltage; and a programmable bias circuit which generates, from a first set of voltages, a second set of voltages for application as the high supply voltage and a low supply voltage, comprising: a high side circuit including a first plurality of individually selectable voltage offset circuits each of which providing a different offset voltage between a high voltage of the first set of voltages and a high voltage of the second set of voltages, wherein the high voltage of the second set of voltages is less than the high voltage of the first set of voltages; and a low side circuit including a second plurality of individually selectable voltage offset circuits each of which providing a different offset voltage between a low voltage of the first set of voltages and a low voltage of the second set of voltages, wherein the low voltage of the second set of voltages is greater than the low voltage of the first set of voltages.