Patent ID: 8537046

Claim:
A circuit for performing an analog to digital (A/D) conversion, the circuit comprising: an amplifier comprising an input and an output; a capacitor array comprising capacitors each having a first end and a second end, wherein respective first ends of a plurality of the capacitors are each coupled to a selection circuit configured to individually couple the respective first end of each of the plurality of the capacitors to a system input voltage, the output of the amplifier, or one of a plurality of reference voltages, and the second end of each of the plurality of the capacitors are coupled to the input of the amplifier; an A/D converter coupled to the output of the amplifier; a control unit configured to: cause the circuit to sample the system input voltage by controlling the selection circuit to couple the first end of each capacitor in the capacitor array to the system input voltage in a sampling step, after the sampling step, cause the A/D converter to perform a first A/D conversion in a first conversion step to produce a first conversion result, after the first conversion step, cause the selection circuit to selectively couple respective first ends of each of a first group of the plurality of the capacitors to one of the plurality of reference voltages based on the first conversion result, and couple respective first ends of the plurality of the capacitors not in the first group to the output of the amplifier in a first redistribution step, after the first redistribution step, cause the A/D converter to perform a second A/D conversion in a second conversion step to produce a second conversion result; and an output circuit configured to perform a weighted sum of the first and second conversion result to produce a system output value.