Patent ID: 7032146

Claim:
A boundary scan device comprising: a (Level Sensitive Scan Design) LSSD circuit; an LSSD clock stricture operatively coupled to said LSSD circuit; and a switch driver circuit operatively coupled to an output of said LSSD circuit, wherein the switch driver circuit includes: a latch; a first gate for gating information into said latch operatively connected to an input of said latch; a second gate for gating information from said latch operatively connected to said latch; wherein the switch driver circuit includes: a first gate ( 606 ) having a first electrode to provide an output signal; a first latch ( 604 ) having an output operatively connected to a second electrode of said first Rate and an input operatively connected to a third electrode of said first gate; a second latch having an output operatively connected to a third electrode of said first gate; a second gate ( 610 ) having an electrode operatively connected to the first latch and the second latch; and a third gate ( 608 ) having an electrode operatively connected to an input of the second latch.