Patent ID: 8153520

Claim:
A method of processing a partially manufactured semiconductor substrate with one or more through silicon vias, the method comprising: positioning the substrate on a layer processing station of a processing chamber, wherein the substrate includes the one or more through silicon vias filled with tungsten and an initial tungsten layer formed on a field region of the substrate, wherein the initial tungsten layer has an intrinsic residual stress that causes an interior portion of the substrate to deviate from a plane defined by edges of the substrate, exposing the field region of the substrate to an etchant; and removing a part of the initial tungsten layer to form an etched tungsten layer substantially covering the field region of the substrate and the one or more through silicon vias such that the through silicon vias remain filled, wherein the etched tungsten layer has an intrinsic residual stress that is less than the intrinsic residual stress of the initial tungsten layer such that the deviation of the substrate from the plane is reduced after forming the etched tungsten layer.