Patent ID: 6948029

Claim:
A DRAM (dynamic random access memory) device comprising: DRAM having a self-refresh function; a DRAM controller for controlling said DRAM; a timer; and a CPU; wherein said DRAM controller monitors access from said CPU to said DRAM and, when there is no access to said DRAM within time set in the timer, said DRAM controller switches a refresh mode of said DRAM to the self-refresh mode; wherein when a predetermined period of time has elapsed in the self-refresh mode, said DRAM controller releases the self-refresh mode and makes a request for interruption; wherein, upon receipt of the request for interruption, said CPU makes a backup copy of the contents of said DRAM in other memory and notifies said DRAM controller of an interruption clear signal and said DRAM controller performs control so as to switch the refresh mode of said DRAM to a power-down mode; and wherein the CPU can continue to perform processing when the DRAM is in the power-down mode.