Patent ID: 7002236

Claim:
A semiconductor package comprising: a first insulating substrate having a first surface and a second surface opposite said first surface, said first surface having electrically conductive patterns and electrically conductive pattern lands formed thereon, said second surface having a heat dissipating pattern and second surface lands formed thereon; a heat radiating plate that radiates heat from within said semiconductor device, said heat dissipating pattern and said second surface lands being between said first insulating substrate and said heat radiating plate; a semiconductor device bonded onto said first surface, bond wires connecting said semiconductor device to said electrically conductive patterns, said electrically conductive patterns being connected to said electrically conductive pattern lands; a sidewall section on said first surface, said sidewall section encircling said semiconductor device, a cavity being a concave shape defined by said first insulating substrate and said sidewall section, said semiconductor device being contained within said cavity; a second insulating substrate covering said sidewall section and said cavity, said second insulating substrate having a through-hole land portion and a solder land portion, said through-hole land portion being disposed at the rim of said second insulating substrate to contact said sidewall section, and a solder land portion being disposed at the central part of said second insulating substrate to contact said cavity; through-hole lands disposed at said through-hole land portion; solder lands disposed at said solder land portion; conductor patterns connecting said solder lands to said through-hole lands; and through-holes extending from said through-hole lands, through said second insulating substrate, said sidewall section, said electrically conductive pattern lands, said first surface, and said second surface, to said second surface lands, said through-holes being plated to form plated through-holes.