Patent ID: 8508967

Claim:
A semiconductor device comprising: first to fourth driver circuits; and a memory cell array comprising a plurality of memory cells arranged in a matrix over the first to fourth driver circuits, wherein one of the plurality of memory cells comprises: a transistor comprising a gate electrode, a source electrode, a drain electrode, an oxide semiconductor layer, and a gate insulating layer; and a capacitor comprising a pair of electrode layers and a dielectric layer therebetween, wherein one of the pair of electrode layers comprises the source electrode or the drain electrode, and the dielectric layer comprises the gate insulating layer, wherein the first driver circuit and the second driver circuit are arranged so as to be substantially symmetrical with respect to a center point of the memory cell array, wherein the third driver circuit and the fourth driver circuit are arranged so as to be perpendicular to the first driver circuit and the second driver circuit, and wherein the third driver circuit and the fourth driver circuit are arranged so as to be substantially symmetrical with respect to the center point of the memory cell array.