Patent ID: 8185859

Claim:
A design structure for designing, manufacturing, or testing an integrated circuit that is tangibly embodied in a machine readable storage medium that when processed on a data processing system generates a functional representation of the integrated circuit, the design structure comprising: at least two metal traces on a same network comprising at least two stack levels, the at least two metal traces being formed on a same stack level; and a metal short formed completely on the same stack level of the at least two metal traces, the metal short connecting and being in physical contact with the at least two metal traces, wherein: the metal short on the same stack level is shorter and has less path resistance than a multi-layer electrical path which connects the at least two metal traces; the metal short is positioned at an end of one of the at least two metal traces; the design structure further comprises another metal short formed on the same stack level of the at least two metal traces, the another metal short connecting and being in physical contact with the at least two metal traces, and the another metal short being positioned at another end of another one of the at least two metal traces; and a space is formed between the metal short and the another metal short to prevent a wide metal spacing violation.