Patent ID: 7414323

Claim:
A TAB tape comprising: a plurality of adjacent pattern areas defining a plurality of semiconductor packages, each of said plurality of adjacent pattern areas comprising: a mounting area for a semiconductor chip, an output test pad area including a plurality of first output test pads for inspecting such semiconductor chip, said output test pad area located adjacent to said mounting area on a first side thereof, and an input test pad area including at least one first input test pad for inspecting such semiconductor chip, said first input test pad located adjacent to said mounting area on a second side of the mounting area opposite the first side, wherein each of said adjacent pattern areas has an overlapping area where the first output test pad area of a first pattern area overlaps a first input test pad area of a second pattern area, and the first output test pads of the first pattern area and the first input test pads of the second pattern area are adjacent to each other without overlapping.