Patent ID: 7541242

Claim:
A method for programming a memory cell in an array of memory cells configured to store at least one bit per F 2 , the method comprising: coupling a first electrode to a first potential, where the first electrode is coupled to one of a first doped region disposed on a surface of a semiconductor substrate or a second doped region disposed on a bottom surface of one of a plurality of trenches formed in the substrate surface; coupling a second electrode to a second potential, where the second electrode is coupled to a remaining one of the first or second doped regions; coupling a third electrode to a gate formed adjacent to one of a plurality of substantially vertical structures each providing electronic memory functions and that are spaced apart a distance equal to one half of a minimum pitch of the array only on opposing sidewalls of the plurality of trenches between the first and second doped regions such that trench bottoms and the substrate surface between trenches have only an oxide dielectric between the substrate and the gate, wherein the structures providing the electronic memory functions are configured to store more than one bit per gate; and storing charge carriers in the one substantially vertical structure.