Patent ID: 8902687

Claim:
A semiconductor device, comprising: a first memory block and a second memory block each having a normal cell area including a plurality of normal memory cells and a redundant cell area including a plurality of redundant memory cells for replacing a defective memory cell among the normal memory cells; and a redundancy determination circuit that, in response to an event in which a normal memory cell that belongs to at least one memory block from among the first memory block and the second memory block is being replaced by the redundant memory cell in a refresh mode, receives a row address corresponding to a source of the replacement, compares the row address with a fuse data, generates a redundancy signal based on the comparison, and deactivates a normal cell area to which the normal memory cell that is the source of replacement belongs based on the redundancy signal generated using a result of the comparison between the row address and the fuse data and activates a redundant cell area to which the redundant memory cell that is to be replaced belongs and a normal cell area to which the normal memory cell that is not being replaced belongs based on the redundancy signal.