Patent ID: 7539823

Claim:
A multiprocessing apparatus comprising a plurality of processors, a shared bus, and a shared bus controller, wherein each of said processors includes a central processing unit (CPU) and a local cache, each of said local caches includes a cache memory, and a cache control unit operable to control said cache memory, each of said cache control units includes a data coherence management unit operable to manage data coherence between said local caches by controlling data transfer carried out, via said shared bus, between said local caches, wherein a first cache control unit of said cache control units belonging to a first processor of said processors is operable to monitor a local cache access signal, outputted from a second processor of said processors, for notifying an occurrence of a cache miss, notify pseudo information to said second processor via said shared bus controller, the pseudo information indicating that data corresponding to the local cache access signal is stored in a first cache memory of a first local cache that includes said first cache control unit when the data corresponding to the local cache access signal is not actually stored in said first cache memory, and issue a memory read request to a main memory via said shared bus controller, the memory read request being issued to read, from the main memory, the data corresponding to the local cache access signal; and a second cache control unit of said cache control units belonging to said second processor is operable to store, in a second cache memory of said second processor, data corresponding to the local cache access signal, which is read out from said main memory via said shared bus in response to the memory read request by the first cache control unit.