Patent ID: 6985096

Claim:
A bimodal serial to parallel converter, comprising: a first stage of registers clocked responsive to a first signal; first select circuitry coupled to the first stage of registers; a second stage of registers coupled to the select circuitry and clocked responsive a second signal; a third stage of registers clocked responsive to a third signal; the third signal having a lower frequency than the first signal; a first portion of the first stage of registers configured as a single shift register chain in a first mode of operation; a second portion of the first stage of registers configured as two shift registers in a second mode of operation; a bitslip controller coupled to receive the first signal and the third signal and configured to provide a clock control signal and an input select control signal; the first select circuitry coupled to receive the input select control signal and to select responsive to the input select control signal between at least two outputs of the first stage of registers to provide parallel input to the second stage of registers; second select circuitry coupled to receive the third signal and the clock control signal and configured to provide the second signal as being either one of the third signal and the clock control signal, the clock control signal being a divided down version of the first signal; the clock control signal being the second signal when in the second mode of operation; and the third signal being the second signal when in the first mode of operation.