Patent ID: 8296698

Claim:
A method, comprising: a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (V th ); b) while maintaining dimensions of other transistors in the SRAM array, adjusting one of a gate channel width (W g ) or a gate channel length (L g ) of one of the first and second MOS transistors to modify the V th of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array in a processor of a simulation tool configured to simulate a response of the SRAM array including the V th for the first and second MOS transistors; d) iteratively repeating steps b) and c) until a predetermined V th is achieved; and e) storing a data file representing a physical layout of the SRAM array, including the first and second MOS transistors having the predetermined V th , in a computer readable storage medium, wherein the data file is accessible to fabricate one or more photomasks for fabricating a semiconductor wafer that includes the SRAM array.