Patent ID: 8159852

Claim:
A semiconductor memory device, comprising: a first driving transistor comprising a first diffusion layer configured to serve as a drain and a second diffusion layer configured to serve as a source of the first driving transistor; a second driving transistor comprising a first diffusion layer configured to serve as a drain and a second diffusion layer configured to serve as a source of the second driving transistor; a first load transistor comprising a first diffusion layer configured to serve as a drain and a second diffusion layer configured to serve as a source of the first load transistor; a second load transistor comprising a first diffusion layer configured to serve as a drain and a second diffusion layer configured to serve as a source of the second load transistor; a first transmission transistor comprising a first diffusion layer configured to serve as a drain and a second diffusion layer configured to serve as a source of the first transmission transistor; a second transmission transistor comprising a first diffusion layer configured to serve as a drain and a second diffusion layer configured to serve as a source of the second transmission transistor, wherein the first and second diffusion layers of each of the first driving transistor, the second driving transistor, the first load transistor, the second load transistor, the first transmission transistor, and the second transmission transistor are isolated on the semiconductor substrate from the first and second diffusion layers of one another via an element isolation region, and wherein the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are in a bit cell; a first wiring configured to connect the drain of the first driving transistor, the drain of the first load transistor, and the drain of the first transmission transistor; and a second wiring configured to connect the drain of the second driving transistor, the drain of the second load transistor, and the drain of the second transmission transistor, wherein the first wiring and the second wiring are not connected to a bit line.