Patent ID: 8046725

Claim:
A method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method comprising: a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA by using a computer; a second step in which, when a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node; and wherein the timing yield of a gate is calculated according to an equation Gate ⁢ ⁢ Timing ⁢ ⁢ Yield = Φ ⁡ ( μ i σ i ) , wherein Φ indicates a cumulative distribution function of a standard normal distribution, and μ i and σ i indicate a mean deviation and a standard deviation of timing slack at an arbitrary gate i.