Patent ID: 7032198

Claim:
A method of designing a circuit having a clock signal supplying source and a plurality of flip-flop cells which are supplied with a clock signal from the clock signal supplying source, the method for designing the circuit comprising: synthesizing logic of circuit designing contents described in a register transfer level so as to create a first netlist which regulates a connection relationship between the flip-flop cells constituting a circuit to be designed; executing a floorplan by using the first netlist so as to create a clock tree of the circuit to be designed, and creating a second netlist containing one or more buffer cells for driving the flip-flop cells based on the clock tree; arranging a clock layout of the circuit to be designed based on floorplan information and the second netlist obtained by executing the floorplan so that the clock layout contains an initial placement of the buffer cells, the flip-flop cells, and clock signal lines connecting the one or more buffer cells and the flip-flop cells; and effecting an ordinary net wiring except for the clock signal lines after arranging the clock layout, wherein in the initial placement, a number of buffer stages are adjusted so that each of the circuit path extending from the clock signal supplying source to the flip-flop cells consists of the same number of buffer stages so that signal delay times of clock signals supplied from the clock signal supplying source to each of the flip-flop cells are equal.