Patent ID: 8592109

Claim:
A mask set used in a lithographic process for patterning multiple masking layers, the multiple masking layers used to pattern an integrated circuit (IC) layer, the mask set comprising: a first mask for defining only fine-line features in a first masking layer, wherein each fine-line feature has a dimension less than a wavelength of a light used to define the fine-line feature; a second mask for one of removing and designating for removal portions of the fine-line features, wherein the second mask includes bloated features, each bloated feature corresponding to a layout feature of a desired layout that is expanded only in directions along a critical dimension of that layout feature, and wherein at least one layout feature in the desired layout includes a fine-line feature and a coarse feature; and a third mask for defining a plurality of coarse features of the IC layer in a second masking layer formed over a patterned first masking layer, wherein at least one coarse feature is formed to connect two fine-line features.