Patent ID: 7240277

Claim:
A parity memory system comprising: a memory array having a plurality of memory lines of a predetermined data length; a parity memory storing at least one parity bit corresponding to each memory line of said memory and a corresponding valid bit; a parity error detection logic connected to said memory array and said parity memory including a parity generator generating at least one parity bit upon a read access of an entire memory line of said memory array, a comparator receiving said at least one parity bit corresponding to a read access of an entire memory line and said at least one parity bit generated by said parity generator, said comparator generating a parity error signal if said at least one parity bit corresponding to a read access of an entire memory line fails to match said at least one parity bit generated by said parity generator; and a parity generator receiving data to be written into said memory array, said parity generator operable to calculate parity from data to be written, store said calculated parity in said parity memory and set said corresponding valid bit to indicate valid upon a write access to an entire memory line of said memory array, and set said corresponding valid bit to indicate invalid upon a write access to less than an entire memory line of said memory array.