Patent ID: 7028280

Claim:
For a system for generating a layout for an integrated circuit (IC) design describing an IC as being formed by a plurality of cells organized into a hierarchy of modules in which descendant modules at lower levels of the hierarchy form ancestor modules at higher levels of the hierarchy, wherein terminals of cells forming the modules are to be interconnected in the layout by nets having segments, wherein the design defines modules as having ports through which the nets pass when extending between cells forming separate modules, wherein the system alters the IC design when generating the layout by inserting buffers into selected segments of the nets, a method for execution by the system for determining whether to insert a buffer into a particular segment of a net, the method comprising the steps of: a. assigning the buffer to a selected module of the hierarchy of modules for insert within the selected module, and b. determining whether insertion of the buffer assigned to the selected module into the particular segment of the net will alter a number of ports of any one of the modules through which the net passes.