Patent ID: 8178960

Claim:
A stacked semiconductor package comprising: a first semiconductor package, the first semiconductor package including a first substrate, at least one first semiconductor chip on the first substrate, a first re-distribution pattern on the at least one first semiconductor chip, and a first sealing member on the first substrate, the first sealing member covering the at least one first semiconductor chip and having at least one first via exposing the first re-distribution pattern; a second semiconductor package on the first semiconductor package, the second semiconductor package including a second substrate, at least one second semiconductor chip under the second substrate, a second re-distribution pattern on the at least one second semiconductor chip, and a second sealing member on a lower side of the second substrate, the second sealing member covering the at least one second semiconductor chip and having at least one second via exposing the second re-distribution pattern; and at least one electrical connection device electrically connecting the first semiconductor package and the second semiconductor package, wherein the at least one electrical connection device is in the at least one first via and the at least one second via and connects the first re-distribution pattern and the second re-distribution pattern.