Patent ID: 7102944

Claim:
A programmable ground circuit for control of a bitline evaluation when interfacing local bitlines to a global bitline or other circuit via a discharge device, the programmable ground circuit comprising: a first programmable input line connected to a gate of a first PFET; a second programmable input line connected to a gate of a first NFET; a default ground line connected to a second NFET; a first power supply connected to a second PFET; a first line connecting a drain electrode of the first PFET to a drain electrode of the first NFET; a second line connecting the first line to a gate of the second PFET; a third line connecting the second line to the gate of the second NFET; a central node connecting the second NFET to the second PFET; a fourth line connecting the first NFET to the central node; and a second power supply connected to the first PFET; wherein the output on the central node provides a programmable ground value so that input logic states of the programmable input lines enable one programmable ground output state to be used for a zero state voltage level to be sent to a discharge device.