Patent ID: 8365102

Claim:
A circuit layout method of forming two masks for a plurality of patterns, said method comprising: receiving layout data representing the plurality of patterns, each pattern having a plurality of runs, ends, and corners; for each pair of adjacent patterns, determining, by a processor of a computer system, whether a distance between the pair of adjacent patterns is a G0-space; for the G0-space, determining, by the processor, whether a G0-rule violation exists; determining, by the processor, whether a G0-space associated with the G0-rule violation is a critical G0-space that, if removed, merges two adjacent odd-loops of G0-spaces into a single even-loop of G0-spaces or converts one odd-loop of G0-spaces to a non-loop of G0-spaces; and outputting a representation comprising the G0-rule violation and the critical G0-space.