Patent ID: 7378710

Claim:
An integrated circuit having at least first and second inverted FinFet transistors (P 2 , N 3 ), said at least first FinFet transistor (P 2 ), comprising: a first gate region ( 108 ) including a semiconductor structure ( 100 ) on a substrate; and a first body region including a semiconductor layer ( 104 ) having a first channel region ( 112 ) disposed on the first gate region and a source ( 110 ) and drain ( 114 ) formed on either side of the first channel region; and said at least second FinFet transistor (N 3 ) coupled to said at least first transistor, comprising: a second body region including the semiconductor structure ( 102 ) having a second channel region ( 118 ) and a source ( 116 ) and drain ( 120 ) formed on either side of the second channel region; and a second gate region ( 122 ) including the semiconductor layer ( 104 ), disposed on the second channel region.