Patent ID: 7498679

Claim:
A semiconductor package including: a package substrate having an upper surface, and a lower surface, the package substrate including: a passivation layer formed on the lower surface of the package substrate, a window formed in a substantially central portion of the package substrate and extending through the package substrate, and at least one sink provided in the lower surface, the at least one sink formed into the passivation layer; a semiconductor chip having an active surface facing the lower surface of the package substrate, the active surface having a plurality of bond pads formed at a substantially central portion of the semiconductor chip to be aligned with the window, wherein the semiconductor chip is disposed on the lower surface of the package substrate to cover a portion of sink and a portion of the passivation layer adjacent to the sink; and an adhesive provided between the package substrate and the semiconductor chip, wherein the adhesive is provided on the passivation layer and extends into the at least one sink.