Patent ID: 7096450

Claim:
A method for designing wiring in a multilayered substrate so as to limit a temperature gradient in said wiring, comprising the steps of: providing an initial wiring design in which the multilayered substrate comprises layers stacked in a Y direction, wherein each layer of said layers has its length oriented in a X direction that is orthogonal to the Y direction, wherein a first electrically conductive wire within a first layer of said layers has its length oriented in the X direction, wherein in the initial wiring design the first wire has a spatially nonuniform temperature distribution T(X) along its length for an assumed current density J 1 in the first wire such that the first wire has a mean time to failure MTF 1 at the current density J 1 ; and altering the initial wiring design to reduce the magnitude of a temperature gradient dT(X)/dX along the length of the first wire for a current density J 2 not less than J 1 in the first wire, wherein the altering does not include changing a cross sectional area of the first wire, wherein the altering includes electrically and thermally coupling the first wire to a second electrically conductive wire in the first layer by an electrically and thermally conductive structure that exists outside of the first layer and adjusting the width distribution of the second wire in a Z direction that is orthogonal to the X and Y directions, wherein the first and second wires do not physically touch each other, and wherein said adjusting controls a temperature in the second wire so as to cause the second wire to act as a heat source or heat sink to the first wire.