Patent ID: 8718115

Claim:
A computing device comprising: a processor; and a memory coupled to the processor, wherein the memory is configured to store program instructions, and wherein the program instructions are executable by the processor to cause the computing device to: generate a chirp sequence having a bandwidth selected, at least in part, by subtracting an excess bandwidth parameter from a low nominal frequency and adding the excess bandwidth parameter to a high nominal frequency; extract a phase angle of a frequency-domain version of the chirp sequence to obtain a flattened frequency spectrum; create a phase quantized sequence based, at least in part, upon the flattened frequency spectrum; employ the phased quantized sequence as a symbol to generate a power line communication (PLC) preamble portion of a PLC frame; repeat the symbol N 1 times to create a first section of the PLC preamble portion, where N 1 is an integer; repeat a phase inverted version of the symbol N 2 times to create a second section of the PLC preamble portion, where N 2 is an integer different from N 1 ; extend the first and second sections of the PLC preamble portion; and combine the first and second extended sections of the PLC preamble portion.