Patent ID: 8461563

Claim:
A resistance change memory comprising: a first interconnect layer which has first interconnect lines arranged in parallel to each other on a semiconductor substrate; a second interconnect layer which is provided to be apart from the first interconnect layer and has second interconnect lines arranged in parallel to each other to cross the first interconnect lines; and memory cell units arranged at respective intersecting portions of the first interconnect lines and the second interconnect lines, wherein each of the memory cell units is configured to stack a resistance change element which stores states having different resistance values as data and a diode element having non-ohmic properties, and the diode element is configured to stack in order to a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type, and a third semiconductor layer having the first conductivity type from a side of the first interconnect layer, and an area density of dopant impurities in the second semiconductor layer is larger than a sum total of area densities of dopant impurities in the first and third semiconductor layers, and smaller than double an area density of an electric flux number associated with a threshold electric field of an interband tunneling current of a material comprising the second semiconductor layer.