Patent ID: 7303972

Claim:
A method of forming a resistor in the back end of the line of a multi-layer integrated circuit comprising the steps of: providing a lower layer having at least one lower metal interconnect and a lower ILD top surface; forming a first ILD layer having a first ILD thickness and a first ILD top surface on said lower ILD top surface; forming on said first ILD top surface a resistor having a resistor thickness and a resistor top surface and comprising at least a resistive layer and an etch-resistant resistor top cap layer above said resistive layer; forming a second ILD layer having a second ILD thickness substantially equal to said resistor thickness; planarizing said second ILD layer to said resistor top surface; forming a third ILD layer on said second ILD layer; simultaneously forming a set of dual-damascene apertures for making contact to at least some of said lower metal interconnects and a set of resistive contact apertures for making contact with said resistor in said third ILD layer; etching said set of resistive contact apertures through said resistor cap layer, whereby the bottom of said resistive contact apertures exposes said resistive layer; and simultaneously filling said set of dual-damascene apertures and said resistive contact apertures with a conductor.