Patent ID: 7688559

Claim:
A semiconductor integrated circuit device comprising: an internal circuit including an output buffer circuit to be protected from an ESD (electrostatic discharge) voltage; a first node connected to one end of the output buffer circuit; a second node connected to another end of the output buffer circuit; an ESD protective circuit which has a trigger terminal and forms a discharge path from the first node to the second node when a trigger signal is applied to the trigger terminal; and a trigger circuit including a first MOS device and a second MOS device, the first MOS device being connected in the output buffer circuit as a constituent thereof and also being coupled between the first and second nodes, the first MOS device having a source and a drain one of which is connected to the first node and forming a conductive path between the drain and the source thereof, the second MOS device having a source and a drain connected between the other of the source and the drain of the first MOS device and the trigger terminal of the ESD protective circuit and a gate connected to receive a power source voltage configured to set the second MOS device in a non-conductive state during a normal operation state and to set in a conductive state for supplying the trigger signals to the trigger terminal of the ESD protective circuit.