Patent ID: 8159040

Claim:
A semiconductor structure comprising: a semiconductor substrate that includes an active region laterally adjacent an isolation region, wherein the isolation region has an upper surface that is co-planar with an upper surface of the semiconductor substrate; a field effect device located within the active region, the field effect device comprising: a gate dielectric located upon the active region and comprising a gate dielectric material having a dielectric constant greater than about 10; and a gate electrode located upon the gate dielectric and comprising a metal material, wherein said gate dielectric has sidewalls that are vertically coincident with sidewalls of said gate electrode; and at least one of a fuse structure, an anti-fuse structure and a resistor structure located over the isolation region, the at least one of the fuse structure, the anti-fuse structure and the resistor structure comprising: a pad dielectric located upon the isolation region and comprising the same gate dielectric material as the gate dielectric and having a dielectric constant greater than about 10, wherein said pad dielectric and said gate dielectric material include upper surfaces that are coplanar to each other and bottom surfaces that are co-planar to each other; and at least one of a fuse, an anti-fuse and a resistor located upon the pad dielectric, wherein said at least one of said fuse, anti-fuse and resistor has sidewalls that are vertically coincident with sidewalls of said pad dielectric, said sidewalls of said pad dielectric are vertically offset from sidewalls of said isolation region.