Patent ID: 8736338

Claim:
A circuit comprising: a plurality of delay measurement circuits connected in a ring oscillator configuration, each delay measurement circuit comprising: a first chain of delay elements connected to receive a first signal from an on-chip circuit component, where each delay element in the first chain has a first delay value; a second chain of delay elements connected to receive a reference clock signal, where each delay element in the second chain has a second delay value that is different from the first delay value; and a plurality of sampling latches connected between the first and second chains, each sampling latch having a data input coupled between adjacent delay elements of the first chain and a clock input coupled between adjacent delay elements of the second chain such that an edge transition in the first signal is indicated by digital values stored in the plurality of sampling latches when the edge transition relative to the reference clock signal occurs within a predetermined measurement window of the circuit; and a frequency mixer comprising a first input coupled to receive an output from the first chain of delay elements of the last delay measurement circuit connected in the ring oscillator configuration to measure a data ring oscillator period, a second input coupled to receive an output from the second chain of delay elements of the last delay measurement circuit connected in the ring oscillator configuration to measure a clock ring oscillator period, and a frequency mixer output, where the output from the first chain of delay elements has a data ring frequency f D ) from the data ring oscillator period, and where the output of the second chain of delay elements has a clock frequency f C representing an inverse of the clock ring oscillator period, such that the frequency mixer combines the data ring frequency f D and the clock ring frequency f C to generate a mixer output signal at the frequency mixer output.