Patent ID: 8612909

Claim:
An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a synthesized logic design for an integrated circuit residing in the memory that includes a plurality of logic blocks and a plurality of inputs; and a logic block identification mechanism residing in the memory and executed by the at least one processor, the logic block identification mechanism identifying at least one logic block in the synthesized logic design that has specified inputs by performing an analysis of the synthesized logic design, wherein the specified inputs are specified and a number of levels is specified, and the logic block identification mechanism performs a forward linear trace to identify inputs at each level for each logic block without regard to logical function of each logic block, identifies from the identified inputs at least one potential equivalency point from the forward linear trace, and following completion of the forward linear trace for the specified number of levels, performs a reverse logical trace from the at least one potential equivalency point to identify equivalent logic, wherein the equivalent logic comprises the identified at least one logic block in the synthesized logic design that has the specified inputs.