Patent ID: 8687684

Claim:
A circuit for correcting the phase error between the in-phase and quadrature sampling clocks in a quadrature bandpass-sampling receiver comprising: a test tone generator configured to generate an in-phase test tone having an in-phase test tone frequency, and a quadrature test tone; a first multiplier configured to multiply the in-phase test tone with the in-phase sampling clock to generate an up-converted in-phase test tone; a second multiplier configured to multiply the quadrature test tone with the quadrature sampling clock to generate an up-converted quadrature test tone; a first D/A converter configured to receive the up-converted in-phase test tone to generate an in-phase analog test tone; a second D/A converter configured to receive the up-converted quadrature test tone to generate a quadrature analog test tone; a quadrature bandpass sampling delta-sigma analog-to-digital demodulator (QBS-ADD) configured to receive the in-phase analog test tone and the quadrature analog test tone, combine the in-phase analog test tone and the quadrature analog test tone into a single-sided test tone, demodulate the single-sided test tone to baseband to generate an in-phase digital signal based on the in-phase sampling clock, and generate a quadrature digital signal based on the quadrature sampling clock: wherein the in-phase digital signal and the quadrature digital signal are bi-level signals; a digital signal processor (DSP) configured to receive the in-phase digital signal and the quadrature digital signal, to generate a phase-shift control signal; wherein the DSP further comprises: a lowpass filter configured to receive the in-phase digital signal to generate a filtered in-phase signal having M bits of accuracy, and receive the quadrature digital signal to generate a filtered quadrature signal having M bits of accuracy; a multiplier configured to multiply the filtered in-phase signal and the filtered quadrature signal to generate a phase error signal; and an integrator configured to filter and amplify the phase error signal to produce a phase shift control signal; wherein M being an integer between 8 and 64; a sampling clock generator configured to generate the in-phase sampling clock, having an in-phase sampling clock frequency; and a ninety-degree phase shifter configured to receive the in-phase sampling clock, and generate a quadrature sampling clock based on the phase-shift control signal.