Patent ID: 7687350

Claim:
A method for manufacturing a semiconductor memory device, comprising the steps of: performing ion implantation for adjusting a threshold voltage to a semiconductor substrate; forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region; implanting a first conductive impurity ion and a second conductive impurity ion using a mask layer pattern covering the storage node junction region while exposing the bit line junction region, wherein the first conductive impurity ion is implanted in a concentration of about 10% to about 30% of a final impurity concentration of the bit line junction region; forming a gate spacer layer at both sides of the gate stack; and implanting the first conductive impurity ion using the gate stack and the gate spacer layer as an ion implantation mask layer to form a storage node junction region and a bit line junction region having different impurity concentrations, and different junction depths from each other, wherein the first conductive impurity ion is implanted in a concentration of about 70% to about 90% of the final impurity concentration of the bit line junction region.