Patent ID: 7738306

Claim:
A method for implementing a Random Access Memory (RAM) product with Data-Line Bit Switch pass transistors implemented as thick-oxide MOS transistor components and realized as an Integrated Circuit (IC) fabricated in MOS technology, comprising: providing a means for realizing the function of a Bit-Line Sense Amplifier (BLSA) which consists of an amplifying means built with MOS transistors of the PMOS and/or NMOS type, here all together designated as BLSA-transistors; providing a pair of Bit Switch (BS) pass transistors implemented as thick-oxide MOS transistors operating as FET-switches and gate controlled by a BS control signal with maximum voltage VBS thus forming two thick-oxide MOS-transistors named as BS FET-switches; providing a pair of Data-Line (DL) conductors connected to one side of said pair of Bit Switch (BS) pass transistors named as BS FET-switches, which on their other side are connected to certain connection points of said means for realizing the function of a Bit-Line Sense Amplifier (BLSA) and serving as input/output terminal pins therefore feeding a first line with normal potential and a second line with complementary potential together forming a pair of complementary Data-Lines switched by said pair of MOS transistors named as BS FET-switches; connecting said input/output terminal pins of said means for realizing the function of a Bit-Line Sense Amplifier (BLSA) to the drains/sources of said pair of Bit Switch (BS) MOS transistors named as BS FET-switches; connecting the sources/drains of said pair of Bit Switch (BS) MOS transistors named as BS FET-switches to said pair of complementary Data-Lines; realizing said RAM product as an IC fabricated in CMOS technology introducing two thicknesses for oxide layers added to a standard CMOS process in order to produce said thin and thick-oxide MOS transistors; implementing said MOS BLSA-transistors within said means for realizing the function of a Bit-Line Sense Amplifier (BLSA) as thin-oxide MOS transistors with a maximum gate voltage VCC, the core voltage of the device; dimensioning the gates of said MOS BLSA-transistors made as thin-oxide MOS transistors within said Bit-Line Sense Amplifier by its Width-to-Length ratio (W/L) 12 =Y 12 ; implementing said pair of Bit Switch (BS) MOS transistors as thick-oxide MOS transistors with a maximum gate voltage VPP, a charge pump voltage of the device which is greater as VCC; dimensioning the gates of said MOS transistors made as thick-oxide MOS transistors for said Bit Switch transistors by its Width-to-Length ratio (W/L) 34 =Y 34 ; choosing the gate dimension (W/L) 34 =Y 34 of said thick-oxide MOS transistors much smaller than the gate dimension (W/L) 12 =Y 12 of said thin-oxide MOS transistors; choosing said maximum voltage value VBS of said Bit Switch control signal driving the gate of said Bit Switch transistors as high as said maximum gate voltage VPP; and optimizing said maximum voltage value VBS of said Bit Switch control signal within said RAM IC for both, a good write stability and a high write speed.