Patent ID: 8594148

Claim:
A pseudo random signal generation circuit comprising: at least one pattern signal output circuit that includes N stages of D flip-flops, wherein N is an integer of 2 or more, the non-inverting terminal of previous stage D flip-flop is connected to the input terminal of the following stage D flip-flop, the non-inverting terminal of final stage D flip-flop and the non-inverting terminal of the D flip-flop of a stage other than the final stage are connected to the input terminal of the first stage D flip-flop through an exclusive-OR circuit, and that outputs a pattern signal repeating bit patterns of 2 N −1 bits from the non-inverting terminal of the final stage D flip-flop; a signal output circuit that outputs a signal expressing the bit pattern length every time 2 N −1 bits of the pattern signal are output; a selection signal output circuit that, based on the signal expressing the bit pattern length, outputs a selection signal for repeatedly selecting a plurality of terminals, from a plurality of terminals including the non-inverting terminals and the inverting terminals of the pattern signal output circuit, a plurality of terminals at a time; and an output circuit that selects the signals output from the plurality of terminals according to the selection signal, and outputs the selected signal as a pseudo random signal.