Patent ID: 8289785

Claim:
An integrated circuit comprising: at least one logic circuit supplied by a first supply voltage controlled by a first supply voltage input to the integrated circuit; and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage controlled by a second input to the integrated circuit, and wherein the logic circuit is configured to read and write the memory circuit even in the case that a magnitude of the first supply voltage is less than a magnitude of the second supply voltage during use, and wherein the memory circuit comprises at least one memory array, and wherein the memory array comprises a plurality of memory cells that are configured to retain stored values responsive to the power supplied from the second supply voltage, wherein the memory circuit comprises a word line driver circuit supplied by the second supply voltage, wherein a first memory cell of the plurality of memory cells is coupled to receive a word line from the word line driver circuit to activate the first memory cell for access, and wherein the memory circuit further comprises a level shifter circuit supplied with the second supply voltage, wherein the level shifter circuit is coupled to receive an input clock signal from the logic circuit and an input enable signal from the logic circuit, and wherein the level shifter is configured to generate a level-shifted gated clock signal for the word line driver circuit responsive to the input clock signal and input enable signal.