Patent ID: 8191021

Claim:
A method for single event transient filtering of an end user logic design, the logic design including design constraints, in a programmable logic integrated circuit device, the device having physical programmable elements and control elements associated with the programmable elements, the method comprising: (a) converting the end user logic design to first electronic data representing virtual programmable elements; (b) processing the first electronic data to identify locations requiring SET filters; (c) generating second electronic data to represent the SET filters as virtual programmable elements, combining the second electronic data representing the SET filter virtual programmable elements with the first electronic data representing the end user logic design virtual programmable elements, and mapping the combined electronic data representing all of the virtual programmable elements into the physical programmable elements of the programmable logic integrated circuit device including analyzing the mapping, and, if the mapping fails to meet the design constraints, then: (i) adjusting the design constraints, and (ii) repeating the step of generating the SET filters out of virtual programmable elements, combining the SET filter virtual programmable elements with the end user logic design virtual programmable elements, and mapping all of the virtual programmable elements into the physical programmable elements of the programmable logic integrated circuit device; (d) creating a data structure for programming the control elements in accordance with the mapping of all of the combined electronic data; and (e) programming the data structure into a PLD.