Patent ID: 7577932

Claim:
A method for determining adjusted parameters for a transistor simulation, the method comprising: determining an object in a layout of a transistor design to be created with a manufacturing process, the object including a drawn width and a first drawn length and a second drawn length in the layout; determining a generated contour object using a contour simulation to represent an effect of processing variation factors that occur during the manufacturing process using a computer processor, the processing variations factors used to simulate a contoured width that is a contoured representation of the drawn width and a first contoured length and a second contoured length that is a contoured representation of the first and second drawn length; determining an adjusted width of the object based on the generated contour object using the computer processor, the adjusted width including a first value representing the contoured width; determining a plurality of segments in the generated contour object; determining the adjusted length from a plurality of edges in at least a portion of the plurality of segments using the computer processor, the plurality of edges from the first contoured length to the second contoured length in the generated contour object, the adjusted length including a second value representing the contoured length; and outputting, to a transistor simulator, the first value and the second value for the adjusted width and the adjusted length, the first value and the second value for use by the transistor simulator to simulate, in the transistor simulation, the contoured width and the contoured length determined to represent the effect of the processing variation factors.