Patent ID: 8635387

Claim:
A method comprising: generating, by an adapter or a host controller, interrupts upon completion of I/O commands; and sending, by the adapter or the host controller, each of said interrupts from a respective I/O channel of a plurality of I/O channels to a respective processor of a plurality of processors in accordance with an interrupt affinity scheme, each of said interrupts having a respective interrupt identifier associated with the respective processor and the respective I/O channel in the interrupt affinity scheme, wherein the interrupt affinity scheme has associations between the plurality of processors, the plurality of I/O channels, and the respective interrupt identifiers, the interrupt affinity scheme including: a first mapping scheme having a first group of associations between said respective processors and said respective interrupt identifiers, the first group of assignments including each of said respective processors assigned to process the interrupt having its associated respective interrupt identifier, and a second mapping scheme generated based on a usage of a saved copy of said first mapping scheme for distributing said interrupts among said respective processors, said second mapping scheme having a second group of associations between said respective interrupt identifiers and said respective I/O channels, the second group of assignments including each of said respective I/O channels assigned to its associated respective interrupt identifier for sending its interrupt to its respective processor.