Patent ID: 7320097

Claim:
A serial to parallel conversion circuit comprising: a shift register including a plurality of flip-flops, connected in cascade, with a first stage flip-flop being supplied with a transfer start signal, said transfer start signal being sequentially transferred through said shift register, responsive to a shift clock signal; a plurality of latch circuits, receiving respective output signals of said plurality of flip-flops, each of said latch circuits latching and outputting a data signal, serially supplied to a data line, responsive to the respective output signals; and a plurality of control circuits corresponding to said plurality of flip-flops, a first stage control circuit of the plurality of control circuits receiving at least said shift clock signal and a start pulse and each remaining control circuit of the plurality of control circuits receiving at least said shift clock signal and an output signal of a corresponding upstream flip-flop, each of said control circuits setting a state of a corresponding downstream flip-flop, when, in case the output signal of a corresponding downstream flip-flop is in an active state, said shift clock signal undertakes a transition from an active state to an inactive state, so that an output signal of the corresponding downstream flip-flop is in an inactive state, to control a pulse width of said output signal; wherein a frequency of said shift clock signal is set to lower than a data transfer frequency.