Patent ID: 8085519

Claim:
A circuit arrangement for providing a DC operating voltage from a mains voltage with a first mains input (J 1 ) and a second mains input (J 2 ) for connecting a rectified mains voltage, a clocked converter circuit (L 11 , S 11 , C 11 , D 11 , L 12 ) with at least one switching transistor (S 11 ) with a first and a second working terminal, the first working terminal being coupled to the first mains input (J 1 ), a storage capacitor (C 12 ), with a first and a second terminal, the first terminal of the storage capacitor being coupled to the first mains input (J 1 ), an evaluation circuit (DET, DRV), which evaluates the voltage between the mains inputs (J 1 , J 2 ) in such a way that, when a given voltage value or voltage rise is exceeded, the evaluation circuit (DET, DRV) emits a switching signal, the switching arrangement being characterized in that it has a dissipating switch (Th) with a first working terminal, a second working terminal and a control terminal, the first working terminal of the dissipating switch (Th) being coupled to the second working terminal of the switching transistor (S 11 ), the second working terminal of the dissipating switch (Th) being coupled to the second terminal of the storage capacitor (C 12 ), and the switching signal being present at the control terminal, wherein a storage inductor (L 11 ) is connected between the second mains input (J 2 ) and the first working terminal of the dissipating switch (Th), wherein the dissipating switch (Th) comprises a thyristor (Th), and the evaluation circuit comprises a driver circuit (DRV), which provides the control signal at the gate of the thyristor (Th), the driver circuit (DRV) being designed in such a way that the control signal is negative with respect to the cathode of the thyristor (Th) in the time in which the driver circuit (DRV) is not triggering the thyristor.