Patent ID: 7437575

Claim:
An information handling system having a low power mode, said system comprising: information handling equipment having at least one system low power mode; at least one peripheral device coupled to said information handling equipment having low power mode capability; a low power enable bit integral to said at least one peripheral device, wherein, when the low power enable bit is in a first logic state, said at least one peripheral device draws reduced power when said information handling equipment is in the at least one system low power mode; and a non-volatile memory in said information handling equipment, said non-volatile memory having a low power mode bit that is set when the information handling system is currently in a low power mode; a BIOS memory that includes software for setting the low power enable bit of the at least one peripheral device to a first logic level and thereby causing the at least one peripheral device to draw reduced power in response to the low power mode bit of the non-volatile memory being at a first logic level.