Patent ID: 8072035

Claim:
A semiconductor device comprising: (a1) a first gate insulation film formed on a semiconductor substrate; (a2) a first gate electrode formed on the first gate insulation film; (a3) a first MISFET having a first source region and a first drain region formed so as to align with the first gate electrode; (b1) a second gate insulation film formed on a semiconductor substrate; (b2) a second gate electrode formed on the second gate insulation film and formed with a conductive film of the same layer as that of the first gate electrode; (b3) a second MISFET having a second source region and a second drain region formed so as to align with the second gate electrode, wherein a film thickness of the second gate insulation film is thinner than that of the first gate insulation film; (c) an insulation film formed over the first MISFET and the second MISFET; (d) a first plug penetrating the insulation film and electrically connected to the first source region; (e) a second plug penetrating the insulation film and electrically connected to the first drain region; (f) a third plug penetrating the insulation film and electrically connected to the second source region; (g) a fourth plug penetrating the insulation film and electrically connected to the second drain region; (h) a first source wire formed over the insulation film and electrically connected to the first plug; (i) a first drain wire formed over the insulation film and electrically connected to the second plug; (j) a second source wire formed over the insulation film and electrically connected to the third plug; and (k) a second drain wire formed over the insulation film and electrically connected to the fourth plug, wherein the first source wire, the first drain wire, the second source wire, and the second drain wire are formed on a same layer, wherein when a distance from an interface between the semiconductor substrate and the first gate insulation film to an upper surface of the first gate electrode is defined as a, and a distance from the upper surface of the first gate electrode to an upper surface of the insulation film on which the first source wire, the first drain wire, the second source wire, and the second drain wire are formed is defined as b, a relation of a>b is established, wherein the first gate electrode and the first source wire are arranged not to be overlapped planarly with each other, and the first gate electrode and the first drain wire are arranged not to be overlapped planarly with each other, and wherein the second gate electrode and the second source wire are arranged to be overlapped planarly with each other, and the second gate electrode and the second drain wire are arranged to be overlapped planarly with each other.