Patent ID: 7345530

Claim:
A switched-capacitor amplifier circuit for sampling a pair of input signals, the switched-capacitor amplifier circuit comprising first and second pairs of sampling capacitors, each pair of sampling capacitors coupled to sample a respective input signal and transfer charge associated with the sampled input signal to a first input terminal of an amplifier where a second input terminal of the amplifier is coupled to a first reference voltage, the switched-capacitor amplifier circuit being fabricated in a dual gate oxide fabrication process having thick gate oxide devices as high voltage MOS transistors and thin gate oxide devices as low voltage MOS transistors, the switched-capacitor amplifier circuit further comprising: a voltage regulator coupled to receive the first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage of the switched-capacitor amplifier circuit; a clock signal generator receiving a master clock signal and generating a first clock signal and a second clock signal based on the master clock signal and referenced to the first power supply voltage, the first and second clock signals having opposite phase and being non-overlapping and being used to control the input signal sampling and charge transfer operations of the first and second pairs of sampling capacitors, the clock signal generator further generating a third clock signal related to the first clock signal and a fourth clock signal related to the second clock signal, the third and fourth clock signals being referenced to the first regulated output voltage; a first switch coupled between the bottom plates of the first pair of sampling capacitors and the first reference voltage, the first switch being controlled by the third clock signal; a second switch coupled between the bottom plates of the second pair of sampling capacitors and the first reference voltage, the second switch being controlled by the fourth clock signal; a third switch coupled between the bottom plates of the first pair of sampling capacitors and the first input terminal of the amplifier, the third switch being controlled by the fourth clock signal; and a fourth switch coupled between the bottom plates of the second pair of sampling capacitors and the first input terminal of the amplifier, the fourth switch being controlled by the third clock signal, wherein each of the first, second, third and fourth switches is implemented using one or more low voltage MOS transistors and the first regulated output voltage has a voltage value suitable for operating the low voltage MOS transistors.