Patent ID: 8526237

Claim:
A memory, comprising: first and second arrays of non-volatile re-programmable memory elements, wherein a selected row of re-programmable memory elements in each array is accessible by a selected word line and a selected row of bit lines at a plurality of crossing with the selected word line; a reference row of non-volatile reprogrammable memory elements in each of the first and second arrays for storing a value associated a location of the word line at each crossing so as to provide a reference adjustment to compensate the location due to finite resistance along the word line; a row of sensing circuits disposed between first and second arrays, a set of global bit lines traversing said first and second arrays and said row of sensing circuits, each global bit line having in-line first and second segments, the first segment for coupling a respective bit line of a selected row of bit lines in said first array to a respective sensing circuit in said row of sensing circuits, and the second segment for coupling a respective bit line of a selected row of bit lines in said second array to a respective sensing circuit in said row of sensing circuits; and wherein when coupled to sense a selected row in said first array, said row of sensing circuits simultaneously are coupled to reference the reference row in the second array; and when coupled to sense a selected row in said second array, said row of sensing circuits simultaneously are coupled to reference the reference row in said first array.