Patent ID: 8185338

Claim:
An interface module comprising: a test data line configurable in an input mode to receive test input data and in an output mode to output test output data; a test clock line configured to receive a test clock signal; a controlling module operatively coupled to the test clock line and operable in response receipt of the test clock signal to generate an unlock signal and a lock signal; a processing module operatively coupled to the controlling module and including an instruction register and an instruction decoder, the processing module operable in response to the unlock signal to load an instruction in the instruction register, said instruction decoded by the instruction decoder to generate test control and test data line configuration signals, and further operable in response to the lock signal to enable output of the generated test control signals; wherein the test data line is configured in the input mode and output mode in response to said test data line configuration signal; and a storage module operatively coupled to the test data line and operable in response to the test control signal and test clock signal to scan test input data from the test data line into the storage module based on the decoded instruction and scan test output data from the storage module to the test data line based on the decoded instruction.