Patent ID: 7880233

Claim:
A transistor with raised source and drain formed on SOI substrate comprising: an SOl substrate including a substrate layer, a middle insulation layer, and a silicon layer pattern; device isolation insulation layers over and contacting the middle insulation layer, and beside and contacting the silicon layer pattern; a gate insulation layer formed over a portion of the silicon layer pattern; a gate insulation layer pattern formed beside the device isolation insulation layers and apart from the gate insulation layer and having the same height and material with the gate insulation layer; a gate electrode including a first gate conductive layer pattern formed over a portion of the gate insulation layer and a second gate conductive layer pattern formed over the first gate conductive layer pattern; a first gate conductive layer spacers formed on and contacting the gate insulation layer pattern and a sidewall of the device isolation insulation layers and having same material with the first gate conductive layer pattern; a insulation layer spacers formed adjacent to sides of the gate electrode and over a portion of the gate insulation layer; source and drain conductive layer formed over the silicon layer pattern and beside the gate insulation layer, the gate insulation layer pattern, the first gate conductive layer spacers and a portion of the insulation layer spacers; and a salicide layer formed over each of the gate electrode and the source and drain conductive layer.