Patent ID: 8521921

Claim:
A system comprising: a processor; a memory; and a direct memory access (DMA) controller configured to: receive an allowable number of data transmissions, the allowable number determined by the processor; receive a request to transfer data, the request received after the allowable number is determined by the processor; determine, independent of the processor, that a data transfer number associated with the request to transfer data is less than, greater than, or equal to the allowable number; responsive to the data transfer number being less than or equal to the allowable number, approve, independent of the processor, the request to transfer data; responsive to the data transfer number being greater than the allowable number, disapprove, independent of the processor, the request to transfer data; responsive to disapproving the request to transfer data, interrupt the processor; responsive to interrupting the processor, receive a new number of allowable data transmissions from the processor.