Patent ID: 8095747

Claim:
An apparatus, comprising: a memory controller configured to control first and second memory components; a point-to-point data bus configured to pass data between the memory controller and the memory components, the point-to-point data bus having a direct connection from each memory component to the memory controller; and a daisy chained address bus configured to pass commands between the memory controller and the memory components, the address bus having a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component, wherein each memory component has a data interface connected to the point-to-point data bus, wherein if the apparatus is set to depth expansion a portion of each data interface is de-powered while the memory components exchange data with the memory controller over the data bus, wherein if the apparatus is not set to depth expansion the entire data interfaces are powered while the memory components exchange data with the memory controller over the data bus.