Patent ID: 7557872

Claim:
A thin film transistor array, comprising: a substrate, comprising a plurality of pixel shots; a plurality of thin film transistors, respectively disposed in each pixel shot and each thin film transistor comprising a gate, a channel layer, a source and a drain, wherein the channel layer is disposed between the source, the drain and the gate, and a first overlapped area is formed between the source and the gate, thereby forming a parasitic capacitance between the source and the gate; a plurality of pixel electrodes, respectively disposed in each pixel shot, wherein each drain extends over its corresponding channel layer along a direction to be underneath its corresponding pixel electrode, and each drain is electrically connected to the pixel electrode; a plurality of common-used distributed lines, disposed on the substrate and a portion of the common-used distributed lines being underneath the pixel electrode; a plurality of conductive blocks, respectively disposed in each pixel shot and over the common-used distributed lines, wherein the plurality of conductive blocks is respectively electrically connected to the common-used distributed lines; and a plurality of auxiliary electrodes, respectively disposed underneath the pixel electrode in each exposure shot and each auxiliary electrode extending over its corresponding common-used distributed line along the direction to the corresponding common-used distributed line's one side, wherein a plurality of first storage capacitances are formed between the plurality of conductive blocks and their corresponding auxiliary electrodes, a second overlapped area is formed between each auxiliary electrode and its corresponding common-used distributed line, and the auxiliary electrodes are respectively electrically connected to their corresponding pixel electrodes to form a plurality of second storage capacitances between the auxiliary electrodes and their corresponding common-used distributed lines.