Patent ID: 8329565

Claim:
A method of fabricating a semiconductor structure having a reduced number of surface dislocations comprising: enhancing the extent of surface disturbance about a plurality of emergent surface dislocations appearing at a semiconductor surface by: etching the semiconductor surface under first etch conditions selected to encourage etching associated with the surface dislocations, wherein the etching is enhanced by the simultaneous addition of laser or UV energy; and forming an intermediate semiconductor layer under first epitaxial growth conditions selected to encourage opening of growth pits associated with the etched surface dislocations; depositing a layer of a dielectric masking material so as to cover in a discontinuous manner, at least, the disturbed portions of the surface about a plurality of emergent surface dislocations, portions of the surface being covered with masking material while other portions of the surface not being so covered, and forming a following semiconductor layer with substantially continuous lateral extent and a reduced number of surface dislocations.