Patent ID: 8769458

Claim:
A prototype verification system for a high-end fault-tolerant computer, comprising a plurality of single junction prototype verification systems and an interconnection router chipset; wherein, the plurality of single junction prototype verification systems are interconnected with each through the interconnection router chipset; wherein, each single junction prototype verification system comprises: a computer board, which is a four-path tightly-coupled computer board; a chip verification board, comprising two junction controller chipsets; wherein, each junction controller chipset comprises: two field-programmable gate array (FPGA) chips which bear a logic of a junction controller together; and an interconnection board, comprising two FPGA chips; wherein, each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets; wherein the four-path tightly-coupled computer board comprises 4 CPUs, the 4 CPUs are interconnected internally, and share memories with each other; and all CPUs in the plurality of the single junction prototype verification systems are interconnected with each other through the interconnection router chipset, and share memories.