Patent ID: 6962870

Claim:
A method of manufacturing a semiconductor device, comprising: forming a lower-layer interconnection; forming a protective film on a surface of the lower-layer interconnection; forming a multilayer-structured film by stacking a first porous film, a first non-porous film, a second porous film, and a second non-porous film on a surface of the protective film in this order; forming a via hole in the first porous film and the first non-porous film, and forming an interconnect trench communicating with the via hole in the second porous film and the second non-porous film, by dry etching the multilayer-structured film using a resist mask; removing the resist mask; removing the protective film exposed at a bottom of the via hole after removing the resist mask; and forming an upper-layer interconnection of dual damascene structure by embedding an interconnect material in the via hole and the interconnect trench, the upper-layer interconnection being connected to the lower-layer interconnection, wherein for the first non-porous film, used is a multilayer film including at least two layers in which a first layer, which is located close to the first porous film, is made of a material that has a high etching selectivity ratio relative to the protective film, and a second layer, which is located closer to the second porous film than the first layer is, is made of a material that has a high etching selectivity ratio relative to the resist mask and the second porous film.