Patent ID: 7656705

Claim:
A method of programming two or more memory cell element-pairs on a wordline of a multi-level flash memory array in a single programming phase, the memory cell element-pairs individually having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising: providing one or more unprogrammed memory cell core element-pairs of the two or more memory cell element-pairs on the word line to be programmed; providing one or more memory cell learn element-pairs of the two or more memory cell element-pairs on the wordline for determining a program drain voltage therefrom; determining a program verify gate voltage and program verify current for each of the program levels on the wordline of the memory array; performing a patterned programming operation on the memory cell learn element-pairs of the wordline of the array using one or more program patterns, the determined program verify gate voltage, and the determined program verify current, until each element of the learn element-pairs generally corresponds to the respective program pattern; learning a program drain voltage required to program the wordline to a predetermined one of the three or more data levels; and performing a core programming operation on the core element-pairs of the array using the learned program drain voltage and the determined program verify current, until each element of the core element-pairs generally corresponds to the respective program pattern.