Patent ID: 8713411

Claim:
A memory device, comprising: a memory cell array; and a processor including at least one of a decoder and an encoder, wherein the processor is configured to adjust a redundant information rate of each of a plurality of channels, where each of the channels is a path of the memory cell array from which data is at least one of stored and read, the redundant information rate is adjusted by generating at least one codeword based on information from a previous codeword, the processor includes the decoder, the decoder being configured to perform error-control code (ECC) decoding with respect to a first codeword generated from first data read from the memory cell array to estimate a first message, to combine the estimated first message and second data read from the memory cell array to generate a second codeword, and to perform ECC decoding with respect to the second codeword to estimate a second message, and the ECC decoding is performed according to a decoding scheme which uses systematic codes, the ECC decoding including dividing the first codeword into the first message and a first parity, and dividing the second codeword into the second message and a second parity, where each of the first parity and the second parity is redundant information for an occurrence of an error.