Patent ID: 7276950

Claim:
A clock delay circuit comprising: a delay circuit section for delaying a clock signal with a different delay amount to provide a plurality of delay clock signals; a selection circuit section for selecting and providing any one of the plurality of delay clock signals that are provided from said delay circuit section; and jitter suppression elements that are connected in series between said delay circuit section and said selection circuit section; wherein: said delay circuit section is of a configuration wherein a plurality of delay circuits are connected in a cascade configuration for delaying clocks each having a fixed delay amount; said selection circuit section is of a configuration wherein a plurality of selection circuits are connected in a cascade configuration, each of said selection circuits being associated with a respective delay circuit of said plurality of delay circuits and being configured to select and provide delay clock signal that has been provided from the delay circuit associated with said selection circuit; and said jitter suppression elements are associated with each of said plurality of delay circuits and each of said plurality of selection circuits, each of said jitter suppression elements being connected in series between the delay circuit and the selection circuit associated with said jitter suppression elements.