Patent ID: 6989564

Claim:
A nonvolatile semiconductor storage apparatus comprising: a NOR type cell array including memory cells arranged in a row direction and a column direction, each of the memory cells having a source region, a drain region and a channel region formed in a well region formed in a surface layer of a semiconductor substrate, a floating gate formed on the well region via a gate insulating film and a control gate formed on the floating gate via an inter-gate insulating film, two adjacent the memory cells arranged in the column direction forming a set and sharing the drain region, two adjacent sets of the memory cells arranged in the column direction sharing the source region, and a plurality of columns of the memory cells being isolated by trench type element isolation regions; a plurality of word lines arranged on the cell array and extending in the row direction in correspondence to a plurality of rows, each of the word lines being commonly connected to a control gate of each of the memory cells on a corresponding row; a plurality of local source lines formed of metal wirings, the local source lines being arranged on the cell array and extending in the row direction in correspondence to a plurality of rows, each of the local source lines extending in the row direction to run on the source regions of the memory cells on a corresponding row and the element isolation regions isolating the columns of the memory cells, and being commonly connected to the source regions of the memory cells on the corresponding row; a plurality of bit lines formed of metal wirings, the metal wirings being arranged on the cell array and extending in the column direction in correspondence to a plurality of columns, and each of the bit lines being commonly connected to the drain regions of the memory cells on a corresponding column; and a plurality of main source lines formed of metal wirings, the main source lines being arranged intermittently between the columns of the bit lines on the cell array and extending in the column direction, and each of the main source lines being commonly connected to the local source lines, wherein a height of embedded material layers in the element isolation regions under the local source lines or a height of a portion of the embedded material layers contacting the semiconductor substrate is lower than an upper surface of the source regions under the local source lines, and the local source lines and the well region are electrically connected to each other in the cell array.