Patent ID: 7248516

Claim:
A method of testing a memory device, comprising: accessing a memory array to generate a page of output containing some number of words more than one, wherein each word of the page of output has two or more bit locations; for a first bit location of each word of the page of output, driving a first current level for each word whose first bit location has a first data value and sinking a second current level for each word of the page of output whose first bit location has a second data value, wherein the first current level is greater than a product of the second current level times the number of words minus one; for the first bit location of each word of the page of output, driving a third current level for each word whose first bit location has the first data value and sinking a fourth current level for each word of the page of output whose first bit location has the second data value, wherein the fourth current level is greater than a product of the third current level times the number of words minus one; summing the first and second current levels for the first bit location for each word of the page of output to generate a first output signal having a logic level; summing the third and fourth current levels for the first bit location for each word of the page of output to generate a second output signal having a logic level; comparing the first and second output signals corresponding to the first bit location; disabling output for data signals corresponding to at least the first bit location if the first and second output signals corresponding to the first bit location have different logic levels; attempting to read a word of the page of output; and determining whether output is disabled for at least the first bit location, wherein disabled output is indicative of failure of the memory device.