Patent ID: 7171631

Claim:
A method of generating a design of a user-configurable processor having enhanced jump control, the method comprising: providing a base processor core configuration having a pipeline comprising at least fetch, decode, and execute stages, and an instruction set comprising at least one of each of flag setting and jump instructions; and modifying said base core configuration such that pipeline control logic associated with said core is configured to, during program execution, treat a flag setting instruction which is disposed within said pipeline at a stage later than that of a subsequent jump instruction as logically disposed at an earlier stage; wherein said act of providing a base processor core configuration core comprises providing a core configuration adapted to (i) stall a first instruction within said decode stage of said pipeline; (ii) execute a second instruction within said execute stage of said pipeline; (iii) move the executed instruction within said execute stage to another stage; and (iv) insert a blank slot into said execute stage of said pipeline to prevent duplicative processing of said second instruction.