Patent ID: 7636274

Claim:
A memory module comprising: a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks, each DDR memory device having a corresponding load; a circuit comprising a logic element and a register, the circuit electrically coupled to the plurality of DDR memory devices and configured to be electrically coupled to a memory controller of a computer system to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and chip-select signals, the set of input signals compatible with a system memory domain of the computer system, the circuit configurable to be responsive to the set of input signals by selectively isolating one or more of the loads of the DDR memory devices from the computer system, the circuit configurable to translate between the system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain has a first memory density per rank, and the physical memory domain has a second memory density per rank less than the first memory density per rank; and a phase-lock loop device operationally coupled to the plurality of DDR memory devices, the logic element, and the register.