Patent ID: 7500211

Claim:
A unit cell that forms a rectangular-shaped fundamental unit in a layout of a semiconductor integrated circuit device and in which a first power wiring is wired in a first direction by a layout arrangement, the unit cell comprising: an input/output terminal that includes at least one wiring connecting portion connectable to a signal wiring wired on an upper level wiring layer; and at least one upper-layer wiring region that is formed, through the unit cell in a second direction orthogonal to the first direction, at a predetermined position in the first direction, wherein the input/output terminal is arranged so that the at least one wiring connecting portion exists outside the at least one upper-layer wiring region, and wherein the at least one wiring connecting portion is an intersection between A) a wiring pitch determined based on a wiring width and a wiring interval of the signal wiring in the first direction and B) a wiring pitch of the signal wiring in the second direction and is a site where a via for connection between wiring layers can be formed.