Patent ID: 8751755

Claim:
An external memory coupled to a mass storage controller, wherein the mass storage controller is coupled to a plurality of groups of flash memory devices, the external memory comprising: a portion for a data buffer for holding data received by the mass storage controller from one or more hosts, and for holding data received by the mass storage controller from the plurality of groups of flash memory devices coupled to the mass storage controller, each group of flash memory devices comprising a plurality of banks, each bank comprising a plurality of blocks, each block comprising a minimum size erase unit of flash memory and further comprising a plurality of superpages, each superpage comprising a plurality of flash pages, wherein each group of flash memory devices further includes a plurality of superblocks, wherein each superblock includes a corresponding block from each bank of the plurality of banks in the group of flash memory devices; a portion for a first table including a series of physical addresses in the plurality of groups of flash memory devices, the series of physical addresses arranged in an order reflecting a logical addressing system used by the one or more hosts, the first table including one physical flash memory address for every n addresses from the logical addressing system, n being larger than one and representing the number of logical addresses assignable to each superpage, and further including a field to store a count for the number of times each of the physical flash memory addresses has been accessed; a portion for a plurality of second tables, the plurality of second tables comprising a separate second table for each group of flash memory devices, each second table indicating, for each superpage in a respective group of flash memory devices, whether the superpage contains valid data, and for each superblock in the respective group of flash memory devices, a count for the number of superpages in the superblock which store invalid data and a count for the number of times the superblock has been erased; and an interface to the mass storage controller, wherein the mass storage controller is configured to generate and store aggregated data in the external memory, the aggregated data including data stored in the first table and the plurality of second tables in the external memory.