Patent ID: 7582512

Claim:
A semiconductor device fabrication method comprising: arranging, on one side of a base plate carrying at least one first conductive layer, a plurality of semiconductor constructing bodies each having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate, such that said plurality of semiconductor constructing bodies are spaced apart from each other; forming an insulating layer on said one side of the base plate around each semiconductor constructing body; forming a plurality of second conductive layers each having at least one layer on the semiconductor constructing body and insulating layer, such that said plurality of second conductive layers are electrically connected to the external connecting terminals of the semiconductor constructing body; defining a cut line on the insulating layer of the base plate, the cut line defining a region such that at least one semiconductor constructing body is included in the region; forming a vertical conducting portion which includes the cut line to extend to the cut line, and electrically connects the first conductive layer and at least one of the second conductive layers; and cutting the insulating layer, base plate, and vertical conducting portion along the cut line, thereby obtaining a plurality of semiconductor devices each having a portion of the vertical conducting portion on a side surface.