Patent ID: 7243192

Claim:
A system controller device adapted to be connected between a microprocessor and a main memory and to provide an interface to the main memory, the system controller device comprising: a memory interface circuit configured to receive a main memory address from the microprocessor over a bus that interconnects the microprocessor and the system controller device, and to use the main memory address to perform a memory read operation in which data is read from the main memory; and a cache tag comparison circuit configured to receive a cache tag value as the cache tag value is read by the microprocessor from an external cache memory that is external to the microprocessor and the system controller device, and to compare the cache tag value with the main memory address received by the memory interface circuit to determine whether the data associated with the memory read operation resides in said external cache memory; wherein the memory interface circuit is configured to begin the memory read operation before the cache tag comparison circuit compares the cache tag value with the main memory address, and the cache tag comparison circuit is further configured to prevent the memory interface circuit from completing the memory read operation if the comparison of the cache tag value with the main memory address reveals that said data resides in the external cache memory.