Patent ID: 8217682

Claim:
An integrated circuit driver, comprising: a bias control circuit to provide a bias signal for a first mode and a second mode; wherein the bias signal has a first voltage level associated with operation in the first mode and a second voltage level associated with operation in the second mode; an output driver circuit to receive the bias signal, the output driver circuit including a first NMOS transistor that is gated with the bias signal, and only the first NMOS transistor is biased for operating the output driver in the first and second modes; wherein the output driver circuit operates in the first mode in response to the first NMOS transistor being partially conductive, in response to the first voltage level of the bias signal, wherein when the first NMOS transistor is partially conductive the first NMOS transistor is in a linear region of operation that is closer to a saturation region of operation of the first NMOS transistor than to a region of operation of zero drain-to-source voltage, and operates in the second mode in response to the first NMOS transistor being fully conductive in response to the second voltage level of the bias signal; wherein in the first mode, the output driver circuit operates as a supply referenced driver; and wherein in the second mode, the output driver circuit operates as a ground referenced driver.