Patent ID: 8324022

Claim:
A method for manufacturing a three-dimensional electronic system, comprising: (a) providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure comprises a first contact pad at a first main side of the first substrate; (b) providing a second substrate with a second main side; (c) forming a recess in the second substrate from the second main side to form a vertical contact area; (d) after step (c), epitaxial growth of a semiconductor layer on the second main side of the second substrate with the vertical contact area; (e) forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer, the semiconductor layer serving as a substrate layer for the semiconductor device; (f) removing substrate material from a side of the second substrate opposite to the second main side, so that the vertical contact area at the opposite side is electrically exposed; (g) arranging the first and second substrates on top of each other aligning the vertical contact area with the first contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area and the first contact pad.