Patent ID: 7271867

Claim:
A method of fabricating a thin film transistor array substrate for a liquid crystal display, the method comprising the steps of: forming a gate line assembly on an insulating substrate, the gate line assembly having gate lines, and gate electrodes connected to the gate lines; depositing a gate insulating layer onto the substrate with the gate line assembly; forming a semiconductor layer on the gate insulating layer; forming a data line assembly, the data line assembly having data lines crossing over the gate lines, source electrodes connected to the data lines while being positioned close to the gate electrodes, and drain electrodes positioned opposite to the source electrodes with respect to the gate electrodes; depositing a protective layer; forming an organic insulating layer on the protective layer; patterning the organic insulating layer to thereby form first contact holes exposing the protective layer over the drain electrodes; dry-etching the protective layer exposed through the first contact holes such that the drain electrodes are exposed; ashing the organic insulating layer to remove a dry-etch residue or solid film; curing the organic insulating layer with contraction and reflow after etching the protective layer to remove an undercut and form gradually sloped step coverage of the insulating layer; and forming pixel electrodes on the protective layer such that the pixel electrodes are connected to the drain electrodes through the first contact holes, wherein a profile of the contact holes is changed according to the sequence of dry-etching, ashing, and curing with contraction and reflow.