Patent ID: 7420212

Claim:
A flat panel display, comprising: a substrate; a plurality of signal lines arranged on the substrate, the signal lines comprising a data line, a common power line, and a scan line, wherein the data line and the common power line are arranged substantially parallel with each other and crossing the scan line; a unit pixel region defined by a crossing arrangement of the signal lines and having a pixel driving circuit region and an emission region; a pixel driving TFT positioned in the pixel driving circuit region, the pixel driving TFT including a semiconductor layer having a first end and a second end, and a gate electrode that corresponds to a predetermined portion of the semiconductor layer, wherein the gate electrode is formed in a same layer with one of the entire data line and the common power line; a pixel electrode electrically connected to the pixel driving TFT and positioned in the emission region; and a capacitor comprising a lower electrode arranged in a same layer as the semiconductor layer and an upper electrode arranged in the same layer as the gate electrode, the lower electrode being separated from the semiconductor layer and connected to the common power line through a capacitor interconnection line arranged in a same layer as the pixel electrode, wherein the common power line transmits a common voltage for driving the pixel electrode.