Patent ID: 7683819

Claim:
A pipeline analog-to-digital converting circuit including one stage and a stage succeeding said one stage, each stage comprising: a sampling capacitor that samples an input signal voltage from a preceding stage; a sub analog-to-digital converting circuit that converts the input signal voltage from the preceding stage to output a digital signal; a sub digital-to-analog converter that selects a reference voltage corresponding to the digital signal output from said sub analog-to-digital converter; and an amplifier, for which the sampling capacitor that has sampled the input signal voltage is connected as a feedback capacitor in an operational amplification time period in which said amplifier amplifies a difference voltage between the sampled voltage of the input signal and the reference voltage, said amplifier being shared by said one stage and said succeeding stage, the sampling capacitor of said one stage comprising a plurality of divided sampling capacitors, some of the plurality of divided sampling capacitors in said one stage being adopted as sampling capacitors of said succeeding stage.