Patent ID: 7022577

Claim:
A method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate defining a gate structure and first and second regions, each region being provided on one side the gate structure; ion implanting dopant impurities over a first time period into the first and second regions of the semiconductor device with a first ion energy of implanting the dopant impurities over the first time period; ion implanting the dopant impurities over a second time period into the first and second regions of the semiconductor device with a second ion energy of implanting the dopant impurities over the second time period; ion implanting the dopant impurities over a third time period into the first and second regions of the semiconductor device with a third ion energy of implanting the dopant impurities over the third time period; and activation annealing the dopant impurities to form at least one doped region extending below the surface of the semiconductor substrate, wherein the three separate ion-implantation steps are performed to provide the first and second regions with ultra shallow junctions.