Patent ID: 7851884

Claim:
A field-effect transistor comprising the following layers built up on a GaAs semiconductor substrate comprising gallium and arsenic, said built up layers comprising: an i-type GaAs layer serving as a buffer layer and comprising gallium and arsenic and containing no carrier impurities; an i-type InGaAs layer serving as a two-dimensional gas layer and comprising indium, gallium and arsenic and containing no carrier impurities; an n-type AlGaAs layer serving as an electron supply layer and comprising aluminum, gallium and arsenic and containing an n-type carrier impurity; a gate electrode being provided on and in linear Schottky contact with said n-type AlGaAs layer serving as the electron supply layer; an n-type InGaP layer serving as an etching stop layer spaced away from both sides of the gate electrode and comprising indium, gallium and phosphorous and containing an n-type carrier impurity; and an i-type GaAs layer serving as a spacer layer and comprising gallium and arsenic and containing no carrier impurities is provided between said i-type InGaAs layer serving as the two-dimensional electron gas layer and said n-type AlGaAs layer serving as the electron supply layer.