Patent ID: 7821138

Claim:
A semiconductor device, comprising: an n-channel transistor forming region; a p-channel transistor forming region; contact plugs formed on both said n-channel transistor forming region and said p-channel transistor forming region; and an element isolation region which separates said n-channel transistor forming region and said p-channel transistor forming region, wherein first contact plugs of said contact plugs of said p-channel transistor forming region are extended in the longitudinal direction of a gate electrode with respect to second contact plugs of said contact plugs of said n-channel transistor, a difference between stress in said p-channel transistor forming region and stress in said n-channel transistor forming region is generated by a difference in the shapes of said first contact plugs and said second contact plugs; and one of said first contact plugs and said second contact plugs are the minimum size and the other of said first contact plugs and said second contact plugs are larger than said minimum size in a direction that is parallel with said gate electrode.