Patent ID: 7667316

Claim:
A semiconductor integrated circuit comprising: an integrated power transistor formed on a semiconductor substrate; an interlayer insulation film formed on the power transistor; a plurality of first metal patterns which comprise a first metal layer formed right above the power transistor, in the interlayer insulation film, and function as a first electrode of the power transistor; a plurality of second metal patterns which comprise the first metal layer and function as a second electrode of the power transistor; a plurality of first buses which comprise a second metal layer formed right above the first metal layer, in the interlayer insulation film, and are electrically connected with, of a plurality of the first metal patterns, a corresponding first metal pattern; and a plurality of second buses which comprise the second metal layer and are electrically connected with, of a plurality of the second metal patterns, a corresponding second metal pattern, wherein one contact pad is provided to each of a plurality of the first buses and each of a plurality of the second buses.