Patent ID: 7310754

Claim:
A test circuit for a second macro block that performs transmission and reception processing to and from a first macro block at a first clock frequency, the test circuit comprising: a test transmission buffer which stores a transmission data signal from a test input terminal at a second clock frequency that is lower than the first clock frequency; and a test reception buffer which outputs a reception data signal from the second macro block to a test output terminal at a third clock frequency that is lower than the first clock frequency, wherein, after storing the transmission data signal from the test input terminal at the second clock frequency, the test transmission buffer outputs the stored transmission data signal to the second macro block at the first clock frequency, the second macro block including a physical-layer circuit for data communications, and wherein, after storing the reception data signal from the second macro block at the first clock frequency, the test reception buffer outputs the stored reception data signal to the test output terminal at the third clock frequency.