Patent ID: 7245534

Claim:
A nonvolatile semiconductor memory, comprising: a memory cell array constituted by a plurality of word lines, a plurality of bit lines, and electrically erasable/writable memory cell transistors, which have respective tunnel insulating films and are arranged at intersections of the plurality of word lines and the plurality of bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer; wherein, channel width of the word line transfer transistor is at least six times width of the word line contact plug, and distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.