Patent ID: 7508062

Claim:
An integrated circuit package comprising: a multi-layer package substrate configured for use without decoupling capacitors and arranged in a stripline configuration with a plurality of striplines, each stripline having at least one signal plane positioned between an associated pair of reference planes, the multi-layer package having an upper package surface and a lower package surface configured so that the upper package surface has a first plane formed thereon wherein the first plane comprises a reference plane of a first stripline and the lower package surface having a second plane formed thereon wherein the second plane comprises one of a reference plane of a second stripline; a first dielectric layer formed over the upper package surface and first plane; a second dielectric layer formed over the lower package surface and second plane; a first supplemental plane formed on a top surface of the first dielectric layer, the first supplemental plane having a polarity opposite of the first plane, the first supplemental plane being configured to include a decoupling capacitor; a second supplemental plane formed on a bottom surface of the second dielectric layer, the second supplemental plane having a polarity opposite of the second plane; and at least one decoupling capacitive element.