Patent ID: 6973612

Claim:
Apparatus for detecting and correcting all 15 possible familial bit errors in data from any single 4-bit RAM in a first data word of 20 bits and for also detecting all double bit, non-familial errors and for detecting uncorrectable multi-bit errors in said first 20 bit word, wherein said first 20 bit word is a data word storable in a RAM memory within a computer system and retrievable therefrom, and wherein said computer system has input circuits to said RAM memory for sending said first data word to storage in said RAM memory and output circuits for retrieving a 128 bit data word from said storage in said RAM memory, wherein said retrieved 20 bit data word will be equivalent to said first data word if no errors occur, said apparatus comprising: a check bit generator associated with said input circuits for generating in a predetermined manner, a generated 12 check bits from said 20 bit data word and for sending said generated 12 check bits together with said 20 bit data word into said RAM memory for storage associated with said 20 bit data word as stored check bits, a check bit regenerator associated with said output circuits for generating in said predetermined manner, a regenerated 12 check bits from said retrieved 20 bit data word, a syndrome generator for generating 12 syndrome bits from said regenerated 12 check bits wherein each of said regenerated 12 check bits is modula 2 added to a one of said generated check bits, producing thereby a 12 bit syndrome, a syndrome decode and comparator circuit for producing a no error signal, a correctable data signal, and a correctable check bit signal, wherein said correctable data signal is produced by determining if a correction was required by decoding said 12 bit syndrome through a syndrome decode circuit, said correctable check bit signal is produced by determining if a correction is required for said generated 12 check bits, and wherein said no error signal is produced if said syndrome signal value is a predetermined value and further comprising: a multi-bit undetectable (MUE) error signal generating circuit for generating an MUE signal if a said no error signal indicates an error and either of said correctable check bit signal or said correctable data signal.