Patent ID: 7543250

Claim:
A synchronous apparatus integrated on a chip, comprising: a plurality of agent functional blocks integrated on the chip and connected to a shared functional block through a corresponding plurality of unidirectional packet buses; and a set of repeaters integrated on the chip, the set of repeaters including a repeater comprising a register positioned to segment a packet bus connecting an agent functional block and the shared functional block, the repeater receiving a packet from a first unit on a first clock cycle, the repeater transmitting the packet to a second unit on a second clock cycle subsequent to the first clock cycle, wherein the first unit and the second unit are selected from the agent functional block and the shared functional block; wherein a communications protocol between the shared functional block and the agent functional block is substantially capable of operation for a source-receiver traveltime having a first value and a second value, wherein the first value is a first number of clock cycles defining a signal traveltime between the shared functional block and agent functional block through the repeater, and the second value is a second number of clock cycles different from the first number of clock cycles; wherein a first physical connection distance between the repeater and the agent functional block over the packet bus does not exceed a single-clock-cycle length; and wherein a second physical connection distance between the shared functional block and the agent functional block over the packet bus exceeds the single-clock-cycle length.