Patent ID: 8331520

Claim:
A phase-locked loop circuit comprising: an oscillator operable to oscillate at a frequency corresponding to a phase difference signal; a divider operable to generate a first clock obtained by dividing an output of the oscillator and a second clock higher than the first clock in frequency; and a phase comparator, wherein the phase comparator includes: a first detector which receives the first clock, the second clock, and a reference clock, detects a phase difference between the first clock and the reference clock to an accuracy of a first time period given by a cycle of the second clock, and outputs the phase difference signal corresponding to the detected phase difference until the detected phase difference reaches a predetermined range; and a second detector which receives the first clock and the reference clock, detects the phase difference between the first clock and the reference clock to an accuracy of a second time period shorter than the first time period after the phase difference detected by the first detector reaches the predetermined range, and outputs the phase difference signal corresponding to the detected phase difference.