Patent ID: 7579225

Claim:
A method of forming a semiconductor device, the method comprising: forming a first transistor including a first gate pattern and a first source/drain region on both sides of the first gate pattern, over a semiconductor substrate, wherein the first source/drain region is disposed in the semiconductor substrate; forming a first interlayer insulating layer to cover the first transistor; forming a first epitaxial contact plug in contact with the first source/drain region through the first interlayer insulating layer; forming a first semiconductor single crystalline layer on the first interlayer insulating layer, wherein the first semiconductor single crystalline layer is in contact with the first epitaxial contact plug; forming a second transistor including a second gate pattern and a second source/drain region on both sides of the second gate pattern, over the first semiconductor single crystalline layer, wherein the second source/drain region is disposed in the first semiconductor single crystalline layer; forming a second interlayer insulating layer to cover the second transistor; forming a common contact hole to expose the semiconductor substrate by patterning the second interlayer insulating layer, the first semiconductor single crystalline layer, and the first epitaxial contact plug; forming a blocking layer to cover the bottom of the common contact hole but to expose the sidewall of the first semiconductor single crystalline layer; forming a first ohmic layer to cover the sidewall of the first semiconductor single crystalline layer; removing the blocking layer; forming a second ohmic layer on the semiconductor substrate on the bottom of the common contact hole; and forming a common contact plug to fill the common contact hole.