Patent ID: 7719868

Claim:
An integrated semiconductor memory comprising: a substrate with a substrate area and with a memory cell array; a multiplicity of memory cells disposed in the memory cell area; at least one pair of bit lines which comprises a first bit line and a second bit line, where the first bit line and the second bit line respectively have a plurality of memory cells coupled to them; at least one sense amplifier to which the first bit line and the second bit line in the pair of bit lines are coupled; wherein the first bit line and the second bit line in the at least one pair of bit lines respectively each have a first conductor track structure and a second conductor track structure; wherein the memory cells are connected to the second conductor track structure of the respective bit line; wherein the first conductor track structure of the respective bit line is interposed between the sense amplifier and the second conductor track structure of the respective bit line and is arranged at a greater distance from the substrate area than the second conductor track structure of the respective bit line; wherein the first conductor track structures of the first bit line and of the second bit line are routed away from the sense amplifier in the same direction parallel to one another and have, at an end that is remote from the sense amplifier, an electrically conductive connection to the second conductor track structure of the respective bit line; and wherein the second conductor track structure of the first bit line in the pair of bit lines runs from its end which is connected to the first conductor track structure of the first bit line in a direction back to the sense amplifier, whereas the second conductor track structure of the second bit line in the same pair of bit lines, starting from its end which is connected to the first conductor track structure of the second bit line, is routed away from the sense amplifier even further than the first bit line.