Patent ID: 7092302

Claim:
A nonvolatile semiconductor memory device comprising: memory cell transistors each having a floating gate electrode and a control gate electrode (WL); a plurality of decoders (XDEC), each of the decoders including a transfer gate which drives the control gate electrodes (WL), and the transfer gate including a first NMOS; redundant control gate electrodes (WL) replaceable when the control gate electrodes (WL) are defective; memory means (redundant element) which stores addresses for the defective control gate electrodes (WL), said control gate electrode (WL) of the memory cell transistor assuming a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential according to an operating state at the selection thereof; and a plurality of redundancy selectors (RXSEL) for activating and deactivating the decoders (XDEC), wherein the redundancy selectors (RXSEL) input signals (RA, /RA and RDDEN) held in and outputted from the memory means (redundant element), and each of the decoders further includes a second NMOS transistor (NMO) having a drain connected to a gate of the first NMOS transistor of the transfer gate, a gate connected to the first power supply potential (VCC), and a source connected to a control signal (/ER).