Patent ID: 7561468

Claim:
A non-volatile semiconductor memory device, comprising a NAND cell unit including a plurality of electrically rewritable non-volatile memory cells serially connected, the NAND cell unit having one end connected to a bit line via a first selection gate transistor and the other end connected to a source line via a second selection gate transistor, wherein the device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor than the selected memory cell, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both electrically separated from each other in the NAND cell unit, wherein in the data write mode a write non-selection voltage applied to a non-selected memory cell next to the second selection gate transistor is switched in accordance with the position of the selected memory cell in the NAND cell unit, at least in two stages, between a lower voltage V 1 than a write non-selection voltage Vm applied to other non-selected memory cells in the NAND cell unit and a higher voltage V 2 than the lower voltage (V 1 <V 2 ≦Vm).