Patent ID: 7522453

Claim:
A non-volatile memory array segment including: an odd-select transistor having a drain coupled to an odd-source line, a source, and a gate coupled to an odd-select signal line; an even-select transistor having a drain coupled to an even-source line, a source, and a gate coupled to an even-select signal line; a first segment-select transistor having a drain coupled to the source of the odd-select transistor, a source coupled to ground, and a gate coupled to a segment-select line; a second segment-select transistor having a drain coupled to the source of the even-select transistor, a source coupled to ground, and a gate coupled to the segment-select line; a plurality of odd non-volatile memory transistors, each odd non-volatile memory transistor having a drain coupled to a common drain line, a source coupled to the odd-source line, a floating gate, and a control gate; a plurality of even non-volatile memory transistors, each even non-volatile memory transistor having a drain coupled to the common drain line, a source coupled to the even-source line, a floating gate, and a control gate, the control gate of each of the even non-volatile memory transistors coupled to the control gate of a different one of the odd non-volatile memory transistors.