Patent ID: 8569180

Claim:
A method for fabricating an integrated circuit, the method comprising: providing a first semiconductor substrate having a first surface region; forming one or more CMOS integrated circuit (IC) devices provided on a CMOS IC device region overlying the first surface region, the CMOS IC device region having a CMOS surface region; forming a dielectric layer overlying the CMOS surface region; forming a sacrificial layer overlying a portion of the dielectric layer; forming an enclosure layer overlying the sacrificial layer; removing the sacrificial layer via an ashing process to form a void region between the portion of the dielectric layer and the enclosure layer; sealing the void region in a predetermined environment, wherein sealing the void region comprises forming a barrier material overlying at least the void region to hermetically seal the one or more CMOS IC devices; forming a seal ring encircling the CMOS IC devices, the seal ring being electrically coupled with the barrier material to shield the one or more CMOS IC devices.