Patent ID: 7564725

Claim:
An integrated circuit, comprising: a memory array comprising a plurality of SRAM memory cells arranged in a plurality of rows and columns, said array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells; a power supply controller having an input operable for receiving an operation signal indicative of whether said array is in a read or write operation, said power supply controller operable to provide a variable low voltage for said array (VSSM) coupled to a low voltage supply terminal of said array, a level of said VSSM based on said operation signal, wherein said VSSM is at a lower level when in said read operation as compared to a higher level when in said write operation, and wherein a high voltage supply for said array (VDDM) coupled to a high voltage supply terminal for said array is biased above a word line voltage (VWL) level in said read operation.