Patent ID: 7650549

Claim:
An apparatus comprising: a master stage that is adapted to receive a clock signal, a data signal, a enable signal, a scan data signal, and a scan clock signal, wherein the master stage includes: clock input logic including: a NOR gate that receives the enable signal and the clock signal; and an clock inverter that is coupled to the NOR gate; a first multi-state circuit that receives the data signal and that is coupled to the clock input circuit, wherein the clock input circuit controls the first multi-state circuit; scan clock input logic that receives the scan clock signal wherein the scan clock input logic includes a scan clock inverter; a second multi-state circuit that receives the scan data signal and that is coupled to the clock input logic, wherein the scan clock input logic controls the second multi-state circuit; and a control circuit that is coupled to the first and second multi-state circuits, wherein the control circuit includes a plurality of transistors coupled in series with one another, wherein the control electrode of each transistor is coupled to at least one of the input terminal of the scan clock inverter, the output terminal of the scan clock inverter, the input terminal of the clock inverter, the output terminal of the clock inverter, and the input circuit, and wherein the second multi-state circuit is coupled to a node between at least two of the transistors; and a slave stage including: input circuit that is coupled to the control circuit and that receives the clock signal; output logic that is coupled to input circuit and that provides a scan mode output.