Patent ID: 8856446

Claim:
A data processing system comprising: a central processing unit executing program instructions to manipulate data; a data cache connected to said central processing unit temporarily storing in a plurality of cache lines data for manipulation by said central processing unit; a direct memory access unit connected to said central processing unit controlling data transfer, said direct memory access unit operating under control of said central processing unit to control data transfers; a cache controller connected to said data cache capable controlling data transfers into and out of said data cache including a cache read monitor including a plurality of entries, each entry storing an address of a cache read operation in progress, an entry initialized upon a cache read request and extinguished upon supply of data in response to said corresponding cache read request, a direct memory access first-in-first-out stack including a plurality of entries, each entry storing an address of a corresponding direct memory access request to said data cache and an indication whether said direct memory access request is a read request or a write request, an entry initialized upon receipt of a direct memory access request and extinguished upon completion of said direct memory access request, and a comparator connected to said cache read monitor and said direct memory access first-in-first-out stack for comparing an address of said direct memory access request in a final entry of said direct memory access first-in-first-out stack to said address of each entry of said cache read monitor if said direct memory access request is a write request, said comparator generating a stall signal to stall said direct memory access first-in-first-out stack preventing completion of any direct memory access request upon detection of a match.