Patent ID: 7924650

Claim:
A memory device, comprising multiple banks, wherein a given bank includes: a block of static random access memory (SRAM) having a standby mode and an active operating mode; a first power-signal line and a second power-signal line that are each coupled to the block of SRAM and are each coupled to one or more additional banks in the multiple banks, wherein the first power-signal line is configured to couple to a power-supply circuit, which is configured to provide a first voltage to the multiple banks; a regulator circuit configured to regulate a second voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line; a selection circuit configured to couple the first voltage to the block of SRAM during the active operating mode and the second voltage to the block of SRAM during the standby mode; and a recycling circuit configured to selectively open a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to the one or more additional blocks of SRAM in the one or more additional banks.