Patent ID: 7142008

Claim:
In an integrated circuit having a plurality of Input/Output (I/O) pins, a programmable logic device coupled to the I/O pins to provide dedicated and configurable logic functions, the programmable logic device comprising: a plurality of logic blocks coupled to receive first input signals from the I/O pins and coupled to provide first output signals having a logical relationship to the first input signals in accordance with a user defined configuration; a programmable interconnect array coupled to receive the first output signals and coupled to distribute the first output signals in accordance with the user defined configuration; and a dedicated logic block coupled to receive second input signals from the I/O pins and coupled to provide second output signals in accordance with the dedicated function, wherein the second input and output signals bypass the programmable interconnect array; and wherein the dedicated logic block includes a dedicated clock divider coupled to receive a clock signal at a first frequency and coupled to provide a clock signal at a second frequency; and wherein the dedicated clock divider is coupled to provide the clock signal at the second frequency in response to a clock enable signal.