Patent ID: 7629253

Claim:
A method of forming a memory cell, comprising: forming a first trench in a first dielectric over and interfacing with a semiconductor substrate, the first trench not formed all the way through to the semiconductor substrate; filling the first trench with a first conductor; recessing the first conductor in the first dielectric, such that the first conductor is not substantially flush with the first dielectric; filling the recess with a fourth diffusion barrier, such that the fourth diffusion barrier is substantially flush with the first dielectric; forming a semiconductor pillar over the fourth diffusion barrier such that the pillar interfaces with the fourth diffusion barrier but not the first conductor; forming a second trench in a second dielectric over the pillar; forming a sixth diffusion barrier over and interfacing with the pillar in the second trench; forming a second conductor over and interfacing with the sixth diffusion barrier in the second trench, the second conductor not interfacing with the pillar; recessing the second conductor in the second dielectric, such that the second conductor is not substantially flush with the second dielectric; and filling the recess with a ninth diffusion barrier, such that the ninth diffusion barrier is substantially flush with the second dielectric, the semiconductor pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell.