Patent ID: 8386978

Claim:
A system to estimate timing delays in an integrated circuit design for optimization during synthesis, the system comprising: one or more processors to execute instructions; and a storage device coupled to the one or more processors, the storage device to store instructions including instructions to generate a physical wire-load model to model parasitic capacitance per unit length of a net and parasitic resistance per unit length of a net, the physical wire-load model responsive to a physical library; instructions to convert circuit information for each net into a plurality of equivalent net lengths; instructions to estimate a net length for each of the plurality of nets in the netlist of the integrated circuit design between each driver and one or more receivers; instructions to sum respectively the plurality of equivalent net lengths and the estimated net length for each net together to generate a total net length estimate for each net; and instructions to calculate a timing delay for each of the plurality of nets in the netlist in response to the physical wire load model modeling parasitic capacitance per unit length and parasitic resistance per unit length, in response to the converting of circuit information into the plurality of equivalent net lengths, and in response to the total net length estimate.