Patent ID: 7952187

Claim:
A wafer level package comprising: an integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof; a plurality of polymer laminates positioned on the IC substrate, each of the plurality of polymer laminates having a plurality of vias formed therein, each of the plurality of vias corresponding to a respective die pad; a plurality of interconnects formed on each of the plurality of polymer laminates, each of the plurality of interconnects covering a portion of a top surface of a respective polymer laminate and extending down through the via and into contact with an interconnect on a neighboring polymer laminate positioned below; and an input/output (I/O) system interconnect positioned on a top surface of the wafer level package and attached to the plurality of interconnects; wherein each of the plurality of polymer laminates comprises a separate pre-formed laminate sheet; and wherein each of the plurality of polymer laminates includes a dice area, with the dice area having at least a portion of polymer material removed therefrom to form a trench that reduces residual stress in the IC substrate.