Patent ID: 7313586

Claim:
An adder-subtracter circuit for processing a first binary number of a predetermined plurality of bits and a second binary number of the predetermined plurality of bits, the circuit being adapted to add the two binary numbers together or to subtract the two binary numbers from each other dependent on the state of a subtract signal, being adapted to bypass the result of the processing of the two binary numbers for processing by the circuit dependent on the state of a bypass signal and comprising: a subtract logic circuit receiving the second binary number and the subtract signal for XORing each bit of the second binary number and the subtract signal to generate an intermediate second binary number; a select logic circuit receiving the intermediate second binary number and a feedback binary number to output the second binary number or the feedback binary number dependent on the state of the bypass signal; a main logic circuit receiving the output of the select logic circuit and the first binary number for processing each pair of respective bits from the first binary number and the output of the select logic circuit to generate a set of intermediate carry terms and a set of summation carry terms relative to bit positions of a sum of the first binary number and the output of the select logic circuit; output logic gates for combining the set of the intermediate carry terms with the set of the summation carry terms from the main logic circuit to generate an output related to the result of the processing of the circuit; and a feedback logic circuit receiving the set of the intermediate carry terms, the set of the summation carry terms and the subtract signal for processing the received sets to generate a set of intermediate feedback terms by XORing each intermediate carry term with the inverse of the subtract signal and to generate the feedback binary number by bitwise XORing each intermediate feedback term with the respective summation carry term.