Patent ID: 8541826

Claim:
A memory array structure, comprising: a substrate; a plurality of memory cells formed on the substrate, wherein the plurality of memory cells are parallel arranged in a first direction and a second direction respectively, each memory cell including a vertical transistor which comprises: a semiconductor pillar, a gate structure which includes a gate dielectric and a gate electrode and is formed on a side wall of the semiconductor pillar, a source region and a drain region, and a vertical channel region formed between the source region and the drain region, wherein the gate structure is formed in a first trench extending in the first direction and adjacent to the semiconductor pillar, one of the source region and the drain region is formed in an upper end of the semiconductor pillar and near the gate electrode, and the other is formed in a whole lower end of the semiconductor pillar; a plurality of word lines in the first direction, each word line formed in the first trench for connecting the gate electrodes; a plurality of bit lines in the second direction, each bit line formed in lower sides of the semiconductor pillars for connecting the source regions or the drain regions; a plurality of body lines in the first direction, a first portion of each body line formed on the gate electrodes and one word line, a second portion of each body line covering a part of a top surface of the semiconductor pillar for providing a substrate contact to the vertical channel regions; and a plurality of data storage device contacts, each data storage device contact formed on each semiconductor pillar for connecting a data storage device with each vertical transistor via each data storage device contact.