Patent ID: 8885394

Claim:
A semiconductor device comprising: a plurality of memory banks, wherein each memory bank in the plurality of memory banks includes a plurality of sections arranged between a global bit line and a complementary global bit line, and each section in the plurality of sections includes a first memory cell group and a second memory cell group connected between a local bit line and a complementary local bit line and a section control unit disposed between the first memory cell group and the second memory cell group, wherein the section control unit is connected between the global bit line and the complementary global bit line to provide a first read signal to the global bit line and a second read signal to the complementary global bit line in response to a read operation directed to a memory cell in one of the first memory cell group and the second memory cell group; a signal converter that receives the first read signal via the global bit line and the second read signal via the complementary global bit line in response to the read operation and generates a stable controlled read signal indicative of a data value stored in the memory cell; and a latch unit that receives and latches the controlled read signal provided by the signal converter to generate a latched read signal.