Patent ID: 8133767

Claim:
A method of forming a semiconductor structure including a high EM resistant interconnect structure and a lower EM resistant fuse structure located within a same interconnect level, said method comprising: providing an upper interconnect level atop a lower interconnect level, said upper interconnect level including a dielectric material having an interconnect area and a fuse area; forming at least one conductive feature within said dielectric material in said interconnect area and at least one other conductive feature within said dielectric material in said fuse area; selectively forming a surface oxide layer on an upper exposed surface of each of said at least one other conductive feature embedded within said dielectric material in said fuse area; and forming a dielectric capping layer on said surface oxide layer and extending atop said dielectric material in said fuse area, said dielectric capping layer is also located atop said dielectric material and said at least one conductive feature of said interconnect area.