Patent ID: 7917873

Claim:
A method for verifying integrated circuit design, comprising: defining a set of intent units, each intent unit comprising a code component, wherein the set of intent units comprises at least one base intent unit and at least one derived intent unit, the derived intent unit derived from the base intent unit and inheriting one or more interfaces or processes from the base intent unit, the derived intent unit referencing the base intent unit; coupling multiple intent units together to form a composite intent unit; providing a graphical user interface that allows users to associate intent units to specific design elements of an integrated circuit, wherein the specific design elements comprise constituent elements of the integrated circuit design; linking the one or more intent units including the composite intent unit to a design element of the integrated circuit based on input in the graphical user interface wherein the design element of the integrated circuit corresponds to the design element corresponding to the intent unit; generating, by a computer, a verification plan corresponding to the integrated circuit based upon each of the one or more intent units, wherein the verification plan describes a verification procedure for the integrated circuit and contains information from each intent unit linked to the design element in an integrated verification plan; generating, by a computer, a testbench corresponding to the design of the integrated circuit based upon each of the one or more intent units, wherein generating a test bench comprises compiling the code components of the one or more intent units including code components of the intent units coupled together to form the composite intent unit; and generating, by a computer, a test model from the testbench and a design component corresponding to the integrated circuit.