Patent ID: 6911740

Claim:
A semiconductor device comprising: a semiconductor substrate including active regions defined by a field region; gates disposed on the active regions; source and drain regions in the active regions adjacent to the gates; an interlayer dielectric layer in gaps between the gates; spacers between sidewalls of the gates and the interlayer dielectric layer, the spacers comprising at least two layers of different materials; gate oxide layers between the gates and the active regions; capping insulating layers on the gates; and conductive contact pads penetrating the interlayer dielectric layer and electrically connected to the active regions, wherein the spacers comprise: first spacer layers between the interlayer dielectric layer and the sidewalls of the gates, and including a silicon oxide layer; and second spacer layers between the conductive contact pads and the sidewalls of the gates and including a silicon oxide layer and a silicon nitride layer.