Patent ID: 7432156

Claim:
A method for fabricating a memory device in and on a silicon substrate, the method comprising the steps of: forming a gate oxide layer on a surface of the silicon substrate; depositing and patterning a layer of polycrystalline silicon to form a polycrystalline silicon gate electrode overlying the gate oxide layer, the polycrystalline silicon gate electrode having first and second opposing edges; etching the gate oxide layer to form first and second undercut regions of the gate oxide layer at the first and second opposing edges, respectively, of the polycrystalline silicon gate electrode; in each of the first and second undercut regions: thermally oxidizing the silicon substrate and the polycrystalline silicon gate electrode to form a first silicon oxide layer at the surface of the silicon substrate and a second silicon oxide layer on the polycrystalline silicon gate electrode; depositing a layer of nitride on the first silicon oxide layer and on the second silicon oxide layer, leaving a void between the layer of nitride on the first silicon oxide layer and the layer of nitride on the second silicon oxide layer; and depositing a layer comprising polycrystalline silicon to fill the void; implanting conductivity determining ions into the silicon substrate to form first and second bit lines in alignment with the first and second opposing edges, respectively; and depositing and patterning a layer of conductive material to form a word line electrically coupled to the polycrystalline silicon gate electrode.