Patent ID: 8504961

Claim:
An integrated circuit comprising: a processing circuitry including a plurality of critical path circuits, each of said plurality of critical path circuits performing a part of functional data processing operations of said integrated circuit and having a path delay corresponding to a time for a processing signal to propagate therethrough; and a path control circuitry coupled to said plurality of critical path circuits and configured to detect a path delay through each critical path circuit of said plurality of critical path circuits; wherein said each critical path circuit includes a variable delay circuitry configured to increase a path delay through said critical path circuit by an additional delay amount controlled by said path control circuitry; said path control circuitry is configured to control said variable delay circuitry to increase said path delay to match a target path delay; and said variable delay circuitry includes a tank capacitor, said path control circuitry is configured to control charge stored in said tank capacitor to provide a control voltage level at one terminal of said tank capacitor, and a portion of said variable delay circuitry is provided with a power supply voltage dependent upon said control voltage level.