Patent ID: 7031377

Claim:
A digital filter, comprising: at least two multiple stage shift registers; a plurality of multipliers corresponding in number to the total number of stages in the at least two multiple stage shift registers, each multiplier receiving as a first input an output from a stage of the at least two multiple stage shift registers; a tap weight shifter coupled to a tap weight source to receive tap weights, the tap weight shifter coupled to provide a second input to each multiplier, the tap weight shifter capable of shifting tap weights, each multiplier producing an output corresponding to a product of the first and second inputs; and an adder for summing the multiplier outputs to provide a sum output, wherein: two or more sum outputs are generated by the adder between consecutive shiftings of new data into the at least two multiple stage shift registers; and no new data is shifted into any of the at least two multiple stage shift registers between generation of a first of the two or more sum outputs by the adder and a last of the two or more sum outputs by the adder.