Patent ID: 8581327

Claim:
A memory comprising: at least two memory cells, each memory cell comprising: an isolation bottom layer formed on a substrate and positioned between a first isolation wall and a second isolation wall; a conductive layer disposed on the isolation bottom layer and positioned between the first isolation wall and the second isolation wall; a first charge storage structure formed on the substrate and disposed adjacent to the first isolation wall and separated with the conductive layer by the first isolation wall; and a second charge storage structure formed on the substrate and disposed adjacent to the second isolation wall and separated with the conductive layer by the second isolation wall; a first gate and a second gate respectively disposed on the first and the second charge storage structures; a patterned isolation material layer disposed outside the first and the second charge storage structures and filling up spaces between adjacent memory cells, wherein the patterned isolation material layer directly contacts the first gate and the first charge storage structure of the memory cell and also directly contacts another second gate and another second charge storage structure of another adjacent memory cell; and a word line formed above and covering top surfaces of the first gate, the first isolation wall, the conductive layer, the second isolation wall and the second gate; wherein the word line is formed above a top surface of the patterned isolation material layer and covers a portion of the top surface of the patterned isolation material layer, thereby exposing another portion of the patterned isolation material layer.