Patent ID: 7174418

Claim:
A semiconductor device for refreshing data stored in a memory device, comprising: a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells wherein the N number of unit cell blocks are corresponded to logical cell block addresses and one unit cell block is added for accessing data with high speed; a predetermined cell block table for assigning M number of word lines among the (N+1)Ã—M number of the word lines as predetermined restorable word lines; a tag block having N+1 number of unit tag blocks, each unit tag block storing at least one physical cell block address storing data wherein the tag block receives a logical cell block address designated for accessing one of N number of unit cell blocks and converts the logical cell block address into a physical cell block address designated for accessing one of the N+1 number of unit cell blocks; and a control means for activating one word line of a unit cell block selected by the physical cell block address and a corresponding one of the predetermined restorable word lines by controlling the tag block and the predetermined cell block table, wherein the tag block stores information representing an update of the logical cell block address and a refresh operation is preformed through the use of the information.