Patent ID: 8060793

Claim:
A processor operation inspection system which is composed of a processor and an operation inspection circuit that inspects an operation of said processor, wherein said processor comprises: a state switching signal output unit that outputs a state switching signal indicating a state transition to said operation inspection circuit at the time of a transition from one predefined state to another state; and a status output unit that outputs a state signal indicating a current state to said operation inspection circuit; and said operation inspection circuit comprises: a state switching signal input unit that receives an input of said state switching signal; a state signal input unit that receives an input of said state signal; a state storage unit that stores the state of said processor; a state calculation unit that calculates a new state to be taken by said processor from the state of said processor stored in said state storage unit and said state switching signal; and an inspection unit that inspects the operation of said processor by making a comparison between the new state to be taken by said processor which has been calculated by said state calculation unit and the state of said processor inputted through said state signal input unit; and said processor is able to execute a plurality of tasks; said operation inspection circuit is composed of a reconfigurable processor; and said operation inspection circuit further comprises a circuit information storage unit that stores circuit information of said operation inspection circuits corresponding to said plurality of tasks, respectively; and a control unit that loads the circuit information corresponding to said task into said reconfigurable processor according to a task which is being executed by said processor.