Patent ID: 7898283

Claim:
A secured integrated circuit, the integrated circuit comprising: a physical unclonable function (PUF) including an input circuit, a configurable delay circuit, and an output circuit serially coupled together; wherein the configurable delay circuit comprises a plurality of configurable delay chains of serially coupled configurable switching-delay elements, where each configurable delay chain comprises two parallel paths adapted to receive two signals, configurably switch and propagate the two received signals along the two parallel paths, and output two delayed signals for the output circuit; wherein the input circuit comprises an input network coupled to the one or more configurable delay chains, where the input network is configured to responsively output configuration signals to configure the switching-delay elements of the configurable delay chains, in response to challenges provided to the input network; and wherein the output circuit comprises a plurality of arbiters coupled to respective ones of last switching-delay elements of respective ones of the plurality of configurable delay chains, where each arbiter is configured to output a signal based at least in part on relative arrival of the two delayed signals output by the respective ones of the last switching-delay elements.