Patent ID: 8694839

Claim:
A method for operating a chip, wherein the chip is connected with a high speed bus and a low speed bus, the method comprising: enabling either a transmission mechanism or a receiving mechanism of the chip while normally operating the chip, wherein an output of the transmission mechanism is electrically connected to an input of a data connecting circuit, a multiplexer has a first input electrically connected to the output of the transmission mechanism, a second input electrically connected to an output of the data connecting circuit, and an output coupled to the receiving mechanism, wherein the output of the data connecting circuit is coupled to the high speed bus; enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip; transmitting, with the transmission mechanism, a testing signal; receiving, with receiving mechanism, the testing signal transmitted by the transmission mechanism and a strobe signal while testing the chip; reading, with the receiving mechanism, the testing signal according to the strobe signal; and controlling the multiplexer, while testing the chip, to selectively output the testing signal from the transmission mechanism or the testing signal from the data connecting circuit to the receiving mechanism, wherein testing the chip comprises selectively testing the data connecting circuit by controlling the multiplexer.