Patent ID: 6856215

Claim:
A group delay adjusting circuit comprising: a first stub matching structure coupled to a microstrip input transmission line; a first DC blocking capacitor having a first terminal coupled to the microstrip input transmission line, and a second terminal; a main transmission line having a first terminal coupled to the second terminal of the first DC blocking capacitor, a second terminal, a third terminal along its length, a fourth terminal along its length, and a fifth terminl along its length; a first varactor diode having a first terminal coupled to the fifth terminal of the main transmission line, and a second terminal coupled to a ground; a first high impedence line having a first terminal coupled to the third terminal of the main transmission line, and a second terminal; a first RF by pass capacitor having a first terminal coupled to the second terminal of the first high impedance line and a first signal input pad, and a second terminal coupled to ground; a second DC blocking capacitor having a first terminal coupled to the second terminal of the main transmission line, and a second terminal; a second stub matching structure coupled to a microstrip output transmission line, and to the second terminal of the second DC blocking capacitor; a third DC blocking capacitor having a first terminal coupled to the fourth terminal of the main transmission line, and a second terminal; a transmission line of a quarter wavelength at a frequency of operation having a first terminal at a first end coupled to the second terminal to the third DC blocking capacitor, a second terminal at a second end, and a third terminal along its length; a second varactor diode having a first terminal coupled to the second terminal of the transmission line of a quarter wavelength at a frequency of operation, and a second terminal coupled to the ground; a second high impedance transmission line having a first terminal coupled to the third terminal of the transmission line of a quarter wavelength at a frequency of operation, and a second terminal; and a second RF bypass capacitor having a first terminal coupled to the second terminal of the high impedance transmission line and to a second signal input pad, and a second terminal coupled to the ground.