Patent ID: 8518741

Claim:
A method for fabricating a multi-chip stacked structure comprising: joining a first wafer and a second wafer with a first interconnect structure interposed therebetween to form a wafer stack; filling a gap between the first wafer and the second wafer; thinning the second wafer to expose a first through silicon via; performing a back side metallization process on a surface of the second wafer having the exposed first through silicon via; joining the surface of the second wafer having the exposed first through silicon via of the wafer stack to a third wafer with a second interconnect structure interposed therebetween, the third wafer having a second through silicon via; filling a gap between the second wafer and the third wafer; thinning the third wafer to expose the second through silicon via; performing a back side metallization process on a surface of the third wafer having the exposed second through silicon via; dicing the wafer stack including the third wafer; and joining the wafer stack to a substrate with a third interconnect structure interposed therebetween.