Patent ID: 8108562

Claim:
A storage system, comprising: a first controller including a first CPU core, a second CPU core and a first memory; a first logical unit coupled to the first controller and associated with the first CPU core; a second logical unit coupled to the first controller and associated with the second CPU core; a second controller including a third CPU core, a fourth CPU core and a second memory, and coupled to the first controller; a third logical unit coupled to the second controller and associated with the third CPU core; a fourth logical unit coupled to the second controller and associated with the fourth CPU core; and a host computer coupled to the first controller, wherein the first memory includes a first queue area associated with the first logical unit and a second queue area associated with the second logical unit, wherein the second memory includes a third queue area associated with the third logical unit and a fourth queue area associated with the fourth logical unit, wherein when the first controller receives a first write command targeted to the first logical unit from the host computer, the first CPU core is configured to store the first write command in the first queue area and to process the first write command to the first logical unit, wherein when the first controller receives a second write command targeted to the second logical unit from the host computer, the first CPU core is configured to store the second write command in the second queue area, and the second CPU core is configured to read the second write command from the second queue area and to process the second write command to the second logical unit, wherein when the first controller receives a third write command targeted to the third logical unit from the host computer, the first CPU core and the second CPU core are configured so that one of the first CPU core or the second CPU core stores the third write command in the third queue area, and the third CPU core is configured to read the third write command from the third queue area and to process the third write command to the third logical unit, and wherein when the first controller receives a fourth write command targeted to the fourth logical unit from the host computer, the first CPU core and the second CPU core are configured so that one of the first CPU core or the second CPU core stores the fourth write command in the fourth queue area, and the fourth CPU core is configured to read the fourth write command from the fourth queue area and process the fourth write command to the fourth logical unit.