Patent ID: 7755966

Claim:
A memory device comprising: a memory cell array having a plurality of memory blocks; a memory controller for controlling a refresh operation with respect to the memory blocks; a refresh check bit circuit for storing refresh check bits corresponding to the memory blocks, respectively; a block select control circuit for setting refresh check bits of memory blocks to be refreshed to a checked state according to a first control signal of the memory controller; a using check bit circuit for storing using check bits corresponding to the memory blocks, respectively, wherein the using check bits indicate blocks to which access is requested in the memory cell array; a using check control circuit for setting using check bits of memory blocks to which access is requested to a checked state according to a second control signal of the memory controller; and a partial refresh control circuit for controlling the refresh operation such that memory blocks corresponding to checked using check bits or checked refresh check bits are refreshed according to a third control signal of the memory controller.