Patent ID: 7225323

Claim:
A multipurpose functional unit for a processor, comprising: an input section configured to receive first, second, and third operands and an opcode designating one of a plurality of supported operations to be performed and further configured to generate a plurality of control signals in response to the opcode; a multiplication pipeline coupled to the input section and configurable in response to the control signals to compute a product of the first and second operands and to select the computed product as a first intermediate result; a test pipeline coupled to the input section and configurable in response to the control signals to perform a comparison on one or more of the first, second, and third operands and to select a result of the comparison as a second intermediate result; an addition pipeline coupled to the multiplication section and the test pipeline and configurable in response to the control signals to compute a sum of the first and second intermediate results and to select the computed sum as an operation result; an exponent pipeline coupled to the input section and configurable in response to the control signals to perform an exponent computation on one or more of the first, second, and third operands and to select a result of the exponent computation as an exponent result; and an output section coupled to receive the operation result and the exponent result and configurable in response to the control signals to generate a final result for the one of the supported operations designated by the opcode, wherein the plurality of supported operations includes a floating-point multiply-add (FMAD) operation, an integer multiply-add (IMAD) operation, and at least one comparison test operation.