Patent ID: 8569753

Claim:
A semiconductor device comprising: a first memory cell comprising a first transistor and a second transistor, the first transistor and the second transistor overlapping with each other at least partly; and a second memory cell comprising a third transistor and a fourth transistor, the third transistor and the fourth transistor overlapping with each other at least partly, wherein each of the first transistor and the third transistor comprises: a first source region; a first drain region; a first channel formation region between the first source region and the first drain region, the first channel formation region comprising a first semiconductor material; and a first gate electrode over the first channel formation region with a first gate insulating layer interposed between the first gate electrode and the first channel formation region, wherein each of the second transistor and the fourth transistor comprises: a second channel formation region comprising a second semiconductor material different from the first semiconductor material; a source electrode electrically connected to the second channel formation region; a drain electrode electrically connected to the second channel formation region; and a second gate electrode over the second channel formation region with a second gate insulating layer interposed between the second gate electrode and the second channel formation region, wherein one of the first source region and the first drain region is electrically connected to one of the source electrode and the drain electrode via a first conductive layer, wherein the first conductive layer and the first gate electrode are patterned portions of a same layer, and wherein the one of source electrode and the drain electrode of the second transistor is electrically connected to the one of source electrode and the drain electrode of the fourth transistor via a wiring.