Patent ID: 8780634

Claim:
A memory circuit comprising: an array of non-volatile memory cells arranged along a plurality of word lines and a plurality of M bit lines into a NAND type of architecture, the array formed of multiple blocks, each of the blocks including a plurality of M NAND strings connected along a corresponding one of the M bit lines and each having a plurality of N memory cells connected in series with a plurality of N word lines spanning the M NAND strings, each of the N word lines connected to a corresponding one of the N memory cells thereof; word line driving circuitry connectable to the word lines, whereby one or more word lines in a plurality of blocks can be concurrently and individually be set to one of a plurality of data dependent read values corresponding to a respective data pattern for each of the plurality of blocks; and sensing circuitry connectable to the M bit lines individually determine those of the M bit lines where at least one of the NAND strings connected therealong are conducting in response the word line driving circuitry applying said respective data patterns to the corresponding plurality of blocks.