Patent ID: 8364910

Claim:
A method of regulating an execution of a program by a microprocessor, said microprocessor having a memory comprising a plurality of locations addressed by a plurality of instruction addresses, each instruction address having an instruction, and said microprocessor having a plurality of data addresses, each data address having a datum and each data address being associated with an owner subset of instruction addresses, said method comprising: when an accessing instruction at an accessing instruction address attempts to access a datum at a data address, allowing the access or issuing a fault based on an evaluation of at least one access condition comprising: (a) allowing the access if said accessing instruction address is an element of the owner subset of instruction addresses associated with the data address being accessed by said accessing instruction, when a set-owner operation taking a plurality of set-owner arguments, said set-owner arguments comprising a data address and a new owner subset of instruction addresses, attempts to alter an owner subset of instruction addresses associated with at least one data address to a new owner subset of instruction addresses, allowing said set-owner operation by altering the owner subset of instruction addresses associated with the at least one data address to be the new owner subset of instruction addresses, or issuing a fault, based on an evaluation of at least one set-owner condition comprising: (a) at least one instruction address of at least one instruction of said set-owner operation being an element of the owner subset of instruction addresses associated with said data address of said set-owner arguments.