Patent ID: 8629499

Claim:
A vertical MOSFET comprising: a semiconductor body comprising at least a portion of a silicon wafer and having a substantially planar first surface defining a source and a substantially planar second surface defining a drain, said first surface and said second surface being substantially parallel and not co-planar, wherein said source is electrically coupled to a source electrode associated with said first surface and said drain is electrically coupled to a drain electrode associated with said second surface; a gate comprising a conductive material and an insulating layer which electrically isolates said conductive material from said body formed proximate said second surface; and an electrically conductive path at least partially through said semiconductor body from said first surface to said gate, wherein said electrically conductive path comprises a via structure including a conductive material and an insulating layer which at least partially electrically isolates the conductive material from said semiconductor body, wherein both the conductive material and the insulating layer comprise silicon; wherein said via is disposed between said source and said gate and said gate is disposed between said via and said drain of at least one of a plurality of MOSFET cells; and wherein said vertical MOSFET comprises a plurality of MOSFET cells having their sources, drains, and gates electrically connected to said source, drain, and gate, respectively, of said vertical MOSFET.