Patent ID: 8181342

Claim:
A method for manufacturing a coreless packaging substrate, comprising the following steps: providing a carrier, which comprises a core layer, a first dielectric layer disposed on the core layer, a release film disposed on the first dielectric layer, and a metal layer disposed on the release film and the first dielectric layer, wherein an area of the release film is smaller than that of the first dielectric layer such that the first dielectric layer has a frame-shaped region not covered by the release film and the metal layer is connected with the frame-shaped region by overlapping; forming a first wiring layer on the metal layer of the carrier, wherein the first wiring layer has a plurality of first conductive pads; forming a built-up structure on the first wiring layer and the metal layer, wherein the built-up structure comprises at least one second dielectric layer, at least one second wiring layer disposed on the second dielectric layer, and a plurality of conductive vias disposed in the second dielectric layer, wherein the conductive vias electrically connect the first wiring layer and the second wiring layer, and the outermost second wiring layer has a plurality of second conductive pads; and cutting the built-up structure, the metal layer, the releasing film, and the first dielectric layer along a border of the releasing film, and removing the carrier from the built-up structure such that the first conductive pads are embedded in and exposed from the second dielectric layer.