Patent ID: 7808112

Claim:
An electronic system, comprising: a processor; and a pre-packaged integrated circuit device coupled to the processor, wherein the pre-packaged integrated circuit device further comprises: a first semiconductor die that includes an active side and an opposing back side, wherein the active side includes a first plurality of connection pads that are coupled to circuits formed on the first semiconductor die; a second semiconductor die having an active side that includes a second plurality of connection pads that are coupled to circuits formed on the second semiconductor die, wherein the back side of the first semiconductor die is bonded to the active side of the second semiconductor die such that the first plurality of connection pads is spaced apart from the second plurality of connection pads; an adhesive layer disposed on the first semiconductor die and the second semiconductor die that includes a plurality of openings in positional correspondence with the first plurality of connection pads and the second plurality of connection pads and extending through the adhesive layer to provide access to the first plurality of connection pads and the second plurality of connection pads; and a conductive material positioned in at least a portion of the plurality of openings to provide electrical communication between the processor and the pre-packaged integrated circuit device; wherein the adhesive layer has a chamfer in the vicinity of each opening of the plurality of openings.