Patent ID: 7477570

Claim:
A sequential access memory device, comprising: a sequential access memory array configured to sequentially store a group of bytes on each of a plurality of rows; a plurality of bit-lines for sequentially transferring each of the group of bytes into and out of the sequential access memory array; and a pre-charging unit configured to pre-charge the plurality of bit-lines once per sequential transfer of one of the group of bytes into or out of one of the plurality of rows of the sequential access memory array, wherein the group of bytes is less than an entire row, and wherein the pre-charging unit further comprises at least one of a read-pre-charge unit configured to generate a read-pre-charge signal once for every transfer of one of the group of bytes out of one of the plurality of rows of the sequential access memory array or a write-pre-charge unit configured to generate a write-pre-charge signal once for every transfer of one of the group of bytes into one of the plurality of rows of the sequential access memory array.