Patent ID: 8725922

Claim:
A data processor comprising: a central processing unit configured to execute instructions; a plurality of circuit modules operatively coupled to the central processing unit and each configured to output one of a plurality of event signals; a first controller configured to output an interrupt request to the central processing unit based on a selected one of the event signals; and a second controller configured to output a start control signal to a first circuit module of said plurality of circuit modules based on the event signal generated from a second circuit module of the plurality of circuit modules, said second controller including a multiplexer; an operation select circuit; a connection set register; and an operation set register, wherein the multiplexer includes inputs to receive the event signals, and an output to output one of the event signals selected from among the received event signals based on a value of the connection set register, wherein the operation select circuit outputs to the start control signal as one of a first and a second start control output signal to the first circuit module which causes the first circuit module to perform a given operation when the operation select circuit receives the selected event signal, wherein the first circuit module is configured to perform a plurality of functions, and wherein the second control signal is used for selecting one of the plurality of functions, and the first start control signal is used for a start signal of the selected function.