Patent ID: 8108593

Claim:
A memory system comprising: a first storing area as a cache memory included in a volatile semiconductor memory; second and third storing areas included in a nonvolatile semiconductor memory in which data reading and writing is performed by a page unit and data erasing is performed by a physical block unit that is twice or larger natural number times as large as the page unit; a first input buffer included in the nonvolatile semiconductor memory that functions as an input buffer for the third storing area; a second input buffer included in the nonvolatile semiconductor memory that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area; and a controller that allocates a storage area of the nonvolatile semiconductor memory to the second and third storing areas in logical block unit associated with one or more of physical blocks, wherein the controller executes: first processing for flushing a plurality of data in sector unit written in the first storing area to the second storing area as data in first management unit; second processing for flushing the plurality of data written in the first storing area to the second input buffer in second management unit as data in second management unit that is twice or a larger natural number times as large as the first management unit; third processing for flushing the plurality of data written in the first storing area to the first input buffer in logical block unit as data in the second management unit; fourth processing for flushing a plurality of data written in the second storing area to the first input buffer in logical block unit; fifth processing for relocating a plurality of data written in the first input buffer to the third storing area in logical block unit; and sixth processing for relocating a plurality of data written in the second input buffer to the third storing area.