Patent ID: 8380936

Claim:
A multi-core processor system comprising: a multi-core processor that includes a plurality of processor cores each including a cache; and a shared memory that includes a first memory area in which an access using the cache is possible and an access without using the cache is impossible, that is shared by the plurality of processor cores, and that is connected to the multi-core processor via a bus, wherein the multi-core processor includes a state manager that classifies an area allocated to the multi-core processor in the first memory area into one of a first state in which allocation to the processor cores is not performed, a second state in which allocation to one of the processor cores is performed and read and write are performed, and a third state in which allocation to one or more of the processor cores is performed and read and write are prohibited, and further performs a transition from one of the first state, the second state, and the third state to another; and a cache/memory manager that writes back a corresponding cache line on the core where the transition is performed.