Patent ID: 7456636

Claim:
A test structure for voltage contrast (VC) inspection of a transistor, the test structure comprising: a gate stack that is grounded by a ground to maintain a channel under the gate stack in an off state of the transistor during VC inspection, wherein the ground is distinct from an inspection ground used to ground a source and a drain of the transistor; wherein only one of a source region for the gate stack or a drain region for the gate stack is consistently grounded by the inspection ground, providing a grounded region; and wherein the transistor is within a silicon-on-insulator (SOI) substrate over a grounded bulk silicon substrate, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer, the ground includes: a polysilicon ground extending through the SOI layer and the BOX layer to the grounded bulk silicon substrate; a gate oxide layer of the gate stack on an upper surface of the polysilicon ground, the gate oxide layer being insufficiently insulative to prevent electrical conductivity therethrough; and wherein the gate stack contacts the gate oxide layer.