Patent ID: 7274764

Claim:
A phase-locked loop (PLL) comprising: a charge-pump loop filter configured to provide a control voltage having a voltage lever based on a state of a first charge-pump (CP) control signal and on a state of a second CP control signal; a phase detector system configured to receive a first clock having a state, a second clock having a state, and an input signal defining a plurality of states including a first state and a second state, and configured to provide the first CP control signal and the second CP control signal each having a state based on the states of and on a phase difference between the first and second clocks when the input signal has the first state, and to provide the first CP control signal and second CP control signal each having a state asynchronously controlled by the input signal when the input signal has the second state; wherein the phase detector system further comprises: a clock control circuit configured to provide a first output signal having a state substantially equal to the state of the first clock and a second output signal having a state substantially equal to the state of the second clock when the input signal has the first state, to provide the first and second output signals having a state asynchronously controlled by the input signal when the input signal has the second state, and to provide a third output signal having a state based on the first and second CP control signals when the input signal has the first state and a state asynchronously controlled by the input signal when the input signal has the second state; and a sequential phase-frequency detector (PFD) configured to provide the first CP control signal having a state based on the states of the first and/or third output signals and the second CP control signal having a state based on the states of the second and/or third output signals.