Patent ID: 8782301

Claim:
A semiconductor device comprising: a direct memory access controller configured to execute data transfer for a certain number of transfer times, when receiving, via a request signal, a request for data transfer by direct memory access; a control circuit configured to receive a first request signal and to supply the direct memory access controller with a second request signal as the request signal, the second request signal being based on the first request signal; an information obtaining circuit configured to obtain a transfer address and a remaining number of transfer times when the first request signal is inactivated while the data transfer for the certain number of transfer times is in progress; and a re-setting circuit configured to set, in the direct memory access controller, the transfer address and the remaining number of transfer times which are obtained by the information obtaining circuit, after the direct memory access controller executes the data transfer for the certain number of transfer times, wherein, when the first request signal is inactivated while the data transfer for the certain number of transfer times is in progress, the control circuit keeps the second request signal inactive during a period after the first request signal is inactivated and before the direct memory access controller finishes the data transfer for the certain number of transfer times.