Patent ID: 8283958

Claim:
A delay locked loop comprising: a delay line configured to generate an output clock signal based on operations of a plurality of delay cells, the plurality of delay cells configured to delay a phase of a first clock signal; a phase detection block configured to detect a phase difference between the first clock signal and the output clock signal, and the phase detection block is configured to generate a plurality of first control signals and to generate a plurality of second control signals based on the phase difference; an inverter configured to invert the first clock signal; a plurality of first transistors electrically connected between an input terminal of the inverter and a first voltage terminal and each of the plurality of first transistors configured to perform a switching operation in response to one of the first clock signal and a first of the plurality of second control signals, the plurality of first transistors include, a first transistor electrically connected between the input terminal of the inverter and a first node and configured to operate in response to a second clock signal output from the inverter, a second transistor electrically connected between the first node and a second node and configured to operate in response to the first clock signal, and a third transistor electrically connected between the second node and the first voltage terminal and configured to operate in response to the first of the plurality of second control signals; and a plurality of second transistors electrically connected between an output terminal of the inverter and a second voltage terminal and each of the plurality of second transistors configured to perform a switching operation in response to one of the first clock signal and a second of the plurality of second control signals, the plurality of second transistors include, a fourth transistor electrically connected between the output terminal of the inverter and a third node and configured to operate in response to the first clock signal, a fifth transistor electrically connected between the third node and a fourth node and configured to operate in response to the second clock signal, and a sixth transistor electrically connected between the fourth node and the second voltage terminal and configured to operate in response to the second of the plurality of second control signals, wherein a number of the plurality of delay cells are configured to generate the output clock signal from the first clock signal in response to the plurality of first control signals during a locking operation and a phase delay value of at least one delay cell of the plurality of delay cells is controlled in response to the plurality of second control signals after the locking operation is completed.