Patent ID: 7202656

Claim:
An integrated circuit configured for timing delay fault testing, the integrated circuit comprising: a reference clock input signal path configured to receive an externally generated reference clock signal having a first frequency; a phase lock loop coupled to the reference clock input signal path and configured to generate a PLL Clock signal having a second frequency wherein the second frequency is higher than the first frequency of the external reference clock signal; a TDF enable input signal path configured to receive an externally generated TDF enable signal to enable operation of the integrated circuit to perform timing delay fault testing; and control logic coupled to receive the PLL Clock signal and coupled to receive the TDF enable signal and configured to use the PLL Clock signal to generate a timing delay fault launch pulse and to generate a timing delay fault capture pulse, wherein the control logic further comprises: gate logic coupled to receive the PLL Clock signal and configured to selectively apply the PLL Clock signal to a TDF Clock signal path within the integrated circuit in response to receipt of a Control Signal; and counter logic communicatively coupled to the gate logic to generate the Control Signal for a duration of two clock periods of the PLL Clock signal in response to receipt of the TDF enable signal, and wherein the gate logic further comprises: an AND gate having two input signal paths and an output signal path coupled to the TDF Clock signal path; and a D-flop having a clock input coupled to receive the PLL Clock signal and having a CLR input coupled to receive the Control Signal and having a D input signal path coupled to a logic 1 level and having a Q output signal path, wherein the Q output signal path is coupled to a first input of the AND gate and wherein the second input signal path of the AND gate is coupled to the PLL Clock signal such that the PLL Clock signal is applied to the TDF Clock signal path only for such period of time as the CLR input is held active high by the Control Signal.