Patent ID: 7853838

Claim:
An apparatus for handling a failure of an address line from among memory address lines connected from the apparatus to a memory, each of the memory address lines representing a bit, and the apparatus receiving a system address from a processor via system address lines connected from the processor and the apparatus, the apparatus comprising: a failed address line specifying unit that examines the memory address lines and specifies a failed address line; an address line substituting unit that switches between an input from an upper address line connected to an upper bit of the system address lines and an input from a branch address line branched off from a lower address line connected to a lower bit of the system address lines other than the upper bit, outputs either of the inputs to an upper bit of the memory address lines, and outputs the input from the upper address line when the failed address line specifying unit does not specify a failed address line, the upper bit of the memory address lines corresponding to the upper bit of the system address lines; and an address line substitution instructing unit that instructs the address line substituting unit to output the input from the branch address line branched off from the lower address line when the failed address line specifying unit specifies a memory address line corresponding to the lower address line, as the failed address line.