Patent ID: 7251803

Claim:
A method of re-implementing at least one memory module having an undesirable timing delay, the at least one memory module having the undesirable timing delay being on an FPGA device, the FPGA device comprising generic logic blocks and dedicated logic blocks, the at least one memory module having the undesirable timing delay being implemented by a first set of at least one of the logic blocks, the at least one logic block of said first set having at least one critical pin, the method comprising: (a) identifying the at least one memory module having the undesirable timing delay; (b) selecting a second set of logic blocks for use in re-implementing said at least one memory module having the undesirable timing delay, at least a first logic block of the said second set having a pin that is logically equivalent to said at least one critical pin of the at least one logic block of said first set, the first logic block of the second set being non-identical to the at least one logic block of the first set; and (c) selectively re-implementing the at least one memory module having the undesirable timing delay using the second set of logic blocks in the event that re-implementation using the second set of logic blocks reduces the undesirable timing delay of the at least one memory module having the undesirable timing delay.