Patent ID: 8338252

Claim:
A method of manufacturing a non-volatile semiconductor memory device, comprising: forming a well region of a first conductivity type in a silicon substrate; forming a gate insulation film on the silicon substrate; forming a gate electrode of a memory cell transistor, a gate electrode of a first selection gate transistor adjacent to the memory cell transistor, a gate electrode of a second selection gate transistor adjacent to the first selection gate transistor, on the gate insulation film; injecting a first impurity having the first conductivity type between the first selection gate transistor and the second selection gate transistor, while covering a region between the gate electrode of the memory cell transistor and the gate electrode of the first selection gate transistor, using a mask; and injecting a second impurity having a second conductivity type different from the first conductivity type of the first impurity between the first selection gate transistor and the second selection gate transistor and between the gate electrode of the memory cell transistor and the gate electrode of the first selection gate transistor and between the gate electrode of the memory cell transistor, using the gate electrode of the memory cell transistor, the gate electrode of the first selection gate transistor and the gate electrode of the second selection gate transistor as a mask.