Patent ID: 7504725

Claim:
A semiconductor memory device comprising: a semiconductor substrate which has a conductive region; an insulating layer on the semiconductor substrate; and an interlayer insulating film on the insulating layer, the interlayer insulating film having a contact hole that exposes the conductive region; a bit line on an upper surface of the insulating layer and electrically connected to the conductive region, the bit line comprising: a barrier metal layer on the upper surface of the insulating layer; an amorphous conductive layer on the surface of the barrier metal layer; a tungsten nucleation layer on the amorphous conductive layer; and a bulk tungsten layer on the tungsten nucleation layer; and a contact plug within the contact hole, the barrier metal layer being on a surface of the contact hole, the contact plug being between the barrier metal layer on the surface of the contact hole and the amorphous conductive layer.