Patent ID: 7765424

Claim:
A system for injecting phase jitter in a digital signal, comprising: a delay circuit having an input to which an input clock signal is applied, the delay circuit being configured to delay the input clock signal to provide a delayed clock signal, the delayed clock signal being delayed from the input clock signal by a delay corresponding to a delay control value applied to a control input of the delay circuit; a memory array storing a plurality of the delay control values at respective addresses, the memory array being coupled to the delay circuit to provide one of the delay control values to the delay circuit when the memory array is accessed at a corresponding address; a memory array access circuit coupled to the memory array, the memory array access circuit sequentially addressing the memory array to cause the memory array to sequentially apply delay control values to the delay circuit; and an interface circuit coupled to receive the delayed clock signal and the digital signal, the interface circuit being configured to transmit samples of the digital signal responsive to transitions of the delayed clock signal.