Patent ID: 8319330

Claim:
A semiconductor device comprising: a semiconductor chip having a plurality of surface electrodes; a die pad with the semiconductor chip mounted thereover; a plurality of inner leads arranged around the semiconductor chip; a plurality of wires for coupling the surface electrodes of the semiconductor chip and the inner leads with each other electrically; a sealing body for sealing the semiconductor chip, the inner leads and the wires; a plurality of outer leads integrally coupled to the inner leads respectively and exposed from the sealing body; and exterior plating films formed over surfaces of the outer leads respectively, wherein the exterior plating films are each formed so that the number of grains not larger than 1 μm in diameter and present on an interface side closer to the corresponding lead with respect to a center in the thickness direction of the exterior plating film is larger than the number of grains not larger than 1 μm in diameter and present on a surface side of the exterior plating film.