Patent ID: 8686532

Claim:
A semiconductor device comprising: a semiconductor substrate comprising a first device region, a second device region and a guard ring region, the semiconductor substrate being a first conductivity type, and the guard ring region surrounding the first device region and the second device region; a first semiconductor region formed in the guard ring region, said first semiconductor region being a second conductivity type which is opposite conductivity type to the first conductivity type; a first p-type transistor and first n-type transistor formed in the first device region and a second p-type transistor and a second n-type transistor formed in the second device region; an insulating interlayer formed over the semiconductor substrate; an annular guard ring surrounding both the first device region and the second device region and comprising a conductive film buried in the insulating interlayer and formed over the guard ring region, the annular guard ring being electrically connected to the first semiconductor region; a first well region formed in the first device region, the first well region being the first conductivity type; and a second well region formed in the second device region, the second well region being the first conductivity type, wherein a pn junction plane is formed between the first semiconductor region and the semiconductor substrate.