Patent ID: 8405668

Claim:
A translation unit comprising: a memory comprising a plurality of entries, each entry configured to store a translation for a different virtual page corresponding to a source buffer; and a control circuit coupled to the memory, wherein the control circuit is configured to maintain the memory as a first-in, first-out buffer (FIFO) of translations, and wherein the control circuit is coupled to receive an indication that data fetching is complete from one or more virtual pages corresponding to the source buffer, and wherein the control circuit is configured to discard a corresponding one or more oldest translations from the memory responsive to the indication and to prefetch additional translations for other virtual pages corresponding to the source buffer responsive to the indication, wherein the other virtual pages include a first virtual page that is adjacent to a second virtual page, and wherein a translation for the second virtual page is a most recently fetched translation of the translations stored in the memory, and wherein the second virtual page is different from the one or more virtual pages.