Patent ID: 7779280

Claim:
A computer-implemented method of managing power for a computing device, comprising: under control of a configured computer system having: a primary processor in communication with a primary memory that stores machine state data, wherein the primary processor is configured to consume power at a first rate, and a secondary processor in communication with a secondary memory, wherein the secondary processor is configured to consume power at a second rate that is less than the first rate; distributing power to the primary processor from a power source responsive to the power source level above a selected level; distributing power to the secondary processor instead of the primary processor responsive to the power source level at or below the selected level; and transferring at least a first portion of the machine state data from the primary memory to the secondary memory during switching the power distribution from the primary processor to the secondary processor; wherein at least a second portion of the machine state data that is not transferred to the secondary memory is stored in a non-volatile memory.