Patent ID: 8564030

Claim:
A semiconductor device fabrication process, comprising: providing a transistor comprising one or more replacement metal gates on a semiconductor substrate, wherein the transistor comprises gate spacers of a first insulating material around each gate and a first insulating layer of a second insulating material between the gates and gate spacers, and wherein at least some of the second insulating material overlies sources and drains of the gates; forming one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate; forming mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top; forming a second insulating layer of the second insulating material over the insulating mandrel and the mandrel spacers; forming one or more first trenches to the sources and drains of the gates by removing the second insulating material from portions of the transistor between the insulating mandrels, wherein at least a portion of each mandrel spacer is exposed in each of the first trenches; and forming trench contacts to the sources and drains of the gates by depositing conductive material in the first trenches, wherein the trench contacts are wider at the top than at the bottom.