Patent ID: 8924904

Claim:
A computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication, the computer-implemented method comprising: obtaining a geometric characteristic of an in-line defect on a chip; obtaining design data of the chip including defining a search area where the in-line defect is located on the chip, the design data associated with the in-line defect, wherein the design data includes a design layout within the search area on which the in-line defect was found and routing information of the design layout on which the in-line defect was found; determining a pattern density within the search area around the in-line defect based on the geometric characteristic and the design data; determining, by a criticality factor determination system, a criticality factor of the in-line defect based on the geometric characteristic and the design data within the search area, the criticality factor indicating a likelihood of the in-line defect to cause a failure of the chip; and outputting the criticality factor; and outputting the pattern density, wherein the in-line defect on the chip is inspected and reported by an inspection tool.