Patent ID: 7608491

Claim:
Method for manufacturing an SOI substrate associating at least one silicon based area ( 4 ′) and at least one GaAs based material area ( 8 ) at the thin layer ( 1 ) of the SOI substrate, the SOI substrate comprising a support ( 2 ) having a silicon face supporting successively a layer ( 3 ) of dielectric material and a thin silicon based layer ( 4 ), the method being characterised in that it comprises the following steps: supply of a SOI substrate ( 1 ) comprising a support ( 2 ) having a silicon face mismatched by an angle of between 2° and 10° inclusive, the thin silicon based layer ( 4 ) being oriented parallel to the plane (001) or (010) or (100) or (110) or (101) or (011) or (111), preservation of at least one area ( 4 ′) of the thin silicon based layer ( 4 ), elimination of at least one non-preserved area of the thin layer of silicon until the layer ( 3 ) of dielectric material is revealed, opening, in said non-preserved area, of the dielectric material layer ( 3 ) until the silicon face of the support ( 2 ) is revealed, growth, from the silicon of the support ( 2 ) revealed by said opening ( 6 ) and by liquid phase epitaxy or by lateral epitaxy, of mismatched germanium ( 7 ) on the dielectric material layer revealed, growth of the GaAs based material ( 8 ), from mismatched germanium ( 7 ) obtained in the preceding step.