Patent ID: 7459747

Claim:
A nonvolatile semiconductor memory device comprising: a plurality of word lines; a plurality of data lines; a plurality of memory cells formed on a semiconductor substrate, each of the memory cells comprising a drain region, a transistor and a capacitor, the drain region comprising a first drain region arranged between the transistor and the capacitor, the transistor comprising a impurity-implanted second drain region formed in the drain region, a source region and a gate electrode connected with a corresponding word line, the capacitor comprising an impurity-implanted lower electrode formed in the drain region overlapping or adjacent to the second drain region, an insulation film disposed on the lower electrode and an upper electrode disposed on the insulation film and connected with a corresponding data line, wherein the second drain region and the lower electrode are both formed over the first drain region and both have a higher impurity concentration than the first drain region; and a voltage supply circuit applying a voltage to the data lines, wherein the insulation film is configured to break down when a predetermined voltage is applied to the insulation film through a corresponding data line so that a predetermined data is written in the memory device.