Patent ID: 7216276

Claim:
A system for testing a target integrated circuit, comprising: a test host for running a debugging and testing analysis program, wherein said debugging and testing analysis program transmits testing instructions and data to the target integrated circuit, receives testing results from the target integrated circuit, and analyzes the received testing results; a testing interface on the target integrated circuit for receiving the testing instructions and data from the test host and forwarding the testing instructions and data; a testing unit on the target integrated circuit for receiving the testing instructions and data from the testing interface and for performing testing and debugging of the integrated circuit; a serializer for serializing testing results, and outputting the serialized testing results from the target integrated circuit; a deserializer for deserializing the serialized testing results; an analyzer for receiving the testing results from said deserializer, for storing the testing results, and forwarding the testing results to the test host; and a Joint Task Action Group (JTAG) monitor in communication with the testing unit, wherein the analyzer receives the testing results based in part on input from the JTAG monitor.