Patent ID: 7397284

Claim:
A bootstrapping circuit, comprising: a first transistor coupled between an input node and an output node, wherein a gate of said first transistor is coupled to a first control node; a second transistor having a first end coupled to said first control node, wherein a second end of said second transistor is coupled to a second control node; a capacitor having a first end coupled to said second control node, wherein a second end of said capacitor is coupled to a third control node; a first switching circuit, coupled to said first control node for connecting a ground node to said first control node; a third transistor having a first end coupled to said input node, wherein a gate of said third transistor is coupled to said first control node, and wherein a second end of said third transistor is coupled to said third control node; a second switching circuit, coupled to said second transistor for controlling said second transistor, wherein said second switching circuit is coupled to a first clock node; a fourth transistor having a first end coupled to said third control node, wherein a gate of said fourth transistor is coupled to a second clock node, and wherein a second end of said fourth transistor is coupled to said ground node; a fifth transistor having a first end coupled to said second control node, wherein a gate of said fifth transistor is coupled to a fourth control node, and wherein a second end of said fifth transistor is coupled to a source node; a sixth transistor having a first end coupled to said fourth control node, wherein a gate of said sixth transistor is coupled to said source node, and wherein a second end of said sixth transistor is coupled to said first clock node; and a seventh transistor having a first end coupled to said fourth control node, and wherein a second end of said seventh transistor is coupled to said second control node.