Patent ID: 7088128

Claim:
A circuit arrangement including a plurality of circuit modules comprising: a controller circuit for providing a source of input signals, a source reference voltage, a first termination voltage, and a second termination voltage; an input signal bus having a first end connected to receive said input signals and a second end connected to said first termination voltage; a reference voltage bus having a first end connected to said source reference voltage and a second end connected to said second termination voltage; a first circuit chip comprising a first signal input connected to said input signal bus and a first reference input connected to said reference voltage bus, said first circuit chip operable to detect information by comparing a first signal voltage applied to the first signal input and a first reference voltage applied to the first reference input; a second circuit chip comprising a second signal input connected to said input signal bus and a second reference input connected to said reference voltage bus, said second circuit chip operable to detect information by comparing a second signal voltage applied to the second signal input and a second reference voltage applied to the second reference input; a first resistance between the first signal input and the second signal input; a second resistance between the first reference input and the second reference input; a first termination resistor connecting the second signal input to said second end of said input signal bus; a second termination resistor connecting the second reference input to said second end at said reference voltage bus; and a first ratio between the first resistance and the first termination resistor corresponding to a second ratio between the second resistance and the second termination resistor.