Patent ID: 8211806

Claim:
A method of manufacturing an integrated circuit comprising: providing a substrate having a first material layer over the substrate and a second material layer over the first material layer, wherein the first material layer comprises a dielectric material; patterning the second material layer to form at least two first features with a first opening between the first features, wherein the first opening exposes a top surface of the first material layer; performing a thermal oxidation process to oxidize the first features and the first material layer so as to reduce each width of the first features and to form an oxide layer a surrounding each of the first features and on the first material layer; providing a conductive layer over the oxide layer; planarizing the conductive layer to expose the oxide layer; and removing the conductive layer, the oxide layer, and the first material layer underneath the oxide layer to form a number of second features and expose portions of the substrate, wherein a second opening is formed between each two neighboring second features and wherein the second opening is narrower than the first opening.