Patent ID: 8183135

Claim:
A method for manufacturing a thin film transistor having a source region and a drain region formed in a polycrystalline silicon thin film and a gate electrode formed on said polycrystalline silicon thin film with a gate insulating film interposed between said polycrystalline silicon thin film and said gate electrode, said method comprising: a process of forming an island-structured polycrystalline silicon thin film on an insulating substrate; a process of forming, after having formed said gate insulating film on said polycrystalline silicon thin film, a micro-crystalline silicon thin film and a metal thin film sequentially on said gate insulating film; a process of etching, after having formed a corrosion-resistant mask layer on said metal thin film, said metal thin film using said corrosion-resistant mask layer to form said gate electrode having a desired shape; a process of etching said micro-crystalline silicon thin film using said corrosion-resistant mask layer to form a hydrogen feeding layer having an approximately same shape as said gate electrode; a process of forming a first insulating film on entire surfaces being exposed containing a surface of said gate electrode; a process of selectively implanting an impurity of a conductive type on said polycrystalline silicon thin film to form said source region and said drain region; a process of forming contact holes in said first insulating film and said gate insulating film in a manner to expose said source region and said drain region and forming a source electrode to be connected to said source region through one of said contact holes and a drain electrode to be connected to said drain region through another of said contact holes; and a process of forming a second insulating film on entire surfaces being exposed containing surfaces of said source electrode and said drain electrode, wherein each process after having formed said micro-crystalline silicon thin film is performed at room temperature being lower than about 400° C. to prevent hydrogen from being unnecessarily released from said micro-crystalline silicon thin film, wherein said process of forming said second insulating film is performed using SiH 4 , NH 3 , and H 2 as reactant gas at 300° C. to 400° C. simultaneously to feed hydrogen from said hydrogen feeding layer into an interface between said polycrystalline silicon thin film and said gate insulating film, and wherein said process of forming said second insulating film is performed in an atmosphere containing hydrogen plasma to improve an efficiency of hydrogenation of said interface.