Patent ID: 7880709

Claim:
A display apparatus comprising: at least two display units, each of which has a plurality of pixels arranged in a matrix; a clock pulse generating unit which generates a clock pulse; a pulse generating unit which includes a plurality of shift register units which each generate a separate timing pulse for groups of pixels in each display unit based on the clock pulse; a write pulse generating unit which simultaneously generates a write pulse to the plurality of pixels in each display unit based on the timing pulse; a detection unit which detects the rising and falling edges of the timing pulse generated by the last shift register to process the clock signal in each display unit and which calculates and generates a detection pulse; at least one delay counter unit for each display unit which receives a reset count for each display unit and the clock pulse from the clock pulse generating unit and generates a delay pulse for each display unit based on the reset count and clock pulse; and a timing adjustment unit which receives the detection pulse for each display unit from the detection unit and the delay pulse for each unit and adjusts the timing pulse for each display unit separately by decoding the delay pulse based on the detection pulse to minimize the amount of the timing delay, wherein, the write pulse is sent in parallel to a subset of said plurality of pixels of each display unit.