Patent ID: 8099632

Claim:
A method for operating a NAND memory storage device having a controller and a NAND memory in an isochronous system, the method comprising: performing a plurality of read operations of the NAND memory that are requested by a system processor; performing at least one write operation of the NAND memory that is requested by the system processor; gathering an indicia of errors in the NAND memory; assessing the indicia of errors; based on assessing the indicia of errors, providing one or more alerts of a first level to the system processor that a data integrity operation should be performed within the NAND memory; based on assessing the indicia of errors, changing the level of alerts to be provided to the system processor to a second level; providing one or more alerts of the second level to the system processor that a data integrity operation should be performed within the NAND memory, wherein each of the one or more alerts of the first level and the second level are provided, in an isochronous cycle for requesting a read or a write operation, to the system processor; sending a request for a grant of time, either at the end or in a sideband of the isochronous cycle, from the controller to the system processor for tending to internal housekeeping operations; and in response to the request, at the controller receiving from the system processor a grant of time for tending to the internal housekeeping operations at the NAND memory such that the isochronous cycle is not disturbed.