Patent ID: 7335943

Claim:
A vertical MOS transistor comprising: a vertically stacked sandwich arrangement of drain, channel, and source regions with a top and bottom on a lightly doped silicon substrate within an active area defined by isolation regions in the substrate wherein one of the source and drain regions is at least partially in the substrate with a first extension at the bottom of the sandwich arrangement and extending away from the stacked sandwich arrangement and having a first conductivity type, the channel having a second conductivity type and the other of the source and drain regions at the top of the sandwich arrangement having the first conductivity type; an L-shaped gate with upright portions laterally adjacent to said stacked sandwich arrangement but separated by thin insulation, the gate having a non-upright portion forming a second extension away from the stacked sandwich arrangement and separated from the first extension by said thin insulation; and a plurality of electrical contacts with first and second contacts having vertical portions contacting said first and second extensions and a third contact contacting the region at the top of the sandwich arrangement, the first, second, and third contacts having portions arranged in a planar array.