Patent ID: 7394155

Claim:
An interconnect structure comprising: a substrate having an active region, said active region comprising a gate structure having a gate electrode over a gate dielectric layer in said active region and first and second source/drain regions adjacent each side of said gate structure wherein said first source/drain region located between said gate structure and said shallow trench isolation region; a patterned conductor layer over a shallow trench isolation region adjacent the active region; a bridging conductor layer formed upon a top surface and and directly contact a top surface of said patterned conductor layer, an entire sidewall surface of said patterned conductor layer, layer, and a surface of the active region, said bridging conductor layer forming an electrical connection between said patterned conductor layer and said surface of said active region; and, an interlevel dielectric layer over said bridging conductor layer, said gate electrode, and said second source/drain region; a first conductor filled via extending through said interlevel dielectric layer to said bridging conductor layer, said first conductor filled via over a portion of said patterned conductor layer and a portion of said first source/drain region, said first conductor filled via extending to said bridging conductor layer including to said bridging conductor layer upon and directly contact said top surface and said entire sidewall surface of the patterned conductor layer.