Patent ID: 7269528

Claim:
A method for evaluating a threshold level of a data cell structure in an electrical memory storage device; said electrical memory storage device including at least one programming locus coupled with said data cell structure for receiving at least one programming signal for setting a stored signal level in said data cell structure; said electrical memory storage device responding to a read signal at a predetermined read signal level to indicate said stored signal level in an output signal at a read output locus; the method comprising the steps of: (a) in no particular order: (1) selecting at least one test threshold signal level; and (2) setting said read signal at a non-read signal level other than said predetermined read signal level; (b) applying said at least one test threshold signal level to said at least one programming locus; (c) effecting a cycling of said read signal substantially between said predetermined read signal level and said non-read signal level while applying said at least one test threshold signal level to said at least one programming locus to present at least two test signals at said read output locus when said read signal is substantially at said predetermined read signal level; and (d) while effecting said cycling, observing whether said at least two test signals manifest a difference less than a predetermined amount at an output node of the electrical memory storage device to verify proper operation of said electrical memory storage device.