Patent ID: 7776680

Claim:
A method of forming a semiconductor device, said method comprising: providing a p-type substrate, having a first section and a second section positioned laterally adjacent to said first section; forming an n-type well region in said first section; forming a first gate stack on said first section and a second gate stack on said second section, wherein said forming of said first gate stack and said second gate stack comprises: forming a dielectric layer adjacent to said substrate; forming an n-type metal layer adjacent to said dielectric layer; forming a polysilicon layer adjacent to said n-type metal layer; and patterning and etching said polysilicon layer, said n-type metal layer and said polysilicon layer so as to form said first gate stack and said second gate stack; and removing said polysilicon layer and said n-type metal layer from said first gate stack; and electroplating a p-type metal layer on said dielectric layer of said first gate stack, wherein said electroplating is performed with a current applied to said substrate and under illumination so as to ensure electron flow through said substrate and said n-type well region to said first gate stack.