Patent ID: 7968965

Claim:
A device, comprising: a first device including a plurality of first transistors formed on a substrate, a first multilayered interlayer insulation film formed over the substrate, a protective layer formed on the first multilayered interlayer insulation film, a plurality of first metal wires formed in the first multilayered interlayer insulation film, and a plurality of first contacts formed in the first multilayered interlayer insulation film to interconnect the plurality of first metal wires; an etch stop layer formed on the protective layer; a silicon epitaxial layer formed over the etch stop layer; a second device formed over the silicon epitaxial layer, wherein the second device includes a plurality of second transistors on the silicon epitaxial layer, a second multilayered interlayer insulation film over the silicon epitaxial layer, a plurality of second metal wires formed in the second multilayered interlayer insulation film, and a plurality of second contacts formed in the second multilayered interlayer insulation film to interconnect the plurality of second metal wires; and a connection via formed through the silicon epitaxial layer, the etch stop layer, and the protective layer to electrically interconnect the first device and the second device.