Patent ID: 7418698

Claim:
A method of handling register spills in a CPU having parallel registers, said parallel registers including a first register set and a second register set, the method comprising: (i) determining that register spill instructions in spill code generated by a register allocator can be paired, wherein paired register spill instructions relate to corresponding register locations in each of the first register set and the second register set and that no instructions between said register spill instructions modify any of said register spill instructions; (ii) based on determining, modifying said register spill instructions as a parallel register spill instruction; and (iii) based on said modified parallel register spill instruction, configuring storage of associated register spills in memory in such a manner that said register spills can be loaded into said first and second register sets in parallel, wherein the configuring includes allocating space on a memory stack such that paired register spills are double word aligned.