Patent ID: 6879188

Claim:
A semiconductor integrated circuit device comprising: a first clock signal generating circuit which receives a reference clock and outputs a first clock signal, wherein the first clock signal is phase-synchronized with the reference clock and has a frequency which is a multiple or a fraction of a frequency of the reference clock; a second clock signal generating circuit which receives the reference clock and outputs a second clock signal, wherein the second clock signal is phase-synchronized with the reference clock and has a frequency which is a fraction of the frequency of the reference clock; a selector which selects one of the first clock signal and the second clock signal; and a clock control circuit which specifies whether the first clock signal or the second clock signal should be selected by the selector, wherein one of the first clock signal and the second clock signal selected by the selector is distributed to an internal circuit of the semiconductor integrated circuit device, wherein the first clock signal generating circuit takes a longer clock-settling time than the second clock signal generating circuit, wherein the clock control circuit includes a register which sets an operating state of the first clock signal generating circuit and an operating state of the second clock signal generating circuit, and the register is updated from outside of the semiconductor integrated circuit device, and wherein the semiconductor integrated circuit device can be in at least three states when the selector selects the first clock signal and the semiconductor integrated circuit device can be in at least two states when the selector selects the second clock signal.