Patent ID: 7187738

Claim:
Signal generating circuitry comprising: a first clocked element connected for receiving a clock signal and a first synchronised signal which changes its logic state synchronously with respect to said clock signal, and switchable by said clock signal between a responsive state, in which the element is operable in response to said state change in said first synchronised signal to change a logic state of a second synchronised signal produced thereby, and a non-responsive state in which no state change in the second synchronised signal occurs; and a second clocked element connected for receiving said clock signal and said second synchronised signal, and switchable by said clock signal between a responsive state, in which the element is operable in response to said state change in said second synchronised signal to change a logic state of a third synchronised signal produced thereby, and a non-responsive state in which no state change in the third synchronised signal occurs; wherein, when said clock signal has a first logic state the first clocked element has said non-responsive state and said second clocked element has said responsive state, and when said clock signal has a second logic state the first clocked element has said responsive state and said second clocked element has said non-responsive state.