Patent ID: 8225248

Claim:
A method of compensating for manufacturing defects, comprising: receiving a circuit design having a layout including a plurality of devices and a plurality of interconnects; calculating a manufacturing variance of a device or interconnect, wherein the manufacturing variance is due to manufacturing effects of a neighboring device or interconnect on the device or interconnect; modifying the circuit design to compensate for the manufacturing variance thereby generating a modified circuit design, wherein modifying the circuit design comprises modifying a cell within the circuit design by applying the manufacturing variance to the cell; and storing the modified circuit design on a non-transitory computer readable storage medium; wherein the manufacturing variance includes a capacitance variation, and wherein determining the capacitance variation comprises: discretizing each interconnect into rectangular subsegments, wherein each subsegment is represented by at least one dimension; discretizing the subsegments into a plurality of panels; and calculating a coefficient of potential at each panel due to a unit charge placed on every other panel of the plurality of panels; generating a potential matrix that includes coefficients of potential of all panels of each interconnect; generating a capacitance matrix by inverting the potential matrix, the capacitance matrix including capacitances of all panels of the interconnect; and determining capacitance between any pair of subsegments by summing capacitances between corresponding panels of the subsegments using information of the capacitance matrix.