Patent ID: 6853221

Claim:
A power monitor circuit operable to notify processing circuits operating from a first power supply having a VDD output voltage when a second power supply having a VDDIO output voltage is powered up, wherein VDDIO is greater than VDD, said power monitor circuit comprising: a voltage divider circuit coupled to said first power supply and said second power supply and between said second power supply and ground, said voltage divider circuit having an output node that rises to a high voltage when said second power supply is powered up; and one or more inverters operating from said first power supply, said one or more inverters comprising an odd number of serially connected inverters, wherein an input of one of said one or more inverters is connected to said voltage divider circuit output node and an output of one of said one or more inverters produces a status signal that is low when said voltage divider circuit output node is high and is high when said voltage divider circuit output node is low, and wherein said status signal is an input signal to said voltage divider circuit operable to minimize DC current consumption in said voltage divider circuit when said second power supply is powered up while maintaining a value of said status signal.