Patent ID: 7580305

Claim:
A semiconductor memory, comprising: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of the precharged first and second bit lines according to a signal held by the selected memory cell; word lines for selecting the memory cells; first and second reference cells connected to the first and second bit lines, respectively, a selected one of the first and second reference cells discharging the first or second bit line connected to the selected reference cell; and first and second reference cell word lines for selecting the first and second reference cells, respectively, wherein when one of the memory cells connected to one of the first and second bit lines is selected for reading a signal held in the memory cell, one of the reference cells which is connected to the other bit line is selected.