Patent ID: 7193275

Claim:
A logic circuit comprising: first and second field-effect transistors connected in series between nodes respectively supplying first and second voltages, and having a first conductivity type and a conductivity type opposite to said first conductivity type, respectively; each of said first and second field-effect transistors including: a source and a drain, a rectangular first gate for forming a channel region between said source and said drain, and a second gate formed in a region between said source and said drain for forming a channel region between said source and said drain, and overlapping at least partially with said first gate in a plan view; geometry of said second gate being defined by a group of straight lines along geometry of said first gate, and providing a gate length discontinuously changing at least in one position along the gate length; a signal input node connected to said first gate of each of said first and second field-effect transistors; a signal output node connected to connection nodes of said first and second field-effect transistors; and a control input node for controlling voltages applied to said second gates of said first and second field-effect transistors.