Patent ID: 7012465

Claim:
A circuit having a class-AB output stage, comprising: first, second, third, and fourth MOS transistor devices configured in a translinear loop including semiconductor junctions of the first, second, third, and fourth MOS transistor devices connected in series, semiconductor junctions of a first pair of the first, second, third, and fourth MOS transistor devices connected in a clockwise direction, and semiconductor junctions of a second different pair of the first, second, third, and fourth MOS transistor devices connected in a counter-clockwise direction, the first MOS transistor device carrying a first control current, the second MOS transistor device carrying a second control current, the third MOS transistor device carrying a current equal to the sum of the first and second control currents, and the fourth MOS transistor device carrying a bias current; a first output circuit coupled to a first voltage supply and an output node, the first output circuit sourcing a first output current based on the first control current; and a second output circuit coupled to a second voltage supply and the output node, the second output circuit sourcing a second output current based on the second control currents.