Patent ID: 8565007

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; a plurality of first word lines extending in a stacking direction perpendicular to the semiconductor substrate, the first word lines being arranged having a certain pitch in a first direction parallel to a surface of the semiconductor substrate and being arranged having a certain pitch in a second direction parallel to the surface of the semiconductor substrate and orthogonal to the first direction; a plurality of bit lines extending in the first direction and arranged having a certain pitch in the second direction and the stacking direction, the bit lines being configured to intersect the first word lines such that a first surface of the bit lines faces the first word lines; a resistance varying material disposed at respective intersections of the first word lines and the bit lines; a plurality of second word lines extending in the stacking direction and arranged having a certain pitch in the first direction and the second direction, the second word lines being configured to intersect the bit lines so as to face a second surface of the bit lines, the second surface of the bit lines being on an opposite side of the first surface of the bit lines; and an insulating film disposed at respective intersections of the second word lines and the bit lines, the first word lines and the second word lines being disposed alternately in the second direction so as to sandwich the bit lines, the second word lines, the bit lines, and the insulating film configuring a field-effect transistor at respective intersections of the second word lines and the bit lines, the field-effect transistor having one of the second word lines as a control electrode and one of the bit lines as a channel region, and the field-effect transistor and the resistance varying material configuring one memory cell.