Patent ID: 7375409

Claim:
A semiconductor device, comprising: a supporting substrate; an insulating layer formed on the supporting substrate; a first semiconductor layer formed on the insulating layer; a first high breakdown-voltage transistor formed in the first semiconductor layer; a second semiconductor layer formed on the insulating layer; a second high breakdown-voltage transistor formed in the second semiconductor layer; a first element isolation region having a depth that reaches the insulating layer and provided between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the insulating layer; a first low breakdown-voltage transistor formed in the third semiconductor layer; a second low breakdown-voltage transistor formed in the third semiconductor layer; and a second element isolation region having a depth that terminates prior to reaching the insulating layer and formed in the third semiconductor layer and provided between the first low breakdown-voltage transistor and the second low breakdown-voltage transistor, wherein the first element isolation region comprises a trench insulating layer having a dual-trench structure; and the first and the second high breakdown-voltage transistors further comprise: a first gate insulating layer formed above a channel region; and a second gate insulating layer formed of outer edges of the first gate insulating layer and of a second trench insulating layer, and above an offset region, wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer and the outer edges of the first gate insulating layer are stepped upward from an inner portion of the first gate insulating layer, wherein only the first and second high breakdown-voltage transistors are formed in each of the first and second semiconductor layers, respectively.