Patent ID: 7470614

Claim:
A method for fabricating a semiconductor structure, the method comprising the steps of: providing a semiconductor substrate; forming two members extending from said semiconductor substrate, wherein said two members are separated by a portion of said semiconductor substrate; forming a first semiconductor device and a second semiconductor device in and on said semiconductor substrate, wherein said first and second semiconductor devices each comprise a common impurity doped region that is disposed within said portion of said semiconductor substrate; depositing a dielectric layer overlying said two members, said first and second semiconductor devices, and said common impurity doped region to a thickness such that a depression within said dielectric layer and overlying said common impurity doped region is formed; depositing a fill material to at least substantially fill said depression; etching a portion of said dielectric layer after the step of depositing said fill material such that said dielectric layer is etched at a faster rate than said fill material; depositing a masking layer overlying said dielectric layer and said fill material; removing a portion of said masking layer to expose said fill material and form an etch mask that is self-aligned to said fill material; etching said fill material and said dielectric layer using said etch mask to form a via through said dielectric layer; depositing a conductive material within said via such that said conductive material is electrically coupled to said impurity doped region.