Patent ID: 7218558

Claim:
An integrated circuit memory device, comprising: a memory array having a plurality of multi-column memory blocks therein; a multi-column redundant memory array; a redundancy column selecting unit configured to route data read from said multi-column redundant memory array to a redundant data line, in response to a column address; a data input/output unit connected to the redundant data line and a data line associated with a defective column in said memory array, said data input/output unit configured to respond to an instruction to read first data from the defective column in said memory array by routing first data read from a selected redundant column in said multi-column redundant memory array to an input/output bus while concurrently blocking data read from the defective column from being transferred to the input/output; and a redundancy data input unit having an output connected to the redundant data line, a first plurality of inputs connected to the input/output bus and a second plurality of inputs responsive to a plurality of input/output selection signals.