Patent ID: 8514650

Claim:
A semiconductor memory device comprising: a first bank group configured to include a first bank and a second bank; a second bank group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first bank group and the second bank group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first bank group and the second bank group in response to the address strobe pulse signal and a second bank address, wherein the address strobe pulse signal is shared by the first bank group and the second bank group, wherein the strobe signal generating unit comprises: a decoder configured to decode the second bank address into a bank signal; a first strobe signal generator configured to generate a first strobe signal or a second strobe signal in response to the address strobe pulse signal, a bank grouping signal and the bank signal, and output the first strobe signal or the second strobe signal to a corresponding bank of the first bank group; and a second strobe signal generator configured to generate a third strobe signal or a fourth strobe signal in response to the address strobe pulse signal, the bank grouping signal and the bank signal, and output the third strobe signal or the fourth strobe signal to a corresponding bank of the second bank group.