Patent ID: 8407564

Claim:
An apparatus, comprising a processor and a non-volatile (NV) memory, the NV memory comprising a memory controller to control reading a NV memory array, the apparatus to perform operations comprising: obtaining a block of binary data read from a specified range of sequentially-addressed memory cells in a charge-based non-volatile (NV) memory, the block containing errors that were uncorrectable by an error checking and correcting (ECC) unit, the block covering a single codeword in an ECC process; determining, for each of the memory cells in the range of memory cells, respective changes in read reference voltages that would offset effects of systematic noise on each of the memory cells in the range of memory cells, to produce respective changed read reference voltages; quantizing the respective changed read reference voltages into multiple quantized values, the multiple quantized values being nearest incremental read reference voltage values that are likely to correct the errors; organizing the memory cells into groups, each group associated with a particular respective one of the multiple quantized values; changing the read reference voltage to equal a first of the quantized values; reading data from the group of memory cells associated with the first of the quantized values such that only the data from the group associated with the first of the quantized values is retained; repeating iterations of said changing and said reading for each of the other groups associated with the other quantized values, such that, in the iterations of the reading, only respective data from respective ones of the groups associated with respective ones of the quantized values is retained; combining the respective data obtained with and retained in said changing, said reading, and said repeating, into a combined data set covering the codeword; and processing the combined data set through the ECC process.