Patent ID: 8189379

Claim:
A FLASH memory device comprising: a plurality of FLASH memory cells configured to store data received from a source external to the flash memory device; and at least one modified memory cell associated with the plurality of FLASH memory cells that is configured in such a manner that it is more susceptible to a read disturb error than the plurality of FLASH memory cells, each of the plurality of FLASH memory cells and the modified memory cell including a floating gate transistor; and circuitry for applying a voltage to a gate of the modified memory cell when a voltage is applied to a gate of at least one of the plurality of FLASH memory cells, wherein voltages are applied to the gates of the plurality of FLASH memory cells and the modified memory cell during a READ operation, the voltages that are applied to the gates of the plurality of FLASH memory cells varying depending on whether the FLASH memory cell is being read during the READ operation; wherein an amount of time the voltage is applied to the gate of the modified memory cell during a READ operation is greater than an amount of time a voltage is applied to the gate of one of the plurality of FLASH memory cells that is not being read as part of the READ operation, such that the greater amount of time over which the voltage is applied to the gate of the modified cell configures the modified memory cell so that it is more susceptible to a read disturb error than the plurality of FLASH memory cells.