Patent ID: 7456673

Claim:
A multi-phase clock generator comprising: a first delay line generating a first clock signal by delaying an input clock for a first delay time; a second delay line generating a second clock signal by delaying the input clock for a second delay time in response to a control signal; a phase detector detecting a phase difference between the first and second clock signals; and an up/down counter generating the control signal in response to an output of the phase detector, wherein the phase detector comprises: a first NAND gate receiving the first clock signal and an inverted second clock signal; a second NAND gate receiving the second clock signal and a third clock signal; a first single-to-differential converter converting an output of the first NAND gate into first differential signals A and /A; a second single-to-differential converter converting an output of the second NAND gate into second differential signals B and /B; a first integrator performing an integration on the first differential signals in response to a control clock having a period that is two times a period of the differential signals; a second integrator performing an integration on the second differential signals in response to the control clock; and a comparator comparing outputs of the first and the second integrators, wherein the third clock signal is a signal obtained by converting a phase of the first clock signal, and wherein the control clock has a period that is two times the period of the differential signals.