Patent ID: 8409956

Claim:
A method of forming an integrated circuit device, comprising: forming first and second gate electrodes at side-by-side locations on a substrate; forming first and second sidewall spacers on sidewalls of the first gate electrode and the second gate electrode, respectively; covering the first and second gate electrodes with a first electrically insulating layer of a first material; depositing a second electrically insulating layer of a second material on the first electrically insulating layer; patterning the second electrically insulating layer to define a first opening therein that exposes a first portion of the first electrically insulating layer; selectively etching the first portion of the first electrically insulating layer to define a second opening therein that exposes a first portion of the substrate, a first sidewall spacer on the first gate electrode, a second sidewall spacer on the second gate electrode and an upper surface of the second gate electrode, using the second electrically insulating layer as an etching mask; lining sidewalls of the first and second openings, the first and second sidewall spacers, the exposed first portion of the substrate and the exposed upper surface of the second gate electrode with an electrically insulating protective layer comprising the second material; removing a portion of the electrically insulating protective layer from between the first and second gate electrodes to expose the first portion of the substrate; and filling the second opening and at least a portion of the first opening with an electrically conductive material.