Patent ID: 7101776

Claim:
A method of fabricating a MOS transistor comprising: a) forming an insulated gate pattern on a semiconductor substrate, the insulated gate pattern including a silicon pattern and a sacrificial layer pattern sequentially stacked, wherein forming the insulated gate pattern comprises sequentially forming a gate insulating layer and a silicon layer on the semiconductor substrate, forming a sacrificial layer on the semiconductor substrate having the silicon layer, doping the silicon layer with impurities to control a threshold voltage prior to formation of the sacrificial layer, and sequentially patterning the sacrificial layer and the silicon layer; b) forming spacers covering sidewalls of the gate pattern; c) injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks to form source/drain regions; d) removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions to expose the silicon pattern; and e) converting the exposed silicon pattern into a gate silicide layer, and concurrently selectively forming source/drain silicide layers at surfaces of the source/drain regions.