Patent ID: 8627263

Claim:
A method comprising: determining, by a processor, a power consumption for a number of logic gates in an electronic circuit that exceeds a threshold value; selecting a logic gate of the number of logic gates to be resized in response to determining the power consumption for the logic gate exceeds the threshold value; and determining, from a library, a gate configuration for the logic gate to be resized, the determining the gate configuration to be resized comprising, defining at least one variable for the logic gate to be resized, wherein the at least one variable comprises at least one of to be resized and a speed factor of the logic gate to be resized; defining at least one net influenced by the logic gate to be resized; determining at least one constraint relative to other logic gates of the number of logic gates in the electronic circuit affected by the logic gate to be resized, wherein the at least one constraint comprises timing at an output at the at least one net; formulating an objective function, wherein the objective function comprises a formulation of a sum of power metrics at the at least one net influenced by the logic gate to be resized; solving the objective function based on the at least one variable and the at least one constraint; and selecting the gate configuration from the library for the logic gate to be resized based on the solved objective function.