Patent ID: 7447932

Claim:
A semiconductor data processing device, comprising: a first peripheral circuit that inputs and outputs parallel data in units of 2n bits; a second peripheral circuit that inputs and outputs parallel data in units of 2n bits; a data transfer controller capable of controlling data transfer between the first and the second peripheral circuits and that inputs and outputs data in parallel in units of 2n bits; a 2n-bit first data bus coupled to the data transfer controller; a 2n-bit second data bus coupled to the first and the second peripheral circuits; a bus controller for connecting said first data bus to said second data bus; and a central processing unit that processes parallel data in units of n bits or less, coupled to one of a lower and an upper part of said first data bus, wherein the bus controller fixes the correspondence between each signal line of the second bus and a bit position of access data and varies the correspondence between each signal line of the first data bus and bit positions of the access data according to access data size.