Patent ID: 8862909

Claim:
A semiconductor chip comprising: one or more processing units, each assigned a respective power limit that is a portion of a chip power limit for the semiconductor chip; an input/output (I/O) controller (IOC) comprising a plurality of interfaces, wherein the IOC is assigned an I/O power limit that is a portion of the chip power limit; and a power manager; wherein the IOC is configured to determine a power estimate for the IOC based at least in part on monitored activity levels of the interfaces; and wherein in response to detecting a difference between the power estimate and an assigned I/O power limit, the power manager is configured to adjust a power limit of at least one of the processing units based on said difference; wherein the IOC is further configured to determine the power estimate based on a ratio of a number of either or both input/output (I/O) and direct memory access (DMA) transactions on a given interface to a maximum number of I/O and DMA transactions supported by the given interface during a given time interval.