Patent ID: 8472253

Claim:
A nonvolatile semiconductor memory device comprising: a memory-cell array including a plurality of memory cells connected to a plurality of word lines; a first row decoder and a second row decoder, both provided in a first region, and each configured to select a word line from the plurality of word lines; a first power line provided in the first region, and configured to transfer a first voltage to the first row decoder; a second power line provided in the first region, and configured to transfer the first voltage to the second row decoder; a first power-supply circuit configured to supply the first voltage to the first power line and to the second power line; a first switching circuit configured to switch between connection and disconnection between the first power line and the first power-supply circuit; and a second switching circuit configured to switch between connection and disconnection between the second power line and the first power-supply circuit, wherein in a write operation, the first switching circuit connects the first power line and the first power-supply circuit to each other whereas the second switching circuit disconnects the second power line and the first power-supply circuit from each other.