Patent ID: 8164971

Claim:
A dual power rail word line driver for driving a word line of a memory array according to a predecode signal from a decoder powered by a first supply voltage, comprising: a signal buffering unit coupled between the word line and a node; a pull-down unit coupled between the node and a ground, wherein the pull-down unit is controlled by the predecode signal and a first pulse signal; and a first pull-up unit coupled between the node and a second supply voltage higher than or equal to the first supply voltage, wherein the first pull-up unit is controlled by a second pulse signal; wherein the signal buffering unit provides a word line signal corresponding to the predecode signal to the memory array via the word line when the first pull-up unit is turned off by the second pulse signal and the pull-down unit is turned on by the predecode signal and the first pulse signal, and there is no level shifter on a critical timing path of the dual power rail word line driver.