Patent ID: 8237267

Claim:
A semiconductor device comprising: a memory chip having a front surface with a first front side and a second front side perpendicular to the first front side in a plan view, a plurality of first pads formed on the front surface and arranged along the first front side, a plurality of second pads formed on the front surface, the second pads being arranged along the first front side and further from a periphery of the front surface than the first pads in the plan view, a plurality of third pads formed on the front surface and arranged along the second front side, a plurality of fourth pads formed on the front surface, the fourth pads being arranged along the second front side and further from the periphery of the front surface than the third pads in the plan view, a first wiring coupling the first pads and the second pads, respectively, a second wiring coupling the third pads and the fourth pads, respectively, and a rear surface opposite to the front surface; a microcomputer chip having a main surface with a first main side and a second main side perpendicular to the first main side in the plan view, a plurality of first electrodes formed on the main surface and arranged along the first main side, a plurality second electrodes formed on the main surface and arranged along the second main side, and a back surface opposite to the main surface, and mounted over the front surface of the memory chip such that the first, second, third and fourth pads are exposed from the microcomputer chip in the plan view, and such that the back surface of the microcomputer chip faces to the front surface of the memory chip; a plurality of terminals arranged next to the memory chip in the plan view; a plurality of first wires coupling the first electrodes and the second pads, respectively; a plurality second wires coupling the second electrodes and the fourth pads, respectively; and a plurality of third wires coupling the third pads and the terminals, respectively; wherein the second and fourth pads are arranged closer to the microcomputer chip than the first and third pads, respectively, in the plan view; wherein each of the first electrodes is an electrode for internal interface to perform input and output of data for the interior of a system comprised of the memory chip and the microcomputer chip; and wherein each of the second electrodes is an electrode for external interface to perform input and output of data for the exterior of the system.