Patent ID: 7112480

Claim:
A method of forming an integrated circuit chip containing at least one relatively low-voltage NMOS transistor and at least one relatively high voltage NMOS transistor, comprising: providing a silicon substrate having a first P-well and a second P-well; forming a low-voltage NMOS transistor in the first P-well including source and drain regions in the surface of the silicon substrate spaced by a gate region; forming a first buried N-well in the bottom of the second P-well; forming first and second buried P-layers in the second P-well on the upper surface of the buried N-well; and forming a high-voltage NMOS transistor in the second P-well including source and drain regions in the surface of the silicon substrate, the source and drain regions each spaced from the first and second P-layers and spaced from one-another by a gate region.