Patent ID: 8357591

Claim:
A method of processing a wafer, the method comprising: establishing a line of symmetry to define left and right adjacent die areas on a front side of the wafer and to define corresponding left and right adjacent die areas on a back side of the wafer; using a first photolithographic mask to form a first interconnection layer on the left and right die areas on the front side of the wafer, the first interconnection layer comprising a first portion on the left die area and a second portion different than the first portion on the right die area; using a second photolithographic mask to form a second interconnection layer on the left and right die areas on the front side of the wafer, the second interconnection layer comprising a third portion on the left die area and a fourth portion different than the third portion on the right die area; reusing the first photolithographic mask to form a third interconnection layer on the left and right die areas on the back side of the wafer; and reusing the second photolithographic mask to form a fourth interconnection layer on the left and right die areas on the back side of the wafer.