Patent ID: 7868648

Claim:
An on-die termination (ODT) circuit, comprising: an ODT synchronous buffer configured to receive a first clock signal delay-locked to an external clock signal and configured to generate a synchronous ODT command from an external ODT command in synchronization with the first clock signal; and an ODT gate configured to receive a second clock signal delay-locked to the external clock signal and the synchronous ODT command and configured to generate signals for controlling the ODT based on the second clock signal and the synchronous ODT command, wherein the ODT synchronous buffer includes, a delay unit configured to generate a plurality of delayed clock signals from the first clock signal by sequentially delaying the first clock signal, and a latch unit including a plurality of latches, each of the plurality of latches configured to receive a corresponding one of the plurality of delayed clock signals from the delay unit, the delay unit is configured generate a first delayed clock signal of the plurality of delayed clock signals by delaying the first clock signal, a latch unit configured to latch the external ODT command in response to the first delayed clock signal and output the latched external ODT command as the synchronous ODT command, the delay unit includes, a first delay configured to delay the first clock signal to generate the first delayed clock signal, a second delay configured to delay the first delayed clock signal to generate a second delayed clock signal of the plurality of delayed clock signals, and a third delay configured to delay the second delayed clock signal to generate a third delayed clock signal of the plurality of delayed clock signals, and the latch unit includes, a third latch of the plurality of latches configured to latch the external ODT command in response to the third delayed clock signal output from the third delay, a second latch of the plurality of latches configured to latch the output signal of the third latch in response to the second delayed clock signal output from the second delay, and a first latch of the plurality of latches configured to latch the output signal of the second latch in response to the first delayed clock signal output from the first delay and output the latched signal as the synchronous ODT command.