Patent ID: 8479133

Claim:
A method of configuring a filter in a circuit to be implemented in an integrated circuit, the method comprising: receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; transforming, using a computer, the filter of the high level design to a symmetric transpose filter using a plurality of processing blocks, each processing block of the plurality of processing blocks configured to accommodate a common coefficient associated with the processing block, wherein the filter receives an input signal external to the filter at a first processing block and each processing block after the first processing block is configured to receive a different tap associated with the common coefficient for the processing block and the input signal directly at the processing block, and wherein the first processing block receives a highest order coefficient; implementing, for each processing block of the plurality of processing blocks, a pre-adder circuit having an adder/subtractor coupled to an output of a first logic gate and an output of a second logic gate; coupling, for each processing block of the plurality of processing blocks, control signals to the adder/subtractor, the first logic gate and the second logic gate; dynamically selecting, for each processing block of the plurality of processing blocks, whether the adder/subtractor operates as an adder or a subtractor based upon the control signals during operation of the integrated circuit; and dynamically selecting, for each processing block of the plurality of processing blocks, a register depth to an input port of the first logic gate based upon the control signals during operation of the integrated circuit; wherein a second input port of the first logic gate and a third input port of the second logic gate enable dynamic power gating of the pre-adder circuit to enable power conservation.