Patent ID: 7734899

Claim:
A method of operating a pipelined computer processor, said method comprising: i. identifying program instructions dependent upon results of prior program instructions in a set of instructions; ii. dividing said set of instructions into a plurality of subsets of instructions, each subset comprising a number of instructions from said set of instructions, based on the identified program instructions, each instruction of said set belonging to only one subset; iii. providing a validity pipeline comprising a first and a second stage where said first stage corresponds to a first of said subsets of instructions and said second stage corresponds to a second of said subsets of instructions; iv. assigning a bit indicating validity in said first stage when said first subset of instructions operating on a first piece of input data is processed to produce a first processed piece of input data; and v. propagating said bit in said first stage to said second stage when said second subset of instructions operating on said first processed piece of input data is processed.