Patent ID: 6965906

Claim:
For use in a processor having integer and floating point execution cores and logic circuitry, a method for converting negative floating point numbers to integer notation in said processor, said method comprising the steps of: receiving in a shifter of said processor a floating point number having a fraction portion and an exponent portion and a sign portion; shifting in said shifter the fraction portion based on the exponent portion to obtain a shifted fraction portion and rounding data; deriving in a rounding logic circuit coupled to said shifter a rounding indicator from the rounding data; generating in a one's complementer coupled to said shifter a one's complement of the shifted fraction portion; determining in a logic circuit that is coupled to said rounding logic circuit that said sign portion of said floating point number is one and that said rounding indicator is equal to said sign portion of said floating point number; and providing in a register of said processor the one's complement as an integer representation of the floating point number when said sign portion of said floating point number is one and when said rounding indicator is equal to said sign portion of said floating point number.