Patent ID: 7663402

Claim:
A high voltage stress test circuit comprising: an internal data generation unit for generating internal data and inverted internal data using a low supply voltage as a pull-up voltage; and a level shifter for receiving the internal data and the inverted internal data, and for generating digital data and inverted digital data in which a pull-up voltage is level-shifted to a high supply voltage, wherein in a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, in a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, in the normal mode, the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data, respectively, and in the high voltage stress test mode, the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.