Patent ID: 7370155

Claim:
A method of maintaining cache coherency in a multiprocessor data processing system (MP) having a plurality of processors and associated processor caches coupled together via a bifurcated system bus, said method comprising: snooping, at a first processor, a request from a second processor for access to a cache line, for which the first processor has current ownership but has not yet received data of the cache line; when said request is homogenous with a previous request issued by the first processor to obtain the current ownership of the cache line, issuing a response indicating that the ownership will be passed to the second processor once the data has been received at the first processor's cache; and contemporaneously setting an intermediate cache coherency state of the cache line within the first processor's cache to a first chained intermediate coherency state indicating that said first processor will forward the cache line data once the cache line data is received at said first processor's cache.