Patent ID: 8358780

Claim:
An execution unit adapted to perform a given round of the Data Encryption Standard, the execution unit comprising: a) a Left Half input; b) a Key input; c) a Table input; d) a Select input; e) a first group of transistors configured to receive the Table input, perform a table look-up, and output data; f) a first exclusive-or operator having two inputs and an output, the first exclusive-or operator configured to receive the Left Half input and the Key input; g) an inverter operator having an input and an output, the inverter operator receiving the Select input; h) a NAND operator, the NAND operator having two inputs and an output, the first of the two inputs of the NAND operator configured to receive the data output by the first group of transistors, the second of the two inputs of the NAND operator configured to receive the data output by the inverter operator; i) a exclusive-nor operator having two inputs and an output, the exclusive-nor operator configured to receive the output of the NAND operator and the output of the first exclusive-or operator; and j) a second exclusive-or operator having two inputs and an output, the second exclusive-or operator configured to receive the Left Half input and the output of the first group of transistors; k) wherein the output of the second exclusive-or operator is used as a Right Half input for a next round for the given round of the Data Encryption Standard.