Patent ID: 8288279

Claim:
A method for fabricating a conductive contact, comprising: providing a semiconductor substrate with a gate structure formed thereover and a pair of first conductive regions formed therein in a first region thereof, and a pair of second conductive regions and an isolation element formed therein, and a first dielectric layer and a second dielectric layer thereon in a second region thereof, wherein the pair of first conductive regions are formed in the semiconductor substrate from opposite sides of the gate structure and the isolation element isolates the pair of the second conductive regions from each other; conformably and sequentially forming a third dielectric layer and a fourth dielectric layer over the semiconductor substrate in the first region; forming a pattern mask layer with a first opening therein over the second dielectric layer in the second region, wherein the first opening is substantially located over the isolation element; performing an etching process to etch back the third and fourth dielectric layers in the first region and a portion of the first and second dielectric layers in the second region exposed by the first opening in the patterned mask layer, thereby forming a composite spacer on opposite sidewalls of the gate structure in the first region and a second opening in the first and second dielectric layers in the second region, wherein the second opening formed in the first and second dielectric layers exposes a portion of a top surface of the isolation element and portions of a top surface of the pair of second conductive regions; removing the patterned mask layer; performing an epitaxy process and forming a first conductive semiconductor layer over the pair of the first conductive regions and a second conductive semiconductor layer over the top surface of the isolation element and portions of the top surface of the pair of second conductive regions exposed by the second opening; blanketly forming a fifth dielectric layer over the semiconductor substrate in the first and second regions; forming a third opening in the fifth dielectric layer in the second region, exposing a top surface of the second conductive semiconductor layer; and forming a conductive layer in the third opening, overlying the second conductive semiconductor layer and filling the third opening.