Patent ID: 7774578

Claim:
A method comprising: receiving a first cache miss indicator in response to a first instruction accessing a first memory location, wherein the first memory location could not be found in a cache; in response to receiving the first cache miss indicator, storing first information at a first record, the first information comprising: information representing an address space location from which the first instruction was accessed; and a first indicator identifying a first block of memory that includes the first memory location; receiving a second cache miss indicator in response to a second instruction accessing a second memory location, wherein the second memory location could not be found in the cache; and in response to receiving the second cache miss indicator, storing second information at the first record, the second information comprising: a second indicator identifying a second block of memory that includes the second memory location but not the first memory location; wherein the relative position of the first indicator within the first record identifies the first block of memory and the relative position of the second indicator within the first record identifies the second block of memory.