Patent ID: 8572449

Claim:
A method for functional testing of an integrated circuit, the method comprising: determining, at a testing unit of the integrated circuit, to test an instruction cache (I-cache) memory associated with a processor of the integrated circuit; determining at the testing unit, a plurality of instructions to be executed by the processor for testing the I-cache memory associated with the processor; for each of the plurality of instructions to be executed by the processor for testing the I-cache memory associated with the processor, receiving, at the testing unit, a memory address associated with the instruction from the processor, wherein the memory address is generated by the processor in response to executing the instruction; determining, at the testing unit, an expected memory address associated with the instruction of the plurality of instructions associated with testing the I-cache memory, wherein the expected memory address indicates a memory location at which the next of the plurality of instructions is stored; determining whether the memory address generated by the processor matches the expected memory address associated with the instruction; providing, from the testing unit, an indication of a next of the plurality of instructions for execution by the processor in response to determining that the memory address generated by the processor matches the expected memory address associated with the instruction; and generating, at the testing unit, an error notification in response to determining that the memory address generated by the processor does not match the expected memory address associated with the instruction.