Patent ID: 7087462

Claim:
A method for forming leadless semiconductor packages comprising: providing a leadframe comprising a first metal layer formed on an upper surface of the leadframe and a plurality of units in an array arrangement, wherein each of the units comprises a die pad, a plurality of leads comprising a plurality of bond regions, and a plurality of outer dambars disposed in a periphery of each of the units; adhering a lower surface of a die to the first metal layer of the die pad, wherein a plurality of bond pads are disposed on an upper surface of the die; forming a plurality of conductive wires to electrically connect the bond pads with the corresponding bond regions of the leads; forming an encapsulation covering the die, the leads, and the leadframe, wherein the encapsulation exposes lower surfaces of the die pad, the leads, and the outer dambars; forming a patterned photoresist layer on a lower surface of the leadframe, wherein the patterned photoresist layer exposes a plurality of interval regions of the leads and the outer dambars; performing an etching process by utilizing the patterned photoresist layer as a mask to expose the first metal layer located in the interval regions and the outer dambars; removing the patterned photoresist layer; forming a second metal layer on the lower surfaces of the die pad, the leads, and the outer dambars after removing the patterned photoresist layer; cutting off the first metal layer located in the interval regions by utilizing a half cutting process to electrically isolate the bond regions; and performing a singulation process to singulate the units by cutting off the first metal layer and the encapsulation located in the outer dambars.