Patent ID: 7355239

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a plurality of isolation trenches in a substrate; filling the isolation trenches with a trench dielectric; forming a tunnel oxide layer on the substrate above active areas of the semiconductor device between the isolation trenches; forming a first polysilicon layer on the tunnel oxide layer to provide a plurality of floating gates; forming a gate dielectric layer on the floating gates above the active areas and on exposed portions of the trench dielectric; forming a second polysilicon layer on the gate dielectric layer; partially etching the second polysilicon layer above the isolation trenches, wherein at least a portion of the second polysilicon layer above the isolation trenches remains following the partial etching; and further etching the second polysilicon layer and the gate dielectric layer above the isolation trenches, wherein a remaining portion of the second polysilicon layer above the active areas provides a plurality of control gates.