Patent ID: 8429569

Claim:
A method, comprising: providing a present wafer to be processed by a photolithography tool to form a new integrated circuit design thereon; selecting a processed wafer out of a plurality of previously processed wafers, the processed wafer having a past integrated circuit design different than the new integrated circuit design, the selecting based upon the similarity of the past integrated circuit design to the new integrated circuit design; selecting a plurality of critical dimension (CD) data points extracted from the processed wafer after the processed wafer was etched, wherein the selecting the plurality of CD data points includes: selecting the plurality of CD data points from a plurality of fields on the processed wafer; and selecting a subset of the plurality of CD data points, the subset including CD data points extracted from a plurality of fields on the processed wafer, wherein the selecting the subset includes: grouping fields on the processed wafer into a plurality of groups; randomly selecting a primary field from each of the plurality of groups; and selecting a first number of CD data points from each of the primary fields and a second number of CD data points from each of the remaining fields on the wafer, the first number being greater than the second number; creating an initial exposure dose map for the new integrated circuit design using the plurality of CD data points; and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new integrated circuit design on the present wafer.