Patent ID: 7940202

Claim:
An apparatus, comprising: a chip having an analog domain and a digital domain; a clock generation component configured to receive a master clock and generate a plurality of clock signals that are shifted relative to one another; a first selection component coupled to the clock generation component, the first selection component configured to select a first one of the generated clock signals and drive the digital domain according to the first clock signal; a second selection component coupled to the clock generation component, the second selection component configured to select a second one of the generated clock signals that is shifted relative to the first clock signal and configured to drive an analog component of the analog domain; and an inverter coupled with the analog component, the inverter configured to invert the second clock signal to generate an inverted clock signal to feed to the analog component, wherein a delay between operating edges of the inverted clock signal and the first clock signal is greater than a delay between operating edges of the selected clock signals.