Patent ID: 7333116

Claim:
A graphics display device comprising: a CPU, the CPU generating drawing procedure information including graphic diagrams to be displayed and top (apex) parameters thereof; a graphics memory, the graphics memory storing the drawing procedure information generated by the CPU and drawing data to be output to a display unit; and a graphics processor which performs drawing access for the drawing procedure information, stores the drawing data in the graphics memory and further reads out the drawing data for outputting the same to the display unit, the graphics memory permitting access from both the CPU and the graphics processor, wherein when the CPU writes the data in the graphics memory, the CPU causes to temporarily store an address and the data to be written in a FIFO within the graphics processor, and when under the condition that the data is stored in the FIFO and no new data are written from the CPU to the FIFO for a predetermined period, the graphics processor writes the data stored in the FIFO into the graphics memory according to the address, wherein the graphics processor varies data storing timing in the graphics memory according to a cache system of a cache memory, said cache system being provided in the CPU and transferring data to the graphics memory, and wherein the graphics processor further comprises: a CPU interface; a counter; a match detector; and a flip-flop, wherein when the CPU performs a store operation to the graphics memory, a write request signal is sent from the CPU interface, the counter is incremented, and a write address and data of the CPU are stored in the FIFO, wherein the match detector compares a value of the counter with a capacity of the FIFO, and wherein the flip-flop is set if it is determined that the FIFO is full as a result of the comparison, such that the CPU interface is notified that the FIFO is busy and the CPU is prevented from storing any more data.