Patent ID: 7630275

Claim:
A latency counter that counts latencies of an internal command synchronously with an internal clock, the latency counter comprising: a point-shift type FIFO circuit having a plurality of latch circuits connected in parallel, each latch circuit including an input gate and an output gate, and the internal command being supplied in common to the input gates; and a selector that selects any one of the input gates and selects any one of the output gates, the selector including, a counter that changes a selection operation of selecting the input and output gates and that outputs a count value in a binary format synchronously with the internal clock, a decoder that decodes the count value in the binary format, and assigns one of the input gate and the output gate to be selected, based on the output value of the decoder, and a synchronizing circuit that supplies the output of the decoder to the point-shift type FIFO circuit synchronously with a first delay clock obtained by delaying the internal clock, wherein a delay amount of the first delay clock from the internal clock corresponds to the sum of a delay time of the counter and a delay time of the decoder.