Patent ID: 7500042

Claim:
An access control device for a bus bridge circuit connected between a first bus and a second bus connected to peripheral devices, all on a single chip, comprising: a status controller for determining a state of access to the first and second buses; a number-of-waits setting circuit for setting a wait periodicity corresponding to an operating speed of each of the peripheral devices connected to the second bus according to an address corresponding to an access request to the second bus sent from the first bus, in response to the access request, the first bus entering a standby state over a duration equivalent to the wait periodicity; a count value generator for generating a present count value up to the wait periodicity set by the number-of-waits setting circuit; a control signal holding circuit for holding a control signal for holding a state of the second bus at the selling of the wait periodicity by the number-of-waits setting circuit during a count period of the count value generator and maintaining an access state of the status controller; and a clock control circuit for dividing a clock for the first bus responsive to the wait periodicity set by the number-of-waits setting circuit and the present count value, and outputting a result of the division to the second bus.