Patent ID: 7166896

Claim:
An integrated circuit comprising: a plurality of bit lines and a plurality of word lines; and a plurality of memory cells connected to the bit lines and the word lines, each of the memory cells including: a first inverter connected to a second ionverter at a srorage node and a second storge node, each of the first and second inverters including; a first transistor connected to a second transistor, the first and second transistor including a shared gate structure, the shared gate structure including: a polysilicon layer including a first gate portion of first conductivity type, and a second gate portion of second conductivity type, wherein a source of the first transistor and drain of the second transistor are located on a first side of the polysilicon layer, wherein a drain of the first transistor and a source of the second transistor are located on a second side of the polysilicon layer, and wherein the polysilicon layer includes a segment located between the source of the first transistor and the drain of the second transistor for coupling to one of a source and a drain of a third transistor; an electrode layer; and a cross diffusion barrier layer sandwiched between the electrode layer and the polysilicon layer, the cross diffusion barrier layer is being formed to below a top surface of the polysilicon layer, wherein the cross diffusion barrier layer is formed to prevent cross diffusion between the first gate portion and the second gate portion, and wherein the cross diffusion barrier layer has a thickness of about one percent of a thickness of the gate layer; and a pair of access devices controlled by one of the word lines and connected to the first and second storage nodes and to a pair of bit lines among the plurality of bit lines.