Patent ID: 8042070

Claim:
A method of designing and manufacturing a set of physical masks for a semiconductor chip comprising: providing one or more of a program or a compact model either or both of which including a threshold voltage adder calculation means; determining, employing said threshold voltage adder calculation means, a calculated threshold voltage adder for a device within a subset of a semiconductor chip design including an effect of at least one design parameter of said subset other than inherent geometric dimensions and inherent characteristics of said device; estimating a parametric yield estimation value of said subset of said semiconductor chip design, wherein said parametric yield estimation value is based on said calculated threshold voltage adder; iteratively modifying, if said parametric yield estimation value does not exceed a predetermined target for said parametric yield estimation value, said semiconductor design and estimating said parametric yield estimation value until a most recent parametric yield estimation value exceeds a predetermined target for said parametric yield estimation value; and manufacturing, employing data representing said semiconductor chip design as most recently provided or modified, a set of physical masks for said semiconductor chip design, wherein said determining of said calculated threshold voltage adder is effected by performing at least one step of: calculating an incremental on-current deviation for said subset of said semiconductor chip design, wherein said incremental on-current deviation is an increment in statistical deviation of on-current of said subset of said semiconductor chip deign from a scaling-estimated statistical deviation of on-current, which is obtained by scaling of statistical deviation of on-current of at least one nominal device, due to said design parameters of said subset other than inherent geometric dimensions and inherent characteristics of devices in said subset; and calculating an incremental off-current deviation for said subset of said semiconductor chip design, wherein said incremental off-current deviation is an increment in statistical deviation of off-current of said subset of said semiconductor chip deign from a scaling-estimated statistical deviation of off-current, which is obtained by scaling of statistical deviation of off-current of at least one nominal device, due to said design parameters of said subset other than inherent geometric dimensions and inherent characteristics of devices in said subset.