Patent ID: 7609111

Claim:
A negative capacitance circuit, comprising: a first transistor (Qn 1 , Qp 1 , Mn 3 or Mp 3 ) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the first transistor connected to a first voltage rail (Vsp or Vsm); a second transistor (Qn 2 , Qp 2 , Mn 4 or Mp 4 ) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the second transistor connected to the control terminal (base or gate) of the first transistor, and the control terminal (base or gate) of the second transistor receiving a bias voltage; a first bias current source (Ibias) connected between the second current path terminal (emitter or source) of the first transistor and a second voltage rail (Vsm or Vsp); a second bias current source (Ibias) connected between the second current path terminal (emitter or source) of the second transistor and the second voltage rail (Vsm or Vsp); a capacitor (C 1 ) connected between the second current path terminal (emitter or source) of the first transistor and the second current path terminal (emitter or source) of the second transistor; and a resistor (R c ) including a first resistor terminal and second resistor terminal, the first resistor terminal connected to the control terminal (base or gate) of the first transistor and to the first current path terminal (collector or drain) of the second transistor, and the second resistor terminal forming the input node of the negative capacitance circuit.