Patent ID: 7426146

Claim:
A reference voltage generating circuit for producing a predetermined reference voltage at an output node, comprising: a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage; a second field-effect transistor having one node thereof coupled to another node of the first field-effect transistor and having a highly-doped n-type gate; and a third field-effect transistor having one node thereof coupled to another node of the second field-effect transistor, another node thereof coupled to a ground voltage, and a highly-doped p-type gate, wherein a gate of the first field-effect transistor is coupled to a joint point between the first field-effect transistor and the second field-effect transistor, substrate gates of the first and third field-effect transistors coupled to the ground voltage, and the gate and substrate gate of the second field-effect transistor and the gate of the third field-effect transistor coupled to a joint point serving as the output node between the second field-effect transistor and the third field-effect transistor, and wherein each of the second and third field-effect transistors is configured to have such a ratio of a channel width to a channel length that a characteristic indicating a relationship between a gate-source voltage and a drain current exhibit a positive temperature dependency for both of the second and third field-effect transistors or a negative temperature dependency for both of the second and third field-effect transistors.