Patent ID: 7646642

Claim:
A semiconductor device comprising: a nonvolatile memory including: a memory array having a plurality of 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on a difference of the binary data held by themselves, a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit, wherein the control circuit performs: initialization control including a step of making uniform threshold voltages of the first and second storage devices of the twin cells into an initialization level in initialization units, and write control including a step of changing the threshold voltage of one of the first and second storage devices of the twin cell selected for write from the initialization level, and a step of writing the complementary data into the twin cell, and wherein the control circuit responds to an initialize command supplied from outside of the nonvolatile memory, and performs the initialization control on the initialization unit specified by an initialization address, wherein the control circuit responds to a write command supplied from the outside to the nonvolatile memory, and performs the write control including a step of writing the complementary data specified by write data into the twin cell specified by a write address, and wherein the control circuit responds to an initialization check command supplied from the outside of the nonvolatile memory, and performs check control including a step of sending back as a reply a result of judgment about whether or not the twin cell of the initialization unit specified by a check address is in an initialization state.