Patent ID: 7245532

Claim:
A semiconductor device comprising: a flash memory including a plurality of memory cells, each of the plurality of memory cells having a floating gate and a control gate; and a processing unit reading out a write data which has a plurality of bits from a Static Random Access Memory (SRAM), and transferring write information according to the write data to the flash memory, wherein each of the plurality of memory cells stores the plurality of bits of the write data by setting to a first state by taking electric charges into or out from the floating gate in a first write operation or a second state by taking electric charges into or out from the floating gate in a second write operation, wherein in the first and second write operations, each of the plurality of memory cells is supplied a plurality of write pulses according to the write information from the processing unit, and wherein a pulse height of a last write pulse of the plurality of write pulses is larger than a pulse height of a first write pulse of the plurality of write pulses.