Patent ID: 7940580

Claim:
A device, comprising: a first word-line coupled to a first bit cell; a second word-line coupled to a second bit cell; a first driver module comprising an input to receive a first select signal and an output coupled to the first word-line; a second driver module comprising an input to receive a second select signal and an output coupled to the second word-line; and a first level shifter comprising: a first input to receive a clock signal; a first terminal coupled to the first driver module and the second driver module; the first level shifter configured to: shift the first select signal so that the first driver module provides a first level-shifted signal at the first word-line in response to assertion of the first select signal, the first level shifter to shift the first select signal in response to assertion of the clock signal; and shift the second select signal so that the second driver module provides a second level-shifted signal at the second word-line in response to assertion of the second select signal.