Patent ID: 8228923

Claim:
A network device, comprising: a global time counter coupled to an ingress circuit of the network device and configured to generate an arrival time stamp in accordance with arrival time of a packet; an egress circuit coupled to the ingress circuit and capable of forwarding the packet to other network devices via an output port, wherein the egress circuit obtains a departure time stamp from the global time counter in accordance with departing time of the packet; a clock circuitry arranged in a hierarchical stratum clock tree having at least a first (1) stratum level of reference clock signals and a second (2) stratum level of reference clock signals, wherein the first (1) stratum level is logically higher level than the second (2) stratum level, wherein the global time counter is updated by a reference clock in accordance with the first (1) stratum level of the reference clock signals; and a processor coupled to the egress circuit and configured to calculate a packet latency of the network device in response to the arrival time stamp and the departure time stamp.