Patent ID: 7646244

Claim:
A circuit for buffering, comprising: a unity gain buffer having at least an input and an output, wherein the unity gain buffer includes: a first translinear loop that is coupled between the input of the unity gain buffer and the output of the unity gain buffer, wherein the first translinear loop includes a first translinear element and a second translinear element; a second translinear loop that is coupled between the input of the unity gain buffer and the output of the unity gain buffer, wherein the second translinear loop includes a third translinear element and a fourth translinear element; a first bias current source that is arranged to provide a first bias current to the first translinear loop, wherein the first bias current source is arranged to provide the first bias current such that, if an input voltage at the input of the unity gain buffer is greater than zero, the first bias current includes a component that is proportional to the input voltage; and a second bias current source that is arranged to provide a second bias current to the second translinear loop, wherein the second bias current source is arranged to provide the second bias current such that, if the input voltage is less than zero, the second bias current includes a component that is proportional to a magnitude of the input voltage.