Patent ID: 8214602

Claim:
A processor comprising: a data cache; and a load/store unit (LSU) coupled to the data cache, and the LSU comprises a queue, and each entry in the queue is assigned to a different load that, if the entry is marked valid, has accessed the data cache but has not retired, and the LSU further comprises a control unit coupled to the queue, and the control unit is configured to update a data cache hit status of each load represented in the queue as a content of the data cache changes in response to snoop operations and other operations, and the LSU is coupled to receive a snoop index corresponding to a snoop operation received by the processor, and the control unit is configured to detect a snoop hit on a first load in a first entry of the queue responsive to: the snoop index matching a load index stored in the first entry, the data cache hit status of the first load indicating hit, the data cache detecting a snoop hit for the snoop operation, and a load way stored in the first entry matching a first way of the data cache in which the snoop operation is a hit; and the load way is a way of the data cache in which the load hits, and wherein the control unit is configured to update the data cache hit status of the first load to indicate not hit responsive to an invalidation of a cache line that is hit by the first load in the data cache.