Patent ID: 8018241

Claim:
An integrated circuit comprising: A. a semiconductor substrate; B. functional circuits formed on the substrate; C. a first bond pad formed on the substrate to input serial test input data; D. plural scan path circuits formed on the substrate, each of the scan path circuits having a serial input to receive test data, and parallel outputs coupled to the functional circuits; and E. logic circuitry formed on the substrate, the logic circuitry having a first serial input coupled to the first bond pad to receive serial test input data from the first bond pad and plural parallel outputs, each of the parallel outputs being coupled to the serial input of a scan path circuit, the logic circuitry adapted to load a multi-bit test stimulus data pattern into each of the plural scan paths in parallel by repeatedly both receiving serial test input data from the first bond pad on the first serial input and applying a set of data bits to the serial inputs of the plural scan path circuits in parallel, the logic circuitry adapted to receive serial test input data from the first bond pad at the first serial input including data bits presented in a pattern made up of a series of ordered bits, the logic circuitry further adapted to apply a first bit of a first one of the sets of data bits to a first scan path, where the first bit is derived from a bit at a first bit position in the series of ordered bits, and to apply a second bit also of the first set of data bits to a second data path different from the first data path, where the second data bit is derived from a bit at a different bit position in the series of ordered data bits than the first bit position.