Patent ID: 8051253

Claim:
A main memory comprising: a programmable heterogeneous memory controller having a first memory channel interface to couple to a first memory channel; the first memory channel coupled to the programmable heterogeneous memory controller, the first memory channel having a first memory channel bus coupled to the first memory channel interface of the programmable heterogeneous memory controller, and a plurality of sockets coupled to the first memory channel bus, the plurality of sockets capable of respectively receiving a plurality of memory modules; and wherein the programmable heterogeneous memory controller just prior to accessing a first memory module adapts the first memory channel interface on the fly to communicate with the first memory module with a first type of memory, just prior to accessing a second memory module adapts the first memory channel interface on the fly to communicate with the second memory module with a second type of memory differing from the first type of memory, and just prior to accessing a third memory module adapts the first memory channel interface on the fly to communicate with the third memory module with a third type of memory differing from the second type of memory.