Patent ID: 8843687

Claim:
A semiconductor device comprising: a first bus circuit that includes: a first outbound system bus and a second outbound system bus, the first outbound system bus and the second outbound system bus each having one end connected to a first outbound input terminal, a first outbound path switching section that connects another end of either the first outbound system bus or the second outbound system bus to a first outbound output terminal, a first inbound system bus and a second inbound system bus, the first inbound system bus and the second inbound system bus each having one end connected to a first inbound input terminal, and a first inbound path switching section that connects another end of either the first inbound system bus or the second inbound system bus to a first inbound output terminal; a second bus circuit that includes: a third outbound system bus and a fourth outbound system bus, the third outbound system bus and the fourth outbound system bus each having one end connected to a second outbound input terminal, a second outbound path switching section that connects another end of either the third outbound system bus or the fourth outbound system bus to a second outbound output terminal, a third inbound system bus and a fourth inbound system bus, the third inbound system bus and the fourth inbound system bus each having one end connected to a second inbound input terminal, and a second inbound path switching section that connects another end of either the third inbound system bus or the fourth inbound system bus to a second inbound output terminal; a storing section that stores, as a first setting state, a connecting state of the first outbound system bus or the second outbound system bus, and a connecting state of the first inbound system bus or the second inbound system bus, the storing section storing, as a second setting state, a connecting state of the third outbound system bus or the fourth outbound system bus, and a connecting state of the third inbound system bus or the fourth inbound system bus; and a control section that controls, based on the first setting state, the first outbound path switching section and the first inbound path switching section, the control section controlling, based on the second setting state, the second outbound path switching section and the second inbound path switching section.