Patent ID: 7623126

Claim:
A computer comprising: a processor having core logic, primary and secondary memory, and at least one system bus, at least one display coupled to the processor for displaying graphics and text output, and a display controller coupled to the processor and the display for receiving graphics display data at a first resolution, and controlling asynchronous output of graphics display data in at least one second resolution using a discrete cosine transform interpolation in conjunction with a polyphase interpolator; wherein a flat panel display and a CRT display are included; wherein the CRT display comprises a fixed resolution CRT display; wherein the flat panel display is a fixed resolution LCD panel and the CRT display is a fixed resolution projection display and the resolution of the fixed resolution projection display is lower than the resolution of the fixed resolution LCD panel; wherein the first resolution is associated with the fixed resolution projection display, the at least one second resolution is associated with the fixed resolution LCD panel, and duplicate lines are generated for the fixed resolution LCD panel before an end of a line timing interval associated with the fixed resolution projection display.