Patent ID: 8329529

Claim:
A method for fabricating an integrated circuit device, the method comprising: providing a semiconductor substrate, the substrate comprising a first region and a second region; forming a device layer overlying the first region of the semiconductor substrate; forming an inter-metal layer dielectric overlying the device layer; forming a stop layer overlying the inter-metal layer dielectric in the first region and the second region; forming a low k dielectric layer overlying the stop layer in the first region and the second region; forming a cap layer overlying the low k dielectric layer; initiating formation of a plurality of via structures within a first portion of the low k dielectric layer overlying the first region and simultaneously initiating formation of an isolated via structure for a test structure in the second region of the semiconductor substrate, using an etching process; and ceasing formation of the plurality of via structures within the first portion and ceasing formation of the isolated via structure in the second region when a portion of the stop layer has been exposed; wherein the first region is a cell region and the second region is a peripheral region.