Patent ID: 7122906

Claim:
A die-wafer package comprising: a first semiconductor die having an active surface; a second semiconductor die having a first side, having a second opposing side and including a first plurality of bond pads disposed on the first side and a second plurality of bond pads disposed on the second side, at least a portion of at least some bond pads of the first plurality of bond pads including an under-bump metallization layer disposed on and contiguous therewith, and at least a portion of at least some bond pads of the second plurality of bond pads including an under-bump metallization layer disposed on and contiguous therewith; a first plurality of conductive bumps disposed between the first semiconductor die and the second semiconductor die and facilitating electrical communication between at least a first set of bond pads disposed on the active surface of the first semiconductor die and at least some of the first plurality of bond pads of the second semiconductor die; a second plurality of conductive bumps electrically coupled to at least a second set of bond pads disposed on the active surface of the first semiconductor die; a third plurality of conductive bumps electrically coupled to the second plurality of bond pads of the second semiconductor die; and at least one passivation layer disposed over at least the second surface of the second semiconductor die and at least a portion of the first semiconductor die; wherein an upper end of at least some of the second plurality of conductive bumps and an upper end of at least some of the third plurality of conductive bumps are exposed through the at least one passivation layer.