Patent ID: 8350336

Claim:
A semiconductor device comprising: a semiconductor substrate having defined thereon a first area and a second area; a first active pattern comprising first single-crystalline semiconductor material grown from a surface of the first area of the substrate; a first device isolation pattern comprising first insulation material and defining the first active pattern, to thereby electrically insulate neighboring elements of the first active pattern from each other; a second active pattern comprising second single-crystalline semiconductor material grown from a surface of the second area of the substrate; a second device isolation pattern comprising second insulation material and defining the second active pattern, to thereby electrically insulate neighboring elements of the second active pattern from each other, a side profile of the second device isolation pattern having an inclination that is opposite that of a side profile of the first device isolation pattern; first and second lower conductive structures on the first and second active patterns, respectively, the first lower conductive structure including a first lower gate insulation layer on a surface of the first active pattern and a first lower gate conductive layer on the first lower gate insulation layer, and the second lower conductive structure including a second lower gate insulation layer on a surface of the second active pattern and a second lower gate conductive layer on the second lower gate insulation layer; an insulation interlayer covering the first lower conductive structure and having a supplementary opening through which the first active pattern is partially exposed, an upper surface of the insulation interlayer being planarized; a plug layer comprising a third single-crystalline semiconductor material and filling the supplementary opening; an upper active layer on the insulation interlayer, the upper active layer comprising a fourth single-crystalline semiconductor material and making contact with the plug layer; and an upper conductive structure on the upper active layer, the upper conductive structure including an upper gate insulation layer on the upper active layer and an upper gate conductive layer on the upper gate insulation layer.