Patent ID: 7358562

Claim:
A vertical NROM flash memory array comprising a substrate having a lower source/drain region; an oxide pillar extending outward from the substrate above the lower source/drain region; a plurality of ultra-thin silicon body regions, each comprising epitaxial regrowth of silicon along opposite sidewalls of the oxide pillar, each body region extending vertically from each side of the lower source/drain region; an upper source/drain region formed on the oxide pillar, each side of the upper source/drain region coupled to a different body region; an insulator layer formed around either side of the lower source/drain region, the plurality of body regions, and the upper source/drain region, portions of the insulator layer on each side of the lower source/drain region having a greater thickness than the remaining insulator layer such that the lower source/drain region is isolated between the thicker insulator layer portions; and a control gate formed over the insulator layer.