Patent ID: 8243083

Claim:
A method, comprising: identifying a fixed-length sequence of elements utilizing a parallel processor architecture including a plurality of processors, each of the plurality of processors being capable of physically executing a predetermined number of threads in parallel, where the fixed-length corresponds with the predetermined number of threads, each element in the fixed-length sequence of elements corresponding to a unique index value reflecting a position of the corresponding element within the fixed-length sequence; generating a first array of head flags based on the fixed-length sequence of elements, each element of the first array of head flags comprising one of a first value or a second value, and each element of the first array of head flags corresponding to an element in the fixed-length sequence of elements and the unique index value reflecting a position of the corresponding element within the fixed-length sequence of elements; generating a second array header index based on the first array of head flags and the unique index values, wherein each element of the second array header index is: set to the first value if a corresponding element in the first array of head flags comprises the first value, and set to a value of a unique index value reflecting a position of the corresponding element in the first array of head flags if the corresponding element in the first array of head flags comprises the second value; generating a third array limit index by scanning the second array header index and applying a max operator, wherein the third array limit index comprises a plurality of elements and each element in the third array limit index corresponds to an element in the fixed-length sequence of elements and a corresponding element of the second array header index; and performing a segmented scan operation on the fixed-length sequence of elements utilizing the parallel processor architecture and the third array limit index to produce an output.