Patent ID: 8219948

Claim:
A layout verification device that includes a layout verification unit, the layout verification unit verifying consistency of a first layout pattern where vertices are arranged along with grid intersections and a design rule and outputting a first error graphic corresponding to a position judged as inconsistent, the layout verification device comprising: a target error graphic setting unit that specifies a location of the first error graphic in the first layout pattern, and sets a processing target area including the first error graphic; an error graphic search unit that searches a second error graphic located in an area corresponding to a processing target area of a second layout pattern where a verification of consistency by the layout verification unit has already been performed; and an error graphic equivalence judgment unit that compares a plurality of vertex coordinates of the first error graphic with a plurality of vertex coordinates of the second error graphic to verify equivalence of the second error graphic and the first error graphic, wherein the error graphic equivalence judgment unit sets vertices having different coordinates between the first error graphic and the second error graphic as a first target vertex coordinate and a second target vertex coordinate, respectively, and judges that the first error graphic and the second error graphic are non-equivalent when the second target vertex coordinate does not match any one of a plurality of peripheral vertex coordinates set in grid intersections that are adjacent to the first target vertex coordinate.