Patent ID: 7249226

Claim:
A semiconductor system comprising: a shared memory; first to n-th processing units each of which designates a memory size to use and an address to access; and first to n-th address circuits corresponding to the first to n-th processing units; wherein the first address circuit provides a value obtained by adding a memory size designated by the first processing unit to a base address given in advance for the second address circuit as a base address of the second processing circuit, the k-th (k=2 to n−1) address circuit provides a value obtained by adding a memory size designated by the k-th processing unit to a base address provided from the (k−1)-th address circuit for the (k+1)-th address circuit as a base address of the (k+1)-th processing circuit, the first address circuit generates a memory address to access in the shared memory by adding the base address given in advance to an address designated by the first processing unit, and the second to n-th address circuits generate a memory address to access in the shared memory by adding the base address provided from the first to (n−1)-th address circuits to an address designated by the second to n-th processing units.