Patent ID: 7770077

Claim:
A memory system comprising: a memory hub device integrated in a memory module; a memory device data interface integrated in the memory hub device that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device; a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed; a link interface, coupled to the memory device data interface and the memory hub controller, that provides a communication path between the memory module and an external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface; a first multiplexer coupled to the link interface and a second multiplexer in the memory device data interface; and a read data queue coupled to the first multiplexer and the second multiplexer in the memory device data interface, wherein the memory hub controller controls the transfer of data between the second multiplexer and the link interface by sending one or more control signals to the first multiplexer to select either a direct input from the second multiplexer or an input from the read data queue for output by the first multiplexer to the link interface.