Patent ID: 8592303

Claim:
A method for manufacturing a multi-layered wiring in which a plurality of unit wiring structures are laminated, the unit wiring structure having a wiring and a connection plug formed by filling metal including Cu as a main component into a wiring trench and a via hole formed in an insulation film on a substrate forming a semiconductor element, the method comprising: forming a first insulation film directly contacting on the copper wiring or the copper connection plug and a porous insulation film laid on the first insulation film, forming a second insulation film laid on the porous insulation film, forming a wiring trench or a via hole in the second insulation film and the porous insulation film, such that a bottom of the wiring trench or the via hole is comprised entirely of an upper surface of the first insulation film, forming an insulation barrier layer including organic substance at upper surface, side surface and bottom surface of a wiring structure sectioned by the wiring trench or the via hole, etching back the insulation barrier layer including organic substance and removing the insulation barrier layer including organic substance remaining on the upper surface and bottom surface portions of the wiring structure, and embedding a metal film in the wiring structure trench or the via hole, wherein the insulation barrier layer includes silicon atoms with a silicon content of less than 3 atm %, and wherein the silicon content of the insulation barrier layer is smaller than a silicon content of the first insulation film and a silicon content of the second insulation film.