Patent ID: 7683419

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; a memory cell of a random access memory (DRAM) arranged at a first region on the main surface and including a first MISFET and a first capacitor element such that the first capacitor element is electrically connected to a source-drain path of the first MISFET, wherein the first MISFET includes a source region and a drain region each formed in the semiconductor substrate, a gate electrode, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode; a logic circuit arranged at a second region of the main surface including a second MISFET, wherein the second MISFET includes a source region and a drain region each formed in the semiconductor substrate, a gate electrode, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode; a first insulating film formed over the first MISFET and the second MISFET, a lower electrode of the first capacitor element formed on the first insulating, a dielectric insulating film of the first capacitor element formed on the lower electrode of the first capacitor element, a higher electrode of the first capacitor element formed on the dielectric insulating file of the first capacitor element; a second insulating film formed over the first capacitor element and the first insulating film; and a second capacitor element formed over the second insulating film, a lower electrode of the second capacitor element formed on the same level layer a wiring layer, a dielectric insulating film of the second capacitor element formed on the lower electrode of the second capacitor element, a higher electrode of the second capacitor element formed on the dielectric insulating film of the second capacitor element, and a third insulating film formed over the second capacitor element and the second insulating film, wherein the third insulating film having a via hole for connecting the wiring layer.