Patent ID: 6970389

Claim:
An integrated memory, comprising: a memory cell array, the memory cell array including a plurality of word lines for the selection of memory cells and a plurality of bit lines for reading out or writing data signals of the memory cells, the bit lines being organized in bit line pairs, the bit lines of a bit line pair crossing one another at a crossing location, the bit lines running parallel to one another; a sense amplifier, the sense amplifier being connected to one of the bit line pairs at one end of the bit line pair; and at least one activatable isolation circuit, the isolation circuit being switched into one of the bit line pairs, wherein the activated state during an access to the memory cell array, the isolation circuit isolating a part of one of the bit line pairs which is more remote from the sense amplifier, from the sense amplifier circuit being arranged at a first distance from the crossing location and at a second distance from the sense amplifier, the first distance being less than the second distance.