Patent ID: 7676697

Claim:
A data recording apparatus comprising: a target integrated circuit including a source of digital data, a clock input for receiving an external clock signal, said clock input having a clock insertion delay, and a data output device having a first input receiving data from said source of digital data and a clock signal subject to said clock insertion delay from said clock input and a first output outputting said digital data in synchronism with said clock subject to said clock insertion delay; a trace integrated circuit including a source of clock signals having a second output connected to said clock input of said target integrated circuit, a first programmable delay device having a first programmable delay, a second input connected to said first output of said data output device and a third output, a second programmable delay device having a second programmable delay, a third input connected to said second output of said source of clock signals and a fourth output, and a digital processing element having a data input connected to said third output of said first programmable delay device, a clock input connected to said fourth output of said second programmable delay device and a fifth output, said digital processing element operable to sample data at said data input at a selected one of the positive or negative transition of a signal at said clock input; wherein said first programmable delay and said second programmable delay are dynamically adjusted to compensate for said clock insertion delay.