Patent ID: 8023610

Claim:
A shift register comprising: an input terminal, an output terminal, a first clock terminal and a reset terminal; a first transistor to supply a first clock signal received at said first clock terminal to said output terminal; a second transistor to discharge said output terminal in accordance with a discharging signal; a charging circuit to charge a first node to which a control electrode of said first transistor is connected, in accordance with an input signal received at said input terminal; and a discharging circuit to discharge said first node in accordance with a reset signal received at said reset terminal, wherein said charging circuit includes a plurality of third transistors, connected in series between said first node and a power terminal, with control electrodes connected in common to said input terminal, and said discharging circuit includes a fourth transistor having a control electrode connected to said reset terminal, the fourth transistor being connected to said first node and discharging the first node, said charging circuit turns on said plurality of third transistors when said input signal reaches a voltage level (H) higher than a threshold voltage of said plurality of third transistors, to thereby charge said first node, and then pulls down each connection node between said plurality of third transistors to a voltage level (L) lower than said threshold voltage when the input signal changes to the L level, and a width of an electrode being a connection point between any one of the plurality of third transistors and another one of the plurality of third transistors is greater than a width of an electrode being a connection point between one of the plurality of third transistors and the fourth transistor.