Patent ID: 7906404

Claim:
A method for fabricating a semiconductor device with an in-substrate capacitor coupled to an active circuit layer and a power plane, the substrate having a first surface and a second surface, the method comprising: forming an active circuit layer adjacent the first surface of the substrate; etching a first cavity through the active circuit layer and the first surface of the substrate to a first depth, the first cavity having a first perimeter; etching a second cavity through the second surface of the substrate to a second depth, the second cavity having a second perimeter, the first and second cavities forming a via hole through the substrate; depositing a first conductive material layer in the via hole such that the first conductive material layer is electrically continuous across a length of the via hole; depositing a first isolation material layer over the first conductive material layer, the isolation material layer being electrically insulating, continuous and substantially conformal; depositing a second conductive material layer over the isolation material layer such that the second conductive material layer is electrically continuous across the length of the via hole, the first and second conductive material layers and the first isolation material layer forming the in-substrate capacitor; forming a power plane adjacent the second surface of the substrate; and electrically coupling the active circuit layer and the power plane to the in-substrate capacitor to provide power conditioning and distribution to the active circuit layer.