Patent ID: 7461180

Claim:
An apparatus for synchronizing use of buffer descriptors for shared packet data in memory, comprising: a network interface that is coupled to a network for communicating therewith a data packet; one or more processors; one or more memory devices comprising computer-readable media for storing packet data for the data packet in one or more memory buffers of a plurality of allocated memory buffers for storing data from a plurality of data packets, and a plurality of buffer descriptors corresponding to the plurality of allocated memory buffers; and a data communication channel connected to the network interface, the one or more processors and the one or more memory devices, wherein: each buffer descriptor holds data that includes location data that indicates a location of a corresponding memory buffer and owner data that indicates which of the network interface and the one or more processors has current exclusive use of the corresponding memory buffer; the network interface includes a direct memory access (DMA) controller for exchanging data between the network interface and the one or more memory devices; the DMA controller includes a queue of memory exchange commands to be sent over the data communication channel to the one or more memory devices, a private index register that holds data that indicates an index to a first buffer descriptor most recently used in the queue, and a different public index register that holds data that indicates an index to a second buffer descriptor; the DMA controller is configured to send data that includes data from the public index register in response to a request, from the one or more processors, for a buffer descriptor most recently used; and when the second buffer descriptor is accessed by the one or more processors after receiving the data from the public index register, the contents of the second buffer descriptor are guaranteed to include owner data that indicates the one or more processors.