Patent ID: 7256626

Claim:
A pre-emphasis circuit suitable for a low-voltage differential signal (LVDS) driver with a current input end and a current output end, the pre-emphasis circuit comprising: a first PMOS transistor, wherein the first source/drain end thereof is coupled to a voltage supply through a first resistor and the gate end thereof receives a first driving signal with a preset time delay; a second PMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first PMOS transistor, the gate end thereof receives a second driving signal, and the second source/drain end is coupled to said current input end; a third PMOS transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first PMOS transistor and the gate end thereof receives said second driving signal with said preset time delay; a fourth PMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third PMOS transistor, the gate end thereof receives said first driving signal, and the second source/drain end thereof is coupled to the second source/drain end of said second PMOS transistor; a first NMOS transistor, wherein the first source/drain end thereof is coupled to said current output end and the gate end receives a third driving signal; a second NMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first NMOS transistor, the gate end thereof receives a fourth driving signal with said preset time delay, and the second source/drain end thereof is grounded through a second resistor; a third NMOS transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first NMOS transistor and the gate end thereof receives said fourth driving signal; and a fourth NMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third NMOS transistor, the gate end thereof is coupled to said third driving signal with said preset time delay, and the second source/drain end thereof is coupled to the second source/drain end of said second NMOS transistor.