Patent ID: 8399992

Claim:
A semiconductor package comprising: a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate, a redistribution, and a molding layer molding the lower semiconductor chip; an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, the upper package being stacked on the lower package; an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper package and the lower package to each other; and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper package and the lower package to each other, wherein the dummy interconnector comprises at least one of a first dummy interconnector extending toward the lower semiconductor chip; and a second dummy interconnector disposed further adjacent to an edge portion of the upper substrate when compared to the first dummy interconnector to extend toward the lower substrate in an outer region of the lower semiconductor chip, wherein the redistribution comprises: a first redistribution connected to the electrical interconnector and electrically connected to the lower substrate; and a second redistribution connected to the first dummy interconnector and not electrically connected to the lower substrate, and wherein the molding layer comprises at least one of a mold via hole exposing the first redistribution to provide a disposition space for the electrical interconnector, a first dummy mold via hole exposing the second redistribution to provide a disposition space for the first dummy interconnector, and a second dummy mold via hole providing a disposition space of the second dummy interconnector, wherein the first dummy mold via hole has an empty space which is not filled with the first dummy interconnector.