Patent ID: 8269268

Claim:
A charge trap flash memory device comprising: a tunnel insulating layer formed on a semiconductor substrate; a charge trap layer formed on the tunnel insulating layer; a blocking insulating layer formed on the charge trap layer; and a gate electrode formed on the blocking insulating layer, wherein the charge trap layer comprises: a plurality of trap layers comprising a first material having a first band gap energy level; a plurality of nanodots spaced apart from one another, each of which is at least partially surrounded by at least one of the trap layers, the nanodots comprising a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer formed between at least two of the plurality of trap layers, the intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, wherein at least one of the trap layers comprises a first trap layer formed to contact the tunnel insulating layer and a second trap layer formed directly on the first trap layer, wherein the first trap layer comprises a plurality of nanodots formed directly on the tunnel insulating layer and partially surrounded by the first material of the first trap layer, and wherein the second trap layer comprises a second group of the nanodots that are substantially completely surrounded by the first material.