Patent ID: 7043511

Claim:
A vector-domain engine for performing a conditional operation in a programmable logic device, comprising: an input port to receive an operand vector; a function unit having an input coupled to the input port and an output that outputs a first output vector comprising the operand vector modified by a logical or arithmetic operation; a comparison unit having an input coupled to the input port and an output that outputs a selection signal based on whether a bit-field of the operand vector matches a pattern; a multiplexer having a selection input coupled to the comparison unit output, a first multiplexer input coupled to the function unit output, and a second multiplexer input coupled to the input port; and a shifter having an input coupled to at least the input port and having an output coupled to the comparison unit input, the shifter being configured to shift the bit-field of the operand vector and output a shifted vector to the comparison unit input.