Patent ID: RE44064

Claim:
A semiconductor memory device comprising: a memory cell for storing data; an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal; a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the first internal clock signal; a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device, the controller having a mode register for generating the mode control signal; a control circuit for selecting between a first mode and a second mode in response to the mode control signal, wherein in the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal; a data input unit for receiving data in synchronization with the second internal clock signal; a data output unit for outputting data including a preamble in synchronization with the third internal clock signal; and a data processing unit for storing data inputted through the data input unit in the memory cell according to the control signals of the control unit, or transferring the data from the memory cell to the data output unit, wherein the preamble is added to a header of the outputted data and is indicative of start of the data; wherein: in the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal, and in the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal.