Patent ID: 7303949

Claim:
A method of manufacturing a semiconductor structure, comprising the steps of: forming a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel in a substrate; forming a pFET stack in the pFET channel and an nFET stack in the nFET channel; providing a first layer of material at source/drain regions associated with the pFET stack, the first layer of material having a lattice constant different than a base lattice constant of the substrate to create a compressive state within the pFET channel; and providing a second layer of material at the source/drain regions associated with the nFET stack, the second layer of material having a lattice constant different than the base lattice constant of the substrate to create a tensile state at the nFET channel; the first layer of material being formed by placing a mask over the nFET channel and etching the regions of the pFET and selectively growing the first layer of material within the regions of the pFET channel, and the second layer of material being formed by placing a mask over the pFET channel and etching regions of the nFET and selectively growing the second layer of material within the regions of the nFET channel; providing a protection layer under the mask and over the nFET stack prior to the etching of the regions of the pFET stack and selectively growing the first layer of material; and providing a protection layer under the mask and over the nFET stack prior to the etching of the regions of the pFET stack and selectively growing the second layer of material.