Patent ID: 7310722

Claim:
A method for processing instructions in a microprocessor configured for parallel processing of a plurality of threads, wherein each thread includes a sequence of instructions, the method comprising: fetching a first instruction from a first thread of the plurality of threads into an instruction buffer configured to store an instruction from each of the plurality of threads, wherein the act of fetching the first instruction includes the acts of: receiving a candidate program counter value from each of the plurality of threads; assigning a priority ranking to each of the plurality of threads, wherein the priority ranking is different at different times; and selecting the first thread among the plurality of threads based at least in part because the first thread is the highest priority thread for which an instruction is not stored in the instruction buffer, wherein the first instruction is fetched in response to selecting the first thread; subsequently fetching a second instruction from a second one of the plurality of threads into the instruction buffer; determining that the first instruction and the second instruction are each ready to execute; and issuing a ready one of the first instruction and the second instruction for execution in response to the selection of the first thread, wherein the second instruction is issued prior to issuing the first instruction in the event that the second instruction is ready to execute and the first instruction is not ready to execute.