Patent ID: 7645620

Claim:
A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures, the method comprising: forming a test structure in a kerf region of a semiconductor wafer, said test structure comprising at least a via structure and a trench structure in contact with said via structure; said via structure being formed in accordance with a critical dimension associated with a corresponding via structure in a circuit region of the semiconductor wafer; and said trench structure in said kerf region being formed so as to have a greater width with respect to a width of a corresponding trench structure in a circuit region of the semiconductor wafer, wherein the width of the trench structure in the circuit region corresponds to a defined minimum ground rule dimension; wherein said greater width of said trench structure of said test structure is a function of a defined, non-zero overlay tolerance with respect to said via structure and said trench structure determined in accordance with the expression: Mx trench width= Mx minimum spacing+ N*Mx to prior level overlay specification; wherein Mx trench width represents the x th level of metallization in the semiconductor wafer, Mx minimum spacing represents said defined minimum ground rule dimension associated with said corresponding trench structure in a circuit region of the semiconductor wafer, Mx to prior level overlay specification represents said overlay tolerance with respect to said via structure and said trench structure, and N represents a factor of said overlay tolerance.