Patent ID: 7502246

Claim:
A memory cell structure, comprising: a substrate side wall including a side wall surface; a substrate main chamber including a main chamber outer wall positioned parallel and spaced from the side wall surface to define a linear ballistic channel therebetween, the linear ballistic channel including a linear ballistic channel entrance aligned with an electron source emitting a flow of electrons into the linear ballistic channel, wherein the substrate main chamber further includes first, second, and third main chamber inner surfaces positioned to define a hollowed area and a substrate island including first, second, third and fourth island outer surfaces disposed centralized within the hollow area and spaced from the main chamber inner surfaces to define a deflection channel circumventing the substrate island and including a deflection channel entrance and a deflection channel exit wherein the deflection channel entrance is defined by a space between two substrate points and accessible from the linear channel, the substrate main chamber further includes first, second, third, and fourth deflective surfaces, the deflective surfaces comprising rounded corners defined where the main chamber inner surfaces and the substrate points intersect at respective ends; a first deflection controller for generating a first electrical field bias on an electron entering the linear ballistic channel, the first deflection controller comprising a pair of positive and negative terminals disposed in opposition to one another and coupled onto the main chamber outer wall and side wall surface and positioned intermediate the deflection channel entrance and the linear ballistic channel entrance; a second deflection controller for generating a second electrical field bias on the electron traveling through the deflection channel comprising a pair of positive and negative terminals disposed in opposition to one another and coupled onto the second main chamber inner surface and the second island outer surface and positioned intermediate the second internally reflective surface and the deflection channel exit, wherein the second set of deflection controllers is configured to apply the second electrical field bias on the electron traveling through the deflection channel to bias a trajectory of the electron to flow either out the deflection channel exit or on toward the third and fourth reflective surfaces wherein the electron is reflected back toward the first reflective surface again; and first and second logic output terminals, wherein the first logic output terminal is positioned for receiving an electron flowing out the linear ballistic channel exit, and the second logic output terminal is positioned for receiving an electron flowing out the deflection channel exit.