Patent ID: 8108652

Claim:
A computer processing system for improving execution throughput of vector processing, comprising: an execution unit for executing one or more instructions from an instruction cache, wherein the execution unit comprises a vector execution unit; a vector memory for storing one or more data streams which are transferred from the vector memory to a vector register file when the vector execution unit issues a vector load command; a prefetch unit for obtaining data from a data cache and storing data in the vector memory such that the data from one or more data streams in the data cache are obtained in a round-robin manner and made available in the vector memory before the execution unit requests the data for executing an instruction; whereas the instruction is executed in one or more iterations using a portion of the data from one or more data streams which correspond to each iteration; a prefetch counter for counting the amount of data from one or more data streams which have become available in the vector memory for execution by the execution unit such that the execution unit starts executing the instruction in one or more iterations using at least a portion of data from the corresponding one or more data streams before all the data in each data stream are made available in the vector memory; whereas the execution unit compares the amount of data from one or more data streams which is required for executing the instruction in one or more iterations with the prefetch counter to determine when to start executing the instruction; and the vector execution unit executes the same instruction for one or more iterations in parallel in one or more staggered execution pipelines; wherein a delay of different durations is imposed in each staggered execution pipeline such that each port of the vector memory is only accessed by one iteration at a time.