Patent ID: 7657850

Claim:
A method of planning chip level scan chains for a hierarchical integrated circuit design having a plurality of physical blocks; a plurality of scan elements, wherein the plurality of scan elements includes a plurality of block scan elements and a plurality of non-block scan elements; and wherein each physical block has a physical block location and the plurality of physical blocks has a plurality of physical block locations, the method comprising: collecting the scan elements from the hierarchical integrated circuit design; determining a block scan chain size for each of a plurality of block scan chains; determining a quantity of chip level block scan chains based on configurable parameters; partitioning, by using a computer, the hierarchical integrated circuit design to form a partition for each chip level block scan chain by: determining a first scan chain size; sorting the plurality of scan elements to form a scan element list; parsing scan element on the scan element list to assign scan elements to a first partition; placing each parsed non-block scan element in the first partition; determining whether all the scan elements of a first physical block containing a parsed block scan element can fit in the first partition; assigning the block scan elements of the first physical block to the first partition when the first physical block can fit in the first partition; splitting the first physical block when the first physical block can not fit in the first partition; and assigning a first subset of the block scan element of the first physical block to the first partition and a second subset of the block scan elements of the first physical block to a second partition; determining a block scan port location for each of a plurality of block scan ports to form a plurality of block scan port locations; placing block scan elements using the block scan port locations; and determining a scan chain path through each partition.