Patent ID: 6939786

Claim:
A method for manufacturing a semiconductor device, comprising: forming on a substrate a plurality of gate electrodes having offset nitride films and gate insulation films; forming a silicon oxide layer so as to cover said substrate and said gate electrodes; forming a lower side wall spacer precursor layer that is thinner than said gate electrodes by etching said silicon oxide layer; forming a silicon nitride layer so as to cover said lower side wall spacer percursor layer; successively etching said silicon nitride layer and said lower side wall spacer precursor layer so as to form side wall spacers having a structure consisting of upper side wall spacer wall spacer portions, said upper side wall spacer portions being formed of said silicon nitride layer remaining on upper side walls of said gate electrodes, and said lower side wall spacer portions being formed of said silicon oxide layer remaining on lower side walls of said gate electrodes; forming an interlayer insulation film so as to cover said gate electrodes having said side wall spacers formed thereon; and etching said interlayer insulation film to form self-aligned contact holes that go through said interlayer insulation film, wherein said forming a plurality of gate electrodes comprises forming said gate electrodes so as to provide a dense region where said gate electrodes are densely gathered and a sparse region where said gate electrodes are more scattered, so that a film thickness of said silicon oxide layer in said dense region is greater than a film thickness of said silicon oxide layer in said sparse region, the method further comprising performing chemical mechanical polishing to smooth out said silicon oxide layer, prior to said forming a lower side wall spacer percursor layer.