Patent ID: 7561655

Claim:
A shift register circuit, comprising: an OR-gate unit for receiving a start pulse or an output of a previous stage and a feedback signal; a level shift unit for level-shifting a swing voltage of a clock signal in response to an output signal of an inverter circuit of the OR-gate unit; and a buffer for transferring an output of the level shift unit to a next stage as an input signal, wherein the OR-gate unit includes an NOR-gate circuit and an inverter circuit serially connected to the NOR-gate circuit, wherein the NOR-gate circuit includes two PMOS transistors (T 1 , T 2 ) connected in serial and two NMOS transistors (T 3 , T 4 ) connected in parallel which are connected to the two PMOS transistors in serial, and the inverter circuit includes an NMOS transistor (T 5 ) and a PMOS transistor (T 6 ), and wherein the level shift unit includes a plurality of NMOS transistors and a plurality of PMOS transistors, and a predetermined bias voltage is additionally applied to the level shift unit.