Patent ID: 7743279

Claim:
An integrated circuit comprising: a first processor configured to output a plurality of program counter (PC) trace records, wherein the plurality of PC trace records provide data indicating the PCs of instructions retired by the first processor; a second source of trace records configured to output a plurality of trace records; and a trace unit coupled to receive the plurality of PC trace records from the first processor and the plurality of trace records from the second source, wherein the trace unit comprises a trace memory into which the trace unit is configured to store the plurality of PC trace records and the plurality of trace records, wherein the trace unit is configured to interleave the plurality of PC trace records and the plurality of trace records from the second source in the trace memory according to the order of receipt of the records, and wherein the interleave includes, in at least one case: a first entry of the trace memory storing a first one or more of the plurality of PC trace records from the first processor, a second entry of the trace memory storing a second one or more of the plurality of trace records from the second source, and a third entry of the trace memory storing a third one or more of the plurality of PC trace records from the first processor, and wherein the second entry is consecutive to the first entry in the trace memory, and wherein the third entry is consecutive to the second entry in the trace memory.