Patent ID: 8173549

Claim:
A method of forming a semiconductor device pattern, comprising: forming a first mask layer pattern comprising a plurality of parallel line portions on an etch target layer on a semiconductor substrate; forming recesses in the etch target layer between the parallel line portions of the first mask layer pattern; forming a sacrificial layer on the first mask layer pattern and in the recesses between the parallel line portions of the first mask layer pattern; forming a second mask layer pattern on the sacrificial layer, the second mask layer pattern comprising respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer; forming a third mask layer pattern comprising first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends; and etching the sacrificial layer and the etch target layer using the third mask layer pattern, the first mask layer pattern and the second mask layer pattern as a mask to thereby form a plurality of parallel trenches in the etch target layer between the line portions of the first and second mask layer patterns.