Patent ID: 7940587

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells, a plurality of word lines, a plurality of bit lines, an associated one of the memory cells being arranged at each of a plurality of intersections of the plurality of word lines and the plurality of bit lines; a first sense amplifier connected to a first bit line at a predetermined position of the plurality of bit lines; a second sense amplifier connected to a second bit line adjacent to the bit line; a supplying circuit for supplying a predetermined voltage to each bit line connected to the first or second sense amplifier; and a sense amplifier control circuit capable of controlling the first and second sense amplifiers independently; wherein the sense amplifier control circuit performs a control in which an operation of either of the first and second sense amplifiers is stopped, the predetermined voltage is supplied to the bit line connected to the stopped sense amplifier, and the other of the first and second sense amplifiers is operated.