Patent ID: 8862951

Claim:
A circuit, comprising: a first summation circuit configured to receive an input data signal and a feedback signal including a previous data bit, the first summation circuit configured to combine the input data signal and the feedback signal to generate a conditioned input data signal that is output to a clock and data recovery circuit that is coupled to an output of the first summation circuit; a first flip-flop coupled to the output of the first summation circuit, the first flip-flop configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit; and a second flip-flop coupled to the output of the first summation circuit, the second flip-flop configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit, wherein the first flip-flop and the second flip-flop are configured output respective signals to additional circuitry that receives the signals from the first flip-flop and the second flip-flop and outputs the feedback signal.