Patent ID: 7672420

Claim:
A shift register stage circuit comprising: a single stage transistor, MP 1 , connected to receive a clock signal, ck, at a source terminal, connected to receive a state input signal at a gate terminal, and to provide a stage output node signal at a drain terminal, the clock signal being a low voltage clock signal having a voltage range between a high voltage supply reference, VDD, and a low clock voltage, VEE, with VEE being greater than a low supply reference voltage, VSS; an input circuit, comprising at least one input transistor, having a gate terminal connected to receive a stage input signal, one of a drain or source terminal connected to the high voltage supply reference, and one of another source or drain terminal connected to a bias voltage, Vgp, with voltage Vgp depending up a threshold voltage of the input transistor, Vth, and the low clock voltage, VEE, and the input circuit connected to provide the state input signal to the gate terminal of the single stage transistor; and a single buffer transistor, MN 1 , connected to receive the low supply voltage, VSS, at a drain terminal, connected to the stage output node at a source terminal, and connected to receive a precharge signal at a gate terminal.