Patent ID: 8325704

Claim:
A device for adjusting a time of reception of a data packet, comprising: a radio receiver having a radio-frequency input for receiving a radio-frequency signal, a first counter for counting cycles of a clock input signal, and a data output for outputting a stream of digital chips obtained from the radio-frequency signal; a data-clock recovery device configured to recover a data-clock clock signal from the stream of digital chips, said data-clock recovery device including a data-clock recovery device input coupled to said data output and a phase-offset output for outputting a phase-offset signal indicative of a phase offset relative to the stream of digital chips, wherein the data-clock recovery device comprises a comparator configured to determine whether edges of chips of the stream of digital chips are received before or after expected times for the edges of the chips, and to output the phase-offset signal; a second counter configured to be initialized at a time of reception of a data packet; circuitry operative, based on the phase-offset signal, to either increment or decrement the second counter based on whether the edges of chips are determined to be received before or after the expected times; and a timestamp determining unit configured to take a sampled count value of said first counter at the time of reception of the data packet, wherein said sampled count value provides an estimate of arrival time of said data packet, and to adjust the sampled count value using a value of said second counter to provide a corrected timestamp providing the corrected time of reception of the data packet.