Patent ID: 7990765

Claim:
A Least Significant Bit (LSB) page recovery method used in a multi-level cell (MLC) flash memory, in which LSB pages and Most Significant Bit (MSB) pages are paired with each other in a paired page structure and are programmed or read, the method comprising: setting first through n th LSB page groups (n being a natural number that is larger than 2) comprising at least two LSB pages from among the LSB pages included in the MLC flash memory; programming first through x th LSB pages (x being a natural number that is larger than 2) included in an i th LSB page group (i being a natural number that is smaller than n); generating and storing an i th LSB parity page for the first through x th LSB pages; programming first through x th MSB pages which correspond to one LSB page from among the first through x th LSB pages; and recovering a j th LSB page, paired with a j th MSB page, using the i th LSB parity page corresponding to the i th LSB page group, when a power supply to the MLC flash memory is stopped during the programming of the j th MSB page (j being a natural number that is smaller than x).