Patent ID: 8076780

Claim:
A semiconductor device comprising: a semiconductor substrate; a circuit portion including a plurality of semiconductor elements formed on said semiconductor substrate; lamination of insulator covering said circuit portion, formed on said semiconductor substrate and including a passivation film as an uppermost layer having an opening; a ferro-electric capacitor formed in said lamination of insulator; a wiring structure formed in said lamination of insulator and connected to said semiconductor elements and said ferro-electric capacitor; a pad electrode structure connected to said wiring structure, formed in said lamination of insulator and exposed in the opening of said passivation film; a conductive pad protection film including a Pd film, formed on said lamination of insulator, covering said pad electrode structure via the opening of said passivation film, and extending on said passivation film; and a stud bump or a bonding wire coupling to a partial area of said conductive pad protection film, and connected to said pad electrode structure via said conductive pad protection film, wherein said pad electrode structure has an uppermost surface having a flaw.