Patent ID: 7732294

Claim:
A method of forming a semiconductor device, comprising: providing a substrate having at least one metal wiring level within the substrate; depositing an insulative layer on a surface of the substrate; forming an inductor within the insulative layer using a patterned plate process; forming a wire bond pad within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor; before depositing the insulative layer on the surface of the substrate, further comprising: depositing a dielectric capping layer on the surface of the substrate, wherein forming the inductor further comprises: forming an at least one opening within the insulative layer; depositing a liner on the surface of the substrate and on a surface within the at least one opening; depositing a seed layer on a surface of the liner; removing a portion of the seed layer from the surface of the liner, leaving the seed layer on the surface of the liner within the at least one opening within the insulative layer; depositing a conductive material within the at least one opening within the insulative layer, such that the conductive material extends above the surface of the substrate; and planarizing the surface of the substrate to remove excess conductive material extending beyond the surface of the substrate, between removing the portion of the seed layer from the liner and depositing the conductive material, further comprising: depositing a layer of photoresist over the surface of the substrate; and forming an opening within the layer of photoresist above and adjacent to the at least one opening within the insulative layer to expose the seed layer within the at least one opening, wherein the opening within the insulative layer has a diameter smaller than a diameter of the opening within the layer of photoresist above and adjacent to the at least one at least one opening within the insulative layer.