Patent ID: 8448034

Claim:
A semiconductor memory device comprising a plurality of semiconductor memory chips in which data requested to be written by an information processing apparatus is written, the data having a plurality of pieces of first data in a predetermined unit, and the device comprising: a setting unit configured to set a pointer pointing to a location to which writing is to be performed in an erased storage region in each of the plurality of the semiconductor memory chips; a write controller configured to write each of the pieces of the first data in a location pointed to by the pointer for the plurality of the semiconductor memory chips and to write redundancy information in a location pointed to by the pointer for a semiconductor memory chip that is different from semiconductor memory chips to which the pieces of the first data are written, the redundancy information being calculated by using the pieces of the first data and being used for correcting an error in the pieces of the first data; and a storage unit configured to store therein identification information and region specifying information so as to be associated with each other, the identification information associating the pieces of the first data and the redundancy information, and the region specifying information specifying a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written, wherein when writing in a storage region in each of the semiconductor memory chips is performed, the setting unit updates the pointer to point to a new location following the location to which the writing is performed.