Patent ID: 8478953

Claim:
A memory configured by storing data and instructions in a computing system which has a processor operable in communication with the memory, the configured memory comprising: an editable buffer; a snapshots data structure stored in the memory, including a directed acyclic graph (DAG) of node(s), and a first snapshot head identifying a first tree within the DAG, the first tree including leaf node(s) having unmodifiable span(s) that hold data element(s) representing a first snapshot of a first version of information that was resident in the buffer at a particular point in time regardless of subsequent editing of the buffer; and processor instructions stored in the memory and designed for creating a second snapshot head identifying a second tree within the DAG and for creating in the DAG a second tree whose leaf node(s) have span(s) whose data element(s) represent a second snapshot of a second version of information that was resident in the buffer including data element(s) that match one-to-one a subsequence of data element(s) held by span(s) of leaf node(s) of the first tree of the DAG, thereby storing in the DAG a plurality of snapshots comprising a plurality of versions of information that was in the editable buffer.