Patent ID: 7501836

Claim:
A capacitance variation determination circuit incorporated into an integrated circuit, comprising: at least first and second parasitic capacitances, the first parasitic capacitance being associated with a first portion of the integrated circuit and having a first capacitance value associated therewith, the second parasitic capacitance being associated with a second portion of the integrated circuit and having a second capacitance value associated therewith; means for providing a transient stimulus signal to the capacitance variation determination circuit and the at least first and second parasitic capacitances; a first logic element operably coupled to the at least first and second parasitic capacitances, the first logic element being configured to switch state: (a) upon detecting the transient stimulus signal, and (b) when a difference between the first and second values exceeds a predetermined amount, and means, operably coupled to the first logic element, for providing an output signal indicative of whether the difference exceeds the predetermined amount.