Patent ID: 7397313

Claim:
A digital phase-locked loop (PLL) system, comprising: a phase detector, coupled to an input signal and a clock signal, for generating a phase difference signal indicating a phase difference between the input signal and the clock signal; a first multiplier, coupled to the phase detector, for multiplying the phase difference signal by a first gain factor; a second multiplier, coupled to the phase detector, for multiplying the phase difference signal by a second gain factor; a digital loop filter, coupled to the first multiplier and the second multiplier, for providing an integral signal and a proportional signal according to outputs of the first multiplier and the second multiplier and for generating a control signal according to the integral signal and the proportional signal; a digitally controlled oscillator, coupled to the digital loop filter, for generating the clock signal according to the control signal; an auto-gain control (AGC) unit, coupled to the second multiplier and the digital loop filter, for updating the second gain factor according to the proportional signal.