Patent ID: 6963420

Claim:
An image processing apparatus which refers to peripheral pixels of a target pixel to perform processing of said target pixel, said image processing apparatus comprising: an input I/F memory configured to read pixels having a predetermined length, subject these pixels to buffering, and write these pixels in a SIMD type processor; a SIMD type processor configured to perform batch processing of the pixels from said input I/F memory so as to provide batch processed pixels; an output I/F memory configured to read the processed pixels, subject the processed pixels to buffering, and write the pixels in a predetermined output destination; and a control unit configured to control read and/or write time of said input I/F memory and said output I/F memory, wherein an effective number of pixels obtained by subtracting the number of peripheral pixels from the number of batch processed pixels is a multiple of the number of rows or columns of a dither matrix and an integer.