Patent ID: 8150028

Claim:
A circuit device comprising: a first circuit comprising a first plurality of serial terminals including a first data receive terminal and a first data transmit terminal, the first plurality of serial terminals communicatively coupled to a particular circuit via isolation circuitry to communicate first serial data, the first circuit includes a frame synchronization terminal to receive a frame synchronization signal from the particular circuit via a frame synchronization isolation circuit; and a second circuit comprising a second plurality of serial terminals including a second data receive terminal coupled to the first data transmit terminal and including a second data transmit terminal coupled to the first data receive terminal to communicate second serial data to the particular circuit via the first data receive and transmit terminals, the second circuit includes a chip selection terminal coupled to the frame synchronization terminal to receive frame synchronization signal from the particular circuit via the frame synchronization isolation circuit wherein the second circuit is selectively activated based on a logic level associated with the frame synchronization signal.