Patent ID: 7818492

Claim:
A flash memory system comprising: flash memory organized into a plurality of blocks of pages, for storage of information, at least each of some of the pages including data and spare, the blocks being identifiable, within the flash memory, by a physical address; and a flash controller adapted to communicate with a host and the flash memory and including volatile memory configured to store a source-shadow table of logical addresses addressable by the physical addresses, the logical addresses identifying the blocks, by the controller, the source-shadow table having an address mapping table and a property value table, the property value table including property values, each of which is associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation, further wherein during power-up, the property values are used to construct the property value table to reflect the current status of the recent information stored in the predetermined group of blocks.