Patent ID: 7482215

Claim:
A method of forming a dual segment liner covering a first and a second set of semiconductor devices on a single substrate, the method comprising: forming a first liner covering said first set of semiconductor devices and a first protective layer on top of said first liner, said first protective layer having a flat top surface; forming a second liner, said second liner having a first section covering said first protective layer, a transitional section on top of an inter-connect structure, and a second section covering said second set of semiconductor devices, said second section being self-aligned to said first liner via said transitional section; forming a second protective layer on top of said second section of said second liner; removing said first section and at least a portion of said transitional section of said second liner; planarizing said second protective layer to be co-planar with at least one of said first and said second liners; and obtaining said dual segment liner including said first liner, at least a part of said transitional section and said second section of said second liner.