Patent ID: 8785283

Claim:
A method for forming a semiconductor structure having at least a metal connect, comprising: providing a substrate; forming a transistor on the substrate and a first inter-dielectric (ILD) layer on the transistor, wherein the transistor comprises a gate and a source/drain region; forming a contact plug in the first ILD layer to electrically connect the source/drain region, wherein a top surface of the first contact plug is higher than a top surface of the gate, and the top surface of the gate is level with a bottom surface of the first ILD layer; forming a second ILD layer on the first ILD layer and forming a third ILD layer on the second ILD layer, wherein etching rates of the first ILD layer and the second ILD layer are different from each other by using a same etchant; forming a first opening correspondingly above the gate and a second opening correspondingly above the first contact plug in the third ILD layer, wherein a depth of the first opening is greater than that of the second opening; deepening the first opening and the second opening such that the gate is exposed by the first opening and the first contact plug is exposed by the second opening, wherein the bottom of the first opening and the bottom of the second opening are in different layers before the deepening process; and filling a metal layer in the first opening and the second opening to form a first metal connect and a second metal connect respectively.