Patent ID: 8299542

Claim:
A field-effect transistor comprising: a gate structure including a fully silicided gate material overlying a gate dielectric disposed on a substrate, the fully silicided gate material having an upper region and a lower region, wherein the lower region has a first lateral dimension in accordance with a lateral dimension of the gate dielectric; the upper region comprises a top region and a middle region having different outer most lateral dimensions, wherein the top region has an uppermost lateral dimension in accordance with the lateral dimension of the gate dielectric and a lowermost lateral dimension at an interface with the middle region in accordance with the lateral dimension of the gate dielectric, and the middle region has a lateral dimension greater than the first lateral dimension; and the top region is of a first silicide material and the middle region and lower region are of a second silicide material different from the first silicide material, and wherein sidewalls of said lower region and at least a portion of a bottom surface of said middle region are in direct contact with a layer of insulating material.