Patent ID: 8026169

Claim:
A method of fabricating a semiconductor device, the method comprising: depositing a layer of copper (Cu) or a Cu alloy in an opening in a dielectric layer, the opening being a dual damascene opening; conducting chemical mechanical polishing (CMP) on an overburden formed in the depositing; conducting a first anneal by heating the deposited layer of Cu or Cu alloy in an atmosphere of nitrogen (N 2 ) and 0 to 4 vol. % hydrogen (H 2 ), at a temperature of about 100° C. to less than 200° C. for up to 5 minutes; and, subsequently, conducting a second anneal by heating the deposited layer of Cu or Cu alloy in N 2 without H 2 at a temperature of about 100° C. to less than 200° C., wherein both the first and second anneals are conducted after the CMP; and wherein the semiconductor device comprises a mirrorbit device having a gate dielectric layer, comprising an oxide/nitride/oxide (ONO) stack on a substrate, and a gate electrode on the ONO stack.