Patent ID: 8003415

Claim:
A method of making a semiconductor chip assembly, comprising: providing a post, a base, an adhesive and a substrate, wherein the substrate includes a first conductive layer, a second conductive layer and a dielectric layer therebetween, the post is adjacent to the base, extends above the base in an upward direction, extends through an opening in the adhesive and extends into an aperture in the substrate, the base extends below the post in a downward direction opposite the upward direction and extends laterally from the post in lateral directions orthogonal to the upward and downward directions, the adhesive is mounted on and extends above the base, is sandwiched between the base and the substrate and is non-solidified, the substrate is mounted on and extends above the adhesive, the first conductive layer extends above the dielectric layer, the dielectric layer extends above the second conductive layer, and a gap is located in the aperture between the post and the substrate; then flowing the adhesive into and upward in the gap; solidifying the adhesive; then mounting a semiconductor device on a heat spreader that includes the post and the base, wherein the semiconductor device overlaps or is overlapped by the post, the assembly includes a pad, a terminal, a routing line and first and second vias, the pad includes a selected portion of the first conductive layer, the routing line includes a selected portion of the second conductive layer, the first via extends through the dielectric layer between the first conductive layer and the routing line, the second via extends through the adhesive to the routing line, the terminal extends below the adhesive and a heat spreader includes the post and the base; electrically connecting the semiconductor device to the pad or the terminal, thereby electrically connecting the semiconductor device to the other of the pad and the terminal, wherein an electrically conductive path between the pad and the terminal includes the first via, the routing line and the second via; and thermally connecting the semiconductor device to the post or the base, thereby thermally connecting the semiconductor device to the other of the post and the base.