Patent ID: 7768075

Claim:
A semiconductor die package comprising: a planar metal substrate within the semiconductor die package; a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture extending through the semiconductor die, wherein the metal substrate is attached to the second surface and exposed by the at least one aperture, wherein the semiconductor die has a thickness of about 30 microns or less; and a plurality of solder structures on the semiconductor die, wherein the plurality of solder structures includes at least one first solder structure disposed on the first surface of the semiconductor die, and at least one second solder structure disposed in the at least one aperture, wherein the at least one second solder conductive structure is in electrical communication with the second terminal at the second surface of the semiconductor die, and the at least one second solder structure directly contacts a portion of the planar metal substrate.