Patent ID: 7111193

Claim:
A circuit which re-configures fuse sets in a semiconductor memory integrated circuit, which utilizes redundant memory rows and columns to repair defective cells within memory cell arrays to improve product yield, comprising: fuse sets which allow unused word lines of the memory cell array to be used to replace defective word lines, fuse sets which allow unused column lines of the memory cell array to be used to replace defective column lines, and at least one of the following: a) circuitry which allows the use of unused column lines to repair defective word lines, b) circuitry which allows the use of unused word lines to repair defective column lines, wherein there exists a sub-circuit, which allows the use of unused column lines to repair defective word lines and which allows the use of unused word lines to repair defective column lines, combines two row address lines, such as RA 0 and RA 11 and their complements, NRA 0 and NRA 1 , to form four row factor lines, RF 0 – 4 .