Patent ID: 7861039

Claim:
An integrated circuit comprising a first-in-first-out memory (FIFO) comprising: a first FIFO sub-block comprising: a first read circuit to provide an indication of whether the first FIFO sub-block is accepting read requests and, when the first FIFO sub-block is accepting read requests, to receive read requests; and to provide the read requests; a first counter to count read requests received by the first FIFO sub-block and to provide the count to the first read circuit; and a first memory array to provide data; and a second FIFO sub-block comprising: a second read circuit to provide an indication of whether the second FIFO sub-block is accepting read requests and, when the second FIFO sub-block is accepting read requests, to receive read requests from the first FIFO sub-block; a second counter to count read requests received by the second FIFO sub-block and to provide the count to the second read circuit; and a second memory array to provide data.