Patent ID: 7574581

Claim:
A computer system comprising: a service processor which issues supervisory commands; a first processing unit, separate from said service processor, having at least a first processor core, a first memory subsystem accessible by said first processor core, a first plurality of scan communication satellites having first registers which enable functions of said first processor core and said first memory subsystem, including a first scan communication satellite located in said first processor core and a second scan communication satellite located in said first memory subsystem, a first scan communication controller connected in a ring with said first and second scan communication satellites which accesses said first registers without interrupting processing of program instructions by said first processor core, a first access port which passes supervisory commands from said service processor to said first scan communication controller, and a first external command interface connected to said first scan communication controller which transmits access commands to an output line, wherein said first scan communication controller includes logic which arbitrates between supervisory commands from said first access port, assembly code commands from said first processor core, and access commands from said first external command interface; a second processing unit, separate from said service processor, having at least a second processor core, a second memory subsystem accessible by said second processor core, a second plurality of scan communication satellites having second registers which enable functions of said second processor core and said second memory subsystem, including a third scan communication satellite located in said second processor core and a fourth scan communication satellite located in said second memory subsystem, a second scan communication controller connected in a ring with said third and fourth scan communication satellites which accesses said second registers without interrupting processing of program instructions by said second processor core, a second access port which passes supervisory commands from said service processor to said second scan communication controller, and a second external command interface connected to said second scan communication controller which receives the access commands at an input line connected to said output line, wherein said second scan communication controller includes logic which arbitrates between supervisory commands from said second access port, assembly code commands from said second processor core, and access commands from said second external command interface; and a fabric bus connecting said first memory subsystem to said second memory subsystem.