Patent ID: 7023251

Claim:
An integrated circuit including a lock loop circuit comprising: a clock input terminal for accepting a clock signal; a phase/frequency detector (PFD) circuit including a reference clock input connected to the clock input terminal and including a PFD feedback input and including a PFD output; a first charge pump (CP) circuit including a first CP input connected to the PFD output and including a first CP output; at least one external feedforward output terminal connectable to couple at least one of a PFD output signal and a charge pump output signal to an external loop filter; a first loop filter (LF) including a filter input connected to the first CP output and including a LF output; a loop controlled signal source (LCSS) including a LCSS input connected to the LF output; an external signal input terminal first frequency selection circuitry responsive to an LCSS output signal for producing a first feedback signal suitable for use with the first loop filter; second frequency selection circuitry responsive to an external signal on the external signal input terminal for producing a second signal suitable for use with an external loop filter if one is connected; and multiplex circuitry coupled to be operable selectively to either couple the first frequency selection circuitry to provide a first signal to the PFD feedback input or to couple the second frequency selection circuitry to provide a second signal to the PFD feedback input.