Patent ID: 7835710

Claim:
A circuit comprising: a delay module that receives a digital transmit signal and that generates a delayed transmit signal; a first digital to analog converter that converts said delayed transmit signal to an analog transmit signal; an analog output circuit that receives said analog transmit signal; an envelope generating module that generates a digital envelope signal based on amplitude information related to said digital transmit signal; a supply adjustment module that supplies a voltage supply reference when said digital envelope signal is less than said voltage supply reference and that boosts a bias voltage of said analog output circuit to a voltage level that is greater than a voltage level of said digital envelope signal when said digital envelope signal is greater than said voltage supply reference; a second digital to analog converter that converts said digital envelope signal to an analog envelope signal, wherein said first digital to analog converter has a higher resolution than said second digital to analog converter; and a third digital to analog converter that receives said digital envelope signal and generates an analog output signal and that selectively boosts a bias current for said analog output circuit based on said analog output signal.