Patent ID: 7295459

Claim:
A memory cell comprising: a first data line; a second data line; a first write line that transmits a first write signal; a second write line that transmits a second write signal; a first read line that transmits a first read signal; a second read line that transmits a second read signal; a bi-stable flip flop between the first data line and second data line, the bi-stable flip-flop including a first and a second inverter, the first inverter having an input from the first data line, and the second inverter having an output to the second data line; a first addressable transmission gate coupled between the first inverter and the first data line, the first addressable transmission gate being controlled by the first write signal and the second write signal; a second addressable transmission gate coupled between the second inverter and the second data line, the second addressable transmission gate being controlled by the first read signal and the second read signal; and a third addressable transmission gate coupled between the output of the second inverter and the input of the first inverter that controls feedback between the first inverter and the second inverter.