Patent ID: 7301798

Claim:
A memory bit cell, comprising: a flip-flop that has additional first and second read/write terminals, the second terminal being different from the first terminal; a 1-bit write line; a first switching transistor connected between the 1-bit write line and the first terminal and the gate of which is connected to a first word selection line; a 0-bit write line being different from the 1-bit write line; a second switching transistor connected between the 0-bit write line and the second terminal, and the gate of which is connected to a second word selection line different from the first word selection line; a bit read line; and first and second read transistors connected in series between ground and the bit read line, the gate of the first read transistor being connected to one of the read/write terminals, the gate of the second read transistor being connected to a word selection line; and wherein one of the read transistors and the switching transistor connected to the same read/write terminal have their gate connected to one and the same word selection line.