Patent ID: 7257720

Claim:
A semiconductor data processing device for connecting a non-volatile storage device to a general-purpose bus of a host system, in which said data processing device enters an active state or standby state in response to a state of said general-purpose bus, said data processing device comprising: a clock circuit for stopping an internal clock signal in said standby state; a voltage generation circuit for applying a substrate bias voltage in a direction for reducing a threshold leak current in said standby state; a rewritable non-volatile memory for storing a control program that connecting said non-volatile storage device to said general-purpose bus; a rewritable non-volatile memory for storing a control program that connecting said non-volatile storage device to said general-purpose bus; a central processing unit for executing said control program, wherein said central processing unit and said non-volatile memory receive said substrate bias voltage; a circuit for detecting the state of said general-purpose bus to control state changes from said standby state to said active state; wherein said substrate bias voltage is not applied to any of this circuit and said voltage generation circuit a first interface controller that interfaces with said non-volatile storage device; a second interface controller that interfaces with said general-purpose bus; and a data transfer controller for controlling data transfer between said first interface controller and said second interface controller; wherein said first and second interface controllers, as well as said data transfer controller input/output parallel data in units of 2n bits while said central processing unit inputs/outputs parallel data in units of n bits or below.