Patent ID: 8334567

Claim:
A device comprising: a substrate; a gate on the substrate, the gate having first and second sides; a first junction region in the substrate adjacent to the gate on the first side; a second junction region in the substrate adjacent to the gate on the second side; at least one dummy gate on the substrate over the second junction region; and a stress layer over the substrate, the gate and the at least one dummy gate, the stress layer creates a stress in the channel and in the second junction region, wherein a placement of the dummy gate over the second junction region distributes the stress of the stress layer over the second junction region to increase the stress exerted across the second junction region as compared to that without the at least one dummy gate to improve performance of the device, wherein the substrate further comprising a fourth junction region adjacent to the gate on the first side, the fourth junction region separating the first junction region from the second junction region, wherein the fourth junction region comprises a depth deeper than the first and second junction regions, the fourth junction region encompassing the first junction region and only overlaps a portion of the second junction region and extends beyond the second side of the gate.