Patent ID: 7082516

Claim:
A method of aligning instructions in a processor comprising: storing a plurality of instructions of different sizes in a plurality of buffer areas, each buffer area including a plurality of sub-buffers, each sub-buffer storing a unit instruction width, with an instruction of greater than a unit instruction width stored in more than one sub-buffer; aligning a first instruction from said buffer areas; decoding a size of the first instruction; selecting at least one of said plurality of sub-buffers from which to output said first instruction on an output part; during said outputting, determining a beginning of a second instruction from selected ones of the plurality of sub-buffers based on the size of the first instruction, decoding the size of the second instruction, and determining whether processing the second instruction will deplete any of said plurality of buffer areas based on comparing a most significant bit of a pointer to a first sub-buffer to a most significant bit of a pointer to a second sub-buffer; and based on said determining whether processing the second instruction will deplete said plurality of buffer areas, instructing the plurality of buffer areas to receive additional instructions.