Patent ID: 7685354

Claim:
A processor, comprising: a cache including a plurality of cache banks; a plurality of processor cores configured to access said plurality of cache banks, wherein to access a given one of said plurality of cache banks, a given one of said plurality of processor cores is further configured to issue a load or store operation that specifies a particular memory address, and wherein said particular memory address uniquely identifies a corresponding storage location within an address space; and core/bank mapping logic coupled to said plurality of cache banks and said plurality of processor cores and configured to receive bank availability information that is configurable to indicate availability for use of ones of said cache banks; wherein said core/bank mapping logic is configurable, according to a configuration of said bank availability information, to map a particular value of a cache bank select portion of said particular memory address specified by said given one of said processor cores to any corresponding one of said plurality of cache banks, wherein said cache bank select portion is a proper subset of said particular memory address that includes fewer than all bits of said memory address, such that: according to one configuration of said bank availability information, said particular value of said cache bank select portion of said particular memory address selects a given one of said plurality of cache banks; and according to a different configuration of said bank availability information, said particular value of said cache bank select portion of said particular memory address selects a different one of said plurality of cache banks; wherein said processor is operable to create a map indicating which of said plurality of processor cores and which of said plurality of cache banks are enabled dependent upon processor configuration information, wherein said map is indicative of said bank availability information; wherein according to any of said configurations of said bank availability information, said core/bank mapping logic is further configured to pass said particular memory address from said given processor core to a selected one of said plurality of cache banks without modifying said particular memory address, such that according to different configurations of said bank availability, different ones of said cache banks are selected for a same value of said particular memory address in a manner that is transparent to said given processor core.