Patent ID: 8171225

Claim:
A cache for a processor, the cache comprising: a plurality of instruction queues configured to handle at least one out-of-order instruction return, wherein each instruction queue corresponds to an execution unit and the instruction queues are configured to be used for capturing requests made to the cache by a plurality of cores of the processor; a data Random Access Memory (RAM) capable of storing a plurality of data; a tag RAM capable of storing memory addresses of the plurality of data stored in the data RAM, wherein said memory addresses stored in said tag RAM are utilized to determine whether a cache lookup results in a hit or a miss; an in-flight RAM capable of: holding outstanding requests forwarded to a next-level memory subsystem; clearing a service request after the request has been fulfilled; determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem; matching fulfilled requests serviced by the next-level memory subsystem to at least one requestor who issued requests while an original request was in-flight to the next-level memory subsystem; and storing information specific to each request, the information including a set attribute and a way attribute, the set and way attributes configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including thread ID, instruction queue position and a color indicator configured to identify a sequential stream in a requesting thread that made the request to the cache, wherein the color indicator is configured to allow the requesting thread to determine whether the returned data is valid or stale; and an arbiter for scheduling hit and miss data returns to each execution unit.