Patent ID: 8178386

Claim:
A method for manufacturing an array of memory cells, comprising: forming a separation layer on a substrate having an array of contacts; forming a patterning layer on the separation layer over the array of contacts, the patterning layer including material having etching characteristics different than the separation layer; forming a sacrificial layer over the patterning layer; forming an array of mask openings in the patterning layer over the array of contacts using a patterning process, said forming an array of mask openings includes forming upper opening segments within the sacrificial layer, and lower opening segments within the patterning layer, the upper and lower opening segments having first and second widths, the sacrificial layer having overhanging portions extending into the openings so that the first widths are less than the second widths; depositing a fill material in the mask openings in the array of mask openings by a process causing formation of voids within the lower opening segments, the voids having widths determined by the difference between the first and second widths; and anisotropically etching the fill material to open the voids and then continuing to anisotropically etch the fill material to expose the separation layer in areas over corresponding contacts in the array of contacts, the areas having widths substantially equal to the widths of the voids, and stopping the etching on or within the separation layer, leaving sidewalls of fill material on the sides of the lower opening segments defining etch masks within the mask openings; etching through the separation layer using the etch masks to define an array of electrode openings exposing corresponding contacts in the array of contacts; depositing electrode material in the electrode openings to form an array of bottom electrodes contacting corresponding contacts in the array of contacts; forming memory elements over and in contact with bottom electrodes within the array of bottom electrodes, the memory elements comprising programmable resistance material; and forming top electrodes in contact with the memory elements.