Patent ID: 7375552

Claim:
An integrated circuit, comprising: an interconnect structure; and a programmable logic block comprising: a programmable lookup table (LUT) having a plurality of LUT input terminals coupled to the interconnect structure, a first LUT output terminal non-programmably coupled to the interconnect structure via a first logic block output terminal, and a second LUT output terminal; a first programmable multiplexer having an output terminal coupled to the interconnect structure, a first multiplexer input terminal coupled to the first LUT output terminal, and a second multiplexer input terminal coupled to the second LUT output terminal; a flip-flop having an output terminal coupled to the interconnect structure; and a second programmable multiplexer, the second programmable multiplexer having an output terminal coupled to a data input terminal of the flip-flop, a first multiplexer input terminal coupled to the first LUT output terminal, and a second multiplexer input terminal coupled to the second LUT output terminal.