Patent ID: 8498372

Claim:
A counter circuit, comprising: plural stages of flip flops connected in cascade, in which a flip flop in a first stage receives a clock from an oscillator as an input signal, and a flip flop in a given stage after the first stage receives a Q output of a preceding stage as an input signal, wherein all or part of the plural stages of flip flops receive a mode signal, and wherein each of the plural stages of flip flops divides by 2 a frequency of the received input signal for output as a Q output when the mode signal indicates a normal delay mode, and each stage of the flip flops that receives the mode signal allows through passage of the received input signal for output as a Q output when the mode signal indicates a delay shortened mode, wherein at least one of the plural stages of flip flops includes: a first latch circuit including a first analog switch to load input data at a D terminal, a first inversion element to invert an output of the first analog switch, a second inversion element to invert an output of the first inversion element, and a second analog switch to form a loop with the first and second inversion elements; and a second latch circuit including a third analog switch to load output data of the first latch circuit, a third inversion element to invert an output of the third analog switch, a fourth inversion element to invert an output of the third inversion element, and a fourth analog switch to form a loop with the third and fourth inversion elements, and wherein the second and fourth inversion elements produce a fixed output at a redetermined level when the mode signal indicates the delay shortened mode.