Patent ID: 7507602

Claim:
A semiconductor device manufacturing method comprising the steps of: preparing a wiring substrate including a wiring pattern on a surface; bonding a connection terminal of an electronic chip, which has a predetermined element and the connection terminal on one surface, to the wiring pattern of the wiring substrate by a flip-chip bonding; forming a first insulating film on the wiring substrate, the first insulating film having a film thickness that covers the electronic chip, or a film thickness that exposes at least another surface of the electronic chip; reducing a thickness of the electronic chip by grinding the first insulating film and said another surface of the electronic chip; forming a via hole having a depth, which reaches the connection terminal on said one surface of the electronic chip from a predetermined portion on said another surface of the electronic chip, in the electronic chip; forming a second insulating film on the electronic chip and the first insulating film without filling up the via hole: forming a wiring recess, which communicates with the via hole, by etching a predetermined portion of the second insulating film containing a portion that corresponds to the via hole; and forming a conductive film pattern, which is electrically connected to the connection terminal via the via hole, by filling a conductive film in the via hole and the wiring recess.