Patent ID: 7915123

Claim:
A method for fabricating a semiconductor memory device in and on a semiconductor substrate, the method comprising the steps of: forming a layered structure comprising a first insulator layer at a surface of the semiconductor substrate, a charge storage layer overlying the first insulator layer, and a second insulator layer overlying the charge storage layer; depositing a sacrificial layer overlying the second insulator layer; patterning and etching the sacrificial layer, the second insulator layer, the charge storage layer, and the first insulator layer to form two spaced apart stacks and an exposed portion of the semiconductor substrate between the two spaced apart stacks; depositing a gate insulator on the exposed portion of the semiconductor substrate; depositing a gate electrode material overlying the gate insulator and the two spaced apart stacks; polishing the gate electrode material to expose the sacrificial layer and to define a gate electrode between the spaced apart stacks wherein the gate electrode material is removed before the sacrificial layer is exposed; removing the sacrificial layer and the second insulator layer; depositing a third insulator layer overlying the charge storage layer and the gate electrode; forming sidewall spacers on each side of the gate electrode and overlying the third insulator layer wherein the sidewall spacers are separated from the gate electrode by respective insulator layers; implanting conductivity determining ions into the semiconductor substrate using the sidewall spacers as ion implantation masks to form bit lines in the semiconductor substrate spaced apart from the gate electrode; depositing an insulating layer overlying the bit lines; depositing a conductive material electrically contacting the gate electrode and the sidewall spacers, and patterning the conductive material to form a word line.