Patent ID: 8214414

Claim:
An apparatus comprising: selector logic to select a logic operation on an input word having a number (N) of input bits, where the logic operation is one of a PopCount operation that indicates a number of set bits in the input word, or a BitScan operation that indicates a bit position within the input word of a first set bit encountered by scanning through the input word; an encoder coupled to the selector logic, the encoder to be enabled by the selector logic, to receive the input word and encode the input word into groups of input bits for the BitScan operation in response to the BitScan operation being selected; and a compressor tree logic circuit coupled to the selector logic and the encoder, to receive the input bits for the PopCount operation or the groups of input bits for the BitScan operation, and perform logic operations on the input bits as bits all having an equal level of significance, to compress the received input bits into a binary value having fewer than N bits, each with a different level of significance.