Patent ID: 7821035

Claim:
An enhancement/depletion inverter circuit comprising: a first semiconductor layer formed with a first nitride-based compound semiconductor with a smaller bandgap on a substrate; a second semiconductor layer formed with a second nitride-based compound semiconductor with a wider bandgap on the first semiconductor layer, the second semiconductor layer including a first opening at a predetermined position; a gate insulating layer formed on a portion of the first semiconductor layer exposed through the first opening; a first gate electrode formed on the gate insulating layer; a first source electrode and a first drain electrode formed at predetermined positions on the second semiconductor layer across the first gate electrode, the first source electrode and the first drain electrode making an ohmic contact to the second semiconductor layer; a second gate electrode formed on the second semiconductor layer, the second gate electrode making a Schottky contact to the second semiconductor layer; and a second source electrode and a second drain electrode formed at predetermined positions on the second semiconductor layer across the second gate electrode, the second source electrode and the second drain electrode making an ohmic contact to the second semiconductor layer.