Patent ID: 8921928

Claim:
A semiconductor device, comprising: a first trench, provided in a semiconductor region of a first conduction type; a drain electrode, formed within the first trench; a second trench, provided in the semiconductor region of the first conduction type; a source electrode, formed within the second trench; a third trench narrower than the first trench and second trench, provided in the semiconductor region of the first conduction type, and in contact with a drift region associated with the first trench and a source region associated with the second trench; and a gate electrode, formed within the third trench; wherein the third trench is in contact with the drift region along a first wall of the third trench from a top edge of the drift region to a bottom edge of the third trench, and is in contact with the source region from a top edge of the source region to the bottom edge of the third trench; wherein in a plan view a plurality of third trenches are arranged perpendicularly to both the first trench and the second trench, each of the plurality of third trenches having at least a third wall that begins at a point where a corresponding first wall is in contact with the drift region and ends at a point where a corresponding second wall is in contact with the source region, and wherein at least one third trench of the plurality of third trenches is separated from another third trench of the plurality of third trenches by an area of an element formation region, the area of the element formation region being bounded by a third wall of the at least one third trench, a third wall of the other third trench, the drift region and the source region, and the area of the element formation region including a pickup region.