Patent ID: 8735257

Claim:
A method, comprising: disposing at least two varactor gate conductors arranged in parallel over an active area defined in a semiconductor substrate, the two parallel varactor gate conductors overlying gate dielectric material; disposing source and drain regions in the active area in parallel to one another and in parallel to the at least two varactor gate conductors, and disposed on opposite sides of the at least two varactor gate conductors; forming a first metal layer gate connector over the at least two varactor gate conductors; electrically coupling the first metal layer gate connector to the varactor gate conductors using vertical contacts through an insulator material; forming a second metal layer source/drain connector over the active area spaced from the gate connector, the second metal layer source/drain connector not overlapping the at least two varactor gate conductors; and electrically coupling the source and drain regions to the second metal layer source/drain connector by forming vertical connections comprising a first level via through an interlevel dielectric to a first metal layer portion and to a contact to the source drain regions in the active area.