Patent ID: 6957399

Claim:
A system comprising: a printed circuit board, wherein configured on the printed circuit board is: a memory controller; a memory unit; and an interface unit, wherein the memory controller is coupled to the memory unit through the interface unit; wherein the interface unit is configured to receive an input clock and a read signal from the memory controller and a trigger signal from the memory unit; wherein the interface unit is further configured to generate an enable signal based on the read signal and to conditionally propagate the trigger signal based on the enable signal; wherein the interface unit includes a qualifying circuit, the qualifying circuit comprising: a first logic gate; a second logic gate; and a set of flip-flops coupled in a series; wherein an output of the first logic gate is the enable signal and is coupled to an input of the second logic gate; wherein an output of a last flip-flop of the series is coupled to an input of the first logic gate; wherein an input of a first flip-flop of the series is coupled to a constant value; wherein a delayed version of the read signal is coupled to a preset input of each flip-flop of the series; wherein another input of the first logic gate is configured to receive the delayed version of the read signal; wherein a clock input of each flip-flop of the series is configured to receive the trigger signal so as to induce triggering of each flip-flop on the trailing edge of each pulse of the trigger signal; and wherein another input of the second logic gate is configured to receive the trigger signal.