Patent ID: 8681807

Claim:
A packet switching device, comprising: at least one ingress port configured to receive incoming packets of data; a plurality of egress ports that are configurable to transmit outgoing packets of data, the egress ports being all of the egress ports available in the packet switching device; an allocation manager configured to determine a subset of the egress ports actively coupled to outer links; a dynamically configurable storage unit configured to include all memory blocks of the packet switching device that are allocatable to the subset of the egress ports, each of the egress ports having one of a plurality of congestion statuses, wherein the all memory blocks are allocated among the subset of the egress ports, and all memory blocks that are de-allocated from the subset of the egress ports are always dynamically re-allocated back to the subset of the egress ports based on the congestion statuses such that egress ports having a same congestion status are allocated with a same number of memory blocks; a controller configured to change a size of a memory block that is allocated to an egress port as a function of a condition of at least one egress port; a counter configured to keep a count of interfaces connected to the subset of the egress ports; a resource allocation table configured to periodically fetch an entry of the resource allocation table, which is accessed by a dynamic allocation pointer derived based on the count; and an allocation register configured to copy values of the entry into the allocation register, the allocation register further configured to control a number of the memory blocks allocated for each of the interfaces based on the copied values.