Patent ID: 8850262

Claim:
An apparatus comprising: non-transitory computer readable storage medium storing computer readable prongram code executable by a plurality of centaral processing units (CPU), wherein the plurality of CPUs are configured in a ring and each CPU n determines whether a CPU n+1 that is logically adjacent to the CPU n in the ring has failed, the computer readable program code comprising: a retrieval module of the CPU n configured to retrieve a timestamp n+1 from a shared memory that is shared by the plurality of CPUs, wherein the timestamp n+1 is written to the shared memory by the CPU n+1 , wherein the CPU n is a first core in a multi-core processor and the CPU n+1 is a second core in a multi-core processor, the multi-core processor comprising a plurality of cores; a comparison module of the CPU n configured to compare the timestamp n+1 to a timestamp n generated by a CPU n checking the CPU n+1 for failure and determine a delta value; the comparison module of the CPU n further configured to compare the delta value with a threshold value and determine whether the CPU n+1 has failed; and a detection module of the CPU n configured to, in response to the comparison module determining that the CPU n+1 has failed, initiate error handling for the plurality of CPUs.