Patent ID: 8180998

Claim:
A system for performing data-parallel operations and task-parallel operations, comprising: a first switch fabric node (SFN), including: a first lane processing engine (LPE) having a first set of lane processing units (LPUs) configured to perform data-parallel operations, wherein in-order scheduling is implemented across the first set of LPUs, each LPU within the first set of LPUs performs a set of operations, each LPU within the first set of LPUs uses a different set of data for the set of operations, and the first set of LPUs accesses a first set of shared memory units (SMUs) via a first LPU interconnect; and a second LPE having a second set of LPUs configured to perform task-parallel operations, wherein in-order scheduling is implemented across the second set of LPUs, each LPU within the second set of LPUs performs a different set of operations, and the second set of LPUs accesses a second set of SMUs via a second LPU interconnect; and a processing control engine (PCE) configured to distribute instructions and data to the first LPE and the second LPE, wherein the instructions and data are associated with the data-parallel operations and the task-parallel operations as the case may be, wherein the PCE is further configured to: cause a first data movement unit (DMU) associated with the first LPE to transmit a first instruction set and multiple data sets to the first set of SMUs; and cause a second DMU associated with the second LPE to transmit multiple instruction sets to the second set of SMUs.