Patent ID: 7178075

Claim:
A method for maximizing the frequency of test clocks in a Level Sensitive Scan Design (LSSD) system wherein non-overlapping Shift A and Shift B test clocks are synchronized to rise and fall simultaneously at inputs of all LSSD registers, the method comprising the steps of: determining the number of pipeline stages needed to reach the farthest corner of said LSSD system to establish the depth of the pipeline; grouping said LSSD registers into regions defined by the number of pipeline stages needed to ensure high speed operation; balancing the pipeline depth to achieve simultaneous rise or fall of a signal at the inputs of said LSSD registers; and ensuring that all Shift A and Shift B test clocks are distributed at high speed, and verifying that pipeline latches are placed in proximity of said LSSD registers to enable a high speed synchronous propagation of the Shift A and Shift B test clocks.