Patent ID: 8079004

Claim:
A method for performing an efficient path-based static timing analysis (STA) in a circuit design, the method comprising: identifying a set of paths within the circuit design, wherein each path comprises one or more segments; for a path in the set of paths, determining, by computer, if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information; and if so, performing an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path; otherwise, computing a path-based delay for the path by performing a path-based STA on the path, wherein the method reduces computational time by reusing timing information associated with previously computed paths to quickly estimate path-based delays for paths which have not been analyzed.