Patent ID: 6849880

Claim:
A power semiconductor device comprising: a first semiconductor layer of a first conductivity type having first and second main surfaces opposite to each other; a plurality of second semiconductor layers of a second conductivity type disposed in the first semiconductor layer, the second semiconductor layers extending in a depth direction from the first main surface side, and being arrayed at intervals; a plurality of third semiconductor layers of the second conductivity type respectively disposed in contact with the second semiconductor layers on the first main surface side; a plurality of fourth semiconductor layers of the first conductivity type respectively formed in surfaces of the third semiconductor layers; a first main electrode disposed on the second main surface side and electrically connected to the first semiconductor layer; a gate electrode facing, through a first insulating film, a channel region, which is each of portions of the third semiconductor layers interposed between the fourth semiconductor layers and the first semiconductor layer; an additional electrode disposed on each of the second semiconductor layers through a second insulating film, and facing, through said each of the second semiconductor layers, the first main electrode, the additional electrode being electrically connected to the gate electrode; and a second main electrode disposed on the first main surface side and electrically connected to each set of the third semiconductor layers and the fourth semiconductor layers.