Patent ID: 7629264

Claim:
A method of forming an interconnect comprising: providing an interconnect dielectric layer atop a substrate, the interconnect dielectric layer including at least one stud consisting of tungsten (W) extending from an upper surface of the interconnect dielectric layer to the substrate; recessing an upper surface of the at least one stud below the upper surface of the interconnect dielectric layer to provide at least one recessed stud; forming a first low-k dielectric layer atop the upper surface of the interconnect dielectric layer and the at least one recessed stud; depositing a second low-k dielectric layer atop an upper surface of the first low-k dielectric layer; forming a thermal oxide atop the second low-k dielectric layer; forming a block mask atop the thermal oxide exposing a portion of the thermal oxide overlying the recessed stud; etching the portion of the thermal oxide that is exposed by the block mask selective to the second low-k dielectric layer with an anisotropic etch step; etching the second low-k dielectric layer selective to the upper surface of the at least one recessed stud to provide an opening to expose an upper surface of the at least one recessed stud; applying an isotropic etch through the opening to remove a portion of the interconnect dielectric layer selective to the first low-k dielectric layer; and filling the opening with copper (Cu).