Patent ID: 7684531

Claim:
A data recovery circuit comprising: a sampling unit configured to oversample received data that have been transmitted serially in sync with a first clock of frequency f 1 , using a multiphase clock generated by shifting a phase of a second clock of frequency f 2 at a prescribed interval, the second frequency f 2 of the multiphase clock being at or below the first frequency f 1 ; a data restoration unit configured to extract f 1 /f 2 bits on average from the oversampled data and recover the extracted bits to restore the received data, wherein the multiphase clock is generated independently of the first clock of the received data, the data restoration unit recovers the extracted bits by counting the extracted bits and converting the extracted bits to symbol data when the count reaches a prescribed value, the data restoration unit includes a selection signal generator configured to generate a selection signal for designating bits to be extracted from the oversampled data, and the data restoration unit is configured to extract the f 1 /f 2 bits on average from the oversampled data based on the selection signal.