Patent ID: 6885572

Claim:
A semiconductor memory device comprising: at least one piece of a memory cell array; a plurality of sub-banks having a plurality of main amplifiers being placed in a vicinity of said memory cell array and being used to amplify data read from said memory cell array; a plurality of data inputting and outputting pads arranged according to predetermined specifications in a wiring space placed among said plurality of said sub-banks; a plurality of global input and output lines to connect said plurality of said main amplifiers and said plurality of said data inputting and outputting pads; and wherein said plurality of said sub-banks is divided into a plurality of groups of said sub-banks and said plurality of said data inputting and outputting pads is divided in a manner so as to be corresponded to said plurality of said groups of said sub-banks and wherein said plurality of said main amplifiers belonging to one of said groups of said sub-banks being placed far from a corresponding plurality of said data inputting and outputting pads is arranged in same order as said corresponding plurality of said data inputting and outputting pads, and said plurality of said main amplifiers belonging to an other of said groups of said sub-banks being placed near to a corresponding plurality of data inputting and outputting pads is arranged in order symmetric to an order in which said corresponding plurality of said data inputting and outputting pads is arranged and wherein wiring of said plurality of said global input and output lines is carried out so that said plurality of said global input and output lines is placed in a distributed manner without being concentrated in certain places in each of said groups of said sub-banks.