Patent ID: 8086930

Claim:
An encoder, comprising: an encoding module for encoding a plurality of information bits thereby generating a plurality of parity bits; and wherein: the encoding module for employing a fixed spacing to intersperse the plurality of parity bits among the plurality of information bits thereby generating a codeword; according to the fixed spacing, a first subset of information bits of the plurality of bits being between a first parity bit of the plurality of parity bits and a second parity bit of the plurality of parity bits; according to the fixed spacing, a second subset of information bits of the plurality of bits being between the second parity bit of the plurality of parity bits and a third parity bit of the plurality of parity bits; each of the first subset of information bits and the second subset of information bits including a same number of bits; the encoding module for combining at least one information bit and the plurality of parity bits to generate a plurality of tail bits; and the encoding module for employing the fixed spacing to intersperse the tail bits among the plurality of information bits thereby generating the codeword.