Patent ID: 7560343

Claim:
A manufacturing method of the non-volatile memory, comprising: providing a substrate, wherein the substrate has a device isolation structure for defining a plurality of pairs of active regions; forming a control gate in one of each pair of the active regions of the substrate; forming a gate oxide layer, a conductor layer, and a patterned mask layer on the substrate in sequence, wherein the patterned mask layer exposes a portion of the conductor layer; forming a first dielectric layer on the surface of the exposed portion of the conductor layer; removing the patterned mask layer; removing the conductor layer not covered the first dielectric layer, and using the remained conductor layer as a floating gate; forming a second dielectric layer on sidewalls of the floating gate; forming an erase gate over the floating gate above the control gate, wherein the erase gate covers the first dielectric layer and the second dielectric layer; and forming a source region and a drain region in the other one of each pair of the active regions of the substrate, wherein the source region and the drain region are disposed at both sides of the floating gate respectively.