Patent ID: 8014288

Claim:
A packet switch, comprising: a plurality of output ports; a plurality of input ports, each input port of the plurality of input ports configured to receive a data packet including data units at the input bandwidth of the input port and identify a destination output port of the plurality of output ports for the data packet; a switch fabric coupled to the plurality of input ports and the plurality of output ports; a plurality of credit counters corresponding to the plurality of input ports and configured to store a corresponding plurality of credit values for the plurality of input ports; a plurality of latency counters corresponding to the plurality of input ports; and an arbiter coupled to the plurality of input ports, the plurality of credit counters, and the plurality of latency counters, the arbiter configured to select an input port of the plurality of input ports in a plurality of nonconsecutive arbitration cycles based on the plurality of credit values, the selected input port configured to route the data packet received at the selected input port to the switch fabric in the plurality of nonconsecutive arbitration cycles by routing a data unit of the data packet in each arbitration cycle of the plurality of nonconsecutive arbitration cycles, the arbiter further configured to measure a latency for routing the data packet received at the selected input port from the selected input port to the switch fabric by starting the latency counter corresponding to the selected input port for a first data unit of the data packet routed from the selected input port to the switch fabric and stopping the latency counter corresponding to the selected input port for a last data unit of the data packet routed from the selected input port to the switch fabric such that the latency counter corresponding to the selected input port indicates the measured latency, the arbiter further configured to modify the credit value of the selected input port based on the measured latency for reducing variance among latencies of data packets subsequently routed through the packet switch, wherein the latency for routing the data packet received at the selected input port to the switch fabric is equal to a number of clock cycles of a clock signal spanning a time period for routing the data packet from the selected input port to the switch fabric, the switch fabric configured to route the data packet received from the selected input port to the destination output port of the data packet.