Patent ID: 7737480

Claim:
A semiconductor memory device comprising: a MIS transistor including source/drain regions formed in a substrate; a first interlayer insulating film formed on the substrate and the MIS transistor; a capacitor including a storage node electrode formed above one of the source/drain regions, a capacitor insulating film formed on the storage node electrode, and a plate electrode formed on the capacitor insulting film; a second interlayer insulating film formed on or above the plate electrode and the first interlayer insulating film; a bit line formed on the second interlayer insulating film and extending in a gate width direction of the MIS transistor; a first conductive plug passing through the first interlayer insulating film and connecting one of the source/drain regions and the storage node electrode; a second conductive plug passing through the first interlayer insulating film and connected to other source/drain region that is not connected to the first conductive plug; and a third conductive plug passing through at least the second interlayer insulating film on the second conductive plug and connecting the second conductive plug and the bit line, wherein a central axis of the third conductive plug is displaced from a central axis of the second conductive plug in a direction perpendicular to a direction that the bit line extends when viewed in plan, the third conductor plug has a bottom surface, a part of which is in contact with the first interlayer insulating film, a lower end part of the third conductive plug is embedded in the first interlayer insulating film, and the third conductive plug is in contact at the lower end part thereof with part of an upper end part at an upper face and a side face of the second conductive plug.