Patent ID: 8356240

Claim:
An information processing apparatus comprising: a data transmitting apparatus that transmits data of an N-bit width, where N is a positive integer greater than or equal to 4; a data receiving apparatus that receives the data of the N-bit width from the data transmitting apparatus; and a data bus of the N-bit width connecting the data transmitting apparatus and the data receiving apparatus, wherein the data transmitting apparatus comprises: a first error-detection-code-attached data generation circuit that generates, for first data of an X-bit width, where X is a positive integer greater than or equal to 1 satisfying X<N, from among the data of the N-bit width, first error-detection-code-attached data provided with an error detection code for detecting a data transmission error by the data receiving apparatus; a second error-detection-code-attached data generation circuit that generates, for second data of an (N-X)-bit width from among the data of the N-bit width, second error-detection-code-attached data provided with an error detection code for detecting a data transmission error by the data receiving apparatus; a first degeneration correspondence register that records therein an error occurring position in the data bus, based on a first or second error notifying signal from the data receiving apparatus; and a transmission-side selection circuit that selects either one of a first data bus of an X-bit width and a second data bus of an (N-X)-bit width of the data bus of the N-bit width, based on a data degeneration notifying signal to output the first and second error-detection-code-attached data, and selects either bits of the first and second data buses in another data bus not selected from among the first and second data buses, based on a usable bit position notifying signal based on recorded contents of the first degeneration correspondence register to output third data different from the first and second error-detection-code-attached data, and wherein the data receiving apparatus comprises: a first error checking circuit that detects an error in the first errordetection-code-attached data and outputs the first error notifying signal when having detected an error; a second error checking circuit that detects an error in the second errordetection-code-attached data and outputs the second error notifying signal when having detected the error; and a second degeneration correspondence register that records therein an error occurring position in the data of the N-bit width based on the first or second error notifying signal.