Patent ID: 8073891

Claim:
A device for implementing Montgomery modular multiplication, comprising: a computation cell having a multiplier-adder comprising pipelined logic-register pairs, which are configured to receive several digits to be added together and multiplied, at least two outputs of the multiplier-adder corresponding to a low order of the digits and to a high order of the digits, and an adder receiving the two outputs of the multiplier-adder, wherein a number p of the pipelined logic-register pairs is chosen in such a way that the maximum frequency F 1 max of the multiplier-adder is greater than or equal to the maximum frequency F 2 max of the adder, said digits of the multiplier-adder includes x, y and z, which correspond to inputs of the multiplier-adder, and said two outputs of the multiplier-adder correspond to an operation xÃ—y+z and an operation xÃ—y+z.