Patent ID: 7706167

Claim:
A resistance change memory device comprising: a substrate; a plurality of cell arrays stacked above the substrate, each the cell array including a matrix layout of memory cells, first wiring lines and second wiring lines disposed to cross the first wiring lines as being isolated from the first wiring lines, each the memory cell having a variable resistance element for storing as information a resistance value and a diode stacked at each cross portion of the first wiring lines and the second wiring lines; a write circuit configured to write a pair cell constituted by two neighboring memory cells within the cell arrays in such a manner as to store complementary data; and a read circuit configured to read complementary resistance value states of the pair cell as one bit of data, wherein upper and lower neighboring cell arrays share at least one group of the first wiring lines and the second wiring lines, the write circuit is configured to be operatively associated with a plurality of neighboring memory cells to be selected from the plurality of cell arrays, for supplying a negative logic write pulse to a selected first wiring line and supplying a positive logic write pulse to a selected second wiring line while adjusting a phase of these pulses in accordance with data to be written, and wherein the variable resistance element comprises: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein, and wherein the write circuit comprises: a pulse generator circuit configured to generate two types of pulses being nearly equal in pulse width as each other and having a phase difference therebetween; a logic gate circuit configured to output a negative logic pulse given to one of the first and second wiring lines and a positive logic pulse given to the other with an overlap time thereof determined by a combination logic depending upon write data of the two types of pulses as output from the pulse generator circuit; and a pulse booster circuit for boosting at least one of the negative logic pulse and the positive logic pulse output from the logic gate circuit when the write data is in a high resistance value state so as to generate the negative logic write pulse and the positive logic write pulse.