Patent ID: 7728657

Claim:
A Phase Locked Loop (PLL) circuit comprising: a clock signal generating means configured to generate a first clock signal with a frequency approximately equal to that of a Phase Shift Keying (PSK) modulation signal which is a digital signal subjected to PSK modulation, and a second clock signal of which the phase differs from said first clock signal by Π/2; a computing means configured to compute, for each time period of a predetermined length, first phase comparison results showing the results of comparing the phases of a signal wherein said first clock signal is subjected to phase shifting of an amount equivalent to a control angle which is an angle to virtually control the phases of said first clock signal and said second clock signal with said PSK modulation signal during said time period, and second phase comparison results showing the results of comparing the phases of a signal wherein said second clock signal is subjected to phase shifting of an amount equivalent to said control angle with said PSK modulation signal during said time period, based on a first parameter corresponding to the cosine of said control angle, a second parameter corresponding to the sine of said control angle, said first clock signal, said second clock signal, and said PSK modulation signal; a control direction setting means configured to set the control direction for virtually controlling said control angle based on said first phase comparison results and said second phase comparison results; a parameter control means configured to control said first parameter and said second parameter based on said control angle virtually controlled in said control direction; and a reading control means configured to control the timing of reading data from said PSK modulation signal based on said control angle virtually controlled in said control direction.