Patent ID: 8630115

Claim:
A memory comprising: first and second arrays of memory cells, wherein the first and second arrays of memory cells include bitlines, and wherein a first row of the first array of memory cells is coupled to a second row of the first array of memory cells and a first row of the second array of memory cells is coupled to a second row of the second array of memory cells; third and fourth arrays of memory cells, wherein the third and fourth arrays of memory cells include bitlines; a first row decoder between the first and second arrays of memory cells, the first row decoder coupled to the first and second rows of the first array of memory cells and the first row decoder configured to simultaneous select the first and second rows of the first array of memory cells, and the first row decoder further coupled to the first and second rows of the second array of memory cells and the first row decoder further configured to simultaneous select the first and second rows of the second array of memory cells; a second row decoder between the third and fourth arrays of memory cells; a first sense latch coupled directly to said bitlines of said first array of memory cells and indirectly to said bitlines of said third array of memory cells through said first array of memory cells and a bank of decoupling transistors on each bitline to decouple said first and third arrays of memory cells when a cell in said first array of memory cells is being accessed; and a second sense latch coupled directly to said bitlines of said second array of memory cells and indirectly to said bitlines of said fourth array of memory cells through said second array of memory cells and a bank of decoupling transistors on each bitline to decouple said second and fourth arrays of memory cells when a cell in said second array of memory cells is being accessed.