Patent ID: 7411432

Claim:
An integrated circuit, comprising: synchronous logic having at least one master-slave register with a data input, in which the master portion comprises a first latch and true and complementary gatable data paths driving the respective true and complementary nodes of the first latch, and the slave portion comprises a second latch and true and complementary gatable data paths to drive the respective true and complementary nodes of the second latch, the gatable data paths each comprising a switch configured to enable selective transfer of a signal therethrough dependent on a gate signal, and an inverter disposed electrically in series with the switch; combinational logic to electrically drive at least one data input of the synchronous logic; and a clocking circuit to clock the master portion and the slave portion of the at least one master-slave register with respective lag and lead relative renderings of a clock signal, the clocking circuit configured to selectively enable the gatable data paths of the master portion based on the lag rendering of the clock signal and to selectively enable the gatable data paths of the slave portion based on the lead rendering of the clock signal, the clock circuit comprising: a first latch of CMOS inverters inter-coupled input-to-output and output-to-input for the respective true and complementary nodes; a second latch of CMOS inverters inter-coupled input-to-output and output-to-input for the respective true and complementary nodes; a first inverter to invert and forward a signal from the true node of the first latch to a true node of the second latch; and a second inverter to invert and forward a signal from the complementary node of the first latch to a complementary node of the second latch; the true and complementary nodes of the second latch of the clock circuit operable together as a differential output to source the lag rendering of the clock signal and to drive the switches in the data paths of the master portion of the master-slave register; and the true and complementary nodes of the first latch of the clock circuit operable together as a differential output to source the lead rendering of the clock signal and to drive the switches in the data paths of the slave portion of the master-slave register.