Patent ID: 8700950

Claim:
A solid-state storage subsystem comprising: a non-volatile memory array; a controller configured to implement a data redundancy configuration with a plurality of data stripes in the non-volatile memory array; and a volatile memory for temporarily storing data to be written to the non-volatile memory array and parity data for one or more of the data stripes in the non-volatile memory array, wherein each of the plurality of data stripes is of a pre-defined stripe size and wherein the controller is configured to write parity data for a data stripe to the non-volatile memory array when data already written to the non-volatile memory for the data stripe reaches the pre-defined stripe size; wherein the controller is further configured to: detect an occurrence of a data access error in one of the plurality of data stripes for which parity data has not been written to the non-volatile memory array; and in response to detecting an occurrence of a data access error, move the parity data for the data stripe causing the error from the volatile memory to the non-volatile memory array ahead of a scheduled writing of the parity data, and attempt to correct the data access error with the newly written parity data.