Patent ID: 7782276

Claim:
A scan driving circuit comprising: a first scan driver comprising a plurality of first stages and configured to sequentially output a selection signal; and a second scan driver comprising a plurality of second stages and configured to sequentially output an emission signal, wherein each of the first and second stages comprises: a first transistor configured to receive an output voltage of a previous stage or a first input signal, and comprising: a gate terminal coupled to a first clock terminal; and an output terminal; a second transistor coupled with a second clock terminal and an output line, and comprising a gate terminal coupled to the output terminal of the first transistor; a third transistor coupled between a second power supply and a first node, comprising a gate terminal coupled to one of the first and second clock terminals; a fourth transistor coupled with the first clock terminal and the first node, and comprising a gate terminal coupled to the output terminal of the first transistor; a fifth transistor coupled between a first power supply and the output line, and comprising a gate terminal coupled to the first node; and first and second clock input lines configured to receive first and second clock signals, respectively, wherein the first clock input line is coupled to the first clock terminal of a plurality odd numbered stages of the first scan driver, and the second clock input line is coupled to the second clock terminal of the plurality of odd numbered stages of the first scan driver, wherein each of the plurality of odd numbered stages of the first scan driver is configured to perform a precharge operation when the first clock signal has a low level, and to perform an evaluation operation when the first clock signal has a high level.