Patent ID: 7231413

Claim:
A transposition circuit for generating data packets arranged as a transposed matrix and obtained from data packets in the form of an N×N matrix (where N is an integer of 2 or greater) by interchanging rows and columns of an original matrix, wherein N input terminals and N output terminals are provided; wherein N packets of data are output in parallel for each matrix column from said output terminals when N packets of data are input in parallel for each matrix row to said input terminals; wherein the transposition circuit is provided with N memory units having storage areas to accommodate N data packets, N input selectors having output ports individually connected to input ports of the memory units, N output selectors having output ports individually connected to said output terminals, and a control unit; wherein said input and output selectors having N ports, and any of the ports of said input and output selectors are used as an input port in accordance with a common selection signal from said control unit to said input and output selectors; wherein the ports of said input selectors are connected to corresponding ones of the input terminals; wherein the ports of said output selectors are connected to output ports of corresponding ones of the memory units; and wherein said control unit generates the common selection signal, and produces address signals to specify a common storage area for each of the memory units, to both read data from and write data to the common storage areas during a same period.