Patent ID: 7016988

Claim:
An output buffer register comprising: a first flip-flop register comprising a given number N of flip-flops each having a data input, a data output, and an enable input; a second flip-flop register comprising N flip-flops, each having a data input, a data output, and an enable input; a third flip-flop register comprising a flip-flop having a data input, a data output, and an enable input; and an output multiplexer having N first inputs, N second inputs, N outputs and a selection input, and wherein the enable inputs of the flip-flops of the first, second, and third registers, receive one and the same clock signal; the data inputs of the N flip-flops of the first register respectively receive N input signals; the data outputs of the N flip-flops of the first register are respectively linked to the the N first inputs of the output multiplexer; the N outputs of the output multiplexer deliver N respective output signals; the data inputs of the N flip-flops of the second register are respectively linked to the N outputs of the output multiplexer; the N data outputs of the N flip-flops of the second register are respectively linked to the N second inputs of the output multiplexer; the data input of the third register receives an enable signal; and the data output of the third register is linked to the selection input of the output multiplexer.