Patent ID: 8679878

Claim:
A method of forming an array substrate, comprising: forming a first conductive layer on a substrate; forming a first photoresist layer on the first conductive layer; patterning the first photoresist layer by a lithography process with a first multi-tone photomask to form a first non-photoresist region, a first thin photoresist pattern, and a first thick photoresist pattern; etching the first conductive layer of the first non-photoresist region to form a gate electrode, a gate line connecting to the gate electrode, a common line, and a bottom conductive line, wherein the first thin photoresist pattern is on the gate electrode, the gate line, the common line, and a wiring region of the bottom conductive line, and wherein the first thick photoresist pattern is on a contact region of the bottom conductive line; ashing the first thin photoresist pattern to expose the gate electrode, the gate line, the common line, and the wiring region of the bottom conductive line; selectively depositing an insulation layer on the substrate, the gate electrode, the gate line, the common line, and the wiring region of the bottom conductive line; selectively depositing a semiconductor layer on the insulation layer; removing the first thick photoresist pattern; and forming a second conductive layer on the semiconductor layer and the contact region of the bottom conductive line.