Patent ID: 8084852

Claim:
A semiconductor device comprising: (a) a wiring substrate having a main surface and a back surface which is opposite to the main surface, amount pad being disposed over the main surface, and the back surface having two pairs of sides in a plan view; (b) a semiconductor chip including: a plurality of first transistors for a first power amplifying system (e), and a plurality of second transistors for a second power amplifying system (f), mounted over the mount pad; (c) a plurality of first electrode terminals disposed over the back surface of the wiring substrate, the plurality of first electrode terminals being arranged along each of the two pairs of sides, the plurality of the first electrode terminals including: a first input terminal for the first power amplifying system, a first output terminal for the first power amplifying system, a second input terminal for the second power amplifying system, and a second output terminal for the second power amplifying system, (d) a plurality of second electrode terminals disposed over the back surface of the wiring substrate, the plurality of second electrode terminals being disposed inside the plurality of the first electrode terminals in a plan view, the plurality of the second electrode terminals being used for ground potential supply to the first and second power amplifying systems, and the first and second electrode terminals comprising a land grid array structure; and (e) a via hole in which a conductor film is filled formed under the mount pad and inside the wiring substrate, and one of the second electrode terminals being coupled to the mount pad via the conductor film filled in the via hole.