Patent ID: 7476962

Claim:
A stack semiconductor package, comprising: a first semiconductor package including a first leadframe, a first semiconductor chip, first wires, and a first sealing resin, wherein a bottom surface of the first semiconductor chip is exposed from a lower surface of the first semiconductor package; and a second semiconductor package including a second semiconductor chip, second wires, and a second sealing resin, wherein the second semiconductor package is stacked on the first semiconductor package, the second semiconductor chip of the second semiconductor package being in contact with the first sealing resin of the first semiconductor package and the second sealing resin being molded together with the first sealing resin, the second semiconductor package combined with the first semiconductor package using the second sealing resin, wherein the second semiconductor package further includes a second leadframe vertically stacked on a portion of a surface of the first leadframe, wherein the first and second leadframes respectively comprise first leads coupled to the first and second semiconductor chips by first and second wires, respectively, and second leads coupled to the first leads and extending upwards such that the stacked semiconductor packages are electrically connected to each other, and wherein top surfaces of the second leads in the first leadframe are electrically connected to bottom surfaces of the first leads in the second leadframe.