Patent ID: 7298027

Claim:
A surface mount semiconductor die assembly comprising a lead frame and a first and second plurality of die to be interconnected to form a circuit; said lead frame comprising a thin, flat elongated pad for reception of a first plurality of die spaced along its length; second, third, and fourth pads laterally spaced from said first pad and coplanar therewith and in line with one another for receiving respective ones of a second plurality of die; and a thin elongated wire bond receiving pad disposed spaced from one edge of said first elongated pad and one edge of said second, third and fourth pads and coplanar therewith; said first and second plurality of die each having first and second power electrodes on their respective opposite surfaces, and including a gate electrode; said first power electrodes of said first plurality of die conductively mounted on said first pad with said first plurality of die in a generally straight row along the length of said first pad; said second power electrode of said die generally centrally conductively mounted on said second, third, and fourth pads respectively; said second power electrodes of said first plurality of die being wire bonded to said second, third and fourth pads respectively; said first power electrode of said second plurality of die being wire bonded to said thin wire bond receiving pad; and a first plurality of gate pins disposed spaced opposite from another edge of said first elongated pad opposite said one edge thereof, and a second plurality of gate pins each disposed spaced opposite another edge of a respective one of said second, third, and fourth pads opposite said one edge thereof; wherein each of said gate pins is disposed near a respective one of said die, said gate electrodes being electrically connected to said respective ones of said gate pins.