Patent ID: 8831029

Claim:
An apparatus comprising: a root complex fabric coupled to a plurality of integrated endpoint devices and a root port, the root port coupled to a Peripheral Component Interconnect Express (PCIe) device via an off-chip link, the root port and the PCIe device each including a transaction layer, a link layer and a physical layer; a virtual root port coupled to the root complex fabric and having a master interface to interface with the root complex fabric and a target interface to interface with an integrated device fabric; and the integrated device fabric coupled to the virtual root port via an on-chip link and including a multi-function logic to handle interrupts, power management messages, and non-function specific error messages, the integrated device fabric coupled to at least one agent and having a primary channel to communicate data and command information between the at least one agent and the virtual root port and a sideband channel to communicate sideband information between the at least one agent and the multi-function logic.