Patent ID: 8396913

Claim:
An apparatus for performing a fast fourier transform operation, the apparatus comprising: a plurality of first data processing elements, each being configured to receive input data and perform at least a portion of said fast fourier transform operation; a first data scheduler, connected to receive outputs from each of said plurality of first data processing elements; and at least one further fast fourier transform processor, comprising a plurality of second data processing elements; wherein the first data scheduler is configured to supply inputs to each of said plurality of second data processing elements of the further fast fourier transform processor from the outputs of each of said plurality of first data processing elements, wherein: each of said first data processing elements comprises a plurality of butterfly circuits and a corresponding plurality of multipliers for receiving the outputs from the butterfly circuits, and wherein said apparatus further comprises: a plurality of second data schedulers; and a plurality of second fast fourier transform processors, each connected to receive input signals from a respective one of said plurality of second data schedulers, wherein each of said first data processing elements is a radix 2 2 single path delay-feedback fast fourier transform processor, wherein at least one of said plurality of butterfly circuits comprises a pair of first and second butterfly means with a respective feedback path from an output of said butterfly means to an input thereof.