Patent ID: 8258040

Claim:
A method of manufacturing a semiconductor device, comprising: forming an element isolation groove in the semiconductor substrate by etching the semiconductor substrate so as to define a plurality of cell active regions in a cell region in the semiconductor substrate by the element isolation groove, and to define a dummy active region in the semiconductor substrate beside the cell region; forming an element isolation insulating film in the element isolation groove; etching the element isolation insulating film to lower an upper surface of the element isolation insulating film than the upper surface of the semiconductor substrate; forming a thermally-oxidized film on a side surface of the element isolation groove after the etching of the element isolation insulating film to make the thermally-oxidized film and the element isolation insulating film into a capacitor dielectric film; forming an upper electrode over the capacitor dielectric film and a gate electrode of a MOS transistor over the cell active region with a gate insulating film interposed therebetween, the upper electrode constituting a capacitor together with the capacitor dielectric film and the semiconductor substrate; and implanting an impurity into the semiconductor substrate of the cell active region beside the gate electrode and the dummy active region.