Patent ID: 8082410

Claim:
An address exclusive control system, comprising: a register, within a system controller, for retaining an address, a request type, an access destination and a cache block, the system controller enables accesses to plural central processing units (CPUs), an input/output apparatus and plural memory, wherein the system controller refers to a corresponding item of the register in accordance with the type of a new request, when the new request is received from one of the CPUs, the system controller searches whether or not an address exclusive control is in progress, on a basis of a busy address lock judgment function which compares an address, a CPU identifier or a cache block included in the new request with the address, a CPU identifier or the cache block retained in the register, respectively, the system controller carries out, if the address exclusive control is not in progress, the address exclusive control for another CPU in the CPUs, and the system controller issues the request to the another CPU.