Patent ID: 8906705

Claim:
A method for manufacturing a semiconductor device comprising steps of: (a) forming a plurality of semiconductor elements in chip area of a semiconductor substrate; (b) forming a lower interlayer insulating film covering said plurality of semiconductor elements on said semiconductor substrate; (c) forming a ferro-electric capacitor on said lower interlayer insulating film; (d) forming a multilayer interlayer insulating film covering said ferro-electric capacitor on said lower interlayer insulating film; (e) forming a wiring structure connected to said semiconductor elements and said ferro-electric capacitor and disposed in or on a surface of said lower interlayer insulating film and said multilayer interlayer insulating film; (f) forming pad electrode structure disposed in and on a surface of said multilayer insulating film and connected to said wiring structure; (g) forming a passivation film on said multilayer insulating film, said passivation film having an opening exposing said pad electrode structure; (h) performing an inspection by abutting a needle on said pad electrode structure; and (i) forming a conductive pad protection film including a Pd film, covering said pad electrode structure after inspection, via said opening of said passivation film, and extending on said passivation film.