Patent ID: 7020040

Claim:
A computer system, the computer system comprising: a processor for controlling operations of the computer system; a dynamic random access memory (DRAM) electrically connected to the processor for storing data; a south bridge chipset electrically connected to the processor and the DRAM, the south bridge chipset comprising: a system controller for controlling operations of the south bridge chipset; a buffer for temporarily storing the data; a memory controller for accessing the data in the DRAM; an integrated device electronics controller (IDE controller) for accessing data in an integrated device electronics (IDE) component; and a data conversion circuit electrically connected to the memory controller and the IDE controller for converting a hard-disk access command transmitted from the system controller to the IDE controller into a memory access command of the memory controller wherein the memory controller accesses the buffer and the DRAM by executing the memory access command; a power supply for generating a plurality of operating voltages to drive the computer system; and a battery device for generating the operating voltages that self-refresh the DRAM; wherein when the computer system performs a power supply management operation consistent with an advanced mode and an advanced configuration and power interface (ACPI) and enters a power-saving mode, the computer system can make use of the battery device to constantly self-refresh the DRAM for maintaining the data stored in the DRAM.