Patent ID: 8355088

Claim:
A method for manufacturing a thin film transistor array panel comprising: forming a gate line on a substrate, the gate line comprising a gate electrode; disposing a semiconductor and a data wire sequentially on the substrate; patterning the semiconductor and the data wire, wherein the data wire comprises a first data line, a second data line, a source electrode and a drain electrode, the second data line is spaced apart from the first data line, the drain electrode faces a part of the first data line and the second data line, and the source electrode is connected to one of the first data line and the second data line; forming an organic insulating layer on the first data line and the second data line, the organic insulating layer having a contact hole exposing the drain electrode; and forming a pixel electrode on the organic insulating layer, the pixel electrode electrically connected to the drain electrode; wherein the pixel electrode comprises a first part overlapping the first data line, and a second part overlapping the second data line, and wherein the width of the first part is different from that of the second part.