Patent ID: 7475225

Claim:
A computer implemented method for execution of micro-operations comprising: decoding a plurality of macro-instructions having a sequential instruction ordering into a plurality of micro-operations representing the sequential ordering; predicting whether the plurality of decoded micro-operations belong to one of two sets of micro-operations before the micro-operations are dispatched to execution resources for execution, the two sets comprising: a first set of producer micro-operations, including memory access micro-operations and other micro-operations that, when executed, each produce a result that is written into a register which will in turn be read and used by memory access micro-operations occurring later in the sequential ordering, but not including branch micro-operations; and a second set of consumer micro-operations, including branch micro-operations and micro-operations in the sequential instruction ordering not included in the first set of micro-operations; partitioning the plurality of micro-operations representing the sequential instruction ordering into the two sets based on the predicting; allocating to the first set of micro-operations execution resources from a first cluster of execution resources including execution resources to execute the micro-operations in the first set including memory access operations but not including execution resources to perform control branching operations; allocating to the second set of micro-operations execution resources from a second cluster of execution resources including execution resources to execute micro-operations in the second set including control branching operations but not including execution resources to perform memory access operations; executing the first and second sets of micro-operations out of said sequential order; and retiring the first and second sets of micro-operations to represent the sequential instruction ordering.