Patent ID: 7543132

Claim:
A single chip multithreaded processor comprising: a plurality of processor cores, wherein each core is configured to support processing of multiple threads by generating requests for data and instructions related to processing of said multiple threads and wherein said plurality of cores supports a plurality of virtual memory page sizes; a memory management unit configured to generate a plurality of miss requests related to the processing of data and instructions for said multiple threads, wherein each of said miss requests comprises a plurality of data parameters and wherein the plurality of data parameters comprises context information corresponding to a particular thread; priority logic configured to select a single miss request from said plurality of miss requests; hashing logic configured to receive and process said data parameters of said selected miss request and to generate a miss request index therefrom; and prediction array logic configured to process said miss request index thereby generating a predictor to be provided as an input to a prediction array to select a desired translation storage buffer, wherein said predictor corresponds to one of said plurality of virtual memory page sizes.