Patent ID: 8028265

Claim:
A computer-implemented method for generating an electronic circuit layout with placed circuit elements, comprising: receiving a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters; associating a plurality of first placement parameters with each of the plurality of circuit elements; wherein the first placement parameters comprise a cell horizontal position, a cell vertical stacking position, and a cell vertical adjacent spacing; retrieving, from a design library, design parameters associated with at least one of the plurality of circuit elements; assigning first absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters and the design parameters; selecting a subset of circuit elements; defining an adjustment operation to operate on the placement parameters of the selected subset of circuit elements; performing the adjustment operation on the placement parameters of the selected subset of circuit elements to generate adjusted placement parameters; assigning second absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters, the design parameters, and the adjusted placement parameters; and generating an electronic circuit layout with placed circuit elements based on the second absolute placement coordinates.