Patent ID: 7462906

Claim:
An integrated circuit structure comprising: a substrate; a flash memory cell at a top surface of a first region of the substrate, the flash memory cell comprising: a first gate oxide over the substrate; a poly silicon floating gate over the first gate oxide; a first thick oxide feature over the poly silicon floating gate, wherein the first thick oxide feature is an oxide of the poly silicon floating gate; and a control gate comprising a conductive material over the first thick oxide feature; a first source region and a first drain region on opposite sides of the first gate oxide; and a transistor at a top surface of a second region of the substrate, wherein the transistor is a high-voltage laterally diffused metal-oxide semiconductor (HV-LDMOS) device, the transistor comprising: a second gate oxide over the substrate; a second thick oxide feature over the substrate and adjoining the second gate oxide, wherein the second thick oxide feature is an oxide of the substrate; a transistor gate over the second gate oxide and the second thick oxide feature, wherein the transistor gate comprises substantially a same material, and has substantially a same thickness, as the control gate of the flash memory cell; and a second source region and a second drain region on opposite sides of the second gate oxide.