Patent ID: 7643325

Claim:
A ferroelectric memory, comprising: a plurality of normal memory cells each having a ferroelectric capacitor and storing data written via an external terminal; a nonvolatile decision memory unit storing decision data indicating whether data stored in said normal memory cells is true or false; an operation control circuit controlling a write operation, a read operation, and a rewrite operation on said normal memory cells and said decision memory unit, the rewrite operation being executed in a latter half of the read operation; an inversion control circuit outputting an inverting signal and setting the inverting signal to a valid level with a predetermined probability larger than 0 and smaller than 1 at least during said rewrite operation; a write circuit writing, at least during said rewrite operation, data having logic which is an inverse of logic of data to be rewritten to said normal memory cells and writing decision data indicating false to said decision memory unit when said inverting signal indicates a valid level, and writing data having logic to be rewritten to said normal memory cells and writing decision data indicating true to said decision memory unit when said inverting signal does not indicate a valid level; and a data restoration circuit inverting and outputting, during a read operation, logic of data read from said normal memory cells when decision data indicating false is read from said decision memory unit, and outputting data read from said normal memory cells when decision data indicating true is read from said decision memory unit.