Patent ID: 7519797

Claim:
A computing device configured for operation with an operating system that includes an application programming interface (API) for graphics processing, said computing device comprising: a first execution pipeline that includes a first stage; a second execution pipeline that includes a second stage and a third stage; a first event detector within the first execution pipeline for monitoring the first stage for a first specified event; a second event detector within the second execution pipeline for monitoring the second stage for the first specified event; a third event detector within the second execution pipeline for monitoring the third stage for a second specified event; a first m-bit counter that is incremented when the first event detector detects the first specified event at the first stage; a second m-bit counter that is incremented when the second event detector detects the first specified event at the second stage; a third n-bit counter that is incremented when the third event detector detects the second specified event at the third stage; and an n-bit accumulation counter configured to: receive a count value from the first m-bit counter, the second m-bit counter, and the third m-bit counter, add the received count value from the first counter and the second counter to a current count value associated with the first specified event, add the received count value from the third counter to a current count value associated with the second specified event, and report the current count value associated with the first specified event and the current count value associated with the second specified event in response to a request from the API, wherein n>m, the first m-bit counter is configured to transmit the count value into the first execution pipeline when the first m-bit counter has saturated, and the second m-bit counter is configured to transmit the count value into the second execution pipeline when the second m-bit counter has saturated.