Patent ID: 8615667

Claim:
A processor, comprising: a core configured to execute instruction codes; and a cache memory part including a plurality of ways and configured to store output data from the core and input data to the core, wherein the cache memory part is configured to store encrypted counter data in one way among the plurality of ways, the output data being encrypted with the encrypted counter data in a common key encryption system, the input data being decrypted with the encrypted counter data in the common key encryption system, wherein the cache memory part includes an operation circuit configured to perform an exclusive logical disjunction operation process between the encrypted counter data and at least one of the output data and the input data, and wherein a first operation mode and a second operation mode are switched in accordance with a setting, the encrypted counter data being stored in the one way of the cache memory part during the first operation mode, the one way being used as a cache configured to store the output data and the input data during the second operation mode.