Patent ID: 7848179

Claim:
An output enable signal generating circuit, comprising: a first count value generation unit that provides a first count value by counting from an initial count value corresponding to a CAS latency information, the counting being performed in response to an internal clock signal; a second count value generation unit that provides a second count value by counting in response to an external clock signal; an output enable signal generation unit that provides an output enable signal that is activated at each time that the second count value and the first count value become equal to each other comm., wherein the output enable signal veneration unit comprises a plurality of latches which sequentially latch the second count value in response to a plurality of control signals, respectively; and a control signal generation unit that provides the plurality of control signals in response to a plurality of read commands, wherein the control signal generation unit comprises: a plurality of shifters that each latch an output signal from a previous-stage shifter in response to a respective one of the plurality of read commands, and provide the output signal to a next-stage shifter; and a plurality of output portions that each provide one of the control signals in response to a respective one of the plurality of read commands and an output signal from a respective shifter.