Patent ID: 7941577

Claim:
A data processing system for performing a record operation, wherein the record operation allows a system image to record its memory addresses with a super-privileged resource, comprising: a bus system; a system image, which utilizes the bus system; and a hypervisor that utilizes the bus system, wherein the hypervisor receives a memory record request from the system image; translates a first memory address used by the system image into a second memory address used by one of a system processor and system input/output chips to access memory; locates a memory record entry in one of a plurality of address translation and protection tables used by the one of a system processor and system input/output chips to access host memory in response to determining that the second memory address is associated with the system image that issued the memory record request; creates a peripheral component interconnect bus address associated with the second memory address; records into the memory record entry of the one of the plurality of address translation and protection tables a memory translation required to convert the peripheral component interconnect bus address into the second memory address; records into the memory record entry of the one of the plurality of address translation and protection tables a bus number, device number, and function number associated with one of a plurality of peripheral component interconnect bus adapters that is associated with the peripheral component interconnect bus address and second memory address; returns the peripheral component interconnect bus address to the system image that issued the memory record request in response to determining that the record operation is successful; creates an indirect address translation and protection table that includes a plurality of entries, each one of the plurality of entries being referenced by a bus number, device number, and function number associated with one of the plurality of peripheral component interconnect bus adapters; includes, in each one of the plurality of entries in the indirect address translation and protection table, a pointer to one of the plurality of address translation and protection tables; receives an operation from a particular one of the plurality of peripheral component interconnect bus adapters; uses a bus number, device number, and function number associated with the particular one of the plurality of peripheral component interconnect bus adapters to locate a particular entry in the indirect address translation and protection table; and uses a particular pointer that is included in the located particular entry to identify a particular one of the plurality of address translation and protection tables.