Patent ID: 7335934

Claim:
An integrated circuit device disposed in or on a semiconductor layer which resides on or above an insulating layer of a substrate, the integrated circuit device comprising: memory section including a plurality of memory cells wherein each memory cell includes a transistor having: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate spaced apart from, and capacitively coupled to, the body region; and wherein each memory cell includes: a first data state which is representative of a first charge in the body region wherein the first charge is substantially provided by accumulating majority carriers in the body region; and a second data state which is representative of a second charge in the body region wherein the second charge is substantially provided by removing majority carriers from the body region; and a logic section including a plurality of transistors wherein each transistor includes: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the source, drain and body regions of an associated transistor are disposed in a segment of the semiconductor layer such that the body region includes a plurality of surfaces; and a gate spaced apart from and opposing the plurality of surfaces of the body region.