Patent ID: 7053434

Claim:
A ferroelectric memory device, comprising: first and second active regions defined by an isolation region in a substrate; first and second gate lines being selectively formed in the first and second active regions, respectively; first and second capacitors being separately formed on corresponding portions of the isolation region, each of said first and second capacitors having a lower electrode, an upper electrode and a ferroelectric layer formed therebetween, wherein the lower electrode of said first capacitor is coupled to said second gate line and the lower electrode of said second capacitor is coupled to said first gate line; first and second source/drain regions formed on both sides of said first and second gate lines, respectively, wherein one of said first source/drain region is coupled to the upper electrode of said first capacitor and one of said second source/drain regions is coupled to the upper electrode of said second capacitor; a first insulation layer being selectively formed on said first and second gate lines and said first and second source/drain regions, respectively; a second insulation layer being selectively formed on said upper electrodes; and first and second conductive line layers being coupled to the other first and second source/drain regions, respectively.