Patent ID: 6847088

Claim:
A non-volatile semiconductor memory device comprising: a semiconductor substrate; an impurity region and an element isolation region formed in the semiconductor substrate; and first and second memory elements mutually isolated by the element isolation region, the impurity region including a first impurity diffusion layer and a second impurity diffusion layer, the first memory element and the second memory element each including a gate dielectric layer, a floating gate, a selective oxide dielectric layer and a third impurity diffusion layer, also including a common intermediate dielectric layer and a common control gate, and being connected to the first and second impurity diffusion layers, the third impurity diffusion layer located in each of the first and second memory elements including a channel region, and an impurity concentration of the third impurity diffusion layer located in the first memory element being different from an impurity concentration of the third impurity diffusion layer located in the second memory element.