Patent ID: 7514322

Claim:
A method of forming a FET comprising: providing a semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region; performing a first silicon etch to form an upper trench portion extending into and terminating within the epitaxial layer; forming protective material extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion; performing a second silicon etch to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, the lower trench portion being narrower than the upper trench portion; and performing a two-pass angled implant of dopants of the first conductivity type to form a silicon region of first conductivity type along sidewalls of the lower trench portion, the protective material blocking the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.