Patent ID: 8503219

Claim:
An apparatus, comprising: an array of programmable resistance memory cells; a current source, said current source providing programming current in the form of a programming current pulse to a first memory cell of said array, said first memory cell comprising a phase-change material, said programming current pulse having a leading edge over which said programming current increases to a first current level over a first time window and a trailing edge over which said programming current decreases to a second current level over a second time window, said first current level initiating a structural change in said phase-change material; and a feedback control circuit configured to adjust said programming current pulse, said adjustment occurring in response to a current measured by said feedback control circuit in said array, said adjustment modifying said first current level, said first time window, said second current level, or said second time window; wherein said feedback control circuit is configured to adjust the rate of decrease of said programming current to said second current level during said second time window.