Patent ID: 7323773

Claim:
A semiconductor device comprising: (a) an interconnect substrate having first and second main surfaces on opposite sides; (b) a first semiconductor chip mounted on a side of the first main surface of said interconnect substrate and having a memory circuit; (c) a second semiconductor chip mounted on a side of the first main surface of said interconnect substrate and having a circuit controlling said memory circuit; and (d) a sealing body formed on a side of the first main surface of said interconnect substrate to seal the first and second semiconductor chips; wherein plural first terminals and plural second terminals are arranged on the first main surface of said interconnect substrate, plural terminals of said first semiconductor chip being electrically connected with the first terminals, plural terminals of said second semiconductor chip being electrically connected with the second terminals; wherein plural first external terminals and plural second external terminals are arranged on the second main surface of said interconnect substrate, the first external terminals being electrically connected with the second semiconductor chip via interconnects located inside said interconnect substrate, the second external terminals being electrically connected with plural interconnects located inside said interconnect substrate which electrically connect said first and second semiconductor chips; wherein said first external terminals are arranged in plural rows along an outer periphery of the second main surface of said interconnect substrate; wherein said second external terminals are arranged in an inner region located more inwardly than, and spaced from, the innermost row of the first external terminals by a distance equal to or greater than the spacing between adjacent rows of the first external terminals, and wherein said second semiconductor chip and said first semiconductor chip are stacked on top of each other.