Patent ID: 8426953

Claim:
A semiconductor package comprising: a planar leadframe having a first side and an opposite second side, said planar leadframe having a first plurality of conductive traces; at least two coplanar dies having first sides bonded to said first side of at least one of said first plurality of conductive traces on said planar leadframe, said at least two dies having second sides comprising a second plurality of solder bumps; another leadframe having a third plurality of conductive traces, at least one of said third plurality of conductive traces being attached to at least one die of said two dies on said second side thereof, and another of said third plurality of conductive traces attached to at least one of said first side of at least one of said first plurality of conductive traces on said planar leadframe; at least another die bonded to, and electrically insulated from, said another leadframe; a third plurality of wire bonds connecting said at least another die with said another leadframe; and encapsulating material molded to at least a portion of said planar leadframe, to said two coplanar dies, to said another leadframe, to said another die, and to said third plurality of wire bonds, with at least a fourth plurality of conductive traces on said second side of said planar leadframe being external electrical terminals of said semiconductor package.