Patent ID: 7795933

Claim:
A timing-signal generator, comprising: a PLL circuit for outputting M voltage controlled signals in response to a reference signal, wherein every adjacent two of the M voltage controlled signals have the same frequency and a first constant phase difference; a rising/falling edge generating unit coupled to the PLL circuit for receiving the M voltage controlled signals, and generating a rising point signal and a falling point signal corresponding to respective ones of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals; and a timing-signal generating unit coupled to the rising/falling edge generating unit for generating a timing signal which toggles high in response to the rising point signal and/or toggles low in response to the falling point signal; wherein the rising/falling edge generating unit includes a Jason counter coupled to the PLL circuit for receiving one of the M voltage controlled signals at a time and dividing the frequency F vco of the voltage controlled signal by P to output P counting signals, wherein P is a positive integer and every adjacent two of the P counting signals have the same frequency and a second constant phase difference.