Patent ID: 8633923

Claim:
A boost converter of a liquid crystal display, wherein a transistor performing a switching operation in response to a switching pulse causes a reactor to be driven to generate a panel driving voltage, the boost converter comprising: an oscillator configured to generate an oscillation signal having a frequency, which varies in a predetermined pattern or randomly hops around a center frequency, in synchronization with a synchronizing signal, the oscillation signal also having the same frequency whenever each frame begins; a controller configured to output a switching signal for generating a required panel driving voltage through use of the oscillation signal output from the oscillator, a voltage detected as the panel driving voltage, and a preset reference voltage; and a driver configured to perform the switching operation on the transistor, which drives the reactor generating the panel driving voltage, through use of the switching signal output from the controller, wherein the oscillator comprises: first and second current source sections configured to output a variable current; a counter section configured to count the synchronizing signal, and to vary an output current of the first and second current source sections through use of a counted value; a set-signal output section configured to change a charge voltage so as to correspond to the output current of the first current source section, to compare the changed charge voltage with a first reference voltage, and to generate a set signal according to a result of the comparison; a reset-signal output section configured to change a charge voltage so as to correspond to the output current of the second current source section, to compare the changed charge voltage with a second reference voltage, and to generate a reset signal according to a result of the comparison; and an SR latch configured to generate an output signal and an inverted output signal in the form of a square wave according to the set signal and the reset signal output from the set-signal output section and the reset-signal output section, respectively, and to control the output current of the first and second current source sections through use of the output signal and the inverted output signal, and wherein the counter section comprises: a pseudo-random bit generator configured to be reset by a vertical synchronizing signal whenever each frame begins, to output an n-bit switching control signal having a preset value, and then to count up/down a horizontal synchronizing signal or a data enable signal in a random pattern, thereby outputting an n-bit switching control signal, where n is a positive integer.