Patent ID: 7326975

Claim:
A buried channel type transistor comprising: a semiconductor substrate having a trench of a predetermined depth from a surface of the semiconductor substrate; a first threshold voltage control region having a first conduction type at a portion of the substrate beneath a bottom face of the trench; a second threshold voltage control region having the first conduction type at a portion of the substrate adjacent to a sidewall of the trench; a gate electrode filling the trench; source/drain regions at portions of the substrate adjacent to the sidewall of the gate electrode; and stopper regions beneath the source/drain regions and the first and second threshold voltage control regions, wherein each of the stopper regions has a second conduction type opposite to the first conduction type, wherein the stopper regions are spaced apart from each other by portions of the substrate and wherein a concentration of an impurity of the second conduction type within the stopper regions is greater than a concentration of an impurity of the second conduction type within the portions of the substrate.