Patent ID: 7919978

Claim:
An ODT control circuit, comprising: a mode identification signal generation unit for logically combining an ODT enable signal and a clock enable signal and outputting a mode identification signal; a clock control circuit which receives an internal clock signal and a DLL clock signal, and which selects either one of the internal clock signal or the DLL clock signal to output a plurality of delayed clock signals according to a power mode; and an ODT control signal generation circuit which receives an ODT command, and which controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal, wherein the clock control circuit includes: a DLL clock enable signal generation unit which combines the ODT enable signal and the mode identification signal to output a DLL clock enable signal; and an internal clock enable signal generation unit which combines the ODT enable signal and an inverted mode identification signal to generate an internal clock enable signal.