Patent ID: 8543735

Claim:
A data processing system comprising: a first data processor; a memory device provided in a part of an address space of the first data processor and coupled to an outside of the first data processor; and a second data processor coupled to an outside of the first data processor, wherein the first data processor includes: a first external interface circuit which controls access to the address space of the first data processor from the second data processor; and a second external interface circuit which controls access to the memory device, wherein the first external interface circuit includes: an external terminal arrangement for inputting, from the second data processor, a part of an address signal used to access the address space; a supplementary register in which supplementary information for supplementing an upper portion of an address information that has been input from the external terminal arrangement is written by the second data processor; a mode register in which mode information is written by the second data processor; and an address control circuit which generates an address signal to access the address space of the first data processor in a form based on information input from the external terminal arrangement, the supplementary register, and the mode register, and wherein the second data processor, after setting the mode register and the supplementary register, outputs address information to the external terminal to issue read access or write access.