Patent ID: 7176126

Claim:
A method of fabricating a dual damascene interconnection, comprising: (a) forming a lower interconnect feature on a substrate; (b) forming a dielectric layer on the lower interconnect feature; (c) forming a hard mask on the dielectric layer, wherein the hard mask is formed using BN, and the dielectric layer is formed using an oxide layer; (d) forming a via in the dielectric layer using the hard mask as an etch mask; (e) forming a trench hard mask defining a trench by patterning the hard mask; (f) forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask; (g) removing the trench hard mask using wet etch; and (h) forming an upper interconnection line by filling the trench and the via with an interconnection material.