Patent ID: 7576577

Claim:
A phase-locked loop device including a phase comparator having first and second inputs respectively receiving first and second clock signals and first and second outputs respectively delivering first and second logic signals, a symmetrical time-voltage conversion block comprising two structurally identical basic time-voltage converters each having an input respectively receiving the first and second logic signals and each having an output respectively delivering a first voltage and a second voltage as a function of the duration of the first and/or second logic signals, and a voltage processing block comprising a differentiator block having first and second inputs respectively receiving first and second voltages, the device further comprising: a first pair of switches and a second pair of switches opened/closed alternately in accordance with first and second phases, interleaved between the first and second outputs of the symmetrical time-voltage conversion block, and the first and second inputs of the voltage processing block, and a third pair of switches and a fourth pair of switches opened/closed alternately in accordance with the first and second phases, disposed on an upstream side of the first and second inputs of the phase comparator, wherein the differentiator block has a positive input and a negative input each connected to an output of an associated basic time-voltage converter via the first and second pairs of switches, and an output connected to an integrator block, the output delivering a signal representative of a voltage difference between the first and second logic signals, and control means for controlling opening/closing of the first to fourth pairs of switches in such a manner as to connect, during the first phase, the first clock signal to the first input of the comparator and the second clock signal to the second input of the comparator and the first output of the conversion block to the second input of the processing block and the second output of the conversion block to the first input of the processing block, and during the second phase, the first clock signal to the second input of the comparator and the second clock signal to the first input of the comparator and the first output of the conversion block to the first input of the processing block and the second output of the conversion block to the second input of the processing block.