Patent ID: 8557694

Claim:
A method for forming a triple gate of a semiconductor device, the method comprising: forming a buffer layer and a hard mask over a substrate; etching the hard mask and, the buffer layer to form a hard mask pattern and a buffer pattern; forming first and second trenches spaced apart within the substrate by partially etching the substrate by a vapor etching process using the hard mask pattern as an etching harrier layer; forming a passivation layer on inner surfaces of the first and second trenches; partially etching, by a first etching process, the hard mask pattern to align both sides of the hard mask patterns with both edges of the first and second trenches; subsequently partially etching, by a second etching process separate from the first etching process, the buffer pattern to align both sides of the buffer pattern with both edges of the first and second trenches; forming a buried insulation layer to fill the first and second trenches; removing the hard mask pattern and the buffer pattern; recessing a part of the buried insulation layer to partially expose sidewalls of the first and second trenches; forming a gate insulation layer directly contacting a top surface of the substrate and directly contacting the exposed sidewalls of the trenches between the first trench and the second trench, the substrate being exposed as result of removing the hard mask pattern and the buffer pattern; forming a gate electrode on the gate insulator layer which partially covers the buried insulation layer.