Patent ID: 6972222

Claim:
A method of forming a MOS transistor on a semiconductor substrate, comprising; (a) providing a substrate having isolation regions and an active region formed therebetween, said active region has a gate dielectric layer formed thereon and a gate electrode with two sides on the gate dielectric layer; (b) forming a temporary sidewall spacer on opposite sides of the gate electrode; (c) forming a temporary etch stop layer between an isolation region and an adjacent temporary sidewall spacer; (d) removing said temporary sidewall spacers and replacing with permanent sidewall spacers; (e) implanting impurity ions in said gate electrode, permanent sidewall spacers, etch stop layer, and in the substrate in the active region and performing a rapid thermal anneal (RTA) to activate shallow source/drain regions and deep source/drain regions in said active region, (f) removing the temporary etch stop layer to expose portions of the substrate; and (g) forming a metal silicide layer on the exposed portions of substrate, permanent sidewall spacers, and on the gate electrode.