Patent ID: 8076702

Claim:
An apparatus comprising: an epitaxial layer formed over a semiconductor substrate; a device isolation layer formed in the epitaxial layer defining an active area including a photodiode region and a transistor region, and a device isolation region; a gate insulating layer formed over the epitaxial layer of the transistor region; a gate electrode formed over the epitaxial layer of the transistor region including the gate insulating layer; a gate spacer formed on both sidewalls of the gate electrode and the gate insulating layer; n+ type source and drain regions formed in the epitaxial layer adjacent both sides of the gate spacer; at least one n+ type island region formed in the epitaxial layer adjacent the photodiode region and separated from the n+ type source region by the device isolation layer; an insulating interlayer formed over the epitaxial layer including the gate electrode and the gate spacer; a first contact hole extending through the insulating interlayer exposing the n+ type source region; a second contact hole extending through the insulating interlayer exposing the at least one island region; a first contact plug formed in the first contact hole and connected to the n+ type source region; a second contact plug formed in the second contact hole and connected to the at least one island region; a metal line formed over the first contact plug and the second contact plug to electrically connect the n+ type source region to the at least one island region; and an electrode protruding from the metal line and electrically connected to the second contact plug.