Patent ID: 8324033

Claim:
A method of manufacturing a thin film transistor (TFT) array substrate, comprising the following steps performed in the order presented: (a) forming stacked layers of a gate metal layer, a gate insulating layer, a semiconductor layer, and an ohmic contact layer sequentially on a substrate, and then patterning the stacked layers of the gate metal layer, the gate insulating layer, the semiconductor layer, and the ohmic contact layer to form a pattern of a gate line and a gate electrode; (b) forming an insulating layer on the resulting substrate of step (a), a thickness of which is greater than a total thickness of the gate metal layer, the gate insulating layer, the semiconductor layer, and the ohmic contact layer, and thinning the insulating layer partially to expose the ohmic contact layer; (c) forming and patterning a source/drain metal layer on the resulting substrate of step (b) to form first and second source/drain electrodes and a data line and to expose the ohmic contact layer between the first and second source/drain electrodes, and patterning the exposed ohmic contact layer to form a trench that divides the ohmic contact layer, the first and second source/drain electrodes opposing to each other with respect to the trench; (d) forming and patterning a passivation layer on the resulting substrate to form a via hole in the passivation layer over the second source/drain electrode; and (e) forming and patterning a pixel electrode layer on the resulting substrate to form a pixel electrode that is connected with the second source/drain electrode through the via hole.