Patent ID: 7660928

Claim:
An arbitration circuit comprising: latch control means which outputs a latch signal of a predetermined pulse width when the occurrence of a first or second request signal is detected; first holding means which is set by the input of the first request signal and reset when an operation required by the first request signal is completed; first latch means which fetches therein a state of the first holding means while the latch signal is being outputted and outputs the fetched state when the latch signal is stopped; first gate means which outputs a first enable signal in a set state of an output signal of the first latch means and when a delay enable signal is unsupplied; second holding means which is set by the input of the second request signal and reset when an operation required by the second request signal is completed; second latch means which fetches therein a state of the second holding means while the latch signal is being outputted and outputs the fetched state when the latch signal is stopped; second gate means which outputs a second enable signal in a set state of an output signal of the second latch means and when the first enable signal is not outputted; and delay means which delays the second enable signal and supplies the delayed second enable signal to the first gate means as the delay enable signal.