Patent ID: 8566772

Claim:
A tangible non-transitory computer system for optimizing an architectural model of a microprocessor, the computer system comprising: a tangible non-transitory computer-readable medium, a computer program being embodied in said computer-readable medium, wherein said computer program configures the computer system to execute the steps of: representing an instruction set of said microprocessor as a graph by configuring elements of said instruction set as a plurality of nodes of said graph; determining whether said plurality of nodes with identical bit position and value encoding is present in said graph; when said plurality of nodes with the identical bit position and value encoding is present, separating a path from a source node to a target node into a common node for each node in said graph and reusing the common node to optimize common paths out of said graph; directly connecting said source node to the common node in said graph using a forward edge; adding a back-edge from the common node to said source node through said target node and recursively repeating the above steps until all the nodes of said graph are processed; and creating a new node in said graph when said plurality of nodes with the identical bit position and value encoding is not present in said graph.