Patent ID: 6850580

Claim:
A bit synchronizing circuit for use in a reception circuit in serial communication, comprising: a data sampling circuit for over-sampling bit data at a sampling rate faster than a bit rate and outputting in parallel sampled bit data at a slower rate than the sampling rate; a change point detecting circuit for detecting rising and falling edges of the bit data based on the bit data outputted in parallel from the data sampling circuit; a selected value setting circuit for determining based on a change point outputted from the change point detecting circuit, which piece of the data of the data sampling circuit to be selected; and a data selecting circuit, in response to an output from the selected value setting circuit, for carrying out selection of the bit data from the data sampling circuit, the bit synchronizing circuit further comprising: a change point holding circuit for holding the change point outputted from the change point detecting circuit, and changing the held change point stepwise, data outputted from the change point holding circuit being inputted to the selected value setting circuit.