Patent ID: 7376885

Claim:
An apparatus for performing Low Density Parity Check (LDPC) decoding operations, comprising: means for receiving a control signal; storage means including a plurality of state storage elements, each state storage element corresponding to a check node and including a first and a second location for storing message magnitude values corresponding to messages directed to the check node to which said state storage element corresponds, each state storage element further including a sign memory location for storing an accumulated sign value; ii) check node processor means for updating state stored in said storage means based on the content of a received variable node to check node state message to be processed; and iii) control means, coupled to said check node state memory, for controlling said storage means to output check node state, corresponding to the same check node as the received variable node to check node message to be processed, said check node state being output from the one of said state storage elements which corresponds to the same node as said received variable to check node message to be processed, said control means operating as a function of said control signal.