Patent ID: 7451171

Claim:
In a processor having a pipeline, a method for providing hardware assists for microcoded floating point divide and square root operations, the method consisting of: receiving a first microcoded instruction in the pipeline; decoding the first microcoded instruction in a decode stage of the pipeline; flushing subsequent instructions already in the pipeline; initiating a microcode engine coupled to the processor, the microcode engine configured to process the microcode routine; for a 6-cycle period after receiving the microcoded instruction in the pipeline, performing in the instruction's pipeline slot of the pipeline: if an operand associated with the microcode routine is de-normalized, pre-normalizing the operand and writing the pre-normalized operand to a scratch register coupled to the processor; if an operand being a normalized number, copying the operand into the scratch register; determining whether operands associated with the instruction are a-typical and not dealt with by the streamlined microcode routine; wherein the pipeline slot reserved for microcode instructions is used to perform processing selected from the group consisting of: (for divide); de-normalized divisor (implicit bit=0, ie fraction=0.XXX . . . X); either operand is an SNaN (Signaling Not a Number); either operand is a QNaN (Quiet Not a Number); normalized/0; 0/0; Inf/Inf; 0/X; X/Inf; Inf/X; (for square root); de-normalized operand; operand is an SNaN; operand is a QNaN; Sqrt(<0); Sqrt(−0); Sqrt(0); and Sqrt(Inf); and producing a final result and copying the result from the scratch register to a floating point architectural register associated with the processor.