Patent ID: 8135104

Claim:
A serial transceiver, comprising: a transmitter which receives parallel data to be transmitted to encode the received parallel data as transmission data including DC (direct current) balancing information and includes a serial transmission unit for performing serial transmission on data encoded according to a communication clock of an internal PLL (phase locked loop) operating based on an externally provided clock; and a receiver which includes a clock recovery unit including a frequency detector and a linear phase detector for receiving the encoded data from the transmitter and performing sequential synchronization by using the received encoded data and an output of a voltage controlled oscillator, a parallelizer for converting the received serial data into parallel data by using clocks of a plurality of stages generated by the voltage controller oscillator from the clock recovery unit, a start bit detector for detecting a start bit by comparing data in the output of the parallelizer through a logic circuit, and a decoder for decoding and outputting the output of the parallelizer, wherein the frequency detector comprises: a divider dividing, during a delay time, each clock of the plurality of stages generated by the voltage controlled oscillator according to a rate of the received data and outputting the divided signals; a serial data delayer for delaying the serial data by the amount of said delay time, and outputting a signal of the delayed serial data; one or more synchronization detectors comparing an output of the delayer to one of the outputs of the divider to detect synchronization and providing a result of the comparison as a synchronization signal; and a frequency controller which outputs a frequency down signal to continuously decrease the frequency of a periodic pulse signal, which is the output of the divider, when the output of the delayer and the periodic pulse signal are different, wherein the frequency controller generates and maintains the frequency down signal to be “0”, in a case when two synchronization detectors are used, both of the two synchronization detectors detect a lock condition, wherein the lock condition is detected when the frequency of the output of the delayer and the frequency of the periodic pulse signal are in synchronization with each other.