Patent ID: 7706996

Claim:
A circuit comprising: control circuitry having a first output; a plurality of output channels, each output channel including: an output timing device having a data input coupled with the first output of the control circuitry; one or more channel delays, each having an input coupled with the output timing device and having an output coupled with an output pad; and a calibration timing device having a data input coupled with the channel delays and having an output coupled with the control circuitry; and a clock path including: a first node that receives a clock signal and that is coupled with a clock input of each output timing device; one or more clock delays, each having an input coupled with the first node and an output coupled with a clock input of each calibration timing device, wherein the channel delays and the clock delays are programmable via one or more delay control signals from the control circuitry; wherein the control circuitry is adapted to: transmit a first test signal via the first output to the data input of each output timing device; determine, for each output channel, a relative timing between a first channel signal at the data input of the calibration timing device and a clock signal at the clock input of the calibration timing device, wherein the relative timing is based on the output of the calibration timing device; and align a first edge of the first channel signals by adjusting at least one of the delays.