Patent ID: 8446783

Claim:
An apparatus comprising: a first plurality of row address register units, wherein a count of the first plurality of row address register units corresponds to a count of rows that are expected to have at least one memory cell unable to retain data, each of the first plurality of row address register units configured to store a row address corresponding to a respective row containing at least one memory cell unable to retain data; a second plurality of row address register units, wherein a count of the second plurality of row address register units corresponds to a count of the first plurality of row address register units, each of the second plurality of row address register units operable to store a subset of bits of the row address stored in a respective first plurality of row address register units; and a plurality of comparator units, each of the comparator units configured to receive a refresh row address and respectively coupled to a corresponding row address register unit of the first plurality of row address register units and a corresponding row address register unit of the second plurality of row address register units, each of the plurality of comparator units operable to compare the received refresh row address to the row address bits stored in the corresponding row address unit of the first plurality of row address register units and to the subset of bits stored in the corresponding row address unit of the second plurality of row address register units and generate a high match signal in the event of a match.