Patent ID: 7514960

Claim:
A level shifter circuit comprising: a first transistor configured to be activated in response to a logic signal whose high level voltage is a first voltage to be shifted; a second transistor configured to be activated in response to an inverse logic signal whose logic is opposite to that of said logic signal; a third transistor connected to a drain of said first transistor through a first node; a fourth transistor connected to a drain of said second transistor through a second node; a resistive element connected between said first node and said second node; and a power down terminal to which a power down signal is supplied, wherein said first transistor is connected between a power supply line and a ground line by way of said third transistor, said power supply line supplying a second voltage different from said first voltage, said second transistor is connected between said power supply line and said ground line by way of said fourth transistor, a gate of said third transistor is connected to said drain of said second transistor through said second node, a gate of said fourth transistor is connected to said drain of said first transistor through said first node, and the resistive element is deactivated in response to said power down signal applied.