Patent ID: 7704803

Claim:
A method for manufacturing a semiconductor device that includes a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films; and memory cells formed at intersections of the gate insulating films and the word lines, the method comprising the steps of: (a) forming the plurality of bit line diffusion layers each extending in the row direction in the upper portion of the semiconductor region; (b) forming the bit line insulating films on the plurality of bit line diffusion layers; (c) forming the plurality of word lines each extending in the column direction on the semiconductor region so as to intersect with each of the bit line diffusion layers and each of the bit line insulating films; (d) forming exposed regions for exposing respective ones of end portions of the bit line diffusion layers by removing regions of the bit line insulating films from end portions thereof to a word line close to the respective one end portions thereof, the region including at least the respective one end portions of the bit line diffusion layers; and (e) forming connection parts in regions including the exposed regions and connection diffusion layers electrically connected to the bit line diffusion layers through the connection parts by selectively forming, in the semiconductor region, a plurality of diffusion layers each extending in the row direction of the semiconductor region.