Patent ID: 7624320

Claim:
A system-on-chip (SoC) test apparatus including a plurality of Intellectual Property (IP) cores, the apparatus comprising: a Test Interface Controller (TIC) module for receiving scan input data via a two-way data bus connected to an external part during a scan test mode, applying the scan input data to an Intellectual Property (IP) core via a bus, and creating an output data read signal; a signal creation module for receiving a scan test mode signal received for the scan test mode and the output data read signal, and creating a scan output read signal using the received scan test mode signal and the received output data read signal; an External Bus Interface (EBI) module for reading scan output data from the IP core according to the scan output read signal, and outputting the read scan output data; a multiplexer for transmitting the scan output data and an output address to the external part according to the scan test mode signal; a bridge for delaying the scan data received from the TIC module via an Advanced High-performance Bus (AHB) when the IP core is determined to be an Advanced Peripheral Bus (APB) core connected to an Advanced Peripheral Bus (APB), and generating the delayed scan data as APB scan data, converting the APB output data received from the APB core into output data at intervals of a predetermined time, and outputting the converted result; an Advanced Peripheral Bus (APB) input multiplexer for selecting the scan data from among the scan data and the APB scan data, and applying the selected scan data to the APB core; and an Advanced Peripheral Bus (APB) output multiplexer for selecting the APB output data from among the APB output data and the output data according to the scan test mode signal, and transmitting the selected APB output data to the AHB.