Patent ID: 7026249

Claim:
A method of fabricating a SiGe-on-insulator substrate having selected parameters, said method comprising the steps of: providing an initial SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters has or have an adjustable value, and wherein the parameters of said initial SiGe-on-insulator substrate are selected using the following equations: f m ′ ⁢ ⁢ ( % ) = f m ⁢ ⁢ ( % ) -  ɛ res  with f m ⁢ ⁢ ( % ) = 4.17 ⁢ x ⁢ ⁢ or ⁢ f m ⁢ ⁢ ( % ) = ( ( 0.19836 ) ⁢ x + ( 0.03265 ) ⁢ x 2 - ( 0.00436 ) ⁢ x 3 5.43105 ) × 100 and ɛ res ⁢ ⁢ ( % ) = b ⁡ ( 1 - v 4 ) 4 ⁢ π ⁡ ( 1 + v ) ⁢ h ⁢ ln ⁡ ( 2 ⁢ h b ) × 100 ⁢ ⁢ or ⁢ ⁢ ɛ res ⁢ ⁢ ( % ) = 2290.4 h 1.4267 where f m ′ is the in-plane lattice parameter of a relaxed, thermodynamically stable SiGe alloy layer, given in percent larger than an unstrained Si in-plane lattice parameter, f m is the mismatch strain corresponding to an unrelaxed SiGe alloy, x is the Ge content of the SiGe alloy layer in terms of atomic fraction in the expression Si 1-x Ge x , ε res is the residual strain in the SiGe alloy layer, b is the 60° dislocation Burgers vector (3.84 Å), v is the value of the Poisson ratio of the SiGe alloy layer (0.275) and h is the SiGe alloy layer thickness; and adjusting one or both of the other parameters to a final selected value, while maintaining the selected in-plane lattice parameter, said adjusting comprises a non-selective etching process or a thermal dilution process.