Patent ID: 7352025

Claim:
An integrated circuit semiconductor memory device provided with a semiconductor fin comprising: a substrate; a first dielectric layer covering a first portion of said substrate, said first dielectric layer being absent from a second portion of said substrate; a second dielectric layer having a property different from said first dielectric layer, said second dielectric layer at least partly covering said second portion of said substrate; a source region formed in a first doped region on said first dielectric layer; a drain region formed in a second doped region on said first dielectric layer; and a gate formed over said second dielectric layer and between said first and second doped regions, wherein said substrate has an upwardly facing first surface at an upper level and an upwardly facing second surface at a lower level, said first dielectric layer being a dielectric layer formed on said first surface, said second dielectric layer being a dielectric layer formed on said second surface, and said fin being formed over said first dielectric layer.