Patent ID: 7203050

Claim:
An electrostatic discharge protection circuit comprising: an npn Darlington circuit comprising an input end and an output end; and an N-type channel metal-oxide semiconductor (NMOS) transistor, a drain of the NMOS transistor connected to the input end of the npn Darlington circuit, a source of the NMOS transistor connected to a control end of the npn Darlington circuit, a gate of the NMOS transistor connected to the output end of the npn Darlington circuit; wherein the npn Darlington circuit further comprises two npn-type bipolar junction transistors (BJTs), each npn BJT comprising an N+ buried layer, a P well formed on the N+ buried layer, an N well formed on the N+ buried layer around the P well, and an N+ node formed in a top side of the P well; and the NMOS transistor comprises an N+ buried layer, a P well formed on the N+ buried layer, an N well formed on the N+ buried layer around the P well, and two N+ nodes formed in a top side of the P well; the two BJTs and the NMOS transistor are formed on a P-substrate, and the N wells of the two npn BJTs and the NMOS transistor are used to isolate the P wells and the P-substrate; and further comprising a P-epi layer formed on the P-substrate, and wherein the N wells of the two npn BJTs and the NMOS transistor are formed on the P-epi layer.