Patent ID: 8373478

Claim:
A semiconductor device, comprising: a first phase detector configured to detect a phase of a second clock by comparing the phase of the second clock with a phase of a first clock; a second phase detector configured to detect a phase of a clock obtained by delaying the second clock by a delay amount by comparing the phase of the delayed second clock with the phase of the first clock; a third phase detector configured to detect the phase of the second clock by comparing the phase of the second clock with a phase of a clock obtained by delaying the first clock by the delay amount; and a phase difference detection signal generator configured to set a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks in response to signals respectively outputted from the first to third phase detectors, detect that the phase of the first or second clock is changed by a phase corresponding an amount two times greater than the delay amount, and change the logic level of the phase difference detection signal in response to the detected result.