Patent ID: 8321760

Claim:
A semiconductor memory device comprising: a nonvolatile memory including a memory cell array of multi-level cells (MLCs), each MLC being configured to store data according to a plurality of data states including; an erase state indicated by a threshold voltage in a first threshold voltage distribution, a first program state indicated by a threshold voltage in a second threshold voltage distribution greater than the first threshold voltage distribution, a second program state indicated by a threshold voltage in a third threshold voltage distribution greater than the second threshold voltage distribution, and a third program state indicated by a threshold voltage in a fourth threshold voltage distribution greater than the third threshold voltage distribution; and a memory controller configured to perform a data rearrangement operation and an error correction code (ECC) operation for write data having an initial data arrangement and to be stored in the nonvolatile memory, wherein the data rearrangement operation rearranges the initial data arrangement to generate a new arrangement for the write data such that data in the write data having the erase state and data in the write data having the third program state are not stored in adjacent memory cells.