Patent ID: 7536694

Claim:
A method of code execution in a system having first and second processors, comprising: storing a first programmable address in a first data structure; said first processor encountering a first exception; said first processor jumping to execute a first exception handler code at a first predetermined address; said first processor executing said first exception handler code at said first predetermined address, wherein said first instruction handler code directs said first processor to read said first programmable address at said first data structure; said first processor jumping to execute a second exception handler code at a second address as a function of said first programmable address read from said first data structure; said first processor executing said second exception handler code to handle said first exception; storing a second programmable address in a second data structure; said second processor encountering a second exception; said second processor jumping to execute said first exception handler code at said first predetermined address; said second processor executing said first exception handler code at said first predetermined address, wherein said first instruction handler code directs said second processor to read said second programmable address at said second data structure; said second processor jumping to execute a third exception handler code at a third address as a function of said second programmable address read from said second data structure; said second processor executing said third exception handler code to handle said second exception; and adding said first programmable address read from said first data structure as an offset to a base address to calculate said second address, and adding said second programmable address read from said second data structure as an offset to a base address to calculate said third address.