Patent ID: 7056782

Claim:
A process for fabricating a complementary metal oxide semiconductor (CMOS) structure comprising: providing a plurality of polySi gates overlying a semiconductor substrate, each polySi gate comprises a dielectric cap located on an upper surface thereof; wherein said dielectric cap comprises a first dielectric material; forming silicided source/drain regions in the semiconductor substrate; forming a dielectric stack on the semiconductor substrate; wherein said dielectric stark comprises a first lower dielectric layer and a second, upper dielectric layer, wherein the first, lower dielectric layer comprises the first dielectric material, and wherein the second, upper dielectric layer comprises a second, different dielectric material; planarizing the dielectric stark to remove an upper portion of the second, upper dielectric layer; performing an etching process to selectively remove the first, lower dielectric layer and the dielectric cap gainst the second, upper dieleetric layer to thereby epose only an upper surface of each polySi gate, wherein the exposed upper surface of each polySi gate is below an upper surface of the second, upper dielectric layer; and performing a salicide process which converts each polySi gate to a metal silicide gate, wherein each metal silicide gate has substantially the same height, is composed of the same silicide phase, and has substantially the same workfunction for the same polySi ion implant conditions.