Patent ID: 7610569

Claim:
A chip design verification apparatus for verifying a target unit including at least one hardware block, the chip design verification apparatus comprising: a computer including at least one software block in data communication with the at least one hardware block, and which verifies an operation between the at least one hardware block and the at least one software block, the computer comprising: an interface means of transmitting output data of the hardware block, determining whether output data of the software block which comprises a system clock count value of a chip design verification program when the output value of the software block is changed is valid, and applying only valid output data of the software block to the hardware block; a storage means of storing the at least one software block and the chip design verification program for verifying the at least one software block; and a controller for transmitting the output data of the software block generated by an operation of executing the chip design verification program to the interface means, determining whether the output data of the at least one hardware block input via the interface means is valid, and applying only valid output data of the at least one hardware block to the at least one software block.