Patent ID: 8623724

Claim:
A method of manufacturing a semiconductor device, comprising: preparing a substrate having a first region and a second region; forming a pillar protruding upwardly from the substrate in the first region; forming a first transistor having an impurity region in an upper portion of the pillar; forming a second transistor in the second region of the substrate; forming an insulation interlayer pattern on the first region and the second region to cover the second transistor in the second region and expose an upper surface of the pillar in the first region through an opening in the insulation interlayer pattern, the insulation interlayer pattern having an upper surface in the second region which is substantially higher than an upper surface of the impurity region in the upper portion of the pillar in the first region; and forming a capacitor which is electrically connected to the impurity region of the first transistor in the first region of the substrate, wherein the forming of the capacitor comprises: forming a lower electrode directly contacting the impurity region in the upper portion of the pillar exposed by the insulation interlayer pattern; forming a dielectric layer on an entire outer surface of the lower electrode; and forming an upper electrode on the dielectric layer, wherein the upper surface of the insulation interlayer pattern in the second region is substantially higher than a lower surface of the lower electrode of the capacitor.