Patent ID: 8828827

Claim:
A manufacturing method of anti punch-through leakage current MOS transistor, comprising: providing a second type substrate; forming a high voltage deep first type well region in the second type substrate; forming a first type light doping region in the high voltage deep first type well region in the second type substrate to form a drain structure, a doping concentration of a first type dopant of the first type light doping region is greater than a doping concentration of the first type dopant of the high voltage deep first type well region; forming a mask with a dopant implanting opening on the second type substrate; forming an anti punch-through leakage current structure in the high voltage deep first type well region by implanting the first type dopant through the dopant implanting opening, a doping concentration of the first type dopant of the anti punch-through leakage current structure being greater than a doping concentration of the first type dopant of the high voltage deep first type well region; forming a second type body by implanting a second type dopant through the dopant implanting opening so as to form a source structure and a body structure, a location of the anti punch-through leakage current structure being deeper than a location of the second type body, the second type body and the second type substrate are separated by the high voltage deep first type well region and the anti punch-through leakage current structure; and forming a gate structure on the second type substrate, the gate structure connecting between the second type body and the first type light doping region.