Patent ID: 7728374

Claim:
An embedded memory device, comprising: a core circuit surrounded by a grounding ring and a power source ring; a metal-oxide-semiconductor (MOS) capacitor located below the power source ring and the grounding ring of the core circuit, said MOS capacitor being electrically connected with the power source ring and the grounding ring, wherein the MOS capacitor is coupled in parallel with the core circuit, and wherein the MOS capacitor is composed of an ion distributing layer, a polysilicon layer, and a metal layer, and is located on an additional space below the power source ring and the grounding ring; and a metal-insulator-metal (MIM) capacitor located above the core circuit, said MIM capacitor being connected with the power source ring and the grounding ring, wherein the MIM capacitor is coupled in parallel with the core circuit and the MOS capacitor; wherein the stability of the power source is enhanced by utilizing the MOS capacitor and the MIM capacitor.