Patent ID: 7927934

Claim:
A method comprising: providing a substrate; providing an insulating layer overlying the substrate; providing a body region comprising a body material overlying the insulating layer; forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region; and forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source; forming a second transistor having a source, a drain and a gate and being electrically isolated from the at least one transistor, the second transistor having silicide regions formed in the source, the drain and the gate; and forming the first silicide region and second silicide region of the at least one transistor and the silicide regions of the second transistor by angled ion implanting the source, drain and gate of the at least one transistor with a first ion implant comprising germanium while masking the second transistor, and angled ion implanting the source, drain and gate of the second transistor with a second ion implant while masking the first transistor.