Patent ID: 7598570

Claim:
An SRAM comprising: an SOI substrate comprising a structure where a semiconductor support substrate, a buried insulating film and an SOI layer are layered in this order; an access transistor which is formed in said SOI layer and has a first active region that is formed in a surface of said SOI layer; a first insulating film that is formed beside one side of said first active region from the surface of said SOI layer to said buried insulating film; a second insulating film that is formed beside the other side of said first active region, which is opposite to said one side, from the surface of said SOI layer to a predetermined depth that does not reach said buried insulating film; a first conductor that is provided on said first active region toward a side where said first insulating film exists, off a center of said first active region in a plan view, said first conductor contacting said first insulating film; a first load transistor which is formed in said SOI layer and has a second active region that is formed in the surface of said SOI layer; a third insulating film that is formed beside one side of said second active region from the surface of said SOI layer to said buried insulating film; a fourth insulating film that is formed beside the other side of said second active region, which is opposite to said one side, from the surface of said SOI layer to a predetermined depth that does not reach said buried insulating film; and a second conductor that is provided on said second active region toward a side where said third insulating film exists, off a center of said second active region in a plan view.