Patent ID: 7506207

Claim:
A processor that performs operations specified by instructions fetched from a memory, the processor comprising: means for maintaining a plurality of register fields for indicating one or more conditions, statuses, and/or modes that are present within the processor; means for fetching instructions from memory; means for executing an instruction within the processor; means for receiving a plurality of types of interruptions; means for indicating whether the trap mode is active or inactive using a trap mode field within the processor, wherein a first trap mode field indicates that a single-step trap mode is active and wherein a second trap mode field indicates that a taken-branch trap mode is active; means for determining whether a trap mode is to remain active during interruption processing in response to receiving an interruption; means for deactivating a trap mode in response to a determination that the trap mode is to be deactivated during interruption processing; and means for invoking an interruption handler to perform interruption processing for a received interruption.