Patent ID: 8299821

Claim:
An integrated gate driver circuit, receiving a plurality of clock signals and comprising a plurality of cascaded drive units, each drive unit comprising: an input terminal; an output terminal; an output drive circuit, comprising: a first switch, comprising a control terminal receiving a first clock signal, a first terminal coupled to the input terminal, and a second terminal coupled to a first node; a second switch, comprising a control terminal coupled to the first node, a first terminal receiving a second clock signal, and a second terminal coupled to the output terminal; and a third switch, comprising a control terminal receiving the first clock signal, a first terminal coupled to the output terminal, and a second terminal coupled to a first voltage; and a first voltage stabilizing circuit, comprising: a fourth switch, comprising a first terminal coupled to a second voltage, a second terminal coupled to a second node, and a control terminal coupled to the first terminal of the fourth switch; a fifth switch, comprising a first terminal coupled to the second node, a second terminal coupled to the first voltage, and a control terminal coupled to the output terminal; and a sixth switch, comprising a first terminal coupled to the output terminal, a second terminal coupled to the first voltage, and a control terminal coupled to the second node.