Patent ID: 8035417

Claim:
An apparatus, comprising: a plurality of output buffer circuits coupled in parallel to provide a combined output drive strength, each output buffer circuit of the plurality of output buffer circuits including: a buffer data input receiving a data input signal shared across the plurality of output buffer circuits; a first buffer enable input receiving a first buffer enable signal shared across the plurality of output buffer circuits; a second buffer enable input receiving a second buffer enable signal customized across the plurality of output buffer circuits; a buffer data output providing a data output signal having a drive strength, wherein the data output signal is combined across the plurality of output buffer circuits to provide a combined data output signal having the combined output drive strength, and the combined output drive strength is tuned by the second buffer enable signals customized across the plurality of output buffer circuits, wherein buffer enable signals are received together with complements of the buffer enable signals, and the buffer enable signals and the complements of the buffer enable signals control pairs of transistors having opposite conductivity types, and the buffer enable signals include the first buffer enable signal and the second buffer enable signal.