Patent ID: 7382038

Claim:
A semiconductor wafer, comprising: a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing; a plurality of wafer acceptance testing pads in the dicing line, said wafer acceptance testing pad comprising a plurality of dielectric layers; and a reinforcing structure disposed in said wafer acceptance testing pads, said reinforcing structure comprising a plurality of damascened metal blocking structures in the dielectric layers disposed along at least one side of each said wafer acceptance testing pad for stopping propagation of dielectric de-lamination originating from the mechanical wafer dicing, wherein the bottom of a first damascened metal blocking structure is embedded into an upper dielectric layer and the bottom of a second damascened metal blocking structure is embedded into an underlying dielectric layer of the upper dielectric layer.