Patent ID: 7590787

Claim:
A microprocessor, for dynamically specifying a data transaction burst order for a burst transfer, the microprocessor comprising: a cache memory; and bus interface logic, interfaced with request signals and data signals on a system bus, comprising: a request interface which provides a request via said request signals for a data transaction, wherein said request signals provide for specification of a plurality of burst orders for the burst transfer, and wherein said request specifies one of said plurality of burst orders, and wherein said request interface specifies said one of said plurality of burst orders by configuring a field of a request packet during a request phase of said data transaction, said request interface comprising: one or more machine specific registers to enable configuration of a custom order table; and a response interface, coupled to said cache memory, which stores data for the burst transfer received via said data signals into said cache memory according to said one of said plurality of burst orders; wherein said one of said plurality of burst orders is selected from an interleaved order, a linear order, a nibble linear order, and a custom order, and wherein said custom order is programmed into said custom order table during initialization of the microprocessor.