Patent ID: 8030981

Claim:
A semiconductor device comprising: an internal clock signal generating block configured to generate a delay control signal by detecting a phase difference between a reference clock signal and a feedback clock signal and generate an internal clock signal and the feedback clock signal; a latency signal generating block configured to receive locking completion information of the internal clock signal generation block, receive a column address strobe (CAS) latency value, generate a latency signal by synchronizing a read command signal with the internal clock signal, and calculate a measure delay value, wherein the latency signal is activated at a time determined in response to the CAS latency value and the measured delay value and, in response to the locking completion information, the measured delay value is calculated based on a phase difference between the reference clock signal and the feedback clock signal; and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.