Patent ID: 8035429

Claim:
A semiconductor device, comprising: a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals, respectively, by mixing phases of first and second source clock signals having an identical frequency; a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction; a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction; and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data, wherein the first source clock signal is applied to the synchronization clock generators in the forward direction through the first clock transmission path and the second source clock signal is applied to the synchronization clock generators in the backward direction through the second clock transmission path in that the first source clock signal is sequentially applied to the synchronization clock generators in a first order of the synchronization clock generators, the second source clock signal is sequentially applied to the synchronization clock generators in an opposite order of the synchronization clock generators from the first order, the first order is from first to n-th synchronization clock generators, and n is a natural number.