Patent ID: 8405670

Claim:
A circuit arrangement, comprising: hardware logic configured to host a multithreaded rendering software pipeline using a plurality of parallel threads of execution, the multithreaded rendering software pipeline including a plurality of stages configured to perform work in connection with rendering an image in a buffer; a rolling texture context data structure accessible by the plurality of stages in the multithreaded rendering software pipeline, the rolling texture context data structure configured to store a plurality of texture contexts, each texture context configured to enable access to at least one texture, and each texture context further configured to store state data for the at least one texture as work is being performed by the plurality of stages of the multithreaded rendering software pipeline, the plurality of texture contexts including a first texture context used to perform first work with a first texture in the multithreaded rendering software pipeline; and control logic configured to, in response to an attempt to modify the first texture context in connection with performing second work with the first texture in the multithreaded rendering software pipeline, copy the first texture context to a second texture context and modify the second context such that the first and second work with the first texture are respectively performed in the multithreaded software pipeline using the first and second texture contexts.