Patent ID: 8547729

Claim:
A dynamic random access memory (DRAM), comprising: a substrate; an active area, in the substrate; an insulating layer, on the substrate, and the active area is exposed from the insulating layer; a plurality of bit lines, disposed on the substrate in a first direction, wherein each of the bit lines covers a portion of the active area; a plurality of word lines, disposed on the bit lines in a second direction; a plurality of embedded channels, disposed in the substrate between two adjacent bit lines below the word lines in the active area; a plurality of conductive plugs, connecting each of the word lines and the embedded channels, wherein each of the conductive plugs is on the active area; a plurality of trench capacitors, disposed in the substrate between the two adjacent bit lines except where the embedded channels are disposed, wherein a plurality of tops of the trench capacitors is covered by the insulating layer; a silicon oxide layer, disposed on a first sidewall of the insulating layer to be sandwiched by a portion of the insulating layer and one of the bit lines disposed at a first side of each of the trench capacitors, and the silicon oxide layer is further sandwiched by a surface of the substrate and the one of the bit lines at the first side of each of the trench capacitors; and a bit line contact, disposed between the substrate and another of the bit lines disposed at a second side of each of the trench capacitors, wherein the second side is opposite to the first side, and the bit line contact is directly contacted with a second sidewall of the insulating layer, wherein the second sidewall is opposite to the first sidewall.