Patent ID: 7797118

Claim:
A calibrated real-time clock system comprising: a first clock responsive to an uncompensated clock signal for generating a fast clock signal at higher frequency than said uncompensated clock signal; a second clock responsive to said uncompensated clock signal for generating a slow clock signal at lower frequency than said uncompensated clock signal; a switching circuit for selectively, momentarily, replacing said uncompensated clock signal with said fast or slow clock signal to generate a compensated clock signal; a calibration timing circuit for generating a calibration strobe and a window trigger from said compensated clock signal; and a logic circuit responsive to said window trigger for detecting any uncompensated clock frequency error and responsive to said calibration strobe for driving said switching circuit to selectively, momentarily, replace said uncompensated clock signal with said fast or slow clock signal to reduce the uncompensated clock frequency error.