Patent ID: 7476938

Claim:
A chip, comprising: an active semiconductor region having a major surface and a thickness extending from said major surface to a first depth below said major surface; a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within said active semiconductor region, a length of said channel region being oriented in a longitudinal direction of said active semiconductor region, and a width of said channel region being oriented in a transverse direction of said active semiconductor region transverse to said longitudinal direction; a first dielectric stressor element laterally adjacent to a first edge of said active semiconductor region, said first dielectric stressor element extending from said major surface of said active semiconductor region downward to a depth not substantially greater than said first depth; and a second dielectric stressor element underlying only a portion of said active semiconductor region at a second edge of said active semiconductor region opposite said first edge, said second dielectric stressor element having a horizontally extending upper surface at said first depth, said second dielectric stressor element sharing an edge with said active semiconductor region, said edge extending in a direction away from said upper surface, said first dielectric stressor element applying a first stress to said channel region in a first direction and said second dielectric stressor element applying a second stress to said channel region in a second direction opposite to said first direction such that said first and second stresses cooperate together to apply a shear stress to said channel region.