Patent ID: 8179389

Claim:
A decoder for receiving a digital data and outputting an analog voltage, the decoder comprising: a main switch array for receiving the digital data and outputting a voltage if the digital data is in a first range, wherein the main switch array is a full-type decoder; a first pre-decoding switch array for receiving the digital data, pre-decoding a part of the digital data, and outputting a voltage if the digital data is in a second range, wherein each row of the first pre-decoding switch array comprises a first pre-decoding switch and a plurality of first switches, and the first pre-decoding switch is controlled by the first pre-decoded signal; and a second pre-decoding switch array for receiving the digital data, pre-decoding the part of the digital data, and outputting a voltage if the digital data is in a third range, wherein each row of the second pre-decoding switch array comprises a second pre-decoding switch and a plurality of second switches, and the second pre-decoding switch is controlled by the second pre-decoded signal, wherein combination of the main switch array, the first pre-decoding switch array and the second pre-decoding switch array is in a substantially rectangular layout structure; and wherein an amount of switches in each row of the main switch array is N 0 , an amount of the first pre-decoding switch and the first switches in each row of the first pre-decoding switch array is N 1 , an amount of the second pre-decoding switch and the second switches in each row of the second pre-decoding switch array is N 2 , and N 0 =N 1 +N 2 , wherein N 0 , N 1 and N 2 are positive integers.