Patent ID: 7584317

Claim:
A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a reconfigurable circuit provided in a succeeding stage, comprising: a data storing unit to store input data from the preceding stage circuit; an output enable signal generating unit to generate an output enable signal for outputting data stored in the data storing unit to the reconfigurable circuit on a basis of configuration information of the reconfigurable circuit; an address specifying unit to specify an address for read of an output data for the data storing unit based on the output enable signal; and a start signal generating unit to output a start signal to the output enable signal generating unit at a time point when storing of an initial input data is started for a time interval externally specified in the data storing unit, wherein the output enable signal generating unit generates an output enable signal which is delayed, by a number of clocks specified with a parameter, from an input time point of the start signal.