Patent ID: 7956420

Claim:
A circuit comprising: a first transistor of an n-type conductivity in a first area of the circuit; a second transistor of a p-type conductivity in the first area of the circuit; a third transistor of an n-type conductivity in a second area of the circuit; a fourth transistor of a p-type conductivity in the second area of the circuit; a stress control layer on the first transistor, wherein a first type of stress is applied to a channel of the first transistor by the stress control layer, wherein the second transistor includes an epitaxial layer, wherein a second type of stress is applied to a channel of the second transistor and the second type of stress is not applied to a channel of the fourth transistor; a silicide layer on source/drain regions of the second transistor; and a trench isolation in the first area of the circuit between the first and second transistors.