Patent ID: 8102936

Claim:
A data receiver circuit comprising: a first transmission line comprising at least one segment of a first predetermined length, said first transmission line to receive a clock signal and to propagate said clock signal for said first predetermined length, such that a time to propagate said clock signal for said first predetermined length corresponds to a partial period of a transmission bit time for a serial bit stream, said first transmission line further comprising a first tab for extracting, from said first predetermined length of said first transmission line, a delayed clock signal; a second transmission line comprising at least one segment of a second predetermined length, said second transmission line to receive data from said serial bit stream and to propagate said data for said second predetermined length, such that a time to propagate said data signal for said second predetermined length corresponds to a partial period of said transmission bit time for said serial bit stream, said second transmission line further comprising a tab to extract, from said second predetermined length of said second transmission line, a delayed data signal; and a sampling circuit, coupled to said first and second transmission lines, to generate samples from said delayed data signal and said delayed clock signal, so as to generate at least two samples per said transmission bit time.