Patent ID: 7739476

Claim:
A processor comprising: circuitry that executes software instructions defined in an instruction set architecture implemented by the processor, including load/store operations, during use; a memory management unit (MMU) comprising a queue that stores pending hardware-generated page table entry (PTE) updates during use, wherein the PTEs are stored in a software-created page table in memory during use, and wherein the hardware-generated PTE updates are generated within the processor directly in response to the processor using the PTEs to translate addresses of the load/store operations to the pages mapped by the PTEs during use, and wherein the hardware-generated PTE updates modify one or more usage attributes in the PTE entry that identify use of the PTE entry by the processor without changing the translation defined by the PTE entry during use, and wherein the hardware-generated PTE updates are generated during translation operations during use; and an interface unit coupled to the MMU and to an external interface of the processor, wherein the processor communicates with other agents on the external interface during use, and wherein the interface unit receives a synchronization operation on the external interface from another agent on the external interface during use, wherein the synchronization operation is defined to cause the pending hardware-generated PTE updates in the queue, if any, to be written to memory, and wherein each hardware-generated PTE update includes an address phase, a response phase, and a data phase on the external interface, and wherein the address phase includes transmission of a command and a memory address of the PTE that is being updated by the hardware-generated PTE update, and wherein the response phase is used to ensure cache coherency, and wherein the data phase includes transmission of the one or more usage attributes being modified by the hardware-generated PTE update, and wherein a synchronization operation includes the address phase and the response phase but excludes the data phase on the external interface; and wherein the MMU accepts a subsequent hardware-generated PTE update into the queue as a new pending hardware-generated PTE update during use, wherein the subsequent hardware-generated PTE update is generated subsequent to receiving the synchronization operation and prior to the synchronization operation completing on the interface during use.