Patent ID: 7174489

Claim:
A semiconductor integrated circuit device comprising: a plurality of selectable memory sections comprising: a first memory section having a minimum input/output data bit width of n bits (n a positive integer), and a second memory section having a bit width of m bits (m a positive integer greater than n); a data width expansion circuit that converts an n-bit data pattern to an m-bit data pattern; a data width reduction circuit that converts an m-bit data pattern to an n-bit data pattern; a memory self-test circuit that tests a selected one of the memory sections, the memory self-test circuit comprising: an address generation circuit that generates an address of the memory sections, the generated address determining which of the memory sections is selected, a data pattern generation circuit that generates a data pattern, a control signal generation circuit that generates a memory control signal for controlling: (a) a data writing operation of writing first test data to the selected memory section at the generated address and (b) a data reading operation of reading the stored first test data from the selected memory section at the generated address, a pass/fail judgment circuit that compares expected value data corresponding to the generated data pattern with second test data so as to determine that the selected memory section is non-defective when the compared data coincide and determine that the selected memory section is defective when the compared data do not coincide, and a test completion judgment circuit that determines completion of the memory test; and a reset circuit that resets the memory self-test circuit in response to a completion determination of the memory test by the test completion judgment circuit, wherein: when the first memory section is selected: the generated data pattern is stored in the selected memory section as the first test data, and the stored first test data read from the selected memory section is supplied to the pass/fail judgment circuit as the second test data for comparison with the expected value data; and when the second memory section is selected: the data width expansion circuit converts the n-bit generated data pattern to an m-bit data pattern that is stored in the selected memory section as the first test data, and the data width reduction circuit converts the stored m-bit first test data read from the selected memory section to an n-bit data pattern that is supplied to the pass/fail judgment circuit as the second test data for comparison with the expected value data.