Patent ID: 6973002

Claim:
A semiconductor integrated circuit comprising: a memory cell array having memory cells arranged in matrix form; sense amplifiers which amplify a signal read out from the memory cells and which include N channel sense amplifiers each comprising an N channel MOS transistor and P channel sense amplifiers each comprising a P channel MOS transistor; a first and second drive circuits each including an N channel MOS transistor which drives the N channel sense amplifiers or P channel sense amplifiers, respectively, included in the sense amplifiers, the first and second drive circuits being arranged adjacent to the sense amplifiers; and a sense amplifier control circuit which supplies a common control signal to both gate electrodes of the N channel MOS transistors included in the first and second drive circuits, wherein the P channel MOS transistors each constituting the P channel sense amplifier are formed on an N type well area, the N channel MOS transistors each constituting the N channel sense amplifier are formed on a P type well area located adjacent to the N type well area, and the N channel MOS transistors included in the first and second drive circuits are formed on the P type well area.