Patent ID: 7164596

Claim:
A memory array having a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality of column select lines and bit lines for accessing columns of cells, the memory array comprising: the memory cells comprising first and second cross-coupled inverters having first and second outputs, respectively, a first pair of pass gates comprising a first column select pass gate connected to a first one of the column select lines for selecting a column of cells, and a first row select pass gate connected to a first one of the word lines for selecting a row of cells, the first pair of pass gates connected in series between the first output of the first inverter and a first of the plurality of bit lines; a high voltage supply operable to provide a variable high voltage to a high voltage supply terminal of the cross-coupled inverters; and a low voltage supply operable to provide a variable low voltage to a low voltage supply terminal of the cross-coupled inverters; wherein the high and low voltage supplies are operable to supply a write bias condition to the cross-coupled inverters during a write operation and a read bias condition to the cross-coupled inverters during a read operation, and wherein the write bias condition is different from the read bias condition.