Patent ID: 7353487

Claim:
An integrated circuit, comprising: a global signal distribution network; a first regional signal distribution network and a second regional signal distribution network; a regional buffer having an output coupled at an end of the first regional signal distribution network and at an end of the second regional signal distribution network; the first regional signal distribution network spanning a first row of adjacent configurable logic blocks of respective adjacent columns of configurable logic blocks; the second regional signal distribution network spanning a second row of adjacent configurable logic blocks of the columns of configurable logic blocks different from the first row; the regional buffer coupled to a first input/output block; the first input/output block being part of a column of input/output blocks bordering the columns of configurable logic blocks at one end thereof; the first input/output block being a regional clock capable input/output block; the first regional signal distribution network coupled to the regional buffer to receive clock signaling for providing the clock signaling to the first row of configurable logic blocks via the first input/output block; and the second regional signal distribution network coupled to the regional buffer to receive the clock signaling for providing the clock signaling to the second row of configurable logic blocks via the first input/output block.