Patent ID: 7952207

Claim:
An electronic package comprising: a chip carrier comprising: a substrate; a first conductive pad on said substrate; a solder resist layer on said substrate covering said first conductive pad, said solder resist layer has a top surface; a via, having a first diameter, and extending through said solder resist layer to said first conductive pad; an electroplated metal layer having a lower portion and an upper portion, said lower portion being immediately adjacent to said first conductive pad and filling said via, and said upper portion being above said lower portion and having a second diameter greater than said first diameter such that said upper portion extends laterally over and physically contacts said top surface of said solder resist layer, said upper portion having a first side adjacent to said top surface and a second side opposite said first side, said second side being curved such that a thickness of said upper portion tapers from a center of said upper portion to an outer edge of said upper portion; and a plurality of ball limiting metallurgy layers covering said second side of said upper portion of said metal layer; a semiconductor chip comprising a second conductive pad; and a solder layer extending between said at least one ball limiting metallurgy layer and said second conductive pad so as to electrically connect said semiconductor chip to said chip carrier.