Patent ID: 7141502

Claim:
A silicon integrated circuit fabricated using a method of removing excess interconnect material during fabrication of said silicon integrated circuit, said method of removing comprising the steps of: dispensing a slurry including abrasive particles and chemical on a sample having said excess interconnect material; polishing said sample with said slurry, using a polishing pad having a plurality of pits, to remove said excess interconnect material, wherein said abrasive particles and chemical become embedded into said plurality of pits of said polishing pad; reducing said dispensing of said slurry after said polishing for a first period of time, wherein said dispensing of said slurry is reduced to a stop, said step of reducing occurring after detecting an endpoint of said step of polishing said sample with said slurry, based on a thickness of said excess interconnect material; and polishing said sample using said polishing pad for a second period of time to remove said excess interconnect material.