Patent ID: 7584442

Claim:
A memory timing database recorded on a computer-readable medium and accessible by a computer, the database comprising: timing characteristics for each of a plurality of different tiling netlists described by triple (MEM, Memory Resource, tiling_variant), wherein Memory Resource identifies a memory resource on an integrated circuit, MEM identifies a characterization memory of a set of characterization memories having different variants of tiling a specific design memory to the Memory Resource, and tiling_variant identifies the variant of tiling MEM to Memory Resource, wherein the timing characteristics comprise, for each tiling netlist: evaluated timing characteristics corresponding to a first subset of combinations of input ramptimes and output loads of the tiling netlist; and estimated timing characteristics corresponding to a second, different subset of combinations of input ramptimes and output loads of the tiling netlist, which are mathematical functions of at least one or more of the timing characteristics for the first subset.