Patent ID: 7510923

Claim:
A method for implementing slim sidewall spacers in transistor fabrication on a semiconductor substrate, comprising: forming a first layer of oxide based material over a gate stack on the substrate and over exposed areas of a substrate on either side of the gate stack; forming source/drain extension regions in the substrate on either side of the gate stack; performing a first anneal; forming a second layer of oxide based material over the first layer of oxide based material; forming a first layer of nitride based material over the second layer of oxide based material; patterning the first layer of nitride based material to establish first sidewall spacers on either side of the gate stack; forming source/drain regions in the substrate on either side of the gate stack and first sidewall spacers; forming a second layer of nitride based material over the first sidewall spacers and exposed areas of the second layer of oxide based material; performing a second anneal; removing the second layer of nitride based material and the first sidewall spacers; forming a third layer of nitride based material over the second layer of oxide based material; and patterning the third layer of nitride based material to establish second sidewall spacers on either side of the gate stack, the second sidewall spacers having a second width that is smaller than a first width of the first sidewall spacers.