Patent ID: 8621183

Claim:
A system, comprising: a processor of a plurality of processors coupleable to a shared memory; wherein the processor is configured to initiate execution of a section of code according to a first transactional mode of the processor, wherein the processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors; wherein the processor is configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor; wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition; and wherein the recovery actions associated with the second transactional mode comprise: discarding any modifications to the shared memory made by one or more of the plurality of protected memory access operations of the subsection of code; and continuing execution of the subsection of code without executing any store operations of the plurality of protected memory access operations that are within the subsection of code.