Patent ID: 7123066

Claim:
A die having an operating condition, the die comprising: an output bus; a speed-locked loop to provide on the output bus a value indicative of the operating condition and to provide a ready signal indicative of whether the speed-locked loop has attained lock; and a speed-compensating circuit responsive to the output bus value if the ready signal indicates lock; wherein the speed-locked loop comprises: a digitally controlled oscillator(DCO) having a frequency; a first counter coupled to an output of the DCO to provide a first counter value indicative of the oscillator frequency, the first counter value being a digital value having a plurality of bits and each bit being one of logically high and logically low values; an input bus having predetermined bits representing an input bus value; a comparator to compare the first counter value to the input bus value to generate a first signal indicating whether to increase or decrease the frequency of the DCO; and a control functional unit coupled to the comparator and the oscillator, in response to the first signal, to generate a second signal to decrease the oscillator frequency if the counter and input bus values satisfy a first relationship and to increase the oscillator frequency if the counter and input bus values satisfy a second relationship.