Patent ID: 7899953

Claim:
A data transfer system comprising: a plurality of data generation terminals that generate divided data of apparatus control data; a host terminal that is connected to each data generation terminal for performing transmission control of said divided data; a plurality of data transfer apparatuses that randomly receive said divided data, store said data in a memory, and transfer said divided data from an extension card corresponding to a general purpose high-speed data transfer bus; and a predetermined apparatus to be controlled by the transferred divided data, wherein each of said data transfer apparatuses includes, a parameter list generation means that reads information specifying the order of transfer among information including said divided data from the divided data stored in said memory and generates a transfer parameter list in order to control said predetermined apparatus; and a transfer processing means that sets the parameter list to said extension card, receives divided data transferred in a DMA mode from said memory via said high-speed data transfer bus by bypassing a CPU, and transfers said divided data to a memory on the side of said predetermined apparatus according to the order recorded in the set parameter list, and said host terminal includes a transmission control means that randomly groups two or more divided data having consecutive address information to form block data in a range not exceeding the maximum memory size of each data transfer apparatus and transmits data in units of said block data to any of the data transfer apparatuses.