Patent ID: 8855299

Claim:
A processor comprising: instruction circuitry to receive an encryption instruction, the encryption instruction including a field for an address of a storage region; encryption circuitry to perform, in response to the instruction circuitry receiving the encryption instruction, encryption including a plurality of rounds, each round using a corresponding round key from a plurality of round keys; key generation circuitry to derive the plurality of round keys from an input key provided by the encryption instruction; and control logic to fetch, for use during each of the plurality of rounds, the corresponding round key from the storage region, to determine, based on a comparison of the input key provided by the encryption instruction to the contents of a storage location for the input key in the storage region, whether the storage region contains the plurality of round keys, and, in response to determining that the storage location does not contain the plurality of round keys, to cause the key generation circuitry to derive the plurality of round keys from the input key and to store the plurality of round keys in the storage region.