Patent ID: 8023325

Claim:
A nonvolatile memory apparatus comprising: a control unit; and a nonvolatile memory including a plurality of memory cells, and two buffers, wherein each of the memory cells has a threshold voltage in one of plural voltage ranges, one of which indicates an erase status, and the others of which indicate different program status, wherein a first buffer of the two buffers is configured to be used for reading or programming for a first page, and a second buffer of the two buffers is configured to be used for reading or programming for a second page, wherein, when data is programmed into one page of the first page and the second page, the threshold voltage of the memory cell to be programmed is moved into or kept as one of two voltage ranges, wherein, when data is programmed into both pages of the first page and the second page, the threshold voltage of the memory cell to be programmed is moved into or kept as one of four voltage ranges, and wherein a first memory cell to be programmed is configured to be used for storing information indicating whether one or both pages of the first page and the second page are programmed.