Patent ID: 7911239

Claim:
A method comprising: receiving a first clock input signal of a plurality of clock input signals in a clock multiplexer circuit, each of the plurality of clock input signals associated with one or more of a plurality of clock select signals that indicates whether the associated clock input signal is selected; providing a clock signal output from said clock multiplexer circuit in response to said clock multiplexer circuit receiving said first clock input signal and a first clock select signal of the plurality of clock select signals configured to indicate a selection of the first clock input signal; determining a low phase output level in said clock signal output in response to a low phase input level in said first clock input signal; locking said clock multiplexer circuit to maintain said low phase output level irrespective of the phase level of said first clock input signal, wherein the locking of said clock multiplexer circuit is performed by locking a set of internal request lines of said clock multiplexer circuit in response to the first clock select signal of the plurality of clock select signals being configured not to indicate a selection of the associated clock input signal, wherein the set of internal request lines is used to facilitate transitions of the clock signal output from said clock multiplexer circuit between the plurality of clock input signals, and wherein said clock multiplexer circuit maintains said low phase output level at least so long as the set of internal request lines remain locked; receiving a second clock input signal of the plurality of clock input signals in said clock multiplexer circuit; determining the presence of a low phase input level in said second clock input signal; switching, if a second clock select signal of the plurality of clock select signals is configured to indicate a selection of the second clock input signal, from providing said clock signal output based on the locked low phase output level to providing said clock signal output in response to said second clock input signal while maintaining said low phase output level and while said low phase input level is present in said second clock input signal, wherein the switching step includes unlocking the set of internal request lines; and allowing said clock signal output of said clock multiplexer circuit to follow the phase level of said second clock signal input after said switching step.