Patent ID: 8034686

Claim:
A method for manufacturing an N-channel integrated configuration comprising a plurality of trench MOSFETs having trench contacts and a plurality of trench Schottky rectifiers having planar contacts further comprising the steps of: growing a lighter N doped epitaxial layer upon a heavily N doped substrate; applying a trench mask with open and closed areas on the surface of said epitaxial layer; removing semiconductor material from exposed areas of said trench mask to form a plurality of gate trenches and at least a wider gate trench for common trench gate; growing a sacrificial oxide layer onto the surface of the all the gate trenches to remove the plasma damage; removing said sacrificial oxide and trench mask and depositing a first insulation layer along the inner surface of all the gate trenches; depositing doped poly into all the gate trenches; etching back or CMP the doped poly; applying a body mask and implanting said epitaxial layer with P type dopant to form P body regions; removing the body mask and diffusing the P type dopant; applying a source mask implanting said epitaxial layer with N+ type dopant to form N+ source regions; removing the source mask and diffusing the N+ type dopant; depositing a second insulating layer along the top surface of the epitaxial layer; applying a first contact mask; etching said second insulating layer from exposed areas of the first contact mask to form a plurality of trench contacts for trench Schottky rectifier and common trench gate; removing the first contact mask and applying a second contact mask instead; etching said second insulating layer and the N+ source regions and into the P body regions by successively dry oxide etching and dry Si etching to form a plurality of source-body trench contacts; removing the second contact mask and ion implanting the epitaxial layer with BF2; activating BF2 dopant by RTA under 900˜1000° C. for 15˜60 sec; depositing a barrier layer along inner surface of all the contact trenches; forming silicide by RTA under 700˜800° C. for 15˜60 sec; depositing a W layer into all the contact trenches and etching back or CMP said W and said barrier layer; depositing a resistance-reduction metal layer onto said W layer and said second insulating layer; depositing a source metal layer onto front side; applying a metal mask to pattern front metal layer into source metal (or anode metal) and gate metal; depositing a drain metal on rear side of wafer after backside grinding.