Patent ID: 7890699

Claim:
A circuit arrangement, comprising: a single instruction multiple data (SIMD) execution unit including an SIMD register file; a fixed point execution unit including a general purpose register file; a memory bus configured to be coupled to a memory; an L1 cache; an L2 cache; and control logic coupled to the SIMD and fixed point execution units, the memory bus and the L1 and L2 caches, the control logic configured to: in response to each request from the fixed point execution unit for first data, issue the request from the fixed point execution unit on the memory bus to initiate retrieval of the first data from the memory, and upon return of the first data over the memory bus, initiate storage of the first data in the general purpose register file and the L1 cache; and in response to each request from the SIMD execution unit for second data, issue the request from the SIMD execution unit on the memory bus to initiate retrieval of the second data from the memory, and upon return of the second data over the memory bus, initiate storage of the second data in the SIMD register file while bypassing the L1 cache; and wherein the L2 cache is configured to snoop the memory bus and store in the L2 cache any data requested by the control logic over the memory bus such that, in response to each request from the fixed point execution unit, the first data is stored in the fixed point execution unit, the L1 cache and the L2 cache, and in response to each request from the SIMD execution unit, the second data is stored in the SIMD execution unit and the L2 cache, but not in the L1 cache.