Patent ID: 8368435

Claim:
A method for reducing jitter in a received clock input signal, the received input signal having a second frequency and a second phase comprising: receiving a high frequency clock signal based on a reference signal, the reference signal at a first frequency and a first phase, the high frequency clock signal at the first frequency and the first phase; receiving a clock input signal at a second frequency and at a second phase, wherein the second frequency and the second phase is different than the first frequency and the first phase; receiving the high frequency clock signal at a phase interpolator; processing the high frequency clock signal with the phase interpolator based on input from a loop filter to generate a high frequency clock output which has less jitter than the high frequency clock signal; receiving the clock input signal and a divided version of the high frequency clock output at a phase detector; processing the clock input signal and the divided version of the high frequency clock output with the phase detector to generate one or more loop filter input signals to a loop filter; receiving the one or more loop filter input signals at a loop filter; and processing the one or more loop filter input signals with the a loop filter to generate the input to the phase interpolator, wherein the processing by the phase interpolator, the phase detector, and the loop filter occur in the digital domain.