Patent ID: 8867597

Claim:
A clock dejitter method comprising: operating, by an input of a data sending adapter module, under a system clock and using a sending clock to send data; associating the system clock with the sending clock of the data sending adapter module using a clock dejitter module; and tracking variations, by the clock dejitter module, in a data enable signal reflecting data sending state by referring to the system clock, and dynamically generating the sending clock varying with the data sending state; wherein the data sending adapter module uses a clock generated by the clock dejitter module as the sending clock upon initialization, and the sending clock is updated dynamically in real time and finally stabilized by the clock dejitter module such that data rates at both sides of an adapter are matched; wherein the clock dejitter module comprises a first in first out (FIFO) buffer area and a dejitter controller connected to the FIFO buffer area, the FIFO buffer area reflects a relationship between the sending clock and the system clock, the FIFO buffer area operates under the system clock and uses the data enable signal as a writing enable signal of the FIFO buffer area, and the dejitter controller balances and adjusts fluctuation generated by the data enable signal in the FIFO buffer area based on the system clock so as to dynamically generate a sending clock prototype as an FIFO reading enable signal.