Patent ID: 7772065

Claim:
A method of manufacturing a semiconductor memory device, comprising: forming a transistor including first and second diffusion regions; forming first and second cell contacts connected to the first and second diffusion regions, respectively; forming first and second pillars connected to the first and second cell contacts, respectively; forming a bit line connected to the first pillar; forming a capacitor contact connected to the second pillar; and forming a storage capacitor connected to the capacitor contact, wherein a diameter of at least one of an upper surface portion of the first pillar and an upper surface portion of the second pillar is smaller than a diameter of a bottom surface portion of the first pillar and a bottom surface portion of the first portion of the second pillar, respectively, wherein the upper surface portion of the first pillar is a surface portion that contacts the bit line, the upper surface portion of the second pillar is a surface portion that contacts the capacitor contact, the bottom surface portion of the first pillar is a surface portion that is opposite to the upper surface portion of the bit contact, and the bottom surface portion of the second pillar is a surface portion that is opposite to the upper surface portion of the second pillar.