Patent ID: 7052951

Claim:
A method of fabricating a ferroelectric memory device, the method comprising: forming a lower insulating layer including a conductive plug on a semiconductor substrate; forming an oxygen-diffusion barrier pattern that is electrically connected to the conductive plug and forming an upper insulating pattern on the lower insulating layer such that the upper insulating pattern surrounds sidewalls of the oxygen-diffusion barrier pattern and a top surface of the tipper insulating pattern is higher than a top surface of the oxygen-diffusion barrier pattern; forming a lower electrode layer on the upper insulating pattern and the oxygen-diffusion barrier pattern; forming a ferroelectric layer on the lower electrode layer; forming an upper electrode layer on the ferroelectric layer; patterning the lower electrode layer, the ferroelectric layer and the upper electrode layer; and after forming the upper electrode layer, forming a third insulating layer that directly contacts sidewalls of the patterned lower electrode layer, the patterned ferroelectric layer and the patterned upper electrode layer.