Patent ID: 8716785

Claim:
A semiconductor device, comprising: a semiconductor substrate; a source and a drain region formed on the semiconductor substrate; an inter-layer dielectric (ILD) layer disposed over the semiconductor substrate; and a gate structure disposed on the substrate between the source and drain regions, the gate structure including: a trench formed within the ILD layer and having a top surface; and a metal layer partially filling the trench, wherein the metal layer includes a sidewall portion and a bottom portion, wherein the sidewall portion is thinner than the bottom portion, wherein the sidewall and bottom portions of the metal layer form part of a gate electrode of the gate structure, and wherein the ILD layer extends from an interface between the sidewall portion and the bottom portion to at least a topmost surface of the sidewall portion such that the sidewall portion continuously physically contacts the ILD layer from the interface to at least the topmost surface of the sidewall portion, wherein the topmost surface of the sidewall portion is positioned further away from the top surface of the semiconductor substrate than any other portion of the metal layer, wherein the ILD layer extends from the interface between the sidewall portion and the bottom portion to at least a bottommost surface of the bottom portion such that the bottom portion continuously physically contacts the ILD layer from the interface to at least the bottommost surface of the bottom portion, and wherein there is no other material that is part of the gate electrode positioned between the bottommost surface of the bottom portion and a topmost surface of the semiconductor substrate, wherein the bottommost surface of the bottom portion is directly over and faces the topmost surface of the substrate.