Patent ID: 7714362

Claim:
A semiconductor device comprising: a workpiece; a plurality of active areas formed in the workpiece; a plurality of input/output cells formed over the plurality of active areas, wherein each input/output cell is electrically coupled to one of the plurality of active areas; and a bond pad layer disposed over the plurality of input/output cells, wherein the bond pad layer comprises: a first plurality of bond pads, disposed in a first pattern, wherein the first pattern is a circuit-under-pad (CUP) pattern, wherein each of the first plurality of bond pads is over a respective one of the plurality of input/output cells; and at least a second plurality of bond pads, disposed in a second pattern, wherein the second pattern comprises a non-CUP pattern; wherein a first electrical connection of a first input/output cell of the plurality of input/output cells is coupled to a first bond pad and a second bond pad from, respectively, the first plurality of bond pads and the at least second plurality of bond pads, the first electrical connection being physically interposed between the first plurality of bond pads and the plurality of input/output cells, the first pattern being different from the second pattern.