Patent ID: 7361546

Claim:
A method of forming a polysilicon stud on a vertical memory device, comprising: providing a semiconductor substrate; forming a pad dielectric layer on said semiconductor substrate; forming a deep trench in said semiconductor substrate; forming a trench capacitor in a lower portion of said deep trench; forming a gate dielectric layer on a sidewall of a higher portion of said deep trench; forming a conductive layer over said gate dielectric layer to fill said deep trench, and removing a portion of said conductive layer to expose said gate dielectric layer; forming a spacer above said gate dielectric layer and within said deep trench; forming a polysilicon layer over said pad dielectric layer to fill said deep trench; and performing a chemical mechanical polishing on said polysilicon layer to remove an overhang over a top corner of said deep trench so as to form said polysilicon stud in said higher portion of said deep trench, said polysilicon stud having comprising an upper surface lower than an upper surface of said pad dielectric layer in said higher portion of said deep trench.