Patent ID: 7518177

Claim:
A semiconductor storage device, comprising: a first transistor having a gate comprised of a first polysilicon segment over a first active region, a source formed in the first active region, and a drain formed in the first active region; a first capacitor having a first terminal comprised of the first polysilicon segment over a second active region, a second terminal in the second active region, and a first capacitance; a second capacitor having a first terminal comprised of the first polysilicon segment over a third active region, a second terminal in the third active region, and a second capacitance, wherein the first capacitance is greater than the second capacitance; a second transistor having a gate comprised of a second polysilicon segment over the first active region, a source formed in the first active region and coupled to the source of the first transistor, and a drain formed in the first active region; a third capacitor having a first terminal comprised of the second polysilicon segment over the second active region, a second terminal in the second active region, and a third capacitance; a fourth capacitor having a first terminal comprised of the second polysilicon segment over the third active region, a second terminal in the third active region, and a fourth capacitance, wherein the fourth capacitance is greater than the third capacitance.