Patent ID: 7646228

Claim:
A repeater circuit comprising: a circuit for accessing an input signal at an input terminal and producing an output signal at an output terminal analogous to said input signal, said circuit comprising: a delay chain of inverters for producing first and second delayed versions of said input signal; a holding subcircuit coupled to receive said first delayed version of said input signal and coupled to said output terminal of said repeater circuit; a rising edge subcircuit comprising a first pulse generator to generate a rising output transition at said output terminal; said first pulse generator accessing said input signal and said second delayed version of said input signal; a falling edge subcircuit comprising a second pulse generator to generate a falling output transition at said output terminal; said second pulse generator accessing said input signal and said second delayed version of said input signal; a first latching circuit coupled to an output node of said first pulse generator and to said output terminal; and a second latching circuit coupled to an output node of said second pulse generator and to said output terminal.