Patent ID: 8086828

Claim:
A computing system comprising: a first processor configurable to operate in any one of a plurality of modes including a native mode and a compatible mode; and a second processor communicably coupled to the first processor and configurable to operate in any one of a plurality of modes including a native mode and a compatible mode, the second processor having a design that differs in at least one respect from a design of the first processor, wherein the computing system is configurable such that the first processor and the second processor cooperate to perform a distributed processing task and wherein: when operated in the compatible mode, each of the first and second processors accepts a same baseline command set and produces identical results upon executing any command in the baseline command set, wherein the baseline command set includes a first command that, when executed by either the first or second processor in the compatible mode, produces a first result; when operated in the native mode, the first processor, upon executing the first command, produces a second result that is different from the first result; and when operated in the native mode, the second processor, upon executing the first command, produces a third result that is different from both the first result and the second result wherein the design of the second processor differs from the design of the first processor in at least one respect from a design of the first processor in that a bug fix is present in the design of the second processor but not in the design of the first processor, and wherein the bug fix is disabled when the processor is configured to operate in the compatible mode.