Patent ID: 8732359

Claim:
A computing device, in a technical computing environment, comprising: a memory to store executable instructions to implement an executable graphical model of a dynamic system; and a processor configured to: receive an indication of a first set of operations, wherein the first set of operations: outputs data upon occurrence of a triggering event, and has a first periodicity value; receive an indication of a second set of operations, wherein the second set of operations: executes concurrently with the first set of operations, reads the data output by the first set of operations, and has a second periodicity value, wherein: the second periodicity value of the second set of operations is an integer or inverse integer multiple of the first periodicity value of the first set of operations, and execution of instances of the first set of operations and the second set of operations share a common time base; create, within the executable graphical model, a first buffer and a second buffer; configure the first set of operations to write the data to the first buffer during a first execution instance of the first set of operations; configure the first set of operations to write the data to the second buffer during a second execution instance of the first set of operations; and configure the second set of operations to read the data from the first buffer during an execution instance of the second set of operations, the execution instance of the second set of operations executing contemporaneously with the second execution instance of the first set of operations, wherein determinations regarding access to the first buffer and second buffer by the first set of operations are self-contained within the first set of operations, and wherein determinations regarding access to the first buffer and the second buffer by the second set of operations are self-contained within the second set of operations.