Patent ID: 8488357

Claim:
A method to realize reference current circuits for reliable sensing operations in segmented memory architecture, comprising the following steps: (1) providing a segmented memory array structure comprising Poly-Si Read Word lines, Write Select Lines, Write Word lines, bit lines, a multiplexer, sense amplifiers, and reference word lines; (2) applying a folded bit line scheme to array structure; (3) deploying two pairs of Reference Word Lines, wherein a first line of each pair is connected to cells with stored data 0 and a second line of each pair is connected to cells with stored data 1 ; (4) selecting a first pair of Reference Word to supply reference and read currents on two bit lines adjacent to the cells to be read if an even read word line is selected to read correspondent cells; and (5) selecting a second pair of Reference Word Line to supply reference and read currents on two bit lines adjacent to the cells to be read if an odd read word line is selected to read correspondent cells, and a sense amplifier is connected to the two adjacent bit lines to compare the reference and supply current.