Patent ID: 8610511

Claim:
A high-frequency digitally controlled oscillator, comprising: an even number of digital delay stage (DDSs) circuits, each of the DDS circuits having at least one capacitive load cell, each of the capacitive load cells having a digital switch, each of the digital switches being configured to turn on and off in response to control words applied to the switches to change the capacitance of the capacitive load cell; two digital oscillators having identical inverters, each of the digital oscillators having a plurality of stages arranged in cascade, each of the stages having at least two of the DDS circuits; a merging NAND gate, the two digital oscillators each having a high frequency output fed through the cascade of DDS stages to an input of the merging NAND gate, the NAND gate having an output; a counter, the output of the merging NAND gate being fed to an input of the counter, the counter having an output; and a multiplexer, the output of the merging NAND gate and the output of the counter being input to the multiplexer, the multiplexer having an output; wherein the multiplexer output has a frequency programmably determined by the control words applied to the switches of the capacitive load cells of the DDS circuits.