Patent ID: 8140825

Claim:
A memory controller, in an instruction execution system with one or more processing cores, for selectively opening and closing pages in banks of memory, comprising: a receive mechanism configured to receive a switch signal from an operating system indicating that a context switch, in which a first process is configured to be context-switched out of a first core, is imminent, and configured to receive a core identifier to identify the first core to undergo the context switch; a logical table with rows corresponding to banks of memory and columns corresponding to cores, so that a bit set in a specific row and column indicates an open page of memory for the corresponding bank and core; and a table controller, in response to the switch signal and to the core identifier, configured to unset a bit in a first column of the table corresponding to the identified first core and in a row indicating a first bank, wherein unsetting the bit indicates an open page is configured to close if there is no other bit set in the row; and wherein the table controller further is configured to set a bit in the table to indicate an open page when a memory access is received from a second process being executed in a second core.