Patent ID: 6845493

Claim:
A method for preparing a semiconductor substrate for use in characterizing line end shortening associated with integrated circuit fabrication, the method comprising: providing on the semiconductor substrate a plurality of conductive paths which each has at least one contact portion; for each of said conductive paths, designing an associated line end structure corresponding to an integrated circuit design, including designing each said line end structure such that, when provided on the semiconductor substrate, the line end structure is expected to contact only a predetermined amount of the contact portion of the associated conductive path, wherein the predetermined amount associated with each said line end structure differs from the predetermined amount associated with each remaining said line end structure; providing the line end structures on the semiconductor substrate; sequentially measuring conductivity between each of said conductive paths and the associated line end structure; and calculating line end shortening according to a change of measured conductivity between at least two sequential conductivity measurements, wherein at least one of the at least two sequential conductivity measurements includes a measurement of a substantially open-circuit.