Patent ID: 8312299

Claim:
A computer-implemented method, comprising: providing a first operating voltage and a first clock frequency to a peripheral device, operating in a first operating state, wherein the peripheral device is coupled to an input-output (I/O) controller in a processing system with a serial bus; monitoring bus transactions on the serial bus using a power manager, coupled between the I/O controller and the peripheral device, to assess a current processing demand for the peripheral device; and dynamically adjusting at least one of the first operating voltage or the first clock frequency in response to the current processing demand, wherein a plurality of peripheral devices are coupled to the I/O controller using the power manager, including the peripheral device, and wherein the monitoring comprises: receiving a start signal from the I/O controller for a current bus transaction; decoding a device address of the current bus transaction to select one of the plurality of peripheral devices to send the current bus transaction; delaying the current bus transaction from being sent to the selected peripheral device by placing the I/O controller in a wait state for the current bus transaction; while delaying the current bus transaction, transitioning the selected peripheral device to a second operating state from the first operating state by said dynamically adjusting, wherein the first operating state is a lower power state than the second operating state; initiating a device communication flow between the I/O controller and the peripheral device for the current bus transaction when the selected peripheral device is operating at the second operating state; and determining that the selected peripheral device is a serial peripheral interface (SPI) device, and wherein initiating the device communication flow comprises: asserting a chip select (CS) signal to the SPI device; releasing the clock line between the I/O controller and the power manager to activate the I/O controller from the wait state; and determining whether the current bus transaction is a read operation or a write operation, wherein if the current bus transaction is a read operation, the determining comprises: holding the clock line between the I/O controller and the power manager low; reading a first set of one or more bits of data from SPI device; releasing the clock line between the I/O controller and the power manager; and sending the first set of data to the I/O controller, and wherein if the current bus transaction is a write operation, the determining comprises: buffering a second set of one or more bits of data received from the I/O controller; acknowledging the I/O controller; holding the clock line between the I/O controller and the power manager low; sending the second set of data received from the I/O controller to the SPI device; and releasing the clock line between the I/O controller and the power manager.