Patent ID: 7317603

Claim:
An integrated circuit with electrostatic discharge protection, the integrated circuit comprising: at least one input terminal that applies a signal level; a terminal that applies a reference potential; a functional unit containing logic gates and memory cells; a first transistor comprising a source terminal, a drain terminal and a gate terminal connected to the drain terminal of the first transistor; and a second transistor comprising a source terminal, a drain terminal and a gate terminal connected to the drain terminal of the second transistor; wherein: a series circuit is arranged by connecting the first transistor in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor; the functional unit and the series circuit are connected in parallel between the at least one input terminal and the terminal that applies the reference potential; the functional unit is configured such that, in a normal operating mode, the functional unit carries out a digital signal process when the potential present at the at least one input terminal matches a first signal level; the series circuit is configured such that the at least one input terminal is connected to the terminal that applies the reference potential with lower resistance via the series circuit and via the functional unit when, during a discharge, the signal level present at the at least one input terminal is greater than a threshold value above the first signal level; and the series circuit is configured such that the at least one input terminal is connected to the terminal that applies the reference potential with higher resistance via the series circuit and via the functional unit when, in the normal operating mode, the signal level present at the at least one input terminal is less than or equal to the first signal level.