Patent ID: 7679183

Claim:
A method of fabricating a device, comprising: forming a pair of p-type semiconductor bodies and a pair of n-type semiconductor bodies on each of first and second silicide patterns such that the p-type semiconductor bodies of the pair of p-type semiconductor bodies are separated from each other and the n-type semiconductor bodies of the pair of n-type semiconductor bodies are separated from each other; forming a first dielectric layer on the p-type and n-type semiconductor bodies, and exposing top surfaces of the n-type and p-type semiconductor bodies; forming a third silicide layer on a first one of the n-type semiconductor bodies on the first silicide layer and on a first one of the p-type semiconductor bodies on the second silicide layer; forming a second dielectric layer on the third silicide layer and on an uppermost surface of a second one of the p-type semiconductor bodies and a second one of the n-type semiconductor bodies; and etching the second and first dielectric layers to form a contact hole exposing top surfaces of the first and second silicide layers.