Patent ID: 7718528

Claim:
A semiconductor process comprising: forming an etch stop layer; forming an ILD superjacent to the etch stop layer; etching a trench within the etch stop layer and the ILD; depositing a sacrificial light absorbing material (SLAM) within the trench, the SLAM comprising a photoactive generator (PAG); forming a poison barrier layer (PBL) superjacent to the SLAM; applying a photoresist layer superjacent to the PBL; exposing a portion of the photoresist to incident light; a bake operation, during which amines are generated; and wherein the PBL comprises a compound blend chosen from a group consisting of: poly-t-butyl vinylcarbamate, polyacetaldehyde with polyvinylchloride, and polyorthonovolaks with trichlorotriazine.