Patent ID: RE41653

Claim:
A method of forming a metal wiring of a semiconductor device, comprising the steps of: sequentially forming a first anti-diffusion film, a second interlayer insulating film, a third interlayer insulating film and a capping film on a first interlayer insulating film in which a first metal wiring is formed; patterning the capping film, the third interlayer insulating film, the second interlayer insulating film and the first anti-diffusion film so that the first metal wiring is exposed, thus forming a via hole; patterning the capping film and the third interlayer insulating film so that a given surface of the second interlayer insulating film is exposed on the result in which the via hole is formed, thus forming a metal wiring trench; forming a second anti-diffusion film in the via hole and the metal wiring trench by sequentially performing an ionized sputtering process, a high pressure sputtering process and a bias sputtering process; and sequentially forming copper seed layers in the via hole and the metal wiring trench in which the second anti-diffusion film is formed, and then forming a copper layer by means of an electroplating process, thus forming a via and a metal wiring.