Patent ID: 7639678

Claim:
A switch comprising: a plurality of input ports; a plurality of output ports; a plurality of transit-memory devices each cyclically connecting to each of said input ports and output ports during a predefined time-slotted frame, and each logically partitioned into: a first group of primary memory divisions each for holding a data segment from any of said input ports destined to any of said output ports; and a second group of secondary memory divisions having a one-to-one correspondence to said output ports; a plurality of transit-memory controllers each transit-memory controller associated with a respective one of said transit-memory devices; and a master controller communicatively coupled to each of said input ports and each of said transit-memory controllers; wherein said master controller is operable to: receive, from said input ports, scheduling requests each scheduling request associated with a specific data segment from a specific input port and including an identifier of a specific data stream to which said specific data segment belongs; determine a preferred group, from said first group and said second group, to receive said specific data segment; determine a transfer time of said specific data segment from said specific input port to said preferred group; communicate said transfer time to respective input ports; determine an address in each of said transit memory devices from which address a data segment is to be transferred to an output port during each time slot in said time-slotted frame; and communicate said address to said each of said transit memory devices.