Patent ID: 7478193

Claim:
A content addressable memory (CAM) system comprising: a host controller; N CAM devices, N being an integer; a plurality of forwarding buses for coupling the first of the N CAM devices to the host controller and for coupling each of the first through N−1 CAM devices to a subsequent CAM device in the N CAM devices to form a cascade chain of the N CAM devices, each of the first N−1 CAM devices and the subsequent CAM device to which it is coupled in the cascade chain being coupled via one of the plurality of forwarding buses; a final search result provider for enabling transfer of a final search result from the Nth CAM device to the host controller; and a synchronizer for providing a clock signal to the Nth CAM device, so that the transfer of the final search result from the Nth CAM device to the host controller is synchronized.