Patent ID: 8020057

Claim:
An integrated circuit comprising: A. input pads; B. output pads; C. core circuitry coupled between the input pads and the output pads, the core circuitry having an output lead, and an output control lead; D. a tri-state buffer having an input lead connected to the output lead of the core circuitry, a data output lead connected to an output pad, and an enable input lead carrying an enable signal that can place the data output lead of the tri-state buffer in a high impedance state; E. comparator circuitry having an input lead connected to the output lead of the core circuitry, a control input lead connected to the output control lead, an encoded response input lead connected to the output pad and the data output lead of the tri-state buffer, and an enable input lead; and F. a logic gate having an input connected to the output control lead, another input connected to the enable input lead of the comparator circuitry, and an output connected to the enable input lead of the tri-state buffer.