Patent ID: 7889568

Claim:
A memory comprising: a plurality of memory cells each of which includes a memory transistor and a selection transistor coupled to the memory transistor; a control gate line commonly coupled to gates of the memory transistors; a selection gate line commonly coupled to gates of the selection transistors; a source line commonly coupled to the memory cells; a bit line coupled to each of the memory cells; a first driver that sets the control gate line and the selection gate line at a first voltage in a program operation of the memory cell; a second driver that sets the source line at a second voltage in the program operation, and sets the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage; and a third driver that sets the bit line at a fourth voltage after the source line is set at the second voltage, the bit line being coupled to a memory cell being programmed.