Patent ID: 6963965

Claim:
An instruction-programmable processor, comprising: a program memory for storing instruction opcodes; a central processing unit, including one or more execution units for executing data processing instructions, and including an instruction fetch unit for presenting a fetch address to the program memory for fetching therefrom an instruction opcode corresponding to the fetch address; and a loop cache, coupled to the instruction fetch unit, and comprising: a base address register, for storing a base fetch address; a branch cache register file, having a plurality of storage locations for storing instruction codes corresponding to a sequence of fetch addresses beginning with the base fetch address, having a data input coupled to the output of the program memory, and having a data output; a multiplexer, having a first input coupled to an output of the program memory, having a second input coupled to the data output of the branch cache register file, having a select input, and having an output coupled to the instruction fetch unit of the central processing unit; and loop cache control logic, having a first control output coupled to a control input of the program memory, having a second control output coupled to the select input of the multiplexer, and having a third control output coupled to the branch cache register file for controlling writes thereto and reads therefrom, the loop cache control logic for controlling the multiplexer to select the output of the branch cache register file and for disabling a read of the program memory, responsive to the fetch address corresponding to one of the instruction codes stored in the branch cache register file; wherein the loop cache control logic also has an input for receiving a backward branch signal indicating that a fetch address corresponds to a backward branch, the loop cache control logic also for controlling the branch cache register file to load an instruction code received at its data input from the program memory responsive to receiving a backward branch signal in combination with the fetch address not corresponding to one of the instruction codes stored in the branch cache register file.