Patent ID: 7919368

Claim:
A method of manufacturing an integrated circuit comprised of an electrically erasable programmable non-volatile memory, comprising the steps of: defining first and second well regions at a surface of a substrate; forming at least one isolation structure extending from the surface at a location between the first and second well regions, and defining moat region at the surface overlying each of the first and second well regions; forming a gate dielectric layer over the moat regions in the first and second well regions; forming a unitary polycrystalline silicon element overlying the gate dielectric layer at the first and second well regions, the unitary polycrystalline silicon element having an area overlying the first well region that is substantially larger than an area of the unitary polycrystalline silicon element overlying the second well region, and having a shape that defines a coupling capacitor by its portion disposed over the dielectric layer at the first well region, and that defines a combined read transistor and tunneling capacitor by its portion disposed over the dielectric layer at the second well region; forming diffusion regions into the moat regions of the first and second well regions adjacent the location of the unitary polycrystalline silicon element; and forming conductors in contact with the first and second well regions and the diffusions formed by the diffusing step.