Patent ID: 7452773

Claim:
A method of manufacturing a flash memory device, comprising: forming an insulation layer pattern on a substrate comprising a cell region and a peripheral region, the insulation layer pattern comprising openings selectively exposing portions of the substrate; etching the exposed portions of the substrate to form trenches; filling the trenches with an insulation material to form trench structures; removing the insulation layer pattern to expose the surface of the substrate between the trench structures; forming a tunnel oxide layer on the exposed surface of the substrate; filling a gap space between the trench structures by forming a first conductive layer on the tunnel oxide layer; partially removing the trench structures to form trench isolation structures and to form a conductive layer pattern from the first conductive layer; forming a dielectric layer on the first conductive layer pattern and the trench isolation structures; forming a doped second conductive layer on the dielectric layer to fill gap space between adjacent elements in the first conductive layer pattern; removing the second conductive layer, the dielectric layer, the first conductive layer pattern and the tunnel oxide layer in the peripheral region to expose the surface of the substrate; forming an insulation layer on the exposed surface of the substrate in the peripheral region; forming a un-doped third conductive layer on the second conductive layer in the cell region, and on the insulation layer and the trench isolation structures in the peripheral region; and forming a first gate structure in the cell region and a second gate structure in the peripheral region, wherein the first gate structure comprises the tunnel oxide layer, a floating gate electrode corresponding to the first conductive layer pattern, a dielectric layer pattern, and a control gate electrode comprising the second and third conductive layers, and the second gate structure comprising a gate insulation layer corresponding to the insulation layer and a gate conductive layer comprising the third conductive layer.