Patent ID: 7424694

Claim:
A layout device for an integrated circuit, comprising: a recording unit recording connection information and delay information of wirings; a timing value calculating unit calculating a timing value with respect to each wiring path by a delay analysis of signal propagation based on the connection information and the delay information of the wirings; a target value determining unit determining a first target value serving as an improvement target of the wiring path; a detecting unit detecting an error wiring path exhibiting the timing value larger than the first target value; a improving unit changing the wiring connection so that the detected error wiring path shows a timing value smaller than the first target value; a unit updating the connection information and the delay information of the wirings, which are recorded in said recording unit, into connection information and delay information of the wirings after changing the wiring connection; a distribution calculating unit calculating a first distribution about each wiring path by the delay analysis of the signal propagation based on the post-updating connection information and the post-updating delay information of the wirings, and a fluctuation factor; a yield calculating unit calculating a first yield of said integrated circuit from the first distribution; and a judging unit judging whether or not the first yield is within an allowable range of a predetermined value.