Patent ID: 7743176

Claim:
An apparatus for communication between a plurality of hardware blocks configured in an integrated circuit and a computation device external to the integrated circuit, comprising: a bus controller for receiving words from the computation device; a first-in-first-out buffer (FIFO) in communication with the bus controller for storing the words; a processing engine having respective memory spaces associated with the hardware blocks, the processing engine configured to store the words from the FIFO in the memory spaces; an address decoder for decoding an address component of each of the words to obtain addresses of memory locations in the memory spaces; a multiplexer having a control port coupled to the address decoder, input ports respectively coupled to the hardware blocks for receiving write-ready signals, and an output port coupled to a pop control terminal of the FIFO; a strobe generator for providing strobe signals to the processing engine, the strobe signals configured to store the words in the respective memory locations; and wherein after a word is stored in the respective memory space associated with an addressed one of the hardware blocks, the addressed one of the hardware blocks asserts a respective write-ready signal to the multiplexer, in response to a control signal from the address decoder the multiplexer selects the respective write-ready signal for input to the pop control terminal, and a top word is popped from the FIFO.