Patent ID: 7968416

Claim:
A method for fabricating an integrated circuit arrangement that includes a NPN transistor containing an n-doped emitter region, a p-doped base region, and an n-doped collector region, and a PNP transistor containing a p-doped emitter region, an n-doped base region, and a p-doped collector region, the method, implemented without restrictions by the order prescribed, comprising: depositing an insulating layer on a monocrystalline semiconductor material; patterning the insulating layer to produce a first cutout, depositing a first connection layer on the patterned insulating layer, the first connection layer comprising an electrically conductive material or a material convertible into an electrically conductive material; patterning the first connection layer to produce an emitter connection region for the emitter region of the PNP transistor in the first cutout and to overlap the insulating layer outside the first cutout; providing the base region of the NPN transistor in a second cutout of the insulating layer after patterning the connection layer; wherein the base region of the PNP transistor is arranged below the cutout.