Patent ID: 8898511

Claim:
A memory system comprising: a memory controller; a plurality of memory channels in communication with the memory controller; an error detection code mechanism configured for detecting a failing memory channel; and an error recovery mechanism configured to perform a method comprising: receiving notification of the failing memory channel; blocking off new operations from starting on the memory channels; shutting down the failing memory channel and ignoring any pending stores and fetches in the failing memory channel; based on shutting down the failing memory channel, completing any in-progress fetches only on a portion of the memory channels based on the failing memory channel being detected, the portion of the memory channels consisting of non-failing channels; performing a recovery operation on the memory channels, the recovery operation comprising resetting the memory channels and performing data calibration on at least a first subset of the memory channels in the memory system while any other memory channels in the memory system that are not in the first subset are idle; retrying any pending stores that were issued prior to receiving notification of the failing memory channel after performing the recovery operation; and starting the new operations on at least a second subset of the memory channels, the memory system capable of operating with the second subset of the memory channels.