Patent ID: 8703608

Claim:
A method of forming an integrated circuit at a semiconducting surface of a body, comprising: forming isolation dielectric structures at the surface, the isolation dielectric structures defining active regions of the surface at which one of the isolation dielectric structures is not present; forming a gate dielectric layer; forming a gate layer overlying the gate dielectric layer; dispensing a photoresist over the gate layer; exposing the photoresist to light through a photomask, the photomask having photomask features arranged to define: a plurality of electrodes in the gate layer, each electrode extending for a length in a common direction with others of the plurality of gate electrodes, each gate electrode having a width at about a critical dimension corresponding to a minimum photolithographically patterned feature size, the plurality of electrodes disposed relative to one another at a substantially constant pitch; and at least one interconnect in the gate layer, the interconnect having a width at about the critical dimension and disposed at a location overlying the isolation dielectric structure, the interconnect having a length extending in a direction substantially perpendicular to the common direction of the plurality of electrodes; wherein, for one or more of the plurality of electrodes neighboring the at least one interconnect, the photomask feature defining each neighboring electrode has an end located closest to the interconnect at a distance from the photomask feature defining the interconnect between about 1.00 and about 1.20 times the nominal spacing of photomask features defining the gate electrodes, or greater than about 1.80 times the pitch; etching portions of the gate layer as defined by the mask to form the electrodes, interconnect, and neighboring electrodes; and forming source/drain regions in the active regions on sides of portions of the electrodes extending over the active regions.