Patent ID: 7881106

Claim:
A nonvolatile semiconductor memory device comprising: a nonvolatile memory including a first area which stores data for every n bits (n is a natural number of not less than 2), and a second area which stores data for every 1 bit, each of the first area and the second area including a plurality of memory cells each configured to store n-bit data on the basis of a threshold voltage; and a controller configured to set 2 n threshold voltages corresponding to n bits when writing n-bit data to a first memory cell included in the first area, and to execute the n-bit data write operation when writing 1-bit data to a second memory cell included in the second area, wherein the controller is configured to write the 1-bit data as a least significant bit to the second memory cell, and to write dummy data as data except for the least significant bit to the second memory cell.