Patent ID: 7885322

Claim:
A jitter measuring circuit comprising: a jitter measuring section including a data holding section, which latches data in accordance with a clock signal, and a variable logic delaying section, which gives a variable delay time to an output of the data from said data holding section, inverts the logic of the data, and returns the inverted data to an input of said data holding section; a jitter assessing section which determines on the basis of an output from said data holding section whether said data holding section outputs predetermined data; and a controller which instructs said variable logic delaying section to change the delay time to be given to the output of the data from said data holding section, and obtains on the basis of the result of determination output from said jitter assessing section a marginal value of the delay time given by said variable logic delaying section at which said data holding section can perform a marginal operation to output predetermined data.