Patent ID: 8301856

Claim:
Apparatus for processing data comprising: a processor responsive to a stream of program instructions to perform processing operations; and memory control circuitry coupled to said processor and to a memory and configured to control access to said memory by said processor; wherein said processor has a plurality of hardware modes of operation including at least a first mode and a second mode; said memory control circuitry controls access to said memory such that: (i) when said processor is in said first mode, said memory control circuitry permits write access to a first portion of said memory and does not permit at least write access to a second portion of said memory; and (ii) when said processor is in said second mode, said memory control circuitry permits write access to said first portion of said memory and permits write access to a second portion of said memory; and said memory control circuitry is responsive to a security flag having a set value to give said processor in said first mode an execution access not given to said processor in said second mode by preventing said processor reading, from said first portion of said memory, program instructions for execution by said processor in said second mode, wherein when said security flag has said set value and said processor is in said second mode, said memory control circuitry permits said processor to read data values from said first portion of said memory.