Patent ID: 8675437

Claim:
A semiconductor device comprising: a plurality of bank sets, each bank set comprising a plurality of banks, each bank comprising a plurality of memory mats and sense amplifier circuits corresponding to row addresses, the plurality of bank sets being arranged at first and second sides of arrays of power electrode pads to be used for operations of the sense amplifier circuits, the plurality of bank sets commonly coupled to the arrays of power electrode pads; and a controller that generates different row addresses that are supplied to bank sets, to designate different memory mats disposed at the first side or the second side of the power electrode pads, in the bank sets, when a refresh operation in accordance with a refresh command is requested, wherein the plurality of memory mats and sense amplifier circuits correspond to the least significant addresses in refresh operation, the controller logically inverts the least significant address for one of the plurality of bank sets for refresh operation, activations for refresh operation of the plurality of banks are performed at different timings, the plurality of banks are included in the bank set and are coupled to the same array of power electrode pads, and the plurality of bank sets comprises first, second, third and fourth bank sets, the first and second bank sets commonly coupled to a first one of the arrays of power electrode pads, and the third and fourth bank sets commonly coupled to a second one of the arrays of power electrode pads.