Patent ID: 7408224

Claim:
A vertical transistor structure formed on a semiconductor substrate on which an active region and a non-active region are defined by a shallow trench insulator, the structure comprising: gate electrodes, which are distanced by a predetermined interval in the active region and are formed in a vertical shape to have a predetermined depth from a top surface of the semiconductor substrate; a gate insulation layer formed between a first side wall of the gate electrodes and the semiconductor substrate; a gate spacer formed on a second side wall of the gate electrodes, covering the gate electrodes; a contact plug, which is formed in the gate spacer and which electrically connects an upper conductive line with the semiconductor substrate; a plug impurity layer formed in a lower part of the contact plug; a source/drain formed opposite to the gate electrode within the active region; a threshold voltage control region for controlling a threshold voltage within the active region, the threshold voltage control region disposed below the source/drain; and a silicon nitride layer, the silicon nitride layer disposed in contact with a top surface of the gate electrodes, the silicon nitride layer disposed directly over an entirety of the top surface of the gate electrodes.