Patent ID: 7320101

Claim:
A method of computing cyclical redundancy check bits for a message comprising: receiving a first word of the message, the first word comprising N message bits; computing a plurality of feedforward bits for the first word by: logically combining message bits of K groups of the N message bits to form K logical expressions, wherein K and N are integers, combining the K logical expressions into a plurality of terms, and storing the plurality of terms as a plurality of feedforward bits; providing the plurality of feedforward bits to a first logic circuit; providing a plurality of cyclical redundancy check bits using the first logic circuit; providing a plurality of feedback bits for the plurality of cyclical redundancy check bits using a feedback circuit; and providing the plurality of feedback bits to the first logic circuit, wherein the first logic circuit is a summing circuit, and wherein the feedback circuit is pipelined such that it receives an input and provides a corresponding output two clock cycles later.