Patent ID: 8178412

Claim:
A method of manufacturing a semiconductor memory device, comprising: forming a plurality of arrays each constituted of a gate electrode of a memory cell transistor having a laminated structure composed of a charge storage layer and a control gate layer and a gate electrode of a select transistor in and on a semiconductor substrate of a first conductivity type such that a distance between the gate electrode of the memory cell transistor and the gate electrode of the select transistor is set shorter than a distance between the gate electrodes of different memory cell transistors and a distance between the gate electrodes of different select transistors; simultaneously introducing an impurity of a second conductivity type in a surface region of the semiconductor substrate between the gate electrode of the memory cell transistor and the gate electrode of the select transistor, a surface region of the semiconductor substrate between the gate electrodes of the memory cell transistors and a surface region of the semiconductor substrate between the gate electrodes of the select transistors with the gate electrode of the memory cell transistor and the gate electrode of the select transistor used as a mask; the introducing the impurity having a first introduction and a second introduction, the first introduction being introducing of the impurity of the second conductivity type in a first direction tilted with respect to the surface region of the semiconductor substrate and having a component parallel to a gate length direction of the memory cell transistor and the select transistor, and the second introduction being introducing of the impurity of the second conductivity type in a second direction tilted with respect to the surface region of the semiconductor substrate and having a component perpendicular to the gate length direction of the memory cell transistor and the select transistor; and annealing to form source/drain diffusion layers of the memory cell transistor and the select transistor such that an impurity concentration in the surface region of the semiconductor substrate between the gate electrode of the memory cell transistor and the gate electrode of the select transistor is lower than an impurity concentration in the surface region of the semiconductor substrate between the gate electrodes of the memory cell transistors and an impurity concentration in the surface region of the semiconductor substrate between the gate electrodes of the select transistors.