Patent ID: 8421732

Claim:
An image display system having a display device, wherein the display device comprises: a timing control circuit for generating a plurality of timing signals; a display matrix comprising a plurality of display elements arranged in a matrix and vertically divided into N banks to be sequentially updated; a timing signal adjusting circuit coupled to the timing control circuit for adjusting the duty cycle of the timing signals; and a horizontal driving circuit coupled to the timing signal adjusting circuit for generating a plurality of switch signals according to the adjusted timing signals and sequentially turning on the banks, wherein, the switch signals are non-overlapping signals, wherein the timing signals comprise a horizontal start signal, a horizontal timing signal and a complementary horizontal timing signal, wherein the timing signal adjusting circuit comprises a first NAND gate circuit for adjusting the duty cycle of the horizontal timing signal, and the first NAND gate circuit of which comprises: an odd number of serial-connected first inverters for receiving the horizontal timing signal to generate an inverse signal of the horizontal timing signal; a second NAND gate coupled to the odd number of serial-connected first inverters, wherein a first terminal of the second NAND gate receives the inverse signal of the horizontal timing signal and a second terminal of the second NAND gate receives the complementary horizontal timing signal for generating a first output signal; and a third inverter coupled to the second NAND gate for receiving the first output signal to generate an updated horizontal timing signal, wherein the timing signal adjusting circuit comprises a second NAND gate circuit for adjusting the duty cycle of the complementary horizontal timing signal, and the second NAND gate circuit of which comprises: an odd number of serial-connected fourth inverters for receiving the complementary horizontal timing signal to generate an inverse signal of the complementary horizontal timing signal; a fifth NAND gate coupled to the odd number of serial-connected fourth inverters, wherein a first terminal of the fifth NAND gate receives the inverse signal of the complementary horizontal timing signal and a second terminal of the fifth NAND gate receives the horizontal timing signal for generating a second output signal; and a sixth inverter coupled to the fifth NAND gate for receiving the second output signal to generate an updated complementary horizontal timing signal.