Patent ID: 8046643

Claim:
An apparatus comprising: a controller configured to (i) present one or more commands and (ii) receive one or more responses; a plurality of transport circuits each configured to (i) receive said one or more commands, (ii) present said one or more responses, and (iii) generate one or more control signals, wherein said plurality of transport circuits are connected to form a pipeline chain with said controller connected to an end of the chain and each of said plurality of transport circuits are further configured to respond to a relevant one of said one or more commands, pass non-relevant ones of said one or more commands to another transport circuit, and pass said one or more responses along the chain to said controller; and a plurality of memory-controlling circuits, each of said plurality of memory-controlling circuits coupled to a respective one of the plurality of transport circuits and configured to (i) generate one or more memory access signals in response to said one or more control signals, (ii) receive one or more memory output signals from a respective memory in response to said one or more memory access signals, and (iii) generate a respective one of said one or more responses in response to said one or more memory output signals; wherein (i) each respective memory is independently sized and (ii) said controller provides a common testing routine for each respective memory that is adjusted for the size of each respective memory by said memory-controlling circuits.