Patent ID: 7768845

Claim:
A memory, comprising: bit lines and word lines arranged to intersect with each other at intersectional positions; and memory cells respectively arranged on the intersectional positions between the bit lines and the word lines, wherein: the memory is configured to perform a read operation, a first rewrite operation, and a second rewrite operation if data of the memory cells is read; the memory is further configured to start the read operation, the first rewrite operation, and the second rewrite operation by respectively changing voltages applied to the bit lines and the word lines to a first voltage in response to the read operation, to a second voltage in response to the first rewrite operation, and to a third voltage in response to the second rewrite operation the memory is further configured to directly change the voltages applied to the bit lines and the word lines from the first voltage, in response to the read operation, to the second voltage, in response to the first rewrite operation; and the memory is further configured to directly change the voltages applied to the bit lines and the word lines from the second voltage, in response to the first rewrite operation, to the third voltage, in response to the second rewrite operation.