Patent ID: 7929658

Claim:
A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a driving control voltage and a first clock, wherein the Nth gate line is employed to deliver the Nth gate signal; a carry unit for generating a preliminary start pulse signal according to the driving control voltage and the first clock; a carry control unit, electrically connected to the carry unit for receiving the preliminary start pulse signal, for outputting the preliminary start pulse signal to become the an Nth forward start pulse signal or an Nth backward start pulse signal according to a first bias and a second bias; an input unit, electrically connected to an (N−1)th shift register stage and an (N+1)th shift register stage of the shift register stages for receiving an (N−1)th forward start pulse signal and an (N+1)th backward start pulse signal respectively, for inputting the (N−1)th forward start pulse signal having high voltage level or the (N+1)th backward start pulse signal having high voltage level to become the driving control voltage; a control unit for generating a control signal according to the first clock, the Nth gate signal and the driving control voltage; a first pull-down unit, electrically connected to the control unit, the Nth gate line and the carry unit, for pulling down the Nth gate signal according to the control signal, a second clock, or a fourth clock, and for pulling down the preliminary start pulse signal according to the fourth clock; and a second pull-down unit, electrically connected to the input unit and the Nth gate line, for pulling down the driving control voltage and the Nth gate signal according to a third clock; wherein N is a positive integer.