Patent ID: 8050355

Claim:
A transmitter using pseudo-orthogonal code, comprising: a serial-to-parallel converter for converting serial transmission data into 9-bit parallel data; and a pseudo-orthogonal code memory for receiving the parallel data from the serial-to-parallel converter and outputting 16-bit pseudo-orthogonal code by using the parallel data as addresses, wherein the pseudo-orthogonal code memory is configured to generate an output code having a relationship to the input address as expressed in the following equation: c ( i )=0.5×((−1) b 2 ⊕(i 1 b 1 )⊕(i 0 b 0 ) (−1) b 5 ⊕i 2 ⊕(i 1 b 4 )⊕(i 0 b 3 ) (−1) b 8 ⊕i 3 ⊕(i 1 b 7 )⊕(i 0 b 6 ) (−1) ( b 2 ⊕b 5 ⊕b 8 )⊕i 3 ⊕i 2 ⊕(i 1 (b 1 ⊕b 4 ⊕b 7 ))⊕(i 0 (b 0 ⊕b 3 ⊕b 6 )) ) where C(i) is a pseudo-orthogonal code value, i is each bit of the pseudo-orthogonal code, 0≦i≦15, and b 0 -b 8 are a transmission data bit stream input in the memory as addresses.