Patent ID: 8704358

Claim:
A method for forming an integrated circuit having a surface capable of being placed on another integrated circuit, on a printed circuit, or on a package, and having its other surface capable of receiving an additional integrated circuit, the method comprising the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels) on said front surface and leveling said surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling said surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.