Patent ID: 8072032

Claim:
A semiconductor integrated circuit device, comprising: a CMOS circuit that comprises: a well region of a first conductivity type formed in a band form in a substrate; a well region of a second conductivity type formed in a band form in said substrate, said well region of the second conductivity type being arranged in parallel with and adjacent to said well region of the first conductivity type; a first diffusion region of the first conductivity type formed in said well region of the first conductivity type and connected to a first back bias supplying power supply line that supplies a back bias to be supplied to said well region of the first conductivity type; first and second power supply lines that supply power to said CMOS circuit; and a MOSFET of the second conductivity type formed in said well of the first conductivity type, a gate and a drain of the MOSFET of the second conductivity type being connected to the well region of the first conductivity type through a second diffusion region of the first conductivity type formed in the well region which is not connected to the first back bias supplying power supply line, and a source of the MOSFET of the second conductivity type being connected to the first power supply line.