Patent ID: 7538408

Claim:
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a first region of a second conductivity type selectively provided in a surface layer on a side of a first principal surface of the semiconductor substrate; a second region of a second conductivity type provided in the surface layer on the side of the first principal surface of the semiconductor substrate apart from the first region; a third region of the first conductivity type provided between the first region and the second region in the surface layer on the side of the first principal surface of the semiconductor substrate, the third region having an impurity concentration higher than the semiconductor substrate; a first electrode in contact with the third region; a second electrode in contact with a second principal surface of the semiconductor substrate and coupled to be at a potential equal to the potential of the first electrode; a third electrode in contact with the first region and coupled to a high side power supply; and a fourth electrode in contact with the second region and coupled to a low side power supply; wherein the distance between the first region and the second region is shorter than the diffusion length of minority carriers in the semiconductor substrate; wherein the distance between the first region and the second region is shorter than 100 μm; and wherein operation of a parasitic transistor formed between the first region the second region and the third region is inhibited.