Patent ID: 6838388

Claim:
A fabrication method of a semiconductor integrated circuit device, comprising the steps of: (a) depositing a silicon oxide insulating film over a patterned silicon nitride film with a doped polycrystalline silicon plug over a semiconductor substrate; (b) forming a hard mask over said silicon oxide insulating film; and (c) subjecting said semiconductor substrate to a plasma etching treatment through the hard mask as an etching mask using an etching gas containing a fluorocarbon gas, oxygen and a dilution gas to process said silicon oxide insulating film, so as to form a hole in said silicon oxide insulating film down to the patterned silicon nitride film in such a manner that an upper surface of the doped polycrystalline silicon plug is exposed, wherein a residence time of the etching gas within an etching chamber is set at 50 to 700 ms.