Patent ID: 7735030

Claim:
A method of simulating a restorable register in a power domain of an RTL (register transfer level) design, comprising: specifying the power domain in the RTL design, wherein the power domain includes one or more registers and is configured to change power levels separately from other portions of the RTL design; identifying the restorable register in the power domain, wherein the restorable register is updated during power-on operations in the power domain; simulating the restorable register in a power cycle, wherein using a computer for simulating the restorable register includes operations for: maintaining one or more backup values during a power-off operation for updating the restorable register after the power-off operation, corrupting the restorable register during the power-off operation, and updating the restorable register during a power-on operation after the power-off operation by using the one or more backup values; and saving one or more values from the simulated restorable register.