Patent ID: 8201038

Claim:
A computer-implemented method of monitoring reliability, functional, and structural performance of a semiconductor chip in order to recover from and prevent failure, said method comprising: executing computerized instructions stored within a computer storage medium within said semiconductor chip using a centralized programming interface within said semiconductor chip to issue stimulus to sensors and components within said semiconductor chip; monitoring said sensors and components within said semiconductor chip, using said centralized programming interface, to measure characteristics of said semiconductor chip in response to said stimulus, said sensors and components producing component outputs representing said characteristics; performing preventive and recovery actions including engineering evaluations to determine whether said component outputs are within predetermined limits, using said centralized programming interface; and reporting occurrences of instances of said component outputs being outside said predetermined limits, using said centralized programming interface, as reports to at least one of said computer storage medium, external test equipment and a computerized device separate from said semiconductor chip, said instructions causing said centralized programming interface to alter preventive and recovery actions, configurations, frequencies and types of said stimulus, said reports and said engineering evaluation depending upon whether said characteristics are within said predetermined limits.