Patent ID: 8168480

Claim:
A fabrication method for forming an integrated structure of an insulated gate bipolar transistor (IGBT) and a diode, the fabrication method comprising the steps of: providing a semiconductor substrate, the semiconductor substrate having a first conductivity type, and the semiconductor substrate comprising an upper surface and a lower surface; forming at least a first doped cathode region and at least a second doped cathode region in the semiconductor substrate, the first doped cathode region and second doped cathode region having a second conductivity type, and the first doped cathode region and second doped cathode region overlapping and contacting with each other, wherein a distance between the second doped cathode region and the lower surface is larger than a distance between the first doped cathode region and the lower surface, and an implanted area of the second doped cathode region is larger than an implanted area of the first doped cathode region; forming a drift epitaxial layer on the upper surface of the semiconductor substrate, the drift epitaxial layer having the second conductivity type; forming at least a gate insulating layer and at least a gate electrode on the drift epitaxial layer, the gate insulating layer being disposed between the drift epitaxial layer and the gate electrode; forming a doped base region in the drift epitaxial layer, the doped base region having the first conductivity type and being adjacently connected to the gate insulating layer; forming a doped source region in the doped base region, the doped source region having the second conductivity type and being adjacently connected to the gate insulating layer; forming a doped contact region in the doped base region, the doped contact region having the first conductivity type; forming a first conductive layer on the doped base region, the first conductive layer being electrically connected to the doped source region and the doped contact region; performing a thinning process on the lower surface of the semiconductor substrate until the first doped cathode region is exposed; and forming a second conductive layer on the lower surface of the semiconductor substrate, the second conductive layer being electrically connected to the first doped cathode region and the semiconductor substrate.