Patent ID: 6857061

Claim:
An information processor, including a decoder for decoding instructions including at least some graphics instructions and at least one paired singles instruction, wherein the decoder is operable to decode a 32-bit paired singles floating point add instruction, wherein bits 0 - 5 encode a primary op code of 4, bits 6 - 10 designate a floating point destination register for storing a pair of 32-bit single-precision floating point values resulting from the paired singles floating point add instruction, bits 11 - 15 designate a floating point source register storing a pair of 32-bit single-precision floating point values, bits 16 - 20 designate a further floating point source register storing a pair of 32-bit single-precision floating point values, bits 21 - 25 encode a reserved field of “00000”, bits 26 - 30 encode a secondary op code of 2 , and bit 31 comprises a record bit indicating updating of a condition register.