Patent ID: 8005885

Claim:
An arithmetic unit configurable to perform directed rounding emulation for rounding a result of an arithmetic computation, said arithmetic unit comprising: an instruction decoder configured to decode an instruction to extract rounding control information, wherein said rounding control information is a single rounding control bit, wherein said single rounding control bit consists of: (a) a first state specifying a first rounding mode for said result; and (b) a second state specifying a second rounding mode for said result and invoking emulated rounding for said result; and a directed rounding emulator configured to: (1) determine an emulated rounding mode based on a context of said arithmetic computation when said single rounding control bit is in said second state; and (2) adjust said result toward an adjusted result in accordance with said emulated rounding mode; wherein said emulated rounding mode is one of a third rounding mode and a fourth rounding mode; wherein said first rounding mode, said second rounding mode, said third rounding mode, and said fourth rounding mode are different from one another; and wherein said third rounding mode is a round-to-negative infinity rounding mode and said fourth rounding mode is a round-to-positive infinity rounding mode, said adjusted result is one of a first value and a second value, and said first value represents negative infinity (“−INF”) and said second value represents positive infinity (“+INF”).