Patent ID: 7681057

Claim:
A controller for a non-volatile memory system, comprising: a system bus; a power management system in communication with the system bus and comprising a clock oscillator adapted to selectively output a fundamental clock signal, a phase-locked loop adapted to selectively output a second clock signal in response to the fundamental clock signal, and a system clock control adapted to selectively distribute a system clock signal in response to the second clock signal; a microprocessor in communication with the system bus; a first interface in communication with the system bus and adapted for communication with a non-volatile memory device; and a second interface in communication with the system bus and adapted for communication with a host system; wherein the power management system is adapted to monitor events from sources including at least the first interface and the second interface; wherein the power management system is further adapted to select one of a plurality of successive power-down modes in response to the events; wherein, in a first power-down mode, the controller is adapted to provide for normal operation; wherein, in a second power-down mode, the microprocessor is disabled; wherein, in a third power-down mode, the system clock control is further disabled; wherein the phase-locked loop is configured to receive the fundamental clock signal from the clock oscillator and to generate the second clock signal by directly multiplying the fundamental clock signal by a multiplication factor that is received at an input of the phase-locked loop; and wherein the power management system is further adapted to alter the multiplication factor in response to one or more of the events.