Patent ID: 7231414

Claim:
An apparatus for performing addition of propagate, kill, and generate recoded numbers, said apparatus comprising: circuitry configured to receive at least a first operand, a second operand, and a carry-in bit, the first and second operands comprising respective first and second propagate, kill, and generate recoded number representations of respective first and second binary operands; a first carry-save adder configured to add said first operand and said second operand to generate a third propagate, kill, and generate recoded number representation and a carry-out bit; and a modified carry-save adder configured to receive the third propagate, kill, and generate recoded number representation from the first carry-save adder and the carry-in bit from the circuitry, add the separate propagate, kill, and generate bits of the third propagate, kill, and generate recoded number representation with the carry-in bit to generate a sum value and a carry value, wherein the circuitry provides the carry-out bit from the first carry-save adder at a first output and the carry value from the modified carry-save adder at a second output, wherein each of the propagate, kill, and generate recoded number representations, including the first, second, and third propagate, kill, and generate recoded number representations, has a respective kill bit, a respective propagate bit, and a respective generate bit that are indicative of a respective coded logical value having a plurality of bits, wherein the kill bit, if set, indicates that each of the bits of the respective coded logical value is not set, wherein the propagate bit, if set, indicates that only one of the bits of the respective coded logical value is set, and wherein the generate bit, if set, indicates that each of the bits of the respective coded logical value is set.