Patent ID: 8293580

Claim:
A method of forming a semiconductor package, comprising: forming a plurality of through silicon vias (TSVs) through an upper surface of a wafer, the wafer having a plurality of first semiconductor chips, the plurality of TSVs being formed to have lower ends buried in the wafer and upper ends exposed by one surface of the wafer; forming an encapsulant on the wafer using a wafer level molding process, the encapsulant being formed to cover the upper ends of the TSVs; partially removing a lower surface of the molded wafer to expose the lower ends of the TSVs; forming openings through the encapsulant after the partially removing a lower surface of the molded wafer, the openings being aligned on the upper ends of the TSVs; dividing the encapsulant with the openings and the wafer to form a plurality of first semiconductor packages; and stacking a second semiconductor package on a first semiconductor package selected from the plurality of first semiconductor packages, the second semiconductor package being electrically connected to the TSVs.