Patent ID: 8383501

Claim:
A method for fabricating a vertical field effect transistor array semiconductor structure comprising: forming at least one first composite mask having a first diameter on one portion of a semiconductor substrate and at least one second composite mask having a second diameter different from the first diameter on another portion of said semiconductor substrate, wherein said first composite mask comprises a first pillar mask layer, a second pillar mask layer located on an exposed topmost surface of the first pillar mask layer, and a first spacer layer located on sidewall surfaces of the first pillar mask layer and the second pillar mask layer, and said second composite mask comprises another first pillar mask layer, another second pillar mask layer located on an exposed topmost surface of the another first pillar mask layer, another first spacer layer located on sidewall surfaces of the another first pillar mask layer and the another second pillar mask layer, and a second spacer layer located on exposed sidewall surfaces of said another first spacer layer; and etching the semiconductor substrate while using the first composite mask and the second composite mask as an etch mask layer to provide a corresponding first semiconductor pillar having a first linewidth and a second semiconductor pillar having a second linewidth different from the first linewidth, wherein each of said first linewidth and said second linewidth is greater than a separation distance from an adjacent semiconductor pillar.