Patent ID: 8131814

Claim:
A system comprising: a processor; a dynamic pinning remote direct memory access helper on the processor core; and a network interface controller comprising: a network interface to connect the network interface controller to a second network interface controller on a remote computing node; a system bus interface to connect the network interface controller to the processor via a system bus; buffers usable as cacheable memory regions for the processor; and a direct memory access engine communicatively coupled to the dynamic pinning remote direct memory access helper via the system bus interface and to receive a request for data, the dynamic pinning remote direct memory access helper to: decompose the data to be transferred through a remote direct memory access into at least first and second remote sections, each of the first and second sections being less than an entire memory page; pin the first remote section until a first portion of the data from the first remote section is transferred to the remote computing node; after the first portion of the data is transferred, release the first remote section; after releasing the first remote section, pin the second remote section until a second portion of the data from the second remote section is transferred to the remote computing node; and after the second portion of the data is transferred, release the second remote section, wherein the first section is pinned at a first time and for a first duration sufficient to transfer the first section, and the second section is pinned at a second time for a second duration sufficient to transfer the second section.