Patent ID: 8060698

Claim:
A cache controller that controls a cache memory including a plurality of ways, each of the plurality of ways includes a plurality of blocks that stores therein entry data and each of the plurality of blocks includes a protected area protected by an error correction code and a non-protected area that is not protected by the error correction code, the cache controller comprising: a detecting unit that detects a failed block; a writing unit that writes a first data into the protected area of the failed block indicating the failed block is to be degraded and a second data into the non-protected area of the failed block indicating the failed block is to be degraded, when the failed block is detected by the detecting unit; a reading unit that reads an entry data from a block; a determining unit that determines whether the block from which the entry data is read by the reading unit is to be degraded based on whether the read entry includes the first data and the second data; and a degradation unit that degrades the failed block based on a determination result determined by the determining unit.