Patent ID: 8219851

Claim:
A system, comprising: a host processor having one or more sockets, each socket coupled with memory; a first region of the memory reserved for use by an on-board processing unit during runtime; n-1 additional reserved regions of memory, wherein the first region and the n-1 additional reserved regions of memory are invisible to and inaccessible by an operating system executing on the host processor; logic for error correction of the memory, wherein the logic for error correction maintains a count of correctable and uncorrectable errors within the memory; and migration logic configured to migrate data in the first region of memory to one of the n-1 additional regions of memory, the migration responsive to the count of correctable errors reaching a pre-determined threshold, and wherein the migration logic is further configured to notify the on-board processing unit of the one of the n-1 additional regions of memory to be used during runtime instead of the first region of memory, wherein the migration logic is further configured to initiate a change of power state of the on-board processing unit to cause the on-board processing unit to save the data in the first region of memory to local memory, and then initiate a second active power state of the on-board processing unit, after the notifying the on-board processing unit of the one of the n-1 additional regions of memory to be used during runtime.