Patent ID: 7871869

Claim:
A method for fabricating an extremely-thin-silicon-on-insulator transistor, the method comprising the steps of: forming a gate stack on a silicon layer that is above a buried oxide layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer; forming a first nitride layer on the silicon layer and the gate stack; forming an oxide layer on the first nitride layer; forming a second nitride layer on the oxide layer; etching the first nitride layer and the oxide layer so as to form a nitride liner and an oxide liner adjacent to the gate stack, and etching the second nitride layer so as to form a first nitride spacer adjacent to the oxide liner; epitaxially forming a raised source/drain region adjacent to the nitride liner, the oxide liner, and first nitride spacer; and implanting ions into the raised source/drain region using the first nitride spacer to align the implantation.