Patent ID: 8753900

Claim:
A computer-implemented method for forming an integrated circuit, comprising: receiving one or more metal density specifications, wherein the metal density specifications define parameters for determining a dummy fill pattern for the integrated circuit, wherein at least one of the parameters is a predefined instance threshold; logically dividing the integrated circuit in a plurality of windows, and for each of the windows: determining one or more signal paths for transferring signals of the integrated circuit between a plurality of cells within a current window of the plurality of windows that each define respective regions of the integrated circuit, wherein the signal paths between the plurality of cells are determined based on the one or more electrical characteristics; selecting the dummy fill pattern for the integrated circuit by comparing a total number of cells within the current window to the predefined instance threshold indicating metal congestion within the current window; extracting an RC of the signal paths and the selected dummy fill pattern; determining whether one or more timing requirements of the integrated circuit are satisfied based on the RC; upon determining that the one or more timing requirements are not satisfied, re-routing one of the signal paths extending between at least two of the cells and optimizing the dummy fill pattern associated with the re-routed signal path; after optimizing the dummy fill pattern, determining whether the one or more timing requirements are satisfied based on a new RC of the re-routed signal path and the optimized dummy fill pattern; and upon determining that the one or more timing requirements are satisfied, saving the corresponding dummy fill pattern in a memory device.