Patent ID: 7235425

Claim:
A method of fabricating a semiconductor device, comprising: mounting a first semiconductor chip on a wiring substrate; bonding a spacer having a first main surface and a second main surface opposing the first main surface so that the first main surface contacts the first semiconductor chip; bonding a second semiconductor chip having a third main surface larger than the first main surface, onto the second main surface via a layer of a die bonding material selectively formed on a part of the third main surface to cover at least those portions of the third main surface which are in contact with the second main surface, wherein: the layer of the die bonding material is formed on a part of the third main surface by screen printing, and the second semiconductor chip is bonded thereto; and the layer of the die bonding material is selectively applied on a region of the third main surface defined by curved lines connecting adjacent apexes of a polygon, wherein the center of each curved line runs into an inner area of lines connecting adjacent apexes, which correspond to a beginning and the end point of each curved line; integrating semiconductor elements in a first surface of a wafer; forming recesses in the first wafer surface; bonding a surface protection sheet onto the first wafer surface; grinding a second wafer surface opposing the first wafer surface so as to cut off the second semiconductor chip from the wafer.