Patent ID: 7521333

Claim:
A method of forming a trench isolation structure in a semiconductor device, the method comprising: defining a cell region, a low voltage region and a high voltage region in a semiconductor substrate, the cell region, the low voltage region and the high voltage region including respective sites for a cell trench isolation region, a low voltage trench isolation region and a high voltage trench isolation region, respectively; forming a mask layer on the substrate; patterning the mask layer to form a mask pattern that exposes a portion of the substrate in the cell region and a portion of the substrate in the high voltage region; forming a resist pattern that covers the exposed portion of the substrate in the cell region and that exposes a portion of the mask pattern in the low voltage region and a portion of the substrate in the high voltage region; etching exposed portions of the mask pattern and the substrate using the resist pattern as an etch mask to expose a portion of the substrate in the low voltage region and to form a recess at the site for the high voltage trench isolation region; simultaneously etching portions of the substrate in the low voltage region and the recess without etching the site for the cell trench isolation region to form a low voltage trench at the site for the low voltage trench isolation region in the low voltage region and a high voltage trench deeper than the low voltage trench at the site for the high voltage trench isolation region in the high voltage region; simultaneously etching portions of the substrate in the cell region, the low voltage trench and the high voltage trench to form a cell trench at the site for the cell trench isolation region in the cell region and to deepen the low voltage trench in the low voltage region and the high voltage trench in the high voltage region; and filling the cell trench, the low voltage trench and the high voltage trench with insulating material to form a trench isolation structure comprising the cell trench isolation region in the cell region, the low voltage trench isolation region in the low voltage region, and the high voltage trench isolation region in the high voltage region.