Patent ID: 8194470

Claim:
A method of operating a NAND flash memory array that has word lines of a first block connected to word lines of a second block, the first block and the second block sharing a plurality of bit lines, the first block having a first shield plate and the second block having a second shield plate, the first block having first non-volatile storage elements with first floating gates, the second block having second non-volatile storage elements with second floating gates, comprising: erasing data in the first block while maintaining data in the second block by applying a first voltage to the first shield plate while applying a second voltage to the second shield plate, the first shield plate capacitively couples to the first floating gates to modify voltage of the first floating gates, the second shield plate capacitively couples to the second floating gates to modify voltage of the second floating gates to maintain data in the second block; and maintaining a common voltage on the word lines of the first block and the word lines of the second block during the erasing.