Patent ID: 7068560

Claim:
A processing system, comprising: a processor; and a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising: an array of memory cells; control circuitry to read, write and erase the memory cells; address circuitry to latch address signals provided on address input connections; and a driver for the array, comprising: an enable circuit providing an enable signal; a pull down transistor having its gate connected to the enable signal, to ground an output node when the enable signal is disabled; a pass transistor having its gate connected through a first p-type pull-up transistor connected between a pumped voltage and the gate of the pass transistor; an inverter connected between the enable circuit output and the pass transistor; a second pull down transistor connected between ground and the gate of the pass transistor; a series connection of two inverters connected between the output of the first inverter and the gate of the second pull down transistor; and a second p-type transistor connected between the pumped voltage and the output node, the gate of the second p-type transistor connected to the gate of the pass transistor.