Patent ID: 8383479

Claim:
A method of fabricating non-volatile memory, comprising: forming a plurality of isolation trenches in a substrate, the isolation trenches elongated in a first direction with a spacing between isolation trenches adjacent in a second direction perpendicular to the first direction, the isolation trenches being filled with an isolation material, the isolation material in each trench including a portion extending above a surface of the substrate; forming a tunnel dielectric layer over a surface of the substrate; self-aligning a nanostructure coating over the tunnel dielectric layer between adjacent portions of the isolation material extending from each isolation trench; forming an intermediate dielectric layer over the nanostructure coating; forming a control gate layer over the intermediate dielectric layer; forming a pattern including a plurality of strips elongated in the second direction with spacing therebetween in the first direction; and etching the control gate layer, the intermediate dielectric layer, and the nanostructure coating according to the pattern, wherein etching the control gate layer forms a plurality of word lines elongated in the second direction and etching the nanostructure coating forms a plurality of columns of charge storage regions.