Patent ID: 7715242

Claim:
An erasing method of the non-volatile memory, wherein the non-volatile memory has a control gate disposed in a substrate; a floating gate disposed over the control gate and located over a portion of the substrate and comprising a coupling part and a gate part; a gate oxide layer disposed between the floating gate and the substrate; a source region disposed in the substrate and neighboring to one side of the gate part of the floating gate; a drain region disposed in the substrate and neighboring to the other side of the gate part of the floating gate; a first dielectric layer disposed on the floating gate; a second dielectric layer disposed on sidewalls of the floating gate; and an erase gate disposed over the coupling part of the floating gate and covering the second dielectric layer, the erasing method comprises: applying a first voltage on the control gate, applying a second voltage on the drain, applying a third voltage on the source, applying a fourth voltage on the erase gate, and applying a fifth voltage on the substrate, such that the electrons are drawn from the floating gate to the erase gate to be erased.