Patent ID: 8924826

Claim:
An apparatus comprising: physical medium dependant (PMD) sublayer logic that is configured to communicate with a communications medium; PMA sublayer logic that is coupled to the PMD logic; PCS sublayer logic that is configured to communicate with an interface; and forward error correction (FEC) sublayer logic having: a decoder that is coupled to the PMA sublayer logic and the PCS sublayer logic; and an encoder having: a formatter that is coupled to the PCS sublayer logic by way of a first bus having a first width; a second bus having a second width that is coupled to the formatter; a transcoder that is coupled to the second bus, wherein the transcoder is configured to generate a transcode bit for each frame; a syndrome generator that is coupled to the second bus, wherein the syndrome generator uses a number of bits that are equal to the second width, and wherein the syndrome generator is configured to generate a set of parity bits for each data word; and a converter that is coupled to the second bus and that is coupled to the PMA sublayer logic by way of a third bus having the first width, wherein the converter is configured to generate a frame having a data payload concatenated with the set of parity bits, wherein the encoder further comprises a scrambling circuit that is coupled to the third bus, wherein the scrambling circuit further comprises: a pseudorandom number generator; and a combiner that is coupled to the pseudorandom number generator and the third bus, wherein the formatter further comprises an input register, wherein the first width is 66 bits, and wherein the second width is 65 bits.