Patent ID: 8437429

Claim:
A data processing apparatus, comprising: a clock signal generation unit configured to receive a data signal comprising a preamble signal, information about DC balance codes for DC balance, an embedded clock signal between the DC balance codes, and information about serialized valid data, to generate a synchronous clock signal that is synchronized with the serialized valid data based on the data signal, and to generate at least one sample clock signal based on the synchronous clock signal; a data processor configured to deserialize the serialized valid data based on the at least one sample clock signal, to decode deserialized data based on the DC balance codes, and to output decoded data; wherein the clock signal generation unit comprises: a clock signal restoring block configured to receive the data signal and to generate the synchronous clock signal synchronized with the serialized valid data based on the embedded clock signal in the data signal; and a clock generator configured to generate the at least one sample clock signal in response to the synchronous clock signal; wherein the clock signal restoring block comprises: a delay signal generation unit configured to delay the data signal a predetermined period of time after the clock generator is locked in response to the preamble signal comprising a training signal and to output a delayed data signal; and a synchronous clock signal generation unit configured to detect the embedded clock signal in the delayed data signal in response to the delayed data signal and to generate the synchronous clock signal based on a result of the detection, wherein the delay signal generation unit controls the DC balance codes comprised in the delayed data signal to transition from a first logic level to a second logic level.