Patent ID: 7538411

Claim:
An integrated circuit, comprising: a substrate comprising a surface; wordline stacks arranged parallel at a distance from one another on the surface; bitlines arranged transversely to the wordlines at a distance from one another; source/drain regions formed as doped regions in the vicinity of the wordline stacks; a layer sequence comprising a bottom electrode layer, a resistive layer, and an upper electrode layer disposed between a plurality of the source/drain regions and the bitlines, wherein the resistive layer is disposed in a plane that is vertical to the substrate surface and at least a part of the resistive layer is disposed in a recess of the substrate surface; the upper electrode layer comprising separate sections; the bottom electrode layer comprising separate sections corresponding to the sections of the upper electrode layer; a bitline connecting a plurality of sections of the upper electrode layer; and source lines arranged parallel to the wordline stacks, the source lines connecting further pluralities of the source/drain regions.