Patent ID: 8120957

Claim:
A memory system comprising: a nonvolatile semiconductor memory; and a memory controller; wherein the nonvolatile semiconductor memory comprises, a memory cell array in which a plurality of electrically rewritable memory cells are arranged, a plurality of first data storing units which store a page unit of read or write data to be simultaneously read from or written to the memory cells, a part of the plurality of first data storing unit constituting a column, a second data storing unit which is arranged per the column and which stores defect column information indicating whether or not the column has a defect, and an output circuit which outputs the defect column information stored in the second data storing unit outside the nonvolatile semiconductor memory; wherein the memory controller receives the defect column information from the nonvolatile semiconductor memory and manages defect column addresses, the total number of columns in the page unit is equal to a sum of the number of a first column area and the number of a second column area, the number of the first column area is equal to the maximum number of columns which continuously output data from or input data to the nonvolatile semiconductor memory, and the number of the second column area is equal to the number of columns only used within the nonvolatile semiconductor memory.