Patent ID: 7633114

Claim:
A semiconductor device comprising: a first region of a first conductivity type in a semiconductor substrate; at least one pair of parallel implant region lines of a second conductivity type in said first region; and for each pair of parallel implant region lines, a column of plural non-volatile memory cells overlapping the respective pair of implant region lines, wherein one of the implant region lines of the pair includes a respective source region for each of the memory cells of the column, and the other implant region line of the pair includes a respective drain region for each of the memory cells of the column, with a respective subportion of the first region between the source and drain region of each of the memory cells comprising a channel region for the respective memory cell, wherein each of the non-volatile memory cells comprises: a tunnel dielectric layer in contact with one of the implant region lines of the pair of implant region lines; an electrically isolated floating gate over and in contact with the tunnel dielectric layer and extending only part of a distance between the source and drain regions; a dielectric structure over and in contact with the floating gate and extending only part of the distance between the source and drain regions; a control gate over and in contact with the dielectric structure and extending the entire distance between the source and drain regions; and a gate dielectric layer between the control gate and a surface of the first region.