Patent ID: 7685333

Claim:
A method comprising: selecting, at a memory controller, a first set of timing parameters relating to memory control signals from a plurality of sets of timing parameters associated with a particular memory operation in one or more tables at the memory controller; communicating with a flash memory device of the computational system by generating memory control signals at the memory controller based on a clock signal and the first set of timing parameters; determining, at the memory controller, an error rate associated with communicating with the flash memory device; selecting, at the memory controller, a second set of timing parameters relating to memory control signals from the plurality of sets of timing parameters based on the determined error rate, wherein selecting the second set of timing parameters includes selecting a set of timing parameters faster than the first set of timing parameters when the determined error rate is below a threshold, and selecting a set of timing parameters slower than the first set of timing parameters when the determined error rate is above the threshold; and communicating with the flash memory device of the computational system by generating memory control signals based on the clock signal and the second set of timing parameters.