Patent ID: 7444481

Claim:
An apparatus for interfacing a packet processing engine with a memory system comprising: a first data storage element storing information based upon a memory read comprising a first packet identifier, wherein said first data storage element comprises read data; a second data storage element storing information based upon a memory write comprising a second packet identifier, wherein said memory write comprises memory write data; read processing logic coupled to said first data storage element and said second data storage element, wherein said first data storage element is modified based on said memory read and said second data storage element is searched based on said memory read; write processing and conflict detection logic coupled to said first data storage element and said second data storage element, wherein said second data storage element is modified based on said memory write and said first data storage element is searched based on said memory write, and wherein a determination is made whether a memory conflict exists between said memory read and said memory write; logic for signaling a restart coupled to said write processing and conflict detection logic and utilizing said first associated packet identifier; wherein if a memory conflict is detected, said memory write data is compared to said read data and a restart is not signaled if said memory write data matches said read data.