Patent ID: 7092314

Claim:
A semiconductor memory device communicating data with outside in synchronization with a rise and a fall of an external clock, comprising: a plurality of memory cells storing data; an internal circuit inputting/outputting data to/from said plurality of memory cells; and a control circuit controlling an operation of said internal circuit in an operation unit being consecutive, multiple cycles of said external clock; wherein said control circuit includes an internal command generating circuit generating an internal control command to instruct an operation of said internal circuit based on an externally input control command, said internal command generating circuit carries out one of first and second processings, upon receiving a plurality of control commands corresponding to a plurality of internal control commands generated within said multiple cycles, in said first processing, an internal control command corresponding to any one of said plurality of control commands is generated, while at least one, other control command is invalidated, and in said second processing, said plurality of control commands are all invalidated.