Patent ID: 7738299

Claim:
An erase discharge control method of a nonvolatile memory device including a memory array in which a plurality of cells are arranged in a matrix form, each of the cells having a floating gate type field effect transistor of which a control gate, a drain and a source are respectively connected to a word line, a bit line and a ground line, the source and drain being disposed in a P-well provided in an N-well of a semiconductor substrate, the method comprising: drawing charges accumulated in a floating gate of the floating gate type field effect transistor into the semiconductor substrate to perform an erase operation by applying a first voltage to the word line, a second voltage to the N-well and the P-well, and opening the bit line and the ground line; grounding the word line during a discharge operation, the discharge operation following the erase operation, the discharge operation discharging charge accumulated during the erase operation; and grounding the N-well and the P-well to discharge charges accumulated in the N-well and P-well, wherein a discharge transistor connected to the bit line is turned on during the discharge operation before the grounding of the word line or simultaneously with the grounding of the word line.