Patent ID: 7521977

Claim:
A variable delay circuit comprising: a first loading node and a second loading node; a first common node and a second common node; a loading circuit including a first loading unit disposed between a first power source and the first loading node; and a second loading unit disposed between the first power source and the second loading node; a first input circuit including a first input transistor disposed between the first loading node and the first common node; and a second input transistor disposed between the second loading node and the first common node, the first input transistor and the second input transistor being gated by a first differential input signal and a second differential input signal, respectively; a second input circuit including a third input transistor disposed between the first loading node and the second common node; and a fourth input transistor disposed between the second loading node and the second common node, the third input transistor and the fourth input transistor being gated by a third differential input signal and a fourth differential input signal, respectively; a first source circuit disposed between the first common node and a second power source; and a second source circuit disposed between the second common node and the second power source, wherein the first source circuit comprises a first current source and a second current source connected in electrical parallel with each other and disposed between the first common node and the second power source, and wherein the second source circuit comprises a third current source and a fourth current source connected in electrical parallel with each other and disposed between the second common node and the second power source, wherein the second current source and the third current source are supplied with a bias current.