Patent ID: 8190860

Claim:
A system, comprising: a processor comprising a pipeline, wherein the pipeline comprises: a plurality of pipeline stages, wherein the plurality of pipeline stages comprise a prior pipeline stage and a subsequent pipeline stage, wherein the prior pipeline stage performs a first set of computational operations if a first data-dependent instruction is being executed and a first mode has been selected, and wherein the subsequent pipeline stage performs the first set of computational operations if the first data-dependent instruction is being executed and a second mode has been selected; feedforward logic capable of providing computational results obtained from execution of a previous instruction by the subsequent pipeline stage to the prior pipeline stage for use during execution of the first data-dependent instruction; and feedforward control circuitry which selects a first set of feedforward control values to provide to the feedforward logic during execution of the first data-dependent instruction if the first mode has been selected, and which selects a second set of feedforward control values to provide to the feedforward logic during execution of the first data-dependent instruction if the second mode has been selected, wherein the first set of feedforward control values and the second set of feedforward control values are different.