Patent ID: 6944032

Claim:
An interconnect adapted for use with a pixel layer of a pixel web, comprising: an interconnect substrate including a plurality of conductive leads; a plurality of contact vias formed on and extending from said interconnect substrate, said plurality of contact vias being formed in a predetermined pattern on said interconnect substrate and being in electrical communication with said plurality of conductive leads of said interconnect substrate; and a patterned spacer of a thickness substantially equal to a height of said plurality of contact vias, said patterned spacer including a plurality of through-holes also formed according to said predetermined pattern and having a dimension substantially equal to a dimension of said plurality of contact vias; wherein said interconnect substrate and said patterned spacer are capable of being assembled onto said pixel layer of said pixel web, with said patterned spacer being in a middle position and said plurality of contact vias extending through said plurality of through-holes of said patterned spacer to contact corresponding cathode portions on said pixel layer.