Patent ID: 7812912

Claim:
A display panel, comprising: a substrate having a plurality of pad regions located in a non-display region of the substrate, wherein a plurality of first pins with the same length is disposed in each of the pad regions, and a pin pitch between the two adjacent first pins, a width of each of the first pins, or both said pin pitch and said width vary with the positions where the first pins are disposed in a corresponding pad region, said pin pitch is calculated according to an effective equation Y=(Y2−Y1)*(X/X1) n +Y1, wherein Y is pin pitch, Y2 is an N th pin pitch, Y1 is a first pin pitch, X is the first pin of the pins, and X1 is a X1 th pin of the pins; and a plurality of driving chips disposed in the non-display region of the substrate, wherein each of the driving chips has a plurality of second pins, and each second pin is electrically connected to each first pin.