Patent ID: 7194717

Claim:
A layout method for a top module including instances of a base module in a memory matrix, said top module and said base module each including data pins and at least one control pin, data pins of said instances being replicated in said top module, a control signal being shared among said instances and said top module by tying together corresponding control pins of said instances and a corresponding control pin of said top module, comprising steps of: extending, at a library preparation stage, data pins and control pins of standard cells in said top module vertically for easy access; assigning positions for said data pins of said top module and said at least one control pin of said top module in said top module; arranging said instances within said top module; implementing signal routing for said instances and said top module; and performing power routing for said instances and said top module, wherein said assigning step comprises: grouping said data pins of said top module into a plurality of groups, each of said plurality of groups being suitable for connecting to one of said instances, relative positions of said data pins of said top module within said each of said plurality of groups being fixed; assigning positions for said plurality of groups uniformly across a width of said top module; and assigning said at least one control pin of said top module to at least one position available after said data pins of said top module are assigned positions.