Patent ID: 7598168

Claim:
A method of forming a dual damascene interconnection comprising the ordered steps of: (a) sequentially forming on a surface of a semiconductor substrate on which a lower metal wiring is formed a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer; (b) etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; (c) forming a sacrificial layer of HSQ or SOG within the via, wherein said HSQ or SOG sacrificial layer is a different material than the first intermetal dielectric, the second intermetal dielectric, or the capping layer; (d) etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; (e) removing portions of the sacrificial layer remaining within the via and on the capping layer using an etchant composition consisting essentially of NH 4 F, HF, H 2 O and a surfactant; and, (f) forming an upper metal wiring within a dual damascene pattern including the via and the trench.