Patent ID: 7005338

Claim:
A method for fabricating an integrated circuit comprising a first nonvolatile memory cell, the method comprising: forming a first trench in a top surface of a semiconductor substrate; forming a dielectric on a surface of the first trench; forming a conductive floating gate at least partially located in the first trench; wherein the first nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate, and comprises a second FET for controlling access to the first FET; wherein the method further comprises forming in the substrate: a first semiconductor region of a first conductivity type adjacent to the first trench and providing a first source/drain region for the first FET; a second semiconductor region of a second conductivity type adjacent to the first trench above the first semiconductor region and providing a channel region for the first FET; a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the first trench above the second semiconductor region and provides a second source/drain region for the first FET, wherein the third semiconductor region also provides a source/drain region for the second FET; a fourth semiconductor region of the second conductivity type adjacent to the third semiconductor region and providing a channel region for the second FET; and a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region and providing a source/drain region for the second FET; and wherein the method further comprises forming a conductive member having a portion overlying the first trench, wherein the conductive member provides a gate for the second FET; wherein the first and second source/drain regions of the first FET and the channel region of the first FET curve around the first trench.