Patent ID: 7755407

Claim:
A variable delay circuit that outputs an output signal delayed with respect to an input signal by a designated delay time, comprising: a delay controller that outputs a control voltage according to a set value of the delay time; a power current controlling MOS transistor that receives the control voltage at a gate thereof, and outputs a drain power current according to the control voltage; a correction section that is connected in parallel to a source and a drain of the power current controlling MOS transistor, and outputs a correction power current on a monotonic decrease as the drain power current increases in a range larger than a predetermined boundary power current within a normal usage range of the drain power current; and a delay element that runs an output power current resulting from adding the correction power current to the drain power current, between the delay element and an output terminal of the variable delay circuit, and outputs the output signal delayed by a time according to the output power current, when changing a signal value of the output signal according to the input signal.