Patent ID: 8201037

Claim:
A semiconductor integrated circuit comprising: a plurality of memories configured to store data; a built-in self-test circuit configured to perform a test for the plurality of memories, the built-in self-test circuit comprising: a test controller configured to perform the test and generate a memory selection signal selecting a memory to be tested from the plurality of memories; an address generator configured to generate write and read addresses; a data generator configured to generate write data and an expected output value of the memory corresponding to the write data; and a control signal generator configured to generate a control signal performing a write operation for the write data to the write address of the memory and a read operation for read address of the memory; and an analyzer configured to analyze a test result of the built-in self-test circuit, the analyzer comprising: a memory output selector configured to select output data of the plurality of memories based on the memory selection signal generated by the test controller; a bit comparator configured to compare the output data selected by the memory output selector with the expected output value generated by the data generator bit by bit; an error detection unit configured to determine whether there is an error in the memory based on a comparison result of the bit comparator; a plurality of pass/fail flag registers corresponding to the plurality of memories and configured to store a pass/fail flag of the error detection unit; a repair analyzer configured to analyze a memory error based on the comparison result of the bit comparator and generate a repair analysis result; a plurality of repair analysis result registers corresponding to the plurality of memories and configured to store the repair analysis result generated by the repair analyzer; and an output unit configured to output the pass/fail flag stored in the plurality of pass/fail flag registers and the repair analysis result stored in the plurality of repair analysis result registers.