Patent ID: 7170142

Claim:
A planar integrated circuit, comprising: a semiconductor substrate having a substrate surface; a waveguide buried in said substrate and comprising a core and a waveguide confiner around said core, said waveguide confiner including a ceiling; an electrode in said ceiling and contacting said core to form an interface between said electrode and said core, said interface defining a detector portion of said core, said detector portion of said core and said electrode comprising a Schottky barrier detector buried in said substrate; plural transistors formed in or over said substrate surface, each of said transistors comprising a source, a drain and a gate; an insulator layer overlying said waveguide and said plural transistors, said insulator layer having plural contact openings to respective ones of said source, drain and gate of respective ones of said transistors, to said electrode and to one of: (a) said semiconductor waveguide core, (b) said waveguide confiner; and a conductive interconnect layer formed over said insulator layer and comprising conductive contacts in said contact openings and conductive lines on said planar surface of said insulator layer connected to respective ones of said conductive contacts, at least one of said conductive lines forming a connection between said electrode and one of said source, drain or gate of one of said transistors.