Patent ID: 7149768

Claim:
A 3-input adder/subtractor unit, comprising: a first input for receiving a first operand A, a second input for receiving a second operand B, a third input for receiving a third operand C, and an add/subtract unit including: a control input for receiving a user-specified opcode, a first 3-to-2 carry-save adder for receiving a respective least significant bit of said operands or its complement, a Half Adder coupled to the first 3-to-2 carry-save adder and responsive to an output thereof and to a first bit of said opcode for outputting a least significant bit of a sum equal to A+B+C or A+B−C or A−B+C or A−B−C, a plurality of 3-to-2 carry-save adders each in respect of remaining bits of said operands for receiving a respective bit of said operands or its complement, a 2-input adder coupled to all of said 3-to-2 carry-save adders for receiving respective carry and save outputs thereof and computing respective bits of said sum apart from the least significant bit, and a logic circuit having inputs coupled to a carry out bit of the Half Adder and to a second bit of the opcode and being responsive to either or both of said input being at logic “1” for feeding a logic “1” bit to a carry input of the 2-input adder.