Patent ID: 8681162

Claim:
A multi-shader system in a programmable graphics processing unit (GPU) for processing video data, comprising: a first shader stage executed by the GPU, configured to receive slice data from a frame buffer and perform variable length decoding (VLD), wherein the first shader stage outputs data to a first buffer within the frame buffer; a second shader stage executed by the GPU, configured to receive the output data from the first shader stage and perform transformation and motion compensation on the slice data, wherein the second shader stage outputs decoded slice data to a second buffer within the frame buffer; a third shader stage executed by the GPU, configured to receive the decoded slice data and perform in-loop deblocking filtering (IDF) on the frame buffer; a fourth shader stage executed by the GPU, configured to perform post-processing on the frame buffer; and a scheduler executed by the GPU, configured to schedule execution of the shader stages, the scheduler comprising a plurality of counter registers; wherein execution of the shader stages is synchronized utilizing the counter registers, wherein the second shader stage outputs unfiltered YUV-based color space video data, wherein the third shader stage performs IDF on an entire frame of unfiltered YUV-based color space video data to generate the final YUV-based color space video data, and wherein the final YUV-based color space video data is cycled back to the second shader stage to undergo motion compensation.