Patent ID: 8693296

Claim:
A PLL circuit that extracts a synchronizing clock from an analog signal in which a channel frequency changes, said PLL circuit comprising: a phase synchronization loop having a loop gain and comprising: an A/D converter that converts the analog signal into a digital signal; a digital phase comparator that operates in synchrony with the synchronizing clock to output a phase error signal between the analog signal and the synchronizing clock based on the digital signal output from said A/D converter; a digital loop filter that operates in synchrony with the synchronizing clock to output a digital frequency value proportional to the channel frequency based on the phase error signal; a D/A converter that converts said digital frequency value into an analog frequency signal and outputs the analog frequency signal; and an oscillator that outputs the synchronizing clock having a frequency controlled based on the digital frequency value; and a loop-gain control unit that controls the loop gain of said phase synchronization loop based on said digital frequency value which is converted into said analog frequency signal by said D/A converter, wherein said loop-gain control unit comprises a multiplier that multiplies the phase error signal output from said digital phase comparator by a value corresponding to the digital frequency value output from said digital loop filter to output the multiplied value to said digital loop filter, said multiplier being provided between an output side of the digital phase comparator and an input side of the digital loop filter.