Patent ID: 7294790

Claim:
An electrical component contacting a packaged integrated circuit type device in determining the parasitic capacitance of an electrical lead of a packaged integrated circuit type device during the testing of the packaged integrated circuit type device, comprising: a substrate contacting a packaged integrated circuit type device in determining the parasitic capacitance of an electrical lead of a packaged integrated circuit type device during the testing of the packaged integrated circuit type device, the substrate including an upper surface, an insulative layer, and a conductive layer of material; a plurality of cavities extending into the substrate formed through the conductive layer of material to expose the insulative base layer of the substrate; a plurality of leads formed on the upper surface of the substrate in the conductive layer of material contacting a packaged integrated circuit type device, each lead isolated from another lead, each lead of the plurality of leads at least including a conductive trace formed on a surface of the substrate, a conductive via extending through the substrate having one end thereof electrically connected to the conductive trace, and a ball lead formed on an opposing surface of the substrate and in electrical communication with an opposing end of the conductive via, the plurality of leads contacting a packaged integrated circuit type device in determining the parasitic capacitance of an electrical lead of a packaged integrated circuit type device during the testing of the packaged integrated circuit type device; and a central electrically conductive plane formed on the upper surface of the substrate isolated from the plurality of leads, the central electrically conductive plane comprising a layer of electrically conductive metal formed on at least a portion of the upper surface of the substrate, the conductive trace of at least one lead of the plurality of leads electrically connected to the central electrically conductive plane, the central electrically conductive plane in determining the parasitic capacitance of an electrical lead of a packaged integrated circuit type device during the testing of the packaged integrated circuit type device.