Patent ID: 7913213

Claim:
A method for automatically identifying corrections for circuit paths of an integrated circuit (IC) that include minimum timing violations, the method comprising: a design tool creating an internal node report corresponding to a received node report for the IC that includes a listing of circuit nodes and a maximum timing slack available at each of the nodes; for each circuit path having a minimum timing violation: the design tool identifying locations along the circuit path to change a delay; the design tool sequentially trying at particular locations a plurality of circuit delay changes including: selected circuit delay changes that add delay including swapping a datapath gate with a gate having a longer delay, and selected circuit delay changes that reduce a clock delay including reducing a clock delay of a destination clock-delayed flip-flop, reducing a delay of an L0header component in the clock path of a datapath destination flip-flop; and removing the L0header component in the clock path of the datapath destination flip-flop in response to the reducing the delay not correcting the minimum timing violation, and evaluating a result of each circuit change until an acceptable percentage of the minimum timing violation has been corrected; in response to each circuit change, the design tool updating the internal node report by reducing a maximum slack value of each affected node by an amount of the added delay; and the design tool generating an output report including a listing of the circuit changes which correct the minimum timing violations.