Patent ID: 8900986

Claim:
A method for flux-free bumping using indium, comprising: A. a first step of providing an under bump metallization (UBM) and seed layer on a silicon substrate, the first step comprising: (a) growing a first oxide layer on the silicon substrate by thermal oxidation; and (b) depositing, in sequence, a first layer of titanium on the first oxide layer, a first layer of copper on the first layer of titanium, and second layer of titanium on the first layer of copper, the deposition performed by sputtering; B. a second step of providing contact holes for contacting the UBM layer, the second step comprising: (c) forming a second layer of oxide on the UBM layer by plasma enhanced chemical vapor deposition (PECVD); (d) forming a layer of photoresist on the second layer of oxide; (e) defining a pattern of contact holes in the photoresist layer by a lithography process; (f) opening contact holes in the second oxide layer according to the pattern by etching the second oxide layer and the second layer of titanium with one of a CF4 plasma and buffer oxide etch (BOE); C. a third step of electroplating a second layer of copper on the first layer of copper; D. a fourth step of providing indium bumps on the UBM layer, the fourth step comprising: (h) immersing the silicon substrate in a hot acetone thereby removing the photoresist layer; (i) electroplating a layer of indium on the second layer of copper; (j) electroplating a layer of silver on the layer of indium thereby providing an anti-oxidation layer on the indium layer, the mass ratio of the layer of indium to the layer of silver is close to the indium-silver eutectic point; and (k) reflowing the silver coated indium layer at a summit temperature of 180-220° C. in an annealing furnace in an atmosphere of H2 or N2, thereby forming indium solder bumps in the openings.