Patent ID: 7227876

Claim:
A method of deriving an estimate of a number of bits read from a FIFO buffer per FIFO buffer write clock cycle during demapping of an input data stream characterized by a first frequency to an output data stream characterized by a second frequency, said demapping comprising extracting payload data bits from said input data stream, accumulating said extracted payload data bits until an n-bit payload data byte is accumulated, writing said payload data byte into said FIFO buffer during one of said FIFO buffer write clock cycles and reading said payload data byte from said FIFO buffer during a FIFO buffer read clock cycle, said method comprising: (a) repetitively consecutively producing one of j predefined integer values I i during each consecutive one of j of said FIFO buffer write clock cycles, where i=1, . . . , j and wherein j and said integer values I i are selected such that ∑ i = 1 j ⁢ ⁢ I i j closely approximates said number of bits read from said FIFO buffer per FIFO buffer write clock cycle; and, (b) during each k th one of said FIFO buffer write clock cycles, outputting as said estimate of said number of bits read from said FIFO buffer per FIFO buffer write clock cycle, a value I k +I k-1 , where k=1, . . . , p; wherein i, j, k and p are integers.