Patent ID: 7820499

Claim:
A method for manufacturing a nonvolatile memory device, the method comprising: forming a tunnel insulation layer over a semiconductor substrate including isolation regions and active regions; forming a conductive layer for gates over the tunnel insulation layer; forming a dielectric layer over the conductive layer for gates; forming an etch mask pattern over the dielectric layer such that a width of a lower end of each opening defined in the etch mask pattern is less than a width of an upper end thereof; and defining contact holes by removing portions of the dielectric layer using the etch mask pattern, wherein forming the etch mask pattern comprises forming a passivation layer over the dielectric layer, forming a BARC (bottom anti-reflection coating) layer over the passivation layer, forming a mask pattern over the BARC layer, slope-etching the BARC layer using the mask pattern, thereby patterning the BARC layer, and patterning the passivation layer using the patterned BARC layer.