Patent ID: 8017467

Claim:
A method of manufacturing a semiconductor memory device comprising forming, on a semiconductor substrate, gate electrodes of memory cell transistors, a gate electrode of a first select transistor, and a gate electrode of a second select transistor, the first select transistor being adjacent to the memory cell transistor, the second select transistor being adjacent to the first select transistor; making a mask between the gate electrodes of the memory cell transistors, the mask including an opening between the gate electrode of the first select transistor and the gate electrode of the second select transistor; etching the semiconductor substrate between the gate electrode of the first select transistor and the gate electrode of the second select transistor; forming a first insulating film between the gate electrode of the first select transistor and the gate electrode of the second select transistor; and forming a contact electrode between the gate electrode of the first select transistor and the gate electrode of the second select transistor.