Patent ID: 8589467

Claim:
An apparatus that comprises a systolic array of processing units and that receives matrices and performs complex matrix computation on the matrices received using MFA (Modified Faddeeva Algorithm) to output a processing result, the systolic array of processing units comprising: a trapezoid systolic array of processing units that includes a triangular systolic array of processing units and a square systolic array of processing units, the trapezoid systolic array of processing units receiving the matrices as an input at a first row of thereof; and a linear systolic array of processing units arranged corresponding to a last row of the square systolic array of processing units, the linear systolic array of processing units receiving an output from the last row of the square systolic array of processing units and outputting the processing result, processing units arranged in one row in the trapezoid systolic array supplying a phase-shifted MFA intermediate processing result to processing units arranged in a row following the one row, processing units arranged in the following row receiving the phase-shifted MFA intermediate processing result and performing phase rotation processing to the phase-shifted MFA intermediate processing result received to absorb an effect of a phase shift, and the linear systolic array of processing units correcting a phase shift of an MFA processing result output from processing units arranged in the last row of the trapezoid systolic array, wherein each of second and subsequent rows of the trapezoid systolic array of processing units comprises: a boundary processing unit that receives a first component of the phase-shifted MFA intermediate processing result and a phase shift parameter supplied from the preceding row and generates first and second vector rotation parameters, a multiply-and-accumulate accumulate coeffeicient, and a phase shift parameter; and a plurality of internal processing units each of which receives a component other than the first component of the phase-shifted MFA intermediate processing result, and first and second vector rotation parameter and the multiply-and-accumulate coefficient and supplies the phase-shifted MFA intermediate processing result to the following row.