Patent ID: 8530283

Claim:
A process of forming an electronic device comprising a nonvolatile memory cell comprising: forming a field isolation region over a substrate, wherein the field isolation region defines a first active region and a second active region spaced apart from each other; forming a gate electrode layer over the field isolation region, the first active region, and the second active region; forming a conductive layer over the gate electrode layer; patterning the conductive layer and the gate electrode layer to form a first gate stack and a second gate stack; and patterning the conductive layer to remove a portion of the conductive layer overlying the gate electrode layer, wherein: the first gate stack includes a first gate member and a first conductive member, and the second gate stack includes a second gate member; the first gate member overlies a portion of the first active region and includes a gate electrode of a read transistor and a first electrode of an antifuse component; the first conductive member overlies the first gate member and includes a second electrode of the antifuse component; and the second gate member overlies a portion of the second active region and includes a gate electrode of an access transistor.