Patent ID: 6871305

Claim:
A device for prolonging lifetime of nonvolatile memory, the device being connected with a host electronic machine and a nonvolatile memory unit, comprising a RAM (Random Access Memory) buffer zone, a counter, and two sets of inverters, wherein: the RAM buffer zone is connected with the counter and the inverters and employed for temporary storage of a unit data train and a corresponding state flag during when a host electronic machine is to read/write from or to the nonvolatile memory unit, wherein the state flag determines whether the unit data train is to be inverted by the inverters; the counter connected with the host electronic machine and the RAM buffer zone is in charge of counting the total bits of logic “0” in the unit data train and judging whether the counted result outnumbers a default proportion or not, wherein if a counted result outnumbers a default proportion, the state flag corresponding to the unit data train is turned into “0”, otherwise, the state flag corresponding to the unit data train is turned into “1”; and the inverters are arranged to check the corresponding state flag of the unit and invert the unit data train if the state flag has been turned into “0”; whereby the electronic machine will write fewer bits of logic “0” to prolong the lifetime of the nonvolatile memory unit.