Patent ID: 6915249

Claim:
A noise checking method used upon circuit designing for checking noise which has an influence on a signal waveform which propagates in a noticed wiring line on a design object circuit, comprising the steps of: producing a simulation model of a circuit portion relating to the noticed wiring line; performing a simulation using the simulation model to calculate a signal waveform which propagates in the noticed wiring line and calculate a noise waveform superposed on the signal waveform in the noticed wiring line for a plurality of kinds of noise; synthesizing with generation timings of the noise waveforms taken into consideration the signal waveform and the noise waveforms calculated for each of the plurality of kinds of noise to obtain a noise composite waveform which is the signal waveform on which the noise is superposed; and performing noise checking based on the noise composite waveform: wherein when the noise checking is performed, a maximum delay time and a minimum delay time of the noticed wiring line are extracted from the noise composite waveform, and overdelay/racing checking for the noticed wiring line is performed using the maximum delay time and the minimum delay time.