Patent ID: 7061058

Claim:
An integrated circuit comprising a plurality of transistors, a particular one of the transistors including a substrate, a gate, and a gate oxide layer between the substrate and the gate, the substrate including a channel region located generally below the gate; wherein the channel region includes a retrograde well having been formed at least by: implanting a first dopant into the channel region; implanting a second dopant into the substrate to form a doped source region and a doped drain region; implanting a third dopant into the gate oxide layer; performing a source/drain anneal to form a source and a drain in the doped source region and the doped drain region, respectively, the source/drain anneal causing a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer such that the concentration of the first dopant in the channel region increases from a first region adjacent the gate oxide layer to a second region further from the gate oxide.