Patent ID: 7620140

Claim:
A programmable integer and fractional frequency divider, dividing a frequency of an input signal by a first divisor to generate an output signal, wherein the first divisor is an integer or a fraction, and the programmable integer and fractional frequency divider comprises: a dual-modulus divider, dividing the frequency of the output signal by a second divisor, wherein the second divisor is first or second integers according to a divisor switching signal; a programmable counter, calculating a pulse count of the output signal of the dual-modulus divider, and generating the output signal when the pulse count equals to a third integer; a swallow counter, calculating the pulse count of the output signal of the dual-modulus divider, switching a mode signal to a second level when the output signal equals to a fourth integer, and resetting the mode signal to a first level when the output signal is a predetermined level; and a fractional number switch, calculating a pulse count of the mode signal of the swallow counter, generating the divisor switching signal to switch a divisor of the dual-modulus divider when the pulse count of the mode signal equals to a predetermined pulse count, wherein the predetermined pulse count is determined by a fractional part of the first divisor, and the fractional number switch receives at least one fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor.