Patent ID: 8743042

Claim:
A display device (i) including a display panel provided with a matrix of memory circuits and (ii) having a normal mode during which a display is carried out by a data signal potential written to the memory circuits for each frame and a memory mode during which a display is carried out by refreshing and retaining a data signal potential written to the memory circuits, the display panel including data signal lines, scanning signal lines, auxiliary capacitor lines, and a common electrode, the memory circuits each comprising: a pixel electrode; a first switch circuit for selectively making conduction or cutoff between a corresponding one of the data signal lines and the pixel electrode in accordance with a potential of a corresponding one of the scanning signal lines; a first capacitor formed between the pixel electrode and a corresponding one of the auxiliary capacitor lines; and a refresh control section for controlling a refresh of a potential of the pixel electrode, in a case where it is necessary to cause the common electrode and the auxiliary capacitor lines to change in potential along with a switch between the normal mode and the memory mode, the change in potential being made while electrically connecting the pixel electrode of each of the memory circuits to the data signal line with the data signal line having its potential fixed and with the first switch circuit in a conductive state.