Patent ID: 7414909

Claim:
A nonvolatile semiconductor memory comprising: a plurality of memory cells arranged in a matrix fashion, the respective memory cells including a cell select transistor and a data storage, connected in series with each other; a plurality of bit lines disposed so as to correspond to respective columns of the memory cells, the respective bit lines being connected to the memory cells in columns corresponding thereto, and being laid out such that the respective bit lines in columns adjacent to each other form a bit line pair; a plurality of source lines disposed so as to correspond to the respective columns of the memory cells such that the respective source lines are shared by the memory cells in columns adjacent to each other, the respective columns of the memory cells, sharing the respective source lines, being connected to the respective bit lines of the individual bit line pairs; a plurality of word lines disposed so as to correspond to respective rows of the memory cells, the respective word lines being connected to the respective cell select transistors of the memory cells in rows corresponding thereto, wherein at the time of selection of the word line, a current is caused to selectively flow between the bit line and the source line, corresponding thereto, in the respective memory cells connected to the word line as selected, according to stored data in the data storage; at least one dummy word line laid out so as to be in parallel with the word lines; a plurality of dummy cells disposed so as to correspond to the at least one dummy word line and the respective bit lines, wherein the respective dummy cells include at least a first switching transistor and a second switching transistor connected in series with each other, the first switching transistor is turned into a conducting state at the time of selection of the dummy word line corresponding thereto while the second switching transistor is turned into the conducting state at the time of nonselection of the source line in a column corresponding thereto or at all times, thereby forming a path through which a current flows between the source line adjacent to the source line corresponding thereto and the bit line corresponding thereto when both the first and second switching transistors are in the conducting state.