Patent ID: 7395524

Claim:
A method in a data processing system of specifying a relationship between latches in a digital design in one or more hardware description language (HDL) files, said method comprising: in an HDL statement within one of one or more HDL files representing a digital design, specifying a parent latch within the digital design; in the one or more HDL files, specifying a clone latch within the digital design utilizing an HDL clone latch declaration; associating an HDL attribute-value pair with said HDL clone latch declaration indicating a relationship between said clone latch and said parent latch according to which said clone latch is automatically set to a same value as said parent latch when the parent latch is set after said clone latch created; additionally indicating said relationship between said clone latch and the parent latch in a configuration specification language clone latch declaration included within said one or more HDL files; and processing said one or more HDL files to obtain a simulation executable model and a configuration database containing a data structure in a configuration database representing said clone latch and a relationship between said clone latch and said parent latch.