Patent ID: 7903460

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array having a plurality of non-volatile memory cells, the memory cell array being divided into a plurality of first erase units respectively including a plurality of second erase units; and a control circuit which executes erase and write operations of each selected memory cell in the memory cell array in accordance with erase or write instructions, wherein the control circuit includes a first erase control unit which performs an erase in the first erase unit and a second erase control unit which performs an erase in the second erase unit, wherein the second erase control unit sets a voltage applied to the target memory cell at erasing smaller in absolute value than at erasing by the first erase control unit and makes short the time necessary for erasure, and wherein when the second erase unit including each selected memory cell is in a state in which erasing and writing are being done by the first erase control unit, the second erase control unit erases the second erase unit including the selected memory cell.