Patent ID: 7566595

Claim:
A method of protecting an electronic circuit from ESD damage: operably coupling an SCR circuit having first and second terminals to a terminal of the electronic circuit, wherein the SCR circuit has a full guardring for shielding the SCR circuit from triggering by fast transients; wherein the guardring includes a pair of resistors resulting in a guardring resistance for triggering the SCR at the onset of an ESD event; and wherein the SCR circuit includes: a lightly doped region of a first conductivity type; a first highly doped region of a second conductivity type opposite the first conductivity type, wherein the first highly doped region is disposed within the lightly doped region at a surface of the lightly doped region, and at least a portion of the boundary between the first highly doped region and the lightly doped region forms a forward-biased SCR junction; a second highly doped region of the first conductivity type forming the guardring disposed within the lightly doped region at the surface, wherein the guardring surrounds the first highly doped region in a plane coplanar to the surface; and the pair of resistors dividing the guardring into first and second regions, wherein the resistors are disposed at the surface, wherein the first region of the guardring is electrically connected to the first terminal; and the second region of the guardring is electrically connected to the first terminal throucih the resistors.