Patent ID: 8230134

Claim:
A hardware automated input/output (IO) path, comprising: a message transport unit configured for transporting an IO request to a local memory via a direct memory access (DMA) operation, the message transport unit further configured for determining a local message index descriptor (LMID) for associating with a request descriptor of the IO request; a fastpath engine communicatively coupled with the message transport unit, the fastpath engine configured for validating the request descriptor and creating a fastpath descriptor based on the request descriptor, the fastpath engine further configured for posting the fastpath descriptor into a fastpath descriptor control queue; a data access module communicatively coupled with the fastpath descriptor control queue and a fastpath completion queue, the data access module configured for performing an IO operation based on the fastpath descriptor, the data access module further configured for posting a completion message into the fastpath completion queue upon a successful completion of the IO operation; a fastpath device table communicatively coupled with said fastpath engine, the fastpath device table configured for storing a list of fastpath enabled devices, and said fastpath engine further configured for maintaining current state information associated with each of the list of fastpath enabled devices; said fastpath engine further configured for: receiving the completion message from the fastpath completion queue, releasing the IO request stored in the local memory, and providing a reply message based on the completion message; and said message transport unit further configured for providing the reply message in response to the IO request; wherein each of said message transport unit, said fastpath engine and said data access module are implemented as a state machine realized utilizing an electronic circuit.