Patent ID: 7166882

Claim:
A semiconductor memory device including a memory cell having a transistor and a capacitor, comprising: the transistor formed over a semiconductor substrate, the transistor including a gate electrode and a pair of source/drain regions; a word line formed over the semiconductor substrate and connected to the gate electrode of the transistor; a bit line formed over the semiconductor substrate and connected to one of the pair of source/drain regions of the transistor; a first insulation film formed over the semiconductor substrate and covering the transistor, the word line and the bit line; a second insulation film formed on the first insulation film and having an opening; and the capacitor formed over the second insulation film, a storage electrode of the capacitor being formed at least in the opening and electrically connected to another one of the pair of source/drain regions of the transistor; wherein a cavity is formed in the first insulation film at least between the bit line and another bit line adjacent to said the bit line.