Patent ID: 8093601

Claim:
An active matrix substrate comprising: a gate bus line; a buffer inverter including a first-conductivity-type transistor section and a second-conductivity-type transistor section, wherein each of the first-conductivity-type transistor section and the second-conductivity-type transistor section includes a semiconductor layer and a gate electrode, the semiconductor layer including a source region, a drain region and a channel region; an interlayer film covering the gate bus line and the gate electrode; and a contact portion for electrically connecting the drain regions of the first-conductivity-type transistor section and the second-conductivity-type transistor section with the gate bus line, wherein the gate bus line and the gate electrode extend in a first direction, the first-conductivity-type transistor section includes a plurality of first-conductivity-type transistors arranged in the first direction, the second-conductivity-type transistor section includes a plurality of second-conductivity-type transistors arranged in the first direction, the contact portion includes a flat portion provided on the interlayer film, a plurality of gate bus line connecting portions each electrically connecting the flat portion with the gate bus line, a plurality of first-conductivity-type drain connecting portions each electrically connecting the flat portion with the drain region of the first-conductivity-type transistor section, and a plurality of second-conductivity-type drain connecting portions each electrically connecting the flat portion with the drain region of the second-conductivity-type transistor section, and a direction of a straight line denoting a shortest distance between one of the plurality of first-conductivity-type drain connecting portions that is closest to the gate bus line and the gate bus line is inclined with respect to a second direction perpendicular to the first direction.