Patent ID: 7620678

Claim:
A system for providing individualized design for embedded systems using an adaptive computing engine, the system comprising: a plurality of heterogeneous processing nodes, each one of the heterogeneous processing nodes including an interface that supports a definition of the processing performed by the adaptive computing engine through customization of elements in each of the heterogeneous processing nodes, wherein each of the heterogeneous processing nodes comprises a plurality of reconfigurable matrices, and each of the matrices includes a different mix of fixed and configurable application specific integrated circuits; a controller for separately configuring each one of the heterogeneous processing nodes according to individualized design needs of the adaptive computing engine thereby providing a desired embedded function; a matrix interconnection network for communication between each of the heterogeneous processing nodes and a controller and carrying data capable of configuring and reconfiguring the plurality of heterogeneous processing nodes to execute different functions in the heterogeneous processing nodes, the matrix interconnection network supporting plural services including direct memory access services and read/write services between the heterogeneous processing nodes and a host processor; and a network root configured to communicate with a first network and a second network, wherein a first set of the plurality of heterogeneous processing nodes is configured as a first group that is configured to execute a plurality of functional nodes and that communicates using the first network, and wherein a second set of the plurality of heterogeneous processing nodes is configured as a second group that is configured to execute a plurality of functional nodes different than the functional nodes executed by the first group and that communicates using the second network, the network root providing communication between each of the nodes of the first and second groups and a single common system interface, a bulk RAM, a common memory interface, and a network output interface.