Patent ID: 8554962

Claim:
A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory, the data transfer control device comprising: a plurality of registers configured to store a plurality of data transfer requests from the plurality of DMA channels; a request rearranging section configured to rearrange the plurality of data transfer requests that are stored in the plurality of registers in a transfer order so that the plurality of data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers based on a successive transfer flag; and a transfer section configured to transfer data to the memory based on an output from the request rearranging section, wherein the request rearranging section comprises: a first pointer configured to indicate one of the plurality of registers that stores a first data transfer request from a first DMA channel, wherein the first data transfer request is selected first from among the plurality of data transfer requests; and a second pointer configured to indicate another one of the plurality of registers that stores a second data transfer request from the first DMA channel, when the second data transfer request is stored in the another one of the plurality of registers, and wherein the request rearranging section over-writes a value held in the second pointer into the first pointer after outputting the first data transfer request.