Patent ID: 7825681

Claim:
A common module for a double data rate-synchronous II synchronous dynamic random access memory (DDRII SDRAM) and a DDRIII SDRAM, applied in a computer, comprising: a first bus transmitting a plurality of signals; a termination circuit card comprising a plurality of termination resistors; a first slot disposed on the common module and coupled to the first bus, wherein the DDRII SDRAM is selectively installed in the first slot; and a second slot disposed on the common module and coupled to the first bus, wherein the DDRIII SDRAM or the termination circuit card is installed in the second slot; wherein when the DDRII SDRAM is installed in the first slot, the termination circuit card is installed in the second slot, wherein the signals comprise a plurality of data signals, a plurality of address signals, and a plurality of control signals, and the termination resistors comprise a plurality of first termination resistors and a plurality of second termination resistors, and wherein the first termination resistors match the address signals, and the second termination resistors match the control signals.