Patent ID: 8890322

Claim:
A semiconductor apparatus comprising: a semiconductor substrate which is a single crystal silicon semiconductor substrate, having a first principal surface on which an electric circuit is formed and a second principal surface opposed to the first principal surface, and a through hole that penetrates the first principal surface and the second principal surface and has a taper shape in which an opening on the second principal surface is greater than a through hole opening on the first principal surface, the through hole being formed by anisotropic wet etching; a multilayered wiring layer formed on the first principal surface having a plurality of conductive wiring layers connected to the electric circuit and a plurality of inter-layer insulating layers having an insulating layer opening of a same size and at a same position as the through hole opening which is an opening of the through hole on the first principal surface; an electrode pad that covers the insulating layer opening connected to the conductive wiring layer; and a lead-out wiring layer having a through wiring layer connected to the electrode pad formed inside the through hole and a connection wiring layer formed on the second principal surface side integral with the through wiring layer; wherein there is no difference in level in a portion of the single crystal silicon semiconductor substrate where the through hole opening contacts the insulating layer opening.