Patent ID: 7053486

Claim:
A semiconductor device comprising: a base frame including a first surface, and a second surface which opposes said first surface, and including an opening portion formed through the base frame; a semiconductor chip which includes a first main surface on which a plurality of electrode pads is included and a second main surface opposing said first main surface, said semiconductor chip being disposed within said opening portion such that the level of said first main surface is substantially equal to the level of said first surface; an insulating film formed on said first surface and said first main surface such that a part of each of said plurality of electrode pads is exposed; a plurality of wiring patterns which are electrically connected to said plurality of electrode pads, respectively and which extend from said electrode pads to the upper side of the first surface of said base frame, respectively, portions of said wiring patterns on a boundary and vicinity thereof between a region on the upper side of said semiconductor chip and the base frame being wider or thicker than other portions of said wiring patterns; a sealing portion formed on said wiring patterns and said insulating film such that a part of each of said wiring patterns is exposed; and a plurality of external terminals provided included over said wiring patterns in a region including the upper side of said base frame.