Patent ID: 7054978

Claim:
In a data processing system having a first component and a second component, the improvement comprising: a. A first data bus having a first set of characteristics responsively coupled between said first component via a first interface and said second component via a second interface; b. A second data bus having a second set of characteristics responsively coupled between said first component via a third interface and said second component via a fourth interface; and c. A circuit responsively coupled to said first data bus and said second data bus having a single set of interrupt handling logic which handles interrupts from both said first data bus and said second data bus and a selector which can couple said first data bus to said third interface and said second interface and which can couple said second data bus to said first interface and said second interface for alternately selecting transfers from said first data bus and said second data bus which combines said first data bus and said second data bus into a logical bus having a third set of characteristics wherein said third set of characteristics is different from either said first set of characteristics and said second set of characteristics.