Patent ID: 7755386

Claim:
An integrated circuit device comprising: a field programmable gate array region having: an input line, an output line, and an enable line; a mask-programmable gate array region having: an input line, an output line, and an enable line; an I/O system including I/O pads and associated driver circuits having: an input line, and output line, and an enable line; and a user-programmable interconnect architecture for selectively making connections between and coupled to the input line, the output line, and the enable line for said field programmable gate array region, said mask-programmable gate array region, and said I/O system, wherein: the user-programmable interconnect architecture comprises: a first multiplexer having: a first data input responsively coupled to the enable signal line of the field programmable gate array region; a second data input responsively coupled to the enable signal line of the mask-programmable gate array region; an output coupled to the enable signal line for the I/O system; and a select input.