Patent ID: 8284880

Claim:
A semiconductor memory device, comprising: a storage configured to store data; a phase comparator configured to compare a phase of a e reference clock with a phase of an internal clock to output phase comparison result signals; a digital filter configured to filter the phase comparison result signals received during predetermined periods to output control signals; a driver configured to control the digital filter by adjusting the predetermined periods, determining the predetermined periods and outputting an enable signal; and an interface configured to transfer data and signals corresponding to an external command to the storage in response to the control signals, wherein the digital filter is enabled in response to the enable signal from the driver, wherein the digital filter is configured to output a lagging state signal when a state that the reference clock lags behind the internal clock occurs during the predetermined periods, and output a leading state signal when the state that the reference clock leads the internal clock occurs during the predetermined periods wherein the digital filter includes: a lagging digital unit filter configured to output the lagging state signal in response to the enable signal outputted from the driver; and a leading digital unit filter configured to output the leading state signal in response to the enable signal outputted from the driver, wherein the lagging digital unit filter includes: a lagging pulse generating unit configured to receive the phase comparison result signals to generate lagging pulses; a lagging latching unit configured to latch the lagging pulses in response to the enable signal; and a lagging state holding unit configured to output an output value of the lagging latching unit as the lagging state signal in response to the reference clock.