Patent ID: 7322015

Claim:
A method of using a subcircuit model for dose rate simulation of a circuit design, comprising in combination: replacing an NMOS transistor in a circuit design with a subcircuit model, wherein the subcircuit model includes: an NMOS transistor having a source, a drain, a body, and a gate; a first diode having an anode connected to the body and a cathode connected to the drain; a first current source connected in parallel with the first diode, wherein current flows through the first current source from the drain to the body, and wherein the first diode and the first current source provide a model of a drain junction during a dose rate event; a second diode having an anode connected to the body and a cathode connected to the source; a second current source connected in parallel with the second diode, wherein current flows through the second current source from the source to the body, and wherein the second diode and the second current source provide a model of a source junction during the dose rate event; an NMOS transistor size parameter; a dose rate parameter of the dose rate event; and performing a computer simulation of the circuit design to determine dose rate hardness of the circuit design.