Patent ID: 7340585

Claim:
A fast linked multiprocessor network in an integrated circuit, comprising: a plurality of processing modules implemented on a field programmable gate array; a plurality of configurable uni-directional links coupled by way of a plurality of switches between a pair of processing modules comprising a first processing module and a second processing module, said plurality of said configurable uni-directional links providing a streaming communication channel between the pair of processing modules; a plurality of second configurable uni-directional links from the outputs of said second processing module of said pair of processing modules and coupled to a bus; a plurality of third configurable uni-directional links from said bus to the plurality of switches, wherein the plurality of switches enables the connection from one of the outputs of the first processing module by way of the plurality of configuration uni-directional links or the bus by way of the plurality of third configuration uni-directional links to the second processing module; and a processor coupled to the bus, the processor communicating with the second processing module of the pair of processing modules and enabling a computation in parallel with the streaming communication channel between the pair of processing modules by way of the plurality of second configurable uni-directional links.