Patent ID: 6931561

Claim:
Interfacing circuitry for transferring data from a first domain to a second domain, wherein the first domain is synchronized to a first clock and the second domain is synchronized to a second clock, the interfacing circuitry comprising: a first storage component configured for temporarily storing one or more data bits and a valid bit, the first storage component being synchronized to the first clock; a first multiplexer component connected to the first storage component for providing one or more data bits and a valid bit thereto and for receiving one or more data bits and a valid bit therefrom, coupled to the first domain for receiving one or more data bits and a valid bit therefrom, and controlled by a first Write_enable signal from the first domain, wherein the first Write_enable signal determines whether the first storage component keeps its current data and valid bit or latches in a new data and a new valid bit; a second storage component configured for temporarily storing one or more data bits and a valid bit, the second storage component being synchronized to the second clock; and a second multiplexer component connected to the second storage component for providing one or more data bits and a valid bit thereto and for receiving one or more data bits and a valid bit therefrom, coupled to the first storage component for receiving one or more data bits and a valid bit therefrom, and controlled by a second Write_enable signal from the second domain, wherein the second Write_enable signal determines whether the second storage component keeps its current data and valid bit or latches in a new data and a new valid bit.