Patent ID: 8094766

Claim:
A digital data signal capture circuit for synchronization of a received high frequency digital data signal, the digital data signal capture circuit comprising: a) a transition detector comprising: 1) a digital data signal sampler capable of sampling and holding a received digital data signal at a first time, a second time, and a third time; and 2) an early/late transition detector in communication with the digital data signal sampler, the early/late transition detector being constructed to receive samples of the received digital data signal at the first time, the second time, and the third time and from the received samples determine if a state transition occurs between the first time and the second time and if the state transition occurs between the first time and the third time and generate increment and decrement transition signals based on whether the state transition occurs between the first time and the second time and whether the state transition occurs between the first time and the third time; b) a strobe adjustment circuit coupled within the digital data signal capture circuit and configured so as to generate a strobe signal based on the increment and decrement transition signals from the early/late transition detector; and c) a capture circuit constructed to capture the received digital data signal using the strobe signal, wherein the digital data signal sampler comprises a clock generator to generate a first timing signal and a second timing signal, wherein the first timing signal has a phase difference of approximately 90° from the second timing signal, and wherein the digital data signal sampler is configured to use the first and second timing signals to sample and hold the received digital data signal at the first time, the second time, and the third times, wherein the digital data signal sampler further comprises: A) a first tracking flip flop configured to capture and retain the received digital data signal at the first time and at the third time B) a second tracking flip flop configured to capture and retain the received digital data signal at the second time; and C) a third tracking flip flop in communication with the first tracking flip flop and configured to receive the received digital data signal captured at the first time for storage until the third time, and wherein the clock generator is connected to provide the first timing signal at the first time and the third time to the first flip flop to capture and retain the received digital data signal and wherein the clock generator is connected to provide the first timing signal to the third flip flop to receive the received digital data signal captured at the first time for storage until the third time, and wherein the clock generator is connected to provide the second timing signal to the second flip flop at the second time to capture and retain the received digital data signal at the second time.