Patent ID: 8154664

Claim:
A feedback circuit for compensating for DC offset in an output signal comprising: a bi-level sync signal detection circuit configured to generate a bi-level sync signal detection pulse upon detection of a bi-level sync signal in said output signal; a first delay circuit for delaying said bi-level sync signal detection pulse a first period of time; a tri-level sync signal detection circuit configured to generate a tri-level sync signal detection pulse and disabling said bi-level sync signal detection pulse upon detecting a presence of a tri-level sync signal in said output signal during said first period of time; a clamp pulse generation circuit for generating a clamp pulse upon receiving said bi-level sync detection pulse or said tri-level sync signal detection pulse; a sampling circuit configured to sample said output signal during a time period of said clamp pulse to obtain a DC offset value; a compensation circuit for applying an inverse of said DC offset value to said input signal.