Patent ID: 8112731

Claim:
A computer-implemented method of reducing signal congestion in configuration data that implements a circuit design in a programmable logic device (PLD), the method comprising: mapping in a computer a plurality of circuit components of the circuit design to a plurality of components of the PLD; placing in the computer the plurality of PLD components in the PLD, wherein each of the placed PLD components is associated with one of a plurality of regions of the PLD and with one or more unique signal paths entering the PLD region; determining in the computer a cost value for each PLD region associated with a placed PLD component based at least in part on the number of unique signal paths entering the PLD region from other PLD regions, wherein the cost value reflects the amount of signal congestion in the PLD region; selecting in the computer one of the PLD components to move from a first one of the PLD regions to a second one of the PLD regions; updating in the computer the cost values associated with the first and second PLD regions based on a change in the number of unique signal paths entering the first and second PLD regions; and selectively accepting or rejecting in the computer the move based at least in part on the updated cost values.