Patent ID: 7231477

Claim:
A bus controller for controlling processing levels of plural requesters which access a common memory, the bus controller including: an access cycle counter for counting the number of access cycles for which the common memory is accessed; an arbiter coupled to the access cycle counter for judging a processing level of a processing of a requester, from plural processing levels that are different dependent on each requester, for which an access permission is given, and for performing the processing of the processing level that is judged previously; a correspondence information unit coupled to the arbiter for storing correspondence information that shows correspondences between the plural processing levels of the respective requesters and the access cycle numbers, wherein the arbiter is operable to judge the processing levels of the respective requesters for which an access permission is given, in accordance with a present cycle number that is counted by the access cycle counter, the number of remaining cycles up to a predetermined limit cycle number, and the correspondence information showing the correspondences between the processing levels of the respective requesters and the access cycle numbers.