Patent ID: 8642414

Claim:
A method for forming a MOS transistor structure with an in-situ doped source and drain, comprising steps of: providing a substrate; forming a first Ge content layer on the substrate; forming a first strained SiGe layer with Ge content lower than that of the first Ge content layer on the first Ge content layer; forming a gate stack on the first strained SiGe layer and forming a side wall of one or more layers on both sides of the gate stack; etching the first strained SiGe layer and the first Ge content layer to form a source region and a drain region; and forming a source and a drain in the source region and the drain region respectively by a low-temperature selective epitaxy, and introducing a doping gas during the low-temperature selective epitaxy to heavily dope the source and the drain and to in-situ activate a doping element.