Patent ID: 7420263

Claim:
A semiconductor wafer processing system, comprising: a first wafer processing station for (a) forming an array of grooves in a first side of a semiconductor wafer to a chosen depth which is 70-90 percent of a chosen thickness of the semiconductor wafer, (b) applying a back-grinding tape to the first side of the semiconductor wafer, (c) back-grinding a second side of the semiconductor wafer until the semiconductor wafer has the chosen thickness, wherein the back-grinding removes a portion of the second side of the semiconductor wafer without exposing the grooves from the second side of the semiconductor wafer which leaves a remaining portion across the second side of the semiconductor wafer, (d) applying an adhesive layer to the remaining portion of the second side of the semiconductor wafer, and (e) applying a first side of dicing tape over the adhesive layer; and a second wafer processing station having a vacuum table for securing a second side of the dicing tape, the second wafer processing station including, (f) means for removing tho back-grinding tape, and (g) means for severing the remaining portion of the second side of the semiconductor wafer, adhesive layer, and dicing tape to provide individually removable die from the semiconductor wafer without having incurred die tilt from the first and second wafer processing station features (a) - (g).