Patent ID: 7991966

Claim:
A processor comprising: a first processing core including a first low-level cache and a second processor core including a second low-level cache; page table storage associated with the first processing core, the page table storage adapted to hold an inclusive value to indicate a corresponding address is an inclusive address and an exclusive value to indicate the corresponding address is an exclusive address; a high level cache adapted to be shared by the first processing core and the second processing core; an interface adapted to communicate with other agents; and a cache bridge being adapted to receive a request from an agent referencing the corresponding address; to report a miss for the request from the agent without sending a snoop to the first and second processing cores responsive to the page table storage holding the inclusive value to indicate the corresponding address is an inclusive address and the high-level cache not containing a cache line for the corresponding address, and to issue a snoop to the first and second processing cores to determine if the cache line is within the first or the second low-level cache to determine if a miss is to be reported responsive to the page table storage holding the exclusive value to indicate the corresponding address is an exclusive address and the high-level cache not containing a cache line for the corresponding address.