Patent ID: 8508515

Claim:
An output buffering circuit of a driver device for a display device, comprising: a first amplifier circuit comprising: a first input stage coupled between a first power voltage and a second power voltage lower than the first power voltage, wherein the first input stage includes a differential transistor pair that is connected with a circuit node, the differential transistor pair being operable to receive a differential signal pair and provide an output signal; a first output stage coupled between the first power voltage and the second power voltage, and having a first output node; and an assistant discharging unit coupled between the first output node and a first intermediate power voltage higher than the second power voltage, wherein the assistant discharging unit is configured to provide a discharging current from the first output node to the first intermediate power voltage during a discharging operation of the first amplifier circuit; and a second amplifier circuit comprising: a second input stage coupled between the first power voltage and the second power voltage; a second output stage coupled between the first power voltage and the second power voltage, and having a second output node; and an assistant charging unit coupled between the second output node and a second intermediate power voltage lower than the first power voltage, wherein the assistant charging unit is configured to provide a charging current flowing from the second intermediate power voltage to the second output node during a charging operation of the second amplifier circuit; wherein the assistant discharging unit includes a discharging transistor connected between the first output node of the first output stage and the first intermediate power voltage, and a control circuit connected with a gate of the discharging transistor, the control circuit including: a first, a second and a third transistor that are connected with one another in series between the first power voltage and the circuit node of the first input stage; and a fourth and a fifth transistor that are connected with each other in series between the first power voltage and the second power voltage, wherein a gate of the fourth transistor is controlled by the output signal of the first input stage, drains of the fourth and fifth transistors are respectively connected with a gate of the second transistor, and a connection node between the second and third transistors is coupled with the gate of the discharging transistor.