Patent ID: 7265419

Claim:
A semiconductor memory device, comprising: a semiconductor device base having an insulating substrate and a semiconductor layer overlying it; a cell array formed on said semiconductor device base with cell transistors disposed in such a manner that each of source and drain layers is shared by adjacent two cell transistors arranged in a direction, said cell transistors each having an electrically floating channel body to store data defined by a carrier accumulation state of the channel body; logic transistors formed on said semiconductor device base to constitute a peripheral circuit of said cell array, at least a part of source and drain layers of each said cell transistor is formed with a thickness different from source and drain layers of said logic transistors; and wherein each of said cell transistors comprises: a first gate electrode formed above the semiconductor layer with a gate insulating film interposed therebetween; first and second insulating spacers formed on either side wall of the first gate electrode; and source and drain layers each comprising first diffusion layers formed in the semiconductor layer to reach the insulating substrate and self-aligned to the gate electrode, second diffusion layers formed in the semiconductor layer to reach the insulating substrate and self-aligned to the first insulating spacers and third diffusion layers formed in the semiconductor layer to reach the insulating substrate and self-aligned to the second insulating spacers, and a portion of the semiconductor layer in which the second and third diffusion layers are formed is thinned in comparison with the remaining portions.