Patent ID: 8750048

Claim:
A memory comprising: first flag cells configured to store first flag data; second flag cells configured to store second flag data; third flag cells configured to store third flag data; first sensing nodes having voltage levels determined by the first flag data of the first flag cells, respectively; second sensing nodes having voltage levels determined by the second flag data of the second flag cells, respectively; third sensing nodes having voltage levels determined by the third flag data of the third flag cells, respectively; a selection circuit configured to select the first sensing nodes or the second sensing nodes in response to a flag address; and a determination circuit having a first internal node through which current corresponding to voltage levels of the selected sensing nodes flows and a second internal node through which current corresponding to the voltage levels of the third sensing nodes flows, wherein the determination circuit is configured to determine a logic value of flag data corresponding to the selected sensing nodes among the first and second flag data by using the amount of current flowing through the first internal node and determine a logic value of the third flag data by using the amount of current flowing through the second internal node.