Patent ID: 8255726

Claim:
In a data processor, a method for reducing power consumption when processing mathematical operations by utilizing processor hardware devices that receive one or more operands from an execution unit, the method comprising: detecting when at least one operand of multiple operands is a zero operand before the operand is forwarded to an execution component for completing a mathematical operation; in response to at least one operand being a zero operand or being unordered, setting a first flag that triggers a gating of a clock signal, wherein the gating reduces an active floating point unit (FPU) data path by disabling select processing devices/stages of one or more processing stages/devices within the FPU data path and enables a bypassing of the completion of the mathematical operation, wherein an operand is unordered if the operand is one of a non-number or infinity; in response to the first flag being set, gating the clock signal to disable only select processing stages/devices of the one or more processing stages/devices within the FPU data path, wherein the select processing stages/devices are not needed to calculate a result of the mathematical operation, and wherein needed processing stages/devices for calculating the result are left active; in response to the at least one disabled processing stages/devices containing a multiplier circuit, forcing the multiplier output to zero during the second computation when the one or more operands yields a zero; and in response to the at least one disabled processing stages/devices containing an adder circuit, forcing the adder output to the nonzero operand when the zero operand is input for one operand in the second computation.