Patent ID: 7671648

Claim:
A clock generator comprising: a delay locked loop having at least one input to which an input clock signal is applied, and at least one output at which an output clock signal is provided, the delay locked loop operable to adjust the input clock signal by propagating the input clock signal through an adjustable delay line to generate the output clock signal synchronized with the input clock signal, the delay locked loop comprising: a phase detector having a first input coupled to receive the input clock signal and a second input coupled to receive the output clock signal, the phase detector configured to determine the phase difference between the output clock signal and the input clock signal, and to provide fine adjustments to the adjustable delay line during a normal operation mode of the delay locked loop; and a feedback loop coupled to the second input of the phase detector, the feedback loop operable to generate a feedback signal from the output clock signal of the delay locked and to apply the feedback signal to the second input of the phase detector during the normal operation mode of the delayed locked loop, the feedback loop being configured to provide the feedback signal to the delay control circuit for synchronizing delay measurement operations during a delay measurement mode; and a delay control circuit having a first input coupled to the input of the delay locked loop and a second input coupled to receive the feedback signal, the delay control circuit operable in the delay measurement mode to measure a delay by propagating a measurement signal through the adjustable delay line of the delay locked loop, the delay control circuit further operable upon entering the normal operation mode to stop the measurement of the delay and set the adjustable delay line to delay the input clock signal according to the measured delay, the delay control circuit comprising: a first logic control circuit configured to receive the input clock signal and the feedback signal to generate a start control signal to start measuring the delay applied to the adjustable delay line of the delay locked loop; and a second logic control circuit coupled to the first control logic circuit, and configure to receive the start control signal and the applied input clock signal to generate a stop control signal to stop measuring the delay applied to the adjustable delay line of the delay locked loop.