Patent ID: 7680234

Claim:
A computer readable medium storing a computer program to implement a Phase-Locked Loop (PLL), the computer program comprising: program instructions to generate a product signal by multiplying an input signal of interest representing an in-phase fundamental component of an ac voltage waveform with a PLL output signal to be locked with the input signal; program instructions to generate a substantially dc phase error signal by averaging the product signal over half-cycles of a waveform period of interest; program instructions to generate a frequency correction signal based on proportional-integral processing of the substantially dc phase error signal; and program instructions to generate the PLL output signal by clocking through a waveform lookup table at a desired clock rate determined by configuring a digital counter to generate a periodic clock signal at a period determined by a configuration value, and to adjust that clock rate as a function of the substantially dc phase error signal by adjusting the period as a function of the frequency correction signal to output successive sine and cosine values from a stored data table.