Patent ID: 7050352

Claim:
A data input apparatus of DDR SDRAM, comprising: a data strobe buffer for generating a first signal and a second signal by dividing a data strobe signal and further generating a data strobe pulse signal by delaying the data strobe signal; a data strobe signal division unit for generating a rising edge detecting pulse signal and a falling edge detecting pulse signal in response to the first and second signals; a data input means for dividing an input data inputted from an external of a chip into a rising data and a falling data and then outputting them according to the rising edge detecting pulse signal and the falling edge detecting pulse signal; an input control signal generation unit for generating a data input strobe pulse signal in order to control that the rising data and the falling data are transferred to an output bus in response to the data strobe pulse signal; and a global input/output transmission unit for transferring the rising data and the falling data to the output bus in response to the data input strobe pulse signal.