Patent ID: 7752355

Claim:
An asynchronous, data packet based, dual port, data management structure for transferring and managing a plurality of different transfers of packets of data that are being transferred at one time, comprising: a multi-port data RAM (random access memory) which stores a plurality of bits of data at a plurality of addresses in the data RAM, the multi-port RAM having a separate write port and a separate read port, such that write operations and read operations can be carried on simultaneously in parallel; a data tag buffer including a plurality of data tags to keep track of the locations of the packets of data in the data RAM, wherein each of the data tags includes an address pointing to memory space in the data RAM and each data tag has a free state and a used state; and wherein, when one of the data tags is in the free state, the space in the data RAM pointed to by said one of the data tags, is free; and when said one of the data tags is in the used state, the space in the data RAM pointed to by said one of the data tags is occupied by one of the packets of data; a header RAM that holds data headers which hold data transfer information and each data header includes a linked address that functions as a pointer to an address of one of the data tags in the data tag buffer; wherein the data RAM includes a receive (RX) buffer and a transmitter (TX) buffer, and an Application Layer AL communicates with a transaction layer TL by a packet-based protocol through the multi-port data RAM; and the application layer AL and the transaction layer TL have different clocks and clock frequencies mat run independently of each other, and write and read operations are conducted at the different clock frequencies simultaneously in parallel through the separate write port and read port.