Patent ID: 8261006

Claim:
A system comprising: a flash memory array component that stores data; and a memory hierarchy component coupled to a host and the flash memory array component, wherein the memory hierarchy component transfers the data between the host and the flash memory array component, the memory hierarchy component includes a write component that writes the data to a cache line of a plurality of cache lines of a level one cache in response to a determination that an address associated with the data is contained in the cache line or the cache line is not dirty, copies a block of data from the flash memory array component to a merge buffer in response to a determination that the cache line is dirty and flash memory data is not erased at a location in the flash memory array component associated with the address contained in the cache line, cleans the dirty cache line by writing the dirty cache line to the location in the flash memory array component associated with the address in response to a determination that the cache line is dirty and the flash memory data is erased at the location in the flash memory array component associated with the address contained in the cache line, and writes the data to the dirty cache line cleaned by the write component, wherein the dirty cache line is a cache line that the write component has written to but has not copied to the flash memory array component, and wherein the level one cache is coupled to the merge buffer, the flash memory array component, and the host.