Patent ID: 7353288

Claim:
An apparatus to remap SONET/SDH payloads from a received STS/STM frame structure to a destination STS/STM frame structure, comprising: a plurality of cards coupled via a backplane, the plurality of cards comprising: a plurality of cross-connect cards, wherein the plurality of cross-connect cards comprise at least one working card and at least one protection card; a plurality of trunk interface cards, wherein the trunk interface cards provide an interface to one or more other devices using higher speed connections; and a plurality of tributary interface cards coupled to the plurality of trunk interface cards via the plurality of cross-connect cards, wherein the tributary interface cards provide an interface to one or more other lower speed devices; a buffer memory coupled to receive a payload portion of the received SONET/SDH framed data; a pointer generator coupled to the buffer memory, the pointer generator to operate in a time-sliced manner to generate the destination STS/STM frame structure with aligned, remapped payload; and a pointer interpreter coupled to the buffer memory that operates in a time sliced manner to identify overhead portions of the SONET/SDH framed data and a payload portion of the SONET/SDH framed data, the pointer interpreter comprising: a first level pointer interpreter that operates in a time sliced manner; a first memory coupled to the first level pointer interpreter the first memory to store data for the first level pointer interpreter: a second level pointer interpreter coupled to the first level pointer interpreter, the second level pointer interpreter to operate in a time sliced manner; and a second memory coupled to the second level pointer interpreter, the second memory to store data for the second level pointer interpreter; wherein the buffer memory and pointer generator are located within the plurality of cross-connect cards; wherein the first level pointer interpreter is configured to extract VC-4, TUG-structured VC-3, and non-TUG structured VC-3 payloads; and wherein the second level pointer interpreter is configured to process VC-4 and TUG-structured VC-3 payloads from the first level pointer interpreter and to extract low-order payloads in a format of VC-3 VC-2 VC-12, VC-11, and combinations thereof.