Patent ID: 7649224

Claim:
A semiconductor device comprising: a semiconductor layer of a first general conductivity type; a body layer of a second general conductivity type formed in the semiconductor layer and comprising a channel region; a source layer formed in the body layer; a gate electrode disposed on the body layer; a first well layer of the first general conductivity type formed in the semiconductor layer; a drain layer of the first general conductivity type formed in the first well layer; a first withstand voltage boosting layer of the second general conductivity type configured to improve a withstand voltage of the semiconductor device, the first boosting layer being formed in a portion of the semiconductor layer operating as a drift region extending from the drain layer to the body layer; a second well layer of the first general conductivity type configured to lower an on-resistance and formed in the semiconductor layer under the gate electrode; and a third well layer of the first general conductivity type configured to lower the on-resistance and formed in the drift region so that the second and third well layers are physically separated from each other.