Patent ID: 7371650

Claim:
A method for fabricating a transistor structure comprising at least a first and a second bipolar transistor having different collector widths, the method comprising: A) providing a semiconductor substrate, and B) producing at least a first collector region of the first bipolar transistor having a first collector width and a second collector region of the second bipolar transistor having a second collector width, wherein a) at least a first zone of a first buried layer of a first conductivity type of the first bipolar transistor and a first zone of a second buried layer of a first or a second conductivity type of the second bipolar transistor are introduced into the semiconductor substrate, b) a first epitaxial layer is produced, which covers, over the whole area at least the first zones, c) at least a second zone of the first conductivity type is produced within the first epitaxial layer, the second zone adjoining the first zone of the first buried layer, d) a second epitaxial layer is produced, which covers, over the whole area, at least the first epitaxial layer and the second zone of the first buried layer, d) at least one insulation region is produced which isolates at least the collector regions from one another, and e) the second zone of the first buried layer adjoins the first collector region and the first zone of the second buried layer adjoins the second collector region.