Patent ID: 8921925

Claim:
A semiconductor device, comprising: an n-type drain layer; an n-type base layer provided on the n-type drain layer; a p-type base layer partially formed in a surface layer portion of the n-type base layer; an n-type source layer partially formed in a surface layer portion of the p-type base layer; a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer; a gate electrode formed on the gate insulation film to face, through the gate insulation film, the surface of the p-type base layer between the n-type source layer and the n-type base layer; a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer; a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer so as to be within the n-type base layer, the depletion layer alleviation region including first baryons converted to donors; a trap level region including second baryons for forming a trap level to be locally formed within the depletion layer alleviation region, the second baryons being heavier than the first baryons; a source electrode electrically connected to the n-type source layer; and a drain electrode electrically connected to the n-type drain layer.