Patent ID: 7871890

Claim:
A method of fabricating a semiconductor device, the method comprising: preparing a semiconductor substrate having a first circuit region and a second circuit region; forming a lower interlayer insulating layer on the semiconductor substrate having the first and second circuit regions; patterning the lower interlayer insulating layer to form a first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region; forming a first semiconductor pattern and a second semiconductor pattern sequentially stacked in the first hole; and forming a barrier impurity region and a first resistor sequentially stacked in the second hole, the method further comprising: before forming the lower interlayer insulating layer, forming a separation layer in the semiconductor substrate to define a first active region in the first circuit region and a second active region in the second circuit region; injecting impurity ions having a different conductivity type from the semiconductor substrate in the first circuit region into the first active region to form a word line; and injecting impurity ions having a different conductivity type from the semiconductor substrate in the second circuit region into the second active region to form a second resistor, wherein the separation layer is formed to cover a sidewall of the word line and a sidewall of the second resistor, the first hole is formed to expose a predetermined region of the word line, and the second hole is formed to expose a predetermined region of the second resistor.