Patent ID: 7007151

Claim:
A memory interface device for interfacing a number of host applications to a memory device, the memory interface device comprising: a host interface for interfacing with the number of host applications in a protocol associated with the corresponding host application; a memory interface for interfacing with the memory device wherein one or more of the host applications and the memory device operate in response to different protocols; a number of contexts operably coupled to the host interface for receiving memory access requests from the number of host applications and providing result/status information to the number of host applications, wherein each context corresponds to one and only one of the number of host applications; and control logic operably coupled to obtain memory access requests from the number of contexts, translate the memory access requests into memory access requests in accordance with a protocol of the memory device, interact with the memory device over the memory interface for servicing the memory access requests on behalf of the number of host applications, and provide the result/status information to the number of host applications via the number of contexts in accordance with the protocol associated with each of the number of host applications.