Patent ID: 8405439

Claim:
A duty cycle adjusting system, comprising a detection circuit, a first clock signal adjusting circuit connected with said detection circuit, and a second clock signal adjusting circuit connected with said detection circuit, wherein said detection circuit detects a duty cycle of a first output signal outputted by said first clock signal adjusting circuit and a duty cycle of a second output signal outputted by said second clock signal adjusting circuit, and outputs a first detection signal and a second detection signal, said first and second output signals are a pair of differential clock signals, said first and second detection signals are adapted for respectively adjusting rising edges of said pair of differential clock signals, wherein said first detection signal is adapted for adjusting rising edges of said second output signal, and said second detection signal is adapted for adjusting rising edges of said first output signal, wherein said detection circuit comprises a first field effect transistor, a second field effect transistor connected with said first field effect transistor, a third field effect transistor connected with said first field effect transistor, a fourth field effect transistor connected with said second field effect transistor, a fifth field effect transistor connected with said first and third field effect transistors, a sixth field effect transistor connected with said second and fourth field effect transistors, a first capacitor and a second capacitor connected with said first capacitor.