Patent ID: 7518935

Claim:
A random access memory (RAM) circuit, comprising: a plurality of memory cells which can be selectively addressed; a data connection for receiving and transmitting data; an address input for receiving address information for selecting memory cells; a command input for receiving commands; a clock input for receiving a system clock signal; an access control device which responds to the address information and to the commands which have been received in order to write received data to, and read data to be transmitted from, the memory cells which have been selected using the address information, under the control of the system clock signal; a reception sampling circuit for sampling the received data using a reception strobe signal; a transmission sampling circuit for sampling the data to be transmitted using a transmission strobe signal; a transmission strobe signal generating device which generates the transmission strobe signal with synchronization to the received system clock signal; a bidirectional data clock signal port comprising: a data clock transmission device for transmitting the transmission strobe signal in parallel with the transmitted data, wherein the transmission strobe signal is synchronized with a clock of the transmitted data; and a data clock reception device for receiving an external data clock signal which is synchronized with a clock of the received data; and a changeover device for selecting one of: the transmission strobe signal; and the external data clock signal, the changeover device forwarding the selected signal to the reception sampling circuit, the reception sampling circuit using the forwarded signal as the reception strobe signal to sample the received data.