Patent ID: 7009243

Claim:
A semiconductor memory device comprising: a write transistor having a first source region, a first drain region, a first channel region of a semiconductor material formed on a first insulating film and connecting the first source region and the first drain region, a first gate insulating film formed over the first channel region, and a first gate electrode formed over the first gate insulating film; a read transistor having a second source region, a second drain region, a second channel region located between the second source region and the second drain region, a charge storage region, a second gate insulating film formed over the second channel region, and a second gate electrode formed over the second gate insulating film; and a peripheral circuit transistor having a third gate insulating film; wherein the first gate electrode of the write transistor controls potential of the first channel region of the write transistor, and the second gate electrode of the read transistor controls potential of the second channel region of the read transistor, wherein the second source region of the read transistor is connected to a source line, one of the first source or first drain regions of the write transistor is connected to the charge storage region of the read transistor, and the other of the first source or first drain regions of the write transistor is connected to a data line; and wherein a thickness of the first gate insulating film is thickest among the first, second and third gate insulating film, and a thickness of the second gate insulating film is thicker than a thickness of the third gate insulating film.