Patent ID: 7521342

Claim:
A fabrication method of a semiconductor structure with high-voltage sustaining capability, comprising the steps of: forming at least one first doped layer of a first conductivity type on the surface of a semiconductor substrate; forming a semiconductor layer of the first conductivity type on the semiconductor substrate; alternatively forming a plurality of second doped layers of the first conductivity type and third doped layers of a second conductivity type in the semiconductor layer, wherein each first doped layer is substantially disposed under one of the second doped layers; and performing an annealing process on the doped layers to form a plurality of first well regions of the first conductivity type, a plurality of second well regions of the second conductivity type and at least one anti-punch through region of the first conductivity type, wherein each anti-punch through region overlaps portions of the lower portion of the first well region thereabove to increase the doping concentration therein, forming a semiconductor structure with high-voltage sustaining capability.