Patent ID: 7079410

Claim:
A device for driving a ferroelectric memory cell array comprising: first and second bitlines formed in a first direction, wherein the first bitline is formed in a first cell region and the second bitline is formed in a second cell region; first, second, third, and fourth split wordlines formed to cross the first and second bitlines, wherein the first, second and third split wordlines cross each other between the first and second cell regions; first and second switches operated by a pulse generated from a first pulse generator for controlling a wordline function of a split wordline; third and fourth switches operated by a pulse generated from a second pulse generator for controlling a plate line function of a split wordline; a first detector choosing either the first split wordline or the third split wordline in response to a first signal from the first switch, a second signal from the third switch, and a corresponding address signal; and a second detector choosing either the second split wordline or the fourth split wordline in response to a third signal from the second switch, a fourth signal from the fourth switch, and a corresponding address signal.