Patent ID: 7106654

Claim:
An arrangement comprising: a memory device for storing data, and a program-controlled unit with a memory interface for reading data out of the memory device, the memory device being supplied with a first clock signal, and the memory device transmitting the data requested from the memory device at the rate of a second clock signal based on the first clock signal, and the second clock signal to the memory interface when the memory interface performs a read access of the memory device, wherein the first clock signal is also supplied to the memory interface, the memory interface generates from the first clock signal supplied to it a third clock signal which has the same frequency as the first and the second clock signal but has a predetermined phase shift with respect to the second clock signal, the memory interface accepts the data supplied to it from the memory device with the rising and/or falling edges of the third clock signal or the inverted third clock signal, and the third clock signal is also used as clock signal by other components of the memory interface.