Patent ID: 8245167

Claim:
An apparatus for electronic circuit design, the apparatus comprising: one or more processors to execute machine readable instructions stored in a storage device to analyze a circuit design, the machine readable instructions stored in the storage device including instructions to analyze a hierarchy of a netlist of a circuit to determine one or more primary inputs and a plurality of primary outputs of the circuit at an upper level, and one or more internal vertices of the circuit at lower levels between the one or more primary inputs and the plurality of primary outputs; instructions to form a timing graph of the circuit including a plurality of timing delay edges representing timing delay between the one or more primary inputs, the one or more internal vertices and one or more of the primary outputs; instructions to add a super primary output to the timing graph of the circuit with timing delay edges having zero timing delay coupled to the plurality of primary outputs to form a plurality of paths of a path space from the one or more primary inputs to the super primary output; and instructions, responsive to the timing delay of the plurality of timing delay edges, to dynamically prune paths of the plurality of paths using branch and bound techniques on bounds of timing delay that are a function of one or more circuit parameters to reduce the path space down to one or more critical timing paths of the circuit with a worse case metric of timing delay between the one or more primary inputs and the super primary output.