Patent ID: 7130984

Claim:
An electronic device, comprising: a memory structure comprising an integer M of word storage locations; a write shift register for storing a sequence of bits, wherein the sequence in the write shift register comprises a number of bits equal to a ratio of 1/R 1 times the integer M; circuitry for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations; wherein in response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register; wherein one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written; a read shift register for storing a sequence of bits, wherein the sequence in the read shift register comprises a number of bits equal to a ratio of 1/R 2 times the integer M; circuitry for providing a read clock cycle to the read shift register for selected read operations with respect to any of the word storage locations; wherein in response to each read clock cycle, received from the circuitry for providing the read clock cycle, the read shift register shifts the sequence in the read shift register; wherein one bit in the sequence in the read shift register corresponds to an indication of one of the memory word storage locations from which a word will be read; and circuitry for evaluating continuous selected bits in the sequence in the write register relative to complementary continuous selected bits in the sequence in the read register for detecting a level of data fullness in the memory structure.