Patent ID: 7050345

Claim:
A static random access memory with reduced parasitic capacitive coupling for improved noise performance, comprising: an array of plural static memory bit cells, having a bit-latch coupled between a bit-true pass-gate and a bit-compliment pass-gate, organized as plural columns and plural rows; plural bit lines pairs aligned with said plural columns, each of said bit line pairs including a bit-true and a bit-compliment bit line aligned in parallel, and wherein said plural bit cell pass-gates are electrically coupled to each of a bit-true and a bit-compliment pair of said plural bit lines within all of that portion of said plural static memory bit cells that lie along the corresponding one of said plural columns, and plural word lines aligned with each of said plural rows, each of said rows having an integer multiple number, greater than one, of word lines aligned therewith, each one of said integer multiple number of word lines electrically coupled to an alternating fraction, equal to the inverse of said integer multiple, of all of that portion of said plural bit cells that lie along the corresponding one of said plural rows, and wherein said plural bit-true and bit-compliment pass gates do not couple their respective bit cell memory states until activated by one of said plural word lines, and wherein no two bit cells within each of said fractions of said plural bit cells are positioned adjacent to one another within said array, such that the conductive traces in the memory that form said plural bit lines pairs alternate position corresponding to said alternating coupling of said word line fractions, thereby ensuring that no two adjacent bits lines are simultaneously coupled to bit cells during any given word line activation, and thereby causing said non-coupled bit lines to act as a neutral conductive elements between activated and accessed bit lines.