Patent ID: 7228510

Claim:
A method of laying out a semiconductor integrated circuit device comprising: (a) decomposing circuit data into cells, and reading cell data including configuration data and interconnection data; (b) grouping cells on a semiconductor substrate into a plurality of rows, each of said rows including a plurality of cells aligned along a direction of a row, each cell including active regions, shape-fixed wiring regions disposed over the active regions, and shape-variable wiring regions disposed outside the active regions and having height along a direction crossing a direction of said row; (c) designing a layout of wirings in said shape-fixed wiring region; (d) designing a layout of wirings in said shape-variable wiring region; (e) checking possible variations of wirings in said shape-variable wiring region, for a pair of adjacent rows of cells grouped in said step (b), which will produce shape-variable wiring regions of locally varied height capable of a mutually fitting configuration, and which can reduce the distance between said pair of adjacent rows; and (f) if there is a variation which can reduce the distance between said pair of adjacent rows, redesigning the layout of wirings in the shape-variable wiring region to realize mutually fitting shape-variable wiring regions.