Patent ID: 8380137

Claim:
A circuit for transmitting and/or receiving in a radio network, the circuit comprising: a memory having a first interface for reading and writing and a second interface for reading and writing; an arithmetic logic unit connected to the first interface for reading and writing; a control unit connected to the second interface for reading and writing and to the arithmetic logic unit; and a transmit/receive unit connected to the control unit; wherein the arithmetic logic unit is configured to store a first receive address and a first transmit address in the control unit, wherein the control unit is configured to receive data from the transmit/receive unit and write the received data to the memory at the first receive address via the second memory interface, and wherein the control unit is configured to read transmit data from the memory at the first transmit address via the second interface of the memory and send the transmit data to the transmit/receive unit via the second interface of the memory.