Patent ID: 8853003

Claim:
A method for manufacturing a wafer level chip scale (WLCS) package device with a thick bottom metal comprising: providing a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip and a plurality of scribe lines to separate the semiconductor chips; attaching a metal interconnecting structure on each bonding pad; forming a top package layer covering a front surface of the semiconductor wafer and surrounding each metal interconnecting structure; thinning from a back surface opposite the front surface of the semiconductor wafer to thin the wafer and depositing a back metal layer to cover the back surface of the thinned wafer; attaching a lead frame comprising a plurality of thick bottom metals onto the back metal layer, wherein each thick bottom metal is aligned to a central portion of each chip, a plurality of connecting bands thinner than the thick bottom metal interconnecting the thick bottom metals constituting the lead frame; forming a plurality of back side cutting grooves along the scribe lines penetrating through the connecting bands, the back metal layer and into the wafer to a depth such that at least a portion of the top package layer forms a bottom of the back side cutting grooves; filling the back side cutting grooves and a space between the adjacent thick bottom metals with a package material; and cutting through the package material along the back side cutting grooves and the top package layer along the portion of the top package layer forming the bottom of the back side cutting grooves thus forming a plurality of singulated WLCS package devices.