Patent ID: 7529918

Claim:
A method for performing, in a processor, a plurality of bit field extractions to populate a plurality of destination lanes via a single instruction, comprising: (a) reading a plurality of bit field sizes, one bit field size per destination lane; (b) reading a plurality of bit fields from a source reservoir of bits, one bit field per destination lane, wherein the number of bits in each bit field is determined by the bit field size of its respective destination lane; (c) writing each bit field into a respective one of the plurality of destination lanes; (d) reducing a value of a count of the number of bits in the source reservoir by the sum of the bit field sizes read in step (a); (e) reading fill data from at least one fill data register designated as an operand in the instruction if the count of the number of bits in the source reservoir is less than a predetermined number; (f) writing a first value of a fill flag indicating that data from the at least one designated fill data register was used during execution of the instruction; and (g) increasing the value of the count of the number of bits in the source reservoir by the number of bits read from the at least one designated fill data register.