Patent ID: 7689896

Claim:
An apparatus, comprising: a processing module; and a memory, coupled to the processing module, that is operable to store operational instructions that enable the processing module to perform at least one of: employ either a joint ISI (Inter-Symbol Interference)-parity trellis or an ISI trellis to perform trellis encoding of a first information bit; and employ either the joint ISI-parity trellis or the ISI trellis when decoding a received symbol thereby making a best estimate of a second information bit encoded within the received symbol; and wherein: the memory is operable to represent the joint ISI-parity trellis by storing information corresponding to: a plurality of initial states of the joint ISI-parity trellis; a plurality of final states of the joint ISI-parity trellis; and corresponding branch connectivity between the plurality of initial states and the plurality of final states within the joint ISI-parity trellis; the memory is operable to represent the ISI trellis by storing information corresponding to: a plurality of emanating states selected from the plurality of initial states of the joint ISI-parity trellis such that the plurality of emanating states includes each possible initial state of a plurality of initial states of the ISI trellis; a plurality of resultant states that is reached when transitioning across the joint ISI-parity trellis from each emanating state of the plurality of emanating states; at least one expansion state, that is selected from the plurality of final states of the joint ISI-parity trellis and that is added to the plurality of resultant states to generate an expanded plurality of resultant states such that the expanded plurality of resultant states includes each possible final state of a plurality of final states of the ISI trellis; and a first sum of the plurality of initial states of the joint ISI-parity trellis, the plurality of final states of the joint ISI-parity trellis, and the at least one expansion state of the ISI trellis includes fewer states than a second sum of the plurality of initial states of the joint ISI-parity trellis, the plurality of final states of the joint ISI-parity trellis; the plurality of initial states of the ISI trellis, and the plurality of final states of the ISI trellis.