Patent ID: 7154787

Claim:
A semiconductor memory comprising: a first main bit line; a first source line; a first transistor; a first sub bit line connected through said first transistor to said first main bit line; a first memory transistor having one end connected to said first sub bit line and another end connected to said first source line; a second main bit line; a second source line; a second transistor; a second sub bit line connected through said second transistor to said second main bit line; a second memory transistor having one end connected to said second sub bit line and another end connected to said second source line; and an amplifier for differential amplification receiving respective currents flowing through said first and second main bit lines, wherein said first transistor and said first memory transistor are turned on and no current flow is generated in said second memory transistor in verify operation of said first memory transistor, wherein said second transistor is turned off in verify operation of said first memory transistor.