Patent ID: 7800969

Claim:
A semiconductor memory device, comprising: a bit line sense amplifier configured to sense and amplify data applied to bit lines; a voltage line driver configured to drive voltage lines of the bit line sense amplifier to a normal driving voltage or an overdriving voltage; a normal driving voltage charge driver configured to pull up a normal driving voltage terminal when a voltage level of the normal driving voltage terminal is lower than a first target normal driving voltage level; a normal driving voltage discharge driver configured to pull down the normal driving voltage terminal when the voltage level of the normal driving voltage terminal is higher than a second target normal driving voltage level during an activation period of a discharge enable signal; a voltage detector configured to detect the overdriving voltage level to output a plurality of detection signals, levels of which are determined according to the detection result; and an activation period adjusting unit configured to adjust the activation period of the discharge enable signal according to the detection signals.