Patent ID: 7723851

Claim:
A structure, comprising: a first substrate, said first substrate including: first transistors electrically connected to a set of wiring levels of said first substrate, said set of wiring levels stacked on top of one another from a lowermost wiring level closet to said first substrate to a uppermost wiring level furthest from said first substrate, each wiring level of said set of wiring layers including electrically conductive wires formed in a respective interlevel dielectric layer; an etch stop layer on a top surface of said uppermost wiring level; and a bottom surface of a first dielectric bonding layer on a top surface of said etch stop layer; a second substrate, said second substrate including: a second dielectric bonding layer; a buried oxide layer on a top surface of said second dielectric bonding layer; a silicon layer on a top surface of said buried oxide layer, said silicon layer including second transistors electrically isolated from each other by dielectric isolation in said silicon layer; a profile modulation layer on a top of said silicon layer and on a top surface of said dielectric isolation; and an additional dielectric layer on a top surface of said profile modulation layer; a top surface of said second dielectric bonding layer bonded to a bottom surface of said buried oxide; and a via contact comprising an electrical conductor filling an opening extending from said top surface of said additional dielectric layer, through said profile modulation layer, through said dielectric isolation, through said buried oxide layer through said first and second dielectric bonding layer and through said etch stop layer to a top surface of a wire of said uppermost wiring layer, said electrical conductor in physical and electrical contact with said wire.