Patent ID: 7813189

Claim:
A static random access memory (SRAM) comprising in combination: an array of memory cells; write control logic coupled to said array of memory cells to control the writing of data in to said array of memory cells, said write control logic having a data input and a write enable input; a programmable array local clock buffer for generating a write enable clock signal having an active state and a standby state coupled to said write enable input of said write control logic; an L 1 data latch with a data input, a data output coupled directly to the data input of said write control logic, and clock signal input establishing hold and flush states of said L 1 data latch; a programmable normal local clock buffer for generating an L 1 clock signal having a hold state and a flush state; a logic circuit for combining said write enable clock signal and said L 1 clock signal to generate a clock signal coupled to said clock input of said L 1 data latch that maintains said L 1 Latch is in hold state until the end of the active state of the write enable clock.