Patent ID: 7529893

Claim:
A system, comprising: a node including a processing subsystem and an interface coupled by an address network and a data network; an additional node including an additional processing subsystem and an additional interface coupled by an additional address network and an additional data network; an inter-node network configured to convey communications between the node and the additional node, wherein the interface and the additional interface are coupled to send and receive communications on the inter-node network; wherein the processing subsystem is configured to transition an access right to a coherency unit in response to receiving a data packet, including requested data, on the data network and to transition an ownership responsibility for the coherency unit in response to receiving a corresponding address packet on the address network; wherein the corresponding address packet and the data packet are part of a read-to-own transaction initiated by the processing subsystem; wherein the interface within the node is configured to delay providing the data packet on the data network until the interface receives an indication from the additional interface via the inter-node network that any shared copies of the coherency unit in the additional node have been invalidated; wherein in response to receiving the address packet via the address network, a memory subsystem included in the node is configured to send another data packet indicating the read-to-own transaction to the interface, wherein the interface is configured to forward a read-to-own message on the inter-node network in response to receiving the another data packet indicating the read-to-own transaction; and wherein the additional interface is configured to receive the read-to-own message via the inter-node network and to responsively send an invalidating address packet on the additional address network, wherein in response to the additional processing subsystem having an access right to but not an ownership responsibility for the coherency unit, the additional processing subsystem is configured to transition its access right to the coherency unit in response to the invalidating address packet.