Patent ID: 7675323

Claim:
A differential signal receiver, comprising: a waveform shaping circuit selectively outputting an upper limit value having a first potential difference from a first power supply potential, and a lower limit value having a second potential difference from the upper limit value, from a first and a second output terminals according to a differential signal input; an amplifier comparing voltages of the first and the second output terminals and outputting one of a voltage almost the same as the first power supply potential or a voltage almost the same as a second power supply potential; a first potential difference setting device for setting the first potential difference; and a second potential difference setting device for setting the second potential difference, wherein at least one of the first and the second potential difference setting devices comprises a diode connected transistor, wherein the amplifier comprises a first Nch enhancement type transistor and a second Nch enhancement type transistor, a source of the first Nch enhancement type transistor connected in common with a source of the second Nch enhancement type transistor, wherein a gate of the first Nch enhancement type transistor is connected with the first output terminal, wherein a gate of the second Nch enhancement type transistor is connected with the second output terminal, wherein the amplifier further comprises a first Pch enhancement type transistor, a second Pch enhancement type transistor, a third Pch enhancement type transistor, a fourth Pch enhancement type transistor, a third Nch enhancement type transistor, and a fourth Nch enhancement type transistor, wherein a gate of the first Pch enhancement type transistor is connected with a gate of the second Pch enhancement type transistor, wherein a gate of the third Pch enhancement type transistor is connected with a gate of the fourth Pch enhancement type transistor, wherein a gate of the third Nch enhancement type transistor is connected with a gate of the fourth Nch enhancement type transistor, wherein a source of the third Nch enhancement type transistor is connected with a drain of the fourth Pch enhancement type transistor, and wherein a drain of the fourth Nch enhancement type transistor is connected to a drain of the second Pch enhancement type transistor.