Patent ID: 7339223

Claim:
A semiconductor device, comprising: a semiconductor substrate having a cell array region and a peripheral circuit region; a plurality of word line patterns placed in the cell array region of the semiconductor substrate, each word line pattern including a word line and a word line capping layer pattern; at least one gate pattern including a gate electrode and a gate capping layer pattern located in the peripheral circuit region, the gate capping layer pattern having an etching selectivity ratio different from the word line capping layer pattern; a plurality of gate spacers placed on side walls of the word line patterns and the at least one gate pattern; a pad interlayer insulating layer having a first etch selectivity; a bit line interlayer insulating layer having a second etch selectivity, the bit line interlayer insulating layer sequentially stacked on the pad interlayer insulating layer over a surface of the semiconductor substrate having the gate spacers, the first etch selectivity being approximately the same as the second etch selectivity and an etch selectivity of the gate capping layer pattern; a cell contact hole penetrating the bit line interlayer insulating layer and the pad interlayer insulating layer in a region between the word line patterns; and a peripheral circuit contact hole penetrating the bit line interlayer insulating layer, the pad interlayer insulating layer, and the gate capping layer pattern to expose the gate electrode.