Patent ID: 7435629

Claim:
A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line and a storage electrode line on a substrate; forming a gate insulating layer on the gate line and the storage electrode line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode on the ohmic contact layer; depositing a passivation layer on the data line and the drain electrode; forming a first photoresist including a first portion and a second portion on the passivation layer, wherein the second portion of the first photoresist overlaps a portion of the drain electrode, a portion of the storage electrode line and a pixel area; etching the passivation layer using the first photoresist to expose a portion of the data line and a first portion of the gate insulating layer overlapping a portion of the gate line; removing the second portion of the first photoresist and reducing an initial thickness of the first portion of the first photoresist when the second portion of the first photoresist is removed; etching the first portion of the gate insulating layer and the passivation layer using the first portion of the first photoresist having the reduced thickness to expose a second portion of the gate insulating layer, a portion of the drain electrode and a portion of the gate line; depositing a conductive film on the first portion of the first photoresist having the reduced thickness and the second portion of the gate insulating layer; and removing the first portion of the first photoresist having the reduced thickness and the conductive film formed on the first portion of the first photoresist to form a pixel electrode on the pixel area, wherein the pixel electrode is connected to the exposed portion of the drain electrode and overlaps the portion of the storage electrode line with only the second portion of the gate insulating layer therebetween.