Patent ID: 7640471

Claim:
A test system comprising: a tester, the tester having an internal tester clock operable at a tester clock speed, the tester operable to communicate a first plurality of test signals at the tester clock speed; a device for testing, the device having an internal device clock operable at a device clock speed, the device being operable to use the device clock to communicate a second plurality test signals at the device clock speed, wherein the device clock speed is greater than the tester clock speed; and a test module located on an interface board, the interface board being removably secured to a test head, the test module being electrically coupled to the tester and to the device, wherein the test module includes: a bus to communicate the first and second plurality of test signals between the tester and the device; a memory module coupled to the bus, the memory module being operable to store the first plurality of test signals at the tester clock speed and the second plurality of test signals at the device clock speed; and a controller operable to control the flow of the first and second plurality of test signals through the device interface and the tester interface, wherein the device interface is disabled when the bus operates at the tester clock speed, wherein the tester interface is disabled when the bus operates at the device clock speed.