Patent ID: 7880202

Claim:
A field effect transistor comprising: a source region in a semiconductor body having a portion defining an inner edge of said source region; a drain region in the semiconductor body having a portion defining an inner edge of said drain region; a channel region in the semiconductor body interposed between the inner edge of the source region and the inner edge of the drain region, the channel region having a length defining a distance between the source region inner edge and the drain region inner edge and also having a width extending perpendicular to said length from a first edge to a second edge; and a multiplicity of extensions disposed at the inner edges of the source and drain regions, the multiplicity of extensions located within said channel width between said first edge and said second edge, said multiplicity of extensions affecting the transistor such that a threshold voltage for current flow through the channel region varies at different ones of said multiplicity of extensions along the width direction thereof, wherein the field effect transistor is a planar transistor.