Patent ID: 7990203

Claim:
An internal voltage generation apparatus for a semiconductor device, comprising: a power-up detector configured to generate a power-up signal in response to a level of an external supply voltage, the power-up signal having a voltage level that is below a threshold voltage level in a first period, the power-up signal having a first logic level that is above the threshold voltage level in a second period after the first period, and the power-up signal having a second logic level in a third period after the second period; an internal voltage generator configured to receive the power-up signal, and generate a plurality of internal voltages; and an initial level holder comprising a plurality of transistors connected between the external supply voltage and an output terminal of the internal voltage generator, and a plurality of passive elements connected between the external supply voltage and the output terminal of the internal voltage generator, wherein each one of said transistors is connected in parallel, the transistors are turned on to stabilize the output terminal of the internal voltage generator in response to the power-up signal in the second period, and the transistors are turned off in the first and third period, wherein the internal voltage generator comprises: a VPP regulator for generating a high voltage to a word line; a VINT regulator for generating a local voltage of a cell; a VBL regulator for generating a bit line equalization voltage; a VCP regulator for generating a cell plate voltage; and a VBB regulator for generating a bulk voltage of the cell.