Patent ID: 8546233

Claim:
A method that produces a capacitor in an interconnect layer in a circuit arrangement, the method comprising: producing an electrically insulating layer; patterning the electrically insulating layer to produce cutouts within the electrically insulating layer; forming conductive structures in the cutouts; planarizing the formed conductive structures; patterning the electrically insulating layer a second time to produce a further cutout within the electrically insulating layer adjacent to at least one of the conductive structures, a bottom of the further cutout arranged in or at an electrically insulating material; forming an electrically conductive bottom electrode layer within the further cutout; after forming the bottom electrode layer, introducing an electrically insulating capacitor dielectric layer into the further cutout; after introducing the capacitor dielectric layer, introducing an electrically conductive top electrode layer into the further cutout; patterning the bottom electrode layer, the capacitor dielectric layer and the top electrode layer to produce a capacitor forming a projection at least partially within the electrically insulating layer; and depositing a dielectric material into the areas adjacent the sides of the capacitor.