Patent ID: 7587578

Claim:
A reconfigurable processor equipped with at least one reconfigurable circuit for implementing optional logics upon data input thereinto, comprising: an input data dividing unit dividing, at a first time point, data input to the processor to generate a plurality of pieces of divided data, and outputting only a part of the plurality of pieces of divided data necessary for computing to the reconfigurable circuit; at least one retiming output buffer temporarily storing data output from the reconfigurable circuit and remaining pieces of divided data which are output from the dividing unit without being processed via the reconfigurable circuit thereby outputting at a second timing point the buffered data in matched timing as before being processed by the input data dividing unit, the second time point being later than the first time point; and an output data binding unit synthesizing at a third time point the data parts read from the retiming output buffer together in the matched timing to output the synthesized data outside of the processor, the third time point being later than the second time point, wherein, within a time period during which computing processing is not executed in the reconfigurable circuit and which is included in a time period from the inputting of the data to the processor to the outputting of the data to the outside of the processor, a logic implemented in the reconfigurable circuit is changed for the next data input to the processor by controlling a plurality of logical elements mounted in the reconfigurable circuit.