Patent ID: 7199025

Claim:
A method of fabricating multiple layers of a memory device, comprising: assembling a common substrate having multiple sections; constructing at least one fold line on the substrate to separate the multiple sections; forming first and second layers of a memory array respectively disposed on first and second sections of the multiple sections, wherein the first and the second layers comprise first and second pluralities of conductor lines, respectively; fabricating memory structures on at least the two sections of the substrate; folding the substrate along the fold line to stack the multiple sections on top of each other and align the memory structures on adjacent folded sections to form at least one operable electrical device; forming a layer of semiconductor materials disposed on at least one of the first and second layers the memory array, wherein the first and the second sections are configured to be folded along the at least one fold line so that the first and the second layers of the memory array are in contact with each other and wherein the first and the second pluralities of conductor lines are arranged to interact with each other and the layer of semiconductor materials upon folding to form at least one memory cell spanning the first and the second layers of the memory array at intersections of the first and the second pluralities of conductor lines.