Patent ID: 7035368

Claim:
A digital system comprising: circuitry for generating a reference clock signal; clock circuitry for generating a clock signal; phase circuitry connected to receive the clock signal and having outputs for providing a plurality of clock phase signals; a phase selection circuit, connected to receive the plurality of clock phase signals, the phase selection circuit having an output for providing an adjusted clock signal selected from the plurality of clock phase signals in response to a phase selection signal; a clock correlation circuit connected to receive the reference clock signal and the adjusted clock signal, the clock correlation circuit operable to determine a phase difference between the reference clock signal and the adjusted clock signal and to provide the phase selection signal such that the phase difference is minimized, wherein the clock correlation circuit includes a counter and the phase selection signal s a count value output by the counter, a first comparator connected to the counter for asserting a decrement signal if a first input of the first comparator is at a higher potential than a second input of the first comparator, a second comparator connected to the counter for asserting an increment signal if a first input of the second comparator is at a higher potential than a second input of the second comparator, a first digital to analog converter with an output connected to the second input of the first comparator and to the second input of the second comparator for generating a voltage that is correlated with the phase difference between the reference clock signal and the adjusted clock signal; a second digital to analog converter with an output connected to the first input of the first comparator for generating a voltage that is correlated with a phase difference between the reference clock signal and a first selected one of the plurality of clock phase signals that leads the adjusted clock signal by a defined phase amount; and a third digital to analog converter with an output connected to the first input of the second comparator for generating a voltage that is correlated with a phase difference between the reference clock signal and a second selected one of the plurality of clock phase signals that lags the adjusted clock signal by a defined phase amount.