Patent ID: 7925912

Claim:
A device for adjusting a timing of at least one edge of an output pulse created in response to a reference pulse, the device comprising: a first memory circuit including two or more first memory cells and configured to periodically sample the reference pulse at rising edges of a first sample clock to generate positive sample output signals, the first memory circuit providing first sample output signals for each first memory cell; a second memory circuit including two or more second memory cells and configured to periodically sample the reference pulse at falling edges of the first sample clock to generate negative sample output signals, the second memory circuit providing second sample output signals for each second memory cell; and a combinatorial logic circuit configured to produce the output pulse having at least one adjusted edge based on a set of timing instructions generated from a control node and at least one of the positive sample output signals and the negative sample output signals, wherein the control node feeds the set of timing instructions to a clock logic circuit that is coupled with one of the first and second memory circuits.