Patent ID: 7031330

Claim:
A switching system comprising: I input port mechanisms with a width, which receive packets having data from a communication line, where I is greater than or equal to 1 and is an integer; O output port mechanisms with a width, which send packets to a communication line, where O is greater than or equal to 1 and is an integer; a carrier mechanism for carrying packets in an allocated time slot, said carrier mechanism having a width wider than the width of the input and output port mechanisms so data from more than one packet at a time is transferred in the allocated time slot, said carrier mechanism connected to each input port mechanism and each output port mechanism; a memory mechanism in which packets are stored, said memory mechanism connected to the carrier mechanism; and a mechanism for providing data from more than one packet at a time to the memory mechanism through the carrier mechanism from the input port mechanisms, the providing mechanism includes input stage queue groups connected to the carrier mechanism and the input port mechanisms for storing packets received by the input port mechanisms, and output stage queue groups connected to the providing mechanism and the output port mechanisms for storing packets to be sent out the output port mechanisms, said providing mechanism transferring more than one packet at a time in the allocated time slot whose total width equals the width of the carrier mechanism in each allocated time slot to the memory mechanism, said providing mechanism transferring more than one packet at a time to the memory mechanism in the allocated time slot only when there is enough data from more than one packet from an input stage queue group to fill the width of the carrier mechanism but not transferring any data from any packets from the input stage queue group in the allocated time slot when there is not enough data to fill the width of the carrier mechanism.