Patent ID: 7296186

Claim:
A system-on-chip development test apparatus comprising: a core kernel section for constructing a logic circuit using a device integrating a RISC (Reduced Instruction Set Computer) microprocessor and a FPGA (Field Programmable Gate Array) provided therein, and processing a protocol according to at least one communication system in hardware or software; a clock section for providing a clock signal for the core kernel section; a reset section for providing a reset signal for the core kernel section; a handset interface connected to the core kernel section to perform a connection function to connect to a VoIP (Voice over Internet Protocol) handset; a BBP (BaseBand Processor) logic section comprising an FPGA (Field Programmable Gate Array), the BBP logic section being connected to the core kernel section to perform a baseband wireless modem function comprising an FPGA; a memory section connected to the core kernel section to store a start program, an operation program, user data, and various application programs; a JTAG (Joint Test Action Group) interface connected to the core kernel section to perform a connection function to connect to another debugging device; and an EIA232 interface connected to the core kernel section to perform a connection function to connect to a terminal, wherein the test apparatus operates to test a system-on-chip for verification of functions for a wire/wireless network telephone, which is directly connected to the network through a wire/wireless line and, to test a core section of the core kernel section, the core section including the RISC microprocessor and a basic control circuit.