Patent ID: 7797575

Claim:
An address concentrating processor system for communicating data with an external bus, comprising: a. three address concentrating processors, each address concentrating processor including data processing elements and a lower level address concentrator; b. a common clock circuit that generates a common clock signal that is applied to each of the address concentrating processors; c. a common bridge in communication with each of the address concentrating processors and the common clock signal, the common bridge having a common I/O interface that communicates data with the external bus, the common bridge including a highest level address concentrator that is in data communication with each of the plurality of address concentrating processors, the highest level address concentrator configured to send a command received from any of the lower level address concentrators identically and simultaneously to each of the address concentrating processors so that each of the address concentrating processors processes the data unit simultaneously, the highest level address concentrator in the common bridge configured to apply a triple-voting fault detection algorithm to information received from each of the address concentrating processors, thereby ensuring lock step operation; and d. a secondary clock circuit that receives the common signal and that generates at least one secondary clock signal that is in phase with the common clock signal, the secondary clock signal being applied to each of the address concentrating processors to provide a timing reference to a preselected processor function of each of the address concentrating processors.