Patent ID: 6996512

Claim:
A method for designing buffer and wire placement in an integrated circuit, the method comprising: representing the surface of a integrated circuit design as a tile graph; receiving an allocation of buffer locations for selected tiles in the tile graph; routing nets between a source and one or more associated sinks; and selectively assigning buffer locations within selected tiles based upon buffer needs of the nets, wherein the nets are routed through selected tiles and assigned buffer locations using a cost minimization algorithm, wherein a cost array of the cost minimization algorithm for buffer placement is computed using a single-sink buffer insertion algorithm for one associated sink and a multi-sink insertion algorithm for more then one associated sink, and wherein the selectively assigning step includes computing a cost, q(v), for using a buffer in a particular tile and the cost, q(v), is given by the equation: q ⁡ ( v ) = { b ⁡ ( v ) + p ⁡ ( v ) + 1 B ⁡ ( v ) - b ⁡ ( v ) if ⁢ ⁢ b ⁡ ( v ) B ⁡ ( v ) < 1 ∞ otherwise } wherein p(v) is a sum of probabilities for tile v over all unprocessed nets, wherein b(v) is a current number of used buffer sites, and wherein B(v) is a number of buffer sites in tile v.