Patent ID: 8037382

Claim:
A scannable flop circuit comprising: a functional flop having a data input, a clock input, and a data output; a scan flop, the scan flop having a scan data input and a scan data output; and a mode select circuit coupled between the functional flop and the scan flop, wherein the mode select circuit includes: a plurality of mode signal inputs; a first buffer configured to, when activated, convey signals from the functional flop to the scan flop and further configured to, when deactivated, inhibit signals from being conveyed from the functional flop to the scan flop; a second buffer configured to, when activated, convey signals from the scan flop to the functional flop and further configured to, when deactivated, inhibit signals from being conveyed from the scan flop to the functional flop; and a keeper coupled to the data output and configured to, when activated, hold a logic value on the data output of the functional flop; wherein the mode select circuit is configured to, depending on a state of each of a plurality mode signals received at respective ones of the plurality of mode signal inputs, wherein each of the plurality of mode signals corresponds to a respective one of a plurality of modes: activate the first buffer responsive to assertion of a first one of the plurality of mode signals; activate the second buffer responsive to assertion of a second one of the plurality of mode signals; and activate the keeper responsive to de-assertion of the second one of the plurality of mode signals when a clock signal received on the clock input of the functional flop is in a first phase.