Patent ID: 8253172

Claim:
A semiconductor device, comprising: a number of N-diffusion and a number of P-diffusion defined in a region of the semiconductor device, the number of N-diffusion arranged relative to the number of P-diffusion such that an inner non-diffusion region exists between the number of N-diffusion collectively and the number of P-diffusion collectively; at least six linear shapes extending along a first direction in a gate layer region of the region of the semiconductor device such that each of the at least six linear shapes has its lengthwise centerline extending in the first direction, the at least six linear shapes spaced apart from each other in accordance with an integer multiple of a first pitch as measured in a second direction perpendicular to the first direction between lengthwise centerlines of the at least six linear shapes, and wherein some of the at least six linear shapes are gate defining shapes, and some of the gate defining shapes forming P-transistors with respective ones of the number of P-diffusion, and some of the gate defining shapes forming N-transistors with respective ones of the number of N-diffusion, wherein the P-transistors and N-transistors define a set of at least eight transistors in the region of the semiconductor device, including, (a) a first N-transistor, a second N-transistor, a third N-transistor, and a fourth N-transistor electrically connected in a serial manner, (b) a first P-transistor, a second P-transistor, a third P-transistor, and a fourth P-transistor electrically connected in a serial manner, wherein N diffusions of the first, second, third, and fourth N-transistors do not form part of any transistor other than one or more of the first, second, third, and fourth N-transistors, wherein P diffusions of the first, second, third, and fourth P-transistors do not form part of any transistor other than one or more of the first, second, third, and fourth P-transistors, wherein the first N and P transistors have respective gate electrodes aligned along the first direction and electrically connected to each other through their gate defining shapes, wherein the second N and P transistors have respective gate electrodes aligned along the first direction, wherein the third N and P transistors have respective gate electrodes aligned along the first direction, and wherein the fourth N and P transistors have respective gate electrodes aligned along the first direction and electrically connected to each other through their gate defining shapes.