Patent ID: 8502321

Claim:
A semiconductor device comprising: a first transistor formed on a substrate and comprising a first gate electrode and first source and drain regions; a second transistor formed on the substrate and comprising a second gate electrode and second source and drain regions of a conductive type different from that of the first source and drain regions; a first contact plug electrically connected to the first source and drain regions and comprising a first bottom surface which has a longitudinal direction and a short direction, a width of the first bottom surface in a direction parallel to a gate width direction of the first gate electrode being wider than a width of the first bottom surface in a direction parallel to a gate length direction of the first gate electrode; a second contact plug electrically connected to the second source and drain regions and comprising a second bottom surface, widths in all directions of the second bottom surface being narrower than a width of the first bottom surface in the longitudinal direction, and high-concentration impurity regions being formed between the first source and drain regions and the first contact plugs, the high-concentration impurity regions being a same conductive type as that of the first source and drain regions, wherein the first contact plug is electrically connected to the first source and drain regions through the high-concentration impurity regions, at least one of extending widths of an outline of the high-concentration impurity region extending from an outline of the first bottom surface in the longitudinal direction is larger than extending widths of an outline of the high-concentration impurity region extending from an outline of the first bottom surface in the short direction, and a shape of the outline of the high-concentration impurity region substantially matches a shape of the outline of the first bottom surface.