Patent ID: 7902023

Claim:
A method of manufacturing a non-volatile semiconductor storage device, the method comprising: forming a control circuit layer, the control circuit layer comprising at least any one of a row decoder driving word lines provided in a memory cell array, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array; forming a support layer on the control circuit layer; and forming a memory cell array layer including the memory cell array on the support layer, the memory cell array layer being formed by: laminating a plurality of first conductive layers on the support layer in the lamination direction via first insulation layers; forming second conductive layers on the first conductive layers via second insulation layers; forming first trenches extending to a first direction perpendicular to the lamination direction penetrating the first insulation layers, the first conductive layers, the second insulation layers, and the second conductive layer; sequentially forming a third insulation layer, a charge accumulation layer, and a fourth insulation layer on the sidewalls of the first conductive layers facing the first trenches; forming a fifth insulation layer on the sidewall of the second conductive layer facing the first trenches; forming a semiconductor layer in contact with the fourth insulation layer and the fifth insulation layer facing the first trenches; and after forming the semiconductor layer, forming second trenches extending to a second direction perpendicular to the lamination direction and the first direction, spaced apart by a predetermined pitch in the first direction, penetrating up to the support layer.