Patent ID: 8259516

Claim:
A memory circuit for writing information into a memory cell selected by selecting a column and a row of the memory cell, the memory circuit comprising: memory cells A arranged in columns and rows; memory cells B for storing information indicative of whether writing into the memory cells A of the each of the rows has been completed or not, where an associated memory cell B is provided for each of the rows; and a logic circuit for selecting one of the rows of memory cells A by utilizing the information stored in one of the memory cells B, wherein the memory circuit is configured to: write the information indicative of a completion of a writing into a selected row of memory cells A into an associated memory cell B upon the completion of writing into the selected row of memory cells A by action of the logic circuit to send an output voltage change of the associated memory cell B to a bit line of the selected row and to a bit line of a second row of memory cells A, such that the selected row is switched from a selected state to a non-selected state, and the second row of memory cells A is switched from the non-selected state to the selected state to enable writing of the second row of memory cells A; and repeat writing into additional associated memory cells B to thereby sequentially select additional rows of memory cells A for writing information.