Patent ID: 6914935

Claim:
A fractional N synthesizer, comprising: a phase detector configured to receive first and second input signals and further configured to generate a phase detector output signal having a pulse width indicative of the phase relationship between the first and second input signals; a pulse-width-to-amplitude (PW/A) conversion circuit configured to receive the phase detector output signal and enabled to generated a PW/A output signal having an amplitude indicative of the phase detector output signal pulse; a loop filter configured to low pass filter the PW/A output signal to generate a loop filter output having voltage; a voltage controlled oscillator (VCO) configured to receive the loop filter output and further configured to generate an RF output signal having a frequency determined by the loop filter output signal voltage; a fractional N divider circuit configured to receive the VCO output signal and further configured to generate a digital signal having a frequency that is a fraction of the VCO output signal frequency, wherein the fraction is determined by a programmable divider circuit modulus; an accumulator circuit configured to receive the fractional N divider circuit output signal and enabled to alter the programmable divider circuit modulus; wherein the PW/A conversion circuit includes a current circuit connected to a capacitor, wherein the current circuit is configured to receive the phase detector output signal as an input and further configured to source a constant current during a charging phase, wherein each charging phase lasts for the duration of the phase detector output signal; and wherein the current circuit is further configured to sink a current during a discharge phase, wherein the sink current is sufficient to discharge the capacitor to a predetermined clamp voltage prior to the start of the next successive charging phase.