Patent ID: 7990791

Claim:
A semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells arranged in a matrix; a plurality of bit lines connected to memory cells arranged in a first direction in the memory cell array; a plurality of word lines connected to the memory cells arranged in a second direction crossing the first direction in the memory cell array; a plurality of sense amplifiers detecting information data on the basis of reference data transmitted to a second bit line, the information data being transmitted to a first bit line among the bit lines; a plurality of first determination transistors receiving information data detected by the sense amplifiers at their gates and making a connection between a first voltage source and a first determination node be in a conductive state or a non-conductive state on the basis of a logic value of the information data; a plurality of second determination transistors receiving the information data detected by the sense amplifiers at their gates and making a connection between the first voltage source and a second determination node be in a conductive state or a non-conductive state on the basis of the logic value of the information data; a second voltage source charging the first and the second determination nodes; and a determination unit connected to the first and the second determination nodes and detecting potentials of the first determination node and the second determination node when a logic of the information data detected by the sense amplifiers is inverted from a first logic to a second logic or from the second logic to the first logic in order to determine maximum and minimum values of potential of the information data stored in the memory cells.