Patent ID: 8924835

Claim:
A system, comprising: a content addressable memory including a plurality of core cells, the plurality of core cells configured with memory cells for storing a plurality of bits of a first entry written to the content addressable memory, the plurality of bits of the first entry being in a first state, the plurality of core cells further including comparison logic for comparing the bits of the first entry to search data inputs provided to the content addressable memory, the content addressable memory configured for providing a first output based upon the first entry, the first output including a parity bit having a first value, the parity bit being stored in a latch circuit of the system; and an encoder connected to the content addressable memory, the encoder configured for providing a first address output based upon the first entry to a memory, wherein the content addressable memory is configured for providing a second output when a state of a bit included in the plurality of bits changes from the first state to a second state, thereby changing the first entry to a second entry, the second output being a generated parity output, the generated parity output having a second value, wherein the comparison logic is configured to continuously compare the first value with the second value, producing an entry error output from the content addressable memory when the first value is different than the second value, and preventing comparing of search data inputs to the second entry, wherein each core cell included in the plurality of core cells includes an XOR2 logic gate, the XOR2 logic gates of the plurality of core cells connected together in a daisy-chain configuration.