Patent ID: 8238452

Claim:
A circuit for performing synchronization for a plurality of serial communication channels, comprising: a plurality of respective receivers for the serial communication channels, one of the receivers being a master receiver, wherein each of the respective receivers includes: a comparator configured to generate a flag for each character in a respective stream of characters received by the receiver, the flag being asserted in response to the character being a channel bonding character; a delay element configured to delay each character in the respective stream relative to the flag for the character; a FIFO buffer that is periodically written with each character delayed by the delay element and the flag from the comparator, wherein the FIFO buffer is periodically read except between a start and an end of the synchronization of the respective receiver; and a synchronizing element coupled to the FIFO buffer; wherein the synchronizing elements of the respective receivers are coupled together, wherein the start of the synchronization of the master receiver is generated in response to reading a channel bonding character from the FIFO buffer of the master receiver, wherein the start of the synchronization of each respective receiver other than the master receiver is generated after the start of the synchronization of the master receiver and in response to reading a channel bonding character from the FIFO buffer of the respective receiver, and wherein the end of the synchronization of the respective receivers is generated a time interval after the start of the master receiver.