Patent ID: 7535269

Claim:
A multiplier circuit comprising: a bias circuit which outputs a reference voltage and a bias signal; a first delay circuit which has an input signal input thereto and that outputs a first delayed signal responsive to the reference voltage and the bias signal; a second delay circuit which has an inversed input signal input thereto and that outputs a second delay signal responsive to the reference voltage and the bias signal; and an OR circuit which outputs an OR logic result responsive to the first and second delayed signals, wherein the first delay circuit includes an input node, a first inverter connected to the input node, a one-shot pulse generating circuit connected to the input node, a first PMOS transistor controlled by a first control signal, a second PMOS transistor connected to the first PMOS transistor in series, the second PMOS transistor being controlled by an output of the first inverter, a first NMOS transistor connected to the second PMOS transistor in series, the first NMOS transistor being controlled by the output of the first inverter, a second NMOS transistor connected to the first NMOS transistor in series, the second NMOS transistor being controlled by a second control signal, a capacitor connected to the second PMOS transistor, the first NMOS transistor and a reference voltage line, a switch that selectively electrically connects and disconnects the second PMOS transistor and the first NMOS transistor, and the reference voltage line, a comparator connected to the second PMOS transistor, the first NMOS transistor and the reference voltage line, and a second inverter connected to an output of the comparator.