Patent ID: 7239177

Claim:
An off-chip circuit comprising: a pre-driver circuit; and a driver circuit; wherein an output of said pre-driver circuit is coupled to an input of said driver circuit; wherein said pre-driver circuit comprises: a driver data input node; and a driver enable signal node; wherein said driver circuit comprises: an output node; and a push pull circuit connected to said output node and a power supply; wherein said push pull circuit comprises: a first p-channel transistor; a first n-channel transistor coupled to said first p-channel transistor; and a second n-channel transistor, said second n-channel transistor connected in series to said first n-channel transistor, said first n-channel transistor and said second n-channel transistor positioned between said output node and ground; wherein the gate of said first n-channel transistor is connected to said power supply to reduce an external signal level at the drain of said second n-channel transistor to avoid punch through of said second n-channel transistor; a feedback NAND circuit controlled by said driver enable signal node and said output node; an isolation circuit, said isolation circuit comprising: a second p-channel transistor; a third p-channel transistor, said second p-channel transistor and said third p-channel transistor connected in series between a first reference node and said power supply; a third n-channel transistor; and a fourth n-channel transistor; wherein said third p-channel transistor is coupled to said third n-channel transistor, and wherein said third n-channel transistor and said first n-channel transistor operate as transmission transistors; wherein the gate of said third p-channel transistor is connected to a second reference node; and wherein the gate of said third n-channel transistor is connected to said power supply to avoid punch through of said fourth n-channel transistor; a fifth n-channel transistor; and a sixth n-channel transistor, said fifth n-channel transistor and said sixth n-channel transistor connected in series between said second reference node and ground; wherein the gate of said fifth n-channel transistor is connected to said power supply to avoid punch through of said sixth n-channel transistor; wherein the gate said sixth n-channel transistor is connected to an output of said NAND circuit; and wherein said fifth n-channel transistor and said sixth n-channel transistor provide proper bias control for said isolation circuit and the output of said first p-channel transistor.