Patent ID: 8363493

Claim:
A memory controller comprising: first circuitry to drive address bits and a first timing signal to a dynamic random access memory (DRAM), wherein the address bits are associated with one or more edges of the first timing signal, wherein the first timing signal requires a first propagation delay time to propagate from the memory controller to the DRAM, wherein the address bits indicate a location within an array of the DRAM for storage of write data bits; second circuitry to drive the write data bits and to drive a second timing signal to the DRAM, wherein the write data bits are associated with one or more edges of the second timing signal, wherein the second timing signal requires a second propagation delay time to propagate from the memory controller to the DRAM; a delay circuit including a plurality of delay elements coupled in series to provide a plurality of internal delayed timing signals, each delay element providing one of the internal delayed timing signals and each delayed timing signal being a differently delayed version of an internal timing signal; and a multiplexer to select one of the delayed timing signals to be driven as the second timing signal by the second circuitry, wherein the multiplexer selects the one of the delayed timing signals based on a difference between the first propagation delay time and the second propagation delay time.