Patent ID: 8700947

Claim:
A cache memory apparatus comprising: a data holding unit configured to include a plurality of ways that has a plurality of cache lines and to hold data in the cache lines; an alternation data register configured to hold data in one line of the cache lines or in a part of the cache lines held by the data holding unit; an alternation address register configured to hold an index address that is used for cache access and indicates a faulty cache line in which a fault has occurred in the data holding unit and a part in which the fault has occurred in the faulty cache line; and an address match circuit configured to compare, when an access is performed to the data holding unit, an index address used for the access and the index address held by the alternation address register, wherein when a read access is input into the data holding unit and the comparison by the address match circuit resulted in an address match, data read out from a way corresponding to the way information held by the alternation way register are replaced with contents of the alternation data register, to be read-out data from the data holding unit.