Patent ID: 7759743

Claim:
A semiconductor memory device comprising: a memory array having a plurality of memory cells arranged in a matrix of rows and columns, each including a first and a second P-channel MOS load transistors formed in a N well region, a first N-channel MOS diver transistor formed in a first P well region, connected to said first P-channel MOS load transistor to configure a first inverter, a second N-channel MOS diver transistor formed in a second P well region, connected to said second P-channel MOS load transistor to configure a second inverter, a first N-channel MOS access transistor formed in said first P well region, connected to said first inverter, and a second N-channel MOS access transistor formed in said second P well region, connected to said second inverter, and a plurality of power feed cells, each provided corresponding to a memory cell column, which constitute a row provided to feed said first P well region, said second P well region and said N well region in a row direction to extend in a column direction respectively, wherein a first power supply line provided corresponding to said plurality of power feed cells along the row direction and electrically coupled to said power feed cell to supply a first power supply voltage to said N well region; a second power supply line provided corresponding to said plurality of power feed cells along the row direction and electrically coupled to said power feed cell to supply a second power supply voltage to said first and second P well regions, a third power supply line provided corresponding to said plurality of memory cells along the row direction and electrically coupled to said power feed cell to supply a third power supply voltage to said first and second P-channel MOS load transistors, and a forth power supply line provided corresponding to said plurality of memory cells along the row direction and electrically coupled to said power feed cell to supply a forth power supply voltage to said first and second N-channel MOS driver transistors, wherein said first power supply line is formed in a first metal interconnection layer, said third power supply line is formed in a second metal interconnection layer above said first connection layer, and said second and forth power supply lines are formed in a third metal interconnection layer above said second connection layer.