Patent ID: 7167402

Claim:
A redundancy circuit provided in a semiconductor storage device including a plurality of memory elements, first lines selected by first address signals, and second lines selected by second address signals, wherein: each of the memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge and being formed by at least one of an insulating film including an insulator having the function of holding electric charges, an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge is polarized by an electric field and in which the polarized state is held, the redundancy circuit comprising a plurality of redundant lines, programmable decoder means for selecting the redundant lines upon receipt of predetermined ones of the first address signals, the decoder means being programmed so as to recognize said predetermined ones of the first address signals, and selecting means which receives at least a part of the second address signals, the second address signals being for selecting the programmable decoder means during programming and for disabling programming of the programmable decoder means upon receipt of a certain signal.