Patent ID: 8842485

Claim:
A delay controller comprising: a delay circuit comprising a first delay unit and a second delay unit connected in series and configured to delay an input signal to generate a delayed signal, wherein the first delay unit includes a first signaling pathway, and is configured to change, based on a first delay control signal, a first amount of delay to be provided to the input signal by switching signaling pathways for transmitting the input signal that are within the first pathway, and the second delay unit includes a second signaling pathway, and is configured to (i) provide to the input signal an amount of delay which is a sum of a predetermined delay value and a second amount of delay, and (ii) change the second amount of delay based on a second delay control signal without switching the second signaling pathway for transmitting the input signal; a delay adjusting unit configured to generate the first delay control signal and the second delay control signal; and a processing unit configured to execute processing using the delayed signal generated by the delay circuit, wherein the delay adjusting unit is configured to: update the first amount of delay and the second amount of delay by updating the first delay control signal and the second delay control signal in an invalid duration in which the processing unit does not execute the processing using the delayed signal; and update the second amount of delay by updating the second delay control signal in a valid duration in which the processing unit executes the processing using the delayed signal.