Patent ID: 7492641

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array having electrically rewritable and non-volatile semiconductor memory cells arranged therein; and a sense amplifier circuit configured to read data of and hold data to be written into the memory cell array, the device being internally controlled to execute a write sequence with write pulse applications and write-verify operations repeated for writing a set of memory cells selected in the memory cell array, wherein the sense amplifier circuit performs, after a certain write pulse application at the beginning of the write sequence, a write speed verify operation for detecting write speed of plural memory cells to be written into a certain data state, thereby getting discriminating data for classifying the plural memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group, and wherein after the write speed verify operation, the first and second cell groups are alternately written on different write conditions from each other with reference to the discriminating data.