Patent ID: 8505013

Claim:
A packet processor in a network processor having a plurality of processing modules, wherein the network processor is coupled to at least one external memory and generates one or more tasks corresponding to each of a plurality of received packets, the packet processor comprising: a scheduler configured to generate one or more contexts for each task received by the packet processor, the one or more contexts associated with a thread that corresponds to an order of instructions applied to the corresponding received packet, wherein the packet processor is coupled to a tree memory within the at least one external memory, the tree memory has multiple banks and is configured to store a first subset of the instructions; and a multi-thread instruction engine configured to process the thread in accordance with a look-up table, each thread corresponding to a context received from the scheduler, the multi-thread instruction engine comprising: an instruction cache within the multi-thread instruction engine configured to store a second subset of the instructions that has a lower read latency than the first subset of the instructions, and one or more status indicators configured to track the status of the first and second subsets of the instructions within the instruction cache and the tree memory; wherein one or more instructions in the first subset of the instructions are duplicated onto the second subset of the instructions, whereby the multi-thread instruction engine is configured to access a given one of the duplicated instructions concurrently in the instruction cache and the tree memory so as to process multiple threads; wherein the multi-thread instruction engine, based on the one or more status indicators, is further configured to access the look-up table while processing the thread so as to translate between a logical address and a physical address of the corresponding instruction of the first subset and the second subset of the instructions; and a function bus interface configured to transmit the contexts within the multi-thread instruction engine and the scheduler, queue the contexts so that newer context wait for oldest context to be executed, and determine if a function call of the context is a terminating function call that causes the packet processor to end the context processing and generate an output task for subsequent processing in the network processor.