Patent ID: 6950330

Claim:
A method of driving a ferroelectric memory having an array of addressable cells, comprising: driving a plurality of word lines, each of said plurality of word lines being arranged substantially parallel to each other; and driving a plurality of bit lines, each of said plurality of bit lines being arranged substantially parallel to each other, the plurality of word lines and bit lines being orthogonal such that the crossing points of the word lines and bit lines create the array of cells; wherein the driving performs read and write operations on the plurality of word lines and bit lines by changing the voltages across selected cells, wherein the change in potential difference on any non-addressed cell does not significantly exceed ⅓ Vs wherein the potential difference across each non-addressed cell is about ⅓ V s , wherein the potential difference across addressed cells is V s for a read operation and a write operation involving a change in the polarization state and ⅓ V s for a write operation when no change in the polarization state shall occur, wherein an addressed cell is a cell corresponding to an active bit line and active word line and a non-addressed cell is every other cell, and an active bit or word line is a bit or word line activated to read or write a cell and an inactive bit or word line is a bit or word line not activated to read or write a cell.