Patent ID: 7769954

Claim:
A data processing system comprising: a cache memory comprising a plurality of ways, each of which stores a data line including a data and address information of the data; an analysis module that analyzes whether or not a data requested in a read instruction is to be used in a subsequent instruction to be executed within a predetermined time period after the execution of the read instruction is started; a mode selection module that selects one of a plurality of access modes for accessing the cache memory based on a result of the analysis module; and an access unit that accesses the cache memory in the selected one of the access modes when the read instruction is executed, wherein the plurality of access modes comprise: a high-speed access mode that gives a higher priority to the small number of clock cycles required for reading data from the cache memory; and a low-power access mode that gives a higher priority to a small power consumption taken for reading data from the cache memory; wherein the selection module selects the high-speed access mode when the data read by the read instruction is to be used in the subsequent instruction, and wherein the selection module selects the low-power access mode when the data read by the read instruction is not to be used in the subsequent instruction.