Patent ID: 8748215

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: forming a gate electrode layer including a flat surface over a surface of a base; forming a gate insulating layer over the gate electrode layer; forming a first oxide semiconductor layer over the gate insulating layer; causing crystal growth which proceeds from an upper surface toward an inside of the first oxide semiconductor layer by first heat treatment to form a first non-single crystalline layer; forming a second oxide semiconductor layer over the first non-single crystalline layer; causing crystal growth which proceeds from the first non-single crystalline layer toward an upper surface of the second oxide semiconductor layer over the first non-single crystalline layer by second heat treatment to form a second non-single crystalline layer; and forming a source electrode layer and a drain electrode layer over a stack of the first non-single crystalline layer and the second non-single crystalline layer, wherein a bottom interface whose crystal is aligned of the first non-single crystalline layer is provided to be spaced from a surface of the gate insulating layer.