Patent ID: 8691630

Claim:
A method of manufacturing a semiconductor package structure, comprising: providing a conductive substrate, the conductive substrate having a first surface and a second surface opposite to the first surface; adhering a heat-conductive block to a portion of the second surface of the conductive substrate via a first adhesive layer; after adhering the heat-conductive block to the portion of the second surface of the conductive substrate via the first adhesive layer, removing a portion of the conductive substrate by performing a half-etching process on the first surface of the conductive substrate to form an opening on the first surface of the conductive substrate; patterning the remaining conductive substrate to form a plurality of leads electrically insulated from one another and to expose a portion of the heat-conductive block, each of the plurality of leads having a first portion and a second portion, a thickness of each first portion being greater than a thickness of each second portion, a first lower surface of each first portion and a second lower surface of each second portion being coplanar; after patterning the remaining conductive substrate to form the plurality of leads electrically insulated from one another and exposing the portion of the heat-conductive block, disposing a chip on the exposed portion of the heat-conductive block, wherein the second portions of the plurality of leads neighbor and surround the chip, and the chip is electrically connected to the second portions of the plurality of leads; and forming a molding compound to encapsulate the chip, a portion of the plurality of leads, and the exposed portion of the heat-conductive block, and a bottom surface of the heat-conductive block is exposed by the molding compound.