Patent ID: 7356047

Claim:
A system for implementing 2.5 Gbps Ethernet on a 10/100/1000 Ethernet legacy infrastructure, with the system comprising: a physical layer (PHY) chip including: a multi-rate (PHY) module for transferring and receiving data to and from a data transfer medium at a data transfer rate of either 2500/1000/100/10 Mbps, with the PHY module including a Tx PHY portion having a GMII (Gigabit Media Independent Interface) configured to receive frame data bytes at a clock rate of either 2.5, 25, 125, or 312.5 MHz and with the PHY module having an Rx PHY portion having a GMII configured to send frame data bytes at a clock rate of either 2.5, 25, 125, or 312.5 MHz; an 802.3z physical coding sublayer (PCS) module including an 802.3z PCS Rx state machine configured to receive encoded data bytes at a clock rate of 312.5 MHz and configured to send data bytes at a clock rate of 312.5 MHz and with the 802.3z PCS module further including an 803.2z PCS Tx state machine configured to receive data bytes at a clock rate of 312.5 MHz and configured to transmit encoded data bytes having a clock rate of 312.5 MHz; and a rate adaptation unit, coupling the PHY module and the 802.3z PCS module, configured to compensate for the difference between the 312.5 MHz clock rate of the 802.3z PCS module and the 2.5, 25, 125 data transfer rates of the PHY module, with the rate adaptation module having a PHY Rx rate adapter, coupling the Rx PH portion and the 802.3z PCS Tx state machine, configured to form elongated frames having each having first and second segments, with the first segment repeating a first frame byte a multiple of 2 time and the second segment repeating second frame byte a multiple of 3, times when transferring data between the Rx PH portion and 802.3z PCS Tx state machine and with the rate adaptation unit having a PHY Tx rate adapter, coupling the 802.3z PCS Rx state machine and the Tx PHY portion, configured to sample each segment of a received elongated frame only once when transferring data between the 802.3z PCS Rx state machine and the Tx PHY portion.