Patent ID: 8180996

Claim:
A multi processor system, comprising: a first processor section integrated circuit having a first processing unit, a first memory controller coupled to the first processor unit, a first high speed communication port and a memory local to the first processor section that is coupled to the first memory controller; a second processor section integrated circuit adjacent the first processor section integrated circuit, the second processor section having a second processing unit and a second memory controller coupled to the second processor unit, a memory local to the second processor section that is coupled to the second memory controller and a second high speed communication port, wherein the first processor section and second processor section communicate with each other using the first and second high speed communication ports; and the first memory controller and the second memory controller each being capable of controlling memories local to the respective memory controller and a global virtual memory, wherein first memory controller and the second memory controller each uses multiple levels of virtual memory to map a file system into global virtual memory and the memories local to the respective memory controllers.