Patent ID: 8731006

Claim:
A signal multiplexing circuit for receiving data signals of first and second channels which are RZ (Return to Zero) signals, and for generating a multiplexed signal obtained by time-division multiplexing the data signals of the first and second channels at a repetition period T of the first and second channels, comprising: defining T 1 as the pulse period of the data signal of the first channel, defining T 2 as the pulse period of the data signal of the second channel, further defining T 1 and T 2 such that T=T 1 +T 2 ; a first pulse generating circuit converting the data signal of the first channel to a signal which has a period of m as the pulse width of the “Hi” level and a period of T 1 −m as the pulse width of the “Lo” level of a logic “1” data signal of the first channel based on a clock signal; a second pulse generating circuit converting the data signal of the second channel to a signal which has a period of n as the pulse width of the “Hi” level and a period of T 2 −n as the pulse width of the “Lo” level of a logic “1” data signal of the second channel based on the clock signal; a time-division multiplexing circuit time-division multiplexing and outputting the data signals of the first and second channels as a multiplexed signal having “Hi” level period m, “Lo” level period T 1 −m, “Hi” level period n, and “Lo” level period T 2 −n, wherein the minimum value of the “Hi” level period n and the “Lo” level periods (T 1 −m) and (T 2 −n) is not smaller than a predetermined value while n<m is satisfied.