Patent ID: 8358552

Claim:
A sense amplifier (nSA) of a series of cells (Ci, Cj) of a memory, including: a writing stage comprising a CMOS inverter (T 1 -T 2 ), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, and a reading stage comprising a sense transistor (T 3 ), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter; wherein each of the transistors has a back control gate formed in the base substrate below the channel and capable of being biased in order to modulate the threshold voltage of the transistor.