Patent ID: 7773236

Claim:
An image forming processing circuit having a clock stop function, comprising: an image forming processing unit that has processing blocks constituted in plural stages, clocks for processing being separately inputted to the processing blocks in plural stages, the processing block at a first stage processing, when a main scanning signal and a sub-scanning signal of a predetermined time width specifying a two-dimensional valid image area and an image information signal scanned by these main and sub-scanning signals are inputted, the image information signal in accordance with the clock in a period in which the main scanning signal is valid and outputting a result of the processing, and the processing blocks at next and subsequent stages processing, when a main scanning signal and a sub-scanning signal for a next stage involving a predetermined clock delay with respect to a pre-stage and an image information signal processed at the pre-stage are inputted, the image information signal in accordance with the clocks in a period in which the main scanning signal is valid and outputting a result of the processing; a judging unit that cancels a stop state of supply of the clocks to the processing blocks at the respective stages when the main scanning signal and the sub-scanning signal are inputted; and a clock control unit that starts the clock supply to the processing blocks at the respective stages when the clock supply stop state is canceled by the judging unit and inputs main scanning signals for the processing blocks at the respective stages, respectively, and, when a main scanning signal corresponding to a processing clock is invalidated, stops the supply of the clock to the processing block using this main scanning signal.