Patent ID: 8390127

Claim:
A semiconductor device, comprising: a first transistor having a first transistor width and a first transistor length and comprising a first gate electrode structure that extends along a first transistor width direction; a second transistor comprising a second gate electrode structure and having an opposite conductivity type of said first transistor; an interlayer dielectric material above said first and second transistors, wherein said interlayer dielectric material comprises a stressed dielectric layer around and above said first and second gate electrode structures, and said entire stressed dielectric layer has a first type of intrinsic stress of a substantially uniform first magnitude; a first contact trench positioned in said interlayer dielectric material and connecting to at least one of a drain region and a source region of said first transistor, wherein said first contact trench has a first trench length that continuously extends along said first transistor width direction and a first trench width that is substantially parallel to said first transistor length direction, said first contact trench comprising a stressed conductive material having a second type of intrinsic stress that is of an opposite type from said first type; and a second contact trench positioned in said interlayer dielectric material and connecting to at least the other one of said drain and said source region of said first transistor, wherein said second contact trench has a second trench length that continuously extends along said first transistor width direction and a second trench width that is substantially parallel to said first transistor length direction, wherein at least one of said second trench length and said second trench width is different than said first trench length and said first trench width, respectively, and wherein said second contact trench comprises said stressed conductive material.