Patent ID: 6956262

Claim:
A pull-up element for a silicon based semiconductor circuit comprising: a silicon based n-channel metal insulator semiconductor (MIS) field effect transistor (FET) configured to include a trapping region situated proximate to an interface with a channel of said silicon based MISFET, said channel coupling a high voltage potential supplied to the silicon based semiconductor circuit and a first node of the silicon based semiconductor circuit; said trapping region including carrier trapping sites configured for trapping and de-trapping charge carriers from said channel; wherein said trapping sites are characterized by an energy level that is higher than a conduction band edge of said channel and lower than a conduction band of said trapping region; said trapping sites further having a concentration and arrangement so that said channel can be controlled and shut off by operation of said trapping region to reduce static power dissipation by the pull-up element during operation of the silicon based semiconductor circuit.