Patent ID: 8525263

Claim:
A memory device comprising: a semiconductor substrate including a first portion and a second portion; a programmable memory device present in the first portion of the semiconductor substrate comprising a first gate structure and spacers abutting the first gate structure, the first gate structure comprising a first metal gate electrode in direct physical contact with a first high-k gate dielectric that is selected from the group consisting of HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 and mixtures thereof, wherein a portion of the first high-k gate dielectric extends beyond a sidewall of the first metal gate electrode, and is present beneath the spacers abutting the first gate structure, wherein an outer edge of the first high-k gate dielectric is aligned with an outer edge of the spacers abutting the first gate structure; and a semiconductor device present in the second portion of the semiconductor substrate, the semiconductor device comprising a second gate structure, the second gate structure comprising a second metal gate electrode atop a second high-k gate dielectric, wherein a sidewall of the second metal gate electrode is aligned to an edge of the second high-k gate dielectric.