Patent ID: 8193622

Claim:
A semiconductor die package comprising: a mounting surface adapted to be mounted to a printed circuit board; a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface, the second bottom semiconductor die surface facing toward the mounting surface and the first top semiconductor die surface facing away from the mounting surface; a leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface, wherein the second leadframe surface is coupled to the first top semiconductor die surface using a reflowable solder, the leadframe further having at least one lead with a portion coplanar with the mounting surface; a clip disposed at the mounting surface, between the semiconductor die and the mounting surface, and having a first clip surface and a second clip surface, wherein the second clip surface is coupled to the second bottom semiconductor die surface; and a molding material having exterior molding material surfaces and covering at least a portion of the leadframe, the clip, and the semiconductor die, wherein the first leadframe surface and the first clip surface are exposed by the molding material, and wherein the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package.