Patent ID: 7869388

Claim:
A full-duplex transceiver for transmitting and receiving a signal on a differential pair channel, comprising: a transmitter comprising, on a common substrate: a bias generator configured to generate a transmitter reference voltage equal to V REF +V GS , and a DAC segment coupled to the bias generator, the DAC segment comprising: first and second main source follower transistors, each main source follower transistor having a gate configured to receive the reference voltage and a drain coupled to the differential pair channel, first and second replica source follower transistors, each replica source follower transistor having a gate configured to receive the reference voltage, a first Class B amplifier having a resistance R and coupling sources of the first main and first replica source follower transistors to ground, and a second Class B amplifier having the resistance R and coupling sources of the second main and second replica source follower transistors to ground; a receiver having an input; and a summing node connected to the differential pair channel, drains of the replica source follower transistors, and the input of the receiver, the summing node configured to combine the signal on the differential pair channel and signals from the replica source follower transistors such that signals from the main source follower transistors are reduced in a signal at the input of the receiver, wherein: a gate-source voltage drop across one of the source follower transistors is V GS , a voltage at the sources of the source follower transistors is V REF , and an output current generated by the transmitter at the drains of the source follower transistors when the Class B amplifier is on is V REF /R.