Patent ID: 7646626

Claim:
A memory device, comprising: a plurality of non-volatile memory elements arranged in an array having a plurality of columns and a plurality of rows; a plurality of switches, wherein each switch is connected to one of the plurality of memory elements; a plurality of column lines, wherein each column line connects the memory elements disposed in a particular column; a plurality of row lines, wherein each row line connects the switches disposed in a particular row; access circuitry for accessing two or more of the memory elements disposed in a particular row in parallel; a plurality of row ground lines disposed in parallel with the row lines, wherein each row ground line connects the switches disposed in a particular row; and at least one column ground line disposed in parallel with the column lines and interconnecting the plurality of row ground lines; wherein the column ground line and row ground lines conduct currents applied by the circuitry passing through the memory elements and through the switches.