Patent ID: 7545027

Claim:
A wafer level package, comprising: a semiconductor substrate supporting an electrode pad; a first insulating layer provided on the semiconductor substrate, the first insulating layer having a first opening through which the electrode pad is exposed; a seed metal layer provided on the electrode pad and the first insulating layer; a redistribution interconnection metal layer provided on a portion of a surface of the seed metal layer so that an edge portion of the surface of the seed metal layer is exposed; a second insulating layer provided on the exposed edge portion of the surface of the seed metal layer and the redistribution interconnection metal layer, the second insulating layer having a second opening through which a portion of the redistribution interconnection metal layer is exposed, the exposed portion of the redistribution interconnection metal layer being spaced apart from the electrode pad; and an external connection electrode provided on the exposed portion of the redistribution interconnection metal layer, wherein the seed metal layer extends beyond a side of the redistribution interconnection metal layer, and the second insulating layer is provided on the redistribution interconnection metal layer and the extended portion of the seed metal layer.