Patent ID: 7829417

Claim:
A method of manufacturing a semiconductor apparatus with a superjunction structure including a column region, comprising: forming a gate electrode in a mesh pattern in a crystalline semiconductor layer; forming a photo resist pattern for forming an ion implantation region in the crystalline semiconductor layer, the photo resist pattern being formed by using a photomask, the photomask having a compensation pattern in such a way that the compensation pattern is surrounded by the gate electrode in a plane view and distances, measured using the line perpendicular from one linear edge of the gate electrode to the compensation pattern gradually change depending on a location on the one linear edge of the gate electrode, and the compensation pattern has a shape depending on an impurity diffusion coefficient along a crystal plane direction of said ion implantation region in the crystalline semiconductor layer; forming the ion implantation region by using the photo resist pattern, wherein the ion(s) have at least two different diffusion coefficients in the crystalline semiconductor layer and the mask is formed of such a shape to compensate for the differences in the diffusion coefficients; and performing heat treatment on the crystalline semiconductor layer.