Patent ID: 6864152

Claim:
A method of forming an isolation structure on an integrated circuit substrate, comprising: providing a substrate configured so that it includes: a silicon layer that overlies a buried oxide layer; a pad oxide layer overlying the silicon layer; and a nitride layer overlying the pad oxide layer; forming a first pattern mask over the substrate such that a first pattern of apertures is formed the first pattern mask; first etching of the nitride layer through apertures defined by the first pattern mask to form a fist set of trenches in the nitride layer having a first depth; removing the first pattern mask; forming a second pattern mask over the substrate that defines a second pattern of apertures in the second pattern mask; second etching of the of the substrate through the apertures defined by the second pattern mask to form a second set of trenches of a second depth in the substrate and to extend the depth of exposed portions of the first set of trenches to a third depth; and third etching of the of the substrate through the apertures defined by the second pattern mask to form to extend the depths of the second set of trenches to a fourth depth and to further extend the depth of exposed portions of the second set of trenches.