Patent ID: 6846709

Claim:
A method of fabricating an electronic device comprising: implanting a dopant into an area of a semiconducting substrate, the implanted area being located within a region isolated by a dielectric isolator; depositing a film stack over the implanted and dielectric isolator areas, the film stack including a first dielectric layer and a first polysilicon layer; etching a dielectric window through the first dielectric layer; depositing a second dielectric layer into the dielectric window and over the film stack; etching the second dielectric layer anisotropically to form a first spacer; etching portions of the film stack lying between the implanted area and the first dielectric layer anisotropically thereby forming an epitaxial via; filling the epitaxial via with epitaxial silicon, thereby forming an epitaxial channel; forming a second polysilicon layer over the epitaxial channel; depositing a third dielectric layer over the second polysilicon layer and surrounding areas; etching the third dielectric layer anisotropically to form a second spacer; etching the first polysilicon layer; depositing a fourth dielectric layer over the second polysilicon layer and the first polysilicon layer; etching the fourth dielectric layer to form a third spacer; and etching any remaining layers surrounding the third spacer down to substantially a level of the implant area.