Patent ID: 7439790

Claim:
A level shifter circuit, comprising: a first level shifter unit, comprising: a first transistor comprising a first gate, a first source/drain and a second source/drain, wherein the first source/drain is electrically connected to a first voltage; a second transistor comprising a second gate, a third source/drain and a fourth source/drain, wherein the second gate is electrically connected to the second source/drain, the third source/drain is electrically connected to the first voltage, and the fourth source/drain is electrically connected to the first gate; a first diode, wherein a first end of the first diode is electrically connected to the second source/drain, and a second end of the first diode receives an inverted clock pulse signal; a first capacitor electrically connected to the first diode in parallel; a second diode, wherein a first end of the second diode is electrically connected to the fourth source/drain, and a second end of the second diode receives a clock pulse signal; a second capacitor electrically connected to the second diode in parallel; a second level shifter unit, comprising: a third transistor comprising a third gate, a fifth source/drain and a sixth source/drain, wherein the third gate is electrically connected to the second gate, and the fifth source/drain is electrically connected to the first voltage; a third diode, wherein a first end of the third diode is electrically connected to the sixth source/drain, and a second end of the third diode is electrically connected to a second voltage; a fourth transistor comprising a fourth gate, a seventh source/drain and a eighth source/drain, wherein the fourth gate is electrically connected to the second gate, and the seventh source/drain is electrically connected to the first voltage; and a fifth transistor comprising a fifth gate, a ninth source/drain and a tenth source/drain, wherein the fifth gate is electrically connected to the sixth source/drain, the ninth source/drain is electrically connected to the eighth source/drain, and the tenth source/drain is electrically connected to the second voltage; wherein the ninth source/drain outputs a first level adjusted clock pulse signal corresponding to the clock pulse signal.