Patent ID: 7295257

Claim:
A manufacturing method of a thin film transistor array panel, comprising steps of: forming a gate wiring pattern, including a gate line, a gate electrode, and a gate pad on an insulating substrate; forming a gate insulating layer on the gate wiring pattern; forming a semiconductor pattern on the gate insulating layer; forming a transparent conductive layer on the gate insulating layer; patterning the transparent conductive layer to form a pixel electrode; and, forming an opening at a circumference of the pixel electrode, wherein the step of forming the opening comprises a step of removing any portion of the semiconductor pattern remaining in the opening, and the step of removing any portion of the semiconductor pattern remaining in the opening comprises adjusting the etch selectivity between the gate insulating layer and the semiconductor pattern to be substantially small, or by performing a dry etching process at a high etch rate while adjusting an etching gas and an etching time such that the remaining semiconductor pattern is substantially removed from the opening.