Patent ID: 8624260

Claim:
An enhancement-mode transistor comprising: a channel layer including GaN; a barrier layer, the barrier layer including AlGaN touching the channel layer; a lower transition layer touching the barrier layer; a region of Si 3 N 4 , the region of Si 3 N 4 touching the lower transition layer on the lower side of the Si 3 N 4 , wherein the Si 3 N 4 layer and the barrier layer share anions to produce the lower transition layer; an upper transition layer touching the Si 3 N 4 on the upper side of the Si 3 N 4 , the upper transition layer produced by an oxidation of the Si 3 N 4 ; a region of SiO 2 , the region of SiO 2 having a top surface, touching the, upper transition layer and lying over the region of Si 3 N 4 ; and a metal gate, the metal gate having a bottom surface that touches the top surface of the region of SiO 2 in a horizontal plane, and being spaced apart from the region of Si 3 N 4 , no portion of the region of SiO 2 lying above the horizontal plane, a spaced-apart metal source region and metal drain region that touch the barrier layer, wherein the barrier layer including AlGaN is below a threshold of thickness such that when substantially zero volts are applied to the metal gate region, and the metal gate region and the metal drain region are differently biased, substantially no electrons comprise a two-dimensional electron gas region between the barrier layer including AlGaN and the channel layer including GaN; and when a voltage that exceeds a threshold voltage of the enhancement-mode transistor is applied to the metal gate region, and the metal source region and the metal gate region are differently biased, electrons accumulate in the two-dimensional electron gas region between the barrier layer including AlGaN and the channel layer including GaN, and the electrons flow from the metal source region to the metal drain region.