Patent ID: 8759939

Claim:
A semiconductor device arrangement, comprising: a semiconductor layer; at least one series circuit with a first semiconductor device and with a plurality of n second semiconductor devices, with n>1, the first semiconductor device having a load path and having active device regions integrated in the semiconductor layer, each of the second semiconductor devices having active device regions integrated in the semiconductor layer and having a load path between a first and a second load terminal and a control terminal, the second semiconductor devices having their load paths connected in series and connected in series to the load path of the first semiconductor device, each of the second semiconductor devices having its control terminal connected to one of the load terminals of another one of the second semiconductor devices or to one of the load terminals of the first semiconductor device; and an edge termination structure, wherein there is at least the load path of the another one of the second semiconductor device between the one of the load terminals of the another one of the second semiconductor devices and the second semiconductor device that has its control terminal connected to the one of the load terminals of the another one of the second semiconductor devices.