Patent ID: 7495986

Claim:
A system comprising: a memory including dynamic memory cells, an internal voltage generator generating an internal voltage to be supplied to an internal voltage line, and a power supplying circuit supplying a power supply voltage as said internal voltage, the memory having a low power consumption mode, in which the dynamic memory cells do not retain data therein by stopping the operation of the internal voltage generator, by supplying said power supply voltage as said internal voltage by operating said power supplying circuit, and by prohibiting refresh operations, and an idle mode that operates said internal voltage generator, stops the operation of said power supplying circuit, and can perform the refresh operations, and a memory controller outputting a command signal to the memory during the idle mode, thereby entering the memory into the low power consumption mode, wherein said memory has a low power entry circuit to control the operations of said internal voltage generator and said power supplying circuit, and to switch between the low power consumption mode and the idle mode in response to the command signal.