Patent ID: 7398406

Claim:
A data processor comprising: a clock pulse generation circuit; and a circuit module operating on a clock signal output from said clock pulse generation circuit; wherein said clock pulse generation circuit stepwise changes frequencies of said clock signal from low to high frequencies, when a power-on reset is released according to input of a reset signal to said data processor from outside; wherein said clock pulse generation circuit comprises a PLL circuit and a divider; wherein said divider comprises a plurality of dividing circuits, a selection circuit to select outputs from said dividing circuit, and a frequency control circuit to control said selection circuit; wherein, upon release from said power-on reset, said frequency control circuit controls said selection circuit to select output states of said dividing circuit so as to change a frequency of said clock signal from a low frequency to a high frequency in a stepwise manner; wherein said circuit module includes a central processing unit; and wherein said circuit module includes an asynchronous DRAM controller, a display controller, and a rendering controller.