Patent ID: 8879742

Claim:
An apparatus for determining a spatial output multi-channel audio signal based on an input audio signal, comprising: a semantic decomposer configured for decomposing the input audio signal to obtain a first decomposed signal having a first semantic property, the first decomposed signal being a foreground signal part, and a second decomposed signal having a second semantic property being different from the first semantic property, the second decomposed signal being a background signal part; a renderer for rendering the first decomposed signal using a first rendering characteristic to obtain a first rendered signal having the first semantic property and for rendering the second decomposed signal using a second rendering characteristic to obtain a second rendered signal having the second semantic property, wherein the first rendering characteristic and the second rendering characteristic are different from each other, wherein the renderer comprises a first DirAC monosynth stage for rendering the foreground signal part, the first DirAC monosynth stage being configured for creating a first mono-DirAC stream leading to a perception of a nearby point-like source, and a second DirAC monosynth stage for rendering the background signal part, the second DirAC monosynth stage being configured for creating a mono-DirAC stream leading to a perception of spatially-spread sound, wherein a mono-DirAC stream comprises omnidirectional signal data and directional data, and wherein the corresponding DirAC monosynth stage is configured for generating the directional data by controlling, in time or frequency, directional data input into the corresponding DirAC monosynth stage; and a processor for processing the first rendered signal and the second rendered signal to obtain the spatial output multi-channel audio signal, wherein the processor comprises a DirAC merging stage for merging the first mono-DirAC stream and the second mono-DirAC stream, wherein at least one of the semantic decomposer, the renderer, and the processor comprises a hardware implementation.