Patent ID: 8195986

Claim:
A system for processing errors comprising: a processor comprising: a first local fault isolation register having a first unique identifier, the first register operative to store a first error data; a second local fault isolation register having a second unique identifier, the second register operative to store a second error data; a global fault isolation register that summarizes a status of the first and second local fault isolation registers; host firmware operative to retrieve the first error data from the first local fault isolation register, associate the first error data with the first unique identifier of the first local fault isolation register, retrieve the second error data from the second local fault isolation register, associate the second error data with the second unique identifier of the second local fault isolation register, retrieve status data from the global fault isolation register, and generate a first uniform error packet including the first error data and the first unique identifier of the first local fault isolation register, the second error data and the second unique identifier of the second local fault isolation register, and the status data from the global register; and an error database storage medium operative to store a first uniform error summary compiled from the first uniform error packet; and a processing device comprising an error database processing program that accesses the error database and analyzes the error data in the first uniform error summary.