Patent ID: 8058919

Claim:
A delay circuit, comprising: a resistance element; a capacitor element; and a connection wiring including a first silicide layer connecting said resistance element and said capacitor element, wherein said connection wiring further includes a first polysilicon layer provided above a semiconductor substrate, said first silicide layer being provided on said first polysilicon layer, said capacitor element includes: a diffusion layer provided in a surface region of said semiconductor substrate, a gate insulating layer provided on said diffusion layer, a second polysilicon layer provided on said gate insulating layer, and a second silicide layer provided on said second polysilicon layer, said resistance element includes a third polysilicon layer provided above said semiconductor substrate, said first polysilicide layer, said second polysilicide layer, and said third polysilicon layer are integrally provided, and said first silicide layer and said second silicide layer are integrally provided.