Patent ID: 8916910

Claim:
A reconfigurable 3D interconnect, comprising: an array of vertical interconnect vias; and a routing circuit connected to each vertical interconnect via of the array of vertical interconnect vias, an input/output node of a first core element, and an input/output node of a second core element stacked above the first core element to allow re-routing of a signal through the array of vertical interconnect vias during operation, wherein the routing circuit is configured to selectively connect each vertical interconnect via of the array of vertical interconnect vias from a ground line, voltage line, or floating line to a signal path between the input/output node of the first core element and the input/output node of the second core element and vice versa in a plurality of configurations during operation for routing a signal between the input/output node of the first core element and the input/output node of the second core element, wherein the plurality of configurations include a first configuration comprising a plurality of the vertical interconnect vias selectively connected for routing the signal between the input/output node of the first core element and the input/output node of the second core element, a second configuration comprising more of the vertical interconnect vias than the first configuration, and a third configuration comprising less or different ones of the vertical interconnect vias than the first configuration.