Patent ID: 8634511

Claim:
A digital phase frequency detector (PFD) comprising: a detection unit configured to detect an edge of a reference signal and an edge of a feedback input signal to generate a reference edge signal and a feedback edge signal; a reset unit configured to generate a reset signal that resets the detection unit based upon the reference edge signal and the feedback edge signal; and a phase comparison unit configured to generate a first phase comparison signal and a second phase comparison signal based upon the reference edge signal and the feedback edge signal, the phase comparison unit comprising: a first flip-flop having a data input terminal configured to receive the reference edge signal and a clock input terminal configured to receive the feedback edge signal, and configured to generate a first comparison signal based upon the reference edge signal and the feedback edge signal; a second flip-flop having a data input terminal configured to receive the feedback edge signal and a clock input terminal configured to receive the reference edge signal, and configured to generate a second comparison signal based upon the reference edge signal and the feedback edge signal; and a latch block configured to latch the first comparison signal and the second comparison signal to generate the first phase comparison signal and the second phase comparison signal.