Patent ID: 7612391

Claim:
A semiconductor integrated circuit comprising: a first flip-flop comprising a first latch circuit and a second latch circuit; a first logic circuit connected to an output node of the first flip-flop; a first power line; a second power line; and a third power line, wherein: an output node of the first latch circuit is connected with the output node of the first flip-flop, an input node of the second latch circuit is connected with the output node of the first latch circuit or an input node of the first latch circuit, the first latch circuit and the first logic circuit is supplied with a first operation voltage through the first and the second power line, the second latch circuit is supplied with a second operation voltage through the first and the third power line, a first difference between a width of the first power line and a width of the third power line is larger than a second difference between the width of the third power line and a width of a wiring for connecting the input node of the second latch circuit and the output node or input node of the first latch circuit, a third difference between the width of the second power line and the width of the third power line is larger than the second difference, the third power line has a first state and a second state, and a potential of the third power line in the second state is higher than a potential of the third power line in the first state.