Patent ID: 7433238

Claim:
A method of programming a memory cell including a substrate, a drain and a source disposed in the substrate, and a gate disposed on the substrate between the drain and the source, wherein the gate comprises, sequentially from the substrate, a first oxide layer, a nitride layer, a second oxide layer and a polysilicon layer, the method comprising: performing a first programming operation, comprising applying a first gate voltage to the gate, applying a first drain voltage to the drain, applying a first source voltage to the source, and applying a first substrate voltage to the substrate, so as to inject electrons into the nitride layer adjacent to a side of the drain through a channel hot electron injection (CHEI) effect; and performing a second programming operation, comprising applying a second gate voltage to the gate, applying a second drain voltage to the drain, applying a second source voltage to the source, and applying a second substrate voltage to the substrate, so as to inject the electrons into the nitride layer adjacent to a side of the source through a CHEI effect, wherein the second gate voltage is less than the first gate voltage.