Patent ID: 8471295

Claim:
A flash memory cell string constructed with sequentially connected cell devices and at least one switching device for selecting the cell string which is located at an end of the connected cell devices, wherein each of the cell devices includes a semiconductor substrate and a tunneling insulating layer formed on the semiconductor substrate, and a charge storage node, a control insulating layer and a first control electrode which are formed in the described order on the tunneling insulating layer, wherein the cell devices do not include source and drain regions, and wherein a first region of the substrate directly under the first control electrode is doped more highly than a second region which extends from the upper surface of the substrate between the cell devices, wherein the first and second regions are both doped regions, so that, during operation of the cell device, an inversion layer is easily induced by a fringing electric field generated by sides of the control electrode and then effectively suppress a short channel effect.