Patent ID: 8110896

Claim:
A capacitor component-embedded substrate structure, comprising: a substrate having first and second surfaces and one or more holes penetrating the first and second surfaces; a capacitor component disposed in each of the one or more holes of the substrate, wherein the capacitor component has a plurality of electrode pads on at least one surface, and the at least one surface of the capacitor component is a rough surface, and wherein the capacitor component comprises a metallic roughness layer formed on a side of the capacitor component so as to increase bonding strength between the side of the capacitor component and walls of the holes of the substrate; first and second dielectric layers respectively formed on the surfaces of the substrate and capacitor components, allowing the capacitor components to be secured in position in the holes of the substrate, in which the dielectric layers have openings to expose the electrode pads of the capacitor components, and gaps between the substrate and the metallic roughness layer of the capacitor components are filled with either one or both of the first and second dielectric layers so as to secure in position the capacitor components in the holes of the substrate; circuit layers formed on the surface of the dielectric layers, having conductive structures in the openings of the dielectric layers, so as to allow the circuit layers to be electrically connected to the electrode pads of the capacitor components; a circuit build-up structure formed on the surface of the first and second dielectric layers and the circuit layers, wherein the circuit build-up structure further comprises dielectric layers, circuit layers stacked on the dielectric layers, and conductive structures formed in the dielectric layers, in which the conductive structures are formed in the circuit build-up structure so as to be electrically connected to the circuit layer on the surface of the first and second dielectric layers while electrical connection pads are formed on the surface of the circuit build-up structure; and a plurality of plated through holes penetrating the circuit layers on the first and second surfaces of the substrate and the circuit build-up structure.