Patent ID: 7291926

Claim:
A multi-chip package structure comprising: a third substrate having a top surface and a bottom surface; a first sub-package having a top surface and a bottom surface, wherein the bottom surface of the first sub-package is attached to the top surface of the third substrate directly, the first sub-package includes: a first substrate having a top surface and a bottom surface, the first substrate being electrically connected to the third substrate; a first chip attached to the top surface of the first substrate and electrically connected to the first substrate; and a first molding compound used for encapsulating the first chip and part of the top surface of the first substrate; a second sub-package having a top surface and a bottom surface, wherein the bottom surface of the second sub-package is attached to the top surface of the first sub-package, the second sub-package including: a second substrate having a top surface and a bottom surface, the second substrate being electrically connected to the third substrate; a second chip attached to the top surface of the second substrate and electrically connected to the second substrate; and a second molding compound used for encapsulating the second chip and part of the top surface of the second substrate; and a third molding compound used for encapsulating the first sub-package, the second sub-package and the top surface of the third substrate.