Patent ID: 7202540

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a gate insulating film formed on said semiconductor substrate; a gate electrode formed by patterning on said gate insulating film; a pair of diffusion layers formed at both sides of said gate electrode and in a surface layer of said semiconductor substrate; and a pair of sidewall films formed on side surfaces of said gate electrode, wherein one diffusion layer of said pair of diffusion layers is formed to be aligned with said gate electrode, and wherein the other diffusion layer of said pair of diffusion layers includes a lightly-doped impurity region formed to be aligned with said gate electrode and doped with impurities at a concentration lower than the concentration of said one diffusion layer, and a heavily-doped impurity region formed to be aligned with said sidewall film and doped with impurities at a concentration higher than the concentration of said lightly-doped impurity region.