Patent ID: 7068541

Claim:
A nonvolatile memory comprising: a memory array unit having a plurality of nonvolatile memory cells; a control unit; and a voltage generating unit for supplying voltages to said nonvolatile memory cells, wherein said nonvolatile memory cells store information corresponding to a quantity of electric charges in a floating gate of each nonvolatile memory cell, wherein said control unit controls a write operation to store information into said nonvolatile memory cells, a read operation to read information stored in said nonvolatile memory cells; and an erase operation to erase information stored in said nonvolatile memory cells, wherein said voltage generating unit has an erase voltage generating unit for generating, in accordance with control from said control unit, erase voltages to be applied to said nonvolatile memory cells in said erase operation, and wherein said erase voltage generating unit generates, in response to a control signal supplied from said control unit, erase voltages of two or more levels including a lower erase voltage and a higher erase voltage, and wherein said control unit performs control such that in said erase operation the lower erase voltage is applied to a control gate of each of said nonvolatile memory cells and thereafter the higher erase voltage is applied to the control gate of each of said nonvolatile memory cells.