Patent ID: 7095405

Claim:
An output control circuit, which is used together with transfer means in which a number of unit circuits that shift a starting pulse sequentially in synchronization with a clock signal are in cascade connection with each other, and generates a set of a positive logic output signal and a negative logic output signal which is an inversion of the positive logic output signal based on an output signal from each of the unit circuits, the output control circuit having, a first logic operation unit which, based on an output signal from a unit circuit and an output signal from a subsequent-stage unit circuit, generates an output signal that is enabled in a period while the output signals from the two unit circuits are enabled at the same time, and, a second logic operation unit which generates the positive logic output signal and the negative logic output signal based on the output signal from the first logic operation unit, and controls an enabling period of the positive logic output signal or the negative logic output signal based on the output signal from a first logic operation unit in a subsequent-stage output control circuit.