Patent ID: 7387925

Claim:
A method for fabricating a PMOS device, comprising: depositing epitaxially a monocrystalline SiGe seed layer directly onto a relaxed SiGe layer, wherein said SiGe seed layer has between about 50% and 90% of Ge concentration and a thickness of between about 0.3 nm and about 3 nm, wherein said relaxed SiGe layer has up to about 50% of Ge concentration; depositing epitaxially a monocrystalline compressively strained Ge layer directly onto said SiGe seed layer, wherein said compressively strained Ge layer has a thickness of between about 5 nm and about 20 nm; depositing epitaxially a monocrystalline Si top layer directly onto said compressively strained Ge layer, wherein said Si top layer has a thickness of between about 0.3 nm and about 4 nm; executing said epitaxial depositions of said SiGe seed layer, said compressively strained Ge layer, and said Si top layer, in such manner as to be selective in regard to dielectric materials; hosting a p-channel in said compressively strained Ge layer, wherein said PMOS device comprises said p-channel; and using a high-K material in a gate insulator, wherein said PMOS device comprises said gate insulator.