Patent ID: 8799621

Claim:
Apparatus for processing data comprising: memory address translation circuitry configured to perform a top down page table walk operation to translate a virtual memory address to a physical memory address using translation data stored in a hierarchy of translation tables; wherein said translation data specifies translations between pages of 2 N contiguous bytes of virtual memory addresses and corresponding pages of 2 N contiguous bytes of physical memory addresses, where N is a positive integer; said hierarchy of translation tables comprises translation tables of 2 N contiguous bytes in size such that a complete translation table is stored within one page of said physical memory; and said memory address translation circuitry is responsive to a page size variable specifying a current value of N to control said memory address translation circuitry to operate with a selected size of pages of physical memory addresses, pages of virtual memory addresses and translation tables, wherein a predetermined portion of said virtual address extending from a most significant bit end of said virtual address is given a fixed translation to a corresponding portion of said physical address without requiring a page table walk.