Patent ID: 8654562

Claim:
A method of fabricating a memory in an integrated circuit, comprising the steps of: forming first and second transistors within each of a plurality of adjacent bit cell areas at a semiconducting surface; forming one or more buffer circuit transistors within each of the bit cell areas, the one or more buffer circuit transistors having features larger than corresponding features of the first and second transistors, the first and second transistors and buffer circuit transistors arranged in the bit cell area so that the first transistor is disposed within its bit cell area between the buffer circuit transistors and the second transistor of that bit cell area; forming interconnections among the first and second transistors and buffer circuit transistors within each bit cell to define first and second cross-coupled inverters, the first inverter including the first transistor and the second inverter including the second transistor, an output of one of the first and second inverters coupled to the buffer circuit transistors; wherein the second transistors in first and second adjacent bit cell areas are disposed adjacent one another; wherein the buffer circuit transistors in first and third adjacent bit cell areas are disposed adjacent one another; and wherein the forming steps form the first transistor in each bit cell area to differ from the second transistor in its bit cell area in one or more physical attribute selected from the group consisting of channel width, channel length, and net channel dopant concentration.