Patent ID: 7245191

Claim:
A phase-locked loop (PLL) circuit with self-selecting variable divide ratio, comprising: an L-C tank oscillator having an input and which produces a clock output having a frequency that varies within a predetermined frequency range with a control voltage applied to said input; a variable divider having an divide ratio control input and which receives said L-C tank oscillator clock output and divides it by a divide ratio value that varies with a divide ratio control signal applied to said divide ratio control input; a phase detector which receives a reference clock and said divided-down L-C tank oscillator clock at respective inputs and produces one or more outputs that vary with the difference in phase between said inputs; and a loop filter which receives at least one of said phase detector outputs and provides said control voltage to said L-C tank oscillator input so as to reduce the difference in phase between said reference clock and said divided-down L-C tank oscillator clock; and a frequency band select circuit which provides said divide ratio control signal to said variable divider's divide ratio control input such that a divide ratio value is selected which enables said phase difference to be driven toward zero with said L-C tank oscillator clock output within said predetermined frequency range, wherein said PLL circuit has a predetermined loop gain specification, said frequency band select circuit arranged to provide said divide ratio control signal such that said PLL circuit's loop gain remains within said predetermined loop gain specification.