Patent ID: 6944069

Claim:
A semiconductor memory device comprising: a plurality of memory cell arrays; an enable master signal generator which receives a predetermined signal and generates a column select line enable master signal; a disable master signal generator which receives the predetermined signal and generates a column select line disable master signal; a plurality of enable master signal delayers which delay the column select line enable master signal; a plurality of disable master signal delayers which delay the column select line disable master signal; a plurality of column select line enable controllers which generate column select line enable control signals, respectively, in response to signals output from the enable master signal delayers; a plurality of column select line disable controllers which generate column select line disable control signals, respectively, in response to signals output from the disable master signal delayers; and a plurality of column select line drivers which drive column select lines of the related memory cell arrays, respectively, in response to signals output from the column select line enable controllers and signals output from the column select line disable controllers.