Patent ID: 7099196

Claim:
A flash memory device comprising: a memory cell array block having a plurality of flash memory cells arrayed therein; a program verification voltage generator structured to variably generate program verification voltages to verify whether the flash memory cells are programmed or not; and a word line level selector structured to transfer the program verification voltages to word lines connected to control gates of the flash memory cells; wherein the program verification voltage generator comprises: a PMOS transistor and a series of resistors, which are connected between a power supply voltage and a ground reference voltage; a first NMOS transistor connected to both terminals of a first resistor and structured to electrically short the first resistor in response to a first program verification control signal and to generate a program verification voltage at a node between drains of the PMOS transistor and the first NMOS transistor; a second NMOS transistor connected to both terminals of a second resistor and structured to electrically short the second resistor in response to a second program verification control signal; and a comparator structured to compare a reference voltage to a voltage of a node between the first and second resistors, and having an output connected to a gate of the PMOS transistor.