Patent ID: 8399314

Claim:
A method of fabricating a field effect transistor (FET), comprising the steps of: providing a doped substrate having a dielectric thereon; placing at least one silicon nanowire on the dielectric; masking off one or more portions of the nanowire leaving other portions of the nanowire exposed; growing epitaxial germanium on the exposed portions of the nanowire; interdiffusing the epitaxial germanium with silicon in the nanowire to form silicon germanium regions embedded in the nanowire that introduce compressive strain in the nanowire, wherein the doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded silicon germanium regions serve as source and drain regions of the FET; and further increasing a concentration of germanium in the silicon germanium regions using germanium condensation.