Patent ID: 7157372

Claim:
A method performed on a wafer having multiple chips each including a doped semiconductor and substrate, the method comprising: a) etching an annulus trench from an outer surface of the doped semiconductor, through the doped semiconductor, and partially into the substrate to a total depth of at least 100 microns; b) metalizing an inner and an outer perimeter side wall and a bottom surface of the annulus trench by applying a metal thereto; c) etching a via trench into the wafer between the outer surface and the substrate and peripherally bounded within a portion of the doped semiconductor that is within the periphery of the annulus trench, the via trench having a periphery and a bottom and being bounded about the periphery by the doped semiconductor and at the bottom by the substrate; d) making a length of the via trench, extending from the substrate to the outer surface, and at least a portion of the bottom of the via trench, electrically conductive; and e) thinning a surface of the substrate opposite the doped semiconductor until at least the substrate covering the bottoms of the annulus trench and via trench are both removed so as to expose the metal and the electrically conductive material.