Patent ID: 8164974

Claim:
An interleaved memory circuit comprising: a first memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line; a first local control circuit coupled with the first memory bank; a second memory bank including at least one second memory cell for storing a charge representative of a second datum, the second memory cell being coupled with a second word line and a second bit line; a second local control circuit coupled with the second memory bank; an IO block coupled with the first memory bank and the second memory bank; and a global control circuit coupled with the first and second local control circuits, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.