Patent ID: 8803276

Claim:
In a structure of an integrated circuit chip, the structure comprising: a substrate with a region of triple wells, N-Wells separated by and isolated from a P-Well therein; a MOSFET with a source, drain and gate in the isolated P-Well; a lateral p-n-p having a base, emitter and collector in each of the N-Wells and integrated with the MOSFET; an input/output pad coupled to the emitters of the lateral p-n-p and to the drain of the MOSFET; and VDD applied to each of the bases of the lateral p-n-p, the source and the gate of the MOSFET and the collectors of the lateral p-n-p and source of the MOSFET being connected to ground, whereby a parasitic lateral n-p-n turns on and safely discharges ESD current to ground when an ESD event occurs by creating an avalanche generation of carriers near the drain of the P-Well junction and an increase in the lateral p-n-p collector current.