Patent ID: 7809994

Claim:
A flash memory system, comprising: a flash memory device, having a plurality of memory cells arranged into pages and blocks, each page having a number of memory cells sufficient to store data for a plurality of sectors, and each block having a plurality of pages; a flash memory controller, coupled to the flash memory device, comprising: a host interface, for interfacing to a host system; a device interface, for interfacing to the flash memory device; and controller circuitry for managing the writing of user data received at the host interface to the flash memory device according to a sequence of operations comprising: receiving user data corresponding to a first plurality of sectors via the host interface; encoding error correction coding (ECC) bits for a unitary data block, the unitary data block comprising the user data corresponding to the first plurality of sectors and control data corresponding to a sector not including user data and not including header data associated with user data, so that the ECC bits are encoded using both the user data and the control data together, wherein the control data comprises data related to operation or management of the flash memory system; programming a first page to store the encoded unitary data block; reading the programmed first page; decoding the read first page, using the ECC bits, to recover the data bits as a unitary data block including the data corresponding to the first plurality of sectors; and retrieving a desired sector of data from the decoded unitary data block.