Patent ID: 7292672

Claim:
A register circuit comprising a passage control circuit and a holding circuit, wherein the passage control circuit includes a first transistor having a gate to which a clock signal is input, a second transistor having a gate to which a data signal is input, and a third transistor having a gate to which a control signal is input, a source-drain path of the first transistor, a source-drain path of the second transistor, and a source-drain path of the third transistor are connected in series, the passage control circuit enables passage of a first data signal input in the passage control circuit to the holding circuit according to a state of the clock signal when the control signal is in a first state that is one of an active state and an inactive state, and disables passage of a second data signal input in the passage control circuit to the holding circuit when the control signal is in a second state that is one of the active state and the inactive state and different from the first state, and when the control signal is in the second state, the holding circuit latches the first data signal passed from the passage control circuit.