Patent ID: 7868442

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein: the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes: a semiconductor chip having a first surface with a device formed thereon, a second surface opposite to the first surface, and four side surfaces; an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and a plurality of electrodes connected to the semiconductor chip; the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed; each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions; and the plurality of layer portions include at least a pair of layer portions that are disposed such that the first surfaces of the respective semiconductor chips face toward each other.