Patent ID: 7454672

Claim:
A semiconductor memory device operable in a merged data input/output pin (DQ) test mode, comprising: a first path circuit receiving a first data bit, a second single data rate (SDR) signal, and a first transmission signal pair and producing a first path output signal and including a first switching element controlled by the second single data rate signal; a second path circuit receiving a second data bit, a first single data rate signal, and a second transmission signal pair and producing a second path output signal and including a second switching element controlled by the first single data rate signal; and a merged output generator configured to generate a merged data bit based on the first path output signal and the second path output signal having a single data rate (SDR) pattern and/or a dual data rate (DDR) pattern, as determined by the first single data rate signal fed to the second switching element and the second single data rate signal fed to the first switching element and the first and second transmission signal pairs.