Patent ID: 8572323

Claim:
A device comprising: at least one processor core; a memory hierarchy coupled to each of the at least one processor core and including a memory and one or more levels of cache, wherein each cache has a cache result register (CRR) which captures cache access information that can be utilized to access a location at which specific information is stored within the cache; and transaction address processing logic within each cache of the memory hierarchy that responsive to receipt of a transaction address of a dummy transaction while the one or more levels of caches are in debug mode determines whether the transaction address of the dummy transaction hits within the cache; wherein in response to a hit of the transaction address of the dummy transaction within the cache, the transaction address processing logic automatically updates the CRR of the cache with the cache access information and passes the transaction address down to a next level of the memory hierarchy; and wherein in response to a miss of the transaction address of the dummy transaction within the cache, the transaction address processing logic passes the transaction address down to a next level of the memory hierarchy.