Patent ID: 6947047

Claim:
A programmable graphics processor operable in any one of a parallel processing mode and a serialized mode, said processor comprising; at least two processing pipelines, wherein each of the pipelines is configured to process data in accordance with a program, including by executing branch instructions; and mode control circuitry coupled and configured to receive instructions for pipelined execution of the program, to assert the instructions to the pipelines, to monitor the instructions at least in the parallel processing mode to identify each branch instruction of the instructions before execution of the branch instruction in any of the pipelines, and to cause the processor to operate in the serialized mode when necessary to prevent any conflict between the pipelines due to branching, wherein in the parallel processing mode, data values are launched into N of the pipelines during one clock cycle, where N≧2, and the data values are processed in parallel in said N of the pipelines in accordance with the program with said N of the pipelines each executing identical instructions, and in the serialized mode, each data value launched into one of the pipelines is processed in said one of the pipelines while operation of each other one of the pipelines is frozen.