Patent ID: 8175198

Claim:
A matched filter for calculating a correlation between a received signal and a known symbol Y of length N, N being a power of 2, to output an absolute value, where the symbol Y is symmetric in the sense that Y[k]=−Y[N−k], where k=1, . . . , N/2−1, and Y[0]=0, the matched filter comprising: (N−2) stage serial delay circuits; N/2 conjugation circuits; N/2 multiplication circuits, each of them adapted to receive a symbol component Y[k], k=1, . . . N/2, through a respective one of the conjugation circuits; a summing circuit for summing outputs of the multiplication circuits; an absolute value circuit for calculating an absolute value of the output from the summing circuit; and (N/2−1) addition circuits for receiving signals of length N directly and via the N−2 stage delay circuits and for subtracting the (N−1)-th to (N/2+1)-th second half signal components from the 1st to (N/2−1)-th first half signal components, respectively, wherein the multiplication circuits are adapted to receive the subtracted signal components from the addition circuits and to multiply them with respective ones of the symbol components Y[k], k=1, . . . , N/2−1, at respective clock timings.