Patent ID: 7861028

Claim:
A system for configuration and management of flash memory, comprising: a flash memory, comprising a plurality of physical erase units, each physical erase unit being configured to comprise a plurality of consecutive segments, each segment being configured to comprise a plurality of consecutive frames, each frame being configured to comprise a plurality of consecutive pages, said segments and said frames being a plurality of newly defined basic data access control units for said flash memory; a virtual memory region, being configured to comprise a plurality of areas, each area being configured to comprise a plurality of virtual erase units, said areas and said virtual erase units being the newly defined basic data access control units for said flash memory; and a memory logical block region, being configured to comprise a plurality of clusters, each cluster comprising a plurality of consecutive memory logical blocks, said clusters being the newly defined basic data access control units for said flash memory; wherein a mapping correspondence is formed among said physical erase units, segments, frames, pages of said flash memory, said virtual erase units, said areas of said virtual memory region, and said memory logical blocks, said clusters of said memory logical block region, and configuring the sizes of said segments, frames, areas, and clusters to adjust memory consumption and data access efficiency for said flash memory.