Patent ID: 8053358

Claim:
A method of forming an integrated circuit device, comprising: forming an interlayer insulating layer on a semiconductor substrate, said interlayer insulating layer comprising a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer; forming a contact hole that extends through the interlayer insulating layer and exposes the semiconductor substrate, by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material; forming a polysilicon layer on sidewalls of the first and second electrically insulating layers within the contact hole and on the exposed portion of the semiconductor substrate within the contact hole; etching the polysilicon layer to form a spacer that is arranged on the exposed portions of the sidewalls of the first electrically insulating layer and exposed portions of a lower surface of the second insulating layer; and then filling the contact hole with an electrically conductive plug.