Patent ID: 8355293

Claim:
An integrated circuit comprising: a supply voltage node and a retention voltage node; retention voltage generation circuitry configured receive a supply voltage from said supply voltage node and to provide a retention voltage at said retention voltage node; and functional circuitry connected between said retention voltage node and a reference voltage node, said functional circuitry configured to be held in a data retention state when at least a minimum voltage is provided between said retention voltage node and said reference voltage node, each of said functional circuitry and said retention voltage generation circuitry comprising at least one p-type threshold device and at least one n-type threshold device, said p-type threshold devices and said n-type threshold devices respectively having a characteristic threshold voltage, wherein said at least one p-type threshold device and said at least one n-type threshold device in said retention voltage generation circuitry are connected in parallel between said supply voltage node and said retention voltage node, wherein a variation in said characteristic threshold voltage of either said at least one p-type threshold device or said at least one n-type threshold device in said functional circuitry, is accompanied by a corresponding variation in said characteristic threshold voltage of either said at least one p-type threshold device or said at least one n-type threshold device respectively in said retention voltage generation circuitry, thus maintaining at least said minimum voltage between said retention voltage node and said reference voltage node and thus keeping said functional circuitry in said data retention state.