Patent ID: 8084305

Claim:
A method comprising: forming a dielectric layer directly on a semiconductor substrate; forming a silicon semiconductor mesa on the dielectric layer, wherein the silicon semiconductor mesa has a first surface and a second surface each substantially parallel to a top surface of the semiconductor substrate, the first surface being opposite the second surface, and wherein the first surface is spaced a first distance from the semiconductor substrate and the second surface of the silicon semiconductor mesa is spaced a second distance from the semiconductor substrate, the first distance being greater than the second distance; forming an undercut region in the dielectric layer, wherein the undercut region extends laterally underneath the silicon semiconductor mesa; forming a gate stack on the semiconductor mesa, wherein the silicon semiconductor mesa extends laterally beyond the gate stack; and forming a first source region and a first drain region using selective epi growth (SEG) of at least one of silicon germanium and silicon carbide, wherein the first source region and first drain region are grown on the first surface of the silicon semiconductor mesa and surrounding the silicon semiconductor mesa such that an interface is formed between each of the first source region and the first drain region and the first surface of the silicon semiconductor mesa, wherein the interface formed between the first source region and the first surface of the silicon semiconductor mesa is between the first source region and a channel region of the silicon semiconductor mesa; wherein the first source and the first drain regions substantially fill in the undercut and wherein the silicon semiconductor mesa does not include the first source region or the first drain region.