Patent ID: 8468504

Claim:
A computer-implemented method comprising: displaying a graphical representation of assembly code instructions including multiple individual operations that have been scheduled by an automated instruction scheduler, for execution by a target VLIW processor, along with a graphical representation of one or more instruction-scheduling constraints; displaying a linear list view of the individual operations, wherein the individual operations are arranged in topological order and displayed alongside each operation is a graphical indicator indicating the scheduling state of the operation, wherein possible scheduling states include: scheduled, ready, and not ready; displaying a grid view of individual operations scheduled in cells of a two-dimensional grid, wherein columns of the grid correspond with VLIW issue slots and rows of the grid correspond with cycle numbers; displaying directed lines to show a partial view of a dependency graph indicating specified levels of a parent-child relationship of a selected operation in the list and grid view; displaying dotted lines to show latencies associated with a selected operation and that of the selected operation's parents in the grid view; highlighting those VLIW issue slots in the grid view where a selected operation can be scheduled; and facilitating interactive reordering of the multiple individual operations by means of the graphical user interface.