Patent ID: 7243170

Claim:
An instruction buffer, comprising: a physical memory array partitioned into multiple physical and identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple physical instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of said memory sub-arrays, said set of concurrent instructions arranged in sequential order from a first instruction to a last instruction; a rotator multiplexer adapted to receive said set of concurrent instructions and direct each instruction of said set of concurrent instructions to an entry position in different consecutive memory sub-arrays; an output multiplexer adapted to order a sequence of instructions read out of said memory array to match the order of instructions in said set of concurrent instructions; a write address decoder adapted to determine a write address of a wordline of said memory array to which said first instruction of said set of instructions will be written; a read address decoder adapted to determine a read address of a wordline of said memory array from which a first instruction of a group of instructions will be read from; wherein a number of write ports is less than a number of instructions to be written into said memory array and a number of read ports is less than a number of instructions to be read out of said memory array; wherein each instruction entry position is defined by a physical instruction entry position and a corresponding logical instruction entry position, each logical instruction entry position in a particular memory sub-array is a fixed number higher than an immediately previous logical instruction entry position in said particular memory sub-array; wherein said physical instruction entry positions in each memory sub-array are one logical instruction entry position higher than corresponding physical entry positions of a immediately previous memory sub-array, the first physical instruction entry position and first logical instruction entry position of a first memory sub-array being the same; and wherein each said instruction of said set of concurrent instructions is stored in consecutive logical instruction entry positions of said memory array.