Patent ID: 7724093

Claim:
A phase locked loop (PLL) circuit comprising: a digitally controlled oscillator (DCO) for generating an output signal; and a phase frequency detector (PFD) for providing a control signal to control the oscillator, the PFD having a first input coupled to receive a feedback clock signal representative of the oscillator output signal from the oscillator and a second input coupled to receive a reference clock signal, and wherein the PFD includes: a frequency detection stage adapted to calculate a frequency difference between the feedback clock signal and the reference clock signal in a frequency detection mode and to adjust the control signal based on the frequency difference; a phase detection stage adapted to calculate a phase error between the feedback clock signal and the reference clock signal in a phase detection mode; a switch for switching between the frequency detection mode and the phase detection mode upon a frequency of the feedback clock signal reaching a predetermined value; a pattern shift stage that calculating the average frequency error based on a phase detector output signal; and a correction means for applying a correction to the control signal so as to compensate for average frequency error.