Patent ID: 7600081

Claim:
A data processing system comprising: a multiport memory module having N first ports and J second ports, wherein N and J are integers greater than one; N first data communication buses and J second data communication buses; N hardware acceleration modules that communicate with a respective one of the N first ports on a respective one of the N first data communication buses, wherein a first one of the N hardware acceleration modules performs a first processing task on data and transmits the data to the multiport memory module on a first one of the N first data communication buses, a second one of the N hardware acceleration modules receives the data from the multiport memory module on a second one of the N first data communication buses and performs a second processing task on the data, wherein the N hardware acceleration modules store intermediate data in the multiport memory module while performing processing tasks; J-A processor modules and J-B dynamic random access memory (DRAM) modules that communicate with the multiport memory module on respective ones of the J second data communication buses, wherein A and B are integers greater than or equal to one, and A+B=J; and a shared bus, comprising: a first bus portion; a second bus portion; and a bus bridge that communicates with the first bus portion and the second bus portion, wherein the N hardware acceleration modules communicate on the first bus portion at a first rate and the J-A processor modules and J-B dynamic random access memory (DRAM) modules communicate on the second bus portion at a second rate.