Patent ID: 7924620

Claim:
A nonvolatile semiconductor memory comprising: a memory cell transistor which includes a charge accumulation layer, a control gate, and a first impurity diffused layer, the charge accumulation layer being formed on an active region, the first impurity diffused layer acting as a source and a drain; a first MOS transistor which is formed on the active region, the first MOS transistor including a first gate electrode and a second impurity diffused layer, the second impurity diffused layer acting as a drain and a source, the source being commonly connected to the drain of the memory cell transistor; a second MOS transistor which is formed on the active region, the second MOS transistor including a second gate electrode and a third impurity diffused layer, the third impurity diffused layer acting as a drain and a source, the drain being commonly connected to the source of the memory cell transistor; a first voltage generating circuit which applies a first voltage to the active region to generate a forward bias between the active region and the first to third impurity diffused layers; and a second voltage generating circuit which applies a second voltage to the control gate of the memory cell transistor which is not a write target, the second voltage generating circuit applying a third voltage to the control gate of the memory cell transistor which is the write target, the third voltage being higher than the second voltage, after the first voltage generating circuit charges the first to third impurity diffused layer to the first voltage, the second voltage generating circuit applying the second voltage and the third voltage to the control gate of the memory cell transistor while the active region is grounded, thereby forming channels in the memory cell transistor and the first and second MOS transistors, after the channels are formed, the first MOS transistor and the second MOS transistor being cut off to set the formed channels to a floating state.