Patent ID: 8493763

Claim:
A content addressable memory (CAM) device including a CAM array comprising: a reference row including a plurality of reference CAM cells coupled to a reference match line, the reference match line configured to generate a self-timed control signal; and a plurality of regular rows, each comprising: a first row segment including a number of first CAM cells coupled to a first match line segment; a second row segment including a number of second CAM cells coupled to a second match line segment; and a control circuit configured to selectively disable the second row segment in response to match results in the first row segment and the self-timed control signal, wherein the control circuit comprises: a pull-down transistor coupled between the second CAM cells and ground potential, and having a gate; and a combinational logic gate having a first input coupled to the first match line segment, having a second input to receive the self-timed control signal, and having an output coupled to the gate of the pull-down transistor.