Patent ID: 7278010

Claim:
An instruction execution apparatus, in information processing equipment, comprising: a commit stack entry units having a plurality of entries, and storing, according to a clock signal cycle, instructions in order, executing said instructions out of order using a superscalar method, and then releasing entries from said commit stack entry unit in order and in response to a completion signal indicating that the executing of said instructions is completed; a register, which is separate from the commit stack entry unit, storing only a copy of contents of each of a maximum number of entries that can be completed simultaneously in one cycle, the storing in the separate register at one cycle before a cycle for determining completion conditions of the entries in said commit stack entry unit, and an entry at a head of said maximum number of entries stored in the register storing an oldest unreleased instruction among all the entries in said commit stack entry unit; a completion condition determination section determining whether the instructions stored in the entries of said separate register are completed in a-the cycle for determining completion conditions of the entries in said commit stack entry unit; and an entry release section releasing only the entries that are determined to be completed by said completion condition determination section among all entries in said commit stack entry unit, and updating resources of said information processing equipment when an entry is released.