Patent ID: 8543757

Claim:
A method of operating a memory system that includes a memory circuit having an array of non-volatile memory cells and a controller circuit, the controller overseeing the transfer of user data between a host and the memory array and managing the storage of user data on the memory array, the method comprising: receiving from the host at the controller one or more segments of user data identified by a respective logical address; assigning by the controller of a respective physical address in a first block of the memory array to each of the segments of user data; maintaining by the controller of a mapping of the correspondence between the respective logical and physical addresses for each of the segments of user data; writing a first set of one or more of the segments of user data as a plurality of write pages to the corresponding assigned physical addresses in the first block of the memory array; writing the logical to physical mapping for the first set of segments of user data to a write page of the first block, wherein the logical to physical mapping includes the logical to physical mapping of one or more of the segments of user data written to the first block prior to writing the logical to physical mapping thereto; and subsequently performing a data consolidation operation including: consolidating segments of the first set of segments of user data from the first block into a second block; and writing the logical to physical mapping for the consolidated segments of the first set of segments to a third block dedicated to storing logical to physical mappings.