Patent ID: 7598598

Claim:
A semiconductor package comprising: a leadframe comprising: a die pad defining opposed, generally planar top and bottom die pad surfaces and a peripheral edge; at least one tie bar connected to and extending from the peripheral edge of the die pad; and a plurality of leads extending at least partially about the die pad in spaced relation to the peripheral edge thereof, each of the leads defining: a generally planar top lead surface; a generally planar bottom lead surface disposed in opposed relation to the top lead surface; a recessed lead shelf formed within the top lead surface adjacent the peripheral edge of the die pad; and a pair of ear portions extending laterally from respective sides of each of the leads in opposed relation to each other, the ear portions each having a top ear surface which extends in generally co-planar relation to the top lead surface and a bottom ear surface which is recessed relative to the bottom lead surface; a semiconductor die attached to the top die pad surface and electrically connected to at least one of the leads; and a package body at least partially encapsulating the leadframe and the semiconductor die such that the bottom lead surface of each of the leads is exposed within the package body.