Patent ID: 8599312

Claim:
An apparatus comprising: a digital signal processor (DSP) configured to demodulate a digitized analog television signal encoded in a plurality of analog-to-digital (ADC) output signals that form a complex representation of a low-intermediate frequency (IF) signal obtained from a radio frequency (RF) signal, the DSP comprising: first automatic gain control (AGC) circuitry to time and compensate for gain variation in the low-IF signal; digital compensation circuitry to compensate for RF and IF gain and phase distortion; zero intermediate frequency (ZIF) channelization filter circuitry to receive and filter the digitally compensated digitized analog television signal to obtain a filtered ZIF signal; second AGC circuitry coupled to an output of the ZIF channelization filter circuitry to compensate for gain variation in the filtered ZIF signal; and a phase lock loop (PLL) coupled to an output of the second AGC circuitry to relocate a carrier of the compensated ZIF signal to a substantially DC signal; and a microcontroller coupled to the DSP to configure and control the DSP, wherein the microcontroller is to control a variable rate clock for spur avoidance.