Patent ID: 8309414

Claim:
A method of manufacturing a semiconductor device, said method comprising: forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which is included in a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell of a DRAM (Dynamic Random Access Memory) or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM; forming an extension region of said first transistor and an extension region of said second transistor; forming a first sidewall in a sidewall of said first gate electrode; forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode; and forming a source and drain region in each of said first transistor and said second transistor, wherein a layer structure of said first sidewall is the same as a layer structure of said second sidewall.