Patent ID: 6940430

Claim:
A Gray code decoder for decoding input numbers, comprising: a first select circuit to select a M-bit Gray code number from a M-bit Gray code having a one-bit separation I and a two-bit separation J; a second select circuit to select a N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M≧N, and at least one of I and J is greater than, or equal to, 2 N ; a concatenate circuit to concatenate the selected M-bit Gray code number and the selected N-bit Gray code number to produce a K-bit Gray code number; wherein to generate the next 2 N −1 sequential K-bit Gray code numbers, the first select circuit is further to select a next M-bit Gray code number from the M-bit Gray code, and the concatenate circuit is further to concatenate the selected M-bit Gray code number and the selected N-bit Gray code number to produce a next K-bit Gray code number; and wherein the second select circuit is further to select a next N-bit Gray code number from the N-bit Gray code; and a decoding circuit to decode the input numbers according to the K-bit Gray code numbers.