Patent ID: 7779083

Claim:
A buffer device, for transmitting a plurality of messages between a source controller and a destination controller, comprising: a plurality of message rows, for storing the messages that the source controller intends to transmit to the destination controller, each of the message rows at least comprising a write complete flag and a distribution complete flag; a write control unit, coupled between the source controller and the plurality of message rows, used to sequentially output a plurality of free message row addresses according to the plurality of distribution complete flags, wherein when the buffer device still has a free message row, the source controller reads an address of a target message row that is currently free among said plurality of message rows, and the distribution complete flag of the target message row is set by the write control unit; and when the source controller completes writing a message of the target message row, the write complete flag of the target message row is set by the write control unit, and a read request for informing the destination controller to read the message of the target message row is issued; and when the buffer device has no free message row, said write control unit outputs a non-free message row signal; and a read control unit, coupled between the destination controller and the plurality of message rows, to issue the read request to inform the destination controller to read the message of the target message row when the write complete flag of the target message row is set, wherein once the destination controller completes reading the message of the target message row in response to the read request, the distribution complete flag set by the write control unit and the write complete flag of the target message row are both cleared by the read control unit, wherein the distribution complete flag has not been cleared by the write control unit before being cleared by the read control unit; wherein the plurality of message rows are coupled between the write control unit and the read control unit.