Patent ID: 7998862

Claim:
A method of fabricating a semiconductor device, comprising: forming a first isolation layer on a semiconductor substrate; forming a via hole through the first isolation layer in the semiconductor substrate; forming a second isolation layer on an inner side including a bottom of the via hole; removing the bottom portion of the second isolation layer so as to expose a portion of the semiconductor substrate; forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner side of the via hole including the bottom portion of the via hole where the second isolation layer is formed by depositing a diffusion barrier material over the substrate where the second isolation layer is formed and anisotropically etching the diffusion barrier material to expose the bottom portion of the semiconductor substrate through the bottom portion of the via hole; arranging a solvent, which contains electrically charged metal particles, on the semiconductor substrate where the diffusion barrier layer is formed; filling the via hole with the metal particles by moving the metal particles using applied external force, the applied external force including a voltage causing an electric current to flow between the semiconductor substrate and the solvent; removing the solvent after the via hole is filled with the metal particles by its top portion; and curing the semiconductor substrate after removing the solvent.