Patent ID: 7313032

Claim:
A static random access memory (“SRAM”), comprising: a plurality of SRAM cells arranged in an array, said array including a plurality of rows and a plurality of columns; and a plurality of voltage control circuits corresponding to respective ones of said plurality of columns of said array, each of said plurality of voltage control circuits coupled to an output of a power supply, each said voltage control circuit being operable to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells belonging to a selected column of said plurality of columns, said selected column being selected during a write operation in which a bit is written to one of said plurality of SRAM cells belonging to said selected column, wherein each said voltage control circuit includes an n-type field effect transistor (“NFET”) and a p-type field effect transistor (“PFET”), each of said NFET and said PFET having a conduction path connected between the output of the power supply and said power supply inputs of said plurality of SRAM cells.