Patent ID: 7564286

Claim:
A clock regeneration circuit at which a multi-level input signal of a predetermined period, with at least two signal levels, is inputted and which outputs a clock signal synchronized with the predetermined period, the clock regeneration circuit comprising: a first delay device that delays the multi-level input signal by a duration shorter than a one-bit length of the multi-level input signal and outputs a first multi-level delayed signal; a second delay device that delays the multi-level input signal by a duration of the one-bit length of the multi-level input signal and outputs a second multi-level delayed signal; an adder that adds the second multi-level delayed signal with the multi-level input signal and outputs an added signal; an attenuator that attenuates the added signal and outputs a threshold signal; an exclusive or circuit, at which the multi-level input signal, the first multi-level delayed signal and the threshold signal are inputted, that calculates an exclusive or of (a) a two-level input signal which is at a logical zero when a level of the multi-level input signal is less than or equal to a level of the threshold signal and is at a logical one when the level of the multi-level input signal is higher than the level of the threshold signal and (b) a two-level delayed signal which is at a logical zero when a level of the first multi-level delayed signal is less than or equal to the level of the threshold signal and is at a logical one when the level of the first multi-level delayed signal is higher than the level of the threshold signal, and outputs a result of this calculation as an exclusive or signal; and a clock regeneration element that outputs the clock signal with a frequency corresponding to a bit rate of the exclusive or signal.