Patent ID: 8006039

Claim:
A system for merging data, comprising: an input/output device configured to send a request to merge a data, wherein a merge of the data comprises a manipulation of the data; and a shared cache subsystem in local communication with the input/output device and configured to receive and respond to the request to merge the data from the input/output device, wherein the shared cache subsystem comprises: an input/output data buffer in local communication with the input/output device and configured to store the data during an operation to merge the data; a local cache memory in communication with the input/output data buffer and configured to store the data before and after the operation to merge the data; a data manipulation station in communication with the input/output data buffer and the local cache memory and configured to merge the data; and a cache memory control in communication with the data manipulation station and the input/output device and configured to control an access of the data to the local cache memory, a remote cache memory, and a main memory before and after the operation to merge the data; wherein the shared cache subsystem is configured to merge the data without including a memory controller within a control flow or a data flow of the shared cache subsystem to merge the data, the control flow comprising: a plurality of input/output ports in local communication with the input output device and a plurality of other input/output devices and configured to input the request and other requests to the shared cache subsystem; a plurality of input/output group address register controllers in local communication with the input/output ports and configured to group and store request instructions; a first multiplexer in communication with the plurality of input/output group address register controllers; a pipeline circuitry in communication with the first multiplexer, wherein the pipeline circuitry comprises: a second multiplexer in communication with the first multiplexer and other request inputs; a first register in communication with the second multiplexer; a second register in communication with the first register; and a third register in communication with the second register; a local group address register controller in communication with the data manipulation station and with the pipeline circuitry, via the third register and the second multiplexer, and configured to control receiving and responding to the request; a local fetch address register controller in communication with the pipeline circuitry via the third register and configured to control fetching the data to the local cache memory from the remote cache memory or the main memory during the operation to merge the data; and a local store address register controller in communication with the pipeline circuitry via the third register and configured to control returning a merged data to the remote memory or the main memory during the operation to merge the data.