Patent ID: 7492182

Claim:
A non-volatile-memory-transistor based lookup table for an FPGA including: a multiplexer having 3 address inputs, 8 data inputs, and an output; a plurality of data-input circuits, each coupled to one of the data inputs of the multiplexer and including: a first non-volatile memory cell having an output coupled to the gate of a first n-channel MOS transistor, the first n-channel MOS transistor having a source coupled to the data input of the multiplexer and a drain coupled to a power supply potential; a second non-volatile memory cell having an output coupled to the gate of a second n-channel MOS transistor, the second n-channel MOS transistor having a source coupled to the data input of the multiplexer and a drain coupled to an input signal; a third non-volatile memory cell having an output coupled to the gate of a third n-channel MOS transistor, the third n-channel MOS transistor having a source coupled to the data input of the multiplexer and a drain coupled to the complement of the input signal; and a fourth non-volatile memory cell having an output coupled to the gate of a fourth n-channel MOS transistor, the fourth n-channel MOS transistor having a drain coupled to the data input of the multiplexer and a source coupled to ground; a sense amplifier is coupled to the output of the multiplexer and wherein the first, second, third, and fourth memory cells include: a non-volatile memory transistor having a source coupled to ground, a gate coupled to a first reference voltage, and a drain coupled to the memory cell output; and an n-channel transistor having a drain coupled to a voltage potential, a gate coupled to one of a second reference voltage and a pulse source, and a source coupled to the drain of the non-volatile memory transistor.