Patent ID: 8173990

Claim:
An integrated circuit structure comprising: a memory array comprising a plurality of memory cells arranged as rows and columns, wherein the memory array comprises: a transistor comprising a first, a second, and a third terminal, wherein the transistor is selected from the group consisting essentially of a MOS device and a bipolar junction transistor (BJT), and wherein the second terminal is a gate of the MOS device or a base of the BJT; a word-line of the memory array electrically connected to the second terminal; a first bit-line and a second bit-line; a contact plug connected to the first terminal; a metal line overlying and connected to the contact plug; a first resistive memory cell comprising: a first bottom electrode overlying and connected to the metal line; a first resistive element over the first bottom electrode; and a first top electrode overlying the first resistive element, wherein the first top electrode is electrically connected to the first bit-line; and a second resistive memory cell comprising: a second bottom electrode overlying and connected to the metal line; a second resistive element over the second bottom electrode; and a second top electrode overlying the second resistive element, wherein the second top electrode is electrically connected to the second bit-line.