Patent ID: 8433970

Claim:
An apparatus comprising: an iterative decoder including: a plurality of variable node processors each to receive a channel input and at least one of a plurality of check node values and to calculate a variable node value; a variable node memory including a plurality of nodes each associated with one of the variable node processors; a shuffle unit coupled to receive a variable node value from each of the plurality of variable node processors and to provide the variable node value to at least one of a plurality of check node processors coupled to the shuffle unit; the plurality of check node processors each to receive at least one variable node value and to calculate a check node value including a parity value and a magnitude value; a check node memory including a plurality of nodes each associated with one of the check node processors; and a controller coupled to the plurality of variable node processors, the variable node memory, the plurality of check node processors, the check node memory, and the shuffle unit to individually enable or disable each of the corresponding variable node processors, the variable node memory, the plurality of check node processors, and the check node memory during iterative decoding.