Patent ID: 7803676

Claim:
A method of fabricating a semiconductor device, which forms a DMOS transistor including a gate electrode, a drain electrode, a body electrode, and a source electrode on a substrate, the method comprising: providing the substrate including an active region, on which the DMOS transistor will be formed; forming a gate insulating layer pattern on a portion of the substrate, on which the gate electrode will be formed; forming a first polysilicon layer on an entire substrate including the gate insulating layer pattern; injecting a high concentration of first conductive type impurities as ions onto portions of the first polysilicon layer, on which the gate electrode and the body electrode will be formed; injecting a high concentration of second conductive type impurities onto a portion of the first polysilicon layer, on which the drain electrode will be formed; forming the body electrode and the gate electrode by patterning the first polysilicon layer; performing a first thermal treatment of the substrate so as to form a first conductive type first impurity region in the substrate under the body electrode, and a second conductive type first impurity region in the substrate under the drain electrode; sequentially injecting a low concentration of first conductive type impurities and a low concentration of second conductive type impurities as ions onto the body electrode, the gate electrode, and portions between the body electrode and the gate electrode; performing a second thermal treatment of the substrate so as to form a second conductive type second impurity region and a first conductive type second impurity region between the gate electrode and the body electrode in the active region; forming a second polysilicon layer on an entire substrate including structures formed on the substrate; forming the source electrode by by injecting a high concentration of second conductive type impurities onto a portion of the first polysilicon layer, on which the source electrode will be formed and by patterning the second polysilicon layer; and performing a third thermal treatment of the substrate so as to form a second conductive type source region.