Patent ID: 7384727

Claim:
A semiconductor processing patterning method, comprising: forming a first and second resist layers over a surface of a silicon-comprising substrate, the first layer being both beneath the second layer and having a thickness which is less than a thickness of the second resist layer; forming a mask pattern over the silicon-comprising substrate, the mask pattern comprising a plurality of pillars comprising the material of the first and second resist layers, wherein individual pillars of the pattern are comprised by: the material of the first resist layer defining opposing sidewalls in at least one cross section, the material of the first resist layer extending continuously between the opposing sidewalls of the individual pillar of the mask pattern; the material of the second resist layer defining opposing sidewalls in the one cross section, the material of the second resist layer extending continuously between the opposing sidewalls of the individual pillar of the mask pattern; and an entirety of the opposing sidewalls of the material of the first resist layer received laterally inward of an entirety of the opposing sidewalls of the material of the second resist layer in the one cross section; and etching material of the silicon-comprising substrate using the mask pattern as a mask.