Patent ID: 8089129

Claim:
Isolated CMOS transistors formed in a semiconductor substrate of a first conductivity type, the substrate not comprising an epitaxial layer, the isolated CMOS pair of transistors comprising: a floor isolation region of a second conductivity type opposite to the first conductivity type submerged in the substrate; and a first filled trench extending downward from a surface of the substrate into the floor isolation region, a floor of the first filled trench being located in the floor isolation region, walls of the first filled trench being lined with a dielectric material, the first filled trench further comprising a conductive material, the conductive material being laterally surrounded by the dielectric material and being in contact with the floor of the first filled trench such that the conductive material provides electrical contact from the floor isolation region to a surface of the substrate, wherein the floor isolation region and the first filled trench together enclose an isolated pocket of the substrate, the isolated pocket comprising an N-well and a P-well, the N-well comprising a P-channel MOSFET, the P-well comprising an N-channel MOSFET.