Patent ID: 8432186

Claim:
A programmable logic switch comprising: a first nonvolatile memory having: a first channel region provided between a first source and a first drain; a first insulating film formed on the first channel region; a first charge storage film formed on the first insulating film; a second insulating film formed on the first charge storage film; and a first gate electrode formed on the second insulating film; a second nonvolatile memory having: a second channel region provided between a second source and a second drain; a third insulating film formed on the second channel region; a second charge storage film formed on the third insulating film; a fourth insulating film formed on the second charge storage film; and a second gate electrode formed on the fourth insulating film; a first line connected to the first gate electrode and to the second gate electrode; a second line connected to the first source; a third line connected to the first drain and to the second drain; a fourth line connected to the second source; a substrate electrode through which a substrate voltage is applied to a well, the first nonvolatile memory and the second nonvolatile memory being formed in the well; one or more first logic transistors connected to the third line, each first logic transistor being connected to the third line at a gate electrode thereof; and a controller configured to connect, to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage to the first line, a second write voltage to the second line, and a third write voltage lower than the second write voltage to the fourth line, wherein no logic transistor other than the first logic transistors is connected to the third line.