Patent ID: 7629199

Claim:
A fabrication method of a semiconductor package with build-up layers formed on a chip, comprising the steps of: preparing a wafer comprising a plurality of chips, each of the chips having an active surface and a non-active surface and formed with a plurality of bond pads on the active surface; forming a conductive bump on each of the bond pads of the chips; singulating the wafer to form a plurality of single chips each having a plurality of the conductive bumps thereon; providing a carrier having a cavity for receiving at least one of the chips therein, wherein the non-active surface of the chip is attached to a bottom surface of the cavity, and the conductive bumps are positioned within the cavity and partly protruded from the cavity; applying a first dielectric layer over the active surface of the chip and the carrier, wherein the first dielectric layer fills in the cavity and encapsulates the conductive bumps with ends of the conductive bumps being exposed without forming vias through the first dielectric layer; and forming a plurality of first conductive traces on the first dielectric layer, and allowing the first conductive traces to be electrically connected to the exposed ends of the conductive bumps.