Patent ID: 7939420

Claim:
A process for forming an isolation structure for an integrated circuit device comprising: providing a semiconductor substrate of a first conductivity type, the substrate not containing an epitaxial layer; forming a first mask layer above a top surface of the substrate; patterning the first mask layer to form a first opening in the first mask layer; implanting a dopant of a second conductivity type through the opening in the first mask layer and the top surface of the substrate so as to form a floor isolation region, the floor isolation region having an upper boundary below the top surface of the substrate immediately following said implanting; forming a second mask layer above the top surface of the substrate within the opening in the first mask layer, an edge of the second mask layer being separated from an edge of the first opening in the first mask layer to create a gap; etching the substrate through the gap to form a trench, the trench extending downward at least to the floor isolation region; and filling the trench so as to form an isolated pocket of the substrate.