Patent ID: 6950446

Claim:
An apparatus comprising: a memory unit to store a set of per-alignment state machines; a memory controller coupled to the memory unit, the memory controller to access the set of per-alignment state machines; a first deframing slice coupled to the memory controller, the first deframing slice having a first set of buffers coupled to the memory controller, the first set of buffers to store a first set of states from a first subset of the set of per-alignment state machines, a first set of logic coupled to the first set of buffers, the first set of logic to sync hunt a first signal with the first set of states and to update the first set of states, a second set of buffers coupled to the first set of logic, the second set of buffers to store the updated first set of states, the updated first set of states to be written to the first subset of the set of per-alignment state machines; and a second deframing slice coupled to the memory controller, the second deframing slice having a third set of buffers coupled to the memory controller, the third set of buffers to store a second set of states from a second subset of the set of per-alignment state machines, a second set of logic coupled to the third set of buffers, the second set of logic to sync hunt a second signal with the second set of states and to update the second set of states, a fourth set of buffers coupled to the second set of logic, the fourth set of buffers to store the updated second set of states, the updated second set of states to be written to the second subset of the set of per-alignment state machines.