Patent ID: 8854878

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array connected to word lines and bit lines, and including memory cells each of which is capable of storing n values (n is a natural number of 3 or more); and a controller configured to control voltages at a word line and a bit line according to write data, and to perform a write operation to write data to the memory cell and a verify operation to verify a threshold voltage of the memory cell, wherein the controller is configured to perform a verify operation using a first verification voltage and a second verification voltage (first verification voltage<second verification voltage) when first value data is stored in a first memory cell, the controller is configured to determine whether a write operation to the first memory cell is completed or continued based on write data of a second memory cell adjacent to the first memory cell when a threshold voltage of the first memory cell is greater than or equal to the first verification voltage and less than the second verification voltage, the controller is configured to complete the write operation to the first memory cell when the threshold voltage of the first memory cell is greater than or equal to the first verification voltage and less than the second verification voltage, and when second value data is stored in the second memory cell, and a threshold voltage of the second value data is greater than that of the first value data.