Patent ID: 8575988

Claim:
An integration circuit comprising: a resistive element configured to receive an input voltage signal; an amplifier coupled to an output of the resistive element; an integrating feedback capacitor coupled to an input of the amplifier and to an output of the amplifier; a voltage adjustment circuit coupled to the input of the amplifier, wherein the voltage adjustment circuit is configured to adjust an output voltage at the output of the amplifier by a voltage adjustment if the output voltage reaches one or more defined limits; a logic circuit coupled to the voltage adjustment circuit, wherein the logic circuit is configured to control the voltage adjustment circuit and to count a number of times the voltage adjustment is performed by the voltage adjustment circuit during an integration time period, wherein each voltage adjustment of the output voltage comprises a fixed adjustment voltage Vj; and a multiplication circuit coupled to the logic circuit, wherein the multiplication circuit receives a first input comprising a count of the number of times the voltage adjustment is performed by the voltage adjustment circuit during the integration time period and a second input comprising a digital representation of the adjustment voltage Vj, and the multiplication circuit outputs a product of the first and second inputs.