Patent ID: 7247535

Claim:
A method for making a transistor within a semiconductor wafer, comprising: forming a gate stack, said gate stack having a gate silicon oxide layer coupled to said semiconductor wafer and a gate polysilicon layer coupled to said gate silicon oxide layer; forming source/drain extension sidewall spacers coupled to said gate stack; forming deep source/drain sidewall spacers coupled to said source/drain extension sidewall spacers; implanting dopants into said semiconductor wafer at deep source/drain locations; removing said deep source/drain sidewall spacers; reshaping said source/drain extension sidewall spacers; etching a recess in a surface of said semiconductor wafer at source/drain extension locations; depositing SiGe within each said recess to form SiGe source/drain extensions; implanting dopants into said SiGe source/drain extensions; and performing a first post extension implant anneal of said semiconductor wafer.