Patent ID: 8595410

Claim:
A memory system comprising: a board; a package for a memory chip mounted on the board; a first nonvolatile memory chip in the package; a second nonvolatile memory chip in the package; a first signal wiring in the package electrically connected to the first nonvolatile memory chip; a second signal wiring in the package electrically connected to the second nonvolatile memory chip; an interface configured to communicate with a host; a first controller configured to control power supply to the memory system which includes the first nonvolatile memory chip and the second nonvolatile memory chip; and a second controller configured to control a load capacity of the first nonvolatile memory chip and the second nonvolatile memory chip according to a command from the host by switching a connection of the first signal wiring and the second signal wiring, wherein the second controller controls the load capacity of the first nonvolatile memory chip to be increased and the load capacity of the second nonvolatile memory chip to be reduced, when the first nonvolatile memory chip is accessed, and when the power of the first nonvolatile memory chip and the second nonvolatile memory chip is on, the second controller controls the load capacity of the first nonvolatile memory chip to be reduced and the load of the second nonvolatile memory chip to be increased, when the second nonvolatile memory chip is accessed when the power of the first nonvolatile memory chip and the second nonvolatile memory chip is on.