Patent ID: 7479673

Claim:
An integrated circuit comprising: a first transistor having first and second impurity regions formed at a semiconductor substrate; a first interlayer insulating layer on the first transistor; a second transistor having first and second impurity regions on the first interlayer insulating layer opposite the first transistor; a second interlayer insulating layer on the second transistor opposite the first interlayer insulating layer; a third transistor having first and second impurity regions on the second interlayer insulating layer opposite the second transistor; a third interlayer insulating layer on the third transistor opposite the second interlayer insulating layer; and a node plug penetrating the first, second and third interlayer insulating layers to electrically connect the first impurity region of the first transistor, the first impurity region of the second transistor and the first impurity region of third transistor to one another.