Patent ID: 8862851

Claim:
A non-volatile memory (NVM) package, comprising: an interface configured to receive a block address and a first chip enable signal from a host processor coupled to the interface; a plurality of concurrently addressable memory units each containing a plurality of blocks; and a processor configured to: activate, in response to the first chip enable signal from the host processor, a first concurrently addressable memory unit using a first internal chip select enable signal; activate a second concurrently addressable memory unit using a second internal chip select enable signal; map the block address to blocks in the activated first and second concurrently addressable memory units; execute a sequence of commands for concurrently performing read or write operations on the blocks in the activated first and second currently addressable memory units; receive a command from the interface for an operation, wherein the operation includes a sequence of commands that perform atomic transactions on one or more of the concurrently addressable memory units; and wherein a quantity of data that is read from or written to one of the one or more concurrently addressable memory units is equal to a product of N, a stride parameter for the concurrently addressable memory unit and a number of bytes equivalent to a page size plus a number of bytes associated with page allowing for metadata, where N is a positive integer representing a number of pages to be read or written, and stride is a number of blocks for operation commands within the concurrently addressable memory unit.