Patent ID: 7601594

Claim:
A method for fabricating a semiconductor memory having a semiconductor substrate having a concave portion and a convex portion, an element isolation region, a gate electrode and a charge storing layer, the method comprising: (a) forming the element isolation region in the concave portion of the semiconductor substrate; (b) forming a layer made of a gate electrode material so as to cover the concave portion of the semiconductor substrate and the element isolation region; (c) forming the gate electrode by forming a mask on a surface of the layer made of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer made of the gate electrode material; (d) forming the charge storing layer at on least one of side surfaces of the gate electrode in contact with the convex portion of the semiconductor substrate; and (e) forming a sidewall on at least a part of the charge storing layer.