Patent ID: 8395240

Claim:
A method for manufacturing a semiconductor device comprising: providing a semiconductor substrate; forming a plurality of gate structures formed on a portion of the semiconductor substrate; forming an interlayer dielectric layer overlying the gate structures, the interlayer dielectric layer having a substantially flat surface region; forming a first copper interconnect layer overlying the substantially flat surface region of the interlayer dielectric layer; forming an additional dielectric layer overlying the first copper interconnect layer; forming a second copper interconnect layer overlying the dielectric layer; providing a copper ring structure enclosing an entirety of an inner region of the dielectric layer, the copper ring structure being provided between the first copper interconnect layer and the second copper interconnect layer to maintain the inner region of the additional dielectric layer dielectric layer; and forming a bonding pad structure overlying a region within the inner region, the bonding pad structure having a patterned bottom portion including multiple regions in contact with the second copper interconnect layer.