Patent ID: 7039887

Claim:
A method for verifying an electronic design, comprising: determining clock domains of the electronic design; coloring each of a plurality of netlists of the electronic design based on the clock domain determination, with a color indicating a clock domain associated with each netlist, wherein the netlist coloring comprises coloring a clocked flip-flop instance including: if an asynchronous reset port does not exist, coloring output ports with the clock color of the flip-flop instance; if an asynchronous reset port exists, and the clock and reset ports have the same color, coloring output ports with the clock color of the flip-flop instance; and if an asynchronous reset port exists, and the clock and reset ports do not have the same color, coloring output ports with an initial color; assigning one of a plurality of simulation timing modes to each of a plurality of instances of the electronic design based on the netlist coloring; and simulating each of the plurality of instances of the electronic design in the respective assigned simulation timing mode.