Patent ID: 7994069

Claim:
A method of fabricating an integrated circuit device on a semiconductor wafer, comprising: forming on the wafer a dielectric layer having a first value of dielectric constant; forming a metal line in a trench region formed within the dielectric layer; capping the metal line; producing first and second regions in said dielectric layer after capping the metal line by masking an area of the dielectric layer corresponding to said first region with a hard mask pattern and applying radiation to said area of the dielectric layer corresponding to said second region, to cause the dielectric constant of the dielectric material layer to reduce, wherein the hard mask pattern is substantially opaque to the radiation; and wherein the first region retaining said first value of dielectric constant, the second region including the trench region and having a second value of dielectric constant, said second value being lower than said first value and lower than 3.0, wherein the mechanical strength of said first region is greater than the mechanical strength of the second region, and wherein said producing comprises treating an area of the dielectric layer corresponding to said second region to lower the dielectric constant thereof to said second value.