Patent ID: 7890673

Claim:
An information-handling system, comprising: a plurality of processing elements; and a memory having a first memory section, wherein the first memory section is operatively coupled to each processing element, and wherein the first memory section comprises: a memory array having processor-addressable and non processor-addressable memory; a memory interface operatively connecting the memory array to each of the processing elements; and a block transfer engine operatively coupled to between the memory interface and the memory array, wherein the block transfer engine operates to receive a block transfer command from one of the processing elements and to transfer data from a first memory location in the non processor-addressable memory of the memory array to a second memory location in the processor-addressable memory of that memory array, wherein the first memory location can be accessed only indirectly by one or more of the plurality of processing elements via the block transfer engine and wherein the second memory location can be accessed directly by one or more of the plurality of processing elements using a processor address generated by a corresponding processing element; wherein the memory interface includes one or more FIFOs, wherein the one or more FIFOs accept block transfer commands from one or more of the processing elements and transmit transmits the block transfer commands to the block transfer engine.