Patent ID: 7502216

Claim:
A multilayer chip capacitor comprising: a capacitor body formed by laminating a plurality of dielectric layers; a plurality of internal electrodes disposed in the capacitor body, each of the internal electrodes having one or more lead drawn to a side surface of the capacitor body, the internal electrodes of opposite polarities alternately disposed to face each other with the dielectric layer interposed therebetween; a plurality of external electrodes disposed on first and second side surfaces facing each other of the capacitor body to extend in a lamination direction and to be electrically connected to the internal electrodes through the leads, the external electrodes of opposite polarities alternately disposed on each of the first and second side surfaces; wherein the internal electrodes constitute a plurality of blocks stacked repeatedly one atop another, each of the blocks including a plurality of the internal electrodes which are arranged successively in the lamination direction, wherein an average number of leads in each internal electrode is smaller than half of the total number of the external electrodes, and wherein the leads of the internal electrodes having opposite polarities and adjacent in the lamination direction are disposed to be adjacent to each other as seen from the lamination direction, and wherein all the internal electrodes having the same polarity are electrically connected to each other by the external electrodes.