Patent ID: 8030968

Claim:
An apparatus comprising: a first circuit cell having a first transistor coupled in series to a second transistor to receive a least significant bit of a input signal; and a second circuit cell having a third transistor coupled in series to a fourth transistor to receive a bit of the input signal that is next order higher than the least significant bit, wherein: the first and third transistors are transistors of a first type, and the second and fourth transistors are transistors of a second type that is different from the first type, the third transistor is structurally larger than the first transistor by a first coefficient, wherein the first coefficient is a ratio between a geometric size of the third transistor and a geometric size of the first transistor, the fourth transistor is structurally larger than the second transistor by a second coefficient, wherein the second coefficient is a ratio between a geometric size of the fourth transistor and a geometric size of the second transistor, and the second coefficient is different from the first coefficient.