Patent ID: 7512731

Claim:
A computer system comprising a mother board, the mother board comprising: at least one first processor socket and at least one second processor socket, each mounted on the mother board; at least one memory; at least one processor bus, electrically connecting the first processor socket and the second processor socket; at least one memory bus, electrically connecting the second processor socket and the memory; at least one processor configured in the first processor socket, electrically connected to the processor bus through the first processor socket; and at least one memory bridge configured in the second processor socket, electrically connected to both the processor bus and the memory bus through the second processor socket, the memory bridge comprising: a plurality of first electrical contacts for configuring into the second processor socket to electrically connect the processor bus; a plurality of second electrical contacts for configuring into the second processor socket to electrically connect the memory bus; a memory controller in circuit connection with the second electrical contacts; and a control unit in circuit connection with the first electrical contacts and the memory controller, thereby controlling signal/data transmission between the first electrical contacts and the memory controller, the control unit further comprising: a phase locked loop, configured to generate a core clock to limit all electrical components of the memory bridge to a specific operating frequency range; and a reset logic to reset and initialize the memory bridge; wherein the processor accesses the memory through the processor bus, the memory bridge and the memory bus.