Patent ID: 7725754

Claim:
An integrated circuit, comprising: interface circuitry for controlled passing of information to and from the integrated circuit; the interface circuitry having: a hardwired block for receiving a user clock signal and a core clock signal; the hardwired block having a clock divider circuit coupled to receive the user clock signal and the core clock signal; the clock divider circuit configured to divide the core clock signal responsive to a frequency of the user clock signal to provide a divided clock signal; the clock divider circuit further configured to provide the divided clock signal with edges aligned to the core clock signal; the divided clock signal having the frequency of the user clock signal but the divided clock signal having pulses of a pulse width equal to a pulse width of pulses of the core clock signal; the pulses of the divided clock signal having the edges aligned to the pulses of the core clock signal with a phase relationship of the user clock signal; wherein edges of a single pulse of the divided clock signal are aligned to edges of a single pulse of the core clock signal; a user-side resource coupled to receive the divided clock signal for the controlled passing of information responsive to the divided clock signal; and a core-side resource coupled to receive the core clock signal for the controlled passing of information responsive to the core clock signal.