Patent ID: 7625795

Claim:
A method of forming a memory cell comprising: forming a bottom electrode of a capacitor having a container shape with exterior and interior surfaces in a supporting dielectric insulation region, the dielectric insulation region abutting a portion of the exterior surface of the bottom electrode; forming a substantially vertically extending bit line contact site extending from a vertical height above the bottom electrode to a source/drain region of an access transistor, the dielectric insulation abutting an entire vertical exterior surface portion of the bottom electrode adjacent the bit line contact site; forming recesses in the supporting dielectric to expose surface portions of the exterior of the container at a level below the top of the container exterior, wherein forming recesses further comprises depositing an etch mask between the surface portions of the exterior; and removing the supporting dielectric not masked by the etch mask; forming a dielectric layer over the interior surface and the exterior surface not abutting the insulation region; and forming a top plate over the dielectric layer.