Patent ID: 8418116

Claim:
A computer-implemented method for optimizing a circuit design, the method comprising: selecting an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate under a focus multi-mode multi-corner (MCMM) scenario in a set of MCMM scenarios; determining, by computer, whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate under each MCMM scenario in the set of MCMM scenarios, wherein the zone around the logic gate includes the local context of the logic gate and at least one additional logic gate; in response to determining that applying the optimizing transformation to the logic gate degrades the timing metric in the zone under at least one MCMM scenario, rejecting the optimizing transformation; and in response to determining that applying the optimizing transformation to the logic gate does not degrade the timing metric in the zone under any MCMM scenario in the set of MCMM scenarios, determining whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design under each MCMM scenario in the set of MCMM scenarios, and accepting the optimizing transformation if the logic gate does not degrade the timing metric in the circuit design under any MCMM scenario in the set of MCMM scenarios.