Patent ID: 7952132

Claim:
A semiconductor memory device comprising: a source region and a drain region formed separated from each other in a surface of a semiconductor substrate; a channel region formed in the semiconductor substrate and located between the source region and the drain region; a charge storage layer formed on the channel region with a first insulating film interposed therebetween; and a control gate electrode formed on the charge storage layer with a second insulating film interposed therebetween, and having a convex shape at its upper surface, the control gate electrode including an upper area having a first width, and a lower area having a second width wider than the first width, and having a gentler gradient as compared with a gradient of a side face of the upper and lower areas, the gentler gradient being located in part of the upper area which is continuous with the lower area, and having a width that increases from the first width of the upper area to the second width of the lower area, and a corner portion of the convex shape of a control gate having a rounded shape.