Patent ID: 8611484

Claim:
A receiver comprising a clock recovery unit configured to recover and output a clock signal, and a serial-to-parallel converter configured to recover and output a data signal, wherein the clock recovery unit is configured to: receive a clock embedded data signal in which only the clock signal is included during a clock training interval and the clock periodically embedded between the data signals after the clock training interval; generate a first master clock signal from the clock embedded data signal during the clock training interval; generate a second master clock signal from the clock embedded data signal after the clock training interval; after the training interval, generate the second master clock signal by a first delay clock signal that delays the first master clock signal so as to have a phase difference and then generates the second master clock signal by a second delay clock signal that delays the second master clock signal so as to have a phase difference; and provide a recovery clock signal from the second delay clock signals, and wherein the clock recovery unit is configured based on a delay locked loop.