Patent ID: 7219178

Claim:
Bus logic operable to couple a plurality of master logic units with a plurality of slave logic units to enable data transfers to occur, each master logic unit being operable to perform an address transfer over an address channel which, when received by a specified one of said plurality of slave logic units, causes an associated data transfer to be performed over a data channel between that master logic unit and said specified one of said plurality of slave logic units, each of said plurality of slave logic units being required to complete a data transfer, once initiated, prior to performing any further data transfers, at least one of said plurality of slave logic units being operable to perform data transfers in an order which differs from that in which associated address transfers were received by that slave logic unit, said bus logic comprising: interconnect logic configurable, responsive to an address transfer, to couple a master logic unit with a slave logic unit to enable a data transfer to take place; and deadlock prediction logic operable to receive information indicative of each address transfer and to determine, based on an ability of said at least one of said plurality of slave logic units to perform data transfers in an order which differs for associated address transfers, whether propagation of that address transfer may cause said interconnect logic to be configured such that a deadlock situation can occur in which data transfers are unable to take place between affected master logic units and slave logic units and, if so, to prevent the propagation of that address transfer.