Patent ID: 6874097

Claim:
An apparatus for detecting and correcting the timing skew of a data signal in a parallel data transmission system, comprising: a data path for adjusting the timing skew of the data signal with respect to a clock signal, said data path including: a delay digital-to-analog converter (DAC), a falling edge DAC, at least two receive registers, an output multiplexer, and control logic; a clock path for correcting the duty-cycle of a receive clock and for delaying said receive clock in normal receive operations, wherein said clock path is selectably switchable between a timing skew correction mode and a receive-data mode; a local accurate tuning system for generating a timing signal to tune all of the delay elements of said parallel data transmission system according to a bit-cell time of the data signal; wherein said control logic detects the timing skew of the data signal and controls said delay DAC and said falling edge DAC to provide appropriate delay to the data signal in accordance with the detected timing skew of said data signal.