Patent ID: 8677103

Claim:
An apparatus comprising: an asynchronous pipelined data path including: a plurality of adjacent stages having a stage that includes: a data store to store data, a valid indicator to indicate whether the data in the data store is valid or invalid, and a transfer controller to control the transfer of data into and out of the data store without sending or receiving an acknowledgement for the data transfer to or from an adjacent stage, respectively, after the transfer of the data and before processing of the data is complete, the transfer controller including a state machine having a plurality of states and operative to: control the stage to load data from a previous stage into the data store in response to a first state transition indicating data in the previous stage has been processed and a signal indicating the data in the previous stage is valid, and control the stage to transfer data in the data store to the next stage in response to a second state transition indicating data in the stage and data in the next stage have been processed and a signal indicating that data in a stage downstream from the next stage is invalid and data in all stages between the stage and the downstream stage are valid, wherein the signal indicates that the data in all stages between the stage and the downstream stage are valid when the data in all stages between the stage and the downstream stage have been processed and have not been transferred to a next stage; and control logic to: receive status signals from each of the plurality of stages, wherein the status signals for each of the stages include a valid indicator and a signal indicating whether data in the respective stage has been processed, identify, based on the received status signals, the stage downstream from the next stage that is invalid, determine, based on the received status signals, that the data in all the stages between the stage and the downstream stage are valid, and send control signals to the transfer controller, wherein the control signals include the signal indicating that the data in the stage downstream from the next stage is invalid and the data in all the stages between the stage and the downstream stage are valid, wherein the stage is configured to send a status indicator different from the valid indicator to the state machine to indicate whether new data will be processed by the stage in a next cycle, and whether data will be transferred in the next cycle between the stage and the adjacent stage.