Patent ID: 8208324

Claim:
A semiconductor memory device comprising: a plurality of memory cells; true and complementary main I/O lines; a read/write bus; a main amplifier comprising a read amplifier that includes first and second input nodes respectively coupled to the true and complementary main I/O lines and a first output node coupled to the read/write bus, and a write amplifier that includes a third input node coupled to the read/write bus and second and third output nodes coupled respectively to the true and complementary main I/O lines, the read amplifier being activated, in a data read mode, to respond to a potential difference between the true and complementary main I/O lines and drive the read/write bus, and the write amplifier being activated, in a data write mode, to respond to a data signal on the read/write bus and drive the true and complementary main I/O lines; a relief storage cell; and a control circuit configured to electrically connect the true and complementary main I/O lines to one of the memory cells with an intervention of a sense amplifier when an access address is inconsistent with a defective address and to the relief storage cell without an intervention of a sense amplifier when the access address is coincident with the defective address, so that, in the data read mode, the read amplifier drives the read/write bus in response to the potential difference between the true and complementary main I/O lines caused by data stored in the one of the memory cells when the access address is inconsistent with the defective address and by data stored in the relief storage cell when the access address is coincident with the defective address, and in the data write mode, data on the read/write bus is written, by the write amplifier driving the true and complementary main I/O lines, into the one of the memory cells when the access address is inconsistent with the defective address and into the relief storage cell when the access address is coincident with the defective address.