Patent ID: 7515472

Claim:
A page buffer circuit of a flash memory device, comprising: a main register to store first or second input data according to an input control signal, the main register being coupled to a sensing node coupled to a bit line selection circuit to store first sensing data of the sensing node according to a first latch control signal; a program transmission circuit provided between the main register and the sensing node, the program transmission circuit configured to receive the first sensing data, the first input data, or the second input data at a given time and to output one of the data received from the main register to the sensing node in response to a program control signal; a temporary register coupled to the sensing node, wherein the temporary register is configured to store second sensing data in response to a second latch control signal; and a verification transmission circuit to transmit the second sensing data to the main register through the sensing node in response to a transmission control signal during a program verification operation, wherein during a program operation, the program transmission circuit outputs one selected from the first sensing data, the first input data, and the second input data to the sensing node as program data in response to the program control signal, wherein the temporary register senses a voltage of the sensing node during the program operation, the voltage corresponding to a logic value of the program data, and wherein the temporary register stores the second sensing data according to the voltage of the sensing node in response to the second latch control signal, and wherein a logic value of the second sensing data is the same as a logic value of the program data.