Patent ID: 8748248

Claim:
A method for forming a semiconductor device comprising contact holes, comprising: forming a dual-stress liner over a substrate, wherein the dual-stress liner comprises a first stress liner and a second stress liner having opposite stress types and partially overlapped to form an overlapping portion, the overlapping portion comprising an upper stress liner formed by a portion of one of the first and second stress liners and a lower stress liner formed by a portion of an other of the first and second stress liners; forming a first dielectric layer over the dual-stress liner, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer, wherein the second dielectric layer has a top surface leveling with a top surface of the overlapping portion; etching the third dielectric layer with an etching selectivity over the second dielectric layer and over the upper stress liner to form a plurality of first openings through the third dielectric layer to expose the second dielectric layer and an upper stress liner in the overlapping portion; forming a plurality of second openings through the second and first dielectric layers to expose each of the lower stress liner in the overlapping portion, the first stress liner, and the second stress liner such that an exposed portion of the each of the lower stress liner, the first stress liner, and the second stress liner at least have a same thickness; and removing the exposed portion of each of the first stress liner, the second stress liner, and the lower stress liner along the plurality of second openings to form a plurality of contact holes.