Patent ID: 8921924

Claim:
A semiconductor memory device comprising: a semiconductor substrate including a first region, a second region, a third region, and a fourth region, the second region being provided between the first region and the third region, the third region being provided between the second region and the fourth region, and the fourth region including a first portion and a second portion; a cell transistor provided on the first region and including a first insulating film having a first film thickness, a charge storage film provided on the first insulating film, and a first electrode provided on the charge storage film; an extraction section provided on the second region and including a second insulating film having a second film thickness thicker than the first film thickness, and an extension electrode provided on the second insulating film, being continuous with the first electrode, and extending from above the first region to above the second region; a guard ring provided on the third region and including a third insulating film having a third film thickness thicker than the first film thickness; a first transistor provided on the first portion and including a fourth insulating film having a fourth film thickness thicker than the first film thickness, and a second electrode provided on the fourth insulating film; a second transistor provided on the second portion and including a fifth insulating film having a fifth film thickness thinner than the fourth film thickness, and a third electrode provided on the fifth insulating film; a first device isolation section provided in the first region; a second device isolation section provided between the first region and the second region; a third device isolation section provided between the second region and the third region; and a fourth device isolation section provided between the third region and the fourth region, wherein the first device isolation section has a first depth when a surface of the semiconductor substrate in the first region is used as a reference position, the second device isolation section has a second depth deeper than the first depth as viewed from the reference position, the third device isolation section has a third depth deeper than the second depth as viewed from the reference position, and the fourth device isolation section has a fourth depth deeper than the second depth as viewed from the reference position.