Patent ID: 8389334

Claim:
A method for packaging integrated circuits, comprising: laminating a metallic foil, a metal carrier and a photoresist layer sandwiched therebetween, the photoresist layer acting as an intermediate adhesion layer that bonds the carrier to the metallic foil, wherein the metal carrier has a plurality of openings to provide access to the underlying photoresist layer; exposing and patterning the photoresist layer, wherein developing of the photoresist layer is performed after a die attach, a wire bond and an encapsulation operation; drilling a plurality of alignment features through the metallic foil and the photoresist layer; attaching a plurality of integrated circuit die to the metallic foil using the alignment features for alignment; wirebonding the plurality of integrated circuit die directly to the metallic foil with no intermediate adhesion layer; encapsulating the integrated circuit die, bonding wires and portions of the foil in a molding material; removing portions of the exposed photoresist layer using a developer solution to expose portions of the underlying metallic foil; etching the exposed portions of the metallic foil through the plurality of openings in the metal carrier to define a plurality of device areas in the metallic foil; removing the photoresist layer, wherein removal of the photoresist layer causes the metal carrier to detach from the etched metallic foil to form a molded foil structure; electroplating the exposed portions of the metallic foil to plate the exposed portions of the metallic foil with a solder layer; and singulating the molded foil structure using either sawing or laser cutting.