Patent ID: 7068083

Claim:
An output buffer comprising: an output terminal; a pull up module for pulling up an output terminal to a first source voltage when the pull up module is active; a pull down module for pulling down the output terminal to a second source voltage that is lower than the first source voltage when the pull down module is turned on; and an output latching module, (i) the output latching module maintaining the pull up module and the pull down module in an inactive state to maintain the output terminal in a high impedance state when the output buffer is in a stand-by mode, (ii) the output latching module latching a data signal in response to a level of an output clock signal, and the output latching module driving the pull up module and the pull down module with the latched data signal, and the pull up module and the pull down module operating to output the data signal at the output terminal in response to the latched data signal when the output buffer is in a first operation mode, (iii) the output latching module latching the data signal in response to an edge of the output clock signal, and the output latching module driving the pull up module and the pull down module with the latched data signal, the pull up module and the pull down module operating to output the data signal in response to the latched data signal when the output buffer is in a second operation mode, wherein the output terminal in the first operation mode and the output terminal in the second operation mode are the same output terminal.