Patent ID: 7718506

Claim:
A method for forming an isolation structure for a MOS transistor, comprising the following steps: forming a sacrificed oxide layer over a semiconductor substrate; forming a first photoresist layer over the sacrificed oxide layer, and patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region on the semiconductor substrate; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, and patterning the second photoresist layer to define an NMOS active region and an NMOS isolation region on the semiconductor substrate; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively.