Patent ID: 7689956

Claim:
An evaluation method for calculating a yield of LSIs including sets including delay element sets, wherein within the delay element sets sequential circuits are connected through delay elements including gates, and nets, the method comprising: calculating, with a computer, a first predicted distribution of a yield of an LSI by using all the delay element sets; extracting, with the computer, from the plurality of the delay element sets an independent delay element set that is a subset of the delay element sets that do not have a gate or net in common with another delay element set, the extracting includes extracting using a net list which is supplied before start of the evaluation method; calculating, with the computer, a second predicted distribution of a yield by using only the independent delay element set; outputting the first predicted distribution and the second predicted distribution; and deriving an actual yield of the LSI is from a difference between the predicted distribution of a yield obtained by using all the delay element sets and the predicted distribution of a yield obtained by using only the independent delay element set.