Patent ID: 7038692

Claim:
A graphics system, comprising: an input/output (I/O) bus; a central processing unit (CPU) having an associated system memory, said CPU and said associated system memory coupled to said I/O bus, said CPU adapted to issue commands for rendering polygons of a graphical image, said CPU having to acquire access to said I/O bus in order to transfer vertex data across said I/O bus; a graphics accelerator coupled to said I/O bus, said graphics accelerator comprising: a cache for storing vertex data; a cache controller configured to receive a command to render a polygon from said CPU, said cache controller checking said cache for previously cached vertex data for vertices of said polygon; and said graphics accelerator configured to utilize said vertex data to render pixel data for said polygon; wherein said graphics accelerator caches vertex data received from said I/O bus to reduce the number of data transfers of vertex data across said I/O bus required to render polygons in response to said commands issued from said CPU.