Patent ID: 7544570

Claim:
A production method for manufacturing a vertical-type metal insulator field effect transistor device, comprising: preparing a first conductivity type drain region layer; forming a plurality of trenches at a given pitch in the first conductivity type drain region layer; stuffing said trenches with an insulating material to thereby producing buried-insulator regions; forming a gate insulating layer on said first conductivity type drain region; implanting second conductivity type impurities in said first conductivity type drain region layer to thereby produce a plurality of second conductivity type base regions in said first conductivity type drain region layer such that each of the second conductivity type base regions is positioned between two adjacent buried-insulator regions; forming a gate electrode layer on said gate insulating layer; patterning said gate electrode layer such that a portion of said gate electrode layer is defined as a span portion which bridges a space between two adjacent second conductivity type base regions; implanting first conductivity type impurities in said second conductivity type base regions to thereby produce a first conductivity type source region in each of said second conductivity type base regions; and patterning said gate insulating layer such that a portion of said gate insulating layer is defined as a span portion which bridges a space between two adjacent second conductivity type base regions.