Patent ID: 8116146

Claim:
A semiconductor device, comprising: an overdriving control circuit configured to generate a first drive signal and a second drive signal in response to an internal signal; an equalizing signal generating unit configured to generate an equalizing signal having an overdriving voltage higher than a normal drive voltage during a first duration of an activation period of the internal signal and having the normal drive voltage during a second duration of the activation period after the first duration in response to the first drive signal and the second drive signal; and an equalizing unit configured to equalize first and second lines in response to the equalizing signal, wherein the equalizing signal generating unit includes: a first drive unit configured to output the overdriving voltage to a second node in response to the first drive signal; and a second drive unit configured to output the normal drive voltage to a first node in response to the second drive signal, wherein the second drive unit includes: a first transistor configured to form a current path between a terminal supplying the normal drive voltage and the first node in response to the second drive signal; and a second transistor configured to form a current path between the first node and a ground voltage terminal in response to the second drive signal.