Patent ID: 7325124

Claim:
A pipeline, comprising: a plurality of operational stages, the stages including: a pointer register stage which stores pointer information and updates in a pointer register file; a pointer dependency checking stage located upstream of the pointer register stage, which determines if instruction pointer dependencies exist and stalls an instruction if necessary to resolve inter-instruction dependencies in the pointer register stage; a dependence checking stage located downstream of the pointer register file and configured to perform checking on instructions and stalling an instruction if necessary to resolve inter-instruction dependencies in an instruction register file; an issue stage located downstream from the dependence checking stage; the instruction register file configured to store instruction information and updates: at least one pointer functional unit providing pointer information updates directly to the pointer register stage and/or directly to an input of the at least one pointer functional unit as a pointer bypass such that the pointer information is processed and updated; and at least one instruction functional unit providing information updates directly to the instruction register stage and/or directly to an input of the at least one instruction functional unit as an instruction bypass such that instruction update information is processed and updated and wherein instructions updating the instruction register file and instructions updating the pointer register file are simultaneously processed to track and keep current pointer and dependency updates between instructions.