Patent ID: 6864564

Claim:
A semiconductor package, comprising: a lead frame having a first side and a second side, and formed with a die pad and a plurality of leads surrounding the die pad, wherein the leads are each defined into an inner lead, an outer lead and a middle portion positioned between the inner lead and the outer lead, and each of the middle portions extends outwardly at sides thereof to form protrusions for reducing spacing between the adjacent middle portions of the leads, wherein the middle portions of the leads are arranged in a manner that spacing between adjacent middle portions is 0.10 mm, or equal to or smaller than 0.15 mm; an encapsulant for encapsulating the middle portions of the leads and the second side of the lead frame with the outer leads being exposed, wherein a cavity is formed in the encapsulant for exposing the die pad and the inner leads on the first side of the lead frame, allowing a semiconductor chip and bonding wires to be received in the cavity; the semiconductor chip mounted in the cavity on the die pad of the first side of the lead frame; the plurality of bonding wires formed in the cavity for electrically connecting the semiconductor chip to the inner leads of the lead frame; and a lid adhered onto the encapsulant for covering an opening of the cavity.