Patent ID: 8510521

Claim:
A memory controller comprising: an agent interface unit coupled to a plurality of ports of the memory controller, wherein the agent interface unit is configured to receive memory operations and corresponding quality of service (QoS) parameters on each port; and a plurality of memory channel units coupled to the agent interface unit, wherein the memory channel units each comprise a presorting queue and a memory interface unit to couple to a memory; wherein the agent interface is configured to schedule memory operations from the ports to a given memory channel unit responsive to the QoS parameters of the memory operations, and wherein the agent interface unit is configured to reorder memory operations to a given memory channel unit based on the QoS parameters; wherein the memory channel units are configured to group memory operations in the presorting queue according to an effect that performing the memory operations together will have on memory bandwidth utilization, and wherein the memory channel units are configured to schedule groups based on a highest level QoS parameter in each group; and wherein the memory channel units are configured to presynthesize the memory operations into commands for the memory, and wherein at least one of the memory operations is presynthesized into a plurality of the commands for the memory, and wherein the memory interface unit is configured to further reorder the commands to achieve higher memory bandwidth utilization than other orders of the commands would achieve.