Patent ID: 7643003

Claim:
An LCD device, comprising: a plurality of gate lines formed in an LCD panel; a plurality of driving stages, each of which sequentially outputting a respective scan pulse to a corresponding one of the plurality of gate lines; a dummy stage responsive to a scan pulse from a last driving stage and supplying a disabling scan pulse to the last driving stage to disable outputting of the scan pulse, wherein the last driving stage outputs a scan pulse later than the other driving stages; and a dummy gate line electrically connected to the dummy stage, wherein the dummy gate line is supplied with the disabling scan pulse from the dummy stage; wherein a start pulse is supplied to both the dummy stage and a first driving stage; wherein the dummy stage is disabled by the start pulse, and the first driving stage is enabled by the start pulse; wherein the first driving stage outputs a scan pulse earlier than the other driving stages; wherein each of the driving stage includes a first switching device for charging the first node with a high-potential voltage source in response to the start pulse or the driving scan pulse of the preceding driving stage; a second switching device for discharging the second node with a low-potential voltage source in response to the start pulse or the scan pulse of the preceding driving stage; a third switching device for charging the second node with a high-potential voltage source in response to the first clock pulse synchronized with the scan pulse outputted from the following driving stage; a fourth switching device for discharging the first node with a low-potential voltage source in response to the high-potential voltage source charged in the second node; a fifth switching device for discharging the second node with the low-potential voltage source in response to the high-potential voltage source charged in the first node; a sixth switching device for discharging the first node with the low-potential voltage source in response to the scan pulse outputted from the following driving stage; a pull-up switching device for outputting a second clock pulse prior to the first clock pulse as the scan pulse in response to the high-potential voltage source charged in the first node; and a pull-down switching device for outputting the low-potential voltage source in response to the high-potential voltage source charged in the second node.