Patent ID: 8753929

Claim:
A structure fabrication method, said method comprising: providing a structure which comprises a substrate, a gate dielectric region on and in direct physical contact with the substrate, and a gate electrode region on and in direct physical contact with a top surface of the gate dielectric region, wherein the top surface of the gate dielectric region defines a reference direction perpendicular to the top surface of the gate dielectric region; implanting atoms in a top portion of the gate electrode region, which expands the top portion of the gate electrode region in a lateral direction parallel to the top surface of the gate dielectric region; after said implanting atoms, forming a conformal dielectric layer on top and side walls of the gate electrode region; forming a dielectric spacer layer on the conformal dielectric layer; and etching the dielectric spacer layer such that only spacer portions of the dielectric spacer layer which are under the conformal dielectric layer remain, wherein for any point of the remaining spacer portions, a straight line through that point and parallel to the reference direction intersects the conformal dielectric layer.