Patent ID: 7539952

Claim:
A computer implemented design system comprising: a library information storage section configured to store geometry information of a cell disposed on a substrate, a plurality of wirings connected to the cell, and a provisional via between the wirings; a layout design information storage section configured to store design information of the cell, the wirings, and the provisional via; an optimal via list creating unit configured to read the geometry information from the library information storage section and the design information from the layout design information storage section, and to create an optimal via list by optimizing the geometry and size of the provisional via based on environment profiles of the provisional via; an optimal via list storage section configured to store the optimal via list; a layout design unit configured to design an integrated circuit by reading the geometry information from the library information storage section and the design information from the layout design information storage section and arrange the cell, the wirings and the provisional via on a layout; and an optimal via replacement unit configured to extract the provisional via from the layout and replace the provisional via with the optimal via stored in the optimal via list storage section based on the environment profiles of the provisional via.