Patent ID: 8710623

Claim:
An integrated circuit, comprising: a semiconductor die; wherein the semiconductor die has first and second surfaces; at least one discrete capacitor mounted on the semiconductor die; wherein the at least one discrete capacitor is mounted on the first surface of the semiconductor die; two electrodes for each discrete capacitor; two flexible adhesive connections for each discrete capacitor, each of the two flexible adhesive connections connecting the discrete capacitor to one of the two electrodes for the discrete capacitor; wherein the two flexible adhesive connections accommodate a difference in thermal expansion between the discrete capacitor and the semiconductor die; a plurality of bond pads and a plurality of land pads disposed on the semiconductor die, wherein the land pads include two land pads for each discrete capacitor; two solder connections for each discrete capacitor, each of the two solder connections connected to, and between, one of the two electrodes for the discrete capacitor and one of the two land pads for the discrete capacitor; and a package arrangement electrically coupling the plurality of bond pads to a plurality of interconnect terminals of the package arrangement; wherein the package arrangement is attached to the semiconductor die at the second surface of the semiconductor die.