Patent ID: 8188535

Claim:
A nonvolatile semiconductor memory device comprising: a first semiconductor layer having impurity regions; a second semiconductor layer having a source region and a drain region; a first insulating film over the first semiconductor layer and the second semiconductor layer; a floating gate over the first insulating film, the floating gate overlapping with the first semiconductor layer and the second semiconductor layer; a second insulating film over the floating gate; a control gate over the second insulating film, the control gate overlapping with the first semiconductor layer, the second semiconductor layer, and the floating gate; and a first conductive film electrically connected to the impurity regions over the control gate, a second conductive film electrically connected to one of the source region and the drain region over the control gate; and a third conductive film electrically connected to the other of the source region and the drain region over the control gate, wherein the first conductive film entirely overlaps with the first semiconductor film, wherein the second conductive film and the third conductive film partially overlap with the second semiconductor film, and wherein, in a region between the first semiconductor layer and the second semiconductor layer the width of the floating gate and the width of the control gate are wider in a direction parallel to the direction of the source region to the drain region than the distance between the source region and the drain region.