Patent ID: 7409491

Claim:
A memory subsystem comprising: a host configured to initiate memory accesses, said host being coupled to a first memory module of a plurality of memory modules by one or more links, each of said memory modules including one or more memory chips; and a switching circuit configured to convey data, the switching circuit being manufactured in a stacked formation with at least one of the memory chips, wherein the switching circuit is configured to: detect a memory access initiated by the host; route the detected access to another memory module of said memory modules, in response to determining the access is not directed to a memory chip of the first memory module; and process the detected access within the first memory module, in response to determining the access is directed to a memory chip of the first memory module; wherein when a switching circuit in a particular memory chip retrieves data from a memory chip, the switching circuit conveys the retrieved data either (i) directly to the host, or (ii) to a switching circuit in a memory chip which is closer to the host than the particular memory module.