Patent ID: 7535762

Claim:
A semiconductor memory device comprising: a memory cell unit having a plurality of memory cells connected in series, a first select transistor and a second select transistor, the plurality of memory cells being positioned between the first select transistor and the second select transistor, the memory cell unit being arranged in an array form; a bitline, the first select transistor being positioned between the bitline and the plurality of memory cells; and a programming circuit for programming into a selected memory cell among the plurality of memory cells in a selected memory cell unit, wherein at a time of programming, the programming circuit applies a first high voltage for programming to a gate electrode of the selected memory cell, applies a second high voltage to a gate electrode of a first memory cell positioned between the selected memory cell and the first select transistor, applies a third voltage to a gate electrode of a second memory cell positioned between the selected memory cell and the second select transistor, applies a fourth high voltage to a gate electrode of a third memory cell positioned between the selected memory cell and the second select transistor, the third memory cell being different from the second memory cell, and applies a fifth voltage to a gate electrode of the first select transistor, wherein all of the selected memory cell, the first memory cell, the second memory cell and the third memory cell are included in the selected memory cell unit, the first high voltage is higher than both the second high voltage and the fourth high voltage, both the second high voltage and the fourth high voltage are higher than the third voltage and higher than the fifth voltage, and at the time of programming, the third voltage is lower than a voltage applied to a memory cell positioned between the select memory cell and the first select transistor and adjacent to the selected memory cell.