Patent ID: 7176763

Claim:
A phase-locked loop (PLL) integrated circuit, comprising: a voltage-controlled oscillator; a loop filter having first and second input terminals and an output terminal coupled to an input of said voltage-controlled oscillator; a charge pump configured to drive the first input terminal of said loop filter with a pump output signal; a first phase detector configured to generate a first pair of output signals in response to the reference clock signal and the feedback clock signal; and a phase-lock accelerator configured to drive the second input terminal of said loop filter with an analog output signal, in response to a reference clock signal and a feedback clock signal, said phase-lock accelerator comprising: a second phase detector configured to generate a second pair of output signals in response to the reference clock signal and the feedback clock signal; and a digital-to-analog converter configured to generate the analog output signal in response to the second pair of output signals.