Patent ID: 6861740

Claim:
A flip-chip package substrate, comprising: a plurality of wiring layers forming a stack and having an uppermost wiring layer, a bottommost layer, and at least one inner wiring layer; a plurality of insulation layers sandwiched between two neighboring wiring layers for isolating the wiring layers such that an insulation layer and a wiring layer stack on top of each other alternately; and a plurality of conductive plugs passing through the insulation layer for connecting the wiring layers electrically; wherein the uppermost wiring layer has a plurality of core power/ground bump pads, at least one signal bump pad rings, at least one power bump pad rings and at least one ground bump pad rings, the core power/ground pads are located in the central region of the die while the signal pad ring, the power pad ring and the ground pad ring are located outside the central power/ground pad region but concentric to the central power/ground pad region; wherein at least one non-signal bump pad ring encloses at least one signal bump pad ring; and wherein at least one inner wiring layer has at least one signal trace, and at least one guard traces and the guard trace is adjacent to the signal trace.