Patent ID: 7581086

Claim:
A digital signal processor, comprising: at least one cluster, comprising: at least two function units, each conducting different type instructions, comprising a load/store unit for executing loading and storing instructions, and an arithmetic unit for performing arithmetic calculations, wherein the load/store unit and the arithmetic unit support pointer instructions; two index register files respectively connected to the load/store unit and the arithmetic unit, each maintaining an index value and an offset value; wherein each index register file updates the index value by adding the offset value to the index value after per read operation; at least two private register files, individually connected to the load/store unit and the arithmetic unit for data storage; a ping-pong register, connected to the load/store unit and the arithmetic unit for providing exclusively accessible data storage; and a public register file, comprising: two read ports, individually connected to the load/store unit and the arithmetic unit, allowing the load/store unit and the arithmetic unit to concurrently read same data from the public register file; and one write port directly connected to the load/store unit, via which data is input and stored in the public register file.