Patent ID: 8587989

Claim:
A nanotube memory array comprising: a substrate; a first conductor layer disposed on the substrate, the first conductor layer having a defined pattern; a nanotube fabric layer disposed over and in electrical communication with the first conductor layer; a second conductor layer disposed over, and in electrical communication with the nanotube fabric layer; a memory operation circuit including a circuit for generating and applying a select signal on the first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers; wherein at least two adjacent memory cells are formed in at least two selected cross sections of the first conductor layer, nanotube fabric layer, and second conductor layer, each memory cell uniquely addressable and programmable by said memory operation circuit, wherein for each memory cell, a change in the resistance between first and second conductor layers corresponds to a change in an informational state of the memory cell; wherein the nanotube fabric layer and the second conductor layer are conformally disposed, have a corresponding defined pattern, and form a conductor-on-nanotube trace.