Patent ID: 8581324

Claim:
A floating-gate memory cell disposed at a surface of a substrate, comprising: a first well region of a first conductivity type at a location of the surface; a second well region at a location of the surface; a dielectric layer overlying portions of the first and second well regions; a polycrystalline silicon gate element disposed over the dielectric layer at locations of the first and second well regions, the portion of the gate element disposed over the dielectric layer at the first well region defining a coupling capacitor, and the portion of the gate element disposed over the dielectric layer at the second well region defining a combined read transistor and tunneling capacitor; a first diffused region of a second conductivity type formed at a surface of the first well region at least at locations adjacent to the locations at which the gate element is disposed; source and drain diffusions disposed in the second well region on opposite sides of the gate element, and of an opposite conductivity type from that of the second well region; and plurality of conductor elements making electrical contact to the first well region, to the second well region, and to the source and drain diffusions; wherein the gate element has an area overlying the first well region that is substantially larger than an area of the gate element overlying the second well region.