Patent ID: 7028196

Claim:
A processor integrated circuit comprising: at least one processor having at least one power connection; a lower level of cache memory coupled to provide instructions to the at least one processor; an upper level of cache memory coupled to provide instructions to the lower level of cache memory upon a miss in the lower level of cache memory, the upper level of cache memory having at least one power connection separate from the at least one power connection of the at least one processor; and a clock generator circuit for providing a clock signal having a clock rate to the processor integrated circuit, wherein the upper level of cache memory is adaptable to at least a first and a second level of latency; wherein the integrated circuit is capable of switching between a first mode wherein the cache memory operates at the first level of latency at a first cache power connection voltage and a second mode wherein the upper level of cache memory operates at the second level of latency at a second cache power connection voltage.