Patent ID: 7987321

Claim:
A multicore processor, comprising: a plurality of cache memories configured to store one or more cache lines; and a plurality of processor cores, each associated with one of the cache memories; with each of a respective cache memory of at least some of the cache memories configured to maintain at least a portion of the respective cache memory in which each cache line is dynamically managed as either local to the associated processor core according to a first level in a cache hierarchy or shared among multiple processor cores according to a second level in the cache hierarchy, with at least some of the shared cache lines assigned as a home location for caching a corresponding portion of the main memory, with a cache memory associated with a first processor core being configured to retrieve data from a main memory and store the data in a shared cache line in response to memory requests from the first processor core and in response to memory requests from other processor cores, and with the first processor core being configured to access a portion of the main memory at a given address according to the first level using a first portion of the address if the address is not assigned a home location in a shared cache line, and using a second portion of the address if the address is assigned a home location in a shared cache line.