Patent ID: 8296550

Claim:
A processor including a plurality of execution clusters and a hierarchical register file, the processor comprising: a plurality of first-level store buffers with each first-level store buffer including one or more entries being configured to: store age information that comprises at least one of a definition time or a kill time; a second-level register file including a plurality of mappable registers, the second-level register file being shared between or among the plurality of execution clusters, the second-level register file being configured to: allocate the plurality of mappable registers so as to store execution results of instructions executed by the plurality of execution clusters; and provide secondary register storage for each of the plurality of execution clusters; a plurality of first-level register files operatively coupled with the second-level register file, each of the plurality of first-level register files included in a respective execution cluster, the plurality of first-level register files being configured to: store instruction operands; and provide the instruction operands to respective execution units of the plurality of execution clusters for use in executing associated instructions; a plurality of operand capture structures operatively coupled with the second-level register file and respective first-level register files, each of the plurality of operand capture structures included in a respective execution cluster and including at least one read port and at least two types of write ports, a first write port and a second write port, the plurality of operand capture structures being configured to: provide operands to execution units; and a plurality of bypass caches configured to provide immediate literal values directly to respective execution units of the plurality of execution clusters prior to, or contemporaneously with, writing the immediate literal values to one or more of the second-level register file, a first-level register file of the plurality of first-level register files, or an operand capture structure of the plurality of operand capture structures, wherein the processor is configured to: write, substantially contemporaneously with when an instruction is written into a scheduler, to the first write port of an operand capture structure with at least one of a value read from a first-level register file of the plurality of first-level register files or a value read from the second level register file; write to the second write port of the operand capture structure with execution results; read from the at least one read port of the operand capture structure after instruction scheduling; and store a definition time reflecting a time at which a respective entry is written into a first-level store buffer of the plurality of first-level store buffers and store a kill time reflecting another time at which another entry that has a matching same address as the respective entry is subsequently written into the first-level store buffer.