Patent ID: 7297584

Claim:
A method of manufacturing a semiconductor device comprising: forming a PMOSFET and an NMOSFET on a substrate; and forming a dual stress liner including a first portion having a first stress and a second portion having a second stress smaller than the first stress on the PMOSFET and the NMOSFET, wherein the first portion is formed on the PMOSFET, and the second portion is formed on the NMOSFET, wherein the forming the dual stress liner comprises: forming a stress liner on the PMOSFET and the NMOSFET; and relaxing a stress of a portion of the stress liner formed on the NMOSFET; and wherein the stress of the portion of the stress liner on the NMOSFET is relaxed by selectively exposing the portion of the stress liner on the NMOSFET to an ultraviolet light.