Patent ID: 7388408

Claim:
A phase-frequency detector capable of reducing dead zone and generating output signals at a first output end and a second output end based on input signals received at a first input end and a second input end, the phase-frequency detector comprising: a first latch circuit having a first end coupled to the first output end of the phase-frequency detector; a second latch circuit having a first end coupled to the second output end of the phase-frequency detector; a reset control circuit coupled to first ends of the first and second latch circuits and the first and second output ends of the phase-frequency detector for generating corresponding signals to the first ends of the first and second latch circuits based on voltage levels obtained at the first and second output ends of the phase-frequency detector; a first pulse generator comprising: a first input end coupled to the first input end of the phase-frequency detector; a second input end; and an output end coupled to the second end of the first latch circuit; a second pulse generator comprising: a first input end coupled to the second input end of the phase-frequency detector; a second input end; and an output end coupled to the second end of the second latch circuit; a first inverting circuit comprising: an input end coupled to the first input end of the phase-frequency detector; and an output end coupled to the second input end of the first pulse generator; a second inverting circuit comprising: an input end coupled to the second input end of the phase-frequency detector; and an output end coupled to the second input end of the second pulse generator; a first sensing device comprising: a first end coupled to the second input end of the first pulse generator; a second end coupled to the first inverting circuit; and a control end coupled to the second end of the first latch circuit; and a second sensing device comprising: a first end coupled to the second input end of the second pulse generator; a second end coupled to the second inverting circuit; and a control end coupled to the second end of the second latch circuit.