Patent ID: 7075825

Claim:
For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell, wherein the operation of setting the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell using at least one programming voltage applied to the bit line, wherein the program operation includes a series of programming operations each followed by a related verifying operation, and wherein the series of programming operations includes a first programming operation and a second programming operation after the first programming operation, the duration of the second programming operation being shorter than that of the first programming operation.