Patent ID: 6987041

Claim:
A method of manufacturing a semiconductor device comprising the steps of: preparing a semiconductor substrate having a memory cell area and a logic circuit area defined an a principal surface of the semiconductor substrate; forming a gate insulating film on the principal surface of the semiconductor substrate; forming a silicon film on the gate insulating film; doping impurities into the silicon film to make a region of the silicon film in the memory cell area having a first impurity concentration and to make a region of the silicon film in the logic circuit area having a second impurity concentration lower than the first impurity concentration; patterning the silicon film to leave wood lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area; and forming source/drain regions MISFETS in a surface layer of the semiconductor substrate by doping impurities into regions on both sides of each word line in the memory cell area and into regions on both sides of each gate electrode in the logic circuit.