Patent ID: 6883053

Claim:
A data transfer control circuit including an externally accessible address bus, an externally accessible data bus, an external interrupt signal line, a plurality of data receiver-transmitters, and an interrupt controller, each data receiver-transmitter having a plurality of registers selectively accessible via the address bus and the data bus, the plurality of registers in each said data receiver-transmitter including a data register for storing transmitted data and received data, and an interrupt identification register for indicating interrupt sources, the data receiver-transmitters generating respective internal interrupt signals, the interrupt controller generating an external interrupt signal on the interrupt signal line responsive to the internal interrupt signals generated by the data receiver-transmitters, wherein: one of the data receiver-transmitters in the plurality of data receiver-transmitters also receives the internal interrupt signals generated by the plurality of data receiver-transmitters, and has, as one of said plurality of registers, an interrupt status register with bits indicating logic levels of said internal interrupt signals.