Patent ID: 7318126

Claim:
A method for providing a non-synchronized memory consistency model in a computing device having multiple processors that allow a shared memory programming model, comprising the step of: maintaining memory consistency with a corresponding broadcast-free, latency-hiding coherence protocol that permits the multiple processors to have incoherent views of a state of an address space, wherein said maintaining step comprises the steps of: utilizing a push instruction and a pull instruction to respectively export and import views to the multiple processors; utilizing an accepted invalidation bit and an unaccepted invalidation bit for each of a plurality of cache lines, the accepted invalidation bit for causing a cache line miss when set and the cache line is accessed, the unaccepted invalidation bit for causing the accepted invalidation bit to be reset in response to an issuance of the pull instruction; and utilizing a tree based on point-to-point connections with leaf nodes corresponding to the multiple processors and internal nodes corresponding to administration units that allows broadcast free implementation of the push instruction and the pull instruction and atomic instructions and memory accesses.