Patent ID: 7305635

Claim:
An integrated circuit comprising (a) at least one core, each of which contains one or more scan chains, and each of which operates in modes A and B, where in mode A said at least one core advances in its normal operation with each appearance of an operational clock pulse, and in mode B said one or more scan chains of said at least one core output a stream of bits that reflect state of memory elements in said at least one core, and (b) a functionally reconfigurable module (FRM) that is coupled to said at least one core, the improvement comprising: a bit extractor element configured from said FRM to be responsive to said stream of bits outputted by said one or more scan chains of said at least one core, and further configured to deliver at least one stream of selected bits from said each of said stream of bits outputted by said one or more scan chains of said at least one core; and a finite state machine module configured from said FRM to be responsive to said at least one stream of selected bits, which module comprises a logic sub-module and a memory sub-module, where the logic sub-module is responsive to said at least one stream of selected bits and to one or more signals fed back from said memory sub-module, and said logic sub-module outputs one or more signals that are applied to said memory sub-module, and one or more signals that form an output of said finite state machine module.