Patent ID: 8724385

Claim:
A semiconductor memory comprising: a plurality of memory cells for storing data; at least one word line connected to a plurality of the memory cells; a plurality of first sub-bit lines running crosswise to the at least one word line, each first sub-bit line being connected to at least one of the memory cells; a plurality of second sub-bit lines running crosswise to the at least one word line, each second sub-bit line being connected to at least one of the memory cells; a plurality of selector elements having respective first terminals and respective second terminals, the first terminals being connected to respective ends of the plurality of first sub-bit lines; at least one main bit line connected to the second terminals of two mutually adjacent selector elements; at least one fixed potential line paralleling the at least one main bit line; a voltage generating circuit connected to the second sub-bit lines; a first dielectric layer on which the first sub-bit lines and the second sub-bit lines are disposed; and a second dielectric layer covering the first dielectric layer, the at least one main bit line and the at least one fixed potential line being disposed on the second dielectric layer, wherein each memory cell in the plurality of memory cells is connected to one of the first sub-bit lines and one of the second sub-bit lines, first sets each including the one of the first sub-bit lines, the one of the second sub-bit lines and the memory cells disposed therebetween are positioned directly below and overlapped by one said main bit line through the second dielectric layer, second sets each including the one of the first sub-bit lines, the one of the second sub-bit lines and the memory cells disposed therebetween are positioned directly below and overlapped by one said fixed potential line through the second dielectric layer, and the first sets and the second sets are arranged in a direction perpendicular to the main bit line alternately.