Patent ID: 8036010

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cell arrays stacked on said semiconductor substrate and arranged in a matrix, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing said first lines, and a plurality of memory cells arranged at intersections of said first lines and said second lines, each memory cell having one end connected to one of said first lines and the other end connected to one of said second lines; a first control circuit provided on said semiconductor substrate immediately beneath said memory cell arrays and having one end connected to said first lines to select and drive said first lines; and a second control circuit provided on said semiconductor substrate immediately beneath said memory cell arrays and having one end connected to said second lines to select and drive said second lines; a plurality of third lines commonly connected to said first control circuit located immediately beneath plural memory cell arrays in the same column of said memory cell arrays arranged in a matrix; a plurality of fourth lines commonly connected to said second control circuit located immediately beneath plural memory cell arrays in the same row of said memory cell arrays arranged in a matrix; a third control circuit connected to one end of said third lines to select and drive said third lines; and a fourth control circuit connected to one end of said fourth lines to select and drive said fourth lines.