Patent ID: 8243543

Claim:
A semiconductor memory device comprising: a first serializer configured to partially serialize input 8-bit parallel data, which are received from the internal unit cells in response to a read command, to output first to fourth serial data; a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data; and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data, wherein the first serializer comprises: a first phase shifter configured to shift the phases of 4-bit data among the 8-bit parallel data four times a data window of each data in the seventh serial data; a first multiplexer configured to multiplex the other 4-bit data among the 8-bit parallel data and the output of the phase shifter to output the first to fourth serial data; and a first latch unit configured to latch the output of the multiplexer, and wherein the first phase shifter comprises: a plurality of unit phase shifters configured to shift the phase of the 4-bit data, each of the unit phase shifters comprising: an inverter configured to invert input data; a transfer gate configured to transfer the output of the inverter in response to a first control pulse, and an inverter latch configured to latch and invert the output of the transfer gate.