Patent ID: 8630133

Claim:
A memory device comprising: a memory cell array storing data comprising a first bit and lower bits; an address decoder selecting an address of the memory cell array corresponding to an address signal comprising most significant bits and less significant bits and serially inputted in synchronization with a clock; a plurality of read-out circuits, each corresponding to a bit of the data, respectively; and a shift register serially outputting data from the first bit in synchronization with the clock, the data being read out from the plurality of read-out circuits, wherein the address decoder inputs candidate bit data of a predetermined number for the first bit, which determined by the most significant bits, to corresponding read-out circuits of the predetermined number, before the less significant bits of the address signal are established, so that reading out the candidate bit data of the predetermined number is commenced before all bits of the address signal are established, and the read-out circuits of the predetermined number are configured to read not only the candidate bit data but also the same number of lower bits of the data stored in the memory cell as the predetermined number.