Patent ID: 7447103

Claim:
A row decoder circuit for electrically programmable and erasable non volatile memories being monolithically integrated on semiconductor with: at least one matrix of memory cells having a NOR structure, organized into sectors with rows and columns of memory cells, associated circuit portions for addressing, decoding, reading, writing and erasing the content of the memory cells, a plurality of pre-decoding circuit portions, as many as there are sectors of the matrix of cells, and a plurality of row decoding circuit portions, each row decoding circuit portion comprising a row driver or inverter final stage incorporating a complementary pair of transistors with a pull-up transistor and a pull-down transistor; a pass-transistor being provided upstream of the input of the inverter final stage to receive an output signal from a NOR gate of the pre-decoding circuit portion, wherein the row decoder circuit further comprises: a pull-up stage or decoupler inserted between a power supply of the inverter final stage and an input of the same inverter final stage to apply a positive potential at the input of the inverter final stage further to negative pre-decoding signals and maintain the pull-up transistor off during the selective erasing step by means of the decoupler as to apply a negative voltage onto a plurality of sole selected matrix rows maintaining instead a plurality of gates of the cells belonging to the rows not selected for the erasing step floating.