Patent ID: 7657858

Claim:
A method of designing a power pad layout in an integrated circuit, the method comprising the steps of: determining a location of at least one electrostatic discharge (ESD) structure in the integrated circuit so as to minimize a placement cost; and determining a location of at least one connection between the at least one ESD structure and at least one power ring in the integrated circuit; wherein the steps are performed at least in part by a processor; wherein the step of determining a location of at least one connection comprises: representing a power pad layout as a set of corner-stitched tiles comprising at least one corner-stitched tile representing each of a plurality of elements to be connected to a given power ring; and determining a minimum spanning tree of the corner-stitched tiles representing elements to be connected to a given power ring; and wherein the step of determining a minimum spanning tree of corner-stitched tiles representing elements to be connected to a given power ring comprises the steps of: (1) adding a tile from a set of all tiles representing the elements to be connected to a given power ring to an enclosed tile set; (2) selecting a member of the enclosed tile set; (3) selecting a tile adjacent to the selected member of the enclosed tile set such that the selected adjacent tile can be reached from the selected member tile in compliance with one or more design rule checks; (4) if the selected adjacent tile is not within the enclosed tile set, adding the selected adjacent tile to a set of minimum cost tiles; (5) repeating steps (3) and (4) for each tile adjacent to the selected member of the enclosed tile set; (6) repeating steps (2) through (4) for each member of the enclosed tile set; (7) appending the set of minimum cost tiles to the enclosed tile set; and (8) repeating steps (2) through (7) until the enclosed tile set includes all tiles representing elements to be connected to the given power ring.