Patent ID: 7796442

Claim:
A nonvolatile semiconductor memory device configured to be electrically erased and programmed, the memory device comprising: a first conductive type semiconductor substrate having a first side and a second side opposite to the first side, the substrate including a source and a drain that are formed near a surface of the first side of the substrate and spaced apart from each other, each of the source and drain having a second conductive type opposite to the first conductive type; a floating gate disposed on a channel region of the substrate through an electrically insulating film, the channel region being located between the source and the drain and having a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions, the first and second end portions having approximately same width; and a control gate at least partially capacitively coupled to the floating gate, wherein the memory device is configured to be electrically erased by a hot carrier generated in the first end portion of the channel region due to avalanche breakdown between the substrate and the drain, wherein the channel region has an electric field concentration zone, where an electric field in the channel region reaches a maximum during a program operation, wherein the electric field concentration zone is located in the middle portion between the first and second end portions of the channel region, and wherein a distance between the electric field concentration zone and the first end portion of the channel region is greater than or equal to 0.06 μm.