Patent ID: RE44013

Claim:
A method for computing a zero digital sum variation (ZDSV) of a stream of channel-bit symbols, comprising the steps of: (a) providing an initial value ZDSV n−1 , an initial value ODD(t 0 ˜efm n−1 ) and a initial bias value by a digital sum variation (DSV) computation system , wherein the initial value ZDSV n−1 is the zero digital sum variation of a previous start-to-channel-bit symbol efm n−1 , wherein the ODD(t 0 ˜efm n−1 ) indicates that the stream of the channel-bit symbols from a starting logic voltage state to the previous start-to-channel-bit symbol efm n−1 contains an odd-number or an even-number of 1s, the initial bias value is either 1 or −1; (b) providing a current channel-bit symbol efm n by the DSV computation system , and obtaining a partial digital sum variation (PDSV) value PDSV(efm n ) and a ODD(efm n ) value in accordance with the current symbol efm n ; (c) obtaining a plurality of partial digital sum variation (PDSV) values PDSV(m n i ) and ODD(m n i ) values in accordance with all possible merge-bit symbols m n i by the DSV computation system , wherein i=0, 1, . . . , x, the number of the possible merge-bit symbols is x+1; (d) calculating ZDSV n i =ZDSV n−1 +ZDSV(m n i )+ZDSV(efm n ) i by the DSV computation system and calculating ODD(t 0 ˜efm n ) i =ODD(t 0 ˜efm n−1 )⊕ODD(m n i ).⊕ODD(efm n ) by the DSV computation system , wherein i=0, 1, . . . , x, in order to determine the ZDSV n of the zero digital sum variation of the current channel-bit symbol efm n , wherein ZDSV(m n i )=PDSV(m n i )*(−1) ODD(t0˜efmn−1) and ZDSV(efm n ) i =PDSV(efm n )*(−1) ODD(t0˜mni) , wherein ODD(t 0 ˜m n i )=ODD(t 0 ˜efm n−1 )⊕ODD(m n i ), wherein ⊕ represents the XOR logic operation, the ZDSV n i is the zero digital sum variation of the channel-bit symbol efm n corresponding to the i-th merge-bit symbol of the possible merge-bit symbols, the ZDSV(m n i ) means a zero digital sum variation of the i-th merge-bit symbol of the possible merge-bit symbols corresponding to the current channel-bit symbol efm n , the ZDSV(efm n ) i means a zero digital sum variation of the current channel-bit symbol efm n corresponding to the i-th merge-bit symbol of the possible merge-bit symbols; (e) DSV n i =ZDSV n i +(initial bias value)*ODD(t 0 ˜efm n−1 ) i , wherein the DSV n i is a digital sum variation of the current channel-bit symbol efm n corresponding to the i-th merge-bit symbol of the possible merge-bit symbols; (f) determining a final merge-bit symbol m n j in accordance with the absolute value of DSV n i and a run time limit by the DSV computation system , wherein jε{i}, wherein i=0, 1, . . . , x; and (f) assigning the initial value ZDSV n−1 =ZDSV n j , the ODD(t 0 ˜efm n−1 )=ODD(t 0 ˜efm n ) j by the DSV computation system , and then jumping to step (b).