Patent ID: 7888788

Claim:
A semiconductor device comprising: a package substrate including an upper surface, a first wiring layer formed on the upper surface, a lower surface opposed to the upper surface, a second wiring layer formed on the lower surface, a third wiring layers formed between the upper surface and the lower surface, and a plurality of through holes formed from one of the upper surface and the lower surface to the other; a semiconductor integrated circuit includes a front surface, a plurality of pad electrodes formed on the front surface, and a back surface opposed to the front surface, and mounted on the upper surface of the package substrate such that the front surface faces the upper surface; a plurality of module terminals formed on the lower surface of the package substrate; and a plurality of external connection terminals arranged between the front surface of the semiconductor integrated circuit and the upper surface of the package substrate, and electrically connecting the pad electrodes with the module terminals, respectively; wherein the external connection terminals include an external input terminal, an external output terminal, an external ground terminal and an external power terminal; wherein the external input terminal and the external output terminal are able to input/output external data in parallel to each other; wherein one of the external input terminal and the external output terminal is electrically connected with a first module terminal of the module terminals via a first upper wiring formed in the first wiring layer, a first through hole of the through holes and a first lower wiring formed in the second wiring layer; wherein the other is electrically connected with a second module terminal of the module terminals via a second upper wiring formed in the first wiring layer, a second through hole of the through holes and a second lower wiring formed in the second wiring layer; wherein a length of first upper wiring is longer than that of second upper wiring; and wherein a length of first lower wiring is shorter than that of second lower wiring.