Patent ID: 7420240

Claim:
A memory device comprising: a substrate; a gate stack pair comprising two gate stacks formed on the substrate; a conductive contact between the two gate stacks and in contact with a doped region of the substrate; a pair of vertical oxide spacers adjacent to each gate stack of said gate stack pair; a respective nitride layer overlaying and in contact with each said vertical oxide spacer and a top layer of each said gate stack, wherein neither of said nitride layers extends to overlay said doped region and a portion of each said nitride layer is situated between respective vertical oxide spacers; and a respective dielectric layer overlaying each said nitride layer, the dielectric layer being spaced from each said vertical oxide spacer by said nitride layer such that said dielectric layer is not in direct contact with said vertical oxide layer, wherein the pair of vertical oxide spacers is partially etched back and the respective nitride layers are of a thickness sufficient to fill the etched back portion of a respective one of the pair of vertical oxide spacers.