Patent ID: 8395947

Claim:
A memory device, comprising: an array of memory cells configured to store information; a first bitline coupled to the memory cells in the array and a second bitline coupled to the memory cells in the array; and a sense amplifier coupled to the first bitline and the second bitline, wherein the sense amplifier is configured: to receive the information stored in a given memory cell via one of the first bitline and the second bitline; in response to an activation signal, to develop a signal by amplifying the information; and, in response to a gating signal, output the signal; control logic which, in response to a read command, is configured to: turn on a first isolation signal and turn off a second isolation signal, thereby coupling the sense amplifier to the given memory cell via the first bitline; provide the activation signal to the sense amplifier to develop the signal; after the signal is developed, turn off the first isolation signal and turn on the second isolation signal, thereby coupling an output of the sense amplifier to an unused input/output (I/O) line of the memory device via the second bitline, as opposed to an I/O line of the memory device that is proximate to the sense amplifier; and provide the gating signal to the sense amplifier, thereby outputting the signal on the unused I/O line.