Patent ID: 8269262

Claim:
A semiconductor device comprising: an n-type substrate having a front surface and a back surface; a first layer of n-type semiconductor material on and in direct contact with the front surface of the n-type substrate, wherein the first layer of n-type semiconductor material is non-coextensive with the underlying n-type substrate thereby forming a mesa having an upper surface and sidewalls, wherein the upper surface and sidewalls of the mesa form an edge and wherein the front surface of the n-type substrate adjacent the edge is exposed; a plurality of raised n-type regions on the upper surface of the mesa, the raised n-type regions comprising an upper layer of n-type semiconductor material on a lower layer of n-type semiconductor material which is on the upper surface of the mesa, the raised n-type regions have an upper surface comprising the upper layer of n-type semiconductor material and sidewalls comprising an upper sidewall portion comprising the upper layer of n-type semiconductor material and a lower sidewall portion comprising the lower layer of n-type semiconductor material, wherein the lower layer of n-type semiconductor material has a different doping concentration than the first layer of n-type semiconductor material; p-type regions on the upper surface of the mesa between and adjacent the raised n-type regions and along the lower sidewall portion of the raised regions, wherein the p-type regions are adjacent the edge of the mesa; a first dielectric layer on the sidewalls of the raised regions, on the p-type layer between and adjacent the raised regions and on the sidewalls of the mesa; one or more additional layers of dielectric material on the first dielectric layer on the sidewalls of the mesa and between and adjacent the raised regions on the upper surface of the mesa; source ohmic contacts on the upper surfaces of the raised regions; a gate ohmic contact on the p-type regions; a drain ohmic contact on the back surface of the substrate layer opposite the first layer of semiconductor material; one or more layers of metal on the source ohmic contacts; one or more layers of metal on the gate ohmic contact; and one or more layers of metal on the drain ohmic contact.