Patent ID: 7349332

Claim:
A traffic management processor for processing an unspecified bit rate (UBR) traffic flow and a constant bit rate (CBR) traffic flow, comprising: a departure time calculator (DTC) circuit for calculating a departure time for each packet received; a content addressable memory (CAM) device coupled to the DTC circuit and having a plurality of rows, each row including a first portion for storing the departure time for a corresponding packet and including a second portion for storing a CBR bit indicating whether the corresponding packet belongs to the UBR traffic flow or to the CBR traffic flow, wherein an asserted CBR bit indicates the departure time corresponds to a packet of the CBR traffic flow, and a de-asserted CBR bit indicates the departure time corresponds to a packet of the UBR traffic flow; and compare logic coupled to the CAM device and configured to determine which of the departure times selectively output from the CAM device is the earliest; wherein the CAM device is configured to forward to the compare logic only the departure times having a de-asserted CBR bit so that only the departure times for packets belonging to the UBR traffic flow participate in determining which departure time is the earliest in the compare logic.