Patent ID: 7652926

Claim:
A non-volatile semiconductor memory device, comprising: a memory array having a cell string, the cell string including: a plurality of normal memory cells connected serially to each other; a ground selection transistor gated so as to provide a source voltage to the normal memory cells; and at least two dummy cells connected serially between a normal memory cell on one side end of the plurality of normal memory cells and the ground selection transistor, wherein the plurality of normal memory cells and the dummy cells are non-volatile, the normal memory cells being configured to store data and the dummy cells being configured to not store data; and a word line selection block which controls normal word lines to gate the normal memory cells and dummy word lines to gate the dummy cells, wherein the dummy word lines are controlled as sequential voltage levels during a program operation to select the normal memory cell on the one side end, the sequential voltage levels being different from each other and each being between a voltage level of a signal gating the ground selection transistor and a voltage level of a normal word line gating the normal memory cell on the one side end.