Patent ID: 7879671

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: depositing a sacrificial layer over a cell region and over a peripheral region of a substrate in which the cell region includes capacitors on a first interlayer dielectric wherein defects occur on capacitors and occur on the sacrificial layer; removing selectively the sacrificial layer from the peripheral region such that the sacrificial layer remains over the cell region; forming a second interlayer dielectric over the remaining sacrificial layer and over the peripheral region; polishing down the second interlayer dielectric by using the remaining sacrificial layer as a barrier such that the defects on the capacitors and on the sacrificial layer are substantially removed and such that the second interlayer dielectric in the peripheral region is substantially planarized with the remaining sacrificial layer; etching away the remaining sacrificial layer; and forming a third interlayer dielectric on the cell region and on the peripheral region.