Patent ID: 7323381

Claim:
A method of manufacturing a semiconductor device in which an n channel MIS transistor is formed in a first region on a main surface of a semiconductor substrate made of single crystal silicon and a p channel MIS transistor is formed in a second region on said main surface, said method comprising the steps of: (a) forming a gate insulator mainly containing hafnium oxide on the main surface of said semiconductor substrate; (b) after said step (a), forming a first silicon gate electrode of said n channel MIS transistor on said gate insulator in said first region and forming a second silicon gate electrode of said p channel MIS transistor on said gate insulator in said second region; (c) after said step (b), depositing a first insulator with a thickness larger than that of said first and second silicon gate electrodes on the main surface of said semiconductor substrate, and then, planarizing the surface of said first insulator, thereby exposing each of the surfaces of said first and second silicon gate electrodes on the surface of said first insulator; (d) after said step (c), selectively covering the surface of said second silicon gate electrode exposed on the surface of said first insulator with a second insulator, and then, forming a first metal film on said first and second insulators; (e) after said step (d), heating said semiconductor substrate to react said first silicon gate electrode contacting with said first metal film, thereby converting said first silicon gate electrode of said n channel MIS transistor into a metal silicide gate electrode; (f) after said step (e), removing said second insulator, and then, removing said second silicon gate electrode such that said gate insulator thereunderneath remains; and (g) after said step (f), filling a gap formed by the removal of said second silicon gate electrode with a second metal film, thereby forming a metal gate electrode of said p channel MIS transistor over said gate insulator.