Patent ID: 8249850

Claim:
A simulation apparatus for executing simulation for performance evaluation of a system to be implemented by software and hardware using a hardware model, the simulation apparatus comprising a processor, wherein the processor executes a process including: first acquiring a first execution log representing a history of an instruction executed when existing tentative software is executed; dividing the first execution log into a plurality of basic processing units; modifying some of the plural basic processing units to produce a basic processing execution log to be used for the simulation; and inputting the basic processing execution log to the hardware model to execute the simulation to acquire information required for the performance evaluation, wherein the modifying comprises: extracting a modification target basic processing unit from among the plural basic processing units and producing a software model based on the extracted modification target basic processing unit; second acquiring a tentative execution log based on the software model; and synthesizing the plural basic processing units other than the modification target basic processing unit and the tentative execution log to produce the basic processing execution log.