Patent ID: 6927933

Claim:
An apparatus for use in applying write signals for driving a write head coupled between a first head locus and a second head locus to effect writing information to a memory device; said write signals including a first write signal and a second write signal; the apparatus being configured for varying circuit parameters according to predetermined operational characteristics; the apparatus comprising: (a) a current directing circuit; said current directing circuit being coupled with a first supply voltage and receiving said write signals; said current directing circuit directing a write current through a first circuit path including said write head in response to said first write signal; said current directing circuit directing said write current through a second current path including said write head in response to said second write signal; (b) at least one of: (1) an impedance adjustment system; said impedance adjustment system including a first impedance unit and a second impedance unit; said first impedance unit including at least one first impedance device configured for including at least one selected first impedance unit of a plurality of first impedance units within said first current path; said second impedance unit including at least one second impedance device configured for including at least one selected second impedance unit of a plurality of second impedance units within said second current path; and (2) a current adjustment system; said current adjustment system including a first current boost unit and a second current boost unit; said first current boost system being coupled between said first head locus and a second supply voltage lower than said first supply voltage; said first current boost system being configured for selectively including at least one selected first circuit element of a plurality of first circuit elements between said first head locus and said second supply voltage; said second current boost system being coupled between said second head locus and said second supply voltage; said second current boost system including at least one second circuit element configured for selectively including at least one selected second circuit element of a plurality of second circuit elements between said second head locus and said second supply voltage; and (c) a control unit coupled with at least one of said impedance adjustment system and said current adjustment system; said control unit generating control signals for effecting said selective including for at least one of said impedance adjustment system and said current adjustment system to effect said varying.