Patent ID: 7915706

Claim:
A semiconductor wafer comprising: a Silicon semiconductor substrate having at least one passivation region and at least one non-passivation region; a first insulator layer formed over the at least one non-passivation region; a polycrystalline Silicon layer: formed over the at least one passivation region to passivate the semiconductor substrate to trap carriers from the semiconductor substrate, thereby substantially immobilizing a surface conduction layer in the semiconductor substrate; and formed over the first insulator layer, such that over the at least one non-passivation region, the polycrystalline Silicon layer is doped to form a doped polycrystalline Silicon layer; at least one active device formed in the at least one non-passivation region; and at least one passive device formed over the at least one passivation region, wherein over the at least one passivation region, the polycrystalline Silicon layer is not doped.