Patent ID: 7493445

Claim:
A method of writing data to a cache memory having a plurality of memory segments, each segment allocating a different number of bytes per word line for data storage comprising the steps of: matching width of a first write data to a first memory segment having a correspondingly sized cache line data width; storing the first write data at an address of the first memory segment having a correspondingly sized cache line data width; and wherein if the first write data is initially written to a memory address contiguous with a first valid data, concatenating the first write data with the first valid data and storing in a second memory segment having a cache line data width corresponding to the size of the concatenated first write data and first valid data when all memory segments corresponding to the size of a combined data to be written are occupied by valid data, such that the valid data is replaced with the write data when an address space contiguous with the valid data is not available and valid data is present in an address specified by the write data.