Patent ID: 8274331

Claim:
A differential receiver, comprising: a first amplifying circuit comprising: a first differential pair of PMOS transistors configured to receive first and second input voltages; a first current source connected between a supply voltage source and the first differential pair of PMOS transistors; and a first load resistance section connected between a common node and the first differential pair of PMOS transistors, wherein nodes between the first differential pair of PMOS transistors and the first load resistance section serve as an output terminal and an inversion output terminal; and a second amplifying circuit comprising: a second differential pair of NMOS transistors configured to receive the first and second input voltages; a second current source connected between the common node and the second differential pair of NMOS transistors; and a second load resistance section connected between the supply voltage and the second differential pair of NMOS transistors, wherein nodes between the second differential pair of NMOS transistors and the second load resistance section are respectively connected to the output terminal and the inversion output terminal.