Patent ID: 7763480

Claim:
A method of manufacturing a thin film transistor (TFT) array substrate, comprising: providing a substrate; sequentially forming a first conductive layer, a insulating layer, a channel layer, and an ohmic contact layer over the substrate, and simultaneously patterning the first conductive layer, the insulating layer, the channel layer, and the ohmic contact layer, to form a plurality of gate lines parallel to each other on the substrate, and each gate line having a gate terminal port at a terminal; forming a plurality of color filer patterns over the substrate; removing at least a part of the insulating layer and the channel layer of each gate terminal port to expose the first conductive layer in the gate terminal port; removing a partial thickness of the color filter patterns to expose the gate lines; forming a patterned transparent electrode layer and a patterned second conductive layer to form a plurality of data lines, a plurality of electrode patterns and a plurality of sources/drains, wherein the data lines are parallel to each other and intersected with the gate lines to form a plurality of sub-pixel areas on the substrate, the electrode patterns are correspondingly located in the sub-pixel areas, the sources/drains are corresponding to the sub-pixel areas and disposed over the corresponding gate lines, and each source/drain is respectively connected to the corresponding data line and the corresponding electrode pattern; removing the ohmic contact layer exposed by the second conductive layer and the transparent electrode layer after forming the patterned transparent electrode layer and the patterned second conductive layer; forming a black matrix over the substrate for at least exposing the electrode patterns; and removing the second conductive layer in the electrode patterns with the black matrix as a mask.