Patent ID: 8644083

Claim:
A memory circuit comprising: a memory array comprising a plurality of memory cells arranged as a plurality of rows and a plurality of columns, wherein each of the plurality of rows is selectable via an address input to the memory array; and a control circuit configured to selectively invert data in the plurality of columns, wherein the memory array comprises an additional row of memory cells in the plurality of rows, and wherein the control circuit is configured to store a plurality of indications in the additional row of memory cells, wherein each of the plurality of indications corresponds to a respective column of the plurality of columns and indicates whether or not the data in the respective column is inverted whereby an inversion status of the data in the memory array is maintained on a column-by-column basis, and wherein the control circuit is configured to periodically modify the plurality of indications, and wherein each instance of the periodic modification of the plurality of indications changes only one of the plurality of indications corresponding to only one of the respective columns.