Patent ID: 8865553

Claim:
A method for structuring a dielectric material in a semiconductor component, the method comprising: producing a gate structure ( 4 ) on a semiconductor area ( 2 a ), the gate structure ( 4 ) having a gate insulation layer ( 4 b ), which is formed on the semiconductor area ( 2 a ), and an electrode layer ( 4 c ), which is formed on the gate insulation layer ( 4 b ), generating at least one dielectric layer over the gate structure ( 4 ); forming an etching mask ( 10 ) on the at least one dielectric layer, the etching mask ( 10 ) determining a lateral position and lateral size of a window opening ( 11 ) to be formed over the gate structure ( 4 ) in the at least one dielectric layer; etching the dielectric layer through the etching mask ( 10 ), using the electrode layer ( 4 c ) as a first etch stop material; etching the electrode layer ( 4 c ) using the gate insulation layer ( 4 b ) as a second etch stop material.