Patent ID: 8354315

Claim:
A fabrication method of a power semiconductor structure with schottky diode, comprising: a) forming a polysilicon layer including at least a polysilicon gate structure and a first polysilicon structure separated by a predetermined distance, on a silicon substrate, wherein the polysilicon gate structure is located in a gate trench on the silicon substrate; b) forming at least a body and at least a source region in the silicon substrate by implanting dopants through the first polysilicon structure, wherein the first polysilicon structure is located on an upper surface of the silicon substrate; c) forming a dielectric layer covering the polysilicon gate structure and the first polysilicon structure; d) forming an open, which is substantially aligned to the first polysilicon structure, in the dielectric layer to expose the silicon substrate below the body, and the open having a depth smaller than a greatest depth of the body; and e) filling a metal layer in the open.