Patent ID: 8522114

Claim:
A memory system comprising: a nonvolatile memory including a memory cell array and a read/write circuit configured to retrieve first read data stored in the memory cell array during a read operation; and a controller configured to receive the first read data from the nonvolatile memory, perform an error detection and correction operation on the first read data, wherein upon detecting an error in a received portion of the first read data, the controller is further configured to halt further transmission of the first read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the first read data to correct the detected error, and after correcting the detected error in the received portion of the first read data, resume transmission of the first read data from the nonvolatile memory, wherein the read/write circuit is configured to retrieve the first read data on a first unit basis, the controller performs the error detection operation on the received portion of the first read data on a second unit basis, and the first unit is larger than the second unit, wherein upon detecting an error, the controller is further configured to receive second read data from the nonvolatile memory corresponding to the detected error of the received portion of the first read data on a third unit basis, the second unit being larger than the third unit, and correct the detected error in the received second read data corresponding to the detected error, wherein the controller comprises an error correction block configured to detect whether the received portion of the first read data contains an error and activating a wait signal upon detecting an error in the received portion of the first read data, and a state machine configured to halt the transmission of the first read data in response to the wait signal, wherein the error correction block is further configured upon detecting an error in the received portion of the first read data to provide error position information related to the detected error to the state machine, and the state machine is further configured to correct the detected error using the error position information, wherein the state machine is further configured following correction of the detected error to transmit a return control signal to the error correction block indicating correction of the detected error, and wherein the detected error includes a number of detected errors, and the error correction block is further configured to count a number of return control signal transmissions, and indicate when the counted number of return control signal transmissions is equal to the number of detected errors.