Patent ID: 7675441

Claim:
An analog-to-digital converter (ADC) system comprising: a plurality of component ADCs to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each component ADC being coupled to receive an associated gain correction signal that controls a magnitude of the digital representations therefrom; correction circuitry, coupled to the plurality of component ADCs, to generate a plurality of fast-Fourier transforms (FFTs) that correspond to the digital representations of the input signal and to generate the associated gain correction signal for each of the component ADCs based on variations between the magnitudes of corresponding digital representations of the component ADCs as indicated by the FFTs; and a timing signal generator to generate the timing signals and having a timing correction input to receive a plurality of timing control values from the correction circuit, each timing control value to control a phase angle of a corresponding one of the timing signals, and wherein the correction circuit is configured to adjust the timing control values based on phase variations indicated by the FFTs.