Patent ID: 7873101

Claim:
A digital filter, comprising a symbol buffer having p−1 storage locations for storing arriving symbols, a coefficient memory having p−1 storage locations; a counter for counting from k=0 to p−1; a multiply and accumulate (MAC) block for multiplying and accumulating C(k)*S(n−k) from said storage locations of said symbol buffer and said coefficient memory; said counter providing control signals to cause said MAC block to calculate, ∑ k = 1 k = p - 1 ⁢ C ⁡ ( k ) * S ⁡ ( n - k ) between the arrival of the (n−1) th and n th symbols; and, upon arrival of the n th of said symbols, calculating Y ⁡ ( n ) = ∑ k = 0 k = p - 1 ⁢ C ⁡ ( k ) * S ⁡ ( n - k ) ; and wherein each location of said symbol buffer and said coefficient memory each store two real values; and wherein said counter further provides control signals to cause said MAC block to calculate, ∑ k = 1 k = p - 1 ⁢ C ⁡ ( k + 8 ) * S ⁡ ( n - 8 - k ) between the arrival of the n−1 th and n th of said symbols; between the arrival of the n−1 th and n th of said symbols; and upon arrival of the n th of said symbols, calculates Y ⁡ ( n ) = ∑ k = 0 k = p - 1 ⁢ S ⁡ ( n - k - 8 ) * C ⁡ ( k + 8 ) .