Patent ID: 8396179

Claim:
A frame synchronizing device for a binary data transmission system wherein digital data are transmitted as a serial bit stream organized into frames, each frame including a pre-defined frameheader, the device comprising: a serial input parallel output shift register for receiving said serial bit stream and outputting said frames in a consecutive order, said shift register including a serial input portion and a parallel output portion and having at least as many stages as the number of bits of a frame, first clock circuitry that generates first clock pulses, separated by a first time period, for clocking the serial input portion of the shift register; second clock circuitry that generates second clock pulses for clocking the parallel output portion of the shift register, the second clock circuitry generating the second clock pulses responsive to the first clock pulses, and control circuitry for detecting whether or not a frameheader is present at the output of said parallel output portion and, if not, controlling said shift register so that the clocking of the parallel output portion is delayed by at least the first time period, the control circuitry delaying the clocking of the parallel output portion by preventing one of the first clock pulses from reaching the second clock circuitry.