Patent ID: 7902877

Claim:
An apparatus, comprising: clock circuitry generating a plurality of clock signals having an odd number of clock signals being three or more, the plurality of clock signals having a common frequency, and a phase delay corresponding to the odd number of clock signals evenly separating the first plurality of clock signals; a plurality of latches connected in series, wherein adjacent latches of the series are connected such that an output of a preceding latch of the adjacent latches in the series is connected to an input of a following latch of the adjacent latches in the series, the plurality of latches being clocked by the plurality of clock signals and inverted versions of the plurality of clock signals such that half of the phase delay separates clock signals of the preceding latch and the following latch of the adjacent latches in the series; combinational logic coupled to outputs of the plurality of latches, the combinational logic generating pulses at a rate of two times the odd number of clock signals times the common frequency of the plurality of clock signals.