Patent ID: 7325100

Claim:
A processing system for entering and exiting low power mode comprising: a processor having a cache; a power management means connected to said processor for controlling a plurality of power management states, at least one of said power management states being a low latency low power state; a memory subsystem including a self sustaining mechanism connected to said processor for retaining data during said low power state; a pre-fetching means in said memory subsystem for loading instructions into a cache prior to entering said low power state; a disabling mechanism in said processor for disabling any interrupts that may disturb said pre-fetched instructions; an enabling means in said memory subsystem for initiating the self sustaining operation of said memory subsystem; a detecting means connected to said processor for sensing a trigger to exit from said low power state; and a restoring means in said power management mechanism for restoring the clock of said apparatus; thereby said processor disabling said self sustaining operation and resuming normal operation at the end of said low power state.