Patent ID: 8860652

Claim:
A shift register comprising: a plurality of successively cascaded shift register units, each controlled by a first clock signal to generate an output signal at an output node, wherein the output signals generated by the cascaded shift register units are enabled successively, and each of the shift register units comprises: a first switch having a control terminal coupled to a first node, an input terminal receiving the first clock signal, and an output terminal coupled to the output node; a second switch having a control terminal, an input terminal coupled to the control terminal of the second switch, and an output terminal coupled to the first node; a third switch having a control terminal coupled to the first node (N 1 ), an input terminal receiving the first clock signal, and an output terminal; a first capacitor coupled between the output terminal of the third switch and the first node; a fourth switch having a control terminal, an input terminal coupled to the first node, and an output terminal coupled to a low voltage terminal; and a second capacitor coupled between the output node and a ground terminal, wherein for a current shift register unit among the shift register units, the control terminal of the second switch receives the output signal generated by previous shift register unit to the current shift register unit.