Patent ID: 8793640

Claim:
A method for extracting a capacitance from a layout of an integrated circuit (IC), comprising: receiving a computer file of a layout by a computer, wherein the layout comprises a first net and a second net; decomposing by a processing unit of the computer, the first net into a first component and a second component; decomposing by the processing unit of the computer, the second net into a third component and a fourth component; testing a first condition for the first component and the third component to obtain a first condition result; obtaining a first capacitance for the first component and the third component by a first method based on the first condition result; testing the first condition for the second component and the fourth component to obtain a second condition result; testing a second condition, based on the second condition result, for the second component and the fourth component to obtain a third condition result; obtaining a second capacitance for the second component and the fourth component by a second method different from the first method based on the third condition result; and determining by a computing unit of the computer, a net capacitance of the first net and the second net based on the first capacitance and the second capacitance.