Patent ID: 7990752

Claim:
A semiconductor memory comprising: a first main bit line; a pair of bit lines comprising the first main bit line and a first sub-bit line; a first word line extended in a direction crossing a direction of extension of the first main bit line; a first resistive memory element which comprises a first terminal and a second terminal, the first terminal being connected with the first main bit line; a first select transistor which comprises a first current path and a first gate electrode connected with the first word line, a first end of the first current path being connected with the second terminal of the first resistive memory element, and a second end of the first current path being connected with the first sub-bit line; a pair of bit lines comprising the first main bit line and a second sub-bit line; a second word line extended in a direction crossing the direction of extension of the first main bit line; a second resistive memory element which comprises a third terminal and a fourth terminal, the third terminal being connected with the first main bit line; and a second select transistor which comprises a second current path and a second gate electrode connected with the second word line, a first end of the second current path being connected with the fourth terminal of the second resistive memory element, and a second end of the second current path being connected with the second sub-bit line.