Patent ID: 8644081

Claim:
A flash memory device, comprising: a memory cell array, comprising a plurality of memory cells, and electrically connected to a plurality of word lines and a plurality of bit lines; a row decoder, for driving a specific word line among the word lines during an enabling period; a first page buffer, for sequentially driving a first to an N th bit lines among the bit lines during the enabling period, so as to program the memory cells electrically connected to the specific word line and the first page buffer, wherein N is an integer equal to or greater than 3; and a second page buffer, for sequentially driving an (N+1) th to a (2*N) th bit lines among the bit lines during the enabling period, so as to program the memory cells electrically connected to the specific word line and the second page buffer, wherein one of an (i−1) th bit line and an (i+1) th bit line is not driven when an i th bit line is not driven, and i is an integer and 1<i<2*N.