Patent ID: 7012339

Claim:
A semiconductor device, comprising: a semiconductor substrate which includes a first region that includes a plurality of circuit element connection pads, and a second region that surrounds the first region; a plurality of first external terminals which are arranged over the first region; a plurality of second external terminals which are arranged over the second region; a plurality of first wiring structures which are formed over the first region, and electrically and individually connect a plurality of the first external terminals and a first predetermined number of the circuit element connection pads; a plurality of second wiring structures which are formed from the first region to the second region, and electrically and individually connect a plurality of the second external terminals and a second predetermined number of the circuit element connection pads; a passive element which is disposed over the second region, and which is electrically connected to one of the second wiring structures; wherein; each of the first wiring structures includes a first redistribution wiring layer which is electrically and individually connected to one of the first predetermined number of the circuit element connection pads, and a first post electrode which electrically and individually connects the first redistribution wiring layer and the one of the first external terminals; each of the second wiring structures includes a second redistribution wiring layer which is formed ranging from the first region to the second region and is electrically and individually connected to one of the circuit element connection pads, and a second post electrode which electrically and individually connects the second redistribution wiring layer and one of the second external terminals; and the passive element is electrically connected to one of the second redistribution wiring layer; and wherein; the passive element is a capacitor which includes an upper electrode, a lower electrode and a dielectric film which is placed between the upper electrode and the lower electrode; and the upper electrode is electrically connected to one of the second redistribution wiring layer, and the lower electrode is electrically connected to another of the second redistribution wiring layer.