Patent ID: 7124231

Claim:
An intermediate device configured to receive data from one or more target devices located over a split transaction bus and to return the data in a predetermined order to one or more sources, the intermediate device comprising: (a) split transaction bus logic that couples the intermediate device to the split transaction bus; and (b) a DMA controller coupled to both the split transaction bus logic and the one or more sources, including: (i) a first control logic that issues requests for data to the split transaction bus logic and returns their corresponding responses in a predetermined order to the one or more sources; and (ii) a response memory that stores responses received by the split transaction bus logic, wherein the first control logic comprises: (a) a tag counter that generates an identification number for each request issued by the first control logic; (b) a wrap-around detector that prevents the first control logic from concurrently issuing more than a predetermined number of requests; and (c) a response counter that generates a sequence of values indicative of the order in which the first control logic retrieves responses from the response memory.