Patent ID: 7537973

Claim:
A method for fabricating a TFT array, comprising: providing a substrate having a gate electrode layer, a gate insulating layer and a silicon layer formed thereon; patterning the gate electrode layer, the gate insulating layer and the silicon layer to define a gate area, a gate line and a gate line wiring area; forming a passivation layer on the whole substrate; patterning the passivation layer to form at least two contact holes in the passivation layer over the silicon layer of the gate area, and to remove a portion of the passivation layer above the gate line and the passivation layer above the gate line wiring area; forming an ion implanting layer and a metal layer on the whole substrate; patterning the ion implanting layer and the metal layer to form a source region, a drain region, a data line, a data line wiring area and a second layer of the gate line wiring area; and forming a pixel electrode on the passivation layer, wherein the pixel electrode is electrically coupled to the drain region.