Patent ID: 7646223

Claim:
A phase locked loop circuit comprising: a capacitive element having a voltage level; a phase detecting and correcting unit configured to charge or discharge the capacitive element according to a phase difference between a phase of a reference clock and a phase of a feedback clock, and to correct the phase of the feedback clock using the voltage level of the capacitive element such that the phase of the reference clock and the phase of the feedback clock are synchronized with each other; a digital-to-analog converting unit configured to generate an analog voltage having a level according to a predetermined digital code and to charge the capacitive element with the analog voltage; a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal; a comparing unit configured to compare the level of the analog voltage and the voltage level of the capacitive element and to output a comparison signal; and a code setting unit configured to search the digital code when the level of the analog voltage is consistent with the voltage level of the capacitive element, using the comparison signal according to a power down signal, and to set the digital code in the digital-to-analog converting unit.