Patent ID: 7774558

Claim:
A device comprising: a first processor having an associated first cache and a second processor having an associated second cache; and a cache manager implemented in a hardware-logic and operable to: compare an execution of a given instruction group by the first processor while a first cache management policy is applied to the associated first cache and an execution of the given instruction group by the second processor while a second cache management policy is applied to the associated second cache, the execution of the given instruction group by the second processor initiated independently of the execution of the given instruction group by the first processor, wherein the first cache management policy assumes based on at least one of predicted information or historical information that the given instruction group will execute in a substantially optimal manner such that less than a preselected level of at least one error will occur during execution of the given instruction group and the second cache management policy assumes based on at least one of predicted information or historical information that the given instruction group will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the given instruction group; select from the first cache management policy and the second cache management policy a cache management policy likely to provide a substantially optimum execution of the given instruction group according to a preselected criterion; and associate in a recordable-type signal bearing medium the selected cache management policy with the given instruction group.