Patent ID: 7978560

Claim:
A semiconductor device comprising: a plurality of static memory cells, each of which has a first power supply node being a higher power supply node, a second power supply node being a lower power supply node and MOS transistors having gates and drains cross-coupled to each other; a first power supply line coupled to the first power supply nodes of the plurality of static memory cells; and a second power supply line coupled to the second power supply nodes of the plurality of static memory cells, wherein a first static memory cell is included in the plurality of static memory cells, and wherein a first potential supplied to the first power supply node of the first static memory cell, in case that the first static memory cell is written, is lower than a second potential supplied to the first power supply node of the first static memory cell, in case that the first static memory cell is read, the semiconductor device further comprising: a peripheral circuit to read from or write to the static memory cells; wherein an absolute value of a threshold voltage of a MOS transistor used in the peripheral circuit is smaller than an absolute value of a threshold voltage of MOS transistors having gates and drains cross-coupled to each other of the static memory cells.