Patent ID: 6878561

Claim:
A method of measuring an extent of misalignment between first and second layers of an integrated circuit, the method comprising: a. patterning first and second circuit features in the first layer; b. patterning a third circuit feature in the second layer, the third circuit feature designed to extend over the first circuit feature to create a first overlap area, wherein the first overlap area is a first intended overlap when the first and second layers are perfectly aligned in one dimension parallel to the layers, and wherein the first overlap area increases with misalignment in a positive direction along the dimension and decreases with misalignment in a negative direction along the dimension; c. patterning a fourth circuit feature in the second layer, the fourth circuit feature designed to extend over the first circuit feature to create a second overlap area, wherein the second overlap area is a second intended overlap when the first and second layers are perfectly aligned in the one dimension, and wherein the second overlap area decreases with misalignment in the positive direction and increases with misalignment in the negative direction; d. measuring a first resistance through the first overlap areas; and e. measuring a second resistance through the second overlap area.