Patent ID: 8415734

Claim:
A memory device, comprising: a substrate; a plurality of memory cells, each memory cell, of the plurality of memory cells, including: a first dielectric layer formed over the substrate, a charge storage layer formed over the first dielectric layer, the charge storage layer including a nitride, a second dielectric layer formed over the charge storage layer, and a control gate layer formed over the second dielectric layer; a plurality of source regions formed in the substrate, each source region, of the plurality of source regions, being formed adjacent to a first side of each memory cell of the plurality of memory cells; a plurality of drain regions formed in the substrate, each drain region, of the plurality of drain regions, being formed adjacent to a second side, of each of the plurality of memory cells, that is opposite the first side; a protection layer formed on: a top surface of each of the plurality of source regions, a top surface of each of the plurality of drain regions, the first dielectric layer of each of the plurality of memory cells, the charge storage layer of each of the plurality of memory cells, the second dielectric layer of each of the plurality of memory cells, and the control gate layer of each of the plurality of memory cells, the protection layer including oxynitride, and a thickness of the protection layer ranging from about 50 Å to about 150 Å; spacers formed: in contact with the protection layer, and on opposite sides of each of the plurality of memory cells; a third dielectric layer formed over each of the plurality of memory cells and the spacers, the third dielectric layer contacting: a top of surface of the control gate layer, of each of the plurality of memory cells, and a portion of the spacers; and a contact formed between each of the plurality of memory cells, the contact contacting the spacers and the third dielectric layer, and the contact not substantially contacting the plurality of memory cells.