Patent ID: 7172938

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a tunneling dielectric layer on a semiconductor substrate; forming a charge trapping layer on the tunneling dielectric layer; sequentially forming a first length defining layer and a second length defining layer on the charge trapping layer; forming a second length defining layer pattern, a first length defining layer first pattern, a charge trapping layer pattern, and a tunneling dielectric layer pattern by partially removing the second length defining layer, the first length defining layer, the charge trapping layer, and the tunneling dielectric layer; forming a first length defining layer second pattern by selectively etching sidewalls of the first length defining layer first pattern, thereby forming recessed regions therein and exposing a region of the charge trapping layer pattern; forming a charge blocking layer on the semiconductor substrate and on the exposed region of the charge trapping layer pattern; forming a gate layer overlying the resulting structure and filling the recessed regions with the gate layer; forming spacer shaped gates by etching the gate layer; selectively etching the second length defining layer pattern and the first length defining layer pattern; and forming a first dopant region between the gates, and forming a second dopant region outside the gates.