Patent ID: 8436865

Claim:
A memory controller for controlling a memory having areas of data unit of K bits, comprising: a data mapping unit dividing N bits of data, where N is not a multiple of K, into K bits and (N−K) bits, and in regard to L pieces of the N bits of data, arranging L K-bit data into L data units, and arranging L (N−K)-bit data into M(M=L×(N−K)/K) data units by packing; and an access control unit access-controlling the memory to access the L K-bit data as L data units, and access-controlling the memory to access the packed L (N−K)-bit data as M data units, wherein the access control unit stores the L K-bit data and the packed L (N−K)-bit data into consecutive (L+M) data unit areas in the memory.