Patent ID: 7153781

Claim:
A process for etching poly silicon gate stacks with a raised shallow trench isolation (STI) structure where the thickness of poly silicon gate stacks at the active area (AA) and STI are different, and wherein said poly silicon gate stacks comprise a gate silicide layer, a second poly silicon layer and a first poly silicon layer that overlie a gate oxide, the process comprising: a) etching said gate silicide layer and said second poly silicon layer thereby exposing a top surface of said first poly silicon layer; b) forming a continuous passivation layer on sidewalls of said silicide layer and second poly silicon layer and on the exposed top surface of said first poly silicon layer; c) affecting a breakthrough etch to clear the passivation layer on the exposed top surface of said first poly silicon layer while leaving intact said passivation layer on said sidewalls of said silicide layer and second poly silicon layer; and d) etching said first poly silicon layer with an oxide selective process to preserve the underlying thin gate oxide and to preserve the passivation layer at the sidewalls of said silicide layer and second poly silicon layer to obtain vertical profiles of poly silicon gate stacks both at the AA and the STI oxide.