Patent ID: 8514001

Claim:
A memory interface comprising: an input to receive an input signal; a phase-shift circuit coupled to the input to cause a phase shift in the input signal, the phase shift corresponding to a number of time steps, wherein a duration of the time steps depends at least in part on a frequency range associated with the input signal; and a phase comparison circuit to control the number of time steps based at least in part on a phase comparison between a reference clock signal and another clock signal, wherein the other clock signal is delayed by the phase shift, or a multiple of the phase shift, wherein the frequency range is one of multiple frequency ranges including a first frequency range and a second frequency range that is different from the first frequency range, and wherein the duration of the time steps is a first duration in response to the frequency range corresponding to the first frequency range and the duration of the time steps is a second duration that is different from the first duration in response to the frequency range corresponding to the second frequency range.