Patent ID: 7184480

Claim:
A digital pulse width modulated (PWM) circuit, comprising: a binary counter configured to receive a clock signal and generate a plurality of binary signals; a digital to analog converter (DAC) circuit configured to receive said plurality of binary signals and generate a plurality of ramp signals; a PWM comparator configured to compare said ramp signals and a DC signal and generate a PWM signal having a duty cycle based on the intersection of said ramp signals and said DC signal; and reset circuitry comprising a reset comparator configured to compare said ramp signals with a reference signal and generate an output signal, and a pulse shaper configured to receive said output signal from said comparator and generate a reset signal based on the comparison between said ramp signal and said reference signal; said reset circuitry is configured to reset said binary counter, using said reset signal, to control the frequency of said plurality of ramp signals and to control the duty cycle of said PWM signal.