Patent ID: 7073002

Claim:
An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a plurality of hardware resources coupled to the at least one processor; a plurality of locks residing in the memory, wherein each of the plurality of hardware resources has a corresponding lock; a plurality of logical partitions defined on the apparatus; a lock mechanism that controls access to each hardware resource by the plurality of logical partitions by requiring exclusive ownership of the corresponding lock before transferring control of the corresponding hardware resource to one of the plurality of logical partitions and before allowing one of the plurality of logical partitions to access the corresponding hardware resource; and a power on/power off mechanism residing in the memory and executed by the at least one processor, the power on/power off mechanism powering off a selected hardware resource when control of the selected hardware resource is removed from one of the plurality of logical partitions and powering on the selected hardware resource when control of the selected hardware resource is transferred to one of the plurality of logical partitions.