Patent ID: 7443911

Claim:
An apparatus comprising: a communication device having a first pin to receive a system clock frequency of a system and a second pin which, in connection with the first pin, is to receive a reference clock frequency or a system clock frequency from a crystal oscillator coupled to the communication device; a clock interface coupled to the first and second pins to receive the system clock frequency or the reference clock frequency; a phase-locked loop coupled to the clock interface to provide a plurality of internal clocks to drive multiple components of the communication device from the system clock frequency or the reference clock frequency; logic coupled to the phase-locked loop to control the phase-locked loop based on which one of the system clock frequency and the reference clock frequency is input into the communication device, wherein the logic is coupled to receive and analyze a clock selection input signal received in the apparatus during a first portion of a power on or reset state of the apparatus and to exclusively select the system clock frequency or the reference clock frequency based on a value of the clock selection input signal; and wherein an interconnect of the communication device is shared between the clock selection input signal and an output logic signal; and a driver is coupled to the interconnect, wherein the logic is to cause an output of the driver into a high-impedance state during the power on or reset state.