Patent ID: 7694156

Claim:
A cryptographic unit which, in faultless operation, processes an input signal into an encrypted output signal according to the round-based advanced encryption standard (AES) algorithm in a round i of the first to the next to last round of the AES algorithm and outputs the same and, in the case of a fault, does not output any encrypted output signal, comprising: a first processing unit designed to determine an encrypted output signal from the respective input signal in the corresponding round i of the first to the next to last round of the AES algorithm in subcircuits corresponding to the successive operations Subbyte, ShiftRows, MixColumns, AddRoundKey of the AES algorithm, and to process this output signal in a further subcircuit designed to execute an inverse MixColunms operation or a bitwise inverted inverse MixColumns operation to obtain a first comparison signal for the corresponding round i of the AES algorithm, wherein the respective round i is designated by the variable i and a cryptographic key to be used in the i-th round is designated by the variable k i ; a second processing unit designed to determine, from the input signal applied to the first processing unit in a round i of the first to the next to last round of the AES algorithm, a second comparison signal for the corresponding round i of the AES algorithm in subcircuits corresponding to the successive operations Subbytes, ShiftRows, and an addition operation of the inverse MixColumns operation of the operation AddRoundKey or a bitwise inverted inverse MixColumns operation of the operation, AddRoundKey, wherein, in a faultless operation of the cryptographic unit, the first comparison signal and the second comparison signal are related to each other in a predetermined relationship; and a release unit for providing the output signal, wherein the release unit is designed to perform a defense measure against a tapping of the output signal external to the cryptographic unit, when the first comparison signal is not related to the second comparison signal in the predetermined relationship.