Patent ID: 7897446

Claim:
A method of forming a semiconductor device on a semiconductor substrate including a protective dielectric layer disposed on the semiconductor substrate, the method comprising: forming drain and source ohmic vias in the protective dielectric layer; depositing ohmic metal into the drain and source ohmic vias to form drain and source contacts, including depositing the ohmic metal into predetermined portions of the drain and source ohmic vias so that ohmic vias gaps remain in the drain and source ohmic vias between the deposited ohmic metal and the protective dielectric layer; depositing metallizations in the ohmic vias gaps and on the drain and source contacts; forming a resist layer on the protective dielectric layer and on the metallizations in the ohmic via gaps and on the drain and source contacts; forming a resist opening in the resist layer; etching a predetermined portion of the protective dielectric layer via the resist opening to form a window in the protective dielectric layer; widening the resist opening so that a width of a lower portion of the resist opening is greater than a width of the window in the protective dielectric layer; depositing a metal film in the window and the resist opening; and lifting off the resist layer to form a T-gate and a field mitigating plate disposed at a side portion of the T-gate on the semiconductor substrate.