Patent ID: 7772652

Claim:
A semiconductor component arrangement comprising: a semiconductor layer formed on a semiconductor substrate, and an insulation and wiring region formed above the semiconductor layer, the semiconductor layer having dopants of a first conductivity type in a first concentration; further semiconductor zones formed within the semiconductor layer and having further dopants, the further semiconductor zones forming a power transistor in a first region of the semiconductor layer and further semiconductor components in a second region of the semiconductor layer, it being the case that a semiconductor structure having only the dopants in the first concentration, within the semiconductor layer, adjoins a further semiconductor structure at the underside of the semiconductor layer, which further semiconductor structure, below the first and second regions of the semiconductor layer has the first conductivity type and has a higher concentration of dopants in comparison with the first concentration, wherein the further semiconductor structure comprises a first buried layer formed in the first region and a second buried layer formed in the second region, the layer thickness of the second buried layer being smaller than the thickness of the first buried layer, and the first buried layer adjoining the second buried layer; a distance between the underside of the semiconductor structure and a horizontal reference level within the insulation and wiring region is smaller in the first region of the semiconductor layer than in the second region of the semiconductor layer; and a surface of the semiconductor layer adjoining the insulation and wiring region is flat along the first and second regions, respectively.