Patent ID: 8274133

Claim:
A semiconductor package, comprising: a substrate, having a first surface, a second surface, at least one groove and at least one via structure, the groove penetrating through the first surface and the second surface, the via structure disposed in the groove and exposed on the first surface and the second surface of the substrate; a first metal layer, disposed on the first surface of the substrate, and having a first lower electrode, the first metal layer directly contacting the via structure; a first dielectric layer, disposed on the first lower electrode; a first upper electrode, disposed on the first dielectric layer, wherein the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor; a first protective layer, encapsulating the first capacitor, the first protective layer having at least one first opening, part of the first upper electrode exposed on the first opening; a second metal layer, disposed on the first protective layer, and having a first inductor, the second metal layer directly contacting the first upper electrode; and a second protective layer, encapsulating the first inductor.