Patent ID: 6847245

Claim:
A latch circuit having a total current and at least one output, the output having a first distinct state and a second distinct state, the output being controllable by a first trigger signal and a second trigger signal, the latch circuit comprising: a SET circuit; a RESET circuit; wherein at least one of the conditions from the group consisting of the following is true: 1) at the first state, the total current is conducted by the SET circuit wherein the SET circuit switches when the first trigger signal is applied to the SET circuit and 2) at the second state, the total current is conducted by the RESET circuit wherein the RESET circuit switches when the second trigger signal is applied to the RESET circuit; wherein, the SET circuit includes a first latch transistor and a SET transistor, and the RESET circuit includes a second latch transistor and a RESET transistor; and wherein at least one of the conditions from the group consisting of the following is true: 1′) the base and emitter of the first latch transistor are coupled to the base and emitter of the SET transistor, respectively, and 2′) the base and emitter of the second latch transistor are coupled to the base and emitter of the RESET transistor, respectively.