Patent ID: 7093215

Claim:
A semiconductor circuit device comprising a cell in which MIS transistors are provided in a plurality of active areas surrounded by a trench isolation, wherein the cell comprises: a plurality of PMIS active areas each provided with a gate of at least one P-channel transistor and arranged in a channel length direction; and a plurality of NMIS active areas each provided with a gate of at least one N-channel transistor and arranged in a channel length direction, wherein the plurality of PMIS active areas and the plurality of NMIS active areas are located to face each other in a channel width direction, wherein the semiconductor circuit device is designed such that the ends of at least one plurality of active areas, facing the other plurality of active areas, are aligned substantially on a single straight line, the one plurality of active areas and the other plurality of active areas being the plurality of PMIS active areas and the plurality of NMIS active areas, and wherein the semiconductor circuit device is designed such that a distance between each of the PMIS active areas and each of the NMIS areas in the channel width direction is 0.8 μm or less.