Patent ID: 8607169

Claim:
An intelligent defect diagnosis method for manufacturing fab, comprising: receiving, by a processor, pluralities of defect data from at least one defect inspection tool, pluralities of design layouts generated from a profile design system, and pluralities of fabrication data produced in the fab; analyzing, by a processor, the defect data, design layouts, and the fabrication data, wherein the analyzing step further contains the following sub-steps: segmenting and grouping the design layouts into pluralities of multi-pattern group cells to construct Layout Pattern Group (LPG) cell based pattern groups; introducing the defect data; segmenting defect image into pluralities of defect and pattern contours; mapping the defect data to each multi-pattern group cells to form the LPG based defect composite pattern groups, and identifying the frequent failure defect layout pattern; performing coordinate conversion and image pattern match between image pattern contour and design layout for coordinate correction; fulfilling Critical Area Analysis (CAA) with defect contour, pattern contour or design layout polygon, and obtaining corresponding defect yield; classifying the defect type of defect data through defect image classification analysis; performing the pattern metrology analysis to create and measure pattern contour, defect contour, and obtain defect hot spot pattern; and integrating image pattern contours and defect contours and creating the full chip manufacturing contour pattern viewer, wherein the contour pattern viewer creating step and uploading step further comprises the following sub-steps: creating a blank full chip frame of a product with full chip layout size x and y dimension; converting pluralities of images into pluralities of pattern contours through image pattern segmentation and contour tracing and obtaining pluralities of layout polygons; performing pattern match for the defect image pattern contour, layout pattern polygon or simulation pattern polygon; obtaining correct coordinate and wafer, defect, LPG, scale information for the full chip frame of the image pattern contour or the defect contour; uploading every product's image pattern contour and defect contour onto its full chip frame with correct coordinate and wafer, defect, LPG, scale information; sorting every product's full chip frame with image pattern contour and defect contour based on wafer data layer, equipment, mask, metrology, process and Optical Proximity Correction (OPC); sorting every product's full chip frame with image pattern contour and defect contour based on legend mode equipment, defect classification, scale size, hot spot, LPG group and metrology data; generating image pattern contour zooming up and down function and full chip view function; generating scale ruler that can map onto full chip manufacturing contour pattern viewer; integrating every product's full chip frame with all image pattern contours and defect contours for review and measurement.