Patent ID: 7952383

Claim:
A semiconductor device comprising: a first terminal; an output buffer electrically coupled to the first terminal; a signal generator generating an impedance adjustment signal; a through rate setting circuit generating a through setting signal irrespective of the impedance adjustment signal; and a control circuit receiving impedance adjustment and the through rate setting signal, adjusting an impedance of the output buffer to one of first and second impedance in response to the impedance signal, adjusting a through rate, at which the output buffer drives the first terminal to one of first and second logic levels, to one of first and second through rates in response to the impedance adjustment signal and the through rate, setting signal, wherein the control circuit operates first and second operations, the control circuit in the first operation sets the impedance to the first impedance which is greater than a designed impedance and sets the through rate to the first through rate which is less than a designed through rate, and the control circuit in the second operation sets the impedance to the second impedance which is less than the designed impedance and sets the through rate to the second through rate which is greater than the designed through rate.