Patent ID: 8522189

Claim:
A system on a chip (SoC), comprising: an interconnect fabric, configured to support communication between components coupled thereto; a test interface configured to facilitate communication between an external tester and the SoC; a test controller, communicatively coupled to the interconnect fabric and the test interface; a plurality of intellectual property (IP) blocks, operatively coupled to the interconnect fabric; and a first test wrapper; communicatively coupled to each of the interconnect fabric and a first IP block; wherein, in response to receiving tester input the test controller is configured to generate a test package comprising test data and/or test commands corresponding to the tester input and to transmit the test package to the first test wrapper via the interconnect fabric, wherein, in response to receiving the test package the first test wrapper is configured to provide corresponding test input data, control and/or stimulus signals to the first IP block to perform one or more test operations on circuitry in the first IP block, and wherein during normal operation, the SoC is configured to facilitate communication between the plurality of IP blocks via the interconnect fabric a plurality of test wrappers, each test wrapper communicatively coupled to the interconnect fabric and a respective IP block; wherein each of the test wrappers is configured to receive test packages from the test controller via the interconnect fabric and provide corresponding test input data, control and/or stimulus signals to the IP block to perform one or more test operations defined by the test packages on circuitry in the IP block.