Patent ID: 8363484

Claim:
A memory device comprising: an array of memory cells, each memory cell being configured to support writing and simultaneous reading of that memory cell; write circuitry configured, during a write operation, to provide write data to a number of addressed memory cells within the array; word line select circuitry, responsive to a start of the write operation, to assert a write word line signal to enable said number of addressed memory cells to store said write data; and comparing circuitry configured, during the write operation, to compare said write data with data currently stored in said number of addressed memory cells; the comparing circuitry being responsive to detecting that said write data matches the data currently stored in said number of addressed memory cells, to assert a control signal to the word line select circuitry to cause the word line select circuitry to de-assert said write word line signal; whereby a pulse width of the asserted write word line signal is dependent on time taken by the number of addressed memory cells to store said write data.