Patent ID: 7408212

Claim:
An integrated circuit comprising: a first array of memory cells, each memory cell in the first array comprising a resistive element and a Schottky diode coupled in series and having first and second terminals, the resistive element being formed by a single layer of material, the Schottky diode being formed by two layers, the single layer for the resistive element and the two layers for the Schottky diode being stacked together; a first plurality of bit lines, one bit line for each column of the first array, each bit line coupled to the first terminal of memory cells in a respective column of the first array; and a first plurality of word lines, one word line for each row of the first array, each word line coupled to the second terminal of memory cells in a respective row of the first array wherein the resistive element for each memory cell is formed by a perovskite material.