Patent ID: 7888738

Claim:
A microelectronic structure including a conductive element contacting a bulk semiconductor region of a substrate, the bulk semiconductor region being separated from a semiconductor-on-insulator (“SOI”) layer of the substrate by a buried dielectric layer, the microelectronic structure comprising: a trench isolation region overlying the buried dielectric layer, the trench isolation region sharing an edge with the SOI layer; a conformal layer overlying the trench isolation region, the conformal layer having a top surface and an opening defining a wall extending from the top surface towards the trench isolation region, the top surface including a lip portion adjacent to the wall; and a dielectric layer overlying the top surface of the conformal layer, wherein the conductive element is in conductive communication with the bulk semiconductor region, the conductive element consisting essentially of at least one of a semiconductor, a metal, and a conductive compound of a metal and extending through the dielectric layer, the opening in the conformal layer, the trench isolation region, and the buried dielectric layer, and the conductive element contacting the lip portion, and wherein the opening has a first width, the conductive element has a second width greater than the first width, the conductive element contacts the lip portion at locations adjacent to left and right edges of the opening, the right edge being opposite the opening from the left edge.