Patent ID: 7084506

Claim:
A semiconductor device comprising a plurality of memory cells each of which comprises a first inverter including a first load transistor and a first driver transistor, a second inverter including a second load transistor and a second driver transistor, a first transfer transistor for controlling the first inverter and the second inverter, and a second transfer transistor for controlling the first inverter and the second inverter; a logic block forming a logical circuit, based data set in said plurality of memory cells; and an interconnection region connected to the logic block, the semiconductor device comprising: a first gate interconnection including the gate electrode of the first load transistor and the gate electrode of the first driver transistor, the first gate interconnection being formed linearly and reached to a vicinity of the source/drain diffused layer of the second load transistor; a second gate interconnection including the gate electrode of the second load transistor and the gate electrode of the second driver transistor, the second gate interconnection being formed linearly and reached to a vicinity of the source/drain diffused layer of the first load transistor; a third gate interconnection including the gate electrode of the first transfer transistor, the third gate interconnection being positioned on an extension of the second gate interconnection; a fourth gate interconnection including the gate electrode of the second transfer transistor, the fourth gate interconnection being positioned on an extension of the first gate interconnection; a first conductor plug contacting the first gate interconnection and the source/drain diffused layer of the second load transistor; and a second conductor plug contacting the second gate interconnection and the source/drain diffused layer of the first load transistor, one of the source/drain diffuse layer of the first transfer transistor, and one of the source/drain diffused layer of the first driver transistor being formed of the common source/drain diffused layer.