Patent ID: 8397133

Claim:
A memory device comprising: a first wordline for transmitting a first wordline control signal when the first wordline is asserted; a second wordline for transmitting a second wordline control signal when the second wordline is asserted; a first memory element comprising a first memory cell, wherein the first memory cell comprises: a first transistor having a first control terminal coupled to receive the first wordline control signal from the first wordline; a second transistor having a second control terminal coupled to receive the second wordline control signal from the second wordline, wherein the first transistor and the second transistor are operable to both activate when both the first wordline and the second wordline are asserted; a bit cell coupled to the first transistor and the second transistor such that the bit cell is accessible to write a bit into the bit cell when the first transistor and the second transistor are both activated and to hold the bit in the bit cell when one or more of the first transistor and the second transistor are deactivated; and a second memory element; wherein the first and second memory elements are redundant to each other.