Patent ID: 7379331

Claim:
A nonvolatile semiconductor memory comprising: a cell array comprising a plurality of memory cells; a redundancy array comprising a plurality of redundant cells configured to replace the memory cells; an erase circuit which performs an erase operation on a target cell including one of the memory cell and the redundant cell; a timer which measures a time elapsed from start of the erase operation performed for the target cell by the erase circuit; a controller which stops the erase operation and replaces the target cell with the redundant cell, when detecting that a predetermined time has elapsed from the start of the erase operation by the measurement of the elapsed time by the timer; a storage circuit which is formed for each redundant cell, and stores an address, replacement enable information, and replacement disable information, the address being an address of the memory cell replaced with the redundant cell, the replacement enable information indicating that the redundant cell is used in replacement, and the replacement disable information indicating that the redundant cell is disabled for replacement; a write circuit which writes the address, the replacement enable information, and the replacement disable information in the storage circuit; and a read circuit which reads out the address, replacement enable information, and replacement disable information stored in the storage circuit, wherein the control circuit checks whether an unused redundant cell exists by causing the read circuit to read out the replacement enable information and replacement disable information stored in the storage circuit, if the unused redundant cell exists, checks whether the target cell for which the predetermined time has elapsed from the start of the erase operation is an already replaced redundant cell, if the target cell is a replaced redundant cell, writes the replacement disable information in the storage circuit which corresponds to the redundant cell, and writes an address and replacement enable information of the target cell in the storage circuit which corresponds to the unused redundant cell.