Patent ID: 7250339

Claim:
A manufacturing method of a memory device, comprising: providing a substrate comprising a memory cell area and a peripheral circuit area, wherein the peripheral circuit area comprises a high operational voltage component area and a low operational voltage component area; forming a tunnel layer and an inter-gate dielectric layer over a surface of the substrate in the memory cell area respectively, and forming a first inter-gate dielectric layer and a second inter-gate dielectric layer on a surface of the substrate of the high operational voltage component area and the low operational voltage component area of the peripheral circuit area respectively; forming a doped region used as a control gate in the substrate under the inter-gate dielectric layer; forming a floating gate over the inter-gate dielectric layer and the tunnel layer of the memory cell area, and forming a first gate and a second gate over the first inter-gate dielectric layer and the second inter-gate dielectric layer of the peripheral circuit area respectively; and forming a first source region and a first drain region in the substrate on two sides of the floating gate under the tunnel layer of the memory cell area, and forming a second source region and a second drain region in the substrate on two sides of the first gate of the peripheral circuit area, and forming a third source region and a third drain region in the substrate on two sides of the second gate of the peripheral circuit area.