Patent ID: 7372750

Claim:
An integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and comprising: a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising: an error memory for storing an item of repair information; and an assignment unit in order, when accessing an address of the memory cell array, depending on the repair information, to access either a memory area of the memory cell array or a redundancy memory area, and a test unit for determining the repair information, the test unit comprising: a write unit, which successively writes first test data and second test data to a plurality of memory cells of a memory area of the memory cell array; a read-out unit which reads out data stored in the memory area; a modification unit in order to modify the bits of the read-out data to provide the second test data, which are subsequently written to the memory area by the write unit, and a comparator unit in order to compare the data read out after the writing of the second test data with expected data and to provide the repair information depending on the comparison result.