Patent ID: 7952392

Claim:
A logic circuit comprising: a depletion transistor having a gate, a source, and a drain, an enhancement transistor having a gate, a source, and a drain, a first terminal electrically connected to the gate of the enhancement transistor; and a second terminal electrically connected to a portion where the enhancement transistor is connected to the depletion transistor, wherein a high power supply voltage terminal is electrically connected to one of the source and the drain of the depletion transistor, and the gate of the depletion transistor is electrically connected to the other of the source and the drain of the depletion transistor; wherein one of the source and the drain of the enhancement transistor is electrically connected to the other of the source and the drain of the depletion transistor, and a low power supply voltage terminal is electrically connected to the other of the source and the drain of the enhancement transistor, wherein each of the depletion transistor and the enhancement transistor includes: a gate electrode; a gate insulating layer provided over the gate electrode; a first oxide semiconductor layer provided over the gate insulating layer; a source region and a drain region in contact with part of the first oxide semiconductor layer, wherein the source region and the drain region are second oxide semiconductor layers; a source electrode in contact with the source region; and a drain electrode in contact with the drain region, wherein the enhancement transistor includes a reduction prevention layer over the first oxide semiconductor layer, the source electrode, and the drain electrode, and wherein the depletion transistor does not include a reduction prevention layer over the first oxide semiconductor layer, the source electrode, and the drain electrode.