Patent ID: 8775771

Claim:
A block management method for managing a plurality of physical blocks of a flash memory chip, the block management method comprising: configuring a plurality of logical addresses; mapping the logical addresses to a plurality of logical blocks, and mapping the logical blocks to the physical blocks; configuring a logical block-physical block mapping table to record mapping relationships between the logical blocks and the physical blocks; obtaining at least one deleting record from a host system, wherein the at least one deleting record has information about deleted logical addresses among the logical addresses and the host system marks data stored at the deleted logical addresses as invalid data in a file allocation table; obtaining a deleted logical block among the logical blocks based on the at least one deleting record, wherein data stored at the deleted logical addresses of the deleted logical block is recognized as invalid data by the host system; and marking each of the logical address mapped to the deleted logical block as a bad logical address in the file allocation table, wherein according to the file allocation table, the bad logical addresses are not used for writing data anymore by the host system.