Patent ID: 7561394

Claim:
A system for overvoltage protection comprising: a controller for detecting a voltage in excess of an upper threshold voltage value and a voltage less than a lower threshold voltage value, the controller comprising a logic circuit; a plurality of switches independently controlled by the control circuit; and a plurality of resistors configured to define a load resistance, each resistor in the plurality of resistors being connected to a corresponding switch in the plurality of switches whereby each resistor in the plurality of resistors is connected by its corresponding switch to combine in a manner directed by the control circuit that defines the load resistance necessary to maintain a voltage to a level below a maximum safe value; wherein the logic circuit comprises: a voltage to be monitored; a first comparator having a first input receiving the voltage to be monitored and a second input receiving the upper threshold voltage value, the first comparator providing an upper threshold voltage detected signal upon detecting a voltage in excess of the upper threshold voltage value; a second comparator having a first input receiving the voltage to be monitored and a second input receiving the lower threshold voltage value, the second comparator providing a lower threshold voltage detected signal upon detecting a voltage below the lower threshold voltage value; a binary counter having a reset input, a clock input and a plurality of counter outputs, each output in the plurality of outputs corresponding to each switch in the plurality of switches; and logic control circuitry having an input receiving the lower threshold voltage signal, an input from a clock source and an input representing a present count, the logic control circuitry having an output to the binary counter clock input; wherein the binary counter is set to an initial count upon receiving the upper threshold voltage detected signal at the reset input, the initial count closes all of the switches in the plurality of switches, thereby decreasing the load resistance defined by the plurality of resistors in combination and dissipating power due to the upper threshold value being exceeded; wherein the binary counter adjusts the present count toward a final count upon receiving the lower threshold voltage signal at the clock input and provides a modified resistor combination for each consecutive count between the initial count and the final count, and wherein upon reaching the final count and all of the switches in the plurality of switches being open, the binary counter stops counting.