Patent ID: 7615991

Claim:
A method for measuring an analog channel resistance of a semiconductor device having a gate, a source, a source sense coupled to the source, a drain, and a drain sense coupled to the drain, the method comprising: setting a measuring condition including at least one bias voltage; measuring a first drain current by applying a first voltage to the drain after applying the at least one bias voltage of the measuring condition; measuring a first voltage difference of the drain sense and the source sense under the condition that currents of the source sense and the drain sense are constrained to zero Ampere; measuring a second drain current by applying a second voltage to the drain after applying the at least one bias voltage of the measuring condition; measuring a second voltage difference of the drain sense and the source sense under the condition that currents of the source sense and the drain sense are constrained to zero Ampere; and measuring the analog channel resistance by calculating a ratio of a voltage drop between the first and second voltage difference, and a current difference between the first and second drain currents.