Patent ID: 8828867

Claim:
A method for manufacturing integrated circuits comprising: providing a semiconductor substrate; defining a plurality of contact regions on the semiconductor substrate; forming at least one dielectric structure on the plurality of contact regions; forming a plurality of openings on the semiconductor substrate, each of the openings being characterized by at least a depth, a width, and an aspect ratio; performing deposition within the openings using a titanium material; forming, within the openings, an insulating material on the titanium material; annealing the titanium material using a temperature range of 500 to 600 degrees Celsius and an oxygen concentration range of 141 to 1,000 parts per million, the annealing causing oxidation of the top surface of the titanium material to form a barrier configured to prevent silicon from diffusing through the titanium material; and forming metal contacts by filling a tungsten material into the plurality of openings, the metal contacts being associated with a low resistance value.