Patent ID: 8604838

Claim:
An apparatus comprising: a CMOS sense amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first output circuit having a first load capacitance; a second output circuit having a second load capacitance; and an isolation circuit that is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and that is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier, wherein the isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier, wherein the CMOS sense amplifier is controlled by a clock signal, and wherein the isolation circuit further comprises: a plurality of precharge circuit that are each coupled to the first and second load capacitances, respectively, and that are controlled by the clock signal; wherein a.) the gates of the precharge circuits are coupled together, and b.) the sources of the precharge circuits are not shorted through an intermediate switch also driven by the clock signal; a first isolation element that is coupled between the first output terminal of the CMOS sense amplifier and the first inverter; and a second isolation element that is coupled between the second output terminal of the CMOS sense amplifier and the second inverter.