Patent ID: 6867447

Claim:
A semiconductor device, comprising: a ferroelectric memory cell array comprising a plurality of ferroelectric memory cells for storing data, the cell data being accessible along a plurality of bitlines, the cells being operated according to a plurality of plateline signals and a plurality of wordline signals, the ferroelectric memory cells individually comprising: a ferroelectric cell capacitor structure formed in a capacitor layer above a semiconductor body, the ferroelectric cell capacitor structure comprising a first conductive electrode electrically coupled with a plateline, a second conductive electrode, and a ferroelectric material formed between the electrodes; and a cell transistor comprising a gate electrically coupled with a wordline, a first source/drain electrically coupled with the second conductive electrode and a second source/drain electrically coupled with a bitline; and a plurality of conductive bitline structures extending from beneath the capacitor layer to a layer above the capacitor layer, individual conductive bitline structures passing through the capacitor layer proximate a corner of at least one of the ferroelectric cell capacitor structures.