Patent ID: 8531226

Claim:
An apparatus, comprising: an n-channel metal-oxide-semiconductor field effect transistor (MOSFET) device, the n-channel MOSFET device being a vertical MOSFET device having a drain on a bottom portion of the n-channel MOSFET device and having a source pad on a top portion of the n-channel MOSFET device; a p-channel MOSFET device having a drain on a bottom portion of the p-channel MOSFET device and having a source pad on a top portion of the p-channel MOSFET device; a first lead frame portion defining a first polarity insensitive input, the drain of the n-channel MOSFET device and the drain of the p-channel MOSFET device both being disposed on the first lead frame portion; a voltage limiter circuit disposed on top of the source pad of the n-channel MOSFET between the source pad and a gate pad of the n-channel MOSFET device, the voltage limiter circuit including a zener diode and a polysilicon resistor; a second lead frame portion defining a second polarity insensitive input coupled to the gate bad of the n-channel MOSFET device via a first wire interconnect, the zener diode, the polysilicon resistor and the n-channel MOSFET all being electrically connected to the second polarity insensitive input via the first wire interconnect and via the gate pad of the n-channel MOSFET device, the n-channel MOSFET device having a gate dielectric rating greater than twenty-five volts; and a third lead frame portion defining a fixed polarity output coupled to the source pad of the n-channel MOSFET device via a second wire interconnect.