Patent ID: 8725955

Claim:
A processor chip coupled to a shared memory, the processor chip comprising: an MP core (main processor core); an AP core (application processor core) configured to perform a processing function designated by a control of the MP core; a first SM controller configured to set a path such that the MP core is coupled with the shared memory; a second SM controller configured to set a path such that the AP core is coupled with the shared memory; and a command transfer unit configured to transfer command information or authorization information from one of the MP core and the AP core to the other, wherein the command transfer unit comprises a storage area for storing an identification code corresponding to the command information or the authorization information, wherein the identification code identifies which of the MP core and the AP core to output request information for accessing the shared memory, wherein the command transfer unit transfers the request information from one of the MP core and the AP core to the other when a request by one of the MP core and the AP core desiring access to a common area of the shared memory is written in the storage area of the command transfer unit, wherein upon receipt of the request, the other of the MP core and the AP core completes access to the common area, and transfers the access to the common area back to the one of the MP core and the AP core desiring the access to the common area using the storage area of the command transfer unit, and wherein the one of the MP core and the AP core desiring the access to the common area recognizes end of the access to the common area by the other of the MP core and the AP core by a pre-designated code value written in the storage area of the command transfer unit.