Patent ID: 7483033

Claim:
A storage device comprising: a memory array including a plurality of memory blocks, each of which includes plural lines of cells in correspondence with a data length; a first register for storing a first address representing a first cell within a region for storing a specific number of data each having a same value; an adder for adding run-length data representing the specific number of the data each having the same value to the first address so as to produce a second address; a second register for storing the second address; a counter for supplying a write address designating a cell of the memory array subjected to a write operation; a multiplexer for outputting the write address supplied from the counter to the memory array when performing the write operation and for outputting a read address to the memory array when performing a read operation; and a controller for selecting a certain number of the cells within a line designated by the write address based on the first address and the second address within the memory array to be simultaneously placed in a write-enable state, wherein, when the region for storing the specific number of data, which are specified by the first address and the second address, lies in two or more lines of the cells, the counter increases the write address from a first write address to a second write address during execution of the write operation for writing the data into the region, the controller changes the cells, which are simultaneously placed in the write-enable state, from a first number of cells designated by the first write address within a first line to a second number of cells designated by the second write address within a second line.