Patent ID: 8391402

Claim:
An encoder comprising a first and a second input which are to be connected to an electrical conductor of a less significant bit and to an electrical conductor of a more significant bit, respectively; a first and a second output which are to be connected to an electrical conductor of a less significant bit and to an electrical conductor of a more significant bit, respectively; a selection block suitable for selecting a transition of the more significant bit and a transition of the less significant bit, each between a clock cycle t−1 and a clock cycle t, the two transitions being spatially inverted on the electrical conductors of the less significant bit and of the more significant bit, said transitions comprising a passage between clock cycle t−1 and clock cycle t from a bit value of 0 to 1 on one electrical conductor among said electrical conductors of the less significant bit and of the more significant bit and a passage between said clock cycle t−1 and clock cycle t from a bit value of 1 to 0 on the other electrical conductor among said electrical conductors; a switching block suitable for connecting the first input to the first output, and the second input to the second output, and for being switched in order to connect the first input to the second output and the second input to the first output when the selection block has selected the two transitions being spatially inverted; and means for transmitting a warning signal of an inverted bit transmission.