Patent ID: 8912666

Claim:
A chip package comprising: a substrate; a die having a first side coupled to the substrate, in which a first opening through the substrate exposes the first side of the die, and the die comprises a first conductive layer, a second conductive layer and a passivation layer at the first side of the die, in which a second opening in the passivation layer exposes a first contact point of the first conductive layer, and the first contact point is exposed by the second opening, the second conductive layer is coupled to the first contact point through the second opening, and the second conductive layer has a second contact point exposed by the first opening; an adhesive material between the substrate and the first side of the die; a conductive interconnect coupled to the die on the second contact point through the first opening; a dielectric material coupled to the passivation layer on the first side of the die; and a molding material directly coupled to the die and directly coupled to the substrate.