Patent ID: 7507656

Claim:
A method for forming a low K dielectric layer, the method comprising: providing a substrate; forming a layer of transistor elements overlying the substrate; forming a first interlayer dielectric layer overlying the layer of transistor elements; forming a first etch stop layer overlying the first interlayer dielectric layer; patterning the first interlayer dielectric layer to form a contact structure; filling the contact structure with metallization; forming a thickness of a first sacrificial layer overlying the contact structure and overlying the first etch stop layer; forming a first metal layer overlying the thickness of the first sacrificial layer and the first etch stop layer, the first metal layer including an interconnect structure and coupled to the contact structure, and the first metal layer directly contacting the first sacrificial layer; selectively removing the thickness of the first sacrificial layer while maintaining the first metal layer and the first etch stop layer intact to form an air gap between a portion of the first etch stop layer and one or more other layers, the air gap allowing the interconnect structure to be free standing; and wherein the one or more other layers are formed over the first metal layer and wherein the selectively removing maintains a portion of the thickness of the first sacrificial layer.