Patent ID: 8811905

Claim:
A system, comprising: a processor of a wireless communication device, wherein the wireless communication device includes a multimode device, and wherein the multimode device includes an air interface for communicating with one or more terminals, and the multimode device is configured to: select a power state of the multimode device selected from a plurality of power states including a first power state, a second power state, and a third power state, wherein the multimode device is in the first power state, and wherein the selected power state is the second power state; transition the multimode device from the first power state to the second power state; in the event that A) the multimode device is in the second power state and B) the multimode device 1) receives a transition signal to transition to the first power state or 2) is not communicating with any terminals and has not communicated with any terminals for a predefined period of time, transition the multimode device from the second power state directly to the first power state; determine whether interference with another multimode device exceeds a predefined threshold; in the event that A) the interference with the other multimode device exceeds the predefined threshold and B) the multimode device is not in the third power state, transition the multimode device to the third power state; and in the event that A) the multimode device detects a terminal is present or receives a request to transition to the first power state and B) the multimode device is in the third power state, transition the multimode device from the third power state to the first power state, wherein the first power state is a serving power state communicating with one or more terminals; wherein the second power state is a scan power state communicating with the one or more terminals less frequently than in the first power state and more frequently than in the third power state; and wherein the third power state is a silent power state; and a memory coupled to the processor and configured to provide the processor with instructions.