Patent ID: 7813914

Claim:
A method for providing a digital design on a programmable chip, comprising: receiving at an interface a plurality of components for implementing a digital design on a programmable chip, wherein the plurality of components include a plurality of master components and a slave component and the slave component configured to respond to one of the master components and wherein a plurality of ports are associated with the plurality of components, the plurality of ports allowing selective communication between the plurality of components and ports associated with the plurality of components include master ports and slave ports and one of the master ports is coupled to one of the slave ports; connecting at least two of the plurality of components using at least two of the plurality of ports to form a connection fabric by determining desired interconnections between the master ports and slave ports; receiving information identifying the master ports and slave ports and providing a connectable node in a patch panel; displaying, via the interface, the patch panel representing at least a portion of the connection fabric with the plurality of master components only on one side of the patch panel, wherein the patch panel includes connection node information between the plurality of components in the patch panel and wherein the connection node information comprises a first type of one or more possible connections and a second type of one or more actual connections; identifying in the display the slave and master ports of the plurality of components; receiving data from an input device relating to a selection of a subset of the plurality of components along with a portion of the connection fabric; receiving, via the input device, a command to toggle a connection of the patch panel either from the first type to the second type or from the second type to the first type; and selectively displaying the subset of the plurality of components along with the portion of the connection fabric on a display device, wherein a processor performs a mapping of the selection data onto the connection fabric.