Patent ID: 8181101

Claim:
A data bus encoder, comprising: a bus-invert encoder, configured for generating encoded data and invert-indication information by performing bus-invert encoding on data to be encoded according to a predetermined bus-invert encoding scheme; a virtual bit-group generator, configured for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-check bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, wherein the mapping is such that the hamming distance between any possible value of the virtual bit-group and a reference virtual bit-group which cannot be converted into under the mapping is a fixed value, and not greater than the number of error-correction bits of the error-checking-and-correction encoding scheme, and wherein the virtual word includes the encoded data and the virtual bit-group corresponding to the encoded data, and if there is one or more other bits which are not occupied in the virtual word, the one or more other bits take respective fixed values.