Patent ID: 6959066

Claim:
A programmable frequency divider used to transform one import clock to one target clock with an import clock having a frequency 2 m times as high as that of the target clock wherein m is an integer larger than zero, comprising: a) a NOR Gate using remaining bits after the elimination of the most significant bit of an adjustment parameter as a input signal to form one output signal wherein the adjustment parameter contains n bits, n is an integer larger than zero, and m≦n, said adjustment parameter is controlled by program command; b) a n-bit adder (n-bit ADD) using a first signal and one return signal to create one first output signal wherein said first signal comprises the one output signal of the NOR Gate and the remaining bits after elimination of the most significant bit of the adjustment parameter, and said output signal is a most significant bit of the first signal; c) a n-bit D Flip Flop connected to said n-bit adder to form a cyclic circuit receiving the first output signal and the import clock and generating a second output signal wherein said second output signal comprises a second signal comprising the most significant bit of said second output signal and a return signal comprising n-bits from said second output signal, and said return signal is sent back to said n-bit adder to make addition calculations with said first signal; d) a NAND Gate using a first import and a second import to create a fourth output signal wherein said first import receives said output signal, and said second import from a inverse import for receiving the most significant bit of said adjustment parameter; e) a second D Flip Flop receiving the fourth output signal and the import clock to create a third signal; f) an AND Gate using a third import and a fourth import to create a fifth output signal wherein a third import receives said second signal and said fourth import form the inverse import for receiving said third signal; g) a third D Flip Flop receiving the fifth output signal and an inverse import clock to create the fourth signal, said inverse import clock making use of an inverter to inverse output the import clock; and h) a XOR Gate using said second signal and said fourth signal to create a target signal wherein said target signal is the basis for the output of the target clock.