Patent ID: 8751211

Claim:
A method for design simulation, comprising: partitioning a logical verification task of a design into a first plurality of atomic Processing Elements (PEs); determining execution dependencies between the PEs, each execution dependency specifying that a respective first PE is to be executed before a respective second PE; providing a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device; computing an order for executing the PEs on the multiprocessor device, the order formed of a sequence of slots to which the PEs are assigned, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE such that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device; providing the PEs and the computed order to the multiprocessor device for execution according to the scheduling policy, so as to produce a simulation result; and verifying a performance of the design responsively to the simulation result, wherein computing the order comprises preserving the execution dependencies by inserting dummy PEs into the order.