Patent ID: 7936005

Claim:
A semiconductor memory device comprising: a first active region and a second active region formed in a semiconductor substrate, respectively; an element isolation region which is formed in the semiconductor substrate and which isolates the first active region and the second active region from each other; and memory cell transistors which are formed on the first active region and the second active region, respectively and each of which includes a laminated gate and a first impurity diffusion layers functioning as a source and a drain, the laminated gate including a first insulating film which is formed on the semiconductor substrate and which accumulates electric charges, a second insulating film formed on the first insulating film by using a material having a dielectric constant higher than that of the first insulating film, and a control gate electrode formed on the second insulating film, the second insulating film being commonly connected between the memory cell transistors to step over the element isolation region and being in contact with an upper surface of the element isolation region, and an upper surface of the element isolation region being higher than a bottom surface of the first insulating film and, a center portion of the upper surface of the element isolation region being level with the upper surface of the first insulating film.