Patent ID: 8914617

Claim:
A processor comprising: a first storage unit having a plurality of physical registers to store content for a physical register as an entry; a second storage unit to store one or more pointers, indexed according to one or more logical registers, that map said one or more logical registers to a physical register corresponding to the entry; a Reorder Buffer (ROB) to store information about an in flight instruction or micro-operation to facilitate retirement of the in flight instruction or micro-operation; a tracking mechanism operatively coupled with retirements in the ROB to track sharing in time of any entries in the first storage unit, to which more than one of the logical registers map, by a record, indexed according to said more than one of the logical registers, and indicating for every shared entry of the plurality of physical registers which of the logical registers are currently sharing it; and logic to cause one of the one or more pointers to point to the entry and to update the record indexed by a logical register corresponding to said one of the one or more pointers in response to a request to copy content of the entry to said logical register.