Patent ID: 7385422

Claim:
A voltage generating circuit comprising: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having an input node and two output nodes, wherein said voltage selecting circuit generates tri-state output logic from said two output nodes in accordance with different setting voltages of said input node, wherein said voltage selecting circuit comprises a pair of NMOS transistors coupled in common source, wherein gates of said pair of NMOS transistors are commonly coupled to said input node and drains of said pair of NMOS transistors form said two output nodes, wherein the NMOS transistors are not electrically operable except when a first switch coupled to the sources of the pair of NMOS transistors is closed by the pulse of the pulse generating circuit; an inner voltage-generating unit for providing a voltage having one fixed value between threshold voltage of one of the NMOS transistor and threshold voltage of the other of the NMOS transistors, wherein the inner voltage-generating unit provides the voltage to the pair of NMOS transistors under control of the pulse of the pulse generating circuit, thereby preventing waste of power supplying the inner voltage-generating unit; and a plurality of flip-flops coupling to said two output nodes for locking the output voltages of said two output nodes according to the pulses.