Patent ID: 7588972

Claim:
A method of manufacturing a thin film transistor, the method comprising: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate; forming a semiconductor layer and a conductive adhesive layer on the gate insulating layer such that the semiconductor layer and the conductive adhesive layer overlay the gate electrode; depositing a barrier layer, a conductive thin layer and a capping layer over the substrate; partially etching the capping layer and the conductive thin layer to form a first capping pattern, a second capping pattern spaced apart from the first capping pattern, a source pattern and a drain pattern spaced apart from the source pattern on the gate electrode; and partially etching the baffler layer and the conductive adhesive layer to form a first barrier pattern, a second barrier pattern spaced apart from the first barrier pattern, a first conductive adhesive pattern and a second adhesive pattern spaced apart from the first conductive adhesive pattern on the gate electrode.