Patent ID: 7932779

Claim:
A D-class amplifier comprising: a pulse-width modulation generating first signal and a second output signals being pulse-width modulated corresponding to an input signal and with one rising while the other falls; and signal processing circuit that when the D-class amplification operation starts, while the pulse widths of the first signal and the second output signals are set at a predetermined minimum value, an pulse interval between the pulses of both signals is set at a predetermined minimum value, the pulse interval is then slowly increased from a minimum value, and when the pulse interval reaches a maximum value, the pulse width is gradually increased until the first signal and the second signal become signals with a duty ratio of 50% and in phases opposite each other, and wherein the signal processing circuit gradually reduces the pulse widths of the first signal and the second signal when the D-class amplification operation is stopped, and it sets each of the pulse widths at the minimum values, respectively, and, at the same time, sets the pulse interval between the first signal and the second signal at the maximum, and it then gradually reduces the pulse interval to the predetermined minimum value.