Patent ID: 7371665

Claim:
A method for fabricating an isolation layer of a semiconductor device comprising: forming a sacrificial layer on a substrate; forming a moat pattern which defines an active area and an isolation area by coating a photoresist on the sacrificial layer and performing an exposure and development process to the coated photoresist; patterning the sacrificial layer by using the moat pattern as a mask; forming an insulating layer on an entire surface of the substrate including the patterned sacrificial layer after removing the moat pattern; forming spacers at the sidewalls of the patterned sacrificial layer by anisotropically etching the insulating layer; removing the patterned sacrificial layer and exposing an entire surface of the substrate except for areas of the substrate under the spacers; depositing a silicon layer on an entire surface of the substrate including the spacers, wherein the silicon layer is deposited on both an inside and an outside of each of the spacers at the same time; and planarizing the surface of the silicon layer and the spacers by CMP.