Patent ID: 8890571

Claim:
A method for aligning an input signal to a clock signal in an integrated circuit, the method comprising: receiving the input signal; determining whether the input signal is arriving too early or too late via a plurality of delay lines, wherein the determining comprises: splitting the input signal into a first signal and a second signal; delaying the first signal by a first amount of delay via a first delay line of said plurality of delay lines; delaying the second signal by a second amount of delay via a second delay line of said plurality of delay lines, where said second amount of delay is different from the first amount of delay; sampling a delayed version of the first signal using the clock signal; sampling a delayed version of the second signal using the clock signal; comparing the delayed version of the first signal to the delayed version of the second signal; and averaging results of the comparing acquired over a plurality of cycles of the clock signal; and adjusting a delay of the plurality of delay lines in accordance with a result of the determining.