Patent ID: 8352819

Claim:
Apparatus for processing data comprising: data processing circuitry configured to perform data processing operations; a plurality of state retention circuits coupled to said data processing circuitry to capture and restore respective state values from and to respective nodes within said data processing circuitry; a mode controller coupled data processing circuitry and said plurality of state retention circuits to switch said apparatus between an active mode in which said data processing circuitry performs data processing operations and a sleep mode in which said data processing circuitry does not perform data processing operations, said plurality of state retention circuits being configured to store said state values captured from said data processing circuitry upon entering said sleep mode, said mode controller being configured to control said data processing circuitry and said plurality of state retention circuits such that upon exiting said sleep mode and returning to said active mode said state values are restored under hardware control to said respective nodes before data processing by said data processing circuitry is resumed; error management circuitry coupled to said plurality of state retention circuits and configured to detect one or more errors in retention of said state values and to trigger an error recovery response when said one or more errors are detected; and a voltage controller coupled to said error management circuitry and configured to vary one or more supply voltage levels to said plurality of state retention circuits during said sleep mode so as to maintain a finite non-zero error rate in said retention of said state values.