Patent ID: 7458046

Claim:
A method for estimating the difficulty level of a verification problem, comprising: receiving input comprising a design and a set of properties, a property of the set of properties operable to be verified on the design; repeating the following for each property of the set of properties: performing a plurality of verification processes on the each property on the design by performing an automatic test pattern generation process on the design; and establishing a property verifiability metric value for the each property in accordance with the verification processes by establishing a lower difficulty level if the runtime of the automatic test pattern generation process is less than a runtime threshold, the property verifiability metric value representing a difficulty level of verifying the each property on the design; and determining a design verifiability metric value from the property verifiability metric values of the set of properties, the design verifiability metric value representing a difficulty level of verifying the set of properties on the design.