Patent ID: 7436706

Claim:
An integrated circuit device comprising: a memory cell array having a plurality of memory cells wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate disposed over the body region; and wherein each memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor; circuitry, coupled to the memory cell array, to program one or more of the memory cells, wherein the circuitry includes: control signal generation circuitry, coupled to the memory cells, to generate control signals, having temporal characteristics, of a first predetermined program operation and a second predetermined program operation; and programmable duration circuitry, coupled to the control signal generation circuitry, to control the temporal characteristics of one or more control signals of the first predetermined program operation and the second predetermined program operation; and wherein the temporal characteristics of the one or more control signals of the first predetermined program operation are different from the temporal characteristics of corresponding control signals of the second predetermined program operation.