Patent ID: 8207569

Claim:
An integrated circuit, comprising: a plurality of capacitive structures formed on a substrate, wherein each capacitive structure includes: a first conductive finger, and a second conductive finger, wherein the first and second conductive fingers are arranged in parallel with each other and separated from each other by a dielectric material and wherein the first finger is connected to a first interconnect and the second conductive finger is connected to a second interconnect, wherein the first interconnect and second interconnect form a set of common interconnects, and wherein the first finger and the first interconnect are on separate layers, and the second finger and the second interconnect are on separate layers, wherein the first interconnect and second interconnect form different levels; a first capacitor formed from a first group of the plurality of capacitive structures having a first set of common interconnects; and a second capacitor formed from a second group of the plurality of capacitive structures having a second set of common interconnects, wherein the capacitive structures of the first group are intertwined with the capacitive structures of the second group.