Patent ID: 8377769

Claim:
A method for integrating a replacement gate in a semiconductor device, comprising: forming a well region on a semiconductor substrate, and defining a N-type device region and/or a P-type device region; forming a sacrificial gate stack or sacrificial gate stacks respectively on the N-type device region and/or the P-type device region, the sacrificial gate stack or each of the sacrificial gate stacks comprising a sacrificial gate dielectric layer and a sacrificial gate electrode layer, wherein the sacrificial gate dielectric layer is disposed on the semiconductor substrate, and the sacrificial gate electrode layer is disposed on the sacrificial gate dielectric layer; forming a spacer or spacers surrounding the sacrificial gate stack or the respective sacrificial gate stacks; forming source/drain regions on both sides of the sacrificial gate stack or the respective sacrificial gate stacks and embedded into the semiconductor substrate; forming a SiO 2 layer on the semiconductor substrate; forming a Spin-On-Glass (SOG) layer on the SiO 2 layer; etching the SOG layer until the SiO 2 layer is exposed; etching the SOG layer and the SiO 2 layer at different rates in such a manner that the SiO 2 layer is planarized; and forming a N-type replacement gate stack on the N-type device region and/or a P-type replacement gate stack on the P-type device region, respectively.