Patent ID: 8159859

Claim:
A semiconductor storage device comprising: a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic element and a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit from a low resistance state to a high resistance state, to a selected memory cell through a selected first wiring and a selected second wiring, when applying the control voltage to the memory cell plural times, the control circuit operative to set a value of the control voltage applied in a first control voltage application operation to be substantially equal to a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element in the memory cell from the high resistance state to the low resistance state, and the control circuit operative to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value in each of second and subsequent control voltage application operations.