Patent ID: 7684274

Claim:
A differential sense circuit for reading an 8 transistor (8T) memory cell, the differential sense circuit comprising: a differential input circuit having a pair of differential inputs and an output, wherein an output signal provided at the output is indicative of a difference between two signals received at the pair of differential inputs, wherein the difference is in accordance with a logic state read from the 8T memory cell; and a sense amplifier coupled to the output, wherein the sense amplifier is operable to amplify a change in the output signal, the change being greater than a threshold, wherein the sense amplifier switches the output signal to have a voltage level corresponding to the logic state, wherein a first one of the pair of differential inputs is coupled to a soft ground level reference node of a read buffer of the 8T memory cell and a second one of the pair of differential inputs is coupled to a read bit line of the read buffer.