Patent ID: 8185722

Claim:
A processor comprising: an execution unit; and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective status for each thread, each thread comprising a sequence of instructions; wherein the execution unit is configured to execute thread scheduling instructions which manage said statuses, the thread scheduling instructions included within a thread being for managing a respective status of that thread, and the thread scheduling instructions including at least: a thread event enable instruction by which a thread sets the respective thread's own status to event-enabled to allow the thread to accept events, the setting being performed while the respective thread is running, a wait instruction by which a thread sets a respective status of that thread to suspended in order to suspend that thread until generation of at least one of said events upon which continued execution of that thread depends, and a thread event disable instruction by which a thread sets a respective status to event-disabled to stop that thread from accepting events; and wherein said continued execution comprises retrieval of a continuation point vector for the thread.