Patent ID: 8854875

Claim:
A processing system, comprising: one or more memory units, one or more processors which execute programmable instruction sequences, and one or more input/output units; a phase change memory unit; multiple groups of phase change memory cells within said phase change memory unit configured to store and output configuration data, ones of said groups comprising multiple phase change memory storage cells and multiple phase change memory reference cells storing one or more references, and configured such that said storage cells and said reference cells in ones of said groups are read together; multiple sense amplifiers, ones of said sense amplifiers configured to sense read outputs of corresponding ones of said storage cells and said reference cells when one of said groups is read, and to produce sense amplifier outputs at times at least partially dependent on the states stored by said corresponding storage cells and reference cells; one or more vote units, ones of said vote units configured to generate a clock signal when a majority of said sense amplifier outputs corresponding to one of said references are detected to have transitioned at said vote unit; and multiple output units, ones of said output units configured to output a different binary value depending on whether one of said clock signals or one of said sense amplifier outputs corresponding to one of said storage cells first changes state at said output unit; wherein said processor and/or said input/output unit are configured to operate external elements in accordance with said configuration data.