Patent ID: 8581756

Claim:
A reconfigurable signal processing circuit for processing an input signal, comprising: a detector for generating a measure of at least one of an amplitude or a frequency of the input signal; a plurality of digital processing stages connected in cascade for processing the input signal, wherein the plurality of processing stages have differing output sample rates while operational; and a power management block for receiving the measure generated by the detector and determining particular ones of the plurality of digital signal processing stages that are placed in a low-power non-operational state in conformity with the measure of amplitude or frequency, whereby in at least one operating mode, when the measure indicates that the amplitude of the input signal or the frequency of the input signal is below a threshold value, at least one but not all of the plurality of digital signal processing stages is placed in the low-power non-operational state, and wherein when the measure indicates that the amplitude of the input signal or the frequency of the input signal is above the threshold value, the at least one digital signal processing stage is placed in an operational state to provide a higher performance from the plurality of digital signal processing stages.