Patent ID: 7656197

Claim:
A decoder circuit comprising: first and second transistors connected in series between a first reference node and a second reference node; third and fourth transistors connected between a connection node between the first and second transistors and the second reference node; an inverter having an input terminal which is connected to the connection node; and a fifth transistor connected between the second reference node and the connection node and receiving an output of the inverter at its gate, wherein the first transistor is connected between the second reference node and the second transistor and receives a first signal at its gate, the second transistor is connected between the first transistor and the first reference node and receives the first signal at its gate, the third transistor is connected between the second reference node and the fourth transistor and receives a second signal at its gate, the fourth transistor is connected between the third transistor and the connection node and receives a third signal at its gate, and the first and second transistors are of the different conductivity type.