Patent ID: 8843723

Claim:
A memory control system, comprising: a memory device controller configured to interface with one or more memory devices, the memory device controller coupled to the memory devices and configured for data communication with the one or more memory devices via a bus; memory configured to maintain values that are adjustable to tune bus timing margins in multi-dimensions, the bus timing margins tunable for implementation with the one or more memory devices; and a memory timing tuner configured to adjust the values to tune the bus timing margins in the multi-dimensions, the adjust at least comprising: adjust, for a first dimension of the multi-dimensions, the bus timing margin in a positive direction of the first dimension from an initial starting point until a first timing fail is determined, the initial starting point corresponding to a passing bus timing; adjust, for the first dimension of the multi-dimensions, the bus timing margin in a negative direction of the first dimension from the initial starting point until a second timing fail is determined; and determine, for the first dimension of the multi-dimensions, a point between the first and second timing fails as an optimal bus timing of the first dimension.