Patent ID: 7028233

Claim:
A method analyzing the performance of a parallel electronic data bus comprising: generating at least one digital data pattern, said digital data pattern being a pattern of digital data bits that have values of either one or zero; applying said digital data pattern to said parallel electronic data bus; using an adjustable data strobe to capture a set of said digital data bits on said parallel electronic data bus before and after a transitional edge of an electronic data bus transmission clock cycle; adjusting a data strobe offset to capture said digital data bits while said digital data pattern is transferred across said parallel electronic bus; comparing said digital data bits captured by said data strobe to said digital data pattern; identifying errors whenever said digital data bits do not match said digital data pattern; and displaying a two dimensional graph, said graph having cells delineated by an intersection of said data strobe offset on a first axis and a bit identifier specifying said digital data bits of said digital data pattern on a second axis, such that each cell of said graph displays a representation of an accumulation of said errors for said strobe adjustment offset.