Patent ID: 8723270

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a first CMOS inverter comprising first and second MOS transistors having respective, mutually opposite channel conductivity types and connected in series at a first node on said semiconductor substrate; a second CMOS inverter comprising third and fourth MOS transistors having respective, mutually opposite channel conductivity types and connected in series at a second node on said semiconductor substrate, said second CMOS inverter forming, together with said first CMOS inverter, a flip-clop circuit; a first transfer transistor provided on said semiconductor substrate between a first bit line and said first node, said first transfer transistor having a first gate electrode connected to a word line and driven by a selection signal on said word line; a second transfer transistor provided on said semiconductor substrate between a second bit line and said second node, said second transfer transistor having a second gate electrode connected to said word tine and driven by a selection signal on said word tine, said first MOS transistor being formed in a first device region of a band shape formed on said semiconductor substrate by a device isolation region, said first MOS transistor having a gate electrode of a first polysilicon pattern traversing said first device region, said third MOS transistor being formed in a second device region of a band shape formed on said semiconductor substrate by said device isolation region, said third MOS transistor having a gate electrode of a second polysilicon pattern traversing said second device region, said first polysilicon pattern being connected to a first end part of said second device region by a first via-plug, said second polysilicon pattern being connected to a first end of said first device region by a second via-plug, a third via-plug being in contact with a part of said first device region at a side opposite to a side of said first via-plug with regard to said first polysilicon pattern as a power contact, a fourth via-plug being in contact to a part of said second device region at a side opposite to said second via-plug with regard to said second polysilicon pattern as a power contact, said third via-plug having a diameter larger than a width of said first device region, said fourth via-plug having a diameter larger than a width of said second device region, said third via-plug being offset from a central line of said first device region, said fourth via-plug being offset from a central line of said second device region.