Patent ID: 7664933

Claim:
An instruction code encoding system comprising: a central processing unit (CPU); and a memory coupled to the CPU, the memory storing an instruction having a predetermined fixed-length format, the instruction including at least an operation code and a first operand and a second operand for indicating operation tar of executing of the instruction in accordance with the operation code, one of the first operand and the second operand being used as a source target of the executing of the instruction and an other of the first operand and the second operand being used as a destination target of the executing of the instruction, wherein, the operation targets of the instruction are set to be identical so as to invoke a modified operation for the instruction different from a normal operation of the instruction without modification of the predetermined fixed length format, the modified operation of the instruction being executed by replacing the operation target of the one of or the other of the first operand and the second operand with a predetermined another operation target, wherein: the CPU includes a general-purpose register and a condition code register including a carry flag portion that indicates an execution result; the predetermined another operation target being used as the source target includes the carry flag portion of the condition code register, and the other of the first operand and the second operand being used as the destination target includes a position within the general purpose register; wherein, when the operation targets of the instruction are set to be identical so as to invoke a modified operation, a content of the carry flag portion of the condition code register is transferred to the position within the general purpose register associated with the destination target.