Patent ID: 7917710

Claim:
A system, comprising: a processor; and a memory subsystem configured to communicate with said processor, wherein said memory subsystem comprises a memory controller and data storage; wherein said processor is configured to: allocate a portion of said data storage for use by a given set of instructions that are currently executing on said processor, wherein said portion of said data storage comprises a plurality of storage locations to be subsequently made accessible to the given set of instructions for their use during execution of the given set of instructions, and wherein the given set of instructions is collectively distinguishable as an executable entity; and in response to allocating said portion of said data storage to the given set of instructions: assign an identifier to said given set of instructions; and convey said identifier to said memory controller to indicate said allocating; and wherein said memory controller is configured to: associate said identifier with said portion of said data storage; receive a packet requesting access to said portion of said data storage, wherein said packet comprises a token corresponding to a particular allocation of memory by the processor for use by a set of instructions that are collectively distinguishable as an executable entity; compare said token of said packet to said identifier; and in response to said token matching said identifier, grant access to said portion of said data storage.