Patent ID: 8008733

Claim:
A semiconductor device having a power cutoff transistor comprising: a semiconductor substrate of a first conductivity type; and first and second wells of the first conductivity type formed to be spaced from each other in the semiconductor substrate, wherein a transistor of a logic circuit section is formed in the first well, a power cutoff transistor is formed in the second well, the power cutoff transistor being connected to a source current path adapted to drive the logic circuit section and turning off in response to an input control signal so as to electrically cut off the path, a shielding section is formed between the first and second wells to shield potential interference in the semiconductor substrate, and of two substrate regions shielded against potential interference by the shielding section, the one on the side of the second well has a substrate contact region formed therein, the substrate contact region being used to apply a substrate bias to the power cutoff transistor.