Patent ID: 7923806

Claim:
A semiconductor device comprising: a semiconductor substrate; a plurality of interlayer insulating layers formed above said semiconductor substrate, and including a first interlayer insulating layer below an uppermost interlayer insulating layer; a plurality of wiring layers including a first damascene wiring which is not an uppermost wiring layer and is buried in said first interlayer insulating layer, the first damascene wiring including: a barrier metal layer defining a bottom and a side wall of said first damascene wiring and defining a first hollow portion inside said barrier metal layer; a copper wiring layer disposed in said first hollow portion and defining a second hollow portion inside said copper wiring layer, the second hollow portion not contacting the barrier metal layer; and an auxiliary barrier metal layer disposed in said second hollow portion and separated from said barrier metal layer and defining a third hollow portion inside the auxiliary barrier metal layer; an auxiliary copper wiring layer filled in said third hollow portion; wherein the plurality of interlayer insulation layers include an insulating copper diffusion preventing film disposed directly on said first damascene wiring and said first interlayer insulating layer, the insulating copper diffusion preventing film having a bottom surface directly contacting with the barrier metal layer, the copper wiring layer, the auxiliary barrier metal layer and the auxiliary copper wiring layer and; an upper level via conductor disposed above said first damascene wiring, and contacting, through said insulating copper diffusion preventing film, directly with at least a top surface of the copper wiring layer of the first damascene wiring, and wherein said barrier metal layer, said auxiliary barrier metal layer and the insulating copper diffusion preventing film suppress diffusion of copper.