Patent ID: 8054122

Claim:
A circuit, comprising: a first transistor coupled between a signal input and an output; a second transistor coupled between the signal input and a node; a third transistor coupled between the node and the output; and a gate control circuit having an output coupled to the gates of the first, second and third transistors, and having a control input coupled to receive a control signal; and a capacitor coupled across the gate-to-source of the first transistor between the signal input and the output of the gate control circuit, the gate control circuit comprising pre-charge circuitry including a delay circuit coupled to the control input and adapted to respond to a change in state of the control signal received at the control input to generate a pulse signal having a pulse duration set by said delay circuit, said pre-charge circuitry operable in response to the pulse signal to couple a first reference voltage to the capacitor for the duration of the pulse signal so as to store a voltage across the capacitor which sets a gate-to-source voltage of the first transistor.