Patent ID: 8731120

Claim:
A circuit for reducing interference in an input signal, the input signal having a wanted signal and a larger interference signal, the circuit comprising: a hard limiter circuit coupled to the input signal for detecting the polarity of the input signal; a window comparator circuit coupled to the input signal for detecting when the absolute value of the amplitude of the input signal exceeds a threshold value, and generating a pulse-width modulated rectangular wave output signal; a feedback circuit coupled to an output of the window comparator for generating a control signal that controls the duty cycle of the pulse-width modulated rectangular wave output signal, wherein the feedback circuit includes a duty cycle discriminator having an output that is a monotonic function of the duty cycle of its input; and a logic circuit having a first input coupled to the hard limiter circuit, a second input coupled to the window comparator circuit, and an output, wherein an output signal of the logic circuit includes the wanted signal at a first frequency and the interference signal at a second, higher frequency.