Patent ID: 6891224

Claim:
A semiconductor device comprising: a base layer of a first conductivity type; a barrier layer of the first conductivity type formed on the base layer; a well layer of a second conductivity type formed on said barrier layer; a first trench formed from the surface of the well layer to such a depth as to reach a region in the vicinity of a junction surface between the barrier layer and the base layer; a gate electrode formed in the first trench via a gate insulating film; a contact layer of the second conductivity type selectively formed in a surface portion of the well layer; a source layer of the first conductivity type selectively formed in the surface portion of the well layer so as to contact a side wall of the gate insulating film in the first trench and the contact layer; and a first main electrode formed so as to contact the contact layer and the source layer, wherein assuming that a total sum of impurity densities in the region of said barrier layer between the first trench and a second trench is Qn, said Qn has a relation of the following equation: Qn≧ 2×10 12 cm −2 .