Patent ID: 7999293

Claim:
A semiconductor device, comprising: a p++-type silicon substrate; a p−-type first epitaxial layer formed on the p++-type silicon semiconductor substrate; an n-type second epitaxial layer formed on the p−-type epitaxial layer; the substrate and first and second epitaxial layers defining a pn junction of a PIN structural arrangement photodiode device; a plurality of p++-type semiconductor regions extending from a top of the second epitaxial layer to a surface layer part of the first epitaxial layer and serving to divide the photodiode device into the four square-shaped quadrant PIN photodiode regions; an n+-type semiconductor region formed in a surface layer part of the second epitaxial layer in each of the PIN photodiode regions; a silicon nitride layer formed on the surface of the second epitaxial layer in a central part of the four PIN photodiode regions, including over the n+-type semiconductor regions; a silicide layer formed on the surface of the second epitaxial layer along an outside edge of each n+-type semiconductor region at an outer periphery of the silicon nitride layer; isolation regions formed to surround and isolate the four PIN photodiode regions from other regions of the second epitaxial layer; a conductive layer electrically connected to the n+-type semiconductor regions via the silicide layer at the outer periphery of the four PIN photodiode regions, and being divided into L shaped segments respectively marginally bordering separate ones of the PIN photodiode regions, with two adjacent inside sides of each L-shaped segment overlapping corresponding two adjacent outside sides respectively of each square-shaped photodiode region; a first insulation layer formed over the conductive layer; a mask layer formed on the first insulation layer in a pattern of rectangular segments having inside corner portions superposed with respective outside corner portions of adjacent ones of the L-shaped segments of the PIN photodiode regions, and having other portions between and outward of, and not superposed with, the adjacent ones of the L-shaped segments; a second insulation layer formed over the mask layer; there being an opening formed in the first and second insulation layers that reaches down to the silicon nitride layer and to the silicide layer over the n+-type semiconductor regions in a central region within the segment patterns of the conductive layer and the mask layer; and a surface protective layer formed in the opening.