Patent ID: 6885227

Claim:
A clock generator comprising: an input circuit adapted to selectively receive an input signal and modify a frequency of the input signal by a first programmable amount to generate a first input signal; a feedback loop circuit adapted to receive a feedback signal and modify a frequency of the feedback signal by a second programmable amount to generate a second input signal; a phase-locked loop core adapted to receive the first input signal and the second input signal and provide a first signal; a divider circuit adapted to receive the first signal and modify a frequency of the first signal to generate a plurality of second signals having programmable frequencies; an output circuit adapted to select from the plurality of second signals and provide at least one output signal; and a skew control circuit adapted to selectively apply skew to the output signal by a third programmable amount, wherein the first, second, and third programmable amounts and the programmable frequencies are determined by data selected from electrically erasable memory.