Patent ID: 7139993

Claim:
An arrangement of differential pairs of wires that carry differential signals across a semiconductor chip, comprising: a set of parallel tracks on the semiconductor chip that are used to route the differential pairs of wires; wherein each differential pair of wires includes a true wire and a complement wire that carry corresponding true and complement signals; wherein the differential pairs of wires are non-adjacent, so that each true wire is separated from its corresponding complement wire by at least one intervening wire in the set of parallel tracks, thereby reducing coupling capacitance between corresponding true and complement wires; and one or more twisting structures, wherein a twisting structure twists a differential pair of wires so that the corresponding true and complement wires are interchanged within the set of parallel tracks, and wherein the one or more twisting structures are arranged so that substantially zero net differential coupling capacitance exists for each differential pair of wires, wherein the set of parallel tracks includes a possibly repeating pattern of six adjacent tracks, including a first track, which is adjacent to a second track, which is adjacent to a third track, which is adjacent to a fourth track, which is adjacent to a fifth track, which is adjacent to a sixth track; wherein the differential pairs of wires include a first differential pair, A and Ā, a second differential pair, B and {overscore (B)}, and a third differential pair, C and {overscore (C)}; wherein A starts in the first track, B starts in the second track, Ā starts in the third track, C starts in the fourth track, {overscore (B)} starts in the fifth track and {overscore (C)} starts in the sixth track; and wherein a first twisting structure causes A and Ā to interchange, so that Ā is in the first track, B is in the second track, A is in the third track, C is in the fourth track, {overscore (B)} is in the fifth track and {overscore (C)} is in the sixth track.