Patent ID: 8343810

Claim:
A method of making a wafer level chip scale package (WLCSP), comprising: providing a first polymer layer including a plurality of contact pads formed within the first polymer layer; mounting the first polymer layer to a carrier; mounting a semiconductor die to the first polymer layer; forming a second polymer layer over the semiconductor die and first polymer layer; forming a plurality of first conductive vias through the first and second polymer layers with the first conductive vias electrically connected to the contact pads within the first polymer layer; forming a first conductive layer over the second polymer layer and electrically connected to the first conductive vias and semiconductor die; forming a third polymer layer over the second polymer layer and first conductive layer; forming a plurality of second conductive vias through the third polymer layer and electrically connected to the first conductive layer; forming a second conductive layer over the third polymer layer and electrically connected to the second conductive vias; and forming a first interconnect structure over the third polymer layer and second conductive layer.