Patent ID: 7977124

Claim:
A method of designing a semiconductor device, comprising: registering a unit capacitor including: a first electrode formed on a first wiring layer; a second electrode formed on a second wiring layer arranged to sandwich the insulating layer with the first wiring layer in such a manner that the second electrode overlaps with the first electrode; two connection wirings connected to the first electrode; and two connection wirings connected to the second electrode, in a library as a unit cell; reading out a unit cell from the library and disposing the unit cell on an integrated circuit, when a capacitor is positioned between a first wiring for connecting between a first node and a second node in the integrated circuit and a second wiring for connecting between a third node and a fourth node in the integrated circuit; and connecting the first node and the second node to the two connection wirings connected to the first electrode, respectively, and connecting the third node and the fourth node to the two connection wirings connected to the second electrode, respectively.