Patent ID: 6867128

Claim:
A method for fabricating an electronic component with a self-aligned source, drain and gate, comprising the steps of: a) forming a dummy gate on a silicon substrate, said dummy gate defining a position for a channel of the component; b) at least one implantation of doping impurities in the substrate, to form a source and a drain on either side of the channel, using the dummy gate as an implanting mask; c) forming a metal layer on the source, drain and dummy gate: d) superficial, self-aligned siliciding of the source and drain by selectively siliciding the metal layer on the source and drain; e) depositing at least one contact metal layer having a total thickness greater than a height of the dummy gate, polishing the at least one contact metal layer stopping at the dummy gate, and imparting an insulation characteristic to a surface region of the at least one contact metal layer and the metal layer on sides of the gate electrode; and f) replacing the dummy gate by at least one final gate separated from the substrate by a gate insulating layer, and electrically insulated from the source and drain.