Patent ID: 7754601

Claim:
A method for forming a multi-layered semiconductor structure comprising: forming an etch stop layer on a silicon substrate; forming a dielectric layer on the etch stop layer; forming an anti-reflective coating on the dielectric layer; forming a patterned photoresist layer on the anti-reflective coating; using an etching gas to form an interconnect recess in the dielectric layer for creating an electrical interconnect, the recess defining an exposed sidewall in the dielectric layer and further exposing the etch stop layer, wherein the recess does not penetrate the etch stop layer; using an ashing gas to oxidize at least a portion of the exposed dielectric sidewall; depositing a non-metallic sidewall protective layer on the anti-reflective coating, oxidized portion of dielectric sidewall to encapsulate the oxidized portion, and the etch stop layer; using an anisotropic etching gas process to remove the sidewall protective layer from the etch stop layer and anti-reflective coating, wherein at least a portion of the sidewall protective layer remains to define a non-metallic spacer; depositing an electrically conductive material in the recess adjacent to the spacer; removing the anti-reflective coating to expose at least an upper portion of the oxidized portion of the dielectric sidewall; removing the oxidized portion of the dielectric sidewall to form an air gap between the spacer and the dielectric layer, wherein the electrically conductive material is supported by and isolated from the air gap by the non-metallic spacer.