Patent ID: 8164937

Claim:
A digital potentiometer, comprising: a silicon die including a front-end-of-the-line (FEOL) portion and a back-end-of-the-line (BEOL) portion vertically fabricated above and in direct contact with the FEOL portion; active circuitry included in the FEOL portion and fabricated FEOL on a semiconductor surface the silicon die; an interconnect structure included in the FEOL portion and fabricated FEOL above the active circuitry and including a plurality of electrical structures electrically coupled with at least a portion of the active circuitry; a plurality of re-writeable non-volatile memory elements (ME's) included in the BEOL portion and integrally vertically fabricated directly above the interconnect structure, each ME having exactly two terminals, each ME configured to store a resistive state as one of a plurality of conductivity profiles that are retained in the absence of electrical power and are reversibly re-writeable by applying a write voltage across the two terminals of the ME; a switch included in the active circuitry and configured to electrically couple one or more of the ME's with a first pin and a second pin; and a non-volatile register including FEOL elements and BEOL elements, the FEOL elements comprise register logic included in a sub-portion of the active circuitry and the BEOL elements comprise one or more of the ME's electrically coupled with the register logic through a subset of the plurality of electrical structures in the interconnect structure, the non-volatile register electrically coupled with the switch and configured to control the switch.