Patent ID: 7197659

Claim:
A timing circuit comprising: at least one driving circuit outputting an output signal onto a first interconnect; at least one receiving circuit receiving an input signal from a second interconnect; a phase locked loop receiving a reference clock signal and a delayed feedback clock signal, and supplying an output clock signal to said at least one driving circuit and said at least one receiving circuit, said phase locked loop generating said output clock signal according to said received reference clock signal and delayed feedback clock signal; and first and second delay elements located in the path of said reference clock signal and the path of a feedback clock signal, respectively, said first and second delay elements being configured to provide a delay in order to make said output signal meet a predetermined valid data timing requirement, wherein each of the first and second delay element comprises: at least one delay buffer to receive said reference clock and to generate a delayed reference clock, said reference clock having a falling edge, said delayed reference clock having a rising edge; a phase detector to determine whether said rising edge of said delayed reference clock is early or late with respect to said falling edge of said reference clock; a counter to increment if said rising edge of said delayed reference clock is early with respect to said falling edge of the reference clock and to decrement if said rising edge of said delayed reference clock is late with respect to said falling edge of said reference clock; and a digital-to-analog converter (DAC) coupled to receive an output from said counter, said DAC further to increase a bias applied to said delay buffer if said rising edge of said delayed reference clock is early with respect to said falling edge of said reference clock.