Patent ID: 7681168

Claim:
A semiconductor integrated device having a plurality of wires, comprising: a minimum wiring space between a first plurality of wires disposed in a first wiring layer in a first location is defined as SL 1 , where each of the first plurality of wires disposed in the first location are fine wires and all wires in the first location are disposed at the first wiring layer, a minimum wiring space between a second plurality of wires disposed in a second wiring layer in a second location is defined as SL 2 , where at least one of the second plurality of wires disposed in the second location is a wide wire and neighboring wires with respect to the at least one of the second plurality of wires are at an equal voltage potential and all wires in the second location are disposed at the second wiring layer, and a minimum wiring space between a third plurality of wires disposed in a third wiring layer in a third location is defined as SL 3 , where at least one of the third plurality of wires disposed in the third location is a wide wire and all neighboring wires with respect to the at least one of the third plurality of wires are fine wires and are at an unequal voltage potential with respect to the wide wire in the third location and all wires in the third location are disposed at the third wiring layer, wherein said semiconductor integrated device has a wire layout structure such that SL 1 ≦SL 2 <SL 3 .