Patent ID: 7493473

Claim:
A process, comprising: using a control structure that includes a first control unit configured to execute a first instruction set; a second control unit configured to execute a second instruction set; and a state register that provides state information to each of the control units, wherein the first control unit includes a first finite state machine, the second control unit includes a second finite state machine, and the second instruction set duplicates, at least in part, the first instruction set, the using including: including with each of the instructions to be executed an operating code that includes at least one bit identifying one between the first control unit and the second control unit designed to generate control signals for the instruction to be executed; executing a function for debugging the first control unit and, in the event, in the context of the debugging function, of a given instruction not being implementable in a satisfactory way on the first control unit, implementing on the second control unit the instruction not implementable in a satisfactory way on the first control unit; recognizing whether a current instruction of the plurality of instructions is to be executed by the first control unit or by the second control unit; generating a first state signal from the first control unit; generating a second state signal from the second control unit; and selectively providing one of the first and second state signals to the state register depending on which of the control units is recognized as being appropriate for executing the current instruction.