Patent ID: 8786891

Claim:
An information processing apparatus, comprising: a memory configured to hold output data; a transfer unit configured to transfer output data held in the memory to a buffer of an output unit using an inter-chip bus, wherein the transfer unit transfers a first amount of the output data held by the memory in a first mode to the buffer, and when the transfer unit receives a first type of notification from the output unit, the transfer unit initiates a second mode, in which: the transfer unit transfers a second amount of the output data multiple times to the buffer, and the second amount is less than the first amount; and a control unit configured to determine an interval based on an output data amount per unit time of the output unit and the second data amount of the output data, wherein the interval is between a first transfer of the second amount of output data in the second mode and a second transfer of the second amount of output data in the second mode, and wherein the second transfer is next data transfer from the memory to the buffer after the first transfer in the second mode.