Patent ID: 7106612

Claim:
A semiconductor memory device comprising: a plurality of banks, each bank comprising a pair of sub-banks; a plurality of LIO (local input & output) sense amplifiers installed in each of the sub-banks, the LIO sense amplifiers sensing and amplifying data stored in memory cells of the sub-banks; and a plurality of GIO (global input & output) sense amplifiers installed between the plurality of banks, the plurality of GIO sense amplifiers sensing and amplifying outputs from the plurality of LIO sense amplifiers, wherein the pair of sub-banks of each bank are diagonally arranged on opposite sides with respect to a center of the banks, one of the sub-banks of the pair being arranged farther away from its corresponding GIO sense amplifier than the other sub-bank of the pair is to its corresponding GIO sense amplifier, and wherein the LIO sense amplifiers are arranged in such a way that driving capabilities of the LIO sense amplifiers for the one sub-bank of each bank that is arranged farther way from its corresponding GIO sense amplifier are greater than driving capabilities of the LIO sense amplifiers for the other sub-bank of each bank that is arranged nearer to its corresponding GIO sense amplifier, and wherein, within each sub-bank, the driving capabilities of the LIO sense amplifiers are the same as each other.