Patent ID: 7365421

Claim:
An IC (integrated circuit) chip package comprising: a substrate comprising: a top planar surface; a bottom surface opposite to the top surface; a receiving chamber, having an opening at the top planar surface; a plurality of solder pads arranged on the top planar surface; a plurality of solder pads arranged on the bottom surface, respectively corresponding to the solder pads arranged on the top planar surface; and a plurality of vias defined therein, the vias having conductive material electrically connecting the solder pads on the top and the bottom surfaces; a chip mounted in the receiving chamber of the substrate, the chip comprising a plurality of solder pads arranged around a top surface thereof; a plurality of bonding wires respectively directly electrically connecting the solder pads on the top surface of the substrate and the solder pads of the chip; an adhesive means applied to exclusively cover the bonding wires and areas where the bonding wires connect with the solder pads on the top surface of the substrate and the solder pads of the chip; and a cover glued directly to the top planar surface of the substrate and covering the opening such that the solder pads on the top planar surface are partially exposed at the top planar surface, the cover providing a clearance above the solder pads on the top planar surface.