Patent ID: 7269288

Claim:
An apparatus for parallel calculation of prediction bits for a spatially predicted coded block pattern having an A 0 bit, an A 1 bit, an A 2 bit, and an A 3 bit, the apparatus comprising: a storage device storing rows of bits including the spatially predicted coded block pattern, a D 0 bit, an X 0 bit, an X 1 bit, a Y 0 bit, and a Y 1 bit; a first circuit connected to the storage device for setting the A 0 bit; a second circuit connected to the storage device for setting the A 2 bit; wherein the first circuit and the second circuit operate in parallel for setting the A 0 bit equal to the Y 0 bit and setting the A 2 bit equal to the Y 1 bit if the X 0 bit is equivalent to the D 0 bit, otherwise setting the A 0 bit equal to the X 0 bit.