Patent ID: 8094562

Claim:
An apparatus, comprising: a data input to receive frames carrying a continuous datastream from a frame-based transport network; an egress buffer circuit configured to buffer the continuous datastream and to generate a feedback signal based at least in part on a fill-level of the egress buffer circuit; a phase locked loop (“PLL”) coupled to receive the feedback signal from the egress buffer circuit and to determine a clock signal from the continuous datastream; a de-framer coupled between the data input and the egress buffer circuit, the de-framer configured to extract the continuous datastream from the frames, wherein the de-framer is configured to be clocked by a transport clock of the frame-based transport network independent of the clock signal of the continuous datastream received by the de-framer; and a data output configured to output data of the continuous datastream from the egress buffer circuit based on the clock signal, wherein the PLL is configured to generate the clock signal to read out the continuous datastream from the egress buffer circuit at an average read rate approximately twice an average write rate at which the continuous datastream is to be written into the egress buffer circuit while an average read size of each read operation from the egress buffer circuit is approximately half an average write size of each write operation into the egress buffer circuit, wherein the PLL is configured to decrease an associated charge pump current to reduce jitter in a steady state phase; and wherein the PLL comprises: a summation circuit coupled to generate a sum of the feedback signal and the clock signal; a phase detector coupled to the summation circuit to generate an error signal indicative of a phase difference between the feedback signal and the clock signal; a low pass filter coupled to filter the error signal; and a voltage controlled oscillator (“VCO”) coupled to generate the clock signal responsive to the error signal; and the apparatus further comprising startup logic coupled to selectively couple either the clock signal from the VCO or a local clock signal into the summation circuit, the startup logic to temporarily couple the local clock signal into the summation circuit to initially synchronize the PLL.