Patent ID: 7562320

Claim:
An ASIC based hardware accelerated simulation engine for accelerating a process of logic verification of integrated circuit designs including: a simulation engine memory module interconnected to a field of ASIC chips; each of said ASIC chips includes an Instruction Memory Module (IMM) and a Logic Evaluation Unit (LEU); said IMM having an instruction row output connected to an input of said LEU; said LEU including as follows: an Instruction Row Decoder (IRD) connected to said instruction row output; Gate Evaluation Processors (GEPs) which simulate a piece of device under test, with said GEPs having an input connected to an output of said IRD; Internal Storage Registers (ISRs) connected to said GEPs; a pair of Conveyor Belt Programmable Cross-Point Switches (CBPCPS)s in said LEU connected between said ISRs and input pins to said ASIC chip and output pins from said ASIC chip with said IRD configured to provide command bits to said GEPs; said GEPs in said ASIC chips being interconnected by a said pair of CBPCPSs and input pins and output pins to an interconnect network which provide a direct connection with said simulation engine memory module; each of said CBPCPSs having an input port, an output port, and a command port; and each of said CBPCPSs being configured to propagate signals from said input port to said output port following a permutation determined by values on said command port.