Patent ID: 8677294

Claim:
A system comprising: a first device; a second device; and a bus interconnecting the first and second devices to each other; wherein the first device comprises: a first semiconductor chip that comprises, a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode, the first data control circuit receiving the first data signal and responding to change from the inactive level to the active level of the first output timing signal to initiate driving the first data electrode to a logic level related to the first data signal; a second semiconductor chip that comprises, a second memory cell array including a plurality of second memory cells, a second control logic circuit accessing the second memory cell array and producing a second data signal in response to data stored in a selected one of the second memory cells, the second control logic circuit being configured to store second timing adjustment information and to produce a second output timing signal that is adjustable in timing of change from an inactive level to an active level by the second timing adjustment information, a second data electrode, and a second data control circuit coupled to the second control logic circuit and the second data electrode, the second data control circuit receiving the second data signal and responding to change from the inactive level to the active level of the second output timing signal to initiate driving the second data electrode to a logic level related to the second data signal; and a third semiconductor chip that is configured to control each of the first and second semiconductor chips; wherein the first, second and third semiconductor chips are stacked with each other such that the second semiconductor chip is between the first and third semiconductor chips; and wherein the first timing adjustment information and the second timing adjustment information control the first output timing signal and the second output timing signal, respectively, so that a first timing at which the third semiconductor chip receives the logic level related to the first data signal from the first semiconductor chip is approximately aligned with a second timing at which the third semiconductor chip receives the logic level related to the second data signal from the first semiconductor chip.