Patent ID: 7712009

Claim:
A cyclic redundancy check circuit comprising: a first shift register to a p-th (p is a natural number greater than 1) shift register which each have one stage or a plurality of stages connected in cascade, and in which an inputted signal is delayed and then outputted from the one stage or the plurality of stages, and in which the output of signal from the one stage or the plurality of stages is performed in synchronization with a clock signal; a first exclusive OR circuit to a (p−1)th exclusive OR circuit each calculating an exclusive OR of two inputted signals; and a switching circuit to which a data signal, a select signal, and an output of a last stage of the p-th shift register are inputted, and which switches one of a first signal or a second signal to be outputted in response to the select signal, wherein an output of the switching circuit is inputted to a first stage of the first shift register, wherein an output of a last stage of an r-th (r is a natural number smaller than p) shift register, and the output of the switching circuit are inputted to an r-th exclusive OR circuit, and an output of the r-th exclusive OR circuit is inputted to a first stage of a (r+1)th shift register, wherein the first signal is an exclusive OR of the data signal and the output of the last stage of the p-th shift register, and wherein the second signal is a logical value of “0”.