Patent ID: 8254153

Claim:
A semiconductor memory device comprising: a first memory cell array area and a second memory cell array area in which memory cell arrays are formed; a peripheral circuit area that is arranged between the first memory cell array area and the second memory cell array area, and in which a peripheral circuit is formed; a first pad row that is arranged between the first memory cell array area and the peripheral circuit area along a first direction in which an end of the first memory cell array area extends; a second pad row that is arranged between the second memory cell array area and the peripheral circuit area along a second direction in which an end of the second memory cell array area extends; a first trunk area that is arranged between the first memory cell array area and the first pad row along the first direction; a second trunk area that is arranged between the second memory cell array area and the second pad row along the second direction; a first lead wiring that connects a first pad included in the first pad row to a first trunk arranged in the first trunk area without using a through hole electrode; and a second lead wiring that connects a second pad included in the second pad row to a second trunk arranged in the second trunk area without using a through hole electrode, wherein the peripheral circuit is not substantially arranged between the first memory cell array area and the first pad row and between the second memory cell array area and the second pad row.