Patent ID: 8407540

Claim:
Data processing circuitry for processing data, said data processing circuitry comprising: a data input, a data output and at least one processing path arranged between said data input and said data output, said at least one processing path comprising: a plurality of synchronisation circuits for capturing and transmitting said data in response to a clock signal; and a plurality of combinational circuits arranged between said synchronisation circuits for processing said data; a plurality of retention circuits for storing data in a low power mode, said plurality of retention circuits being arranged in parallel with said at least one processing path; and at least one potential error detecting circuit for detecting potential errors by determining during processing of said data if said data signal pending at an input to one of said plurality of synchronisation circuits is stable during a predetermined time prior to capture of said data and for signalling a potential error if said data input is determined to be unstable during said predetermined time, said at least one potential error detecting circuit comprising: a potential error detecting path for transmitting said data signal pending at said input of said one of said plurality of synchronisation circuits to one of said retention circuits said potential error detecting path comprising delay circuitry for delaying said data signal such that said data signal arrives at said retention circuit said predetermined time after it arrives at said synchronisation circuit; comparison circuitry for comparing a value of said data signal captured by said one of said synchronisation circuits with a value of said data signal captured by a corresponding one of said retention circuits, said comparison circuitry being configured to signal a potential error in response to detecting a difference in said captured data values; and a control signal input for receiving a low power mode enable signal, each of said plurality of retention circuits configured, in response to said low power enable signal being asserted, to capture a data value currently captured by a corresponding one of said synchronisation circuits and to retain said data value during said low power mode, wherein during said low power mode said corresponding ones of said synchronisation circuits are powered down.