Patent ID: 7012850

Claim:
A Dynamic Random Access Memory (DRAM) for performing read, write, and refresh operations, said DRAM comprising: (a) a plurality of sub-arrays, each comprising a plurality of memory cells, each memory cell is coupled to a bit line of a complementary bit line pair of a plurality of complementary bit line pairs, and to a word line of a plurality of word lines; (b) a word line enable circuit for activating a selected one of said plurality of word lines; (c) a column select circuit for activating a selected one of said plurality of bit line pairs; (d) a timing circuit for controlling said word line enable circuit, said column select circuit, and said read, write, and refresh operations in response to a word line timing pulse; and (e) wherein each sub-array of said plurality of sub-arrays comprise separate, dedicated plurality of bit line sense amplifiers.