Patent ID: 7986171

Claim:
A mixed-voltage input/output (I/O) buffer, comprising: an output buffer circuit, comprising: an output stage circuit comprising stacked pull-up P-type transistors and stacked pull-down N-type transistors, a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors being coupled to an I/O pad; a gate-tracking circuit for controlling gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad, the gate-tracking circuit including a second P-type transistor coupled between the gate of said first P-type transistor and said I/O pad to control said gate voltage; and a floating N-well circuit for providing N-well voltages for an N-well of the first P-type transistor and an N-well of said second P-type transistor.