Patent ID: 7295456

Claim:
A semiconductor memory comprising: a memory cell block comprising a plurality of memory cells connected in series in each of which two electrodes of a ferroelectric capacitor are electrically connected to a source and a drain of a first MOS transistor, respectively; a plurality of word lines each of which is electrically connected to a gate of said first MOS transistor; a plate line electrically connected to a first terminal of a memory cell series circuit formed of the series connected memory cells of said memory cell block; a block selector switch which is used to select the memory cell block; a bit line electrically connected to a second terminal of the memory cell series circuit of the memory cell block through the block selector switch; and a sense amplifier coupled to said bit line to compare and amplify voltages of a bit line pair of the bit line and its complementary bit line; wherein the first MOS transistor has a threshold level of 0V or near 0V.