Patent ID: 7663851

Claim:
A tie-low circuit capable of protecting a core circuit element during an electrostatic discharge (ESD) event, the tie-low circuit comprising: at least one resistor coupled between the core circuit element and a ground potential for preventing the core circuit element from floating during a normal circuit operation, wherein the core circuit element includes a PMOS transistor and an NMOS transistor serially connected between a power supply voltage and the ground potential to form an inverter; and a first diode string having a first set of diodes coupled in series, an anode of the first diode string being connected to an input terminal of the inverter and a cathode of the first diode string being connected to the ground potential for raising a gate voltage of the PMOS transistor, thus lowering a source-to-gate voltage (Vgs) of the PMOS transistor to protect a gate oxide of the PMOS transistor when the gate voltage of the PMOS transistor is larger than a voltage at the ground potential during the ESD event.