Patent ID: 8010750

Claim:
An invalidate method for maintaining cache coherency on a network on chip (‘NOC’): wherein the NOC includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and at least one network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, at least one memory communications controller further comprising a cache coherency controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising: executing a memory access instruction by a first memory communications controller, including determining a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid, including: sending a request from the first memory communications controller to a second first memory communications controller having a cache coherency controller; retrieving, by a cache coherency controller of the second memory communications controller from a cache coherency directory, the state of the cache line; and returning, by the second memory communications controller, the state of the cache line to the requesting memory communications controller; if the state of the cache line is shared, broadcasting an invalidate command to a plurality of IP blocks of the NOC; and if the state of the cache line is exclusive, transmitting an invalidate command only to an IP block that controls a cache where the cache line is stored.