Patent ID: 7868392

Claim:
An integrated circuit comprising: a substrate; a plurality of doped zones formed in the substrate so as to form a plurality of parasitic thyristor structures that each include two parasitic bipolar transistors; a plurality of first metallizations and a plurality of second metallizations, each of the first metallizations interconnecting two of the doped zones of one of the parasitic thyristor structures and a each of the second metallizations interconnecting another two of the doped zones of one of the parasitic thyristor structures, so as to reduce base resistances of the two bipolar transistors; a first power supply metallization; and a second power supply metallization, wherein none of the first metallizations is directly connected to the first or second power supply metallization, at least two of the first metallizations are directly connected by a third metallization, none of the second metallizations is directly connected to the first or second power supply metallization, and at least two of the second metallizations are directly connected by a fourth metallization.