Patent ID: 6868458

Claim:
A communication system which stores packet data received via a plurality of channels in a memory or transmits packet data stored in a memory through the plurality of communication channels, the communication system comprising: a plurality of buffer descriptors in which information on packet data received or transmitted via the plurality of communication channels is stored; a central processing unit (CPU) which stores the information on packet data in each of the plurality of buffer descriptors, and allots a flag bit to each buffer descriptor indicating whether a buffer descriptor is being organized, whether an error occurred in packet data received via the plurality of communication channels, or whether the organization of each of the buffer descriptors is completed; and a direct memory access (DMA) controller which determines the flag bit allotted by the central processing unit, and according to the flag bit, stops processing a buffer descriptor currently being accessed and accesses a next buffer descriptor, or processes packet data according to information stored in the buffer descriptor currently being accessed, wherein the flag bit comprises an ownership bit for indicating that the buffer descriptor is in a CPU mode if each of the buffer descriptors is being organized or an error occurred in packet data received via the communication channels, and for indicating that the buffer descriptor is in a DMA mode, in which the DMA controller is accessible, if the organization of each of the buffer descriptors is completed, and a skip bit for indicating whether the CPU is organizing the buffer descriptor or whether or not an error occurred in packet data received via the communication channels.