Patent ID: 7363460

Claim:
A semiconductor memory device, comprising: a cell area having N+1 number of unit cell blocks, each including M number of word lines wherein the N number of unit cell blocks are each corresponded to a logical cell block address and one unit cell block is added for accessing data with high speed; a predetermined cell block table for storing candidate information representing at least more than one candidate word line among the M * (N+1) number of the word lines; and a tag block for receiving a row address, sensing the logical cell block address in an inputted row address and outputting a physical cell block address based on the logical cell block address and the candidate information, wherein the tag block includes: N+1 number of unit tag tables corresponding to the N+1 number of unit cell blocks, each having M number of registers, the M number of registers corresponding to M number of word lines of corresponding unit cell blocks, each register storing one logical cell block address; and an initialization unit for initializing the N+1 number of unit tag tables.