Patent ID: 7276723

Claim:
A field effect transistor (FET) comprising: a substrate, a source, a gate and a drain; multiple channels in said substrate between said drain and said source to improve the linearity of drain current vs drain voltage characteristics when a gate voltage exceeding the threshold voltage is applied at the gate, said multiple channels having alternate layers of undoped layers of first kind of semiconductor and doped layers of second kind of semiconductor, and said doped layers having doping concentrations which varies in steps with depth from said gate, wherein the channels are selected from the group consisting of uniformly doped, delta doped, spike doped, doped sub-well, and (InAs sub-well, TlP (TlAs) sub-well, InN sub-well and InAs, TlP, TlAs, InN) self assembled quantum dots for Ill-V compound semiconductors, wherein the channels are selected from the group consisting of uniformly doped, delta doped, spike doped, Ge sub-well, Sn sub-well and self assembled quantum dots selected from the group consisting of Ge and Sn for IV-IV compound semiconductors, and formed on buffer layer grown on the substrate, and wherein said the doped channel/undoped barrier semiconductor pairs are selected from the group of II-VI/III-V, IV-IV/III-V, IV-IV/II-VI semiconductors consisting of Si/GaP, Si/ZnS, GaAs/ZnSe, and InSb/CdTe.