Patent ID: 7173557

Claim:
An A/D converter for converting an analog input signal into a binary-encoded word during a series of conversion steps, the A/D converter comprising: a bit-weight memory for storing a group of binary-encoded bit weights for encoding an analog input signal into a binary-encoded data word, the group including at least a maximum binary-encoded bit weight, a minimum binary-encoded bit weight, and a medium binary-encoded bit weight; a first register in communication with the bit-weight memory for storage of a lower bit weight during a conversion step; a second register in communication with the bit-weight memory for storage of an upper bit weight during the conversion step; a D/A converter for converting one of the upper and lower bit weights into an analog bit-weighting signal during the conversion step; a comparison device in communication with the D/A converter for providing a comparison result indicative of a comparison between the analog input signal and the analog bit-weighting signal during the conversion step; a third register in communication with the comparison device for storage of the comparison result during the conversion step; a multiplexer in communication with the first and second registers for selecting, during the conversion step, a bit weight from one of the upper and lower bit weights, the multiplexer being configured to select the upper bit weight when the comparison result indicates that the analog input signal is greater than the analog bit-weighting signal; and to select the lower bit weight when the comparison result indicates that the analog input signal is less than the analog bit-weighting signal; a subtractor in communication with the multiplexer and with the bit-weight memory for providing a new lower bit weight for the conversion step, the subtractor being configured to subtract, from the bit weight of a preceding conversion step, a smaller binary-encoded bit weight selected from the group of binary-encoded bit weights, the smaller binary-encoded bit weight being smaller than the binary-encoded bit weight selected in the preceding conversion step; and closest to the binary-encoded bit weight selected in the preceding conversion step; and an adder in communication with the bit-weight memory and the subtractor for providing a new upper bit weight for the conversion step, the adder being configured to add the new lower bit weight provided by the subtractor to the smaller binary-encoded bit weight.