Patent ID: 8212536

Claim:
A method of generating a regulated voltage, comprising: generating the regulated voltage through controlled closing and opening of a series switch element and shunt switch element, the series switch element being connected between a first voltage supply and a common node, and the shunt switch being connected between the common node and a second supply voltage, comprising; closing the series switch element during a first period, the series switch element comprising an NMOS series switching transistor stacked with an NMOS series protection transistor, the closing of the series switch element comprising; applying a switching gate voltage to a gate of the NMOS series switch transistor of the series switch element, wherein the switching gate voltage has a voltage potential of at least a threshold voltage greater than a voltage potential of the common node; closing the shunt switch element during a second period, the shunt switch element comprising an NMOS shunt switching transistor stacked with an NMOS shunt protection transistor; wherein closing the series switch element during the first period further comprises applying a second switching gate voltage to the NMOS series protection transistor, and further comprising charging a floating capacitor during the second period, wherein the floating capacitor is coupled between the common node and a gate of the NMOS series protection transistor, and aids in control of the second switching gate voltage.