Patent ID: 7508361

Claim:
A display device comprising: a plurality of pixel circuits arranged in a matrix array, at least one data line laid for a column of the matrix array of said pixel circuits and supplied with a plurality of data signals in accordance with luminance information, a first control line laid for every row of the matrix array of said pixel circuits, first and second reference potentials, at least one reference current supply line laid for the column of the matrix array of said pixel circuits and supplied with a predetermined reference current, and a plurality of pixel units each including at least two pixel circuits of said plurality of pixel circuits, said at least two pixel circuits being arranged in a single column of the matrix array and connected to a single one of the at least one data line; each said pixel unit including: a reference current transfer line connected in common to the at least two pixel circuits in the pixel unit, and a current transfer circuit configured to accumulate reference currents supplied to said reference current supply line over a predetermined period and configured to transfer reference currents accumulated after an elapse of said predetermined period to said reference current transfer line; each said pixel circuit of said at least two pixel circuits including: an electro-optical element, first, second, and third nodes, a drive transistor forming a current supply line between a first terminal and a second terminal connected to said first node and configured to control a current flowing through said current supply line in accordance with a potential of a control terminal connected to said second node, a first switch connected to said first node, a second switch connected between said first node and said second node, a third switch connected between said single at least one data line and said third node and controlled in its conduction by said first control line, a fourth switch connected between said first node and said reference current transfer line, and a coupling capacitor connected between said second node and said third node; and the current supply line of said drive transistor, said first node, said first switch, and said electro-optical element being connected in series between said first reference potential and second reference potential.