Patent ID: 7776653

Claim:
A method for fabricating a semiconductor device, comprising the steps of: providing a first chip having an active and a passive surface, the active surface including devices and an interior first set of contact pads and a peripheral second set of contact pads; providing a substrate having a first surface with an attachment location and a third set of contact pads near the attachment location; attaching the passive surface of the first chip onto the attachment location of the substrate; pressing a first gold ball on the first and the second set of contact pads; pressing a second gold ball on the first pressed gold ball on the first set of contact pads to create column-shaped spacers; forming low profile stitch wire bonds on the pressed first gold balls on the second set of contact bond pads and spanning the wires to electrically connect the first chip and the substrate; providing a second semiconductor chip having a fourth set of contact pads matching the first set of contact pads and an edge; aligning the fourth set of contact pads of the second semiconductor chip to the spacers on the first set of contact pads and with the edge overhanging at least one low profile stitch wire bond; and applying thermal energy to reflow a solder metal for bonding the fourth set of contact pads to the spacers on the first set of contact pads, electrically connecting the first and the second chip.