Patent ID: 7319731

Claim:
A PLL (Phase Locked Loop) implemented to perform high precision continuous time BPF (Band Pass Filter) tuning, the PLL comprising: a PFD (Phase/Frequency Detector) that is operably coupled to determine a phase difference between transitions of a feedback signal and an input signal; a CP (Charge Pump) operably coupled to convert the phase difference into a charge pump current; a loop filter operably coupled to convert the charge pump current into a VCO (Voltage Controlled Oscillator) control voltage; a VCO (Voltage Controlled Oscillator) operably coupled to convert the VCO control voltage into a recovered clock, wherein the feedback signal is derived from the recovered clock; wherein the VCO includes a plurality of g m (transconductance) cells; an amplitude detector that detects an amplitude of the recovered clock and that biases the plurality of g m cells of the VCO such that the each g m cell of the plurality of g m cells operates substantially within its linear operating region; wherein the loop filter is implemented as a LPF (Low Pass Filter) having a resistor and a capacitor connected in series such that the capacitor is shunted to ground; wherein a BPF (Band Pass Filter) control voltage is selected from a node that connects the resistor and the capacitor; and wherein the BPF control voltage determines a tuning frequency of a BPF to which the PLL is communicatively coupled.