Patent ID: 8531327

Claim:
An analog to digital converter (ADC), comprising: a clock control unit configured to provide an operating clock signal having an operating frequency corresponding to a luminance condition, wherein the operating frequency is set to a higher frequency for a lower luminance condition and to a lower frequency for a higher luminance condition; and a signal conversion unit configured to generate a count value corresponding to an inputted pixel signal, wherein the counting is performed according to the operating frequency during an overall count section of a predetermined duration, wherein the overall count section during which counting is performed includes at least two subsections such that the operating frequency provided in one subsection is different from another subsection, wherein the operating clock signal having the operating frequency to be provided in each subsection is selected from one or a plurality of clock signals having different frequencies, wherein the signal conversion unit comprises: a ramp signal generating unit generating a ramp signal having a predetermined slope; a comparing unit comparing the ramp signal with an inputted pixel signal to output a comparison result signal; a counter counting according to the operating frequency and storing a count value counted at a time of the generating of the comparison result signal; and wherein the signal conversion unit further comprises: a pulse generating unit receiving the comparison result signal from the comparing unit and outputting a pulse at the time of generating of the comparison result signal to store the count value in a register.