Patent ID: 8737142

Claim:
An internal voltage generation circuit of a semiconductor memory device to which a first power supply voltage is supplied, comprising: a voltage generation circuit that generates a second power supply voltage based on the first power supply voltage, outputs the second power supply voltage to an output node, compares a value of a voltage of the output node and a detection voltage value, and controls the voltage of the output node so as to be a voltage between a first voltage corresponding to a lower limit of the detection voltage value and a second voltage corresponding to an upper limit of the detection voltage value; and a voltage control circuit that includes: a first current load circuit that is connected to the output node and that changes the voltage of the output node so as to pull down the voltage of the output node; and a second current load circuit that is connected to the output node and that changes the voltage of the output node so as to pull up the voltage of the output node, wherein the voltage of the output node is maintained at the first voltage by the first current load circuit of the voltage control circuit operating, and the voltage of the output node is maintained at the second voltage by the second current load circuit of the voltage control circuit operating.