Patent ID: 7447621

Claim:
A method for providing verification for a simulation design, comprising: obtaining the simulation design comprising a programming language interface system call; obtaining a reference value corresponding to the programming language interface system call; encoding the reference value into the simulation design to obtain a modified simulation design, comprising: obtaining a set of hardware state elements from the simulation design; obtaining a set of high-level state elements from a high-level design; determining a common set of state elements from the set of hardware state elements and the set of high-level state elements; identifying at least one relationship between the high-level state element and the hardware state element in the common set of state elements; determining whether the at least one relationship is influenced by a test vector to obtain an influenced set of relationships; and encoding the influenced set of relationships to obtain the modified simulation design, comprising: obtaining high-level state element values for the high-level state elements in the influenced set of relationships from a simulation of the high-level design, and storing the high-level state element values in an array, wherein at least one of the high-level state element values is the reference value; compiling the modified simulation design to obtain a compiled simulation design; and verifying the compiled simulation design using a simulation test bench.