Patent ID: 8265132

Claim:
A high-speed serial bit stream conditioning circuit configured to generate a conditioned TX signal and a conditioned RX signal, the high-speed serial bit stream conditioning circuit comprising: a line side interface that communicatively couples to a line side media, the line side interface configured to receive a RX signal therefrom, and to transmit the conditioned TX signal thereto; a board side interface that communicatively couples to a communication ASIC, the board side interface configured to receive a TX signal therefrom, and to transmit the conditioned RX signal thereto; an equalizer that receives a high-speed serial bit stream as the RX signal or the TX signal and that spectrally shapes the high-speed serial bit stream to produce an equalized high-speed serial bit stream, wherein the equalizer is configured to receive the RX signal from the line side interface and to produce the equalized high-speed serial bit stream, and the equalizer is configured to receive the TX signal from the board side interface and to produce the equalized high-speed serial bit stream; and a clock and data recovery circuit operable to compensate for jitter, the clock and data recovery circuit operably coupled to an output of the equalizer that recovers the equalized high-speed serial bit stream to produce an output high-speed serial bit stream as either respectively the conditioned TX signal or the conditioned RX signal.