Patent ID: 8018445

Claim:
A serial data input system comprising: a first register that receives and shifts serially transferred data in synchronization with a clock so as to hold the serially transferred data; a clock counter that counts clock pulses of the clock and outputs a first clock count signal when the counted clock pulses reach a first predetermined number and outputs a second clock count signal when the counted clock pulses reach a second predetermined number greater than the first predetermined number; a second register that receives from the first register first data serially transferred to the first register in response to the first clock count signal; and a third register that receives directly from the first register second data serially transferred to the first register in response to the second clock count signal, wherein both the second register and the third register receive the first and second data, respectively, by parallel data transfer without reversing a state of either the first data or the second data, the first data is all the serially transferred data that is held by the first register at the time of the parallel data transfer to the second register, and the second data is all the serially transferred data that is held by the first register at the time of the parallel data transfer to the third register.