Patent ID: 8645602

Claim:
A microcomputer comprising: a bus master that operates in accordance with a first clock having a variable frequency; a bus slave that operates in accordance with a second clock; and a bus controller that is coupled to the bus master through a main bus and coupled to the bus slave through a peripheral bus, wherein, when the first clock and the second clock are provided simultaneously for the bus master and the bus slave, respectively, and the frequency of the first clock is higher than the frequency of the second clock, the bus controller generates a bus control signal for the bus slave by using a first synchronization signal, which indicates the change timing of a bus control signal for the peripheral bus, and wherein, when the first clock and the second clock are provided simultaneously for the bus master and the bus slave, respectively, and the frequency of the first clock is lower than the frequency of the second clock, the bus controller generates a bus control signal for the bus master by using a second synchronization signal, which indicates the change timing of a bus control signal for the main bus.