Patent ID: 8347072

Claim:
A processing system comprising: a display controller adapted to communicate with a display device; a non-volatile memory to store verification enforcement instructions; a system memory having a secure partition; and a processor coupled to the non-volatile memory and the system memory, the processor comprising: an on-chip basic input/output system (BIOS) containing bootstrap security logic; and an execution unit coupled to the on-chip BIOS and the system memory, the execution unit configured to perform operations specified by the bootstrap security logic, the operations including copying the verification enforcement instructions from the non-volatile memory to the secure partition and verifying the authenticity of the verification enforcement instructions; secure partition enforcement logic coupled to the execution unit, the secure partition enforcement logic configured to monitor accesses to the secure partition and to determine whether to permit or deny a memory access; a translation look-aside buffer (TLB) coupled to the secure partition enforcement logic and configured to match a virtual memory address to physical memory addresses; and cryptographic logic coupled to the execution unit and a key storage element, the cryptographic logic configured to decrypt the verification enforcement instructions based on the key, wherein the cryptographic logic implements an RSA algorithm.