Patent ID: 8766379

Claim:
An integrated circuit device comprising: a semiconductor substrate; and a p-type metal oxide semiconductor (PMOS) gate stack disposed over the semiconductor substrate and an n-type metal oxide semiconductor (NMOS) gate stack disposed over the semiconductor substrate, wherein the PMOS and NMOS gate stacks both include: an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, wherein the first conductive layer includes: a first metal layer disposed over the high-k dielectric layer, wherein the first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and wherein the material of the first metal layer is a conductive, reactive metal material selected from the group consisting of hafnium (Hf), titanium (Ti), cobalt (Co), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), and combinations thereof; a second metal layer disposed over the first metal layer, wherein material of the second metal layer is one of titanium-rich TiN and tantalum-rich TaN, and a third metal layer disposed over the second metal layer, wherein the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer; and wherein the NMOS gate stack further comprises: a second conductive layer disposed over the first conductive layer, wherein the second conductive layer provides an n-type work function; and wherein the PMOS gate stack further comprises: a third conductive layer disposed over the first conductive layer, wherein the third conductive layer provides a p-type work function.