Patent ID: 7626244

Claim:
A structure, comprising: an NFET comprising a first and a second source/drain separated by a first channel region in a semiconductor substrate, and a first gate dielectric between an electrically conductive first gate and said first channel region; a PFET comprising a third and a fourth source/drain separated by a second channel region in said substrate, and a second gate dielectric between an electrically conductive second gate and said second channel region regions of a first dielectric layer of a first material over said first gate and said third and fourth source/drain regions and not over said second gate and regions of a second dielectric layer of a second material over said second gate and first and second source/drains, and not over said first gate, top surfaces of said first and second dielectric layers coplanar; and said first dielectric layer having an internal stress different from an internal stress of said second layer.