Patent ID: 7747902

Claim:
System comprising: at least two processors each executing an identical instruction stream, wherein at least one of said processors is a checking processor and at least another one of said processors is a master processor; checking logic coupled to said at least two processors for receiving outputs of said at least two processors and comparing them, wherein the checking logic outputs an error signal if the outputs miscompare; and said at least one master processor coupled to the checking logic for detecting the error signal and, in response thereto, determining whether to issue a restart signal for restarting execution of the instruction stream, the instruction stream includes instructions for initializing the master processor and checking processor, the instructions are expected to generate at least one miscompare when executed during an initialization sequence at start up time before the master processor and checking processor have been initialized for the first time, wherein an initial execution of the instruction stream comprises execution of the series of instructions for generating the at least one miscompare and restarting execution of the instruction stream, and wherein the restarting comprises a subsequent re-execution of the series of instructions without generating the at least one miscompare.