Patent ID: 8638623

Claim:
A semiconductor storage device, comprising: a memory cell array comprising a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a plurality of memory cells provided in intersection portions of the plurality of word lines and the plurality of bit lines; a plurality of sense amplifiers configured to detect a signal level of the corresponding bit lines; and a timing generation circuit comprising a timing selection circuit configured to select a timing in a preset order from among timings in which each bit line signal in the plurality of bit lines changes, the timing generation circuit being configured to generate activation timing to activate the plurality of sense amplifiers based on the selected timing, wherein the timing selection circuit selects a timing in some order for each group from among the timings in which the plurality of bit line signals change, the timings being divided into a plurality of groups, repeats, one or more times, a process of selecting a timing in some order for each group from among a predetermined number of timings divided into one group or more and selected immediately before, until the single timing is ultimately selected, and sets the single timing ultimately selected as the timing in the preset order, wherein the timing selection circuit comprises: a first timing selection circuit configured to select Y (Y is a positive integer)-th earliest timing for each group from among the timings in which the plurality of bit line signals change, the timings being divided into X (X is an integer equal to 2 or greater) groups in advance; and a second timing selection circuit configured to select Z-th earliest timing from among the X selected Y-th earliest timings, as the timing in the preset order and the timing generation circuit outputs the timing in the preset order as the activation timing.