Patent ID: 8195880

Claim:
A method comprising: sending, by a processor element, a plurality of requests for memory operations to a cache memory, the cache memory including first and second cache banks, the memory operations including load operations and store operations, each load and store operation exhibiting a respective size requirement; arbitrating, by an arbitration mechanism, among the plurality of requests for memory operations to select a particular load operation and a particular store operation for access to the cache memory; arbitrating, by the arbitration mechanism, in a first arbitration stage among the load operation requests in the plurality of requests for memory operations, to provide the particular load operation for access to the cache memory; arbitrating, by the arbitration mechanism, in the first arbitration stage among the store requests, to provide the particular store operation for access to the cache memory; arbitrating, by the arbitration mechanism, in the first arbitration stage among read claim state machine requests, cast out state machine requests and snoop requests to determine a cache arbiter arbitration result; arbitrating, by the arbitration mechanism, in a second arbitration stage that includes first and second arbiters that operate in parallel to provide particular first and second store instructions to a third arbitration stage; commencing, by the arbitration mechanism, the particular load operation on the first cache bank during a first cache cycle; commencing, by the arbitration mechanism, the particular store operation on the second cache bank during the first cache cycle such that both the particular load operation and the particular store operation commence during the same first cache cycle; and performing, by the first and second cache banks, the particular load operation and the particular store operation simultaneously.