Patent ID: 7249296

Claim:
A semiconductor integrated circuit comprising: a memory; an ECC circuit that has an error correction function of N (N is a natural number) bits for output data of the memory; an error detection circuit configured to output a signal indicative of the following fact, if a total of an error bit number n 1 detected by the ECC circuit when a first data pattern in testing target addresses of the memory is read out and an error bit number n 2 detected by the ECC circuit when a second data pattern that is an inversion of the first data pattern in at least a part of the testing target addresses is read out exceeds N; and a BIST circuit configured to read the first data pattern out of the testing target addresses of the memory as a first operation, write the second pattern in at least a part of the testing target addresses as a second operation, and read out the written second data pattern, wherein the first data pattern has been corrected by the ECC circuit and is input to the BIST circuit.