Patent ID: 7884454

Claim:
A semiconductor package assembly, comprising: a lead frame having a first die bonding pad and a plurality of leads; a first semiconductor device bonded to the first die bonding pad wherein the first semiconductor device comprises a vertical discrete semiconductor device; and an electrically isolated conductive trace formed from a layer of conductive material in the top portion of the vertical discrete semiconductor device, wherein the conductive trace is configured to provide an electrically conductive path between a first bond wire and a second bond wire, wherein the first bond wire connects a first end of the electrically isolated conductive trace to a first lead of the plurality of leads, and the second bond wire is connected to a second end of the electrically isolated conductive trace and wherein either the conductive path passes underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or wherein the conductive path results in a reduced length for the first or second bond wires that is less than a predetermined maximum length.