Patent ID: 6888395

Claim:
A semiconductor integrated circuit device, comprising: a first circuit block to which a first supply voltage is to be applied, the first supply voltage being defined by first operating points; a first-stage intermediate circuit to which the first supply voltage is to be applied, and which receives an output of the first circuit block; a second-stage intermediate circuit to which a second supply voltage is to be applied, and receiving an output of the first-stage intermediate circuit, the second supply voltage being defined by second operating points; and a second circuit block to which the second supply voltage is to be applied and which receives an output of the second-stage intermediate circuit, wherein the second circuit block outputs a first-state first control signal to the second-stage intermediate circuit when the first supply voltage is applied to the first circuit block and the first-stage intermediate circuit so that the output of the second-stage intermediate circuit changes in state according to a change in the output of the first circuit block, and wherein the second circuit block outputs a second-state first control signal to the second-stage intermediate circuit when the first supply voltage is not applied to the first circuit block and the first-stage intermediate circuit so that the second-stage intermediate circuit controls its output to a potential of one of the second operating points, and further comprising: a first MOS transistor, the first supply voltage being applied to the first circuit block through the first MOS transistor; and a first controlling circuit which controls a state of the first MOS transistor, wherein the first controlling circuit outputs a first-state second control signal to the first-stage intermediate circuit when the first MOS transistor is to be in an ON state so that the output of the first-stage intermediate circuit is changed in state according to a change of the output of the first circuit block, and wherein the first controlling circuit outputs a second-state second control signal to the first-stage intermediate circuit when the first MOS transistor is to be in an OFF state so that the first-stage intermediate circuit controls its output to a potential of one of the first operating points.