Patent ID: 8288233

Claim:
A method of forming a tri-gate transistor comprising: providing a tri-gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the tri-gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the tri-gate electrode; forming a silicon germanium layer on exposed portions of a top surface and first and second laterally opposite sidewalls of the source drain region; oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region; and wherein the tri-gate electrode comprises a portion of the tri-gate transistor, and wherein the converted portion of the silicon source drain region exerts a compressive stress into all three channels of the tri-gate transistor.