Patent ID: 8471588

Claim:
A semiconductor wafer device, comprising: a semiconductor wafer; a plurality of semiconductor chip portions provided in the semiconductor wafer in an X-direction and in a Y-direction with respect to each reticle unit, each of the semiconductor chip portions having a first identification code generation circuit and a switching circuit configured to control connection between inside and outside of the semiconductor chip portion the first identification code generation circuit configured to generate a first identification code to select the corresponding semiconductor chip portion dicing line areas provided respectively between the semiconductor chip portions arranged in the X-direction and in the Y-direction; second identification code generation circuits each of which is provided at a portion of the dicing line areas within each reticle unit and is configured to generate a second identification code to select the corresponding reticle unit; coincidence detection circuits provided at portions of the dicing line areas within each reticle unit, each of the coincidence detection circuits corresponding to each of the semiconductor chip portions within each reticle unit and being configured to determine whether or not the corresponding first and second identification codes and a chip select signal from the outside coincide with each other; a pad portion provided at a peripheral portion between the semiconductor chip portions and a peripheral edge of the semiconductor wafer, the pad portion having a plurality of test pads to input and output test signals; and a plurality of bus lines provided on the dicing line areas, one ends of the bus lines being connected to the first identification code generation circuit, the switching circuit, the second identification code generation circuit, and the coincidence detection circuit, respectively, the other ends of the bus lines being connected to at least part of the test pads, respectively.