Patent ID: 8351246

Claim:
A circuit for reading programmable memory cells, comprising: a first sense amplifier selectably connected to a first programmable memory cell and having an input connected to a read control signal; a second sense amplifier selectably connected to a second programmable memory cell and having an input connected to the read control signal; a first transistor having a gate terminal connected to a signal corresponding to the read control signal; a second transistor having a gate coupled to a ground reference potential, a source terminal connected to a pumped voltage source of greater magnitude than a power supply voltage (Vcc), and a drain terminal connected to a source terminal of the first transistor; a third transistor having a gate terminal connected to an output of the first sense amplifier and a source terminal connected to a drain terminal of the first transistor; a fourth transistor having a gate terminal connected to an output of the second sense amplifier and a source terminal connected to the drain terminal of the first transistor; a fifth transistor having a source terminal connected to the ground reference potential and a drain terminal connected to a drain terminal of the third transistor; a sixth transistor having a source terminal connected to the ground reference potential, a drain terminal connected to a drain terminal of the fourth transistor, and a gate terminal connected to the drain terminal of the fourth transistor and a gate terminal of the fifth transistor; and an output stage connected to the drain terminals of the third and fifth transistors, wherein the second programmable memory cell is programmed complementary to a state of the first programmable memory cell.