Patent ID: 7814496

Claim:
A system comprising: a memory; a memory controller to coordinate memory operations of the memory; a plurality of virtual machines; and a host controller with a set of registers for each one of the plurality of virtual machines and an interrupt request line for each one of the plurality of virtual machines, each of the sets of registers to be assigned by a virtual machine monitor (VMM) for each one of the plurality of virtual machines, each of the register sets including configuration and operational registers, wherein when a virtual machine accesses a register in the host controller, the access is directed to a register within the set of registers assigned to the virtual machine by trapping of the access by the VMM and propagation of the access by the VMM to the register, wherein at least the configuration register is accessible only by the VMM, and the host controller is to execute a periodic schedule for each interface between the host controller and the plurality of virtual machines and an asynchronous schedule after completion of the periodic schedule for all of the interfaces.