Patent ID: 7183829

Claim:
A semiconductor device comprising: first and second circuit blocks provided on a semiconductor chip and including respective functional elements; a timing adjustment circuit block for adjusting a propagation timing of a transmission signal flowing on a line connecting the first and second circuit blocks to each other; and a comparison control circuit for receiving an input signal input to the first circuit block and an output signal output from the second circuit block which has received the transmission signal, comparing the input signal to the output signal, and controlling the timing adjustment circuit block, wherein the comparison control circuit includes a control circuit for outputting timing adjustment control signals to the timing adjustment circuit block when the comparison result shows that the input signal and the output signal differ from each other, the timing adjustment circuit block includes: a counter circuit for receiving the timing adjustment control signals, and counting and electrically holding the number of the received timing adjustment control signals; a delay element block which includes at least one delay element and in which a delay amount depending on the number of the timing adjustment control signals is added to the transmission signal; and a fuse circuit which includes at least one fuse and holds the number of the timing adjustment control signals in correspondence with the number of fuses which are melted down, wherein an output signal from the counter circuit or an output signal from the fuse circuit is selectively input to the delay element block, and the fuse is melted down based on the output signal from the counter circuit.