Patent ID: 8185855

Claim:
A capacitor-cell in an integrated circuit that is configured by disposing a plurality of cells on a site that is on a chip and that is provided between a power line and a grounding line in a direction of the power line and grounding line, wherein the capacitor cell is disposed in a remaining region on the site, after the plurality of cells are disposed on the site, the capacitor-cell comprises a gate poly for accumulating capacitance extending up to a planar quadrangular cell-frame that is set for disposing the plurality of cells on the site and that is disposed on at least one of the power line and the grounding line; and a diffusion region extending up to the position of the grounding line and connected to other diffusion region in a vertical direction perpendicular to the direction of the power line and grounding line, and the gate poly includes a margin extending further from the position of the grounding line of the cell-frame by a predetermined length and overlapping the other diffusion region layer being adjacent to the diffusion region.