Patent ID: 8766270

Claim:
A pixel structure comprising: a substrate having a capacitor region, a first device region and a second device region; a first polysilicon pattern located in the first device region and having a first source region, a first drain region, and a first channel region; a first insulating pattern located on the first polysilicon pattern, wherein a thickness of the first insulating pattern located on the first source region, the first drain region and the first channel region is the same, wherein the first source region and the first drain region have N-type doping; a second polysilicon pattern located in the second device region and having a second source region, a second drain region, and a second channel region; a third polysilicon pattern located in the capacitor region; a second insulating pattern located on the second polysilicon pattern, the first insulating pattern being separated from the second insulating pattern, wherein a thickness of the second insulating pattern located on the second channel region is greater than a thickness of the second insulating pattern located on the second source region and the second drain region, wherein the second source region and the second drain region have P-type doping; a third insulating pattern located on the third polysilicon pattern, wherein a thickness of the third insulating pattern is smaller than the thickness of the second insulating pattern located on the second channel region and is smaller than the thickness of the first insulating pattern, and the third insulating pattern is separated from the second insulating pattern and the first insulating pattern, wherein the third polysilicon pattern has P-type doping; insulating layer covering the first insulating pattern, the second insulating pattern and the third insulating pattern; a first gate located on the insulating layer above the first channel region; a second gate located on the insulating layer above the second channel region; a capacitor electrode located on the insulating layer above the third polysilicon pattern; a first covering layer covering the first gate and the second gate; a first source metal layer and a first drain metal layer, located on the first covering layer and electrically connected to the first source region and the first drain region, respectively; a second source metal layer and a second drain metal layer, located on the first covering layer and electrically connected to the second source region and the second drain region, respectively; a second covering layer covering the first source metal layer, the first drain metal layer, the second source metal layer, and the second drain metal layer; and a pixel electrode located on the second covering layer, electrically connected to the first drain metal layer, and electrically connected to the third polysilicon pattern.