Patent ID: 8126050

Claim:
A video signal decoder module for processing video signals of different resolutions, the different resolutions including a first resolution and a second resolution, the first resolution being a higher resolution than the second resolution, the video signal decoder module comprising: a mode control circuit for controlling the decoder module to operate in one of a plurality of different modes of operation, the plurality of different modes of operation including a first mode of operation during which a particular data reduction operation is performed and a second mode of operation during which decoding is performed without performing the particular data reduction operation which is performed during the first mode of operation, the mode control circuit controlling the decoder to operate in the first mode of operation when processing video signals of the first resolution and to operate in the second mode of operation when processing video signals of the second resolution; and a controllable data reduction circuit for performing the particular data reduction operation when the mode control circuit indicates that operation is in the first mode of operation but not when the mode control circuit indicates that operation is in the second mode of operation.