Patent ID: 7701265

Claim:
A semiconductor device wherein a latch signal is reset to an inactive level in response to a power-on reset signal, comprising: a setting asynchronous set-reset SR (set-reset) flip-flop comprising a set terminal and a reset terminal, the reset terminal of the setting asynchronous set-reset SR flip-flop receiving a first reset input based on one of a reset signal and the power-on reset signal; a dummy asynchronous SR (set-reset) flip-flop comprising a set terminal and a reset terminal, the set terminal of the dummy asynchronous SR flip-flop being fixed at a constant potential and being free from receiving any signals, the reset terminal of the dummy asynchronous SR flip-flop receiving a second reset input based on one of the reset signal and the power-on reset signal; and a logic circuit receiving, as an input, an output signal from said setting asynchronous SR flip-flop and an output signal from said dummy asynchronous SR flip-flop, and outputting a latch signal at an inactive level upon receiving at least one of said output signals.