Patent ID: 8445295

Claim:
A method for manufacturing a semiconductor device, comprising steps of: (a) providing a semiconductor wafer, the semiconductor wafer having a main surface partitioned into a plurality of chip areas; (b) forming a semiconductor integrated circuit in each of the chip areas; (c) forming a plurality of electrode pads over a surface of each of the chip areas, the electrode pads including a first electrode pad and a second electrode pad both coupled electrically to the semiconductor integrated circuit; (d) performing an electrical characteristics test for the semiconductor integrated circuit by contacting a probe or a plurality of probes with each of the electrode pads; and (e) after the step (d), dicing the semiconductor wafer to divide the wafer into the individual chip areas, thereby obtaining a plurality of semiconductor chips, wherein the area of the first electrode pad is larger than the area of the second electrode pad and the area of the first electrode pad is smaller than twice the area of the second electrode pad, and wherein the electrical characteristics test in the step (d) includes an electrical characteristics test using a Kelvin contact method in which two probes are brought into contact with the first electrode.