Patent ID: 8520449

Claim:
A semiconductor device that comprises a hierarchical bit line structure comprising: a first local bit line transmitting a first signal of a first memory cell corresponding to a selected word line; a first global bit line electrically connected to the first local bit line through a first switch; a first sense amplifier electrically connected to the first global bit line; a second local bit line transmitting a second signal of a second memory cell corresponding to the selected word line; a second global bit line electrically connected to the second local bit line through a second switch; a second sense amplifier electrically connected to the second global bit line; and a control circuit controlling the first and second sense amplifiers and the first and second switches, wherein, during a first period after the first and second memory cells are simultaneously accessed by activating the selected word line, the control circuit controls the first switch to a conduction state and controls the first sense amplifier to an active state so that the first sense amplifier amplifies the first signal and controls the second switch to a non conduction state, and during a second period after sensing of the first sense amplifier finishes in the first period, the control circuit controls the second switch to a conduction state and controls the second sense amplifier to an active state so that the second sense amplifier amplifies the second signal.