Patent ID: 8026166

Claim:
A method for forming an integrated circuit structure, comprising: forming a conductive interconnect embedded in an interlevel dielectric layer disposed above a semiconductor substrate; depositing a first capping layer comprising Si w C x N y H z upon the conductive interconnect; depositing a second capping layer comprising Si a C b N c H d having a dielectric constant less than about 4 upon the first capping layer; depositing a third capping layer comprising Si w C x N y H z upon the second capping layer, wherein the second capping layer has a lower nitrogen content than the first capping layer, and wherein the second capping layer has a lower nitrogen content than the third capping layer, wherein the second capping layer has a treated layer extending therethrough, between top and bottom surfaces of the second capping layer, wherein the treated layer incorporates includes additional nitrogen atoms incorporated therein with respect to untreated portions of the capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.