Patent ID: 8209366

Claim:
An arithmetic shifter with saturation detection, comprising: an arithmetic shifter for receiving input data and a shift amount indication and in response to the received input data and the received shift amount indication providing shifted output data shifted N bits according to the shift amount indication in a single cycle; a saturation detector, coupled to the arithmetic shifter, for receiving the N most significant bits of the input data from the arithmetic shifter and detecting when overflow or underflow saturation occurs based on the received N most significant bits of the input data and generating a saturation detected signal in response thereto; a saturation value generator for generating a saturation value equal to a maximum saturation value when a most significant bit of the input data is one and for generating a saturation value equal to a minimum saturation value when the most significant bit of the input data is zero; and an output selector, coupled to the arithmetic shifter, the saturation detector and the saturation value generator, for selecting to provide as an output the shifted output data from the arithmetic shifter or the saturation value from the saturation value generator in response to the saturation detected signal from the saturation detector; wherein the saturation detector comprises an underflow detector, an overflow detector and a saturation decision multiplexor for indicating a saturation condition by selecting between an input signal from the underflow detector and a signal from the overflow detector based upon the most significant bit of the input data to the arithmetic shifter, and wherein the saturation detector further comprises a detector for determining when a most significant bit of the arithmetic shifter output and the most significant bit of the input data to the arithmetic shifter are different.