Patent ID: 7207638

Claim:
An integrated circuit for an ink jet printer comprising: a. a state machine ( 20 ) comprising a plurality of sequenced logic circuits, wherein the state machine ( 20 ) receives a tachometer ( 22 ) input, a first comparator output ( 32 ), and a second comparator output ( 33 ), and wherein the state machine ( 20 ) generates a plurality of buffered control signals ( 24 , 25 , 26 , 27 , 28 , 30 ) from the tachometer input ( 22 ); b. a counter ( 34 ) comprising a plurality of sequenced logic circuits to count one of the buffered control signals from the state machine forming a write address ( 36 ); c. a synchronous loadable up-down counter ( 38 ) adapted to receive a cue delay value ( 39 ), wherein the cue delay value is loaded into the synchronous loadable up-down counter ( 38 ) when the synchronous loadable up-down counter receives one of the buffered control signals forming a delayed count ( 40 ); d. an adder ( 42 ) adapted to receive the write address ( 36 ) and the delayed count ( 40 ), wherein the adder ( 42 ) generates a read address ( 44 ); e. a comparator ( 46 ) adapted to compare the delayed count ( 40 ) to the cue delay value ( 39 ), wherein the comparator ( 46 ) sets the first comparator output at a logic high value when the delayed count ( 40 ) is greater than the cue delay value ( 39 ), and wherein the comparator sets the second comparator output at the logic high value when the delayed count ( 40 ) is less than the cue delay value ( 39 ); f. a multiplexer (mux) ( 48 ) adapted to receive the read address ( 44 ), the write address ( 36 ), and one of the buffered control signals, wherein the mux forms a multiplexer output ( 50 ); g. a random access memory (ram) ( 52 ) adapted to receive the multiplexer output ( 50 ); and h. a logic circuit ( 70 ) adapted to receive one of the buffered control signals, wherein the logic circuit outputs a delayed cue signal ( 72 ) to the printing system.