Patent ID: 7852684

Claim:
A page buffer circuit of a memory device including a plurality of MLCs connected to at least a pair of bit lines, the page buffer circuit comprising: a bit line selection unit configured to select one of the pair of bit lines according to an input address; upper and lower data transmission circuits connected to a sensing node connected to the bit line selection unit, and configured to output a program data to the bit line selection unit through the sensing node; a MSB latch circuit connected to the sensing line and the upper data transmission circuit, and configured to store and output a MSB sensing data or a program data; a data I/O circuit unit connected to the MSB latch circuit and further an external data I/O line, and configured to receive data to be programmed into the MSB latch circuit and output the sensing data, stored in the MSB latch circuit, to an external data I/O line; a LSB latch circuit connected to the sensing node, and configured to store a LSB sensing data, or receive a LSB data to be programmed into the MSB latch circuit through the MSB data transmission circuit and store the received LSB data, and output the LSB data to the sensing node; and an inverted output circuit configured to invert the data stored in the LSB latch, and output the inverted data to the MSB latch.