Patent ID: 8426963

Claim:
A power semiconductor package structure, comprising: a carrier; a first power chip having a first surface and a second surface opposing to the first surface, wherein a first control electrode and a first main power electrode are disposed on the first surface, a second main power electrode is disposed on the second surface, and the second surface is disposed on the carrier and electrically connected to the carrier through the second main power electrode; a second power chip having a third surface and a fourth surface opposing to the third surface, wherein a third main power electrode is disposed on the third surface, a fourth main power electrode is disposed on the fourth surface, and the fourth surface is disposed on the first power chip; a first conductive sheet electrically connected to the first main power electrode and the fourth main power electrode; a second conductive sheet electrically connected to the third main power electrode; and a third conductive sheet electrically connected to the first control electrode; wherein, at least a part of the first control electrode is non-covered by the second power chip along a projection direction perpendicular to the carrier.