Patent ID: 7415640

Claim:
An apparatus, comprising: two or more memories having one or more redundant components associated with each memory, the one or more redundant components include at least one redundant column of memory cells; a first processor on-chip with the two or more memories and containing redundancy allocation logic to execute one or more repair algorithms to generate a repair signature for each of the two or more memory; and a repair data container on-chip with the two or more memories and to store a concatenated repair signature, composed by the first processor, that comprises a string of bits arranged as a plurality of fields, one field for each of the memories, (1) for each memory having one or more defective memory cells detected during fault testing, the field consists of (a) a single bit that identifies the memory, followed by (b) a plurality of bits being compressed, repair signature data for the memory, and (2) for each memory with no defective memory cells, the field consists of a single bit that identifies the memory.