Patent ID: 7389218

Claim:
A hardware and software co-simulation method for verifying access mechanism for a cache, comprising: performing a software simulation for a software modeling of the cache; performing a hardware simulation for a hardware modeling of the cache; adding at lease one way buffer into the software modeling; issuing a trigger event for reading request, when a data memory of the hardware modeling is fully filled, and an address to be accessed is ‘miss’ and a read request is issued to a main memory; issuing a trigger event for reading completion when the hardware modeling obtains the data from the main memory at the address to be accessed; storing the data of the address to be accessed into the way buffer of the software modeling when the software modeling obtains the trigger event for reading request; writing the data from the way buffer into a data memory of the software modeling when the software modeling obtains the trigger event for reading completion; and comparing verification results of the software simulation and the hardware simulation.