Patent ID: 7869246

Claim:
A bit line decoder for sensing states of memory cells of a memory array, the bit line decoder comprising: control devices that selectively communicate with bit lines and that are arranged in a multi-level configuration having a plurality of levels, wherein each of said levels includes a plurality of said control devices connected to each other in series forming one or more junctions, and each of said one or more junctions in one of said levels is directly connected to a respective one of said bit lines; a control module that selects from said bit lines a first bit line and a second bit line associated with a memory cell located in said memory array when determining a state of said memory cell, and generates first control signals that deselect one or more of said control devices at each of said levels, wherein when said one or more control devices at each of said levels are deselected, a first group of said bit lines including said first bit line is charged to a first potential and a second group of said bit lines including said second bit line is charged to a second potential; and an isolation circuit to isolate a first one of said levels from a second one of said levels, wherein said isolation circuit includes a plurality of isolation devices having (i) first ends that communicate with said control devices of said first one of said levels and (ii) second ends that communicate with said control devices of said second one of said levels.