Patent ID: 7109110

Claim:
A partially manufactured semiconductor device comprising: a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface; a first oxide layer formed over the first main surface with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench being etched through the oxide layer into the semiconductor substrate through openings in the mask forming mesas, each first trench having a first extending portion extending from the first main surface toward the heavily doped region to a first depth position relative to the first main surface, the at least one second trench having a second extending portion extending from the first main surface toward the heavily doped region to a second depth position relative to the first main surface, each mesa having a sidewall surface, each of the plurality first trenches and the at least one second trench being separated from adjacent trenches by one of the mesas, the at least one second trench being deeper and wider than each of the plurality of first trenches; a second oxide layer formed over an area of mesas and the plurality of first trenches, the second oxide layer covering the top of each mesa and sealing the top of each of the plurality of first trenches and the at least one second trench at an edge of the area containing the mesas and the plurality of first trenches; a layer of masking material selected from a group including a photoresist, a nitride, a metal, and polysilicon, deposited over a preselected area of an edge termination region adjacent to an active region containing at least the area of mesas and the plurality of first trenches, and partially over the at least one second trench at an edge of the area of the active region containing the mesas and the plurality of first trenches, the edge termination region containing a portion of the at least one second trench, the active region being the area on which a semiconductor device will be formed and the termination region being an area which provides insulation between cells of semiconductor devices; the area of mesas and the plurality of first trenches not covered by the masking layer having the oxidant seal removed over the plurality of trenches including the at least one second trench; an overhang area that includes the masking material and that is formed by a wet process etch which removes areas of the oxide layer not protected by the masking material, the overhang area extending partially over the at least one second trench; and implanted areas, including the sidewalls of each trench in the active region, which form P-N junctions along the first depth direction of each of the plurality of first trenches and part of the at least one second trench along the second depth direction.