Patent ID: 8532796

Claim:
A method for processing a wafer comprising: receiving, by a processing system, a first set of patterned wafers and associated contact-etch (CE) data, each patterned wafer having a plurality transistor stacks and a plurality of additional layers thereon; selecting a first patterned wafer from the first set of patterned wafers; establishing a first double-pattern-contact-etch (DPCE) processing sequence for the selected first patterned wafer using the CE data; determining if the first DPCE processing sequence includes a first contact-etch procedure; performing the first contact-etch procedure when the first DPCE processing sequence includes the first contact-etch procedure, wherein a second set of patterned wafers is created when the first contact-etch procedure is performed using the first set of patterned wafers; performing a first corrective action when the first DPCE processing sequence does not include the first contact-etch procedure; determining if the first DPCE processing sequence includes an Ion Energy Optimized (IEO)-etch procedure; performing the IEO-etch procedure when the first DPCE processing sequence includes the IEO-etch procedure, wherein the IEO-etch procedure uses a new etch subsystem having a new process chamber configured therein; and performing a new corrective action when the first DPCE processing sequence does not include the IEO-etch procedure.