Patent ID: 7847759

Claim:
A semiconductor circuit comprising: a logic circuit block that sequentially shifts and outputs a signal to be output to scanning lines in synchronization with a clock signal, the logic circuit block including a clock control circuit, a clock generating circuit, a unit shift circuit, a bidirectional transfer circuit, a NAND circuit, and an inverter circuit; an external interface circuit block including a level shift circuit that boosts a low-amplitude signal from the logic circuit block to a high-amplitude signal and a buffer circuit that drives the scanning lines; and power wiring lines that supply a plurality of reference potentials, wherein the logic circuit block and the external interface circuit block are both connected to a common power wiring line that is one of the power wiring lines and supplies a common reference potential, the current consumption of the logic circuit block and the external interface circuit block are different, and a width of the common power wiring line that is supplied to the logic circuit block being different than a width of the common power wiring line that is supplied to the external interface circuit block with a width of each wiring formed according to the current consumption respectively.