Patent ID: 7920026

Claim:
An output driver system that is responsive to a differential input signal to generate a drive current for an output transistor, wherein the output driver system is arranged to dynamically boost the drive current, the output driver system comprising: a differential amplifier block that is arranged to generate a first current (I 1 ) in response to the differential input signal, wherein the first current (I 1 ) has a first magnitude corresponding to a sum (I+S), wherein I corresponds to a DC current portion from the differential amplifier block and S corresponds to a signal varying portion from the differential amplifier block; a first gain block that is arranged to generate a second current (I 2 ) in response to the first current, wherein the second current (I 2 ) has a second magnitude that is related to the first magnitude by a scaling factor; a threshold detector block that is arranged to generate a control signal in response to a comparison between the first magnitude of the first current (I 1 ) and a threshold level; a second gain block that is arranged to generate a third current (I 3 ) and that is responsive to the control signal, wherein the third current (I 3 ) has a third magnitude, and wherein the second gain block is arranged such that the third current (I 3 ) is approximately zero when the first magnitude of the first current (I 1 ) is below the threshold level and non-zero when the first magnitude of the first current (I 1 ) is above the threshold level; a bias current block that is arranged to generate a nominal biasing current (IB) for the output transistor; a current mirror block that is arranged to generate a fourth current (I 4 ) having a fourth magnitude that is proportional to a difference (I−S) according to the scaling factor; and a summer block that is arranged to combine the nominal biasing current (IB), the second current (I 2 ), the third current (I 3 ), and the fourth current (I 4 ) to generate a biasing current (IOUT) for the output transistor, wherein the summer block is arranged such that IOUT=IB+I 2 +I 3 −I 4 .