Patent ID: 8792278

Claim:
A non-volatile semiconductor memory device comprising: a cell array including a plurality of first wirings, a plurality of second wirings that intersects the plurality of first wirings, and memory cells that are formed at intersections of the first wirings and the second wirings and are connected between the first and second wirings; a first contact plug that comes into contact with a side portion of one of the first wirings provided at a first position and extends in a laminated direction to a layer on which one of the second wirings provided at a second position higher than the first position is formed; a second contact plug that comes into contact with a side portion of another of the second wirings provided at a third position between the first position and the second position and extends in the laminated direction to the layer; a third contact plug that comes into contact with a side portion of another of the first wirings provided at a fourth position between the third position and the second position and extends in the laminated direction to the layer; and a fourth contact plug that extends in the laminated direction to the layer, and does not come into contact with a side portion of the first wirings and a side portion of the second wirings, wherein a bottom surface of the first contact plug, a bottom surface of the second contact plug, a bottom surface of the third contact plug, and a bottom surface of the fourth contact plug come into contact with each of portions on which yet another of the second wirings provided at a fifth position lower than the first position is formed, respectively.