Patent ID: 8787498

Claim:
A system for enhanced carrier suppression, the system comprising: a digital logic block that receives a current version of a first signal, a delayed version of the first signal, a current version of a second signal and a delayed version of the second signal, the digital logic block configured to generate a cover sequence that includes only a subset of transitions from the current version of the first signal and the current version of the second signal, wherein the subset of transitions is less than all transitions from the current version of the first signal and the current version of the second signal, the digital logic block further configured to generate an altered version of the first signal and an altered version of the second signal that reflect transitions that remain after the subset of transitions have been removed; a mixer that is communicatively coupled to the digital logic block, the mixer configured to receive the cover sequence and configured to generate a modulated cover sequence by modulating a radio frequency (RF) carrier with the cover sequence, wherein the mixer includes a binary phase shift keyed (BPSK) modulator; a modulator that is communicatively coupled to the digital logic block, the modulator configured to receive the altered version of the first signal and the altered version of the second signal, the modulator configured to receive the modulated cover sequence as an RF carrier input, the modulator further configured to generate an RF output by modulating the modulated cover sequence with the altered version first the first signal and the altered version of the second signal; and a delay component coupled to the digital logic block and the modulator, the delay component configured to provide path equalization delays to the altered version of the first signal and the altered version of the second signal, wherein the system exhibits 40 dB of carrier suppression.