Patent ID: 8099269

Claim:
A method of estimating aging of a circuit having a plurality of transistors, comprising: identifying initial bias parameters for the transistors of the circuit; simulating the circuit using the identified initial bias parameters; deriving modified bias parameters for the transistors of the circuit in accordance with the simulation; replacing the transistors with aging subcircuits, the aging subcircuits containing aging models; subsequently simulating the circuit by inputting the modified bias parameters into the aging models; and determining a result representative of the aging of the circuit in response to the subsequent simulation, wherein the steps of simulating comprise applying a SPICE circuit simulation and wherein the step of identifying comprises forming a netlist of circuit elements, the netlist containing nominal bias values for elements of the circuit, and modifying the netlist with the modified bias parameters prior to the subsequent simulation, the modified netlist being representative of the condition of the aging subcircuits.