Patent ID: 7678619

Claim:
A method for manufacturing thin film transistors, comprising: forming a first conductive layer on a transparent substrate; patterning the first conductive layer to form at least a gate electrode and at least a first conductive wire layer, so that the gate electrode and the first conductive wire layer are electrically connected; sequentially depositing a first dielectric layer, a semiconductor layer, and a second dielectric layer to cover the transparent substrate, the gate electrode, and the first conductive wire layer; forming a photoresist layer on the second dielectric layer; patterning the photoresist layer by a photomask, so that the photoresist layer on the second dielectric layer above the gate electrode is thicker than that above the transparent substrate, and the second dielectric layer above the first conductive wire layer is exposed; removing a part of the photoresist layer, the second dielectric layer and the semiconductor layer so that a first opening is formed in the second dielectric layer and the semiconductor layer to expose the first dielectric layer on the first conductive wire layer, and the photoresist layer having a reduced thickness is formed on the second dielectric layer above the gate electrode; removing a part of the photoresist layer, a part of the second dielectric layer, a part of the semiconductor layer and a part of the first dielectric layer so that a stack, which is composed of a passivation layer and a channel region above the gate electrode, is formed above the gate electrode, and a second opening in the first dielectric layer is formed to expose the first conductive wire layer, wherein the passivation layer is formed by the second dielectric layer and the channel region is formed by the semiconductor layer; forming ohmic contact layers on sidewalls of the stack above the gate electrode; forming a transparent conductive layer to cover the first conductive wire layer, the ohmic contact layer, and the first dielectric layer; and patterning the transparent conductive layer to define a source/drain on both sides of the channel region, a pixel electrode, and a second conductive wire layer, wherein one of the source/drain is electrically connected to the pixel electrode.