Patent ID: 8549389

Claim:
A device for operating a 1553 serial data bus, the device comprising: a first logic circuit implementing a primary 1553 function, the first logic circuit coupled to a 1553 bus transceiver and a primary memory; a second logic circuit implementing a secondary 1553 function, the second logic circuit coupled to the 1553 bus transceiver and a secondary memory; and a checking mechanism coupled to the first logic circuit and the second logic circuit; wherein the first logic circuit and the second logic circuit are coupled to a self-checking processor pair; wherein when outgoing data for transmission over a 1553 bus via the 1553 bus transceiver is received from a master processor of the self-checking pair, the first logic circuit stores the outgoing data into the primary memory and the second logic circuit stores the outgoing data into the secondary memory; wherein the primary 1553 function formats the outgoing data stored in the primary memory into a first 1553 formatted message and operates the 1553 bus transceiver to write the first 1553 formatted message to the 1553 bus; wherein the secondary 1553 function formats the outgoing data stored in the secondary memory into a second 1553 formatted message; wherein the checking mechanism compares the first 1553 formatted message to the second 1553 formatted message and generates an error indication when the first 1553 formatted message does not match the second 1553 formatted message.