Patent ID: 8179714

Claim:
A nonvolatile storage device comprising: a semiconductor substrate which has a region of a first conductivity type; a memory cell array which includes memory cells each of which includes a variable resistance element and a transistor that are connected in series and formed above said semiconductor substrate; a selection circuit which selects, from among said memory cells included in said memory cell array, at least one memory cell by applying a voltage pulse to a gate of said transistor included in said at least one memory cell; a write circuit which applies a voltage pulse for writing to said variable resistance element included in said at least one memory cell selected by said selection circuit, via said transistor included in said at least one memory cell; and a substrate bias circuit which applies a first bias voltage to said semiconductor substrate, wherein said variable resistance element included in each of said memory cells includes: a first electrode; a second electrode; and a variable resistance layer which is interposed between said first and second electrodes and whose resistance state reversibly changes between a low resistance state and a high resistance state based on a voltage pulse applied between said first and second electrodes, said transistor included in each of said memory cells is formed within the region of the first conductivity type of said semiconductor substrate, and includes: a first diffusion region of a second conductivity type; the gate; and a second diffusion region of the second conductivity type, the second conductivity type having a polarity which is reverse to a polarity of the first conductivity type, and said substrate bias circuit applies, to said region of the first conductivity type of said semiconductor substrate, the first bias voltage in a forward direction with respect to said first and second diffusion regions, when said write circuit applies the voltage pulse for writing between said first and second electrodes included in said variable resistance element included in said at least one memory cell selected by said selection circuit.