Patent ID: 8055930

Claim:
An integrated circuit device comprising: a main clock signal input pad configured to receive a main clock signal having a main clock frequency, wherein the main clock signal input pad is configured to receive the main clock signal from outside the integrated circuit device; a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, wherein the high speed clock signal input pad is configured to receive the high speed clock signal from outside the integrated circuit device; a frequency divider configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal received from outside the integrated circuit device wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase; and a phase controller configured to select one of the preliminary internal clock signals having a phase most closely matched with a phase of the main clock signal received from outside the integrated circuit device, and configured to translate the preliminary internal clock signals to internal clock signals so that the preliminary internal clock signal having the phase most closely matched with the phase of the main clock signal is translated as a primary internal clock signal, so that the internal clock signals have the main clock frequency.