Patent ID: 7518193

Claim:
A semiconductor structure comprising: a substrate; a first device on said substrate and comprising a first n-type transistor and a first p-type transistor; a second device on said substrate adjacent said first device, wherein said second device comprises a second n-type transistor and a second p-type transistor; and a dual-strain layer over said first device and said second device, wherein said dual-strain layer comprises: a first tensile section over said first n-type transistor and a compressive section over said first p-type transistor; and an additional tensile section over said second device, wherein said additional tensile section comprises a relaxed region above said second p-type transistor and not above said second n-type transistor and wherein said relaxed region comprises a predefined area that minimizes degradation of performance of said second p-type transistor and that further minimizes variability in transconductance of said second p-type transistor and said second n-type transistor in said second device so as to avoid degradation of performance and stability of said second device.