Patent ID: 7444275

Claim:
A method of modeling a cell of an integrated circuit design, the method comprising the steps of: generating a polynomial model of a modeling space by fitting to cell information comprising measured data points associated with one or more independent variables; generating error values indicative of error between the measured data points and the polynomial model of the modeling space; partitioning the modeling space into domains having boundaries based on the error values; and for at least a given one of the domains, performing the following steps: (i) generating a first polynomial model of given domain by fitting to a plurality of data points including a subset of the measured data points and at least one additional data point determined by interpolation from one or more of the measured data points in the subset; (ii) generating error values indicative of error between the measured data points of the subset and the first polynomial model of step (i); (iii) generating a shifted model by applying correction factors determined from the error values of step (ii) to respective data points taken from the first polynomial model of step (i), wherein for a given such data point corresponding to the additional data point of step (i), the associated correction factor is determined by interpolation from one or more of the error values of step (ii); and (iv) generating a second polynomial model of the given domain by fitting to a plurality of data points from the shifted model of step (iii); wherein the integrated circuit design is processed using at least the second polynomial model of the given domain in order to determine if the integrated circuit design meets specified performance criteria.