Patent ID: 8339893

Claim:
A static random access memory (SRAM) array comprising: a plurality of SRAM cells, an SRAM cell comprising: a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio; and a second read port, the second read port having a third beta ratio that is approximately the same as the first beta ratio; wherein data read from the first read port has a polarity that is opposite to a polarity of data read from the second read port, and wherein the SRAM array further comprises a first read sense amplifier stage connected to the first read port, and a second read sense amplifier stage connected to the second read port, wherein the second read sense amplifier stage is configured to correct the polarity of data read from the second read port to a polarity that is the same as the data read from the first read port.