Patent ID: 8503597

Claim:
A dual-path phase lock loop (PLL) circuit comprising: an oscillator configured to adjust a frequency of an output signal based at least in part on a voltage difference between a first signal and a second signal; a phase detector configured to generate a first control signal and a second control signal based at least in part on a phase difference between a reference signal and the output signal; and a low-pass filter (LPF) coupled to the phase detector, wherein the LPF comprises: a first stage configured to convey the first signal and convey an intermediate signal; and a second stage coupled to receive the intermediate signal; wherein in response to detecting the PLL is in a locked state, the second stage is configured to convey the second signal based at least in part on the intermediate signal and an intervening impedance element; and wherein in response to detecting the PLL is not in a locked state, the second stage is configured to convey the second signal based at least in part on the intermediate signal while bypassing the intervening impedance element.