Patent ID: 6862015

Claim:
A liquid crystal display device having a liquid crystal display panel, a plurality of cascade-connected liquid crystal drive circuits for sequentially transferring a signal, and a plurality of signal lines formed over an edge portion of the liquid crystal display panel for transmitting a signal between any two of the drive circuits, wherein each of the liquid crystal drive circuits comprises: an image input terminal connected with one of the signal lines to receive an external image signal being input thereto as an internal image signal into said each of the liquid crystal drive circuits; a clock input terminal connected with another one of the signal lines to receive an external clock signal being input thereto; a clock compensation circuit for generating an internal clock signal based on the external clock signal thereby compensating for a duty ratio deviation of the external clock signal, said internal clock signal swinging from a first voltage to a second voltage lower than the first voltage; a data storage circuit for storing therein the internal image signal at a timing of a voltage change from the first voltage to the second voltage as a first image signal and at a timing of a voltage change from the second voltage to the first voltage of the internal clock signal as a second image signal; a first data bus for transmitting the first image signal from the data storage circuit; a second data bus for transmitting the second image signal from the data storage circuit; a voltage select circuit for selecting a voltage according with he first and the second image signals to drive the liquid display panel; and a clock signal output circuit for outputting the internal clock signal as a subsequent external clock signal and for outputting the first image signal and the second image signal in sequence as a subsequent external image signal to a subsequent liquid crystal drive circuit, said clock signal output circuit having a delay circuit, wherein the delay circuit delays the internal clock signal to become the subsequent external clock signal to the subsequent liquid crystal drive circuit so as to provide phase margins thereof in a dual-edge accept scheme.