Patent ID: 7783663

Claim:
A data processing system, comprising: a bus system; a plurality of host bus adapters, wherein each host bus adapter within the plurality of host bus adapters forms a path to one or more of a plurality of devices; a memory connected to the bus system, wherein the memory includes a set of instructions; a processing unit connected to the bus system, wherein the processing unit executes the set of instructions to collect configuration information for a plurality of paths connecting a host to a plurality of devices in response to expiration of a partitioning interval, identify a throughput for each path within the plurality of paths based on the configuration information, identify a load for each device with the plurality of devices based on the configuration information, and selectively disable paths for devices based on the throughput for each path and the load for each device; wherein the processing unit executes the set of instructions to select a highest throughput path from within the plurality of paths, identify a highest load device connected to the highest throughput path from within the plurality of devices, and attempt to disable the highest throughput path for each device, other than the highest load device, connected to the highest throughput path; and wherein the processing unit executes the set of instructions to identify, for each path within the plurality of paths, a device list defining a subset of devices within the plurality of devices connected to a given path and identify, for each device within the plurality of devices, a path list defining a subset of paths within the plurality of paths connected to a given device.