Patent ID: 8413082

Claim:
A method for designing masks adapted to the forming of integrated circuits in a considered technology, comprising the steps of: (a) forming a first test file comprising a set of randomly-generated configurations of integrated circuit elements not known to comply with design rule manuals; (b) forming a second test file comprising all the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) transforming the second test file by means of a set of logical operations implemented by computing means to obtain a first mask file representative of a set of masks necessary to obtain an integrated circuit associated with the second test file; (d) testing, post generation, the first mask file for compliance with predetermined criteria and, if a post-generation test result is negative, modifying and adapting the design rule manuals and/or the logical operations according to the post-generation test result; and (e) reiterating steps (b) to (d) as many times as necessary until the post-generation test result of step (d) is positive.