Patent ID: 7800967

Claim:
A semiconductor memory device comprising: a plurality of word lines extending to a first direction; a plurality of bit lines extending to a second direction crossing the first direction; a memory cell array including a plurality of cell blocks each including a plurality of memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, the sense amplifiers reading data stored in the memory cells, or writing data into the memory cells, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers.