Patent ID: 6909149

Claim:
An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, the ESD protection circuit comprising: an SCR for shunting ESD current away from said protected circuitry, said SCR comprising: a substrate; an N-well and an adjacent P-well formed over said substrate and defining a PN junction therebetween; an insulator layer formed over said substrate and electrically isolating said N-well and P-well from said substrate; an N+ cathode region formed in said P-well and for coupling to ground; a P+ anode region formed in said N-well and for coupling to a pad of said protected circuitry; at least one P+ trigger tap region disposed in said P-well and spaced proximate to said N+ cathode region, said at least one P+ trigger tap being adapted to trigger said SCR; and at least one N+ trigger tap region disposed in said N-well and spaced proximate to said P+ anode region, said at least one N+ trigger tap being adapted to trigger said SCR.