Patent ID: 7707532

Claim:
A method for designing an integrated circuit from a user design containing logic gates, the method comprising: assigning, with a computer processing system, each of a plurality of sets of the logic gates to a respective one of a plurality of abstract blocks, wherein each of the plurality of abstract blocks performs a function with the respective assigned set of the logic gates; and placing, with the computer processing system, each of the plurality of abstract blocks into a respective one of a plurality of logic blocks based at least in part on a correspondence between a predetermined functional attribute of the respective logic block and a functional attribute of the respective abstract block, wherein the plurality of logic blocks are grouped into a plurality of logic block clusters, and wherein the respective abstract block satisfies a set of design rules for the respective logic block and the respective logic block cluster in which that abstract block is placed, and wherein placing the respective abstract block into one of the plurality logic block clusters is determined based on an attraction of the abstract block to the cluster, and the attraction measures at least one selected from the group of: a number of nets and connections of nets absorbed into the cluster if the abstract block is placed inside the cluster, and a number of timing critical connections absorbed into the cluster if the abstract block is placed inside the cluster.