Patent ID: 7479803

Claim:
A programmable logic integrated circuit comprising a hard intellectual property block, the hard intellectual property block comprising: a first logic circuit configured to receive data from an external device; a second logic circuit configured to transmit data to the external device; a first state machine configured to output first state machine information depending on selected signals within the first logic circuit; a second state machine configured to output second state machine information depending on selected signals within the second logic circuit; first data registering logic configured to capture the first state machine information, the first data registering logic coupled to at least one data bus, and second data registering logic configured to capture the second state machine information, the second data registering logic coupled to the at least one data bus, wherein the at least one data bus couples with an interface of the programmable logic integrated circuit, and wherein the at least one data bus comprises: a first data bus dedicated to output first state machine information; and a second data bus dedicated to output second state machine information.