Patent ID: 7211902

Claim:
A semiconductor device comprising: a semiconductor substrate; and a bonding pad portion formed on said semiconductor substrate; said bonding pad portion comprising: an insulating film formed on said semiconductor substrate; a first-level conductive pad layer of a large island shape formed on said insulating film; first-level to (n−1)-level (n is an integer of 3 or larger) interlayer insulating films formed on and over said insulating film; second-level to n-level conductive pad layers formed on said interlayer insulating films in areas generally corresponding to an area where said first conductive pad layer was formed; a plurality of small diameter first through holes from the first-level to (n−1) level formed through said first-level to (n−1) level interlayer insulating films; a plurality of first conductive plugs filled in said small diameter first through holes from the first-level to (n−1)-level, said first conductive plugs at each level being conductive and electrically connecting two conductive pad layers adjacent along a normal to a surface of said semiconductor substrate, among said first-level to n-level conductive pad layers disposed on said insulating film, and first-level to (n−1)-level interlayer insulating films; an n-level interlayer insulating film formed on said (n−1)-level interlayer insulating film and covering said n-level conductive pad layer; a large diameter through hole formed through said n-level interlayer insulating film to expose an area of said n-level conductive pad layer; and a bonding pad formed on said n-level interlayer insulating film and n-level conductive pad layer via said large diameter through hole, wherein said small diameter first through holes include ones located in a peripheral area outside of said large diameter through hole.