Patent ID: 8482054

Claim:
A semiconductor memory device, comprising: an element region demarcated by an element isolating portion within a semiconductor substrate; a first gate insulating film provided on the element region; a charge accumulation layer provided on the first gate insulating film; a second gate insulating film which has a first portion covering an upper surface of the charge accumulation layer and a second portion covering a side surface of the charge accumulation layer when a side of a surface on which the element region of the semiconductor substrate is demarcated is an upper side; and a control gate electrode provided above the upper surface and the side surface of the charge accumulation layer via the second gate insulating film, wherein a breakdown voltage of the first portion is higher than a breakdown voltage of the second portion, and the first portion is formed of a first material, the second portion is formed of a second material, and a breakdown voltage per unit film thickness of the first material is higher than a breakdown voltage per unit film thickness of the second material.