Patent ID: 8847221

Claim:
A semiconductor device, comprising: first, second and third internal circuits each formed in a semiconductor substrate; first, second and third through electrodes each formed to penetrate the semiconductor substrate; a wiring supplied with a test voltage in a test mode; a first switch connected between the first internal circuit and the first through electrode; a second switch connected between the second internal circuit and the second through electrode; a third switch connected between the third internal circuit and the third through electrode; and fourth, fifth and sixth switches each having first and second terminals, the first terminals of the fourth, fifth and sixth switches being connected in common to the wiring, and the second terminals of the fourth, fifth and sixth switches being connected respectively to the first, second and third through electrodes; each of the first, second and third switches being rendered nonconductive in the test mode and of fourth, fifth and sixth switches being rendered conductive in the test mode to supply the test voltage respectively to the first, second and third through electrodes.