Patent ID: 7037770

Claim:
A method of manufacturing a semiconductor structure, comprising the steps of: forming, by removing material from an upper surface of a substrate, a p-type field-effect-transistor (pFET) channel and a n-type field-effect- transistor (nFET) channel in a the substrate; providing a first layer of material within the pFET channel having a lattice constant different than the lattice constant of the substrate; providing a second layer of material within the nFET channel having a lattice constant different than the lattice constant of the substrate, the second layer of material being different from the first layer of material; forming an epitaxial semiconductor layer over the first layer of material in the pFET channel and the second layer of material in the nFET channel, the epitaxial semiconductor layer having substantially a same lattice constant as the substrate such that a stress component is created within the pFET channel and the nFET channel.