Patent ID: 7756232

Claim:
A clock and data recovery circuit comprising: a plurality of latch circuits for receiving and sampling an input data; a phase shift circuit for supplying multiple phases of clock signals having mutually distinct phases of said clock signals to said plurality of latch circuits, respectively; and a circuit unit for generating phase control signals for controlling a delay or an advance of the multiple phases of clock signals supplied to said plurality of latch circuits from said phase shift circuit, based on a result of a phase comparison using data sampled by said latch circuits and supplying the generated phase control signals to said phase shift circuit, wherein predetermined ones of the multiple phases of clock signals are set as clock signals for edge detection, each of the predetermined ones for detecting a transition point of an input data signal, the other clock signals being set as data sampling clock signals for sampling the input data signal, respectively, said phase shift circuit adjustably shifting the phases of the clock signals for edge detection and the phases of the data sampling clock signals based on the phase control signals, thereby recovering the data and the clock signal, said circuit unit including a first up/down counter which is subjected to an up/down control based on the result of the phase comparison, said circuit unit performing control so that control over the phases of the clock signals for edge detection is performed by an associated phase control signal in accordance with a count value of said first up/down counter, and control over the phases of the data sampling clock signals is performed by associated phase control signals from a second up/down counter in step-wise variable control in which the phases of the data sampling clock signals are advanced or delayed according to when a combination of a current count value of said second up/down counter and the result of the phase comparison satisfies a predetermined condition, wherein the shifting of the phases of the data sampling clock signals does not directly follow the count value of said first up/down counter.