Patent ID: 7552360

Claim:
A debug and test system comprising: A. a first bus of signal leads including a test data input lead, a test data output lead, a test clock lead, and a test mode select lead; B. a second bus of signal leads; C. a third bus of signal leads, separate from the first bus of signal leads, including a test data input lead, a test data output lead, a test clock lead, and a test mode select lead; D. serializer circuitry having a first set of leads connected with the first bus of signal leads, a second set of leads connected with the second bus of leads, and a third set of leads; D. multiplexer and demultiplexer circuitry having a control input, a first set of leads connected with the first bus of signal leads, a second set of leads connected with the third set of leads of the serializer circuitry, and a third set of leads that connect with the third bus of signal leads; and E. format select register circuitry having an output connected with the control input of the multiplexer and demultiplexer circuitry.