Patent ID: 7035162

Claim:
A memory device, comprising: a plurality of memory blocks, each block including a plurality of memory cells; a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in the memory blocks; a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks; a plurality of word line decoders coupled to word lines of respective ones of plurality of the memory blocks, each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto; and a plurality of source line decoders coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, a memory block selection signal, and the source line selection signals and to responsively generate source line signals on the source lines coupled thereto.