Patent ID: 8004326

Claim:
A digital phase lock loop circuit comprising: a voltage controlled oscillator for providing an output clock signal having a first frequency in response to control signals; a divider for converting the output clock signal into an internal clock signal having a second frequency; a digital charge pump circuit for generating a phase offset word corresponding to a difference in phase between the internal clock signal and a reference clock signal, the digital charge pump circuit including a quantizing circuit for generating the phase offset word in response to a phase difference between active edges of the internal clock signal and the reference clock signal; a phase frequency detector for providing a first signal from a first output terminal and a second signal from a second output terminal, the phase frequency detector including logic circuitry for driving the first signal to an active logic level in response to an earliest active edge between the reference clock signal and the internal clock signal, the first signal being driven to an inactive logic level in response to a latest active edge between the reference clock signal and the internal clock signal, the difference in time between the earliest active edge and the latest active edge corresponding to the phase difference between the internal clock signal and the reference clock signal, the logic circuitry including an XOR gate having a first input for receiving the reference clock signal, a second input for receiving the internal clock signal, and a first output corresponding to the first output terminal, and an inverter having a third input connected to the first output and a second output corresponding to the second output terminal; and, a digital processing circuit for receiving the phase offset word and for generating the control signals in response to the phase offset word.