Patent ID: 8230143

Claim:
An apparatus comprising: a control circuit configured to present a plurality of pairs of signals in response to (i) one or more input data signals operating at a first clock speed, (ii) one or more input address signals operating at said first clock speed, and (iii) an input clock signal operating at a second clock speed, wherein (a) a first one or more of said plurality of pairs of signals comprise internal data signals, (b) a second one or more of said plurality of pairs of signals comprise internal address signals, (c) a second signal in each of said plurality of pairs of signals comprises a clock signal operating at said second clock speed, and (d) said internal data signals and said internal address signals operate at said second clock speed; a buffer circuit configured to generate a buffered signal in response to each of said plurality of pairs of signals, wherein each of said buffered signals operates at said second clock speed; and a memory circuit configured to read and write data at said second clock speed in response to said buffered signals.