Patent ID: 8810499

Claim:
A shift register unit, comprising: twelve transistors M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8 , M 9 , M 10 , M 11 , and, M 12 ; one capacitor C 1 ; four signal input terminals INPUT, RESET, CLK, CLKB; one signal output terminal OUTPUT; and one power supply terminal VSS, and connection relationships among them are as follows: a gate of the M 1 is connected to both the signal input terminal INPUT and gates of the M 6 and M 9 , and a source of the M 1 is connected to drains of the M 2 and M 11 ; a gate of the M 2 is connected to the signal input terminal RESET; both a gate and a drain of the M 5 are connected to the signal input terminal CLKB, and a source of the M 5 is connected to drains of the M 6 and M 7 ; a gate of the M 8 is connected to the source of the M 5 , a drain of the M 8 is connected to both drains of the M 9 and M 10 and gates of the M 11 and M 12 ; a drain of the M 3 is connected to the signal input terminal CLK, a gate of the M 3 is connected to one end of the capacitor C 1 and the source of the M 1 , and a source of the M 3 is connected to the other end of the capacitor C 1 , gates of the M 7 and M 10 , drains of the M 12 and M 4 and the signal output terminal OUTPUT; sources of M 2 , M 11 , M 6 , M 7 , M 9 , M 10 , M 12 and M 4 are connected to the power supply terminal VSS, and a gate of the M 4 is connected to the signal input terminal RESET; said shift register unit further comprises two additional signal input terminals: fifth signal input terminal and sixth signal input terminal, a drain of the M 1 is connected to the fifth signal input terminal, and when the gate of the M 1 is at the high level, the signal input terminal at the drain of the M 1 is also at a high level; a source of the M 8 is connected to the sixth signal input terminal, and when the gate of the M 8 is at the high level, the signal input terminal at the source of the M 8 is also at a high level.