Patent ID: 7254076

Claim:
A semiconductor memory device, comprising: a normal cell array comprising a plurality of memory cells arranged in a matrix of rows and columns; a redundant cell array comprising a plurality of memory cells adapted to replace memory cells in the normal cell array; an address input unit adapted to generate an internal address that sequentially changes in response to a counted signal; an address decoding unit for decoding the internal address to specify a memory cell in the normal cell array; a redundancy enable unit adapted to generate a redundancy shift signal that is activated in response to the generation of the internal address corresponding to an embedded address; and a data input/output unit controlled such that input data is provided to the redundant cell array instead of the normal cell array in response to the redundancy shift signal; wherein the embedded address corresponds to an internal address preceding the internal address specifying a memory cell in the normal cell array to be repaired by a number of shift clocks, wherein the number of shift clocks is defined by an integer equal to or greater than 1.