Patent ID: 7134005

Claim:
A microprocessor, comprising: a branch target address cache (BTAC), configured to cache, for each of a plurality of previously executed branch instructions: a prediction of whether said branch instruction will be taken and is present in a cache line of instruction bytes provided by an instruction cache in response to a fetch address, a target address of said branch instruction, and a location of an opcode byte of said branch instruction within said cache line; wherein said BTAC is further configured to provide said prediction, said target address, and said location in response to said fetch address; an instruction buffer, coupled to receive said cache line from said instruction cache and to mark a byte in said cache line within said instruction buffer indicated by said location provided by said BTAC if the microprocessor branches to said target address provided by said BTAC based on said prediction; an instruction decoder, coupled to said instruction buffer, configured to format said instruction bytes in said cache line into formatted instructions; and prediction check logic, coupled to said instruction decoder, configured to indicate the microprocessor erroneously branched to said target address if said instruction decoder indicates said marked byte is in a non-opcode location within one of said formatted instructions.