Patent ID: 8349726

Claim:
A method of fabricating a structure for a semiconductor device, the method comprising, forming a second low-k dielectric layer, having an upper surface, on an etch stop layer, the etch stop layer formed on and covering a first low-k dielectric layer and a covered portion of a first metal layer; etching a via in the second low-k dielectric layer, wherein the via aligns with an exposed portion of the first metal layer not covered by the etch stop layer, and wherein the via has sidewalls that extend from the upper surface of the second low-k dielectric layer to the first metal layer; depositing a first layer of material on the exposed portion of the first metal layer and on the sidewalls of the via using an atomic layer deposition process that includes alternating pulses of the first and second precursors, at least one of which includes a halogen, the pulses of the first and second precursors separated from each other by a purge pulse consisting of an inert gas; and using residual halogen from the deposition of the first layer of material to catalyse growth of a second layer of material on the first layer.