Patent ID: 7254049

Claim:
A data comparison circuit, comprising: a first and second plurality of data input signal lines; a plurality of bit comparators coupled to the first and second plurality of data input signal lines; a common error signal line coupled to each of the plurality of bit comparators; and a pull-up circuit coupled to the common error signal line; wherein each bit comparator further comprises: a first series-coupled transistor chain, having a first and second transistors coupled in series, wherein the first series-coupled transistor chain is coupled to the common error signal line and to a low signal level power rail, and where a control gate of the first transistor is coupled to a normal signal of the first data input and a control gate of the second transistor is coupled to a inverted signal of the second data input; and a second series-coupled transistor chain, having a first and second transistors coupled in series, wherein the second series-coupled transistor chain is coupled to the common error signal line and to a low signal level power rail, and where a control gate of the first transistor is coupled to a inverted signal of the first data input and a control gate of the second transistor is coupled to a normal signal of the second data input.