Patent ID: 7617473

Claim:
A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing comprising: providing a design of an integrated circuit layout having a plurality of segments of critical width; creating a first mask design using a computer system, by aligning mask features of alternating phase shifting regions or sub-resolution assist features (SRAFs) used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, the first mask design meeting predetermined manufacturability design rules comprising process window considerations, minimum phase width and minimum phase-to-phase spacing or SRAF size and spacing; creating a second mask design using the computer system, by aligning mask features of alternating phase shifting regions or sub-resolution assist features (SRAFs) used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, the second mask design meeting predetermined lithographic design rules in regions local to the critical width segments, the second mask design comprising a subset of the first mask design; identifying design features of the second mask design that violate the predetermined manufacturability design rules; creating a third mask design using the computer system, derived from the second mask design wherein the mask features of the second mask design that violate the predetermined manufacturability rules are selectively replaced by mask features from the first mask design so that the third mask design meets the predetermined manufacturability design rules.