Patent ID: 7177975

Claim:
A memory system, comprising: a plurality of memory groups, each of said memory groups comprising a plurality of memory sectors, each of said memory sectors comprising a plurality of memory cells, wherein the number of memory sectors in each memory group is configurable; a plurality of group tags, each of said group tags corresponds to one of said memory groups, each of said group tags indicating whether the memory cells under the corresponding memory group are erasable; and a plurality of sector tags, each of said sector tags corresponds to a memory sector, each of said sector tags indicating whether the memory cells under the corresponding memory sector are erasable, wherein all the memory cells belonging to one memory sector are erasable when either the corresponding sector tag or the corresponding group tag of the memory sector is set; wherein any combination of memory sectors in a memory group can be simultaneously erased, and any combination of the memory groups can be simultaneously erased; and wherein in response to too few tags being set, a received erase command is aborted.