Patent ID: 7564313

Claim:
A phase locked loop (PLL) system for generating an output signal according to a first reference signal, the PLL system comprising: a clock generator receiving the first reference signal and a first frequency-divided signal to generate the output signal according to a phase difference between the first reference signal and the first frequency-divided signal; a phase-shift detector generating a phase adjusting signal; a phase-controllable frequency divider coupled to the clock generator and the phase-shift detector for dividing the frequency of the output signal by a frequency dividing ratio to generate the first frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the first frequency-divided signal; and at least a second phase locked loop (PLL) coupled to the output signal, for generating a second output signal according to the output signal; wherein the phase-controllable frequency divider adjusts the frequency dividing ratio according to the phase adjusting signal.