Patent ID: 7838359

Claim:
A method, comprising: forming a first transistor element comprising a first gate electrode structure including a first sidewall spacer structure having a first width; forming a second transistor element comprising a second gate electrode structure including a second sidewall spacer structure having a second width other than said first width; forming a hard mask to expose said first transistor element and cover said second transistor element; forming a first metal silicide in said first transistor element using said hard mask; forming a first stress-inducing contact liner layer above said first transistor element and said second transistor element after forming said first metal silicide; selectively removing said first stress-inducing contact liner layer above said second transistor element using said hard mask; removing said hard mask above said second transistor element; forming a second metal silicide in said second transistor element after forming said first stress-inducing contact liner; and forming a second contact liner layer above said first and second transistor elements, said first stress-inducing contact liner layer and said second contact liner layer differing in at least one of material composition and or internal stress.