Patent ID: 7382025

Claim:
A semiconductor structure for the protection of integrated circuits from ESD pulses, the structure comprising: a semiconductor substrate of a first conductivity type and with a first dopant concentration; a well of a second conductivity type and with a second dopant concentration lying within the semiconductor substrate; a first area of the first conductivity type and with a third dopant concentration, wherein at least a first part of the first area lies within the well, wherein the first area lies partially in the well and partially in the substrate outside the well; a second area of the first conductivity type and with a fourth dopant concentration, wherein the second area lies fully within the well and is spaced apart from the first area; and a first protective zone of the second conductivity type and with a fifth dopant concentration disposed in the well between the first area and the second area, the first protective zone being spaced from the first area by the well and being spaced from the second area by the well.