Patent ID: 8330491

Claim:
An electronic device comprising: a high voltage tolerant circuit having: an input terminal for receiving an input signal, a first node and a second node, wherein the second node is coupled to an input of a receiver, a first NMOS transistor and a first PMOS transistor coupled in parallel between the input terminal and the second node, a second PMOS transistor coupled between the input terminal and the first node, and a second NMOS transistor coupled with one of its terminals to the first node, wherein the gate of the first NMOS transistor is coupled to a supply voltage, wherein the gate of the first PMOS transistor is coupled to the first node, wherein the gate of the second NMOS transistor and the gate of the second PMOS transistor are coupled to the supply voltage, a third NMOS transistor coupled between the supply voltage and the second node, wherein the gate of the third NMOS transistor is coupled to the input terminal, wherein the second terminal of the second NMOS transistor is coupled to the second node.