Patent ID: 8084318

Claim:
A method of fabricating an integrated circuit device, the method comprising: forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions thereof, respectively; etching the semiconductor substrate using the first and second gate patterns as etching masks to define trenches therein adjacent the first and second gate patterns on opposite sides thereof; forming spacer patterns on sidewalls of the trenches extending adjacent to sidewalls of the first and second gate patterns; forming an insulating layer on surfaces of the trenches exposed by the spacer patterns; removing the spacer patterns; and then epitaxially growing p-type source/drain regions in the trenches on the opposite sides of the first gate pattern in the PMOS region to exert a net compressive stress on a first channel region comprising a portion of the substrate therebetween adjacent the first gate pattern; and epitaxially growing n-type source/drain regions in the trenches on the opposite sides of the second gate pattern in the NMOS region to exert a net tensile stress on a second channel region comprising a portion of the substrate therebetween adjacent the second gate pattern.