Patent ID: 7783840

Claim:
A memory system control apparatus that controls coherency between a cache memory and a main memory, the cache memory being provided for each of a plurality of processors of a multiprocessor system and storing status of a line of the cache memory as any one of statuses including at least “Modified” and “Exclusive”, the memory system control apparatus comprising: a cache-status maintaining unit that stores address information of data stored in each entry of the cache memory, and maintains a utilization status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”, wherein when the “Modified” is stored as the status of a line of the cache memory, the “strongly modified” or the “weakly modified” is maintained, and when the “Exclusive” is stored as the status of a line of the cache memory, the “weakly modified” is maintained even if the status of a line of the cache memory changes from “Exclusive” to “Modified”; a data-fetching-procedure selecting unit that selects, upon receiving a data read request from one of the processors, at least one data fetching procedure based on the address information and the utilization status maintained by the cache-status maintaining unit; a read-data delivering unit that selects latest data from among the data fetched by the fetching procedure selected by the data-fetching-procedure selecting unit, and delivers the latest data selected to a processor that issued the data read request; and a cache-status updating unit that updates, when registering the address information of the data in one of the entries of the cache-status maintaining unit corresponding to the processor that issued the data read request, the utilization status of the entry based on a type of the data read request; wherein when receiving the data read request from a first processor, the cache-status updating unit registers the utilization status of the data as “strongly modified” in the cache-status maintaining unit, the data read request being a type that is issued in order to modify the data by the first processor.