Patent ID: 7864834

Claim:
A method of estimating jitter for a digital frequency synthesizer (DFS) circuit element for use on an integrated circuit, the method comprising: determining a plurality of linear equations, wherein each linear equation comprises a combination of multiplier and divisor attributes and sets an output frequency of the DFS; identifying maximum and minimum values for a slope component and a vertical axis intercept component from the plurality of linear equations; providing an equation, comprising a constant that depends upon an operational mode of the DFS, for determining minimum jitter of the DFS given, at least in part, an input frequency; providing an equation, comprising a constant that depends upon the operational mode of the DFS, for determining maximum jitter of the DFS given, at least in part, an input frequency; and deriving a linear equation for estimating jitter of an output signal of the DFS according to a specified input frequency provided to the DFS and a specified value of the divisor attribute of the DFS, wherein the linear equation for estimating jitter further depends upon the minimum jitter and the maximum jitter.