Patent ID: 8208084

Claim:
An array substrate having a display region and a peripheral circuit region adjacent to the display region, the array substrate comprising: a pixel array disposed in the display region; a plurality of test shorting bars disposed in the peripheral circuit region, wherein the test shorting bars comprises a first type test shorting bar and a second type test shorting bar, and wherein the first type test shorting bar comprises a first trace and a common trace; and a plurality of wires disposed in the peripheral circuit region and electrically connected with the pixel array, wherein each wire comprises a first signal source connection wire, the common trace and a pixel array connection wire, wherein the first trace of the first type test shorting bar is connected with one of first signal source connection wires and one of pixel array connection wires through the common trace, which is used for transmitting driving signals and test signals, and wherein the second type test shorting bar is not connected with any one of first signal source connection wire and any one of pixel array connection wire.