Patent ID: 7898889

Claim:
A nonvolatile semiconductor memory device comprising: a plurality of word lines along a first direction; a plurality of bit lines along a second direction crossing the first direction; a plurality of memory cell transistors whose gates are connected to the word lines and that are serially connected to constitute a plurality of cell strings; a first selective gate line along the first direction; a second selective gate line along the first direction; a cell source line along the first direction; a plurality of first selective transistors connected between one end of the cell strings and the bit lines and whose gates are connected to the first selective gate line; a plurality of second selective transistors connected between the other end of the cell strings and the cell source line and whose gates are connected to the second selective gate line; a plurality of dummy cell transistors arranged along the second direction and serially connected to each other to constitute at least one dummy cell string; at least one dummy bit line along the second direction; at least one first dummy selective transistor connected between one end of the dummy cell string and the dummy bit line and whose gate is connected to the first selective gate line; at least one second dummy selective transistor connected between the other end of the at least one dummy cell string and the cell source line and whose gate is connected to the second selective gate line; a cell source driver for supplying a cell source voltage to the cell source line; and a dummy bit driver for supplying a voltage to the dummy bit line, wherein at a time of writing in a selected memory cell transistor, a voltage of a first dummy bit line selected from the dummy bit lines is driven to a different voltage from a voltage of an unselected bit line, and any of the dummy cell transistors connected to the first dummy bit line is written.