Patent ID: 6909646

Claim:
A semiconductor memory device, including: a first bit line; a second bit line; a first redundant bit line; a second redundant bit line; a plurality of first memory cells connected to said first bit line; a plurality of second memory cells connected to said second bit line; a plurality of first redundant memory cells connected to said first redundant bit line; a plurality of second redundant memory cells connected to said second redundant bit line; a first amplifier circuit connected to said first bit line and said second bit line to amplify a difference of potential between said first bit line and said second bit line; and a first redundant amplifier circuit connected to said first redundant bit line and said second redundant bit line to amplify a difference of potential between said first redundant bit line and said second redundant bit line, wherein said first bit line is to be replaced with said first redundant bit line but said second bit line is not to be replaced with said second redundant bit line.