Patent ID: 6900492

Claim:
A semiconductor integrated circuit device comprising: a memory cell composed of a memory cell selecting n channel MISFET and a capacitor which are formed in a memory cell forming area of a semiconductor substrate; and an n channel MISFET and a p channel MISFET which are formed in peripheral circuit forming areas, wherein each of said n channel MISFET and said p channel MISFET in said peripheral circuit forming are includes: a source and drain formed in said semiconductor substrate; a gate electrode formed between said source and drain on the semiconductor substrate via a gate insulating film; and a silicon oxide cap insulating film formed on said gate electrode and a silicon oxide side wall insulating film formed on a side wall of said gate electrode, said memory cell selecting n channel MISFET includes: a source and drain formed in said semiconductor substrate; a gate electrode formed between said source and drain on the semiconductor substrate via a gate insulating film; a silicon oxide insulating film formed on said gate electrode; a silicon oxide side wall film formed on a sidewall of the gate electrode of said memory cell selecting n channel MISFET, wherein, a thickness of said side wall film is substantially the same at an upper portion and a lower portion along said sidewall of the gate electrode, a p type impurity is contained in the gate electrode of said memory cell selecting n channel MISFET and in the gate electrode of said p channel MISFET, and an n type impurity is contained in the gate electrode of said n channel MISFET; and a contact plug electrode through which said source or said drain of said memory cell selecting n channel MISFET is connected to the capacitor or a bit line, said contact plug electrode being formed between said side wall films of adjacent gate electrodes of the memory cell selecting n channel MISFETs wherein a height of said contact plug electrode is substantially the same as a height of said cap insulating film on said gate electrode and a width of said contact plug electrode is substantially the same at an upper portion and a lower portion along the sidewall film of the gate electrode; wherein said side wall film formed on each gate electrode of said n channel MISFET and said p channel MISFET that are formed in said peripheral circuit forming area is thicker than said side wall film formed on the gate electrode of said memory cell selecting n channel MISFET.