Patent ID: 8775902

Claim:
A memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device, the memory controller comprising: an external interface configured to transmit and receive the write data/the read data to and from the host device; a first ECC generating unit configured to generate parity data and a first ECC code for the write data; an access unit configured to control writing and reading of the write data/the read data or parity data to and from the memory; a first ECC correcting unit configured to correct an error of read data, by using data and parity data read from the memory via the access unit; and a control unit configured to control the external interface, the first ECC generating unit, the access unit, and the first ECC correcting unit, wherein the control unit reads data in a first read unit upon reading data from the memory, and when an error occurs in the data read in the first read unit, reads the data in a second read unit having a reading size smaller than that of the first read unit by switching the first read unit to the second read unit, and controls the first ECC correcting unit to correct an error of the data that is read in the second read unit, by using the first ECC code.