Patent ID: 7141475

Claim:
A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semiconductor substrate with a first insulating film over a memory cell forming region, with a second insulating film formed over a peripheral circuit region, with first conductor patterns formed over said first insulating film and said second insulating film, and with grooves formed into said semiconductor substrate, in self-alignment with said first conductor patterns, at said memory cell forming region and at said peripheral circuit region, such that said grooves serve as an element isolation region in said memory cell forming region and in said peripheral circuit region, wherein said second insulating film has a thickness greater than that of said first insulating film; (b) filling third insulating films in said grooves at said memory cell forming region and at said peripheral circuit region by polishing an insulating film deposited over said memory cell forming region and said peripheral circuit region; (c) after said step (b), forming second conductor patterns over said first conductor patterns; (d) forming a fourth insulating film over said first conductor patterns; (e) forming a conductive film over said fourth insulating film; and (f) patterning said conductive film, said second conductor patterns and said first conductor patterns in said memory cell forming region and in said peripheral circuit region, wherein, in said step (f), said conductive film in said memory cell forming region is patterned to form a control gate electrode of a memory cell, wherein, in said step (f), said first conductor patterns and said second conductor patterns in said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and wherein, in said step (f), said conductive film, said first conductor patterns and said second conductor patterns in said peripheral circuit region are patterned to form a gate electrode of a MISFET of said peripheral circuit region.