Patent ID: 7286389

Claim:
A static random access memory (SRAM) cell comprising: (a) a latch including first and second p-channel enhancement-type metal-oxide semiconductor field-effect transistors (PMOSFETs) for storing data, a gate of the first PMOSFET is connected to a drain of the second PMOSFET at a first memory node, and a gate of the second PMOSFET is connected to a drain of the first PMOSFET at a second memory node; (b) third and fourth PMOSFETs forming a pull-down circuit, a gate and a source of the third PMOSFET are connected to the first memory node, and a gate and a source of the fourth PMOSFET are connected to the second memory node; and (c) access circuitry for accessing data at the first and second memory nodes for read or write operations.