Patent ID: 8812787

Claim:
A router configured to manage routing of a packet transferred between a plurality of cores and at least one of cache memories to which the cores can access, the router comprising: an analyzer configured to determine whether the packet is a read-packet or a write-packet; a packet memory configured to store at least part of the write-packet issued by one of the cores; and a controller configured to, when the analyzer determines that the packet is the write-packet and the packet memory is not full, store cache data of the write-packet and a cache address in the packet memory, the cache address indicating an address in which the cache data is stored, when the analyzer determines that the packet is the write-packet and the packet memory is full, output the packet to a subsequent router or one of the cache memories without storing the packet in the packet memory, and when the analyzer determines that the packet is the read-packet and the cache address corresponding to the read-request is stored in the packet memory, output the cache data stored in the packet memory to the core issuing a read-request as a response data corresponding to the read packet.