Patent ID: 8108847

Claim:
A system for handling register spills, the system including a CPU having parallel registers including a first register set and a second register set, the system comprising: (a) an analyzer module configured to analyze spill code generated by a register allocator to determine that register spill instructions can be paired, wherein paired register spill instructions relate to corresponding register locations in each of the first register set and the second register set and that no instructions between said register spill instructions modify any of said register spill instructions; (b) a rewriter module configured to, based on the determining, modify said register spill instructions as a parallel register spill instruction; and (c) a storage module configured to configure storage of associated register spills in memory in such a manner that said register spills can be loaded back in parallel into corresponding registers of said first and second register sets based on said modified parallel register spill instruction, wherein the configuration of storage includes allocation of space on a memory stack such that the register spills are double word aligned.