Patent ID: 7391634

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a first unit memory device on the semiconductor substrate, wherein the first unit memory device is configured to receive first through N th data bits and/or to provide first through N th data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal; and a second unit memory device on the semiconductor substrate wherein the second unit memory device is configured to receive (N+1) th through 2N th data bits and/or to provide (N+1) th through 2N th data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal; wherein the first unit memory device and the second unit memory device are separated by an uncut scribe line and wherein other scribe lines adjacent the first unit memory device and the second unit memory device are cut.