Patent ID: 7552251

Claim:
A single-chip flash device comprising: an interface to a host bus that connects to a host; a bus transceiver for detecting and processing commands sent over the host bus; a buffer for storing data sent over the host bus; an internal bus coupled to the buffer; a random-access memory (RAM) for storing instructions for execution; the RAM coupled to the internal bus, a central processing unit (CPU) coupled to the internal bus, the CPU accessing and executing instructions in the RAM; a flash-memory controller, coupled to the internal bus, for generating flash-control signals and for buffering commands, addresses, and data to a flash bus; a direct-memory access (DMA) engine, coupled to the internal bus, for transferring data over the internal bus; flash mass storage blocks, coupled to the flash-memory controller, for storing non-volatile data for the host, the data in the flash mass storage blocks being block-addressable and controlled by the flash-control signals; a flash programming engine, activated by a reset, for initially programming the DMA engine to transfer an initial program of instructions from the flash mass storage blocks to the RAM before the CPU begins execution of instructions after the reset; and wherein the flash-memory controller is coupled to the flash mass storage blocks that are block-addressable; the flash bus having parallel data lines for transferring data from the flash-memory controller to the flash mass storage blocks, the flash bus also carrying a command to the flash mass storage blocks over the parallel data lines and also carrying a flash address over the parallel data lines; wherein a block of data in the flash mass storage blocks is addressable by the flash-memory controller sending the command and a physical address over the parallel data lines, the command and the physical address being used to transfer the block of data over the parallel data lines as a plurality of data words transferred in a plurality of bus cycles, wherein the flash mass storage blocks comprise a plurality of multi-level-logic (MLC) memory cells.