Patent ID: 8782585

Claim:
A method of C4 ball placement layout, comprising: using a computer to perform the following: (a) converting a circuit into a weighted graph G(V,E), wherein V represents nodes of said circuit and E represents conductors between said nodes, wherein a weight of an i th node (w(v i )) is a current source at the node (I i ), and wherein the weight of the i th edge (w(e i )) is a conductance of the conductor between the nodes connected by that edge; (b) finding a minimum number of balls (Nm) that satisfies a predetermined current draw constraint (I thres ); (c) partitioning said circuit into sub-circuits; (d) determining whether a supply current in each of said sub-circuits is sent only to transistors within said each sub-circuit and if an IR drop in each said sub-circuit is minimized; (e) if in step (d) the determination is no, increasing Nm by K, wherein K is an integer, and looping back through steps (a) through (d) with said increased Nm; (f) if in step (d) the determination is yes, performing a binary search between Nm and Nm−K balls to obtain an optimal solution, wherein that optimal solution is the lowest number of balls that passes step (d); and (g) locating a C4 balls each sub-circuit partitioning from step (c) using the lowest number of balls so as to satisfy the current draw constraint (I thres ).