Patent ID: 8482076

Claim:
An integrated circuit structure comprising: a substrate; at least one first-type field effect transistor partially within said substrate; at least one second-type field effect transistor partially within said substrate and positioned adjacent said first-type field effect transistor; and a shallow trench isolation region positioned between said first-type field effect transistor and said second-type field effect transistor, said first-type field effect transistor comprising first-type source and drain regions within said substrate, a first-type channel region within said substrate between said first-type source and drain regions, a first-type gate conductor adjacent said first-type channel region, a first-type gate insulator between said first-type channel region and said first-type gate conductor, and a first-type silicide layer on said first-type source and drain regions, said second-type field effect transistor comprising second-type source and drain regions within said substrate, a second-type channel region within said substrate between said second-type source and drain regions, a second-type gate conductor adjacent said second-type channel region, and a second-type gate insulator between said second-type channel region and said second-type gate conductor, and a second-type silicide layer on said second-type source and drain regions, said first-type silicide layer being different than said second-type silicide layer, and said first-type silicide layer being positioned at a first distance from a center of said first-type channel region, said second-type silicide layer being positioned at a second distance from a center of said second-type channel region, and said first distance being different than said second distance.