Patent ID: 7721177

Claim:
A device for determining a position of a bit error in a bit sequence using a check matrix, wherein the check matrix comprises a predefined number of rows and a predefined number of columns, wherein the check matrix includes a plurality of square submatrices having a submatrix row number and a submatrix column number, wherein the submatrix row number corresponds to the predefined number of rows or the submatrix column number corresponds to the predefined number of columns of the check matrix, wherein each submatrix includes submatrix entries arranged circulantly with respect to a first submatrix row or a first submatrix column, wherein a bit and a bit group are arranged in each submatrix row or in each submatrix column, and wherein, in a first submatrix, the bit and the bit group are arranged in a first predetermined relationship to each other and, in a second submatrix, the bit and the bit group are arranged in a second predetermined relationship to each other, wherein the first predetermined relationship differs from the second predetermined relationship, and wherein the device for determining comprises: a unit configured to receive a bit sequence; a unit configured to identify a syndrome using the check matrix and the received bit sequence; and a unit configured to establish a position of a bit error in the received bit sequence, wherein the unit configured to establish is further configured to identify a syndrome bit and a syndrome bit group in the syndrome, and wherein the unit configured to establish is further configured to determine the position of the bit error of the received bit sequence using information on a position of the syndrome bit or the syndrome bit group in the syndrome, information on a relationship between the syndrome bit and the syndrome bit group and the submatrix row number or the submatrix column number.