Patent ID: 7356797

Claim:
A logic design method, comprising the steps of: (a) providing a logic block comprising an input stage and an output stage; and (b) placing each input gate of the input stage in a vicinity of the input gate's respective inputs, wherein step (a) comprises the step of transforming a gate G into the logic block, wherein inputs of the input stage are the inputs of the gate G, and wherein outputs of the output stage are the outputs of the gate G wherein the step of transforming the gate G into the logic block comprises the steps of: dividing the inputs of the gate G into M input groups, each group of the M input groups having at least two proximate inputs; dividing the outputs of the gate G into N output groups, each group of the N output groups having at least two proximate outputs; and replacing the gate G by (i) M gates in the input stage corresponding to the M input groups and (ii) N gates in the output stage corresponding to the N output groups, wherein M and N are positive integers, wherein each gate of the M gates is configured to receive input signals from all the inputs of its corresponding input group, wherein each gate of the N gates is configured to receive input signals from all the M gates, and wherein each gate of the N gates is configured to send output signals to all outputs of its corresponding output group.