Patent ID: 7408912

Claim:
A modulation circuit for time division multiple access comprising: a first encoder and a second encoder for differentially encoding transmission data signals in odd-numbered and even-numbered time-slots respectively; a first filter and a second filter for generating narrow-banded signals in accordance with at least one shift clock signal and at least one reset signal on the basis of the signals differentially encoded by said first and second encoders; a signal combiner for combining signals output from said first and second filters to generate transmission signals; and at least one timing generator for generating said at least one shift clock signal in accordance with at least one transmission-window signal giving timing of transmission data in odd-numbered and even-numbered time-slots, and for generating said at least one reset signal at an end of the each transmission data, wherein each of said first filter and said second filter comprises: a shift register for transforming said signal differentially encoded by applying a synchronized shift operation with said at least one shift clock signal for said signal differentially encoded into a parallel-formed signal, said register being configured to be cleared in its content in response to said at least one reset signal; and a ROM for storing data of narrow-banded signal waveforms corresponding to said signal differentially encoded in its memory areas, and reading data of the narrow-banded signal waveforms in a memory area specified by said parallel-formed signal from said shift register as an address signal.