Patent ID: 7623399

Claim:
A semiconductor memory, comprising: a memory unit including a regular cell array having a plurality of memory cells and a decoder for decoding an input address and selecting a memory cell corresponding to the input address in the regular cell array, in which an access operation is performed to the selected memory cell; a defective address storage section which stores a defective address corresponding to a defective bit in the regular cell array; and a replacement address storage section which stores a replacement address corresponding to a replacement bit in the regular cell array, wherein when a supply address supplied to the memory unit matches the defective address, the replacement address, in place of the supply address, is supplied to the memory unit as the input address, and the decoder decodes the replacement address so as to select a memory cell corresponding to the replacement address in the regular cell array, and when an image data is stored in the regular cell array, the replacement address to replace the defective address is set to an address corresponding to a memory cell which stores said image data of an edge area of an image.