Patent ID: 7596038

Claim:
A design structure embodied in a machine readable medium, the design structure comprising: a memory array including a plurality of first DRAM cells connected to a first word line circuit and a bit line circuit or bit line bar circuit; a plurality of second DRAM cells connected to the bit line circuit or bit line bar circuit and a second word line circuit; a plurality of reference DRAM cells connected to a reference word line circuit and the bit line circuit or bit line bar circuit; a first power supply for supplying a bit line voltage to the DRAM cells, the bit line circuit, and the first word line; a second power supply for supplying a reference voltage to the reference DRAM cells and reference bit line circuit wherein the reference voltage is different from the bit line voltage; control logic communicating with the DRAM memory device and an integrated circuit (IC) for providing normal DRAM cycle operation and initiating a body refresh cycle, and the control logic generates a word line signal, a bit line control signal, a bit line bar control signal, and a reference word line signal; a sense amplifier circuit which amplifies the signal voltage at the bit line circuit and the bit line bar circuit; and the control logic adapted to generate the body refresh cycle periodically, wherein the voltage supplied to the first word line is deactivated while the bit line and bit line bar voltages continue, and the control logic is adapted to re-activate the first word line voltage.