Patent ID: 8762911

Claim:
A computer-implemented method of designing a layout of a multi-finger CMOS inverter for maximal drain current, comprising: disposing, by a computer, a multi-finger N-type field effect transistor (NFET), having n f fingers, proximate to a multi-finger P-type field effect transistor (PFET), also having n f fingers, in said layout, said n f fingers contacting multiple parallel gates of a common gate for each multi-finger NFET and multi-finger PFET, said multiple parallel gates separating multiple drains and multiple sources that are aligned for each multi-finger NFET and multi-finger PFET; disposing, by said computer, a first metallization wire, along a length of said multi-finger NFET in said layout, said first metallization wire connecting said multiple drains and contacting every drain of said multi-finger NFET; disposing, by said computer, a second metallization wire, along a length of said multi-finger PFET in said layout, said second metallization wire connecting said multiple drains and contacting every drain of said multi-finger PFET; and connecting, by said computer, a third metallization wire to said first and said second metallization wires at common output nodes for drain currents from said multi-finger NFET and said multi-finger PFET, respectively, in said layout, based on calculations of a minimal wiring resistance to said output nodes using: a total number of drains of said multi-finger NFET and said multi-finger PFET, and one of: a disposition of one outer drain along an outer width of each multi-finger NFET and multi-finger PFET, and of at least one inner drain between two sources of each multi-finger NFET and multi-finger PFET, and a disposition of no outer drains along outer widths of each multi-finger NFET and multi-finger PFET, and of at least two inner drains, each being disposed between two sources, of said each multi-finger NFET and multi-finger PFET.