Patent ID: 7016245

Claim:
A memory system comprising: an actual memory array comprising a plurality of cells, each of said plurality of cells storing a corresponding one of a plurality of data values; a decoder to retrieve a signal from said actual memory array according to an address; an actual sense amplifier to sense said signal as a bit; a latch latching said bit at a time point specified by a latch enable signal; a dummy memory array offering a load when accessed; and a dummy sense amplifier said dummy sense amplifier sensing another signal which is received when said dummy memory array is accessed, said dummy sense amplifier generating said latch enable signal according to a time of completion of sensing said another signal, wherein a positive correlation exists between an amount of said load and a delay in generating said another signal, wherein said dummy memory array is designed to offer said load such that said latch enable signal is generated in an appropriate time window to cause said bit to be latched, wherein each of said dummy sense amplifier and said actual sense amplifier comprises: a first transistor having a drain terminal connected to a supply voltage and a gate terminal connected to a sense enable signal; a second transistor and a third transistor, wherein said third transistor is implemented as a mirror of said second transistor, a gate terminal of said second transistor being connected to a gate terminal of said third transistor at a first node, a drain terminal of both of said second transistor and said third transistor being connected to a source terminal of said first transistor, a source terminal of said second transistor also being connected to said first node; a resistive load connected to a source terminal of said third transistor at a second node; an inverter having an input path connected to said second node; and a fourth transistor having a drain terminal connected to said first node and a gate terminal connected to said sense enable signal.