Patent ID: 8630106

Claim:
A semiconductor memory device, comprising: a memory cell unit including a plurality of memory cells connected in series, the plurality of memory cells including charge accumulation layers and control gates; a plurality of word lines connected to the control gates of memory cells, the plurality of word lines including a first word line, a second word line, a third word line, a fourth word line, and a fifth word line, the fifth word line being adjacent to the first word line; a driver circuit configured to supply a voltage to the memory cells; and a plurality of transistors each including two impurity diffused layers, one of the two impurity diffused layers being connected to the driver circuit, the other of the two impurity diffused layers being connected to one of the word lines, the transistors including a first transistor and a second transistor, the first transistor being connected to the first word line, the second transistor being connected to the fifth word line, wherein when data is written into a memory cell connected to the first word line, a first voltage is applied to the first word line, a second voltage is applied to the second word line and the third word line, and a third voltage is applied to the fourth word line, the first voltage being larger than both the second voltage and the third voltage, the third voltage being larger than the second voltage, both the second word line and the third word line being located above gate electrodes of the first transistor and the second transistor without passing over the two impurity diffused layers of the first transistor and the two impurity diffused layers of the second transistor.