Patent ID: 7576579

Claim:
A DLL circuit comprising: a dividing circuit unit that frequency-divides a first clock signal to generate at least first and second frequency-divided signals having different phases; a first delay adjusting circuit that adjusts an amount of delay of the first frequency-divided signal based on a first feedback signal; a second delay adjusting circuit that adjusts an amount of delay of the second frequency-divided signal based on a second feedback signal; a synthesizing circuit that synthesizes at least outputs of the first and second delay adjusting circuits to generate a second clock signal, and supplies the second clock signal to a real path in a clock tree unit; a first clock driver that receives the output of the first delay adjusting circuit and supplies the output to a replica path in the clock tree unit; and a second clock driver that receives the output of the second delay adjusting circuit, wherein the first clock driver and the second clock driver have substantially the same circuit configuration.