Patent ID: 7924963

Claim:
A circuit, comprising: a circuit for generating a plurality of output data signals on an output data line at times controlled by a plurality of clock signals, wherein: a first output data signal of the plurality of output data signals is generated in accordance with a first logical combination of at least two clock signals in the plurality of clock signals; a second output data signal of the plurality of output data signals is generated in accordance with a second logical combination of at least two clock signals in the plurality of clock signals, wherein the first logical combination is distinct from the second logical combination; a first phase adjustment circuit coupled to at least one of the plurality of clock signals, wherein the first phase adjustment circuit adjusts a trailing edge time of the first output data signal; and a second phase adjustment circuit coupled to at least one of the plurality of clock signals, wherein the second phase adjustment circuit adjusts a leading edge time of the first output data signal and adjusts a trailing edge time of the second output data signal.