Patent ID: 7219253

Claim:
A process for limiting a performance of a processor to a selected submodel capability comprising the steps of: A) sample a Real Time Clock (RTC) to obtain a first time value T 1 ; B) reset an Instruction Count (Icnt) Counter; C) determine if a current instruction is a “RTC-access-type”; 1) if the current instruction is not a “RTC-access-type”, proceed to step D); and 2) if the current instruction is a “RTC-access-type”: a) inhibit service of the current instruction; and b) go to step F) D) process instructions while incrementing the Icnt Counter to reflect the processing of each instruction; E) compare the count in the Icnt Counter to a predetermined count Instruction Count Maximum (IcntMax); and 1) if the count in said Icnt Counter is less than IcntMax, then return to step C); and 2) if the count in said Icnt Counter is at least IcntMax, then proceed to step F); F) sample the RTC to obtain a second time T 2 ; G) subtract T 1 from T 2 to obtain a time difference DT; H) multiply DT by ((1−1/DF)−1) to obtain a Degradation Delay DD period, DF being a constant having a value which is a desired submodel performance with respect to full performance; I) delay; J) during step I): 1) sample the RTC to obtain a test third time T 3 ; 2) it test third time T 3 minus T 2 is less than DD, then continue step I); and K) determine if the current instruction is a “RTC-access-type”; L) if the current instruction is not a “RTC-access-type”, go to step N); M) service the “RTC-access-type” instruction; N) set T 1 equal to T 3 as used in step I) 2); and O) go to step B).