Patent ID: 7629828

Claim:
An apparatus comprising: an output clock signal controller that generates toggle signals in response to rising or falling edges of a selected next input clock signal, wherein the toggle signals include a toggle high signal triggered by a rising edge of the selected next input clock signal, wherein the toggle signals further include a toggle low signal triggered by a falling edge of the selected next input clock signal, and wherein the output clock signal controller comprises: a delay logic that receives a signal identifying the selected next input clock signal and that delays the signal, wherein the delay logic comprises: a first D flip-flop that receives the selected next input clock signal and a signal identifying selected next input clock signal and; a second D flip-flop that receives the selected next input clock signal and a signal identifying the selected next input clock signal; and an OR gate that performs a logical OR on outputs from the first and second D flip-flops; and a toggle signal generator that delays generating any toggle signal in response to receipt of the signal identifying the selected next clock input signal until elapse of at least one half period of the selected next input clock signal; and an output clock signal generator that generates an output clock signal in response to the toggle signals, wherein the output clock signal generator changes the output clock signal to a digital high level in response to receipt of the toggle high signal and wherein the output clock signal generator changes the output clock signal to a digital low level in response to receipt of the toggle low signal.