Patent ID: 8242826

Claim:
A master-slave retention flip-flop comprising: a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal; a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal; and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal, wherein the master or slave latch with the embedded retention latch comprises a primary storage ring operable during normal operation mode and a secondary storage ring operable during the power down mode, wherein the primary and second storage rings share at least one device, wherein the primary storage ring comprises first and second inverters, a first pass gate coupled between an output of the first inverter and an input of the second inverter, and a second pass gate coupled between an output of the second inverter and an input of the first inverter, wherein the first pass gate is controlled by the power down control signal and the second pass gate is controlled by the input clock signal, and wherein the secondary storage ring includes the second inverter, a third inverter having an input coupled to the output of the second inverter and a third pass gate coupled between an output of the third inverter and the input of the second inverter, wherein the third pass gate is controlled by the power down control signal.