Patent ID: 7093223

Claim:
A method for performing noise analysis in an integrated circuit model, the integrated circuit model having a plurality of nets, the method comprising: performing a preliminary routing of the plurality of nets by dividing the integrated circuit model into a plurality of cells and, for each cell of the plurality of cells, determining a set of nets from the plurality of nets which traverse the cell; determining aggressor strength or coupling capacitance and grounded capacitance for each of the plurality of nets based on the preliminary routing, wherein determining the coupling and grounded capacitance comprises: selecting a net from the plurality of nets; and for each cell traversed by the net, determining a probability of occurrence of a predetermined configuration of nets within the cell and using the probability to determine the coupling and grounded capacitance; performing, before detailed routing, noise analysis using the aggressor strength or the coupling and grounded capacitance; and performing detail routing of the integrated circuit model after performing noise analysis.