Patent ID: 6884676

Claim:
A method of forming a memory cell of a memory cell array comprised of a plurality of said memory cells arranged in rows and columns, said method comprising: forming a deep trench structure within a semiconductor substrate, said deep trench structure including at least one conducting region; forming a patterned bit line structure atop of, and electrically isolated from, said conducting region of said deep trench structure and atop of, but contacting at least part of, regions of said semiconductor substrate; etching exposed portions of said semiconductor substrate to form at least one isolation trench adjoining said deep trench structure using said patterned bit line structure as an etch mask; filling said isolation trench with a dielectric material; forming, within said dielectric material of said isolation trench, a contact region to said conducting region of said deep trench structure that is electrically isolated from said bit line structure; and forming a word line structure that connects to said contact region and that is at least in part atop of, but electrically isolated from, said bit line structure.