Patent ID: 8289273

Claim:
A scan line driving circuit which selects a plurality of scan lines arranged in rows in predetermined turn and changes a logical level of the selected scan lines into an active level and which is used in an electro-optical device including a plurality of scan lines arranged in rows and grouped into a plurality of blocks, each block having p (p is an integer of two or more) rows, a plurality of data lines arranged in columns, and pixels which are disposed corresponding to intersections of the plurality of scan lines arranged in rows and the plurality of data lines arranged in columns and which become gray-scale images in response to data signals supplied to the data lines when a logical level of the scan lines becomes an active level, the scan line driving circuit comprising: unit circuits prepared corresponding to the plurality of scan lines arranged in rows; wherein p unit circuits of the entire unit circuits, which correspond to p rows of scan lines belonging to one block, are commonly supplied with a logical signal which becomes an active level in a period in which each of the scan lines corresponding to the p rows is selected, and wherein the unit circuit includes a first transistor having a source electrode to which the logical signal is supplied and a drain electrode connected to the corresponding scan line, a second transistor having a gate electrode to which a clock signal is supplied, a source electrode to which a select signal is supplied, and a drain electrode connected to a gate electrode of the first transistor, wherein the select signal is outputted at times synchronized with the clock signal, and a short-circuiting circuit which causes a parasitic capacitor of the first transistor to be short-circuited.