Patent ID: 6884682

Claim:
A method of manufacturing a flash memory device, the method comprising the steps of; (a) providing a semiconductor substrate having a high voltage transistor area in which a first gate oxide film and a first poly-silicon layer are formed between first element isolation films, and a low voltage transistor/cell area in which a second gate oxide film and the first poly-silicon layer are formed between second element isolation films; (b) forming a planarizing film on the surfaces of the first poly-silicon layer and the first and second element isolation films; (c) performing a first etching process to remove upper portions of the planarizing film and the element isolation films in the low voltage transistor/cell area to a certain thickness; (d) performing a second etching process to remove upper portions of the planarizing film and the element isolation films in the high voltage transistor area and the low voltage transistor/cell area; and, (e) forming a second poly-silicon layer on the surfaces of the first poly-silicon layer and the element isolation films.