Patent ID: 7546330

Claim:
A system for multiplying complex numbers, comprising: a first register configured to store first data having a first operand, the first operand representing a first complex number; a second register configured to store second data having a second operand, the second operand representing a second complex number; a processor configured to perform a multiplication of the first operand by the second operand to produce a first result, the first result representing a third complex number; and a third register configured to store third data having the first result, the first result having at least a product of the multiplication, wherein each of a least significant bits portion of the first operand, a most significant bits portion of the first operand, a least significant bits portion of the second operand, and a most significant bits portion of the second operand is represented as an H-bit two's complement signed number, and each of a least significant bits portion of the first result and a most significant bits portion of the first result is represented as an A-bit two's complement signed number, wherein A is greater than (2H+1), and wherein a value of a (2H+1) least significant bit indicates a sign of the A-bit two's complement signed number, and a value of [A−(2H+1)] most significant bits of the A-bit two's complement signed number is equal to the value of the (2H+1) least significant bit of the A-bit two's complement signed number.