Patent ID: 7928791

Claim:
A clocked digital device having dynamically adjustable operating characteristics comprising: (a) a first input pin for receiving an externally supplied clock signal; (b) a first digital clock management (“DCM”) circuit having a clock input, a phase adjust input and an output, wherein: (i) the clock input of the first DCM circuit is coupled to receive a clock signal corresponding to the externally supplied clock signal; (ii) the output of the first DCM circuit provides an internal clock signal having a frequency corresponding to the frequency of the clock signal received at the clock input of the first DCM circuit; and (iii) the amount of delay between receipt of an active edge of the clock signal received at the clock input of the first DCM circuit and the appearance of an active edge of the internal clock signal provided at the output of the first DCM circuit corresponds to a signal applied to the first DCM circuit's phase adjust input; (c) a first clocked register having an input, an output, and a clock input, wherein: (i) the first clocked register input is coupled to receive a clock signal corresponding to the externally supplied clock signal; and (ii) the first clocked register clock input is coupled to receive the internal clock signal provided at the output of the first DCM circuit; and (iii) the first clocked register samples the value of the clock signal at its input in response to receipt of the active edge at its clock input; (d) a first delay adjustment circuit having an input and an output, wherein: (i) the input of the first delay adjustment circuit is coupled to receive a signal from the output of the first clocked register; (ii) the output of the first delay adjustment circuit is coupled to the first DCM circuit's phase adjust input; and (iii) the first clocked register outputs a digital signal that can vary between a logic high level and a logic low level, and the first delay adjustment circuit provides an output signal that varies in response to the digital signal to adjust an amount of delay between the receipt of an active edge at the input of the first DCM circuit and the appearance of an active edge of the internal clock signal provided at the output of the first DCM circuit.