Patent ID: 7054216

Claim:
A programmable metal-oxide-semiconductor (MOS) memory circuit comprising: a latch module having a first output and a second output based on a voltage difference between a first input and a second input; a first N-type transistor having a gate region tied with a drain region and connectable to a first control voltage level, and a source region connected to a second control voltage level; a second N-type transistor having a gate region tied with a drain region and connectable to the first control voltage level, and a source region connected to the second control voltage level; and a connection module for connecting the drain region of the first N-type transistor to the first input, and the drain region of the second N-type transistor to the second input, wherein the first and second control voltage levels are imposed to program either the first or second N-type transistor by causing a voltage difference between the drain region and the source region (Vds) and voltage difference between the gate region and the source region (Vgs) to be bigger than an operating voltage to induce a hot carrier effect, and wherein the first and second outputs of the latch produce voltage results representing whether the first or second N-type transistor has been programmed when the connection module is enabled.