Patent ID: 7456105

Claim:
A process for the formation of semiconductor wafers, wherein said wafers comprise a plurality of layers, each said layer comprising a metallic material and a dielectric material, said process comprising the steps of: providing a chemical-mechanical planarization wafer polishing station; providing to said station a plurality of semiconductor wafers having exposed a said layer to be polished; applying an RL-based slurry to said exposed layer; said RL-based slurry adapted to polish said layers preponderantly by interaction of particles with said layers, said slurry consisting of: particulate matter having a concentration in said RL-based slurry in the range of from 50 PPM to 450 PPM and a particle diameter size centered at substantially 100 nm, with a diameter variation in the range of plus/minus 80 nm, and with substantially no particle diameter exceeding 180 nm; and terminating the application of said RL-based slurry when a desired degree of removal of said metallic material and said dielectric material has been reached for a one of said layers.