Patent ID: 7639036

Claim:
A semiconductor integrated circuit having a plurality of pads to be connected by bonding wires to respective external terminals so that logic levels of signals applied to said external terminals are given to said plurality of pads, and a test circuit for inspecting states of connections between said plurality of pads and said respective external terminals, wherein said test circuit comprises: for each of said plurality of pads, a control terminal provided to receive a control signal of a logic level equal to the logic level of a signal applied to a corresponding one of said external terminals; an inverter which inverts the logic level on said control terminal, an inverted output terminal of said inverter being connected to the pad via a connection line; and an exclusive-NOR gate which is separately connected to said connection line and said control terminal, and outputs an exclusive NOR of the logic level on said connection line and the logic level on said control terminal, and wherein an output of the exclusive NOR indicates a test result of the connection state between the pad and the corresponding external terminal.