Patent ID: 8069279

Claim:
A direct memory access (DMA) controller comprising: a transmit circuit configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory, where there is a data structure for each DMA channel that is in use, wherein a given DMA descriptor that describes a DMA transfer includes data that defines a source and a target of the DMA transfer, and wherein the transmit circuit is configured to process the given DMA descriptor to determine the source and the target, and wherein the transmit circuit is configured to generate read operations to read data from the source to be transmitted to the target responsive to processing the given DMA descriptor that describes the DMA transfer; a data flow control circuit coupled to the transmit circuit and configured to control the transmit circuit's processing of DMA descriptors for each DMA channel; and one or more registers coupled to the data flow control circuit, wherein the one or more registers are configured to store a set of flags, and wherein a first control descriptor is coded to specify a first flag in the set of flags, and wherein, responsive to the first control descriptor in a first data structure corresponding to a first DMA channel, the data flow control circuit is configured to delay processing of subsequent DMA descriptors in the first data structure until the first flag is changed to a first value, and wherein the transmit circuit is configured to process DMA descriptors in other data structures corresponding to other DMA channels while the data flow control circuit is delaying processing of the subsequent DMA descriptors in the first DMA channel.