Patent ID: 8798553

Claim:
A signal processing circuit, comprising: a first multiplying unit that multiplies a first signal including a frequency component of a first frequency by a second signal including a frequency component of a second frequency and thereby outputting a third signal; a second multiplying unit that multiplies said first signal by a fourth signal of said second frequency whose phase is lagging equals to a first phase difference relative to said second signal and thereby outputting a fifth signal; a third multiplying unit that multiplies said first signal by a sixth signal of said second frequency whose phase is lagging equals to a second phase difference relative to said second signal and thereby outputting a seventh signal; a first adding unit that adds said third signal with a first weight, said fifth signal with a second weight and said seventh signal with a third weight respectively; and a signal generating unit that controls said first phase difference and said second phase difference based on a control signal and thereby outputting said second signal, said fourth signal and said sixth signal, wherein said signal generating unit: inputs a reference signal whose frequency is an integral multiplication of said second frequency; generates said second signal by an integral division of said reference signal to a specified fraction of said multiplied frequency; sets said first phase difference and said second phase difference by delaying said first signal with an amount of integral multiplication of time when setting that half the cycle of said reference signal as a unit time based on said control signal; and generates said fourth signal and said sixth signal.