Patent ID: 7067927

Claim:
An integrated circuit package comprising: a first die having an active surface; a first set of connectors that electrically connect I/O pads exposed on the active surface of the first die to a carrier; and a second die stacked on the first die, the second die having a pedestal and an active region, the pedestal being integrally formed with the active region and including sidewalls, the pedestal having a smaller footprint than a footprint of the second die so that portions of a bottom surface of the second die are recessed relative to a bottom surface of the pedestal, and wherein the pedestal is mounted on the active surface of the first die, the die including an electrically insulating layer that covers at least portions of the sidewalls of the pedestal, wherein the insulating layer only coats and covers portions of the second die and does not encapsulate any portions of the first set of connectors, whereby the insulating layer helps prevent connectors in the first set of connectors from electrically communicating with the pedestal.