Patent ID: 7479801

Claim:
A method of implementing power gating with a virtual rail voltage clamp of a semiconductor integrated circuit having a virtual ground rail comprising the steps of: adding N f quantity of NFETs to the integrated circuit between the virtual ground rail and a ground rail for power gating and virtual rail voltage clamping, where N f is a number of footer devices required to produce a certain amount of leakage reduction in the integrated circuit; adding N max-VC latches in a scan chain with the output of each latch coupled to a respective one of N max-VC NFETS of the N f NFETS, so that the N max-VC NFETs act as virtual rail voltage clamps, where N max-VC is the maximum number of footer devices needed for said virtual ground rail to be substantially at a voltage value V clamp , where V clamp is a desired steady state voltage at the virtual ground rail; and coupling the remaining (N f −N max-VC ) NFETs to a control signal, S sleep 13 n for causing the (N f −N max-VC ) NFETs to act as footer devices for implementing power gating of the integrated circuit.