Patent ID: 7642597

Claim:
A power semiconductor device comprising: a semiconductor substrate having a plurality of trenches formed in an upper surface thereof; a buried insulating film formed on an inner surface of the trenches; a buried field plate electrode buried in the trenches; a control electrode insulated from the semiconductor substrate by a gate insulating film; a first main electrode provided on a lower side of the semiconductor substrate; and a second main electrode provided on an upper side of the semiconductor substrate, the semiconductor substrate including: a first semiconductor layer of a first conductivity type with its lower surface connected to the first main electrode; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged parallel to the upper surface of the semiconductor substrate; a fourth semiconductor layer of the second conductivity type formed above the second semiconductor layer and the third semiconductor layer and connected to the second main electrode; and a fifth semiconductor layer of the first conductivity type selectively formed in an upper surface of the fourth semiconductor layer and connected to the second main electrode, the buried insulating film being thicker than the gate insulating film, at least one of the second semiconductor layer and the third semiconductor layer having a portion with its sheet dopant concentration varying along depth direction of the semiconductor substrate, the sheet dopant concentration in the third semiconductor layer being higher than the sheet dopant concentration in the second semiconductor layer in an upper part of the portion with varying sheet dopant concentration, and the sheet dopant concentration in the third semiconductor layer being lower than the sheet dopant concentration in the second semiconductor layer in a lower part of the portion.