Patent ID: 7755587

Claim:
An integrated circuit device comprising: first to Nth circuit blocks (N is an integer of three or more), the first to Nth circuit blocks being lined along a first direction when a direction from a first side that is a short side of the integrated circuit device toward a third side opposite to the first side is the first direction and a direction from a second side that is a long side of the integrated circuit device toward a fourth side opposite to the second side is a second direction; a first interface region provided along the fourth side at one side of the first to Nth circuit blocks in the second direction; and a second interface region provided along the second side at another side of the first to Nth circuit blocks in a fourth direction opposite to the second direction, one of the circuit blocks at both ends of the first to Nth circuit blocks being a scan driver block that drives a scan line, the circuit block(s) of the first to Nth circuit blocks excluding the scan driver block including at least one data driver block that drives a data line, the circuit block(s) of the first to Nth circuit blocks excluding the scan driver block and the at least one data driver block including at least one memory block that stores image data, one of the at least one memory block being lined adjacent to one of the at least one data driver block along the first direction, the circuit blocks excluding the scan driver block, the at least one data driver block and the at least one memory block including: a logic circuit block that sets grayscale characteristic adjustment data, a grayscale voltage generation circuit block that generates a grayscale voltage based on the set adjustment data, and a power supply circuit block that generates a power supply voltage, the one of the at least one data driver block receiving the grayscale voltage from the grayscale voltage generation circuit block and the one of the at least one data driver block driving the data line, and in the at least one memory block, a shield line being provided in an upper layer of a bitline and a grayscale voltage output line to which the grayscale voltage from the grayscale voltage generation circuit block is output being provided in an upper layer of the shield line.