Patent ID: 7159153

Claim:
A semiconductor integrated circuit, comprising: a plurality of detectors, wherein each detector detects a corresponding operating condition of the integrated circuit and generates a detection signal that indicates an abnormal condition; a reset signal generator for generating a reset signal; a nonvolatile memory; a plurality of latch circuits for respectively latching the detection signals from the plurality of detectors, output signals from said plurality of latch circuits being fed to the nonvolatile memory; a logic circuit connected to said output signals from said plurality of latch circuits and producing a program signal upon a latch output signal indicating an abnormal condition, said program signal fed to said nonvolatile memory to cause said latch circuit outputs to be stored therein and said program signal being fed to said reset signal generator for generating a reset signal in response thereto; and a central processor unit (CPU) which is restarted in response to the reset signal after the detection signals have been stored in the nonvolatile memory in response to the program signal from the logic circuit, wherein upon restarting the CPU, a read signal is generated by the CPU to automatically read out stored detection signals from the nonvolatile memory to be referred to by a user to indicate there was an abnormal condition detected.