Patent ID: 8400188

Claim:
An edge detector circuit for detecting an edge of an input signal and producing an output level-sensitive signal that is synchronous to a clock signal having an active edge corresponding to a transition from a first-signal level to a second-signal level, the circuit comprising: a first flip-flop that is configured and arranged with the input signal as a clock input to produce an internal level-sensitive signal and to be reset by the output level-sensitive signal; logic configured and arranged to pass the internal level-sensitive signal in response to the clock signal being at the second-signal level and to block the internal level-sensitive signal in response to the clock signal being at the first-signal level; and a second flip-flop that is configured and arranged to set by the passed internal level-sensitive signal and to produce the output level-sensitive signal and that is cleared in response to the output level-sensitive signal, a reset input and the clock signal.