Patent ID: 7830740

Claim:
A semiconductor memory device comprising: a control circuit which controls access to a memory cell according to an input command; a transfer mode setting circuit which holds a transfer mode, by which a transfer manner of data stored or to be stored in the memory cell is determined, according to a command from the control circuit; an address pin which inputs an address in a first transfer mode and inputs or outputs data in a second transfer mode; a data pin which inputs or outputs data in both the first and second transfer modes; a switching circuit which switches a connection destination of the address pin between an address buffer and an input/output buffer according to the transfer mode; and a data controller which processes data such that said data is to be transferred through the data pin or through both the address pin and the data pin according to the transfer mode, wherein the data controller outputs first data such that said first data is to be transferred through the data pin in the first transfer mode, and outputs second data such that said second data is to be transferred through both the data and address pins in the second transfer mode.