Patent ID: 8475976

Claim:
A method of fabricating an integrated circuit using photolithography, comprising: selectively exposing a photoresist layer to pattern a coarse line region of a layer on a wafer using a trim mask; wherein the trim mask comprises: a) a transparent region comprising a substantially transparent material operable to substantially transmit light; b) an attenuated phase-shift region comprising an attenuated phase-shift material operable to attenuate and phase-shift light, the phase-shifted attenuated light operating to substantially pattern the coarse line region; and c) an opaque region comprising an opaque material operable to substantially block light; the opaque region operating to keep light from exposing the fine line region of the photoresist layer, the body of the opaque region being fully opaque, the opaque region further having tabs that project beyond a base of the opaque region to join at a boundary of the attenuated phase-shift region; selectively exposing a same or different photoresist layer to pattern a fine line region of the layer on the wafer using an alternating phase-shift mask, wherein the alternating phase-shift mask comprises a) alternating phase-shift regions operable to transmit phase-shifted light, the transmitted alternating phase-shifted light operable to pattern substantially only the fine line region; and b) one or more alternating phase-shift regions that transmit light to pattern and overlap with at least a portion of the region left unexposed by the opaque region of said trim mask but does not substantially transmit light to pattern and overlap with the coarse line region patterned by said attenuated phase-shift region of said trim mask, wherein the trim exposure on the wafer occurs before the alternating phase exposure.