Patent ID: 7751225

Claim:
A read-only memory (ROM), comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, and wherein each memory cell transistor includes diffusion regions, each diffusion region having a contact, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node, and wherein at least one of the memory cell transistors is as programmed memory cell transistor, each programmed memory cell transistor being shorted through a metal connection between the programmed memory cell transistor's contacts, the metal connection being formed in a semiconductor manufacturing metal layer overlaying the contacts such that it is conducting regardless of whether the corresponding word line is asserted, and wherein the contacts of non-programmed memory cell transistors do not couple to overlaying metal patches.