Patent ID: 8085088

Claim:
An apparatus including quadrature signal demodulator circuitry, comprising: a plurality of quadrature signal demodulator circuits each of which includes signal routing circuitry responsive to a respective one of a plurality of received signals by providing corresponding first and second input signals, and signal mixing circuitry coupled to said signal routing circuitry and responsive to said first and second input signals, one or more clock signals and respective one or more phase control signals by providing respective first and second output signals which are related to said first and second input signals, have substantially mutually quadrature signal phases, and are respective ones of first and second pluralities of output signals, respectively, wherein first and second ones of said first plurality of output signals have a first mutual signal phase difference, first and second ones of said second plurality of output signals corresponding to said first and second ones of said first plurality of output signals have a second mutual signal phase difference, and said first and second mutual signal phase differences are substantially equal; signal scaling circuitry coupled to said plurality of quadrature signal demodulator circuits and responsive to one or more magnitude control signals by magnitude scaling said first and second pluralities of output signals to provide first and second pluralities of scaled output signals, wherein said first and second pluralities of output signals include first and second pluralities of current signals with said first and second mutual signal phase differences, respectively, and said signal scaling circuitry includes first current mirror circuitry responsive to said one or more magnitude control signals by scaling said first and second pluralities of current signals; and output signal combining circuitry coupled to said plurality of quadrature signal demodulator circuits and responsive to said first and second pluralities of scaled output signals by providing first and second resultant signals, respectively.