Patent ID: 7833872

Claim:
A method of forming a microelectronic device, comprising: (a) providing (i) a plurality of trenches extending vertically from an exposed major surface of a substrate through a plurality of layers of the substrate, (ii) a dielectric layer lining walls of the trenches and (iii) a plurality of exposed columnar elements overlying the dielectric layer within the trenches, the plurality of columnar elements extending vertically from within the trenches to different heights above the major surface; (b) recessing the columnar elements to below the major surface of the substrate by etching the columnar elements selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches without mechanically polishing the major surface and so that a surface of the dielectric layer is exposed above the uniform depth, wherein each columnar element has a top surface at a first depth below the major surface at a location within the trench away from a wall of the trench, the top surface being at a second depth below the major surface at the wall, the second depth being greater than the first depth, the first depth being determined by the etch time multiplied by the etch rate R; (c) removing exposed portions of the dielectric layer within the trenches above the uniform depth; and (d) forming microelectronic devices coupled to the columnar elements, wherein, after the columnar elements have been etched to the first depth, the exposed surfaces of each columnar element defines a “W” shape as viewed in cross-section, the method further comprising further recessing the columnar elements within the trenches to a second uniform depth from the major surface by a reactive ion etch (RIE) process.