Patent ID: 7781804

Claim:
A non-volatile memory disposed on a substrate, the non-volatile memory comprising: a plurality of active regions defined by a plurality of isolation structures adapted to be disposed in the substrate, the active regions and the isolation structures being extended in a first direction; a first memory array disposed on the substrate, the first memory array comprising: a plurality of memory cell columns, each of the memory cell columns comprising: a plurality of memory cells connected in series with one another and adapted to be disposed on the substrate at the active regions; a source/drain region, adapted to be disposed in the substrate outside the memory cells; a plurality of select transistors disposed between the source/drain region and the memory cells for connecting the memory cells to the source/drain region in series; a plurality of control gate lines extending across the memory cell columns and extended in a second direction orthogonal to the first direction, the control gate lines respectively connecting the memory cells in the second direction in series; a plurality of first select gate lines extending across the active regions and respectively connecting the select transistors in the second direction in series; and a plurality of first contacts arranged along the second direction and disposed on the substrate at a side of the first memory array, each of the first contacts extending across the isolation structure and connecting the source/drain regions in every two of the adjacent active regions.