Patent ID: 7307889

Claim:
A semiconductor memory comprising: a select gate extending in a first direction; and a plurality of floating gates coupled with said select gate, said plurality of floating gates including: a first floating gate; and a second floating gate arranged adjacent to said first floating gate and deviating from said first floating gate in a second direction perpendicular to said first direction, wherein adjacent ends of the first and second floating gates overlap each other in the first direction; a substrate having a major surface on which said select gate and said plurality of floating gates are formed respectively through gate insulating films; a plurality of memory cells sharing said select gate and each having one of said plurality of floating gates; and a potential supply circuit for supplying a potential to said plurality of memory cells, wherein, for access to a selected memory cell selected from said plurality of memory cells, said potential supply circuit supplies a potential lower than a potential applied to said substrate to said selected memory cell.