Patent ID: 7343509

Claim:
A car-mounted electronic control device comprising: a main control circuit unit including a microprocessor to become a main CPU powered by a car-mounted battery through a switching clement responding to an action of a power source switch and a main power source circuit, for driving various electric loads in response to action states of various input sensors and contents of a first program memory; and a timer circuit unit powered at all times by the car-mounted battery through an auxiliary power source circuit, for measuring a lapse of time from a time measurement starting command of the main CPU, so as to generate a starting output signal, when a predetermined target measurement time is reached, and to feed the main power source circuit with the car-mounted battery thereby to start and activate said main CPU, wherein said timer circuit unit includes: a microprocessor to become a sub CPU acting synergistically with a second program memory and in synchronism with a high-speed clock signal generated by a first oscillator; timing counters for counting a number of low-speed clock signals generated by a second oscillator, to measure the lapse of time after said main power source circuit is interrupted; first estimation means for estimating a pulse period of said high-speed clock signal by receiving a correcting reference clock having a period divided or multiplied from a reference oscillator output signal for driving said main CPU, when said main CPU is active, and by counting generated pulses of said high-speed clock signal with a first counter of the timing counters for a predetermined measurement period of said correcting reference clock; second estimation means for estimating a period of said low-speed clock signals by counting generated pulses of said high-speed clock signal with a second counter of the timing counters for a frequency-divided pulse period of said low-speed clock signals when said main CPU is inactive; and periodic correction means for cumulatively correcting current values of said timing counters and the lapse of time obtained by the timing counters in accordance with the period of the low-speed clock signals sequentially updated and estimated by executing the period estimation of the low-speed clock signals periodically with said second estimation means.