Patent ID: 6887779

Claim:
A method of forming a semiconductor chip carrier, comprising the steps of: providing a substrate, having a plated through hole therein; forming a first power plane on a first external surface of the substrate and in direct mechanical contact with the first external surface; forming a second power plane on a second external surface of the substrate and in direct mechanical contact with the second external surface; depositing a first redistribution layer on the first power plane and in direct mechanical contact with a surface of the first power plane, wherein the first power plane is disposed between the first redistribution layer and the first external surface; depositing a second redistribution layer on the second power plane and in direct mechanical contact with the second power plane, wherein a surface of the second power plane is disposed between the second redistribution layer and the second external surface; forming a first plated blind via the first redistribution layer, wherein the first via is in electrical contact with the plated through hole, and wherein the first via is in direct mechanical and electrical contact with first power plane; and forming a second plated blind via in the second redistribution layer, wherein the second via is in electrical contact with the plated through hole, and wherein the second via is in direct mechanical and electrical contact with the second power plane.