Patent ID: 7697317

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including memory cells each having a variable resistance element storing information by a change of an electric resistance, the memory cells being in row and column directions, a plurality of word lines extending in the row direction, each word line connecting first ends of the memory cells in a same row, and a plurality of bit lines extending in the column direction, each bit line connecting second ends of the memory cells in a same column; a memory cell selecting circuit structured to select a word line and a bit line from the plurality of word lines and the plurality of bit lines such that a memory cell whose first and second ends connected to the selected word line and the selected bit line is selected; and a programming voltage applying circuit structured to apply a row programming voltage to the selected word line, a column programming voltage to the selected bit line, a row programming blocking voltage to unselected word lines, and a column programming blocking voltage to unselected bit lines so as to apply a programming voltage sufficient for programming the selected memory cell only, and wherein the programming voltage applying circuit is structured to apply a programming compensating voltage to each of unselected memory cells, the programming compensating voltage having an opposite polarity to that of a programming disturbance which is a voltage applied to each of the unselected memory cells while the programming voltage is applied to the selected memory cell.