Patent ID: 7939400

Claim:
A method of fabricating a semiconductor device comprising: performing well formation and isolation processing in a semiconductor body; forming a gate oxide layer on the semiconductor body; forming gate electrodes on the gate oxide layer; forming offset spacers on lateral edges of the gate electrodes; forming extension regions in the semiconductor body in NMOS and PMOS regions; forming sidewall spacers adjacent the offset spacers; implanting n-type dopant(s) to form source/drain regions in the NMOS region; implanting p-type dopant(s) to form source/drain regions in the PMOS region; forming a strain inducing liner over the device; masking the PMOS region with a lithographic coating and exposing the NMOS region; and exposing one of an ultraviolet beam and an electron beam to strain inducing liner formed over the NMOS region with a dose and duration that obtains a stress type and magnitude within the NMOS region.