Patent ID: 8522174

Claim:
A method, comprising: a) selecting a number of bit cells per bit line to be included in a semiconductor memory; b) selecting a size of a device to be disposed between and coupled to a first memory bit cell and to a first power supply line, the size based on the number of bit cells; c) simulating a first design of the semiconductor memory that includes the device disposed between and coupled to the first memory bit cell and to the first power supply line, the first memory bit cell disposed in a column including the selected number of bit cells; d) determining if at least one simulated operational value of the semiconductor memory is above a threshold value; e) adjusting at least one of the size of the device or a type of the device if the at least one simulated operational value is below the threshold value; f) repeating steps d) and e) until the at least one simulated operational value is at or above the threshold value; and g) storing a final model of the semiconductor memory in a non-transient computer readable storage medium when the at least one simulated operational value is at or above the threshold value, wherein the semiconductor memory includes a transistor coupled in parallel with the device, the transistor including a drain coupled to a node disposed between the first memory bit cell and the device, a source coupled to the first power supply line, and a gate configured to receive a control signal to selectively turn the transistor on and off based on a voltage on a word line to which the first memory bit cell is coupled.