Patent ID: 7768837

Claim:
A flash memory device comprising: a memory cell array comprising a plurality of memory cells arranged in a matrix comprising a plurality of word lines and a plurality of bit lines; a column decoder configured to select at least one bit line of the plurality of bit lines in response to a column address; a write driver circuit configured to drive the at least one selected bit line to a bit line voltage in accordance with input data in response to an enable signal; and a bit line detecting/driving circuit configured to drive the at least one selected bit line to the bit line voltage, while the write driver circuit continues to drive the at least one selected bit line, when the bit line detecting/driving circuit detects variations of the at least one selected bit line from the bit line voltage, in response to a decoding result of the column address during a programming operation, wherein the bit line detecting/driving circuit comprises: a switch circuit for connecting the at least one bit line of the plurality of bit lines in response to the decoding result of the column address; and a plurality of bit line detector/driver units, at least one bit line detector/driver unit being connected to the at least one selected bit line through the switch circuit, the bit line detecting/driving unit detecting voltages from the at least one bit line and driving the at least one selected bit line to the bit line voltage in accordance with the detected voltages, and wherein each of the bit line detecting/driving units comprises: a PMOS transistor connected between the bit line voltage and an output terminal; an NMOS transistor connected between the output terminal and a ground voltage, the NMOS transistor being controlled by a control signal from a controller; and a detector configured to detect voltage variation of the output terminal and to control the PMOS transistor in response to the voltage variation detection.