Patent ID: 7391649

Claim:
A non-volatile memory device, said memory device comprising a non-volatile memory cell array and a page buffer, wherein said page buffer comprises: a sense node selectively connected to a bit line of the memory cell array; a main latch circuit including first and second main latch nodes, wherein the first main latch node is selectively connected to the sense node; a latch input node selectively connected to the first and second main latch nodes; a cache latch circuit including first and second cache latch nodes; a switching circuit which selectively connects the second cache latch node to the latch input node; and a shared sense circuit connected between to the latch input node and a reference potential, wherein the shared sense circuit selectively connects the latch input node to the reference potential in response to a voltage of the sense node and a voltage of the first cache latch node; wherein the shared sense circuit comprises: first and second transistors connected in parallel between the main latch input node and an intermediate node; and third and fourth transistors connected in parallel between the intermediate node and the reference potential.