Patent ID: 7387942

Claim:
A method for fabricating an integrated circuit comprising a conductive transistor gate formed on a gate dielectric formed on an active area of a semiconductor substrate, the active area having a first conductivity type, the method comprising: (i) forming a dielectric layer on the semiconductor substrate, wherein the gate dielectric comprises at least a portion of the dielectric layer; (ii) forming a first layer on the dielectric layer, wherein the conductive transistor gate comprises at least a portion of the first layer; (iii) forming a mask over the first layer to define one or more substrate isolation regions to be formed adjacent to the active area; (iv) patterning the first layer, and dielectric layer, and the semiconductor substrate to form a pattern defined by the mask, the patterning operation comprising: (iv-a) removing a portion of the first layer; (iv-b) removing a portion of the dielectric layer to form a dielectric layer sidewall, wherein the dielectric layer sidewall is part of the gate dielectric; and (iv-c) removing a portion of the semiconductor substrate to form a trench at a location of each of the isolation regions, the trench having a sidewall at a boundary of the active area; (v) introducing a dopant of the first conductivity type into the trench sidewall by ion implantation of dopant ions with the gate dielectric sidewall facing a stream of the dopant ions; (vi) forming a dielectric over the trench sidewall, the dielectric being part of the isolation regions; and (vii) heating the gate dielectric in one or more thermal step to anneal a damage to the gate dielectric caused by the ion implantation, wherein at least one of the thermal steps is performed with the gate dielectric not being exposed.