Patent ID: 8477777

Claim:
A bridge apparatus comprising: a second line card, a second memory, a first memory, and a first line card, wherein the first line card includes: an ingress processor, wherein the ingress processor includes: an addition process circuit that adds a first flag to a frame to be transmitted to the second line card, the first flag indicating whether or not a destination address stored in the first memory matches a destination address of the frame to be transmitted; and a first transmitter that transmits, to the second line card, the frame to which the first flag is added, wherein the second line card includes an egress processor, wherein the egress processor includes: a first receiver that receives the frame to which the first flag is added; a determination circuit that determines whether or not a destination address stored in the second memory matches the destination address of the received frame when the first flag indicates that the address stored in the first memory does not match the destination address of the frame, and a second transmitter that transmits, when the determination circuit determines that the address stored in the second memory matches the destination address of the frame, address information associated with at least the destination address of the frame to the first line card.