Patent ID: 7675344

Claim:
A level shifter comprising: a first transistor of a first conductivity-type connected between a first source potential and a first internal node and ON/OFF-controlled by a signal of a second control node; a second transistor of the first conductivity-type connected between the first source potential and a second internal node and ON/OFF-controlled by a signal of a first control node; a third transistor of the first conductivity-type connected between the first internal node and a first output node and ON/OFF-controller by an input signal corresponding to a second source potential: a first transistor of a second conductivity-type connected between the first output node and a around potential and ONIOFF-controlled by the input signal; a fourth transistor of the first conductivity-type connected between the second internal node and a second output node and ON/OFF-controlled by an inverse input signal obtained by inverting the input signal; a second transistor of the second conductivity-type connected between the second output node and the around potential and ON/OFF-controlled by the inverse input signal; a fifth transistor of the first conductivity-type connected between the first internal node and the first control node and ON/OFF-controlled by the input signal; a third transistor of the second conductivity-type connected between the first control node and the ground potential and ON/OFF-controlled by the input signal; a sixth transistor of the first conductivity-type connected between the second internal node and the second control node and ON/OFF-controlled by the inverse input signal; a fourth transistor of the second conductivity-type connected between the second control node and the around potential and ON/OFF-controlled by the inverse input signal; and a holding circuit which holds the signals of the first control node and the second control node and which, even when the input signal and the inverse input signal are both brought to the around potential, maintains and outputs the signals of the first control node and the second control node to the first control node and the second control node, wherein the holding circuit includes a seventh transistor of the first conductivity-type connected between the first internal node and the first control node and ON/OFF-controlled by the signal of the second control node, a fifth transistor of the second conductivity-type connected between the first control node and the ground potential and ON/OFF-controlled by the signal of the second control node, an eighth transistor of the first conductivity-type connected between the second internal node and the second control node and ON/OFF-controlled by the signal of the first control node, and a sixth transistor of the second conductivity-type connected between the second control node and the ground potential and ON/OFF-controlled by the signal of the first control node.