Patent ID: 7242712

Claim:
A receiver with a decision feedback equalizer (DFE), the receiver comprising: a subtracting circuit configured to receive a received signal and a feedback signal as inputs, where the received signal has embedded therein symbols at a symbol rate with symbol intervals, where the subtracting circuit is configured to subtract the feedback signal from the received signal to generate an equalized signal for reduction of inter-symbol interference (ISI); a slicer in communication with the subtracting circuit to receive the equalized signal as an input, where the slicer is configured to determine a logical state of the equalized signal and to provide an output signal; and a feedback filter circuit in communication with the slicer and the subtracting circuit, where the feedback filter circuit is configured to receive the output signal from the slicer as an input and to provide the feedback signal to the subtracting circuit, where the feedback signal has canceling terms for cancellation of one or more post-cursor ISI terms by the subtracting circuit, where the feedback filter circuit includes a first delay tap for a feedback filter, where the first delay tap is configured to delay the feedback signal such that transitions of the feedback signal are substantially time aligned with symbol interval transitions of the received signal for the subtracting circuit.