Patent ID: 8368436

Claim:
A programmable frequency synthesizer, comprising a phase-locked loop that receives a reference clock and generates a first in-phase clock and a first quadrature-phase clock, the first in-phase clock having a first phase relationship to the reference clock and the first quadrature-phase clock having a second phase relationship to the reference clock, the first in-phase and quadrature-phase clocks having a first frequency that is related to the reference clock; a post-scaler, coupled to receive the first in-phase clock and the first quadrature-phase clock, the post-scaler generates a second in-phase clock and a second quadrature-phase clock, the second in-phase and quadrature-phase clocks having a second frequency that is a fraction of the first frequency; and an application processor, coupled to the phase-locked loop and the digital frequency divider, the application processor defines the fraction value of the second frequency in relation to the first frequency and defines a multiplication value that relates the first frequency to the reference clock.