Patent ID: 7193550

Claim:
A driving circuit of a flat display device, said driving circuit generating driving signals by subjecting image data to digital-to-analog conversion processing, and driving signal lines of a display unit formed by arranging pixels in a form of a matrix by said driving signals, said driving circuit comprising: an original reference voltage generating circuit for generating a plurality of original reference voltages; a reference voltage generating circuit formed by connecting a plurality of voltage divider circuits in series with each other, said voltage divider circuits each being formed by connecting a plurality of resistances in series with each other, said original reference voltages being inputted to both ends of said voltage divider circuits and between said voltage divider circuits, respectively, said reference voltage generating circuit outputting a plurality of reference voltages as voltages divided by said plurality of voltage divider circuits; a plurality of selecting circuits for outputting said driving signals by receiving said plurality of reference voltages and selecting and outputting the reference voltages according to said image data for corresponding signal lines; and an input circuit for inputting original reference voltage setting data for specifying settings of said original reference voltages; wherein said original reference voltage generating circuit includes a plurality of digital-to-analog converter circuits for generating said original reference voltages by generating a plurality of candidate voltages for said original reference voltages by voltage divider circuits for generating the original reference voltages and selecting and outputting the candidate voltages according to said original reference voltage setting data; and a first digital-to-analog converter circuit of said plurality of digital-to-analog converter circuits divides a reference voltage generating voltage by a voltage divider circuit for generating said original reference voltage, and outputs a first original reference voltage of said plurality of original reference voltages; a second digital-to-analog converter circuit of said plurality of digital-to-analog converter circuits divides said reference voltage generating voltage by a voltage divider circuit for generating said original reference voltage, and outputs a second original reference voltage of said plurality of original reference voltages; and voltage divider circuits for generating said original reference voltages of the other digital-to-analog converter circuits of said plurality of digital-to-analog converter circuits are connected in series with each other, and said first original reference voltage and said second original reference voltage are input to both ends, respectively, of the other digital-to-analog converter circuits.