Patent ID: 8179162

Claim:
A method for a circuit having a phase lock assistant circuit that receives an input signal and a feedback clock signal having a first phase, a second phase, a third phase, a fourth phase, and fifth phase, and a sixth phase corresponding to a first phase clock, a second phase clock, a third phase clock, a fourth phase clock, a fifth phase clock, and a sixth phase clock, respectively, the method comprising: using the first phase clock, the third phase clock and the fifth phase clock to sample the input signal and generate a first relationship between the feedback clock signal and the input signal and a second relationship between the feedback clock signal and the input signal; using the second phase clock, the fourth phase clock, and the sixth phase clock to sample the input signal and generate a third relationship between the feedback clock signal and the input signal and a fourth relationship between the feedback clock signal and the input signal; and generating a fifth relationship between the feedback clock signal and the input signal based on the first relationship, the second relationship, the third relationship and the fourth relationship; wherein the first phase, the second phase, the third phase, the fourth phase, the fifth phase and the sixth phase are in an order of phase degree.