Patent ID: 7225390

Claim:
A semiconductor memory device comprising: an SDRAM array made up of a plurality of memory cells and having an information bit area wherein information bits are written in and/or read from and a parity bit area wherein parity bits are written in and/or read from, and a redundant circuit to replace error bits contained in at least one of said information bits and said parity bits; and an error correcting code (ECC) circuit to perform error correcting processing, using a Hamming Code on data including said information bits and said parity bits being written in and/or read from said information bit area and said parity bit area, respectively, in said SDRAM array, wherein use of redundant correcting processing to correct said error bits using a redundant circuit in said SDRAM array is combined with said error correcting processing using said Hamming Code in said error correcting code (ECC) circuit, and wherein said error correcting code circuit comprises a plurality of divided error correcting code circuits provided independently of each other for each independent data mask block and controlled by independent data mask signals as external signals.