Patent ID: 7135726

Claim:
A semiconductor memory comprising: a first conductivity type semiconductor substrate; one or more memory cells comprising an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein an active region of at least one of said memory cells is electrically insulated from the semiconductor substrate by: a second conductivity type impurity diffusion layer formed in the semiconductor substrate or in the island-like semiconductor layer, and means for forming a depletion layer formed at a junction between the second conductivity type impurity diffusion layer and the semiconductor substrate or the island-like semiconductor layer; and wherein a lower gate electrode of a first selection transistor, the control gate of the memory cell, and an upper gate electrode of a second selection transistor are arranged in an upward order in a direction vertical to the semiconductor substrate, so that the first and second selection transistors are located on opposite vertical sides of the memory cell in a vertical direction.