Patent ID: 7583772

Claim:
A system for shifting bits multiple times per clock cycle, comprising: a controller that receives a phase input signal and a feedback signal, the feedback signal feeding back from an output of the controller, and that generates a first signal and a second signal; a multiple data bit per clock shifting device, that receives the first signal from the controller, that includes a first storage device with a first data signal and a second storage device with a second data signal, and that shifts data bits in the first and second data signals multiple times per clock cycle to produce a shifted signal based on the first signal from the controller; a selector controller that receives the second signal from the controller and generates a selector control signal during a first half of the clock cycle; a selector that receives the selector control signal from the selector controller during a second half of the clock cycle and the shifted signal from the shifting device and that generates a selected signal; and a clock that establishes the clock cycle through transmitting a clock signal to the controller, the first and second storage devices in the shifting device, and the selector controller.