Patent ID: 7635898

Claim:
A semiconductor device comprising: a first gate electrode including a dielectric layer formed on a substrate, a first conducting layer formed on the dielectric layer, and a first insulating layer formed on the conducting layer, the first gate electrode functioning as a flash memory; first spacers on sidewalls of the first gate electrode, one first spacer being on a first sidewall of the first gate electrode, a second first spacer being on a second sidewall of the first gate electrode opposite to the first sidewall of the first gate electrode; a second gate electrode comprising a gate oxide layer and a second conducting layer on the substrate, the second gate electrode functioning as a normal gate electrode; first source/drain regions comprising a shallow junction region formed adjacent to one side of the first gate electrode and a shallow junction region formed adjacent one side of the second gate electrode on the substrate; second spacers on a sidewall of one of the first spacers and on sidewalls of the second gate electrode, the second spacer on the sidewall of the one of the first spacers being directly on the sidewall of the second first spacer; and second source/drain electrode regions comprising a deep junction region on the first spacer source/drain regions on the substrate.