Patent ID: 6859857

Claim:
A memory interface circuit comprising: a memory bus arbitrating circuit having a refresh request signal and other processing request signals input thereto, and which selects from among the request signals simultaneously-inputted thereto a request signal with a highest priority; a memory controlling circuit for controlling a main memory on the basis of said request signal selected by said memory bus arbitrating circuit; a counting circuit for counting a timing for refreshing said main memory; and a monitoring circuit for outputting said refresh request signal based on a result of comparing a count value of said counting circuit against a comparison value stored in an overwrite-capable memory, said monitoring circuit comprises a first overwrite-capable memory for storing a first comparison value inputted from outside, a second overwrite-capable memory for storing a second comparison value inputted from outside, a first comparing circuit for outputting a first signal when the count value of said counting circuit either matches or exceeds said first comparison value, a second comparing circuit for outputting a second signal when the count value of said counting circuit either matches or exceeds said second comparison value, and a gate circuit for outputting said refresh request signal from an output timing of said first signal to an output timing of said second signal.