Patent ID: 6882557

Claim:
A semiconductor memory device comprises: a memory array having plurality of word-lines arranged in a predetermined direction and in parallel to each other, a plurality of bit lines arranged orthogonally to a plurality of the word-lines and in parallel to each other, and a plurality of memory cells arranged at predetermined intersection points of a plurality of the word-lines and a plurality of the bit-lines, the number of the predetermined intersection points being equal to half of all the intersection points; a plurality of switches connected to one-side end of the bit-lines provided at an odd-numbered position of a plurality of the bit-lines and connected to the other-side end of the bit-line provided at an even-numbered position, respectively; and a plurality of unit circuits each having two terminal connected to a pair of odd-numbered or even-numbered bit lines of a plurality of the bit lines, the unit circuits being arranged in a column in a predetermined direction in the vicinities to the both ends of a plurality of the bit lies, respectively, the predetermined intersection points being determined in such a manner that when one of a plurality of the word lines is selected, the memory cells of a plurality of the memory cells connected to the selected word line can be electrically connected, one by one, to the terminals of a plurality of the unit circuit.