Patent ID: 8766839

Claim:
A method comprising: generating an intermediate set of bits; converting the intermediate set of bits to a first intermediate analog value from a first set of representative capacitors from a plurality of capacitors in a successive approximation register (SAR) analog-to-digital converter (ADC); converting the intermediate set of bits to a second intermediate analog value from a second set of representative capacitors from the plurality of capacitors in the SAR ADC; and generating a plurality of digital code bits from the first intermediate analog value and the second intermediate analog value, wherein more than one capacitor in the second set of representative capacitors and the first set of representative capacitors are not same, wherein the plurality of capacitor further comprises plurality of capacitor banks of equal capacitance value with each capacitor bank being placed at different location on a semiconductor die and the first set of representative capacitors and the second set of representative capacitor are formed by coupling a set of banks to a reference voltage.