Patent ID: 8230137

Claim:
A network processor, comprising: a descriptor storage circuit which stores a plurality of descriptors stored on an external memory, the external memory including a plurality of storage areas storing a plurality of received data, a descriptor specifying a location of a storage area; a DMA (Direct Memory Access) control circuit configured to transfer the plurality of descriptors from the external memory to the descriptor storage circuit through a DMA transfer, to transfer the plurality of received data to the plurality of storage areas in the external memory through the DMA transfer on a basis of the plurality of descriptors stored in the descriptor storage circuit upon receipt of the received data, and to generate a reception status indicating a condition of the received data each time the received data is transferred to the external memory through the DMA transfer; a reception status storage circuit which stores the reception status; and a reception status combination control circuit which combines the reception statuses which are stored in the reception status storage circuit, wherein the DMA control circuit transfers the reception statuses having been combined to the external memory through the DMA transfer, and wherein the DMA transfer of the reception statuses having been combined is independent of the DMA transfer of the plurality of descriptors.