Patent ID: 8751731

Claim:
A memory controller, comprising: control circuitry coupled to one or more memory devices having multiple groups of planes associated therewith, each group including at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes, and wherein the control circuitry is configured to: receive a first unassigned logical block address (LBA) associated with a write operation; determine a particular free super block within a selected one of the multiple groups to receive data associated with the write operation; receive a different unassigned LBA associated with a subsequent write operation; determine a particular free super block within a selected one of the multiple groups to receive data associated with the subsequent write operation; track, for each of the multiple groups, a number of free super blocks available in each group; determine which of the super blocks have stale data; determine when the super blocks having stale data are to be erased; and for each of the multiple groups, prevent the super blocks having stale data from being erased until the group does not include any free super blocks.