Patent ID: 7943286

Claim:
A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of: (a) providing a coating of three layers of resists, with a polymethylmethacrylate (PMMA) layer with high molecular weight on the bottom, a polydimethylglutarimide (PMGI) layer in the middle, and a PMMA layer with low molecular weight on the top; (b) in a first exposure and developing cycle, exposing and developing the layers with a dose that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure and developing cycle, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.