Patent ID: 8599528

Claim:
A surge protection circuit to reduce capacitance inherent of standard diode packaging and to improve voltage clamping reaction speeds under high surge conditions, the surge protection circuit comprising: a housing; a cavity defined by the housing; a signal path for propagating DC currents and RF signals, the signal path including: a first port for receiving the DC currents and the RF signals; a foil positioned within the cavity and having a first plate connected to the first port, a second plate and a third plate connecting the first plate to the second plate; and a second port for transmitting the DC currents and the RF signals, the second port being directly connected to the second plate of the foil, wherein the signal path is not directly connected to any capacitor or any diode, for minimizing attenuation of the DC currents and the RF signals; and a surge path including: the first port; a coil positioned within the cavity, the coil having a first end connected to the first port, and a second end; and a diode cell having a top layer, a center diode junction, and a bottom layer, the top layer directly connected to the second end of the coil and the bottom layer directly connected to a ground, wherein the diode cell has no wire leads.