Patent ID: 8549329

Claim:
A method, comprising: monitoring power information associated with a computing system; and based on the monitored power information, determining whether (i) a first hardware memory throttling signal will be asserted at a first memory throttle pin on a processor socket, (ii) a second hardware memory throttling signal will be asserted at a second memory throttle pin on the processor socket, and (iii) a processor throttling signal will be asserted at a processor power control pin on the processor socket; wherein at least one of the two memory throttling signals is asserted only when both: (i) a memory voltage regulator current trip point is triggered and (ii) a system power utilization exceeds a pre-set limit and wherein the computing system includes a plurality of processors, and said determining comprising: based on the monitored power information, determining whether a hardware processor power control signal will be individually asserted for each of the plurality of processors.