Patent ID: 7821817

Claim:
A semiconductor storage device, including a plurality of memory cells, each of the plurality of memory cells comprising: a first inverter and a second inverter; a first node and a second node, the first node being connected to an output of the first inverter and an input of the second inverter, the second node being connected to an output of the second inverter and an input of the first inverter; a first transistor and a second transistor, the first transistor having one of a source and a drain connected to the first node, the second transistor having one of a source and a drain connected to the second node; a first bit line and a second bit line, the first bit line being connected to the other of the source and the drain of the first transistor, the second bit line being connected to the other of the source and the drain of the second transistor; and a word line connected to a gate of the first transistor and a gate of the second transistor, the semiconductor storage device comprising: a third transistor having one of a source and a drain connected to the first bit line; and a fixed voltage keeping circuit keeping a potential of the other of the source and the drain of the third transistor to a fixed potential in a memory cell non-selected state.