Patent ID: 7173850

Claim:
A nonvolatile semiconductor memory comprising: a memory cell array which includes a memory cell unit having one memory cell and one select transistor connected in series, wherein the one memory cell has a stacked gate structure having a floating gate and a control gate; a bit line connected to the one memory cell; and a source line connected to the one select transistor, wherein the memory cell unit comprises a 2-Tr block having the one memory cell and the one select transistor, and wherein data of the one memory cell is changed by using a F-N tunneling phenomenon, wherein when the memory cell unit is selected in a read operation, the control gate of the one memory cell is set to have 0 V and the one select transistor is in an ON-state, and when the memory cell unit is unselected in a read operation, the control gate of the one memory cell is set to have 0 V and the one select transistor is in an OFF-state.