Patent ID: 7213184

Claim:
A method of testing a plurality of modules in an integrated circuit, said plurality of modules comprising a first module and a second module, wherein data is transferred on a path connecting said a first module to said second module wherein said first module and said second module are to be operated together during said testing such that said second module operates using a second one of a plurality of characteristics of a first control signal when said first module is operated using a first one of said plurality of characteristics of said first control signal comprising a clock signal, said method comprising: providing said second module with a capability of being tested in each of said plurality of characteristics of said first control signal; providing a bit indicating whether a derived control signal is to be generated as a positive clock signal or a negative clock signal; generating said derived control signal by performing XOR logical operation of said bit and said clock signal, wherein said derived control signal having a desired characteristic the same as said second one of a plurality of characteristics providing said derived control signal as a control signal to said second module; and testing said second module with said desired characteristic of said first control signal by using said derived control signal.