Patent ID: 8269273

Claim:
A trench MOSFET with an etching buffer layer in a trench gate, comprising: a substrate which has a first surface and a second surface opposite to each other and comprises at least a drain region, a gate region, and a source region which are constructed as a plurality of semiconductor cells with MOSFET effect; a plurality of gate trenches, each of which is extended downward from the first surface and comprises a gate oxide layer covered on a inner surface thereof and a gate conductive layer, a doped polysilicon, filled inside, comprised in the gate region; at least a gate runner metal layer formed on the first surface according to the gate region; and at least a source metal layer formed on the first surface according to the source region; wherein the gate trenches distinguished into at least a first gate trench wrapped in the source region, and at least a second gate trench formed at a terminal of the source region for gate metal contact; and the second gate trench comprises a gate contact hole which is filled with metal to form a gate metal contact plug electrically connected with the gate runner metal layer, and a gate buffer layer which is formed at where is corresponding to the gate contact hole in the gate conductive layer of the second gate trench and is selected from a undoped polysilicon layer or a lightly doped polysilicon layer with less doping of polysilicon than the gate conductive layer, wherein the trench width of the second gate trench at the terminal of the source region is wider the first gate trench in source region.