Patent ID: 7454587

Claim:
An integrated circuit for managing memory logic, comprising: user logic for providing allocation requests for the memory logic, access requests for the memory logic, and de-allocation requests for the memory logic; virtual port logic coupled to the user logic and the memory logic; and a processor coupled to the virtual port logic; wherein the virtual port logic is configured to forward the allocation requests and de-allocation requests to the processor, and to process the access requests; and wherein the processor is configured to allocate space in the memory logic in response to the allocation requests and de-allocate space in the memory logic in response to the de-allocation requests; wherein the memory logic includes a plurality of memories, wherein the user logic includes a plurality of logic blocks, and wherein the virtual port logic includes a plurality of cluster managers and a plurality of virtual ports, each of the plurality of cluster managers being coupled to at least one of the plurality of virtual ports, each of the plurality of virtual ports begin coupled to at least one memory of the plurality of memories and at least one logic block of the plurality of logic blocks.