Patent ID: 7692501

Claim:
An optical communication system including a clock and data recovery circuit, comprising: a phase detector to receive as input a data signal and a clock signal, the phase detector to sample the data signal at a plurality of sampling points to partition a clock cycle into four phase regions P 1 , P 2 , P 3 , and P 4 , the phase detector further to determine in which phase region a date transition edge occurs to generate an UP or DOWN signal to adjust clock signal phase; a frequency detector to generate a TIMING signal if the data transition edge traverses a P 2 /P 3 boundary and a UNLOCKED signal if the data transition edge traverses a P 1 /P 2 boundary, the frequency detector further comprising a latch receiving as an input the TIMING signal and latched by the UNLOCKED signal to produce a SPEED signal, the TIMING signal, the UNLOCKED signal and the SPEED signal used to adjust clock signal frequency.