Patent ID: 8557674

Claim:
A method of fabricating a high voltage semiconductor device, the method comprising: forming a field shaping layer on substantially the entire surface of a first conductivity-type semiconductor substrate, wherein the impurity concentration of the field shaping layer is higher than that of the semiconductor substrate; forming a second conductivity-type semiconductor layer on the field shaping layer; forming a first insulating layer on the semiconductor layer; forming a first conductivity-type body region in the semiconductor layer; forming a second insulating layer on the semiconductor layer except for portions of the semiconductor layer and a portion of the body region; forming a gate on a portion of the first insulating layer and a portion of the second insulating layer, wherein the gate overlaps a portion of the body region and a portion of the semiconductor layer; forming a second conductivity-type source region in the body region and a drain region in the body region, wherein the source region is separated from the drain region.