Patent ID: 8703550

Claim:
A method of forming a semiconductor structure comprising: etching a shallow trench laterally surrounding a stack of a top semiconductor portion, a buried insulator portion, and an upper portion of a handle substrate in a semiconductor-on-insulator (SOI) substrate; depositing a stack of a dielectric metal oxide liner and a silicon nitride liner in said shallow trench; recessing said dielectric metal oxide liner to a depth between a top surface of said buried insulator portion and a bottom surface of said buried insulator portion, wherein a divot laterally surrounding said top semiconductor portion is formed by said recessing; filling said divot with a dielectric material portion laterally surrounding said top semiconductor portion, wherein said dielectric material portion is formed by depositing a conformal dielectric material layer within said divot and above said top semiconductor portion and removing said conformal dielectric material layer from above said divot, wherein a remaining portion of said conformal dielectric material layer laterally surrounds said top semiconductor portion; filling said shallow trench with a shallow trench fill portion; and forming a semiconductor device on said top semiconductor portion.