Patent ID: 8232627

Claim:
A device comprising: a semiconductor layer; multiple gates on said semiconductor layer, said gates defining channel regions in said semiconductor layer for multiple planar field effect transistors connected in a series; gate sidewall spacers adjacent to said gates; source/drain regions within said semiconductor layer on opposing sides of each of said channel regions such that each portion of said semiconductor layer between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor; and a conformal conductive layer above said multiple planar field effect transistors, said conformal conductive layer conformally covering said source/drain regions, said gate sidewall spacers and said gates, being electrically isolated from said gates, and being in contact with said source/drain regions, said conformal conductive layer comprising a conductive material having a higher resistance than said channel regions when said multiple planar field effect transistors are in an “on” state and a lower resistance than said channel regions when said multiple planar field effect transistors are in an “off” state.