Patent ID: 7947588

Claim:
A method comprising: providing a semiconductor substrate having a first and second region; forming an interfacial dielectric layer over the semiconductor substrate; forming a high-k dielectric layer over the interfacial dielectric layer; forming a first doped-conducting metal oxide layer over the high-k dielectric layer in the first region; forming a second doped-conducting metal oxide layer over the high-k dielectric layer in the second region; forming a capping layer over the first doped-conducting metal oxide layer and the second doped-conducting metal oxide layer; patterning and etching the capping layer, the second doped-conducting metal oxide layer, the first doped-conducting metal oxide layer, the high-k dielectric layer, and the interfacial layer, wherein the patterning and etching forms a first gate stack in the first region and a second gate stack in the second region, the first gate stack including the interfacial layer, the high-k dielectric layer, the first doped-conducting metal oxide layer, and the capping layer, and the second gate stack including the interfacial layer, the high-k dielectric layer, the second doped-conducting metal oxide layer, and the capping layer.