Patent ID: 7941472

Claim:
An apparatus for correlating M-bit first and second signals comprises: a plurality of N-bit correlators, where N is less than M, each of said N-bit correlators of said plurality comprising: (a) an N-bit multiplexer including an N-bit input port coupled to receive a subset of bits of said M-bit second signal, and also including a single-bit output port, for selectively coupling to its output port one bit at a time of the subset of bits; (b) a multiplier including an output port, a first multibit input port and second single-bit input port, said single-bit input port of said multiplier being coupled to the output port of said multiplexer for receiving said one bit at a time, said multiplier being coupled for receiving the first signals in parallel form at its first input port, for controllably coupling to its output port a multibit product signal in response to that one bit of said second signal applied to its second input port, and for one of (a) multiplying the words of the first signal by +1 if the one bit of the second digital signal applied to its second input port has a logical value of 1 and by −1 if the one bit of the second digital signal applied to its second input port has a logical value of 0, and (b) multiplying the words of the first signal by −1 if the one bit of the second digital signal applied to its second input port has a logical value of 1 and by +1 if the one bit of the second digital signal applied to its second input port has a logical value of 0; (c) a summer including an input port coupled to the output port of the multiplier, for summing the multiplied parallel signals received from the multiplier with delayed parallel signals, to thereby produce summed parallel signals representing the correlated output; and a delay circuit coupled to receive the summed parallel signals, for delaying the summed parallel signals for a number of clock cycles at least equal to the number of bits in the digital first signals, for thereby producing the delayed parallel signals; and a clocked register for selectively applying said summed parallel signals representing the correlated output from one of said N-bit correlators to the next one of said N-bit correlators in a cascade.