Patent ID: 7129119

Claim:
A method for fabricating semiconductor packages, comprising the steps of: preparing a plurality of substrates, wherein a length and width of each of the substrates are equal to a predetermined length and width of each of the semiconductor packages, respectively, and each of the substrates is mounted with at least one chip thereon; preparing a carrier having a plurality of openings, with a protruded portion of the carrier being formed at each corner position of each of the openings and extending toward a center of each of the openings, wherein a distance between two protruded portions at diagonal corner positions of each of the openings is larger than that between two diagonal corners of each of the substrates; embedding and fixing the plurality of substrates in the plurality of openings respectively, and sealing gaps between the substrates and the carrier; performing a molding process to form an encapsulant over each of the openings to encapsulate the corresponding chip, wherein an area on the carrier covered by the encapsulant is larger in length and width than the corresponding opening; performing a mold-releasing process; and performing a singulation process to cut along edges of the substrates so as to form a plurality of the semiconductor packages.