Patent ID: 7324389

Claim:
A non-volatile memory, comprising: a memory array of non-volatile storage units partitioned into an user array portion and a redundant array portion such that a defective location in the user array portion is replaceable by a redundant location in the redundant array portion; a group of access circuits including a group of data latches for latching data associated with both the user array portion and the redundant array portion; a data bus; a defect map buffer for storing addresses of defective locations of the user array portion; a redundant data buffer for storing redundant data from the data latches of the redundant array portion; and redundant data buffer control circuits responsive to a current address of the user array portion that does not correspond to a defective location in the defect map buffer to enable exchange of data between said data bus and said user portion data latches and, responsive to a current address of the user array portion that corresponds to a defective location in said defect map buffer to enable exchange of data between said data bus and said redundant data buffer.