Patent ID: 7099188

Claim:
A memory comprising: a bit line connected to a column of memory cells; a first reference bit line connected to a column of reference cells; a plurality of word lines, wherein each word line is coupled to control one of the memory cells and one of the reference cells; a sense amplifier coupled to sense a difference between the bit line and the first reference bit line; a bias bit line coupled to a column of reference cells, each reference cell coupled to the bias bit line being connected to a corresponding one of the word lines; a first pull-up device coupled to the first reference bit line during a sensing operation; a bias pull-up device coupled to the bias bit line during the sensing operation; and a normal pull-up device coupled to the bit line during the sensing operation, wherein the first and normal pull-up devices are coupled to mirror a current through the bias pull-up device, wherein the first pull-up device has a first effective size, and the normal pull-up device has an effective size that differs from the first effective size.