Patent ID: 7068072

Claim:
An integrated circuit die comprising an array of tiles, the tiles arranged in rows and columns, wherein one of the tiles is a routing tile having four edges, the routing tile having other tiles adjacent each of its four edges, the routing tile comprising: a first routing conductor that extends to a first of the four edges of the tile; and a micropad that has an exposed and conductive upper surface, the micropad being couplable to the first routing conductor such that a signal received onto the micropad from a source external to the integrated circuit die can be communicated from the micropad to the first routing conductor and to the first of the four edges of the tile; wherein the first routing conductor is a conductor segment that extends to the first edge of the tile, and wherein the first edge of the tile abuts a second tile, the second tile having a conductor segment that meets the first routing conductor end-to-end at the first edge to form a conductor that extends from a point inside the tile to a point inside the second tile.