Patent ID: 7170183

Claim:
A wafer level stacked package comprising: a substrate comprising: an insulative layer having a first surface, a second surface being opposite to the first surface, and four third surfaces being formed around and substantially perpendicular to the first and second surfaces; at least an electrically conductive terminal formed on the third surfaces of the insulative layer; at least a first electrically conductive pattern formed on the first surface of the insulative layer; and at least a second electrically conductive pattern formed on the second surface of the insulative layer; a first semiconductor die being connected to the first surface of the insulative layer, wherein the first semiconductor die comprises: a first surface; a second surface being opposite to the first surface of the first semiconductor die and formed with at least a bond pad; and four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the first semiconductor die, wherein each third surface of the first semiconductor die and each corresponding third surface of the insulative layer are substantially coplanar with one another and form the same plane; and a second semiconductor die being connected to the second surface of the insulative layer, wherein the second semiconductor die comprises: a first surface; a second surface being opposite to the first surface of the second semiconductor die and being formed with at least a bond pad; and four third surfaces being formed around and substantially perpendicular to the first and second surfaces of the second semiconductor die, wherein each third surface of the second semiconductor die and each corresponding third surface of the insulative layer are substantially coplanar with one another and form the same plane.