Patent ID: 6891262

Claim:
A semiconductor device comprising: a plurality of memory transistors arranged in an array; a plurality of word lines extending in a row direction and repeating at distances in a column direction, said word lines being gate electrodes for said plurality of memory transistors; a first charge storage film on a semiconductor, said first charge storage film including a plurality of first films and having a first charge storage capability; first word lines of said plurality of word lines on said first charge storage film and in parallel with each other at predetermined distances; a second charge storage film covering surfaces of said first word lines and surfaces of said semiconductor exposed between said first word lines, said second charge storage film including a plurality of second films and having a second charge storage capability; and second word lines of said plurality of word lines facing said surfaces of said semiconductor exposed between said first word lines across said second charge storage film, said second word lines being insulated and isolated from said first word lines by said second charge storage film, wherein said first word lines and said second word lines extend outward from a memory cell array region and then are bent in a direction different from a direction of arrangement of said word lines, and wherein a pitch of arrangement between said first word lines and said second word lines at front end sides from said bent portions is set larger than a pitch of arrangement between said first word lines and said second word lines in said memory cell array.