Patent ID: 8391350

Claim:
Decision feedback equalizer (“DFE”) circuitry for operating on a serial data signal comprising: circuitry for delaying a digitized, serial data output signal of the DFE circuitry by passing that signal successively through a plurality of respective delay circuit elements so that, at any given time, each respective delay circuit element outputs one respective previous bit from the serial data output signal of the DFE circuitry; circuitry for applying a respective scaling factor to a respective output signal of each of the respective delay circuit elements to produce a respective feedback signal; circuitry for combining the serial data signal with the respective feedback signals to produce a source signal for the output signal of the DFE circuitry; and circuitry for determining the respective scaling factor for each of the respective feedback signals based on (1) an algebraic sign of error in the output signal of the DFE circuitry and (2) the output signal of the respective delay circuit element, including circuitry for integrating over time a product signal for each of the respective scaling factors to produce a time-integrated signal for use in determining each of the respective scaling factors.