Patent ID: 8532296

Claim:
A processor connected to a memory device comprising: a random number generator that generates random numbers identical to random numbers generated in the memory device, the random numbers related to reproducing a specified address for access in the memory device; an XOR logic unit that performs an XOR operation of the random numbers generated by the random number generator and the specified address in the memory device to be accessed; an after-operation-address sending unit that sends an after-operation-address indicating a result of the XOR operation; a transfer sequence changing unit that stores a rule for determination of an access order based on the random numbers generated by the random number generator; a control unit that controls access to the specified address, wherein the access to the specified address is accessed according to the access order determined by the transfer sequence changing unit based on the rule; an encryption unit that encrypts data sent by the processor by using the specified address in the memory device for the data or a portion of the specified address as an encryption key; and an encrypted data sending unit that sends the encrypted data.