Patent ID: 8035601

Claim:
An image display device comprising: a pixel block having a plurality of pixel circuits arranged on an image display panel in a matrix form; a gate driver section which generates a signal for scanning each of the pixel circuits; a data driver section which supplies a video signal via a data signal line to each of the pixel circuits; a protection circuit block; and a level shift circuit which converts a low amplitude signal to a high amplitude signal and which transmits the high amplitude signal to the gate driver section and the data driver section, wherein the level shift circuit includes a first PMOS transistor and a second PMOS transistor each having a source electrode connected to a power voltage and a gate electrode and a drain electrode, the gate electrode of the first PMOS transistor being connected to the drain electrode of the second PMOS transistor, the drain electrode of the first PMOS transistor being connected to the gate electrode of the second PMOS transistor; a first NMOS transistor having a source electrode connected to ground, a drain electrode connected to the drain electrode of the first PMOS transistor via the protection circuit block, and a gate electrode connected to an input terminal; a second NMOS transistor having a source electrode connected to ground, a drain electrode connected to the drain electrode of the second PMOS transistor via the protection circuit block, and a gate electrode connected to an input inverting terminal; a third NMOS transistor having a gate electrode connected to the drain electrode of the first NMOS transistor via the protection circuit block and to the drain electrode of the first PMOS transistor, a drain electrode connected to the drain electrode of the second NMOS transistor via the protection circuit block, and a source electrode connected to the gate electrode of the first NMOS transistor via the protection circuit block; and a fourth NMOS transistor having a gate electrode connected to the drain electrode of the second NMOS transistor via the protection circuit block and to the drain electrode of the second PMOS transistor, a drain electrode connected to the drain electrode of the first NMOS transistor via the protection circuit block, and a source electrode connected to the gate electrode of the second NMOS transistor via the protection circuit block, wherein the pixel block, the gate driver section, the data driver section, the protection circuit block, the first and second PMOS transistors, and the third and fourth NMOS transistors are comprised of TFT devices formed on a glass substrate, and wherein the first and second NMOS transistors are monocrystal silicon semiconductor devices formed on a semiconductor substrate.