Patent ID: 8669620

Claim:
A semiconductor device comprising: first and second MOS transistors, each MOS transistor comprising source and drain regions formed on a main surface of a semiconductor substrate, a channel region sandwiched between the source and drain regions, and a gate electrode provided over the channel region through a gate insulating film; a circuit comprising the first MOS transistor whose gate is connected to a first signal line and the second MOS transistor whose gate is connected to a second signal line, the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line; and a third MOS transistor including source and drain regions formed on the main surface of the semiconductor substrate, a channel region sandwiched between the source and drain regions and a gate electrode provided over the channel region through a gate insulating film; wherein the channel regions of the first and second MOS transistors include no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms the source and drain regions, and the channel region of the third MOS transistor contains a second impurity whose concentration has a maximum value at a second depth and is simply decreased from the second depth toward the surface of the semiconductor substrate.