Patent ID: 7519849

Claim:
A computer system, comprising: a host module (HM); and a plurality of client modules (CMs) in communication with the HM and each including one or more associated registers, wherein each of the CMs is separately addressable and at least one of the CMs operates at a different clock frequency than the remaining CMs and includes a clock synchronizer, and wherein the clock synchronizer provides a clock enable signal to facilitate reading of or writing to the associated registers of the at least one of the CMs by the HM; and a control and status register (CSR) bus coupling the HM to the CMs, wherein the CSR bus includes separate data-in lines coupling the HM to each of the CMs and a common data-out line coupling the HM to all of the CMs and the HM receives data from an addressed one of the CMs on an associated one of the data-in lines and provides data to the CMs on the data-out line, and wherein the one or more associated registers each include at least one control register and at least one status register.