Patent ID: 7169655

Claim:
A method for fabricating an FET comprising: forming a first insulating layer above a semiconductor substrate; forming a first conductive layer for a fin above the first insulating layer; etching the first conductive layer so that an area of a lower part of the first conductive layer is wider than an area of an upper part of the first conductive layer; forming voltage adjust regions through an ion implantation method; forming a gate insulating layer of transition metal oxynitride by depositing a transition metal or an alloy of transition metals, reoxidizing the transition metal or the alloy of transition metals on the first conductive layer to form a transition metal oxide layer, and performing a forming gas annealing process to form transition metal oxynitride, wherein the forming gas includes N 2 and H 2 ; forming a second conductive layer on the gate insulating layer, patterning the second conductive layer and the gate insulating layer to form a gate electrode, wherein the gate insulating layer is in full contact with the gate electrode between the gate electrode and the first insulating layer and the gate electrode and the first conductive layer; forming LDD regions by implanting ions into the first conductive layer; forming sidewall spacers on sidewalls of the gate insulating layer and the gate electrode; and forming source/drain regions adjacent to the sidewall spacers by implanting ions into the first conductive layer.