Patent ID: 7375554

Claim:
Voltage level translation circuitry, comprising: a first input node; a first output node; a first translator circuit comprising at least a first, second, and third transistor, each having a first terminal, a second terminal, and a third terminal, wherein: the first transistor having said first terminal coupled to a first voltage source, and said second terminal coupled to said first output node; the second transistor having said first terminal coupled to said first output node, and said third terminal coupled to a second voltage source; and the third transistor having said first terminal coupled to said second terminal of said second transistor, said second terminal coupled to a third voltage source, and said third terminal coupled to said first input node; and a first voltage protection circuit coupled to at least one of said first, second, and third transistors, wherein said first voltage protection circuit comprises at least one transistor having a first terminal, a second terminal, and a third terminal, and wherein: the first terminal of said at least one transistor of said first voltage protection circuit is coupled to the second voltage source; the second terminal of said at least one transistor of said first voltage protection circuit is coupled to a node between the second and third transistors; and the third terminal of said at least one transistor of said first voltage protection circuit is coupled to the first input node.