Patent ID: 7327014

Claim:
A semiconductor integrated circuit device comprising: grooves formed in a semiconductor substrate and defining a first dummy region, second dummy regions and a third dummy region such that a width of the first dummy region is greater than a width of each of the second dummy regions and such that a width of the third dummy region is greater than a width of each of the second dummy regions; element isolation insulating films filled in the grooves such that the element isolation insulating films are adapted to serve as an element isolation region; a conductor pattern formed over the first dummy region and adapted to be used for optical pattern recognition; and dummy conductor patterns formed with the same level layer as the conductor pattern, wherein the first dummy region is formed under the conductor pattern such that the grooves are not formed under the conductor pattern, wherein the first dummy region and the dummy conductor patterns are formed at a scribing area, wherein the second dummy regions are spaced from one another by a predetermined spacing at the scribing area and at a product area, and wherein the third dummy region is formed at the product area.