Patent ID: 8913618

Claim:
A system comprising: a source processor; and a memory configured to communicate with the source processor, the memory having instructions stored thereon that, in response to being executed, cause the source processor to perform operations comprising: assigning a time stamp and a priority value to a plurality of packets, the time stamp comprising a transmission latency parameter and a current time for at least one packet of the plurality of packets; accounting for transmission latency based on the transmission latency parameter for the at least one packet, the accounting comprising updating the time stamp for the at least one packet based on the current time and the transmission latency parameter for the at least one packet; and transmitting the plurality of packets through a plurality of communication fabrics to a destination processor configured to: determine order information based on the time stamp and the priority value, and output a data stream in response to an instant time stamp matching the updated time stamp for the at least one packet.