Patent ID: 8860141

Claim:
A method for improving tracking between FETs (Field Effect Transistor) in an SRAM (Static Random Access Memory) cell on a semiconductor chip produced in a process having a photolithography limitation of 14 nm or smaller minimum feature size requiring a first gate definition mask to define a first set of gates shapes on a gate shape level and a second gate definition mask to define a second set of gate shapes on the gate shape level, the second set of gate shapes interdigitated with the first set of gate shapes on the gate shape level to produce gate shapes on the gate shape level at a minimum pitch supported by the 14 nm photolithography process comprising: the method comprising: identifying all FETS in the SRAM cell that require close tracking in FET characteristics; and laying out the SRAM cell such that all the FETs identified as requiring close tracking are defined by the first gate definition mask on the gate shape level.