Patent ID: 8098505

Claim:
In an interleaved power factor correction (PFC) circuit with a plurality of channels providing input power to a load, a method comprising: shedding a first channel in the plurality of channels when a compensation voltage indicative of an output power of the PFC circuit reduces to a value below a phase shedding threshold, wherein ON time of a second channel in the plurality of channels is increased to compensate for loss of input power provided by the first channel to the load, the first and second channels operating out of phase; adding the first channel to provide input power to the load when the compensation voltage increases to a value above a phase adding threshold, wherein ON time of the second channel is reduced to compensate for additional input power provided by the first channel to the load; detecting when an input AC line voltage to the PFC circuit crosses zero; and allowing the shedding and the adding of the first channel to occur only during a time the AC line voltage is zero.