Patent ID: 6865695

Claim:
A shared memory computer system, comprising: a plurality of processing nodes connected to operate in a high speed, high bandwidth system interconnect topology; each of the processing nodes having at least one processor therein that executes software instructions to process data; volatile memory distributed in one or more of said processing nodes providing data and instruction storage in a shared memory address space accessible to multiple of said plurality of processing nodes through communication via said high speed system interconnect; a recovery bus operating at a lower speed than the high speed topology and connecting the plurality of processing nodes together; cache coherency circuitry snooping communication on the high speed system interconnect topology to maintain cache coherency in said distributed volatile memory; agents in the processing nodes monitoring the high speed interconnect topology to sense an error therein; and the agents in the processing nodes transferring communication from the high speed interconnect topology to the recovery bus in response to sensing an error in the high speed interconnect topology.