Patent ID: 7638403

Claim:
A manufacturing method of an integrated circuit structure, comprising: providing a substrate with a heavily doped region and a lightly doped region formed thereon; forming a dielectric layer on the substrate; forming a contact hole and an opening simultaneously in the dielectric layer, exposing the heavily doped region and the lightly doped region respectively; forming a barrier layer on the dielectric layer; forming a first metal layer on the barrier layer; removing a part of the first metal layer on the dielectric layer above the heavily doped region and a part of the first metal layer in the opening, wherein the step of removing the part of the first metal layer leaves the first metal layer filled in the contact hole and makes the remaining first metal layer in the opening form a spacer on a sidewall of the opening; forming a second metal layer over the substrate; and patterning the second metal layer to separate the second metal layer above the heavily doped region from the second metal layer above the lightly doped region.