Patent ID: 8637959

Claim:
A vertical parasitic PNP transistor in a BiCMOS process, formed on a silicon substrate, wherein an active region is isolated by shallow trench isolations, comprising: a collector region, comprising a 9-type ion implantation region formed in the active region, wherein the collector region is deeper than or equal to the bottom of the shallow trench isolations; pseudo buried layers, comprising P-type ion implantation regions formed at the bottom of the shallow trench isolations located on both sides of the collector region, wherein the pseudo buried layers extend laterally into the active region and contact with the collector region, and the electrodes of the collector region are picked up through deep-hole contacts formed on top of the pseudo buried layers in the shallow trench isolations; abuse region, comprising an N-type ion implantation region formed on the collector region and contacting with the collector region; an emitter region, comprising a P-type Silicon-Germanium epitaxial layer formed on the base region and contacting with the base region, wherein the electrode of the emitter region is directly picked up through a metal contact; N-type polysilicon, formed on the base region and contacting with the base region, wherein the electrodes of the base region are picked up through metal contacts on the N-type polysilicon.