Patent ID: 7852839

Claim:
A system for processing Asynchronous Transfer Mode (ATM) cells at an interface arranged between a first and a second node of a transmission system, in an order according to ATM channels comprising: a Content Addressable Memory (CAM); and an autoconfiguration unit coupled to the CAM, the autoconfiguration unit generating queries to the CAM and receiving results of queries from the CAM, the autoconfiguration unit further performing the steps of: a) determining address information for a specific ATM cell; b) verifying, whether the address information has already been recorded in a table, in which the address information is mapped onto a channel ID (CH), by providing the address information to CAM; b1) when the address information has already been recorded in the table: assigning the mapped channel ID (CH) from the CAM memory to the ATM cell for further processing; b2) when the address information has not yet been recorded in the table: indicating that the address information has not yet been recorded; assigning an available channel ID (CH) to the address information; recording said available channel ID (CH) and the address information in the table; wherein step b) uses a main state machine to generate a request to the CAM memory, and uses a result state machine to record the result of the request in step b1) and in step b2); and wherein the main state machine, the CAM memory and the result state machine are synchronized with each other to a common clock signal, whereby the main state machine generates a plurality of requests during a first group of clock cycles and applies the requests to the CAM memory, whereby the CAM memory makes results of the requests available to the result state machine during a second group of clock cycles, whereby a duration of the second group of clock cycles is longer than a duration of the first set of clock cycles; and c) providing the ATM cells, in an order according to channel IDs (CH) assigned to the ATM cells, for further processing.