Patent ID: 7313181

Claim:
A circuit to calibrate a scalar in an adaptive equalizer during a training sequence, the circuit comprising: a discrete-time FIR (Finite Impulse Response) filter comprising n multiplier units to implement a filter response [ h (t)] i , i=0,1, . . . , n−1, where t is a time index; a data generator to provide a discrete-time sequence of desired voltages d(t), t=1,2, . . . , T, a multiplier to provide a sequence of voltages Kd(t), t=1,2, . . . , T, where K is the scalar; a filter increment generator to provide, for t=1,2, . . . , T, n voltages indicative of n filter increments [δ h (t)] i , i=0,1, . . . , n−1; at least one summer to perform the sum [ h (t)] i ,+[δ h (t)] i , i=0,1, . . . , n−1, to update the filter response; an overflow counter to provide an overflow count indicative of the number of numerical overflows in the at least one summer during the time period t=1,2, . . . , T; wherein the scalar K is increased by a first increment if after completion of the time period t=1,2, . . . , T the overflow count and a threshold satisfy a first relationship, and wherein the scalar K is used during the training sequence to update the adaptive equalizer.