Patent ID: 8861265

Claim:
A semiconductor storage device comprising: a memory cell array comprising memory cells each including a variable resistance element, the memory cells arranged at crossing portions between a plurality of first wirings and a plurality of second wirings; and a control circuit configured to apply a predetermined voltage to a selected first wiring and a selected second wiring to thereby apply a voltage to a memory cell disposed at a crossing portion between the selected first wiring and the selected second wiring, the control circuit executing: a set operation of applying a set pulse to the variable resistance element to change the variable resistance element from a high resistance state to a low resistance state; a reset operation of applying a reset pulse to the variable resistance element to change the variable resistance element from the low resistance state to the high resistance state, the reset pulse having an opposite polarity to the polarity of the set pulse; and a training operation of continuously applying the set pulse and the reset pulse to the variable resistance element.