Patent ID: 7227775

Claim:
A memory comprising: a memory array that includes a plurality of two-terminal memory cells; a plurality of array lines that access the memory array; at least one reference cell external to the memory array and accessed by at least some of the array lines, wherein the reference cell is a two-terminal memory cell and contributes to a reference level; and a substrate positioned below the memory array and the reference cell, the substrate including, address lines operable to carry address signals, control lines operable to carry control signals, data lines operable to carry data signals, and a plurality of drivers that, as a function of the control signals, are operative to cause selected array lines to be placed at a first write voltage, a second write voltage, or a read voltage; sensing circuitry, and address decoding circuitry operative to decode the address signals on the address lines and to activate certain array lines; wherein the two-terminal memory cells are operable to be reversibly written to a first non-volatile resistive state when the selected array lines are at the first write voltage, reversibly written to a second non-volatile resistive state when the selected array lines are at the second write voltage, and produce a read output when the selected array lines are at the read voltage, and wherein the sensing circuitry is operative to compare the read output to the reference level and produce data signals.