Patent ID: 8072238

Claim:
An integrated circuit comprising: a first logic element comprising a first sub-function generator, wherein the first sub-function generator comprises a first set of selection inputs, wherein all selection inputs of the first set are operable to receive selection signals of a first plurality; a second logic element comprising a second sub-function generator, wherein the second sub-function generator comprises a second set of selection inputs, wherein all selection inputs of the second set are operable to receive selection signals of a second plurality other than the selection signals of the first plurality, wherein the first sub-function generator is operable to provide a first sub-function output signal based on the selection signals of the first plurality, wherein the second sub-function generator is operable to provide a second sub-function output signal based on the selection signals of the second plurality; and first programmable sharing circuitry coupled to the first and second logic elements, wherein the first programmable sharing circuitry is operable to use the first and second sub-function output signals to allow the first logic element to implement a function of a first order, wherein the first order is higher than a second order of a function implemented by the second logic element.