Patent ID: 7927963

Claim:
A method of forming a semiconductor structure, said method comprising: providing a wafer comprising: a semiconductor substrate comprising a single crystalline semiconductor material; an insulating layer on said semiconductor substrate; and a semiconductor layer on said insulating layer; forming a shallow trench isolation region within said semiconductor layer and a first deep trench isolation region extending through said semiconductor layer and said insulator layer to said semiconductor substrate such that said shallow trench isolation region and said first deep trench isolation region are separated by semiconductor material and such that said first deep trench isolation region comprises a different material than said insulating layer and said shallow trench isolation region, said forming defining an integrated circuit device area of said wafer; etching a trench extending through said shallow trench isolation region and said insulating layer and stopping one of at a top surface of said semiconductor substrate and a predetermined depth within said semiconductor substrate; implanting inert ions into said semiconductor substrate so as to form an at least partially amorphized region of said semiconductor substrate adjacent to a bottom surface of said trench; performing an isotropic etch process to selectively remove a portion of said insulating layer and said shallow trench isolation region within said integrated circuit device area of said wafer so as to create an air gap between said semiconductor layer and said semiconductor substrate and an opening within said semiconductor layer extending to said air gap; and depositing a dielectric material through said opening and into said air gap so as to form a second deep trench isolation region.