Patent ID: 7790553

Claim:
A method comprising: providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a trench isolation; forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different, wherein the forming a FET includes: forming a first stack including a first gate dielectric layer and a polysilicon layer over the long channel region only, forming a second stack including a second gate dielectric layer, the first work function adjusting material and a first metal over the first short channel active region; forming a third stack including a third gate dielectric layer, the second work function adjusting material and a second metal over the second short channel active region; depositing polysilicon over the substrate; and forming a gate structure for each of the first and second short channel regions and the long channel region from the first, third and second stacks and the polysilicon.