Patent ID: 7968924

Claim:
A semiconductor device including: a nonvolatile memory cell having a first field effect transistor in a first region of a principal surface of a semiconductor substrate, and a second field effect transistor adjacent to the first field effect transistor, in a second region; and a capacitive element for a power supply circuit, in a third region, said nonvolatile memory cell comprising: a first insulating film formed in the first region; a first gate electrode of the first field effect transistor formed over the first insulating film; a second insulating film formed in the second region, including a charge storage layer having a function for storing charge; a second gate electrode of the second field effect transistor formed over the second insulating film; and a third insulating film formed between the first gate electrode and the second gate electrode, said capacitive element comprising: a first capacitor formed between an active region surrounded by inter-device separation parts of the semiconductor substrate, formed in the third region, and a lower electrode provided, through a first capacitive insulating film, over the active region surrounded by the inter-device separation parts of the semiconductor substrate; and a second capacitor formed between the lower electrode and an upper electrode provided, through a second capacitive insulating film, over the lower electrode, wherein the lower electrode is comprised of a conductor film in the same layer as the first gate electrode of the first field effect transistor, the second capacitive insulating film is comprised of an insulating film in the same layer as the second insulating film, and the upper electrode is comprised of a conductor film in the same layer as the second gate electrode of the second field effect transistor, wherein a planar shape of the lower electrode is a grid-like shape having a plurality of lengths of linear conductor films, each having a first width, formed along a first direction with a first interval provided therebetween, and a plurality of lengths of linear conductor films, each having a second width, formed along a second direction intersecting the first direction with a second interval provided therebetween, and wherein through a contact hole reaching an active region of a power supply unit, surrounded by inter-device separation parts of the semiconductor substrate, and through a contact hole reaching an outlet of the upper electrode, the active region of the power supply unit is coupled to the outlet of the upper electrode through an interconnection, thereby parallel-coupling the first capacitor to the second capacitor.