Patent ID: 7830887

Claim:
An apparatus, comprising: a Central Processing Unit (CPU) Management Interface Controller (CMIC) configured to transmit packets between at least a portion of the apparatus and a CPU using a plurality of channels, and the CMIC comprising: a class of service bitmap associated with the plurality of channels, and the plurality of channels, wherein each of the plurality of channels is associated with at least one class of service, includes a per channel bit, is configured to store one or more packets, and is assigned a priority level, wherein the CMIC is further configured to sort packets according to the class of service to which the packet belongs, store each packet in an associated one of the plurality of channels, use the per channel bit to determine how to process packets in each of the plurality of channels for which there is no available CPU buffer, and when there is no available CPU buffer for one of the plurality of channels, set an appropriate bit in the class of service bitmap and transmit the class of service bitmap to a memory management unit.