Patent ID: 8466012

Claim:
A method for fabricating a complementary metal-oxide semiconductor (CMOS) circuit having a SOI finFET device and a bulk finFET device, the method comprising the steps of: providing a wafer having an active layer separated from a substrate by a buried oxide (BOX), wherein the wafer has at least a first region and a second region; removing portions of the active layer and the BOX in the second region of the wafer so as to expose the substrate; growing an epitaxial material in the second region of the wafer templated from the substrate; forming a first fin lithography hardmask on the active layer in the first region of the wafer and a second fin lithography hardmask on the epitaxial material in the second region of the wafer; etching a plurality of first fins in the active layer using the first fin lithography hardmask and a plurality of second fins in the epitaxial material using the second fin lithography hardmask; forming a first gate stack covering at least a portion of each of the first fins and a second gate stack covering at least a portion of each of the second fins, wherein the portions of the first fins covered by the first gate stack serve as a channel region of the SOI finFET device and the portions of the second fins covered by the second gate stack serve as a channel region of the bulk finFET device; and growing an epitaxial material on exposed portions of the first fins which serves as source and drain regions of the SOI finFET device and an epitaxial material on exposed portions of the second fins which serves as source and drain regions of the bulk finFET device.