Patent ID: 7873161

Claim:
An apparatus for performing a SubByte function of the Rijndael Block Cipher, comprising: an S-box circuit including an inverse transformation circuit having a lookup table and being configured and arranged to transform an input using a look-up table, wherein the look-up table is the multiplicative inverse in the finite field GF(2 8 ) having {00} mapped to itself, and the look-up table is implemented by a read-only memory (ROM); a combinational logic circuit configured and arranged to perform an affine-all transformation that performs both an affine and inverse affine transformation in response to respective load patterns, wherein the combinatorial logic circuit implements the equations: b′ 0 =[( b 0 ·p 0 )⊕( b 1 ·p 1 )⊕( b 2 ·p 2 )⊕( b 3 ·p 3 )⊕( b 4 ·p 4 )⊕( b 5 ·p 5 )⊕( b 6 ·p 6 )⊕( b 7 ·p 7 )]⊕ v 0 b′ 1 =[( b 0 ·p 7 )⊕( b 1 ·p 0 )⊕( b 2 ·p 1 )⊕( b 3 ·p 2 )⊕( b 4 ·p 3 )⊕( b 5 ·p 4 )⊕( b 6 ·p 5 )⊕( b 7 ·p 6 )]⊕ v 1 b′ 2 =[( b 0 ·p 6 )⊕( b 1 ·p 7 )⊕( b 2 ·p 0 )⊕( b 3 ·p 1 )⊕( b 4 ·p 2 )⊕( b 5 ·p 3 )⊕( b 6 ·p 4 )⊕( b 7 ·p 5 )]⊕ v 2 b′ 3 =[( b 0 ·p 5 )⊕( b 1 ·p 6 )⊕( b 2 ·p 7 )⊕( b 3 ·p 0 )⊕( b 4 ·p 1 )⊕( b 5 ·p 2 )⊕( b 6 ·p 3 )⊕( b 7 ·p 4 )]⊕ v 3 b′ 4 =[( b 0 ·p 4 )⊕( b 1 ·p 5 )⊕( b 2 ·p 6 )⊕( b 3 ·p 7 )⊕( b 4 ·p 0 )⊕( b 5 ·p 1 )⊕( b 6 ·p 2 )⊕( b 7 ·p 3 )]⊕ v 4 b′ 5 =[( b 0 ·p 3 )⊕( b 1 ·p 4 )⊕( b 2 ·p 5 )⊕( b 3 ·p 6 )⊕( b 4 ·p 7 )⊕( b 5 ·p 0 )⊕( b 6 ·p 1 )⊕( b 7 ·p 2 )]⊕ v 5 b′ 6 =[( b 0 ·p 2 )⊕( b 1 ·p 3 )⊕( b 2 ·p 4 )⊕( b 3 ·p 5 )⊕( b 4 ·p 6 )⊕( b 5 ·p 7 )⊕( b 6 ·p 0 )⊕( b 7 ·p 1 )]⊕ v 6 b′ 7 =[( b 0 ·p 1 )⊕( b 1 ·p 2 )⊕( b 2 ·p 3 )⊕( b 3 ·p 4 )⊕( b 4 ·p 5 )⊕( b 5 ·p 6 )⊕( b 6 ·p 7 )⊕( b 7 ·p 0 )]⊕ v 7 having p=p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 a load pattern consisting of {10001111} for the affine transformation and {00100101} for the inverse affine transformation and having v as a load vector=v 0 v 1 v 2 v 2 v 4 v 5 v 6 v 7 consisting of {11000110} for the affine transformation and {10100000} for the inverse affine transformation.