Patent ID: 7580233

Claim:
A circuit for protecting a semiconductor chip from an electrostatic discharge (ESD) event, the circuit comprising: an ESD sensing circuit including an RC circuit, a first inverter, and a second inverter, the RC circuit connected between VDD and VSS, the first inverter connected between the second inverter and the RC circuit, the output of the second inverter providing an enable signal EN, the output of the first inverter providing a signal EN that is the inverse of EN; and a disable circuit configured to receive the EN and EN signals and disable the transistors of an output driver of the semiconductor chip, the disable circuit comprising: a first PMOS transistor configured to receive the EN signal at its gate and further configured to connect a second PMOS transistor to VDD when EN is low; and a first NMOS transistor configured to receive the EN signal at its gate and further configured to connect a second NMOS transistor to VSS when EN is high.