Patent ID: 7002496

Claim:
A calibrated digital-to-analog converter (DAC), comprising: a main DAC having a digital input and an analog output, the main DAC being configured, in the event a first input code value is applied to its digital input, to produce a corresponding first output voltage level at its analog output based on a transfer function of the main DAC; a memory having an address input and a data output, the memory being configured to store a first plurality of code values at respective locations within the memory, the respective memory locations being addressable by a second plurality of code values, wherein corresponding pairs of code values of the first and second pluralities of code values define respective breakpoints of a piecewise linear (PWL) approximation of the DAC transfer function, each code value of the second plurality representing a respective input code value, successive code values of the first plurality representing uniformly spaced output voltage levels corresponding to the respective code values of the second plurality; and calibration logic circuitry configured to receive the first input code value, to access a pair of code values of the first plurality from successive locations within the memory based on the first input code value, to compute a third code value using the accessed pair of code values by a PWL approximation technique, and to apply the computed code value to the digital input of the main DAC, thereby allowing the main DAC to produce a calibrated output voltage level corresponding to the first input code value.