Patent ID: 8238159

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array including an array of NAND cell units, each of the NAND cell units including a memory string having a plurality of non-volatile memory cells connected in series and select transistors each connected to an end of the memory string; word lines each connected to a control gate electrode of each of the non-volatile memory cells; bit lines each connected to a first end of each of the NAND cell units; a source line connected to a second end of each of the NAND cell units; and a control circuit configured to control a data read operation by selecting one of the non-volatile memory cells as a selected memory cell, the non-volatile memory cells being provided with a plurality of threshold voltage distributions allocated corresponding to multiple pieces of data to be stored, when performing the data read operation, the control circuit being configured to: apply a first voltage to a selected word line as one of the word lines that is connected to the selected memory cell, the first voltage being a voltage between the plurality of threshold voltage distributions; apply a second voltage to a first unselected word line as one of the word lines adjacent to the selected word line, the second voltage being not more than the first voltage; apply a third voltage to a second unselected word line as one of the word lines adjacent to the first unselected word line, the third voltage being not less than a read pass voltage at which the non-volatile memory cells may become conductive irrespective of the plurality of threshold voltage distributions provided thereto; and apply the read pass voltage to a third unselected word line, the third unselected word line being an unselected word line other than the first unselected word line and the second unselected word line.