Patent ID: 7301219

Claim:
A memory cell, comprising: a substrate; first and second impurity doped junctions on the substrate, the first and the second impurity doped junctions having a first polarity; a composite charge trapping layer defined over the substrate and between the first and the second impurity doped junctions, the composite charge trapping layer including a nonconductive charge trapping layer sandwiched between two dielectric layers, wherein charges of the memory cell are stored at an end of the nonconductive charge trapping layer that is above the second impurity doped region after the memory cell is programmed; a first impurity doped region positioned adjacent to the first impurity doped junction and under the composite charge trapping layer and having the first polarity; and a second impurity doped region being positioned adjacent to the second impurity doped junction and under the composite charge trapping layer and having a second polarity, wherein the second polarity is opposite to the first polarity.