Patent ID: 7093257

Claim:
A computer-implemented method performed in relation to a multi-processor system having a number of building blocks interconnected to one another via one of a crossbar and a scaleable coherent interconnect, the method comprising: in a first clock cycle, receiving an initial part of a non-network transaction by one of the building blocks from another of the building blocks, the transaction selected from the group essentially consisting of: a memory read, a memory invalidate, a memory write, an input/output (I/O) read, an I/O write, an interrupt, and an interrupt transaction; determining, in only the first clock cycle, non-network resources potentially needed by the transaction based on the initial part of the transaction received, the resources potentially needed by the transaction including resources actually needed by the transaction, the resources selected from the group essentially consisting of: memory, I/O, a bypass queue, a read or write buffer, a partial write buffer, a register queue, a register request, a bus side-band, an outband request credit, and a transaction identifier; allocating the resources potentially needed by the transaction; in a final clock cycle, receiving a final part of the transaction; and, determining the resources actually needed by the transaction from the resources potentially needed that were previously allocated, based at least on the final part of the transaction received.