Patent ID: 7839774

Claim:
A data processing circuit contained on an integrated circuit, comprising: a network ( 12 ) contained on the integrated circuit, that is operable in successive time-slots; a plurality of data processing units ( 10 ) contained on the integrated circuit, interconnected by the network ( 12 ), and arranged to send streams of messages concurrently through the network ( 12 ), each stream comprising messages that occupy shareable resources ( 20 ) in the network ( 12 ) in a periodically repeating selection of successive time-slots, a period of repetition (P) being the same for all the streams; node circuits ( 22 ) in the network ( 12 ), the node circuits ( 22 ) being arranged to forward the messages along multi-node paths through the network ( 12 ), each particular stream being assigned a respective stream specific path along which the node circuits ( 22 ) forward all messages of the particular stream, the node circuits ( 22 ) being arranged to decide whether to forward or discard each message dependent on a measure of seniority of the message in its particular stream, each particular node circuit ( 22 ) being arranged to prevent forwarding of a more junior message in the particular stream for which insufficient resources ( 20 ) are left because of forwarding of a more senior message from another stream from the particular node circuit ( 22 ) wherein at least one of the node circuits is arranged to send back a confirmation of successful forwarding of a message from an initial part of a particular stream up to said at least one of the node circuits, at least a further one of the node circuits ( 22 ) being arranged to forward a subsequent message from the particular stream only after timely reception of the confirmation.