Patent ID: 8581414

Claim:
A three-dimensional integrated circuit apparatus comprising: a first chip provided with a first via, a first wiring layer and an alignment marker; n pieces of chips (n is an integer equal to or greater than 1) stacked and bonded on a front surface side of the first chip; a first insulating film buried in a first through hole provided in a first region of the n pieces of chips located on the first via or the first wiring layer; a through electrode provided in the first insulating film, and buried in a second through hole being narrower than the first through hole in width so as to be in contact with the first via or the first wiring layer, a top of the through electrode being connected to a wiring layer of one of the n pieces of chips; and a second insulating film buried in a second through hole provided in a second region of the n pieces of chips located on the alignment marker.