Patent ID: 7941586

Claim:
A memory system comprising: a flash memory; a processing unit which generates a source address and a destination address for a copy-back program operation of the flash memory, and which generates control information for the copy-back program operation; and a flash controller including an address register, a control register, and a state machine, wherein the address register is configured to store the source and destination addresses from the processing unit, and the control register is configured to store the control information from the processing unit, wherein the state machine is configured to access the address register and the control register, and is further configured to control execution of the copy-back program operation in hardware alone and independently of the processing unit based on the source and destination addresses stored in the address register and the control information stored in the control register, and wherein the state machine is further configured to control a repeat execution of the copy-back program operation based on copy-back repeat information stored in the control register.