Patent ID: 8097915

Claim:
An integrated circuit including a semiconductor memory device comprising a plurality of memory cells, wherein each memory cell comprises a respective transistor, said transistor comprises: a transistor body of a first conductivity type, wherein the transistor body is electrically isolated from transistor bodies of neighboring memory cells; a drain area and a source area each having a second conductivity type, said drain area and source area are embedded in the transistor body on a first surface of said transistor body; a gate structure having a gate dielectric layer and a gate electrode, wherein said gate structure is arranged between said drain area and said source area; an emitter area of said first conductivity type, wherein said emitter area is operably associated with said drain area; and at least one bit line and at least one source line, wherein said source area is connected to said source line, and said emitter area is connected directly to said bit line through a bit line contact.