Patent ID: 7444475

Claim:
A semiconductor integrated circuit having a cache capability, comprising: a translation look side buffer (TLB) and a cache, wherein, said cache comprises a cache memory index (TAG) memory module and a cache data memory module, and said TAG memory module comprises an input section, wherein said TAG memory module is immediately adjacent said TLB, a part connected to said TAG memory module, said part comprising a line connected between said TLB and said input section of said TAG memory module, wherein said input section of said TAG memory module is located immediately adjacent said TLB, a bus area located between said cache and said TLB, wherein said cache data memory module comprises an output section, and an output signal line connected to said output section of said cache data memory module and passes through the bus area, an amplifier that is connected to said output signal line and is located substantially where said output signal line goes out of said bus area, and a power supply line and a grounding line located in a layer under or above said output signal line, wherein said power supply line and said grounding line intersect said output signal line.