Patent ID: 8873693

Claim:
A method comprising: generating, by a clock signal generator, a first clock signal at a first frequency and a first phase; generating, by a frequency detector, a frequency-correction signal based on a frequency difference between the first frequency and a reference clock frequency; adjusting, by the clock signal generator, the first clock signal based on the frequency-correction signal to substantially lock the first frequency to the reference clock frequency; generating, by a phase detector, a phase difference signal based on a phase difference between the first clock signal and an input data bit stream at an input data bit frequency and an input data bit phase; calculating, by a filter, an integrated phase difference signal based on the phase difference signal; and further adjusting, by the clock signal generator, the first clock signal based on the integrated phase difference signal and the frequency-correction signal to substantially lock the first frequency and the first phase to the input data bit frequency and the input data bit phase, wherein the frequency-correction signal and the integrated phase difference signal are combined to update the clock signal generator.