Patent ID: 7754559

Claim:
A method comprising: completing front-end processing of a semiconductor wafer, wherein the front-end processing includes formation of a pre-metal dielectric layer, but not the formation of contacts through the pre-metal dielectric layer; then forming a first set of grooves through the pre-metal dielectric layer; forming a gate dielectric layer over the pre-metal dielectric layer, wherein the gate dielectric layer extends into the first set of grooves; then forming a plurality of contact openings through the gate dielectric layer and the pre-metal dielectric layer; and then simultaneously forming stacked metal structures in the contact openings and the first set of grooves by: forming a barrier conductive composite layer in the contact openings and the first set of grooves, wherein the barrier conductive composite layer is formed directly on the gate dielectric layer within the first set of grooves; depositing a metal layer over the barrier conductive composite layer in the contact openings and the first set of grooves; and then performing a planarization process to remove portions of the barrier conductive composite layer and the metal layer not located in the contact openings or the first set of grooves.