Patent ID: 7575969

Claim:
A method of forming a CMOS structure, comprising the steps of: forming an isolation region in a semiconductor layer; forming a first mask having a first void therein on a first surface of said semiconductor layer; implanting first conductivity-type dopants into said semiconductor layer through said first void to form a first buried region, a portion of said first buried region extending underneath a portion of said isolation region; implanting second conductivity-type dopants into said semiconductor layer through said first void to form a first well between said first buried region and said first surface, a portion of said first well extending underneath a portion of said isolation region between said isolation region and said first buried region; forming a second mask having a second void therein on the first surface of said semiconductor layer; implanting second conductivity-type dopants into said semiconductor layer through said second void to form a second buried region, a portion of said second buried region extending underneath a portion of said isolation region; and implanting second conductivity-type dopants into said semiconductor layer through said second void to form a second well between said second buried region and said first surface, a portion of said second well extending underneath a portion of said isolation region between said isolation region and said second buried region.