Patent ID: 8407567

Claim:
A node unit of a reconfigurable error-correction decoder comprising a reconfigurable adder, wherein: the reconfigurable adder is adapted to receive a first set of bits and a second set of bits; the reconfigurable adder comprises: a first non-reconfigurable adder adapted to add (i) a first operand comprising a first subset of the first set of bits and (ii) a second operand comprising a first subset of the second set of bits to generate a first sum; logic circuitry adapted to receive (i) a mode control signal and (ii) a most significant bit of the first sum and generate an intermediate value; and a second non-reconfigurable adder adapted to add (i) a third operand comprising a second subset of the first set of bits, (ii) a fourth operand comprising a second subset of the second set of bits, and (iii) the intermediate value to generate a second sum; the reconfigurable adder is selectively configurable to operate in a first operating mode to add multi-bit values in a pair of multi-bit values, in which each multi-bit value has a first number of bits; and the reconfigurable adder is selectively configurable to operate in a second operating mode to add multi-bit values in a pair of multi-bit values, in which each multi-bit value has a second number of bits different from the first number of bits.