Patent ID: 8782451

Claim:
A multi-core processor comprising: a plurality of physical processing cores; and inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores; wherein: the inter-core state discover microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process; and wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance; each core has a target operating state; the processor includes a domain comprising at least two of the microprocessor's cores; the processor provides a resource to the domain, which resource is shared by the cores of the domain; the synchronization logic is configured to discover whether the domain is prepared to implement a restricted power-conserving operating state for the resource which would limit the power, speed, or efficiency with which the cores sharing the resource are able to operate; and wherein the domain is prepared to implement the restricted operating state if any only if each of the enabled cores in the domain sharing the resource has a target operating state at least as restrictive as the restricted operating state.