Patent ID: 7254741

Claim:
Apparatus comprising: a first device including a first reserved space; a second device including a second reserved space; a third device including a copy of the first reserved space; a fourth device including a copy of the second reserved space, each device having a unique address represented by a separate plurality of address bits; a first power branch for providing power to the first device and the second device; a second power branch for providing power to the third device and the fourth device; and logic for producing intermediate bits, the number of intermediate bits being fewer than the number of address bits, the intermediate bits being used to drive the address bits, some of the intermediate bits driving more than one address bit; wherein each device is a Fibre Channel Arbitrated Loop device having an arbitrated loop physical address as the unique address of that device; and wherein the apparatus further comprises: a programmable logic device coupled to the logic for producing the intermediate bits, the programmable logic device being configured to (i) receive a particular intermediate bit from the logic and (ii) generate multiple arbitrated loop physical address bits belonging to multiple arbitrated loop physical addresses in response to receipt of that particular intermediate bit, each of the multiple arbitrated loop physical address bits belonging to a different arbitrated loop physical address which uniquely corresponds to a particular Fibre Channel Arbitrated Loop device to provide consolidation of addressing in which the particular intermediate bit maps to the multiple arbitrated loop physical address bits.