Patent ID: 8634550

Claim:
Non-transitory computer-usable memory that stores an instruction to be decoded and executed by a processor, decoding and executing of the instruction by the processor resulting in performance of operations by the processor, the operations comprising: decoding a first parameter of the instruction that selects a programmable number of rounds of a non-standard Advanced Encryption Standard (AES) algorithm to be executed by the processor, the instruction permitting a selected value of the first parameter to be different from each of the following values: 10, 12, and 14 so as to permit execution of the instruction by the processor to result in the processor performing a particular number of non-standard AES algorithm rounds to produce a non-standard AES algorithm encryption/decryption result, the particular number of non-standard AES algorithm rounds being a non-standard number of AES algorithm rounds as defined by a standard AES algorithm, the first parameter to be stored, as a result of the decoding of the instruction by the processor, as a corresponding field value with other field values in a control register of the processor, the control register to be used in executing of the instruction by the processor; and the performing by the processor of the particular, non-standard number of AES algorithm rounds in accordance with the field values; wherein the processor comprises an execution unit that includes at least one key register to store at least one portion of at least one key prior to the execution unit performing an XOR operation involving the at least one portion, and when the programmable number of non-standard AES algorithm rounds is set to 1, the instruction, when executed by the processor, results in (1) bypassing storing of the at least one portion in the at least one key register, and (2) performance of a single non-standard AES algorithm round by the execution unit involving the at least one portion.