Patent ID: 8131951

Claim:
A data processing system comprising: a processor coupled to a system memory via a system interconnect; a cache coupled to the processor, the cache storing data and having a first data port and one or more control inputs for receiving control information; a first buffer circuit coupled to the cache for receiving one or more data words from the system interconnect, the first buffer circuit storing the one or more data words in each of one or more entries, the one or more data words of a first entry of the one or more entries to be written to the cache in response to error free receipt of the one or more data words from the system interconnect; a second buffer circuit coupled to the cache, the second buffer circuit having one or more entries for storing store requests, each entry having an associated control bit that determines whether an entry formed from a first store request is a valid entry to be written to the system memory from the second buffer circuit, wherein the first buffer circuit comprises a linefill buffer and the second buffer circuit comprises a store buffer for writethrough stores; control circuitry coupled to the cache and second buffer circuitry, the control circuitry providing an error determination whether error free receipt of the one or more data words occurred and selectively setting the associated control bit to a value that invalidates the entry in the second buffer circuit based upon the error determination; and a valid bit associated with a predetermined store request for establishing validity of the predetermined store request in the second buffer circuit separate from the associated control bit, the associated control bit invalidating the predetermined store request in the second buffer circuit if the error determination indicates that no error occurred in filling a correlated entry of the first buffer circuit.