Patent ID: 7075353

Claim:
A circuit for generating a clock signal comprising: a first current source providing an output current having constant or near constant temperature coefficient, the output current being mirrored to generate a set of bias currents; a voltage reference generator coupled to receive at least a first bias current from the first current source and generating first and second DC reference voltages, the difference between the first and second DC reference voltages being a PTAT (proportional to absolute temperature) reference voltage, the voltage reference generator further receiving first and second switching control signals and generating at least a first switching voltage reference signal in response; a second current source receiving a second bias current from the first current source and the first and second DC reference voltages from the voltage reference generator and providing a first output current being super-PTAT, the second current source further comprising a current mixing circuit for generating second and third output currents based on a ratioed combination of a fourth bias current from the first current source and the first output current, the second output current being larger than the third output current; a voltage ramp generator receiving the second and third output currents from the second current source and the first and second switching control signals, the voltage ramp generator comprising a capacitor being charged and discharged by the second and third output currents to generate a voltage ramp signal, wherein the voltage ramp signal has a period controlled by the first and second switching control signals; and a linear comparator receiving the first switching voltage reference signal and the voltage ramp signal as input signals, the linear comparator providing first and second switching output signals as the first and second switching control signals, wherein either one of the first and second switching output signals can be used as the clock signal.