Patent ID: 8372692

Claim:
A method of fabricating a semiconductor package, the method comprising: mounting a first chip onto a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip; bonding a wire from a first bump pad of the plurality of bump pads to the substrate; forming an intermediate layer on at least a portion of the active surface of the first chip; forming a via in the intermediate layer, wherein the via extends to a second bump pad of the plurality of bump pads; placing a second chip on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer; forming a corresponding bump on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, wherein the corresponding bump is formed on the second bump pad located on the active surface of the first chip, and wherein a height of the corresponding bump is greater than a height of the intermediate layer; and heating the corresponding bump formed on the one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip to melt the corresponding bump within the via and thereby form an electrical connection between the second bump pad and the third bump pad.