Patent ID: 7504857

Claim:
An integrated circuit, comprising: an embedded core, containing inputs and outputs, for processing digital signals; logic, operably connected to the embedded core; and a plurality of characterization cells, operably connected to the logic and the embedded core for allowing creation of timing transitions that are used for timing measurements of the inputs and outputs of the embedded core, wherein at least one characterization cell within the plurality of characterization cells comprises: a functional boundary flip-flop that is a first flip-flop sampling input from a clock domain having an input operatively connected to receive functional data and having an output that outputs the functional data; a capture flip-flop, having a data input operatively connected to the output of the functional boundary flip-flop, that captures a falling edge of a clock cycle; a shift flip-flop, having a data input operatively connected to the output of the capture flip-flop, and having a shift data input connected to a previous characterization cell in a shift register; a circuit element operatively connected to the capture flip-flop, that determines when the rising edge an internal multiplying clock is synchronized to a rising edge of an external clock; and a synchronizer, operatively connected to the internal clock, having output slip between the circuit element and another characterization cell in the plurality of characterization cells.