Patent ID: 8581225

Claim:
A method of manufacturing a variable resistance nonvolatile memory device, said method comprising: a step (A) of forming a plurality of lower layer copper lines on a substrate, each of the lower layer copper lines being shaped into a strip; a step (B) of forming a plurality of electrode seed layers each of which is shaped into the strip and disposed on a surface of a corresponding one of the lower layer copper lines, using electroless selective growth plating with which a metal thin film is precipitated not on an insulating body but only on the surfaces of the lower layer copper lines, each of the lower layer copper lines comprising a conductive material; a step (D 2 ) of forming an interlayer insulating layer above the electrode seed layers and the substrate; a step (E 2 ) of forming a plurality of memory cell holes in the interlayer insulating layer, each of the memory cell holes penetrating through the interlayer insulating layer and extending to a corresponding one of the electrode seed layers; a step (C 2 ) of forming a plurality of noble metal electrode layers each of which is disposed on an exposed surface of a corresponding one of the electrode seed layers in a corresponding one of the memory cell holes, using the electroless selective growth plating; a step (F) of forming a plurality of variable resistance layers each of which is connected to the noble metal electrode layer in a corresponding one of the memory cell holes; and a step (G) of forming, above the interlayer insulating layer and the variable resistance layers, a plurality of upper layer copper lines each of which is (i) connected to a corresponding one of the variable resistance layers and (ii) shaped into a strip that crosses the lower layer copper lines.