Patent ID: 7567228

Claim:
A method of driving a liquid crystal display (LCD), comprising the steps of: (a) providing an LCD panel comprising: (i) a common electrode; (ii) a plurality of scanning lines, {G n }, n=1, 2, . . . , N, N being an integer greater than zero, spatially arranged along a row direction; (iii) a plurality of data lines, {D m }, m=1, 2, . . . , M, M being an integer greater than zero, spatially arranged crossing the plurality of scanning lines {G n } along a column direction perpendicular to the row direction; and (iv) a plurality of pixels, {P n,m }, spatially arranged in the form of a matrix, each pixel P n,m defined between two neighboring scanning lines G n and G n+1 and two neighboring data lines D m , and D m+1 , and comprising at least a first sub-pixel, P n,m ( 1 ), and a second sub-pixel, P n,m ( 2 ), wherein each of the first sub-pixel and the second sub-pixel comprises a sub-pixel electrode, a liquid crystal (LC) capacitor electrically coupled between the sub-pixel electrode and the common electrode in parallel, and a transistor having a gate, a source and a drain electrically coupled to the sub-pixel electrode, wherein the gate and the source of the transistor of the first sub-pixel P n,m ( 1 ) of the pixel P n,m are electrically coupled to the scanning line G n+1 and the data line D m , respectively, and wherein the gate and the source of the transistor of the second sub-pixel P n,m ( 2 ) of the pixel P n,m are electrically coupled to the scanning line G n and the sub-pixel electrode of the first sub-pixel P n+1,m ( 1 ), respectively; and wherein the gate and the source of the transistor of the first sub-pixel P n−1,m m( 1 ) of the pixel P n−1,m are electrically coupled to the scanning line G n+1 and the sub-pixel electrode of the second sub-pixel P n+1,m ( 2 ), respectively, and wherein the gate and the source of the transistor of the second sub-pixel P n+1,m ( 2 ) of the pixel P n+1,m are electrically coupled to the scanning line G n−2 and the data line D m−1 , respectively; and (b) applying a plurality of scanning signals to the plurality of scanning lines {G n } and a plurality of data signals to the plurality of data lines {D m }, respectively, wherein the plurality of scanning signals is configured to turn on the transistors connected to the plurality of scanning lines {G n } in a predefined sequence, and the plurality of data signals is configured such that any two neighboring data signals have inverted polarities.