Patent ID: 8656397

Claim:
A computer-implemented method, comprising: creating, by a memory manager of a computing device, a page table (PT) hierarchy associated with a group of threads executing on a first processing device of the computing device, wherein the PT hierarchy comprises identifying information used to identify a plurality of memory pages accessible by the group of threads and access bit information associated with the plurality of memory pages, wherein the identifying information further identifies each of the plurality of memory pages as either local or remote to the first processing device, and wherein the access bit information comprises a plurality of access bits, with each of the plurality of memory pages identified in the PT hierarchy associated with a respective access bit; setting, by a memory management unit (MMU) of the first processing device, the respective access bit of one or more memory pages accessed by the group of threads while executing on the first processing device; collecting, by a scheduler executing on the computing device, access bit information in order to identify the one or more memory pages accessed by the group of threads; determining, by the scheduler, memory access statistics for the group of threads, wherein the memory access statistics indicates an average frequency in which the group of threads accessed the one or more memory pages identified as remote to the computing device; and dynamically migrating the group of threads to a second processing device, based on a determination by the scheduler that the average frequency in which the group of threads accessed the one or more memory pages identified as remote to the computing device exceeded a high threshold.