Patent ID: 6904507

Claim:
An architecture for the allocation and deallocation of buffer memory associated with a variable number of one or more Virtual Lanes (VL's) in a subnetwork, wherein said buffer memory is allocated and deallocated using blocks of one or more credits while said buffer memory is stored in increments of a word, and the one or more credits are allocated and deallocated using a variable length packet size, further comprising: a linked list, operable to track the allocation and deallocation of the buffer memory among the one or more VL's; a first table, operable to store one or more words associated with the buffer memory; a second table, operable to store the linked list, said second table comprising: one or more pointer addresses, each pointer address corresponding to one credit of the buffer memory and a tag address; one or more pointer data words, each pointer data word of the one or more pointer data words containing the address of the next pointer word in the linked list; a third table, operable to store one or more tag words, each tag word of the one or more tag words corresponding to one credit in the buffer memory and each tag word of the one or more tag words further comprising one or more of: one or more tag addresses corresponding to a pointer address and the one credit of buffer memory; a field indicating the packet is good or bad; a field containing the VL identifier associated with the packet; a field containing the number of grants associated with the packet; a field containing the packet start address; a field corresponding to the packet length; and a field that distinguishes a continuation tag from a start tag.