Patent ID: 8484840

Claim:
A computer-implemented leading wiring method comprising: determining, based on wiring board information, whether each of surface-mounted components located on a surface of a multilayer printed wiring board has a predetermined shape; for the surface-mounted components that are determined as having the predetermined shape, identifying a position of each via formed on the multilayer printed wiring board and a position of a footprint of each chip component located on a back surface of the board, and then determining whether each chip component and each surface-mounted component of the predetermined shape can be connected using chip on hole; and for the surface-mounted components and chip components that are determined as ones that can be connected using chip on hole, carrying out leading wiring from the vias, formed leading to the footprint, to terminals of the surface-mounted components so that the terminals of the surface-mounted components and the chip components are connected using chip on hole.