Patent ID: 8766203

Claim:
A solid state imaging device comprising: a photodetecting section including M×N pixel portions P 1,1 to P M,N two-dimensionally arrayed in M rows and N columns, each including a photodiode which generates charges as much as incident light intensity and a switch connected to the photodiode, where the photodiode is connected to a readout wiring L O,n via the switch in each pixel portion P m,n ; a scintillator layer which is provided so as to cover the photodetecting section and generates scintillation light in response to incidence of radiation; a dummy photodetecting section including dummy photodiodes disposed so as to neighbor the outer sides of the first row and the M-th row of the photodetecting section; a signal readout section which is provided on the outer side of the first row or the M-th row of the photodetecting section, includes N integrating circuits S 1 to S N and N holding circuits H 1 to H N , accumulates charges input into each integrating circuit S n through the readout wiring L O,n in a capacitive element and outputs a voltage value corresponding to the accumulated charge amount, and holds the voltage value output from the integrating circuit S n in each holding circuit H n and outputs the voltage value; and a bias voltage supply wiring connected to the dummy photodiodes, wherein the bias voltage supply wiring discharges the junction capacitance portion of the dummy photodiodes by applying a fixed voltage to the dummy photodiodes, where M and N are integers not less than 2, M<N, m is an integer not less than 1 and not more than M, and n is an integer not less than 1 and not more than N, wherein the photodetecting section, the dummy photodetecting section, and the signal readout section are formed on a same semiconductor substrate, and wherein a peripheral region other than the photodetecting section of the semiconductor substrate is larger than an area formed by the photodetection section.