Patent ID: 7613038

Claim:
A semiconductor integrated circuit device comprising: a memory cell array having a plurality of word lines, a plurality of bit lines across the plurality of word lines, and a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit lines, each of the plurality of memory cells having a phase-change resistance; a word driver coupled to the plurality of word lines; and a column selector having a plurality of sense amplifiers coupled to the plurality of bit lines, wherein, when the semiconductor integrated circuit device receives a first command with a first address, the word driver selects one of the plurality of word lines according to the first address, and the plurality of sense amplifiers amplifies first data read out from the plurality of memory cells by selecting one of the plurality of word lines and holds the first data therein, wherein, when the semiconductor integrated circuit device receives a second command, which indicates a write operation, with a second address and second data next to the first command, the column selector selects a part of the plurality of sense amplifiers according to the second address and inputs the second data to the part of the plurality of sense amplifiers to change a part of first data to the second data, wherein, when the semiconductor integrated circuit device receives a third command, which indicates a read operation, with a third address next to the first command, the column selector selects a part of the plurality of sense amplifiers according to the third address and outputs a part of first data held in the selected sense amplifiers.