Patent ID: 7321525

Claim:
A semiconductor integrated circuit device comprising: an interface circuit; a data processor; and a clock generator, wherein the clock generator generates an internal clock and an external clock, wherein the interface circuit includes: a first output circuit which supplies the external clock to an external device; a first input circuit which inputs a data strobe signal formed corresponding to the external clock at the external device; a second input circuit which inputs data formed in sync with the timing of a change in the data strobe signal at the external device; a dummy input/output circuit in which signal delay times are respectively equally set to any of the first output circuit and the first and second input circuits; a pulse control circuit which supplies a test clock to the dummy input/output circuit; a first delay time determination circuit which determines a signal delay time in response to the test clock sent through the dummy input/output circuit; a second delay time determination circuit which determines an arriving delay time relative to the internal clock in a predetermined determination region in response to the data strobe signal inputted via the first input circuit; a sampling circuit which samples the data inputted via the second input circuit in accordance with a timing signal obtained by 90° shifting the phase of the data strobe signal inputted through the first input circuit; and a synchronization circuit which synchronizes the sampled data with the internal clock on the basis of the result of determination by the second delay time determination circuit, and wherein the determination region of the second delay time determination circuit is changed in time based on the result of determination by the first delay time determination circuit.