Patent ID: 7580493

Claim:
A digital electronic circuit comprising: a timing element for generating a clock signal for the circuit; and a controller for synchronizing the clock signal with a received digital stream in response to an identification of a transition in the digital data stream, wherein: the clock signal is synchronized with the received digital stream for both situations where the timing element operates at a frequency greater than twice a data rate of the received digital stream and where the timing element operates a frequency less than the twice a data rate of the received digital stream; and the timing element comprises first and second current mirrors arranged in association with one another in order to effect generation of the clock signal; and first and second capacitors respectively connected to first and second current mirrors, wherein a current mirror is adapted to provide a respective capacitor with a substantially constant current in order that the capacitor charges to a threshold voltage value, the circuit further comprising a suitable switch arrangement adapted to effect discharge of the capacitor charged to its respective threshold voltage value, and charging of the other capacitor; and a first switch and a second switch, the first and second switches arranged in association with the timing element and operable to effect a change of state of the timing element in response to a control signal.