Patent ID: 7868862

Claim:
A liquid crystal display, comprising: a liquid crystal display panel including a plurality of first pixels and a plurality of second pixels, wherein each of the first pixels have Red, Green anc Blue (RGB) sub-pixels provided with RGB color filters, respectively, and each of the second pixels have Cyan, Magenta and Yellow (CMY) sub-pixels provided with CMY color filters, respectively, for displaying color and wherein the first pixels and the second pixels are alternatively arranged along a horizontal direction and are alternatively arranged along a vertical direction; a video processing part generating CMY data using input RGB data and outputting RGB data or CMY data; a timing controller controlling a supply of RGB data or CMY data inputted from the video processing part; and a data driving part converting RGB data or CMY data outputted from the timing controller into an analog data in accordance with the timing controller, and supplying it to the plurality of first pixels or the plurality of second pixels, wherein the video processing part includes: a data processor generating CMY data using input RGB data and outputting RGB data and CMY data; a data supply controller supplying a supply control signal in accordance with a clock signal, if the data supply controller recognizes a start of a frame by a vertical synchronization signal inputted and an input of the RGB and CMY data by a data enable signal inputted; and a data selector selecting RGB data or CMY data inputted from the data processor in accordance with the supply control signal inputted from the data supply controller to output it to the timing controller, wherein the data selector includes: a first multiplexer selecting a R data or a C data inputted from the data processor in accordance with the supply control signal to output it to the timing controller; a second multiplexer selecting a G data or a M data inputted from the data processor in accordance with the supply control signal to output it to the timing controller; and a third multiplexer selecting a B data or a Y data inputted from the data processor in accordance with the supply control signal to output it to the timing controller, wherein the data supply controller recognizes that one frame for displaying at the liquid crystal display panel is started if a vertical synchronization signal Vsych is inputted, and the data supply controller recognizes that RGB video data and CMY video data are inputted to the first to third multiplexers if a high-level data enable signal is inputted, wherein if a low-level supply control signal is inputted from the data supply controller, the first, second and third multiplexers select and output RGB data, respectively, and wherein if a high-level supply control signal is inputted from the data supply controller, the first, second and third multiplexers select and output CMY data, respectively.