Patent ID: RE44051

Claim:
A data bus line control circuit, comprising: a two pairs of global data bus line which is lines arranged between adjacent memory units adjacent to each other as two pairs, and transmits a transmitting data from a plurality of local data bus line lines positioned between adjacent sub blocks; and transmission means which is connected between the local data bus line lines and the global data bus line, and transmits lines transmitting in a first mode of operation bit line signals of two sub blocks, amplified by a plurality of bit line sense-amp sense-amps , to one pair both pairs of global data bus lines different from each other through the local data bus line lines , when the two sub blocks are simultaneously selected by a block isolation selection signal signal, and transmitting in a second mode of operation bit line signals of one sub block, amplified by a plurality of bit line sense-amps, to at least one pair of the global data bus lines through local data bus lines, when the one sub block is selected by the block isolation selection signal .