Patent ID: 7835184

Claim:
A memory device, comprising: a substrate doped with a first-type dopant; a plurality of electrically-conductive bit lines extending along a bit line direction; a plurality of electrically-conductive word lines extending along a word line direction; a plurality of electrically-conductive control gate lines extending along said word line direction; and a plurality of memory cells arranged respectively along said bit lines and said word lines, wherein each memory cell comprises: a program/erase transistor including a first gate, and first and second terminals formed within a well doped with a second-type dopant, wherein the well is formed within said substrate, and further wherein said first terminal of the program/erase transistor is electrically connected to a corresponding bit line; an access transistor including a second gate, and third and fourth terminals formed within said well, wherein said third terminal is electrically connected to said second terminal of said program/erase transistor, and further wherein said second gate is electrically connected to a corresponding word line; and a control gate transistor formed in an isolated first-type dopant region which, in turn, is formed within said well, wherein said control gate transistor comprises a third gate, and fifth and sixth terminals formed within said isolated first-type dopant region, wherein said fifth and sixth terminals are electrically connected to a corresponding control gate line, and further wherein said third gate is electrically connected to said first gate of said program/erase transistor to form a floating gate.