Patent ID: 7184360

Claim:
A high-speed interface circuit implemented in a semi-conductor memory chip including a memory core, the high-speed interface circuit comprising: a first interface circuit section connectable to a write data-/command and address bus and including: a serial input terminal to receive a serial stream of write data-/command and address signals from a serial output terminal of a corresponding first interface circuit section of a preceding same memory chip or from a serial output terminal of a memory controller, the serial input terminal further being connected to: a write data-/command and address re-driver/-transmitter path arranged to re-drive the serial stream of write data-/command and address signals to a serial output terminal of the write data-/command and address re-driver/-transmitter path and connectable to a serial input terminal of a corresponding first interface circuit of a next same memory chip; and a main write signal path arranged between the serial input terminal and a parallel output terminal and including serial-to-parallel conversion and synchronization means for serial-to-parallel converting and synchronizing with a reference clock signal the write data-/command and address signals received at the serial input terminal and delivering the serial-to-parallel converted and synchronized write data-/command and address signals to the parallel output terminal of the first interface circuit section and from the parallel output terminal of the first interface circuit to the memory core; and a second interface circuit section connectable to a read data bus and including: a parallel read data input terminal connected to the memory core to receive parallel read data from the memory core; a serial read data input terminal connected to receive a serial read data stream from a serial read data output terminal of a corresponding second interface circuit section of a preceding same memory chip and arranged to re-drive the received serial read data stream through a read data re-driver/receiver path to a serial read data output terminal of the second interface circuit section; and a main read signal path connected between the parallel read data input terminal and the serial read data output terminal of the second interface circuit section and having means for inserting the parallel-to-serial converted read data read from the memory core and received at a parallel input terminal of the main read signal path into the serial read data stream from the serial read data input terminal, synchronizing the serial read data stream with a reference clock signal and providing the serialized read data stream to the serial read data output terminal connectable with the read data bus to a serial read data input terminal of a corresponding second interface circuit section of a next same memory chip or to a serial read data input terminal of the memory controller; wherein the first and second interface circuit sections further include a reference clock receiving terminal to receive the reference clock signal.