Patent ID: 8741757

Claim:
A method of forming a semiconductor structure, said method comprising: forming a first gate cavity and a second gate cavity above a semiconductor portion, wherein each of said first gate cavity and said second gate cavity is laterally surrounded by a planarization dielectric layer, wherein a top surface of said semiconductor portion is exposed at a bottom of each of said first and second gate cavities; forming a gate dielectric layer within said first and second gate cavities; forming a component conductive metallic nitride layer on said gate dielectric layer; removing said component conductive metallic nitride layer from above a second portion of said gate dielectric layer within said second gate cavity, while said component conductive metallic nitride layer is not removed from above a first portion of said gate dielectric layer within said first gate cavity; forming another component conductive metallic nitride layer on said second portion of said gate dielectric layer and on a portion of said component conductive metallic nitride layer in contact with said first portion of said gate dielectric layer; filling said first gate cavity and said second gate cavity with a conductive material, wherein a first conductive material portion is formed within said first gate cavity and a second conductive material portion is formed within said second gate cavity; forming a third gate cavity above said semiconductor portion, wherein said gate dielectric layer is formed within said third gate cavity, and said component conductive metallic nitride layer is subsequently formed within said third gate cavity; removing said component conductive metallic nitride layer from within said third gate cavity; forming yet another component conductive metallic nitride layer in said first, second and third gate cavities; removing said yet another component layer from within said second cavity, while said yet another component layer is not removed from within said first and third gate cavities, wherein said another component layer is deposited in said first, second, and third gate cavities.