Patent ID: 7642635

Claim:
A stacked semiconductor package comprising two semiconductor chips each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern, and a substrate having upper and lower surfaces on which the two semiconductor chips are mounted so that the mounting surfaces are faced to each other with the substrate interposed therebetween, wherein the substrate has a plurality of package pins corresponding to the chip pins, respectively, said plurality of package pins being formed in an area which is different from a chip mounting area where either of the semiconductor chips is mounted and which becomes another lower surface when the substrate is folded in two to wrap the semiconductor chip mounted on the lower surface, wherein at least one of the package pins is an option pin connected to a corresponding chip pin of either one of the semiconductor chips and at least one of the package pins is a regular pin connected to a corresponding chip pin of each of the semiconductor chips, wherein the substrate has a common wire having one end connected to the regular pin and a branch wire portion connecting the other end of the common wire to two chip pins as the corresponding chip pins of the semiconductor chips; and wherein the branch wire portion includes a front layer side signal layer and a back layer side signal layer which are connected to the corresponding chip pins at points where wiring length from the one end of the common wire to one of the corresponding chip pins is substantially equal to that from the one end of the common wire to the other end of the corresponding chip pins.