Patent ID: 7170160

Claim:
A chip structure, comprising: a chip having a wire bonding area adjacent to one side or two sides adjacent to each other of the chip, wherein the chip comprises a plurality of first bonding pads disposed inside the wire bonding area and a plurality of second bonding pads disposed outside the wire bonding area; a first passivation layer disposed on the chip, wherein the first passivation layer has a plurality of first openings by which the first bonding pads and the second bonding pads are exposed; a redistribution layer disposed on the first passivation layer, wherein the redistribution layer extends from the second bonding pads to the wire bonding area, and the redistribution layer has a plurality of third bonding pads located inside the wire bonding area; and a second passivation layer disposed over the redistribution layer, wherein the second passivation layer has a plurality of second openings by which the first bonding pads and the third bonding pads are exposed.