Patent ID: 7706194

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in rows and columns for holding information, each of the memory cells having a control gate; a plurality of word lines extending in a row direction, each of the word lines being connected to the control gates of the memory cells of a corresponding row of the memory cell array; a plurality of bit lines extending in a column direction and connected to sources or drains of the memory cells; a charge pump circuit for generating a voltage higher than a supply voltage; a row decoder for receiving a first output voltage of the charge pump circuit, selecting any of the plurality of word lines, and supplying the first output voltage to the selected word lines; a column decoder for selecting any of the plurality of bit lines; a writing circuit supplied with a second output voltage of the charge pump circuit and configured to output a writing potential to one of the plurality of bit lines selected by the column decoder according to input data which is to be written; a first switch located in a connection path between the row decoder and the charge pump circuit; and a control circuit for controlling an operation timing of the writing circuit and the first switch.