Patent ID: 6995589

Claim:
A frequency divider for dividing a frequency of a clock signal by a divisor, the divisor being an odd number, the frequency divider comprising: a flip-flop chain having a plurality of flip-flops for latching signals, an amount of flip-flops being equal to the divisor, each flip-flop having a data input node, a clock input node, a first output node, and a second output node for outputting a logic signal complementary to a logic signal outputted at the first output node, the first output node of each but the last flip-flop being electrically connected to the data input node of the next flip-flop, the second output node of the last flip-flop being electrically connected to the data input node of the first flip-flop; an XOR gate having two input nodes and an output node, one input node of the XOR gate being electrically connected to the clock signal, the other input node of the XOR gate being electrically connected to the second output node of the last flip-flop, the output node of the XOR gate being electrically connected to the clock input nodes of the odd flip-flops in the flip-flop chain; and an inverter having an input node and an output node for inverting a signal inputted at the input node of the inverter, the input node of the inverter being electrically connected to the output node of the XOR gate, the output node of the inverter being electrically connected to the clock input nodes of the even flip-flops in the flip-flop chain; whereby a frequency of a signal outputted at the first output node of the last flip-flop is equal to the frequency of the clock signal divided by the divisor.