Patent ID: 6900812

Claim:
A logic enhanced memory circuit, comprising: a receiving block that receives commands, wherein at least a portion of the commands correspond to graphics processing operations, wherein the commands include row and column commands, wherein each of the commands includes a control portion, wherein at least a portion of the column commands include a corresponding input data packet; an input buffer operably coupled to the receiving block, wherein the input buffer buffers input data packets of column commands that are pending execution; a control block operably coupled to the receiving block, wherein for each command, the control block executes the control portions of the command to generate control information corresponding to the command; a memory that stores graphics data, wherein for each command that is executed, the memory receives a first portion of the control information corresponding to the command, wherein for each column command that is executed, the memory outputs a stored data packet stored in a selected location in response to the first portion of the control information, and wherein for each row command that is executed, the memory receives row selection information such that the memory prepares a row corresponding to the row selection information for subsequent access based on subsequently executed column commands; an output buffer that stores output data packets; and an operation pipeline operably coupled to the control block, the input buffer and the memory, wherein for each column command that is executed, the operation pipeline: receives a second portion of the control information corresponding to the column command from the control block; receives the input data packet corresponding to the column command from the input buffer when the column command includes a corresponding input data packet; receives the stored data packet corresponding to the column command from the memory; performs an operation selected from a predetermined set of operations based on the second portion of the control information; and stores a result packet for the operation in at least one of the memory and the output buffer.