Patent ID: 7081387

Claim:
A method of forming a damascene gate field effect transistor (FET) structure comprising the steps of: providing a planar structure comprising a pad stack located atop a Si-containing semiconductor layer; removing portions of the pad stack to define at least one device aperture in said structure; forming at least one mesa region comprising a portion of said Si-containing semiconductor layer in said at least one device aperture, said at least one mesa region having sidewall portions; forming a dielectric material having an opening that exposes a portion of said at least one mesa region; forming a first gate region including a channel region, gate dielectric and gate conductor in said opening, said channel region being formed into said at least one mesa region, while said gate dielectric and gate dielectric being formed on said at least one mesa region; removing said dielectric material about said gate region and forming spacers on exposed vertical sidewalls of said gate conductor; and forming source and drain regions in said sidewall portions of said at least one mesa region, wherein solid source and drain regions are formed by a gas phase doping process, a plasma doping process, angled ion implantation, or a combination thereof.