Patent ID: 7791109

Claim:
A static random access memory (SRAM) structure comprising six transistors and a set of six gate conductor lines, wherein said six transistors include: a first pair of a first pass gate NFET and a first pull-down NFET, said first pair having a first active area containing a first source/drain of said first pass gate NFET and a first drain of said first pull-down NFET; a second pair of a second pass gate NFET and a second pull-down NFET, said second pair having a second active area containing a second source/drain of said second pass gate NFET and a second drain of said second pull-down NFET; a first pull-up PFET containing a third active area, wherein said third active area is electrically connected to said first active area through a first gate conductor line and a first gate conductor sidewall silicide alloy, wherein said first gate conductor sidewall silicide alloy is located directly on said first gate conductor line and adjoined to a first active area silicide alloy located directly on said first active area; a second pull-up PFET containing a fourth active area, wherein said fourth active area is electrically connected to said second active area through a second gate conductor line and a second gate conductor sidewall silicide alloy, wherein said second gate conductor sidewall silicide alloy is located directly on said second gate conductor line and adjoined to a second active area silicide alloy located directly on said second active area, wherein said four active areas comprise a semiconductor material and said set of six gate conductor lines are arranged as three groups of parallel gate conductor lines located over said four active areas, wherein each group is laterally spaced from, and is parallel to, the other two groups, and each of said six gate conductor lines comprise a semiconductor material, and said three groups of parallel gate conductor lines include: a first group including said first gate conductor line and said second gate conductor line, wherein said first and second gate conductor lines are located along a first line.