Patent ID: 7320913

Claim:
A method for fabricating a split-gate memory cell array, comprising: forming a floating gate electrode on a semiconductor substrate; forming a first conformal dielectric layer on the floating gate electrode and semiconductor substrate; forming a first diffusion region in the semiconductor substrate adjacent a first side of the floating gate electrode, wherein the first diffusion region is formed such that a first side of the floating gate electrode overlaps the first diffusion region; removing a portion of the first conformal dielectric layer that is disposed on the first side of the floating gate electrode and the first diffusion region; forming a second conformal dielectric layer on the floating gate electrode and semiconductor substrate; forming a conformal conductive layer over the second conformal dielectric layer on the semiconductor substrate; and patterning the conformal conductive layer to form a coupling gate electrode on the first side of the floating gate electrode and to form a control gate electrode on a second side of the floating gate electrode; and forming a second diffusion region in the semiconductor substrate adjacent the control gate electrode.