Patent ID: 7602007

Claim:
A method comprising: using an element isolation structure, defining both a first element active region and a second element active region in a semiconductor substrate; forming a transistor in the first element active region, the transistor including a first electrode; forming a first conductive region in the second element active region, the first conductive region forming a control gate of a non-volatile memory; forming a second electrode above at least a portion of the first conductive region, separated from the first conductive region by a dielectric; electrically connecting the first electrode and the second electrode to form a floating gate of the non-volatile memory; and connecting a third electrode to a second conductive region in the semiconductor substrate, wherein the second conductive region abuts a third conductive region that is part of the transistor, and wherein the third electrode is configured so that when a voltage is applied to the third electrode, an electric potential is generated in the first element active region to control the threshold voltage of the transistor.