Patent ID: 7609326

Claim:
An image scaler comprising a horizontal downscaler, a horizontal upscaler, a vertical scaling unit, a first buffer area, and a synchronization unit, wherein the horizontal downscaler is configured in front of the vertical scaling unit and the horizontal upscaler is configured in back of the vertical scaling unit, wherein a selective control method is used to control an image input route depending on horizontal downscaling or upscaling requirements, so as to choose to go through or to bypass the horizontal downscaler or the horizontal upscaler to horizontally and vertically resize an image; the horizontal downscaler comprises an input terminal coupled to an image input terminal, wherein an input clock frequency is used as a base signal for image processing; the first buffer area comprises a plurality of first line buffers connected in series, wherein an input terminal of the first line buffer is coupled to the horizontal downscaler or the image input terminal; the vertical scaling unit is coupled to the horizontal downscaler or the image input terminal, wherein the input clock frequency is used as the base signal of the vertical scaling signal for image processing; the synchronization unit comprises an input terminal coupled to an output terminal of the vertical scaling unit to synchronize sorting the upscaled image data and then to output a vertical signal, wherein the output data of the vertical scaling unit that the synchronization unit receives uses the input clock frequency as the base signal, and an output clock frequency is used as a base signal for processing an synchronization sorting operation; and the horizontal upscaler is coupled to an output terminal of the synchronization unit to perform an interpolation on a horizontal signal of input image data to upscale the image data, wherein the horizontal upscaler takes the output clock frequency as the base signal.