Patent ID: 7991606

Claim:
A method comprising: receiving instructions for entering a hardware design including one or more embedded logic analyzers in a system level interface, the instructions specifying one or more embedded logic analyzer nodes in the hardware design where the one or more embedded logic analyzers are provided to capture signals, wherein the system level interface is integrated with an electronic design automation (EDA) system configured to design programmable chips and compile designs for the programmable chips; receiving at the system level interface parameter information for parameterizing the one or more embedded logic analyzers, wherein the parameter information is used to select particular capture bits with a mask block specifying the most significant bit and the least significant bit bounding the selected particular capture bits; receiving a command entered in the system level interface for converting the hardware design, with the one or more embedded logic analyzers, to a Hardware Design Language (HDL) representation of the hardware design, including the one or more embedded logic analyzers; converting the hardware design specifying the one or more embedded logic analyzers to the HDL representation, wherein the HDL representation is compiled by the EDA system to create a compiled hardware design, the compiled hardware design including compiled instructions for implementing the one or more embedded logic analyzers.