Patent ID: 8508041

Claim:
A three-dimensional integrated circuit, comprising: a first integrated circuit, comprising: a first substrate; a first film layer, formed on the first substrate, having a first pattern structure formed thereon; and a first metal co-deposition layer disposed on the first film layer, having a first metal and a second metal deposited therewithin; and a second integrated circuit, comprising: a second substrate; a second film layer, formed on the second substrate, having a second pattern structure formed thereon; and a second metal co-deposition layer disposed on the second film layer, having the first metal and the second metal deposited therewithin; wherein the second integrated circuit is superimposed onto the first integrated circuit at a predetermined temperature, such that the first metal co-deposition layer and the second metal co-deposition layer are bonded with each other, and at least a portion of atoms of the first metal diffuse toward a bonding interface between the first metal co-deposition layer and the second metal co-deposition layer, and at least a portion of atoms of the second metal diffuse toward the respective film layers of each of the integrated circuits to form adhesion and barrier layers for the first metal.