Patent ID: 7978509

Claim:
A memory device, comprising: first and second access devices and a memory element sharing a common current flow terminal, the first and the second access devices and the memory element each having an additional current flow terminal; a bit line electrically coupled to the additional current flow terminal of the memory element; a first conductive line electrically coupled to the additional current flow terminal of the first access device; a second conductive line electrically coupled to the additional current flow terminal of the second access device; a control circuit causing a first current path through the bit line, the memory element, and both the first access device and the second access device for a reset operation; and the control circuit causing a second current path through the bit line, the memory element, and either: (i) for both a set operation and a read operation, the first access device but not the second access device, or (ii) for both the set operation and the read operation, the second access device but not the first access device.