Patent ID: 7000092

Claim:
An apparatus for providing a reference design for an integrated circuit, comprising: at least two processors; a MultiCore Communication Module (MCCM), the MCCM providing a facility for the at least two processors to communicate with each other; a common memory controller communicatively coupled to the at least two processors, the common memory controller providing a shared memory resource to the at least two processors; and a bus interconnect communicatively coupling the at least two processors, MCCM, common memory controller and bus interconnect, wherein the MCCM has at least two of the following features: (a) a configurable memory size; (b) a memory to allow communication and event signaling between the at least two processors; (c) multiported to enable expansion beyond the at least two processors; (d) asynchronous interface so as to allow AHB buses to have different frequencies; and (e) endianess selection.