Patent ID: 8443227

Claim:
A processor configured to perform: enabling as a workaround trigger, a data dependent execution state of an instruction to be executed, the instruction comprising an opcode; associating the workaround trigger with an opcode compare result; initiating execution of the instruction within a microarchitecture of the processor, the execution comprising: determining, within the microarchitecture, whether an event matching the workaround trigger is encountered by the execution of the instruction, the determining based on one of: data input characteristics, data output characteristics, and floating point controls; setting a pseudo exception based on determining that the event matching the workaround trigger is encountered, the pseudo exception set based on a plurality of pseudo exception codes available to modify behavior of the processor based on the pseudo exception that is set; performing a predetermined work-around action to finish execution of the instruction based on the pseudo exception that is set from the plurality of pseudo exception codes, the opcode of the instruction, and data associated with the instruction; and finishing execution of the instruction without performing the predetermined work-around action based on the executing instruction not setting the pseudo exception.