Patent ID: 8427209

Claim:
A circuit, comprising: a sampling phase locked loop (PLL) circuit configured to generate a PLL output clock phase locked to a reference clock, wherein the sampling PLL circuit includes a sampling phase detector circuit that is coupled to receive the PLL output clock, and that is responsive to a sampling control signal to generate a PLL control signal used to phase lock the PLL output clock to the reference clock; and a buffer circuit that is configured to receive the reference clock, and that is configured to generate the sampling control signal with a substantially square wave duty cycle defined by a sampling edge and a signal edge which establish a sampling duration, the buffer circuit including: a first transistor of a first type and a second transistor of a second type coupled in series in a pull-up pull-down arrangement with a buffer output node between the transistors, the transistors characterized by respective threshold voltages; and a pulser circuit receiving the reference clock and configured to generate a switch control pulse characterized by a switch-on edge and a pulse width; wherein the first transistor is configured to receive at its control input the reference clock, and the second transistor receiving at its control input the switch control pulse; and wherein the pulser circuit is configured to introduce a controlled delay in the switch-on edge of the switch control pulse relative to the reference clock cycling through the threshold voltage of the second transistor, and to control the pulse width of the switch control pulse; and wherein the buffer circuit is configured such that: the first transistor switches on in response to the reference clock cycling through its threshold voltage, thereby transitioning the buffer output node to generate the sampling edge of the sampling control signal; the second transistor switches on in response to the switch-on edge of the switch control pulse, thereby transitioning the buffer output node to generate the signal edge of the sampling control signal; and the switch-on edge and pulse width of the switch control pulse are controlled such that the first and second transistors are not on at the same time.