Patent ID: 8304907

Claim:
An integrated circuit chip, comprising: a silicon substrate; multiple MOS devices in and on said silicon substrate; a first metallization structure over said silicon substrate, a passivation layer over said first metallization structure, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said first metallization structure; and said second contact point is at a bottom of said second opening; and a second metallization structure on said passivation layer and said first and second contact points, wherein there is no polymer layer between said second metallization structure and said passivation layer, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a width greater than 2 micrometers, wherein said second metallization structure comprises a titanium-containing layer having a thickness between 0.01 and 3 micrometers, a first copper layer having a thickness between 0.05 and 3 nicrometers on said titanium-containing layer, and a second copper layer having a thickness between 2 and 100 micrometers on said first copper layer, wherein an undercut with an edge of said titanium-containing layer from an edge of said first copper layer is between 0.03 and 2 micrometers.