Patent ID: 8008946

Claim:
A semiconductor integrated circuit, comprising: a plurality of circuit units arranged therein; a first counter configured to detect a rising edge of a clock signal and generate a first signal having a multiplied cycle of the clock signal; a second counter configured to detect a falling edge of the clock signal and generate a second signal having a multiplied cycle of the clock signal; a first line for transferring the first signal; a second line for transferring the second signal; and a phase comparator connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units, the phase comparator being disposed on the first line and the second line, and plurality of the phase comparators being disposed between ends of the first line and the second line and the circuit units, wherein the wiring time constant of the first line and the wiring time constant of the second line are less than half of the cycles of the first signal and the second signal transferred on the first line and the second line.