Patent ID: 7816261

Claim:
A method for forming a semiconductor device, comprising: forming at least one isolation region in a semiconductor substrate, wherein a semiconductor material portion comprising a single-crystalline semiconductor material and having a planar top surface throughout is provided between a first isolation region portion of said at least one isolation region and a second isolation region portion of said at least one isolation region, wherein said single-crystalline semiconductor material is exposed at said planar top surface and has a same composition between said first and second isolation region portions; forming a gate dielectric layer and a gate conductor on a portion of said planar top surface, wherein a first planar top surface portion of said planar top surface is exposed between said gate dielectric layer and said first isolation region portion, and a second planar top surface portion of said planar top surface is exposed between said gate dielectric layer and said second isolation region portion; crystallographically etching said semiconductor material portion at said first and second planar top surface portions to form recesses therein, wherein said crystallographic etching removes portions of said single-crystalline semiconductor material along fast-etched crystal planes and is terminated at slowly-etched crystal planes that constitute slanted sidewall surfaces of said recesses, wherein each recess includes a first slanted sidewall surface that terminates at an edge of an interface between said gate dielectric layer and a remaining portion of said semiconductor material portion and a second slanted sidewall surface that terminates at an edge of a top surface of one of said first and second isolation region portions after said etching, wherein each of said first and second slanted sidewall surfaces are slanted in relation to a remaining portion of said planar top surface of said semiconductor material portion; and forming a stress-inducing dielectric layer over each of said first and second slanted sidewall surfaces of the recesses, wherein at least a portion of said stress-inducing dielectric layer is formed within said recesses and below said remaining portion of said planar top surface of said semiconductor material portion.