Patent ID: 8212362

Claim:
A semiconductor device comprising: a semiconductor chip having a first main surface with an electrode pad in an exposed state and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed, said interlayer insulation layer including a surface with a post electrode mounting area defined thereon; a plurality of stress resistance resin patterns formed on the post electrode mounting area, each of said stress resistance resin patterns being disposed away from each other; a re-wiring layer including a wiring pattern, said wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion connected to the other end portion of the linear portion and formed on each of the stress resistance resin patterns, said post electrode mounting portion being formed in a polygonal shape; a base metal layer formed between the stress resistance resin patterns and the re-wiring layer; a post electrode formed on the post electrode mounting portion; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.