Patent ID: 7428651

Claim:
An electronic circuit, comprising: a central processing unit having a clock connection for receiving a first clock and a data connection; a peripheral unit having a clock connection and a data connection; synchronization means comprising a first and a second data connection, said first data connection being connected to said data connection of said peripheral unit; and a data bus being connected to said data connection of said central processing unit and to said second data connection of said synchronization means, wherein said central processing unit, said peripheral unit, said synchronization means, said data bus and an oscillator are arranged on a common chip card, said clock connection of said peripheral unit is connected to said signal output of said controllable oscillator, said clock connection of said central processing unit is coupled to an external connection device being arranged to be connectable to a corresponding contact connection of a terminal, and said controllable oscillator being controlled independent from the first clock, a controlling means being arranged to control said controllable oscillator depending on energy available for said electronic circuit such that the energy available for said electronic circuit is distributed to the peripheral unit and the central processing unit, and a computing speed with the energy available for said electronic circuit is maximized.