Patent ID: 7846788

Claim:
A method of fabricating a semiconductor device, comprising the steps of: forming a gate insulation film on a semiconductor substrate; forming a first silicon layer on said gate insulation film; forming a mask film over said first silicon layer; employing a single mask and thus etching said mask film, said first silicon layer, said gate insulation film and said semiconductor substrate to provide a trench; filling said trench with an insulation film to provide an isolating insulation film; planarizing said isolating insulation film to expose said mask film; removing said mask film and forming a second silicon layer on said first silicon layer and said isolating insulation film; and patterning said second silicon layer, wherein in the step of forming said first silicon layer an undoped amorphous silicon layer is formed as said first silicon layer and in the step of forming said second silicon layer a doped silicon layer is formed by depositing a silicon layer having a predetermined impurity concentration as said second silicon layer, and an impurity included in said second silicon layer is thermally diffused through a subsequent thermal process corresponding to annealing at 900° C. or more into said first silicon layer, so that a distribution of said impurity's concentration throughout the first and second polysilicon layers has an absolute maximum value located in said first polysilicon layer, and said distribution substantially monotonously increases from said second polysilicon layer to said absolute maximum value and decreases from said absolute maximum value toward said gate insulation film.