Patent ID: 7475368

Claim:
A method for analyzing a circuit design comprising: discretizing a circuit design into a series of pixel elements comprising copper and a low dielectric constant dielectric material; determining for each pixel element a fraction of at least one constituent material; and determining for each pixel element a deflection predicated upon a planarizing of the pixel element while utilizing an algorithm that includes the fraction of the at least one constituent material, wherein the algorithm is: δ = P A ⁢ ∑ i ⁢ [ h i x Cu i ⁢ E Cu + ( 1 - x Cu i ) ⁢ E diel ] where: δ=deflection; P=planarizing downforce; A=pixel area; h i =height of the i th wiring level; x i Cu =area fraction of copper in the i th wiring level; E Cu =Young's modulus of copper; and E diel =Young's modulus of dielectric.