Patent ID: 6897555

Claim:
A BGA package, which comprises: a substrate having a front side and a back side; a die attachment region formed on the front side of the substrate; an electrically conductive first power ring that includes a plurality of spaced apart conductive first ring segments formed on the front side of the substrate, the first ring segments being arranged around the die attachment region; an electrically conductive second power ring that includes a plurality of spaced apart conductive second ring segments formed on the front side of the substrate, the second ring segments being arranged around the die attachment region and positioned at a greater distance from the die attachment region than the first ring segments; a plurality of vias penetrating through the substrate, including: a subgroup of first vias which are connected to the first ring segments of the first power ring; and a subgroup of second vias which are connected to the second ring segments of the second power ring; a semiconductor die mounted over the die attachment region on the front side of the substrate, the semiconductor chip having a plurality of bond pads; bonding wires for connecting the plurality of bond pads of the die to associated first ring segments and second ring segments; wherein the each of the first ring segments includes a conductive tab that electrically connects the first ring segments to at least some of the first vias; and wherein the conductive tabs of the first ring segments are arranged so that they pass through spaces between the plurality of spaced apart conductive second ring segments.