Patent ID: 7879626

Claim:
A method for manufacturing a semiconductor memory device having a cross point structure, comprising: depositing on a semiconductor substrate a first insulating material and a lower electrode material for lower electrodes; patterning and planarizing the first insulating material and/or the lower electrode material to configure the lower electrodes such that surfaces of the lower electrodes and the first insulating material are substantially coplanar; depositing a memory material of a perovskite material on the surfaces of the lower electrodes and the first insulating material; depositing an upper electrode material for upper electrodes on the memory material; patterning the memory material and the upper electrode material with a use of an upper electrode masking to configure the upper electrodes; and depositing a second insulating material on the upper electrodes, wherein the lower electrodes extend in a direction, wherein the upper electrodes extend in a direction substantially perpendicular to the direction of the lower electrodes, wherein the patterned memory material extend along corresponding to the upper electrodes, and wherein each lower electrode spans multiple upper electrodes such that each lower electrode extends beyond a cell region of a memory cell, which is an area defined by a cross-section between the lower electrode and any upper electrode spanned by the lower electrode.