Patent ID: 8664754

Claim:
A high power semiconductor package comprising: a control transistor disposed on a leadframe and including a bottom surface having a control source and a control gate and a top surface having a control drain; a sync transistor disposed on said leadframe and including a bottom surface having a sync drain and a top surface having a sync source and a sync gate; a driver integrated circuit (IC) disposed on said leadframe and electrically coupled to said control gate and said sync gate; a control transistor conductive clip electrically coupling said control drain to a first pad of said leadframe; a sync transistor conductive clip electrically coupling said sync source to a second pad of said leadframe, said control source being electrically coupled to said sync drain by a common region of said leadframe; said driver IC disposed on a third pad of said leadframe, said third pad isolated from said common region, and said first pad and said second pad disposed on a common side of said leadframe opposite of said third pad.