Patent ID: 8578139

Claim:
A data processing apparatus comprising: execution circuitry configured to execute a sequence of program instructions; checkpoint circuitry configured to identify an instance of a predetermined type of instruction in said sequence of program instructions and to store checkpoint information associated with said instance of said predetermined type of instruction, said checkpoint information identifying a state of said data processing apparatus prior to execution of said instance of said predetermined type of instruction, wherein said predetermined type of instruction has an expected long completion latency, and wherein if said execution circuitry does not complete execution of said instance of said predetermined type of instruction due to occurrence of a predetermined event, said data processing apparatus is arranged to reinstate said state of said data processing apparatus with reference to said checkpoint information, such that said execution circuitry is configured to recommence execution of said sequence of program instructions at said instance of said predetermined type of instruction, wherein said execution circuitry is configured to perform speculative execution of at least some of said program instructions before they are confirmed to be required to be executed, wherein said data processing apparatus further comprises branch prediction circuitry, said branch prediction circuitry configured to predict an outcome of a branch instruction and to cause said execution circuitry to perform said speculative instruction execution on the basis of said outcome, wherein said checkpoint circuitry further comprises branch monitoring circuitry configured to store branch information as said checkpoint information until said outcome of said branch instruction is known, said branch information indicative of a position of said branch instruction in said sequence of program instructions, wherein said checkpoint circuitry is configured, upon identification of said instance of said predetermined type of instruction, to store as said branch information in said branch monitoring circuitry associated with said instance of said predetermined type of instruction information indicative of a position of said predetermined type of instruction in said sequence of instructions.