Patent ID: 8838406

Claim:
A re-configurable test circuit for use in an automated test equipment, the test circuit comprising: a test processor; a programmable logic device; and a pin electronics circuit configured to provide an interface between the re-configurable test circuit and a device-under-test; wherein the test processor comprises a timing circuit configured to provide one or more adjustable-timing signals comprising an adjustable timing; wherein the programmable logic device is configured to implement a state machine, a state sequence of which is dependent on one or more input signals received via the pin electronics circuit; wherein the re-configurable test circuit is configured to acquire, using the programmable logic device, an output signal, which output signal is dependent on a current or previous state of the state machine, and which output signal is indicative of a signal to be output by the pin electronics circuit, in response to the one or more input signals received from the pin electronics circuit; and wherein the test processor is coupled to the programmable logic device and wherein the test processor is configured to adjust, using the one or more adjustable-timing signals, a timing used in a signal processing path, wherein the signal processing path comprises a path through the programmable logic device to provide the output signal in dependence on the one or more input signals.