Patent ID: 7045406

Claim:
A method of fabricating a semiconductor device, comprising depositing a gate dielectric layer over a semiconductor substrate; forming a gate electrode comprising a lower part and an upper part over the gate dielectric layer, the gate dielectric layer and the gate electrode forming a gate stack; and tuning overall electronegativity of the lower part of the gate electrode by adjusting the composition of the lower part of the gate stack to provide a desired work function for the gate stack, wherein at least the lower part of the gate electrode is formed by an atomic layer deposition (ALD) type process selected from the group consisting of atomic layer deposition (ALD), radical assisted atomic layer deposition (RA-ALD) and plasma enhanced atomic layer deposition (PEALD), wherein the atomic layer deposition type process comprises one or more deposition cycles comprising a sequence of alternating and repeated exposure of the substrate to two or more different reactants to form an elemental metal film or a compound film of at least binary composition and wherein the work function of the lower part of the gate electrode is tuned by oxygen doping by adjusting the deposition cycles by introducing at least one additional reactant in selected deposition cycles, and wherein the additional reactant comprises an oxygen precursor.