Patent ID: 7061782

Claim:
A content addressable memory comprising at least a first single bit storage, a word line, at least one bit write line and a hit/miss line, and at least a first single bit compare circuit, said first single bit storage comprises at least a first output and said first single bit compare circuit comprises at least a first compare bit input and two field effect transistors, characterized in that said first output of said single bit storage is applied to the gate of only one, a first field effect transistor of said two field effect transistors, a second output of said single bit storage is applied to the gate of only one, a second field effect transistor of said two field effect transistors, the source of said first field effect transistor is connected with the source of said second field effect transistor, and characterized by a third field effect transistor, whereby the sources of said first and said second field effect transistors are connected with the source of said third field effect transistor and a restore signal is applied to the gate of said third field effect transistor.