Patent ID: 8824184

Claim:
A semiconductor memory device comprising: a substrate including a cell array region between a first and a second connection region; a first stacked structure including, a plurality of first wordline structures sequentially stacked, each of the first wordline structures including, a plurality of first wordlines extending in a first direction on the cell array region of the substrate, and a first connecting pad extending in a second direction that crosses the first direction on the first connection region of the substrate, the first connecting pad being connected in common to at least one of the plurality of the first wordlines; and an insulating layer covering the first stacked structure; a plurality of first interconnections disposed on the insulating layer in the first connection region of the substrate, the first interconnections being connected to the first connecting pad of the plurality of first wordline structures, respectively, wherein a length of the first connecting pad in the first direction is substantially equal to a product of a minimum pitch between the first interconnections and a stack number of one of the plurality of first wordline structures, the first connecting pad is formed on the same layer as the plurality of first wordlines, in each of the first wordline structures.