Patent ID: 8344455

Claim:
A semiconductor device comprising: a gate electrode formed on an active region of a substrate; a first silicon-germanium layer formed in a first recess provided in a portion of the active region on a first side of the gate electrode; a first silicide layer formed on the first silicon-germanium layer; a gate interconnect formed on a region of the active region opposite side of the gate electrode to the first silicon-germanium layer; a second silicide layer formed on the gate interconnect; a first contact plug connected to the first and second silicide layer; a first side wall formed on one side surface of the first gate interconnected closer to the first silicon-germanium layer; and a second side wall formed on another side surface of the gate interconnect opposite to the first silicon-germanium layer, wherein: the first contact plug is a shared contact plug to connect the first silicon-germanium layer and the gate interconnect, and a top position of a part of the first side wall which is located under first contact plug is lower than a top position of the second side wall.