Patent ID: 8884653

Claim:
A comparator comprising: a switching element configured to turn on or off in synchronization with a clock signal; a differential pair configured to conduct a comparison between input voltages in synchronization with turning on or off of the switching element; and a positive feedback part configured to output a result of the comparison conducted by the differential pair, the positive feedback part including a first CMOS inverter and a second CMOS inverter, the first CMOS inverter and the second CMOS inverter being subjected to a positive feedback, the first CMOS inverter including a first PMOS transistor, a first NMOS transistor, and a first element configured to provide an electric potential difference between a drain of the first PMOS transistor and a drain of the first NMOS transistor, the second CMOS inverter including a second PMOS transistor, a second NMOS transistor, and a second element configured to provide an electric potential difference between a drain of the second PMOS transistor and a drain of the second NMOS transistor, a higher electric potential side of the first element being connected to a gate of the second NMOS transistor, a lower electric potential side of the first element being connected to a gate of the second PMOS transistor, a higher electric potential side of the second element being connected to a gate of the first NMOS transistor, and a lower electric potential side of the second element being connected to a gate of the first PMOS transistor, wherein the differential pair is connected to both a source of the first NMOS transistor and a source of the second NMOS transistor.