Patent ID: 7576377

Claim:
A ferroelectric memory device comprising: a semiconductor substrate having a memory cell array area and a logic circuit area; a first insulating film in the memory cell array area and the logic circuit area; a plurality of first plugs which extend through the first insulating film in the memory cell array area; a plurality of second plugs which extend through the first insulating film in the logic circuit area; a plurality of conductive hydrogen barrier films over the first insulating film so as to individually cover top faces of the plurality of first plugs, the conductive hvdrogen barrier films having end edge portions; ferroelectric capacitor structural bodies over parts of the plurality of conductive hydrogen barrier films lying in the memory cell array area, each of said ferroelectric capacitor structural bodies are a lamination including a lower electrode, a ferroelectric layer and an upper electrode; a first insulating hydrogen barrier film over the first insulating film in the memory cell array area so as to cover the ferroelectric capacitor structural bodies and the conductive hydrogen barrier films and so as to be connected with the end edge portions of the conductive hydrogen barrier films, said first insulating hydrogen barrier film having first apertures exposing parts of the upper electrodes and a second aperture exposing part of the corresponding conductive hydrogen barrier film; a second insulating film over the first insulating hydrogen barrier film and having third apertures communicating with the first apertures and a fourth aperture communicating with the second aperture, wherein end edge portions of the first insulating hydrogen barrier film are exposed from the second insulating film in a closed annular form as exposed portions; a plurality of local wirings extending over the second insulating film, the plurality of local wirings connecting the upper electrodes exposed from the third apertures and the conductive hydrogen barrier film exposed from the fourth aperture, connecting the upper electrodes to one another and connecting the conductive hydrogen barrier films to one another; a second insulating hydrogen barrier film over the memory cell array area and so as to be connected with the exposed portions of the first insulating hydrogen barrier film, the plurality of the local wirings and the second insulating film; a third insulating film which covers the second insulating hydrogen barrier film and the logic circuit area; third plugs in the logic circuit area and respectively extending through the third insulating film so as to be electrically connected to the second plugs; and a first wiring layer extending over the third insulating film and including a plurality of wiring portions, said first wiring layer being connected to the third plugs, wherein the ferroelectric capacitor structural bodies and the plurality of local wirings are sealed by the first and second insulating hydrogen barrier films and the plurality of conductive hydrogen barrier films.