Patent ID: 8803549

Claim:
A latch circuit comprising a signal output circuit having two input terminals and two output terminals, wherein only when logic signals having the same logic level are input to the two input terminals, signals having the same phase as the logic signals are output, the latch circuit comprising: a feedback circuit including the signal output circuit; and an input circuit for inputting signals having the same logic level as input signals, input to the latch circuit, to the input terminals of the signal output circuit in synchronization with a clock signal; wherein, in the feedback circuit, when signals having the same logic level are input to the input terminals of the signal output circuit, positive feedback is applied to the input terminals of the signal output circuit; and wherein the feedback circuit further comprises: multiple inverter circuits, each having two first input terminals and one first output terminal, wherein only when logic signals having the same logic level are input to the two first input terminals, inverted signals of the logic signals are output from the output terminal; and a voltage supply circuit having first and second voltage supply terminals and second and third input terminals, wherein when a logic level of the second input terminal is high, a signal having a low logic level is supplied from the first voltage supply terminal, and when a logic level of the third input terminal is high, a signal having a low logic level is supplied to the second voltage supply terminal; wherein the two first input terminals of the inverter circuits are connected to the two output terminals of the signal output circuit; the first output terminals of the inverter circuits are connected to the two input terminals of the signal output circuit; and the second input terminal and the second voltage supply terminal are connected to one second output terminal of the signal output circuit, and the third input terminal and the first voltage supply terminal are connected to another second output terminal of the signal output circuit.