Patent ID: 7256975

Claim:
An electrostatic discharge (ESD) protection circuit, comprising: a first first-type transistor; a first second-type transistor; a second second-type transistor, wherein the drains of the first first-type and second-type transistors are coupled to a pad, wherein the source of the first second-type transistor is coupled to the drain of the second second-type transistor, wherein the source of the first first-type transistor is coupled to a first power rail, and the source of the second second-type transistor is coupled to a second power rail, and wherein, during normal operation, the gate of the first second-type transistor is coupled to the first power rail, and the gate of the second second-type transistor is controlled by a pre-driver; an ESD detection circuit configured to detect whether ESD occurs at the pad, the ESD detection circuit being further configured to equalize voltage levels of the gates of the first and second second-type transistors and the second power rail during ESD; a redundant circuit having a second first-type transistor, a third second-type transistor, and a fourth second-type transistor, wherein the drain of the second first-type transistor and the drain of the third second-type transistor are coupled to the pad, wherein the source of the third second-type transistor is coupled to the drain of the fourth second-type transistor, wherein the source of the second first-type transistor is coupled to the first power rail, wherein the source and the gate of the fourth second-type transistor are coupled to the second power rail, and wherein, during normal operation, the gate of the third second-type transistor is coupled to the first power rail; and an inverter circuit coupled to the ESD detection circuit, the inverter circuit configured to couple the gate of the first second-type transistor and the gate of the third second-type transistor to the second power rail.