Patent ID: 7400526

Claim:
A memory element comprising: a resistance element having a first resistance value in a first state and a second resistance value in a second state, wherein the resistance element is configured to be placed in one of the second state and the first state, and wherein the first resistance value and the second resistance value are different; a current generating device coupled to one of a first terminal and a second terminal of the resistance element, wherein the current generating device is configured to: generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, wherein the current with the first amplitude is configured to place the resistance element into the first state with the first resistance value; and generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, wherein the current with the second amplitude is configured to place the resistance element into the second state with the second resistance value, wherein the first resistance value represents a first memory state and the second resistance value represents a second memory state.