Patent ID: 7949981

Claim:
A computer-implemented method comprising: obtaining a circuit design including a plurality of viafill vias, the circuit design having differing via density across the circuit design, wherein each viafill via interconnects non-functional metal fill shapes in different layers of the circuit design; selecting a region of the circuit design to evaluate using an evaluation window; determining a via density within the evaluation window; comparing the via density within the evaluation window with a threshold via density, the threshold via density being based upon a likelihood of a subsequent coating deposition resulting in a substantially planar surface; and decreasing, using at least one computing device, a number of viafill vias within the region in the circuit design, or modifying, using the at least one computing device, a shape of one of the plurality of viafill vias, the decreasing or the modifying being performed in response to the via density being different than the threshold via density.