Patent ID: 7639056

Claim:
A data retention apparatus comprising: a first latch for latching a data input; a second latch coupled to the first latch for retaining the data input while the first latch is inoperative in a standby power mode; and a controller having a clock input and a retention input, the controller providing a clock output to the first latch and to the second latch, wherein a change in a retention signal received at the retention input is indicative of a transition to the standby power mode, wherein the controller holds the clock output at a predefined voltage level in the standby power mode, and wherein the controller includes: a first switch controlled by an inverse of the retention signal, wherein the first switch is inoperative in the standby power mode; and a second switch controlled by the inverse of the retention signal, wherein the second switch holds the clock output at the predefined voltage level responsive to the inverse of the retention signal.