Patent ID: 8266464

Claim:
A method of operating a static random access memory comprising a plurality of memory blocks within the memory, the memory operable in an active state when powered at a first power supply voltage, and in a low leakage data retention state when powered at a second power supply voltage that is lower than the first power supply voltage, the method comprising: while in an access mode of operation, applying the first power supply voltage to the memory to place all of its memory blocks in an active state allowing memory access, and accessing one or more locations in the memory, wherein each memory access is performed in defined period of time, T; while in a retain-till-access mode of operation, applying the second power supply voltage to all of the plurality of memory blocks until an access request is received, then only when an access request is received applying the first power supply voltage to only one of the memory blocks corresponding to the access request, accessing the one memory block, and then applying the second power supply voltage to all of the plurality of memory blocks upon completing the memory access; and while in an extended retain-till-access mode of operation, applying the second power supply voltage to all of the plurality of memory blocks until an access request is received, then when an access request is received applying the first power supply voltage to all of the plurality of memory blocks corresponding to the access request, accessing the one memory block, waiting for a latency period of time, then accessing a requested one of the memory blocks; measuring time after a memory access, while applying the first power supply voltage to the memory to maintain all of its memory blocks in the active state; and responsive to the measured time reaching a specified period of time without a memory access occurring, applying the second power supply voltage to the memory to place all of its memory blocks into the low leakage data retention state.