Patent ID: 7763922

Claim:
A semiconductor memory comprising: a first interlayer insulating film formed on a silicon substrate having an impurity diffusion layer; a capacitor contact formed to penetrate the first interlayer insulating film and connected to the impurity diffusion layer; a second interlayer insulating film formed on the first interlayer insulating film; a trench formed to penetrate the second interlayer insulating film and connected to the capacitor contact; a lower electrode formed only in the trench and connected to the capacitor contact; a capacitive insulating film directly formed on the lower electrode; an upper electrode formed on the capacitive insulating film; and a third interlayer insulating film formed on the upper electrode; wherein the lower electrode is not formed in an upper region of side surfaces of the second interlayer insulating film in the trench, the capacitive insulating film is formed directly on the upper region of side surfaces of the second interlayer insulating film, and the capacitive insulating film and the upper electrode extend from a side surface of the second interlayer insulating film within the trench onto a top surface of the second interlayer insulating film, and said third interlayer insulating film is buried in the trench with the upper electrode interposed therebetween.