Patent ID: 7346099

Claim:
A system, comprising: a bus; first logic having a multiphase phase lock loop to generate a multiphase encoded waveform, the first logic including an input register to receive at least one data word or at least one command/control word, and wherein the command/control word is to indicate whether the multiphase encoded waveform is a data structure or a command/control structure, wherein the bus includes at least one differential transmission line to receive differential signal levels for the multiphase encoded waveform; and second logic coupled to the first logic to generate differential signal levels representing the multiphase encoded waveform and wherein the second logic further comprises impedence matching circuitry to match impedance of the second logic to the differential transmission line, the impedence matching circuitry comprising: an operational amplifier; a first resistor; a second resistor; a first capacitor; a second capacitor; and a transistor, wherein a first terminal of the first resistor, a first terminal of the second capacitor, and a first terminal of the first capacitor are coupled to a minus input of the operational amplifier, wherein a second terminal of the first capacitor is coupled to ground, wherein a plus input of the operational amplifier is coupled to Vcc/ 2 , wherein a second terminal of the first resistor, a second terminal of the second capacitor, and a first terminal of the resistor are coupled to a first terminal of the transistor, wherein a second terminal of the second resistor is coupled to Vcc, wherein an output terminal of the operational amplifier is coupled to a second terminal of the transistor, and wherein a third terminal of the transistor is coupled to ground, and wherein the second logic is further to drive the multiphase encoded waveform onto the bus.