Patent ID: 7844971

Claim:
A data manipulation system in a computing device, the data manipulation system comprising: a processor; a memory having instructions which, when executed by the processor, cause the processor to, generate a first data structure (“T”) in the memory, the first data structure to include, for each of a plurality of threads, a termination status of the each of a plurality of threads; generate a second data structure (“S”) in the memory, the second data structure to include, for each of a plurality of synchronization primitives, the termination status of a plurality of threads that is associated with a synchronization primitive; execute a propagation logic to propagate the termination status, of a first thread and a second thread, between the first data structure and the second data structure in response to thread operations; and execute a detection logic to determine, based on the termination status of the first thread and the second thread contained in the first data structure and the second data structure, whether the first thread could access a stack allocated in the memory and designated to the second thread before a termination of the second thread, the detection logic having an actual-access reporting logic to report an actual cross-thread stack access if the second thread has not terminated, and a potential-access reporting logic to report a potential cross-thread stack access if the second thread has terminated and the termination status of the second thread has not propagated to the first thread.