Patent ID: 8091219

Claim:
A method of coupling a first circuit board with a second circuit board, comprising: providing a plurality of wafers positioned within a connector frame between parallel first and second walls secured to the first and second circuit boards, respectively, each wafer having a first edge in sliding contact with the first wall, an opposing second edge in sliding contact with the second wall, and a plurality of electrically conducting pathways extending from the first edge to the second edge, wherein the plurality of wafers are supported with a wafer guide structure disposed within the frame and defining a plurality of wafer-support aisles on each of the first and second walls, each wafer support aisle on the first wall receiving the first edge of a respective one of the plurality of wafers and each wafer support aisle on the second wall receiving the second end of a respective one of the plurality of wafers, to constrain the wafers with a fixed spacing and generally parallel alignment, and wherein a plurality of terminals disposed on the first circuit board are biased to protrude laterally into the wafer support aisles provided on the first circuit board and a plurality of terminals disposed on the second circuit board are biased to protrude laterally into the wafer support aisles provided on the second circuit board, the terminals being spaced along the wafer support aisles; and moving each wafer within the respective wafer support aisle between a first position, wherein each electrically conducting pathway is not in electrical contact with one of the terminals on the first wall and an associated one of the terminals on the second wall, to a second position, wherein each electrically conducting pathway is in electrical contact with one of the terminals on the first wall and an associated one of the terminals on the second wall.