Patent ID: 7254183

Claim:
An apparatus comprising: a primary link transmitter having a plurality of primary link data channels to transmit encoded and serialized primary link data; a secondary link transmitter having a plurality of secondary link data channels to transmit encoded and serialized secondary link data; and a clock generator coupled to the primary link transmitter and to the secondary link transmitter to generate a primary clock signal and a secondary clock signal, wherein during a single link mode of operation the primary clock signal is used as a primary link bit clock for the primary link data channels and the secondary clock signal is selected as a secondary link bit clock for the secondary link data channels, but during a dual link mode of operation the primary clock signal is used as the primary link bit clock for the primary link data channels and also selected as the secondary link bit clock for the secondary link data channels to ensure synchronization of data on the primary link data channels and the secondary link data channels.