Patent ID: 7177229

Claim:
An apparatus for adjusting a RAS active time in a memory device for outputting a constantly tuned RAS active time, comprising: a clock sync time generating unit that generates a first RAS signal tRAS 1 in synchronization with a result of counting a predetermined number of clocks after a row active operation of a memory device; an inverter delay time generating unit that generates a second RAS signal tRAS 2 using an inverter delay after the row active operation of a memory device; a delay correcting unit that corrects the duration of the second RAS signal tRAS 2 output from the inverter delay time generating unit; a comparing unit that compares signals output from the dock sync time generating unit and the delay correcting unit and which outputs a signal corresponding to a result of the comparison; and a delay control unit that generates and provides a control signal corresponding to the output signal of the comparing unit to the delay correcting unit.