Patent ID: 8239708

Claim:
A system on a chip (SoC) device verification system comprising: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting the external IP verification model and selecting an external device in response to a memory control signal received from the memory controller of the SoC device model, wherein the external IP verification model comprises: an IP verifying unit that verifies the operation of the one or more IPs included in the SoC device model; and a common model interface signal converting unit receiving a common model interface signal from the bus select model and converting the common model interface signal into a signal that is compatible with the IP verifying unit; wherein the IP verifying unit verifies the operation of the one or more IPs in response to the signal generated by the common model interface signal converting unit, and wherein the bus select model transmits the common model interface signal to the external IP verification model when selecting the external IP verification model, and transmits the memory control signal to the external device when selecting the external device.