Patent ID: 8686390

Claim:
A nonvolatile memory element comprising: a lower line formed above a substrate; a first electrode formed on said lower line; an interlayer insulating layer formed on said first electrode and provided with a memory cell hole that reaches a portion of said first electrode; a barrier layer formed in a recessed shape to cover a bottom surface and at least a portion of a side wall inside said memory cell hole and connected to said first electrode, said barrier layer being a semiconductor layer or an insulating layer; a second electrode formed inside said memory cell hole and connected to both a portion of said barrier layer formed on the side wall and a portion of said barrier layer formed on the bottom surface; a variable resistance layer formed on said second electrode and having a stacked structure including a first oxide layer and a second oxide layer having an oxygen content atomic percentage that is higher than an oxygen content atomic percentage of said first oxide layer; and a third electrode formed on said interlayer insulating layer and connected to said variable resistance layer, wherein a resistance state of said variable resistance layer changes to a different resistance state based on an electric signal applied between said second electrode and said third electrode, said barrier layer forms a Schottky barrier junction with at least one of said first electrode and said second electrode, and said first electrode is formed lower than a bottom plane of said memory cell hole and on an entire top surface of said lower line.