Patent ID: 7191313

Claim:
A microprocessor comprising: a pipeline task execution module having at least two stages, including: (i) at least two, one-element arithmetic means for performing arithmetic processing of task data, each defining a corresponding stage; (ii) at least two-element memory means associated with a respective one of the at least two stages for storing said task data processed by said associated, one-element arithmetic means; task control means for saving data on a second task held by the other of said at least two-element memory means while a first task is executed by using said at least two-element memory means selected by said task control means, said task control means selects said other of said at least two, two-element memory means when an interrupt control signal is input from outside, and performs control such that, if said interrupt control signal is input while said task data is saved by said at least two, two-element memory means, said interrupt control signal is held until saving of said task data is completed by said at least two, two-element memory means, and said other of said at least two-element memory means is selected when the saving of said task data is completed; and restore means for restoring task data on a third task stored in a save means to said other memory means while said first task is executed by using said at least two-element memory means selected by said task control means.