Patent ID: 7939941

Claim:
A stacked integrated circuit (IC) comprising: a first semiconductor die having a front-side and a back-side, wherein said first semiconductor die contains a substrate and one or more active devices on the substrate; one or more through silicon vias (TSVs) running through the substrate and a front-side insulation layer of said first semiconductor die; an inter-layer dielectric (ILD) layer on said front-side of said first semiconductor die, said ILD layer having at least one contact physically connected to a front-side of said one or more TSVs and an interface between said at least one contact and said one or more TSVs; an inter-metal dielectric (IMD) layer on said ILD layer, said IMD layer having at least one bonding pad electrically connected to said at least one contact; a second semiconductor die connected to said first semiconductor die at said at least one bonding pad; and a metallization layer on said back-side of said first semiconductor die, wherein said metallization layer comprises: at least one back-side dielectric layer over said back-side; and an etch-stop layer over one of said at least one back-side dielectric layers; said metallization layer having at least one back-side contact having a first side electrically connected to a back-side of said one or more TSVs and a second side opposite the first side exposed to allow current to flow through the second side.