Patent ID: 8044394

Claim:
A semiconductor chip comprising: a passive first region extending from a top side to a bottom side of the semiconductor chip, the top side of the semiconductor chip defining a plane; an active second region on the top side of the semiconductor chip; an arrangement of contact areas and test areas having respective top surfaces which are arranged in a common plane that is parallel to the plane of the top side of the semiconductor chip, wherein the top sides of the contact areas are square and have width and height dimensions, and the top sides of the test areas are rectangular with larger length dimensions than the width dimensions of the contact areas; a plurality of bonding balls arranged on the contact areas; the contact areas and test areas are in each case electrically conductively connected to one another via a conduction web that has a top surface that lies in the common plane, the contact areas being arranged in the passive first region, the passive first region having no active components of an integrated circuit, the test areas being arranged in the active second region, the active second region having active components of an integrated circuit, and wherein the test areas are sealed and the contact areas are not sealed; an insulating layer situated between the top side and a lower plane; through contacts extending through a portion of the insulating layer directly below the conduction web and extending from the conduction web to the lower plane, the through contacts being connected to interconnects that are connected to electrodes of the components of the integrated circuit; wherein portions of the insulating layer directly below the contact areas and the test areas are free from the through contacts.