Patent ID: 7010626

Claim:
A method for prefetching data from a system memory to a cache for a direct memory access (DMA) in a multi-processor computer system having a plurality of processor complexes (PCs) and at least one processing unit, wherein each PC comprises a processor unit (PU) coupled to a local store and a memory flow controller (MFC), the method comprising the steps of: coupling the cache to each MFC and the system memory such that the cache interfaces all PCs to each other and each PC to the system memory; requesting, by a first MFC in a first PC, data from the system memory to be transferred to a first local store for processing by a first PU; detecting a load access pattern of the data by the first MFC; predicting at least one potential load of data based on the load access pattern; in response to the prediction, prefetching the potential load of data from the system memory to the cache before a DMA command requests the potential load of data; and in response to any one of the plurality of MFCs issuing a DMA command request for the potential load of data, fetching the potential load of data directly from the cache to the local store coupled to the issuing MFC without accessing system memory.