Patent ID: 7279744

Claim:
A metal-oxide semiconductor (MOS) device, comprising: a semiconductor layer of a first conductivity type; first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another; a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions; an insulating layer formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region; a gate formed on the insulating layer and at least partially between the first and second source/drain regions; and a shielding structure formed on the insulating layer above at least a portion of the drift region, the shielding structure having an amount of coverage over an upper surface of the drift region configured to produce a peak substrate current in the MOS device less than about 70 microamperes while maintaining a breakdown voltage in the device greater than about 75 volts, such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of the amount of coverage of the shielding structure over the upper surface of the drift region; wherein the shielding structure is spaced laterally from the gate and is configured to overlap at least an edge of the gate.