Patent ID: 8553462

Claim:
A method comprising: applying a series of one or more programming pulses to a multi-level memory cell to set a threshold voltage of the multi-level memory cell at a level above a program voltage; applying a test read voltage to the multi-level memory cell to verify that the multi-level memory cell is set at the level, the test read voltage being less than the program voltage and greater than a read voltage to be used to read a state of the multi-level memory cell, and applied before any further pulses; programming a least significant bit (LSB) of a logic value to be associated with the multi-level memory cell by said applying of the series of one or more programming pulses; programming a most significant bit (MSB) of the logic value by applying another series of one or more programming pulses to the multi-level memory cell to set the threshold voltage at another level above another program voltage; and applying another test read voltage to the multi-level memory cell to verify that the multi-level cell is set at the another level, the another read voltage being smaller than the another program voltage.