Patent ID: 8365179

Claim:
A multi-thread processor comprising: a plurality of hardware threads each of which generates an independent instruction flow; a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads; a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread; an execution pipeline that executes an instruction output from the first selector, wherein whenever the hardware thread is executed in the execution pipeline, the first scheduler updates the priority rank for the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank; a second scheduler that specifies execution of at least one hardware thread selected in a fixed manner among the plurality of hardware threads in a predetermined first execution period, and outputs a second thread selection signal specifying execution of an arbitrary hardware thread in a second execution period other than the first execution period and a real-time bit signal indicating one of the first execution period and the second execution period; and a second selector that receives the real-time bit signal, and when the real-time bit signal indicates the first execution period, provides the second thread selection signal to the first selector, and when the real-time bit signal indicates the second execution period, provides the first thread selection signal to the first selector.