Patent ID: 7839679

Claim:
A nonvolatile semiconductor memory comprising: a memory cell array which includes a plurality of cell units; a power supply pad which is disposed on one end in a first direction of the memory cell array; a first page buffer which is disposed on the other end in the first direction of the memory cell array; a bit line which is disposed in a first layer on the memory cell array while extending in the first direction; a non-power supply line which is disposed in a second layer on the first layer; a power supply line which is disposed in the second layer to connect the power supply pad and the first page buffer, and the power supply line having a first portion above the memory cell array and a second portion in an area except above the memory cell array; and a switching element which is connected to one end of the non-power supply line to set the non-power supply line in a floating state or a potential other than the power supply voltage, wherein the non-power supply line and the first portion of the power supply line are adjacent to each other in a second direction orthogonal to the first direction, and extend in a meandering manner in the first direction, wherein the bit line intersects to both of the non-power supply line and the first portion of the power supply line, when the bit line, the non-power supply line and the first portion of the power supply line are seen from a third direction orthogonal to the first and second direction.