Patent ID: 8766344

Claim:
A memory cell comprising: a vertical transistor comprising a body of semiconductor material having a surface; a buried conductive region of a first conductivity type positioned in the body; a channel region in the body, the channel region having a top and a bottom, all of the bottom being in contact with the buried conductive region; a gate insulation region extending at sides of and contiguous to the channel region; and a gate region extending at sides of and contiguous to the gate insulation region wherein the buried conductive region further extends under the gate region, the buried conductive region and the gate region being insulated electrically from one another by a dielectric material layer; a phase change memory element coupled to a surface conductive region of the vertical transistor with a ring-shaped heater; and a dielectric material within an interior of the ring-shaped heater wherein the surface conductive region is of the first conductivity type, and is in the body and arranged on top of the channel region and the buried conductive region; wherein the ring-shaped heater is coupled to the surface conductive region through a multiple layer contact, the multiple layer contact comprising a via formed vertically in a dielectric layer, the via filled by a plurality of materials to form the multiple layer contact.