Patent ID: 8339834

Claim:
A non-volatile semiconductor memory device comprising: a first line; a second line intersecting with the first line; and a memory cell arranged at a position where the second line intersects with the first line; wherein, the memory cell includes: a variable resistance element; a negative resistance element connected in series to the variable resistance element; a first buffer portion connected to one end of the negative resistance element; and a second buffer portion connected to the other end of the negative resistance element; the negative resistance element includes: a first semiconductor layer constituting the one end; and a second semiconductor layer constituting the other end; the first buffer portion includes: a first buffer layer in contact with the first semiconductor layer; and a first electrode layer in contact with a surface of the first buffer layer opposite to a surface in contact with the first semiconductor layer; and the second buffer portion includes: a second buffer layer in contact with the second semiconductor layer; and a second electrode layer in contact with a surface of the second buffer layer opposite to a surface in contact with the second semiconductor layer; and wherein an interatomic distance of the first buffer layer in a direction along a contact surface to the first semiconductor layer is closer to an interatomic distance of the first semiconductor layer in the direction along the contact surface than an interatomic distance of the first electrode layer in the direction along the contact surface; and an interatomic distance of the second buffer layer in a direction along a contact surface to the second semiconductor layer is closer to an interatomic distance of the second semiconductor layer in the direction along the contact surface than an interatomic distance of the second electrode layer in the direction along the contact surface.