Patent ID: 8853818

Claim:
A memory device including an array of NAND strings of memory cells, comprising: an integrated circuit substrate; a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane (GSL) of conductive strips, a plurality of intermediate planes (WLs) of conductive strips, and a top plane of conductive strips (SSLs); a plurality of bit line structures arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, including inter-stack semiconductor body elements between the stacks, and linking elements over the stacks connecting the inter-stack semiconductor body elements; charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the stacks and inter-stack semiconductor body elements of the plurality of bit line structures; at least one reference line structure arranged orthogonally over the plurality of stacks, including inter-stack vertical conductive elements between the stacks, and linking elements over the stacks connecting the inter-stack vertical conductive elements; and sidewall silicide formations disposed on side surfaces of a side of at least one of the conductive strips in the stacks opposite a second side of the at least one of the conductive strips, wherein on the side surfaces of the second side the charge storage structures are formed.