Patent ID: 7242235

Claim:
A flip-flop comprising: a first latch configured to operate in a sampling mode when a clock signal is at a first logic level and in a holding mode when the clock signal is at a second logic level; said first latch having a data input terminal configured to receive a data signal; a second latch configured to operate in a holding mode when the clock signal is at the first logic level and in a sampling mode when the clock signal is at the second logic level; said first latch having a data input terminal configured to receive the data signal; a first logic gate configured to receive a first output signal supplied by the first latch and a second output signal supplied by the second latch; said first logic gate further configured to supply one of the received first and second output signals as an output signal of the flip-flop, wherein said first logic gate is a first multiplexer having first and second input terminals that receive the first and second output signals, and a select terminal adapted to receive a first select signal generated in response to a mode select signal, wherein said first select signal is generated by a logic gate performing an AND function and adapted to receive the clock signal and the mode select signal and to generate the first select signal in response.