Patent ID: 8486762

Claim:
A method of manufacturing a leadless integrated circuit (IC) package comprising: providing a leadframe strip having top and bottom surfaces; removing portions of the top surface of the leadframe strip to form recesses therein partially defining upper portions of one or more die-attach areas and upper portions of a plurality of electrical contacts; mounting a first IC chip to the leadframe strip in a first die-attach area of the partially defined one or more die-attach areas; mounting a second IC chip in a second die-attach area of the partially defined one or more die-attach areas; forming electrical connections between the plurality of partially defined electrical contacts and the first IC chip; covering the first IC chip, the second IC chip, the partially defined one or more die-attach areas, the partially defined electrical contacts, and the electrical connections with a molding layer, the molding layer filling the recesses; forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the partially defined one or more die-attach areas and the plurality of partially defined electrical contacts; and selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby etching through portions of the leadframe strip to define lower portions of the plurality of electrical contacts and lower portions of the one or more die-attach areas.