Patent ID: 8218390

Claim:
A semiconductor device comprising: a plurality of memory cells arranged in rows and columns; a plurality of bit lines, provided corresponding to the columns, each connected to memory cells on the corresponding column; a power supply node supplying a power supply voltage; a plurality of cell power supply lines, provided corresponding to the columns, each connected to memory cells on the corresponding column; an internal data line; a plurality of column select gates, provided corresponding to the columns, each connected to a bit line on the corresponding column and electrically coupling the bit line on the corresponding column to the internal data line in accordance with a column select signal; and a plurality of switch circuits, provided corresponding to the columns, each electrically connecting and disconnecting a cell power supply line on the corresponding column to the power supply node in accordance with the column select signal, wherein on each column, a memory cell connected closest to the switch circuit via the cell power supply line provided on the corresponding column is the same as a memory cell connected closest to the column select gate via the bit line provided on the corresponding column.