Patent ID: 7485910

Claim:
A semiconductor structure comprising: a semiconductor substrate including at least one array region and at least one support region, said semiconductor substrate having an upper active area; a semiconductor memory device including a trench gate conductor, a silicide region vertically abutting said trench gate conductor, and a gate spacer laterally abutting said silicide region and said trench gate conductor, wherein said trench gate conductor and said gate spacer are located in a deep trench that is present in said semiconductor substrate in each array region; a dielectric material layer located above and vertically abutting said silicide region and said gate spacer; an active wordline located above said semiconductor memory device and embedded in said dielectric material layer, wherein said active wordline laterally abuts sidewalls of said dielectric material layer and vertically abuts said silicide region; and a passive wordline located above said upper active area and embedded in said dielectric material layer and within said at least one array region, wherein said passive wordline laterally abuts sidewalls of said dielectric material layer.