Patent ID: 7870468

Claim:
An error correction elementary unit for use with a clock, said elementary unit having: a FIFO data input; a gamma input; a delta input; a gamma control input; a data input; a move control input; an update control input; an F1 register which generates an output by storing an input upon said clock; an F2 register which generates an output by storing an input upon said clock; a first multiplexer having an output selected by said gamma control, said output being said gamma input when said gamma control input asserted, and said FIFO data input at other times; a first Galois field multiplier generating the product of said first multiplexer output and said data input; a second Galois field multiplier generating as output the product of said delta input and said F2 output; a first Galois field adder having an output derived from the sum of said first multiplier output and said second multiplier, said first adder output coupled to said F1 input; a second multiplexer controlled by said move control input, said second multiplexer output being said first Galois field adder output when said move control input is asserted, and said data input at other times; a third multiplexer controlled by said update control input, said third multiplexer having an output coupled to said F2 input, said multiplexer selecting said F2 output when said update control input is asserted, and said second multiplexer output at other times.