Patent ID: 7202762

Claim:
A Q enhancement circuit for a component having a parasitic resistance RL 1 , said enhancement circuit comprising; a first resistance R 1 disposed in series with said component; first means for making said resistance R 1 disposed in series with said component a negative resistance −R 1 , wherein said first means for making said resistance R 1 a negative resistance includes a first transistor Q 1 ; a second component having a parasitic resistance RL 2 ; second resistance R 2 disposed in series with said second component; and second means for making said second resistance R 2 a negative resistance −R 2 , wherein said second means for making said resistance includes a second transistor Q 2 and each of said transistors has a collector, a base and an emitter terminal, wherein each of said collector terminals of said transistors Q 1 and Q 2 is connected to a respective one of first or second resistors R 1 or R 2 and said emitter terminals are connected to a respective one of said components.