Patent ID: 7344957

Claim:
A method of forming a silicon-on-insulator wafer having one or more cooling channels underlying a buried oxide layer therein, comprising: forming one or more cooling channels on a top surface of a first wafer; forming a buried oxide layer on a top surface of a second wafer; forming a micro-bubble layer below the buried oxide layer in the second wafer, wherein a depth of the micro-bubble layer below the buried oxide layer generally corresponds to a desired depth of silicon overlying the buried oxide layer of the resulting silicon-on-insulator wafer; bonding the top surface of the first wafer to the top surface of the second wafer, wherein the one or more cooling channels abut the buried oxide layer; splitting the second wafer along the micro-bubble layer therein, resulting in a portion of the second wafer overlying the buried oxide layer, which is turn overlies the one or more channels of the first wafer; and surface treating the portion of the second wafer.