Patent ID: 7102407

Claim:
A delay circuit, comprising: a first circuit including: a circuit input to receive a reference signal; a circuit output to output a delayed signal being a delayed response to the reference signal; a logic circuit including a logic input and a logic output, the logic input coupled to the circuit input to generate an inversion of the reference signal at the logic output; a pull up path coupled to the logic output; and a pull down path coupled to the logic output; a falling edge delay circuit coupled to the pull up path to control delay of a falling edge of the reference signal, wherein the pull up path includes a first transistor to selectively couple the logic output to the falling edge delay circuit; and a rising edge delay circuit coupled to the pull down path to control delay of a rising edge of the reference signal, wherein the pull down path includes second and third transistors coupled in series to selectively couple the logic output to the rising edge delay circuit.