Patent ID: 7424417

Claim:
A system for simulating a design of a digital integrated circuit chip comprising: at least one processor module in an automatic test pattern generation (ATPG) tool used for first generating a clock grouping report based on identifying and grouping one or more independent clock domain groups, and modifying said design using said clock grouping report; and at least one processor module in a timing analysis (TA) tool for: verifying said design after modifying said design using said clock grouping report, said modifying performed by a computer based chip design tool residing off-line and outside of said ATPG tool, said ATPG tool communicatively coupled to said TA tool; second generating a timing analysis of said design definition file using a timing analysis tool to generate capture mode violations; transmitting said capture mode violations into said automatic test pattern generation (ATPG) tool, said automatic test pattern generation (ATPG) tool modifying said clock grouping reports to generate a modified clock grouping report based on said capture mode violations, said computer based chin design tool remodifying said design based on said modified clock grouping report; and reperforming said second generating and said transmitting until said capture model violations are not generated by said timing analysis (TA) tool.