Patent ID: 7292481

Claim:
A semiconductor storage device comprising: a memory cell array including a plurality of memory cells respectively disposed at intersections between a plurality of bit line pairs and a plurality of word lines disposed in a direction orthogonal to said bit line pairs; and a plurality of per-bit sensing circuits connected to said plurality of bit line pairs respectively; each of said per-bit sensing circuits including: a first circuit connected to a corresponding one of said bit line pairs, for setting voltages at the corresponding one of said bit line pairs to a first level when a bit line pair selection signal received is in an inactive state; a second circuit connected to the corresponding one of said bit line pairs, for setting the corresponding one of said bit line pairs to mutually complementary levels according to a signal read onto the corresponding one of said bit line pairs from a selected memory cell when the bit line pair selection signal is in an active state and a sensing circuit activation signal received is also in an active state; and a third circuit connected to the corresponding one of said bit line pairs, for receiving a write data signal, and setting one bit line of the corresponding one of said bit line pairs, which are set in common to the first level, to a second level complementary with said first level, based on the write data signal, when the bit line pair selection signal is in an active state, thereby setting complementary write data on the corresponding one of said bit line pair; said semiconductor storage device further comprising a data output circuit for receiving respective one bit lines of said bit line pairs from said per-bit sensing circuits, and outputting data read onto a selected bit line pair.