Patent ID: 8234321

Claim:
A circuit for accelerating an initial pseudo-random bit flow having a length of 2 n-1 bits generated from a polynomial of an irreducible degree n at a first frequency, into an identical accelerated bit flow at a second frequency greater than the first clock frequency, the circuit comprising a combiner having a first input adapted to receive the initial bit flow and having an output adapted to provide the accelerated flow, a second input of the combiner being connected by a delay element to the combiner output, the delay τ of the delay element respecting the following relation: τ=((2 l )* T 1 )− T 0 , wherein T 1 represents the clock period of the input bit flow, T 0 represents the clock period of the output bit flow, and l is a non-zero integer setting a decimation parameter, wherein delay τ is also selected to respect the following relation: τ=(2 k+ 1)*(2 n −1)* T 0 , where k represents any non-zero integer, and where n represents the degree of the irreducible polynomial of the random sequence.