Patent ID: 7683432

Claim:
A semiconductor device, comprising: a well of a first conductive type formed in an upper layer of a substrate; a low-concentration layer of the first conductive type having a lower impurity concentration than the well, the low-concentration layer being formed in an extreme surface layer of a channel portion of the well; a high-k gate dielectric layer having a higher dielectric constant than a silicon oxide film, the high-k gate dielectric layer being formed on the low-concentration layer; a gate electrode formed on the high-k gate dielectric layer; extension regions of a second conductive type formed in an upper layer of the well, the extension regions sandwiching the low-concentration layer; and source/drain regions of the second conductive type formed in an upper layer of the well, the source/drain regions sandwiching the low-concentration layer and the extension regions; wherein a depth of the low-concentration layer from an upper surface of the substrate is smaller than a death of the extension regions from the upper surface of the substrate.