Patent ID: 7382030

Claim:
A semiconductor comprising: a wafer comprising a source region and a drain region; a gate electrode formed over a surface of the wafer and between the source region and the drain region, wherein the gate electrode is electrically isolated from the surface of the wafer; a shield isolation layer over at least a portion of the surface of the wafer between the gate electrode and the drain region, wherein the shield isolation layer comprises a dielectric; a metallic source contact via comprising a first top end and a first bottom end, which is electrically coupled to and extends from the source region; a metallic shield contact via comprising a second top end and a second bottom end, which is in contact with and extends from the shield isolation layer, wherein the metallic shield contact via is between the gate electrode and the drain region; a source contact electrically coupled to the first top end of the metallic source contact via; and a source contact extension electrically coupled to the second top end of the metallic shield contact via, wherein the source contact extension and the metallic shield contact via form a metal shield about the gate electrode.