Patent ID: 8497832

Claim:
A flat panel display, comprising: a display panel having a plurality of gate lines; a power supply circuit having a system voltage end and a reference voltage end, wherein the power supply circuit pulls up a voltage of the reference voltage end during a power-off period; a shift register series powered by the system voltage end and the reference voltage end of the power supply circuit, wherein the shift register series has a plurality of shift registers series-connected to one another, and an output end of each of the shift registers is one-on-one coupled to the one of the gate lines; a plurality of first transistors, wherein a first end of each of the first transistors is one-on-one coupled to one of the output ends of the shift registers respectively, and a second end of each of the first transistors is coupled to the power supply circuit; and a capacitor, wherein a first end of the capacitor is coupled to a control end of each of the first transistors, and a second end of the capacitor is coupled to the reference voltage end of the power supply circuit.