Patent ID: 7279736

Claim:
A nonvolatile memory device, comprising: a plurality of active regions on a semiconductor substrate, the active regions being defined by a plurality of device isolation layers; a tunnel oxide layer on the plurality of active regions; gate structures including floating gates, the floating gates facing each other at a distance on the tunnel oxide layer, oxide-nitride-oxide (ONO) layers on each of the floating gates, control gates on each of the ONO layers, and injection gates in contact with the floating gates; a drain region wherein the injection gates are made of a material selected from the group consisting of SiC, AlP, AlAs, AlSb, GaP, GaAs, lnP, ZnS, ZnSe, ZnTe, CdS, CdSe and CdTe in the semiconductor substrate, between the gate structures; and source regions in the semiconductor substrate, on opposite sides of the gate structures from the drain region.