Patent ID: 6878613

Claim:
A method for fabricating a field-effect transistor, which comprises the steps of: providing a substrate having a substrate surface; forming a gate oxide on the substrate surface; forming a first part of a gate electrode on the gate ocide; forming a second part of the gate electrode on the first part of the gate electrode; forming a first insulating layer on the second part of the gate electrode; patterning the first insulating layer to form a patterned hard mask; patterning the second part of the gate electrode and the first part of the gate electrode using the patterned hard mask as an etching mask, to form a gate stack; introducing a dopant into the substrate to form a source doping region and a drain doping region; removing material from the second part of the gate electrode in a lateral direction to produce an overhang; depositing a third insulating layer covering the first insulating layer above the gate stack, the gate stack, and sidewalls of the gate stack; removing the third insulating layer from the surf ace of the substrate by a directional etching; depositing a second insulating layer on the third insulating layer and on the uncovered substrate surface after the directional etching of the third insulating layer; forming a contact hole next to the gate stack in the second insulating layer by self-aligning etching with an etching rate of the second insulating layer being greater than etching rates of the first and third insulating layers causing the contact hole etching to be self-aligned with respect to the source doping region, the source doping region being uncovered at the substrate surface, the self-aligning etching of the second insulating layer being performed in a mingle etching step resulting in the contact hole next to the gate stack, the contact hole reaching from the top of the second insulating layer to the source drain region in the substrate; and filling the contact hole with a contact plug.