Patent ID: 8609483

Claim:
A method of forming an integrated circuit containing an iso-device comprising: simultaneously forming a first n-well and a second n-well, said first n-well and said second n-well having a same depth and dopant concentration; simultaneously forming a first p-well and a ci-p-well, wherein said ci-p-well is formed within said second n-well; forming a core NMOS transistor in said first p-well; forming a core PMOS transistor in said first n-well; and forming said iso-device in said ci-p-well wherein said iso-device is an iso-capacitor further comprising steps of: simultaneously with forming a gate dielectric of core NMOS transistor, forming a capacitor dielectric of said iso-capacitor; simultaneously with forming a gate of said core NMOS transistor, forming a top plate of said iso-capacitor; and simultaneously with forming a p-type source and drain on said core PMOS transistor forming a ci-p-well contact.