Patent ID: 8732440

Claim:
A method of generating a digital signal pattern at M outputs, comprising: receiving an instruction including two fields, a first field identifying a first set of N bits which are a subset of the M outputs subject to the instruction, wherein N is less than M, and a second field corresponding to states of respective subset outputs identified in the first field; for each subset output: if a bit in the second field for the respective output is in a first state, then toggling a signal at the respective output, and if the bit in the second field for the respective output is in a second state, then keeping the signal in a same state at the respective output; counting a number of subset outputs that are toggled; based on a comparison between the number of subset outputs and a toggle count value that sets a minimum value for an event, outputting the digital signal pattern at the M outputs including the subset outputs that were either toggled or kept in the same state as before the event, and the remaining M outputs not included in the subset that are kept at a same state as before the event.