Patent ID: 6898742

Claim:
An automatic deskew system for use in high-speed, parallel interconnections for a digital system for correcting skew greater than or equal to one-half bit time on signals on said parallel interconnections, comprising: a deskew controller for computing the amount of delay needed for each interconnection to align said signals on each of said interconnections, the deskew controller comprising: a selector coupled to the outputs of each of said deskew subsystems and configured for selecting between or among the outputs of said deskew subsystems; two pairs of all-zero and all-one detectors, one pair coupled to the output of said selector and the other pair coupled to the outputs of said deskew subsystems, said all-zero detector configured for indicating whether all the inputs thereto are zeroes, said all-one detector configured for indicating whether all the inputs thereto are ones; a controller coupled to said selector and said pairs of all-zero and all-one detectors, said controller configured for computing and sending a control value to said selector for selection between or among the outputs of said deskew subsystems; and a plurality of registers coupled to said controller and said deskew subsystems, said registers containing delay control values computed by said deskew controller for correcting skew on each interconnection; and a plurality of deskew subsystems, each of said deskew subsystems couple to an associated interconnection and to said deskew controller, each deskew subsystem configured for (i) unfolding a signal on an associated interconnect on, and (ii) correcting any skew in said signal greater than or equal to bit time based upon the amount of delay computed by said deskew controller.