Patent ID: 7782105

Claim:
A semiconductor memory apparatus, comprising: a first delay locked loop configured to compare a system clock with a first feedback clock and generate a first delay locked clock and a first locking signal; a second delay locked loop configured to compare an inverse system clock with a second feedback clock and generate a second delay locked clock and a second locking signal; and a clock selection block configured to select one of the first and second delay locked clocks and output the selected delay locked clock as a reference clock for data output, wherein the first delay locked clock is selected when the first locking signal is generated before the generation of the second locking signal, and wherein the second delay locked clock is selected when the second locking signal is generated before the generation of the first locking signal, wherein the first delay locked loop includes: a first delay line configured to delay the system clock; a first delay model configured to delay an output of the first delay line by a modeled delay time to generate the first feedback clock; a first phase comparator configured to compare a phase of the first feedback clock with that of the system clock; a first shift register configured to control a delay amount of the first delay line according to a comparison result of the first phase comparator; and a first locked detector configured to output the first locking signal to the clock selection block when the phase of the first feedback clock is the same as that of the system clock.