Patent ID: 7435626

Claim:
A method of manufacturing a chip-size package of a semiconductor device comprising a semiconductor chip, the method comprising: providing the chip, the chip having a semiconductor chip lower surface and an active-signal upper surface comprising bonding pads; providing a rearrangement sheet comprising an insulating sheet and a conductive metallic pattern on an upper single surface of the insulating sheet, wherein said rearrangement sheet is limited to such lateral dimensions as to be positioned inside of and encircled by a closed-loop line of the bonding pads on the upper surface of the chip; positioning and sticking the rearrangement sheet onto a region, on the upper surface of the chip, that is encircled by the bonding pads, whereby, due to the lateral dimensions, a perimeter of the chip is not covered by the insulating sheet, and the rearrangement sheet does not cover any of the bonding pads; wherein a surface of the insulating sheet, that is opposite to the single surface having the conductive metallic pattern, faces the active-signal upper surface of the chip and is stuck in contact thereto, whereby the conductive metallic pattern is exposed adjacent the bonding pads; connecting said bonding pads to wire connection portions of said conductive metallic patterns by fine metallic wires or leads; forming conductive posts on rearrangement posts of said conductive metallic patterns by stud bumps produced by wire bonding; forming a sealed portion by sealing using molded resin so as to cover said bonding pads, said rearrangement sheets, said fine metallic wires or leads and said conductive posts on the upper surface of the chip; and exposing the upper surfaces of said conductive posts by grinding the surface of said sealed portion.