Patent ID: 8729616

Claim:
A method of fabricating an electrically programmable capacitor structure for an analog semiconductor integrated circuit, formed at a semiconductor surface of a body, comprising the steps of: forming isolation dielectric structures at selected locations of the semiconductor surface, the isolation dielectric structures defining active regions of the surface therebetween; forming a gate dielectric layer over the active regions; then forming an electrode layer comprised of polycrystalline silicon over the semiconductor surface including the gate dielectric layer and the isolation dielectric structures; removing selected portions of the electrode layer to define first and second electrodes comprised of polycrystalline silicon, the first electrode including a portion overlying an isolation dielectric structure and a plurality of portions overlying active regions; forming source and drain regions on opposite sides of a portion of the first electrode overlying a first active region; forming a layer of silicon dioxide over the first and second electrodes; removing the silicon dioxide selectively from the second electrode, so that the silicon dioxide remains over the first electrode; after the step of removing the silicon dioxide, reacting exposed portions of the polycrystalline silicon, including the second electrode, with a metal to form a metal silicide; then depositing a dielectric film over the semiconductor surface including the remaining silicon dioxide and the metal silicide; then depositing a conductor layer comprising a metal; and removing selected portions of the conductor layer to define a first conductive plate overlying a portion of the first electrode, at a location overlying an isolation dielectric structure, with the dielectric film and the silicon dioxide therebetween.