Patent ID: 7416951

Claim:
A method of making an integrated circuit, comprising: (a) forming a circuit element in a semiconductor layer and a first thin film resistor on a first dielectric layer on the semiconductor layer; (b) forming a first layer of interconnect conductors on the first dielectric layer including a first interconnect conductor electrically contacting a first contact area of the first thin film resistor, a second interconnect conductor electrically contacting a second contact area of the first thin film resistor, and a circuit element interconnect conductor extending through a first opening in the first dielectric layer and directly contacting a contact area of the circuit element, wherein the first opening in the first dielectric layer extends to the contact area of the circuit element; (c) forming a second dielectric layer on the first dielectric layer, the first thin film resistor, and the first layer of interconnect conductors; (d) forming a second thin film resistor on the second dielectric layer; (e) forming a third dielectric layer on the second dielectric layer and the second thin film resistor; and (f) forming a second layer of interconnect conductors on the third dielectric layer including a third interconnect conductor extending through a first opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through a second opening in the second and third dielectric layers to contact the second interconnect conductor, and a fifth interconnect conductor extending through a third opening in the second and third dielectric layers to contact the circuit element interconnect conductor, wherein the fifth interconnect conductor and one of the third and fourth interconnect conductors extend through first and second openings in the third dielectric layer to first and second contact areas, respectively, of the second thin film resistor.