Patent ID: 7612600

Claim:
A DC offset calibration apparatus comprising: an adjustment circuit used for receiving an input signal and an offset calibration signal and for raising or lowering a voltage level of the input signal to generate an output signal according to a voltage level of the offset calibration signal; and an offset calibration circuit, coupled to the output signal and the adjustment circuit, for determining the voltage level of the offset calibration signal, the offset calibration circuit comprising: a comparator used for comparing the output signal with a predetermined threshold voltage level and thereby generating a control signal; and a transistor, having a first end coupled to a reference voltage level, a second end coupled to the voltage level of the offset calibration signal and the adjustment circuit, and a control end coupled to the comparator, wherein the control signal turns on the transistor when the output signal reaches the predetermined threshold voltage level and enters a predetermined voltage range, so as to raise or lower the voltage level of the offset calibration signal by the reference voltage level and consequently adjust the voltage level of the input signal through the adjustment circuit, and the control signal turns off the transistor and keeps the voltage level of the input signal unchanged when the output signal neither reaches the predetermined threshold voltage level nor enters the predetermined voltage range.