Patent ID: 8883572

Claim:
A manufacturing method of a low temperature poly-silicon thin film transistor (LTPS-TFT) array substrate, comprising: sequentially forming a poly-silicon layer and a data-line-metal layer on a base substrate, and performing a patterning process by using a mask to simultaneously form an active layer and source and drain electrodes, the active layer being provided on the base substrate and the source and drain electrodes being provided on the active layer, Step 1 of sequentially forming the poly-silicon layer and the data-line-metal layer on the base substrate, and performing the patterning process by using a first mask to simultaneously form the active layer and source and drain electrodes; Step 2 of depositing a gate insulating layer on the base substrate after Step 1, and performing a patterning process by using a second mask to form a first contact hole in the gate insulating layer expose one of the source and drain electrodes; Step 3 of depositing a gate-metal-layer on the base substrate after Step 2, and performing a patterning process by using a third mask to form a gate electrode, the gate electrode being provided on the gate insulating layer and corresponding to the active layer; and Step 4 of depositing a transparent conductive layer on the base substrate after Step 3, and performing a patterning process by using a fourth mask to form a pixel electrode, the pixel electrode being provided above the one of the source and drain electrodes and connected with the one of the source and drain electrodes through the first contact hole.