Patent ID: 8135917

Claim:
A snoop filter device associated with each processing unit of a computing environment having multiple processing units, each processing unit having one or more cache memories associated therewith, said snoop filter device in 1:1 correspondence with an associated processing unit, said snoop filter device comprising: a first memory storage means adapted to track cache line addresses of content that have been loaded into a cache memory level of its associated processing unit, said first memory storage means comprising a first plurality of stream register sets, each stream register set comprising one or more stream registers, each stream register including a base register and a corresponding mask register, said base register tracking address bits common to all cache line addresses represented by the stream register; and, said corresponding mask register tracking bits representing differences between a base register address and subsequent load/store addresses to the one or more cache memories of said processing unit included in its corresponding base register, wherein differing bit positions are indicated in said mask register to indicate corresponding bits of said base register as insignificant; means for receiving snoop requests from one or more memory writing sources; and snoop check logic means for comparing an address of a received snoop request against addresses stored in said first plurality of stream register sets of said first memory storage means; and, means for forwarding said received snoop request to said processing unit in response to matching an address stored in said stream register set, or otherwise discarding said snoop request, whereby a number of snoop requests forwarded to a processing unit is reduced thereby increasing performance of said computing environment.