Patent ID: 8470614

Claim:
A process of forming an integrated circuit, comprising steps: disposing a wafer containing said integrated circuit in a dielectric deposition tool under a TEOS delivery showerhead of said dielectric deposition tool, said showerhead including: an input port, said input port configured to receive TEOS gas; an interior region connected to said input port, said interior region configured to distribute said TEOS gas; and a bottom plate abutting said interior region, said bottom plate including an edge band and a central region, such that: said edge band extends from an outer edge of said bottom plate at least one half an inch and up to one fourth of a diameter of said wafer; said bottom plate includes a set of edge TEOS delivery apertures in said edge band, said edge TEOS delivery apertures being configured to deliver said TEOS gas from said interior region to said wafer; said bottom plate includes a set of central TEOS delivery apertures in said central region, said central TEOS delivery apertures being configured to deliver said TEOS gas from said interior region to said wafer; and so that an area percentage of said edge TEOS delivery apertures is at least twice an area percentage of said central TEOS delivery apertures, in which: said area percentage of said edge TEOS delivery apertures is calculated by dividing a total area of said edge TEOS delivery apertures by an area of said edge band; and said area percentage of said central TEOS delivery apertures is calculated by dividing a total area of said central TEOS delivery apertures by an area of said central region; forming a layer of silicon dioxide on a top surface of said wafer by providing TEOS gas to said input port, so that: an average flow rate per unit area of said TEOS gas from said edge band of said showerhead is at least twice an average flow rate per unit area of said TEOS gas from said central region of said showerhead; and said silicon dioxide layer is thicker in a wafer outer annulus under said edge band of said showerhead than in a wafer core under said central region of said showerhead; planarizing said silicon dioxide layer using a chemical mechanical polish (CMP) process, so that a thickness difference between an average thickness in said wafer outer annulus and an average thickness in said wafer core after completion of said CMP process is less than half a thickness difference between an average thickness in said wafer outer annulus and an average thickness in said wafer core after formation of said silicon dioxide layer and before said CMP process.