Patent ID: 7257015

Claim:
A semiconductor memory device including a plurality of transistors, wherein each of the transistors comprises: a semiconductor layer which is a first conduction type and electrically isolated from other memory cells such that is floating; a drain diffusion region which is a second conduction type, formed in the first conduction-type semiconductor layer, and connected to a bit line; a source diffusion region which is the second conduction type, formed apart from the drain diffusion region in the first conduction-type semiconductor layer, and connected to a source line; and a gate electrode formed on the semiconductor layer between the drain diffusion region and the source diffusion region with a gate insulator therebetween, and forms a word line, wherein the transistor has a first data state having a first threshold voltage in which excessive majority carriers are held in the semiconductor layer and a second data state having a second threshold voltage in which the excessive majority carriers in the semiconductor layer are emitted, wherein the bit line is one of a plurality of bit lines, a sense amplifier being provided for the plurality of bit lines, one of the bit lines being selected to be connected to the sense amplifier, and wherein the first data state is a state in which impact ionization is generated near a drain junction by operating the transistor and in which excessive majority carriers produced by this impact ionization are held in the semiconductor layer, and the second data state is a state in which a forward bias is applied between the semiconductor layer and the drain diffusion region to extract the excessive majority carriers from within the semiconductor layer to the drain diffusion region.