Patent ID: 7250807

Claim:
A threshold scaling circuit comprising: a MOS transistor connected to output a current, the transistor having a gate, a first terminal, a second terminal, and a body connected to receive a back bias voltage; a first clock circuit connected to output a first clock signal, the first clock signal having a plurality of first edges, and a frequency that varies in response to a magnitude of the current, the first clock circuit being connected to the transistor to receive the current; a second clock circuit connected to output a second clock signal, the second clock signal having a plurality of second edges; a counter connected to count the plurality of first edges to generate a sequence of count values, each count value representing a number of first edges of the first clock signal that occur during a period defined by a pair of second edges, the counter being connected to the first clock circuit to receive the first clock signal and the second clock circuit to receive the second clock signal; a minimum count detector connected to evaluate the sequence of count values to determine a minimum count value, and store the minimum count value, the minimum count detector being connected to the counter to receive the count values; a counting circuit connected to step through a count range in response to the second clock signal, the count range having a sequence of steps and a corresponding sequence of counts, the counting circuit being connected to output a step value at each step that represents the count of the step, the counting circuit being connected to the second clock circuit to receive the second clock signal; a multiplexer connected to pass either a step value output by the counting circuit or the minimum count value output by the minimum count detector as an output value, the multiplexer being connected to the counting circuit to receive the step value at each step and the minimum count detector to receive the minimum count value; and a digital-to-analog converting circuit connected to convert the output value into the back bias voltage, the digital-to-analog converting circuit being connected to the multiplexer to receive the output value.