Patent ID: 7519645

Claim:
A system for performing a decimal floating point operation, the system comprising: a first register storing a first coefficient and a first exponent; a second register storing a second coefficient and a second exponent; a mechanism including exponent difference circuitry calculating an absolute difference between the first exponent and the second exponent, leading zero detect circuitry connected to the first register and the second register, rotator circuitry connected to the first register, the second register, the exponent difference circuitry and the leading zero detect circuitry, a two cycle adder connected to the first register and the second register, result selector circuitry connected to the two cycle adder, the mechanism: receiving an operation associated with the first operand and the second operand, wherein the operation is an addition or a subtraction; performing three concurrent calculations on the first operand and the second operand, the three concurrent calculations including: applying the operation to the first operand and the second operand based on a first assumption that the first exponent is equal to the second exponent, wherein the applying the operation based on the first assumption results in a first result and includes utilizing the two cycle adder; applying the operation to the first operand and the second operand based on a second assumption that an absolute difference between the first exponent and the second exponent is less than or equal to a number of leading zeros in the coefficient of the operand with the larger exponent, wherein the applying the operation based on the second assumption results in a second result and includes utilizing the exponent difference circuitry, the rotator circuitry, and the two cycle adder; and applying the operation to the first operand and the second operand based on a third assumption that the absolute difference between the first exponent and the second exponent is greater than the number of leading zeros in the coefficient of the operand with the larger exponent, wherein the applying the operation based on the third assumption results in a third result and includes utilizing the exponent difference circuitry, the leading zero detect circuitry, the rotator circuitry, and the two cycle adder; and selecting a final result using the result selector circuitry, the selecting from the first result, the second result and the third result.