Patent ID: 8748282

Claim:
A method of manufacturing a semiconductor device, comprising: stacking, over a semiconductor substrate, an insulating interlayer and a first insulating film in this order; selectively removing said first insulating film and said insulating interlayer in this order, to thereby form a hole as being extended through said first insulating film and said insulating interlayer; allowing side-etching of an inner wall of said hole to proceed specifically in a portion of said insulating interlayer, to thereby form a structure having said first insulating film projected out from the edge towards the center of said hole; forming a lower electrode film as being extended over the top surface, side face and back surface of said first insulating film, and over the inner wall and bottom surface of said hole; filling a protective film in said hole; removing said lower electrode film specifically in portions fallen on the top surface and side face of said first insulating film; removing said protective film; stacking, in said hole and over said lower electrode film, a capacitor insulating film and an upper electrode in this order; patterning said first insulating film, said capacitor insulating film and said upper electrode so as to align an end surface of said first insulating film with an end surface of said capacitor insulating film and with an end surface of said upper electrode; and forming a fourth insulating film on said insulating interlayer and said upper electrode so as to contact with said end surface of said first insulating film, said end surface of said capacitor insulating film and said end surface of said upper electrode.