Patent ID: 7812674

Claim:
A method of protecting a circuit design implemented within an integrated circuit (IC) from electrostatic discharge (ESD), the method comprising: positioning a device array pair comprising a first device array and a second device array on the IC to share a common centroid, wherein the first device array and the second device array are matched; positioning an ESD diode array pair comprising a first ESD diode array and a second ESD diode array on the IC outside and adjacent to a first perimeter encompassing the device array pair, wherein the first ESD diode array and the second ESD diode array share the common centroid and are matched; and coupling a cathode terminal of each ESD diode of the first ESD diode array to an input of the first device array and coupling a cathode terminal of each ESD diode of the second ESD diode array to an input of the second device array.