Patent ID: 8482095

Claim:
A semiconductor device comprising: first, second, third, and fourth high-voltage insulated-gate field-effect transistors arranged on a main surface of a semiconductor substrate, the first and second high-voltage insulated-gate field transistors being adjacent each other in the gate-width direction, the third and fourth high-voltage insulated-gate field transistors being adjacent each other in the gate-width direction, the first and third high-voltage insulated-gate field transistors being adjacent each other in the gate-length direction, the second and fourth high-voltage insulated-gate field transistors being adjacent each other in the gate-length direction, and each of the transistors having a gate electrode, a gate electrode contact formed on the gate electrode; a first wiring layer which is formed on the gate electrode contacts of the first and second transistors; a second wiring layer which is formed on the gate electrode contacts of the third and fourth transistors; and a shielding gate provided on portions of an element isolation region which lie between the first and second transistors, and lie between the third and fourth transistors, and used to apply one of a reference potential and a potential of a polarity different from that of a potential applied to the gates of the transistors to turn on a current path of the transistors to the element isolation region.