Patent ID: 8786108

Claim:
A package structure, comprising: a dielectric layer having a first surface, a second surface opposing the first surface, and a plurality of through holes passing through the first and the second surfaces; a strengthening layer formed on the first surface of the dielectric layer; a circuit layer formed on the second surface of the dielectric layer and having a plurality of wire bonding pads exposed in the through holes and a plurality of ball pads electrically connected to the wire bonding pads; a first solder mask layer formed on the first surface of the dielectric layer and the strengthening layer and having a plurality of first apertures corresponding to the through holes for exposing the wire bonding pads, wherein the strengthening layer is formed between the first surface of the dielectric layer and the first solder mask layer; a second solder mask layer disposed on the second surface of the dielectric layer and the circuit layer and having a plurality of second apertures formed therethrough for exposing the ball pads; and a semiconductor chip disposed on the first solder mask layer, and electrically connected via conductive wires to the wire bonding pads exposed from the through holes.