Patent ID: 7509617

Claim:
A method for generating a design for an FPGA, the design being partially reconfigurable by allowing for at least one relocatable bit stream, the method comprising: specifying given areas of the FPGA where the relocatable bit stream module can be located; verifying that a same relative frame area is available for storing the relocatable bit stream in each of the given areas; generating a list of routing resources available for the relocatable bit stream within each of the given areas, wherein the list has the following parameters: requiring that all entry points to each routing resource listed for a given area exist within a boundary of the given area, requiring that at least one exit point on each routing resource listed for a given area exists within the given area, requiring all the routing resources listed for each of the given areas provide the same connectivity, allowing routing resources that cross a boundary of a given area to be included on the list when an entry point and at least one exit point of the routing resource are located within the given area, excluding each routing resource from the list of routing resources that does not map directly to another routing resource having same connectivity within each of the given areas; and placing and routing the relocatable bit stream using the routing resources listed, wherein when a routing resource that crosses a boundary of a given area is used, the entry point and the exit point of the routing resource are located within the given area.