Patent ID: 8159019

Claim:
A semiconductor memory device comprising: a first active region which is formed in a semiconductor substrate and in which a first MOS transistor that has a stacked gate including a charge storage layer and a control gate is arranged; a second active region which is formed in the semiconductor substrate and in which a second MOS transistor is arranged; a first element isolating region which includes a first insulating film buried in a first trench made in the semiconductor substrate, the first insulating film making contact with the first active region in the sidewall part of the first trench; and a second element isolating region which includes a second insulating film buried in a second trench made in the semiconductor substrate, the second insulating film making contact with the second active region in the sidewall part of the second trench, wherein an impurity concentration of part of the second active region which is in contact with a side face of the second element isolating region is higher than that of a central part of the second active region, and the impurity concentration of part of the first active region which is in contact with a side face of the first element isolating region is equal to that of the first active region.