Patent ID: 8748252

Claim:
A method of fabricating a replacement metal gate transistor, comprising: depositing a dummy gate, wherein the dummy gate comprises an N-type region, a P-type region, and a transition region; depositing a bi-layer over the dummy gate, wherein the bi-layer comprises a first sub-layer comprised of nitride, and a second sub-layer comprised of a first oxide layer; depositing a conformal nitride layer over the dummy gate; forming a first set of spacers adjacent to the dummy gate in the N-type region; forming a second set of spacers adjacent to the dummy gate in the P-type region; depositing a second oxide layer to cover the bi-layer, the first set of spacers, and the second set of spacers; planarizing the second oxide layer to leave a remaining portion with a height at the level of the top of the conformal nitride layer; and recessing the second oxide layer to the level of the first sub-layer of nitride.