Patent ID: 7461213

Claim:
A ring-based communication network based on four or more separate rings configured to transmit a set of packets among a set of elements in an advanced processor system, the advanced processor system including a plurality of processor cores on a chip wherein the set of elements includes at least the plurality of processor cores connected to least one L2 cache, and a memory bridge, the ring-based communication network comprising: a first request ring component configured to pass a first request portion of the set of packets among the set of elements, the first request ring component including, a first request ring input interface, a first request ring output interface, and a first request valid bit input interface, the first request portion of the set of packets containing at least a destination ID, a transaction ID, an address, a request type, and a cacheable indication; a second response ring component configured to pass a second response portion of the set of packets among the set of elements, the second response ring component including, a second response ring input interface, a second response ring output interface, and a second response valid bit input interface; a third data ring component configured to pass a third data portion of the set of packets among the set of elements, the third data ring component including, a third data ring input interface, a third data ring output interface, and a third data valid bit-input interfaces; and a fourth snoop ring component configured to pass a snoop packet among the set of elements, the snoop ring component including, a fourth snoop ring input interface, a fourth snoop ring output interface, and a fourth snoop valid bit input interface, wherein the fourth snoop ring component is configured to provide a snoop based cache coherency by designating an owner of requested data, and wherein each ring component is a ring structure; wherein said memory bridge inspects a success of packet transmission among said plurality of processor cores by examining a status of said request ring, said response ring or said snoop ring, and fetches data requested by request packets from long latency memory and places it on a data packet in said data ring if said packet transmission between cores can not be achieved by said cores interacting with said at least one L2 cache, or writes the data requested to be written by said request packets to the long latency memory if said packet transmission between cores can not be achieved by said cores interacting with said at least one L2 cache.