Patent ID: 8399309

Claim:
A semiconductor device manufacturing method, comprising: a step of, in a first conductivity type silicon wafer wherein the plane orientation of a first main surface is the (100) plane, using a first mask opened by an equal amount on either side of a first central line in places which are to be <110> direction dicing lines, forming a second conductivity type thermal diffusion layer from the first main surface side toward the interior of the silicon wafer; a step of reducing the thickness of the silicon wafer from a second main surface side; a step of forming a second mask opened by an equal amount on either side of a second central line, which is a projection of the first central line on a second main surface of the silicon wafer reduced in thickness, on the second main surface; a step of forming a groove reaching the thermal diffusion layer from the second main surface, using the second mask, by an anisotropic etching with an alkaline solution; a step of carrying out a first ion implantation with a second conductivity type impurity into side wall surfaces of the groove using the second mask; a step of removing the second mask, and carrying out a second ion implantation with the second conductivity type impurity into the second main surface and the side wall surfaces of the groove; and a step of carrying out an annealing process for activating the impurity introduced by the first ion implantation and second ion implantation, and forming an in-groove diffusion layer and a collector layer.