Patent ID: 7082385

Claim:
A method for verifying optimization of processor link for a system comprising a Northbridge, a bus coupled between a CPU and the Northbridge, and a Southbridge, the method comprising the following steps: setting an initial bus width and an initial bus frequency of the bus coupled between the CPU and the Northbridge, wherein the bus operates at the initial bus width and the initial bus frequency; generating a read request to read the Southbridge; outputting a bus disconnection signal by the Southbridge to disconnect the CPU and the Northbridge when the Southbridge receives the read request, initializing a timer for calculating an elapsed time value and outputting an optimization verification signal with a first voltage level; outputting a bus connection signal by the Southbridge when the elapsed time value reaches a predetermined value; transforming the voltage level of the optimization verification signal to a second voltage level according to the bus connection signal; and reconnection of the CPU and the Northbridge by the bus according to the optimization verification signal with the logic level transformed to the second voltage level, wherein the bus operates thereafter at another bus operating bus width and another bus operating frequency.