Patent ID: 8706939

Claim:
An arbiter configured to arbitrate access requests for a memory by a plurality of modules, the arbiter comprising: an issuance unit configured to select and issue one of the access requests in a request queue which may store either a write request or a read request received from the plurality of modules; an estimation unit configured to estimate data amount to be accumulated in a write buffer if write requests in the request queue are executed and amount of free space to be obtained in a read buffer if read requests in the requests queue are executed; a register configured to store a type of access request representing whether a next-previous access request issued from the issuance unit is a read request or a write request; and a determination unit configured to determine the type of the next-previous access request stored in the register, and wherein the issuance unit preferentially selects a write request if the estimated data amount to be accumulated in the write buffer is greater than a first threshold and the next-previous access request is a write request, and selects a read request if the estimated data amount is not greater than the first threshold and the estimated amount of free space to be obtained in the read buffer is greater than a second threshold and the next-previous access request is a read request.