Patent ID: 8581636

Claim:
An arrangement in a sample-and-hold electronic circuit, comprising: an amplifier configured to receive an input signal and to produce an output signal; a controllable sampling switch in communication with the amplifier; a sampling capacitor configured to receive the output signal through the sampling switch when the sampling switch is closed; a boost circuit configured to receive the output signal independent of whether the sampling switch is closed or open and to be in parallel with the sampling capacitor when the sampling switch is closed, wherein the boost circuit comprises: at least one first capacitor-switch arrangement in parallel with at least one second switch-capacitor arrangement, wherein the at least one first capacitor-switch arrangement includes a first capacitor connected in series with a first controllable switch, and the at least one second switch-capacitor arrangement includes a second controllable switch connected in series with a second capacitor; at least one third controllable switch connected between the at least one first capacitor and the at least one second capacitor; and a control circuit configured for generating control signals for the controllable sampling switch and the first, second, and third controllable switches that switch the arrangement between a sampling phase and a holding phase.