Patent ID: 7229904

Claim:
A method for forming landing plug contacts in a semiconductor device, comprising the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the gate structures; planarizing the inter-layer insulation layer and the gate structures for obtaining a uniformly planarized surface of overall regions through a chemical mechanical polishing (CMP) process employing a high selectivity slurry (HSS) until the gate hard mask is exposed; forming a hard mask material on the uniformly planarized surface; forming a hard mask; forming a plurality of contact holes exposing the substrate disposed between the gate structures by etching the planarized inter-layer insulation layer using the gate hard mask and the hard mask as an etch mask; forming a polysilicon layer in the contact holes; and forming landing plug contacts in the contact holes through a planarization process performed to the polysilicon layer until the gate hard mask is exposed.