Patent ID: 7813161

Claim:
A dual port static random access memory (SRAM) having dedicated read and write ports to provide a high speed read operation with a low leakage comprising: at least one write word line; at least one read word line; at least one pair of read and write bit lines; a plurality of rows and columns, each of said rows and columns having at least one cell, the at least one cell comprising: at least one pair of memory elements cross-coupled to form a latch for storing data, a pair of write access transistors connected between said write bit line and a latch output node of said memory element, said pair of write access transistors having a gate terminal connected to said write word line, and a pair of read access transistors connected between said read bit line and a local drive line, said pair of read access transistors having a gate terminal controlled by said latch output node; at least one inverter circuit separate from said at least one pair of memory elements; and a pull down circuit separate from said inverter circuit and from said at least one pair of memory elements, wherein the at least one inverter circuit and pull down circuit are operatively coupled to the least one cell to increase read operation performance with low leakage.