Patent ID: 7685587

Claim:
A computer implemented process for generating a micro-processor instruction set extension for a processor application, comprising: generating a data flow graph G(V,E) of nodes V representing primitive operations of the processor application and edges E representing data dependencies of said application; evaluating subgraphs S of G(V,E) as candidates for an instruction set extension, each said subgraph S having a number of inputs IN(S) and a number of outputs OUT(S), said instruction set extension having a number of available register-file read ports Nin and a number of available register-file write ports Nout; wherein said evaluating a subgraph S includes, if OUT(S) is less than or equal to Nout, and if S is convex, and if IN(S) is less than or equal to Nin, then identifying S as a candidate for transformation into an instruction set extension, else disregarding S as a candidate for transformation into an instruction set extension; wherein S is convex when no path exists from a node in S to another node in S when said path involves a node that is not in S; evaluating said identified candidates using a function M(S) as a measure of merit; transforming said instruction set by adding an instruction set extension representing said identified candidate to said instruction set if said candidate satisfies said function M(S).