Patent ID: 7409529

Claim:
A processing element, comprising: a first circuit coupled to a first sequencer, the first sequencer directing processing of data in the first circuit, and the first circuit comprising: a logic unit, the logic unit having a plurality of inputs and an output, and the logic unit performing logical operations as directed by the first sequencer, and a first multiplexer having a plurality of inputs and an output, one of the plurality of inputs coupled to the output of the logic unit, the output of the first multiplexer coupled to one of the plurality of inputs of the logic unit and to an input of a register file; and a second circuit coupled to a second sequencer, the second sequencer directing movement of data between the processing element and neighboring processing elements, and the second circuit comprising: a first data bus for receiving data from a portion of a main memory associated with the processing element, a second data bus for sending data to the portion of the main memory associated with the processing element, a plurality of internal data buses, each of the plurality of internal data buses having a width of a plurality of bits, and a buffer register having a width of a plurality of bits, the buffer register connected to at least one of the internal data buses, the width of the buffer register being equal to the width of the at least one of the internal data buses, and wherein the buffer register buffers data transfers between the first data bus and the second data bus.