Patent ID: 7506114

Claim:
A data transfer device which controls data transfer between a first memory device and a second memory device, comprising: a first transfer arbiter circuit which outputs, in response to a transfer instruction for transfer of data from the first memory device to the second memory device, first transfer instructions to transfer data in a first transfer unit in an order of addresses; and a second transfer arbiter circuit which outputs, in response to the first transfer instruction, second transfer instructions to transfer the data of the first transfer unit in a second transfer unit smaller than the first transfer unit, the second transfer arbiter circuit outputting the second transfer instruction in an order of accessible addresses in the first and second memory devices; wherein the second transfer arbiter circuit outputs an acknowledge signal after all second transfer instructions are output with respect to one of the data of the first transfer unit, and the first arbiter circuit outputs the first transfer instruction relating to a next address, in response to the acknowledge signal; wherein the first transfer instruction includes a first address which represents a leading address of a memory area in the first memory device, where the data which is to be transferred in the first transfer unit is stored; a second address which represents a leading address of a memory area in the second memory device, where the data which is transferred in the first transfer unit is to be stored; and the first transfer unit, and the second transfer instruction includes a third address which represents a leading address of a memory area in the first memory device, where the data which is to be transferred in the second transfer unit is stored; a fourth address which represents a leading address of a memory area in the second memory device, where the data which is transferred in the second transfer unit is to be stored; and the second transfer unit; and wherein the first transfer arbiter circuit includes a third memory device which stores an address generation program and a first transfer unit table; and a processor which generates the first transfer instruction by calculating the first address, the second address and the first transfer unit on the basis of the address generation program and the first transfer unit table, the first transfer unit table stores a relationship between addresses, which are assigned to the first and second memory devices, and the first transfer units associated with the addresses assigned to the first and second memory devices, the address generation program causes the processor to add the first address and any one of the first transfer units read out of the first transfer unit table to generate a next first address, and the address generation program causes the processor to add the second address and any one of the first transfer units read out of the first transfer unit table to generate a next second address.