Patent ID: 8238502

Claim:
A communication system, comprising: an inter-device communication channel; and first and second devices coupled to one another by the inter-device communication channel and configured to be independently clock, each device including a transmitter, a receiver, and a synchronization block that includes: an input terminal coupled to said receiver of the device; an output terminal coupled to said transmitter of the device; a clock terminal; a test pattern generator structured to generate a test pattern signal; a pattern detector configured to check a matching between a received test pattern signal and a stored test pattern signal, said pattern detector having an input terminal configured to receive the received test pattern signal, a memory configured to store the stored test pattern signal, and an output terminal, the pattern detector being configured to compare the received and stored test pattern signals and lock a clock phase of said synchronization block by providing a first internal check signal indicative of whether the received test pattern signal matches the stored test pattern signal; a comparator having a first input terminal coupled to the output of the pattern detector, a second input terminal configured to receive a reset signal, and an output terminal configured to provide a second internal check signal; a delay block coupled to the clock terminal and structured to change said clock phase of the synchronization block until a synchronized condition of said synchronization blocks is verified, said synchronized condition corresponding to a matching between the stored and received test pattern signals; and a first counter and a second counter coupled, in cascade to each other, between said first input terminal of said comparator and said delay block, the first counter having an enabling terminal coupled to said output terminal of said pattern detector and configured to receive said first internal check signal from said pattern detector.