Patent ID: 7329582

Claim:
A method for fabricating a semiconductor device in and on a silicon substrate comprising the steps of: forming a gate electrode overlying the silicon substrate; ion implanting conductivity determining dopant ions to form a shallow source region and a shallow drain region in the semiconductor substrate, the shallow source region and the shallow drain region self aligned with the gate electrode; forming a layer of metal silicide on each of the shallow source region and the shallow drain region; electrolessly depositing a layer of metal on the layer of metal silicide to form a first metal contact in electrical contact with the shallow source region and a second metal contact in electrical contact with the shallow drain region; depositing a dielectric layer overlying the first metal contact and the second metal contact; etching a first opening through the dielectric layer to expose a portion of the first metal contact and a second opening through the dielectric layer to expose a portion of the second metal contact; and electrolessly depositing an electrically conductive material to fill the first opening and the second opening by a process of selective deposition nucleated on the first metal contact and the second metal contact.