Patent ID: 8319353

Claim:
An apparatus comprising: a microelectronic die, wherein the microelectronic die includes a conductive bump formed on a bonding pad, the bonding pad not having been probed prior to the conductive bump being formed on the bonding pad, and an insulating layer formed on at least a portion of a surface of the conductive bump; and a carrier structure wire-bonded to the conductive bump, wherein, prior to probing the conductive bump to test functionality of the microelectronic die, each of (i) the insulating layer and (ii) the conductive bump are planarized to remove material from each of the insulating layer and the conductive bump, and wherein each of (i) the insulating layer and (ii) the conductive bump are planarized such that a top surface of the insulating layer is substantially co-planar with a top surface of the conductive bump.