Patent ID: 7592667

Claim:
A semiconductor device, comprising: a semiconductor substrate; a nonvolatile memory cell including a first MOS transistor having a first gate formed on the semiconductor substrate, the first gate being a layered gate structure having a first gate insulating film, a first gate electrode film, a second gate insulating film, a second gate electrode film, and a source and a drain formed in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the first gate, and a logic circuit including a plurality of second MOS transistors, each of the second MOS transistors having a second gate formed on the semiconductor substrate, the second gate being a gate structure having a third gate insulating film and said second gate electrode film, and a source and a drain formed in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the second gate, the plurality of second MOS transistor including at least a second MOS transistor having a third gate insulating film of a first thickness, a second MOS transistor having a third gate insulating film of a second thickness and a second MOS transistor having a third gate insulating film of a third thickness; wherein the first thickness is thicker than the second thickness and the second thickness is thicker than the third thickness, and a thickness of the second gate insulating film is thicker than the second thickness and thinner than the first thickness.