Patent ID: 7509446

Claim:
An IIC bus communication system comprising: two bus lines including a SCL (serial clock) line and a SDA (serial data) line; multiple master devices connected in parallel to the bus lines; a state detector for detecting a frozen state of an IIC bus communication on the basis of the states of the SCL line and the SDA line so as to output a freeze detection signal, and detecting the state where the frozen state is released so as to output a freeze-release detection signal; a pulse generator for supplying a pulse signal corresponding to a clock signal with respect to the SCL line in accordance with the freeze detection signal outputted from the state detector; and a reset signal generator for supplying a reset signal to the multiple master devices in accordance with the freeze-release detection signal outputted from the state detector, wherein the multiple master devices return to a normal communication state in accordance with the supply of the reset signal.