Patent ID: 8404497

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing an assembly including a wiring substrate having an upper surface, a first electrode pad formed on the upper surface, a second electrode pad formed on the upper surface, a lower surface opposed to the upper surface, a first land formed on the lower surface and coupled with the first electrode pad, a second land formed on the lower surface and coupled with the second electrode pad, and a conductive member formed on the first land serving as an external terminal, and a semiconductor chip mounted over the upper surface of the wiring substrate, the second land having a diameter larger than the diameter of the first land; and (b) placing the assembly into a probe socket, and contacting a first contact pin of the probe socket with the conductive member, and contacting a second contact pin of the probe socket with the second land, and performing electrical characteristic tests for the assembly, wherein the conductive member is not contacted with the second land and the second land is used only for performing electrical characteristic tests for the semiconductor device.