Patent ID: 7510912

Claim:
A method of making a wirebond electronic package, said method comprising: providing an organic laminate substrate having an external surface; forming an electrically conductive circuit on said external surface of said organic laminate substrate including a plurality of wirebond pads; forming a pattern of thermally conductive material on said external surface of said organic laminate relative to said wirebond pads of said electrical circuit, said pattern of thermally conductive material including a plurality of substantially concentric, spaced-apart lines; positioning a semiconductor chip on said external surface of said organic laminate substrate and bonding said semiconductor chip to said external surface of said organic laminate substrate and said plurality of substantially concentric, spaced-apart lines of said pattern of thermally conductive material such that said semiconductor chip is thermally coupled to said plurality of concentric, spaced-apart lines of said pattern of thermally conductive material; and electrically connecting said semiconductor chip to said plurality of said wirebond pads.