Patent ID: 7074670

Claim:
A method of forming a storage node of capacitor, the method comprising: sequentially forming a second interlayer insulation layer, an etching stop layer, and a mold layer on a semiconductor substrate, a lower structure of which includes a bit line pattern and a conductive region, said conductive region being formed in a first interlayer insulation layer to be connected with a capacitor storage node; partially etching the mold layer until a top surface of the etching stop layer is exposed; partially removing the exposed portion of the etching stop layer and also an upper portion of the second interlayer insulating layer, thereby forming a first aperture part that exposes a portion of the conductive region; etching the portion of the conductive region exposed in the first aperture part to form a second aperture part; and depositing a conductive layer on sidewalls of the first and second aperture parts to form the capacitor storage node.