Patent ID: 7730227

Claim:
A system for managing I/O traffic in a multi-bus environment, comprising: a communication bus configured to support a plurality of physically different bus structures coupled to a device and to a circuit having a plurality of physically shared bus pins, including control pins, address pins, and data pins; an address map block configured to receive a communication request from the device and to match an address of the device to respective physically different bus structures; a state machine coupled to the address map block to change the functionality of the plurality of physically shared bus pins, including control pins, address pins, and data pins based on the respective physically different bus structures, wherein a change in functionality of each of the plurality of physically shared bus pins can reconfigure a control pin to be an address pin or a data pin, or vice versa, and can reconfigure an address pin to be a data pin or vice versa; and a bus arbitration circuit coupled to the state machine and adapted to grant the device ownership of the plurality of physically shared control pins, address pins, and data pins once the functionality changes are completed.