Patent ID: 7956948

Claim:
A pixel structure, formed on a substrate and electrically connected with a scan line and a data line, the pixel structure comprising: a semiconductor pattern, comprising: at least two channel areas, located below the scan line, each of the two channel areas is a region of the semiconductor pattern overlapping with the scan line, and the two channel areas having different aspect ratios; at least one doping area, connected between the channel areas; a source area and a drain area; and a pixel electrode, electrically connected with the drain area, wherein the source area is connected between the data line and one of the two channel areas, and the drain area is connected between the pixel electrode and the other of the two channel areas, wherein the scan line overlapping with different channel areas has two different widths including a first width and a second width, a length of one of the channel areas is substantially equal to the first width, and a length of the other one of the channel areas is substantially equal to the second width.