Patent ID: 7558902

Claim:
An integrated circuit for interconnecting a serial digital bus with a microcontroller unit, comprising: a first interface providing a physical layer connection between the integrated circuit and the microcontroller unit enabling data to be transmitted between the integrated circuit and the microcontroller unit; a second interface providing a physical layer connection between the integrated circuit and the serial digital bus enabling data to be transmitted between the integrated circuit and the serial digital bus; wherein the second interface further comprises: a physical interface for transmitting messages onto the serial digital bus and for receiving messages from the serial digital bus; wherein the first interface further comprises: a communication interface including a serial interface for communicating with the microcontroller unit, said communication interface further for extracting clock data and information data from the received messages from the serial digital bus in a format that may be transmitted to the microcontroller unit via the serial interface, said communication interface further for formatting data received from the serial interface into messages for transmission onto the serial digital bus; wherein the communications interface further comprises: a clock/data recovery and flow control block for extracting the clock data and the information data from the received messages from the serial data bus, for extracting a serial data sync edge from the received messages and for inhibiting the serial interface when no received messages from the serial digital bus are present; a clock and data formatter block for formatting data received from the serial interface into a message for transmission onto the serial digital bus; and a sync timing generator for generating a sync pulse for synchronizing all timing operations of the microcontroller unit with a timing provided by the serial bus.