Patent ID: 7219251

Claim:
A programmable synchronizer system for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising: a first synchronizer controller circuit operating in said first clock domain responsive to a SYNC pulse that is sampled in said first clock domain; a configuration interface for configuring said first synchronizer controller circuit to compensate for at least one of a variable skew factor and a variable latency factor associated with said first clock signal; and a second synchronizer controller circuit operating in said second clock domain responsive to said SYNC pulse that is sampled in said second clock domain, said second synchronizer controller circuit operating to generate a plurality of inter-controller control signals towards said first synchronizer controller circuit, wherein each of said first and second synchronizer controller circuits generates a set of synchronizer control signals, a portion of which signals are provided to a first synchronizer operating to control data transfer from said first circuitry to said second circuitry and a portion of which signals are provided to a second synchronizer operating to control data transfer from said second circuitry to said first circuitry.