Patent ID: 8274819

Claim:
An SMT MRAM memory device comprising: an array of SMT MRAM cells arranged in rows and columns; a plurality of sense amplifiers, wherein each sense amplifier is in communication with one of the columns of SMT MRAM cells to sense a read data current to determine a data state of selected SMT MRAM cells; a read reference circuit to provide a read reference current to sense amplifiers for reading a data state from selected SMT MRAM cells of the array, wherein the read reference circuit comprises: at least two columns of reference SMT MRAM cells appended to the array of SMT MRAM cells with a word line connected to each row of the array of the SMT MRAM cells connected to an associated row of the reference SMT MRAM cells, where the reference SMT MRAM cells of a first of the two columns are programmed to have a maximum resistance of a first data state and the reference SMT MRAM cells of a second of the two columns are programmed to have a minimum resistance of a second data state, wherein a true bit line of the first column of reference SMT MRAM cells is connected to the complement bit line of the second column of reference SMT MRAM cells such that the read reference circuits will not be disturbed during the reading of the data state from the selected SMT MRAM cells.