Patent ID: 6992911

Claim:
A semiconductor memory device comprising: a first bit line; a memory cell formed of a first transistor connected to the first bit line and a first ferroelectric capacitor connected to the first transistor; a second bit line; a first reference cell formed of a second transistor connected to the second bit line and to a first word line to be controlled and a second ferroelectric capacitor connected to the second transistor, the first reference cell holding a potential corresponding to predetermined data; a third bit line; a second reference cell formed of a third transistor connected to the third bit line and to the first word line to be controlled and a third ferroelectric capacitor connected to the third transistor, the second reference cell holding a potential corresponding to predetermined data; a first redundant reference cell formed of a fourth transistor connected to the second bit line and to a second word line to be controlled and a fourth ferroelectric capacitor connected to the fourth transistor, the first redundant reference cell holding a potential corresponding to predetermined data; a second redundant reference cell formed of a fifth transistor connected to the third bit line and to the second word line to be connected and a fifth ferroelectric capacitor connected to the fifth transistor, the second redundant reference cell holding a potential corresponding to predetermined data; a switching circuit connected between the second bit line and the third bit line, the switching circuit electrically connecting the second bit line to the third bit line in response to a first control signal and generating a reference potential in the second bit line and the third bit line; a data read-out circuit connected to any one of the second bit line and the third bit line and to the first bit line so as to compare the reference potential with a potential generated in the first bit line; and a word line select circuit selecting any one of the first word line and the second word line and generating the reference potential in the second bit line and the third bit line by the first and second redundant reference cells by selecting the second word line when the first or second reference cell is defective.