Patent ID: 8036049

Claim:
A semiconductor memory device, comprising: a first input/output sense amplifying group which amplifies data provided from a first bank group in a read operation and transfers it to a first global input/output line; a second input/output sense amplifying group which amplifies data provided from a second bank group in the read operation and transfers it to a second global input/output line; a first write driver group which amplifies data provided from the first global input/output line in a write operation and transfer it to any one pair of a plurality of local input/output line pairs; a second write driver group which amplifies data provided from the second global input/output line in the write operation and transfers it to any one pair of a plurality of local input/output line pairs; and a data transferring unit configured to transfer data between the first bank group and the first global input/output line when the first bank group is selected, and transfer data between the second bank group and the second global input/output line when the second bank group is selected, in response to command and address input in the read and write operations, wherein the data transferring unit comprises: a controller which generates control signals corresponding to command and address input in the read and write operations, the controller comprises: a read controller which outputs a first control signal controlling selection of the first global input/output line and a second signal controlling selection of the second global input/output line in the read operation, as first and second read strobe signals generated in the read operation; and a write controller which outputs a third control signal controlling selection of the first global input/output line and a fourth control signal controlling selection of the second global input/output line in the write operation, as a data input strobe signal and a bank control signal generated in the write operation.