Patent ID: 7894491

Claim:
A method of allowing data and transmit de-emphasis codes to be conveyed across an interface at different bit rates in multiple channels in a processor comprising: receiving a data stream in a form of n-bit words into a first register at a first clock frequency f 1 ; loading first n/2 bit words from the first register into a shift register at a second clock frequency f 2 , wherein the second clock frequency f 2 is equal to 2*f 1 , wherein one or more of the first n/2 bit words loaded into the shift register are shifted by n/2 bits at the second clock frequency f 2 ; selecting outputs in parallel from the shift register such that two or more second n/2 bit words are stored in two or more n/2 bit latches, wherein the outputs of the two or more n/2 bit latches are connected to the multiple channels; connecting a multiple channel from the multiple channels to the interface at a clock frequency f 3 until all of the multiple channels have been connected to the interface, wherein the clock frequency f 3 is equal to 8*f 1 ; wherein n is an even integer value equal to or greater than 2.