Patent ID: 8234326

Claim:
A processor core to execute an instruction to perform both vector and single value multiplication, comprising: a plurality of general purpose registers; an accumulation register; and an execution unit, coupled to the general purpose registers and the accumulation register that includes: a partial product generator that generates a plurality of first partial products and a plurality of second partial products given a first input and a second input, a first adder array, coupled to the partial product generator, that generates a first result for the plurality of first partial products; a second adder array, configured in parallel with the first adder array, coupled to the partial product generator, that generates a second result for the plurality of second partial products; and a combiner, coupled to the first adder array and the second adder array, that generates a final result based on the first result and the second result, wherein if the first input and the second input represent single values, the partial product generator assigns a value of zero only to either a most significant partial product of the plurality of second partial products or to a least significant partial product of the plurality of first partial products.