Patent ID: 8877594

Claim:
A method for fabricating a CMOS device for reducing a radiation-induced charge collection, comprising: 1) providing a semiconductor substrate; 2) thermally growing a silicon dioxide layer on the substrate as a buffer layer and depositing a silicon nitride layer; defining a field region by photolithography technology and etching the silicon nitride layer by reactive ion etching; performing an implantation for the field region; depositing a silicon dioxide layer and a barrier layer and planarizing a resultant surface by chemical-mechanical polishing to form a device isolation region; 3) performing a cleaning; after the cleaning, growing a gate dielectric layer and depositing a gate electrode layer; defining a gate pattern by photolithography technology, etching the gate electrode layer and the gate dielectric layer outside the pattern to form a gate region; and performing an implantation for a LDD region to form the LDD region; 4) depositing a silicon oxide layer or a silicon nitride layer and anisotropically etching the silicon oxide layer or the silicon nitride layer to form a gate sidewall; 5) depositing a barrier layer and anisotropically etching the barrier layer to form a barrier layer sidewall; 6) performing a heavily-doped ion implantation to form a charge collection-suppressed region; 7) etching the barrier layer sidewall, performing implantation for a source region and a drain region with impurities, wherein the source region and the drain region have implantation depths less than that of the heavily doped charge collection-suppressed region and have doping types opposite to that of the charge collection-suppressed region, and activating the impurities by rapid annealing technology to form the source region and the drain region.