Patent ID: 8115500

Claim:
A test structure formed on a semiconductor substrate for measuring the parasitic capacitance between a via and adjacent conductive features of a semiconductive device, said test structure comprising: said semiconductor substrate; a first conductive element having a first regularly repeating pattern, formed in a first metal layer over the substrate; a second conductive element having a second regularly repeating pattern, formed in the first metal layer over the substrate and electrically isolated from the first conductive element; a third conductive element, having a third regularly repeating pattern, formed in a second metal layer over the substrate; a fourth conductive element, having a fourth regularly repeating pattern, formed in the second metal layer and electrically isolated from the third conductive element, wherein said respective first, second, third, and fourth regularly repeating patterns comprise a comb structure; a first pattern of regularly spaced vias electrically connecting the first and fourth conductive elements; and a second pattern of regularly spaced vias electrically connecting the second and third conductive elements.