Patent ID: 8367492

Claim:
A method comprising: forming on a semiconductor substrate a nanowire first channel for a n-FET device having a first crystal orientation along a length of the first channel and a first thickness t C1 ; forming a nanowire second channel for a p-FET device having a second crystal orientation along a length of the second channel and a second thickness t C2 ; disposing over a surface of the first nanowire a gate dielectric and a gate having a thickness t G1 and made of materials selected to impose a net tensile force on the surface of the first nanowire; and disposing over a surface of the second nanowire a gate dielectric and a gate having a thickness t G2 and made of materials selected to impose a net compressive force on the surface of the second nanowire; wherein the first crystal orientation is selected such that the net tensile force operates to increase mobility of charge carriers along the length of the first nanowire; and wherein the second crystal orientation is selected such that the net compressive force operates to increase mobility of charge carriers along the length of the second nanowire; wherein the first crystal orientation is substantially along the <100> Miller index and the second orientation is substantially along a <110> Miller index.