Patent ID: 8901638

Claim:
A trench-gate semiconductor device comprising a semiconductor body having a major surface defining a plane, a trench extending into the semiconductor from the major surface and having sidewalls and having therein a conductive gate and a field plate, the conductive gate having a bottom level which is a first distance from the plane, the conductive gate being spaced apart from the sidewalls by a first gate oxide layer of a first thickness, the field plate being more remote from the plane than is the conductive gate, and being spaced apart from the sidewalls by a second gate oxide layer of a second thickness which is thicker than the first thickness, a first region of a first conductivity type adjacent the trench at the major surface, a second region of the first conductivity type and having a first doping level of a first dopant and spaced apart from the first region by a gap, wherein the second region comprises an epitaxial silicon layer, and wherein the doping of the epitaxial silicon layer is linearly or exponentially graded, and a channel-accommodating region of a second conductivity type therebetween filling the gap, the channel-accommodating region having a first layer which has a second doping level of a second dopant and a second layer which is more remote from the surface than the first layer and which has a third doping level of a third dopant, the first layer being adjacent the second layer adjacent the trench at a second distance from the plane which is less than the first distance, the channel-accommodating region being adjacent the second region and at a third distance that is measured from the plane to a bottom level of the second layer of the channel-accommodating region, wherein the field plate has a top level that is at a fourth distance from the plane and a bottom level that is at a fifth distance from the plane, and wherein the third distance is greater than the fourth distance but less than the fifth distance, wherein the channel-accommodating region is adjacent the trench across the whole of the gap, the third distance is greater than the first distance, and the third doping level is such that, in operation, when a reverse bias is applied across the trench-gate semiconductor device, at least 30% of the bias is across the channel accommodating region.