Patent ID: 7995379

Claim:
A semiconductor memory device comprising: a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other; a first metal oxide semiconductor field effect transistor (MOSFET) having a drain terminal connected with the first node; a second MOSFET having a drain terminal connected with the second node; a memory cell connected with a source terminal of the first MOSFET; a reference cell; and a connection control circuit that connects a source terminal of the second MOSFET with the reference cell during a regular operation and connects the source terminal of the second MOSFET with a reference voltage terminal during a test operation, wherein during a test operation of the memory cell, the semiconductor memory device supplies a test current that differs from a current during the regular operation to the second node by controlling a voltage of a gate terminal of the second MOSFET and compares the test current with a current that reflects a resistance state of the memory cell and is supplied to the first node.