Patent ID: 7694004

Claim:
A computer comprising: a processor subsystem; a device which transfers data to or from said processor subsystem; and a controller connected between said device and said processor subsystem and adapted to control the transfer of data between said device and said processor subsystem, said controller executing a method comprising, receiving a data value of a write directed to a control register in the controller, interpreting bits of the data value as a data field, the number of bits in the data field being equal to the number of bits in the control register in the controller and bit locations in the data field corresponding respectively to bit locations in the control register; interpreting bits of the data value as enable bits in a bit enable field, the number of enable bits in the bit enable field being equal to the number of bits in the control register and bit locations in the bit enable field corresponding respectively to bit locations in the control register; and overwriting only the bits at the bit locations of the control register for which the enable bit in the corresponding location in the bit enable field is set with the bit in the corresponding location in the data field, wherein the processor subsystem is to post an entire command sequence in the controller for setting up an IDE (integrated drive electronics) data transfer.