Patent ID: 7684272

Claim:
A semiconductor memory device, comprising: a first memory cell array; a sense amplifier that reads and writes data from and to the first memory cell array; a first pair of bit lines connected to the sense amplifier; a second pair of bit lines connected to the first memory cell array; a first transfer switch provided between the first pair of bit lines and the second pair of bit lines; a first precharge circuit connected to the second pair of bit lines and that precharges the first pair of bit lines and the second pair of bit lines at the same potential; and a control circuit that controls at least the sense amplifier, the first memory cell array, the first transfer switch, and the first precharge circuit, wherein, before the reading or writing data, the control circuit controls the first transfer switch to be in a nonconductive state and controls the first precharge circuit to be in an active state to set the first pair of bit lines to a first predetermined potential and, via the first precharge circuit, to set the second pair of bit lines to a second predetermined potential different from the first predetermined potential, and wherein, when data is to be written or read via the first and second pairs of bit lines, the control circuit first controls the first transfer switch to be in a conductive state to set the first pair of bit lines to the second predetermined potential via the first precharge circuit, second controls the first precharge circuit to switch from the active state to an inactive state, and third controls the first memory cell array to be in an active state and the sense amplifier to be in an active state.