Patent ID: 8477535

Claim:
A semiconductor device comprising: a memory array having a plurality of memory cells provided therein each having a transistor with a variable threshold voltage, the memory cells included in the memory array being grouped into a plurality of twin cells each having two memory cells, each of the twin cells storing complementary data, with the threshold voltage of one memory cell being set higher than that of the other memory cell; a selection circuit which selects a plurality of selected twin cells forming a part of the twin cells; a first determination unit which determines, for each of the selected twin cells, whether or not a first condition that the threshold voltage of one memory cell is higher than a reference value commonly set for the selected twin cells and the threshold voltage of the other memory cell is lower than the reference value is satisfied; a second determination unit which determines whether or not a second condition that all the selected twin cells satisfy the first condition is satisfied; and a third determination unit which determines, based on the determination result of the second determination unit, whether or not each of the selected twin cells is in a blank state in which no complementary data is stored.