Patent ID: 8369134

Claim:
A memory device, comprising: first and second cross-coupled inverters, the first inverter having a first ground node and the second inverter having a second ground node different than the first ground node; first and second access transistors coupled to an input node of the second inverter; and at least one control circuit configured for providing a first reference voltage at the first ground node of the first inverter and a second reference voltage at the second ground node of the second inverter and selectively adjusting a difference between the first reference voltage and the second reference voltage, wherein the first access transistor is configured to conduct current from a first bit line to the input node and to be substantially incapable of conducting current from the input node to the first bit line, and wherein the second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to be substantially incapable of conducting current from the one of the first and the second bit lines to the input node.