Patent ID: 7436707

Claim:
A method of operating a flash memory cell structure, the flash memory cell structure comprising a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region, the substrate having a stacked gate including a control gate, the select gate being formed on the substrate and adjacent to a side of the stacked gate, the first-type doped region being located in the substrate and adjacent to the select gate as a drain, the shallow second-type doped region surrounding the first-type doped region and being short-circuited to the shallow second-type doped region, the doped source being located on a side of the shallow second-type doped region as a source, the method comprising: applying a high voltage to the control gate, applying a voltage relatively lower than the voltage applied to the control gate to the drain, floating the source, and grounding the select gate in a programming process; applying a low voltage to the control gate, applying a voltage relatively higher than the voltage applied to the control gate to the select gate, and floating the source and the drain in an erasing process; and applying a word line voltage to the control gate, applying a voltage relatively lower than the word line voltage to the source, grounding the drain, and applying a power voltage to the select gate in a reading process.