Patent ID: 7436227

Claim:
An apparatus comprising: a phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a controllable oscillator circuit, and a feedback divider circuit; a control loop circuit configured to be selectively coupled to supply a control value to the feedback divider circuit to thereby control the oscillator output signal; a nonvolatile storage; wherein while the control loop circuit is not coupled to control the PLL circuit, the PLL circuit is coupled to receive a digital control value as the control value to control a divide ratio of the feedback divider, the digital control value being determined at least in part according to a stored control value stored in the nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal; and wherein, while the control loop circuit is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between a feedback signal coupled to the oscillator circuit and a reference signal coupled to an input of the control loop circuit.