Patent ID: 8105856

Claim:
A method of manufacturing a semiconductor device, comprising: providing a semiconductor wafer comprising a first die and a second die, a top surface of the wafer being covered by a first insulation film, a first top wiring portion and a second top wiring portion being formed on the first insulation film so that the first and second top wiring portions are disposed above the first and second dice, respectively, the first top wiring portion being physically separated from the second top wiring portion and the first insulation film existing between the first top wiring portion and the second top wiring portion; bonding a holding member to the wafer so that the holding member faces the top surface of the wafer; etching a back surface of the wafer held by the holding member along a border between the first and second dice to expose a side surface and a back surface of the first die and a side surface and a back surface of the second die; forming a second insulation film on the exposed side surfaces and back surfaces of the first and second dice; forming a first bottom wiring portion on the second insulation film so that the first bottom wiring portion is physically in contact with the first top wiring portion and extends to the back surface of the first die; forming a second bottom wiring portion on the second insulation film so that the second bottom wiring portion is physically in contact with the second top wiring portion and extends to the back surface of the second die; forming a first conductive terminal on the first bottom wiring portion and forming a second conductive terminal on the second bottom wiring portion; and separating the first and second dice by cutting the holding member to produce the first semiconductor device comprising the first top and bottom wiring portions and a cut holding member and a second semiconductor device comprising the second top and bottom wiring portions and another cut holding member, wherein the forming of the first and second bottom wiring portions comprises exposing a back surface of each of the first and second top wiring portions and connecting the first and second bottom wiring portions to corresponding exposed back surfaces of the first and second top wiring portions, the exposed back surfaces of the first and second top wiring portions being on a plane of the top surface of the wafer.