Patent ID: 7734861

Claim:
A non-volatile flash memory chip, comprising: a memory array organized into a plurality of pages of storage units, each page of storage units being programmed or read together; a code stored in a hidden area, said code being a plurality of pseudo random bits, each bit of the plurality of bits defining whether encoding of data of a page of the plurality is to be inverted or remain as is; a controller for controlling memory operations on the memory array, said controller operations include: transferring the code from the non volatile memory chip to a register on chip allocated to store the plurality of bits of the code; assigning each of bits in the register to a page address of a page of the plurality of pages; and upon receiving a user command to program or read user data in the non volatile memory chip, triggering application of the code to a block of the user data to randomize the encoding of the user data, each of the bits of the code determining whether a corresponding group of one or more pages of the block is stored as is or is inverted prior to being stored, and wherein the code is stored in the non volatile memory chip along with the corresponding group.