Patent ID: 7962725

Claim:
A method of pre-decoding an instruction in a processor, comprising: identifying a property of a first instruction wherein the property is different from other properties encoded in a first set of pre-decode bits for which all available encodings are defined or reserved; encoding the first instruction in a second format having a different length than a first format including a first instruction portion and the first set of pre-decode bits, the second format including a second instruction portion and a second set of pre-decode bits for which all available encodings of the second set of pre-decode bits are not defined or reserved; encoding the second set of pre-decode bits using one of the available encodings not defined or reserved in the second set of pre-decode bits to identify the property of the first instruction; and writing to a storage location the first instruction encoded in the second format including the encoded second set of pre-decode bits instead of the first instruction encoded in the first format wherein the first instruction in the second format, when fetched for execution, will cause an exception; and wherein the first instruction is undefined.