Patent ID: 7873757

Claim:
A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations, said plurality of data sources and data destinations communicating with said direct memory access controller via a plurality of channels, said direct memory access controller further communicating with a memory and a processor, said memory being adapted to store two sets of control data for each of said plurality of channels and for said processor, said direct memory access controller comprising: means for receiving a data transfer request from at least one of said plurality of channels and from said processor; means for accessing at least one set of corresponding control data stored in said memory; means for performing at least a portion of said data transfer requested in dependence upon said accessed control data; and an indicator store for each of said plurality of channels and processor, said indicator store comprising an indicator bit indicating which of said two sets of control data is to be accessed, said direct memory access controller configured to toggle said indicator bit following completion of at least a portion of said data transfer controlled by said one set of control data, said direct memory access controller being adapted to perform all of said data transfer in dependence upon said one set of control data and to access the other of said two sets of control data in response to a subsequent data transfer request from a same channel or processor, wherein said direct memory access controller is responsive to completion of a data transfer controlled by said one set of control data to issue an interrupt to said processor to request that said one set of control data is updated, and is responsive to said subsequent data transfer request to access said other set of control data and to perform a further data transfer controlled by said other set of control data, and following completion of said further data transfer to issue an interrupt to said processor to request that said other set of control data is updated, and in response to a further data transfer request from a same channel or processor to access said one set of control data if it has been updated and to commence said further data transfer under control of said one set of control data, and if said one set of control data is detected as not being updated to halt said further data transfer.