Patent ID: 8085609

Claim:
A nonvolatile semiconductor memory comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of word lines, each being commonly connected to respective gates of memory cells arranged in one of the rows; a plurality of bit lines commonly connected to respective sources of memory cells arranged in one of the columns; a drain voltage generator that provides a drain voltage to respective drains of the plurality of memory cell; a row decoder that selects one of the plurality of word lines; a column decoder that selects one of the plurality of bit lines; a sense amplifier that outputs data based on comparison of a cell current from a memory cell corresponding to the selections by the row and column decoders with a reference current; and a mode selector that outputs either a normal mode signal or a test mode signal according to a mode selection instruction, wherein the row decoder provides a normal mode voltage to the selected word line according to the normal mode signal and provides a test mode voltage lower than the normal mode voltage to the selected word line according to the test mode signal.