Patent ID: 7804890

Claim:
A circuit to facilitate deterministic operation of an integrated device comprising: a counter circuit to generate a first control signal to have a periodic pulse based on a training sequence length of a data packet, the first control signal to be used to synchronize a state machine during a transition from a detect state to a polling state; a circuit to generate a second control signal to add latency to incoming data such that an overall latency is of a predetermined amount; generating a deterministic response for the integrated device to any applied test vectors based on the first and second control signals; wherein the first control signal and the second control signal are generated based on a signal from a phase-locked loop (PLL) and a reset deassertion as sampled by a reference clock; and further wherein the first control signal based on a reset condition, wherein the synchronizing event is based on a predetermined time after the reset condition that is based on a training sequence length.