Patent ID: 7480882

Claim:
A method for measuring and predicting reliability of a VLSI chip, said method comprising: running a plurality of selective signature shmoo tests on said VLSI chip; determining a first plurality of top critical paths based on a first selective signature shmoo test of said plurality of selective signature shmoo tests; wherein there are a predetermined number of critical paths in said first plurality of top critical paths; ordering a first critical path in said first plurality of top critical paths based on a first timing of said first critical path and assigning a first critical path order to said first critical path; storing said first plurality of top critical paths; wherein if said storing step is done off-chip, said first plurality of top critical paths are recorded in a storage media; wherein if said storing step is done on-chip, said plurality of top critical paths are recorded in one or more critical path registers on said VLSI chip; determining a second plurality of top critical paths based on a second selective signature shmoo test of said plurality of selective signature shmoo tests; wherein said second selective signature shmoo test is performed in a field after a cycle time proceeding said first selective signature shmoo test; ordering each second critical path in said second plurality of top critical paths based on a second timing of said second critical path and assigning a second critical path order to said second critical path; comparing said second plurality of top critical paths with said first plurality of top critical paths; if in said comparing step, said second critical path order is the same as said first critical path order, and said second critical path is not the same as said first critical path, then reporting a change in critical path order of said first critical path and a potential reliability issue; if in said comparing step, said second critical path order is the same as said first critical path order, said second critical path is the same as said first critical path, and said first timing is more than said second timing by more than a time degradation threshold value, then reporting an increase in timing of said first critical path and a potential reliability issue; wherein said plurality of selective signature shmoo tests are performed using a level sensitive scan design and testing methodology; wherein said VLSI chip has a logic-built-in-self-test feature; and wherein said logic-built-in-self-test feature comprises one or more latches and one or more registers, concatenated in one or more scan chains, accessible via one or more serial inputs and one or more serial outputs, a linear feedback shift register generating one or more pseudo-random patterns, a control logic to select a set of said one or more latches and test results from said set of said one or more latches associated with a selective signature for collection into a multiple-input-signature register, and said multiple-input-signature register.