Patent ID: 6977605

Claim:
A delay locked loop clock generation circuit comprising: (a) a delay locked loop circuit including i. a delay line including a plurality of serially connected delay stages, a first delay stage being connected to receive a first clock signal, each of the delay stages having a delay control input connected to receive a delay control signal, various tap points of the delay line being coupled to inputs of a clock logic circuit operating on various tap point signals conducted by the various tap points, respectively, to generate a plurality of clock signals, ii. a phase detector having a first input connected to receive the first clock signal, a second input connected to an output of a final delay stage of the delay line, and an output, and iii. a delay control circuit having an input connected to the output of the phase detector and an output producing the delay control signal; (b) a dummy delay line including a delay line including a plurality of serially connected dummy delay stages that are matched to corresponding delay stages of the delay line, respectively, a first dummy delay stage being connected to receive a second clock signal which is inverted with respect to the first clock signal, each of the dummy delay stages having a delay control input connected to receive the delay control signal; and (c) a watchdog circuit having a plurality of inputs coupled to various tap points of the dummy delay line to generate a first control signal coupled to the phase detector and a second control signal coupled to the delay control circuit, wherein corresponding delay stages and dummy delay stages are located physically close to each other in a substrate of an integrated circuit chip and co-act to cancel noise injected into the substrate as a result of switching of the delay stages.