Patent ID: 8151042

Claim:
A memory controller in a memory system, the memory controller comprising: a first mechanism for receiving data packets at indeterminate times via an upstream channel, the first mechanism comprising a means for identifying bits received via the upstream channel as corresponding to a received data packet; and a second mechanism including instructions for facilitating: determining if the received data packet is in response to a request from the memory controller, wherein input to the determining includes an upstream identification tag included in the received data packet, the upstream identification tag comprising at least one bit indicating that the received data packet is in response to a request from the memory controller or indicating that the received data packet is not in response to a request from the memory controller; determining if the received data packet is a partial response and that additional data related to the received data packet will be transferred in subsequent data packets, the determining responsive to inspecting a continuation bit in the received data packet; and matching the received data packet to the request responsive to determining that the received data packet is in response to a request from the memory controller.