Patent ID: 7954018

Claim:
A multi-level memory defect analysis system to analyze failed bits in multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits, comprising: a memory tester that tests multi-level memory cells from memory chips to provide a defect data set that includes one or more failed bits, wherein each multi-level memory cell stores an energy level representing two or more bits, each bit comprising two states; and a computer configured: to analyze the defect data set to generate, for each failed multi-level memory cell, a failed bit location and one or more fail states for the failed bit; and to classify a vertical fail pattern that indicates for each multi-level memory cell which of each of the two states for each bit of the multi-level memory cell comprises a fail state; whereby after being classified, each vertical fail pattern has three data attributes comprising a vertical fail pattern class, a number of failed bits or a number of fail states, and a sequence of the fail states.