Patent ID: 8008724

Claim:
A structure that adjusts carrier mobility in CMOS transistors comprising: a substrate, a first transistor having a gate dielectric, gate electrode, and source, drain, and gate regions, formed on said substrate, a second transistor having a gate dielectric, gate electrode, and source, drain, and gate regions, formed on said substrate, a first film providing tensile stress at least at the channel of said first transistor, a second film providing compressive stress at least at the channel of said second transistor, a portion of said second film extending in the same region of said substrate as a portion of said first film, and a shear force isolation layer separating said first film and said second film and said tensile and compressive stress therein in at least one area, wherein said first film is closer to the substrate than said second film, and does not fully surround said first transistor, but rather the sides only, while the remaining surfaces of said first transistor are contacted by said shear force isolation layer.