Patent ID: 8761916

Claim:
A digital signal processor (DSP) comprising a plurality of D arithmetic logic units (ALUs), wherein the DSP is adapted to: receive an N-sample data frame comprising digital samples corresponding to an audio signal; and perform tone detection for the data frame using the ALUs of the plurality of D ALUs in parallel, wherein the tone detection comprises: (i) determining a power P(F) of a frequency F for the data frame by performing the following operations on the N-sample data frame: (a) generate V a (n) where V a (n)=M·x nD+a , for a=1, . . . , D and n=0, . . . , [N/D−1], wherein the DSP is adapted to perform operation (a) in one clock cycle for at least one value of n by using all of the ALUs of the plurality of D ALUs in parallel; ( b ) ⁢ ⁢ generate ⁢ ⁢ Re a ⁡ ( n + 1 ) ⁢ where ⁢ ⁢ Re a ⁡ ( n + 1 ) = Re a ⁡ ( n ) + V a ⁡ ( n ) · cos ⁡ ( 2 ⁢ π ⁢ ⁢ F F s ⁢ ( n - Dn - a ) ) , for a=1, . . . , D and n=0, . . . , [N/D−1], wherein the DSP is adapted to perform operation (b) in one clock cycle for at least one value of n by using all of the ALUs of the plurality of D ALUs in parallel; and ( c ) ⁢ ⁢ generate ⁢ ⁢ Im a ⁡ ( n + 1 ) ⁢ where ⁢ ⁢ Im a ⁡ ( n + 1 ) = Im a ⁡ ( n ) + V a ⁡ ( n ) · sin ⁡ ( 2 ⁢ π ⁢ ⁢ F F s ⁢ ( n - Dn - a ) ) , for a=1, . . . , D and n=0, . . . , [N/D−1], wherein the DSP is adapted to perform operation (c) in one clock cycle for at least one value of n by using all of the ALUs of the plurality of D ALUs in parallel, wherein V a (k), Re a (k), and Im a (k) are storage variables, F s is a sampling frequency for the data frame, x i is the ith sample of the data frame, a, k, and n are counting variables, and M is a normalization factor; and (ii) thresholding the determined power P(F) to determine whether a tone corresponding to the frequency F is present in the audio signal.