Patent ID: 7067369

Claim:
A method for fabricating a flash memory cell transistor, comprising: the first step of forming a n-well region and a p-well region on a silicon substrate which are divided by an isolation film; the second step of after performing a nMOS channel ion-implantation with p-type ions which are identical with the p-well region and a pMOS channel ion-implantation with n-type ions which are identical with the n-well region, sequentially depositing a first gate oxide film, an insulating film having an electron trap, and a buffer oxide film on the exposed p-well and n-well regions; the third step of coating a photoresist film and patterning the film with a pMOS oxide film mask to etch the insulating film having an electron trap in the n-well region using the buffer oxide film of the exposed nMOS region as a mask and simultaneously etch the first gate oxide film and the buffer oxide film of the exposed nMOS region; the fourth step of forming a second gate oxide film on the p-well region of the exposed nMOS region and the insulating film having an electron trap of the pMOS region; the fifth step of depositing a n+ polysilicon gate electrode on the second gate oxide film; and the sixth step of coating a photoresist film and patterning the n+ polysilicon gate electrode using a gate mask to etch the n+ polysilicon of the exposed region and remove the residual photoresist film.