Patent ID: 6982897

Claim:
A random access memory (RAM) circuit coupled to a write control line, a read control line, and at least one bitline, the RAM circuit comprising: a write switch having a control terminal and first and second terminals, the first terminal of the write switch coupled to the at least one bitline, the control terminal of the write switch coupled to the write control line; a charge-storage device having first and second terminals, wherein the first terminal of the charge-storage device is coupled to the second terminal of the write switch and the second terminal of the charge-storage device is coupled to the read control line; and a read switch having a control terminal and first and second terminals, the control terminal of the read switch coupled to the first terminal of the charge-storage device and coupled to the second terminal of the write switch, the first terminal of the read switch coupled to the at least one bitline, and the second terminal of the read switch coupled to ground.