Patent ID: 8296628

Claim:
A solid-state memory device, comprising: at least one memory array block including a plurality of memory cells arranged in rows and columns; a first sense circuitry bank associated with a first group of columns of the at least one memory array block; a second sense circuitry bank associated with a second group of columns of the at least one memory array block; an internal data bus of a bit width corresponding to a number of columns in one of the groups of columns; input/output circuitry coupled to the internal data bus, for arranging the contents of the first and second groups of columns sensed by the first and second sense circuitry banks into a data word comprised of a payload portion and an error correction coding (ECC) portion including an ECC value based on the contents of the payload portion, and for receiving input data corresponding to at least a portion of the data word; error correction coding (ECC) logic for generating ECC values based on the contents of the payload portion of data words; and control logic, for controlling the input/output circuitry, ECC logic, and the first and second sense circuitry banks to perform a read/write sequence of a data word in a selected row of the at least one memory array block according to a plurality of operations comprising: receiving input data to be stored; enabling the first and second sense circuitry banks to sense data states stored in memory cells of the first and second group of columns, respectively, in a selected row of the at least one memory array block; coupling the sensed data states from the first sense circuitry bank to the input/output circuitry via the internal data bus; then coupling the sensed data states from the second sense circuitry bank to the input/output circuitry via the internal data bus; generating the ECC value for a data word to be stored in the selected row, the data word including the received input data and the generated ECC value; then coupling, to the internal data bus, a portion of the data word to be stored in memory cells of the second group of columns in the selected row; and then coupling, to the internal data bus, a portion of the data word to be stored in memory cells of the first group of columns in the selected row.