Patent ID: 8566671

Claim:
A method of operating a memory system including a non-volatile memory circuit formed of one or more blocks of non-volatile memory cells, the block being a minimum erase unit, where each of the blocks includes one or more groups of memory cells that can be operated in parallel, the method comprising: for each of the blocks, maintaining by the memory system of an experience count indicative of the number of erase-program cycles that the corresponding block has experienced; maintaining by the memory system of a file wherein, for at least first and second non-overlapping ranges of experience counts, a corresponding first and second sample of data in a group of previously programmed memory cells is to be selected for a post-write process, wherein the file is configurable so that the first and second samples can be configured independently; programming multiple subsets of data into a first group of memory cells, each subset of data being provided with an ECC; subsequent to said programming, selecting by the memory system of a sample of the data programmed in the first group of memory cells from said multiple subsets of data programmed into the first group, wherein the selecting of a sample includes: determining whether the corresponding experience count for the first group of memory cells corresponds to one of the first or the second non-overlapping ranges of experience counts; and selecting a sample based on the sample corresponding to the determined experience count in the file; reading the selected sample; checking the selected sample as read to determine an amount of error therein, and reprogramming said multiple subsets of data into a second group of memory cells whenever the amount of error determined from the selected sample is more than a predetermined number of error bits.