Patent ID: 8850236

Claim:
A method for power gating one or more cores by a SoC, wherein the SoC includes a CPU register, the method comprising: performing operations as follows on at least one processor: tracking Instruction Pointer information and one or more states of the one or more cores, wherein the Instruction Pointer information is obtainable from the CPU register during execution of one or more code blocks by a processor in the SoC; receiving information of a first state of a first core from the one or more cores when the first state of the first core changes; retrieving first wake up latency information and a first core access information of the first core from a database responsive to receiving the information of the first state of the first core, wherein the database includes one or more latency information and one or more core access information of the one or more cores, respectively; determining a requirement of using the first core by the SoC based on the retrieved first wake up latency information, the first core access information, and the instruction pointer information, during the execution of the one or more code blocks; and performing one of power gating the first core and un-gating the first core based on the determined requirement.