Patent ID: 8802517

Claim:
An NMOS transistor, comprising: an indium phosphide (InP) substrate; an indium aluminum arsenide (InAlAs) buffer layer disposed above the InP substrate; a bottom barrier layer disposed above the InAlAs buffer layer; an indium arsenide (InAs) quantum well layer disposed above the bottom barrier layer; a top barrier layer disposed above the InAs quantum well layer; a gate stack disposed above the top barrier layer, the gate stack comprising: an aluminum oxide (Al 2 O 3 ) high-k gate dielectric layer disposed above the top barrier layer; and a metal gate electrode disposed above the Al 2 O 3 high-k gate dielectric layer; and raised source and drain regions disposed above an etch stop layer disposed above the top barrier layer, the raised source and drain regions disposed on either side of the gate stack, wherein the raised source and drain regions are formed in an indium gallium arsenide (InGaAs) cap layer disposed above the etch stop layer.