Patent ID: 7767566

Claim:
A method comprising: forming a plurality of cell gate patterns over a semiconductor substrate including a first cell gate pattern, a second cell gate pattern adjacent to the first cell gate pattern, a third cell gate pattern adjacent to the second cell gate pattern and a fourth cell gate pattern adjacent to the third cell gate pattern, each cell gate pattern having a first portion and a second portion, wherein the first portion of the second cell gate pattern and the third cell gate pattern are separated from each other by a first distance and the second portions of the second cell gate pattern and the third cell gate pattern are separated from each other by a second distance less than the first distance; forming spacers on both sidewalls of the cell gate patterns; forming a mask pattern covering the first portions of the cell gate patterns; removing the spacers formed on sidewalls of the second portions of the cell gate patterns using the mask pattern as an etching mask; and removing the mask pattern.