Patent ID: 7772644

Claim:
A VDMOS, comprising: an n-well formed within a semiconductor wafer; a drain coupled to said n-well of said VDMOS; a first source coupled to said n-well of said VDMOS; a second source coupled to said n-well; a gate coupled to said n-well, said gate having a gate dielectric and a gate electrode; a first p-body region and a second p-body region within said n-well, said first and second p-body regions including an n + -type region and an n-type region; and a first channel region located under said gate electrode and within said first p-body region; a second channel region located under said gate electrode and within said second p-body region; wherein a width of said first and second channel regions of said VDMOS are located between an inner boundary of said first and second p-body regions and an outer boundary of said n-type region of said first and second p-body regions, and further wherein said width of said first and second channel regions is less than 80% of a distance between an outer boundary of said n + -type region of said first and second p-body regions and said inner boundary of said first and second p-body regions at a surface of said first and second p-body regions located below said gate electrode.