Patent ID: 7486756

Claim:
A phase detector, comprising: a first latch, having a first input end for receiving a data signal and being enabled by a first level portion of a clock signal; a second latch, coupled to the first latch, having a second input end for receiving an output signal of the first latch and being enabled by a second level portion of a clock signal; a third latch, coupled to the second latch, having a third input end for receiving an output signal of the second latch and being enabled by the first level portion of the clock signal; a fourth latch, coupled to the third latch, having a fourth input end for receiving an output signal of the third latch and being enabled by the second level portion of the clock signal; a fifth latch, coupled to the fourth latch, having a fifth input end for receiving an output signal of the fourth latch and being enabled by the first level portion of the clock signal; a sixth latch, coupled to the fifth latch, having a sixth input end for receiving an output signal of the fifth latch and being enabled by the second level portion of the clock signal; a logic gate for processing a logic operation of the output signal of the second latch and the output signal of the third latch; a first SR-type latch, having a first setting end and a first resetting end for respectively receiving the data signal and an output signal of the logic gate, and for outputting a first up signal; a second SR-type latch, having a second setting end and a second resetting end for respectively receiving the output signal of the second latch and the output signal of the fourth latch, and for outputting a first down signal; a third SR-type latch, having a third setting end and a third resetting end for respectively receiving the output signal of the third latch and the output signal of the fifth latch, and for outputting a second down signal; and a fourth SR-type latch, having a fourth setting end and a fourth resetting end for respectively receiving the output signal of the fourth latch and the output signal of the sixth latch, and for outputting a second up signal.