Patent ID: 8023057

Claim:
A method for manufacturing a thin film transistor array panel, the method comprising: forming a gate line and a gate electrode on a substrate by using a first mask; depositing an insulation layer on the gate line and on the gate electrode; depositing a semiconductor layer on the insulating layer; depositing an n+ amorphous silicon layer on the semiconductor layer; forming a data line, a source electrode and a drain electrode on the substrate by using a second mask before first etching of the n+ amorphous silicon layer; removing the exposed portion of the n+ amorphous silicon layer; forming a passivation film on the semiconductor layer, the n+ amorphous silicon layer, the data line, the source electrode and the drain electrode by using a third mask, the passivation film exposing a portion of the drain electrode and a portion of the semiconductor layer; removing the exposed portion of the semiconductor layer by using the passivation film as a mask; and forming a pixel electrode connected to the exposed portion of the drain electrode by using a fourth mask.