Patent ID: 7348233

Claim:
A method for fabricating a CMOS device including a silicon substrate having a first region of N-type conductivity and a second region of P-type conductivity, the method comprising the steps of: forming a first silicon gate electrode overlying the first region and a second silicon gate electrode overlying the second region, each of the first silicon gate electrode and the second silicon gate electrode having sidewalls; depositing a silicon oxide layer overlying the first silicon gate electrode and the second silicon gate electrode to form a silicon oxide layer on the sidewalls; forming a first oxide liner on the silicon oxide layer overlying the sidewalls of the first gate electrode and overlying a portion of the first region and a second oxide liner on the silicon oxide layer overlying the sidewalls of the second gate electrode and overlying a portion of the second region; forming first nitride sidewall spacers on the first oxide liner and second nitride sidewall spacers on the second oxide liner; removing the second nitride sidewall spacers; etching the first oxide liner using the first nitride sidewall spacers as an etch mask to expose a portion of the first region, the exposed portion of the first region spaced a first distance from the sidewall of the first gate electrode; etching the second oxide liner, after removing the second nitride sidewall spacers, to expose a portion of the second region, the exposed portion of the second region spaced a second distance from the sidewall of the second gate electrode, wherein the first distance is greater than the second distance; and forming a first silicide layer at the exposed portion of the first region and a second silicide layer at the exposed portion of the second region.