Patent ID: 8722493

Claim:
A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising: forming a charge storage layer over the substrate in the NVM region and the logic region; forming a first conductive layer over the charge storage layer in the NVM region and the logic region; patterning the first conductive layer and the charge storage layer to form a control gate in the NVM region and to remove the first conductive layer and the charge storage layer from the logic region; forming a first dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region; forming a barrier layer over the first dielectric layer in the NVM region and the logic region; forming a sacrificial layer over the barrier layer in the NVM region and the logic region; planarizing the sacrificial layer, wherein the first dielectric layer comprises a sidewall portion located along a sidewall of the control gate, between the control gate and the barrier layer and the barrier layer comprises a sidewall portion located adjacent the sidewall of the control gate, between the sidewall portion of the first dielectric layer and the sacrificial layer; forming a first masking layer over the sacrificial layer and the control gate in the NVM region, wherein the first masking layer defines a select gate location laterally adjacent the control gate in the NVM region; forming a second masking layer over the sacrificial layer in the logic region, wherein the second masking layer defines a logic gate location in the logic region; using the first masking layer to remove exposed portions of the sacrificial layer in the NVM region, wherein a first portion of the sacrificial layer remains at the select gate location; using the second masking layer to remove exposed portions of the sacrificial layer in the logic region, wherein a second portion of the sacrificial layer remains at the logic gate location; forming a second dielectric layer in the NVM region and the logic region, wherein the second dielectric layer is formed over the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer; planarizing the second dielectric layer to expose the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer; and removing the first portion of the sacrificial layer to result in a first opening at the select gate location and the second portion of the sacrificial layer to result in a second opening at the logic gate location, wherein each of the first opening and the second opening exposes the barrier layer.