Patent ID: 7072633

Claim:
A double-conversion tuner, comprising: an input for receiving an RF signal having a number of channels; a first mixer configured to up-convert said RF signal to a first IF signal using a first local oscillator signal; a first local oscillator having a delta-sigma fractional-N phase lock loop to produce said first local oscillator signal, said delta-sigma fractional-N phase lock loop configured to perform fine tuning of said first local oscillator signal and configured to have a wide tuning range sufficient to cover said number of channels, and said delta-sigma fractional-N phase lock loop including a feedback path having a programmable frequency divider, and a delta-sigma modulator configured to receive a static fractional input and generate an output having a plurality of pulses that when averaged over time have an amplitude corresponding to said static fractional input, said delta-sigma modulator including a series of registers with a summer in-between adjacent registers, a slicer configured to quantize an output of a last register in said series of registers so as to produce an integer at an output of said slicer, and a plurality of multipliers configured to multiply said output of said slicer by a series of coefficients, outputs of said plurality of multipliers coupled to inputs of said summers that are in-between said adjacent registers; a bandpass filter configured to select a subset of channels from said first IF signal; a second mixer configured to down-convert said subset of channels to a second IF signal using a second local oscillator signal; and a second local oscillator configured to generate said second local oscillator signal, and configured to perform coarse frequency tuning and have a narrow tuning range relative to said first local oscillator.