Patent ID: 8084327

Claim:
A method of forming a field effect transistor having an active area and a termination region surrounding the active area, comprising: forming a well region in a first silicon region, the well region and the first silicon region being of opposite conductivity type; forming gate trenches extending through the well region and terminating within the first silicon region; forming a recessed gate in each gate trench; forming a dielectric cap over each recessed gate; removing a portion of the well region between adjacent trenches to expose upper sidewalls of each dielectric cap; performing a blanket source implant to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches, the second silicon region being of the same conductivity type as first silicon region; thereafter, forming a dielectric spacer along each exposed upper sidewall of the dielectric cap, every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region; and recessing the second silicon region through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain, the remaining portions of the second silicon region forming source regions.