Patent ID: 8412761

Claim:
A single-precision floating-point data storing method for use in a processor including a register, which has a size that can store double-precision floating-point data, configured to store double-precision floating-point data and single-precision floating-point data, comprising: writing input single-precision floating-point data to a high-order half of the register, and writing all zeros to a low-order half of the register when a single-precision floating-point data process is specified and a first process is specified; and writing input single-precision floating-point data to the high-order half of the register, and writing no data to the low-order half of the register when the single-precision floating-point data process is specified and a second process is specified, wherein whether the writing the input single-precision floating point data to the high-order half of the register is the first process or the second process is determined based on results of decoding of an instruction.