Patent ID: 7031456

Claim:
An output impedance calibration method for invariably maximizing hybrid performance, said method comprising one or more steps selected from the group consisting of: a) calibrating an adjustable resistor R 1 by disabling a replica digital-to-analog converter (DAC) current K; transmitting constant current (DC) from a main DAC; measuring an input peak amplitude A peak — 1 at a receiver; transmitting random data within a time constraint; and adjusting R 1 until an input peak amplitude A peak — i is on average half of A peak — 1 , thereby matching R 1 to a load impedance Z L ; b) calibrating K for optimum DC matching in presence of Z L by enabling K; setting K to a nominal value; forcing a timing recovery loop such that said receiver and a corresponding transmitter are 180 degree out of phase, thereby forcing said receiver to sample hybrid output between transitions; and incrementing bias current in discrete steps until sampled hybrid output is minimized on average, thereby rendering an optimal K for Z L ; and c) calibrating a slope-matching capacitor C 2 by forcing said timing recovery loop such that said receiver and said transmitter are in phase; transmitting random data within a time constraint through both said main DAC and said replica DAC; observing sampled voltage at an input of said receiver; and adjusting C 2 until voltage at said receiver input changes sign.