Patent ID: 7998802

Claim:
A method of manufacturing a semiconductor device comprising the steps of: (a) preparing a semiconductor substrate having a major surface including an NMOS region for forming a NMOS transistor and a PMOS region for forming a PMOS transistor; (b) forming a first gate insulating film of said NMOS transistor in said NMOS region and forming a second gate insulating film of said PMOS transistor in said PMOS region and forming a first gate electrode over said first gate insulating film and forming a second gate electrode over said second gate insulating film, and said first gate electrode and said second gate electrode each having side surfaces; (c) after said step (b), forming a first offset insulating film over said side surfaces of said first gate electrode formed in the NMOS region and said side surfaces of said second gate electrode formed in the PMOS region; (d) after said step (c), forming a lightly doped N-type extension by implanting an N-type impurity into said first NMOS region leaving the first offset insulating film over side surfaces of said first gate electrode; (e) after the N-type impurity implanting of said step (d), forming a silicon oxide second offset insulating film over said first offset insulating film formed over said side surfaces of said second gate electrode; (f) after said step (e), forming a lightly doped P-type extension by implanting P-type impurity into said first PMOS region leaving said first offset insulating film and said silicon oxide second offset insulating film over said side surfaces of said second gate electrode.