Patent ID: 7825437

Claim:
A method comprising forming N-diffusion and P-diffusion fins in a semiconductor substrate; forming a P-diffusion gate layer over the semiconductor substrate; removing the P-diffusion gate layer from the N-diffusion fins; forming a pass-gate N-diffusion gate layer over the semiconductor substrate; removing the pass-gate N-diffusion gate layer from the P-diffusion fins and a pull-down portion of the N-diffusion fins; and forming a pull-down N-diffusion gate layer over the semiconductor substrate, wherein a P-diffusion gate electrode stack includes the P-diffusion gate layer and the pull-down N-diffusion gate layer; a pass-gate gate electrode stack includes the pass-gate N-diffusion gate layer and the pull-down N-diffusion gate layer; and a pull-down gate electrode stack includes the pull-down N-diffusion gate layer, wherein threshold voltage of the pass-gate gate electrode stack and threshold voltage of the pull-down gate electrode stack are different.