Patent ID: 7127647

Claim:
An apparatus, comprising: a first set of two or more memory arrays, each memory having one or more redundant components associated with that memory array, the one or more redundant components include at least one redundant column, the first set of two or more memory arrays are located on a single chip; and a first processor located on the single chip, the first processor containing redundancy allocation logic having a repair algorithm, the repair algorithm to determine and optimize the allocation of the one or more redundant components to repair one or more defects detected in the first set of two or more memory arrays while fault testing the two or more memory arrays, wherein the first processor couples to the first set of two or more memory arrays and the repair algorithm to make multiple passes through a first memory array under analysis until a successful repair of the first memory array is achieved, where each pass implements a repair sequence having at least one of 1) a different order of assigning repair components compared to a previous pass and 2) a different memory address order compared to the previous pass in analyzing the first memory array to repair the first memory array.