Patent ID: 7210022

Claim:
A packet processing system comprising: a processor; a co-processor separated from said processor by a boundary; and an interface coupled with said processor and said co-processor and operative to bridge said boundary, said interface including: a memory coupled with said processor and said co-processor, said memory having at least two read/write ports for reading and writing data to said memory wherein said processor is coupled with one of said at least two read/write ports and said co-processor is coupled with the other of said at least two read/write ports; and control logic coupled with said at least two read/write ports; wherein said processor stores data intended for said co-processor to said memory and reads data stored by said co-processor from said memory; said co-processor stores data intended for said processor to said memory and reads data stored by said processor from said memory; and said control logic operative to facilitate the reading of said stored data by said processor and said co-processor by detecting a store operation by said co-processor of data, intended for said processor, to said memory and, based thereon signaling said processor of the detected store operation and by detecting a store operation by said processor of data, intended for said co-processor, to said memory and, based thereon, signaling said co-processor of the detected store operation, said processor and co-processor not otherwise signaling said control logic of said store operations; and wherein said processor and said co-processor are capable of storing data to said memory substantially simultaneously.