Patent ID: 7185186

Claim:
A deadlock avoidance apparatus in a microprocessor having a speculative branch target address cache (BTAC), the apparatus comprising: a first signal, for indicating a miss of a fetch address in an instruction cache, wherein said fetch address is a speculative branch instruction target address provided by the BTAC; a second signal, for indicating an instruction formatter has determined said branch instruction wraps across two cache lines in response to decoding a first of said two cache lines, wherein said instruction cache provided said first cache line containing only a first portion of said branch instruction prior to said first signal indicating said miss of said target address in said instruction cache; and a third signal, for indicating the BTAC predicted said branch instruction is wholly contained within said first cache line, whereby a second of said two cache lines is not fetched because the BTAC predicted said branch instruction is wholly contained within said first cache line; a fourth signal, for indicating execution logic has detected and corrected a BTAC misprediction, wherein said execution logic does not detect said BTAC incorrectly predicts that said branch instruction is wholly contained within said first cache line because said instruction formatter is stalled waiting for said second cache line to be fetched; and control logic, coupled to receive said first, second, third, and fourth signals, for invalidating said target address in the BTAC, in response to a true indication on said first, second, and third signals and a false indication on said fourth signal.