Patent ID: 7157295

Claim:
A method of manufacturing a liquid crystal display, wherein said method comprises the following steps of: providing a substrate; forming a conductive layer over said substrate; forming a first metal layer over said conductive layer; forming a heavily doped layer over said first metal layer; patterning said heavily doped layer, said first metal layer and said conductive layer to define a peripheral circuit region, a transistor region, a reflection region, a transmission region and a capacitor region; forming a semiconductor layer over said substrate and said heavily doped layer; forming an insulating layer over said semiconductor layer; patterning said insulating layer, said semiconductor layer and said heavily doped layer to define a source/drain region and a channel region and to partially expose said first metal layer; forming a resin layer over said substrate, said first metal layer and said insulating layer; patterning said resin layer to form a non-uniform surface on said reflection region; performing a thermal process to soften said non-uniform surface to form a smooth surface; forming a second metal layer over said resin layer, said substrate, said first metal layer and said insulating layer; patterning said second metal layer to define a gate electrode substrate, a reflection electrode and a capacitor electrode; forming a patterned photoresist layer over said gate electrode substrate, said reflection electrode, said substrate, said first metal layer, said capacitor electrode and said insulating layer; performing an ion implantation into said source/drain region located in said peripheral circuit region using said patterned photoresist layer as a mask; removing said patterned photoresist layer; forming a passivation layer over said gate electrode structure, said reflection electrode, said substrate, said first metal layer, said capacitor electrode and said insulating layer; patterning said passivation layer to expose said transmission region; and etching partial said first metal layer to expose said conductive layer.