Patent ID: 7338874

Claim:
A method of manufacturing a highly integrated semiconductor device, the method comprising: forming a gate electrode on a semiconductor substrate; forming an offset spacer along sidewalls of the gate electrode; growing predetermined portions of the semiconductor substrate on the both sides of the gate electrode to a predetermined thickness to form a selective epitaxial growth layer; forming a source region and a drain region in the predetermined grown portions of the semiconductor substrate on the both sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain region and a heavily doped region; and forming a silicide layer on the gate electrode, the source region, and the drain region, wherein the silicide layer is formed on each of the lightly doped drain region and the heavily doped region, and wherein the forming of the source region and the drain region and the forming of the silicide layer include: implanting low concentration impurities into the predetermined portions of the semiconductor substrate on the two sides of the gate electrode to form the lightly doped drain regions; forming the silicide layer on the lightly doped drain regions; forming an insulating spacer along sidewalls of the gate electrode; and implanting high concentration impurities into predetermined portions of the semiconductor to form the heavily doped regions such that the insulating spacer is disposed between the heavily doped regions and the semiconductor substrate.