Patent ID: 8624622

Claim:
An apparatus comprising: a sequential processor; a first communication bus coupled to the sequential processor, the first communication bus for configuration and control information; and a plurality of circuit arrays coupled to the first communication bus, each circuit array of the plurality of circuit arrays comprising: a plurality of composite circuit elements, each composite circuit element comprising an element interface and a circuit element of a plurality of different circuit element types, each element interface comprising at least one data input queue and at least one data output queue, a first composite circuit element of the plurality of composite circuit elements to perform a first function, a second composite circuit element of the plurality of composite circuit elements to perform a second function, a third composite circuit element of the plurality of composite circuit elements configurable to perform the second function and a third function; and a second communication bus coupling each at least one data input queue to each at least one data output queue for a plurality of configurable data links, the first composite circuit element having a first configurable data link of the plurality of configurable data links to the second composite circuit element for performance of a first data operation and a second configurable data link of the plurality of configurable data links to the third composite circuit element for performance of the first data operation or performance of a second data operation.