Patent ID: 7834949

Claim:
A liquid crystal display device comprising: a pair of substrates opposed to each other; a liquid crystal layer sealed between the substrates; a plurality of gate bus lines formed on one of the substrates so as to be parallel with each other; a plurality of drain bus lines formed so as to cross the gate bus lines with an insulating film interposed in between; a plurality of storage capacitance bus lines formed parallel with the gate bus lines; first and second transistors each having a gate electrode electrically connected to an nth gate bus line and a drain electrode electrically connected to one of the drain bus lines; a first pixel electrode electrically connected to a source electrode of the first transistor; a second pixel electrode which is electrically connected to a source electrode of the second transistor and is separated from the first pixel electrode; a pixel region having at least a first sub-pixel in which the first pixel electrode is formed and a second sub-pixel in which the second pixel electrode is formed; a third transistor having a gate electrode electrically connected to an (n+1)th gate bus line, a source electrode connected or coupled to the second pixel electrode, and a drain electrode connected or coupled to one of the storage capacitance bus lines; a buffer capacitance portion which establishes capacitive coupling between the drain electrode of the third transistor and the storage capacitance bus line or between the source electrode of the third transistor and the second pixel electrode; wherein the buffer capacitance portion comprises a first buffer capacitance electrode electrically connected to the drain electrode of the third transistor, a second buffer capacitance electrode which is opposed to the first buffer capacitance electrode and is electrically connected to the storage capacitance bus line, and a dielectric layer interposed between the first and second buffer capacitance electrodes; wherein the first and second buffer capacitance electrodes are both located proximate to a semiconductor material of the third transistor; wherein a location where the first and second buffer capacitance electrodes overlap each other is, when viewed from above, provided between: (a) the (n+1)th gate bus line connected to the third transistor, and (b) majorities of the first and second pixel electrodes, and wherein, along a straight line between the closest proximity of the (n+1)th gate bus line to said overlap of the first and second buffer capacitance electrodes, no significant portion of the first and second pixel electrodes is provided between the (n+1)th gate bus line and the location where the first and second buffer capacitance electrodes overlap each other.