Patent ID: 7358782

Claim:
A frequency divider, comprising: an input; a counter having a counter reset port and configured to receive a clock signal from the input and to produce a sum signal; a first comparator configured to receive the sum signal, to compare the sum signal to a first integer, and to produce a first comparison signal; an interconnect configured to convey the first comparison signal from the first comparator to the counter reset port; a second comparator configured to receive the sum signal, to compare the sum signal to a second integer, and to produce a second comparison signal; a first flip-flop having a set port and a reset port and configured to receive the first comparison signal at the set port, to receive the second comparison signal at the reset port, and to produce an output signal; and an output coupled to the first flip-flop; wherein the clock signal has a periodic waveform, the sum signal represents a first sum, the first sum equals a number of waveforms of the clock signal received by the counter after the counter has been reset, the first integer is selectable from a range of at least three consecutive integers, and the first integer is greater than the second integer.