Patent ID: 7558142

Claim:
A memory device having an array of memory cells arranged in rows and columns, at least some of the rows containing at least one memory cell unable to retain data during refresh, the memory device comprising: a row address register circuit operable to receive and store a plurality of row addresses that identity rows of memory cells containing at least one memory cell that is unable to retain data, and operable to store a predetermined number of bits of each of the plurality of row addresses; a refresh counter operable to generate refresh row addresses during a refresh cycle; a comparator circuit coupled to the row address register circuit and the refresh counter circuit, the comparator circuit operable to compare each of the plurality of row addresses of the row address register and each of the predetermined number of bits to the refresh row addresses generated by the refresh counter and generate a match signal in the event of a match; and a control logic circuit coupled to the comparator circuit, the control logic circuit being configured to receive the match signal and operable to refresh the row matched to the row address stored in the row address register responsive to each occurrence of the match signal in a manner that allows the row matched to the stored row address to selectively receive at least an extra refresh.