Patent ID: 8406724

Claim:
An apparatus for unified down-conversion and filtering, comprising: a down conversion module comprising first and second sampling circuits, each circuit comprised of a switching device and a storage module; the first sampling circuit receiving as an input an RF information signal, and providing as an output a first down-converted signal; the second sampling circuit receiving as an input the output down-converted signal from the first sampling circuit and providing as an output a second down-converted signal that is phase shifted relative to the first down-converted signal; the switching device of the first sampling circuit receiving as an input a first control signal and the switching device of the second sampling circuit receiving as in input a second control signal that differs in phase from the first control signal; and the first control signal controlling a charging and discharging cycle of the storage module of the first sampling circuit by controlling the switching device of the first sampling circuit so that a portion of energy is transferred from the RF information signal to the storage module of the first sampling circuit during a charging part of the cycle and a portion of the transferred energy is discharged during a discharging part of the cycle, and the first control signal operating at an aliasing rate selected so that energy of the RF information signal is sampled and applied to the storage module of the first sampling circuit at a frequency that is equal to or less than twice the frequency of the RF information signal, and wherein the storage module of the first sampling circuit generates said down-converted signal from the alternate charging and discharging applied to the storage module of the first sampling circuit using said first control signal; a delay module comprising first and second delay circuits; the first delay circuit receiving at its input (i) the second down-converted signal that is phase shifted, and (ii) the first control signal, and outputting a delayed version of the second down-converted signal; and the second delay circuit receiving at its input (i) the delayed version of the second down-converted signal, and (ii) the second control signal, and outputting a version of the second down-converted signal that is further delayed relative to the output of the first delay circuit; and a summing module that forms a final down-converted, filtered output signal by combining the second down-converted, phase shifted signal output from the second sampling circuit and the further delayed version of the second down-converted signal output by the second delay circuit.