Patent ID: 8078947

Claim:
A data processing circuit, comprising: a page buffer for storing target page data; a first syndrome calculator and a second syndrome calculator for respectively obtaining a first syndrome polynomial and a second syndrome polynomial according to the target page data, and for respectively saving the target page data as a first codeword and a second codeword; a key equation device for obtaining an errata locator polynomial according to the first syndrome polynomial and the second syndrome polynomial, and obtaining a first error count and a second error count according to the errata locator polynomial, the first codeword and the second codeword; a Chien searcher for obtaining a set of reference codes according to the errata locator polynomial; an address counter for storing addresses of a plurality of programmed-error bits; a latch, which is coupled to the address counter and for temporarily storing the addresses of the programmed-error bits; a switching device, which is coupled to the key equation device, the latch and the page buffer, and for outputting read page data according to the addresses of the programmed-error bits, the first error count and the second error count; and a correcting unit for correcting the read page data according to the set of reference codes to obtain corrected read page data.