Patent ID: 7251280

Claim:
A circuit structure for a serial Advanced Technology Attachment (ATA) external physical layer comprising: a decoder/encoder connected to a storage medium controller via a set of parallel signal transmission lines and a set of parallel signal receiving lines for decoding a parallel transmission signal originated from said storage medium controller into a parallel transmission data signal and at least one control signal; at least one serializer/deserializer connected to said decoder/encoder for the conversion of said parallel transmission data signal into a serial transmission data signal; at least one phase locked loop connected to said decoder/encoder and said at least one serializer/deserializer, respectively, for receiving said at least one control signal originated from said decoder/encoder, as well as generating clock signals required for the operation of said physical layer and transmitting a reference clock signal to said storage medium controller; a plurality of transmitters, connected to said serializer/deserializer, each of said transmitters being used to transmit said serial transmission data signal to a serial ATA device connected thereto via a set of serial signal transmission lines; a plurality of receivers connected to said serializer/deserializer, each of said receivers being used to transmit a serial receiving data signal received from said serial ATA device connected thereto to said serializer/deserializer, and then said serial receiving data signal being converted into a parallel receiving data signal by said serializer/deserializer for transmitting to said decoder/encoder; and at least one out of band (OOB) signal detector connected to receiving signal lines of said corresponding receivers, respectively, for detecting the operation condition of said serial ATA device and transmitting at least one set of detected status signals to said decoder/encoder, said parallel receiving data signal and said status signals then being encoded into a parallel receiving signal by said decoder/encoder and, afterward, transmitted to said storage medium controller via said set of parallel signal receiving lines.