Patent ID: 7470953

Claim:
An insulated gate type semiconductor device comprising: a body region arranged at upper surface side in a semiconductor substrate, the body region having a first conductive type semiconductor; a drift region being in contact with bottom surface of the body region, the drift region having a second conductive type semiconductor; and a trench section arranged with penetrating the body region from upper surface of the semiconductor substrate and reaching level further below bottom surface of the body region, wherein the insulated gate type semiconductor further comprises a floating region surrounded by the drift region, the floating region having a first conductive type semiconductor, bottom of the trench section is arranged in the floating region, in the trench section, there are formed a deposited insulating layer consisting of deposited insulating material and a gate electrode being arranged above the deposited insulating layer and facing the body region, and a lower end of the gate electrode is further above top of the floating region, a space between the bottom surface of the body region and the top of the floating region is wider than a space between a lower end of the deposited insulating layer and a lower end of the floating region, and a space between the lower end of the gate electrode and the lower end of the deposited insulating layer is wider than a space between the bottom surface of the body region and the top of the floating region, the space between the adjacent floating regions is a space where positive field intensity distribution curves connect with each other during the off time of the gate electrode voltage, in a middle portion between the floating regions in a direction that connecting the floating regions, the deposited insulating layer having a thickness capable of forming peaks of a electric field at two positions in a direction of thickness of the semiconductor substrate during the off time of the gate electrode voltage.