Patent ID: 7352057

Claim:
A semiconductor module having an internal semiconductor chip stack on a wiring substrate, the semiconductor chip stack comprising: semiconductor chips which are stacked on top of one another and comprise a top semiconductor chip and at least one bottom semiconductor chip, the semiconductor chips having, on their active top side, an additional wiring structure with a metal coating, which comprises a plurality of metal layers, and with interconnects between contact areas in a central region and bonding connection pads in edge regions, the wiring structure configuring originally identical semiconductor chips in such a manner that the contact areas which were originally arranged centrally in the central region are rewired to bonding connection pads in edge regions, and the bonding connection pads being electrically connected to the wiring substrate via bonding connections, and the semiconductor chips being stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them.