Patent ID: 8004895

Claim:
A method of operating an erasable and re-programmable non-volatile memory system having an array of memory cells organized into blocks of a minimum number of memory cells that are erasable together that include a plurality of pages individually storing one or more units of data, comprising: in response to the occurrence of at least one of a plurality of predefined events, identifying at least one page of at least one block to be scrubbed, reading data stored in said at least one page with a first set of read conditions comprising a first set of breakpoint levels, determining whether there are any errors in the read data, if there are errors in the read data, determining whether the errors can be corrected, in response to determining that the errors in the read data cannot be corrected, re-reading the data stored in said at least one page with a second set of read conditions comprising a second set of breakpoint levels shifted with respect to the first set of breakpoint levels within guardbands separating memory storage levels, determining whether there are any errors in the re-read data, and, if so, whether the errors can be corrected, in response to other memory activity being scheduled, deferring further action with respect to the read or re-read data, after the other memory activity is completed and in response to determining that the errors in either of the read or re-read data can be corrected, correcting such errors to provide corrected data, and writing the corrected data into at least a second page of a second block different from said one block.