Patent ID: 8271767

Claim:
An information processing apparatus comprising: an arithmetic circuit that executes a predetermined arithmetic operation; a determining unit that compares a data size of data to be processed with a predetermined first threshold value, and determines one of a synchronous mode and an asynchronous mode as an execution mode when the data size is larger than the first threshold value, and the other as the execution mode when the data size is not larger than the first threshold value, the synchronous mode executing the processing after waiting for completion of the arithmetic operation by the arithmetic circuit, and the asynchronous mode executing the processing without waiting for completion of the arithmetic operation by the arithmetic circuit; a control unit that controls the arithmetic operation performed by the arithmetic circuit according to the execution mode determined by the determining unit; and a threshold value calculating unit that determines processing loads of the processing on the data of a plurality of data sizes for each of the synchronous mode and the asynchronous mode and calculates the first threshold value by using first data and second data, the first data being weighted data of data on one side of a node where a first line and a second line cross, the second data being weighted data of data on another side of the node, the first line being a line connecting the processing loads of the processing in the synchronous mode, the second line being a line connecting the processing loads of the processing in the asynchronous mode.