Patent ID: 7176512

Claim:
A semiconductor memory device comprising: a substrate; a plurality of word lines extended in a column direction and arranged in parallel on the substrate; a plurality of bit lines extended in a row direction perpendicular to the column direction such that the bit lines intersect the word lines and are arranged in parallel on the substrate; a plurality of active regions formed on the substrate, wherein each of the active regions includes a first impurity region, a second impurity region, and a channel region defined by the first impurity region and the second impurity region, wherein the channel region is crossed by each word line formed on the channel region; and a memory cell array comprising a plurality of memory cell pairs, wherein each memory cell of a memory cell pairs is formed in one of the active regions and comprises a charge storage capacitor, a first contact connecting one of the bit lines to the first impurity region, and a second contact connecting a storage node of the charge storage capacitor to the second impurity region, wherein each first contact of the memory cell pairs is electrically connected to each other.