Patent ID: 7263624

Claim:
A method for conserving power in a processor pipeline during conditional execution of instructions of multiple types, comprising the steps of: determining in a first pipeline cycle for an instruction of a first type whether subsequent cycles of operation can be stopped for the instruction of the first type based in part on an examination of one or more conditional execution flags during the first pipeline cycle; determining in a second pipeline cycle for an instruction of a second type whether subsequent cycles of operations can be stopped for the instruction of the second type based in part on an examination of one or more condition execution flags during the second pipeline cycle; and stopping execution at the end of the first pipeline cycle for the first type of instruction or at the end of the second pipeline cycle for the second type of instruction if the conditional execution flags that are examined are determined to be such that no execution is to occur in the subsequent cycles of operation, wherein if the execution is stopped, it is stopped without affecting execution of one or more other instructions already in the processor pipeline.