Patent ID: 8683285

Claim:
A method for error-correcting in a parallel interconnect link, the method comprising: at a parallel interconnect transmitting device at one end of the link: detecting a frame transition in a transmission from the-transmitting device to a parallel interconnect receiving device at another end of the link; tracking time between the frame transition and a transition of a response signal corresponding to the frame transition received from the receiving device; detecting an error in the transmission; and restarting a portion of the transmission in response to the error, wherein the size of the portion of the transmission to restart is based upon the tracked time between the frame transition and the transition of a response signal corresponding to the frame transition; at a parallel interconnect receiving device at another end of the link: storing transmissions received from the error-correcting parallel interconnect transmitting device in a receive FIFO buffer; detecting a parity error in a transmission from the error-correcting parallel interconnect transmitting device; and dropping two-cycle's worth of the transmission prior to adding it to the receive FIFO buffer and ignoring all subsequent transmissions until a transmission indicating a start of replay framing is received.