Patent ID: 8599982

Claim:
An interface system for interfacing a synchronous circuit with an asynchronous circuit, wherein said synchronous circuit generates, in response to a clock signal, a first control signal indicating the fact that a first data signal contains valid data, and wherein said asynchronous circuit generates, according to an asynchronous communication protocol, a second control signal indicating the transmission status of a second data signal, characterized in that the system comprises: a conversion circuit configured for converting, according to said asynchronous communication protocol, said first data signal into an encoded data signal, a first-in first-out memory, comprising a plurality of memory locations, wherein the signal currently read from said memory corresponds to said second data signal, and a control circuit configured for: writing said encoded data signal in said memory in a synchronous way in response to said clock signal, and reading said second data signal from said memory in an asynchronous way in response to said second control signal, wherein said control circuit is configured for writing said encoded data signal in said memory when said first control signal indicates that said first data signal contains valid data, wherein said control circuit comprises a first counter configured for managing a write pointer indicating the memory location in said memory in which said encoded data signal is written, wherein said first counter is configured for incrementing said write pointer in a synchronous way in response to said clock signal when said first control signal indicates that said first data signal contains valid data, wherein said control circuit comprises a second counter configured for managing a read pointer indicating the memory location in said memory from which said second data signal is read, wherein said second counter is configured for incrementing said read pointer when said second control signal indicates that said asynchronous circuit can receive new data, and wherein said control circuit is configured for resetting the contents of the memory location indicated via said read pointer when said second control signal indicates that said second data signal has been sampled.