Patent ID: 8269863

Claim:
A solid-state image pickup device comprising: a pixel array unit including a plurality of pixels, each pixel having a photoelectric converter; a signal conversion circuit configured to convert a pixel signal output from the pixel array unit into an output signal, the output signal being an image signal; and a clamp correction circuit configured to generate a predetermined signal from the image signal and correct a clamp level included in the predetermined signal, the predetermined signal being the image signal including an optical black level read from the pixel array unit, wherein, the clamp correction circuit includes (a) a circuit to generate the predetermined signal from the image signal; (b) analog-to-digital conversion means for receiving the predetermined signal from the circuit and performing analog-to-digital conversion of the predetermined signal and generating and outputting N+M bits of digital data at the time of the analog-to-digital conversion, N+M bits being obtained by adding M bits for correction to N bits, the N bits being assigned to the predetermined signal at a time of quantization by the analog-to-digital conversion means; (c) correction value generating means for determining a correction value on the basis of the N+M bits of digital data output by the analog-to-digital conversion means and a target value, the correction value used for correcting variations and/or a black level to an appropriate clamp value; (d) computing means for performing a correction computation using the N+M bits of digital data output by the analog-to-digital conversion means and the correction value output by the correction value generating means so as to generate lowest N bits of clamp-corrected data, said computing means generating the lowest N bits of clamp-corrected data after performing the correction computation, and (e) gain control means for lowering a gain of data in a first specified-level region of the N+M bits of digital data output by the analog-to-digital conversion means; and wherein, said computing means includes level shifting control means for level-shifting data in a second specified-level region of the N+M bits of digital data output by the analog-to-digital conversion means, and said computing means receives N+M bits of digital data as input directly from the analog-to-digital conversion means, and outputs a resulting value with N bits of clamp corrected data by subtracting the correction value from the digital data.