Patent ID: 7898509

Claim:
A display comprising: a pixel array part configured to include pixel circuits arranged in a matrix, each of the pixel circuits having a drive transistor that produces a drive current, a holding capacitor connected between a control input terminal and an output terminal of the drive transistor, an electro-optical element connected to the output terminal of the drive transistor, a sampling transistor that writes information corresponding to a signal potential of a video signal supplied via a video signal line to the holding capacitor, and an initialization transistor that has an output terminal coupled to a connecting node between the holding capacitor and the output terminal of the drive transistor and initializes a potential of the output terminal of the drive transistor, a drive current based on information held in the holding capacitor being produced by the drive transistor and being applied to the electro-optical element for light emission of the electro-optical element; and a controller configured to include a write scanner and a horizontal driver, the write scanner sequentially controlling the sampling transistors with a horizontal cycle to thereby carry out line-sequential scanning of the pixel circuits and writing information corresponding to a signal potential of a video signal to each of the holding capacitors on one row, the horizontal driver supplying video signals for one row to the video signal lines in matching with the line-sequential scanning by the write scanner, wherein the controller implements control for execution of threshold correction operation for holding a voltage equivalent to a threshold voltage of the drive transistor in the holding capacitor by keeping the initialization transistor at a non-conductive state and keeping the sampling transistor at a conductive state in a time zone during which the signal potential is supplied to the sampling transistor, and the threshold correction operation is executed after potentials of the control input terminal and the output terminal of the drive transistor are initialized by keeping the sampling transistor and the initialization transistor at a conductive state in a time zone during which a predetermined initialization potential is supplied to the sampling transistor and the initialization transistor.