Patent ID: 7112519

Claim:
A semiconductor device manufacturing method comprising the steps of: forming a drain region of a first conductivity type; forming, over a surface of the drain region, alternate layers of a drift region of the first conductivity type and a second semiconductor region of a second conductivity type, wherein the alternate layers are substantially orthogonal to the surface of the drain region; forming, over the drift region, a first semiconductor region of the first conductivity type, wherein the first semiconductor region is broader than the drift region in a direction parallel with the surface of the drain region; forming, over the second semiconductor region and the first semiconductor region, a body region of the second conductivity type; forming a gate trench that penetrates the body region and connects with the first semiconductor region; and filling a gate electrode in the gate trench, wherein, after the alternate layers of the drift region and the second semiconductor region are fo formed, an intermediate first semiconductor region of the first semiconductor type is formed, wherein a connecting region that is the second conductivity type and reaches the second semiconductor region is then formed as an extended portion of the second semiconductor region by adding a second conductivity type impurity to a portion of the intermediate first semiconductor region, and the first semiconductor region is farmed as a region excluding the connecting region from the intermediate first semiconductor region, and wherein the body region is formed for being deposited over the first semiconductor region and the second semiconductor region that includes the connecting region.