Patent ID: 6948112

Claim:
A computer system capable of performing backward error recovery, comprising: a memory unit having a plurality of memory locations; and a memory controller configured to maintain a checksum in one of said memory locations, said memory controller further configured to receive a plurality of requests to update said checksum with a plurality of combined data values, said memory controller configured to combine said checksum to each of said combined data values and to store each of said combined data values, at least one of said combined data values representing a result of combining a first data value with a second data value, wherein said first data value and said second data value are stored at different times in the same memory location of a memory unit, said memory controller further configured to retrieve a plurality of said combined data values, including said one combined data value, in response to a data error and to recover a previous state of a particular memory location by combining each of said retrieved data values to said checksum.