Patent ID: 8222105

Claim:
A method of fabricating a memory device, the method comprising; forming a semiconductor substrate having a first surface; forming a recessed gate in the substrate, wherein the recessed gate defines first and second lateral sides; forming a first source/drain region on the first surface of the semiconductor substrate adjacent a first lateral side of the recessed gate; forming a second source/drain region on the first surface of the semiconductor substrate adjacent a second lateral side of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is recessed into the semiconductor substrate; forming a charge storage device above the semiconductor substrate, wherein the charge storage device is electrically coupled to the first source/drain region; and forming a conductive data line between the charge storage device and the first surface of the semiconductor substrate, wherein the conductive data line is formed to electrically and directly physically contact the second source/drain region in the absence of any separately formed conductive plug extending between the second source/drain region and the conductive data line in a completed construction of the memory device.