Patent ID: 8536619

Claim:
A metal-oxide-semiconductor (MOS) device comprising: a semiconductor substrate having a top surface; a gate stack on the semiconductor substrate; and stressors in the semiconductor substrate on opposing sides of the gate stack, wherein each stressor comprises at least a first portion with a first top surface lower than the top surface of the semiconductor substrate and a second portion having a second top surface higher than the first top surface, and wherein the second portion is directly under a gate spacer on a sidewall of the gate stack, wherein the semiconductor substrate directly under the gate stack is the same material as directly under the stressors, the first portion extending from the second portion to an isolation region, the first top surface of the first portion being planar, an upper surface of the first portion of the stressors being self-aligned with the gate spacer and silicided, an upper surface of the silicide being lower than the top surface of the semiconductor substrate.