Patent ID: 7999570

Claim:
An integrated circuit, comprising: a L-level permutable switching network (L-PSN); wherein the L-PSN comprises: (L+2) levels of conductors, wherein each of the (L+2) levels of conductors comprises I i number of conductors for i=[0:L+1], wherein the i-th level of conductors of I i number of conductors comprises D[i] sets of conductors and each of the D[i] sets of conductors comprises (I i /D[i]) number of conductors for i=[0:L+1], D[0]=1 and D[i]≧1, wherein at least one of the D[i] is at least three for an i selected from [1:L+1], wherein the I i−1 number of conductors of the (i−1)-th level of conductors selectively couple to the I i number of conductors of the i-th level of conductors through at least T1=((I i−1 −D[i]+1)×D[i]) number of switches without requiring traversal of any other conductors for i=[1:L+1]; at least one j selected from [1:L+1], wherein D[j] is at least two, wherein each conductor of the I j−1 number of conductors of the (j−1)-th level of conductors selectively couples to at least (D[j]+1) number of conductors of the I j number of conductors of the j-th level of conductors through a corresponding at least (D[j]+1) number of switches without requiring traversal of any other conductors, wherein the (D[j]+1) number of conductors comprise at least one conductor in each of the D[j] sets of conductors of the I j number of conductors, and wherein the I j−1 number of conductors selectively couple to the I j number of conductors through at least (I j−1 ×D[j]+I j ) number of switches without requiring traversal of any other conductors.