Patent ID: 8453087

Claim:
A method comprising: receiving data corresponding to one or more problematic layout patterns associated with an integrated circuit manufacturing process; receiving data corresponding to a block layout design of a modular component including a plurality of geometric elements and configured to be integrated with one or more integrated circuit designs; scanning a boundary of the block layout design against the one or more problematic layout patterns, the boundary being an outer area of the block layout design configured to be adjacent to the one or more integrated circuit designs; identifying, at the boundary, one or more partial matches of the one or more problematic layout patterns; generating results indicating the one or more partial matches; and modifying the layout design based on the results, wherein modifying the layout design at least includes modifying the layout design to include at least one localized blockage around at least a portion of at least one of the one or more partial matches, and wherein, at the at least one localized blockage, routing and/or placement resources for other geometric elements are either reduced or made unavailable.