Patent ID: 8654970

Claim:
A processor, comprising: an instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); and a cryptographic unit configured to receive instructions for execution from the instruction fetch unit, wherein the instructions include one or more Data Encryption Standard (DES) instructions defined within said ISA, wherein each of the one or more DES instructions includes opcode bits and is executable by the cryptographic unit to implement a portion of a DES cipher that is compliant with Federal Information Processing Standards (FIPS) Publication 46-3, wherein an opcode encoded in the opcode bits of the given DES instruction is sufficient when executed to implement the portion of the DES cipher; wherein in response to receiving a DES key expansion instruction defined within said ISA, the cryptographic unit is further configured to generate one or more of an intermediate set of values from an input key according to the DES cipher, wherein each given member of the intermediate set of values is generated such that upon application of a Permuted Choice 2 (PC 2 ) function of the DES cipher to any given member of the intermediate set, a corresponding expanded cipher key of the DES cipher key schedule is generated.