Patent ID: 8375238

Claim:
A memory system comprising: a memory; a memory controller; and a memory interface electrically connecting the memory and the memory controller to each other, wherein the memory interface includes a data line driven by the memory for transferring data, and a clock line which is driven by the memory controller and transfers read clocks for controlling a timing of outputting the data from the memory to the data line, when the memory outputs N pieces of data, the memory starts outputting N pieces of data in synchronization with first to Nth read clocks consecutively output from the memory controller, stops the outputting of first to (N−1)th pieces of data respectively in synchronization with second to Nth read clocks, and stops the outputting of Nth piece of data after a first predetermined time from stop of output of the Nth read clock, and the memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth read clocks, and takes in the Nth piece of data in a period from start of output of the Nth piece of data based on the Nth read clock to stop of the output of the Nth piece of data, and the memory controller sets an output period of the Nth read clock to be longer than an output period of each of the first to (N−1)th read clocks.