Patent ID: 8203860

Claim:
A semiconductor memory device, comprising: a supply voltage pad; a ground voltage pad; at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad; a first pull-up driver and a first pull-down driver both connected to a first data input/output pad of the at least two data input/output pads; and a second pull-down driver and a second pull-up driver both connected to a second data input/output pad of the at least two data input/output pads, wherein: the first pull-up driver and the first pull-down driver are between the supply voltage pad and the ground voltage pad, respectively, and the first data input/output pad, a number of transistors in the first pull-up driver is less than a number of transistors in the first pull-down driver, and the first data input/output pad is closer to the supply voltage pad than the ground voltage pad, and the second pull-down driver and the second pull-up driver are between ground voltage pad and the supply voltage pad, respectively, and the second data input/output pad, a number of transistors in the second pull-down driver is less than a number of transistors in the second pull-up driver, and the second data input/output pad is closer to the ground voltage pad than the supply voltage pad.