Patent ID: 8166259

Claim:
A memory control apparatus for retrieving a fetch response data corresponding to a fetch request of a processor from a main storage unit and sending out the fetch response data to the processor, the apparatus comprising: a storage unit operable to store the fetch response data retrieved from the main storage unit; a first port operable to receive, while bypassing the storage unit, the fetch response data retrieved from the main storage unit and to set the received fetch response data therein; a second port that sets therein, through the storage unit, the fetch response data retrieved from the main storage unit in a case where the fetch response data cannot be set in the first port; a transmission control unit that transmits the fetch response data to both the storage unit and the first port in a case where the fetch response data retrieved from the main storage unit is a specific data; and a priority control unit that performs priority control to send out the fetch response data set in the first port or the second port to the processor in accordance with a predefined priority.