Patent ID: 7420252

Claim:
A semiconductor device comprising: a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; a first contact disposed on the first doped region, and a second contact disposed on the second doped region; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions, wherein a first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance between edges of the second doped region and the second contact, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.