Patent ID: 8209141

Claim:
A system for automatically generating test patterns for an at-speed structural test of a circuit partition group of an integrated circuit device, said system comprising: an automatic test pattern generator performing a first test pattern generation pass for said circuit partition group, said first test pattern generation pass comprising generating test patterns from a set of available test patterns; and an analyzer determining, during said first test pattern generation pass, test coverage with each test pattern generated and communicating said test coverage to said generator, said test coverage comprising a percentage of simulated faults detected, and said generator further performing the following: stopping said first test pattern generation pass, based on at least one predetermined stopping criterion related to said test coverage, such that only a sub-set of test patterns is generated, said sub-set comprising less than all of said available test patterns in said set; removing at least one test pattern from said sub-set; and after said removing, performing a second test pattern generation pass for said circuit partition group, said second test pattern generation pass comprising generating test patterns from said sub-set.