Patent ID: 8244933

Claim:
An integrated circuit (IC), comprising: core circuitry configured to process input data and provide output data; input/output (IO) circuitry configured to receive the input data, and transmit the output data; wherein the IO circuitry is configured to communicate with a memory bus and a sideband bus; a control circuit configured to provide a selection signal; and an inter-IC communication port coupled between the core circuitry and the IO circuitry and configured to pass the input data and the output data, the inter-IC communication port having a first memory interface and a first memory controller, wherein the control circuit is coupled to the IO circuitry and is configured to provide a first notification in response to configuring the selection signal to select the first memory interface, and the IO circuitry is configured to send the first notification to another IC on the memory bus over the sideband bus; wherein the first memory controller is configured to transmit memory read requests to retrieve the input data and memory write requests with the output data via the IO circuitry to a second memory interface external to the IC; wherein the first memory interface is configured to receive memory read requests for the output data and memory write requests with the input data via the IO circuitry from a second memory controller external to the IC; and wherein the inter-IC communication port is configured to selectively couple either the first memory interface or the first memory controller between the core circuitry and the IO circuitry responsive to the selection signal.