Patent ID: 8659070

Claim:
A semiconductor memory device comprising: a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation layer and a plurality of electrodes formed around the second insulation film, the plurality of electrodes of a memory string being shared with the plurality of electrodes of other memory strings; a plurality of bit lines respectively connected to one end of the plurality of memory strings via a plurality of selection transistors; and a plurality of conductive layers including a memory transistor region and a contact region and extending in two dimensions, the memory transistor region being formed by the plurality of electrodes of the plurality of memory strings, the contact region being arranged in an end part of the plurality of conductive layers, the end part of the plurality of conductive layers being arranged in a first direction perpendicular to a bit line direction, the plurality of conductive layers in the contact region being formed in a step shape in the bit line direction, and both edges of the plurality of conductive layers in the memory transistor region in the bit line direction being aligned respectively.