Patent ID: 8402340

Claim:
A parity-check code-decoder adapted for receiving through a channel at least (N) bits that are to be decoded, each of the (N) bits being encoded through parity-check coding, said parity-check-code decoder treating each of the bits as a bit node, and comprising: a verifying device for multiplying the (N) bit nodes by a parity-check-code matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator for generating a reliability index for each of the bit nodes in accordance with the channel; a reliability-updating device coupled to said verifying device and said reliability generator for using the bit nodes and the check nodes to exchange messages iteratively based on the reliability indices, and following each iteration, updating (N) exchange results corresponding to the (N) columns, respectively; and a recording controller coupled to said reliability-updating device, and including a separator for dividing the parity-check-code matrix into a number (G) of column groups according to column weights of the (N) columns, wherein G≧1, and outputting (N) characterizing signals corresponding to the exchange results, respectively, based on the column weights of each of the column groups, wherein the column weights of the columns belonging to a same column group have a same value, and the characterizing signals of the same column group are expressed using a same bit length, a quantizing determiner coupled to said separator for determining a shift signal for each of the column groups according to the characterizing signals, and a quantizer coupled to said quantizing determiner for quantizing the characterizing signals according to the shift signals for subsequent output.