Patent ID: 8329518

Claim:
A method for manufacturing a thin film transistor array substrate, comprising the following steps: forming a plurality of gate electrodes on a transparent substrate; forming a gate insulating layer, a semiconductor layer, an ohmic contact layer, an electrode layer and a first photo-resist layer on the transparent substrate and the gate electrodes in sequence; patterning the first photo-resist layer to form channels, wherein the channels are formed above the gate electrodes; etching the ohmic contact layer and the electrode layer, so as to remove a portion of the ohmic contact layer and a portion of the electrode layer, and to form a plurality of source electrodes and a plurality of drain electrodes at both sides of the channels, respectively; coating a second photo-resist layer on the patterned first photo-resist layer and in the channels, wherein, after coating the second photo-resist layer, a thickness of the second photo-resist layer in the channels is larger than another thickness of the second photo-resist layer on the patterned first photo-resist layer; using an ashing process to remove the second photo-resist layer on the patterned first photo-resist layer and to allow the second photo-resist layer in the channels to remain therein; etching the semiconductor layer to remove a portion of the semiconductor layer; removing the patterned first photo-resist layer and the second photo-resist layer; forming a passivation layer on the channels, the source electrodes and the drain electrodes; and forming a pixel electrode layer on the passivation layer, wherein the pixel electrode layer is electrically connected to the drain electrodes.