Patent ID: 7656338

Claim:
An analog-digital converter, comprising: an analog signal line which transmits an analog signal; an upper limit voltage line which transmits upper limit voltage of the analog signal; a lower limit voltage line which transmits lower limit voltage of the analog signal; a ramp voltage line which transmits ramp voltage quantized in the range between (the lower limit voltage−ΔV) and (the upper limit voltage+ΔV) by n+k bits (n: 1 or larger natural number) according to a clock signal when ΔV=(the upper limit voltage−the lower limit voltage)×k/2 (k: real number in the range 0<k<1); a comparison circuit which has a first terminal and a second terminal and outputs a comparison result signal indicating comparison between voltage applied to the first terminal and voltage applied to the second terminal from a comparison result output terminal; a reference voltage line connected to the first terminal to transmit reference voltage for determining operation voltage of the comparison circuit; a switching element connected between the second terminal and the comparison result output terminal to have continuity during the period of transmitting the analog signal to the analog signal line; m capacitor element (m: 1 or larger natural number), the capacity of the ith element of which capacitor element (1≦i≦m) is set at 2 m−i ×C (C: positive real number), one end of each of the m capacitor element being connected with the second terminal in parallel; m switching circuit connected with the other end of each of the m capacitor element to perform switching control such that any of the analog signal line, the lower limit voltage line, and the upper limit voltage line can be connected to the switching circuit; a second capacitor element whose capacity is set at C, one end of the second capacitor element being connected with the second terminal; a second switching circuit connected with the other end of the second capacitor element to perform switching control such that any of the analog signal line, the lower limit voltage line, and ramp voltage line can be connected to the second switching circuit; a count line which transmits a count value counting the clock number from the start of the clock signal; an m-bit latch circuit; an n+1-bit latch circuit; and a control circuit connected with the output line of the comparison result output terminal and the count line to control the m switching circuit according to the comparison result signal, sequentially write the comparison result signal outputted through sequential connection between the upper limit voltage line and the m capacitor element to the m-bit latch circuit, and write the count value at the time when the potential of the comparison result signal outputted through connection between the second capacitor element and the ramp voltage line shifts from a first potential to a second potential to the n+1-bit latch circuit.