Patent ID: 7694078

Claim:
A data processing apparatus for processing an at least two dimensional array of data values, the apparatus comprising a main memory ( 12 ) for storing data values from the array; a processing unit ( 10 ) arranged to signal region movement of a sliding region ( 20 , 22 ) in the array, and, between signalling of region movements, to output addresses indicative of locations in the array, the sliding region ( 20 , 22 ) extending along at least two dimensions in the array over pluralities of separately addressable locations; a cache memory unit ( 14 ) coupled between the processing unit ( 10 ) and the main memory ( 12 ), the cache memory unit ( 14 ) comprising a plurality of cache locations ( 142 ) for caching data values addressed by addresses that are adaptively associated with the cache locations, the cache memory unit ( 14 ) being arranged to apply cache replacement, changing the associated addresses and corresponding cached data in case of a cache miss, and to selectively exempt from replacement cache locations that store data values for locations in the sliding region ( 20 , 22 ) that applies at the time of addressing.