Patent ID: 7701017

Claim:
A MOS semiconductor device comprising: 1) a substrate having a major area comprising a first region and a second region, Si surface of the first region being aligned to a {110} plane, and Si surface of the second region being aligned to a {100} plane; 2) a p channel MOSFET comprising: a first gate electrode insulatively disposed over the first region; first source/drain regions formed in the first region with the first gate electrode arranged between the first source/drain regions, the first source/drain regions including a surface region having extrinsic impurities consisting of N atoms; and a first silicide layer formed on the first source/drain regions, and containing N atoms at an areal density of 8.5×10 13 to 8.5×10 14 cm −2 ; and 3) an n channel MOSFET comprising: a second gate electrode insulatively disposed over the second region; second source/drain regions formed in the second region, with the second gate electrode arranged between the second source/drain regions, the second source/drain regions including a surface region having extrinsic impurities consisting of F atoms; and 4) a second silicide layer formed on the second source/drain regions, and containing F atoms at an areal density of not less than 5.0×10 13 cm −2 .