Patent ID: 7247530

Claim:
A method of fabricating an ultrathin SOI memory transistor, comprising: preparing a substrate, including forming an ultrathin SOI layer of the substrate; adjusting the threshold voltage of the SOI layer; depositing a layer of silicon oxide on the SOI layer; patterning and etching the silicon oxide layer to form a sacrificial oxide gate in a gate region; depositing a layer of silicon nitride and forming the silicon nitride into a silicon nitride sidewall for the sacrificial oxide gate; depositing a first layer of amorphous silicon; smoothing the first layer of amorphous silicon by CMP; selectively etching the sacrificial gate oxide; growing a layer of oxide in the gate region; depositing a second layer of amorphous silicon; smoothing the second layer of amorphous silicon by CMP; patterning and etching the first layer of amorphous silicon; implanting ions to form a source region and a drain region; annealing the structure to diffuse the implanted ions; depositing a layer of passivation oxide; patterning and etching the passivation oxide to form contact holes; and metallizing the structure to complete the memory transistor.