Patent ID: 7100022

Claim:
A VLIW processor comprising: first and second register file banks, said first register file bank comprising a first plurality of read ports and write ports, and said second register file bank comprising a second plurality of read ports and write ports; first and second data path blocks, said first data path block comprising a first plurality of execution units, and said second data path block comprising a second plurality of execution units; a first plurality of buses coupling said first plurality of read ports to each of said first and second data path blocks; a second plurality of buses coupling said second plurality of read ports to each of said first and second data path blocks; wherein an operand residing in said first plurality of read ports is concurrently accessed by said first data path block and by said second data path block, wherein said operand is used by only one execution unit in said first data path block, and by only one execution unit in said second data path block, during a single clock cycle and wherein a result of an operation performed in said first data path block is written to only said first plurality of write ports without being written to said second plurality of write ports, wherein said VLIW processor does not include a move bus.