Patent ID: 7761728

Claim:
A system to reset an Inter-Integrated Circuit (I2C) bus slave, the system comprising: an I2C bus master comprising hardware circuits and communicating over a data line and a clock line and comprising a clock module generating a clock signal at a clock signal frequency that is transmitted over the clock line; a hang detection module detecting that the data line is hung; a pulse generation module transmitting specified clock pulses with a specified increased frequency in the range of 1.5 to 3 times the clock signal frequency to the I2C bus slave over the clock line in response to the detected data line hang; the I2C bus slave comprising hardware circuits and communicating with the I2C bus master over the data line and the clock line and comprising a frequency detector module detecting clock pulses at the specified increased frequency; a timer module detecting the specified clock pulses at the specified increased frequency; and a reset module resetting the I2C bus slave in response to the timer module detecting the specified clock pulses.