Patent ID: 6954092

Claim:
A PLL circuit comprising: a phase comparison circuit generating a phase difference signal in accordance with a phase difference between a reference clock signal and a comparison target clock signal; a charge pump circuit for outputting a current in accordance with said phase difference signal; and an oscillation circuit oscillating at a predetermined oscillation frequency in accordance with the control signal generated in accordance with the output current of said charge pump circuit, generating said comparison target clock signal in accordance with the oscillation signal, and outputting it to said phase comparison circuit; wherein said PLL circuit has a locked state detection circuit for detecting whether said PLL circuit is in a locked state; the charge pump circuit comprises first and second transistors connected in series between a first power supply and an output terminal, a third transistor connected between a connection point of said first and second transistors and a second power supply, and a control signal generation circuit; said control signal generation circuit: generates a first control signal for turning on said first transistor in a period in accordance with an effective period of said phase difference signal when it is detected by said locked state detection circuit that the PLL circuit is in the locked state and turning off said first transistor at times other than this in accordance with said phase difference signal and supplies said first control signal to the control terminal of the first transistor, generates a second control signal for turning on said second transistor before said first transistor is turned on, turning off said second transistor after said first transistor is turned off, and holding a level where a desired output current flows when said second transistor is conductive and supplies said second control signal to the control terminal of said second transistor, and generates a third control signal for turning off said third transistor before said second transistor is turned on and turning on said third transistor after said second transistor is turned off and supplies said third control signal to the control terminal of said third transistor; and said first, second and third control signals are generated by said control generation circuit in accordance with said phase difference signal.