Patent ID: 6965991

Claim:
A reconfigurable register file system comprising: an instruction register for storing an instruction specifying an operational requirement; a reconfigurable register file comprising an odd register file having at least one data read port, and an even register file having at least one data read port; an execution unit connected to said data read ports of the odd and even register files; and port usage control logic connected to the instruction register and the reconfigurable register file to control the odd register file and the even register file port address input so that data read port lines change only as needed to support the operational requirement specified by the instruction, wherein the port usage control logic further comprises odd and even address control latches which are clocked every cycle in response to the clock input and which maintain their same state when required by the decoding of an instruction by recirculating their outputs back to odd and even input multiplexers, respectively, wherein the port usage control logic further comprises gating circuitry for providing a control input to said odd and even input multiplexers whereby new data from a bit field of the instruction register is introduced into the odd and even register files for a first state and data at the outputs of the odd and even address control latches is recirculated for a second state.