Patent ID: 8174920

Claim:
A semiconductor memory device comprising: a plurality of memory cells respectively comprising a body in an electrically floating state and configured to store data based on number of carriers within the body; word lines configured to function as gates of the memory cells; a first bit line and a second bit line configured to transmit data to the memory cells or from the memory cells; a first sense node and a second sense node corresponding to the first bit line and the second bit line, respectively; a first transfer gate connected between the first bit line and the first sense node; a second transfer gate connected between the second bit line and the second sense node; a latch circuit configured to latch data from the first bit line to the first sense node, and to latch data from the second bit line to the second sense node; a first data line configured to read data latched to the first sense node to outside, or to transmit data from outside to the first sense node; and a second data line configured to read data latched to the second sense node to outside, or to transmit data from outside to the second sense node, wherein write data is transmitted from the first and second data lines to the first and second sense nodes corresponding to selected memory cells before the first and second transfer gates are set to be a conductive state, when writing data into the selected memory cells to be written out of the memory cells, and write data in the first and second sense nodes corresponding to the selected memory cells are started to be written into the selected memory cells, when the first and second transfer gates are set to be a conductive state.