Patent ID: 7075352

Claim:
A pulse generator comprising a plurality of unit cells, wherein an n th unit cell (n is a natural number more than 2) generates a pulse in response to a divided-by-N clock signal (N is a natural number), a signal output from an (nâˆ’1) th unit cell and a signal output from an (n+1) th unit cell, wherein the n th unit cell comprises: a first NAND gate that NANDs the signal output from the (nâˆ’1) th unit cell and the signal output from the (n+1) th unit cell; a first inverter that inverts a signal output from the first NAND gate; a second NAND gate that NANDs the divided-by-N clock signal and a signal output from the first inverter; a second inverter that inverts a signal output from the second NAND gate and outputs the pulse as an inverted signal; and a latch that latches a reset signal and the signal output from the second NAND gate.