Patent ID: 6842396

Claim:
A semiconductor memory device which inputs and outputs data in synchronization with a rise and fall of an external clock, comprising: a memory cell array storing data; a clock generating circuit generating first and second internal clocks corresponding to the rise and fall of said external clock, respectively; a data output circuit receiving said first and second internal clocks to output the data read from said memory cell array to outside based on said first and second internal clocks; a data strobe signal output circuit receiving said first and second internal clocks, generating a data strobe signal coinciding with or in synchronization with an output timing of said data outputted to outside from said data output circuit, and outputting said data strobe signal to outside based on said first and second internal clocks; and an internal clock control circuit receiving said first and second internal clocks, detecting an operating frequency of the semiconductor memory device based on said first and second internal clocks, and controlling a transmission period during which said first and second internal clocks generated in said clock generating circuit are transmitted to said data output circuit and said data strobe signal output circuit, based on said operating frequency.