Patent ID: 7009441

Claim:
A phase multiplier subcircuit, comprising: first and second subcircuit power supply terminals; a PULLUPBIAS subcircuit terminal; a COMMON subcircuit terminal; INA and /INB subcircuit terminals; OUTA, /OUTB, and OUTB subcircuit terminals; a first dual-gate transistor having a single drain, a first gate coupled to the OUTB subcircuit terminal, a second gate coupled to the /INB subcircuit terminal, and a single source coupled to the COMMON subcircuit terminal; a first transistor having a gate and a drain coupled to the single drain of the first dual-gate transistor, and a source coupled to the first subcircuit power supply terminal; a second transistor having a drain coupled to a BIASP integration node, a gate coupled to the gate of the first transistor, and a source coupled to the first subcircuit power supply terminal; a third transistor having a drain coupled to the BIASP node, a gate coupled to the PULLUPBIAS subcircuit terminal, and a source coupled to the second subcircuit power supply terminal; a fourth transistor having a drain coupled to a BIASN node, a gate coupled to the BIASP node, and a source coupled to the second subcircuit power supply terminal; a fifth transistor having a gate and a drain coupled to the BIASN node, and a source coupled to the first subcircuit power supply terminal; a second dual-gate transistor having a single drain, a first gate coupled to the BIASP node, a second gate coupled to the INA subcircuit terminal, and a single source coupled to the second subcircuit power supply terminal; a third dual-gate transistor having a single drain coupled to the single drain of the second dual-gate transistor, a first gate coupled to the BIASN node, a second gate coupled to the INA subcircuit terminal, and a single source coupled to the first subcircuit power supply terminal; a fourth dual-gate transistor having a single drain coupled to the OUTA subcircuit terminal, a first gate coupled to the BIASP node, a second gate coupled to the single drain of the third dual-gate transistor, and a single source coupled to the second subcircuit power supply terminal; a fifth dual-gate transistor having a single drain coupled to the OUTA subcircuit terminal, a first gate coupled to the BIASN node, a second gate coupled to the drain of the third dual-gate transistor, and a single source coupled to the first subcircuit power supply terminal; a first inverter having an output terminal coupled to the /OUTB subcircuit terminal, and an input terminal coupled to the OUTA subcircuit terminal; and a second inverter having an output terminal coupled to the OUTB subcircuit terminal, and an input terminal coupled to the /OUTB subcircuit terminal.