Patent ID: 6958712

Claim:
An apparatus for generating a channelization code, comprising: a binary counter circuit that is arranged to: receive a spreading factor signal and a clock signal, provide a binary count signal that is responsive to the clock signal, and reset the binary counter circuit when the binary count signal reaches a limit number that is associated with a spreading factor, wherein the spreading factor is associated with the spreading factor signal; a code logic circuit that is arranged to: receive a code number signal and the spreading factor signal, and provide a right-justified code signal in response to the code number signal and the spreading factor signal, wherein the right-justified code signal corresponds to a right justified version of the code number signal; a register circuit that is arranged to: receive the right-justified code signal and the clock signal, store the right-justified code signal in response to the clock signal, and provide the stored right-justified code signal as a stored code signal; and a channelization logic circuit that is arranged to: receive the stored code signal and the binary count signal, and provide the channelization code in response to the stored code signal and the binary count signal such that the channelization code is associated with the code number and the spreading factor.