Patent ID: 8163597

Claim:
A method of making a semiconductor device, comprising: providing a first sacrificial carrier; forming a first conductive layer over the first sacrificial carrier; forming a first solder bump over the first conductive layer; depositing a no-flow underfill material over the first sacrificial carrier, first conductive layer, and first solder bump; compressing a first semiconductor die or component into the no-flow underfill material to electrically contact the first conductive layer; planarizing a first surface of the no-flow underfill material and first solder bump; forming a first interconnect structure over the first surface of the no-flow underfill material, the first interconnect structure being electrically connected to the first solder bump; mounting a second sacrificial carrier over the first interconnect structure; removing the first sacrificial carrier; forming a second interconnect structure over a second surface of the no-flow underfill material opposite the first interconnect structure, the second interconnect structure being electrically connected to the first solder bump, first interconnect structure, and first semiconductor die or component; and removing the second sacrificial carrier.