Patent ID: 7135908

Claim:
A circuit comprising: signal input (IN) for receiving an input signal (s(t)), a digital input stage ( 15 ) being designed for operation at a supply voltage (VDD), the digital input stage ( 15 ) comprising: CMOS transistors sensitive to voltages across transistor nodes going beyond a voltage limit (V max ) an input (IINV), voltage limiting means (B) being arranged between the signal input (IN) and the input (IINV) for limiting voltages at the input (IINV) to the supply voltage (VDD), the voltage limiting means (B) comprising: an input switch (ns) being controllable by the state of the input signal (s(t)), means for over-voltage protection (A) being situated between the signal input (IN) and the supply voltage (VDD), the means for over-voltage protection (A) comprising at least one active circuit element which functions so as to mimic at least a breakdown part of a zener function, and speed boost means (C) having at least one capacitive element (Cb) speeding up the turn-on/turn-off behavior of the input switch (ns).