Patent ID: 8131977

Claim:
A microprocessor comprising: a processor core that performs pipeline processing; an instruction analyzing section that analyzes an instruction to be processed by the processor core and outputs analysis information indicating whether the instruction matches with a specific instruction that is previously defined; and a memory having a tag storage unit that stores the analysis information and a data storage unit that temporarily stores the instruction in relation to the analysis information, wherein the processor core includes: an instruction fetch unit that fetches the instruction stored in the memory; an instruction decode unit that decodes the instruction fetched by the instruction fetch unit; an instruction execute unit that executes the instruction decoded by the instruction decode unit; and a specific instruction execute controller that reads out the analysis information stored in the memory and controls operation of at least one of the instruction fetch unit and the instruction decode unit when the analysis information indicates that the instruction matches with the specific instruction, wherein, when a no operation instruction, for which no processing is required, is defined as the specific instruction and the analysis information indicates that the instruction matches with the no operation instruction, the memory inhibits the instruction from being written into the data storage unit, and the specific instruction execute controller instructs the instruction decode unit to not perform a decoding operation.