Patent ID: 8164938

Claim:
A semiconductor memory device comprising: a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored; a first MOS switch configured to connect the input of the first inverter and a write bit line; a first MOS transistor having a gate connected to the output of the first inverter; and a second MOS switch configured to connect the first MOS transistor to a read bit line, wherein the first MOS switch is a CMOS switch including a P-channel MOS transistor and an N-channel MOS transistor, and the first and second inverters have different sizes, a source power supply to a P-channel MOS transistor included in the second inverter is different from a source power supply to a P-channel MOS transistor included in the first inverter, and a source power supply to an N-channel MOS transistor included in the second inverter is different from a source power supply to an N-channel MOS transistor included in the first inverter.