Patent ID: 7193311

Claim:
A multi-chip circuit module comprising: a multi-layered wiring section formed of a plurality of unit wiring layers, each said unit wiring layer having a preset circuit pattern formed in an insulating layer by etching away a portion of the insulating layer and depositing a wiring material to fill the pattern formed by the etch, each said unit wiring layer further comprising at least one via-hole, and having a planarized surface providing for a substantially flat surface for the formation of a subsequent layer, such that a top level of each wiring layer is at a same level as its corresponding insulating layer, each respective unit wiring layer being layered on said planarized surface of a subjacent unit wiring layer, at least one via-hole in each respective unit wiring layer being located on a via-hole in a subjacent unit wiring layer in order to provide a via-on-via structure, and a connection terminal provided on an outermost layer of the plurality of unit wiring layers; a semiconductor chip mounted on the major surface of at least one outermost unit wiring layer of said multi-layered wiring section; and a sealing resin layer provided on the major surface of the outermost unit wiring layer for sealing the semiconductor chip and the connection terminal; characterized in that a polishing processing of polishing said semiconductor chip and for exposing said connection terminal is applied to said sealing resin layer, whereby the thickness of the circuit module is reduced.