Patent ID: 7911822

Claim:
Integrated circuit, comprising: a plurality of bit-lines (bl), a plurality of word-lines (wl), and a plurality of memory cells (MC) coupled between a separate bit-line/word-line pair of the plurality of bit-lines (bl) and word-lines (wl) for storing data in a selected memory cell (MC); wherein each memory cell (MC) comprises: a selecting unit (T) with an effective resistance of V dd /I m , where V dd is a supply voltage of the selected memory cell (MC) applied to each of the bit-lines (bl) and the word-lines (wl), and I m is a maximum drive current (I m ) of the selecting unit (T); and a programmable phase-change resistor (R) with a resistance of R pc ; wherein a ratio of the resistance R pc of the phase-change resistor (R) relative to the effective resistance V dd /I m of the selecting unit (T) is greater than 1, as follows: R pc *I m /V dd >1, where ‘*’ represents a multiplication operation and ‘/’ represents a division operation.