Patent ID: 7606982

Claim:
A semiconductor memory device, comprising: a plurality of ports; at least one shared memory region of a memory cell array accessible through the ports; and a data transmission controller coupled to the shared memory region and the ports, wherein the data transmission controller is configured to apply a read command of a plurality of read operation commands received through a first one of the ports in association with a read operation to the shared memory region after a write command of a plurality of write operation commands received through a second one of the ports in association with a write operation before applying any other commands associated with the read operation and the write operation to the shared memory region when at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent; wherein the data transmission controller comprises: a command decoder coupled to the ports and configured to combine signals received through the ports associated with the read operation and the write operation and configured to generate a port decoding signal; and a port permission signal generator coupled to the command decoder and configured to generate a port permission signal in response to the port decoding signal; wherein the data transmission controller is further configured to apply the read command after the write command before applying any other commands to the shared memory region in response to the port permission signal.