Patent ID: 7122430

Claim:
A method for manufacturing a semiconductor memory having a memory cell site and a peripheral site disposed around the memory cell site, a memory cell matrix disposed in the memory cell site includes a plurality of cell columns arranged along a row-direction, peripheral circuitry disposed in the peripheral site being configured to drive the memory cell transistors and select transistors and to read information from the memory cell transistors, the method comprising: forming the cell site gate insulator on the semiconductor substrate; depositing the lower conductive layer on the cell site gate insulator; depositing an inter-electrode dielectrics on the lower conductive layers; opening an inter-electrode through-hole in the inter-electrode dielectric; depositing an upper conductive layer on the inter-electrode dielectric; removing selectively the upper conductive layer, the inter-electrode dielectric, the lower conductive layer and the cell site gate insulator at the peripheral site so as to expose a portion of the semiconductor substrate; and forming selectively a peripheral site gate insulator on the exposed portion of the semiconductor substrate, the peripheral site gate insulator having a thickness thinner than the cell site gate insulator.