Patent ID: 8760131

Claim:
A voltage regulator receiving an input voltage and generating an output voltage, comprising: a power device comprising an NMOS transistor having a drain terminal coupled to the input voltage, a source terminal providing the output voltage and a gate terminal receiving a gate drive signal; and an integrated AC/DC control loop configured to access the output voltage and to generate the gate drive signal based on a value of the output voltage in relation to a first reference voltage and a second reference voltage, the integrated AC/DC control loop comprising an AC control portion and a DC control portion, wherein: the AC control portion is configured to access a difference between a voltage indicative of the output voltage and the first reference voltage, the AC control portion generating a gate drive control signal, the gate drive control signal being AC coupled to the gate terminal of the power device, an AC component only of the gate drive control signal being coupled to the gate terminal of the power device as an AC component of the gate drive signal, the AC control portion being powered by the input voltage, wherein the voltage regulator further comprises a voltage offset circuit configured to receive the input voltage and to generate an offset input voltage, the offset input voltage being the input voltage decreased by an offset voltage, and the voltage regulator further comprises a low pass filter configured to filter the offset input voltage to remove high frequency noise and to provide a filtered offset input voltage as the first reference voltage to the AC control portion; and the DC control portion is configured to access a difference between the gate drive control signal and the second reference voltage, the DC control portion controlling a DC voltage level only of the gate drive signal at the gate terminal of the power device, the DC control portion being powered by a high supply voltage greater than the input voltage.