Patent ID: 7091080

Claim:
A process for manufacturing a planar power semiconductor device comprising: providing a semiconductor die including an epitaxially grown silicon layer of a first conductivity formed over a substrate; designating an active area, said active area being a portion of said epitaxially grown silicon layer in which channel regions are formed; implanting dopants of a second conductivity in all of said active area of said epitaxially grown silicon layer; forming a plurality of spaced channel regions of said second conductivity in said active area of said epitaxially grown silicon layer, each channel region being spaced from another channel region by a first conductivity region in said epitaxially grown silicon layer; forming a source region of said first conductivity in each of said channel regions, each source region being less wide and less deep than a channel region in which it is formed; and forming a horizontally oriented gate structure over said epitaxially grown silicon layer and at least each channel region.