Patent ID: 7387917

Claim:
A process of fabricating a ball grid array package substrate, comprising the steps, executed in the order listed, of: (A) forming a first blind via hole, opened at a side thereof and having a closed portion at an opposite side thereof, through a copper clad laminate using a laser; (B) forming first copper plating layers on copper foil layers and on a wall of the first blind via hole of the copper clad laminate, and forming a predetermined circuit pattern on the copper foil layer and the first copper plating layer, wherein the copper foil layer and the first copper plating layer are close to an open portion of the first blind via hole; (C) repeating the steps (A) to (B) to prepare another copper clad laminate which has a second blind via hole and a predetermined circuit pattern formed on a side thereof; (D) forming an insulating layer having at least one connection part formed in the insulating layer; (E) layering two copper clad laminates on both sides of the insulating layer so that open portions of the first and second blind via holes face the insulating layer, and pressing the two copper clad laminates and the insulating layer to achieve lamination; (F) forming a through hole through the copper foil layers and the first copper plating layers, wherein the copper foil layers and the first copper plating layers constitute external layers, of the two copper clad laminates; (G) forming second copper plating layers on the first copper plating layers and on a wall of the through hole, and forming external layer circuit patterns, wherein the external layer circuit patterns includes a wire bonding pad and a solder ball pad, on the copper foil layers, the first copper plating layers, and the second copper plating layers; and (H) layering solder resists on the external layer circuit patterns, and forming openings, wherein the openings correspond to the wire bonding pad and the solder ball pad, through the solder resists.