Patent ID: 7408962

Claim:
A demultiplexer apparatus comprising a plurality of integrating circuits which operate in parallel, wherein said plurality of integrating circuits receive input time-series binary data commonly, each of the plurality of integrating circuits converts said input binary data in a current stage corresponding into multi-value data in said current stage, and generates recovery data in said current stage based on said multi-value data and recovery data from one of said plurality of integrating circuits in a stage immediately or more previous to said current stage integrating circuit, and said plurality of integrating circuits output the generated recovery data as parallel data to said input binary data, wherein each of said plurality of integrating circuits generates said recovery data in said current stage based on said multi-value data in said current stage and said recovery data from said immediately previous integrating circuit to said current stage integrating circuit, and outputs the generated recovery data to one of said plurality of integrating circuits in a next stage, wherein each of said plurality of integrating circuits comprises a converting unit which converts said input binary data into said multi-value data for every a predetermined bit quantity, wherein said converting unit adds said input binary data for every n bits (n is an integer of 2 or more) to generate said multi-value data, wherein said converting unit comprises an adding circuit, wherein said adding circuit comprises: a capacitor; and a switch, and said switch operates in response to a clock signal to carry out said addition such that a charge is stored in said capacitor and then the stored charge is discharged from said capacitor based on said input binary data, or such that the charge is discharged from said capacitor and then said capacitor is charged based on said input binary data.