Patent ID: 8700851

Claim:
An information processing apparatus comprising: a main memory, which stores a program compiled by a compiler, the program being divided into pre-compiled units of program blocks that may refer to each other in an instruction sequence of the program; a local memory including 1 to n memory banks, where n is a natural number, each memory bank being a fixed allocated area having sufficient memory space to cache at least one program block, wherein a memory bank i is selected as a current memory bank for caching; a processor, which processes the instruction sequence of the program by sequentially referring to one or more cached program blocks containing the division of the program as required during the flow of the instruction sequence, wherein, when the instruction sequence references a program block that has not been cached in a memory bank, the processor caches the referenced program block into the current memory bank if there is sufficient memory space available, and, if there is insufficient memory space available, the processor selects a memory bank (i+1) mod n as the current memory bank, deletes all previously-cached program blocks within, and caches the referenced program block into the current memory bank, and wherein the processor stores reference destination information, including bank identification information and local memory address information, of a cached program block at the current memory bank so as to be referenced during the instruction sequence.