Patent ID: 6894364

Claim:
An integrated device having a capacitor in an interconnect system, comprising: a plurality of metal lines; a planarized first insulating layer disposed over the metal lines; an etch stop layer disposed over the planarized first insulating layer; a second insulating layer disposed over the etch stop layer; a first via, a second via and the capacitor configured in the first insulating layer, wherein the first via is configured over and in contact with the capacitor element, the capacitor is configured over and in contact with one of the metal lines, and the second via is configured over and in contact with another metal line; and a first conductive line and a second conductive line configured in the second insulating layer and the etch stop layer, wherein the first conductive line is configured over and connected to the first via and the second conductive line is configured over and connected to the second via, wherein said metal lines, said first and second vias, said first and second conductive lines have tapered sidewalls and a barrier lining on said sidewalls.