Patent ID: 8606988

Claim:
A flash memory control circuit, for transferring data from a host system to a flash memory chip having a first flash memory and a second flash memory, wherein the first flash memory and the second flash memory respectively have a plurality of memory cell arrays, and each of the memory cell arrays at least has a lower page, a middle page and an upper page, wherein write speeds of the lower pages are greater than write speeds of the middle pages and the write speeds of the middle page are greater than write speeds of the upper pages, the flash memory control circuit comprising: a microprocessor unit; a first interface unit, coupled to the microprocessor unit, and configured to couple to the first flash memory and the second flash memory; a second interface unit, coupled to the microprocessor unit, and configured to couple to the host system; a buffer memory, coupled to the microprocessor unit, and configured to temporarily store the data, wherein the data has a 1 st page data, a 2 nd page data, a 3 rd page data, a 4 th page data, a 5 th page data, and a 6 th page data, wherein the microprocessor unit executes a plurality of instructions to: group a 0 th page, a 1 st page and a 2 nd page of the first flash memory into a first data transfer unit set and group a 0 th page, a 1 st page and a 2 nd page of the second flash memory into a second data transfer unit set, wherein the 0 th pages of the first flash memory and the second flash memory are the lower pages, the 1 st pages of the first flash memory and the second flash memory are the middle pages, the 2 nd pages of the first flash memory and the second flash memory are the upper pages, the 0 th page, the 1 st page and the 2 nd page of the first flash memory share a common memory cell, and the 0 th page, the 1 st page and the 2nd page of the second flash memory share a common memory cell; transfer the 1 st page data into the first flash memory through the first interface unit; immediately after the 1 st page data is programmed into the 0 th page of the first flash memory, transfer the 2 nd page data into the first flash memory through the first interface unit; immediately after the 2nd page data is programmed into the 1 st page of the first flash memory, transfer the 3 rd page data into the first flash memory through the first interface unit; while the 3 rd page data is programmed into the 2 nd page of the first flash memory, transfer the 4 th page data into the second flash memory through the first interface unit; immediately after the 4 th page data is programmed into the 0 th page of the second flash memory, transfer the 5 th page data into the second flash memory through the first interface unit; and immediately after the 5 th page data is programmed into the 1 st page of the second flash memory, transfer the 6 th page data into the second flash memory through the first interface unit, program the 6 th page data into the 2 nd page of the second flash memory.