Patent ID: 7117232

Claim:
An apparatus comprising: a decoder to receive a control signal of a packed instruction format that can specify a variable data size, an operation type, a first source operand, and a second source operand; a storage location corresponding to the first source operand to hold a first packed data having a set of source data elements of a size specified by the variable data size; said decoder to generate a decoded signal including a first field of control bits indicating a first number of bits less than or equal to the variable data size and corresponding to a comparison between the second source operand and the variable data size, and a second field of one or more select bits according to the operation type; a correction circuit to produce a set of destination data elements corresponding to the set of source data element, said decoder coupled with the correction circuit to select, according to the second field of one or more select bits, a corresponding replacement bit for each element of the set of source data elements to correct said first number of bits in each element of the set of destination data elements according to the first field of control bits.