Patent ID: 7627712

Claim:
A computational system comprising: a multi-plane solid state memory device having an architecture that includes a first plane and a second plane, each of the first plane and the second plane including a plurality of blocks, each block of the plurality of blocks including a plurality of pages; and a controller coupled to the multi-plane solid state memory device and configured to communicate with a second computational system, the controller including: block management software configured to communicate with the second computational system using a virtual block address; and a device driver configured to communicate with the multi-plane solid state memory device and configured to provide the virtual block address to the block management software to enable the block management software to communicate with the second computational system without knowledge of the architecture of the multi-plane solid state memory device, wherein the virtual block address represents two or more blocks including a first block from the plurality of blocks included in the first plane and a second block from the plurality of blocks included in the second plane; wherein the controller is configured to write a first virtually addressed page to a first page of the first plane and to write a second virtually addressed page to a second page of the second plane, wherein the second virtually addressed page is located sequentially next to the first virtually addressed page, and wherein writing the first virtually addressed page and writing the second virtually addressed page are performed substantially simultaneously.