Patent ID: 7449401

Claim:
A method for fabricating a semiconductor device, comprising: preparing a substrate structure having device isolation regions, first active regions, and a second active region; rounding a border region between the individual first active regions and the second active region; forming a gate insulation layer over the substrate structure; performing a gate oxide pre-cleaning process to obtain a height difference between the individual first active regions and the individual device isolation regions, thereby forming a resultant structure; forming gate patterns in a step structure on the resultant structure over the border region between the individual first active regions and the second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; forming spacers on lateral walls of the gate patterns; forming first cell junction regions in the first active regions; and forming a second cell junction region in the second active region.