Patent ID: 8885409

Claim:
A nonvolatile memory device, comprising: an array of nonvolatile memory cells; a plurality of page buffers configured to receive a corresponding plurality of pages of data read from a target page of nonvolatile memory cells in said array using different read voltage conditions for each of the plurality of pages of data being read; a control circuit electrically coupled to said plurality of page buffers, said control circuit configured to perform a test operation by driving said plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits that are derived from at least two of the plurality of pages of data read from the target page of the nonvolatile memory cells using the different read voltage conditions; and an input/output device configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device; and wherein the test operation comprises: storing first data, which is read from the target page using first read voltage conditions, in a first of the plurality of page buffers; storing second data, which is read from the target page using second read voltage conditions that differ from the first read voltage conditions, in a second of the plurality of page buffers; and changing third data in a third of the plurality of page buffers using at least part of the first data transferred from the first page buffer and at least part of the second data transferred from the second page buffer to generate data, which is the same as bit-wise XOR data with respect to the first data and the second data.