Patent ID: 7152138

Claim:
A system-on-a-chip comprising: a microprocessor; a non-volatile imperfect semiconductor memory device; a memory controller separate from the microprocessor and transferring data between the microprocessor and the non-volatile semiconductor imperfect memory device; a buffer memory receiving plural data blocks from the microprocessor and sending the plural data blocks to the non-volatile semiconductor-based imperfect memory device; and a buffer manager including (1) a hardware-implemented logic block managing transfer of the plural data blocks between the microprocessor and the non-volatile semiconductor-based imperfect memory device, and (2) a memory mapping block receiving from the non-volatile semiconductor-based imperfect memory device a memory map indicating reserved memory locations within the non-volatile semiconductor-based imperfect memory device, wherein the buffer manager enables the microprocessor to access a first data block at a first location within the buffer memory while a second data block is concurrently written to the non-volatile semiconductor-based imperfect memory device from a second location within the buffer memory, wherein the buffer manager receives plural set-up information blocks from the microprocessor, wherein each of the set-up information blocks comprises information to transfer the plural data blocks between the microprocessor and the non-volatile semiconductor-based imperfect memory device.