Patent ID: 7414898

Claim:
A semiconductor memory device comprises: an active interval security means for generating security signals activated during a first predetermined operation period corresponding to a row active signal and a second predetermined operation period corresponding to a column active signal; an active driving signal generating means for generating an active driving signal, responsive to the security signals; a standby driving means for keeping an internal voltage to a predetermined level; and an active driving means, which is additionally driven based on the active driving signal to hold the internal voltage, wherein the active interval security means includes: a row-active interval sensing means for sensing the first predetermined operation period corresponding to the row active signal; and a column-active interval security signal generating means for sensing the second predetermined operation period corresponding to the column active signal, wherein the row-active interval sensing means includes: an interval end signal generating means for generating an interval end signal which represents end of the first predetermined operation period; and a row-active interval security signal generating means, responsive to the row-active signal and the interval end signal, for generating a row-active interval security signal activated during first predetermined operation period, wherein the security signals includes the row-active interval security signal.