Patent ID: 7631348

Claim:
A computer system comprising: a CPU; a low pin count (LPC) bus coupled to the CPU; an integrated circuit (IC) device interface coupled to the LPC bus; and a memory medium coupled to the CPU; wherein the memory medium stores program instructions which are executable by the CPU to: receive a request for access; receive first information from a first IC device coupled to the IC device interface, wherein the first IC device is operable to be carried by a user, and wherein the first information is received from the first IC device during one or more special read cycles of the LPC bus; determine a result for the request for access, wherein, in determining the result for the request, the result is based on at least a portion of the first information; if the result indicates the request for access is to be granted, grant said access; and if the result indicates the request for access is to be denied, deny said access: wherein the special read cycles are reserved type cycles of the LPC bus, wherein the reserved type cycles are associated with one or more trusted channels.