Patent ID: 7349223

Claim:
A test apparatus for an integrated circuit wafer, comprising: a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface; a probe chip substrate comprising a probe surface and a connector surface, a plurality of probe springs on the probe surface, a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection; at least one intermediate connector located between the motherboard substrate and the probe chip substrate, the intermediate connector comprising at least one electrically conductive connection between each of the plurality of electrical contacts on the probe chip substrate and each of the electrical conductors on the bottom surface of the motherboard substrate; a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member; and a stiffening ring fixedly attached to the probe chip substrate through the compliant member; wherein the probe chip substrate and the stiffening ring are supported by the compliant member relative to the motherboard.