Patent ID: 8218612

Claim:
A timing error detector, adapted for generating a timing error instant estimation value with respect to a receiver side effective data sequence (EDS) and an error signal, the timing error detector, together with a loop filter (LPF), a first signal converter, and a voltage control oscillator (VCO) constituting a timing loop employed in a receiver of a communication system that uses a Tomlinson-Harashima precoder (THP) in a transmitter of the communication system, the timing error detector comprising: a first subtractor, for obtaining a transmitter side EDS estimation value by subtracting the error signal from the receiver side EDS; a first delayer, for generating a first delayed signal by performing a delaying process to the transmitter side EDS estimation value; a second delayer, for generating a delayed transmitter side EDS estimation value by performing a delaying process to the first delayed signal; a second subtractor, for generating a difference signal by subtracting the delayed transmitter side EDS estimation value from the transmitter side EDS estimation value; a third delayer, for generating a delayed error signal by performing a delaying process to the error signal; and a first multiplier, for generating the timing error instant estimation value by multiplying the difference signal with the delayed error signal.