Patent ID: 7898080

Claim:
A power semiconductor device comprising a semiconductor chip stack with power field effect transistors connected in a bridge circuit, parallel circuit or series circuit, the power semiconductor device comprising a base power semiconductor chip with a first large-area external electrode on each of a top side and rear side, the base power semiconductor chip carrying a first stacked power semiconductor chip that is surface-mounted with a first large-area external electrode on the first large-area external electrode of the top side of the base power semiconductor chip, a first metallic structured spacer being arranged between the base power semiconductor chip and the first stacked power semiconductor chip, the first metallic structured spacer electrically connecting the first large-area external electrode on the top side of the base power semiconductor chip with the first large-area external electrode of the first stacked power semiconductor chip, the structure of said first metallic structured spacer comprising at least one cutout for a non-surface-mountable connecting element of the base power semiconductor chip, wherein a drain electrode is arranged as a large-area external electrode on the rear side of the base power semiconductor chip and two source electrodes are arranged on the top side of the base semiconductor chip, the top side of the base semiconductor chip, the top side of the base semiconductor chip having two gate electrodes that are electrically connected as non-surface-mountable external electrodes to a circuit carrier via bonding wires.