Patent ID: 7416946

Claim:
A method of manufacturing a semiconductor device, comprising: forming a drain silicide on a semiconductor substrate; forming a drain region at both sides of the drain silicide; forming a gate nitride layer on the drain silicide; forming a first epitaxial layer on lateral sides of the gate nitride layer; forming a protection nitride layer on the first epitaxial layer and the gate nitride layer; etching the protection nitride layer and the gate nitride layer to form a trench; forming a first gate insulation layer on the drain silicide; forming a gate oxide layer on a portion of the first epitaxial layer exposed by the trench; forming a second epitaxial layer on the first epitaxial layer after removal of the protection nitride layer; filling the trench with polysilicon to form a gate electrode; ion-implanting impurities on the second epitaxial layer to form a source region; forming a second gate insulation layer on the gate electrode and the gate oxide layer; forming a source suicide on the second gate insulation layer; forming an interlayer insulation layer on the second epitaxial layer, the source region and the source silicide; forming a source contact hole to expose a portion of the source silicide; forming a gate contact hole to expose a portion of the gate electrode; and forming a drain contact hole to expose a portion of the drain silicide.