Patent ID: 7291521

Claim:
A semiconductor fabrication method, comprising: introducing a counter doping impurity distribution having a first conductivity type into a semiconductor layer of a semiconductor-on-insulator (SOI) wafer having a second conductivity type, the SOI wafer including the semiconductor layer overlying a buried oxide (BOX) layer; wherein the top semiconductor layer has a first thickness at a first region in the wafer and a second thickness at a second region in the wafer wherein the first thickness is less than the second thickness; wherein the counter doping impurity distribution is introduced wherein a first percentage of the impurity distribution is located in the semiconductor layer at the first region and wherein a second percentage of the impurity does is located in the semiconductor layer at the second region, wherein the first percentage is less than the first; wherein the counter doping impurity distribution reduces a difference in net charge between the first region and the second region.