Patent ID: 7667498

Claim:
A circuit comprising: a first transistor stack that receives an input signal, a voltage reference, a reference potential, a clock signal and an inverted clock signal, and that generates an output signal that is an inverse of the input signal; a first inverter that receives the output signal from the first transistor stack; a second transistor stack that receives the voltage reference, the reference potential, the clock signal and the inverted clock signal, and that generates an output signal that is an inverse of an output signal from the first inverter; and a pass control circuit that includes first and second transistors, wherein first terminals of the first and second transistors are coupled together and receive the output signal of the second transistor stack, control terminals of the first and second transistors receive the clock signal and the inverted clock signal, respectively, and second terminals of the first and second transistors are coupled together and output the output signal of the second transistor stack; and a logic circuit that receives an external clock signal and a standby signal, and that generates the clock signal.