Patent ID: 7129775

Claim:
A circuit of a current mirror configuration having three branches to measure a load current in an integrated circuit is comprising: a first biasing branch comprising a current source and a first and a second NMOS transistor, wherein the current source is connected between VDD voltage and the drain of the first transistor, said drain is connected to the gate of the first transistor, the source of the first transistor is connected to the gate and to the drain of the second transistor, and the source of the second transistor is connected to ground; a second load branch comprising a load and a first and a second NMOS transistor, wherein the load is connected between VDD voltage and the drain of the first transistor of the load branch, the gate of the first transistor of the toad branch is connected to the gate of the first transistor of said biasing branch and the source of the first transistor of the load branch is connected to the gate and to the drain of the second transistor of the load branch and the source of the second transistor of the load branch is connected to ground; and a third measurement branch in which a current, which is proportional to a current through said second load branch and can hence be used for measurement purposes, is generated, wherein said measurement branch is comprising a first and a second NMOS transistor, wherein the gate of the first transistor of the measurement branch is connected to the gate of the first transistor of the load branch, the source of the first transistor of the measurement branch is connected to the drain of the second transistor of the measurement branch, and the gate of the second transistor of the measurement branch is connected to the gate of the second transistor of the load branch and the source of the second transistor of the measurement branch is connected to ground.