Patent ID: 8290097

Claim:
A multi-channel sequential Viterbi decoder comprising: an input data buffer; a signal driver for reading a single data word from the input data buffer; a processing unit selector; a decoder channels parameters registers unit; a processing unit for resetting path metrics; a processing unit for setting a path metric value based on a path number; a processing unit for getting a single bit from the path with assigned number; a processing unit for processing input samples; a decoding paths and path metrics random access memory (RAM); a unit for generating current decoder channel base address for the decoding paths and the path metrics RAM; a unit for generating cell address for the decoding path and the path metric RAM; and a data buffers unit for decoder channels output, wherein: inputs and outputs of the processing units are connected by first and second buses; a first input of the unit for generating cell address for the decoding path and path metric RAM is connected to the second bus; a second and a third inputs of the unit for generating cell address are connected to first and second outputs of the unit for generating current decoder channel base address for the decoding paths and the path metrics RAM; a first input of the unit for generating current decoder channel base address for the decoding paths and the path metrics RAM is connected to a first input of the decoder channel parameter registers unit and to a first output of the input data buffer; a second output of the input data buffer is connected to a first input of the processing unit selector; a second input of the processing unit selector is connected to the second input of the input buffer and to an output of the signal driver; a first input of the signal driver is connected to a third output of the input buffer; a fourth and a fifth outputs of the processing unit selector are connected to a first and a second inputs of the processing unit for setting the path metric value; and a sixth output of the input buffer is connected to a first input of the processing unit for processing input samples.