Patent ID: 8341572

Claim:
A method for modeling non-linear logic gates in an electronic circuit design for improved accuracy and efficient computations during static timing analysis, the method comprising: executing, with at least one processor, one or more spice transistor level circuit simulations of a circuit of a non linear logic gate using a state-space equation for a plurality of simulated time points; for each of the simulated time points, taking Jacobians of charge and current of the state-space equation of the non-linear logic gate to provide a capacitance matrix of a plurality of capacitors and a conductance matrix of a plurality of resistors; forming a small-signal state-space equation for the plurality of capacitors and the plurality of resistors for a small-signal circuit equivalent of the non-linear logic gate; and manipulating the small-signal state space equation for each of the simulated time points to compute one or more time varying linear equivalent capacitors, one or more time varying linear equivalent resistors, and one or more time varying linear equivalent current sources coupled in parallel together for a time varying linear gate model at an input or output node of interest of the circuit to capture the impact of the plurality of capacitors and the plurality of resistors representing the non-linear logic gate.