Patent ID: 7154502

Claim:
A reconfigurable architecture for processing 3D graphics, comprising: a transform/lighting stage which programmably performs lighting calculations and geometric transforms on incoming data, and which writes resulting fragment data, through a respective memory interface, to bulk memory which is not local to said transform/lighting stage; a rasterization stage which, when active, reads said resulting fragment data from said bulk memory, and generates pixel outputs for multiple respective pixels of said fragments; a Z-buffering stage which, when active, performs Z-buffering processes for ones of said pixels to obtain Z-buffer comparison values, and then tests each of said pixels against said Z-buffer comparison values to determine which fragment-pixels are occluded, and then writes corresponding pixel outputs, through a second respective memory interface, to bulk memory which is not local to said Z-buffering stage; and a texturing stage which, when active, reads said pixel outputs from said bulk memory, and performs at least some per-pixel rendering operations, to thereby generate image data outputs; wherein, when one of said Z-buffering and texturing stages are inactive, at least one of said memory interfaces is also made inactive.