Patent ID: 8223574

Claim:
A method for block refreshing a semiconductor memory device comprising the steps of: arranging a plurality of memory cells in one or more arrays of rows and columns, each of the plurality of memory cells comprising: a first region coupled to a source line; a second region; a first body region disposed between the first region and the second region, wherein the body region is electrically floating and charged to a first predetermined voltage potential; a first gate coupled to a word line, wherein the first gate is spaced apart from, and capacitively coupled to, the first body region; a third region coupled to the second region; a fourth region coupled to a bit line; a second body region disposed between the third region and the fourth region, wherein the second body region is charged to a second predetermined voltage potential; and a second gate coupled to a control line spaced apart from, and capacitively coupled to, the second body region; and applying voltage potentials to the plurality of memory cells to refresh a plurality of data states stored in the plurality of memory cells; wherein the plurality of data states comprise a binary 0 data state and a binary 1 data state; wherein applying voltage potentials to the plurality of memory cells further comprises a first voltage applied to the third region for the binary 0 data state and a second voltage applied to the first region for the binary 1 data state; wherein the first voltage is same as the second voltage.