Patent ID: 8551853

Claim:
A non-volatile semiconductor memory device comprising: a substrate; a plurality of first wires of a stripe shape which are formed on the substrate; an interlayer insulating layer formed to cover the plurality of first wires; a plurality of second wires of a stripe shape which are formed on the interlayer insulating layer such that the plurality of second wires are located above the plurality of first wires and cross the plurality of first wires, respectively; a plurality of memory cell holes formed at cross-points of the plurality of first wires and the plurality of second wires, respectively, when viewed from above, the memory cell holes being formed through the interlayer insulating layer between the plurality of first wires and the plurality of second wires such that the memory cell holes expose upper surfaces of the plurality of first wires, respectively; a plurality of dummy holes formed on the plurality of first wires, respectively, in the interlayer insulating layer such that the plurality of dummy holes reach the upper surfaces of the plurality of first wires, respectively; and stacked-layer structures formed inside the memory cell holes and inside the dummy holes, respectively, each of the stacked-layer structures including a first electrode and a variable resistance layer formed on the first electrode; an area of a portion of the first wire which is exposed in a lower opening of one of the dummy holes being greater than an area of a portion of the first wire which is exposed in a lower opening of one of the memory cell holes; and one or more of the dummy holes being formed on each of the first wires.