Patent ID: 7779318

Claim:
A self-test structure for interconnect and logic element testing in a programmable logic device, comprising: a plurality of logic elements, each of the plurality of logic elements comprising at least one look-up table (LUT) and at least one flip-flop; an interconnect structure that includes a programmable switch matrix for connecting the logic elements; SRAM-based configuration latches for configuring the interconnect structure; and test configuration means for configuring a set of one or more of the plurality of logic elements, a portion of the interconnect structure, and one or more of the configuration latches during a reset state by linking the one or more logic elements, the portion of the interconnect structure, and the one or more configuration latches to form a complete path between interface points of the self-test structure to enable testing of the one or more logic elements, the portion of the interconnect structure, and the one or more configuration latches in the complete path, and testing the one or more logic elements, the testing of the one or more logic elements automatically testing the portion of the interconnect structure.