Patent ID: 8533645

Claim:
A method comprising: creating, by a processor, an integrated circuit device library including one or more cells, each cell having a plurality of transistors, wherein each transistor is specified to have a minimum transistor channel width determined by a manufacturing capability of a particular manufacturing facility within which the integrated circuit is manufactured; characterizing the device library while varying process, voltage and temperature parameters; synthesizing, by the processor, a hardware description language representation of a functional logic block including cells from the device library; assessing timing, area, and power values for the functional logic block; modifying the transistor channel width responsive to the assessing; and repeating the characterizing, synthesizing, assessing, and modifying to identify a particular transistor channel width for which the timing value of the functional logic block meets a timing goal and for which the area and power values are minimized among the attempted transistor channel widths; wherein the modifying includes iteratively increasing the transistor channel width of at least a portion of the plurality of transistors of at least one of the cells in the device library to a transistor channel width that is larger than the a minimum transistor channel width, and repeating the characterizing, synthesizing, assessing to identify the particular transistor channel width; wherein the portion of the plurality of transistors of the at least one of the library cells having a transistor channel width that is larger than the minimum transistor channel width correspond to transistors in a forward path of the cell.