Patent ID: 7417911

Claim:
A semiconductor memory device having hierarchically structured data lines, comprising: a plurality of memory cells disposed in a first direction and a second direction perpendicular to each other; a plurality of word lines disposed in the first direction and used for selecting the memory cells disposed in the second direction simultaneously; a plurality of bit lines disposed in the second direction, and connected to and shared by the memory cells disposed in the first direction; a plurality of sense amplifiers for amplifying signals on the bit lines; a write circuit for writing externally input data into the memory cell; a read circuit for outputting data read from the memory cell to an outside; a plurality of global data lines each provided corresponding to one or more of the bit lines; a local data line provided corresponding to two or more of the global data lines and connected to the write circuit and the read circuit; a plurality of data line selection switches provided corresponding to the global data lines and used for switching states of connection between the global data lines and the local data line; a precharge circuit provided corresponding to the local data line and operated in accordance with a received control signal, wherein, in a command waiting state, all of the data line selection switches are in a connected state and the precharge circuit is operated.