Patent ID: 8318568

Claim:
A method for fabricating an FET device, said method comprising: forming a hard-mask, which hard-mask covers a gate-stack, a first junction and a second junction, wherein said gate-stack has a first side and a second side and said first junction and said second junction respectively adjoin said gate-stack, wherein said first junction and said second junction both are of a first conductivity type; performing an ion implantation at a tilted angle, wherein a first portion of said hard-mask is receiving said ion implantation and a second portion of said hard-mask is not receiving said ion implantation due to being shadowed by said gate-stack; selecting said tilted angle in such manner that said first portion covers said first side and adjoining said first junction, while said second portion covers said second side and adjoining said second junction; performing a selective etch, wherein said first portion of said hard mask is removed and said second portion of said hard-mask remains in place; removing said first junction by etching, while said second junction is being protected by said second portion of said hard-mask; depositing by selective epitaxy a new junction adjoining said first side, and in-situ doping said new junction to a second conductivity type; and wherein said FET device comprises said gate-stack, said new junction, said second junction, and a channel region underneath said gate-stack, wherein said channel region, said new junction, and said second junction are of SiGe, and wherein said FET device is characterized as being a tunnel FET (TFET) device.