Patent ID: 8035431

Claim:
A Delay Locked Loop (DLL), comprising: a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock and output an up signal or a down signal; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock, wherein the quantization unit comprises: an up-code generator configured to quantize the up signal to generate an up-code indicating a value of a quantized up signal; a down-code generator configured to quantize the down signal to generate a down-code indicating a value of a quantized down signal; a right adjustor configured to activate, for a number of times corresponding to the down-code, a right signal to decrease a delay value of the delay unit; and a left adjustor configured to activate, for a number of times corresponding to the up-code, a left signal to increase a delay value of the delay unit.