Patent ID: 7709330

Claim:
A method of manufacturing a high voltage metal oxide semiconductor field effect transistor, comprising: forming a substrate, the substrate including a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer wherein the SiGe epitaxial layer of the substrate has a first-type conductivity; forming a gate oxide layer from the Si epitaxial layer such that a portion of the Si epitaxial layer remains underneath the formed gate oxide layer; forming a drift region in portions of the remaining Si epitaxial layer and the SiGe epitaxial layer wherein the portions of the remaining Si epitaxial layer and the SiGe epitaxial layer in which the drift region is formed form part of a channel underneath a gate and wherein the drift region has a second-type conductivity which is different than the first-type conductivity; forming an LDD region in the Si epitaxial layer and the SiGe epitaxial layer under the first lateral portion of the gate opposite the drift region, wherein the LDD region has the second-type conductivity; and forming a source region and a drain region in the Si epitaxial layer and in the SiGe epitaxial layer under the first and second lateral portions of the gate such that the drain region is confined within the drift region and the source region overlaps the LDD region, wherein the source and drain regions have the second-type conductivity.