Patent ID: 8728882

Claim:
A manufacturing method for a thin film transistor array panel, the method comprising: providing a gate line comprising a gate electrode, on a substrate; providing a gate insulating layer covering the gate line; providing a semiconductor material layer on the gate insulating layer; providing a data wire material layer on the semiconductor material layer; providing a first photosensitive film pattern on the data wire material layer, the first photosensitive film pattern comprising a first region, and a second region having a larger thickness than the first region; etching the data wire material layer by using the first photosensitive film pattern as a mask; etching back the first photosensitive film pattern to provide a second photosensitive film pattern which exposes an upper surface of the data wire material layer corresponding to a channel region of a thin film transistor; etching the semiconductor material layer, while the upper surface of the data wire material layer corresponding to the channel region of the thin film transistor is exposed by the second photosensitive film pattern, by using the second photosensitive film pattern as a mask; and etching the data wire material layer by using the second photosensitive film pattern as a mask, to form a source electrode and a drain electrode, wherein the etching the semiconductor material layer comprises using a first non-sulfur fluorinated gas.