Patent ID: 7739637

Claim:
A design structure in a data format tangibly embodied in machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a substrate; a plurality of processing engines (PE's) disposed on the substrate, each processing engine including a measurement and storage unit for performing a self-test of the processing engine and storing results of the self-test; a PE controller coupled to each of the plurality of processing engines, wherein the PE controller is configured to cause the measurement and storage unit of each processing engine to perform self-tests and to store the results of the self-tests, wherein the PE controller is further configured to receive the results of the self-tests for each of the processing engines and select a sub-plurality of the plurality of processing engines based on the results and an optimization algorithm; a programmable voltage regulator coupled to the PE controller configured to produce a supply voltage; and a clock controller coupled to the PE controller and each of the sub-plurality of processing engines.