Patent ID: 7977965

Claim:
A system, comprising: a circuit coupling to a latch, wherein said circuit is capable of a response to a state change of said latch; clocking received by said latch and by said circuit, wherein said clocking is defining a window in time during which said latch is prevented from receiving data, and wherein said clocking is enabling said response for said circuit, wherein said clocking is synchronized in such a manner between said latch and said circuit that said clocking is enabling said circuit for said response only inside said window; additional ones of said circuit with each said additional circuit respectively coupling to a latch, wherein each said additional circuit is capable of said response to a state change of its said respective latch, wherein each said additional circuit and its said respective latch receive said clocking in said manner of synchronization, wherein a plurality of said responses are combined in a scheme corresponding to a logical OR; and wherein said system is characterized as being a soft error detection system.