Patent ID: 6914451

Claim:
A digital logic signal interface circuit ( 1 ) for adaptively receiving and discriminating at least one digital logic input signal ( 31 , 32 ) taking signal amplitude levels each representative of one of a plurality of different logic levels in accordance with a logic signalling definition, said digital logic signal interface circuit ( 1 ) comprising a circuit ( 2 ) adapted to receive a digital logic representative signal ( 31 ) taking signal amplitude levels representative of said logic signalling definition, for generating a threshold signal (Vth) depending on a logic swing amplitude occurring in said digital logic representative signal ( 31 ), said threshold signal generating circuit ( 2 ) comprising an amplitude detector circuit ( 21 , 22 ) for detecting at least one signal amplitude level repetitively taken by said digital logic representative signal ( 31 ), and for providing at least one amplitude detection signal (V+, V−) which is indicative of said at least one detected signal amplitude level; a logic level discriminator circuit ( 41 , 42 ) adapted to receive said at least one digital logic input signal ( 31 , 32 ) and said threshold signal (Vth), and adapted to provide for each of said at least one digital logic input signal a corresponding digital interface output signal ( 51 , 52 ) taking one of a plurality of predetermined signal amplitude levels indicative of a result of comparing said digital logic input signal ( 31 , 32 ) amplitude level to said threshold signal (Vth); characterized by at least one output buffer circuit ( 4 ) adapted to receive a digital logic interface input signal ( 53 ) and to generate in accordance therewith, a digital logic output signal ( 33 ) taking signal amplitude levels each representative of one of said plurality of different logic levels; said output buffer circuit ( 4 ) being coupled to receive said at least one amplitude detection signal (V+, V−) from said amplitude detector circuit ( 21 , 22 ) and to generate said signal amplitude levels in accordance with said at least one amplitude detection signal, such that said digital logic output signal ( 33 ) can adaptively meet said logic signalling definition of said digital logic input signal ( 31 , 33 ).