Patent ID: 7937635

Claim:
An integrated circuit comprising: A. a substrate; B. a serial data in lead, a mode select lead, and a clock lead, all formed on the substrate; C. first functional circuits formed on the substrate, the first functional circuits including a first scan path and a first access port, the first access port is connected to the first scan path, the serial data in lead, and the clock lead, the first access port having a mode select input; D. second functional circuits formed on the substrate, the second functional circuits including a second scan path and a second access port, the second access port is connected to the second scan path, the serial data in lead, and the clock lead, the second access port having a mode select input; E. a shift register formed on the substrate, the shift register having a serial data input connected to the serial data in lead, parallel output leads and a control input; F. control circuitry formed on the substrate, the control circuitry having parallel input leads connected to the parallel output leads of the shift register and enable output leads; G. a state machine formed on the substrate, the state machine having a clock input connected to the clock lead and a mode select input connected to the mode select lead, the state machine having control output leads connected to the control input leads of the shift register; and H. gating circuits formed on the substrate, each gating circuit having a first input connected to the mode select lead, a second input connected to a respective enable output lead, and an output connected to the mode select input of an access port.