Patent ID: 7868670

Claim:
An apparatus comprising: a phase-locked loop circuit that receives a reference clock signal, wherein the phase-locked loop circuit includes: a phase-frequency detector; a charge pump that is coupled to the phase-frequency detector; a voltage controlled oscillator that is coupled to the charge pump, wherein the voltage controlled oscillator operates at a substantially constant frequency when the charge pump is disabled; reference clock failure detection circuitry with inputs connected to the inputs of the phase-frequency detector, wherein the reference clock failure detection circuitry compares the phase offset between clock signals at the inputs to the reference clock failure detection circuitry with a predetermined value to provide a reference clock failure indication signal when the phase offset exceeds the predetermined value, and wherein the reference clock failure detecting circuitry includes: a lock detector that is coupled to the inputs of the phase-frequency detector, wherein the lock detector is operable to detect when the phase-locked loop is in lock by comparing the phase offset between clock signals at the inputs to the lock detector; and a phase offset detector that is coupled to the phase-frequency detector; and a controller that is coupled to the reference clock failure detection circuitry and to the charge pump, wherein the controller disables the charge pump when the reference clock failure indicated signal is received by the controller, and wherein the controller includes: a control block that is coupled to the reference clock failure detection circuitry; and a latch module having a set input and a reset input, wherein one of the set and reset inputs is connected to receive an output of the reference clock failure detection circuitry, and the other of the set and reset inputs is connected to receive an output from the control block.