Patent ID: 7765503

Claim:
A method for automatically reducing common path pessimism for half-cycle timing paths of an integrated circuit (IC), the method comprising: a computer system: receiving a timing report for the IC, wherein the timing report includes a listing of circuit paths and corresponding path delay values; for each source clock path and destination clock path of each half-cycle timing path: identifying common circuit elements; determining a process, voltage, and temperature (PVT) path delay value corresponding to PVT scaling of each identified common circuit element by summing: a difference between a PVT compensated rise time delay and an uncompensated rise time delay, and a difference between a PVT compensated fall time delay and an uncompensated fall time delay; summing together PVT path delay values of each identified common circuit element to obtain a total PVT compensation value; generating a new total skew value by subtracting the total PVT compensation value from a total compensated skew value by taking a difference between: a summation of edge delays corresponding to a first clock edge of all circuit elements in the source clock path, and a summation of edge delays corresponding to a clock edge opposite that of the first clock edge of all circuit elements in the destination clock path; and generating a corrected timing report that includes a new total skew values for each half-cycle circuit path having common circuit elements.