Patent ID: 7033918

Claim:
A production process for manufacturing a semiconductor device including at least one p-channel type MOS transistor, which process comprises: preparing a semiconductor device; forming a gate insulating layer on said semiconductor substrate; forming a gate electrode on said gate insulating layer, said gate electrode having a multi-layered structure including a silicon-seed layer formed as a lowermost layer on said gate insulating layer, a polycrystalline silicon layer formed as an uppermost layer above said lowermost layer, and a silicon/germanium layer formed as an intermediate layer between said lowermost and uppermost layers, the formation of said uppermost layer being carried out at a higher process temperature than a process temperature at which said lowermost and intermediate layers are formed; implanting p-type impurities in said gate electrode; and annealing said semiconductor substrate at a higher process temperature than the process temperature at which said uppermost layer is formed, such that said p-type impurities are substantially uniformly distributed in said gate electrode along a height thereof, and the germanium atoms are diffused from said intermediate layer into said lowermost layer at high density.