Patent ID: 8717080

Claim:
A digital driver, comprising: a delay line to provide adjustable transition control for an output signal, the delay line having multiple n-type transistors coupled in parallel to drive a digital output line low, wherein each transistor has an output terminal, a control terminal, and a reference terminal, wherein the output terminals are coupled to an output node to generate the output signal at the output node, and wherein the control terminals are coupled together to be activated in response to an input signal; control logic coupled to the control terminals of the multiple transistors of the delay line, the control logic to generate signals at selective control terminals in response to digital control bits to selectively drive the multiple transistors of the delay line at one or more selected points in the delay line in response to the signal, according to the digital control bits, to dynamically adjust a slew rate for the digital driver; a second delay line having multiple p-type transistors coupled in parallel, wherein each p-type transistor has an output terminal, a control terminal, and a reference terminal, wherein the output terminals are coupled to the output node to generate an output signal to drive the digital output line high in response to the input signal, and wherein the control terminals are coupled together to be activated in response to the input signal; and p-type control logic coupled to the control terminals of the multiple p-type transistors, the p-type control logic to generate signals at selective control terminals in response to the digital control bits to selectively drive the multiple p-type transistors of the second delay line at one or more selected points in the second delay line in response to the input signal, according to the digital control bits, to dynamically adjust a slew rate on the output signal for transitions to a logic high on the output line, wherein the p-type control logic comprises half tristate inverters controlled by the digital control bits, each half tristate inverter including: a tristate portion activated by one of the control bits to place the half tristate inverter in a high impedance state when the one control bit is a logic low, and drive the control terminal of the coupled transistor of the delay line when the one control bit is a logic high; and an inverter portion activated by the input signal to deactivate the coupled transistor of the delay line when the input signal in a logic low.