Patent ID: 8492875

Claim:
A nonvolatile memory element array comprising: a substrate; a plurality of first electrode wires formed on the substrate to extend in parallel with each other within a plane parallel to a main surface of the substrate; a plurality of second electrode wires formed on the substrate to extend in parallel with each other within a plane parallel to the main surface of the substrate and to three-dimensionally cross the plurality of first electrode wires; and nonvolatile memory elements provided to respectively correspond to three-dimensional cross points of the plurality of first electrode wires and the plurality of second electrode wires; wherein each of the nonvolatile memory elements includes a nonvolatile memory portion and a fixed resistance portion which are provided in series to connect an associated one of the first electrode wires and an associated one of the second electrode wires; wherein the nonvolatile memory portion includes a first electrode, a second electrode, and a variable resistance layer which is disposed between the first electrode and the second electrode, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the first electrode and the second electrode, the plurality of resistance states including a low-resistance state and a high-resistance state whose resistance value is higher than a resistance value of the low-resistance state; wherein the variable resistance layer comprises a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx; and wherein when a resistance value of the variable resistance layer in a state where the variable resistance layer is in the low-resistance state is RL, a resistance value of the variable resistance layer in a state where the variable resistance layer is in the high-resistance state is RH, and a resistance value of the fixed resistance portion is R 0 , R 0 satisfies RL<R 0 .