Patent ID: 7251296

Claim:
A system for determining an optimal clock signal to associate with an incoming data stream, the system comprising: a candidate clock generation circuit, comprising a phase detector, a loop filter having a filter output voltage, a plurality of voltage controlled oscillators, a first selector connected to the plurality of voltage controlled oscillators, and a second selector connected to the first selector, wherein each voltage controlled oscillator generates an output signal having a selected frequency that is determined by the voltage level of the filter output voltage, and wherein the number of voltage controlled oscillators determines the number of candidate clocks, that operates to receive the incoming data stream and generate at least one candidate clock signal; a transition density detector circuit that operates to receive the incoming data stream and a selected candidate clock signal to determine a transition density parameter associated with the selected candidate clock signal, wherein the transition density parameter comprises the number of bit transitions in a selected measurement period; a controller coupled to the generation circuit and the detector circuit and operable to control the input of each of the at least one candidate clock signals to the detector circuit as the selected candidate clock signal, so that one or more transition density parameters are determined, wherein the controller is operable to perform a timing function to determine the selected measurement period responsive to the incoming data stream, and wherein the controller operates to determine the optimal clock signal from the at least one candidate clock signal based on the one or more transition density parameters; wherein the generation circuit locks the optimal clock signal to the incoming data stream; and wherein the system is operable to determine a new optimal clock signal responsive to a change in rate of the incoming data stream.