Patent ID: 7057955

Claim:
A sense amplifier connected to first and second bit lines, comprising: means for precharging said bit lines to a high voltage; means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction; first and second transistors respectively controlled by the first and second bit lines; and in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage, wherein the first and second transistors are identical MOS transistors of a first conductivity type and wherein the controllable means comprises third and fourth transistors having their drain terminals connected to the source terminal of the first transistor, and fifth and sixth transistors having their drain terminals connected to the source terminal of the second transistor, the third and fifth transistors being of same dimensions and receiving on their gate terminal a signal for activating the sense amplifier, the fourth and sixth transistors being of same dimensions and respectively receiving on their gate terminal control signals for the reading from the first and second bit lines.