Patent ID: 8049511

Claim:
A method for detecting whether or not a printed circuit board has a faulty via hole, the printed circuit board including a plurality of electric trace segments, the method comprising: providing a testing system, the testing system comprising a processor, a storing means, and a resistance measuring device, the storing means storing a first function: Y min =f min (X), wherein X represents a reference resistance associated with a given electric trace segment, and Y min represents a minimum threshold value associated with the given electric trace segment; the first function being determined by: providing a plurality of standard printed circuit boards having the same structure of the printed circuit board, each standard printed circuit board having a standard electric trace segment corresponding to the given electric trace segment; measuring resistances of the standard electric trace segments; averaging the resistances of the standard electric trace segments as the reference resistance of the given electric trace segment; providing a plurality of sample printed circuit boards having the same structure of the printed circuit board, each sample printed circuit board having a sample electric trace segment corresponding to the given electric trace segment; measuring resistances of the sample electric trace segments; marking a portion of the sample printed circuit boards whose resistances exceed the reference resistance by a predetermined range; verifying the type of faulty via hole of the electric trace segment of each marked printed circuit board; and taking the minimum of resistance differences between the reference resistance and the reference of the sample electric trace segment of each marked printed circuit board as the minimum threshold value of the given electric trace segment; measuring a resistance of the given electric trace segment using the resistance measuring device, a to-be-tested via hole being located on the given electric trace segment; and judging whether or not the to-be-tested via hole is a faulty via hole using the processor according to the following criteria: if |Xa−X|≧Y min , the to-be-tested via hole is a faulty via hole, and if |Xa−X|<Y min , the to-be-tested via hole is an acceptable via hole, wherein Xa represents the resistance of the given electric trace segment.