Patent ID: 8030774

Claim:
A microelectronic device comprising: a substrate; a plurality of components on said substrate; an insulating layer adjacent said substrate; and a plurality of metallic interconnection levels within said insulating layer and for said plurality of components, said plurality of metallic interconnection levels comprising at least one given metallic level comprising a plurality of conductive lines of a first metallic material, and another metallic level adjacent said at least one given metallic level and comprising at least one conductive zone of the first metallic material and coupled to at least one of said plurality of conductive lines of said at least one given metallic level, and at least one other conductive zone of a second metallic material and coupled to at least one other of said plurality of conductive lines of said at least one given metallic level, the at least one other conductive zone of the second metallic material being co-planar with the at least one conductive zone of the first metallic material.