Patent ID: 8729694

Claim:
A semiconductor device, comprising: a semiconductor wafer including a plurality of semiconductor die separated by a peripheral region around the semiconductor die; a plurality of vias formed at least partially in the semiconductor die; a trench including opposing sidewalls formed in the peripheral region with a portion of the peripheral region remaining between the opposing sidewalls of the trench and the semiconductor die, the trench extending into the vias and continuous from a first via to a second via in the semiconductor die; an insulating layer formed over the opposing sidewalls of the trench and a sidewall of the vias; a first conductive layer deposited over the insulating layer along the opposing sidewalls of the trench from the first via to the second via and over the sidewall of the vias to form conductive vias; and a second conductive layer formed over a first surface of the semiconductor die and electrically connected between the first conductive layer and a contact pad on the semiconductor die.