Patent ID: 8711154

Claim:
A method for parallel processing of video signal encoding operations, comprising: using a multi-core processor, comprising a plurality of individual processing cores, to establish a master-slave processing protocol for encoding a video signal, wherein one of said individual processing cores is designated as a master processor core and a predetermined number of other individual processing cores are designated as slave processor cores; using a shared memory to store video data frames and control messages for encoding the video data frames by said master processor core and said slave processor cores; using said master processor core to control encoding of each video data frame by dynamically partitioning each video data frame into a plurality of partition slices and assigning each partition slice to a corresponding slave processor core for H.264 high-definition (HD) video encoding of said partition slice by sending a starting address and ending address for each partition slice assigned to each corresponding slave processor core to balance the video data processing load among said slave processor cores, wherein the master processor core is operable to send the starting address to each corresponding slave processor core when assigning each partition slice to said corresponding slave processor core, and is operable to send the ending address to each corresponding slave processor core after assigning each partition slice to said corresponding slave processor core.