Patent ID: 7135373

Claim:
A method for fabricating a transistor structure, comprising the steps of: providing a substrate having a surface and a channel region; forming a lightly doped drain (LDD) region in said substrate contiguous to said channel region and said surface; implanting a first dopant having a lower dopant concentration than that of said LDD region into said lightly doped drain (LDD) region to a depth less than the LDD junction depth; and implanting a second dopant into said substrate beyond the LDD junction depth to form a source/drain region, the implantation of the second dopant of sufficient dopant concentration to overpower a portion of the LDD remote from said channel and a substantial portion of the first dopant to define a floating region of the first dopant completely within the LDD region, the source/drain region and said surface and remote from said channel region with reduced dopant concentration relative to the dopant concentration of the LDD region.