Patent ID: 8575697

Claim:
A SRAM-type memory cell comprising: a semiconductor on insulator substrate comprising a thin film of semiconductor material separated from a base substrate by an insulating layer; six transistors comprising two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters, with each of the transistors comprising a drain region and a source region arranged in the thin film, a channel extending between the source region and the drain region and a front gate situated above the channel, wherein each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential, and wherein the first and second potentials are modulated according to the type of cell control operation.