Patent ID: 7421634

Claim:
A method of testing an integrated circuit having first and second modules and an interface module, the first module being designed to operate at a first clock frequency in a functional mode and has an output connected to an input of the interface module, the second module being designed to operate at a second clock frequency in the functional mode and has an input connected to an output of the interface module, wherein the first clock frequency is not equal to the second clock frequency, the method comprising: providing a first clock signal to the first module and a second clock signal to the second module, each of the first and second clock signals having (2n+1) clock pulses with corresponding latch edges, wherein n is an integer greater than 1; clock pulses number 1 to number (n−1) of the first and second clock signals have synchronized corresponding latch edges; the latch edges of clock pulses number n and number (n+1) of the first clock signal have a time interval inversely proportional to the first clock frequency, the latch edges of clock pulses number n and number (n+1) of the second clock signal have a time interval inversely proportional to the second clock frequency, where the latch edges of the clock pulse number (n+1) of the first and second clock signals are synchronized; and clock pulses number (n+2)to number (2n+1) of the first and second clock signals have synchronized corresponding latch edges; clocking n bits of a scan vector into the first and second modules using the clock pulses number 1 to number n of a corresponding one of the first and second clock signals, wherein the scan vector has at least n bits; operating the first and second modules in the functional mode for the duration of the clock pulse number (n+1) of the corresponding one of the first and second clock signals, wherein the scan vector causes a transition at the output of the interface module at the latch edge of the clock pulse number (n+1) of one of the first and second clock signals; and clocking an n-bit vector from the second module using the clock pulses number (n+2)to number (2n+1) of the second clock signal.