Patent ID: 7747892

Claim:
A system, comprising: a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage; a counter coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal; a divider coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal; a filter coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal; a fixed potential configured to generate a second comparison signal; and a comparator coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.