Patent ID: 8837198

Claim:
A circuit for determining a binary value of a memory cell, the binary value of the memory cell represented by an electrical resistance level of the memory cell, the binary value of the memory cell including most significant bits and least significant bits, the circuit comprising: a plurality of shunt capacitors having different capacitances configured to selectively couple with the memory cell; a controller configured to: iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range; determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor; charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell; and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell.