Patent ID: 7502915

Claim:
An integrated circuit comprising: a plurality of computational elements; a first and a second processing node each having a core processor with a common architecture, wherein the common architecture is configurable in response to a first configuration command to be a control node adapted to control an interconnection of said computational elements to perform a selected task and configurable in response to a second configuration command to be a programmable scalar node (PSN) adapted to perform a computational application; a first memory associated with said first processing node; a second memory associated with said second processing node, each of said first and second memories including at least one of a data cache and an instruction cache of sufficient capacity to store instructions and data necessary to implement a plurality of algorithms; a first interface coupling said core processor of said first processing node to said first memory and to said computational elements; a second interface coupling said core processor of said second processing node to said second memory and to said computational elements, the first interface and the second interface having the same architecture; and a third processing node coupled to each of the first and second processing nodes and comprising a core processor with a common architecture, wherein the common architecture is configurable in response to a first configuration command to a control node adapted to control an interconnection of said computational elements to perform a selected task and configurable in response to a second configuration command to a programmable scalar node (PSN) adapted to perform a computational application and being configured to run boot code, operating system code and application code and further configured to adapt each of the first and second processing nodes to perform the computational application in response to the first and second configuration commands.