Patent ID: 8879305

Claim:
A memory array comprising: a first active area, a second active area, a third active area, and a fourth active area each traversing a first memory cell area and a second memory cell area, the first memory cell area being adjacent to the second memory cell area; wherein in the first memory cell area: the first active area is a component of a first pull-down transistor, the second active area is a component of a first pull-up transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node, the third active area is a component of a first isolation transistor and a second pull-up transistor, and the fourth active area is a component of a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node; wherein in the second memory cell area: the first active area is a component of a third pull-down transistor, the second active area is a component of a third pull-up transistor, a drain of the third pull-up transistor being electrically coupled to a drain of the third pull-down transistor at a third node, the third active area is a component of a second isolation transistor and a fourth pull-up transistor, and the fourth active area is a component of a fourth pull-down transistor, a drain of the fourth pull-up transistor being electrically coupled to a drain of the fourth pull-down transistor at a fourth node, a gate of the fourth pull-up transistor and a gate of the fourth pull-down transistor being electrically coupled to the third node, a gate of the third pull-up transistor and a gate of the third pull-down transistor being electrically coupled to the fourth node; and wherein the first isolation transistor and the second isolation transistor have a shared source/drain region at a boundary between the first memory cell area and the second memory cell area, the shared source/drain region not having a contact directly coupled thereto.