Patent ID: 8405415

Claim:
A test apparatus that tests a device under test, comprising: a processor; a memory in communication with the processor; a plurality of test modules that test the device under test; a synchronization module in communication with the processor and connected to each of the plurality of test modules, and that synchronizes the plurality of test modules; and a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module, wherein the synchronization module includes: a receiving section in communication with the memory that receives, from each of the plurality of test modules, a ready signal indicating that the test module is in a ready state; an aggregating section in communication with the memory that generates an aggregate ready signal indicating that the plurality of test modules are in the ready state, on a condition that ready signals have been received from all of the plurality of test modules; and a transmitting section in communication with the memory that transmits, to each of the plurality of test modules, a common synchronization signal ordering test initiation, in response to the generation of the aggregate ready signal, such that the test modules are commonly synchronized.