Patent ID: 7414876

Claim:
A nonvolatile ferroelectric memory device having a power control function, comprising: a voltage dropping unit for dropping an external power voltage to a predetermined level and supplying an internal power voltage; a nonvolatile ferroelectric circuit unit having a hierarchical bit line structure including a plurality of sub bit lines connected to one of a plurality of main bit lines and including a first nonvolatile ferroelectric capacitor for reading/writing data depending on the internal power voltage, wherein a voltage of a sub bit line induced by cell data is converted into current by a current controller according to the voltage of the sub bit line so that a sensing voltage of a main bit line is induced; a power stabilization unit including a second ferroelectric capacitor and a capacitor connected in parallel between the internal power voltage and a ground voltage for reducing noise from the internal power voltage applied from the voltage dropping unit to stabilize the internal power voltage; a power-up detection reset unit for detecting the external power voltage level and generating a reset signal to initialize the nonvolatile ferroelectric circuit unit; and a nonvolatile ferroelectric register unit, driven depending on the external power voltage, for storing cell data in a nonvolatile memory cell, wherein the nonvolatile ferroelectric register unit comprises: a pull-up regulating unit for selectively supplying the external power voltage in response to a pull-up enable signal; a pull-down regulating unit for selectively supplying a ground voltage to the nonvolatile memory cell in response to a pull-down enable signal; and the nonvolatile memory cell for storing the cell data depending on the external power voltage applied from the pull-up regulating unit, wherein the nonvolatile memory cell comprises: a pull-up latch unit having a cross-coupled structure for latching the external power voltage applied from the pull-up regulating unit; a write/read port selecting unit for selectively connecting an internal bit line to nodes at both output terminals in response to a word line driving signal, and controlling a write operation; a ferroelectric capacitor unit, connected to the node at both output terminals, for storing the cell data into a plurality of third nonvolatile ferroelectric capacitors in response to a cell plate signal; and a pull-down latch unit having a cross-coupled structure for latching the ground voltage applied from the pull-down regulating unit.