Patent ID: 7181576

Claim:
A method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having at least one data area and one identification area, the method comprising the steps of: a) providing, using the processor, a synchronization value for comparison purposes, the synchronization value being used to determine which memory entry or entries of the cache memory is/are to be synchronized with the main memory; b) comparing, using a cache logic circuit of the cache memory, the synchronization value provided with contents of at least one memory field of each memory entry; c) when the synchronization value provided matches the contents of the at least one memory field, checking, using the cache logic circuit of the cache memory, a first flag of a third memory field of the identification area for a first state, which indicates that a change has been made to the data area of the memory entry since the last synchronization; and d) when the first flag is in the first state, transferring the contents of the data area of the memory entry or entries to the main memory.