Patent ID: 7385258

Claim:
A semiconductor structure, comprising: (a) a semiconductor layer; (b) a gate dielectric region on top of the semiconductor layer; (c) a gate electrode region on top of the gate dielectric region, wherein the gate electrode region is electrically insulated from the semiconductor layer by the gate dielectric region, wherein the semiconductor layer comprises a channel region, a first source/drain region, and a second source/drain region, and wherein the channel region is disposed between the first and second source/drain regions and directly beneath and electrically insulated from the gate electrode region by the gate dielectric region; (d) a first electrically conducting region and a second electrically conducting region on top of the first and second source/drain regions, respectively; and (e) a first contact region and a second contact region on top of and electrically coupled to the first and second electrically conducting regions, respectively; wherein the first electrically conducting region and the first source/drain region are in direct physical contact with each other at a first common surface and a second common surface, wherein the first and second common surfaces are not coplanar, wherein the first contact region overlaps both the first and second common surfaces, wherein the first common surface makes an angle of about 70°, 90°, 125°, 135°, or 145° with the second common surface, wherein the first common surface makes an angle of about 125° with the second common surface, and wherein the first and second common surfaces are in (100) and (111) crystalline planes, respectively.