Patent ID: 7711927

Claim:
A method of preloading instructions, the method comprising: setting an instruction set preload indicator identifying one of a plurality of instruction sets, the instruction set preload indicator generated by an instruction execution unit; executing, according to a current processor instruction set operating mode, an instruction operative to preload instructions into an instruction cache; providing the instruction set preload indicator to a pre-decoder upon executing the instruction operative to preload instructions into an instruction cache; pre-decoding the pre-loaded instructions according to an instruction set operating mode other than the current processor instruction set operating mode in response to the instruction set preload indicator generated by the instruction execution unit; wherein the instruction execution unit includes processing logic operative to track properties of instructions and data fetched from a second cache memory, wherein the second cache memory is interposed between the instruction cache and a memory interface and wherein the pre-decoder is interposed between the instruction cache and the second cache memory; and wherein the pre-loaded instructions are pre-decoded according to an instruction set operating mode other than the current processor instruction set operating mode in an interworking mode, and are otherwise pre-decoded according to the current processor instruction set operating mode, wherein the interworking mode is indicated by an interworking mode indicator bit in a status register and wherein one or more bits of the instruction set preload indicator are gated by the interworking mode indicator bit.