Patent ID: 8310880

Claim:
A method of operating a non-volatile memory controller comprising a processor and a plurality of non-volatile memory interfaces, the method comprising: each non-volatile memory interface in the plurality of non-volatile memory interfaces receiving from the processor, multiple non-volatile memory operations to be performed; wherein each non-volatile memory interface is coupled to a corresponding group of non-volatile memories; wherein each non-volatile memory operation uniquely identifies a non-volatile memory from within said group of non-volatile memories; wherein said each non-volatile memory operation comprises a plurality of phases in a predetermined sequence; a first non-volatile memory interface in the plurality of non-volatile memory interfaces using a first set of bidirectional input-output pins to communicate with a first non-volatile memory in a first group of non-volatile memories to initiate performance of a first phase of a first non-volatile memory operation; wherein a second phase is specified to be performed subsequent to said first phase, in the first non-volatile memory operation; the first non-volatile memory interface using said first set of bidirectional input-output pins to further communicate with the first non-volatile memory to initiate performance of a second phase of the first non-volatile memory operation, subsequent to receipt of a first status signal from the first non-volatile memory indicating readiness of the first non-volatile memory; between performance of said first phase and performance of said second phase, said first non-volatile memory interface using said first set of bidirectional input-output pins to communicate with a second non-volatile memory in said first group of non-volatile memories to initiate performance of another phase of another non-volatile memory operation among said multiple non-volatile memory operations, based at least partially on a second status signal from the second non-volatile memory indicating readiness of the second non-volatile memory and said first status signal from the first non-volatile memory indicating busyness of the first non-volatile memory during performance of the first phase.