Patent ID: 7920000

Claim:
A PLL circuit comprising: a phase frequency detector that detects a phase difference between a reference signal and a feedback signal; a filter circuit that outputs a control voltage based on an output signal from the phase frequency detector; a voltage control oscillation circuit that controls a frequency of a clock signal output based on the control voltage; a frequency dividing circuit that divides the frequency of the clock signal and outputs the feedback signal; and an automatic adjustment circuit that adjusts a frequency division ratio of the frequency dividing circuit based on the control voltage, wherein the automatic adjustment circuit comprises: a comparison circuit that outputs a first control signal for controlling the frequency division ratio based on a potential difference between the control voltage and a first reference voltage, and outputs a second control signal for controlling the first reference voltage based on the potential difference between the control voltage and the first reference voltage; and a reference voltage selection circuit that selects the first reference voltage based on the second control signal and outputs the first reference voltage selected.