Patent ID: 8089812

Claim:
A semiconductor memory device, comprising: a plurality of memory banks; a plurality of cell arrays arranged in each of the memory banks; a plurality of array word lines arranged in each of the cell arrays; one or more repair word lines arranged in each of the cell arrays; and a plurality of repair information storages configured to store bank information and row addresses of array word lines to be replaced with the repair word lines, wherein each of the repair information storages is configured to store statuses relating to different ones of the memory banks, respectively, and includes: a plurality of first storage units corresponding to the memory banks and configured to output a plurality of enable signals in response to bank active signals; a second storage unit configured to store a row address of an array word line to be repaired; and an output unit enabled in response to the enable signals and configured to output a signal to enable a repair word line when a row address of an array word line to be accessed is identical to the row address stored in the second storage unit.