Patent ID: 7675347

Claim:
A semiconductor device comprising: a target transistor operating in either an active mode or a standby mode; a substrate-potential power source line and a source-potential power source line for providing a substrate potential and a source potential, respectively, to said target transistor; and a potential equalizing transistor for controlling coupling between said substrate-potential power source line and said source-potential power source line, wherein: said potential equalizing transistor is OFF, and different potentials are supplied to said substrate-potential power source line and said source-potential power source line in said standby mode; said potential equalizing transistor is turned ON during a mode shift from said standby mode to said active mode; a common potential is supplied to said substrate-potential power source line and said source-potential power source line in said active mode; a source-potential generation circuit for generating said common potential and a first potential supplied to said source-potential power source line in said active mode and said standby mode, respectively; and a substrate-potential generation circuit for generating a second potential supplied to said substrate-potential power source line in said standby mode, said first and second potentials providing a specific potential difference between said substrate-potential power source line and said source-potential power source line in said standby mode, wherein said source-potential power source line and said substrate-potential power source line include a high-source-potential power source line and a high-substrate-potential power source line, said source-potential generation circuit and said substrate-potential generation circuit include a high-source-potential generation circuit and a high-substrate-potential substrate potential, respectively, which supply a high-potential-side source potential and a high-potential-side substrate potential to said high-source-potential power source line and said high-substrate-potential power source line, respectively, wherein the following relationship holds: Δ Vbp×Cbp=ΔVsp×Csp, wherein ΔVbp, ΔVsp, Cbp and Csp are a difference between said second potential and said common potential, a difference between said common potential and said first potential, a load capacitance of said high-substrate-potential power source line, and a load capacitance of said high-source-potential power source line, respectively.