Patent ID: 7644382

Claim:
A method implemented by an integrated-circuit-design computer for generating an engineering change order (ECO) netlist for an integrated circuit (IC), the method comprising: (a) performing, by the computer, a formal equivalence check between an implementation netlist and a reference netlist, to identify one or more failed comparisons, at least one failed comparison corresponding to a failed compare point in the implementation netlist and a failed compare point in the reference netlist; (b) for the at least one failed comparison: (i) identifying, by the computer, a fan-in cone for the corresponding failed compare point in the implementation netlist, wherein the fan-in cone comprises a set of one or more implementation-netlist cells having one or more pins; (ii) identifying, by the computer, a fan-in cone for the corresponding failed compare point in the reference netlist, wherein the fan-in cone comprises a set of one or more reference-netlist cells having one or more pins; (iii) performing, by the computer, equivalence verifications between the set of one or more implementation-netlist cells and the set of one or more reference-netlist cells to generate pin pass/fail information; (iv) tracing, by the computer, the fan-in cone for the corresponding failed compare point in the reference netlist to generate ECO pin and cell information; (v) automatically modifying, by the computer, the implementation netlist to generate the ECO netlist by adding one or more new ECO cells to the implementation netlist and appropriately connecting the one or more new ECO cells.