Patent ID: 7587686

Claim:
A clock distribution network for a structured ASIC, the clock distribution network comprising: a deterministic portion of the clock distribution network that distributes at least one clock signal and at least one clock enable signal to a plurality of predetermined locations on the structured ASIC; a first clock gating circuit associated with a first of the plurality of the predetermined locations and connected with the deterministic portion of the clock distribution network, wherein the first clock gating circuit produces a first gated clock signal output based on a first clock signal and a first clock enable signal; and a first configurable portion of the clock distribution network connected with the first clock gating circuit, wherein the first configurable portion distributes the first gated clock signal output to a first set of logic elements, wherein the first gated clock signal output includes: a first gated clock signal in response to the first clock signal when the first clock enable signal has a first value, wherein the first gated clock signal operates the first set of logic elements; and a second gated clock signal in response to the first clock signal when the first clock enable signal has a second value, wherein the second gated clock signal suppresses operation of the first set of logic elements, wherein the structured ASIC includes a two-dimensional array of logic elements, and wherein logic elements of the array are customizable to provide the first clock gating circuit and are customizable to provide the first set of logic elements that receive the first gated clock signal.