Patent ID: 6963628

Claim:
A receiver comprising: an oscillator outputting three or more phases of a clock signal; and a retiming mechanism coupled to said oscillator having circuitry for receiving said phases of said clock signal and serial data, and circuitry operable to reduce timing uncertainties in said serial data by outputting a value of said serial data sampled at a particular phase of said clock signal; wherein said retiming mechanism comprises a plurality of first units, wherein each of said plurality of first units comprises circuitry for sampling said serial data using a said particular phase of said clock signal; wherein said retiming mechanism further comprises a plurality of second units, wherein each of said plurality of second units is associated with a particular first unit, wherein each of said plurality of second units comprises circuitry for outputting the value of said serial data sampled by said associated first unit upon activation; wherein a particular second unit of said plurality of second units is activated based on a logical state of each input to said particular second unit; and wherein said logical state of each input is determined based on combinational logic using said phases of said clock signal and complements of said phases of said clock signal.