Patent ID: 8375343

Claim:
A method for statically analyzing timing of an electronic circuit design, the method comprising: receiving a netlist of an electronic circuit design to determine a plurality of circuit cells coupled together by interconnect networks; from a cell library, receiving matrix coefficients for a time varying linear gate model for each circuit cell instantiated in the electronic circuit design, wherein the matrix coefficients for the time varying linear gate model include one or more circuit parameter coefficients for each respective circuit cell to be multiplied together with a variable circuit parameter for variation aware modeling; forming a set of matrix-based state-space equations for each of the interconnect networks and each of the time varying linear gate models of each respective circuit cell of the electronic circuit design; solving the set of matrix-based state-space equations at each simulation time step to determine an output full waveform for each output of each circuit cell in the electronic circuit design to efficiently, statically simulate timing of the electronic circuit design; and wherein one or more of the reading, the generating, the solving, and the sequentially determining are performed with a processor.