Patent ID: 7016242

Claim:
A semiconductor memory apparatus comprising: a memory unit having a plurality of unit blocks, wherein each unit block includes: a memory core including a plurality of memory cells laid out to form a cell matrix; and redundant lines including redundant memory cells each used for repairing an abnormal memory cell generated in any of said memory cores, wherein said plurality of unit blocks form a block matrix or a plurality of block matrixes, and each of said plurality of unit blocks forms a one-dimensional group oriented in a first direction (row or column direction) or a second direction (column or row direction); and said redundant lines are shared by a group of said plurality of unit blocks, wherein the group of said plurality unit blocks have a common orientation of said one-dimensional group; self-test means for evaluating said memory cells to determine whether said memory cells are abnormal, wherein said self-test means is mounted in the same chip as said memory unit; and self-repair means for receiving address pairs associated with an abnormal memory cell from said self-test means, selecting a minimum number of address pairs of the plurality of address pairs received from said self-test means, wherein each address pair includes a first-direction address (row or column address) and a second-direction address (column or row address) associated with the abnormal memory cell, storing said selected minimum number of address pairs in first storage means for each of said plurality of unit blocks required to determine a redundant line to be used to repair the abnormal memory cell; and finding a redundant line to repair the abnormal memory cell based on address pairs stored in said first storage means.