Patent ID: 7962538

Claim:
A circuit comprising: an electronic computing circuit for processing two N-bit input operands of a bit length N and generating two M-bit output operands of a reduced bit length M, where M<N, the electronic computing circuit comprising: means for receiving said two N-bit operands as an input; means for adding the (N−M+1) most significant bits of said two N-bit operands in an auxiliary adder logic; a decision logic processing the add result of said auxiliary adder logic for calculating at least the two most significant bits of reduced-bit-length output operands such that a predetermined post-processing can be correctly performed with said M-bit output operands, wherein the add result is a signed integer; wherein said decision logic sets the MSB of the output operands to 1 when the auxiliary adder result is less than or equal to −2, 0 when the auxiliary adder result is greater than or equal to 0, and propagates the Nth-bit of the input when the auxiliary adder result is equal to −1; and wherein said decision logic sets the second MSB of the output operands to 0 when the auxiliary adder result is less than −2, 1 when the auxiliary adder result is greater than 0, and propagates the (N−1)th-bit of the input when the auxiliary adder result is between and inclusive of 0 and −2.