Patent ID: 7366937

Claim:
A method for synchronizing a plurality of digital clocks to a synchronizing signal, said method comprising: generating centrally a reference clock; synthesizing, from said reference clock using a first clock multiplier, a first digital clock, wherein said first clock multiplier includes: (a) a phase locked loop having a divider that is programmable to provide a first divider ratio so that said first digital clock has a first frequency, wherein said first clock multiplier has a first settling time, and (b) a first masking circuit that, in response to said synchronizing signal, generates a first time delay signal that masks an output of said first clock multiplier for a period of time that is at least as long as said first settling time; synthesizing, from said reference clock using a second clock multiplier, a second digital clock, wherein said second clock multiplier includes: (a) a phase locked loop having a divider that is programmable to provide a second divider ratio so that said second digital clock has a second frequency, wherein said second clock multiplier has a second settling time, and (b) a second masking circuit that, in response to said synchronizing signal, generates a second time delay signal that masks an output of said second clock multiplier for a period of time that is at least as long as said second settling time; and in response to a receipt of said synchronizing signal: (i) resetting said first and second clock multipliers; and (ii) generating said first and second time delay signals, thus masking said output of said first clock multiplier during said first settling time, and masking said output of said second clock multiplier during said second settling time.