Patent ID: 8209645

Claim:
A system for designing a functional circuit, comprising: a hierarchizing means for extracting a second description representing a synchronous unit circuit from a first description representing a functional circuit at register transfer level, blocking the second description, and converting the first description into a third description which is hierarchized with a use of a blocked second description as one class; a first logic synthesis means for generating a first net list by logic synthesis of the third description; a first placement and routing means for performing placement and routing based on the first net list; a first substitution means for substituting a fourth description indicating an asynchronous unit circuit for the blocked second description indicating the synchronous unit circuit; a second logic synthesis means for generating a second net list by logic synthesis of the fourth description; a second placement and routing means for performing placement and routing based on the second net list; a calculation means for calculating delay information corresponding to the second net list from circuit information determined by the second placement and routing means; and a second substitution means for selectively substituting the asynchronous unit circuit on which placement and routing is performed by the second placement and routing means for the synchronous unit circuit on which placement and routing is performed by the first placement and routing means based on a calculation result by the calculation means, and for performing timing verification with a layout in which the selective substitution is completed, wherein the second substitution means is configured to selectively substitute process again if the layout has any malfunction.