Patent ID: 8218372

Claim:
A semiconductor storage device comprising a memory cell configured to store 1-bit information, the memory cell comprising a first p-channel metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first n-channel metal-oxide-semiconductor (NMOS) transistor, a second NMOS transistor, a first transistor, a second transistor, and a third transistor, wherein sources of the first and second PMOS transistors are connected to a first power supply line, a drain of the first PMOS transistor is connected to a first node, a drain of the second PMOS transistor is connected to a second node, sources of the first and second NMOS transistors are connected to a second power supply line, a drain of the first NMOS transistor is connected to the first node, a drain of the second NMOS transistor is connected to the second node, the first node is connected to a gate of the second PMOS transistor and a gate of the second NMOS transistor, the second node is connected to a gate of the first PMOS transistor and a gate of the first NMOS transistor, a gate of the first transistor is connected to a first signal line, a source of the first transistor is connected to the first node, and a drain of the first transistor is connected to the second node, a gate of the second transistor is connected to the second node, a source of the second transistor is connected to a third node, and a drain of the second transistor is connected to a second signal line, and a gate of the third transistor is connected to a third signal line, a source of the third transistor is connected to a fourth signal line, and a drain of the third transistor is connected to the third node.