Patent ID: 8300465

Claim:
A semiconductor system, comprising: a flash memory device which stores page data in a plurality of page data cells of a first non-volatile memory and spare data in a plurality of spare data cells of a second non-volatile memory, reads the stored page data and the stored spare data when a read command is applied from an external portion, and sequentially selects a plurality of first or second page buffers according to address information applied from the external portion to output the page data and the spare data; a central processing device which receives the spare data and executes a stored booting program to boot an operating system of an electronic device system; a memory controller which provides address information and a command to the flash memory device and controls an operation of the flash memory device; a memory bus which serves as a medium for transmitting data, address information and a command between the flash memory device and the memory controller; and a row decoder configured to decode a row address of the second non-volatile memory to have the same address as a row address for selecting a page in the first non-volatile memory, wherein the first non-volatile memory and the second non-volatile memory are different types of non-volatile memory.