Patent ID: 7757062

Claim:
A semiconductor integrated circuit apparatus, comprising: a first functioner that includes: a first clock generator formed with a phase-locked loop that generates a first system clock; a first internal memory in which data is at least one of written to and read from, using said first system clock; and a first selector; and a second functioner that includes: a second clock generator formed with a phase-locked loop that generates a second system clock; a second internal memory in which data is at least one of written to and read from using said second system clock; and a second selector, wherein: said first internal memory stores a value representing an operating voltage and a value representing an operating frequency corresponding to work of said second functioner, and a division ratio of an output signal of said first clock generator, in a form of an operation program, said second internal memory stores a value representing an operating voltage and a value representing an operating frequency corresponding to work of said first functioner, and a division ratio of an output signal of said second clock generator, in a form of an operation program, said first functioner reads and executes said operation program from said first internal memory, said second selector selects said first system clock from among said first system clock and said second system clock as a clock to operate said second internal memory, said first functioner and said second internal memory being operated and synchronized using said first system clock, when data in said first functioner is at least one of read from and written to said second internal memory, said second functioner reads and executes said operation program from said second internal memory, said first selector selects said second system clock from among said first system clock and said second system clock as a clock to operate said first internal memory, said second functioner and said first internal memory being operated and synchronized using said second system clock, when data in said second functioner is at least one of read from and written to said first internal memory.