Patent ID: 7733738

Claim:
A semiconductor memory device comprising: a write data controller writing data received with an address to a memory cell corresponding to the address and storing the data in a data register in parallel with writing the data to the memory cell according to a synchronous operation mode signal and an asynchronous operation mode signal; an address controller decoding and storing the address in an address register according to the synchronous operation mode signal and the asynchronous operation mode signal; and a read data controller outputting data from the memory cell corresponding to an address received with a data read command if the received address is different from the address stored in the address register, and outputting the data stored in the data register if the received address is equal to the address stored in the address register, wherein the write data controller comprises: a synchronous operation write circuit receiving the data to be written in response to the synchronous operation mode signal and writing the data to the memory cell in response to a first control signal; and an asynchronous operation write circuit receiving the data to be written in response to the asynchronous operation mode signal or the synchronous operation mode signal, storing the data to be written in the data register in response to the first control signal or a second control signal, and writing the data stored in the data register to the memory cell in response to a third control signal.