Patent ID: 8509078

Claim:
A method of deflection routing in an on-chip interconnection network having one or more on-chip routers, the method comprising: receiving a flow control digit (flit) at an input port of a first on-chip router, each on-chip router in the on-chip interconnection network comprising a number of output ports greater than or equal to a number of input ports, the output ports in communication with other on-chip routers, each on-chip router reachable from every other on-chip router via one or more on-chip network connections; ranking the flit within the first on-chip router; prioritizing the ranked flit to a prioritized output port among the output ports of the first on-chip router; sending the flit towards a destination via the prioritized output port; computing a route of the flit at the first on-chip router; sending lookahead information including the route of the flit from the first on-chip router to a second on-chip router via a lookahead link contemporaneously with the flit traversing a portion of the first on-chip router; allocating a designated output port to a worm comprising a sequence of related flits; and truncating a lower ranking worm previously allocated to the designated output port.