Patent ID: 8335973

Claim:
A processing module for obtaining an error locator polynomial of a BCH code in an error correction decoding circuit in which error corrections of t words are performed using the error locator polynomial, where t denotes a predetermined integer, the processing module comprising: a first register including 0 th to 2t th storage areas, coefficients of a syndrome polynomial being initially stored in the 1 st to 2t th storage areas of the first register; a second register including 0 th to 2t th storage areas; a Galois field division unit configured to perform a Galois field division such that a coefficient stored in the 2t th storage area of said second register is Galois-field-divided by the coefficient stored in the 2t th storage area of said first register; a group of Galois field multiplication units configured to perform Galois field multiplications such that a result of the division of said Galois field division unit is Galois-field-multiplied by the 0th to (2t−1) th coefficients of said first register to obtain respective multiplied coefficients; a group of Galois field addition units configured to perform Galois field additions such that respective ones of the obtained multiplied coefficients are Galois-field-added to respective ones of coefficients stored in the 0 th to (2t−1) th storage areas of said second register to output resulting coefficients of the Galois field additions; a first selector configured to select, as output coefficients thereof, either the resulting coefficients outputs from said group of Galois field addition units or the coefficients stored in said first register; a shifter configured to shift the output coefficients of said first selector to be stored in predetermined storage areas of said first register or predetermined storage areas of said second register; an insertion unit configured to substitute with zero or delete one of the output coefficients of said first selector to output zero-inserted coefficients; and a second selector configured to store the shifted output coefficients of said first selector into one of said first register and said second register, and to store the zero-inserted coefficients from said insertion unit into the other of said first register and said second register, wherein coefficients of the error locator polynomial are a result of repeated calculations performed by said Galois field division unit, said group of Galois field multiplication units and said group of Galois field addition units.