Patent ID: 8188776

Claim:
A phase-locked loop circuit comprising: a first phase comparator configured to compare a phase of a local clock signal with a phase of a first clock signal and to output a signal according to a comparison result; a voltage-controlled oscillator configured to output an output clock signal with a frequency according to a voltage of the signal that is output from the first phase comparator; a first frequency divider configured to frequency-divide the output clock signal that is output from the voltage-controlled oscillator and to output the frequency-divided output signal to the first phase comparator as the first clock signal; a second phase comparator configured to compare a phase of an input clock signal with the output clock signal that is output from the voltage-controlled oscillator; and a control unit configured to control a frequency dividing ratio of the first frequency divider according to a signal that is output from the second phase comparator, wherein the control unit includes an input clock interruption detection unit that is configured to detect an interruption of the input clock signal, and wherein the input clock interruption detection unit is further configured, when the interruption of the input clock signal is detected, to maintain the frequency-dividing ratio of the first frequency divider before the interruption and to control the first divider so that frequency-dividing is applied with the maintained frequency-division ratio of the first frequency divider.