Patent ID: 8456400

Claim:
A liquid crystal device comprising: a plurality of scanning lines; a plurality of data lines that intersect with the scanning lines; a plurality of pixel electrodes that are provided at positions corresponding to intersections of the plurality of scanning lines and the plurality of data lines; a capacitor electrode that is provided opposite each of the pixel electrodes and that forms a capacitor with each of the pixel electrodes or with an electrode layer connected to each of the pixel electrodes; a control circuit that alternately supplies the capacitor electrode with a first voltage or a second voltage that is higher in electric potential than the first voltage, the control circuit including transistors; a scanning line driving circuit that sequentially supplies the plurality of scanning lines with a scanning line selection voltage that selects the scanning line; and a data line driving circuit that, when the scanning line is selected, alternately supplies the plurality of data lines with a positive polarity image signal that is higher in electric potential than the first voltage or a negative polarity image signal that is lower in electric potential than the second voltage, wherein the control circuit includes a selection circuit and a selection signal output circuit, wherein the selection circuit alternately selects and outputs the first voltage or the second voltage to the capacitor electrode, wherein the selection signal output circuit outputs a selection signal to the selection circuit, wherein the first voltage is higher in electric potential than a low electric potential of the selection signal, and the second voltage is lower in electric potential than a high electric potential of the selection signal, wherein a difference in electric potential between a gate and a source of each transistor that constitutes the selection circuit is set lower than a difference in electric potential between a gate and a source of each transistor that constitutes the selection signal output circuit, and wherein a gate length of each transistor that constitutes the selection circuit is set shorter than the gate length of each transistor that constitutes the selection signal output circuit to reduce an amount of crosstalk between the plurality of data lines and the capacitor electrode.