Patent ID: 8539212

Claim:
A method comprising: receiving (i) an address of a branch instruction from a program counter and (ii) a thread tag identifying a thread associated with the branch instruction; determining whether a first active thread and a second active thread reside in (i) separate code spaces within a memory or (ii) a same code space within the memory, wherein one of the first active thread and the second active thread is the thread associated with the branch instruction, and in response to the first active thread and the second active thread being determined to reside in separate code spaces within the memory, selecting a first branch indexing scheme from a plurality of branch indexing schemes, and in response to the first active thread and the second active thread being determined to reside in a same code space within the memory, selecting a second branch indexing scheme from the plurality of branch indexing schemes, wherein each branch indexing scheme of the plurality of branch indexing schemes indicates (i) a corresponding section of the address and (ii) a corresponding section of the thread tag; and generating a branch prediction index based at least in part on selecting (i) a section of the address corresponding to the branch indexing scheme that is selected and (ii) a section of the thread tag corresponding to the branch indexing scheme that is selected.