Patent ID: 8102717

Claim:
A method of testing for a leakage current between bit lines of a nonvolatile memory device, the method comprising: supplying a test voltage to a first bit line of the nonvolatile memory device having a page buffer having the first bit line and a second bit line coupled thereto to a first voltage; supplying a second voltage to the second bit line; floating the second bit line and evaluating the second bit line for a set period of time; measuring a voltage of the second bit line by the page buffer and latching a sensing result in the page buffer; and determining whether the leakage current has occurred between the first bit line and the second bit line by sensing the voltage of the second bit line by the page buffer and storing a first data in the page buffer when the leakage current has occurred between the first bit line and the second bit line and storing a second data in the page buffer when the leakage current has not occurred between the first bit line and the second bit line.