Patent ID: 8552464

Claim:
A device patterned out of a multi-layer interconnect stack atop an Integrated Circuit (IC)-substrate, the multi-layer interconnect stack having: a plurality of microstructures, each microstructure comprising one or more layers of conductive material and insulating material, the microstructures including a microstructure having an upper flange structure, a lower flange structure and a pin structure between the upper and lower flange structures, the upper and lower flange structures forming a gap around the pin structure, wherein the microstructure includes a patterned conductive via material through each insulating material layer for bridging consecutive conductive material layers at selected locations; and an optional bottom anchor layer for anchoring at least one of the microstructures to the IC-substrate, wherein at least a particular one of the microstructures includes a shell portion fully enclosing the particular one microstructure, wherein the shell portion comprises the conductive material plus the conductive via material, wherein the particular one microstructure includes a core portion within the shell portion, the core portion comprising insulating layer material, wherein the layers of conductive material and insulating material comprise CMOS complementary-symmetry metal oxide semiconductor) compatible material, and wherein the microstructure is usable as part of a sensing or actuation device via movement constrained by the gap.