Patent ID: 7908499

Claim:
A semiconductor integrated circuit device comprising: at least one data holding circuit; a combinational circuit including a plurality of logic gate circuits and for receiving an output of the data holding circuit; a high potential power supply line and a low potential power supply line; a first pseudo-power supply line connected via a first power control transistor to the high potential power supply line; and a second pseudo-power supply line connected via a second power control transistor to the low potential power supply line, wherein, of the plurality of logic gate circuits of the combinational circuit, one outputting “L” when the output of the data holding circuit has a predetermined fixed value has a high potential-side power supply end connected to the first pseudo-power supply line and a low potential-side power supply end connected to the low potential power supply line, and one outputting “H” when the output of the data holding circuit has the predetermined fixed value has a high potential-side power supply end connected to the high potential power supply line and a low potential-side power supply end connected to the second pseudo-power supply line, the data holding circuit can continue to hold data during cut-off of power supply which turns off the first and second power control transistors, and the data holding circuit receives a control signal, and when obtaining a predetermined value as the control signal, the data holding circuit can output the predetermined fixed value, wherein: the data holding circuit is a flip-flop circuit having a master latch circuit and a slave latch circuit; the master latch circuit holds data during cut-off of power supply; and the slave latch circuit outputs the predetermined fixed value when the control signal has the predetermined value, and wherein: the master latch circuit comprises: a first logic gate circuit for receiving a D input; and a first data holding inverter circuit for holding an output of the first logic gate circuit, and having a high potential-side power supply end and a low potential-side power supply end connected to the high potential power supply line and the low potential power supply line, respectively, and the slave latch circuit comprises: a second logic gate circuit for receiving an output of the master latch circuit and the control signal, and when the control signal has the predetermined value, outputting the predetermined fixed value; and a second data holding inverter circuit for holding an output of the second logic gate circuit.