Patent ID: 8471323

Claim:
A non-volatile memory device, comprising: a semiconductor substrate including a surface region; a source region within the semiconductor substrate; a drain region within the semiconductor substrate; a first channel region within the semiconductor substrate, the first channel region extending between a first portion of the source region and a first portion of the drain region; a second channel region within the semiconductor substrate, the second channel region extending between a second portion of the source region and a second portion of the drain region; a first dielectric layer overlying the first channel region; a second dielectric layer overlying the second channel region; a floating gate structure overlying the first dielectric layer over the first channel region, the floating gate structure not extending over the second channel region; a third dielectric layer over the floating gate structure; and a control gate layer overlying the second dielectric layer and the third dielectric layer; whereby the second channel region is configured to provide electric carriers to the first channel region during a programming operation of the non-volatile memory device.