Patent ID: 8299466

Claim:
A thin film transistor fabrication method, comprising: depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon; depositing two or more doped silicon layers over the amorphous silicon layer, each doped silicon layer having at least one characteristic that is different than the other doped silicon layers, wherein depositing the two or more doped silicon layers comprises: depositing a first doped silicon layer on the amorphous silicon layer under first deposition conditions, wherein the first deposition conditions comprise a deposition rate of between about 800 Angstroms per minute and about 4000 Angstroms per minute, a deposition time of up to about 30 seconds to produce a first doped silicon layer having a resistivity of between about 70 Ωcm to about 3000 Ωcm; and depositing a second doped silicon layer on the first doped silicon layer under second deposition conditions different than the first deposition conditions, wherein the second deposition conditions comprise a deposition rate of between about 50 Angstroms per minute and about 800 Angstroms per minute for a deposition time of between about 15 seconds to about 3000 seconds to produce the second doped silicon layer having a resistivity of between about 10 Ωcm to about 70 Ωcm; depositing a metal layer over the two or more doped silicon layers; patterning the metal layer to form a source electrode and a drain electrode; patterning the two or more doped silicon layers to expose the amorphous silicon layer; and depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.