Patent ID: 8127262

Claim:
A processor-implemented method of generating a specification of a pipelined packet processor, comprising: inputting a textual specification including an input packet format and an output packet format for packets input to and output from the pipelined packet processor, the input packet format and output packet format including a format for each field in the input packet and output packet, respectively, and a plurality of actions for processing one or more of the fields of the input packet; determining a plurality of pipeline stages from the actions in the textual specification, each of the plurality of actions assigned to a corresponding one of the plurality of pipeline stages; wherein the plurality of pipeline stages includes at least three stages; determining at least one shared variable from the textual specification, each shared variable accessed by actions in at least two stages of the at least three stages, wherein for an initial stage and a last stage of the at least two stages, at least one action in the initial stage writes the shared variable and at least one action in the last stage reads the shared variable, and the initial and last stages are separated by an intermediate stage; and generating with a processor and storing in a storage arrangement, a hardware description that includes, the plurality of pipeline stages and assigned actions, a respective first-in-first-out (FIFO) queue between each adjacent pair of pipeline stages, a respective first register coupled to transfer the shared variable from the initial stage to the intermediate stage and a respective second register coupled to transfer the shared variable from the intermediate stage to the last stage, and control logic for writing to and reading from each respective register.