Patent ID: 7688629

Claim:
A memory device, comprising: a memory cell which includes a floating gate MOS transistor having a charge trap region; a memory cell array, wherein a plurality of memory cells is serially connected to configure NAND flash memory, one side of the memory cell array is connected to a first select transistor, and the other side of the memory cell array is connected to a second select transistor, where the first select transistor is connected to a local bit line; a first reduced swing amplifier serving as a local sense amp, wherein the first reduced swing amplifier includes a local read transistor connecting a local amp node to the local bit line, a local pre-charge transistor for pre-charging the local amp node to a read voltage, a local amplify transistor having a gate for reading the local amp node and a source for connecting to the read voltage, a local select transistor connecting to the local amplify transistor serially where the local select transistor is connected to a segment bit line, and a local write transistor for connecting the local bit line to a write bit line; a second reduced swing amplifier serving as a segment sense amp, wherein the second reduced swing amplifier includes a segment reset transistor for resetting the segment bit line, a segment amplify transistor for reading the segment bit line, and a segment select transistor connecting to the segment amplify transistor serially, where the segment select transistor is connected to a global bit line; a global sense amp which includes a write circuit for transferring a write voltage to the write bit line, a read circuit serving as a third reduced swing amplifier for reading the segment sense amp through the global bit line, and a data transfer circuit receiving an output from the read circuit and sending to an output node, where the third reduced swing amplifier is connected to the read voltage for reducing voltage swing; a variable voltage generator for generating the read voltage, wherein swing of the read voltage is lower than that of the write voltage; a delay circuit serving as a locking signal generator, wherein the delay circuit generates a delayed signal as a locking signal for locking the read circuit, and the delay circuit receives a latched signal from the read circuit as a reference signal based on at least a reference memory cell.