Patent ID: 6858511

Claim:
A method of manufacturing a semiconductor wafer having a via test structure comprising: providing a semiconductor substrate having a plurality of semiconductor devices; depositing a first dielectric layer over the semiconductor substrate; forming a plurality of openings in the first dielectric layer, depositing a first barrier layer to line the plurality of openings; depositing a first conductor core to fill the openings; planarizing the first barrier layer and the first conductor core to form second and fourth channels unconnected to the plurality of semiconductor devices; depositing a via dielectric layer over the first dielectric layer; forming first and second via openings and third and fourth via openings in the via dielectric layer respectively open to opposite ends of the second channel and the fourth channel; depositing a second dielectric layer over the via dielectric layer; forming first, third, and fifth channel openings in the via dielectric layer respectively open to the first via opening, the second and third via openings, and the fourth via opening; depositing a second barrier layer to line the first, second, third, and fourth via openings and the first, third, and fifth channel openings; depositing a second conductor core to fill the first, second, third, and fourth via openings and the first, third, ar fifth channel openings; and planarizing the second barrier layer and the second conductor core to form first, third, and fifth channels having the first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel connected in series whereby the first and fifth channels are probed to determine the presence or absence of voids in the vias.