Patent ID: 8223572

Claim:
A memory device including a memory array, the memory array comprising a plurality of bit line columns comprising a plurality of bit lines, each of the plurality of bit line columns connected to a plurality of memory cells, wherein each of the plurality of memory cells are connected to a plurality of word lines, the memory device comprising: one or more address decoders for selecting at least one of the plurality of bit lines and word lines; a word line driver for enabling at least one of the plurality of word lines; a plurality of sense amplifiers for sensing the plurality of bit lines, wherein each of the plurality of sense amplifiers is associated with a corresponding bit line of the plurality of bit lines; a reference word line column for vertical tracking of the at least one of the plurality of word lines using a first predefined loopback; a reference bit line column comprising a reference bit line for vertical tracking of at least one of the plurality of bit lines using a second predefined loopback; and a control circuit comprising: a dummy decoder for generating a reference word line signal; a first programmable delay circuit connected to the dummy decoder for programming delay of the reference word line signal; and a sense amplifier enable driver for activating a sense amplifier of the plurality of sense amplifiers, wherein fan-out of the sense amplifier enable driver is equal to a fan-out of the word line driver.