Patent ID: 7405441

Claim:
A non-volatile semiconductor memory comprising: a semiconductor body; a charge-trapping element arranged over the semiconductor body, the charge-trapping element comprising a nitride layer sandwiched between a bottom oxide layer and a top oxide layer, the charge-trapping element having two lateral sidewalls opposed to one another; a recess disposed in the bottom oxide layer, wherein the recess does not expose a surface of the semiconductor body; a gate stack arranged over the charge-trapping element, the gate stack having two lateral sidewalls opposed to one another; electrically insulating elements disposed directly upon the opposing sidewalls of the charge-trapping element and covering the sidewalls of the charge-trapping element and only a portion of the sidewalls of the gate stack, the electrically insulating elements comprising inner spacers having a first thickness adjacent the charge-trapping element and smoothly tapering to an end having no thickness at a distance away from the charge-trapping element; and nitride spacers covering the electrically insulating elements, wherein the nitride spacers are arranged on opposing sidewalls of the gate stack and on the electrically insulating elements.