Patent ID: 6897109

Claim:
A method of manufacturing an integrated circuit device comprising the steps of: i) forming a plurality of bit line structures on an integrated circuit substrate, each of said bit line structures including a first conductive layer pattern and a first insulating layer pattern stacked on said integrated circuit substrate; ii) forming a first insulating layer on a surface of the integrated circuit substrate, a sidewall and a surface of the bit line structures; iii) partially etching said first insulating layer using said first insulating layer pattern as an etching mask to thereby form a storage node contact hole exposing a surface of said integrated circuit substrate corresponding to a position between said bit line structures; iv) forming a conductive plug type storage electrode in said storage node contact hole, the conductive plug type storage electrode including a first conductive material; v) forming a first stopping layer on an upper surface of said bit line structures and said storage electrode; vi) forming a second insulating layer on said first stopping layer; vii) forming a contact hole exposing a lower electrode by sequentially etching a portion of said second insulating layer and said first stopping layer; and viii) forming a storage node making contact with said storage electrode in said contact hole with a second conductive material.