Patent ID: 7516310

Claim:
A method for reducing the number of times in-flight loads are searched by store instructions in a multi-threaded processor, the method comprising: i. freezing load issue for a thread t-old for a number of cycles when a thread t-new issues a load instruction and a cache line L is owned by thread t-old such that no new loads for the cache line L are put in flight, wherein the number of cycles is between 8 and 16 cycles to allow existing loads to line L from t-old to finish, making a subsequent snoop from t-new a NOP; ii. rejecting the t-new load instruction; iii. sending notification to the rest of the processor that the t-new load instruction has been rejected; iv. snooping a load reorder queue (LRQ) of thread t-old for any load which comes from the cache line L accessed by the t-old load instruction and then forcing such loads to be re-executed; and v. changing ownership of cache line L to thread t-new.