Patent ID: 8635411

Claim:
A data processing apparatus comprising: an interconnect having a plurality interconnect nodes a arranged to provide at least one ring; a plurality of caching nodes, each caching node being configured to cache data and being coupled into the interconnect via an associated one of said interconnect nodes; at least coherency management node for implementing a coherency protocol to manage coherency of the data cached by each of said caching nodes, each coherency management node being coupled into the interconnect via an associated one of said interconnect nodes; said at least one ring providing a plurality of slots for transmission of information around said at least one ring, within each said at least one ring the slots provided for that ring being passed sequentially between said plurality of interconnect nodes: the at least one coherency management node being configured in response to detection of a coherency condition, to issue a snoop request to at least a subset of said plurality of caching nodes the snoop request having an identifier which identifies at least one slot of said plurality of slots to be used to transmit snoop responses for that snoop request; when each caching node in said at least a subset produces a snoop response for said snoop request, the associated interconnect node being configured to output that snoop response in one of said at least one identified slots; and each interconnect node associated with a caching node having merging circuitry configured, when outputting the snoop response in one of said at least one identified slots, to merge that snoop response with any current snoop response information held in that slot, wherein said plurality of slots comprise request slots and response slots, and said snoop request is output on said at least one ring in one of said request slots, and wherein said identifier for the snoop request is inferred from the request slot in which that snoop request is output.