Patent ID: 7664915

Claim:
An apparatus comprising: a first data processing path to receive a block of data, the first data processing path including a first accumulate buffer to store the block of data and a first arithmetic logical unit to perform a first operation on the block of data; and a second data processing path to receive the block of data, the second data processing path including a second accumulate buffer to store the block of data and a second arithmetic logical unit to perform a second operation on the block of data, the first data processing path and the second data processing path sharing a multiplier, the multiplier to perform a multiply operation on the block of data, each of the data processing paths to process the block of data in parallel to provide a first result block of data and a second result block of data in a single pass of the block of data through the data processing paths, the first arithmetic logical unit has a first programmable polynomial and the second arithmetic logical unit has a second programmable polynomial.