Patent ID: 8470683

Claim:
A method of manufacturing an integrated circuit, the method comprising: depositing and structuring an electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing a first electrically insulating layer on the electrically resistive layer of the TFR, depositing a first conductive layer of an electrically conductive material, leaving an area without the first conductive layer overlapping the electrically resistive layer of the TFR, depositing a second electrically insulating layer on top of the first conductive layer, etching a first VIA opening through the second insulating layer, the area without the first conductive layer adjacent to the first conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR, and depositing a conductive material in the first VIA opening to form a first via that directly electrically connects the first conductive layer and the electrically resistive layer of the TFR.