Patent ID: 7479682

Claim:
A field effect transistor including a gate electrode and a channel region defined by a source region and a drain region, comprising: an insulating layer; a semiconductor layer formed on the insulating layer, wherein the semiconductor layer includes the channel region therein; a pair of impurity layers respectively formed in the source region and the drain region, and which are in contact with the channel region; and a pair of metallic silicide layers respectively formed in the source region and the drain region, wherein the pair of metallic silicide layers are respectively in contact with the pair of impurity layers, wherein bottom surfaces of the pair of metallic silicide layers extend to bottom surfaces of the semiconductor layer, wherein the metallic silicide layers are composed of refractory metal and silicon, wherein a contact specific resistance between the metallic silicide layers and the impurity layers is less than 1×10 −7 Ω−cm 2 , and wherein the semiconductor layer has a thickness of 20 nm or below.