Patent ID: 8680625

Claim:
A semiconductor device, comprising: a semiconductor substrate having an active region and an isolation region, wherein the active region has a first edge which interfaces with the isolation region; a gate structure formed on the semiconductor substrate, the gate structure directly overlying the isolation region, wherein the gate structure includes a first sidewall and an opposing second sidewall; a first spacer element abutting the first sidewall of the gate structure and directly overlying the first edge; and a second spacer element abutting the second sidewall of the gate structure and extending laterally over the isolation region away from the gate structure, wherein the second spacer element includes an outermost edge that is positioned further away from the gate structure than any other edge of the second spacer element, wherein the isolation region extends within the semiconductor substrate from the first edge that is directly below the first spacer element to beyond the outermost edge of the second spacer element, wherein the second spacer element includes a portion physically contacting the isolation region.