Patent ID: 6846704

Claim:
A method for manufacturing a semiconductor package, comprising the steps of: a) providing a semiconductor die having opposed first and second surfaces, a peripheral edge, and a plurality of bond pads disposed on the second surface in close proximity to the peripheral edge; b) providing a plurality of homogenously formed leads which each include a first surface, a second surface disposed in opposed relation to the first surface, and a third surface disposed in opposed relation to the second surface and oriented between the first and second surfaces; c) electrically and mechanically connecting the bond pads of the semiconductor die to the third surface of respective ones of the leads through the use of conductive bumps; and d) applying an encapsulant to the leads, the semiconductor die and the conductive bumps to form an encapsulating portion which at least partially encapsulates the leads, the semiconductor die and the conductive bumps such that the first and a portion of the third surface of each of the leads are covered by the encapsulating portion and the second surface of each of the leads is exposed therein.