Patent ID: 8004087

Claim:
A semiconductor device, comprising: a semiconductor substrate; an insulating film formed above the semiconductor substrate; and a multilayered wiring formed in a prescribed area within the insulating film; wherein the multilayered wiring has a dual damascene wiring positioned on at least one layer of said multilayered wiring, wherein the dual damascene wiring comprises an alloy having copper as a principal component, wherein a concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is determined according to a width of the wiring on an upper layer of the multilayered wiring where the via is connected, wherein the concentration of the at least one metallic element within the via connected to the upper layer wiring increases with the width of the wiring of the upper layer, wherein said multilayered wiring comprises a plurality of wirings, each of said plurality of wiring is spaced apart from an adjacent one of the wirings by said insulating film, widths of the wirings being different from one another, and wherein said via is one of a plurality of vias in the semiconductor device, each of said vias having a same diameter.