Patent ID: 7282410

Claim:
A method of forming an integrated circuit comprising the steps of: forming a first structure at a first region of a substrate wherein the first structure comprises a first insulating layer formed on the substrate, and a poly silicon feature formed on the first insulating layer; forming a second insulating layer at a second region of the substrate, the second insulating layer having an opening formed therein; forming a first thick oxide on the poly silicon feature and simultaneously forming a second thick oxide in the opening of the second insulating layer; forming a first conductive feature over at least a portion of the first thick oxide, and simultaneously forming a second conductive feature physically separated from the first conductive feature, wherein the second conductive feature is over a portion of the second insulating layer, and wherein at least one end of the second conductive feature is over a portion of the second thick oxide; forming a first source and a first drain at the first region and a second source and a second drain at the second region; forming a first spacer along a sidewall of the first conductive feature, the polysilicon feature and the first thick oxide; and forming a second spacer along sidewall of the second conductive feature.