Patent ID: 8230180

Claim:
A multipath-accessible memory device comprising: N input/output ports, each disposed for connection to one of N processors, wherein N is a real number greater than one; at least one channel buffer per each of the N processors, each disposed for storing a plurality M of data packets to be transferred from one processor to another one processor, wherein M is a real number greater than one; a shared memory bank connected in read/write communication to each of the N ports; a plurality of N(N−1) mailboxes, each mailbox connected in read communication to one of the N ports and dedicated for receiving shared memory access command messages from one of the N processors; a semaphore area for storing N(N−1)/2 bits, each bit being connected in read communication to one of the N ports and connected in selectable write communication to a different one of the N ports, the N(N−1)/2 bits being indicative of the currently negotiated access to the shared memory region, wherein the shared memory bank includes the at least one channel buffer per each processor, and each of the at least one channel buffer is disposed for storing a plurality M of data packets to be transferred in a burst mode, and wherein each of the mailboxes is configured to store: bits of a channel index field indicating an active channel buffer; and bits of a packet count field corresponding to a count of the data packets stored the active channel buffer and to be transferred from one processor corresponding to a first mailbox to another one processor corresponding to a second mailbox.