Patent ID: 7957176

Claim:
A semiconductor memory device, comprising: a first inverter and a second inverter which constitute a memory cell and each of which has an input terminal and an output terminal connected crosswise to an output terminal and an input terminal, respectively, of the other; a first power supply control circuit which supplies a first voltage to the first inverter; and a second power supply control circuit which supplies a second voltage to the second inverter, wherein the first and second power supply control circuits control the first and second voltages, respectively, supplied to the first and second inverters in a selected memory cell for a writing operation in accordance with write data, the first power supply control circuit includes a first MOS transistor, a second MOS transistor, a third inverter, and a first NAND circuit, the first inverter is connected to a node where one end of a current passage through the first MOS transistor is connected to one end of a current passage through the second MOS transistor, the first voltage is supplied to the other end of the current passage through the first MOS transistor, and the second voltage is supplied to the other end of the current passage through the second MOS transistor, an output terminal of the first NAND circuit is connected to a gate of the first MOS transistor and to a gate of the second MOS transistor via the third inverter, the second power supply control circuit includes a third MOS transistor, a fourth MOS transistor, a fourth inverter, and a second NAND circuit, the second inverter is connected to a node where one end of a current passage through the third MOS transistor is connected to one end of a current passage through the fourth MOS transistor, the first voltage is supplied to the other end of the current passage through the third MOS transistor, and the second voltage is supplied to the other end of the current passage through the fourth MOS transistor, and an output terminal of the second NAND circuit is connected to a gate of the third MOS transistor and to a gate of the fourth MOS transistor via the fourth inverter.