Patent ID: 7263117

Claim:
An analog delay element for receiving an input clock signal and delaying the input clock signal to produce an output clock signal, the analog delay element comprising: a current source for providing a constant current in response to a first bias voltage, the first bias voltage being generated by a first bias voltage generator programmable by a first set of signals; a clock input transistor connected in series to the current source at a common terminal, the clock input transistor receiving the input clock signal; a first load transistor and a second load transistor arranged in a current mirror configuration; a first input transistor connected in series to the first load transistor, the first input transistor gate being connected to the common terminal; a second input transistor connected in series to the second load transistor at a common output terminal, the second input transistor gate receiving a second bias voltage generated by a second bias voltage generator programmable by a second set of signals, the output clock signal being provided at the common output terminal and, an activating transistor connected to a common node of the first input transistor and the second input transistor for enabling the analog delay element.