Patent ID: 8487682

Claim:
A clock generator, comprising: a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal and to generate a third intermediate clock phase signal in response to the clock signal and a fourth intermediate clock phase signal, the first latch including a second phase interpolation circuit having a first input coupled to a second input of the first latch and a second input coupled to a second output of the first latch; and a first phase interpolation circuit having a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch, wherein the first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals, and wherein the second phase interpolation circuit is configured to output a second clock phase signal in response to receiving the third and fourth intermediate clock phase signals.