Patent ID: 8153481

Claim:
A method of manufacturing a power semiconductor device comprising: on a substrate of more strongly doped first conductivity type silicon, forming a less strongly first conductivity type epitaxial silicon layer; using a plasma enhanced chemical vapor deposition process forming a first silicon dioxide layer directly on the epitaxial silicon layer; introducing into a first region of the epitaxial layer more strongly doped first conductivity type impurity to define a channel stopper region, and introducing into a second region spaced apart from the first region an opposite conductivity type impurity to define an emitter region; using a plasma enhanced chemical vapor deposition process forming a second silicon dioxide layer directly on at least the first silicon dioxide layer to thereby form a first passivation layer which includes both the first silicon dioxide layer and the second silicon dioxide layer; forming a first field plate on the passivation layer, the first field plate extending to electrically contact at least a portion of the emitter region and overlying at least a portion of the epitaxial layer adjacent to the emitter region; forming a second passivation layer on at least a portion of the first passivation layer and on at least a portion of the first field plate; and further comprising a step of introducing platinum or gold into the epitaxial layer.