Patent ID: 7949971

Claim:
A non-transitory machine readable medium including a design structure, the design structure embodied or represented as executable program code which, when executed, causes a machine to perform a method for creating a VLSI circuit, wherein the VLSI circuit includes an IVC-based scan chain for implementing lowered global power dissipation in a semiconductor chip, the method comprising: creating the VLSI circuit including the scan chain, wherein the scan chain comprises: at least two flip-flops, including a first flip-flop and a second flip-flop, configured to operate in normal mode operation, in scan mode operation and in low leakage power mode operation, where each flip-flop includes a data input, a data output, a clock input, a scan-in input and a scan-out output; and an input vector control (IVC) circuit electrically connected between the scan-out output of the second flip-flop and the scan-in input of the first flip-flop within a scan chain, the IVC circuit comprising: a mode control element for controlling operation of the first flip-flop to one of: scan mode, low power leakage mode and initialization mode, wherein the first flip-flop is set to a data output value upon exit from the low power leakage mode, the set data output value equivalent to a value that the first flip-flop is set to at initialization during normal mode operation.