Patent ID: 7599140

Claim:
An output control device that controls an output of a clock signal generated by an oscillator, the output control device comprising: a determining unit that receives the clock signal generated by the oscillator and determines whether the clock signal has an amplitude equal to or greater than a predetermined value; and an output control unit that outputs the clock signal to an output destination when the determining unit determines that the clock signal has the amplitude equal to or greater than the predetermined value, and suspends the output of the clock signal to the output destination when the determining unit determines that the clock signal does not have the amplitude equal to or greater than the predetermined value, wherein the determining unit is configured to output a “High” signal if the determining unit determines that the clock signal has the amplitude equal to or greater than the predetermined value and a “Low” signal if the determining unit determines that the clock signal does not have the amplitude equal to or greater than the predetermined value, a first AND gate configured to receive the clock signal generated by the oscillator and the delayed “High”or “Low” signal from the delay circuit and output the clock signal received if the first AND gate receives the delayed “High”signal from the delay circuit; a second AND gate configured to output a “High” output signal if the second AND gate receives the delayed “High” signal from the delay circuit and a “high” reset signal: and a third AND gate as the output control unit configured to receive the clock signal from the first AND gate and output the clock signal received to the output destination if the third AND gate receives the “High” output signal from the second AND gate.