Patent ID: 8754483

Claim:
A structure comprising: a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, said gate stacks having spacers formed at sidewalls thereof and including a cap layer on top thereof; one or more conductive contacts formed directly on top of said semiconductor substrate and interconnecting at least one source/drain of one of said plurality of field-effect-transistors to at least one source/drain of another one of said plurality of field-effect-transistors, wherein said one or more conductive contacts is part of a low-profile local interconnect (LPLI), said LPLI having a height lower than a height of said gate stacks; one or more vias formed on top of said one or more conductive contacts and directly next to said spacers of said gate stacks, and a conductive path line formed directly above, but not in contact with, said one or more conductive contacts of said LPLI, said conductive path line being formed on top of and in contact with said cap layer of at least one of said gate stacks.