Patent ID: 8350606

Claim:
A delay circuit for delaying and switching the level of an output signal relative to the switching between two levels in a single input signal, wherein: in a period in which the output signal is at a first output level correlated with a first input level of the input signal, a predetermined quantity to be evaluated is increased according to an integrated value of a period in which the input signal is at a second input level, and the output signal is switched from the first output level to the second output level when the quantity to be evaluated exceeds a predetermined upper threshold; and in a period in which the output signal is at a second output level correlated with the second input level, the quantity to be evaluated is reduced according to the integrated value of a period in which the input signal is at a first input level, and the output signal is switched from the second output level to the first output level when the quantity to be evaluated declines below a lower threshold set lower than the upper threshold.