Patent ID: 7791010

Claim:
A design structure encoded on a machine readable data storage medium, said encoded design structure including instructions that when processed by an electronic design automation tool generates a machine executable representation of a CMOS imaging sensor cell, the instructions comprising: a first instruction processed to generate a first FET device adapted to transfer a voltage from a first diffusion region to a second diffusion region, said transferred voltage representing an incident illumination level for a pixel of said sensor cell; a second instruction processed to generate a second FET device configured as a reset switch, a first terminal of the second FET device coupled to the second diffusion region of the first FET device; and a third instruction processed to generate a third FET device having a gate terminal coupled to the second diffusion region of the first FET device for receiving said transferred voltage, a first terminal of said third FET device coupled to a row select (RS) signal and a second terminal of said third FET device coupled to a column signal line, wherein an output signal corresponding to said transferred voltage is generated for output at said column signal line in response to an applied row select signal.