Patent ID: 8847380

Claim:
A method of fabricating a semiconductor assembly, comprising: providing a semiconductor element having a front surface, a rear surface remote from the front surface, and a plurality of conductive pads, each pad having a top surface exposed at the front surface and having a bottom surface remote from the top surface; forming a hole extending at least through a respective one of the conductive pads by processing applied to the respective one of the conductive pads from above the front surface; forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the hole and the opening meet at a location between the front and rear surfaces; forming a first continuous dielectric layer overlying an interior surface of the semiconductor element within the opening; forming a second continuous dielectric layer partially overlying the respective conductive pad at least at a location above the respective conductive pad and overlying an interior surface of the semiconductor element within the hole; and forming a conductive interconnect exposed at the rear surface for electrical connection to an external device, the conductive interconnect extending at least into the opening; and forming a conductive via exposed at the front surface, the conductive via extending at least within the hole and being electrically connected with and directly coupled to the conductive interconnect and the respective conductive pad, wherein the step of forming the conductive interconnect is performed before the step of forming the conductive via, such that the conductive via is formed in contact with a surface of the conductive interconnect exposed within the hole, and wherein the step of forming the hole includes: exposing a surface of the first continuous dielectric layer within the hole; and extending the hole through the surface of the first continuous dielectric layer to expose the surface of the conductive interconnect within the hole.