Patent ID: 8211766

Claim:
A method for manufacturing a trench-typed power MOS transistor, comprising the steps of: forming a deep well region having a first conductivity type property above a substrate region; forming a double diffusion doping region having the first conductivity type property above the deep well region; etching a sidewall of the double diffusion doping region to form a trench region; filling insulating material into the trench region; etching a sidewall of the insulating material opposing the double diffusion doping region to form a gate region such that the trench region comprises a thick sidewall region filled with the insulating material between the gate region and the double diffusion doping region, and to form a thick bottom region filled with the insulating material between the gate region and the deep well region; filling gate conductor into the gate region; forming a well region having a second conductivity type property beside the gate region and above the deep well region; forming a drain region having the first conductivity type property above the double diffusion doping region; and forming a source region having the first conductivity type property above the well region.