Patent ID: 7989294

Claim:
A method comprising: fabricating a field-effect transistor having the following steps to be performed without restriction by the order specified: provision of a carrier material having a surface to be processed, formation of a first terminal region near the surface and a second terminal region remote from the surface, wherein formation of the second terminal region comprises formation of a connecting region extending up from a portion of the of the second terminal region approximately as far as the surface or being electrically conductively connected to an electrically conductive connection leading from the second terminal to the surface; formation of a first depression; formation of a second depression between the first terminal region and the connecting region; production of an electrical insulating layer in the first depression, introduction of an electrically conductive control region into the first depression, wherein the first depression is the only depression formed in the field-effect transistor in which the control region is formed; and using the field-effect transistor at a word line or a bit line of a memory cell array.