Patent ID: 7217999

Claim:
A semiconductor device comprising: an interconnection board having first and second surfaces, said interconnection board having a multilevel insulating resin layer and a multilayer wiring layer therein; at least one external electrode pad buried in said interconnection board, said at least one external electrode pad having an exposed surface level with said second surface so that said second surface and said exposed surface form a single flat plane; at least a semiconductor chip mounted on said first surface of said interconnection board; a buffer layer having a first surface contacting said second surface of said interconnection board; a supporting plate spaced from a second surface of said buffer layer and defining a gap between said second surface of said buffer layer and said supporting plate, said supporting plate having plural holes therein; at least one external electrode in one of said holes in said supporting plate and connected to said at least one external electrode pad through said buffer layer, said at least one external electrode having a diameter smaller than said one of said holes so as to define a space between said at least one electrode and an internal periphery of said one of said holes at a surface of said supporting plate opposite said buffer layer; and a sealing resin in said gap and in said space surrounding and supporting said at least one external electrode.