Patent ID: 8533438

Claim:
A microprocessor, comprising: a queue, comprising a plurality of entries each configured to hold store information for a store instruction, wherein the store information specifies sources of operands used to calculate a store address, wherein the store instruction specifies store data to be stored to a memory location identified by the store address; and control logic, coupled to the queue, configured to encounter a load instruction, the load instruction comprising load information that specifies sources of operands used to calculate a load address, wherein the control logic is configured to detect that the load information matches the store information held in a valid one of the plurality of queue entries and responsively to predict that the microprocessor should forward to the load instruction the store data specified by the store instruction whose store information matches the load information; wherein each of the plurality of entries of the queue is configured to hold a reorder buffet index of the store instruction, wherein the control logic is configured to predict that the microprocessor should forward to the load instruction the store data specified by the store instruction whose store information matches the load information by outputting the reorder buffer index of the store instruction whose store information matches the load information.