Patent ID: 7864865

Claim:
A decoder system for decoding and displaying video data, said decoder system comprising: a frame buffer for storing the video data in accordance with a selected one of a plurality of storing formats; a feeder for rasterizing the stored video data in accordance with a display format; a host processor for providing at least one starting address for a display frame to the feeder; and the feeder calculates at least one starting address for one or more lines in the display frame, based on the selected one of the plurality of storing formats, the feeder further comprising: at least one register for storing the at least one starting address for the current line; a circuit for selecting an increment from a plurality of increments, wherein the circuit selects the increment based on the selected one of the plurality of storing formats that the video data is stored; and an adder for adding the increment to the at least one starting address for the current line; and wherein the circuit for selecting an increment further comprises: a first memory for storing a packed line stride; a second memory for storing a row stride; and at least a third memory for storing at least one line stride for a macroblock storage format.