Patent ID: 7969215

Claim:
A circuit for generating a signal having a desired phase delay comprising: a first delay chain including M delay cells, each of which delay cells phase shifts an incoming signal applied to a first input of the delay cell by an amount determined by a phase shift control signal applied to a second input of the delay cell; a second delay chain for generating the desired phase delay for the signal, said second delay chain including N delay cells, each of which delay cells phase shifts an incoming signal applied to a first input of the delay cell by an amount determined by a phase shift control signal applied to a second input to the delay cell, a first circuit for generating a first phase shift control signal that is applied to the second input of the M delay cells and the second input of at least one of the N delay cells; and a second circuit for generating a second phase shift control signal that is applied to the second input of at least one other of the N delay cells.