Patent ID: 8159199

Claim:
An integrated electronic device including circuitry for providing a single system supply voltage from a primary power supply, the circuitry comprising: a high power (HP) stage coupled to the primary power supply and receiving the single system supply voltage and having an output node coupled to a supply system node for providing a HP system supply voltage level and a HP output current such that the HP stage is configured to be active in a full power mode; and a low power (LP) stage coupled to the primary power supply for receiving the single system supply voltage and to the supply system node through a voltage follower for following a continuous fixed bias voltage and providing a LP supply voltage level and an LP output current such that the LP stage is configured to be active in a low power mode, wherein the HP system supply voltage level is greater than the LP system supply voltage level and the voltage follower of the LP stage is back-biased to switch off in response to a voltage level at the supply system node becoming greater than the HP system supply voltage level and to be forward-biased and switch on in response to the voltage level at the supply system node becoming lower than the HP system supply voltage level, wherein the HP stage comprises a PMOS transistor having a source coupled to the primary power source and a drain coupled to the supply system node, wherein the circuit provides a smooth spike free transition from the high power mode to the low power mode.