Patent ID: 7879738

Claim:
A method for manufacturing an integrated circuit structure including a substrate having a channel region at a surface of the substrate for a memory cell, comprising: forming a bottom dielectric layer in contact with the channel region on the substrate; forming a charge storage element consisting of a middle dielectric layer in contact with the bottom dielectric layer, the middle dielectric layer having a top surface and a bottom surface and comprising a plurality of materials with respective concentration profiles for at least two of the plurality of materials between the top and bottom surfaces that are non-uniform; and forming a top dielectric layer in contact with the middle dielectric layer, wherein the middle dielectric layer comprises silicon oxynitride, and wherein the concentration of oxygen is higher in a region near the interface with the bottom dielectric than near the interface with the top dielectric, and the concentration of nitrogen is higher in a region near the interface with the top dielectric than near the interface with the bottom dielectric, and wherein an energy gap of the middle dielectric layer decreases from (i) maximum energy gaps near the top and bottom surfaces of the middle dielectric layer, toward (ii) a middle of the middle dielectric layer.