Patent ID: 7675055

Claim:
A complementary metal oxide semiconductor (CMOS) structure comprising: a rotated Si-containing semiconductor substrate having a (100) crystal orientation and a wafer notch along the <100> direction; at least one pFET located on a first region of said rotated Si-containing semiconductor substrate, said at least one pFET having a channel that is along said <100> direction; at least one first stressed well located within the first region of said rotated Si-containing semiconductor substrate that induces a stress on said channel of each pFET, wherein said at least one first stressed well includes a compressively strained material of Si or Si containing at least one of C and Ge; at least one nFET located on a second region of said rotated Si-containing semiconductor substrate, said at least one nFET having a channel that is along said <100> direction; at least one second stressed well located within the second region of said rotated Si-containing semiconductor substrate that induces a stress on said channel of each nFET, wherein said at least one second stressed well includes a tensile strained material of Si or SiC; and a tensile strain inducing liner present in the first region over the at least one nFET and in the second region over the at least one pFET, wherein the tensile strain inducing liner has a substantially equal strain in both the first region and the second region.