Patent ID: 7522445

Claim:
A semiconductor device manufacturing system, a semiconductor memory having a plurality of static random access memory cells, a plurality of word lines, and a plurality of first and second bit lines substantially orthogonal to the word lines, each of the static random access memory cell, comprising: a first inverter having a first driver transistor and a first load transistor connected in series between a power supply voltage line and a ground line; a second inverter having a second driver transistor and a second load transistor connected in series between the power supply voltage line and a ground line; a first transfer transistor connected in series between a first bit line and an output of the first inverter; and a second transfer transistor connected in series between a second bit line and an output of the second inverter, the output of the first inverter being connected to an input of the second inverter and an input of the first inverter being connected to the output of the second inverter, wherein at least one of the first and the second driver transistors, the first and the second load transistors, and the first and the second transfer transistors is configured by a plurality of Fin field effect transistor, and the Fin effect transistor is configured by a separate-gate type double-gate field effect transistor comprising a first gate electrode and a second gate electrode, controlling a voltage for the first gate electrode to form a channel, and controlling a voltage for the second gate electrode to decrease a threshold voltage at the time of writing data, wherein the applied voltage for the second gate electrode changes synchronizing with a write enable signal of the static random access memory cell, and the threshold voltage of the double-gate field effect transistor lowers synchronizing with the write enable signal.