Patent ID: 6915356

Claim:
A method of providing access to registers in a data processing system having registers directly accessible by a host processor, the method comprising the steps of: combining into a first group, registers that must frequently be read by the host processor, assigning to the registers in the first group, consecutive addresses corresponding to a first end of an address range, combining into a second group, registers that must frequently be written by the host processor, assigning to the registers in the second group, consecutive addresses corresponding to a second end of the address range opposite with respect to the first end, accessing the registers in the first group in a single burst read transfer, accessing the registers in the second group in a single burst write transfer, combining into a third group, registers that must frequently be both read and written by the host processor, assigning to the registers in the third group, consecutive addresses between the addresses of the first group and the addresses of the second group, accessing the registers in the first and third groups in the same burst read transfer, and accessing the registers in the second and third groups in the same burst write transfer.