Patent ID: 7459852

Claim:
A plasma display panel comprising: a front substrate; a common electrode and a scan electrode arranged on a lower surface of the front substrate; a bus electrode electrically connected to the common electrode and the scan electrode; a front dielectric layer covering the common electrode, the scan electrode, and the bus electrode; a rear substrate facing the front substrate; an address electrode arranged on an upper surface of the rear substrate to cross the bus electrode; a barrier rib arranged between the front and rear substrates; and a phosphor layer arranged on a discharge space defined by the barrier rib; wherein the bus electrode includes a display unit bus electrode arranged on a display area that displays pixels and a non-display unit bus electrode arranged on a non-display area electrically connected to the display unit bus electrode and connected to an external terminal, and wherein the display unit bus electrode and the non-display unit bus electrode have different structures; wherein the display unit bus electrode includes a dual-layered structure of a first bus electrode and a second bus electrode arranged on the first bus electrode, the first bus electrode being arranged close to the front substrate than the second bus electrode; wherein the second bus electrode is wider than the first bus electrode; and wherein the non-display unit bus electrode includes a single-layered structure electrically connected to the external terminal.