Patent ID: 7242741

Claim:
A core logic chip that transmits out a parallel data according to a strobe signal and a parallel data signal, comprising: a delay phase-locked loop (PLL) device for generating a plurality of output clock signals with different phases in response to a reference clock signal, comprising: a controlled delay circuit having a plurality of controlled delay lines interconnected in series and outputting therefrom a plurality of output clock signals; a phase detector electrically connected to an output end of said controlled delay circuit, and generating an adjusting signal according to a phase relation between said reference clock signal and one of said output clock signals; and a control circuit electrically connected to said phase detector and said controlled delay lines, and asserting a plurality of control signals to said controlled delay lines, respectively, in response to said adjusting signal in order to independently adjust the delay time of said output clock signals using said controlled delay lines, thereby obtaining four output signals P 0 , P 1 , P 2 and P 3 with different phases; and a logic circuit for logically operating said four output signals P 0 , P 1 , P 2 and P 3 to generate a SEL-data signal and a SEL-strobe signal, based on which said parallel data signal and said strobe signal are generated, said logic circuit comprising: a first inverter for inverting said output signal P 1 ; a first AND gate for logically operating said output signal P 0 and said inverted output signal P 1 to obtain a first logic output R 1 ; a second inverter for inverting said output signal P 3 ; a second AND gate for logically operating said output signal P 2 and said inverted output signal P 3 to obtain a second logic output S 1 ; and a first flip flop for outputting said SEL-data signal with said first logic output R 1 and said second logic output S 1 serving as reset and set terminals thereof, respectively.