Patent ID: 7732317

Claim:
A method of forming a contact structure for a memory device, comprising: forming first and second spaced apart gate patterns on a substrate; forming an etch stop layer on at least a first sidewall of the first gate pattern and a second sidewall of the second gate pattern, wherein the etch stop layer on the first and second sidewalls define a gap therebetween; forming an interlayer dielectric layer on the etch stop layer, the interlayer dielectric layer filling the gap; planarizing the interlayer dielectric layer; anisotropically etching the interlayer dielectric layer to form a preliminary contact hole in the interlayer dielectric layer that has a width that is narrower than a width of the gap; isotropically etching the interlayer dielectric layer to widen the preliminary contact hole to form a contact hole, wherein the isotropic etching of the interlayer dielectric layer exposes the etch stop layer in the gap; and depositing a conductive material in the contact hole to form a contact plug that is electrically connected to the substrate, wherein a width of an upper portion of the contact hole is larger than a width of a bottom portion of the contact hole; and wherein the anisotropic etch of the interlayer dielectric layer that forms the preliminary contact hole does not expose the etch stop layer and wherein a width of the preliminary contact hole is narrower than the width of the gap at the bottom of the gap.