Patent ID: 8867404

Claim:
An apparatus for synchronizing a plurality of digital subscriber line access multiplexers (DSLAMs) comprising: a reference clock configured to generate a reference clock signal; an interface configured to transmit the reference clock signal to the DSLAMs, wherein each of the DSLAMs is configured to align its system clock with the reference clock; a trigger clock configured to generate a trigger clock pulse; a tick counter clock; at least one memory; and a processor configured to: upon a rising edge of the trigger clock pulse, save values of a tick counter, a symbol counter, and a Sync symbol counter into the at least one memory, wherein the tick counter, the symbol counter, and the Sync symbol counter are based on a count of clock cycles of the tick counter clock; receive values of a DSLAM tick counter, a DSLAM symbol counter, and a DSLAM Sync symbol counter from each of the at least one DSLAMs; for each of the DSLAMs, compute a first offset between the tick counter and the DSLAM tick counter, and compute a second offset in symbols based on the values of the symbol counter, the Sync symbol counter, the DSLAM symbol counter, and the DSLAM Sync symbol counter, wherein, for each of the DSLAMs, the apparatus is configured to transmit the first offset and the second offset to the corresponding DSLAM so that the corresponding DSLAM can synchronize with the apparatus.