Patent ID: 7163883

Claim:
An edge seal around the periphery of an integrated circuit device comprising: a semiconductor substrate; a layer of low-k dielectric material over the semiconductor substrate; a layer of hard material over or under the layer of low-k dielectric material, the layer of hard material selected from the group consisting of a dielectric material and a hard mask material; and an edge seal structure around the periphery of an integrated circuit device comprising: a metallic wall of a high conductivity metal in the layer of low-k dielectric material and in the layer of hard material; and a layer of insulation material on sidewalls of the metallic wall between the metallic wall and the low-k dielectric material and between the metallic wall and the layer of hard material, wherein the insulation material and low-k dielectric material are different materials and wherein the insulation material is selected from the group consisting of SiO 2 , SiC, Si 3 N4, Al 2 O 3 , diamond like carbon, polyimide and combinations thereof.