Patent ID: 8546868

Claim:
A MONOS non-volatile semiconductor memory device, comprising: source/drain regions formed in a semiconductor substrate; a first gate insulating layer formed on a channel region located between the source/drain regions; a first charge trapping layer formed on the first gate insulating layer; a second gate insulating layer formed on the first charge trapping layer, having a larger film thickness than that of the first gate insulating layer, and comprising an insulating film comprising Al and O as major elements, wherein: the insulating film comprises a first insulating film, a second insulating film formed on the first insulating film and functioning as a second charge trapping layer, and a third insulating film formed on the second insulating film and having a larger thickness than that of the first gate insulating layer, the second insulating film comprises Al and O as major elements, and comprises an Al vacancy, an interstitial O atom, an N atom substituting for O atom, or a divalent cationic atom substituting for Al atom, the second insulating film has electron unoccupied levels within a range of 2 eV from the valence band maximum of Al 2 O 3 ; and a controlling electrode formed on the second gate insulating layer.