Patent ID: 7242615

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a data hold circuit configured to hold read data or write data of said memory cell array; a data bit detection circuit so connected to said data hold circuit as to detect a bit number of “ 0 ” or “ 1 ” in data held therein; and an internal control circuit, which serves for controlling data write, erase and read, and includes a data bit register for storing the bit number detected by said data bit detection circuit, said internal control circuit serving to output the bit number stored in said data bit register to external terminals in response to a command input, wherein said data bit detection circuit is a fail bit counter circuit, which detects a fail bit number in a data write mode or a data erase mode, and said data bit register is a fail bit register, which stores data of the fail bit number detected by said fail bit counter circuit, and wherein said internal control circuit performs sequence control by repeat of write or erase voltage application and the following verify operation, and makes said fail bit counter circuit detect a fail bit number held in said data hold circuit prior to the sequence ending due to that the number of write or erase cycles has reached a certain value, and then stores the detected result in said fail it register.