Patent ID: 7498255

Claim:
A method for fabricating a chip structure, comprising: providing a silicon substrate, a first internal circuit in and on said silicon substrate, a second internal circuit in and on said silicon substrate, a first intra-chip driver or receiver in and on said silicon substrate, a second intra-chip driver or receiver in and on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure connects a first terminal of said first intra-chip driver or receiver to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure connects a first terminal of said second intra-chip driver or receiver to said second internal circuit, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a second terminal of said first intra-chip driver or receiver, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to a second terminal of said second intra-chip driver or receiver, and a passivation layer over said dielectric layer; and forming a fifth interconnecting structure and a polymer layer over said passivation layer, wherein said fifth interconnecting structure is in said polymer layer, and wherein said second terminal of said first intra-chip driver or receiver is connected to said second terminal of said second intra-chip driver or receiver through, in sequence, said third interconnecting structure, said fifth interconnecting structure and said fourth interconnecting structure.