Patent ID: 7573092

Claim:
A semiconductor device comprising: a first transistor; and a second transistor, wherein the first transistor comprises: a semiconductor layer; a first insulating film formed on a memory cell region of the semiconductor layer; a first electrode layer formed on the first insulating film; a first element isolating region formed of a first element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the first element isolating region isolating a first element region and being self-aligned with the first electrode layer; a second insulating film formed on the first electrode layer and the first element isolating region; and a second electrode layer formed above the second insulating film, the second transistor comprises: a third insulating film formed on the semiconductor layer; a third electrode layer formed on the third insulating film; a second element isolating region formed of a second element isolating insulating film formed to extend through the third electrode layer and the third insulating film to reach the inner region of the semiconductor layer, the second element isolating region isolating a second element region and being self-aligned with the third electrode layer; a fourth insulating film formed on the third electrode layer and the second element isolating region, an open portion exposing a surface of the third electrode layer being formed in the fourth insulating film; and a fourth electrode layer formed above the fourth insulating film and the exposed surface of the third electrode layer, the fourth electrode layer being electrically connected to the third electrode layer via the open portion, the third and fourth electrode layers forming a second gate electrode, and a void is formed between a plurality of transistors.