Patent ID: 7528027

Claim:
A method of forming a device, comprising: forming an oxide layer on top of an SOI CMOS structure having an nFet region and a pFet region, wherein a top of the oxide layer is co-planar with a top of the pFet region; patterning a hardmask nitride layer to cover the oxide layer above the nFet region; removing poly-Si in the pFet region; removing gate oxide in the pFet region to expose an SOI layer in a channel area of the pFet region; removing the hardmask nitride layer above the nFet region; performing a wet anisotropical etch of the SOI layer in the pFet region to form a v-shape trench having a surface in a (111) plane; forming a gate oxide in the trench; depositing poly-Si on top of the gate oxide; and removing the oxide layer.