Patent ID: 8009489

Claim:
A memory, comprising: a first pair of bit lines comprising a first bit line and a second bit line; a word line; a first memory cell coupled to the word line, the first bit line, and the second bit line; a sense amplifier including a first input, a second input, a first output, and a second output, the second output being a complementary output to the first output; a first pair of coupling transistors comprising a first transistor and a second transistor, wherein the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier; and a write back circuit including a first input coupled to the first output of the sense amplifier, a second input coupled to the second output of the sense amplifier, a first terminal coupled to the first bit line, and a second terminal coupled to the second bit line; wherein the first terminal of the write back circuit is connected to the first bit line and the second terminal of the write back circuit is connected to the second bit line such that the write back circuit provides a path from one of the first bit line or the second bit line to a supply voltage terminal to write a first value or a second value respectively to the first memory cell during a write back phase of a read cycle of the first memory cell.