Patent ID: 8166229

Claim:
A processor-based system, comprising: a processor; a system memory coupled to the processor; a mass storage device; a multi-level non-volatile cache memory located between the system memory and the mass storage device; and code stored on the processor-based system to cause the processor-based system to utilize the multi-level non-volatile cache memory, wherein the multi-level non-volatile cache memory includes: a first level non-volatile cache memory, the first level non-volatile cache memory having a first set of operating characteristics; and a second level non-volatile cache memory, the second level non-volatile cache memory having a second set of operating characteristics, wherein the second set of operating characteristics are different from the first set of operating characteristics, wherein the code is configured to cause the processor-based system to utilize the first level non-volatile cache memory differently from the second level non-volatile cache memory in accordance with the respective first and second set of operating characteristics, wherein the code is configured to cause the processor-based system to implement a first cache insertion policy for the first level non-volatile cache memory and a second cache insertion policy for the second level non-volatile cache memory, wherein the first cache insertion policy is different from the second cache insertion policy, and wherein the code is further configured to cause the processor-based system to receive a request for mass storage access, the request requesting information to be accessed on the mass storage device, and to cache the information in one of the first level non-volatile cache memory and the second level non-volatile cache memory in accordance with the respective first and second cache insertion policies.