Patent ID: 8891310

Claim:
An electrically erasable and programmable memory comprising: a word of memory cells each including a floating gate transistor; a first control gate transistor configured to apply a control gate voltage to the floating gate transistors of the memory cells of the word; a second control gate transistor in parallel with the first control gate transistor and of a same conductivity type as the first control gate transistor, and configured to also apply the control gate voltage to the floating gate transistors of the word; and a control circuit configured to supply a first control voltage to a control terminal of the first control gate transistor and a second control voltage to a control terminal of the second control gate transistor, the control circuit including: a first current limiter electrically coupled to the control terminal of the first control gate transistor and configured to limit current drawn through the first control gate transistor, and a second current limiter electrically coupled to the control terminal of the second control gate transistor and configured to limit current drawn through the second control gate transistor.