Patent ID: 8102471

Claim:
An H-sync phase locked loop device, comprising: an analog-to-digital converter, for receiving a TV video signal with an H-sync and converting the received signal into a digital TV video signal; an auto-gain-control and clamping circuit, for receiving the digital TV video signal, performing an AGC and clamping processing and then generating a clamped signal with a controlled amplitude; a slice level calculator, for receiving the above-mentioned clamped signal, estimating the level of the H-sync and outputting a level-indicating signal; an H-sync frequency calculator, comprising: a first circuit section, for receiving the clamped signal and the level-indicating signal, detecting the falling and rising transients of the H-sync according to the received signals and producing a first enabling signal for updating and a second enabling signal for updating; a second circuit section, for calculating the difference between the period of the H-sync of the input signal and the period of a standard H-sync; a clamping and low-pass filtering circuit, for receiving the difference output from the second circuit section and converting the difference into an average error value by means of the operation of the clamping and low-pass filtering circuit; a third circuit section, for receiving the average error value and the first enabling signal for updating, adding the predetermined total pixel quantity output from each line to the average error value and then updating the standard period of the input H-sync according to the first enabling signal for updating; a low-pass filter, for low-pass filtering the standard period of the H-sync for output; a register unit, for receiving the output from the low-pass filter and the second enabling signal for updating, updating the storage content according to the enabling of the second enabling signal for updating for output; and a calculation circuit, for receiving the storage content of the register unit, calculating the received content and obtaining an H-sync frequency; an increment step number calculator, for outputting an increment step number according to the H-sync frequency, a predetermined frequency for each line to output pixels, and a predetermined total pixel quantity output from each line; and a discrete time oscillator, for receiving the increment step number and a dynamic increment step number and for adjusting the frequency of the timing signal output from the phase locked loop circuit according to the received step numbers.