Patent ID: 8095343

Claim:
A method for modeling source-drain current of a thin film transistor (TFT), comprising: (a) receiving experimentally determined sample data, the sample data including sample input values and a sample output value; (b) adjusting modeling variables of a modeling equation according to the sample input values; (c) calculating a model output value according to the adjusted modeling variables; (d) repeating steps (b) and (c) with the adjusted modeling variables until a difference between the calculated model output value and the sample output value is smaller than a predetermined threshold value, the adjusted modeling variables when the difference becomes smaller than the threshold value being used as final modeling variables for the modeling equation; applying values for V G and V D as actual input data to the modeling equation with the final modeling variables, where V G is a gate voltage and V D is a drain voltage; and outputting a result value corresponding to the actual input data, wherein the modeling equation predicts the source-drain current of the TFT, wherein the modeling equation is I DS =I leak +(1/I b +1/I a ) −1 , where I DS denotes drain-source current, I leak denotes leakage current of the TFT, I b denotes a first current value that is a source-drain current value calculated in a regime below a threshold voltage, and Ia denotes a second current value that is a source-drain current value calculated in a regime above a threshold voltage, wherein the first current value is determined by equations: I b =( WC/L )( K b /( b +2))( V GF b+2 −( V GF −V D ) b+2 ) when V GF >0, and I b =0 when V GF ≦0 where V GF denotes a difference between a gate voltage and a flat band voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V D denotes a drain voltage, and K b and b denote modeling variable values, and wherein the second current value is determined by the following equation: I a =( WC/L )( K a /( a+ 2))( V GTe a+2 −( V GTe −V D ) a+2 ), where V GTe =(V min /2)(1+(V GT /V min )+(Δ 2 +(V GT /V min −1) 2 ) 0.5 ), V GT denotes a difference between a gate voltage and a threshold voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V D denotes a drain voltage, Vmin denotes a minimum voltage, ka and a denote modeling variable values, and Δ denotes a variable indicating convergence strength.