Patent ID: 8879351

Claim:
A page buffer of a memory bank having a memory array coupled to bitlines and wordlines, the page buffer comprising: first and second page buffer sections, the first page buffer section comprising a first enabler and a first page buffer segment coupled to first bitlines and datelines and configured to access the first bitlines, the second page buffer section comprising a second enabler and a second page buffer segment coupled to second bitlines and the datelines and configured to access the second bitlines, the first enabler being configured: to receive an input column select signal; and to provide an output column select signal in response to a clock signal, the output column select signal being derived from the input column select signal, and a first enable signal to the first page buffer segment in response to the input column select signal, the first enable signal enabling column selection of the first page buffer segment, the second enabler being configured: to receive the output column select signal from the first enabler as an input column select signal thereof, and to provide a second enable signal to the second page buffer segment in response to the input column select signal thereof, the second enable signal enabling column selection of the second page buffer segment.