Patent ID: 8664777

Claim:
A semiconductor die comprising: i) an integrated circuit formed on one surface of a piece of semiconductor wafer; ii) a plurality of input-output (I/O) pads interconnected to said integrated circuit; iii) a routing layer formed on said semiconductor wafer, said routing layer comprising a layer of dielectric material; iv) a plurality of under-bump metallizations (UBMs) formed atop said routing layer, each for attaching a respective one of a plurality of solder bumps; v) a plurality of conductive traces, each extending through said routing layer from one of said I/O pads to a contact point for a corresponding one of said UBMs and electrically interconnecting said one of said I/O pads to said corresponding one of said UBMs; wherein at least one of said conductive traces passes beneath a reinforced one of said UBMs without electrically contacting said reinforced one of said UBMs, to mechanically reinforce said routing layer proximate said reinforced one of said UBMs.