Patent ID: 8212547

Claim:
A system, comprising: an apparatus configured to measure a duty cycle of a clock signal, the apparatus including: a first multi-tap delay module having an input to receive the clock signal, the first multi-tap delay line configured to provide a first constant incremental delay at each tap; a second multi-tap delay module having an input to receive the clock signal, the second multi-tap delay line configured to provide a second constant incremental delay at each tap where the first constant incremental delay is less than the second constant incremental delay; and a multi-element detecting module in which each element has a first input operatively coupled to a selected tap of the first multi-tap delay module, and a second input operatively coupled to a corresponding tap of the second multi-tap delay module, the multi-element detecting module structured to determine the ratio of the number of outputs of the multi-element detecting module in which the sampled clock signal level is high with respect to a total number of steps covering one complete clock cycle to thereby determine the duty cycle of the clock signal.