Patent ID: 7543258

Claim:
A clock design apparatus comprising: a delay time adjusting section configured to adjust signal delay time of signal propagation paths on a semiconductor integrated circuit to be designed; a prohibition specifying section configured to provide circuit specifications which identify a part of the signal propagation paths as a circuit prevented from being changed; and a clock tree synthesis section configured to perform a clock tree synthesis (CTS) process to synthesize a clock tree of the semiconductor integrated circuit in accordance with the circuit specifications made by the prohibition specifying section, wherein delay times associated with fixed delay information are obtained; wherein the delay adjusting section is configured to specify delay as a function of the delay times: wherein the semiconductor integrated circuit comprises a first logical block, and a second logical block, wherein an operating frequency of the second logical block and a voltage supplied to the second logical block are variable; wherein an operating frequency of the first logical block and a voltage supplied to the first logical block are predetermined fixed values: and wherein clock delay adjustments that are independent of changes to apparatus supply voltages may be obtained as a function of the specified delay.