Patent ID: 6858494

Claim:
A method of fabricating a new structure for split gate flash memories in which contact regions are self aligned to conductive lines, comprising: providing a silicon substrate and forming parallel alternating isolation regions and active regions; forming a gate oxide- 1 layer over said active regions; forming a doped poly- 1 layer over said gate oxide- 1 layer; forming a silicon nitride layer over said poly- 1 layer; forming and patterning a first photoresist layer and etching said silicon nitride layer to form equally spaced parallel, alternating wide and narrow silicon nitride sections perpendicular to the active regions; etching said poly- 1 layer between said silicon nitride sections to form sloped poly- 1 profiles; removing said first photoresist layer; depositing an oxide- 2 layer and performing CMP on this layer to the level of the silicon nitride sections; forming and patterning a second photoresist layer and sequentially etching the narrow silicon nitride sections and the underlying poly- 1 regions to expose the underlying gate oxide- 1 and creating narrow openings; performing a source ion implantation to form source regions under the exposed gate oxide- 1 ; removing the second photoresist layer; forming an oxide- 3 layer and etching said oxide- 3 layer to form oxide- 3 spacers along sidewalls of said narrow openings; depositing a doped poly- 2 layer and performing CMP to remove all poly- 2 outside said narrow openings and creating poly- 2 source lines running perpendicular to the active regions and contacting the source regions; forming oxide- 4 caps over the tops of said poly- 2 source lines; performing a silicon nitride etch to remove the wide silicon nitride sections and creating wide openings; sequentially etching the poly- 2 layer and oxide-layer from the bottoms of the wide openings; forming an oxide- 5 layer over exposed silicon and polysilicon surfaces; forming a doped poly- 3 layer- and perform CMP on said poly- 3 layer to the top of the oxide- 2 layer; performing a poly- 3 etch to form poly- 3 spacer regions that act as word lines running perpendicular to the active regions; forming an oxide- 6 layer over exposed surfaces of poly- 3 spacer regions; performing a drain ion implantation to form drain regions under the exposed oxide- 5 ; performing an oxide etch to remove exposed oxide- 5 and underlying oxide formed during formation of said oxide- 6 layer but leaving an oxide- 6 layer of reduced thickness over said poly- 3 spacer regions; forming a doped poly- 4 layer; and forming and patterning a third photoresist layer and etching said poly- 4 layer to produce poly- 4 lines over said active regions that serve as bit lines.