Patent ID: 7855420

Claim:
A design structure embodied in a machine readable medium, the design structure comprising: one or more logic circuits positioned in a region of a semiconductor substrate, said substrate having a top surface and a bottom surface, said one or logic circuits comprising first FETs having first well regions in said substrate, said first well regions extending from said top surface of said substrate into said substrate a first distance, said first distance less than a whole distance between said top and bottom surfaces of said substrate; an I/O cell and an ESD protection device in said region of said substrate, said I/O cell comprising second FETs having second well regions in said substrate and said ESD protection device comprising third FETs having third well regions in said substrate, said second well regions extending from said top surface of said substrate into said substrate a second distance, said third well regions extending from said top surface of said substrate into said substrate a third distance, said second and third distances less than said whole distance; shallow trench isolation between said first, second and third FETs, said shallow trench isolation having a top surface coplanar with said top surface of said substrate and a opposite bottom surface in said substrate, said shallow trench isolation extending from said top surface of said substrate into said substrate a fourth distance, said fourth distance less than said whole distance; and an electrically conductive through via extending from said bottom surface of said substrate into said substrate a fifth distance, said fifth distance less than said whole distance, said through via abutting said bottom surface of shallow trench isolation between said ESD protection device and said I/O cell and at least one of said one or more logic circuits and intervening between said ESD protection device and said I/O cell and at least one of said one or more logic circuits.