Patent ID: 7263015

Claim:
A signal interface for interfacing with an address decoder, said signal interface comprising: a signal capture element operable to receive an address portion signal associated with a data access to a memory and to provide a first interim address portion signal and a second interim address portion signal, said signal capture element being operable during a pre-charged period to provide a first pre-charged logic level as said first interim address portion signal and said first pre-charged logic level as said second interim address portion signal, said signal capture element being further operable during an evaluate period to output an address portion logic level representative of said address portion signal as said first interim address portion signal and an inverted address portion logic level representative of an inverted address portion signal as said second interim address portion signal; and an inverter circuit operable to receive said first interim address portion signal and said second interim address portion signal from which a first address portion signal and a second address portion signal is respectively derived, said inverter circuit being operable during said pre-charged period to output to an address decoder a second pre-charged logic level as said first address portion signal and said second pre-charged logic level as said second address portion signal, receipt by said address decoder of said first address portion signal and said second address portion signal at said second pre-charged logic level causing said address decoder to be prevented from causing a data access to said memory from occurring, said inverter circuit having transfer characteristics which cause said first address portion signal and said second address portion signal to be maintained at voltage levels interpreted by said address decoder as being said second pre-charged logic level should said first interim address portion signal or said second interim address portion signal fail to transition to a valid logic level during said evaluate period.