Patent ID: 7071679

Claim:
A method for testing a system on a chip having a programmable section and a plurality of high-speed interfaces, the method comprises: configuring the programmable section to support a first level testing of the plurality of high-speed interfaces; testing one of the plurality of high-speed interfaces at the first level testing via the programmable section, wherein the first level testing tests performance characteristics of the one of the plurality of high-speed interfaces to produce tested performance characteristics; evaluating the tested performance characteristics in accordance with prescribed performance characteristics of one of a plurality of standards to determine whether the one of the plurality of high-speed interfaces conforms with the one of the plurality of standards; when the one of the plurality of high-speed interfaces conforms with the one of the plurality of standards, configuring the plurality of high-speed interfaces for a second level testing; and testing remaining ones of the plurality of high-speed interfaces in accordance with the second level testing.