Patent ID: 8555225

Claim:
A method comprising: generating, on a computer, a set of stress parameters based on locations of transistors within an integrated circuit layout, wherein each stress parameter in the set includes coordinates within the layout to which the stress parameter applies, and wherein each stress parameter in the set includes a modifier for a transistor parameter that applies to the location indicated by the coordinates; generating, on the computer, a database of transistors and locations of the transistors corresponding to a block of the integrated circuit, wherein the database maintains a hierarchy of the block and one or more subblocks of the block that are instantiated in an electronic description of the block; querying, on the computer, the database of transistors and locations using a schematic transistor name, wherein an output from the database includes coordinates of the transistor identified by the schematic transistor name; identifying stress parameters from the set of stress parameters that correspond to the schematic transistor name responsive to the coordinates of the stress parameters and the coordinates output from the database; and annotating each queried schematic transistor with identified stress parameters from the set as determined in the querying and the identifying.