Patent ID: 7026859

Claim:
A delay locked loop control circuit, comprising: a latch connected to a first node for latching a locked state signal; a level setting unit for setting an initial level of the locked state signal, which is decided whether or not phases of a reference clock and a feedback clock are aligned; a signal generation unit for generating a third control signal according to a first control signal, the first control signal is a phase difference indicating the result of phases comparison of the reference clock and the feedback clock, and a second control signal, the second control signal is for checking out phases of the reference clock and the feedback clock in every predetermined time; a level maintaining unit for maintaining a level of the locked state signal according to the locked state signal and a fourth control signal outputted from a phase detector, the fourth control signal is a phase difference indicating the result of phases comparison of a signal delaying the feedback clock for a predetermined time with the reference clock; a detection unit for varying a level of the locked state signal by detecting whether or not phases of the reference clock and the feedback clock are aligned according to the first to third control signals; and a control unit for controlling a variation of the locked state signal by means of the detection unit according to the fourth control signal.