Patent ID: 7754560

Claim:
An integrated circuit, comprising: a memory circuit comprising: a first P-channel transistor, wherein the first P-channel transistor includes a first channel region; a first N-channel transistor coupled to the first P channel transistor, wherein the first N-channel transistor includes a second channel region; and a second N channel transistor functioning as a pass transistor coupled to the first P channel transistor and the first N channel transistor; a logic circuit comprising: a second P-channel transistor, the second P-channel transistor includes a third channel region, the third channel region includes a portion located along a first sidewall of a first semiconductor structure, the first sidewall of the first semiconductor structure having a surface orientation of (110), the portion of the third channel region along the first sidewall has a first vertical dimension, wherein the hole transport of the third channel region is in a generally horizontal direction, wherein the first semiconductor structure has a top surface with a surface orientation of (100); wherein: the first channel region includes a portion located along a second sidewall of the second semiconductor structure, the second sidewall of the second semiconductor structure has a surface orientation of (110), the portion of the first channel region along the second sidewall has a second vertical dimension, the second vertical dimension is less than the first vertical dimension, the second semiconductor structure has a top surface with a surface orientation of (100), and the second channel region includes a portion located along a third sidewall of a third semiconductor structure, the third sidewall of the third semiconductor structure has a surface orientation of (100), the structure has a top surface with a surface orientation of (100).