Patent ID: 7565585

Claim:
An integrated redundancy architecture for providing BIST redundancy allocation to an embedded memory system, the integrated redundancy architecture comprising: a BIST for identifying and transmitting row and column addresses of failed memory cells of embedded memory; a first memory element for storing, as to-be-repaired row addresses, ones of the row addresses assigned by said BIST for repair by row redundancy; a second memory element for storing, as to-be-repaired column addresses, ones of the column addresses assigned by said BIST for repair by column redundancy; a third memory element for accumulating ones of the row and column addresses of the failed memory cells not already contained in said first and second memory elements and for assigning each of the row and column addresses accumulated in said third memory element a particular weight value based on the number of the row and column addresses already accumulated in said third memory element and the relative locations within the memory system of the row and column addresses accumulated in said third memory element; and a means for: determining whether the row address of a failed memory cell matches any of the to-be-repaired row addresses stored in the first memory element; determining whether the column address of the failed memory cell matches any of the to-be-repaired column addresses stored in the second memory element; if the row address of the failed memory cell does not match any of the to-be-repaired row addresses stored in the first memory element and the column address of the failed memory cell does not match any of the to-be-repaired column addresses stored in the second memory element, storing the row and column addresses of the failed memory cell in the third memory element; if either the row address of the failed memory cell matches one of the to-be-repaired row addresses stored in the first memory element or the column address of the failed memory cell matches one of the to-be-repaired column addresses stored in the second memory element, or both, then: determining whether the row address of another failed memory cell matches any of the to-be-repaired row addresses stored in the first memory element; and determining whether the column address of the another failed memory cell matches any of the to-be-repaired column addresses stored in the second memory element.