Patent ID: 7366035

Claim:
A ferroelectric memory, comprising: a memory cell array in which a plurality of memory cells are disposed, each of the memory cells including a ferroelectric capacitor; a plurality of wordlines; a plurality of platelines; and a plurality of wordline driver circuits, wherein a K-th wordline driver circuit among the plurality of wordline driver circuits includes: a driver which drives a K-th wordline; a transfer transistor provided between the driver and the K-th wordline; and a gate control circuit which performs gate control of the transfer transistor, and wherein the gate control circuit performs gate control which causes the transfer transistor to be turned on, and performs gate control which causes the transfer transistor to be turned off to set the K-th wordline in a high impedance state, before a voltage of the K-th wordline is boosted after the transfer transistor has been turned on and the K-th wordline has been driven by the driver, wherein the driver drives a K-th plateline corresponding to the K-th wordline after the transfer transistor has been turned off.