Patent ID: 8902460

Claim:
A signal processing circuit that transfers a signal between an externally connected device and an internal circuit, the signal processing circuit comprising: a clock selecting unit that selects and outputs any one of clocks received from a plurality of different systems; a plurality of data latch units that respectively latch, according to the respective clocks received from the systems, input data to form latched data; a data selecting unit that selects and outputs, among the latched data, a piece of the latched data latched according to the selected clock; and a data retaining unit that temporarily retains the piece of the latched data between the data latch units and the internal circuit, wherein when the piece of the latched data is processed between the data retaining unit and the internal circuit, the data retaining unit operates according to an operating clock of the internal circuit, but when the piece of the latched data is processed between the data retaining unit and the data latch units, the data retaining unit operates according to the selected clock.