Patent ID: 8487454

Claim:
A semiconductor device, comprising: a die pad comprising a first surface and a second surface; a first chip arranged on the first surface of the die pad, the first chip comprising a first side and a second side crossing to the first side; a second chip arranged over the first surface of the die pad; a plurality of first recesses formed on the first surface of the die pad; a plurality of second recesses formed on the first surface of the die pad, the plurality of second recesses being different from the plurality of first recesses in at least one of size and geometry; a wire, one end of the wire being connected to the first chip; a resin encapsulating the first chip, the second chip, and the wire; and a lead, one end of the lead being connected to another end of the wire, and a part of the lead being encapsulated by the resin, wherein the plurality of first recesses comprises a third recess and a fourth recess, and the first chip is arranged in a first area, wherein the first area is defined as an area surrounded by a first imaginary line, a second imaginary line, a third imaginary line, and a fourth imaginary line, wherein the first imaginary line is crossed to the third recess and is parallel to the first side of the first chip, wherein the second imaginary line is crossed to the third recess and is parallel to the second side of the first chip, wherein the third imaginary line is crossed to the fourth recess and is parallel to the first side of the first chip, and wherein the fourth imaginary line is crossed to the fourth recess and is parallel to the second side of the first chip.