Patent ID: 8633580

Claim:
A stacked semiconductor chip assembly, comprising: a first semiconductor chip having a first face, a dielectric material exposed at the first face and metallic features exposed at the first face and protruding away from the dielectric material; a second semiconductor chip having a second face, a dielectric material exposed at the second face and metallic features exposed at the second face and protruding away from the dielectric material, the second face confronting the first face and the metallic features of the second semiconductor chip being joined with the metallic features of the first semiconductor chip, the first and second semiconductor chips including a conductive via extending continuously within the first and second semiconductor chips, the conductive via being spaced apart from the joined metallic features and extending through a cavity between the dielectric material exposed at each of the first and second faces; and a wall at least partially occupying the cavity adjacent the conductive via and extending between the first and second faces, the wall hindering movement of a first conductive material from the conductive via to the metallic features, and the wall hindering movement of a second conductive material from the metallic features to the conductive via.