Patent ID: 6995617

Claim:
A frequency acquisition and phase-lock loop having a symbol rate, and comprising: a first input; a VCO having an I and a Q outputs; a first multiplier that receives as input the first input and the I and Q outputs, and which has an I′ and a Q′ outputs; a second multiplier that multiplies the I′ and Q′ outputs by a first fixed frequency to produce an I″ and Q″ outputs; a third multiplier that receives as input the I″ and Q″ outputs and convolves them to produce an I′″ and Q′″ outputs; a fourth multiplier that receives at input the I′″ and Q′″ outputs and multiplies them by a second fixed frequency to produce a first I″″ and Q″″ outputs; a fifth multiplier that receives at input the I′″ and Q′″ outputs and multiplies them by a third fixed frequency to produce a second I″″ and Q″″ outputs; first and second low-pass filters that receive as input the first and second I″″ outputs to produce a first and second filtered I″″ outputs, respectively; a sixth and seventh multipliers that receive as input the first and second Q″″ outputs, respectively, and the first and second filtered I″″ outputs, respectively, to produce a first and second response outputs, respectively; a summer that receives as input the first and second response outputs to produce a combined response signal; a third low-pass filter that receives as input the combined response signal to produce a filtered combined response signal; wherein the filtered combined response signal is returned to the VCO to complete the feedback loop.