Patent ID: 8344792

Claim:
A circuit for generating a reference voltage for use in a semiconductor device, the circuit comprising: an external reference voltage generating circuit, disposed outside a chip, configured to output a first reference voltage, based on an external power supply voltage, to an output terminal of the external reference voltage generating circuit; and an internal reference voltage generating circuit, disposed inside the chip, configured to output a second reference voltage, based on an internal power supply voltage of the chip, to an output terminal of the internal reference voltage generating circuit, wherein the internal reference voltage generating circuit includes: at least one pull-up resistor coupled between a first node and the output terminal of the internal reference voltage generating circuit, wherein the first node is electrically coupled to the internal power supply voltage of the chip; and at least one pull-down resistor coupled between a second node and the output terminal of the internal reference voltage generating circuit, wherein a voltage at the second node is lower than a voltage at the first node, and wherein the reference voltage corresponding to an average value between a voltage level corresponding to a logic high and a voltage level corresponding to a logic low is present at a node where the output terminal of the external reference voltage generating circuit is coupled to the output terminal of the internal reference voltage generating circuit.