Patent ID: 7767536

Claim:
A method of fabricating a semiconductor device, comprising: forming a device isolation area on a semiconductor substrate to define an active area therein; forming a well region, a channel stop region, and a threshold voltage adjustment doped region in the entire active area by implanting impurity ions in the active area at different depths, respectively; after forming the well region, channel stop region, and threshold voltage adjustment doped region, stacking a gate oxide layer and a gate on the active area of the substrate; forming lightly doped regions and halo regions in prescribed regions in the active area of the substrate; forming a spacer on a sidewall of the gate; and using the gate and the spacer as a mask, forming source and drain regions in prescribed regions in the active area of the substrate; and using the gate and the spacer as a mask, separately forming additional doped regions below the source and drain regions and above the channel stop region, wherein the additional doped regions and the source and drain regions are doped with the same impurity ions.