Patent ID: 7630410

Claim:
A bit stream multiplexer that couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media, the bit stream multiplexer comprising: a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than the first plurality, the first transmit data multiplexing integrated circuit includes: an input ordering block having an input to receive the first plurality of bit streams, and an output that presents to the multiplexing hierarchy of the first transmit data multiplexing integrated circuit the first plurality of bit streams in the first input order or a different input order than the first input order in accordance with an input order select input; a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order; a media interface that receives the single bit stream output at the line bit rate and couples the single bit stream output at the line bit rate to the high-speed bit stream media; and wherein the first plurality of bit streams is differential with a positive and a negative polarity signal and is presented to the multiplexing hierarchy in the first input order in response to a first state of the input order select input, and in an input order that swaps the polarities of differential output signals of the first input order in response to a second state of the input order select input.