Patent ID: 8462569

Claim:
A system on a chip (SOC), comprising: memory having a plurality of memory locations and a plurality of redundant memory elements, the memory configured to store data in the plurality of memory locations, wherein each of the plurality of memory locations has a corresponding memory address; a memory control module configured to, in response to detecting that one or more of the plurality of memory locations are defective, locate one or more of the plurality of redundant memory elements that are available, and store, in a memory repair database, information associating the memory address of each of the plurality of memory locations detected to be defective with a corresponding one of the plurality of redundant memory elements that is available; and a redundant memory decoder module configured to, based on the information, physically remap the memory address of each of the plurality of memory locations detected to be defective to the corresponding one of the plurality of redundant memory elements that is available.