Patent ID: 8461888

Claim:
A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a divider arranged to receive the output signal and divide the output signal to form a feedback signal, the divider being arranged to vary the divisor by which the output signal is divided, a comparison unit arranged to compare the feedback signal with the reference signal and a charge pump arranged to generate current pulses for controlling the signal generator in dependence on said comparison, the phase-locked loop being arranged such that: when the comparison unit determines that the phase-locked loop is in a locked condition, the charge pump generates current pulses in dependence on an error in the feedback signal that is caused by the variation of the divisor; and when the comparison unit determines that the phase-locked loop is not in the locked condition, the charge pump does not generate current pulses in dependence on an error in the feedback signal that is caused by the variation of the divisor.