Patent ID: 8443029

Claim:
A computer method of executing a machine instruction by a central processing unit, the method comprising: a) executing, by a computer processor, a decimal floating point instruction configured to perform a decimal floating point operation, the decimal floating point instruction configured to utilize a round-for-reround mode, the executing step comprising: 1) producing, by the computer processor, an intermediate result of the executed decimal floating point operation, the intermediate result having a high order portion and a low order portion, the high order portion corresponding to a hardware format, the hardware format having a first number of digits of precision including a least significant digit; 2) rounding, by an Arithmetic Unit (AU), the high order portion according to the round-for-reround mode, wherein the rounding step comprises the step of: 2.1) if the least significant bit of the high order portion is 0 and if the value of the low order portion is greater than 0, changing the least significant bit of said high order portion to 1 to form a to-be-stored high order portion; 2.2) if the least significant bit of the high order portion of the intermediate result produced in step 1) is 1, or if the value of the low order portion of said intermediate result produced in step 1) is 0, leaving the least significant digit of said high order portion unchanged to form said to-be-stored high order portion; 3) storing, in a computer processor storage unit, the to-be-stored high order portion as a final result of the executed decimal floating point operation; and b) subsequent to execution of the decimal floating point instruction, executing, by the computer processor, a decimal reround instruction, the decimal reround instruction configured to round a decimal floating point number to any of a plurality of rounding precisions, the step of executing the decimal reround instruction execution comprising the steps of: 1) fetching, by the processor, the stored final result of the executed decimal floating point operation, the fetched final result having a first number of bits representing a first number of decimal digits; 2) determining a decimal reround instruction specified rounding precision of the plurality of rounding precisions, wherein the specified rounding precision employs a second number of digits consisting of two or more fewer digits than the first number of digits; 3) rounding, by the AU, the fetched final result to the second number of digits specified by the decimal reround interaction; and 4) storing, in a computer processor storage unit, the rounded final result of the executed decimal floating point operation as a result of the decimal reround instruction.