Patent ID: 7333171

Claim:
A thin film transistor array panel comprising: an insulating substrate; a plurality of first signal lines formed on the insulating substrate; a plurality of second signal lines formed on the insulating substrate, insulated from the first signal lines, and intersecting the first signal lines; a plurality of pixel electrodes provided on the respective pixel areas defined by the intersections of the first and the second signal lines, each pixel electrode having a cutout; a plurality of direction control electrodes provided on the respective pixel areas defined by the intersections of the first and the second signal lines; a first thin film transistor connected to a relevant one of the first signal lines, a relevant one of the second signal lines and a relevant one of the pixel electrodes; a second thin film transistor connected to a previous one of the first signal lines, a previous one of the second signal lines and a relevant one of the direction control electrodes; and a third thin film transistor connected to the previous first signal line, the relevant second signal line and the relevant pixel electrode.