Patent ID: 8854858

Claim:
A system on chip (SoC) comprising: one or more core logic blocks that are configured to operate on a lower supply voltage; a memory array configured to operate on a higher supply voltage, wherein the memory array comprises: n rows by m columns of bit cells; m bit lines each coupled to a corresponding one of the m columns of bit cells; m write drivers each coupled to a corresponding one of the m bit lines, wherein the m write drivers are configured to operate on the lower supply voltage; and wherein each bit cell comprises: two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors; a sense amp coupled to the node Q, wherein the sense amp is configured to operate on the higher supply voltage; and a transfer gate coupled between the node Q and one of the m bit lines; and wherein the memory array further comprises a controller, wherein the controller is operable to perform a write cycle to a selected bit cell by: activating the write driver coupled to the bit line of the selected cell to provide a data bit voltage responsive to the lower supply voltage and enabling the transfer gate of the selected bit cell, such that the data bit voltage is transferred to the node Q of the selected bit cell; isolating the node Q of the selected bit cell from the write driver; and activating the sense amp of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage.