Patent ID: 8122192

Claim:
A data processing apparatus, comprising: a first processor which executes a target program; a second processor; and an external RAM to/from which the first processor writes/reads data; wherein the first processor includes: a cache memory that stores at least a part of the target program; and a first memory controller which controls input/output of data to/from the cache memory; wherein the second processor includes a second memory controller which controls input/output of data directly to/from the cache memory of the first processor; wherein the first processor initializes the cache memory so that the first memory controller accesses the cache memory without accessing the external RAM; wherein the first processor notifies the second processor of completion of the initialization of the cache memory using a notification signal; wherein, in response to the notification signal, the second memory controller directly writes the at least a part of the target program into the initialized cache memory of the first processor without using the first memory controller to perform said writing; wherein the first processor executes the target program without accessing the external RAM; and wherein initialization of the cache memory causes the first processor to execute the target program such that the first processor recognizes the at least a part of the target program that was written into the initialized cache memory of the first processor as being a program code that was fetched by the first processor from the external RAM, rather than as being a program code that was written by the second processor.