Patent ID: 8334198

Claim:
A method of fabricating a plurality of gate structures, comprising: providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process, wherein the hard mask layer is not formed over the plurality of dummy gates; removing the dummy gate electrode layer; removing the dummy oxide layer, wherein removing the dummy oxide layer comprises exposing the dummy oxide layer to a vapor mixture at a pressure between 10 mTorr and 25 mTorr; depositing a gate dielectric over the hard mask layer; depositing a gate electrode over the gate dielectric and the hard mask layer; and removing portions of the gate dielectric, portions of the gate electrode and the hard mask layer using a planarization process.