Patent ID: 8324052

Claim:
A method of fabricating a nonvolatile memory device, the method comprising: forming a string selection gate, a ground selection gate, and a plurality of memory cell gates therebetween on an active region of a semiconductor substrate; forming first impurity regions extending into the active region to a first depth in portions of the active region between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, in portions of the active region between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto, and in portions of the active region between adjacent ones of the plurality of memory cell gates; and forming second impurity regions of a same conductivity type as the first impurity regions extending into the active region to a second depth greater than the first depth in the portions of the active region between the string selection gate and the first one of the plurality of memory cell gates, and in the portions of the active region between the ground selection gate and the last one of the plurality of memory cell gates, wherein the portions of the active region between the adjacent ones of the plurality of memory cell gates are free of impurity regions extending to depths greater than the first depth such that the first impurity regions define respective single-diffused source/drain regions therein, and wherein the portions of the active region between the string selection gate and the first one of the plurality of memory cell gates and the portions of the active region between the ground selection gate and the last one of the plurality of memory cell gates include both the first and second impurity regions to define double diffused source/drain regions therein.