Patent ID: 7750667

Claim:
A semiconductor integrated circuit for use in performing a revision of an integrated circuit mask, comprising: an MOS logic including a plurality of MOS transistors operating by a first voltage and a second voltage; a first switching transistor unit disposed between a supply terminal of the first voltage and the MOS logic, and being operable to be turned off to disconnect an electrical connection between the supply terminal of the first voltage and the MOS logic; a second switching transistor unit disposed between a supply terminal of the second voltage and the MOS logic, and being operable to be turned off to disconnect an electrical connection between the supply terminal of the second voltage and the MOS logic; a first fuse unit disposed between the supply terminal of the first voltage and the first switching transistor unit, including first fuses for cuffing off a supply of the first voltage to the first switching transistor unit by a selective cut based on a test result including a current drive capability of the first switching transistor unit; and a second fuse unit disposed between the supply terminal of the second voltage and the second switching transistor unit, including second fuses for cuffing off a supply of the second voltage to the second switching transistor unit by a selective cut based on a test result including a current drive capability of the second switching transistor unit, wherein the first and second fuses are cut to perform the revision.