Patent ID: 8097940

Claim:
A stack package, comprising: a substrate having a first face and a second face opposite the first face, and including an opening; a first semiconductor chip mounted on the first face of the substrate and including a first through electrode provided in the middle region of the first semiconductor chip, wherein the first through electrode is exposed through the opening of the substrate; a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the first through electrode of the first semiconductor chip; and a circuit pattern on the second face of the substrate, the circuit pattern including a bonding pad arranged adjacent to the opening and electrically connected to the first through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad, wherein first surfaces of the first and second semiconductor chips face the first face of the substrate.