Patent ID: 7781808

Claim:
A semiconductor apparatus on a floating silicon substrate of an SOI (Silicon On Insulator) structure, wherein: the semiconductor apparatus comprises: a perfectly depleted or close to being perfectly depleted partially depleted-type MIS (Metal Insulator Semiconductor) transistor on the floating silicon substrate surrounded by an insulating isolation region and electrically insulated; and a capacitor comprising two electrodes and an insulating film; one electrode of the capacitor is connected to a gate electrode of the MIS transistor and the other electrode of the capacitor is connected to an impurity diffusion layer within the floating silicon substrate, the other electrode of the capacitor being diffused with same impurities as the floating silicon substrate, and different from a source and a drain of the MIS transistor; and a BJT (Bipolar Junction Transistor) where the drain of the MIS transistor corresponds to a collector, the floating silicon substrate corresponds to a base, and the source of the MIS transistor corresponds to an emitter, and where, when gate voltage with respect to the source is V GS , gate capacitance of the MIS transistor is C G , capacitance of the capacitor is C C , parasitic capacitance is C P , clamp voltage of the BJT is V C , and a floating silicon substrate potential immediately prior to change in gate potential is V B(I) , then V B(I) +(C G +C C )*V GS /(C G +C C +C P )>V C .