Patent ID: 6956519

Claim:
A switched capacitor circuit comprising: an operational amplifier having a first input terminal and a first output terminal; a first sampling capacitor having a first terminal and a second terminal, the first terminal being connected to the first input terminal of the operational amplifier; a first signal input switch controlled by a first clock having a first terminal and a second terminal, the first terminal being connected to the second terminal of the first sampling capacitor, the second terminal being used for receiving a first input signal; a first reference input switch controlled by a second clock having a first terminal and a second terminal, the first terminal being connected to the second terminal of the first sampling capacitor, the second terminal being used for receiving a first reference signal; a first input reset switch controlled by a third clock having a first terminal and a second terminal, the first terminal being connected to the first input terminal of the operational amplifier, the second terminal being used for receiving a common signal; a first reference reset switch controlled by a reset clock having a first terminal and a second terminal, the first terminal being connected to the second terminal of the first reference input switch, the second terminal being used for receiving the common signal, the first clock, the second clock, and the reset clock each being out of phase with each other; and a first feedback network connected between the first input terminal of the operational amplifier and the first output terminal of the operational amplifier.