Patent ID: 7471538

Claim:
A memory module, comprising: an interconnection board having a first side and a second side, the first side including a hub location and the second side including an unpopulated location opposite the hub location, the first and second sides further including a plurality of memory device stack locations exclusive to the hub location and the unpopulated location; a hub operatively coupled to the interconnection board at the hub location of the interconnection board, the hub configured to support a plurality of DQ signals on the memory module; and a plurality of memory devices including a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices, the first and second portions of memory devices grouped into a plurality of memory device stacks and operatively coupled to the interconnection board at the plurality of memory device stack locations, wherein each of the plurality of memory device stacks includes at least one of the plurality of memory devices coupled to a first portion of the plurality of DQ signals and at least another one of the plurality of memory devices coupled to a different second portion of the plurality of DQ signals.