Patent ID: 7751212

Claim:
A circuit, comprising: first, second, and third input terminals to receive respective first, second, and third phase signals for three-phase power signals; a diode bridge coupled to the first, second, and third input terminals and having DC output terminals; a series of terminal sets for respective load capacitors, the series of terminal sets coupled across the DC output terminals; a first pair of series-coupled switches having a first end coupled to the first input terminal to receive the first phase signal and a second end coupled to a DC output voltage terminal; a second pair of series-coupled switches having a first end coupled to a second input terminal to receive the second phase signal and a second end coupled to the DC output voltage terminal; a third pair of series-coupled switches having a first end coupled to the third input terminal to receive the third phase signal and a second end coupled to the DC output voltage terminal, and a first pair of series-coupled diodes, a second pair of series-coupled diodes, and a third pair of series-coupled diodes, the first, second, and third pairs of series-coupled diodes coupled in parallel, wherein diodes in the first pair of series-coupled diodes are coupled cathode to anode, diodes in the second pair of series-coupled diodes are coupled cathode to anode, and diodes in the third pair of series-coupled diodes are coupled cathode to anode, wherein a first node is located between diodes in the first pair of series-coupled diodes and between switches in the first pair of series-coupled switches, a second node is located between diodes in the second pair of series-coupled diodes and between switches in the second pair of series-coupled switches, and a third node is located between diodes in the third pair of series-coupled diodes and between switches in the third pair of series-coupled switches wherein the first, second, and third pairs of series-coupled diodes include a first end directly connected to a point between first and second load capacitor terminal pairs, and a second end directly connected to a point between third and fourth load capacitor terminal pairs.