Patent ID: 8860111

Claim:
A memory device, comprising: a substrate including an array of access devices having a corresponding array of contacts; a plurality of word lines coupled to the array of access devices; a separation layer over the substrate and the plurality of word lines; an array of bottom electrodes, the bottom electrode comprising pillars of electrode material through the separation layer, contacting corresponding contacts in the array of contacts; an array of memory elements comprising programmable resistance material in contact with the array of bottom electrodes, wherein the memory elements in the array of memory elements have respective widths that vary across the array within a range having an extent of more than 4.5 nm; and a plurality of bit lines in electrical communication with the memory elements providing a current path from the bottom electrodes through corresponding memory elements; wherein the bottom electrodes in the array of bottom electrodes have respective widths that vary across the array of bottom electrodes within a range having an extent of less than 3 nm.