Patent ID: 7132362

Claim:
A method for manufacturing a semiconductor device comprising: forming plural interconnection lines, each comprising an interconnection layer, a capping layer, the capping layer defining a contact resistance, and an etching stopper, on a semiconductor substrate; forming an interlayer insulating layer overlying the plural interconnection lines, wherein the thickness of a portion of the interlayer insulating layer on one of the etching stoppers is different from the thickness of a portion of the interlayer insulating layer on the others; etching the interlayer insulating layer to form first contact holes therein; stopping etching when a top surface of each etching stopper is exposed; removing a portion of each etching stopper exposed by the first contact holes by performing a dry etching method using an etchant having a low etching selectivity between the etching stopper and the capping layer, thereby forming second contact holes, and leaving the capping layers of the plural interconnection lines at substantially the same thickness such that the contact resistances of the plural interconnection lines are substantially uniform; and forming a conductive layer within the second contact holes, wherein the interconnection layer, the capping layer, and the etching stopper are formed by sequentially depositing a first material layer for interconnection, a second material layer for capping, and a third material layer for stopping etching, patterning the third material layer, and then patterning the second and first material layers, using the patterned third material layer.