Patent ID: 8917119

Claim:
An output driving circuit, comprising: a first buffer configured to generate a first control signal at a first node in response to a first input signal; a second buffer configured to generate a second control signal at a second node in response to a second input signal having an opposite phase of the first input signal; a pull-up transistor configured to generate a first output signal at an output node, and electrically connect a supply voltage to the output node in response to the first control signal; a pull-down transistor configured to generate a second output signal at the output node, and electrically connect a ground voltage to the output node in response to the second control signal; and a noise canceller configured to form a current path between the output node and the ground voltage to decrease noise of the first output signal when the pull-up transistor is in an on state and the pull-down transistor is in an off state, wherein the noise canceller is electrically connected to the first node, the second node, and the output node, wherein the pull-down transistor is an NMOS transistor, wherein the pull-up transistor is an NMOS transistor configured to have a lower threshold voltage than that of the pull-down NMOS transistor, or the pull-up transistor is a PMOS transistor, and wherein the noise canceller comprises: an auxiliary pull-down NMOS transistor having a source connected to the ground voltage and a drain connected to the output node; and a driving control circuit electrically connected to the first node and the second node, and configured to control the auxiliary pull-down NMOS transistor in response to the first and second control signals.