Patent ID: 8405953

Claim:
A capacitor-embedded substrate comprising: a base material of silicon having a desired thickness; a pair of conductors formed in respective desired patterns to penetrate completely through the base material in a thickness direction thereof, and oppositely disposed with an insulating layer of silicon dioxide interposed therebetween, wherein the pair of conductors is formed in respective comb-shaped patterns, and is oppositely disposed in such a manner that respective comb-tooth portions are meshed with each other, and the pair of conductors is divided into a plurality of divided portions electrically insulated from each other, such that a plurality of capacitor portions are arranged; an upper insulating layer formed on the plurality of capacitor portions; via holes reaching the pair of conductors in the plurality of capacitor portions, respectively; and a wiring pattern formed on the upper insulating layer, and connecting the conductors of the plurality of capacitor portions through the via holes.