Patent ID: 7652353

Claim:
A semiconductor device comprising: a first transistor including a plurality of first gates that are arranged in a multi-finger structure, wherein the plurality of first gates are arranged in parallel at a predetermined pitch in a first region; and a second transistor including a plurality of second gates that are arranged in a multi-finger structure and having a conductivity type differing from that of the first transistor, wherein the plurality of second gates are arranged in parallel at a predetermined pitch and at an angle of 45 degrees in a second region with respect to a gate width direction of the first transistor, with one of the plurality of second gates having a maximum gate width; wherein the second region includes an ineffective region free from the second transistor, and a ratio of the pitch between the second gates to the maximum gate width of the second transistor is set less than a reference ratio that is determined in accordance with a ratio of the area of the ineffective region to the area of the second region; and wherein the first region and the second region each have a square shape or a rectangular shape, each first gate of the first transistor is arranged in parallel to one side of the first region, each second gate of the second transistor is arranged at an angle of 45 degrees with respect to one side of the second region, and the second gates of the second transistor are formed in two or more different gate widths.