Patent ID: 7948794

Claim:
A nonvolatile memory device comprising: a plurality of memory blocks divided into a plurality of memory block groups, each memory block group comprising at least two memory blocks of the plurality of memory blocks; a main word line common to the plurality of memory blocks; a plurality of sub-word lines corresponding to the plurality of memory blocks; a plurality of sub-word line drivers coupled between the main word line and each sub-word line, each sub-word line driver responding to a signal applied to the main word line and controlling a level of a corresponding sub-word line, wherein sub-word lines of the plurality of sub-word lines located within the same memory block group of the plurality of memory block groups are electrically connected and sub-word lines of the plurality of sub-word lines located in different memory block groups of the plurality of memory block groups are electrically isolated from each other, and wherein the plurality of sub-word lines are discharged when the signal applied to the main word line is a first level and the plurality of sub-word lines are maintained with a fixed level higher than ground voltage when the signal applied to the main word line is a second level.