Patent ID: 7797824

Claim:
A method for decreasing impedance of a power source in a printed circuit board, comprising: forming a first metal plane in a first routing layer of the printed circuit board; forming a second metal plane and a third metal plane horizontally spaced therefrom, in a second routing layer of the printed circuit board, the second and third metal planes being vertically spaced from the first metal plane, the vertical spacing between the first metal plane and the second and third metal planes being greater than the horizontal spacing between the second and third metal planes, the third metal plane entirely overlying the first metal plane and being connected to a common electrical ground potential, the third metal plane being formed in a first notch formed in the second metal plane, and the third metal plane defined entirely within the second metal plane and being insulated from the second metal plane, wherein a dielectric layer is disposed between the first routing layer and the second routing layer of the printed circuit board for insulating the first routing layer from the second routing layer; connecting the second metal plane to a first electric potential different from the common electrical ground potential, wherein the first metal plane and the third metal plane are both connected to the common electrical ground potential; and punching holes through the dielectric layer between the first metal plane and the third metal plane for connecting the third metal plane with the first metal plane.