Patent ID: 8334860

Claim:
A data processor system comprising: a baseband processor configured as a host microcomputer to perform a reproducing process of audio data from an audio port and an image process of photographing data from a camera port; an accelerator coupled to the baseband processor; a display driving control device coupled to the baseband processor and the accelerator; and a display device coupled to the display driving control device, wherein the display driving control device includes: a first high-speed serial interface circuit coupled to the baseband processor and which has one differential serial data channel; a second high-speed serial interface circuit coupled to the accelerator and which has a plurality of differential serial data channels; a control circuit which controls an internal operation based on control information input to the first high-speed serial interface circuit from the baseband processor; a RAM to receive data that is input to the first high-speed serial interface circuit from the baseband processor and data that is input to the second high-speed serial interface circuit from the accelerator; and a display driver circuit which generates a display driving signal, based on data read from the RAM, to output to the display device, wherein whether the first high-speed serial interface circuit or the second high-speed serial interface circuit is used when receiving the data to be supplied to the RAM is determined by the control circuit based on the control information input to the first high-speed serial interface circuit.