Patent ID: 8103934

Claim:
A system for detecting and correcting memory errors in a memory word containing N data bits, wherein N is a numerical multiple of 4, using an interleaved code word containing 2N bits, wherein N bits are check bits and the remaining N bits are the data bits from the memory word, and wherein the check bits and the data bits are interleaved, the system comprising: a check bit generator coupled to a processor and a memory, comprising N check bit generator blocks divided into groups, wherein a check bit generator block performs logical operations on inputs to generate an output, wherein each check bit generator block applies a logical operation of XOR on three data bits, wherein a group of 4 check bit generator blocks takes four data bits as inputs and generates four check bits as outputs, and wherein each check bit is determined from a unique group of three data bits; a syndrome bit generator coupled to the memory, comprising N syndrome bit generator blocks to generate N syndrome bits, wherein each syndrome bit is the output of a syndrome bit generator block, wherein each syndrome bit generator block applies a logical operation of XOR on four bits comprising three date bits and one check bit in total, and wherein the three data bits are the unique group; and a correction bit generator coupled to the syndrome bit generator and the processor, comprising N correction bit generator blocks, wherein each correction bit generator block has four inputs, one data bit and three syndrome bits, and one output, wherein the data bit input to a correction bit generator block is a data bit to be corrected, wherein the three syndrome bits input to the correction bit generator block are the three syndrome bits that were determined using the data bit to be corrected, wherein each correction bit generator block applies a logical operation of XOR on a result and the data bit, wherein the result outputs from a logical operation of AND on the three syndrome bits, and wherein a corrected data bit is the output of the correction bit generator block.