Patent ID: 8365117

Claim:
A computer-implemented method of generating a library object for an integrated circuit design, the method performed using at least one computing device, the method comprising: analyzing a pair of integrated circuit design objects for fringe capacitance effects between the pair of integrated circuit design objects using the at least one computing device, the analyzing including: determining a type of fringe capacitance scenario between the pair of integrated circuit objects, the type of fringe capacitance scenario selected from the group consisting of: a fringe capacitance between a signal metal line and a wide metal line or ground plane in the integrated circuit design, a fringe capacitance between a first signal line and a second signal line in the integrated circuit design, and a fringe capacitance between an edge of a first line on a first level of the integrated circuit design and a second line on a second level of the integrated circuit design; and building a model of the fringe capacitance effect based upon the determined type of fringe capacitance effect; and generating the library object accounting for the fringe capacitance effects prior to completion of a layout design for the integrated circuit design using the at least one computing device.