Patent ID: 7871913

Claim:
A method for manufacturing a semiconductor device having a vertical transistor, comprising the steps of: forming hard masks on a semiconductor substrate such that portions of the semiconductor substrate are exposed; etching the exposed portions of the semiconductor substrate to define grooves therein, wherein the grooves comprise first grooves and second grooves, the second grooves being formed beneath the first grooves and having a width greater than that of the first grooves; forming a gate conductive layer on the hard masks and surfaces of the first and second grooves to a thickness, wherein the gate conductive layer does not fill the first and second grooves; forming a sacrificial layer on the gate conductive layer to fill the first and second grooves; removing a partial thickness of the sacrificial layer to expose the gate conductive layer, removing a portion of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the first grooves; removing the remaining sacrificial layer; and forming gates on sidewalls of the second grooves by selectively etching the gate conductive layer formed on sidewalls of lower portions of the first grooves and on bottoms of the second grooves.