Patent ID: 8829482

Claim:
A programmable impedance memory device structure, comprising: a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface throughout the memory element, and including a memory material layer in physical contact with the planar surface of the first barrier layer, the first barrier layer being formed above and in physical contact with a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface of the first barrier layer; wherein the first and second barrier layers have lower mobility rates for at least one element within the memory material layer than the first insulating layer, the memory material layer is programmable by application of an electrical field between at least two different impedance states, and the first insulating layer is formed from a different material than the first barrier layer.