Patent ID: 8583856

Claim:
A memory system, comprising: a nonvolatile memory that includes a plurality of storage areas each including a plurality of blocks, each of which is a unit of data-erase, the nonvolatile memory being configured such that parallel write is enabled with respect to the blocks included in the different storage areas; a managing unit that holds, for each of the plurality of storage areas, a plurality of free block lists, each of the free block lists indicating zero or more free blocks where valid data is not stored; an order rule holding unit that holds an order rule that is information used to determine an order of the plurality of free block lists; a position information storing unit that stores position information indicating the position of one of the plurality of free block lists in the order rule; a list selecting unit that selects a free block list from the plurality of free block lists corresponding to the position indicated by the position information; a block selecting unit that selects the free block from the free block list selected by the list selecting unit; a writing unit that writes data in the free block selected by the block selecting unit; and an updating unit that updates, after the free block list is selected by the list selecting unit, the position information stored in the position information storing unit with position information indicating the position of a subsequently selected free block list from the plurality of free block lists.