Patent ID: 8665635

Claim:
A circuit for reading a programmable memory cell, comprising: a first transistor having a source terminal connected to a ground reference potential; a second transistor having a source terminal connected to a drain terminal of the first transistor, and a gate terminal connected to a power supply voltage; a third transistor having a gate terminal connected to a drain terminal of the second transistor and a source terminal connected to a gate terminal of the first transistor; a fourth transistor having a drain terminal connected to the source terminal of the third transistor, and a source terminal being selectably connected to the programmable memory cell; a fifth transistor having a gate connected to the ground reference potential, a source terminal connected to a pumped voltage source of greater magnitude than the power supply voltage, and a drain terminal connected to a drain terminal of the third transistor; and a sixth transistor having a gate connected to the ground reference potential, a source terminal connected to the pumped voltage source, and a drain terminal connected to a drain terminal of the second transistor, wherein the fourth transistor has a gate terminal connected to a read control signal, the read control signal being driven towards a magnitude of the pumped voltage source during reading the programmable memory cell.