Patent ID: 8193049

Claim:
A method comprising: amorphizing a source/drain region of an NMOS portion of a substrate comprising an NMOS gate, wherein a PMOS portion of the substrate is not amorphized; forming a stress material on a top surface and on a sidewall region of the NMOS gate and the PMOS gate; and annealing the stress material, wherein a first dislocation is formed in a first source/drain region and a wherein a second dislocation is formed in a second source/drain region wherein a the first dislocation and the second dislocation are formed adjacent a channel region of the NMOS portion of the substrate; wherein the first and second dislocations comprise a length of between about 20 nm and about 50 nm, and wherein an angle is disposed between a top surface of the first source/drain region of the NMOS substrate and the first dislocation and wherein an angle is disposed between a top surface of the second source/drain region of the NMOS substrate and the second dislocation.