Patent ID: 8799833

Claim:
A method of generating integrated circuit (IC) designs comprising a FinFET structure layout, said method comprising: receiving, by a layout generator comprising a processor component, a planar structure layout for an IC design, the planar structure layout including a plurality of planar active areas and planar dummy areas; defining a plurality of FinFET active areas and FinFET dummy areas corresponding to the planar active areas and planar dummy areas; defining a plurality of FinFET boundaries, each FinFET boundary including one or more FinFET active areas; generating a plurality of mandrels for the plurality of FinFET active areas and FinFET dummy areas; for each FinFET boundary, generating a dummy mandrel parallel to the generated mandrels on top and/or bottom of a FinFET boundary if a space between the FinFET boundary and an adjacent feature is greater than a dummy mandrel insertion spacing; and for each FinFET boundary, extending one or both ends of the generated mandrels, each generated mandrel extension being sufficient to reduce a gap between a mandrel end and an adjacent feature to less than or equal to a minimum end-to-end space; outputting a FinFET structure layout.