Patent ID: 8310056

Claim:
A semiconductor device comprising: a substrate; a multi-layered interconnect structure formed over said substrate, and comprising a plurality of insulating interlayers, the plurality of insulating interlayers including at one insulating interlayer comprising a low-k film; and a pad formed over said multi-layered interconnect structure formed over said substrate, wherein said multi-layered interconnect structure further comprises: a lower multi-layered interconnect structure comprising: a first interconnect-level insulating interlayer which comprises a first interconnect formed in a region overlapped with said pad in a plan view; and a first via-level insulating interlayer which comprises a first via formed in the region overlapped with said pad in a plan view; an upper multi-layered interconnect structure comprising: a second interconnect-level insulating interlayer which comprises a second interconnect formed in the region overlapped with said pad in plan view; and a second via-level insulating interlayer which comprises a second via formed in the region overlapped with said pad in a plan view, the upper multi-layered interconnect structure being formed over said lower multi-layered interconnect structure; and an intermediate insulating film formed between said lower multi-layered interconnect structure and said upper multi-layered interconnect structure, wherein, in the region overlapped with said pad in a plan view, said second interconnect and said second via in said upper multi-layered interconnect structure are formed so as to be electrically connected with said pad, wherein, in said region overlapped with said pad in plan view, said intermediate insulating film comprises other than an electro-conductive material layer which connects said second interconnect or said second via in said upper multi-layered interconnect structure, with said first interconnect or said first via in said lower multi-layered interconnect structure, and wherein, in said region overlapped with said pad in plan view, a ratio of an area occupied by said first via in said first via-level insulating interlayer contained in said lower multi-layered interconnect structure, is smaller than a ratio of an area occupied by said second via in said second via-level insulating interlayer contained in said upper multi-layered interconnect structure.