Patent ID: 7408221

Claim:
A memory device, comprising: a substrate comprising a memory cell area and a peripheral circuit area, wherein the peripheral circuit area comprises a high operational voltage component area and a low operational voltage component area; at least a memory cell, disposed in the memory cell area, wherein each of the memory cell comprises: an inter-gate dielectric layer and a tunnel layer, disposed over a surface of the substrate of the memory cell area respectively; a doped region, disposed in the substrate under the inter-gate dielectric layer, and used as a control gate; a floating gate, disposed over the tunnel layer and the inter-gate dielectric layer; and a first source region and a first drain region, disposed in the substrate of two sides of the floating gate under the tunnel layer; at least a high operational voltage component, disposed in the high operational voltage component area, wherein each of the high operational voltage component comprises: a first inter-gate dielectric layer, disposed over a surface of the substrate of the high operational voltage component area; a first gate, disposed over the first inter-gate dielectric layer; and a second source region and a second drain region, disposed in the substrate of two sides of the first gate; and at least a low operational voltage component, disposed in the low operational voltage component area, wherein each of the low operational voltage component comprises; a second inter-gate dielectric layer, disposed over a surface of the substrate of the low operational voltage component area; a second gate, disposed over the second inter-gate dielectric layer; and a third source region and a third drain region, disposed in the substrate of two sides of the second gate.