Patent ID: 7378311

Claim:
A method of forming memory cells in an array including: forming a first memory cell relative to a substrate, the first memory cell including a first access transistor and a first data storage element, a first load electrode of the first access transistor being coupled to the first data storage element via a first storage node; forming a second memory cell relative to the substrate, the second memory cell including a second access transistor and a second data storage element, a first load electrode of the second access transistor being coupled to the second data storage element via a second storage node formed on the substrate, wherein forming the first and second memory cells includes forming the first and second access transistors to have a first threshold voltage; and forming an isolation gate extending above the substrate, between the first and second storage nodes and configured to provide electrical isolation therebetween, wherein forming the isolation gate includes forming the isolation gate to have a second threshold voltage greater than the first threshold voltage, wherein forming the first and second memory cells comprises forming first and second DRAM memory cells.