Patent ID: 8450858

Claim:
A semiconductor device comprising: an underlying insulating film formed on a semiconductor substrate; a first wiring layer formed on a portion of the underlying insulating film; a first interlayer insulating film formed on the underlying insulating film and the first wiring layer; a second interlayer insulating film formed on concavities in the first interlayer insulating film by spin-coating and an etch-back process; a third interlayer insulating film formed on the first interlayer insulating film and the second interlayer insulating film; and a second wiring layer formed on the third interlayer insulating film, wherein the first wiring layer and the second wiring layer have widths of 10.0 μm or greater, and wherein an overlap portion where the first wiring layer and the second wiring layer overlap has an overlap width of 1.0 μm or greater, and wherein the second wiring layer is disposed relative to the first wiring layer such that when a stress in a direction in which the first wiring layer and the second wiring layer pull away horizontally from each other is generated during manufacturing of the device, or while the device is in use, the first interlayer insulating film, the second interlayer insulating film and the third interlayer insulating film remain intact.