Patent ID: 8410997

Claim:
A plasma display panel driving circuit, comprising: a logic controller configured to generate a plurality of scan driver reset control reference signals; a buffer block configured to receive the scan driver reset control reference signals and to generate at least three reset control signals based on the scan driver reset control reference signals, wherein each of the reset control signals has a selected one of at least three different selectable delay times; and a scan driver configured to drive a plurality of scan lines with reset driving signals, wherein the scan lines are divided into at least three groups, wherein the reset driving signals for each of the groups is based on one of the three reset control signals, and wherein the reset driving signals of each of the groups comprises: a voltage ramp starting at a start voltage and ending at an end voltage, wherein the start and end voltages for each of the groups is substantially the same, and wherein the voltage ramp of each of the groups occurs at substantially the same time, a voltage transition to the start voltage, which occurs at a time based on the selected delay times of the reset control signals, and a voltage transition from the end voltage, which occurs at a time based on the selected delay times of the reset control signals.