Patent ID: 8050904

Claim:
A computer-implemented method of performing time-based symbolic simulation, the method comprising: creating a delay-aware representation of a circuit, wherein the delay-aware representation includes a plurality of circuit nodes; simulating a first plurality of transitions from a first set of circuit nodes selected from the plurality of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events; generating a second set of simulation events in response to executing the first set of simulation events, wherein the second set of simulation events are generated based on the execution of the first set of simulation events; simulating a second plurality of transitions from the second set of circuit nodes to a third set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing the second set of simulation events; computing a plurality of times corresponding to the first and the second plurality of transitions; and constructing an event scheduling diagram that depicts the first and second plurality of transitions and the computed times corresponding to the first and second plurality of transitions.