Patent ID: 7999596

Claim:
An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I 2 C) bus, the apparatus comprising: a serial data (SDA) filter that is adapted to receive an SDA signal from the I 2 C bus, wherein the SDA filter includes a hold terminal and a disable terminal, and wherein the hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected, wherein the SDA filter includes: a first flip-flop that is adapted to receive the SDA signal; a second flip-flop that is coupled to an output of the first flip-flop; a third flip-flop that is coupled to an output the second flip-flop; an XOR gate that is coupled to the output of the second flip-flop and to an output of the third flip-flop, wherein the XOR gate issues the disable signal when the transient in the SDA signal is detected a first multiplexer having a plurality of input terminals, a plurality of select terminals, and an output terminal, wherein at least one of the select terminals of the first multiplexer is coupled to the output of the second flip-flop, and wherein at least one of the select terminals of the first multiplexer is coupled to the output of the third flip-flop; a second multiplexer having a plurality of input terminals, a select terminal, and an output terminal, wherein at least one of the input terminals of the second multiplexer is coupled to the output terminal of the first multiplexer, and wherein the select terminal of the second multiplexer is coupled to the hold terminal of the SDA filter; and a fourth flip-flop that is adapted to receive a signal from output terminal of the second multiplexer; a serial clock (SCL) filter that is adapted to receive an SCL signal from the I 2 C bus, wherein the SCL filter includes a hold terminal and a disable terminal, and wherein the hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected, and wherein the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and wherein the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter; I 2 C interface logic that is coupled to the SDA filter and to the SCL filter; and operational circuitry that is coupled the I 2 C interface logic.