Patent ID: 8837200

Claim:
A nonvolatile semiconductor memory device comprising: word lines formed in parallel in a first plane; bit lines formed in parallel in a second plane and three-dimensionally crossing the word lines, the second plane being parallel to the first plane; and a cross-point cell array including cells each provided at a corresponding one of three-dimensional cross-points of the word lines and the bit lines, wherein the cells include: a memory cell including a memory element that operates as a memory by reversibly changing in resistance value between at least two states based on an electrical signal applied between a corresponding one of the word lines and a corresponding one of the bit lines; and an offset detection cell having a resistance value that is, irrespective of an electrical signal applied between a corresponding one of the word lines and a corresponding one of the bit lines, higher than the resistance value of the memory element in a high resistance state which is a state of the memory element when operating as the memory.