Patent ID: 8502312

Claim:
A semiconductor power device comprising: a semiconductor substrate including a plurality of deep trenches and a plurality of semiconductor regions between the deep trenches having a width significantly wider than a width of the deep trenches; an epitaxial layer filling said deep trenches, the epitaxial layer further including a simultaneously grown overflow over trench top epitaxial layer covering an entire top surface of said semiconductor substrate over said deep trenches, wherein the epitaxial layer is of an opposite conductivity type as the semiconductor regions between the deep trenches; and a plurality of trench MOSFET cells each having a trenched gate opened from said top epitaxial layer and extends into the semiconductor regions between said deep trenches with the top epitaxial layer functioning as the body region encompassing doped regions having a functioning as source regions wherein a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and the semiconductor regions between and adjacent to the deep trenches for conducting a current between the source region and the drain region, with a breakdown voltage of said MOSFET cells based on a controlled thickness of said overflow over trench top epitaxial layer; wherein each of said plurality of trench MOSFET cells includes a trench DMOS transistor cell having gate sidewall dopant regions surrounding sidewalls of the trenched gate and a gate-bottom dopant region below the trenched gate, wherein the gate sidewall dopant regions and gate-bottom dopant regions are of an opposite conductivity type of the epitaxial layer filled in the deep trenches.