Patent ID: 6894534

Claim:
A dynamic programmable logic array (DPLA) comprising: at least one logic plane; and at least one reprogrammable evaluate module within the at least one logic plane, the at least one reprogrammable evaluate module including a first program input, a second program input, a storage element coupled to the first and second program inputs, an input pass transistor coupled to the output of storage element and an evaluate transistor coupled to the input pass transistor, wherein the storage element comprises at least one of SRAM cell, FLASH memory cell, fuse, anti-fuse, ferroelectric memory cell, EEPROM cell and EPROM cell, wherein the at least one programmable evaluate module includes the first program input, the second program input, and the storage element coupled to the first and second program inputs, and the input pass transistor, the input pass transistor including a gate, source and drain, wherein the gate is coupled to the output of the storage element and the source and the drain are coupled to a control input and a gate of the evaluate transistor and in which the control input and one of the first and second program inputs are combined into one signal.