Patent ID: 7304898

Claim:
A semiconductor memory device, comprising: an align control signal generation unit for generating a plurality of align control signals sequentially activated by dividing a data strobe signal only when a data input/output is performed; and a data align unit for outputting a plurality of data which are sequentially inputted as a plurality of align data, at the same time in response to the plurality of align control signals, wherein the align control signal generation unit includes: a dividing unit for dividing the data strobe signal by 2 in response to an activation of a write flag signal; and an output unit for generating a plurality of align control signals by synchronizing a main output and a sub output of the dividing unit with the data strobe signal, said plurality of align control signals including first to fourth align control signals which are activated in synchronization with a rising edge and a falling edge of the data strobe signal inputted after an activation of the write flag signal.