Patent ID: 8493120

Claim:
Storage circuitry comprising: a first storage block configured, in at least one mode of operation, to store data to perform a first function; a second storage block configured, in at least one mode of operation, to store said data to perform a second function distinct from said first function; and configuration circuitry, responsive to a predetermined mode of operation where said second function is unused, to re-configure said second storage block to store said data in parallel with said first storage block data to increase resilience of said first storage block to single event upsets (SEUs) whilst performing said first function during said predetermined mode of operation, wherein: one of said at least one modes of operation is a normal mode of operation; said first storage block is configured to perform said first function by operating as a master latch of a flip-flop during said normal mode of operation, and said second storage block is configured to perform said second function by operating as a slave latch of said flip-flop during said normal mode of operation; said predetermined mode of operation is a standby mode of operation where said first storage block performs said first function to retain a data value, and said second function is unused.