Patent ID: 8453075

Claim:
A method of modifying lithographic hot spots in a chip design layout comprising: generating a set of reference feature key points by performing, employing at least one computing means, a first scale invariant feature transformation (SIFT) on a reference pattern including a lithographic hot spot located in a first chip design layout; generating a set of target feature key points by performing, employing said at least one computing means, a second SIFT on a target pattern located in a second chip design layout; matching said set of reference feature key points with said set of target feature key points by identifying, employing said at least one computing means, pairs of feature key points across said set of reference feature key points and said set of target feature key points, wherein each of said pairs are selected to provide maximum matching between topological features of said set of reference feature key points and topological features of said set of target feature key points; and storing data representing a result of said matching in a non-transitory machine readable data storage medium employing said at least one computing means, wherein said stored data represents presence of at least one lithographic hot spot in said target pattern; modifying said stored data to enhance printability of said chip design layout employing said at least one computing means.