Patent ID: 8497576

Claim:
A device comprising a first semiconductor chip and a second semiconductor chip; the first semiconductor chip comprising: a first outer peripheral region and a first inner region surrounded by the first outer peripheral region; a plurality of first through-electrodes each formed in the first inner region and each penetrating the first semiconductor chip; a plurality of first electrode pads each provided on an associated one of the first through-electrodes on a first main surface side of the first semiconductor chip; a plurality of second electrode pads each provided on an associated one of the first through-electrodes on a second main surface side of the first semiconductor chip; a plurality of first reinforcement bumps each provided in the first outer peripheral region on the first main surface side of the first semiconductor chip; a plurality of second reinforcement bumps each provided in the first outer peripheral region on the second main surface side of the first semiconductor chip; and the second semiconductor chip comprising: a second outer peripheral region and a second inner region surrounded by the second outer peripheral region; a plurality of third electrode pads each formed in the second inner region on a first main surface side of the second semiconductor chip; and a plurality of third reinforcement bumps each provided in the second outer peripheral region on the first main surface side of the second semiconductor chip; the second semiconductor chip being stacked over the first semiconductor chip such that each of the third electrode pads of the second semiconductor chip is connected to an associated one of the second electrode pads of the first semiconductor chip and each of the third reinforcement bumps of the second semiconductor chip is connected to an associated one of the second reinforcement bumps of the first semiconductor chip; and the first reinforcement bumps being arranged substantially in line on the first main surface side of the first semiconductor chip, the second reinforcement bumps being arranged substantially in line on the second main surface side of the first semiconductor chip, and the third reinforcement bumps being arranged substantially in line on the first main surface side of the second semiconductor chip.