Patent ID: 8003453

Claim:
A method of fabricating a semiconductor structure comprising: providing at least one patterned gate stack on one portion of a layer of at least one one-dimensional nanostructure, said at least one patterned gate stack including, from bottom to top, a gate dielectric and a gate electrode, wherein said gate dielectric and said gate electrode have outer edges that are aligned to each other and said layer of at least one one-dimensional nanostructure is located directly on an upper surface of a dielectric layer which is located on an upper surface of a semiconductor layer; forming at least one spacer on a surface of said layer of at least one one-dimensional nanostructure, wherein an inner edge of said at least one spacer is laterally abutting both a sidewall of both said gate electrode and a sidewall of said gate dielectric; forming a source/drain metal on other portions of said layer of at least one one-dimensional nanostructure and around said at least one patterned gate stack, said other portions of said layer of at least one one-dimensional nanostructure are laterally adjacent to said one portion of said layer of at least one one-dimensional nanostructure; and forming a metal carbide by reacting said source/drain metal with said other portions of said layer of at least one one-dimensional nanostructure, wherein said metal carbide contact is aligned to and laterally abuts, but does not overlap, both a sidewall edge of said layer of at least one one-dimensional nanostructure and a sidewall edge of said at least one spacer.