Patent ID: 7657855

Claim:
A processor-implemented method for processing an electronic circuit design, the design represented by a netlist and a corresponding primary timing graph identifying a plurality of input and output pins and a plurality of resource blocks and a plurality of connections between the plurality of input and output pins, comprising: executing program code by a processor, the code causing the processor to perform operations including: selecting a subset timing graph from the primary timing graph in a memory; generating one or more alternative subset timing graphs that are functionally equivalent and structurally different with respect to the selected subset timing graph; for each of the one or more alternative timing graphs, determining a respective timing metric; comparing each determined timing metric and a timing metric for the selected subset timing graph; selecting one of the one or more alternative timing graphs in response to the comparison; verifying structurally different portions of the selected one of the one or more alternative timing graphs against design constraints; and storing the structurally different portions to the primary timing graph in the memory.