Patent ID: 8418105

Claim:
A method for fabricating an integrated circuit comprising: providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a plurality of non-double patterning technology compliant patterns of the plurality of patterns; applying a computerized electronic design automation (EDA) decomposition tool to the plurality of non-double patterning technology compliant patterns, wherein after application of the EDA decomposition tool, a first subset of the plurality of non-double patterning technology compliant patterns are decomposed and a second subset of the plurality of non-double patterning technology compliant patterns are not decomposed; identifying the coordinate points of each pattern of the second subset of the plurality of non-double patterning technology compliant patterns that were not decomposed; using a computing system, automatically comparing the coordinate points of each pattern of the second subset against an electronic library of decomposed, double patterning technology compliant patterns, wherein the electronic library comprises a plurality of decomposed, double patterning technology compliant patterns that correspond to non-decomposed patterns that are not able to be decomposed automatically using the EDA decomposition tool; based on the comparison, using the computing system, automatically providing a double patterning technology compliant pattern for replacing each of the identified non-double patterning technology compliant patterns of the second subset, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.