Patent ID: 7224560

Claim:
A circuit for protecting an Integrated Circuit (IC) against an ElectroStatic Discharge (ESD) transient, the circuit comprising: a master circuit responsive to an ESD voltage V(t) and having an output; and a slave circuit comprising multiple parallel shunt devices having a common input coupled to the output of the master circuit; wherein as V(t) increases the master circuit applies a portion of V(t) to the input of the multiple parallel shunt devices thereby lowering a threshold voltage Vt 1 at which the multiple parallel shunt devices would otherwise turn on, to a smaller value Vt 1 ′ much closer to a holding voltage Vh of the multiple parallel shunt devices; wherein when V(t) reaches VT 1 ′, all of the multiple parallel shunt devices turn on substantially simultaneously, thereby shunting the ESD transient harmlessly to ground, wherein the master circuit comprises a transient voltage divider having a first resistor R 1 , a capacitor C 1 and a second resistor R 2 series coupled between V(t) and ground, and an active device having a control terminal T 1 and power terminals T 2 , T 3 , wherein T 1 is coupled to a first terminal of C 1 , a second terminal of C 1 is coupled through R 1 to V(t), T 1 is coupled to a first terminal of R 2 , a second terminal of R 2 is coupled to ground, T 2 is coupled to the second terminal of C 1 and through R 1 to V(t), and T 3 is coupled through a third resistor R 3 to ground, wherein the output of the master circuit is derived from T 3 .