Patent ID: 7944262

Claim:
A duty correction circuit comprising: a first inverter including a first transistor, and second and third transistors having a conduction type which is different from a conduction type of the first transistor, wherein the first transistor whose gate receives an input clock signal is connected between a first voltage and a first output terminal, the second transistor whose gate receives the input clock signal is connected to a second voltage, and the third transistor is connected in series to the first transistor in connection with the first output terminal; a second inverter including a fourth transistor, and fifth and sixth transistors having a conduction type which is different from a conduction type of the fourth transistor, wherein the fourth transistor whose gate is connected to the first output terminal is connected between the first voltage and a second output terminal, the fifth transistor whose gate is connected to the first output terminal is connected to the second voltage, and the sixth transistor is connected in series to the fourth transistor in connection with the second output terminal; and a bias circuit that supplies a first bias voltage to a gate of the third transistor and that supplies a second bias voltage to a gate of the sixth transistor, wherein the input clock signal is delayed by the first inverter and the second inverter in turn and is converted into an output clock signal, whose duty ratio is corrected based on the first bias voltage or the second bias voltage and which is output from the second output terminal.