Patent ID: 6984861

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a transistor formed on the semiconductor substrate, and having a gate electrode and first and second diffusion layers; a first insulating film formed on the transistor; a first multi-layer interconnect layer formed in the first insulating film, and including a plurality of interconnect layers and contacts; a first recessed portion formed to continuously and vertically penetrate the first insulating film including at least two layers of the first multi-layer interconnect layer, and arranged so that at least part of the first recessed portion overlaps with the gate electrode; and a ferroelectric capacitor three-dimensionally formed in the first recessed portion, and having first and second electrodes and a ferroelectric film, the first electrode being electrically connected with the first diffusion layer, the ferroelectric capacitor comprising a first portion which is formed at a bottom of the first recessed portion and is extended horizontal to the semiconductor substrate, and a second portion which is formed on a side wall of the first recessed portion and is extended vertical to the semiconductor substrate.