Patent ID: 8727508

Claim:
A print head jet stack comprising a plurality of transducers, wherein the print head jet stack comprises: a semiconductor substrate body plate; a diaphragm overlying the semiconductor substrate body plate; a patterned piezoelectric layer overlying the diaphragm; a first patterned conductive layer overlying the patterned piezoelectric layer, wherein the diaphragm comprises a conductive bottom electrode of the plurality of transducers, the patterned piezoelectric layer comprises a plurality of piezoelectric elements for the plurality of transducers, wherein each piezoelectric element is separated from an adjacent piezoelectric element by a space, and the first patterned conductive layer comprises a plurality of top electrodes for the plurality of transducers; a dielectric interstitial layer interposed directly between adjacent transducers of the plurality of transducers, wherein the dielectric interstitial layer physically contacts the diaphragm and the patterned piezoelectric layer, fills the space between each adjacent piezoelectric element from the diaphragm to an upper surface of the first patterned conductive layer, comprises a planar upper surface, and overlies a portion of the first patterned conductive layer; a second patterned conductive layer that physically contacts the planar upper surface of the dielectric interstitial layer, wherein a portion of the dielectric interstitial layer is directly interposed between the first patterned conductive layer and the second patterned conductive layer in a direction perpendicular to the diaphragm, the second patterned conductive layer comprising: a plurality of first pads that overlie and physically and electrically contact the plurality of top electrodes, and physically contact the planar upper surface of the interstitial dielectric layer; a plurality of traces electrically coupled to the plurality of first pads that physically contact the planar upper surface of the interstitial dielectric layer; a plurality of second pads electrically coupled to the plurality of traces and to the plurality of first pads, wherein the plurality of second pads are each laterally located with respect to the patterned piezoelectric layer; and an application specific integrated circuit (ASIC) electrically coupled to each of the plurality of second pads.