Patent ID: 7663233

Claim:
A pad part of a semiconductor device, comprising: a semiconductor substrate having a pad forming region; a plurality of dot type stack patterns of a dielectric layer and a conductive layer for option capacitors, formed in the pad forming region of the semiconductor substrate, and arranged at regular intervals; a first interlayer dielectric formed on the semiconductor substrate to cover the stack patterns; first metal lines formed on the first interlayer dielectric in the pad forming region to be connected to the stack patterns, which are arranged in diagonal directions; a second interlayer dielectric formed on the first interlayer dielectric to cover the first metal lines; second metal lines formed on the second interlayer dielectric to be brought into contact with the first metal lines; a pad formed on the second interlayer dielectric to be separated from the second metal lines; and option metal lines formed on the second interlayer dielectric to connect the second metal lines and the pad to each other.