Patent ID: 7849441

Claim:
A method for specifying stateful, transaction-oriented systems for configuring one of a programmable hardware array or programmable processor array through a FlowLogic language, comprising method operations of: designating a plurality of primitive FlowModules; defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interuptable sequence of procedure code, a single point of entry and is invoked by a named concurrent call; encapsulating one of the primitive FlowModules or a HierarchicalFlowModule into another HierarchicalFlowModule, wherein the another HierarchicalFlowModule includes input ports for every intersected incoming arc and output ports for every intersected outgoing arc; designating an Arc from a calling FlowGate to a called FlowGate, the designating including designating an Arc pair as a CallForwardArc and a ForwardArc, wherein the ForwardArc does not have an explicit destination FlowGate name on invocation, and the CallForwardArc explicitly specifies the destination FlowGate of the resulting ForwardArc; generating a Signal for each named invocation of the called FlowGate; defining a Channel for carrying the Signal; and compiling the HierarchicalFlowModule for configuring one of the programmable hardware array or the programmable processor array.