Patent ID: 8018259

Claim:
A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO), and wherein the PLL is configured to receive a reference signal and a feedback signal, the method comprising: operating the PLL in a training mode, wherein operating the PLL in the training mode comprises: setting a control voltage of the VCO at a first voltage level, increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected, and storing an indicator value corresponding to the second voltage level of the control voltage of the VCO; and after operating the PLL in the training mode, operating the PLL in a normal mode, wherein operating the PLL in the normal mode comprises: monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO, and asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value.