Patent ID: 8354704

Claim:
A flash memory device comprising: a semiconductor substrate including a surface region; a gate dielectric layer overlying the surface region; a floating gate layer having a floating gate layer thickness and including a first floating gate structure overlying a first portion of the gate dielectric layer and a second floating gate structure overlying a second portion of the gate dielectric layer; a trench region provided between the first floating gate structure and the second floating gate structure and extending through an entirety of the floating gate layer thickness, the trench region extending through a portion of the surface region into a depth of the semiconductor substrate; a dielectric material filling an entirety of the depth of the trench region in the semiconductor substrate and filling a portion of the trench region between the first floating gate structure and the second floating gate structure; an oxide on nitride on oxide layer overlying the first floating gate structure, the dielectric material, and the second floating gate structure; and a control gate overlying the oxide on nitride on oxide layer; wherein the gate dielectric layer comprises a first thickness and a second thickness.