Patent ID: 8106447

Claim:
A semiconductor device, comprising: a first semiconductor region of a first conductivity type disposed at a side of a first electrode; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity type alternately provided along a surface on a side of a second electrode disposed on a side opposite said first electrode; a third semiconductor region of the second conductivity type formed on a surface portion on a side of said second electrode of said second semiconductor region; a fourth semiconductor region of the first conductivity type formed on a part of a surface of said third semiconductor region so as to be connected to said second electrode; and control electrodes each provided within a trench and being separated by an insulating film, a sidewall of said trench being formed so as to contact each of said third semiconductor region and said fourth semiconductor region, wherein said second pillar regions are formed by filling a semiconductor of the second conductivity type in each of said trenches formed in said second semiconductor region through epitaxial growth, and are arranged in a stripe pattern in a common direction in an element portion having said third semiconductor region and said fourth semiconductor region disposed therein, said first pillar regions are formed as regions each located between two second pillar regions, and said control electrodes are arranged in stripe shapes so as to intersect at approximately an angle of 45° with a longitudinal direction of the stripes of said second pillar regions.