Patent ID: 8116418

Claim:
A clock data recovery system comprising: a phase detector configured to receive an incoming data stream and an interpolated clock signal and output an early/late value indicating whether the incoming data stream is early or late relative to the interpolated clock signal; a phase interpolator configured to receive the early/late signal and at least one reference clock signal and generate an interpolated clock signal considering the early/late value and the at least one reference clock signal; an initial phase detector configured to receive the incoming data stream and output first data indicating a phase of the incoming data stream; an initial phase decoder configured to receive data indicating a phase of the incoming data stream and select the at least one reference clock signal from a plurality of clock signals considering the data indicating a phase of the incoming data stream, the initial phase decoder being further configured to derive an estimation of the phase of the incoming data stream and select the at least one reference clock signal considering the estimation, wherein the data indicating the phase of the incoming data stream comprises the first data; and wherein the initial phase detector and the initial phase decoder are configured to deactivate after the at least one reference clock signal is selected, wherein the plurality of clock signals comprises a Clock Q signal with a phase angle of π/2, a Clock IB signal with a phase angle of π, a Clock QB signal with a phase angle of 3π/2, and a Clock I with a phase angle of 2π, and wherein the estimation of the phase of the incoming data stream comprises a quadrant, and wherein the at least one reference clock signal comprises two clock signals bounding the quadrant.