Patent ID: 7519938

Claim:
A processor-based method for generating an implementation of an electronic design, comprising: specifying in a memory coupled to a processor, information describing a set of strategies, each strategy of the set including at least one option for directing generation of an implementation of the electronic design, and each option being a set of one or more input parameter values to an implementation tool; displaying the set of strategies; selecting a subset of the set of strategies in response to user input; for each strategy of the subset, generating a respective implementation of the electronic design from a specification of the electronic design in a hardware description language, wherein the generating of the respective implementation of the electronic design for the strategy is directed by the at least one option of the strategy input to at least one implementation tool wherein the generating of the respective implementation of the electronic design for each strategy of the subset includes: mapping the specification of the electronic design to a plurality of instances of a plurality of primitives of an electronic device, placing the instances of the primitives in respective locations in the device, and routing connections between the respective locations in the device; wherein each option of each strategy of the set is an option for the mapping, the placing, and the routing; and for each strategy of the subset, displaying a plurality of quality metrics of the respective implementation of the electronic design.