Patent ID: 7157324

Claim:
A method, comprising: providing a substrate; depositing a first layer on the substrate; depositing a second layer on the first layer; forming a process stack that includes the first layer, the second layer and a portion of the substrate; forming a trench wall in the substrate; forming an implant region, without the use of spacers covering the implant region, by pulling back the first and second layers a pull back distance from the trench wall, wherein forming the implant region includes forming a rounded corner between the portion of the substrate and the trench wall; and reducing transistor leakage for a subsequently fabricated transistor, including doping the implant region using the same dopant type as the substrate type to raise a threshold voltage of the implant region to be approximately equal to or greater than the threshold voltage on the portion of the substrate and whereby the pull back distance defines a width of the implant region which is approximately uniform around the process stack.