Patent ID: 8710881

Claim:
A PLL circuit which receives an input of a reference pulse, and outputs an output pulse, comprising: a voltage controlled oscillator that outputs the output pulse having a frequency according to an input voltage; a loop filter that feeds a voltage according to an input current to the voltage controlled oscillator; a phase comparator that outputs a phase difference pulse having a width according to a phase difference between a first input signal and a second input signal; a charge pump circuit that receives the phase difference pulse, and inputs the current to the loop filter; and a phase-difference-pulse stop unit that stops the input of the phase difference pulse to the charge pump circuit in a non-input state in which the reference pulse is not input, wherein: the first input signal is a signal based on the reference pulse; and the second input signal is a signal based on the output pulse, wherein the phase-difference-pulse stop unit stops the output of the phase difference pulse from the phase comparator in the non-input state, and wherein the phase-difference-pulse stop unit includes a non-input-state detector that detects the non-input state in which the first input signal is not input, and receives a detection of the non-input state by the non-input-state detector, thereby stopping the output of the phase difference pulse from the phase comparator.