Patent ID: 8384174

Claim:
A chip package, comprising: a substrate having a first surface and a second surface of the substrate; an optical device disposed on the first surface of the substrate; a conducting layer located on the second surface of the substrate and electrically connected to the optical device; a passivation layer disposed on the second surface of the substrate and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump disposed on the second surface of the substrate, wherein the conducting bump has a bottom portion and an upper portion, and the bottom portion of the conducting bump is disposed in the opening and electrically contacts the exposed conducting layer, and the upper portion of the conducting bump is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer disposed on the second surface of the substrate, extending under the upper portion of the conducting bump, and partially located in the recess and overlapping a portion of the conducting bump.