Patent ID: 6907438

Claim:
A method of performing a two-dimensional inverse discrete cosine transform (IDCT) using a microprocessor having an instruction set that includes single-instruction multiple-data (SIMD) floating-point instructions, wherein the method comprises: receiving a two-dimensional block of integer data having C columns and R rows, wherein each of the R rows contains a set of C row data values, wherein the block of integer data is indicative of a portion of an image, wherein each of C and R is an even integer; and for each row, loading the entire set of C row data values of the row into a set of C/2 registers of the microprocessor; converting the C row data values into floating-point form, wherein each of the registers holds two of the floating-point row data values; and performing a plurality of weighted-rotation operations on the values in the registers, wherein the weighted-rotation operations are performed using SIMD floating-point instructions; altering the arrangement of values in the registers; performing a weighted-rotation operation and a plurality of sum and difference pair calculations on the values in the registers; again altering the arrangement of the values in the registers; performing a second plurality of sum and difference pair calculations on the values in the registers; yet again altering the arrangement of the values in the registers; and performing a fourth plurality of sum and difference pair calculations on the values in the registers to obtain C intermediate floating-point values; and storing the C intermediate floating-point values to a next available row of an intermediate buffer; for two columns of the intermediate buffer at a time, loading data from said two columns into a plurality of registers of the microprocessor so that each of the registers holds one value from a first of the two columns and one value from a second of the two columns, wherein the one value from the first of the two columns and the one value from the second of the two columns are taken from the same row of the intermediate buffer; and performing a plurality of weighted-rotation operations on the values in the registers, wherein the weighted-rotation operations for said two columns are independently performed using interleaved SIMD floating-point instructions.