Patent ID: 8153494

Claim:
A method of forming a semiconductor structure comprising: forming a gate dielectric over a conductive substrate; forming undoped semiconductor nanowires over said gate dielectric; depositing a dielectric stack comprising, from bottom to top, an oxide and a nitride over said undoped semiconductor nanowires; forming a first contact hole in said dielectric stack to expose a first region of each of said undoped semiconductor nanowires and forming a second contact hole in said dielectric stack and in contact with a second region of each of said undoped semiconductor nanowires; forming a first doped semiconductor material in said first contact hole and in contact with said first region of said undoped semiconductor nanowires and forming a second doped semiconductor material in said second contact hole and in contact with said second region of said undoped semiconductor nanowires, wherein said first doped semiconductor material serves as a source region, and the second doped semiconductor serves as a drain region; and forming a first metal semiconductor alloy atop the first doped semiconductor material and forming a second metal semiconductor alloy atop the second doped semiconductor material.