Patent ID: 7554417

Claim:
An impedance adjusting circuit comprising: a semiconductor device accommodated in a semiconductor device case which has case pins and having a folded conductive line; an external reference resistor connected between a positive power supply line and a first one of said case pins, wherein a first line between said first case pin and said semiconductor device has a specific resistance; a first reference voltage generation resistor connected between said power supply line and a second one of said case pins; a second reference voltage generation resistor connected between the ground and a third one of said case pins; a resistance circuit comprising a second line between said second case pin and said folded conductive line and a third line between said third case pin and said folded conductive line, wherein a resistance between said second case pin and said third case pin is equal to the specific resistance; and a fourth line connected from said semiconductor device to the ground through said second reference voltage generation resistor and having a resistance equal to the specific resistance, wherein said semiconductor device comprises: an adjusting circuit having a buffer and configured to adjust an output impedance of said buffer to be adaptive for a predetermined impedance.