Patent ID: 6969893

Claim:
A semiconductor device comprising: a semiconductor substrate; a first-conductive-type first-deepest well region formed in the semiconductor substrate; a first-conductive-type second-deepest well region formed on the first-conductive-type first-deepest well region; a second-conductive-type shallow well region formed on the first-conductive-type second-deepest well region; a first-conductive-type dynamic threshold transistor which is formed on the second-conductive-type shallow well region and in which a gate electrode and the second-conductive-type shallow well region are electrically connected to each other; a second-conductive-type second-deepest well region formed on the first-conductive-type first-deepest well region; a second-conductive-type shallow well region formed on the second-conductive-type second-deepest well region; a first-conductive-type field effect transistor formed on the second-conductive-type shallow well region; an input terminal which is formed on the second-conductive-type shallow well region and which serves for changing a substrate bias of the first-conductive-type field effect transistor; a second-conductive-type first-deepest well region formed in the semiconductor substrate; a second-conductive-type second-deepest well region formed on the second-conductive-type first-deepest well region; a first-conductive-type shallow well region formed on the second-conductive-type second-deepest well region; a second-conductive-type dynamic threshold transistor which is formed on the first-conductive-type shallow well region and in which a gate electrode and the first-conductive-type shallow well region are electrically connected to each other; a first-conductive-type second-deepest well region formed on the second-conductive-type first-deepest well region; a first-conductive-type shallow well region formed on the first-conductive-type second-deepest well region; a second-conductive-type field effect transistor formed on the first-conductive-type shallow well region; an input terminal which is formed on the first-conductive-type shallow well region and which serves for changing a substrate bias of the second-conductive-type field effect transistor; device isolation regions which are deeper than a depth of a junction between the first-conductive-type second-deepest well region and the second-conductive-type shallow well region and which are shallower than a depth of a junction between the first-conductive-type first-deepest well region and the second-conductive-type second-deepest well region; and device isolation regions which are deeper than a depth of a junction between the second-conductive-type second-deepest well region and the first-conductive-type shallow well region and which are shallower than a depth of a junction between the second-conductive-type first-deepest well region and the first-conductive-type second-deepest well region.