Patent ID: 7527985

Claim:
A method for manufacturing a memory device, comprising: forming a first dielectric layer, a conductive layer overlying the first dielectric layer, and a second dielectric layer overlying the conductive layer; patterning the second dielectric layer and the conductive layer having first edges that align substantially near the center of the top surface of a contact plug, the second dielectric layer and the conductive layer having first sidewalls; forming a first electrode that extends vertically having a first sidewall surface and a second sidewall surface, the first sidewall surface of the first electrode in contact with the first sidewalls of the second dielectric layer and the conductive layer; forming a sidewall insulating member having a first sidewall surface and a second sidewall surface, the first sidewall surface of the sidewall insulating member in contact with the second sidewall surface of the first electrode; forming a second electrode that extends vertically having a sidewall surface in contact with the second sidewall surface of the sidewall insulating member, the second electrode formed by depositing an electrode layer overlying the top surface of the sidewall insulating member and the second sidewall of the sidewall insulating member and isotropically etching the electrode layer to form the second electrode; and forming a bridge of memory material between the first electrode and the second electrode across the top surface of the sidewall insulating member, the bridge comprising a patch of memory material contacting the top surface of the first electrode and the top surface of the second electrode to define an inter-electrode path between the first electrode and second electrode having a path length defined by a thickness of the insulating sidewall member.