Patent ID: 6839261

Claim:
A semiconductor memory device comprising: a plurality of memory banks each including a memory cell array and a control circuit for the memory cell array; and an interface circuit shared by the plural memory banks; the semiconductor memory device being adapted for performing reading of data from the plural memory banks and rewriting of data to the plural memory banks, wherein in an operation mode for performing the reading, the following processing is performed: processing A 1 in which the interface circuit outputs an active read enable signal to the plural memory banks; processing A 2 in which the interface circuit outputs address information specifying a memory cell as a reading target to the plural memory banks; processing A 3 in which each of the plural memory banks reads out data of the memory cell specified by the inputted address information and outputs the read-out data as an output data group to the interface circuit; and processing A 4 in which the interface circuit selectively outputs one of plural output data groups outputted from the plural memory banks, to outside, and in an operation mode for performing the rewriting, the following processing is performed: processing B 1 in which the interface circuit outputs address information specifying a memory cell as a rewriting target to the plural memory banks; processing B 2 in which the interface circuit outputs an input data group from outside to the plural memory banks; processing B 3 in which the interface circuit selectively outputs an active write enable signal to one of the plural memory banks; and processing B 4 in which a memory bank to which an active write enable signal is inputted, of the plural memory banks, rewrites data of the memory cell specified by the address information to data of the input data group.