Patent ID: 7358134

Claim:
A fabrication method for a split gate flash memory cell, comprising: providing a substrate, wherein the substrate is already formed with a device isolation structure; forming a selective gate structure on the substrate, the selective gate structure comprises a gate dielectric layer, a conductive layer and a cap layer; forming a spacer on a sidewall of the selective gate structure; forming a source region and a drain region in the substrate beside both sides of the selective gate structure, wherein the source region is at a certain distance away from the selective gate structure, and the drain region is adjacent to the selective gate structure; forming an interlayer dielectric layer on the substrate; forming an opening in the interlayer dielectric layer, wherein the opening exposes the substrate between the selective gate structure and the source region, a portion of the selective gate structure and the device isolation structure; forming a tunneling dielectric layer on the substrate that is exposed by the opening; forming a floating gate in the opening, wherein the floating gate extends to a part of the interlayer dielectric layer; forming a gate dielectric layer on the substrate; and forming a control gate on the substrate, wherein the control gate fills the opening.