Patent ID: 7580408

Claim:
A method for controlling a packet processor having an ingress, a control logic circuit, a parser memory, a context memory, and a match engine memory to perform a packet processing, comprising: receiving a packet having a plurality of bits, at the ingress of the packet processor; retrieving by the control logic circuit certain of the plurality of bits to obtain a first information regarding the packet; retrieving from the parser memory, based on said first information, an entry comprising a context memory base address and a label bit information, the label bit information indicating whether or not label bits specifying a protocol associated with the packet exist and, if indicating label bits exist, indicating a location in the packet of one or more of the label bits; if said retrieved label bit information indicates said label bits exist, retrieving from the packet the label bits based on said location; retrieving from the context memory a match engine index, based on the memory base address and, if said retrieved label bit information indicates said label bits exist, further based on said retrieved label bits; forming a key comprising said match index and, if said label bit information indicates said label bits exist, said key comprising said match key index combined with the retrieved label bits; searching the match engine memory to obtain a match engine entry comprising an action for the packet processor to take on the packet, based on said key; and executing an action on the packet processor, pertaining to the packet, based on the match engine entry.