Patent ID: 7948536

Claim:
A method for equalizing gain in an array of electron multiplication (EM) pixels, each pixel comprising a phase 1 clocked gate, an EM: clocked gate, and two DC gates formed between the phase 1 clocked gate and the EM clocked gate with directionality implants, comprising the steps of: (a) applying initial voltages to each of the DC gates and the EM clocked gates of at least two pixels of a plurality of pixels; (b) clocking phase 1 clock gates and an EM clock gates associated with the at least two pixels of the plurality of pixels a predetermined number of times to achieve an average pixel intensity value after impact ionization gain; and (c) selectively adjusting the difference in voltage between the DC gate and corresponding EM clocked gate of the at least two pixels of the plurality of pixels until the difference between the resulting pixel intensity values and the average pixel intensity value needed to produce a desired image is below a predetermined threshold.