Patent ID: 8592275

Claim:
A method for producing a semiconductor device including a first memory cell having a first control gate electrode and a first memory gate electrode and a second memory cell having a second control gate electrode and a second memory gate electrode, the first and second memory cells being formed over the main face of a semiconductor substrate, the method comprising the steps of: (a) forming a well of a first conductivity type over the semiconductor substrate; (b) forming a first gate insulation film over the well; (c) forming the first and second control gate electrodes over the first gate insulation film; (d) after the step (c), forming a second gate insulation film over the main face of the semiconductor substrate; (e) after the step (d), forming a conductive film over the main face of the semiconductor substrate; (f) after the step (e), forming a first insulation film over the main face of the semiconductor substrate; (g) patterning the first insulation film in the manner of covering the first control gate electrode and the vicinity thereof; (h) after the step (g), forming a sidewall comprised of the first insulation film by anisotropic etching over the side face of the conductive film with which the sidewall of the first control gate electrode is covered; (i) after the step (h), forming the first and second memory gate electrodes over both the sidewalls of the first and second control gate electrodes by patterning the conductive film formed over the second gate insulation film; (j) after the step (i), removing the sidewall; (k) after the step (j), removing one of the first and second memory gate electrodes formed over both the sidewalls of each of the first and second control gate electrodes; (l) after the step (k), leaving the second gate insulation film between the sidewalls of the first and second control gate electrodes and the first and second memory gate electrodes and between the well and the first and second memory gate electrodes by patterning the second gate insulation film; and (m) after the step (l), forming source and drain regions of a second conductivity type functioning as the conductivity type opposite to the first conductivity type of the first and second memory cells respectively in the well, wherein the first memory gate electrode is formed so as to have a gate length longer than the gate length of the second memory gate electrode.