Patent ID: 8873317

Claim:
A memory device comprising: memory cells, a first driver coupled to a terminal and driven by a first signal; a second driver coupled to the terminal and driven by a second signal; a first pre-driver which receives a third signal based on data from the memory cells while a signal is being output to outside the memory device at the terminal, outputs the first signal in accordance with the third signal, and during a transition to and from a state assumed while a signal is being received from outside the memory device at the terminal, outputs the first signal which transitions at a lower rate than that during a transition to and from a state assumed while a signal is being output to outside the memory device at the terminal; and a second pre-driver which receives a fourth signal based on data from the memory cells while a signal is being output to outside the memory device at the terminal, outputs the second signal in accordance with the fourth signal, and during a transition to and from a state assumed while a signal is being received from outside the memory device at the terminal, outputs the second signal which transitions at a lower rate than that during a transition to and from a state assumed while a signal is being output to outside the memory device at the terminal.