Patent ID: 7375557

Claim:
A phase-frequency detector, comprising: a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a delayed reset signal; a second flip-flop configured to generate a second signal, the second signal transitioning to the first logic level in response to a second edge of a second input signal and transitioning to the second logic level in response to the delayed reset signal; a first delay unit configured to delay a reset signal to generate the delayed reset signal; and a second delay unit configured to delay the reset signal to generate an output control signal for adjusting at least one of the first and second signals; an output unit configured to adjust at least one of the first and second signals based on the output control signal to generate first and second output signals, wherein the first output signal transitions to the first logic level in response to a leading edge of the first signal and transitions to the second logic level in response to the output control signal, and the second output signal transitions to the first logic level in response to a leading edge of the second signal and transitions to the second logic level in response to the output control signal.