Patent ID: 6889300

Claim:
A memory system, comprising: a communication channel coupled to a master memory device and coupled to a slave memory device; the master memory device configured to generate control information and associated data information including a plurality of write commands with associated write information for each write command to the slave memory device followed by any operation code other than a read or write command to the slave memory device and then followed by a read command to the slave memory device; and the slave memory device configured to process the read command prior to completing the processing of at least one of the plurality of write commands without causing a column resource conflict at a memory core of the slave memory device; wherein the slave memory device includes: a write data buffer to store the associated write information of at least one of the plurality of write commands, the write buffer configured to receive the associated write information in a first step and to retire the associated write information from the write data buffer to the memory core of the slave memory device in a second step.