Patent ID: 7051227

Claim:
A circuit comprising: a finite state machine (FSM) having a first state and a second state, the FSM to operate in the second state when a first set of selected conditions are satisfied in an integrated circuit (IC), and to operate in the first state when a second set of selected conditions satisfied in the IC, the first set of selected conditions indicative of a low workload period in the IC; a clock signal generator to generate a first clock signal having a first frequency; and a gating circuit coupled to the FSM and the clock signal generator, the gating circuit to output a second clock signal having the first frequency when the FSM is in the first state, and to output the second clock signal having a second frequency that is less than the first frequency when the FSM is in the second state, the gating circuit including a mask generator coupled to the FSM and the clock signal generator to generate a mask signal used to mask selected clock cycles of the first clock signal, the mask generator comprising: a multiplexer including an output port, input ports, and a control lead, wherein two of the input ports of the multiplexer are coupled to receive first and second reference signals; a first comparator including an output lead coupled to the control lead of the multiplexer, a first input port coupled to receive a third reference signal, and a second input port; a first register including an input port coupled to the output port of the multiplexer, an output port, and a clock terminal coupled to the clock signal generator; a second comparator including an output lead, a first input port coupled to receive a fourth reference signal, and a second input port coupled to the output port of the first register; an increment circuit including an input port counted to the output port of the first register and an output port coupled to one of the input ports of the multiplexer and to the second input port of the first comparator; and a second register including a clock terminal coupled to the clock signal generator, an output lead, and an input lead coupled to the output lead of the second comparator.