Patent ID: 8922404

Claim:
A signal processor, comprising: an AD-convertor having a plurality of input channels and outputting a conversion result and a conversion end flag when an AD-conversion is ended, each channel of the AD-convertor configured to be inputted a first signal, a second signal, a first inverse signal and second inverse signal, the second signal having a phase difference with ninety degrees to the first signal, a phase of the first inverse signal being inversed to a phase of the first signal, a phase of the second inverse signal being inversed to a phase of the second signal; a first comparator configured to compare signal levels of the first signal and the second signal to output a first comparison signal; a second comparator configured to compare signal levels of a first inverse signal and the second signal to output a second comparison signal; a channel selection signal generation unit configured to generate a channel selection signal to select an input channel in the AD-convertor on a basis of signal values of the first comparison signal and the second comparison signal; an direction identification flag generation unit configured to generate an direction identification flag on a basis of a phase relation between the first comparison signal and the second comparison signal; an edge signal generation unit configured to generate rising edges and lowering edges of the first comparison signal and the second comparison signal; an up-down counter configured to subject to be up or down on a count value in an output of each of edge signals using the direction identification flag as an up-down exchange signal; and an arithmetic processing unit configured to interlink the count value of the up-down counter and the conversion result of the AD-convertor to generate output data; wherein the arithmetic processing unit interpolates the count value of the up-down counter in the interlinking by using a correction value corresponding to a value of the direction identification flag in a period between an output of the edge signal and an output of the conversion end flag.