Patent ID: 8018249

Claim:
A logic system, the logic system comprising: a plurality of individually addressable resource blocks, wherein the individually addressable resource blocks are arranged at different resource block positions of a reconfigurable logic chip; a configuration repository comprising a plurality of block configurations describing configurations of resource blocks; wherein one or more of the block configurations are communication-bar-bypass block configurations, and wherein one or more of the block configurations are communication-bar-access blocks configurations; wherein the one or more communication-bar-bypass block configurations comprise configuration information describing a bypass connection segment extending between corresponding communication bar interface locations, wherein the corresponding communication bar interface locations are arranged at opposite boundaries of a resource block, and wherein the communication bar interface locations are predetermined with respect to the boundaries of a resource block; wherein the one or more communication-bar-access block configurations comprise configuration information describing an access structure to be inserted between a first of the predetermined communication bar interface locations and a second of the predetermined communication bar interface locations, to allow for a read access or a write access or a combined read/write access, in which combined read/write access an upstream segment and a downstream segment are used at the same time, to the communication bar; and a logic chip configuration manager, wherein the logic chip configuration manager is adapted to configure the individually addressable resource blocks using the one or more communication-bar-bypass block configurations and the one or more communication-bar-access block configurations, to establish a communication bar extending across a plurality of adjacent resource blocks, such that a communication bar signal is routed to bypass one or more of the resource blocks configured in accordance with a communication-bar-bypass block configuration, and such that the communication bar signal is coupled to a resource block logic circuitry of one or more of the resource blocks configured in accordance with a communication-bar-access block configuration.