Patent ID: 8391302

Claim:
An integrated circuit device including a packet switch, the packet switch comprising: a plurality of egress ports configured to output packets from the packet switch; a plurality of ingress ports selectively coupled to the plurality of egress ports and including a corresponding plurality of ingress buffers each comprising a random access memory having a storage capacity for storing data including a header portion including a plurality of storage units each having a storage capacity for storing a packet header and a data portion including a plurality of storage units each having a storage capacity for storing a data segment, wherein a storage unit of the plurality of storage units in the header portion of the random access memory is configured to store both a packet header of a packet and a data pointer to a storage unit in the data portion of the random access memory for storing a first data segment of a data payload of the packet; and an ingress controller coupled to the plurality of ingress ports and configured to allocate the storage capacity of the random access memory in a selected ingress buffer of the plurality of ingress buffers among a plurality of transactions types by allocating a plurality of credits to each transaction type of the plurality of the transaction types for the selected ingress buffer.