Patent ID: 8624368

Claim:
A QFN semiconductor package, comprising: a die pad; a plurality of I/O connections disposed at a periphery of the die pad; a chip mounted on a top surface of the die pad; a plurality of bonding wires for electrically connecting the chip and the I/O connections; an encapsulant for encapsulating the die pad, the I/O connections, the chip, and the bonding wires but exposing bottom surfaces of the I/O connections and a bottom surface of the die pad; a surface layer formed on the bottom surfaces of the I/O connections and the bottom surface of the die pad, wherein the surface layer partially covers the bottom surfaces of the I/O connections and the bottom surface of the die pad, such that the bottom surfaces of the I/O connections, the bottom surface of the die pad, and the surface layer together form a stepped structure; and a dielectric layer in contact with a bottom surface of the encapsulant and a bottom surface of the surface layer and having a plurality of openings for exposing the surface layer.