Patent ID: 7681167

Claim:
A layout design apparatus for designing layout of a semiconductor device, comprising: an input section for a receiving circuit-connection data including a plurality of cells in the semiconductor device and a plurality of nets connecting said cells, and an arrangement/interconnect data including an arrangement of said cells and an interconnect length of said nets; a power-dissipation calculation section for calculating a power dissipation of the semiconductor device based on said circuit-connection data, said arrangement/interconnect data, and a power dissipation library data including a power dissipation of a plurality of cells and a plurality of nets for use in the semiconductor device; an improvement-target-cell extraction section for extracting an improvement-target cell based on said circuit-connection data; a power-dissipation-reduction-possibility judgment section for judging whether a reduction in the power dissipation is possible by a relocation of said improvement-target cell in a specific shift distance, and assuming said relocation of said improvement-target cell and an associated change in said interconnect length in said arrangement/interconnect data and comparing power dissipations before and after said assumed relocation of said improvement-target cell, which are calculated by said power-dissipation calculation section, a path extracting section for extracting a signal path including said improvement-target cell based on said circuit-connection data after said power-dissipation-reduction-possibility judgment section judges that the reduction in power dissipation is possible; a possible-cell-shift-distance calculation section for calculating a possible shift distance of said improvement-target cell in said extracted signal path based on a delay library data of a plurality of cells and a plurality of nets for use in the semiconductor device, said possible shift distance satisfying a delay constraint specified for the semiconductor device; and a layout change section for relocating said improvement-target cell in said arrangement/interconnect data within a range of a shift distance in which said specific shift distance and said possible shift distance overlap each other, to update said arrangement/interconnect data.