Patent ID: 7555058

Claim:
A delay locked loop circuit comprising: an all-pass IIR filter for receiving first input IQ signals; a subtractor connected to output terminals of the all-pass IIR filter, for receiving signals based on output signals of the all-pass IIR filter, and second input IQ signals; a delay comparator connected to the output terminals of the all-pass IIR filter, for receiving the output signals of the all-pass IIR filter; and a smoothing filter connected to an output terminal of the delay comparator, and to an input terminal of the all-pass IIR filter, for receiving and smoothing an output signal of the delay comparator, and outputting a smoothed signal as an integration value to the all-pass IIR filter wherein the all-pass IIR filter is controlled by the integration value, wherein either the first input IQ signals or the second input IQ signals are signals generated as a result of output IQ signals undergoing digital-to-analog conversion, and again undergoing analog-to-digital conversion after passing through an analog circuit, and delay control is implemented for checking distortion occurring to the output IQ signals due to the same passing through the analog circuit by means of a variable delay element.