Patent ID: 7805688

Claim:
A memory construction apparatus that constructs logical memories in designing an integrated circuit, comprising: a logical memory construction-processing section that reads several kinds of physical memories and registers prepared in advance as libraries, generates respective candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, so as to construct the logical memory that satisfies a logical condition defining a memory space, and makes a list of the candidates for each individual logical memory, the listed candidates being arranged in increasing order of a total number of physical memories used in the respective candidates; an optimum construction extraction-processing section that extracts an optimum construction of logical memories which satisfy a limit number of usable physical memories and a limit number of usable registers, by evaluating each combination of candidates extracted from said lists of the candidates, until a combination satisfying said limit numbers is found; and a circuit description-processing section that describes a circuit using the physical memories and the registers to realize the extracted optimum construction of logical memories, and thereby generate a circuit description file, wherein when generating the candidates for each logical memory, said logical memory construction-processing section compares a bit number of the logical memory and a bit number of a physical memory, and when the bit number of the logical memory is smaller, said logical memory construction-processing section judges that no division in a bit direction is required, whereas when the bit number of the logical memory is larger, said logical memory construction-processing section divides the bit number of the logical memory by the bit number of the physical memory to thereby calculate a number of divisions in the bit direction and a bit number of registers.