Patent ID: 8572444

Claim:
A memory apparatus, comprising: an error correction code (ECC) memory, comprising: a plurality of data storage blocks, each data storage block having a corresponding address and storing a plurality of data bits; a plurality of parity bit storage blocks, each parity bit storage block storing a plurality of parity bits; and an error correction code (ECC) logic circuit for correcting the data bits stored in the data storage blocks according to the parity bits; a testing module, coupled to the memory, the testing module comprising: a test pattern generator, for generating a test pattern to the memory; at least one testing unit, comprising: a first judgment circuit, for reading a first data bit and a second data bit of the memory, and for determining whether the first data bit and the second data bit have an error according to the test pattern, wherein the first data bit corresponds to a first address in the memory and the second data bit corresponds to a second address in the memory; an error recording unit, coupled to the first judgment circuit, for recording the first address when the first data bit has the error; a second judgment circuit, coupled to the error recording unit, for comparing the second address in the memory with the first address recorded in the error recording unit so as to determine whether the memory has multi-bit error; and a counter for counting a number of addresses corresponding to errors of the error recording unit so as to determine an error tolerance; wherein the testing module determines whether the memory has multi-bit error when the ECC logic circuit is disabled wherein the testing module performs a first test according to the plurality of data bits and the plurality of parity bits when the ECC logic circuit is enabled, and wherein the testing module performs a second test according to only the plurality of data bits when the ECC logic circuit is disabled.