Patent ID: 8610262

Claim:
A process for manufacturing an integrated circuit comprising: mounting a semiconductor die to a first surface of a substrate; wire bonding said semiconductor die to ones of conductive traces of said substrate; fixing at least one ground pad to said substrate; encapsulating the wire bonds and said semiconductor die in a glob-top encapsulant material; disposing over said glob-top encapsulant material a heat spreader having a cap protruding therefrom, the heat spreader having at least one sidewall extending from the cap; embedding the cap into the glob-top encapsulant material while the glob-top encapsulant is in an uncured state such that the cap extends inwardly from the heat spreader and is spaced apart from the semiconductor die, the cap and the semiconductor die defining a space disposed therebetween, the space being completely filled by the glob-top encapsulant material; fixing said at least one sidewall to said at least one ground pad, an outer surface of the heat spreader is exposed to the surrounding environment and an inner surface of the at least one sidewall being spaced apart from the encapsulant material; and forming a ball grid array on a second surface of said substrate, bumps of said ball grid array being electrically connected to said conductive traces.