Patent ID: 7492198

Claim:
A delay locked loop circuit comprising: a phase comparator which receives a binary output signal and an input signal, samples the binary output signal by a timing of a rising edge or a falling edge but not both of the input signal, and outputs a phase signal representing a lead or a lag of a phase of the binary output signal relative to the input signal where the lead or lag is represented solely by one bit of either high or low; a counter which receives the phase signal, outputs a control signal, increases a value of the control signal when the phase signal has a value representing a lead of a phase, and decreases a value of the control signal when the phase signal has a value representing a lag of the phase; and a variable delay circuit which receives the control signal and the input signal, generates the binary output signal, prolongs a delay time of the binary output signal relative to the input signal when a value in the control signal is large, and shortens the delay time of the binary output signal relative to the input signal when a value in the control signal is small; wherein the phase comparator is configured by a dynamic D flip-flop and a non-dynamic D flip-flop which receives an output from the dynamic D flip-flop so that the phase comparator minimizes a hysteresis width which is dependent upon a change of direction of the phase signal that is output from the phase comparator.