Patent ID: 7890898

Claim:
A design method for a semiconductor circuit, for extraction of semiconductor circuit characteristics, having a field-effect transistor, the transistor including plural gate electrodes provided in a periphery portion of a channel section and gate insulating films sandwiched between the plurality of gate electrodes and the channel section, the method comprising the steps of: providing a device-circuit simulator; calculating capacity-voltage characteristics in a direction normal to each of the gate insulating films provided onto the channel section; obtaining a flat band voltage of the field-effect transistor by making use of the calculated capacity-voltage characteristics and premeasured capacity-voltage characteristics of the respective gate insulating films; calculating an effective normal electric field by making use of measured values of an inversion layer capacity, an accumulation layer capacity, and a depletion layer capacity of the field-effect transistor, and of the flat band voltage; extracting roughness scattering mobility at a gate insulating film interface of the field-effect transistor by making use of effective mobility, which is calculated based on the inversion layer capacity and current-voltage characteristics in a source-drain path of the field-effect transistor; inputting the extracted roughness scattering mobility to said device-circuit simulator; and performing a circuit simulation for the semiconductor circuit using said device-circuit simulator, wherein the flat band voltage is determined as a set of a plurality of voltages corresponding to the plurality of gate insulating films and to each gate electrode, through comparison of an actual measurement value in an accumulation layer capacity of an accumulated transistor that is prepared in advance for measurement with the calculated capacity-voltage characteristics.