Patent ID: 8639918

Claim:
An apparatus, comprising: a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard; a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard; a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket; a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system; and a power regulation module communicatively coupled to the virtualization module and the second socket, the power regulation module configured to output an amount of power to the second socket based upon the initialization data.