Patent ID: 7304899

Claim:
An integrated semiconductor memory, comprising: a multiplicity of externally programmable elements irreversibly programmable with a first or second programming state via a production unit during fabrication of the integrated semiconductor memory; a read-out circuit for reading out the respective programming state of the programmable elements with an output terminal for generating a bit sequence of a first data record, wherein the read-out circuit reads out the respective programming state from a respective one of the programmable elements and generates the bit sequence of the first data record at the output terminal depending upon the respective programming state of the programmable elements; and a decompression circuit with an input terminal for applying the bit sequence of the first data record and an output terminal for generating a bit sequence of a second data record, wherein the decompression circuit generates the bit sequence of the second data record based on a decompression method, so that the bit sequence of the second data record is longer than the bit sequence of the first data record.