Patent ID: 8842473

Claim:
A method of accessing a non-volatile memory circuit, the memory circuit including an array non-volatile memory cells formed along multiple columns, the array having a series of first shift registers connected thereto, each first shift register connected to a distinct plurality of N of the columns, where as a pointer moves through the series of first shift registers in response a clock signal one of the columns connected thereto is selected and the pointer loops through the series of first shift registers N times to access all of the columns, wherein each column has an associated bit indicating whether it is defective, in response to which the first shift register skips the corresponding defective column in the series, the method comprising: maintaining in the non-volatile memory a count of the number of defective columns for each loop except the last in the series; receiving an address; determining the corresponding loop and residual column address within the corresponding loop for the received address if none of the columns were defective; determining from the count of defective columns for each loop the cumulative number of defective columns for the loops preceding the loop to which the received address would correspond if none of the columns were defective; offsetting the residual column address within the corresponding loop to which the received address would correspond by the cumulative number of defective columns for the preceding loops; and starting from the offset column address in the corresponding loop, subsequently shifting through the columns to account for defective columns in the corresponding loop.