Patent ID: 8102697

Claim:
A programmable resistance memory device comprising: a semiconductor substrate; at least one cell array, formed above the semiconductor substrate, which comprises a plurality of bit lines arranged in parallel with each other, a plurality of word lines arranged in parallel with each other in such a direction as to cross the bit lines, and memory cells connected between the bit lines and the word lines at cross points of the bit lines and word lines, each memory cell comprising a programmable resistance element which stores a high resistance state or a low resistance state in a non-volatile manner; and a read/write circuit formed on the semiconductor substrate and under the cell array and connected to the bit lines and word lines, the read/write circuit being configured to apply a first write voltage in data writing to develop the low resistance state and a second write voltage in data writing to develop the high resistance state to one of the bit line or the word line, the first write voltage and the second write voltage being generated to have values shifted in directions that oppose each other.