Patent ID: 8001450

Claim:
A semiconductor memory device having an error correction function, comprising: a data memory cell array which includes a plurality of memory cells and inputs and outputs data of 2 I bits (where I is an integer of two or more) with respect to a data bus in response to word selection; a parity memory cell array which includes a plurality of memory cells and inputs and outputs parity bits of a number of bits which corresponds to the 2 I bit data with respect to a parity bus in response to the word selection; a data I/O terminal; a parity generation circuit which generates the parity bits from write data of 2 I bits which are input from the data I/O terminal and outputs the parity bits to the parity bus; a syndrome generation circuit which generates, from the parity bits which are read from the parity memory cell array to the parity bus and read data of 2 I bits which are read from the data memory cell array to the data bus, a syndrome bit indicating an error bit position in the read data; and an error correction circuit which corrects errors in the read data on the basis of the syndrome bit, wherein the parity generation circuit and the syndrome generation circuit are constituted so as to be capable of switching to either a first ECC having 2 I bit data and parity bits of I+1 bits or a second ECC having 2 J groups of data of 2 (I−J) bits (where I>J and J is an integer of one or more) and parity bits of I−J+1 bits.