Patent ID: 7904765

Claim:
A test apparatus for testing a plurality of memories under test, the test apparatus comprising: a plurality of test signal supply sections, each of which is connected to a corresponding terminal of a corresponding one of the memories under test, and supplies a test signal for writing test data to the memory under test being the connection destination, to the terminal; a plurality of terminal correspondence determination sections, each of which is connected to a corresponding terminal of a corresponding one of the memories under test, and outputs a terminal unit determination result indicating whether test data read from the terminal being the connection destination matches an expected value; a determination-side connection information memorizing section that memorizes determination-side connection information that associates each of the terminal correspondence determination sections to a corresponding one of the memories under test that is the connection destination; and a determination result treatment section that determines whether writing to each of the memories under test succeeded based on a plurality of terminal unit determination results collected from the plurality of terminal correspondence determination sections and the determination-side connection information, and causes the plurality of test signal supply sections to re-test memories under test to which writing failed, the determination result treatment section comprising a determination result selection section that selects, for each memory under test, the plurality of terminal unit determination results outputted from the plurality of terminal correspondence determination sections and rearranges the selected terminal unit determination results in the order of a plurality of terminals of the plurality of memories under test, based on the determination-side connection information.