Patent ID: 7555695

Claim:
A data transmitting apparatus that transmits a plurality of bits in parallel in a clock cycle, the data transmitting apparatus comprising: a code generating unit that divides original transmission data into a plurality of partial data, and generates an error correction code for each of the partial data; a data dividing unit that divides the original transmission data into a plurality of 1-clock data each of which is transmitted in parallel in a clock cycle, wherein the 1-clock data and the partial data are different data; and a transmission control unit that sequentially transmits the plurality of 1-clock data one-by-one in synchronization with a clock, and collectively transmits the error correction codes generated by the code generating unit in a clock cycle in synchronization with the clock, wherein each of the error correction codes is made redundant if a sum of lengths of the error correction codes is shorter than a size of the 1-clock data.