Patent ID: 8158967

Claim:
An integrated memory array, comprising: a plurality of horizontally-extending electrically conductive lines supported by a semiconductor substrate, the lines being vertically spaced from one another and extending primarily along a first horizontal axis; a plurality of horizontally-extending semiconductor material wires joined to the lines and extending outwardly from the lines, the wires extending primarily along a second horizontal axis that is orthogonal to the first axis; the wires having first ends adjacent the electrically conductive lines, and having second ends in opposing relation to the first ends; the wires being arranged in a two-dimensional array; one of the dimensions of the two-dimensional array being rows along the first horizontal axis, and the other of the dimensions of the two-dimensional array being columns along a vertical axis orthogonal to the first and second horizontal axes; the horizontally-extending electrically conductive lines interconnecting wires along the rows of the array; gate dielectric along outer edges of the wires; gate material contacting the gate dielectric material along at least two sides of each individual wire, the gate material being comprised by a gate structure that extends primarily along the vertical dimension; memory cell structures at the second ends of the wires; and a plurality of vertically-extending electrical interconnects connected to the wires through the memory cell structures, the vertically-extending electrical interconnects being horizontally spaced from one another; individual vertically-extending electrical interconnects extending along individual columns of the array.