Patent ID: 7822113

Claim:
An integrated decision feedback equalizer and clock and data recovery circuit, comprising: a decision feedback equalizer including: a flip-flop that outputs a first feedback signal, and a sub-portion of a plurality of latches, wherein each latch of the sub-portion of the plurality of latches outputs a respective latch-generated feedback signal; a clock recovery circuit including: the flip-flop that outputs a first phase detector input signal, and the plurality of latches, wherein each latch in the plurality of latches outputs a respective latch-generated phase detector input signal, wherein the plurality of latches receives the output of the flip-flop as a first input to the plurality of latches, and wherein the plurality of latches includes both the sub-portion of a plurality of latches and latches which are not included by the sub-portion of a plurality of latches; and the flip-flop that is included by both the decision feedback equalizer and the clock recovery circuit.