Patent ID: 8856708

Claim:
A method of verifying a field programmable gate array for use in an integrated system, the method comprising: selecting, by a computer, from a set of requirements of the field programmable gate array, a first subset of the requirements that are not influenced by dynamics of the integrated system and are explicit, deterministic and timing independent with respect to inputs of the field programmable gate array; selecting, from the set of requirements of the field programmable gate array, a second subset of the requirements that are influenced by the dynamics of the integrated system and comprise one or more of a timing requirement, an arbitration requirement, a hardware/software integration requirement, an external logic control requirement, a test mode feature requirement, a closed loop operation requirement, and a transient response requirement; executing a first hardware test on the field programmable gate array using a chip tester circuit board that verifies the first subset of the requirements; and executing a second hardware test on the field programmable gate array to verify the second subset of the requirements while the field programmable gate array is installed within the integrated system.