Patent ID: 7575973

Claim:
A method of making a monolithic, three dimensional NAND string comprising a first memory cell located over a second memory cell, the method comprising: forming a select transistor on a substrate or in a trench in the substrate; growing a semiconductor active region of a second memory cell comprising epitaxially growing a second semiconductor layer on a semiconductor active region of the select transistor; planarizing the second semiconductor layer; patterning the second semiconductor layer into a second semiconductor strip extending in a first direction; forming a third insulating layer adjacent to exposed lateral sides of the second semiconductor strip; patterning the second semiconductor strip to form a second semiconductor pillar; forming a third charge storage dielectric located adjacent to a first exposed side of the second semiconductor pillar; forming a third control gate adjacent to the third charge storage dielectric; forming a fourth charge storage dielectric located adjacent to a second exposed side of the second semiconductor pillar; forming a fourth control gate adjacent to the fourth charge storage dielectric; and epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the second memory cell in a different growth step from the step of growing the semiconductor active region of second memory cell; wherein: the second semiconductor pillar comprises the semiconductor active region of the second memory cell; the second semiconductor pillar comprises a first conductivity type semiconductor region located between second conductivity type semiconductor regions; and the second semiconductor pillar is not aligned to the semiconductor active region of the first memory cell.