Patent ID: 7672187

Claim:
A memory device comprising: a first power supply line; a second power supply line; a static random access memory (SRAM) cell comprising a first logic gate and a second logic gate that are cross-coupled, wherein the first power supply line supplies the first logic gate, and the second power supply line supplies the second logic gate; and an elastic power header device connected between a reference voltage and each one of the first power supply line and the second power supply line, wherein the elastic power header device is configured to provide, during a write operation of the SRAM cell, different power supply levels on the first power supply line and the second power supply line and is configured to provide, during a read operation, a first resistance in the first power supply line and a second resistance in the second power supply line, and wherein the elastic power header device is configured to receive one or more write data signals and a write enable signal through a logic circuit and to selectively adjust the power supply levels on the first power supply line and the second power supply line based on an output of the logic circuit.