Patent ID: 6876572

Claim:
A programmable logic device configuration memory cell on a programmable logic device that receives programming data at a programmable logic device configuration memory cell input terminal and that provides an output signal at a corresponding programmable logic device configuration memory cell output terminal, wherein the output signal is applied to a programmable logic connector on the programmable logic device to configure the programmable logic connector, the programmable logic device configuration memory cell comprising: a pair of cross-coupled inverters connected between the programmable logic device memory cell input terminal and the programmable logic device memory cell output terminal, wherein the cross-coupled inverters store the programming data; and a stabilizing capacitor connected between the programmable logic device configuration memory cell input terminal and the programmable logic device memory cell output terminal, wherein the stabilizing capacitor has at least two opposing metal electrodes and serves to buffer voltages at the programmable logic device configuration memory cell input terminal and the programmable logic device configuration memory cell output terminal when the memory cell is subjected to a radiation strike.