Patent ID: 7943486

Claim:
A method for forming a silicon-containing semiconductor material comprising: providing a silicon-containing <110> layer; forming by electrolytic anozidation at least one porous Si layer in an uppermost surface of said <110> Si-containing layer, said at least one porous Si layer having a porosity of about 0.1% or greater; annealing at a temperature from about 900° to about 1150° C. the uppermost surface to create a non-porous surface layer; forming a crystalline epitaxial Si-containing layer having a <110> orientation on the non-porous surface layer thereby forming a transfer structure; bonding the transfer structure to a material that has a higher coefficient of thermal expansion than Si at a temperature that is elevated above the ultimate device operating temperature to provide a bonded structure; cooling the bonded structure so that a mechanically weak interface forms at said at least one porous Si layer, wherein a difference in coefficient of thermal expansion between the transfer structure and the at least one porous Si layer produces a biaxial compressive stress in the silicon-containing <110> layer and cleaves said bonded structure at an interface present on the at least one porous Si layer; removing remaining portions of the least one porous Si layer from the cleaved structure; and forming a CMOS device on the silicon-containing <110> layer having the biaxial compressive stress, wherein a channel length of an n-type field effect transistor and a p-type field effect transistor is positioned along a direction, wherein a compressive stress greater than 0.2% produced by the biaxial compressive stress increases carrier mobility in both the n-type field effect transistor and p-type field effect transistor of the CMOS device in comparison to a relaxed silicon-containing <100> layer.