Patent ID: 8482044

Claim:
A semiconductor memory device comprising a ferroelectric capacitor comprising: a substrate; a field effect transistor comprising a word line on the substrate via an insulating layer and a pair of impurity diffusion layers in an element region in a surface layer of the substrate, the word line being interposed between the pair of impurity diffusion layers; a ferroelectric capacitor above the substrate, the ferroelectric capacitor comprising a lower electrode connected to a first one of the pair of the impurity diffusion layers, a ferroelectric film on the lower electrode, and an upper electrode on the ferroelectric film; and a bit line below the lower electrode, the bit line connecting to a second one of the pair of impurity diffusion layers via a bit line contact; wherein each of memory cells comprises the field effect transistor and the ferroelectric capacitor, a memory cell group comprises the memory cells in a first direction with a predetermined pitch, and memory cells in the group are aligned in rows in a second direction, each memory cell is configured to share the bit line contact with an adjacent memory cell at one side in the first direction and to connect to the bit line, and three of the word lines are disposed between the bit line contacts in the first direction; and wherein the bit line is at an acute angle to the first direction, and the ferroelectric capacitor is substantially perpendicular to the word line.