Patent ID: 7464243

Claim:
An apparatus for performing sequenced read and write operations on a computer memory, comprising: a data communication channel; a processor in communication with the data communication channel; a memory comprising a computer-readable medium; and a memory controller circuit block configured for: receiving from the processor over the data communication channel a single command comprising: address data that indicates a location in memory, first length data that indicates an amount of memory to be initialized, pattern data comprising a particular plurality of bits, and second length data that indicates a length of the pattern data to be written to the memory, wherein the length of the pattern data is much shorter than the amount of memory to be initialized; and performing a plurality of write operations on memory beginning at a first location in memory based on the address data and ending at a second location in memory based on the first length data, wherein each write operation of the plurality of write operations writes the pattern data to a current location in memory, whereby an arbitrary portion of memory is initialized with an arbitrary pattern based on the pattern data.