Patent ID: 6879203

Claim:
A whole chip electrostatic discharge ECD method comprising the steps of: connecting all input/output, I/O pads to each other with double isolation; and inserting a circuit of the first embodiment of this invention between each adjacent I/O pair on a semiconductor chip, wherein the first embodiment comprises; a PN diode whose p-side connects to the input/output, I/O pad to be protected and whose N-side is connected to Vcc supply voltage; a PMOS FET plus NMOS FET 2-device input stage connected between Vcc and Vss; a resistor plus NMOS FET first mid stage connected between Vcc and Vss (ground); a resistor to ground second mid-stage; and a PMOS FET plus NMOS FET output stag connected between Vec and Vss (ground) whose input connects from the mid-stages and whose output drives an unused I/O pad.