Patent ID: 7482966

Claim:
An algorithm analog-to-digital converter (ADC), comprising: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage; two flash ADCs for converting one analog input signal into two digital signals n 1 and n 2 through different capacitor connections and outputting the two digital signals; one multiplying digital-to-analog converter (MDAC) for amplifying a difference between an output voltage Vs of the SHA and a reference voltage ±Vref through different capacitor connections according to the digital signals output from the flash ADCs and outputting the amplified difference to the flash ADCs again; a sequential multiphase clock generating circuit for outputting different operating clock frequencies according to the required resolution; and an output stage for adding the two digital signals n 1 and n 2 output from the flash ADCs to obtain a final output value.