Patent ID: 7969810

Claim:
A dynamic random access memory, comprising: a plurality of individual arrays of memory cells providing a capacity of 256 Meg and organized into four symmetrically arranged arrays each having a capacity of 64 Meg, each 64 Meg array being divided into two 32 Meg arrays, each 32 Meg array being divided into eight blocks with the blocks organized into four pairs of two blocks each; a plurality of pads located centrally with respect to said array blocks; a plurality of peripheral devices for transferring data between said memory cells and said plurality of pads, said peripheral devices including logic for accessing said memory device by: using a plurality of address bits to select one of the four 32 Meg arrays; using two address bits to select one of the four pairs of blocks; using another one address bit to select one of the blocks in the selected pair; and using additional address bits to address individual rows or columns in said selected block; a plurality of voltage supplies located proximate said plurality of pads for generating a plurality of supply voltages, wherein said plurality of voltage supplies includes a bias generator for supplying a bias voltage to said array blocks, said bias generator including an output status monitor; and a power distribution bus for delivering said plurality of supply voltages to said individual arrays and said plurality of peripheral devices.