Patent ID: 8461877

Claim:
A complementary metal oxide semiconductor (CMOS) circuit comprising: a plurality of CMOS gates, each CMOS gate connected to a negative power supply terminal (Vss) and a positive power supply terminal (Vdd), each CMOS gate including a plurality of logic inputs and a logic output; a first parasitic net connected to each of the CMOS gates; and a first net pulldown circuit comprising: a first transistor having a first drain terminal connected to the first parasitic net, a first source terminal, and a first gate terminal connected to a first one of the logic inputs; and a second transistor having a second drain terminal connected to the first source terminal, a second gate terminal connected to a second one of the logic inputs, and a second source terminal connected to the negative power supply terminal (Vss); a second parasitic net connected to each of the CMOS gates; and a second net pulldown circuit comprising: a third transistor having a third drain terminal connected to the second parasitic net, a third source terminal, and a third gate terminal connected to the second logic input; and a fourth transistor having a fourth drain terminal connected to the third source terminal, a fourth gate terminal connected to the first logic input, and a fourth source terminal connected to the negative power supply terminal (Vss).