Patent ID: 7287325

Claim:
A method of simultaneously forming different structures in an integrated circuit structure, said method comprising: forming a release layer on a dielectric layer; etching a multi-tier trench, comprising a deep first tier and a shallow second tier, into said dielectric layer; lining said multi-tier trench with a liner; filling said multi-tier trench with a conductor so as to create a conductive interconnect line in said shallow second tier and a conductor-filled via in said deep first tier; polishing said liner and said conductor off said release layer, wherein trace amounts of at least one of said liner and said conductor remain on said release layer after polishing said liner and said conductor; removing said release layer, wherein said trace amounts are removed as said release layer is removed; depositing a second dielectric layer over said dielectric layer and said conductive interconnect line; polishing said second dielectric layer to expose said conductive interconnect line; and depositing a capping layer over said second dielectric layer and said conductive interconnect line, wherein said process of etching said second tier comprises performing an isotropic etching process such that said second tier is formed with sidewalls overlapped by said release layer, wherein said processes of polishing said liner and said conductor and removing said release layer thereby forms a narrow top portion of said conductive interconnect line that extends above said dielectric layer, and wherein said process of depositing said second dielectric layer comprises depositing said second dielectric layer around said narrow top portion to form reinforced corners around said top portion of said conductive interconnect line.