Patent ID: 7975172

Claim:
A circuit arrangement, comprising: an integrated circuit device including: a multistage execution pipeline including a stage configured to perform an operation during execution of an instruction by the multistage execution pipeline; and control logic coupled to the multistage execution pipeline and configured to verify a result computed by the stage of the multistage execution pipeline during execution of the instruction by causing the stage to repeat the operation for the instruction during a subsequent execution cycle in which a bubble exists in the multistage execution pipeline, wherein the multistage execution pipeline is configured to perform the operation during a first execution cycle, wherein the control logic is configured to cause the stage to repeat the operation during a second execution cycle, and wherein the control logic is configured to verify the result by storing first result data computed by the stage during execution of the instruction in the first execution cycle and comparing the stored first result data with second result data computed by the stage during the repeat of the operation during the second execution cycle.