Patent ID: 7838334

Claim:
A semiconductor package comprising: a substrate having an upper surface and a lower surface opposite to the upper surface; a chip electrically connected to the upper surface of the substrate; an interposer disposed on the chip and electrically connected to the substrate, wherein the interposer has an upper surface and a lower surface, the lower surface is opposite to the upper surface and faces the chip, the interposer comprises an embedded component and a plurality of first electric contacts, the embedded component is located between the upper and lower surfaces of the interposer, and the first electric contacts are located on the upper surface of the interposer, the interposer further comprises a silicon substrate and a molding compound material, the silicon substrate includes an opening, the embedded component is disposed within the opening and secured by the molding compound material, and the interposer further comprises upper circuit layers formed on the upper surface; and a molding compound sealing the chip and covering the upper surface of the substrate and the lower surface of the interposer.