Patent ID: 7397642

Claim:
An ESD protection circuit, comprising: a trigger current generation circuit generating a trigger current; and a stacked MOS circuit that receives said trigger current, and then conducts electrically as a first releasing path of ESD; wherein said trigger current generation circuit comprises: a first resistor, having a first end connecting to a first power supply; a first capacitor, having a first end connecting to a second end of said first resistor; a first NMOS, having a gate connecting to said second end of said first resistor, and a substrate connecting to a source; a second resistor, having a first end connecting to a drain of said first NMOS, a second end connecting to said source of said first NMOS and a second end of said first capacitor, and said second end connecting to a ground; a third capacitor, having a second end connecting to said first end of said second resistor; a second capacitor, having a second end connecting to a first end of said third capacitor, and a first end connecting to a second power supply; a fourth capacitor, having a first end connecting to said first end of said second capacitor and said second power supply; and a third resistor, having a second end connecting to a second end of said fourth capacitor, and a first end connecting to said first power supply.