Patent ID: 8392770

Claim:
A resistance change memory device comprising a cell array, in which memory cells are arranged, the memory cell being reversibly set in one of a first data state and a second data state defined in accordance with the resistance value, wherein the memory device has a data write mode including: a first write procedure for writing the first data in the cell array; and a second write procedure for writing the second data in the cell array, the second write procedure being different from the first write procedure, wherein the memory cell has such a property that the time necessary for writing the second data is twice or more as long as the first data, and wherein the first write procedure is for writing the first data in all cells in a selected cell area in a lump while the second write procedure is for sequentially writing the second data in multiple cell groups sectioned in the selected cell area on the condition that the total cell current of simultaneously written cells is limited under a permissible value.