Patent ID: 7545185

Claim:
A dual-mode frequency divider, comprising: (a) a differential input inputting a signal of a to-be-divided frequency; (b) a pair of latch circuits, each said latch circuit comprising a plurality of transistors, said plurality of transistors comprising a pair of input transistors, a pair of flip-flop transistors and a pair of feedback-receiving transistors, wherein said input transistor receives said signal of said to-be-divided frequency from said differential input, said flip-flop transistor obtains a first buffer signal by processing said signal of said to-be-divided frequency together with an inner switching signal, and said feedback-receiving transistor receives a second buffer signal from another latch circuit; (c) an output buffer connecting to an output of said pair of latch circuits, said output buffer magnifying a signal of a divided frequency obtained from said pair of latch circuits through a magnifying circuit; and (d) a differential output outputting said signal of said divided frequency, wherein an output divisor of an even number is obtained from said signal of said to-be-divided frequency through said latch circuit, wherein a power of said signal of said to-be-divided frequency is increased to widen a frequency range of said signal of said to-be-divided frequency and to obtain said output divisor of said even number, wherein the dual-mode frequency divider is configured to have two selectable operation modes comprising a static operation mode and an injection-locking operation mode, wherein said differential input further comprises a DC controlling signal device.