Patent ID: 8482136

Claim:
A chip scale package, comprising: a semiconductor die embedded in a die support body formed of a molding composition, the semiconductor die having a die surface with a first area, the die support body having a layer support surface proximal the first area, the die having a plurality of first bond pads disposed in a first spaced arrangement on the first area, the first spaced arrangement having a first minimum center-to-center bond pad spacing; a bond pad spacing interface structure supported, at least in part, by the layer support surface of the die support body, the bond pad spacing interface structure having a plurality of second bond pads in a second spaced arrangement over a second area, the second spaced arrangement having a second minimum center-to-center bond pad spacing, and a plurality of electrical conductors, each of the electrical conductors connecting a corresponding one of the first bond pads to a corresponding one or more of the second bond pads, wherein the first bond pads are arranged with a first average density of bond pads per unit area and the second bond pads are arranged with a second average density value of bond pads per unit area that is lower than said first density.