Patent ID: 7639530

Claim:
A method for operating a CMOS memory system comprising a processor coupled to an NROM array that comprises a plurality of NROM cells, each NROM cell having a gate and two source/drain regions, the method comprising: applying a constant voltage to the gate of each NROM cell to be erased; applying a constant positive current into a first of the source/drain regions of each NROM cell to be erased; applying a ground potential to the remaining source/drain region of each NROM cell to be erased, wherein a nitride charge storage layer that is being erased is a continuous blanket over the NROM array such that the nitride charge storage layer does not cover the gate and an oxide layer between the gate and the nitride charge storage layer; monitoring the first source/drain region for a predetermined voltage level; and ending the method for operating when the predetermined voltage level is reached.