Patent ID: 7760560

Claim:
A flash memory device comprising: a plurality of memory cell blocks respectively including a plurality of memory cells sharing local word lines and bit lines; a X-decoder to decode a row address signal and output first decoding signals and second decoding signal; a plurality of block selection units to output a plurality of block selection signals, respectively, in response to the first decoding signals, respectively; a plurality of gate circuits to connect a global drain selection line, a global source select line, and global word lines to local drain selection lines, local source select lines, and the local word lines of the memory cell blocks, respectively, in response to the plurality of block selection signals, respectively; a first pump to generate a program voltage in response to a program command; a second pump to generate a program pass voltage in response to the program command; a voltage selection circuit to select one selected from a plurality of global word lines, and supply the program voltage to the selected global word line and the program pass voltage to the remaining global word lines, in response to the second decoding signal; a first high-voltage switch circuit to supply the program voltage to the voltage selection circuit in response to an enable control signal and clock signals; and a second high-voltage switch circuit to supply the program pass voltage to the voltage selection circuit in response to the enable control signal and the clock signals, wherein each of the plurality of block selection units comprises: a block switch to receive the program voltage, and output one of the plurality of block selection signals as a voltage level higher than that of the program voltage or a voltage level lower than that of the program voltage in response to a block switch control voltage; and a third high-voltage switch circuit to receive the program voltage, and output the program voltage as the block switch control voltage in response to one of the first decoding signals and the clock signals, wherein each of the high-voltage switch circuits comprises an amplification circuit of a cross-coupled type.