Patent ID: 8823174

Claim:
An electronic device comprising: a substrate having a first main surface, a second main surface opposite the first main surface and a plurality of wirings; a first semiconductor chip arranged above the first main surface and having a first obverse surface, a CPU circuit and a plurality of bumps formed on the first obverse surface; a first memory chip having a first group of electrodes; and a second memory chip having a second group of electrodes and through electrodes penetrating the second memory chip in a thickness direction of the second memory chip, the through electrodes being electrically connected to the second group of electrodes; wherein the first memory chip is stacked on the second memory chip over the substrate such that the first group of electrodes of the first memory chip are electrically connected to the through electrodes of the second memory chip, wherein the first group of electrodes of the first memory chip, the second groups of electrodes of the second memory chips are arranged in a first predetermined pitch, and wherein the bumps of the first semiconductor chip, the second groups of electrodes of the second memory chips are electrically connected to the wirings of the substrate.