Patent ID: 6922650

Claim:
Semiconductor device test equipment which performs a test while stretching the period of a preset test cycle to a stretch cycle period, characterized by the provision of: a pattern-generation memory provided with a test pattern storage part having stored therein a test pattern to be applied to a semiconductor device under test and an expected value pattern for comparison with the output from said semiconductor device under test and a control pattern storage part having stored therein a control pattern for controlling the period for application of said test pattern read out of said test pattern storage part; a test cycle memory which stores a plurality of pieces of period data and from which one of said plurality of period data is read out in accordance with said control pattern; a test cycle generator which is supplied with the period data read out of said test cycle memory and controls, in accordance with said period data, the period for application of said read-out test pattern; a period data storage having stored therein period data on said stretch cycle period; a stretch cycle detecting part which has set therein data representing the test cycle to be cycle-stretched and, when the read-out test cycle of said test pattern reaches the test cycle represented by said data set therein, detects it; and switching part which is controlled by the detection signal from said stretch cycle detecting part to switch long-period data stored in said period data storage to the period data read out of said test cycle memory for application to said test cycle generator.