Patent ID: 7088622

Claim:
A nonvolatile semiconductor memory apparatus, comprising: a memory transistor; and memory peripheral circuits for controlling an operation of said memory transistor, wherein said memory transistor comprises: a first conductive type semiconductor substrate; a first conductive type channel forming region regulated in a surface region of said semiconductor substrate; a first source/drain region formed on one side of said channel forming region in the surface region of said semiconductor substrate and electrically connected to said memory peripheral circuits; a second source/drain region formed on the other side of said channel forming region in the surface region of said semiconductor substrate and electrically connected to said memory peripheral circuits; a charge storage film formed at least on said channel forming region and having a charge storage faculty; and a gate electrode formed on said charge storage film and electrically connected to said memory peripheral circuits; and said memory peripheral circuits generate a first voltage, apply said generated first voltage to said second source/drain region by using potential of said first source/drain region as a reference, generate a first polarity voltage and a second polarity voltage, a potential difference thereof is equal to a second voltage, apply said generated first polarity voltage to said gate electrode, apply said generated second polarity voltage to said semiconductor substrate and inject hot electrons to said charge storage film, and wherein said channel forming region includes a first conductive type high concentration channel region with higher concentration than that in other regions of said channel forming region at least at an end portion on said second source/drain region side.