Patent ID: 7489263

Claim:
A discrete-time sampling circuit, comprising: an input terminal for receiving an input voltage; an amplifier having a feedback capacitor connected from an output of the amplifier to an input of the amplifier to form an integrator; a gain-setting capacitor for changing a gain at the output of the integrator with respect to the input signal; a reference feedback capacitor; and a switching circuit for coupling the reference feedback capacitor and the input gain-setting capacitor in parallel and between the input terminal and a reference voltage substantially equal to a common-mode voltage of the input terminal in a first clock phase, coupling the reference feedback capacitor between a feedback reference voltage source and the input of the amplifier in a second clock phase, and coupling the input gain-setting capacitor between a common-mode reference voltage source and the input of the amplifier in the second clock phase whereby at repetitions of the first clock phase, a charge placed on the reference feedback capacitor during the second clock phase substantially reduces the charge transferred from the input terminal during the first clock phase.