Patent ID: 7692987

Claim:
A semiconductor storage device comprising: a memory cell which stores data; a bit line connected to the memory cell; a first capacitor which supplies a charge to the memory cell; a first sense node thorough which a potential corresponding to data of the memory cell is transmitted; a first pre-charge part which is for charging the bit line, the first capacitor, and the first sense node; a first latch part which latches the data of the memory cell; a first sense part which includes a first sense transistor whose gate is connected to the first sense node, one of a source or a drain is connected to a power supply, and the other of them is connected to the first latch part; and a first clamp part which allows a first node between the first latch part and the first sense transistor to be connected to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting the data of the memory cell, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node.