Patent ID: 8878503

Claim:
A voltage regulator configured to generate on an output node a regulated voltage that is substantially a replica of a reference voltage provided on an input node of the regulator, comprising: a power stage driven by a control voltage and configured to generate the regulated voltage; a first error amplifier configured to generate the control voltage on an output terminal, and configured to receive the reference voltage on a first input terminal; a first feedback network connected between said output node of the voltage regulator and a second input terminal of the first error amplifier; a second feedback network connected between said output terminal of the first error amplifier and said second input terminal thereof; a current cancellation network input with the reference voltage and coupled to said second input of the error amplifier, configured to inject into said second input a unidirectional compensation current configured to compensate first and second currents of said first and second feedback networks, respectively, the compensation current being determined by at least one of time variations of a difference between a replica of the output regulated voltage and the reference voltage, and of time variations of the reference voltage; wherein said cancellation network comprises a second error amplifier configured to receive the reference voltage on a first input, a cascode stage configured to be biased in a conduction state and controlled by said second error amplifier and having a current terminal shorted to a second input of the second error amplifier, a third feedback network connected between said second input terminal of the second error amplifier and to at least one of said output of the voltage regulator and a node at a reference potential, and configured to generate a third current representative of at least one of a time derivative of the difference between the reference voltage and the output regulated voltage, and of the time derivative of the reference voltage, a mirroring network coupled between another current terminal of said cascode stage and said second input of the first error amplifier, configured to inject the third current into said second input of the first error amplifier when the third current assumes a predetermined sign.