Patent ID: 7759927

Claim:
A test apparatus for testing a device-under-test, comprising: a reference clock source for generating a reference clock; a clock regenerating circuit coupled to said reference clock source and generating, based on a phase adjusting signal to be inputted, a regenerated clock having a phase difference from said reference clock corresponding to said phase adjusting signal, said clock regenerating circuit including: a frequency divider which receives and divides said regenerated clock; and a phase comparator including a first input connecting to said frequency divider and a second input connecting to said reference clock source; a timing comparator coupled to said clock regenerating circuit for obtaining a value of an output signal outputted from said device-under-test based on said regenerated clock; a first phase comparing section coupled to said device-under-test and to said clock regenerating circuit, said first phase comparing section receiving said output signal outputted from said device-under-test and said regenerated clock from said clock regenerating circuit, comparing a phase of said output signal and a phase of said regenerated clock, and outputting an output signal representing a result of the phase comparison as said phase adjusting signal; a storage section for sequentially storing said phase adjusting signals per interval outputted from said first phase comparing section; an operating section that receives said phase adjusting signals and calculates a theoretical value of the phase differences between the reference clock and the regenerated clock based on said phase adjusting signals stored in said storage section, wherein said operating section calculates the theoretical value of the phase differences by storing in advance a transfer function and by converting the phase adjusting signal of digital value by using said transfer function; and a display section for displaying a graph of the theoretical value of said phase difference calculated by said operating section, wherein said display section selectively displays either the phase adjusting signal or the theoretical value of the phase difference based on an instruction of a user.