Patent ID: 8461698

Claim:
An integrated circuit assembly, comprising: a substrate, the substrate including a top layer circuit routing and an external dielectric layer on one of a top surface and a bottom surface, the external dielectric layer made of a solder mask; a die assembly, the die assembly being connected to the substrate, the die assembly including an integrated circuit chip, the integrated circuit chip having a first surface and a second surface, the first surface being disposed generally opposite the second surface, the first surface being oriented away from the substrate, the second surface being oriented towards the substrate, the second surface of the integrated circuit chip having configured thereon a plurality of solder bumps, the integrated circuit chip being connected to the substrate via the plurality of solder bumps, and an underfill configured between the integrated circuit chip and the substrate; and a conductive coating, the conductive coating at least substantially covering the external dielectric layer of the substrate and contacting the underfill, wherein the conductive coating forms an external ground plane of the substrate, the conductive coating including at least one of a nano-particle coating, a conductive organic polymer, a metallic-filled organic, or a ceramic material, the external dielectric layer configured to provide electrical isolation between the conductive coating and the top layer circuit routing.