Patent ID: 7024543

Claim:
A data processing apparatus comprising: a processor for executing a sequence of instructions, the processor having a first pipeline and a second pipeline, the processor routing an instruction in the sequence through either the first or the second pipeline dependent on predetermined criteria, each pipeline having a plurality of pipeline stages including a retirement stage; counter logic for maintaining a first counter relating to the first pipeline and a second counter relating to the second pipeline, and, for each instruction in the first pipeline, for making a determination as to when that instruction reaches a point within the first pipeline where an exception status of that instruction is resolved, and for incrementing the first counter responsive to said determination, the processor generating an indication within the second pipeline each time an instruction is routed to the first pipeline, and the counter logic for incrementing the second counter responsive to said indication; and synchronisation logic, when an instruction is in the retirement stage of the second pipeline, for determining with reference to the values of the first and second counters whether that instruction can be retired, and if the instruction can be retired the retirement stage causes an update of a state of the data processing apparatus dependent on the result of execution of that instruction.