Patent ID: 7711078

Claim:
A system for synchronizing a first frequency of a local clock signal with a second frequency of a reference clock signal, the system comprising: (a) a reference counter block comprising divide-by-N circuitry configured for successively dividing a number of received pulses of the reference clock signal by a value N equal to a predetermined reference value, and for successively producing therefrom a hit signal when the number of received pulses is the predetermined reference value; (b) a feedback counter block comprising resettable counter circuitry configured for receiving the local clock signal and the hit signals, for counting pulses of the local clock signal between successive received hit signals, and for producing a feedback count signal having a value corresponding to the count of the pulses of the local clock signal since the last hit signal; (c) adder circuitry configured for receiving the feedback count signal and a predetermined feedback value and for producing therefrom a count error signal representing the difference between the feedback count signal value and the predetermined feedback value; and (d) a controller block comprising circuitry configured for receiving the count error signal and the hit signals, the controller block being triggered by receipt of one of the hit signals, and producing a frequency adjust signal based on the count error signal, the frequency adjust signal being configured for use to synchronize the first frequency by increasing or decreasing the first frequency.