Patent ID: 8108648

Claim:
An integrated circuit comprising: an interconnect for the integrated circuit to communicate requests between multiple initiator intellectual property (IP) cores and multiple target IP cores coupled to the interconnect; an address map with assigned addresses for the target IP cores in the integrated circuit to route the requests between the target IP cores and initiator IP cores in the integrated circuit; and a memory scheduler coupled to a first target memory core of the target IP cores that includes a bank of memories, where the memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a first request to the first target memory core to determine what physical addresses in the bank of memories will service the first request, wherein the two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the first target memory core with each memory region having its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler, and the multiple tiling functions are configured to operate concurrently in the integrated circuit.