Patent ID: 7417288

Claim:
A semiconductor structure comprising: a substrate including at least one logic device region and at least one SRAM device region, said device regions are separated by an isolation region and said substrate is a fragment of a semiconductor-on-insulator comprising a bottom semiconducting layer and a buried insulating layer atop said bottom semiconducting layer; at least one double gated logic device within said at least one logic device region, wherein said at least one double gated logic device includes, from bottom to top, a back gate, a back gate dielectric, a body region, a front gate dielectric and a front gate, said body region of said logic device includes a doped channel; and at least one double gated SRAM device within said least one SRAM device region, wherein said at least one double gated SRAM device includes, from bottom to top, a back gate having a dopant concentration of about 1×10 20 atoms/cm 3 or greater, a back gate dielectric, a body region, a front gate dielectric and a front gate, said body region of said SRAM device includes a non-doped channel and said back gate of said SRAM device has a higher doping level that said back gate of said logic device, and wherein said back gate within said logic device region and said SRAM device region both have an n-type conductivity, said front gate within both said device regions has a p-type conductivity, said doped channel has said n-type conductivity.