Patent ID: 7259602

Claim:
Apparatus for implementing a fault tolerant phase locked loop (PLL) circuit comprising: a divide by N circuit providing an output feedback frequency signal; said divide by N circuit including a plurality of sub-divide by N functions; said divide by N circuit including compare and reload logic coupled to each said sub-divide by N function; each of said plurality of sub-divide by N functions including a counter circuitry and an N register storing a factor for dividing a received frequency signal; said compare and reload logic responsive to identifying a failed counter event, synchronizing said counter circuitry of said plurality of sub-divide by N functions; a voter circuit coupled to said plurality of sub-divide by N functions; each of said sub-divide by N function providing a feedback frequency signal applied to a voter circuit; and said voter circuit providing said output feedback frequency signal based upon a majority vote of the sub-divide by N functions.