Patent ID: 7429963

Claim:
An image processing device comprising: a frame buffer for storing therein digital image data; a first display engine in communication with said frame buffer for processing said digital image data into pixel digital data comprising an image data portion and a display control portion, said display control portion including a vertical synchronization bit, a horizontal synchronization bit and a data active bit; a clock signal generator in communication with said first display engine for generating a working clock signal required for operations of said first display engine; a spread spectrum clock generator in communication with said clock signal generator for generating a spread spectrum clock signal in response to said working clock signal; a first-in-first-out (FIFO) buffer in communication with said first display engine, said clock signal generator and a planar display for receiving and storing said pixel digital data from said first display engine according to a data writing index controlled by said working clock signal and outputting said pixel digital data to said planar display according to a data reading index controlled by said spread spectrum clock signal; and a reset signal generator in communication with said first display engine and said FIFO buffer for receiving and checking said pixel digital data and generating a reset signal to said FIFO buffer to reset said data writing index and said data reading index when one of said pixel digital data to be inputted into said FIFO buffer is consistent with a preset condition; wherein said preset condition is satisfied when said vertical synchronization bit, horizontal synchronization bit and data active bit are “1”, “0” and “0” or “0”, “0” and “0”, respectively, and all image data bits included in said image data portion are “0 ”.