Patent ID: 8638884

Claim:
A data processing unit for a receiver of signals carrying data, said data processing unit comprising: clock and data recovery circuitry, which is clocked by a local clock signal and which includes a numerical phase lock loop, in which there is a numerically controlled oscillator, which generates as output at least one pulse signal, the phase and frequency of which are adaptable based on a data signal received at an input of the clock and data recovery circuitry, and processor circuitry connected to the clock and data recovery circuitry, wherein the processor circuitry is configured to calculate the mean and variance over time of a numerical input signal of the numerically controlled oscillator so as to determine coherence of the data signal when the calculated mean and variance are below a predefined coherence threshold, and to perform a reset of the receiver when the calculated mean and variance of the numerical input signal of the numerically controlled oscillator are above the predefined coherence threshold, wherein the numerically controlled oscillator supplies the output as an in-phase pulse signal and a quadrature pulse signal, wherein the numerical phase lock loop includes a clock counter, which receives the data signal as an input and which is clocked by the local clock signal to oversample the data signal, and wherein the clock counter is configured to be reset at a reset input at each pulse of the quadrature pulse signal supplied by the numerically controlled oscillator, and an output signal value of the clock counter at a time of reset following a binary transition of the data signal enables the numerically controlled oscillator to be adapted.