Patent ID: 8055964

Claim:
A semiconductor device, comprising: a plurality of scan chains for testing a plurality of clock domains whose operating frequencies are different from one another, each of the plurality of scan chains including a plurality of flip-flop circuits; a clock oscillator which generates a plurality of clock signals corresponding to respective operating frequencies that are used to test the plurality of clock domains; a scan clock signal input circuit which receives, from an outside, a scan clock signal that is supplied to the plurality of scan chains; a pulse generation circuit unit which generates a clock pulse signal used for the testing based on the clock signals and the scan clock signal, the pulse generation circuit unit including a plurality of pulse generation circuits corresponding to respective operating frequencies; a clock control circuit unit which selectively activates a part of a pulse generation circuit in the pulse generation circuit unit, the clock control circuit including a plurality of logic circuits corresponding to the plurality of scan chains, respectively; and a clock control signal generation unit which generates a clock control signal to control the clock control circuit unit, based on the scan clock signal, wherein a number of the scan clock signal input circuit is fewer than a number of the plurality of clock domains.