Patent ID: 7884423

Claim:
A complementary semiconductor device comprising: an n-channel type first MISFET; and a p-channel type second MISFET, the n-channel type first MISFET comprising: a first gate insulating film placed on a semiconductor substrate surface; a first metal oxide layer placed on the first gate insulating film, and having a composition ratio shown with M1xM2yO (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr, or Ta, and x/(x+y)>0.12); a second metal oxide layer placed on the first metal oxide layer; and a first conductive layer placed on the second metal oxide layer, the p-channel type second MISFET comprises: a second gate insulating film placed on the semiconductor substrate surface; a third metal oxide layer placed on the second gate insulating film, and having a composition ratio shown with M3zM4wO (where M3=Al, M4=Hf, Zr, or Ta, and z/(z+w)>0.14); a fourth metal oxide layer placed on the third metal oxide layer; and a second conductive layer placed on the fourth metal oxide layer.