Patent ID: 7791634

Claim:
A pixel clock generator comprising: a multiphase clock generator that generates multiphase clocks in which phases are mutually shifted from each other by a phase difference T/P, where T is a cycle and P is number of the phases; a comparator that detects a time interval between a first synchronization signal and a second synchronization signal, compares the detected time interval with a target value, and outputs an error between the detected time interval and the target value; a frequency calculator that calculates a set value of a pixel clock frequency based on the error output from the comparator, and outputs a frequency specification signal for specifying the pixel clock frequency based on a calculated set value; a counting unit that sets the phase difference T/P as a unit time based on the frequency specification signal, and calculates a rising time and a falling time of the pixel clock by counting number of the unit times; a pixel clock output unit that generates the pixel clock based on the rising time and the falling time of the pixel clock calculated by the counting unit, with reference to the multiphase clocks; and a frequency divider that generates an internal clock in which one of the multiphase clocks is divided by Q, where Q a positive integer, wherein the counting unit calculates the rising time and the falling time by counting based on the internal clock generated by the frequency divider and by calculating addition or subtraction of a fraction that is below a cycle of the internal clock.