Patent ID: 8878337

Claim:
An integrated circuit structure, comprising: a first area comprising at least one first type device that has a metal layer and a dielectric layer; a second area comprising at least one second type device that has a metal layer and a dielectric layer; wherein the metal layer of the first area has a first surface that defines a first plane, the metal layer of the second area has a second surface that defines a second plane, the dielectric layer of the first area has a third surface that defines a third plane, and the dielectric layer of the second area has a fourth surface that defines a fourth plane; and a third area comprising at least one capacitor having an uppermost layer of polysilicon that has a surface that defines a fifth plane, and the capacitor having a dielectric layer that has a surface that defines a sixth plane, wherein the first, second, and fifth planes are coplanar and the third, fourth, and sixth planes are coplanar, wherein an area of the layer of polysilicon is greater than a sum of areas of the metal layers in the first and second areas, and wherein the third area is distributed among the first and second areas.