Patent ID: 8355287

Claim:
A method for operating of NAND-like dual charge retaining transistor NOR flash memory cell comprises the steps of: providing the NAND-like dual charge retaining transistor NOR flash memory cell wherein the NAND-like dual charge retaining transistor NOR flash memory cell comprises: a pair of charge retaining transistors connected serially such that a source of a first charge retaining transistor of the pair of charge retaining transistors is connected to solely to a drain of a second charge retaining transistor of the pair of charge retaining transistors; receiving a pair of external input data bits; erasing the NAND-like dual charge retaining transistor NOR flash memory cell to an erased threshold voltage level; keeping the first charge retaining transistor of the pair of charge retaining transistors at the erased threshold voltage level when a first input data bit of the pair of input data bits is a first datum; programming the first charge retaining transistor of the pair of charge retaining transistors to a first programmed threshold voltage level when the first input data bit of the pair of input data bits is a second datum; keeping the second charge retaining transistor of the pair of charge retaining transistors at the erased threshold voltage level when a first input data bit and second input data bit are the second datum; programming the second charge retaining transistor of the pair of charge retaining transistors to the first programmed threshold voltage level when the first data bit of the pair of input data bits and a second data bit of the pair of input data bits have unequal states of the first and second data; and programming the second charge retaining transistor to a second programmed threshold voltage level when the pair of input data bits are the first datum to prevent excess leakage current.