Patent ID: 8359558

Claim:
A design optimization method for a target circuit design including cells specified by a machine-readable file, comprising: executing, using a computer system, for a cell having an initial form, a cell modification procedure to modify a characteristic of the cell to produce a modified cell; determining a characteristic of an event in cell switching behavior of the modified cell, where changes in the characteristic of the event correlate with changes in delay of the cell due to the modification procedure, wherein the event is a transition in a cell switching behavior from a first region in which one behavior dominates the cell switching to a second region in which another behavior dominates cell switching, wherein the first region is a short circuit behavioral region including competing pull-up and pull-down currents, and the second region is a current flow region dominated by one of pull-up and pull-down currents affecting an output of the cell, wherein the characteristic of the event is a value of voltage V SC , where V SC is equal to an output voltage for the modified cell, and the event is a point at which an input voltage V in crosses outside a short circuit behavioral range, in which range of the input voltage V in is between thresholds for the first and second regions according to a computer-implemented model of cell switching behavior; and determining a value for delay of the modified cell as a function of the determined characteristic of the event.