Patent ID: 7328330

Claim:
A method for managing single instruction multiple data (SIMD) instructions and general purpose (GP) instructions within a processor, the method comprising: configuring a first logic unit of an instruction unit to: receive GP instructions and SIMD instructions; decode the GP instructions and the SIMD instructions; check the GP instructions for dependencies; resolve any dependencies in the GP instructions; unconditionally stall subsequent SIMD instructions until all pending GP instruction dependencies are resolved; provide GP instructions that are free of dependencies to a GP unit for execution; subsequent to providing the GP instructions that are free of dependencies to the GP unit, provide the SIMD instructions to the second logic unit; configuring a second logic unit of the instruction unit to, subsequent to providing, by the first logic unit, the GP instructions that are free of dependencies to the GP unit: receive the SIMD instructions from the first logic unit; check the SIMD instructions for dependencies; resolve any dependencies in the SIMD instructions; and provide the SIMD instructions that are free of dependencies to a SIMD unit for execution.