Patent ID: 7225105

Claim:
A performance monitor for monitoring an occurrence of incidences of one or more events related to operation of a processor, comprising: at least one monitor mode control register; and a plurality of performance monitor counters operatively connected to said at least one monitor mode control register to count incidences of said one or more events, said at least one monitor mode control register grouping said performance monitor counters so that when one of said performance monitor counters reaches capacity in connection with the counting incidences of a first of said one or more events, a second of said performance monitor counters begins counting subsequent incidences of said first of said one or more events; wherein the number of events equals X, and the number of performance monitor counters equals Y, whereby said at least one monitor mode control register groups said performance monitor counters into Z groups, wherein Y/X=Z; and wherein when X<Y, said at least one monitor mode control register assigns a number of performance monitor counters, said number of performance monitor counters equal to an integer resulting from dividing Y by X, to each of said events to be counted; and wherein said at least one monitor control register assigns any unassigned performance monitor counters to at least one of said events.