Patent ID: 8343818

Claim:
A method of forming an electrical device comprising providing a substrate having a dielectric layer located on the substrate and having a semiconductor layer located on the dielectric layer; forming at least one semiconductor device on the semiconductor layer, wherein a gate structure of the at least one semiconductor device is present on a second surface of the semiconductor layer that is opposite a first surface of the semiconductor layer that is in contact with the dielectric layer, and source regions and drain regions are formed in contact with portions of the semiconductor layer that are adjacent to a portion of the semiconductor layer that is in contact with the gate structure; forming a handling structure on the at least one semiconductor device and the second surface of the semiconductor layer; removing the substrate and at least a portion of the dielectric layer; forming a retrograded well through the first surface of the semiconductor layer, wherein the retrograded well extends to a thickness from the first surface of the semiconductor layer that is opposite the second surface of the semiconductor layer that the gate structure is present on, wherein the retrograded well does not extend to contact the gate structure; forming a buried dielectric layer positioned on the first surface of the semiconductor layer; removing at least a portion of the handling structure; and activating the retrograded well.