Patent ID: 8370565

Claim:
A boot system of an electronic device, comprising: a central processing unit (CPU); a NAND flash electronically connected with the CPU; a synchronous dynamic random access memory (SDRAM) electronically connected with the CPU; and a pulse count unit electronically connected with the CPU and the NAND flash, the pulse count unit comprising a counter, an AND gate, a first NOT gate, and a second NOT gate; wherein the counter comprises count pins 0 - 7 , the AND gate comprises three input pins and an output pin, the count pins 0 and 1 are electronically connected with two input pins of the AND gate; the count pins 2 is electronically connected with other input pin of the AND gate through the first NOT gate; the count pin 3 is electronically connected with the second NOT gate, and the count pin 5 is electronically connected with the NAND flash; wherein the pulse count unit initializes and enables the NAND flash; and wherein the CPU reads a pre-boot loader stored in the NAND flash and loads the pre-boot loader in the SDRAM to boot the electronic device.