Patent ID: 7994822

Claim:
A semiconductor device comprising: a first LSI having a plurality of first flip-flops, to which a first clock signal is supplied, and a first logic circuit connected between the plurality of first flip-flops; and a second LSI formed on a chip different from a chip of the first LSI and having a plurality of second flip-flops, to which a second clock signal is supplied, and a second logic circuit connected between the plurality of second flip-flops, wherein the first LSI and the second LSI are stacked in one semiconductor package; the first LSI transmits data to the second LSI based on the first clock signal; the second LSI receives the data transmitted from the first LSI based on the second clock signal; the second clock signal is controlled so as to be synchronized with the first clock signal; the first clock signal of the first LSI is transmitted to the second LSI through a first through-electrode that mutually electrically connects the first and second LSIs, the first through-electrode being provided to penetrate the second LSI; the second LSI has a first DLL circuit; and the first DLL circuit controls a phase of the second clock signal based on the first clock signal supplied via the first through-electrode.