Patent ID: 7763924

Claim:
A dynamic random access memory (DRAM) structure, comprising: a substrate; a recessed-gate transistor disposed in the substrate; a word line disposed on and electrically connected to the recessed-gate transistor; a trench capacitor structure disposed in the substrate and electrically connected to the recessed-gate transistor; a first conductive structure disposed on and in direct contact with an electrode of the trench capacitor structure, wherein the first conductive structure has a central axis that is coaxial with a central axis of the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to each other to serve as a common electrode; and a bit line disposed above and electrically connected to the recessed-gate transistor, wherein a top of the bit line is lower than a top of the word line.