Patent ID: 7945763

Claim:
A method of predecoding instructions for execution in a multi-core processor, comprising: receiving a first line of complete instructions for execution by a first processor core of the multi-core processor, wherein the first processor core comprises a cascaded delayed execution pipeline unit having at least first and second execution pipelines, wherein instructions in a common issue group issued to the cascaded delayed execution pipeline unit begin execution in the first execution pipeline before the second execution pipeline, and wherein at least the first execution pipeline comprises circuitry for forwarding results of a first instruction from a first issue group to an execution unit in one of the first pipeline and the second pipeline, wherein the execution unit is executing a second instruction from a second issue group; predecoding the first line of complete instructions with a shared predecoder; sending the predecoded first line of complete instructions from the shared predecoder to the first processor core for execution in the cascaded delayed execution pipeline; receiving a second line of complete instructions for execution by a second processor core of the multi-core processor; predecoding the second line of complete instructions with the shared predecoder; sending the predecoded second line of complete instructions from the shared predecoder to the second processor core for execution; receiving a third line of instructions for execution by a third processor core; determining whether to predecode the third line of instructions, based on whether an instruction cache miss has occurred for the third line of instructions and whether at least one schedule flag associated with the third line of instructions has changed; upon determining to predecode the third line of instructions: predecoding the third line of instructions with the shared predecoder; and sending the predecoded third line of instructions from the shared predecoder to the third processor core for execution; and upon determining not to predecode the third line of instructions: sending the predecoded third line of instructions from the shared predecoder to the third processor core for execution without predecoding.