Patent ID: 7865860

Claim:
A layout design device for designing layout of an integrated circuit, comprising a routing section for adjacently wiring a first signal line having a high activity rate and a second signal line having a low activity rate based on an activity rate of the signal line of each circuit element, wherein the activity rate is determined by logic simulation or by clock definition, wherein the first signal line connects a first circuit component to a second circuit component, the second circuit component being different than the first circuit component, wherein the second signal line connects a third circuit component to a fourth circuit component, the third circuit component being different than the second circuit component and the first circuit component, the fourth circuit component being different than the third circuit component, the second circuit component, and the first circuit component, and wherein the routing section adjacently wires the first signal line and the second signal line without regards to which circuit components the first signal line interconnects and without regards to which circuit components the second signal line interconnects.