Patent ID: 7554870

Claim:
A dynamic random access memory (DRAM), comprising: a plurality of rows of memory cells, each of the memory cell rows being arranged into columns, wherein each of the memory cell rows is crossed by a row of four word lines, and wherein each of the columns is crossed by a bit line; a plurality of sense amplifiers corresponding to the bit lines such that a single sense amplifier corresponds to every four bit lines; and a plurality of 4:1 multiplexers corresponding to the plurality of sense amplifiers, each 4:1 multiplexer selectively coupling its corresponding sense amplifier to its corresponding four bit lines; wherein each sense amplifier includes: a differential amplifier adapted to amplify an input voltage difference (V P -V N ) between a pair of bit lines selected by the corresponding 4:1 multiplexer, wherein a first one of the bit lines is charged to the voltage V P and a second one of the bit lines is charged to the voltage V N , the differential amplifier amplifying the input voltage difference according to a gain G so as to drive an output voltage difference (V PO -V NO ) between a pair of output nodes, wherein a first one of the output nodes is charged to the voltage V PO and a second one of the output nodes is charged to the voltage V NO , the differential amplifier having a non-zero offset bias voltage (ΔV) such that if the input voltage difference is zero, the output voltage difference is non-zero; and a self-bias generation circuit adapted to couple the first output node to the second bit line such that the output voltage V PO equals the input voltage V N and to couple the second output node to the first bit line such that the output voltage V NO equals the input voltage V P ,the offset bias voltage ΔV thereby being reduced responsive to the gain G.