Patent ID: 7274583

Claim:
A memory system having a multi-drop bus structure comprising: a bus line; a connector connected to a bus line; a memory controller in which a port connected to the bus line is terminated by a resistor having a second impedance value; and a memory module connected to the connector and having at least one memory chip and a termination resistor in the memory chip, wherein the memory module comprises: a first load connected to the connector; a second load connected to the first load and having a first impedance value; a first chip in which a port connected to the second load is terminated by a resistor having the first impedance value; a via hole penetrating a printed circuit board of the memory module between the first load and the second load; a third load connected to the via hole and having the first impedance value; and a second chip in which a port connected to the second load is terminated by a resistor having the first impedance value, wherein the first load, the second load, and the first chip are formed on a first surface of the memory module while the third load and the second chip are formed on a second surface thereof, and a property impedance of a wire to which the memory chip is connected has the first impedance value.