Patent ID: 8112698

Claim:
A diversity baseband processing system for iteratively decoding received multipath signals arriving at multiple antennas of a Multiple Input/Multiple Output (MIMO) system, the baseband processing system comprising: at least two soft decision decoders adapted to receive soft data associated with corresponding signal paths, wherein the at least two soft decision decoders are serially coupled and have at least a first soft decision decoder and a last soft decision decoder, wherein the last soft decision decoder is adapted to output soft data for the serially coupled series of soft decision decoders in iterative mode, and wherein each soft decision decoder further comprises: a branch metric module adapted to receive soft input signal and configured to compute branch metric values for each branch in a Trellis by calculating a Euclidean distance for each branch; a branch metric memory module coupled to the branch metric module and adapted to store data associated at least with the branch metric values; a state metric module coupled to the branch metric memory module and configured to compute state metric values for each state in the Trellis using the computed branch metric values; a state metric memory module coupled to the state metric module and adapted to store data associated at least with the state metric values; a log-likelihood ratio (LLR) computation module coupled to at least the branch metric memory module and the state metric memory module, and configured to compute a soft decision output based at least on the branch metric values and the state metric values; a control logic state machine module adapted to utilize sliding windows on at least one of the branch metric module, the branch metric memory module, the state metric module, the add-compare-select circuit, the state metric memory module, and the computation module; and an add-compare-select circuit coupled to the state metric module and configured to compute state metric values at each node in the Trellis, wherein the add-compare-select circuit further comprises: a first adder for computing the sum of a first state metric value and a first branch metric value; a second adder for computing the sum of a second state metric value and a second branch metric value; a comparator for comparing the results of the first adder and the results of the second adder; and a multiplexer for selecting a larger sum for a predetermined state; at least one memory module electrically coupled to an output of a corresponding soft decision decoder, wherein the output of the memory module associated with the last soft decision decoder is fed back as an input to the first soft decision decoder of each of the at least two decoders, and wherein at least one memory module comprises an interleaver memory having an interleaver that generates a write address sequence for a memory core in a write mode; and at least a hard decoder arranged to perform hard decoded output for the baseband processing system.