Patent ID: 8610172

Claim:
A method of fabricating a complementary metal oxide semiconductor (CMOS) circuit, comprising the steps of: providing a wafer having a first semiconductor layer on an insulator, wherein the first semiconductor layer comprises germanium; using shallow trench isolation to divide the first semiconductor layer into at least two portions, one of which serves as a first active region of the circuit and another of which serves as a second active region of the circuit; forming a hardmask covering the second active region; recessing the first semiconductor layer in the first active region using a series of oxidation and oxide strip steps to incrementally reduce a thickness of the first semiconductor layer in the first active region; epitaxially growing a second semiconductor layer on the first semiconductor layer that has been recessed in the first active region, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element; removing the hardmask after epitaxially growing the second semiconductor layer such that the hardmask serves to mask the second active region while both the step of recessing the first semiconductor layer and the step of epitaxially growing the second semiconductor layer are being performed; forming an n-channel field effect transistor (n-FET) in the first active region using the second semiconductor layer as a channel material for the n-FET; and forming a p-channel field effect transistor (p-FET) in the second active region using the first semiconductor layer as a channel material for the p-FET.