Patent ID: 8395139

Claim:
A memory structure, comprising: an active area of a semiconductor substrate, surrounded by first isolation trenches extending along a first direction and second isolation trenches extending along a second direction; a bit line trench recessed into the active area of the semiconductor substrate, wherein the bit line trench extends along the second direction and intersect the first isolation trenches; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench, wherein the word line trench extends along the first direction and intersect the second isolation trenches, and wherein the bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions; a bit line embedded in the bit line trench; a word line embedded in the word line trench; a vertical transistor built in each of the pillar-shaped sub-regions; and a resistive memory element electrically coupled to the vertical transistor.