Patent ID: 6865701

Claim:
A semiconductor chip, comprising: a) a multi-ported memory having a plurality of data input ports; b) a controller to execute test commands to test said multi-ported memory; and, c) an interface circuit to interface said data input ports to both said controller and a system that uses said memory, said interface circuit comprising a group of three circuit paths for each one of said memory input ports, each circuit path of said group of three circuit paths to transport data to be written into said memory, each said group of three circuit paths comprising: i) a first circuit path that flows from said system to a data input port that said first circuit path's group of three circuit paths are associated with, said first circuit path to transport data provided by said system; ii) a second circuit path that flows from said controller to said data input port, said second circuit path to transport first test data provided by said controller; iii) a third circuit path that flows from said controller to register circuitry and from said register circuitry to said data input port, a portion of said third circuit path that precedes said register circuitry to transport second test data provided by said controller, a portion of said third circuit path that follows said register circuitry to transport said second test data after it has already been transported into said memory by another group's second circuit path.