Patent ID: 7453300

Claim:
A multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) flip-flop comprising: a first stage charging or discharging an internal node in response to an input data signal, a clock signal, and a sleep signal activated in a sleep mode; and, a second stage charging or discharging an output node in response to a signal apparent at the internal node, the clock signal, and a combination of the clock signal and the sleep signal, and storing an output data signal generated by charging or discharging the output node; wherein the first stage comprises: a clock delay unit delaying the clock signal in an active mode; a first leakage break transistor comprising a NMOS transistor having a low threshold voltage, being connected to a virtual ground, being gated by an output signal from the clock delay unit, and being turned off in response to an activated sleep signal, thereby breaking a leakage current path during sleep mode; a first charge path charging the internal node to a logic level “high”; and, a first discharge path discharging the internal node to a logic level “low”, wherein the first discharge path comprises the first leakage break transistor inactivating the first discharge path in response to the output signal of the clock delay unit in sleep mode; wherein the second stage comprises an output latch unit storing the output data signal; wherein the output latch unit comprises cross-coupled inverters; and, wherein each of the cross-coupled inverters comprises a transistor having a high threshold voltage.