Patent ID: 7552161

Claim:
An apparatus, comprising; a multiplexing device comprising M R , M R >1, input terminals each receiving one of M R input data streams supplied in parallel, and an output terminal at which the M R input data streams are output in a multiplexed manner; a fast fourier transformation device configured to perform fast fourier transformation of a data stream supplied at an input terminal thereof and to output the fast fourier transformation transformed data stream at an output terminal thereof, the input terminal of the fast fourier transformation device being connected to the output terminal of the multiplexing device; and a demultiplexing device comprising an input terminal connected to the output terminal of the fast fourier transformation device and M R output terminals at which a respective one of M R transformed output data streams is output in a demultiplexed manner, wherein each of the M R input data streams contains a number of N=2 k samples, the fast fourier transformation device has a pipeline architecture composed of k stages with a respective feedback path including a single delay element per each stage of the pipeline architecture and is controlled by a first and second internal control signals, the delay element in a feedback path of an i th stage, l<=i<=k, of the pipeline architecture imposes a delay of M R *N/2 i samples, the first internal control signal is clocked M R times faster compared to a clock rate at which the samples of the M R streams are supplied, and the second internal control signals are clocked M R times slower compared to the first internal control signal).