Patent ID: 6839811

Claim:
A circuit, comprising: a register which stores therein a semaphore address; a semaphore control circuit which asserts a control signal in response to a read access by a processor directed to the semaphore address, and negates the control signal in response to a write access by the processor directed to the semaphore address, and a bus-arbitration control circuit which receives a signal indicative of a bus-arbitration request, the control signal, and a chip enable signal output from the processor, and wherein other resources are prohibited from accessing the semaphore address when the control signal is asserted, and a right to use a bus given to the processor is not relinquished in response to the bus-arbitration request supplied from an external source during an asserted state of the control signal, and said bus-arbitration control circuit operating not to assert a bus-arbitration-acknowledge signal in response to the bus-arbitration request signal regardless of a state of the chip enable signal when the control signal is in the asserted state, operating not to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in an asserted state and the control signal is in a negated state, and operating to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in a negated state and the control signal is in the negated state.