Patent ID: 8458560

Claim:
A system for the efficient parallel implementation of a burst error correction code, comprising: error trapping circuitry calculating a first syndrome of a Fire Code and configured to find an error pattern and a starting location of an error burst within a data word of a plurality of data words comprising a full code word; error location circuitry calculating a second syndrome of the Fire Code and configured to find the data word of the plurality of data words that holds the starting location of the error burst, wherein the error location circuitry comprises circuitry configured to perform Galois Field arithmetic to align a starting location of the error burst based on the error trapping circuitry; and error correction circuitry configured to correct the error burst; wherein the error trapping circuitry and first syndrome are implemented parallel to the error location circuitry and the second syndrome; wherein Syndrome Computation, Error Trapping and Syndrome Normalization, and Error Correction are performed simultaneously using the parallel implementation; wherein an input data stream is received simultaneously at the error trapping circuitry, the error location circuitry, and a first-in-first-out block; and wherein, as an output of the first-in-first-out block is being read, an output of the error trapping circuitry is compared to an output of the error location circuitry, and: if the output of the error trapping circuitry and the error location circuitry are equal, then an error location has been found and the output of the error trapping circuitry is shifted; and if the output of the error trapping circuitry and the error location circuitry are not equal, then the output of the error location circuitry is multiplied by a normalization multiplier.