Patent ID: 6937173

Claim:
A serializer for transforming N (where N is a natural number greater than 2) parallel data into a serial data stream using N clock signals each having different phase to output the serial data stream, the serializer having N stages, each of the stages coupled in parallel, each of the stages comprising: a logic section for receiving i-th data of the N parallel data and outputting the i-th data (where i is a natural number less than or equal to N) or inverted i-th data in response to an active status or an inactive status of a j-th clock signal (where j is a natural number less than or equal to N) of the N clock signals; and a first inverter for receiving the i-th data or the inverted i-th data from the logic section, and for inverting the i-th data or the inverted i-th data to output a first output signal.