Patent ID: 7589988

Claim:
An analog sampler ( 1 ) for continuous recording and read-out of analog data relative to a signal comprising: at least one write analog bus ( 5 , 5 a , 5 b ) carrying the signal to be recorded; at least one read analog bus ( 4 , 4 a , 4 b ) carrying the recorded signal and directing it towards read outputs ( 101 ), a matrix array ( 10 ) for capturing, recording and reading cells ( 2 ) arranged in L rows ( 13 ) or pairs of lines and C columns ( 12 ), L and C designating positive integer numbers, each one of the cells ( 2 ) having at least one analog input ( 3 , 3 a , 3 b ) coupled with said at least one write analog bus ( 5 , 5 a , 5 b ), at least one write control digital input ( 23 , 23 a , 23 b ), at least one read control digital input ( 26 , 26 a , 26 b ), and at least one analog output ( 103 , 103 a , 103 b ) linked to the read analog bus ( 4 , 4 a , 4 b ), each of the columns ( 12 ) having one column input ( 8 - 1 ) coupled with at least one write digital input ( 11 - 1 ) of each cell ( 2 ) of said column ( 12 ); a shift register ( 6 ) having one input ( 7 ) for receiving a clock signal, one input ( 104 ) to initialize it and a plurality of shifted outputs ( 8 ) coupled to the column inputs ( 8 - 1 ) of the matrix array ( 10 ); the sampler comprising for each column ( 12 ), an associated delay line ( 9 ) having one input ( 8 - 1 ) of the delay line ( 9 ) and successive shifted outputs ( 11 ) in number equal to or greater than the number L of matrix array rows ( 13 ), the input ( 8 - 1 ) of the delay line ( 9 ) constituting the column input, the column input ( 8 - 1 ) being coupled with each one of the write digital inputs ( 11 - 1 ) of the column cells ( 2 ) by the intermediary of said delay line ( 9 ), each output ( 11 ) of the delay line being coupled respectively to one of the at least one write digital inputs ( 11 - 1 ) of a cell ( 2 ) of said column ( 12 ), analog sampler ( 1 ) characterized in that it comprises means ( 116 , 113 ) permitting to apply simultaneously to the writing of a column ( 12 ) a read command to all the read digital inputs ( 26 ) of the cells ( 2 ) of a read column, said read column being a column ( 12 ) which during its reading duration does not comprise any cell ( 2 ) in the course of being written, said means ( 116 , 113 ) comprising means of synchronization between the arrival of the write column pointer signal on a column input ( 8 - 1 ) and the application of the read command to the read digital inputs ( 26 ) of the cells ( 2 ) of a read column ( 12 ).