Patent ID: 8310881

Claim:
A semiconductor device comprising: a plurality of terminals, each terminal being configured to receive similar data during a test mode; a plurality of buffers, each buffer being configured to receive data from a corresponding terminal and output either the data or changed data to a corresponding memory cells in response to a control signal; and a control unit configured to generate a plurality of control signals, each control signal being respectively applied to a corresponding buffer, wherein each of the plurality of buffers comprises: a first switch configured to receive the data and be turned ON/OFF in response to a corresponding one of the plurality of control signals; a buffering unit configured to pass the data received from the first switch without changing a logic state of the data; a second switch configured to receive the data and be turned ON/OFF in response to the corresponding one of the plurality of control signals; and an inversion unit configured to invert the logic state of the data received from the second switch and pass the inverted data as changed data.