Patent ID: 8466050

Claim:
A method for forming a MOS device comprising: providing a semiconductor substrate, the semiconductor substrate comprising a surface region; forming a gate dielectric layer overlying the surface region of the semiconductor substrate; forming a gate layer overlying the gate dielectric layer; patterning the gate layer to form a gate structure including a first edge and a second edge, the gate structure having a width of 90 nanometers and less; and concurrently implanting a first dose of a selected species at a first depth with a first energy and a second dose of the selected species at a second depth with a second energy using the gate structure as a mask to form a lightly doped drain (LDD) region, the first depth being a predetermined first depth from the surface region, the second depth being a predetermined second depth from the surface region; wherein the first energy is different from the second energy; wherein the first and second doses are implanted at a same incident angle relative to the surface region of the semiconductor substrate.