Patent ID: 7428631

Claim:
An apparatus comprising: a storage structure to store at least one entry, the at least one entry to include a register identifier value; a first physical rename register of a first length; a second physical rename register of a second length different than the first length, wherein the first and second rename registers are distinct from each other and do not share any common bits; a logical register; and rename logic to map an instance of the logical register to a selected physical rename register, where the selected physical rename register is selected from a plurality of registers comprising the first physical rename register and the second physical rename register; wherein the register identifier value is to indicate a current length, wherein the current length is selected from a set including the first length and the second length; wherein the logical register includes a plurality of x bit positions; wherein a selected one of the x bit positions may be accessed individually responsive to a first instruction that indicates the selected bit position; wherein all x bit positions may be accessed together responsive to a second instruction; and the rename logic is further to allocate the first physical rename register responsive to the first instruction, the rename logic further to allocate the second physical rename register responsive to the second instruction.