Patent ID: 6867095

Claim:
A method for fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate in which a transistor consisting of a gate electrode, and source/drain regions was formed, the gate electrode having a spacer formed on its sidewall; forming a first bit-line contact plug and a storage node contact plug on the source/drain regions, respectively, forming a first insulating layer on the resulting structure; polishing the first insulating layer by CMP until the first bit-line contact plug and the storage node contact plug are exposed; forming a second bit-line contact plug and a storage node on the first bit-line contact plug and the storage node contact plug, respectively; sequentially forming a capacitor insulating layer and a plate node on the resulting structure including the second bit-line contact plug and the storage node; forming a second insulating layer on the entire surface of the substrate including the plate node; selectively etching a portion of the second insulating layer, a portion of the plate node and a portion of the capacitor insulating layer, to form a bit-line contact hole exposing the second bit-line contact plug; and forming a bit-line in the bit-line contact hole and on the second insulating layer.