Patent ID: 6841471

Claim:
A fabrication method of a semiconductor device, comprising the steps of: forming an interlayer dielectric film over an entire structure including a lower metal line formed over a semiconductor substrate; forming on the interlayer dielectric film a barrier layer having an etching rate that is lower than an etching rate of the interlayer dielectric film, and selectively etching the barrier layer to expose a predetermined region of the interlayer dielectric film corresponding to where a via is to be formed; forming a photoresist pattern on the barrier layer having an opening of a predetermined area corresponding to the exposed region of the interlayer dielectric film and to where a line opening is to be formed, the opening of the photoresist pattern having an area that is greater than an area of the exposed region of the interlayer dielectric film such that a region of the barrier layer adjacent to the exposed region of the interlayer dielectric film is exposed; simultaneously forming the line opening and the via by etching the exposed regions of the barrier layer and the interlayer dielectric film dielectric film using the photosensitive film pattern as a mask; and forming a metal plug by filling the line opening and the via with a metal material.