Patent ID: 7788556

Claim:
An apparatus for evaluating an erroneous state associated with a target circuit, comprising: a partitioned ordered binary decision diagram (POBDD) data structure comprising logic encoded on a first computer-readable storage medium, the POBDD data structure operable to receive information associated with a target circuit, the information identifying a property within the target circuit to be verified, the POBDD data structure executing one or more operations in order to identify an erroneous state associated with a sub-space within the target circuit; and an auxiliary data structure comprising logic encoded on a second computer-readable storage medium, the auxiliary data structure operable to: store a trace record comprising one or more computations, one or more communications between at least two partitions, and one or more time intervals associated with the one or more communications; and identify a path associated with the erroneous state, the path reflecting a correlation between an initial state associated with the erroneous state and a point where the erroneous state was encountered by the POBDD data structure.