Patent ID: 8245105

Claim:
A hub device comprising: an interface to a high speed bus for communicating with a memory controller, the memory controller and the hub device included in a cascade interconnect memory system and the high-speed bus including bit lanes and one or more clock lanes; a bi-directional fault signal line in communication with the memory controller and readable by a service interface; a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures; and error recovery logic for responding to a failure detected at the hub device, the responding including: recording a severity level of the failure in the FIR; and taking an action at the hub device that is responsive to the severity level of the failure, the action including one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane, wherein the severity level is fault and the hub device notifies the memory controller of the failure via the fault signal line, preserves contents of internal latches and memory devices in response to the hub device operating in a slow clock mode, asserts fences and turns off logical clocks.