Patent ID: 8076979

Claim:
A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal, comprising: a first counter that outputs a first counter value indicative of a number of clock cycles of the reference signal; a second counter that outputs a second counter value indicative of a number of clock cycles of the feedback signal; an asynchronous comparator connected to the first and second counters and receives the first and second counter values and generates a comparator output signal having a pulse width that is proportional to the difference between the first and second counter values; a pulse width detector, connected to the comparator, that receives the comparator output signal and generates an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value; and a state machine, connected to the pulse width detector, for controlling the state of at least one lock indication signal according to the pulse width detector output signal, wherein when the pulse width detector output signal indicates that the pulse width of the comparator output signal exceeds the predetermined threshold value, the state machine asynchronously resets the first and second counters, and wherein the first and second counters continue to increment otherwise.