Patent ID: 7324397

Claim:
A semiconductor integrated circuit having over one semiconductor substrate a nonvolatile memory and a logic circuit which uses information stored in said nonvolatile memory to perform logical operation, wherein said nonvolatile memory and logic circuit use common supply voltage as their operating power supply voltage, wherein said nonvolatile memory comprises memory cells, word lines, complementary bit lines, and differential amplifiers connected with said complementary bit lines, wherein said memory cell comprises a pair of MOS transistors whose gate electrodes are connected with the same word line, the source/drain electrodes of one MOS transistor are connected with a bit line and a voltage signal line supplied with predetermined voltage, and the source/drain electrodes of the other MOS transistor are floated with respect to a bit line or said voltage signal line, and wherein said MOS transistors respectively included in a plurality of memory cells disposed along said bit lines are formed in a common well, and the MOS transistors are electrically separated from each other by a dummy MOS transistor whose gate electrode is supplied with off potential.