Patent ID: 7962811

Claim:
A method for disabling a scan chain function for power saving in a processor, comprising: inserting gates in the scan chain; generating scan chain control signals delivered to the gates; and controlling connectivity of the scan chain with the control signals during functional mode of the processor, wherein: inserting gates in the scan chain further comprises inserting the gates at the scan out port of a final latch bit of an array of latch bits inside a register of the scan chain, gates are not inserted at the scan out ports of latch bits in the array of latch bits that are positioned prior to the final latch bit in the array of latch bits of the scan chain, and controlling the connectivity of the scan chain with the control signals during functional mode of the processor further comprises: producing control signals that will disable the scan chain during a primary mode of the processor; and producing control signals that will enable the scan chain during a scan mode of the processor.