Patent ID: 8751773

Claim:
A method of scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein at least one processor element comprises reconfigurable logic, the method comprising: providing a plurality of executable transaction schedulers, each executable transaction scheduler comprising a scheduling algorithm for determining a most eligible executable transaction for execution from a number of candidate executable transactions; linking the executable transaction schedulers together to form a multilevel scheduler; providing a configuration queue of executable transactions for a first configuration of the reconfigurable logic, the executable transactions allocated to and ready for execution by the reconfigurable logic; outputting a most eligible executable transaction from the multilevel scheduler to the configuration queue; outputting the most eligible executable transaction from the configuration queue to the reconfigurable processor element for execution when the reconfigurable logic is configured according to the first configuration; and reconfiguring the reconfigurable logic according to a second configuration when a pre-determined threshold is reached.