Patent ID: 7279714

Claim:
A flat panel display device, comprising: a substrate; a first transistor, comprising: a first gate electrode formed on said substrate; a first drain electrode insulated from said first gate electrode; a first source electrode insulated from said first gate electrode and surrounding said first drain electrode in the same plane; and a first semiconductor layer disposed above and electrically contacting said first drain electrode and said first source electrode, and insulated from said first gate electrode; a first capacitor electrode connected to said first gate electrode; a second capacitor electrode connected to said first source electrode; a second transistor, comprising: a second gate electrode; a second drain electrode insulated from said second gate; a second source electrode insulated from said second gate electrode and surrounding said second drain electrode; and a second semiconductor layer disposed above and electrically contacting said second drain electrode and said second source electrode, and insulated from said second gate electrode, with said second drain electrode being electrically connected to said first gate electrode, and said first semiconductor layer and second semiconductor layer together forming a semiconductor layer as a single body; a gate insulating layer formed on said entire surface of said substrate and covering said first gate electrode, said second gate electrode, and said first capacitor electrode; a protective layer formed on the entire surface of said substrate and covering said first drain electrode and said first source electrode, said second drain electrode and said second source electrode, said second capacitor electrode, and said semiconductor layer; a first contact hole formed in said protective layer and said semiconductor layer to expose a portion of said second drain electrode; a second contact hole formed in said protective layer, said semiconductor layer, and said gate insulating layer which correspond to a region other than the region between said first drain and source electrodes to expose a portion of said first capacitor electrode, with said second drain electrode and said first capacitor electrode being electrically connected to each other by an interconnection formed in said first contact hole and said second contact hole and on said protective layer; and a display element including a pixel electrode electrically connected to said first drain electrode.