Patent ID: 7801696

Claim:
A semiconductor memory device having a data access mode and an off chip driver (OCD) control mode to adjust a data output impedance, comprising: a data input/output (I/O) pad; a data input unit for buffering and latching an input data signal inputted from the data I/O pad during the data access mode, and aligning an OCD control code inputted from the data I/O pad during the OCD control mode; a data output driving unit for receiving an output data signal from a memory core and adjusting the data output impedance in response to a plurality of impedance adjustment control signals to output the adjusted output data signal to the data I/O pad; a signal generating unit for generating a column address strobe (CAS) signal to transfer the input data signal to the memory core during the data access mode, and an OCD operation signal during the OCD control mode; and an OCD control unit for generating the plurality of impedance adjustment control signals based on the OCD operation signal and the aligned OCD control code.