Patent ID: 8598663

Claim:
A semiconductor structure comprising: a semiconductor on insulator (SOI) substrate comprising: a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer; a circuit formed with respect to the SOI layer, the circuit comprising: an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and an NFET gate; a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a PFET gate; a first well in the base semiconductor layer under the NFET; and a second well in the base semiconductor layer under the PFET; and the SOI substrate having a nonzero electrical bias; wherein (i) the NFET source and drain extensions are overlapped with respect to the NFET gate and the PFET source and drain extensions are underlapped with respect to the PFET gate, or (ii) the NFET source and drain extensions are underlapped with respect to the NFET gate and the PFET source and drain extensions are overlapped with respect to the PFET; and wherein for the NFET and PFET each having source and drain extensions and a gate channel underneath a gate, overlapped is defined as the source and drain extensions extending into the gate channel and underlapped is defined as the source and drain extensions spaced away from the gate channel.