Patent ID: 8278203

Claim:
A method of forming a memory array comprising non-volatile storage elements and transistors, the method comprising: forming stacks including a first region of polysilicon, a dielectric, a second region of polysilicon, and a sacrificial material, a first group of the stacks for non-volatile storage elements, a second group of the stacks for transistors, the dielectric resides between the first and second regions of polysilicon, the sacrificial material covers the second region of polysilicon; forming insulation between adjacent stacks; removing the sacrificial material to reveal first openings in the first stacks between the insulation and second openings in the second stacks between the insulation; etching a cutout region within the second opening through the second region of polysilicon and the dielectric in regions in which control gates of transistors are to be formed to expose the first region of polysilicon; and forming metal at least in the first openings and the second openings, control gates of the non-volatile storage elements are formed at least in part from the metal in the first openings and adjacent portions the second region of polysilicon, control gates of the transistors are formed at least in part from the metal in the second openings and adjacent portions of first region of polysilicon.