Patent ID: 7508732

Claim:
A flash memory device, comprising: a memory cell array comprising first type memory cells capable of storing m-bit data and second type memory cells capable of storing n-bit data, where n is not equal to m; a page buffer circuit comprising a plurality of page buffers adapted to operate in programming, erasing, and reading operations of the first and second type memory cells; and a control logic unit adapted to determine respective functions performed by the page buffers based on whether each page buffer is associated with first type memory cells or second type memory cells; wherein each page buffer comprises a plurality of latches adapted to store data for different purposes during programming and reading operations depending on the data storage capacities of corresponding memory cells among the first and second type memory cells, each one of the plurality of latches is further adapted to operate in relation to a selected one of a plurality of variable data storage functions, and the selection of the one variable data storage function is determined by the control logic unit in relation to the data storage capacities of corresponding memory cells among the first and second type memory cells.