Patent ID: 8723313

Claim:
A semiconductor package structure comprising: a bonding pad; an insulating board affixed on the bonding pad, and having a plurality of cavities and a plurality of alignment marks; at least one semiconductor die disposed in one of the cavities, at least one connection pad and a passivation layer being formed on the semiconductor die, and a bottom surface of the semiconductor die being connected to the bonding pad; a first metallic layer formed on a surface of the connection pad; an insulating layer formed on the passivation layer and the first metallic layer, and having at least one conductive via through which the first metallic layer is exposed; a wiring layer formed on a surface of the insulating layer and in the conductive via, the wiring layer being connected with the first metallic layer; at least one pin base disposed on the wiring layer; and at least one metallic bump connected to the pin base, the metallic bump electrically connecting the connection pad with an outer circuit board, wherein the connection pad is disposed on a wiring surface of the semiconductor die, which is opposite to the bottom surface of the semiconductor die, and the passivation layer covers the wiring surface of the semiconductor die and has a plurality of openings through which an upper surface of the connection pad is exposed, and the passivation layer includes at least one positioning structure corresponding to the alignment marks.