Patent ID: 7148737

Claim:
A semiconductor switching circuit comprising: a common terminal; first, second, and third terminals; first, second, and third ground terminals; first, second, and third control terminals; a first through FET having a source and drain connected in series between said common terminal and first terminal, and a gate connected to said first control terminal via a first resistor; a second through FET having a source and drain connected in series between said common terminal and second terminal, and a gate connected to said second control terminal via a second resistor; a third through FET having a source and drain connected in series between said common terminal and third terminal, and a gate connected to said third control terminal via a third resistor; 11th and 12th shunt FETs each having a source and drain connected in parallel between said first terminal and first ground terminal; 21st and 22nd shunt FETs each having a source and drain connected in parallel between said second terminal and second ground terminal; and 31st and 32nd shunt FETs each having a source and drain connected in parallel between said third terminal and third ground terminal, wherein gates of said 11th and 22nd shunt FETs are connected to said third control terminal via 11th and 22nd resistors, respectively, gates of said 21st and 31st shunt FETs are connected to said first control terminal via 21st and 31st resistors, respectively, gates of said 12th and 32nd shunt FETs are connected to said second control terminal via 12th and 32nd resistors, respectively, and when a first electric potential is supplied only to a Jth (J is a natural number of 1 to 3) control terminal, and a second electric potential lower than the first electric potential is supplied to the rest of said control terminals, said common terminal and a Jth terminal are electrically connected, and said first to third terminals except for said Jth terminal and said common terminal are electrically disconnected.