Patent ID: 7795941

Claim:
A frame pulse signal latch circuit comprising: a pulse-width expanding unit which outputs a frame pulse signal which is obtained by expanding a pulse width of an input frame pulse signal which has the pulse width of an m (m is a positive integer) -clock cycle to a pulse width which is slightly longer than the m-clock cycle; a phase adjustment unit which generates an output clock by adjusting a phase of an input clock based on a directed phase adjustment amount; a first latch unit which obtains an output frame pulse signal by latching the frame pulse signal, which is output from the pulse-width expanding unit, in synchronization with the output clock; a racing detection unit which generates signals including a signal shifted by one clock to a signal shifted by m clocks with respect to the output frame pulse signal and detects a racing state, which is generated in the output frame pulse due to a phase relation between the frame pulse signal, which is output from the pulse-width expanding unit, and the output clock, based on a result of an AND operation of the output frame pulse signal and the signals including the one-clock shifted signal to the m-clock shifted signal; and a control unit which sequentially selects and directs different phase adjustment amounts to the phase adjustment unit, determines an optimal phase adjustment amount based on a worst phase adjustment amount of the case in which the racing state is detected by the racing detection unit, and gives a direction about the optimal phase adjustment amount to the phase adjustment unit.