Patent ID: 7312144

Claim:
A method of fabricating an interconnection structure in a semiconductor device comprising: forming a first active region in a substrate; forming a second active region in the substrate; forming a first field region in the substrate disposed between the first active region and the second active region; forming an interlayer dielectric on the substrate; forming a first opening in the interlayer dielectric exposing the first active region and the second active region; filling the first opening with a conductive material to form a first unitary interconnection structure connecting the first active region to the second active region; forming a third active region in the substrate; forming second and third field areas in the substrate and on opposite sides of the third active region; forming a first conductive line on the second field area; forming a second conductive line on the third field area; forming a second opening in the interlayer dielectric exposing first surfaces of the first conductive line and the second conductive line, wherein the interlayer dielectric remains in a gap between the first and the second conductive lines; and filling the second opening with a conductive material to form a second unitary interconnection structure contacting the first conductive line and the second conductive line and electrically connecting the first conductive line to the second conductive line.