Patent ID: 6871267

Claim:
A method for increasing communication efficiency in a multi-processor system, comprising: snooping, at a processor having a transition cache and at least one level of cache associated therewith, a first command on a system bus, said system bus providing communication between processors in said multi-processor system, said first command requesting invalidation of a cache line; generating a second command in response to said first command at one of said levels of cache which stores said cache line if a memory image coherency state for said cache line indicates that said cache line includes modified data, said second command instructing that said cache line be castback; transferring said second command and said cache line from said one of said levels of cache to said transition cache in response to said first command; invalidating said cache line in each level of cache associated with said processor that stores said cache line; snooping a system response to said first command at said processor, said snooping a system response step being performed after said invalidating step; and processing said second command at said processor based on said system response to said first command; wherein said processing step converts said second command to a third command in said transition cache if said system response to said first command is a retry, said third command requesting that said cache line be stored in a main memory of said multi-processor system, and discards said second command without issuing a bus command if said system response to said fist command indicates normal completion of said first command.