Patent ID: 8604946

Claim:
A data processing device, comprising: a decoder operable to read an instruction for information specifying a bit sequence storage area in which an N-bit (N being an integer greater than or equal to two) target sequence is stored, information indicating a first bit range that includes a first end bit of a given N-bit sequence, and information indicating a second bit range that does not include a second end bit of the given N-bit sequence and that is contiguous with the first bit range, to decode the information so read, and to output a decoded signal in response to the information so read; and a bit manipulation circuit operable to, once the decoder outputs the decoded signal, generate and output an N-bit output sequence by manipulating the target sequence stored in the bit sequence storage area in accordance with the decoded signal, wherein the bit manipulation circuit generates the output sequence by arranging a bit sequence identical in value to the first bit range of the target sequence in the first bit range of the output sequence, arranging a bit sequence identical in value to the second bit range of the target sequence in a third bit range of the output sequence that is equal in length to the second bit range and that includes the second end bit of the output sequence, and filling a portion of the output sequence that belongs to neither of the first bit range and the third bit range with uniform bits of a predetermined value.