Patent ID: 7326629

Claim:
A method for forming an integrated device layer stack comprising: (a) providing a first device wafer having an underside; (b) providing a base device wafer having an exposed array of at least one bond pad; (c) thinning said first device wafer to a thickness by planar polishing said underside, thereby forming a first device layer; (d) forming a blanket insulative shield layer on said underside; (e) patterning a non-conductive adhesive layer on said shield layer to form an array of at least one closed loop adhesive band placed in an arrangement mirroring said array of at least one bond pad whereby each one of said at least one of bond pad is provided with a corresponding perimetrically mating closed loop adhesive band; (f) positioning said array of at least one closed loop adhesive band over and facing said array of at least one bond pad and, while aligning said thinned first device wafer to said base device wafer, pressing said first and said base wafers together, thereby forming a device layer stack; (g) curing said non-conductive adhesive layer thereby forming a bond; (h) patterning and anisotropically etching first device layer and said shield layer to form at least one opening exposing a subjacent bond pad; (i) forming insulative sidewalls within each said opening; and (j) forming a conductive pass-through element in each said opening.