Patent ID: 7495943

Claim:
A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines each intersecting the plurality of word lines; a plurality of memory cells each arranged at a desired crossing point between any one of the plurality of word lines and any one of the plurality of bit lines; first and second memory arrays of a rectangular shape, inclusive of the plurality of memory cells, both the first and second memory arrays having a first memory capacity; third and fourth memory arrays of a rectangular shape, inclusive of the plurality of memory cells, both the third and fourth memory arrays having a second memory capacity smaller than the first memory capacity; a first memory block including the first and third memory arrays; a second memory block including the second and fourth memory arrays; and first and second bank addresses for selecting the first and second memory blocks, respectively, wherein: the first memory block forms an L shape by being disposed such that the third memory array has one side shorter than and opposed to one side of the first memory array; the second memory block forms an L shape by being disposed such that the fourth memory array has one side shorter than and opposed to one side of the second memory array; and the third and fourth memory arrays are arranged between the first and second memory arrays such that respective long sides of the third and fourth memory arrays face each other, and the first and second memory blocks are arranged so as to be point-symmetrical with respect to each other.