Patent ID: 8179177

Claim:
A wideband delay-locked loop (DLL) circuit, comprising: a primary delay block receiving an external clock signal and comprising a plurality of series connected delays cells providing a plurality of clock delay signals; a switching block selecting two of the plurality of clock delay signals and providing the selected two clock delay signals as first and second switching clock signals, and an interpolator receiving and interpolating between the first and second switching clock signals to generate a zero internal clock signal; a path selecting switch receiving the zero internal clock signal and either (1) passing the zero internal clock signal to generate an internal clock signal or (2) applying the zero internal clock signal to a secondary delay block providing a secondary delay time to the zero internal clock signal to generate the internal clock signal; a clock path delay block receiving the internal clock signal and applying a clock path delay time to the internal clock signal to generate a first internal clock signal; and a phase detection/control circuit receiving and comparing a phase of the first internal clock signal with a phase of the external clock signal.