Patent ID: 7851356

Claim:
A method of manufacturing an integrated circuit, the method comprising: forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region; and forming wiring lines within a peripheral region of the substrate; wherein forming the landing pads and forming the wiring lines comprises a common lithographic process being effective both in the array and peripheral regions and comprising: a first lithographic exposure process using a first mask comprising first line structures in an array portion corresponding to the array region and wiring line structures in a peripheral portion corresponding to the peripheral region; and a second lithographic exposure process using a second mask with second line structures in the array portion corresponding to the array region and with a block structure in the peripheral portion corresponding to the peripheral region, the second line structures intersecting the first line structures, wherein intersecting portions of the first and the second line structures correspond to the landing pads.