Patent ID: 8078806

Claim:
A microprocessor coupled to a system memory, the microprocessor comprising: a memory subsystem, having a translation look-aside buffer (TLB) configured to store TLB information; an instruction decode unit, coupled to said memory subsystem, configured to decode an instruction, said instruction specifying a data stream in the system memory and an abnormal TLB access policy; a stream prefetch unit, coupled to said memory subsystem, configured to generate a prefetch request to said memory subsystem to prefetch a cache line of said data stream from the system memory into said memory subsystem, wherein if a virtual page address of said prefetch request causes an abnormal TLB access, said memory subsystem is configured to selectively abort said prefetch request based on said abnormal TLB access policy specified in said instruction; and a load unit, coupled to said memory subsystem, configured to generate a load request to said memory subsystem to load data specified by an address from the system memory into said memory subsystem, wherein said instruction specifies a fetch-ahead distance, wherein said stream prefetch unit is configured to monitor said load request to determine when said address hits in said data stream, wherein said stream prefetch unit is configured to generate one or more of said prefetch request such that said data stream is prefetched into said memory subsystem at least said fetch-ahead distance ahead of said load request address hitting in said data stream.