Patent ID: 7132848

Claim:
A power management circuit, comprising: a logic cell comprising: a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of data signal outputs; a first PMOS transistor comprising a first gate, a first source, and a first drain coupled to one data signal output; and a second PMOS transistor comprising a second gate coupled to the first drain, a second source coupled to the first source, and a second drain coupled to the other data signal output, wherein the logic cell is switched between normal and standby modes according to a power control signal; a first switch coupled between a power voltage, the power control signal and the connection point of the first source and the second source, wherein the first switch is turned off to disconnect the power voltage and the logic cell when the power control signal is at a predetermined level, such that the logic cell operates in standby mode; and a latch circuit coupled between the power voltage and the data signal outputs to preserve the voltage levels respectively of the complementary pair of data signal outputs when the logic cell operates in the standby mode.