Patent ID: 7782706

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a matrix composed of rows and columns; a redundant memory cell array including a plurality of redundant memory cells for repairing the memory cell array; a plurality of access control line activation means each connected to either of access control lines which are a word line for controlling an access in a row direction of the memory cell array and a bit line for controlling an access in a column direction thereof; one or more redundant access control line activation means each connected to either of redundant access control lines which are a redundant word line for controlling an access in a row direction of the redundant memory cell array and a redundant bit line for controlling an access in a column direction thereof to activate the redundant access control line connected thereto; and an address decoder for sending out an address specification signal for specifying the access control line activation means corresponding to an address inputted thereto, wherein each of the access control line activation means has a temporary memory circuit for storing access control line inactivation information for inactivating the access control line of a defective memory cell, and an inactivation address sensing circuit for determining whether or not the corresponding one of the redundant memory cells is to be used in accordance with the access control line inactivation information and the address specification signal, and the redundant access control line activation means activates the redundant access control line connected thereto when the inactivation address sensing circuit determines that the redundant memory cell is to be used.