Patent ID: 7107175

Claim:
A method for calibration of a pipelined analog-to-digital converter, ADC, comprising the steps of: arranging the topology of a pipelined ADC to conform to the equation; y ⁡ ( 2 ⁢ b sc - 1 ) = X in ⁡ ( 2 ⁢ b sc - 1 ) + ɛ Q ⁡ ( 2 ⁢ b sc - 1 ) + ∑ i ≠ k n ⁢ ɛ DAC , i ⁡ ( 2 ⁢ b sc - 1 ) + ɛ k , where; y is a digital output signal; x in is an AC input signal; ε Q is an inherent quantization error; ε DAC is a residual error in the digital-to-analog converter, DAC, elements of the pipelined ADC; ε k is an error in a given kth DAC element under calibration; b sc is a binary modulation signal orthogonal to the input signal and consists of a pseudo-random sequence of ones and zeros with a white noise spectrum; averaging the digital output y(2 b sc −1) for a selected calibration time in order to obtain a kth error term described by, < y (2 b sc −1)>=ε k ; adding all the k error terms to form an integral nonlinearity profile, INL; and at least once per selected calibration time, subtracting the INL from the ADC transfer characteristic, thereby calibrating the pipelined ADC.