Patent ID: 7016235

Claim:
An integrated circuit comprising a memory providing read and write burst operations with data sequences defined in Table 2, the memory comprising: a plurality of memory cells; circuitry for providing a first signal specifying whether a burst operation to be performed is sequential or interleaved, and specifying a burst length and at least two least significant address bits A 0 and A 1 of a starting address of the burst operation; at least four multiplexer circuits (“read multiplexer circuits”) Mr 1 , Mr 2 , Mr 3 , Mr 4 . . . , wherein each read multiplexer circuit Mri (i=1, 2, 3, 4 . . . ) comprises one or more multiplexers, wherein each read multiplexer circuit Mri is to receive data read from the memory cells in a burst read operation and to select a respective ith data item to be provided serially by the memory in the burst read operation, the data item comprising one or more data bits; and at least four multiplexer circuits (“write multiplexer circuits”) Mw 1 , Mw 2 , Mw 3 , Mw 4 . . . , wherein each write multiplexer circuit Mwi (i=1, 2, 3, 4 . . . ) comprises one or more multiplexers, wherein each write multiplexer circuit Mwi is to receive data to be written to the memory cells in a burst write operation and to select a data item to be written at an address A 1 A 0 =i; circuitry for receiving in parallel data items selected by the read multiplexer circuits and for providing the data items serially as an output of a burst read operation; and circuitry for receiving in parallel data items selected by the write multiplexer circuits and for writing the data items in parallel to the memory cells.