Patent ID: 8653557

Claim:
An electrostatic discharge (ESD) protection circuit comprising: a first lowly-doped well of a first conductivity type; a second lowly-doped well of a second conductivity type; a first highly-doped region of the first conductivity type formed within the first lowly-doped well; a second highly-doped region of the second conductivity type formed within the first lowly-doped well; a third highly-doped region of the first conductivity type formed within the second lowly-doped well, wherein the second highly-doped region functions as either a cathode or an anode of the ESD protection circuit and the third highly-doped region functions as the other of the anode or the cathode; a fourth highly-doped region of the second conductivity type formed within the second lowly-doped well; a fifth highly-doped region of the first conductivity type formed within the first lowly-doped well between the second highly-doped region and the second lowly-doped well; a sixth highly-doped region of the second conductivity type formed within the first lowly-doped well between the second highly-doped region and the second lowly-doped well; a first external resistive element electrically coupled between the first highly-doped region and the second highly-doped region; a second external resistive element electrically coupled between the third highly-doped region and the fourth highly-doped region; and a trigger circuit to turn on the ESD protection circuit during an ESD event, wherein the trigger circuit is electrically coupled between any two of: the first highly-doped region, the second highly-doped region, the third highly-doped region, the fourth highly-doped region, the fifth highly-doped region, and the sixth highly-doped region; wherein a first transistor is formed by an emitter including the third highly-doped region, a base including the second lowly-doped region, and a collector including the first lowly-doped region; a second transistor is formed by an emitter including the second highly-doped region, a base including the first lowly-doped region, and a collector including the second lowly-doped region; and a third transistor is formed by an emitter including the second highly-doped region, a base including the first lowly-doped region, and a collector including the sixth highly-doped region.