Patent ID: 8384129

Claim:
A transistor, comprising: a substrate structure with laterally disposed source, drain, and gate regions, the substrate structure comprising; a semiconductor body extending laterally throughout the source, drain and gate regions, a first layer structure comprising a compound including at least two of Aluminum, Gallium, Indium, and Nitrogen disposed above the semiconductor body in the source, drain and gate regions, a barrier material layer disposed above the first layer structure in the source, drain and gate regions, the barrier material layer comprising a compound including at least two of Aluminum, Gallium, Indium, and Nitrogen and having a substantially uniform thickness throughout the source, drain and gate regions, with a heterointerface between the barrier material layer and the first layer structure forming a two dimensional electron or hole gas (2DEG or 2DHG), the barrier material layer additionally comprising a Gallium Nitride capping layer and an enhanced channel charge inducing material layer (ECCIML) formed above the barrier material layer in the source region and the drain region, the ECCIML layer comprising a compound including at least two of Aluminum, Gallium, Indium, and Nitrogen; a gate structure disposed above at least a portion of the gate region, at least a portion of the gate structure extending downward to and at least partially engaging a top surface of the barrier material layer in the gate region; a source structure electrode formed in source region in contact with the 2DEG or 2DHG; and a drain structure electrode formed in drain region in contact with the 2DEG or 2DHG.