Patent ID: 7797481

Claim:
A method of wear-leveling a memory device, the method comprising: grouping a first region of the device into a plurality of logical groups each comprising a plurality of logical block numbers; checking whether logical group information comprising block erase counts for logical block numbers in a logical group is loaded into random access memory (“RAM”), and if not, loading the logical group information into RAM; calculating a group erase count for the logical group from the block erase counts in RAM wherein the calculated group erase count is one of a minimum, maximum or average of all of the block erase counts for the logical block numbers currently in the logical group; receiving a command having a logical address; converting the logical address into a logical block number; determining a logical group number for a current logical group that includes the converted logical block number; and checking whether an accumulated number of merge operations is greater than a predetermined number, and if so, selecting a logical block number currently classified as a data block number and having a minimum block erase count from another logical group having a minimum group erase count, and swapping the selected logical block number from the other logical group into the current logical group in exchange for a logical block number currently classified as a free block number and having a maximum block erase count.