Patent ID: 7567468

Claim:
A selective discharging memory circuit comprising: a plurality of memory units arranged in an array, wherein each memory unit has a corresponding row line and column line; a plurality of discharging modules connected to the corresponding column line, each discharging module receiving a discharging signal and a column selective signal and each discharging module comprising a pulling unit and a decision unit, wherein the decision unit determines whether to discharge the column line through the pulling unit according to the discharging signal and the column selective signal of the column line and for each discharging module of the plurality of discharging modules, the selective discharging memory circuit further comprising: an auxiliary module connected to the discharging module for enhancing an increase of the voltage level of the column line after an objective memory unit is enabled by a row decoder and upon the voltage level of the column line reaching a threshold voltage of a control unit of the auxiliary module; a switch connected to the auxiliary module; and a sense amplifier connected to the switch; while the objective memory unit is selected out of the plurality of memory units for accessing, both of the discharge signal and the column selective signal of the objective memory unit are enabled for discharging the objective memory unit; after the objective memory unit is discharged, the discharge signal is disabled and the row line of the objective memory unit is enabled, the column line of the objective memory unit, as a result, is charged to a determined voltage by the help of the auxiliary module of the objective memory unit; then the sense amplifier reads out the value of the objective memory unit.