Patent ID: 8423661

Claim:
A packet communication system connectable to a plurality of networks, comprising: a plurality of physical layer transceivers; a packet communication device connectable to the plurality of networks through the plurality of physical layer transceivers, respectively; an analog input terminal that generates an analog transmit signal; an A/D converter that receives the analog transmit signal from the analog input terminal, converts the analog transmit signal into a digital transmit signal, and applies the digital transmit signal to the packet communication device; a D/A converter that receives a digital received signal from the packet communication device, and converts the digital received signal into an analog received signal; an analog output terminal that receives the analog received signal from the D/A converter, wherein the packet communication device comprises: a plurality of communication circuits for transmitting and receiving a packet to and from a plurality of communication targets; a packet generation processing circuit for generating a packet to be transmitted by the plurality of communication circuits, and processing a packet received by the plurality of communication circuits; a transfer buffer circuit for holding a transfer packet which is used to give and receive information mutually between the plurality of communication targets; and a transfer control circuit for, if it is judged that the packet received by the plurality of communication circuits is the transfer packet, outputting the received packet to the transfer buffer circuit, and outputting either a packet generated by the packet generation processing circuit or a transfer packet held in the transfer buffer circuit on a priority basis to a specified communication circuit corresponding to a communication target to which the packet is transmitted or transferred, wherein, if a usage rate of the transfer buffer circuit exceeds a threshold value, the transfer control circuit makes the priority order of the transfer packet higher than that of the generated packet, and thereby outputs the transfer packet to the specified communication circuit in preference to the generated packet, and wherein the transfer control circuit comprises a priority-order register which can be set by the packet generation processing circuit, and the priority-order register is loaded with the threshold value for changing the priority order, the threshold value being related to a usage rate of the transfer buffer circuit.