Patent ID: 6869837

Claim:
A method of fabricating word-line spacers, comprising the steps: a) providing a substrate having an inchoate split-gate flash memory structure formed thereover; b) forming a conductive layer over the substrate and the inchoate split-gate flash memory structure; the conductive layer having a upper portion and lower vertical portions over the inchoate split-gate flash memory structure and lower horizontal portions over the substrate; c) forming a dual-thickness oxide layer over the conductive layer; the dual-thickness oxide layer having a greater thickness over the upper portion of the conductive layer; d) partially etching-back the oxide layer to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer; and e) etching: i) away the exposed portions of the conductive layer over the substrate; and ii) through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.