Patent ID: 7724068

Claim:
An integrated circuit including: a bandgap reference circuit for generating a bandgap reference voltage and a temperature dependent voltage that varies in proportion to an ambient temperature of said integrated circuit and is referenced to said bandgap reference voltage; means for generating a temperature independent voltage that is independent of said ambient temperature of said integrated circuit and is referenced to said bandgap reference voltage, and a thermal sensor including means for comparing said temperature independent voltage and said temperature dependent voltage, and for generating a control signal based on a predetermined relationship between said temperature dependent voltage and said temperature independent reference voltage, wherein said thermal sensor comprises a thermal shutdown circuit including means for generating a thermal shutdown signal when said temperature dependent voltage is equal to said temperature independent voltage, wherein said thermal shutdown circuit comprises a first operational amplifier including an inverting input terminal connected to receive said temperature dependent voltage, and a non-inverting input terminal connected to receive said temperature independent voltage, and wherein said bandgap reference circuit comprises: a second operational amplifier having an output terminal, an inverting input terminal, and a non-inverting input terminal; a first resistor and a first diode connected in series between the output terminal of the second operational amplifier and ground, wherein the non-inverting input terminal of the second operational amplifier is connected to a first node disposed between said first resistor and said first diode; and a second resistor, a third resistor, a fourth resistor, and a second diode connected in series between the output terminal of the second operational amplifier and ground, wherein the inverting input terminal of the second operational amplifier is connected to a second node disposed between said second and third resistors, wherein the inverting input terminal of the first operational amplifier is connected to a third node disposed between said third and fourth resistors.