Patent ID: 8130580

Claim:
A low power sense amplifier, comprising: an output latch circuit coupled to a data output line and a reset input; a sense capacitor circuit including a sense capacitor; a pre-charge circuit having a memory output line coupled to a memory cell, the pre-charge circuit configurable, in a pre-charge phase and in response to a reset signal, to charge the sense capacitor and the memory output line to a reference voltage, and during a sensing phase occurring after the pre-charge phase, allow the voltage on the sense capacitor and on the memory output line to discharge due to current of the memory cell; a voltage detection circuit coupled to the memory output line, the voltage detection circuit configurable to: detect that the voltage of the capacitor has reached a threshold voltage level; to decouple the sense capacitor from the memory output line; and to allow the voltage on the memory output line to continue to discharge due to the current of the memory cell; and a delay path coupled to the voltage detection circuit, the delay path configured for inverting and delaying a voltage on an output of the voltage detection circuit, and to cause the output latch circuit to latch a data voltage level on the data output line due to the inverted and delayed voltage.