Patent ID: 7930530

Claim:
A multi-processor system, comprising: a first intellectual property (IP) block including a first processor, the first IP block including a boot memory storing a plurality of boot codes, each of the plurality of boot codes configured to initialize one of a plurality of IP blocks, the plurality of IP blocks including shared access to the boot memory via the first IP block; a second IP block included among the plurality of IP blocks, the second IP block including a second processor reading a boot code corresponding to the second IP block from the boot memory, wherein the first processor includes at least one interface buffer storing the read boot code, the plurality of IP blocks are connected to the first IP block via at least one of a system bus and a local bus, and the second IP block reading the read boot code from the boot memory includes sending a request to the first IP block to provide the boot code for the second IP block, the request including a control instruction configured to enable the at least one interface buffer.