Patent ID: 7355601

Claim:
A system comprising: a system memory; a computer processing module, including: a host processing element configured to perform a task; a data-generating processing element configured to perform a subtask within the task, including: logic configured to receive input data; and logic configured to process the input data to produce output data, wherein an amount of output data is greater than an amount of input data, a ratio of the amount of input data to the amount of output data defining a decompression ratio, wherein the output data generated by the data-generating processing element is not contained in the system memory prior to it being generated by the data-generating processing element; a cache memory coupled to the data-generating processing element for receiving the output data; a computer processing module interface for outputting the output data from the cache memory; coherent cacheable memory of the computer processing module separate from the cache memory coupled to the data-generating processing element; a communication bus; a data processing module, including: a data processing module interface coupling to the computer processing module interface via the communication bus for receiving the output data; and a data processing engine for receiving and processing the output data from the cache memory, wherein the data processing engine uses a tail pointer to indicate a location within the cache memory from which it has just retrieved data; wherein, in a write streaming mode of operation, the computer processing module is configured to allocate a portion of the cache memory for the purpose of receiving streaming write output data from the data-generating processing element, wherein, in the write streaming mode of operation, the system is configured to forward output data from said allocated portion of the cache memory to the data processing module rather than from the system memory, and wherein the data processing module is configured to forward the tail pointer to the coherent cacheable memory of the computer processing module, the tail pointer informing the data-generating processing element of the location within the cache memory from which the data processing module has just retrieved data.