Patent ID: 7990185

Claim:
A circuit comprising: a first differential output terminal; a unity gain amplifier; a first transistor including a base, a collector and an emitter, the emitter being coupled to the first differential output terminal; a first differential pair that comprises a second transistor having a collector coupled to the emitter of the first transistor and a third transistor including a collector coupled to the base of the first transistor and an emitter coupled to the emitter of the second transistor; a first isolation circuit coupled to the unity gain amplifier, the collector of the third transistor of the first differential pair and the base of the first transistor, the first isolation circuit to isolate parasitic capacitance from attenuating an output signal at the first differential output terminal; a second differential output terminal; a fourth transistor including a base, a collector and an emitter, the emitter being coupled to the second differential output terminal; a second differential pair that comprises a fifth transistor having a collector coupled to the emitter of the fourth transistor and a sixth transistor including a collector coupled to the base of the fourth transistor and an emitter coupled to the emitter of the fifth transistor; a second isolation circuit coupled to the unity gain amplifier, the collector of the sixth transistor of the second differential pair and the base of the fourth transistor, the second isolation circuit to isolate parasitic capacitance from attenuating an output signal at the second differential output terminal; and a first feedforward capacitor coupled to the base of the first transistor and the emitter of the fourth transistor.