Patent ID: 8593440

Claim:
A liquid crystal display comprising: a liquid crystal display panel including a liquid crystal layer between an upper substrate and a lower substrate of the liquid crystal display panel, m×n liquid crystal cells arranged in a matrix format according to a crossing structure of m/2 data lines and 2n gate lines, and thin film transistors (TFTs) respectively connected to the m×n liquid crystal cells, where m and n are a positive integer; a data drive circuit supplying a data voltage to the data lines in response to a polarity control signal; a gate drive circuit sequentially supplying a gate pulse to the gate lines; and a POL logic circuit controlling the polarity control signal so that a phase of the polarity control signal varies every frame period, wherein the POL logic circuit sequentially outputs first to fourth polarity control signals to generate the polarity control signal, wherein the POL logic circuit sequentially performs an operation of generating the first polarity control signal during (4i+1)-th frame periods, an operation of generating the second polarity control signal, whose a phase is different from a phase of the first polarity control signal, during (4i+2)-th frame periods, an operation of generating the third polarity control signal, whose a phase is opposite to the phase of the first polarity control signal, during (4i+3)-th frame periods, and an operation of generating the fourth polarity control signal, whose a phase is opposite to the phase of the second polarity control signal, during (4i+4)-th frame periods, where i is a positive integer including zero.