Patent ID: 8212987

Claim:
A method of manufacturing a liquid crystal display (LCD) device, the LCD device comprising a substrate at least having a transistor region, a pixel region, and a storage capacitor region, the manufacturing method comprising the steps of: (a) forming a conductive structure including a gate in the transistor region and a first electrode in the storage capacitor region, wherein the gate is composed of a patterned first transparent conductive layer and a patterned first conductive layer stacked in series in the transistor region, and the first electrode is composed of the patterned first transparent conductive layer in the storage capacitor region; (b) forming a semiconductor structure in the transistor region, the pixel region, and the storage capacitor region, wherein the semiconductor structure is composed of a dielectric layer, a patterned semiconductor layer, and a patterned second conductive layer stacked in series in the transistor region, and the dielectric layer in the pixel region and the storage capacitor region; and (c) forming a patterned second transparent conductive layer in the transistor region, in the pixel region, and in the storage capacitor region and removing a portion of the patterned second conductive layer, wherein the patterned second transparent conductive layer in the pixel region and in the storage capacitor region respectively construe a pixel electrode and a second electrode of the storage capacitor, and the patterned second transparent conductive layer in the transistor region used to defines a source region and a drain region of the transistor region; wherein a first half-tone mask (HTM) is applied in the step (a) to form the conductive structure in a first single mask process, the first single mask process comprises the steps of: forming a first transparent conductive layer on the substrate; forming a first conductive layer to cover the first transparent conductive layer; forming photo-resistors with different vertical dimensions in the transistor region and the storage capacitor region respectively by the first HTM to define etching regions; etching the first conductive layer and the first transparent conductive layer at parts thereof that are not covered by the photo-resistors; ashing the photo-resistors until exposing the patterned first conductive layer in the storage capacitor region; etching the patterned first conductive layer in the storage capacitor region; and removing residual photo-resistors.