Patent ID: 7860203

Claim:
A programmable logic device comprising: programmable logic circuitry; a plurality of channels of nominal data-handling circuitry, each including a data receiver portion and a data transmitter portion, the data receiver portion including a clock reference loop and a data recovery loop; at least one channel of nominal clock management unit circuitry including a clock reference loop and a data recovery loop; global circuitry for distributing a clock signal output by the clock reference loop of the clock management unit channel to each of the data-handling channels as a global clock signal; local circuitry associated with each of the data-handling channels for conveying a clock signal output by the clock reference loop of that channel to the transmitter portion of that channel as a local clock signal; and selection circuitry associated with each of the data-handling channels for selecting either the global clock signal or the local clock signal supplied by the local circuitry associated with that channel for use by the transmitter portion of that channel.