Patent ID: 7872910

Claim:
A non-volatile semiconductor storage system comprising: a memory cell array comprising a plurality of memory cells enabled to store multi-value data, the memory cells being arranged along a plurality of bit-lines and a plurality of word-lines; a bit-line control circuit connected to the bit-lines to control the bit-line; a word-line control circuit controlling applying a soft-value read voltage as a word line voltage to the word line, the soft-value read voltage being smaller than an upper limit of each of the plurality of the threshold voltage distributions and larger than a lower limit thereof to generate a plurality of soft-values; a likelihood calculation circuit calculating a likelihood of plural-bit data stored in the memory cell based on the soft-value generated by setting the word-line voltage at the soft-value read voltage; and an error correction circuit executing data error correction for the plural-bit data based on the calculated likelihood.