Patent ID: 7589648

Claim:
A data decompression circuit comprising: a decompression engine for decompressing a data stream having a series of variable-sized data frames each having a header indicating the number and location of compressed repeated data words and uncompressed data words in the data frame followed by a body that includes the uncompressed data words in the data frame, the decompression engine including: a data process engine adapted to decode the header of a data frame to identify the uncompressed data word locations and compressed repeated data word locations therein and to insert an uncompressed data word from the body of the data frame and a repeated data word into their respective word locations in a corresponding decompressed data frame; a counter adapted to determine from the header the number of uncompressed data words in the data frame; and a header register coupled to the counter and the data process engine for providing the header of a data frame, the register adapted to load the header of a second data frame in response to a load signal indicating that a first data frame has been decompressed into a corresponding decompressed data frame, the data process engine responsive to the number determined by the counter to insert in a separate clock cycle each uncompressed data word into its word location in the decompressed data frame and to insert in one clock cycle the repeated data words into their word locations in the decompressed data frame.