Patent ID: 8169013

Claim:
A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, comprising, a first transistor formed in said logic section and having gate electrodes and source and drain regions, and a second transistor formed in said memory section having gate electrodes, source and drain regions and a capacitor, said capacitor being of a MIM (metal-insulator-metal) structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, said capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2 (O<x<1), (Zr y , Ti (O<y<1), (Hf Z , Ti 1-z )O 2 (O<z<1) and (Zr k , Ti 1 , Hf m )O 2 (O<k, l, m<1, k+l+m=1), wherein the thickness of said dielectric film is 5 to 15 nm; and wherein each of said first and second transistors further has a refractory metal silicide layer formed over each of said source and drain regions thereof and said lower metal electrode is connected through a metal plug to said refractory metal suicide layer formed over one of said source and drain regions of said second transistor.