Patent ID: 8010926

Claim:
A method for designing the layout of a plurality of latches in two or more clock domains of an integrated circuit carried out by a computer system, comprising: receiving an input layout of logic cells which include the latches located in a common plane, by executing first program instructions in the computer system; creating a rectangular grid in a region of the integrated circuit containing the latches, the grid having grid intersection points defined by a horizontal pitch and a vertical pitch, by executing second program instructions in the computer system; placing clock distribution structures at the grid intersection points in the common plane of the latches, said placing including bipartite matching of (i) cost and capacity for clock distribution structures to (ii) corresponding clock domains, by executing third program instructions in the computer system; and locating the latches around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures, by executing fourth program instructions in the computer system.