Patent ID: 8060725

Claim:
A processor comprising: an instruction subsystem for inputting instructions to be executed; a plurality of processor clusters coupled to said instruction subsystem, each processor cluster comprising a plurality of homologous processing elements that are symmetrical with processing elements in other processor clusters for processing data according to the instructions to be executed for providing a vectorial processing capability, and for processing data with a given bit length N and data with bit lengths obtained by partitioning the given bit length N according to a Single Instruction Multiple Data function, with processing elements in each processor cluster having a same range of computational resources of symmetrical processing elements in the other processor clusters; a load unit for loading into said plurality of processor clusters the data to be processed in sets of high significant bits and low significant bits of operands according to an instruction; an intercluster data path for exchanging data between said plurality of processor clusters, said intercluster data path being scalable to activate selected processor clusters for operating simultaneously on Single Instruction Multiple Data, scalar data and vectorial data; and said plurality of processor clusters configured so that only one processor cluster is activated to operate on data having the given bit length N when in a scalar functionality mode, and configured so that said plurality of processor clusters operate in parallel on data having the given bit length N when in a vectorial functionality mode.