Patent ID: 8395268

Claim:
A semiconductor memory device comprising: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each including electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in a same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each including electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element group in an arrangement direction of the electrode pads; metallic wires for electrically connecting the electrode pads of the plurality of semiconductor elements included in the first and second element groups to the connection pads of the wiring board; and a sealing resin layer formed on the wiring board so as to seal the first and second element groups together with the metallic wires.