Patent ID: 7674700

Claim:
A method for manufacturing a semiconductor device comprising the steps of: forming an insulation layer having a trench that exposes a lower interconnection on a substrate, wherein the insulation layer comprises a first interlayer dielectric layer including fluorine silicate glass (FSG) and a second interlayer dielectric layer including an oxide; pre-processing the insulation layer having the trench on the substrate; forming a TiSiN layer on inner walls and a bottom surface of the trench in a first process chamber; exposing the lower interconnection by selectively removing a portion of the TiSiN layer that covers the bottom surface of the trench in a second process chamber; forming a tantalum layer on the TiSiN layer and the lower interconnection exposed in the bottom surface of the trench in the second process chamber; forming a copper seed layer on the tantalum layer in a third process chamber; and forming a copper interconnection in the trench on the copper seed layer.