Patent ID: 8245017

Claim:
A microprocessor, comprising: a first branch condition state; a second branch condition state; a conditional branch instruction of a first type, configured to instruct the microprocessor to wait to correctly resolve the conditional branch instruction of the first type based on the first branch condition state until other instructions within the microprocessor that update the first branch condition state and that are older than the conditional branch instruction of the first type have updated the first branch condition state; a conditional branch instruction of a second type, configured to instruct the microprocessor to correctly resolve the conditional branch instruction of the second type based on the second branch condition state without determining whether there are other instructions within the microprocessor that are older than the conditional branch instruction of the second type that have not yet updated the second branch condition state; an execution unit, coupled to the first branch condition state, configured to resolve the conditional branch instruction of the first type; and an instruction scheduler, coupled to the execution unit, configured to wait to issue to the execution unit the conditional branch instruction of the first type until an instruction makes available to the conditional branch instruction of the first type the result with which the instruction updates the first branch condition state, wherein the instruction is a newest one of the other instructions within the microprocessor that update the first branch condition state and that are older than the conditional branch instruction of the first type; wherein the microprocessor is configured to retire the conditional branch instruction of the second type without sending it to the instruction scheduler.