Patent ID: 7400527

Claim:
A non-volatile memory structure comprising: a MOSFET including a storage layer for storing charge representing any one of N different multi-bit words, where N is a selected integer greater than one, and a control gate; a source of said N multi-bit words in sequence, said N multi-bit words representing in digital form N different voltage levels; a digital-to-analog converter for receiving in sequence said N multi-bit words from said source and for providing to said control gate N different voltage levels corresponding to said N multi-bit words; an output buffer for receiving said N multi-bit words; an output lead for carrying a signal representing the state of said MOSFET; and a control circuit responsive to a change in said signal representing the state of said MOSFET, for providing a signal to said output buffer to cause said output buffer to output a signal or signals corresponding to the value of the multi-bit word represented by the charge stored on the storage layer of said MOSFET.