Patent ID: 7689881

Claim:
A memory sub-system, comprising: a main memory; an ECC (Error Correction Code) circuit electrically coupled to the main memory; and a hard fail identifier circuit electrically coupled to the ECC circuit, wherein the ECC circuit is configured to detect a first bit fail at a first bit location at a first location address of the main memory and to send an error flag signal to the hard fail identifier circuit to notify the hard fail identifier circuit about the first bit fail, wherein the hard fail identifier circuit is configured to, in response to receiving the error flag signal sent by the ECC circuit, generate a threshold reached signal to indicate that the first bit fail is a hard fail, and wherein the hard fail identifier circuit comprises a failure stack electrically coupled to the ECC circuit, said failure stack comprising N entries, N being a positive integer, each entry of the N entries comprising a use bit, an address field, an age field, and a bit location field, said N entries comprising M unavailable entries and P available entries, M and P being non-negative integers, M plus P being equal to N, each unavailable entry of the M unavailable entries storing a bit fail.