Patent ID: 8867650

Claim:
An interference cancellation apparatus, applicable to a communication system that includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain, comprising: a First-In-First-Out (FIFO) circuit, receiving a digital transmission signal of the transmitter in the first clock domain and outputting the digital transmission signal in the second clock domain according to an accumulated timing difference between the first clock domain and the second clock domain, the digital transmission signal including a plurality of sampled points, the FIFO circuit further including: a synchronic (Sync) FIFO unit, receiving the sampled points in the first clock domain and storing temporarily part of the sampled points; and an asynchronic (Async) FIFO unit coupled with the Sync unit for basing on the accumulated timing difference to perform one of following output processes in each timing of the second clock domain: outputting one of the sampled points, outputting two consecutive points of the sampled points, and outputting no sampled point; and a cancellation signal generator, coupled with the FIFO circuit, generating a cancellation signal based on the digital transmission signal for cancelling an interference signal received by the receiver; wherein the interference signal is generated in response to the digital transmission signal, and the cancellation signal generator adjusts the cancellation signal according to a phase difference between the interference signal and the cancellation signal.