Patent ID: 7528438

Claim:
A non-volatile memory, comprising: a substrate; an assist gate disposed on the substrate, wherein the bottom portion of the assist gate has a first width and the top portion of the assist gate has a second width, and the first width is greater than the second width; a gate dielectric layer disposed between the assist gate and the substrate; a word line disposed on the substrate; a floating gate disposed on one side of the assist gate and located between the word line and the substrate, wherein the bottom portion of the floating gate has a third width and the top portion of the floating gate has a fourth width, the fourth width is greater than the third width, and the assist gate, the floating gate and the word line together form a memory unit; a tunneling dielectric layer disposed between the floating gate and the substrate; an inter-gate dielectric layer disposed between the word line and the floating gate, between the word line and the assist gate and between the assist gate and the floating gate; and a source/drain region disposed in the substrate on the respective sides of the memory unit.