Patent ID: 7791379

Claim:
A comparator circuit comprising: a first, second, third, and fourth transistors coupled in series between a first voltage and a second voltage and having their gates coupled both together and to a junction of said second and third transistors; a fifth, sixth, seventh, and eighth transistors coupled in series between said first voltage and said second voltage and having their gates coupled both together and to a junction of said sixth and seventh transistors; a ninth and tenth transistors coupled between said first voltage and a first node; an eleventh and twelfth transistors coupled between a second node and said second voltage, wherein said ninth and eleventh transistors have their gates coupled together to the gates of said first, second, third and fourth transistors and said tenth and twelfth transistors have their gates coupled together to the gates of said fifth, sixth, seventh, and eighth transistors; a thirteenth transistor coupled between said first node and a junction of said third and fourth transistors; a fourteenth transistor coupled between said second node and a junction of said first and second transistors, wherein said thirteenth and fourteenth transistors have their gates coupled together to receive a first differential input signal; a fifteenth transistor coupled between said first node and a junction of said seventh and eighth transistors; and a sixteenth transistor coupled between said second node and a junction of said fifth and sixth transistors, wherein said fifteenth and sixteenth transistors have their gates coupled together to receive a second differential input signal.