Patent ID: 8344749

Claim:
A method of testing an electronic assembly on a substrate carrier, comprising: providing said electronic assembly including a singulated through-substrate via (TSV) die flip chip attached to a multilayer (ML) package substrate that is disposed on said substrate carrier, wherein said singulated TSV die includes a plurality of TSVs that extend from a back end of the line (BEOL) metal layer within a frontside of said singulated TSV die to a bottomside of said singulated TSV die to a contactable TSV tip, wherein said frontside of said TSVs are coupled to topside substrate pads of said package substrate that are coupled to bottomside BGA substrate pads, and wherein said substrate carrier includes through-holes aligned with said bottomside BGA substrate pads; topside coupling to said contactable TSV tips with a topside coupler that comprises a pattern of coupling terminals that matches a layout of at least a portion of said contactable TSV tips or pads coupled to said contactable TSV tips, and wherein said topside coupler includes lateral connection circuitry that couples pairs of said coupling terminals to provide a plurality of TSV loop back paths; bottomside contacting said BGA substrate pads with a plurality of probe tips that extend through said through-holes to couple to said frontside of said TSVs, and performing electrical testing across said electronic assembly to obtain at least one test parameter.