Patent ID: 8525720

Claim:
A successive approximation analog to digital converter (SA-ADC) to convert a sample of an analog signal to a digital value in a set of iterations, said SA-ADC comprising: a successive approximation register (SAR) logic to generate a sequence of digital codes, the sequence representing a complete set of digital codes required to be generated for the determination of the digital value representing the magnitude of the sample, each digital code in the sequence being generated in a corresponding iteration in the set of iterations, and wherein at least a first subset of the sequence of digital codes is generated according to a non-binary search technique; a binary-weighted digital to analog converter (DAC) to receive the sequence of digital codes and to generate corresponding analog outputs; and a comparator to compare the corresponding analog outputs with a first voltage to generate corresponding comparison results, wherein the comparison results represent the digital value, wherein the binary-weighted DAC contains a plurality of search-window setting elements designed to have values according to a binary-weighted technique.