Patent ID: 7245684

Claim:
A system for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain, wherein said first clock domain is operable with a first clock signal and said second clock domain is operable with a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, the system comprising: a phase detector operable to detect a phase difference between said first clock signal and said second clock signal; a skew state detector disposed in communication with said phase detector for generating a skew state signal which tracks a phase relationship between said first clock signal and said second clock signal relative to a zero point of a timing window corresponding to said second clock signal; and a synchronizer control signal generator, responsive to said skew state signal, for generating at least one control signal according to a value of said skew state signal.