Patent ID: 8196082

Claim:
A method of assigning a plurality of signals of a circuit design to a plurality of input pins of a component having asymmetric delays, the method comprising: using at least one processor programmed to perform operations including: determining a respective latency of each signal-pin combination of the plurality of signals and plurality of input pins as a function of: an arrival time of the signal at a respective driver pin; a transit delay time to route the signal from the respective driver pin to the input pin; and a processing delay time attributable to processing by the component of a signal received by the input pin; selecting a first one of the respective latencies as a latency threshold; determining whether a one-to-one signal-to-pin assignment exists that includes the plurality of signals and includes only signal-pin combinations having latencies less than or equal to the latency threshold; and in response to determining that a one-to-one signal-to-pin assignment that includes the plurality of signals and includes only signal-pin combinations having latencies less than or equal to the latency threshold exists, storing the one-to-one signal-to-pin assignment.