Patent ID: 7382164

Claim:
A glitch suppressing apparatus, comprising: a first switch, for receiving a first input signal and a second input signal, for determining whether or not to output the second input signal according to the first and second input signals, wherein the second input signal is an inverted signal of the first input signal; a second switch, for receiving the first input signal, the second input signal and a first logic signal, for determining whether or not to output the first logic signal according to the first input signal and the second input signal, wherein outputs of the first switch and the second switch form a first signal; a first delay circuit, for receiving the first signal and delaying the negative edge of the first signal to generate a first delay signal; a first logic circuit, for receiving the first signal and the first delay signal to generate a second logic signal; a first inverter, for receiving and inverting the second logic signal to generate a first output signal; a third switch, for receiving the first input signal, the second input signal and the second logic signal, for determining whether or not to output the second logic signal according to the first input signal and the second input signal; a fourth switch, for receiving the first input signal and the second input signal, for determining whether or not to output the second input signal, wherein the outputs of the third switch and the fourth switch form a second signal; a second delay circuit, for receiving the second signal and delaying the positive edge of the second signal to generate a second delay signal; a second logic circuit, for receiving the second signal and the second delay signal to generate the first logic signal; and a second inverter, for receiving and inverting the first logic signal to generate a second output signal.