Patent ID: 7416933

Claim:
A method of forming complementary transistors on a semiconductor assembly comprising: forming a metal dielectric layer simultaneously over a first region having a concentration of n-type conductive dopants and a second region having a concentration of p-type conductive dopants; forming an Al 2 O 3 layer on the metal dielectric layer in both the first region and the second region; masking the Al 2 O 3 layer overlying the first region; removing the Al 2 O 3 layer overlying the first region; forming a silicon material directly on the metal dielectric layer in the first region and the Al 2 O 3 layer in the second region; forming an NMOS transistor comprising metal-silicon bonds that create predominately Fermi level pinning near the valance band; and forming a PMOS transistor comprising metal-silicon bonds that create predominately Fermi level pinning near the conductive band.