Patent ID: 7952911

Claim:
A static random access memory (SRAM) cell array structure comprising: a first and second conductive line coupled to a column of SRAM cells, the first and second conductive lines being substantially parallel to each other and formed by a first metal layer, wherein during a write operation, when voltage at the first conductive line decreases from a high voltage (Vcc) to a low voltage (Vss), voltage at the second line stays at the Vcc; and a third conductive line placed between the first and second conductive lines, and spanning across the column of SRAM cells without making conductive coupling thereto, the third conductive line being also formed by the first metal layer, wherein during the write operation, voltage at the third conductive line decreases from the Vcc to the Vss to further decrease the voltage of the first conductive line from the Vss to a voltage (Vneg) lower than the Vss.