Patent ID: 7627065

Claim:
A data communications system comprising: a source clock signal; a first clock domain comprising a first clock signal which is derived from the source clock signal, wherein the first clock signal has a first frequency; and a second clock domain comprising a second clock signal which is derived from the source clock signal, wherein the second clock signal has a second frequency which is different from the first frequency, and wherein a ratio of the first frequency to the second frequency is N:M; wherein the first clock domain includes circuitry which is configured to: receive values indicative of N and M; initialize a count to N, in response to detecting N is less than 2*M; and initialize the count to M, in response to detecting N is not less than 2*M; wherein each cycle of the first clock signal, the circuitry is configured to: add a value equal to (M−N) to the count and assert a sample enable signal, in response to determining the count is greater than or equal to N; add a value equal to M to the count and negate the sample enable signal, in response to determining the count is not greater than or equal to N.