Patent ID: 7013398

Claim:
A data processor comprising at least two processor cores, each said processor core having a first interface supporting a first bus coupled to an associated one of at least two program memories, a second interface supporting a second bus coupled to a common data memory accessible by each of said at least two processor cores, and a third interface supporting a third bus coupled to at least one input/output device accessible by each of said at least two processor cores, each of said first, second and third buses comprise an address bus that is sourced from one of said processor cores and a data bus, where said at least two processor cores are contained within a single integrated circuit package, and where said integrated circuit package is installed within a mobile station, where a first processor core functions as a CPU for controlling the overall operations of said mobile station, including a user interface, and where a second processor core functions as a DSP for controlling aspects of the wireless operation of said mobile station.