Patent ID: 7701780

Claim:
A method for operating an array of non-volatile memory cells, the method comprising: biasing a first select gate transistor coupled to a string of memory cells at substantially 0 volts; biasing a second select gate transistor coupled to the string at substantially 0 volts; extracting electrons accumulated in a dielectric layer in association with a diffusion region between the first select gate transistor and a first edge memory cell stack of the string by applying a first healing voltage to a first edge word line to provide a potential difference between the first edge memory cell stack and the first select gate transistor that creates a lateral electric field opposite in direction to a lateral electric field created during an erase operation; and extracting electrons accumulated in a dielectric layer in association with a diffusion region between the second select gate transistor and a second edge memory cell stack of the string by applying a second healing voltage to a second edge word line to provide a potential difference between the second edge memory cell stack and the second select gate transistor that creates a lateral electric field opposite in direction to a lateral electric field created during an erase operation.