Patent ID: 7109077

Claim:
A method for forming MOS transistors, comprising: providing a semiconductor substrate comprising a first region and a second region; forming a gate dielectric layer on said semiconductor substrate over said first region and said second region; forming a polysilicon layer over said gate dielectric layer containing 0 to 50 atomic percent of germanium; forming a metal layer on said polysilicon layer over said first region of said semiconductor substrate; reacting said metal layer and said polysilicon layer to form a silicide layer over said first region of said semiconductor substrate and contacting said gate dielectric layer; forming a cladding layer over said silicide layer and said polysilicon layer, wherein said cladding layer comprises a refractory metal; forming a gate electrode comprising said silicide layer and said cladding layer over said first region of said semiconductor substrate; and forming a gate electrode comprising said polysilicon layer and said cladding layer over said second region of said semiconductor substrate.