Patent ID: 7680180

Claim:
A decision feedback equalizer system configured to equalize an input signal and to compensate for a phase factor component generated in the system such that an output signal decoded by the system reduces the influence by the phase factor component, the system comprising: a linear feed-forward filter circuit configured to provide a linearly filtered output signal based on the input signal, the linearly filtered output signal containing the phase factor component; a linear or non-linear feedback filter circuit configured to provide an output feedback filter circuit signal; and a composite trellis decoder circuit coupled to the linear feed-forward filter circuit, the composite trellis decoder circuit including a state metrics comparator and configured to: process a combined signal input into the composite trellis decoder circuit in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal in the state metrics comparator, the combined signal being based on a combination of at least the linearly filtered output signal and the output feedback filter circuit signal, provide a trellis-decoded output signal determined by a state metrics comparator output signal, the state metrics comparator output signal being produced by the state metrics comparator as a result of the processing a composite trellis diagram, wherein the trellis-decoded output signal is supplied as an input to the linear or non-linear feedback filter circuit, and generate a particular phase output of the combined signal, determined by the state metrics comparator output signal as the decoded output signal, wherein the linear or non-linear feedback filter circuit is coupled to the composite trellis circuit and configured to receive and process the trellis-decoded output signal from the composite trellis circuit, and wherein the processing the combined signal input into the composite trellis decoder circuit compensates for the phase factor component present in the linearly filtered output signal.