Patent ID: 7554997

Claim:
A system for monitoring packetized data traffic between user terminals of a local area network (LAN) and a wide area network (WAN) interface to the internet, said system comprising an integrated router and switch fabric architecture; an Ethernet switch having a plurality of ports that are adapted to be coupled to said user terminals of said LAN; a processor and switch fabric coupled to said Ethernet switch and being operative to route packets from said Ethernet switch as sourced thereto from user terminals to said processor for delivery to said WAN interface, and to route packets supplied thereto to said Ethernet switch for delivery via ports thereof to destination user terminals and said processor is connected directly between said switch fabric and said WAN interface and further comprising a motherboard on which the processor and switch fabric are positioned and a Peripheral Component Interconnect (PCI) bus interfacing the processor and switch fabric; and a monitoring terminal coupled to one of said plurality of ports of said Ethernet switch, and being operative to monitor all traffic between said WAN interface and said plurality of ports of said Ethernet switch, wherein said Ethernet switch is operative to mirror all traffic between said WAN interface and said plurality of ports of said Ethernet switch to said monitoring terminal, wherein connectivity between said processor and said switch fabric is established by way of a virtual trunk link therebetween wherein the processor and switch fabric are automatically configured by the processor in response to virtual LAN (VLAN) address-containing user commands to insert VLAN tags into frames, wherein the VLAN tags correspond to VLAN data that identify VLAN's for transport of communications signals transported from the router to the switch fabric and from the switch fabric to are router and used by said processor for updating a new VLAN and for tagging packets wherein requisite variables for VLAN tags are performed automatically from the processor, and said processor includes a port to which the switch fabric is coupled and designated as a mirroring port.