Patent ID: 8099651

Claim:
A method for detecting address errors and data errors using error-detection bits comprising: generating address check bits from a write address, wherein each of the address check bits is generated as a compressing function of at least two-thirds of address bits in the write address; concatenating the address check bits with write data to be written to a memory at a location indicated by the write address to form a check word; generating an address-data codeword from the check word using a linear block code generator; storing the address-data codeword in an error-check portion of the memory at a location indicated by the write address; storing the write data to a data portion of the memory at a location indicated by the write address; reading read data from the data portion of the memory at a location indicated by a read address; reading a stored codeword from the error-check portion of the memory at a location indicated by the read address; generating address read check bits from the read address, wherein each of the address read check bits is generated as the compressing function of at least two-thirds of address bits in the read address; concatenating the address read check bits with read data from the memory at the location indicated by the read address to form a read-check word; generating an address-data-error codeword from the read-check word using the linear block code generator; comparing the stored codeword to the address-data-error codeword to determine mis-matches; when no mis-matches are detected, sending the read data to a requestor; when the stored codeword and the address-data-error codeword mis-match, decoding a syndrome generated by the mis-match to determine when an error in the address read check bits occurs and signaling an address error; when the error is in the read data, using a difference of the stored codeword to locate and correct a correctable error in the read data to generate corrected read data, or using a difference of the stored codeword to locate but not correct an un-correctable error in the read data and signaling a data error; sending the corrected read data or signaling the data error or the address error to the requestor; wherein the write data comprises 64 data bits and the address-data codeword comprises 12 bits of a (84,72) correction code, whereby data correction is attempted in a subset of mis-matches.