Patent ID: 8924901

Claim:
A method for performing circuit synthesis, the method comprising: receiving a cell in a circuit design that is to be optimized; performing, by a computer, one or more table lookup operation on one or more tables based on information associated with the cell to obtain a set of optimal cell configurations, wherein said performing one or more table lookup operations includes: performing a table lookup operation based on a library arc group for the cell to obtain a logical effort value for the cell; performing a table lookup operation based on a library arc group for a driver cell that drives an input of the cell to obtain a logical effort value for the driver cell; determining an output load value that is being driven by the cell; computing an optimal input capacitance value for the cell based on the logical effort value for the cell, the logical effort value for the driver cell, and the output load value; and identifying one or more cells in a cell library based on the optimal input capacitance value; and replacing the cell in the circuit design with a cell configuration selected from the set of optimal cell configurations.