Patent ID: 8466727

Claim:
A method for detecting a disturbance of a state of a master-slave flip-flop of synchronous type, the master-slave flip-flop comprising two bistable circuits in series, the method comprising: triggering, when two terminals of application of triggering signals receive the triggering signals, the two bistable circuits by two first signals different from each other, wherein each bistable circuit of the two bistable circuits comprises a triggering terminal; generating, by a first logic circuit, two second signals providing an indication as to a presence of a possible disturbance of the state of the master-slave flip-flop by: generating a first of the two second signals by comparing, at a first time, a first level of an intermediary junction point between the two bistable circuits to a second level present at the input of the master-slave flip-flop, the first of the two second signals having a value indicating a disturbance of the state of the master-slave flip-flop when the first level differs from the second level at the first time; and generating a second of the two second signals by comparing, at a second time, different than the first time, the first level of the intermediary junction point to a third level present at an output of the master-slave flip-flop, the second of the two second signals having a value indicating a disturbance of the state of the master-slave flip-flop when the first level differs from the third level at the second time; and outputting, by an output terminal, the second signals to a detector circuit arranged to determine whether there is a disturbance of the state of the master-slave flip-flop when the first of the two second signals generated at the first time or the second of the two second signals generated at the second time has a value indicating a disturbance of the state of the master-slave flip-flop.