Patent ID: 8571068

Claim:
A network component comprising: a source-delay locked loop (S-DLL); a source timestamp queue (S-Q) coupled to the S-DLL; a switch fabric coupled to the S-Q such that the S-Q is positioned between the switch fabric and the S-DLL; a generation timestamp queue (G-Q) coupled to the S-DLL and the switch fabric but not directly coupled to the S-Q; a receiving Media Access Control (MAC) component coupled to the switch fabric such that the switch fabric is positioned between the S-Q and the receiving MAC component; a receiving Physical (PHY) layer component coupled to the receiving MAC component such that the receiving MAC component is positioned between the receiving PHY layer component and the switch fabric; a forwarding MAC component coupled to the switch fabric such that the switch fabric is positioned between the S-Q and the receiving MAC component; a forwarding PHY layer component coupled to the forwarding MAC component such that the forwarding MAC component is positioned between the forwarding PHY layer component and the switch fabric; an oscillation (OSC) circuit coupled to the S-DLL component; and a local time component coupled to the S-DLL, wherein the S-DLL is configured to couple to an absolute timing component, and wherein the network component operates in the electrical domain.