Patent ID: 7005906

Claim:
The semiconductor integrated-circuit device, comprising: a plurality of flip-flop circuits for acquiring and holding signals by use of clock signals; and a plurality of signal transferring paths each including a plurality of CMOS-constructed logic gate circuits provided between one pair of flip-flop circuits within said plurality of flip-flop circuits; said plurality of signal transferring paths further including: a first signal transferring path in which said plurality of logic gate circuits are constituted by enhancement-type MOSFETs, said first signal transferring path providing a signal transferring delay time equal to, or less than, a permissible signal transferring delay time; a second signal transferring path in which, among all said plurality of logic gate circuits, a logic gate circuit having a delay time longer than said permissible signal transferring delay time when the logic gate circuit is constituted by an enhancement-type MOSFET is replaced with a depletion-type MOSFET so that the second signal transferring path may provide a signal transferring delay time equal to, or less than, said permissible signal transferring delay time; and wherein the depletion-type MOSFET constituting the logic gate circuit to be replaced is formed by applying a manufacturing step for depletion to a MOSFET having the same pattern and size as those of the enhancement-type MOSFET that has not been replaced.