Patent ID: 7761285

Claim:
A method of detecting a predetermined data processing condition in either of first and second bus signal architectures that respectively produce first and second combinations of active and inactive signals when the predetermined bus signal condition exists therein, comprising: programming a lookup table to have an active bit at a first location therein if the predetermined bus signal condition is to be detected with respect to said first bus signal architecture using said first signal combination; programming the lookup table to have an active bit at a second location therein if the predetermined bus signal condition is to be detected with respect to said second bus signal architecture using said second signal combination; applying a selected one of said first and second signal combinations produced by the associated one of said first and second bus signal architectures to the lookup table; and outputting from the lookup table, in response to the applied one of said first and second signal combinations, the associated one of said active bit at said first location and said active bit at said second location.