Patent ID: 8301990

Claim:
A programmable compute unit for executing a Viterbi decode, the programmable compute unit comprising: forward-path circuitry for (i) accumulating a best path to each state in each stage in a decoded window of received data in an internal register and (ii) storing in a bit FIFO, in parallel, a plurality of survivor trace-back information bits for a plurality of states; trace-back circuitry for selecting an optimal best path through a Viterbi trellis comprising the accumulated best paths by reading, one bit at a time, trace-back information bits from the bit FIFO, beginning with a survivor bit of a last-stage best path; and output circuitry for generating, in response at least in part to a current bit FIFO address, (i) a next bit FIFO address by subtracting a given Viterbi constraint length factor from higher-order bits of the current bit FIFO address and concatenating, to a result of the subtraction, lower-order bits of the current bit FIFO address and a survivor trace-back information bit and (ii) a decoded output bit for a stage previous to a current stage.