Patent ID: 7539966

Claim:
A method of automating a determination of at least one optimal edit location on an integrated circuit for a purpose of making layout structural changes while maintaining logic design integrity, comprising method steps of: a. providing a database for said integrated circuit, said database including functional unit placement and connectivity data including conducting net data, and building block data of different functional units and features in layout form, said database containing said functional unit placement and connectivity data, and said building block data of different functional units and features being in polygon form; b. providing layer-by-layer layout information for said integrated circuit; c. providing an interface with said database to acquire all feature polygons on a given integrated circuit design; d. applying user defined constraints and limitations provided by a user to optimize edit location searches; e. using enhanced algorithms to find, from said database and said layer-by-layer layout information, the at least one optimal edit location under said user defined constraints; and f. reporting said at least one optimal edit location to said user.