Patent ID: 8071437

Claim:
A method of fabricating an efuse, a resistor and a transistor comprising: providing a substrate; forming a transistor gate, a resistor, and an efuse on the substrate, wherein the transistor gate, the resistor and the efuse together comprise a first dielectric layer, a polysilicon layer, a hard mask; forming a source/drain doping region in the substrate near the transistor gate; removing the hard mask in the resistor and in the efuse; performing a salicide process to form a silicide layer in the source/drain doping region, the resistor and the efuse, respectively; forming a planarized second dielectric layer on the substrate, and exposing the polysilicon in the transistor gate, in the resistor and in the efuse; removing the polysilicon in the transistor gate to form a recess; and forming a metal layer filling up the recess.