Patent ID: 8381154

Claim:
A method of manufacturing a hardware circuit component for executing multiple sum-of-products operations, characterised by the steps of: receiving a set of multiplexed sum-of-products functions of a plurality of operands, any one of which functions can be selected in dependence upon a select value by multiplex operations; re-arranging the sum-of-products functions; merging the rearranged set of sum-of-products functions into a single merged sum-of-products function containing one or more multiplexing operations; generating a layout design in dependence upon the single merged sum-of-products function; and manufacturing a hardware circuit component from the layout design; and in which the step of re-arranging the multiple sum-of-products functions comprises aligning the elements of the set of sum-of-products functions in such a manner that the amount of multiplexing in the single merged sum-of-products function is less than in the input set of sum-of-products functions.