Patent ID: 7230870

Claim:
A semiconductor memory device including a plurality of cells in need of refreshing for data retention, in which the refresh period for a fail cell with regard to refreshing is made shorter than the refresh period for normal cells, and in which, if, in refreshing a cell of a first address, generated responsive to a refresh command, a second address, different from said first address as to the value of a predetermined bit, is determined, based on the pre-programmed information, as corresponding to a fail cell, the cell of said second address is refreshed, said semiconductor memory device further comprising a control circuit for exercising control so that, if the second address, different from said first address generated responsive to a refresh command as to the value of a predetermined bit, is determined, based on said pre-programmed information, as corresponding to a fail cell, the cell of said second address only is refreshed without refreshing the cell of the first address.