Patent ID: 7269091

Claim:
Integrated memory circuitry, comprising: a plurality of rows of word lines; at least one word line driver coupled to at least one of said plurality of rows of word lines and coupled to receive a signal, DOUT, that causes said at least one word line driver to drive the voltage on said at least one word line between HIGH and LOW, said at least one word line driver comprising: a first transistor coupled to said at least one word line and is selectively activated by DOUT; and current limiting protection circuitry coupled to said first transistor and operative to drive the word line voltage on said at least one word line to a LOW voltage and to prevent current on said at least one word line from exceeding a predetermined current level while the word line voltage is LOW, said current limiting protection circuitry comprising: a second transistor coupled to said first transistor and a low voltage source, said second transistor providing a low impedance current path for driving said at least one word line down to said LOW voltage when turned ON, wherein the low impedance current path is utilized for a predetermined period of time after DOUT transitions to a state that causes said at least one word line driver to pull said at least one word line down to a LOW voltage; and high impedance circuitry coupled to a node formed between said first and second transistors and said low voltage source, said high impedance circuitry providing a high impedance current path that limits leakage current on said at least one word line when said at least one word line is pulled LOW.