Patent ID: 8735250

Claim:
A method of forming a gate of a semiconductor device, the method comprising: forming first and second dummy gate electrodes on first and second regions of a substrate, respectively; forming gate spacers on opposing sidewalls of each of the first and second dummy gate electrodes; forming an interlayer dielectric film on the gate spacers and on the first and second dummy gate electrodes to provide an n-type transistor in the first region and a p-type transistor in the second region; forming first and second recesses in the first and second regions, respectively, by removing the first and second dummy gate electrodes; forming a high-k layer by providing a high dielectric constant material in the first and second recesses and on the interlayer dielectric film; forming a first sacrificial layer on the high-k layer, the first sacrificial layer substantially filling the first and second recesses; selectively removing the first sacrificial layer from the second recess while at least a portion of the first sacrificial layer remains in the first recess; providing a first metal within the second recess; and after providing the first metal within the second recess, removing the first sacrificial layer from the first recess and providing a second metal substantially filling the first and second recesses.