Patent ID: 7882405

Claim:
A flash memory device comprising: a flash memory array; a set of non-volatile redundancy registers; pads to couple to an external tester through a five-wire connection during a testing of the flash memory device; a serial interface to couple to the pads to decode a set of serial commands exchanged between the external tester and the flash memory device through a single bi-directional pad included in the pads; and testing logic coupled to the serial interface and configured to: accept the set of serial commands from the serial interface; generate a test pattern based on the set of serial commands decoded by the serial interface; erase the array; program the array with the test pattern; read the array and compare results from reading of the array with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and generate redundancy information if the errors can be repaired; and program the redundancy information into the non-volatile redundancy registers, wherein the serial interface comprises a state machine formed from a status flip-flop and a first combinatorial logic block having a plurality of inputs, the state machine configured to determine a future state based on a current state and the plurality of inputs, wherein the plurality of inputs includes: a busy input that carries a signal indicating whether a routine is currently being performed or is completed; a fuse input that controls a permanent disablement of the serial interface; an instruction input that indicates a complete acquisition of an instruction code; an address input that indicates a complete acquisition of an address; and a data input that indicates a complete acquisition of data.