Patent ID: 8797069

Claim:
A Radio Frequency (RF) quadrature clock divider comprising: positive and negative differential RF clock inputs; four clocked inverter stages connected in a serial ring formation, each clocked inverter stage comprising a pair of stacked PMOS transistors connected to a pair of stacked NMOS transistors; and an inverter interposed between each clocked inverter stage; wherein one of the PMOS transistors of each clocked inverter stage is connected to a positive voltage supply node and one of the NMOS transistors is connected to a ground node; wherein the gates of one PMOS transistor and one NMOS transistor of each clocked inverter stage are connected together to form an inverter; and wherein the gate of one PMOS transistor and one NMOS transistor of each clocked inverter stage are each connected to a different input clock, such that the positive and negative inputs to the PMOS and NMOS transistors alternate at each successive clocked inverter circuit in the ring.