Patent ID: 6859386

Claim:
A semiconductor memory device comprising: a memory cell storing data; a word line connected to said memory cell; a pair of bit lines connected to said memory cell and each having a first capacitance value; a bit line precharge circuit precharging said pair of bit lines to a power source potential; a boosted voltage generating circuit generating a voltage of a first potential higher than said power source potential; and a word line activating circuit receiving said voltage of the first potential from said boosted voltage generating circuit and activating said word line with said voltage of the first potential, wherein said memory cell includes: first and second inverters each of which has a load element and a drive element and which are cross-coupled; a first storage node connected to an output node of said first inverter and an input node of said second inverter and having a second capacitance value which is equal to or larger than ⅛ of said first capacitance value; a second storage node connected to an output node of said second inverter and an input node of said first inverter and having said second capacitance value; and first and second gate elements connecting said first and second storage nodes to one bit line in said pair of bit lines and the other bit line, respectively, and current drivability of said drive element is lower than twice of current drivability of said first and second gate elements.