Patent ID: 7249210

Claim:
A processing system, comprising: a bus; a plurality of processors coupled to the bus; and a bus arbiter configured to assign a second tier weight to one or more of the processors, and sequentially grant bus access to the one or more processors having a second tier weight during an initial portion of a bus interval based on the assigned second tier weights, the bus arbiter being further configured to grant bus access to any one of the processors during the initial portion of the bus interval in response to a first tier request from said any one of the processors having a first tier weight, for each of the one or more of the processors granted access during the initial portion of the bus interval, the tier weight associated with a corresponding tier request is reduced for each time slot within the initial portion of the bus interval a processor has been granted access, the bus arbiter being further configured to reset the first tier weight of the one or more processors at the beginning of a quality of service interval wherein the length of the quality of service interval is not equal to the length of the bus interval.