Patent ID: 7176085

Claim:
A method of manufacturing a split gate type memory device, comprising: forming a first conductive layer on a semiconductor substrate; forming mask patterns on the first conductive layer to define at least a pair of first openings to expose the first conductive layer; forming intergate oxide films by selective thermal oxidation of the first conductive layer exposed by the mask patterns; forming a conformal capping oxide film on the mask patterns and the intergate oxide films; exposing a portion of the mask patterns by removing a portion of the capping oxide film between the intergate oxide films; defining a second opening by removing the exposed mask patterns using the remaining capping oxide film as an etch mask; removing the remaining capping oxide film; defining a third opening by etching the first conductive layer using the remaining mask patterns and the intergate oxide films as etching masks; forming an insulating film plug by filling the third opening to avoid a step with the mask patterns; exposing side faces of the insulating film plug by removing the mask patterns; forming a pair of floating gates by dry etching portions of the first conductive layer using the intergate oxide films as etch masks; forming a tunnel insulating film on side walls of each floating gate; and, forming spacer type control gates by self aligning on side walls of the insulating film plug.