Patent ID: 7203081

Claim:
A semiconductor memory device which includes a Content Address Memory “CAM”) portion capable of holding entry data, comparing input comparison data with the entry data, and outputting a result of the comparison, the semiconductor memory device further comprising: a control circuit which fetches a result of a comparison of a part of bits of the entry data with corresponding bits of the comparison data and prohibiting a comparison of residual bits in the entry data with corresponding bits of the comparison data when the result of the comparison is mismatched; wherein the CAM portion has first and second memory cell groups, first and second comparison data amplifiers, and first and second write amplifiers; the first and second memory cell groups have a plurality of word lines, a plurality of comparison data lines, and a plurality of memory cells; the plurality of comparison data lines in the first memory cell group are connected to the first comparison data amplifier; the plurality of comparison data lines in the second memory cell group are connected to the second comparison data amplifier; wherein the part of bits of the entry data is held in the memory cells in the first memory cell group; the residual bits of the entry data are held in the memory cells in the second memory cell group; and the control circuit outputs a signal which disables the second comparison data amplifier when the result of the comparison is mismatched.