Patent ID: 8373251

Claim:
A semiconductor device comprising: a first semiconductor chip; a second semiconductor chip; and first and second bonding wires that connect said first semiconductor chip and said second semiconductor chip, wherein said first semiconductor chip includes: a first transmitting circuit and a first receiving circuit that are formed over a first substrate; a first multi-layer interconnect layer that is formed over said first substrate; a first inductor that is provided in said first multi-layer interconnect layer; and a second inductor that is provided in said first multi-layer interconnect layer and is disposed above said first inductor, and said second semiconductor chip includes: a second transmitting circuit and a second receiving circuit that are formed over a second substrate; a second multi-layer interconnect layer that is formed over said second substrate; a third inductor that is provided in said second multi-layer interconnect layer; and a fourth inductor that is provided in said second multi-layer interconnect layer and is disposed above said third inductor, wherein one of said first inductor and said second inductor is connected to one of said first transmitting circuit and said second transmitting circuit, wherein one of said third inductor and said fourth inductor is connected to the other transmitting circuit of said first transmitting circuit and said second transmitting circuit, wherein, in the event that one of said first inductor and said second inductor is connected to said first transmitting circuit, the other inductor of said first inductor and said second inductor is connected to said second receiving circuit, wherein, in the event that one of said first inductor and said second inductor is connected to said second transmitting circuit, the other inductor is connected to said first receiving circuit, wherein, in the event that one of said third inductor and said fourth inductor is connected to said first transmitting circuit, the other inductor of said third inductor and said fourth inductor is connected to said second receiving circuit, and wherein, in the event that one of said third inductor and said fourth inductor is connected to said second transmitting circuit, the other inductor is connected to said first receiving circuit.