Patent ID: 7109772

Claim:
A flipflop circuit, comprising: a clock input for applying a clock signal; a data input for applying a data signal; an noninverted output; an inverted output; a first holding element comprising a first feedback loop comprising a first node and a second node; and a second holding element comprising a second feedback loop comprising a third node and a fourth node; wherein the first node is coupled to the fourth node via a first signal path and the second node is coupled to the third node via a second signal path exclusive of the first signal path, the second signal path including a delay element in the form of a transmission gate permanently switched on when the circuit is in a normal operating mode; wherein the first holding element is configured such that at a first clock level of the clock signal the logic value of the data signal is transferred to the first holding element and the logic value of the data signal is made available on the first node, and the inverted logic value of the data signal is made available on the second node; and wherein the second holding element is configured such that at a second clock level of the clock signal (i) the logic value of the data signal is transferred, and inverted, from the first node to the fourth node, thereby making the inverted logic value of the data signal available on the fourth node, and (ii) the inverted logic value of the data signal is transferred, and inverted, from the second node to the third node, thereby making the noninverted logic value of the data signal available on the third node; wherein the fourth node in the second feedback loop corresponds to the noninverted output and the third node in the second feedback loop corresponds to the inverted output.