Patent ID: 6897519

Claim:
A method of operating a floating gate pixel, comprising: providing a P type silicon substrate; forming an N well in said substrate, wherein said N well is N type silicon and has no contact regions formed therein; forming a P well in said N well, wherein said P well is P type silicon; forming a contact region in said P well, wherein said contact region is P + type silicon and is the only contact region formed in said P well; forming a gate oxide on said substrate, wherein said gate oxide has a thickness which is sufficiently small to allow tunneling through said gate oxide; forming a floating gate on said gate oxide, wherein said floating gate is directly over part of said P well and part of said N well and the only electrical connection to said floating gate is to connect said floating gate to a means for determining the potential of said floating gate; resetting the potential between said P well and said substrate during a reset period wherein a tunneling current between said P well and said floating gate resets the potential of said floating gate; accumulating charge at the PN junction between said P type silicon substrate and said N well during a charge integration period, thereby changing the potential of said N well, said P well, and said floating gate and wherein said charge integration period follows said reset period; and reading the potential of said floating gate after said charge integration period has been completed.