Patent ID: 8049328

Claim:
A semiconductor device, comprising: a substrate including a first semiconductor die or component; a first interconnect structure formed over a first surface of the substrate including: a first conductive layer formed over the first surface of the substrate, a first insulation layer formed over the first conductive layer, a second conductive layer formed over the first insulation layer, a second insulation layer formed over the second conductive layer, and a conductive pillar formed over the second conductive layer and the substrate; a second semiconductor die or component mounted to the first interconnect structure over the substrate; an encapsulant deposited over the second semiconductor die or component and first interconnect structure; a via having a tapered sidewall formed through a second surface of the substrate, opposite the first surface of the substrate, the via extending through the first semiconductor die or component to the first conductive layer; a third insulation layer conformally applied over the tapered sidewall of the via; and a bump partially disposed within the via and extending above the second surface of the substrate.