Patent ID: 7979223

Claim:
A system for power hardware in the loop testing comprising: a power system and a control system, the power system connected to a power converter of a device under test, the control system being in communication with the power system and the power converter, the control system determining the voltage input to the power system by utilizing the voltage output of the power converter, the voltage input determination being made by a control algorithm comprising v Ok = Sx k + Pv Ik + Qi Ak + 1 where ⁢ : S = 1 T ⁢ ( CL A ⁢ T C + L B T + R B + R C T + CR C - L B - C ⁢ L B + R B ⁢ T T + CR C ) P = 1 + C T + CR C ⁢ L B + R B ⁢ T T Q = - L A + R A ⁢ T T - L B + R B ⁢ T T - C T + CR C ⁢ L A + R A ⁢ T T ⁢ L B + R B ⁢ T T wherein symbols in the equation refer to a circuit for a decoupling filter in the control system with: V i representing the external voltage; V o representing the controlled voltage; the filter inductances modeled like an inductor in series with a resistance whose values are represented by R A and L A for the inductor on the output side and R B and L B for the inductor on the controlled converter side; the filter capacitor modeled like a capacitor in series with a resistance whose values are C and R C ; and T representing the discretization time.