Patent ID: 7919369

Claim:
A method of fabricating a flash memory device, the method: forming a stack layer in a cell region of a semiconductor substrate, wherein the stack layer comprises a tunnel insulating layer, a charge-trapping layer, a blocking oxide layer and a first capping conductive layer; forming a gate insulating layer, a second capping conductive layer and the stack layer in a peri region of the semiconductor substrate; etching the stack layer at a region where a gate will be formed in the peri region, thereby forming a contact hole; forming a metal layer and a hard mask over the stack layer including the contact hole; patterning the stack layer of the cell region and the peri region to form a cell gate in the cell region; and etching the hard mask so that a step formed between the cell region and the peri region is decreased while patterning the second capping conductive layer of the peri region, thereby forming a gate of a transistor in the peri region.