Patent ID: 7855593

Claim:
A semiconductor integrated circuit device comprising: a first circuit block; a second circuit block; and a third circuit block, wherein the first circuit block has a first power supply state in which the operation of internal circuits thereof is guaranteed in accordance with a first instruction from the third circuit block and a second power supply state in which the operation of the internal circuits thereof is not guaranteed in accordance with a second instruction from the third circuit block, wherein the second circuit block has an input unit which receives signals supplied from the first circuit block and the third circuit block, and wherein the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, prohibits receipt of unfixed levels from the first circuit block and causes a fixed level signal to be transmitted to internal circuits of the second circuit block in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block to the second circuit block when the third circuit block instructs the second power supply state to the first circuit block by sending the second instruction to the first circuit block, wherein the third circuit block includes an input circuit to receive a standby signal and a clock signal comprised of a series of clock pulses, wherein the third circuit block operates to generate the control signal to transmit to the second circuit block after the third circuit block receives the standby signal, wherein the third circuit block also generates the second instruction to the first circuit block after the third circuit block receives the standby signal, and wherein the third circuit block generates the control signal for the second circuit block before it generates the second instruction for the first circuit block.