Patent ID: 7075840

Claim:
A memory system, comprising: a memory cell; first and second bitlines operably connected to said memory cell; a write line operably connected to said memory cell; and an equilibration circuit controlled by a reference voltage, said equilibrium circuit connected to said first and second bitlines, said equilibrium circuit comprising first and second pMOS devices in series with said first and second bitlines, respectively, and a third pMOS device connected between said first and second bitlines and wherein the gates of said first, second and third pMOS devices are connected to said reference voltage, wherein said first, second and third pMOS devices operate as resistors in the linear region of MOSFET device operation, and wherein said equilibration circuit is operable: to maintain a predetermined equilibrium condition between said first and second bit lines; and to generate an impedance load in said first and second bit lines at a level that allows generation of differential signals in said bit lines.