Patent ID: 8598660

Claim:
A semiconductor device comprising: a substrate; a well region formed in the substrate; a first shallow trench isolation region formed on and adjacent to the well region, wherein the first shallow trench isolation region is proximate to a body contact doped with the dopants of a first polarity type; a source region formed on the well region and adjacent to the first shallow trench isolation region; a drift region formed in the substrate adjacent to the well region; a second shallow trench isolation region formed on and adjacent to the drift region; a drain region formed on the drift region and adjacent to the second shallow trench isolation region; a gate formed between the source region and the drain region; a sidewall spacer formed adjacent to sidewalls of the gate; and a stress layer deposited over the semiconductor device, wherein the stress layer is also deposited inside the second shallow trench isolation region, and wherein the stress layer is proximate to the drift region.