Patent ID: 8013455

Claim:
A semiconductor device, comprising: an interlayer dielectric layer formed on a surface of a substrate; a plurality of first pads arranged on the interlayer dielectric layer along a first row; a plurality of second pads arranged on the interlayer dielectric layer along a second row; a plurality of first via contact portions extending from the first pads toward the second row; a plurality of second via contact portions extending from the second pads toward the first row; at least one first via plug arranged in the interlayer dielectric layer below each of the first via contact portions such that the at least one first via plug contacts one of the first via contact portions; and at least one second via plug arranged in the interlayer dielectric layer below each of the second via contact portions such that the at least one second via plug contacts one of the second via contact portions, wherein the first via contact portions and the second via contact portions are arranged along a third row between the first row and the second row, the first pads and the second pads include a power pad supplying a power supply voltage, and a signal pad receiving and outputting an electrical signal, one of the first or second via contact portions is connected to the signal pad and each of the via contact portions connected to the signal pad has a width smaller than a width of the signal pad, the other of the first or second via contact portions is connected to the power pad and each of the via contact portions connected to the power pad has a width wider than the width of each via contact portion connected to the signal pad, and the widths of the signal pad, the via contact portions connected to the signal pad and the via contact portions connected to the power pad are parallel to the first, second and third rows.