Patent ID: 7460385

Claim:
A memory circuit arrangement comprising: a cell array substrate, which has an integrated memory cell array contained in a memory circuit, the integrated memory cell array including memory cells; a logic circuit substrate, which has an integrated logic circuit that controls access to the memory cells, the logic circuit substrate being a different substrate than the cell array substrate; the logic circuit substrate has a circuit arrangement of a processor which is suitable for processing program instructions, and the cell array substrate has an analog circuit; wherein the logic circuit substrate has a sense amplifier, with the aid of which a memory state of a memory cell of the memory cell array can be determined; wherein the logic circuit includes at least one of: a control circuit contained in the memory circuit, the control circuit controlling sequences when at least one of reading or writing content of a memory cell of the memory cell array, or a decoding circuit contained in the memory circuit, the decoding circuit selects, in a manner dependent on an address datum, a word line or a bit line connected to a plurality of memory cells of the memory cell array.