Patent ID: 7225422

Claim:
A method of designing a logic circuit, the method comprising: providing a leaf cell including at least one transistor, the leaf cell being suitable for use as a 1-cell or a 0-cell; tiling a first array of abutting leaf cells using at least one 1-cell and at least one 0-cell to define at least one logical expression by the relative positions of the array cells, wherein the first array is characterized by a set of rows and a set of columns, and wherein leaf cells in the set of rows define the at least one logical expression, and wherein the set of columns corresponds to inputs of the at least one logical expression; and adding length optimized column interconnects that selectively interconnect leaf cells in an array column, wherein column interconnects that correspond to a true input contact a gate electrode of the transistor of each 0-cell in the array column, and wherein column interconnects that correspond to a complement input contact a gate electrode of the transistor of each 1-cell in the array column, such that each true input signal terminates at a last 0-cell in a column and each complement input signal terminates at a last 1-cell in a column.