Patent ID: 7400013

Claim:
A transistor comprising: a substrate; first and second shallow trench isolation regions in said substrate; a substantially U-shaped trench situated in said substrate between said first and second shallow trench isolation regions; a substantially U-shaped gate situated in said substantially U-shaped trench; first and second lightly doped drain (LDD) implant regions situated on opposite sides of said gate; a channel situated below said gate, said channel having a channel length extending substantially from a first diffusion edge of said first LDD implant region to a second diffusion edge of said second LDD implant region; first and second spacers situated on opposite sides of said gate and situated over said substrate; first and second source/drain regions situated in said substrate; a first silicide layer situated on said first source/drain region and situated in alignment with said first spacer and a second silicide layer situated on said second source/drain region and situated in alignment with said second spacer.