Patent ID: 8924455

Claim:
A matrix multiplication circuit, comprising: a plurality of systolic arrays; a pre-processing circuit coupled to the plurality of systolic arrays and configured to: decompose a first input matrix into a first plurality of sub-matrices; and input each of the plurality of sub-matrices to at least a respective one of the plurality of systolic arrays for multiplication with a second input matrix; and a post-processing circuit configured to combine output of the systolic arrays into a result matrix; and wherein the pre-processing circuit is configured to decompose the second matrix into a second plurality of sub-matrices, each sub-matrix of the second plurality of sub-matrices including one or more rows of the second input matrix; and the pre-processing circuit is configured to input, for each systolic array of the plurality of systolic arrays, sequentially input two or more of the second plurality of sub-matrices to the systolic array.