Patent ID: 7511580

Claim:
A charge pump circuit, comprising: a first PMOS transistor; a first NMOS transistor connected with the first PMOS transistor at a CPOUT node that is configured to provide an output signal from the charge pump circuit; a second PMOS transistor connected between a high-voltage supply terminal (VDD) and the first PMOS transistor, the second PMOS transistor being configured to provide a current IUP to the first PMOS transistor; a second NMOS transistor connected between a low-voltage supply terminal (VSS) and the first NMOS transistor, the second NMOS transistor being configured to receive a current IDN from the first NMOS transistor; a capacitor connected to VDD and a gate of the second PMOS transistor; an operational amplifier (OP-AMP) having its negative input and its output connected to the gate of the second PMOS transistor, and its positive input connected to the CPOUT node; a third NMOS transistor connected to the node CPOUT and VSS, the third NMOS transistor configured to be controlled by an external signal ENB; and a fourth NMOS transistor connected between the first NMOS transistor and VSS, the fourth NMOS transistor configured to be controlled by an external signal EN, wherein EN and ENB are complementary signals.