Patent ID: 8859372

Claim:
A method comprising: performing a first well doping on a first active region and a second active region simultaneously; forming a first dummy gate covering a first middle portion of the first active region; forming a second dummy gate covering a second middle portion of the second active region; removing the first and the second dummy gates; after the step of removing the first and the second dummy gates, masking the second middle portion of the second active region with a mask; performing a second well doping on the first middle portion when the mask is on the second middle portion, wherein end portions of the first active region on opposite sides of the first middle portion are masked during the second well doping; after the second well doping, forming a first gate dielectric and a first gate electrode on the first middle portion to form a first transistor; and forming a second gate dielectric and a second gate electrode on the second middle portion to form a second transistor.