Patent ID: 8217486

Claim:
A semiconductor wafer comprising: a semiconductor substrate; a plurality of first epitaxial semiconductor layers of a first general conductivity type grown from the semiconductor substrate, the first epitaxial semiconductor layers standing on the semiconductor at a predetermined interval; a plurality of second epitaxial semiconductor layers of a second general conductivity type grown from corresponding first epitaxial semiconductor layers, the second epitaxial semiconductor layers standing on the semiconductor substrate and being in contact with the corresponding first epitaxial semiconductor layers; a plurality of third epitaxial semiconductor layers of the first general conductivity type grown from corresponding second epitaxial semiconductor layers, the third epitaxial semiconductor layers standing on the semiconductor substrate and being in contact with the corresponding second epitaxial semiconductor layers; and a plurality of insulating layers standing on the semiconductor substrate so that a third epitaxial semiconductor layer, a second epitaxial semiconductor layer, a first epitaxial semiconductor layer, another second epitaxial semiconductor layer and another third epitaxial semiconductor layer are disposed in this order between two insulating layers with no other insulating layer being disposed between the two insulating layers, wherein epitaxial semiconductor layers in contact with the insulating layers are of the same general conductivity type.