Patent ID: 7181589

Claim:
A method for performing address translation in a computer system, comprising: identifying a base virtual address and a block size for a block of memory; adding the block size to the base virtual address to establish an end virtual address for the block of memory; receiving an input virtual address to a location in the memory; determining whether the input virtual address is within a range defined by the base virtual address and the end virtual address; generating an index to a physical base address in a physical base table in response to the virtual address being within the range, the index being generated by: subtracting the base virtual address from the input virtual address to obtain a first index result; subtracting a node block size from the first result to obtain a second index result; identifying particular bits in the second result to obtain the index; generating an offset, the offset being generated by: subtracting the base virtual address from the input virtual address to obtain a first offset result; dividing the first offset result by the node block size to obtain the offset; generating a physical address in response to the offset and the physical base address, the physical address being the physical base address plus the offset.