Patent ID: 8284772

Claim:
A processor-based method for creating a hardware description language (HDL) specification of a network packet processor, comprising: inputting a textual language specification of processing of a type of network packets by the network packet processor, wherein the textual language specification includes at least one memory read action and at least one modification action, each memory read action for reading a stored value from a memory of the network packet processor and each modification action for modifying one of a plurality of fields of the type of network packets; determining a respective availability, relative to a beginning of the type of network packets, of the fields which are read from the type of network packets for the at least one memory read action and the at least one modification action; determining a respective availability, relative to the beginning of the type of network packets, of the stored value read from the memory for the at least one memory read action; determining a look-ahead interval in response to the respective availabilities of the fields that are read from the type of network packets for the at least one modification action and the stored value for the at least one memory read action; determining respective storage classes for the fields which are read from the type of network packets for the at least one memory read action and the at least one modification action, wherein each respective storage class is one of a bus, a register, and a register with bypass; and generating the HDL specification of the network packet processor based on the look-ahead interval and the respective storage classes.