Patent ID: 7094642

Claim:
A method of fabricating a semiconductor device, comprising steps of: (a) forming a gate electrode of a MISFET over a main surface of a first semiconductor region of a first conductivity type formed in a semiconductor body, wherein a gate length of said gate electrode is less than 200 nm; (b) after said step (a), implanting ions in said first semiconductor region to form a second semiconductor region of a second conductivity type opposite to said first conductivity type; (c) after said step (b), forming a side wall spacer on side surfaces of said gate electrode; (d) after said step (c), implanting ions in a first region in said first semiconductor region to form a third semiconductor region of said second conductivity type; (e) after said step (c), implanting ions in a second region deeper than said first region in said first semiconductor region to form a fourth semiconductor region of said second conductivity type; and (f) after said steps (d) and (e), forming a cobalt-silicide layer in said third semiconductor region, wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said third semiconductor region is greater than an impurity concentration of said fourth semiconductor region, and wherein a depth of said fourth semiconductor region is greater than a depth of said third semiconductor region.