Patent ID: 8232837

Claim:
A communication device, comprising: a first input/output terminal; a second input/output terminal; a first JK flip-flop to output a first output signal from a Q-output or a reversed Q-output in response to a first input signal at a J-input and a reversed signal of the first input signal at a K-input; a second JK flip-flop to output a second output signal from a Q-output or a reversed Q-output in response to a second input signal at a J-input and a reversed signal of the second input signal at a K-input; a first logical conversion circuit to control a logic level of a signal input to the first input/output terminal so that the signal input to the first input/output terminal is input to the J-input of the first JK flip-flop as the first input signal and the second output signal is output from the first input/output terminal to an external device; and a second logical conversion circuit to control a logic level of a signal input to the second input/output terminal so that the signal input to the second input/output terminal is input to the J-input of the second JK flip-flop as the second input signal and the first output signal is output from the second input/output terminal to an external device, wherein a clock signal input to a NAND gate at the J-input of the first JK flip-flop is provided by a reversed signal of the Q-output of the second JK flip-flop, a clock signal input to a NAND gate at the K-input of the first JK flip-flop is provided by a reversed signal of the second input signal, a clock signal input to a NAND gate at the J-input of the second JK flip-flop is provided by a reversed signal of the Q-output of the first JK flip-flop, and a clock signal input to a NAND gate at the K-input of the second JK flip-flop is provided by a reversed signal of the first input signal.