Patent ID: 8336002

Claim:
An integrated circuit (IC) design method comprising: providing IC design layout; providing chemical mechanical polishing (CMP) manufacturing data and the IC design layout to a CMP process model; thereafter simulating a CMP process to a material layer using the CMP process model, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; performing circuit timing analysis based on the extracted resistance and capacitance, the circuit timing analysis being performed by using a computer; adjusting spacing and widths of the IC design layout according to the circuit timing analysis; performing a design rule check verification of the IC design layout against at least one design rule in parallel with the adjusting spacing and widths of the IC design layout according to the circuit timing analysis; and making semiconductor circuits according to the IC design layout after the adjusting spacing and widths.