Patent ID: 7930610

Claim:
A system embodied in a hardware system, comprising: a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain; wherein the circuit analysis module is further configured to identify sub-circuits within the DUT; a don't-care analysis module coupled to the circuit analysis module and configured to identify absolute don't-care latches associated with the identified sub-circuits; wherein the circuit analysis module is further configured to identify a logical description of an identified sub-circuit; a sub-circuit exception module coupled to the circuit analysis module and configured to select weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit; and wherein the sub-circuit exception module is further configured to store the selected weighted input values for the identified sub-circuit and to associate the selected weighted input values with the logical description.