Patent ID: 8612371

Claim:
An apparatus comprising: a memory having an address space; a lower-level recognition unit that, for a first set of input patterns loaded into a first lower-level-input-pattern portion of the memory, generates a first set of paths of addresses, wherein the first set of paths of addresses includes a first path for a first pattern in the first set of input patterns and a second path for a second pattern in the first set of input patterns, wherein each respective one of the first set of paths of addresses has a respective series of addresses in the address space based on its corresponding respective input pattern, wherein the lower-level recognition unit outputs a first set of recognition codes for the first set of input patterns based on the first set of paths of addresses, and wherein the first set of recognition codes are loaded as at least part of a first upper-level pattern into an upper-level-pattern portion of the memory; and a upper-level recognition unit that, for the first set of recognition codes loaded as the first upper-level pattern into the upper-level-pattern portion of the memory, generates a third path of addresses, wherein the third path of addresses has a series of addresses in the address space that are based on the first upper-level pattern, and wherein the upper-level recognition unit outputs a first upper-level recognition code for the first set of input patterns based on the third path of addresses.