Patent ID: 8781792

Claim:
A method for optimizing parametric chip yield, comprising the steps of: computing parametric chip yield based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme having multiple voltage bins, wherein the voltage binning scheme includes a set of supply voltage levels and a set of voltage bins corresponding to the supply voltage levels, and wherein the voltage binning scheme comprises, for each of the manufactured chips, i) finding highest voltage level V i at which the chip satisfies power consumption constraints, ii) testing chip performance for supply voltage equal to V i , iii) determining whether the chip performance meets timing constraints, and iv) assigning the chip to a voltage bin U i with voltage level equal to V i if the chip meets the timing constraints, otherwise rejecting the chip; determining whether the parametric chip yield computed is optimal with the given voltage binning scheme, wherein the parametric chip yield is optimal when each of the chips which satisfies the power consumption constraints and the timing constraints of at least one of the voltage bins is assigned to one of the voltage bins; and if the parametric chip yield is not optimal altering the voltage binning scheme and repeating the steps of computing the parametric chip yield and determining whether the parametric chip yield computed is optimal, otherwise leaving the voltage binning scheme unaltered, wherein the method is carried out by a computer device having a processor configured to perform the steps.