Patent ID: 7149880

Claim:
A system comprising: a first multiplexer associated with instruction pointers of a first thread; a second multiplexer associated with instruction pointers of a second thread; a first storage element dedicated to the first multiplexer; and a second storage element dedicated to the second multiplexer, wherein said first and second multiplexers to provide said instruction pointers of said first and second threads for execution in said processor; one of the first and second threads is to be active while the other of said first and second threads is inactive; and said instruction pointers for the active thread are to be delivered to processor logic; if the first thread is inactive, said instruction pointers for the first thread are to be delivered to the first storage element for delivery to the processor logic if the first thread becomes active; and if the second thread is inactive, said instruction pointers for the second thread are to be delivered to the second storage element for delivery to the processor logic if the second thread becomes active.