Patent ID: 7791927

Claim:
A memory circuit, comprising: a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node; a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch; and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make a lingering change in a threshold voltage of the MIS transistor in a first operation and to cause the latch in a second operation to store data responsive to whether a lingering change in the threshold voltage is present, wherein the MIS transistor includes: diffusion regions formed in a substrate; a gate electrode; and sidewalls, wherein a metallurgical junction of each of the diffusion regions is positioned under the gate electrode, and a lateral boundary of a depletion layer in one of the diffusion regions serving as a drain is positioned under a corresponding one of the sidewalls in the first operation.