Patent ID: 6893916

Claim:
A process for forming an integrated circuit structure, comprising the steps of: providing a silicon substrate of a first conductivity type; depositing a first insulating layer over the silicon substrate of the first conductivity type; forming first gate insulating regions in the insulating layer; forming first and second buried silicon regions of a second conductivity type within the silicon substrate of the first conductivity type; depositing a first polycrystalline silicon layer, said first polycrystalline silicon layer contacting said first buried silicon regions; depositing a second insulating layer over the first insulating layer, the first polycrystalline silicon layer and the second buried silicon regions; and depositing a second polycrystalline silicon layer over said second insulating layer and said second buried silicon regions of the second conductivity type, said second buried silicon regions of the second conductivity type being insulated from said second polycrystalline silicon layer.