Patent ID: 7572738

Claim:
A method of fabricating a semiconductor device, the method comprising: (a) forming on a substrate an interconnect stack that includes a plurality of layers with interconnecting metal overlying the substrate; (b) subsequent to step (a), forming a crack stop trench extending through the plurality of layers of the interconnect stack; (c) filling the crack stop trench with a prescribed material; (d) forming on the substrate a dielectric layer that includes an organosilicon material; (e) forming a via photoresist pattern over the dielectric layer; (f) etching an interconnect via in the dielectric layer using the via photoresist pattern as an etch mask; (g) removing the via photoresist pattern; (h) forming a trench photoresist pattern over the dielectric layer; (i) etching an interconnect trench in the dielectric layer using the trench photoresist pattern as an etch mask, said trench being connected to the interconnect via; (j) removing the trench photoresist pattern; (k) forming a barrier layer overlying the interconnect via and the interconnect trench; and (l) completing interconnections by filling the interconnect trench and the interconnect via with copper.