Patent ID: 8455958

Claim:
An insulated gate semiconductor device comprising: a first conductivity type semiconductor substrate having a front surface and a back surface opposite to the front surface; a second conductivity type drift layer on the front surface of the semiconductor substrate; a first conductivity type base layer on the drift layer, the base layer having a cell area; a ring-shaped gate trench located in the cell area and reaching the drift layer by penetrating and dividing the base layer into a channel layer and a floating layer; a second conductivity type emitter region located in the channel layer to be in contact with a side surface of the gate trench; a gate insulating layer on the gate trench; a gate electrode on the gate insulating layer; a first conductivity type well region located on the periphery of the cell area and having a depth greater than a depth of the base layer; an emitter electrode electrically connected to the emitter region; a collector electrode on the back surface of the semiconductor substrate, and a ring-shaped buffer trench located adjacent to and spaced from the gate trench in a length direction of the gate trench, wherein the well region has a first edge in the length direction of the gate trench, and the first edge of the well region is located in an area enclosed by the buffer trench.