Patent ID: 7734938

Claim:
A method of controlling power consumption in a system including first and second serial interface blocks, comprising: transitioning the first serial interface block to a power saving mode in response to a status of a first transmission channel, the first transmission channel configured to forward information from the first serial interface block to the second serial interface block; transitioning the second serial interface block to the power saving mode in response to a status of a second transmission channel, the second transmission channel configured to forward information from the second serial interface block to the first serial interface block; disabling external interface functions of the first and second serial interface blocks; setting the first transmission channel into a suspension state, the first transmission channel associated with a higher impedance during the suspension state, the suspension state being the status which triggers the transition of the first serial interface block to the power saving mode; setting the second transmission channel into the suspension state, the second transmission channel associated with a higher impedance during the suspension state, the suspension state being the status which triggers the transition of the second serial interface block to the power saving mode; releasing the first serial interface block from the power saving mode in response to a first interrupt; activating the second transmission channel; outputting packet data through the activated second transmission channel; releasing the second serial interface block from the power saving mode upon receipt of packet data via the activated second transmission channel; activating the first transmission channel; outputting flag packet data through the activated first transmission channel; and generating a second interrupt indicating that the first and second serial interface blocks have been released from the power saving mode based on the output flag packet data, wherein first and second system clock signals of the first and second serial interface blocks, respectively, are each disabled during the power saving mode.