Patent ID: 7994560

Claim:
An integrated circuit memory cell, comprising: a substrate; at least one transistor produced in an active region comprising, separate from the substrate, a first layer containing a source or drain first region, a second layer above the first layer, and a third layer above the second layer containing a drain or source second region, respectively, which regions are connected by a channel formed in the second layer, and a gate structure adjacent said channel, said gate structure formed in a trench extending into at least the first and second layers; at least one memory cell capacitor positioned laterally adjacent the at least one transistor, comprising a first electrode, a second electrode and a dielectric layer between the first and second electrodes; at least one electrode line connected to the first electrode of the laterally adjacent memory cell capacitor; and at least one bit line located beneath the gate structure; and wherein the second electrode of said capacitor is formed at least partly in the third layer which also contains the drain or source second region of the transistor.