Patent ID: 7360061

Claim:
Apparatus for processing data, said apparatus comprising: a data processing circuit operable in response to program instructions to perform data processing operations; a cache memory coupled to said data processing circuit and operable to store said program instructions; a compressed instruction data memory coupled to said cache memory; and an instruction decompression circuit disposed between said compressed instruction data memory and said cache memory and operable to receive compressed instruction data from said compressed instruction data memory, to decompress said compressed instruction data to form program instructions and to supply said program instructions to said cache memory, wherein said instruction decompression circuit is operable to form a plurality of said program instructions from a mask and a plurality of bit slice specifiers within said compressed instruction data, said mask having bit values specifying whether respective corresponding bit positions within each of said plurality of program instructions have a predetermined default bit value or have bit values specified by a corresponding bit slice specifier, and a programmable default bit value word specifies said predetermined default bit values for respective bit positions within said program instructions.