Patent ID: 7725522

Claim:
A method of multiplying in a multiplier unit a first integer with a second integer to generate a result, wherein each of said first integer and said second integer can be in either signed or unsigned form, said method comprising: receiving at said multiplier unit said first integer, said second integer and type data indicating whether each of said first integer and said second integer is represented in signed form or unsigned form; appending a first extend bit to said first integer and a second extend bit to said second integer to generate a first extended integer and a second extended integer respectively, wherein said first extend bit equals a logic zero if said type data indicates that said first integer is represented in unsigned form and equals the most significant bit of said first integer if said type data indicates that said first integer is represented in signed form, wherein said second extend bit equals a logic zero if said type data indicates that said second integer is represented in unsigned form and equals the most significant bit of said second integer if said type data indicates that said second integer is represented in signed form; performing a signed multiplication operation of said first extended integer and said second extended integer to generate a product; generating an overflow bit indicating whether a result of the multiplication would fit in a number of bits used to represent said result; and providing as outputs said product and said overflow bit if said overflow bit indicates that said result would fit in said number of bits, and a default value and said overflow bit if said overflow bit indicates that said result would not fit in said number of bits.