Patent ID: 7913137

Claim:
An apparatus for testing a plurality of electronic circuits, the apparatus comprising: a plurality of scan chain groups, each scan chain group comprising one or more scan chains and one or more corresponding scan chain group outputs; a plurality of comparator circuits, each comparator circuit comprising a comparator input and a comparator output; an encoder circuit comprising a plurality of encoder inputs and an encoder output, wherein the encoder inputs are coupled to respective comparator outputs; and a plurality of compactors, each compactor comprising an XOR or XNOR tree configured to compact test response values output from the scan chain group outputs of a respective one of the scan chain groups, each compactor further comprising two or more compactor inputs coupled to the scan chain group outputs of the respective one of the scan chain groups and further comprising a compactor output coupled to the comparator input of a respective comparator, the encoder circuit being configured to detect more than two error values output from the compactor outputs.