Patent ID: 7796439

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cell strings arranged along a first direction respectively, each of the memory cell strings including a plurality of memory cells having current paths connected in series along a second direction which is perpendicular to the first direction, each of the memory cells having a charge accumulation layer and a control electrode, the control electrode extending in the first direction and connected to a memory cell located in an adjacent memory cell string; a plurality of bit lines extending in the second direction, each of the bit lines electrically connected to one end of the current path of the associated memory cell string; a source line extending in the first direction and electrically connected to the other end of the current paths of the memory cell strings; a sense amplifier including a plurality of sense amplifier circuits, each of the sense amplifier circuit electrically connected to one of the bit lines, respectively; a data buffer including a plurality of first latch circuits, each of the first latch circuits electrically connected to one of the bit lines; an input terminal holding data from an external device; and a control circuit executing a first verify write operation and a second verify write operation; the first verify write operation including, loading data from the input terminal to each of the first latch circuits, writing each loaded data in the first latch circuits to one of the memory cells connected one of the bit lines, respectively, reading the written data of the memory cells into the sense amplifier circuits, verifying whether threshold voltages based on the written data are larger than a predetermined voltage, and rewiring to a memory cell storing a written data having a threshold voltage which is smaller than the predetermined voltage; and the second verify write operation including, reloading the data from the input terminal to each of the first latch circuits, restoring the written data of the memory cells into the sense amplifier circuits, comparing first values of the reloaded data stored in the first latch circuits and second values of the restored data stored in the sense amplifier circuits, and rewriting to each reloaded data to one of the memory cells connected one of the bit lines, respectively, when the first value is not same as the second value.