Patent ID: 8318547

Claim:
A method of packaging an integrated circuit in a packaging structure, the method comprising: thinning a first lead in a lead frame to a first thickness that is thinner than an initial thickness of the lead frame, the lead frame including a first die paddle and a second die paddle; thinning at least a portion of the second die paddle to a second thickness thinner than the initial thickness of the lead frame; mounting a first component on the first die paddle and a second component on at least the portion of the second die paddle, wherein the second component comprises a vertical cavity surface emitting laser (VCSEL); coupling the first component with the second component through an interconnect configured to route electrical signals between the first component and the second component; and forming an electrically insulating packaging material over the lead frame and the interconnect such that: a thinned portion of the first lead is encapsulated by the packaging material and the thinned portion of the first or second die paddle is electrically insulated from a lower surface of the packaging structure by the packaging material; and at least a portion of a second lead of the lead frame is exposed to form an external electrical connection through the packaging material, wherein the interconnect does not comprise the second lead.