Patent ID: 6891486

Claim:
A method of measuring capacitor mismatch in an analog to digital converter (ADC), said ADC converting an analog signal to a plurality of digital codes, said ADC containing a plurality of stages and a code generator, said plurality of stages being connected in sequence, a first stage contained in said plurality of stages comprising a sub_ADC, a plurality of input capacitors, an amplifier and a feedback capacitor, said sub_ADC generating a sub_code from which said code generator generates each of said plurality of digital codes, said method comprising: sampling a first voltage on each of said plurality of input capacitors in a first phase, wherein said first voltage is designed to cause at least some of said plurality of stages to generate a sub_code equaling zero; charging said feedback capacitor to a second voltage, wherein said second voltage is not equal to said first voltage; connecting one of said plurality of input capacitors to said second voltage in a second phase; connecting said feedback capacitor across said amplifier in said second phase; and determining a capacitor mismatch of said one of said plurality of input capacitors by examining a first signal generated by said second phase.