Patent ID: 7724051

Claim:
A DLL circuit comprising: a delay line for delaying a clock signal, the delay line including a plurality of cascade-connected variable delay elements, the variable delay elements having a differential circuit structure in which a delay value thereof can be varied by a bias current, the variable delay elements comprising a plurality of bias transistors and a switching circuit connected to a gate of the plurality of bias transistors; a first controller for setting the bias current by controlling the switching circuit to select a bias transistor of the plurality of bias transistors; and a second controller for selecting an output-producing variable delay element from the plurality of the variable delay elements, the second controller including: a phase comparator for comparing a phase of the clock signal and an internal clock signal delayed by the delay line; and a counter circuit for performing addition or subtraction based on a results of a phase comparison by the phase comparator, and an other delay line which receives an output of the delay line, the other delay line having a pitch for adjusting the delay value which is less that a pitch for adjusting a delay value of the delay line, wherein the second controller further comprises a bias circuit for controlling the other delay line based on the count value from the counter circuit.