Patent ID: 8115285

Claim:
A semiconductor package comprising: a die pad including: a peripheral edge region including an upper surface and defining a cavity with a cavity bottom; an upper sloped portion disposed adjacent to the upper surface of the peripheral edge region and facing away from the cavity; and a lower sloped portion disposed adjacent to the upper sloped portion and facing away from the cavity; a plurality of leads disposed around the die pad, wherein each of the plurality of leads includes: an upper surface; a lower surface; an upper sloped portion disposed adjacent to the upper surface of each of the plurality of leads; and a lower sloped portion disposed adjacent to the lower surface of each of the plurality of leads; a first semiconductor chip disposed on the cavity bottom and electrically coupled to the plurality of leads; a package body formed over the first semiconductor chip and the plurality of leads so that the package body substantially fills the cavity and substantially covers the upper sloped portions of the die pad and the plurality of leads, and the lower sloped portions of the die pad and the plurality of leads at least partially extend outwardly from a lower surface of the package body; and a protective layer substantially covering the lower sloped portion and the lower surface of at least one of the plurality of leads.