Patent ID: 7834388

Claim:
An electrically alterable, non-volatile memory array, comprising: a first memory string in a first column of the memory array and a second memory string being placed parallel the first memory string in a second column of the memory array, each memory string having: a first select transistor; a second select transistor; a first conductor connected to a first drain or source terminal of the first select transistor, a first select line connected to a gate of the first select transistor, a control line connected to a gate of a memory cell transistor in the memory string, the memory cell transistor being one of a plurality of serially connected non-volatile memory transistors in the memory string connected between a second drain or source terminal of the first select transistor and a first drain or source terminal of the second select transistor, each memory transistor having two floating gates, a second select line connected to a gate of the second select transistor in the memory string, and a second conductor connected to a second drain or source terminal of the second select transistor; and wherein (i) the first conductor of the first memory string and the first conductor of the second memory string are electrically coupled to each other; (ii) the first select line of the first memory string and the first select line of the second memory string are electrically isolated; (iii) the second select line of the first memory string and the second select line of the second memory string are electrically isolated, and (iv) the second conductor of the first memory string and the second conductor of the second memory string are electrically isolated; and (v) the first and second conductors of each memory string are each coupled to a charging transistor, a discharging transistor and a sense amplifier.