Patent ID: 8798223

Claim:
A clock and data recovery device, comprising: reference clock generator circuitry configured to receive a serial data signal and to produce a first clock signal oscillating at a frequency substantially a sub-harmonic of a data rate of the serial data signal without utilizing an external reference clock signal; and clock and data recovery circuitry configured to receive the serial data signal and the first clock signal and produce the data output signal representing data recovered from the serial data signal and the second clock signal that is synchronous with the data output signal, wherein the reference clock generator circuitry comprises: an oscillator configured to supply a third clock signal oscillating at a controlled frequency, wherein the reference clock generator circuitry utilizes the third clock signal to produce the first clock signal; a beat frequency generator configured to receive the serial data signal and the third clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial input signal and the frequency of the third clock signal; a first divider configured to receive the third clock signal and produce an output signal at a lower frequency; and a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator.