Patent ID: 7176581

Claim:
A semiconductor device comprising: a semiconductor chip including a plane polygon and an integrated circuit; a plurality of electrodes formed on the surface of the plane polygon of the semiconductor chip; a resin layer formed on the surface of the plane polygon of the semiconductor chip; a wiring formed to reach an upper side of the resin layer from at least one of the plurality of electrodes; and an external terminal formed on a part of the surface of the resin layer, wherein: the plane polygon has a pair of first sides, which are parallel to each other, and a pair of second sides which are parallel to each other; the surface of the resin layer, which is opposite to the plane polygon, has a third side opposed to one of the first sides, and a fourth side oppose to one of the second sides; a first space between the one first side and the third side is narrower than a second space between the one second side and the fourth side; the plurality of electrodes are arranged in a first region located between the one second side and the fourth side and are spaced apart from a second region located between the one first side and the third side; the third side includes a first curved line and a pair of second curved lines connected to both ends of the first curved line; and the first curved line is convexly bent toward an inside of the resin layer and each of the second curved lines is convexly bent toward an outside of the resin layer.