Patent ID: 7366031

Claim:
A memory arrangement, comprising: a plurality of memory elements, wherein each memory element stores at least one data word, the at least one data word including at least one bit and each memory element addressable by a plurality of address bits; and a switching arrangement comprising: a plurality of logic elements; and a plurality of address inputs; wherein the plurality of logic elements, starting from a data input of the switching arrangement, comprises a binary tree hierarchy in a direction of a number of outputs of the switching arrangement, each memory element of the plurality of memory elements being coupled to an output of the switching arrangement, each of the logic elements of the plurality of logic elements suppliable with an address bit by an address input of the plurality of address inputs and each of the logic elements of the plurality of logic elements assuming a switching state based on the address bit supplied, such that, when the plurality of logic elements are supplied with the plurality of address bits by the plurality of address inputs, the at least one data word which is supplied to the input of the switching arrangement is output at the switching arrangement to which the memory element is coupled and which is addressed by the plurality of address bits.