Patent ID: 7853756

Claim:
A method for controlling a first processor which executes a first thread and accesses information of a main memory through cache memory, comprising: reading information stored in a target address or an address range of the main memory by issuing a particular load instruction that loads the information and monitoring whether a second processor occurs an update access to the address or the address range, wherein the monitoring starts when the particular load instruction is issued as a trigger; entering the first processor into a suspense status in which the execution of the first thread is suspended; and releasing the first processor from the suspense status and resuming the execution of the first thread using the occurrence of the update access of an exclusive right request for acquiring an exclusive right of the main memory by the second processor executing a second thread as a trigger, and wherein realizing a possibility prediction, via the access, of a rewriting of a lock variable by the second processor for an exclusive control of memory access and suspending the execution of the first thread by entering the first processor into the suspense status to avoid an occurrence of a spin loop due to release waiting.