Patent ID: 7017000

Claim:
A data transfer control circuit in a system large-scale integration, which controls data transfer when a plurality of bus masters access a commonly shared external device, wherein at least one bus master of the bus masters has an arrangement for instructing pre-read of data, at the time of issuing a data read request, the data transfer control the circuit comprising: an external address generation unit that receives an address generation instruction and generates an address signal of the external device based on an address signal issued by the one bus master; an external device control unit that makes the external address generation unit to continuously generate an address for normal readout this time and an address for the next pre-read, upon reception of the data read request accompanied with the data pre-read instruction issued by the one bus master, and executes readout based on the next pre-read address, provided that when the normal readout this time is finished, the bus master other than the one bus master has not issued a data read request; a data holding unit that holds the normal data read based on the normal readout address this time; and a pre-read data storage unit that stores the pre-read data read based on the next pre-read address.