Patent ID: 8250268

Claim:
A display data channel (DDC) interface circuit, comprising: a first N type metal oxide semiconductor (NMOS) transistor comprising: a gate arranged to receive a 3.3V system power via a first resistor; a source connected to a display data channel clock pin DDC_CLK of a north bridge on a motherboard; and a drain arranged to receive a 5V system power via a second resistor, and also connected to a serial clock pin SCL of a video graphics array (VGA) interface on the motherboard via a third resistor, the VGA interface also connected to an automatic color killer (ACK) in a monitor to receive an ACK signal; and a second NMOS transistor comprising: a gate arranged to receive the 3.3V system power via the first resistor; a source connected to a display data channel data pin DDC_DATA of the north bridge; and a drain arranged to receive the 5V system power via a fourth resistor, and also connected to a serial data pin SDA of the VGA interface via a fifth resistor to receive the ACK signal.