Patent ID: 7550384

Claim:
A method for forming a fine pattern in a semiconductor device, the method comprising: forming a first hard mask layer over a semiconductor substrate and a second hard mask layer over the first hard mask layer; selectively etching the second hard mask layer and the first hard mask layer by using a line/space mask as an etching mask to form a second hard mask layer pattern and a first hard mask layer pattern, wherein a line width of an upper part of the second hard mask layer pattern is narrower than that of its lower part; forming an insulating film filling the second hard mask layer pattern and the first hard mask layer pattern; selectively etching the second hard mask layer pattern and its underlying first hard mask layer pattern by using the insulating film as an etching mask to form a third hard mask layer pattern and an underlying fourth hard mask layer pattern; removing the insulating film and the third hard mask layer pattern; and patterning the semiconductor substrate by using the fourth hard mask layer pattern as an etching mask, to form a pattern.