Patent ID: 8786351

Claim:
A level shifter, comprising: a plurality of Type 1 transistors, wherein each of the Type 1 transistors includes a source, a gate, and a drain, the Type 1 transistors include: a first Type 1 transistor; a second Type 1 transistor, wherein the gate of the first Type 1 transistor and the gate of the second Type 1 transistor are connected to a first input terminal and a second input terminal respectively, the sources of both the first Type 1 transistor and the second Type 1 transistor are connected to a first voltage terminal; a third Type 1 transistor, wherein the gate and the drain of the third Type 1 transistor are interconnected, the source of the third Type 1 transistor is connected to the drain of the first Type 1 transistor; and a fourth Type 1 transistor, wherein the gate and the drain of the fourth Type 1 transistor are interconnected, the source of the fourth Type 1 transistor is connected to the drain of the second Type 1 transistor; and a plurality of Type 2 transistors, wherein each of the Type 2 transistors includes a source, a gate, and a drain, the Type 2 transistors include: a first Type 2 transistor, wherein the drain and the gate of the first Type 2 transistor are interconnected and also connected to the drain of the third Type 1 transistor; a second Type 2 transistor, wherein the drain and the gate of the second Type 2 transistor are interconnected and also connected to the drain of the fourth Type 1 transistor; a third Type 2 transistor, wherein the drain of the third Type 2 transistor is connected to the source of the first Type 2 transistor, the gate of the third Type 2 transistor is connected to the drain and the gate of the second Type 2 transistor; and a fourth Type 2 transistor, wherein the drain of the fourth Type 2 transistor is connected to the source of the second Type 2 transistor, the gate of the fourth Type 2 transistor is connected to the drain and the gate of the first Type 2 transistor, the sources of both the third Type 2 transistor and the fourth Type 2 transistor are connected to a second voltage terminal; wherein the Type 1 transistors further include: a fifth Type 1 transistor, the gate of the fifth Type 1 transistor connected to the second input terminal, the source of the fifth Type 1 transistor connected to the drain of the second Type 1 transistor and the source of the fourth Type 1 transistor, the drain of the fifth Type 1 transistor connected to the source of the second Type 2 transistor, the drain of the fourth Type 2 transistor and a first output terminal; and a sixth Type 1 transistor, the gate of the sixth Type 1 transistor connected to the first input terminal, the source of the sixth Type 1 transistor connected to the drain of the first Type 1 transistor and the source of the third Type 1 transistor, the drain of the sixth Type 1 transistor connected to the source of the first Type 2 transistor, the drain of the third Type 2 transistor and a second output terminal.