Patent ID: 7129113

Claim:
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes: a first semiconductor chip that includes first and second opposing surfaces, wherein the first surface of the first chip includes a first conductive pad; a first conductive trace that includes a first routing line and a first metal pillar and is electrically connected to the first pad; and a first encapsulant that includes first and second opposing surfaces, wherein the first surface of the first encapsulant faces in a first direction, the second surface of the first encapsulant faces in a second direction opposite the first direction, the first chip is embedded in the first encapsulant, the first routing line overlaps the first metal pillar and extends laterally beyond the first metal pillar towards the first chip, and the first metal pillar is devoid of solder and conductive adhesive, is disposed outside a periphery of the first chip and extends vertically beyond the first chip, the first routing line and the first encapsulant in the second direction; providing a second semiconductor chip assembly that includes: a second semiconductor chip that includes first and second opposing surfaces, wherein the first surface of the second chip includes a second conductive pad; a second conductive trace that includes a second routing line and a second metal particle and is electrically connected to the second pad; and a second encapsulant that includes first and second opposing surfaces, wherein the first surface of the second encapsulant faces in the first direction, the second surface of the second encapsulant faces in the second direction, a second aperture in the second encapsulant extends from the first surface of the second encapsulant to the second metal particle, the second chip and the second metal particle are embedded in the second encapsulant, the second routing line extends laterally beyond the second metal particle towards the second chip, and the second metal particle overlaps the second routing line, is disposed outside a periphery of the second chip and extends vertically across at least some of a thickness of the second chip between the first and second surfaces of the second chip; then positioning the first and second assemblies such that the first assembly overlaps the second assembly, the first surfaces of the encapsulants face in the first direction, the second surfaces of the encapsulants face in the second direction, the first surface of the second encapsulant faces towards the second surface of the first encapsulant, and the first metal pillar extends into the second aperture; reflowing the second metal particle such that the first metal pillar extends into and is embedded in the second metal particle; and electrically connecting the first metal pillar and the second metal particle within the second encapsulant.