Patent ID: 8030963

Claim:
A standard cell of an integrated circuit, the cell comprising: a master-slave flip-flop; and a comparator logic having inputs adapted to receive an input signal of the master-slave flip-flop, an inverted input signal of the master-slave flip-flop, an output signal of the master-slave flip-flop, and an inverted output signal of the master-slave flip-flop, wherein the master-slave flip-flop has a master flip-flop and a slave flip-flop, wherein the slave flip-flop has a first inverting element and a second inverting element, wherein, for feedback, an output of the first inverting element is connectable to an input of the second inverting element and an output of the second inverting element is connectable to an input of the first inverting element, and wherein, to output the output signal and the inverted output signal of the master-slave flip-flop, the output and the input of the second inverting element are connectable to inputs of the comparator logic so that the second inverting element and the comparator logic and an additional inverter form an exclusive-OR operation of the standard cell.