Patent ID: 6925699

Claim:
A method of producing a quantity of integrated circuits, that includes testing a set of semiconductor wafers that is made up of a first subset and a second subset, said first subset being configured in such a manner that a first tester is more readily adapted to perform said testing and said second subset being configured in such a manner that a second tester is more readily adapted to perform said testing, said method comprising the steps of: (a) creating, on a head plate, a head plate-tooling plate attachment region having fastening and alignment items; (b) providing a first tooling plate and a second tooling plate, each having fastening and alignment items adapted to mate to said head plate-tooling plate attachment region fastening and alignment items and each defining an aperture designed to engage a probe card dish and adapted to facilitate docking to a unique tester out of said set of testers; (c) fastening said first tooling plate to said head plate-tooling plate attachment region using said alignment and fastening items; (d) mating said probe station to said first tester to test said first subset of wafers; (e) removing said first tooling plate from said head plate-tooling plate attachment region; (f) fastening said second tooling plate to said head plate-tooling plate attachment region using said alignment and fastening items; (g) mating said probe station to said second tester to test said second subset of wafers; and (h) dicing at least one wafer from said first subset and said second subset to create said quantity of integrated circuits.