Patent ID: 8290729

Claim:
A low voltage differential signaling (LVDS) timing test system, the test system comprising: a storage system; at least one processor; a timing test unit being stored in the storage system and executable by the at least one processor, the timing test unit comprising: a waveform obtaining module operable to obtain a waveform of a clock signal and a waveform of a data signal, wherein the clock signal and the data signal are generated by an LVDS device; a data identification module operable to select clock cycles of the clock signal from the waveform of the clock signal, and identify values of data bits transmitted within the selected clock cycles from the waveform of the data signal according to voltage values of the data signal waveform, wherein a data bit with a high voltage is identified as a digital 1, a data bit with a low voltage is identified as a digital 0; a timing analysis module operable to determine bit positions of the data bits relative to the clock signal; a determination module operable to determine whether the number of the bit positions of each of the data bits is less than a predetermined number, determine a minimum value and a maximum value of the bit positions of each of the data bits, and determine whether the bit positions of each of the data bits complies with LVDS timing specifications according to the minimum value and the maximum value of the bit positions of each of the data bits; and an output module operable to output the minimum value and the maximum value of the bit positions of each of the data bits to an output device.