Patent ID: 8543629

Claim:
A processing system, comprising: a memory having first, second and third sections that are each shared exclusively by an encoder, an IFFT, and a post-processor, where the encoder and the IFFT read from, and write to, the memory sections, and the post-processor reads from the memory sections; the encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, wherein the encoder reads a first data from the first memory section, processes the first data, and writes the first data back to the first memory section as a first encoded data; the IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, wherein the IFFT is further configured to read the first encoded data from the first memory section, process the first encoded data, and write the first encoded data back to the first memory section as a first IFFT processed data, concurrent to the encoder reading a second data from the second memory section, processing the second data, and writing the second data back to the second memory section as a second encoded data; and the post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion, wherein the post-processor is further configured to read the first IFFT processed data from the first memory section and process the first IFFT processed data concurrent to the IFFT reading the second encoded data from the second memory section, processing the second encoded data, and writing the second encoded data back to the second memory section as a second IFFT processed data, and concurrent to the encoder reading a third data from the third memory section, processing the third data, and writing the third data back to the third memory section as a third encoded data, such that the encoder, the IFFT, and the post-processor take turns accessing each of the first, second, and third memory sections.