Patent ID: 8654539

Claim:
A capacitor-incorporated wiring substrate which has a core having an accommodation portion in the form of a recess or a through hole, a capacitor having dielectric layers and electrode layers laminated alternatingly, and accommodated in the core, and a laminate portion formed on at least an upper surface of the core and having insulation layers and conductor layers laminated alternatingly, comprising: a first via-conductor group to be electrically connected to a first electric potential, and adapted to connect, in a direction of lamination, the electrode layers and the conductor layers; a second via-conductor group to be electrically connected to a second electric potential, and adapted to connect, in the direction of lamination, the electrode layers and the conductor layers; a first electrode pattern formed in a front-surface electrode layer on a front surface of the capacitor and electrically connected to the first via-conductor group; a plurality of second electrode patterns formed in the front-surface electrode layer and connected to respective columns of via conductors of the second via-conductor group; a first conductor pattern formed in a proximate conductor layer of the laminate portion disposed in proximity to and facing the capacitor, and electrically connected to the first via-conductor group; and a plurality of second conductor patterns formed in the proximate conductor layer and connected to respective columns of via conductors of the second via-conductor group, wherein each of the second electrode patterns connects a predetermined number of capacitor-side via conductors arranged in a first direction, and each of the second conductor patterns connects a predetermined number of laminate-portion-side via conductors arranged in a second direction intersecting with the first direction.