Patent ID: 8543356

Claim:
A system for multi-channel acquisition, comprising: at least one host processor having at least one user interface, said host processor configured to accept user input to define signature events and user selected time intervals; more than two acquisition channels, each of said more than two acquisition channels configured to detect similar or dissimilar events defined by a user as said signature events; a user configurable processor comprising at least one field programmable gate array (FPGA) device to rapidly reconfigure sets of said acquisition channels from which input is received; the user configurable processor configured to correlate said signature events detected by each of said more than two acquisition channels to identify coincidences occurring within said user selected time intervals, each of said more than two acquisition channels configured to detect one or multiple signature events one after another or simultaneously without requiring a fixed delay to be added to any of said more than two acquisitions channels; wherein said user configurable processor further includes a processing component configured to identify said coincidences by identifying a plurality predetermined sequences of events within said coincidences, identifying a plurality predetermined time bins, and associating said one or more predetermined sequences of events within said coincidences with one or more of said plurality of time bins to identify overlapping subsets of signature events within two or more coincidences; a memory component which stores data about coincidences and said signature events on which said coincidences are based and wherein the user configurable processor correlates said signature events to detect multiple types of coincidences with overlapping signature events that occur within said user defined time interval; a multi-coincidence detector configured to identify a user defined subset of signature events from one or more coincidences and report the identification of said user defined subset of signature events to said host processor; and wherein each of said more than two acquisition channels further includes at least one trigger component operatively coupled with an internal clock configured using field programmable gate array circuitry.