Patent ID: 8018767

Claim:
A semiconductor device comprising: a memory cell array that includes non-volatile memory cells; bit lines that are connected to sources and drains of transistors that form the memory cells; word lines that are connected to gates of the transistors; a plurality of divided regions that are contained in the memory cell array, each of the divided regions having memory cells connected to the same one of the word lines; a plurality of sub divided regions that are contained in each of the divided regions, each of the sub divided regions having memory cells connected to the same one of the word lines; a plurality of cell blocks each having at least one bit contained in each of the divided regions, memory cells in each of the cell blocks being physically adjacent to one another; and a connecting circuit that connects bit lines connected to neighboring memory cells to each other in the divided region; wherein a first bit line connected to a first memory cell that is one of the memory cells in which data is to be written is precharged before the data is written in the first memory cell; when the first bit line is precharged, the connecting circuit connects the first bit line to a second bit line connected to a second memory cell that is a memory cell neighboring the first memory cell in the divided region; and before the data is written in the first memory cell, the connecting circuit disconnects the first bit line from the second bit line.