Patent ID: 7989899

Claim:
An inverter comprising: a load transistor including a first oxide channel layer, a first gate and a first gate insulating layer between the first oxide channel layer and the first gate, the first gate insulating layer includes a first layer and a second layer sequentially disposed on the first gate; and a switching transistor connected to the load transistor, the switching transistor including a second oxide channel layer, a second gate and a second gate insulating layer between the second oxide channel layer and the second gate, the second gate insulating layer includes a third layer having a same material as the second layer, the second gate insulating layer being a different structure than the first gate insulating layer, the second gate insulating layer includes a charge trap region such that charges are trapped in the charge trap region of the second gate insulating layer rather than in the first gate insulting layer and a threshold voltage of the switching transistor is increased by the trapped charges such that the switching transistor is an enhancement-mode transistor.