Patent ID: 8647988

Claim:
A method of fabricating a memory device, comprising: filling a first dielectric material in a plurality of deep trenches and a plurality of shallow trenches to separately form a plurality of deep isolations and a plurality of shallow isolations in a substrate, wherein each shallow trench is formed between two adjacent ones of the plurality of the deep trenches; forming a plurality of depressions transverse to the plurality of deep isolations, wherein two adjacent ones of the plurality of depressions define a mesa structure, and a depression is wider than the mesa structure; filling the plurality of depressions with a second dielectric material; removing a portion of the first dielectric material from the plurality of shallow trenches and the plurality of deep trenches and a portion of the second dielectric material from the plurality of depressions; forming a conductive layer in the plurality of shallow trenches, the plurality of deep trenches and the plurality of depressions; and removing a portion of the conductive layer in the depression to form two word lines.