Patent ID: 6958544

Claim:
A semiconductor device, in which a plurality of electronic chips which include a predetermined element and a connection terminal, on one surface of the electronic chip, and a conductive film pattern that is connected electrically to the connection terminal via a via hole which passes through the electronic chip, on another surface side of the electronic chip, are laminated and packaged on a wiring substrate including a wiring pattern, in a direction that is perpendicular to a surface direction of the wiring substrate, in a state that the electronic chips are buried in an interlayer insulating film, wherein a thickness of the electronic chip is about 150 μm or less, and the connection terminals of the electronic chips are bonded to the wiring pattern of the underlying wiring substrate or the conductive film pattern of the electronic chips by a flip-chip bonding respectively, and the plurality of electronic chips are connected mutually via the via holes in the electronic chips.