Patent ID: 7366045

Claim:
A sense circuit coupled to a first bit line connected to a resistive memory cell to be sensed and a second bit line, the sense circuit comprising: a power supply for supplying a primary voltage and an equalization voltage; a first power circuit, coupled to the power supply for receiving the primary voltage and producing a first reference voltage different from the primary voltage; an equalization circuit, coupled to the first and second bit lines, and to the power supply for receiving the equalization voltage, the equalization circuit being configured to set a voltage of the first and second bit lines to the equalization voltage; a reference circuit, coupled to the first and second bit lines and the first power circuit, for receiving the first reference voltage, said reference circuit being configured to set a voltage of said second bit line to the first reference voltage; a sense amplifier, controllably coupled to the first and second bit lines; and a control circuit, for calibrating and controlling the first power circuit.