Patent ID: 7269044

Claim:
A memory device comprising: a first memory unit comprising at least first and second resistance variable memory elements; a second memory unit comprising at least third and fourth resistance variable memory elements, each memory element having a first and a second electrode, the first and second memory elements having a common first electrode, the third and fourth memory elements having a common first electrode, and the second and third memory elements having a common second electrode; and switching circuitry configured to selectively apply a voltage to first and second electrodes of at least one of the first, second, third and fourth memory elements, the switching circuitry comprising: a first select line connected to the first memory element second electrode; a second select line connected to the second and third memory element common second electrode; a third select line connected to the fourth memory element second electrode; a first a voltage supply line switchably connected to the first, second, and third select lines by first, second, and third transistors, respectively, and wherein first and third transistors are a first conductivity type and the second transistor is a second conductivity type.