Patent ID: 7804129

Claim:
A transistor comprising: a silicon substrate having: an active area including: a channel having a channel length; a channel width; and a recess including: a recess depth; a recess bottom; and rounded corner edges at the recess bottom; a gate on top of the channel and formed in the recess; and a gate insulation layer between the gate and the channel wherein the gate insulation layer is positioned on the recess bottom in which a portion of the gate insulation layer covers over the rounded corner edges at the recess bottom such that part of the gate extends below the portion of the gate insulation layer that covers over the rounded corner edges of the recess bottom; and an isolation area including: a trench having: a trench depth; a trench bottom; and a lower sidewall; an oxide layer and a nitride layer formed on the trench bottom and on the lower sidewall of the trench; and an insulation layer formed on the nitride layer and filling the trench, wherein the recess depth is smaller than the trench depth, an edge of the oxide layer and the nitride layer is positioned lower than the recess bottom, the channel length and the channel width of the transistor are increased corresponding to the gate formed above the oxide layer and the nitride layer, a portion of the gate insulating layer is positioned below all portions of the gate, and the rounded corner edges contribute to raising the transistor's threshold voltage, and wherein the oxide layer, the nitride layer and the gate insulation layer form a triple contiguous layer immediately between an adjacent connecting portion of the insulation layer of the trench and an adjacent connection portion the channel.