Patent ID: 7675972

Claim:
A system comprising: a memory; a memory controller to access the memory; a first processor to parse received video data to generate a plurality of packets, each packet having a video data payload and information related to the video data payload, and provide the plurality of packets for storage in the memory, wherein a format of the plurality of packets is independent of a video standard of the video data and wherein the first processor comprises a general purpose processor; a second processor comprising a video transcoder, the first processor and the second processor integrated at the same package substrate; and a decoder instruction packet (DIP) sequencer to: access one or more packets of the plurality of packets from the memory via the memory controller; configure the second processor based on opcodes of the one or more packets; provide the one or more packets to the second processor; and wherein the second processor is to transcode the video payload of each of the one or more packets to generate a channel of compressed video data.