Patent ID: 7232722

Claim:
A method of forming a multibit non-volatile memory cell structure, comprising: depositing a first polysilicon layer on a semiconductor substrate of a first conductivity type; depositing and patterning a first hardmask layer to form at least a first hardmask region upon the first polysilicon layer; depositing and anisotropically etching a second hardmask layer forming second hardmask spacers adjacent to the at least a first hardmask region; selectively removing exposed parts of the first polysilicon layer; removing the at least first hardmask region to expose the first polysilicon layer underneath the at least first hardmask region; removing the exposed parts of the first polysilicon layer underneath the at least first hardmask region to form first and second polysilicon gates having an uniform thickness, one on each side of the at least first hardmask region; removing the second hardmask spacers and exposing the first and second polysilicon gate; and depositing and patterning a second polysilicon layer perpendicular to the first and second polysilicon gate to form a third polysilicon gate separating the first and the second polysilicon gate.