Patent ID: 8125267

Claim:
An IO circuit comprising: an IO core-end block to generate a control signal, the IO core-end block comprising at least one constituent active circuit element having an upper tolerable limit of an operating voltage thereof; a driver block to drive at least one external active circuit element; an IO pad interfaced with the driver block; and a bias voltage generating circuit: to receive a supply voltage, to receive an external voltage supplied through the IO pad, and to generate an output bias voltage within the upper tolerable limit of the operating voltage of the at least one constituent active circuit element of the IO core-end block, wherein the bias voltage generating circuit comprises: a multiplexer block configured: to receive a first bias voltage controllably generated from the supply voltage to be within the upper tolerable limit of the operating voltage of the at least one constituent active circuit element of the IO core-end block to be interfaced with the IO pad, to receive a second bias voltage controllably generated from the external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the at least one constituent active circuit element of the IO core-end block to be interfaced with the IO pad, and to derive the output bias voltage from one of the first bias voltage during a driver mode of operation and the second bias voltage during a failsafe mode of operation and a tolerant mode of operation through a controllable utilization of the control signal generated by the IO core-end block, wherein the external voltage supplied through the IO pad varies from zero to a value of the supply voltage during the driver mode of operation, wherein the supply voltage is zero during the failsafe mode of operation, and wherein the external voltage supplied through the IO pad increases to a value above the supply voltage during the tolerant mode of operation.