Patent ID: 7894241

Claim:
A memory cell array, comprising: a first sub memory cell array that is activated in response to a first word line enable signal; a second sub memory cell array that is activated in response to a second word line enable signal; a sense-amplifier/precharge circuit connected to the first sub memory cell array through first bit lines and connected to the second sub memory cell array through second bit lines, the sense-amplifier/precharge circuit configured to precharge the first bit lines and the second bit lines and to amplify data provided from the first sub memory cell array and the second sub memory cell array; first capacitors, each of the first capacitors connected between a first dummy word line and each of the second bit lines, the first capacitors boosting the second bit lines in response to the first word line enable signal; and second capacitors, each of the second capacitors connected between a second dummy word line and each of the first bit lines, the second capacitors boosting the first bit lines in response to the second word line enable signal, wherein the memory cell array has an open bit line structure.