Patent ID: 7434141

Claim:
A computer network, comprising: a first computer system containing a memory system including a chipset and at least one memory module, the chipset operable to receive a physical memory address and to translate the physical memory address into a corresponding memory bus address according to configuration data stored in the chipset, and the chipset further operable to detect erroneous data stored in the memory system and to store a physical memory address and error data associated with the erroneous data; a second computer system coupled to the first computer system through a communications link to receive the physical memory address, error data, and configuration data stored in the chipset, and operable to output the physical memory address, error data, and configuration data over the communication link; and a server computer system coupled to the second computer system through the communications link to receive the physical memory address, error data, and configuration data from the second computer system, the server computer system including a memory error decoder component that is operable to process the physical memory address and configuration data to generate a memory bus address corresponding to the physical memory address, and is operable to process the error data to generate possible electrical routes of an erroneous data bit within a group of data bits associated with the memory bus address, the server system being further operable to communicate the data indicating the memory bus address and possible electrical routes to the second computer system over the communications link.