Patent ID: 7656204

Claim:
A circuit comprising: at least two clock edge controlled differential buffer store elements, each being clocked by one of a pair of complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising a differential data input; the internal storage nodes of the buffer store elements either being pre-charged at the pre-charge potential or storing a logic level, depending on the corresponding input clock signals, the differential data inputs of one of the buffer store elements being connected to the internal storage nodes of the other buffer store element, wherein the internal differential storage nodes generate pulsed signals; and at least one pulldown device, the pulldown device being configured to discharge a dynamic storage node pre-charged to a pre-charge potential and outputting a conditioned pulsed signal in response to at least one of the pulsed signals wherein the at least one pull down device comprises four pulldown devices, each comprising a controllable discharge switch being controlled by a respective pulsed signal; the respective pre-charge switch being controlled by a conditioned pulsed signal being phase shifted by 90° relative to a further of the conditioned pulsed signals.