Patent ID: 7554858

Claim:
A method of testing a plurality of memory devices using a tester having a plurality of input/output terminals, the method comprising: using at least some of the same terminals in a first set of the plurality of input/output terminals of the tester to communicate command signals, address signals, and write data signals to at least a first one of the memory devices and to communicate to the tester read data signals from the at least a first one of the memory devices; using at least some of the same terminals in a second set of the plurality of input/output terminals of the tester to communicate command signals, address signals, and write data signals to at least a second one of the memory devices that is different from the at least a first one of the memory devices and to communicate to the tester read data signals from the at least a second one of memory devices, at least some of the terminals in the first set being different from at least some of the terminals in the second set; within the at least a first one of the memory devices, routing the command signals received through the terminals in the first set to a first set of signal lines, and routing the address and write data signals received though the terminals in the first set to a second set of signal lines, the signals lines in the second set being different from the signal lines in the first set; and within the at least a second one of the memory devices, routing the command signals received through the terminals in the second set to a first set of signal lines, and routing the address and write data signals received through the terminals in the second set to a second set of signal lines, the signals lines in the second set being different from the signal lines in the first set.