Patent ID: 8709867

Claim:
A method for manufacturing a dual-leadframe multi-chip package, comprises the following steps: Step 1: provide a first leadframe comprising a first die pad and multiple outer pins; Step 2: provide a first chip and a second chip, wherein the first chip and the second chip each comprising a bottom contact area and a plurality of top contact areas respectively; Step 3: mount the first chip on the first die pad, the bottom contact area of the first chip be electrically connected with the first die pad; Step 4: provide a second leadframe with a second die pad and a three-dimensional connecting plate, electrically connect the three-dimensional connecting plate to a top contact area of the first chip, wherein the second die pad and the three-dimensional connecting plate forming an integrated body; Step 5: mount the second chip on the second die pad with the bottom contact area of the second chip is electrically connected to the second die pad; and Step 6: provide a top connecting plate connecting a top contact area of the second chip to an outer pin of the first leadframe.