Patent ID: 7796527

Claim:
A method of computer hardware fault administration, the method carried out in a parallel computer, the parallel computer comprising a plurality of compute nodes, the compute nodes coupled for data communications by at least two independent data communications networks including a first data communications network and a second data communications network, wherein the first data communication network and the second data communications network have different network topologies, each data communications network comprising data communications links connected to the compute nodes, the method comprising: identifying a location of a defective link in the first data communications network of the parallel computer; identifying, in dependence upon the location of the defective link in the first network, a location in the second network of a first compute node connected to the defective link; identifying, in dependence upon the location of the defective link in the first network, a location in the second network of a second compute node connected to the defective link; configuring the first compute node with the location in the second network of the second compute node; configuring the second compute node with the location in the second network of the first compute node; and routing communications data around the defective link from the first computer node directly to the second compute node through the second data communications network of the parallel computer.