Patent ID: 7851299

Claim:
A method of fabricating a semiconducting device comprising: providing a substrate including a plurality of semiconducting regions, wherein adjacent semiconducting regions of the plurality of semiconducting regions of the substrate are separated by an isolation region; forming a gate dielectric layer overlying the substrate; forming a metal layer overlying the gate dielectric layer; forming at least two conductors atop the metal layer, wherein each conductor of the at least two conductors is positioned overlying one semiconducting region of the plurality of semiconducting regions; forming a spacer abutting a sidewall of the each conductor of the at least two gate conductors, the spacer having a width that covers a portion of the metal layer that is overlying the semiconducting regions, wherein an exposed portion of the metal layer is overlying a portion of the isolation region; and etching the exposed portion of the metal layer and a portion of the gate dielectric layer underlying the exposed portion of the metal layer.