Patent ID: 7898295

Claim:
An apparatus for differential signaling, the apparatus comprising: a replica bias circuit comprising a replica NMOS transistor and a replica PMOS transistor; an explicit resistor having a resistance of about N times a characteristic impedance intended to be driven by a main driver circuit, wherein the explicit resistor is operatively coupled in a current path between sources of the replica NMOS transistor and the replica PMOS transistor, wherein N is greater than 1; the main driver circuit comprising a driver NMOS transistor and a driver PMOS transistor and steering switches; wherein the driver NMOS transistor is N times larger than the replica NMOS transistor, wherein a source of the driver NMOS transistor is configured to source current to a load via the steering switches; wherein the driver PMOS transistor is N times larger than the replica PMOS transistor, and is configured to sink current from the load via the steering switches; wherein outputs of the steering switches comprises a differential output of the main driver circuit, and wherein control of the steering switches controls the differential output data; a biasing circuit configured to bias the replica NMOS transistor such that the source of the replica NMOS transistor is biased relative to a first reference level V HIGH and configured to bias the replica PMOS transistor such that the source of the replica PMOS transistor is biased relative to second reference level V LOW different from the first reference level, wherein gate and drain voltages of the replica NMOS transistor and the driver NMOS transistor are coupled for replica biasing, and wherein gate and drain voltages of the replica PMOS transistor and the driver PMOS transistor are coupled for replica biasing; and a protection control circuit and protection switches, wherein the protection control circuit is configured to control the protection switches, wherein in a normal operating mode, the protection switches permit the biasing circuit to bias the driver NMOS transistor and the driver PMOS transistor, and wherein in a protected mode of operation, the protection switches cut off the driver NMOS transistor and the driver PMOS transistor.