Patent ID: 8902674

Claim:
A semiconductor memory device, comprising: a memory cell array comprising a plurality of memory cells coupled in series between a bit line and a common source line; peripheral circuits configured to read out data stored in a memory cell, selected from among the plurality of memory cells, by sequentially applying a plurality of read voltages to a word line, coupled to the selected memory cell, in a read operation; and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line and read normal read data when a first read voltage, among the plurality of read voltages, is applied and the peripheral circuits overlap data, read by sensing a voltage level of the bit line when a second read voltage lower than the first read voltage by a specific level is applied, with data read by sensing a voltage level of the bit line when a third read voltage higher than the first read voltage by the specific level is applied, to generate over-sampling data in order to determine whether a threshold voltage distribution of the selected memory cell falls within a set voltage distribution in the read operation.