Patent ID: 8423943

Claim:
A method of filling dcaps in an integrated circuit design comprising: identifying a set of dcap-eligible areas of the integrated circuit design for areas large enough to accommodate at least one dcap cell having a selected size by a computer, wherein the selected size is smaller than a default size, the dcap cell including at least one built-in power track; filling a set of dcap cells in the identified set of dcap-eligible areas by the computer; and connecting each of the built-in power tracks included in the set of dcap cells to a corresponding power grid by the computer, wherein the built-in power tracks are formed in an adjacent metal layer to the metal layer including the power grids, and wherein the built-in power tracks are formed in an m 1 metal layer of the integrated circuit and the power grids are formed in an m 2 metal layer of the integrated circuit and, each of the set of dcap-eligible areas being divided into a plurality of rows, each one of the plurality of rows having a height substantially equal to a height of the dcap cell and wherein each one of the plurality of rows is divided into a plurality of equal shaped areas having a shape substantially equal to a shape of the dcap cell, wherein at least a portion of the plurality of dcaps are located within the power grid channel.