Patent ID: 6954370

Claim:
A nonvolatile ferroelectric memory device, comprising: a memory control block for outputting control signals in response to a write enable command signal, a read enable command signal and a reset signal, wherein the control signals control data read/write operations; a ferroelectric memory cell array for writing data and reading data stored in a sense amplifier in response to the control signals, the ferroelectric memory cell array comprising: a plurality of bitline pairs; a plurality of first single port memory cells connected in a column direction between bitline pairs; and the sense amplifier connected between one of the plurality of bitline pairs; and a power-up reset circuit for outputting the reset signal to restore data stored in the ferroelectric memory cell array, wherein the plurality of first single port memory cells comprise: a first latch means for amplifying a high level by using a voltage difference among output nodes; a write control means for selectively connecting the plurality of bitlines to output nodes in response to the control signals; a storage means including a plurality of ferroelectric capacitors; a second latch means for amplifying a low level by using the voltage difference among output nodes; a pull-up switch for selectively applying a power supply voltage to the first latch means in response to the control signals; and a pull-down switch for selectively connecting the second latch means to a ground voltage in response to the control signals.