Patent ID: 8866653

Claim:
An analog-to-digital conversion method used in a successive approximation (SAR) analog-to-digital converter to convert an analog signal to obtain a digital value, wherein the digital value comprises an (N−1)-th to a 0-th bit sequentially corresponding to the most significant bit (MSB) to the least significant bit (LSB) of the digital value respectively, N is an integer greater than 1, and the analog-to-digital conversion method comprises: using a sampling-and-hold circuit to sample the analog signal to generate a sampling voltage; using a capacitive digital-to-analog conversion circuit to provide a comparison voltage, wherein the capacitive digital-to-analog conversion circuit comprises N−1 conversion units being an (N−1)-th conversion unit, and an (N−2)-th conversion unit to a first conversion unit, the first conversion unit to the (N−2)-th conversion unit comprise a first capacitor to an (N−2)-th capacitor respectively, the (N−1)-th conversion unit at least comprises a first sub-capacitor and a second sub-capacitor to an (N−2)-th sub-capacitor, and each of the first sub-capacitor to the (N−2)-th sub-capacitor has substantially the same capacitance with corresponding capacitor of the (N−2)-th capacitor to the first capacitor; using a comparator to compare the sampling voltage with the comparison voltage to generate a comparison signal; using an SAR control circuit to determine the (N−1)-th bit of the digital value according to the comparison signal; using the SAR control circuit to re-distribute the charges stored in at least the first sub-capacitor to the (N−2)-th sub-capacitor of the (N−1)-th conversion unit according to the (N−1)-th bit to update the comparison voltage; using the comparator to compare the sampling voltage with the updated comparison voltage to obtain the updated comparison signal following the step of updating the comparison voltage; using the SAR control circuit to determine the (N−2)-th bit of the digital value according to the updated comparison signal and judge whether the (N−1)-th and the (N−2)-th bit correspond to the same logic value; and using the SAR control circuit to re-distribute the charges stored in at least one of the first sub-capacitor to the (N−2)-th sub-capacitor of the (N−1)-th conversion unit to update the comparison voltage when the (N−1)-th bit and the (N−2)-th bit correspond to different logic values.