Patent ID: 7579229

Claim:
A method of manufacturing a semiconductor device having p-MOS and n-MOS transistors, the method comprising: (a) forming a Si 1-x Ge x strain applying layer, which is substantially strain relaxed and has an in-plane lattice constant larger than that of unstrained Si within a range of proportions greater than 0% and less than 4% on a semiconductor substrate, where 0<x<1; (b) growing a strained Si layer on said Si 1-x Ge x strain applying layer, thereby forming said strained Si layer which is subjected to in-plane tensile strain; (c) forming a SiO 2 layer on a surface of said strained Si layer; (d) bonding said SiO 2 layer and a supporting substrate to each other; (e) removing said semiconductor substrate, said Si 1-x Ge x strain applying layer and a part of said strained Si layer, thereby forming an SOI substrate composed of a stack of said supporting substrate, said SiO layer and said strained Si layer; and (f) forming said p-MOS and n-MOS transistor on a surface of said strained Si layer.