Patent ID: 7554374

Claim:
A duty cycle bounding circuit, comprising: a state holding logic element having at least two inputs and an output, the state holding element having a first delay; a delay element coupled from the output of the state holding logic element to a first one of the at least two inputs, the delay element having a second delay; a processor having a clock signal with an unbounded duty cycle, the clock signal coupled with a second one of the at least two inputs; and wherein a first transition on the output and a second transition on the output occur in response to the clock signal, further wherein an output duty cycle is different than the unbounded duty cycle on the second one of the at least two inputs; an inversion element configured to invert the output of the state holding logic element; and wherein the second transition on the output relative to the first transition on the output is temporally separated by about the delay of the delay element plus the delay of the state holding logic element and further wherein a sum of the first delay plus the second delay is less than half a period, T, of the clock signal.