Patent ID: 8001361

Claim:
A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: a design of an integrated circuit comprising: a plurality of processor cores, wherein at least one of the plurality of processor cores comprises a cascaded delayed execution pipeline unit having at least first and second execution pipelines, wherein instructions in a common issue group issued in parallel to the cascaded delayed execution pipeline unit begin execution in the first execution pipeline before beginning execution in the second execution pipeline, wherein the common issue group is not specified by the instructions and is formed subsequent to the instructions being fetched, and wherein at least one of the first and second execution pipelines operates on a floating point operand, and wherein at least the first execution pipeline comprises circuitry for forwarding results of a first instruction from a first issue group to an execution unit in one of the first execution pipeline and the second execution pipeline, wherein the execution unit is configured to execute a second instruction from a second issue group; and a shared predecoder configured to: receive lines of instructions to be executed by the pipeline unit; predecode the lines of instructions to form issue groups, whereby first and second instructions in each group are scheduled for execution in the first and second execution pipelines, respectively; receive a subsequent line of instructions for execution by one of the execution pipelines; and determine whether to predecode the subsequent line of instructions, based on whether an instruction cache miss has occurred for the subsequent line of instructions and whether at least one schedule flag associated with the subsequent line of instructions has changed.