Patent ID: 8700881

Claim:
A controller controlling a non-volatile memory device comprising a plurality of flash memory chips accessed via a plurality of channels extending between the controller and the non-volatile memory device, the controller comprising: a plurality of address translation central processing units (CPUs), each configured to perform logical-physical address translation with respect to at least one of the plurality of channels, wherein each address translation CPU comprises; an address translation unit that translates a logical address received from the host into a corresponding physical address, a wear leveling unit that performs a wear leveling operation on the memory cells of the non-volatile memory device and provides resulting wear level information, and a bad-block management unit that manages bad blocks of the non-volatile memory device and provides bad block information, and each address translation CPU is configured to change an address mapping table including the logical address and the physical address in response to at least one of the wear leveling information and the bad block information; and a plurality of flash memory controllers, each configured to control an access operation related to at least one of the plurality of channels in response to a control signal output from at least one of the plurality of address translation CPUs.