Patent ID: 7984358

Claim:
A system comprising: a first circuit configured to generate error-correction (EC) bits based on test data; memory comprising a plurality of memory lines each including a data portion, the data portion configured to store the test data, and ii) an error-correction (EC) portion, the EC portion configured to store corresponding ones of the EC bits; an input configured to receive the test data; and a switching device configured to selectively output one of the test data from the input and the EC bits and the test data from the first circuit to the memory, wherein the test data comprise T pairs of test vectors, wherein a first test vector of each of the T pairs of test vectors is an inverse of a second test vector of each of the T pairs of test vectors, wherein each of the first test vectors in the T pairs of test vectors is different from others of the first test vectors, and wherein each of the second test vectors in the T pairs of test vectors is different from others of the second test vectors, where T is an integer greater than one.