Patent ID: 8031552

Claim:
A multi-port memory device, comprising: a plurality of ports (PORT 0 -PORT 3 ); a first global data bus coupled to said ports; a second global data bus coupled to said ports; an I/O controller ( 91 - 94 ) corresponding to each of said plurality of ports, said I/O controller configured to transmit a test signal (PO_RXD) from its corresponding port (PORT 0 -PORT 3 ) to the second global data bus (GIO_IN) when the multi-port memory device performs a DRAM core test operation; a test I/O controller ( 95 ) which transmits a test I/O signal to the second global data bus (GIO IN) in response to an internal write command, and transmits data input from the first global data bus (GIO_OUT) in response to an internal read command; and a mode register set for generating a test enable signal in response to a mode register enable signal and outputting a mode selection signal which determines a data transmission mode of said test I/O signal.