Patent ID: 8325516

Claim:
A method for forming a semiconductor device, comprising: providing a substrate having a cell region and a peripheral region; forming a first well region of a first conductivity type in the cell region and simultaneously forming a second well region of the first conductivity type in the peripheral region; forming a third well region of a second conductivity type in the cell region and simultaneously forming a fourth well region of the second conductivity type in the peripheral region; forming a floating gate on a junction of the first and third well regions; forming a control gate over the sidewall of the floating gate and partially extending to the upper surface of the floating gate, and simultaneously forming first and second gates respectively in the second and fourth well regions; forming a first doping region in the third well region near one side of the control gate and simultaneously forming a pair of second doping regions in the fourth well region on both sides of the second gate; and forming a pair of third doping regions in the second well region on both sides of the first gate.