Patent ID: 8362805

Claim:
An integrated circuit comprising: a plurality of power switches coupled to a supply voltage node and configured to provide supply voltage to a circuit block responsive to a plurality of enables, wherein each of the plurality of power switches is coupled to one of the plurality of enables; and a power control circuit configured to generate the plurality of enables for the plurality of power switches responsive to an input block enable, wherein the power control circuit comprises a plurality of series-connected clocked storage devices, wherein a first clocked storage device of the plurality of series-connected clocked storage devices is coupled to receive the input block enable, and wherein an output of each of the plurality of series-connected clocked storage devices corresponds to one of the plurality of enables, and wherein the plurality of series-connected clocked storage devices are clocked by a clock signal, wherein a clock period of the clock signal is greater than a propagation delay from the output of one of the plurality of series-connected clocked storage devices to the plurality of power switches that are controlled by that output.