Patent ID: 6892323

Claim:
A selectable basic input/output system (BIOS) for a computer system, the computer system comprising: a central processing unit (CPU); and a chipset for supporting the CPU, the chipset having a first general purpose input/output (GPIO) register programmable by the CPU; the selectable BIOS comprising: a primary BIOS program executable by the CPU and comprising confirmation code for generating a confirmation signal on the first GPIO register; a secondary BIOS program executable by the CPU; a timer circuit for generating a delay signal at a predetermined time after power-on of the computer system; and a BIOS switching circuit for causing shadowing of the primary BIOS program or the secondary BIOS program into a predetermined address space of the CPU according to the confirmation signal and the delay signal; wherein while the primary BIOS program is shadowed into the predetermined address space of the CPU, if the BIOS switching circuit receives the delay signal before receiving the confirmation signal, then the BIOS switching circuit causes the CPU to undergo a first reset operation and shadows the secondary BIOS program into the predetermined address space for execution by the CPU after the first reset operation, and if the BIOS switching circuit receives the delay signal after receiving the confirmation signal, then the BIOS switching circuit does not cause the CPU to undergo the first reset operation.