Patent ID: 6855572

Claim:
A method of packaging and stacking integrated circuit chips fabricated on a same wafer, each of the integrated circuit chips having active circuit areas, the method comprising: coupling active circuit areas of a first integrated circuit chip on a wafer to active circuit areas of a second integrated circuit chip on the wafer with a plurality of first electrical contacts; coupling a plurality of second electrical contacts to and on top of the plurality of first electrical contacts wherein the second electrical contacts are substantially thicker than the first contacts and are positioned between the first and second chips; encapsulating the second electrical contacts such that the top surfaces of the second electrical contacts are left exposed; cutting the wafer through the second electrical contacts between the first and second chips, the first and second chips being separated, the second electrical contacts having exposed top and side surfaces; and stacking the first integrated circuit chip over the second integrated circuit chip such that (1) the active circuit areas of the first integrated circuit chip are in a plane substantially parallel to the active circuit areas of the second integrated circuit chip, and (2) the corresponding second electrical contacts of the first and second integrated circuit chips are in the same plane.