Patent ID: 8659337

Claim:
A latch circuit comprising: a storage sub-circuit including two cross-coupled inverters and configured to capture a level of an input signal at a falling transition of a clock signal from high to low and hold the captured level of the input signal to generate an output signal that equals the captured level of the input signal while the clock signal is low and until a rising transition of the clock signal from low to high, wherein the inverters each have a power supply terminal coupled to a power supply; a bridging transistor coupled between the power supply terminals and configured to receive the clock signal to turn on or off the bridging transistor and allow current to flow from the power supply to the storage sub-circuit; and a propagation sub-circuit configured to receive the input signal and propagate the input signal to generate the output signal so that the input signal is passed through to the output signal beginning at the rising transition of the clock signal from low to high, continuing while the clock signal is high, and ending at the falling transition of the clock signal from high to low, wherein at least one pull-down transistor activates the propagation sub-circuit when the clock signal is high and deactivates the propagation sub-circuit when the clock signal is low.