Patent ID: 7250672

Claim:
A semiconductor package comprising: a molded housing; a lead frame including a first die pad having a die receiving surface, a second die pad having a die receiving surface, a first power lead disposed at one side of said molded housing electrically connected to said first die pad, a second power lead and a control lead at said one side of said molded housing; a first semiconductor die disposed on said die receiving surface of said first die pad, said first semiconductor die including a first power electrode and a control electrode on a first surface thereof and a second power electrode on a second opposing surface thereof, said second power electrode of said first semiconductor die being electrically connected to said die receiving surface of said first die pad, whereby said second power electrode of said first semiconductor die is electrically connected to said first power lead; and a second semiconductor die disposed on said die receiving surface of said second die pad, said second semiconductor die including a first power electrode and a control electrode on a first surface thereof and a second power electrode on a second opposing surface thereof, said second power electrode of said second semiconductor die being electrically connected to said die receiving surface of said second die pad, said first power electrode of said second semiconductor die being electrically connected to said second power lead and said control electrode of said semiconductor die being electrically connected to said control lead; wherein a distance without an intervening power lead between said second power lead corresponding to the first semiconductor die and an adjacent said first power lead corresponding to the second semiconductor die, at an outer peripheral side of the package, is larger than a distance between said control lead corresponding to the first semiconductor die and said second power lead corresponding to the first semiconductor die, at the outer peripheral side of the package.