Patent ID: 7007059

Claim:
A method of performing a pipelined arithmetic function comprising the steps of: a) receiving two N-bit operands into each of a plurality of adder elements in separate pipelines; b) performing an add operation in each of said plurality of adder elements wherein a first N-bit result and a first carry bit is output from each of said adder elements; c) receiving said first N-bit result from each of said adder elements into a respective N-bit result register and receiving said first carry bit from each of said adder elements into a respective carry bit register; d) outputting from an incrementor in one of said pipelines, a second N-bit result and a second carry bit from the combination of a first result from a first of said N-bit result registers, a first carry bit from a first of said carry bit registers, and a first carry bit from a second of said carry bit registers from a second of said pipelines; and e) supplying a final result being a combination of said second N-bit result from said incrementor, said second carry bit from said incrementor, and said first N-bit result from a second N-bit result register in said second pipeline.