Patent ID: 8597993

Claim:
A method of providing electrostatic discharge (ESD) protection of an integrated circuit chip comprising: providing a substrate with a region of triple wells, N-Wells separated by and isolated from a P-Well therein; forming a MOSFET with a source, a drain and a gate in the isolated P-Well; forming a lateral p-n-p having a base, an emitter and a collector in each of the N-Wells and integrated with the MOSFET; providing an input/output (I/O) pad and coupling the emitters of the lateral p-n-p and the drain of the MOSFET to the (I/O) pad; and providing VDD to each of the bases of the lateral p-n-p and grounding the source and gate of the MOSFET and collectors of the lateral p-n-p, whereby a parasitic lateral n-p-n turns on and safely discharges ESD current to ground when an ESD event occurs by creating an avalanche generation of carriers near the drain of the P-Well junction and an increase in the lateral p-n-p collector current, wherein, during an ESD event, the emitter of the lateral p-n-p injects holes into the isolated P-Well, lowering the ESD trigger voltage and increasing the failure current of the MOSFET.