Patent ID: 7847384

Claim:
A semiconductor package comprising: a semiconductor chip; a sealing resin for sealing the semiconductor chip, the sealing resin comprised of a single-continuous layer of resin and defining a first surface at a lower extent of the sealing resin and a second surface opposite from the first surface at an upper extent of the sealing resin; a wiring including a pattern wiring part connected to the semiconductor chip and a post part, the pattern wiring part having a lower surface and an upper surface and is formed such that the lower surface is exposed from the first surface of the sealing resin and the upper surface is in contact with the first surface of the sealing resin, the post part extending in a thickness direction of the sealing resin and having a first end connected to the upper surface of the pattern wiring part and a second end exposed from said second surface of said sealing resin; a first electrode in contact with the lower surface of the pattern wiring part; a second electrode on the second end of the post part which is exposed from the second surface of the sealing resin; and a test electrode formed directly on the lower surface of the pattern wiring part adjacent to the first electrode, wherein the test electrode remains open to the outside for testing said semiconductor chip, and wherein the first electrode includes a first layer formed on the lower surface of the pattern wiring part and a second layer formed on the first layer.