Patent ID: 7755077

Claim:
A semiconductor memory device comprising: a first bit line and a second bit line formed by the same interconnection layer, running in the same direction, and adjacent to each other; a first word line and a second word line intersecting the first bit line and the second bit line, and adjacent to each other; a first transistor having a first gate electrode, a first source/drain diffusion region, and a second source/drain diffusion region, the first gate electrode being connected to the first word line, the first source/drain diffusion region and the second source/drain diffusion region being positioned below the second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region being positioned between the first word line and the second word line and connected to the first bit line; a second transistor having the second source/drain diffusion region shared by the first transistor, a second gate electrode, and a third source/drain diffusion region, the second gate electrode being connected to the second word line, and the second source/drain diffusion region and the third source/drain diffusion region being positioned below the second bit line to sandwich the second word line therebetween; a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having one terminal connected to the second bit line and the other terminal connected to the first source/drain diffusion region; and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having one terminal connected to the second bit line and the other terminal connected to the third source/drain diffusion region.