Patent ID: 8395939

Claim:
A method for generating back pattern effect compensation in a memory device, the method comprising: generating an indication of a back pattern effect in a string of memory cells by: biasing all select lines coupled to the string of memory cells, wherein a selected one of the select lines, the select line closest to a drain select gate, and all of the select lines between the selected one and the select line closest to the drain select gate are biased from a selected one of the select lines to a select line closest to a drain select gate, with a first bias voltage; and wherein the select lines, other than the selected one, the select line closest to the drain select gate, and all of the select lines between the selected one and the select line closest to the drain select gate, are biased with a second bias voltage that is greater than the first bias voltage; and compensating a read operation of the string of memory cells in response to the indication.