Patent ID: 7599982

Claim:
A method for using the Newton-Raphson technique to perform a division operation within an arithmetic-logic unit (ALU) of a computer system, comprising: receiving a numerator a and a denominator b; and dividing a by b within the ALU by first using the Newton-Raphson technique to find 1/b, and then multiplying 1/b by a to produce the result a/b; wherein using the Newton-Raphson technique to find 1/b involves obtaining an initial estimate x 0 for 1/b and iteratively solving the equation x i+1 =x i (2−bx i ) by, using a multiplier circuit to multiply b by x i to compute bx i , performing a bit-wise complement operation on bx i to compute 2−bx i , whereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation, and using the multiplier circuit to multiply x i by 2−bx i to compute x 1 (2−bx i ), wherein a separate inverter and a separate multiplexer are attached to each bit position of the multiplier circuit to selectively perform a bit-wise complement or a shift operation during specific passes through the multiplier circuit.