Patent ID: 7353320

Claim:
A memory module, comprising: at least one memory device; and a memory hub, comprising: a link interface operable to receive memory requests for access to memory cells in the at least one memory device; a memory device interface coupled to the at least one memory devices, the memory device interface being operable to couple memory requests to the at least one memory devices for access to memory cells in the at least one memory device and to receive read data responsive to at least some of the memory requests; a performance determining device coupled to the memory device interface, the performance determining device operable to track at least one performance metric; and a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance determining device.