Patent ID: 8039877

Claim:
A semiconductor device having a heavily doped p-type (110) semiconductor layer overlying a metal substrate, comprising: a first metal layer; a first p-type semiconductor layer overlying the first metal layer, the first p-type semiconductor layer being heavily doped and having a surface crystal orientating of (110), the first p-type semiconductor layer being characterized by a first conductivity; a second p-type semiconductor layer overlying the first p-type semiconductor layer, the second semiconductor layer having a surface crystal orientation of (110) and a second conductivity that is lower than the first conductivity; a gate dielectric layer including a high dielectric constant material, the gate dielectric layer lining a (110) crystalline plane in the second p-type semiconductor layer; and a second metal layer overlying the second p-type semiconductor layer, wherein a current conduction between the first metal layer to the second metal layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane.