Patent ID: 7426665

Claim:
A method for testing a routing circuitry in a field programmable gate array (FPGA) having a first FPGA tile, the routing circuitry having a plurality of first sets of tracks running in a first direction, each first set of tracks having a plurality of individual track segments that are programmably connectable to one another between a first end and a second end by individual programmable elements, the method comprising: providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of tracks; defining individual test inputs to apply to the first end of each of the at least two of the first sets of tracks; determining an expected logic result for a selected logical combination of the individual test inputs to the at least two of the first sets of tracks; applying the individual test inputs to the first end of each of the at least two of the first sets of tracks; performing the selected logical combination on the second ends of the at least two of the first sets of tracks to generate an actual logic result; and flagging an error if the actual result is not identical with the expected logic result.