Patent ID: 6887763

Claim:
A transistor formation method for an integrated circuit device comprising: providing a substrate for said integrated circuit device; forming a gate dielectric layer on said substrate; forming a gate structure on said gate dielectric layer having a gate oxide layer formed on said gate dielectric layer and having a metal silicide layer formed on said gate oxide layer, said gate structure having a first sidewall and a second sidewall, said first sidewall having a thickness of less than about 150 Angstroms and a second sidewall having a thickness in the range of about 400 to 1000 Angstroms, a first contact region, a channel region and a second contact region, said first contact region and said second contact region positioned at least partially between said first sidewall and said second sidewall within said substrate; and forming first and second subregions within said second contact region, each subregion having a dopant concentration that differs from that of the other subregion, said forming of each said first subregion comprising: depositing a thin conformal layer of dielectric material over said substrate; anisotropically etching said conformal layer of dielectric material for forming a first single thin layer sidewall spacer of dielectric material on said first sidewall and said second sidewall; performing an annealing/oxidation process on said dielectric material on said first sidewall and said second sidewall; forming a second single layer sidewall spacer overlying said first sidewall spacer; and introducing a dopant into said substrate to form said first subregion, said first subregion being generally aligned with said second sidewall spacer; forming said second subregion comprising: depositing a conformal layer of dielectric material over said second single layer sidewall spacer; anisotropically etching said conformal layer of dielectric material for forming an additional layer sidewall spacer on said second sidewall spacer; performing an annealing/oxidation process on said dielectric material on said additional layer sidewall spacer; and introducing said dopant into said substrate to form said second subregion, said second subregion being generally aligned with said additional layer sidewall spacer.