Patent ID: 8313999

Claim:
A method of forming a multi-gate transistor, comprising: forming a gate stack over a channel region of semiconductor fin having a gate-coupled channel sidewall height (H si ); implanting an etch rate controlling dopant into a source/drain region of the semiconductor fin adjacent to the gate stack; etching a doped fin region proximate to the channel region to remove a thickness of the semiconductor fin that is approximately equal to H si and form a source/drain extension cavity that undercuts the gate stack by an amount substantially constant across H si and exposes a semiconductor substrate portion subjacent to a portion of the gate stack; etching a region of the semiconductor fin distal from the channel region to remove a thickness of semiconductor that is greater than the thickness removed proximate to the channel region; and growing a material on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension cavity and extending a length away from the gate stack in a direction substantially parallel to a length of the channel.