Patent ID: 7741217

Claim:
A method of fabricating a CMOS diode comprising the steps of: forming a gate structure on a silicon substrate; doping the silicon substrate to form a P doped region and an N doped region on the silicon substrate, wherein the step of doping the silicon substrate to form the P doped region and the N doped region on the silicon substrate is performed via ion implantation; forming an N-side hardmask, wherein the N-side hardmask is comprised of silicon oxide with a thickness in the range of about 20 nanometers to about 80 nanometers; forming a P-type silicide region on the P doped region of the silicon substrate; removing the N-side hardmask; forming a P-side hardmask, wherein the P-side hardmask is comprised of silicon oxide with a thickness in the range of about 20 nanometers to about 80 nanometers; forming an N-type silicide region on the N doped region of the silicon substrate; removing the P-side hardmask; and forming a nitride layer over the silicon substrate, gate structure, and silicide, the step of forming a nitride layer comprises depositing a nitride layer using a chemical vapor deposition process; and wherein the step of forming an N-type silicide region comprises the steps of: sputtering a metal selected from the group consisting essentially of Erbium, Ytterbium, Yttrium, Holmium, Terbium, Gadolinium, Lutetium, Dysprosium, and Scandium; and annealing the metal at a temperature in the range of about 200 degrees Celsius to about 550 degrees Celsius.