Patent ID: 7781274

Claim:
A method for manufacturing a multi-gate field effect transistor, comprising: forming a plurality of semiconductor layers in parallel on a substrate; forming a protection film on an upper face of each semiconductor layer; forming a first insulating layer on the semiconductor layers, the first insulating layer covering side faces of each semiconductor layer and side faces and an upper face of the protection film; forming a first interlayer insulating film on an entire surface and flattening the first interlayer insulating film to expose an upper face of each first insulating layer; removing the first insulating layers to form a plurality of holes at locations from which the first insulating layers are removed; forming a gate insulating film on both side faces of each semiconductor layer inside the holes; forming a gate metal film to cover side faces and a bottom face of each hole, the gate insulating film, and the protection film inside the holes; forming a polysilicon film to cover the gate metal film; etching the polysilicon film and the gate metal film existing in each hole, so as not to expose the gate metal film on the protection film; depositing again a polysilicon film to fill each hole; flattening the polysilicon film to divide the polysilicon film into a plurality of polysilicon layers and expose an upper face of the first interlayer insulating film; forming masks having shapes of gate electrodes on the polysilicon layers; patterning the polysilicon layers with the use of the masks; forming sidewalls made of an insulator so that the sidewalls sandwich the patterned polysilicon layers in a gate length direction; patterning the protection film with the use of the sidewalls to selectively expose an upper face of each semiconductor layer; implanting an impurity into the selectively exposed semiconductor layers to form source and drain regions; removing the masks to expose an upper face of each polysilicon layer; forming a second interlayer insulating film on an entire surface, forming an opening continuing to each of the polysilicon layers on the second interlayer insulating film, and filling the opening to form a metal connecting portion connecting the polysilicon layers; and forming a wire connected to the connecting portion.