Patent ID: 7320116

Claim:
A method of generating library data for a cell constructed of interconnected MOS transistors having source and drain regions with metal silicided surfaces, the method comprising: a resistance extraction step which extracts source and drain resistances for the MOS transistors according to source and drain region surface areas by using a resistance calculating formula or referring to a resistance extraction reference file which, when the source and drain regions have surface areas with a first surface area region, treats the source and drain resistances as resistance values which depend on said surface areas, and when the source and drain regions have surface areas with a second surface area region that is larger than the first surface area region, treats the source and drain resistances as fixed resistance values which are independent of said surface areas; and a simulation step which generates an input-output characteristic for the cell from a netlist containing a MOS transistor model that includes the source and drain resistances extracted in the resistance extraction step and connection information for the model, and from input signals.