Patent ID: 8873292

Claim:
A nonvolatile semiconductor memory device comprising: a plurality of memory cells configured to hold a threshold voltage included in any one of a plurality of threshold voltage distributions; a memory cell array having NAND cell units arranged therein, each of the NAND cell units including a memory string in which the memory cells are connected in series and select transistors connected to both ends of the memory string, respectively; word lines connected to the memory cells; bit lines connected to a first end of each of the NAND cell units; a source line connected to second ends of the NAND cell units; and a control circuit configured to control a data read operation, when controlling the data read operation, the control circuit applying one of read voltages to a selected word line connected to a selected memory cell, each of the read voltages being set to a voltage between two adjacent threshold voltage distributions, the control circuit applying a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, the first read pass voltage being set so that the data-written memory cells become conductive regardless of the kind of the plurality of threshold voltage distributions formed by the data-written memory cells, and the control circuit applying a second read pass voltage to a second non-selected word line connected to a non-written memory cell, the second read pass voltage being set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages.