Patent ID: 6999357

Claim:
A memory circuit comprising: a regular memory cell array having a plurality of redundant replacement units; a plurality of input/output circuits each of which corresponds to the plurality of redundant replacement units; a redundant memory cell array coupled with the regular memory cell array; a redundant replacement memory for storing data on the redundant replacement unit having the failed portion in the regular memory cell array; and a pre-charge circuit having pre-charge switches for redundant replacement units and the redundant memory cell array respectively, wherein depending on the data stored in the redundant replacement memory, the redundant replacement unit having the failed portion in the regular memory cell array is or is not replaced with the redundant memory cell array, in case where a failed portion does not exist in the regular memory cell array, the pre-charge switches of the plurality of redundant replacement units are enabled, and the pre-charge switch of the redundant memory cell array is not enabled, and in case where a failed portion exists in the regular memory cell array, the pre-charge switch of the redundant replacement unit having a failed portion is disabled and the pre-charge switches of the remaining redundant replacement units and the redundant memory cell array are enabled.