Patent ID: 8410485

Claim:
A pixel structure, comprising: a scan line having a mainline and a branch; a semiconductor layer disposed on the mainline and the branch to respectively define a first gate and a second gate; a data line intersected with the mainline; a source directly connected to the data line, disposed on the semiconductor layer, and located between the first gate and the second gate; a first drain contacting the semiconductor layer, and the first gate being located between the first drain and the source; a second drain contacting the semiconductor layer, and the second gate being located between the second drain and the source; a third gate, electrically connected to the scan line, wherein the third gate and the first gate are located between the source and the first drain and the second gate is located between the source and the second drain; a first pixel electrode electrically connected to the first drain; and a second pixel electrode electrically connected to the second drain.