Patent ID: 8799702

Claim:
A method for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device, the method comprising: exchanging a first set of bussed bits between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge; in response to detecting a failure in the first link, at a PCIE bridge end, swapping from using the first set of lanes to using a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device, wherein the first and the second PCIE bridges are housed in a PCIE root complex, in response to detecting the failure in the first link, at an IO device end, switching from using the first set of lanes to using the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.