Patent ID: 7280399

Claim:
A semiconductor memory array, comprising: a plurality of semiconductor dynamic random access memory cells arranged in a plurality of rows and columns, each semiconductor dynamic random access memory cell includes a transistor including: a source region; a drain region; a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and a gate spaced apart from the body region; wherein each memory cell includes: (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell wherein the second charge is substantially provided by removing majority carriers from the body region through the source region of the transistor of the memory cell; and wherein the source region of the transistor of each memory cell of a first row of semiconductor dynamic random access memory cells is connected to the same source line and wherein the gate of the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells is connected to the same word line.