Patent ID: 7879669

Claim:
A method of fabricating an enhancement-mode field-effect transistor from a semiconductor body having body material of a first conductivity type, the method comprising: providing a gate electrode above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone for the transistor; and subsequently (a) introducing semiconductor dopant of the first conductivity type into at least the intended channel-zone portion of the body material and (b) introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to form first and second source/drain zones of the second conductivity type laterally separated by the channel zone such that the first source/drain zone comprises a main source/drain portion and a more lightly doped lower source/drain portion underlying, and vertically continuous with, the main source/drain portion, the channel zone having a channel length extending along the gate dielectric layer from either of the source/drain zones to the other of the source/drain zones, the transistor having a threshold voltage which depends on the channel length at a given set of post-layout fabrication process conditions so as to reach a maximum absolute value V TAM at a value L C of the channel length, to be at least 0.03 volt less than V TAM in absolute value when the channel length is approximately 0.3 μm greater than L C , and to be materially decreasing with increasing channel length when the channel length is approximately 1.0 μm greater than L C .