Patent ID: 6969657

Claim:
A process for manufacturing a power device comprising: providing a semiconductor substrate; growing epitaxially a first semiconductor layer of a first conductivity on said semiconductor substrate; forming a mask over a free surface of said first semiconductor layer, said mask including a plurality of windows exposing portions of said semiconductor layer, and being capable of blocking implants; performing a series of implants through said implant windows to form a plurality of vertically adjacent regions of a second conductivity in said first semiconductor layer below said implant windows; and applying a diffusion drive to link said regions of said second conductivity to form vertically oriented regions of said second conductivity in said first semiconductor layer; growing epitaxially a second semiconductor layer of said first conductivity over said first semiconductor layer of said first conductivity; forming a second mask over a free surface of said second semiconductor layer, said second mask including a plurality of windows exposing portions of said second semiconductor layer, and being capable of blocking implants; and performing a series of implants through said implant windows in said second mask to form a plurality of vertically adjacent regions of said second conductivity in said second semiconductor layer below said implant windows and above said vertically oriented regions of said second conductivity in said first semiconductor layer; forming a channel region of said second conductivity above said second semiconductor layer; forming a plurality of MOS-gated structures through said channel region; forming conductive regions of said first conductivity adjacent each MOS-gated structure; forming a first electrical contact on said substrate; and forming a second electrical contact in electrical contact with at least said conductive regions of said first conductivity; wherein said vertically oriented regions of said second conductivity are in substantial charge balance with said first and said second semiconductor layers.