Patent ID: 8148757

Claim:
A semiconductor device comprising: a base substrate comprising a semiconductor layer at least by a surface of the base substrate; a channel region formed in the semiconductor layer; first and second diffusion layers formed in the semiconductor layer so as to sandwich the channel region; an insulating film formed on the base substrate so as to cover the channel region; and a gate electrode formed on the base substrate via the insulating film; wherein the insulating film contains a structure in which a first insulating region containing an electric charge trap, a second insulating region containing no electric charge trap, and a third insulating region containing an electric charge trap are disposed in this order in a direction from the first diffusion layer to the second diffusion layer along the channel region of the semiconductor layer; wherein the channel region between the first and second diffusion layers has first to third planes in the order from the first diffusion layer side; wherein a boundary of the first plane and the second plane and a boundary of the second plane and the third plane are formed so as to be practically perpendicular to the direction from the first diffusion layer to the second diffusion layer; wherein the first insulating region containing the electric charge trap is disposed on the first plane; wherein the second insulating region containing no electric charge trap is disposed on the second plane; and wherein the third insulating region containing the electric charge trap is disposed on the third plane.