Patent ID: 8693243

Claim:
A memory array, comprising: a plurality of memory cells; a plurality of paralleled bit lines formed on a semiconductor substrate, and a plurality of word lines perpendicular to the bit lines, wherein each bit line is connected to a source and a drain of adjacent memory cells; a part of a word line between adjacent bit lines is connected to a gate of a memory cell; wherein, the memory cells are split-gate memory cells, each comprising a first memory bit cell arranged between a word line and a source of the memory cell, and a second memory bit cell arranged between the word line and a drain of the memory cell, the first and the second memory bit cells comprising a first control gate and a second control gate, respectively; the memory array further comprises a plurality of first control lines and second control lines connected to the first control gates and the second control gates, respectively, each pair of first control lines and second control lines being arranged on both sides of a word line and being parallel to the word line; and wherein the first and second memory bit cells share one word line, the first and second memory bit cells erasing electric charges by applying a high voltage of 9 V to 12 V to the word line or by both applying a high voltage of 5 V to 10 V to the word line and applying a negative voltage of −5 V to −10 V to the first/second control gate.