Patent ID: 7461286

Claim:
A memory system comprising: a reference clock generator operable to generate a reference clock signal; a first memory module coupled to the reference clock generator, the first memory module operable to generate an internal clock signal based at least in part on the reference clock signal; a second memory module coupled to the reference clock generator and operable to generate an internal clock signal based at least in part on the reference clock signal, the second memory module being coupled to the first memory module, the second memory module operable to transmit data to the first memory module and to receive data from the first memory module; and wherein the first and second memory modules each comprises a receiver comprising: a phase adjustment circuit configured to receive data and a predetermined pattern of data, and operable to compare the received data and the predetermined pattern of data to adjust a phase of its internal clock signal based on the comparison to generate a receive clock signal; and a capture circuit coupled to receive the receive clock signal from the phase adjustment circuit and the data transmitted from the other memory module, the capture circuit being operable to capture the data transmitted from the other memory module in the receiver responsive to the receive clock signal.