Patent ID: 7551667

Claim:
An equalizer, comprising: an integrated block comprising: a tapped filter having multiple filter multipliers; a correlator having multiple correlator multipliers; and a set of shared delay elements to connect to said multiple filter multipliers and said multiple correlator multipliers, with each delay element to include at least two delay stages in series, with a first delay stage to receive an input data signal and output a first delay signal to one of said multiple correlator multipliers and to a second delay stage in the delay element, said first delay signal having a first amount of delay that corresponds to an amount of delay through one of said multiple correlator multipliers and an error signal generator, and the second delay stage to receive said first delay signal as an input and output a second delay signal to one of said multiple filter multipliers, said second delay signal having amount of delay that corresponds to a difference between a total delay for a delay element and said first amount of delay, wherein each correlator multiplier receives as input a data signal with said first amount of delay from a first delay stage of said set of shared delay elements.