Patent ID: 6947309

Claim:
A ferroelectric memory device comprising: a memory cell array region divided into a plurality of sector regions in row and column directions; a plurality of main-wordlines disposed in the memory cell array region in parallel along the row direction; a plurality of main-bitlines disposed in the memory cell array region in parallel along the column direction; a plurality of sub-wordlines, each of the sub-wordlines being provided for one of the main-wordlines in one of the sector regions; a plurality of sub-bitlines, each of the sub-bitlines being provided for one of the main-bitlines in one of the sector regions; a plurality of ferroelectric memory cells, each of the ferroelectric memory cells being disposed at an intersecting point of one of the sub-wordlines provided for one of the main-wordlines and one of the sub-bitlines provided for one of the main-bitlines; a plurality of first sub-wordline select switches, each of the first sub-wordline select switches being disposed between one of the main-wordlines and one end of one of the sub-wordlines provided for the one main-wordline and being driven independently at least in one of the sector regions; a plurality of first sub-bitline select switches, each of the first sub-bitline select switches being disposed between one of the main-bitlines and one end of one of the sub-bitlines provided for the one main-bitline and being driven independently at least in one of the sector regions; at least one unselected wordline potential supply line which supplies an unselected wordline potential to the sub-wordlines; at least one unselected bitline potential supply line which supplies an unselected bitline potential to the sub-bitlines; a plurality of second sub-wordline select switches, each of the second sub-wordline select switches being disposed between the other end of one of the sub-wordlines and the unselected wordline potential supply line and being driven independently at least in one of the sector regions; and a plurality of second sub-bitline select switches, each of the second sub-bitline select switches being disposed between the other end of one of the sub-bitlines and the unselected bitline potential supply line and being driven independently at least in one of the sector regions.