Patent ID: 7824970

Claim:
A method for manufacturing a semiconductor structure, comprising: forming a semiconductor layer on a substrate, in which the semiconductor layer is provided with a source area and a drain area; forming a patterned first dielectric layer on the semiconductor layer; forming a patterned first metal layer on the patterned first dielectric layer, in which the patterned first metal layer has a data line and a gate electrode partially formed on the semiconductor layer respectively; forming a patterned second dielectric layer on the patterned first metal layer to define a first contact hole, a second contact hole, and third contact hole, wherein the first contact hole exposes portion of the source area and exposes portion of the data line, the second contact hole exposes portion of the drain area, and the third contact hole exposes portion of the gate electrode; and forming a patterned second metal layer on the patterned second dielectric layer, in which the patterned second metal layer has a gate line, a common electrode, a source line and a drain line, wherein the gate line is partially formed on the gate electrode, and the gate line is electrically connected to the gate electrode through the third contact hole, the common electrode is partially formed on the data line, the source line covers the first contact hole and is electrically connected to the data line and the source area, and the drain line covers the second contact hole and is electrically connected to the drain area.