Patent ID: 8415985

Claim:
A sample and hold circuit capable of operating on a single positive supply voltage, the sample and hold circuit comprising: first and second input switch circuits configured to receive first and second input signals of a differential signal, respectively, each of the first and second input switch circuits comprising: an output, and a PMOS switch coupled in series with an NMOS switch; a sample and hold circuitry comprising: first and second sampling capacitors, each having an output terminal, and a plurality of switches configured to: electrically couple the outputs of the first and second input switch circuits with the first and second sampling capacitors, respectively, to enable a sampling of the first and second input signals at the first and second sampling capacitors, respectively, in a sample phase, and isolate the first and second input signals from the first and second sampling capacitors, respectively, in a hold phase; and an operational amplifier having first and second inputs and first and second outputs, the first and second inputs coupled with the output terminals of the first and second sampling capacitors, respectively, and the plurality of switches being further configured to pass a differential of the first and second input signals in the hold phase at the first and second outputs of the operational amplifier; wherein the NMOS switch comprises: a main NMOS switch; a bootstrapping circuit comprising one or more NMOS switches and bootstrapping capacitors connected to a gate of the main NMOS switch; and a bulk voltage control circuit connected to a bulk of the main NMOS switch, the bulk voltage control circuit configured to maintain a bulk voltage of the main NMOS switch equal to a voltage at one of a source terminal and a drain terminal of the main NMOS switch in the sample phase, and to maintain a pull down of the bulk voltage by a threshold voltage in the hold phase.