Patent ID: 8489943

Claim:
A system comprising: a memory; a processor; and an integrated circuit (IC) chip coupled to the memory and to the processor, the IC chip comprising: a plurality of input-output (IO) cells; a controller to exchange signals between the memory and the processor through the plurality of IO cells; and a protocol sequence generator comprising a control unit to receive at least one control signal to generate at least one synchronized control signal, wherein the at least one synchronized control signal is synchronized with an external clock signal and a sequencing unit in communication with the IO cells to receive an internal clock signal derived from the external clock signal and the at least one synchronized control signal to generate test signals, said protocol sequence generator operative to generate test signals to test characteristics of the plurality of IO cells, wherein the protocol sequence generator generates the test signals based on said at least one synchronized control signal, wherein the protocol sequence generator is in communication with the cells through a switching unit, and the controller is in direct communication with the IO cells and also through the switching unit.