Patent ID: 8124976

Claim:
A semiconductor device including a plurality of SRAM cell units, each of the SRAM cell units comprising: a data holding section comprising a pair of a first driving transistor and a second driving transistor and a pair of a first load transistor and a second load transistor; a data write section comprising a pair of a first access transistor and a second access transistor; and a data read section comprising a third access transistor and a third driving transistor, wherein: each of the first driving transistor, second driving transistor, first load transistor, second load transistor, first access transistor, second access transistor, third access transistor, and third driving transistor comprises a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of a source area and a drain area provided in the semiconductor layer, a longitudinal direction of each of the semiconductor layers is provided along a first direction, a longitudinal direction of each of the gate electrodes is perpendicular to the first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first direction in the other transistor.