Patent ID: 8445972

Claim:
A semiconductor device comprising: a circuit comprising transistors, including at least a first transistor, a second transistor, and a third transistor, wherein each of the transistors includes: a gate electrode formed above a semiconductor substrate; source/drain regions formed in the semiconductor substrate below and on both sides of the gate electrode; and a charge storage layer formed on and in direct contact with an upper surface of the semiconductor substrate and interposed between the gate electrode and the semiconductor substrate, wherein the source/drain regions of the transistors are connected in series so as to form a closed loop, wherein the source/drain regions in adjoining transistors are respectively connected to form the closed loop, wherein the first transistor shares one of the source/drain regions with the second transistor, and the second transistor shares another one of the source/drain regions with the third transistor, and wherein a reconfigurable logical function of the circuit is selected by controlling an amount of charge stored in the charge storage layer of each of the transistors, and wherein the circuit can be configured as a non-volatile memory cell.