Patent ID: 6967141

Claim:
A method of manufacturing a semiconductor integrated circuit device, comprising steps of: (a) forming a first silicon oxide film over a semiconductor substrate; (b) forming an oxidation resistant film over said first silicon oxide film; (c) selectively etching said oxidation resistant film and said first silicon oxide film; (d) recessing an end of said first silicon oxide film inward more than an end of said oxidation resistant film so as to expose a surface of said semiconductor substate under the end of said oxidation resistant film; (e) forming a second silicon oxide film having a thickness larger than that of said first silicon oxide film over said semiconductor substrate by a thermal oxidation method, so that a front portion of said second silicon oxide film, under said oxidation resistant film, extends into the end of the first silicon oxide film and into the semiconductor substrate surface; (f) exposing a surface of an element isolation region by etching said second silicon oxide film, wherein said surface of said element isolation region has an inclined surface which extends under the end of the oxidation resistant film; (g) after said step (f), forming a trench in said semiconductor substrate of said element isolation region by etching said semiconductor substrate using said oxidation resistant film as a mask; (h) forming a third silicon oxide film over an inner wall of said trench by a thermal oxidation method, wherein both edge portions of said inclined surface are rounded; (i) forming a fourth silicon oxide film over said oxidation resistant film and inside of said trench; (j) forming an element isolation trench in said element isolation region by polishing said fourth silicon oxide film using said oxidation resistant film as a stopper; (k) removing said oxidation resistant film; (l) introducing impurities into said semiconductor substrate to control threshold voltage of a MISFET; (m) exposing said surface of said semiconductor substrate; and (n) forming a gate insulating film over said semiconductor substrate and gate electrode for said MISFET over said gate insulating film.