Patent ID: 7533363

Claim:
An IC design layout processing system having computer instructions stored in or on a computer-readable medium to be executed by a processor, the instructions comprising: instructions for receiving an IC design layout containing at least two segregated pieces of critical data; instructions for enabling a halo range to be pre-specified to determine an interact area between one geometry of the IC design layout and another geometry of said IC design layout for processing the IC design layout; instructions for identifying a part of the IC design layout comprising at least one piece of non-critical data such that said piece of non-critical data is within the pre-specified halo range of said at least two segregated pieces of critical data; and instructions for processing the critical data and non-critical data that is within the pre-specified halo range of said at least two segregated pieces of critical data, wherein a partition is produced and wherein said at least two segregated pieces of critical data are processed independently from each other; and instructions for combining processed data of the IC design layout; whereby the non-critical data within the pre-specified halo range of each of said at least two segregated pieces of critical data is processed together with the critical data of each of said at least two segregated pieces of critical data.