Patent ID: 8264257

Claim:
An integrated circuit on a semiconductor wafer, comprising: a contact pad; and a first data buffer circuit coupled to the contact pad, the first data buffer circuit including: a first transistor and a second transistor coupled together, each having a conduction terminal coupled to the contact pad; a third transistor in series with the first transistor, the third transistor having a conduction terminal coupled to a first bias voltage terminal configured to receive a first bias voltage; and a fourth transistor in series with the second transistor, the fourth transistor having a conduction terminal coupled to a second bias voltage terminal configured to receive a second bias voltage; and means for applying: a third bias voltage less than the second bias voltage on a control terminal of the first transistor, a fourth bias voltage greater than the first bias voltage on a control terminal of the second transistor, and data signals on a control terminal of the third transistor and on a control terminal of the fourth transistor, wherein the means for applying include: boost means for supplying the third bias voltage; means for storing a setpoint signal and for applying to the boost means the setpoint signal and determine an amplitude of the third bias voltage supplied by the boost means.