Patent ID: 8159018

Claim:
A method for manufacturing a finFET-based non-volatile memory device on a semiconductor substrate including source and drain regions, a fin body, a charge trapping stack and a gate; the fin body extending between the source region and the drain region, the fin connecting the source region and the drain region; the charge trapping stack being arranged to cover at least a portion of the fin body; the gate being arranged to cover the charge trapping stack at the location of the fin body, the method comprising: forming the fin body with an entirely corner-free shape and on a gap defined by a lower surface of the fin body and an upper surface of an underlying substrate; etching to provide a recess level that is either equal to, or larger than, the thickness of a layer of the charge trapping stack; and wherein: the substrate comprises an insulating layer, which is covered by a monocrystalline silicon layer; the source and drain regions and the fin body being arranged in the monocrystalline silicon layer, the insulating layer adjacent to the source and drain regions and the fin body being recessed to a recess level; the etching is extended to a level that the insulating layer under the fin body is completely removed; and the etching is achieved by combining a first anisotropic dry etching for partly recessing the insulating layer under the fin body with a second isotropic oxide etching for removing the insulating layer below the fin body.