Patent ID: 8513723

Claim:
An integrated circuit comprising: a substrate having a first device region and a second device region, wherein the first device region of the substrate includes a first semiconductor layer present on a buried insulating layer, wherein the buried insulating layer is present on a second semiconductor layer, and the second device region includes the second semiconductor layer, in which the first semiconductor layer and the buried insulating layer are not present in the second device region; a finFET semiconductor device located in the first device region of the substrate, wherein the first semiconductor layer provides a fin body of the finFET semiconductor device and a finFET gate structure is present on a channel potion of the fin body; and a capacitor is in the second device region, the capacitor includes a buried plate electrode, a node dielectric and an upper electrode, wherein the buried plate electrode is present in the second semiconductor layer of the substrate and includes plateaus of material from the second semiconductor layer, wherein adjacent plateaus are separated by recessed regions of the second semiconductor layer, and an upper surface of the plateaus of second semiconductor layer that provides the buried plate electrode are vertically offset from an upper surface of the fin body, and an upper surface of the finFET gate structure is coplanar with an upper surface of the upper electrode, wherein the node dielectric is present on the buried plate electrode, and the upper electrode is present on the node dielectric.