Patent ID: 7595681

Claim:
A circuit for compensating for a variance in resistance of a buried resistor, the compensation circuit comprising: a waveform that is representative of the thermal characteristics of a first and second buried resistor ( 506 , 508 ); functions to compensate for the variance in resistance according to the waveform; the compensation circuit ( 500 ) further comprises a first and second thermal compensation unit ( 502 , 504 ), a first and second inverter (INVA, INVB), and a differential driver ( 510 ); the differential driver ( 510 ) further comprising at least a first and second pFET (PA, PB), and a first and second nFET (NA, NB), the first and second pFET (PA, PB) are coupled in series with a voltage supply (VDD) and the first and second buried resistor ( 506 , 508 ) and the first and second nFET (NA, NB) respectively; the first thermal compensation unit ( 502 ) comprises a fast response circuit ( 512 ), a slow response circuit ( 514 ), and an amplifying circuit ( 516 ); the slow response circuit ( 514 ) comprises a third pFET (P 1 ) coupled in series with a third resistor (R 11 ) coupled in series with a first capacitor (C 1 ), a fifth resistor (R 12 ) coupled in series to a third nFET (N 1 ), the fifth resistor (R 12 ) and the third nFET (N 1 ) are coupled in parallel to the first capacitor (C 1 ) and further coupled to ground; the third pFET (P 1 ) further coupled to the output of the first inverter (INVA), receives a first inverter signal at its gate; an eighth resistor (R 2 ) is further coupled to the outputs of the third resistor (R 11 ) and the first capacitor (C 1 ) and feeds a first operational amplifier ( 516 A), which in turn couples to the gate of the first pFET (PA) of the differential driver ( 510 ); the fast response circuit ( 512 ) comprising a fourth pFET (Pf) whose gate is coupled to the output of the first inverter (INVA) and the drain is coupled to a fourth resistor (Rf 1 ), which is further coupled to a second capacitor (Cr) and ground; a sixth resistor (Rf 2 ) is coupled in series to a fourth nFET (Nf) and are subsequently coupled in parallel with the second capacitor (Cr); a ninth resistor (R 3 ) is coupled to the fourth resistor (Rf 1 ) and the second capacitor (Cr), the ninth resistor (R 3 ) is further coupled in series to a seventh resistor (R 1 ), which is further coupled to the gate of the first pFET (PA), thereby altering the resistance of the first pFET (PA) to compensate for variance in resistance of first resistor ( 506 ).