Patent ID: 8536628

Claim:
An integrated circuit comprising: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell comprises: a transistor having a gate, a gate dielectric, and source, drain, and body regions, wherein: (i) the body region is electrically floating; and (ii) the source region is a portion of a common source region that is shared between transistors of adjacent memory cells; a first plurality of barriers, wherein the common source region of transistors of adjacent memory cells is formed with an associated barrier disposed therein to form a discontinuity between separate portions of the common source region such that a first portion of the common source region forming the source region of a respective transistor is separated from a second portion of the common source region forming the source region of a respective adjacent transistor, wherein the associated barrier includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common source region, wherein the associated barrier and the common source region are disposed over and directly coupled to a common base region; and a plurality of electrical contacts, wherein at least one electrical contact is electrically and directly coupled to separate portions of an associated common source region and its associated barrier which is disposed therein.