Patent ID: 7089170

Claim:
A method of testing an embedded electronic system having a target processor adapted to execute a target program, the target processor being coupled to target hardware that has a physical portion and a simulated portion, the method comprising: monitoring signals present on a plurality of externally accessible terminals of the target processor as the target processor executes the target program; determining when the target processor is attempting to access the simulated portion of the target hardware by inputting monitored address signals into a mapping memory and outputting a stored map result from a corresponding address in the mapping memory, for each of the monitored address signals, from the mapping memory; in response to determining that the target processor is attempting to access the simulated portion of the target hardware, suspending execution of the target program; and in response to determining that the target processor is attempting to access the simulated portion of the target hardware, processing output signals present on a plurality of the externally accessible terminals in a hardware simulator.