Patent ID: 8519462

Claim:
A DRAM array comprising: a pair of cells, each cell comprising an access transistor having n-type source/drain regions defining a channel region, and a capacitor, one source/drain region of each access transistor in a first pair of cells being connected to a common via contact providing a connection to a bit line, the other source/drain region of each access transistor being separated from other source/drain regions of access transistors of adjacent pairs of cells by common channel regions defined by the n-type source/drain regions; access word lines extending generally perpendicular to the bit line, each access word line extending over a channel region of an access transistor, the access word lines comprising a material with a work function favoring n-channel devices; and dummy word lines extending generally perpendicular to the bit line, each dummy word line extending over one of the common channel regions, the dummy word lines comprise a material with a work function favoring p-channel devices.