Patent ID: 7411840

Claim:
A sense mechanism for data bus inversion, comprising: a first memory device that stores bits of N-bit bus in a previous bus cycle; and an analog adder that compares said bits of said N-bit bus in said previous bus cycle with bits of said N-bit bus in a current bus cycle and that provides a data inversion signal indicative of whether more than half of said bits of said N-bit bus have changed state, wherein said analog adder comprises: a logic comparison circuit that compares said bits of said N-bit bus in said previous bus cycle with said bits of said N-bit bus in said current bus cycle and that provides a plurality of changed state bits; and an analog sense amplifier that provides said data inversion signal based on said plurality of changed state bits, wherein said analog sense amplifier comprises: a first voltage divider network that divides a first voltage referenced to a common voltage into a weight voltage at a weight node, said weight voltage being one of a plurality of discrete voltage levels indicative of a number of said plurality of changed state bits being asserted, said first voltage divider network comprising: at least one activated first P-channel device coupled between said weight node and said first voltage; and N equivalent-sized first N-channel devices coupled between said weight node and said common voltage, each having a gate receiving a corresponding one of said plurality of changed state bits; a reference circuit that provides a reference voltage relative to said first voltage and indicative of more than half of said plurality of changed state bits being asserted; and a comparator that compares said reference voltage with said weight voltage and that provides said data inversion signal.