Patent ID: 8838939

Claim:
A method, in a processor of processing system, for debugging application code, comprising: receiving an instruction in a hardware unit of the processor, the instruction having a target memory address that the instruction is attempting to access in a memory of the data processing system; searching a content addressable memory (CAM) associated with the hardware unit for an entry in the CAM corresponding to the target memory address, wherein each entry of a set of entries in the CAM comprise a start address a length, a store bit (S bit), and a load bit (L bit), wherein the S bit and the L bit identify types of instructions for which an exception is to be generated wherein a setting of either the S bit or the L bit to a predetermined value indicates that a corresponding type of instruction is an instruction for which the exception is to be generated, and wherein the processor searches the CAM by searching entries in the CAM for an en that falls within one of a plurality of entries indicated by a starting address and length corresponding to a range of memory addresses within which the target memory address is present; responsive to the entry in the CAM corresponding to the target memory address being found, determining whether information in the entry identifies the received instruction as the instruction for which the exception is to be generated by: determining a type of the received instruction:, determining whether the value in the entry indicates that the type of the received instruction is a type of instruction for which the exception should be generated; and responsive to the value in the entry indicating that the type of the received instruction is the type of instruction for which the exception should be generated, identifying that the received instruction is the instruction for which the exception is to be generated; responsive to the entry identifying the received instruction as the instruction for which the exception is to be generated, generating an exception and sending the exception to one of an exception handler or a debugger application; responsive to the exception handler or the debugger application detecting access to a particular variable with which the target memory address is associated, verifying that the instruction has procured a necessary synchronization construct prior accessing the particular variable thereby indicating that a race condition to the particular variable has not been encountered; and responsive to the exception handler or the debugger application detecting a failure to access the particular variable with which the target memory address is associated, verifying that the instruction has not procured the necessary synchronization construct prior to accessing the particular variable thereby indicating that the race condition to the particular variable has been encountered.