Patent ID: 8273633

Claim:
A method of forming a semiconductor device, comprising: providing a semiconductor substrate having a gate structure patterned thereon; performing a first ion implantation process to form source/drain extension regions in said semiconductor substrate on opposing sides of said gate structure; performing a first anneal process on said source/drain extension regions; forming dielectric spacers on sidewalls of said gate structure respectively; performing a second ion implantation process with said gate structure and said dielectric spacers as the mask to form source/drain regions in said semiconductor substrate; performing a third ion implantation process before performing said first anneal process and after performing said first ion implantation process to form halo regions in said semiconductor substrate in contact with said source/drain extension regions; performing a second anneal process on said source/drain regions; and performing a third anneal process on said semiconductor substrate after performing said second anneal process; wherein, said first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, said second anneal process is a rapid thermal anneal process performed at a temperature lower than 900° C. for a time of between about 1 second and 30 seconds, and said third anneal process is a laser anneal process.