Patent ID: 7687862

Claim:
A semiconductor device, comprising: a first transistor comprising a channel region at a top surface of a first active area; a second transistor comprising a channel region at a top surface of a second active area, wherein the top surface of the first active area is elevated or recessed with respect to the top surface of the second active area; and an isolation region disposed between the first transistor and the second transistor, a top surface of the isolation region being planar between the first and the second active areas, wherein the top surface of the second active area is elevated or recessed with respect to the top surface of the isolation region by a different amount than the top surface of the first active area is elevated or recessed with respect to the top surface of the isolation region, and wherein the top surface of the second active area of the second transistor is elevated or recessed with respect to an entire top surface of the isolation region.