Patent ID: 7200780

Claim:
A semiconductor memory comprising: a data memory having a plurality of memory regions to store data at addresses specified; a code memory having the same address space as the data memory to store error correction codes for correcting each piece of data that is stored in the memory regions of the data memory; an error correction code control circuit including an error correction code generation circuit, a syndrome generation circuit and an error correction code decoding circuit, generating an error correction code for correcting data read from any memory region of the data memory before the data is written back into the memory region, and comparing the generated error correction code with an error correction code read from the code memory corresponding to the memory region, thereby to determine whether the data is erroneous and to correct the data when the data is erroneous; and an error correction code function invalidity control circuit connected to the error correction code control circuit and a valid bit array, initializing into an invalid state a valid bit in each of memory cells of the valid bit array after power application, and invalidating an error correction function of the error correction code control circuit on pieces of data read from the memory regions of the data memory when the memory regions are accessed first after power application.