Patent ID: 7412581

Claim:
A memory access method comprising: detecting a write operation to a non-volatile memory; determining an access mode of said non-volatile memory corresponding to a value in a mode register for controlling said non-volatile memory performing a fast write operation of data to said non-volatile memory in response to a determined access mode that is a first mode; performing a slow write operation of data to said non-volatile memory, in response to a determined access mode that is a second mode; responding to a determined access mode that is a third mode by performing a write operation such that: if an address of said non-volatile memory from a processing logic indicates a write operation to a first address area, then said non-volatile memory write operation is executed according to said fast write operation of data, if an address of said non-volatile memory does not indicate a write operation to the first address area, then said non-volatile memory write operation is executed according to said slow write operation of data; and performing a cache write operation of data to a cache memory comprised of a random access memory based on an exception handler routine in response to a determined access mode that is a fourth mode.