Patent ID: 7808095

Claim:
An ultra slim semiconductor package comprising: a multilayer thin film layer including a first dielectric layer, a first redistribution layer on the first dielectric layer, and a second dielectric layer on the first redistribution layer; at least one semiconductor chip electrically connected to the first redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the first redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; a second redistribution layer on the top side of the molding part; a third second dielectric layer directly formed on the second redistribution layer; bumps for external connection formed on the molding part and electrically connected to the conductive structures through the second redistribution layer, wherein the bumps are adapted to be mounted on a circuit board, the bumps extending below a lowermost surface of the third dielectric layer; wherein substantially all of the bumps are disposed such that they do not overlap with a top side of the semiconductor chip; wherein the top side of the molding part has the same height as the top side of the semiconductor chip; and wherein, at one side of the semiconductor chip, a heat spreader is positioned between the bumps for external connection.