Patent ID: 7139202

Claim:
A semiconductor storage device, comprising: a memory array comprising a plurality of memory elements; a write state machine for applying a first voltage for performing a write operation or an erase operation, with respect to one of the plurality of memory elements, to the one memory element via a bit line connected thereto, and thereafter, applying a second voltage for verifying whether or not the write operation or the erase operation has been performed, with respect to the one memory element, to the one memory element via the bit line connected thereto; and a reset portion for grounding the bit line connected to the one memory element after the write state machine has applied the first voltage and before the write state machine has applied the second voltage, wherein at least one of the plurality of memory elements is a multi-level memory element and comprises a gate electrode provided via a gate insulating film on a semiconductor layer, a channel region provided under the gate electrode, diffusion regions provided on opposite sides of the channel region and having a conductivity type opposite to that of the channel region, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges independent of one another, and wherein each memory function section is formed by at least one of an insulating film including an insulator having a function of retaining charges, an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge is polarized by an electric field and in which a charge polarization state is held.