Patent ID: 7642619

Claim:
A semiconductor device, comprising: one or more levels of semiconductor structure, each level of semiconductor structure including one or more damascene structures in an intra-metal dielectric layer; wherein the intra-metal dielectric layer comprises: one or more copper interconnects; one or more inductor loops and one or more vias in an air gap; wherein the air gap is formed by removing portions of the intra-metal dielectric layer between the inductor loops and coupled to an extraction via using a supercritical fluid process; and one or more copper bulkhead structures, wherein the copper bulkhead structure provides a seal to prevent supercritical fluid flow to adjacent portions of the semiconductor structure; an inter-level dielectric layer between the one or more levels of semiconductor structure, wherein the one or more vias extend through the inter-level dielectric layer; and a non-conformal layer over an etch stop layer, wherein the non-conformal layer hermetically seals an opening of the extraction via.