Patent ID: 7078933

Claim:
An integrated circuit, comprising: a first region comprising: a first plurality of cells located along a first dimension and a second dimension, wherein the first plurality of cells comprises a first cell and a second cell, wherein the first region has a first span along the first dimension and a second span along the second dimension; a plurality of switches; and a first plurality of conductors located within the first region spanning cells of the first plurality of cells along the first dimension and the second dimension, wherein each conductor is configured to selectively couple to the inputs and outputs of cells of the first plurality of cells and conductors of the first plurality of conductors through the plurality of switches, wherein the first plurality of conductors in the first region comprises: a first conductor having a first span, a second conductor having a second span, a third conductor having a third span, a fourth conductor having a fourth, a fifth conductor having a fifth span and a sixth conductor having a sixth span; wherein the first span of the first region is greater than the first span of the first conductor along the first dimension, wherein the first span of the first conductor is greater than the second span of the second conductor along the first dimension, and wherein the second span of the second conductor is greater than the third span of the third conductor along the first dimension; wherein the second span of the first region is greater than the fourth span of the fourth conductor along the second dimension, wherein the fourth span of the fourth conductor is greater than the fifth span of the fifth conductor along the second dimension and the fifth span of the fifth conductor is greater than the sixth span of the sixth conductor along the second dimension; and two independently program controlled switches comprising a first switch and a second switch, wherein the first cell of the first plurality of cells is configured to selectively couple to drive the third conductor through at least the first switch and wherein the second cell of the first plurality of cells is configured to selectively couple to drive the third conductor through at least the second switch.