Patent ID: 8703596

Claim:
A method of manufacturing a semiconductor device comprising: forming a gate electrode over a n-type channel region of a silicon substrate; forming a first sidewall insulating film on a side wall of the gate electrode; forming p-type source/drain regions in the silicon substrate on both sides of the gate electrode; forming a first semiconductor layer of a first semiconductor material for applying a first stress in a first direction parallel to a surface of the silicon substrate on the silicon substrate in a region where the silicon substrate is not covered by the gate electrode and the first sidewall insulating film; forming a second sidewall insulating film on the side wall of the gate electrode with the first sidewall insulating film formed on; etching the first semiconductor layer and the silicon substrate with the gate electrode, the first sidewall insulating film and the second sidewall insulating film as the mask to thereby remove the first semiconductor layer in a region where the second sidewall insulating film is not formed and form a trench in the silicon substrate, leaving a portion of the first semiconductor layer under the second sidewall insulating film; and burying in the trench a second semiconductor layer of a second semiconductor material for applying to the silicon substrate a second stress in a second direction opposite to the first direction, wherein a lattice constant of the first semiconductor material is smaller than a lattice constant of silicon, a lattice constant of the second semiconductor material is larger than the lattice constant of silicon, and the n-type channel region is compressed by the first stress and the second stress.