Patent ID: 8415811

Claim:
A semiconductor package assembled with flip chip bonding and sealed with resin, comprising: an IC chip comprising: an element arrangement region; a pad array having at least four pads including a voltage input pad to supply an input voltage and a voltage output pad to which an output voltage is supplied, the voltage input pad and the voltage output pad being disposed at edges of the pad array; a driver transistor disposed between the voltage input pad and the voltage output pad to receive the input voltage from the voltage input pad and output the output voltage to the voltage output pad, the driver transistor being disposed in contact with an edge of the element arrangement region; and at least four leads on which the IC chip is mounted by the flip chip bonding to be formed in a lead array, the leads being disposed corresponding to the pads in the pad array, the leads including a voltage input lead electrically connected to the voltage input pad and a voltage output lead electrically connected to the voltage output pad, the voltage input lead and the voltage output lead being disposed at edges of the lead array.