Patent ID: 8434046

Claim:
A method of fabricating an integrated circuit on a semiconductor chip, the method comprising: designing an architecture of the integrated circuit, the architecture including first and second standard cells configured to implement a same basic function; designing an integrated circuit layout corresponding to the integrated circuit architecture; and fabricating the integrated circuit on the semiconductor chip according to the integrated circuit layout; wherein designing the integrated circuit layout includes: designing a preliminary cell layout for the basic function; creating first and second cell layouts having at least one layout difference from each other; using the first cell layout to implement the first standard cell in the integrated circuit layout; and using the second cell layout to implement the second standard cell in the integrated circuit layout, wherein: creating the first cell layout includes obtaining a first randomly altered cell layout by randomly altering the preliminary cell layout, and using the first randomly altered cell layout to implement the first standard cell; and creating the second cell layout includes obtaining a second randomly altered cell layout by randomly altering the preliminary cell layout, and using the second randomly altered cell layout to implement the second standard cell.