Patent ID: 7685467

Claim:
A method of debugging a pipelined processor comprising: A. processing a simulated event detected by a data processing system to determine a boundary of the simulated event, the processing including determining a set of simulated events using a module in the data processing system and transmitting information concerning the simulated events from the data processing system to the pipelined processor; B. generating in the pipelined processor a matrix having combinations of the simulated event and other events occurring simultaneously in the pipelined processor, the generating including generating, analyzing, and evaluating combinations of simultaneous events that can occur in the pipelined processor; C. capturing output data of observed ones of the simulated event and other events; and D. applying the matrix to generate encoded debug data of the output data, the applying including encoding and serializing the output data and transmitting the output data from the pipelined processor to the data processing system.