Patent ID: 7538699

Claim:
A single ended pseudo differential interconnection circuit comprising: a transmitter configured to transmit n (n≧2) data signals and a compelled signal; and a receiver configured to receive the n data signals and the compelled signal, wherein the receiver includes: a data judgment unit configured to sequentially compare neighboring two signals of a first group of the data signals including half (n/2) of the n data signals and the compelled signal, generate first through (n/2)th detection signals, sequentially compare neighboring two signals of a second group of the data signals including the remaining half of the n data signals, and generate ((n/2)+1)th through nth detection signals, and a decoder configured to receive the compelled signal and the first through (n/2)th detection signals to generate first through (n/2)th decoded signals and receive the compelled signal and the ((n/2)+1)th through nth detection signals to generate ((n/2)+1)th through nth decoded signals.