Patent ID: 8301949

Claim:
A method of operation within an integrated circuit device, the method comprising: receiving a sequence of data packets from an external source; storing data values from each of the data packets in a first memory; updating error descriptor values within a second memory based on error information associated with the sequence of data packets, the error descriptor values each including an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region; generating a sequence of multiple-bit error values based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values; and concurrently with generating at least one multiple-bit error value of the sequence of multiple-bit error values, changing the state of one or more bits of the data values stored in the first memory based on a previously-generated multiple-bit error value of the sequence of multiple-bit error values.