Patent ID: 7884421

Claim:
A semiconductor device comprising: a gate electrode formed over a semiconductor substrate of a first conductivity type with a first insulating film interposed therebetween; a source region and a drain offset region of a second conductivity type formed away and facing each other over a surface of the semiconductor substrate with a channel region interposed therebetween, the channel region being formed immediately below the gate electrode; a drain region of the second conductivity type formed to be included in the drain offset region; and a punch through prevention region of the first conductivity type formed to be in contact with the drain offset region, wherein, in a portion immediately below the gate electrode, peaks of concentration distribution in a depth direction of a first conductivity type impurity and a second conductivity type impurity in the drain offset region are in a same depth, the second conductivity type impurity being higher concentrated than the first conductivity type impurity.