Patent ID: 7569480

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a first mask pattern on a substrate, the first mask pattern having a first opening exposing a first portion of the substrate, the first opening being T-shaped, wherein the first mask pattern includes a lower mask layer pattern and an upper mask layer pattern, the lower mask layer pattern exposes the first portion of the substrate, and the upper mask layer pattern exposes a portion of the lower mask layer pattern; forming an oxidation barrier region in the exposed first portion of the substrate; patterning the first mask pattern to form a second mask pattern having a second opening, the second opening exposing a second portion of the substrate, the second opening being I-shaped, wherein a width of the lower mask layer pattern is the same width as the upper mask layer pattern; and forming a gate insulation layer on the exposed second portion of the substrate, the gate insulation layer having a variable thickness, wherein a width of the second opening substantially has the same width as an upper part of the first opening, and the width of the second opening is wider than a width of a lower part of the first opening.