Patent ID: 8004307

Claim:
An electronic circuit comprising: an input stage coupled to an input node and including a first input circuit and a second input circuit; an intermediate stage including a first intermediate circuit and a second intermediate circuit; an output stage including a first output circuit and a second output circuit each coupled to an output node and configured to drive the output node, when active; and a feedback path, wherein a first node of the feedback path is the output node and wherein a second node of the feedback path is coupled to the intermediate stage; wherein, responsive to a transition from a first logic level to a second logic level of an input signal on the input node, the first input circuit is configured to activate the first intermediate circuit and wherein, responsive thereto, the first intermediate circuit is configured to activate the first output circuit, wherein, the first output circuit is configured to, when activated, drive an output signal on the output node, and wherein, after a delay, the first intermediate and first output circuits are configured to be deactivated responsive to a first feedback signal received by the intermediate stage via the feedback path.