Patent ID: 7687353

Claim:
An ion implantation method for forming a high-voltage device, the method comprising: defining a logic region and a high-voltage region in a semiconductor substrate; forming a first conductive well region in the logic region; forming a second conductive well region in the high-voltage region; forming a first gate insulation layer on the semiconductor substrate in the logic region and a second gate insulation layer on the semiconductor substrate in the high-voltage region, the second gate insulation layer being thicker than the first gate insulation layer; forming a mask pattern which exposes the first conductive well region in the logic region and the second conductive well region in the high-voltage region; simultaneously forming a hollow region in the logic region, and a source region in the high-voltage region, by simultaneously implanting first conductive impurities into the logic region and source region of the semiconductor substrate using the mask pattern as an ion implantation mask; and forming a second conductive impurity layer in the hollow region by implanting second conductive impurities into the logic region and the source region in the high-voltage region using the mask pattern as an ion implantation mask, wherein the second gate insulation layer prevents the implantation of ions in the source regions of the semiconductor substrate.