Patent ID: 7932784

Claim:
A radio frequency (RF) circuit comprising: a first frequency-locked loop (FLL), which during a first FLL operating mode is adapted to: receive a first reference signal having a first reference frequency; provide a first frequency-reduced output signal having a first reduced output frequency, which is approximately equal to a first output frequency divided by a first constant; and provide a first output signal having the first output frequency, which is based on a difference between the first reduced output frequency and the first reference frequency; a first phase-locked loop (PLL), which during a first PLL operating mode is adapted to: receive a second reference signal; and provide the first output signal, which is based on a phase difference between the first output signal and the second reference signal, wherein the first FLL provides coarse tuning of a frequency of the first output signal during the first FLL operating mode and the first PLL provides fine tuning of a frequency of the first output signal during the first PLL operating mode; a first variable frequency oscillator adapted to: receive a first control signal and a second control signal; and provide the first output signal having the first output frequency, which is based on at least one of the first control signal and the second control signal; a first frequency reduction circuit, which during the first FLL operating mode is adapted to: receive the first output signal; and provide the first frequency-reduced output signal; a first frequency detector circuit, which during the first FLL operating mode is adapted to: receive the first frequency-reduced output signal and the first reference signal; and provide a first frequency error signal, which is based on the difference between the first reduced output frequency and the first reference frequency; a first loop filter circuit, which during the first FLL operating mode is adapted to: receive and filter the first frequency error signal to create a first filtered frequency error signal; and provide the first control signal based on the first filtered frequency error signal; and PLL circuitry, which during the first PLL operating mode is adapted to: receive one of the first output signal and the first frequency-reduced output signal, and a second reference signal having a second reference frequency; and provide the second control signal based on the one of the first output signal and the first frequency-reduced output signal, and further based on the second reference signal.