Patent ID: 8842687

Claim:
A network interface module comprising: first and second communication ports; a dedicated bypass communication port configured to bypass the first and second communication ports; and one or more bypass switches configured to operate in first and second configurations, the one or more bypass switches being operative to form the first configuration upon a reception of one or more control signals from a network device and being operative to form the second configuration upon a termination of the one or more control signals received from the network device, the one or more bypass switches being further operative to form a plurality of signal links, wherein one and only one of the plurality of signal links are operable for communication along the entire communication path of the respective one of the plurality of signal links at any particular time, the plurality of signal links comprising: a first signal link that forms a communication path between the first communication port and, a network interface controller and between the network interface controller and the second communication port, the first signal link being operable for communication along the first signal link when the one or more bypass switches are configured in the first configuration, wherein during communication along the first signal link one or more packets are transmitted through the first communication port and are processed by one or more processors upon transmission through the network interface controller before being transmitted out of the second communication port, or, one or more packets are transmitted through the second communication port and are processed by one or more processors upon transmission through the network interface controller before being transmitted out of the first communication port; and a second signal link that forms a direct electrical connection between the first communication port and the bypass communication port, the second signal link being operable for communication along the second signal link when the one or more bypass switches are configured in the second configuration, wherein during communication along the second signal link one or packets are transmitted directly through the first and bypass communication ports bypassing processing by the one or more processors.