Patent ID: 7977163

Claim:
A method of forming an embedded electronic component package comprising: providing a substrate, the substrate having a substrate first surface and a substrate second surface, opposite the substrate first surface; providing a first dielectric layer, the first dielectric layer having a first dielectric layer first surface and a first dielectric layer second surface, opposite the first dielectric layer first surface; applying the first dielectric layer second surface to the substrate first surface; forming a cavity in the first dielectric layer first surface, the cavity having a bottom surface at a predetermined depth below the first dielectric layer first surface; providing an electronic component, the electronic component having an electronic component first surface and an electronic component second surface, opposite the electronic component first surface, a plurality of bond pads being formed on the electronic component; attaching the electronic component second surface to the cavity bottom surface; providing a second dielectric layer, the second dielectric layer having a second dielectric layer first surface and a second dielectric layer second surface, opposite the second dielectric layer first surface; applying the second dielectric layer second surface to the first dielectric layer first surface such that the electronic component first surface is covered by the second dielectric layer; forming via apertures through the second dielectric layer to expose selected bond pads of the plurality of bond pads on the electronic component; filling the via apertures with an electrically conductive material to form electrically conductive vias electrically coupled to the selected bond pads of the plurality of bond pads on the electronic component; inspecting the integrity of the electrically conductive vias; when the electrically conductive vias comprise defective electrically conductive vias, removing the electrically conductive vias; and reapplying the electrically conductive material in the via apertures to reform the electrically conductive vias.