Patent ID: 8008177

Claim:
A method for fabricating a semiconductor device comprising: forming a gate pattern and a source/drain region on a silicon substrate; forming a Ni-based metal layer comprised of a nickel alloy for silicide on the silicon substrate where the gate pattern and the source/drain region are formed; forming an N-rich titanium nitride layer on the Ni-based metal layer comprised of the nickel alloy for silicide; thermally treating the Ni-based metal layer comprised of the nickel alloy for silicide and the N-rich titanium nitride layer to form a nickel silicide layer on each of the gate pattern and the source/drain region; and selectively removing the Ni-based metal layer comprised of the nickel alloy for silicide and the N-rich titanium nitride layer to expose a top portion of the nickel silicide on the gate pattern and the source/drain region, whereby the nickel silicide on the gate pattern is neither shorted nor cut, and lumping of the nickel silicide is prevented, and wherein the Ni-based metal layer comprised of the nickel alloy for silicide is a nickel alloy layer including greater than 0 to about 20% of a material selected from the group consisting essentially of Ta, Zr, Ti, Hf, W, Pt, Pd, V, Nb, or any combination thereof.