Patent ID: 7730374

Claim:
A semiconductor integrated circuit having a checking circuit that can self-check the circuit operation corresponding to the timing relationship between a first input signal and at least one second input signal, comprising: a checking signal output circuit that outputs a first checking signal and a second checking signal synchronously with an input clock signal; a first flip-flop circuit that holds the first checking signal synchronously with a first checking clock signal; a second flip-flop circuit that holds the second checking signal synchronously with a second checking clock signal; a checking signal input circuit that inputs the checking signal held in the first flip-flop circuit instead of the first input signal and the checking signal held in the second flip-flop circuit instead of the second input signal when performing the self-checking; and a timing control circuit that controls the timing relationship between the first checking clock signal and the input clock signal corresponding to a first control signal and the timing relationship between the second checking clock signal and the input clock signal corresponding to a second control signal.