Patent ID: 7537977

Claim:
A thin film transistor (TFT) array panel, comprising: a substrate; a gate wire formed on the substrate and including a gate line, a gate electrode and a gate pad; a gate insulating layer pattern formed on the gate wire and having a contact hole exposing the gate pad; a semiconductor layer pattern formed on the gate insulating layer pattern; an ohmic contact layer pattern formed on the semiconductor layer pattern; a data wire formed on the ohmic contact layer pattern, including a data line, a source electrode, a drain electrode and a data pad; a passivation layer pattern formed on the data wire, having contact holes exposing the gate pad, the data pad and the drain electrode; and a pixel electrode electrically connected to the exposed portion of the drain electrode, wherein the ohmic contact layer pattern includes a portion disposed under the data pad and having a planar shape substantially the same as that of the data pad due to simultaneous etching and wherein the contact hole of the passivation layer, exposing the gate pad coincide with the contact hole of the gate insulating layer due to simultaneous etching.