Patent ID: 7480772

Claim:
A method of data processing in a cache coherent data processing system including at least first and second coherency domains, wherein the first coherency domain includes at least first and second cache memories and the second coherency domain includes at least a third cache memory, said method comprising: in the first cache memory within said first coherency domain of said data processing system, said first cache memory including a data array and a cache directory, holding a memory block in a storage location of the data array associated with both an address tag in the cache directory and a coherency state field in the cache directory, wherein said memory block held in the data array of the first cache memory is concurrently cacheable in both the first and second coherency domains; and setting said coherency state field of the cache directory to a state among a plurality of states that indicates that said memory block is possibly shared with the second cache memory in said first coherency domain and cached only within said first coherency domain.