Patent ID: 8261085

Claim:
A processor adapted to process data blocks of a first computer program, the data blocks having a length in bytes and comprising first data comprising information fields, second data comprising executable instructions and third data usable to verify at least the second data, the information fields of the first data comprising a first information field identifying a format of the data blocks, a second information field identifying a first cryptographic key and a third information field identifying a first cryptographic algorithm usable to verify the at least second data using the first cryptographic key and the third data, the processor comprising a first core having an L 1 instruction cache memory with cache lines having a length in bytes that is same length in bytes as the data blocks, the L 1 instruction cache memory adapted to store a data block of the first computer program in a cache line of the L 1 instruction cache memory, the first core comprising a security component adapted to read information of the data block stored in the cache line and to access inside the processor the first cryptographic key identified in the second information field of the data block and use the first cryptographic key in the execution of the first cryptographic algorithm to calculate fourth data based at least on the second data, and to verify at least the second data if the calculated fourth data is the same as the third data stored in the data block, the first core adapted to execute the executable instructions of a data block stored in the cache line of the L 1 instruction cache memory only upon the security component verifying at least the second data of the data block, the processor further comprising a second core, registers, a logic unit and a set of instructions, the second core being a non-secure core and sharing with the first core the registers, the logic unit and the set of instructions.