Patent ID: 7549091

Claim:
A system for detecting transaction errors in which the system has a plurality of data processing devices that use a common system interconnect bus, comprising: a node controller operably coupled to the system interconnect bus; a plurality of interface agents operably coupled to the node controller to have transactions with a source external to the system; and an address table coupled to the node controller and having a plurality of predetermined virtual addresses that operate as dummy registers, wherein the virtual addresses correspond to predetermined transaction error conditions and wherein an error in a particular transaction through one of the interface agents is identified as having one of the predetermined transaction error conditions in the node controller, in which the error is associated with a corresponding address in the address table and particular transaction is routed to the corresponding address, so that the node controller is operable to flag the error by placement of the corresponding address on the system interconnect bus for detection by the data processing devices, in order to inhibit one or more data processing devices from generating additional error indications when processing the particular transaction with the error and the particular transaction is stored for subsequent debugging.