Patent ID: 8854107

Claim:
An integrator circuit, comprising: a first operational amplifier; a second operational amplifier; a first reset switch; a second reset switch; and a capacitor, wherein inverting input terminals of the first and second operational amplifiers are configured to be connected to a first terminal of the capacitor through a first switch and a second switch, respectively, a second terminal of the capacitor is configured to be connected to a first potential and a second potential through a third switch and a fourth switch, respectively, a first inverting input terminal and a first output terminal of the first operational amplifier are configured to be connected to each other through a first feedback capacitor, a second inverting input terminal and an output terminal of the second operational amplifier are configured to be connected to each other through a second feedback capacitor, non-inverting input terminals of the first and second operational amplifiers are configured to be connected to a third potential, and a voltage difference between the first output terminal and the second output terminal is provided as an output of the integrator circuit, the first inverting input terminal and the first output terminal being configured to be connected to each other through the first reset switch, the second inverting input terminal and the second output terminal being configured to be connected to each other through the second reset switch, and wherein both of the first reset switch and the second reset switch being configured to be in an off-state during an integration cycle, and to be in an on-state during a predetermined period between two integration cycles.