Patent ID: 7982515

Claim:
A latch circuit, comprising: a data input unit to which input data is input, said data input unit comprising: a first data input unit having a first data input unit output; and a second data input unit having a second data input unit output; and a data retention unit comprising: a first node connected to said first data input unit output; a second node connected to said second data input unit output; a third node at which an inverted data of data at said first node appears; and a fourth node at which inverted data of data at said second node appears, wherein said first data input unit and said second data input unit transmit data depending on said input data to said first node and said second node when both of a first clock signal and a second clock signal are at a first level, wherein both of said first clock signal and said second clock signal are driven independently from each other, and wherein said data retention unit holds said data when at least one of said first clock signal and said second clock signal is at a second level that is an inverted level of said first level.