Patent ID: 8407644

Claim:
A data processing system having a processor performing a method for reducing crosstalk in a pre-defined system design, the method comprising the processor executing an enhanced crosstalk reduction utility; the processor identifying, based on a pre-identified system design of a device, one or more of: a first set of one or more interconnect paths as driven traces; and a second set of one or more interconnect paths as receiver traces; and the processor generating an optimal layer configuration for placement of the driven traces and receiver traces within one or more layers of the device, the generating further comprising: identifying, from the driven traces and receiver traces, a primary victim trace that is a victim trace of crosstalk from at least two adjacent traces in a first layer of the pre-identified system design, wherein the primary victim trace is identified based on (1) a central location of an interconnect of the primary victim trace and (2) the primary victim trace having a largest number of adjacent signal traces versus all other traces within the driven traces and receiver traces; determining whether a second trace is placed as one of an intra-layer adjacent trace to the primary victim trace and an inter-layer adjacent trace to the primary victim trace; and placing the primary victim trace according to design specifications and layout feasibility; wherein the optimal layer configuration provides an optimally low level of crosstalk noise to receivers at one end of the primary victim trace of the pre-identified system, wherein the primary victim trace is one of a driven trace and a receiver trace, and wherein the layer configuration substantially avoids an implementation of isolation layers in the device for increasing separation between driver and receiver components of the device.