Patent ID: 8461654

Claim:
A semiconductor device comprising: a semiconductor substrate; a gate stack on the semiconductor substrate, wherein the gate stack comprises: a gate dielectric comprising a planar bottom portion and sidewall portions; and a gate electrode over the planar bottom portion of the gate dielectric and adjoining the sidewall portions of the gate dielectric, wherein a portion of the gate electrode is level with the sidewall portions of the gate dielectric; a gate spacer adjacent a sidewall of the gate stack; a source/drain region adjacent the gate spacer; a source/drain silicide region on the source/drain region, wherein the source/drain silicide region does not contact any portion of the gate spacer; and a secondary gate spacer having at least a portion horizontally between the source/drain silicide region and the gate spacer, wherein the secondary gate spacer has a top edge lower than a top edge of the gate spacer, and wherein the secondary gate spacer has an outer edge vertically misaligned to an inner edge of the source/drain silicide region.