Patent ID: 7139957

Claim:
A method for testing an integrated circuit (IC) component, comprising: a) loading a multi-bit test value into a latch of the component; b) selecting a first pad of the component; c) automatically generating a plurality of different sequences of test values based on the multi-bit test value stored in the latch, without scanning-in further multi-bit values into the latch; and d) driving a signal that is based on the plurality of different sequences of test values into the selected pad and out of the component; e) looping back the driven signal; and f) determining for the selected pad a difference between the plurality of different sequences of test values and a plurality of sequences of looped-back test values that are based on the looped back signal, wherein c)–f) are performed while automatically adjusting one of driver and receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.