Patent ID: 7499513

Claim:
A clocking arrangement, comprising: an integrated circuit including a plurality of serializing data transmitters, each arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit, wherein the at least one of the data transmitters repeatedly transmits a particular one pattern of data, and only the particular one pattern of data, for the clocking of the respective target circuit; wherein the integrated circuit is a programmable logic device (PLD) responsive to a source clock and including a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for the at least one of the serializing data transmitters provides a respective target clock; wherein the integrated circuit includes a phase locked loop (PLL) circuit adapted to generate a synthesized clock from a reference clock, wherein the reference clock is based on the source clock and a transmit clock for the transmitting of the periodic data by the at least one of the data transmitters is based on the synthesized clock; wherein the integrated circuit includes a delay-locked loop (DLL) circuit coupled to the PLL circuit; wherein the DLL circuit is adapted to shift a phase of the source clock to produce the reference clock, and the transmit clock is coupled to the synthesized clock; and wherein the DLL circuit is further adapted to align a phase of a feedback clock, which is based on one of the target clocks, to the phase of the source clock.