Patent ID: 6850444

Claim:
A data input device of a DDR SDRAM comprising: a clock pulse generator for outputting a data-in-strobe signal based on an internal clock in a write mode; a first data buffer an being directly controlled by the data-in-strobe signal from the clock pulse generator and having an output line, which corresponds to a first global input/output line of the DDR SDRAM; and a second data buffer being directly controlled by the data-in-strobe signal from the clock pulse generator and having an output line, of which corresponds to a second global input-output line of the DDR SDRAM; a multiplexer for receiving a first data, a second data, and a multiplexer control signal and determining, based on the multiplexer control signal, whether the first data is to be outputted to the first or second data buffer and whether the second data is to be outputted to the first or second data buffer, wherein if the multiplexer control signal is in a low level and the data-in-strobe signal is high, the first data is directly applied to the first data buffer to be transferred to the first global input/output line, and second data is directly applied to the second data buffer to be transferred to the second global input/output line; and wherein if the multiplexer control signal is in a high level and the data-in-strobe signal is high, the first data is directly applied to the second data buffer to be transferred to the second global input/output line, and the second data is directly applied to the first data buffer to be transferred to the first global input/output line.