Patent ID: 7772899

Claim:
A delay locked loop (DLL), comprising: a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock so as to achieve a delay locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained only during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit, wherein the weight storage unit includes: a delay lock enable signal generator configured to output a delay lock enable signal in response to a first delay lock signal and a second delay lock signal; a weight selection pulse generator configured to generate a weight selection pulse in response to the delay lock enable signal; and a weight selection signal storage configured to store the weight selection signal in response to the weight selection pulse.