Patent ID: 8018754

Claim:
A non-volatile memory circuit, comprising: a plurality of memory cells, each memory cell comprising a ferroelectric capacitor connected in series with an access transistor, said plurality of memory cells being connected between a plurality of respective drive lines and a common bit line; a plurality of word lines connected respectively to control terminals of said access transistors for activating respective ones of said access transistors in response to a selection signal for selecting one of said memory cells; and a differential sense amplifier for reading from and writing to said memory cells, said sense amplifier having a first input connected to said bit line, and a second input connected to receive a reference signal, said sense amplifier having a data input terminal and a data output terminal, said sense amplifier for differentially comparing signals on said first and second input lines for reading a data state from a selected one of said memory cells, and for applying a data state read from said selected memory cell to said data output terminal, and said sense amplifier for driving said bit line connected to said selected memory cell to one of a set of predetermined voltage states corresponding to a data state received at said data input terminal for writing said received data state into the selected one of said memory cells.