Patent ID: 7659751

Claim:
A method for designing a logic circuit, comprising: implementing a first logic function as a first transistor network and a complementary second transistor network connected at a central node, said central node serving as a first logic output, each of said first and said second transistor networks being further connected to a respective root, said first and second transistor networks having equivalent inputs so as to form a complementary logic network; selecting a first intermediate node in said first transistor network; determining a first logical path from said first intermediate node to said central node; implementing a third transistor network having a complementary structure to the transistors in said first determined path, being of the opposite transistor type as said first network, having equivalent inputs relative to the transistors in said first determined path and comprising a second logic output; and placing said third transistor network between said first intermediate node and said root of said first transistor network, thereby to provide a logic circuit design having two logic outputs.