Patent ID: 7327616

Claim:
A non-volatile semiconductor memory device comprising a first bit line connected to a first memory cell; a second bit line connected to a second memory cell, the second bit line being adjacent to said first bit line; a bit line shielding circuit, for providing a predetermined shield potential to said second bit line when said first memory cell connected to said first bit line is sensed and for providing said predetermined shield potential to said first bit line when said second memory cell connected to said second bit line is sensed; a data cache circuit for sequentially providing a first data to said first bit line and a second data to said second bit line; a bit line potential holding circuit for holding said first data provided to said first bit line at the time of programming said first memory cell and said second memory cell; and a program circuit for simultaneously programming said first memory cell and said second memory cell while said bit line potential holding circuit holds said first data provided to said first bit line and while the data cache is providing the second data to said second bit line.