Patent ID: 8650452

Claim:
A non-binary quasi-cyclic (QC) low-density parity-check (LDPC) code decoding device obeying a constraint h′v′+h″v″=hv and having an input that is a log-likelihood ratio vector that has q elements, and every element is represented for numbers using only log.sub.2(q) binary bits, q is a positive integer that greater than 1, a parity-check matrix H is related to a finite field GF(q) and defines the constraint h′v′+h″v″=hv, according to the constraint h′v′+h″v″=hv, defines i.sub.0 and j.sub.0 to control the behavior of a first barrel-shifter, a routing network and a second barrel-shifter, h, h′, h″ are non-zero elements, v, v′, v″ are code symbols that relate to the elements of the finite field GF(q) and are presented by non-binary quasi-cyclic (QC) low-density parity-check (LDPC) codes, and comprising a first barrel-shifter using the constraint h′v′+h″v″=hv to shift q−1 elements of the input by j.sub.0 positions to produce first temporary elements; a routing network connecting to the first barrel-shifter, permuting the first temporary elements to produce second temporary elements if v′ of the constraint is not zero and designating the first temporary elements as the second temporary elements if v′ of the constraint is zero; and a second barrel-shifter connecting to the routing network and using the constraint h′v′+h″v″=hv to shift q−1 elements of the second temporary elements by i.sub.0 positions.