Patent ID: 8576649

Claim:
An integrated circuit, comprising: a sense amplifier coupled to a first bitline and a second bitline of a memory array; wherein the sense amplifier includes: a latch circuit having a first sense amplifier node and a second sense amplifier node respectively coupled to the first bitline and the second bitline; a group select input/output circuit coupled to the first sense amplifier node and the second sense amplifier node; and a read-precharge-reference voltage circuit coupled to the first sense amplifier node and the second sense amplifier node; wherein the read-precharge-reference circuit includes: a first transistor coupled between a first reference voltage and the first sense amplifier node for pass gating, the first transistor gated with a first read signal; and a second transistor coupled between a second reference voltage and the second sense amplifier node for pass gating, the second transistor gated with a second read signal; a first bit voltage select circuit coupled between the first sense amplifier node and the first bitline; a second bit voltage select circuit coupled between the second sense amplifier node and the second bitline; wherein the first bit voltage select circuit includes a third transistor coupled between the first sense amplifier node and the first bitline for pass gating; wherein the first bit voltage select circuit further includes a fourth transistor commonly gated with the third transistor to receive a first select signal, the fourth transistor having a first source/drain node coupled to receive a bit voltage and a second source/drain node coupled to the first bitline; wherein the second bit voltage select circuit includes a fifth transistor coupled between the second sense amplifier node and the second bitline for pass gating; and wherein the second bit voltage select circuit further includes a sixth transistor commonly gated with the fifth transistor to receive a second select signal, the sixth transistor having a first source/drain node coupled to receive the bit voltage and a second source/drain node coupled to the second bitline.