Patent ID: 6870790

Claim:
A synchronous DRAM comprising: a first input terminal which receives an external clock signal; a second input terminal which receives a clock enable signal; a plurality of third input terminals which receive command signals; a fourth input terminal which receives an external power supply voltage; and a voltage limiter circuit which generates an internal power supply voltage lower than said external power supply voltage; and a control circuit which receives said command signals in synchronism with said external clock signal, wherein said DRAM is in a power down mode when said clock enable signal is low, wherein said DRAM is out of said power down mode when said clock enable signal is high, wherein said voltage limiter circuit is not in operation when said DRAM is in said power down mode, wherein said voltage limiter circuit is in operation when said DRAM is out of said power down mode, and wherein said voltage limiter circuit starts operating in synchronism with a rising edge of said clock enable signal.