Patent ID: 7259083

Claim:
A method of forming a local interconnect for a transistor on a semiconductor substrate, the method comprising: providing a semiconductor substrate having formed thereon a transistor with a gate including a top gate contact in a gate region and a plurality of active regions having active contacts associated with a source and a drain of the transistor, the sides of the gate further including spacers; depositing, an etch stop layer over the substrate and the transistor such that it covers at least the top gate contact, the spacers, the source, and the drain of the transistor; forming a dielectric layer over the etch stop layer; anisotropically etching a first cavity in the dielectric layer, the first cavity exposing the etch stop layer inside the first cavity, the first cavity being made in a first region selected from among the gate and active regions; after said etching of the first cavity, filling at least a portion of the first cavity with a protective cavity fill material to cover the exposed etch stop layer; forming a second cavity in the dielectric layer exposing the etch stop layer in a second region selected from among gate and active regions not forming part of the first region; removing the protective cavity fill material from the first cavity to form an expanded cavity that includes the first cavity and the second cavity exposing the etch stop layer in the expanded cavity; removing the etch stop layer in the expanded cavity thereby exposing at least two of the gate contact and the active contacts; and filling the expanded cavity with conductive material to electrically connect the exposed contacts.