Patent ID: 7164698

Claim:
An apparatus for interfacing a high-speed link to a network device, comprising: a receiver module, operating at a first clock rate, for receiving a stream of in-coming data from the high-speed link; a framer module, operating at a second clock rate, for deserializing the stream of in-coming data onto a multi-line bus and extracting data packets from the deserialized data on the multi-line bus, wherein the second clock rate is lower than the first clock rate; a sprayer module to receive the extracted data packets from the framer module and, for each of the extracted data packets, select one of a plurality of processing paths in the network device and transmit the extracted data packet to the selected processing path; a deframer module, operating at the second clock rate, for receiving data packets and processing the data packets into a stream of out-going data for transmission on the high-speed link; a transmitter module, operating at the first clock rate, for transmitting the stream of out-going data onto the high-speed link; and a desprayer module for receiving data packets from the plurality of processing paths and transmitting the received data packets to the deframer module.