Patent ID: 7616518

Claim:
A multi-port memory device, comprising: a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a plurality of banks arranged at upper and lower regions of the multi-port memory device, each bank for coupling to a corresponding one of said ports; first and second global I/O data buses disposed between the banks and the ports, each for independently performing a data transmission between the banks and the ports; and a plurality of bank control units, each of the bank control units allocated to a corresponding one of the banks and controlling the data transmission between the corresponding bank and the ports, wherein each of the bank control units receives a bank selection signal and an input valid data signal from each of the ports and determines whether the input valid data signal belongs to the corresponding bank based on the bank selection signal to transfer the input valid data signal to the corresponding bank, and transfers an output valid data signal outputted from the corresponding bank to a corresponding one of the ports selected based on the bank selection signal.