Patent ID: 8724762

Claim:
A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, the clock regeneration method comprising: performing data/pattern detection on at least one input signal to generate recovered data, wherein the step of performing data/pattern detection on the at least one input signal to generate the recovered data further comprises: detecting logical values represented by the input signal at a plurality of time points, respectively, wherein a length between any two adjacent time points of the plurality of time points is equivalent to a predetermined delay amount; analyzing at least one portion of the logical values, in order to dynamically determine/update a unit bit length, wherein the unit bit length is a multiple that is measured by utilizing the predetermined delay amount as a measurement unit; and converting the logical values into the recovered data according to the unit bit length; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern, where the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data; and performing frequency-locking on the synchronization signal to generate the clock signal.