Patent ID: 8445335

Claim:
A method of forming a pixel structure, comprising: providing a substrate, and defining a first sub-pixel region and a second sub-pixel region on the substrate; forming a first patterned metal layer on the substrate, the first patterned metal layer comprising: a first gate line disposed on a side of the first sub-pixel region and the second sub-pixel region; a second gate line disposed on the other side of the first sub-pixel region and the second sub-pixel region opposite to the first gate line; a first gate electrode disposed in the first sub-pixel region and electrically connected to the first gate line; and a second gate electrode disposed in the second sub-pixel region and electrically connected to the second gate line; forming an gate insulating layer and a semiconductor layer; forming a second patterned metal layer comprising: a first source electrode and a first drain electrode disposed in the first sub-pixel region, wherein the first source electrode, the first drain electrode and the first gate electrode form a first switching element; and a second source electrode and a second drain electrode disposed in the second sub-pixel region, wherein the second source electrode, the second drain electrode and the second gate electrode form a second switching element; forming a dielectric layer; and forming a transparent conductive layer on the dielectric layer, and patterning the transparent conductive layer to from: a first pixel electrode disposed in the first sub-pixel region and electrically connected to the first drain electrode, wherein the second source electrode is electrically connected to the first drain electrode through the first pixel electrode; and a second pixel electrode disposed in the second sub-pixel region and electrically connected to the second drain electrode.