Patent ID: 8575684

Claim:
A nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors comprising: a semiconductor substrate; a plurality of column-shaped semiconductor portions being formed on the semiconductor substrate nearly perpendicular to the semiconductor substrate; a plurality of memory cell transistors, each of the memory cell transistors having a first insulating layer and a first gate electrode, the first insulating layer being formed on a surface of each of the column-shaped semiconductor portions and including a charge storage insulating layer, the first gate electrode being formed on a surface of the first insulating layer; and a select transistor having a second insulating layer and a second gate electrode, the second insulating layer being formed on a surface of each of the column-shaped semiconductor portions and adjacent to the first insulating layer, the second gate electrode being formed on a surface of the second insulating layer, wherein the first gate electrode is provided with a first material selected from impurity-doped silicon materials and metallic conductive materials, and the second gate electrode is provided with a second material selected from the impurity-doped silicon materials and the metallic conductive materials, the second material being different from the first material.