Patent ID: 6956416

Claim:
An electronic device having a clock generation circuit, the clock generation circuit comprising: a) a phase locked loop generating a control signal and having a clock output and an enable input enabling operation of the phase locked loop when a first value is applied to the enable input and disabling the phase locked loop when a second value is applied to the enable input, and; b) a control circuit having an output connected to the enable input, the control circuit comprising: i) a first sub-circuit, receiving the control signal and producing an output indicating the condition of the control signal; ii) a second sub-circuit, coupled to the clock output of the phase locked loop, that detects a pulse and produces an output indicating that a pulse is present during a first interval of time; and iii) a third sub-circuit, having inputs coupled to the first sub-circuit and the second sub-circuit and an enable output, the third sub-circuit, when at least one of the control voltage and the pulse are not detected at the end of the first interval of time, provides an enable input to the phase locked loop with the second value and maintains the enable input with the second value for a second interval of time and thereafter provides the enable input the first value for at least a third interval of time.