Patent ID: 7448132

Claim:
A method of fabricating a multi-layer circuit board, the method comprising: fabricating a plurality of high-speed core layers, each comprising a dielectric core of a first dielectric material with a patterned reference plane on one side and a plurality of patterned high-speed differential trace pairs on the opposite side; fabricating at least one power core layer, comprising a dielectric core of a second dielectric material with a patterned power plane on at least one side, the patterned power plane having a thickness at least equivalent to the thickness of three-ounces-per-square-foot copper; stacking the high-speed core layers and the at least one power core layer together with other layers, including b-stage dielectric layers of the first and second dielectric materials, the stacked layers arranged such that at least two patterned power planes exist, separated by at least one layer of the second dielectric material, each trace-pair side of a high-speed core layer abuts a b-stage layer of the first dielectric material, each power-plane side of a power core layer abuts a b-stage layer of the second dielectric material, a transition from the first dielectric material to the second dielectric material occurs across a reference plane, and where two high-speed core layers are adjacent, the trace-pair side of one high-speed core layer faces the reference plane side of the other high-speed core layer; laminating the stacked layers together; and forming a large plurality of plated thru-holes distributed throughout the circuit board, the plated thru-holes electrically connecting the reference plane layers, the power plane layers remaining electrically isolated from each other and from the reference plane layers, within the circuit board.