Patent ID: 7113119

Claim:
An electronic circuit with a sigma delta analog to digital converter, comprising: an input for receiving an analog input signal; a output for outputting a digital output signal selected from a set of three or more available values; a feedback loop arranged to generate the digital output signal so that a time averaged difference between the analog input signal and an analog feedback signal representative of the digital output signal is minimized; a feedback signal generator for generating signal levels of the feedback signal, each under control of a respective one of the output signal values, the feedback signal generator having a return to zero switch circuit for inserting return to zero levels between the signal levels in the feedback signal, the return to zero switch circuit being suitable to provide the signal level for at least one of the available values, wherein the input has two or more differential input terminals, and the feedback loop has two or more current summing nodes connectable to the differential input terminals, and a digitizing circuit for determining the output signal values from a difference between net currents supplied to the current summing nodes, and wherein the feedback signal generator has two or more resistors each coupled between a respective one of the current summing node and a respective internal node, a switching circuit coupled to the internal nodes, for inverting currents through the resistors depending on the output signal values, the return to zero switch circuit coupling the summing nodes via the internal nodes.