Patent ID: 7539072

Claim:
A semiconductor memory device, comprising: a burn-in adjusting circuit to produce a burn-in mode test signal; a first reference voltage generating circuit to produce a first reference voltage for a burn-in test in response to the burn-in mode test signal; a second reference voltage generating circuit to produce a second reference voltage for a normal mode; a detecting circuit for detecting voltage levels of the first and second reference voltages and outputting a detection signal; and an internal voltage generating circuit for generating an internal voltage in response to the detection signal, wherein the detecting circuit includes a voltage divider for dividing the internal voltage to output a comparison voltage; a comparison unit for comparing the comparison voltage with one of the first and second reference voltages provided through a reference node; a voltage level controlling unit for controlling a voltage level of a driving voltage which is provided for the comparison unit; and an output unit for outputting an internal voltage generating signal in response to an output signal of the comparison unit.