Patent ID: 8451151

Claim:
A successive approximation ADC (SAR ADC) with capacitance mismatch calibration, comprising: a first digital to analog converter (DAC) comprising a first array of capacitors with binary weighted values and at least two first compensating capacitors, wherein the first compensating capacitors are binary scaled; a SAR control logic configured to select a capacitor from the first array of capacitors as a capacitor-under-test and then control the terminal voltages on the terminals of the first array of capacitors and the first compensating capacitors accordingly to generate a first comparison voltage of the first DAC; a second digital to analog converter (DAC) comprising a second array of capacitors with binary weighted values and at least two second compensating capacitors with binary weighted values; wherein, the SAR control logic configured to control the terminal voltages on the terminals of the second array of capacitors and the second compensating capacitors accordingly to generate a second comparison voltage of the second DAC; a comparator, coupled between the first DAC and the SAR control logic, configured to output a comparison result based on the first comparison voltage and the second comparison voltage; and a digital error correction logic coupled to the SAR control logic; wherein, the SAR control logic controls a sequence of comparisons based on the comparison result to output the corresponding digital bits, and the digital error correction logic calculates a calibration value to calibrate the value of the capacitor-under-test according to the digital bits; wherein the SAR control logic resets the first array of capacitors and the first compensating capacitors to a common voltage and controls the capacitor-under-test to couple to a first reference voltage in a sample phase; wherein the SAR control logic controls the terminal voltages on the terminals of the capacitors based on the comparison result in a sequence of comparison phases, so as to control a difference between the first comparison voltage and the second comparison voltage to approximate to “0”; and wherein the second DAC is symmetrically operated with the first DAC in the sample phase and the sequence of comparison phases.