Patent ID: 7580288

Claim:
A memory comprising: an array, the array including a plurality of memory cells, each memory cell of plurality of memory cells including a control gate; decode circuitry including a plurality of outputs coupled to control gates of the memory cells of the plurality of memory cells, an adjustable voltage supply including an output whose voltage is adjustable, the output of the adjustable supply voltage is coupled to the decode circuitry, wherein the decode circuitry is operable to couple the output of the adjustable voltage supply to control gates of the plurality of memory cells, wherein the adjustable voltage supply includes: a first resistor ladder having a first plurality of nodes located along the first resistor ladder; a first multiplexer having a first plurality of inputs and an output, each input of the first plurality of inputs is coupled to a node of the first plurality of nodes of the first resistor ladder, the output of the first multiplexer is coupled to the output of the adjustable voltage supply; a control input, wherein a voltage of each node of the first plurality of nodes is based upon a voltage received at the control input, wherein the voltage received at the control input is adjustable; a second resistor ladder having a second plurality of nodes located along the second resistor ladder; a second multiplexer having a second plurality of inputs, each input of the second plurality of inputs is coupled to a node of the second plurality of nodes, the output of the second multiplexer is coupled to the control input; and a voltage control circuit coupled to a first node of the first plurality of nodes to control the voltage of a first node of the first plurality of nodes, the voltage control circuit having an input coupled to the control input, wherein the voltage control circuit comprises an operational amplifier and a transistor, wherein the input of the voltage control circuit is provided to an input of the operational amplifier, wherein an output of the operational amplifier is provided to a control electrode of the transistor, and wherein a current electrode of the transistor is coupled to the first resistor ladder.