Patent ID: 7388412

Claim:
A clock multiplier comprising: a phase-locked loop (PLL) configured to generate a phase-locked clock signal and an oscillated control voltage in response to an input clock signal; a bias generator configured to generate at least one delay cell bias signal in response to the oscillated control voltage; a counter configured to perform a count operation in response to a first feedback signal to generate an input selection signal; a selection circuit configured to choose one of the input clock signal and a second feedback signal in response to the input selection signal to output the chosen signal as a set signal; a flip-flop configured to generate a delay reference signal in response to the set signal and the first feedback signal; a phase comparator configured to compare the input clock signal with the second feedback signal to generate an error signal; a delay controller configured to generate a delay selection signal for controlling an amount of a delay time, based on the error signal; and a variable delay circuit configured to delay the delay reference signal by a first delay time and by a second delay time to generate the first feedback signal corresponding to the first delay time and the second feedback signal corresponding to the second delay time in response to the delay selection signal, the variable delay circuit being biased by a delay cell bias signal, the second delay time being longer than the first delay time.