Patent ID: 7541643

Claim:
A semiconductor device, comprising: a first semiconductor layer of a first conductivity type; a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type, said first and second semiconductor pillar layers formed alternately on said first semiconductor layer along a direction of a surface of said first semiconductor layer; a first main electrode electrically connected to said first semiconductor layer; a semiconductor base layer of a second conductivity type formed on a surface of said pillar layer; a semiconductor diffusion layer of a first conductivity type formed selectively on a surface of said semiconductor base layer; a second main electrode formed to have a junction with said semiconductor base layer and said semiconductor diffusion layer; and a control electrode formed via an insulating film in an area ranging from said semiconductor diffusion layer to said first semiconductor pillar layer to form a channel between said semiconductor diffusion layer and said first semiconductor pillar layer; wherein said pillar layer is formed not only in a device region but also in an end region outside said device region; and wherein at the same depth position in said device region and said end region, an impurity dose amount Q11 [cm-2] to said first semiconductor pillar layer in said device region, an impurity dose amount Q21 [cm-2] to said second semiconductor pillar layer in said device region, an impurity dose amount Q12 [cm-2] to said first semiconductor pillar layer in said end region, and an impurity dose amount Q22 [cm-2] to said second semiconductor pillar layer in said end region, meet the relationship of Q21/Q11<Q22/Q12.