Patent ID: 7577089

Claim:
An apparatus for use in an ETHERNET switch, comprising: a primary output port and a secondary output port, said primary and secondary output ports operably coupled to an ETHERNET PHY device; a register indicating link status of the primary and secondary output ports; a first queue associated with the primary output port; a second queue associated with the secondary output port; a first plurality of class-of-service queues for buffering packet data received from a plurality of input ports, and a first port scheduler for scheduling transfer of packet data from the first plurality of class-of-service queues to said first queue; a second plurality of class-of-service queues for buffering packet data received from the plurality of input ports, and a second port scheduler for scheduling transfer of packet data from the second plurality of class-of-service queues to said second queue; switch means, coupled between said first and second queues and said primary and secondary output ports, for directing the packet data stored in the first and second queues to one or both primary and secondary output ports; and logic arranged to accept input from the register and operate said switch means to direct the packet data stored in the first queue to the secondary output port when the link status of the primary output port indicates that the link is down.