Patent ID: 8018417

Claim:
A common voltage driving circuit of a liquid crystal display, comprising: a clock signal output unit that includes a first to a sixth transistors M 1 -M 6 and outputs first and second clock signals (VCLK 1 , VCLK 2 ) input from the external system according to a control of at least the gate output voltage of first to third gate output voltages (VGOUT 1 , VGOUT 2 and VGOUT 3 ); an output node voltage controller that comprises a seventh to a thirteenth transistors (M 7 -M 13 ) and a first to a fourth condensers (C 1 -C 4 ) and changes voltages of positive and negative polarity output nodes by the first and second clock signals and first to third gate output voltages (VGOUT 1 , VGOUT 2 and VGOUT 3 ); an initialization voltage supply unit that comprises a fourteenth to a twenty first transistors (M 14 -M 21 ) and supplies an initialization voltage of the output node voltage controller; and a common voltage output unit that comprises a twenty second and a twenty third transistors (M 22 , M 23 ) and a fifth condenser (C 5 ) and prevents the voltages of the positive and negative polarity output nodes from being changed by the fifth condenser (C 5 ) when higher and lower common voltages are alternately output according to the voltages of the positive and negative polarity output nodes.