Patent ID: 8129753

Claim:
An integrated circuit, comprising: a substrate region; a gate electrode level region formed above the substrate region, the gate electrode level region including at least seven linear-shaped conductive structures each formed to extend lengthwise in a first direction, each of the seven linear-shaped conductive structures having a lengthwise centerline, wherein the seven linear-shaped conductive structures are positioned in a side-by-side and spaced apart manner such that a distance as measured in a second direction perpendicular to the first direction between lengthwise centerlines of side-by-side positioned ones of the seven linear-shaped conductive structures is substantially equal to a first pitch, wherein each of the seven linear-shaped conductive structures has a substantially equal length as measured in the first direction, wherein the seven linear-shaped conductive structures include at least two single-transistor-forming linear-shaped conductive structures each having only one gate portion corresponding to a gate electrode of a transistor and each having an extending portion that extends in the first direction away from its one gate portion, and wherein each of the at least two single-transistor-forming linear-shaped conductive structures has a length of its extending portion as measured in the first direction greater than a length of its one gate portion as measured in the first direction.