Patent ID: 8259786

Claim:
A channel smoothing filter having: a controller; a plurality of preamble equalizers; an FFT memory addressed by said controller, said FFT memory providing values X*H as parallel data applied to a unique one of each said preamble equalizers; each said preamble equalizer also coupled to a preamble zero generator and a preamble sign generator, said preamble zero generator causing the output of said preamble equalizer to be zero, said preamble sign generator causing said preamble equalizer output to be either the input value applied to said preamble equalizer input or the two's compliment of the input value applied to said preamble equalizer; a channel smoothing filter having a first filter processor, a second filter processor, and a third filter processor, each said filter processor having a filter engine coupled to each said preamble equalizer output, each said filter engine also accepting a filter coefficient whereby no more than one of each said filter engines in each said filter processor is active, said filter processor output formed by selecting the said no more than one filter engine which is active, said channel smoothing filter also having: a register clocked by a system clock; a summer having an output coupled to said register, said summer having inputs coupled to: said first filter processor through a first shifter; said second filter processor through a second shifter; said third filter processor; said register output; whereby said filter engine coefficients coupled to said first filter processor, said second filter processor, and said third filter processor provide edge filtering coefficients during an edge interval followed by central filtering coefficients during a central interval, followed by edge filtering coefficients during an edge interval; where said controller addresses said FFT memory to cause an even function to be produced.