Patent ID: 7436229

Claim:
A frequency synthesis circuit comprising: a phase locked loop circuit for receiving a reference clock and a feedback clock and for generating an output clock comprising a frequency based on said reference clock and said feedback clock, said phase locked loop circuit comprising a switched capacitor charge pump loop filter circuit, the switched-capacitor charge-pump loop filter circuit comprising a first charge pump, a second charge pump, a first capacitor coupled to the first charge pump, a second capacitor coupled to the second charge pump, a switch selectively coupled to the first capacitor and the second capacitor thereby generating a first charge pump path and a second charge pump path; and an interpolator circuit, coupled in a feedback path to said phase locked loop circuit, the interpolator circuit for receiving said output clock and for generating said feedback clock by introducing a time delay in said output clock that varies over time so as to change said frequency of said output clock, wherein during a reference clock cycle T PEF , the first charge pump path is active and thereby generates a loop integral control voltage V INT , and the second charge pump path is equalizing, wherein said switched capacitor charge pump loop filter circuit minimizes jitter introduced by said interpolator circuit.