Patent ID: 7496878

Claim:
A semiconductor package automatic wiring apparatus which determines an optimum wiring route from each pad to a corresponding one of vias on a semiconductor package having a multi-tier bonding pad structure in which pads to be connected to a semiconductor chip are arranged in multiple rows, said apparatus comprising: a row identifier identifying a row for said each pad as to which row said pad belongs to; a tentative placer mapping a position of said each pad to a position on a matrix table after said each pad has been identified by said row identifier as to which row said pad belongs to; and a determiner reading out said matrix table and determining said optimum wiring route based on said read matrix table, wherein a pad-to-pad space through which said wiring route can pass corresponds to a blank entry between adjacent columns in said matrix table, wherein said tentative placer includes a drawer drawing an extension line on a virtual plane from said each pad identified by said row identifying as to which row said pad belongs to, said extension line extending in a direction in which a wiring line is run from said semiconductor chip to said pad or in a direction in which said pad is oriented, and an evaluator evaluating a positional relationship between the extension line drawn from said pad belonging to a first row and a pad belonging to a second row adjacent to said first row, and wherein said matrix table is generated based on said positional relationship evaluated by said evaluator.