Patent ID: 7966145

Claim:
Integrated circuit comprising: at least one external input configured to receive a predetermined test sequence having a predetermined test signal pattern in a test mode of the integrated circuit, a power supply, a plurality of elementary components, each having at least one internal output that is responsive to the predetermined test sequence, and at least one test unit comprising an AND gate, each input of the AND gate is connected to an internal output of one of said elementary components and an output of the AND gate is connected to said power supply, via a resistor, wherein said internal outputs connected to said inputs of the AND gate are selected so that said AND gate delivers a first logic state if the internal outputs of said elementary components match respective, expected logic states in response to said predetermined test signal pattern being applied to the at least one external input and said AND gate delivers a second, different logic state if at least one of the internal outputs of said elementary components does not match the respective, expected logic state.