Patent ID: 7660150

Claim:
A memory array having a memory cell coupled to a read word line and a write word line of the memory array, the memory cell comprising: a storage element for storing a logical state of the memory cell; a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to an activated high voltage state on the write word line for writing the logical state to the memory cell and configured to disconnect the storage element from the at least first write bit line in a deactivated low voltage state on the write word line; a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array, the read circuit being enabled and configured to read the logic state of the storage element in response to an activated low voltage state on the read word line and disabled and disconnected from the storage element in response to a deactivated high voltage state on the read word line; and wherein the memory array is configured, during a write operation to the storage element, to change the state of the write word line from a deactivated low voltage state to an activated high voltage state and subsequently change the state of the read word line from an activated low voltage state to a deactivated high voltage state to provide a voltage boost from the read word line to the voltage on the write word line caused by the electrical coupling between the read word line and the write word line.