Patent ID: 8497176

Claim:
A method for manufacturing a semiconductor device comprising steps of: (a) forming a mask insulating film pattern on a semiconductor substrate having a memory area and a logic circuit area, said mask insulating film pattern having an opening of an isolation region shape for defining a plurality of active regions; (b) by using said mask insulating film pattern as an etching mask, etching said semiconductor substrate to form an isolation trench for defining said plurality of active regions; (c) depositing an isolation material film burying said isolation trench; (d) subjecting said isolation material film to chemical mechanical polishing to form an isolation region and expose said mask insulating film pattern; (e) after said step (d), forming a resist pattern covering said logic circuit area, etching said isolation region in said memory area to remove a partial thickness of said isolation region in said memory area; (f) after said step (e), removing said mask insulating film pattern; (g) after said step (f), forming a first structure having a first height and extending on an area from the active region in said memory area to a nearby isolation region; (h) after said step (f), forming a second structure having a second height lower than the first height and extending on an area from the active region in said logic circuit area to a nearby isolation region, (i) before said step (g), forming a gate insulating film for a memory cell in said plurality of active regions; (j) removing the gate insulating film for the memory cell in said logic circuit area; (k) forming a gate insulating film for a MOS transistor in said plurality of active regions in said logic circuit area, and (l) by using the resist pattern used in said step (e), implanting ions for threshold voltage control in said memory area.