Patent ID: 7461163

Claim:
A device for measuring system latency regarding packets of information from sources to destinations, comprising: 1) means for generating time-stamps at a location among a plurality of locations of a network, said location between sources and destinations of packets as the packets of information pass through said plurality of locations, said time-stamps distinct from said packets of information, wherein each time-stamp identifies the packet of information passing through the location, including time-stamp information based on a real-time clock set to a universal standard; and 2) means for analyzing at said location the time-stamps generated at the location in order to determine component latency and latency jitter as said packets traverse from sources to destinations; and 3) means for sending the component latency and latency jitter to a central location for further analysis with component latency and latency jitter sent from other locations of said plurality of locations so as to determine a real-time multiple end-to-end latency jitter representing a real-time mesh view of latency and latency jitter regarding the network.