Patent ID: 8497158

Claim:
A method for encapsulating electronic components comprising: providing a leadframe strip having an axis with two component positions arranged along the axis, each component position including a chip support substrate having a drain lead extending from the chip support substrate parallel to the axis and a source lead and a gate lead each extending parallel to the axis; providing a plurality of semiconductor chips, each semiconductor chip having a source electrode, a gate electrode and a drain electrode coupled together by a tie bar; mounting the plurality of semiconductor chips on respective ones of the chip support substrates; electrically connecting the gate electrode with an inner bonding area of the gate lead and the source electrode with an inner bonding area of the source lead by a plurality of bond wires; electrically connecting the drain electrode with the drain lead; encapsulating the semiconductor chips, the bond wires and the inner bonding areas of the source lead and of the gate lead in plastic material to form a component housing in each component position by a transfer mold process; wherein each component position is encapsulated at essentially the same time; and wherein a central portion of a first support bar extending parallel to the axis between the chip support substrates of the two component positions remains outside of the component housings.