Patent ID: 7605075

Claim:
A method of manufacturing a multilayer circuit board which permits mounting of an integrated circuit chip having bump electrodes spaced at a pitch, the method comprising the steps of: a) forming first and second patterned circuit layers, each circuit layer including a plurality of metal patterns, on a top surface and a bottom surface of a first insulating layer, respectively; b) after step (a), forming a second insulating layer on said first circuit layer and a third circuit layer on a surface of the second insulating layer; c) after step (b), forming a first via hole permitting an insertion of one of the bump electrodes of the integrated circuit chip in the first and second insulating layers and a second via hole permitting an insertion of another one of the bump electrodes of the integrated circuit chip in the second insulating layer at the same pitch as for the bump electrodes of the integrated circuit chip; and d) after step (c), forming a first conductive film in contact with a metal pattern of at least one of the first to third circuit layers on an inner surface of the first via hole and a second conductive film in contact with a metal pattern of at least one of the first and third circuit layers on an inner surface of the second via hole.