Patent ID: 7164172

Claim:
A semiconductor device comprising: an SOI substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said SOI layer having a semiconductor surface of a first crystal plane, and a <100> crystal direction of said SOI layer is aligned with a <110> crystal direction of the support substrate; an N-channel MIS transistor including a gate insulating film formed on said semiconductor surface of said SOI layer, a gate electrode extending in a first direction and formed on said gate insulating film, N-type active layers aligned in a second direction which is perpendicular to said first direction and formed at both sides of said gate electrode, and a P-type body layer formed under said gate electrode and between said N-type active layers; a P-type active layer for body voltage application which is formed on said crystal plane of said SOI layer; and a P-type path portion connecting said P-type body layer and said P-type active layer for body voltage application, wherein said first direction is aligned to said <100> crystal direction of said SOI layer.