Patent ID: 8508278

Claim:
A method comprising: inputting a first transition associated with a first clock signal to a first buffer; generating a first pulse at a single output from the first buffer to latch an output signal at a circuit output to a first state; inputting a second transition associated with a second clock signal to a second buffer; generating a second pulse at a single output from the second buffer to latch the output signal at the circuit output to a second state, wherein the output signal and one of the first and second clock signals have the same phase; providing a signal from the first buffer to a first multiplexor; providing a signal from the second buffer to a second multiplexor; and coupling an output of the first multiplexor and an output of the second multiplexor to the circuit output, such that output signal of the circuit output is latched to the first state in response to the first pulse and to the second state in response to the second pulse.