Patent ID: 8704692

Claim:
A D/A converter configured to convert an N-bit (N represents an integer) digital input code into an analog output voltage that corresponds to the digital input code, the D/A converter comprising: an upper-side terminal to which an upper-side reference voltage is applied; a lower-side terminal to which a lower-side reference voltage is applied; an output terminal configured to output the analog output voltage; a center resistor associated with the most significant bit of the digital input code, and configured to have a resistance that is weighted in an essentially binary manner according to the most significant bit; N-1 upper-side resistors that are respectively associated with the upper second bit to the least significant bit of the digital input code, that are configured to have resistances that are respectively weighted in an essentially binary manner according to the corresponding bits, and that are arranged in series between the upper-side terminal and one terminal of the center resistor; N-1 lower-side resistors that are respectively associated with the upper second bit to the least significant bit of the digital input code, that are configured to have resistances that are respectively weighted in an essentially binary manner according to the corresponding bits, and that are arranged in series between the lower-side terminal and the other terminal of the center resistor; an upper-side center switch arranged between the aforementioned one terminal of the center resistor and the output terminal, and configured such that the on/off state thereof is controlled according to the most significant bit; a lower-side center switch arranged between the other terminal of the center resistor and the output terminal, and configured such that the on/off state thereof is controlled according to logical inversion of the most significant bit; N-1 upper-side switches that are respectively associated with the upper second bit to the least significant bit of the digital input code, that are each arranged in parallel with the corresponding upper-side resistor, and that are each configured such that the on/off state thereof is controlled according to the corresponding bit; and N-1 lower-side switches that are respectively associated with the upper second bit to the least significant bit of the digital input code, that are each arranged in parallel with the corresponding lower-side resistor, and that are each configured such that the on/off state thereof is controlled according to logical inversion of the corresponding bit.