Patent ID: 7292464

Claim:
A ferroelectric memory device equipped with a word line, a bit line and a plate line, the ferroelectric memory device comprising: a first n-type MOS transistor having a gate connected to the word line; a ferroelectric capacitor having one end connected through the first n-type MOS transistor to the bit line, and another end connected to the plate line; and a plate line control circuit that drives the plate line, wherein the plate line control circuit includes: an inverter having a first p-type MOS transistor and a second n-type MOS transistor and an output terminal connected to the plate line, a voltage source that supplies a voltage to be supplied to a source of the first p-type MOS transistor, and a third n-type MOS transistor having a drain connected to a drain of the first p-type MOS transistor and a source connected to the output terminal, and applying a voltage smaller than the voltage source and greater than a threshold voltage to the output terminal, wherein the word line is connected to a gate of the third n-type MOS transistor.