Patent ID: 8149611

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of said first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch said variable resistor; a column control circuit operative to, during data read from said memory cell, select a certain at least one of said second lines and charge the selected second line to a certain charged-level; and a row control circuit operative to, during data read from said memory cell, select a certain at least one of said first lines, supply to the selected first line a certain selected first line voltage, and supply to unselected first lines a blocking voltage higher than said charged-level and said selected first line voltage, wherein said column control circuit changes a clamp voltage for limiting said charged-level in response to a temperature.