Patent ID: 7752475

Claim:
An interface chip that interfaces synchronous data that is comprised of two parts, one half from one bit stack (Bitstack 0 ) and the other half from another bit stack (Bitstack 1 ) to a double data rate bus, comprising in combination; a master latch stage having its input connected to said Bitstack 0 and its output directly connected to one input of a multiplexer whose output is coupled to said double data rate bus via an I/O port on the chip; a master-slave L 1 -L 2 latch having its master L 1 stage input connected to said Bitstack 1 and its slave L 2 stage output connected directly to another input of said multiplexer; clock and control logic generating a local clock signal comprised of a CK 1 clock signal of one phase, a CK 2 clock signal of opposite phase, and a multiplexer select signal that selects the output of the master latch connected to Bitstack 0 on one edge of a double data rate select clock signal operating at the local clock signal frequency, and selects the output of the output of the slave L 2 stage connected to Bitstack 1 on the other edge of the double data rate select clock signal; latching the one half from Bitstack 0 in the master latch stage in response to the CK 1 clock signal, also latching the other half from Bitstack 1 in the master L 1 stage in response to the CK 1 clock signal, and latching the other half from Bitstack 1 latched in the master L 1 stage in the slave L 2 stage in response to the CK 2 clock signal; launching the one half from Bitstack 0 on the double data rate bus from the master latch stage on the next edge of the double data rate select clock signal following the CK 1 clock signal and launching the other from the Bitstack 1 on the double data rate bus from the master L 1 stage on the following next edge of the double data rate select clock signal.