Patent ID: 8138023

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: preparing a wafer including a first circuit formation region and a first surrounding region formed to surround said first circuit formation region, the first circuit formation region having a plurality of first through-electrodes and a plurality of first bumps formed respectively on a surface of each first through-electrode of the plurality of first through-electrodes; laminating a first chip on said first circuit formation region in contact with the plurality of first bumps, said first chip having a plane dimension that is substantially the same as a plane dimension of said first circuit formation region; pouring a first underfill comprised of a first resin into a first space between said first circuit formation region and said first chip from said first surrounding region, the first underfill having a first viscosity; hardening said first underfill; forming a laminated structure comprised of a first chip block that includes a second chip including said first circuit formation region, said first chip, and said first underfill by conducting dicing with respect to said wafer, the second chip having a plurality of second through-electrodes and a plurality of second bumps formed respectively on a surface of each second through-electrode of the plurality of second through-electrodes that is opposite that of the plurality of first bumps; laminating said laminated structure on a substrate; pouring a second underfill comprised of a second resin into a second space between said laminated structure and said substrate, the second underfill having a second viscosity that is higher than that of said first underfill; and hardening said second underfill.