Patent ID: 8769190

Claim:
A storage subsystem, comprising: a controller; a solid-state memory management subsystem; and a non-volatile solid-state memory array including a plurality of memory units, each memory unit capable of being independently accessed, the plurality of memory units being subdivided into a plurality of distinct sets, each set comprising one or more, but less than all, of the plurality of memory units; wherein the controller is configured to allocate a first set of the plurality of distinct sets of memory units for operations associated with the solid-state memory management subsystem, and to allocate a second set of the plurality of distinct sets of memory units for operations associated with a host device based at least in part on a ratio of a number of memory units designated for execution of operations associated with the solid-state memory management subsystem to a number of memory units designated for execution of operations associated with the host device, the ratio being based at least in part on a runtime condition comprising a number of free memory units in the non-volatile solid-state memory array, and wherein the controller is further configured to update the ratio in response to determining that the number of free memory units is below a free memory threshold so that additional memory units are allocated to the first set for operations associated with the solid-state memory management subsystem.