Patent ID: 6963894

Claim:
A method of predicting an absence of an underflow condition associated with a result of a floating-point multiply-add operation in a floating-point unit, the floating-point multiply-add operation including a first operand exponent (ea), a second operand exponent (eb), and a third operand exponent (ec), the first operand exponent (ea) having a predefined minimum value (emin), the first operand exponent (ea) being associated with a first significand, the first significand having a first number of significant bits (N 1 ), the result of the floating-point multiply-add operation being associated with a second significand, the second significand having a second number of significant bits (N 2 ), the method comprising: determining if (−2)<=(eb+ec−ea)<=(0); determining if (eb+ec)>=(emin+2*N 1 −2+2*(N 1 −N 2 )); and asserting an output signal indicative of the absence of the underflow condition if (−2)<=(eb+ec−ea)<=(0) and (eb+ec)>=(emin+2*N 1 −2+2*(N 1 −N 2 )).