Patent ID: 8239633

Claim:
An apparatus, comprising: a first core that includes: a processor executing one or more threads, wherein the threads execute one or more memory transactions; a cache associated with the processor that stores data operated on by the memory transactions; and a coherence controller in hardware that computes one or more signatures summarizing read-sets and write sets of the memory transactions performed with respect to the cache, receives a coherence request from a second core different from the first core, and detects a conflict to the data stored in the cache for the coherence request based on the computed signatures, wherein the coherence request does not include any signatures computed by the second core, and wherein the signatures provide false positives but no false negatives for the conflict on the coherence request, wherein the signatures comprise fixed-size representations of a substantially arbitrary set of addresses for the read-sets and the write-sets of the memory transactions, and wherein the processor is associated with the coherence controller.