Patent ID: 8085072

Claim:
A semiconductor integrated circuit comprising: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a DLL clock signal; a locking control block configured to compare a phase of a reference clock signal and a phase of a feedback clock signal, and synchronize the phase of the reference clock signal and the phase of the feedback clock signal in response to the plurality of delay control signals; and a locking detection block configured to detect whether the phase of the reference clock signal and the phase of the feedback clock signal are synchronized and the DLL clock signal is locked, and activate a locking signal when the DLL clock signal is locked, wherein the locking control block is configured to receive the locking signal and provide the reference clock signal, which is obtained by dividing the input clock signal by n (where n is a natural number equal to or greater than 2), as an internal DLL clock signal, when the locking signal is activated.