Patent ID: 8863067

Claim:
A method of designing an integrated circuit (IC), the IC design expressed as a graph comprising a plurality of edges and a plurality of nodes representing a plurality of IC components, each edge connecting two nodes without encompassing a third node, the method comprising: defining a cost function that has a component for each edge that is based on (i) a spatial relationship comprising a difference in horizontal and vertical coordinates of the two nodes of the edge and (ii) a temporal relationship comprising a difference between event times of the two nodes of the edge; optimizing, by a computer, the IC design by changing at least one of an event time and a coordinate of a node and modifying the IC design to satisfy a set of constraints on each component of the cost function such that, for each edge, a difference between the event times of the nodes connected by the edge is not less than a signal propagation delay caused by the spatial relationship between the two nodes connected by the edge; and placing the IC components based on the optimized IC design.