Patent ID: 8595459

Claim:
A synchronous memory device, comprising: first and second bank groups, each comprising at least one storage array; a request interface to receive first and second memory access read commands directed respectively to the first and second bank groups; data path circuitry to output data from the first and second bank groups to at least one shared line of an external signalling path; where a minimum time interval comprising a minimum number of clock cycles must elapse between successive read accesses to an open row of storage cells in a selected one of the storage arrays; where the data path circuitry is to output, for an open first row in a first bank group storage array and a concurrently-open second row in a second bank group storage array and during respective portions of a first time interval, first data from the first bank group storage array, responsive to the first memory access read command, and second data from the second bank group storage array, responsive to the second memory access read command, to the at least one shared line of the external signalling path; and where the first time interval is less than twice the minimum time interval.