Patent ID: 7948093

Claim:
A memory IC package assembly comprising: a memory die having bond pad terminations on a face thereof; a first metal layer having first and second surfaces, the first surface being bonded to the face of the die by a first adhesive layer, the first adhesive layer and the first metal layer configured to cover at least some of the die face and to expose the bond pad terminations; and, a first circuit layer comprising of a plurality of metal circuits disposed on a substrate, each of the plurality of metal circuits having a circuit trace coupling a first point of termination for interconnection to the die and a second point of termination for interconnection to a next level assembly, said first circuit layer being bonded to the second surface of the first metal layer using a second adhesive layer, wherein the first circuit layer and the second adhesive layer are configured to cover areas of the second surface of the first metal layer and to expose the bond pad terminations of the die and the substrate of the circuit layer and further having termination apertures aligned to expose select areas of the first metal layer.