Patent ID: 7307460

Claim:
A phase locked loop (PLL), comprising: a detector coupled to receive a reference signal and a PLL output signal and adapted to provide an error signal indicative of a difference between the reference signal and the PLL output signal; a first charge pump coupled to receive the error signal and adapted to provide a first current signal in response to the error signal; a loop filter coupled to receive the first current signal, the loop filter including, a resistive element having a first conductor coupled to the first charge pump and a second conductor coupled to a common node; a capacitive element having a first conductor coupled to the common node and a second conductor coupled to a reference potential; and a current mirror coupled to the common node and adapted to conduct a first portion of the first current signal in magnitude proportion to a current conducted by the capacitor; and a second charge pump coupled to the common node and coupled to receive the error signal, the second charge pump being adapted to extract a second portion of the first current signal from the loop filter.