Patent ID: 7675118

Claim:
A semiconductor structure comprising: at least one n-type field effect transistor (nFET) located on a surface of a semiconductor structure, said at least one nFET including a material stack comprising a fully silicided gate electrode overlying a gate dielectric, and at least one spacer located on vertical sidewalls of said material stack; a first stress liner located on said semiconductor substrate and partially wrapping around said at least one nFET, said first stress liner having an upper surface that is coplanar with an upper surface of said fully silicided gate electrode of said at least one nFET; wherein the first stress liner is not present atop the fully silicided gate electrode; a second stress liner of an opposite stress type as that of the first stress liner located on said upper surface of said first stress liner and atop the at least one nFET. at least one PFET isolated from said at least one nFET by a trench isolation region, said second stress liner completely surrounds and is present atop a gate electrode of said at least one pFET.