Patent ID: 7379007

Claim:
A parallel analog-to-digital converter comprising: a plurality of comparators for comparing an input signal in parallel to a plurality of reference voltages; an input signal line for distributing the input signal to the plurality of comparators; and a sampling clock distributor for distributing sampling clock for sampling the input signal to the plurality of comparators at a distribution timing determined according to delay of the input signal due to the input signal line comprising: a first clock line for transmitting a first clock signal along a first direction; a second clock signal for transmitting a second clock signal along a second direction opposite from the first direction; and a phase interpolator for receiving the first clock signal transmitted through the first clock line and the second clock signal transmitted through the second clock line and outputting the sampling clock at a timing dividing a time difference between the first clock signal and the second clock signal at a prescribed ratio in accordance with the distribution timing of the sampling clock.