Patent ID: 7522396

Claim:
An ESD protection circuit, comprising: an ESD protection element, coupled to a pad; a transmitting gate circuit, coupled to the pad and an output terminal; a first N MOSFET, coupled to the transmitting gate circuit and a second voltage level, for providing a first biasing voltage to the transmitting gate circuit according to the second voltage level; a first P MOSFET, coupled to the transmitting gate circuit and a first voltage level, for providing a second biasing voltage to the transmitting gate circuit according to the first voltage level; a delay circuit, coupled to the ESD protection element, for determining a turning on and turning off time of the transmitting gate circuit, wherein the delay circuit is not directly connected to the transmitting gate circuit; a first inversing logic circuit, coupled to the delay circuit, the transmitting gate circuit and the N MOSFET, for generating a first control signal according to the output of the delay circuit; and a second inversing logic circuit, coupled to the first inversing logic circuit, the P MOSFET and the transmitting gate circuit, for generating a second control signal according to the output of the first inversing logic circuit, wherein the transmitting gate circuit turns on or turns off according to the first control signal and the second control signal.