Patent ID: 8136072

Claim:
A method of generating a layout of an integrated circuit using a computer, said integrated circuit comprised of a plurality of circuit elements and connections between circuit elements, said circuit elements comprising a variety of standard cells in abutting relationships, each of said variety of standard cells having boundaries, said method comprising the steps of: providing the computer with functional data representing said circuit elements and said connections between said circuit elements of said integrated circuit; providing the computer with a cell library defining said plurality of standard cells, each standard cell representing a potential component for forming said integrated circuit; providing the computer with compatibility information indicative of compatibility of boundaries of each of said variety of standard cells; and generating on the computer a placement of standard cells in dependence on said functional data and said compatibility information so as to produce said layout such that no abutting cells have incompatible boundaries, wherein said incompatible boundaries result from positions of elements of respective standard cells relative to their respective standard cell boundaries, wherein said incompatible boundaries arise from dopant implantation extending beyond a standard cell boundary, wherein said incompatible boundaries arise from a first standard cell having a first dopant implantation extending beyond a first standard cell boundary and a second standard cell having a second dopant implantation extending beyond a second standard cell boundary, and said first dopant implantation and second implantation have different dopant characteristics.