Patent ID: 6946738

Claim:
A semiconductor packaging substrate, comprising: a first, second, third, fourth, fifth, and sixth patterned metal layers sequentially stacked up, wherein the first metal layer bas a plurality of power/ground bump pads, a plurality of first signal bump pads and a plurality of second signal bump pads, and wherein the first signal bump pads surround the power/ground bump pads and are surrounded by the second signal bump pads, and wherein the sixth metal layer has a plurality of ball pads; a plurality of inner insulation layers, located between the second and third metal layers, between the third and fourth metal layers, and between the fourth and fifth metal layers; at least one contact via formed through the insulation layers and the second, the third, the fourth, and the fifth metal layers, such that at least two of the second, the third, the fourth, and the fifth metal layers are electrically connected to one another; a first external insulation layer and a second external insulation layer arranged between the first and second metal layers and between the fifth and the sixth metal layers, respectively, and at least one first via formed through the first external insulation layer and at least one second via formed through the second external insulation layer, thereby the first metal layer being electrically connected to the second metal layer through the first via, and the sixth metal layer being electrically connected to the fifth metal layer through the second via; wherein the first signal bump pads are routed to the sixth metal layer and then fanned out to the corresponding ball pads, the second signal bump pads are fanned out on the first metal layer and then routed to the corresponding ball pads, and the power/ground bump pads are routed to the third and fourth metal layers and then fanned out to the corresponding ball pads.