Patent ID: 8472273

Claim:
A semiconductor device comprising: a plurality of memory cells; a pair of bit lines coupled to ones of said memory cells; a sense amplifier circuit coupled to said pair of bit lines, said sense amplifier including: a first transistor including a first control electrode coupled to one of bit lines of said pair of bit lines, a second transistor including a second control electrode coupled to the other of said bit lines of said pair of bit lines, a third transistor coupled in series to said first transistor, said third transistor including a third control electrode, and a fourth transistor coupled in series to said second transistor, said fourth transistor including a fourth control electrode, and a control circuit supplying a control voltage in common to said third and said fourth control electrodes of said third and fourth transistors of said sense amplifier; wherein the control circuit, during a first period of time when said sense amplifier circuit amplifies a difference of potential levels between said bit lines of said pair of bit lines, controls said control voltage so that said third and fourth transistors provide a first current supply ability, and during a second period of time when said sense amplifier holds an amplified difference of potential levels between said bit lines of said pair of bit lines, controls said control voltage so that said third and fourth transistors are rendered conductive and provide a second current supply ability that is different from said first current supply ability.