Patent ID: 7447984

Claim:
An apparatus, comprising: a metric generator that is operable to: receive a sequence of discrete valued modulation symbols; calculate a plurality of symbol metrics for each m+n bit symbol of the sequence of discrete valued modulation symbols; based on each possible value of n bits of the m+n bit symbol, pair a corresponding value of m bits having a highest likelihood indicating correspondence to that particular value of n bits; de-interleave the m+n bit symbol thereby generating a first bit stream corresponding to n bits of the m+n bit symbol; and compute a LLR (Log-Likelihood Ratio) for each bit of the first bit stream corresponding to the n bits of the m+n bit symbol, corresponding to an LDPC (Low Density Parity Check) code or a turbo code by which the m+n bit symbol was originally encoded, thereby generating soft information corresponding to the n bits of the m+n bit symbol; a FIFO (First-In First-Out) buffer that is operable to queue the pairings of each possible value of n bits with its corresponding value of m bits having the highest likelihood; either an LDPC decoder or a turbo decoder that is operable to decode the soft information corresponding to the n bits of the m+n bit symbol according to either the LDPC code or the turbo code thereby generating an LDPC or turbo decoded bit stream; an interleaver that is operable to interleave the LDPC or turbo decoded bit stream thereby generating an n-bit symbol sequence; an m-bit un-pairing functional block that is operable to select an m-bit symbol sequence corresponding to the m+n bit symbol based the n-bit symbol sequence; a de-interleaver that is operable to de-interleave the m-bit symbol sequence thereby generating a second bit stream; and a RS (Reed-Solomon) decoder that is operable to decode the second bit stream thereby generating a RS decoded bit stream.