Patent ID: 7663401

Claim:
A programmable logic device comprising: a plurality of multiplexers, with each of the multiplexers having fuse input terminals and input signal terminals; a plurality of fuses associated with the plurality of multiplexers and adapted to provide fuse signals to the fuse input terminals to control selection of the input signal terminals; wherein the fuses in a first state select a first input signal terminal of the input signal terminals; an address shift register adapted to provide wordlines to the plurality of fuses; and a data shift register adapted to provide bitlines to the plurality of fuses, wherein, with the fuses in the first state, a first multiplexer from the plurality of multiplexers is adapted to receive a first logic level signal at the first input signal terminal and provide the first logic level signal to the first input signal terminal of a first set of the plurality of multiplexers, and the fuses are disposed relative to the address shift register such that the fuses associated with the first set of multiplexers are programmed before the fuses associated with the first multiplexer.