Patent ID: 7141882

Claim:
A semiconductor wafer device comprising: a semiconductor wafer having a circuit area disposed in a central area of said semiconductor wafer and a peripheral area of said semiconductor wafer not formed with circuits; a number of semiconductor elements formed in the circuit area; a multi-layer wiring structure formed in the circuit area and having multi-layer wirings connected to said semiconductor elements and interlevel insulating films, at least some of the multi-layer wirings being damascene wirings including wiring patterns and via conductors embedded in the interlevel insulating films; and a multi-layer structure formed in the peripheral area, having insulating films made of same materials as the interlevel insulating films and conductor patterns made of same materials as the wiring patterns, and not having conductor patterns corresponding to the via conductors, wherein at least one of the interlevel insulating films and at least one of the insulating films corresponding to at least one layer of the multi-layer wirings each includes a first etching stopper layer, a first insulating layer, a second insulating layer and a third insulating layer, the wiring patterns and the conductor patterns are disposed in grooves formed through the third and second insulating layers, and the via conductors are disposed in holes formed through the first insulating layer and the first etching stopper layer.