Patent ID: 6847246

Claim:
An apparatus for an integrated circuit, comprising: delay elements serially coupled to provide a delay line, the delay elements configured to receive a digital input signal to be progressively delayed; each of the delay elements including logic components serially coupled; each delay element of the delay elements having a first logic component of the logic components having at least two inputs, the first logic component configured to gate the at least two inputs; a first input of the at least two inputs coupled for receiving one of a progressively delayed version of the digital input signal and a progressively delayed inverted version of the digital input signal, the first input of the at least two inputs coupled in series with a second logic component of the logic components; a first portion of the delay elements having a second input of the at least two inputs of the first logic component coupled for receiving a reference voltage; a second portion of the delay elements having the second input of the at least two inputs of the logic component coupled for receiving a control signal; and the delay elements of the second portion of the delay elements spaced apart by being coupled through at least one of the delay elements of the first portion of the delay elements.