Patent ID: 7185239

Claim:
An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits, comprising: a programmable delay circuit having a signal input that receives a first input signal and an output that provides a delayed signal that is a delayed version of said first input signal, the output of said programmable delay circuit being connected to a first input of a circuit under test during timing parameter characterization; a timing analyzer having a first input connected to the output of the programmable delay circuit during skew measurement; a second input connected to receive a second input signal during the skew measurement, the second input signal being connected to a second input of said circuit under test during the timing parameter characterization; a first output connected to a first control input of said programmable delay generator for controlling a delay value of the programmable delay generator; and a second output providing a result of the skew measurement and/or timing parameter characterization; a chip delay element characterization circuit for determining chip specific delay values having one output connected to a second control input of said programmable delay generator and receiving an output from said programmable delay generator for providing a value corresponding to a measured chip specific delay element timing, said characterization circuit being enabled by a control signal from said analyzer during a setup phase.