Patent ID: 7705463

Claim:
An apparatus for reducing a parasitic capacitance in an integrated circuit, comprising: a substrate, upon which the integrated circuit is disposed, having a first capacitance between a first portion of the substrate and an element of the integrated circuit; and a diode, including a first portion and a second portion, the second portion of the diode being in electrical contact with the first portion of the substrate, configured to bias the first portion of the substrate to a voltage different than a voltage of a second portion of the substrate to induce a second capacitance between the first portion of the substrate and the second portion of the substrate, wherein the first portion of the substrate and the first portion of the diode each comprise a concentration of dopants of a first type, and wherein the second portion of the substrate and the second portion of the diode each comprise a concentration of dopants of a second type, the dopants of the second type being different from the dopants of the first type.