Patent ID: 7567094

Claim:
A driver circuit for generating an output drive signal (SIG) associated with a bandwidth-limited load, where the driver circuit is configured to reduce the presence of intersymbol interference and comprises: a first MOS device, responsive to a first control signal, for providing a drive input signal (D) at a first logic level to the bandwidth-limited load during a transition from a first data value to a second data value; a second MOS device, of opposite conductivity type and responsive to a second control signal, for providing a drive input signal (D) at a second, opposite logic level to the bandwidth-limited load during a transition from the second data value to the first data value, the first and second MOS devices coupled together to provide the drive input signal to the bandwidth-limited load to generate the output drive signal (SIG); and a tri-state device, responsive to an input data signal and providing the first and second control signals to the first and second MOS devices, respectively, and configured to turn OFF the first and second MOS devices after the transmission of a pair of like-valued data bits, allowing the output drive signal (SIG) to thereafter transition to one of the first and second logic levels and reduce intersymbol interference during the transition.