Patent ID: 7920422

Claim:
A method for erasing non-volatile storage, the method comprising: applying one or more erase pulses to a group of non-volatile storage elements, the group of non-volatile storage elements are associated with a plurality of bit lines, the group of non-volatile storage elements are associated with a plurality of word lines; applying one or more non-negative compare voltages to at least a portion of the plurality of word lines after applying the one or more erase pulses; allowing strong conduction currents of the plurality of bit lines to contribute to source line bias; sensing conditions of the bit lines, the sensing is performed while applying the one or more compare voltages and allowing the strong conduction currents to contribute to source line bias; determining whether the group of non-volatile storage elements are sufficiently erased to a negative threshold voltage based on the conditions; and applying at least one additional erase pulse to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased.