Patent ID: 8860138

Claim:
A complementary metal oxide semiconductor (CMOS) device, comprising: a first patterned gate structure formed over an extremely thin silicon-on-insulator (ETSOI) semiconductor substrate corresponding to a first polarity type transistor region, and a second patterned gate structure formed over the ETSOI semiconductor substrate corresponding to a second polarity type transistor region, the ETSOI semiconductor substrate having a thickness on the order of about 10 nanometers (nm) or less; a first vertical sidewall spacer formed adjacent the first patterned gate structure; a first type raised source/drain (RSD) structure formed atop the ETSOI semiconductor substrate and adjacent the first vertical sidewall spacer of the first patterned gate structure, wherein the first type RSD structure has a vertical sidewall profile so as to abut the first vertical sidewall spacer of the first patterned gate structure and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the first patterned gate structure; a second vertical sidewall spacer formed adjacent the second patterned gate structure; and a second type raised source/drain (RSD) structure formed over the ETSOI semiconductor substrate and adjacent the vertical sidewall spacer of the second patterned gate structure, wherein the second type RSD structure has a vertical sidewall profile so as to abut the second vertical sidewall spacer of the second patterned gate structure and produce the other of a compressive and a tensile strain on a channel region of the semiconductor substrate below the second patterned gate structure.