Patent ID: 7518915

Claim:
A nonvolatile semiconductor storage device comprising a plurality of juxtaposed NAND strings, each of said plurality of NAND strings comprising: a memory cell block obtained by connecting current paths of a plurality of nonvolatile memory cells in series, each of said plurality of nonvolatile memory cells comprising a floating gate electrode formed on a first insulating film on a device area isolated by an isolation insulating film which forms an isolation in a semiconductor substrate, and a control gate electrode formed on a second insulating film on the floating gate electrode to cover side surfaces and an upper surface of the floating gate electrode; a first selection gate transistor comprising a first gate electrode in which a first electrode layer made of the same electrode material as the floating gate electrode and a second electrode layer made of the same electrode material as the control gate electrode are formed in direct contact with each other through a first hole formed in a portion of a third insulating film made of the same insulating material as the second insulating film, a current path of the first selection gate transistor comprising one end connected to one end of current paths of series-connected nonvolatile memory cells in the memory cell block, and the other end connected to a data transfer line via a data transfer line contact; and a second selection gate transistor comprising a second gate electrode in which a third electrode layer made of the same electrode material as the floating gate electrode and a fourth electrode layer made of the same electrode material as the control gate electrode are formed in direct contact with each other through a second hole formed in a portion of a fourth insulating film made of the same insulating material as the second insulating film, a current path of the second selection gate transistor comprising one end connected to the other end of the current paths of the series-connected nonvolatile memory cells in the memory cell block, and the other end connected to a source line via a source line contact, wherein an upper surface of the isolation insulating film between the data transfer line contacts included in adjacent NAND strings is higher than a major surface of the semiconductor substrate in a device area between the other end of the current path of the first selection gate transistor and the data transfer line contact, or an upper surface of the isolation insulating film between the source line contacts included in adjacent NAND strings is higher than a major surface of the semiconductor substrate in a device area between the other end of the current path of the second selection gate transistor and the source line contact.