Patent ID: 7773435

Claim:
A semiconductor memory device comprising: a command buffer configured to receive an external command and to output a first command signal; a clock buffer configured to receive an external clock signal and to output a first internal clock signal; a delay measurement and initialization unit configured to receive the first internal clock signal and a fourth internal clock signal and to output a second internal clock signal and a plurality of delayed signals corresponding to a delay time between when the external clock signal is input and data is output; a delay locked loop configured to receive the second internal clock signal and to output a third internal clock signal and the fourth internal clock signal; a latency signal generation unit configured to delay the first command signal by a delay time between when the second internal clock signal is input to the delay locked loop and when the third internal clock signal is output from the delay locked loop, and to output the delayed first command signal as a latency signal, in response to the second and third internal clock signals and the delayed signals; and a data output buffer configured to output the data in response to the latency signal and the third internal clock signal.