Patent ID: 7409031

Claim:
A clock and data recovery device for generating data samples in response to data having jitter, said device including: sampling circuitry coupled and configured to receive the data and to employ 2× oversampling using a data sampling clock and an edge sampling clock to generate the data samples; clock generation circuitry configured to generate the data sampling clock in response to at least one control signal and to assert the data sampling clock to the sampling circuitry, wherein the phase of said data sampling clock is determined by the control signal; phase detection circuitry configured to generate feedback indicative of the amount of the jitter and of phase error between the data sampling clock and the data; and clock control circuitry, coupled and configured to generate the control signal in response to the feedback and to assert the control signal to the clock generation circuitry, wherein the control signal is at least substantially independent of the amount of the jitter over each time interval over which φ av is nonzero, where φ av is an average of instantaneous values of the phase error between the data sampling clock and the data over the time interval, wherein the clock generation circuitry is configured to generate a second clock whose phase is fixed relative to the data sampling clock in response to said at least one control signal and to generate the edge sampling clock by applying variable delay to the second clock such that the edge sampling clock has a varying phase that defines a dead zone having a dead zone width, and wherein the feedback includes a jitter signal indicative of the amount of the jitter, the clock control circuitry includes a dead zone width control circuit configured to generate the jitter signal, and the clock generation circuitry is configured to adjust the dead zone width in response to the jitter signal.