Patent ID: 6960529

Claim:
A method for fabricating a multiple-layered semiconductor interconnect device in which one metal layer is connected to another metal layer using one or more vias having metal interconnect sidewall protection against unlanded vias, the protection provided using a single barrier metal or compound without requiring Chemical Vapor Deposition (CVD) processes, the method comprising the following: an act of forming a metal interconnect component; an act of depositing a single barrier metal or compound directly on at least a portion of the metal interconnect component including at least a portion of a sidewall of the metal interconnect component using a Physical Vapor Deposition (PVD) process; an act of forming a dielectric layer over the metal interconnect component and the single barrier metal or compound layer such that the dielectric layer is in direct contact with the single barrier metal or compound; an act of etching an unlanded via through the dielectric layer to the metal interconnect component so that the single barrier metal or compound that covers at least a portion of the sidewall of the metal interconnect component is exposed at the sidewall of the metal interconnect component; and an act of filling the unlanded via with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.