Patent ID: 7642807

Claim:
A compensated buffer circuit operative in at least a first mode and a second mode, the buffer circuit comprising: a plurality of output blocks, respective outputs of the output blocks being connected together and forming an output of the buffer circuit, the output blocks being arranged in a sequence and being binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block; and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks and selectively enabling the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating an output drive strength of the buffer circuit as a function of variations in at least one of process, voltage and temperature (PVT) conditions to which the buffer circuit may be subjected, the respective control signals supplied to the predrivers collectively representing a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.