Patent ID: 7772890

Claim:
A dynamic logic device, the device comprising: a logic circuit, wherein the logic circuit includes: an inverting output buffer; a logic function, wherein an input of the logic function is electrically coupled to a logic input, wherein an output of the logic function is electrically coupled to an input of the inverting output buffer, and wherein the logic function exhibits a leakage current; and a bias transistor, wherein the gate of the bias transistor is electrically coupled to an output of the inverting buffer, and wherein a first leg of the bias transistor is electrically coupled to the input of the inverting buffer; and a current circuit, wherein the current circuit supplies a current to a second leg of the bias transistor, wherein the current circuit includes: a transistor stack, wherein the transistor stack includes at least one off-state transistor exhibiting the current corresponding to the leakage current; and a current mirror, wherein the current mirror is configured to cause the current corresponding to the leakage current to be provided to the second leg of the bias transistor, wherein the current mirror includes a first P-channel device, a second P-channel device and an operational amplifier; and wherein the source of the first P-channel device and the source of the second P-channel device are electrically coupled to a supply, wherein the drain of the first P-channel device is electrically coupled to the at least one off-state transistor and to a first input of the operational amplifier, wherein the gate of the first P-channel device and the gate of the second P-channel device are electrically coupled to each other and to the output of the operational amplifier, and wherein the drain of the second P-channel device is electrically coupled to the second leg of the bias transistor.