Patent ID: 7074718

Claim:
A method of fabricating a semiconductor device, comprising: forming a bit line interlayer insulating layer over a semiconductor substrate; forming two bit line patterns adjacent to and in parallel with each other on the bit line interlayer insulating layer, each of the two bit line patterns including a bit line and a bit line capping layer pattern stacked in sequence; forming a buried contact interlayer insulating layer over a surface of the semiconductor substrate having the two bit line patterns; forming a first contact hole in a predetermined region of the buried contact interlayer insulating layer and the bit line interlayer insulating layer between the two bit line patterns; etching the buried contact interlayer insulating layer and the bit line interlayer insulating layer through the first contact hole to form a second contact hole that exposes at least one side wall of the two adjacent bit line patterns; etching the buried contact interlayer insulating layer and the bit line interlayer insulating layer through the second contact hole to form a third contact hole that removes one side portion of the bit line interlayer insulating layer below the two adjacent bit line patterns; forming a contact hole spacer on the side wall of the third contact hole; and forming a contact hole plug that fills the third contact hole and is surrounded by the contact hole spacer.