Patent ID: 7107501

Claim:
A test device, comprising: an interface for connecting to a memory circuit to be tested and for receiving fault addresses; a fault address memory having memory cells for storing the fault addresses; and a control unit connected between said interface and said fault address memory, said control unit allocating and storing the fault addresses at an address in said fault address memory, a first sequence of said memory cells in said fault address memory can be addressed with a first access time, and a second sequence of said memory cells can be addressed with a second access time, the second access time being longer than the first access time, first fault addresses of the fault addresses can be received at a first data rate, and second fault addresses of the fault addresses can be received at a second data rate, through said interface, with the second data rate being lower than the first data rate, said control unit storing the first fault addresses in said fault address memory on a basis of said first sequence of said memory cells, and storing the second fault addresses in said fault address memory on a basis of said second sequence of said memory cells.