Patent ID: 8560932

Claim:
A digital system, the digital system having a digital input vector, the digital system comprising: a first terminal for receiving the digital input vector; a digital processing unit coupled to the first input terminal, the digital processing unit processing the digital input vector, the digital processing unit comprising a Module under Test, the Module under Test having a second input terminal coupled to the first input terminal and having a second output terminal, the Module under Test being responsive to the digital input vector by (a) providing a responsive digital vector in response to the digital input vector; an Actual Parity Generator having a third input terminal coupled to the second output terminal and having a third output terminal, the Actual Parity Generator providing, at the third output terminal, an actual parity signal representing the parity of the responsive digital vector; a State Parity Generator having a sixth input terminal coupled to the first input terminal and having a sixth output terminal, the State Parity Generator arranged to provide (a) responsive to the digital input vector causing the Module under Test to enter at least one used state, a representative parity signal representative of the parity of an errorless digital vector predetermined for at least one used state of the Module under Test and (b) responsive to the digital input vector causing the Module under Test to enter at least one unused state, a selected signal characterizing the unused state; and a comparator having a seventh output terminal, having a fourth input terminal coupled to the third output terminal for receiving the actual parity signal and having a fifth input terminal coupled to a sixth output terminal for receiving the representative parity signal, the comparator realizing a digital comparison between the actual parity signal and the representative parity signal and providing a comparator output signal at the seventh output, the comparator output signal terminal being a function of the realized digital comparison and the selected signal and indicative of a potential error associated with the Module under Test.