Patent ID: 7271416

Claim:
A semiconductor structure, comprising: a substrate having a first in-plane unstrained lattice constant; a first layer comprising a first semiconductor material on the substrate and having a second in-plane unstrained lattice constant that is different from the first in-plane unstrained lattice constant; and a variable mismatch layer comprising a second semiconductor material disposed between the substrate and the first layer, the variable mismatch layer being configured to reduce stress in the first layer to below a level of stress resulting from growth of the first layer directly on the substrate; wherein the variable mismatch layer is grown on the substrate and comprises a second layer disposed adjacent the substrate, where the second semiconductor material has a third in-plane unstrained lattice constant that is mismatched with the first in-plane unstrained lattice constant and the second layer being strained with an in-plane strained lattice constant that is substantially matched to the second in-plane unstrained lattice constant of the first layer; wherein the variable mismatch layer further comprises a third layer comprising a third semiconductor material disposed between the second layer and the first layer that transitions from the strained in-plane lattice constant of the second layer to the second in-plane unstrained lattice constant of the first layer; wherein the third semiconductor material comprises a graded semiconductor material that transitions from the second semiconductor material to the first semiconductor material.