Patent ID: 8116134

Claim:
A semiconductor memory device comprising: a plurality of memory cells which store k bits of data (k is a natural number not less than 2) into a single cell; a number n (n is a natural number not less than 2) of data storage circuits which store externally supplied k bits of data temporarily to write data into the memory cells; and a control circuit which selects the k bits of data bit by bit as a first page, a second page, . . . , a k-th page and which, when inputting first data, externally inputs the data on the first page, second page, . . . , the k-th page to h1 (h1≦n) of the data storage circuits, when inputting second data, externally inputs the data on the first page, second page, . . . , the k-th page to h2 (h2≦n ) of the data storage circuits, and when inputting i-th data, externally inputs the data on the first page, second page, . . . , the k-th page to hi (hi≦n ) of the data storage circuits, and which stores data into the memory cells on the basis of the k bits of data stored in the n data storage circuits.