Patent ID: 7506325

Claim:
A computer implemented method comprising: identifying one or more prolonged instructions in a process; dividing the process into a plurality of threads based upon the number of identified prolonged instructions; inserting, by a compiler, conditional branching logic after each of the identified prolonged instructions in each of the plurality of threads, wherein a first of the plurality of threads is programmed to conditionally branch to a second of the plurality of threads and wherein a last of the plurality of threads is programmed to conditionally branch back to the first thread; and executing the plurality of threads after the insertion of the conditional branching logic, wherein the executing comprises: storing a “return to” address in a hardware register for each of the threads, the “return to” address being an address to resume execution of the thread; mapping a logical “return to” register for each of the threads to the hardware register corresponding to each of the respective threads used to store the respective threads' “return to” address; mapping a logical “branch to” register for each of the threads to the hardware register that corresponds to another of the plurality of threads so that each of the threads' logical “branch to” registers points to a different thread from the plurality of threads; branching from a first of the plurality of threads to a second of the plurality of threads using the “return to” address corresponding to the second thread, wherein the branching is to the logical “branch to” address of the first thread and to the logical “return to” address of the second thread, wherein the logical “branch to” address of the first thread and the logical “return to” address of the second thread are the same address.