Patent ID: 8441854

Claim:
A nonvolatile memory apparatus comprising: a page buffer; an even bit line coupled to the page buffer; an odd bit line connected to the page buffer; an even memory cell string coupled on the even bit line; an odd memory cell string coupled on the odd bit line; and a bit line select unit including a first path section coupled between the even bit line and the even memory cell string, and a second path section coupled between the odd bit line and the odd memory cell string, wherein the first path section and the second path section include a MOS transistor and a flash transistor coupled in series to the MOS transistor, respectively, and wherein the MOS transistor of the first path section is turned on in response to a signal of an even drain select line, and the flash transistor of the first path section is turned on in response to the signal of the even drain select line or a signal of an odd drain select line.