Patent ID: 8415222

Claim:
A method for manufacturing a semiconductor device, comprising: 101 . providing a substrate; 102 . forming a gate stack on the substrate, then forming a metal silicide on the gate stack and the substrate, and controlling a schottky barrier after forming the metal silicide; 103 . forming an inter layer dielectric (ILD) to cover the device; 104 . etching the ILD at both sides of the gate stack and the substrate below the ILD, so as to form a groove of source and drain regions respectively; 105 . depositing a metal diffusion barrier layer in the groove; and 106 . filling the groove with a metal to form the source and drain regions; wherein step 102 further comprises: forming an interface layer on the substrate; depositing a high k gate dielectric layer on the interface layer; depositing a metal gate electrode layer on the high k gate dielectric layer; and depositing one of a polycrystalline silicon layer and an amorphous silicon cap layer on the metal gate electrode layer; wherein the method further comprises, after step 102 : forming a metal silicide on the gate stack and the substrate; and controlling a schottky barrier after forming the metal silicide; wherein the step of controlling the schottky barrier comprises: sputtering a layer of metal on the metal silicide on the substrate; diffusing the metal into the metal silicide through annealing, and separating the metal on an interface between the metal silicide and the semiconductor substrate, so as to decrease the schottky barrier.