Patent ID: 8542162

Claim:
A shift register unit, comprising: an input module which inputs a first clock signal, a second clock signal, a frame start signal, a high voltage signal, and a low voltage signal, wherein the first clock signal is identical with the phase-inverted signal of the second clock signal within time interval of one frame; a processing module comprising a plurality of thin film transistors and connected to the input module, which generates a gate drive signal according to the first clock signal, the second clock signal, and the frame start signal, and controls to configure a positive feedback of voltage changes between a first node and a second node formed by the plurality of thin film transistors to cut off a transient direct current path formed by the input terminal of the high voltage signal, the input terminal of the low voltage signal, and at least one thin film transistor in time; and an output module connected with the processing module, which sends the gate drive signal generated by the processing module.