Patent ID: 7268028

Claim:
A semiconductor fabrication method, comprising: providing a semiconductor structure which includes: (a) a semiconductor substrate, and (b) a patterned hard mask layer on top of the semiconductor substrate; etching the semiconductor substrate using the patterned hard mask layer as a mask, resulting in a well isolation trench, a first shallow trench, and a second shallow trench; after said etching the semiconductor substrate is performed, covering the first and second shallow trenches without covering the well isolation trench; after said covering the first and second shallow trenches is performed, etching the semiconductor substrate through the well isolation trench, resulting in the well isolation trench becoming deeper such that when going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function after said etching the semiconductor substrate through the well isolation trench is performed, uncovering the first and second shallow trenches so as to expose the first and second shallow trenches to a surrounding ambient; and then filling the first and second shallow trenches and the well isolation trench with a dielectric material so as to form a first shallow trench isolation (STI) region, a second STI region and a well isolation region in the first and second shallow trenches and the well isolation trench, respectively.