Patent ID: 7630247

Claim:
A nonvolatile semiconductor memory device, comprising: a plate line; a latch circuit including a first inverter and a second inverter cross-coupled to each other, the first inverter including a first MIS transistor of a first conduction type and a second MIS transistor of a second conduction type connected in series, the second inverter including a third MIS transistor of the first conduction type and a fourth MIS transistor of the second conduction type connected in series, a source node of the second MIS transistor and a source node of the fourth MIS transistor being both coupled to the plate line; and a control circuit configured to apply a first potential to the plate line in a store mode to cause a change in threshold voltage to one of the second MIS transistor and the fourth MIS transistor, whichever is selected in response to data latched in the latch circuit, and configured to apply a second potential to the plate line in a power-on mode to cause the latch circuit to latch data responsive to the change in threshold voltage generated in the store mode, such that the data latched by the latch circuit in the power-on mode is automatically output from an output terminal to outside the nonvolatile semiconductor memory device upon power-on thereof.