Patent ID: 7277349

Claim:
A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; an antifuse bank coupled to the address decoder, the antifuse bank having a plurality of antifuses; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a circuit coupled to an antifuse of the antifuse bank for sensing a programmed or un-programmed state of the antifuse in response to an input pulse, the circuit comprising: an initialization circuit having an input node at which the input pulse is applied and further having an output node, the initialization circuit configured to couple the output node to an initialization voltage and decouple the output node from the initialization voltage in response to the input pulse; a current sensing circuit coupled to the initialization circuit and having a sense node to which the antifuse is coupled and further having an output node, the current sensing circuit configured to generate a reference current and, in response to decoupling the output node of the initialization circuit from the initialization voltage, compare a current at the sense node relative to the reference current, the current sensing circuit further configured to couple the output node to a first voltage level in response to the current being greater than the reference current and couple the output node to a second voltage level in response to the current being less than the reference current; and an output circuit having an input coupled to the output node of the current sensing circuit and having an output, the output circuit configured to generate an output signal having a logic level indicative of the programmed or un-programmed state of the antifuse according to the voltage level of the output node.