Patent ID: 8339883

Claim:
A semiconductor memory device comprising: a bitline sensing amp configured to detect and amplify data of a pair of bitlines, the data of the pair of bitlines being memory cell data transmitted to the pair of bitlines; a column selecting unit configured to transmit the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal; a dataline precharging unit configured to precharge the pair of local datalines to a precharging voltage level in response to a precharging signal; and a dataline sensing amp configured to detect and amplify data of the pair of local datalines, wherein the dataline sensing amp includes: a charge sync unit configured to discharge charges of the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and the data of the pair of local datalines; and a data sensing unit configured to transmit data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.