Patent ID: 8817932

Claim:
A receiver comprising: a data input to receive a data input signal; a first sampler coupled to the data input to sample the input signal and produce a first sequence of data samples; a second sampler coupled to the data input to sample the input signal and produce a second sequence of data samples; a clock recovery circuit coupled to the data input, the first sampler, and the second sampler, the clock recovery circuit to provide a recovered clock signal to at least one of the first sampler and the second sampler; a multiplexer having a first multiplexer input coupled to the first sampler to receive the first sequence of data samples, a second multiplexer input coupled to the second sampler to receive the second sequence of data samples, and a multiplexer output to convey a selected one of the first and second sequences of data samples as a selected sequence of data samples; and a shift register coupled to the multiplexer output to convert the selected sequence of data samples into parallel data.