Patent ID: 8438523

Claim:
An integrated circuit manufacturing method including: a layout design step of creating a mask pattern for integrated circuit manufacturing; and a manufacturing step of manufacturing an integrated circuit on a semiconductor material using the mask pattern, wherein the layout design step includes: a first step of determining placement of a functional block; a second step of determining placement of a plurality of IO (Input-Output) terminals for connecting the integrated circuit to an external device; a third step of determining placement of one or more IO blocks each to be connected to any of the plurality of IO terminals, according to the placement of the plurality of IO terminals determined in the second step; and a fourth step of determining placement of one or more buses each connecting a different one of the IO blocks to the functional block, and determining (i) a number of timing adjustment circuits to be inserted into each of the buses according to a wiring length of the bus and (ii) placement of the determined number of timing adjustment circuits, the timing adjustment circuits each adjusting timing of signals flowing through the bus, and at least one of the first step, the second step, the third step and the fourth step is performed by a design device.