Patent ID: 8891314

Claim:
A semiconductor memory device, comprising: a memory cell array including cell strings, each including word lines stacked on a substrate and a vertical channel layer formed to penetrate the word lines, wherein two or more of the cell strings are connected to a single bit line through a selection transistor; a peripheral circuit for programming a selected memory cell; and a control circuit for controlling the peripheral circuit to perform a multi-stepwise boosting process at channels of unselected cell strings to be not programmed during a program operation, wherein the multi-stepwise boosting process includes: a primary boosting process, including boosting channels of the unselected cell strings by applying a pass voltage to the word lines when drain selection transistors of the unselected cell strings are turned off, and a secondary boosting process, including boosting the channels of the unselected cell strings by using a gate induced drain leakage (GIDL) phenomenon occurring between the turned-off drain selection transistors and the bit line when a first voltage is applied to the bit line.