Patent ID: 8908719

Claim:
A clock rate control method, comprising: detecting a usage of a first-input-first-output (FIFO) buffer in an electronic device; determining whether the usage falls within a first specific interval, wherein the first specific interval has a first upper limit value and a first lower limit value; when the usage is larger than the first upper limit value, increasing a clock rate of an internal device of the electronic device; when the usage is less than the first lower limit value, decreasing the clock rate; when the usage falls within the first specific interval, calculating a deviation value between a current differential value and a previous differential value, and determining whether the deviation value falls within a second specific interval, wherein the differential value is a difference between a write pointer and a read pointer of the FIFO buffer, and the second specific interval has a second upper limit value and a second lower limit value; when the deviation value is larger than the second upper limit value, increasing the clock rate; when the deviation value is less than the second lower limit value, decreasing the clock rate; and when the deviation value falls within the second specific interval, maintaining the clock rate.