Patent ID: 7446607

Claim:
A regulated cascode circuit comprising: a first PMOS FET and a second PMOS FET connected in series between an output terminal and a first terminal configured to receive a first supply voltage; a first NMOS FET and a second NMOS FET connected in series between the output terminal and a second terminal configured to receive a second supply voltage; and a regulation circuit configured to: output a first control signal to a gate of the second PMOS FET that is based on a voltage of a drain of the second PMOS FET, wherein the first control signal is configured to stabilize the voltage at the drain of the first PMOS FET; and output a second control signal to a gate of the first NMOS FET that is based on a voltage of a source of the first NMOS FET, wherein the second control signal is configured to stabilize the voltage at the source of the first NMOS FET.