Patent ID: 8537953

Claim:
A time-interleaved clock data recovery circuit, the circuit comprising: a time-interleaved sampler/phase-detector circuit for receiving an input signal and a plurality of clock signals, sampling the input signal according to the plurality of clock signals to detect different data transition points of the input signal, and thereby outputting N-bit data and a plurality of phase signals, wherein N is an integer greater than 1; a control circuit, coupled to the time-interleaved sampler/phase-detector circuit, for receiving the plurality of phase signals and converting the plurality of phase signals into a control signal; and a controlled oscillator, coupled to the control circuit, for generating the plurality of clock signals under the control of the control signal, wherein the controlled oscillator comprises a digitally-controlled oscillator circuit comprises: a digitally controlled biasing circuit for receiving the control signal and generating a plurality of biasing signals in response to the control signal; and a plurality of delay cells for receiving the biasing signals and adjusting the clock signals.