Patent ID: 7197730

Claim:
A method of designing an integrated circuit (IC) including performing an electro-migration (EM) check, said method being performed in a computer aided design (CAD) tool, said designing including a plurality of stages including a placement stage, a routing stage and a verification stage in that sequence, said method comprising: receiving as input a set of cells, a desired connectivity between pairs of said set of cells, wherein said desired connectivity defines a set of paths, with each path connecting a corresponding pair of cells; receiving in a first stage a set of load limits respectively corresponding to said set of paths as a performance constraint, wherein each load limit indicates a corresponding maximum limit at which EM violation is avoided, wherein said first stage is at a stage prior to said verification stage; and performing design in said first stage while meeting said performance constraint, whereby electro-migration check is performed for said IC in said first stage prior to said verification stage.