Patent ID: 8443321

Claim:
A method to analyze simultaneous switching noise (SSN) with a circuit design tool, the method comprising: determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design, the determined physically impossible combinations being culled out of a list of possible victim-aggressor combinations; analyzing switching window SSN of the circuit design via simulation with an uncertainty removal algorithm and the list of possible victim-aggressor combinations, the analyzing comprising: preprocessing aggressor pins to create exclusion sets, wherein each exclusion set contains aggressor pins compatible with each other and having a same exclusive relationship with pins outside of the exclusion set, wherein the same exclusive relationships include a same intergroup exclusion constraints and same activity exclusion constraints; creating profile waveforms by sweeping simulation waveforms across switching windows for the aggressor pins in the exclusion sets; determining maximum voltage noise induced on I/O pins of the circuit design, using the profile waveforms; and displaying the determined maximum voltage noise, wherein at least one method operation is executed by a processor.