Patent ID: 7453103

Claim:
A semiconductor construction, comprising: a semiconductor substrate comprising a conductively-doped semiconductive material; a trenched isolation region within the conductively-doped semiconductive material, the trenched isolation region having a sidewall; a bitline between the sidewall of the trenched isolation region and the conductively-doped semiconductive material; a dielectric material over the bitline and trenched isolation region; a wordline over the dielectric material; a vertically-extending pillar proximate the wordline and comprising a channel region vertically between a pair of source/drain regions, the wordline comprising a transistor gate which gatedly connects the source/drain regions to one another through the channel region, one of the source/drain regions being electrically connected to the bitline; and wherein the vertically-extending pillar comprising the channel and the pair of the source/drain regions is spaced apart from and is not directly over the bitline.