Patent ID: 7712001

Claim:
A macro circuit, comprising: a first combinational circuit receiving a first input data to output a first operation result in a normal mode; a first memory element coupled to said first combinational circuit in said normal mode to latch said first operation result and to output said latched first operation result as a second input data; a second combinational circuit coupled to said first memory element in said normal mode to receive said second input data from said first memory element, and to output a second operation result based on said received second input data in said normal mode; a second memory element coupled to said second combinational circuit in said normal mode to latch said second operation result and to output said latched second operation result as a third input data; a third combinational circuit coupled to said second memory element in said normal mode to receive said third input data from said second memory element, and to output a third operation result based on said received third input data in said normal mode; a third memory element coupled to said third combinational circuit in said normal mode to latch said third operation result, and to output said latched third operation result as a fourth input data; a fourth combinational circuit coupled to said third memory element in said normal mode to receive said fourth input data from said third memory element in said normal mode; and a scan chain including said first, second, and third memory elements to perform a test of said first, second, third, and fourth combinational circuits in a test mode, wherein said third memory element latches a test pattern for said test through said scan chain to provide said latched test pattern to both said fourth combinational circuit and said first combinational circuit in said test mode.