Patent ID: 7529329

Claim:
A method for controlling a sampling edge position in a clock and data recovery (CDR) circuit, the CDR having a phase offset control circuit for adjusting the sampling edge position, the CDR receiving a high speed data signal, the method comprising: (a) generating one or more error signals from the received high speed data signal, comprising: (i) sampling the high speed data signal with each of an advanced, current and delayed clock signal to generate advanced, current and delayed sampled data signals; (ii) comparing the advanced and delayed sampled data signals with the current sampled data signal to generate respective advanced and delayed error signals; (b) prior to processing the error signals, recording in a memory the occurrence of the first of each of the advanced and delayed error signals during a selected time interval; (c) processing the generated advanced and delayed error signals to generate a phase offset control signal to adjust the sampling edge position in the CDR; and wherein the step (c) comprises: (iii) setting a selected time interval (T.out) to a predetermined time interval; (iv) clearing the memory and waiting for the selected time interval to expire; (v) if the advanced and delayed error signals are not equal, adjusting the sampling edge position by a fraction of the clock period; and (vi) if the advanced and delayed error signals are equal, changing the selected time interval to another longer predetermined time interval, and repeating the steps (iv) to (vi) until the selected time interval reaches its maximum value (Tmax).