Patent ID: 7430134

Claim:
A memory cell comprising: first and second inverters having input terminals respectively connected to output terminals of the other inverters, a first write transfer gate having one of source and drain terminals connected to a first common connection node of the output terminal of the first inverter and the input terminal of the second inverter and a gate terminal connected to a word line, a second write transfer gate having one of source and drain terminals connected to a second common connection node of the output terminal of the second inverter and the input terminal of the first inverter and a gate terminal connected to the word line, a first write buffer transistor having one of source and drain terminals connected to the other one of the source and drain terminals of the first write transfer gate, the other one of the source and drain terminals connected to a reference potential node and a gate terminal connected to a first bit line, a second write buffer transistor having one of source and drain terminals connected to the other one of the source and drain terminals of the second write transfer gate, the other one of the source and drain terminals connected to the reference potential node and a gate terminal connected to a second bit line, a read transfer gate having one of source and drain terminals connected to a third bit line and a gate terminal connected to the word line, and a read driver transistor having one of source and drain terminals connected to the other one of the source and drain terminals of the read transfer gate, the other one of the source and drain terminals connected to the reference potential node and a gate terminal connected to the first common connection node.