Patent ID: 7546497

Claim:
A semiconductor memory device, comprising: a memory cell array for writing and reading data; a clock signal generating means for receiving an external clock signal applied from an external portion to generate first and second clock signals having the same phase and frequency as the external clock signal during a normal operation including a normal read operation and a normal write operation and to generate the first clock signal having the same phase and frequency as the external clock signal and the second clock signal having the same phase as and a higher frequency than the external clock signal during a test operation including a test read operation and a test write operation; a data write means for receiving a first predetermined-bit serial input data applied at a first data rate and converting the first predetermined-bit serial input data into a first predetermined-bit parallel input data in response to the first clock signal during the normal write operation and for receiving and converting a second predetermined-bit serial input data having a second predetermined-bit number that is smaller than a first predetermined-bit number of the first predetermined-bit serial input data into a second predetermined-bit parallel input data, and extending the second predetermined-bit parallel input data to the first predetermined-bit number to generate the first predetermined-bit parallel input data in response to the second clock signal during the test write operation, and for outputting the first predetermined-bit parallel input data to the memory cell array in response to the first clock signal during the normal write operation and the test write operation; and a data read means for generating a first predetermined-bit parallel output data outputted from the memory cell array in response to the first clock signal during the normal read operation and the test read operations, converting the first predetermined-bit parallel output data into serial output data and outputting the serial output data at the first data rate in response to the second clock signal during the normal read operation, and converting the predetermined-bit parallel output data into serial data and outputting the serial output data at a second data rate in response to the second clock signal during the test read operation.