Patent ID: 8125489

Claim:
A processing unit coupled to a frame buffer and configured to read data from and write data to the frame buffer, the processing unit comprising: a processing pipeline having multiple sections, the multiple sections including at least a first section and a second section; a first cache coupled to the input and the output of the processing pipeline, wherein results for transactions having completed processing through the processing pipeline are stored in and retrieved from the first cache; a second cache coupled to the input and the output of the first section; and a third cache coupled to the input and the output of the second section, wherein first data generated by a first transaction upon completion of processing in the first section is written to the second cache and is transmitted from the output of the first section to the input of the second section, wherein second data generated by the first transaction upon completion of processing in the second section is written to the frame buffer, the first cache, and the third cache, wherein a second transaction requiring the first data for processing and subsequently entering the first section receives the first data from the second cache if the first data is available in the second cache, receives the first data from the first cache if the first data is not available in the second cache and is available in the first cache, and receives the first data from the frame buffer if the first data is not available in either the second cache or the first cache, and wherein the second transaction requiring the second data for processing and subsequently entering the second section receives the second data from the third cache if the data is available in the third cache, receives the data from the first cache if the data is not available in the third cache and is available in the first cache, and receives the data from the frame buffer if the data is not available in either the third cache or the first cache.