Patent ID: 7095117

Claim:
A semiconductor device comprising: a package substrate having a multilayer structure; a semiconductor chip mounted on a main surface of said package substrate; wherein said semiconductor chip includes, an internal circuit; an I/O circuit interacting a signal between said internal circuit and an external device; a first voltage supply electrode which supplies a first operating voltage to said internal circuit; and a second voltage supply electrode which supplies a second operating voltage, being different from said first operating voltage, to said I/O circuit, and wherein said package substrate includes, a first electrode provided on said main surface of said package substrate and being electrically coupled to said first voltage supply electrode of said semiconductor chip; a second electrode provided on said main surface of said package substrate and being electrically coupled to said second voltage supply electrode of semiconductor chip; a first wiring plane being formed of a wiring layer which is different from said first and second electrodes and being electrically coupled to said first electrode via a through hole; a second wiring plane being formed of the same wiring layer as that of said first wiring plane and being electrically coupled to said second electrode via a through hole; a third wiring plane being formed of a wiring layer which is different from both said first and second wiring planes and each of said first and second electrodes, said third wiring plane commonly supplying a reference potential to said internal circuit and said I/O circuit of said semiconductor chip: third electrodes provided on said back surface opposing to said main surface of said package substrate; and said third electrodes being used as external terminals of said package substrate, wherein said first wiring plane and said second wiring plane are separated from each other in a plane view.