Patent ID: 6970030

Claim:
A circuit comprising: a first signal generation circuit for generating a first output signal having a frequency which is proportional to that of a first input signal, said first signal generation circuit comprising a first phase locked loop (PLL) circuit for generating a first intermediate signal having a frequency which is proportional to the first input signal frequency; and a second phase locked loop circuit for generating the first output signal having a frequency which is proportional to the first intermediate signal frequency; wherein, for a given first input signal frequency and a given first output signal frequency, the first intermediate signal frequency is selectable from a first plurality of available frequencies; a second signal generation circuit for generating a second output signal having a frequency which is proportional to that of a second input signal, said second signal generation circuit comprising a third phase locked loop circuit for generating a second intermediate signal having a frequency which is proportional to the second input signal frequency; and a fourth phase locked loop circuit for generating the second output signal having a frequency which is proportional to the second intermediate signal frequency; wherein the first input signal frequency is substantially identical to the second input signal frequency; and wherein the first and second signal generation circuits are configured so that the first output signal frequency is substantially identical to the second output signal frequency, but also configured so that the first intermediate signal frequency is different than the second intermediate signal frequency.