Patent ID: 8008959

Claim:
A flip-flop circuit operated by a first clock signal whose amplitude is smaller than that of input data, the circuit comprising: a pair of transistors which receive the input data and reversed input data thereof, respectively, to latch the input data; an activation circuit which activates said pair of transistors in a conduction state; and a control circuit which receives the first clock signal and sets said activation circuit to a conduction state for a predetermined time period starting from an edge timing of the received first clock signal, wherein said control circuit increases the amplitude of the first clock signal and sets said activation circuit in a conduction state by using a second clock signal which is the first clock signal with the increased amplitude, and said control circuit includes: an inverter including a first P-channel transistor and a first N-channel transistor, which are cascade-connected to each other, that are provided between a first fixed potential corresponding to a high-level-side potential of the second clock signal and a second fixed potential corresponding to a low-level-side potential thereof; and a second P-channel transistor having a source terminal connected directly or indirectly to the first fixed potential, a gate terminal receiving an output of the inverter, and a drain terminal supplying voltage to a gate terminal of the first P-channel transistor.