Patent ID: 8630107

Claim:
An electronic memory, comprising: a first chip enable input pad; a second chip enable input pad that is isolated from the first chip enable input pad; and circuitry coupled to the first chip enable input pad and the second chip enable input pad, the circuitry comprising: a first latch that is cleared before the electronic memory is ready for operation and is set if the first chip enable input pad is driven to a predetermined logic level by an external source after the electronic memory is ready for operation; a first weak driver to hold the first chip enable input pad at an inverse of the predetermined logic level if the first latch is clear; a second latch that is cleared before the electronic memory is ready for operation and is set if the second chip enable input pad is driven to the predetermined logic level by the external source after the electronic memory is ready for operation; a second weak driver to hold the second chip enable input pad at the inverse of the predetermined logic level if the second latch is clear; and logic to enable the electronic memory for access only if one input pad is at the inverse of the predetermined logic level and the other input pad is active, wherein the circuitry is configured to determine whether the electronic memory is enabled for access based on an input voltage level asserted on the first chip enable input pad by an external source if the second chip enable input pad is not connected externally.