Patent ID: 8637982

Claim:
A method for fabricating a semiconductor device, comprising: providing a pattern in an area of a layered semiconductor material, the area extends in a first direction and in a second direction, transverse to the first direction, the area comprises a central area, a left-side lateral area on a left side of the central area, and a right-side lateral area on a right side of the central area, portions of the pattern in the left-side and right-side lateral areas comprise lines which extend uninterrupted through the left-side and right-side lateral areas, respectively, in the first direction, the central area comprises four quadrants relative to a reference point, a portion of the pattern in each quadrant comprises a loop, each loop comprises a closed end in the central area, and a portion of the pattern in the central area comprises a cross which extends uninterrupted through the central area, between the loops, the cross is symmetric with respect to a first axis which passes through the reference point and which is in the first direction, and with respect to a second axis which passes through the reference point and which is in the second direction; and masking the pattern to provide a masked pattern, the masked pattern defines a cut out area, the cut out area is contained within the central area and extends from the reference point outward to overlap the closed ends in the quadrants and to overlap portions of the cross which are between the reference point and the closed ends; and using the masked pattern, providing a patterned metal wiring layer in the layered semiconductor material, the cut out area defines an area in which the metal wiring layer is excluded.