Patent ID: 8631483

Claim:
A packet processor for incoming communications packets comprising: extractor circuitry operable to extract packet data from a packet; and processing circuitry operable to fetch and then execute an instruction one at a time from a set of micro-coded instructions, the instruction execution for performing an arithmetic/logic operation on the packet data from the extractor circuitry to supply a packet drop signal, and the instruction comprising: one or more operands, wherein each operand of the one or more operands is selected from a source comprising the instruction or the packet data, wherein executing the instruction comprises selectively masking one or more of the one or more operands with a mask that is generated from information provided in the instruction; at least one conditional limit field in response to which the processing circuitry is operable for controlling a rate of allowable receipt of a specific type of packet without dropping packets of the specific type; and at least one conditional jump field providing a condition in response to which the processing circuitry is operable for, if the condition is true, causing the processing circuitry to next fetch and then execute an instruction out of sequence relative to an immediately-preceding fetched and executed instruction in the set of micro-coded instructions.