Patent ID: 7308618

Claim:
An interleaver, comprising: a first and a second random access memories for storing data; an addressing device linked to respective address inputs of the first and second memories, the addressing device transmitting, at each instant of a clock linked to the addressing device, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory, the addressing device furthermore transmitting, at each instant, a first address of a first sequence of addresses to the first memory and a second address of a second sequence of addresses to the second memory, the addressing device constructing the first and second sequence of addresses transmitted to each memory from a single successively traversed ranking of the addresses of said memories which is selected from two different rankings of addresses that are interleaved with respect to each other, each of the two different rankings being traversed in combination with a read access cue and a write access cue before the other ranking is traversed.