Patent ID: 7620795

Claim:
A microcontroller comprising: a microprocessor having internal storage units and bussing for accessing the internal storage units; the internal storage units including an instruction cache unit and a data cache unit, the instruction cache unit in part for storing code loaded during configuration of the microprocessor, the code for operating the microprocessor as a microcontroller; a first portion of the bussing having hardwired input for configuration of an instruction-side of the microprocessor, the first portion having first tie-offs for providing the hardwired input thereto; a second portion of the bussing having hardwired input for configuration of a data-side of the microprocessor, the second portion having second tie-offs for providing the hardwired input thereto; and a third portion of the bussing hardwired for providing operation codes, the third portion having third tie-offs for providing the hardwired input thereto, the operation codes at least in part for reactivating the instruction cache after a reset of the microprocessor without having to reload the code stored therein; the first tie-offs, the second tie-offs, and the third tie-offs having respective portions connected either to a reference voltage bus for inputting logic highs or a ground bus for inputting logic lows; the first tie-offs being for the instruction cache unit for setting an instruction-side speed ratio control between the microprocessor and a first external memory, for identifying a beginning addressable location for the instruction cache unit, and for locating an instruction-side memory read data bus port of the microprocessor; the second tie-offs being for the data cache unit for setting a data-side speed ratio control between the microprocessor and a second external memory, for identifying a beginning addressable location for the data cache unit, and for locating a data-side memory read data bus port of the microprocessor.