Patent ID: 8700961

Claim:
A controller comprising: one or more interfaces through which to communicate with a plurality of multi-chip memory packages, wherein each multi-chip memory package comprises a plurality of memory dies, and wherein each memory die has a respective plurality of memory blocks, some of which are good blocks and some of which are bad blocks; and a processor in communication with the one or more interfaces, wherein the processor is configured to: determine a number of good blocks in each memory die in each of the multi-chip memory packages; based on the determined number of good blocks in each memory die, select a memory die from each of the multi-chip memory packages to access in parallel, wherein the selected memory dies are not necessarily all in the same relative position in each multi-chip package; and create a metablock from a set of good blocks from each of the selected memory dies, wherein a maximum number of metablocks that can be created across the selected memory dies is determined by a lowest number of good blocks in the selected memory dies.