Patent ID: 7955967

Claim:
A method, comprising: forming a first substrate, said first substrate including: first transistors electrically connected to a set of wiring levels, each wiring level including electrically conductive wires in a respective dielectric layer; an etch stop layer on a top surface of an uppermost wiring level of said set of wiring levels that is furthest from said substrate, said etch stop layer in contact with a wire of said uppermost wiring level; and a first dielectric bonding layer on a top surface of said etch stop layer; forming a second substrate, said second substrate including: a second dielectric bonding layer; a buried oxide layer on a top surface of said second dielectric bonding layer; a semiconductor layer on a top surface of said buried oxide layer, said semiconductor layer including second transistors electrically isolated from each other by dielectric isolation in said silicon layer; a profile modulation layer on a top of said silicon layer and on a top surface of said dielectric isolation; and a first dielectric layer on a top surface of said profile modulation layer; bonding a top surface of said first dielectric bonding layer to a bottom surface of said second dielectric bonding layer, said first and second dielectric bonding layers, said buried oxide layer and said dielectric isolation comprising a multilayer second dielectric layer; reactive ion etching an opening through said first dielectric layer, said profile modulation layer, said second dielectric layer and said etch stop layer to a top surface of said wire; and filling said opening with an electrical conductor, said electrical conductor in electrical contact with said wire.