Patent ID: 8482127

Claim:
A chip comprising: a silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride, wherein one of multiple openings in said passivation layer has a diameter between 0.5 and 30 micrometers; a first via in one of said multiple openings, wherein said first via is connected to said first interconnecting structure; a second via in one of said multiple openings, wherein said second via is connected to said second interconnecting structure; and a clock bus over said passivation layer, wherein said clock bus is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.