Patent ID: 7266036

Claim:
A semiconductor memory device comprising: a plurality of memory blocks including a plurality of word lines and a plurality of bit line pairs intersecting the individual word lines, a plurality of memory cells provided at each of intersections where the individual word lines intersect the individual bit line pairs, and a plurality of sense amplifiers respectively provided in correspondence with the plurality of bit line pairs; a plurality of common data bus line sets each electrically connected via first selection switches to the corresponding memory blocks; and at least one latch circuit electrically connected via second selection switches to each of the common data bus line sets, wherein switching from a first state to a second state is performed by the first selection switches and the second selection switches, each of the common data bus line sets is connected with the corresponding memory blocks in the first state, each of the common data bus line sets is connected to at least one latch circuit in the second state, and the first selection switches are on and the second selection switches are off in the first state and the first selection switches are off and the second selection switches are on in the second state.