Patent ID: 8539173

Claim:
A memory system comprising: a memory device comprising: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines, the plurality of memory cells of the consecutive addresses being accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells, wherein, among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address; and a memory control device executing access control on the memory device, wherein, when executing a read operation on the memory device, the memory control device selects and outputs data read from one of the first and second memory cells having the same address, and wherein, when a read address and a read data length externally specified indicate that requested data includes an address overlapping between the first and second memory cells, if the requested data further includes an address that is selected by the first word line and is not selected by the second word line, the memory control device outputs data read from the first memory cell, or if the requested data further includes an address that is selected by the second word line and is not selected by the first word line, the memory control device outputs data read from the second memory cell.