Patent ID: 7937062

Claim:
An integrated circuit including a multiple-FET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the integrated circuit comprising: a) a series stack of J same-polarity FETs M N , N an integer between 1 and J and J an integer 3 or greater, each FET M N having a source S N , a gate G N and a drain D N , b) an input signal node coupled to the gate G 1 of a signal-input FET M 1 of the FET stack; c) for 0<N<J, a series coupling between each drain D N and the source S (N+1) of a next higher FET M (N+1) of the FET stack; d) for 1<N≦J, a gate coupling element that is predominately capacitive connected directly between each gate G N and Vref, in a configuration enslaving each FET M (N+1) to M 1 so as to conduct substantially concurrently with, and under control of, conduction in M 1 , wherein, for 1<N≦J, each FET M N is biased to avoid exceeding breakdown characteristics of the FET M N ; and wherein each gate G N is provided with a suitable bias voltage, and wherein the bias voltage is decoupled to Vref; e) a source coupling for the FET stack between S 1 and Vref; and f) a drain coupling for the FET stack between D J and Vdrive.