Patent ID: 8219754

Claim:
A self-configuring cache architecture for a digital signal processor, comprising a computational unit, the computational unit comprising: an execution-space decode logic circuit that (i) dynamically determines, during run-time execution of an executable program, whether a current instruction in the executable program is coming from an external memory or an internal memory and (ii) outputs an external execution-space control signal if the current instruction is coming from the external memory and outputs an internal execution-space control signal if the current instruction is coming from the internal memory; and a cache control logic circuit that configures a cache memory to store, in a traditional cache space, a conflict-free instruction from the external memory or to store, in a conflict cache space, a conflicted instruction from the internal memory based on an outcome of the determination, wherein the cache control logic circuit transfers the current instruction to and between the cache memory, the internal memory, and the external memory based on the configuration of the cache memory, thereby avoiding a pipeline stall during a next use of the current instruction, the cache control logic circuit comprising: a cache controller; a conflict instruction cache enabler that determines whether the current instruction in the executable program has a memory conflict condition and then outputs a conflict instruction load enable signal upon finding the memory conflict condition; a traditional instruction cache enabler that enables a traditional instruction load enable signal for the current instruction in the executable program upon receiving the current instruction from the external memory, wherein the conflict instruction cache enabler and the traditional instruction cache enabler output an instruction load enable signal via the cache controller to configure the cache memory to behave like a traditional cache or a conflict cache based on the instruction load enable signal, wherein the instruction load enable signal transfers the current instruction to and between the cache memory, the internal memory, and the external memory based on the configuration of the cache memory; and a MUX, coupled to the execution-space decode logic circuit, outputs the instruction load enable signal and enables the cache memory to behave like a conflict cache via the cache controller and transfers the current instruction to and between the internal memory, cache memory and the computational unit upon finding the memory conflict condition and receiving the internal execution-space control signal.