Patent ID: 6911868

Claim:
A phase-locked loop (PLL) frequency synthesizer comprising: a voltage controlled oscillator (VCO) that receives a frequency control voltage level stored on a loop filter and generates an output clock signal having an operating frequency, Fout, determined by said frequency control voltage level; a first frequency divider for dividing said operating frequency, Fout, of said output clock signal by a first divider value, N, to produce a first divided clock signal having a frequency, Fout/N; a second frequency divider for dividing a reference frequency, Fin, of an incoming reference clock signal by a second divider value, M, to produce a second divided clock signal having a frequency, Fin/M; a phase-frequency detector capable of comparing said first and second divided clock signals and generating an UP control signal if said first divided clock signal is slower than said second divided clock signal and generating a DOWN control signal if said first divided clock signal is faster than said second divided clock signal; a charge pump capable of receiving said UP and DOWN control signals and increasing said frequency control voltage level on said loop filter by injecting a charge pump current, Ic, and decreasing said frequency control voltage level on said loop filter by draining said charge pump current, Ic; and a loop response control circuit capable of adjusting a value of Ic as a function of said first divider value, N, and said second divider value, M, wherein said loop response control circuit is capable of adjusting the value of Ic based at least partially on at least one of: one of a first plurality of ranges in which said first divider value lies and one of a second plurality of ranges in which said second divider value lies.