Patent ID: 7126399

Claim:
An intergrated circuit comprising: a plurality of programmable logic elements, configurable to implement user-defined logic functions; a double data-rate register coupled to the plurality of programmable logic elements and having data and clock inputs and comprising: a first storage circuit having a data input coupled to the data input of the double data-rate register; a second storage circuit having a data input coupled to the data input of the double data-rate register; and a third storage circuit having a data input coupled to the an output of the second storage circuit; a first delay element to provide a delay between a signal at the data input of the double data-rate register and a signal at the clock input of the double data-rate register, the first delay element comprising: a first delay circuit; a second delay circuit; and a multiplexer having a first input coupled to an output of the first delay circuit and a second input coupled to an output of the second delay circuit; and a control circuit coupled to adjust the delay provided by the first delay element, the control circuit comprising; a second delay element comprising: a first delay circuit; a second delay circuit; and a multiplexer having a first input coupled to an output of the first delay circuit and a second input coupled to an output of the second delay circuit; and a control logic circuit.