Patent ID: 7393780

Claim:
A dual damascene semiconductor device structure comprising: a substrate having a metallization layer formed thereon; a first barrier layer containing silicon carbide and nitrogen formed on the substrate such that it covers at least a portion of the metallization layer; a nitrogen-free second barrier layer formed on top of the first barrier layer to reduce the effects of nitrogen poisoning in subsequently formed photoresist layers; a first low-k dielectric layer formed on the second barrier layer; an etch stop layer deposited on top of the second barrier layer; a second low-k dielectric layer deposited on top of the etch stop layer; a via formed such that it extends through the first and second low-k dielectric layers but does not substantially extend into the underlying barrier layers; a trench formed such that it extends through the second low-k dielectric layer but not into the first low-K dielectric layer; and a conductive material filling the via and trench but does not substantially extend into the underlying barrier layers.