Patent ID: 7629230

Claim:
A wafer processing method for dividing, along a plurality of streets, a wafer having a device area where devices are formed in a plurality of areas sectioned by the plurality of streets arranged in a lattice pattern on the front surface of a substrate and a peripheral extra area surrounding the device area and comprising electrodes which are embedded in the substrate of the device area, comprising: a dividing groove forming step for forming dividing grooves having a depth corresponding to the final thickness of each device along the streets from the front surface side of the substrate of the wafer; an annular groove forming step for forming an annular groove having a depth corresponding to the final thickness of each device along the boundary between the device area and the peripheral extra area from the front surface side of the substrate; a protective member affixing step for affixing a protective member to the front surface of the wafer which has undergone the dividing groove forming step and the annular groove forming step; a rear surface grinding step for grinding the rear surface corresponding to the device area of the substrate of the wafer which has undergone the protective member affixing step to expose the dividing grooves and the annular groove to the rear surface of the substrate of the wafer and form an annular reinforcing portion in an area corresponding to the peripheral extra area; and a rear surface etching step for etching the rear surface of the substrate of the wafer which has undergone the rear surface grinding step to project the electrodes from the rear surface of the substrate.