Patent ID: 8243493

Claim:
A resistance change memory device comprising: a semiconductor substrate; a cell array so formed on the substrate as to have resistance-change memory cells three-dimensionally stacked and arranged; and a sense amplifier array formed on the substrate under the cell array, wherein the cell array includes first and second cell array blocks arranged in a bit line direction, and first and second bit lines are selected from the first and second cell array blocks, respectively, to constitute a pair, and are coupled to differential input nodes in the sense amplifier array, wherein the first and second cell array blocks include reference cells, each of which has a reference resistance value used for sensing data of a selected memory cell, the first bit line is connected to a selected memory cell in the first cell array block and connected to one differential input node of the sense amplifier array via a vertical wiring at a side of the second cell array block of the cell array, and the second bit line is connected to the reference cell in the second cell array block and connected to another differential input node of the sense amplifier array via another vertical wiring at a side of the first cell array block of the cell array.