Patent ID: 7688393

Claim:
A substrate for a liquid crystal display, comprising: a plurality of gate bus lines formed in parallel with each other on a substrate; a plurality of drain bus lines formed across the plurality of gate bus lines with an insulation film interposed between them; a plurality of storage capacitor bus lines formed in parallel with the gate bus lines; first and second transistors each having a gate electrode electrically connected to an n-th gate bus line and a drain electrode electrically connected to one of the drain bus lines; a first pixel electrode electrically connected to a source electrode of the first transistor; a second pixel electrode electrically connected to a source electrode of the second transistor and separated from the first pixel electrode; a pixel region including a first sub-pixel at which the first pixel electrode is formed and a second sub-pixel at which the second pixel electrode is formed; a third transistor having a gate electrode electrically connected to an (n+1)-th gate bus line and a source electrode electrically connected to the second pixel electrode; and a buffer capacitor portion including a first buffer capacitor electrode disposed in the pixel region except in a region occupied by either of the first and second sub-pixels and electrically connected to a drain electrode of the third transistor and a second buffer capacitor electrode which is disposed opposite to the first buffer capacitor electrode with an insulation film interposed therebetween and which is electrically connected to the storage capacitor bus line.