Patent ID: 8373263

Claim:
An interconnection structure comprising a semiconductor chip, a mounting substrate on which said semiconductor chip is mounted, and a group of bonding wires provided to connect said semiconductor chip and said mounting substrate, wherein said group of bonding wires comprises: a first signal bonding wire contained in a first envelope and provided to propagate a signal; a first power supply bonding wire contained in said first envelope and applied with a first power supply voltage; and a second power supply bonding wire contained in a second envelope and applied with a second power supply voltage, wherein one of said first envelope and said second envelope is arranged between the other of said first envelope and said second envelope and said mounting substrate, and said second power supply bonding wire is arranged in a position in which electromagnetic coupling between said second power supply bonding wire and said first signal bonding wire is smaller than electromagnetic coupling between said second power supply bonding wire and said first power supply bonding wire.