Patent ID: 8314493

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a first wiring substrate including a first main surface, a plurality of bonding leads formed on the first main surface, a plurality of first lands formed on the first main surface, a first back surface opposed to the first main surface, and a plurality of second lands formed on the first back surface; (b) disposing a plurality of second conductive members over the first lands of the first wiring substrate; (c) mounting a first semiconductor chip on the first main surface of the first wiring substrate, the first semiconductor chip including a second main surface, a plurality of electrode pads formed on the second main surface, and a second back surface opposed to the second main surface, the plurality of bonding leads being arranged in plan view in a region of the first main surface between the first semiconductor chip and the plurality of first lands; (d) electrically connecting the electrode pads of the first semiconductor chip and the bonding leads of the first wiring substrate via a plurality of first conductive members, respectively; (e) sealing the first semiconductor chip and the second conductive members with resin forming a sealing body; (f) after the step (e), removing a portion of the sealing body such that each of the second conductive members is exposed at a front surface of the sealing body; and (g) after the step (f), reforming the second conductive members without stacking another member on the second conductive members such that a part of each second conductive member protrudes from the front surface of the sealing body.