Patent ID: 8598657

Claim:
A semiconductor device comprising: (a) a semiconductor chip having a first main surface and a second main surface and including a power MOSFET; (b) a source electrode of the power MOSFET provided on the side of the first main surface of the semiconductor chip; (c) a drift region of the power MOSFET provided in the surface of the semiconductor chip on the first main surface side and having a first conductivity type; (d) a plurality of trenches penetrating through the drift region from the first main surface side of the semiconductor chip; (e) a plurality of second conductivity type column regions embedded in the trenches by epitaxial growth, respectively, and having a second conductivity type opposite to the first conductivity type; and (f) a plurality of first conductivity type column regions provided between the second conductivity type column regions, constituting a super junction structure together with the second conductivity type column regions, and having the first conductivity type; wherein each of the first conductivity type column regions comprises: (f1) a lower layer region having a first impurity concentration; (f2) an upper layer region present between the lower layer region and the first main surface and having a second impurity concentration higher than the first impurity concentration; and (f3) a middle layer region present between the lower layer region and the upper layer region and having a third impurity concentration between the first impurity concentration and the second impurity concentration, and wherein the drift region is a conventional epitaxial layer.