Patent ID: 7186637

Claim:
A method of making an electronic assembly comprising: providing a first substrate having a first conductive interconnecting structure formed thereon; providing a second substrate having a second conductive interconnecting structure formed thereon; selectively forming a first conductive passivation layer over exposed areas of said first conductive interconnecting structure, said first conductive passivation layer protecting said first conductive interconnecting structure; selectively forming a second conductive passivation layer over exposed areas of said second conductive interconnecting structure, said second conductive passivation layer protecting said first conductive interconnecting structure; and bonding said first substrate and said second substrate together, said first conductive passivation layer bonding to said second conductive passivation layer to create a passivation-passivation interface; and wherein said first conductive interconnecting structure is deposited as a blanket layer to overfill a first via formed in a first dielectric layer, the first conductive interconnecting structure and first dielectric layer are polished to expose the first conductive interconnecting structure and wherein said second conductive interconnecting structure is deposited as a blanket layer to overfill a second via formed in a second dielectric layer, the second conductive interconnecting structure and second dielectric layer are polished to expose the second conductive interconnecting structure.