Patent ID: 8604568

Claim:
A method for forming a stacked integrated circuit package comprising one or more primary dies supported on a carrier die, the method comprising the steps of: forming electrically conductive pillars at connection pads defined on an active face of a carrier wafer incorporating a plurality of carrier integrated circuits, the electrically conductive pillars being configured to provide electrical connections to said carrier integrated circuits; attaching a plurality of primary dies to the active face of the carrier wafer, each primary die supporting one or more electrically conductive pillars at connection pads defined on an active face of the primary die for providing electrical connections to a primary integrated circuit incorporated in the primary die, wherein the perpendicular height of the electrically conductive pillars of the carrier dies above the active surface of the carrier wafer is greater than the thickness of the at least one primary die plus the perpendicular height of the electrically conductive pillars of that primary die above the active surface of that primary die; encapsulating the active face of the carrier wafer and the primary dies attached thereto in an insulating material, the thickness of the insulating material being sufficient to cover at least the plurality of primary dies; and removing a thickness of the insulating layer sufficient to expose the electrically conductive pillars.