Patent ID: 7948039

Claim:
A semiconductor device comprising: an element formed on a substrate in a chip region; a multilayer structure including a plurality of dielectric films formed on the substrate; an interconnect formed in at least one of the dielectric films in the chip region; a plug formed in at least one of the dielectric films in the chip region and connecting either the element and the interconnect or the interconnect and another interconnect; a seal ring structure formed through the multilayer structure in a peripheral part of the chip region and surrounding the chip region; and a protection film formed on the multilayer structure in which the interconnect, the plug and the seal ring are provided, the seal ring structure includes at least two seal rings surrounding the chip region, the protection film has a first opening only on a top of any one of the seal rings other than an innermost seal ring, a cap layer is formed in the first opening to be connected to the one of the seal rings other than the innermost seal ring, the plurality of dielectric films includes a first dielectric film and a second dielectric film, at least one of the seal rings includes one or more first seal vias in the first dielectric film and one or more second seal vias in the second dielectric film, the first dielectric film is formed between the substrate and the second dielectric film, a number of first seal vias is greater than a number of second seal vias, and the second seal vias have a length that is greater than a length of the first seal vias.