Patent ID: 7666786

Claim:
A method of fabricating a semiconductor device, comprising: forming a gate electrode structure, comprising a gate oxide layer pattern, a polysilicon layer pattern, and sidewall spacers on a silicon substrate; forming source/drain regions on both sides of the gate electrode structure in the silicon substrate; depositing a physical vapor deposition (PVD) cobalt layer on the gate electrode structure using PVD; depositing a chemical vapor deposition (CVD) cobalt layer on the PVD cobalt layer using CVD; annealing the silicon substrate to react the PVD and CVD cobalt layers with polysilicon on an upper surface of the gate electrode structure; stripping at least a portion of the PVD cobalt layer and the CVD cobalt layer that has not reacted; and annealing the silicon substrate after stripping the at least the portion of the PVD cobalt layer and the CVD cobalt layer.