Patent ID: 8618891

Claim:
A PLL (Phase Lock Loop) comprising: a differential VCO (Voltage Controlled Oscillator) with an output node and an inverse output node; said inverse output node coupled to an input of a first buffer; an output of said first buffer coupled to an input of a first function; an output of said first function coupled to an input of a divide by N; an output of said divide by N coupled to a first input of a PFD (Phase and Frequency Detect); a reference frequency coupled to a second input of said PFD; an output of said PFD coupled to an input of a charge pump; an output of said charge pump coupled to an input of said differential VCO; said output node coupled to an input of a second buffer; an output of said second buffer coupled to a second function; an output of said first function coupled to an input of a third buffer; and an output of said second function coupled to an input of a fourth buffer, wherein an output of said third buffer is in a desired phase separation from an output of said fourth buffer.