Patent ID: 8347254

Claim:
An integrated circuit (IC), comprising: a silicon substrate including a logic plane having circuitry fabricated on the logic plane, the circuitry including a first logic configured to electrically communicate with at least one re-writeable non-volatile non-Flash memory, and a second logic electrically coupled with the first logic and configured to control data operations access to at least one re-writeable non-volatile non-Flash memory; and at least one memory plane in direct contact with and vertically fabricated directly above the silicon substrate, the at least one memory plane including the at least one re-writeable non-volatile non-Flash memory, the at least one re-writeable non-volatile non-Flash memory is electrically coupled with the second logic and includes a plurality of re-writeable non-volatile memory elements (ME's), each ME having exactly two terminals, each ME is positioned between a unique pair of conductive array lines and is electrically in series with its unique pair of conductive array lines and with its two terminals.