Patent ID: 8367515

Claim:
A method for fabricating an integrated circuit, the method comprising: providing a substrate including a first region and a second region; forming a gate dielectric material layer on the substrate in the first and second regions; forming a gate electrode on the gate dielectric material in the first and second regions; forming a first trench in the first region, the first trench having a first aspect ratio in the first region and extending through the gate electrode, the dielectric material, and into the substrate; forming a second trench in the substrate through the second region, the second trench having a second aspect ratio in the second region, wherein the first aspect ratio is greater than the second aspect ratio; performing a high aspect ratio deposition process to form a first layer over the first and second regions of the substrate, wherein the first layer fills the first and second trenches; removing the first layer from the second region, wherein the first layer is removed from the second trench, wherein removing the first layer from the second region comprises forming a masking layer over the first region and etching the first layer in the second region; and performing a high density plasma deposition process to form a second layer over the first and second regions of the substrate, wherein the second layer fills the second trench and the first trench.