Patent ID: 6924180

Claim:
A method of forming a metal oxide semiconductor field effect transistor (MOSFET), on a semiconductor substrate, featuring formation of a combination of two pocket implant regions, one completely surrounding a lightly doped source/drain region and the other formed adjacent to the sides of a heavily doped source/drain region, comprising the steps of: providing a gate insulator layer on a semiconductor substrate comprised with a first conductivity type, with a gate structure overlying said gate insulator layer; forming a said lightly doped source/drain (LDD) region of a second conductivity type, in portion of said semiconductor substrate not covered by said gate structure; forming first pocket region of a first conductivity type in a portion of said semiconductor substrate not covered by said gate structure, with said first pocket region completely surrounding said LDD region, and wherein said first pocket region, completely enclosing said LDD region, is comprised with a dopant level greater than the dopant level of said semiconductor substrate; forming a composite insulator spacer on sides of said gate structure, with said composite insulator spacer comprised of an underlying L shaped insulator component, and comprised of an overlying insulator component; forming said heavily doped source/drain region of a second conductivity type, in a portion of said semiconductor substrate not covered by said gate structure or by said composite insulator spacer; removing said overlying insulator component of said composite insulator spacer; and forming a second pocket region of a first conductivity type in a portion of said semiconductor substrate underlying horizontal portion of L shaped insulator component and adjacent to sides of said heavily doped source/drain region, with said second pocket region comprised with a dopant level greater than the dopant level of said first pocket region.