Patent ID: 6888755

Claim:
In a non-volatile memory including an array of charge storage elements positioned over a substrate surface between source and drain regions, a method of altering or determining charge states of designated ones of the storage elements, comprising: applying first voltage levels to at least a first and a second control gates that are both capacitively coupled with the designated storage elements to combine to cause the charge states of the designated storage elements to be either altered or determined, simultaneously applying a second voltage level to at least a third control gate that is capacitively coupled with a first group of non-designated storage elements that are also coupled with one of the first or second control gates to combine to cause the charge states of the first group of non-designated storage elements to be neither altered nor determined, and simultaneously applying third voltage levels to additional control gates to which other non-designated storage elements are capacitively coupled with at least two thereof to combine to cause the charge states of the other non-designated storage elements to be neither altered nor determined.