Patent ID: 7752586

Claim:
A design structure for designing, manufacturing, or testing a design, the design structure comprising a Large Scale integrated (LSI) circuit chip including: a first flip-flop which is capable of flushing test data, and which operates by using a first clock signal; a second flip-flop which is capable of flushing said test data, and which operates by using a second clock signal, and which is connected to the first flip flop; a third flip-flop which operates by using the second clock signal, and which is connected to the first flip-flop; and a fourth flip-flop which operates by using the first clock signal, and which is connected to the second flip-flop, the integrated circuit chip, wherein a test is performed in a computer on a path linking the first and the second flip-flops and is carried out in: a first test mode in which said test data is released from the third flip-flop on receipt of the second clock signal, is flushed by the first flip-flop, and is captured in the second flip-flop; and a second test mode in which said test data is released from the first flip-flop on receipt of the first clock signal, is flushed by the second flip-flop, and is captured in the fourth flip-flop.