Patent ID: 8719549

Claim:
A device to reconfigure multi-level logic networks, wherein a plurality of pq elements storing look-up tables (LUTs) of subfunctions obtained by the functional decomposition of an objective logic function F(X) with input variables X, are connected to form a network according to a connection relation among inputs and outputs of said subfunctions, due to a logic modification that modifies an output vector F(b) of said objective logic function F(X) for an input vector b to an “invalid value”, comprising: means to select an element that selects pq elements one-by-one from a pq element E G that is in a nearest place to an output terminal, among unmodified said plurality of pq elements; means to check correspondence that checks whether the input vector corresponding to an output vector c exists other than said input vector b, wherein c denotes the output vector for said input vector b among output vectors of LUTs of said pq element E G ; and means to modify by deleting a vector that changes the state of said pq element E G one-by-one as modified, and to rewrite the output vector c for said input vector b to the “invalid value”, when said input vector b is the only vector that produces said output vector c in LUTs of the pq element E G .