Patent ID: 8284620

Claim:
An integrated circuit comprising a memory controller interface comprising: a first plurality of address lines coupled to a first memory circuit; a first plurality of control lines coupled to the first memory circuit; a second plurality of address lines coupled to a second memory circuit; and a second plurality of control lines coupled to the second memory circuit, wherein when a first control line in the first plurality of control lines is also coupled to the second memory circuit and the memory controller interface operates at an interface frequency below a first frequency, then the first control line operates at a first rate; and wherein when the first control line is not also coupled to the second memory and the interface frequency is below a second frequency, the second frequency higher than the first frequency, then the first control line also operates at the first rate, otherwise the first control line operates at the second rate, where the first rate is faster than the second rate, wherein when the first control line is not also coupled to the second memory and the memory controller interface operates at a frequency above the second frequency, then the first control line operates at the second rate.