Patent ID: 7262986

Claim:
A memory system comprising: a ferroelectric memory having a cell driving block and a data amplifying block, the cell driving block applying voltage to a data retention element and the data amplifying block amplifying readout data from the data retention element; a data latch circuit retaining output timings and pulse widths of control signals respectively controlling the cell driving block and the data amplifying block; a timing generating circuit respectively outputting the control signals to the cell driving block and to the data amplifying block according to the output timings and the pulse widths of the control signals retained in the data latch circuit; and a temperature detecting circuit detecting an ambient temperature and outputting a selecting signal corresponding to the detected temperature to the data latch circuit; wherein: the data latch circuit retains, as the pulse widths of the control signals, a plurality of different pulse widths that correspond to temperatures and selects a pulse width corresponding to the selecting signal from the temperature detecting circuit; and operating periods of the cell driving block and the data amplifying block of the ferroelectric memory are varied according to the ambient temperature.