Patent ID: 8264068

Claim:
A multi-chip stack package structure, comprising: a substrate, having an upper surface and a lower surface, a chip placement area being defined on and a plurality of contacts being disposed on said upper surface, said plurality of contacts being located outside said chip placement area; a first chip, having an active surface and a rear surface opposite to said active surface, said first chip being disposed in said chip placement area with said rear surface, a plurality of first pads being disposed on peripheral regions of said active surface and a plurality of first bumps each being formed on one of said plurality of first pads; a plurality of metal wires, connecting said plurality of first bumps to said plurality of contacts; a second chip, having an active surface, a rear surface opposite to said active surface and a plurality of through silicon vias, each of said plurality of through silicon vias penetrating through said second chip interconnecting said active surface and said rear surface and forming a first end on said active surface and a second end on said rear surface, a plurality of second bumps being respectively formed on said second ends of at least a portion of said plurality of through silicon vias, wherein said second chip is mounted to said first chip with said rear surface of said second chip facing said active surface of said first chip and said plurality of second bumps being correspondingly connected to said plurality of metal wires and said plurality of first bumps respectively; a third chip, having an active surface, a rear surface opposite to said active surface and a plurality of through silicon vias, each of said plurality of through silicon vias penetrating through said third chip interconnecting said active surface and said rear surface and forming a first end on said active surface and a second end on said rear surface, a plurality of third bumps being respectively formed on said second ends of at least a portion of said plurality of through silicon vias, wherein said third chip is mounted to said second chip with said rear surface of said third chip facing said active surface of said second chip and said plurality of third bumps being correspondingly connected to said first ends of said plurality of through silicon vias of said second chip respectively; and an encapsulant, encapsulating said substrate, said first chip, said second chip, said third chip, and said plurality of metal wires.