Patent ID: 8347068

Claim:
A computer-implemented method for processing a number of threads in a data processing system, the computer-implemented method comprising: responsive to changing an execution mode of a processor to operate in in-order thread execution mode, switching a physical register in the data processing system to operate as part of an architected facility to form a switched physical register; issuing an instruction to an execution unit, wherein the issued instruction comprises a thread bit; examining the thread bit to determine if the instruction accesses a logical register of the architected facility or the switched physical register of the architected facility; executing the instruction; writing results of the executed instruction to the architected facility; responsive to changing the execution mode of the processor to operate in out-of-order thread execution mode, switching the switched physical register in the data processing system from operating as part of the architected facility back to operating as the physical register; issuing a second instruction to an execution unit; executing the second instruction; and writing results of the executed second instruction to the physical register; wherein the physical register is switched from being an entry in a register rename buffer when the processor is operating in the out-of-order thread execution mode to being the switched physical register when the processor is operating in the in-order thread execution mode in order to augment logical registers in the architected facility when the processor is operating in the in-order thread execution mode; and wherein the out-of-order thread execution mode for the processor is a mode where the processor executes at least one instruction of a given thread out of order with respect to other instructions of the given thread, and the in-order thread execution mode for the processor is a mode where the processor executes all instructions of the given thread in order.