Patent ID: 8612917

Claim:
A method for selecting gate sizes for a logic network of an integrated circuit, wherein the logic network is defined by a plurality of logic paths that includes nodes, gates and interconnect, the method comprising: assigning, at one or more computers, gate sizes to gates adjacent to timing path end nodes of the logic network; determining an n-tuple of performance and loading parameters for each of the assigned gate sizes based on gate and interconnect delay models; determining whether two or more logic paths share a descendent gate, wherein two or more logic paths that share a descendent gate are coupled and wherein the shared descendent gate resides within at least two instances of a hierarchical block; grouping the n-tuples of performance and loading parameters of coupled logic paths into bins based on gate sizes of the shared descendent gate; recursively propagating, node by node, the bins of n-tuples of performance and loading parameters along the coupled logic paths; detecting whether any of the bins of n-tuples of performance and loading parameters are suboptimal for all of the coupled logic paths based on a comparison of the n-tuples of performance and loading parameters in bin-pairs; and eliminating all n-tuples of performance and loading parameters of the suboptimal bins along the coupled logic paths to prune gate sizes associated with the suboptimal bins.