Patent ID: 7310788

Claim:
A method for determining a sampling of a probability of fault (POF) for an integrated circuit design layout, the method comprising the steps of: constructing a critical defect size map based on a layout geometry of the integrated circuit design under any distance measure defined by a polygonal unit shape, wherein the critical defect size map is partitioned into a plurality of faces corresponding to the polygonal unit shape; accumulating a convolved sampling of POF contributions of each critical defect size map face, wherein the accumulating includes invoking a convolution operator to convolve the POF function of each critical defect size map face to a form independent of defect size r, wherein the convolution operator is of the form: C n ⁡ ( F , x ) = ∑ i = 0 n ⁢ ( - 1 ) n ⁢ ( n i ) ⁢ F ⁡ ( x + n - i 2 ⁢ w ) where C n (F, x) is the convolution operator, n is an order of the convolution, F represents any polynomial function, x is a sampling point, i is iteration number, and w is a size of a sampling interval; and accumulating a sum of the convolution operator from all critical defect size map faces in the critical defect size map; and reconstructing an exact value of the POF at the sample points based on the accumulated convolutions.