Patent ID: RE42202

Claim:
A circuit for controlling an enabling period of an internal control signal in accordance with variation of an operating frequency in a memory device, the circuit comprising: a pulse width adjusting circuit comprised of a first delay circuit and a NAND gate at least one of a NAND gate and a NOR gate , which changes a pulse width of an input signal in accordance with the operating frequency, said NAND gate at least one of a NAND gate and a NOR gate receiving the input signal and an output signal of the first delay circuit, the first delay circuit receiving the input signal and a clock signal of the memory device and adjusting a delay time in accordance with a frequency of the clock signal until the input signal is applied to an input terminal of the NAND gate at least one of a NAND gate and a NOR gate ; a signal transmission circuit for buffering a signal outputted from the pulse width adjusting circuit; and an output circuit for outputting a first signal to control an operation of a data bus of the memory device in response to a signal outputted from the signal transmission circuit, wherein as the clock signal duration shortens, the pulse width of the first signal is narrower.