Patent ID: 7196000

Claim:
A method for a wafer level chip scale package (CSP), the method comprising: providing a semiconductor wafer, the semiconductor wafer including semiconductor chips having chip pads and a passivation layer, the wafer further including scribe lines between the chips; forming a first patterned dielectric layer on the passivation layer that exposes the chip pads; forming a second patterned dielectric layer on the first patterned dielectric layer that exposes the chip pads; forming an embossed region on the first patterned dielectric layer, the second patterned dielectric layer, and the passivation layer including a concave portion that exposes a portion of the passivation layer where a ball pad is to be formed and a convex portion that is formed from the second patterned dielectric layer; forming a metal wiring layer on the embossed region directly on the exposed portion of the first patterned dielectric layer, the exposed portion of the second patterned dielectric layer, and the exposed portion of the passivation layer, the metal wiring layer being electrically connected to the chip pads; forming a third dielectric layer on the metal wiring layer; and removing a portion of the third dielectric layer over the embossed region to form a connection hole therein, the connection hole exposing a portion of the metal wiring layer to form the ball pad.