Patent ID: 8625334

Claim:
A memory cell comprising: a first pull-up transistor and a first pull-down transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node; a second pull-up transistor and a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node; a first pass-gate transistor electrically coupled to the first node; a second pass-gate transistor electrically coupled to the second node; a first isolation transistor electrically coupled to the first node; and a second isolation transistor electrically coupled to the second node, wherein the first isolation transistor and the second isolation transistor are configured to have a negligible operational effect at the first node and the second node, respectively.