Patent ID: 7587443

Claim:
A multiplication circuit comprising: a 2N-bit multiplier, wherein the multiplication circuit has a first short word length multiplication mode and a second long word length multiplication mode, wherein a short word length is N and a long word length is 2N, wherein N is an integer; a first register that stores N bits and that has an output coupled with a first 2N-bit input of the 2N-bit multiplier; a second register that stores N bits and that has an output coupled with a second 2N-bit input of the 2N-bit multiplier; a first and a second 2N-bit accumulation unit, each having an input connected to an output of the 2N-bit multiplier, wherein: in the first mode for multiplying two N-bit numbers, a first long word length multiplicand is formed at the first 2N-bit input from a first short word length multiplicand stored in the first register, a second long word length multiplicand is formed at the second 2N-bit input from a second short word length multiplicand stored in the second register, and the first and second long word length multiplicands are multiplied together using the 2N-bit multiplier to form a 4N-bit result that includes the product of the first and second short word length multiplicands; and in the second mode for multiplying two 2N-bit numbers, a third long word length multiplicand is formed at the first 2N-bit input from a first pair of short word length words, wherein a first word of the first pair is stored in the first register, a fourth long word length multiplicand is formed at the second 2N-bit input from a second pair of short word length words, wherein a first word of the second pair is stored in the second register, and subsequently the third and fourth long word length multiplicands are multiplied together using the 2N-bit multiplier to form a 4N-bit result.