Patent ID: 8127204

Claim:
A memory system, comprising: a plurality of stacked memory device dice containing a plurality of memory cells; and a logic die coupled to the memory device dice through a plurality of through silicon vias, the logic die being operable to transfer data to and from the memory device dice in a packet each of which includes a serial burst of a plurality of parallel data bits, the logic die further comprising: an error checking system configured to generate a plurality of error checking bits from the write data transferred from the logic die to the memory device dice for storage in the memory device dice, the error checking system being configured to transfer the generated error checking bits from the logic die to the memory device dice in a serial burst of parallel error checking bits using respective through silicon vias, the error checking system further being structured to receive the read data transferred from the memory device dice to the logic die and corresponding error checking bits transferred from the memory device dice in a serial burst of parallel error checking bits using the respective through silicon vias, the error checking system further being configured to use the received error checking bits to determine if the corresponding read data contains at least one erroneous read data bit; and a data encoding system receiving the write data and being configured to use an encoding algorithm to encode the write data before the write data are transferred to the memory device dice and to transfer to the memory device dice at least one data encoding bit indicative of the encoding of the write data, the at least one data encoding bit being transferred to the memory device dice using at least one of the through silicon vias through which the error checking bits are transferred.