Patent ID: 8533721

Claim:
A processor comprising: logic to: determine in a first cycle, whether one or more operations are ready to be executed, wherein each of the one or more operations has a time stamp; determine in the first cycle, whether each of one or more input sources of each operation is to match an output destination of the one or more operations ready to be executed; in response to the determination that the one or more operations are ready to be executed, select in a second cycle, one of the one or more operations ready to be executed in a third cycle, wherein the first cycle, the second cycle and the third cycle are sequential time clock cycles; and in response to the determination that none of the one or more operations are ready to be executed, select in the second cycle, an operation with the oldest time stamp; determine in the second cycle, whether the selected operation with the oldest time stamp is ready to be executed; and dispatch the selected operation with the oldest time stamp for execution in the third cycle responsive to the determination that the selected operation with the oldest time stamp is ready to be executed.