Patent ID: 6990096

Claim:
A switch fabric implemented on a chip, comprising: a) an array of cells; b) an I/O interface in communication with said array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells; c) each cell including: I) a transmitter in communication with said I/O interface and in communication with every other cell of said array, said transmitter operative to process a data packet received from said I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on a basis of the determined destination; II) a plurality of receivers associated with respective cells from said array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver; III) said receivers in communication with said I/O interface for releasing data packets to said I/O interface; wherein said array of cells includes a plurality of data channels, each data channel being associated with a given cell, the data channel associated with said given cell connecting the transmitter of said given cell to receivers in cells other than said given cell and associated with said given cell; wherein the transmitter of said given cell includes a memory for storing data packets received from said I/O interface; wherein said memory includes a plurality of segments, each segment being associated with a receiver in a cell of said array to which the transmitter of said given cell is capable of forwarding a data packet via the data channel associated with said given cell; wherein the transmitter of said given cell includes a control entity that processes a data packet forwarded from said I/O interface to determine a cell of said array to which the packet is destined and identify on a basis of the determined cell a segment of said memory into which the packet is to be loaded; wherein said control entity includes a plurality of queue controllers associated with respective segments of said memory; wherein said memory implements a plurality of registers, each register being associated with a queue controller and being suitable for holding data representative of a degree of occupancy of a segment of said memory associated with the queue controller; wherein a data packet received by said transmitter from said I/O interface is characterized by a priority level selected from a group of priority levels, each segment of said memory being partitioned into slots, each slot being capable of storing at least one data packet, each slot being associated with a given priority level of said group of priority levels.