Patent ID: 7405440

Claim:
A nonvolatile semiconductor memory on a semiconductor chip, comprising: a cell array region configured with device isolating regions in a semiconductor substrate arranged in parallel to device activating regions in a memory cell transistor, which comprises a floating gate electrode, an insulating film formed on the floating gate electrode, a first control gate electrode stacked on the floating gate electrode via the insulating film, and a first metallic salicide film electrically coupled with the first control gate electrode; a high voltage circuit region including a high voltage transistor, which comprises a second metallic salicide film, a first source region and a first drain region, and a first gate region arranged between the first source region and the first drain region and electrically coupled with the second metallic salicide film; a low voltage circuit region including a low voltage transistor, which comprises a third metallic salicide film, a second source region and a second drain region electrically coupled with the third metallic salicide film, and a second gate region arranged between the second source region and the second drain region and electrically coupled with the third metallic salicide film; and a resistive element region electrically insulated from the first through third metallic salicide films, wherein the resistive element region is formed on the device isolating regions in the semiconductor substrate.