Patent ID: 6961271

Claim:
A memory device comprising: a memory cell array block comprising pairs of memory cells, each being composed of a memory cell and a complementary memory cell and disposed at intersections of rows and columns, in which first and second memory cells and first and second complementary memory cells are connected to a first wordline arranged in the row direction, third and fourth memory cells and third and fourth complementary memory cells are connected to a second wordline, the first and third memory cells are adjacently disposed between the first and second wordlines, the second and fourth memory cells are adjacently disposed therebetween, the first and third complementary memory cells are adjacently disposed therebetween, and the second and fourth complementary memory cells are adjacently disposed therebetween; a first sense amplifier disposed over the memory cell array block; a second sense amplifier disposed under the memory cell array block; a first switch for connecting bitlines coupled to the first memory cell and the first complementary memory cell with the first sense amplifier and connecting bitlines coupled to the second memory cell and the second complementary memory cell with the second sense amplifier; and a second switch for connecting bitlines coupled to the third memory cell and the third complementary memory cell with the first sense amplifier and connecting bitlines coupled to the fourth memory cell and the fourth complementary memory cell with the second sense amplifier.