Patent ID: 7100025

Claim:
An apparatus comprising: a multiply accumulate (MAC) unit coupled to operand busses at respective operand inputs, the MAC unit configured to latch a first multiple-bit data value during a first cycle and execute the MAC functions on the first multiple-bit data value during the next subsequent cycle while latching a second multiple-bit data value, the MAC unit further configured to supply a first MAC result responsive to the first multiple-bit data value on a result bus once the first MAC result is available and latch a second MAC result responsive to the second multiple-bit data value; a register coupled to the result bus and configured to latch the first MAC result; and a miscellaneous logic unit coupled between the result bus and the register, the miscellaneous logic unit configured to detect one or more exceptional conditions, the miscellaneous logic unit further configured to generate first and second control signals responsive to at least one certain exceptional condition, wherein when the first control signal is asserted the MAC unit supplies the second MAC result on the result bus, when the second control signal is asserted the first MAC result is driven from the register onto the result bus, and wherein when the second control signal is not asserted a miscellaneous-unit generated result is driven onto the result bus.