Patent ID: 7333909

Claim:
A circuit for verifying a data transfer protocol, said circuit comprising: a processor of a programmable logic device implementing a variable latency data transfer protocol; a memory coupled to receive an address from a memory controller of said programmable logic device; a counter coupled to receive an enable signal from said memory controller; a comparator coupled to said counter, said comparator receiving a selected delay number and the output of said counter, wherein said selected delay number is varied to represent a variable number of clock cycles for transferring data according to said variable latency data transfer protocol; a multiplexer coupled to receive output data from said memory and known invalid data; an acknowledge signal generated by said comparator when said output of said counter equals said selected delay number, wherein said acknowledge signal is used to select either said output data from said memory or said known invalid data, and said output of said multiplexer is used in verifying that said processor is implementing said variable latency data transfer protocol.