Patent ID: 7610433

Claim:
A memory controller interface for enabling a processor designed to support NOR flash and static random access memory (SRAM) components to use NAND flash and synchronous dynamic random access memory (SDRAM), the memory controller interface comprising: a cache controller module for managing the flow of data between the NAND flash and sectors of SDRAM comprising a cache for storing data read from sectors of the NAND flash; a read-write buffer in communication with the cache controller module and with interface controllers for the NAND flash and SDRAM, respectively, for buffering data read or written between the cache and the NAND flash memory; a cache tag memory for storing at least one tag entry for correlating a sector of cache with a sector of NAND flash, such that when a processor requests data from the NAND flash, the memory controller interface is capable of accessing the appropriate data sector from the NAND flash, reading the requested data, and writing the data using the read-write buffer to a sector of the cache for future processor requests for said data sector; a register accessible to the processor for storing fetched instructions; and a register for storing predefined memory boundaries allocated to code execution by the processor, wherein the memory controller interface is configured, upon detecting a request by the processor for access to a memory address beyond the predefined memory boundaries, to latch the memory address requested by the processor and to write a non-executable instruction to the register for storing fetched instructions, such that a software interrupt or undefined instruction trap is triggered when the processor reads the non-executable instruction.