Patent ID: 7840734

Claim:
A buffering circuit comprising: a first buffer circuit for a clock signal path for buffering a clock or timing signal and a second buffer circuit for a data signal path for buffering a data signal, wherein the clock and data signal paths each comprise a first bi-directional signal path providing circuitry adapted to generate a logic high level on said first bi-directional signal path and a second bi-directional signal path including circuitry adapted to generate a logic high level on said second signal bi-directional signal path; one or more first stations connected to at least one of the first bi-directional signal paths adapted to monitor a logic level on at least one of first bi-directional signal paths, and to generate a logic low level on at least one of the first bi-directional signal paths; a bus buffer operatively coupled to at least one of the first bi-directional signal paths, said bus buffer device having a first receive input also capable of functioning as an output capable of pulling at least one of the first bi-directional signal paths low; one or more second stations connected to at least one of the second bi-directional signal paths adapted to monitor the logic level on at least one of the second bi-directional signal paths, and to generate a logic low level on at least one of the second bi-directional signal paths, wherein at least one of the second bi-directional signal paths is operatively coupled to a second receive input of the bus buffer, wherein the second receive input is also capable of functioning as an output capable of pulling at least one of the second bi-directional signal paths low; the bus buffer further including in a clock control buffer a means adapted to ensure that an output voltage on the second bi-directional signal path of the clock signal path follows an input voltage on the first bi-directional signal path of the clock signal path; and the bus buffer further including in a data control buffer a means adapted to ensure that if the first bi-directional signal path of the data signal path is pulled low first then the second bi-directional signal path of the data signal path follows the first bi-directional signal path of the data signal path, or, if the second bi-directional signal path of the data signal path is pulled low first then the first bi-directional signal path of the data signal path will follow the second bi-directional signal path of the data signal path.