Patent ID: 8842986

Claim:
A circuit for controlling multi-channel power, said circuit comprising: a single channel selection module, configured that a first input end inputs a channel selection signal in a previous clock cycle; a second input end inputs at least one channel signal in the previous clock cycle; an output end outputs one channel signal in the previous clock cycle selected from said at least one channel signal in the previous clock cycle according to the channel selection signal in the previous clock cycle; a gain module, configured that a first input end inputs an amplification factor control signal in the previous clock cycle; a second input end inputs said one channel signal selected in the previous clock cycle; and an output end outputs a first signal acquired by amplifying said one channel signal selected in the previous clock cycle according to said amplification factor control signal in the previous clock cycle; an A/D conversion module, configured that an input end inputs said first signal; an output end outputs a second signal acquired by performing A/D conversion on the first signal; and a gain control module, configured that an input end inputs said second signal; a first output end connects with the first input end of the single channel selection module and outputs the channel selection signals in the previous clock cycle and a next clock cycle, and the channel selection signal in the next clock cycle is the same as that in the previous clock cycle; a second output end connects with the first input end of said gain module, and outputs the amplification factor control signal in the previous clock cycle, as well as outputs the amplification factor control signal in the next clock cycle generated according to the second signal, wherein when said second signal is less than a first threshold, the amplification factor in the next clock cycle is greater than a second threshold, and when said second signal is greater than or equal to the first threshold, the amplification factor in the next clock cycle is less than or equal to the second threshold, so that the gain module amplifies one channel signal selected in the next clock cycle according to said amplification factor control signal in the next clock cycle.