Patent ID: 6931613

Claim:
A method of computing parasitic electrical properties of circuit elements to be created in an integrated circuit, comprising: receiving at least a portion of a hierarchical layout database having a number of data levels that define circuit elements to be created in the integrated circuit; dividing the circuit elements to be created into a number of subsets, each of which defines circuit elements to be created in an area of the integrated circuit; flattening the data in each subset to define circuit elements in an interior region that do not interact with circuit elements in other areas and circuit elements in a boundary region that may interact with circuit elements in other boundary regions; computing the parasitic electrical properties of circuit elements in the interior regions of the areas; forming a circuit representation of the computed parasitic electrical properties of the interior circuit elements; computing the parasitic electrical properties of the circuit elements in the boundary regions due to interactions with circuit elements in the interior region of the areas; promoting the circuit elements within the boundary regions and their parasitic electrical properties due to interactions with circuit elements in the interior regions of the subsets to another hierarchy data level; computing the parasitic electrical properties of the promoted circuit elements due to interactions with other promoted circuit elements and interactions with circuit elements in the interior regions; forming a circuit representation of the computed parasitic electrical properties of the promoted circuit elements; and combining the circuit representations for the interior circuit elements and the promoted boundary region circuit elements into a representation suitable for circuit analysis.