Patent ID: 7469308

Claim:
An apparatus, comprising: means for sending a write command or a write address, or combinations thereof, from a first bus master in a plurality of bus masters to a bus cycle assignment unit over a bus in a first bus transaction initiated by the first bus master, wherein the bus cycle assignment unit is configured for allocating bus cycles to each bus master in the plurality of bus masters on the bus to control accesses to a shared memory; means for sending write data from the first bus master to the bus cycle assignment unit over the bus in a second bus transaction initiated by the first bus master, the write data corresponding to the write command or write address, or combinations thereof, sent in the first transaction; and means for using the write address or the write data, or combinations thereof, received by the bus cycle assignment unit to perform a write operation to the shared memory, wherein bus masters other than the first bus master may perform memory access operations on the bus between the initiation of the first bus transaction and the completion of the second bus transaction, wherein the memory access operations include transferring data to or from the shared memory.