Patent ID: 7519497

Claim:
In a target processor having three states: a primary code execution state, a secondary code execution state, and an execution halt state, a trace apparatus comprising: a trigger unit responsive to user and target processor state input signals corresponding to the three states, the trigger unit generating control signals in response to the input signals; timing trace apparatus, the timing trace apparatus responsive to the control signals for selectively providing timing trace streams during the secondary code execution state and the primary code execution state; program counter and data trace apparatus, the program counter and data trace apparatus responsive to the control signals for selectively providing program counter and data trace streams during the secondary code execution state when the timing trace apparatus is providing timing trace streams during the secondary code execution state; and a test and debug port, the test and debug port adapted for coupling to a communication bus, the test and debug port receiving signals from and sending signals to a host processor unit, wherein the control signals individually enable and disable each of the timing trace apparatus and the program counter and data trace apparatus based on a current state of the target processor.