Patent ID: 8853782

Claim:
A semiconductor device comprising: an insulating layer having a first region and a second region thinner than the first region; a semiconductor layer with a thickness of 10 nm to 25 nm on the first region; a first insulating layer on a side surface of the semiconductor layer; a side-wall insulating layer at the side surface of the semiconductor layer with the first insulating layer interposed therebetween; a gate insulating layer over the semiconductor layer; a gate electrode over the gate insulating layer; and a second insulating layer over and in contact with the gate electrode, a side surface of the gate insulating layer, the second region, a top surface of the semiconductor layer, the first insulating layer, and the side-wall insulating layer, wherein a thickness of the gate insulating layer is 2 nm or more and less than 20 nm, wherein a channel length is ten times or more and less than forty times the thickness of the semiconductor layer.