Patent ID: 8178933

Claim:
A semiconductor device including a transistor pair having one input gate, the transistor pair comprising a first transistor and a second transistor each of which is comprised of a plurality of fin transistors, wherein: the fin transistors are positioned along a row and the first transistor is comprised of odd-numbered fin transistors and the second transistor is comprised of even-number transistors, sources of the and the second transistor are commonly connected, gates of the first transistor and the second transistor are commonly connected; each fin transistor has a fin active layer protruding above a semiconductor substrate; each fin active layer has a source region provided in a surface region of the fin active layer and a drain region provided in a position in the surface region apart from the source area such that a channel region can be formed; the fin active layers are arranged in a row at constant intervals such that currents flowing through the respective channel regions between the source regions and the drain regions of the fin active layers are parallel to each other, the fin active layers having the same or substantially the same size; each of the first transistor and the second transistor is formed by 2m (m represents 2 or a greater integer) fin active layers, and the transistor pair a whole is formed by 4m fin active layers; the drain region and the source region are disposed in each of the fin active layers forming the first transistor such that the direction of the current flowing through each of the channel regions of the first to (2m−1)-th fin active layers is opposite to the direction of the current flowing through each of the channel regions of the (2m+1)-th to (4m−1)-th fin active layers; the drain region and the source region are disposed in each of the fin active layers forming the second transistor such that the direction of the current flowing through each of the channel regions of the second to 2m-th fin active layers is opposite to the direction of the current flowing through each of the channel regions of the (2m+2)-th to 4m-th fin active layers; the drain regions of the fin active layers forming the first transistor are commonly connected; the drain regions of the fin active layers forming the second transistor are commonly connected; and the source regions of the fin active layers are commonly connected.