Patent ID: 8405062

Claim:
A multi-layer cross point resistive memory device comprising: a conductive line on a semiconductor substrate; a first vertical diode on the conductive line; a first lower electrode on the first vertical diode; a first stacked line-shaped pattern on the first lower electrode crossing the conductive line at a right angle, the first stacked line-shaped pattern including a first resistor for storing first data, the first data being physically stored in the first resistor, and a first upper electrode that are sequentially stacked; a second vertical diode on the first stacked pattern; a second lower electrode on the second vertical diode; and a second stacked line-shaped pattern on the second lower electrode crossing the first stacked pattern at a right angle, the second stacked line-shaped pattern including a second resistor for storing second data, the second data being physically stored in the second resistor, and a second upper electrode that are sequentially stacked, wherein at least one of the first and second vertical diodes includes a poly-silicon pattern, an n-type impurity region on a lower portion of the poly-silicon pattern, and a p-type impurity region on an upper portion of the poly-silicon pattern, and the first and second vertical diodes have narrower widths than widths of the first and second lower electrodes.