Patent ID: 8621291

Claim:
A semiconductor device comprising: a bit line that transmits write data to be written to a memory cell and read data read from the memory cell; a write amplifier that is connected to the bit line; a read amplifier that is connected to the bit line via a first switch circuit; a relief memory element that includes a write port and a read port, the write port being connected to the bit line via a second switch circuit, and the read port being connected to the read amplifier via a third switch circuit; and a control circuit that controls an operation of each of the first, second and third switch circuits, wherein the control circuit controls the second switch circuit into an electrically on state so as to supply the write data from the write amplifier to the relief memory element via the bit line in response to the memory cell being defective during a write operation, and the control circuit controls the first switch circuit into an electrically off state and controls the third switch circuit into an electrically on state so as to supply relief data from the relief memory element to the read amplifier in response to the memory cell being defective during a read operation.