Patent ID: 8503259

Claim:
A memory test method for testing a memory by generating addresses and by writing and reading test data to and from the memory according to the addresses, the method comprising: sequentially generating 2n n-bit addresses (where n is a positive integer) different from each other, including, a first address of the 2n n-bit addresses having n-bits all set to one of two values, 0 or 1, a second address of the 2n n-bit addresses having a first bit set to the other one of the two values and a second bit to n-th bit all set to the one of the two values, a (2n−1)th address of the 2n n-bit addresses having a first bit to a (n−1)th bit all set to the one of two values and a n-th bit set to the other one of the two values, a 2n-th address of the 2n n-bit addresses having n-bits all set to the other one of two values, a third to (2n−2)th addresses of the 2n n-bit addresses configured to alternate two types of addresses, the one type of address having first to k-th bits (1<k<n) all set to the one of the two values and (k+1)th to n-th bits all set to the other one of the two values, and the other type of address having bits all set to the one of the two values except for the k-th bit and the k-th bit set to the other ones of the two values; writing test data to each of the generated 2n n-bit addresses in the memory; reading test data from each of the 2n n-bit addresses in the memory after the writing; comparing the written test data with the read test data; and determining that the memory is faulty, if the written test data and the read test data do not match each other as a result of the comparison.