Patent ID: 6990539

Claim:
An apparatus for implementing bus request routing to allow functionality with 2 way or 4 way processors, the apparatus comprising: a bus configured to provide bus request routing, wherein the bus comprises a first bus line, a second bus line, a third bus line, and a fourth bus line; and a bus request route switching stage coupled to the bus and configured to select a first route configuration if one or two processors are coupled to the bus, the switching stage configured to select a second route configuration if more that two processors are coupled to the bus; wherein the bus request route switching stage includes a first switching element, a second switching element, and a logic stage coupled to the first and second switching elements, wherein the logic stage is configured to detect if one or two processors are coupled to the bus or if more than two processors are coupled to the bus, wherein the logic stage is configured to generate a control signal that permits the switching elements to perform switching of bus request signals that are received by one of the processors coupled to the bus, and wherein a value of the control signal is determined by a number of processors coupled to the bus; wherein the logic stage outputs the control signal with a first value if one or two processors are coupled to the bus, and wherein the control signal with the first value causes the second switching element to pass a BREQ#[ 0 ] signal from the first bus line to a BR#[ 1 ] pin of a second processor, if two processors are coupled to the bus; wherein the logic stage outputs the control signal with a second value if more than two processors are coupled to the bus, wherein the control signal with the second value causes the second switching element to pass a BREQ#[ 2 ] signal from the third bus line to the BR#[ 1 ] pin of the second processor, and wherein the control signal with the second value causes the first switching element to pass the BREQ#[ 0 ] signal from the first bus line to a BR#[ 3 ] pin of the second processor, if more than two processors are coupled to the bus.