Patent ID: 8640066

Claim:
A method of designing an integrated circuit, the method comprising: with a processor receiving a first netlist of a first partition block for a top level of a hierarchical design of an integrated circuit, the first partition block including one or more circuits and one or more pins coupled together; analyzing each of the one or more pins of the first partition block for an attribute associated with the pin indicating a timing exception, including analyzing each sub-property timing exception of each phase attribute of each pin of the first partition block; and if a timing exception other than false path is indicated, then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block, wherein the internal timing pin is a multiphase timing pin and adds a timing exception constraint into a file in response to each timing exception.