Patent ID: 8867695

Claim:
An apparatus comprising: a prescalar counter configured to repeatedly increment once for each cycle of a clock signal at a first frequency and reset upon reaching a threshold counter value, wherein the prescalar counter further comprises toggling logic configured to generate a clock pulse of a global time base signal upon each reset of the prescalar counter; and a frequency divider configured to divide the global time base signal into a plurality of separate clock signals with each of the separate clock signals having a different frequency and provide, to each of a plurality of timers, one of the separate clock signals, and wherein each of the plurality of timers is associated with one of a plurality of components in a system that includes the apparatus, and wherein a first clock signal of the plurality of separate clock signals is provided to a first timer of the plurality of timers, the first clock signal having a frequency that is based on a first period of time corresponding to a first component of the plurality of components, wherein the first component is associated with the first timer, and wherein the first period of time, when elapsing without activity from the first component, indicates a potential failure of the first component, and wherein the first timer is configured to interrupt a processor in the system responsive to the first timer reaching the first period of time.