Patent ID: 7378343

Claim:
A dual damascene process, comprising: providing a substrate having thereon a base layer, a lower conductive layer inlaid into said base layer, and a lower cap layer covering said base layer and said inlaid lower conductive layer; depositing a dielectric layer on said lower cap layer; depositing a TEOS-based silicon oxide cap layer on said dielectric layer, said TEOS-based silicon oxide cap layer having a carbon content lower than 1×10 19 atoms/cm 3 ; depositing a metal hard mask on said TEOS-based silicon oxide cap layer; etching a trench recess into said metal hard mask and said TEOS-based silicon oxide cap layer; etching a partial via feature into said TEOS-based silicon oxide cap layer and said dielectric layer through said trench recess; and etch transferring said trench recess and said partial via feature into said dielectric layer, thereby forming a dual damascene opening therein, which exposes a portion of said lower conductive layer.