Patent ID: 7664908

Claim:
A semiconductor memory device comprising a memory array; a set of write registers; an input buffer sequentially receiving a series of write data during a burst cycle, and writing said write data into associated ones of said write registers; a write release register containing a set of write release flags associated with said write registers; a write release register controller asserting associated ones of said write release flags in response to said write data being written into said associated ones of said write registers; a write amplifier writing said write data contained in said write registers associated with asserted ones of said write release flags-into said memory array when said burst cycle is aborted in response to a control signal, and a register initialize signal generator providing a register initialize signal for said write release register, wherein said write amplifier is designed to write a complete set of said write data contained in all of said write registers when said burst cycle is not aborted, wherein said set of write release flags are negated when said burst cycle is initiated, wherein said register initialize signal is activated before said burst cycle is initiated, and wherein said write release register negates all of said write release flags in response to said register initialize signal being activated.