Patent ID: 8056036

Claim:
A method of designing a semiconductor integrated circuit based on a test point insertion technique, said method comprising: selecting a target node from a plurality of nodes included in a design circuit, as executed by a processing unit on a computer; inserting a test point at said target node; designating a delay time with respect to a test point path that includes a path connected to said test point; and laying out said design circuit such that a delay time of said test point path becomes said designated delay time, wherein said selecting the target node comprises: calculating delay times of fan-in paths and fan-out paths with respect to each of said plurality of nodes; and selecting said target node from said plurality of nodes based on said calculated delay times, wherein said selecting said target node from said plurality of nodes based on said calculated delay times comprises: calculating a priority parameter with respect to each of said plurality of nodes, said priority parameter depending on a minimum value of said calculated delay times; wherein said priority parameter is a difference between a maximum value and a minimum value of said calculated delay times.