Patent ID: 7615418

Claim:
A method of manufacturing a semiconductor structure comprising: forming, simultaneously, a layered structure with an underlying stress inducing material in a p-type field-effect-transistor (PFET) channel region and a n-type field-effect-transistor (NFET) channel region, wherein the layered structure with the underlying stress inducing material comprises a top layer of Si of uniform thickness and the underlying layer of SiGe; forming on the top layer of Si of uniform thickness sidewall spacers of different sizes on NFET and PFET regions; and etching an island in the NFET channel region and the PFET channel region comprising a channel length corresponding to the different sizes of the sidewall spacers, wherein the channel length of the NFET creates a higher resultant stress component in the NFET channel region than the PFET channel region; and forming a stress inducing material in etched portions of the PFET channel region creating an opposite stress component in the PFET channel region than in the NFET channel region.