Patent ID: 7190339

Claim:
A ferroelectric memory device comprising: a memory cell array region divided into a plurality of block regions; a plurality of wordlines arranged in parallel along a first direction within the memory cell array region; a plurality of bitlines arranged in parallel along a second direction intersecting the first direction, within the memory cell array region; a plurality of sub-bitlines provided for each of the bitlines in each of the block regions; a sub-bitline select switch provided between each of the sub-bitlines and corresponding one of the bitlines; a plurality of ferroelectric memory cells respectively disposed at intersections between the sub-bitlines and the wordlines; a first driver section which drives the wordlines and the sub-bitline select switches; and a second driver section which drives the bitlines, wherein the first driver section selects one of the wordlines sequentially in the second direction, and turns on the sub-bitline select switches connected to the sub-bitlines intersecting the selected one of the wordlines; and wherein the number of the wordlines in each of the block regions is set equal to or less than a predetermined limit number of times for preventing excessive relaxation of the ferroelectric memory cells.