Patent ID: 8416601

Claim:
A phase change memory apparatus, comprising: a plurality of sub blocks; a plurality of latch controllers, wherein each of the plurality latch controllers is coupled to the plurality of sub blocks and transmits data outputted from the coupled sub blocks in response to a latch enable signal and a sub-block selection signal which is generated based on an address of the at least one of the sub blocks provided in response to a read or a write commands, wherein the plurality of the latch controllers is connected to the latch enable signal and sub-block selection signal; a latch block coupled in common with the plurality of latch controllers, and configured to latch data outputted from one of the latch controllers; and a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal, wherein the comparison signal controls a write driver controller.