Patent ID: 7439118

Claim:
A method of manufacturing a semiconductor integrated circuit said method comprising the steps of: (A) forming a logic part and a memory array part in a semiconductor substrate the logic part and the memory array part each including (1) an N channel type field effect transistor comprising gate parts, channel regions and source/drain regions, and (2) a P channel type field effect transistor comprising gate parts, channel regions and source/drain regions; (B) forming a first insulation film having a tensile stress on an entire surface of the semiconductor substrate with said logic part and said memory array part formed therein and forming a second insulation film on said first insulation film; (C) selectively removing said second insulation film and said first insulation film present on an upper side of a region of said P channel type field effect transistor in said logic part; (D) forming a third insulation film having a compressive stress on a whole surface; and (E) selectively removing said third insulation film present on an upper side of a region of said N channel type field effect transistor in said logic part and an upper side of a region of said N channel type field effect transistor in said memory array part and an upper side of a region of said P channel type field effect transistor in said memory array part; (G) applying ion implantation for relaxation of tensile stress to said first insulation film on the region of said P channel type field effect transistor in said memory array subsequent to step (E).