Patent ID: 8266412

Claim:
A hierarchical store buffer included in a hierarchical microprocessor including a plurality of execution clusters, the hierarchical store buffer comprising: a second-level store buffer that includes a plurality of entries, the second-level store buffer configured to: receive data values to be written to a memory subsystem from the plurality of execution clusters; store the received data values in at least one of the plurality of entries prior to writing the data values to the memory subsystem; and store a definition time reflecting a time at which a respective entry of the plurality of entries is written into and a kill time reflecting another time at which another entry of the plurality of entries that has a matching same address as the respective entry is subsequently written into, wherein the second-level store buffer includes a segmented sequential data structure, the segmented sequential data structure segmented into a plurality of partitions with one or more partitions restricted to a particular address range, a respective partition of the plurality of partitions associated with a respective definition time of a particular entry of the plurality of entries, with the particular entry comprising an oldest entry of the respective partition of the plurality of partitions; and a plurality of first-level store buffers each operatively coupled with the second-level store buffer, each first-level store buffer being included in a respective execution cluster, the first-level store buffers each configured to: receive data values to be written to the memory subsystem from one or more execution units of the respective execution cluster; and store the received data values in a respective first-level store buffer prior to copying the data values to the second-level store buffer, wherein the plurality of first-level store buffers and the second-level store buffer are collectively configured to: copy the stored data values from the first-level store buffers to the second-level store buffer; compare memory subsystem addresses of store buffer entries with a memory subsystem address of a memory load instruction; provide a data value from a youngest store buffer entry subsequent to scheduling of the memory load instruction; determine a youngest entry, for each of multiple partitions of the plurality of partitions, that matches a memory subsystem address of another memory load instruction; and exclude one or more partitions of the plurality of partitions from a determination of the youngest entry based at least partially on a load timestamp of the other memory load instruction and respective definition times associated with respective partitions of the plurality of partitions.