Patent ID: 8329573

Claim:
A method of fabricating a wafer level integration module according to a construction whereby semiconductor functional device fabrication is carried out only after interconnect structures are processed on a bare wafer, the fabrication and processing including forming the interconnect structures in a first side of the wafer; depositing a first insulation layer on the first side of the wafer; depositing a first conductive layer on the insulation layer, the first conductive layer filling the interconnect structures so as to contact the first insulation layer on the walls of the interconnect structures, the first conductive layer in the interconnect structures forming interconnection contacts on the first side of the wafer and interconnection vias in the wafer; exposing the first conductive layer including the interconnection contacts on the first side of the wafer; fabricating a semiconductor functional device on the first side of the wafer, the semiconductor functional device interconnected with the interconnection contacts during the fabricating the semiconductor functional device; exposing from the second side of the wafer, portions of the first conductive layer associated with the interconnection vias, the method comprising: selectively removing a portion of the first conductive layer to form interconnection via redistribution connection structures; and filling the interconnection via redistribution connection structure with a low resistivity material to form low resistivity redistribution interconnect with the semiconductor functional device through the first conductive layer.