Patent ID: 8232195

Claim:
A method of fabricating a back end of the line (BEOL) interconnect structure of a semiconductor, the method comprising: depositing a noble metal layer onto an intermediate interconnect structure, wherein the intermediate interconnect structure includes an opening disposed between two top surfaces of dielectric material wherein the opening includes a bottom surface; sputter-etching the noble metal layer on the two top surfaces and the bottom surface to at least substantially thin down the noble metal layer wherein the sputter-etched noble metal layer comprises a first thickness on the bottom surface and the sputter-etched noble metal layer comprises a second thickness on the two top surfaces wherein second thickness is less than the first thickness; depositing a conductive wiring material to fill the opening by electroplating; and polishing the intermediate interconnect structure such that the sputter-etched noble metal layer and the conductive wiring material are coplanar with the two top surfaces of dielectric material of the intermediate interconnect structure.