Patent ID: 8578256

Claim:
An apparatus comprising a decoder for decoding error-correction encoded codewords, the decoder comprising: a check-node unit adapted to: receive an initial set of initial values generated by an upstream processor, wherein: the initial set corresponds to a first error-correction-encoded codeword; and each initial value in the initial set corresponds to a different bit of the first error-correction-encoded codeword; and initiate generating check-node messages based on one or more initial values in the initial set before the upstream processor generates all of the initial values in the initial set; a combiner adapted to generate an updated set of updated values corresponding to the bits of the first error-correction-encoded codeword based on the check-node messages and the initial values generated by the upstream processor; and a parity-check calculator adapted to determine whether the updated values correspond to a valid codeword, wherein: the apparatus further comprises the upstream processor; and the upstream processor transmits the initial set of initial values to the decoder without storing all of the initial values in the initial set in memory.