Patent ID: 7482227

Claim:
A method for manufacturing a flash memory, comprising providing a substrate with a first sacrificial layer formed on said substrate, a second sacrificial layer formed on said first sacrificial layer, a first hard mask layer formed on said second sacrificial layer and a first trench exposing part of said substrate; filling said first trench with a first oxide layer; removing said first hard mask layer and said second sacrificial layer to form a second trench and expose said first sacrificial layer; forming a spacer as a STI oxide spacer surrounding said first oxide layer to allow the spacer to engage with the substrate and to allow the second trench to have an inverted trapezoidal shape; forming a floating gate oxide layer on said substrate; filling said second trench with a floating gate poly-Si layer; and forming a second hard mask layer on top of said first oxide layer and on said floating gate poly-Si layer.