Patent ID: 8841931

Claim:
A method of preparing a wafer test system, comprising: determining a probe card design to test a first wafer having a first type of device and a second wafer having a second type of device, wherein the second type of device having a different signal scheme, wherein the determining the design includes: defining a space transformer having first power/ground lines and first signal lines embedded therein, wherein the first power/ground lines are disposed in an edge region of the space transformer and the first signal lines are disposed in a central region of the space transformer, the edge region surrounding the central region, and defining a printed circuit board (PCB) bonded to the space transformer and embedded with second power/ground lines and second signal lines that are coupled to the first power/ground lines and signal lines, respectively, and wherein the second power/ground lines are disposed in an epoxy material edge region of the PCB and the second signal lines are disposed in an epoxy central region of the PCB, the edge region of the PCB surrounding the central region of the PCB; fabricating a first and a second probe card according to the design; adding a first set of conductive lines to the first probe card such that the first set of conductive lines are positioned above the PCB and each conductive line having two ends attached to a surface of the PCB remote to the space transformer, wherein the adding the conductive lines is based on the signal scheme of the first device; adding a second set of conductive lines to the second probe card such that the second conductive lines are positioned above the PCB and each conductive line having two ends attached to a surface of the PCB remote to the space transformer, wherein the adding the conductive lines is based on the signal scheme of the second device.