Patent ID: 6873392

Claim:
A manufacturing method of an array substrate for a liquid crystal display device, comprising: forming a plurality of gate lines, a plurality of gate electrodes, and a plurality of odd-numbered and even-numbered gate pads on a substrate; forming a gate insulating layer on the plurality of gate lines, the plurality of gate electrodes and the plurality of odd-numbered and even-numbered gate pads; forming a plurality of active layers on the gate insulating layer; forming a plurality of ohmic contact layers on the plurality of active layers; forming a plurality of data lines, a plurality of odd-numbered and even-numbered data pads, a plurality of source electrodes, and a plurality of drain electrodes on the plurality of ohmic contact layers; forming a first shorting bar electrically connected to each of the odd-numbered gate pads; forming a second shorting bar electrically connected to each of the even-numbered gate pads; forming a third shorting bar electrically connected to each of the odd-numbered data pads; forming a fourth shorting bar electrically connected to each of the even-numbered data pads; forming first, second, third, and fourth connection lines electrically connected to the first, second, third, and fourth shorting bars, respectively; forming first, second, third, and fourth test pads connected to the first, second, third, and fourth connection lines, respectively; forming a passivation layer on the plurality of data lines, the plurality of odd-numbered and even-numbered data pads, the plurality of source electrodes, and the plurality of drain electrodes; and forming a plurality of pixel electrodes on the passivation layer, wherein the steps of forming the first shorting bar, the third shorting bar, the first, second, third, and fourth connection lines, and the first, second, third, and fourth test pads arc simultaneously performed with the steps of forming the plurality of gate lines, the plurality of gate electrodes, and the plurality of odd-numbered and even-numbered gate pads, and wherein the steps of forming the second shorting bar and the fourth shorting bar are simultaneously performed with the step of forming the plurality of data lines, the plurality of odd-numbered and even-numbered data pads, the plurality of source electrodes, and the plurality of drain electrodes.