Patent ID: 7560785

Claim:
A semiconductor device comprising; a bulk semiconductor substrate; a first fin of a first finFET formed in the substrate, the first fin having a first height, the first fin including a first channel region and first source/drain regions on opposing sides of the first channel region, the first fin being in direct contact with a semiconductor material of the underlying substrate; a second fin of a second finFET formed in the substrate, the second fin having a second height, the second fin including a second channel region and second source/drain regions on opposing sides of the second channel region, the first height being different than the second height, the first fin and the second fin having a co-planar top surface; a first pair of trenches in the substrate, the first pair of trenches having a first depth, portions of the substrate between adjacent trenches of the first pair of trenches forming the first fin; a second pair of trenches in the substrate, the second pair of trenches having a second depth, portions of the substrate between adjacent trenches of the second pair of trenches forming the second fin, the second depth being substantially the same as the first depth; a first dielectric layer along a bottom of each of the first pair of trenches; and a second dielectric layer along a bottom of each of the second pair of trenches, the second dielectric layer having a thickness different than the first dielectric layer.