Patent ID: 8053373

Claim:
A method for fabricating a semiconductor structure comprising: nitriding, while using a thermal nitriding method, an oxide layer located upon a base semiconductor substrate to provide a nitrided oxide layer having a first nitrogen gradient that peaks at an interface of the nitrided oxide layer with the base semiconductor substrate; nitriding, while using a plasma nitriding method, the nitrided oxide layer to provide a twice nitrided oxide layer having a second nitrogen gradient that peaks at the exposed surface of the twice nitrided oxide layer; laminating a surface semiconductor layer upon the twice nitrided oxide layer to contact the second nitrogen gradient; and forming at least one transistor upon and in said surface semiconductor layer, wherein said forming the at least one transistor comprises forming a gate material stack on the surface semiconductor layer, and forming a source region and a drain region within the surface semiconductor layer at a footprint of the gate material stack, wherein a channel region is interposed between the source region and the drain region, and said channel region is located directly beneath the gate material stack.