Patent ID: 7940127

Claim:
A digital phase lock loop, comprising: a digitally controlled oscillator controlled by an oscillator tuning word to generate a variable signal, wherein the oscillator tuning word comprises a first tuning word and a second tuning word, wherein a second tuning word adjustable frequency range of the digitally controlled oscillator is broader than a first tuning word adjustable frequency range of the digitally controlled oscillator; a phase detector arranged to measure a phase error between the variable signal and a reference signal; and a loop filter arranged to generate the oscillator tuning word in response to the phase error, wherein the loop filter comprises: a plurality of low pass filter stages, including a front low pass filter and a back low pass filter; and a modification circuit arranged to adjust the second tuning word based on an output from at least one of the front low pass filter and the back low pass filter, wherein the modification circuit comprises a first decision circuit configured to output a first variation based on the filter output of the back low pass filter, a second decision circuit configured to output a second variation based on the filter output of the front low pass filter, and an accumulator configured to adjust the second tuning word based on accumulated differences between the first variation and the second variation.