Patent ID: 8018768

Claim:
A non-volatile static random access memory (NVSRAM) device including a plurality of unit memory cells arranged in an array, wherein each of the plurality of unit memory cells comprises: a volatile circuit for retaining a bit data at a data true node and a data complement node when an external power is applied; and a non-volatile circuit for retaining the bit data after the power has been removed from the volatile circuit, the non-volatile circuit comprising: an inverter circuit including: an input end coupled to the data complement node; and an output end coupled to the data true node; and a non-volatile erasable programmable memory (NVEPM) circuit including: a programmable transistor for storing data from the data complement node in response to an interruption of power supplied to the volatile circuit; a store transistor for selectively coupling the programmable transistor to the data complement node in response to a change in state of power supplied to the volatile circuit; and a recall transistor for selectively coupling the programmable transistor to a first power supply so as to recall the data stored in the storage transistor in response to supply of power to the volatile circuit.