Patent ID: 8719506

Claim:
An apparatus comprising: a first port controller coupled to receive transactions and corresponding quality of service (QoS) parameters on a first port, wherein the first port is configured to detect high priority QoS transactions and to transmit an increment indication to a second clock domain, wherein the first port controller is operable in a first clock domain; a memory port controller coupled to receive the increment indication from the first port controller, the memory port controller operable in the second clock domain and coupled to a memory port to communicate with a memory controller; and a cache interface unit coupled to the memory port controller and the first port controller, and wherein the cache interface unit is configured to detect high priority QoS transactions that complete in the cache and configured to transmit a decrement indication to the second clock domain; and wherein the memory port controller is coupled to receive the decrement indication, and wherein the memory port controller is configured to maintain a count of outstanding high priority QoS transactions responsive to the increment indication and the decrement indication, and wherein the memory port controller is configured to push transactions on the memory port at a higher priority responsive to the count being non-zero.