Patent ID: 7283401

Claim:
A nonvolatile memory cell formed on a substrate comprising: a floating gate placed over a channel region of said memory cell and between a source and a drain region of said memory cell, said floating gate aligned with an edge of said source region and an edge of said drain region and having a width constrained by a width of said edge of said source and said edge of said drain to prevent said floating gate from having wings overlapping a shallow trench isolation region bounding said nonvolatile memory cell; and a gating transistor having a source connected to said drain region, a drain, and a gate connected to a select gate signal to selectively apply a bit line voltage signal to the drain region; wherein said memory cell has a relatively small coupling ratio of capacitance formed by a control gate placed over said floating gate to a total capacitance of said floating gate and said control gate, wherein said coupling ratio is less than 50%, and wherein said memory cell is in communication with an erasing apparatus to remove electrical charge from said floating gate, said erasing apparatus comprising: means for applying a very large negative voltage from approximately −15V to approximately −22V to said control gate, wherein said erasing apparatus has a duration from approximately 1 ms to approximately 1 s.