Patent ID: 8422620

Claim:
A shift register comprising: a first shift registering unit for generating a first trigger signal at a first output terminal, wherein the first shift registering unit comprises a first pull-down circuit; and a second shift registering unit for receiving the first trigger signal and generating a second trigger signal at a second output terminal, wherein the first trigger signal and the second trigger signal are sequentially asserted, and the second shift registering unit comprises a second pull-down circuit; wherein the first pull-down circuit and the second pull-down circuit perform pull-down operations at different times; wherein when the first pull-down circuit does not perform the pull-down operation, the second pull-down circuit performs pull-down operations to the first output terminal; wherein each of the first and second shift registering units comprises: a pull-up control circuit; and a pull-up circuit, coupled to the pull-up control circuit at a first node and controlled by the pull-up control circuit, for receiving a first clock signal and generating an output signal; wherein the pull-up circuit of the first shift registering unit generates the corresponding output signal at the first output terminal to serve as the first trigger signal, and the pull-up control circuit of the second shift registering unit receives the first trigger signal; and wherein for the first and second shift registering units, each of the first and second pull-down circuits comprises: a first transistor having a control terminal and an input terminal both receiving a second clock signal and an output terminal; a second transistor having a control terminal coupled to the output terminal of the first transistor, an input terminal coupled to the corresponding first node, and an output terminal coupled to the corresponding first or second output terminal; a third transistor having a control terminal coupled to the output terminal of the first transistor, an input terminal coupled to the corresponding first or second output terminal, an output terminal coupled to a reference voltage source; and a fourth transistor having a control terminal coupled to the corresponding first node, an input terminal coupled to the output terminal of the first transistor, and an output terminal coupled to the reference voltage source, wherein a size of the fourth transistor is larger than a size of the first transistor.