Patent ID: 8209493

Claim:
A system comprising: two or more processor cores, each processor core associated with a queue occupancy monitor to monitor a last level cache pipeline request occupancy value for each processor core; and resource sharing logic coupled with the two or more processor cores, the resource sharing logic to determine a selected processor core, the selected processor core to have access to at least one resource based, at least in part, on the last level cache pipeline request occupancy value corresponding to the selected processor core; and a memory controller to control access to main system memory, the memory controller including dynamic random access memory (DRAM) throttle logic to determine whether the system is in DRAM throttling mode (DTM) and to provide an indication to the resource sharing logic if the system is in DRAM throttling mode, the memory controller to apply a pre-specified scheduling policy based on the occupancy value for each processor core in conjunction with the DTM to determine which requests from which cores are allowed to make progress.