Patent ID: 7295553

Claim:
A packet buffer having a configuration that reception packets are written to a data buffer and a scheduler adjusts a read order of the packets written to the data buffer according to a service class recognized by a classifying unit, and wherein said data buffer comprises: M memory banks capable of being accessed simultaneously; and a data access unit for accessing said memory banks in each memory cycle having a predetermined length, according to a predetermined number N or less of read commands and write commands; a write requesting unit for dividing each reception packet into at least one data block according to a predetermined data length, and for issuing write requests for the respective data blocks; a write-bank selecting unit for selecting different memory banks in response to N+1 consecutive write requests, respectively; a data writing unit for selecting, in each memory cycle, maximum N write requests from said write requests issued by said write requesting unit, the selecting being performed in issuance order, and for inputting, to said data access unit, a write command to the effect that each of data blocks corresponding to the selected write requests is to be written to said memory banks selected by said write-bank selecting unit; an address managing unit for managing information about said memory banks, and addresses of their storage areas where respective data blocks of each packet have been written; a primary read-bank selecting unit for receiving, in each memory cycle, read requests for N or less data blocks from said scheduler, and for selecting one or more memory bank(s) capable of being read in the same memory cycle from memory banks in which the data blocks specified by the respective read requests are stored, based on said information stored in said address managing unit; a secondary read-bank selecting unit for storing a read request which has not been achieved in each memory cycle, the read request being among read requests received in the same memory cycle from said scheduler, and for selecting a memory bank corresponding to the stored read request in the next memory cycle; and a data reading unit for selecting a predetermined number L or less of read requests from said read requests for the memory banks selected by said primary and secondary read-bank selecting units, and for inputting, to said data access unit, L or less read commands to the effect that respective data blocks are to be read from the memory banks corresponding to said read requests.