Patent ID: 8918689

Claim:
An integrated circuit comprising; an input node configured to receive a test clock input signal; circuitry configured to generate from said test clock input signal a plurality of test clock signals; and test circuitry configured to use said test clock signals in a test mode, wherein said circuitry is configured to generate said plurality of test clock signals and comprises a plurality of selector circuitry, each of said selector circuitry configured to receive said test clock input signal from the test clock input node, wherein each of said selector circuitry comprises a multiplexor, wherein said circuitry comprises a test clock selector configured to provide a test signal to each of said selector circuitry, wherein said test clock selector comprises a de-multiplexor, wherein said test clock selector has an input node configured to receive said test clock input signal and a plurality of output nodes coupled respectively to said plurality of selector circuitry, configured to provide said test clock signal, and wherein a first input of each of the multiplexors is directly coupled to the input node, and a second input of each of the multiplexors is directly coupled to a respective output of the de-multiplexor.