Patent ID: 8131936

Claim:
A method for implementing a combined data/coherency cache for a shared memory multi-processor, the combined data/coherency cache including a system cache with a number of entries, the method comprising: utilizing a system cache directory with a number of directory entries equal to the number of cache entries of the system cache, the utilizing comprising: designating two or more sub-entries for each directory entry, each of the sub-entries having a separate address, and only one of the two or more sub-entries for each directory entry includes a corresponding cache entry, wherein only one of the sub-entries for each directory entry indicates that data is available in the corresponding cache entry responsive to matching a requesting address to one of the separate addresses, the number of sub-entries determined by a multiple of the number of directory entries; wherein each directory entry comprises a corresponding sub-entry logic designator; and mapping one of the sub-entries for each directory entry to the system cache via the sub-entry logic designator, the sub-entry logic designator comprising a least recently used (LRU) logic designator, the LRU logic designator indicating which of the two or more sub-entries within the corresponding directory entry is least recently used.