Patent ID: 7524763

Claim:
A method for fabricating a wafer level chip scale package, the method comprising: providing a wafer including a first face, a second face, a plurality of integrated circuit (IC) chips having chip pads on the first face, and scribe lanes running between the IC chips; forming holes in the first face of the wafer such that the holes respectively penetrate through the chip pads; forming a base metal layer on the first face of the wafer such that the base metal layer covers inner surfaces of the holes; forming electrode metal layers respectively on the chip pads such that the electrode metal layers respectively fill the holes; grinding the second face of the wafer such that the electrode metal layers are exposed through the second face of the wafer; after grinding the second face of the wafer, attaching a temporary buffer tape to the base metal layer on the first face of the wafer; forming plated bumps respectively on the electrode metal layers exposed through the second face of the wafer; removing the temporary buffer tape from the first face of the wafer; selectively removing the base metal layer located between the electrode metal layers after removing the temporary buffer tape; and separating the wafer along the scribe lanes.