Patent ID: 6973468

Claim:
A data interpolating device, comprising: three stages of delay circuits for successively delaying discrete data sequentially inputted; and a multiplication/addition circuit that performs weighted addition of data outputted from the output stages of said three stages of delay circuits according to the value of a digital basic function and thereby determines interpolation data for said discrete data sequentially inputted, said multiplication/addition circuit comprising: a first multiplication unit for multiplying the output data of a first stage delay circuit by −1; a second multiplication unit for multiplying the output data of a second stage delay circuit by 8; a third multiplication unit for multiplying the output data of a third stage delay circuit by −1; a first switching circuit for selectively switching between the output data of said first stage delay circuit and the output data of said first multiplication unit; a second switching circuit for selectively switching between the output data of said third stage delay circuit and the output data of said third multiplication unit; and an adder for adding the output data of said second multiplication unit, the output data of said first switching circuit and the output data of said second switching circuit.