Patent ID: 7859880

Claim:
A semiconductor memory apparatus comprising: a first memory cell region including a plurality memory cells; a second memory cell region including a plurality memory cells, the second memory cell region positioned adjacent to the first memory cell region; a sub-local data bus coupled with some of the plurality of memory cells in each of the first and second memory cell regions, the sub-local data bus configured to execute data I/O operations of the first and second memory cell regions; a data bus region disposed between the first and second memory cell regions; a first local data bus disposed within the data bus region and configured to execute data I/O operations in communication with the sub-local data bus and a first data I/O sense amplifier; and a second local data bus also disposed within the data bus region and also configured to execute data I/O operations in communication with the sub-local data bus and a second data I/O sense amplifier.