Patent ID: 7345909

Claim:
A semiconductor memory cell comprising: a first inverter including a pair of CMOS field effect transistors that are coupled in series, that respectively have gate terminals, and that further have a first common connection node, said first inverter being adapted to be coupled between a power terminal and a ground terminal; a second inverter including a pull-up transistor adapted to be coupled to the power terminal, and a pull-down transistor coupled in series to said pull-up transistor, said pull-up and pull-down transistors having a second common connection node coupled to said gate terminals of said field effect transistors, and respectively having gate terminals coupled to said first common connection node; first and second read bit lines; first and second read access transistors, each of which selectively couples a respective one of said first and second read bit lines to a respective one of said first and second common connection nodes; a read word line coupled to said first and second read access transistors to control turn on and turn off activities of said first and second read access transistors; a switching transistor for selectively coupling said second inverter to the ground terminal; a write bit line; a write access transistor for selectively coupling said second common connection node to said write bit line; and a write word line coupled to said write access transistor to control turn on and turn off activities of said write access transistor.