Patent ID: 6996658

Claim:
A device accessible by a host processor for expanding access over a first bus to a second bus, said first bus and said second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, said device comprising: a link; a first circuit adapted to couple between said first bus and said link; and a second circuit adapted to couple between said link and said second bus, said first circuit and said second circuit each being independently operated as a PCI bridge and being operable to (a) send outgoing information serially through said link in a form different from that of said first bus and said second bus (b) approve an initial exchange between said first bus and said second bus in response to pending bus transactions having a characteristic signifying a destination across said device, and (c) allow said host processor, communicating through said first bus, to individually address different selectable ones of the bus-compatible devices on said second bus: (i) using on said first bus substantially the same type of addressing as is used to access devices on said first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on said second bus.