Patent ID: 7585705

Claim:
A method for preventing a gate oxide damage of a trench MOSFET during wafer processing while adding an electrostatic discharge (ESD) protection module atop the trench MOSFET, said ESD protection module having a bottom layer whose patterning process is known to cause the gate oxide damage to the trench MOSFET, the method comprises sequential steps: a) providing a wafer with a plurality of the trench MOSFETs fabricated thereon; b) providing an oxide layer on top of the wafer c) adding an isolation layer, capable of preventing the bottom layer patterning process from damaging the gate oxide of the trench MOSFET, over the oxide layer atop the wafer; d) providing an oxide layer over the isolation layer; e) adding and patterning the ESD protection modules atop the isolation layer; f) removing those portions of the isolation layer that are not beneath the ESD protection modules.