Patent ID: 8832391

Claim:
A semiconductor device, comprising: a data control unit configured to selectively process data for writing to a memory, the data control unit configured to enable a processing function from a group of processing functions based on a mode register command during a write operation, the group of processing functions including at least three processing functions; a pin associated with the group of functions; and wherein the data control unit is configured to selectively perform the enabled processing function based on a signal received on the pin; the group of processing functions includes a first function, a bus inversion function, and a data masking function; the data control unit includes, a first circuit configured to receive the data for writing and configured to selectively perform the first function on the data for writing based on a signal received by the pin if enabled by a first control signal; a data bus inversion circuit configured to receive the data for writing and configured to selectively invert the data for writing based on a signal received by the pin if enabled by a second control signal; a data masking circuit configured to receive the data for writing and configured to selectively mask the data for writing based on the signal received by the pin if enabled by a third control signal; and a control signal generation circuit configured to generate the first, second and third control signals based on the mode register command.