Patent ID: 8553443

Claim:
A memory device comprising a plurality of memory sets each including a data bit storage area, the memory device comprising: a one time programmable (OTP) memory including at least one OTP memory block and at least one pseudo-multi time programmable (MTP) memory block, the at least one OTP memory block including a first number of memory sets of the plurality of memory sets that comprise an OTP memory, the at least one pseudo-MTP memory block including a second number of memory sets of the plurality of memory sets that comprise a pseudo-MTP memory, wherein each of the second number of memory sets comprises at least one mark bit, the mark bit indicating the presence or absence of data, the memory device further comprising: an address search unit that refers to the mark bits of the second number of memory sets to obtain an identified address of the second number of memory sets in which most recent data is written; a writing unit that writes the data bit storage area of one memory set of the second number of memory sets whose address is indicated by the identified address; a reading unit that accesses the data bit storage area of one memory set of the second number of memory sets whose address is indicated by the identified address; and a mark bit writing unit that writes the mark bit of one memory set of the second number of memory sets whose address is indicated by the identified address, wherein the mark bit writing unit changes the value of mark bit at the identified address.