Patent ID: 8418114

Claim:
A mask formed by a method for generating mask data that is used for a method for manufacturing a semiconductor device, the method comprising the steps of: (a) setting a restriction region pattern that defines a restriction region; (b) setting dummy patterns that define the dummy wiring layers; (c) reversing the restriction region pattern; (d) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded and prevented from being formed; and (e) forming the dummy patterns on the semiconductor device according to the restriction region pattern, wherein the semiconductor device includes a first wiring layer defining a first direction and a second direction perpendicular to the first direction and a plurality of dummy wiring layers provided in an identical level as the first wiring layer, and wherein each of the dummy wiring layers has a generally square shape in plan, adjacent ones of the dummy wiring layers that are disposed next to one another in the first direction are spaced a first distance from one another, the first distance being about a half of a side of each of the dummy wiring layers, and the adjacent ones of the dummy wiring layers that are disposed next to one another in the first direction are offset by a second distance from one another in the second direction, the second distance being about a half of a side of each of the dummy wiring layers.