Patent ID: 7566652

Claim:
A method of fabricating a semiconductor device comprising: forming a metal line in a first dielectric layer; forming a second dielectric layer over the metal line; forming a first conductive via in the second dielectric layer and on the metal line; forming a second conductive via in the second dielectric layer and on the metal line at a distance from the first conductive via; forming an electrically isolated conductive via in the second dielectric layer and on the metal line between the first and second conductive via; forming a first conductive line over in contact with the first conductive via; forming a second conductive line over and in contact with the second conductive via; wherein an electric path is established by the first conductive line, the first conductive via, the metal line, the second conductive via, and the second conductive line; and wherein the electrically isolated conductive via remains electrically isolated during device operation and mitigates void formation in the metal line.