Patent ID: 6885105

Claim:
A semiconductor device comprising: a silicon substrate having an n-type region; a gate insulating film formed on the n-type region, said gate insulating film being comprised from nitrogen-containing silicon oxide; a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon; p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode; side wall spacers formed on side walls of said gate electrode, using silicon oxide; an interlayer insulating film having a planarized surface layer of silicon oxide and covering said gate electrode and side wall spacers; a wiring trench formed in said interlayer insulating film from the planarized surface layer to an inside thereof; a copper wiring pattern including an underlying barrier layer and an upper level copper region, said copper wiring pattern being filled in said wiring trench; and a silicon carbide layer formed on the planarized surface layer of said interlayer insulating film to cover the upper level copper region of said copper wiring pattern.