Patent ID: 8736757

Claim:
A frame rate conversion circuit comprising: selection circuitry that receives a plurality of video signals and selects a video signal of the plurality of video signals; a scaler positioning module that routes a first video signal path through a first scaler and a second video signal path through a second scaler, the scaler positioning module comprising: a first scaler slot positioned within the first video signal path and configured to receive the selected video signal; and a second scaler slot positioned within the second video signal path and configured to receive a video signal retrieved from storage, wherein the first scaler is coupled to the first scaler slot and the second scaler is coupled to the second scaler slot; wherein the first scaler is configured to: scale the selected video signal; write the scaled selected video signal to a memory via a memory interface; and output the scaled selected video signal to a first input of a selector; and wherein the second scaler is configured to: read the scaled selected video signal from the memory via the memory interface; further scale the read scaled selected video signal; and provide the further scaled selected video signal to a second input of the selector.