Patent ID: 8713384

Claim:
A semiconductor apparatus comprising first and second chips sharing first and second data channels, wherein the first and second chips output normal data of the respective chips through the first and second data channels in a normal operation, and the first chip outputs test data of the first chip through the first data channel, and the second chip outputs test data of the second chip through the second data channel in a test operation, wherein the first chip comprises a first data selection unit configured to output the normal data of the first chip to a plurality of first-chip data lines, respectively, in the normal operation, and output the test data of the first chip to the plurality of first-chip data lines in the test operation; and a first data output unit configured to output the normal data of the first chip, which are transmitted through the plurality of data lines, through the first and second data channels, respectively, in the normal operation, and output the test data of the first chip, which are transmitted through the plurality of data lines, through the first data channel.