Patent ID: 8241954

Claim:
A method of making a wafer level chip scale package, comprising: providing a first semiconductor die having an active surface at a first level; disposing a second semiconductor die over the first semiconductor die, the second semiconductor die having an active surface at a second level; forming a first insulation layer over the first semiconductor die and extending from the first level to the second level; removing a portion of the first insulation layer over a contact pad formed on the first semiconductor die to create an opening such that a top surface of the first insulation layer is substantially coplanar with the second level from the opening to the second semiconductor die; forming a first conductive layer over the first insulation layer, the first conductive layer following a contour of the first insulation layer and extending into the opening to provide electrical connection between the contact pad on the first semiconductor die at the first level and a contact pad on the second semiconductor die at the second level vertically offset from the first level; disposing a third semiconductor die having an active surface over the second semiconductor die and over a portion of the first conductive layer; forming a second conductive layer over the third semiconductor die at a third level, the second conductive layer following a contour of the first conductive layer between the first and second levels and extending into the opening for electrical vertical interconnection forming a second insulation layer over the second conductive layer and extending into the opening; and forming a bump on a surface of the wafer level chip scale package that electrically connects to the first and second conductive layers and first, second, and third semiconductor die.