Patent ID: 7162671

Claim:
A method of testing response characteristics of a memory circuit which has a plurality of signal nodes for receiving an operation control signal for controlling a memory selecting operation and an operation timing signal, and a word-line selecting operation, a sense amplifier operation following the word-line selecting operation, the memory selecting operation including a data transmitting operation, and the termination of the memory selecting operation including the termination of the word-line selecting operation being affected on the basis of an internal operation timing signal, the internal operation timing signal being generated based on the operation control signal, comprising the steps of: lowering a frequency of the operation timing signal at the time of a test operation by a testing apparatus to a level lower than at the time of a normal memory operation in correspondence with the performance of said testing apparatus; and changing a period of the test operation of said memory circuit by the internal operation timing signal made by combining the operation control signal at the time of the test operation with a timing signal used exclusively for testing which is supplied externally into said memory circuit and changing a phase of the timing sianal to control a reset timing of the internal operation timing signal.