Patent ID: 8238501

Claim:
A burst-mode clock and data recovery circuit using phase selecting technology, comprising: a phase-locked loop circuit for providing a plurality of fixed clock signals, each of which comprises a clock phase; an oversampling phase selecting circuit, coupled to the phase-locked loop circuit, for using the clock signals to detect a data edge of received data signal by counting a number of times that the data edge of the data signal falls between two of the fixed clock signals, and selecting the clock phase to be locked according to the position of the data edge, wherein the oversampling phase selecting circuit comprises: an amplifier for amplifying the received data signal; a sampler, coupled to the amplifier, for sampling a state of the data signal using the clock signals; and a phase selecting control circuit, coupled to the sampler, for determining the data edge of the data signal according to the state sampled by each of the clock signals and selecting the clock phase to be locked by the delay-locked loop circuit, wherein the phase selecting control circuit comprises: a plurality of phase detectors, each of which receives one of the data signal and the clock signals, for determining the two clock signals which the data edge of the data signal is fallen between; a voting circuit, coupled to the phase detector, for counting the number of times that the data edge of the data signal falls between the clock signals of the phase detectors, so as to obtain a voting result; and a control circuit, coupled to the voting circuit, for selecting one of the phase detectors and using the same as the phase detector to be used by the delay-locked loop circuit according to the voting result; and a delay-locked loop circuit, coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, for comparing a data phase of the data signal with the clock phase to be locked so as to control the data phase of the data signal to be delayed for a delay time period until the data phase is locked to the clock phase.