Patent ID: 7839682

Claim:
An array of non-volatile memory cells arranged in a plurality of rows and columns, wherein each memory cell is formed in a semiconductor substrate of a first conductivity type, with a first region of a second conductivity type along the surface of the substrate, a second region of the second conductivity type along the surface of the substrate, spaced apart from the first region defining a channel region therebetween, a floating gate over a portion of the channel region, a coupling gate over the floating gate, a word gate over another portion of the channel region and adjacent to and separated from the floating gate, and an erase gate over the second region adjacent to and separated from the floating gate, wherein cells in the same column have a common bit line connected to the first regions of memory cells in the same column, said array comprising: a first and second sub arrays of memory cells arranged adjacent to one another in the same row; a first decoder to one side of the first sub array in the same row as the first sub array; a second decoder to another side of the second sub array in the same row as said second sub array; a first coupling gate line connected to the second decoder and to only the coupling gate of the memory cells in the first sub array; a second coupling gate line, different from the first coupling gate line, connected to the second decoder and to only the coupling gate of the memory cells in the second sub array; a word line connected to the first decoder and to the word gate of the memory cells of said first and second sub arrays; a first erase gate line connected to the second decoder and to only the erase gate of the memory cells of said first sub array; and a second erase gate line connected to the second decoder and to only the erase gate of the memory cells of said second sub array.