Patent ID: 8687436

Claim:
A computer system comprising: a central processing unit coupled to and configured to communicate with a memory controller by at least an address bus and a data bus, wherein the memory controller is further coupled to one or more memory devices, wherein the memory controller introduces a delay between outputting a memory address for a write access and outputting data for said write access by delaying the data for said write access; the memory controller also removing said delay between said memory address for said write access and said data for said write access after receipt of said memory address for said write access and said data for said write access; the memory controller transferring said memory address for said write access to one or more said memory device and transferring said data for said write access to one or more said memory devices, wherein when a memory read access is to the same memory location as a pending memory write access, the data for the memory read access is provided by a pipeline register and not by the memory location, and when the memory read access is not to the same memory location as the pending memory write access, the data for the memory read access is provided by the memory location.