Patent ID: 8316335

Claim:
A method of facilitating placement of logic cells in an integrated circuit design layout, comprising: parsing hardware function operation descriptions of a circuit in hardware description language to identify multiple instantiations of at least one type of logic function, each logic function type of the at least one logic function type to be implemented by a plurality of logic cells; performing by one or more processors, without shape restriction, a first synthesis on each logic function type of the at least one logic function type to produce therefrom an irregular-shaped logic unit layout comprising a plurality of logic cells; establishing at least one irregular-shaped blocking mask, each irregular-shaped blocking mask corresponding to a respective irregular-shaped logic unit layout produced by the first synthesis of each logic function type of the at least one logic function type; creating a partial circuit layout by placing each irregular-shaped blocking mask multiple times therein corresponding to the multiple instantiations of the respective logic function type of the at least one logic function type; and performing by the one or more processors, employing the partial circuit layout, a second synthesis on the balance of the hardware function operation descriptions of the circuit outside of the multiple instantiations of the at least one logic function type to place logic cells in the partial circuit layout about the irregular-shaped blocking masks, wherein the irregular-shaped blocking masks facilitate producing the integrated circuit design layout.