Patent ID: 8239793

Claim:
A routing design method comprising: determining with a computer device whether a design rule check (DRC) error of one of first and second routing portions is present in a system in package (SiP) having large scale integrated circuit (LSI) chips stacked on a package board that has via holes formed to connect upper and lower routes and having the first and second routing portions that are connected to each other via bonding wires and selecting the DRC error when the DRC error is present, specifying a plurality of nets associated with the selected DRC error, removing at least part of routes of the specified nets, changing bonding wire allocations of the specified nets, rerouting nets that are subjected to the route removal and bonding wire allocation changing while occurrence of a DRC error is prevented after the removal and allocation changing, and determining whether a result of the rerouting is accepted, wherein correction is accepted if improvement is made when the DRC error is eliminated at time of determining whether the result of rerouting is accepted, and correction is not accepted and a state before correction is restored when the DRC error is not improved.