Patent ID: 7984203

Claim:
A computer hardware apparatus to receive a direct memory access (DMA) request from an input/output (IO) device, the computer hardware apparatus comprising: an input/output memory management unit (IOMMU) coupled to a Virtual Machine Monitor (VMM), the IOMMU including: a hardware DMA remapping circuit to: assign the IO device to a specific guest virtual machine (VM) domain; and provide an address translation for the DMA request via a DMA remapping structure including an address window (AW), address window page tables (AWPTs), and an address window pointer table (AWPTR) associated with the specific guest VM domain; an input/output translation lookaside buffer (IOTLB) to cache the address translation associated with the specific guest virtual machine domain; a logic to determine from the access request whether the address translation for the access request exists in the IOTLB; and a context-cache for further determining the address translation if the logic determined the access request is non-existent in the IOTLB, wherein the hardware DMA remapping circuit to provide the address translation for the DMA request based, at least in part, on the AWPTs and the IOTLB, and based on determining whether the address translation exists in the IOTLB, and wherein the hardware DMA remapping circuit to provide the address translation for the DMA request for the address of the IO device to be directly mapped to a respective guest VM via the hardware DMA remapping circuit.