Patent ID: 7492637

Claim:
A nonvolatile semiconductor memory device comprising: a cell array including, a plurality of word lines, a plurality of bit lines configured to intersect the word lines, a plurality of cell transistors, each of the plurality of cell transistors being arranged at an intersections of a word line and a bit line, having a drain connected to the bit line and a gate connected to the word line, and a plurality of source lines connected to sources of the plurality of cell transistors; a program-voltage modulation unit for modulating a program voltage based on a number of cell transistors selected for programming and providing the modulated program voltage to one of the plurality of source lines; and a data input unit for inputting data to the plurality of cell transistors and to the program-voltage modulation unit, wherein the program-voltage modulation unit modulates the program voltage through a plurality of program current paths having different resistances in response to the data from the data input unit.