Patent ID: 8351277

Claim:
A method for operating a semiconductor memory device, the semiconductor memory device including: a substrate; a stacked body including a plurality of word electrode layers and a plurality of insulating layers alternately stacked on the substrate; a memory film including a charge storage film provided on an inner wall of a memory hole punched through the stacked body; a channel body provided inside the memory film in the memory hole; a select transistor including a select gate stacked on the stacked body and connected to an end portion of the channel body; and a wiring connected to the select transistor, the method comprising: boosting a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer; and after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, decreasing a potential of the word electrode layer to a second erase potential lower than the first erase potential.