Patent ID: 7767506

Claim:
A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line including a gate electrode; forming a gate insulating layer on the gate line; forming a semiconductor on the gate insulating layer; forming a data line including a source electrode and a drain electrode over the semiconductor layer; depositing a passivation layer on the data line and the drain electrode; and forming a pixel electrode connected to the drain electrode, wherein the semiconductor, the data line, and the drain electrode are etched through a photolithography process using one exposure mask, wherein the exposure mask includes: a translucent area comprising a translucent layer that generates a phase difference in an incident light passing through the translucent area, the phase difference provided in the range from about −70° to about +70°; a light blocking opaque area comprising an opaque layer, wherein the opaque area faces the data line and the drain electrode; and a remaining area other than the translucent area and the light blocking opaque area.