Patent ID: 8219879

Claim:
A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder, comprising steps of: presetting a maximum delay unit length; reading a starting address line of each of a plurality of memory blocks, wherein each said memory block saves multiple entries of data, and the multiple entries of data in each said memory block are sequentially read or written, starting from a corresponding said starting address line, each said starting address line corresponding to a starting address number; arranging the starting address numbers in order; sequentially assigning the starting address numbers to a plurality of groups such that a difference between a maximum said starting address number and a minimum said starting address number in each said group is smaller than or equal to the maximum delay unit length, thereby producing a rearrangement result; and constructing at least one memory group by rearranging at least one said memory block according to the rearrangement result.