Patent ID: 7560766

Claim:
A semiconductor device, comprising: a semiconductor substrate including an upper surface; a gate insulating film formed on the upper surface of the semiconductor substrate; a memory cell unit including a plurality of first gate electrodes of non-volatile memory cell transistors located along a first direction, a second gate electrode of a first select gate transistor located at one end of the first gate electrodes and a third gate electrode of a second select gate transistor located at the other end of the first gate electrodes, the first, the second and the third gate electrodes formed on the gate insulating film, the memory cell transistors and the select gate transistors connected in series; a contact plug located at one end of the memory cell unit, the contact plug connected to a diffusion layer formed in the upper surface of the semiconductor substrate; a first source line located at the other end of the memory cell unit and located along the first direction, the first source line connected to a diffusion layer formed in the upper surface of the semiconductor substrate; a first inter-layer insulating film formed on the first, the second and the third gate electrodes and the first source line; a bit line electrically connected to the contact plug, the bit line formed on the first inter-layer insulating film and located along a second direction perpendicular to the first direction; a second inter-layer insulating film formed on the bit line; and a second source line electrically connected to the first source line, the second source line formed on the second inter-layer insulating film, the second source line located above the memory cell unit and along the first direction.