Patent ID: 8477056

Claim:
An apparatus, comprising: an analog-to-digital converter (ADC) circuit configured to receive an input signal and sample the input signal at a sampling rate to supply a first plurality of samples of first data at a first data rate; a memory configured to receive the first plurality of samples of the first data at the first data rate and the memory having circuitry that outputs a second plurality of samples of the first data at a second data rate less than the first data rate; a filter circuit configured to receive the second plurality of samples of the first data from the memory at the second data rate and supply a plurality of samples of second data at the second data rate; and a digital signal processor, a portion of which being configured to receive the plurality of samples of second data at the second data rate, wherein each of the first plurality of samples of the first data includes a first number of bits, each of the second plurality of samples of the first data includes a second number of bits, and each of the plurality of samples of the second data includes a third number of bits, the first number of bits being equal the second number of bits, and the first number of bits being equal to the third number of bits.