Patent ID: 7337382

Claim:
A data transfer control device for data transfer through a bus, the data transfer control device comprising: a buffer controller which controls access to a packet buffer which stores data; a transfer controller which controls transfer of the data stored in the packet buffer; and a state controller which controls a plurality of states including a state of a host operation in which the data transfer control device operates in a role of a host, and a state of a peripheral operation in which the data transfer control device operates in a role of a peripheral, wherein the transfer controller includes: a host controller which transfers data as the host during the host operation; and a peripheral controller which transfers data as the peripheral during the peripheral operation, and wherein, during the host operation, the buffer controller allocates a plurality of pipe regions in the packet buffer, and the host controller transfers data between one of the allocated pipe regions and an endpoint corresponding to the one of the pipe regions; wherein a transaction for performing data transfer with a transfer destination is issued, and wherein, when a negative acknowledgment (NAK) response to the issued transaction is returned from the transfer destination, issuance of a retransmission transaction for the NAK response is allowed after waiting for a predetermined skip timing.