Patent ID: 8836011

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor layer; a first stacked body including a plurality of electrode layers and a plurality of first insulating films alternately stacked on the semiconductor layer; a pair of first channel body layers piercing through the first stacked body in a stacking direction of the first stacked body, lower ends of the pair of the first channel body layers being connected to each other; a first memory film provided between the pair of the first channel body layers and the plurality of electrode layers; a pair of second channel body layers piercing through the first stacked body in the stacking direction of the first stacked body, lower ends of the pair of the second channel body layers being connected to each other; a second memory film provided between the pair of the second channel body layers and the plurality of electrode layers; a second stacked body including a first interlayer insulating film provided on the first stacked body and a select gate layer provided on the first interlayer insulating film; a second interlayer insulating film provided on the select gate layer of the second stacked body; a third channel body layer provided at an upper end of each of the pair of the first channel body layers and piercing through the second stacked body in a stacking direction of the second stacked body; a first gate insulating film provided between the third channel body layer and the select gate layer; a fourth channel body layer provided at an upper end of each of the pair of the second channel body layers and piercing through the second stacked body in the stacking direction of the second stacked body; a second gate insulating film provided between the fourth channel body layer and the select gate layer, the third channel body layer and the fourth channel body layer being disposed in a first direction perpendicular to the stacking direction, the device further comprising: a pad layer provided on the second interlayer insulating film and electrically connecting one of the adjacent third channel body layers to one of the fourth channel body layers; a bit line connected on the pad layer through a via electrode, the bit line extending in the first direction; a first source line connected to the other of the adjacent third channel body layers, the first source line extending in a second direction crossing to the first direction; and a second source line connected to the other of the adjacent fourth channel body layers, the second source line extending in the second direction.