Patent ID: 7120203

Claim:
A dual link transmitter that transmits a primary link having a plurality of primary link data channels, a secondary link having a plurality of secondary link data channels, a primary link bit clock, and a secondary link bit clock, the transmitter comprising: a primary link transmitter comprising: a plurality of primary link data channel encoders, each of which receives and encodes a respective primary link data; and a plurality of primary link data channel serializers, each of which couples to a corresponding primary link data channel encoder and serializes a respective encoded data for the respective primary link data channel; a secondary link transmitter comprising: a plurality of secondary link data channel encoders, each of which receives and encodes a respective secondary link data; and a plurality of secondary link data channel serializers, each of which couples to a corresponding secondary link data channel encoder and serializes a respective encoded data for the respective secondary link data channel; and a dual link clock generator coupled to the primary link transmitter and to the secondary link transmitter to generate a primary clock signal and a secondary clock signal, wherein during a single link mode of operation the primary clock signal is used as the primary link bit clock for the primary link data channels and the secondary clock signal is selected as the secondary link bit clock for the secondary link data channels, but during a dual link mode of operation the primary clock signal is used as the primary link bit clock for the primary link data channels and also selected as the secondary link bit clock for the secondary link data channels to ensure synchronization of data at a receive end of the primary link data channels and the secondary link data channels.