Patent ID: 8024595

Claim:
A semiconductor integrated circuit comprising: a plurality of internal blocks connected to a power supply circuit in parallel; a clock generating unit configured to generate a clock signal; a phase locked loop configured to receive the clock signal of the clock generating unit; a clock supply unit configured to receive a clock signal from the phase locked loop and configured to supply clock signals to each of the plurality of internal blocks, the clock supply unit including a control unit, and a clock selecting unit connected to the clock generating unit, the control unit, and each of the plurality of internal blocks, the clock selecting unit being configured to change the frequency of the clock signal output to each of the plurality of internal blocks in a stepwise manner so as to supply a clock signal of a first frequency to the plurality of internal blocks, thereafter to supply a clock signal of a second frequency to the plurality of internal blocks, and thereafter to supply a clock signal of a third frequency to the plurality of internal blocks; and a detection unit configured to detect that a fluctuation in power consumption in the semiconductor integrated circuit is stabilized; the control unit being configured to set the phase locked loop, control the frequency of the clock signals supplied to the plurality of internal blocks by the clock selecting unit, control the timing at which the clock selecting unit supplies the clock signals to the plurality of internal blocks, and wait until the detection unit detects that the fluctuation in power consumption in the semiconductor integrated circuit is stabilized before each occurrence of the control unit instructing the clock selecting unit to supply a clock signal of a new frequency to the plurality of internal blocks.