Patent ID: 8462028

Claim:
A parallel to serial conversion apparatus having a first and a second mode, comprising: a bit-swapping circuit that receives bits of input parallel data from parallel input terminals and generates bit-swapped parallel data by swapping the bits of the input parallel data; and a parallel to serial conversion circuit having internal input terminals that receives respective bits of the bit-swapped parallel data, the parallel to serial conversion circuit acquiring M1 bits of the bit-swapped parallel data received at M1 of the internal input terminals in the first mode and M2 bits of the bit-swapped parallel data received at M2 of the internal input terminals in the second mode, where each of M1 and M2 is an integer and 2≦M2<M1; wherein: the parallel to serial conversion circuit generates serial data by arranging the acquired bits of the bit-swapped parallel data in a first specified order in the first mode and in a second specified order, different from the first specified order, in the second mode; and the bit-swapping circuit swaps the bits of the input parallel data in a first way in the first mode and in a second way, different from the first way, in the second mode such that the parallel to serial conversion circuit acquires 1st to M1-th and 1st to M2-th bits of the input parallel data in the first and second modes, respectively, and arranges the acquired bits of the input parallel data in a same order independent of the modes.