Patent ID: 7825682

Claim:
A method comprising: adjusting a first on-chip termination calibration code based on a first voltage signal generated between a first reference resistance and first pull-up transistors; adjusting a first value of a first set of bits that form the first on-chip termination calibration code based on a first control signal that is not responsive to the first voltage signal to generate a second value of a first control code that is different from the first value; adjusting the first value of the first set of bits based on a second control signal that is not responsive to the first voltage signal to generate a third value of a second control code that is different from the second value; controlling second pull-up transistors in a first buffer that provide termination impedance at a first pin using the second value of the first control code; and controlling third pull-up transistors in a second buffer that provide termination impedance at a second pin using the third value of the second control code, wherein the second value of the first control code causes the second pull-up transistors to generate a different impedance at the first pin than the impedance that the third value of the second control code causes the third pull-up transistors to generate at the second pin.