Patent ID: 8166357

Claim:
An apparatus for implementing integrated circuit security features to selectively disable testability features on an integrated circuit chip comprising: a test disable logic circuit receiving a test enable signal with the integrated circuit chip powering up to establish a test mode; said test disable logic circuit establishing said test mode and disabling ASIC signals responsive to the test enable signal set for said test mode; and said test disable logic circuit, enabling ASIC signals in a functional mode and disabling the testability features on the integrated circuit chip responsive to the test enable signal not being set for said functional mode; said test disable logic circuit includes a latch; said latch being reset on a power up state establishing said test mode; and said ASIC signals being disabled by a pair of input AND gates coupling an inverted test enable signal and said ASIC signals to said latch; and said latch being set for disabling the testability features on the integrated circuit chip and said ASIC signals being applied to respective inputs of said latch to selectively set or reset said latch responsive to the test enable signal not being set for said functional mode.