Patent ID: 8186049

Claim:
A method for making a circuit structure, comprising: forming a base conductive layer on a carrier board; forming a first patterned plating-resistant layer on the base conductive layer, the first patterned plating-resistant layer comprising at least one trench which exposes a part of the base conductive layer; forming a first patterned conductive layer in the trench; forming a second patterned plating-resistant layer covering the first patterned conductive layer and a part of the first plating-resistant layer, the second patterned plating-resistant layer comprising a first opening to expose a part of the first patterned conductive layer; forming a second patterned conductive layer on the first patterned conductive layer that is exposed by the first opening; removing the first patterned plating-resistant layer and the second patterned plating-resistant layer; removing the base conductive layer that is exposed by the first patterned conductive layer; and forming a patterned solder mask covering a part of the first patterned conductive layer, the patterned solder mask comprising at least one second opening to expose the second patterned conductive layer and a part of the first patterned conductive layer adjacent to the second patterned conductive layer.