Patent ID: 7538388

Claim:
A semiconductor device comprising: a semiconductor substrate; a first-conductivity-type drift region formed in said semiconductor substrate; a plurality of second conductivity type base regions formed in an upper part of said first-conductivity-type drift region; and a plurality of second-conductivity-type partition regions formed beneath said second-conductivity-type base region and arranged in said first-conductivity-type drift region, said second-conductivity-type partition regions being periodically formed in said first-conductivity-type drift region at a specified distance, and S A /S (where, S A is a sectional area per a single second-conductivity-type partition region as viewed in a plane parallel with said/ main surface, and S is a sectional area of a unit structural region, periodically formed as containing one of said second-conductivity-type partition regions, as viewed in a plane parallel with said main surface) in an element-forming region allowing current to flow therethrough is smaller than S A /S in at least a portion of a periphery region surrounding said element-forming region, wherein each of said second-conductivity-type partition regions has a columnar form, aligned in the thickness-wise direction of said semiconductor substrate, and two-dimensionally arranged in a plan view, and wherein said second-conductivity-type partition regions are provided as being arranged according to a rhombic lattice pattern in a plan view.