Patent ID: 8405942

Claim:
An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage comprising, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further comprising protection means for simultaneously turning-on the two transistors when a positive overvoltage occurs between the first and second power supply rails, said protection means comprising a detection and trigger circuit comprising: a first edge detector comprising a resistor in series with a capacitor, connected between the first and second rails; a second edge detector comprising a resistor in series with a capacitor, connected between the second and first rails; a P-channel MOS transistor having its source and its drain respectively connected to the first rail and to a first output, and having its gate connected between the resistor and the capacitor of the first edge detector; an N-channel MOS transistor having its source and its drain respectively connected to a second rail and to a second output, and having its gate connected between the resistor and the capacitor of the second edge detector; and first and second zener diodes respectively forward-connected between the second rail and the gate of the P-channel transistor, and between the gate of the N-channel transistor and the first rail.