Patent ID: 7676639

Claim:
An apparatus for handling read operations and write operations of Read-Modify-Write (RMW) commands in memory system, comprising: at least one memory controller interfacing at least one of a plurality of memory channels; at least one of a plurality of Extreme Data Rate (XDR) Dynamic Random Access Memories (DRAMs) interfacing the at least one of the plurality of memory channels; at least one RMW buffer associated with the at least one of the plurality of memory channels and associated with at least one arbiter; at least one write buffer associated with at least one of the plurality of memory channels and associated with the at least one arbiter; and at least one multiplexer (MUX) that is configured to merge data from the at least one RMW buffer and the at least one write buffer in response to the at least one arbiter transmitting the merged data from the at least one RMW buffer and the at least one write buffer, wherein the at least one memory controller is able to execute at least one of a read command or a write command in the time between the data being received from the at least one of the plurality of XDR DRAMs into the at least one RMW buffer and an Input/Output Cell (XIO) transmitting the merged data to at least one of the plurality of XDR DRAMs.