Patent ID: 7917875

Claim:
A buffer with programmable delay, comprising: an input node; a first voltage supply node receiving a first supply voltage; a second voltage supply node receiving a second supply voltage; a plurality of pull-up devices having current paths coupled between said first voltage supply node and at least one output node and having a corresponding first plurality of gates, wherein each of said first plurality of gates is coupled to a selected one of said input node and said second voltage supply collectively forming a first plurality of programmable connections; and a plurality of pull-down devices having current paths coupled between said at least one output node and said second voltage supply node and having a corresponding second plurality of gates, wherein each of said second plurality of gates is coupled to a selected one of said input node and said first voltage supply node collectively forming a second plurality of programmable connections; wherein said first and second plurality of programmable connections are programmed to adjust delay from said input node to said at least one output node.