Patent ID: 6856166

Claim:
A status scheme signal processing circuit, comprising: an input circuit configured to receive an input signal IN; a one-shot pulse circuit connected to an output of the input circuit and configured to generate a one-shot pulse ONEON representing ON of the input signal IN during a first period of time after a leading edge of the input signal IN, said one-shot pulse circuit further configured to generate a one-shot pulse ONEOFF representing OFF of the input signal IN during a first period of time after a trailing edge of the input signal IN; a status signal-generating circuit configured to generate a status signal OSC; a status signal conversion circuit configured to output said status signal OSC as a status-on signal OSCON while said input signal IN has a high level, said status signal conversion circuit further configured to output said status signal OSC as a status-off signal OSCOFF while said input signal IN has a low level; a mask signal-generating circuit connected to another output of the input circuit and configured to generate a mask signal MSK during a second period of time after the leading edge of said input signal IN, and after a second period of time after the trailing edge of said input signal IN; a first circuit configured to generate an OR signal (MON) of said one-shot pulse signal ONEON and said status-on signal OSCON; a second circuit configured to generate an OR signal (MOFF) of said one-shot pulse signal ONEOFF and said status-off signal OSCOFF; a third circuit configured to generate an AND signal (DON) of said OR signal MON and said mask signal MSK; a fourth circuit configured to generate an AND signal (DOFF) of said signal MOFF and said mask signal MSK; and a flip-flop circuit configured to receive said signal DON as a set signal, and said signal DOFF, as a reset signal.