Patent ID: 7292084

Claim:
A timer circuit comprising: a current mirror receiving a reference current as an input current, the current mirror providing a first output current on a first output node and a second output current on a second output node, the second output current being N times the first output current; a capacitor coupled between the first output node and a ground voltage, the capacitor receiving the first output current as a sinking current; a first switch coupled between a positive power supply voltage and the first output node, the first switch being controlled by a first control signal to be in a first position for precharging the capacitor to the positive power supply voltage and in a second position to allow the capacitor to be discharged by the first output current; a resistor coupled between the second output node and the ground voltage, the resistor being biased by the second output current to develop a reference voltage across the resistor; and a comparator having a first input terminal coupled to the first output node and a second input terminal coupled to the second output node, the comparator providing an output signal having a first state when the voltage across the capacitor at the first output node is greater than the reference voltage and providing an output signal having a second state when the voltage across the capacitor is equal to or less than the reference voltage.