Patent ID: 8120430

Claim:
A semiconductor device having a phase-locked loop (“PLL”), comprising: a voltage-controlled oscillator (“VCO”) configured to generate an output clock signal having an output frequency controlled by a control voltage; a charge pump configured to output current pulses in response to a plurality of UP control pulses and a plurality of DOWN control pulses; a loop filter configured to generate the control voltage in response to the current pulses from the charge pump; a phase-frequency detector (“PFD”) wherein: in response to a reference frequency of a first reference clock signal being present at the PFD and the output frequency of the output clock signal being locked to the reference frequency, the PFD generates the UP and DOWN control pulses to maintain the control voltage in a locked condition of the PLL, wherein one or more of the UP control pulses are simultaneous with one or more of the DOWN control pulses, respectively, and in response to the reference frequency of the first reference clock signal not being present at the PFD, the PFD generates the UP control pulses alternating with the DOWN control pulses based on a second reference clock signal.