Patent ID: 8607111

Claim:
A method of operating an integrated circuit tester, comprising: executing a command sequence of a test on an integrated circuit tester containing two or more Algorithmic Pattern Generators (APGs) by executing the test command sequence in parallel on the two or more APGs, wherein each APG of the two or more APGs generates a single sub-instruction of a test instruction during each APG clock cycle; coupling the outputs of the two or more APGs to one or more integrated circuit devices under test (DUTs), wherein only one sub-instruction is coupled to the one or more DUTs during a DUT clock cycle and where each APG clock cycle contains two or more DUT clock cycles; and repeating a selected sub-instruction of a single APG by coupling the selected sub-instruction of that single APG to the one or more DUTs over two or more consecutive DUT clock cycles.