Patent ID: 8751720

Claim:
A computationally-networked unified data bus for a multi-core architecture, comprising: a unified data bus; a first data bus adapter coupled to the unified data bus; a first core, comprising a first customer data bus, coupled to the first data bus adapter, the first data bus adapter configured to encapsulate, translate, and interpret data communicated to the unified data bus from the first core from a first format of the first core into a common format of the unified data bus and to the first core from the unified data bus from the common format to the first format for delegation of processing to a second core, wherein the first data bus adapter is specific to the first core and wherein all data communicated to the first core and all data communicated from the first core pass through the first data bus adapter; a second data bus adapter coupled to the unified data bus; and the second core, comprising a second customer data bus, coupled to the second data bus adapter, the second data bus adapter configured to encapsulate, translate, and interpret data communicated to the unified data bus from the second core from a second format of the second core into the common format of the unified data bus and to the second core from the unified data bus from the common format to the second format for delegation of processing to the first core, wherein the second data bus adapter is specific to the second core and wherein all data communicated to the second core and all data communicated from the second core pass through the second data bus adapter; wherein the first core and the second core are hybrid cores.