Patent ID: 7349267

Claim:
A semiconductor memory device which includes a memory cell array in which memory cells are arranged in a matrix, each said memory cell being formed of a single transistor, the semiconductor memory device comprising: a plurality of word lines provided so as to correspond to rows in the matrix, respectively, each said word line being connected in common to respective gate terminals of transistors located in an associated one of the rows; a plurality of bit lines provided so as to correspond to columns in the matrix, respectively, each said bit line being connected to at least one of respective drain terminals of transistors located in an associated one of the columns; a plurality of source lines provided so that each said source line corresponds to every adjacent two rows in the matrix and is connected in common to respective source terminals of transistors located in the two rows; a plurality of source bias control circuits for controlling, in an active period in which an operation of reading data from the memory cells, according to a row selection signal for selecting one or more of the source lines which are to be controlled, one or more of the source lines which are not connected to one of the memory cells which is to be read out to be in a state where a source bias potential is higher than a ground potential and lower than a power supply potential; and a source line selection circuit for selecting said one of the source lines which is to be read out and generating the row selection signal.