Patent ID: 7796721

Claim:
An apparatus comprising: a ring counter having a plurality of master-slave flip-flops arranged in a series, wherein each master-slave flip-flop receives a clock signal, and wherein the ring counter has an even integer multiple of N states, and wherein the series includes a first sequence and a second sequence; correction logic having: a first logic gate that gates outputs from the last master-slave flip-flop of the second sequence and at least one master-slave flip-flop in the first sequence; and a second logic gate that gates outputs from the first logic gate and the last master-slave flip-flop of the first sequence, wherein the first master-slave flip-flop of the second sequence receives an output from the second logic gate; and an output logic gate that gates an internal state from at least one of the master-slave flip-flops with an output from one of the master-slave flip-flops to produce the clock signal divided by N.