Patent ID: 8875076

Claim:
A method of generating a FinFET structure layout performed by a layout generating machine having a processor component executing instructions, the method comprising: receiving a planar structure layout for an integrated circuit (IC) design, the planar structure layout including a plurality of planar active areas; generating a plurality of FinFET active areas corresponding to the plurality of planar active areas; generating mandrels in a FinFET active area of the plurality of FinFET active areas according to a FinFET active area width; determining a beta number for the FinFET active area of the plurality of FinFET active areas; determining a beta number for a planar active area of the plurality of planar active areas corresponding to the FinFET active area of the plurality of FinFET active areas; and adjusting the mandrels in the FinFET active area of the plurality of FinFET active areas such that a beta ratio of the FinFET active area beta number to the planar active area beta number is within a predetermined beta ratio range.