Patent ID: 8422270

Claim:
A nonvolatile semiconductor memory device having a two-dimensional memory cell array in which a plurality of two-terminal memory cells each having a nonvolatile variable resistance element which stores information by a change in electric resistance are arranged in a form of a matrix in a first direction and a second direction perpendicular to each other, a plurality of bit lines extending in the first direction and a plurality of data lines extending in the second direction are arranged, one terminals of the memory cells located at the same position in the first direction are commonly connected to one of the data lines, and the other terminals of the memory cells located at the same position in the second direction are commonly connected to one of the bit lines, the nonvolatile semiconductor memory device comprising: a bit line voltage supply circuit which supplies, for each of the bit lines, a predetermined first voltage to a selected bit line connected to the other terminal of the memory cell selected as an object to be read and supplies a predetermined second voltage to a non-selected bit line connected to the other terminal of the non-selected memory cell serving as an object not to be read; a data line voltage supply circuit which supplies the second voltage to a selected data line connected to one terminal of the memory cell selected as an object to be read and a non-selected data line connected to one terminal of the non-selected memory cell serving as an object not to be read; and a sense circuit which detects a current flowing in the selected data line separately from a current flowing in the non-selected data line to detect an electric resistance state of the selected memory cell in reading, wherein the data line voltage supply circuit has a data line selecting circuit which independently sets each of the data lines to any one of the selected data line and the non-selected data line, the bit line voltage supply circuit has a bit line selecting circuit which independently sets each of the bit lines to any one of the selected bit line and the non-selected bit line, at least one of the bit line voltage supply circuit and the data line voltage supply circuit includes a voltage adjusting circuit having an operational amplifier and a MOS transistor having a gate terminal connected to an output terminal of the operational amplifier, a drain terminal connected to an inverted input terminal of the operational amplifier, and a source terminal connected to a predetermined fixed potential, and any one of the first voltage and the second voltage applied to the non-inverted input terminal of the operational amplifier is applied from the MOS transistor to at least one of the bit line and the data line through a connection node between the drain terminal of the MOS transistor and the inverted input terminal of the operational amplifier.