Patent ID: 7646655

Claim:
A memory device comprising: a fail block to verify and store addresses of failed memory cells of an array of memory cells during execution of a test algorithm, said fail block comprising a logic gate having a first input coupled to an output of a sense amplifier, and a second input to receive an expected logic value according to the test algorithm, and a resettable bistable circuit to store information of the failed memory cells and coupled to said logic gate; a pattern block to be input with addresses of memory cells generated by an internal address counter and to output, based on a pattern for testing an integrity of said array of memory cells, command flags for programming the addressed memory cell to a microcontroller and the expected logic value to the second input of said logic gate; and a redundancy block coupled to and interacting with said microcontroller to substitute redundant memory cells for the failed memory cells or to generate a non-redundancy flag.