Patent ID: 7484113

Claim:
A delay lock loop for an FPGA architecture comprising: an external clock I/O pad; an internal clock node; a clock tree having an input and an output, the input of the clock tree coupled to the external clock I/O pad, the internal clock node; a flip-flop having a clock input coupled to the output of the clock tree, a data input, and a data output; a reference delay line having an input and an output, the input programmably coupled to the external clock I/O pad and the internal clock node; a feedback delay line having an input and an output the input programmably coupled to the data output of the flip-flop and the output of the clock tree; a first divide-by-two circuit having an input coupled to the output of the reference delay line and an output; a first matching delay line having an input coupled to the output of the reference delay line and an output; a feedback delay line having an input and an output; a second divide-by-two circuit having an input coupled to the output of the feedback delay line and an output; a second matching delay line having an input coupled to the output of the feedback delay line and an output; a phase detector having first input, a second input, and a plurality of outputs, the first input programmably coupled to one of the output of the first divide-by-two circuit and the first matching delay line, the second input programmably coupled to one of the output of the second divide-by-two circuit and the second matching delay line; control logic coupled to the plurality of outputs of the phase detector; a programmable delay line having a reference clock input programmably coupled to one of the external clock I/O pad and the internal clock node, a plurality of data inputs, and an output, the plurality of data inputs coupled to the plurality of outputs of said control logic circuit to receive data to program a delay in the programmable delay line, and an output programmably coupled to one of the input of the clock tree; a first I/O pad programmably coupled to the data output of the flip-flop; and a second I/O pad programmably coupled to the clock input of the flip flop and the input to the feedback delay line.