Patent ID: 7068543

Claim:
A flash memory, comprising: at least one floating-gate memory cell comprising a source, a drain, a control gate, a floating gate and a substrate; a memory control circuit for controlling operations on the at least one floating-gate memory cell; a wordline coupled to the control gate of the at least one memory cell; and a wordline drive transistor coupled to the wordline; wherein the memory control circuit is adapted to apply a voltage of a first polarity relative a common voltage to the control gate of the at least one floating-gate memory cell beginning substantially concurrently with applying a voltage of a second polarity relative the common voltage to the source of the at least one floating-gate memory cell; and wherein the memory control circuit is further adapted to begin discharging the voltage of the second polarity while allowing the voltage of the first polarity to float, and discharging the voltage of the first polarity at least two microseconds after beginning to discharge the voltage of the second polarity.