Patent ID: 8330098

Claim:
A high resolution, high speed, single track optical encoder, comprising: a light emitter configured to emit light therefrom; a plurality of photodetectors or photodiodes having leading and trailing edges arranged along a single track and a common axis to form a single track light detector, the single track light detector having disposed along the common axis pairs of A and A\ data channel light detectors and B and B\ data channel light detectors, the A and B light detectors, and the A\ and B\ light detectors, respectively, being arranged to generate output signals that are 90 degrees out of phase with respect to one another, the A, A\ , B and B\ light detectors generating respective first, second, third and fourth output ramp signals; signal generation circuitry comprising at least first, second, third and fourth current amplifiers configured to receive as inputs thereto, respectively, the first, second, third and fourth output ramp signals corresponding to the A, A\ , B and B\ light detectors, the first current amplifier, being configured to provide full A and fractional A output ramp signals, the second current amplifier being configured to provide full A\ and fractional A\ output ramp signals, the third current amplifier being configured to provide full B and fractional B output ramp signals, the fourth current amplifier being configured to provide full B\ and fractional B\ output ramp signals, the first, second, third and fourth current amplifiers having no amplification or filtering feedback loops operably connected to the inputs and outputs corresponding thereto, each of the current amplifiers generating full and fractional output ramp signals; comparator circuitry configured to receive pairs of the A and fractional A output ramp signals, the A\ and fractional A\ output ramp signals, the B and fractional B output ramp signals, and the B\ and fractional B\ output ramp signals as inputs thereto, and to provide intermediate output signals therefrom; and logic circuitry configured to receive the intermediate signals from the comparator circuitry and generate channel A and channel B output square wave or pulse signals on the basis of the intermediate signals.