Patent ID: 6858920

Claim:
A semiconductor device comprising: a first semiconductor element having a plurality of first pads and a plurality of second pads arrayed along two facing sides of a major surface; a second semiconductor element having a plurality of third pads along sides where the first pads and the second pads are arrayed, a plurality of fourth pads along sides proximate said two sides at which the first pads and the second pads are not arrayed and first wirings for electrically connecting the plurality of third pads to the plurality of fourth pads; a substrate carrying the first semiconductor element and the second semiconductor element; a plurality of electrodes arrayed along all the circumferential sides of the major surface of the substrate; second wirings for electrically connecting the plurality of first pads and the plurality of fourth pads to the plurality of electrodes; and third wirings for electrically connecting the plurality of second pads to the plurality of third pads.