Patent ID: RE41441

Claim:
An output buffer s , comprising: a data coder having complimentary data input terminals, a pair of data read output terminals, and a data mask control terminal, the data coder generating at respective first and second data read output terminals complimentary data read output signals corresponding to complimentary data input signals applied to respective data input terminals when an inactive data mask control signal is applied to the data mask control terminal, the data coder generating at the respective first and second data read output terminals data read output signals having predetermined values when an active data mask control signal is applied to the data mask control terminal, the data coder comprising: a data mask register including the data mask control terminal, the data mask register receiving the data mask control signal on the data mask control terminal and a periodic clock signal on a clock input terminal, the data mask register generating an output signal responsive to a predetermined portion of the clock signal after the data mask control signal becomes active; and a data output register coupled to the data mask register and including the data input terminals and the data read output terminals, the data output register forcing the data read output signals to have the predetermined values responsive to the output signal from the data mask register; and an output stage having respective input terminals coupled to the first and second data read output terminals of the data coder, the output stage generating a data output signal at an output terminal that corresponds to the data read output signals from the data coder when the data read output signals do not have the predetermined values, the output stage producing a relatively high impedance at the data output terminal when the data read output signals have the predetermined values.