Patent ID: 8261217

Claim:
A pattern forming method comprising: performing, by a computer, a first design-rule check on design data of a pattern to be formed in a semiconductor substrate according to a first design rule; modifying, by a computer, design data that has been subjected to the first design-rule check on the basis of a modification guideline regulated by a criterion, the criterion satisfying at least one of a request on a design of a semiconductor device or a request on processes of manufacturing the semiconductor device; performing, by a computer, a second design-rule check on the modified design data also according to the first design rule; outputting, by a computer, a first portion of the modified design data which does not violate the first design rule as pattern forming design data used in actual pattern formation; extracting a second portion of the modified design data which violates the first design rule; performing a third design-rule check, according to a second design rule, on only the second portion of the modified design data, the second design rule having an allowable range wider than that of the first design rule; outputting, by a computer, a first sub-portion of the second portion of the modified design data, which does not violate the second design rule, as the pattern forming design data; extracting a second sub-portion of the second portion of the modified design data, which violates the second design rule; and performing one of redesigning or adjusting the modification guideline for only the second sub-portion of the second portion of modified design data to make the second sub-portion of the second portion of modified design data satisfy the second design rule.