Patent ID: 7575957

Claim:
A method for manufacturing a leadless semiconductor package, comprising: (a) providing a metal plate having an upper surface and a lower surface; (b) half-etching the lower surface of the metal plate, so as to form a recession; (c) forming a non-conductive ink in the recession of the metal plate; (m) grinding the lower surface of the metal plate where the recession is formed and the non-conductive ink, so that the non-conductive ink does not cover the lower surface of the metal plate; (d) patterning the upper surface of the metal plate corresponding to the location of the non-conductive ink to form a plurality of inner leads and a chip pad connected to the inner leads by the non-conductive ink so that the non-conductive ink is between every two of the inner leads and couples the inner leads to the chip pad; (e) placing a semiconductor chip on the chip pad; (f) using a plurality of bonding wires electrically connecting the semiconductor chip to the inner leads; and (g) forming a molding compound on the inner leads and the non-conductive ink for encapsulating the semiconductor chip and the bonding wires; wherein the step (d) is performed after the step (c).