Patent ID: 7746155

Claim:
An apparatus comprising: an output node; a first power supply; a second power supply; a first node; a second node; a first NMOS transistor that is coupled to the first node at its drain and the output node at its source; a first driver that is coupled to the first power supply and the gate of the first NMOS transistor, wherein the first driver actuates and deactuates the first NMOS transistor, and wherein the first driver receives a first signal; a second NMOS transistor that is coupled to the second node at is source and the output node at its drain; and a second driver including: a drive circuit that receives a second signal and that is coupled to the gate of the second NMOS transistor and the second power supply; a current source that is coupled to the second power supply; a third NMOS transistor that is coupled to the current source at its drain, the gate of the second NMOS transistor at its gate, and the second node at its source; and an AND gate that is coupled to the current source and that receives the second signal; and a strong pulldown circuit that is coupled to the AND gate and the gate of the second NMOS transistor.