Patent ID: 8046566

Claim:
A method for reducing power consumption associated with a register file of a processor supporting simultaneous multithreading processing(SMT), wherein a control logic element manages the allocation of register file resources with respect to specific ones of a plurality of program threads, the method comprising: monitoring the number of currently executing or scheduled processing threads in the processor; defining a minimum and maximum threshold of currently executing or scheduled processing threads for a given architected state triggering a change in the number of register file entries required to support SMT processing; determining when a minimum or maximum threshold of currently executing or scheduled processing threads is reached; identifying a sub-area of the register file to be disabled, such that current SMT processing requirements are satisfied; controlling register file usage such that an address space corresponding to the register file sub-area is not used during future allocation of register entries; checking whether all register entries in the register file sub-area are disabled or have not been used within a predefined timing period and are no longer in use; disabling the address space of the register file sub-area; applying a power saving technique for the register file sub-area selected for deactivation when no entries within the register file sub-area are required for the current operation of the processor; marking all register entries associated with the register file sub-area selected for deactivation with a DEAD-flag bit; and restricting an allocation of new register entries to address ranges outside the address range of the register file sub-area.