Patent ID: 8811065

Claim:
A memory module comprising: a plurality of groups of dynamic random access memory (DRAM) integrated circuits comprising a first group, each group of DRAM integrated circuits including a plurality of data-storing DRAM integrated circuits and a tag-storing DRAM integrated circuit that is distinct from the plurality of data-storing DRAM integrated circuits, wherein the plurality of data-storing DRAM integrated circuits of the first group store first data, and wherein the tag-storing DRAM integrated circuit of the first group stores error-checking information associated with the first data; and an interface circuit for providing an interface between the plurality of groups of DRAM integrated circuits and a memory controller, the interface circuit configured to: receive a read command from the memory controller for the first data; read the first data from the plurality of data-storing DRAM integrated circuits of the first group; determine that the first data as read is erroneous; and recover the first data using at least the error-checking information from the tag-storing DRAM integrated circuit of the first group, in response to determining that the first data as read is erroneous.