Patent ID: 7280383

Claim:
A semiconductor memory device including a first memory cell array, an IO control circuit and a second memory cell array arranged between the first memory cell array and the IO control circuit, comprising: first local data IO signal lines arranged above the first memory cell array; second local data IO signal lines arranged on the same layer and in the same direction as the first local data IO signal lines above the second memory cell array; first global data IO signal lines connected to the first local data IO signal lines and arranged in a perpendicular direction to the first and second local data IO signal lines to extend from the first memory cell array to the IO control circuit; and second global data IO signal lines connected to the second local data IO signal lines arranged to extend from one side of a region of the second memory cell array adjacent to the IO control circuit to an opposite side of the second memory cell array region and from the opposite side of the second memory cell array region back to the IO control circuit, wherein the first and second global data IO signal lines are arranged on different layers than the first and second local data IO signal lines, wherein the first global data IO signal lines are arranged such that portions above a region of the first memory cell array are arranged on the same layer as portions of the second global data IO signal lines extending back to the IO control circuit from the opposite side of the second memory cell array region and portions above the second memory cell array region are arranged on a different layer than portions of the second global data IO signal lines extending from the side of the second memory cell array region adjacent to the IO control circuit.