Patent ID: 8471595

Claim:
A selectable latch comprising: a pair of parallel gates comprising a first parallel gate receiving a seed signal, and a second parallel gate receiving a data signal; a logic circuit operatively connected to said parallel gates, said logic circuit performing logic operations using signals output by said parallel gates to produce an updated data signal; an additional gate operatively connected to said logic circuit, said additional gate controlling passage of said updated data signal; two inputs, one of said inputs being connected to said first parallel gate and another of said inputs being connected to said second parallel gate; a first feedback loop operatively connected to said first parallel gate; a second feedback loop operatively connected to said second parallel gate; and a third feedback loop operatively connected to said additional gate, each of said first, second, and third feedback loops comprising: an inverter operatively connected to said gate; a clock controlled gate operatively connected to said inverter, said clock controlled gate receiving a feedback data signal from said inverter; and a mode controlled gate operatively connected to said clock controlled gate, said mode controlled gate receiving data from said clock controlled gate and outputting data to said inverter, said clock controlled gate comprising a stacked gate and said mode controlled gate comprising a pass gate, or said clock controlled gate comprising a pass gate and said mode-controlled gate comprising a stacked gate.