Patent ID: 8347186

Claim:
Systematic encoder assembly comprising: a parallelized hardware implementation of a systematic encoder, the parallelized hardware implementation including a circuit configured for a transform G from an input word to an output word, the circuit containing memory, the memory having elements, the elements having a state, the state taking values of “known” and “unknown”; a first part of the memory establishing an input array, a second part of the memory establishing a code word array, the input array having a fixed part, the code word array having a data part and a parity part; the circuit having an existing knowledge, the existing knowledge being the set of memory elements in the “known” state, the existing knowledge being initialized by loading a data word into the data part of the code word array and a fixed word into the fixed part of the input array; the circuit extracting new knowledge from existing knowledge via local constraints according to a schedule of caluclations; the memory elements in “unknown” state being updated in accordance with the new knowledge; whereby a parity word is obtained in the parity part of the code word array and the code word array is output as a systematic code word for transmission thereof as a robust transform of the data word, wherein the tranform G has a form P(F 1 G 1 )Q, wherein P is a row-permuter, F 1 is a first kernel transform, G 1 is a first-tier transform, Q is a column permuter, the row permuter is a permutation matrix, the column permuter is a permutation matrix, the first kernel transform F 1 has a size greater than one, the first-tier transform has a size smaller than a size of the transform G, and the circuit includes at least one first-tier subcircuit, the subcircuit implementing the first-tier transform G 1 .