Patent ID: 7335596

Claim:
A method for fabricating Cu-based interconnections in a semiconductor device, comprising the steps of: depositing a thin film of Cu or Cu alloy on a dielectric film by sputtering, the dielectric film having trenches and/or via holes and being arranged on or above a substrate; and carrying out high temperature and high pressure treatment to thereby embed the Cu or Cu alloy into the trenches and/or via holes, wherein the step of carrying out high temperature and high pressure treatment comprises cooling the work at a rate of 10° C./min or more after holding the work at high temperature and high pressure so that the filling percentage of the Cu or Cu alloy in the trenches and/or via holes is at least 95%; and wherein the sputtering is carried out under the following conditions: sputtering gas: a gaseous mixture containing hydrogen gas and an inert gas in a ratio in percentage of 5:95 to 20:80 substrate temperature: −20° C. to 0° C.