Patent ID: 7408248

Claim:
A lead frame for use in a semiconductor device comprising inner leads and outer leads, wherein a whole surface of the substrate constituting the lead frame or at least the outer leads has a composite plated layer applied thereon, and the composite plated layer comprises an underlayer consisting of an Ni-based plating layer deposited on the whole surface of the substrate constituting the lead frame or on at least the outer leads, a Pd— or Pd alloy-plating layer deposited at a thickness of 0.005 to 0.01 μm on an upper surface of the underlayer, and an Ag— or Ag—Au alloy-plating layer of a thickness of not larger than 0.03 μm and an Au-plating layer of a thickness of not larger than 0.03 μm successively deposited on an upper surface of the Pd— or Pd alloy-plating layer.