Patent ID: 7870365

Claim:
An integrated circuit comprising a microprocessor matrix of mesh-interconnected matrix processors, the matrix comprising: a first matrix processor comprising a first hardware data switch configured to transfer inter-processor data messages and control messages between the first matrix processor and a plurality of matrix processors immediately neighboring of the first matrix processor over a corresponding plurality of inter-processor matrix links, wherein each inter-processor matrix link includes a data channel and a control channel, wherein the data channel and the control channel are mutually non-contentious, and wherein the first data switch is configured to receive a set of control messages over a control channel of a first inter-processor matrix link, and a first instruction processing pipeline connected to the first data switch and configured to process a set of instructions, the set of instructions including a data streaming instruction for initiating an inter-processor data stream over a plurality of consecutive clock cycles over a data channel of a second inter-processor matrix link; and a second matrix processor immediately neighboring the first matrix processor and connected to the first matrix processor over the second inter-processor matrix link, wherein the second matrix processor comprises a second instruction processing pipeline configured to process the set of instructions, and a second hardware data switch connected to the second instruction processing pipeline and the first data switch and configured to receive the data stream over the data channel of the second inter-processor matrix link, and the set of control messages over a control channel of the second inter-processor matrix link concurrently and non-contentiously with respect to the data stream.