Patent ID: 8822295

Claim:
A static random access memory (SRAM) fabrication method, comprising: forming a first gate stack and a second gate stack on a substrate, the first gate stack and the second gate stack having a gate dielectric layer having a width; forming first isolating spacers adjacent to the first gate stack, the isolating spacers and first gate stack having a gate length, Lgate; forming second isolating spacers adjacent to the second gate stack such that a second source region and a second drain region underlap the second isolating spacers, wherein the second gate stack, the isolating spacers and second gate stack have the gate length Lgate; forming a first source region and first drain region adjacent the first gate stack, which generates an effective electrical gate length, Leff, wherein the first source region, the first drain region and the first gate stack define a pull down transistor; forming the second source and the second drain region adjacent the second gate stack, wherein the second source region, the second drain region and the second gate stack define a pull up transistor and wherein the second source and second drain regions are formed from a high extension dose implant performed at a dose between 1×10 15 atoms/cm 2 to 5×10 15 atoms/cm 2 , wherein the first source and first drain regions are formed from a low extension dose implant performed at a dose between 1×10 10 atoms/cm 2 to 1×10 13 atoms/cm 2 that decreases a difference between Lgate and Leff, such that the first source and first drain regions underlap only the first isolating spacers, and that Leff is greater than the width of the gate dielectric layer, the low extension dose implant not affecting a transition voltage or a channel length of the SRAM, and wherein the pull down transistor has a higher resistance than the pull up transistor.