Patent ID: 6862232

Claim:
A semiconductor device comprising: a plurality of first memory cells for storing either one of first information or second information, arranged at points of intersection between a plurality of word lines and a first data line; a plurality of first dummy cells for storing the first information, arranged at points of intersection between said plurality of word lines and a first dummy data line; a plurality of second dummy cells for storing the second information, arranged at points of intersection between said plurality of word lines and a second dummy data line; a plurality of first redundancy cells arranged at points of intersection between said plurality of word lines and a first redundancy data line; a plurality of second redundancy cells arranged at points of intersection between said plurality of word lines and a second redundancy data line; and a plurality of third redundancy cells arranged at points of intersection between said plurality of word lines and a third redundancy data line, wherein when one of said plurality of first memory cells has a defect, said first redundancy data line replaces said first data line, wherein when one of said plurality of first dummy cells has a defect, said second redundancy data line replaces said first dummy data line, and wherein when one of said plurality of second dummy cells has a defect, said third redundancy data line replaces said second dummy data line.