Patent ID: 8508392

Claim:
A pipelined analog-to-digital converter comprising: a conversion stage part including K conversion stages (K being an integer of 2 or more) connected in series, each of the K conversion stages being configured to convert an input voltage into a B-bit digital code (B being a natural number) in response to a plurality of clock signals and to output a residual voltage, the K conversion stages being divided into an upper conversion part having a conversion stage being an error-measured object and a lower conversion part having at least one conversion stage connected in series with the upper conversion part; a first digital correction circuit configured to receive at least one digital code from the lower conversion part and to perform a data correction operation; a pipelined conversion stage error measuring and correcting circuit configured to measure an error of the upper conversion part and to correct an output value from the first digital correction circuit using the measured error; and a second digital correction circuit configured to receive at least one digital code from the upper conversion part and an output value of the pipelined conversion stage error measuring and correcting circuit and to perform a data correction operation.