Patent ID: 7240253

Claim:
A semiconductor storage device comprising: a memory cell array including a plurality of memory cells provided as an array at the intersections of a plurality of word lines and a plurality of bit lines; a plurality of sense amplifiers connected to said bit lines of said memory cell array; a column decoder selecting bit lines; an IO line connected to each of the bit lines selected by said column decoder, each said IO line being a data line exchanging write data and readout data with said memory cell array, two of said IO lines comprising an IO line pair; a write register connected to each said IO line pair, each write register for storing and holding the write data entered from a data terminal of the semiconductor storage device; a write amplifier driving and outputting to each said IO line pair based on the write data held by said write register; a read amplifier connected to each said IO line pair and amplifying readout data from a connected memory cell; plural comparators and plural inversion control circuits, a different comparator and a different control circuit connected to each read amplifier and connected to each write register, each comparator comparing the readout data amplified by said connected read amplifier and the expectation data applied from said connected write register via the connected inversion control circuit; and the inversion control circuit supplying non-inverted and inverted values of data stored in said write register, based on an input inversion control signal input to said inversion control circuit; wherein, an output of each said inversion control circuit is supplied as said expectation data to said connected comparator; the write data stored in each said write amplifier is written in the memory cell of the selected address during the normal operation and during testing; data is written in the memory cells during testing through each said write register, each connected inversion control circuit and each connected said write amplifier; and wherein the readout data read out from said memory cell and amplified by said read amplifier and expectation data output from said inversion control circuit supplied with data held by said write register are supplied to said comparator comparing the readout data and the expectation data.