Patent ID: 7774563

Claim:
A computer-implemented method for reducing memory access latency, the method comprising: receiving, at a memory controller, a memory access request, wherein the memory access request includes an address; determining if the address falls within an address range of a plurality of paired memory address range registers; responsive to the address falling within one of the address range of the plurality of paired memory address range registers, determining if an enable bit is set to 1, wherein the enable bit is associated with the address range within which the address falls; responsive to the enable bit being set to 1, flagging the memory access request as a high-priority request; placing the high-priority request on a request queue; receiving an indication, at a dispatcher in the memory controller, that a memory bank in a set of memory banks is idle forming an idle memory bank; determining if a set of high-priority requests is present in the request queue; responsive to an existence of the set of high-priority requests, sending an earliest high-priority request from the set of high-priority requests to the idle memory bank; starting a countdown interval timer for a predetermined time interval; and incrementing a high-priority dispatch counter each time the set of high-priority requests is dispatched.