Patent ID: 8151162

Claim:
An encoder, comprising: an ECC encoder which interleaves a data string into n (n≧2) blocks of data strings at every m (m≧2) bits, generates a first error correction code parity from the data string of each of said interleaved blocks, and adds said first error correction code parity of each block to said data string to create an error correction code word; a parity encoder which creates a parity bit at every plurality of bits of said error correction code word, and adds the parity bit to said error correction code word; and a second ECC encoder which divides a second error correction code word in which a parity generated by said parity encoder is added to said error correction code word, into L (L≧2) number of blocks of data strings at every K (K≧2) bits, generates a second error correction code parity, which is a linear code, in said block units, from the data string of each block, and adds said second error correction code parity of each block to said second error correction code word to create a third error correction code word.