Patent ID: 7649879

Claim:
A pipelined packet processing system comprising: a pipelined processor configured to 1) provide at least one pipeline having one or more slots, 2) assign packets to each of one or more available ones of the slots, 3) process one or more of the assigned packets during one or more processing cycles, and 4) derive a packet classification or forwarding decision for each of the one or more assigned packets, upon or after the one or more assigned packets have undergone one or more cycles of processing; wherein the pipelined processor is further configured to process a packet, assigned to a slot, during a processing cycle by 1) accessing one or more resources responsive to packet processing state data relating to the packet, 2) retrieving data from the one or more resources, and 3) selectively updating the packet processing state data relating to the packet responsive to the data retrieved from the one or more resources; and the packet processing state data relating to the packet is stored in or assigned to the same slot of the pipeline as the packet, updated packet processing state data is formed from the packet processing state data after a predetermined number of processing cycles of the packet on the pipeline, where the predetermined number of processing cycles is programmable, and the processor derives the classification or forwarding decision for the packet from the updated packet processing state data for the packet after the predetermined number of processing cycles of the packet is completed.