Patent ID: 8378948

Claim:
A circuit, comprising: a first decoder adapted to output a plurality of first decoding signals employing first bits of a digital data signal; a first selection unit adapted to generate a plurality of first selection signals and a plurality of first inverse selection signals in correspondence with the first decoding signals; a switch unit adapted to select a first reference voltage and second reference voltage from a plurality of reference voltages employing the first selection signals and the first inverse selection signals, the second reference voltage being lower than the first reference voltage; a second decoder adapted to output a plurality of second decoding signals employing second bits of the digital data signal; a second selection unit adapted to generate a plurality of second selection signals and a plurality of second inverse selection signals in correspondence with the second decoding signals; and a plurality of voltage distribution units adapted to receive and distribute the selected first reference voltage and the selected second reference voltage, wherein a voltage distribution unit includes a data voltage generation unit adapted to receive the second selection signals and the second inverse selection signals to generate a data voltage, wherein the switch unit includes: a first transistor adapted to receive a first selection signal and switch the first reference voltage; a second transistor adapted to receive a first inverse selection signal and switch the first reference voltage; a third transistor adapted to receive the first selection signal and switch the second reference voltage; and a fourth transistor adapted to receive the first inverse selection signal and switch the second reference voltage.