Patent ID: 7795934

Claim:
A device, comprising: a delay lock loop configured to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising: a coarse delay unit configured to provide a coarse delay upon at least one of said reference signal and a data output signal; a fine delay unit configured to provide a fine delay upon at least one of said reference signal and said data output signal, said fine delay unit comprising: a first inverter configured to invert an input signal; an N-channel transistor set operatively coupled to said first inverter, said N-channel transistor set comprising a first and a second N-channel transistor, wherein a source terminal of said first N-channel transistor is coupled to a source terminal of said second N-channel transistor and a drain terminal of said first N-channel transistor is coupled to a drain terminal of said second N-channel transistor; a P-channel transistor set comprising a first and a second P-channel transistor, wherein a source terminal of said first P-channel transistor is coupled to a source terminal of said second P-channel transistor and a drain terminal of said first P-channel transistor is coupled to a drain terminal of said second P-channel transistor; and a second inverter operatively coupled to said P-channel transistor, said second inverter configured to provide a complementary control signal for said P-channel transistor set; a phase detector configured to detect said phase difference; and a feedback delay unit operatively coupled to said coarse delay unit, said fine delay unit, and said phase detector, said feedback delay unit configured to provide a delay upon said output signal to generate said feedback signal.