Patent ID: 8522094

Claim:
An integrated circuit comprising: A. a substrate carrying a serial data input lead, a serial data output lead, a select lead, and a clock lead; B. functional circuitry on the substrate having data input leads and data output leads; C. test access port circuitry on the substrate having a test data input lead connected to the serial data input lead, a test data output lead selectively connected to the serial data output lead, scan circuitry control output leads, a TAP controller having a test mode select input lead selectively coupled to the select lead, a test clock input lead connected to the clock lead, and a buffer enable output lead, the test access port circuitry including a data register having an input connected to the test data input lead and having an output selectively coupled to the test data output lead; D. scan test port circuitry on the substrate having a scan input lead connected to the serial data input lead, a scan output lead selectively coupled to the serial data output lead, a capture select input lead, a scan clock input lead, and a scan register connected between the scan input lead and the scan output lead, the scan register having functional data output and input leads connected to the functional circuitry data input leads and data output leads; E. connection circuitry on the substrate coupling the scan test port circuitry to the test access port circuitry, the connection circuitry having control inputs connected to the scan circuitry control output leads, the select lead, and the clock lead, and the connection circuitry having control outputs connected to the capture select input lead, and the scan clock input lead; F. a first buffer on the substrate having an input connected to the scan output lead, a control input, and an output connected to the serial data output lead; G. a first gate on the substrate having an output connected to the control input of the first buffer, a scan output enable input connected to a scan circuitry control output lead, and a lock out signal input; H. a second buffer on the substrate having an input connected to the test data output lead, an input connected to the buffer enable output lead, and an output connected to the serial data output lead; I. a second gate having an input connected to the select lead, a lock out signal input, and an output connected to the test mode select input lead; and J. a lock out core lead extending from a terminal and connected to the lock out signal input of the first and second gates.