Patent ID: 7941652

Claim:
An apparatus for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU), said apparatus comprising: a trace engine; said trace engine including a set of device control registers (DCRs) accessible by the APU, and a single trace buffer; said set of device control registers (DCRs) including a trace buffer pointer register storing a base address of said trace buffer and an offset indicating a current trace buffer entry and including a base address mask register storing a mask indicating which bits in said trace buffer pointer register hold said base address and which hold said offset; said base address mask register used to determine a wrap point of said trace buffer; a trace instruction; said trace instruction including a primary op code and encoded first and second general purpose registers (GPRs), said first GPR containing an index to said trace engine DCRs and said second GPR indicating a first GPR containing data to be written into a current trace entry in said trace buffer; said data to be written being saved automatically in at least one GPR including said first GPR during normal context switch processing; the APU processes said trace instruction performing the steps of signaling the CPU with a pipeline stall signal for stalling a CPU instruction stream pipeline; responsive to identifying an enabled trace engine for said trace instruction, writing trace data into said single trace buffer utilizing said set of device control registers (DCRs) included in said single trace engine to determine where to write the data into said trace buffer and including writing trace data into said single trace buffer from multiple execution contexts; and signaling the CPU with an op done signal for allowing the CPU to continue with instruction stream pipeline processing.