Patent ID: 7401318

Claim:
A method for performing mask edge fragmentation of an integrated circuit design edge, comprising steps of: (a) making initial edge fragmentation of an IC design edge; (b) performing a process intensity of said IC design edge; (c) building process intensity profiles at ideal edge positions along said IC design edge; said building including: (c1) defining a sign changing region of said IC design edge as follows: (c11) when Δ i =I(p i )−C 0 >0 and Δ i+1 =I(p i+1 )−C 0 <0, i=1, . . . , P edge −1, then (p i , p i+1 ) is said sign changing region of said IC design edge; (c12) when Δ i =I(p i )−C 0 <0 and Δ i+1 =I(p i+1 )−C 0 >0, i=1, . . . , P edge −1, then (p i , p i+1 ) is said sign changing region of said IC design edge; and (c13) when I(p i−1 )<0, I(p i )=0 and I(p i+1 )>0, or when I(p i ) >0, I(p i )=0 and I(p i+1 )<0, i=1, . . . , P edge −1, then p i is a sign changing point, wherein I(p i ) is a process intensity value at an i-th point on said IC design edge; C 0 is a desired intensity value (cutline of an aerial image contour); and P edge is a number of control points on said IC design edge; (c2) adding new fragmentation points corresponding to a new design process intensity of said IC design edge to a list of fragmentation points of said IC design edge; (d) selecting new fragmentation points for said IC design edge; and (e) changing edge fragmentation of said IC design edge.