Patent ID: 8476951

Claim:
A latch circuit, comprising: a first bank of logic gates, each logic gate in the first bank of logic gates having an input coupled to a first input node, having two feedback inputs, having an input coupled to a load enable signal, and having an output; and a second bank of logic gates, each logic gate in the second bank of logic gates having an input coupled to a second input node, having two feedback inputs, having an input coupled to the load enable signal, and having an output; wherein the two feedback inputs of each logic gate in the first bank of logic gates are connected to outputs of two separate logic gates in the second bank of logic gates; wherein the two feedback inputs of each logic gate in the second bank of logic gates are connected to outputs of two separate logic gates in the first bank of logic gates; wherein the output of each logic gate in the first bank of logic gates is connected to a feedback input of each of two logic gates of the second bank of logic gates; wherein the output of each logic gate in the second bank of logic gates is connected to a feedback input of each of two logic gates of the first bank of logic gates; and wherein the latch circuit has an output at the output of one of the logic gates in one of the first and second banks of logic gates.