Patent ID: 8493807

Claim:
A system comprising: a first circuit and a second circuit that are constituted by a semiconductor device, the second circuit controlling the first circuit, wherein the first circuit includes: an interface unit that performs communication with the second circuit; a plurality of sense amplifiers including a first sense amplifier, each of the plurality of sense amplifiers performing communication with the interface unit; a first global bit line; a dummy global bit line; a plurality of first memory blocks that are arranged in a first direction, each of the first memory blocks including a first hierarchy switch that is connected to the first global bit line, and a first local bit line that is connected to the first global bit line via the first hierarchy switch; a dummy memory block including a dummy hierarchy switch that is connected to the dummy global bit line, and a first dummy local bit line that is connected to the dummy global bit line via the dummy hierarchy switch; and a control circuit that controls the first hierarchy switches and the dummy hierarchy switch such that any one of a plurality of the first hierarchy switches and the dummy hierarchy switch are switched on, wherein the first sense amplifier is arranged between the first memory blocks and the dummy memory block, and amplifies a potential difference between the first global bit line and the dummy global bit line, wherein a total number of memory cells connected to a plurality of the first local bit lines allocated to the first sense amplifier is larger than a total number of dummy memory cells connected to the first dummy local bit line, wherein a length of each of the first local bit lines is substantially equal to a length of the first dummy local bit line, wherein a length of the first global bit line is longer than a length of the dummy global bit line, wherein the second circuit includes a logic circuit that controls the first circuit, wherein each of the memory cells and the dummy memory cells includes a series circuit of a cell transistor and a memory element that stores information therein, wherein the cell transistor is constituted by a pillar transistor having a pillar-shaped channel that is substantially perpendicular to a main surface of a semiconductor substrate, and wherein each of the first hierarchy switch and the dummy hierarchy switch is constituted by the pillar transistor.