Patent ID: 8516280

Claim:
A parallel processing computing system comprising: (a) an ordered set of m memory banks including a first and a last memory bank, wherein m is an integer greater than 1; and (b) a processor core that implements: (i) n ordered virtual processors, wherein n is an integer greater than 1, and (ii) a pipeline having p ordered stages, including a memory operation stage, wherein p is an integer greater than 1 and less than or equal to n; and (c) a network-on-chip connected to the processor core and the memory banks through an IO processor, wherein the memory banks are the most local data memory to the processor core, and are connected to the processor core through the IO processor, wherein the processor core clock speed is faster than the memory access rate of the memory banks by an integer multiple k, and a memory bank access causes that bank to be unavailable for k cycles, wherein each virtual processor is assigned in order to one of the memory banks, wherein after the last memory bank is assigned, the next virtual processor is assigned to the first memory bank, and wherein the virtual processors and their respective memory banks are adapted to simultaneously execute independent threads, and each virtual processor is adapted to execute pipeline stages in order, and no virtual processor executes the same pipeline stage as any other virtual processor at the same time.