Patent ID: 6868432

Claim:
An addition circuit for digital data with delayed saturation operation for the most significant digital bits, the circuit comprising: a digital adder for the addition of digital input data values which are present at data inputs of the digital adder to form a summation output data value, which is output at an output of the digital adder, the data inputs having a predetermined data bit width n, and a saturation circuit for limiting the summation output data value present at a data input of the saturation circuit within a data value range which is determined by an upper threshold data value and a lower threshold data value, the n−m least significant data bits of the summation output data value being present directly with a clock signal at the data input of the saturation circuit and the m most significant data bits of the summation output data value being switched through only with an inverted clock signal proceeding the clock signal at the data input of the saturation circuit a clock-state-controlled latch register.