Patent ID: 7948816

Claim:
A memory comprising: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data, said plurality of data storage cells being arranged in an array; a plurality of said arrays; each of said arrays comprising detecting circuitry for detecting and outputting stored data in response to a control signal received at said detecting circuitry; delay circuitry for providing a delay to said control signal sent to said detecting circuitry of at least some of said plurality of arrays, said delay provided to said control signal being longer for at least one array located relatively closer to said input and said output of said memory than to at least one array located relatively further from said input and said output of said memory, wherein said input is for receiving an input control signal for controlling access to data stored in said memory; and said output is for outputting data from said memory in response to said input control signal; said memory further comprising: input data communication circuitry for providing data communication of said input control signal to said plurality of arrays; output data communication circuitry for providing data communication between said output and said plurality of arrays; wherein said delay circuitry is adapted to provide said delay to said control signal sent to said detecting circuitry of at least some of said arrays that has a value dependent upon at least one of an input delay, said input delay being a time taken for said input control signal to reach said array, and an output delay, said output delay being a time taken for said data from said array to reach said output.