Patent ID: 7701052

Claim:
A device comprising a semiconductor and a power core having an exterior surface on which the semiconductor is mounted wherein the power core comprises: at least one embedded singulated capacitor layer containing multiple embedded singulated individual capacitors wherein said embedded singulated individual capacitors each comprise at least a first electrode and a second electrode and wherein said embedded singulated individual capacitors are positioned proximate the exterior surface of the power core with the first and second electrodes of said embedded singulated individual capacitors each including electrode pads that are exposed on the exterior surface of the power core; at least one planar capacitor laminate embedded within the power core, wherein the at least one planar capacitor laminate has a first electrode and a second electrode, and wherein the first electrodes of said multiple embedded singulated individual capacitors are electrically connected to the first electrode of the at least one planar capacitor laminate and the second electrodes of said multiple embedded singulated individual capacitors are electrically connected to the second electrode of the at least one planar capacitor laminate, such that said embedded singulated individual capacitors are connected in parallel to said at least one planar capacitor laminate and said planar capacitor laminate serves as a low inductance path to supply a charge to said embedded singulated individual capacitors; and wherein the semiconductor has Vcc (power) terminals and Vss (ground) terminals, and Vcc (power) terminals of the semiconductor are connected to first electrodes of the multiple embedded singulated individual capacitors and Vss (ground) terminals of the semiconductor are connected to second electrodes of the multiple embedded singulated individual capacitors.