Patent ID: 8916920

Claim:
A memory structure, having a memory cell region and a non-memory cell region, and comprising: a plurality of memory cells comprising a plurality of first doped regions and a plurality of second doped regions disposed in the memory cell region of a substrate, wherein a plurality of first concave portions are separately present in the plurality of memory cells, one of the plurality of first doped regions is located in a top surfaces of the substrate between two adjacent first concave portions, the plurality of second doped regions is respectively located under bottom surfaces of the plurality of first concave portions, and the plurality of first doped regions and the plurality of second doped regions are at different height levels; a conductive material, continuously extending across the memory cell region and the non-memory cell region, covering the plurality of memory cells, extending into the plurality of first concave portions; and a dielectric structure located between the conductive material and the plurality of first doped regions and between the conductive material and the plurality of second doped regions, and contacted with the plurality of first doped regions and the plurality of second doped regions.