Patent ID: 8437967

Claim:
A method, comprising: selecting a multi-layer reticle having an array of cells arranged in R rows and C columns; defining a full inspection region that includes all cells of said array of cells; using a computer, generating an inspection recipe based on the algorithm: when R is equal to one and C is an integer equal to or greater than two and a cell of said array of cells is a dummy cell that does not define a layer of an integrated circuit chip and said dummy cell is in a first or last position of a row of said array of cells or when C is equal to one and R is an integer equal to or greater than two and a cell of said array of cells is a dummy cell that does not define a layer of an integrated circuit chip and said dummy cell is not in a top or bottom position of a column of said array of cells, then reducing said full inspection region to generate a shrunken inspection region that does not include said dummy cell; and inspecting said shrunken inspection region for defects using a mask inspection tool running said inspection recipe.