Patent ID: 8294137

Claim:
A Spatial Wavefunction Switching (SWS) field-effect transistor device, comprising: a source region, a gate region, and a drain region, wherein said gate region includes a thin gate insulator layer and at least one additional layer configured to serve as an electrical gate contact, said gate region being configured to control charge carrier location in a transport channel, wherein one end of said transport channel is located in proximity to said source region and the other end of said transport channel is located in proximity to said drain region, said transport channel includes a asymmetric coupled quantum well layer having at least two quantum wells and at least two barrier layers, wherein said at least two quantum wells and barrier layers are selected from semiconductor materials and wherein said at least two quantum wells are implemented using materials having a lower energy gap than materials used to implement said barrier layers, wherein said at least two quantum wells including an upper well and a lower well, each of said upper well and said lower well having a well thickness and a well material composition, wherein said upper well and said lower well differ in said well thickness, and wherein said at least two barrier layers include an upper barrier and a lower barrier, said lower barrier being located in proximity to a substrate region, wherein one side of said upper well is located in proximity to said thin gate insulator layer and the other side of said upper well is located in proximity to said upper barrier, and wherein one side of said lower well is located in proximity to said upper barrier and the other side of said lower well is located in proximity to said lower barrier, and wherein said transport channel, includes at least one of said quantum wells and at least one of said barriers and is located on top of a semiconductor layer, wherein said semiconductor layer is hosted on a substrate selected from semiconductor selected from a list of Si, Ge, InP, GaAs, SiC, ZnSe, ZnS, and wherein said drain region includes two contacts electrically isolated from each other, wherein one of said two contacts is connected to said upper well to form a first drain region and the other of said two contacts is connected to said lower well to form a second drain region, and wherein said source region includes at least one contact, wherein said at least one contact is connected to at least one of said upper quantum well and said lower quantum well to form at least one source input.