Patent ID: RE44699

Claim:
A semiconductor integrated circuit device, comprising: a semiconductor chip having a memory cell array region and a peripheral circuit region surrounding the memory cell array region; a plurality of bonding pads disposed on only one a first side of the semiconductor chip on the peripheral circuit region; and a plurality of leads formed on both the one side of the semiconductor chip on which the bonding pads are disposed and a second side of the semiconductor chip opposite the first side on which the bonding pads are disposed for connection with the bonding pads ; the plurality of leads including a first leads group on the first side of the semiconductor chip on which the bonding pads are disposed and a second leads group on the second side of the semiconductor chip opposite the first side on which the bonding pads are disposed; a plurality of bonding wires having a first plurality of bonding wires and a second plurality of bonding wires electrically connecting the first leads group and the second leads group, respectively, with the plurality of bonding pads; wherein the first plurality of bonding wires only cross the peripheral circuit region and; wherein the second plurality of bonding wires or the second plurality of bonding wires and the second leads group cross the memory cell array region .