Patent ID: 7977194

Claim:
A method for fabricating a semiconductor device comprising: forming over a semiconductor substrate a first MISFET including first source/drain regions formed in the semiconductor substrate with a first channel region between them, and a first gate electrode of a polycrystalline silicon formed over the first channel region with a first gate insulation film interposed therebetween, and a second MISFET including second source/drain regions formed in the semiconductor substrate with a second channel region between them, and a second gate electrode formed over the second channel region with a second gate insulation film interposed therebetween, formed of a polycrystalline silicon and having a gate length larger than a gate length of the first gate electrode; forming over the semiconductor substrate with the first MISFET and the second MISFET, a thickness of the first insulating film on an upper surface of the first gate electrode and an upper surface of the second gate electrode being thinner than a thickness of the first insulating film on the first source/drain regions and the second source/drain regions; etching the first insulating film without using a mask, being left on the whole first source/drain regions and the whole second source/drain regions and exposing at least a part of the upper surface of the first gate electrode and a part of the upper surface of the second gate electrode so as to satisfy a relationship of (S1b/S1a)>(S2b/S2a), wherein S1a is an area of the upper surface of the first gate electrode, S1b is an area of the upper surface of the first gate electrode where the first insulating film is removed, S2a is an area of the upper surface of the second gate electrode and S2b is an area of the upper surface of the second gate electrode where the first insulating film is removed; and after etching the first insulating film, depositing a metal film over the exposed upper surface of the first gate electrode and the exposed upper surface of the second gate electrode, and making a thermal processing to substitute the polycrystalline silicon forming the first gate electrode and the polycrystalline silicon forming the second gate electrode with a metal silicide, wherein in the substituting the polycrystalline silicon with the metal silicide, the polycrystalline silicon forming the first gate electrode being totally substituted with the metal silicide and a part of the polycrystalline silicon forming the second gate electrode being substituted with the metal silicide.