Patent ID: 8143101

Claim:
A method of making a semiconductor package, comprising: (a) providing a first substrate having a first surface and a second surface; (b) mounting a first chip onto the first surface of the first substrate, the first chip being electrically connected to the first substrate; (c) forming a plurality of conductive elements on the first surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of protrusions, wherein covering the conductive elements with the mold includes aligning the mold with respect to the conductive elements such that the protrusions of the mold are contacting top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the first surface of the first substrate, the first chip and parts of the conductive elements, wherein a height of the first molding compound is greater than a height of each of the conductive elements, and the first molding compound has a plurality of cavities to expose top ends of the conductive elements.