Patent ID: 7335559

Claim:
A fabricating method for a non-volatile memory, comprising: providing a substrate; defining an active region by forming a plurality of trench isolation structures in the substrate; forming a first conducting type well region; forming a second conducting type shallow doped region in the first conducting type well region, wherein the second conducting type shallow doped region is contiguous to a surface of the substrate; forming at least a pair of stacked gate structures on the substrate of the active region, wherein each stacked gate structure is disposed at a side of the each trench isolation structure, and the stacked gate structure is formed with at least a floating gate layer and a control gate layer on the floating gate layer; forming two second conducting type pocket doped regions in the substrate and at peripheries of the stacked gate structures, wherein each pocket doped region is extended to an underneath of each stacked gate structure; forming two first conducting type drain regions in the two pocket doped regions at the peripheries of the pair of stacked gate structures; removing a portion of the trench isolation structures between the stacked gate structures for a surface of the trench isolation structures to be lower than a bottom of the second conducting type shallow doped region and formed at least two trenches in the substrate; forming a gate dielectric layer on surfaces of the stacked gate structures and an exposed substrate; forming an auxiliary gate layer on the gate dielectric layer between the two stacked gate structures; forming a dielectric layer on the substrate to cover the gate dielectric layer and the auxiliary gate layer, wherein at least two contact window openings are formed in the dielectric layer, and each drain region and a portion of each pocket doped region are exposed by the contact window openings; and forming a plurality conducting plugs in the contact window openings.