Patent ID: 7715256

Claim:
A memory device, comprising: a plurality of externally-accessible terminals; a command decoder configured to receive memory command signals through at least one of the externally accessible terminals, the command decoder configured to generate memory control signals responsive to predetermined combinations of the command signals; an address decoder configured to receive address signals through at least one of the externally accessible terminals, the address decoder configured to generate row and column addressing signals responsive to the address signals; at least one memory array, the at least one memory array configured to write data to and read data from locations corresponding the address signals responsive to the memory control signals; a data path extending between at least one of the plurality of externally accessible terminals and the memory array and configured to couple data signals to and from the memory array; and an active termination circuit configured to set the input impedance of a first plurality of the externally accessible terminals to a predetermined value, the active termination circuit comprising: a respective first controllable impedance device coupled between a first supply voltage and each of the externally accessible terminals in the first plurality, each of the first controllable impedance devices configured to receive an impedance control signal, an impedance of the first controllable impedance devices based at least in part on the impedance control signal; a second controllable impedance device coupled between a second supply voltage and a feedback node, the second controllable impedance device being a different controllable impedance device from the first controllable impedance devices, and the feedback node being different from one of the externally accessible terminals, the impedance of the second controllable impedance device based at least in part on the impedance control signal; a resistance coupled between the feedback node and a third supply voltage, the second controllable impedance device and the resistance configured to produce a feedback voltage at the feedback node; and circuitry configured to generate the impedance control signal based at least in part on the feedback voltage.