Patent ID: 8139477

Claim:
A non-transitory computer readable memory storing a program of instructions that when executed by a processor result in actions comprising: monitoring a state of a self-adjusting multi-tier computer processing system; comparing the state of the self-adjusting multi-tier computer processing system to at least one predetermined criterion; and in response to the comparing, dynamically bypassing at least one computing resource within one of the tiers of the self-adjusting multi-tier processing system by energizing or de-energizing at least one switch so as to route data between tiers of the system in a manner that excludes the at least one computing resource, wherein the self-adjusting multi-tier processing system comprises a multiplicity of tiers arranged hierarchically relative to one another, each tier performing one or more specific sub-sections of an overall processing task performed by the system; in which the said one of the tiers which has the at least one computing resource that is bypassed is an intermediate tier which is neither highest nor lowest in the hierarchical arrangement of tiers.