Patent ID: 7623374

Claim:
A non-volatile memory device, comprising: a plurality of main cells, each of the plurality of main cells arranged at first intersection regions between one of a plurality of word lines and one of a plurality of main bit line pairs; and a plurality of flag cells, each of the plurality of flag cells arranged at second intersection regions between one of the plurality of word lines and a plurality of flag bit line pairs, each of the plurality of flag cells configured to store page information in a manner such that page information associated with main cells corresponding to one of the main bit line pairs is stored in flag cells corresponding to more than one of the flag bit line pairs, wherein a first page information and a second page information corresponding to a first main memory cell and a second memory cell commonly coupled to the one of the plurality main bit lines, are stored to a first flag cell coupled to a first flag bit line and a second flag cell coupled to a second flag bit line, respectively.