Patent ID: 7725608

Claim:
An apparatus comprising: a first memory device register coupled to an I/O (input/output) bus with values set to indicate the presence of a virtual memory device on a peripheral component bus to a computer system; a second memory device register coupled to the I/O bus with values set to indicate the absence of any device on the peripheral component bus to a computer system; a plurality of address registers coupled to the I/O bus to store an address for the virtual memory device; a command register coupled to the I/O bus to receive commands from the computer system and to control memory devices across a memory bus; a network controller coupled to the I/O bus and to a management port to interface with a management console and to interface with the computer system through the I/O bus; a microcontroller to read and write commands in the command register to emulate the operation of the virtual memory device, the microcontroller further to send and receive commands and data to the network controller based on commands in the command register; a switch coupled between the I/O bus and the first and second memory device registers to indicate the presence and absence of the virtual memory device; and an external interface coupled to the switch to operate the switch.