Patent ID: 8700837

Claim:
A field programmable gate array (FPGA) integrated circuit, comprising one or more signal processing engines, each signal processing engine including a signal processing unit having a computation circuit and a plurality of configurable dedicated connection circuits, the plurality of configurable dedicated connection circuits being interconnected with one another through bus-based connections to form a bus architecture, each configurable dedicated connection circuit having a plurality of bus-based inputs, a plurality of bus-based outputs, and a first multiplexer, the first multiplexer having configuration bits for routing a first bus-based input in the plurality of bus-based inputs via a first bus to a first bus-based output in the plurality of bus-based outputs, each configurable dedicated connection circuit being directly connected to a corresponding signal processing unit, each configurable dedicated connection circuit having a second multiplexer, the second multiplexer having configuration bits for routing a second bus-based input in the plurality of bus-based inputs via a second bus to a second bus-based output in the plurality of bus-based outputs.