Patent ID: 8117524

Claim:
A data recovery circuit for generating backup data of actual data with a plurality of memory regions, the data recovery circuit comprising: a write circuit coupled to the plurality of memory regions including: a first parity generation circuit which writes the actual data with even parity to an actual data region defined by one of the plurality of memory regions; and a second parity generation circuit which writes the backup data with odd parity to at least one copy region defined by at least another one of the plurality of memory regions, wherein instead of the backup data, the second parity generation circuit is capable of writing any other actual data with even parity to the at least one copy region; and a read circuit connected to the plurality of memory regions to read data from the actual data region and the at least one copy region, the read circuit including: an even parity checker which detects a parity error in the actual data based on the data read from the actual data region; and at least one odd parity checker which checks whether the data read from the at least one copy region is the backup data.