Patent ID: 7821303

Claim:
A comparator for receiving a plurality of differential voltage pairs and performing a comparison operation, in synchronism with a clock signal, on each difference voltage of the plurality of differential voltage pairs, comprising: an input transistor section for receiving the plurality of differential voltage pairs and performing a predetermined weighting operation and a voltage-current conversion operation on the plurality of differential voltage pairs, thus performing a differential comparison operation on each difference voltage of the plurality of weighted differential voltage pairs, and outputting a differential current pair being a result of the differential comparison; a positive feedback section for receiving the differential comparison result from the input transistor section and, in synchronism with the clock signal, amplifying the received differential comparison result to a predetermined voltage level to output the amplified result as a comparison result of the comparator, when the clock signal is at a predetermined level; and a reset section for resetting both of two connecting portions between the input transistor section and the positive feedback section to a predetermined reset voltage when the clock signal is not at the predetermined level, wherein: the reset section includes a reset voltage generator for generating the predetermined reset voltage; the reset voltage generator includes a replica circuit including at least one circuit portion of a differential pair of a circuit identical to a circuit formed by the input transistor section and the positive feedback section; and the reset voltage generator outputs, as the predetermined reset voltage, a voltage at a connecting portion between the input transistor section and the positive feedback section of the replica circuit.