Patent ID: 8605507

Claim:
A memory comprising: a plurality of sensing nodes and reference nodes; a plurality of strings of memory cells, each string in the plurality being arranged for connection between a corresponding sensing node and a corresponding reference node in the plurality of sensing nodes and reference nodes, and including a string select switch to selectively connect the string to the corresponding bit line; a plurality of word lines and at least one string select line, word lines in the plurality coupled to corresponding memory cells in the plurality of strings and the at least one string select line coupled to corresponding string select switches in the plurality of strings; and logic and circuitry coupled to the plurality of word lines, to the at least one string select line, and to a plurality of bit lines and reference nodes including a program node to program a memory cell in a selected string at a selected word line to establish a programmed cell threshold within a target threshold range, the logic and circuitry configured to apply a program bias pulse, including: applying a program voltage to the selected word line and pass voltages to other word lines in the plurality of word lines, the program voltage and at least one of the pass voltages having first magnitudes during an initial interval of the program bias pulse, and being shifted during a subsequent interval to respective second magnitudes; applying a bit line voltage to the sensing node corresponding to the selected string and a reference voltage to the reference node corresponding to the selected string; and applying a string select voltage to the at least one string select line, the bit line voltage and string select voltage being set to turn on the string select switch during the initial interval of the program bias pulse, and being shifted during the subsequent interval of the program bias pulse to turn off, or to reduce conductivity of, the string select switch.