Patent ID: 8525824

Claim:
A display system comprising: a display panel including source lines, gate lines and pixels provided between the source lines and the gate lines; a gate driver coupled to the gate lines; and a source driver coupled to the source lines, the source driver comprising: a plurality of output circuits coupled to the source lines of the display panel and including a first group of output circuits and a second group of output circuits outputting gradation voltages to respective source lines of the display panel; and a timing circuit coupled to the first and second groups of output circuits to control output timings of the first and second groups of output circuits; wherein, in a first frame, the timing circuit controls the first and second groups according to a first output timing, and in a second, consecutive frame, the timing circuit controls the first and second groups according to a second output timing; in the first output timing, the second group of output circuits output voltages after the first group of output circuits output voltages in a period for outputting voltages to respective source lines of the display panel, and in the second output timing, the first group of output circuits output voltages after the second group of output circuits output voltages in a period for outputting voltages to respective source lines of the display panel.