Patent ID: 7600210

Claim:
A method of modular circuit design for an integrated circuit (IC), comprising: capturing a circuit design having plurality of modules and one or more logic interface macros positioned on a floorplan, each of the plurality of modules being one of a static module or a reconfigurable module, each of the one or more logic interface macros: being positioned at a boundary between a module pair of the plurality of modules; and comprising one or more configurable logic block (CLB) slices having a plurality of pins, a first half of the plurality of pins being located within a first module of the module pair and coupled only to ports of the first module, and a second half of the plurality of pins being located within a second module of the module pair and coupled only to ports of the second module; implementing each of the plurality of modules using information generated from the capturing step; and assembling the plurality of modules using the information generated from the capturing step and information generated from the implementing step.