Patent ID: 8023327

Claim:
A non-volatile semiconductor memory device comprising a NAND string, in which multiple memory cells are connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the memory device has a data read mode performed under the bias condition of: a selected cell in the NAND string is applied with a read voltage; and unselected cells in the NAND string are applied with read pass voltages set to turn on cells without regard to cell data, and wherein in the data read mode, one of the unselected cells adjacent to one of the first and second select gate transistor is applied with a first read pass voltage, two unselected cells adjacent to the selected cell are applied with the first read pass voltage, and the other unselected cells are applied with a second read pass voltage lower than the first read pass voltage.