Patent ID: 7661084

Claim:
A design structure embodied in a computer-readable storage medium used in a design process, the design structure comprising: a data receiver circuit tangibly embodied in the computer-readable storage medium used in the design process, said data receiver circuit for implementing memory storage read data eye stretcher; said data receiver circuit including a plurality of input data paths, each input data path receiving input data and a respective voltage reference level; a pair of data latches coupled to each of the input data paths; said pair of data latches including an even data latch latching even data and an odd data latch latching odd data; control logic selecting one voltage reference level to maximize a data eye for current data being latched based upon a previous data state of latched data; a respective one of said pair of data latches latching said current data responsive to said selected voltage reference level; and wherein said plurality of input data paths includes an odd multiplexer coupled to said odd data latch and an even multiplexer coupled to said even data latch; wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said data receiver circuit.