Patent ID: 8541279

Claim:
A manufacturing method for a semiconductor device, in which a first MOS transistor having a relatively thick gate insulating film and a second MOS transistor having a relatively thin gate insulating film are formed simultaneously, the manufacturing method comprising: forming a pad oxide film on a semiconductor substrate of a first conductivity type; forming a nitride film on the pad oxide film; etching a predetermined region of the nitride film; performing ion implantation of impurities into the semiconductor substrate for later forming an inversion-preventing diffusion layer of the first conductivity type and an offset diffusion layer of a second conductivity type, through an opening region in the nitride film formed by the etching; forming a field insulating film in the opening region where the nitride film is etched and forming the inversion-preventing diffusion layer of the first conductivity type and the offset diffusion layer of the second conductivity type; removing the nitride film and the pad oxide film; forming the relatively thick gate insulating film in contact with an active surface region of the semiconductor substrate; removing the relatively thick gate insulating film from a source region and a drain region of the active surface region of the first MOS transistor and from an inner portion of the active surface region of the second MOS transistor that is spaced apart from a bird's beak portion of the field insulating film and leaving remaining portions of the relatively thick gate insulating film on the active surface region of the second MOS transistor; forming the relatively thin gate insulating film on the remaining portions of the relatively thick gate insulating film and in contact with the active surface region; depositing a polycrystalline silicon film on the relatively thick gate insulating film and the relatively thin gate insulating film; imparting electrical conductivity to the polycrystalline silicon film; etching the polycrystalline silicon film to form a gate electrode, wherein the gate electrode is spaced away from the remaining portions of the relatively thick gate insulating film on a second active surface region; and performing, in a self-aligned manner, ion implantation of impurities into a region which becomes a high concentration diffusion layer of the second conductivity type using the relatively thick gate insulating film as a mask.