Patent ID: 7623131

Claim:
A graphics subsystem comprising: a plurality of graphics processors, each graphics processor having: at least two input/output (I/O) ports, each I/O port being configurable to communicate pixel data into the graphics processor or out of the graphics processor; and a display head configured to generate output pixel data, the display head being connectable to deliver the output pixel data to either of the I/O ports and further connectable to receive pixel data from at least one of the I/O ports; and a plurality of links, each link connecting one of the I/O ports of one of the graphics processors to one of the I/O ports of another one of the graphics processors such that the plurality of graphics processors are connected in a ring topology, wherein each of the plurality of graphics processors is connected by respective links to two others of the plurality of graphics processors, each link being configured to transfer pixel data in at least one direction, and wherein the graphics subsystem is configured to iteratively detect a connection topology among the plurality of graphics processors, wherein for each graphics processor the graphics subsystem is further configured to: select a first graphics processor from the plurality of graphics processors; configure a first I/O port of the first graphics processor as an output port; configure a second I/O port of the first graphics processor as an input port; configure the at least two I/O ports of the graphics processors of the plurality of graphics processors other than the first graphics processor as input ports; configure the first I/O port of the first graphic processor to assert test pixel data; configure the plurality of graphics processors other than the first graphics processor to detect the test pixel data received via the input ports; and identify graphics processors that detect the test pixel data as being connected to the first graphics processor.