Patent ID: 7457388

Claim:
A redundant synchronous clock distribution system, comprising: at least first and second clock modules, first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system, each of the first and second clock modules adapted to act, in a master mode, as a master clock module for providing one of said clock distribution branches with an active clock signal, and adapted to act, in a slave mode, as a slave clock module for providing the respective other of said clock distribution branches with a standby clock signal, a clock switchover module adapted to switch each of the first and second clock modules to change between the master mode and the slave mode, wherein said clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part, said first circuit part of said flip-flop-circuit located on said first clock module and said second circuit part of said flip-flop-circuit located on said second clock module, wherein said first circuit part of said flip-flop-circuit comprises a first logical gate, said first logical gate having a first input adapted to receive a first request signal which indicates a demand to change between the master mode and the slave mode, said first logical gate having a second input coupled to said second circuit part of the flip-flop-circuit, said first logical gate having an output adapted to output a first command signal which indicates the current master or slave status of the first clock module.