Patent ID: 7088132

Claim:
A programmable logic device (PLD) comprising a serial data interface, the serial data interface including: a first pin adapted to transmit a chip select signal from within the PLD directly to a first pin of a serial PROM; a second pin adapted to transmit a configuration clock signal from within the PLD directly to a second pin of the serial PROM; a third pin adapted to transmit a read command and an address signal from within the PLD directly to a third pin of the serial PROM, and a fourth pin adapted to receive a configuration bitstream directly from a fourth pin of the serial PROM, the PLD including one or more of the following configuration modes: a first configuration mode wherein the read command transmitted from the third pin is hardwired within the PLD; and a second configuration mode wherein the read command transmitted from the third pin is user programmable within the PLD.