Patent ID: 7974055

Claim:
An integrated circuit comprising: a protection circuit device receiving a current or a voltage during a plasma-related manufacturing process of the integrated circuit, and an integrated circuitry being protected by said protection circuit device, the protection circuit device comprising: a single protection transistor, a single circuitry formed by a plurality of the single protection transistors, or a circuitry network formed by a plurality of said single circuitries, wherein the protection transistors are enhancement-mode N-channel MOSFETs, having a thick-gate oxide and a small negative threshold voltage of less than 100 milivolts; a coupling of a poly resistor to a gate of the protection transistor, the poly resistor being coupled to a wafer substrate, to maintain the protection transistor gate, which is exposed to plasma, at nearly substrate potential during plasma process; a protection node coupling the drain of the protection transistor to a gate of a protected transistor and a coupling of the source of the protection transistor to its substrate to dissipate negative plasma charges at the protection node through a forward-biased drain-to-substrate junction of the protection transistor, and to dissipate positive plasma charges at the protection node through the gate channel current from drain to source to substrate of the protection transistor during plasma process; a coupling of the gate of the protection transistor to a power supply to turn off the protection transistor during circuit operation; and a coupling of two or more gates of the protection transistors in a protection circuitry or a protection circuitry network.