Patent ID: 7180824

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells which are provided correspondingly to an address signal that consists of high order and low order address signals designated by first and second bit numbers; a read control part reading a prescribed number of memory cell information from said memory cell array based on said high order address signal; a sense amplifier performing a sense amplifying operation on each of said prescribed number of memory cell information to obtain a prescribed bit number of sense data; a latch for sense data latching said prescribed bit number of sense data at timing indicated by a first latch signal; a latch for page data latching said prescribed bit number of sense data stored in said latch for sense data as page data at timing indicated by a second latch signal, said page data being classifiable under n partial page data correspondingly to said low order address signal; a page mode control circuit outputting said first and second latch signals; and a selector circuit outputting said n partial page data as page selection data sequentially based on said low order address signal that changes n times during a page mode reading period, said page selection data being output as external data, after a first memory cell information group which is said prescribed number of memory cell information read from said memory cell array based on said high order address signal that defines a first address is latched into said latch for page data as said page data via said sense amplifier and said latch for sense data, said page mode control circuit performing a bit reversal process reversing prescribed bits in said first address defined by said high order address signal to generate a second address successive to said first address, during said page mode reading period based on said first memory cell information group, said page mode control circuit storing a second memory cell information group which is said prescribed number of memory cell information read from said memory cell array based on said high order address signal that defines said second address in said latch for sense data as said prescribed bit number of sense data via said sense amplifier, and after said page mode reading period based on said first memory cell information group has elapsed, said page mode control circuit latching said prescribed bit number of sense data based on said second memory cell information group stored in said latch for sense data into said latch for page data as said page data, thereby setting a page mode reading period based on said second memory cell information group after said page mode reading period based on said first memory cell information group.