Patent ID: 8130890

Claim:
A system comprising: a data processing unit configured to inactivate and fix a data clock and transferring a command for the performance of a clock alignment training and the data clock; and a semiconductor memory device configured to generate a clock alignment training signal in response to the command and dividing a frequency of the data clock in half in response to the clock alignment training signal to align phases of the data clock of which the frequency is half-divided and a system clock and, wherein the semiconductor memory device comprises: a training decoder configured to generate the clock alignment training signal by decoding a command and an address of a mode register set corresponding to the command; and a frequency divider, which is reset in response to an output of the training decoder, configured to receive an internal data clock to divide a frequency of the internal data clock in half, a data transfer between the semiconductor memory device and the data processing unit is aligned after operations of the training decoder and the frequency divider are preformed.