Patent ID: 8587060

Claim:
A semiconductor device comprising: a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer of which n-type impurity concentration is less than that of the first n-type silicon carbide layer; a first p-type impurity region formed in the second n-type silicon carbide layer; a first n-type impurity region of 4H-SiC structure formed in the second n-type silicon carbide layer; a second n-type impurity region of 3C-SiC structure formed in the second n-type silicon carbide layer and having a depth shallower than that of the first n-type impurity region; a gate insulating film extending over surfaces of the second n-type silicon carbide layer, the first p-type impurity region, and the first n-type impurity region; a gate electrode formed on the gate insulating film; a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion, the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion; and a second p-type impurity region, the second p-type impurity region connected to the first p-type impurity region and having a depth shallower than that of the first p-type impurity region and having a p-type impurity concentration higher than that of the first p-type impurity region, wherein the metallic silicide layer is formed on the second p-type impurity region.