Patent ID: 8806110

Claim:
A memory management system comprising: a memory organized as a plurality of programmable memory segments, said memory segments having a strict priority, a plurality of requestors operable to originate memory access requests wherein the request includes a logical memory address to be accessed, a descriptor of the requested access and a permission field containing a plurality of bits indicating the access permissions associated with the request, an extended memory controller connected to said plural memory segments of said memory and to said plural requestors operable to control access to said memory, said extended memory controller including a segment register associated with each memory segment operable to store parameter fields defining the memory segment including a set of upper bits of a memory starting address, memory size and a plurality of permission bits, and a set of replacement address bits, a comparison circuit operable to compare the memory address range in the segment registers as defined by the upper bits of the starting address and memory size of each segment register, and the logical memory address provided as part of the memory access request provided by the requestor, and further operable to select a segment register corresponding to a memory section having the highest priority having the requested address is within said memory address range of the selected segment register, and a logic circuit granting a memory access request if said plurality of permission bits of said selected segment register permit access to said access permissions associated with said request, said logic circuit generating an access address by replacing said upper bits of said logical memory address with said replacement address bits while retaining lower bits of said logical memory address of said memory access request.