Patent ID: 7351650

Claim:
A method for fabricating a chip comprising: providing a silicon substrate, an ESD circuit in or on said silicon substrate, a driver, receiver or I/O circuit in or on said silicon substrate, a first internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit and to a first terminal of said driver, receiver or I/O circuit, and wherein said ESD circuit is connected, in parallel with said driver, receiver or I/O circuit, to said first interconnecting structure, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to a second terminal of said driver, receiver or I/O circuit, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said first internal circuit, wherein said first, second and third interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process, and a passivation layer over said dielectric layer; and forming a fourth interconnecting structure over said passivation layer, wherein said second terminal is connected to said first internal circuit through, in sequence, said second interconnecting structure, said fourth interconnecting structure and said third interconnecting structure, and wherein said forming said fourth interconnecting structure comprises: forming a first metal layer; after said forming said first metal layer, forming a patterned photoresist layer; after said forming said patterned photoresist layer, electroplating a second metal layer; after said electroplating said second metal layer, removing said patterned photoresist layer; and after said removing said patterned photoresist layer, etching said first metal layer.