Patent ID: 7220600

Claim:
A method of fabricating a ferroelectric capacitor structure in a semiconductor device, the method comprising: forming a lower electrode diffusion barrier structure over a dielectric material, the lower electrode at least partially engaging a conductive structure in the dielectric material; forming a lower electrode over the lower electrode diffusion barrier structure; forming a ferroelectric material over the lower electrode; forming an upper electrode over the ferroelectric material; forming a patterned etch mask over the upper electrode, the patterned etch mask exposing a portion of the upper electrode; etching portions of the upper electrode, the ferroelectric material, and the lower electrode to define a patterned ferroelectric capacitor structure using the patterned etch mask; etching a portion of the lower electrode diffusion barrier structure using the patterned etch mask; ashing the patterned ferroelectric capacitor structure using a first ashing process; performing a wet clean process after the first ashing process; and ashing the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a temperature of about 300 degrees C. or more in an oxidizing ambient; wherein the second ashing process is performed using a gas ambient with a primary gas comprising O2 gas; wherein the second ashing process is performed at a temperature of about 300 degrees C. or more and about 350 degrees C. or less for about 2 minutes or more and about 3 minutes or less; and wherein the first ashing process, the wet clean process, and the second ashing process are performed after etching portions of the upper electrode, the ferroelectric material, and the lower electrode and before etching the portion of the lower electrode diffusion barrier structure.