Patent ID: 6977427

Claim:
An electronic component, comprising: a chip stack including a first semiconductor chip having an active surface and a second semiconductor chip having an active surface; a plurality of flat conductors, each one of said plurality of flat conductors including an inner section, a central section, a transitional section, and an outer section, said inner section of each one of said plurality of flat conductors and said central section of each one of said plurality of flat conductors configured between said first semiconductor chip and said second semiconductor chip; a package; a plurality of first bonding connections; and a plurality of second bonding connections; said first semiconductor chip having a plurality of contact surfaces; said second semiconductor chip having a plurality of contact surfaces; said contact surfaces of said first semiconductor chip and said second semiconductor chip being disposed at mutually congruent positions; a first interposer layer or interposer film configured on said active surface of said first semiconductor chip, said first interposer layer or interposer film having first bonding fingers, first interposer lines and first bonding surfaces; and a second interposer layer or interposer film configured on said active surface of said second semiconductor chip, said second interposer layer or interposer film having second bonding fingers, second interposer lines and second bonding surfaces; each one of said plurality of first bonding connections connecting one of said first bonding surfaces on said first interposer layer or interposer film to said inner section of one of said plurality of flat conductors; and each one of said plurality of second bonding connections connecting one of said second bonding surfaces on said second interposer layer or interposer film to said transitional section of one of said plurality of flat conductors.