Patent ID: 7791523

Claim:
A two-step sub-ranging analog-to-digital converter (ADC) comprising: a first sampler/buffer circuit configured obtain odd samples of an analog input signal, ADC_IN, during odd phases of a first clock signal, ADC_CLK; a second sampler/buffer circuit configured to obtain even samples of the analog input signal ADC_IN during even phases of the first clock signal ADC_CLK; a first multiplexer (MUX) configured to select an odd sample obtained by the first sampler/buffer circuit at a first instant in time and to select an even sample obtained by the second sampler/buffer circuit at a second instant in time; a second MUX configured to select an even sample obtained by the second sampler/buffer circuit at the first instant in time and to select an odd sample obtained by the first sampler/buffer circuit at the second instant in time; a coarse ADC (CADC) circuit, the CADC circuit being configured to receive samples selected by the first MUX and to process the received samples to produce CADC decision values; a fine ADC (FADC) circuit, the FADC circuit being configured to receive samples selected by the second MUX and to process the received samples to produce FADC decision values; a sub-ranging MUX circuit coupled to an input of the FADC circuit, the sub-ranging MUX circuit being configured to sub-range the FADC circuit; and an encoder configured to process the CADC and FADC decision values to produce output ADC values.