Patent ID: 8229111

Claim:
A security circuit, comprising: at least two finite state machine units, storing data to and reading data from a multiport memory in a pipelined manner; and an intermediate memory, for facilitating transfer of data between the at least two finite state machine units, wherein the at least two finite state machine units include, a read finite state machine unit configured to read the data from the multiport memory in the pipelined manner and output the data to the intermediate memory, and a write finite state machine unit configured to receive the data from the intermediate memory and write the data to the multiport memory in the pipelined manner, the read finite state machine is configured to supply a first command and a first address to the multiport memory, the write finite state machine is configured to supply a second command and a second address to the multiport memory, the read and write finite state machines are configured to operate simultaneously with the multiport memory, and the intermediate memory includes a plurality of registers for storing previous addresses to access the multiport memory or temporary substitution box (Sbox) data for encryption/decryption.