Patent ID: 8589759

Claim:
An error detection and correction (EDAC) circuit for use in a redundant memory system, the EDAC circuit comprising: a first input for receiving first data and parity information stored by a first memory device; a second input for receiving second data and parity information stored by a second memory device, wherein the second data and parity information stored by the second memory device mirrors the first data and parity information stored by the first memory device; a first output for providing either the first data or the second data onto a data bus; first parity check logic that calculates whether parity is ‘good’ or ‘bad’ in the received first data and parity information; second parity check logic that calculates whether parity is ‘good’ or ‘bad’ in the received second data and parity information; bit comparison logic that detects differences between the first data and the second data, and between the first parity information and the second parity information; and data select logic that selects either the first data or the second data for supplying to the first output based on the calculated parity of the first data and the second data and the differences between the first data and the second data, and between the first parity information and the second parity information.