Patent ID: 8669561

Claim:
A semiconductor device comprising: a semiconductor substrate made of silicon carbide in which an angle between a normal vector of a substrate surface and an orientation <0001> or <000-1> is 0° or more and 8° or less; a first conductivity type semiconductor layer made of silicon carbide formed on the semiconductor substrate; an active area formed on a surface of the semiconductor layer; a first semiconductor area of a second conductivity type having an impurity concentration and depth, formed on the surface of the semiconductor layer to surround the active area; a second semiconductor area, provided to adjoin an outer side of the first semiconductor area on the surface of the semiconductor layer and surround the first semiconductor area, in which a second conductivity type impurity area having the same impurity concentration and the same depth as those of the first semiconductor area is formed in a mesh shape; a third semiconductor area of the second conductivity type formed around the first semiconductor area and the second semiconductor area and having a depth and impurity concentration; a first electrode provided on the active area; and a second electrode provided on a rear surface of the semiconductor substrate, wherein, where γdenotes a relative permittivity of silicon carbide, Ec 1 and Ec 2 denote breakdown electric field intensities of silicon carbide in the orientation <0001> and <11-20>, respectively, and q denotes an electric charge elementary quantum, a depthwise integral value of the impurity concentration of the first semiconductor area is set to be 0.8 γEc 1 /q or more and 1.2 γEc 1 /q or less, and the value obtained by averaging the depthwise integral value of the impurity concentration of the impurity area within the second semiconductor area is 0.4 γEc 2 /q or more and 1.1 γEc 2 /q or less, and a depthwise integral value of the impurity concentration of the third semiconductor area is 0.4 γEc 2 /q or more and 1.1 γEc 2 /q or less.