Patent ID: 8527684

Claim:
A method for allocating on chip bus transactions between multiple masters and one or more of multiple slaves in a system on chip (SoC) using inner characteristic information of the on chip bus transactions based on the multiple masters and the multiple slaves, wherein: the SoC includes the multiple masters, the multiple slaves, and an interconnect module; the multiple masters and the multiple slaves are connected to the interconnect module via multiple buses; the multiple masters, the multiple slaves, and the interconnect module are further coupled via an inner characteristic bus, wherein the inner characteristic bus is separate from the multiple buses in the SoC, and the inner characteristic bus does not convey any of the on chip bus transactions from any of the multiple masters; and allocating the on chip bus transactions comprises: the interconnect module receiving, via the multiple buses, the on chip bus transactions substantially simultaneously from the multiple masters to be processed on one or more of the multiple slaves; the interconnect module receiving, via the inner characteristic bus, inner characteristic information of the on chip bus transactions based on the multiple masters and the one or more of the multiple slaves; and the interconnect module allocating the received on chip bus transactions from the multiple masters to associate one or more of the multiple slaves based on the received inner characteristic information of the on chip bus transactions.