Patent ID: 8639884

Claim:
A method comprising: in a computer system executing multiple program threads in a processing unit: configuring a first load/store execution unit to handle instructions from a first program thread; configuring a second load/store execution unit to handle instructions from a second program thread; in the computer system executing a single program thread in the processing unit: configuring the first and second load/store execution units to handle instructions from the single program thread; configuring a Level 1 (L1) data cache with a first port to communicate with the first load/store execution unit and a second port to communicate with the second load/store execution unit; adding a second tag array for the first L1 data cache, wherein the first load/store execution unit uses a first tag array to access the first L1 data cache and the second load/store execution unit uses the second tag array to access the first L1 data cache; for every load/store instruction from the first and second load/store execution units, maintaining duplicate data and address information in a first load/store buffer associated with the first load/store execution unit and in a second load/store buffer associated with the second load/store execution unit.