Patent ID: 8525568

Claim:
A clock generation circuit, comprising: a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator, wherein the RS trigger outputs clock signals to an input control terminal of the first demux circuit and an input control terminal of the second demux circuit, when the first demux circuit is enabled, the capacitor is charged by the second current source, and when the second demux circuit is enabled, the capacitor is discharged by the second current source, wherein the resistance of the resistor is R, the first current source is proportional to 1 R 2 , and the second current source is proportional to 1 R .