Patent ID: 6936386

Claim:
A reticle alignment procedure employed on a semiconductor wafer, a surface of the semiconductor wafer comprising a cell pattern area and a minor pattern area, the minor pattern area comprising at least one pre-layer wafer alignment mark (pre-layer wafer AM) transferred onto the semiconductor wafer from a pre-layer reticle alignment mark (pre-layer reticle AM) on a pre-layer reticle, the reticle alignment procedure comprising: providing a current-layer reticle, the current-layer reticle comprising at least one current-layer reticle alignment mark (current-layer reticle AM) and a circuit pattern; performing a baseline check (BCHK) to align the current-layer reticle AM with the pre-layer wafer AM; capturing and comparing image signals of the current-layer reticle AM and the pre-layer wafer AM to calibrate a corresponding coordinate of the current-layer reticle to the semiconductor wafer; and performing a lithography process to simultaneously transfer layouts of the circuit pattern and the current-layer reticle AM onto the semiconductor wafer to form a current-layer wafer alignment mark (current-layer wafer AM) within the minor pattern area of the semiconductor wafer corresponding to the current-layer reticle alignment mark.