Patent ID: 7615433

Claim:
A method of fabricating a semiconductor device comprising: providing a substrate having a NFET transistor in a NFET region in the substrate, and a PFET transistor in a PFET region in the substrate; forming a first contact etch-stop liner over the NFET region, the first etch-stop liner having a tensile stress; performing a first deuterium anneal at a first temperature after forming the first contact etch-stop liner; forming a second contact etch-stop liner over the PFET region after performing the first deuterium anneal, the second etch-stop liner having a compressive stress; forming a dielectric layer over the substrate; forming a contact opening in the dielectric layer; and performing a second deuterium anneal at a second temperature after forming the second etch-stop liner, the second temperature is lower than the first temperature, wherein the second deuterium anneal does not relax the compressive stress of the second etch-stop liner.