Patent ID: 8040079

Claim:
A circuit comprising: a signal input to receive an input signal; a digital output to provide a multiple-bit digital value; a plurality of level detect units, each level detect unit comprising: a comparator comprising a first input to receive the input signal, a second input to receive a corresponding reference voltage of a plurality of reference voltages, an output to configure a comparator signal based on a comparison of the input signal to the corresponding reference voltage, and an enable input to receive a local enable signal; and a flip-flop comprising a data input fixed to a predetermined first data state, a clock input coupled to the output of the comparator, a reset input to receive a reset signal, and a first data output to provide a first data signal, the flip-flop to: responsive to the reset signal having a first reset state, configure the first data signal to a second data state that is the complement of the first data state; responsive to the comparator signal having a first comparator state while the reset signal has a second reset state, configure the first data signal to the first data state and maintain the first data signal at the first data state until the reset signal is reconfigured to the first reset state; and responsive to the comparator signal having a second comparator state while the reset signal has the second reset state, maintain a present data state of the first data signal until the reset signal is reconfigured to the first reset state; and an enable circuit to configure the local enable signal to selectively disable the comparator based at least in part on the first data signal.