Patent ID: 8214660

Claim:
A design structure embodied in a nontransitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a plurality of processor cores situated on a semiconductor die, each processor core including a respective temperature sensor that senses the temperature thereof; and a core power controller, coupled to the plurality of processor cores, situated on the semiconductor die, the core power controller being capable of receiving temperature information from each processor core, the core power controller disabling the processor cores whose temperatures exceed a first predetermined temperature value, the core power controller disabling first selected processor cores during a first power control time interval while other processor cores remain enabled, the core power controller disabling second selected processor cores during a second power control time interval following the first power control time interval, the second selected processor cores of the second power control time interval being different from the first selected processor cores of the first power control time interval, the core power controller disabling other selected processor cores during successive power control time intervals that follow the second time power control interval to form a complete cycle wherein all processor cores have been disabled once.