Patent ID: 7893722

Claim:
State storage circuitry comprising: tristate scan signal insertion circuitry responsive to a scan input signal, a first clock signal, a second clock signal and a scan enable signal, said tristate scan signal insertion circuitry comprising transistors controlled by said scan enable signal and a complement of said scan enable signal to control said tristate scan signal insertion circuitry to drive a storage signal in dependence upon said scan input signal at a scan capture time controlled by said first clock signal and said second clock signal when said scan enable signal is asserted; tristate logic circuitry responsive to one or more functional input signals, a third clock signal and a fourth clock signal to drive said storage signal dependent upon said one or more functional input signals at a functional capture time controlled by said third clock signal and said fourth clock signal; signal storing circuitry responsive to said storage signal to set a value of a stored signal in dependence upon a value of said storage signal, said value of said stored signal being held by said signal storing circuitry; and clock signal generating circuitry providing said first clock signal, said second clock signal, said third clock signal and said fourth clock signal, said third clock signal and said fourth clock signal being held at fixed values that control said tristate logic circuitry to a state in which said storage signal is not driven by said tristate logic circuitry when said scan enable signal is asserted.