Patent ID: 8495418

Claim:
A system comprising: a memory; and a processor comprising a plurality of cores, the plurality of cores being partitioned into at least a first partition and a second partition, wherein a first set of cores from the plurality of cores is allocated to the first partition and a second set of cores from the plurality of cores is allocated to the second partition, the first set of cores being different from the second set of cores; wherein the first partition is configurable to operate in a first mode, wherein a set of functions is performed in the first mode; wherein, when the first partition is operating in the first mode, the second partition is configurable to operate in a second mode, wherein the set of functions is not performed in the second mode; wherein, in response to an event, the second partition is configurable to start operating in the first mode instead of the first partition and to start performing the set of functions corresponding to the first mode; and wherein the first partition is configurable to operate in the second mode after the second partition operates in the first mode.