Patent ID: 7038497

Claim:
A differential phase and frequency detector comprising: a first power rail and a second power rail for providing power to said differential phase and frequency detector; a differential logic gate having a first gate input for receiving a first gate input signal, a second gate input for receiving a second gate input signal, a third gate input for receiving a third gate input signal, a fourth gate input for receiving a fourth gate input signal, a first gate output for producing a first gate output signal, and a second gate output for producing a second gate output signal, wherein said first and second gate input signals are the logic compliments of each other, said third and fourth gate input signals are the logic compliments of each other, said first gate output signal is the logical AND of said first and third gate input signals and is the logical NOR of said second and fourth gate input signals, and said second gate output signal is the logical OR of said second and fourth gate input signals and is the is the logical NAND of said first and third gate input signals; a first differential latch having a first latch input, a second latch input, a first clock input, a second clock input, a first reset input, a second reset input, a first latch output, and a second latch output; and a second differential latch having third latch input, a fourth latch input, a third clock input, a fourth clock input, a third reset input, a fourth reset input, a third latch output, and a fourth latch output; wherein: said first and third latch inputs are coupled to a logic high level; said second and fourth latch inputs are coupled to a logic low level; said first clock input is coupled to receive a first frequency signal; said second clock input is coupled to receive a first complement frequency signal, said first complement frequency signal being the logic complement of said first frequency signal; said third clock input is coupled to receive a second frequency signal; said fourth clock input is coupled to receive a second complement frequency signal, said second complement frequency signal being the logic complement of said second frequency signal; said first gate output is coupled to said first and third reset inputs and said second gate output is coupled to said second and fourth reset input; said first latch output is coupled to said first gate input and said second latch output is coupled to said second gate input, said second latch output being the logic complement of said first latch output; and said third latch output is coupled to said third gate input and said fourth latch output is coupled to said fourth gate input, said fourth latch output being the logic complement of said third latch output.