Patent ID: 7186644

Claim:
A method for preventing oxidation of a copper interconnect of a semiconductor device, comprising: forming a lower copper interconnect on a substrate having at least one predetermined structure; depositing a nitride layer on the lower copper interconnect and on the substrate; sequentially depositing a first insulating layer, an etch stop layer, and a second insulating layer on the nitride layer; forming a trench and a via hole through the second insulating layer and the first insulating layer by using a dual damascene process; etching the nitride layer so as to expose some portion of the lower copper interconnect; and supplying combining gas onto the exposed portion of the lower copper interconnect, wherein the combining gas combines with the copper of the exposed portion of the lower copper interconnect, wherein supplying the combining gas is carried out under conditions of time 20 sec/gap 30 mm/N 2 240 sccm/upper power 700 W/bottom power 70 W bottom temperature 20° C./cooling He edge 25 T/center 15 T at an error range of about 10%.