Patent ID: 7521322

Claim:
A method of forming an integrated circuit including a vertical transistor comprising: defining a ridge in a ridge region and a trench adjacent to the ridge in a substrate; forming a bit line within the trench; depositing an insulating material in the trench to isolate the bit line; forming a transistor pillar over the ridge region after depositing the insulating material in the trench, wherein the ridge is adjacent to the trench and extends from a bottom level of the trench to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, wherein the transistor pillar extends upwardly from the shoulder of the ridge, wherein the trench extends from the bottom level to the shoulder, and wherein the bit line is below the shoulder within the trench; exposing a portion of the bit line adjacent to the ridge region after forming the transistor pillar; creating a bit line stitch within the trench connecting the bit line to a lower active area within the ridge region after exposing the portion of the bit line, providing the lower active area to comprise one source/drain region of the vertical transistor; forming a gate surrounding the transistor pillar after creating the bit line stitch; and providing a lower portion of the pillar to comprise a channel region of the vertical transistor and providing an upper region of the pillar to comprise another source/drain region of the vertical transistor.