Patent ID: 8344265

Claim:
An electronic component comprising: a common substrate; at least two elements mounted on a first main surface of the common substrate and arranged adjacent to each other on the first main surface of the common substrate along a first direction; a conductive pattern provided on the first main surface of the common substrate and including a plurality of lands arranged so as to extend in the first direction along which the at least two elements mounted on the first main surface of the common substrate are arranged adjacent to each other, the plurality of lands being disposed at positions corresponding to terminals of the at least two elements mounted on the first main surface of the common substrate; insulating films provided at least on the conductive pattern so as to be spaced apart from and not in contact with both side edges of the lands in a direction perpendicular or substantially perpendicular to a land extending direction and adjacent to and in contact with both ends of the lands in the land extending direction; and solder bumps disposed on the lands and arranged to connect the lands and the terminals of the elements.