Patent ID: 7716564

Claim:
A decoder that is operative to perform radix-4 SOVA (Soft Output Viterbi Algorithm) decoding of a signal, the decoder comprising: an ACS (Add Compare Select) module operatively coupled to: output a first hard decision for a bit within the signal corresponding to a current trellis stage and a second hard decision for a bit within the signal corresponding to a previous trellis stage located one trellis stage from the current trellis stage; and output a first reliability of the first hard decision and a second reliability of the second hard decision; and a REX (Register Exchange) module operatively coupled to: receive the first hard decision, the first reliability, the second hard decision, and the second reliability; simultaneously process the first hard decision, the first reliability, the second hard decision, and the second reliability thereby simultaneously calculating: a first survivor path for a first trellis transition from a previous trellis stage located two trellis stages from the current trellis stage to a previous trellis stage located one trellis stage from the current trellis stage; and a second survivor path for a second trellis transition from a previous trellis stage located one trellis stage from the current trellis stage to the current trellis stage; and wherein: the decoder employs at least one of the first survivor path and the second survivor path to make a best estimate of at least one information bit encoded within the signal.