Patent ID: 8507975

Claim:
A semiconductor device comprising: a first nonvolatile memory cell formed over a semiconductor substrate; and a second nonvolatile memory cell formed over the semiconductor substrate, wherein the first nonvolatile memory cell has a first gate insulating film formed over the semiconductor substrate, a first control gate electrode formed over the first gate insulating film, a second gate insulating film formed over the semiconductor substrate and over a first side wall of the first control gate electrode, a first memory gate electrode formed over the second gate insulating film and arranged adjacent with the first control gate electrode through the second gate insulating film, a first source region formed in the semiconductor substrate and positioned on a first control gate electrode side of the first memory cell, and a first drain region formed in the semiconductor substrate and positioned on a first memory gate electrode side of the first memory cell, wherein the second nonvolatile memory cell has a third gate insulating film formed over the semiconductor substrate, a second control gate electrode formed over the third gate insulating film, a fourth gate insulating film formed over the semiconductor substrate and over a second side wall of the second control gate electrode, a second memory gate electrode formed over the fourth gate insulating film and arranged adjacent with the second control gate electrode through the fourth gate insulating film, the first drain region positioned on a second memory gate electrode side of the second memory cell, and a second source region formed in the semiconductor substrate and positioned on a second control gate electrode side of the second memory cell, wherein the first memory cell and the second memory cell are formed adjacent to one another in a first direction, with the first drain region shared between them, wherein the second gate insulating film and the fourth gate insulating film include a charge storage film, respectively, wherein the first memory gate electrode and the second memory gate electrode are not electrically connected and are formed in the form of a side wall, and wherein the first memory gate electrode and the second memory gate electrode are capable of being applied with a gate signal independently in a case of a write operation of the first memory cell or the second memory cell.