Patent ID: 7206886

Claim:
A method comprising: receiving at a bus interface data having a first data ordering; automatically translating the received data at the bus interface from the first data ordering to a second data ordering, wherein the first data ordering and the second data ordering are each a different one of a linear data ordering and an interleaved data ordering; wherein the data is received at the bus interface pursuant to a request, and wherein the method further comprises obtaining from the request a start address and a size of data associated with the request to be translated, and employing the start address and the size of the data during the automatically translating of the data from the first data ordering to the second data ordering; and wherein the second data ordering is the interleaved data ordering, and the bus interface includes at least one data buffer comprising a plurality of registers, and wherein the method further includes outputting data with the interleaved data ordering in successive unload data cycles from the plurality of registers of the at least one data buffer by exclusive ORing the start address of the data with a current value of an unload address generator, wherein the unload address generator is initialized to zero and is incremented with each successive unload data cycle of the outputting of the data.