Patent ID: 8552959

Claim:
A shift register, comprising: a first thin film transistor having a gate and a drain connected together to a trigger signal terminal, and a source connected to a first node as a pull-up node; a second thin film transistor having a gate connected to the first node, a drain connected to a clock signal terminal, and a source connected to an output terminal of the present stage; a third thin film transistor having a gate connected to the clock signal terminal, a drain connected to the first node, and a source connected to the output terminal of the present stage; a fourth thin film transistor having a gate connected to a feedback signal terminal, a drain connected to the first node, and a source connected to a low level signal terminal; a fifth thin film transistor having a gate connected to the feedback signal terminal, a drain connected to the output terminal of the present stage, and a source connected to a low level signal terminal; a capacitor, connected between the first node and the output terminal of the present stage; a first operation modular, connected between a first operation signal terminal and the first node, and connected to the low level signal terminal; and a second operation modular, connected between a second operation signal terminal and the first node, and connected to the low level signal terminal, wherein, the first operation modular and the second operation modular are alternatively operated, and the first operation modular and the second operation modular are used to maintain both of the gate and source of the second thin film transistor at low level respectively, when the shift register is not operated.