Patent ID: 7260009

Claim:
A semiconductor integrated circuit comprising a logic circuit and a plurality of semiconductor memory devices formed on a semiconductor substrate, and a refresh control circuit for controlling the plurality of semiconductor memory devices, wherein said plurality of semiconductor memory devices are clock synchronous, including a clock input and a refresh function for refreshing data in a memory cell arranged therein; said logic circuit outputs a sleep control signal and a first clock signal; said refresh control circuit receives the sleep control signal and said first clock signal outputted from said logic circuit, and outputs a second clock signal to clock inputs of said plurality of semiconductor memory devices; said refresh control circuit outputs said first clock signal as said second clock signal when the sleep control signal is in a first state to enable the control of said plurality of semiconductor memory devices by said logic circuit; and said refresh control circuit outputs a clock signal having a clock cycle different from that of said first clock signal as said second clock signal when said sleep control signal is in a second state.