Patent ID: 7470949

Claim:
A non-volatile memory cell comprising: a substrate of a substantially single crystalline semiconductive material having a first conductivity type and a planar surface; a first trench in said substrate extending in a first direction, said first trench having a sidewall and a bottom; a first region of a second conductivity type in said bottom of said first trench; a second trench in said substrate extending in the first direction parallel to and spaced apart from the first trench by a section along the planar surface, said second trench having a sidewall and a bottom; a second region of the second conductivity type in said bottom of said second trench; a channel region connecting said first and second regions for the conduction of charges, said channel region having three portions: a first portion along the sidewall of the first trench, a second portion along the sidewall of the second trench; a third portion along the section between the first and second trenches, near the planar surface; a first charge trapping layer spaced apart from the first portion of the channel region for trapping charges; a second charge trapping layer spaced apart from the second portion of the channel region for trapping charges; a dielectric layer spaced apart from the third portion of the channel region; a first control gate in the first trench extending in the first direction, capacitively coupled to the first charge trapping layer and to the first region; a second control gate in the second trench extending in the first direction, capacitively coupled to the second charge trapping layer and to the second region; and a third control gate couple to the dielectric layer for controlling the conduction of charges in the third portion of the channel region.