Patent ID: 7984280

Claim:
A method for storing branch address information in an address table of a computer processor, the method comprising: receiving a request to add an instruction to a single address table comprising addresses for all instructions to be executed by a processor, the single address table being shared by both an instruction fetch unit and a separate branch execution unit, wherein the instruction fetch unit fetches all instructions to be performed by the processor from the single address table, and wherein further the single address table stores both instruction addresses for each instruction to be executed by the processor and branch prediction information simultaneously within the single address table, and the request comprising an address for the instruction; accessing, by the instruction fetch unit, an external interrupt from the single address table; accessing, by the branch execution unit, in the single address table a first entry, the first entry having a base instruction tag for a first stored instruction and a base address associated with the first stored instruction; determining, by the branch execution unit, whether a branch in the first entry is being predicted taken; in response to a branch in the first entry being predicted taken, creating by the branch execution unit a new second entry in the single address table having a second base instruction tag and a second base address and storing by the branch execution unit the instruction requested to be added in the second entry of the single address table; and in response to a branch in the first entry not being predicted taken, storing by the branch execution unit the instruction requested to be added in the first entry of the single address table.