Patent ID: 7552368

Claim:
A method for testing a semiconductor memory device including nm memory cell regions for respectively outputting x-bit data when n word lines and m column selecting signal lines are selected, and each half of the nm memory cell regions is a first memory cell array and a second memory cell array, the method comprising: extending y-bit data received through y data I/O pads to (nm×x)-bit data to write the x-bit data to each of the nm memory cell regions in a test data write step; and comparing the x-bit data output from each of the nm memory cell regions to generate nm-bit comparison result data, and sequentially outputting y-bit comparison result data selected by selecting, by y bits generated from the first memory cell array or from the second memory cell array, the nm-bit comparison result data in response to a control signal to the y data I/O pads, respectively, in a test data read step, wherein n is an integer equal or greater than 2, wherein m is an integer equal or greater than 4, wherein x and y are integers greater than 1, wherein nm comprises n multiplied by m, and wherein y is less than nm.