Patent ID: 7181591

Claim:
A control circuit of memory address decoding for determining whether a given address is located in one of a plurality of sections in memory, each memory section having at least one memory unit and each memory unit being associated with a unique binary address, the control circuit comprising: a pattern calculation module for building at least one bit-pattern for each section based on the associated addresses; an access module for receiving the given address; and a comparing module for calculating a bit-pattern for each section based on the associated addresses, and sending a plurality of comparison signals after comparing at least one of the comparative bits in the given address with each bit-pattern provided by the pattern calculation module respectively, wherein the comparing module comprises a plurality of comparing units, each comparing unit comprising a plurality of NAND gates and one single AND gate, each of the NAND gates having two inputs for respectively receiving one bit of the bit-patterns and another bit associated with the given address, the inputs of the NAND gate being connected to the outputs of the AND gate and thereby sending out the comparison signals.