Patent ID: 8072790

Claim:
A memory device, comprising: a memory cell including four transistors and two capacitors, wherein the memory cell is composed of a pair of ferroelectric capacitors for storing a non-inverting data and an inverting data, a pair of access transistors connecting to the pair of ferroelectric capacitors, a pair of reset transistors connecting to the pair of ferroelectric capacitors, where a local bit line pair is connected to the pair of access transistors, a plate line is connected to the pair of ferroelectric capacitors, a reset line is connected to the pair of reset transistors, and a constant voltage is applied to the plate line and the reset line; and a deselect circuit including a pair of deselect transistors for forcing the local bit line pair from a pre-charge state to the constant voltage which is applied to the plate line and the reset line; and a local sense amp including a pair of local pre-charge transistors for pre-charging the local bit line pair to the pre-charge state, a pair of local pre-amp transistors for receiving voltage difference between the local bit line pair, a local sink transistor connecting to the pair of local pre-amp transistors, a pair of local enable transistors for connecting the pair of local pre-amp transistors to a global bit line pair when reading, and a pair of local write switches for connecting the local bit line pair to the global bit line pair when writing; and a global sense amp including a pair of global pre-set transistors for pre-setting the global bit line pair, a cross coupled latch for connecting to the global bit line pair, and a pair of data transfer transistors for connecting the global bit line pair to a data line pair; and a pair of read paths including the local sense amp for changing one of the global bit lines quickly and another one of the global bit lines slowly when the pair of local enable transistors is turned on; and a pair of write paths for transferring voltages of the global bit line pair to the local bit line pair when the pair of local write switches is turned on; and a locking signal generator for generating a locking signal, wherein the locking signal disables the pair of local enable transistors after reading.