Patent ID: 8653584

Claim:
A dual vertical channel transistor comprising: a tuning fork-shaped substrate body; a buried bit line embedded at a bottom of a recess between two prong portions of said tuning fork-shaped substrate body; a first source/drain region adjacent to said buried bit line in said tuning fork-shaped substrate body; a second source/drain region situated at a top portion of each of said two prong portions of said tuning fork-shaped substrate body; an epitaxial portion connecting said two prong portions of said tuning fork-shaped substrate body, said epitaxial portion being situated between said first source/drain region and said second source/drain region; a front gate situated on a first side surface of said tuning fork-shaped substrate body; and a back gate spaced apart from the front gate and situated on a second side surface opposite to said first side surface of said tuning fork-shaped substrate body, wherein the tuning fork-shaped substrate body is interposed between the front gate and the back gate.