Patent ID: 8289753

Claim:
A semiconductor device comprising: a source line; a bit line; a first signal line; a plurality of second signal lines; a plurality of word lines; a plurality of memory cells connected to each other in parallel between the source line and the bit line; a first driver circuit configured to drive the plurality of second signal lines and the plurality of word lines so that a memory cell specified from the plurality of memory cells by an address signal input to the first driver circuit is selected; a second driver circuit configured to select and output any of a plurality of writing potentials to the first signal line; a reading circuit configured to compare a potential of the bit line and a plurality of reference potentials to read data out; and a potential generating circuit configured to generate and supply the plurality of writing potentials and the plurality of reference potentials to the second driver circuit and the reading circuit, wherein one of the plurality of memory cells comprises: a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode; and a third transistor including a third gate electrode, a third source electrode, and a third drain electrode, wherein the first transistor is provided on a substrate including a semiconductor material, wherein the second transistor includes an oxide semiconductor layer, wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other, wherein the source line and the first source electrode are electrically connected to each other, wherein the first drain electrode and the third source electrode are electrically connected to each other, wherein the bit line and the third drain electrode are electrically connected to each other, wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other, wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other, and wherein one of the plurality of word lines and the third gate electrode are electrically connected to each other.