Patent ID: 7707397

Claim:
An apparatus in a microprocessor for predicting a target address for a variable number of branch instructions in each cache line fetched from an instruction cache at a fetch address, the apparatus comprising: first and second two-way set associative cache memories, each having an index input coupled to receive a portion of the instruction cache fetch address, wherein said index selects one of a plurality of groups of four entries, each said group comprising one entry in each way of each of said first and second cache memories, wherein each of said entries is configured to cache a target address of one previously executed branch instruction; and replacement logic, coupled to said first and second caches, configured to select for replacement one of said entries, in response to resolution of a branch instruction, such that during operation of the microprocessor: a) for a first subset of said plurality of groups, said four entries are caching target addresses for one branch instruction in each of four different cache lines of the instruction cache, to obtain four-way group associativity; and b) for a second subset of said plurality of groups, said four entries are caching target addresses for one branch instruction in each of two different cache lines of the instruction cache and two branch instructions in a third different cache line of the instruction cache, to obtain three-way group associativity, wherein the three-way group associativity is obtained even though the two branch instructions in the third different cache line are located without restriction within the third different cache line.