Patent ID: 7528407

Claim:
A TFT array substrate, comprising: a substrate; a patterned first metallic layer disposed on the substrate, the patterned first metallic layer comprising a plurality of common lines, a plurality of scan lines, and a plurality of source patterns, wherein each two adjacent scan lines are orthogonal to two corresponding source patterns adjacent to each other so as to define a pixel area on the substrate, the common lines are configured passing through their corresponding pixel areas, and parallel with the scan lines, and a protrusion is extruded from each of the source patterns at a position adjacent to its corresponding scan line, acting as a source electrode; a patterned semiconductor layer disposed on the patterned first metallic layer and the substrate, comprising a plurality of first semiconductor patterns and a plurality of second semiconductor patterns, wherein the first semiconductor patterns are correspondingly configured on the source electrodes in the pixel areas, and the second semiconductor patterns are correspondingly configured on the common lines in the pixel areas, respectively, and each second semiconductor pattern has a first opening exposing the common line; a patterned transparent conductive layer disposed on the patterned semiconductor layer and the substrate, defining a pixel electrode in each pixel area, wherein each pixel electrode covers a first semiconductor pattern and a second semiconductor pattern corresponding thereto, and each pixel electrode has a second opening corresponding to the first opening; a patterned dielectric layer disposed over the substrate, comprising a plurality of first dielectric patterns, and a plurality of second dielectric patterns, wherein each first dielectric pattern is disposed over the corresponding common line, and has a third opening corresponding to the second opening, and each second dielectric pattern is disposed at an intersection of an extending direction of each source pattern and its corresponding scan line and extends to cover its corresponding source electrode, and the first semiconductor pattern and the pixel electrode formed over the source electrode; and a patterned second metallic layer, disposed over the substrate, comprising a plurality of data lines, a plurality of gate electrodes, and a plurality of metallic electrodes, wherein each data line is disposed on the corresponding source pattern along the direction the source pattern extending, each gate electrode is disposed on the second dielectric pattern over the corresponding source electrode, extending to connect to the corresponding scan line, and each metal electrode is disposed on the first dielectric pattern in the corresponding pixel area, electrically connected to its corresponding common line via the third opening, the second opening and the first opening.