Patent ID: 7457970

Claim:
A data processing apparatus comprising: an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses; an instruction execution unit, comprising a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units; a power saving circuit arranged to switch a selectable subset of the functional units and/or parts of the instruction memory that supply instructions from the instruction word to the functional units to a power saving state during program execution, the power saving circuit being arranged to select the functional units and/or parts of the instruction memory in the subset dependent on program execution; wherein: the instruction memory system includes a plurality of memory units, each for supplying a respective instruction field in the instruction word for an instruction for a respective functional unit or group of functional units, the clock gating circuit being arranged to switch those memory units to the power saving state that supply the instruction field for the selectable ones of the functional units that are switched to the power saving state, and the memory units each comprise memory locations for at least a part of each instruction words only for instruction words in a respective range of instruction addresses, the instruction memory system allowing for partial overlap of the respective ranges of different ones of the memory units.