Patent ID: 7462543

Claim:
A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure, the NMOS transistor having a polysilicon gate being a floating gate and being connected to an electrode of a coupling capacitor, the other electrode of the coupling capacitor being the control terminal of the flash memory cell, the method comprising: forming a P-well in the P-type semiconductor structure; defining active areas on the P-type semiconductor structure including at least a first active area in which a channel region, a source region and a drain region are to be formed; forming a gate dielectric layer over the P-type semiconductor structure; forming a polysilicon layer over the gate dielectric layer and patterning the polysilicon layer to form the polysilicon gate of the NMOS transistor; forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor, the patterned photoresist layer exposing the first active area; forming a first N-type region and a second N-type region by a first implantation process using the patterned photoresist as an implant mask, the first implantation process using a high implant dose at a low implant energy, the first and second N-type regions being self-aligned to the polysilicon gate and forming the source and drain regions of the NMOS transistor; forming a channel doped region by a second implantation process using the patterned photoresist as an implant mask, the second implantation process using a low implant dose at a high implant energy, the channel doped region being formed under the polysilicon gate for adjusting a threshold voltage of the NMOS transistor; and removing the patterned photoresist.