Patent ID: 8111092

Claim:
A digital data register with a plurality of parallel matched data paths, each data path having a data input for receiving a digital data input signal, an output driver with a data output providing a digital data output signal for application to an associated memory module and a flip-flop arranged between the data input and the data output, the data register further comprising: a clock input for receiving a clock input signal; a clock output for providing an output clock signal to the memory modules; a phase locked loop with a clock input and a feedback input; a feedback output providing a feedback output signal and a clock output providing a clock output signal; a flip-flop and output driver replica matched with the flip-flop and output driver of the data paths; and a phase frequency detector; wherein: the flip-flops of the data paths and the flip-flop of the replica are clocked by the feedback signal applied to the feedback input of the phase locked loop; the phase locked loop includes a phase aligner with a phase interpolator; the phase interpolator has an output that provides the output clock signal to the memory modules through a flip-flop and output driver matched with the flip-flop and output driver of the data paths; the phase frequency detector has a first input coupled to the output of the output driver replica and a second input coupled to the clock output; and the phase interpolator is controlled by the output of the phase frequency detector.