Patent ID: 7687892

Claim:
A semiconductor package, comprising: a leadframe having a horizontal surface and first and second level downset lead extensions, the first level downset lead extension having a vertical surface extending from the horizontal surface of the leadframe, the first level downset lead extension further having a horizontal surface extending from the vertical surface of the first level downset lead extension, the horizontal surface of the first level downset lead extension being vertically offset from the horizontal surface of the leadframe, the second level downset lead extension having a vertical surface extending from the horizontal surface of the first level downset lead extension, the second level downset lead extension further having a horizontal surface extending from the vertical surface of the second level downset lead extension, the horizontal surface of the second level downset lead extension being vertically offset from the horizontal surface of the first level downset lead extension; a quad flat nonleaded package (QFN) attached to the horizontal surface of the first level downset lead extension with solder, the QFN being positioned within a gap of the vertical surface of the first level downset lead extension to limit movement of the QFN during stacking; and a flip chip die attached to the horizontal surface of the second level downset lead extension with solder, the flip chip die being positioned within a gap of the vertical surface of the second level downset lead extension to limit movement of the flip chip die during stacking.