Patent ID: 8463832

Claim:
A programmable logic device (PLD) including a digital signal processing (DSP) block, the DSP block comprising: a first DSP slice including: a first multiplier adapted to multiply a plurality of input signals to provide first product signals; a second multiplier adapted to multiply a plurality of input signals to provide second product signals; and a first arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first second operand inputs, respectively, of the ALU to provide first output signals; and a second DSP slice including: a third multiplier adapted to multiply a plurality of input signals to provide third product signals; a fourth multiplier adapted to multiply a plurality of input signals to provide fourth product signals; and a second arithmetic logic unit (ALU) having at least three operand inputs and adapted to operate on the third product signals, the fourth product signals, and other signals received at the first, second, and third operand inputs, respectively, to provide second output signals, wherein the DSP block is adapted to cascade the input signals of the first multiplier to the third and/or fourth multiplier and the input signals of the second multiplier to the third and/or fourth multiplier, and to cascade the first output signals of the first ALU to the third operand input of the second ALU, wherein the first output signals and the second output signals collectively provide a product resulting from the multiplication of the pluralities of input signals; and wherein: the product has 2n bits; the first and third pluralities of input signals are a first n-bit signal; the second plurality of input signals is the n/2 least significant bits of a second n-bit signal; the fourth plurality of input signals is the n/2 most significant bits of a second n-bit signal; the n most significant bits of the first output signals are cascaded to the second ALU and the n/2 least significant bits of the first output signals are the n/2 least significant bits of the product; and the second output signals are the 3n/2 most significant bits of the product.