Patent ID: 8904114

Claim:
An apparatus to implement a shared cache architecture, the apparatus comprising: a multi-core processor comprising a first subset of processor cores and a second subset of processor cores; a first shared cache memory coupled to the first subset of processor cores and configured to be accessible to the first subset of processor cores; a second shared cache memory coupled to the second set of processor cores and configured to be accessible to the second subset of processor cores; and a module coupled to the first shared cache memory and the second shared cache memory and configured to; access data stored in a first subset of one or more memory locations in the first shared cache memory wherein the data is to be accessed by one or more of the first subset of processor cores and one or more of the second subset of processor cores; mirror the data; store the mirrored data in a second subset of one or more memory locations in the second shared cache memory; and update the mirrored data responsive to modification of the mirrored data by any of the first subset of processor cores and/or the second subset of processor cores, wherein the first subset of processor cores includes different processor cores than the second subset of processor cores.