Patent ID: 8289047

Claim:
A field programmable gate array architecture, comprising: (a) a first logical cluster having a first span in a first dimension and having a second span in a second dimension, the cluster comprising a plurality of cells, each cell comprising: an output, at least one input, and an input multiplexer coupled to each input; (b) a first plurality of intraconnect conductors within the first and second spans, wherein the output of each cell in the first logical cluster is selectively coupleable to at least one input multiplexer coupled to each of the other cells in the first logical cluster by traversing a single one of the first plurality of intraconnect conductors; (c) a second logical cluster having a third span in the first dimension and having a span in the second dimension equal to the second span, the cluster comprising a plurality of cells, each cell having: an output, at least one input, and an input multiplexer coupled to each input; (d) a second plurality of intraconnect conductors within the second and third spans, wherein the output of each cell in the second logical cluster is selectively coupleable to at least one input multiplexer coupled to each of the other cells in the second logical cluster by traversing a single one of the second plurality of intraconnect conductors; (e) a third logical cluster having a fourth span in the first dimension and a span in the second dimension equal to the second span, the cluster comprising a plurality of cells, each cell having: an output, at least one input, and an input multiplexer coupled to each input; (f) a third plurality of intraconnect conductors within the second and fourth spans, wherein the output of each cell in the third logical cluster is selectively coupleable to at least one input multiplexer coupled to each of the other cells in the third logical by traversing a single one of the third plurality of intraconnect conductors; (g) a fourth logical cluster having a fifth span in the first dimension and a span in the second dimension equal to the second span, the cluster comprising a plurality of cells, each cell having: an output, at least one input, and an input multiplexer coupled to each input; (h) a fourth plurality of intraconnect conductors within the second and fifth spans, wherein the output of each cell in the fourth logical cluster is selectively coupleable to at least one input multiplexer of each of the other cells in the fourth logical cluster by traversing a single one of the fourth plurality of intraconnect conductors.