Patent ID: 7528066

Claim:
A method of fabricating a semiconductor structure comprising: providing an initial interconnect structure that includes a lower interconnect level comprising a first dielectric layer having at least one conductive feature embedded therein, an upper interconnect level comprising a second dielectric having at least one via opening that exposes a portion of said at least one conductive feature located atop said lower interconnect level, said lower and upper interconnect levels are separated in part by a dielectric capping layer, and a patterned hard mask on a surface of the said upper interconnect level; forming a first barrier layer on all exposed surfaces of the initial interconnect structure; forming a punch-through gouging feature in said at least one conductive feature that is located at the bottom of said via opening; forming at least one line opening in said second dielectric material that extends above said at least one via opening; forming a second continuous diffusion barrier layer at least within said at least one line opening; forming an adhesion/plating seed layer within both said at least one line opening and said at least one via opening; filling said at least one line opening and at least one via opening with a conductive material; and performing a planarization step after said filling with said conductive material, wherein said planarization step removes said patterned hard mask and provides a conductive filled line that has an upper surface that is coplanar with an upper exposed surface of said second dielectric material.