Patent ID: 8567051

Claim:
Process for the vertical interconnection of n 3D electronic modules, n being an integer greater than 1, each 3D electronic module comprising a stack of K electronic, wafer levels, K being an integer, a wafer level i, i being an integer varying from 1 to K, comprising at least one electronic component, the K wafer levels being electrically connected together by conductors lying along the direction of the stack that is perpendicular to the plane of a wafer, for each wafer level i, comprising: a. fabricating a batch of n wafer levels, a wafer level comprising at least it geometric features bounded by dicing lines, each geometric feature comprising at least one electronic component surrounded by insulating resin and connected to electrical connection pads, the electrical connection pads being connected to electrical connection tracks deposited on a dielectric layer, wherein each electrical connection track extends as far as an electrode interconnecting the electrical connection tracks and located on the dicing lines, and comprises a curved segment placed between two straight segments, the curved segment defining a zone that surrounds a location intended to form a via, this zone being placed between the electrical connection pad and the track interconnection electrode; b. stacking and assembling the K wafer levels obtained after the first step so as to superpose said zones approximately one on top of another; c. drilling vias in the resin along the direction of the stack and over the entire thickness of the stack, at the latter plumb with the locations of the vias, the cross section of the vias being such that, for each wafer level, the straight segments are flush with the vias but not with the curved segments; d. metallizing the wall of each via by electrolytic growth; and e. cutting the stack along the dicing lines, the width of the cuts being greater than that of the track interconnection electrode, so as to obtain the n 3D electronic modules.