Patent ID: 7279950

Claim:
A differential clock signal gating method, comprising the steps of: providing a differential clock signal having a plurality of sequential and equivalent clock pulses, each of the plurality of clock pulses having a clock amplitude and a clock pulse width defined by a positive pulse half and a negative pulse half, the negative pulse half occurring sequentially after the positive pulse half; providing a clock buffer circuit control path; developing a clock gating signal with a timing relationship to the clock signal; providing a buffer differential pair within the control path buffer stage in the clock path, the buffer differential pair further having a differential pair current source device dummy current load; sending differential pair current to the dummy current load; switching the differential pair current from the dummy current load to the buffer differential pair responsive to the clock gating signal during the first clock signal pulse negative half; and the buffer differential pair buffering a buffer clock signal output to a second buffer stage responsive to the step of switching the differential pair current, the buffer clock signal output comprising a second clock signal pulse and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse, the buffer clock signal output comprising a plurality of sequential and equivalent clock pulses each having the clock amplitude and the clock pulse width.