Patent ID: 7317639

Claim:
A method of operating a memory device comprising a plurality of word lines disposed on a semiconductor substrate in parallel and each of which includes a plurality of memory cells, as well as a plurality of bit lines crossing the word lines to be disposed in parallel and connected to one selected from source/drain regions of each word line, wherein each memory cell comprises a word line, source/drain regions formed in the semiconductor substrate at both sides of the word line, and a charge trap insulation layer intervened between the word line and the semiconductor substrate, and wherein each memory cell has one of the source/drain regions in common with one memory cell having a first word line in common as well as a pair of memory cells having a second word line that is adjacent to the first word line, and has another source/drain region in common with another memory cell having the first word line in common as well as another pair of memory cells having a third word line that is adjacent to the first word line, and wherein source/drain regions of each memory cell are respectively connected to different bit lines, the method comprising: a first bit write operation including selecting adjacent first and second bit lines and one word line, and applying a first level voltage, a ground voltage, and a write voltage to a first bit line, a second bit line, and a selected word line, thereby writing a first bit into a region adjacent to the first bit line of the charge trap insulation layer constituting the selected memory cell; a second bit write operation including applying the first level voltage, the ground voltage, and the write voltage to the second bit line, the first bit line, and the selected word line, thereby writing a second bit into the charge trap insulation layer adjacent to the second bit line; a first bit read operation including applying a ground voltage, a second level voltage lower than the first level voltage, and a read voltage lower than the write voltage to the first bit line, the second bit line, and the selected word line; and a second bit read operation including applying the ground voltage, the second level voltage, and the read voltage to the second bit line, the first bit line, and the selected word line.