Patent ID: 7953955

Claim:
A translation memory (TM) system comprising: a memory for storing fixed width abbreviated instructions in place of variable width virtual instructions making up a program, wherein each type of virtual instruction has an instruction format bit width not restricted by a physical memory size and each fixed width abbreviated instruction has an X-TM index value and a Y-TM index value; and a decoder having an X-TM, a Y-TM, and a shuffler, wherein the X-TM and the Y-TM store decoding tables and a fetched abbreviated instruction causes an access of the X-TM based on the X-TM index value to fetch an X-fragment and an access of the Y-TM based on the Y-TM index value to fetch a Y-fragment, the X-fragment and the Y-fragment combined in the shuffler to produce a core instruction formatted to execute on a processor's execution core.