Patent ID: 7756226

Claim:
A method for converting logarithmic values into linear values in digital logic in an integrated circuit, comprising: receiving a logarithmic gain signal; dividing the logarithmic gain signal by a specified number to generate a shift signal and a remainder signal, wherein a shift estimator is configured to to divide the logarithmic gain signal by a specified number to generate a shift signal and a remainder signal, wherein a coarse shifter is coupled to the shift estimator and configured to shift the digital input signal based on the shift signal, wherein the shift estimator comprises a plurality of shifters, a summation block is coupled to the shifters, an upper bit slicer is coupled to the summation block and a lower bit slicer coupled to the summation block, wherein the plurality of shifters left-shift the logarithimic gain signal, and wherein the summation block is configured to add the logarithmic gain signal to an output of each of the shifters to generate a sum signal; generating the shift signal by bit slicing a first specified number of most significant bits of the sum signal; and applying a linear gain to a digital input signal based on the shift signal and the remainder signal to generate a digital output signal.