Patent ID: 7122866

Claim:
A semiconductor memory device comprising: a first MOS transistor including a first gate electrode which is formed on a first element region enclosed by a first element isolating region formed in a semiconductor substrate with a first gate insulating film interposed between the first element region and the first gate electrode, an end portion of the first gate electrode in the gate width direction being located on the first element isolating region; and a second MOS transistor including a second gate electrode which is formed on a second element region enclosed by a second element isolating region formed in the semiconductor substrate with a second gate insulating film at least twice as thick as the first gate insulating film interposed between the second element region and the second gate electrode, an end portion of the second gate electrode in the gate width direction being located on the second element isolating region, the upper part of each of the first and second element isolating regions being formed so as to project from the surface of the semiconductor substrate and have their corners curved, and the width from the position where the first element isolating region contacts the first gate insulating film to the top surface end of the first element isolating region being equal to the width from the position where the second element isolating region contacts the second gate insulating film to the top surface end of the second element isolating region.