Patent ID: 8205033

Claim:
A memory device comprising: a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, a physical translation unit (TU) in the non-volatile memory including a data area and a spare area; a volatile memory; and a control section that manages access to the non-volatile memory, wherein the control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in TUs each being a fraction of a size of the block and a multiple of a page size, writes management information including a corresponding logical TU number, and a sequential number indicating the write order of each block, into the spare area of the non-volatile memory, builds a logical-physical translation table at startup by scanning the management information in the spare area of the non-volatile memory, and stores the logical-physical translation table into the volatile memory, and performs a logical-physical translation process based on the logical-physical translation table on the memory, restores, at the startup, a physical TU state map for managing a physical TU, in parallel with building the logical-physical translation table by scanning the management information in the spare area of the non-volatile memory; and wherein the physical TU state map indicates whether the physical TU is in an unwritten, CLEAN state after an erase operation, an INUSE state in which valid data referenced from the logical-physical translation table is stored, or an INVALID state in which invalid data not referenced from the logical-physical translation table is stored.