Patent ID: 8441842

Claim:
A memory device comprising: a memory array comprising a plurality of memory cells; at least a given one of the memory cells comprising: a pair of cross-coupled inverters; and write assist circuitry; the write assist circuitry comprising: first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell; and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell; wherein each of the first and second switching circuitry comprise at least first, second and third write assist transistors; wherein the first, second and third write assist transistors of the first switching circuitry are controlled using a common control signal, a worldline and a complemented bitline of the memory device, respectively, and the first, second and third write assist transistors of the second switching circuitry are controlled using the common control signal, the wordline and an uncomplemented bitline of the memory device, respectively; and wherein the first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.