Patent ID: 7217631

Claim:
A semiconductor device fabricating method comprising the steps of: forming a first portion having a first substrate, a conductive layer and an insulating layer laminated on the first substrate and a bonding surface that is chemically mechanically polished and exposes a conductive region and an insulating region; forming a second portion having a second substrate, a conductive layer and an insulating layer laminated on the second substrate and a bonding surface that is chemically mechanically polished and exposes at least a conductive region; selectively etching the insulating region of at least one of the bonding surface of the first portion and the bonding surface of the second portion, thereby lowering the surface of the insulating region with respect to the surface of the conductive region; and applying pressure welding loads to the first portion and the second portion for achievement of solid state bonding of the bonding surface of the first portion to the bonding surface of the second portion and for achievement of electrical connection of the conductive region of the first portion with the conductive region of the second portion.