Patent ID: 8324025

Claim:
A method for packaging one or more power semiconductor devices, comprising: constructing a lead frame comprising one or more base die paddles, a plurality of lead terminals, and a tie bar assembly; connecting said one or more base die paddles of said lead frame to said lead terminals by said tie bar assembly, wherein said tie bar assembly mechanically couples said one or more base die paddles to each other and to said lead terminals; selectively configuring said tie bar assembly to isolate said lead terminals from said one or more base die paddles; and creating a plurality of selective connections between one or more of said lead terminals and said one or more power semiconductor devices mounted on said one or more base die paddles; whereby said selective configuration of said tie bar assembly and said selective connections created between said one or more of said lead terminals and said one or more power semiconductor devices enable flexible packaging of one or more isolated power semiconductor devices and one or more non-isolated power semiconductor devices and increases power handling capacity of said packaged one or more power semiconductor devices.