Patent ID: 8247845

Claim:
A semiconductor device, comprising: an array of a plurality of standard cells arranged in a plurality of rows, wherein at least one electrostatic discharge (ESD) protection circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of standard cells; and a plurality of input/output (I/O) or supply pads proximate the array and coupled to the semiconductor device, wherein the at least one ESD protection circuit or the portion thereof is coupled to at least one of the plurality of I/O or supply pads, wherein the at least one ESD protection circuit is configured to turn on during an ESD event at the at least one of the plurality of I/O or supply pads and form a current discharge path so as to clamp a voltage at the at least one of the plurality of I/O or supply pads to a sufficiently low level during the ESD event.