Patent ID: 8664063

Claim:
A method of producing a semiconductor device, the method which comprises: a first step of forming a planar silicon layer on a silicon substrate, and forming a first pillar-shaped silicon layer and a second pillar-shaped silicon layer on the planar silicon layer; a second step, subsequent to the first step, of forming a gate insulating film around the first and second pillar-shaped silicon layers, depositing a metal film and a polysilicon around the gate insulating film, conducting planarization, and conducting etching to expose upper portions of the first and second pillar-shaped silicon layers, forming a first insulating film sidewall on an upper side wall of the first pillar-shaped silicon layer, forming a second insulating film sidewall on an upper side wall of the second pillar-shaped silicon layer, forming, around the gate insulating film, a first gate electrode and a second gate electrode each having a laminated structure of the metal film and the polysilicon, and forming a gate line connected to the first gate electrode and the second gate electrode; a third step, subsequent to the second step, of forming a first n-type diffusion layer in an upper portion of the first pillar-shaped silicon layer, forming a second n-type diffusion layer in a lower portion of the first pillar-shaped silicon layer and an upper portion of the planar silicon layer, forming a first p-type diffusion layer in an upper portion of the second pillar-shaped silicon layer, and forming a second p-type diffusion layer in a lower portion of the second pillar-shaped silicon layer and an upper portion of the planar silicon layer; a fourth step, subsequent to the third step, of forming a third insulating film sidewall on side walls of the first and second insulating film sidewalls, side walls of the first and second gate electrodes, and a side wall of the gate line; and a fifth step, subsequent to the fourth step, of forming a silicide on the first and second n-type diffusion layers, the first and second p-type diffusion layers, and the gate line.