Patent ID: 8304882

Claim:
A power semiconductor device, comprising: an insulating substrate; a circuit pattern formed on an upper surface of said insulating substrate; a power semiconductor formed on said circuit pattern; a plurality of electrode terminals formed perpendicularly to one of said circuit pattern and said power semiconductor so as to be in conduction with external terminals; an integral resin sleeve in which a plurality of sleeve parts are integrated, the plurality of sleeve parts being respectively fitted with said plurality of electrode terminals from above the plurality of electrode terminals and having openings at both ends thereof; and a sealing resin covering said insulating substrate, said circuit pattern, said power semiconductor, said electrode terminals, and said integral resin sleeve, wherein: upper surfaces of said sleeve parts of said integral resin sleeve are exposed from said sealing resin, said insulating substrate has a multi-layer structure with an undermost layer thereof being a base plate made of metal, a back surface of said base plate is exposed from said sealing resin, said integral resin sleeve has a structure in which said plurality of sleeve parts are formed on a resin flat plate, an upper surface of said resin flat plate of said integral resin sleeve is exposed from said sealing resin, and said resin flat plate of said integral resin sleeve is provided with uneven grooves on a surface opposed to said insulating substrate other than said sleeve parts.