Patent ID: 7379369

Claim:
the semiconductor device comprising: an address controller for receiving a normal address and a refresh address and selectively outputting the received refresh address in a refresh mode; a fuse circuit for receiving the refresh address, determining whether the received refresh address corresponds to a word line to be repaired and outputting a redundancy word line enable signal and a first control signal according to a result of the determination; a first signal generator for, in response to a bit value for block selection of the refresh address and the first control signal, outputting a second control signal which defines a multi-word line refresh period; a refresh address generator for generating the refresh address in response to the second control signal; and a row controller for receiving the refresh address, second control signal and redundancy word line enable signal and controlling the refresh operation with respect to a memory core, wherein the semiconductor device performs, in the self-refresh mode, multi-word line refreshing when the refresh address corresponds to a normal word line and single word line refreshing for a certain period when the refresh address corresponds to the word line to be repaired.