Patent ID: 7919792

Claim:
An integrated circuit structure, comprising: a first cell area defined in a semiconductor substrate extending in a first direction and a second direction and having a cell boundary, the first cell area comprising: a first active region; at least one first gate electrode strip overlying the first active region and aligned in the first direction; a first set of lines of a conductor layer having at least two portions and having a minimum spacing distance between the two portions; one of the portions of the first set of lines having a first spacing distance to the cell boundary, wherein the first spacing distance is substantially less than half of the minimum spacing distance; and a second cell area defined in the semiconductor substrate extending in the first direction and a second direction and having a common cell boundary in the first direction with the first cell, the second cell area comprising: a second active region; at least one second gate electrode strip overlying the second active region and aligned in the first direction; a second set of lines of the conductor layer having at least two portions and having the minimum spacing distance between the two portions; and one of the portions of the second set of lines being disposed and spaced from the common cell boundary by a second spacing distance and being disposed adjacent the one portion of the first set of lines in the first cell, the second spacing distance being substantially greater than half of the minimum spacing distance.