Patent ID: 7666746

Claim:
A semiconductor structure fabrication method, comprising: providing a semiconductor structure which includes: (i) a semiconductor substrate which includes a channel region, (ii) a first source/drain region on the semiconductor substrate, (iii) a second source/drain region on the semiconductor substrate, wherein the channel region is disposed between the first and second source/drain regions, (iv) a gate dielectric region which includes a first gate dielectric portion, a second gate dielectric portion, and a third gate dielectric portion, wherein the third gate dielectric portion of the gate dielectric region is in direct physical contact with the channel region, wherein the gate dielectric region comprises a first dielectric material having a first dielectric constant, and wherein the first dielectric constant is greater than 4, (v) a gate electrode region, wherein the first gate dielectric portion of the gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region, and wherein the gate electrode region comprises an electrically conductive material, (vi) a first converting portion, wherein the first gate dielectric portion of the gate dielectric region is disposed between and in direct physical contact with the first converting portion and the gate electrode region, and (vii) a second converting portion, wherein the second gate dielectric portion of the gate dielectric region is disposed between and in direct physical contact with the second converting portion and the gate electrode region, and wherein the first and second converting portions comprise a converting material; causing the converting material of the first converting portion to chemically react with the first dielectric material of the first gate dielectric portion of the gate dielectric region resulting in a first spacer dielectric region; and causing the converting material of the second converting portion to chemically react with the first dielectric material of the second gate dielectric portion of the gate dielectric region resulting in a second spacer dielectric region, wherein the first and second spacer dielectric regions comprise a second dielectric material having a second dielectric constant, and wherein the second dielectric constant is lower than the first dielectric constant.