Patent ID: 7042257

Claim:
Apparatus for generating an output signal whose frequency is lower than the frequency of an input signal, the apparatus comprising: a chain of frequency dividing cells, wherein each of the frequency dividing cells has a definable division ratio and comprises a clock input for receiving an input clock, a divided clock output for providing an output clock to a subsequent frequency dividing cell, a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell, and a mode control output for providing a mode control output signal to a preceding frequency dividing cell; and a logic network having plural inputs and an output, the plural inputs being m in number and being connected to m mode control inputs such that each one of said m inputs is connected to a respective one of m frequency dividing cells and such that the m inputs receive the m frequency dividing cells' mode control input signals, and the logic network providing at the output an output signal having a pulse width responsive to a combination of the pulse widths of the received mode control input signals.