Patent ID: 7566929

Claim:
A nonvolatile memory device comprising: a substrate; a tunnel insulating layer on the substrate; a floating gate electrode on the tunnel insulating layer having a sidewall including a first portion and a second portion above the first portion; a first nitrogen doped layer on the second portion of the sidewall wherein the first nitrogen doped layer is not formed on a portion of the first portion of the sidewall; an intergate dielectric layer on the first nitrogen doped layer, wherein the intergate dielectric layer comprises a bottom oxide layer, a middle dielectric layer, and a top oxide layer, wherein the middle dielectric layer comprises a material with a higher dielectric constant relative to the bottom and top oxide layers; a control gate electrode on the intergate dielectric layer, wherein the control gate electrode includes a polysilicon layer and a metal silicide layer; and a trench isolation region being in direct contact with the first portion of the sidewall; and wherein a majority of an interface between the tunnel insulating layer and the floating gate electrode is free of a nitrogen doped layer.