Patent ID: 7804328

Claim:
A buffer comprising: an input terminal; an output terminal; a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the input terminal, and wherein the second passive electrode of the first transistor is coupled to the output terminal; a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor receives a first bias voltage, and wherein the first passive electrode of the second transistor is coupled to the output terminal; a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor receives a second bias voltage, and wherein the second passive electrode of the second transistor is coupled to the first passive electrode of the third transistor; and a capacitor that is coupled between the input terminal and the first passive electrode of the third transistor.