Patent ID: 7669166

Claim:
A processor-based method for generating a hardware description language (HDL) specification of a processor of network packets, comprising: determining, from a first specification that specifies a plurality of handlers for processing the network packets, at least one independent set of interdependent ones of the handlers, wherein the first specification specifies a plurality of actions for each of the handlers; selecting one of a first pipeline and a cluster of threads as a corresponding architecture for each independent set, wherein the corresponding architecture has at least one concurrent unit for each interdependent handler in the independent set, and each concurrent unit is one of a stage of the first pipeline for an independent set and a thread of the cluster for an independent set; assigning by a computer each of the actions of each interdependent handler in each independent set to a concurrent unit for the interdependent handler in the independent set, and further assigning the action to a stage of a second pipeline for the concurrent unit; and generating a second specification of the processor in the HDL, the second specification specifying the corresponding architecture for each independent set and the second pipeline for each concurrent unit of the corresponding architecture for each independent set.