Patent ID: 8288840

Claim:
A semiconductor device comprising: a lower layer wiring layer which includes a plurality of lower layer wirings; an MIM (Metal Insulator Metal) capacitor which is formed above one of said lower layer wirings and formed above said lower layer wiring layer and includes a lower electrode, a capacity dielectric film and an upper electrode having a planar form smaller than that of said lower electrode which are layered from underneath such that the lower electrode is below the capacity dielectric film and the capacity dielectric film is below the upper electrode; and an upper layer wiring layer which is formed above said MIM capacitor and includes a plurality of upper layer wirings connected to said lower electrode and said upper electrode respectively through a via plug, and wherein a plane of said upper electrode is made rectangular, and said lower layer wirings are not arranged substantially right below one or more than one edge of said plane of said upper electrode.