Patent ID: 7642566

Claim:
A contact substructure for an integrated normally off channel JFET comprising: a layer of silicon dioxide or other insulator (hereafter oxide layer) formed on an upper surface of a substrate in which the normally off JFET is formed in an active area of semiconductor defined by an area of insulating material in said substrate, said oxide layer having: a first hole formed above and at least partially aligned with a source region of the JFET and filled with polysilicon to form a source contact; a second hole formed above and at least partially aligned with a drain region of the JFET and filled with polysilicon to form a drain contact; and a third hole formed above and at least partially aligned with a gate region of the JFET and filled with polysilicon to form a gate contact; and a nitride layer formed at least on top of said oxide layer; wherein: the polysilicon filling said holes in said oxide layer has a surface that is coplanar with a surface of the nitride layer; the polysilicon forming said gate contact is doped to a first conductivity type; the polysilicon forming the source contact is doped to a second conductivity type; and the polysilicon forming the drain contact is doped to the second conductivity type.