Patent ID: 8094495

Claim:
A nonvolatile memory device, comprising: a data memory cell array including multi level memory cells divided into two groups to store multi level data respectively in the multi level memory cells of each group; a write sequence memory cell array configured to store a write sequence indicating in which of the two groups the respective multi level data was written first; a write time memory cell array configured to store a number of write operations performed on the multi level memory cells; and a control circuit configured to control a program operation comprising writing data in the data memory cell array and a read operation comprising reading data from the data memory cell array, wherein the control circuit controls the program operation by determining allocation of data corresponding to a minimum physical voltage distribution causing a reaction of the multi level memory cells, such that a shift of a first minimum physical voltage causing the reaction due to the first write operation and a shift of a second minimum physical voltage causing the reaction due to the second write operation are equal regardless of the write sequence.