Patent ID: 7692246

Claim:
FinFET transistor arrangement comprising: a substrate ( 106 , 108 ); an active region ( 1 ) on the substrate, said active region having a source region ( 114 ), a drain region ( 116 ) and an intervening fin-like channel region ( 113 b ′; 113 b ″) for each individual FinFET transistor; a gate dielectric ( 11 ) and a gate region ( 13 , 14 , 15 ) over the fin-like channel region ( 113 b ′; 113 b ″) for each individual FinFET transistor; a respective region with an STI oxide filling ( 9 ), which reaches as far as above the underside of the fin-like channel regions ( 113 b ′: 113 b ′) over which region the gate dielectric ( 11 ) and the gate region ( 13 , 14 , 15 ) run, being provided between adjacent fin-like channel regions ( 113 b ′; 113 b ″) in the active region ( 1 ); and a gap region (U 1 -U 5 ) filled with an insulating filling ( 17 ) being provided between the respective fin-like channel region ( 113 b ″) and the STI oxide filling ( 9 ), wherein only the gap region (U 1 -U 5 ) is filled with the insulating filling ( 17 ).