Patent ID: 7375408

Claim:
A method of fabricating a high voltage metal oxide semiconductor (MOS) device, comprising the steps of: providing a substrate; forming a buried N-doped region in the substrate; forming an N-type epitaxial layer on the substrate; forming a first N-type well in the N-type epitaxial layer, wherein the first N-type well and the buried N-doped region are connected; forming an isolation structure in the first N-type well; forming a gate dielectric layer on the N-type epitaxial layer; forming a gate on the gate dielectric layer and a portion of the isolation structure; forming a P-type well under a portion of the gate and in the N-type epitaxial layer on that side of the gate away from the isolation structure; and forming an N-type drain region in the N-type epitaxial layer on that side of the gate close to the isolation structure and forming an N-type source region in the P-type well.