Patent ID: 7646660

Claim:
A semiconductor memory, comprising: a plurality of memory blocks each having dynamic memory cells; a refresh set circuit which sets partial refresh information indicating enabling/disabling of a refresh operation for each of the memory blocks according to an external input, and outputs the set partial refresh information as a partial set signal; a refresh request generation circuit which outputs periodically a refresh request signal corresponding to the memory block for which enabling is indicated by the partial set signal; a refresh address counter which generates in response to the refresh request signal a refresh address signal indicating the memory cell for which the refresh operation is executed; an operation control circuit which executes the refresh operation for one of the memory blocks in response to the refresh request signal; and a filter circuit which masks the partial set signal from the refresh set circuit and outputs the partial set signal indicating enabling of the refresh operation for all of the memory blocks to the refresh request generation circuit during a period in which the partial refresh information is changed by the external input.