Patent ID: 7958483

Claim:
An apparatus, comprising: a graphics processing unit including: a graphics pipeline having a plurality of functional blocks and a directional data flow for sequential processing of data through said plurality of functional blocks; a status module configured to produce an activity-level indicator based on an activity-level associated with each of the plurality of functional blocks that is indicative of the directional data flow through said graphics pipeline; and a clock control module configured to receive the activity-level indicator and configured to have a mode of operation in which a clock rate is maintained at a master clock rate in at least a first functional block of said graphics pipeline and a clock rate in at least a second functional block of said graphics pipeline not requiring the master clock rate is throttled down to save power without significantly affecting processing performance of said graphics pipeline, wherein the first functional block has an activity-level that is at least a threshold condition, and the second functional block has an activity-level that is below the threshold condition.