Patent ID: 8643120

Claim:
A finFET device comprising: a buried insulator (BOX) layer; a plurality of fin structures over the BOX layer, the fin structures each comprising a semiconductor layer and extending in a first direction; a gate stack located on the BOX layer, the gate stack being formed over the fin structures and extending in a second direction that is perpendicular to the first direction, the gate stack comprising a dielectric layer and a second layer; at least one gate spacer located on vertical sidewalls of the gate stack, an upper surface of the at least one gate spacer being below an upper surface of the gate stack, wherein a first portion of the at least one gate spacer above an upper surface of the fin structures comprises a width that is greater than a width of a second portion of the at least one gate spacer below the upper surface of the fin structures; source and drain regions located in the fin structures; and silicide regions located in an upper surface of the source and drain regions, wherein the second layer of the gate stack is fully silicided.