Patent ID: 7422976

Claim:
A method for fabricating an integrated circuit chip, comprising: providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper, a second dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a nitride layer; forming a polymer layer on said passivation layer, wherein said forming said polymer layer comprises forming a photosensitive polymer layer on said passivation layer; after said forming said polymer layer, forming an opening through said polymer layer and through said passivation layer to expose a contact point of said first metallization structure; and forming a second metallization structure over said contact point, in said opening and on said polymer layer, wherein said second metallization structure comprises a first portion and a second portion over said first portion and over said polymer layer, wherein said first portion is formed by a first process comprising a sputtering process, and said second portion is formed by a second process comprising a copper electroplating process.