Patent ID: 7660840

Claim:
A system for executing an FFT instruction in a hardware processor to process communication data, comprising: a first electronic input configured to access at least one instance of two complex values of the communication data stored in at least one first storage location associated with the hardware processor; a second electronic input configured to access at least one twiddle factor value stored in at least one second storage location associated with the hardware processor, each accessed at least one twiddle factor associated with a respective one of the accessed at least one instance of two complex values; an electronic storage location configured to store an operation parameter for varying the behavior of the FFT instruction; and electronic transform means configured to execute the FFT instruction according to the operation parameter using the accessed at least one instance of two complex values and accessed at least one twiddle factor value to transform the communication data to at least two outputs corresponding to processed communication data, wherein initiation of execution of the FFT instruction occurs in a single processor cycle.