Patent ID: 7266161

Claim:
An apparatus for efficiently performing parallel processing of high-speed single-bit samples comprising: a single-bit sampler for converting an analog signal into serial single-bit samples; a serial-to-parallel converter for converting the single-bit samples from the single-bit sampler into parallel single-bit samples; and a digital quadrature mix for performing real-to-complex conversion, filtering, and decimation-by-two of the parallel single-bit samples from the serial-to-parallel converter and for providing parallel in-phase (I) and quadrature (Q) output values; a filter and decimate stage to filter and decimate the parallel I and Q single-bit output values, wherein said filter and decimate stage comprises a boxcar decimation filter comprising a plurality of filter and decimate functions, wherein each of said plurality of filter and decimate functions comprise: a NOR gate having two inputs connected to outputs of said digital quadrature mix; and an exclusive NOR gate having two inputs connected to the two inputs of the NOR gate.