Patent ID: 7165018

Claim:
A memory access address comparator comprising: a first programmable reference address register storing a first reference address; a first address alignment map maker receiving said first reference address and a first address input for generating at least one first alignment signal indicative of the alignment between said first reference address and said first address input; a first comparator receiving said first reference address from said first programmable reference address register and said first address input for generating a greater than output, a less than output and an equal to output depending upon the relationship between said first reference address and an address on said address input; a second programmable reference address register storing a second reference address; a second address alignment map maker receiving said second reference address and a second address input for generating at least one second offset signal indicative of the offset between said second reference address and said second address input; a second comparator receiving said second reference address from said second programmable reference address register and said address input for generating a greater than, less than or equal to output depending upon the relationship between said second reference address and an address on said address input; first and second memory access control units connected to respective first and second address alignment map makers and respective first and second comparators, each of said first and second memory access control units generating a corresponding first and second local event signal selectively dependent upon said at least one alignment signal, said greater than output, said less than output and said equal to output of said corresponding comparator and a corresponding first and second memory access event signal selectively dependent upon said local signal of the other memory access control unit; said first memory access control unit receiving said at least one first alignment signal whereby said first local event signal and said first memory access event signal are selectively dependent upon full or partial overlap between said first reference address and said address input; and said second memory access control unit receiving said at least one second alignment signal whereby said second local event signal and said second memory access event signal are selectively dependent upon full overlap or partial overlap between said second reference address and said address input.