Patent ID: 8453024

Claim:
An integrated circuit comprising: A. an input pad; B. an input and output pad; C. core circuitry having a first input lead coupled to the input pad, a second input lead, and an output lead; and D. test circuitry coupled between the core circuitry and the input and output pad, the test circuitry including: i. a tri-state buffer having a core input lead connected to the output lead of the core circuitry, a data output lead connected to the input and output pad, and an enable input lead carrying an enable signal that can place the data output lead of the tri-state buffer in a high impedance state; ii. comparator circuitry having a core input lead connected to the core output lead and the core input lead of the tri-state buffer, an encoded response input lead connected to the input and output pad and the data output lead of the tri-state buffer, and an enable input lead coupled to the enable input lead of the tri-state buffer, the comparator circuitry including compare gate circuitry having a first input connected to the core input lead, a second input coupled to the encoded response input lead, and a compare output, and mask circuitry having a first input connected to the compare output, a second input coupled to the encoded response input lead, and a mask output; and iii. an input buffer having an input lead connected to the input and output pad and an output lead connected to the second input lead of the core circuitry.