Patent ID: 8504332

Claim:
A non-transitory computer-readable recording medium storing therein a design support program that causes a processor, which has access to a simulator simulating a circuit model, to execute a process comprising: inputting a driving capability value, a lumped-constant capacitance value, and an input capacitance value that is part of the lumped-constant capacitance value, each value being defined in the circuit model, and further inputting a first delay time of the circuit model, based on the driving capability value and the lumped-constant capacitance value; setting in the circuit model, the driving capability value, the lumped-constant capacitance value, and the input capacitance value that are input at the inputting; acquiring from the simulator, a second delay time of the circuit model resulting from simulation by the simulator, by providing to the simulator, the circuit model having values set therein at the setting; calculating a relative evaluation value for the first delay time input at the inputting and the second delay time acquired at the acquiring; and storing to a storage apparatus, the calculated relative evaluation value as a delay time correcting coefficient, the calculated relative evaluation value being correlated with the driving capability value, the lumped-constant capacitance value, and the input capacitance value.