Patent ID: 8097526

Claim:
A method comprising: positioning and actively drawing front sides of respective first and second integrated circuit die against a shared planarizing surface and holding the front sides in substantially planar alignment, wherein the front sides comprise circuitry formed therein; applying an adhesive, a vacuum, or a magnetic field, via the shared planarizing surface, to hold the front sides of the first and second integrated circuit die in substantially planar alignment; laterally attaching the respective first and second integrated circuit die to each other, such that the front sides remain in substantially planar alignment, including filling a street between the first and second integrated circuit die substantially without continuously filling regions under back sides of the first and second integrated circuit die; forming a monolithic first insulator overlying the first and second integrated circuit die while the first and second integrated circuit die are substantially laterally attached to each other by the filled streets; forming a first via over the first integrated circuit die; forming a second via over the second integrated circuit die; and electrically interconnecting the first and second integrated circuit die by forming a conductor therebetween, including electrically interconnecting the first and second vias.