Patent ID: 7412681

Claim:
A computer implemented method for evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing at least a portion of a higher level circuit in the design that includes a reference potential connection to identify a port of a call to a first lower level circuit that is DC path connected to the reference potential; determining a DC port signature for a call to the first lower level circuit in the design identified as having a port DC connected to reference potential; producing a new instance of the first lower level circuit in the design that corresponds to the DC port signature and that represents the call to the first lower level circuit having the identified port; and traversing at least a portion of the new instance of the first lower level circuit to identify at least a portion of the first lower level circuit that is DC path connected to the port of the new instance of the first lower level circuit that is identified as DC path connected to the reference potential.