Patent ID: 7349278

Claim:
A dynamic random-access memory (DRAM) device comprising: a memory cell array including a plurality of memory cells, the memory cells being respectively allocated in sections defined by a plurality of word lines a plurality of bit line pairs; and a decoder that is configured to: select a single cell of the word line and the bit line to write one bit of data in the single cell, the single cell being designated by an external address signal; sequentially select each word line of a word line pair corresponding to a twin cell including the single cell so that inverted data of the data written in the single cell is to be written in the other single cell of the twin cell, during a first refresh period of a partial array self-refresh (PASR) mode; and concurrently select the word lines of the word line pair corresponding to the twin cell to execute twin-cell self-refresh operations, during subsequent refresh periods of the PASM mode following the first refresh period.