Patent ID: 7049896

Claim:
A phase locked loop (PLL) circuit, comprising: a frequency integrator circuit responsive to a received signal; a phase integrator circuit responsive to the frequency integrator circuit; and a phase shift measurement circuit responsive to the phase integrator circuit and in communication with the frequency integrator circuit, wherein the phase shift measurement circuit is configured to supply a frequency offset to an input of the frequency integrator circuit, wherein when the input to the frequency integrator circuit selectively receives a predetermined value, the phase integrator circuit is configured to synchronize phase and to output a phase signal, and the phase shift measurement circuit is configured to determine the frequency offset using the phase signal, and wherein when the input to the frequency integrator circuit selectively receives the determined frequency offset, the frequency integrator circuit and the phase integrator circuit are configured to track deviations of frequency and phase in the received signal and to adjust frequency and phase of the received signal.