Patent ID: 6847346

Claim:
A semiconductor device comprising: terminals including a control terminal to receive a transfer direction control signal, a first I/O terminal, and a second I/O terminal; a transfer circuit configured to, when the transfer direction control signal is in a first state: receive an external input data signal from the first I/O terminal, decompose the external input data signal into first and second data signals in synchronism with a clock signal so as to reduce frequency of the external input data signal, combine the first and second data signals in synchronism with the clock signal to compose a retimed signal of the external input data signal, and provide the retimed signal as an external output data signal to the second I/O terminal, and further configured to, when the transfer direction control signal is in a second state: receive an external input data signal from the second I/O terminal, decompose the external input data signal into first and second data signals in synchronism with the clock signal so as to reduce frequency of the external input data signal, compose a retimed signal of the external input data signal on the basis of the first and second data signals in synchronism with the clock signal, and provide the retimed signal as an external output data signal to the first I/O terminal; and a main body circuit to process the external input data signal.