Patent ID: 7184305

Claim:
A nonvolatile semiconductor storage device comprising: a memory array configured such that a plurality of nonvolatile semiconductor memory cells capable of storing one-bit information or multi-bit information are individually arranged in a row direction and a column direction, and a plurality of row lines and a plurality of column lines are arranged to select a predetermined memory cell or memory cells from the plurality of memory cells; a row decoder circuit that selects a part of the plurality of row lines and that selectively provides a selected row line with a voltage level different from that for other row lines; and a current-path isolating circuit that, in a test mode different from a normal operation mode, isolates a current path in the device into a first current path for a current flowing through the row line selected and a second current path for a current not flowing through the row line but flowing through the row decoder circuit, the current path isolated being formed for supplying a testing voltage to the selected row line from a testing voltage source.