Patent ID: 6982196

Claim:
A method of fabricating an integrated circuit including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), said NFET and said PFET each having a channel region and a source and drain region, said method comprising: forming a PFET gate stack and an NFET gate stack over a single-crystal region of a semiconductor, said PFET gate stack and said NFET gate stack each having a gate conductor overlying a gate dielectric formed on a main surface of said single-crystal region and spacers including a first material formed on sidewalls of said gate conductor; forming a film having a stress over said source and drain regions of said NFET and said PFET; blocking said source and drain regions of either said NFET or said PFET with a mask; and oxidizing portions of said film by supplying atomic oxygen to a surface of said film in areas not blocked by said mask to reduce a magnitude of said stress in said film over said source and drain regions of said PFET or said NFET, respectively.