Patent ID: 7183163

Claim:
A method of making an isolation-less array of non-volatile memory cells in a semiconductor substrate, having a planar surface; said substrate is of a first conductivity type comprising; forming a plurality of spaced apart trenches in said planar surface of said substrate in a first direction, each trench having a first sidewall, a second sidewall and a bottom wall; forming a pair of floating gates along the first and second sidewalls in each trench, each floating gate spaced apart from the first and second sidewalls, respectively; forming a first terminal of a second conductivity type along the bottom wall of each trench in the substrate; forming a control gate in each trench; each control gate insulated from and capacitively coupled to the floating gates in the trench and insulated from the first terminal along the bottom wall of the trench, wherein each control gate is continuous in said first direction; forming a conductor on said planar surface, said conductor spaced apart from said planar surface, wherein said conductor serving as a gate for a transistor between adjacent trenches; patterning said conductor along a second direction substantially perpendicular to said first direction to form a plurality of spaced apart strips of conductors, with an opening between each pair of conductor strips; and cutting each pair of floating gates in each trench.