Patent ID: 7572726

Claim:
A method of forming a wire bond structure in an integrated circuit (I/C) chip, comprising: providing an I/C chip having a conductive bond pad for attaching to a wire bond with at least one layer of dielectric material overlying the conductive bond pad for the wire bond; forming a surface defining an opening through said at least one layer of dielectric material to expose a portion of said conductive bond pad for said wire bond; forming at least a first conductive layer of TaN/Ta in directly contact on said exposed portion of said conductive bond pad for said wire bond, a surface of said opening in said at least one layer of dielectric material, and a top surface of the at least one layer of dielectric material surrounding said opening; forming a seed layer on said at least said first conductive layer; applying a photoresist material over said seed layer; exposing and developing said photoresist material to reveal a surface of said seed layer surrounding said opening in said at least one layer of dielectric material; removing said revealed surface of said seed layer surrounding said opening in said at last one layer of dielectric layer; removing said developed photoresist material to reveal a remaining portion of said seed layer under said developed photoresist material, said revealed remaining portion of said seed layer overlying and directly contacting said first conductive layer of TaN/Ta, said revealed remaining portion of said seed layer having at least one exposed edge overlying said top surface of said at least one layer of dielectric material; plating two layers of at least one second layer of conductive material on said revealed remaining portion of said seed layer, said two layers of said at least one second layer of conductive material comprising a Ni layer and an Au layer, said two layers of said at least one second layer of conductive material overlying and directly contacting said at least one exposed edge of said revealed remaining portion of said seed layer and said first conductive layer of TaN/Ta on said top surface of said at least one layer of dielectric material; and removing a remaining portion of said first conductive layer on said at least one layer of dielectric layer around said opening.