Patent ID: 7256055

Claim:
A method for evaluating a fabrication of a semiconductor wafer, the method comprising: locating one or more test structures in a die on the wafer, wherein each of the one or more test structures are configured to provide electrical activity when activated, wherein the electrical activity is indicative of a quality metric of the fabrication sequence and/or of a particular fabrication step or sequence in the fabrication; subjecting the wafer to at least one of a plurality of fabrication processes that comprise the fabrication; activating the one or more test structures using one or more external sources, so as to generate one or more signals from within the die; measuring electrical activity that is invariant and provided by the at least one or more test structures in order to determine a performance parameter value of the one or more test structures; and using a correlation between the particular fabrication step or sequence of the die and the performance parameter value of each of the one or more test structures to evaluate the fabrication.