Patent ID: 7595534

Claim:
A high-resistance p − -Silicon substrate wafer, comprising: a p − -Silicon substrate; an epitaxial Silicon cap layer disposed above the p − -Silicon substrate; one or more buried epitaxial carbon-rich Silicon layers under and in contact with the epitaxial Silicon cap layer and above the p − -Silicon substrate; one or more p-wells arranged fully above the p − -Silicon substrate; one or more n-wells arranged partially above the p − -Silicon substrate; source and drain regions for a plurality of MOS transistors in the Silicon cap layer; a first depletion zone formed in the p − -Silicon substrate and associated with a first p-n junction formed by the one or more n-wells and the p − -Silicon substrate; and at least one second depletion zone formed in the epitaxial Silicon cap layer and associated with a second p-n junction formed by the source and drain regions and the one or more n-wells; wherein the one or more buried epitaxial carbon-rich Silicon layers and the epitaxial Silicon cap layer each have a respective thickness such that under operating conditions neither a) a horizontal depletion-zone portion of the first depletion zone extending parallel to a top surface of the high-resistance p − -Silicon substrate wafer and not including another depletion-zone portion of the first depletion zone bending towards the top surface of the high-resistance p − -Silicon substrate wafer, nor b) the at least one second depletion zone, change their respective extension in a depth direction that is perpendicular to the surface of the high-resistance p − -Silicon substrate wafer to an extent that any of said horizontal depletion-zone portion and said at least one second depletion zone reach any of the one or more buried epitaxial carbon-rich Silicon layers.