Patent ID: 6871311

Claim:
A semiconductor integrated circuit formed on a single semiconductor chip, comprising: a test mode input terminal supplied with a test mode signal; a transmitting circuit having a function of converting first parallel signals for a plurality of channels to a first serial signal; a receiving circuit having a function of converting a second serial signal to second parallel signals for a plurality of channels; a test signal generating circuit responsive to said test mode signal, for generating test parallel signals to be supplied to said transmitting circuit; a first selector for supplying either said test parallel signals generated by said test signal generating circuit or said first parallel signals to said transmitting circuit; a second selector responsive to said test mode signal, for supplying either said first serial signal supplied from said transmitting circuit or said second serial signal to said receiving circuit; and an operation judging circuit responsive to said test mode signal, said operation judging circuit being connected so as to receive response parallel signals from said receiving circuit, wherein each of said test parallel signals includes a pulse sequence, and each of said response parallel signals includes a pulse sequence, wherein said test signal generating circuit comprises a first circuit for generating test parallel signals that are equivalent to said first parallel signals for a plurality of channels, and wherein said operation judging circuit comprises: a plurality of second circuits each capable of holding a value of one pulse in its associated one of the pulse sequences of said response parallel signals received from said receiving circuit; a plurality of third circuits for generating expected values for pulses of pulse sequences in the response parallel signals received from said receiving circuit after the pulses whose signal values have been held, based on signal values held in said second circuits; and a plurality of fourth circuits for comparing values of pulses of the pulse sequences in the response parallel signals received from said receiving circuit with the expected values generated by said third circuits.