Patent ID: 7084465

Claim:
A semiconductor device comprising: one first-conductive-type semiconductor substrate; a plurality of second-conductive-type deep well regions formed in the semiconductor substrate; a first-conductive-type deep well region formed in the second-conductive-type deep well regions; a first first-conductive-type shallow well region formed on the first-conductive-type deep well region; a first second-conductive-type shallow well region formed on the first-conductive-type deep well region; a second first-conductive-type shallow well region formed on the second-conductive-type deep well regions; a second second-conductive-type shallow well region formed on the second-conductive-type deep well regions; a device isolation region; a second-conductive-type field effect transistor formed on the first first-conductive-type shallow well region; an input terminal which is formed on the first first-conductive-type shallow well region and which serves for changing a substrate bias of the second-conductive-type field effect transistor; a first-conductive-type field effect transistor formed on the second second-conductive-type shallow well region; an input terminal which is formed on the second second-conductive-type shallow well region and which serves for changing a substrate bias of the first-conductive-type field effect transistor; a second-conductive-type dynamic threshold transistor which is formed on the second first-conductive-type shallow well region and in which a gate electrode and the second first-conductive-type shallow well region are electrically connected to each other; and a first-conductive-type dynamic threshold transistor which is formed on the first second-conductive-type shallow well region and in which a gate electrode and the first second-conductive-type shallow well region are electrically connected to each other, wherein the second first-conductive-type shallow well region is electrically isolated from device to device by the device isolation region and the second-conductive-type deep well regions, and the first second-conductive-type shallow well region is isolated from device to device by the device isolation region and the first-conductive-type deep well region, wherein the plurality of second-conductive-type deep well regions are electrically isolated at a boundary between the first-conductive-type field effect transistor and the second-conductive-type field effect transistor, at a boundary between the first-conductive-type field effect transistor and the first-conductive-type dynamic threshold transistor, or at a boundary between the first-conductive-type field effect transistor and the second-conductive-type dynamic threshold transistor.