Patent ID: 7494893

Claim:
A method of identifying yield-relevant process parameters in an integrated circuit device fabrication process, the method comprising: processing a first set of wafers in one or multiple process modules of an integrated circuit (IC) device fabrication process to create a first set of test structures in the first set of wafers, the process module comprising a plurality of process steps with each process step including a tool where a wafer in the first set of wafers is processed; obtaining a first set of process tool data from a first set of tools in the process module, the first set of process tool data comprising process parameters by which the first set of wafers is processed in the first set of tools; testing the first set of test structures in the first set of waters to obtain a first set of defectivity data, the first set of defectivity data comprising defects found in testing the first set of test structures; and relating the first set of process tool data to a first yield of the process module to determine an impact of one or more process parameters to the first yield by determining a relationship between the first set of process tool data and the first set of defectivity data and using the relationship between the first set of process tool data and the first set of defectivity data to represent the first yield in terms of the first set of process tool data.