Patent ID: 7020851

Claim:
A universal serial bus circuit comprising: a universal serial bus controller formed on a semiconductor chip; a universal serial bus driver formed on said semiconductor chip; a first signal line pair and a second signal line pair formed on said semiconductor chip for connecting said universal serial bus controller and said universal serial bus driver; a first flip-flop pair provided in said universal serial bus controller which makes a timing of a first signal pair output to said first signal line pair, by latching the first signal pair at substantially the same time; a second flip-flop pair provided in the universal serial bus controller which makes a timing of a second signal pair input from said second signal line pair, by latching the second signal pair at substantially the same time; a third flip-flop pair provided in the universal serial bus driver which matches the timing of said first signal pair input from said first signal line pair, by latching the first signal pair at substantially the same time; and a fourth flip-flop pair provided in the universal serial bus driver which matches the timing of said second signal pair output to said second signal line pair, by latching the second signal pair at substantially the same time.