Patent ID: 7292079

Claim:
A circuit for delaying an input signal comprising: a first and a second high-threshold capacitor-coupling trigger, which receive an input signal at an input terminal of the trigger, and outputs an output signal at an output terminal of the trigger according to the input signal, each comprising: voltage step-down detecting means, with an output terminal, in response to a slow decrease in the voltage level of the input signal, for producing a step-down signal at the output terminal of the voltage step-down detecting means, wherein the step-down signal corresponds to and is delayed against the slow decrease during the slow increase; a first capacitor, coupled to the output terminal of the voltage step-down detecting means at one terminal of the first capacitor, for coupling the step-down signal with the other terminal of the first capacitor; voltage step-down charging means, having an input terminal coupled to the other terminal of the first capacitor, having an output terminal coupled to the output terminal of the trigger, and being controlled by the step-down signal from the first capacitor, for charging the output terminal of the trigger; voltage step-up detecting means, in response to a slow increase in the voltage level of the input signal, for producing a step-up signal corresponding to and being delayed against the slow increase during the slow increase; a second capacitor, coupled to an output terminal of the voltage step-up detecting means at one terminal of the second capacitor, for coupling the step-up signal with the other terminal of the second capacitor; voltage step-up discharging means, having an input terminal coupled to the other terminal of the second capacitor, having an output terminal coupled to the input terminal of the trigger, and being controlled by the step-up signal from the second capacitor, for discharging the output terminal of the trigger; a first inversion-mode PMOS capacitor, the gate being coupled to the other terminal of the first capacitor, for control the delay time of the output signal in response to a control voltage; a second inversion-mode PMOS capacitor the gate being coupled to the other terminal of the second capacitor, for control the delay time of the output signal in response to a control voltage; a first inverter, the input terminal and the output terminal of the first inverter being coupled to the output terminal of the first high-threshold capacitor-coupling trigger and the output terminal of the second high-threshold capacitor-coupling trigger respectively; and a second inverter, the input terminal and the output terminal of the second inverter being coupled to the output terminal of the second high-threshold capacitor-coupling trigger and the output terminal of the first high-threshold capacitor-coupling trigger respectively.