Patent ID: 7123538

Claim:
A semiconductor memory device comprising: an array of memory cells arranged in matrix, selected by an address by first address bits and second address bits less significant than said first address bits, said memory cells being divided into a first memory block and a second memory block based on the more significant bit of said second address bits; a burst address generating circuit for generating an address signal sequentially from a start address to start a read operation in bust mode for continuously reading a predetermined number of data of said memory cell array; a first select circuit corresponding to said first memory block including an address conversion circuit which, in the case where the most significant bit of said second address bits of said address signal meets predetermined conditions, converts an address conversion signal incremented first address bit of said address signal into the signal of said first address bits of said address signal, a first data of a predetermined number of memory cells being selected from said first memory block based on the output of said address conversion circuit; a second select circuit corresponding to said second memory block for selecting a second data of said predetermined number of memory cells from said second memory block based on said first address bits of said address signal; and a data select circuit for sequentially selecting said first data and said second data based on said second address bits of said address signal.