Patent ID: 7127667

Claim:
A Viterbi decoder for decoding a string of encoded data using partial response maximum likelihood with run-length code constraint in a DVD storage system, a trellis structure in the Viterbi decoder containing N trellis states with two-branches and K trellis states with only one branch responsive to the run-length code constraint, wherein N and K are positive integers, the Viterbi decoder comprising: a branch metric generator for calculating and outputting branch metrics for each branch responsive to encoded data; an add-compare-select unit for receiving the branch metrics and (N+K) previous candidate state metrics respective to the trellis state in the trellis structure and outputting N comparison signals; and a survivor path memory and decoding unit for receiving the N comparison signals and generating a string of decoded data; wherein the add-compare-select unit comprises: (2N+K) registers for storing the (N+K) previous candidate state metrics respective to the trellis state, wherein N previous candidate state metrics are stored in duplicate registers; N add-compare-select processors for receiving values stored in the 2 N first registers and corresponding branch metrics, and outputting N candidate state metrics and the N comparison signals, the N output candidate state metrics being stored in the registers; and K first adders for respectively adding a corresponding previous candidate state metric and a branch metric to generate a candidate state metric, which is stored in the register; wherein each add-compare-select processor comprises: a second adder for adding a first value stored in one of the registers and a first branch metric to generate a first addition result; a third adder for adding a second value stored in another of the registers and the first branch metric to generate a second addition result; a comparator for comparing the first value and the second value, and outputting a comparison signal indicating which one is minimum; and a selector for selecting either the first addition result or the second addition result as the candidate state metric according to the comparison signal; wherein each add-compare-select processor is configured with the registers being located before the comparator.