Patent ID: 8130026

Claim:
A booster circuit, comprising: a pump circuit having a plurality of charge pump circuits for outputting a boosted voltage to a first output terminal; a clock adjusting circuit that generates, from a first clock signal, a second clock signal for operating said plurality of charge pump circuits; a pump controlling circuit that outputs the first clock signal for operating said pump circuit; a first comparator coupled to said first output terminal that outputs a first output signal to said pump controlling circuit; a second comparator coupled to said first output terminal that outputs a second output signal to said pump controlling circuit; and a third comparator coupled to said first output terminal that outputs a third output signal to said pump controlling circuit, wherein a gradient of the boosted voltage is decreased when the first output signal is output to the pump controlling circuit, a frequency of the first clock signal is reduced when the second output signal is output to the pump controlling circuit, and the third output signal is output to the pump controlling circuit when the boosted voltage is higher than a set value of the boosted voltage.