Patent ID: 7045401

Claim:
A method of fabricating a strained silicon finFET device, comprising the steps of: a) providing a silicon on insulator substrate having a silicon surface having a silicon-containing multilayer on an insulator layer; a1) depositing a layer of SiGe onto the silicon on insulator substrate, the deposited SiGe having a parallel lattice constant in the directions parallel to the silicon surface and a perpendicular lattice constant in the direction perpendicular to the silicon surface, wherein the parallel lattice constant being similar to the lattice constant of silicon and the perpendicular lattice constant being greater than the parallel lattice constant; b) patterning the silicon and the SiGe multilayer into a source region and a drain region sandwiching a seed channel region, the seed channel being a seed fin structure having a parallel lattice constant and a greater perpendicular lattice constant; c) depositing an epitaxial channel layer onto the seed fin structure, the channel layer material having a lattice constant smaller than that of the perpendicular lattice constant seed fin material, wherein the epitaxial channel layer becomes a tensile strained channel layer in the direction perpendicular to the silicon surface due to the lattice mismatch between the channel layer and the seed fin structure; d) forming a gate dielectric layer on the epitaxial strained channel; and e) forming a gate over the epitaxial strained channel.