Patent ID: 8617797

Claim:
A method for manufacturing a semiconductor device that includes a plurality of gate patterns in parallel with each other within one circuit block provided over a semiconductor substrate, said method comprising: preparing a first photomask, wherein in said first photomask at least one dummy gate pattern in parallel with said gate patterns is provided when a pitch between said gate patterns is larger than a predetermined maximum pitch, so that pitches between said gate patterns including said dummy gate pattern are less than said predetermined maximum pitch, and are greater than a minimum pitch, which is a minimum distance between said gate patterns, and wherein said first photomask comprises a phase shift photomask that comprises first and second openings whose difference in phase is Ï€, said first and second openings alternating between said gate patterns including said dummy gate pattern to form phase edges therein; performing a first photolithography process upon a photoresist layer within said circuit block by using said first photomask; preparing a second photomask, wherein said second photomask comprises a trim photomask that comprises at least one trim opening corresponding to said dummy gate pattern to remove a portion of said photoresist layer corresponding to said dummy gate pattern; and performing a second photolithography process upon said photoresist layer by using said second photomask.