Patent ID: 7443198

Claim:
A non-volatile-memory-transistor based lookup table for an FPGA, comprising: a VCC power supply; a ground supply; X lookup table inputs wherein X is a positive integer; a lookup table output; a multiplexer having X address inputs, Y data inputs, and an output, wherein each address input is coupled to a separate one of said lookup table inputs, the output is coupled to the lookup table output, and Y=2X; an additional lookup table input; an inverting circuit with an input coupled to said additional lookup table input and an output; a first group of Y transistors programmably coupling said VCC supply and separate ones of the Y data inputs of said multiplexer; a second group of Y transistors programmably coupling said additional lookup table input and separate ones of the Y data inputs of said multiplexer; a third group of Y transistors programmably coupling the output of said inverting circuit and separate ones of the Y data inputs of said multiplexer; and a fourth group of Y transistors programmably coupling said ground supply and separate ones of the Y data inputs of said multiplexer.