Patent ID: 7466007

Claim:
A chip comprising: a silicon substrate; a first internal circuit in or on said silicon substrate; an ESD circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first via over said silicon substrate and in said dielectric layer, wherein said first via is connected to said ESD circuit; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride; a second via in said passivation layer and directly over said first via, wherein said second via is connected to said first via; a third via in said passivation layer, wherein said third via is connected to said first interconnecting structure; and a second interconnecting structure over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said third via and said first interconnecting structure.