Patent ID: 7161822

Claim:
A nonvolatile memory array comprising: a plurality of memory cells arranged in rows and columns, each row comprising a corresponding one of a plurality of word lines and each column comprising two of a plurality of bit lines, each memory cell comprising: a select transistor having a first current electrode, a control electrode connected to a predetermined one of the plurality of word lines corresponding to a respective row and a second current electrode connected to a predetermined first of the two of the plurality of bit lines corresponding to a respective column; and a floating gate transistor having a first current electrode connected to the first current electrode of the select transistor, a floating gate, and a second current electrode connected to a predetermined second of the two of the plurality of bit lines corresponding to the respective column; the second current electrode of the select transistor of a first memory cell and the second current electrode of the floating gate transistor of a second memory cell in an adjacent column cell location of a same column are directly connected to a same bit line.