Patent ID: 7529960

Claim:
A bus system comprising: a bus master, coupled between a main bus and a peripheral bus, the bus master generating a peripheral device selection signal, a read/write mode control signal and an address signal in response to a clock signal, the peripheral device selection signal transferring data between the main bus and a plurality of peripheral devices coupled to the peripheral bus; and a self-generated strobe signal generator that receives the peripheral device selection signal and the clock signal and generates a self-generated strobe signal to control data input/output of the plurality of the peripheral devices in response to the peripheral device selection signal and the clock signal, wherein the self-generated strobe signal generator comprises: a logical AND circuit configured to operate in response to the peripheral device selection signal and an inverted signal of the self-generated strobe signal; and a flip-flop configured to receive an output signal of the logical AND circuit, and configured to operate in response to the clock signal.