Patent ID: 8737146

Claim:
A semiconductor memory device, comprising: a first bank including a plurality of cell matrices; a second bank including a plurality of cell matrices; and a shared-fuse set, which is shared by the first bank and the second bank, configured to: receive a first cell matrix signal from the first bank and a second cell matrix signal from the second bank, wherein the first cell matrix signal and the second cell matrix signal indicate a cell matrix selected from the first bank and the second bank, respectively, generate, in response to the first cell matrix signal and the second cell matrix signal, a repair detect signal that indicates a defective cell in the selected cell matrix, and output a defect indication signal based on the repair detect signal, if the first bank or the second bank is enabled and a defective cell matrix exists in the enabled bank, wherein the shared-fuse set includes: a first defect indication signal output unit configured to output the repair detect signal as a first defect indication signal of the first bank if a first bank enable signal is activated; and a second defect indication signal output unit configured to output the repair detect signal as a second defect indication signal of the second bank if a second bank enable signal is activated, and wherein each of the first and second defect indication signal output units includes: a second latch unit configured to latch the repair detect signal if the first bank enable signal is activated, and a third latch unit configured to latch the repair detect signal if the second bank enable signal is activated.