Patent ID: 8386579

Claim:
A bit selection circuit that arbitrarily selects, from among (2 n ) input bits, (2 n−1 ) continuous output bits in the input bit arrangement (where n≧3), the bit selection circuit comprising: a first multiplexer selecting {(2 n −2)−(2 0 +2 1 + . . . +2 n−3 )} continuous bits in the input bit arrangement from among (2 n −2) input bits, excluding two first and (2 n )th input bits at both ends in the input bit arrangement, in accordance with an input first control signal; and a second multiplexer selecting (2 n−1 ) continuous output bits in the input bit arrangement from among the {(2 n −2)−(2 0 +2 1 + . . . +2 n−3 )} bits selected by the first multiplexer, the first input bit, and the (2 n )th input bit in accordance with an input second control signal, wherein the first multiplexer is an at least one-stage barrel shift selection circuit, the i-th stage (where i=1, 2, . . . , n−2) of which has arranged therein (2 n −2 i−1 −1) 2:1 selection circuits, each 2:1 selection circuit selecting one bit from among two bits of the input bits or two bits, which are output from a previous stage, in accordance with the first control signal and outputting the one bit to a subsequent stage, and the second multiplexer has an input stage having arranged therein (2 n −2 n−1 +1) 2:1 selection circuits selecting one bit from among all the bits, which are output from the first multiplexer, the first input bit, and the (2 n )th input bit in accordance with the second control signal and outputting the one bit, and an output stage having arranged therein (2 n−1 ) 2:1 selection circuits, each 2:1 selection circuit selecting one bit from among two bits, which are output from two adjacent 2:1 selection circuits in the input stage, in accordance with the second control signal and outputting the one bit as one of the output bits.