Patent ID: 8335893

Claim:
A storage device comprising; a first memory unit; a second memory unit having a greater access speed than the first memory unit; a receiving unit configured to receive from a writing device a writing instruction including a logical address in which data is to be written, data to be written in the logical address, and a speed designation instruction, which is different from the writing instruction, for designating an access speed of the logical address; a control unit configured to: determine which of a physical address of any one of the first memory unit or the second memory unit is allocated to the logical address based on the speed designation instruction received by the receiving unit; generate a management information indicating the physical address allocated to the logical address; write the data in any one of the first memory unit or the second memory unit according to the writing instruction received by the receiving unit; detect the physical address allocated to the logical address included in the writing instruction received by the receiving unit in accordance with the management information; and write the data in the detected physical address in any one of the first memory unit or the second memory unit.