Patent ID: 8518769

Claim:
A method of manufacturing a semiconductor device, comprising: forming a first insulating layer on a first semiconductor layer; forming a second semiconductor layer on the first insulating layer, the second semiconductor layer including a first region and second and third regions, the second and third regions each having a greater width than a width of the first region, the second and third regions being connected to the first region; forming a gate insulating film at least on a side face of the first region of the second semiconductor layer; forming a gate electrode on an opposite side of the gate insulating film from the first region, side faces of the gate electrode facing the second and third regions, respectively; forming gate sidewalls made of an insulating material on the side faces of the gate electrode; forming concave portions by performing etching on portions of the first insulating layer and another portions of the first insulating layer, and reducing a layer thickness of the first insulating layer in each of the portions and the another portions, the portions of the first insulating layer being located below an area that is between the gate sidewalls and the second region and between the gate below an area that is sidewalls and the third region, the another portions of the first insulating layer being located below the gate sidewalls and immediately below the first region; and forming an epitaxially-grown layer on portions of the concave portions by performing epitaxial growth using the first region as a seed, the portions of the concave portions being located immediately below the first region.