Patent ID: 7254748

Claim:
A content addressable memory (CAM), comprising: a first set of CAM locations coupled to store a first set of values; a second set of CAM locations coupled to store a second set of values; an input control circuit coupled to the first and second sets of CAM locations and operable in an error detection mode and a normal mode, wherein the second set of values is a copy of the first set of values when the input control circuit is in the error detection mode, and wherein the second set of values is independent from the first set of values when the input control circuit is in the normal mode; and a comparator coupled to compare a search key value against the first and second set of values and report an error if a first location within the first set of CAM locations that produces a match is different from a first location within the second set of CAM locations that produces a match when the input control circuit is in the error detection mode.