Patent ID: 7882380

Claim:
A system, comprising: a processor for generating a command or data; a first circuit in a first clock domain of a plurality of clock domains, the first circuit configured to receive the command or data and perform a first function based at least on the command or data; a second circuit in a second clock domain of the plurality of clock domains, the second circuit configured to perform a second function; a clock generator configured to selectively supply a plurality of clock signals to the plurality of clock domains, the plurality of clock signals including one or more clock signals for the first circuit and one or more clock signals for the second circuit; and a software interface circuit coupled to the processor and the clock generator, the software interface circuit configured to autonomously determine based at least on the command or data whether the first circuit will perform the first function or be idle in an upcoming period and whether the second circuit will perform the second function or be idle in the upcoming period, to disable one or more of the clock signals to the first circuit if the first circuit will be idle in the upcoming period, and to disable one or more of the clock signals to the second circuit if the second circuit will be idle in the upcoming period, wherein the software interface circuit is further configured to receive a second command, the second command instructing the software interface circuit to enable the one or more clock signals to the first circuit and the one or more clock signals to the second circuit whether or not the first circuit and the second circuit will be idle in the upcoming period, wherein the one or more of the clock signals to the first circuit and the one or more of the clock signals to the second circuit may be independently disabled.