Patent ID: 7181558

Claim:
A shared bus system, comprising: a bus; a first circuit coupled to said bus to access said bus; a second circuit coupled to said bus to share said bus with said first circuit, and to access said bus; a counter circuit which is provided in said second circuit, and performs a counting operation each time said second circuit accesses said bus; and an arbiter circuit coupled to said bus, said first circuit, and said second circuit to receive requests for a right to use said bus from said first circuit and said second circuit and to arbitrate the requests between said first circuit and said second circuit, wherein said second circuit releases the right to use said bus in response to detection of a predetermined number of counting operations performed by said counter circuit after acquiring the right to use said bus from said arbiter circuit, and wherein said second circuit releases the right to use said bus when a required access operation comes to an end even before said counter circuit performs the predetermined number of counting operations.