Patent ID: 8159042

Claim:
A semiconductor structure comprising: an insulator including at least a pair of adjacent interconnects, each interconnect of said pair includes a diffusion barrier material, an electrically conductive interconnect material located on an upper surface of the diffusion barrier material, and a buried electrically conductive layer embedded in a surface of said insulator and in contact with a bottom surface of said diffusion barrier material, wherein each of said buried electrically conductive layers is located on at least one sidewall of said diffusion barrier material of each respective interconnect, each of said buried electrically conductive layers has an upper surface that is coplanar with an upper surface of said electrically conductive material, and each of said buried electrically conductive layers is separated by a dielectric region which permits current flow when a bias is applied between said pair of adjacent interconnects and wherein at least one of said buried electrically conductive layers is located only partially beneath, and on one side of, said diffusion barrier material that contains one of said interconnects.