Patent ID: 7613053

Claim:
A memory device comprising: a plurality of memory cells arranged in at least one column, during a write operation a data value being written to an addressed memory cell within a selected column from said at least one column; a supply voltage line associated with each of said at least one columns, the supply voltage line being connectable to a first voltage source to provide a supply voltage at a first voltage level to the associated column; threshold circuitry connected to a second voltage source having a second voltage level, the threshold circuitry having a threshold voltage; and control circuitry, responsive to the write operation, to disconnect the supply voltage line for the selected column from the first voltage source for a predetermined period of the write operation, and during said predetermined period to connect the threshold circuitry to the supply voltage line for the selected column, such that the supply voltage to the addressed memory cell transitions to an intermediate voltage level determined by the threshold voltage of the threshold circuitry.