Patent ID: 8853830

Claim:
An integrated circuit comprising: a substrate having an active region formed in a top surface of the substrate; a plurality of vias, each extending through the substrate, each having a first termination substantially aligned with a bottom surface of the substrate and a second termination substantially aligned to the top surface of the substrate; wherein each first termination of the plurality of vias terminate on a common plane at the bottom surface and are electrically insulated from one another; a first conductive contact electrically connected to the second termination of at least one of the vias and electrically connected to a conductive interconnect layer; a first bonding joint connected to the second termination of the via and extending above a topmost insulator of the substrate, wherein there is no semiconductor substrate between the top surface of the substrate and the first bonding joint; and a second conductive contact electrically connected to the conductive interconnect layer and the active region.