Patent ID: 6870774

Claim:
A semiconductor memory device, comprising: an array of rows and columns of multi-level flash memory cells selectively programmable to have one of a plurality of different threshold voltages, each row of said flash memory cells being organized into a plurality of multi-bit words; row address decoding circuitry coupled to said array, for selecting a row of said flash memory cells in response to a plurality of decoded row address signals; column address decoding circuitry coupled to said array, for selecting columns of flash memory cells in selected rows of flash memory cells; sensing circuitry, coupled to said array, for sensing said threshold voltage of each flash memory cell in said selected row and translating each sensed threshold voltage to a multi-bit bit-set of data; read data latch circuitry, coupled to said sensing circuitry, for latching said each of said multi-bit bit-sets of data; and output circuitry, coupled to said read data latch circuitry, for outputting said latched data.