Patent ID: 7378305

Claim:
A method of fabricating a semiconductor integrated circuit device, said semiconductor integrated circuit device comprising a silicon substrate defined with a first device region and a second device region by a device isolation structure, an n-channel MOS transistor formed on said first device region and having a first gate electrode pattern, and a p-channel MOS transistor formed on said second device region and having a second gate electrode pattern, said p-channel MOS transistor including p-type SiGe mixed crystal regions formed epitaxially to said silicon substrate at both lateral sides of a channel region right underneath said second gate electrode pattern, said method comprising the steps of: forming, in each of said first and second device regions, a first sidewall insulation film on respective sidewall surfaces of said first gate electrode pattern and said second gate electrode pattern by using a first material having resistance against HF; forming a source region and a drain region of p-type in said silicon substrate at both lateral sides of said second gate electrode pattern by conducting an ion implantation process of a p-type impurity element in said second device region while using said second electrode pattern and said fist sidewall insulation film on said second gate electrode pattern as a self-aligned mask; forming, in said first device region, a second sidewall insulation film having an etching selectivity to said first sidewall insulation film, on said first sidewall insulation film formed on said first gate electrode pattern; forming a source region and a drain region of n-type in said first device region at both lateral sides of said first gate electrode pattern, by conducting an ion implantation process of an n-type impurity element in said first device region while using said first gate electrode pattern, said first sidewall insulation film and said second sidewall insulation film on said first gate electrode pattern as a self-aligned mask; forming a mask insulation film so as to cover said first device region and expose said second device region; forming, after said step of forming said mask insulation film, first and second trenches at both lateral sides of said second gate electrode pattern with separation therefrom by said first sidewall insulation film, by etching said silicon substrate in said second device region while using said second gate electrode pattern and said first sidewall insulation film on said second gate electrode pattern as a mask; and forming, after said step of forming said first and second trenches, said p-type SiGe mixed crystal regions by causing an epitaxial growth of a p-type SiGe mixed crystal layer in said first and second trenches in a state in which said first device region is covered with said mask insulation film.