Patent ID: 6972747

Claim:
A process for compensating for capacitive disturbances in a display screen including an array of electrodes disposed matrix-wise in rows lj, j varying from 1 to m, and columns ci, i varying from 1 to n, the array of electrodes being linked to image-elements, a coupling capacitor being associated with each row/column crossover, a conductor plane with a reference voltage forming capacitive elements together with the image-elements and having by design a nonzero capacitance with the columns, a row-control circuit and a column-control circuit and at least one compensation conductor bus crossing the rows, the process comprising: measuring current flowing in the conductor plane upon application of a voltage to at least one column; integrating the measured current to obtain a compensation voltage; and applying the compensation voltage to at least one of the rows via the compensation conductor bus, the compensation conductor bus being coupled capacitively to the rows, wherein the measuring the current is carried out by a first impedance in series with the conductor plane and the integrating the current is carried out by an integrator circuit arranged in parallel with the first impedance, and wherein the integrator circuit is constituted by an operational amplifier and a filter formed of a capacitor and of a resistor in parallel, and which is arranged between the output terminal and one of the input terminals of the operational amplifier.