Patent ID: 8532248

Claim:
A shift register unit circuit, comprising: input terminals including a start signal input terminal, a first clock signal input terminal and a second clock signal input terminal; a pre-charging circuit for outputting a turn-on level in response to an enable level of a start signal and of a first clock signal, and keeping the turn-on level being output during one clock period of the first clock signal; a level pulling-down circuit for pulling down a level at an output terminal of the pre-charging circuit and outputting a low level in response to an enable level of the second clock signal, and for outputting a high level in response to a disable level of the second clock signal, after the turn-on level is input; and for outputting the high level after the turn-on level is turned off; an outputting circuit, which is coupled to the output terminal of the level pulling-down circuit, for pulling down a level at an output terminal of the outputting circuit and outputting the low level in response to the high level output from the level pulling-down circuit, and for outputting the high level in response to the low level output from the level pulling-down circuit; and a scan signal output terminal, which is coupled to the output terminal of the outputting circuit, for outputting a scan signal.