Patent ID: 8593201

Claim:
A signal output circuit comprising: an input buffer, a generation control circuit, a control voltage generation circuit, and an output circuit, each using npn transistors, wherein the input buffer externally receives a single-phase switching instruction signal for instructing to switch a state of the output circuit to one of a shutdown disable state and a shutdown enable state, and converts and outputs the single-phase switching instruction signal into a differential switching instruction signal formed from two signals having phases opposite to each other, the generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signal, the control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal based on the generation control signal, and the output circuit externally receives a differential input signal, outputs a differential output signal upon impedance-converting the differential input signal, and switches between the shutdown disable state and the shutdown enable state of the differential input signal based on the control voltage, wherein the generation control circuit comprises a first npn transistor having a collector and base connected to a first power supply potential on a high-potential side, a second npn transistor having a base receiving a signal, of the differential switching instruction signals, which is in phase with the single-phase switching instruction signal, a collector connected to an emitter of the first npn transistor, and an emitter connected to a second power supply potential on a low-potential side via a first resistor, and a third npn transistor having a base receiving a signal, of the differential switching instruction signals, which is opposite in phase to the single-phase switching instruction signal, an emitter connected to an emitter of the second npn transistor, and a collector from which the generation control signal is output.