Patent ID: 7751262

Claim:
A random access memory comprising: a plurality of memory storage elements arranged in rows and columns and each memory element coupled to a bit line and a word line, an address register for receiving an address on a first clock edge, a precharge circuit for precharging the bit line, the precharge circuit responsive to the first clock edge, a row decoder for: decoding a first segment of the address; and activating a word line corresponding to the first segment of the address, a delay circuit for timing deactivation of the precharge circuit and the activation of the word line, a column decoder for: decoding a second segment of the address; and selecting a bit line corresponding to the second segment of the address, a sense amplifier for: sensing data on the bit line; and restoring data in the memory element coupled to the selected bit line and the activated word line, and an output circuit for outputting the data.