Patent ID: 8809927

Claim:
A semiconductor memory device comprising a memory cell array, the memory cell array comprising: a first sense amplifier circuit and a second sense amplifier circuit; first to fourth bit lines, an end of the first bit line and an end of the second bit line being electrically connected to the first sense amplifier circuit, and an end of the third bit line and an end of the fourth bit line being electrically connected to the second amplifier circuit; an island-shaped semiconductor region over the first bit line; a gate insulator over the island-shaped semiconductor region; two word lines over the gate insulator and the island-shaped semiconductor region; and a capacitor overlapping the island-shaped semiconductor region, over the two word lines, wherein the third bit line is provided between the end of the first bit line and the end of the second bit line over the first sense amplifier circuit, and wherein the second bit line is provided between the end of the third bit line and the end of the fourth bit line over the second sense amplifier circuit.