Patent ID: 7701257

Claim:
A data receiver comprising a plurality of equalizers, each of the plurality of equalizers including: a sense amplifier configured to selectively sense and amplify a difference between input data and a first reference voltage or a difference between the input data and a second reference voltage in response to a clock signal and a plurality of control signals; and a latch coupled to the sense amplifier and configured to latch an output signal of the sense amplifier, the plurality of control signals being output signals of the sense amplifier included in another one of the plurality of equalizers, wherein the sense amplifier comprises: a first differential transistor pair configured to receive the input data and amplify a difference between the in input data and the first reference voltage; and a second differential transistor pair configured to receive the in input data and amplify a difference between the input data and the second reference voltage, the output of the first differential transistor pair coupled to the output of the second differential transistor pair.