Patent ID: 7244987

Claim:
A vertical NROM flash memory array comprising: a substrate having a doped region of a different conductivity type than the substrate extending along the substrate, the doped region acting as a first source/drain region; a plurality of oxide pillars extending from the first source/drain region; a plurality of ultra-thin silicon body regions each formed along an opposing sidewall of an oxide pillar, each ultra-thin silicon body region being fully depleted; a polysilicon material formed on top of each oxide pillar and each body region, the polysilicon material acting as a second source/drain region and having the same conductivity type as the first source/drain region; a continuous oxide layer formed over the substrate, body regions, and second source/drain regions such that the oxide layer has a greater thickness along the substrate than in other areas; a nitride-oxide layer formed over the oxide layer only on the opposing sides of each oxide pillar; and a polysilicon control gate formed over each nitride-oxide layer wherein the control gate extends upwards to at least the top of each oxide pillar.