Patent ID: 8461879

Claim:
A packaged controller comprising: a first die comprising a processor, a first terminal, an analog-to-digital converter (ADC), a serial bus interface, and a sequencer, wherein the ADC is coupled to receive an analog signal from the first terminal, wherein the sequencer is coupled to supply a start convert signal to the ADC, and wherein the sequencer is programmable by the processor; a second die comprising a serial bus interface, a first terminal, a plurality of sample/hold circuits, and an analog multiplexer, wherein a serial bus clock signal is communicated from the serial bus interface of the first die to the serial bus interface of the second die, wherein the analog multiplexer couples an output lead of a selected one of the sample/hold circuits to the first terminal of the second die such that a signal from the selected one of the sample/hold circuits is supplied through the first terminal of the second die and through the first terminal of the first die to the ADC of the first die, wherein a trigger signal is asserted within the first die and in response the sequencer causes a first multi-bit value to be communicated from the serial bus interface of the first die to the serial bus interface of the second die, wherein a receiving of at least part of the first multi-bit value onto the second die: 1) causes a sample/hold signal supplied to the plurality of sample hold circuits to be asserted, and 2) determines which one of the sample/hold circuits is coupled through the analog multiplexer to the first terminal of the second die, wherein a latency period between a time when the trigger signal is asserted and a time when the sample/hold signal is asserted is less than eight periods of the serial bus clock signal; and a package that contains the first die and the second die.