Patent ID: 7105884

Claim:
Memory circuitry comprising: a semiconductor substrate; a plurality of word lines received over the semiconductor substrate; an insulative layer received over the word lines and the substrate, the insulative layer comprising at least a single well formed therein, the well comprising a base of said insulative layer received over the word lines, the insulative layer within which said well is formed peripherally defining an outline of a memory array area, area peripheral to the well comprising memory peripheral circuitry area; a plurality of memory cell storage capacitors received within said single well over the word lines; peripheral circuitry within the peripheral circuitry area operatively configured to write to and read from the memory array; and the insulative layer has a substantially planar outermost surface, and the capacitors have inner capacitor storage node electrodes having topmost surfaces received elevationally proximate the substantially planar outermost surface of the insulative layer.