Patent ID: 8750022

Claim:
A semiconductor memory device comprising: a memory cell including a first transistor and a memory element; a pre-charge circuit including a second transistor; a clocked inverter; and a switch, wherein a gate of the first transistor is electrically connected to a first line, one of a source and a drain of the first transistor is electrically connected to a second line, and the other of the source and the drain of the first transistor is electrically connected to one electrode of the memory element, wherein one of a source and a drain of the second transistor is electrically connected to a third line, and the other of the source and the drain of the second transistor is electrically connected to one terminal of the switch and an input terminal of the clocked inverter, wherein an output terminal of the clocked inverter is electrically connected to an output signal line, wherein the other terminal of the switch is electrically connected to the second line, wherein a channel formation region of the first transistor and a channel formation region of the second transistor each include an oxide semiconductor, and wherein an off current value of the first transistor is lower than or equal to 10 aA/μm.