Patent ID: 8629018

Claim:
A method of forming a NAND memory construction, comprising: forming openings extending into a semiconductor material; vertically-extending pillars of the semiconductor material being between the openings; individual pillars having a pair of opposing vertically-extending sides along a cross-section, said opposing vertically-extending sides being a first side and a second side; implanting first dopant into the semiconductor material along the sidewalls of the openings to form first doped regions; filling the openings with first dielectric material to form dielectric regions extending into the substrate; each dielectric region being paired with a directly adjacent semiconductor material pillar along a pillar/dielectric region interface; forming a patterned mask which has gaps extending therethrough to expose segments comprising the pillar/dielectric region interfaces; extending the gaps into the semiconductor material pillars and dielectric regions to form receptacles at locations previously occupied by the pillar/dielectric region interfaces; implanting second dopant into the semiconductor material along the sidewalls of the receptacles to form second doped regions, one of the first and second dopants being n-type and the other being p-type; forming horizontally-extending interconnect lines at the bases of the receptacles and then forming second dielectric material within the receptacles over the interconnect lines; forming select devices over the semiconductor pillars; the select devices having vertical channels directly against the semiconductor material pillars, the vertical channels having a pair of opposing vertically-extending sides along the cross-section, and having electrically conductive gate lines along said opposing sides and spaced from the vertical channels by gate dielectric material, the second doped regions extending from the vertical channels to the interconnect lines; and forming vertical NAND strings over the select devices.