Patent ID: 8878762

Claim:
A level shifter for a source driver of a liquid crystal display, comprising: an input stage for generating a signal with a voltage of between a positive input source voltage and a negative input source voltage according to an input logic; a middle stage for generating a first logic signal, an inverted first logic signal, a second logic signal, and an inverted second logic signal according to the signal; and an output stage, receiving the first logic signal, the inverted first logic signal, the second logic signal, and the inverted second logic signal, for generating a first output signal with a voltage of between a first positive output source voltage and a first negative output source voltage at a first output terminal using the received first logic signal and the received inverted first logic signal and a second output signal with a voltage of between a second positive output source voltage and a second negative output source voltage at a second output terminal using the received second logic signal and the received inverted second logic signal, wherein the output stage further comprises: a second up-level circuit for generating the first output signal according to the first logic signal and the inverted first logic signal, wherein the second up-level circuit further comprises: a first p-type transistor and a second p-type transistor, coupled with a first voltage source; a first n-type transistor, coupled with the first p-type transistor and a second n-type transistor, coupled with the second p-type transistor, wherein the gate of the first p-type transistor is connected with the gate of the first n-type transistor, and the gate of the second p-type transistor is connected with the gate of the second n-type transistor; a third n-type transistor, coupled with the first n-type transistor and a second voltage source; and a fourth n-type transistor, coupled with the second n-type transistor and the second voltage source, wherein the gate of third n-type transistor and the drain of the second p-type transistor are connected to the first output terminal; and a second down-level circuit for generating the second output signal according to the second logic signal and the inverted second signal.