Patent ID: 8531037

Claim:
A semiconductor chip having a power supply line with a minimized voltage drop, the semiconductor chip comprising: a circuit positioned in a center region of the semiconductor chip; a VDD main line extending around the circuit; a VSS main line extending around the circuit; a first branch line connected to the VDD main line and the circuit; a second branch line connected to the VSS main line and the circuit; a first power supply pad positioned on a first edge of the semiconductor chip, connected to the VDD main line, and configured to provide VDD power to the circuit via the VDD main line and the first branch line; a second power supply pad positioned on the first edge of the semiconductor chip, connected to the VSS main line, and configured to provide VSS power to the circuit via the VSS main line and the second branch line; and a plurality of electrostatic discharge (ESD) improvement dummy pads each connected to the VDD main line, the VSS main line, a third branch line, and a fourth branch line, wherein each of the ESD improvement dummy pads is configured to provide VDD power from the VDD main line to the circuit via its respective third branch line, wherein each of the ESD improvement dummy pads is configured to provide VSS power from the VSS main line to the circuit via its respective fourth branch line, and wherein each of the ESD improvement dummy pads is positioned far from the first and second power supply pads on a second edge of the semiconductor chip opposite from the first edge of the semiconductor chip.