Patent ID: 8526225

Claim:
A memory device comprising: an array of memory cells for storing data, each memory cell having a first layer comprising copper in contact with a second layer comprising a chalcogenide material, the second layer including an interfacial layer in contact with the first layer; and a voltage application unit configured and arranged with the interfacial region to write data by switching the interfacial layer in each cell between a first resistance state and a second lower resistance state by applying a voltage to each cell and using the applied voltage to trap carriers within the interfacial layer, the trapped carriers setting the resistance of the interfacial layer to a resistance that is different than a resistance of a portion of the second layer that does not include the interfacial layer, switch one of the cells to the first resistance state by applying a potential difference across the first and second layers such that the potential at the first layer is higher than the potential at the second layer by about 0.5 volts or less, and switch one of the cells to the second resistance state by applying a potential difference across the first and second layers such that the potential at the second layer is higher than the potential at the first layer by about 0.5 volts or less.