Patent ID: 7274705

Claim:
A system comprising: a core that transmits and receives signals at a first clock speed; a receive buffer in communication with said core and configured to transmit said signals to said core at said first clock speed; a transmit buffer in communication with said core and configured to receive signals from said core at said first clock speed; a sync configured to allow signals to be received in said receive buffer at a second clock speed and to allow signals to be transmitted from said transmit buffer at said second clock speed, said sync in communication with said transmit buffer and said receive buffer; a command bus in communication with said sync, said transmit buffer, and said receive buffer; a data bus in communication with said sync, said transmit buffer, and said receive buffer; a processor in communication with said command bus and said data bus, said processor having, a bus arbitrator in communication with said command bus and said data bus to receive, transmit and manage signals transferred along said command bus and said data bus; and an access controller in communication with said bus arbitrator to process said signals.