Patent ID: 8873312

Claim:
A decoder circuit of a semiconductor storage device, comprising: a word line selection circuit that includes, for each of a plurality of word lines, a first voltage application MOS transistor that applies a normal voltage to the word lines corresponding to memory cells selected among a plurality of memory cells positioned at a portion where the plurality of word lines intersect a plurality of bit lines in a predetermined normal operation, and that applies a high voltage higher than the normal voltage in a predetermined high voltage operation, and to which a control signal is input, and a second voltage application MOS transistor connected to the first voltage application MOS transistor, and that includes a control MOS transistor that controls a voltage output to the first voltage application MOS transistor; and a level shift circuit that outputs, to the control MOS transistor, one out of the normal voltage or a ground voltage lower than the normal voltage according to a selection state of the word line in the normal operation, and that outputs, to the control MOS transistor, one out of the normal voltage or the high voltage according to a selection state of the word line in the high voltage operation.