Patent ID: 8166249

Claim:
A method, in a data processing system having a co-processor, memory, and processor, for processing a set of instructions used to access the memory the method comprising: receiving, by the co-processor, the set of instructions from the processor to access a main memory by the co-processor, wherein the set of instructions comprises a set of virtual addresses; and translating, by the co-processor the set of virtual addresses into a set of absolute addresses in order for the co-processor to access the main memory, wherein translating the set of virtual addresses into the set of absolute addresses comprises: accessing, by the co-processor, a Translation Lookaside Buffer (TLB) comprising a plurality of zones that are assigned by the co-processor to identify virtual addresses that are accessed during execution of the set of instructions in a flexible manner more than one at a time; identifying, by the coprocessor, a set of oldest zones in the plurality of zones based on an actual compression service call (CMPSC) instruction using a Least Recently Used (LRU) algorithm, wherein the CMPSC instruction identifies a dictionary size required to execute the instruction and wherein a number of zones of the plurality of zones proportionally relates to the dictionary size; and replacing, by the co-processor, one or more of the set of oldest zones based on the set of oldest zones identified using the LRU algorithm.