Patent ID: 8409962

Claim:
A method of manufacturing a copper interconnection structure with MIM (metal-insulator-metal) capacitor, comprising steps of: (a) making a first copper conductive pattern on a first insulation layer; (b) depositing a first etch stop layer on the first insulation layer, producing a second insulation layer on the first etch stop layer, and making at least one first copper through hole bolt in the second insulation layer connecting with the first copper conductive pattern; (c) deposit a second etch stop layer on the second insulation layer, and produce a third insulation layer on the second etch stop layer; (d) etching out the second and third insulation layer and the first and second etch stop layer around the first copper through hole bolt from the third insulation layer to the first copper conductive pattern for exposing a top and side surface of the first copper through hole bolt and part of a top surface of the first copper conductive pattern forming a recession area; (e) depositing a dielectric layer on top surface of the third insulation layer, an inner surface of the recession area, and an outer surface around the first copper through hole bolt, and filling a protection material which is BARC (Bottom Anti-reflection Coating) material in the recession area covered by the dielectric layer; (f) etching a trench in the third insulation layer from the dielectric layer on the third insulation layer to a bottom of the second etch stop layer for receiving other copper conductive patterns; (g) removing the protection material; (h) plating copper in the recession area covered by the dielectric layer forming an upper electrode of an MIM capacitor, and plating copper in the trench formed in step (f) to form the other copper conductive pattern, so as to obtain a copper interconnection structure with MIM capacitor.