Patent ID: 8384202

Claim:
A semiconductor device comprising a first package embedding a first element, and a second package stacked on and fixed to the first package while internally housing a second element, wherein the first package includes a lead frame and a metallization wiring, and wherein: a certain end of the lead frame is formed as a first external terminal exposed in flush relation with an outer surface of the first package; and metallization wiring resin molded within the first package and including a transfer lead frame having a portion on a surface of molded resin, and having a peripheral region exposed on the side of and in flush relation with the molded resin so as to serve as a second external terminal, the first element including an insulting layer, the first element mounted on the second external terminal of the metallization wiring in at least partially overlapped relation therewith, separated from the second external terminal by the insulator layer, the first element electrically connected to the lead frame and the metallization wiring; and one of the first and second external terminals is exposed on one of upper and lower surfaces of the first package to serve as a mounting terminal, and a remaining one of the first and second external terminals is exposed on a remaining one of the upper and lower surfaces and electrically connected to an external terminal of the second package.