Patent ID: 8649609

Claim:
An FPGA architecture, comprising: a rectification module configured to receive image data from memory and rectify the image data; a filter module configured to receive the rectified image data and filter unwanted data from the rectified image data to generate filtered image data wherein the rectification module and filter module are operatively connected by two pass-through agents associated with the rectification module and filter module respectively; a disparity module configured to receive the filtered image data and generate a result in order to determine a distance between an object and a vehicle, wherein the filter module and disparity module are operatively connected by two pass-through agents associated with the filter module and disparity module respectively; and, a plurality of arbiters, each arbiter interfacing with the memory, wherein each arbiter is configured to receive a request for data from one or more read agents associated with the rectification module, filter module, or disparity module, and wherein a write agent associated with the disparity module is configured to transmit the result to the memory.