Patent ID: 7990781

Claim:
A device comprising: a memory configured to store data; and a memory controller connected to the memory via a plurality of data lines, for writing a data burst as a plurality of data signals, and a strobe line, for transmitting a strobe signal used to control writing of the data signals to the memory, the memory controller including: a plurality of write data generation circuits to each transmit one of the data signals on one of the data lines, the plurality of write data generation circuits being controlled by write enable signals, and a write strobe generation circuit to generate the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the plurality of write data generation circuits, where the write strobe generation circuit includes: logic to generate a first signal that includes the preamble window, the data transfer window, and the postamble window, a buffer to receive the first signal, and logic to generate a drive enable signal that is input to the buffer, the drive enable signal controlling the buffer to source either a tri-state condition or the first signal to an output pad, where the output pad sources the strobe signal to the memory.