Patent ID: 6897141

Claim:
A method for forming a solder terminal structure, the method comprising: forming an insulating layer on a surface of a semiconductor device chip; exposing a plurality of electrode pads separated from each other, by etching the insulating layer selectively; forming an adhesion metal layer, a thermal diffusion barrier and a solder bonding layer in order on the exposed electrode pads and the insulating film; coating photoresist layer on the solder bonding layer and patterning the photoresist layer by exposing and developing so that the solder bonding layer above each electrode pad is selectively exposed; plating solder on the exposed solder bonding layer; removing the patterned photoresist layer and etching the solder bonding layer by using the plated solder as a mask; forming solder bumps by attaching the plated solder to the solder bonding layer; and etching the thermal diffusion barrier and the adhesion metal layer using the solder bumps as a mask.