Patent ID: 7348814

Claim:
A method of generating a power-on reset signal of a circuit, the power-on reset signal having a leading part and a trailing part, comprising: in response to an initial voltage rise of a voltage supply during power-on: initializing any node voltages of the circuit that determine an output voltage of an output node; and generating the leading part of the power-on reset signal, such that at least part of the leading part rises as the voltage supply rises toward a level providing reliable power, including: coupling an inverter output to the voltage supply; coupling, via the inverter, the voltage supply to a gate of a transistor coupled to a ground; and coupling, via the transistor coupled to the ground, an input of a second inverter to the ground; setting an input voltage of a signal source, via at least a first transistor external to the signal source having a nonzero threshold voltage adjusted by ion implantation; in response to a continuing voltage rise of the voltage supply: decoupling, from the power-on reset signal, a circuit generating the leading part of the power-on reset signal; raising the input voltage of the signal source past the trip point voltage of the signal source; and after said decoupling, generating, from the signal source, the trailing part of the power-on reset signal.