Patent ID: 8374296

Claim:
An output system having reduced spurious content, comprising: clock circuitry configured to generate a clock signal; signal generation circuitry configured to receive the clock signal and to generate a digital signal based upon the clock signal, the digital signal having spurious frequency content; output circuitry configured to receive the digital signal from the signal generation circuitry, to receive the clock signal, and to generate a digital output signal based upon the clock signal; first voltage supply circuitry coupled to provide a first supply voltage to the signal generation circuitry, the first supply voltage having spurious frequency content; and second voltage supply circuitry coupled to provide a second supply voltage to the output circuitry; wherein the second supply voltage from the second voltage supply circuitry has reduced spurious content as compared to the first supply voltage from the first voltage supply circuitry; and wherein the digital output signal from the output circuitry has reduced spurious content as compared to the digital signal from the signal generation circuitry.