Patent ID: 8284645

Claim:
A cyclic memory which performs repetitive control for a compensation target signal, comprising: an adder to which a compensation target signal having a periodic frequency component is inputted; and a feedback signal system for receiving an output signal of adder and inputting an output of the feedback signal system to the adder, said feedback signal system including: a filter unit for outputting a signal component included in a learning frequency band that is arbitrarily set among the output signal of the adder; a memory for successively updating and storing the output signal component of the filter unit; a phase correction unit for correcting, when inputting an outputting signal from the memory to the adder, a phase amount of an outputting signal to the adder; and a gain element for multiplying an output signal from the phase correction unit for each one period that is phase-corrected by the phase correction unit by a value not less than 0 and not larger than 1, and inputting the product to the adder, wherein the feedback signal system successively updates and stores into the memory the output signal of the adder for each one period, and inputs the outputting signal stored in the memory for one period stored in the memory back to the adder.