Patent ID: 7038474

Claim:
A system for critical parameter analysis (CPA) of a semiconductor device (DUT), comprising: a laser scanning microscope (LSM); automated test apparatus (ATE) for providing predefined stimulus to the semiconductor device (DUT), for comparing responses from the semiconductor device (DUT) against a set of predefined expected responses, and for generating a short output pulse when a difference is detected between responses from said semiconductor device (DUT) and said predefined expected responses, said automated test apparatus being connected to the DUT while the DUT is disposed within a scanning chamber of said laser scanning microscope (LSM); display means for displaying an image of said semiconductor device produced by said laser scanning microscope (LSM); means for overlaying a visible representation of said short output pulse on said displayed image to indicate a corresponding position on the semiconductor device (DUT) of a scanning beam of the laser scanning microscope (LSM) at the time the output pulse was generated; and means for simultaneously scanning said semiconductor device (DUT) with said laser scanning microscope (LSM) while said ATE repeatedly applies said predefined stimulus to said DUT and compares responses therefrom against said predefined expected responses; wherein the automated test apparatus (ATE) and the semiconductor device (DUT) form a closed loop feedback system; the automated test apparatus (ATE) is programmed to ‘break’ in or out of a vector loop which is detecting pass/fail operation of the semiconductor device (DUT); and said automated test apparatus (ATE) is configured to repeatedly cycle (“short-cycle”) said predefined stimulus from a starting point up to a point of failure when such failure is detected.