Patent ID: 7598175

Claim:
A method for confined area planarization of a semiconductor wafer, comprising: disposing a proximity head over and proximate to a top surface of a semiconductor wafer such that a cation exchange membrane of the proximity head faces the top surface of the semiconductor wafer; disposing an electrolyte solution between a top surface of the cation exchange membrane and a cathode; flowing deionized water between a bottom surface of the cation exchange membrane and the top surface of the semiconductor wafer; controlling a flow rate of the deionized water such that the cation exchange membrane flexes toward the top surface of the semiconductor wafer under the influence of a Bernoulli force without contacting the top surface of the semiconductor wafer and such that a substantially uniform separation distance is maintained between the cation exchange membrane and the top surface of the semiconductor wafer; and applying a bias voltage between the top surface of the semiconductor wafer and the cathode such that cations liberated from the top surface of the semiconductor wafer are influenced to travel through the deionized water through the cation exchange membrane through the electrolyte solution to the cathode.