Patent ID: 7374980

Claim:
A method of fabricating a field effect transistor, comprising: forming a dielectric isolation along a perimeter of a region of a silicon layer to define a silicon body in said silicon layer; forming a gate dielectric layer on said silicon body, a bottom surface of said gate dielectric layer in direct physical contact with a top surface of said silicon body; and forming an electrically conductive gate electrode on said gate dielectric layer, bottom surface of said gate electrode in direct physical contact with a top surface of said gate dielectric layer, said gate electrode having a first region having a first thickness and a second region having a second thickness, said first region extending along said top surface of said gate dielectric layer over said channel region, said second thickness greater than said first thickness; and wherein said forming said gate electrode includes: forming a polysilicon layer on said top surface of said gate dielectric layer; oxidizing a less than whole thickness of said polysilicon layer in a region of said polysilicon layer over said body to form an oxidized polysilicon layer; after forming said source and said drain, removing said oxidized polysilicon layer to form said first region of said gate electrode; and simultaneously converting said first region of said gate electrode to a metal silicide layer and forming said metal silicide layer on exposed surfaces of said second region of said gate electrode.