Patent ID: 7217647

Claim:
A method of fabricating a field effect transistor comprising the steps of: providing a semiconductor substrate having a gate stack on a top surface of the semiconductor substrate, and a first spacer formed on a sidewall of the gate stack; forming, in or on the semiconductor substrate, a silicide adjacent to the first spacer, using the first spacer as a mask; forming a second spacer from one of silicon dioxide and silicon carbide adjacent to and covering the surface of the first spacer, wherein the second spacer covers only a portion of the silicide; forming a contact liner from silicon nitride over at least the gate stack, the second spacer and the silicide; forming an interlayer dielectric over the contact liner; using a first etch process selective to silicon nitride, forming an opening to expose the contact liner over the silicide; and, using a second etch process selective to both the second spacer material and the silicide, extending the opening through the contact liner to expose the silicide without exposing the substrate.