Patent ID: 8036848

Claim:
A method of testing a semiconductor wafer using a semiconductor chip test program stored in a storage unit of a semiconductor wafer testing apparatus, the method comprising: selecting a predetermined number of semiconductor chips from among a plurality of semiconductor chips formed on a semiconductor wafer using said semiconductor wafer testing apparatus; performing a first test on I/O pins of each of said selected semiconductor chips using said semiconductor wafer testing apparatus; and performing a second test on a part of said I/O pins of each one of the non-selected semiconductor chips using said semiconductor wafer testing apparatus, wherein said semiconductor wafer is divided into n regions, wherein n is a natural number more than 1, and said plurality semiconductor chips are formed in said n regions, said selecting comprises: selecting m regions from said n regions, wherein m is a natural number smaller than n; and selecting semiconductor chips from each of said selected m regions as said semiconductor chips of the predetermined number, and said J semiconductor chips are in a range of 0.1 to 0.3% of said plurality of semiconductor chips.