Patent ID: 8415975

Claim:
An apparatus comprising: one or more input interfaces to receive one or more input signals; first logic elements that are individually programmable to be one of a truth table, data register, and a buffer register; second logic elements that are programmable decoders; third logic elements that are individually programmable to be one of a counter, delay element, and a filter; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that selectively forms one or more interconnections within a group comprising the one or more input interfaces, the one or more output interfaces, and the logic elements, wherein the programmable interconnect array is programmable in routing the one or more input signals to at least a portion of the logic elements, is programmable in routing one or more intermediate signals among at least a portion of the logic elements, and is programmable in routing one or signals from at least a portion of the logic elements to produce the one or more output signals via the output interface.