Patent ID: 8456348

Claim:
An SAR ADC capable of reducing energy consumption, comprising: a comparator, having a positive input end, a negative input end, and a comparison output end; a capacitor circuit, having a first capacitor array and a second capacitor array, and both said first capacitor array and said second capacitor array including N groups of capacitors, in which a first group has one capacitor with a capacitance of C, a second group has one capacitor with a capacitance of C, a third group has one capacitor with a capacitance of 2C, and a K-th group has K−2 capacitors with capacitances of 2C, 2 1 C, 2 2 C, . . . 2 K-3 C, K=4 to N, and each of said capacitors of said first capacitor array has an electrode coupled to said positive input end of said comparator, and each of said capacitors of said second capacitor array has an electrode coupled to said negative input end of said comparator; a sampling switch, having one side coupled to a positive input voltage and a negative input voltage, and the other side coupled to said positive input end and said negative input end of said comparator; a logic circuit, having a bit input terminal, N bit output terminals, and a plurality of switch control output terminals, wherein said bit input terminal is coupled to said comparison output end of said comparator, and said switch control output terminals are used for outputting a plurality of switch control signals; and a voltage selecting circuit, used for making the other electrodes of said capacitors of said capacitor circuit floating or coupled to a reference voltage, a common mode voltage, or a ground voltage.