Patent ID: 7161202

Claim:
A semiconductor memory device comprising: a first bit line and a second bit line constituting a bit line pair; a first ferroelectric capacitor having a first electrode and a second electrode provided below the first electrode, the first electrode being selectively electrically connected to the first bit line and the second electrode being selectively provided with a drive potential; a second ferroelectric capacitor having a third electrode and a fourth electrode provided below the third electrode, the third electrode being selectively provided with the drive potential and the fourth electrode being selectively electrically connected to the first bit line; a third ferroelectric capacitor having a fifth electrode and a sixth electrode provided below the fifth electrode, the fifth electrode being selectively electrically connected to the first bit line or the second bit line and the sixth electrode being selectively provided with the drive potential; a fourth ferroelectric capacitor having a seventh electrode and an eighth electrode provided below the seventh electrode, the seventh electrode being selectively provided with the drive potential and the eighth electrode being selectively electrically connected to the first bit line or the second bit line; and a sense amplifier amplifying the potential difference between the first bit line and the second bit line.