Patent ID: 8076703

Claim:
A stress-enhanced semiconductor device, comprising: a substrate comprising an inactive region and an active region, wherein the active region comprises: a lateral edge which defines an active width of the active region, and a transverse edge which defines a length of the active region; a gate electrode structure comprising: a common portion spaced apart from the active region by a first distance; and a plurality of gate electrode finger portions integral with the common portion, wherein a portion of each gate electrode finger portion overlies the active region, wherein a gate length of the portion of each gate electrode finger portion which overlies the active region is substantially uniform; and a compressive layer overlying the active region and the gate electrode finger portions; and a tensile layer overlying the inactive region, the tensile layer being disposed adjacent the transverse edge of the active region so that the tensile layer does not overlie the gate electrode structure, wherein a portion of the tensile layer overlaps with a portion of the compressive layer.