Patent ID: 7888194

Claim:
A method of fabricating a complementary metal oxide semiconductor (CMOS) device, comprising: providing a substrate which comprises a first region and a second region; forming a first conductive type MOS field effect transistor (FET) on the substrate in the first region, wherein the first conductive type MOSFET comprises a first gate structure and a first source/drain region using a semiconductor compound as major material; forming a second conductive type MOSFET in the substrate in the second region, wherein the second conductive type MOSFET comprises a second gate structure and a second source/drain region; performing a pre-amorphous implantation (PAI) process after the first and second conductive type MOSFETs are formed, so as to amorphize a gate conductive layer of the second gate structure in the second region; forming a stress-transfer-scheme (STS) on the substrate in the second region; performing a rapid thermal annealing (RTA) process; and removing the STS.