Patent ID: 7714352

Claim:
A semiconductor device, comprising: a first conductivity-semiconductor substrate; a hetero semiconductor region configured to form a hetero junction in combination with the first conductivity-semiconductor substrate; a gate electrode configured to be adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode configured to connect to the first conductivity-semiconductor substrate; a source electrode configured to connect to the hetero semiconductor region; and a second conductivity-semiconductor region which is a field relaxing region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode by way of the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point, wherein a first face of the second conductivity-semiconductor region has an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region, wherein a depletion layer is formed by a junction between the second conductivity-semiconductor region and the first conductivity-semiconductor substrate, wherein the inversion layer controls a thickness of the depletion layer, and wherein a distance between the second conductivity-semiconductor region and the triple contact point is smaller than a length reached by the depletion layer attributable to a built-in potential.