Patent ID: 7966531

Claim:
A memory diagnosis apparatus that diagnoses a failure in a memory, the memory diagnosis apparatus comprising: an intra-block testing unit that tests for a failure with respect to each bit in each block in the memory; and an inter-block testing unit that tests for a failure between blocks in the memory, wherein the intra-block testing unit repeatedly performs a process of writing a predetermined test pattern in a test-target block and then a process of comparing data read from the test-target block and the test pattern while changing the test pattern, and the inter-block testing unit repeatedly performs a process of writing a predetermined first test pattern in all the blocks, writing an inverted test pattern that is obtained by inverting the first test pattern in one of the blocks, and then a process of comparing data read from blocks other than the block in which the inverted test pattern is written and the first test pattern while successively changing the block in which the inverted test pattern is written in units of block.