Patent ID: 8552551

Claim:
A multiple-die semiconductor chip package comprising: a substrate; a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface; wires bonded to and extending from the bond pads outwardly past the periphery to the substrate; a second die with an electrically non-conductive second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer entirely covering the second surface; a plurality of spaced-apart adhesive/spacer islands within the die bonding region securing the first and second die to one another at a chosen separation to create a multiple-die assembly, the adhesive/spacer islands including deformable spacer elements having a generally ellipsoidal shape and occupying a first percentage of the die bonding region; the adhesive/spacer islands comprising at least one spacer element within an adhesive; and a material encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.