Patent ID: 8261121

Claim:
A method comprising: operating, in a computing system, an arbitration logic of a memory controller at a core clock frequency lower than that of a memory clock frequency, the core clock frequency defining operating frequency of a core of the memory controller configured to generate a command sequence comprising a plurality of commands in accordance with a plurality of external requests to access a memory, the memory clock frequency defining operating frequency of the memory, and the arbitration logic being configured to resolve a contention between the plurality of external requests to share a command bus in order to access the memory; parallelizing, at the core clock frequency, the plurality of commands in the command sequence originating at the core clock frequency based on a timing requirement for a non-first command in the command sequence defined by a memory-access protocol being satisfied at one of a rising edge and a falling edge of the core clock relative to a previous command in the command sequence; and ensuring, through the parallelizing, availability of the plurality of commands in the command sequence to a memory interface operating at the memory clock frequency at a command rate equal to the memory clock frequency.