Patent ID: 7707379

Claim:
A method of controlling computer-readable memory that includes a plurality of memory locations, comprising the actions of: a. determining a usage frequency of a plurality of data units; b. upon each occurrence of a predefined event, determining a memory latency for each of the plurality of memory locations, wherein the determining memory latency action comprises the actions of: i. staffing a data timer; ii. storing a first data unit in a selected memory location; iii. reading a stored data unit from the selected memory location; iv. stopping the data timer when the stored data unit meets a preselected criterion, the data timer holding a memory latency value corresponding to the selected memory location; and v. writing the memory latency value into a selected location of a memory table corresponding to the selected memory location; and c. after the predefined event, storing a data unit with a high usage frequency in a memory location with a low latency.