Patent ID: 8516163

Claim:
A serial buffer comprising: a plurality of queues configured to store data packets received from a host; a direct memory access (DMA) engine coupled to receive data packets read from the queues; a plurality of DMA register sets, wherein each of the DMA register sets is configured to store parameters that define a corresponding DMA channel of the DMA engine, and wherein each of the DMA register sets include a start address register configured to store a start address and a stop address register configured to store a stop address, wherein the start address and the stop address define a unique buffer within a system memory, and wherein each of the DMA register sets include a wrap/stop register configured to store a wrap_stop identifier that indicates whether or not the buffer is accessed in a wrap-around manner; and circuitry for selecting one of the DMA register sets to configure the DMA engine, thereby enabling the DMA engine to transfer the received data packets to the system memory using the corresponding DMA channel.