Patent ID: 7424689

Claim:
A method of optimizing a design, the method comprising: receiving a design including a base clock signal; identifying a component of the design having a data input connected with a data signal and clock input connected with a gated clock signal, wherein the gated clock signal is a product of a function of at least the base clock signal and an input signal; identifying a portion of the design performing the function on the base clock signal to produce the gated clock signal; creating a Boolean expression equivalent to the portion of the design, wherein the Boolean expression includes a first input variable corresponding with the base clock signal and a second input variable corresponding with the input signal; reducing the Boolean expression to cofactors of the first input variable; evaluating the cofactors for values of a set of input values of at least the second input variable; and in response to a determination that one of the cofactors has a constant value for the set of input values, modifying the design by connecting the clock input of the component with the base clock signal and connecting the data input of the component with a modified data signal, wherein the modified data signal is provided by input logic performing a second function of the data signal and a second input signal.