Patent ID: 7522691

Claim:
A phase-locked circuit, comprising a complex signal processor, and a feedback portion, wherein: said complex signal processor receives as an input a first complex signal composed of a real part component and an imaginary part component, phases of which are mutually perpendicular at a first frequency; generates a second complex signal composed of a first signal component and a second signal component and having a second frequency in accordance with a feedback control signal input from said feedback portion, wherein the second frequency is set to have a predetermined polarity; and generates a signal in accordance with a declination of a third complex signal obtained by multiplying said first complex signal with said second complex signal and outputs to said feedback portion; said feedback portion generates said feedback control signal in accordance with a signal input from said complex signal processor, so that said declination converges to a constant value; and said complex signal processor synchronizes a phase of said second complex signal with said first complex signal and outputs; wherein said complex signal processor comprises: a complex signal generation portion for respectively generating said first signal component and said second signal component having a frequency in accordance with said feedback control signal, wherein phases are mutually perpendicular, a first calculation portion for multiplying said first signal component generated by said complex signal generation portion with the real part component of said first complex signal, a second calculation portion for multiplying said second signal component generated by said complex signal generation portion with the imaginary part component of said first complex signal, and a third calculation portion for calculating a sum or difference of multiplication results of said first calculation portion and said second calculation portion; wherein said complex signal generation portion comprises: a signal generation portion for generating a signal having a frequency in accordance with said feedback control signal, cascade-connected m-stage (m indicates positive even numbers) flip-flop, wherein each successively transmits an input signal to a subsequent stage in synchronization with a signal generated by said signal generation portion, and an inverter for performing logical inversion on an output signal of a final stage of said cascade-connected flip-flop and inputting to the initial stage; wherein two signals, phases of which are different by ¼ cycle, among signals input to or output from said cascade-connected flip-flop are output as said first signal component and said second signal component.