Patent ID: 6845429

Claim:
A multi-port cache memory, comprising: first to K-th N-port tag memories each comprising M-number of one-port cell blocks and of an N-port decoder for decoding N cache line indices, each of the cache line indices having 1 bit or more, supplied to the first to K-th tag memories, each of K and M being an integer of 1 or more and N being an integer of more than 1; first to K-th N-port data memories each comprising M-number of one-port cell blocks and an N-port decoder for decoding the N cache line indices, each of the cache line indices having 1 bit or more, and N cache line offsets supplied to the first to K-th data memories, each of the cache line offsets having 0 bits or more; and a conflict management circuit for managing write and read conflicts in the first to K-th N-port tag memories and the first to K-th N-port data memories.