Patent ID: 7876633

Claim:
An integrated circuit, comprising: a plurality of memory circuits including memory cell arrays different in size; a BIST (built in self test) circuit which includes a cell sequential transition test processor executing a cell transition test in which a test target memory cell is caused to sequentially transition in a row or column direction, the BIST circuit outputting a test cell address specifying a location of the memory cell targeted for the cell sequential transition test, a transition direction specification signal specifying a transition direction in the memory cells in the cell sequential transition test, and an active signal determining an execution/non-execution of the cell sequential transition test for the test cell address; and a plurality of adjustment circuits provided for the respective memory circuits, each adjustment circuit performing either replacement of the test cell address outputted from the BIST circuit with an address in an area inside the corresponding memory cell array, or conversion of the active signal into a signal indicating non-execution, when the test cell address corresponds to a cell in a virtual cell array being in an area outside the memory cell array.