Patent ID: 8074051

Claim:
A multithreaded processor comprising: a plurality of hardware thread units; an instruction decoder coupled to the thread units for decoding instructions received therefrom; and a plurality of execution units for executing all of the decoded instructions; wherein the multithreaded processor is configured for controlling an instruction issuance sequence for a plurality of threads associated with respective ones of the hardware thread units; wherein on a given processor clock cycle only a designated one of the threads is permitted to issue one or more instructions, the designated thread that is permitted to issue instructions varying over a plurality of clock cycles in accordance with the instruction issuance sequence; wherein the instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent variable length instruction pipelines; wherein the pipelined instructions comprise at least a vector multiplication and reduction instruction that includes an instruction decode stage, a vector register file read stage, at least two multiply stages, at least two add stages, an accumulator read stage, a plurality of reduction stages, and an accumulator writeback stage; wherein the vector multiplication and reduction instruction is pipelined using a number of stages which is greater than a total number of threads of the processor; and wherein vector multiplication and reduction instruction pipelines are shifted relative to one another to permit computation cycles which are longer than issue cycles without forwarding logic to allow lengthening of execution phases without causing bubbles in the pipelines.