Patent ID: 8195846

Claim:
A direct memory access controller (DMAC), comprising: a timer operating during a predetermined period from the moment a bus control right is obtained; a dedicated and a nondedicated DMA request determining unit for determining whether or not an operation of the timer is completed and whether or not a direct memory access (DMA) request signal of an external module is received, wherein the dedicated DMA request determining unit for estimating a time when the DMA request signal is generated by using a time-out signal of the timer to reduce a time taken to respond to the DMA request signal relative to a response time of the nondedicated DMA request determining unit; a bus control right obtaining unit for requesting and obtaining the bus control right based on whether or not the DMA operation is completed and whether or not the DMA request signal is received; and a data transmitting unit for transmitting data through a DMA scheme.