Patent ID: 8138055

Claim:
A method of making a semiconductor device, the method comprising: forming a first gate stack on a substrate at a pFET region, wherein the first gate stack comprises a first gate electrode material overlying a gate dielectric material, wherein the first gate electrode material comprises SiGe; forming a second gate stack on the substrate at an nFET region; forming spacer structures and implanting ions into source/drain regions of the substrate at the nFET and pFET regions; etching the source/drain regions of the substrate at the pFET region and the first gate electrode material of the first gate stack at the pFET region, wherein source/drain recesses are formed by etching the source/drain regions of the substrate at the pFET region, and wherein at least part of the first gate electrode material is removed by the etching from the first gate stack to form a gate electrode recess; and forming a SiGe material in the source/drain recesses and in the gate electrode recess at the pFET region; forming a tensile-stress-inducing mask layer over the substrate, the spacer structures, and the gate stacks; and removing the tensile-stress-inducing mask layer from the pFET region, while retaining the tensile-stress-inducing mask layer over the nFET region using a first patterned mask layer, wherein the tensile-stress-inducing mask layer is a laminate stack comprising a first tensile-stress-inducing mask layer formed on an etch stop layer, and wherein during the removing of the tensile-stress-inducing mask layer from the pFET region, the first tensile-stress-inducing mask layer has a greater etch rate than the etch stop layer.