Patent ID: 7700450

Claim:
A method for forming MOS transistor comprising steps of: providing a substrate having at least a gate structure thereon; performing a pre-amorphization (PAI) process to form amorphized regions in the substrate adjacent to two sides of the gate structure; performing a pocket implantation process to form pocket-doped regions between the amorphized regions; performing a co-implantation process to implant a co-implant dopant into the amorphized regions; performing a first ion implantation process to implant a first dopant into the amorphized regions; performing a first rapid thermal annealing (RTA) process to activate the first dopant and the co-implant dopant, regrow the amorphized regions to a substantially crystalline form, and form lightly doped drains (LDDs) in the amorphized regions; forming spacers on sidewalls of the gate structure; and forming a source/drain in the substrate adjacent to the spacers.