Patent ID: 7221207

Claim:
A semiconductor apparatus, comprising: first, second, and third switch transistor circuits; first second and third gate bias terminals, a gate of the first switch transistor circuit connected by a resistor to the first gate bias terminal, a gate of the second switch transistor circuit connected by a resistor to the second gate bias terminal, a gate of the third switch transistor circuit connected by a resistor to the third gate bias terminal; an input terminal connected in parallel to a source of each of the first, second and third switch transistor circuits; first, second, third, fourth, fifth, and sixth shunt transistor circuits; a first output terminal connected to a drain of the first switch transistor circuit, the first output terminal connected to a drain of the first and second shunt transistor circuits, a source of each of the first and second shunt transistor circuits connected in parallel by a capacitor to ground, a gate of the first shunt transistor circuit connected by a resistor to the third gate bias terminal, a gate of the second shunt transistor circuit connected by a resistor to the second gate bias terminal; a second output terminal connected to a drain of the second switch transistor circuit, the second output terminal connected to a drain of the third and fourth shunt transistor circuits, a source of each of the third and fourth shunt transistor circuits connected by a capacitor to ground, a gate of the third shunt transistor circuit connected by a resistor to the first gate bias terminal, a gate of the fourth shunt transistor circuit connected by a resistor to the third gate bias terminal; and a third output terminal connected to a drain of the third switch transistor circuit, the third output terminal connected to a drain of the fifth and sixth shunt transistor circuits, a source of each of the fifth and sixth shunt transistor circuits connected by a capacitor to ground, a gate of the fifth shunt transistor circuit connected by a resistor to the first gate bias terminal, a gate of the sixth shunt transistor circuit connected by a resistor to the second gate bias terminal.