Patent ID: 7500306

Claim:
A method of forming an electrical structure, comprising: forming a complex power-signal (CPS) substructure selected from the group consisting of a single CPS substructure, a double CPS substructure, and a L-CPS substructure, wherein L is greater than 2; after said forming the CPS substructure, testing an electrical performance of the CPS substructure to determine whether the CPS substructure satisfies electrical performance acceptance requirements, wherein the testing includes testing for at least one of electrical integrity and electrical signal delay, and wherein the testing for electrical integrity includes testing for at least one of an electrical short, an electrical open, and an erroneous impedance; and after said testing, ascertaining from a result of said testing that the CPS substructure satisfies the electrical performance acceptance requirements; after said ascertaining, forming a dielectric-metallic (DM) laminate on and in direct mechanical contact with a first external surface of the CPS substructure including forming a first multilevel conductive via through the DM laminate, wherein the DM laminate consists of an alternating sequence of an equal number N of dielectric layers and metallic layers, wherein N is equal to 2, wherein the first multilevel conductive via is electrically coupled to a first metal layer of the CPS substructure, and wherein said forming the DM laminate on and in direct mechanical contact with the first external surface of the CPS substructure comprises: forming a first dielectric layer of the N dielectric layers on and in direct mechanical contact with the first external surface of the CPS substructure; after said forming the first dielectric layer of the N dielectric layers on and in direct mechanical contact with the first external surface of the CPS substructure, forming a first metallic layer of the N metallic layers on and in direct mechanical contact with the first dielectric layer of the N dielectric layers; after said forming the first metallic layer of the N metallic layers on and in direct mechanical contact with the first dielectric layer of the N dielectric layers, forming a second dielectric layer of the N dielectric layers on and in direct mechanical contact with the first metallic layer of the N metallic layers; after said forming the second dielectric layer of the N dielectric layers on and in direct mechanical contact with the first metallic layer of the N metallic layers, forming a second metallic layer of the N metallic layers on and in direct mechanical contact with the second dielectric layer of the N dielectric layers, wherein the first metallic layer of the N metallic layers and the second metallic layer of the N metallic layers each include a power plane and do not incude a signal plane.