Patent ID: 8043957

Claim:
A method for manufacturing a semiconductor device including a multilayer wiring comprising: a semiconductor substrate; an insulating film formed on the semiconductor substrate such, at least one part of the insulating film being formed of a first insulating film; a wiring groove and a via hole formed in the insulating film; a wire and a connecting plug formed from a metal respectively filled in the wiring groove and the via hole; and a modified layer formed on an interface between the first insulating film and the metal, wherein the first insulating film is at least one layer insulating film including a siloxane structure containing silicon, oxygen and carbon, the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms, and the modified layer contains a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film, the method comprising: forming the first insulating film containing the siloxane structure; forming a hard mask film on the first insulating film; applying a photoresist to the hard mask film and then patterning a groove thereon; forming a mask pattern through forming a groove in the hard mask film by a dry etching using the photoresist as a mask; removing the photoresist by an oxygen asking; forming the wiring groove and the via hole in the first insulating film by a dry etching using the mask pattern as a mask; forming the modified layer by performing modification treatment onto side faces of the wiring groove and the via hole in the first insulating film; and forming the wire and the connecting plug respectively by filling the wiring groove and the via hole with the metal.