Patent ID: 7884463

Claim:
A wiring board for a semiconductor device in which a semiconductor element with electrode terminals formed on the entire face of one side of the wiring board, wherein on a semiconductor element loading face formed on the one side of the wiring board and having an area wider than an area of the semiconductor element, the wiring board comprising: wiring patterns which are drawn out from loading pads formed in the vicinity of the edge of the semiconductor element in cue loading pads formed so as to correspond to the electrode terminals formed on the semiconductor element, respectively and connected to via pads formed in the vicinity of the edge of the semiconductor element loading face; area pads constructed of the loading pads corresponding to the electrode terminals formed in a central region of the semiconductor element and a vicinity of the central region, which are electrically connected to external connecting terminal pads formed in a lattice pattern in a central region on the other side of the wiring board and a vicinity of the central region so as to correspond to the area pads, respectively through area pad vias encircled by the external connecting terminal pads formed in a lattice pattern and passing through the wiring board and the wiring patterns; and a plurality of the loading pads constituting the area pads commonly use one of the area pad vias.