Patent ID: 7381637

Claim:
A method of forming an interconnect in a semiconductor substrate, said method comprising: forming an insulator stack above a substrate; depositing a hardmask over said insulator stack; patterning troughs into said hardmask; depositing a photoresist layer over said troughs; patterning vias in said photoresist layer such that said vias are positioned within said troughs; etching said vias through said insulator stack, wherein said vias comprise a top portion, a bottom portion, sidewalls and a bottom surface; forming a first conductive layer only in said bottom portion of said vias adjacent said sidewalls and said bottom surface; after said forming of said first conductive layer in said bottom portion, etching said troughs into said insulator stack; applying a second conductive layer over said troughs and said vias such that said second conductive layer is separated from said bottom surface by said first conductive layer; depositing said first conductive layer such that said first conductive layer lines said top portion and said bottom portion of said vias; depositing an anti reflective coating on said first conductive layer; recessing said anti reflective coating such that said anti reflective coating is positioned only within said bottom portion of said vias; and removing exposed portions of said first conductive layer.