Patent ID: 7678636

Claim:
A method of forming a semiconductor structure, the method comprising: providing a semiconductor substrate comprising a first region and a second region; forming a first p-type metal-oxide-semiconductor (PMOS) device in the first region, wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration; forming a stress memorization layer over the first PMOS device in the first region; reducing the stress memorization layer over the first gate electrode and a first source/drain region of the first PMOS device in the first region, at least a portion of the stress memorization layer remaining over the first PMOS device; performing an annealing after the step of reducing the stress memorization layer in the first region; removing the stress memorization layer; and forming a second PMOS device in the second region, wherein the first region has a first active gate electrode pattern density and the second region has a second active gate electrode pattern density, and wherein the first active gate electrode pattern density is less than the second active gate electrode pattern density.