Patent ID: 8514004

Claim:
A clock management unit comprising: a first flip-flop; a second flip-flop; a clock gate; and an AND gate, wherein the first flip-flop comprises a first D terminal configured to receive a reset signal provided to an external circuit for resetting the external circuit, a first clock terminal configured to receive a clock signal, and a first output terminal, the second flip-flop comprises a second D terminal connected to the first output terminal of the first flip-flop, a second clock terminal configured to receive the clock signal, and a second output terminal, the clock gate comprises an enable terminal connected to the second output terminal of the second flip-flop, a third clock terminal configured to receive the clock signal, and an external clock terminal connected to the external circuit, the clock gate being configured to provide an external clock signal to the external circuit through the external clock terminal according to an output signal of the second output terminal of the second flip-flop, the AND gate receives the reset signal and an enable signal and provides the reset signal to the first D terminal of the first flip-flop according to the enable signal, the enable signal is provided to the external circuit so as to operate the external circuit, and the external clock signal does not exhibit an edge transition for at least two periods of the clock signal after the reset signal is activated to reset the external circuit.