Patent ID: 7280410

Claim:
A system for controlling the operation of a plurality of data bus terminals in a memory device, the system comprising: a mode register programmable to select either a first mode or a second mode of operation for the data bus terminals, the mode register being operable to output a mode control signal corresponding to the selected mode; a timing circuit coupled to receive the mode control signal from the mode register, the timing circuit receiving a clock signal and generating timing signals corresponding to the selected one of the first and second modes in synchronism with the clock signal; a data timing circuit coupled to the timing circuit, the data timing circuit receiving read data signals and generating timed data signals corresponding to the read data signals; data bus terminal drive logic coupled to the data timing circuit, the data bus terminal drive logic generating output signals responsive to the timed data signals; and pull-up and pull-down circuitry coupled to the data bus terminal drive logic, the pull-up and pull-down circuitry being operable to drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected.