Patent ID: 8629548

Claim:
A clock network architecture for a structured application specific integrated circuit (Structured ASIC), comprising: a core comprising memory cells and logic cells; at least one metal layer in the Structured ASIC; the memory cells and the logic cells forming columns in the core; a plurality of vias forming conductive paths for clock signals from the metal layer, the vias being substantially perpendicular to the plane containing the core; the plurality of vias defining at least one vertical via channel bus line in the core, substantially parallel to and spaced in-between the memory cells and logic cells forming columns in the core; clock signal traces that form conductive paths between the vias and the logic cells, the via bus line operatively connected to at least one of the logic cells through the clock signal traces, the clock signal traces extending along at least one horizontal row substantially perpendicular to the vertical via channel bus line; and, the vertical via channel bus line and horizontal row of traces forming a clock mesh; wherein a clock may be connected to the clock mesh for providing a clock signal to the logic cells of the Structured ASIC.