Patent ID: 8218369

Claim:
A non-volatile memory low voltage and high speed erasure method, said non-volatile memory comprising: a stacked gate structure disposed on a P-type semiconductor substrate, a source and a drain disposed on two sides of said stacked gate structure and in said P-type semiconductor substrate, said stacked gate structure includes at least a floating gate and a control gate disposed above said floating gate, said non-volatile memory erasure method includes following steps of: applying a substrate voltage V sub , a source voltage V s , a drain voltage V d , and a control gate voltage V c on said P-type semiconductor substrate, said source, said drain, and said control gate, when V sub is a ground voltage (=0), while satisfying following conditions: a. V d >5V, V s is close to or equal to 0; and b. V d >V c ≧0, V c decrementing with erasure time; and when V sub is a negative voltage, while satisfying following conditions: a. V s is close to or equal to V sub ; and b. V d >V c , V c decrementing with erasure time.