Patent ID: 7586159

Claim:
A semiconductor device comprising: a first transistor comprising a first substrate region, a first gate electrode, and a first gate dielectric located between the first substrate region and the first gate electrode; and a second transistor comprising a second substrate region, a second gate electrode, and a second gate dielectric located between the second substrate region and the second gate electrode; wherein the first gate dielectric comprises a first high-k layer having a dielectric constant of 8 or more, wherein the second gate dielectric comprises a second high-k layer having a dielectric constant of 8 or more, and wherein the second high-k layer has a different material composition than the first high-k layer, wherein the first transistor is an NMOS device and the second transistor is a PMOS device, wherein the first gate dielectric comprises a third high-k layer having a dielectric constant of 8 or more, wherein the first high-k layer is a hafnium oxide layer, and wherein the second and third high-k layers are aluminum oxide layers, and wherein the second and third high-k layers are coplanar.