Patent ID: 6897132

Claim:
A method of forming a gate region of a semiconductor device comprising the steps of: (a) forming a layer of semiconductor doped with Sn; (b) forming a region of SiO 2 on said semiconductor layer, the region of SiO 2 corresponding to said gate region; (c) annealing at least the semiconductor layer and the region of SiO 2 at a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of SiO 2 and to thereby form a region in said SiO 2 layer having a reduced concentration of Sn dopant, the annealing step occurring at a temperature sufficiently low and for a period of time sufficiently short to inhibit significant intermixing between the region of SiO 2 and the semiconductor layer; (d) removing the region of SiO 2 after the annealing step is performed; and (e) forming a gate electrode on said semiconductor layer.