Patent ID: 8564024

Claim:
A semiconductor device comprising: a first trench extending into at least a portion of an epitaxial layer of a semiconductor region, the first trench having an end, and a sidewall lined with a dielectric layer, the first trench having a shield electrode disposed in the first trench and having a gate electrode disposed in the first trench, the gate electrode being electrically isolated from the shield electrode of the first trench; a second trench aligned parallel to the first trench and having an end, the second trench having a gate electrode disposed in the second trench, the gate electrode of the second trench having a width narrower than a width of the gate electrode of the first trench; a perimeter trench extending into the semiconductor region and having at least a portion aligned perpendicular to the first trench and the second trench, the perimeter trench having a sidewall lined with a dielectric layer and an electrode disposed in the perimeter trench; and a gap region of the epitaxial layer defining a mesa aligned parallel to the perimeter trench, the gap region being disposed between the portion of the perimeter trench and the end of the first trench and disposed between the portion of the perimeter trench and the end of the second trench.