Patent ID: 7374953

Claim:
A method of forming a FRAM, comprising: providing a semiconductor substrate; forming an interlayer insulating layer on the substrate; forming a diffusion preventive layer on the interlayer insulating layer; forming two node contact holes in the diffusion preventive layer and the interlayer insulating layer; forming node conductive layer patterns that protrude upward from the diffusion preventive layer and are aligned with the node contact holes, respectively; and forming a lower electrode layer that covers the node conductive layer patterns on the diffusion preventive layer; and etching a surface of the lower electrode layer so as to expose the diffusion preventive layer and to separate the lower electrode layer, thereby forming lower electrodes respectively covering the node conductive layer patterns; wherein the lower electrode layer is formed to have different thicknesses on upper surfaces of the node conductive layer pattern and the diffusion preventive layer, and is further formed such that its thickness is gradually reduced along sidewalls of the node conductive layer patterns.