Patent ID: 8223561

Claim:
A method for programming a memory device having a plurality of memory cells logically arranged in rows and in columns, the method comprising: selecting a particular row of memory cells for programming wherein the particular row of memory cells is arranged into three or more mutually exclusive subsets of memory cells without regard to an intended pattern of data states to be programmed into the particular row of memory cells; if it is desired to program a particular subset of memory cells of the particular row, selecting at least one memory cell of the particular subset of memory cells of the particular row for programming while inhibiting each remaining memory cell of the particular subset of memory cells and each remaining subset of memory cells of the particular row from programming and performing a program operation on the particular row of memory cells; wherein each memory cell of each subset of memory cells is separated along the particular row of memory cells by a memory cell of each other subset of memory cells; wherein a first subset of the remaining subsets of memory cells are coupled to a first group of data lines biased to a first inhibit voltage and a second subset of the remaining subsets of memory cells are coupled to a second group of data lines biased to a second inhibit voltage; and wherein the first inhibit voltage and the second inhibit voltage are different.