Patent ID: 7640468

Claim:
An apparatus comprising: an integrated circuit (“IC”) having one or more input/output (“I/O”) pads, each said I/O pad comprising a data output driver having an output impedance, and configured to launch onto a transmission element connected to the I/O pad a test signal having a signal level transition; a data output register configured to receive the test signal having the signal level transition and to provide the test signal to the data output driver in response to a clock signal; a programmable reference generator configured to provide a programmed reference voltage; a receiver configured to receive from the transmission element a reflection of the test signal having the signal level transition and to compare the received reflection to the programmed reference voltage and in response thereto to output a received reflection signal, a programmable delay element configured to receive said clock signal and to output a delayed clock signal; data capture select logic for selecting between the received reflection signal and a scan input signal received from another one of the I/O pads of the IC, and outputting a multiplexed output signal; and a data capture register configured to receive the multiplexed output signal and to output a scan output signal in response to the delayed clock signal.