Patent ID: 8266340

Claim:
A DMA controller comprising: a peripheral device read unit configured to read states of a plurality of peripheral devices to acquire the states of the plurality of peripheral devices; a state comparator; a transfer unit configured to execute a DMA transfer; and a register including contents to operate the peripheral device read unit, the state comparator, and the transfer unit to execute DMA transfer; a peripheral device write unit configured to write data in each register of the peripheral devices according to the contents in the register when the DMA transfer is executed or the DMA transfer is finished for performing control of the peripheral devices or notification of information to the peripheral devices; and an interrupt select unit, wherein, the interrupt select unit is configured to receive a plurality of interrupt signals and to select one interrupt signal among the plurality of interrupt signals, wherein the selected interrupt signal determines whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations, wherein, at the timing when the operations are to be executed by the peripheral device read unit, the state comparator, and the transfer unit, the peripheral device read unit reads the states of the plurality of peripheral devices according to the contents set in the register, and the state comparator determines whether to start the DMA transfer by the transfer unit according to the states of the plurality of peripheral devices and a start condition of the DMA transfer set in the register, wherein, when the state comparator determines to start the DMA transfer, the transfer unit executes data transfer between the peripheral devices.