Patent ID: 7689641

Claim:
A computer implemented method for performing a multiply high with round and shift operation, the method comprising: in response to a single instruction identifying a first operand at a first register having a first set of L data elements and a second operand at a second register having a set of L data elements, a microprocessor executing the single instruction to perform, multiplying together L pairs of data elements to generate a set of L products, wherein each of said L pairs includes a first data element from said first set of L data element and a second data element from a corresponding data element position of said second set of L data elements; shifting each of said L products to the right by fourteen bits to generate L shifted values to be 18 bits wide; rounding each of said L shifted values to generate L rounded values by adding a ‘1’ to a least significant bit position each of said L shifted values; scaling each of said L rounded values right by one bit to generate a set of L scaled values; truncating each of said L scaled values to generate L truncated values by selecting sixteen least significant bits from each of said L scaled values to obtain said L truncated values; and storing said L truncated values at a destination register indicated by said single instruction as a final result of the single instruction, wherein each truncated value is to be stored at a data element position corresponding to its pair of data elements.