Patent ID: 7931818

Claim:
A process of an embedded circuit structure comprising: laminating two complex metal layers, two prepregs and a supporting board, wherein the supporting board is located between the prepregs, the prepregs are located between the complex metal layers and the supporting board, each of the complex metal layers has an inner metal layer and an outer metal layer stacked on the inner metal layer, the roughness of the first outer surface of the inner metal layer away from the corresponding outer metal layer is less than the roughness of the second outer surface of the corresponding outer metal layer away from the corresponding inner metal layer, and the second outer surfaces of the outer metal layers after laminating are exposed outwards; forming two patterned photoresist layers on the second outer surfaces of the outer metal layers respectively; forming a metal material on portions of the second outer surfaces of the outer metal layers not covered by the patterned photoresist layers to form two patterned circuit layers; removing the patterned photoresist layers to form a laminating structure; laminating another laminating structure same as the laminating structure with the laminating structure through a dielectric layer, wherein the patterned circuit layers near to the dielectric layer are embedded in the dielectric layer, and removing portions of the laminating structures and remaining the patterned circuit layers embedded in the dielectric layer and the outer metal layers connecting the patterned circuit layers.