Patent ID: 7776744

Claim:
A method for forming an integrated circuit, comprising: defining a pattern in a selectively definable layer over a substrate; transferring the pattern from the selectively definable layer to an underlying layer of temporary material to form a plurality of temporary placeholders in the layer of temporary material across a region over the substrate; providing a cap layer on a top horizontal surface of the temporary placeholders, wherein the cap layer inhibits reactions on the top horizontal surface and exposes sidewalls of the temporary placeholders; blanket depositing a layer comprising a solid phase reactant over the cap layer and the temporary placeholders; converting some of the temporary material into an other material to form a plurality of spacers underneath the cap layer, the spacers forming a plurality of mask features, wherein converting some of the temporary material comprises selectively reacting sidewalls of the temporary placeholders with the solid phase reactant, wherein at least part of the spacers are formed directly under the cap layer, the cap layer and the spacers formed of different materials; selectively removing the cap layer relative to the spacers; selectively removing unconverted temporary material between the spacers after removing the cap layer; and subsequently etching the substrate through a mask pattern defined by the plurality of spacers.