Patent ID: 7452822

Claim:
A method for forming a dual damascene structure in a semiconductor device manufacturing process comprising the steps of: providing a process wafer comprising a via opening extending through a dielectric insulating layer thickness; forming a resinous polymer plug filling material layer on the process water process surface to include filling the via opening to form a via plug; diffusing an acid into the plug filling material layer; heating the plug filling material layer to react the acid with the plug filling material layer to form a soluble thickness portion of the plug filling material layer; removing the soluble thickness portion in a solvent to leave a remaining thickness portion of the plug filling material layer, said plug filling material layer not subjected to CMP; forming a resist layer over the remaining thickness portion of the plug filling material layer; photolithographically patterning the resist layer to form a trench etching mask; and, etching a trench to form a dual damascene structure.