Patent ID: 8829511

Claim:
A hybrid thin film transistor, comprising: a first thin film transistor, comprising: a first gate, a first source and a first drain; and a first semiconductor layer, disposed between the first gate, the first source and the first drain, wherein the first semiconductor layer includes a crystallized silicon layer and a non-doped silicon layer disposed on the crystallized silicon layer, the crystallized silicon layer comprises a poly-silicon material or a microcrystalline silicon material, and the non-doped silicon layer comprises a microcrystalline silicon material or an amorphous silicon material; a second thin film transistor, comprising: a second gate, a second source and a second drain; and a second semiconductor layer, disposed between the second gate, the second source and the second drain, wherein the second semiconductor layer includes a metal oxide semiconductor layer; and an insulating layer, disposed on the first gate and the second gate, wherein both of the second source and the second drain are disposed between the metal oxide semiconductor layer and the insulating layer, and the first source, the first drain, the second source and the second drain are directly in contact with the insulating layer.