Patent ID: 7163852

Claim:
A method for manufacturing a semiconductor device, comprising the steps of: forming a laminate comprising a lower first conductive layer and an upper second conductive layer over a semiconductor layer with a gate insulating film interposed therebetween; forming a mask pattern over the laminate; using a condition that has a fast etching rate of the mask pattern and etching the second conductive layer and the first conductive layer to form a tapered first conductive layer pattern; selectively etching the second conductive layer in the first conductive layer pattern in accordance with the mask pattern left over the first conductive layer pattern to form a second conductive layer pattern; and forming a lightly doped drain region in a region of the semiconductor film overlapping with the first conductive layer in the second conductive layer pattern with the second conductive layer in the second conductive layer pattern as a mask for shielding ions accelerated by an electric field.