Patent ID: 8064249

Claim:
A static random access memory (SRAM) device, the device comprising: first and second switching devices connected to bit lines; and third and fourth switching devices respectively connected to two load resistors, the third and fourth switching devices being connected in a latch structure, and each of the first, second, third, and fourth switching devices comprising: a source electrode and a drain electrode disposed on an insulating substrate and spaced apart from each other; a first nanowire vertically grown on the source electrode, and to which a V 1 voltage is applied; a second nanowire vertically grown on the drain electrode, and to which a V 2 voltage having an opposite polarity to that of the V 1 voltage; and a gate electrode spaced apart from the second nanowire, partially surrounding the second nanowire and having an opening that faces the first nanowire to avoid disturbing a mutual switching operation of the first nanowire and the second nanowire, and to which a V 3 voltage having the same polarity as that of the V 2 voltage is applied, by an action between an electrostatic force between both of the first and second nanowires and the gate electrode and an elastic restoration force of the second nanowire, the first and second nanowires either contact or disconnect from each other so that the switching device is either switched on or switched off.