Patent ID: 7227370

Claim:
A semiconductor inspection apparatus comprising: (a) a support member supporting a semiconductor wafer having a first principal surface and a second principal surface which is on the other side of the first principal surface, a plurality of semiconductor chips formed on said first principal surface, and a plurality of electrodes disposed on each of said plurality of semiconductor chips; (b) a probe sheet having a third principal surface facing said first principal surface of said semiconductor wafer with a desired space provided therebetween, a fourth principal surface which is on the other side of said third principal surface, a plurality of contact terminals disposed on said third principal surface, a plurality of wirings respectively led from said plurality of contact terminals, and a plurality of lead electrodes led to said fourth principal surface via said plurality of wirings; (c) a tester connected to said plurality of lead electrodes of said probe sheet and electrically inspecting said plurality of semiconductor chips of said semiconductor wafer at one time; and (d) pressure reducing means for reducing the pressure of said desired space in said inspection so that said semiconductor wafer is mainly deformed to bring the plurality of electrodes of the plurality of semiconductor chips of said semiconductor wafer into contact with said plurality of contact terminals of said probe sheet.