Patent ID: 7733985

Claim:
A phase-locked loop circuit comprising: a phase and frequency detector receiving a reference signal and an output signal of the phase-locked loop circuit for generating a detected signal representing a difference between the reference signal and the output signal in frequency or phase; a digital charge pump coupled to the phase and frequency detector for generating a charge control signal in response to the detected signal; a mixed mode loop filter coupled to the digital charge pump for filtering the charge control signal and generating an oscillation control signal, the mixed mode loop filter further comprises; a digital adder coupled to the digital charge pump for digitally processing the charge control signal; a digital-to-analog converter coupled to the digital adder, the digital-to-analog converter having a low resolution from 1 bit to 5 bits; and a voltage controlled oscillator coupled to the mixed mode loop filter for generating the output signal of the phase-locked loop circuit by adjusting its oscillation frequency in response to the oscillation control signal, wherein the mixed mode loop filter has both digital and analog characteristics in carrying out filtering the charge control signal, thereby reducing a layout area for the same to be implemented on a semiconductor substrate, and wherein the digital adder further comprises: a first amplifier coupled to the digital charge pump for generating a first signal equal to the charge control signal multiplied by a first gain; a second amplifier coupled to the digital charge pump for generating a second signal equal to the charge control signal multiplied by a second gain; a first adder coupled to the first and second amplifiers for summing the first and second signals to generate a third signal; a multiplier coupled to the second amplifier for generating a fourth signal equal to the second signal multiplied by a predetermined factor; and a second adder coupled to the first adder and the multiplier for generating an output signal of the digital adder equal to the third minus the fourth signal.