Patent ID: 7389427

Claim:
A platform comprising: a system memory to store output data in an isolated output area and a non-isolated area; a memory controller hub (MCH) coupled to the system memory; and a processor coupled to the MCH to generate a signal to the MCH, the signal indicating whether the output data is to be stored in the isolated output area or the non-isolated area, the signal generated by the processor to further cause the MCH, in response to an indication of the signal that the output data is to be stored in the isolated output area of the system memory, to receive a bus transaction indicating an isolated transaction from a graphics device to enable access to the output data stored in the isolated output area, and to transfer the output data to an isolated bit plane on the graphic device, the graphic device having the isolated bit plane for the output data from the isolated output area and a non-isolated bit plane for the output data from the non-isolated output area.