Patent ID: 8680923

Claim:
An output circuit comprising: a first transistor including a gate, a source, and a drain, wherein the gate of the first transistor is supplied with one of two input signals; a second transistor including a gate, a source, and a drain, wherein the gate of the second transistor is supplied with the other of the two input signals; a third transistor including a drain coupled to the drain of the first transistor, a gate coupled to the drain of the second transistor, and a source; a fourth transistor including a gate coupled to the drain of the first transistor, a drain coupled to the drain of the second transistor, and a source; a first constant current unit coupled to the source of the third transistor and the source of the fourth transistor; a differential pair including two transistors, the two transistors of the differential pair each including a gate, a source, and a drain, wherein the gate of one of the two transistors of the differential pair is coupled to the drain of the first transistor, and the gate of the other of the two transistors of the differential pair is coupled to the drain of the second transistor; and a second constant current unit coupled to the sources of the two transistors of the differential pair, wherein two output signals are output from two nodes respectively corresponding to the drains of the two transistors of the differential pair.