Patent ID: 8750018

Claim:
A resistive type memory sense amplifier circuit, comprising: a first differential output terminal configured to output a first output signal; a second differential output terminal configured to output a second output signal opposite the first output signal; a first input terminal coupled to a bit line associated with a resistive type memory cell; a second input terminal coupled to a reference line associated with a reference memory cell; a first pre-charge transistor coupled to a power supply and to the first differential output terminal, the first pre-charge transistor being configured to pre-charge the bit line associated with the memory cell; a second pre-charge transistor coupled to the power supply and to the second differential output terminal, the second pre-charge transistor being configured to pre-charge the reference line associated with the reference memory cell; a first current modulating transistor coupled directly to the first differential output terminal and to the first pre-charge transistor, the first current modulating transistor being configured to operate in a saturation region mode during at least an amplification stage of the sense amplifier circuit; and a second current modulating transistor coupled directly to the second differential output terminal and to the second pre-charge transistor, the second current modulating transistor being configured to operate in the saturation region mode during at least the amplification stage of the sense amplifier circuit.