Patent ID: 7817655

Claim:
A method for sizing first-in-first-out (FIFO) buffers for pipelining functions of a circuit, the method comprising: performing the functions of the circuit on an input data set, wherein the circuit includes respective FIFO buffers for buffering data elements between coupled pairs of functional blocks; while performing the functions of the circuit, for each FIFO buffer, counting a respective current number of elements added to the FIFO buffer since a previous element was removed from the FIFO buffer, comparing the respective current number to a respective saved number in response to removal of an element from the FIFO buffer, saving the respective current number as a new respective saved number in response to the respective current number being greater than the respective saved number, and resetting the respective current number after the comparing of the respective current number to the respective saved number; determining respective sizes for the FIFO buffers as a function of the respective saved numbers; and storing the respective sizes for the FIFO buffers in a computer-readable storage medium that provides non-transitory storage.