Patent ID: 7082556

Claim:
A system for detecting a bit processing error, including a first circuit, a second circuit, and comparison circuitry; the first circuit configured to generate a first sequence of bit groups by reference to a controlling pattern, the first circuit further configured to transmit said first sequence of bit groups to a first external device, said first external device configured to transmit a second sequence of bit groups to a second external device, said second sequence of bit groups derived by the first external device from the first sequence of bit groups; the second circuit configured to receive a third sequence of bit groups from the second external device, said third sequence of bit groups derived by the second external device from the second sequence of bit groups, said second circuit further configured to generate a subsequent bit group from a first group of bits in the third sequence of bit groups by reference to the controlling pattern; the comparison circuitry configured to receive the third sequence of bit groups from the second external device; and the comparison circuitry further configured to execute a comparison of the subsequent bit group to a second bit group in the third sequence of bit groups, said second bit group following the first bit group in said third sequence of bit groups, whereby an unsuccessful comparison is indicative of a bit processing error.