Patent ID: 7194517

Claim:
In a multi-node computer system partitioned into a sending domain and a receiving domain, the sending domain and the receiving domain each having a processor node, an I/O node, and a memory node communicatively coupled through an interconnect, a method for message passing between the sending domain and the receiving domain, comprising: receiving from a processor node, a write request to a memory-mapped input/output (MMIO) window in an address space of the sending domain, the request including an address; comparing a portion of the address with a value stored in a base register, wherein the value indicates where the MMIO window starts in the address space of the sending domain; and responsive to the portion of the address matching the value in the base register: decoding the receiving domain; combining a plurality of write requests; and responsive to the plurality of the write requests having a cache-line size, transmitting the cache-line size write request from the sending domain to the receiving domain.