Patent ID: 8279695

Claim:
A semiconductor memory device comprising: a plurality of memory blocks; and a local bus connected to said plurality of memory blocks and which is precharged to a first potential before a read operation and a write operation, wherein each of said plurality of memory blocks comprises: a memory cell array in which memory cells are arranged in a matrix form; a plurality of bit line pairs arranged in a column direction of said memory cell array; a plurality of switches respectively provided between said plurality of bit line pairs and said local bus and each of which is turned ON in response to a selection signal; a first control circuit configured to, in said read operation and said write operation, output said selection signal to a selected switch of said plurality of switches so as to electrically connect a selected bit line pair of said plurality of bit line pairs and said local bus; a dummy local bus which is precharged to said first potential before said read operation; and a second control circuit configured to, in said read operation, supply a second potential lower than said first potential to said dummy local bus in response to said selection signal, wherein in said read operation, said first control circuit stops outputting said selection signal when a potential of said dummy local bus is decreased from said first potential to a predetermined set potential that is between said first potential and said second potential.