Patent ID: 8325853

Claim:
A system for clock synthesis for data timing recovery in very short lock time, of the type providing a high frequency output clock that is N times faster than a given reference clock, comprising: a feedback loop structure including a clock generator for generating a high frequency output clock; a clock divider for dividing by a factor N the frequency of the high frequency output clock from the clock generator; a frequency measure block for measuring the divided frequency; a comparator for comparing the measured frequency with a reference clock thus evaluating a frequency error; the value of the frequency error being used by a frequency control block to generate a control word for the selection of an oscillation output frequency; and wherein said feedback loop converges to a stable configuration having the frequency error approximately equal to zero and wherein the convergence to said stable configuration is obtained in two consecutive cycles of the reference clock, wherein each clock cycle comprises one and only one comparison by the comparator.