Patent ID: 7797466

Claim:
A chipset for a data processing system which can be partitioned into a plurality of logical partitions so that memory resources and CPU resources are allocated respectively to each of said logical partitions and a respective operating system instance operates on each of said logical partitions, said chipset includes: an I/O interface providing a connection with a plurality of I/O devices respectively threaded into a plurality of I/O slots; an initialization unit for allocating a corresponding logical partition of said logical partitions to each of the I/O devices threaded into said I/O slots; an I/O control unit for converting a destination address of an inbound memory access transaction accepted from a first I/O device of the plurality of I/O devices via said I/O interface into a memory address area allocated to the corresponding logical partition that is allocated to said first I/O device, wherein said I/O control unit determines whether the converted destination address belongs to the memory address area allocated to the corresponding logical partition that is allocated to said first I/O device, wherein an error handler reports an address error if said I/O control unit determines that the converted destination address does not belong to the memory address area allocated to the corresponding logical partition that is allocated to said first I/O device, and wherein said I/O control unit provides an affirmative response to said first I/O device even if said I/O control unit determines that the converted destination address does not belong to the memory address area allocated to the corresponding logical partition that is allocated to said first I/O device to allow said first I/O device to terminate said memory access transaction normally.