Patent ID: 8368439

Claim:
A phase locked loop (PLL) state detector employable with a PLL circuit including a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal, the PLL state detector comprising: a lock detector configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal, wherein the lock detector includes: a logic gate configured to generate phase difference data of which pulse width is controlled according to the phase difference between the reference clock signal and the output clock signal, a lock enable signal generator configured to determine that the system is in the lock state when the pulse width of the phase difference data is equal to or less than the first reference value and enable a lock enable signal, and an unlock enable signal generator configured to determine that the system is in the unlock state when the pulse width of the phase difference data is greater than the first reference value and enable an unlock enable signal.