Patent ID: 7493543

Claim:
A method for testing an integrated circuit, comprising: obtaining a first vector having first multiple bits; pipelining the first vector to provide a pipelined version of the first vector responsive to a clock signal; providing a bit of the first multiple bits of the pipelined version of the first vector to a first adjustable delay; providing a remainder of the first multiple bits of the pipelined version of the first vector to an input bus of an embedded circuit, the embedded circuit being provided as part of the integrated circuit; adjustably delaying the bit with the first adjustable delay to provide a delayed bit that is delayed with respect to the remainder of the first multiple bits; providing the delayed bit to the input bus of the embedded circuit; wherein the first multiple bits including the delayed bit are provided to the input bus as a second vector; outputting a third vector from the embedded circuit responsive to the second vector; obtaining a fourth vector having second multiple bits; and comparing the fourth vector with the third vector to determine a first period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.