Patent ID: 8467223

Claim:
A non-volatile memory device comprising: a control gate configured to receive a read voltage; an insulation film formed over the control gate; a metal layer formed over the insulation film, the metal layer configured to include a channel region, and a drain region and a source region formed at first and second ends of the channel region; a ferroelectric layer formed over the channel region of the metal layer; and a program and read gate formed over the ferroelectric layer, wherein a write operation of data corresponding to a resistance state of the channel region is performed by changing polarity of the ferroelectric layer in response to a voltage applied to the program and read gate, the drain and source regions, and the control gate, and wherein a read operation of data is performed by sensing a current value changing with a polarity state of the ferroelectric layer if the read voltage is input to the control gate and a sensing bias voltage is input to any of the drain region and the source region.