Patent ID: 8525566

Claim:
A circuit comprising: an input stage configured to receive an input data signal and further configured to receive a clock signal having a first phase and a second phase; an output stage having a first driver circuit and a second driver circuit and configured to drive an output signal on an output node to a first state responsive to a first transition of the input data signal on an input node concurrent with the first phase of the clock signal, wherein the input stage is configured to activate a first driver circuit responsive to detecting the first transition of the input data signal and wherein the input stage is configured to cause the second driver circuit of the output stage to drive the output node to a second state responsive to the second transition irrespective of whether the second transition occurs before or after the delay time has elapsed; a reverse stage having a first reverse circuit configured to assert a first inhibit signal at a delay time subsequent to activation of the first driver circuit, and a second reverse circuit configured to assert a second inhibit signal at the delay time subsequent to activation of the second driver circuit, wherein the first driver circuit is configured to be deactivated responsive to assertion of the first inhibit signal and wherein the second driver circuit is configured to be deactivated responsive to assertion of the second inhibit signal, and wherein the reverse stage is further configured to prevent assertion of the first inhibit signal responsive to a second transition of the input data signal occurring before the delay time has elapsed subsequent to the first transition of the input data signal; and a feedback circuit having a respective input coupled to the output node and a respective output coupled to the first and second reverse circuits, wherein responsive to a state change of the output node, the feedback circuit is configured to drive a corresponding state change on its respective output at a delay time subsequent to the state change on the output node.