Patent ID: 7750692

Claim:
A circuitry that is operable to perform digital division of a signal, the circuitry comprising: first and second p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs); first and second n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs), wherein; a drain of the first P-MOSFET is coupled to a drain of the first N-MOSFET; a drain of the second P-MOSFET is coupled to a drain of the second N-MOSFET; a gate of the first P-MOSFET is coupled to a gate of the first N-MOSFET; a gate of the second P-MOSFET is coupled to a gate of the second N-MOSFET; and a source of the first N-MOSFET is coupled to a source of the second N-MOSFET; third and fourth P-MOSFETs; third and fourth N-MOSFETs, wherein: a drain of the third P-MOSFET is coupled to a drain of the third N-MOSFET; a drain of the fourth P-MOSFET is coupled to a drain of the fourth N-MOSFET; a gate of the third P-MOSFET is coupled to a gate of the third N-MOSFET; a gate of the fourth P-MOSFET is coupled to a gate of the fourth N-MOSFET; a source of the third N-MOSFET is coupled to a source of the fourth N-MOSFET; the drain of the first P-MOSFET is coupled to the drain of the third P-MOSFET and is coupled to the gate of the fourth P-MOSFET; and the drain of the second P-MOSFET is coupled to the drain of the fourth N-MOSFET and is coupled to the gate of the third P-MOSFET; fifth and sixth P-MOSFETs; fifth and sixth N-MOSFETs, wherein: a drain of the fifth P-MOSFET is coupled to a drain of the fifth N-MOSFET; a drain of the sixth P-MOSFET is coupled to a drain of the sixth N-MOSFET; a gate of the fifth P-MOSFET is coupled to a gate of the fifth N-MOSFET; a gate of the sixth P-MOSFET is coupled to a gate of the sixth N-MOSFET; a source of the fifth N-MOSFET is coupled to a source of the sixth N-MOSFET; the drain of the third P-MOSFET is coupled to the coupled gates of the fifth P-MOSFET and the fifth N-MOSFET; and the drain of the fourth P-MOSFET is coupled to the coupled gates of the sixth P-MOSFET and the sixth N-MOSFET; seventh and eighth P-MOSFETs; and seventh and eighth N-MOSFETs, wherein: a drain of the seventh P-MOSFET is coupled to a drain of the seventh N-MOSFET; a drain of the eighth P-MOSFET is coupled to a drain of the eighth N-MOSFET; a gate of the seventh P-MOSFET is coupled to a gate of the seventh N-MOSFET; a gate of the eighth P-MOSFET is coupled to a gate of the eighth N-MOSFET; a source of the seventh N-MOSFET is coupled to a source of the eighth N-MOSFET; the drain of the fifth P-MOSFET is coupled to the drain of the seventh P-MOSFET and is coupled to the gate of the eighth P-MOSFET; and the drain of the sixth P-MOSFET is coupled to the drain of the eighth N-MOSFET and is coupled to the gate of the seventh P-MOSFET; and wherein: the sources of each of the first P-MOSFET, the second P-MOSFET, the third P-MOSFET, fourth P-MOSFET, the fifth P-MOSFET, the sixth P-MOSFET, seventh P-MOSFET, and the eighth P-MOSFET are all directly connected to a power supply voltage.