Patent ID: 7839924

Claim:
A signaling system comprising: a transmitter circuit configured to equalize input data in response to a control signal and to transmit a partial response signal through a transmission medium; and a receiver circuit configured to recover an output data from said partial response signal and to generate said control signal based on said partial response signal and an expected signal to output said control signal to said transmitter circuit, wherein said transmitter circuit comprises a transmitter side equalizing circuit configured to equalize the input data in response to said control signal, wherein said transmitter side equalizing circuit comprises: a plurality of stages of delay circuits; a plurality of parallel-serial converting circuits configured for receiving data in parallel and for serially outputting the received parallel data, the plurality of parallel-serial converting circuit including at least one parallel-serial converting circuit receiving input data in parallel from two delay circuits from among the plurality of delay circuits, and outputting serial data based on the received parallel data; and a plurality of variable output drivers configured for receiving said serial data output from the plurality of parallel-serial converting circuits and configured to output data based on the received serial data and corresponding predetermined weights.