Patent ID: 7937572

Claim:
A processing apparatus arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions, comprising: i. a plurality of issue slots arranged for parallel execution of the plurality of instructions; ii. a plurality of register files accessible by the plurality of issue slots; iii. a communication network for coupling the plurality of issue slots and the register files, iv. characterized in that the processing apparatus is further arranged to produce a first identifier on a validity of a first result data produced by a first issue slot and a second identifier on a validity of a second result data produced by a second issue slot, v. in that the communication network comprises first selection circuits and second selection circuits arranged to dynamically control a selective write back of the first result data and the second result data to a register of the register files, in a single processor cycle, by using the first identifier and the second identifier, vi. wherein the first selection circuits are coupled to outputs of the issue slots, respectively, and vii. wherein the second selection circuits are coupled to inputs of the register files, wherein the first selection circuits select result data and output valid result data for transfer as selected result data and result valid signal via a communication channel to the second selection circuits, and wherein the second selection circuits dynamically select a valid result data from the selected result data using a value of a corresponding result value signal.