Patent ID: 7610470

Claim:
A method for preventing data hazards during simultaneous speculative threading, comprising: executing instructions in an execute-ahead mode using a first thread, wherein executing instructions in the execute-ahead mode involves maintaining dependency information for each register indicating whether the register is subject to an unresolved data dependency; upon the resolution of a data dependency during execute-ahead mode, copying a dependency information to a speculative copy of the dependency information; commencing execution of the deferred instructions in a deferred mode using a second thread; and while executing instructions in the deferred mode, if the speculative copy of the dependency information for a destination register indicates that a write-after-write (WAW) hazard exists with a subsequent non-deferred instruction executed by the first thread in execute-ahead mode, the method further comprises executing the deferred instruction to produce a result, and forwarding the result to be used by subsequent deferred instructions, without committing the result to the architectural state of the destination register; wherein the second thread makes the result available to the subsequent deferred instructions without overwriting a result produced by a following non-deferred instruction; wherein the dependency information includes a “not-there” bit, which indicates whether or not a value to be stored in the register by a preceding instruction is subject to an unresolved data dependency and is consequently not available, and a speculative “not-there” bit, which indicates whether or not the register was subject to an unresolved data dependency when the second thread commenced execution in deferred mode; and wherein copying the dependency information to the speculative copy of the dependency information involves copying the “not-there” bits to the speculative “not-there” bits.