Patent ID: 8058721

Claim:
A package structure, comprising: a core board having a first surface, an opposite second surface, and at least a through cavity penetrating the first and second surfaces; a semiconductor chip received in the at least a through cavity and having an active surface and an opposite inactive surface, the active surface and the inactive surface having a plurality of first electrode pads and a plurality of second electrode pads, respectively, wherein the semiconductor chip has a plurality of through-silicon vias, and a portion of the through-silicon vias penetrate the semiconductor chip for electrically connecting the first and second electrode pads; a first dielectric layer disposed on the first surface of the core board and the active surface of the semiconductor chip; a first wiring layer disposed on the first dielectric layer and formed with a plurality of first conductive vias penetrating the first dielectric layer so as for the first wiring layer to be electrically connected to the first electrode pads; a second dielectric layer disposed on the second surface of the core board and the inactive surface of the semiconductor chip; and a second wiring layer disposed on the second dielectric layer and formed with a plurality of second conductive vias penetrating the second dielectric layer so as for the second wiring layer to be electrically connected to the second electrode pads.