Patent ID: 7051166

Claim:
A memory system employing a directory-based cache coherency scheme, the memory system comprising: a memory unit comprising a plurality of memory modules, each memory module storing a plurality of cache lines, with each cache line comprising a plurality of data bits and a plurality of informational bits; a common data bus coupled to all of the memory modules and configured to read/write data bits from/to all of the memory modules; a plurality of information buses, each information bus coupled to a corresponding one of the memory modules and configured to read/write informational bits of cache lines from/to its corresponding memory module; and a memory controller controlling access to the memory unit, the memory controller configured to read a plurality of data bits and a plurality of information bits of a first cache line from a first memory module via the common data bus and the information bus corresponding to the first memory module, and in a parallel operation to write a plurality of informational bits of a second cache line to a second memory module via the information bus corresponding to the second memory module.