Patent ID: 8773908

Claim:
A nonvolatile memory device comprising: a memory cell array; a page buffer unit connected to the memory cell array via bit lines and configured to store a verify-read result during a verify read operation, to divide the verify-read result into a plurality of verify-read result groups, and to sequentially output the verify-read result groups; a reference current generating unit configured to generate a reference current; a page buffer decoding unit configured to sequentially output currents according to a number of fail bits of each of the plurality of groups based on the reference current; an analog bit counting unit configured to count the currents sequentially output from the page buffer decoding unit based on the reference current signal; a digital adding unit configured to calculate an accumulated sum of a counting result of the analog bit counting unit; a pass/fail checking unit configured to output one of a pass signal and a fail signal according to a calculation result of the digital adding unit; and a control unit configured to control a program operation.