Patent ID: 7345856

Claim:
A transient electrical arc suppression circuit, comprising: (a) first terminal means consisting essentially of: (a1) a source terminal for connection to an electrical power source; (a2) a load terminal for connection to an electrical load; and (b) first switching means comprising: (b1) first active switch comprising at least one active semiconductor switch for switching between a first operating state and a second operating state, the first operating state providing a relatively low resistance electrical pathway between the source terminal and the load terminal, and the second operating state providing a relatively high resistance electrical pathway between the source terminal and the load terminal; (b2) biasing circuitry responsive to a normal current flowing between the source terminal and the load terminal, for biasing the at least one active switch to operate in the first state; (b3) transient sensing circuitry responsive to an increase in the current flowing between the source terminal and the load terminal due to an arc configured to change the biasing of said active semiconductor switch in response to arc current transient, for switching said active semiconductor switch to operate in the second state so as to suppress the arc; (b4) delay circuitry for momentarily delaying return to the first state from the second state after the arc has been suppressed; and wherein connections between the source terminal and an output of a high voltage power supply and between the load terminal and a high voltage terminal of a load are in themselves sufficient to provide each, as needed, but at least two, of power, control signals and ground reference to the said active semiconductor switch, biasing circuitry, transient sensing circuitry and delay circuitry.