Patent ID: 8710868

Claim:
A sense-amplifier monotizer comprising: an amplifier circuit configured to output a select logic state while a clock signal is in a first phase, and sample a data signal and output at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase, wherein the amplifier circuit is configured to be latched responsive to a state transition of an output of the amplifier circuit as the data signal is sampled by the amplifier circuit while the clock signal is in the second phase; and a keeper circuit configured to keep a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase; wherein the amplifier circuit comprises two amplifier legs for sampling the data signal and a complementary logic state of the data signal, respectively, and the amplifier circuit is configured to be latched as the data signal and the complementary logic state of the data signal are sampled while the clock signal is in the second phase and wherein the data signal and the complementary logic state of the data signal drive a NAND gate, which drives, along with the clock signal, a NOR gate, which drives a transistor of the amplifier legs, such that the amplifier circuit is latched as the data signal and the complementary logic state of the data signal are sampled while the clock signal is in the second phase.