Patent ID: 8205145

Claim:
A high speed add-compare-select circuit comprising: a plurality of path metrics; a plurality of branch metrics, each branch metric associated with one of the plurality of path metrics; a first plurality of adders configured to add a plurality of distinct metrics and generate a plurality of outputs therefrom, wherein the first plurality of adders are arranged in pairs, each pair of adders associating with a path metric and its associated branch metric, and each pair of adders comprising: a first adder for generating a sum of a most significant portion of a path metric, a most significant portion of an associated branch metric, and a carry-in bit; and a second adder for generating a sum of a least significant portion of the path metric and a least significant portion of the associated branch metric; and comparing logic coupled to the outputs of the first plurality of adders, for generating selector control signals in response to the plurality of outputs; and selector circuitry configured to generate the next path metric in response to the at least one path metric and further in response to the plurality of outputs.