Patent ID: 7235834

Claim:
A stacked type ferroelectric memory having a plurality of ferroelectric capacitors and transistors connected thereto, wherein lower electrodes of the ferroelectric capacitors and source/drain regions of the corresponding transistors are directly connected by contact plugs, respectively, the ferroelectric memory characterized in that: a first hydrogen barrier layer is formed below the lower electrodes of the plurality of ferroelectric capacitors, and a second hydrogen barrier layer covers upper surfaces and side surfaces of the plurality of ferroelectric capacitors; all upper electrodes of a plurality of the ferroelectric capacitors connected to a common plate line are connected by an upper wiring layer formed above the second hydrogen barrier layer; a third hydrogen barrier layer is formed on the upper wiring layer to surround the second hydrogen barrier layer; all end sections of the third hydrogen barrier layer contact the first hydrogen barrier layer; and the upper wiring layer and the plate line are connected through a lower wiring provided at a dielectric layer on a lower side of the first hydrogen barrier layer.