Patent ID: 8384568

Claim:
A decoder circuit for down-sampling a plurality of samples from an input signal having a differential Manchester encoding, comprising: a first input port arranged to receive a first, a second, and a third sample of the plurality of samples, the plurality of samples being oversamples of the input signal; a second input port arranged to receive a state indicating whether a clock transition or a data transition precedes the first, second, and third samples; a third input port arranged to receive a first, a second, and a third down-sampled bit generated from the plurality of samples; a detector circuit coupled to the first, second, and third input ports and configured to generate a detection signal indicating a presence of a short pulse within the plurality of samples in response to the state indicating the clock transition and the second and third down-sampled bits being equal and differing from the first down-sampled bit and the third sample; and a generator circuit coupled to the detector circuit and the first input port, the generator circuit configured to generate a fourth down-sampled bit, wherein the fourth down-sampled bit equals the third sample in response to the detection signal indicating the presence of the short pulse, and the fourth down-sampled bit equals the second sample in response to the detection signal not indicating the presence.