Patent ID: 7183862

Claim:
A phase-locked loop circuit comprising: a phase-frequency divider, wherein the phase-frequency divider is configured to receive a reference input signal and a feedback input signal, and wherein the phase-frequency divider is configured to provide an up output signal and a down output signal; a counter holding a value, wherein the value is configured to increment with a pulse received from the phase-frequency divider up output signal and decrement with a pulse received from the phase-frequency divider down output signal; a first charge pump, wherein the first charge pump is configured to receive the value from the counter and to provide a first output signal, wherein the first output signal is proportional to the counter value; a second charge pump, wherein the second charge pump is configured to receive the up output signal and the down output signal and to provide a second output signal, wherein the second output signal changes according to the up and down output signals; and a voltage-controlled oscillator, wherein the voltage-controlled oscillator is configured to receive said first and second output signals.