Patent ID: 7500205

Claim:
A process for transforming an initial circuit design, the initial circuit design having at least one primary clock and an initial number of secondary clocks derived from the primary clocks, the secondary clocks comprising generated clocks, the initial circuit design further having a plurality of sequential elements clocked by the secondary clocks, and the initial circuit design having an initial amount of clock skew associated with clocking the sequential elements from the secondary clocks, the process comprising producing a transformed circuit design from the initial circuit design having a transformed number of secondary clocks, wherein the transformed number is less than the initial number a transformed amount of clock skew, wherein the transformed amount is less than the initial amount wherein producing a transformed circuit design further comprises selecting one of the sequential elements, the selected sequential element having a clock input identifying the generated clock connected to the clock input of the selected sequential element extracting the cone of logic that produces the generated clock retiming forward the generated clock cone of logic creating clock-enable logic for the selected generated clock inserting the created clock-enable logic into the transformed circuit design connecting the clock-enable logic to the selected sequential element re-clocking the selected sequential element from the generated clock to the master clock.