Patent ID: 6879510

Claim:
A nonvolatile ferroelectric memory device, comprising: a top cell array block including a first plurality of unit cells, each unit cell having a pair of first and second top split wordlines connected with a gate of a switching transistor and one node of a ferroelectric capacitor, and each unit cell formed in a split structure with a corresponding unit cell along a bitline; a bottom cell array block provided with a second plurality of unit cells, each unit cell having a pair of first and second bottom split wordlines to correspond to the pair of first and second top split wordlines, the first and second bottom split wordlines being connected with a gate of a switching transistor and one node of a ferroelectric capacitor; a top split wordline driver controlling an output signal transmitted to the pair of first and second top split wordlines of the top cell array block; a bottom split wordline driver controlling an output signal transmitted to the pair of first and second bottom split wordlines of the bottom cell array block; a split wordline driver controller outputting first and second split wordline control signals transmitted to the first and second top split wordlines and the first and second bottom split wordlines, under control of the top and bottom split wordline drivers; and a sensing amplifier arranged for each bitline between the top cell array block and the bottom cell array block, wherein the top cell array block includes a first top cell array at a first side of the top split wordline driver and a second top cell array at a second side of the top split wordline driver opposite to the first side, wherein the gate of the switching transistor and the one node of the ferroelectric capacitor of each unit cell of the first top cell array block and the second top cell array block are connected with one split wordline of the pair of split wordlines.