Patent ID: 8502580

Claim:
A semiconductor device, comprising: a variable delay unit configured to delay an external clock signal by a time period corresponding to a delay control signal and to generate an internal clock signal; a delay replica modeling unit configured to generate a feedback clock signal by delaying the internal clock signal by a time period corresponding to a clock path and a data path through a circuit; a phase detection unit configured to compare a phase of the external clock signal with a phase of the feedback clock signal, and to generate a phase detection signal; a control signal generation unit configured to generate a control signal in response to the phase detection signal of the phase detection unit; a delay line control unit configured to control a time delay amount of the variable delay unit in response to the control signal; a locking detection unit configured to detect a locking operation completion time of an internal clock signal generation unit, and to generate a locking detection signal in response to the phase detection signal, wherein the internal clock signal generation unit includes the variable delay unit, delay replica modeling unit, phase detection unit, control signal generation unit and delay line control unit; and a monitoring unit configured to receive the locking detection signal, and to monitor environmental elements reflected in a circuit in response to the control signal and the locking detection signal, wherein the monitoring unit performs a monitoring operation after a locking operation of the internal clock signal generation unit has been completed.