Patent ID: 7456643

Claim:
A method of providing concurrent access to one or more integrated circuits on a wafer, comprising: providing an edge-extended wafer translator having a central portion and an edge-extended portion, the edge-extended portion vertically offset from the central portion; and removably attaching a wafer to the central portion of the edge-extended wafer translator, the wafer having integrated circuits thereon; wherein removably attaching the wafer to the central portion brings a first plurality of wafer-side contact terminals into electrical contact with a first set of pads on the wafer, and brings a second plurality of wafer-side contact terminals into electrical contact with a second set of pads on the wafer; and wherein the first plurality of wafer-side contact terminals are electrically connected to a first plurality of inquiry-side contact terminals disposed on the central portion of the edge-extended wafer translator, and the second plurality of wafer-side contacts are electrically connected to a second plurality of inquiry-side contact terminals disposed on the edge-extended portion of edge-extended wafer translator; further comprising mounting the edge-extended wafer translator to a mounting fixture; wherein mounting the edge-extended wafer translator to the mounting fixture comprises disposing the vertically offset edge-extended portion upon the mounting fixture; further comprising contacting a portion of the first pluralrty of inquiry-side contact terminal with the probes of a probe card.