Patent ID: 8654584

Claim:
A non-volatile memory device, comprising: an electrically insulating layer on a semiconductor substrate; a NAND-type string of nonvolatile memory cells comprising a plurality of vertically-stacked nonvolatile memory cell sub-strings disposed at side-by-side locations on said electrically insulating layer, said NAND-type string of comprising an impurity-doped semiconductor pattern that extends on opposing sidewalls of each of said plurality of vertically-stacked nonvolatile memory cell sub-strings; a string selection transistor comprising a gate electrode extending between said electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate; an electrically conductive string selection plug extending through said electrically insulating layer and electrically connecting a drain terminal of a first of the nonvolatile memory cells in said NAND-type string to the source of said string selection transistor, said electrically conductive string selection plug contacting a portion of the impurity-doped semiconductor pattern that extends adjacent a base of a first of the plurality of vertically-stacked nonvolatile memory cell sub-strings; a ground selection transistor comprising a gate electrode extending between said electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate; and an electrically conductive ground selection plug extending through said electrically insulating layer and electrically connecting a source terminal of a last of the nonvolatile memory cells in said NAND-type string to the drain of said ground selection transistor, said electrically conductive ground selection plug contacting a portion of the impurity-doped semiconductor pattern that extends adjacent a base of a last of the plurality of vertically-stacked nonvolatile memory cell sub-strings.