Patent ID: 8877606

Claim:
A method of implementing dual-depth shallow trench isolation (STI) formation in a semiconductor wafer, the method comprising: forming a hardmask layer over a double buried insulator back gate semiconductor-on-insulator substrate, the double buried insulator back gate semiconductor-on-insulator substrate comprising a bulk substrate, a lower insulating layer formed on the bulk substrate, a lower layer of silicon nitride formed on the lower insulting layer, a polysilicon back gate layer formed on the lower layer of silicon nitride, an upper insulating layer formed on the polysilicon back gate layer, the upper insulating layer comprising an etch stop layer formed directly on the polysilicon back gate layer and an oxide layer formed on the etch stop layer, and a semiconductor-on-insulator layer formed on the upper insulating layer; wherein the lower layer of silicon nitride and etch stop layer act as a dopant diffusion barrier for the polysilicon back gate layer; patterning the hardmask layer and etching through the semiconductor-on-insulator layer so as to form shallow active area level STI recesses, wherein etching of the shallow active area level STI recesses stops on the etch stop layer; forming a photoresist layer over the substrate and lithographically patterning the photoresist layer to selectively expose part of one or more of the shallow active area level STI recesses; etching through any remaining portion of the upper insulating layer and the back gate layer, thereby forming one or more deep back gate level STI recesses having portions thereof self-aligned to portions of one or more of the shallow active area level STI recesses by converting the portions of one or more of the shallow active area level STI recesses to the deep back gate level STI recesses, wherein etching of the deep back gate level STI recess stops within the lower insulating layer; and simultaneously filling both the shallow active area level STI recesses and the self-aligned deep back gate level STI recesses with one or more insulating materials, and thereafter planarizing the one or more filled insulating materials such that top surfaces of the insulating materials in filled shallow active area level STI recesses are substantially coplanar with top surfaces of the insulating materials in filled deep back gate level STI recesses.