Patent ID: 8862954

Claim:
An apparatus comprising: a control module configured to (i) receive a first clock signal, and (ii) generate a gate signal based on the first clock signal; a gate module configured to (i) receive the first clock signal, and (ii) cease outputting the first clock signal based on the gate signal; a function module comprising a plurality of storage elements, wherein the plurality of storage elements are configured to operate according to the first clock signal or a second clock signal; a mode module configured to generate a mode signal subsequent to the control module generating the gate signal, wherein the plurality of storage elements are configured to form a scan chain in response to the mode signal; and a first multiplexer configured to (i) receive the first clock signal, the second clock signal and the mode signal, and (ii) based on the mode signal, output the first clock signal or the second clock signal to the function module, wherein the control module comprises a register configured to store a predetermined number of cycles, a trigger module configured to generate a trigger signal, a counter configured to count cycles of the first clock signal in response to the trigger signal, and a comparator configured to (i) compare the predetermined number of cycles to a number of the cycles counted by the counter, and (ii) provide the gate signal to the gate module in response to the counter counting the predetermined number of cycles of the first clock signal.