Patent ID: 7884451

Claim:
An integrated circuit package, comprising: an integrated circuit die comprising a first pad, a second pad adjacent to the first pad, a third pad adjacent to the second pad, and a fourth pad adjacent to the third pad; a lead frame comprising a first lead, a second lead adjacent to the first lead, a third lead adjacent to the second lead, and a fourth lead adjacent to the third lead; and first, second, third and fourth bondwires connecting the first, second, third and fourth leads to the first, second, third and fourth pads, respectively, wherein the first lead is spaced apart from the second lead at a first distance, the third lead is spaced apart from the fourth lead at the first distance, and the second lead is spaced apart from the third lead at a second distance that is different than the first distance, and wherein the first lead carries a signal having a first polarity, the second lead carries a signal having a second polarity, the third lead carries a signal having the first polarity and the fourth lead carries a signal having the second polarity, and wherein the first polarity is opposite the second polarity.