Patent ID: 7745259

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface and four side surfaces; wiring disposed on at least one of the side surfaces of the main body; a plurality of first terminals disposed on the top surface of the main body; and a plurality of second terminals disposed on the bottom surface of the main body, wherein: the main body includes a plurality of layer portions stacked between the top surface and the bottom surface; each of the plurality of layer portions includes: a semiconductor chip having a top surface, a bottom surface and four side surfaces; an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and a plurality of electrodes connected to the semiconductor chip; the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed; each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals.