Patent ID: 7055054

Claim:
A computer system comprising: a bus subsystem for transferring digital information; a processing unit for processing the digital information; a memory module array having multiple memory modules, each of the memory modules having multiple memory blocks for storing the digital information; a memory fail-over subsystem cooperatively coupled to fail-over individual memory blocks, and the digital information stored therein, of one or more of the memory modules, wherein the memory fail-over subsystem fails-over an individual memory block when a data error for the individual memory block exceeds a permissible threshold, and accesses to remaining memory blocks in the same memory module as the failed-over memory block are satisfied by the remaining memory blocks in the same memory module; a tag storage having storage locations for storing tags corresponding to one or more memory blocks in one or more of the memory modules; wherein a tag corresponding to the failed-over memory block is stored in the tag storage upon fail-over of the failed-over memory block; and a memory controller for controlling transfer, between the bus subsystem, the processing unit and the memory module array, of the digital information; and an auxiliary memory cooperatively coupled to the memory controller to respond to memory accesses, wherein the digital information stored in the failed-over memory block is transferred to an auxiliary location in the auxiliary memory.