Patent ID: 7821865

Claim:
A nonvolatile memory device comprising: a plurality of memory banks, each of which includes a plurality of nonvolatile memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks and including a write global bit line used to write data into the plurality of memory banks and a read global bit line used to read data from the plurality of memory banks; a plurality of main word lines, each main word line arranged corresponding to one of the plurality of memory banks; at least one set of local bit lines, each set of local bit lines associated with the memory cells of at least one of the memory banks; at least one write local column select circuit associated with each set of local bit lines, and coupling at least a portion of the set of local bit lines with one of the write global bit lines during a write operation; and at least one read local column select circuit associated with each set of local bit lines, and coupling at least a portion of the set of local bit lines with one of the read global bit line during a read operation, wherein first and second write local column select circuits are located on respective sides of an array of the memory cells, first and second read local column select circuits are located on respective sides of the memory cell array, and one of the first write local column select circuit and the first read local column select circuit includes selection transistors for half of the local bit lines in the cell array.