Patent ID: 7560970

Claim:
A level converter, comprising: a first latch having first and second power supply terminals, and first and second nodes; a second latch having third and fourth power supply terminals, and third and fourth nodes; a first transistor having a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage; a third transistor having a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode; and a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node.