Patent ID: 7080239

Claim:
A loop control circuit comprising: a means for storage that pushes down a loop leading address, a value indicating the number of loop executions and a loop trailing address of a loop instruction being initially executed into a loop leading address stack, a loop number stack and a loop trailing address stack respectively, and stores the address of the instruction immediately preceding said loop instruction, the loop leading address, the value indicating the number of loop executions and the loop trailing address into a single loop instruction register into which data were input first among a plurality of loop instruction registers; a means for loop instruction recurrence prediction that predicts a recurrence of said loop instruction by comparing the addresses of the instructions each immediately preceding a loop instruction in said plurality of loop instruction registers and a valid loop trailing address with a program counter value; and a means for push down that adds the number of words constituting said loop instruction to the program counter value and also pushes down the loop leading address, the value indicating the number of loop executions and the loop trailing address stored in a loop instruction register having the address of the instruction immediately preceding said loop instruction which matches the program counter value into said loop leading address stack, said loop number stack and said loop trailing address stack respectively, when the address of the instruction immediately preceding the loop instruction stored in one of said plurality of loop instruction registers matches the program counter value and the valid loop trailing address does not match the program counter value and, accordingly, it is predicted that said loop instruction is to occur next.