Patent ID: 7279960

Claim:
An apparatus for generating a stable voltage reference from a reference voltage (V REF ), the apparatus comprising: a parasitic resistance that is coupled between a first node and a second node; a first resistance circuit that is coupled between the second node and a third node, wherein the third node is associated with a signal ground; a voltage reference circuit that is arranged to provide a first input reference voltage (V REFP ) to the first node and a second input reference voltage (V REFN ) to the third node such that the difference between the first input reference voltage (V REFP ) and the second input reference voltage (V REFN ) is responsive to the reference voltage (V REF ); a control circuit that is arranged to provide a first control signal (CTL P ) such that: the first control signal (CTL P ) is responsive to changes from the reference voltage (V REF ), wherein the control circuit includes a second resistance circuit that is arranged such that a voltage across the second resistance circuit is substantially equal to the reference voltage (V REF ), and arranged such that the first control signal (CTL P ) is responsive to changes in operational characteristics of the second resistance circuit and changes in the reference voltage (V REF ; and a first controlled current source (I COM — P ) that is coupled between a power supply terminal and the second node, wherein the first controlled current source (I COMP — P ) is responsive to the first control signal (CTL P ) such that the voltage drop across the first resistance circuit is maintained, wherein the effect of the parasitic resistance is mitigated by operating the first controlled current source (I COMP — P ) in an open loop configuration with respect to the first input reference voltage (V REFP ).