Patent ID: 8441872

Claim:
A method of operation in a memory controller comprising: generating a mode control signal to specify at least one of a first and second mode; wherein for the first mode, the memory controller is configured to operate by: (i) issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, the first data transfer involving a full data width of the first memory device; and (ii) generating a strobe signal to accompany data associated with the first data transfer; and wherein for the second mode, the controller is configured to operate by: (i) issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices, the second data transfer involving a full width that includes data widths of both the first and second memory devices; and (ii) issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.