Patent ID: 7332750

Claim:
A power semiconductor device comprising: a semiconductor substrate with two surfaces, an N+ doped layer extending into the substrate from one surface thereof, an N− doped layer over the N+ doped layer, a P− doped well formed in the N− doped layer and extending from the other surface of the substrate into the N− doped layer, the P− doped well having a first thickness and forming a first boundary with the N− doped layer, a P+ doped region formed in the P− doped well and extending from the other surface of the substrate into the P− doped well having a second thickness and forming a second boundary between the P+ doped region and the P− doped well, an N+ doped region formed in the other surface of the substrate, the N+ doped region having a third thickness and forming a third boundary between the N+ doped region and the N− doped layer, wherein the P+ doped region is vertically thinner than the P− doped well and vertically thinner than the N+ doped region, and recombination centers comprising noble metal impurities disposed in the N− doped layer and the P− doped well.