Patent ID: 7528449

Claim:
A semiconductor device comprising: a plurality of gate electrodes which are arrayed in parallel on a semiconductor region on a semiconductor substrate; a source region and a drain region which are formed in the semiconductor region on both sides of each gate electrode; a plurality of source contacts which are formed on the source region; a plurality of drain contacts which are formed on the drain region; a plurality of substrate contacts which are formed on the semiconductor substrate and electrically connect to the semiconductor substrate; and a salicide block formed between the gate electrode and the plurality of drain contacts, the salicide block preventing silicidation on the drain region wherein the salicde block comprises a first salicide block which is spaced apart from the substrate contacts by a predetermined distance, and a second salicide block which is spaced apart from the substrate contacts by a distance longer than the predetermined distance, and a length of the second salicide block in a channel length directions is larger than that of the first salicide block.