Patent ID: 7456674

Claim:
An integrated circuit device comprising: a waveform generator adapted to generate a waveform signal, wherein said waveform generator is clocked by a first clock signal; and a deskewer circuit adapted to receive and gate said first clock signal and said waveform signal so as to generate a second clock signal such that said second clock signal is synchronously linked to said first clock signal, wherein said deskewer can be tested and comprises: a flip-flop adapted to receive said waveform signal and said first clock signal and to generate a first output signal; a latch in parallel with said flip-flop and adapted to receive said waveform signal and said first clock signal and to generate a second output signal; an AND gate adapted to receive said first output signal and a test mode signal from a test mode pin and to generate a third output signal; and a multiplexer adapted to gate said third output signal, said second output signal, and said first clock signal in order to generate said second clock signal such that when said test mode signal and said first clock signal are both low said second clock signal is low.