Patent ID: 7808052

Claim:
A semiconductor device comprising: a first well region; a second well region; a well isolation region disposed between the first well region and the second well region, the well isolation region isolating the first well region and the second well region from each other; the first and second well regions each including an active region, a device isolation groove that defines the active region, and a device isolation insulating film that fills the device isolation groove; the first well region including a first well layer; the second well region including a second well layer; the well isolation region including a well isolation groove, a well isolation insulating film that fills the well isolation groove, and a diffusion stopper layer disposed under a bottom of the well isolation groove; and the first and second well layers having first and second bottoms respectively, and the first and second bottoms being deeper in depth than a bottom of the device isolation groove and shallower in depth than the bottom of the well isolation groove.