Patent ID: 8379740

Claim:
A signal processor for processing a digital input signal comprising samples sampled at a sampling frequency, the signal processor comprising: a plurality of filters arranged to divide the digital input signal into a first signal in a first frequency band below a first cut-off frequency, and a second signal in a second frequency band above a second cut-off frequency; first frequency shifting circuitry arranged to shift the second signal to a frequency band below the first cut-off frequency; decimation circuitry arranged to decimate the first signal to generate a first decimated signal and the second frequency shifted signal to generate a second decimated signal, the first and second decimated signals having samples at most at half the sampling frequency of the digital input signal, wherein the decimation circuitry is arranged to receive the second frequency shifted signal from the first frequency shifting circuitry; and processing circuitry arranged to process the decimated first and second signals.