Patent ID: 8140040

Claim:
An integrated circuit ( 120 ), comprising: a Phase Locked Loop (PLL) ( 100 ) configured for use with a continuous stream receiver ( 110 ) comprising a control voltage line configured to deliver a control voltage ( 30 ); a capacitor array ( 20 ) coupled to said control voltage line and configured to deliver a capacitive load to said control voltage based upon an add signal ( 26 ) and a subtract signal ( 28 ); a threshold generator ( 80 ) configured to generate a high threshold voltage ( 40 ) and a low threshold voltage ( 42 ) based upon an ambient temperature (T) in said PLL and including at least one process dependent resistor (R) and at least two process dependent current sources ( 50 , 52 ) all responding to said ambient temperature and used to generate said high threshold voltage and said low threshold voltage; with said PLL configured to respond to a calibration signal ( 32 ) being asserted by responding to said control voltage above said high threshold voltage by asserting said add signal to direct said capacitor array to increase said capacitive load and by responding to said control voltage below said low threshold voltage by asserting said subtract signal to direct said capacitor array to decrease said capacitive load.