Patent ID: 7495669

Claim:
An image processing apparatus comprising: an input unit constructed to input image data; a first memory constructed to store the image data inputted by said input unit; a second memory for buffering the image data; an address generation unit constructed to generate first address information to read out image data in a plurality of units of a rectangular area; a transferring unit constructed to read out one of the plurality of units of image data in the units of the rectangular area from said first memory in accordance with the first address information and to transfer the image data read out from said first memory to said second memory, wherein the rectangular area contains an effective pixel area into which the image data is divided, and an overlap area located in one or more adjacent effective pixel areas which is necessary for processing the image data in the effective pixel area; and an image processing unit constructed to sequentially execute two or more types of image processes on the image data stored in the second memory, wherein the image processing unit includes a plurality of image processing portions which respectively execute a plurality of image processes, wherein the second memory is used as a shared buffer memory for the plurality of image processing portions to sequentially execute the two or more types of image processes on the image data stored in the second memory, wherein the plurality of image processing portions need different sizes of image data to execute the respective image processes, wherein a size of the rectangular area read out from the first memory is defined based on a size of the effective pixel area and a maximum size of an overlap area from among all of the overlap areas necessary for each of the plurality of image processing portions to execute its respective image process, wherein a first portion of the plurality of image processing portions executes a first image process on the image data stored in said second memory, and said transferring unit transfers the image data on which the first image process has been executed to a second portion of the plurality of image processing portions without transferring the image data on which the first image process has been executed back to the first memory, wherein the second portion of the plurality of image processing portions executes a second image process on the image data on which the first image process has been executed, wherein said address generation unit generates second address information to store the image data on which the first image process and the second image process have been executed, in the first memory, and wherein said transferring unit transfers the image data, on which the first image process and the second image process have been executed from the second memory to said first memory in accordance with the second address information generated by said address generation unit.