Patent ID: 6876874

Claim:
A process for reducing electrical consumption of a transmitter/receiver device comprising a frequency synthesizer stage controlled by an automatic frequency control algorithm, the process comprising: generating at least one reference signal for a transmission/reception stage within the transmitter/receive device, the at least one reference signal having a first accuracy and being generated based upon at least one first fractional-division phase-locked loop within the frequency synthesizer stage; generating a clock signal based upon a second fractional-division phase-locked loop within the frequency synthesizer stage; generating a base signal for the at least one first fractional-division phase-locked loop and said second fractional-division phase-locked loop, the base signal having a second accuracy less than the first accuracy; and delivering the base signal as a master-clock signal to a modulator/demodulator connected to the transmission/reception stage when the transmission/reception stage and the second fractional-division phase-locked loop are inactive, and delivering the clock signal as the master-clock signal when the transmission/reception stage and the second fractional-division phase-locked loop are active.