Patent ID: 7355892

Claim:
A flash memory device, comprising: a memory array comprised of a plurality of memory cells arranged into pages, each page having a number of memory cells sufficient to store data for a plurality of groups of memory cells; row decode circuitry for selecting a page of memory cells; a data register for receiving input data for each memory cell in a selected page; a plurality of sense amplifiers coupled to the memory array for sensing the contents of memory cells in a selected page; circuitry for selectively biasing memory cells in the array to program the memory cells in a selected page responsive to input data for the page; a plurality of group fail bit detector circuits, coupled to the sense amplifiers and each associated with one of the plurality of groups in a page, for counting a number of memory cells in its associated group that has a programmed state not corresponding to the input data associated with that memory cell; and control logic circuitry for controlling a programming sequence for the selected page responsive to the numbers of memory cells counted by the plurality of group fail bit detector circuits for the page.