Patent ID: 6927106

Claim:
A method of fabricating a MOS transistor, the method comprising: creating a form structure above a starting structure, the form structure having an opening exposing a single portion of the starting structure; forming a semiconductor material in the opening of the form structure to create a formed semiconductor body having a single generally planar bottom surface above the starting structure, the formed semiconductor body comprising a first body portion, a second body portion, and a third body portion, the second body portion being disposed between the first and third body portions and having first and second sides and a top; removing the form structure; forming a gate structure disposed along at least a portion of the top and sides of the second body portion, the gate structure comprising a conductive gate electrode and a gate dielectric disposed between the gate electrode and the second body portion; and doping the first and third body portions to form source/drains in the first and third body portions.