Patent ID: 8044699

Claim:
A level-shift circuit for translating a control signal to a level-shifted output signal, the level-shift circuit comprising: a pulse generator circuit for receiving the control signal and generating in response to the control signal a Set pulse and a Reset pulse; a voltage translation circuit connected to receive the Set and Reset pulses from the pulse generator circuit and to generate in response a level-translated Set pulse and a level-translated Reset pulse, wherein the level-translated Set pulse and level-translated Reset pulse are derived from a bootstrap voltage node having a voltage greater than a voltage of the Set pulse and the Reset pulse, wherein the voltage translation circuit includes: a first resistor network connected between the bootstrap voltage node and a first node for providing the level-translated Set pulse; a second resistor network connected between the bootstrap voltage node and a second node for providing the level-translated Reset pulse; a first high-voltage transistor connected between the first resistor network and a reference node and controlled to be On or Off by the Set pulse provided by the pulse generator circuit, wherein when the first high-voltage transistor is On a current path between the bootstrap voltage node and the reference node through the first resistor network provides the level-translated Set pulse; a second high-voltage transistor connected between the second resistor network and a reference node and controlled to be On or Off by the Reset pulse provided by the pulse generator circuit, wherein when the second transistor is On a current path between the bootstrap voltage node and the reference node through the second resistor network provides the level-translated Reset pulse; a common-mode transient detection circuit connected to monitor voltages across the first and second resistor networks and to provide an output in response to detected common-mode transients; and a gain reduction circuit connected to reduce gain associated with translation of the Set and Reset pulses to level-translated Set and Reset pulses in response to a common-mode transient detected by the common-mode transient detection circuit; a first differential detector connected to receive the level-translated Set pulse and the level-translated Reset pulse, wherein the first differential detector generates a logic high output when a threshold voltage difference is present between the level-translated Set pulse and the level-translated Reset pulse; a second differential detector connected to receive the level-translated Reset pulse and the level-translated Set pulse, wherein the second differential detector generates a logic high output when a threshold voltage difference is present between the level-translated Reset pulse and the level-translated Set pulse; and a gate drive circuit for generating a gate drive signal based on the outputs provided by the first differential detector and the second differential detector.