Patent ID: 7317223

Claim:
A memory device comprising: a P-type silicon substrate; a cell block region formed in a predetermined region of the silicon substrate, the cell block region having a plurality of memory transistors provided thereon in a byte unit; and a selection transistor region having a plurality of selection transistors provided thereon to switch the memory transistors, the selection transistors for each of the plurality of memory transistors, wherein a P-well is formed in at least one of the cell block region and the selection transistor region, and wherein each of the plurality of memory transistors comprises: a floating gate electrode formed on the semiconductor substrate; a control gate electrode formed on the floating gate electrode; an inter-gate-electrode oxide film interposed between the control gate electrode and the floating gate electrode; a tunnel dielectric film and a gate dielectric film which are interposed between the semiconductor substrate and the floating gate electrode; and a cell junction region formed in the semiconductor substrate below the floating gate electrode.