Patent ID: 8279154

Claim:
A liquid crystal display device comprising: a liquid crystal panel formed by bonding one of substrates having pixels each being arranged at an intersection between each of a plurality of drain lines and each of a plurality of gate lines intersecting said drain lines, to the other of said substrates having color filters; a plurality of drain drivers arranged in an extending direction of said gate lines, for applying gray scale voltage signals to said pixels so arranged as to correspond to predetermined groups of said plurality of drain lines on the basis of display data signals; a plurality of gate, drivers arranged in an extending direction of said drain lines, for applying scanning voltage signals to said pixels arranged along said drain lines; a timing converter for generating said display data signals and various high-speed and low-speed clock signals inclusive of pixel clocks on the basis of a display signal and a timing signal inputted from outside; lines directly formed on one of said substrates of said liquid crystal panel, for serially transferring in series said display data signals, said gray scale voltage signals and said various high-speed and low-speed clock signals inclusive of said pixel clocks to and between said drain drivers; and gate circuits controlled by said pixel clock signals, and disposed for each of said drain drivers on either one, or both, of the input side and the output side of said display data and said gray scale voltage relative to said drain driver; wherein the width of lines for said display data signal and said pixel clock signals as high-speed digital signals, the width of the lines for clock signals as low-speed digital signals other than said pixel clock signals and the width of the lines for said gray scale voltage as a low-speed analog signal are varied in accordance of an allowable resistance value of each of said signals.