Patent ID: 6916698

Claim:
A method for fabricating a CMOS device comprising: fabricating the CMOS device with a mid-gap workfunction metal gate which uses the same metal with a mid-gap work function for the gate of both a PFET area and NFET area; adjusting downwardly the threshold voltage Vt for the PFET area by growing a p doped epitaxial layer over the PFET area, the doped epitaxial layer comprising a boron and carbon co-doped silicon enitaxial layer, wherein the carbon co-doping reduces the diffusion of boron, also during subsequent activation thermal cycles, to maintain a shallow boron doping profile, which provides a CMOS device with a mid-gap metal gate while maintaining good short channel effects; and, growing the p doped epitaxial layer comprising a carbon doped silicon epitaxial layer on a silicon substrate, followed by a boron and carbon doped silicon epitaxial layer spaced from the substrate and extending to the surface of the device.