Patent ID: 7239565

Claim:
A memory apparatus, comprising: at least one local bit-line; a precharge control circuit, coupled to the at least one local bit-line, and adapted to be operable to initiate a precharge pulse after the at least one local bit-line is discharged and to terminate the precharge pulse after the at least one local bit-line has been precharged; a precharge pull-up device, coupled to the precharge control circuit, a first voltage source, and the at least one local bit-line, and adapted to be operable to connect the first voltage source to the at least one local bit-line during the precharge pulse to precharge the at least one local bit-line; and a selected one of a plurality of evaluation pull-down devices, coupled to a clock source, a second voltage source, and the at least one local bit-line, and adapted to be operable to couple the at least one local bit-line to the second voltage source during the clock signal pulse to discharge the at least one local bit-line.