Patent ID: 7003060

Claim:
An output circuit comprises: a data output circuit; and a clock output circuit, wherein the data output circuit includes a first D-type flip-flop having a data input terminal to which a first data line for inputting first data is connected and a data output terminal from which a state according to the first data is outputted in synchronization with rise or fall of a clock signal, and a selector having a selector output terminal from which an output from the first D-type flip-flop or second data is outputted selectively according to a selection signal, and wherein said clock output circuit includes a second D-type flip-flop having a data input terminal to which its own negative logic data output terminal is connected and a positive logic data output terminal and a negative logic data output terminal from which positive logic data and negative logic data of data which has been inputted to the data input terminal are respectively outputted in synchronization with the rise of the clock signal, a third D-type flip-flop having a data input terminal to which its own negative logic data output terminal is connected and a positive logic data output terminal and a negative logic data output terminal from which positive logic data and negative logic data of data which has been inputted to the data input terminal are respectively outputted in synchronization with the fall of the clock signal, and a dummy selector circuit connected to the positive logic and negative logic data output terminals of the second and third D-type flip-flops, and having a clock output terminal from which a clock signal is outputted by using same elements as those of the selector in order to realize same delay time as that of the selector.