Patent ID: 6916701

Claim:
A method for fabricating a silicide layer of a flat cell memory device comprising the steps of: sequentially depositing a gate insulating layer, a gate electrode and an etch stop layer on a substrate of a cell array region and peripheral circuit region; patterning the gate insulating layer, gate electrode, and etch stop layer to form a word line; forming a nitride layer on the word line; forming a gap fill insulating layer over the nitride layer; applying planarization of the gap fill insulating layer using the nitride layer as a planarization stop layer, removing the gap fill insulating layer from the peripheral circuit region; forming an insulating layer on a resulting structure; dry etching the insulating layer to expose a surface of word line and a surface of the substrate of the peripheral circuit region, thereby forming a spacer on a side wall of the word line of the peripheral circuit region; and forming a silicide layer on the upper part of the word line of the cell array region and, at the same time, forming a silicide layer on the upper part of the word line of the peripheral circuit region and on the surface of the substrate.