Patent ID: 8131937

Claim:
An apparatus comprising: a plurality of processors; a plurality of cross-coupled caches of a level of cache memories; main memories, each of said main memories associated with a corresponding processor and the level of cache memories shared among said processors; and a data management facility operable with said processors for directing the flow of data from said main memories to said processors and from said processors to said level of cache memories, the apparatus configured to perform: determining a path along which data evicted from a first cross-coupled cache is to return to a main memory; and determining whether a last passed through cross-coupled cache has an empty or invalid compartment for receiving the data being evicted in response to determining that the path passes through a cross-coupled cache associated with another processor; and storing the data being evicted in an available compartment in response to determining that the last passed through cross-coupled cache has at least one empty or invalid compartment for receiving the data being evicted.