Patent ID: 7936581

Claim:
A bit line decoder for sensing states of memory cells of a memory array, the bit line decoder comprising: D control devices that (i) selectively communicate with (D−1) bit lines of said memory array and (ii) are arranged in a first level and a second level of said bit line decoder, wherein (D−2) of said D control devices are arranged in said first level, two of said D control devices are arranged in said second level, said (D−2) control devices are connected to each other in series forming (D−3) junctions, and (D−3) of said (D−1) bit lines are directly connected to said (D−3) junctions, where log 2(D−2) is an integer greater than 2; a control module that generates first control signals, wherein said first control signals (i) deselect a predetermined number of said D control devices and (ii) select two of said (D−1) bit lines that communicate with one of said memory cells; and an isolation circuit to isolate said first level from said second level, wherein said isolation circuit includes a plurality of isolation devices having (i) first ends that communicate with said (D−2) of said D control devices of said first level and (ii) second ends that communicate with said two of said D control devices of said second level.