Patent ID: 8769459

Claim:
A high-end fault-tolerant computer system, comprising N single junction prototype verification systems and M crossbar-switch interconnection router chipsets, wherein, each crossbar-switch interconnection router chipset is used to achieve interconnection among the N single junction prototype verification systems, switching is not performed among all crossbar-switch interconnection router chipsets, and both M and N are positive integers greater than or equal to 2, wherein, the single junction prototype verification system comprises: a computer board, which is a four-path tightly-coupled computer board, a chip verification board, comprising two junction controller chipsets; wherein, each junction controller chipset comprises: two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together; and an interconnection board, comprising two FGPA chips; wherein, each FPGA chip provides a high speed interconnection port configured to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets; wherein the four-path tightly-coupled computer board comprises 4 CPUs, the 4 CPUs are interconnected internally, and share memories with each other; and all CPUs in the N single junction prototype verification systems are interconnected through the junction controller chipsets and the crossbar-switch interconnection router chipsets, and share memories with each other.