Patent ID: 8458676

Claim:
A method comprising: while a first interpreter on a primary core processes platform-independent code that includes a plurality of code units, determining functionality of a first code unit of the plurality of code units and determining that a secondary core in a multi-core heterogeneous processor is indicated as more suitable to perform the functionality than another core in the multi-core heterogeneous processor, wherein said determining that the secondary core is indicated as more suitable to perform the functionality than another core in the multi-core heterogeneous processor is based, at least in part, on accessing a structure that indicates capabilities of cores of the multi-core heterogeneous processor; packaging the first code unit for the secondary core in response to said determining that the capabilities of the secondary core are indicated as more suitable to perform the functionality, wherein said packaging the first code unit comprises transforming instructions and data of the first code unit to conform with an instruction set architecture of the secondary core, wherein said packaging generates a packaged unit of platform-independent code; and offloading the packaged unit of platform-independent code to a secondary interpreter associated with the secondary core.