Patent ID: 7360056

Claim:
A system, comprising: a plurality of nodes, wherein each node includes an active device and a memory subsystem coupled to the active device; wherein an active device included in a node of the plurality of nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address identifying a coherency unit, wherein a portion of the global address identifies a translation function; wherein a memory subsystem included in the node is configured to perform the translation function identified by the portion of the global address on an additional portion of the global address in order to obtain a local physical address of the coherency unit; wherein each active device included in the node is configured to use the portion of the global address identifying the translation function when determining whether a local copy of the coherency unit is currently stored in a cache associated with that active device; wherein a home memory subsystem included in a home node of the plurality of nodes for the coherency unit is configured to store the portion of the global address identifying the translation function for the node, wherein active devices included in the home node are configured to generate a different value of the portion of the global address, wherein the different value identifies a different translation function associated with the coherency unit in the home node; and wherein if the home memory subsystem determines that the coherency transaction involving the coherency unit cannot be completed within the home node, the home memory subsystem is configured to provide the portion of the global address identifying the translation function for an additional node to a home interface included in the home node for conveyance to the additional node.