Patent ID: 6965982

Claim:
A method of pre-fetching instructions during multithreaded program execution in a processor of a data processing system, said method comprising: determining when an instruction associated with a particular thread is to be pre-fetched from a lower-level memory component, wherein said particular thread is one of multiple threads executing on said processor and said particular thread is proximate to being selected for execution; and pre-fetching said instruction from the lower-level memory component, wherein said instruction is fetched prior to a request for said instruction by an instruction fetch unit (IFU) of the processor that issues a request for said instruction during actual execution of said particular thread, and wherein said instruction is returned from the lower-level memory component to the upper processor level for reduced access latency when said request is issued and said instruction is tagged with an identifier (ID) of said particular thread to indicate that it is associated with said particular thread; and providing said instruction from the processor level rather than said lower-level memory component to an executing unit of said processor when said instruction is required during execution of said particular thread.