Patent ID: 7800185

Claim:
A semiconductor power device comprising: a plurality of power transistor cells disposed in an active area near a top surface of an epitaxial layer of first conductivity type grown on a semiconductor substrate of said first conductivity type wherein each of said transistor cells is surrounded by trenched gates; multiple trenched floating rings disposed in a termination area surrounding said active area and each of said trenched floating rings filled with a doped polysilicon layer of said first conductivity type padded by a gate insulation layer in a trench having a floating voltage wherein said trenched floating rings further penetrating through a body region and extending into said epitaxial layer; said body region of a second conductivity type formed in both said active cell area and said termination area disposed immediately adjacent to said trenched floating rings; said trenched gates further extended to a gate contact area having a greater width than said trench gates in said active cell area as wider trenched gates for electrically contacting a gate pad; and a source region of said first conductivity type disposed only in said active area but not in said termination area comprising said multiple trenched floating rings and no source regions disposed in said epitaxial layer regions adjacent to said wider trenched gate in said gate contact area.