Patent ID: 8848474

Claim:
A sense amplifier coupled between a complementary pair of first and second bitlines that are coupled to respective first and second global bitlines in a static random access memory (SRAM) cell, the sense amplifier comprising: a first inverter including a first input node and a first output node, the first input node coupled to the first bitline through a first capacitor, the first output node coupled to the second bitline through a second capacitor; a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor; a first transmission gate switch coupled between the first input node and the second input node; and a second transmission gate switch coupled between a first common node of the first and second inverters and a second common node of the first and second inverters, wherein the sense amplifier is maintained at a maximum gain point in a read cycle of the SRAM cell.