Patent ID: 7332973

Claim:
A digital phase-frequency error detector, comprising: a phase-frequency detector configured to receive an input signal and a sampled reference signal responsive to a loop filter, a voltage controlled oscillator and a divide by N counter, the phase-frequency detector configured to generate first and second differential signals; and an error detector coupled to the first and second differential signals and configured to generate a phase-frequency error signal responsive to the first and second differential signals, the error detector having respective time-to-digital converters, a summer and a delay element, the respective time-to-digital converters, comprising: a ring oscillator configured to receive the differential signal and having a clock input, a first output responsive to a single cycle of the ring oscillator and a multiple-bit second output responsive to the differential signal, wherein the multiple-bit second output represents time from an edge transition of the clock to an edge transition of the differential signal; a counter coupled to the first output and configured to generate a first binary word; an encoder coupled to the multiple-bit second output and configured to generate a second binary word; and a latch coupled to the counter and the encoder, the latch configured to generate a composite word comprising the first and second binary words, wherein the composite word generated by the respective time-to-digital converters is processed by the summer and the delay element to generate a digital representation of the phase-frequency error.