Patent ID: 7001818

Claim:
A MIS-semiconductor-device manufacturing method comprising the steps of: forming a gate dielectric on a semiconductor substrate of a first conduction type; forming a gate electrode on a top surface of said gate dielectric; forming a first side-wall spacer on a side wall of said gate electrode; forming a second side-wall spacer by placing on said first side-wall spacer; forming a first impurity area having a second conduction type opposite to said first conduction type by introduction of impurities into said semiconductor substrate with said gate electrode, said first side-wall spacer and said second side-wall spacer as a mask; forming a third side-wall spacer by placing on said second side-wall spacer; forming a second impurity area having an impurity concentration higher than an impurity concentration of said first impurity area by introduction of impurities into said semiconductor substrate with said gate electrode, said first side-wall spacer, said second side-wall spacer and said third side-wall spacer as a mask; and carrying out a heat treatment so that one edge of said gate electrode overlaps on said first impurity area, wherein said first side-wall spacer is made of a material having a relative dielectric constant greater than that of said second side-wall spacer and said third side-wall spacer.