Patent ID: 7529131

Claim:
A nonvolatile semiconductor memory comprising: a memory cell unit including a plurality of memory cells, each memory cell of said plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; a control signal generation circuit which during a data readout operation staggers a timing for selecting a selected word line connected to a selected memory cell of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory cell; and a select voltage generation circuit which during said data readout operation boosts the voltage of said non-selected word line to a non-select voltage at said timing for selecting said non-selected word line and the voltage of said selected word line to a select voltage, which is lower than said non-select voltage, at said timing for selecting said selected word line, after the voltage of said non-selected word line is boosted to an intermediate voltage, which is higher than said select voltage and is lower than said non-select voltage.