Patent ID: 8325545

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory cells configured to store a plurality of bits, threshold voltages of the memory cells being set lowest in an erase state and sequentially set higher according to data in a program state; a plurality of bit lines connected to the memory cells; a word line connected to the memory cells; and a control circuit configured to execute a program operation by repeating a plurality of program loops in which a program voltage is stepped up, wherein in a case where a first memory cell is programmed to a first threshold voltage that is lowest among threshold voltages in the program state, the control circuit is configured to charge a first bit line connected to the first memory cell to a third voltage between a first voltage applied to a bit line when a memory cell is programmed to a second threshold voltage higher than the first threshold voltage and a second voltage applied to a bit line when a memory cell is inhibited from being programmed, and the control circuit is configured to charge the first bit line to the third voltage from a first program loop in the program loops to a second program loop in which the first memory cell has been programmed.