Patent ID: 8912569

Claim:
A hybrid transistor, comprising: a substrate having therein a first well region of a first conductivity type, a second well region of a second, opposite, conductivity type, extending substantially to a first surface of the substrate, the first and second well regions forming an NP or PN junction therebetween; a MOS portion having a source region of the second conductivity type extending to the first surface in the first well region, and having a gate conductor overlying and insulated from the first surface at least over the first well region with a first lateral end proximate the source region and a second lateral end extending at least to the NP or PN junction; and a drain or anode (D/A) portion in the second well region, the D/A portion comprising a bipolar transistor having an emitter region of the second conductivity type, a base region of the first conductivity type communicating with the emitter region, and a collector region of the second conductivity type communicating with the base region, wherein the collector region is located in the second well region laterally separated from the NP or PN junction.