Patent ID: 8648779

Claim:
A circuit, comprising: a first digital-to-analog converter (DAC) decoder circuit having a first plurality of inputs, each of the first plurality of inputs coupled to a respective output of a first DAC, the first DAC decoder circuit configured to receive a first number of bits of a digital control signal and output a first output signal in response thereto, the first output signal having a first voltage level corresponding to a voltage level received at one of the first plurality of inputs; a second DAC decoder circuit having a second plurality of inputs, each of the second plurality of inputs coupled to a respective output of a second DAC, the second DAC decoder circuit configured to receive a second number of bits of the digital control signal and output a second output signal in response thereto, the second output signal having a second voltage level corresponding to a voltage level received at one of the second plurality of inputs; and a switched capacitor summing circuit configured to be selectively coupled to the output from the first DAC decoder circuit during a first phase of a cycle and to the output of the second DAC decoder circuit during a second phase of the cycle, the switched capacitor summing circuit configured to output a third output signal having a voltage level based on one of the first and second voltage levels received from the outputs of the first and second DAC decoder circuits, wherein a length of the cycle corresponds to a first number of frames with each frame having a respective duration, the first phase of the cycle corresponds to a second number of frames that is greater than one, and the second phase of the cycle corresponds to a third number of frames that is less than the first and second numbers of frames.