Patent ID: 8335103

Claim:
Integrated circuit, comprising a plurality of bit-lines and a plurality of word-lines as well as a plurality of memory cells coupled between a separate bit-line/word-line pair of the plurality of bit-lines and word-lines for storing data in one of the plurality of memory cells, wherein each memory cell includes a selecting unit, a programmable resistor, and a further addressing-line connected to the memory cell, wherein said selecting unit is implemented as a NMOS-transistor, with its gate connected to the respective word-line, and with its source connected to the respective bit-line, wherein the programmable resistor is connected in series to the drain of the transistor, and is further coupled to the further addressing-line, wherein the word-line is selected before the further addressing-line, and wherein a voltage is applied to the gate of the transistor of the selected memory cell, and wherein said further addressing-line is supplied with a voltage that is larger than said voltage applied to the gate of the transistor of the selected memory cell in order to program a selected memory cell.