Patent ID: 8325111

Claim:
A semiconductor device comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein: one of a source and a drain of the first transistor is electrically connected to a first wiring, the other of the source and the drain of the first transistor is electrically connected to a pixel electrode, the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor, the other of the source and the drain of the fourth transistor is directly connected to a second wiring, a gate of the first transistor is directly connected to one of a source and a drain of the second transistor, the other of the source and the drain of the second transistor is electrically connected to a third wiring, the gate of the first transistor is directly connected to one of a source and a drain of the third transistor, the other of the source and the drain of the third transistor is directly connected to the one of the source and the drain of the first transistor, a gate of the second transistor is electrically connected to a fourth wiring, and a gate of the fourth transistor is directly connected to a fifth wiring, wherein a potential inputted to the first wiring has two values V 1 and V 2 , wherein the potential is V 2 when the second to fourth transistors are in an off state, wherein V 1 is a potential between V 2 and a potential inputted to the second wiring, and wherein a difference between V 1 and the potential inputted to the second wiring is larger than an absolute value of a threshold voltage of the first transistor.