Patent ID: 7829949

Claim:
A semiconductor device comprising: a semiconductor substrate having a PMOS region and an NMOS region; a high-k gate dielectric disposed over said semiconductor substrate in said PMOS and NMOS regions; a PMOS gate structure in said PMOS region, said PMOS gate structure including at least said high-k gate dielectric, a work function tuning layer over said high-k gate dielectric and a first metal layer over said work function tuning layer; and an NMOS gate structure in said NMOS region, said work function tuning layer and said first metal layer absent from said NMOS gate structure and said NMOS gate structure including said high-k gate dielectric with at least one dopant incorporated therein and a second metal layer over said high-k gate dielectric, said high-k dielectric in said PMOS region being deficient of said at least one dopant.