Patent ID: 7660916

Claim:
A method for transferring data over a memory bus in a computer system having a processor and at least two Direct Memory Access (DMA) channels, the method comprising: connecting a first set and a second set of DMA registers to the processor; routing both sets of DMA registers through a switch to a single DMA engine, such that only one set is connected to the DMA engine at a time; storing transfer parameters related to a first DMA request in the first set of DMA registers; selecting through the switch the first set of DMA registers; sending an activation signal to the DMA engine that causes the DMA engine to perform a first data transfer on the bus in accordance with the parameters stored in the first DMA register set; storing transfer parameters related to a second DMA request in the second set of DMA registers, wherein the first and the second DMA requests are for different DMA channels coupled to the bus; and upon completion of the first data transfer, selecting through the switch the second set of DMA registers and sending an activation signal to the DMA engine that causes the DMA engine to perform a second data transfer on the bus in accordance with the parameters stored in the second DMA register set, wherein the selecting through the switch is based on a select signal generated by a one bit counter.