Patent ID: 7743181

Claim:
A system for providing Quality of Service (QoS) processing of a plurality of data packets, the system comprising: a processing engine capable of receiving the plurality of data packets; a first memory for storing the plurality of data packets received by the processing engine; a queue manager module comprising: an interrupt status register, and a plurality of queues comprising an address of at least one data packet of the plurality of data packets, wherein at least one individual bit in the interrupt status register specifies a queue of the plurality of queues causing an interrupt; a second memory for storing a plurality of interrupt masks in consecutive locations starting from a base address, each interrupt mask comprising a bit pattern specifying whether an interrupt is masked for a queue of the plurality of queues; a third memory for storing an interrupt mask address pointer; at least one processor configured to: read the interrupt status register to determine which queue of the plurality of queues is causing an interrupt, read an interrupt mask from said plurality of interrupt masks using said interrupt mask address pointer stored in said third memory; perform a logical operation between the contents of the interrupt status register and said plurality of interrupt masks stored in said second memory; and process the plurality of data packets based on said logical operation; and a counter for incrementing the interrupt mask address pointer to point to another interrupt mask of the plurality of interrupt masks.