Patent ID: 8407021

Claim:
A delay analysis device for analyzing a delay of a semiconductor device, the delay analysis device comprising: an acquisition section that acquires circuit information relating to a path through which signal propagation can be delayed between a beginning latch and an ending latch included in an integrated circuit; a determination section that sets up an assumed fault for each of pins disposed between the beginning latch and the ending latch based on the acquired circuit information, and determines whether a signal change output from the beginning latch can be propagated to the ending latch for each of pins for which the assumed faults are set up; an analysis section that calculates a delay distribution for the path by accumulating delay distributions expressed by using probability density functions of delays that occur in individual delay elements included in the path leading from the beginning latch to the ending latch at a pin through which it has been determined that a signal change output from the beginning latch can be propagated to the ending latch, and by not accumulating the delay distributions at a pin through which it has been determined that the signal change cannot be propagated to the ending latch based on the acquired circuit information; and an output section that outputs the delay distribution for the semiconductor device in which the delay distributions at pins through which the signal change cannot be propagated are excluded.