Patent ID: 7679121

Claim:
A strained silicon channel for a vertical field effect transistor comprising: a substrate having a relaxed n-type Si 1-y Ge y (0≦y≦1) epitaxial region and said first region having a doping concentration greater than 1×10 19 atoms/cm 3 ; a relaxed Si 1-a-b Ge a C b (0≦a≦1, 0≦b≦1) epitaxial region over said first relaxed n-type Si 1-y Ge y epitaxial region; a p-type Si 1-z Ge z (0≦z≦1) epitaxial region over said relaxed Si 1-a-b Ge a C b epitaxial region; a relaxed Si 1-e-f Ge e C f (0≦e≦1, 0≦f≦1) epitaxial region over said p-type Si 1-z Ge z epitaxial region; a strained n-type silicon epitaxial region over said relaxed Si 1-e-f Ge e C f epitaxial region having a doping concentration greater than 1×10 19 atoms/cm 3 ; a vertical structure comprising at least one sidewall extending from said relaxed n-type Si 1-y Ge y epitaxial region, over said region of Si 1-a-b Ge a C b , over said region of Si 1-z Ge z region, over said region of Si 1-e-f Ge e C f , and over said region of strained n-type silicon epitaxial region; and a strained silicon epitaxial region over a region of said at least one sidewall of said vertical structure extending from said region of Si 1-a-b Ge a C b , over said region of Si 1-z Ge z region, to said region of Si 1-e-f Ge e C f .