Patent ID: 8860492

Claim:
A switched capacitor circuit, comprising: an inverter, for receiving a control signal to generate an inverting control signal corresponding to the control signal; a first capacitor, coupled between a first output port and a first node; a delay unit, for delaying a first input signal to generate the delayed first input signal; and a first switch unit, coupled to the delay unit, the first switch unit arranged for receiving the delayed first input signal and a second input signal, and selectively coupling the second input signal to the first node according to the delayed first input signal; wherein the first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal; and after a signal level of the control signal is switched, the first switch unit receives the delayed first input signal corresponding to the control signal with the switched signal level at a time later than a time at which the first switch unit receives the second input signal corresponding to the control signal with the switched signal level.