Patent ID: 8053353

Claim:
A method for forming, on a surface of a thinned-down semiconductor substrate, a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate, comprising: forming, on a side of a first surface of a semiconductor substrate, an insulating region penetrating into the substrate and forming, on the first surface of the semiconductor substrate, a conductive region of polysilicon coated with an insulating layer crossed by conductive vias, said conductive vias connecting a metal track of the interconnect stack to said conductive region, said conductive region being formed at the same time as gates of MOS transistors; gluing the external surface of the interconnect stack on a support and thinning down the substrate; and etching the external surface of the thinned-down substrate and stopping on said insulating region; etching said insulating region and stopping on said conductive region; and filling the etched opening with a metal.