Patent ID: 8612713

Claim:
A memory switching control apparatus using an open serial interfacing, comprising: one or more processor interfacing units which perform interfacing with one or more processing units, the processing units including internal and external processing units; one or more memory interfacing units which respectively have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; one or more of arbitrating units, which are respectively provided corresponding to the one or more memory interfacing units, to independently arbitrate usage rights of the one or more processor interfacing units to the one or more memory interfacing units; and a memory port table which manages memory start addresses respectively allocated to the one or more memory interfacing units, memory sizes of the data storage devices connected to the memory interfacing ports or memory end addresses allocated to system addressing regions allocated to the one or more memory interfacing units, and state information of the one or more memory interfacing units, wherein each of the one or more processor interfacing units comprises: a data buffer which temporarily stores data, a memory address, a control signal, and a state signal inputted to and outputted from the processing unit and adjusts data width and speed of data inputted to and outputted from one of the one or more memory interfacing units, and a decoder and a controller which identifies one of the one or more memory interfacing units which is to be requested to be accessed, based on the memory address, the control signal, and the state signal stored in the data buffer and the memory port table, requests for a usage right, and adjusts a data exchange timing for the one of the one or more memory interfacing units.