Patent ID: 7299236

Claim:
A method of a test data compression using a Zero-Detected Run-length (ZDR) code in a system-on-chip, (SOC), which is stored in a form of algorism or computer programming, the method comprising the steps of: defining a test vector T d to be applied and a test set T diff as follows, T d ={t 1 , t 2 , t 3 , t 4 , t 5 , . . . , t n }, and T diff ={d 1 , d 2 , d 3 , d 4 , d 5 , . . . , d n }={t 1 , t 1 ⊕t 2 t 2 ⊕t 3 , . . . , t n-1 ⊕t n } wherein ⊕ is an exclusive-OR operator; creating the test vector T d and the test set T diff with values generated by an Automatic Test Pattern Generator (ATPG); connecting the elements of the test set T diff in a single chain; sequentially scanning the test set T diff ; creating a codeword (“100”, “101”, “110” and “111”) when a bit ‘1’ appears, and when the codeword is ‘0000’ (0001, 0020, 0011, 0100, 0101, 0110 and0111); repeatedly checking a ‘0 Group’ (‘0000’, ‘0000×2’, ‘0000×3’, ‘0000×4’, ‘0000×5’, ‘0000×6’, ‘0000×7’ and ‘0000×8’) while incrementing the bit of the ‘0 Group’ counter by one until ‘1’ appears as the next bit; recording ‘0111’ when the ‘0 Group’ becomes ‘0000×8’ and counting the number of bits having the value ‘0’; and creating a codeword of a ‘1 Group’ on the SOC when a ‘1’ bit appears.