Patent ID: 7898026

Claim:
A Laterally Diffused MOS (LDMOS) transistor formed in a P− epitaxial layer onto an N+ substrate comprising: a P body region formed in P− epitaxial layer and overlapped with a doped polysilicon as a conductive gate padded with a gate oxide for formation of a channel region, wherein said P body region further encompasses an N+ source region, a P++ body contact doping region and a P+ avalanche improved region; a drain contact trench filled with a conductive plug extending from the top surface of said P− epitaxial layer to contact with N+ substrate and an N+ highly, doped region formed along a sidewall of said drain contact trench; a first LDD-N 1 region formed by ion implantation for the formation of a drift drain region between said channel region and N+ highly doped region; a second LDD-N 2 region formed by ion implantation with a lower energy than that of said first LDD-N 1 region but with a dose higher than said first LDD-N 1 region wherein said second LDD-N 2 region is encompassed in said first LDD-N 1 region and contacts said highly doped N+ region; each of said first LDD-N 1 and second said LDD-N 2 regions has one side opposite to said N+highly doped region overlapped with said doped polysilicon; a combination doping profile of said first LDD-N 1 region and second LDD-N 2 region along a direction vertical to said channel region has a non-Gaussian distribution with a double hump shape; a conductive gate of said doped polysilicon insulated from P− epitaxial layer and partially overlapping said N+ source region and said first LDD-N 1 and second LDD-N 2 regions, wherein said conductive gate has a layer of silicide thereon; and a source metal insulated from said conductive gate and shorted to N+ source region and P++ body contact doping region.