Patent ID: 8522099

Claim:
An apparatus comprising: a logic chip to manage operation of an electronic device structure, the logic chip arranged to access data from the electronic device structure and translate the accessed data to an interconnect in the logic chip to transmit the accessed data, from the logic chip via a link, to an apparatus external to the electronic device structure and the logic chip, the interconnect operable such that management of data flow for the electronic device structure is separated from the link to the apparatus and such that the electronic device structure is independent of changes to the link and interface changes of the apparatus; a pattern buffer disposed in the logic chip arranged to provide a test pattern to the electronic device structure; and an embedded processor disposed in the logic chip, the embedded processor configured to build the test pattern into the pattern buffer, wherein the logic chip comprises circuitry to operatively stall the pattern buffer after output of the test pattern to the electronic device structure until another test pattern is built into the pattern buffer by the embedded processor such that a test of the electronic device structure includes a series of bursted patterns and stalls.