Patent ID: 7126392

Claim:
A semiconductor integrated device, comprising: a reference-clock signal generation circuit that generates a predetermined low-speed reference-clock signal used for a time base; a time base processing circuit that receives the reference-clock signal; a high-speed signal processing circuit that conducts high-speed signal processing; and a phase-locked loop circuit that generates a high-speed clock signal by multiplying a frequency of the reference-clock signal generated by the reference-clock signal generation circuit by a factor of N, and provides the high-speed signal processing circuit with the generated high-speed clock signal as a driving signal of the high-speed signal processing circuit; wherein a range of the reference-clock signal generated by the reference-clock signal generation circuit is from 10 KHz to 100 KHz inclusive, the factor N is at least 100, and the high-speed processing circuit communicates with the time base processing circuit and the phase-locked loon circuit.