Patent ID: 8381010

Claim:
A circuit for switching clocks comprising: a first input intended to receive a first clock signal at a frequency alternately equal to a first value F 1 or a second value F 2 , a second input intended to receive a second clock signal, synchronous with the said first clock signal, at a third frequency F 3 and an output intended to deliver a third clock signal without glitches at a frequency alternately equal to the said first value F 1 or to the third value F 3 , a switch receiving the first and second clock signals and delivering one or the other of said signals so as to produce the third clock signal, a “NOR” logic gate delivering a synchronization signal resulting from the “NOR” logic function between the first clock signal and the second clock signal, a frequency detector receiving the first clock signal so as to filter one of the two frequencies F 1 or F 2 of said signal and to produce a signal exhibiting a first level A when the frequency of the first clock signal is equal to F 1 and a second level B when the frequency is equal to F 2 , and a D flip-flop logic circuit receiving the synchronization signal and the signal originating from the frequency detector and producing a control signal destined for the switch driving the switching between the first and second clock signals in such a way that the third clock signal is equal to the first clock signal when the frequency of the first clock signal is equal to F 1 , and is equal to the said second clock signal when the frequency of the first clock signal is equal to F 2 .