Patent ID: 7381508

Claim:
A method of fabricating an integrated circuit semiconductor device, the method comprising: forming a first buried insulating layer and a second buried insulating layer in a first trench in a cell region and an alignment key region trench of an alignment key region, respectively, of a silicon substrate; forming a first insulating pattern and a second insulating pattern in the cell region and an overlay key region, respectively, of the silicon substrate; covering the cell region with a first photoresist pattern; forming a second trench and a third trench by etching the silicon substrate in the overlay key region and the alignment key region, respectively, by using the first photoresist pattern, the second insulating pattern and the second buried insulating layer as a mask; forming a conductive layer over the entire surface of the silicon substrate including the cell region, the overlay key region, and the alignment key region; forming a second photoresist pattern over the conductive layer by using the third trench formed in the alignment key region as an alignment key and using the second insulating pattern as an overlay key; and forming a conductive pattern by patterning the conductive layer using the second photoresist pattern as a mask, the conductive pattern formed by correcting overlay and alignment errors using the second insulating pattern.