Patent ID: 7426132

Claim:
An SRAM device having two outputs respectively coupled to two different apparatuses outside the SRAM device, comprising: a plurality of rows of SRAM cells, each row being connected to one of a plurality of word lines and a plurality of bit lines; a decoder coupled between said plurality of rows of SRAM cells and one of the two outputs, and connected to the bit lines for accessing one of the bit lines; and a row of line-buffer SRAM cells, coupled between said plurality of rows of SRAM cells and the other one of the two outputs, being connected to a read enable line and the bit lines, wherein said row of line-buffer SRAM cells is configured to allow data stored within one of said plurality of rows of SRAM cells to be duplicated to said row of line-buffer SRAM cells, wherein the plurality of rows of SRAM cells and the row of line-buffer SRAM cells form a SRAM cell array; wherein a signal on said read enable line is activated after a signal on said one of the plurality of word lines is activated, and p art of a duration of the activated signal on said read enable line overlaps with part of a duration of the activated signal on said one of the plurality of word lines.