Patent ID: 7676669

Claim:
A processor comprising: a logic block comprising a plurality of execution processing cores that are configured to operate individually and each having an internal setting register; a data register configured to maintain setting information for the internal setting register of each of the plurality of execution processing cores; a sense controller configured to perform sense control of the setting information and to maintain the internal setting register of each of the plurality of execution processing cores; a cores selection fuse device configured to set selection information of each of the plurality of execution processing cores; an interceptor configured to intercept a sense control signal to the internal setting register of each of the plurality of execution processing cores from the sense controller according to a value from the core selection fuse device; a fuse overwrite scan latch configured to overwrite a content of the core selection fuse device by connecting to an output of the core selection fuse device, and to scan setting new core selection information through a TAP controller configured to perform scan controls; and a selector being configured to make the output of the core selection fuse device, or an output of the fuse overwrite scan latch, become the input.