Patent ID: 8086936

Claim:
A memory system comprising: a memory hub device integrated in a memory module; and a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises: first error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices; second error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices, wherein the second error correction logic checks the write data from the link interface for errors; first error correction code generation logic in the write logic integrated in the memory hub device, wherein the first error correction code generation logic generates a first error correction codeword that is added to the write data before transmitting the write data to the set of memory devices; and a link interface that provides a communication pathway between the memory hub device and an external memory controller, wherein the first error correction logic and the second error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices, and wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel.