Patent ID: 7218647

Claim:
Apparatus for implementing frame header alterations in a network processor comprising: a packet buffer storing incoming packet frame data and frame information for data frames, and queuing data frames; a command decoder receiving and decoding frame alteration commands and providing frame alignment commands and alteration instructions; said frame alignment commands and alteration instructions including at least one of insert, delete and save and a position and length of each said at least one of insert, delete and save; a data aligner coupled to said packet buffer receiving frame information and frame data and coupled to said command decoder receiving said frame alignment commands; said data aligner including an insert and delete unit sequentially receiving a predefined number of bytes of frame data, selectively latching data bytes of said received frame data responsive to said frame alignment commands and sequentially providing an aligned frame data output of said predefined number of bytes; said aligned frame data output selectively including one or more inserts, and one or more deletes; said data aligner selectively providing save frame data to said command decoder responsive to said frame alignment commands; and an alteration engine coupled to said data aligner receiving said sequentially provided aligned frame data output and coupled to said command decoder receiving said alteration instructions and providing sequential altered frame data responsive to said received alteration instructions.