Patent ID: 8309453

Claim:
A method of fabricating multilevel interconnects with shielding function comprising: providing a substrate, a pixel array area and a logical circuit area defined on the substrate surface; forming a first dielectric layer on the substrate; performing a first metallizing process on the first dielectric layer to form a first patterned metal layer and a second patterned metal layer above the pixel array area and the logical circuit area respectively, wherein the second patterned metal layer comprises a plurality of first blocks positioned individually above the logical circuit area; forming a second dielectric layer on the first patterned metal layer, the second patterned metal layer, and the first dielectric layer; performing a second metallizing process on the second dielectric layer to form a third patterned metal layer and a fourth patterned metal layer above the pixel array area and the logical circuit area respectively, wherein the fourth patterned metal layer comprises a plurality of second blocks positioned individually above the logical circuit area, and interlacing with the first blocks to completely cover the logical circuit area; and depositing a planarized dielectric layer on the third patterned metal layer and the fourth patterned metal layer.