Patent ID: 8729940

Claim:
A semiconductor device comprising: a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock, the delay line including a plurality of delay units connected in series; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit, wherein the delay amount limit includes a maximum delay amount or a minimum delay amount; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line by a predetermined cycle of the source clock in response to an output signal of the clock cycle measuring unit, wherein the delay amount sensing unit is further configured to: activate a minimum delay amount sense signal in response to a bit value of the delay control code for the first delay unit, of the plurality of delay units in connected in series, and deactivate the minimum delay amount sense signal after the predetermined cycles of the source clock.