Patent ID: 7605623

Claim:
A semiconductor memory apparatus, comprising: a delay line configured to delay a reference clock; a first delay block configured to delay a feedback clock; a first phase comparator configured to compare the reference clock with an output of the first delay block; a second delay block configured to delay the reference clock; a second phase comparator configured to compare the feedback clock with an output of the second delay block; a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators; a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock; and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators, wherein the locking detector includes: a signal input block configured to recognize a locking state based on the comparison results from the first and second phase comparators; a latch block configured to latch an output of the signal input block; and a signal output block configured to output a locking state signal in response to a latched signal in the latch block.