Patent ID: 8589662

Claim:
A microprocessor for multiple instruction issue in the microprocessor, the microprocessor comprising: an instruction buffer; instruction decode and issue logic; a dependency cache, wherein the dependency cache stores information regarding data dependencies between instructions; and a plurality of functional units, wherein the instruction decode and issue logic: identifies an instruction group to be issued to the plurality of functional units in the microprocessor; determines whether a dependency cache entry that identifies predicted data dependencies between instructions in the instruction group exists for the instruction group in the dependency cache, wherein the dependency cache entry includes stored first control signals for executing the instruction group in a pipe of the microprocessor based on the predicted data dependencies between the instructions in the instruction group; uses the stored first control signals in the dependency cache entry to control execution of the instruction group in the microprocessor in response to the dependency cache entry existing for the instruction group in the dependency cache, and in parallel, the instruction decode and issue logic computes second control signals for the instruction group based on actual data dependencies between the instructions in the instruction group to form second computed control signals, compares the second computed control signals with the stored first control signals, and accepts the execution of the instruction group in the microprocessor based on the stored first control signals in response to the second computed control signals matching the stored first control signals, and, in response to the second computed control signals not matching the stored first control signals, the instruction decode and issue logic rolls back the execution of the instruction group in the microprocessor to use the second computed control signals; and computes third control signals for the instruction group to form third computed control signals and stores the third computed control signals in the dependency cache in association with the instruction group based on the actual data dependencies between the instructions in the instruction group in response to the dependency cache entry not existing for the instruction group in the dependency cache.