Patent ID: 8599208

Claim:
An arithmetic logic stage in a graphics processor unit, the stage comprising: a plurality of arithmetic logic units (ALUs) operable for performing operations using a set of input operands for a plurality of pixels comprising more than one pixel, each of the pixels in the plurality of pixels having a unique pixel number associated therewith, wherein the ALUs are programmable by an instruction that is applied to all pixels in the plurality of pixels; and a plurality of registers coupled to the plurality of ALUs and operable for storing a plurality of global values, wherein global values included in the set of input operands are readable from any register in the plurality of registers, and wherein, when the instruction designates a same destination for global values, the results of the operations are written to different destinations instead of to the same destination identified in the instruction, the different destinations selected from a designated subset of the plurality of registers, wherein a register in the designated subset is selected as a destination for receiving a result for a pixel in the plurality of pixels, the destination different from that specified in the instruction, the destination for receiving the result selected by computing a register number uniquely associated with the register, the register number computed as a function of the unique pixel number associated with the pixel and the destination specified in the instruction, the function defined so that only the result for the pixel is writeable to the register.