Patent ID: 7245531

Claim:
A semiconductor device comprising: memory cells arranged in plural array form, said each memory cell including: (a) a drain region and a source region formed in a semiconductor substrate; (b) a first gate electrode and a second gate electrode formed over said semiconductor substrate above between said drain region and said source region, said first gate electrode being positioned on said drain region side and said second gate electrode being positioned on said source region side and adjacent to said first gate electrode with a first insulating film interposed therebetween; (c) a first gate insulating film formed between said first gate electrode and said semiconductor substrate; and (d) a second gate insulating film formed between said second gate electrode and said semiconductor substrate, said second gate insulating film having a charge storage section thereinside, wherein a plurality of first gate lines connected to said first gate electrodes of said memory cells arranged in a first direction, of said plurality of memory cells, and a plurality of second gate lines being adjacent to said first gate lines through a second insulating film interposed therebetween and connected to said second gate electrodes of said memory cells arranged in said first direction, of said plurality of memory cells, are provided, and wherein said second gate lines respectively connected to said second gate electrodes of said memory cells adjacent to one another in a second direction intersecting said first direction with said source regions interposed therebetween are not electrically connected to one another, and voltages are capable of being applied thereto independently.