Patent ID: 8592301

Claim:
A template wafer fabrication process, comprising: at least one of degreasing and removing an oxide surface of a core Si wafer; depositing a Ni layer on a front side of said Si wafer based on evaporation or sputtering; depositing an Al layer onto said Ni layer on the front side based on evaporation or sputtering; depositing a Ni layer on a backside of said Si wafer based on evaporation or sputtering; depositing an Al layer onto said Ni layer on the backside based on evaporation or sputtering; depositing a nonconductive layer based on polytetrafluoroethylene up to a thickness of 20 microns to a top surface of said Al layer of said front side; depositing a nonconductive layer based on polytetrafluoroethylene to a back surface of said Al layer of said backside; applying a baking procedure to remove solvents and/or smooth exposed surfaces upon depositing of at least one of said nonconductive layers; and forming surface features on said front side to expose at least said nonconductive layer underneath, wherein said surface features are either etched or imprinted down to expose said Ni layer on said front side, yielding conductive features capable of indium plating to form indium bumps upon electroplating, wherein said evaporation can be either electron-beam or heated evaporation, and wherein said sputtering can be either AC or DC.