Patent ID: 7683662

Claim:
A logic gate for implementing complex logic within a memory array, comprising: a logic gate output node; a first input circuitry, wherein an output node is coupled to the first input circuitry, and wherein the first input circuitry receives a first storage cell signal, a second storage cell signal, and a first external signal; wherein the first input circuitry comprises: a first pull-up transistor connected to the first storage cell signal; a second pull-up transistor connected to the first external signal; a first pull-down transistor connected to the first external signal; and a second pull-down transistor connected to the second storage cell signal, wherein a drain of the first pull-up transistor is coupled to a drain of the second pull-up transistor, wherein the first pull-down transistor is coupled to the second pull-down transistor, wherein the first pull-up transistor is coupled to a drain voltage, wherein the second pull-down transistor is coupled to a ground, and wherein the second pull-up transistor is coupled to the first pull-down transistor and to the output node; a second input circuitry, wherein the output node is coupled to the second input second input circuitry, wherein the second input circuitry receives the first storage cell signal, the second storage cell signal, and a second external signal, and wherein the same first storage cell signal and the same second storage cell signal are received by both the first input circuitry and the second input circuitry; wherein the second input circuitry comprises: a first pull-up transistor connected to the second storage cell signal; a second pull-up transistor connected to the second external signal; a first pull-down transistor connected to the second external signal; and a second pull-down transistor connected to the first storage cell signal, wherein a drain of the first pull-up transistor is coupled to a source of the second pull-up transistor, wherein the first pull-down transistor is coupled to the second pull-down transistor, wherein the first pull-up transistor is coupled to a drain voltage, wherein the second pull-down transistor is coupled to a ground, and wherein the second pull-up transistor is coupled to the first pull-down transistor and to the output node; an output drive circuitry, wherein the output drive circuitry is coupled to the output node and the logic gate output node, wherein the first input circuitry and second input circuitry are operable to receive at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at their respective input circuitry; and wherein the logic gate performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal.