Patent ID: 8896323

Claim:
An apparatus comprising: an electrical power source; a plurality of comparators, each of the plurality of comparators coupled to one of: a high-side or a low-side field-effect transistor (FET) of direct current (DC)-to-DC converter, each of the plurality of comparators configured to compare an output voltage with a preset overcurrent threshold voltage, wherein the output voltage is the voltage outputted from the direct current (DC)-to(DC) converter, and each of the plurality of comparators further configured to determine whether an overcurrent event has occurred based, at least in part, upon the comparison; and a logic circuit coupled to each of the plurality of comparators, the logic circuit configured to indicate the presence of an overcurrent in response to a selected number of the plurality of comparators determining that the overcurrent event has occurred, and the logic circuit further configured to indicate the absence of the overcurrent in response to fewer than the selected number of the plurality of comparators determining that the overcurrent event has occurred, wherein the plurality of comparators includes a first comparator, a second comparator, and a third comparator, the selected number of the plurality of comparators includes two or more of the plurality of comparators, and fewer than the selected number of the plurality of comparators includes one or none of the plurality of comparators, wherein the logic circuit further includes a first AND gate, a second AND gate, a third AND gate, and an OR gate coupled to: an output of the first AND gate, an output of the second AND gate, and an output of the third AND gate, wherein an output of the first comparator is coupled to a first input of the first AND gate and to a first input of the second AND gate, an output of the second comparator is coupled to a second input of the first AND gate and to a first input of the third AND gate, and an output of the third comparator is coupled to a second input of the second AND gate and a second input of the third AND gate.