Patent ID: 7831979

Claim:
A processor comprising: memory circuitry; and processing circuitry coupled to the memory circuitry; the processing circuitry being operative to retrieve from the memory circuitry an interrupt polling instruction; the interrupt polling instruction causing: polling of one or more interrupt sources to detect a presence of one or more active enabled interrupts; and responsive to the detected presence of one or more active enabled interrupts: selection of an active enabled interrupt from the one or more active enabled interrupts; and generation of an interrupt vector for the selected active enabled interrupt; wherein in conjunction with the selection and generation operations an execution context of a program thread is stored in the memory circuitry, the stored execution context being utilizable to resume the program thread subsequent to interruption of that thread; and wherein the processor further comprises: an instruction decoder; an interrupt controller coupled to the instruction decoder; and at least one multiplexer; the instruction decoder being operative to decode the interrupt polling instruction; the interrupt controller being operative to generate the interrupt vector; the instruction decoder being operative to control the at least one multiplexer such that the interrupt vector is selected as a next instruction address to be fetched from an instruction memory of the memory circuitry, a corresponding returned instruction comprising an instruction of an interrupt handler for the selected active enabled interrupt.