Patent ID: 8125052

Claim:
An integrated circuit structure comprising: a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers comprises a top dielectric layer; a first seal ring along edges of the semiconductor chip and a second seal ring between the first seal ring and the edges of the semiconductor chip, wherein each of the first seal ring and the second seal ring comprises: a plurality of metal lines, each of the plurality of metal lines being in one of the plurality of dielectric layers, wherein the plurality of metal lines comprises a top metal line in the top dielectric layer; and a plurality of vias, each of the plurality of vias being in at least one of the plurality of dielectric layers and interconnecting adjacent ones of the plurality of metal lines, wherein the plurality of vias comprises a top via physically connected to the top metal line, and wherein at least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines; and a first passivation layer over the top dielectric layer, wherein a trench extends from a top surface of the first passivation layer into the first passivation layer to form a ring, and wherein each outer side of the second seal ring is adjacent to a respective edge of the semiconductor chip, wherein a width of the metal lines in the second seal ring is narrower than a width of the metal lines in the first seal ring in a corresponding dielectric layer.