Patent ID: 8350596

Claim:
A clock loss detection circuit, comprising: a first edge detection circuit including a first reset signal circuit coupled to a first clock input, the first reset signal circuit operable to generate a first reset signal in response to a transition of a first clock signal, the first edge detection circuit including a first multiplexer coupled to the first reset signal circuit, and a second multiplexer coupled to the first clock input; a second edge detection circuit including a second reset signal circuit coupled to a second clock input, wherein the second reset signal circuit is decoupled from the first clock input, the second reset signal circuit operable to generate a second reset signal in response to a transition of a second clock signal; and a first clock loss detect counter circuit coupled to the first edge detection circuit and the second edge detection circuit, the first clock loss detect counter circuit operable to receive the reset signal from the second edge detection circuit and the first clock signal of the first edge detection circuit.