Patent ID: 6982449

Claim:
A memory device, comprising: an array of memory cells, wherein each memory cell comprises: a control gate formed overlying a ferroelectric layer; a first source/drain region having a first conductivity type; a second source/drain region having the first conductivity type; a channel region interposed between the first and second source/drain regions and having the first conductivity type; and a well coupled to the second source/drain region and having a second conductivity type, wherein the second conductivity type is opposite the first conductivity type and wherein the well is isolated from the control gate; a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates; a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions; a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their wells; a row decoder coupled to the array of memory cells; and a column decoder coupled to the array of memory cells.