Patent ID: 7750346

Claim:
A semiconductor structure for a flat panel display, comprising: a semiconductor layer, disposed on a substrate, being provided with a source area and a drain area; a patterned first dielectric layer, disposed on the semiconductor layer; a patterned first metal layer, disposed on the patterned first dielectric layer, wherein the patterned first metal layer comprises: a gate electrode, partially disposed on the portion of the semiconductor layer; and a data line, partially disposed on the semiconductor layer; a patterned second dielectric layer, disposed on the patterned first metal layer; and a patterned second metal layer, disposed on the patterned second dielectric layer, wherein the patterned second metal layer comprises: a gate line, partially disposed on the portion of the gate electrode and electrically connected to the gate electrode; a common electrode, partially disposed on the portion of the data line; a source line, electrically connected to the source area of the semiconductor layer and the data line; and a drain line, electrically connected to the drain area of the semiconductor layer.