Patent ID: 8088682

Claim:
A method for fabricating an integrated circuit, comprising: fabricating a gate electrode level region that forms part of an overall gate electrode level of the integrated circuit, wherein fabricating the gate electrode level region includes fabricating at least three linear-shaped conductive structures each fabricated to extend lengthwise in a first direction, the at least three linear-shaped conductive structures positioned in a side-by-side spaced apart manner, wherein side-by-side ones of the at least three linear-shaped conductive structures are spaced apart from each other in a second direction perpendicular to the first direction in accordance with a substantially equal centerline-to-centerline pitch as measured in the second direction, and wherein at least two side-by-side ones of the at least three linear-shaped conductive structures are fabricated to electrically connect to each other through one or more conductive structures formed within a level of the integrated circuit other than the gate electrode level.