Patent ID: 7388801

Claim:
A memory structure comprising a plurality of address banks, each said address bank comprising a predetermined number of physical memory bits operative to store a memory address having the predetermined number of bits, said structure comprising: a first subplurality of address banks wherein the predetermined number of physical memory bits for each of the first subplurality of address banks comprises a first number of least significant memory bits that are shared between all of the first subplurality of address banks; a second subplurality of address banks wherein the predetermined number of physical memory bits for each of the second subplurality of address banks comprises a second number of least significant memory bits that are shared between all of the second subplurality of address banks; and a third subplurality of address banks wherein the predetermined number of physical memory bits for each of the third subplurality of address banks comprises a third number of least significant memory bits that are shared between all of the third subplurality of address banks.