Patent ID: 8168535

Claim:
A method of fabricating a semiconductor device comprising: sequentially forming a first insulation layer, a second insulation layer and first sacrificial layer on a substrate, wherein the second insulation layer has a high etching selectivity relative to the first sacrificial layer; forming a first opening by sequentially etching the first sacrificial layer, the second insulation layer and the first insulation layer; depositing a first conductive material on the first sacrificial layer to a thickness sufficient to fill the first opening; polishing the first conductive material until the first sacrificial layer is exposed and a first contact formed in the first opening is electrically separated from other portions of the first conductive material; forming a second sacrificial layer on the first sacrificial layer including the first contact portion; forming a second opening by sequentially etching the second sacrificial layer, the first sacrificial layer, the second insulation layer and the first insulation layer; depositing a second conductive material on the second sacrificial layer to a thickness sufficient to fill the second opening; polishing the second conductive material until the second sacrificial layer is exposed and a second contact formed in the second opening is electrically separated from other portions of the second conductive material; removing the first sacrificial layer and the second sacrificial layer to expose resultant protruding structures of the first and second contacts extending above the second insulation layer; and thereafter polishing the resultant protruding structures using the second insulation layer as a polishing stopper layer.