Patent ID: 8535998

Claim:
A method for fabricating a gate structure, comprising: depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; forming a lightly doped region in the substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a hafnium oxide sacrificial layer; surrounding the hafnium oxide sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with a contact etch stop layer (CESL); surrounding the CESL with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; substantially completely removing the hafnium oxide sacrificial layer to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric, wherein depositing the gate dielectric comprises depositing the gate dielectric along sidewalls of the nitrogen-containing layer; and depositing a gate electrode, wherein depositing the gate electrode comprises depositing the gate electrode such that the lightly doped region extends beyond an interface of the gate electrode and the gate dielectric.