Patent ID: 7531866

Claim:
A non-volatile semiconductor memory device comprising: a substrate having a surface; a plurality of memory cells formed in a matrix on the substrate, said memory cell including: a first conductive type active region formed on the surface of said substrate, a second conductive type first impurity region formed in said active region, a channel formation region formed in said active region, a second conductive type second impurity region formed in said active region such that the second conductive type first impurity region and the second conductive type second impurity region sandwich the channel formation region, a first gate insulation film which has charge storage capability and is formed closer to said first impurity region on said channel formation region, a second gate insulation film which has charge storage capability and is formed closer to said second impurity region on said channel formation region, a first gate electrode formed on said first gate insulation film, a second gate electrode formed on said second gate insulation film, and an inter-gate-electrode insulation film formed on said channel formation region, wherein the inter-gate-electrode insulation film is a three-layer film consisting of a first oxide film, a nitride film and a second oxide film, and is disposed between the first gate electrode and the second gate electrode, so that the first gate electrode is in direct contact with the first oxide film, the second gate electrode is disposed in direct contact with the second oxide film, and the nitride film is disposed between and in direct contact with the first and second oxide films; and a plurality of pairs of lines that include a bit line and a control line formed in parallel with the channel on said substrate, the pairs including a first pair, wherein: said memory cells include a plurality of memory cells that collectively form a row extending in a direction parallel to the bit line, the memory cells in the row being disposed between the bit line and the control line of the first pair, each memory cell in the row having both the first and second impurity regions, each memory cell in the row being alternately connected with the bit line or the control line of the first pair, the first gate electrode and the second gate electrode in each memory cell in the row being formed in strips in a direction perpendicular to the channel in each memory cell in the row; and two adjacent memory cells in the row are disposed, such that the second impurity region of one memory cell is disposed next to and connected with the first impurity region of the adjacent memory cell.