Patent ID: 8319256

Claim:
A FET, comprising: a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer; a source, gate and drain electrode located over the barrier layer and extending in a longitudinal direction thereon, wherein a portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa and wherein the gate electrodes extends along an edge sidewall of the mesa; a conductive source interconnect disposed over the buffer layer and having a first end electrically connected to the source electrode; a first dielectric layer disposed over the buffer layer and over the conductive source interconnect; a gate via formed in the first dielectric layer; a conductive gate node extending along the buffer layer and electrically connecting the portion of the gate electrode extending along the sidewall of the mesa; a gate pad disposed on the first dielectric layer adjacent the mesa; a conductive gate connect strip located over the conductive gate node and in contact therewith, said conductive gate connect strip being in electrical contact with the gate pad; a source via formed in the first dielectric layer; and a source pad formed in the source via, the conductive source interconnect having a second end in electrical contact with the source pad.