Patent ID: 7124340

Claim:
Method for testing a testable electronic device having a first plurality of test arrangements, a second plurality of test arrangements, a first shift register having a plurality of cells and a second shift register having a plurality of cells, each cell of the first shift register being coupled between an external pin and one of the test arrangements from the first plurality of test arrangements and each cell of the second shift register being coupled between an external pin and one of the test arrangements from the second plurality of test arrangements, the method comprising the steps of: serially communicating first test data between a first shift register and a first test data channel, and at least partially simultaneous therewith, serially communicating second test data between a second shift register and a second test data channel; and parallelly communicating the first test data between the first plurality of test arrangements and the first shift register, and at least partially simultaneous therewith, parallelly communicating the second test data between the second plurality of test arrangements and the second shift register.