Patent ID: 7566623

Claim:
A process of forming an electronic device comprising: forming a first semiconductor fin and a second semiconductor fin, wherein from a cross-sectional view, the first semiconductor fin includes a first wall and a second wall opposite the first wall; forming a first conductive member and a second conductive member each including a gate electrode material, wherein: the first conductive member includes: a first portion adjacent to the first wall; a second portion adjacent to the second wall; and a third portion overlying the first semiconductor fin and connecting the first portion and the second portion; and the second conductive member overlies the second semiconductor fin: and reacting the third portion of the first conductive member to form a first gate electrode adjacent to the first wall and a second gate electrode adjacent to the second wall, wherein: prior to reacting the third portion of the first conductive member: the third portion has a first width: and a portion of the second conductive member overlying the second semiconductor fin has a second width larger than the first width: and after reacting the third portion of the first conductive member, the second conductive member overlies the second semiconductor fin.