Patent ID: 8871548

Claim:
A method, comprising: forming a layer of material having a thickness less than 100 nanometers on a substrate; forming a first region of a first conductivity in the material; forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, forming an anode having a capacitance and a cathode with capacitance, wherein only one of the anode capacitance or the cathode capacitance is non-zero at a given time; depositing a layer of gate dielectric on the layer of material; arranging a metal gate adjacent the channel region on the gate dielectric such that the gate avoids overlapping the first and second regions; and electrically connecting a voltage source to the gate, the voltage source being operable either positively or negatively, wherein a polarity of the voltage determines a gate bias polarity, the gate bias polarity determining which of the anode capacitance or the cathode capacitance is non-zero at the given time.