Patent ID: 8580625

Claim:
A method for manufacturing a MOS transistor, comprising: forming a substrate, the substrate defining a first transistor region and a second transistor region and having a first opening and a second opening formed by removing a dummy gate, the substrate comprising a high-k dielectric layer and a barrier layer on the high-k dielectric layer in each of the first opening and the second opening; forming a dielectric barrier layer on the substrate to fill into the first opening and the second opening and to cover the barrier layer; removing a first portion of the dielectric barrier layer in the first transistor region so as to expose the barrier layer in the first opening; forming a first work function metal layer on the substrate after removing the portion of the dielectric barrier layer in the first transistor region to fill into the first opening and the second opening; removing the first work function metal layer in the second transistor region; removing a second portion of the dielectric barrier layer in the second transistor region so as to expose the barrier layer in the second opening; and forming a second work function metal layer on the substrate after removing the second portion of the dielectric barrier layer in the second transistor region to fill into the first opening and the second opening.