Patent ID: 7230873

Claim:
An array core , comprising: an array of bitcells, wherein each bitcell in the array of bitcells has a bitcell pulldown device that is configured to be activated by a read wordline signal to generate a read bitline; and a global pulldown device that is connected to a given read bitline and configured to be activated by a global bitline pulldown signal, wherein a given bitcell within the array of bitcells is selected using the read wordline signal and wherein the given bitcell is connected to the given read bitline; wherein the bitcell pulldown device of the given bitcell pulls down the given read bitline if a value stored in the given bitcell is zero; and wherein responsive to the global bitline pulldown signal being asserted, the global pulldown device pulls down the given read bitline regardless of the value stored in the given bitcell.