Patent ID: 8445940

Claim:
An integrated circuit device comprising: a semiconductor substrate; a gate stack disposed over the semiconductor substrate; another gate stack disposed over the semiconductor substrate; spacers disposed on sidewalls of the gate stack; a lightly doped source and drain (LDD) region in the semiconductor substrate, the LDD region being interposed by the gate stack; another LDD region in the semiconductor substrate adjacent the another gate stack, the another LDD region having a topmost surface; an epitaxially (epi) grown source and drain (S/D) region in the semiconductor substrate, the epi S/D region being interposed by the gate stack, wherein the epi source region and the epi drain region are each defined by a first facet and a second facet of the semiconductor substrate in a first direction and a third facet of the semiconductor substrate in a second direction; and another epi grown S/D region in the semiconductor substrate, the another epi S/D region having a bottommost surface physically contacting the topmost surface of the another LDD region.