Patent ID: 7447870

Claim:
A device of data characteristic identification for flash memory, comprising: an instruction register, connected to a control instruction end of a flash memory access control circuit for storing high level data access control instructions issued from the flash memory access control circuit; a data register, connected between a data bus of the flash memory access control circuit and a data bus of a flash memory for storing data to be written to the flash memory or data read from the flash memory; an address register, connected between an address bus of the flash memory access control circuit and an address bus of the flash memory for storing high level logical address of the flash memory access control circuit or physical address of access of the flash memory; a microprocessor, connected to the instruction register for receiving the high level data access control instruction to the flash memory from the flash memory access control circuit, and acting as a core for data access control and program execution for the flash memory; a plurality of auxiliary controllers, connected to the microprocessor for assisting the microprocessor in communicating with other elements, one of the auxiliary controllers being connected between the microprocessor, and the data register and the address register for data and address exchange between the microprocessor and the data register and the address register; a plurality of hash function units, each hash function unit having an input end and an output end, the input end being connected to the address register for receiving the high level logical address of the flash memory access control circuit for a hash computation, and the output end for outputting the results of the hash computation; a hash table unit, connected to the output end of each hash function unit, further comprising a plurality of counters forming a hash table, for an initial index from the output end of the hash function unit to find the corresponding counter in the hash table to determine whether data in a logical address being frequently updated; a comparator, connected between one of the auxiliary controllers and the hash table unit, for determining several most significant bits of a specific counter in the hash table of the hash table unit being all zero in order to determine whether the data in the flash memory being frequently updated; a shifter, connected between one of the auxiliary controllers and the hash table unit, for shifting values in the counters in the hash table of the hash table unit one bit to the right, and filling the left most bit with zero; and an adder, connected between one of the auxiliary controllers and the hash table unit, for updating by adding 1 to the values in the counters in the hash table of the hash table unit.