Patent ID: 7889786

Claim:
Apparatus for use in a reduced clock rate finite impulse response filter comprising: i) Q latch means all coupled to an input data signal having a unit interval rate and each latch means providing a latched output signal in response to a latch control signal; ii) Q multiplexer/multiplier, mux/mul, meats, each mux/mul means providing one output and Q inputs to receive the latched output signal of a respective latch means; iii) selection means for controlling said mux/mul means operative to produce an output signal selected from one of said Q inputs; iv) means to produce a clock signal; and v) Q phase delay means coupled to said clock signal providing an output latch control signal to a corresponding latch means; wherein each phase delay means is adapted to produce a unique output latch control signal that is phase delayed from the clock signal by a phase delay of N×360/Q, where unique values of N correspond to each individual phase delay means and range from 0 to Q−1, wherein Q is an integer greater than 1.