Patent ID: 8073995

Claim:
An efficient low latency buffer comprising: a first data path connection and a control path connection to a discontinuous interface, to transfer data intermittently; a second data path connection to a continuous interface, to transfer data continually; a memory buffer for storing data; and a control unit having a first mode and second mode of operation, each mode using a first pointer indicating a fill position in the memory buffer and a second pointer indicating a read position in the memory buffer, wherein: in the first mode of operation the control unit intermittently signals to the discontinuous interface over the control path connection to provide a segment of data of a first predetermined size over the first data path connection to be stored in the memory buffer at a position ahead of the first pointer, and wherein the control unit intermittently signals the discontinuous interface at a first rate; and in the second mode of operation the control unit intermittently signals to the discontinuous interface over the control path connection to read and replace a segment of data of a second predetermined size less than the first predetermined size over the first data path connection at the position in the memory buffer ahead of the first pointer and wherein the control unit intermittently signals the discontinuous interface at a second data rate greater than the first data rate; wherein the continuous interface reads and replaces a block of data stored in the memory buffer over the second data path connection at a position indicated by the second pointer.