Patent ID: 7057232

Claim:
A semiconductor structure, comprising: a substrate; a memory element comprising a gate including a gate oxide layer on the substrate, a floating gate, and a control electrode capacitively coupled to the floating gate, wherein a signal for controlling the memory element is applicable to the control electrode, wherein the floating gate comprises a first floating gate portion and a second floating gate portion connected with each other, the first floating gate portion being formed on the gate oxide layer, the second floating gate portion being laterally and vertically shifted from the first floating gate portion, and wherein the control electrode and the second floating gate portion are disposed opposite to each other with an oxide layer therebetween; and a plurality of metallization layers formed in a portion above the memory element and fully covering the floating gate, wherein at least one of the metallization layers is used as a shield layer for the floating gate, wherein in case the distance of the control electrode to the surface of the substrate is smaller than the distance of the second floating gate portion to the surface of the substrate, the shield is formed by connecting a metallization layer farthest from the second floating gate portion to the substrate, and wherein in case the distance of the second floating gate portion to the surface of the substrate is lower than the distance of the control electrode to the surface of the substrate, the shield is formed by connecting a metallization layer closest to the control electrode to the substrate.