Patent ID: 7428603

Claim:
A device comprising: a memory interface adapted to be coupled to a direct memory access (DMA) controller via a data bus and further adapted to be coupled to at least a first memory device and a second memory device via a data interface, the memory interface comprising: a first state machine including a first chip select interface, a first ready/busy interface, and a first channel to the DMA controller, the first state machine configured to select and monitor the first memory device via the first chip select interface and the first ready/busy interface, respectively, when the first memory device is coupled to the data interface; and a second state machine including a second chip select interface, a second ready/busy interface, and a second channel to the DMA controller, the second state machine configured to select and monitor the second memory device via the second chip select interface and the second ready/busy interface, respectively, when the second memory device is coupled to the data interface.