Patent ID: 7196890

Claim:
An ESD protection circuit comprising: a timing circuit operably coupled to a high supply side node and a low supply side node, and having an RC node; a first inverter operably coupled to the high supply side node and the low side supply node, and having a control node coupled to the RC node, and an output node; a second inverter operably coupled to the high supply side node and the low side supply node, and having a control node and an output node; a first feedback transistor operably coupled to the high supply side node and the output node of the first inverter, and having a control terminal coupled to the output node of the second inverter; a second feedback transistor operably coupled to the low supply side node and the output node of the first inverter, and having a control terminal coupled to the output node of the second inverter; a feedback control circuit operably coupled between the output node of the first inverter and the control node of the second inverter; an ESD dissipation device predriver stage coupled to the output node of the second inverter, and coupled to the input node of an ESD dissipation device; an ESD dissipation device operably coupled to the high supply side node and the low side supply node, and having a control node coupled to the output node of the ESD dissipation device predriver; and wherein the feedback control circuit further comprises a NMOS transistor and a PMOS transistor operably coupled between the output node of the first inverter and the control node of the second inverter, the NMOS transistor having a control terminal coupled the high side supply node, and the PMOS transistor having a control terminal coupled the output node of the second inverter and a well terminal coupled to the high side supply node.