Patent ID: 7039795

Claim:
An apparatus for processing data, the apparatus comprising: a first multiplexer operable to receive data and to perform a selected one of a plurality of first multiplexer operations on the data such that a first output is produced, said plurality of first multiplexer operations including a pass operation passing said received data unchanged to said first output and a plurality of bit rearrangement operations in which each bit in said first output except a most significant bit and a least significant bit are in a different bit position than in said received data; a second multiplexer coupled to the first multiplexer and operable to receive the first output from the first multiplexer and to perform a selected one of a plurality of second multiplexer operations on the first output such that a second output is produced, said plurality of second multiplexer operations including a pass operation passing said first output from said first multiplexer unchanged to said second output and a plurality of bit duplication operations in which a selected bit or bits in said first output is duplicated in a corresponding block of contiguous bits in said second output; and a logic unit coupled to the second multiplexer and operable to receive the second output from the second multiplexer and to generate a result that reflects the first and second outputs produced by the first and second multiplexers respectively.