Patent ID: 7420790

Claim:
A semiconductor integrated circuit comprising: a plurality of input and output terminals, and two or more kinds of protection circuits against electrostatic discharge having different parasitic capacitances from each other as different electrical characteristics thereof, wherein a first protection circuit of said two or more kinds of protection circuits is connected to one of said plurality of input and output terminals through which a first signal having a first frequency passes, and has a first parasitic capacitance, wherein a second protection circuit of said two or more kinds of protection circuits other than said first protection circuit is connected to another of said plurality of input and output terminals through which a second signal having a second frequency lower than the first frequency passes, and has a second parasitic capacitance larger than the first parasitic capacitance, wherein said first protection circuit comprises a plurality of diode-connected transistors connected in series and having the first parasitic capacitance, wherein said second protection circuit comprises a plurality of diode-connected transistors connected in series and having the second parasitic capacitance, the number of diode-connected transistors in said second protection circuit being less than the number of diode-connected transistors in said first protection circuit, and wherein any adjacent transistors of said plurality of diode-connected transistors in said first protection circuit are isolated from one another by a silicon dioxide layer as an insulator so that all of said diode-connected transistors connected in series in said first protection circuit are isolated from each other by the silicon dioxide layer and so that sufficient isolation is provided to avoid thyristor operation of these transistors.