Patent ID: 7804330

Claim:
An adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said keeper comprising: i. keeper PMOS transistor (M 1 ) wherein drain of M 1 connected to WIDE AND-OR logic circuit; ii. rate controller consisting of reference rate transistor (M 4 ), feedback PMOS transistor (M 2 ), feedback shutoff transistor (M 5 ), clock shutoff transistor (M 6 ) and the pre-charge transistor (M 3 ), iii. wherein input of the rate controller is directly connected to the drain of the keeper PMOS (M 1 ) and output of the rate controller connected to gate terminal of the keeper PMOS transistor (M 1 ).