Patent ID: 8415998

Claim:
A PLL circuit, comprising: a phase comparator configured to compare phases of a reference clock and a feedback clock, and output a phase comparison signal indicating a difference between the phases; a charge pump circuit configured to, during a time period corresponding to the difference in phases indicated by the phase comparison signal, output a first charge pump current and a second charge pump current, generate the first charge pump current over a longer time period than the second charge pump current when the phase difference indicated by the phase comparison signal is positive, and generate the first charge pump current over a shorter time period than the second charge pump current when the phase difference is negative; a loop filter including a capacitor storing electric charge based on the first and second charge pump currents, and configured to generate a control voltage due to stored electric charge, one of the first and second charge pump currents being a charging current which charges the capacitor; and the other one of the first and second charge pump currents being a discharging current which discharges the capacitor; an oscillator configured to generate an output clock at a frequency according to the control voltage; a frequency divider configured to frequency-divide the output clock and output the feedback clock; and a charge pump adjustment circuit configured to, when in a locked state, adjust current quantity of the first or the second charge pump current such that the difference in current values of the first and second charge pump currents is suppressed and the phase difference is suppressed, according to the phase difference indicated by the phase comparison signal.