Patent ID: 7126401

Claim:
An integratable, controllable delay device, comprising: an input connection for an input signal to be delayed; an output connection for a delayed output signal; a control connection for a control signal, the control connection controlling the delay time and having two or more bits; at least a first and a second multiplexer, each having a respective first and a respective second input connection and a respective output connection, the multiplexers being connected in series by the second connection of a third multiplexer being connected to the output of a second multiplexer and by the respective first connections of the multiplexers being coupled to the input connection, with a fifth multiplexer being coupled to the output connection, at least one of the at least first and second multiplexers having: a first, a second, a third, and a fourth current paths, each path respectively including a first switch connected to one of the inputs of the respective multiplexer, and a respective second switch connected to a line of a control connection, which is associated with one bit of the control signals; the current paths each being coupled to a resistance element, the first and the second current paths being connected to a current source, the third and the fourth current paths being connected via a resistance element to the current source, with the resistance element and the second switches third and in the fourth current paths being controllable.