Patent ID: 7929369

Claim:
A semiconductor memory device, comprising: a memory cell array having at least one memory bank, the memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block, each memory block including a plurality of memory cells, each memory cell associated with at least one bit line and at least one word line; and a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block, wherein the at least one edge memory block is configured such that the refresh operation involves a plurality of word lines, and the refresh execution circuit is configured to perform the refresh operation on the memory cells in the edge memory block in a first and second stage, and configured to activate a first number of the plurality of word lines one at a time in the first stage and to activate a second number of the plurality of word lines one at a time in the second stage, such that each of the plurality of word lines is activated during the refresh operation.