Patent ID: 8384418

Claim:
A system for protecting an input/output (I/O) pin of an integrated circuit device (IC) from single event transients, the system comprising: a first delay circuit comprising an input coupled to a clock source of the IC, wherein the first delay circuit is configured to delay a clock signal from the clock source by a first predetermined amount of time; a second delay circuit comprising an input coupled to the clock source, wherein the second delay circuit is configured to delay the clock signal by a second predetermined amount of time; a first register comprising an input coupled to the I/O pin, wherein the first register is clocked by the clock signal; a second register comprising an input coupled to the I/O pin, wherein the second register is clocked by the clock signal delayed by the first predetermined amount of time; a third register comprising an input coupled to the I/O pin, wherein the third register is clocked by the clock signal delayed by the second predetermined amount of time; and a first plurality of voter circuits, wherein each voter circuit is configured to receive a first data signal from an output of the first register, a second data signal from an output of the second register, and a third data signal from an output of the third register, wherein the first plurality of voter circuits comprises a first voter circuit, a second voter circuit, and a third voter circuit, wherein the system further comprises: a fourth register coupled to an output of the first voter circuit; a fifth register coupled to an output of the second voter circuit; and a sixth register coupled to an output of the third voter circuit, wherein the fourth register, the fifth register, and the sixth register each is clocked by a rising edge of the clock signal, wherein the clock signal provided to each of the fourth, fifth, and sixth registers is time aligned.