Patent ID: 8686415

Claim:
A semiconductor device comprising: a first memory cell comprising: a first transistor; a second transistor; and a first capacitor; a second memory cell comprising: a third transistor; a fourth transistor; and a second capacitor; a first word line; a second word line; a first bit line; a second bit line; a third bit line; a fourth bit line; a ramp voltage generator circuit; a fifth transistor; and a sixth transistor, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the first bit line, wherein a gate of the first transistor is electrically connected to the first word line, wherein one of a source and a drain of the second transistor is applied to a first voltage, wherein the other of the source and the drain of the second transistor is electrically connected to the second bit line, wherein a gate of the second transistor is electrically connected to a first electrode of the first capacitor, wherein a second electrode of the first capacitor is electrically connected to the second word line, wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the third bit line, wherein a gate of the third transistor is electrically connected to the first word line, wherein one of a source and a drain of the fourth transistor is applied to the first voltage, wherein the other of the source and the drain of the fourth transistor is electrically connected to the fourth bit line, wherein a gate of the fourth transistor is electrically connected to a first electrode of the second capacitor, wherein a second electrode of the second capacitor is electrically connected to the second word line, wherein one of a source and a drain of the fifth transistor is electrically connected to the first bit line, wherein the other of the source and the drain of the fifth transistor is electrically connected to an output terminal of the ramp voltage generator circuit, wherein one of a source and a drain of the sixth transistor is electrically connected to the third bit line, and wherein the other of the source and the drain of the sixth transistor is electrically connected to the output terminal of the ramp voltage generator circuit.