Patent ID: 7558722

Claim:
A method for detecting double shift errors in at least one scan chain of flip-flops in a simulation of a digital integrated circuit chip, said method comprising: initializing the output of each flip-flop in said at least one scan chain to a unique symbol; clocking said each flip-flop with a common clock signal, said common clock signal providing a clock pulse used to shift a binary digital symbol from an input of a first flip-flop to an output of said first flip-flop, said clock pulse used to shift said unique symbol from said output of said first flip-flop to an output of a second flip-flop, wherein said binary digital symbol is not equivalent to said unique symbol, and said first flip-flop and said second flip-flop comprise a pair of contiguous flip-flops in said at least one scan chain; comparing said output symbol of said first flip-flop to said output symbol of said second flip-flop within said at least one scan chain after said clocking by said clock pulse has occurred; and declaring a double shift error between said first flip-flop and said second flip-flop if said output symbol of said second flip-flop is equivalent to said output symbol of said first flip-flop after said clocking.