Patent ID: 7418555

Claim:
A multiprocessor system comprising: a plurality of processors respectively having at least one cache memory; a memory unit with at least one data block that is sharable by at least two of the processors; a directory memory storing information indicating the processors that share the at least one data block; and a control unit connected between the processors and the directory memory, the control unit forwarding an interrupt signal to a first one of the processors when the information in the directory memory indicates that the first one of the processors shares the at least one data block, and when the control unit receives an access request for the at least one data block of the memory unit from a second one of the processors, wherein the access request for the at least one data block of the memory unit is associated with a write request, wherein the at least one data block is stored in the respective cache memory of the first one of the processors, and wherein the first one of processors invalidates the at least one data block stored in the respective cache memory after receiving the interrupt signal.