Patent ID: 7457972

Claim:
A chipset for a computer system having a CPU, a monitor, and a system memory coupled to the CPU, the CPU comprising at least a memory controller controlling access to the system memory, a deep power saving state and at least a shallow power saving state, the chipset comprising: a south bridge; and a north bridge coupled to the south bridge, the CPU, and the monitor, the north bridge comprising: a state machine coupled to the CPU; and a graphics data buffer coupled to the state machine and the monitor, wherein when the CPU is in the deep power saving state and the state machine detects that graphics data stored in the graphics data buffer is insufficient, the state machine sends an NB control signal to the memory controller of the CPU to access data stored in the system memory without changing the deep power saving state of the CPU, and wherein the state machine comprises: a first multiplexer for selectively outputting either a state signal of the graphics data buffer or an SB control signal according to the state signal; a second multiplexer for selectively outputting either what the first multiplexer outputs or an NB−1 control signal according to a counting control signal output from a down counter; and a flip-flop having an input end coupled to an output end of the second multiplexer for outputting the NB control signal based on a control clock, the NB control signal traveling to an input end of the second multiplexer to become the NB−1 control signal.