Patent ID: 7108946

Claim:
A method of fabricating an integrated circuit on a wafer using dual mask exposure lithography, comprising: forming a photo resist layer over the wafer; aligning the wafer with respect to a lithography system using a reference mark that is formed on the wafer; exposing the photo resist layer with a first mask image defined by a first mask using the lithography system, the first mask image including a latent image alignment mark that is transferred to the photo resist layer; re-aligning the wafer with respect to the lithography system using the latent image alignment mark resulting from the exposure to the first mask image; exposing the photo resist layer with a second mask image defined by a second mask using the lithography system; and enhancing detectability of the latent image alignment mark to an alignment sensor, wherein the enhancing includes developing a portion of the photo resist layer after exposure by the first mask image to establish a latent image alignment mark edge in the photo resist layer.