Patent ID: 8014202

Claim:
A non-volatile semiconductor memory device comprising: a memory array which includes: a plurality of non-volatile memory cells arranged in an array extending in X and Y directions, for storing data by locally accumulating electric charge; a plurality of word lines extending in the X direction in a region where the plurality of non-volatile memory cells are provided; and a plurality of bit lines and a plurality of main bit lines extending in the Y direction in the region where the plurality of non-volatile memory cells are provided, wherein: the memory array includes one or more usable regions which can store data, and one or more isolation regions which cannot store data, the one or more isolation regions are arranged in parallel to a bit-line direction, isolating the one or more usable regions from each other, the plurality of bit lines and the plurality of main bit lines are provided in the one or more usable regions, each of the plurality of bit lines is connected via a first select transistor to a corresponding one of the plurality of main bit lines, a first isolation region bit line is provided in the one or more isolation regions, and at least a first main bit line of the plurality of main bit lines is connected via a corresponding first select transistor to the first isolation region bit line in addition to a corresponding one of the plurality of bit lines provided in the one or more usable regions.