Patent ID: 6928534

Claim:
In a microprocessor that manages interlock conditions for load instructions and that supports speculative and out-of-order execution of load instructions, a method of bypassing data to younger instructions, comprising: identifying a source register upon whose contents a current instruction depends for execution; providing a load annex, the load annex having a plurality of sequential load entries, each of the plurality of sequential load entries being capable of storing data associated with the source register, wherein each load entry is associated with one of a plurality of sequential priority levels, the plurality of sequential priority levels comprising a highest priority level and a lowest priority level; storing, in the sequential entries of the load annex, a plurality of load data associated with a particular register, wherein the plurality of load data associated with the particular register are stored in program order with respect to each other; providing a non-load annex, the non-load annex having a plurality of non-load entries, each of the plurality of non-load entries being capable of storing data associated with the source register, wherein each entry of the non-load annex is associated with one of the plurality of sequential priority levels; providing that, at most, only one among the load entry associated with a particular priority level and the non-load entry associated with the particular priority level contains a value associated with the source register; locating, among the plurality of load annex entries and the plurality of non-load annex entries, a freshest value associated with the source register; and providing the freshest value for use in execution of the current instruction.