Patent ID: 8850168

Claim:
A processor apparatus comprising: a plurality of processors which execute a plurality of programs, switchin the programs; at least one hardware resource which includes a register for holding register data and complements execution of an instruction to be executed by each of said processors; a memory for storing extension context data for each program among the programs that includes a predetermined instruction for using said at least one hardware resource, the extension context data being a copy of the register data in said at least one hardware resource; a first determination unit configured to determine whether or not there is a possibility that the extension context data of one of the programs that is currently executed is held in said at least one hardware resource; and a second determination unit configured to determine whether or not the extension context data in said at least one hardware resource belongs to one of said processors that has attempted to execute the predetermined instruction, wherein said at least one hardware resource executes the predetermined instruction, without performing the save and restore of the extension context data between said at least one hardware resource and said memory, when the execution of the predetermined instruction is attempted, and when said first determination unit determines that there is the possibility and said second determination unit determines that the extension context data in said at least one hardware resource belongs to said one of said processors that has attempted to execute the predetermined instruction, and said at least one hardware resource is an extended calculation unit configured to execute an extended instruction that is not executable by said processors, and the predetermined instruction is the extended instruction.