Patent ID: 7849339

Claim:
A method of providing clocking for data transfer comprising: generating a reference clock signal with a reference clock component; switching to a first setting in response to a signal at a first value for a first data transfer requiring high-speed clocking; generating a first clock signal for a data transfer circuit in the first setting, generation of the first clock signal including: enabling a phase-locked loop component, disabling a clock divider component coupled with the reference clock component in the first setting; applying the reference clock signal to the phase-locked loop component, and generating a high-speed clock signal using the phase-locked loop component based on the reference clock signal, and utilizing the high-speed clock signal to provide clocking for the data transfer circuit; switching to a second setting in response to the signal at a second value for operation that does not require high-speed clocking; and generating a second clock signal for the data transfer circuit in the second setting, generation of the second clock signal including: enabling the clock divider component in the second setting to divide the frequency of the reference clock signal using the clock divider component; disabling the phase-locked loop component, and utilizing the reference clock signal to provide clocking for the data transfer circuit.