Patent ID: 7953960

Claim:
A processor implemented method for flushing a register access instruction from a pipeline functional unit having a plurality of stages, wherein each stage in the plurality of stages has an associated dependency tracking register in a plurality of dependency tracking registers, coupled to circuit logic of the stage, the method comprising: detecting a register access instruction in an issue stage targeting a register; detecting a load of the register in a subsequent stage, the load being issued to the pipeline functional unit prior to issuing the register access instruction; in response to detecting the register access instruction in the issue stage and detecting the load of the register in the subsequent stage, marking a bit as a marked bit in a first dependency tracking register associated with the issue stage, wherein each dependency tracking register in the plurality of dependency tracking registers has a separate bit associated with each stage in the plurality of stages of the pipeline functional unit, and wherein the marked bit is a bit, in the first dependency tracking register, corresponding to the subsequent stage thereby identifying the register access instruction as being dependent upon the load, wherein the marked bit is associated with the issue stage and the subsequent stage; propagating the register access instruction from the issue stage to a third stage; propagating the marked bit from the first dependency tracking register to a second dependency tracking register, in the plurality of dependency tracking registers, associated with the third stage; responsive to propagating the register access instruction to the third stage, propagating the register access instruction to a flush stage; responsive to propagating the marked bit to the third stage, propagating the marked bit to the flush stage; and responsive to propagating the register access instruction to the flush stage and responsive to propagating the marked bit to the flush stage, flushing the register access instruction from the pipeline functional unit so that the register access instruction is not propagated to a next stage prior to reaching a final stage.