Patent ID: 7017068

Claim:
A system comprising: a host clock device having a host clock (HOLK) output signal; said HCLK output signal coupled to an input signal of a phase locked loop (PLL) device and an input signal of a memory controller; a main memory array coupled to said memory controller by way of a memory bus, said memory array comprising at least one memory module; a PLL output clock signal coupled to said memory controller, said memory controller reads data on said memory bus responsive to said PLL output clock signal; said PLL device having a feedback path, the length of said feedback path controls the phase relationship between the input signal of the PLL device and the PLL output clock signal; a feedback delay circuit coupled within the feedback path of the PLL device, the feedback delay circuit comprising: a first signal path having a first length, said first signal path selectable by a first FET having its drain coupled to a first end of the first signal path, and a second FET having its source coupled to a second end of the first signal path; a second signal path having a length longer than said first length, said second signal path selectable by a third FET having its drain coupled to a first end of the second signal path, and a fourth FET having its source coupled to a second end of the second signal path; gate connections of the first and second FETs coupled to each other, and further coupled to at least one control signal; gate connections of the third and fourth FETs coupled to each other, and further coupled to the at least one control signal; and wherein the feedback delay circuit, responsive to the at least one control signal, implements a short feedback path using the first signal path when said first and second FETs are in a conductive mode, and said feedback delay circuit further implements a long feedback path using the second signal path when said third and fourth FETs are in a conductive mode.