Patent ID: 8634242

Claim:
A method of fabricating a memory device, the method comprising: forming peripheral circuitry on a substrate; depositing a dielectric layer over the peripheral circuitry and the substrate, wherein said peripheral circuitry is disposed between said substrate and said dielectric layer; successively forming each of a plurality of memory arrays over the dielectric layer to form a stack of memory arrays, each of the memory arrays on a different vertical level such that said memory arrays on different vertical levels are staggered with each of said memory arrays extending into a different horizontal position; and forming a first set of contacts extending through a topmost memory array level to provide electrical connections to each of the plurality of memory array levels and one or both of the peripheral circuit and external circuitry, wherein the contacts contact said memo arrays in regions of said memory arrays without horizontal overlap between said memory arrays; and forming at least one of a second set of contacts extending from external circuitry and in contact with each of said memory arrays to provide electrical connections to each of the plurality of memory array levels and one or both of the peripheral circuit and external circuitry.