Patent ID: 7157338

Claim:
A method for manufacturing a semiconductor power device, comprising: identifying an active region on a semiconductor die, the active region having a central portion, a first peripheral portion disposed about a periphery of said central portion, and a second peripheral portion disposed about a peripheral region of said first peripheral portion; identifying a first region in said central portion of said active region; identifying a second region in said first peripheral portion of said active region; identifying a third region in said second peripheral portion; fabricating active cells in accordance with a first cell design in said first region; fabricating active cells in accordance with a second cell design in said second region, wherein an operational current density of said active cells fabricated according to said second cell design is greater than that of said active cells fabricated according to said first cell design, and fabricating active cells in accordance with a third cell design in said third region, wherein an operational current density of said active cells fabricated according to said third cell design is greater than that of said active cells fabricated according to said second cell design.