Patent ID: 8598002

Claim:
A method for manufacturing a metal gate stack structure in gate-first process, comprising: Step 1) forming an interface layer of SiOx or SiON by rapid thermal annealing at 600-800° C. for 20-120 s or by chemical processing with O 3 , after making conventional LOCOS or STI isolations; Step 2) depositing a high-K gate dielectric film; Step 3) thermal annealing at 600-1050° C. for 4-120 s after the high-K gate dielectric film is deposited; Step 4) forming a metal gate electrode by depositing a TiN gate by Physical Vapor Deposition; Step 5) depositing a barrier layer of AlN or TaN by Physical Vapor Deposition; Step 6) depositing a poly-silicon film and a hard mask by low-pressure Chemical Vapor Deposition, and then performing photo-lithography and the etching of the hard mask; and Step 7) etching the poly-silicon film/AlN or TaN barrier layer/TiN metal gate/high-K gate dielectric film sequentially by using the etched hard mask as a mask, to form the metal gate stack structure, wherein the poly-silicon is etched by F based plasma+Cl based plasma or HBr+Cl based plasma; the plasma etching of the Aln or TaN barrier metal layer, the TiN metal gate and the high-K gate dielectric film is performed by using BGl 3 and Cl, as main etching gases with one or both of O 2 and Ar added as supplementary etching gases to improve etching characteristics.