Patent ID: 8769457

Claim:
A method of data processing, comprising: after a global placement phase of physical design of an integrated circuit, a computer processor iteratively performing intermediate placement by: during each iteration of intermediate placement, iteratively refining local placement of a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules until a module density threshold is satisfied; during each iteration of intermediate placement, separately iteratively refining local wirelength for the plurality of modules in individual subareas among a plurality of subareas of the die area until a wirelength threshold is satisfied; determining whether placement of the plurality of modules has converged; in response to determining that placement of the plurality of modules has not converged, continuing the intermediate placement by performing said refining local placement and said refining local wirelength in another iteration of intermediate placement; in response to determining that placement of the plurality of modules has converged, ending said iteratively performing intermediate placement; and after performing intermediate placement, performing detailed placement of modules in the plurality of subareas to obtain a placed physical design.