Patent ID: 8435898

Claim:
A method of forming a first inter-layer dielectric on a semiconductor structure, comprising: forming a plurality of device components comprising transistors with one or more contact regions on the semiconductor structure; forming an etch stop layer over the plurality of device components; forming a dielectric gap fill layer of undoped dielectric material over the etch stop layer to fill in regions between the transistors; applying a chemical mechanical polish process to planarize the dielectric gap fill layer down to a substantially planar surface; forming a dielectric gettering layer over the substantially planar surface of the dielectric gap fill layer by depositing a BPTEOS layer, PTEOS layer or BTEOS layer or a combination thereof to provide a mobile ion barrier layer which actively performs a gettering function; and selectively etching the dielectric gettering layer and the dielectric gap fill layer to expose the etch stop layer over one or more contact regions in one or more device components.