Patent ID: 8914681

Claim:
An apparatus, comprising: an integrated circuit, comprising: logic analyzer circuitry having a first input receiving a plurality of signals from one or more portions of the apparatus under test, the plurality of signals being available to the logic analyzer circuitry for sampling and event triggering, and a first output for providing selected samples of the plurality of signals appearing at the first input; and a first block having a first input coupled to the logic analyzer circuitry for receiving one or more of the plurality of signals appearing at the first input thereof, and circuitry for generating a distinct set of one or more test signals based upon the one or more of the plurality of signals appearing at the first input of the first block according to a predetermined function, the predetermined function being configurable, the distinct set of one or more test signals being different from the plurality of signals received by the logic analyzer circuitry and from the one or more plurality of signals received by the first block, appearing at an output of the first block, and being provided to the logic analyzer circuitry for at least one of sampling of the distinct set of one or more test signals and event triggering; wherein the first input of the first block is coupled to the first output of the logic analyzer circuitry such that the first block receives one or more of the selected samples of the plurality of signals appearing at the first input of the logic analyzer circuitry, and generates the distinct set of one or more test signals based upon the one or more selected samples.