Patent ID: 8035200

Claim:
A semiconductor structure comprising: (a) a semiconductor layer; (b) a charge accumulation layer on top of the semiconductor layer; (c) a doped region in direct physical contact with the semiconductor layer; and (d) a device layer on and in direct physical contact with the charge accumulation layer, wherein the charge accumulation layer comprises trapped charges of a first sign, wherein the doped region and the semiconductor layer form a P−N junction diode, wherein the P−N junction diode comprises free charges of a second sign opposite to the first sign, wherein the trapped charge in the charge accumulation layer exceeds a preset limit, above which semiconductor structure is configured to malfunction, wherein a first voltage is applied to the doped region, a second voltage is applied to the semiconductor layer, and a third voltage is applied to the device layer, and wherein the third voltage exceeds the first voltage and the second voltage, which accelerates the free charges toward the device layer to enable some of the free charges to enter the charge accumulation layer and neutralize some of the trapped charges in the charge accumulation layer.