Patent ID: 8842232

Claim:
A thin film transistor with a parasitic capacitance compensation structure, comprising a gate terminal, an insulation layer formed on the gate terminal, a first semiconductor silicon layer formed on the insulation layer, a source terminal formed on the first semiconductor silicon layer, and a drain terminal, the drain terminal being partially located on the insulation layer and the first semiconductor silicon layer, the drain terminal and the gate terminal overlapping each other via the insulation layer to form a first overlap region and also overlapping each other via the first semiconductor silicon layer and the insulation layer to form a second overlap region, the first overlap region and the second overlap region respectively generating a first parasitic capacitance and a second parasitic capacitance, the thin film transistor further comprising a compensation structure, whereby when the drain terminal is shifted with respect to the gate terminal, the compensation structure keeping an area of the first overlap region and an area of the second overlap region unchanged; wherein the drain terminal is of a T-shape, which comprises a first body and a second body perpendicular to the first body, the first body having one end arranged on the first semiconductor silicon layer and an opposite end arranged on the insulation layer, the gate terminal forming a through hole in a portion corresponding to the second body of the drain terminal, the compensation structure being arranged to correspond to said one end or said opposite end of the first body.