Patent ID: 8212303

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate including a first region in which a memory cell transistor is arranged, a second region in which an electrode that extracts a word line electrically connected to the memory cell transistor is arranged, and a third region in which a peripheral transistor is arranged, the semiconductor substrate including an element isolation layer which separates adjacent active regions; first active regions provided in the first region and each having a first width; a first stacked film including a tunnel insulating film and a floating gate electrode stacked on each of the first active regions; second active regions provided in the second region and each having a second width greater than the first width; a second stacked film including the tunnel insulating film and the floating gate electrode stacked on each of the second active regions; third active regions provided in the third region and each having a third width greater than the first width; a third stacked film including the tunnel insulating film and the floating gate electrode stacked on each of the third active regions; an intergate insulating film provided on the floating gate electrode and the element isolation layer; a control gate electrode provided on an intergate insulating film in the first and second regions and corresponding to the word line; and a gate electrode provided on an intergate insulating film in the third region, wherein an upper surface of an element isolation layer in the second region is higher than an upper surface of an element isolation layer in the first region, and a curvature radius of a corner of an upper portion of the floating gate electrode of the second stacked film is greater than that of the floating gate electrode of the third stacked film.