Patent ID: 7990192

Claim:
A phase locked loop (PLL), comprising a phase detector (PD), a filter, a voltage-controlled oscillator (VCO), and a frequency divider that are electrically connected in turn, wherein two input ports of the PD are respectively connected to a reference frequency signal and a frequency division signal from an output port of the frequency divider; a signal from the PD is converted to a voltage signal after the signal passes through the filter and is inputted to the VCO; a clock signal generated by the VCO is sent to the frequency divider to obtain the frequency division signal; the PLL further comprising a charge circuit to charge the filter by sending a capacitor voltage to the filter, wherein the charge circuit comprises: a threshold judging module, configured to output a valid signal to a receiving module, when the capacitor voltage reaches a preset threshold; the receiving module, configured to receive a trigger signal and output a first control signal to a charging module according to the trigger signal and output a second control signal to the charging module when the receiving module receives the valid signal; and the charging module, configured to charge the filter when the first control signal is received and stop charging the filter when the second control signal is received.