Patent ID: 8315349

Claim:
A phase detector for generating logic signals indicative of phase transitions of an input data stream with respect to a reference clock signal, the phase detector comprising: a first bit-storage device for sampling the input data stream with the reference clock signal; a second bit-storage device for sampling the input data stream with a first phase shifted clock signal whose phase is delayed by X degrees relative to the reference clock signal; a third bit-storage device for sampling the input data stream with a second phase shifted clock signal whose phase is delayed by Y degrees relative to the reference clock signal, to generate a logic signal “C”; and fourth and fifth bit-storage devices for sampling outputs of the first and second bit-storage devices respectively to generate logic signals “A” and “B” respectively; wherein the first, second, and third bit-storage devices respectively comprise first, second, and third combinations of first and second transparent latches, wherein an output of the first transparent latch is coupled to an input of the second transparent latch in each of the respective combinations; and wherein the first transparent latch is a high or low latching transparent latch, and the second transparent latch is a respective low or high latching transparent latch.