Patent ID: 7657758

Claim:
A processing apparatus comprising: an internal circuit comprising: a CPU executing programs, said CPU is supplied with a first clock and executes the programs synchronously with the supplied first clock, and, at least one internal device having a predetermined function, and a bus line extending internally of the internal circuit and connecting said CPU to said internal device, the bus line comprising an externally extending portion extending externally of the internal circuit and an address bus and a data bus transferring an address and data, respectively, wherein said internal circuit includes at least one internal memory as an internal device, the internal memory storing a program for determining ciphering patterns; and an external circuit provided externally of the internal circuit and connected with the externally extending portion of said bus line and including at least one external device having a predetermined function, wherein said external circuit includes at least one external memory as an external device, wherein said internal circuit further comprises a ciphering section interposed at an entrance to an external side of said internal circuit, and ciphering the address and the data on the bus line by the ciphering patterns according to a plurality of regions divided from an address space allotted to entirety of said at least one external device, to thereby prevent illicit access to the internal memory via the external memory, said ciphering section is supplied with a second clock and performs ciphering synchronously with the supplied second clock and a clock supply section for supplying the second clock at a higher speed than a speed of the first clock supplied to said CPU, to said ciphering section, so that one of the ciphering patterns that is made by using a result of one of other ciphering patterns among the ciphering patterns can be employed.