Patent ID: 6930352

Claim:
An insulated gate semiconductor device comprising: a first semiconductor layer of a first conductivity type; a plurality of second semiconductor layers of a second conductivity type selectively formed on a surface of the first semiconductor layer of the first conductivity type; at least one third semiconductor layer of the first conductivity type selectively formed on a surface of each of said plurality of second semiconductor layers of the second conductivity type; a plurality of first main electrodes connected to said plurality of second semiconductor layers of the second conductivity type and said at least one third semiconductor layer of the first conductivity type, respectively; a fourth semiconductor layer of the first conductivity type formed on a rear surface of the first semiconductor layer of the first conductivity type; a second main electrode connected to the fourth semiconductor layer of the first conductivity type; at least one control electrode formed via a gate insulation film on the surface of the first semiconductor layer of the first conductivity type, including said plurality of second semiconductor layers of the second conductivity type and said at least one third semiconductor layer of the first conductivity type; at least one fifth semiconductor layer of the second conductivity type disposed on an interface of the first semiconductor layer of the first conductivity type in contact with said at least one control electrode, and connected to at least one of said plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layer having impurity concentration lower than that of said plurality of second semiconductor layers of the second conductivity type; and a ninth semiconductor layer of the first conductivity type provided between the first semiconductor layer of the first conductivity type and the fourth semiconductor layer of the first conductivity type.