Patent ID: 8537151

Claim:
An inspection method for an active-matrix substrate including a plurality of scanning lines, a plurality of data lines, a plurality of pixels each disposed at an intersection of one of the scanning lines and one of the data lines, and a power line for supplying current to the pixels, wherein each of the pixels includes: a light-emitting device which emits light according to a flow of a drive current corresponding to a data voltage supplied through one of the data lines; a drive transistor which is connected between the power line and the light-emitting device and which converts the data voltage into the drive current, according to a voltage applied to a gate electrode of the drive transistor; a capacitor which has one electrode connected to the gate electrode of the drive transistor and which holds a voltage corresponding to the data voltage; a first transistor having (i) a gate electrode connected to one of the scanning lines and (ii) one of a source electrode and a drain electrode connected to the gate electrode of the drive transistor; a second transistor having (i) a gate electrode connected to the one of the scanning lines, (ii) one of a source electrode and a drain electrode connected to the other of the source electrode and the drain electrode of the first transistor, and (iii) the other of the source electrode and the drain electrode connected to the one of the data lines; a third transistor having (i) a gate electrode connected to the one of the source electrode and the drain electrode of the first transistor, (ii) a source electrode connected to the other of the source electrode and the drain electrode of the first transistor, and (iii) a drain electrode connected to a first potential line; and a fourth transistor having a gate electrode connected to a drain electrode that is connected to the other of the source electrode and the drain electrode of the first transistor, and a source electrode connected to a second potential line, the inspection method comprising: writing a charge in the capacitor; reading the written charge from the capacitor; and holding the charge for a predetermined period from an end of the writing to a start of the reading, wherein in the holding, the charge is held for a period equal to or longer than a period based on a time constant defined by an off resistance of the first transistor, an off resistance of the second transistor, and the capacitor.