Patent ID: 7315483

Claim:
A semiconductor memory device comprising: a pad; a power supply voltage generating circuit configured to generate a plurality of power supply voltages; and a voltage selection circuit configured to select one of the power supply voltages in response to test mode signals and to provide the selected power supply voltage to the pad, the voltage selection circuit including: a voltage level regulating circuit configured to convert voltage levels of the test mode signals to generate gate control signals; and a plurality of metal-oxide semiconductor (MOS) transistors, each connected to one of the power supply voltages and configured to be turned on in response to a corresponding gate control signal of the gate control signals and to provide the selected power supply voltage to the pad, wherein the voltage level regulating circuit includes a plurality of level-shifters, each connected to a gate electrode of one of the plurality of MOS transistors, and configured to generate the corresponding gate control signal in response to a corresponding test mode signal.