Patent ID: 7490200

Claim:
A method of operating a cache memory in a given level of a multilevel cache hierarchy, comprising: logically partitioning a cache array of the cache memory into at least first and second slices wherein the first slice contains a first plurality of bytes arranged in at least a first row of the cache array and the second slice contains a second plurality of bytes arranged in at least a second row of the cache array, the first plurality of bytes and the second plurality of bytes further being arranged in columns defining common sectors; receiving a load request at a controller of the cache memory, the load request including an address for a requested memory block, and the controller having a first directory associated with the first slice and a second directory associated with the second slice; feeding the address to each of the rows in the cache array; delivering the address selectively to only one of the first and second directories based on a setting of a designated bit in the address; matching the address to an entry in the selected one of the first and second directories and responsively sending an enable signal from the selected one of the first and second directories to a corresponding one of the first and second rows; and successively powering the sectors of the cache array to pipeline the requested memory block to an output of the cache array using a single cache arbiter of the cache controller.