Patent ID: 7729096

Claim:
A semiconductor integrated circuit, comprising: a functional circuit having a signal terminal and a pair of power terminals; and an ESD protection circuit having a first terminal and a second terminal connected to said signal terminal and one of said power terminals, respectively, wherein said ESD protection circuit includes: a first MOSFET having a drain connected to said first terminal, a gate connected to said second terminal and a source connected to said second terminal, and a second MOSFET formed adjacent to said first MOSFET and having the same conductivity type as said first MOSFET, said second MOSFET having a source, gate, and drain, the source, gate, and drain of the second MOSFET all being connected to said first terminal, wherein said functional circuit includes at least one additional MOSFET, wherein said first MOSFET, said second MOSFET, and said at least one additional MOSFET each have an SOI structure formed on a silicon substrate, and wherein said gate of said second MOSFET is connected to said first terminal via a resistance region.