Patent ID: 8013317

Claim:
A nonvolatile storage device comprising: a plurality of unit memory layers; and a plurality of layer selection transistors, wherein the plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers, wherein each of the unit memory layers includes: a plurality of first wirings, a plurality of second wirings provided non-parallel to the plurality of first wirings, and a recording layer provided between the plurality of first wirings and the plurality of second wirings, wherein each of the plurality of layer selection transistors is connected to each of one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, wherein the plurality of layer selection transistors are configured to collectively select some of the one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, the selected some being disposed in a common plane, and wherein the layer selection transistors include a channel along a direction perpendicular to the layer surface of the unit memory layers, and can collectively select the some in a plane perpendicular or parallel to the layer surface.