Patent ID: 7767523

Claim:
A manufacture method for a non-volatile semiconductor memory device, comprising the steps of: (a) forming an isolation region in a semiconductor substrate to define a non-volatile memory area including a plurality of stripe shaped first active regions and a peripheral circuit area including second active regions; (b) forming first electrode layers above said first active regions, each of said first electrode layers having such a shape that said first electrode layers cover said first active regions, extend above said isolation region, are separated from each other and do not reach said peripheral circuit area, and forming an inter-electrode insulating film having such a shape that said inter-electrode insulating film covers said first electrode layer and do not reach said peripheral circuit area; (c) forming a second electrode layer above a whole surface of said semiconductor substrate, said second electrode layer covering said inter-electrode insulating film; (d) patterning said second electrode layer, said inter-electrode insulating film and said first electrode layer in said non-volatile memory area to form gate electrodes having such a shape that said control gates traverse intermediate areas of said first active regions, while completely leaving said second electrode layer in said peripheral circuit area; (e) forming first insulating side walls on side walls of said gate electrode in said non-volatile memory area and forming a first redundant insulating side wall on a side wall of said second electrode layer in said peripheral circuit area; and (f) patterning said second electrode layer in said peripheral circuit area to form single-layer gate electrodes and leaving said second electrode layer adjacent to said first redundant insulating side wall.