Patent ID: 8368571

Claim:
A pipelined analog-to-digital converter (ADC) circuit, comprising: a pipeline stage having an ADC to convert an analog input to a digital output of a predetermined bit-width, a first plurality of digital-to-analog converters (DACs) sufficient in number to produce an analog output corresponding to the digital output, and a second plurality of DACs configured to have their output added into the analog output, wherein the first pipeline stage produces an amplified analog residue from the analog output; a succeeding pipeline portion that converts the amplified analog residue to at least one second digital output and a digitized residue; a mapping circuit to selectively exchange inputs to a selected one of the first plurality of DACs and one of the second plurality of DACs; a calibration signal circuit to provide first and second calibration signals to inputs of the selected one of the first plurality of DACs and another of the second plurality of DACs, wherein the first and second calibration signals are correlated to each other, but uncorrelated to the analog input and digital output of the pipeline stage, and have unequal effects on at least one of: the amplified analog residue, or the digitized residue; and a correction circuit to correct the digital output of the pipeline stage for circuit path errors, including gain errors and component-value mismatch errors, in circuit paths including the first plurality and second plurality of DACs, based on the results of a correlation of the calibration signals to at least one of: the at least one second digital output, or the digitized residue.