Patent ID: 8751748

Claim:
In a multiprocessor system comprising a plurality of processors running speculative threads in parallel; and at least one cache shared by the processors, a method comprising: in a control unit of the cache, maintaining a dynamic record of read accesses to the cache, the record comprising for each cache line a format specification indication specifying a reader encoding format responsive to occurrence of a type of read access, said type including transactional memory (TM), thread level speculation (TLS) and rollback, the record comprises an identification of which speculative thread or threads has read a particular cache line, said identification in the form of a field that encodes thread identification numbers of a group of threads, wherein each bit of said field represents a group of IDs, an aggregate of all IDs is represented as the aggregate of all bits of the field; and a bit set in the field representing the cache line has been read by at least one ID of a corresponding group; directing memory accesses for a same physical address from any of the processors through a same memory addressing scheme of the control unit; abrogating recordation of portions of lines read responsive to one or more of: more than two speculative TM threads have read from the line, a mix of TM and TLS threads have read from the line, and TLS threads from different domains have read from the line; and performing conflict checking for all the processors of the system using the record to locate potential conflicts.