Patent ID: 7688110

Claim:
A Complementary Metal-Oxide Semiconductor (CMOS) Emitter Coupled Logic (ECL) output circuit having an input and an output, wherein the input is arranged to receive an input signal from a CMOS circuit and the output is arranged to provide an output signal to an ECL circuit, the CMOS ECL output circuit comprising: a CMOS differential amplifier having first and second inputs and an output; a reference circuit arranged to provide a reference voltage to the first input of the CMOS differential amplifier, wherein the reference voltage varies based on a temperature of the CMOS ECL output circuit; a feedback loop coupled between the output of the CMOS differential amplifier and the second input of the CMOS differential amplifier, the feedback loop carrying a signal to maintain the output signal of the ECL circuit at about the same level as the reference voltage, wherein the output signal varies in about the same manner as the reference voltage varies due to temperature changes; wherein the CMOS differential amplifier is disabled when the input signal from the CMOS circuit and the output signal provided to the ECL circuit is a logic low; and wherein a first device drives the output of the CMOS ECL output circuit when the input signal from the CMOS circuit and the output signal provided to the ECL circuit is a logic low, and wherein a second device different than the first device drives the output of the CMOS ECL output circuit when the input signal from the CMOS circuit and the output signal provided to the ECL circuit is a logic high.