Patent ID: 7672160

Claim:
A non-volatile semiconductor memory device, comprising: a memory array including first and second memory cells and first and second word lines respectively coupled to the first and second memory cells wherein the first and second word lines are different word lines; a page buffer configured to map data of a set of first, second, and third bits to threshold voltage levels of the first and second memory cells during a write operation; a row decoder configured to control the first word line and the second word line respectively applied to the first memory cell and the second memory cell during a read operation, to respectively apply a first reference voltage and a second reference voltage to the first memory cell and the second memory cell simultaneously during the read operation, the first reference voltage and the second reference voltage having different voltage levels wherein the first reference voltage is lower than the second reference voltage; a first bit line connected to the first memory cell; and a second bit line connected to the second memory cell.