Patent ID: 7275228

Claim:
A method for designing a programmable logic device, the method comprising: assigning each of a plurality of circuit elements to a separate abstract block, wherein the circuit elements are part of a user design for a programmable integrated circuit and each abstract block represents a functional attribute of its assigned circuit element; placing a respective one or more of the abstract blocks into each of a plurality of logic blocks based at least in part on a correspondence between a functional attribute of a particular logic block and the functional attribute of a respective abstract block placed into that logic block, wherein a first abstract block is placed into a first logic block, wherein placing a respective one or more of the abstract blocks into each of a plurality of logic blocks includes: determining whether placing an abstract block assigned to a particular circuit element into a specific logic block violates any of a set of design rules relating to that specific logic block, wherein the logic blocks are grouped into clusters; and determining whether placing the abstract block into a cluster containing that specific logic block violates any of a set of design rules relating to that cluster; removing the first abstract block from the first logic block in response to placement information that indicates a design goal would be improved by rearranging at least a portion of the user design, wherein the design goal includes at least one of routability and signal timing in the user design; and placing the first abstract block into a second logic block on the programmable integrated circuit, wherein the functional attribute of the first abstract block corresponds with a functional attribute of the second logic block, thus improving the design goal.