Patent ID: 8405413

Claim:
An integrated circuit, comprising: a functional logic circuit for providing a function of the integrated circuit, wherein the functional logic circuit has a critical path having a critical path delay; a pulse generation circuit for generating a pulse having a rising edge and a falling edge; a critical path synthesizer circuit having an input coupled to an output of the pulse generation circuit and having at least one delay path for providing synthesized delay indicative of at least a portion of the critical path delay; a monitoring circuit having an input coupled to an output of the critical path synthesizer circuit, for measuring a relative delay through at least one delay path of a single one of the rising edge or falling edge of the pulse and providing a first real-time output indicative of the measured relative delay; and a data output circuit having an input coupled to an output of the monitoring circuit and having selectable operating modes, wherein a processed result is computed from the measured relative delay according to the selected operating mode and provided as a second processed output indicative of the measured relative delay.