Patent ID: 6838345

Claim:
A method of fabricating a silicon nitride read only memory, comprising: providing a substrate; forming a silicon oxide layer on the substrate; forming a charge capture layer on the silicon oxide layer; forming an isolation region in the charge capture layer to partition the charge capture layer into a plurality of charge capture blocks arranged in an array with a plurality of rows extending from one predetermined bit line to another predetermined bit line, and a plurality of columns each having n (n is a positive integer) charge capture blocks; forming a stacked dielectric layer on the charge capture layer in a reaction chamber; patterning the stacked dielectric layer and the charge capture layer to expose regions of the substrate predetermined for forming the bit lines; forming the bit lines in the substrate at two sides of the charge capture layer; forming a control gate on the stacked dielectric layer; and performing a threshold voltage adjustment step allowing channel regions under the charge capture blocks of different rows to have different threshold voltages.