Patent ID: 7401358

Claim:
A method of controlling accesses to control register zero (CR 0 ) of a processor configured to operate in a normal execution mode and a secure execution mode, said method comprising: storing state and mode information in said (CR 0 ); protection logic allowing a software invoked write access to modify said state and mode information within said (CR 0 ) during operation in said normal execution mode; security logic selectively inhibiting said software invoked write access during operation in said secure execution mode; determining whether control bits, within said CR 0 , which said software invoked write access is attempting to modify, are safe to modify in a normal kernel mode of said secure execution mode; wherein said normal kernel mode includes a current privilege level state being equal to zero within a code segment descriptor corresponding to a currently executing code sequence during operation in said secure execution mode, but not in a trusted execution mode; allowing said software invoked write access to proceed in response to determining that said control bits that said software invoked write access is attempting to modify, within said CR 0 , are safe in said normal kernel mode; inhibiting said software invoked write access from proceeding and generating a security exception in response to determining that said control bits within said CR 0 are not safe in said normal kernel mode; and enabling the secure execution mode during operation in the normal execution mode by executing a secure operating system code segment that has been validated using a separate security processor that is external to the processor.