Patent ID: 7817240

Claim:
A thin film transistor array substrate, comprising: a substrate; a plurality of scan lines disposed over the substrate; a plurality of data lines disposed over the substrate, wherein the scan lines and the data lines together define a plurality of pixel areas; a plurality of thin film transistors with each thin film transistor disposed inside one of the pixel areas, wherein each thin film transistor is driven by one of the scan lines; a plurality of pixel electrodes with each pixel electrode disposed inside one of the pixel areas and electrically connected to one of the thin film transistors and each pixel electrode having a plurality of openings; a plurality of common lines disposed over the substrate, wherein a portion area of each pixel electrode is disposed above one of the common lines; and a patterned upper electrode disposed between each pixel electrode and one of the common lines, wherein the patterned upper electrode comprises a plurality of sub-upper electrodes with a portion area of each sub-upper electrode electrically connected to one of the pixel electrodes, and each opening of the pixel electrode is disposed above one sub-upper electrode, respectively.