Patent ID: 8365027

Claim:
A processor comprising: an arithmetic device; a storage device that holds arithmetic data to be supplied to the arithmetic device; a data generator that generates a test pattern to be written to the storage device; an address generator that generates an address of the storage device at which the test pattern is to be written; a test pattern number counter that counts a number of the test pattern every time the data generator generates the test pattern; an error information holder that holds mismatch error information; an error occurrence bit position holder that holds position information of a bit in the test pattern at which a mismatch error has occurred; an error occurrence test pattern number information holder that holds the number of test pattern counted by the test pattern number counter in accordance with test pattern in which a mismatch error has occurred; and a comparator that compares the test pattern written to the storage device with test data read from the storage device, stores error information in the error information holder when a mismatch error has occurred as a result of the comparison, stores position information of a bit at which the mismatch error has occurred in the error occurrence bit position holder, and that stores the number of the test pattern in which the mismatch error has occurred in the error occurrence test pattern number information holder.