Patent ID: 7714638

Claim:
A multi-threshold MOS (MTMOS) transistor arrangement comprising: a subject circuit including low threshold-voltage transistors for which leakage current is to be controlled; and a current cut-off (CCS) switch circuit including, an MOS transistor having a gate and a body and a terminal connected to a system ground voltage, and a governor circuit connected to the gate, the body, a system supply voltage and the system ground voltage for generating a body-bias voltage for the MOS transistor, and for varying a maximum magnitude of the body-bias voltage based on the magnitude of the gate voltage of the MOS transistor; wherein the maximum magnitude of the body bias voltage is varied such that the maximum magnitude is equal to one of the gate voltage of the MOS transistor and a first threshold voltage of the governor circuit, the first threshold voltage is less than the gate voltage of the MOS transistor, and the subject circuit and the CCS switch circuit are serially connected between the system-supply voltage and the system ground voltage.