Patent ID: 8677215

Claim:
A controller for a multi-level, solid-state, non-volatile memory having memory cells, the memory cells configured to store data using a first number of digital levels, the controller comprising: a first encoder configured to generate second data, in response to first data, for storage in the multi-level, solid-state, non-volatile memory, wherein voltages of the memory cells that are programmed to a first level of the digital levels are described by a first probability density function having a first width, voltages of the memory cells that are programmed to a second level of the digital levels are described by a second probability density function having a second width, the first width is greater than the second width, and the first encoder is configured to reduce a first frequency of the first level in the second data compared to a second frequency of the second level in the second data; and an analog-to-digital converter configured to, in response to one of the memory cells of the multi-level, solid-state, non-volatile memory, output a respective digital signal, wherein the respective digital signal is selected from a second number of digital levels that is greater than the first number of digital levels.