Patent ID: 8799748

Claim:
A non-volatile semiconductor memory device comprising: a memory unit including a plurality of memory cells, each of the plurality of memory cells to perform a multi-level storage operation by assigning a value including a plurality of bits to at least four data states defined according to a threshold level; and a controller to control the memory unit, wherein the controller sets at least one of the plurality of bits to an error correction bit that indicates one of a first state and a second state; assigns the first state to the error correction bit that corresponds to the data states having a minimum threshold level and a maximum threshold level and the second state to the error correction bit that corresponds to the data states having other threshold level; sets the error correction bit to the first state when writing data in at least one of the plurality of memory cells; and resets the error correction bit to the first state if the error correction bit indicates the second state when reading the error correction bit periodically.