Patent ID: 8331138

Claim:
A memory cell consisting: a first electromechanical device having a first terminal, a second terminal, and a third terminal, the first terminal of the first electromechanical device connected to a first movable nanoscopic element, the third terminal of first electromechanical device connected to a common output node; a second electromechanical device having a first terminal, a second terminal, and a third terminal, the first terminal of the second electromechanical device connected to a second movable nanoscopic element, the third terminal of the second electromechanical device connected to the common output node, the first and second electromechanical devices operate to store one bit; a transistor having a first terminal, a second terminal, and a third terminal connected commonly to the third terminal of the first electromechanical device, the third terminal of the second electromechanical device, and the common output node; a first wordline extending in a first direction and connected to the first terminal of the first electromechanical device; a second wordline extending in a first direction and parallel to the first wordline, the second wordline connected to the first terminal of the second electromechanical device; a first bitline extending in a second direction, the first bit line connected to the second terminal of the first electromechanical device; a second bitline extending in a second direction and parallel to the first bitline, the second bitline connected to the second terminal of the electromechanical device; and a conductor extending in a second direction and parallel to the first and second bitlines, the conductor connected to the first terminal of the first transistor.