Patent ID: 7173838

Claim:
A semiconductor device, comprising: an I/O circuit provided between a plurality of first signal lines and a plurality of second signal lines; an encoding circuit having input terminals to which said plurality of second signal lines are connected; a decoding circuit having output terminals to which said plurality of second signal lines are connected; and a plurality of memory arrays, wherein said I/O circuit transmits and receives first information based on a first mapping and second information based on a second mapping, wherein said encoding circuit outputs third information encoded from said first information or said second information to said plurality of memory arrays, wherein said decoding circuit outputs said first information or said second information generated by decoding said third information received from said plurality of memory arrays to said I/O circuit, wherein said memory arrays store said third information and compare said stored third information with said third information newly inputted, and wherein said stored third information and said newly inputted information are outputted from the same output node of said encoding circuit.