Patent ID: 7435661

Claim:
A method of fabricating an electrical isolation device, the method comprising: forming a first dielectric layer on a first surface of a substrate; forming a second dielectric layer over the first dielectric layer, the second dielectric layer being comprised of a substantially harder material than the first dielectric layer; etching though a portion of the first and second dielectric layers, thereby exposing a portion of the first surface of the substrate; etching a shallow trench into the substrate in a region substantially circumscribed by the exposed portion of the first surface of the substrate, the shallow trench having exposed sidewalls and a bottom region, the bottom region being substantially parallel with the first surface; depositing a third dielectric layer, the third dielectric layer filling the shallow trench and covering at least a portion of the second dielectric layer; planarizing the third dielectric layer to a level substantially coplanar with an uppermost surface of the second dielectric layer; forming a fourth dielectric layer over the second dielectric layer and the planarized third dielectric layer, the fourth dielectric layer being comprised of a material having a comparable hardness value as the second dielectric layer; etching through the third and fourth dielectric layers in a region substantially circumscribed laterally by the shallow trench; etching into the substrate in the region substantially circumscribed laterally by the shallow trench, the step of etching into the substrate thereby forming a deep trench in the substrate; and depositing a fifth dielectric layer, the fifth dielectric layer filling the deep trench and covering at least a portion of the fourth dielectric layer.