Patent ID: 7964457

Claim:
A manufacturing method for a semiconductor device, comprising the steps of: providing a semiconductor substrate layer of a first conductivity type; forming a first impurity diffusion layer of a second conductivity type on a part of the semiconductor substrate layer; forming a silicon oxide film on the first impurity diffusion layer; forming a gate insulating film on a region of the semiconductor substrate layer where the silicon oxide film is not formed; exposing a silicon surface of the first impurity diffusion layer by removing a part of the silicon oxide film; depositing polycrystalline silicon on the exposed silicon surface of the first impurity diffusion layer and on the gate insulating film, and connecting the silicon surface of the first impurity diffusion layer to the polycrystalline silicon; introducing impurities of the second conductivity type to the polycrystalline silicon; subjecting the polycrystalline silicon to patterning to separate a gate electrode on the gate insulating film and a polycrystalline silicon drain region on the first impurity diffusion layer from each other; forming a second impurity diffusion layer of the second conductivity type adjacent to the first impurity diffusion layer; forming a contact hole for electrical connection of the second impurity diffusion layer; and depositing a wiring metal layer into the contact hole to form therein a drain electrode that is electrically connected to the second impurity diffusion layer and that is disposed apart from and not in contact with the polycrystalline silicon drain region.