Patent ID: 8841190

Claim:
A method of manufacturing a PMOS device, the method comprising the following steps: providing an initial structure, which includes a substrate, an active region having a channel region and formed in the substrate, and a gate stack formed above the channel region; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer on both sides of the gate stack; performing self-aligned dry etching, with the first spacer as a mask, thereby forming a recess, with the amorphous material layer below the first spacer remaining; performing wet etching using an etching solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or equal to the etch rate to the {100} and {110} surfaces of the substrate material but is greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first spacer, such that the substrate material below the amorphous material layer is exposed to the solution and is etched thereby, and in the end, forming a Sigma shaped recess that extends to the active region below the gate stack; and epitaxially forming SiGe in the Sigma shaped recess.