Patent ID: 6868430

Claim:
An arithmetic unit for allocating a linear analog output obtained from a detector using a predetermined number of discrete levels (2 n ), comprising: an A/D converter to convert the analog output from the detector into a digital value (Dx); a memory to store an upper limit value A and a lower limit value B of the digital value (Dx) as predetermined values; and a controller for perform the following processing steps: (1) when the digital value (Dx) is A(a 1 ), which exceeds the upper limit value A, updating the upper limit value stored in the memory to A(a 1 ); (2) computing a virtual lower limit value B(a 1 ) from the upper limit value A(a 1 ) in accordance with the slope of a linear function determined by the preset upper limit value A and the preset lower limit value B and updating the lower limit value stored in the memory to the lower limit value B(a 1 ); and (3) computing an operation output D by calculating the following equation with respect to a subsequently-obtained digital value (Dx): D =(2 n )×{ Dx−B ( a 1 )}/{ A ( a 1 )− B ( a 1 )}.