Patent ID: 8181072

Claim:
A method for testing a main memory in a multi processor system including a main processor and a plurality of sub processors each having a DMA transfer mechanism and a local store, the method comprising: the main processor allocating a partial memory region in a test target memory region of the main memory to each of the plurality of sub processors; the main processor requesting each of the plurality of sub processors to test the allocated partial memory region; each of the plurality of sub processors, in response to receiving the request from the main processor, filling the local store thereof with initial data; each of the plurality of sub processors transferring the filled initial data from the local store thereof to the allocated partial memory region by using the DMA transfer mechanism; each of the plurality of sub processors transferring data from the partial memory region, which has received the filled initial data, to the local store of the sub processor by using the DMA transfer mechanism; each of the plurality of sub processors, after the completion of transferring the data to the local store, testing the local store thereof by checking if the value of the data in the local store which has received the data in the transfer from the partial memory region matches the value of the initial data; and the main processor, in response to the completion of testing the local store for all the plurality of sub processors, judging a test result on the test target memory region of the main memory by putting together results of the tests on the respective local stores wherein each of the plurality of sub processors testing the local store thereof includes each of the plurality of sub processors checking if a checksum value matches an expected checksum value calculated in advance from the initial data, by sequentially adding pieces of the data having been transferred to the local store by a predetermined unit to obtain a checksum; and wherein each of the plurality of sub processors includes means for executing an M-byte SIMD Add instruction, and calculating a checksum includes each of the plurality of sub processors: adding a first M-byte data and a second M-byte data byte by byte by using the SIMD Add instruction; calculating a final M-byte addition data by repeating the adding through the entire region of the local store; and adding each byte of the final M-byte addition data.