Patent ID: 7098722

Claim:
A low power fuse control logic circuit, comprising: a control section having a first and a second input and a common node, said first input receiving a power-up signal having a logical “0” or “1”, said first input coupled to the control gate of a first switching means, said second input coupled to the control gate of a second switching means, where first terminals of said first and said switching means are coupled to a positive terminal of a power supply, where the second terminals of said first and said second switching means are tied to said common node, where said control section controls the state of said fuse control logic circuit as a function of said first input, and where the width-to-length ratio of said second switching means versus said first switching means ranges from 20:1 to 5:1; a blocking section with a third switching means, said third switching means having first and second terminals and a control gate, where said first terminal of said third switching means is coupled to said common node, said control gate of said third switching means coupled to said first input of said control section, where said blocking section blocks DC paths in said control section during a power-up sequence, and where the width-to-length ratio of said third switching means versus said second switching means ranges from 10:1 to 2:1; a fuse section comprising fusible means, one end of said fusible means coupled to said second terminal of said third switching means, the other end of said fusible means coupled to a return terminal of said power supply, said fuse section controlling the voltage level at said second terminal of said blocking section; and a driver section having an input and an output terminal, said driver section comprising inverting means coupled between said common node and said output terminal of said driver section, said driver section coupled further to said control gate of said second switching means, said output terminal of said driver section signaling the state of said fuse control logic circuit.