Patent ID: 8294257

Claim:
A power block comprising: an insulating substrate; a conductive pattern formed on said insulating substrate; a power semiconductor chip bonded onto said conductive pattern by lead-free solder; a first buffering conductor bonded onto said power semiconductor chip; a plurality of electrodes electrically connected to said power semiconductor chip and extending upwardly away from said insulating substrate, at least one of said plurality of electrodes is bonded onto said first buffering conductor such that a portion of said at least one of said plurality of electrodes is arranged directly over the power semiconductor chip; and a transfer molding resin covering said conductive pattern, said lead-free solder, said power semiconductor chip, and said plurality of electrodes, wherein surfaces of said plurality of electrodes are exposed at an outer surface of said transfer molding resin and lie in the same plane as said outer surface, said outer surface being located directly above said conductive pattern.