Patent ID: 8015386

Claim:
A configurable memory manager, comprising: a first plurality of ports, each port of the first plurality arranged to receive requests for accessing a plurality of memories, and each port of the first plurality being independently configurable to specify one of a first plurality of data widths of the port; a second plurality of ports, each port of the second plurality arranged to access a respective one of the memories, each port of the second plurality being independently configurable to specify one of a second plurality of data widths of the port; a translator configured to translate a virtual address of each of the requests into an identifier of one of the memories and a physical address in the memory; wherein the translator is configurable to associate each port of the second plurality with any one of a plurality of translation look-aside buffers, each translation look-aside buffer configured to translate the virtual address of each request into the physical address for the associated port; and a switch coupled to the translator and to the first and second pluralities of ports, the switch, responsive to the identifier translated from a request received at a port of the first plurality, arranged to transfer the physical address translated from the request to a port of the second plurality for accessing the memory identified by the identifier.