Patent ID: 7338852

Claim:
A method of simultaneously forming at least one capacitor, at least two resistors and at least one metal-oxide semiconductor, comprising the steps of: providing a structure having an exposed oxide structure; the structure having a capacitor region within at least a portion of the exposed oxide structure; a first resistor region within at least a portion of the exposed oxide structure; a second resistor region within at least a portion of the exposed oxide structure; and a metal-oxide semiconductor region not within at least a portion of the exposed oxide structure; forming a doped first polysilicon layer over the structure and the exposed oxide structure; forming an interpoly oxide film over the doped first polysilicon layer; patterning the interpoly oxide film to form: a capacitor interpoly oxide film portion within the capacitor region over the oxide structure; and a second interpoly oxide film portion within the second resistor region over the oxide structure; forming a doped second polysilicon layer over the structure; and patterning the doped second polysilicon layer and the doped first polysilicon layer to simultaneously form: within the capacitor region: a lower capacitor doped first polysilicon portion underneath at least a portion of the capacitor interpoly oxide film portion, and an overlying upper capacitor second doped polysilicon portion over at least a portion of the patterned capacitor interpoly oxide film portion; within the first resistor region: a lower first resistor first polysilicon portion and an upper, overlying first resistor second polysilicon portion; within the second resistor region: a lower second resistor first polysilicon portion underneath at least a portion of the second interpoly oxide film portion; and within the metal-oxide semiconductor region: a lower metal-oxide semiconductor first polysilicon portion and an overlying metal-oxide semiconductor second polysilicon portion.