Patent ID: 8645608

Claim:
An electronic device comprising: a high-rank unit, a mid-rank unit, and a low-rank unit serially connected in sequence; a first interface for data communication arranged in the high-rank unit; second and third interfaces for data communication arranged in the mid-rank unit; a fourth interface for data communication arranged in the low-rank unit; a selector arranged in the mid-rank unit and configured to selectively form a first communication path which couples the first interface and the second interface, a second communication path which couples the third interface and the fourth interface, and a third communication path which couples the first interface and the fourth interface; a mid-rank control section arranged in the mid-rank unit, configured to form the first communication path and the second communication path of the selector and cut off the third communication path of the selector in an ordinary state, and configured to form the third communication path of the selector and cut off the first communication path and the second communication path of the selector when data needs to be written from the high-rank unit to the low-rank unit; and a high-rank control section arranged in the high-rank unit, configured to transmit a write preparation command to the mid-rank unit through the first interface when data to be written in the low-rank unit is input to an external interface of the electronic device, and configured to transmit said input data to the mid-rank unit through the first interface in response to receiving a status signal indicating completion of write preparation transmitted from the mid-rank unit through the first interface.