Patent ID: 7861095

Claim:
A data processing apparatus configured to access data values, each data value being associated with a respective address value, the data processing apparatus comprising: a processor configured to process an instruction which causes a data access request; a main memory configured to store data values, said main memory having a region of secure data values and comprising a data region allocation table, said data region allocation table being maintained by said main memory and providing an indication of whether regions of said main memory comprise secure data regions storing said secure data values or non-secure data regions; a cache configured to store previously accessed data values corresponding to both secure data and non-secure data, and cache interface logic comprising: data transaction logic configured to receive a data access request from said processor requesting a data value be accessed in said cache, said data access request having an address value and a security attribute associated therewith; and security determination logic configured, in the event that said security attribute indicates a non-secure data access request for data to be accessed in said cache, to determine whether said non-secure data access request is associated with said region of secure data values by interrogating said data region allocation table and, in the event that said data region allocation table provides an indication that said address value is not associated with said secure data region of said main memory, to enable said data access request to complete and access said data value in said cache.