Patent ID: 8558728

Claim:
A system comprising: a time to digital converter (TDC) comprising: a first series interconnection of a plurality of delay elements, wherein a first delay element of the first series interconnection receives a first timing signal at an input; a first plurality of latches, wherein each latch of the first plurality of latches has an input connected to an output of a respective delay element of the first series interconnection, and each latch of the first plurality of latches receives a second timing signal at a clock input; a second series interconnection of a plurality of delay elements, wherein a first delay element of the second series interconnection receives the first timing signal at an input; and a second plurality of latches, wherein each latch of the second plurality of latches has an input connected to an output of a respective delay element of the second series interconnection, and each latch of the second plurality of latches receives the second timing signal at a clock input; and processing circuitry coupled to the outputs of the first and second pluralities of latches and configured to determine an approximate phase delay between the first timing signal and the second timing signal based on outputs of the first and second pluralities of latches.