Patent ID: 7713792

Claim:
A method for fabricating a fuse structure comprising: patterning a monocrystalline semiconductor material layer located upon a sacrificial layer located over a substrate to form in plan-view a wider end and narrower middle monocrystalline semiconductor material layer aligned upon a wider end and narrower middle sacrificial layer; etching a narrow middle portion of the wider end and narrower middle sacrificial layer from beneath the wider end and narrower middle semiconductor material layer to provide a gap interposed between the narrow middle portion of the wider end and narrower middle monocrystalline semiconductor material layer and the substrate, wherein said etching further leaves a pedestal of the wider end and narrower middle sacrificial layer recessed under a wider end portion of the wider end and narrower middle semiconductor material layer and wherein said etching thus also extends the gap to include a location under a periphery of the wider end portion of the wider end and narrower middle semiconductor material layer; and forming a fuse material layer upon one of: the monocrystalline semiconductor material layer, and sequentially patterning the fuse material layer when patterning the monocrystalline semiconductor material layer; and the wider end and narrower middle monocrystalline semiconductor material layer, said fuse material layer comprising a metal-semiconductor material.