Patent ID: 7960235

Claim:
A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: 1) forming an N well and a P well; 2) performing field region photolithography, field region implantation, and local oxidation isolation or shallow trench isolation; 3) depositing a buffer SiO 2 oxide layer/SiN dielectric layer; 4) performing positive electron beam exposure, and etching the dielectric layer to form slots; 5) depositing a buffer SiO 2 oxide layer and SiN, and etching to form sidewalls; 6) isotropically etching Si; 7) performing a first dry oxidation; 8) removing remaining SiN by wet etching; 9) performing a second dry oxidation to form nanowire; 10) depositing and anisotropically etching tetraethyl orthosilicate, or depositing oxide at a low temperature, and then planarizing the surface; 11) performing isotropic wet etching to release the nanowire; 12) depositing a gate dielectric; 13) depositing a gate electrode material; 14) anisotropically etching the gate electrode; 15) isotropically etching the gate electrode; 16) implanting in source and drain extension regions; 17) isotropically depositing SiN and anisotropically etching it to form sidewalls; 18) performing deep implantation in source and drain regions; 19) forming silicide; and 20) performing metalizing.