Patent ID: 7186594

Claim:
A method for providing an ESD-protection structure, said method comprising: forming an integrated circuit having a lighter doped p-silicon well (P− well); forming a first lighter doped n-silicon well (first N− well) in the P− well; forming a plurality of first heavier doped p-silicon diffusions (first P+ diffusions) in the first N− well; forming a first heavier doped n-silicon diffusion (first N+ diffusion) in the first N− well, wherein the first N+ diffusion surrounds the plurality of first P+ diffusions; forming a second lighter doped n-silicon well (second N− well) in the P− well, the second N− well adjacent to the first N− well; forming a second heavier doped n-silicon diffusion (second N+ diffusion) in the second N− well, the second N+ diffusion is connected to the first N+ diffusion; forming a second heavier doped p-silicon diffusion (second P+ diffusion) in the second N− well; forming a third heavier doped p-silicon diffusion (third P+ diffusion) in the P− well; connecting the third P+ diffusion to the second P+ diffusion, wherein the third P+ diffusion surrounds the first N+ diffusion, the plurality of first P+ diffusions, the second N+ diffusion and the second P+ diffusion; and connecting a bond pad to the plurality of first P+ diffusions.