Patent ID: 7970092

Claim:
A phase comparator for use in clock data recovery means for performing phase regulation and receiving data by using 2N+1 phases of clock signals whose period is (2N+ 1 )T (N is an integer greater than or equal to 1) and whose phase difference is 1T in data communication where a data rate is 1/T bps, the phase comparator comprising: 2N+1 comparison period detection means each for determining whether it is within an m th comparison period, which is defined as a period between a rising edge of a first clock signal and a rising edge of a second clock signal, to output the determination result as an m th comparison enable signal, wherein the first clock signal is the (m−1) th -phase (m−1 is a remainder of division by 2N+1 when it is greater than or equal to 0 and is obtained as m+2N when it is a negative number) clock signal among the 2N+1 phases of clock signals, and the second clock signal is the m th -phase (m is an integer greater than or equal to 0 and less than or equal to 2N) clock signal; and 2N+1 phase difference detection means each for receiving the m th comparison enable signal, the data and a reference clock to output information on a phase difference between the reference clock and the data when the m th comparison enable signal is active, wherein the reference clock is the (N+m) th -phase (N+m is a remainder of division by 2N+1) clock signal.