Patent ID: 8854104

Claim:
A circuit comprising: a first capacitive device; a first latch; a second capacitive device; a second latch; and a first circuit, wherein the first capacitive device includes a first end and a second end; the first end is configured to receive a first input signal; the first latch includes a first transistor and a second transistor; the first transistor and the second transistor are of a first type; a first terminal of the first transistor and a first terminal of the second transistor are configured to receive a first voltage value; a second terminal of the first transistor is coupled with a third terminal of the second transistor; a third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch; the second capacitive device includes a first end and a second end; the first end of the second capacitive device is configured to receive the first input signal; the second latch includes a third transistor and a fourth transistor; the third transistor and the fourth transistor are of a second type different from the first type; the second end of the second capacitive device is coupled with the second latch; and the first circuit is coupled between the second end of the first capacitive device and the second end of the second capacitive device.