Patent ID: 7272040

Claim:
A memory cell arrangement, comprising: a first bit line; a second bit line; a third bit line; a first NAND memory cell string comprising a plurality of serially source-to-drain coupled non-volatile memory cells; a second NAND memory cell string comprising a plurality of serially source-to-drain coupled non-volatile memory cells; the first bit line being coupled to a source/drain region of a first non-volatile memory cell of the plurality of serially source-to-drain coupled non-volatile memory cells of the first NAND string; the second bit line being coupled to a source/drain region of a first non-volatile memory cell of the plurality of serially source-to-drain coupled non-volatile memory cells of the second NAND string; and the third bit line being coupled to a source/drain region of a last non-volatile memory cell of the plurality of serially source-to-drain coupled non-volatile memory cells of the first NAND string and to a source/drain region of a last non-volatile memory cell of the plurality of serially source-to-drain coupled non-volatile memory cells of the second NAND string.