Patent ID: 7006395

Claim:
A semiconductor integrated circuit comprising: a signal generation circuit for generating a first enable signal in synchronization with a period of an external clock; a time adjustment circuit that generates a second enable signal from the first enable signal wherein a pulse width of the second enable signal is shorter than a pulse width of the first enable signal during a test mode and the pulse width of the second enable signal is the same as the pulse width of the first enable signal during a normal mode, and outputs the second enable signal; and a memory control circuit that uses the second enable signal to control a memory cell array, wherein said time adjustment circuit comprises a first logical gate that outputs the second enable signal at the same signal level as the first enable signal when a control signal pattern is at an active level, and that forcibly makes the second enable signal a non-active level when the control signal pattern is non-active, and wherein the control signal pattern is input directly from the outside via an electrode pad.