Patent ID: 8399307

Claim:
A method of forming a memory device; comprising: providing a substrate having a surface region; forming a first dielectric material overlying the surface region of the semiconductor substrate; defining a cell region, a first peripheral region, and a second peripheral region; forming a first crossbar array of memory cells in the cell region overlying the first dielectric material; the first crossbar array of memory cells comprises a first bottom wiring structure spatially extending in a first direction and including a portion extending into the first peripheral region, a first top wiring structure spatially extending in a second direction perpendicular to the first direction and a first switching region sandwiched in an intersection region between the first top wiring structure and the first bottom wiring structure, the first top wiring structure including a portion extending into the second peripheral region; forming a second dielectric material overlying the first crossbar array of memory cells; forming a via opening in a portion of the first periphery region, the via opening exposing a portion of the first bottom wiring structure and a portion of the substrate; depositing a second bottom wiring material to fill the via opening and to form a thickness of second bottom wiring material overlying the second dielectric material; subjecting the second bottom wiring material to a pattern and etch process to fond a second bottom wiring structure for a second array of memory cells, the second bottom wiring structure including a portion spatially extending parallel to the first bottom wiring structure in the cell region and a via structure in the first peripheral region, the via structure electrically connecting the second bottom wiring structure and the first bottom wiring structure to a first control circuitry on the substrate.