Patent ID: 8709871

Claim:
A method comprising: providing a plurality of semiconductor chips, each of the semiconductor chips comprising: a semiconductor substrate, made of a semiconductor material, including a first main surface and a second main surface opposite to the first main surface, a set of penetration electrodes, each of the penetration electrodes penetrating the semiconductor substrate from the first main surface to the second main surface and including a first end portion on a side of the first main surface and a second end portion on a side of the second main surface, a set of surface electrodes formed on the side of the first surface of the semiconductor substrate, and an operation circuit formed on the side of the first main surface of the semiconductor substrate and coupled between the first end portion of the set of penetration electrodes and the set of surface electrodes; and stacking the plurality of semiconductor chips with one another to provide a chip stack structure in which the set of surface electrodes of one of adjacent two of the semiconductor chips is vertically aligned with and electrically connected to the second end portion of the set of penetration electrodes of the other of the adjacent two of the semiconductor chips, wherein each of the semiconductor chips is provided to further comprise: a set of additional penetration electrodes each penetrating the semiconductor substrate from the first main surface to the second main surface, and a comparison circuit formed on the side of the first main surface of the semiconductor substrate, the comparison circuit being electrically connected to the set of penetrating electrodes and the set of additional penetration electrodes to compare first information from the set of penetration electrodes with second information from the set of additional penetration electrodes; and wherein the stacking the plurality of semiconductor chips comprises vertically aligning and electrically connecting the set of additional penetration electrodes of the one of the adjacent two of the semiconductor chips with and to the set of additional penetration electrodes of the other of the adjacent two of the semiconductor chips.