Patent ID: 7650602

Claim:
A parallel processing computer for executing a plurality of threads concurrently and in parallel, said computer comprising: a thread activation controller for determining whether or not each of threads, which are exclusively executable program fragments, is ready-to-run, and to put the thread determined ready-to-run into a ready thread queue as ready-to-run thread; and a thread execution controller having a pre-load unit, an EU (Execution Unit) allocation and trigger unit, a plurality of thread execution units and a plurality of register files including a plurality of registers, and wherein the pre-load unit, prior to when each ready-to-run thread in the ready thread queue is executed, allocates a free register file of the plurality of register files to the each ready-to-run thread, to load initial data for the each ready-to-run thread into the allocated register file, and wherein the EU allocation and trigger unit, when there is a thread execution unit in idle state of the plurality of thread execution units, retrieves ready-to-run thread from the top of the ready thread queue, and to allocate the retrieved ready-to-run thread to the thread execution unit in idle state, and to couple the register file loaded the initial data for the ready-to-run thread with the allocated thread execution unit in idle state, and to activate the ready-to-run thread, and wherein the plurality of thread execution units execute the activated threads concurrently in parallel; and wherein the thread activation controller comprises synchronous control memory, and wherein the synchronous control memory has blocks for every instance, each block having both a count field for synchronously activating thread and a preceding-thread number field in which preceding thread number is previously stored therein for each thread.