Patent ID: 8677180

Claim:
A computer implemented method for failover control in a computer system, the method comprising: maintaining a primary device table entry (DTE) in a first device table activated for a first adapter in communication with a first host processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in the first device table in standby for a second adapter in communication with a second host processor node having a second root complex via a second switch assembly; maintaining a primary DTE in a second device table activated for the second adapter and maintaining a secondary DTE in the second device table in standby for the first adapter; and upon a failover condition, updating the secondary DTE in the first device table as an active entry for the second adapter and forming a failover path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first host processor node.