Patent ID: 7079069

Claim:
An analog-digital converter comprising: a first register for holding a first approximation number which is variable in a first cycle and is fixed in a second cycle; a second register for holding a second approximation number which is fixed in the first cycle and is variable in the second cycle; an adder for adding the first and second approximation numbers and for providing a sum approximation number representing a digital representation of an analog input signal; a processor for calculating the first approximation number, the processor being formed to adjust the first approximation number in the first cycle in response to the analog input signal so that the sum approximation number depends on the analog input signal, and for calculating the second approximation number, the processor being formed to adjust the second approximation number in the second cycle in response to the analog input signal so that the sum approximation number depends on the analog input signal; and a controller for operating the processor in the first or second cycle.