Patent ID: 7656039

Claim:
A multi chip module comprising: a mounting substrate having an upper surface, an electrode formed on the upper surface, and a lower surface opposite to the upper surface; a first semiconductor chip having a first main surface, a first bonding pad formed on the first main surface, and a first back surface opposite to the first main surface, and mounted over the upper surface of the mounting substrate; a second semiconductor chip having a second main surface, a second bonding pad formed on the second main surface, and a second back surface opposite to the second main surface, and mounted over the first semiconductor chip; a silicon substrate mounted over the second semiconductor chip; a third semiconductor chip having a third main surface, a third bonding pad formed on the third main surface, and a third back surface opposite to the third main surface, and mounted over the silicon substrate; and a sealing body sealing the first semiconductor chip, the second semiconductor chip and the third semiconductor chip; wherein the first semiconductor chip is a dynamic random access memory; wherein the second semiconductor chip is a non-volatile memory; wherein the third semiconductor chip has a digital signal processing circuit controlling the first semiconductor chip; wherein the third semiconductor chip generates a noise; wherein the first semiconductor chip is more susceptible to the noise than the second semiconductor chip; and wherein a size of the third semiconductor chip is smaller in an area than that of the first semiconductor chip.