Patent ID: 8171318

Claim:
A flash memory device, comprising: a first plurality of memory cells for storing data; a second plurality of memory cells for storing data; a voltage input adapted for connection to an output of a voltage-regulated power supply; a first register containing information indicating a first minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of the first plurality of memory cells; a second register containing information indicating a second minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of the second plurality of memory cells; and a processor configured to i) identify a greatest minimum operating voltage from among the first minimum operating voltage and the second minimum operating voltage, and ii) determine a selected operating voltage to supply from the voltage-regulated power supply to the voltage input for performing the read operation of the one or more of the first plurality of memory cells based upon the identified greatest minimum operating voltage.