Patent ID: 8183701

Claim:
An integrated circuit, comprising: a semiconductor substrate; a plurality of material layers including a first material layer, a second material layer, and a third material layer formed on the semiconductor substrate, each of the material layers including a circuit pattern therein, wherein the third material layer is disposed over and in contact with the second material layer and the second material layer is disposed over and in contact with the first material layer; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region, wherein the plurality of diffraction-based periodic marks includes a first diffraction-based periodic mark disposed in the first material layer, a second diffraction-based periodic mark disposed in the second material layer, and a third diffraction-based periodic mark disposed in the third material layer, and wherein the third diffraction-based periodic mark has an orientation that is different than the second diffraction-based periodic mark.