Patent ID: 8250419

Claim:
A circuit comprising: A. test access port having: i. a TDI lead, a TDO lead, a TMS lead, a TCK lead, and a TRST lead; and ii. a test access port controller having inputs connected to the TMS, TCK and TRST leads and having ClockIR, ShiftIR, CaptureIR, UpdateIR, Reset, Select, ClockDR, ShiftDR, CaptureDR, and UpdateDR output leads; B. a wrapper serial port having: i. a clock lead, a capture lead, a shift lead, an update lead, a transfer lead, a reset lead, a select lead, a WSI lead, and a WSO lead; and ii. a wrapper serial port controller having inputs connected to the clock lead, the capture lead, the shift lead, the update lead, the transfer lead, the reset lead, and the select lead, and having ClockIR, ShiftIR, CaptureIR, UpdateIR, Reset, Select, ClockDR, ShiftDR, CaptureDR, UpdateDR, and TransferDR output leads; and C. multiplexer circuitry having a first bus input connected to the output leads of the test access port controller and having a TransferDR input, a second bus input connected to the output leads of the wrapper serial port controller, and having an output bus having ClockIR, ShiftIR, CaptureIR, UpdateIR, Reset, Select, ClockDR, ShiftDR, CaptureDR, UpdateDR and TransferDR output leads.