Patent ID: 8219341

Claim:
A method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”), the method being implemented by a computer and comprising: performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting, by the computer, a subset of the plurality of wafer lots using a lot sampling process, wherein the selecting the subset of the plurality of wafer lots comprises prioritizing lots according to a sum of chamber total moves for key stages used in processing the lots and selecting lots to provide maximum tool coverage from the prioritized lots; selecting, by the computer, a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefrom; estimating, by the computer, final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group; and automatically providing, by the computer, the estimated final WAT data to a WAT APC process, the WAT APC process using the estimated final WAT data to control a tuning process or a process APC process.