Patent ID: 6987405

Claim:
An apparatus for generating multi-phase signals, comprising: a single delay chain comprising a series of delay elements and associated taps configured to produce multi-phase signals, a slow boundary signal, and a fast boundary signal, said multi-phase signals corresponding to a plurality of output clock signals that are each phase delayed by a different delay with respect to an input clock signal; an array of trim capacitors connected to said single delay chain; a timing control window circuit to produce a control signal when a reference signal is outside a timing control window defined by said slow boundary signal and said fast boundary signal; and a digital circuit to produce a digital capacitive trim signal for application to said array of trim capacitors in response to said control signal, said digital capacitive trim signal altering the capacitive loading of said single delay chain to control a position of each control timing edge of said plurality of output clock signals with respect to said input clock signal; wherein said control signal operates to maintain said reference signal within said control window such that said reference signal transitions after said fast boundary signal and before said slow boundary signal.