Patent ID: 7751251

Claim:
An apparatus for determining one or more memory cell states in a memory device, comprising: a first memory cell coupled to a first bitline; and a first sensing element coupled to the first bitline, the first sensing element operable to sense a voltage corresponding to a state of the first memory cell wherein the sensed voltage is independent of a bitline voltage discharge over time of the first memory cell, the first sensing element comprising; a first reference current circuit comprising a first transistor; a second reference current circuit comprising a second transistor; a first sensing circuit coupled to the first reference current circuit and the second reference current circuit, wherein the first sensing circuit comprises; a first current mirror comprising a third transistor operable to mirror a current of the first reference current circuit; and a second current mirror comprising a fourth transistor coupled to the first current mirror via the first bitline wherein the second current mirror is operable to mirror a current of the second reference current circuit.