Patent ID: 8810036

Claim:
A semiconductor device comprising: a substrate comprising a memory cell region, a connection region and a group of conductive lines each having a unit width, being arranged in parallel along a defined center line, including a first conductive line and a second conductive line, and extending in a first direction from the memory cell region into the connection region, wherein the first conductive line has a first length in the first direction extending away from the memory cell region that ends in a first portion extending a second length in a second direction away from the center line, the first portion terminates in a portion bending back in the first direction towards the memory cell region to connect a second portion extending in the second direction away from the center line to connect a first pad; and the second conductive line has a third length less than the first length extending in the first direction away from the memory cell region and ends in a first portion extending a fourth length less than the second length in the second direction away from the center line, the first portion terminates in a portion bending back in the first direction towards the memory cell region to connect a second portion extending in the second direction back towards the center line to connect a second pad, and a width separating the first pad from the second pad is greater than the unit width.