Patent ID: 7421635

Claim:
A system-on-chip (SOC) with a built-in-self-test circuit, the SOC comprising: intellectual property (IP) blocks each having a built-in-self-test (BIST) logic circuit that operates in one of a normal mode and a test mode in response to control data received through a system bus, wherein the BIST logic circuit stores the control data in a control register, generates test control signals in response to the stored control data and outputs test result data when the BIST logic circuit operates in the test mode; and a BIST control unit that tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuits through the system bus, and compresses and stores the test result data received through the system bus in the test mode, wherein the test address signals comprise: a first test address signal and a plurality of second test address signals; wherein the BIST logic circuit comprises: a bus interface device that generates a register control signal in response to the first test address signal and the command signal, and generates first through third selection control signals in response to the command signal, the plurality of second test address signals, and first through third test control signals, and wherein the control register is connected to the system bus through a data pass line, stores the control data received through the data pass line, and generates the first through third test control signals based on the stored control data in response to the register control signal fed thereto.