Patent ID: 7624369

Claim:
A computer implemented method for designing an integrated circuit, the method comprising the steps of: a) providing one or more design tolerances, a design layout containing a set of intended design shapes, and a first process model then b) using said design layout and said first process model to generate first image contours which simulate an image printed on a wafer; c) modifying said design layout by computer to form a modified design layout based on step (b); d) repeating steps (b) and (c) using said modified design layout until said first image contours satisfy said one or more design tolerances; then e) using said modified design layout and a second process model, different from the first process model and which corrects for optical proximity, to generate a mask layout representing a manufacturable mask f) generating second image contours which simulate an image printed on a wafer using said mask layout and said second process model; g) modifying said mask layout to form a modified mask layout based on step (e); and h) repeating steps (f) and (g) using said modified mask layout until said second image contours match said first image contours within manufacturability tolerances.