Patent ID: 7400044

Claim:
A semiconductor integrated circuit device comprising: a first wire arranged along a first well in a substrate; a second wire arranged along a second well in the substrate; a third wire arranged in a same layer as the first wire and the second wire, the third wire being arranged in a direction intersecting with the first wire and the second wire and electrically insulated from the first wire and the second wire; a first gate material wire arranged between the first wire and the first well in the vicinity of an intersecting point between wiring directions of the first wire and the third wire, the first gate material wire being electrically connected to the third wire through via holes, the first gate material wire being formed of a same material as a gate material; and a first diffusion layer arranged in the second well in the vicinity of an intersecting point between wiring directions of the second wire and the third wire, the first diffusion layer being electrically connected to the third wire through via holes, the first diffusion layer including impurities having a higher concentration than that of the second well; the first gate material wire and the first diffusion layer being employed as a wiring path associated with the third wire.