Patent ID: 8004897

Claim:
A memory device, comprising: a memory array partitioned into a plurality of memory banks; a buffer; a first sense amplifier including a first latch, the first sense amplifier operably coupled with the buffer and a first memory bank of the plurality of memory banks, the first latch configured to receive first data from the buffer and send the first data to be programmed in the first memory bank; a second sense amplifier including a second latch, the second sense amplifier operably coupled with the buffer and a second memory bank of the plurality of memory banks, the second latch configured to receive second data from the buffer and send the second data to be programmed in the second memory bank; and a controller configured to control flow of the first data received by the first latch and the second data received by the second latch from the buffer such that the buffer receives the second data after sending the first data to the first latch, and further configured to program one of the first data and the second data concurrently with verification of the programming of the other one of the first data and the second data in the corresponding first and second memory banks.