Patent ID: 8587460

Claim:
An A/D conversion apparatus comprising: first to M-th (M being a preset integer not less than two) A/D conversion circuits connected in parallel, the first to M-th A/D conversion circuits converting an analog input signal to digital signals respectively in response to M-phase sampling signals which are obtained by frequency-dividing a clock signal by M and are equally spaced by one cycle of the clock signal; a reference A/D conversion circuit that converts the analog input signal to a digital signal, in response to a sampling signal obtained by frequency-dividing the clock signal by (n×M+1) (n being a preset positive integer), the first to M-th A/D conversion circuits and the reference A/D conversion circuit having analog inputs connected in common; and a control unit that compares, for each period of (n×M+1) cycles of the clock signal, one of the digital signals output from a corresponding one of the first to M-th A/D conversion circuits with the digital signal output from the reference A/D conversion circuit in a predetermined order of the first to M-th A/D conversion circuits, and generates a compensation control signal, based on a result of the comparison to supply the compensation control signal to the corresponding one of the A/D conversion circuits.