Patent ID: 8666019

Claim:
A shift register unit, comprising: a first thin film transistor, whose drain is connected to a first clock signal input terminal, a source thereof is connected to a signal output terminal; a second thin film transistor, whose drain is connected to the source of the first thin film transistor, a gate thereof is connected to a reset signal input terminal, a source thereof is connected to a low voltage signal input terminal; a third thin film transistor, whose drain and gate are both connected to a signal input terminal, a source thereof is connected to the gate of the first thin film transistor; a fourth thin film transistor, whose drain is connected to the source of the third thin film transistor, a gate thereof is connected to the reset signal input terminal, a source thereof is connected to the low voltage signal input terminal; a fifth thin film transistor, whose drain is connected to a high voltage signal input terminal, a gate thereof is connected to the reset signal input terminal; a sixth thin film transistor, whose drain is connected to the source of the fifth thin film transistor, a gate thereof is connected to the signal input terminal, a source thereof is connected to the low voltage signal input terminal; a seventh thin film transistor, whose drain is connected to the high voltage signal input terminal, a gate thereof is connected to a frame start signal input terminal, a source thereof is connected to the drain of the sixth thin film transistor; a eighth thin film transistor, whose drain is connected to the source of the first thin film transistor, a source thereof is connected to the low voltage signal input terminal, a gate thereof is connected to the source of the fifth thin film transistor, a ninth thin film transistor, whose drain is connected to the source of the third thin film transistor, a gate thereof is connected to the source of the fifth thin film transistor, a source thereof is connected to the low voltage signal input terminal; a tenth thin film transistor, whose drain and gate are both connected to the source of the fifth thin film transistor, a source thereof is connected to the low voltage signal input terminal; a eleventh thin film transistor, whose drain is connected to the source of the fifth thin film transistor, a source thereof is connected to the low voltage signal input terminal, a gate thereof is connected to the signal output terminal; and wherein, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor.