Patent ID: 8009784

Claim:
A clock embedded differential data receiving system for receiving first, second and third transfer signals transferred via ternary lines, the clock embedded differential data receiving system, comprising: a monitoring portion which monitors voltage levels of the first, second and third transfer signals, and generates a clock signal, a first pre-data and a second pre-data, wherein the clock signal comprises a logic state according a comparison of the voltage levels between the first transfer signal and the second transfer signal, and wherein the first pre-data comprises a logic state according to a comparison of the voltage levels between the second transfer signal and the third transfer signal, and wherein the second pre-data comprises a logic state a comparison of the voltage levels between the third transfer signal and the first transfer signal; a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding the first pre-data and the second pre-data; and a timing controller which delays a transition time point of the clock signal with a delay phase and generates the sampling control signal, wherein the data generating portion comprises: a data sampling unit which generate a first leading data, a second leading data, a first legging data and a second legging data, wherein a value of the first leading data is determined by a value of the first pre-data at the leading transition of the sampling control signal, a value of the second leading data is determined by a value of the second pre-data at the leading transition of the sampling control signal, a value of the first legging data is determined by a value of the first pre-data at the legging transition of the sampling control signal, and a value of the second legging data is determined by a value of the second pre-data at the legging transition of the sampling control signal; and a decoder which decodes the first leading data, the second leading data, the first legging data and the second legging data to generate the output data group.