Patent ID: 7072218

Claim:
A semiconductor integrated circuit comprising: a memory cell array including a matrix arrangement of a plurality of memory cells which are adapted to operate selectively in certain manners by application of high voltages thereto; a plurality of signal lines for supplying said high voltages to said memory cells; high voltage output drivers which are provided for said signal lines individually; output switching circuits for said high voltage output drivers; and a high voltage generation circuit which supplies high-voltage operational power to said high voltage output drivers, wherein each said high voltage output driver includes a series circuit having a first MOS transistor and a second MOS transistor in current paths of said high voltages, with a serial connection node thereof being driver output terminal, wherein said first MOS transistor has drain-source voltage applied thereto in excess of a breakdown voltage during a voltage transition of a corresponding signal line from a high-voltage level to a low-voltage level, wherein said second MOS transistor has a drain-source voltage applied thereto in excess of a breakdown voltage during a voltage transition of the corresponding signal line from a low-voltage level to a high-voltage level, and wherein each said output switching circuit is coupled with a first control signal and a second control signal and operates in response to a switching command signal to switch states of said first and second MOS transistors of a corresponding high voltage output driver, such that one of said transistors in an on-state is switched to an off-state by outputting said first control signal to a gate terminal of said one transistor via a first control signal line and the other of said transistors is thereafter switched to an on-state by outputting said second control signal to a gate terminal of said other transistor via a second control signal line.