Patent ID: 8234455

Claim:
A system for controlling memory access in a multithreaded processor supporting a plurality of threads, comprising: a processor core; a cache memory storing data accessible by each of the plurality of threads; a main memory storing data accessible by the plurality of threads; an incoherency detection module; and a memory arbiter connected between the incoherency detection module and the main memory, wherein the incoherency detection module is connected between the processor core and the memory arbiter, there is a separate request queue for each thread for read and write requests sent from the cache memory to the memory arbiter, the incoherency detection module stores an indication of a memory address for each write request sent from the cache memory to the main memory in a write address memory, and compares an address of each subsequent read request sent from the cache memory to the main memory with indications in the write address memory and, if the address of the subsequent read request matches one of the indications, inserts a barrier corresponding to the subsequent read request into a request queue of the thread to which the matching indication belongs, and the memory arbiter prevents the subsequent read request from accessing the main memory until the barrier has been received by the memory arbiter.