Patent ID: 8838666

Claim:
A divider logic circuit for obtaining a quotient S of a dividend M divided by a divisor N, comprising: a first constant value input terminal for inputting an estimate value S 1 of the quotient S; a first adder connected with said first constant value input terminal; a second constant value input terminal for inputting a constant value M−N*S 1 ; a base number input terminal for inputting a base number N 1 −N; at least one integer power device connected with said base number input terminal; at least one right shift register connected with said integer power device; a second adder connected with said right shift register, and a multiplier connected with said first adder, said second adder and said second constant value input terminal, wherein N 1 is a standard power value which is the closest to said divisor N, N 1 =2 h , wherein h is a natural number, wherein said integer power device determines a first constant value that said base number is N 1 −N, and an exponent is i−1, wherein i is a natural number, wherein said right shift register shifts said first constant value determined by said integer power device to the right for h*i-digit for outputting a second constant value to said second adder, wherein said multiplier multiplies a third constant value that said second adder outputs by said constant value M−N*S 1 inputted by said second constant value input terminal for outputting a fourth constant value to said first adder, wherein said first adder adds up said estimate S 1 inputted by said first constant value input terminal and said fourth constant value sent by said multiplier and outputs said quotient S of said dividend M divided by said divisor N.