Patent ID: 7081798

Claim:
A variable frequency synthesizer comprising: a voltage controlled oscillator (VCO) generating oscillator signals (u VCO ) with a frequency dependent on input signals (u cp ) applied to said voltage controlled oscillator (VCO); a frequency divider receiving said oscillator signals and generating divider signals (u DIV ) with a frequency which is equal to a frequency of said oscillator signals divided by a divider ratio; a phase detector (PD) providing phase difference signals (u PD )on the basis of a phase difference between said divider signals (u DIV ) and reference signals (u REF ), said phase difference signals determining said input signals applied to said voltage controlled oscillator; a divider ratio controller (DRC) comprising a sigma-delta modulator and providing said divider ratio, said sigma-delta modulator comprising a plurality of accumulator stages being connected in cascade, each accumulator stage adding up input values and providing an overflow signal value when a maximum value is reached, a first accumulator stage in said cascade receiving a fractional part of an intended average divider ratio as a first component of an input value, each following accumulator receiving an accumulator value of an accumulator preceding said following accumulator and adjacent to said following accumulator as a first component of an input value, each overflow signal value being differentiated as many times as accumulator stages are preceding an accumulator stage providing said respective overflow signal value in said cascade before all overflow signal values are added up to form an output signal of said sigma-delta modulator, said divider ratio being a sum of said output signal of said sigma-delta modulator and an integer part of an intended average divider ratio; characterized in that at least one input value has a second component which is equal to an overflow signal multiplied by a factor.