Patent ID: 7944264

Claim:
A variable delay circuit that adjusts a delay given to a first input signal which is one of a reference signal and a data signal according to a second input signal which is the other of the reference signal and the data signal, the circuit comprising: a first delay section that changes a first drive capability of the first delay section or a first capacity load of the first delay section according to a first control signal, receives the reference signals, and generates a first delayed signal by giving a first delay to the reference signal; a second delay section that changes a second drive capability of the second delay section or a second capacity load of the second delay section according to a second control signal, receives the reference signal, and generates a second delayed signal by giving a second delay to the reference signal; a first capacity load setting section that sets at least one of the first capacity load and the second capacity load by providing the first control signal and the second control signal, in order that the first capacity load differs from the second capacity load; a first phase comparing section that compares a first phase of the first delayed signal with a second phase of the second delayed signal; and a drive capability setting section that controls the first drive capability and the second drive capability by providing the first control signal and the second control signal, according to a result of the comparing of the first phase and the second phase, in order that a difference between the first delay and the second delay is equal to a predetermined value and the first drive capability is equal to the second drive capability.