Patent ID: 7446585

Claim:
A programmable delay circuit, for delaying a received differential signal according to a delay-controlled code to obtain a differential output signal, wherein the received differential signal comprises a positive-phase received signal and an anti-phase received signal, and the differential output signal comprises a positive-phase output signal and an anti-phase output signal, and wherein a resolution of the delay-controlled code comprises (M+N) bits, and M and N are integers, the programmable delay circuit comprising: a first inverter, comprising an input end for receiving the positive-phase received signal and an output end coupled to an anti-phase output signal line; a second inverter, comprising an input end for receiving the anti-phase received signal and an output end coupled to a positive-phase output signal line; a variable resistance unit, coupled between the anti-phase output signal line and the positive-phase output signal line, for regulating an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in the delay-controlled code; and a variable capacitance unit, coupled between the anti-phase output signal line and the positive-phase output signal line, for regulating an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code, wherein the anti-phase output signal is obtained from the anti-phase output signal line, and the positive-phase output signal is obtained from the positive-phase output signal line.