Patent ID: 6911702

Claim:
Integrated circuitry comprising: a substrate comprising first and second transistor gates, a source/drain region proximate the second transistor gate, the first transistor gate comprising conductively doped semiconductive material and a conductive suicide received elevationally outward thereof and in electrical connection therewith, the semiconductive material and the suicide having respective elevationally outermost surfaces, the first transistor gate comprising opposing sidewalls of the semiconductive material and the silicide; a first dielectric layer received over the first transistor gate, the first dielectric layer being selected from the group consisting of undoped silicon dioxide, silicon nitride and mixtures thereof; a pair of insulative sidewall spacers received over the first transistor gate sidewalls, the sidewall spacers having respective uppermost surfaces which are substantially elevationally coincident with the uppermost surface of the semiconductive material; a conductive local interconnect electrically connecting the first transistor gate suicide with the source/drain region proximate the second transistor gate, the conductive local interconnect having sidewalls and being received over the first dielectric layer; and a second dielectric layer different in composition from the first a second dielectric layer the second dielectric layer comprising a doped silicon dioxide layer received over a Si x O y N z layer and which contact the conductive local interconnect sidewalls.