Patent ID: 7548482

Claim:
A memory device comprising: a bias controller receiving a deep power down command and generating a deep power down exit mode bias signal; and an internal power supply voltage generator generating an internal power supply voltage used in an active mode in response to an active command or the deep power down exit mode bias signal, wherein the bias controller comprises: a pulse generating unit receiving the deep power down command and generating a deep power down exit pulse signal and the deep power down exit mode bias signal; and a current driving unit generating a deep power down exit mode reference voltage in response to the deep power down exit mode bias signal and a reference voltage, wherein the pulse generating unit comprises: a deep power down exit pulse generator generating the deep power down exit pulse signal having a predetermined pulse width in response to a falling edge of the deep power down command signal; and a deep power down exit mode signal generator generating the deep power down exit mode bias signal in response to the deep power down exit pulse signal.