Patent ID: 7821857

Claim:
A semiconductor memory device comprising: a memory cell array comprising a bit line sense amplifier; an input/output (I/O) line sense amplifier comprising a buffer unit, a first sense amplifier, a precharge unit, and a second sense amplifier, wherein the buffer unit is driven by a first level voltage to buffer a first strobe signal, the first sense amplifier is driven by a second level voltage to amplify a signal of the bit line sense amplifier transmitted to a first I/O line in response to an output signal of the buffer unit, the precharge unit is driven by the first level voltage to precharge an output signal of the first sense amplifier in response to the output signal of the buffer unit, and the second sense amplifier is driven by the second level voltage to amplify the output signal of the first sense amplifier in response to a second strobe signal to generate a driving signal for driving a second I/O line; and a write driver configured to amplify a signal, the signal being input to a data pad and transmitted through the second I/O line, and transmit the signal to the first I/O line.