Patent ID: 8730069

Claim:
A method for serial encoding, comprising: providing a glitch-less multiplexer (mux) having a plurality of mux data inputs, a plurality of select inputs and a mux output, wherein the mux output does not glitch due to a change of any single select input bit; providing a plurality of latches, having latch data inputs and latch data outputs, wherein the latch data outputs are coupled to the plurality of mux data inputs; providing an enabler, coupled to the latches; providing a counter, coupled to the select inputs of the mux, wherein the counter transitions on either a rising or a falling edge of an input clock, and only a single counter state bit changes on a transition between any two consecutive states in a count sequence; employing the enabler to enable and control the latches to update the latch data outputs at a time when the latch data inputs are not changing; and employing the counter to select one of the plurality of mux data inputs in a predetermined sequence for the mux output and control the enabler.