Patent ID: 6989299

Claim:
A method of fabricating on-chip spacers for a TFT panel comprising a substrate having a top and bottom face and a TFT driving circuit with a top face formed on the top face of the substrate, windows and an opaque grid composed of portions of the TFT driving circuit, the TFT panel being fabricating by a process comprising the steps of: preparing a temporary substrate adapted to form semiconductors; forming an etching stop layer on the temporary substrate; forming thin film transistors (TFTs) on the etching stop layer, wherein each thin film transistor has a gate oxide layer; forming pixel electrodes on the etching stop layer adjacent to the TFTs; forming a first metal layer on the gate oxide layer; covering the first metal layer, the gate oxide layer and pixel electrodes with an inner layer; forming a second metal layer through the inner layer to connect the pixel electrodes to the TFT and to adjacent TFTs; covering the second metal and inner layer with a passivation layer; bonding a display panel on the passivation layer; and removing the temporary substrate and portions of the etching stop layer to expose the pixel electrodes, the method of fabricating on-chip spacers for the TFT panel comprising: applying a photoresist layer on the top face of the TFT driving circuit; preparing a mask having a pattern that overlaps a shape of the windows; exposing the photoresist by the mask and the opaque grid; and removing the exposed photoresist to form on-chip spacers where unexposed photoresist on the TFT driving circuit exists only in the opaque grid.