Patent ID: 7688083

Claim:
A method of obtaining parametric test data for use in monitoring alignment of first and second layers of material successively deposited on a substrate defining two respective non-contacting component types on an integrated circuit die, the method comprising: providing a test structure comprising a conductive first line a second line of the material of said first layer of material, and a plurality of component regions each component region comprising one or more components defined by said second layer of material and being provided on said conductive first line relative to said second line of material, wherein a first component region is located at a first distance from said second line of material and a second component region is located in contact with second line of material, said second line of material defining a resistance between said first and second component regions performing a single analogue measurement between said conductive first line and said second line of material so as to measure the resistance therebetween, said resistance being indicative of a probability of a short circuit occurring between said first and second layers of material depending upon the distance therebetween.