Patent ID: 7329922

Claim:
A metal-oxide-semiconductor (MOS) device, comprising: a semiconductor layer of a first conductivity type; first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another; a channel region of the first conductivity type formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, the channel region being non-uniformly doped; an insulating layer formed on at least a portion of the upper surface of the semiconductor layer; a first gate formed on the insulating layer at least partially between the first and second source/drain regions and substantially over the channel region; and at least a second gate formed on the insulating layer substantially over the channel region and between the first gate and the second source/drain region, the second gate having a length which is greater than a length of the first gate, the first and second gates being electrically isolated from one another; wherein a conduction of the channel region is selectively controllable as a function of first and second signals applied to the first and second gates, respectively.