Patent ID: 8456582

Claim:
A pixel structure located on a substrate and comprising: a scan line and a data line; an active device including a gate, a channel, a source, and a drain, wherein the gate is electrically connected to the scan line, and wherein the source is electrically connected to the data line; a gate insulating layer located between the gate and the channel; a pixel electrode electrically connected to the drain; a capacitor electrode located on the gate insulating layer; and a capacitor dielectric layer located between the capacitor electrode and the drain, wherein a thickness of the capacitor dielectric layer is smaller than a thickness of the gate insulating layer, the thickness of the capacitor dielectric layer is about 700 angstroms to about 1500 angstroms, and the thickness of the gate insulating layer is about 3300 angstroms to about 5100 angstroms.