Patent ID: 8822279

Claim:
A manufacturing method for a thin film transistor display panel, the method comprising: forming a gate wire extending in a first direction on a substrate, the gate wire comprising: a lower gate line arranged in the first direction; and a gate electrode protruding from the lower gate line; forming a first blocking layer on the gate electrode; forming an upper gate line on the lower gate line; forming a gate insulating layer on the upper gate line; forming a semiconductor layer on the gate insulating layer; forming a data wire comprising: a source electrode disposed on the semiconductor layer; a drain electrode disposed on the semiconductor layer and opposing the source electrode with respect to the gate electrode; and a lower data line extending in a second direction and intersecting the gate line; forming a passivation layer on the data wire and comprising a contact hole exposing a portion of the drain electrode; and forming a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole, wherein forming the upper gate line comprises using an electroless plating method that uses the lower gate line as a seed layer.