Patent ID: 7335946

Claim:
A trench-gated MIS device formed in a semiconductor chip and comprising: a first active area and a second active area each comprising transistor cells; a gate metal area containing no transistor cells; and a gate metal layer, wherein a plurality of trenches are formed in a pattern on a surface of the semiconductor chip, each trench extending from the first active area to the second active area and passing through the gate metal area, each trench having walls lined with a layer of an insulating material, a conductive gate material being disposed in each trench, a top surface of the conductive gate material being at a level below a top surface of the semiconductor chip, a nonconductive layer overlying the active and gate metal areas, a plurality of apertures being formed in the nonconductive layer, each aperture being formed over a portion of a respective trench in the gate metal area such that each aperture is spaced apart from each other, each aperture being filled with the gate metal layer such that the gate metal layer contacts the conductive gate material in an area of contact within each trench.