Patent ID: 8743636

Claim:
A memory module comprising: a circuit board having a connector interface that enables the circuit board to be removably inserted into an interconnect socket, the circuit board including an address/control signal path, an address/control timing path, a plurality of data signal paths and a plurality of data timing paths; and a plurality of memory components coupled to the address/control signal path at respective, successive points along the length of the address/control signal path such that signal propagation delay on the address/control path progressively increases for successively disposed memory components, each of the memory components being coupled to a respective one of the data signal paths and having: a core of dynamic random access memory cells; first circuitry coupled to the address/control signal path to receive control information that specifies a write operation and coupled to the address/control timing path to receive a clock signal that controls reception of the control information; second circuitry coupled to the respective one of the data signal paths to receive write data corresponding to the write operation and coupled to a respective one of the data timing paths to receive a timing signal indicating that the write data is valid, the second circuitry being operable in a calibration mode to receive multiple delayed versions of the timing signal; and third circuitry to output signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay time between outputting the control information on the address/control signal path and outputting the write data on the respective data signal path, the delay time to compensate for a difference between a propagation time of the control information on the address/control signal path and a propagation time of the write data on the respective data signal path.