Patent ID: 6847563

Claim:
A semiconductor storage device comprising: a memory cell array having a normal memory cell area that corresponds to a specified storage capacity where a plurality of memory cells are arranged in a matrix form and a redundant memory cell area made up of at least one of a plurality of redundant memory cell columns and a plurality of redundant memory cell rows, wherein a test is conducted to check presence or absence of defects in said normal memory cell area and said redundant memory cell area and defective memory cell columns or defective memory cell rows in said normal memory cell area are replaced with said redundant memory cell columns or said redundant memory cell rows respectively; and wherein said semiconductor storage device is configured so that in said test conducted on said redundant memory cell area, if said redundant memory cell columns or said redundant memory cell rows have been already replaced, judgment is made to exclude said redundant memory cell columns or said redundant memory cell rows from said redundant memory cell columns or said redundant memory cell rows respectively, to be replaced.