Patent ID: 8438518

Claim:
An apparatus for designing a semiconductor integrated circuit including flip-flop circuits, comprising: a processor and a program memory; a timing analyzing section, stored in the program memory, configured to detect a hold error according to timing analysis data including values at input and output nodes of said flip-flop circuits, and to identify a node experiencing said hold error; a fall flip-flop/buffer insertion determining section, stored in the program memory, configured to determine insertion of a fall flip-flop or a buffer in said hold error position based on a result of the analysis by said timing analyzing section; a fall flip-flop inserting section, stored in the program memory, configured to insert a fall flip-flop in said hold error position located to insert a fall flip-flop based on fall flip-flop insertion position data from said fall flip-flop/buffer insertion determining section, and to connect a clock line to said inserted fall flip-flop; and a buffer inserting section, stored in the program memory, configured to insert a buffer in said hold error position located to insert a buffer based on buffer insertion position data from said fall flip-flop/buffer insertion determining section.