Patent ID: 7162674

Claim:
An apparatus for selecting test patterns comprising: a first test pattern selecting module configured to classify a plurality of verification patterns of a logic circuit of an LSI into a plurality of selected test patterns fulfilling a reliability criterion and a plurality of unselected test patterns failing to fulfill the reliability criterion; a fault simulation module configured to simulate whether the plurality of selected test patterns and the plurality of unselected test patterns detect a plurality of faults estimated to occur in the logic circuit; a weighting module configured to add weight reflecting a plurality of layout elements of the logic circuit and information on each name of the plurality of layout elements to each of a plurality of first undetected faults that are undetected by the plurality of selected test patterns and define the plurality of first undetected faults to which the weights are given as a plurality of first weighted undetected faults; a fault sampling module configured to extract a plurality of second undetected faults from the plurality of first weighted undetected faults; a second test pattern selecting module configured to extract a plurality of additionally selected test patterns that detects the plurality of second undetected faults from the plurality of the unselected test patterns based on a criterion of the added weight; and a data memory configured to store a plurality of final weighted undetected faults from among the plurality of first weighted undetected faults, the plurality of final weighted undetected faults being not detected by the plurality of additionally selected test patterns.