Patent ID: 7368372

Claim:
A method of fabricating multiple sets of field effect transistors, comprising: forming a series of layers over a semiconductor substrate comprising silicon; the series comprising a conductive gate layer, an insulative layer over the conductive gate layer, and an etch stop layer over the insulative layer, the etch stop layer being formed to a first thickness; patterning and etching the series of layers to form a first set of gate constructions over a first area of the substrate; depositing and etching insulative material effective to form insulative sidewall spacers over sidewalls of the first set of gate constructions, the etch stop layer restricting etching of the insulative layer during the etching of the insulative material; after forming the insulative sidewall spacers, forming and planarizing a dielectric material over the first set of gate constructions, and effective to remove all remaining of the etch stop layer from the substrate during said planarizing; after forming and planarizing the dielectric material, forming a mass of material over the substrate to a second thickness which is within ten percent of the first thickness; and after forming and planarizing the dielectric material, patterning and etching the mass of material, the insulative layer and the conductive gate layer to form a second set of gate constructions over a second area of the substrate.