Patent ID: 7003745

Claim:
An automated integrated circuit design method comprising the steps of: (a) inputting an initial layout of interconnected circuit devices that define a circuit; (b) performing a plurality of circuit simulations for the circuit, with each circuit simulation performed for a unique layout of the circuit devices, with each circuit simulation generating a design point that includes a plurality of device variables for the circuit devices and a plurality of performance goals for the circuit, wherein each device variable and each performance goal has a value associated therewith; (c) allocating the design points to a first subset of model building design points and a second subset of validation design points; (d) utilizing a first model building technique to determine as a function of the model building design points a first circuit model for one of the performance goals; (e) utilizing a second, different model building technique to determine as a function of the model building design points a second, different circuit model for the one performance goal; (f) determining for each validation design point a value for the one performance goal as a function of said first circuit model and the values of the device variables of said validation design point; (g) determining for each validation design point an error between the value of the one performance goal determined therefor in step (f) and the values of the corresponding performance goal of the validation design point; (h) determining in connection with the first circuit model an average of the errors determined in step (g); (i) determining for each validation design point a value for the one performance goal as a function of said second circuit model and the values of the device variables of said validation design point; (j) determining for each validation design point an error between the value of the one performance goal determined therefor in step (i) and the value of the corresponding performance goal of the validation design point; (k) determining in connection with the second circuit model an average of the errors determined in step (j); (l) inputting a set of values of the device variables; (m) processing the input set of values of the device variables with at least one of the first and second circuit models having the smallest average error associated therewith to determine at least one value for the one performance goal associated therewith; and (n) based on the value of the at least one performance goal determined in step (m), generating a layout of the circuit devices based on the values of the device variables input for said one performance goal in step (l).