Patent ID: 7791947

Claim:
A method comprising: adjusting a voltage threshold of a first select gate of a first NAND string electrically connected to a first bit line, the first NAND string comprising a plurality of NAND storage gates including two outer NAND storage gates, NAND[ 0 ] and NAND[N], and a plurality of inner NAND storage gates, N[ 1 ]-N[N− 1 ], between the two outer NAND storage gates, where NAND[ 0 ] is the outer NAND storage gate of the NAND string most closely coupled to the first bit line and NAND[N] is the outer NAND storage gate of the NAND string least closely coupled to the first bit line, and wherein NAND[ 0 ] is coupled in series between the first select gate and an interior NAND storage gate, NAND[I], where I is an integer between 1 and N− 1 , and wherein adjusting comprises one of adjusting the voltage threshold by increasing a relative number of primary carriers at a charge storage location of the first select gate, or decreasing the relative number of primary carriers.