Patent ID: 7068549

Claim:
A circuit for generating a DQS signal in a semiconductor memory device, comprising: a DQS data generation unit for generating a DQS preamble signal earlier than a CAS latency and generating a DQS data after generating the DOS preamble signal, according to a preamble control signal; a DQS output control signal generation unit for generating a control signal to drive the DQS preamble signal output before the CAS latency and to drive the DQS data out after the CAS latency; and a DQS driver for driving the DQS preamble signal and a rising data of the DQS data from the DQS data generation unit according to a rising clock of the DQS output control signal generation unit, and driving a falling data of the DQS data from the DQS data generation unit according to a falling clock of the DQS output control signal generation unit.