Patent ID: 8773298

Claim:
An integrated circuit including a successive approximation register A/D (analog/digital) converter which obtains a comparison result of N bits (N is a number greater than or equal to 1), the integrated circuit comprising: a conversion operation controller that determines an interruption timing of a comparison operation in the successive approximation register A/D converter on the basis of an operation timing of a predetermined circuit that interferes with an operation of the successive approximation register A/D converter, wherein the successive approximation register A/D converter obtains the comparison result of N bits by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states (M is a number greater than or equal to 1) which follows the comparison period and in which a comparison of M bits can be performed, and an operation is interrupted in accordance with the determined interruption timing and a comparison operation of a bit where the comparison is not performed enough in the comparison period due to the interruption is performed in the reserve period.