Patent ID: 7852103

Claim:
A method for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits, the integrated circuit (IC) chip including off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits respectively connected to respective off-chip C4 nodes, said method comprising the steps of: connecting Through Silicon Vias (TSVs) to the respective connections of the driver and the receiver and the respective C4 nodes, said TSVs extending to a backside of the IC chip; adding a metal wire to the chip backside connected to the TSVs to create a connection path between the driver and the receiver; and performing At-Speed Wafer Final Test (WFT) using the connection path between the driver and the receiver and the respective C4 nodes.