Patent ID: 8131790

Claim:
A decimation filter comprising: a plurality of calculating devices each having a multiplier and an accumulator; a plurality of coefficient memories which store filter coefficients, and which correspond to said calculating devices, respectively; and a selector which sequentially selects outputs of said plurality of calculating devices in synchronization with a clock signal, wherein when a decimation ratio is n, filter coefficients which are sequentially shifted by n are read out from said plurality of coefficient memories, and multiplied with a signal in said multipliers of said calculating devices, and results of the multiplications are accumulated in said accumulators to be output wherein said plurality of coefficient memories have a ring memory which stores all filter coefficients that are previously calculated, and from which the filter coefficients are sequentially cyclically read out in synchronization with said clock signal, and a plurality of shift registers which are cascade-connected to said ring memory, and wherein said shift registers have a capacity which, when the decimation ratio is n, can store an n number of filter coefficients, and filter coefficients which are read out from said ring memory are stored into and read out from said plurality of shift registers while sequentially shifting the filter coefficients.