Patent ID: 7423910

Claim:
A semiconductor memory device comprising: a plurality of memory cells each of which has a MOS transistor including a floating gate and a control gate; a memory cell array including the memory cells arranged in a matrix; word lines each of which connects commonly the control gates of the MOS transistors in the same row in the memory cell array; a row decoder which decodes a row address signal used to select any of the word lines; first MOS transistors each provided for a corresponding one of the word lines and which transfer a first voltage to the word line unselected by the row decoder, the first MOS transistor having a drain connected to the word line and a source to which the first voltage is applied; and second MOS transistors each provided for a corresponding one of the word lines and which transfer a second voltage to the word line selected by the row decoder, the second MOS transistor having a drain connected to the word line and a source to which the second potential is applied.