Patent ID: 7259419

Claim:
An integrated circuit, comprising: a plurality of isolation layers for defining a first area, a second area, and a third area in a substrate; a memory device including a floating gate formed over the first area and at least one isolation layer of the plurality of isolation layers, an inter-gate dielectric layer formed on the floating gate and including a composite layer having a silicon oxide layer and a silicon nitride layer, and a control gate formed on the inter-gate dielectric layer; a first transistor including a first gate formed of the same material as the control gate, wherein the first gate is formed in the second area of the substrate on a first gate oxide layer having a thickness greater than or equal to a thickness of a tunnel oxide layer formed on the substrate, and a first source region and a first drain region formed in the second area at least one of under or adjacent both sides of the first gate; and a second transistor including a second gate formed of the same material as the control gate, wherein the second gate is formed in the third area of the substrate on a second gate oxide layer thinner than the first gate oxide layer, and a second source region and a second drain region formed in the third area at least one of under or adjacent both sides of the second gate, wherein a first portion of the floating gate formed over the first area is narrower than a second portion of the floating gate formed over the at least one isolation layer, and wherein the control gate is formed over the second portion of the floating gate and not over the first portion of the floating gate, and a plurality of edges of the control gate do not extend to corresponding edges of the floating gate.