Patent ID: 7782289

Claim:
A timing controller for outputting a scan line data according to outputted a first, a second and a third gate output enable signals to drive a pixel level multiplexing display panel, comprising: a memory comprising an odd-field memory block and an even-field memory block; and a memory controller coupled to the memory and controlling the memory, for controlling the data output of a (I−1) th scan line stored in the odd-field memory block when two of a first, a second and a third gate output enable signals are active, and for controlling the data output of a J th scan line stored in the even-field memory block when one of the first, the second and the third gate output enable signals is active but the other two are inactive, wherein I and J are natural numbers, and I is larger than 1 and J is larger than 0, wherein the memory controller is used to output a data of the M th scan line stored in the even-field memory block and control the memory to write the odd-field field data of the (M+1) th scan line to the odd-field memory block and write the even-field field data of the (M+1) th scan line to the even-field memory block when the first gate output enable signal is active and the second and the third gate output enable signals are inactive; output the data of the (M−1) th scan line stored in the odd-field memory block when the first and the third gate output enable signals are active and the second gate output enable signal is inactive; output the data of the (M+1) th scan line stored in the even-field memory block and control the memory to write the odd-field field data of the (M+2) th scan line to the odd-field memory block and write the even-field field data of the (M+2) th scan line to the even-field memory block when the second gate output enable signal is active and the first and the third gate output enable signals are inactive; output the data of the M th scan line stored in the odd-field memory block when the first and the second gate output enable signals are active and the third gate output enable signal is inactive; output the data of the (M+2) th scan line stored in the even-field memory block and control the memory to write the odd-field field data of the (M+3) th scan line to the odd-field memory block and write the even-field field data of the (M+3) th scan line to the even-field memory block when the third gate output enable signal is active and the first and the second gate output enable signals are inactive; and output the data of the (M+1) th scan line stored in the odd-field memory block when the first and the third gate output enable signals are active and the second gate output enable signal is inactive; wherein M is a natural number, and is larger than 1.