Patent ID: 7428287

Claim:
A method for synchronizing data transmission from a transmit circuit to a receive circuit, comprising: in response to a first clock, the transmit circuit writing data into a buffer memory; in response to a second clock, the receive circuit reading the data from the buffer memory for further processing of the data; comparing the first clock and second clocks; in response to said comparing step, changing a phase relationship between the first and second clocks so that the first and second clocks are in phase with one another during said reading step, including adjusting an adjustable delay element to put the first and second clocks in phase with one another; before said step of comparing the first and second clocks, comparing a divided version of the first clock to a divided version of the second clock and, in response to said step of comparing said divided versions of the first and second clocks, adjusting the adjustable delay element to put the divided versions of the first and second clocks in phase with one another.