Patent ID: 7115926

Claim:
A DRAM construction, comprising: a pair of wordlines over a substrate, the wordlines comprising sidewall edges; carbon-containing sidewall spacers extending along the sidewall edges of the wordlines, the carbon-containing sidewall spacers consisting essentially of silicon, oxygen and from about 2% to about 20% carbon, by weight; three nodes proximate the wordlines, the three nodes comprising a first node, second node and third node, the second node being in gated electrical connection with the first node through one of the wordlines and being in gated electrical connection with the third node through the other of the wordlines; an insulative layer in contact with at least one of the carbon-comprising sidewall spacers; a first capacitor construction in electrical connection with the first node, the first capacitor construction comprising a first storage node; a second capacitor construction in electrical connection with the third node, the second capacitor construction comprising a second storage node; and a bit line contact in electrical connection with the second node, each of the first storage node, second storage node and bit line contact being in physical contact with one or more of the carbon-containing sidewall spacers.