Patent ID: 8493698

Claim:
An electrostatic discharge protection circuit comprising: a plurality of protection circuits, wherein each of the plurality of protection circuits includes a MOS transistor; and a trigger circuit configured to supply a trigger signal to a gate electrode of the MOS transistor of each of the plurality of protection circuits in response to a surge voltage between a low potential node and a high potential node, wherein each of the plurality of protection circuits is configured to electrically connect the low potential node and the high potential node to one another when the trigger signal is supplied to the gate electrode of the MOS transistor, wherein the gate electrode of the MOS transistor of each of the plurality of protection circuits is connected to a resistive element having a larger resistance value than Rmax, wherein Rmax is a largest parasitic resistance between each protection circuit of the plurality of protection circuits and an output of the trigger circuit, and wherein the MOS transistor of a predetermined protection circuit among the plurality of protection circuits includes: a plurality of gate electrodes; a plurality of source electrodes; and a plurality of drain electrodes respectively adjacent to one of the plurality of source electrodes across from one of the plurality of gate electrodes, the plurality of gate electrodes being connected in series to the resistive element.