Patent ID: 8039392

Claim:
A method for manufacturing a memory device, comprising: forming a sacrificial layer of sacrificial material; patterning the sacrificial layer to form a sacrificial member; forming a first spacer layer comprising dielectric material over the sacrificial member and on a sidewall of the sacrificial member; removing a portion of the first spacer layer to form a sidewall insulating member on the sidewall of the sacrificial member; removing the sacrificial member; forming a second spacer layer comprising electrically conductive material over the sidewall insulating member and on a first insulating member sidewall and on a second insulating member sidewall; forming a layer of dielectric material over the second spacer layer; planarizing the layer of dielectric material so as to form a planarized surface and so as to form a first surface of the second spacer layer to provide a first electrode and a second surface of the second spacer layer to provide a second electrode, the first electrode being separated from the second electrode by the sidewall insulating member; forming a bridge of memory material between the first electrode and the second electrode across the sidewall insulating member, the bridge comprising a patch of memory material contacting the first electrode and second electrode to define an inter-electrode path between the first electrode and second electrode across the sidewall insulating member having a path length defined by a thickness of the first spacer layer.