Patent ID: 7102399

Claim:
A phase-locked loop, comprising: a phase-frequency detector coupled to receive a reference signal, wherein the phase-frequency detector produces a phase control signal based upon a difference in phase between the reference signal and a low noise divided signal; a charge pump for producing a voltage controlled oscillator (VCO) control signal based upon the phase control signal; a VCO for producing an oscillation having a frequency based upon the VCO control signal; and a low-noise divider for producing the low phase noise divided oscillation, wherein the low-noise divider further includes: a pulse-swallow configured divider module for producing a pre-scaled divider output and a divided oscillation based upon the oscillation produced by the VCO; a first latching block for latching the divided oscillation based upon the pre-scaled divider output as a clock to produce a first latched signal; a second latching block for latching the first latched signal based upon the VCO oscillation as a clock to produce a second latched signal; and a third latching block for latching the second latched signal based upon the VCO oscillation as a clock to produce a third latched signal, which third latched signal is the low phase noise divided oscillation and is produced to the phase-frequency detector for comparison to the reference signal.