Patent ID: 7956641

Claim:
An interface circuit configured for translating a relatively high input voltage into a relatively low output voltage, the interface circuit comprising: a pair of input transistors having sources that are coupled together for receiving a relatively low voltage from a power supply, wherein a gate of a first one of the pair of input transistors is coupled for receiving the relatively high input voltage and wherein a gate of a second one of the pair of input transistors is coupled for receiving a reference voltage different from the relatively high input voltage; and a current sense amplifier having a pair of input terminals, each coupled to a drain of a different one of the pair of input transistors to receive a pair of differential currents and to generate a pair of differential voltages, wherein the current sense amplifier is configured to clamp gate-drain voltages of the pair of input transistors to a level that reduces stress on gate insulators of the pair of input transistors.