Patent ID: 8222695

Claim:
A process of forming an electronic device including an integrated circuit comprising: providing a substrate that includes a first semiconductor layer over a buried conductive region, wherein the first semiconductor layer has a primary surface and an opposing surface, and the buried conductive region lies closer to the opposing surface than to the primary surface; forming a first doped region within the semiconductor layer and along the primary surface of the first semiconductor layer, wherein the first doped region is part of a first current-carrying electrode of a first transistor, and the first current-carrying electrode is a source or an emitter; forming a first vertical conductive structure extending through the first semiconductor layer; wherein, in a finished device, the buried conductive region, the first vertical conductive structure, and the first doped region are electrically connected to one another; forming a second doped region within the first semiconductor layer and along the primary surface of the first semiconductor layer, wherein the second doped region is part of a second current-carrying electrode of a second transistor, and the second current-carrying electrode is a drain or a collector; and forming a second vertical conductive structure extending through the first semiconductor layer, wherein, in a finished device, the buried conductive region, the second vertical conductive structure, and the second doped region are electrically connected to one another.