Patent ID: 7804706

Claim:
A BE layout (mask) for a memory device with an array of opaque features formed in a plurality of device blocks on a clear mask substrate, comprising: (a) a device section which comprises a plurality of opaque BE shapes that are used to form active BE elements in the memory device, and a plurality of opaque dummy BE shapes that are used to form dummy BE elements in the memory device, said opaque BE shapes in adjacent device blocks have clear substrate regions formed therebetween that are substantially covered by said opaque dummy BE shapes and a certain number of opaque dummy BE shapes have openings formed therein that expose regions of clear substrate to allow alignment to WL pads in a device substrate; (b) a bond pads section comprised of an opaque film with a plurality of openings formed therein, said openings expose regions of the clear substrate to allow alignment to bonding pad regions in a device substrate; (c) a first open field section having an array of opaque dummy BE features with a first area size formed on the clear mask substrate; and (d) a second open field section having an array of opaque dummy BE features with a second area size that cover a substantial portion of the clear mask substrate wherein adjacent dummy BE features are separated by a space of clear mask substrate having a certain dimension, and said second area size is greater than said first area size.