Patent ID: 7035756

Claim:
A self-calibrating pipelined analog-to-digital converter, ADC, system comprising: a pipelined ADC for receiving an AC analog input signal and outputting a digital signal, the pipelined ADC having two or more pipeline stages, the pipeline stages each further comprising a sub-ADC block and a sub-DAC block for generating a stage output signal; means for generating a pseudo-random digital bitstream for modulating each pipeline stage output signal; a reference DAC element for comparison with each stage DAC element; a extra DAC element to substitute the one under calibration to achieve un-interrupted calibration; means for sequentially triggering calibration of each pipeline stage for the duration of a selected calibration cycle; means for calculating the average value of digital bits; means for storing a mismatch error term for each pipeline stage; means for computing an integral nonlinearity profile, INL, from the residual error terms; and means for subtracting the INL from the pipelined ADC output signal once per calibration cycle for providing a calibrated output signal.