Patent ID: 6995072

Claim:
A method of forming an interconnect in an oxide isolation region immediately adjacent to an active area of an integrated circuit, comprising: providing a substrate assembly comprising a silicon substrate having at least one vertically extending segment, wherein the at least one vertically extending segment is doped to form an active area; masking the active area with a nitride layer, wherein an edge of the nitride layer is aligned with a lateral edge of the active area that abuts an oxide isolation region; forming a trench in the silicon substrate and filling the trench with a dielectric material to form the oxide isolation region; exposing the oxide isolation region and a portion of the nitride layer to an etch process that etches the oxide isolation region faster than the nitride layer such that a portion of the oxide isolation region is removed to form a downwardly extending opening in the oxide isolation region that exposes a portion of the lateral edge of the active area; and at least partially filling the downwardly extending opening with a polysilicon material such that the polysilicon material contacts the active area to form the interconnect.