Patent ID: 7299395

Claim:
A test apparatus for testing an electronic device that outputs an output signal: a pattern generating section for generating a test pattern for testing said electronic device; an expected value generating section for generating an expected value pattern of output data to be compared with said output data to be outputted out of said electronic device based on said test pattern; an inversion cycle generating section for generating an expected value pattern of said output signal, during a cycle in which said electronic device inverts and outputs bits of said output data, by inverting the bits of the expected value pattern of said output data corresponding to the cycle wherein the output signal and the expected value comprise level H and/or level L bits, an H-level judging section for outputting H fail data indicating whether or not a bit of said output signal corresponding to a bit of the expected value pattern indicating level H is level H per bit of the expected value pattern; an L-level judging section for outputting L fail data indicating whether or not a bit of said output signal corresponding to a bit of the expected value pattern indicating level L is level L per bit of the expected value pattern; a fail memory for storing said H fail data as fail data when said output data indicates level H and stores said L fail data as fail data when said output data indicates level L; and selecting sections for switching a logic value of said H fail data with a logic value of said L fail data when said inversion cycle generating section inverts the bits of said expected value pattern in storing in said fail memory.