Patent ID: 8643408

Claim:
A flip-flop circuit, comprising: first and second inputs; a first output coupled to the second input; a second output coupled to the first input; first and second switches coupled in series between the first input and the first output, a first intermediate node between the first and second switches, a second intermediate node between the second switch and the first output; third and fourth switches coupled in series between the second input and the second output, a third intermediate node between the third and fourth switches, a fourth intermediate node between the fourth switch and the second output; a first cross-coupled gates arrangement coupled between the first and third intermediate nodes; a second cross-coupled gates arrangement coupled between the second and fourth intermediate nodes; and wherein the first and third switches are configured to be closed in response to a first level of a clock signal and opened in response to a second level of the clock signal; and the second and fourth switches are configured to be opened in response to the first level of the clock signal and closed in response to the second level of the clock signal.