Patent ID: 7795071

Claim:
A method of manufacturing a semiconductor package, comprising the following steps of: providing a carrier; forming a plurality of electrically isolated package trace layout units formed by a first patterned conductive layer having a first top surface and a first bottom surface, wherein each package trace layout unit is formed by a plurality of electrically isolated package traces; forming a second patterned conductive layer having a second top surface and a second bottom surface, the second bottom surface disposed on the first top surface; forming a first insulating layer formed by a molding material, wherein the first insulating layer has a third top surface and a third bottom surface, the first patterned conductive layer and the second patterned conductive layer are disposed inside the first insulating layer, the first bottom surface of the first patterned conductive layer and the third bottom surface of the first insulating layer are located at the same plane, the second top surface of the second patterned conductive layer and the third top surface of the first insulating layer are located at the same plane, the whole area of the first insulating layer is smaller than the whole area of the carrier, and the whole area of the first insulating layer is enclosed within the whole area of the carrier; and selectively removing part of the carrier to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of the first insulating layer, and the positioning opening corresponds with an outside area of the first insulating layer.