Patent ID: 8432740

Claim:
A method of programming a non-volatile memory device, comprising: applying pulses forming a staircase of increasing amplitude to a first wordline; after applying each pulse to the first wordline, performing a verifying operation for memory cells along the first wordline, wherein the series of pulse is applied to the first wordline as a series of a plurality of N subsets of the staircase, the series including at least a first subset and a second subset, wherein the first subset includes the first and every Nth subsequent pulse of the staircase applied sequentially in order of increasing amplitude, the second subset includes the second and every Nth subsequent pulse of the staircase applied sequentially in order of increasing amplitude, and the second subset is applied subsequent to applying the first subset; locking out the memory cells along the first wordline from further programming in response to verifying at the subset's verify level corresponding to the cells' target data state, wherein each subset uses a different set of verify levels for verify operations; and subsequent to applying the first subset and prior to applying the second subset, unlocking the memory cells along the first wordline to allow further programming.