Patent ID: 7786520

Claim:
A merged memory with logic (MML) semiconductor device comprising: a substrate; gates formed on the substrate; a source region and a drain region formed on respective sides of each of the gates in the substrate; a first interlayer dielectric (ILD) layer which covers the gates and the source/drain regions; first via plugs which vertically penetrate the first ILD layer and selectively connect to the source/drain regions; capacitors and second via plugs selectively connected to the first via plugs; a second ILD layer fills between the capacitors and the second via plugs; planarization resistance patterns formed on the second ILD layer, wherein the planarization resistance patterns include an upper resistance pattern formed of a material used as a top electrode of the capacitors, and wherein the planarization resistance patterns include a lower resistance pattern formed of a material used as a dielectric layer of the capacitors, the upper resistance pattern and the lower resistance pattern being separated by a capacitor dielectric layer; a third ILD layer formed on the second ILD layer and the planarization resistant patterns; and third via plugs which vertically penetrate the third ILD layer, and selectively connected to the top electrode of the capacitors and the second via plugs.