Patent ID: 7688972

Claim:
A method for accelerating cryptography operations, the method comprising: performing by one or more processors and/or circuits integrated within a single chip: generating at least a first signal that indicates completion of a round of a Kasumi FI processing when cryptographically processing information; transferring a first output generated from a first round of said Kasumi FI processing and a second output generated from a second round of said Kasumi FI processing to a pipeline register; XORing a third output generated from a third round of said Kasumi FI processing with said second output generated from said second round of said Kasumi FI processing to generate a first portion of an Kasumi FI generated output; and clocking said second output generated from said second round of said Kasumi FI processing from said pipeline register to generate a second portion of said Kasumi FI generated output, after said at least said first signal indicates that said second round of said Kasumi FI processing is complete, wherein resulting information from said cryptographic processing is communicated to a remote location for further processing.