Patent ID: 8884643

Claim:
An electronic circuit arrangement for processing binary input Values xεX of word width n(n>1), comprising: a first combinational circuit component configured to process the binary input values x to form a first binary output value of word width a 1 (a 1 ≧1) and to provide the first binary output value at the output of the first combinational circuit component, the output of the first combinational circuit component being provided with a number of binary outputs A 1 (A 1 >1), wherein A 1 ≧a 1 , a second combinational circuit component configured to process the binary input values x to form a second binary output value, a third combinational circuit component configured to process the binary input values x to form a third binary output value, and a majority voter element, the input of which, for receiving the respective binary input values, is connected with the outputs of the first, second and third combinational circuit components, the majority voter element being configured to provide a majority signal at its output in dependence on the received binary output values, wherein the second and third combinational circuit components are configured, as regards faults during processing of the binary input values x in the first combinational circuit component, to process, for the first binary output value of word width a 1 , binary input values of a true non-empty subset X 1 of the set of binary input values X in a fault-tolerant manner and binary input values of a further non-empty subset X 2 of the set of binary input values X in a non-fault-tolerant manner, the further non-empty partial quantity X 2 being different from the true non-empty subset X 1 ; wherein the second and third combinational circuit components are designed to incorporate the following features: in a fault-free case the second binary output value of the second combinational circuit component and the third binary output value of the third combinational circuit component are equal to the first binary output value of the first combinational circuit component, for all binary input values of the non-empty proper subset X 1 ; for all binary input values from the further non-empty subset X 2 the second binary output value of the second combinational circuit component and the third binary output value of third combinational circuit component are non-equal, and for all binary input values of the subset X 1 the following is true: for each bit of the first binary output value of word width a1: at least the second binary output value of the second combinational circuit component or at least the third binary output value of the third combinational circuit component is equal to the first binary output value of the first combinational circuit component.