Patent ID: 7868606

Claim:
A circuit for sensing a global process variation in an integrated circuit device, comprising: a first transistor, a second transistor, a third transistor, and a fourth transistor, each transistor having a gate terminal, a first source/drain terminal, and a second source/drain terminal, the first transistor and the third transistor being negative-channel type transistors, and the second transistor and the fourth transistor being positive-channel type transistors, wherein: for the first transistor, the gate terminal is coupled to a bias voltage node, the first source/drain terminal is coupled to a ground node, and the second source/drain terminal is coupled to a sense voltage node; for the second transistor, the gate terminal is coupled to the first source/drain terminal, which is coupled to a voltage source node, and the second source/drain terminal is coupled to the sense voltage node; for the third transistor, the gate terminal is coupled to the first source/drain terminal, which is coupled to the ground node, and the second source/drain terminal is coupled to the bias voltage node; for the fourth transistor, the gate terminal is coupled to the first source/drain terminal, which is coupled to the voltage source node, and the second source/drain terminal is coupled to the bias voltage node; such that when the first transistor, the second transistor, the third transistor, and the fourth transistor are operated in a subthreshold region of transistor operation and their threshold voltages shift in a similar manner, a global process variation in the integrated circuit device is monitored at the sense voltage node.