Patent ID: 7847413

Claim:
A semiconductor device comprising: a first wiring substrate having a first main surface and a first back surface opposed to the first main surface; a plurality of first bonding leads formed on the first main surface of the first wiring substrate; a microcomputer chip mounted over the first main surface of the first wiring substrate; a second wiring substrate disposed over the microcomputer chip and having a second main surface, a second back surface opposed to the second main surface, a plurality of second bonding leads formed on the second back surface, a first internal wiring line formed between the second main surface and the second back surface, and a second internal wiring line formed between the second main surface and the second back surface; a first memory chip having a first electrode pad electrically connected with one of the second bonding leads via the first internal wiring line, and arranged between the second main surface and the second back surface; a second memory chip having a second electrode pad electrically connected with one of the second bonding leads via the second internal wiring line, and arranged between the second main surface and the second back surface; a plurality of first bump electrodes electrically connecting the first bonding leads of the first wiring substrate with respective second bonding leads of the second wiring substrate; and a plurality of second bump electrodes disposed over the first back surface of the first wiring substrate, wherein a length of the first internal wiring line is substantially the same as a length of the second internal wiring line, wherein the microcomputer chip is electrically connected with the first memory chip via one of the first bonding leads, one of the first bump electrodes, a corresponding one of the second bonding leads, and the first internal wiring line, and is also electrically connected with the second memory chip via said one of the first bonding leads, said one of the first bump electrodes, said one of the second bonding leads, and the second internal wiring line, and wherein the first and second memory chips are controlled by the microcomputer chip, are double data rate SDRAMs, and are configured to transfer data in synchronism with both leading and trailing edges of an external clock signal.