Patent ID: 8395922

Claim:
A semiconductor memory device comprising: a memory cell array including: a plurality of first memory cell units, each of the plurality of first memory cell units including a plurality of memory cells; a plurality of second memory cell units, each of the plurality of second memory cell units including a plurality of memory cells; a plurality of first interconnects, each of the plurality of first interconnects extending in a first direction and being connected to one end of each of the first memory cell units; and a plurality of second interconnects, each of the plurality of second interconnects extending in the first direction and being connected to one end of each of the second memory cell units, heights of upper surfaces of the second interconnects being equal to heights of upper surfaces of the first interconnects; a first sense amplifier circuit connected to the plurality of first interconnects; and a second sense amplifier circuit connected to the plurality of second interconnects, the plurality of first interconnects and the plurality of second interconnects formed adjacent to each other being formed of a structure in which a plurality of pairs are repeated, and at least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction being set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit being disposed to face each other across the memory cell array.