Patent ID: 8039338

Claim:
A method of forming a CMOS device, the method comprising: forming a gate electrode material on a gate insulation layer; forming a first mask above said gate electrode material, said first mask covering a first portion of said gate electrode material and exposing a second portion of said gate electrode material; performing a first tilted implantation process to form an N-doped region in said second portion of said gate electrode material, wherein said first mask reduces N-type dopant penetration into a junction region of said gate electrode material between said first and second portions during said first tilted implantation process; forming a second mask above said gate electrode material, said second mask covering said second portion and exposing said first portion; performing a second tilted implantation process to form a P-doped region in said first portion of said gate electrode material, wherein said second mask reduces P-type dopant penetration into said junction region during said second tilted implantation process; forming a first gate electrode from said N-doped region; forming second gate electrode from said P-doped region; and performing a wet chemical cleaning process on said first and second gate electrodes.