Patent ID: 6838943

Claim:
An equalizer circuit for equalizing first and second differential input signals, the equalizer circuit comprising: a differential pair defining first and second input nodes and first and second output nodes; a reactive load circuit coupled to the differential pair; a first input follower circuit connected to the first input node of the differential pair, the first input follower circuit operable to receive the first differential input signal and to receive a first feedback signal from the differential pair and in response to generate a first input signal at the first input node of the differential pair; and a second input follower circuit connected to the second input node of the differential pair, the second input follower circuit operable to receive the second differential input signal and to receive a second feedback signal from the differential pair and in response to generate a second input signal at the second input node of the differential pair; wherein the first and second differential input signals are balanced DC signals, and the equalized first and second differential output signals are generated at the first and second output nodes, respectively.