Patent ID: 8839029

Claim:
A microcontroller comprising: a first data processing unit that executes a processing and outputs first write data; a second data processing unit that executes the processing and outputs second write data; a first compressor that compress and retains the first write data; a second compressor that compress and retains the second write data; a comparator that compares the first retained write data and the second retained write data; and a detection unit, comprising a comparison control register (CR) and a comparison result register (FR), wherein the detection unit detects an abnormality of the first data processing unit and the second data processing unit, wherein the first data processing unit outputs a first enable signal to the CR when the first data processing unit completes the processing, wherein the second data processing unit outputs a second enable signal to the CR when the second data processing unit completes the processing, wherein the detection unit fetches a comparison result of the comparator and stores the comparison result of the comparator to the FR when both the first processing unit and the second processing unit output the first enable signal and the second enable signal, and wherein the first write data and the second write data are data used to check whether or not the first data processing unit and the second data processing unit execute the same processing normally.