Patent ID: 7199564

Claim:
A voltage booster converter comprising: a pair of input terminals A and B for connecting a DC input voltage Vin between these two terminals; a pair P 0 of switches SB, SH in series connected by the switch SB to the input terminal B, the input terminal A being connected across an input inductor Lin to the connection point between the two switches SB and SH in series, each switch SB, SH comprising control means so as to be placed simultaneously, one in an on state the other in an isolated state; a pair of output terminals C and D, for powering, by an output voltage Vout, a load Rout, the output terminal D being connected to the input terminal B, wherein: K other additional pairs P 1 , P 2 , . . . P i , . . . P K−1 , P K of switches in series with the pair P 0 between the output terminal C and the switch SH with i=1, 2, . . . K−1, K, the two switches of one and the same additional pair P i being connected across an energy recovery inductor Lr i ; K input groups, Gin 1 , Gin 2 , . . . Gin i , . . . Gin K−1 , Gin K , of Ni capacitors C of like value each in series, with i=1, 2, . . . K− 1 , K and Ni=i, the electrode of the capacitors of one of the two ends of each input group being connected to the common point between the two switches SB, SH of the pair P 0 , at least the electrode of the capacitors of each of the other ends of the input groups being connected respectively to the common point between each the switch SH i and the recovery inductor Lr i of the corresponding pair P i of like rank i, K output groups, Gout 1 , Gout 2 , . . . Gout i , . . . Gout K−1 , Gout K , of Mi capacitors C of like value each in series, with i=1, 2, . . . K and Mi=(K+1)−i, the electrode of the capacitors of one of the two ends of the output groups being connected to the output terminal C, at least the electrode of the capacitors of each of the other ends of the output groups being connected respectively to the connection point between two pairs of consecutive switches P i−1 , and P i ; in that the switches of these other K additional pairs are controlled so as to form, when the switch SB of the pair P 0 linked to the terminal B is switched to the on state for a time Ton, a first capacitor network connected on the one hand across the switch SB to the terminal B and, on the other hand, to the terminal C, comprising the groups of input capacitors in series with the groups of the output capacitors such that a group of input capacitors Gin i is in series with its respective group of output capacitors Gout i , and in that when the switch SB of the pair P 0 linked to the input terminal B is switched to the isolated state for a time Toff these other K pairs of switches form a second capacitor network connected to the terminal A across the input inductor Lin comprising the input group Gin K in parallel with the output group Gout 1 , in parallel with groups of input capacitors in series with groups of the output capacitors such that a group of input capacitors Gin i−1 is situated in series with a group of output capacitors Gout i .