Patent ID: 6875658

Claim:
A high-voltage device process compatible with a low-voltage device process for a high-voltage device with improved punch through voltage, comprising steps of: proving a semiconductor silicon substrate comprising a high-voltage device region and a low-voltage device region, wherein each of the high-voltage device region and the low-voltage device region comprises a gate structure formed on the substrate, a lightly doped region formed in the substrate and lateral to the gate structure, and a spacer formed on the sidewall of the gate structure; forming a first photoresist layer on the substrate to cover the high-voltage device region; performing a first heavy implantation in the low-voltage device region with the gate structure and the spacer as a mask to form a first heavily doped region in the exposed portion of the lightly doped region; removing the first photoresist layer; forming a resist protection oxide layer on the substrate to cover the high-voltage device region and the low-voltage device region; forming a second photoresist layer on the substrate to cover the low-voltage device region; and performing a second heavy implantation in the high-voltage device region with the gate structure and the spacer as a mask to form a second heavily doped region in the exposed portion of the lightly doped region, wherein, a lateral distance is kept between an outside edge of the spacer and the second heavily doped region.