Patent ID: 7833857

Claim:
A method of manufacturing an ESD protecting circuit, the method comprising: forming a device isolation layer in a field region of a semiconductor substrate having a first conductivity type; forming a first well and a second well in the semiconductor substrate; forming a first high-concentration impurity region in the first and second wells and a second high-concentration impurity region in the first well, the first and second high-concentration impurity regions having a second conductivity type; forming a third high-concentration impurity region in the first well on one side of the second high-concentration impurity region, the third high-concentration impurity region having the first conductivity type; and forming a fourth impurity region below the first high-concentration impurity region at a boundary between the first and second wells, the fourth impurity region having the second conductivity type, wherein the first well is in contact with and below the second and third high-concentration impurity region.