Patent ID: 7934110

Claim:
An apparatus comprising: a plurality of cores, a sensor logic to generate a thermal interrupt in response to sensing temperature levels on the plurality of cores, an interleaving logic coupled to the sensor logic, wherein the interleaving logic is to, determine if core hopping is applicable wherein core hopping applicable if there exists at least one core in a cold state and if a rate of occurrence of core bopping is within a allowable rate value, generate a core hop signal if the core hopping is applicable, and provide a thermal trigger to initiate throttling if the core hopping is not applicable, a core hopping logic coupled to the interleaving logic, wherein the core hopping logic is to transfer execution of threads from a first core to a second core in response to receiving the core hop signal, and a throttling logic coupled to the interleaving logic, wherein the throttling logic is to change one or more throttling parameters to throttle the first core if the core hoping is not applicable.