Patent ID: 8327311

Claim:
A method of generating one or more functions for activating processes in a simulation model of a circuit design, comprising: using a processor to perform one or more of: determining at least two mutually exclusive sub-ranges of a plurality of bits of a net of the circuit design, each of the sub-ranges including at least one bit of the plurality of bits of the net; determining a respective process set associated with each sub-range of the plurality of bits, wherein each process set specifies one or more processes to activate in response to a change in value of a bit in the associated sub-range of the plurality of bits; and generating a specification of a wakeup function in the simulation model, wherein the specification includes: for each sub-range of the plurality of bits, a test for a change in value of at least one bit in the sub-range of the plurality of bits, and an initiation of each process in the associated process set in response to a detected change in value of the at least one bit; and control, responsive to a detected change in value of at least one bit in one of the sub-ranges of the plurality of bits, that bypasses a test for a change in value of at least one bit in at least one other of the sub-ranges of the plurality of bits.