Patent ID: 7339846

Claim:
A method for reading memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of cells including a first cell and a last cell, each of the cells in the plurality sharing a bit line with each of its adjacent cells, the first and last cells being further connected to first and last bit lines, respectively, which are not shared with any other cells in the plurality, the bit lines including a first group of at least one adjacent bit line and a last group of at least one adjacent bit line distinct from the first group, the first group being adjacent to the first bit line and the last group being adjacent to the last bit line, the method comprising the steps of: precharging both first and last common bit lines to respective precharged states, the first common bit line being the bit line in the first group that is shared with the first cell in the plurality, and the last common bit line being the bit line in the last group that is shared with the last cell in the plurality; and while both the first and last common bit lines are in their respective precharged states, initiating a sense operation to read both the first and last cells substantially simultaneously, wherein the step of precharging both the first and last common bit lines to respective precharged states comprises the step of precharging to respective precharge states all of the bit lines in the first and last groups of bit lines, and wherein the step of precharging to respective precharge states all of the bit lines in the first and last groups of bit lines comprises the steps of: precharging to respective precharge states all of the bit lines in the first group of bit lines to a first precharge voltage; and precharging to respective precharge states all of the bit lines in the last groups of bit lines to a second precharge voltage.