Patent ID: 7307447

Claim:
An electronic circuit comprising: a data input node, a select input node, and an output node; a plurality of segments arranged in parallel relative to the data input node and the output node, each segment having a pair of transistors and associated resistors; a plurality of pre-buffers, each providing an on/off gate signal to the pair of transistors within one of the segments and which each receive a data input and a complement of the data input and a select signal input that enables individualized selection of one of the data input and the complement data input as the on/off gate signal for that segment; a resistor coupled between a gate input of a first segment and a gate input of a second segment, wherein gate inputs of multiple adjacent segments may be so connected within the plurality of segments; means for enabling said plurality of segments to generate a desired output voltage amplitude utilizing the select signal inputs to turn specific transistors of the pair of transistors in each segment on or off; and means for controlling a slew rate of the circuit's output voltage by selectively turning off the gate input signal from the second segment's pre-buffer and providing the gate input from the first segment through the resistor, such that a delay in providing the gate input and subsequently switching the segment on is registered across the overall output of the plurality of segments.