Patent ID: 7447805

Claim:
A buffer chip for operating with a memory arrangement, comprising: a first data interface for receiving, via a data bus, a first data item and a write command for writing the first data item to the memory arrangement, and for sending a second data item which is read from the memory arrangement; a conversion unit for parallelizing the received first data item and for serializing the second data item; a write buffer for storing the parallelized first data item; a second data interface for writing the parallelized first data item from the write buffer to the memory arrangement via a memory data bus in the course of performing the write command, and for receiving the second data item read from the memory arrangement via the memory data bus; and a control unit configured to, upon receiving a subsequent read command after performance of the write command has been initiated but prior to completion of the write command, suspend completion of the write command by interrupting the parallelized first data item from being written from the write buffer via the second data interface, wherein a portion of the parallelized first data item has been written to the memory arrangement while a remainder of the parallelized first data item is stored in the write buffer, in order to read the second data item from the memory arrangement into the buffer chip via the second data interface.