Patent ID: 7223622

Claim:
A method of fabricating an active-matrix substrate, comprising: (a) providing a transparent dielectric base; (b) forming TFTs, gate lines, and data lines on the base; the gate lines being arranged at intervals on the base; data lines being arranged at intervals on the base to intersect with the gate lines, forming intersections; the TFTs being arranged near the respective intersections of the gate lines and the data lines; (c) forming a transparent dielectric layer on the base to cover the TFTs, the gate lines, and the data lines; (d) selectively etching the transparent dielectric layer to form transparent dielectric portions on the base; the portions being arranged in a matrix array in such a way as to form a first plurality of recesses extending along the respective gate lines and a second plurality of recesses extending along the respective data lines; each of the portions forming a pixel regions with a flat surface; each of the portions having a thickness equal to or greater than a maximum height of the TFTs, the gate lines, or the data lines with respect to a specific reference level; each of the portions having a distance equal to or greater than the thickness thereof from a corresponding one of the TFTs, the gate lines, or the data lines; (e) selectively forming a planarization layer to fill at least the first plurality of recesses and the second plurality of recesses; and (f) forming pixel electrodes arranged on or over the flat surfaces of the respective portions; each of the pixel electrodes having a connection part formed on the surface of the planarization layer to extend over a corresponding one of the second plurality of recesses; the connection part being connected to a corresponding one of the TFTs by way of a corresponding one of holes of the planarization layer.