Patent ID: 8115558

Claim:
A digital phase-locked loop circuit, comprising: an oscillation circuit configured to include an inductance element and a capacitance element and to oscillate at a frequency in accordance with an LC value, wherein an oscillation frequency is controlled by changing a number of the capacitance element to be connected in parallel to the inductance element; and a phase comparator part configured to detect an amount of a phase lead or a phase lag of an output of the oscillation circuit by performing a digital phase comparison of a reference clock and a delayed clock which is successively delayed by a predetermined unit time from the reference clock, with an oscillation output of the oscillation circuit, and based on a detected amount of the phase lead or the phase lag, to control the number of the capacitance element to be connected in parallel to the inductance element thereby controlling the oscillation frequency of the oscillation circuit so as to bring a phase of the output of the oscillation circuit closer to a phase of the reference clock, wherein the capacitance element comprises: at least one coarse adjustment capacitor configured to have a predetermined capacitance and be connectable in parallel to the inductance element; and a plurality of fine adjustment capacitors configured to be connectable in parallel to the at least one coarse adjustment capacitor, wherein each fine adjustment capacitor of the plurality of fine adjustment capacitors has a capacitance of 1/n (wherein n is a positive integer) of the capacitance of the at least one coarse adjustment capacitor, and a predetermined number of fine adjustment capacitors of the plurality of fine adjustment capacitors are controlled as one coarse adjustment capacitor at a time of coarse adjustment.