Patent ID: 8402405

Claim:
A method for correcting gate-level simulation comprising the steps of: identifying, by using a computer, unknown values (Xs) that are false when simulating a given trace of a design netlist; determining a sub-circuit of the design netlist for each false X having inputs of real Xs and an output of a false X; and generating code to correct each false X in simulation based on the sub-circuit to eliminate false Xs in simulation of the design netlist; wherein the step of identifying Xs that are false further comprises the steps of: tracing a fan-in cone of input of storage devices along gates that have X values to build the sub-circuit; building a Boolean function from the sub-circuit; and using a Boolean solver to determine whether the output of the sub-circuit is constant; and wherein the step of generating code to correct each false X in simulation comprises: traversing the inputs of the sub-circuit to generate code that checks for a condition for false X to occur based on its logic simulation value; and generating code to replace the X on the output of the sub-circuit with a non-X value when the condition matches and to disable value overwrite when the condition does not match.