Patent ID: 7925857

Claim:
A method of generating a cache directory to include a plurality of associativity classes, each associativity class including an address tag including a plurality of address bits, each address tag configured to store a unique address to a specific location in an memory space, the method comprising the actions of: a. determining an amount of memory that is in an actually configured portion of the memory space; b. determining a minimum number of bits necessary to address each memory location in the actually configured portion of the memory space; c. configuring each address tag in each associativity class to include the minimum number of bits necessary to address each memory location in the actually configured portion of the memory space; d. configuring the cache directory to include a maximum number of associativity classes per line in the cache directory; and e. normalizing a system address so as to generate a cache directory address used to access the cache directory, wherein the memory space comprises a plurality of nodes, in which each node is configurable up to a predetermined maximum memory capacity, and wherein the action of determining an amount of memory that is in an actually configured portion of the memory space comprises the action of mapping an amount of memory actually configured in each node into a memory map in which the amount of memory actually configured in each node is contiguous with the amount of memory actually configured in another node.