Patent ID: 8455342

Claim:
A mask ROM fabrication method comprising: Step 1: forming a gate dielectric layer on a substrate and a first photoresist layer on the gate dielectric layer; Step 2: letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm and revealing a portion of the gate dielectric layer; Step 3: doping the substrate to form a plurality of embedded bit lines corresponding to the first trenches; Step 4: removing the first photoresist layer; Step 5: forming a polysilicon layer on the gate dielectric layer and a second photoresist layer on the polysilicon layer; Step 6: letting the light pass through a second phase shift mask to photolithographically form on the second photoresist layer a plurality of second trenches revealing a portion of the polysilicon layer; Step 7: using an etching process to selectively remove a plurality of sacrifice regions of the polysilicon layer, which are corresponding to the second trenches, and removing the second photoresist layer to form a plurality of polysilicon word lines on the gate dielectric layer.