Patent ID: 7151682

Claim:
A nonvolatile memory, comprising a first content addressable memory (CAM) cell, wherein the first CAM cell comprises a latch to store volatile binary information and to provide the volatile binary information to an output terminal of the first CAM cell, wherein the first CAM cell further comprises: a first nonvolatile memory cell having a floating gate, a control gate, a drain, and a source coupled to ground; a second nonvolatile memory cell having a floating gate, a control gate coupled to the control gate of the first nonvolatile memory cell, a drain, and a source coupled to ground; a first transistor having a gate, a source coupled to the drain of the first nonvolatile memory cell, and a source; and a second transistor having a gate coupled to the gate of the first transistor, a source coupled to the drain of the second nonvolatile memory cell, and a source; a third transistor having a gate, a drain coupled to a drain of the first transistor, and a source coupled to receive a voltage potential; and a fourth transistor having a gate coupled to the drain of the third transistor, a drain coupled to coupled to the gate of the third transistor, and a source coupled to receive the voltage potential, wherein the drain of the fourth transistor is coupled to the output terminal of the first CAM cell.