Patent ID: 7378727

Claim:
An integrated circuit including a memory device comprising: first conductive lines running along a first direction; second conductive lines running along a second direction, the second direction intersecting the first direction, each of the second conductive lines having a line width wl; memory cells being at least partially formed in a semiconductor substrate, each memory cell being accessible by addressing corresponding ones of said first and second conductive lines; and landing pads made of a conductive material, each of the landing pads being configured to be connected with a corresponding one of said second conductive lines, wherein each of said landing pads has a width wp and length lp, the width wp being measured perpendicularly with respect to the second direction, the length lp being measured along the second direction; wherein the width wp of each of the landing pads is larger than the line width wl and a length lp of each of the landing pads is larger than the line width wl; and wherein the landing pads are arrange in a staggered fashion with respect to the second direction and with an increasing distance with respect to a reference position of the memory device, the distance being measured along the second direction.