Patent ID: 8178408

Claim:
A method of manufacturing a charge trap-type non-volatile memory device, the method comprising: forming an isolation layer pattern extending in a first direction in a substrate; forming recess units in a surface of the substrate by recessing the surface of the substrate that is adjacent the isolation layer pattern; sequentially forming a tunnel insulating layer and a charge trap layer on the substrate; patterning the tunnel insulating layer and the charge trap layer to form isolated islands of the patterned tunnel insulating layer and charge trap layer by removing defined regions of the tunnel insulating layer and the charge trap layer until a top surface of the charge trap layer that is disposed along a bottom surface of the recess units is aligned with a top surface of the isolation layer pattern; forming a blocking insulating layer to cover the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate between the charge trap patterns; and forming a gate electrode pattern on the blocking insulating layer to face the charge trap layer pattern, wherein patterning the tunnel insulating layer and the charge trap layer comprises: forming a buffer layer on the charge trap layer after forming the charge trap layer; partially removing the buffer layer until the charge trap layer that is on the isolation layer pattern is exposed; etching the charge trap layer that is on a region other than the bottom surface of the recess unit until the charge trap layer remains only on the bottom surface of the recess unit, and forms an isolated island-shaped charge trap layer pattern; and removing defined regions of the isolation layer pattern, the buffer layer, the tunnel insulating layer, and the substrate until the charge trap layer pattern is exposed.