Patent ID: 6920074

Claim:
A method for reading a memory cell in a semiconductor memory, which comprises: providing a first bit line having a first portion connected to a memory cell and a second portion; providing a second bit line having a first portion and a second portion, the first portion of the second bit line running opposite the first portion of the first bit line; providing a sense amplifier having a first connection and a second connection carrying a complementary signal with respect to the first connection of the sense amplifier; providing a first switch for connecting the first portion of the first bit line to the first connection of the sense amplifier; providing a second switch for connecting the first portion of the second bit line to the second connection of the sense amplifier; providing a third switch for connecting the second portion of the first bit line to the first connection of the sense amplifier; providing a fourth switch for connecting the second portion of the second bit line to the second connection of the sense amplifier; providing a first precharging circuit connected to the first portion of the first bit line and connected to the first portion of the second bit line; providing a second precharging circuit connected to the second portion of the first bit line and connected to the second portion of the second bit line; in a first phase, controlling the first switch, the second switch, the third switch, and the fourth switch to be conductive; in a subsequent second phase, controlling the third switch to be blocked while the first switch, the second switch and the fourth switch are conductive and the memory cell is coupled to the first portion of the first bit line for reading a stored data value; in a subsequent third phase, controlling the third switch and the fourth switch to be blocked while the first switch and the second switch are conductive and the sense amplifier is enabled for amplification; and in a subsequent fourth phase, controlling the first switch, the second switch, the third switch and the fourth switch to be conductive.