Patent ID: 8019943

Claim:
A non-volatile memory device (NVMD) comprising: a central processing unit (CPU); a data cache subsystem coupled to the CPU, said data cache subsystem being initialized by a method comprises: (a) receiving a power on or reset signal in the NVMD; (b) retrieving a tag, an index, a set number and a number-of-hits flag from a spare area of a first page of a block in the first type of NVM; (c) loading stored data from data area of all of the pages of the block of the first type of NVM into a particular cache line in the data cache subsystem when the particular cache line is empty, wherein the particular cache line is determined by the retrieved index and the retrieved set number; (d) otherwise loading the stored data from data area of all of the pages of the block of the first type of NVM into the particular cache line only if the retrieved number-of-hits flag shows a number greater than number-of-hits already stored in the cache line; and repeating (a)-(d) for another block of the first type of NVM until there is no more blocks; at least one non-volatile memory (NVM) module configured as a data storage of a host as the NVMD is operatively adapted to the host, said at least one non-volatile memory module having first and second types of NVM arranged in a hierarchical scheme with the first type of NVM configured as a buffer between the data cache subsystem and the second type of NVM; a NVM controller, coupling to the CPU, configured for managing said at least one NVM module; and an input/output (I/O) interface, coupling to the NVM controller, configured for receiving incoming data from the host to the data cache subsystem and configured for sending outgoing data from the data cache subsystem to the host.