Patent ID: 7437340

Claim:
A method for testing a circuit design, the method comprising: (a) extracting one or more operations that are defined via data providing a behavioral description of a circuit to be tested; (b) comparing a first circuit area used for implementing a first testing technique and a second circuit area used for implementing a second testing technique, wherein the first testing technique is used for testing one of the extracted operations before generating an expanded description of the extracted operation, and the second testing technique is used for testing one or more of the individual circuit elements associated with the expanded description of the extracted operation; (c) selecting the first testing technique and adding a description for the first testing technique to a description of the circuit to be tested before expanding the extracted operation into the expanded description, if the first circuit area is smaller than the second circuit area; (d) selecting the second testing technique and adding a description for the second testing technique to a description of the circuit to be tested after expanding the extracted operation into the expanded description, if the second circuit area is smaller than the first circuit area; and (e) generating data representing an RTL (register transfer level) description of the circuit incorporating the selected testing technique from the behavioral description, wherein the extracted operation is expanded into the expanded description of the operation when generating the data.