Patent ID: 7749832

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a gate dielectric material over a workpiece; forming a thin layer of conductive material over the gate dielectric material, the thin layer of conductive material physically contacting the gate dielectric material; forming a layer of semiconductive material over the thin layer of conductive material; and patterning the layer of semiconductive material, the thin layer of conductive material, and the gate dielectric material to form at least one PMOS transistor, wherein the gate dielectric material comprises a gate dielectric of the at least one PMOS transistor, wherein the layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of the at least one PMOS transistor, and wherein forming the thin layer of conductive material comprises forming a layer of conductive material comprising a thickness such that the thin layer of conductive material has a substantially negligible effect on a work function of the gate electrode of the at least one PMOS transistor.