Patent ID: 8441941

Claim:
An apparatus comprising: one or more processors; a non-transitory computer readable storage medium comprising one or more stored sequences of instructions which, when executed by one or more processors, cause the one or more processors to: generate a reference model of a bridged network representing a plurality of nodes in the bridged network, wherein each of the plurality of nodes implements a loop-free topology algorithm; determine an expected data path based on the reference model of the bridged network; receive information representing an actual data path in the bridged network; wherein the actual data path is determined by monitoring one or more components along the actual data path in the bridged network; and compare the expected data path based on the reference model and the actual data path in the bridged network to identify a divergence point from which the expected data path and the actual data path differ; wherein the divergence point represents a particular node from which outbound data, intended for a destination node, is sent to a receiving node on the actual data path that is different than an expected receiving node on the expected data path; responsive to identifying the divergence point, performing one or more of: presenting the divergence point to a user; reconfiguring the divergence point based on the reference model; updating the reference model based on the divergence point.