Patent ID: 8164369

Claim:
An apparatus comprising: a voltage controlled oscillator (VCO); an advanced reference clock configured to output an advanced reference clock signal; a programmable delay coupled to advanced reference clock configured to delay the advanced reference clock signal to produce a reference clock signal; a divider circuit coupled to the VCO and configured to receive a signal from the VCO and to output a divider clock signal and an advanced divider clock signal; a phase frequency detector (PFD) coupled to the programmable delay and to the divider, and configured to: receive the divider clock signal; receive the reference clock signal; provide a phase comparison operation; and output an UP pulse and a DOWN pulse; a loop filter configured to generate a control voltage to lock the VCO to a desired operating frequency; a charge pump configured to generate an output signal to the loop filter in response to at least one of the UP pulse and the DOWN pulse; a sampling switch coupled to an input of the loop filter and an output of the charge pump, and characterized by a sampling interval; and a sampling switch controller coupled to the sampling switch, the advanced divider clock signal, the advanced reference clock signal, the UP pulse and the DOWN pulse, and configured to adaptively control a width of the sampling interval to mitigate effects of noise current from the charge pump by closing the sampling switch in advance of the phase comparison operation and opening the sampling switch when the phase comparison operation is completed.