Patent ID: 7478474

Claim:
A method of manufacturing shielded electronic circuit units, the method comprising: forming electronic components and a sealing resin portion in an assembly substrate, the electronic components being mounted so as to correspond to individual multi-layered substrates, the sealing resin portion burying the electronic components; forming slit portions in the assembly substrate and the sealing resin portion at locations between the multi-layered substrates that are adjacent to each other, the slit portions being provided so as to extend from the top surface of the sealing resin portion to a location to which grounding patterns located between laminated layers are exposed, in a state in which the multi-layered substrates are connected to each other by a connecting portion located on a lower portion of the assembly substrate, wherein said forming the slit portions includes: forming first portions of side surfaces facing each other in the sealing resin portion across the slit portions; and; forming second portions of the side surfaces facing each other in the multi-layered substrate across the slit portions; forming a metallic film in the sealing resin portion and the assembly substrate including an inner portion of the slit portions, the metallic film being connected to the grounding patterns located between the laminated layers; forming cutting portions in the assembly substrate at locations between the adjacent multi-layer substrates and corresponding to the locations of the slit portions; and individually separating the shielded electronic circuit units from each other through the slit portions and the cutting portions, wherein the cutting portions have a smaller width than the slit portions.