Patent ID: 6986072

Claim:
A register mounted on a memory module including a plurality of memory devices, said register receiving an external clock signal and one of a command or an address signal from a chip set outside said memory module, generating an internal clock signal from said external clock signal, fetching said one of a command or an address signal in accordance with said internal clock signal, and thus generating one of an internal command or an internal address signal for said memory device, wherein: said register is connected to an external delay replica indicating a propagation delay time corresponding to a reach time of said one of an internal command or an internal address signal to said plurality of memory devices; said register comprising: an internal delay replica indicating a delay time from said internal clock signal to generation of said one of an internal command or an internal address signal corresponding to said internal clock signal; a delay locked loop circuit forming a delay control loop together with said internal delay replica and said external delay replica, said delay locked loop circuit front-loading said external clock signal by a predetermined time indicated by said internal delay replica and said external delay replica and generating said internal clock signal; a flip-flop for latching said one of a command or an address signal in accordance with said internal clock signal and generating one of an intermediate command or an intermediate address signal; and an output unit for buffering said one of an intermediate command or an intermediate address signal and outputting said one of an internal command or an internal address signal, said output unit and said internal delay replica having a plurality of switchable delay times.