Patent ID: 7868375

Claim:
A method of increasing the erase efficiency of a non-volatile memory cell of the type having a substrate of a substantially single crystalline material of a first conductivity type, with a first region of a second conductivity type, and a second region of the second conductivity type, spaced apart from the first region, forming a channel region therebetween; said memory cell having a select gate insulated and spaced apart from a first portion of the channel region adjacent to the first region; and having a floating gate insulated and spaced apart from a second portion of the channel region; the floating gate having a first end closest to the select gate and a second end furthest away from the select gate; said floating gate having a top surface and a bottom surface opposite thereto, with said bottom surface facing the channel region, and a tip on the top surface at the second end, with a tunneling barrier covering said tip; said memory cell having a control gate with a top surface and a bottom surface opposite thereto, with said bottom surface insulated from and facing the top surface of the floating gate; said control gate insulated and adjacent to the selected gate, said control gate having a first end closest to the select gate and a second end furthest away from the select gate; wherein said second end of the control gate is closer to a vertical line aligned with the first end of the floating gate than the second end of the floating gate, whereby a portion of the top surface of the floating gate is not facing the bottom surface of the control gate; said memory cell further having an erase gate having a first portion insulated and spaced apart from the second region of the substrate and having a first end separated from the second end of the floating gate, and a second portion electrically connected to the first portion and having a first end; wherein said method comprising: shielding the tunneling barrier from the control gate by positioning said second portion of the erase gate above the tip of the floating gate and insulated therefrom by said tunneling barrier with said first end adjacent to the control gate, said second portion of the erase gate separated from the floating gate by a first length measured in a direction substantially perpendicular to the direction from the first region to the second region; with said first end of said second portion closest to the second end of the control gate, said second portion of the erase gate having a second length measured from the first end of the second portion of the erase gate to a vertical line aligned with the first end of the first portion of the erase gate in a direction substantially parallel to the direction from the first region to the seconds region; and wherein said ratio of the second length to the first length is between approximately 1.0 and 2.5.