Patent ID: 7047384

Claim:
An apparatus comprising: a first memory device; a second memory device; a first conductor; a second conductor that is longer than the first conductor; and a memory controller to which the first and second memory devices are designed be coupled, and which is coupled to the first memory device by the first conductor and to the second memory device by the second conductor, wherein a first signal transmitted by the first memory device propagates through the first conductor in less time than a second signal transmitted by the second memory device propagates through the second conductor, wherein the first and second signals are transmitted in response to a third signal transmitted by the memory controller to both the first and second memory devices, and wherein the memory controller uses a first timing setting to latch the first signal and uses a second timing setting to latch the second signal, wherein the transmission of the first, second and third signals are synchronized to a clock signal, and wherein the latching of the first and second signals by the memory controller occurs within a single cycle of the clock signal.