Patent ID: 7685542

Claim:
A method for testing logic devices configured across asynchronous clock domains of a computer circuit, the method comprising: deactivating, during at-speed fault testing, a first local clock signal for each of a plurality of latches of the computer circuit, the plurality of latches receiving at least one data input originating from an asynchronous clock domain of the computer circuit, with respect to the plurality of latches; wherein the deactivation of the first local clock signal for each of the plurality of latches occurs while a second local clock signal for each of the plurality of latches remains active, so as to permit data capture within the plurality of latches, and wherein the deactivation of the local clock signal for each of the plurality of latches is further implemented in a manner so as to permit at-speed data launch from the plurality of latches to downstream latches with respect to the plurality of latches during at-speed testing.