Patent ID: 8566765

Claim:
A method of modifying a hierarchical circuit design, comprising: accessing hierarchical circuit data in the hierarchical circuit design; performing timing analysis using one or more processors, on a selected portion of the hierarchical circuit data to determine whether inter-block timing closure is achieved; in the event that inter-block timing closure is not achieved, performing a first set of one or more fixes to logic, component size, or both on the selected portion of the hierarchical circuit data to achieve inter-block timing closure; performing timing analysis on the modified hierarchical circuit data that includes the first set of one or more fixes to determine whether intra-block timing closure is achieved; and in the event that intra-block timing closure is not achieved on the modified hierarchical circuit data, performing a second set of one or more fixes to logic, component size, or both on the modified hierarchical circuit data to achieve intra-block timing closure.