Patent ID: 7002868

Claim:
A semiconductor memory device comprising a cell array including a plurality of memory cells, each of said memory cells including: first and second switch transistors connected in series between a bit line for normal access and a bit line for refresh; and a capacitor for data storage connected to a connection node at which the first and second switch transistors are tied; the first and second switch transistors having control terminals connected to a word line for normal access and a word line for refreshing respectively; said semiconductor memory device, being configured as a late-write configuration, in which a write to a memory cell selected by a write address supplied to an address terminal of said semiconductor memory device from an outside of said semiconductor memory device is performed with a delay of at least one write cycle from input of the write address, further comprising: a sense amplifier for refreshing, connected to the bit line for refreshing: a determination unit for comparing a refresh address with a row address of a write address externally supplied to the address terminal at least one write cycle before to determine whether the refresh address matches the row address or not to output a determination result; and a control unit for performing control so that when a mismatch between the refresh address and the row address of the write address is detected by the determination circuit, a write operation and a refresh operation are performed concurrently in an identical cycle, in which the write operation is performed by activating the word line for normal access selected by the write address, turning on the first switch transistor in the memory cell connected to said word line for normal access, and writing data to the capacitor through the bit line for normal access, while the refresh operation is performed by activating the word line for refreshing selected by the refresh address, turning on the second switch transistor in the memory cell connected to said word line for refreshing, and reading a cell data and restoring said cell data through the bit line for refreshing by the sense amplifier for refreshing connected to the bit line for refreshing, and when a match between the refresh address and the row address of the write address is detected by the determination circuit, the refresh operation is inhibited while the write operation is performed.