Patent ID: 7141845

Claim:
A cell array comprising: memory cells arranged in a semi-conductor substrate to form cell rows and each having a cell capacitor for storing an electrical charge that characterizes a data content of the memory cell; a cell transistor for selection of the memory cell; word line trenches arranged between the cell rows and separating the cell rows; the cell capacitor being provided in a lower region of a hole trench introduced from a substrate surface of the semiconductor substrate with an inner electrode arranged in the hole trench; and the cell transistor being formed in an upper region of the hole trench and having an upper source/drain region, which adjoins the substrate surface and is near the surface, a lower source/drain region, which is connected to the inner electrode of the cell capacitor, and also a channel region, which separates the two source/drain regions from one another and is insulated by a gate dielectric from a gate electrode provided in the word line trenches; wherein the lower source/drain regions of the memory cells are formed as doped regions of a first conductivity type and are sections of a buried source/drain layer perforated exclusively by the hole trenches and the word line trenches; and wherein a doping profile of the buried source/drain layer parallel to the substrate surface is essentially uniform.