Patent ID: 7185170

Claim:
A system for translating memory addresses, comprising: processing circuitry that provides an effective address; a storage array coupled to the processing circuitry for receiving the effective address, the storage array having a plurality of stored effective addresses, each of the plurality of stored effective addresses having a corresponding pair of a lock bit and a valid bit and providing an output tag value and a single valid bit, the lock bit defining one of two predetermined classes of tasks executed by the system, the single valid bit being applicable to both of the two predetermined classes of tasks, the lock bit qualifying the clearing of the single valid bit; and a comparator coupled to the storage array for receiving the output tag value and the single valid bit, the comparator comparing the output tag value and the single valid bit with a predetermined effective address that is provided by the processing circuitry, the comparator providing an output hit signal to the processing circuitry when the valid bit provided by the storage array has a predetermined value and when the output tag value matches the predetermined effective address that is provided by the processing circuitry.