Patent ID: 8778758

Claim:
A method for manufacturing a semiconductor device, comprising: forming a plurality of electrode structures above a substrate; forming an insulating film on the plurality of electrode structures to make a gap between mutually-adjacent electrode structures; forming a silicon nitride film having compressive stress above the insulating film; forming a planarization film above the silicon nitride film; and planarizing a surface of the planarization film by polishing by CMP (chemical mechanical polishing) method; wherein the forming of the electrode structures includes: forming a charge storage layer above the substrate; forming an intermediate insulating film above the charge storage layer; and forming a control electrode above the intermediate insulating film; the forming of the control electrode includes: forming a silicon layer above the intermediate insulating film; and forming a metal layer above the silicon layer; a trench is formed above the substrate by removing a portion of the insulating film and a portion of the electrode structures after the forming of the insulating film on the electrode structures; a silicon nitride barrier film is formed above the insulating film and at an inner wall of the trench; a buried film is formed inside the trench and above the silicon nitride barrier film; the silicon nitride film having the compressive stress is formed above the buried film; and a silicon oxide film is formed as the buried film by thermal CVD method.