Patent ID: 7638245

Claim:
A mask set for a first integrated circuit design, the mask set comprising: a first mask having only a block of a first number of first vertical layer patterns of the first integrated circuit design, where the first number is less than a plurality of integrated circuits formed on a substrate, and the first vertical layer patterns on the first mask are formed at a size that is larger than a size at which corresponding first vertical layer patterns are imaged on the substrate, and the first vertical layer patterns are common between the first integrated circuit design and at least one other integrated circuit design, and a second mask having a block of a second number of second vertical layer patterns of the first integrated circuit design, where the second number is less than the plurality of integrated circuits formed on the substrate, and the second vertical layer patterns on the second mask are formed at a size that is larger than a size at which corresponding second vertical layer patterns are imaged on the substrate, and the second vertical layer patterns are unique to the first integrated circuit design, the second mask also having a block of a third number of third vertical layer patterns of the first integrated circuit design, where the third number is less than the plurality of integrated circuits formed on the substrate, and the third vertical layer patterns on the second mask are formed at a size that is larger than a size at which corresponding third vertical layer patterns are imaged on the substrate, and the third vertical layer patterns are unique to the first integrated circuit design.