Patent ID: 8642989

Claim:
A Resistive Random Access Memory (RRAM) cell comprising a two-state resistor and a resistive switching memory cell connected in series, wherein the two-state resistor comprises a lower conductive electrode, a two-state resistor functionality layer, and a middle conductive electrode, and wherein the two-state resistor functionality layer comprises an n-p-n junction or a p-n-p junction consisted of any one or more of doped Si, Ge, GaAs, InP, and SiGe, wherein the two-state resistor is configured so that: the two-state resistor comes into a low-resistance state from a high-resistance state when a forward sweeping voltage reaches a forward ON voltage V 1 , and keeps this low-resistance state in a forward direction, when the sweeping voltage is swept back from V 1 , the two-state resistor keeps the low-resistance state until the sweeping voltage becomes lower than V 2 , at which point the two-state resistor comes back to the high-resistance state from the low-resistance state, wherein V 1 >V 2 , the two-state resistor comes into the low-resistance state from the high-resistance state when a reverse sweeping voltage reaches a reverse ON voltage V 3 , and keeps the low-resistance state in a reverse direction, and when the sweeping voltage is swept back from V 3 , the two-state resistor keeps the low-resistance state until the sweeping voltage becomes smaller than V 4 , at which point the two-state resistor comes back to the high-resistance state from the low-resistance state, wherein |V 3 |>|V 4 |.