Patent ID: 7955923

Claim:
A method of forming an electrostatic discharge (ESD) protection device for the protection of an I/O logic circuit comprising: forming first and second wells of a first conductivity type; forming a plurality of gates over the first well; lightly doping the first well on both sides of the gates with a dopant of a second conductivity type to form lightly doped drain (LDD) regions of the second conductivity type; lightly doping the second well with a dopant of the first conductivity type to form a lightly doped region of the first conductivity type; heavily doping the first well on both sides of the gates with a dopant of the second conductivity type so as to form source and drain regions from which the LDD regions extend and simultaneously heavily doping a portion of the lightly doped region in the second well with the dopant of the second conductivity type so as to form a diode; and connecting the source and drain regions between ground and an I/O pad and connecting the diode between the first well and the I/O pad.