Patent ID: 7954077

Claim:
A method of designing a circuit arrangement, the method comprising: using a computer machine, laying out an array of functionally interchangeable dynamic logic cells, wherein each functionally interchangeable dynamic logic cell includes a plurality of inputs, a logic circuit configured to generate an output as a function of the plurality of inputs using dynamic logic, and an output latch configured to latch the output of the logic circuit, wherein the dynamic logic in the logic circuit is responsive to a clock signal that precharges the dynamic logic during a precharge phase of the clock signal and evaluates the dynamic logic during an evaluate phase of the clock signal to generate the output for the logic circuit as a function of the plurality of inputs; and using a computer machine, configuring the array of functionally interchangeable dynamic logic cells to collectively implement an application specific logic function by routing a plurality of conductors to electrically interconnect inputs and outputs of at least a subset of the functionally interchangeable dynamic logic cells.