Patent ID: 8218538

Claim:
A system comprising: a switch fabric; a plurality of physical partitions of a physically partitionable symmetric multiprocessor, each physical partition coupled to the switch fabric via at least one respective partition input/output controller; a plurality of links between at least some processors of the physically partitionable symmetric multiprocessor, the links being programmatically configurable to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache memory coherency transactions; wherein at least a first one of the physical partitions is enabled to execute a storage control process to control storage traffic; wherein at least a second one of the physical partitions is enabled to execute a program to process the storage traffic; wherein the partition input/output controllers are enabled to communicate the storage traffic between a plurality of processes executing on the physical partitions and a storage input/output controller coupled to the switch fabric; wherein the switch fabric has a plurality of physical ports, the partition input/output controllers are further enabled to communicate the storage traffic at least in part by addressing cells to physical port addresses corresponding to the physical ports of the switch fabric, and each of the partition and the storage input/output controllers is associated with a respective unique one of the physical ports; and wherein the storage control process is enabled to provide software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces.