Patent ID: 7198993

Claim:
A method of forming fully-depleted and partially-depleted silicon-on-insulator (SOI) devices in an integrated circuit device, comprising: providing a first silicon layer over a buried oxide layer, wherein the silicon layer comprises a first thickness associated with a fully-depleted SOI device, the first silicon layer having a fully-depleted region and a partially-depleted region associated therewith; forming a dielectric portion over the first silicon layer in the fully-depleted region; forming a second silicon layer over the first silicon layer, thereby surrounding the dielectric portion in the fully-depleted region and forming a composite silicon layer comprising the first and second silicon layers in the partially-depleted region, wherein the composite silicon layer has a second thickness associated with a partially-depleted SOI device; forming a dielectric layer over the second silicon layer, thereby covering the composite silicon layer in the partially-depleted region and surrounding the dielectric portion in the fully-depleted region; removing the dielectric portion in the fully-depleted region and a portion of the dielectric layer in the partially-depleted region, thereby forming a fully-depleted gate opening and exposing a portion of the first silicon layer in the fully-depleted region and forming a partially-depleted gate opening and exposing a portion of the second silicon layer in the partially-depleted region; providing insulating material on sidewalls of the gate openings; and forming conductive material in the gate openings, thereby forming fully-depleted and partially-depleted gate electrodes therein, respectively, wherein a distance between a bottom of the fully-depleted gate electrode and the buried oxide layer is less than a distance between a bottom of the partially-depleted gate electrode and the buried oxide layer.