Patent ID: 8188569

Claim:
An integrated circuit comprising: an array of memory cells; wherein each memory cell comprises a volume of switching active material and a selection element; said volume of switching active material being contacted by a first end of a nanotube, the nanotube having a ring-shaped contact formed around a non-conducting nanowire; wherein the material of the nanotube is a metal; wherein the switching active material is a phase change material; and wherein the selection element is provided with at least one source/drain contact, an upper surface of the at least one source/drain contact is disposed with a silicon contact, and the selection element is further provided with at least one spacer such that the upper surface of the at least one source/drain contact, the silicon contact, and the at least one spacer defines a chasm; wherein a second end of the nanotube fills the chasm and surrounds the silicon contact, thereby forming a good electrical connection between the nanotube and the selection element.