Patent ID: 8499127

Claim:
A computer system, comprising: a processing unit operable to perform computing functions; a system controller coupled to the processing unit; at least one input device coupled to the processing unit through the system controller; at least one output device coupled to the processing unit through the system controller; at least one data storage device coupled to the processing unit through the system controller; a plurality of memory devices; and a memory hub comprising: a processor interface coupled to the processing unit; a plurality of memory interfaces coupled to the processor interface through a switch and to respective ones of the memory devices, the memory interface comprising: a cache memory; a preferred unit configured to predict a memory address of a memory location to access based on memory addresses of previously accessed memory locations; and an interface memory controller coupled to the preferred unit and configured to receive the predicted memory address, the interface memory controller further configured to generate command and address signals for accessing the memory location in the respective memory corresponding to the predicted memory address in response to receiving the predicted memory address; wherein there are no other devices coupled to the connection between the processing device and the memory hub.