Patent ID: 7389437

Claim:
A semiconductor circuit including an integrated circuit and a switch, the switch controlling the supply of power to the integrated circuit, the integrated circuit having a power-off area and a backup area, the semiconductor circuit operating in a normal mode in which power is supplied to both the power-off area and the backup area and a standby mode in which power is supplied to the backup area but not to the power-off area, wherein: the power-off area includes a register storing a mask signal having a high level and a low level, the mask signal being set to the high level in the normal mode and changed to the low level before a transition to the standby mode; and the backup area includes a latch circuit and a masking circuit, the latch circuit receiving the mask signal from the power-off area, assuming a first output state when the mask signal is at the high level, assuming a second output state when the mask signal is at the low level, and remaining in the second output state when the power-off area is not powered, the masking circuit masking an input signal from the power-off area to the backup area by holding the input signal at the low level while the latch circuit is in the second output state, wherein the backup area receives a ground potential and the latch circuit comprises: a first inverter having an input terminal receiving the mask signal from the power-off area, the first inverter generating an inverted mask signal; and a transistor through which the input terminal of the first inverter is connected to the ground potential, the transistor having a gate receiving the inverted mask signal from the first inverter.