Patent ID: 8053831

Claim:
A memory cell of a memory device, comprising: an active region of a memory cell defined in a semiconductor substrate; a conductive gate electrode in a trench of the active region, the conductive gate electrode being isolated from the semiconductor substrate and having a top surface coplanar with a top surface of the active region; an insulation layer on the active region and on the top surface of the conductive gate electrode; and a conductive contact in the insulation layer on the active region at a side of the gate electrode and isolated from the gate electrode, the contact having a first width at a top portion thereof and having a second width at a bottom portion thereof, the first width being greater than the second width, the contact being formed of a single-crystal material; wherein the insulation layer comprises: a first insulation layer on the semiconductor substrate and on the gate electrode; a second insulation layer on the first insulation layer, the second insulation layer comprising a material that has etch selectivity with respect to a material of the first insulation layer; and a third insulation layer in the second insulation layer and on the first insulation layer, the third insulation layer comprising a material that has etch selectivity with respect to the material of the second insulation layer, the third insulation layer lining at least a lower portion of an opening formed in the second insulation layer through which the contact is disposed, the first insulation layer and the third insulation layer surrounding, and in direct contact with, a lower portion of the contact, the contact provided through the first, second, and third insulation layers.