Patent ID: 8520107

Claim:
An analog-digital converter comprising: a reference signal generation circuit for generating a reference signal whose voltage value increases or decreases over time; n (n is an integer of 2 or more) comparators arranged in a first direction with a predetermined cell pitch and corresponding respectively to n input voltages, each comparator comparing the voltage value of the reference signal with the input voltage corresponding to the comparator; n counters corresponding respectively to the n comparators, each counter performing a count operation in synchronism with a predetermined clock so as to output a count value at a point when an output of the comparator corresponding to the counter is inverted; and n digital memories corresponding respectively to the n counters, each digital memory storing the count value output from the counter corresponding to the digital memory, wherein each of the n comparators includes first and second differential transistors to which the reference signal and the input voltage corresponding to the comparator are given, respectively, the first differential transistor is formed by p (p is an integer of 2 or more) first unit transistors connected in series, the references signal being given to gates of the p first unit transistors connected in series, the second differential transistor is formed by p second unit transistors connected in series, the input voltage being given to gates of the p second unit transistors connected in series, and the first p unit transistors are all NMOS transistors or all PMOS transistors, and the second p unit transistors are all NMOS transistors or all PMOS transistors.