Patent ID: 7692276

Claim:
An assembly, comprising: a first strip that includes an array of package substrate sections; a plurality of IC dies, wherein each IC die of the plurality of IC dies is mounted to a corresponding package substrate section on a first surface of the first strip; a second strip that includes an array of leadframe sections that each include a planar protruding area extending from a first surface of the second strip and a centrally located cavity formed in a second surface of the second strip, wherein the second strip is coupled to the first strip such that each planar protruding area of the second strip is coupled to a corresponding mounted IC die of the first strip; and an encapsulating material that fills a space between the first and second strips and fills the centrally located cavity of each leadframe section, wherein the encapsulating material does not cover a planar region of the first surface of the first strip surrounding each centrally located cavity; wherein each planar protruding area of the second strip is connected to the first surface of the second strip by a corresponding ring shaped side wall, wherein a plurality of openings is positioned in each ring shaped side wall, the plurality of openings in each ring shaped side wall being open through the second strip into a corresponding centrally located cavity.