Patent ID: 8574958

Claim:
A method for manufacturing the gate-control diode semiconductor memory device, characterized in that it includes the following steps: provide a heavily-doped n-type silicon substrate; form a first kind of insulation film on the n-type silicon substrate; form a ZnO layer on the first kind of insulation film; etch the ZnO layer to form an active region; cover the active region to form a NiO layer doped with p-type impurity ions; photoetch a pattern, etch the NiO layer and preserve the NiO layer on one side of the ZnO active region to form a device source; deposit a second kind of insulation film on the exposed NiO and ZnO surfaces; deposit device floating gate conductive material on the surface of the second kind of insulation film; define the pattern of the floating gate region thereof though photoetching and etching, wherein the floating gate region located between the NiO material on the ZnO active region and the edge of the other end of the ZnO, is in a square pattern, indirectly adjacent to the NiO with a spacing of 10 nm-100 μm, and is 10 nm-100 μm away from the edge of the ZnO; form a third kind of insulation film on the surface of the floating gate conductive material and the exposed ZnO & NiO; define the contact holes of the drain and the source by photoetching and etching the third kind of insulation film, and keep the third kind of insulation film on the floating gate region, wherein the contact holes of the drain and the source are on both sides of the floating gate region respectively, namely on the NiO and the ZnO respectively; form a first kind of conductive film through deposition and etch the first kind of conductive film to form a drain electrode, a gate electrode and a source electrode which are independent of one another, wherein the source electrode makes contact with the NiO on one side of the floating gate region through the source contact hole, the drain electrode makes contact with the ZnO on the other side of the floating gate region through the drain contact hole and the gate electrode cover the non-etched third kind of insulation film on the floating gate region.