Patent ID: 8410617

Claim:
An integrated circuit structure comprising: a first substrate comprising a first surface having interconnect contacts; a second substrate comprising a first surface having interconnect contacts; and a bond layer between the first surface of the first substrate and the first surface of the second substrate, comprising: a plurality of bonds formed from the interconnect contacts of the first surfaces of the first and second substrates and forming portions of signal paths between the first surface of the second substrate and the first surface of the first substrate; and, at least one bond formed between the first surfaces of the first and second substrates and not forming portions of a signal path between the first surfaces of the first and second substrates, wherein at least one of the first substrate and second substrate is substantially flexible and at least one of the first substrate and the second substrate is and formed from a semiconductor wafer or portion thereof; and at least one conductive path that passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said at least one of said first and second substrates, wherein the insulation material comprises a low stress dielectric material having a stress of 5×10 8 dynes/cm 2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon.