Patent ID: 7737771

Claim:
A semiconductor integrated circuit comprising: a first potential supply line having a first potential supply terminal at a first end thereof and a first node at an opposite end thereof, for supplying a first potential, said first potential decreases as said first potential is transmitted through said first potential supply line from said first end to said first node; a second potential supply line having a second potential supply terminal at a second end thereof and a second node at an opposite end thereof, for supplying a second potential, said second potential decreases as said second potential is transmitted through said second potential supply line from said second end to said second node; a first bias generation circuit electrically connected to said first node of said first potential supply line and to said second node of said second potential supply line, for receiving said decreased first potential and said decreased second potential to generate a first reference potential and a second reference potential based on said decreased first potential and said decreased second potential, respectively; a first reference potential line electrically connected to said first bias generation circuit, for supplying said first reference potential from said first bias generation circuit; a second reference potential line electrically connected to said first bias generation circuit, for supplying said second reference potential from said first bias generation circuit; and a first analog circuit electrically connected to said first potential supply line, said second potential supply line, said first reference potential line and said second reference potential line, and placed between said first and second potential supply terminals and said first bias generation circuit, such that a distance from said first bias generation circuit to the first potential supply terminal is larger than a distance from said first analog circuit to the first potential supply terminal and so that said decreased first potential having a most decreased value is provided to said first bias generation circuit, and such that a distance from said first bias generation circuit to the second potential supply terminal is larger than a distance from said first analog circuit to the second potential supply terminal and so that said decreased second potential having a most decreased value is provided to said first bias generation circuit, said first analog circuit receiving the first reference potential from said first bias generation circuit and receiving the second reference potential from said first bias generation circuit.