Patent ID: 7038517

Claim:
A method for generating timing signals with fine resolution time delay said fine resolution time delay being a predetermined fraction of a reference time said reference time being time between two transitions of reference signals comprising the steps of: (a) providing a first and a second control vernier; (b) programming said first control vernier to a first number of delay steps; (c) programming said second control vernier to a second number of delay steps; (d) applying a start signal simultaneously to inputs of said first and second control verniers to obtain first and second delay signals respectively at first and second control vernier outputs; (e) generating a difference signal corresponding to a difference between said first delay signal and second delay signal; (f) comparing the difference signal to a reference signal to generate a control signal, said control signal being coupled to a bias input of said control verniers to continuously adjust a value of delay step of the control verniers; and (g) coupling said control signal to bias inputs of a plurality of timing signal generating verniers to continuously adjust values of delay steps of the timing signal generating verniers.