Patent ID: 7072217

Claim:
A memory array comprising: a plurality of multi-state NAND memory cells arranged in a column, each cell comprising a drain region, a source region, and a nitride trapping layer that is capable of asymmetrical charge trapping, in response to asymmetrical biasing of the drain and source regions, of a first data bit adjacent the drain region and a second data bit adjacent the source region; and a plurality of select gates, a first select gate at one end of the column and a second select gate at the remaining end of the column, wherein during a programming operation of a first multi-state NAND memory cell a voltage differential substantially equal to 20V between a control gate of the first cell and the source region and a voltage differential substantially equal to 25V between the control gate and the drain region when the first data bit is being programmed and a voltage differential substantially equal to 20V between the control gate and the drain region and a voltage differential substantially equal to 25V between the control gate and the source region when the second data bit is being programmed.