Patent ID: 7239176

Claim:
A voltage tolerant protection circuit for an input buffer, the circuit comprising: a transmission gate circuit for receiving an input signal from an input pad; a N-Well generation circuit electrically coupled between the input pad and the transmission gate circuit; a control signal generator electrically coupled between the transmission gate circuit and the input pad to provide a control signal for operating the transmission gate circuit, wherein the control signal generator comprising: a first PMOS transistor electrically coupled to the input pad, the first PMOS transistor receiving control signals from a supply voltage and the N-Well generator block for avoiding consumption on the input pad; a second NMOS transistor electrically coupled to the first PMOS transistor, the second PMOS transistor receiving control signals from the supply voltage and a ground voltage for receiving a voltage potential when the voltage on the input pad voltage is less than the supply voltage; a third NMOS transistor electrically coupled to the second NMOS transistor, the third NMOS receiving control signals for transferring a voltage potential to a source of the second NMOS transistor when the voltage on the input pad is less than or equal to PMOS threshold and to form a open circuit path when the voltage on the input pad is greater than PMOS threshold; a fourth PMOS transistor electrically coupled to the input pad, the fourth PMOS transistor receiving a bias signal and the supply voltage for providing a closed path for conduction when pad voltage is greater than the PMOS threshold; a fifth NMOS transistor electrically coupled to the fourth PMOS transistor, the fifth NMOS transistor for receiving control signals from the supply voltage and the ground voltage to provide a controlled voltage response when the voltage on the pad voltage is greater than supply voltage; a sixth NMOS transistor electrically coupled to the fifth NMOS transistor, the sixth PMOS transistor for providing a controlled potential at a source of the fifth NMOS transistor; a seventh NMOS transistor electrically coupled to the sixth NMOS transistor for providing a controlled closed circuit path; an eighth NMOS transistor and a ninth NMOS transistor electrically coupled to the sixth NMOS transistor for outputting a NMOS threshold voltage potential when the voltage on the pad is less than or equal to the supply voltage; and a ninth PMOS transistor and an tenth NMOS transistor electrically coupled to the sixth NMOS transistors, to the seventh NMOS transistors, and to the eighth NMOS transistor for providing the supply voltage, without any change in amplitude, to the third NMOS transistor; wherein the N-Well generation is electrically coupled to the control signal generator for generating the bias signal for the transmission gate circuit and the control signal generator.