Patent ID: 7689741

Claim:
A memory system comprising: at least a flash memory block structured to store data; a flash interface structured to interface with the flash memory block; a host interface structured to interface with a host; a first buffer structured to temporarily store data read from the flash memory block or data supplied from the host; a second buffer structured to temporarily store data read from the flash memory block or data supplied from the host; a first control circuit structured to receive data read from the flash memory block, a first address, and first control signals through the flash interface or receive input data, a second address, and second control signals applied from the host through the host interface, to select one of the first and second buffers, and to output either the read data, the first address, and the first control signals or the input data, the second address, and the second control signals to the selected buffer; and a second control circuit structured to receive data output from the first buffer or the second buffer, and output the received data to the flash memory block through the flash interface or to the host through the host interface, wherein, while data stored in one of the first and second buffers is loaded in the flash interface through the second control circuit, simultaneously, data stored in the other one of the first and second buffers is output to the host interface through the second control circuit; wherein the first control circuit comprises: a first input selection circuit structured to output read data, a first address, and first control signals received from the flash interface, or to input data, a second address, and second control signals received from the host interface to the first buffer, in response to a first selection signal; and a second input selection circuit structured to output the read data, the first address, and the first control signals received from the flash interface, or the input data, the second address, and the second control signals received from the host interface to the second buffer, in response to a second selection signal; wherein the second control circuit comprises: a first output selection circuit structured to receive data output from the first buffer or the second buffer and output the received data to the host through the host interface, in response to a first selection signal; and a second output selection circuit structured to receive data output from the first buffer or the second buffer and output the received data to the flash memory block through the flash interface, in response to a second selection signal.