Patent ID: 8203216

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface, and four side surfaces; and wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body, wherein: the main body includes: a main part that includes a plurality of layer portions stacked and has a top surface and a bottom surface; and a plurality of terminals that are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the plurality of wires; each of the plurality of layer portions includes a semiconductor chip; the plurality of wires include a plurality of common wires that have a use common to all of the layer portions in the main part, and a plurality of layer-dependent wires that are used by respective different ones of the layer portions; and in at least one of the plurality of layer portions, the semiconductor chip is electrically connected to the plurality of common wires and is selectively electrically connected to only the layer-dependent wire that the layer portion uses, among the plurality of layer-dependent wires.