Patent ID: 8243524

Claim:
A semiconductor storage device comprising: a memory cell array including memory cell transistor from which data depending upon a value of a retained threshold voltage can be read out by applying a readout voltage to a control gate thereof; a row decoder which controls voltage on a word line connected to the control gate of the memory cell transistor; and a sense amplifier connected to a bit line which is connected to the memory cell transistor, wherein the sense amplifier includes: a first lower interconnection formed so as to extend in a first direction on a first interlayer insulation film formed on a semiconductor substrate; a second interlayer insulation film formed on the first interlayer insulation film and top of the first interconnection; a contact interconnection formed in a direction perpendicular to a substrate plane of the semiconductor substrate so as to pass through the second interlayer insulation film, and connected to the first lower interconnection; a first upper interconnection formed on the second interlayer insulation film and connected to the contact interconnection disposed under the first upper interconnection; a dummy contact interconnection formed in a direction perpendicular to the substrate plane of the semiconductor substrate in the second interlayer insulation film, and adjacent to the contact interconnection; and a second upper interconnection formed on the second interlayer insulation film so as to extend in the first direction, and connected to the dummy contact interconnection disposed under the second upper interconnection, and wherein a dummy lower interconnection is electrically connected only to the second upper interconnection.