Patent ID: 7636808

Claim:
A semiconductor device comprising: a plurality of memory banks, each having a plurality of memory cells which are slower in a write operation than in a read operation; and a cache memory for mediating an access to said plurality of memory banks from the outside, said cache memory having a number of ways equal to or larger than a value determined by a ratio (m/n) of a write cycle (m) of said memory cells to a read cycle (n) of said memory cells; wherein, when first data is written into said semiconductor device from the outside, and when said cache memory does not hold a first address at which said first data is to be written, second data held in an entry associated with the first address of said cache memory is written back to one of said plurality of memory banks, and said first data is written into said cache memory, and wherein, when third data is written into said semiconductor device from the outside when the second data is written back to one of said plurality of memory banks and said cache memory does not hold a second address at which said third data is to be written, fourth data held in an entry associated with the second address is written back to a second memory bank, different from the first memory bank, included in said plurality of memory banks.