Patent ID: 7298188

Claim:
A circuit for timing adjustment, comprising: a PLL circuit configured to generate a phase-adjusted clock signal in response to phase comparison between an input clock signal and a delayed clock signal; a feedback path configured to delay the phase-adjusted clock signal for provision as the delayed clock signal to said PLL circuit; a first timing correction circuit configured to add a predetermined delay time to said feedback path; an output data circuit directly coupled to a node to receive the phase-adjusted clock signal from the PLL circuit through the node and configured to supply output data at first timing indicated by the phase-adjusted clock signal; a second timing correction circuit directly coupled to said node to receive the phase-adjusted clock signal from the PLL circuit through the node and configured to delay the phase-adjusted clock signal by a delay time equal to the predetermined delay time to generate a further-delayed clock signal indicating second timing different from the first timing; and an input data circuit configured to receive the further-delayed clock signal and to latch input data at the second timing indicated by the further-delayed clock signal.