Patent ID: 7073026

Claim:
A microprocessor, comprising: an execution unit configured to operate on instructions and data; a cache memory subsystem coupled to said execution unit; wherein said cache memory subsystem includes: a cache memory including a plurality of independently accessible storage blocks; a plurality of independently accessible tag units coupled to said plurality of storage blocks and configured to store a plurality of tags each including an address tag value; a plurality of cache buses coupled to convey a plurality of cache access requests to each of said plurality of storage blocks; and a cache controller configured to select said plurality of cache access requests for conveying via said plurality of cache buses; wherein said cache controller is further configured to select said plurality of cache access requests such that no cache access conflict exists at any of said plurality of independently accessible tag units; and wherein in response to said plurality of cache access requests being conveyed on said plurality of cache buses, different ones of said plurality of storage blocks are concurrently accessible.