Patent ID: 6920510

Claim:
An apparatus comprising: a single port memory; a first circuit configured to transfer data between a plurality of first ports and a second port via said single port memory in response to one or more control signals, wherein said single port memory, said plurality of first ports and said second port are coupled with a bidirectional data bus; one or more first-in-first-out (FIFO) buffers coupling said bidirectional data bus with said plurality of first ports; a number N+1 of registers coupling said bidirectional data bus with said second port, where N comprises a ratio of a data width of said bidirectional data bus to a data width of said second port; and a second circuit configured to generate said one or more control signals, wherein (i) said single port memory is time shared among said second port and said plurality of first ports and (ii) said second port comprises a direct memory access (DMA) channel.