Patent ID: 7944263

Claim:
A timing generator comprising: a plurality of timing generating sections which provide a predetermined delay amount to a data signal to output the data signal; and a clock distribution circuit which distributes a clock to these timing generating sections, the clock distribution circuit including: a clock main path which transmits the clock, a clock return path which returns the clock transmitted by the clock main path, and a bias generation circuit which is provided with a transmitted clock that is input to the clock main path and a returned clock that is returned from the clock return path, wherein the clock main path has a main path buffer which provides a predetermined delay amount to the clock to be transmitted, the clock return path has a return path buffer which provides a predetermined delay amount to the clock to be returned, and a load capacity of the main path buffer is equal to that of the return path buffer, and wherein the bias generation circuit is configured to generate a bias which provides an equal potential to the main path buffer and the return path buffer and then sends the bias to the main path buffer and the return path buffer.