Patent ID: 8255750

Claim:
An integrated circuit comprising: A. first test access port circuitry having a first test data input, a first test data output, a first test clock input, and a first test mode select input; B. second test access port circuitry having a second test data input, a second test data output, a second test clock input, and a second test mode select input; and C. tap linking module circuitry having: i. a first test data output connected to the first test data input; ii. a second test data output, separate from the first test data output, connected to the second test data input; iii. a test data input lead, a test data output lead separate from the first test data output and separate from the second test data output, a test clock input lead, and a test mode select input lead; iv. link configuration circuitry having an input connected to the test data input lead, an output connected to the first test data output, another output connected to the second test data output, and a control input; and v. link shift/update circuitry having an input connected to the test data input lead, an output coupled to the test data output lead, and a control output connected to the control input of the link configuration circuitry.