Patent ID: 7714565

Claim:
An apparatus for testing a delay locked loop (DLL) circuit which generates a plurality of outputs based on a reference clock input, the plurality of outputs offset in predetermined phase amounts relative to the reference clock input, said apparatus comprising: a first delay line having an input and an output, said input of said first delay line being coupled to a first output of the DLL circuit; first comparison means having two inputs, one of the inputs of said first comparison means being coupled to the output of the first delay line and the other being coupled to the reference clock; a second delay line having an input and an output, said input of said second delay line being coupled to the reference clock; and second comparison means having two inputs, one of the inputs of said second comparison means being coupled to the output of the second delay line and the other being coupled to the first output of the DLL circuit; wherein said first and second delay lines and said first and second comparison means are separate and distinct from the DLL circuit.