Patent ID: 6895478

Claim:
A memory control circuit enabling a memory to be accessed from a first processing device in response to a first or a second processing request signal, and enabling the memory to be accessed from a second device in response to a third or a fourth processing request signal, comprising: a first group of watching circuits observing whether both of the first and second processing devices request access to the memory, based on the first and second processing request signal and the third processing request signals, a second group of watching circuits observing whether both of the first and second processing devices request access to the memory, based on the first and second processing request signals and the signal representing an observation of the first group of watching circuits and the fourth processing request signal, an address generating circuit generating and outputting a first address signal in response to the first processing request signal, a second address signal in response to the second processing request signal, a third address signal in response to the third processing request signal, and a fourth address signal in response to the fourth processing request signal, a selection circuit, which is responsive to a selection signal, outputting one of the first through fourth address signals to the memory, and a control circuit generating the selection signal, the control circuit outputting the selection signal for selecting the first or second address signal prior to the third or fourth address signal when signals representing an observation of the first or second group of watching circuits indicate that both of the first and second processing devices request access to the memory.