Patent ID: 6845407

Claim:
A semiconductor memory device, comprising: a first plurality of pads to receive a corresponding plurality of first external signals; a second plurality of pads to receive a corresponding plurality of second external signals; and an input and output mode set circuit coupled with the first and second plurality of pads to generate a plurality of input and output mode signals responsive to the plurality of first and second external signals; wherein, during a test mode, the input and output mode set circuit is adapted to generate the plurality of input and output mode signals responsive only to the plurality of first external signals, the plurality of first pads receiving a high voltage higher than a voltage level of a power supply signal thereby generating a plurality of first external signals having a level higher than a voltage level of the power supply signal; wherein, during normal operations, the input and output mode set circuit is adapted to generate the plurality of input and output mode signals responsive to the plurality of second external signals, the plurality of second external signals having logic levels.