Patent ID: 8060729

Claim:
Apparatus for processing a plurality of successive data packets, wherein each packet includes packet information and undergoes processor tasks and hardware events, the apparatus comprising: a multi-threaded processor that is operable to perform processor tasks; a plurality of hardware blocks, each of which is operable to perform a hardware event; a plurality of memory circuits, each of which is associated with at least one of the hardware blocks and operable to store at least two of the plurality of data packets; and first interface circuitry that is operable to control transferring each of the plurality of packets between each of the plurality of memory circuits; wherein: the first interface circuitry transfers a first one of the successive data packets from a first one of the memory circuits to the multithreaded processor; the multithreaded processor performs a processor task on the packet information of the first one of the successive data packets; the first interface circuitry transfers the first one of the successive data packets, on whose packet information the multithreaded processor performed the processor task, from the multithreaded processor to a second one of the memory circuits, said second one of the memory circuits being associated with a first one of the hardware blocks; the first one of the hardware blocks performs a hardware event on the first data packet, on whose packet information the multithreaded processor performed the processor task; and based on the hardware event, the first interface circuitry transfers the first one of the successive data packets, on whose packet information the multithreaded processor performed the processor task and on which the first one of the hardware blocks performed the hardware event, from the second one of the memory circuits to a third one of the memory circuits, the third one of the memory circuits being associated with a second one of the hardware blocks.