Patent ID: 8324062

Claim:
A method of manufacturing a power semiconductor device, comprising: forming a first oxide layer on a first main side of a substrate of a first conductivity type; forming a gate electrode layer with at least one opening on the first main side on top of the first oxide layer, forming an enhancement layer by implanting a first dopant of the first conductivity type into the substrate on the first main side using the formed gate electrode layer as a mask, and by diffusing the first dopant into the substrate; and forming a base layer by implanting a second dopant of a second conductivity type into the substrate on the first main side, and by diffusing the second dopant into the substrate such that the base layer has a lower depth in a central area below the at least one opening, the depth of the base layer in the central area being shallower than a maximum depth to which the base layer extends in a peripheral area, wherein the first oxide layer is partially removed after diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, and the gate electrode layer is used as a mask for implanting the second dopant.