Patent ID: 6968025

Claim:
A high-speed transmission system having a low latency, comprising: a plurality of first transmitter circuits in a send side; and a plurality of first data processing circuits in a receive side, said first transmitter circuits and said first data processing circuits connected one-to-one via a transmission line, wherein, so as to regulate a Delay Locked Loop (DLL) circuit ( 620 ) that regulates a timing of a sampling clock of a data signal of said first data processing circuit ( 600 ), a second transmitter circuit ( 300 ), a transmission line ( 900 ), and a second data processing circuit ( 700 ) are provided, and wherein, when a second specific signal string has been sent, a regulation start signal is caused to be distributed from said second data processing circuit ( 700 ), and wherein said regulation is caused to be made for said DLL circuit ( 620 ) by a regulating signal string, and wherein data starting with a bit next to a first specific signal string detected in a data signal for which a serial-parallel conversion was made is written into a FIFO circuit ( 660 ), and simultaneously, a read address synchronized with a system clock (CLKSYS) is generated from a third specific signal string that came to said second data processing circuit ( 700 ), and whereby recovery is made for data.