Patent ID: 8441078

Claim:
A method of forming an integrated circuit (IC) that comprises a substrate wafer having a top semiconductor surface including at least one MOS device, comprising: forming a SiON gate dielectric layer including a plurality of different N concentration portions, wherein said forming said SiON gate dielectric layer comprises: forming a 1.0-3.0 nm thick silicon oxide layer by oxidizing said top semiconductor surface; nitriding said silicon oxide layer, and after said nitriding, a multi-step post nitridation annealing (PNA) comprising a first anneal in an inert ambient followed by a second anneal in an oxidizing ambient such that said plurality of different N concentration portions include (i) a bottom portion extending to a semiconductor interface with said top semiconductor surface having an average N concentration of <2 atomic %, (ii) a bulk portion on said bottom portion having an average N concentration >10 atomic %, and (iii) a top portion on said bulk portion extending to a gate electrode interface with said gate electrode having an average N concentration that is ≧2 atomic % less than a peak N concentration of said bulk portion; depositing a gate electrode on said SiON layer, and forming a source and a drain region spaced apart from one another on opposing sides of said gate electrode to define a channel region positioned under said gate electrode.