Patent ID: 7796063

Claim:
A data transmission circuit, comprising: a serial clock generator configured to generate a serial clock; a serializer configured to serialize N-bit parallel data to N-bit serial data in synchronization with the serial clock, N being a natural number greater than one; and a transmission clock generator configured to receive the serial clock to generate a transmission clock, the data transmission circuit simultaneously transmitting the N-bit serial data and the transmission clock, wherein the transmission clock generator includes, a plurality of multiplexers, each of the plurality of multiplexers having a first input terminal that receives a first or second logic value level and a second input terminal that receives a shifted logic value based on the first and second logic value level, the first and second logic value levels alternating among the plurality of multiplexers, and a plurality of flip-flops, each of the plurality of flip-flops receiving an output from one of the plurality of multiplexers, the plurality of flip-flops configured to receive and delay outputs of the plurality of multiplexers to provide the transmission clock.