Patent ID: 8589631

Claim:
Interconnect circuitry for a data processing apparatus, said interconnect circuitry is configured to provide routes for interconnecting a plurality of initiator devices and at least one recipient device, at least one of said at least one recipient device comprising at least one memory for storing at least one data item to be processed by said processing apparatus, at least one of said plurality of initiator devices comprising a cache for storing a local copy of a subset of said data items stored in said at least one memory said interconnect circuitry comprising: a plurality of input ports configured to receive transaction requests from said plurality of initiator devices; at least one output port configured to output transaction requests to said at least one recipient device; a plurality of paths configured to transmit said transaction requests between said plurality of inputs and said at least one output; coherency control circuitry configured to maintain an order in which at least some of said transaction requests to a same data storage location proceed through said interconnect circuitry in order to maintain coherency of data items processed by said data processing apparatus; said interconnect circuitry is configured to not control a writeback transaction request with said coherency control circuitry, such that said writeback transaction request proceeds independently of transaction requests routed through said coherency control circuitry, said writeback transaction request is a write transaction request received from said at least one initiator device comprising said cache and updating said at least one memory with a locally stored updated value of one of said data items.