Patent ID: 6977860

Claim:
A SRAM memory having an internal data bus with reduced internal signal levels, comprising: a plurality of memory-cell banks, with each bank of memory cells having a core in which the memory cells are arranged in word rows and bit columns; each bank receiving a local word line signal for selecting a row of memory cells and for connecting a selected memory cell of a column to a respective bit-line pair for that column to provide a low voltage differential voltage signal from a memory cell to a bit-line pair for that respective bit column; a Y-multiplexer for directly connecting each bit-line pair of a respective column to one end of a corresponding pair of differential data bitlines of an internal data bus while still substantially maintaining low voltage differential voltage level signals on the pairs of differential data bitlines of the internal data bus; differential sense amplifier/output buffers, each connected to the other end of a respective pair of differential data bitlines of the internal data bus, each of said sense amplifier/output buffers receiving low voltage differential voltage level signals from a corresponding bit-line pair, and each of said sense amplifier/output buffers having output signals that are full logic level signals; a plurality of SRAM data output terminals, adjacent to each of which is located a corresponding differential sense amplifier/output buffer that provides full logic level signals to that SRAM data output terminal; and whereby the internal data bus is a differential data bus that carries low voltage differential voltage level signals that are not full logic levels from memory cells to the differential sense amplifier/output buffers to thereby reduce power consumed by not driving full logic levels signals through the internal data bus.