Patent ID: 8076205

Claim:
A method of fabricating a semiconductor memory device including a semiconductor substrate having a first region and a second region located adjacent to the first region, and a first element isolation area extending to a predetermined direction in the first region, a first active area sectionalized by the first element isolation area in the first region, a second element isolation area extending to the predetermined direction in the second region, and a second active area sectionalized by the second element isolation area in the second region, comprising; forming a gate insulating film on the semiconductor substrate in the active area of the first region and the second region; forming a first polysilicon film on the gate insulating film; forming an inter-gate insulating film on the first polysilicon film; forming a second polysilicon film on the inter-gate insulating film; etching the first and the second polysilicon films and the inter-gate insulating film so as to form first gate electrodes in the first region and second gate electrode in the second region, each first gate electrode including a floating gate electrode, the inter-gate insulating film and the control gate electrode, and each second gate electrode including a dummy gate electrode, the inter-gate insulating film and the control gate electrode extending from the first region; filling a first insulating film between the first gate electrodes in the first region and between the second gate electrodes in the second region, the first insulating film including a void in the active area and the element isolation area of the first and the second regions, a position of the void formed in the active area being higher than a position of the void formed in the element isolation area; etching the first insulating film so as to expose an upper side portion of the control gate electrode; forming a metal silicide film on the second polysilicon film; and forming a second insulating film on the first insulating film, wherein an upper portion of the void formed in the active area being opened by the first insulating film etching step.