Patent ID: 6963514

Claim:
A method for testing an integrated semiconductor memory controllable by applying control signals, the integrated semiconductor memory comprising a terminal for reading data in and out, and a memory cell array including memory cells arranged along word and bit lines, each memory cell comprising a selection transistor operable to select the memory cell, the method comprising: operating the integrated semiconductor memory in a normal operating state and in a test operating state, the integrated semiconductor memory operating synchronously with respect to a profile of a clock signal in the normal operating state, and operating synchronously and asynchronously with respect to the profile of the clock signal in the test operating state; selecting at least one memory cell for at least one of a write and read access by applying an address to the integrated semiconductor memory; switching the integrated semiconductor memory from the normal operating state to the test operating state by applying a signal combination formed from the control signals; and during operation of the integrated semiconductor memory in the test operating state: applying an activation signal and a write signal to the integrated semiconductor memory synchronously with respect to the profile of the clock signal to select the memory cell associated with the applied address for a write access by virtue of the selection transistor of the selected memory cell being turned on; applying to the terminal a first test data set for reading into the selected memory cell; applying a first of the control signals to the integrated semiconductor memory asynchronously with respect to the profile of the clock signal, thereby turning off the selection transistor of the selected memory cell; precharging the bit lines to a common equalization potential; and applying a second of the control signals to the integrated semiconductor memory asynchronously with respect to the profile of the clock signal, thereby turning on the selection transistor of the selected memory cell such that the memory content of the selected memory cell is read out.