Patent ID: 8068369

Claim:
A sense amplifier circuit of a single-ended type amplifying a signal which is read out from a memory cell and is transmitted through a bit line, comprising: a first MOS transistor supplying a predetermined voltage to the bit line and controlling a connection between the bit line and a sense node in response to a control voltage applied to a gate thereof; and a second MOS transistor having a gate connected to the sense node and amplifying a signal transmitted from the bit line via the first MOS transistor, wherein the sense amplifier circuit has operating modes including a charge transfer mode and a charge distributing mode, and wherein the predetermined voltage is supplied to the bit line before a read operation of the memory cell, and the predetermined voltage is set to a value such that a required voltage difference at the sense node between high level data and low level data read out from the memory cell can be obtained in a vicinity of a changing point between the charge transfer mode and the charge distributing mode within a range of a read voltage of the memory cell.