Patent ID: 8921897

Claim:
An integrated circuit, comprising: a first conductive structure forming gate electrodes of both a first transistor of a first transistor type and a first transistor of a second transistor type; a second conductive structure forming one gate electrode as a gate electrode of a second transistor of the first transistor type; a third conductive structure forming one gate electrode as a gate electrode of a second transistor of the second transistor type; a fourth conductive structure forming one gate electrode as a gate electrode of a third transistor of the first transistor type; a fifth conductive structure forming one gate electrode as a gate electrode of a third transistor of the second transistor type; a sixth conductive structure forming gate electrodes of both a fourth transistor of the first transistor type and a fourth transistor of the second transistor type, each gate electrode formed to extend lengthwise in a parallel direction, each transistor of the first transistor type formed in part by corresponding diffusion regions of a first diffusion type, each transistor of the second transistor type formed in part by corresponding diffusion region of a second diffusion type, diffusion regions of the first diffusion type collectively separated from diffusion regions of the second diffusion type by an inner non-diffusion region, the second and third conductive structures having respective inner ends positioned over the inner non-diffusion region and separated by a first end-to-end spacing, the fourth and fifth conductive structures having respective inner ends positioned over the inner non-diffusion region and separated by a second end-to-end spacing, wherein either the inner ends of the second and fourth conductive structures are offset in the parallel direction, or the inner ends of the third and fifth conductive structures are offset in the parallel direction, or both the inner ends of the second and fourth conductive structures and the inner ends of the third and fifth conductive structures are offset in the parallel direction.