Patent ID: 7998857

Claim:
A process for fabricating an integrated circuit, the process comprising: providing a substrate; forming a plurality of longitudinal trenches in the substrate; depositing a layer of a first conductive material on a peripheral surface of at least one longitudinal trench of the plurality of longitudinal trenches, wherein the first conductive material comprises tin (Sn); depositing a first layer of a second conductive material on the layer of the first conductive material by using a first plating process; and forming at least one conductive path by depositing a second layer of the second conductive material on the first layer of the second conductive material using a second plating process; wherein an initial thickness of the first layer prior to forming the at least one conductive path is greater than a final thickness of the first layer after forming the at least one conductive path; wherein the second layer of the second conductive material at least partially fills the at least one longitudinal trench of the plurality of longitudinal trenches; and wherein a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.