Patent ID: 7939355

Claim:
A method of fabricating an integrated piezoresistive accelerometer comprising: providing an SOI wafer with a SOI device layer of a selected resistivity to eliminate any need for additional doping of the SOI wafer; providing a single mask on the SOI wafer to define all mechanical and electrical elements in the integrated piezoresistive accelerometer in the SOI device with the selected resistivity; and simultaneously defining all components of the piezoresistive accelerometer in the SOI wafer by selective etching of the SOI device layer without using any pn-junctions to define any piezoresistive components and to provide the same resistivity of all components, where each of the piezoresistive components defined in the SOI device layer are released and isolated from a supporting layer and interconnected with selected ones of the electrical elements of the integrated piezoresistive accelerometer by corresponding low-resistance interconnects defined in the SOI device layer and having increased width relative to the corresponding piezoresistive component.