Patent ID: 7994059

Claim:
A method, comprising: forming a first stress-inducing layer above a plurality of first transistors and a plurality of second transistors formed above a substrate, said first stress-inducing layer generating a first type of stress; removing said first-stress-inducing layer from above said plurality of second transistors; forming a second stress-inducing layer above said plurality of first transistors and said plurality of second transistors after removing said first-stress-inducing layer from above said plurality of second transistors, said second stress-inducing layer generating a second type of stress other than said first type of stress; removing said first-stress-inducing layer from above said plurality of first transistors; and forming a third stress-inducing layer above said portions of said first and second stress-inducing layers formed above said pluralities of first and second transistors, said third stress-inducing layer generating one of said first and second types of stress.