Patent ID: 8451949

Claim:
A clock-data recovery (CDR) circuit comprising: a variable-gain amplifier (VGA) to amplify an input signal with a gain factor controlled by a gain setting to generate an amplified signal; an analog-digital converter to convert the amplified signal into a converter output in accordance with a timing provided by a recovered clock, wherein the converter output has N levels; a timing detection circuit to generate a timing error signal based on the converter output, and in accordance with a logical relationship between sliced data, and a delay of the sliced data; a filter to filter the timing error signal to generate a control signal; a controllable oscillator to generate the recovered clock under a control of the control signal; an automatic gain control (AGC) to set the gain setting to control the gain factor of the VGA based on the converter output; and a data recovery circuit for generate a recovered data based on the converter output.