Patent ID: 6995418

Claim:
An integrated semiconductor memory with at least one memory cell including at least one transistor which forms an inversion channel in the switched-on state, the transistor comprising: a structure element further containing a semiconductor material, the structure element comprising a first source/drain region, a second source/drain region and a region disposed between the first and the second source/drain region, the structure element being insulated from a semiconductor substrate by an insulation layer; and a gate dielectric disposed on the structure element and a word line disposed on the gate dielectric, the gate dielectric comprising a high-resistance tunnel contact including a first region, the layer thickness of which is such that, in the switched-off state of the transistor, majority charge carriers generated thermally in the structure element pass into the word line by direct tunneling through the gate dielectric, and the entire region of the structure element which region is disposed between the first and the second source/drain region being depleted of majority charge carriers in the switched-on state of the transistor.