Patent ID: 8437203

Claim:
A nonvolatile memory apparatus comprising: a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group; and a configuration information processing circuit configured to determine a majority of the first configuration data group received from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group received from the memory device, during a second period after the first period, wherein the configuration information processing circuit comprises a control clock output unit configured to output a counting clock signal and a first latching clock signal when a first period signal is activated, and output the counting clock signal and a second latching clock signal with a cycle shorter than that of the first latching clock signal when a second period signal is activated; and a configuration data processing unit configured to determine the majorities of the first and second configuration data groups which are sequentially received from the memory device, under the control of the counting clock signal and corresponding latching clock signals received from the control clock output unit.