Patent ID: 7129537

Claim:
A stacked gate flash memory cell having two symmetrical memory structures therein, comprising: a substrate having a trench therein; a conductive layer disposed on the bottom of the trench; a pair of source regions, each disposed in the substrate adjacent to one sidewall of the trench, electrically connecting the conductive layer; a source isolation layer disposed on the conductive layer; a pair of tunnel oxide layers, respectively disposed on one sidewall of the trench, contacting the source regions thereby; a pair of floating gates, respectively disposed on the source isolation layer, contacting the tunnel oxide layers thereby; a pair of inter-gate dielectric layers, respectively overlying the floating gate thereby; a pair of control gates, respectively overlying the inter-gate dielectric layer thereby; an insulating layer disposed in the trench, isolating the two control gates, forming two symmetrical memory structures therein; and a drain region disposed in the substrate adjacent to the trench.