Patent ID: 7245168

Claim:
A clock selection circuit that receives first and second clock signals, and selects and outputs one of the clock signals, the clock selection circuit comprising: a first control circuit that generates a first clock control signal activated for a first specified period, and outputs a first gated clock signal based on a delayed first clock signal during the first specified period in response to at least one of a control signal and a first disable signal; a second control circuit that generates a second clock control signal activated for a second specified period, and outputs a second gated clock signal based on a delayed second clock signal during the second specified period in response to at least one of the inverted control signal and a second disable signal; a first disable signal generating circuit that generates the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal; a second disable signal generating circuit that generates the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal; and a logic circuit that generates an output clock signal by performing a logic operation on the first and second gated clock signals.