Patent ID: 7015753

Claim:
A digital signal processing based feed forward amplifier, which comprises: a first directional coupler, the first directional coupler being responsive to an input signal and generating a first signal and a second signal in response thereto; a delay circuit, the delay circuit being responsive to the first signal and generating a third signal in response thereto; a main amplifier, the main amplifier being responsive to the third signal and generating a fourth signal in response thereto; a second directional coupler, the second directional coupler being responsive to the fourth signal and generating a fifth signal and a sixth signal in response thereto; a first analog to digital converter, the first analog to digital converter being responsive to the second signal and generating a seventh signal in response thereto; a second analog to digital converter, the second analog to digital converter being responsive to the sixth signal and generating an eighth signal in response thereto; a digital signal processor, the digital signal processor being at least partially responsive to the seventh signal and the eighth signal and generating a ninth signal in response thereto; a digital to analog converter, the digital to analog converter being responsive to the ninth signal and generating a tenth signal in response thereto; an error amplifier, the error amplifier being responsive to the tenth signal and generating an eleventh signal in response thereto; a third directional coupler, the third directional coupler being responsive to the eleventh signal and generating a twelfth signal and a thirteenth signal in response thereto; a fourth directional coupler, the fourth directional coupler being responsive to the fifth signal and the twelfth signal and generating a fourteenth signal in response thereto; a fifth directional coupler, the fifth directional coupler being responsive to the fourteenth signal and generating a fifteenth signal and an output signal in response thereto; a third analog to digital converter, the third analog to digital converter being responsive to the thirteenth signal and generating a sixteenth signal in response thereto; and a fourth analog to digital converter, the fourth analog to digital converter being responsive to the fifteenth signal and generating a seventeenth signal in response thereto, the digital signal processor being at least partially responsive to the sixteenth signal and the seventeenth signal and generating the ninth signal in response thereto.