Patent ID: 7546565

Claim:
A computer-based method for comparing two design representations of different versions of a layout of electronic circuits, wherein the representations of the two designs comprise several hierarchically related sheets, said method comprising the steps of: a) analyzing the sheet hierarchies to identify added, removed and common sheets; ai. identifying corresponding top-sheets of a first hierarchy level in said versions; aii. generating a list of all sub-sheets for each top-sheet and comparing said lists to identify added, removed and common sheets of said corresponding top-sheets; aiii. defining said common sheets as corresponding top-sheets of a next hierarchy level; and aiii. repeating steps aii. to aiv. until at least one of the top-sheets does not comprise any sub-sheet, and b) determining differences between common sheets to identify modified sheets; and c) displaying the combined sheet hierarchy of the two design representations wherein added, removed and modified sheets are marked.