Patent ID: 8677197

Claim:
A test apparatus comprising: a testing section operable to output a fail indication indicating a cell of a memory under test to be defective and a cell address; a first buffer section operable to buffer the fail indication and the cell address; a second buffer section operable to buffer the fail indication and the cell address; an address fail memory section operable to write the fail indication buffered by the first buffer section to an internal memory address indicated by the cell address using a read-modify-write process; a switching section operable to switch between supplying the fail indication and the cell address output from the testing section, and the fail indication and the cell address buffered in the second buffer section to the first buffer section; and a control section operable to supply the fail indication and the cell address output from the testing section to the second buffer section when an unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value.