Patent ID: 7274230

Claim:
A system for clockless synchronous data recovery comprising: an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating two or more parallel data streams from the serial data stream; and one or more adjustable delays coupled to the input rate demultiplexer, each delay receiving one of the generated parallel serial data streams and delaying bits of data and feeding them back to the input rate demultiplexer, wherein the adjustment of the delays is done automatically such that the delays have a predetermined value associated with the bit rate, wherein the adjustment of the delays is done with a phase-locked loop with reference to a timing reference, wherein the phase-locked loop further comprises: a second input rate demultiplexer generating a periodic signal; one or more second delays coupled to the second input rate demultiplexer, each second delay receiving the periodic signal and feeding it back to the second input rate demultiplexer; and a comparator comparing the periodic signal to the timing reference and adjusting the delay based on the output of the comparison.