Patent ID: 7719899

Claim:
A bit line driver system coupled to a plurality of bit lines, the bit lines being coupled to respective columns of non-volatile memory cells, the bit line driver system comprising: a bias generator circuit coupled to a bias output node, the bias generator circuit being configured to apply a bias voltage to the bias output node, the bias generator circuit comprising a first comparator having a first input coupled to receive the bias voltage and a second input coupled to receive an output signal at the bias output node, the first comparator being operable to compare the bias voltage to the output signal, and to charge the bias node with a voltage having a magnitude corresponding to the bias voltage; a pre-charging circuit coupled to the bias output node, the pre-charging circuit being operable to apply a pre-charge voltage to the bias output node for a period when the bias generator initially applies the bias voltage to the bias output node; and a plurality of bit line drivers, each driver coupled to a respective one of the bit lines and coupled to receive the bias voltage and the pre-charge voltage from the bias output node.