Patent ID: 8584063

Claim:
A method comprising: retrieving a design description and an assertion that both correspond to an electronic circuit design, wherein the assertion includes one or more assertion signal identifiers that correspond to one or more description signal points included in the design description; mapping the one or more assertion signal identifiers to the one or more description signal points; identifying a central propagation point corresponding to the one or more description signal points; propagating the one or more description signal points towards the central propagation point, resulting in one or more boundary points; creating a partitioned region from the design description based upon the one or more boundary points, wherein the partitioned region is a subset of the design description and describes a subset of the electronic circuit design; compiling, by one or more processors, the partitioned region into a machine-recognizable format; and verifying the compiled partitioned region under one or more test conditions, wherein the verifying verifies the electronic circuit design.