Patent ID: 7534678

Claim:
A method of forming an integrated circuit device, comprising the steps of: forming first, second and third transistors in a semiconductor substrate; covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile or compressive stress in a channel region of the first transistor; covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive or tensile stress in a channel region of the third transistor; selectively removing a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor to thereby define a first opening extending through the second electrically insulating layer; and then selectively removing a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor concurrently with removing a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor, to thereby define a first opening extending through the first electrically insulating layer and a second opening extending through the second electrically insulating layer.