Patent ID: 6985022

Claim:
A semiconductor device including a differential level converter circuit that receives a first signal and outputs a second signal of a larger amplitude than an amplitude of the first signal, the differential level converter circuit comprises a first MISFET pair of N type for receiving the first signal; a second MISFET pair of N type for improving a withstand voltage of the first MISFET pair; a third MISFET pair of P type having cross-coupled gates for latching the second signal from output; and fourth MISFET pair of P type for cutting off a supply voltage, wherein a film thickness of gate insulating films of the second MISFET pair is thicker than a film thickness of gate insulating films of the first MISFET pair; wherein a film thickness of gate insulating films of the third MISFET pair is thicker than the film thickness of the gate insulating films of the first MISFET pair; wherein a film thickness of gate insulating film of the fourth MISFET pair is thicker than the film thickness of the gate insulating films of the first MISFET pair; wherein an absolute value of a threshold voltage of the second MISFET pair is smaller than an absolute value of a threshold voltage of the third MISFET pair; and wherein an absolute value of a threshold voltage of the first MISFET pair is smaller than the absolute value of the threshold voltage of the third MISFET pair.