Patent ID: 7739640

Claim:
A method for computing a statistical change of delay due to a coupling event between two adjacent nets in an integrated circuit design, comprising: conducting a statistical timing analysis of the integrated circuit design; computing a statistical overlap window between the two adjacent nets, the statistical overlap window representing a period of time during which signals on the two adjacent nets can switch contemporaneously; and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window, wherein the computing the statistical change of delay comprises: computing a statistical Miller factor to represent an impact of capacitive coupling on delay; computing a sensitivity of the statistical change of delay to the statistical Miller factor; computing a sensitivity of the statistical Miller factor to a process parameter of the integrated circuit design; and chain-ruling the sensitivity of the statistical change of delay and the sensitivity of the statistical Miller factor to obtain the statistical change of delay due to the coupling event, wherein at least one of: the conducting the statistical timing analysis, the computing the statistical overlap window, or the computing the statistical change of delay is performed using a processor.