Patent ID: 7345948

Claim:
A method for producing a read clock signal in a memory device from a clock signal supplied to the memory device, the method comprising: delaying the clock signal by a delay amount depending on a frequency of the clock signal so as to ensure that a read access time is less than a time duration of one cycle of the clock signal; adjusting the delay amount based on a monitored temperature of the memory device and process and voltage conditions of the memory device; and programming the memory device with data that selects the delay amount from a plurality of possible delay amounts based on the frequency of the clock signal; wherein delaying comprises delaying the clock signal by the delay amount that comprises a first portion and a second portion, wherein the first portion is a selectable value between zero and a non-zero value depending on the frequency of the clock signal and the second portion is a value that is independent of the frequency of the clock signal and which is substantially constant over variations in process, voltage and temperature conditions of the memory device.