Patent ID: 6986113

Claim:
A method for estimating noise in an integrated circuit, the integrated circuit adapted to be supplied by a power having a predetermined supply voltage applied between a substrate and a power supply node, comprising the steps of: estimating a core power supply noise of the integrated circuit, by providing a power dissipated by the integrated circuit when clocked at a predetermined clock freguency; computing the current of the integrated circuit from the power dissipated and the supply voltage; creating a model block for a technology process for fabricating the integrated circuit, the model block comprising circuitry having components which can be clocked to provide signal switching; determining the number of model blocks that, at the predetermined clock freguency, conduct the same current as the computed current of the integrated circuit; estimating a noise generated by the number of model blocks by performing a transient analysis on the model blocks, and representing the estimated model block noise as a model block voltage source; estimating a noise generated by a input/output (“I/O”) circuitry to be implemented in the integrated circuit, and representing the estimated I/O noise as an I/O voltage source; generating a substrate netlist for the integrated circuit; determining a floorplan for the integrated circuit and providing said model block voltage source and said I/O voltage source in accordance with the floorplan; determining the noise of the integrated circuit in a selected portion of the integrated circuit using said model block voltage source and said I/O voltage source in accordance with the floorplan and the substrate netlist.