Patent ID: 8349670

Claim:
A method of making a memory cell comprising: doping a first region of a semiconductor substrate with one of an n-type or a p-type dopant and doping a second region of the semiconductor substrate with the other of an n-type or a p-type dopant; forming over the first region a pair of access transistors that are floating body devices and at least one pair of pull-down transistors that are non-floating body devices; forming over the second region at least one pair of pull-up transistors; and coupling the pair of pull-down transistors and the pair of pull-up transistors between the pair of access transistors to form a memory cell, wherein forming over the first region the pair of access transistors that are floating body devices comprises forming the body of each of the access transistors from a layer of partially depleted silicon-on-insulator, and wherein forming over the first region the at least one pair of pull-down transistors that are non-floating body devices comprises forming for each of the pull-down transistors a finFET channel comprising parallel fins spaced from one another and each fin controlled by at least one common gate.