Patent ID: 7977712

Claim:
A semiconductor structure comprising: a semiconductor substrate that includes an active region comprising: a horizontal plateau having a first crystallographic orientation; and a contiguous and adjoining sloped incline having a second crystallographic orientation different than the first crystallographic orientation; a gate electrode located over a channel within the sloped incline, wherein said gate electrode includes a first substantially straight sidewall edge located at a first point intersecting the horizontal plateau and the sloped incline and a second substantially straight sidewall edge located at a second point on the inclined slope, said second point not going beyond the lowest portion of said inclined slope, and wherein said first substantially straight sidewall edge and said second substantially straight sidewall edge are connected by an upper wall that curves outward from said first substantially straight sidewall edge to said second substantially straight sidewall edge; and a plurality of source and drain regions located within the active region and separated by the channel, where the plurality of source and drain regions is asymmetric and wherein the channel within the sloped incline is located at a juncture with the horizontal plateau.