Patent ID: 8898436

Claim:
A processor comprising: a continuous name space mapped register file comprising a plurality of registers, wherein each register in the plurality of registers is of a first size, wherein each register is associated with one of a low portion or a high portion of a register of a second size, and wherein each low portion and each high portion has a valid bit associated with that portion; a decode unit for decoding first instructions having sources and destinations of the first size, and second instructions having sources and destinations of the second size, wherein the second size is an even integer multiple n of the first size; and a mapping unit for mapping register names for the first instructions, and register names for the second instructions, into a common name space, by (i) for instructions having sources and destinations of the first size and a register of the first size in a named set of registers in the plurality of registers, asserting the valid bit for one of the low portion or the high portion of that named set of registers, and mapping the instruction accordingly, and (ii) for instructions having sources and destinations of the second size and a register of the second size in the named set of registers, asserting the valid bits for both the low and high portions of that named set of registers, and mapping the instruction accordingly.