Patent ID: 7461360

Claim:
A method for validating a circuit simulation result, comprising: providing a circuit network specified in a netlist format and input sources associated with the circuit; providing a simulation output for the circuit, wherein the simulation output includes node voltages for each node of the circuit; building a graph data structure from the circuit netlist; using the node voltages, determining branch voltages for branches in the graph; identifying a tree and links in the graph; identifying independent loops in the graph; summing the voltages for each independent loop in the graph; summing the currents at each node in the graph; summing power consumed for each branch in the graph to obtain a total power consumed; determining a total input power to the circuit network using the input sources associated with the circuit; subtracting the total power consumed from the total input power to obtain a total power difference; indicating a not validated condition when at least one of the loops in the graph has a nonzero sum; indicating a not validated condition when at least one of the nodes in the graph has a nonzero sum; and indicating a not validated condition when the total power difference is not zero.