Patent ID: 7171566

Claim:
A computer apparatus, including: a plurality of data channels for writing data to, and reading data from, memory; for at least one of the data channels, a data encrypter operable to encrypt data on the data channel; for at least one of the data channels, a data decrypter operable to decrypt data on the data channel; an encryption and decryption instruction generator operable to generate at least one instruction bit defining encryption or decryption instructions for data to be written to or read from the memory; and a data route controller operable to control the passage of data to and from the memory such that data is passed along a data channel in dependence upon the at least one instruction bit; and an address generator operable to generate data defining memory addresses for storage locations in the memory, wherein the address holds at least one instruction bit, which identifies which of multiple possible forms of encryption/decryption should be used on the data.