Patent ID: 8325537

Claim:
A semiconductor device comprising: a memory circuit producing in a first mode a set of first data and a set of second data in parallel to each other; a mode register producing third data in a second mode; a first data bus coupled to the memory circuit to receive the set of first data in the first mode and to the mode register to receive the third data in the second mode; a second data bus coupled to the memory circuit to receive the set of the second data in the first mode and the second data bus being disconnected from the mode register; third and fourth data buses; a first data control circuit provided between the first data bus and the third data bus to perform a parallel to serial conversion operation on data on the first data bus and output fourth data onto the third data bus; a second data control circuit provided between the second data bus and the fourth bus to perform a parallel to serial conversion operation on data on the second data bus and output fifth data onto the fourth data bus; a first output buffer coupled to the third data bus to output externally the fourth data; and a second output buffer coupled to the fourth data bus to output externally the fifth data.