Patent ID: 8741717

Claim:
A method for fabricating an integrated circuit, the method comprising: forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate; partially filling the first FET trench with a layer of a first work function metal to define an inner cavity in the first FET trench and partially filling the second FET trench with the first work function metal, wherein the first work function metal is one of a N-type work function metal and a P-type work function metal, and wherein the N-type work function metal is selected from the group consisting of titanium, tantalum, hafnium, ytterbium silicide, erbium silicide, and titanium silicide and the P-type work function metal is selected from the group consisting of cobalt, nickel, and tungsten silicide; removing the first work function metal from the second FET trench; depositing a second work function metal into the inner cavity and the second FET trench to fully fill the inner cavity and the second FET trench and form corresponding metal gate structures, wherein the second work function metal is the other one of the N-type work function metal and the P-type work function metal; and depositing a barrier layer of a barrier material in the first and second FET trenches prior to depositing the second work function metal to fully fill the inner cavity and the second FET trench but after removing the first work function metal from the second FET trench such that the barrier layer overlies the first work function metal in the first FET trench and not in the second FET trench.