Patent ID: 7212039

Claim:
A dynamic logic register, comprising: a complementary pair of evaluation devices responsive to a clock signal and providing a pre-charged node and an evaluation node; delayed inversion logic that receives said clock signal and that outputs a complete signal being a delayed and inverted version of said clock signal; a dynamic evaluator, coupled between said pre-charged node and said evaluation node, that evaluates a logic function based on at least one input data signal during an evaluation period between an operative edge of said clock signal and a next edge of said complete signal; latching logic, responsive to said clock and complete signals and the state of said pre-charged node, that enables the state of an output node to be determined by the state of said pre-charged node during said evaluation period and that otherwise clamps said pre-charged node to prevent perturbations of said at least one data signal from propagating to said output node, said latching logic comprising: an N-channel pass device having a gate receiving said complete signal and a drain and source coupled between said pre-charged node and a pull-up control node; a first P-channel pull-up device having a gate receiving said complete signal and a drain and source coupled between a source voltage and said pull-up control node; a second P-channel pull-up device having a gate coupled to said pull-up control node and a drain and source coupled between said source voltage and said output node; a clamp device, coupled between said pre-charged node and said evaluation node and responsive to said complete signal, that clamps said pre-charged node to said evaluation node while said complete signal is low; and a short stack of N-channel pull-down devices coupled between said output node and ground and controlled by said clock signal and said pre-charged node; and a keeper circuit coupled to said output node.