Patent ID: 8806090

Claim:
An apparatus, comprising: a number of hardware masters; non-volatile memory control circuitry coupled to non-volatile memory; volatile memory control circuitry coupled to volatile memory including a plurality of first buffers; and a switch coupled to the volatile memory control circuitry, to the non-volatile memory control circuitry, and to the number of hardware masters, wherein the switch includes: a plurality of second buffers distinct from the non-volatile memory and the volatile memory; and a buffer allocation management (BAM) circuit including a buffer tag pool, wherein the buffer tag pool includes a plurality of tags, each identifying a respective one of the plurality of first buffers or the plurality of second buffers, wherein the BAM circuit is configured to: allocate a tag to one of the number of hardware masters in response to an allocation request from the one of the number of hardware masters; and prioritize allocation of a tag identifying one of the plurality of second buffers over a tag identifying one of the plurality of first buffers; wherein one of the number of hardware masters comprises a processor configured to enable direct memory access (DMA) operations between the non-volatile memory control circuitry and the volatile memory control circuitry with access to an entire space of the volatile memory without regard to the plurality of tags.