Patent ID: 7892889

Claim:
A method for fabricating a semiconductor system, comprising the steps of: fabricating a first array of packaged devices including the steps of: providing a sheet-like substrate having a first surface and a second surface and a thickness, the substrate made of an insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface; forming an array of assembly sites on the substrate, each site including a component attach location, a first and a second set of terminals on the first surface, and a third, a fourth, and a fifth set of terminals on the second surface; providing semiconductor components having a thickness, an active surface with a first and a second set of I/O ports, and a passive surface; attaching the passive surface of a component to each component attach location; forming spans of bond wire to electrically connect the first set ports to the first set terminals, the top of all spans in a plane; forming loops of bond wire on the second set ports, the top of all loops in the same plane as the span tops; forming metal posts on the second set terminals to match the locations of the third set terminals, the posts being about normal to the first surface and having a height to reach the plane of the wire span tops and wire loop tops; embedding the attached components in an encapsulation compound adhering to the first substrate surface, the compound having a thickness at least equal to the post height; exposing the top surface of the posts, the wire loops, and the wire spans; depositing a pad on each exposed top surface of the posts, the wire spans, and the wire loops, the pads on the wire span tops matching the locations of the fourth set terminals, the pads on the wire loop tops matching the locations of the fifth set terminals; and depositing a reflow metal on the pads, the metal having a reflow temperature; fabricating a second array of packaged devices on a second substrate by the same steps as fabricating the first array, the second substrate having a third and fourth surface, terminals on the fourth surface matching the reflow-metal covered pads of the first array, and a reflow metal of the second array having the same reflow temperature as the reflow temperature of the reflow metal in the first array; and assembling the semiconductor system, including the steps of: aligning and contacting the terminals on the fourth surface with the reflow-metal covered pads of the first array; and applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array.