Patent ID: 8495346

Claim:
A processor including: a plurality of packed data registers including a first register to store a first packed data a second register to store a second packed data, a third register to store a third packed data, and a fourth register to store a fourth packed data; a decoder to receive a first control signal that is to indicate the first register and the second register as source operands, and a second control signal that is to indicate the third register and the fourth register as source operands, said first control signal to indicate a pack operation, said second control signal to indicate an unpack operation; at least one functional unit being coupled to said decoder and said plurality of packed data registers, said at least one functional unit to perform said pack operation and said unpack operation, said pack operation to cause a result to be stored in which all data elements from the first and second packed data are represented by half as many bits as in the first and second packed data, said unpack operation to cause a result to be stored in which half of data elements of the third packed data are interleaved with half of data elements of the fourth packed data.