Patent ID: 7836382

Claim:
A processor for writing data contained in payload data of a data packet to memory, comprising: a first register configured to receive first data corresponding to a first segment of payload data of a data packet, and further configured to latch the first data corresponding to the data segment; a second register configured to receive second data corresponding to a second segment of the payload data of the data packet, and further configured to establish validity of the first data latched into the first register before the first data is written to a memory; a micro sequencer and instruction decoder module configured to control transfer of the first data to the memory, wherein each of the first and second registers is controlled by the micro sequencer and instruction decoder module; a third register configured to latch third data representing an address in the memory; and a fourth register configured to latch fourth data indicating an amount of data in the payload data for transferring to the memory, wherein each of the third and fourth registers is controlled by the micro sequencer and instruction decoder module.