Patent ID: 7200522

Claim:
A computer program product that is stored in a computer readable medium for storing, in a performance monitor that is included within a processor, current event signal values as one unit that represents the full event state of said processor, said product comprising: instructions for receiving within said performance monitor a plurality of performance event signals, said plurality of performance event signals indicating the current full event state of said processor; instructions for counting only selected ones of said performance event signals by a plurality of counters included in said performance monitor; instructions for intercepting, by an event register included in said performance monitor, said plurality of performance event signals prior to selected ones of said performance event signals being counted; instructions for storing current values of said plurality of performance event signals together as a single unit in said event register, said unit being a full set of available performance event signals that indicate the current full event state of said processor; control logic that is included in said performance monitor being coupled to said event register utilizing a freeze state line; instructions for receiving, by said control logic, a notification of a freeze condition; instructions for causing, by said control logic, said event register to enter a freeze state in response to said control logic receiving said notification of said freeze condition; instructions for receiving, by said control logic, a notification of that said freeze condition no longer exists; and instructions for causing, by said control logic, said event register to enter a normal, non-freeze state in response to said control logic receiving said notification that said freeze condition no longer exists.