Patent ID: 8543873

Claim:
A method of testing computer memory devices comprising: coupling a plurality of memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices; generating test signal patterns using a test generator of each memory device; and serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the plurality of memory devices, wherein testing of the memory devices includes a first test mode and a second test mode, and wherein the first test mode is a serial IO (input-output) test mode and the second test mode is a memory interface test mode; wherein the serial IO test mode is separated from the memory interface test mode; and wherein test patterns generated for the memory interface test mode are limited to test patterns that are authorized for the memory interface test mode, and wherein test patterns generated for the serial IO test mode include test patterns that are not authorized for the memory interface test mode.