Patent ID: 8179352

Claim:
A gate driving apparatus for a liquid crystal display panel with liquid crystal cells, thin film transistors, gate lines, and data lines comprising: a timing controller generating a gate start pulse, a first gate shift clock and a second gate shift clock; a gate driving integrated circuit (IC) sequentially generating a plurality of control signals in response to the gate start pulse and the first gate shift clock, wherein the gate driving IC mounted on a circuit film, connected to the liquid crystal panel, includes: a first shift register including a plurality of first stages connected in cascade and carrying out a first shift operation using the gate start pulse and the first gate shift clock, so as to sequentially generate the plurality of control signals; and a level shifter array level-shifting and outputting the plurality of control signals from the first shift register, register, wherein an output of one of the first stages is directly connected to both another first stage of the first shift register and the level shifter array; and a plurality of second shift registers built in the liquid crystal display panel, wherein each of the second shift registers includes a plurality of second stages connected in cascade and carries out a second shift operation, each second shift register receiving one of the plurality of control signals from the level shifter array of the gate driving IC and providing scanning signals to at least two of the gate lines, wherein the timing controller supplies the first gate shift clock to the gate driving IC and supplies the second gate shift clock to the second shift registers, wherein the second gate shift clock is supplied to the plurality of second shift registers via the circuit film from the timing controller, and wherein the number of the plurality of control signals from the level shifter array is the same as the number of the plurality of second shift registers.