Patent ID: 7274390

Claim:
A device for parallel data processing, comprising at least one matrix of processors arranged in rows and columns, the rows being staggered and each processor having at least one data port, with at least one of the data ports of one of the processors in a row being connected by means of a substantially straight connection to at least one of the data ports of at least one of the other processors in another row; and least one data buffer having one or more data ports, with at least one of the data ports of at least one processor being connected by means of a substantially straight connection, wherein the data port of a processor in a row is not connected to the data port of another processor in the same row, and wherein the data ports of at least one of the processor include at least one primary data port and at least one secondary data port, with at least one of the secondary data ports being connected by means of a substantially straight connection to a primary data port of another processor.