Patent ID: 7590016

Claim:
An integrated circuit capable of verifying an operation speed of a circuit, the integrated circuit comprising: an internal circuit to be tested; a control circuit, located between the internal circuit and a large-scale integration (LSI) tester, to input read data to the internal circuit from the LSI tester by the use of a read command and to output write data outputted from the internal circuit to the LSI tester by the use of a write command; a test storage section including a read data storage section to store for the read data inputted at a low speed and a write data storage section to store the write data outputted from the control circuit; a command interpretation circuit to interpret the read command and the write command issued by the control circuit, to supply, at the time of determining that the read data must be inputted to the control circuit, the read data from the test storage section to the control circuit at a high speed, and to supply, at the time of determining that the write data is outputted from the control circuit, the write data outputted from the control circuit to the test storage section at a high speed; an input circuit to input the read data inputted from the LSI tester to the test storage section at a low speed; and an output circuit to output the write data supplied to the test storage section to the LSI tester at a low speed.