Patent ID: 8471628

Claim:
An amplifier comprising: an input stage having an input for receiving an input signal, and an output; and an output stage having an input coupled to said output of said input stage, and an output for providing an amplified output signal, wherein said output stage comprises: a gain stage having an input forming said input of said output stage, an output for providing said amplified output signal, and first and second bias terminals, wherein said gain stage comprises: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode forming a first differential input terminal of said gain stage, and a second current electrode coupled to said output of said gain stage; a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode forming a second differential input terminal of said gain stage, and a second current electrode coupled to a second power supply voltage terminal; a third transistor having a first current electrode coupled to said control electrode of said first transistor, a control electrode forming said first bias terminal of said gain stage, and a second current; and a fourth transistor having a first current, a control electrode forming a second bias terminal of said gain stage, and a second current electrode coupled to said control electrode of said second transistor; and a bias circuit having a first and second output terminals coupled to said first and second bias terminals of said gain stage, wherein during a turn-on period said bias circuit gradually ramps said first and second bias terminals from respective first and second initial voltages to respective first and second bias voltages.