Patent ID: 7906840

Claim:
A semiconductor integrated circuit package having one main surface adapted to mount a semiconductor integrated circuit thereon, and another main surface on which a connecting terminal for establishing connection with a printed circuit substrate is disposed, comprising: a power source wiring disposed in the package interiorly thereof so as to be electrically connected to a power terminal of the semiconductor integrated circuit; and a ground wiring disposed in the package interiorly thereof so as to be electrically connected to a ground terminal of the semiconductor integrated circuit, the power source wiring and the ground wiring constituting a first and second pair wiring structures in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval, wherein the first pair wiring structure is formed by juxtaposing the power source and ground wirings in a direction parallel to the main surface, the second pair wiring structure is formed by juxtaposing the power source and ground wirings in a direction perpendicular to the main surface, and a plurality of first pair wiring structures and a plurality of second pair wiring structures are congregated and arranged in a staggered arrangement when viewed in a section perpendicular to a wiring extending direction, the pair wiring structures of the staggered arrangement extending over a range of from a connecting terminal of the semiconductor integrated circuit to the connecting terminal for establishing connection with the printed circuit substrate.