Patent ID: 7320918

Claim:
A method of fabricating a circuit provided on a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a plurality of field effect transistors (FETs), including a first FET and a second FET disposed in a common device layer, the first FET having a gate disposed below the common device layer, the second FET having a gate disposed above the common device layer, the first and second FETs sharing a common body layer, a third and fourth FET, the third FET having a gate disposed below the common device layer, the fourth FET having a gate disposed above the common device layer, the third and fourth FETs sharing a common body layer, the first and second FETs being interconnected in series by a first source/drain region, the second and third FETs being interconnected in series by a second source/drain region, the third and fourth FETs being interconnected in series by a third source/drain region, a gate electrode of the first FET and a gate electrode of the third FET being coupled to a first conductor for providing a first clock signal, a gate electrode of the second FET and a gate electrode of the fourth FET being coupled to a second conductor for providing a second clock signal, wherein the circuit includes a dynamic two-phase shift register.