Patent ID: 7859628

Claim:
A substrate for a liquid crystal display (LCD), comprising: a gate line on a substrate along a first direction; first and second data lines along a second direction and crossing the gate line; a common line between the first and second data lines, wherein the common line, the gate line and the first data line define a first pixel region, and the common line, the gate line and the second data line define a second pixel region, wherein the common line is disposed at a same layer as the first and second data lines; a thin film transistor in each of the first and second pixel regions, the thin film transistor having a gate electrode, a source electrode and a drain electrode; a pixel electrode in each of the first and second pixel regions, the pixel electrode connected with the thin film transistor; first and second connection electrodes extending from the pixel electrode along the first direction and disposed at both end portions of the pixel electrode, respectively, wherein the first connection electrode connects the thin film transistor and the pixel electrode, wherein the pixel electrode is connected to the drain electrode through the first connection electrode; a passivation layer directly on the common line and covering the thin film transistor and the pixel electrode, the passivation layer having a contact hole that exposes the common line; a common electrode on the passivation layer and between the pixel electrode and each of the first and second data lines; an auxiliary common line on the passivation layer, the auxiliary common line overlapping and connected to the common line through the contact hole, the auxiliary common line parallel to the first and second data lines and crossing the gate line, the auxiliary common line completely covering the common line; and third and fourth connection electrodes on the passivation layer, extending from the auxiliary common line along the first direction, and connecting the auxiliary common line and the common electrode, wherein the third and fourth connection electrodes are disposed at both end portions of the common electrode, respectively, wherein the first connection electrode overlaps the third connection electrode and forms a first storage capacitor with the passivation layer therebetween, and the second connection electrode overlaps the fourth connection electrode and forms a second storage capacitor with the passivation layer therebetween.