Patent ID: 8587051

Claim:
An electrically erasable and programmable nonvolatile semiconductor memory device, comprising: a first conductivity-type semiconductor substrate; a second conductivity-type source region and a drain region disposed apart to face each other on a surface of the semiconductor substrate; a channel formation region sandwiched by the source region and the drain region, formed on the surface of the semiconductor substrate; a floating gate electrode disposed on a gate insulating film over the source region, the drain region and the channel region; a control gate electrode disposed on a control insulating film over the floating gate electrode and capacitively coupled to the floating gate electrode; and an injection region for solely injecting electrons into the floating gate electrode from the drain region and an ejection region for solely ejecting electrons from the floating gate electrode to the drain region, both disposed between the floating gate electrode and the drain region, each of the injection region and the ejection region having a tunnel insulating film, the injection region and the ejection region being distinguished by having a region of a different conductivity-type in a part of one of the floating gate electrode and the drain region.