Patent ID: 7446373

Claim:
A semiconductor component, in which, in a semiconductor material region or chip, provision is made of a trench structure semiconductor element arrangement with a semiconductor element cell array of a plurality of trench structure semiconductor elements arranged in strip form, in particular, in trench structures or trenches of the semiconductor material region, in which gate electrode regions or gate regions of the trench structure semiconductor elements are formed essentially in the interior of a respective trench structure and, in particular, in a manner electrically insulated from wall regions of the respective trench structure by an insulating oxide layer, in which source regions, body regions and, if appropriate, body contact regions of the trench structure semiconductor elements are in each case arranged in the mesa regions of the semiconductor material region between adjacent trench structures, the source regions in particular in each case being genuinely contained in the assigned body regions and in particular having a common surface region with the latter, in which the source regions and essentially the semiconductor material region are formed with a first conductivity type or conduction type and the body regions and, if appropriate, the body contact regions are formed with a second conductivity type or conduction type, and in which, at least in a first or upper edge region of the cell array and/or of the semiconductor material region and/or in a second or lateral edge region of the cell array and/or of the semiconductor material region, a surface region or modified doping region is provided which laterally encloses or embeds lateral end regions of the respective trench structure or at least one marginal mesa region with respect to the second or lateral edge region of a corresponding marginal trench structure and in which the doping or dopant concentration is formed such that it is lowered, in particular with respect to an actual doping concentration of a first epitaxial zone, and/or in which the conductivity type or conduction type is formed such that it is opposite to the actual conductivity type or conduction type of the semiconductor material region and, in particular, is of low concentration.