Patent ID: 8507378

Claim:
A method for fabricating a high voltage integrated circuit device, the method comprising: providing a semiconductor substrate comprising a surface region, the surface region comprising a contact region, the contact region being coupled to a source/drain region of a high voltage semiconductor device; forming a plasma enhanced oxide layer overlying the surface region; forming a stop layer overlying the plasma enhanced oxide layer; forming a first contact opening through a portion of the stop layer and through a portion of the plasma enhanced oxide layer to expose a portion of the contact region; forming a silicide layer overlying at least the exposed portion of the contact region to form a silicided contact region; forming an interdielectric layer having a first thickness portion overlying the silicided contact region to fill the first contact opening and having a second thickness portion overlying the stop layer; forming a masking layer overlying the interdielectric layer; forming an opening in the masking layer overlying a vicinity of the silicided contact region, the opening overlapping a portion of the stop layer; patterning the interdielectric layer to form a second opening extending through the first thickness portion to expose a portion of the silicided contact region and through the second thickness portion to expose the portion of the stop layer; maintaining the source/drain region free from any etching damage while patterning the interdielectric layer; and forming a contact plug layer overlying the exposed portion of the silicided contact region and the exposed portion of the stop layer, wherein the first contact opening has a width that is greater than a width of the second opening.