Patent ID: 7217649

Claim:
A method for forming a semiconductor in a dual damascene structure comprising: receiving a patterned semiconductor substrate, having a first conductive interconnect material filling a plurality of features in the pattern, the first conductive interconnect material having a non-planar overburden portion; planarizing the over burden portion without imparting mechanical stress to the plurality of features, leaving a remaining substantially planar overburden portion having a thickness of greater than zero angstroms and less than about 500 angstroms; applying a finish etch to remove the remaining substantially planar overburden portion; reducing a mask layer, the layer having an initial thickness of less than about 250 angstroms; forming a subsequent dielectric layer on the planarized over burden portion; forming a mask on the subsequent dielectric layer; forming one or more features in the subsequent dielectric layer; and filling the one or more features with a second conductive interconnect material.