Patent ID: 7599431

Claim:
A high speed serial receiver comprising: a linear equalizer operably coupled to equalize a serial stream of data to produce an equalized serial stream of data; a summing module operably coupled to sum at least one data element of the equalized serial stream of data with decision feedback equalization (DFE) data elements to produce equalized data elements; a decision module operably coupled to interpret the equalized data elements to produce interpreted data elements; and a decision feedback equalization (DFE) module operably coupled to produce the DFE data elements from the interpreted data elements, wherein the DFE module comprises: a plurality of delay elements operably coupled to delay the interpreted data elements to produce a plurality of delayed interpreted data elements; a plurality of gain stages, wherein at least one of the plurality of gain stages is operably coupled to apply gain to a corresponding one of the plurality of delayed interpreted data elements to produce the DFE data elements; and a delay element selector operably coupled to select one of the plurality of gain stages to produce the DFE data elements based on a channel response.