Patent ID: 7736967

Claim:
A method for manufacturing a OTP-EPROM device structure in an embedded EEPROM array comprising: providing a substrate including a surface region; providing a first cell region and a second cell region within the surface region of the substrate; forming a gate dielectric layer of a first thickness overlying the surface region of the substrate; forming a tunnel oxide window in a portion of the gate dielectric in the second cell region, the tunnel oxide window has a second thickness, the second thickness is less than the first thickness; forming a first OTP EPROM gate overlying the gate dielectric in the first cell region, an EEPROM floating gate and a select gate overlying the gate dielectric in the second cell region using a first polysilicon layer; forming a patterned mask overlying the second cell region associated with the EEPROM and exposing the first cell region associated with the OTP EPROM; forming an OTP EPROM source region and an OTP EPROM drain region in a portion of the substrate in the first cell region; forming an insulating layer overlying the first OTP EPROM gate, the EEPROM floating gate and the select gate; forming an OTP EPROM control gate, an EEPROM control gate and a removable second select gate overlying the insulating layer using a second polysilicon layer; removing the removable second select gate; forming a dielectric layer overlying the OTP EPROM gate structure, the EEPROM gate structure and the select gate; planarizing the dielectric layer; forming contact regions in the dielectric layer; forming a metal layer overlying the dielectric layer and the contact regions; wherein the OTP EPROM source region and the OTP EPROM drain region are provided by masking the second cell region associated with the EEPROM while exposing the first cell region associated with the OTP EPROM.