Patent ID: 6943373

Claim:
A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of static memory cells each including a first, second, third, fourth, fifth, and sixth transistors; and a first and second power lines, feeding operating voltage to said plurality of memory cells and formed of metal layers, wherein said first power line is coupled to sources of said first and second transistors, wherein said second power line is coupled to sources of said third and fourth transistors, wherein gates of said fifth and sixth transistors are coupled to said word lines, wherein source and drain regions of said fifth and sixth transistors are formed inside a semiconductor substrate, wherein said second power line is formed in a layer between a substrate surface of said semiconductor substrate and a layer forming said first power line, wherein channel regions, source and drain regions of said first and second transistors are formed by depositing three poly-silicon layers above the substrate surface, wherein vertical sides of said three poly-silicon layers, which surfaces are vertical against said substrate surface, are totally surrounded by a gate layer having a dioxide layer inbetween, and wherein said layer forming said second power line is formed between said three poly-silicon layers and said substrate surface.