Patent ID: 7111123

Claim:
A priority encoder for receiving a plurality of input signals and from said input signals generating output signals in accordance with an alterable priority sequence, said priority encoder comprising: a plurality of input circuits to receive said input signals from a content addressable memory (CAM) array; a CAM array word line decoder coupled to the CAM array that accesses locations of the CAM array and generates at least one priority transformation signal in response to a received address value; a priority setting circuit for receiving the at least one priority transformation signal that indicates a priority index for modification of said priority sequence; an encoding circuit in communication with said plurality of input circuits and said priority setting circuit for generating said output signals in accordance with said priority sequence; and an enabling circuit for receiving an enabling signal and for communicating said enabling signal to said encoding circuit, such that upon deactivation of said enabling signal, said encoding circuit generates said output signals in accordance with said priority sequence with no modification by said priority setting circuit.