Patent ID: 8364881

Claim:
A system, comprising: a plurality of NAND flash memory devices each having a NAND flash interface, wherein the NAND flash interface of each NAND flash memory device includes an 8-bit data bus, a Command Latch Enable signal, an Address Latch Enable signal, a Read Enable Signal, a Write Enable Signal, a Write Protect signal, and a Ready/busy signal; and a memory controller configured to utilize the 8-bit data bus to exchange data with the plurality of NAND flash memory devices, the Command Latch Enable signal as a synchronization signal when transmitting commands to the plurality of NAND flash memory devices via the 8-bit data bus, the Address Latch Enable signal as a clock signal when communicating with the plurality of NAND flash memory devices via the 8-bit data bus, the Read Enable signal as a read clock signal when reading data from the plurality of NAND flash memory devices via the 8-bit data bus, the Write Enable signal as a configuration signal when configuring the plurality of NAND flash memory devices via the 8-bit data bus, and the Ready/busy signal as an interrupt when performing program and erase operations on the plurality of NAND flash memory devices via the 8-bit data bus, and wherein the memory controller is further configured to select a first NAND flash memory device of the plurality of NAND flash memory devices, without using a Chip Enable signal of the NAND flash interface, by transmitting, on the 8-bit data bus, an identification byte identifying the first NAND flash memory device, transmit, on the 8-bit data bus, a command byte to the first NAND flash memory device, wherein the first NAND flash memory device is configured to (i) perform an operation indicated by the command byte, and (ii) use the Ready/busy signal to indicate completion of the command to the memory controller, transmit, via the 8-bit data bus, the identification byte and the command byte to the first NAND flash memory device by transitioning the Command Latch Enable signal to a first state, wherein the command byte includes a command to program the first NAND flash memory device, transmit, via the 8-bit data bus, a plurality of parameter bytes and a plurality of data bytes following the identification byte and the command byte to the first NAND flash memory device, and transition the Command Latch Enable signal to a second state to terminate the command to program the first NAND flash memory device, wherein the second state is opposite of the first state, and write the plurality of data bytes to a buffer instead of writing the plurality of data bytes to the first NAND flash memory device in response to (i) the Command Latch Enable signal transitioning to the second state, and (ii) the Ready/busy signal not indicating completion of the command to program within a predetermined number of cycles of the Address Latch Enable signal after the Command Latch Enable signal transitions to the second state.