Patent ID: 8625360

Claim:
A semiconductor storage device comprising: a memory cell array including a plurality of memory cells arranged in a matrix; a first comparator comparing data output to a bit line from the memory cell by activating a word line with first search data; a second comparator comparing data output to the bit line from the memory cell by activating the word line with second search data; an address generator sequentially generating a row address; a row decoder activating any of word lines within the memory cell array according to the generated row address; a first priority encoder coupled to the address generator and latching a row address when the first comparator determines coincidence; and a second priority encoder coupled to the address generator and latching a row address when the second comparator determines coincidence, wherein data output to the bit line by activating one word line is input to both the first comparator and second comparator, wherein the first and second priority encoders latch a row address with higher priority if there is a plurality of row addresses when the coincidence is determined, wherein the address generator cyclically generates row addresses from a small value in ascending order, wherein the first and second priority encoders latch a row address with a smaller value if there is a plurality of row addresses when coincidence is determined, and wherein the second priority encoder latches a row address when coincidence is determined first, resets at the same time a row address that is latched when the first row address is input, and latches a row address when coincidence is determined next.