Patent ID: 8617986

Claim:
A method for forming an integrated circuit, said method comprising: forming a first dielectric layer over a gate electrode of a transistor; forming an etch-stop layer over the first dielectric layer, the etch-stop layer further has a first top surface and a second top surface, the first top surface is not level with the second top surface; forming an opening through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor; forming a metal layer in the opening, contacting the S/D region of the transistor, the metal layer having a first surface that extends substantially parallel to an interface between the first dielectric layer and the etch-stop layer and is substantially level with the first top surface of the etch-stop layer, the metal layer is formed at an interface of the first top surface and the second top surface; and forming a damascene structure coupled with the metal layer.