Patent ID: 7978116

Claim:
An apparatus comprising: a pipelined analog-to-digital converter comprising a control and correction circuit; and a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade to one another, wherein at least one of the MDAC stages comprises: an MDAC input configured to receive an analog input voltage; a first flash analog-to-digital converter (ADC) having an input coupled to the MDAC input, wherein the first flash ADC is configured to generate a first digital signal; and a second flash ADC having an input coupled to the MDAC input, wherein the second flash ADC is configured to generate a second digital signal, wherein the first flash ADC and the second flash ADC alternate analog-to-digital conversion in response to control from the control and correction circuit, wherein the at least one of the MDAC stages further comprises: a delay circuit configured to delay the analog input voltage to generate a delayed input voltage; a capacitor block configured to sample and hold the delayed input voltage the capacitor block comprising n number of sub-capacitor blocks, each of the sub-capacitor blocks being configured to subtract a reference voltage from the delayed input voltage to generate a residue signal; and an amplifier configured to amplify the residue signals from the sub-capacitor blocks.