Patent ID: 7146454

Claim:
A memory device architecture comprising: a first bi-directional bus and a second bi-directional bus, said first and second bi-directional buses in parallel coupling a plurality of memory banks with a data cache, said first and second bi-directional buses for reading data from said plurality of memory banks and writing said data to said cache; a first memory bank coupled to said first and second bi-directional buses; a second memory bank coupled to said first and second bi-directional buses; and a cache TAG coupled to said first and second bi-directional buses; wherein a modifiable bit in said cache TAG is configured to control write-back to said first memory bank or said second memory bank from said data cache, wherein during a write cycle and a cache miss with said modifiable bit set: data in said data cache is written back to a first memory location in said first memory bank; input data is written into a second memory location in said second memory bank; said input data is read out from said second memory location and written to said data cache at a corresponding location; and unsetting said modifiable bit.