Patent ID: 7490307

Claim:
An apparatus comprising: a database configured to generate one or more database files representing a design of an integrated circuit (IC); an input module comprising a test insertion application configured to generate one or more test structures and simulation vectors to test predetermined portions of said design of an IC; and a software tool configured to automatically (i) generate test scripts to setup and control a static timing analysis (STA) tool to verify timing constraints of said one or more test structures and (ii) report only those timing issues relevant to the one or more test structures by filtering false timing violations reported by the STA tool, wherein said software tool (A) reads and extracts information about the one or more test structures from the test insertion application tightly linked to the generation of simulation vectors for the one or more test structures and utilizes a pre-layout netlist of a test access port (TAP) controller to define pre-layout registers and port associations of the test access port and (B) is further configured to automatically (i) merge timing constraints of overlapping logic between said tests structures and a functional portion of said IC and (II) generate said scripts to verify timing constraints of said overlapping logic between said test structures and said functional portion of said IC.