Patent ID: 7869288

Claim:
An output enable signal generating circuit for a semiconductor memory apparatus, the circuit comprising: an output control unit configured to receive Column Address Strobe (CAS) latency information and to generate an output control signal having enable timing according to a DLL on/off mode; and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal, wherein the CAS latency information is carried on a CAS latency signal and the DLL on/off mode is defined by a DLL on mode signal, and wherein the output control unit includes: a CAS latency delay unit configured to generate a CAS latency delay signal in response to a reset signal, an external clock signal, and the CAS latency signal; a DLL on delay control unit configured to generate a DLL on output delay signal in response to the reset signal and the CAS latency delay signal; a DLL off delay control unit configured to generate a DLL off output delay signal in response to the reset signal and the CAS latency delay signal; and a switching unit configured to output the DLL on output delay signal or the DLL off output delay signal as an output control signal in response to the DLL on mode signal.