Patent ID: 8174286

Claim:
A transceiver circuit, comprising: a first connection for injecting a transmit/receive selection signal; a second connection for injecting a data signal to be transmitted; a third connection for outputting a further data signal; a fourth connection for a data transmission line; a circuit configuration, which in response to a receive signal at said first connection, makes available at said fourth connection a voltage corresponding approximately to half an operating voltage, wherein an effective terminating resistance at said fourth connection corresponds approximately to a resistance of the data transmission line for achieving line matching at a receiver end and a signal received via the data transmission line is evaluated and output at said third connection; and said circuit configuration in response to a transmit signal at said first connection, makes available at said fourth connection a further voltage corresponding approximately to the operating voltage, if a LOW signal is injected at said second connection and at said fourth connection makes available an additional voltage corresponding approximately to a ground potential if a HIGH signal is injected at said second connection, wherein in both cases an effective source resistance corresponds approximately to the resistance of the data transmission line for achieving line matching at a transmitter end; said circuit configuration including a first resistor and a second resistor, wherein at least said first resistor and said second resistor form said effective terminating resistance at said fourth connection in response to said receive signal at said first connection, and at least said first resistor and said second resistor form said effective source resistance at said fourth connection in response to said transmit signal at said first connection.