Patent ID: 7272024

Claim:
A synchronized rectification circuit comprising: an inputting means for inputting an AC voltage that becomes a negative polarity voltage in a first period, becomes a positive polarity voltage in a third period, and becomes an intermediate voltage between said negative voltage and said positive voltage in second and forth periods; a rectification means including a first switch element and a second switch element and for inputting said AC voltage from said inputting means; a first voltage holding means for holding a voltage in response to shift an input voltage of the rectification means to said positive polarity voltage and releasing the held voltage in response to input said negative voltage; a second voltage holding means connected with said first voltage holding means capable to equalize held voltages in response to sift said input voltage to said intermediate voltage, for holding a voltage in response to shift said input voltage to said negative polarity voltage and releasing the held voltage in response to input said positive voltage; a first driving means for turning on said first switch element according to said held voltage of said first voltage holding means changed in response to shift said input voltage to said intermediate voltage from said negative polarity voltage and turning off said first switch element earlier than a time where said input voltage shifts to said negative polarity voltage from said intermediate voltage; and a second driving means for turning on said second switch element according to said held voltage of said second voltage holding means changed in response to shift said input voltage to said intermediate voltage from said positive polarity voltage and turning off said second switch element earlier than a time where said input voltage shifts to said positive polarity voltage from said intermediate voltage.