Patent ID: 7412000

Claim:
A system for demodulating a current complementary code keying (CCK) symbol, being one of n symbols, and a previous decision into decision data, where said symbol is formed from a plurality of CCK chips, said system comprising: a first plurality said n/16 of post-equalization registers, each said register having a post-equalization estimate containing an inter-chip interference correction derived from said complementary code keying symbols and a channel characteristic; an iteration variable k generating a phase φ 2 ; a pre-equalization register having an inter-symbol interference correction value based on one or more previous symbol decisions compensated with a channel characteristic; a first subtractor having a first input coupled to said current symbol, a second input coupled to said pre-equalization register, and an output equal to said second input subtracted from said first input; a demodulator including in sequence: a Fast Walsh Transform (FWT) with an FWT input and an FWT output, said FWT input coupled to said first subtractor output, said FWT also coupled to said phase φ 2 for use as an FWT butterfly input; a second subtracter having an output formed by subtracting said post-equalization register values from said FWT output; a demodulator biggest picker coupled to said second subtracter output, said demodulator picker having a MAX(k) output equal to the largest magnitude said second subtracter output, and an OUTPUT(k) indicating which said second subtracter output was the largest magnitude; the demodulator having an output coupled to said demodulator biggest picker; a final biggest picker coupled to said demodulator output and also to said k, such that for all said k, said final biggest picker selects the largest magnitude said MAX(k), and forms a data decision using said k, the phase of said MAX(k), and said OUTPUT(k) associated with said MAX(k) where said iteration variable k has more than one value for a said CCK symbol.