Patent ID: 8829978

Claim:
An internal voltage generating circuit of a semiconductor memory apparatus comprising: an internal voltage level detecting unit configured to compare an internal voltage with a target voltage and then generate a detection signal; and an internal voltage level control unit configured to increase an increment range of the internal voltage as a voltage level of the detection signal is lowered, wherein the internal voltage level detecting unit is configured to lower the voltage level of the detection signal as a voltage difference between the internal voltage and the target voltage becomes larger, is configured to enable the detection signal when the internal voltage is lower than the target voltage and control the voltage level of the detection signal based on the voltage difference between the internal voltage and the target voltage and wherein the internal voltage level detecting unit comprises: a comparison unit configured to compare the internal voltage with a reference voltage and then generate a preliminary detection signal; a control voltage generating unit configured to compare the internal voltage with the reference voltage and then determine a control voltage; and a driving unit configured to output the detection signal by driving the preliminary detection signal to the control voltage.