Patent ID: 8799581

Claim:
An apparatus comprising: one or more processors having access to one or more caches, the one or more caches comprising one or more cache lines; a generator that generates memory access operations in response to software running on the apparatus; an assignor that assigns a color to the memory access operations; a receiver that receives and records color information for each cache line in response to a memory access operation utilizing a cache line; and a storage device configured to maintain the color information in color-based counters, wherein at least one of the color-based counters comprises one of: a first counter type comprising a two-dimensional matrix, the two-dimensional matrix including an event dimension and a color dimension, the event dimension representing a specific cache line event, the first counter type representing a number of times that the specific cache line event happens on a specific color represented by the color dimension; and a second counter type comprising a three-dimensional matrix, the three-dimensional matrix including an event dimension, a first color dimension, and a second color dimension, the event dimension representing a specific cache line event, the second counter type representing a number of times that, with respect to a specific cache line event, a color represented by the first color dimension interacts with a color represented by the second color dimension; and wherein hardware of the apparatus is configured to monitor said color-based counters to obtain feedback on one or more cache line events.