Patent ID: 6876405

Claim:
A method for fabricating a thin film transistor array substrate having a display area and a peripheral area, comprising steps of: forming a gate line assembly and a common electrode line assembly on a substrate, the gate line assembly comprising a plurality of gate lines, a plurality of gate electrodes and a plurality of gate pads, the common electrode line assembly comprising a plurality of common signal lines and plurality of common electrodes, the gate pads being arranged in the peripheral area; placing a shadow frame over the substrate, the shadow frame comprising a first deposition blocking area covering the gate pads; forming a gate insulating layer covering the gate line assembly and exposing the portions of the gate pads; forming a semiconductor layer; forming an ohmic contact layer; and forming a data line layer; forming a conductive layer; and simultaneously patterning the semiconductor layer, the ohmic contact layer, the data line layer and the conductive layer to from a semiconductor pattern, an ohmic contact pattern, a data line assembly and a plurality of pixel electrodes, respectively, the data line assembly comprising a plurality of data lines, a plurality of source electrodes, a plurality of drain electrodes and a plurality of data pads, the data pads being arranged in the peripheral area, wherein the step of simultaneously patterning is performed by using a single photoresist pattern comprising: a first portion placed between the source electrode and the drain electrode having a first thickness; a second portion for forming the data line assembly and the pixel electrodes and having a second thickness greater than the first thickness; and a third portion having a third thickness smaller than the first portion.