Patent ID: 7196378

Claim:
A semiconductor apparatus which protects a first-conductivity-type MOS output transistor and a second-conductivity-type MOS output transistor against a surge entering through an output electrode connected to each of drains of said first-conductivity-type MOS output transistor whose source is connected to ground and said second-conductivity-type MOS output transistor whose source is connected to a power supply, said apparatus comprising: a first-conductivity-type MOS protection transistor having a drain connected to the drain of said first-conductivity-type MOS output transistor, a source connected to a source of said first-conductivity-type MOS output transistor, and a gate connected to a second-conductivity-type layer under a gate of said first-conductivity-type MOS output transistor; and a second-conductivity-type MOS protection transistor having a drain connected to the drain of said second-conductivity-type MOS output transistor, a source connected to a source of said second-conductivity-type MOS output transistor, and a gate connected to a first-conductivity-type layer under a gate of said second-conductivity-type MOS output transistor; wherein said first-conductivity-type MOS output transistor further includes a second-conductivity-type area which is formed in said second-conductivity-type layer and substantially surrounds said drain electrode and said source electrode, wherein said second-conductivity-type area has higher dopant concentration than said second-conductivity-type layer.