Patent ID: 7856545

Claim:
A method for co-processing, comprising: coupling an accelerator module to a microprocessor bus, the accelerator module including a Field Programmable Gate Array (“FPGA”); loading a microprocessor bus interface bitstream into the FPGA to program programmable logic thereof; transferring data to first memory of the accelerator module via a microprocessor bus using a microprocessor bus interface instantiated in the FPGA responsive to the microprocessor bus interface bitstream; instantiating a default configuration bitstream stored in the first memory in the FPGA to configure the FPGA to have the microprocessor bus interface with sufficient functionality to be recognized by a microprocessor coupled to the microprocessor bus; and communicating under control of the microprocessor a configuration pattern to second memory of the accelerator module using a first memory interface instantiated in the FPGA responsive to the instantiating of the default configuration bitstream.