Patent ID: 7237153

Claim:
A method for testing an integrated memory having a main data memory with a plurality of data memory units, comprising: a) addressing a data memory unit by applying an address of the data memory unit to an address bus operably coupled to the main data memory; b) applying input test data to a data bus operably coupled to the main data memory to test the addressed data memory unit; c) reading out output test data from the addressed data memory unit; d) comparing the output test data with expected desired output test data; e) storing the applied address, the expected desired output test data, and the output test data as information in a redundancy analysis memory if a deviation of the output test data from the desired output test data occurs; f) providing first redundant areas in the redundancy analysis memory and providing at least second redundant areas outside the redundancy analysis memory; and g) determining a repair strategy by means of the first and second redundant areas on the basis of the information stored in the redundancy analysis memory, wherein determining the repair strategy in accordance with step g) further comprises the following if the storage capacity of the redundancy analysis memory is exceeded by the number of defective data memory units detected, that are stored in the redundancy analysis memory, and a first test run is not yet concluded: h) reading out of the information items stored in the redundancy analysis memory into a computing unit; i) determining an intermediate repair strategy in the computing unit by means of the at least second redundant areas; j) continuing the first test run if the first test run is interrupted before step h); and k) repeating steps a) to j).