Patent ID: 7291925

Claim:
A stack package comprising: an upper chip scale package (CSP), the upper CSP including a plurality of conductive structures projecting from a lower surface, a circuit board, a first conductive pattern formed on a lower surface of the circuit board, and a semiconductor chip mounted on an upper surface of the circuit board and electrically connected to the first conductive pattern, wherein the conductive structures are provided on a peripheral region of the circuit board; a lower chip scale package (CSP), the lower CSP including a plurality of conductive regions provided on an upper surface, a circuit board, a first conductive pattern formed on a lower surface of the circuit board and a second conductive pattern formed on an upper surface of the circuit board, and a semiconductor chip mounted on the upper surface of the circuit board and electrically connected to the first conductive pattern, wherein the conductive regions are provided on a peripheral region of the circuit board; the upper CSP and the lower CSP arranged in a stacked configuration wherein the conductive structures of the upper CSP are aligned with corresponding conductive regions on the lower CSP; and an anisotropic conductive film (ACF) provided between a lower surface of the conductive structures and an upper surface of the corresponding conductive regions, wherein the ACF establishes an electrical connection and a mechanical connection between the conductive structures and the conductive regions to form the stack package.