Patent ID: 8238133

Claim:
A device comprising: a semiconductor memory chip configured to perform data read and write operations in one of 8-bit, 16-bit and 32-bit units; and a package substrate on which the semiconductor memory chip is mounted, the package substrate including a plurality of pins; the semiconductor memory chip comprising: at least two rows of chip pads, each of the rows including a plurality of chip pads electrically connected to the pins of the package substrate, respectively, a first circuit producing a read data strobe signal, a second circuit producing a data signal, and a selection circuit provided among one of the chip pads, the first circuit and the second circuit, the selection circuit electrically connecting the one of the chip pads to the first circuit when the semiconductor memory chip is configured to perform the data read and write operations in 8-bit unit and to the second circuit when the semiconductor memory chip is configured to perform the data read and write operations in 16-bit unit.