Patent ID: 7119015

Claim:
A method for forming a polysilicon plug of a semiconductor device, comprising the steps of: (a) forming a stacked pattern of a wordline and a hard mask film on a semiconductor substrate comprising a cell region and a peripheral circuit region; (b) forming a spacer on a sidewall of the stacked pattern; (c) forming an interlayer insulating film on the semiconductor substrate; (d) polishing the interlayer insulating film via a CMP process until the hard mask film is exposed to planarize an entire surface of the resulting structure; (e) forming a barrier film on the planarized entire surface of the exposed hard mask film and the interlayer insulating film; (f) selectively etching the barrier film and the interlayer insulating film to form a landing plug contact hole; (g) depositing a polysilicon film filling the landing plug contact hole on the semiconductor substrate; (h) blanket-etching the polysilicon film using the barrier film as an etching barrier film; and (i) polishing the polysilicon film and the barrier film using the hard mask film as a polishing barrier film to form a polysilicon plug.