Patent ID: 7873812

Claim:
A method for performing matrix multiplication of a first matrix and a second matrix in parallel, comprising: a) providing a vector register array with the ability to store a plurality of vectors, wherein each of said plurality of vectors contains N vector elements, said plurality of vectors includes a first source vector, a second source vector, and a control vector; b) storing elements of a column of said first matrix into said first source vector; c) storing elements of a respective row of said second matrix into said second source vector, wherein said respective row is equal-numbered as said column; d) storing mapping information of said first source vector and said second source vector into said control vector; e) mapping elements of said first source vector; f) mapping elements of said second source vector; g) performing a vector multiplication of respective elements of said mapped first source vector and said mapped second source vector; h) performing a vector addition of results of said vector multiplication to a vector accumulator; i) repeating steps of b through h for all column vectors of said first matrix; and wherein steps of e through g are performed by a vector multiply instruction in a single pipelined clock cycle.