Patent ID: 8823418

Claim:
A power-on-detection (POD) circuit, comprising: first and second comparator circuits each having first and second inputs, the first inputs of the first and second comparator circuits receiving a reference voltage from a reference voltage source node; a voltage divider circuit including first, second, and third resistors, the first and second resistors coupled together at a first node, the second and third resistors coupled together at a second node, the first node of the voltage divider is coupled directly to the second input of the first comparator circuit and the second node of the voltage divider circuit is coupled directly to the second input of the second comparator circuit; a detection circuit coupled between a first voltage source node and the first resistor of the voltage divider circuit, the detection circuit generating a control signal in response to the first voltage source node having a voltage potential higher than a ground potential, the control signal controlling the turning on and off of the first and second comparator circuits; and logic circuitry coupled to an output of each of the first and second comparator circuits, the logic circuitry outputting a power identification signal based on the outputs of the first and second comparator circuits and the control signal generated by and received from the detection circuit, wherein the detection circuit includes: a first MOS transistor having a source coupled to the first voltage source node; a second MOS transistor having a source and a drain, the drain of the second MOS transistor coupled to a drain of the first MOS transistor: a third MOS transistor having a drain coupled to the first resistor of the voltage divider, a source coupled to the first voltage source node, and a gate coupled to the drains of the first and second MOS transistors at a third node; and a capacitor coupled between the first voltage source node and the third node.