Patent ID: 7408377

Claim:
A driving circuit for an output buffer stage comprising a PMOS transistor and an NMOS transistor coupled together, the driving circuit comprising: a first circuit portion for generating a driving signal for the NMOS transistor of the output buffer stage, and a second circuit portion for generating a driving signal for the PMOS transistor of the output buffer stage; each of said first and second circuit portions comprising a complementary pair of MOS transistors coupled together and having respective conduction terminals directly coupled to supply voltage references, said complementary pair of MOS transistors defining an interconnection node therebetween, a logic network to generate an activation signal and comprising a delay chain including a plurality of identical logic gates coupled in series, and a third MOS transistor having conduction terminals coupled between one of the voltage references and the interconnection node, and a control terminal responsive to the activation signal, said third MOS transistor of said first circuit portion comprising a PMOS transistor, said third MOS transistor of said second circuit portion comprising an NMOS transistor.