Patent ID: 8809141

Claim:
A method of forming an integrated circuit, comprising: providing a semiconductor substrate; forming a gate dielectric layer on a surface of said semiconductor substrate; forming a first gate electrode over said gate dielectric layer for a PMOS device; forming a second gate electrode over said gate dielectric layer for an NMOS device; forming sidewall structures adjacent said first gate electrode and said second gate electrode; forming source and drain regions in said semiconductor substrate adjacent said sidewall structures; forming a high stress liner layer over the first gate electrode, the second gate electrode and the source and drain regions by: forming a silicon nitride layer with a hydrogen concentration greater than 20 atomic percent and a first tensile stress over said first gate electrode, said second gate electrode, and said source and drain regions; and thermally annealing said silicon nitride layer before forming any additional layers on the silicon nitride layer, resulting in a second tensile stress greater than 800 mPa and a second hydrogen concentration greater than 12 atomic % in said silicon nitride layer for the PMOS device and the NMOS device thereby exerting a tensile stress in a channel region of the NMOS device, enhancing channel mobility for the NMOS device without substantially affecting channel mobility of the PMOS device; and forming a pre-metal dielectric (PMD) layer on the high stress liner layer after thermal annealing.