Patent ID: 8077512

Claim:
A flash memory cell, comprising: a first charge-trapping region and a second charge-trapping region both disposed in a semiconductor substrate; a first dielectric layer separating the semiconductor substrate from the first charge-trapping region and the second charge-trapping region; a first conductor disposed above the first charge-trapping region, and applied by a first voltage; a second conductor disposed above the second charge-trapping region, and applied by a second voltage; a first doped region disposed in the semiconductor substrate at a first side of the first charge-trapping region, and applied by a third voltage; a second doped region disposed in the semiconductor substrate at a second side of the first charge-trapping region, and applied by a fourth voltage; a second dielectric layer separating the first charge-trapping region from the first conductor and separating the second charge-trapping region from the second conductor; and wherein during a programming operation, the third voltage is a ground voltage, the fourth voltage is positive, and the first voltage and the second voltage are selected from the range of the third voltage to the fourth voltage, the second charge-trapping region is configured to influence the conduction behavior of a carrier channel in the semiconductor substrate under the first charge-trapping region, the first conductor and the second conductor are arranged in mirror-image symmetry with respect to the second doped region, and the first charge-trapping region and the second charge-trapping region are arranged in mirror-image symmetry with respect to the second doped region.