Patent ID: 8791032

Claim:
A method of manufacturing a thin film transistor (TFT), the method comprising the steps of: forming a buffer layer, an amorphous silicon layer, and an insulating layer on a substrate; crystallizing the amorphous silicon layer as a polycrystalline silicon layer; forming a semiconductor layer and a gate insulating layer which have a predetermined shape by simultaneously patterning the polycrystalline silicon layer and the insulating layer; forming a gate electrode including a first portion and a second portion by forming and patterning a metal layer on the gate insulating layer, wherein the first portion is formed on the gate insulating layer and overlapped with a channel region of the semiconductor layer, and wherein the second portion contacts the semiconductor layer; forming a source region and a drain region on the semiconductor layer by performing doping on a region of the semiconductor layer, wherein the region does not include the channel region overlapping the gate electrode and constitutes a region which does not overlap the gate electrode; forming an interlayer insulating layer on the gate electrode so as to cover the gate insulating layer; forming contact holes on the interlayer insulating layer and the gate insulating layer so as to expose the source region and the drain region, and simultaneously forming an opening for exposing the second portion; and forming a source electrode and a drain electrode by forming and patterning a conductive layer on the interlayer insulating layer, wherein the source electrode and the drain electrode are electrically connected to the source region and the drain region, respectively, via the contact holes, and simultaneously removing the second portion exposed via the opening.