Patent ID: 7558924

Claim:
A memory system comprising: an array of memory cells of a first type; a register having memory cells of a second type, wherein the second type of memory cells stabilize voltage levels corresponding to data therein more quickly than the first type of memory cells; and control circuitry coupled to the array and the register, wherein the control circuitry concurrently writes identical data into memory cells of the array and memory cells of the register, and to read data from the register when a read operation is directed at least in part to a memory location to which a preceding write operation was directed, wherein the control circuitry reads the data only from the register when the read operation is performed in a second processing cycle immediately following a first processing cycle in which the write operation is performed, and wherein the control circuitry reads the data only from the array when a second read operation is performed in a third processing cycle immediately following the second processing cycle.