Patent ID: 7416971

Claim:
A method for fabricating a chip comprising: providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said first metallization structure and exposes said contact point; forming a second metallization structure over said contact point and over said passivation layer, wherein said second metallization structure is connected to said contact point through said first opening, and wherein said forming said second metallization structure comprises sputtering a first adhesion layer over said contact point and over said passivation layer, sputtering a first seed layer over said first adhesion layer, forming a first photoresist layer on said first seed layer, wherein a second opening in said first photoresist layer exposes said first seed layer, electroplating a first bulk metal layer on said first seed layer exposed by said second opening, removing said first photoresist layer, and removing said first seed layer and said first adhesion layer not under said first bulk metal layer; forming a polymer layer on said second metallization structure and over said passivation layer; polishing said polymer layer; and after said polishing said polymer layer, forming a third metallization structure on said polymer layer, wherein said forming said third metallization structure comprises sputtering a second adhesion layer over said polymer layer, sputtering a second seed layer over said second adhesion layer, forming a second photoresist layer on said second seed layer, wherein a third opening in said second photoresist layer exposes said second seed layer, electroplating a second bulk metal layer on said second seed layer exposed by said third opening, removing said second photoresist layer, and removing said second seed layer and said second adhesion layer not under said second bulk metal layer.