Patent ID: 7389452

Claim:
An integrated circuit comprising: first and second circuit blocks each comprising a first internal node; first and second multiplexer circuits each comprising first and second input nodes, a control node, and an output node, the first input node of the first multiplexer circuit coupled to the first internal node of the first circuit block, the first input node of the second multiplexer circuit coupled to the first internal node of the second circuit block, the second input nodes of the first and second multiplexer circuits coupled to logical 0, the control signal nodes of the first and second multiplexer circuits coupled to a control signal; and an OR gate comprising a first input node coupled to the output node of the first multiplexer circuit, a second input node coupled to the output node of the second multiplexer circuit, and an output node; wherein the control signal may be used to select the first internal node of the first circuit block or the first internal node of the second circuit block for monitoring at the output node of the OR gate.