Patent ID: 7062666

Claim:
A method for suspending operation of a pipelined data processor to reduce power consumption, comprising: enabling a first clock signal in response to an occurrence of a first combination of respective states of one or more clock control signals; advancing a sequence of instructions to a first portion of a pipeline subcircuit; executing said advanced sequence of instructions with a second portion of said pipeline subcircuit subsequent to said first pipeline subcircuit portion in response to said enabled first clock signal; and detecting an occurrence of a second combination of said respective states of said one or more clock control signals and in response thereto interrupting said advancing of said sequence of instructions to said first pipeline subcircuit portion, followed by completing executing of said advanced sequence of instructions which had been advanced to said first pipeline subcircuit portion, wherein said advanced sequence of instructions being executed had been advanced to said first pipeline subcircuit portion prior to said interrupting, followed by executing with said second pipeline subcircuit portion a plurality of microcode substantially unrelated to said advanced sequence of instructions in response to said enabled first clock signal, and followed further by disabling said first clock signal.