Patent ID: 6897521

Claim:
A split gate flash memory cell, comprising: a substrate, wherein a device isolation structure is configured in the substrate to define an active region; a selective gate structure, disposed on the substrate, wherein the selective gate structure comprises, sequentially from the substrate, a first gate dielectric layer, a selective gate and a cap layer; a spacer, disposed on a sidewall of the selective gate structure; an interlayer dielectric layer, disposed on the substrate, wherein the interlayer dielectric layer comprises an opening, disposed on one side of the selective gate structure, exposing a portion of the selective gate structure, the substrate and the device isolation structure; a floating gate, disposed in the opening, wherein a portion of the floating gate extends to cover a surface of the interlayer dielectric layer; a tunneling dielectric layer, disposed between the substrate and the floating gate; a control gate, formed over the floating gate and disposed in the opening, filling the opening and extending above the selective gate structure; a second gate dielectric layer, disposed between the floating gate and the control gate; a source region, disposed in the substrate at a side of the control gate that is not adjacent to the selective gate; and a drain region, disposed in the substrate on a side of the selective gate that is not adjacent to the control gate.