Patent ID: 7188263

Claim:
An apparatus for controlling a power state of a multi-lane serial bus link having a plurality of power states, the apparatus comprising: a plurality of lane interface units for a plurality of serial data lanes of said serial bus link; leakage current test circuitry configured to place selected circuits into a quiescent mode for leakage current testing; a plurality of state transition detection circuits, each one of said plurality of state transition detection circuits being associated with one of said plurality of lane interface units and being adapted to detect information indicative of whether its associated lane is to transition out of a particular power consumptive state, said plurality of state transition detection circuits coupled to a portion of said leakage test circuitry, wherein a subset of said state transition circuits are adapted to be disabled by said leakage current test circuitry in a power savings mode with at least one state transition circuit remaining operative as a trigger detector to monitor for subsequent state transition control signals on the behalf of said subset of state transition circuits.