Patent ID: 7271666

Claim:
A phase-lock loop circuit, comprising: a voltage controlled oscillator (VCO) having an output for providing a timebase; a phase comparator for comparing a phase of a reference clock to a local timebase derived from said output of said VCO; a loop filter for filtering an output of said phase comparator and having an output coupled to an input of said VCO; a divider for dividing one of the reference clock and said timebase prior to entering said phase comparator according to a divisor, wherein said divider has an input for receiving an adjustment value that alters the divisor of said divider; a delta-sigma modulator for supplying said adjustment value to said divider; a cancellation signal generating circuit for measuring a quantization error of said modulator and generating a jitter cancellation signal therefrom; and an analog high-pass filter for filtering said jitter cancellation signal and having an output coupled to an input of said loop filter.