Patent ID: 8008157

Claim:
A method of forming a semiconductor structure, the method comprising: providing a semiconductor substrate comprising a PMOS region and an NMOS region; forming a PMOS device in the PMOS region comprising: forming a first gate stack on the semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in the semiconductor substrate using the first offset spacer as a mask, wherein a top surface of the stressor is substantially level with or higher than a top surface of the semiconductor substrate; and epitaxially growing a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region is in-situ doped with a first p-type dopant; and forming an NMOS device in the NMOS region comprising: forming a second gate stack on the semiconductor substrate; forming a second offset spacer on a sidewall of the second gate stack; epitaxially growing a second raised source/drain extension region on the semiconductor substrate using the second offset spacer as a mask, wherein the second raised source/drain extension region is in-situ doped with a first n-type dopant; and forming a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from the stressor formed in the semiconductor substrate.