Patent ID: 8458791

Claim:
A hardware hypervisor for modifying a host processor system to provide security against malware, the host processor system having at least a central processing unit (CPU) with a memory management unit (MMU), a high-speed bus for providing data links between the CPU, other bus masters, and peripherals, wherein one of the bus masters is a debug interface unit, the hypervisor comprising: a monitor co-processor having its hardware processing elements different from, and configured to operate independently from, the host processor system; a communications interface for providing a hardwired communications link between the monitor co-processor and the debug interface unit; wherein the communications interface is a hardware modification of the debug interface unit; a behavioral interface on the high-speed bus, configured to monitor control signals from the CPU and transactions on system interconnects; wherein the behavioral interface has an MMU tracer configured to monitor changes in a context number stored in the MMU and a lapse of time between each change; an access controller on the high-speed bus, configured to store access control data, to intercept requests on the high-speed bus that are associated with operation of the host processor system, to evaluate the requests against the access control data, and to grant or deny the requests; and wherein the behavioral interface and the access controller are accessible to the monitor co-processor via the communications interface and are implemented as slave peripheral hardware devices on the high speed bus.