Patent ID: 7126507

Claim:
An analog-digital converter, comprising: a sample-and-hold amplifier for sampling an analog input signal using clock boosting; a first analog-digital converter for receiving a signal sampled by the sample-and-hold amplifier, and converting the sampled signal into a plurality of bits of first digital output code; a multiple digital-analog converter for receiving and storing the signal sampled by the sample-and-hold amplifier, and amplifying and outputting difference between the stored signal and an analog signal corresponding to the first digital output code; a second analog-digital converter for receiving the output signal of the multiple digital-analog converter, and converting the output signal into a plurality of bits of second digital output code; and a digital correction logic for receiving the first digital output code and the second digital output code, overlapping certain bits of the first digital output code with certain bits of the second digital output code, and outputting remaining bits, exclusive of overlapping bits, as final digital output code, wherein the sample-and-hold amplifier comprises a clock boosting circuit that is connected to an input terminal, to which the analog input signal is input, and a gate of a switch transistor, which is connected to the input terminal, so as to maintain an ON resistance of the switch transistor at a small and constant value and fixed input impedance.