Patent ID: 7362640

Claim:
A dynamic random access memory (DRAM) device comprising: an array of DRAM cells arranged in rows by columns, each DRAM cell of the array being coupled to a wordline of a corresponding row and a bitline of a corresponding column; and refresh circuitry for refreshing data stored in the DRAM cells coupled to wordlines of a first set of rows as main data and for overwriting assistant data into the DRAM cells coupled to wordlines of a second set of rows in a self-refresh mode, the assistant data being opposite data to the main data, each row of the second set being adjacent to each row of the first set, the refresh circuitry comprising: a mode entry detector for detecting an entry into the self-refresh mode to retain the main data and to overwrite the assistant data, the mode entry detector producing a first self-refresh mode signal when entry into the self-refresh mode is detected; dummy establishing circuitry for detecting a starting refresh address for operation of the self-refresh mode in response to the first self-refresh mode signal, and for executing a dummy refresh cycle if the detected starting refresh address mismatches with a predetermined address, wherein no refresh operation occurs during the dummy refresh cycle; entry signal producing circuitry for producing a self-refresh entry signal in response to the first self-refresh mode signal; and adoption circuitry for adopting the dummy refresh cycle in the self-refresh mode.