Patent ID: 8406066

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell transistor configured to electrically rewrite data; a word line connected to a gate of the memory cell transistor; a row decoder which applies a read voltage to the word line; a bit line connected to a drain of the memory cell transistor; a sense amplifier which determines data in the memory cell transistor via the bit line; a first bit line clamp transistor connected in series between the bit line and the sense amplifier; a second bit line clamp transistor connected in parallel to the first bit line clamp transistor; and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor as a first charge operation of the bit line during a first period from a start of charge of the bit line, and turns off only the second bit line clamp transistor as a second charge operation of the bit line after the first period, a charging of the bit line in the first charge operation being quicker than a charging of the bit line in the second charge operation.