Patent ID: 7275196

Claim:
A circuit comprising: a plurality of input/output (I/O) terminals; a plurality of primary function blocks coupled with the I/O terminals, each of the primary function blocks adapted to implement a function, and having built-in self-test (BIST) circuitry adapted to determine whether the primary function block hosting the BIST circuitry is defective or not; at least one redundant function block coupled with the I/O terminals, and configurable to replace any defective one of at least a subset of the primary function blocks, and implement the function of the defective primary function block, in place of the defective primary function, the union of the subset of the primary function blocks that each redundant function block can replace being the whole set of primary function blocks; a rerouting coupler coupling the primary and redundant function blocks with the terminals, and configurable to reroute I/O and internal signals propagating from one function block to another to facilitate any replacement of a primary function block by a redundant function block; and a sequencer coupled to the primary and redundant function blocks, and adapted to determine one or more amount of time to run the BIST inside the function blocks, receive results of the BIST runs, determine at the end of the run(s) which primary function block, if any, is to be replaced by a redundant function block, including which redundant function block or blocks are to be used, and/or provide reconfiguration information to the rerouting coupler to reroute the I/O and internal signals to assist in effectuating the replacement of any defective one of the primary function blocks, if any, by the at least one redundant function block.