Patent ID: 7483429

Claim:
A method for network processor dataflow, comprising: providing a dataflow chip having a plurality of data transmission circuit structures and a plurality of scheduling circuit structures; the plurality of on-chip data transmission circuit structures comprising: a plurality of selectable frame processing circuit structures; and a plurality of selectable data transmission circuit structures; the plurality of scheduling circuit structures comprising: a full internal scheduling circuit structure; a calendar scheduling circuit structure in communication with an external scheduler chip; and an external calendar scheduling circuit structure; providing a plurality of dataflow and logic paths; providing a plurality of switches configured to select the dataflow and the logic paths; a first of the plurality of switches comprising an arbitration element; selecting the scheduling circuit structure responsive to positions of the plurality of switches; the first switch arbitration element dynamically arbitrating between an internal data packet received from an on-chip flow control handler and an external data packet received from the external scheduling chip; and selecting one of the plurality of data transmission circuit structures responsive to a data transmission selection indicator; or selecting one of the plurality of scheduling circuit structures responsive to a scheduling function selection indicator.