Patent ID: 6999371

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, a data input circuit receiving a data signal, inverting said data signal when the number of one of logic values is greater than the number of the other of logic values in said data signal, and writing inverted or non-inverted said data signal and a flag signal, indicating whether said data signal is inverted or non-inverted, of said data signal, into said memory cells, a data output circuit reading out inverted or non-inverted said data signal and said flag signal of said data signal from said memory cells, and re-inverting inverted or non-inverted said data signal when said flag signal indicates inversion, wherein each of said plurality of memory cells comprises a data storage unit storing data, and a readout port unit reading out data from said data storage unit, said readout port including a readout word line arranged in a row direction, a readout bit line arranged in a column direction, a first transistor having a source connected to a first power supply line, and a gate connected to said data storage unit, and a second transistor connected between said first transistor and said readout bit line, and having a gate connected to said readout word line.