Patent ID: 7653762

Claim:
A structure for tracing events in an electronic system, the structure comprising: a bus; a first random access memory (RAM); an application circuit; a processor coupled to the bus; a circuit arrangement coupled to the application circuit for receiving a plurality of event indication signals and further coupled to a write port of the first RAM, wherein the circuit arrangement is configured to write to the first RAM, in response to a change in state of any one of the event indication signals, event data indicative of the one of the event indication signals; wherein the circuit arrangement is further coupled to the bus for receiving a plurality of event indication signals from the processor, and for each event indication signal from the processor the circuit arrangement writes event data to the first RAM; wherein the event data for each event indication signal from both the application circuit and from the processor include an event type code and an associated cycle count value at which the event was detected, the event type codes being descriptive of circuit-generated events from the application circuit and software-controlled events from the processor; and a bus interface circuit coupled to the bus and to a read port of the first RAM, wherein responsive to a read transaction on the bus for the first RAM, the bus interface circuit reads data from the first RAM and outputs the data on the bus in a reply bus transaction.