Patent ID: 8422263

Claim:
A memory module comprising: a module substrate; a plurality of sets of data connectors provided on the module substrate; a plurality of sets of memory chips mounted over the module substrate, each of the sets of memory chips including at least two memory chips; a plurality of data register buffers mounted over the module substrate, each of the data register buffers being coupled to an associated one of the sets of data connectors and to an associated one of the sets of memory chips so that the each of the data register buffers receives write data from the associated one of sets of data connectors, outputs the write data to one of the at least two memory chips of the associated one of the sets of memory chips, receives read data from one of the at least two memory chips of the associated one of the sets of memory chips, and outputs the read data to the associated one of the sets of data connectors; a set of command/address/control connectors provided on the module substrate; and a command/address/control register buffer mounted over the module substrate independently of each of the data register buffers and including a register circuit unit that receives a plurality of first control signals from the command/address/control connectors and transfers the first control signals in common to the sets of memory chips and a control signal generating circuit that receives the first control signals from the command/address/control connectors to generate a second control signal and supplies the second control signal in common to the data register buffers, wherein the command/address/control register buffer further comprises a first clock generation circuit generating a first clock signal and supplying the first clock signal in common to the data register buffers, each of the data register buffers includes a second clock generation circuit receiving the first clock signal and generating a second clock signal, and each of the data register buffers outputs the write data in response to the second clock signal.