Patent ID: 8892841

Claim:
A processor comprising: a pipeline comprising one or more stages between a load/store unit and one or more target locations of one or more store memory operations; a scheduler configured to issue load/store memory operations for execution; address generation hardware coupled to the scheduler, the address generation hardware including an address generation unit and a translation lookaside buffer, and wherein the address generation hardware is configured to generate a physical address for each load/store operation issued by the scheduler; and the load/store unit coupled to the pipeline and to the address generation hardware, wherein the load/store unit comprises a load/store queue having an entry allocated to each pending load/store memory operation, wherein the load/store queue is configured to update an entry with a physical address generated by the address generation hardware responsive to issuance of a load/store operation, wherein the load/store queue is coupled to receive a snoop address indicating a cache block that is to be updated by another device in a system with the processor, and wherein, responsive to detecting that the snoop address hits a particular load memory operation in the load/store queue and identifying a subsequent store memory operation in the load/store queue that has been issued to the pipeline by the load/store unit, wherein the subsequent store memory operation is subsequent to the particular load memory operation in program order, and further identifying that the subsequent store memory operation is in the pipeline between the load/store unit and the one or more target locations at a time that the snoop address hitting the particular load memory operation is detected, the load/store unit is configured to signal the pipeline to prevent an update for the subsequent store memory operation at the target location of the subsequent store memory operation, wherein the subsequent store memory operation is in the pipeline to perform the update.