Patent ID: 6872987

Claim:
A semiconductor device electrostatic discharge protection structure on a substrate comprising: a first doped region of opposite dopent than said substrate extending down from the surface of said substrate; first and second isolation elements at the surface region lateral boundaries between said first doped region and said substrate; a heavily doped second region within said first doped region of similar dopent to said first doped region; a heavily doped third region within said first doped region of opposite doping than said first doped region; a heavily doped fourth region within said substrate of opposite doping than said substrate; a heavily doped fifth region within said substrate of similar dopent to said substrate; a third isolation element adjacent to said fifth doped region and on opposite side from said fourth doped region; a first gate element overlaying the surface region between said second and said third doped regions within said first doped region, and overlaying said surface region between said third doped region and said second isolation element; a second gate element overlying said surface region between said second isolation element and said forth doped region and said surface region between fourth and fifth doped regions within said substrate; a first electrical conduction element connecting said second and third doped regions and said first gate element and to a first voltage source; a second electrical conduction element connecting said fourth and fifth doped regions and said second gate element and to a second voltage source; a passivation layer overlaying said device surface.