Patent ID: 8649225

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells, and a plurality of word-lines connected to gates of the memory cells; and a control circuit configured to perform an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level, the memory cell array comprising: a semiconductor substrate; a first semiconductor layer extending in a direction perpendicular to the semiconductor substrate, and functioning as a body of a memory cell; a charge accumulation layer operative to accumulate charges; and a first conductive layer sandwiching the charge accumulation layer with the first semiconductor layer, and functioning as a gate of the memory cell and a word-line, the control circuit performing the first write operation to the plurality of memory cells, and when the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing a first function operation except for the erase operation and the first write operations, the control circuit performs the first function operation during the first write operations.