Patent ID: 6907098

Claim:
A Gray code counter comprising: a holding circuit storing a plurality of gray code signals received thereto and outputting the stored gray code signals in response to a clock signal; a first conversion circuit receiving the gray code signals from the holding circuit and converting the received gray code signals into a plurality of first binary code signals; an operation circuit for applying a logical operation to the first binary code signals so as to generate a plurality of second binary code signals, the operation circuit generating one of the second binary code signals from two adjacent bits of the first binary code signals; and a second conversion circuit receiving the second binary code signals and converting the received second binary code signals back into gray code signals, which are output the gray code signals to the holding circuit, wherein the holding circuit, the operation circuit, and the first and second conversion circuits comprise a least significant bit block, a most significant bit block, and a plurality of intermediate bit blocks, the intermediate bit blocks having the same circuit configuration.