Patent ID: 8072074

Claim:
A semiconductor device comprising: a semiconductor substrate having a first region including a memory cell and a second region including a logic circuit; a first insulating layer formed on said semiconductor substrate; first and second contact plugs including a first high-melting metal, and formed in said first insulating layer to be electrically connected to said semiconductor substrate, in said first region and whose upper surfaces are exposed from said first insulating layer; a third contact plug including said first high-melting metal, and formed in said first insulating layer to be electrically connected to said semiconductor substrate in said second region and whose upper surface is exposed from said first insulating layer; a second insulating layer formed over said first insulating layer; a capacitor having a electrode including a second high-melting metal, and formed in said second insulating layer to be electrically connected to said first contact plug; a fourth contact plug including said third high-melting metal, and formed in said second insulting layer to be electrically connected to said third contact plug; a third insulating layer formed over said second insulating layer; a first copper wiring having a first copper interconnection and a first barrier metal layer on a side surface and on a lower surface of said first copper interconnection, and formed in said third insulating layer in said first region; and a second copper wiring having a second copper interconnection and a second barrier metal layer on a side surface and on a lower surface of said second copper interconnection, and formed in said third insulating layer, to be electrically connected to said fourth contact plug.