Patent ID: 8584061

Claim:
A semiconductor device comprising: a first semiconductor chip that includes 1 st to n th driver circuits and an output switching circuit, n being a positive integer greater than 1; a second semiconductor chip that includes 1 st to n th receiver circuits and an input switching circuit; and 1 st to n+m th through silicon vias provided on at least one of the first and second semiconductor chips, m being a positive integer equal to 1 or greater than 1, wherein the output switching circuit selectively connects each of the 1 st to n th driver circuits to different ones of the 1 st to n+m th through silicon vias by connecting an i th driver circuit to one of i th to i+m th through silicon vias, where i is an integer among 1 to n, and the input switching circuit selectively connects each of the 1 st to n th receiver circuits to different ones of the 1 st to n+m th through silicon vias by connecting an i th receiver circuit to one of i th to i+m th through silicon vias, wherein the output switching circuit is connected between the 1 st to n th driver circuits and the 1 st to n+m th through silicon vias, and outputs a signal from a driver circuit of the 1 st to n th driver circuits to a through silicon via of the 1 st to n+m th through silicon vias, wherein the output switching circuit includes: 1 st to n th first control circuits each of which generates an associated one of 1 st to n th first selection signals based on at least an associated one of first relief signals; and 1 st to n th first switching circuits each of which receives an associated one of the 1 st to n th first selection signals to connect the i th driver circuit to one of i th and i+m th first signal paths, and wherein the first control circuits includes a j th first control circuit that generates a j th first selection signal based on an associated one of first relief signals and a j−1 th first selection signal, where j is an integer among 2 to n.