Patent ID: 7381616

Claim:
A method of fabricating a multi-level 3D memory array, comprising: a. preparing a wafer and peripheral circuits thereon; b. depositing, patterning and etching in a first direction, a first metal layer, a first memory resistor layer and a second metal layer on the wafer; c. depositing a barrier insulator layer and an oxide layer on and between the etched first metal layer, first memory resistor layer and second metal layer, and smoothing the oxide layer by CMP to the level of the second metal layer; d. patterning, and etching in a second direction substantially perpendicular to the first direction, the first and second metal layers and the first memory resistor layer to form first bit lines from the first metal layer and to form first word lines from the second metal layer; e. depositing a barrier insulator layer and an oxide layer on and between the etched first metal layer, first memory resistor layer and second metal layer, and smoothing the oxide layer by CMP to the level of the second metal layer; f. depositing a second memory resistor layer and a third metal layer; g. patterning and etching in the second direction the third metal layer and the second memory resistor layer; h. depositing a barrier insulator layer and an oxide layer on and between the etched third metal layer and second memory resistor layer, and smoothing the oxide layer by CMP to the level of the third metal layer; i. patterning and etching in the first direction the third metal layer and the first memory resistor layer to form second bit lines from the third metal layer; j. depositing a barrier insulator layer and an oxide layer on and between the etched third metal layer and second memory resistor layer, and smoothing the oxide layer by CMP to the level of the third metal layer; k. depositing a layer of oxide; and j. repeating steps b through k for N levels of memory array.