Patent ID: 7472257

Claim:
A parallel processor for executing code for that has been compiled to achieve code compaction, the code comprising a plurality of successive instruction bundles each comprising a plurality of instructions, one instruction for each of a corresponding plurality of execution units, the instructions including a do nothing instruction pertaining to a first duration in which a single instruction is executed and in response to which an execution unit performs no operation, the parallel processor comprising: a memory; an instruction dispatch stage comprising a plurality of dispatch units, the instruction dispatch stage being configured to detect in a first instruction bundle a dedicated instruction for a particular execution unit; circuitry for flexibly routing different instructions of an instruction bundle from the memory to different ones of the dispatch units; an instruction execution stage comprising a plurality of execution units, coupled to and following the instruction dispatch stage; the instruction dispatch stage being configured to, in response to the dedicated instruction: reduce power to or turn off the particular execution unit for a variable duration in which multiple instructions would otherwise have been executed by the particular execution unit; and cause the circuitry to reroute instructions in a next successive instruction bundle following the first instruction bundle such that an instruction that logically corresponds to the particular execution unit is rerouted to a different execution unit.