Patent ID: 6993447

Claim:
A system large scale integration (LSI), comprising: first, second and third circuit blocks, each circuit block being located on a wafer; a first power supply terminal located on the wafer and supplied with a first power supply voltage for test, wherein the first power supply voltage has a first voltage level and has a second voltage level which is different from the first voltage level; a first power supply line located on the wafer, which surrounds the first, second and third circuit blocks, and which is connected to the first power supply terminal and the first and second circuit blocks; a second power supply terminal located on the wafer and supplied with a second power supply voltage for test, wherein the second power supply voltage has the first voltage level and has a third voltage level which is different from the first and second voltage levels; and a second power supply line located on the wafer, which surrounds the first, second and third circuit blocks, and which is connected to the second power supply terminal and the third circuit block.