Patent ID: 7015110

Claim:
A method for manufacturing integrated circuit devices including capacitor structures, the method comprising: providing a substrate, including an overlying thickness of first dielectric material; forming a plurality of openings within the thickness of the first dielectric material, each of the openings including a width and a height; forming a barrier layer overlying an exposed surface of each of the plurality of openings; filling each of the openings with a metal layer, the metal layer occupying substantially an entire region of each of the openings to form a plurality of metal structures, each of the metal structures having a width and height; planarizing a surface of the metal layer; patterning a region to expose each of the metal structures to expose the barrier layer overlying each of the metal structures, thereby forming an array; forming a capacitor insulating layer overlying the array; and forming a second metal layer overlying the capacitor insulating layer, whereupon each of the metal layer structures, overlying capacitor insulating layer, and second metal layer form a capacitor structure; and planarizing the second metal layer.