Patent ID: 8542521

Claim:
A semiconductor storage device comprising: first memory cells capable of holding 2-level or higher-level data; first bit lines and first word lines capable of selecting the first memory cells and, formed in places where the first memory cells are provided by being crossed; and first sense amps detecting a first current flowing to the first bit line in accordance with the data held by the first memory cell, wherein the first sense amp includes a first supply unit supplying a second current to the first bit line to compensate for the falling first current flowing to the first bit line when the data is read; a first accumulation unit accumulating an amount of charge in accordance with a potential of the first bit line; a detector detecting the potential in accordance with the amount of charge of the first accumulation unit; and a counter counting output from the detector; the counter includes a second supply unit charging a first node in accordance with the second current supplied to the first bit line; a second accumulation unit accumulating a charge in accordance with the potential of the first node; and a sensing unit detecting the amount of charge of the second accumulation unit to detect the data held by the first memory cell based on the amount of the charge.