Patent ID: 8307241

Claim:
A method of managing data transfer from a host to a nonvolatile memory array that stores more than one bit per cell, comprising: receiving lower-page data and upper-page data from a host; buffering the lower-page data and the upper-page data in a memory controller volatile memory; reading the lower-page data from the memory controller volatile memory; storing a safe copy of the lower-page data in a first page buffer of an on-chip cache of a nonvolatile memory array coupled to the memory controller, the volatile memory being distinct from the on-chip cache; storing a target copy of the lower-page data into a second page buffer of the on-chip cache; reading the upper-page data from the memory controller volatile memory; storing a safe copy of the upper-page data in a third page buffer of the on-chip cache; storing a target copy of the upper-page data in a fourth page buffer of the on-chip cache; and while the safe copy of the lower-page data is still stored in the first page buffer and while the safe copy of the upper-page data is still stored in the third page buffer: writing the upper-page data from the fourth page buffer to the non-volatile memory array; and when a write failure occurs during the writing of the upper-page data from the fourth page buffer to the non-volatile memory array then recovering the upper-page data from the third page buffer and writing the recovered upper-page data to the nonvolatile memory array.