Patent ID: 7682903

Claim:
A method of forming a power device, comprising: providing a substrate, a semiconductor layer disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material, the semiconductor layer having a trench, the conductive material being disposed in the trench, the substrate defining a cell region and a plug-contacting region, wherein the trench of the semiconductor layer extends from the cell region into the plug-contacting region, and a top surface of the conductive material is disposed in a predetermined depth of the trench; performing an ion implantation process to form a body layer in the semiconductor layer; performing at least a tilted ion implantation process to form at least a heavy doped region, which contacts a sidewall of the trench and is disposed in the semiconductor layer; forming a first dielectric layer overall on the substrate to fill the trench; performing a chemical mechanical polishing (CMP) process, until exposing the body layer disposed under the heavy doped region, so as to turn the heavy doped region, which contacts the sidewall of the trench, into a plurality of source regions; forming a patterned dielectric layer in the plug-contacting region; forming at least a contact plug, which penetrates through the patterned dielectric layer and the first dielectric layer, and is electrically connected to the conductive material in the trench; and forming at least a gate trace and at least a source trace, wherein the gate trace covers the contact plug, and the source trace covers the source regions disposed in the cell region.