Patent ID: 7555089

Claim:
A method of establishing and adjusting the relative phase between a clock signal transition and a data signal transition, the method comprising: creating multiple clock signals having the same frequency, wherein each clock signal has a different relative phase; establishing a series of timing bins according to the clock signals; dividing the series of timing bins into valid timing bins and invalid timing bins; receiving a data signal having a data transition from a link interface, wherein the data signal has a data phase; and determining whether the data transition occurred during a valid timing bin or an invalid timing bin, wherein when it is determined that the data transition occurred during an invalid timing bin, initiating a retraining process comprising: generating a series of test signals at the link interface, wherein each test signal has a transition, and wherein each test signal has different phase; receiving each test signal at a destination; determining whether each test signal has a transition during a valid timing bin or an invalid timing bin; classifying each test signal as a valid test signal only when the test signal transitions during a valid timing bin; and instructing the link interface to set the data phase to the phase of a valid test signal.