Patent ID: 8217950

Claim:
A processing unit, comprising: a first plurality of graphics processing units (GPUs), wherein each GPU within the first plurality is configured to output at least a portion of a first frame of graphics data; a first plurality of interlink modules, wherein each interlink module of the first plurality of interlink modules is coupled to a respective GPU of the first plurality of GPUs: a second plurality of GPUs, wherein each GPU within the second plurality is configured to output at least a portion of a second frame of graphics data; and a second plurality of interlink modules, wherein each interlink module of the second plurality of interlink modules is coupled to a respective GPU of the second plurality of GPUs, wherein at least one interlink module of the first plurality of interlink modules is configured to selectively pass its corresponding portion of the first frame of graphics data to another interlink module of the first plurality of interlink modules and further configured to selectively receive the second frame of graphics data from the second plurality of interlink modules, merge the second frame of graphics data with its corresponding portion of the first frame of graphics data, and pass the merged graphics data.