Patent ID: 8173507

Claim:
A method of forming integrated circuitry, comprising: forming a charge storage transistor gate stack over semiconductive material; the stack comprising a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric; etching the stack at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material, individual of the gate lines comprising laterally projecting feet comprising the high-k dielectric; after etching the stack to form the gate lines, implanting ions into an implant region comprising the high-k dielectric of the laterally projecting feet, the ions being chemically inert to the high-k dielectric; and etching the ion implanted high-k dielectric of the projecting feet selectively relative to portions of the high-k dielectric outside of the implant region.