Patent ID: 7737490

Claim:
A vertical and trench type insulated gate MOS semiconductor device comprising: a first conductivity type semiconductor substrate; a second conductivity type channel region selectively formed on a first principal surface of the semiconductor substrate; a first conductivity type emitter region selectively formed on a surface of the second conductivity type channel region; trenches, each having a depth that extends through the second conductivity type channel region and into the semiconductor substrate, arranged in parallel in a parallel stripe surface pattern; a polysilicon gate electrode buried in each of the trenches with a gate insulator film interposed between the gate electrode and a sidewall of each of the trenches; an emitter electrode contacting both a surface of the first conductivity type emitter region and the surface of the second conductivity type channel region in a contact region, the contact region being between the trenches as a region including surfaces of both a portion of the first conductivity type emitter region and a portion of the second conductivity type channel region; a collector layer formed on a second principal surface of the first conductivity type semiconductor substrate; and a collector electrode making contact with a surface of the collector layer, wherein surfaces of the second conductivity type channel regions and surfaces of portions of the first conductivity type semiconductor substrate alternate in the longitudinal direction of the trenches between the trenches arranged in parallel, and wherein the first conductivity type emitter region selectively formed on the surface of the second conductivity type channel region has a surface shape that is wider at the side of each trench than it is at the center between the trenches.