Patent ID: 7525854

Claim:
An output circuit of a memory, wherein the output circuit is biased between a voltage source of a logic high level and a ground, the output circuit is connected between a plurality of readout bit lines and an output terminal, and each of the readout bit lines is connected to at least one memory cell, the output circuit comprising: first pre-charge circuit, connected to a target readout bit lines of a target memory cell, pre-charging the voltage of the target readout bit line to logic high level according to a pre-charge signal before reading data from the target memory cell; a multiplexer, connected to the first pre-charge circuit, selecting the target readout bit line from the plurality of the readout bit lines according to a selecting signal, and comprising at least one input selection transistor having a gate coupled to the selecting signal and a drain connected to a first input node; and a sense amplifier, connected to the multiplexer, detecting the voltage of the target readout bit line while the target memory cell is selected, and comparing the voltage of the target readout bit line with the logic high level to generate an output signal to a first output node and an inverse output signal to a second output node; wherein the sense amplifier comprises: a first differential input transistor, having a drain connected to the corresponding input selection transistor, a gate connected to one of the readout bit lines, and a source connected to a second input node; and a second differential input transistor, having a gate connected to a voltage source with the logic high level, and a source connected to the second input node.