Patent ID: 7535294

Claim:
An offset cancellation amplifier comprising: a differential stage that includes first and second differential pairs and a load circuit connected in common to output pairs of said first and second differential pairs; an amplifier stage that receives a common output signal of said first and second differential pairs and outputs an amplified signal to an output terminal of said offset cancellation amplifier; first and second capacitors; and a switch circuit that receives control signals and performs switching control of the connection of signals supplied to an input pair of said first differential pair and to an input pair of said second differential pair; wherein a data output period includes first to third periods in this order; said first capacitor being connected for all time during said data output period to one input of said input pair of said first differential pair; during said first period, the voltage at said output terminal is supplied to said one input of said input pair of said first differential pair; a reference voltage is supplied to the other input of said input pair of said first differential pair; the voltage at an input terminal of said offset cancellation amplifier is supplied in common to said input pair of said second differential pair; and the voltage at said output terminal is accumulated in common in said first and second capacitors with said second capacitor being disconnected from the other input of said input pair of said first differential pair; during said second period, the voltage at said output terminal is supplied to the one input of said input pair of said first differential pair; said reference voltage is supplied to the other input of said input pair of said first differential pair; the voltage at said input terminal is supplied in common to said input pair of said second differential pair; the voltage at said output terminal is accumulated in said first capacitor; and said second capacitor is disconnected from the voltage at said output terminal, connected to the other input of said input pair of said first differential pair and has said reference voltage accumulated therein; and wherein, during said third period, said input pair of said first differential pair is disconnected from the voltage at said output terminal and from said reference voltage; the voltage accumulated in said first capacitor is supplied to the one input of said input pair of said first differential pair; the voltage accumulated in said second capacitor is supplied to the other input of said input pair of said first differential pair; the voltage at said output terminal is supplied to the one input of said input pair of said second differential pair; and the voltage at said input terminal is supplied to the other input of said input pair of said second differential pair.