Patent ID: 7197731

Claim:
A computer readable medium encoded with a computer program for causing a computer to execute a verification of a virtual component for an integrated circuit design described by a hardware description language, the verification comprising: simulating a virtual component unit described by the hardware description language, said virtual component unit comprising a virtual component body having at least one circuit function and a verification-supporting circuit detachably connected to said virtual component body so as not to affect the circuit function of said virtual component body even when a connection thereof to said virtual component body is cut; analyzing, by said verification-supporting circuit, abnormality of said circuit function based on a signal indicating an operation state of said circuit function; outputting a result of analyzing said abnormality of said circuit function through a verification-output terminal of said verification-supporting circuit generating an operation clock and an emulation signal to simulate said virtual component body to operate alone; and supplying said operation clock and said emulation signal to said virtual component body when the simulating of said virtual component unit is performed.