Patent ID: 7759166

Claim:
A method of making microelectronic packages comprising: making a subassembly including providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, said plate including ledges extending into each said opening so that each said opening has a larger diameter adjacent the top surface of said plate and a smaller diameter adjacent the bottom surface of said plate, attaching a compliant layer to the top surface of said plate, said compliant layer having openings that are aligned with the openings extending through said plate, providing electrically conductive features on said compliant layer, wherein at least some of said electrically conductive features extend onto said ledges; after making said subassembly, providing a semiconductor wafer having a top surface and contacts accessible at the top surface; attaching the bottom surface of said plate with the top surface of said semiconductor wafer so that the openings extending through said plate are aligned with the contacts on said wafer; electrically interconnecting the contacts on said semiconductor wafer with said electrically conductive features.