Patent ID: 7795731

Claim:
A semiconductor device comprising: a semiconductor substrate having a cell array region; an interlayer insulating layer covering the substrate having the cell array region; lower metal interconnections disposed on the interlayer insulating layer in the cell array region, each of the lower metal interconnections having a first width; a lower inter-metal insulating layer formed over the lower metal interconnections; a topmost metal layer having a plate shape and disposed on a top surface of the lower inter-metal insulating layer to cover most of the cell array region, the topmost metal layer having at least one opening that penetrates a portion of the topmost metal layer and being surrounded by the topmost metal layer, wherein the opening has vertically flat sidewalls, the at least one opening disposed over the cell array region and over at least a portion of the lower inter-metal insulating layer between the lower metal interconnections, the at least one opening having a second width that is greater than the first width, wherein the at least one opening is formed on a higher position than a surface of the inter-metal insulator layer, and wherein the at least one opening is electrically isolated from the lower metal interconnections, wherein the opening exposes a portion of surface of the lower inter-metal insulating layer.