Patent ID: 7639546

Claim:
A nonvolatile semiconductor memory device, comprising: a latch circuit having two nodes and configured to latch data that is represented by respective signal levels of the two nodes complementary to each other; a nonvolatile memory cell including two MIS transistors; a bit swapping unit coupled between the latch circuit and the nonvolatile memory cell and configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode; and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell.