Patent ID: 8607029

Claim:
A dynamic reconfigurable circuit comprising: a plurality of processing elements each provided with an arithmetic data input port, a configuration data input port and an output port; a data network that is coupled to each of the arithmetic data input ports and each of the output ports of the plurality of processing elements; a configuration memory that is coupled via a configuration path to the configuration data input port of a first processor element being at least one of the plurality of processing elements; and an immediate value network that is independent from the data network and that is directly coupled to the configuration data input port of a second processor element being at least one of the plurality of processing elements, wherein an internal register of a third processor element being at least one of the plurality of processing elements is coupled to the immediate value network so that data stored in the internal register can be outputted to the immediate value network, and wherein a path to transfer data from the configuration memory to the second processor element via the immediate value network is independent from a path to transfer input data from an outside of the data network to the second processor element via the data network.