Patent ID: 7200042

Claim:
A method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path is compared with a reference current flowing via at least one read-out path simulation, the read-out path having a memory cell with a memory transistor, and the read-out path simulation having a reference memory cell simulating the memory cell with a reference memory transistor corresponding to the memory transistor, the method comprising: a) causing the reference memory transistor to a normally on state provided that the reference memory transistor is not already in the normally on state; b) providing a predetermined reference current to the at least one read-out path simulation; c) generating, with the aid of the predetermined reference current, a reference voltage that is dependent on the channel resistance of the reference memory transistor, wherein when the reference memory transistor is in a triode operation, the reference voltage is substantially proportional to the channel resistance, and wherein when the reference memory transistor is in a saturated operation, the reference voltage rises with the channel resistance according to a root function; d) providing the reference voltage to a gate of the memory transistor and a gate of the reference memory transistor; and e) comparing the read current flowing through the memory transistor with the predetermined reference current flowing through the reference memory transistor.