Patent ID: 8908416

Claim:
A semiconductor memory device, comprising: a memory cell array including memory cells that are disposed at intersections of first lines and second lines, and the memory cells having a variable resistance element; and a control circuit, the control circuit being configured to, when performing a setting operation or resetting operation to a selected memory cell selected from among the memory cells, apply a first voltage to a selected first line connected to the selected memory cell, apply a second voltage to a selected second line connected to the selected memory cell, apply a third voltage to a non-selected first line other than the selected first line, and apply a fourth voltage which is larger than the third voltage to a non-selected second line other than the selected second line, a first absolute value of a difference between the third voltage and the fourth voltage being set smaller than a second absolute value of a difference between the first voltage and the second voltage by an offset voltage, and the control circuit being configured to increase the offset voltage as the second absolute value increases.