Patent ID: 7401309

Claim:
An integrated circuit hierarchical design system which executes verification of propagation delays in an integrated circuit which is formed of a plurality of layer blocks, comprising: a unit which shifts a boundary of said layer blocks so that each circuit through which a signal path passes is included in one layer block, wherein the signal path is a signal path that passes through each circuit in said plurality of layers and connects between two flip-flops, a unit which executes verification of propagation delays of each of said circuit in said one layer block; and a unit which, when a flip-flop, on the side of a direction opposite to a signal propagation direction, included in a lower layer is connected to another flip-flop through a plurality of circuits other than the circuit located between said flip-flops, to include both said plurality of circuits and said flip-flops in said lower layer and include a circuit which is branched from an output of any one of said plurality of circuits and connected in a higher layer, inserts a multiplexing circuit as a copy of said one circuit between said flip-flops in between said one circuit and said branched and connected circuit, as well as shifts in the position of said boundary of said layer blocks to an input of said multiplexing circuit and changes the position of said branch to an input of said one circuit.