Patent ID: 7979601

Claim:
An embedded controller, comprising: a processor; a memory medium coupled to the processor; and an interface coupled to the memory medium, wherein the interface is configured to: couple to a host; receive a direct memory access (DMA) request from the host, wherein the DMA request comprises a request to read data from a memory location in the memory medium or a request to write data to a memory location in the memory medium, and wherein the DMA request comprises a relative memory address; translate the relative memory address into a first address of the memory medium; perform operations according to the DMA request using the first address of the memory medium; receive a second DMA request from the host, wherein the second DMA request does not comprise a relative memory address; automatically increment the first address of the memory medium or automatically increment the relative memory address, wherein said automatically incrementing is performed in response to receiving the second DMA request perform operations according to the second DMA request using the automatically determined address of the memory medium; wherein the processor is configured to operate according to data stored in the memory medium.