Patent ID: 8856601

Claim:
An integrated circuit comprising: at least one integrated circuit input terminal; at least one integrated circuit output terminal; a plurality of scan chain circuits, each scan chain circuit including an input multiplexer having a first input receiving a constant digital signal, a second input connected to said at least one integrated circuit input terminal, an output and a control input receiving a corresponding control signal, said input multiplexer connecting said first input or said second input to said output dependent upon said control signal received at said control input; a serial scan chain of a plurality of bits having an input connected to said output of said input multiplexer and an output, each serial scan chain operable in a test mode to serially connect corresponding bits of an operational circuit of said integrated circuit; a bypass flip-flop of one bit having an input connected to said at least one integrated circuit input terminal and an output; an output multiplexer having a first input connected to said output of said bypass flip-flop, a second input connected to said output of said serial scan chain, an output connected to said at least one integrated circuit output terminal and a control input receiving said corresponding control signal, said output multiplexer connecting said first input or said second input to said output dependent upon said control signal received at said control input.