Patent ID: 6933578

Claim:
A semiconductor storage device, comprising: a first driver transistor having a gate and a drain; a second driver transistor including: a drain coupled to the gate of the first driver transistor; and a gate coupled to the drain of the first driver transistor; a first load transistor coupled to the first driver transistor in series, a gate of the first load transistor being coupled to the gate of the first driver transistor; a second load transistor coupled to the second driver transistor in series, a gate of the second load transistor being coupled to the gate of the second driver transistor; a first transfer gate including: a source coupled to the drain of the first driver transistor; a drain coupled to a first bit line; and a gate coupled to a word line; a second transfer gate including: a source coupled to the drain of the second driver transistor; a drain coupled to a second bit line; and a gate coupled to the word line; a reading-out transistor coupled to the second load transistor in series, a gate of the reading-out transistor being coupled to the gate of the second load transistor; a first gate contact region disposed between the first driver transistor and the first load transistor, and for establishing contact with the gates of the first driver transistor and the first load transistor; a second gate contact region disposed on a side of the reading-out transistor, and for establishing contact with the gates of the second driver transistor, the second load transistor, and the reading-out transistor; and a dummy gate contact region disposed between the second driver transistor and the second load transistor, and provided corresponding to the first gate contact region.