Patent ID: 8797332

Claim:
A system, comprising: a computer memory having a physical storage size and logical arrangement; a component resource affinity table disposed in the computer memory; a central processing unit (CPU) coupled to the computer memory; the CPU having a number of discoverable properties, the CPU configured, responsive to executing one or more instructions, to provide at least a portion of the discoverable properties of the CPU, an accelerated processing device, and the memory; the accelerated processing device (APD) coupled to the computer memory, the APD having a number of discoverable properties, and coupled to an APD local memory; and a memory management unit coupled to the computer memory and shared by the CPU and the accelerated processing device; wherein the system is configured to execute an operating system; wherein the discoverable properties are relevant to scheduling and distribution of computational tasks to the CPU and the APD, and expose coherent and non-coherent access ranges of either the computer memory or the APD local memory that the operating system manages differently.