Patent ID: 7514993

Claim:
An apparatus for simultaneously demodulating an input signal frequency into in-phase (I) components and quadrature-phase (Q) components, the apparatus comprising: a) an input signal frequency split into an in-phase (I) component path and a quadrature (Q) component path; b) wherein the in-phase component path comprises an I sampler receiving input from the input signal frequency and an I sample clock, and wherein the I sampler sends a resulting signal to a discrete time processing infinite impulse response/finite impulse response (DTP IIR/FIR) decimator and the DTP IIR/FIR decimator receives further input from an I DTP clock and wherein the resulting output of the DTP IIR/FIR decimator comprises an in-phase component of a resulting signal; c) wherein the quadrature component path comprises a Q sampler receiving input from the input signal frequency and a Q sample clock, and wherein the Q sampler sends a resulting signal to a DTP IIR/FIR decimator and the DTP IIR/FIR decimator receives further input from a Q DTP clock and wherein the resulting output of the DTP IIR/FIR decimator comprises a quadrature component of a resulting signal; and d) wherein a clock generator comprises two identical discrete-time networks, with one network providing input to the in-phase component path by controlling the I sample clock and the I DTP clock and wherein the other network provides input to the quadrature component path by controlling the Q sample clock and the Q DTP clock.