Patent ID: 8675439

Claim:
A digital memory, comprising: an array of bit cells coupled to word lines and bit lines, wherein a word line signal at a selected one of the word lines selects a plurality of bit cells that comprise an addressable word in the array, and bit line signals control reading and writing at bit positions along the addressable words selected by the word lines; wherein the bit cells comprise inverters that are cross coupled between complementary nodes, and at least one passing gate transistor, the passing gate transistor having a gate coupled to the word line signal at the selected one of the word lines, controlling a channel between one of the bit lines and one of the nodes, whereby the passing gate transistors isolate the nodes from the bit lines until an associated one of the word lines is asserted to couple the bit lines of the addressable word to the nodes of the inverters of the addressable word, through the channel of the passing gate transistors; wherein at least one subset of the bit cells in the array is switchable between a sleep mode and a standby mode via a control signal, the bit cells in the subset being accessible for one of read and write operations when in the standby mode; a bit line bias circuit operational in the sleep mode, comprising a pull-up transistor for the bit lines in the subset, coupled between the bit lines and a supply voltage, and rendered conductive by the control signal, wherein the pull-up transistor for each of a complementary pair of bit lines has a channel coupled to a supply voltage and a gate coupled to the other of the complementary pair of bit lines.