Patent ID: 8195923

Claim:
A processor comprising: an instruction fetch unit configured to fetch instructions of a computer program; a decoder coupled to receive instructions fetched by the fetch unit; an execution unit coupled to the decoder; and a features register, wherein said features register provides one or more indications of hardware supported features of the processor; a usage register associated with a thread of execution, wherein said usage register provides one or more indications of particular features requested by the computer program; wherein the decoder is configured to: detect a received instruction comprises an opcode corresponding to a plurality of different functions; and access the usage register to determine the computer program expects a particular one of the plurality of functions to be performed when the opcode is executed; access the features register to determine whether there is hardware support for the particular one of the plurality of functions; wherein in response to determining the features register indicates that hardware support exists to perform said particular one of the plurality of functions responsive to execution of the opcode, the execution unit is configured to execute the received instruction in order to perform said particular one of the plurality of functions.