Patent ID: 8924803

Claim:
A boundary scan test interface circuit, applied for a dynamic random access memory (DRAM), comprising: N test input pads, wherein N is positive integer; a test interfacing module, coupled to the test input pads, the test interfacing module having a plurality of logical gates, and each of input pins of each of the logical gates coupled to each of the test input pads; M test output pads, coupled to output pins of the logical gates in the test interfacing module, wherein M is positive integer, and M is smaller than N; a function block module, having a plurality of function output pins and a plurality of function input pins; a selector, coupled between the function input pins, the test input pads and the input pins of the logical gates of the test interfacing module, the selector selecting each of the function input pins or each of the input pins of the logical gates to connect to each of the test input pads according to a mode selecting signal; and a mode selecting circuit, coupled to the selector, the mode selecting circuit providing the mode selecting signal to the selector, wherein the test interfacing module is configured to test opens or shorts on each of the test input and output pads.