Patent ID: 7486525

Claim:
A temporary chip attach carrier for an integrated circuit chip, comprising: a carrier substrate, a first array of interconnects disposed on a bottom surface of said carrier substrate and a second array of interconnects disposed on a top surface of said carrier substrate, corresponding interconnects of said first and second arrays of interconnects electrically connected by wires in said carrier substrate; an interposer, said interposer comprising an electrically conductive interposer substrate, a first array of pads disposed on a top surface of said interposer and a second array of pads disposed on a bottom surface of said interposer substrate, corresponding pads of said first and second arrays of pads electrically connected by electrically conductive through vias passing through said interposer substrate, said through vias including an electrically conductive material and isolation electrically isolating said electrically conductive material from said interposer substrate, and pads of said second array of pads in direct physical and electrical contact with corresponding interconnects of said second array of interconnects; and wherein said interposer substrate comprises, except for said through vias, a continuous block of a same material as a substrate of said integrated circuit chip; wherein said first array of pads comprise probe pads, each probe pad having a probe tip surrounded by a depression formed in said probe pad, said depression lower than a perimeter region of the probe pad; wherein probe tips of pads of said first array of pads penetrate past surfaces of corresponding solder bumps into said solder bumps forming an electrically conductive mechanical contact.