Patent ID: 8148778

Claim:
A semiconductor device comprising: a semiconductor substrate; a first well diffusion layer of a first conductivity type formed in an upper portion of the semiconductor substrate; a second well diffusion layer of the first conductivity type formed in an upper portion of the first well diffusion layer; a source diffusion layer of a second conductivity type formed in an upper portion of the second well diffusion layer; a third well diffusion layer of the second conductivity type formed in an upper portion of the semiconductor substrate to be positioned away from the second well diffusion layer; a drain diffusion layer of the second conductivity type formed in an upper portion of the third well diffusion layer; a gate insulating film formed on the second well diffusion layer, the first well diffusion layer, and the third well diffusion layer; a gate electrode formed on the gate insulating film; a device isolation insulating film formed on the third well diffusion layer and between the gate insulating film and the drain diffusion layer to be connected to the gate insulating film; and a buffer layer of the second conductivity type formed between the first well diffusion layer and the third diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer, the buffer layer of the second conductivity type having an impurity concentration lower than an impurity concentration in the third well diffusion layer.