Patent ID: 7618854

Claim:
A method of manufacturing a semiconductor device, comprising: forming a buffer N-well and an N-well of a P-type transistor on a semiconductor substrate on which a semiconductor layer is formed, and of which a surface is divided into a lateral double-diffused metal oxidation of silicon (LDMOS) region for an LDMOS transistor, a PMOS region for the P-type transistor and an NMOS region for an N-type transistor, by partially implanting N-type impurities through a surface of the LDMOS region and the PMOS region at a second concentration, so that the buffer N-well is formed on a first portion of the LDMOS region and the N-well of the P-type transistor is formed on the PMOS region; forming a P-well of an N-type transistor on the NMOS region by partially implanting P-type impurities through a surface of the NMOS region; forming first, second and third gate structures on the substrate of the LDMOS region spaced apart from the buffer N-well, on the substrate of the NMOS region and on the substrate of the PMOS region, respectively; forming a lightly doped drain (LDD) between the first gate structure and the buffer N-well and a lightly doped N-type area a sides of the second gate structure by implanting N-type impurities through a surface of the LDMOS region between the first gate structure and the buffer N-well and through a surface of the NMOS region at a third concentration lower than the second concentration, respectively; forming a source and a drain of the LDMOS transistor at surface portions of the LDMOS region, and a source and a drain of the N-type transistor at surface portions of the NMOS region by partially implanting N-type impurities into the LDMOS and NMOS regions of the substrate at a first concentration higher than the second concentration, the source of the LDMOS transistor being formed adjacent to the first gate structure on a second portion of the LDMOS region opposite to the first portion of the LDMOS region with respect to the first structure, the drain of the LDMOS transistor being formed on a substrate corresponding to the buffer N-well, and the source and drain of the NMOS transistor being formed adjacent to the second gate structure and opposite to each other with respect to the second gate structure; and forming a source and a drain of the P-type transistor at surface portions of the PMOS region by partially implanting P-type impurities into the PMOS region of the substrate adjacent to the third gate structure and opposite to each other with respect to the third gate structure.