Patent ID: 8824193

Claim:
A semiconductor storage device comprising: a wiring; a first storage circuit comprising a first transistor, a first capacitor, a first data holding portion, a first circuit, and a first control circuit; a second storage circuit comprising a second transistor, a second capacitor, a second data holding portion, a second circuit, and a second control circuit; and a third transistor, wherein the first storage circuit and the second storage circuit are adjacent to each other, wherein one of a source and a drain of the first transistor is electrically connected to the wiring, wherein the first data holding portion is configured to hold data supplied from the wiring when the first transistor and the second transistor are in an Off-state, wherein the first data holding portion is electrically connected to the other of the source and the drain of the first transistor, a first electrode of the first capacitor, an input terminal of the first circuit, and one of a source and a drain of the second transistor, wherein the first circuit is configured to output a first signal to the first control circuit and a data output portion, a potential of the first signal depending on a potential of the data in the first data holding portion, wherein the first control circuit is configured to output a second signal to a second electrode of the first capacitor so that the potential of the data in the first data holding portion is controlled by the second signal, wherein the second data holding portion is electrically connected to the other of the source and the drain of the second transistor, a first electrode of the second capacitor, an input terminal of the second circuit, and the third transistor, and wherein the second data holding portion is configured to hold the data supplied from the first data holding portion when the second transistor and the third transistor are in an Off-state.