Patent ID: 8193087

Claim:
A method of forming an integrated circuit, the method comprising: providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; forming a diffusion barrier layer in the opening covering the low-k dielectric layer in the opening; filling a copper line over the diffusion barrier layer; removing the diffusion barrier layer from the top surface of the low-k dielectric layer; recessing a top surface of the copper line after the removing the diffusion barrier layer from the top surface of the low-k dielectric layer, the recessing being performed at least in part by removing a portion of a copper oxide layer from the top surface of the copper line, the recessing forming a recess; reducing, after the recessing, remaining portions of the copper oxide layer on the top surface of the copper line to copper; and forming a metal cap on the copper line within the recess using a selective deposition method, wherein the metal cap is only formed within a region directly over the copper line, and wherein the metal cap has a top surface higher or lower than a top edge of the diffusion barrier layer.