Patent ID: 7376795

Claim:
A method for providing memory coherence across a plurality of processors, said method comprising: modifying, by a first processor, a first memory area associated with the first processor; sending, by the first processor, an invalidate signal on a bus in response to the modifying; receiving, by a second processor, the invalidate signal; in response to receiving the invalidate signal: reading, by the second processor, a frequency access count corresponding to a second memory area, the second memory area associated with the second processor and coherent with the first memory area, wherein the frequency access count corresponding to the second memory area is a number of times the second memory area has been accessed; determining, based upon the frequency access count, if the second processor frequently accesses the second memory area; and in response to determining that the second processor frequently accesses the second memory area, sending, by the second processor, an update request on the bus; receiving, by the first processor, the update request from the second processor; and in response to receiving the update request, sending, by the first processor, data stored in the first memory area on the bus.