Patent ID: 7429762

Claim:
A semiconductor device comprising: a semiconductor substrate; first and second CMOS inverter circuits formed on the semiconductor substrate and constituting an SRAM memory cell, each inverter circuit having input and output terminals; and first and second resistance elements formed in the semiconductor substrate and having respective one ends connected to a gate electrode pattern serving as input terminals of the first and second CMOS inverter circuits and the respective other ends connected to electrodes serving as output terminals of the first and second CMOS inverter circuits, wherein the gate electrode pattern includes an underside on which a gate insulation film is formed, the gate insulation film being located between the semiconductor substrate and the gate electrode pattern and having an opening, and the first and second resistance elements include respective portions adjacent to the gate electrode pattern, at which portions the first and second resistance elements are electrically connected via the opening to the gate electrode pattern located over the opening.