Patent ID: 7509559

Claim:
An apparatus comprising: an input error checker in a direct memory access controller (DMA) of a computing device to receive a corrupted error protected unit (EPU) and an adjacent uncorrupted EPU from memory of the computing device, wherein each of the corrupted EPU and the adjacent uncorrupted EPU is associated with a respective error correct code (ECC) and comprises a plurality of data units; a data shifter in the DMA, the data shifter coupled to the input error checker to receive the corrupted EPU and the adjacent uncorrupted EPU, the data shifter to shift the corrupted EPU and the adjacent uncorrupted EPU by a fractional portion of an EPU in the direction of the adjacent uncorrupted EPU to generate two shifted EPUs; and an output error checker in the DMA, the output error checker coupled to the data shifter to receive the two shifted EPUs and mark all of the data units in the two shifted EPUs as corrupted.