Patent ID: 8258007

Claim:
A package process, comprising:providing a circuit substrate, the circuit substrate having a top surface; bonding a plurality of first chips onto the top surface of the circuit substrate, wherein a bottom surface of each of the first chips faces the circuit substrate, each of the first chips has a plurality of first bumps on the bottom surface of the first chip and a plurality of conductive vias, and each of the first bumps electrically connects the corresponding conductive via with the circuit substrate; forming a first molding compound to cover the top surface of the circuit substrate and the first chips; removing the first molding compound above each of the first chips and reducing the thickness of each of the first chips to expose a top surface of each of the first chips and an end of each of the conductive vias, wherein the end of each of the conductive vias protrudes from the top surface of the corresponding first chip to form a through silicon via; and respectively bonding a second chip onto each of the first chips, wherein a bottom surface of each of the second chips faces the corresponding first chip, each of the second chips has a plurality of pillar bumps on its bottom surface, and the pillar bumps electrically connect their corresponding second chip with the through silicon vias.