Patent ID: 8614444

Claim:
A top-gate transistor array substrate, comprising: a transparent substrate, having a plane; an ion release layer, disposed on the transparent substrate and completely coveting the plane; a pixel array, disposed on the ion release layer and comprising a plurality of transistors and a plurality of pixel electrodes, wherein each of the transistors comprises: a source disposed on the ion release layer; a drain disposed on the ion release layer, wherein the pixel electrodes are electrically connected to the drains respectively; a metal oxide semiconductor (MOS) layer disposed on the ion release layer and contacting the ion release layer, the source, and the drain wherein the MOS layer partially covers the source and the drain, and the ion release layer is used for releasing a plurality of ions into the MOS layer a gate disposed above the MOS layer; and a first insulating layer disposed between the MOS layers and the gates and covering the MOS layers, the sources, and the drains.