Patent ID: 7603576

Claim:
A computer implemented method for thermal throttling using hysteresis in a heterogeneous multi-core processor that is implemented on a single integrated circuit chip, comprising: providing, in each one of a plurality of cores that are included in the heterogeneous multi-core processor, a separate digital thermal sensor that senses a temperature in the digital thermal sensor's respective one of the plurality of cores; setting, in a throttle point register that is included in the processor and outside of the plurality of cores, a first throttling temperature that is used for a first one of the plurality of cores and a second throttling temperature that is used for a second one of the plurality of cores, wherein the first and second throttling temperatures are used at the same time; sensing, by each digital thermal sensor, a temperature in each one of the plurality of cores; determining if a first sensed temperature sensed by a first digital thermal sensor in a first one of the plurality of cores is greater than or equal to the first throttling temperature; responsive to the first sensed temperature meeting or exceeding the first throttling temperature, initiating a throttling mode in only the first one of the plurality of cores; sensing, by the first digital thermal sensor, a new first temperature; determining if the new first temperature is less than an end throttling temperature; and responsive to the new first temperature being less than the end throttling temperature, disabling the throttling mode in only the first one of the plurality of cores.