Patent ID: 8344926

Claim:
A successive-approximation analog-to-digital converter for converting an input voltage on at least two bits comprising: a first circuitry configured for setting an upper limit voltage and a lower limit voltage of a conversion range, the input voltage being comprised in the conversion range, an input terminal receiving the input voltage, a first comparator performing a first comparison of the input voltage with a first reference voltage and delivering a first digital bit according to the first comparison, a first calculator comprising a first analog input connected to the input terminal, second and third inputs connected to the first circuitry so as to receive the upper limit voltage and the lower limit voltage, a fourth input connected to the first comparator so as to receive the first digital bit and an output providing an intermediate analog voltage, a second comparator performing a second comparison of the intermediate analog voltage with a second reference voltage and delivering a second digital bit according to the second comparison, a second calculator comprising a first analog input connected to the input terminal, second and third inputs connected to the first circuitry so as to receive the upper limit voltage and the lower limit voltage, a fourth input connected to the first single-bit comparator so as to receive the first digital bit, a fifth input connected to the second comparator so as to receive the second digital bit and an output providing an residual analog voltage.