Patent ID: 7190906

Claim:
A circuit for detecting phase errors between a data signal and a clock signal to facilitate the recovery of data from a data signal comprising: a first storage device receiving the data signal; a first delay block coupled to the first storage device; a second storage device coupled to the first delay block; a third storage device coupled to the first storage device; a second delay block receiving the data signal; a first logic gate coupled to the second storage device and the third storage device; and a second logic gate coupled to the second delay block and the first storage device, wherein the first logic gate and the second logic gate are configured to perform exclusive-OR operations on received signals wherein a clock-to-Q delay of the first storage device and a trace coupling the first storage device to the second logic gate matches a delay through the second delay block and a trace coupling the second delay block to the second logic gate, wherein a clock-to-Q delay of the second storage device and a trace coupling the second storage device to the first logic gate matches a clock-to-Q delay of the third storage device and a trace coupling the third storage device to the first logic gate.