Patent ID: 8115507

Claim:
A parallel test circuit comprising: a first transfer circuit that sequentially transfers a data pattern, supplied from a data pattern supply source, in response to a clock signal, the data pattern from the data pattern supply source being supplied to one of a plurality of chips under test, a data pattern from a corresponding stage of the first transfer circuit being sequentially supplied to each of the remaining ones of the chips under test; a second transfer circuit that sequentially transfers an output of the one chip under test, as an expected value pattern, in response to the clock signal; and a comparator circuit that is provided in association with each of the remaining chips under test and that compares output data of each of the remaining chips under test with the expected value pattern supplied from corresponding stages of the second transfer circuit to determine whether or not the output data coincides with the expected value pattern; a plurality of chips under test being allowed to be tested in parallel by the sole data pattern supply source, wherein as the one chip under test, there are provided a plurality of chips under test connected in parallel, a data pattern from the data pattern supply source and a clock signal from a clock supply source are supplied in parallel to each of the chips under test connected in parallel, and the parallel test circuit includes a compare and select circuit that receives outputs of the chips under test connected in parallel and that gives a majority decision on the outputs to select output data, an output of the compare and select circuit being transferred as the expected value pattern to the second transfer circuit.