Patent ID: 8873302

Claim:
A memory array, comprising: a plurality of memory cells arranged in an array of rows and columns, wherein each memory cell comprises: a floating gate memory transistor including a floating gate, a source region and a drain region; and a coupling capacitor located laterally from said floating gate memory transistor and having a first terminal electrically coupled to said floating gate and a second terminal operational as a control gate; a plurality of first bit lines oriented in a first direction, wherein each first bit line is coupled to drain regions of floating gate memory transistors that are arranged in a corresponding column; a plurality of second bit lines oriented in said first direction, wherein each second bit line is coupled to source regions of floating gate memory transistors that are arranged in a corresponding column; and a plurality of word lines oriented in a second direction that is orthogonal to said first direction, wherein each word line is coupled to the second terminals of said coupling capacitors that are arranged in a corresponding row through one or more doped diffusion regions.