Patent ID: 8032716

Claim:
A method for facilitating processing of a computing environment, the method comprising: receiving a quiesce request at a system controller from an initiating processor; sending the quiesce request to a plurality of processors; receiving a fast quiesce reset command at the system controller from the initiating processor once updates to system resources are complete; indicating to the plurality of processors that a block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the plurality of processors to continue processing without block translation restrictions; receiving an other quiesce request at the system controller; determining a status of a translation look aside buffer (TLB) purging process at the plurality of processors in response to receiving the fast quiesce reset command and to receiving the other quiesce request, the status being one of complete and incomplete; and holding the other quiesce request in response to the status of the TLB purging process being incomplete.