Patent ID: 8683126

Claim:
A storage controller controlling access requests to a plurality of secondary storage units, said storage controller comprising: a buffer; a control unit coupled to said buffer; and a plurality of FIFOs (first in first out) coupled between said control unit and said secondary storage units, wherein there is a one-to-one correspondence between said secondary storage units and said FIFOs, said control unit comprising a data path between said buffer and said FIFOs, and said buffer comprising a data path between said control unit and a main memory; wherein said control unit is operable to receive: i) a first read request specifying a first sequence of data to be read from a first secondary storage unit and transferred to said main memory and ii) a second read request specifying a second sequence of data to be read from a second secondary storage unit and transferred to said main memory, said control unit operable to retrieve said first sequence of data from said first secondary storage unit in response to said first read request and to store said first sequence of data in a first FIFO corresponding to said first secondary storage unit before said first sequence of data is transferred to said buffer, said control unit further operable to retrieve said second sequence of data from said second secondary storage unit in response to said second read request and to store said second sequence of data in a second FIFO corresponding to said second secondary storage unit before said second sequence of data is transferred to said buffer, said buffer concurrently storing both of said first sequence of data and said second sequence of data before said first sequence and said second sequence are each transferred from said buffer to said main memory, said buffer also storing location descriptors that identify where in said main memory said first sequence of data and said second sequence of data are to be stored.