Patent ID: 7079539

Claim:
A processor comprising: first classification circuitry; first memory circuitry coupled to the first classification circuitry, the first memory circuitry being configurable to store at least a portion of a given packet to be processed by the first classification circuitry; second classification circuitry; and second memory circuitry coupled to the second classification circuitry, the second memory circuitry being configurable to store at least a portion of the given packet to permit processing thereof by the second classification circuitry; wherein the first classification circuitry is operative to perform a first pass classification on the given packet, and further wherein the portion of the given packet storable in the second memory circuitry comprises a portion of the given packet determined by the first pass classification to be required for a second pass classification performed by the second classification circuitry; and wherein the first classification circuitry in processing a plurality of packets comprising the given packet and an additional packet generates respective first and second first pass classification determinations that are different from one another and that result in different-sized portions of the respective packets being stored in the second memory circuitry for processing by the second classification circuitry.