Patent ID: 7330992

Claim:
A memory module, comprising: a plurality of memory devices; and a memory hub, comprising: a link interface receiving memory requests for access to at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests; a read synchronization module coupled to the memory device interface, the read synchronization module operable to compare timing between coupling read data from the memory devices and coupling read data from the memory hub and to generate an adjust signal corresponding to the compared timing; and a memory sequencer coupled to the link interface, the memory device interface, and the read synchronization module, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to adjust the timing at which read memory requests are coupled to the memory device interface responsive to the adjust signal.