Patent ID: 7768059

Claim:
A non-volatile single-poly memory cell for one bit storage, comprising: a first unit cell comprising a select gate, a first P + source doped region and a first P + drain/source doped region, wherein the select gate, the first P + source doped region and the first P + drain/source doped region constitute a first select transistor; the first unit cell further comprising: a first floating gate transistor series connecting with the first select transistor in a first row, and the first floating gate transistor comprising a first floating gate, the first P + drain/source doped region and a first P + drain doped region, wherein the first select transistor uses the first P + drain/source doped region mutually with the first floating gate transistor; and a second unit cell parallel connected to the first unit cell, the second unit cell comprising a second select transistor consisting of the select gate extending from the first unit cell, a second P + source doped region and a second P + drain/source doped region; the second unit cell further comprising a second floating gate transistor series connecting with the second select transistor in a second row, and the second floating gate transistor comprising a second floating gate arranged in the same column as the first floating gate, the second P + drain/source doped region and a second P + drain doped region, wherein the second select transistor uses the second P + drain/source doped region mutually with the second floating gate transistor; wherein both the first P + drain doped region and the second P + drain doped region are connected to the same bit line.