Patent ID: 7298171

Claim:
A logic gate comprising: a clocked latch circuit selectively couplable between a supply voltage source and a reference voltage source in response to a first clock signal, said latch circuit having first and second nodes thereof respectively coupled to first and second complementary logic gate outputs; first and second clocked strings of N number of series coupled transistors selectively couplable between said supply voltage source and said reference voltage source in response to a second clock signal, a selected terminal of each of said N transistors defining first through Nth intermediate nodes therebetween; N additional transistors, each of said N additional transistors being coupled between one of said intermediate nodes of said first and second clocked strings and a next higher number intermediate node on an opposite one of said first and second clocked strings, said Nth intermediate node of said first and second clocked strings also being selectively couplable to said first and second nodes of said clocked latch circuit in response to said second clock signal and wherein control terminals of each of said first and second clocked strings of N series coupled transistors and said N additional transistors define logic inputs to said logic gate, wherein said first and second clocked strings of N number of series coupled transistors are selectively couplable to said supply voltage source in response to a signal supplied to a control terminal of a transistor coupled in series with each of said first and second clocked strings and said supply voltage source.