Patent ID: 7939927

Claim:
A semiconductor memory apparatus comprising: a wiring substrate arranged with a device mounting part and connection pads aligned along one exterior side of said wiring substrate; a semiconductor memory device group arranged with a plurality of semiconductor memory devices including electrode pads which are arranged along one external side of said wiring substrate, said plurality of semiconductor memory devices being stacked on said device mounting part of said wiring substrate so that pad arrangement sides all face in the same direction; a controller device including electrode pads arranged along at least one external side of said wiring substrate, and stacked on said semiconductor memory device group; a first metallic wire which electrically connects said electrode pads of said plurality of semiconductor memory devices with said connection pads of said wiring substrate; a second metallic wire which electrically connects said electrode pads of said controller device with said connection pads of said wiring substrate, and a third metallic wire which electrically connects said electrode pads of said plurality of semiconductor memory devices with said electrode pads of said controller device; wherein said electrode pads of said plurality of semiconductor memory devices and said electrode pads of said controller device are arranged parallel to an arrangement position of said connection pads of said wiring substrate.