Patent ID: 7767517

Claim:
A method for fabricating a semiconductor memory comprising dual charge storage nodes overlying a semiconductor substrate, the method comprising the steps of: forming a dielectric plug comprising a first portion recessed into the semiconductor substrate and a second portion extending above the semiconductor substrate; growing a layer of semiconductor material overlying the second portion; forming a first layered structure overlying a first side of the second portion of the dielectric plug and a second layered structure overlying a second side of the second portion of the dielectric plug, each of the first layered structure and the second layered structure overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers, implanting conductivity determining ions into the substrate to form a first bit line adjacent the first side and a second bit line adjacent the second side; depositing and patterning a layer of conductive material to form a control gate overlying the dielectric plug, the first layered structure, and the second layered structure; and forming a layer of gate insulator material overlying the layer of semiconductor material.