Patent ID: 7078723

Claim:
A microelectronic device, comprising: a substrate; a plurality of doped regions forming drain regions and source regions; a first and second patterned feature located over the substrate, each patterned feature including at least one electrode positioned between a drain region and a source region, wherein the first and second patterned features are substantially the same distance from the substrate; and a first sill including at least one monolayer of an impurity, the first sill positioned below the drain and source regions of the first patterned feature and separated from the drain and source regions by a first cap layer underlying the first patterned feature; and a second sill including at least one monolayer of an impurity, the second sill positioned below the drain and source regions of the second patterned feature and separated from the second patterned feature by a second cap layer underlying the second patterned feature, wherein an interface between the second sill and the second cap layer divides each of the drain and source regions of the second patterned feature into an upper portion and a lower portion.