Patent ID: 8546223

Claim:
A manufacturing method of a semiconductor device, the manufacturing method comprising the steps of: (a) forming, over a principal surface of a semiconductor substrate having a first region where a semiconductor element is provided and a second region which is located circumferentially outside the first region and where a breakdown resistant structure is provided, a first semiconductor region of a first conductivity type forming a drift region of the semiconductor element; (b) forming, in a surface side of the first semiconductor region in the second region, a second semiconductor region of a second conductivity type opposite to the first conductivity type; (c) forming, in the surface side of the first semiconductor region on an outermost circumferential side of the second region, a third semiconductor region of the first conductivity type or the second conductivity type in isolated relation to the second semiconductor region and surrounding the first region in plan view; (d) forming an insulating film over the semiconductor substrate; (e) forming a conductive film over the insulating film; (f) patterning the conductive film and the insulating film to form a pattern for exposing a predetermined portion of the first semiconductor region in the first region, and a predetermined portion of the first semiconductor region in the second region; and (g) after the step (f), introducing an impurity of the second conductivity type into the principal surface of the semiconductor substrate to form a fourth semiconductor region, wherein the semiconductor element has trench gates for controlling a current in the drift region, the manufacturing method further comprising the steps of: (h) between the step (d) and the step (e), forming a plurality of trenches in the surface side of the first semiconductor region in the first region; (i) after the step (h), forming a gate insulating film of the semiconductor element in each of the trenches; (j) in the step (f), forming the trench gates by burying the conductive film in each of the trenches and over the gate insulating film, the conductive film being coupled to at least one of the trench gates; and (k) forming a circumferential electrode terminal disposed over the insulating film and electrically coupled to the third semiconductor region, the circumferential electrode terminal surrounding the first region in plan view, wherein the circumferential electrode terminal partially overlaps with the conductive film in plan view.