Patent ID: 8723576

Claim:
A clock generation circuit comprising: a system clock selection circuit that selects one of a first and a second clock signals as a system clock signal according to a selection signal, the first clock signal having a first frequency and the second clock signal having a second frequency; a frequency division circuit that frequency-divides the system clock signal and generates a plurality of divided clock signals; and an output clock selection circuit that selects a third clock signal having a third frequency from the plurality of divided clock signals according to the selection signal and a division ratio setting signal, wherein the output clock selection circuit comprises: a first selection circuit that selects a first divided signal from the plurality of divided clock signals according to the division ratio setting signal; a second selection circuit that selects a second divided signal from the plurality of divided clock signals according to the division ratio setting signal; and a third selection circuit that selects the first divided signal when the first clock signal is selected and selects the second divided signal when the second clock signal is selected according to the selection signal.