Patent ID: 7370298

Claim:
A method for preserving critical inputs in a digital design, said method comprising: receiving an initial circuit design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets that correlate to one or more properties of said initial circuit design that require verification, and one or more state elements; identifying a cut of said initial circuit design including one or more cut gates; computing a relation of one or more values producible to said one or more cut gates in terms of said one or more primary inputs which cannot be eliminated, said one or more primary inputs which can be eliminated and said one or more state elements; synthesizing said relation to form a gate set, wherein said gate set is behaviorally equivalent to said cut of said initial circuit design; forming an abstracted circuit design by replacing said cut of said initial circuit design with said gate set; and performing verification on said abstracted circuit design to generate verification results with reference to said initial circuit design.