Patent ID: 7694209

Claim:
A decoding device which decodes a (k+m) bit codeword including k-bit information symbols and an m-bit parity check code which is composed of a 1-bit correctable Hamming code, comprising: a syndrome calculation unit which is configured to calculate, in accordance with a check matrix, an m-bit syndrome corresponding to the (k+m) bit codeword, the m-bit parity check code being generated in accordance with a generator matrix corresponding to the check matrix, the check matrix including a unit matrix and a coefficient matrix, a most significant bit of each of a second vector to a last vector in the coefficient matrix being 1, binary codes with values 1 to k−1 being sequentially arranged from the second vector to the last vector in a matrix which is obtained by excluding the most significant bits of the second to the last vectors from the matrix comprising the second to the last vectors, a first vector of the coefficient matrix disagreeing with the other vectors in the check matrix, the first vector being composed of a specified bit pattern having a most significant bit of 0, and said k and said m being integers which satisfy restrictive conditions of k+m≦2 m −1 and k≦2 (m−1) ; and an error address output unit which is configured to output a lower (m−1) bit data field of the calculated m-bit syndrome as an error address in a case where a most significant bit of the calculated m-bit syndrome is 1 and the calculated m-bit syndrome disagrees with vectors in the unit matrix, and to output 0 as the error address in a case where the calculated m-bit syndrome has the specified bit pattern, the error address being indicative of a bit position in the k-bit information symbols, at which an error occurs.