Patent ID: 8471593

Claim:
A data processor on a chip comprising: a plurality of data processing cores, each of at least some of the processing cores including: at least one arithmetic logic unit that supports at least division and multiplication of at least 32-bit wide data; and at least 3 registers for storing at least 32-bit wide data; a plurality of memory units to buffer at least 32-bit wide data; at least one interface unit for providing at least one communication channel between the data processor and external memory; and a bus system flexibly interconnecting the plurality of processing cores, the plurality of memory units, and the at least one interface; wherein: the bus system includes a first structure dedicated for data transfer in a first direction and a second structure dedicated for data transfer in a second direction; and each of at least some of the data processing cores includes a physically dedicated connection to at least one physically assigned one of the plurality of memory units, the assigned one of the plurality of memory units being accessible by another of the data processing cores via a secondary bus path of the bus system.