Patent ID: 8486802

Claim:
A method of fabricating a semiconductor device, the method comprising: forming an isolation structure that defines first and second active regions in a substrate, the first and second active regions being on opposite sides of the isolation structure; forming a bit line electrically coupled to a contact plug, the contact plug being on the isolation structure between the first active region and the second active region, wherein the contact plug is electrically coupled to the first active region and the second active region; forming a recess in an upper surface of the isolation structure, such that the upper surface of the isolation structure is lower than an upper surface of the substrate so as to expose a sidewall of the first active region and a sidewall of the second active region; and forming a first silicon layer extending from a first side of the recess, and forming a second silicon layer extending from a second side of the recess, the first silicon layer being separated from the second silicon layer, the first and second silicon layers being formed in the recess and between the isolation structure and the contact plug, wherein: the first silicon layer contacts the sidewall of the first active region, and the second silicon layer contacts the sidewall of the second active region.