Patent ID: 7015148

Claim:
A method of forming a semiconductor device, the method comprising the steps of: forming a photosensitive layer to be patterned; patterning the photosensitive layer to form a pattern including a master horizontal line and a master vertical line without a space therebetween; transferring the pattern to at least one underlying layer using the patterned photosensitive layer; forming a second photosensitive layer over the patterned at least one underlying layer; patterning the second photosensitive layer to form a second pattern including a master space aligned to dissect a horizontal line and a vertical line formed in the at least one underlying layer; transferring the second pattern to the at least one underlying layer to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a precise width dimension; and transferring the third pattern to at least one other underlying layer, wherein the at least one other underlying layer is a dielectric layer and the dielectric layer comprises a charge-trapping dielectric layer.