Patent ID: 7683706

Claim:
A gain amplifier having a switched-capacitor structure for minimizing settling time, comprising: a first switch to which an input voltage is applied from an input terminal; a sampling capacitor for storing the input voltage at a first clock; an N-stage amplifier for amplifying and outputting the input signal stored in the sampling capacitor at a second clock that does not overlap the first clock, wherein N denotes an integer of 2 or greater; second and third switches for applying a common mode voltage to the N-stage amplifier; a feedback capacitor connected between an input and an output of the N-stage amplifier; an input capacitor connected at one side to the input terminal; a fourth switch for connecting the other side of the input capacitor between an N−1th amplifier and an Nth amplifier of the N-stage amplifier at the first clock; and a fifth switch for connecting the N−1th amplifier of the N-stage amplifier to the Nth amplifier at the second clock.