Patent ID: 8881075

Claim:
A method implemented in a programmable system for verifying a design of an integrated circuit, comprising: a) providing a register-transfer language description of the integrated circuit to the system; b) generating a set of assertions sufficient to test a functionality of the integrated circuit; c) measuring an assertion density of the set of assertions, wherein the assertion density is measured by a comparison of a number of predicates computed from the description that are satisfiable on the set of assertions relative to a number of predicates satisfiable on a set of simulation traces of the integrated circuit; d) comparing the measured assertion density with a predetermined threshold; e) repeatedly modifying the set of assertions or generating a new set of assertions, and re-measuring the assertion density until the measured assertion density exceeds said threshold; and f) applying the particular set of assertions for which assertion density exceeds said threshold to a design verification of the integrated circuit.