Patent ID: 8456225

Claim:
A negative charge pump circuit, comprising: a first PMOS/NMOS switch pair coupled between a negative voltage output and a reference potential; a second PMOS/NMOS switch pair coupled between the negative voltage output and a reference potential; a first capacitor having a positive node coupled to a first clock signal configured to charge the first capacitor and negative node coupled to the first PMOS/NMOS switch pair and to the second PMOS/NMOS switch pair and configured to control the conduction state of the second PMOS/NMOS switch pair; a second capacitor having a positive node coupled to a second clock signal configured to charge the second capacitor and negative node coupled to the second PMOS/NMOS switch pair and to the first PMOS/NMOS switch pair and configured to control the conduction state of the first PMOS/NMOS switch pair; first blocking circuitry coupled to the PMOS switch of the first PMOS/NMOS switch pair and to the reference potential, the first blocking circuitry is configured to prevent a charge at said negative node of said first capacitor from leaking to the reference potential through the PMOS switch of the first PMOS/NMOS switch pair; and second blocking circuitry coupled to the PMOS switch of the second PMOS/NMOS switch pair and to the reference potential, the second blocking circuitry is configured to prevent a charge at said negative node of said second capacitor from leaking to the reference potential through the PMOS switch of the second PMOS/NMOS switch pair.