Patent ID: 8203367

Claim:
A frequency divider, comprising: a cascade of at least two triggered delay elements, each having a data input, a clock input, a trigger control input and a data output, the delay elements configured to forward a state of an input signal at their respective data input to their respective data output, wherein it depends on a control signal at the respective trigger control input of the delay element whether the state is forwarded either for a rising clock edge of a clock signal at their respective clock input or for a falling clock edge of the clock signal; a reference frequency input; and a clock output; wherein the clock input of each of the delay elements of the cascade is coupled to the reference frequency input; wherein the data input and the trigger control input of the first delay element of the cascade are coupled to the data output of the last delay element of the cascade; wherein the data input and the trigger control input of further delay elements of the cascade are coupled to the data output of a respective preceding delay element of the cascade; wherein the clock output is coupled to the data output of the last delay element of the cascade; wherein the trigger control input of one of the delay elements of the cascade is coupled to the corresponding data output by inverting means; and wherein the respective data input of the other delay elements of the cascade is coupled to the corresponding data output by respective inverting means.