Patent ID: 8391074

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells, each of the memory cells being capable of holding multi-level data; and a control circuit configured to perform a program cycle including a plurality of program loops, each of the program loops involving a first operation supplying a program voltage and a second operation supplying a verify voltage to be supplied to a gate of a selected memory cell, each of the program cycles involving a first phase, a second phase, and a third phase, the control circuit being configured to perform the second operation after performing the first operation in each of the program loops, the control circuit being configured to supply a first verify voltage without supplying a second verify voltage in the first phase, the control circuit being configured to supply the first verify voltage and the second verify voltage larger than the first verify voltage in the second phase, and the control circuit being configured to supply the second verify voltage without supplying the first verify voltage in the third phase.