Patent ID: 6906556

Claim:
A high-speed domino logic with improved cascode keeper circuit comprising: a first supply voltage; a second supply voltage; a first clock signal; a high-speed domino logic with improved cascode keeper OUT terminal; an inverted and delayed first clock signal being approximately 180 degrees out of phase with said first clock signal and delayed with respect to said first clock signal by a predetermined time; a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first supply voltage being coupled to said first transistor first flow electrode, said first clock signal being coupled to said first transistor control electrode, said first transistor second flow electrode being coupled to a first node, said first transistor having a first threshold voltage; a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said second transistor second flow electrode being coupled to said first node, said second transistor control electrode being coupled to said high-speed domino logic with improved cascode keeper OUT terminal, said second transistor having substantially said first threshold voltage; a logic block, said logic block comprising at least one logic block input terminal and a logic block output terminal; a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said third transistor first flow electrode being coupled to said logic block output terminal, said third transistor second flow electrode being coupled to said second supply voltage, said third transistor control electrode being coupled to said first clock signal; a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode, said first supply voltage being coupled to said fourth transistor first flow electrode, said fourth transistor second flow electrode being coupled to second transistor first flow electrode, said fourth transistor control electrode being coupled to said inverted and delayed first clock signal; an inverter, said inverter comprising an inverter input terminal and an inverter output terminal, said inverter input terminal being coupled to said first node, said inverter output terminal being coupled to said OUT terminal of said high-speed domino logic with improved cascode keeper circuit.