Patent ID: 8635409

Claim:
A cache comprising: a memory portion configured to store data in cache lines; a cache pipeline configured to control access to the memory portion; a plurality of state machines configured to create cache pipeline access requests, the cache pipeline access requests, the cache pipeline requests being of a first mode that includes a first step and a coherency check, the first step requiring access to a particular cache line; a line store coupled to the cache pipeline and configured to store information about the availability of cache lines in the memory portion; an arbiter coupled to the cache pipeline, the line store and the state machines, the arbiter being configured to select one of the pipeline access requests received from the state machines, the arbiter further being configured to determine if the particular cache line of the first step of the selected cache pipeline access request is available and to change the request into a second mode that only includes the coherency check in the event the particular cache line of the first step of the selected cache pipeline access request is not available.