Patent ID: 7968409

Claim:
A method of manufacturing a composite semiconductor device which includes a MOS transistor device and a castellated-gate MOSFET device capable of fully-depleted operation comprising the steps of: creating a starting silicon semiconductor substrate; applying active layer pad nitride masks to form trench isolation islands in said substrate; forming a plurality of thin silicon channel elements by etching a plurality of spaced gate slots to a first predetermined depth into said substrate; filling said slots with a dielectric material; clearing out an area of said dielectric material within said gate slots to form a spacer and bottom gate; depositing a gate dielectric: filling said slot regions with a conductive gate material and connecting them together at their upper end surfaces with a top gate layer; implanting a source and a drain region at opposite end portions of said spaced, channel elements; implanting predetermined active areas in said starting silicon substrate so as to tailor the doping concentration and polarity of the semiconductor bodies formed thereby; forming a planer gate structure by deposing a planer insulating gate material, deposing a conductive gate material and then removing the unpatterned regions of said conductive gate material; and forming self-aligned source and drain regions by implanting a dopant species of a polarity opposite to that of said semiconductor bodies.