Patent ID: 7324403

Claim:
A method, comprising: sending a clock signal across a clock signal trace from a chipset to a first memory device and a second memory device, both memory devices located on a memory module, wherein the chipset is discrete from the memory module; the first memory device and the second memory device receiving the clock signal a first time as an early clock signal; the first memory device and the second memory device receiving the clock signal a second time as a late clock signal; the first memory device and the second memory device generating average clock signals by determining a timing sequence of the early clock signal, determining a timing sequence of the late clock signal, and creating an average clock signal that has a timing sequence halfway between the timing sequence of the early clock signal and the timing sequence of the late clock signal, wherein the first memory device's average clock signal and the second memory device's average clock signal are synchronous; and terminating the clock signal on the memory module with a termination resistor after the first and second memory devices have received both the early and late clock signals.