Patent ID: 8269713

Claim:
A shift register having a configuration in that unit circuits each configured with transistors of an identical conduction type are cascaded, and configured to operate based on two-phase clock signals whose on-level periods do not overlap with each other, wherein the unit circuit includes: an output control transistor having a first conduction terminal configured to receive one of the clock signals, and a second conduction terminal connected to an output terminal; a precharge circuit for applying an on-voltage to a control terminal of the output control transistor during a period that an input signal is at an on-level; a reset signal generation circuit for generating a reset signal which turns into the on-level in a normal state, by use of the two-phase clock signals, and changing the reset signal to an off-level when the input signal turns into the on-level; and a discharge circuit for applying an off-voltage to the control terminal of the output control transistor during a period that the reset signal is at the on-level.