Patent ID: 8049249

Claim:
A semiconductor wafer, comprising: a first die region having a first die and a second die region having a second die, said first die region being adjacent to said second die region; a protective device in a scribe line region, said scribe line region being between said first die region and said second die region; a first mesh of metal lines on a surface of said first die, wherein said first mesh of metal lines is in electrical communication with said protective device; a second mesh of metal lines on a surface of said second die, wherein said second mesh of metal lines is in electrical communication with said protective device; a first plurality of exposed terminals on said surface of said first die, wherein said first plurality of exposed terminals are not in electrical communication with said first mesh of metal lines; and a second plurality of exposed terminals on said surface of said second die, wherein said second plurality of exposed terminals are not in electrical communication with said second mesh of metal lines.