Patent ID: 7038953

Claim:
A memory interface control circuit for reading data in each time slot belonging to a burst data from a memory, said memory outputting said burst data after an elapsed predetermined delay time from inputting a read command, said memory also outputting a data strobe signal, said data strobe signal being in preamble state in a period which starts after said memory inputs said read command and ends just before said memory starts to output said burst data, said data strobe signal being in toggle state in output period when said memory outputs said burst data, said data strobe signal toggling every time slot in said output period, said data strobe signal being in postamble state just after said output period, said memory interface control circuit comprising: a secondary data strobe signal generating circuit which generates, on the basis of said data strobe signal, a secondary data strobe signal which toggles when said data in each time slot belonging to said burst data is stable and which maintains the level of a time when the toggling is completed until at earliest a time when reading data in all time slots stored temporarily in a buffer circuit is completed; and said buffer circuit for temporarily storing data of all time slots belonging to said burst data by using said secondary data strobe signal.