Patent ID: 8194755

Claim:
A system comprising: a bit-stream buffer controller including: a first first-in first-out (FIFO) buffer configured to store an inputted bit-stream; a second FIFO buffer configured to store a payload extracted from the inputted bit-stream; and an interrupt controller configured to: track a first status flag of the first FIFO buffer and a second status flag of the second FIFO buffer; and generate an interrupt signal when the first and second status flags of the first FIFO buffer and the second FIFO buffer meet a predetermined condition; and a video decoder connected with the bit-stream buffer controller, the video decoder being configured to load the payload from the second FIFO buffer in one of a first mode and a second mode of operation, wherein the video decoder checks the second status flag each time the video decoder loads the payload from the second FIFO buffer in the first mode of operation, and the video decoder loads the payload from the second FIFO buffer without checking the second status flag in the second mode of operation, the video decoder switching between the first mode of operation and the second mode of operation in response to the interrupt signal.