Patent ID: 7834420

Claim:
A semiconductor integrated circuit device comprising: a memory cell of a static random access memory including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each of the first-channel MISFET and the second n-channel MISFET having a gate electrode formed over a semiconductor substrate, and a source region and a drain region formed in the semiconductor substrate, each of the first p-channel MISFET and the second p-channel MISFET having a gate electrode formed over the semiconductor substrate, and a source region and a drain region formed in the semiconductor substrate; a first insulating film formed over the MISFETs; a first conductive film and a second conductive film formed on the first insulating film and comprised of a different conductive layer from that of the gate electrodes of the MISFETs, the first conductive film being electrically connected to the drain region of the first n-channel MISFET, the drain region of the first p-channel MISFET, the gate electrode of the second n-channel MISFET and the gate electrode of the second p-channel MISFET, the second conductive film being electrically connected to the drain region of the second n-channel MISFET, the drain region of the second p-channel MISFET, the gate electrode of the first n-channel MISFET and the gate electrode of the first p-channel MISFET; a third conductive film, a fourth conductive film, a fifth conductive film and a sixth conductive film formed with the same level layer as the first conductive film and the second conductive film and arranged separately with each other; a second insulating film formed over the first conductive film, the second conductive film, the third conductive film, the fourth conductive film, the fifth conductive film and the sixth conductive film; a power source line formed over the second insulating film and electrically connected to the source region of the first p-channel MISFET through the third conductive film and to the source region of the second p-channel MISFET through the fourth conductive film; and a reference voltage line formed over the second insulating film, formed with the same level layer as the power source line and electrically connected to the source region of the first n-channel MISFET through the fifth conductive film and to the source region of the second n-channel MISFET through the sixth conductive film.