Patent ID: 8149027

Claim:
A circuit comprising: a depletion mode upper transistor with a second electrode coupled to a first electrode of a lower transistor; a first voltage supply node coupled to a first electrode of the depletion mode upper transistor; a second voltage supply node coupled to a second electrode of the lower transistor; a load node disposed between the second electrode of the depletion mode upper transistor and the first electrode of the lower transistor; an upper driver transistor selectively coupling a gate electrode of the depletion mode upper transistor to an upper drive voltage node, the upper driver transistor having a control electrode coupled to an upper switched voltage supply circuit; a lower switched voltage supply circuit coupled to a gate electrode of the lower transistor; and a voltage dependent resistor coupled across the gate electrode and second electrode of the depletion mode upper transistor, wherein in use when the lower transistor and upper driver transistor are in a non-conductive state, a potential difference across the voltage dependent resistor is sufficiently small so as to place the depletion mode upper transistor into a conductive state and when the lower transistor and upper driver transistor are in a conductive state, the potential difference across the voltage dependent resistor provides a bias voltage to the gate electrode of the depletion mode upper transistor that has a negative potential sufficient to place the depletion mode upper transistor into a non-conductive state.