Patent ID: 7948796

Claim:
A semiconductor memory device comprising: a memory cell unit that is formed with a plurality of nonvolatile memory cells connected in series, is divided into at least two groups each including one or more of the nonvolatile memory cells, and has one end connected to a source line and the other end connected to a bit line, word lines being connected to gates of the nonvolatile memory cells, voltages of the word lines being controlled to store data from the bit line or output stored data onto the bit line; and a voltage applying circuit that applies voltages to the word lines of the nonvolatile memory cells, applying a first voltage to the word lines of the nonvolatile memory cells of the group located closer to the bit line, applying a second voltage which is higher than the first voltage to the word lines of the nonvolatile memory cells of the group located closer to the source line, with respect to the two adjacent groups of the memory cell unit, and applying an erase voltage which is higher than the first and second voltages to the cell well where the nonvolatile memory cells are formed, when a data erasing operation is performed to erase data stored in the nonvolatile memory cells forming the memory cell unit.