Patent ID: 7199428

Claim:
A master chip comprising: a plurality of unit cells arranged in rows and columns, each of the unit cells comprising: a plurality of parallel semiconductor ridges including first to sixth ridges; an insulating layer disposed on each of the first to sixth ridges; a first gate line extending in a direction orthogonal to the first to sixth ridges and disposed above the first to fourth ridges; and a second gate line extending in the direction orthogonal to the first to sixth ridges and disposed above the third to sixth ridges, wherein the first ridge, the insulating layer, and the first gate line implement a first capacitor, the second and third ridges and the first gate line implement a first driver transistor and a first load transistor, the fourth and fifth ridges and the second gate lines implement a second load transistor and a second driver transistor, and the sixth ridge, the insulating layer, and the second gate line implement a second capacitor.