Patent ID: 7196371

Claim:
A flash memory device, comprising: a substrate; a plurality of buried doped regions, disposed in parallel in the substrate, wherein the buried doped regions extend along a direction; a plurality of source regions and a plurality of drain regions respectively disposed in the substrate beside both sides of the buried doped regions; a plurality of floating gates, disposed over the substrate between the buried doped regions and the source regions, and between the buried doped regions and the drain regions, wherein each floating gate is a conductive spacer having a curved side; a plurality of control gates, disposed over the buried doped regions and the floating gates, wherein each control gate fills a space between two neighboring floating gates, and each control gate extends along the direction; a plurality of inter-gate dielectric layers, disposed between the control gates and the floating gates and between the control gates and the buried doped regions; and a plurality of tunneling dielectric layers, disposed between the floating gates and the substrate.