Patent ID: 8369175

Claim:
A memory element, comprising: a first power supply line that receives a first power supply voltage; a second power supply line that receives a second power supply voltage that is different than the first power supply voltage; and first and second circuits that are interconnected to form a bistable element having a data storage node on which data is stored during a normal operating mode of the memory element, wherein the stored data has a first state or a second state during the normal operating mode, wherein the first circuit is powered by the first power supply voltage and includes a transistor with a gate, wherein the gate receives the second power supply voltage at least when the data has the first state, and wherein the second power supply line is connected to the gate of the transistor in the first circuit so that during the normal operating mode the gate of the transistor in the first circuit receives the second power supply voltage when the data has the first state and when the data has the second state.