Patent ID: 7785957

Claim:
A method for fabricating an integrated circuit, comprising: providing a substrate having a semiconductor surface, wherein the semiconductor surface has a PMOS region and an NMOS region; forming a gate dielectric layer over the PMOS and NMOS regions; forming a metal layer over the gate dielectric layer; forming a silicon layer over the metal layer; forming and patterning a mask layer over the silicon layer; selectively etching the silicon layer to expose the metal layer over one of the NMOS region or PMOS region, with the other of the NMOS region or PMOS region protected from etching by the patterned mask layer; and removing the patterned mask layer and residue from the selective etching, including conducting a first wet clean with a material comprising sulfuric acid and a fluoride; and, following the first wet clean, conducting a second wet clean with a material comprising a diluted solution of a hydroxide and a peroxide having a volume ratio of the hydroxide to the peroxide to water of 1:X:Y, wherein X is in a range of 0.5 to 1.0, and Y is at least 250.