Patent ID: 7170795

Claim:
An electrically erasable charge trap nonvolatile memory cell comprising: a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein; the transistor having an initial threshold voltage before initial programming, a program threshold voltage after initial programming that is higher than the initial threshold voltage and an erase threshold voltage after erasing that is lower than the program threshold voltage but is higher than the initial threshold voltage; wherein the transistor comprises spaced apart source and drain regions in the integrated circuit substrate and the gate on the integrated circuit substrate therebetween; wherein the gate comprises a tunnel insulating layer on the substrate, the charge trapping region on the tunnel insulating layer, a blocking insulating layer on the charge trapping region and a gate electrode on the blocking insulating layer; wherein the tunnel insulating layer comprises thermal oxide; and wherein the blocking insulating layer comprises metallic oxide and/or metallic oxynitride that includes Group III or Group VB metals, and having a dielectric constant that is higher than that of the tunnel insulating layer.