Patent ID: 7042911

Claim:
A synchronization control device for sequentially receiving packet data in synchronism with periodic bus clock pulses and outputting one or more received packet data collectively as a data train for each synchronized frame having a period longer than a generating period of the bus clock pulses, said synchronization control device comprising: a first-in-first-out buffer; a write control section that writes received packet data or zero data into said first-in-first-out buffer in synchronism with the bus clock pulses; a read control section that reads out yet-to-be-read data from said first-in-first-out buffer; a synchronism evaluation section that, when a difference between a specific quantity of the yet-to-be-read data in said first-in-first-out buffer and a value represented by synchronization point information is outside an allowable range, controls a data readout rate of said read control section in such a manner that the difference falls within the allowable range; and a synchronization point control section that supplies the synchronization point information to said synchronism evaluation section, said synchronization point control section detecting leading packet data from among a plurality of successive packet data sequentially arriving in synchronism with the bus clock pulses, wherein when a period from the detected leading packet data to a next detected leading packet data has become shorter than the period of the synchronized frame, said synchronization point control section inserts a predetermined quantity of zero data immediately before the next detected leading packet data in said first-in-first-out buffer.