Patent ID: 6855590

Claim:
A semiconductor device manufacturing method comprising the steps of: forming a first dielectric film on an entire upper part of a semiconductor substrate; forming a photoresist pattern on a p-well including a gate pattern of an NMOS transistor and a gate spacer thereof, and subsequently implanting ions into an n-well for forming a high concentration source/drain regions of a PMOS by using the first dielectric film formed on upper parts of a gate pattern and a gate spacer of a PMOS transistor as an implant mask; and forming an interlayer dielectric film thereon and then forming a contact, wherein said semiconductor substrate includes a PMOS transistor region in the n-well; an NMOS transistor region in the p-well; the gate pattern of the PMOS transistor formed on the PMOS transistor region and the gate spacers formed on both side walls of the gate pattern thereof, and the gate pattern of the NMOS transistor formed on the NMOS transistor region and the gate spacers formed on both side walls of the gate pattern thereof; the n-well having a low concentration source/drain regions formed by ion-implantation using the gate pattern of the PMOS transistor as an implant mask; and the p-well having a low concentration source/drain regions formed by ion-implantation using the gate pattern of the NMOS transistor as an implant mask and a high concentration source/drain regions formed by ion-implantation using the gate pattern and the gate spacers of the NMOS transistor as an implant mask.