Patent ID: 7185298

Claim:
A method comprising steps of: (a) receiving as input a design database for an integrated circuit design; (b) receiving as input a first set of operating conditions and a second set of operating conditions for the integrated circuit design; (c) calculating a first resistance solution and a single capacitance solution from the design database and the first set of operating conditions; (d) performing a parasitic extraction of the first resistance solution and the single capacitance solution to generate a first set of parasitic values; (e) saving the single capacitance solution to calculate a second set of parasitic values from a second resistance solution calculated for the second set of operating conditions; (f) calculating the second resistance solution from the design database and the second set of operating conditions; (g) performing a parasitic extraction of the second resistance solution and the single capacitance solution to generate the second set of parasitic values; and (h) generating as output the first set of parasitic values and the second set of parasitic values.