Patent ID: 8880780

Claim:
A method for use in a system comprising a serial interconnection of first to N-th memory devices connected in-series and a memory controller configured to communicate with the interconnection, N being an integer greater than one, each of the N memory devices including a memory for storing data and being associated with a device identification, each of the N memory devices being selectable based on the device identification, each of the N memory devices being configured to transfer an enable signal received at its enable input to a successive memory device of the serial interconnection, each of the N memory devices being configured to transfer a command signal received at its signal input to the successive memory device based on device selection determination and in response to the enable signal received at its enable input, each of the N memory devices being configured to receive a clock signal at its clock input and to perform operations in response to the received clock signal, the method comprising: at the memory controller sending a command signal to the first memory device; the command signal including a device address identification for device selection, an operation instruction and a memory address identification; wherein, the device address identification, the operation instruction and the memory address identification form a modular command structure, the modular command structure being a byte basis, at an i-th memory device of the serial interconnection, i being 1≦i≦N receiving the command signal sent by the memory controller or transferred from a previous memory device, the receiving the command signal being enabled by the enable signal received at the enable input of the i-th memory device, determining whether the i-th memory device is selected based on the device address identification included in the received command signal and the associated device identification, in a case of determination where the i-th memory device is selected, providing a selection determination for processing, and in response to the selection determination for processing, processing the operation instruction included in the received command signal to access the memory included in the i-th memory device in accordance with the memory address identification included in the received command signal, in a case of determination where the i-th memory device is not selected, forwarding the received command signal including the device address identification, the operation instruction and the memory address identification formed in a modular command structure to the signal input of the successive memory device.