Patent ID: 8325511

Claim:
A semiconductor static random-access memory operable in a normal operating mode and a retain-till-accessed (RTA) mode, comprising: a plurality of memory cells, arranged in rows and columns in at least one memory array block, each of the plurality of memory cells comprised of metal-oxide-semiconductor (MOS) array transistors arranged into a latch and a read buffer, wherein the latch of each of the memory cells in each column is biased in parallel between a power supply voltage node and a reference voltage node; a first plurality of bias devices associated with a first memory array block, each of the first plurality of bias devices having a conduction path connected in series with memory cells in its associated memory array block between the reference voltage node and a ground reference voltage node; and a first switch device, having a conduction path connected between the reference voltage node and the ground reference voltage node, and having a control electrode receiving an RTA control signal so that the first switch device is turned on in the normal operating mode and turned off in the RTA mode; wherein the latch in each of the plurality of memory cells comprises: first and second cross-coupled inverters, biased between the power supply voltage and the reference node, the first and second cross-coupled inverters defining first and second storage nodes; and first and second pass transistors, the first pass transistor having a conduction path connected between the first storage node and a first write bit line, the second pass transistor having a conduction path connected between the second storage node and a second write bit line, and the first and second pass transistors having control electrodes coupled to a write word line; and wherein the read buffer comprises: a first read buffer driver transistor, having a conduction path, and having a control electrode coupled to the first storage node; and a first read buffer pass transistor, having a conduction path connected in series with the conduction path of the first read buffer driver transistor between a first read bit line and a ground reference voltage node, and having a control electrode coupled to a read word line.