Patent ID: 8508456

Claim:
A microcomputer comprising: a plurality of segment/key source terminals that connect with a LCD panel and a key matrix, respectively; a plurality of key return terminals that connect with the key matrix; a segment/key source control circuit that connects with the plurality of segment/key source terminals, and outputs a signal for one frame periodically, the one frame containing a display output period and a key source output period; a register that stores a value indicating one of a key-in wait state and a key scan state, the key-in wait state indicating a state that the key matrix is not operated, the key scan state indicating a state that the key matrix is operated; an interrupting circuit that connects with the plurality of key return terminals, and outputs an interrupt signal when a level of an input signal from anyone of the plurality of key return terminals changes; and a processing circuit that stores the value indicating the key scan state in the register in response to the interrupt signal, wherein the segment/key source control circuit: outputs a segment signal to the plurality of segment/key source terminals during the display output period, the segment signal having a display drive voltage indicating a maximum value, a minimum value, and intermediate values between the maximum value and the minimum value, and outputs, when the value in the register indicates the key scan state, a first key scan pulse signal and a second key scan pulse signal following the first key scan pulse signal to the plurality of segment/key source terminals during the key source output period, the first key scan pulse signal varying between the maximum value and the minimum value, the second key scan pulse signal being an inversion signal of the first key scan pulse signal.