Patent ID: 6937727

Claim:
A circuit for implementing the Advanced Encryption Standard (AES) block cipher algorithm in a system having a plurality of channels, the circuit comprising: round key generation means for (i) selectively receiving a cipher key and (ii) generating a round key of a first predetermined bit length from the received cipher key a predetermined number of times based on the AES Rijndael key expansion algorithm; encryption/decryption means for (i) selectively receiving a data block of the first predetermined bit length from one of the plurality of system channels and a round key from the round key generation means and (ii) encrypting/decrypting the received data block a predetermined number of rounds based on the AES block cipher algorithm; and controller means, responsive to control signals from each of the plurality of system channels, for controlling the round key generation means and the encryption/decryption means to selectively encrypt or decrypt the data block from individual ones of the plurality of system channels in a round-robin fashion.