Patent ID: 6977849

Claim:
A semiconductor device, comprising: a first output buffer coupled to an output pad, enabled in a normal operation mode and set to an output high impedance state in a test operation mode, for driving said output pad with first driving capability in accordance with an internal signal when enabled; a second output buffer coupled to said output pad, enabled in said test operation mode and set to an output high impedance state in said normal operation mode, for driving said output pad with a second driving capability greater than said first driving capability in accordance with said internal signal when enabled, said second output buffer including first and second insulated gate type field effect transistors coupled to said output pad, and complementarily rendered conductive to drive said output pad in accordance with said internal signal when the second buffer is enabled; and a back gate voltage generating circuit selectively activated in accordance with an operation mode designating signal, for generating a bias voltage to be applied to a back gate of at least one of said first and second insulated gate type field effect transistors when activated, said back gate voltage generating circuit including a clock generating circuit for generating a pumping clock signal when activated, a pumping circuit generating said bias voltage through a charge pumping operation of a capacitor in accordance with said pumping clock signal, and a detecting circuit for detecting a level of an output voltage of said pumping circuit and selectively activating a pumping clock generating operation of said clock generating circuit in accordance with a result of detection.