Patent ID: 8168493

Claim:
A method of manufacturing a semiconductor memory device, comprising: forming a first conductive layer on a semiconductor substrate including a first active region and a second active region; forming a second conductive layer covering the first conductive layer on the first active region and defining an opening exposing a top surface of the first conductive layer on the second active region; forming a third conductive layer covering top surfaces of the first conductive layer and the second conductive layer on the first active region and the second active region; forming a gate electrode on the first active region and a resistor pattern on the second active region by patterning the first conductive layer, the second conductive layer and the third conductive layer; and forming a silicide layer on the gate electrode by performing a silicidation process, wherein the opening provides a height difference between top surfaces of the gate electrode and the resistor pattern and wherein the silicidation process is performed so as to prevent the silicide layer from being formed on the resistor pattern by the height difference.