Patent ID: 7410874

Claim:
A method of forming triple gate oxide (TGO) structures comprising: providing a substrate comprising regions of a first kind, regions of a second kind, regions of a third kind, internal isolation regions which separate devices within each region and bounding isolation regions which separate devices of different regions; wherein regions of the first kind are semiconductor regions over which devices with a first gate oxide layer are formed, said regions of the first kind comprising the internal isolation regions and the portions of the bounding isolation regions; regions of the second kind are semiconductor regions over which devices with a second gate oxides layer are formed, said regions of the second kind comprising the internal isolation regions and the portions of bounding isolation regions; and regions of the third kind are semiconductor regions over which devices with a third gate oxide layer are formed, said regions of the third kind comprising the internal isolation regions and the portions of bounding isolation regions; forming a second gate oxide layer over said regions of the first, second and the third kind; removing said second gate oxide layer from said regions of the first kind; forming a first gate oxide layer over said regions of the first kind; forming a first conductive layer over said regions of the first, second and the third kind; removing said first conductive layer and said second gate oxide layer from said regions of the third kind; forming a third gate oxide layer; forming a second conductive layer over said regions of the first kind, said regions of the second kind and said regions of the third kind; removing said second conductive layer and said third gate oxide layer from said regions of the first kind and said regions of the second kind; forming a third conductive layer over said regions of the first kind, said regions of the second kind and said regions of the third kind; completing fabrication of devices in said regions of the first kind, said regions of the second kind and said regions of the third kind according to standard manufacturing procedures wherein the first, second and third gate oxide layers have different thickness, the first gate oxide layer being the thickest and the third gate oxide layer being the thinnest.