Patent ID: 8405121

Claim:
A semiconductor device, comprising: a substrate having a main processing surface; a first source/drain region comprising a first material of a first conductivity type; a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second source/drain region is laterally disposed from the first source/drain region; a body region electrically coupled between the first source/drain region and the second source/drain region; a gate dielectric disposed over the body region; and a gate region disposed over the gate dielectric; wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in a direction that is perpendicular to the main processing surface of the substrate; wherein a portion of the body region is a tunneling region electrically coupled between the first source/drain region and a remaining portion of the body region, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the tunneling region in the direction that is perpendicular to the main processing surface of the substrate; and wherein the tunneling region comprises different material than the first material of the first conductivity type.