Patent ID: 7763513

Claim:
A method of manufacturing an integrated circuit comprising a memory device, comprising: defining isolation trenches in a surface of a semiconductor substrate; forming array gate electrodes, wherein forming array gate electrodes comprises: defining a gate groove in the semiconductor substrate; forming a gate electrode material so as to fill the groove; forming word lines, the array gate electrodes being connected with corresponding word lines; and forming peripheral circuitry by forming at least one peripheral transistor, the process of providing a peripheral transistor comprising forming a peripheral gate electrode; wherein the peripheral gate electrodes and the word lines are made by: forming a layer stack comprising at least one layer on the substrate surface so as to cover the memory cells and the peripheral circuitry; and thereafter, patterning the layer stack so as to form the word lines and the peripheral gate electrodes, wherein the method further comprises: providing a gate insulating material at an interface between an active area and a groove and at an interface between the active area and pockets; and depositing a gate electrode material so as to fill the groove and two pockets.