Patent ID: 7177190

Claim:
A nonvolatile memory integrated circuit placed on a substrate comprising a plurality of a nonvolatile memory arrays placed on said substrate; a memory control circuit in communication with external circuitry to receive address, command, and data signals, to interpret said address, command, and data signals, and in communication with said plurality of nonvolatile memory arrays to transfer said address, command and data signals for programming, reading, and erasing said nonvolatile memory arrays; and a voltage generator that generates a very large positive programming voltage and a very large negative erasing voltage and is in communication with said nonvolatile memory arrays to transfer said very large positive programming voltage to selected first sub-arrays of said nonvolatile memory arrays for programming said selected first sub-arrays and to transfer said very large negative erasing voltage to selected second sub-arrays of said nonvolatile memory arrays for erasing said selected second sub-arrays; wherein said voltage generator further generates a power supply voltage, a first moderately high positive program voltage, a second moderately high positive program voltage, an intermediate positive program voltage, and a ground reference voltage.