Patent ID: 8913356

Claim:
A composite electronic circuit assembly comprising two integrated circuit dice of the MOS or CMOS type and an integrated circuit package, with the two circuit dice placed in parallel to one another inside the package and electrically connected to one another by intermediate connection elements, wherein one of the two circuit dice, so-called digital die, contains circuit modules with digital functions, in particular combinatorial and/or sequential logical operators, read-only memory, and/or static random access memory (SRAM), and the other circuit die, so-called hybrid die, contains all circuit modules with analog functions or hybrid digital/analog functions, including switching or linear power supply modules, switch modules, write-once memory modules, phase locked clock generation modules, analog-to-digital converters and digital-to-analog converters, electrical signal input/output modules, physical interface modules, and/or random number generator modules, each digital module that is contained in the digital die being connected so as to be powered by at least one of the electrical power supply modules contained in the hybrid die, based on digital signals that are representative of a difference between an actual voltage of the digital module and a target supply voltage for that digital module, produced by at least one power supply monitoring module contained in the digital die and transmitted to a power, reset, and clock management unit contained in the circuit assembly, said power, reset, and clock management unit being arranged to remain active when the electronic circuit assembly is in idle state.