Patent ID: 7550997

Claim:
A method for decoding a 4-level input data signal comprising: receiving n 4-level input data signals with n being at least one, a clock signal, and a one-bit data signal, the input data signal being 4-level encoded by using the clock signal and the one-bit data signal, the one-bit data signal changing its bit value at least once during a predetermined time interval; comparing each of the n 4-level input data signals with the clock signal and providing for each of the n 4-level input data signals a first comparison data signal in dependence thereupon; comparing each of the n 4-level input data signals with the one-bit data signal and providing for each of the n 4-level input data signals a second comparison data signal in dependence thereupon; determining for each of the n 4-level input data signals if a data bit value of the 4-level input data signal is representing one of the clock signal, the one-bit data signal, and static values of the 4-level input data signal using the first and the second comparison data signal and based on the one-bit data signal changing its bit value at least once during the predetermined time interval; and, using a decode logic circuit generating for each of the n 4-level input data signals a 2-bit output data signal in dependence upon the determined data bit value representation.