Patent ID: 7190009

Claim:
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a first annular region of the first conductivity type, which is formed in an element formation surface side of said semiconductor substrate, and has an annular shape in a plane approximately in parallel with said element formation surface; a second annular region of a second conductivity type, which is formed inside said first annular region in said element formation surface side of the semiconductor substrate, and has an annular shape in a plane approximately in parallel with said element formation surface; a first region of the first conductivity type which is formed inside said second annular region in said element formation surface side of said semiconductor substrate; a first transistor provided on said first region; a second region of the second conductivity type which is formed inside said second annular region in said element formation surface side of said semiconductor substrate; a second transistor provided on said second region; a lower region of the second conductivity type, having a configuration in which said lower region is provided nearer to the bottom side of said semiconductor substrate than said first and said second regions, and said first region and the bottom side of said semiconductor substrate are separated from each other; a plurality of third regions of the first conductivity type which are formed outside said second annular region in said element formation surface side of said semiconductor substrate, and are electrically connected to each other through the bottom side of said semiconductor substrate; a third transistor provided on said third region; a fourth region of the second conductivity type, having a configuration in which said fourth region is formed outside said second annular region in said element formation surface side of said semiconductor substrate, is separated from said second annular region and said lower region by said first annular region, and encloses each of the outside faces of said third regions; and a fourth transistor provided on said fourth region.