Patent ID: 7630223

Claim:
A device comprising: a plurality of sub-memory cell arrays having a plurality of memory cells; a plurality of sense amplifiers to sense and amplify data from the plurality of memory cells; a signal line disposed to cross over the sub-memory cell arrays and the sense amplifiers; first power lines disposed at one side of the signal line, and crossing over an odd-numbered sense amplifier and sub-memory cell arrays adjacent to both sides of the odd-numbered sense amplifier such that each first power line crosses less than all of the sense amplifiers; and second power lines disposed at the other side of the signal line, and crossing over an even-numbered sense amplifier and sub-memory cell arrays adjacent to both sides of the even-numbered sense amplifier such that each second power line crosses less than all of the sense amplifiers; where the sub-memory cell arrays and the sense amplifiers are alternately disposed adjacent to each other and in a line.