Patent ID: 7608503

Claim:
A method of forming a memory cell, comprising: forming a first electrode, an insulating layer over the first electrode, a second electrode over the insulating layer, and a protective layer over the second electrode, with a side wall on the insulating layer; forming a side wall spacer on the side wall, the spacer comprising a layer of a programmable resistive material in electrical communication with the first and second electrodes, the side wall spacer having a length extending from the first electrode to the second electrode along the side wall, a width generally orthogonal to the length, the spacer, the first electrode and the second electrode having respective thicknesses which are less than 40 nm, and wherein forming the side wall spacer comprises depositing a layer of the programmable resistive material over the side wall and on the protective layer; anisotropically etching the layer of programmable resistive material to remove programmable resistive material in areas other than the side wall; forming a fill material on the protective layer and surrounding the programmable resistive material on the side wall; planarizing the fill material to expose tops of the programmable resistive material on the sidewall and leave a remaining portion of the protective layer over the second electrode; forming an etch mask having a lithographic pattern to define a lithographic width; trimming the etch mask to provide a trimmed mask to define a pattern; and selectively etching the programmable resistive material according to the pattern, to define the width of the side wall spacer, the width being less than 40 nm.