Patent ID: 7871882

Claim:
A method for fabricating a power transistor device comprising: forming a buffer layer of a first conductivity type on a substrate of a second conductivity type opposite to the first conductivity type, the buffer layer having a top surface, a first thickness, and a first doping concentration; forming an epitaxial layer of the first conductivity type over the buffer layer, the epitaxial layer having a top surface, a second thickness which is greater than the first thickness; forming a pair of spaced-apart trenches in the epitaxial layer that define a pillar which comprises the epitaxial layer, the pillar having first and second sidewall portions, and a first lateral width, the trenches extending in the vertical direction from the top surface of the epitaxial layer down to a bottom that extends beyond the top surface of the buffer layer, the trenches having a second lateral width; forming a dielectric material in the trenches that covers each of the first and second sidewall portions from at least just beneath the body region down to the bottom; forming a body region of the second conductivity type in the pillar; forming a first region of the first conductivity type in the pillar, the first region being of the first conductivity type and disposed at the top surface, the body region separating the first region of the pillar from a drift region that extends from the body region to the buffer layer; and forming a gate member in each of the trenches at or near the top surface, the gate member being disposed adjacent to and insulated from the body region.