Patent ID: 7283417

Claim:
Write control circuitry for a memory array configured with multiple memory subarrays, the write control circuitry comprising: multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to one associated memory subarray of the multiple memory subarrays, wherein the selectively enabling comprises outpuffing a write enable signal to the associated memory subarray, and wherein at least some subarray write controllers of the multiple subarray write controllers are powered at least in part via a switched power node, and wherein the switched power node is driven by multiple drivers distributively implemented among the multiple subarray write controllers associated with the multiple memory subarrays; a plurality of subarray select signals, only one subarray select signal being active at a time, and wherein each subarray select signal drives a different subarray write controller of the multiple subarray write controllers, resulting in only one write enable signal being output from one subarray write controller to its associated memory subarray at a time; and wherein the multiple subarray write controllers comprise local bitline write control circuits, each local bitline write control circuit comprising a buffer circuit having two series connected inverters, wherein a first inverter in the series is smaller than a second inverter in the series, and wherein the smaller inverter is powered by the switched power node.