Patent ID: 7797610

Claim:
An integrated circuit (IC), comprising: a plurality of configurable logic resources coupled to a plurality of configurable interconnect resources; and an embedded logic circuit coupled to the configurable logic resources and configured to exchange internal data with the configurable logic resources, the embedded logic circuit including, an input register bank coupled to latch a plurality of signals received from the configurable logic resources at a first clock rate; and a non-configurable random access memory (RAM) bank coupled to receive a write address and a read address from the input register bank and configured to provide write and read access to storage locations within the RAM bank at a second clock rate that is faster than the first clock rate; wherein the RAM bank is a dual-ported RAM that provides simultaneous access for respective addresses at first and second ports; wherein the input register bank includes respective data input registers, respective read address registers, and respective write address registers for each port of the dual-ported RAM; wherein the second clock rate is at least double the first clock rate, and the dual-ported RAM appears as a quad-ported RAM to the configurable logic resources with at least four accesses at the two ports of the dual-ported RAM being completed within one cycle of the first clock rate.