Patent ID: 8837657

Claim:
A circuit, comprising: an input section configured to store a data signal in response to phase shifted clocks to generate a plurality of sample values; an output section configured to store one of the sample values; and a logic section configured to selectively output one of the sample values to the output section in response to the sample values and a previous sampled value stored in the output section, the logic section including a compare section configured to generate a mismatch indication when a sampled value differs from the previous sampled value stored by the output section that includes a plurality of logic gates, each having one input coupled to one of the sampled values, one input coupled to the previous sampled value stored by the output section, and an output that provides the mismatch indication, and a path switch section configured to couple a sample value to the output section in response to the mismatch indications that comprises a multiplexer (MUX) having inputs coupled to receive the sampled values, a MUX output coupled to the output section, and control inputs coupled to receive the mismatch indications.