Patent ID: 8372690

Claim:
A method for packing a microelectronic system with a plurality of components comprising the steps of: encasing a trace frame with a bottom surface, a top surface, and a plurality of traces in a first molding compound such that the bottom surface is exposed outside of the first molding compound and the top surface includes a plurality of trace contacts; attaching an interconnect substrate to the top surface of the encased trace frame, the interconnect substrate having: an upper surface that has a plurality of upper contacts arranged in a ring about a central region; a lower surface that has a plurality of lower contacts dispersed within a region bound by the ring; a plurality of interconnects, each of the interconnects connecting one of the upper contacts to one of the lower contacts, the interconnects being embedded in the interconnect substrate for electrically isolating the interconnects from one another; the interconnect substrate being attached such that the trace contacts are in electrical communication with the plurality of lower contacts; mounting a first integrated circuit on the central region of the upper surface; and electrically connecting the first integrated circuit to the plurality of upper contacts.