Patent ID: 8868634

Claim:
A method of a processor performing multiplication of a multiplier and a multiplicand to generate a product, the method comprising: a) during a first cycle of the processor, generating a first subset of a plurality of partial products (PPs) based on the multiplier and the multiplicand; and storing in respective storage devices a pair of preliminary sum results and a carry result obtained by merging the first subset of PPs; b) during another cycle of the processor: generating an additional subset of the PPs based on the multiplier and the multiplicand; outputting the pair of preliminary sum results and a feedback carry result from the respective storage devices; and processing the pair of preliminary sum results to generate a feedback sum result; c) if all of the PPs have not been generated: storing in the respective storage devices a pair of preliminary sum results and a carry result obtained by merging the feedback sum result, the feedback carry result and the additional subset of PPs; and repeating step b); and d) if all of the PPs have been generated: storing in respective storage devices a final sum result and a final carry result obtained by merging the feedback sum result, the feedback carry result and the additional subset of PPs; and adding the final sum result and the final carry result to generate the product.