Patent ID: 7093108

Claim:
An apparatus for processing data, said apparatus comprising: a processing circuit for executing processing instructions from any of a plurality of instruction sets of processing instructions, each processing instruction being specified by an instruction address identifying that processing instruction's location in memory, the instruction address having a predetermined number of bits irrespective of the instruction set to which the associated processing instruction belongs, but a different number of most significant instruction address bits needing to be specified in the instruction address to uniquely idenfity processing instructions in different instruction sets; and encoding logic for encoding at least one instruction address with an indication of the instruction set corresponding to that instruction to generate an n-bit encoded instruction address, the encoding logic being arranged to perform the encoding by performing a computation equivalent to removing any least significant bits not forming the instruction address bits needing to be specified, and extending the specified instruction address bits to n-bits by prepending a pattern of bits to the specified instruction address bits, the number of least significant bits removed and the pattern of bits prepended being dependent on the instruction set corresponding to that instruction.