Patent ID: 8665408

Claim:
A liquid crystal display device comprising: a first substrate which includes: a plurality of pixel electrodes that are arranged in rows and columns to form a matrix pattern; a plurality of gate lines, each of which runs in a row direction; and a plurality of switching elements, each of which includes a gate, a source and a drain, each of the plurality of switching elements having its drain electrically connected to an associated one of the pixel electrodes and its gate electrically connected to an associated one of the gate lines, each set of the switching elements that are arranged in the row direction having their sources electrically connected together; a second substrate including a plurality of signal electrodes which are electrically independent of each other; and a liquid crystal layer which is interposed between the first and second substrates, wherein the first substrate further includes a gate driver which generates gate signals to be supplied to the gate lines, and wherein the second substrate further includes an external connecting terminal section, wherein a signal that has been input through the external connecting terminal section is supplied to the gate driver, wherein the gate driver generates gate signals in response to a plurality of gate clock signals, wherein the gate driver outputs some of the gate dock signals as the gate signals during a predetermined period, and the plurality of gate clock signals include: a first gate clock signal which inverts its level every two horizontal scanning periods; a second gate clock signal of which the phase has shifted by one horizontal scanning period with respect to the first gate clock signal; a third gate clock signal of which the phase has shifted by one horizontal scanning period with respect to the second gate clock signal; a fourth gate clock signal of which the phase has shifted by one horizontal scanning period with respect to the third gate clock signal; a fifth gate clock signal which repeats the same series of level changes from one of low, middle and high levels into another in a predetermined order every four horizontal scanning periods; a sixth gate clock signal of which the phase has shifted by one horizontal scanning period with respect to the fifth gate clock signal; a seventh gate clock signal of which the phase has shifted by one horizontal scanning period with respect to the sixth gate clock signal; and an eighth gate clock signal of which the phase has shifted by one horizontal scanning period with respect to the seventh gate clock signal.