Patent ID: 8368673

Claim:
An output buffer, comprising: a differential input stage, having a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, and a first output terminal; a bias current source, coupled to the differential input stage for providing a bias current to the differential input stage; an output stage, having a second output terminal coupled to the first input terminal for providing an output current via the second output terminal based on a signal of the first output terminal; and a feedback module, coupled between the differential input stage and the output stage for adjusting the bias current and the output current based on the first input signal and the second input signal, wherein the feedback module comprises a first mirror transistor, and a second source/drain of the first mirror transistor generates a reference current, the bias current source comprises a second mirror transistor for mirroring the reference current to adjust the bias current, and the output stage comprises a third mirror transistor for mirroring the reference current to adjust the output current, a first current and a second current are respectively induced in the differential input stage based on the first input signal and the second input signal, a sum of the first current and the second current is equal to the bias current, and the feedback module adjusts the bias current and the output current based on the first current, wherein the first mirror transistor mirrors the first current to generate the reference current, and the differential input stage comprises: a first transistor, having a gate serving as the first input terminal, a first source/drain inducing the first current, and a second source/drain coupled to the bias current source; a second transistor, having a gate serving as the second input terminal, a first source/drain inducing the second current, and a second source/drain coupled to the second source/drain of the first transistor; a third transistor, having a gate coupled to the first source/drain of the first transistor, a first source/drain coupled to a first voltage, and a second source/drain coupled to the gate thereof; and a fourth transistor, having a gate coupled to the gate of the third transistor, a first source/drain coupled to the first voltage, and a second source/drain coupled to the first source/drain of the second transistor.