Patent ID: 7480282

Claim:
An apparatus for generating enable signals in different independent clock domains enabling data transfers across the clock domains, the apparatus comprising: a data transport circuit for receiving data elements in sequential steps during a receive frame, receiving a receive clock, a core clock being independent of the receive clock, and a data valid signal that becomes active upon receiving valid data, where the data elements and the data valid signal are in sync with the receive clock; a multi-bit counter which is operative once the data valid signal becomes active, the multi-bit counter counting the number of sequential steps required to assemble the data elements into a group of data elements, the counting wraps the multi-bit counter to an initial count after the group of data elements is assembled, the multi-bit counter generating a first enable signal that enables the loading of the group of data elements into holding registers, the multi-bit counter changing the state of a toggle signal based on achieving a count that corresponds to the group of data elements being assembled, wherein the multi-bit counter is a log 2 (x/y)-bit counter for y-bit receive data elements to be assembled into an x-bit group of receive data elements, x and y both being a power of 2; and an enable circuit operating in synchronism with a core clock, the enable circuit generating a second enable signal responsive to the toggle signal, the second enable signal enabling the transfer of the group of data elements from the holding registers to core registers in sync with the core clock.