Patent ID: 8486795

Claim:
A method of fabricating transistors, comprising: providing a substrate comprising a first type well and a second type well; forming a first gate on the first type well and forming a second gate on the second type well; forming a third spacer and a mask layer simultaneously, wherein the third spacer is on the first gate and the mask layer covers the second type well and the second gate; forming an epitaxial layer in the substrate at two sides of the first gate; after forming the epitaxial layer, removing the mask layer and the third spacer; forming a material layer covering the second type well, the first type well, the first gate and the second gate; and removing the material layer partially to form a seventh spacer and the fourth spacer on the first gate and the second gate, respectively; forming a silicon cap layer covering the epitaxial layer, and the surface of the substrate at two sides of the second gate; forming a first source/drain region in the substrate at two sides of the first gate; and forming a second source/drain region in the substrate at two sides of the second gate.