Patent ID: 7859053

Claim:
An integrated circuit formed by a process that includes: forming at least two semiconductor bodies, wherein the semiconductor bodies have overlying insulative members; forming a sacrificial layer over the at least two semiconductor bodies and their overlying insulative members; planarizing the sacrificial layer; patterning the sacrificial layer to form a gate-defining member and removing portions of the insulative members to form remaining portions of the insulative members on the semiconductor bodies; forming a dielectric material adjacent the gate-defining member; covering the remaining portion of one of the insulative members; removing the remaining portion of another one of the insulative members after covering the remaining portion of one of the insulative members; removing the gate-defining member; forming an insulative layer and gate electrode layer within a trench defined by removal of the gate-defining member; and planarizing the gate electrode layer to form two gate electrodes separated by the remaining portion of one of the insulative members on one of the semiconductor bodies, and to form another gate electrode on another one of the semiconductor bodies.