Patent ID: 7589374

Claim:
A semiconductor device comprising: a memory cell transistor disposed in a cell region of a semiconductor substrate, the memory cell transistor comprising: a floating gate electrode disposed on a first active region of the semiconductor substrate and comprising a first lower silicon pattern and a first upper silicon pattern; a first gate insulating layer disposed between the first active region and the floating gate electrode; a control gate electrode disposed on the floating gate electrode, the first active region, and the device isolation layer; and an inter-gate insulating layer disposed between the floating gate electrode and the control gate electrode; and a peripheral circuit transistor disposed in a peripheral region of the semiconductor substrate, the peripheral circuit transistor comprising: a peripheral circuit gate electrode disposed on a second active region of the semiconductor substrate and comprising a second lower silicon pattern and a second upper silicon pattern, wherein the second upper silicon pattern has a uniform thickness and the second lower silicon pattern is wider than the second silicon pattern; and a second gate insulating layer disposed between the second active region and the peripheral circuit gate electrode.