Patent ID: 7096413

Claim:
A process of decomposing a set of parallel concatenated convolutional codes to select an address of an addressable location in each of a plurality of memories of up to n memories so that the selected addressable locations can be accessed in parallel, comprising steps of: a) providing a function matrix and first and second matrices implemented at least in part in an integrated circuit, the function matrix having unique coordinates containing addresses of the addressable locations in the memories; b) sorting a set of addresses of addressable locations into unique coordinate locations of the first and second matrices, each having m rows and n columns, such that each row contains no more than one address of a location in any one memory; c) creating third and fourth matrices at least in part in the integrated circuit, each having m rows and n columns, the third and fourth matrices containing entries identifying coordinates of addresses in the function matrix, the entries being arranged at unique coordinate locations in the third and fourth matrices so that each entry in the third matrix is at coordinates that match coordinates in the first matrix containing an address, and each entry in the fourth matrix is at coordinates that match coordinates in the second matrix containing an address; and d) decoding the set of convolutional codes using the function, first, second, third and fourth matrices to select an address of an addressable location in each of the plurality of memories.