Patent ID: 7096293

Claim:
A method of arbitrating a system bus that is shared by a CPU, which is a first master device, and second and third master devices, the method comprising: storing a first bus occupancy rate for each of the CPU and the second and third master devices and a variable bus occupancy rate; applying a second bus occupancy rate for the CPU, which is a sum of the first bus occupancy rate for the CPU and the variable bus occupancy rate, and the first bus occupancy rates for the second and third master devices to a bus arbiter, in response to an activation of an interrupt signal provided to the CPU; applying a third bus occupancy rate for the CPU, which is obtained by subtracting the variable bus occupancy rate from the first bus occupancy rate for the CPU, and the first bus occupancy rates for the second and third master devices to the bus arbiter, in response to an inactivation of the interrupt signal; and controlling a priority for use of the system bus in accordance with the second and third bus occupancy rates for the CPU and the first bus occupancy rates of the second and third master devices that are applied to the bus arbiter.