Patent ID: 6906952

Claim:
A nonvolatile memory apparatus comprising: a central processing unit; and a nonvolatile memory, wherein said central processing unit is capable of outputting a plurality of commands, an address, a write enable signal, a clock signal and data, wherein said commands includes a program command, wherein said nonvolatile memory comprises a plurality of word lines and a plurality of memory cells each of which has a threshold voltage within one of a plurality of threshold voltage distributions, wherein one of said threshold voltage distributions is assigned to an erase state and others of said threshold voltage distributions are assigned to program states, respectively, wherein said nonvolatile memory receives said commands and said address during an enable state of said write enable signal and receives said data in response to said clock signal during a disable state of said write enable signal, and wherein in an operation of said program command, said nonvolatile memory controls selection of one word line according to said address received from said central processing unit and brings said threshold voltage of memory cells coupled to said selected word line from the erase state threshold voltage distribution to one of program state threshold voltage distributions corresponding to data to be stored in respective ones of said memory cells.