Patent ID: 8217520

Claim:
A semiconductor package, comprising: a substrate having a first surface and a second surface opposite the first surface, the substrate having a first and second set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of an adhesive; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; a first set of bond wires electrically coupled from the first semiconductor chip to the first set of bond wire studs on the substrate; and a second set of bond wires electrically coupled from the second semiconductor chip to the second set of bond wire studs on the substrate, wherein the adhesive contacts side surfaces of the first and second set of bond wire studs and does not flow over and overlap top surfaces of the set of bond wire studs.