Patent ID: 8354288

Claim:
A method of manufacturing an array substrate, the method comprising: forming a base substrate; forming a first conductive layer on the base substrate; forming a gate line and a gate electrode by patterning the first conductive layer formed on the base substrate; forming a semiconductor layer on the base substrate including the gate line formed thereon; forming a second conductive layer on the semiconductor layer; forming a source electrode and a drain electrode by patterning the second conductive layer formed on the semiconductor layer; forming a passivation layer including a contact hole formed therethrough, the contact hole exposing a portion of the drain electrode; forming a third conductive layer on the passivation layer; and forming a pixel electrode by patterning the third conductive layer formed on the passivation layer, wherein the pixel electrode is electrically connected to the drain electrode through the contact hole, and wherein the first conductive layer and the second conductive layer are patterned using an etchant comprising ammonium persulfate (NH 4 ) 2 S 2 O 8 , an inorganic acid, an acetate salt, a fluorine-containing compound, a sulfonic acid compound, an azole compound, and water.