Patent ID: 8692356

Claim:
An integrated circuit device, comprising: a first metal interconnect layer, METn−1; a first insulating layer over METn−1 a resistive layer of a thin film resistor (TFR) embedded within the first insulating layer; a second metal interconnect layer, METn, over the first insulating layer such that the resistive layer of the TFR is between METn−1 and METn, wherein METn has a slot without conductive layer located over a portion of the resistive layer of the TFR; a second insulating layer over METn; a third metal interconnect layer METn+1 over the second insulating layer; a first VIA extending through the second insulating layer, the slot, and the first insulting layer to connect METn+1 to the resistive layer of the TFR; and a second VIA extending through the second insulating layer to connect METn+1 to METn.