Patent ID: 7675174

Claim:
A semiconductor structure, comprising: a semiconductor substrate having a conductive region therein; a first insulating layer formed over the substrate; a first metal layer formed on top of the first insulating layer; an interconnect structure used to connect the first metal layer to the conductive region of the substrate; a second insulating layer formed on top of the first metal layer; a second metal layer formed on top of the second insulating layer; a third insulating layer formed on top of the second metal layer; a third metal layer formed on top of the third insulating layer; a fourth insulating layer formed on top of the third metal layer; and an upper metal layer formed overlying the fourth insulating layer, the upper metal layer having a thickness that is in excess of two times a thickness of at least one of the underlying metal layers, wherein said upper metal layer includes a first sublayer and a second sublayer, the first sublayer being a first metal and the second sublayer being a second metal, and having therebetween a layer which is very thin relative to the first and second metal sublayers, the thin layer being a different material from the first and second metal and having a different conductivity than the first and second metals.