Patent ID: 7786477

Claim:
A semiconductor device for determining an overlay error on a semiconductor substrate comprising a first transistor and a second transistor; the first transistor comprising a first and a second diffusion region associated with a first gate; the second transistor comprising a third and a fourth diffusion region associated with a second gate; the first and second gate each having a non-uniform shape, and the second gate being oriented with respect to an orientation of the first gate such that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on the device parameter of the first transistor, wherein the first gate comprises a first gate portion and a second gate portion, the first gate portion and the second gate portion extending parallel to each other in a first direction, the gate length of the first gate portion being different from the gate length of the second gate portion, wherein the second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction, and wherein the second gate comprises a third gate portion and a fourth gate portion, the third gate portion and the fourth gate portion extending parallel to each other in the first direction, the gate length of the third gate portion being different from the gate length of the fourth gate portion, and wherein the first gate portion of the first gate has a side wall substantially in-line with a side wall of the second gate portion of the first gate, and the third gate portion of the second gate has a side wall substantially in line with a side wall of the fourth gate portion of the second gate.