Patent ID: 8913441

Claim:
A glitch circuit for filtering glitches from a received input clock, the glitch circuit comprising: an SR flip-flop having a set input, a reset input, and an output, wherein the received input clock is operatively coupled to the set and reset inputs of the flip-flop, respectively; a configurable delay circuit having a delay circuit input configured to receive an input signal, and having a delay circuit output configured to provide a delayed signal; the configurable delay circuit having a plurality of switchable taps, each tap configured to provide an increment of delay to the input signal so as to delay the input signal by a selected delay period; the delay circuit input operatively coupled to an output of the flip-flop, and the delay circuit output operatively coupled to the inputs of the flip-flop; and wherein the glitch circuit captures a first signal transition of the input clock and blocks all other signal transitions from propagating through the flip-flop during the selected delay period so as to provide a glitch-free output clock at the output of the flip-flop.