Patent ID: 8914688

Claim:
A method comprising: initiating a first built-in self-test (BIST) sequence on a plurality of integrated circuit memory arrays having a common BIST control unit; incrementing each address for each said integrated circuit memory array in common from a common starting point, using said common BIST control unit; receiving, by said common BIST control unit from each said integrated circuit memory array, a signal indicating a maximum valid address in said integrated circuit memory array is reached, to receive a plurality of maximum valid addresses; recording, in said common BIST control unit, said maximum valid addresses; determining a single relatively highest maximum valid address from said plurality of maximum valid addresses, using said common BIST control unit; engaging, by said common BIST control unit, a first mode in each said integrated circuit memory array having reached said maximum valid address, said first mode preventing BIST testing; initiating a second BIST sequence from said common BIST control unit on said plurality of integrated circuit memory arrays having said common BIST control unit, based on said common BIST control unit having received said signal indicating a maximum valid address in said integrated circuit memory array is reached from all said integrated circuit memory arrays connected to said common BIST control unit; decrementing an address count from said single relatively highest maximum valid address, using said common BIST control unit; and disengaging, by said common BIST control unit, said first mode for each said integrated circuit memory array as said address count reaches each of said maximum valid addresses of each of said integrated circuit memory arrays during said decrementing.