Patent ID: 8402232

Claim:
A hardware memory control unit comprising: a register block comprising: a first access count register for storing an access count for a first hardware memory segment; a first low threshold register for storing a low threshold for the first hardware memory segment; a first high threshold register for storing a high threshold for the first hardware memory segment; and a status register for storing a current status for the first hardware memory segment, wherein the current status stored in the status register comprises: a trap bit to indicate whether a trap is generated; a low bit to indicate whether a last event is the access count stored in the first access count register is less than the low threshold stored in the first low threshold register; a high bit to indicate whether a last event is the access count stored in the first access count register is greater than the high threshold stored in the first high threshold register; a running bit to indicate whether the access count in the first access count register is currently incrementing; and a mode bit to indicate a power saving mode of the first hardware memory segment; and hardware logic configured to: increment the access count stored in the first access count register for each memory access to the first hardware memory segment performed during a first predefined duration of time; and at the end of the first predefined duration of time: generate the trap when the access count stored in the first access count register is less than the low threshold stored in the first low threshold register; and generate the trap when the access count stored in the first access count register is greater than the high threshold stored in the first high threshold register, wherein the power saving mode of the first hardware memory segment is modified when the trap is generated.