Patent ID: 8189391

Claim:
A non-volatile semiconductor storage device comprising: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of a respective one of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor; and a control circuit configured to perform erase operation to erase data from the memory cells, the memory string comprising: a first semiconductor layer having a columnar portion extending in a vertical direction to a substrate; an electric charge storage layer formed to surround the first semiconductor layer; and a first conductive layer surrounding the electric charge storage layer and extending parallel to the substrate, the first selection transistor comprising: a second semiconductor layer in contact with a top or bottom surface of the columnar portion and extending in the vertical direction to the substrate; a first gate insulation layer formed to surround the second semiconductor layer; and a second conductive layer surrounding the first gate insulation layer and extending parallel to the substrate, the control circuit being configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference, the certain potential difference being a potential difference that erases data from the memory cells, in the erase operation, the control circuit raising the first wiring to a first voltage and the second wiring to a second voltage so that the certain potential difference is maintained therebetween, and then starting boosting the first wiring from the first voltage while setting the second wiring in a floating state.