Patent ID: 7237172

Claim:
A content addressable memory circuit comprising: a bank of memory cells; and an error detection and correction circuit connected to said bank, said error detection and correction circuit adapted to sequentially test said memory cells for errors, detecting errors within said cells and correcting any detected errors, said error detection and correction circuit comprises: an address generator for generating a test address for a memory cell to be tested, said address generator being connected to said bank, a state machine connected to said address generator, said state machine outputting a signal to said address generator when it is time to generate the test address, said state machine providing access signals to said bank when it is time to access the memory cell to be tested, and a test circuit connected to said bank, said test circuit inputting a content of said memory cell to be tested, determining whether the input content contains an error, and correcting the error if it is determined that said input content contains the error, wherein said test circuit uses additional memory bits associated with the memory cell to be tested to determine if the cell has the error and to correct the error.