Patent ID: 7834902

Claim:
A pixel clock creation device, comprising: a high frequency clock creation unit creating a high frequency clock; a detection unit detecting a scanning time needed to scan a predetermined scanning length, in accuracy of half a period of the high frequency clock, and outputting a detection value indicating the detected scanning time, wherein the detection unit comprises: a counter unit outputting a count value which is counted up in rising of the high frequency clock, a first state detection unit detecting a state of the high frequency clock at a time of transition of a first horizontal sync signal indicating a time that a start point of the scanning length is scanned, the state of the high frequency clock being either high or low, a second state detection unit detecting a state of the high frequency clock at a time of transition of a second horizontal sync signal indicating a time that an end point of the scanning length is scanned, the state of the high frequency clock being either high or low, and a detection data creation unit creating the detection value based on the count value of the counter unit, a state signal outputted by the first state detection unit, and a state signal outputted by the second state detection unit; a comparison result creation unit comparing the detection value and a predetermined target value, and outputting a comparison result; a phase data creation unit creating a phase data based on the comparison result; and a pixel clock creation unit creating a pixel clock whose phase is controlled based on both the high frequency clock and the phase data.