Patent ID: 7094652

Claim:
A method of manufacturing a semiconductor device, comprising: forming a gate of a first transistor and a gate of a second transistor on a semiconductor substrate; forming a first diffusion layer of a second conductivity type having a low impurity concentration in said semiconductor substrate with the gate of said first transistor used as a mask; forming a second diffusion layer of a first conductivity type having a low impurity concentration in said semiconductor substrate with the gate of said second transistor used as a mask; forming gate side walls of the same thickness to surround the gates of said first transistor and said second transistor, respectively; forming a first diffusion layer of a second conductivity type having a high impurity concentration, which is positioned adjacent to said first diffusion layer having a low impurity concentration, within said semiconductor substrate, with the gate side wall of said first transistor used as a mask; depositing a second side wall material and a mask side wall material differing from the second side wall material over said first side walls and gates of the transistors; forming a mask side wall on the side surface of the gate side wall of said second transistor through a second side wall by selectively etching said third side wall material by means of an anisotropic etching using said second side wall material as an etching stopper; forming a second diffusion layer of the first conductivity type having a high impurity concentration, which is positioned adjacent to said second diffusion layer having a low impurity concentration, within said semiconductor substrate, with the mask side wall used as a mask; and removing said mask side wall.