Patent ID: 8866256

Claim:
An apparatus, comprising: a semiconductor substrate; a conductive fuse layer having a bottom surface aligned along a plane substantially parallel to a surface of the semiconductor substrate and having an area tapering along an edge from a first width at a first portion of the area to a second width at a second portion of the area; a first fuse link aligned along the plane and coupled to the edge of the area at the first portion of the area; and a second fuse link aligned along the plane and coupled to the edge of the area at the second portion of the area, the area of the conductive fuse layer tapering from a first width at the first portion to a second width at the second portion, the first fuse link being associated with a current density larger than a current density associated with the second fuse link based on the tapering of the area, the first fuse link sequentially blowing before the second fuse link based on the current density associated with the first fuse link, and the conductive fuse layer, the first fuse link and the second fuse link are formed of a same material.