Patent ID: 6937080

Claim:
A current-controlled metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising: a clocked latch including: first and second n-channel MOSFETs having their source terminals connected together, their gate terminals coupled to receive a first pair of differential logic signals, respectively, and their drain terminals connected to a true output and a complementary output, respectively; a first clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the first and second n-channel MOSFETs, a gate terminal coupled to receive a first clock signal CK, and a source terminal; third and fourth n-channel MOSFETs having their source terminals coupled together, their gate terminals and drain terminals respectively cross-coupled to the true output and the complementary output; a second clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the third and fourth n-channel MOSFETs, a gate terminal coupled to receive a second clock signal CKB, and a source terminal; first and second resistive elements respectively coupling the true output and the complementary output to a logic high level; and a first current-source n-channel MOSFET coupled between the source terminals of the first and second clocked n-channel MOSFETs and a logic low level; and a level shifter coupled to the first clocked latch, the level shifter including: fifth and sixth n-channel MOSFETs having their source terminals coupled together, their gate terminals respectively coupled to receive a second pair of differential logic signals being the true output and the complementary output of the first clocked latch, and their drain terminals coupled to a common node via a respective pair of resistive loads; a level shift resistive element coupled between the common node and the logic high level; and a second current-source n-channel MOSFET coupled between the source terminals of the fifth and sixth n-channel MOSFETs and the logic low level, wherein, the drain terminal of the fifth n-channel MOSFET provides a true output of the level shifter and the drain terminal of the sixth n-channel MOSFET provides the complementary output of the level shifter.