Patent ID: 7589386

Claim:
A semiconductor device in which a first field effect transistor having a first conductivity type channel and a second field effect transistor having a second conductivity type channel are formed on a surface layer of a semiconductor substrate, characterized in that: said first field effect transistor has a first conductivity type channel layer, a first conductivity type source region formed on one end of said first conductivity type channel layer, a first conductivity type drain region formed on the other end of said first conductivity type channel layer, and a gate region formed between said first conductivity type source region and said first conductivity type drain region; said second field effect transistor has a first conductivity type well region comprised of a gate region separated from said first field effect transistor and a second conductivity type channel layer in said first conductivity type well region, a second conductivity type source region formed on one end of said second conductivity type channel layer and a second conductivity type drain region formed on the other end of said second conductivity type channel layer; a first wire connects one end of said second conductivity type channel layer to said first conductivity type drain region; a second wire connects the other end of said second conductivity type channel layer to a first power source; a third wire connects said first conductivity type well region to said gate region of said first field effect transistor; and wherein said first wire corresponds to a combined output of said first conductivity type channel and said second conductivity type channel, and wherein said first conductivity type well region and said second conductivity type channel layer collectively have an impurity profile that is formed such that the one end of said second conductivity type channel layer connected to the first wire is depleted to enter a pinch-off state by reverse bias between said first conductivity type well region and said second conductivity type channel layer when a voltage level sufficient to turn on the first field effect transistor is present on the third wire and applied to the gate of the second field effect transistor.