Patent ID: 7548071

Claim:
A system for reflectometry testing of a signal path, comprising: a system clock configured to output a clock at a chip rate; a pseudo-noise generator coupled to the system clock and configured to output a probe sequence of pseudo-random chips at the chip rate, wherein the sequence repeats every L chips; a sliding pseudo-noise generator coupled to the system clock and configured to output a reference sequence at the chip rate, wherein the reference sequence repeats every L+1 chips and the reference sequence is equal to the probe sequence over a continuous segment of length L chips; a signal path interface coupled to the pseudo-noise generator and configured to inject the probe sequence into the signal path and obtain a resulting response signal from the signal path; a correlator coupled to the signal path interface and the sliding pseudo-noise generator and configured to determine a correlation of the response signal and the reference sequence and output samples of the correlation at intervals of L+1 chips; and an estimator coupled to the correlator and configured to estimate a peak correlation delay time from at least two of the samples of the correlation, wherein the peak correlation delay time includes an integer chip number portion and a fractional chip number portion.