Patent ID: 8452943

Claim:
An address generation apparatus for an array processor, the apparatus being connected to a plurality of data storage units for storing data and to an array computing device that receives data from the plurality of data storage units to perform computation thereon, the apparatus comprising: a base address generation unit that generates a base address for an address issued to the data storage unit; a plurality of base address storage units that temporarily store the base address obtained from the base address generation unit; an address computing unit that performs preset address computation on the base address stored in the base address storage unit; an address transfer unit that transfers the address obtained from the address computing unit to an associated one of the data storage units; and a timing control unit that controls the timing of execution of the address computation by the address computing unit, wherein the timing control unit controls generation of the base address by the base address generation unit through control of one of the plurality of base address storage units, and wherein the base address storage unit issues an interrupt signal to the base address generation unit to discontinue generation of the base address when there is likelihood that the base address storage unit will overflow.