Patent ID: 7757187

Claim:
A method of mapping a system-level description of an integrated circuit, said system-level description comprising a behavioral, RTL or unmapped Boolean network, to a cell-level netlist description of the integrated circuit, said cell-level netlist description comprising a network of interconnected logic components selected from a small library of logic components having no more than 50 unique logic functions, the method comprising the steps of: obtaining the behavioral, RTL or unmapped Boolean network that describes the integrated circuit using a computer system; identifying the small library of logic components having no more than 50 unique logic functions, from which the components of the cell-level netlist description of the integrated circuit will be selected using the computer system, the small library of logic components including a set of complex functions and a set of simple functions, wherein the set of complex functions includes a plurality of non-standard complex Boolean logic functions and wherein substantially all of the plurality of non-standard complex Boolean logic functions each have at least three inputs; and mapping the network using the computer system to the small library of logic functions by directly mapping large functions from the network to different ones of the non-standard complex Boolean logic functions, wherein said direct mapping includes testing said unmapped functions against each complex function in the library using at least one of Boolean factoring and Boolean division, and wherein most of the network is mapped to certain ones of the plurality of non-standard complex Boolean logic functions.