Patent ID: 8547763

Claim:
A memory cell, comprising: a selection transistor formed on a substrate, the selection transistor including: a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region; and an antifuse formed on the substrate, the antifuse including: a first electrode connected to a program word line, and a second electrode connected to the selection transistor; wherein: the second electrode of the antifuse is connected to the first drain region of the selection transistor, and the substrate includes a first portion and a second portion, the first portion of the substrate being adjacent to a side of the first drain region that faces the first source region, the second portion of the substrate being adjacent to a side of the first source region that faces the first drain region, and an impurity concentration of the first portion of the substrate being lower than an impurity concentration of the second portion of the substrate.