Patent ID: 7470578

Claim:
A method of suppressing parasitic device characteristics in a finFET, comprising the steps of: providing a substrate; forming a finFET on said substrate, said finFET including: a source-channel-drain fin including an upper surface; and a gate straddling said source-channel-drain fin so as to define first and second reentrant corners with said upper surface of said fin on corresponding respective opposite sides of said gate; wherein said upper surface has a width extending along each of said first and second reentrant corners; following said forming of the finFET, depositing a layer of a spacer material over said finEET; and removing portions of said layer so as to form a first spacer at said first reentrant corner and a second spacer at said second reentrant corner, each of said first and second spacers having a first end, a second end, and a length extending from said first end to said second end along a corresponding one of said first and second reentrant corners, said length not significantly extending beyond said width of said source-channel-drain fin at said gate.