Patent ID: 7304497

Claim:
A structured application-specific integrated circuit device comprising: a plurality of base semiconductor layers; and a plurality of base metallization layers, wherein said base layers form at least one hard circuit block at a first location, wherein a first portion of a first one of said metallization base layers at said first location is configured as a first global power bus line for said device, wherein a second portion of a second one of said metallization base layers at said first location is configured as a first local power bus line for said at least one hard circuit block, and wherein a third portion of a third one of said base layers is programmable to control the connection between said first portion and said second portion for programmably powering down said at least one hard circuit block, wherein said first one, said second one, and said third one of said base layers are the same metallization base layer, and wherein said third portion includes a programmable metal element between said first and second portions.