Patent ID: 8890596

Claim:
A clock signal generating apparatus, comprising: a first frequency generating circuit for generating a first clock signal having a first oscillation frequency; a second frequency generating circuit for generating a second clock signal having a second oscillation frequency; an output circuit, coupled to the first frequency generating circuit and the second frequency generating circuit, for receiving the first clock signal and the second clock signal, the output circuit including a first output terminal and a second output terminal, the output circuit being arranged to output one of the first and second clock signals as an output signal outputted via the first output terminal and to output the other of the first and second clock signals as an output signal outputted via the second output terminal according to a same oscillation frequency control setting; and a setting signal selection circuit, coupled to the second frequency generating circuit, for selecting one of a first setting signal and a second setting signal according to the oscillation frequency control setting, and outputting a selected setting signal to the second frequency generating circuit for adjusting the second frequency generating circuit.