Patent ID: 6952480

Claim:
An encryption system for the transmission of information encoded in a format using logic level transitions to derive the system clock, the system comprising; a frame generator having a first input to accept information to be transmitted, said frame generator organizing the information into frames including both the information and system overhead, said frame generator having an output to provide frames of information to be transmitted, said frame generator for dividing each frame into time multiplexed sections including a first frame period including information, and a second frame period including overhead, said frame generator having a second output to provide timing information regarding the occurrence of the first and second frame periods; and a self-synchronous scrambling circuit having a first input operatively connected to the output of said frame generator, said scrambling circuit having a second input operatively connected to second output of said frame generator, said scrambling circuit selectively scrambling each frame in response to the received frame period timing information by encrypting the information section of the frame, and selectively encrypting the overhead section of the frame.