Patent ID: 7329911

Claim:
A semiconductor device comprising: an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate, and a gate electrode formed on the gate insulating film, wherein a depletion ratio in a gate electrode of the anti-fuse portion is different from a depletion ratio in a gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion; and wherein the semiconductor substrate comprises an element isolation region, and an element forming region of the anti-fuse portion and an element forming region of the memory cell portion isolated respectively by the element isolation region; a gate electrode formed on each of the element forming regions via a gate insulating film; insulation side wall portions integrally formed along opposite sides of each gate electrode disposed in a height direction from a flat portion of a boundary face between the gate insulating film and the semiconductor substrate; and double insulation films comprising a first side insulation film formed like an L-shape and a second side insulation film, in which both the first and second side insulation films are formed respectively on opposite sides along the side wall portion from the flat portion of the gate insulating film.