Patent ID: 8410618

Claim:
A microelectronic assembly, comprising: a semiconductor chip having a first face, a second face, and a plurality of chip contacts exposed at the first face; a substrate juxtaposed with one of the first or second faces, the substrate having a plurality of substrate contacts exposed at a face of the substrate; and a first electrically conductive bond wire and a second electrically conductive bond wire, the first and second bond wires electrically connecting a first chip contact of the plurality of chip contacts with a corresponding first substrate contact of the plurality of substrate contacts and providing parallel conductive paths between the first chip contact and the first substrate contact, the first bond wire having a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact, the second bond wire being metallurgically joined to at least one of the first or second ends of the first bond wire, wherein the second bond wire is metallurgically joined to each of the first and second ends of the first bond wire.