Patent ID: 6909389

Claim:
An electrical circuit having an N-bit input, for N an integer of at least 2, and an output including an electrical parameter, said electrical circuit comprising: N+1 cells for generating a relatively fixed output of the parameter; N+1 trim cells, each corresponding to one of the N+1 cells, for generating a trimmable output of the parameter, each trim cell adapted to operate in one of two modes, generating a trimmable output of a first magnitude of the parameter in the first mode and generating a trimmable output of twice the first magnitude of the parameter in a second mode; N+1 combiners for combining the value of the parameter from a cell with the value of the parameter from a corresponding trim cell to form a combined parameter output; a first bus combining combined parameter outputs directed thereto to form a first bus parameter value; a second bus combining combined parameter outputs directed thereto to form a second bus parameter value; N+1 switches for directing the combined parameter output from each combiner to one of the first bus and the second bus; and an additional switch for decoupling one of the combiners from both the first bus and the second bus.