Patent ID: 8164961

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell which stores data by a difference in threshold voltage; latch circuits which store a plurality of read data obtained by performing a read operation on the memory cell twice or more under the same read conditions; and an arithmetic operation circuit which takes majority decision of said plurality of data stored in the latch circuits and decides the data determined by the majority decision as data stored in the memory cell, wherein the read operation which is performed twice or more is executed 2n+1 times, and the arithmetic operation circuit decides identical data stored in the latch circuits and read n+1 times or more in the 2n+1 read operations as the data stored in the memory cell (where n is an integer greater than or equal to 1), and wherein, when the identical data stored in the latch circuits is read n+1 times, subsequent read operations are not executed, and the arithmetic operation circuit decides the identical data as the data stored in the memory cell.