Patent ID: 8134855

Claim:
A ferroelectric memory comprising: a memory cell array comprising a memory cell, the memory cell comprising a ferroelectric capacitor and a transistor; a plate-line configured to transmit a plate-line voltage to the ferroelectric capacitor in order to write and read data; a pair of bit-lines configured to transmit a signal charge from the memory cell; a sense amplifier circuit configured to sense, to compare, and to amplify a potential difference between the bit-line pair; a bit-line driver circuit configured to drive the bit-line pair and a plate-line driver circuit configured to drive the plate-line; and a bit-line precharge circuit and a plate-line precharge circuit configured to switch between a state where either a bit-line of the bit-line pair is precharged to a first bit-line precharge potential or the plate-line is precharged to a first plate-line precharge potential and a state where either the bit-line is electrically floating and isolated from the first bit-line precharge potential or the plate-line is electrically floating and isolated from the first plate-line precharge potential, the bit-line driver circuit, the plate-line driver circuit, the bit-line precharge circuit, and the plate-line precharge circuit being configured to apply the first bit-line precharge potential to the bit-line of the bit-line pair while applying a second plate-line voltage to the plate-line in a test mode, and then to switch the bit-line from the first bit-line precharge potential to the floating state and to increase the plate-line voltage from the second plate-line voltage to a first plate-line voltage in order to read data from the memory cell, the second plate-line voltage is set to a value in a manner that a polarization state becomes similar to the state where the ferroelectric capacitor is imprinted.