Patent ID: 7456066

Claim:
A method for forming multiple width offset spacers adjacent respective MOSFET gate structures comprising the steps of: providing a semiconductor substrate comprising at least two gate structures; growing a silicon oxide layer having a respective differential thickness over the at least two gate structures; forming a dielectric layer on the silicon oxide layer having an etching selectivity with respect to the silicon oxide layer; forming offset spacers having a differential thickness comprising the dielectric layer and the silicon oxide layer adjacent either side of the at least two respective gate structures; and, carrying out an ion implant process adjacent the offset spacers to form doped regions in the semiconductor substrate to form at least two MOSFET devices, wherein the differential thickness comprises a relatively thicker and a relatively thinner silicon oxide layer, the relatively thinner silicon oxide layer is formed in a digital MOSFET device, a logic MOSFET device or an PMOS SRAM cell MOSFET device, and the relatively thicker silicon oxide layer is formed in an analog MOSFET device, an SRAM MOSFET device, or a NMOS SRAM cell MOSFET device.