Patent ID: 8775977

Claim:
A method for decomposing a design layout for a semiconductor device into a plurality of photomasks that may be combined to form an exposure pattern using DPL (double pattern lithography) techniques, said method comprising: identifying a design layout of an exposure pattern for a semiconductor device, to be decomposed; generating an electronic file of said design layout on a non-transitory computer readable electronic storage medium using a computer at a design level, said electronic file of said design layout including first features each having a first marking designating said first features to be formed on a first photomask, second features each having a second marking designating said second features to be formed on a second photomask, and stitching locations each having a stitching marking designating each said stitching location as a location at which said first and second features meet to form a continuous device feature of said design layout wherein; said semiconductor device comprises an integrated circuit device and said providing said electronic file of said design layout includes marking said design layout according to criteria other than critical dimension, including: marking similarly sized features with the same marking; marking features that substantially determine device speed, with the same marking; providing said non-transitory computer readable electronic storage medium to a mask foundry; and said mask foundry decomposing said design layout based on said electronic file, into a plurality of layouts, and forming a photomask from each said layout.