Patent ID: 8214597

Claim:
An apparatus comprising: a cache configured to store a plurality of old lines, each of said old lines comprising a plurality of old instructions; a buffer (i) sized to hold a single line at a time and (ii) configured to store a first new line fetched-ahead from a memory in response to a first read command, said first new line comprising a plurality of new instructions; a first circuit (i) coupled unidirectionally to each of said buffer, said cache and said memory and (ii) configured to receive said first new line from said buffer in response to a second read command that identifies a particular one of said new instructions stored in said buffer; a second circuit (i) coupled unidirectionally to each of said first circuit, said cache and a processor and (ii) configured to (a) receive said first new line from said first circuit, (b) multiplex said first new line to select said particular new instruction in response to a control signal and (c) present said particular new instruction alone to said processor, wherein said cache is further configured to (i) receive said first new line from said first circuit and (ii) overwrite a particular one of said old lines with said first new line; and a third circuit configured to generate said control signal that identifies said particular new instruction in response to a cache miss and a buffer hit of said second read command.