Patent ID: 7580492

Claim:
A clock recovery apparatus comprising: an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein said early/late voter passes an Up/Down signal to a phase interpolator for maintaining a clock signal; a frequency accumulator and rate multiplier for generating further signals which are summed with an output signal of the early/late voter to provide the Up/Down signal to the phase interpolator, wherein said frequency accumulator and rate multiplier is responsive to frequency changes in an input signal; the frequency accumulator and rate multiplier comprising a binary counter and a plurality of logic gates, the binary counter is operable to provide a plurality of bits of counter output that are combined in the logic gates to generate an output pulse train constituting said further signals; wherein said phase interpolator acts on said Up/Down signals to adjust the clock signal by stepping the clock signal forward or backward, so that said sampling point can be advanced or retarded and wherein the plurality of logic gates are arranged in a two-tier structure, each tier comprising a plurality of logic gates; the first tier of logic gates operable to logically combine the plurality of bits of counter output to provide a series of different pulse trains; and the second tier of logic gates, dependent upon a control word applied thereto, operable to selectively combine the series of different pulse trains to generate the output pulse train constituting said further signals.