Patent ID: 7434039

Claim:
A processor comprising: an activation controller; a pluralilty of hardware contexts, each of the hardware contexts associated with a predetermined first event and a predetermined second event and comprising: (1) a program counter that stores a first memory address; (2) a first programmable event control register associated with a first event, the first programmable event control register programmed to designate that a first sum of the first memory address and a first offset is to be stored in the program counter when said first event occurs; (3) a second programmable event control register associated with a second event, the second programmable event control register programmed to designate that a second sum of the first memory address and a second offset is to be stored in the program counter when said second event occurs; and (4) the activation controller for responding to said first event and said second event by: (4.1) respectively storing the first sum and the second sum into said program counter when said first event and said second event occurs.