Patent ID: 8189423

Claim:
A system comprising: a control unit for performing a series of instructions; a power supply; a plurality of individual arrays of memory cells providing a capacity of 256 Meg and organized into four symmetrically arranged arrays each having a capacity of 64 Meg, each 64 Meg array being divided into two 32 Meg arrays, each 32 Meg array being divided into eight blocks with the blocks organized into four pairs of two blocks each; a plurality of pads located centrally with respect to said array blocks; a plurality of peripheral devices for transferring data between said memory cells and said plurality of pads, said peripheral devices including logic for accessing said memory device by: using a plurality of address bits to select one of the four 32 Meg arrays; using two address bits to select on of the four pairs of blocks; using another one address bit to select one of the blocks in the selected pair; and using additional address bits to address individual rows or columns in said selected block; a plurality of voltage supplies located proximate said plurality of pads for generating a plurality of supply voltages, wherein said plurality of voltage supplies includes a bias generator for supplying a bias voltage to said array blocks, said bias generator including an output status monitor; and a power distribution bus for delivering said plurality of supply voltages to said individual arrays and said plurality of peripheral devices, wherein said plurality of peripheral devices includes a plurality of sense amplifiers positioned between adjacent rows of individual arrays in said array blocks and a plurality of row decoders positioned between adjacent columns of individual arrays in said array blocks, wherein each of said plurality of individual arrays includes digit lines extending therethrough and into said sense amplifiers, and wherein said array blocks include I/O lines running between adjacent rows of individual arrays and through said sense amplifiers, said sense amplifiers including circuits for transferring signals on said I/O lines, wherein said array blocks include data lines running between adjacent columns of individual arrays and through said row decoders to form intersections with said I/O lines, said plurality of peripheral devices including a plurality of multiplexers positioned at certain of said intersections of I/O lines and data lines for transferring signals on said I/O lines to said data lines.