Patent ID: 7808850

Claim:
A semiconductor device, comprising: a storage circuit performing data reading or data writing according to an external control signal in a normal mode, and performing data reading or data writing according to an internal control signal in a first test mode and a second test mode; a self-test circuit generating the internal control signal, test data to be used as write data of the storage circuit and expected value data to be compared with read data of the storage circuit in the first test mode and the second test mode; a first data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a first input/output pad in the normal mode and the second test mode; a first data input circuit obtaining a corresponding part of the write data of the storage circuit via the first input/output pad in the normal mode, and obtaining output data of the first data output circuit via the first input/output pad in the second test mode; a second data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a second input/output pad in the normal mode and the second test mode; a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad in the second test mode; a comparison object selection circuit selecting the read data of the storage circuit in the first test mode, and selecting data including output data of the first data input circuit and output data of the second data input circuit in the second test mode; a judging circuit performing a test judgment by comparing output data of the comparison object selection circuit with the expected value data and outputting a test result signal in the first test mode and the second test mode; and a test result output circuit obtaining the test result signal and outputting the test result signal to an output pad in the first test mode and the second test mode.