Patent ID: 7243240

Claim:
A system for firmware authentication comprising: a first memory having a firmware embedded therein, the firmware including a random value generator unit, a counting unit, a first cryptographic algorithm unit, and a verifying unit; a programmable microprocessor including a second memory having a second cryptographic algorithm unit embedded therein; and a microprocessor coupling the first memory and the programmable microprocessor; wherein the microprocessor runs the random value generator unit to get random values, the firmware has a data synthesizer unit, the microprocessor runs the data synthesizer unit using the random values generated by the random value generator unit as the input values to the data synthesizer unit to get a 16-bit key, which key is processed value, and respectively sends the key to the first and the second cryptographic algorithm units, and the first cryptographic algorithm unit using a processed value of the generated random values to get a first digital signature, the programmable microprocessor runs the second cryptographic algorithm unit which is identical to the first cryptographic algorithm unit using the same processed value of the generated random values to get a second digital signature, then the microprocessor runs the verifying unit to verify whether the first and the second digital signatures are identical to each other to thereby authenticate the firmware, the microprocessor running the counting unit for preventing a closed-loop, wherein the microprocessor increments a number by running the counting unit, if the number is greater than a predetermined value, the microprocessor will be halted, thereby halting the authentication system, if the number is less than the predetermined value, the microprocessor will proceed.