Patent ID: 8135873

Claim:
An information processing device comprising: an address converter comprising a base address register in which is stored an address conversion information including information relating to an address width of a bus that transmits and receives data and an internal memory address of a device, and a conversion circuit that converts, on the basis of the address conversion information stored in the base address register, a Peripheral Component Interconnect (PCI) Express standard bus address of an inputted packet into a non-PCI Express standard bus address; and a packet generator, wherein when a first configuration information, which is based on the PCI Express standard and which includes a device-unique unique address of a first device that is connected to a non-PCI Express standard bus and that has the unique address and that is unaware of the unique address, is stored previously in a storage, the packet generator generates, on the basis of the first configuration information stored in the storage, an address setting configuration write request packet including the unique address that causes the first device to become aware of the unique address, and outputs the address setting configuration write request packet to the address converter, and when a second configuration information which is based on the PCI Express standard and which includes a change information for changing the base address register to a base address register in which is stored a device-unique unique value of a second device that is connected to a non-PCI Express standard bus, the unique value being at least one of an address width or an internal memory address, is stored previously in the storage, the packet generator generates, on the basis of the second configuration information stored in the storage, a change setting configuration write request packet including the change information, and outputs the change setting configuration write request packet to the address converter.