Patent ID: 8412874

Claim:
A data transfer circuit, comprising: an inputter which inputs data having L words (L: integer of 2 or more), each word of which has a first bit width; a first divider which divides each data of preceding M words (M: integer of less than L), out of the data inputted by said inputter, into partial data having a second bit width smaller than the first bit width; a holder which temporarily holds data having N words (N: integer equivalent to L-M) succeeding to the M words, out of the data inputted by said inputter; a second divider which divides each data of the N words held by said holder, into partial data having the second bit width, after completeion of the dividing process of said first divider; and an outputter which outputs the partial data divided by said first divider and the partial data divided by said second divider in a time-division manner.