Patent ID: 7827408

Claim:
A device for authenticated encryption, comprising: a) a first hardware concatenator, having a first input, having a second input, and having an output; b) a second hardware concatenator, having a first input, having a second input, and having an output; c) a first hardware block cipher, having a first input for receiving a cryptographic key, having a second input connected to the output of the first hardware concatenator, and having an output; d) a second hardware block cipher, having a first input for receiving a cryptographic key, having a second input connected to the output of the second hardware concatenator, and having an output; e) a third hardware concatenator, having a first input connected to the output of the first hardware block cipher, having a second input connected to the output of the second hardware block cipher, having a third input, and having an output; f) a fourth hardware concatenator, having a first input connected to the output of the third hardware concatenator, having a second input for receiving a message to be encrypted, having a third input, and having an output; g) a hardware hash engine, having a first input connected to the output of the fourth hardware concatenator, and having an output; h) a filth hardware concatenator, having a first input connected to the output of the hardware hash engine hardware concatenator, having a second input for receiving the message to be encrypted, and having an output; i) a hardware divider, having a first input connected to the output of the filth hardware concatenator, and having an output; j) a sixth hardware concatenator, having a first input, having a second input, and having an output; k) a third hardware block cipher, having a first input for receiving a cryptographic key, having a second input connected to the output of the sixth hardware concatenator, and having an output; l) a hardware combiner, having a first input connected to the output of the hardware divider, having a second input Connected to the output of the third hardware block cipher, and having an output; and m) a seventh hardware concatenator, having a first input connected to the output of the hardware combiner, having a second input, having a third input, and having an output.