Patent ID: 8775901

Claim:
A method of operating a memory system including an array of flash memory cells formed along a plurality of word lines each capable of storing one or more pages of data, the method comprising: receiving a first data page; storing the received first data page in a first buffer; writing the first data page from the first buffer into a corresponding word line of the flash memory; generating a page of parity data for the received first page of data; storing the page of parity data in a second buffer; subsequent to receiving the first data page, sequentially receiving one or more additional pages of data, and for each of additional received page of data; overwriting the preceding page of received data in the first buffer therewith; writing the page of data from the first buffer into a corresponding word line of the flash memory; and updating the page of parity data stored in the second buffer as a function of parity data as previously stored in the second buffer and the additional received page of data; subsequently determining whether the first data page and the additional pages of data were written correctly; and in response to determining that one of the data pages is written incorrectly, determining the correct data for the incorrectly written page based upon the page of parity data and the first and additional data pages as read from the array.