Patent ID: 7634666

Claim:
A crypto-engine for cryptographic processing of data comprising an arithmetic unit operable as a co-processor for a host processor and an interface controller for managing communications between the arithmetic unit and host processor, the arithmetic unit including: a memory unit for storing and loading data, the memory unit including an input switch for selecting input-interim data; a plurality of Static Random Access Memory elements for receiving and storing the input/interim data from the input switch; a plurality of output switches connected to the memory elements; and an address controller for controlling flow of the data through the switches and memory elements a multiplication unit, an addition unit and a sign inversion unit for performing arithmetic operations on said data, the multiplication unit, the addition unit and the sign inversion unit each having an output; and an arithmetic controller for controlling the storing and loading of data by the memory unit and for enabling the multiplication, addition and sign inversion units; wherein the outputs of the multiplication unit, the addition unit and the sign inversion unit are feedback to the arithmetic controller.