Patent ID: 8344444

Claim:
A semiconductor device having a memory cell, wherein the memory cell has: a first well formed in a semiconductor substrate and exhibiting an n-type conductivity; a first gate insulating film formed over the first well; a selection gate electrode formed over the first gate insulating film and including a first conductive film exhibiting a p-type conductivity; a cap insulating film formed over the selection gate electrode; a memory gate electrode formed over one side surface of the selection gate electrode and the cap insulating film, the memory gate electrode including a second conductive film exhibiting a p-type conductivity; a second gate insulating film formed between the selection gate electrode and the memory gate electrode, formed between the cap insulating film and the memory gate electrode, and formed between the memory gate electrode and the semiconductor substrate, the second gate insulating film having a charge storage layer; and a first source region exhibiting a p-type conductivity and a first drain region exhibiting a p-type conductivity, both formed in the first well, wherein the cap insulating film is thicker than the second gate insulating film, wherein the cap insulating film includes silicon nitride, and wherein data of the memory cell is erased by injecting holes into the charge storage layer from the memory gate electrode.