Patent ID: 8010932

Claim:
A design structure in a data format embodied in a machine-readable storage device, wherein the design structure is for designing, manufacturing, or testing an integrated circuit design, the design structure comprising: logic that, when processed by a computer, holds characteristics of a reference clock signal constant across the integrated circuit design, wherein said logic that holds characteristics of the reference clock constant comprises logic that holds a rise time, fall time, rising edge slew rate and falling edge slew rate of the reference clock signal constant; and logic that, when processed by the computer and while characteristics of the reference clock signal are held constant: optimizes sizes of transistors forming a multi-bit register within the integrated circuit design, wherein the register is coupled to receive and buffer functional data from logic in the integrated circuit design in response to a local clock signal, and wherein optimizing sizes of transistors forming the multi-bit register includes individually optimizing each bit within the register, such that corresponding transistors implementing at least two bits within the register are differently sized between the at least two bits; and thereafter, optimizes sizes of transistors forming one or more clock buffers coupled to said reference clock signal, wherein the one or more clock buffers are coupled to provide the local clock signal to the register.