Patent ID: 7342842

Claim:
A memory cell array comprising: a plurality of memory cells, including a first memory cell and a second memory cell, wherein each memory cell of the plurality of memory cells includes an associated transistor having a source region, a drain region, an electrically floating body region disposed therebetween, and a gate disposed over the electrically floating body region, and wherein each memory cell further includes a charge in the body region of the associated transistor which varies with time and a first data state representative of a first charge provided in the body region of the associated transistor, and a second data state representative of a second charge in the body region of the associated transistor; and circuitry, coupled to the plurality of memory cells, to sequentially apply first and second electrical signals to first and second memory cells wherein: the first electrical signals are simultaneously applied to the first and second memory cells wherein, in response to the first electrical signals, (i) the first memory cell, which is in the first data state, is refreshed and (ii) the second memory cell, which is in the second data state, maintains the second data state; and the second electrical signals are simultaneously applied to the first and second memory cells wherein, in response to the second electrical signals, (i) the first memory cell, which is in the first data state, maintains the first data state and (ii) the second memory cell, which is in the second data state, is refreshed.