Patent ID: 8051342

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions wherein the plurality of word lines and the plurality of bit lines intersect with each other; a plurality of data bus lines connected to the plurality of bit lines; a plurality of sense amplifiers individually connected to the plurality of data bus lines and configured for detecting memory data stored in corresponding memory cells based on values of currents that are generated in the individual data bus lines in accordance with the memory data, wherein each of the plurality of data bus lines is connected between one of the plurality of bit lines and one of the plurality of sense amplifiers, and wherein the plurality of data bus lines, the plurality of bit lines and the plurality of sense amplifiers are connected such that there is an equal number of each of the plurality of data bus lines, the plurality of bit lines and the plurality of sense amplifiers; switching means provided in the individual data bus lines; and a test circuit having a normal operation state wherein, all the switching means are in a conductive state and having a testing state wherein, in short circuit testing, the switching means are in the conductive state or a non-conductive state in accordance with a test pattern.