Patent ID: 7924050

Claim:
An integrated circuit comprising: at least one data pin connecting the integrated circuit to circuits external to the integrated circuit; a plurality of operational units, each including at least one data input/output for data transfer, an enable input and a clock input, a predetermined enable signal on said enable input placing said operational unit in a normal mode to exchange data via said at least one data input/output and a predetermined not-enable signal on said enable input placing said operational unit in a stall mode not capable of exchanging data via said at least one data input/output; a selection logic including a plurality of enable lines each connected to an enable input of a corresponding operational unit, a plurality of data lines, a data line connected to each of said at least one data input/output of each operational unit and connected to said data pin, and a plurality of clock outputs equal in number to the number of operational units, each clock output connected to a clock input of a corresponding operational unit, said selection logic selectively supplying a key and enabling an operation unit and connecting said data input/output of said enabled operation unit to said at least one data pin, and said selection logic further supplying a cycling clock signal via said corresponding clock output to each operational unit in said normal mode and a non-cycling signal via said corresponding clock output to each operational unit operational unit in said stall mode.