Patent ID: 8571502

Claim:
A clock generation unit comprising: a random modulator configured to receive current clock frequency information corresponding to a current clock frequency, and generate a divisor output based on the received current clock frequency information; a clock divider circuit configured to: receive the divisor output from the random modulator; receive an input clock having an input frequency; and generate a reference clock signal for a phase locked loop (PLL) by dividing the input frequency of the input clock by the divisor, wherein the reference clock signal has the current frequency; and first circuitry configured to: receive updated clock frequency information and a transition value, wherein the updated clock frequency information corresponds to an updated clock frequency that is different from the current clock frequency; adjust the clock frequency information based on the updated clock frequency information; and cause the PLL to retain lock with the reference clock signal by adjusting the clock frequency information according to the transition value when adjusting the clock frequency information based on the updated clock frequency information.