Patent ID: 6974995

Claim:
A semiconductor device including a core and a periphery, the semiconductor device comprising: a plurality of core gate stacks in the core, each of the plurality of core gate stacks including a first polysilicon gate and a WSi layer above the first polysilicon gate, wherein each of the plurality of core gate stacks includes an edge; a plurality of core spacers, each of the plurality of core spacers residing along an edge of the plurality core gate stacks; a plurality of sources in the core, the plurality of sources residing between a portion of the plurality of core gate stacks; and a plurality of periphery gates stacks in the periphery, each of the plurality of periphery gate stacks including a second polysilicon gate and a CoSi layer on the second polysilicon gate; wherein each of the plurality of core gate stacks includes the first polysilicon gate, the WSi layer above the first polysilicon gate, a layer of polysilicon above the WSi later and a capping layer above the layer of polysilicon.