Patent ID: 7038269

Claim:
A semiconductor device comprising: a semiconductor substrate in which a first and a second element active regions are demarcated by means of element isolation structure; the first element active region comprising: a first and a second conductive regions formed at a surface region of the semiconductor substrate; a first electrode formed on the semiconductor substrate between the first and the second conductive regions via a first insulating film forming a transistor with said first and second conductive regions; the second element active region comprising: a third conductive region formed at the surface region of the semiconductor substrate; a fourth conductive region formed to cover over side surfaces to a lower surface of said third conductive region, said fourth conductive region having a conductivity type opposite to that of the third conductive region; a second electrode formed on said third conductive region via a second insulating film, wherein said second electrode serves as a floating gate and is capacitively coupled with said third conductive region serving as a control gate by using said second insulating film serving as a dielectric film; and wherein said first electrode and the second electrode are electrically connected and a third electrode is connected to the semiconductor substrate to apply a predetermined electric potential to the semiconductor substrate in said first element active region to control the threshold voltage of said transistor and to said fourth conductive region.