Patent ID: 7551473

Claim:
An integrated circuit with an array of nonvolatile memory cells, comprising: conductive columns conductively coupled to the nonvolatile memory cells, the conductive columns arranged in parallel and defining a first planar orientation; conductive rows conductively coupled to the nonvolatile memory cells, the conductive rows arranged in parallel and defining a second planar orientation parallel with the first planar orientation; a nonconductive layer separating the conductive columns from diode structures; the diode structures connecting programmable resistive elements with the conductive rows, each including: a first terminal having an exterior surface, and an interior surface connected to at least one of the programmable resistive elements; a second terminal in contact with a junction area on the exterior surface of the first terminal providing a diode junction oriented orthogonal to the first and second planar orientations; and the programmable resistive elements each having: a sidewall surface connected to the interior surface of the first terminal of at least one of the diode structures; and a bottom surface conductively coupled to at least one of the conductive columns.