Patent ID: 8122278

Claim:
A computer implemented method for determining a clock skew value between multiple processors in a multiprocessor computer system (MPG), the MPC including a first processor having a first clock, a first cache, and a first cache control module, the MPC also including a second processor having a second clock, a second cache, and a second cache control module, the method comprising the steps of: first causing the second cache control module to modify data in the second cache by executing program code on the first processor; first measuring a characteristic of the first clock by executing program code on the first processor; first detecting when the data in the second cache has been modified by executing program code on the second processor; second measuring a characteristic of the second clock dependent upon the time the data in the second cache is modified by the second cache control module; first calculating a clock skew value between the first processor and the second processor by executing program code on the MPC to process the characteristics of the first clock and the second clock; third measuring an execution time associated with the first causing step by executing program code on the first processor; storing the execution time together with the associated clock skew value; repeating the first causing step, the first measuring step, the first detecting step, the second measuring step, the first calculating step, the third measuring step, and the storing step N times to generate N execution times and N associated clock skew values, wherein N is an integer; determining minimum execution time from the N execution times; and providing an improved clock skew value that corresponds to the one clock skew value associated with the minimum execution time.