Patent ID: 7810010

Claim:
A decoder, comprising: an add stage configured to provide outputs; a compare stage coupled to the add stage to receive the outputs therefrom, the compare stage configured to determine a difference between a pair of the outputs; a first select stage coupled to the compare stage and the add stage, the first select stage configured to select a first output from the pair of the outputs from the add stage responsive to the difference from the compare stage; an initialization stage coupled to receive the first output selected from the first select stage, the initialization stage configured to store the first output as an initialization value; a second select stage coupled to receive the first output selected from the first select stage and coupled to obtain the initialization value stored from the initialization stage, the second select stage configured to output either the first output selected from the first select stage or the initialization value from the initialization stage as a second output; control circuitry coupled to the initialization stage and the second select stage, the control circuitry configured to control storing the initialization value in the initialization stage and to retrieve the initialization value from the initialization stage for the second select stage, the control circuitry further configured to cause the second select stage to select either the first output selected from the first select stage or the initialization value from the initialization stage as the second output; and the initialization stage in combination with the control circuitry facilitating selection between initialization and non-initialization values for providing the second output from the second select stage.