Patent ID: 7996662

Claim:
A processor comprising: a plurality of storage locations, wherein each of the plurality of storage locations is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for a status/control register (SCR), wherein the value includes at least an exception encoding, and wherein the exception encoding encodes an update to a plurality of exception bits in the SCR, and wherein a first number of bits in the plurality of exception bits is greater than a second number of bits in the exception encoding, and wherein the second number of bits is sufficient to encode each possible combination of one or more exceptions that can occur during execution of an instruction operation, and wherein some combinations of exceptions are not possible, and wherein at least one combination includes at least two exceptions; a decode circuit coupled to the plurality of storage locations, wherein the decode circuit is coupled to receive the exception encoding from a first storage location of the plurality of storage locations responsive to retirement of a first instruction operation assigned to use the first storage location as a destination, and wherein the decode circuit is configured to decode the exception encoding to generate the plurality of exception bits responsive to retirement of the first instruction; and the SCR coupled to the decode circuit, wherein the decode circuit is configured to update the SCR with the plurality of exception bits generated from the exception encoding.