Patent ID: 8391077

Claim:
A nonvolatile semiconductor memory device, comprising: a plurality of planes; a memory cell array provided in each of the plurality of planes and configured as an array of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series; word lines each connected to a control gate electrode of the nonvolatile memory cells; bit lines each connected to a first end of the NAND cell units; a source line connected to second ends of the NAND cell units; and a control circuit configured to control a write operation of charging the bit lines up to a certain voltage value, and then setting data in the nonvolatile memory cells to a certain threshold voltage distribution state, the control circuit including: first transistors, each of the first transistors provided between a first power supply and each of the bit lines and configured to charge the bit line up to the certain voltage value based on a voltage applied to a gate thereof; a second power supply connected to the gate of the first transistor and configured to make the first transistor electrically conductive when charging the bit line in the plane; a signal sending unit configured to output a start signal for starting a bit line charging operation; and a voltage supplying unit configured to apply a voltage to the gates of the first transistors from the second power supplies based on the start signal, the control circuit being configured to be capable of executing an operation of charging the bit lines in the write operation by varying timings of starting charging the bit lines among the plurality of planes, and the signal sending unit being configured to be capable of adjusting whether or not to delay the start signal for each of the plurality of planes.