Patent ID: 6983015

Claim:
A signal processor for splicing a compressed bitstream B 0 to a compressed bitstream A 0 , the bitstreams A 0 and B 0 comprising bits representing one or more pictures the signal processor comprising: a decoder for decoding the bitstreams A 0 and B 0 ; a switch coupled to the decoder for producing a spliced bitstream S, comprising data from bitstream B 0 spliced to data from bitstream A 0 at a splice point; and an encoder for re-encoding the spliced bitstream S to form a re-encoded spliced bitstream C for supply to a downstream decoder having a downstream buffer an occupancy of such a downstream buffer being dependent upon the number of bits with which pictures of the spliced bitstream S are re-encoded by the encoder, wherein the encoder is controlled over a transitional region to allocate a number of bits with which to re-encode a picture of the spliced bitstream S in the transitional region in dependence upon a target downstream buffer occupancy for the bitstream B 0 ) and a downstream buffer occupancy for the re-encoded spliced bitstream C, so that the downstream buffer occupancy of the downstream buffer varies over the transitional region from the downstream buffer occupancy for bitstream A 0 to the downstream buffer occupancy for bitstream B 0 according to a path in which the rate of change of downstream buffer occupancy is limited to a predetermined maximum rate.