Patent ID: 7126379

Claim:
An output device for a static random access memory (SRAM), the SRAM having a plurality of memory cells to store data, the output device comprising: a precharger, having a common output node connected to output nodes of a plurality of memory cells, precharging the common output node to a high potential when one of the memory cells is to be read; a charge and discharge path circuit connected to the common output node, controlling a path output voltage on a path output node of the charge and discharge path circuit in accordance with whether an internal first grounding path is on or not; a voltage hold circuit connected to the path output node and the common output node, controlling a voltage of the common output node in accordance with the path output voltage and an internal second grounding path and disconnecting the second grounding path if the precharger is precharging and an output inverter, generating a phase inverse voltage to output in accordance with the path output voltages, wherein the pre-charger and the voltage hold circuit are commonly connected to a signal that simultaneously causes the pre-charger to precharge said common output node to a high potential and to disconnect said internal second grounding path, and wherein the internal first grounding path includes first and second transistors having control electrodes connected to the common output node for connecting said output path node to respective first and second voltages, and a third transistor connected between said first transistor and said second voltage and controlled by an enable signal to further control connection of the output path node to said second voltage.