Patent ID: 7710789

Claim:
A synchronous memory system comprising: a memory array; a dedicated address bus; a multiplexed address/data bus; a mode select line configured to receive a mode select signal that indicates whether the synchronous memory system should operate in a non-multiplexed mode or a multiplexed mode; and a bus configuration circuit configured to route addresses from the dedicated address bus to the memory array and route data values between the multiplexed address/data bus and the memory array when the mode select signal indicates that the synchronous memory system should operate in the non-multiplexed mode, and wherein the bus configuration circuit is further configured to route addresses from the multiplexed address/data bus to the memory array and route data values between the multiplexed address/data bus and the memory array when the mode select signal indicates that the synchronous memory system should operate in the multiplexed mode, wherein the bus configuration circuit comprises: a first multiplexer configured to route addresses from either the dedicated address bus or the multiplexed address/data bus in response to the mode select signal; and a first storage device configured to store addresses routed by the first multiplexer in synchronism with a clock signal.