Patent ID: 7831765

Claim:
A system comprising: a content addressable memory (CAM) device coupled with a processor, the CAM comprising: a CAM block having a plurality of CAM slices, wherein each of the plurality of CAM slices comprises: a plurality of memory storage locations for storing data to be matched with a search word, and an integral priority encoder for determining a highest priority match address for those storage locations of a CAM slice which match a search word, wherein the integral priority encoder is a programmable priority encoder coupled to the plurality of memory storage locations and consists of: an address program register; a slice priority encoder circuit coupled to the address program register; and a programmable priority indicator block coupled to the slice priority encoder circuit, wherein the address program register, the slice priority encoder circuit, and the programmable priority indicator block are encompassed within the same CAM slice and the programmable priority indicator block is used to set a priority level for each memory storage location in the plurality of memory storage locations within the CAM slice; and a block level priority encoder for receiving input from each of the integral priority encoders of the plurality of CAM slices for determining a highest priority match address for the storage locations within the CAM block.