Patent ID: 7564263

Claim:
A high speed logic signal level shifter comprising: a logic signal buffer having first and second outputs, wherein the logic signal buffer receives an input signal and generates a first set of current pulses, the logic signal buffer generates a second set of current pulses when the input signal transitions from a first state to a second state; a binary flip-flop circuit coupled to the logic signal buffer comprising a first inverter and a first NAND gate connected in a feedback loop so an output of the first inverter connects directly to an input of the first NAND gate, and an output of the first NAND gate connects directly to an input of the first inverter; a first coupling capacitor directly attached to the first output of the logic signal buffer and to the output of the second inverter of the binary flip-flop circuit, the first coupling capacitor forcing a change of state of the binary flip flop based on one of the first set of current pulses and the second set of current pulses generated by the logic signal buffer; and a second coupling capacitor directly attached to the second output of the logic signal buffer and to the output of the first inverter of the binary flip-flop circuit, the second coupling capacitor forcing a change of state of the binary flip flop based on one of the first set of current pulses and the second set of current pulses generated by the logic signal buffer; a reset signal circuit for setting the binary flip-flop to a known state with a reset signal; and a DC coupled level translator for connecting the reset signal circuit to the binary flip-flop circuit; wherein the logic signal buffer has a peak-to-peak output voltage approximately equal to an input signal swing of the binary flip-flop.