Patent ID: 7902033

Claim:
A method of forming a backend capacitor for an integrated circuit, the method comprising: forming a plurality of holes within a non-conducting volume of material formed over an underlying circuit metal layer of the integrated circuit; depositing multiple layers of metal over the non-conducting volume of material and within the plurality of holes the multiple layers of metal including at least a top electrode layer, a middle electrode layer and a bottom electrode layer, with at least the bottom electrode layer in contact with a portion of the circuit metal layer; alternately depositing multiple layers of dielectric over the non-conducting volume and within the plurality of holes, between the multiple layers of metal; forming a middle electrode contact opening through the top electrode layer, and a bottom electrode contact opening through the top electrode layer and the middle electrode layer; and depositing a layer of electrode contact material over the top electrode layer and within the bottom electrode contact opening and the middle electrode contact opening, and patterning the layer of electrode contact material to form a top electrode contact in contact with the top electrode layer, a middle electrode contact coupled to an exposed portion of the middle electrode layer in the middle electrode contact opening, and a bottom electrode contact coupled to the bottom electrode layer through the bottom electrode opening and the portion of the circuit metal layer.