Patent ID: 7132726

Claim:
An integrated semiconductor circuit comprising: a first and a second portion of a substrate, in which a power semiconductor circuit structure and a logic circuit structure are respectively formed; an intermediate oxide layer, which insulates portions and regions which are not to be contact-connected, being formed over the power semiconductor circuit structure and the logic circuit structure; and a metallization for the electrical connection of contact regions and electrode portions the power semiconductor circuit structure and of the logic circuit structure to one another and to other contact regions of the integrated semiconductor circuit being formed above the intermediate oxide layer; wherein the metallization has a power metal layer and an in relative terms thinner logic metal layer, which two metal layers are located directly above one another without an intermetal dielectric between them only in the first portion above the power semiconductor circuit structure in the order of the power metal layer as the first metal layer on the intermediate oxide layer, on the electrode portions, and on the contact regions of the power semiconductor circuit structure and the logic metal layer as the second metal layer on the power metal layer and the intermediate oxide layer, and an uninterrupted conductive barrier layer is located at least between the power metal layer and the intermediate oxide layer and between the power metal layer and the contact regions and electrode portions of the power semiconductor circuit structure which the power metal layer contact-connects.