Patent ID: 8850103

Claim:
A physical NAND flash memory logical unit comprising: a plurality of memory cells that are programmable and erasable; a control circuit configured to respond to a plurality of commands including at least read commands, program commands, and erase commands that are targeted at the plurality of memory cells; a communication bus interface communicatively coupled to the control circuit for providing read, program, and erase commands to the control circuit from an external command source; and wherein the control circuit comprises: a plurality of registers comprising an internal data register, an internal address register, an external data register, an external address register, a supplemental data register, and a supplemental address register; a command circuit for responding to the plurality of commands by controlling the plurality of registers; wherein the supplemental data register and supplemental address register are used to enable in-progress erase and program commands to be suspended in order to process a later read command and to resume a suspended erase or program command; wherein the internal data register is a first internal data register, and the internal address register is a first internal address register, wherein the first internal data register and the first internal address register are dedicated to non-read commands; and wherein the supplemental data register is a second internal data register, and the supplemental address register is a second internal address register, wherein the second internal data register and the second internal address register are dedicated to read commands.