Patent ID: 8546256

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming an interlayer insulating layer on a semiconductor substrate; forming an insulating interlayer pattern and a semiconductor substrate pattern by sequentially etching the interlayer insulating layer and the semiconductor substrate, the insulating interlayer pattern and the semiconductor substrate pattern having a via hole exposing side walls of the insulating interlayer pattern and side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the via hole having an impurity layer pattern; treating an upper surface and the side walls of the insulating interlayer pattern exposed by the via hole, the treated upper surface and side walls of the insulating interlayer pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern and the hydrophobic side walls of the insulating interlayer pattern exposed by the via hole; and filling a conductive layer pattern into the via hole and over the first insulating layer pattern.