Patent ID: 8081522

Claim:
A page buffer circuit for a non-volatile semiconductor memory device which is coupled to a non-volatile memory cell array and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory cell array, comprising: at least one latch circuit including a bit line selector, a page buffer unit circuit including a first latch and a second latch, and a third latch, set up for a plurality of bit lines, wherein the bit line selector selects one of the plurality of bit lines and couples it to the page buffer unit circuit; and a control circuit, wherein the control circuit controls so that the first latch temporally stores the data which is read out from the memory cell of the selected bit line, and then outputs the data through the second latch or the third latch; on the other hand, the first latch temporally stores the programming data inputted through the second latch or the third latch, and after that outputs it to the memory cell of the selected bit line for programming.