Patent ID: 8587987

Claim:
A semiconductor memory, comprising: a memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, and an amplification transistor having a gate connected to the connection node, a source connected to a reference voltage line, and a drain connected to a read line; a sense amplifier to determine a logic held in the memory cell by receiving a voltage of the read line varied with a voltage generated in the connection node by resistance dividing between a source/drain resistance of the selection transistor and the resistance variable element, the selection transistor receiving a read control voltage at the gate thereof; a control circuit to set a word line connected to the gate of the selection transistor to the read control voltage in a read operation, set the first voltage line to a high-level voltage, and set the second voltage line to a low-level voltage; and a pre-charge circuit to temporally supply a pre-charge voltage to the read line before the word line is set to the read control voltage in the read operation.