Patent ID: 6847581

Claim:
An integrated circuit, comprising: a connection configured to connect to an externally applied control clock; a processing circuit having an output, and at least a first input and a second input; a first receiver circuit connected upstream from said first input, said first receiver circuit being disconnectable from a power supply using a mode signal; a second receiver circuit connected upstream from said second input, said second receiver circuit being disconnectable from the power supply using the mode signal; and a multiplex circuit having inputs; said output of said processing circuit and said connection being connected to said inputs of said multiplex circuit; and said multiplex circuit being controlled by a mode signal; said first input connected to said connection for receiving at least a first control clock signal derived from said control clock; said second input connected to said connection for receiving at least a second control clock signal derived from said control clock; said first control clock signal and said second control clock signal being shifted in phase with respect to one another; said output being configured to output a third clock signal generated from said first clock signal and said second clock signal; said third clock signal being at a higher frequency than a frequency of said control clock; said processing circuit being activated in a test mode of the integrated circuit for testing a functional capability of the integrated circuit; said third clock signal for controlling the integrated circuit in said test mode; said processing circuit being deactivated during normal operation of the integrated circuit; and said connection also being configured to connect to a further control clock for controlling the integrated circuit during the normal operation.