Patent ID: 7492200

Claim:
A delayed locked loop (DLL) circuit comprising: a delay line including a plurality of delay elements, and configured to delay an internal clock signal generated by buffering external clock signals by a first delay period; an internal delay configured to delay an output signal of the delay line by a second delay period determined by modeling delay elements contained in a DRAM, and generate a feedback clock signal; a phase detector configured to generate an enable signal enabled when a phase difference between the feedback clock signal and a reference clock signal is contained in a predetermined period, and output the enable signal; a delay-period controller configured to generate in response to the enable signal first and second control signals for adjusting a counter output signal corresponding to at least one delay element selected from among the delay elements; a counter configured to receive the first and second control signals, and generate a counter output signal corresponding to the at least one delay element; and a decoder configured to decode the counter output signal, and generate a decoding signal, wherein the decoding signal indicates an enable state of the at least one delay element and adjusts the first delay period, wherein the delay-period controller includes a setup signal generator for receiving the enable signal and a clock signal, and generating first, second, and third setup signals, a start-signal generator for receiving the first, second, and third setup signals, and generating a start signal, a clock signal transmitter configured to transmit the clock signal to the setup signal generator, in response to the start signal and a control signal generator configured to generate first and second control signals, in response to the start signal and the second and third setup signals.