Patent ID: 7143373

Claim:
A computer implemented method for evaluating an assertion expression about a circuit design, the assertion expression having a hierarchy of subexpressions, the hierarchy having a plurality of leaf subexpressions, at least one intermediate subexpression each expressing a portion of the assertion expression in terms of at least one member of the group consisting of the leaf subexpressions and other intermediate subexpressions, and a root expression representing the entire assertion expression in terms of at least one member of the group consisting of the leaf subexpressions and the intermediate subexpressions, for use with a source indicating the status of each binary signal affecting the assertion expression on each of a plurality of clock ticks in an evaluation period, comprising the steps of: evaluating the assertion expression against the binary signals from the source, for a subject assertion attempt beginning within the evaluation period; and reporting status information of at least one of the intermediate subexpressions.