Patent ID: 8508394

Claim:
A semiconductor integrated circuit comprising, in a semiconductor chip, an A/D converter that includes a sample and hold circuit and an A/D conversion circuit, and a central processing unit, wherein analog input signals can be supplied from the sample and hold circuit during a holding period to an input terminal of the A/D conversion circuit, wherein digital output signals resulting from A/D conversion can be generated from an output terminal of the A/D conversion circuit, wherein the central processing unit can perform data processing of the digital output signals, the semiconductor integrated circuit further comprising: in the semiconductor chip, a clock generating unit and a sample and hold signal generating circuit, wherein the clock generating unit generates an operation clock signal which is supplied to the central processing unit and a clock output signal which is supplied to the sample and hold signal generating circuit, wherein, in a calibration operation of the semiconductor integrated circuit, in response to the clock output signal, the sample and hold signal generating circuit generates a plurality of clock signals whose timings differ from one another and supplies the clock signals sequentially to a sample and hold control input terminal of the sample and hold circuit, wherein in the calibration operation, the A/D conversion circuit converts a plurality of analog signals held at each timing of each of the clock signals by the sample and hold circuit sequentially to a plurality of digital signals, wherein in the calibration operation, by executing analysis of the digital signals, a timing of a holding period of the sample and hold circuit for allowing A/D conversion of the A/D converter under a low noise condition is selected from the clock signals, and wherein, in a normal operation of the semiconductor integrated circuit, a clock signal having the timing of the holding period, selected out of the clock signals by the calibration operation, is supplied to the sample and hold circuit as a sample and hold control signal and analog signals held at the timing of the sample and hold control signal by the sample and hold circuit are A/D converted by the A/D conversion circuit and output as the digital output signals.