Patent ID: 7818654

Claim:
An addressing architecture for parallel processing of recursive data, which architecture comprises: memory arranged with a first storage area for storing a first set of path metrics and a second storage area for storing a second set of path metrics, which first storage area is coupled to a first memory input and a first memory output, and which second storage area is coupled to a second memory input and a second memory output; a selector arranged to connect the first memory output or the second memory output to a first selector output, and the first memory output or the second memory output to a second selector output; and a Viterbi butterfly structure having a first set of inputs connected to the first selector output, a second set of inputs connected to the second selector output, a first set of outputs connected to the first memory input and a second set of outputs connected to the second memory input, wherein the selector is configured to control the Viterbi butterfly structure such that new path metrics are stored in desired respective storage areas.