Patent ID: 7906253

Claim:
A method for preparing a photomask set for a lithography process that employs a plurality of photomask patterns to pattern a layer on a substrate in the fabrication of an integrated circuit, the method comprising: loading data describing an integrated circuit level of a drawn circuit design into a computer; using the computer with the loaded data, generating a first mask pattern for defining fine features of the integrated circuit level including phase blocks for defining edges setting critical dimensions of device structures of the drawn circuit design; using the computer, generating a second mask pattern for defining coarse features of the integrated circuit level including pattern segments for masking at least portions of the fine features of the first mask pattern including at least portions of the device structures defined by the first mask pattern; using the computer, identifying edges of the second mask pattern that may potentially doubly define the critical dimension setting edges of the at least portions of the device structures in composite aligned exposures of the first and second mask patterns onto a layer of a substrate for forming the integrated circuit level; using the computer, modifying the second mask pattern the trim mask based on the identified critical dimension setting edges, to prevent such potentially doubly defined critical dimension setting edges; and preparing a first photomask using the first pattern and a second photomask using the modified second pattern.