Patent ID: 7525122

Claim:
A passivated semiconductor structure comprising: a silicon carbide substrate; a thermal oxidation layer on said silicon carbide substrate for lowering the interface density between said silicon carbide substrate and said thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on said thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on said first sputtered layer for positioning subsequent passivation layers further from said substrate without encapsulating said structure; a sputtered stoichiometric silicon nitride layer on said second sputtered layer for encapsulating said structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on said encapsulant layer.