Patent ID: 6905929

Claim:
A method for reading a memory cell having an n type source formed in a p type semiconductor material, an n type drain formed in the p type semiconductor material, a channel in the p type semiconductor material defined between the source and drain, an n type well formed in the p type semiconductor material, the n type well defining an intervening region of the p type semiconductor material between the well and the channel, a heavily doped n type contact region formed in a first central region of the n type well, a control gate region formed by the well and the heavily doped contact region, an oxide layer forming a floating gate oxide over the channel, an isolation oxide over the intervening region, and an open-rectangular control gate oxide over a second central portion of the n type well, a floating gate including an open-rectangular floating gate portion formed over the open-rectangular control gate oxide and a narrow floating gate portion formed over the floating gate oxide and the isolation oxide, and a heavily doped p type isolation region circumscribing the source, the drain, the channel, the well, and the intervening region, the method comprising the steps of: grounding the source and the semiconductor material, applying a first positive read voltage to the contact region and a second positive read voltage to the drain such that a positive read bias is induced on the floating gate, the second positive read voltage sufficient to create a channel current between the drain and the source if the memory cell has not been programmed, and the second positive read voltage insufficient to create the channel current if the memory cell has been programmed, and determining a logic state of the memory cell by comparing the magnitude of the channel current with a reference current.