Patent ID: 7026843

Claim:
A cascode amplifier circuit, said cascode amplifier circuit being connected to a target memory cell via a bit line during a read operation involving said target memory cell, said cascode amplifier circuit comprising: a first intrinsic FET having a source connected to said bit line and a drain connected to a first node, a bit line voltage being generated at said source of said first intrinsic FET, a sense amp input voltage being generated at said first node; a second intrinsic FET having a gate connected to said source of said first intrinsic FET and a source connected to a reference voltage, said second intrinsic FET having a drain connected at a second node to a gate of said first intrinsic FET; a third intrinsic FET having a source connected to said first node and a gate connected to a supply voltage, said third intrinsic FET further providing a load across said supply voltage and said first node; a fourth FET having a source connected to said second node and a drain connected to said supply voltage, said fourth FET having a gate connected to an input control voltage; wherein said third intrinsic FET has a drain connected to said supply voltage through a first enable transistor, and wherein said fourth FET has a drain connected to said supply voltage through a second enable transistor.