Patent ID: 7876626

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of mutually parallel word lines, a plurality of mutually parallel bit lines formed crossing said word lines, and a plurality of memory cells arranged at intersections of said word lines and bit lines, each memory cell having one end connected to said word line and the other end connected to said bit line; a read/write circuit operative to selectively apply a voltage for data read/write between said word line and said bit line and execute data read/write to said memory cell; and an operational circuit operative to compare certain length data read out by said read/write circuit from plural ones of said memory cells with certain length data to be written in said plural memory cells to make a decision, and create a flag representing the decision result, wherein said read/write circuit inverts each bit in said certain length data to be written in said memory cells in accordance with said flag and writes only rewrite-intended data of said certain length data and said flag into said memory cells at the time of data write, wherein said read/write circuit reads said certain length data together with said flag corresponding thereto and inverts each bit in said certain length data in accordance with said flag before the output thereof at the time of data read.