Patent ID: 7091097

Claim:
A method of fabricating a semiconductor device having reduced junction leakage, the method comprising the steps of: A. forming a gate electrode over a substrate; B. forming deep amorphous regions to a first depth by pre-amorphisization implantation; C. implanting dopants within the deep amorphous regions to form amorphisized source/drain regions to a second depth, which is less than the first depth; D. forming intermediate amorphous regions by partially recrystallizing portions of the deep amorphous regions to a third depth, which is less than the first depth, but at least as deep as the second depth; and E. recrystallizing the intermediate amorphous regions and activating the dopants to form final source/drain regions to a depth about equal to the third depth such that deep amorphous regions are located beneath the final source/drain regions and the final source/drain regions comprise activated dopants throughout the final source/drain regions.