Patent ID: 8178923

Claim:
A power semiconductor device having low gate input resistance, comprising: a substrate, having an active region and a gate metal region, the substrate in the active region having at least a gate bus trench and a plurality of cell trenches, wherein the gate bus trench extends to the gate metal region, and the cell trenches and the gate bus trench are connected to each other; at least a trench transistor, disposed in the active region of the substrate and at a side of the gate bus trench; a conductive layer and a metal contact plug, disposed in the gate bus trench; an insulating layer and an interlayer dielectric disposed on the substrate, wherein the insulating layer completely covers the metal contact plug in the active region, the insulating layer covers a portion of the gate metal region to expose a portion of the metal contact plug in the gate metal region, and the interlayer dielectric covers the conductive layer; and a patterned metal layer disposed on the interlayer dielectric and the insulating layer, wherein the patterned metal layer comprises a gate metal layer and a source metal layer respectively disposed on the gate metal region and the active region, the gate metal layer is electrically connected to the metal contact plug for being configured to provide a gate voltage, and the source metal layer covers the insulating layer and is electrically connected to the trench transistor for being configured to provide a source voltage.