Patent ID: 8174969

Claim:
An integrated circuit device comprising a packet switch, the packet switch comprising: an upstream egress port; a first downstream ingress port coupled to the upstream egress port and configured to provide a plurality of non-posted packets to the upstream egress port, the upstream egress port configured to output the plurality of non-posted packets from the packet switch; a first downstream egress port; an upstream ingress port coupled to the first downstream egress port and configured to receive a plurality of completion packets in response to the plurality of non-posted packets output from the packet switch and provide the plurality of completion packets to the first downstream egress port, the first downstream egress port configured to store the plurality of completion packets and output the plurality of completion packets from the packet switch; a second downstream ingress port coupled to the upstream egress port and configured to provide packets to the upstream egress port; a second downstream egress port coupled to the upstream ingress port and configured to receive packets from the upstream ingress port; and a flow control circuit coupled to the first downstream ingress port and the first downstream egress port and configured to determine when the first downstream egress port is congested and prevent the first downstream ingress port from providing a non-posted packet to the upstream egress port when the first downstream egress port is congested.