Patent ID: 8340088

Claim:
An apparatus, comprising: a first edge device having a packet processing module, the first edge device configured to receive a packet, the packet processing module of the first edge device configured to produce a plurality of cells based on the packet, the first edge device including a buffer configured to define a queue having a length associated with a grant-request scheme; a second edge device having a packet processing module configured to reassemble the packet based on the plurality of cells; and a multi-stage switch fabric coupled to the first edge device and the second edge device, the multi-stage switch fabric defining a single logical entity, the multi-stage switch fabric having a plurality of switch modules, each switch module from the plurality of switch modules having a shared memory device, the multi-stage switch fabric configured to switch the plurality of cells so that the plurality of cells are sent to the second edge device, each switch module from the plurality of switch modules excluding a buffer configured to define a queue associated with the grant-request scheme.