Patent ID: 7754596

Claim:
A method of manufacturing a semiconductor device preventing an electrical short, the method comprising: forming a first interlayer insulating layer on a semiconductor substrate having an active region defined by a device isolation layer; forming contact pads inside the first interlayer insulating layer, the contact pad electrically connecting the active region with an upper conductive layer and having a thickness equal to that of the first interlayer insulating layer; forming recessed contact pads to have less thickness than the first interlayer insulating layer by removing a portion of the contact pads; and forming contacts on the contact pads, the contacts being connected with an upper conductive layer, wherein the contact pads include: a bottom electrode contact pad connecting with a capacitor's bottom electrode contact disposed above the bottom electrode contact pad; and a bit line contact pad connecting with a bit line contact disposed above the bit line contact pad, and wherein a distance between the bottom surfaces of the capacitor's bottom electrode contact and the bit line contact is larger than a width of a protruded portion of the first interlayer insulating layer.