Patent ID: 6841825

Claim:
A transistor comprising: a processed substrate including a drain layer of a first conductivity type provided on one face thereof, the processed substrate having a plurality of first deep holes provided on the drain layer side and a plurality of ring-shaped second deep holes provided so as to concentrically surround the plurality of first deep holes; a gate insulating film provided on at least a part of a side face of each of the first deep holes; gate electrode plugs provided in the first deep holes and being in contact with the gate insulating film; a base region of a second conductivity type, provided at a position in contact with the gate insulating film inside the drain layer, having a shallower bottom face than each of the first deep holes; and a source region of a first conductivity type provided at inner surface of the base region to be contact with the gate insulating film, the source region not being in contact with the drain layer due to the base region, wherein, when a voltage is applied to the gate electrode plugs to invert a conductivity type of a portion of the base region in contact with the gate insulating film into the first conductivity type so as to form an inversion layer, the source region and the drain layer positioned below a bottom face of the base region are connected to each other through the inversion layer; and filling regions of the second conductivity type are provided in the second deep holes.