Patent ID: 8385495

Claim:
A frame sync detecting circuit for detecting frame synchronization from a received word pattern, comprising: an average-value calculation section operable to calculate a moving average value of a given number of moving values of the received word pattern; an offset calculation section operable, using a moving average value of moving values of a same number as the given number, in a predetermined sync word pattern, as an ideal average value, to calculate a DC offset from a difference between the ideal average value and the moving average value calculated by the average-value calculation section; a subtraction section operable to subtract the DC offset from respective symbol values of the received word pattern; a correlation processing section operable to perform a correlation processing between the received word pattern after the DC offset correction by the subtraction section, and the sync word pattern; a candidate determination section operable to compare a correlation value derived by the correlation processing section with a predetermined threshold value, wherein it is operable, if the correlation value is greater than the threshold value, to recognize the received word pattern as a sync word candidate; and a final determination section operable, when a sync word candidate is recognized by the candidate determination section, to compare the received word pattern after the DC offset correction with respective symbol values of the sync word pattern, wherein it is operable, if errors in all the symbols fall within a given range, to determine that a sync word pattern is detected.