Patent ID: 7079613

Claim:
An apparatus for determining an estimate of timing error in a digital signal receiver, said apparatus comprising a timing error controller that is capable of determining said estimate of timing error from a difference between an arrival time of a first training sequence and an arrival time of a second training sequence in said digital signal receiver, wherein said timing error controller is capable of extracting y 1 data around said first training sequence received at time t 1 where said y 1 data is represented by: y 1 ( t )=Σ a k h 1 ( t−kT )+ e 1 ( t ) where a k represents said training sequence, h 1 (t) represents a channel impulse response at time t 1 , e 1 (t) represents an error term, and T represents a clock period of a transmitter; and wherein said timing error controller is capable of sampling said y 1 data at a rate T 2 that is approximately equal to said value T of said clock period of said transmitter to obtain sampled y 1 data represented by: y 1 ( nT 2 )=Σ a k h 1 ( nT 2 −kT )+ e 1 ( nT 2 ).