Patent ID: 7560734

Claim:
A semiconductor device comprising: a gate wiring over a substrate; first and second pixels adjacent to each other with the gate wiring interposed therebetween, the first pixel comprising: a semiconductor layer over the substrate, the semiconductor layer comprising: a channel forming region; a first impurity region forming a source region or a drain region containing a single conductivity type impurity element; and a second impurity region forming an LDD region contacting the channel forming region, an insulating film provided over the semiconductor layer, and covering edges of the semiconductor layer; a gate electrode having a tapered portion, and provided over the insulating film; a capacitor comprising a capacitor electrode, a portion of the semiconductor layer overlapped with the capacitor electrode, and a first portion of the insulating film overlapped with the capacitor electrode; wherein a portion of the second impurity region is overlapped with the gate electrode, wherein a thickness of a second portion of the insulating film overlapped with the gate electrode is thicker than a thickness of a third portion of the insulating film overlapping the second impurity regions, wherein the gate electrode is a portion of the gate wiring, and wherein the semiconductor layer extends in the second pixel.