Patent ID: 7965560

Claim:
A nonvolatile memory, comprising: a group of memory cells accessible by associated bit lines; a group of sensing circuits for sensing the group of memory cells in parallel to determine the conduction currents of the memory cells relative to a first reference current; a controller for controlling operations of the memory; said controller controlling the sensing circuits in first and second pass sensing; wherein: the group of memory cells are set up and sensed in a first pass to identify those memory cells with conduction currents higher than a second reference current that is higher than the first reference current by a predetermined margin; the identified higher current memory cells are turned off; the remaining unidentified memory cells are set up and sensed in a second pass relative to the first reference current; and the first pass further includes: a period of setup being reduced by a first predetermined amount; the predetermined margin by being increased by a second predetermined amount sufficient to accurately identify all memory cells with conduction currents higher than the second reference current; and the first predetermined amount is such that the total power consumed by the first and second passes is reduced to a predetermined level.