Patent ID: 7585724

Claim:
A FLASH memory device, comprising: a first group of floating gates comprising a plurality of first floating gates formed over a gate oxide layer formed over a substrate, said first group of floating gates being formed using a selected photolithography process associated with a minimum line width; a second group of floating gates comprising a plurality of second floating gates, wherein said first and second floating gates are disposed in series, with individual ones of said second floating gates disposed between respective ones of said first floating gates; a plurality of spacers, individual ones of said spacers disposed between adjacent ones of said first and second floating gates; a plurality of control gates associated with said floating gates, respective ones of said control gates disposed on top of said floating gates, wherein adjacent ones of said first and second floating gates are each spaced from one another a substantially uniform distance less than said minimum line width and wherein said second floating gates have widths less than said minimum line width.