Patent ID: 8164941

Claim:
A semiconductor memory device comprising: a P-type channel region, a N-type drain region and an N-type source region formed in a substrate; a ferroelectric layer formed over the P-type channel region; and a word line formed over the ferroelectric layer, wherein a data read operation is performed by a cell sensing current value differentiated depending on the polarity state of the ferroelectric layer while a different channel resistance is induced to the P-type channel region depending on a polarity state of the ferroelectric layer, a positive read voltage is applied to the word line and a sensing bias voltage is applied to one of the N-type drain region and the N-type source region, wherein a data write operation is performed by applying voltages to the word line, the N-type drain region and the N-type source region to change a polarity of the ferroelectric layer, and wherein a negative read voltage is applied to the word line and the positive read voltage is applied to the N-type drain region and the N-type source region when high data are written in the ferroelectric layer.