Patent ID: 8564052

Claim:
A trench MOSFET with a plurality of transistor cells in active area and multiple trenched floating gates in termination area, comprising: a substrate of a first conductivity type; an epitaxial layer of said first conductivity type onto said substrate, said epitaxial layer having a lower doping concentration than said substrate; a plurality of source regions of said first conductivity type formed near top surface of said epitaxial layer only within said active area, said source region having a doping concentration higher than said epitaxial layer; a plurality of first type body regions of a second conductivity type formed underneath said source region in said active area; a plurality of second type body regions of said second conductivity type formed in said epitaxial layer from top surface of said epitaxial layer around outside of said active area including said termination area, and said source regions being not disposed on the top of said second type body regions; a plurality of first type trenched gates in said active area surrounded by said source regions and said first type body regions, extending into said epitaxial layer; at least one second type trenched gate having a greater trench width and trench depth than said first type trenched gates in said active area and extending to said first type trenched gates, wherein said second type trenched gate surrounded by said second type body regions is extending into said epitaxial layer; an equal potential ring in said termination area and surrounding outside of said trenched floating gates; wherein said second type trenched gate is connecting to a gate metal pad used for wire bonding; said multiple trenched floating gates in parallel formed in said termination area around outside of said active area are having floating voltage and surrounded by said second type body regions, and having trench depth equal to or deeper than body junction of said second type body region; and said second type body regions between two adjacent of said trenched floating gates in said termination area are having floating voltage.