Patent ID: 8171386

Claim:
Sequential storage circuitry for an integrated circuit, comprising: a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry; a second storage element coupled to an output of the first storage element, for storing a second indication of the input data value during a second phase of the clock signal; an additional storage element for storing a third indication of the input data value on occurrence of a pulse signal derived from the clock signal; and error detection circuitry for detecting a single event upset error in either the first storage element or the second storage element by: (i) during the first phase of the clock signal, detecting the single event upset error in the first storage element if there is a difference in the input data value as indicated by said first indication and said third indication; and (ii) during the second phase of the clock signal, detecting the single event upset error in the second storage element if there is a difference in the input data value as indicated by said second indication and said third indication.