Patent ID: 8576652

Claim:
A memory controller connected to a semiconductor device including a memory cell, the memory controller comprising: a memory control unit that, during a operation mode that allows said semiconductor device to deal with an access to information data from outside, periodically outputs a command that permits said semiconductor device to perform a refresh operation for data written in said memory cell; and a power-down mode refresh control unit that, during a power-down mode that inhibits said semiconductor device from dealing with access to said information data from outside, periodically outputs a first signal, different from said command, to said semiconductor device to execute said refresh operation, wherein, in case said semiconductor device is set to said power down mode, in which said semiconductor memory device does not accept said command, said power-down mode refresh control unit outputs said first signal to one of input buffers of said semiconductor memory device which is able to accept a signal from outside of said semiconductor memory device even during said power-down mode.