Patent ID: 7389375

Claim:
A method for providing a buffer device with multiple operating modes, the method comprising: receiving one or more clock inputs at the buffer device, the buffer device including a first memory interface adapted to connect the buffer device to a cascaded interconnect system though an upstream memory bus and a downstream memory bus, and the buffer device including a second memory interface having two or more selectable modes of operation and one or more second clock lines for driving one or more second clocks derived from the one or more clock inputs; receiving an input signal at the buffer device; determining a mode associated with the input signal, the modes including: a first mode for communicating with one or more synchronous memory devices; and a second mode for communicating with one or more second memory assemblies including one or more of unbuffered and registered memory assemblies, wherein at least one of the second memory assemblies requires that the buffer device communicate with the second memory assembly using one or both of drive strength and timing characteristics that differ from those used to communicate with the synchronous memory devices connected to the first memory assembly in the first mode of operation, the timing characteristics including one or more of read data, write data, address and command timing relationships relative to the one or more second clock; and transmitting the input signal to a synchronous memory device or to a second memory assembly in a format corresponding to the mode.