Patent ID: 7659187

Claim:
A method of forming transistors on a wafer, comprising: forming gates over gate insulators on a surface of the wafer; ion implanting dopant impurity atoms into the wafer to form source and drain regions aligned on opposite sides of each gate; heating the bulk of the wafer to an elevated temperature over 350 degrees C. and below 475 degrees C.; producing a line beam of a selected power density and having a narrow dimension along a fast axis from an array of coherent CW lasers of a selected wavelength; scanning the line beam across the wafer along the direction of the fast axis, so as to heat, up to a peak surface temperature near a melting temperature of the wafer, a moving localized region on the surface of the wafer having (a) a width corresponding to the narrow beam width and (b) a below-surface depth in a range of about 10 to 20 microns, said range being attainable at a nominal scanning rate along said fast axis of said line beam of 100 mm/sec at said selected power density; and during the scanning step, minimizing the surface state density at the interface between the semiconductor material and the gate insulator by: continuing to maintain the temperature of the bulk of the wafer outside of the moving localized region at said elevated temperature; and maintaining the scanning rate along said fast axis of said line beam in excess of 300 mm/sec.