Patent ID: 8477540

Claim:
An SRAM-type memory device, comprising: a memory plane having at least one column of memory cells of the SRAM type, each memory cell comprising two cross-coupled inverters and a single access transistor, each memory cell being connected between two bit lines, wherein the at least one column of the memory plane also comprises an additional memory cell, with a structure identical to that of the memory cells of said column, connected to the two bit lines, the two bit lines being configured to be powered by a power supply voltage; a controllable additional access means connected to said additional memory cell and having a first state to prevent access to said additional cell and a second state to allow access to said additional memory cell so as to store a datum therein or extract a datum therefrom; first control means configured to place said additional access means in said first or in said second state; and second control means configured to deliver, when the additional access means is in said first state, a first control signal to a gate of the access transistor of one of the memory cells of the column and a second control signal to a gate of the access transistor of the additional memory cell so as to place said memory cell in a read mode and the additional memory cell in a write mode, or vice versa.