Patent ID: 8873299

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; a first wiring connected to a memory cell; and a first voltage generating circuit having an output terminal and configured to generate a first voltage to be supplied to the first wiring through the output terminal when the memory cell is selected, the first voltage generating circuit including: a first diode that is connected between a first node and a second node; a first transistor that is connected between the output terminal and a third node, the first transistor having a gate connected to the second node; a second transistor that is connected between the third node and ground, the second transistor having a gate connected to the second node; a third transistor that is connected between the output terminal and the first node, the third transistor having a gate connected to a fourth node; a second diode that is connected between the first node and the fourth node; and a charge pump circuit configured to supply a voltage to the fourth node.