Patent ID: 7342420

Claim:
A low power output driver system comprising: (a) a reference voltage supply; (b) a first voltage regulator that receives reference voltage supply and outputs a first regulated voltage; (c) a second voltage regulator that receives reference voltage supply and outputs a second regulated voltage; (d) a first low power output driver; and (e) a second low power output driver, each of the first and second low power output drivers including: (i) a first driver input that receives a first logic signal; (ii) a second driver input that receives a second logic signal; (iii) a first driver output that outputs a first output signal; (iv) a second driver output that outputs a second output signal; (v) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the respective first and second regulated voltage and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input; (vi) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and an internal ground, the gate of the second NMOS being electrically coupled to the second driver input; (vii) a third NMOS having a gate, a source and a drain, the source and the drain of the third CMOS being electrically coupled between the respective first and second regulated voltage and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and (viii) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input.