Patent ID: 8022409

Claim:
A semiconductor device, comprising: a substrate including an active region divided into a plurality of storage node contact junction regions, a plurality of channel regions and a bit line contact junction region, wherein the storage node contact junction regions and the channel regions are lateral to each other and positioned parallel to a major axis of the active region, wherein the major axis is the X-axis of the active region; a plurality of device isolation layers formed in the substrate and isolating the active region from a neighboring active region; a plurality of recess patterns, each formed in a trench structure and extending from one of the storage node contact junction regions to one of the channel regions in a direction along the major axis of the active region; a plurality of line type gate patterns, each filling a predetermined portion of one of the recess patterns formed in the channel regions in a direction crossing the major axis of the active region; and a plurality of storage node junctions, each formed below a predetermined portion of one of the recess patterns formed in the storage node contact junction regions.