Patent ID: 8503578

Claim:
A method of processing first and second corresponding signals having a delay therebetween, at least the first signal being an irregular binary signal having chip boundaries, the method comprising: sampling the second signal to obtain a plurality of values for each of a plurality of different predetermined delay times relative to a respective chip boundary which lies between bits of the first signal which transit different states and/or have the same state, the plurality of different predetermined delay times differing from each other by less than an interval between chip boundaries; and summing samples of the second signal which are obtained substantially at each of the plurality of different predetermined delay times relative to the respective chip boundary to obtain a representation of how the plurality of values vary according to the plurality of different predetermined delay times, which contains a level change associated with a delay time which bears a predetermined relationship to the delay between the first and second signals, wherein the samples are obtained only in response to chip boundaries between bits of the same state, and the representation includes a sum of samples obtained in response to chip boundaries between bits of a first state minus a sum of samples obtained in response to chip boundaries between bits of a second state.