Patent ID: 7496155

Claim:
A clock circuit having a controlled duty cycle, comprising: a feedback adjustment combining element comprising a first summing element operably disposed to provide a sum of a recovered clock and a duty cycle feedback signal, and further comprising a crossover point control clock amplifier which is operable to generate an adjusted clock based upon the sum of the recovered clock and the duty cycle feedback signal produced by the first summing element; a first operational amplifier having a first input, a second input, and a first output providing the duty cycle feedback signal, wherein the second input is operably coupled to a common mode voltage reference, and further wherein a bandwidth of the first operational amplifier is substantially lower than a frequency of the recovered clock; and a first resistor operably disposed between the feedback adjustment combining element and the first input of the first operational amplifier; wherein the crossover point control clock amplifier, comprises two cross coupled p-channel MOSFET (PMOS) transistors and a second resister coupled between the two PMOS transistors that are jointly operable to adjust cross points of differential clocks' rising and falling edges to be at a substantially similar voltage level.