Patent ID: 8648428

Claim:
A memory array, comprising: a semiconductor material base; a plurality of linearly extending semiconductor mesas upstanding from said base, spaced from one another and arranged in parallel; a plurality of first silicide elements respectively extending along an upper level of each of said mesas in said linear direction; a plurality of second silicide elements respectively on said base at least at a first side of each mesa structure; a plurality of first mesa sidewall gate structures respectively provided on said first side of each of said linearly extending mesa and each comprising a gate insulator material and an overlying gate conductor, first gate structures being operative to control current flow between said respective first and second silicide elements through said respective mesa structure, a plurality of memory cells, each electrically coupled to one of said first silicide elements via a diode device; and a plurality of conductive lines arranged so that each of said memory cells is electrically coupled to one of said conductive lines so that no two memory cells are electrically coupled to the same first silicide element and the same conductive line.