Patent ID: 7751222

Claim:
A semiconductor memory device comprising a memory cell array comprising a single or a plurality of basic cells, and selecting lines, bit lines and word lines respectively provided for designating the basic cells, wherein the basic cell comprises, provided that N and M are respectively integers of at least one: first and second memory cells for retaining data having at least a binary value; a first selecting transistor connected between a first terminal of the first memory cell and the Mth bit line; a second selecting transistor connected between the first terminal of the first memory cell and the M+1th bit line, a third selecting transistor connected between a first terminal of the second memory cell and the M+1th bit line; and a fourth selecting transistor connected between the first terminal of the second memory cell and the M+2th bit line, wherein a gate of the first selecting transistor is connected to the 2·N−1th selecting line, a gate of the second selecting transistor is connected to the 2·Nth selecting line, a gate of the third selecting transistor is connected to the 2·N+1th selecting line, a gate of the fourth selecting transistor is connected to the 2·N+2th selecting line, and the memory cell array is able to control only the selected word line.