Patent ID: 8796770

Claim:
An integrated circuit device comprising: a memory cell including a transistor, the transistor comprising: a body region configured to be electrically floating; a gate disposed over a first portion of the body region; a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion; and a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion; wherein the memory cell is configured to store a first data state representative of a first charge in the first portion of the body region; wherein the memory cell is configured to store a second data state representative of a second charge in the first portion of the body region; and data write circuitry coupled to the memory cell, the data write circuitry configured to apply first write control signals to the memory cell to write the first data state to the memory cell and second write control signals to the memory cell to write the second data state to the memory cell, wherein, in response to first write control signals, the electrically floating body transistor generates a first source current which substantially provides the first charge in the first portion of the body region.