Patent ID: 8170169

Claim:
A clock and data recovery circuit, comprising: a phase detector for comparing an incoming serial data signal with a feedback clock signal and generating a digital phase detector output signal representing a phase difference between the incoming data signal and the feedback clock signal; a dual path filter for receiving the phase detector output signal, the dual path filter including a first path for generating a digital proportional output signal that is proportional to the phase detector output signal and a second path having an integral digital filter for generating a digital integral output signal that is proportional to an integral of the phase detector output signal; a digitally controlled oscillator for receiving the proportional output signal and the integral output signal as tuning inputs and generating in dependence thereon an output clock signal from which the feedback clock signal is obtained; and a clock multiplier unit (CMU) for providing a temperature compensation signal to the digitally controlled oscillator, comprising: a phase frequency detector for comparing a reference clock signal with a CMU feedback clock signal and generating a CMU error signal representing a phase difference and a frequency difference between the reference clock signal and the CMU feedback clock signal; a loop filter for receiving the CMU error signal and producing tuning signals that are representative of the CMU error signal; and an oscillator for receiving the tuning signals and generating in dependence thereon a CMU output clock signal from which the CMU feedback clock signal is obtained, the temperature compensation signal being derived from the CMU error signal.