Patent ID: 7117459

Claim:
A layout check system that checks layout data that defines a layout of a power source, a component that includes a power pin, and a bypass capacitor on a printed wiring board, comprising: a storage unit operable to store the layout data, the layout data including information used for calculating a first value and a second value, the first value corresponding to impedance between the power pin and the power source, and to second value corresponding to impedance between the power pin and the bypass capacitor; a calculation unit operable to calculate, with use of the layout data, a shortest wiring distance between the power pin and the power source as a first value, and a shortest wiring distance between the power pin and the bypass capacitor as a second value; a judgment unit operable to judge, by comparing the first value with the second value, that the layout does not allow the bypass capacitor to function effectively if the first value is less than the second value; and an output unit operable to output error information when a result of the judgment is negative, wherein when a power via exists on wiring that connects the power pin and the bypass capacitor, the calculation unit calculates, with use of the layout data, a shortest wiring distance between the power pin and the power via as the first value, and the shortest wiring distance between the power pin and the bypass capacitor as the second value.