Patent ID: 7304354

Claim:
A semiconductor device comprising: a substrate having a first conductivity type; a first well having the first conductivity type, wherein the first well includes a first well contact region; a plurality of transistors, wherein at least one of the plurality of transistors includes: the first well; a source region having a first width at an interface between the source region and a channel region; a drain region having a second width at an interface between the drain region and the channel region; and the channel region located between the source region and the drain region, wherein the channel region has a channel length and a third width greater than each of the first width and the second width, thereby forming at least one channel extension, and wherein the at least one channel extension provides a net channel edge length between the source region and the drain region that is greater than the channel length; a buried layer having the first conductivity type and located beneath the first well, wherein the buried layer extends substantially continuously beneath the plurality of transistors, and further comprises a buried layer impurity concentration greater than a first substrate impurity concentration; and a vertical conductor extending between the buried layer and one of the first well contact region and a substrate surface terminal.