Patent ID: 7224620

Claim:
A Non-Volatile memory cell structure that is capable of being programmed by one of two methods, and being erased by the other of the two methods, one method being Tunnel-Gun (Tun-Gun) method and the other being the Channel Accelerated Carrier Tunneling (CACT) method, comprising, i. a silicon substrate having one type of doping; ii. a first well within the substrate having a second type of doping; iii. a second well within the first well having the opposite type of doping, similar to the substrate; iv. a trench etched from the surface of the silicon substrate within the second well, etched deep enough to pass through the second well to the first well; v. the trench side walls covered with a select gate oxide, isolating it from the doped silicon of second well; vi. the trench filled with polysilicon, acting as a select/accelerating gate; vii. an oxide insulator over the polysilicon in the trench; viii. a floating gate polysilicon over laying a tunnel oxide adjacent the trench side wall oxide and extending over the oxide insulator over the trench polysilicon; ix. an integrated channel formed in the second well silicon adjacent the select gate oxide and the floating gate oxide between a doped drain adjacent the floating gate and the first well as a source; x. a discontinuity in the integrated channel at the intersection of the trench oxide and the floating gate oxide; xi. a retention oxide formed over and on the sides of the floating gate polysilicon; xii. a Tunnel Gun (Tun-Gun) structure on the floating gate on the floating gate but separated from it by the retention oxide, comprising, a grid collector electrode, an injector electrode separated from the grid collector by a barrier material; xiii. the grid collector and the injector electrode together forming a control gate.