Patent ID: 7488651

Claim:
A method of forming a semiconductor assembly having vertical transistor structures comprising: forming columns of trench isolation material in a silicon substrate; forming circular patterned hard mask material in circular holes in an insulation material overlying the silicon substrate; forming partial silicon pillars by removing an upper portion of the silicon substrate while using the hard mask material as an etching mask; forming nitride spacers on sidewalls of the partial silicon pillars; with the hard mask material in place, etching the trench isolation material and the silicon substrate to a desired depth to form silicon pillars, each having a defined channel length determined by extending the partial silicon pillars in a vertical direction below the nitride spacers; forming a gate dielectric on an exposed portion of the silicon pillars below the nitride spacers; depositing a conformal polysilicon material over the silicon substrate, the trench isolation material, the hard mask material, the nitride spacers and the transistor gate dielectric; forming a silicon pillar isolation material over the conformal polysilicon material; planarizing the conformal polysilicon material and the silicon pillar isolation material; recessing the conformal polysilicon material down to a base of the nitride spacers to form a vertical-surrounding-gate of the vertical transistor structures; forming an anti-reflective coating over the conformal polysilicon material and silicon pillar isolation material; forming conductors to connect to a series of vertical-surrounding-gates; depositing an insulation material over the polysilicon material and silicon pillar isolation material; and removing the hard mask material to create a surface for a vertical-surrounding-gate source contact.