Patent ID: 8018248

Claim:
An integrated circuit formed from a plurality of layers on a semiconductor chip, the integrated circuit comprising: a programmable logic device; a dedicated device; and an interface coupled between the programmable logic device and the dedicated device, the interface comprising a plurality of interface buffer circuits, each interface buffer circuit comprising a logic gate having at least one input terminal and an output terminal; wherein each interface buffer circuit is the same except for routing paths of conductors in one layer of the plurality of layers, wherein the plurality of interface buffer circuits comprises a first set of interface buffer circuits in which the routing paths of the conductors in the one layer couple the at least one input terminal of the logic gate to the programmable logic device and couple the output terminal of the logic gate to the dedicated device; and a second set of buffer circuits in which the routing paths of the conductors in the one layer couple the at least one input terminal of the logic gate to the dedicated device and couple the output terminal of the logic gate to the programmable logic device.