Patent ID: 8015361

Claim:
A computer system comprising: at least one data processor unit connected to a main memory; each of said at least one data processor units comprising: a memory management unit for controlling the conversion of an address of requested data received from a processor into a physical address of said requested data; a data cache for storing recently requested data; a translation unit in said memory management unit for checking received data requests against data stored in said data cache; and a connector for bypassing said data cache; said main memory comprising: storage for the data being accessed in pages at said physical addresses; a page table accessed by said memory management unit for converting to said page addresses; a random access memory (RAM); and a memory controller for controlling said RAM, wherein said memory controller includes a page table walker for proceeding through the entries on said page table; wherein a data request is connected directly to said page table walker in the memory controller, via said connector for bypassing said data cache, for address conversion; wherein said translation unit determines if the data cache is to be bypassed based upon a flag in the address of the requested data.