Patent ID: 8710576

Claim:
A memory device comprising: two vertical memory gates formed in a first direction; a silicon substrate sandwiched between said two vertical memory gates wherein a face of said silicon substrate between said silicon substrate and said memory gate forms a memory gate channel region; source regions underlying said two vertical memory gates; drain regions in a top portion of said silicon substrate; a trench isolation formed between said drain regions in a second direction which provides isolation from an adjacent memory device in said second direction wherein a depth of said trench isolation is less than a depth of said vertical memory gates; and memory gate channel oxide formed between each said source region and said drain region and between each said memory gate and said silicon substrate wherein said memory gate channel oxide comprises a first vertical trapping region adjacent to a top vertical portion of said memory gate and a second vertical non-trapping region adjacent to a bottom vertical portion of said memory gate and a horizontal non-trapping region and wherein holes and/or electrons may be stored in said first vertical trapping region.