Patent ID: 8416840

Claim:
A duobinary transceiver, comprising: a transmitter including an open-loop circuit containing a first logic circuit and a divided-by-two circuit receiving a first digital signal and a clock signal to generate a coded digital signal, wherein the first logic circuit includes an AND gate; a transmission medium converting the coded digital signal to generate a duobinary digital signal; and a receiver including a comparator receiving the duobinary digital signal through the transmission medium; a second logic circuit decoding and recovering the duobinary digital signal to generate a differential digital signal; and an adaptive reference voltage control loop including: a filter filtering the differential digital signal to generate a positive and a negative average DC voltages; an operational amplifier having a positive and a negative terminals, and amplifying a difference between the positive and the negative average DC voltages to generate a control voltage signal; and a voltage-to-current (V/I) converter converting the control voltage signal to a first and a second control current signals, and inputting the first and the second control current signals into the comparator.