Patent ID: 7720015

Claim:
A full-duplex transceiver comprising: a transmitter digital to analog converter (DAC) coupled to a transmission channel, the transmitter digital to analog converter (DAC) converting a digital transmission signal into an analog transmission signal; a receiver connected to the transmission channel, the receiver receiving a desired signal, and an echo signal comprising at least a portion of the analog transmission signal, the receiver comprising; a receiver analog to digital converter (ADC); a programmable delay line for adjustably delaying a clock signal of the receiver analog to digital converter (ADC); receiver processing circuit for adjusting the delay of the clock signal based at least in part upon the echo signal, wherein the delay of the clock signal is adjusted so that sampling of the analog to digital converter (ADC) occurs when the echo signal is below a threshold and linearity of the echo signal is above a threshold; and a summer circuit coupled to the input of the receiver, for summing the desired signal and the echo signal with an estimated echo signal to provide cancellation of the echo signal previous to the receiver analog to digital converter (ADC).