Patent ID: 7589653

Claim:
A digital to analog converter (DAC) circuit that operates over an upper range and a lower range, comprising in combination: an upper voltage node designated AVDD; a middle voltage node designated HVDD; a lower voltage node designated ground; an upper DAC stage comprising an upper PMOS transistor having its source and body coupled to AVDD and having its drain coupled to the drain of an upper NMOS transistor whose source is coupled to HVDD, wherein the junction of the upper PMOS transistor and the upper NMOS transistor forms an upper range output node; a lower DAC stage comprising a lower PMOS transistor having its source coupled to HVDD and having its drain coupled to the drain of a lower NMOS transistor whose source and body are coupled to ground, wherein the junction of the lower PMOS transistor and the lower NMOS transistor forms a lower range output node; and a body bias control circuit that couples the body of the upper NMOS transistor to a voltage source equal to HVDD−Vbe and connects the body of the lower PMOS transistor to voltage source equal to HVDD+Vbe.