Patent ID: 7585721

Claim:
A process for fabricating a nano-floating gate flash memory structure, comprising providing a substrate in a high or ultrahigh vacuum chamber of a first air pressure, which is lower than about 10 −6 torr; providing a nanocluster source having a nanocluster target contained therein, the nanocluster target being Ge and the nanocluster source being at a second air pressure substantially higher than the first air pressure; providing rare gas of Ar and He to the nanocluster source; activating the nanocluster target for generating a plurality of nanoclusters; directing at least part of the nanoclusters through an aperture at the nanocluster source to generate a nanocluster beam due to the air pressure difference between the nanocluster source and the chamber; and receiving at least part of the nanoclusters of the beam atop the substrate in the chamber, whereby a plurality of nanoclusters of controllable size of approximately 3 to 10 nanometers in diameter are formed atop the substrate.