Patent ID: 8086919

Claim:
A flash memory controller having a flash memory testing function, comprising: a microprocessor unit; a flash memory interface unit, coupled to the microprocessor unit and configured to connect with a plurality of flash memory dies, wherein each of the plurality of flash memory dies comprises a plurality of physical blocks; a host interface unit, coupled to the microprocessor unit and configured to connect with a host system; and a memory cell testing unit, coupled to the microprocessor unit, simultaneously enabling each of the flash memory dies, and writing a testing datum into all of the flash memory dies simultaneously via at least one data bus, wherein the memory cell testing unit generates a plurality of physical addresses to be written according to an identification code (ID) of each of the flash memory dies and writes the testing datum into the physical blocks of the plurality of flash memory dies according to the physical addresses, wherein the memory cell testing unit reads the testing datum from each of the physical blocks to determine whether each of the physical blocks is a damaged physical block.