Patent ID: 7454722

Claim:
A method for converting a combinational loop in a circuit design into an acyclic circuit, comprising: sending first data representing the combinational loop; and receiving second data representing an acyclic path including at least one added state-holding element, the acyclic path being functionally equivalent to the combinational loop, wherein the second data is generated by determining whether the combinational loop is monotonic and, responsive to a determination that the combinational loop is monotonic, transforming the combinational loop into the acyclic path by adding the at least one state-holding element, and wherein determining whether the combinational boy is monotonic comprises determining a function F(I), a function G(I), and a function B(I), wherein I represents at least one non-cyclic input to the loop, such that A =(F(I) AND A) OR (G(I) AND INV(A)) OR B(I), and wherein A represents a first output of the loop, determining whether G(I) is zero or nonzero, and determining that the combinational loop is mono tonic based on a determination that G(I) is zero.