Patent ID: 8299632

Claim:
A semiconductor die comprising: an integrated circuit formed on one surface of a piece of semiconductor wafer; a plurality of input-output (I/O) pads interconnected to said integrated circuit; a routing layer comprising: a dielectric layer formed on said one surface; and a plurality of conductive traces formed on said dielectric layer, each of said conductive traces extending from one of said I/O pads; a plurality of under-bump metallizations (UBMs), each comprising a top surface for attaching a respective one of a plurality of solder bumps; wherein at least one of said UBMs has at least a first one of said conductive traces passing beneath said one of said UBMs and is electrically interconnected to said first conductive trace through said dielectric layer, and wherein at least a second one of said plurality of conductive traces passes proximate said first conductive trace and under said one of said UBMs to mechanically reinforce said routing layer proximate said one of said UBMs.