Patent ID: 7768813

Claim:
A DRAM, comprising: a word line; a first bit line; a comparison bit line, a memory cell at an intersection of the word line and the first bit line, the memory cell including an access transistor adapted to couple a storage cell to the first bit line if its gate voltage is raised by an assertion of the word line; a word line compensation circuit adapted to compensate for a capacitively-coupled voltage increase on the first bit line if the word line is asserted by producing a replica voltage increase on the comparison bit line, the word line compensation circuit including a replica word line driving a gate of a replica access transistor adapted to couple a replica storage cell to the comparison bit line; a differential amplifier adapted to amplify a voltage difference between the first bit line and the comparison bit line; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference and to compensate for the capacitively-coupled voltage increase on both the first bit line and the comparison bit line.