Patent ID: 7678637

Claim:
A method of forming a complementary metal oxide semiconductor (CMOS) integrated circuit (IC), comprising the following steps, performed in the order listed: providing a substrate; forming an n-channel metal oxide semiconductor (NMOS) gate and a p-channel metal oxide semiconductor (PMOS) gate on said substrate; forming p-type lightly doped drain (PLDD) regions in said substrate adjacent to said PMOS gate; forming NMOS gate sidewall spacers on lateral surfaces of said NMOS gate and PMOS gate sidewall spacers on lateral surfaces of said PMOS gate; ion implanting p-type source and drain (PSD) regions in said substrate adjacent to said PMOS gate sidewall spacers with a first set of p-type dopants and a first carbon species; performing a PSD ultra high temperature (UHT) anneal on said PSD regions at a temperature above 1200 C for a time duration between 50 microseconds and 100 milliseconds; ion implanting n-type source and drain (NSD) regions in said substrate adjacent to said NMOS gate sidewall spacers with a first set of n-type dopants; forming a stress memorization technique (SMT) layer with 500 to 1500 MPa tensile stress on said NMOS gate and said PMOS gate, wherein the instant step is performed after said step of performing a PSD UHT anneal; performing a rapid thermal process (RTP) anneal on said CMOS IC at a temperature above 850 C; and removing said SMT layer.