Patent ID: 7148565

Claim:
A three-dimensional (3-D) vertically stacked wafer structure, comprising: a first wafer including an active device layer comprised of silicon to support one or more integrated circuit (IC) devices; a second wafer including an active layer to support one or more integrated circuit (IC) devices; metallic lines deposited on opposing surfaces of the first and second wafers at designated areas to establish metal bonding between the first and second wafers in a stack and electrical connections between active IC devices on the first and second wafers in the stack; and one or more interwafer vias formed within the first wafer through the silicon active device layer, to provide electrical connections between active IC devices on the first and second wafers in the stack and an external interconnect, wherein each of the interwafer vias comprises: a contact plug in contact with selected metallic lines of the first wafer; an etch stop layer selective to a silicon etch at an end of the via formed through the silicon active device layer, adjacent the contact plug; an oxide layer deposited to insulate a sidewall of the via; and a barrier layer and a conduction metal deposited in the via to provide electrical connection between active IC devices on the first and second wafers in the stack and the external interconnect.