Patent ID: 8266450

Claim:
An information processing device, comprising: a memory in which an encrypted code is stored; a decryptor which performs, to the encrypted code, a multiple-stage decryption process including a first stage and a second stage performed after decryption through the first stage, and which sets a k-th stage which is any one stage of the multiple stages, thereby outputting a decrypted code having passed through a k-stage decryption process; and an instruction execution unit for executing the decrypted code, wherein, when the instruction execution unit issues a branch instruction in a course of an execution cycle of the decrypted code, the decryptor sets a small value to “k” of the k-th stage with respect to the encrypted code of a branch destination, and thereafter, the decryptor outputs the decrypted code while changing the value of “k” to a larger value each time when the execution cycle of the instruction execution unit advances, the decryptor includes: a decryption processing circuit which has a multiple-stage pipeline and performs a decryption process using a key for each stage of the multiple-stage pipeline upon reception of the encrypted code; a selection circuit which selects any one output from outputs of each stage of the multiple-stage pipeline in accordance with a select signal and outputs the selected output to the instruction execution unit; and a control circuit for generating the select signal while detecting issuance of the branch instruction by the instruction execution unit, the decryption processing circuit includes: a first node to which the encrypted code is transmitted; a first-stage pipeline provided between the first node and a second node; and a second-stage pipeline provided between the second node and a third node, the first-stage pipeline includes: a first EXOR circuit which executes an exclusive OR operation using the first node and a first key as inputs; a first transform circuit which performs a nonlinear transform of an output of the first EXOR circuit; a first register which delays a signal of the first node by a predetermined number of cycles; and a second EXOR circuit which executes an exclusive OR operation using an output of the first transform circuit and an output of the first register as inputs, and outputs an operation result of the second EXOR circuit to the second node, and the second-stage pipeline includes: a third EXOR circuit which executes an exclusive OR operation using the second node and a second key as inputs; a second transform circuit which performs a nonlinear transform of an output of the third EXOR circuit; a second register which delays a signal of the second node by a predetermined number of cycles; and a fourth EXOR circuit which executes an exclusive OR operation using an output of the second transform circuit and an output of the second register as inputs, and outputs an operation result of the fourth EXOR circuit to the third node.