Patent ID: 7406584

Claim:
An integrated circuit, comprising: a communication network including a plurality of clocked communication channel segments, at least some of the communication channel segments structured to operate at different clock rates; and a plurality of microprocessor pairs each coupled between a single one of the plurality of communication channel segments of the communication network, each of the plurality of microprocessor pairs including microprocessors structured to operate independently from one another and at an independently controllable clock rate, and each microprocessor having: more than one sending port structured to send a split outgoing data message from its associated processor over at least two communication channels of the communication network, each sending port including one or more sequential output registers, each sequential output register including: a data register for storing a data portion of the outgoing data message, a valid register for storing an indication of a validity of the data stored in the data register, and an accept register for storing an indication that a subsequent element in the communication network is able to accept one of the outgoing data messages, and more than one receiving port structured to receive incoming data messages for its associated processor from the communication network, each receiving port including one or more sequential input registers, each sequential input register including: a data register for storing a data portion of the incoming messages, a valid register for storing an indication of a validity of the data stored in the data register, and an accept register for storing an indication that the sequential input register is able to accept one of the incoming data messages.