Patent ID: 8325522

Claim:
A memory array comprising: a plurality of memory cells organized in a matrix of rows and columns, each of the memory cells comprising: a high voltage access transistor; a floating gate memory transistor electrically connected to the access transistor; and a coupling capacitor electrically connected to the memory transistor; a first set of word lines each electrically connected to the coupling capacitor in each of the memory cells in a respective row; a second set of word lines each electrically connected to the access transistor in each of the memory cells in a respective row; a first set of bit lines each electrically connected to the access transistor in each of the memory cells in a respective column; a second set of bit lines each electrically connected to the memory transistor in each of the memory cells in a respective column, the second set of bit lines each electrically connected together; a plurality of column address transistors each electrically connected to a bit line in the first set of bit lines; a single voltage supply point electrically connected to the second set of bit lines; a program charge pump electrically connected to the voltage supply point; and an erase charge pump electrically connected to the voltage supply point; wherein various combinations of voltages can be applied to the word lines and the bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.