Patent ID: 7657801

Claim:
A test apparatus that tests a device under test having a memory block inside, comprising: an address generating circuit that generates a physical address to be supplied to the memory block inside the device under test; a plurality of mask registers being provided in correspondence with each of a plurality of memory input bits constituting at least a part of a memory input address to be supplied to the device under test, the plurality of mask registers setting values indicating whether a plurality of physical bits constituting at least a part of the physical address is masked every the physical bit; a plurality of mask arithmetic circuits being provided in correspondence with each of the plurality of memory input bits, the plurality of mask arithmetic circuits respectively masking the physical address in accordance with the value set by the mask register corresponding to this memory input bit; a plurality of logical operation circuits being provided in correspondence with each of the plurality of memory input bits, the plurality of logical operation circuits respectively outputting bit data obtained by performing a predetermined logical operation on a masking result by the mask arithmetic circuit as the memory input bit; and an address supplier that supplies the memory input address including the plurality of memory input bits output from the plurality of logical operation circuits to the device under test.