Patent ID: 7814650

Claim:
A method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas, the method comprising: constructing contact openings over a first portion of the active areas and conductor openings over second portions of the active areas; depositing a first conductive material into the contact openings to form contacts and into the conductor openings to form conductors; forming a trench through an upper portion of a plurality of the contacts and portions of the dielectric layer, the trench having a first sidewall and a second sidewall, wherein the trench is between two adjacent conductor openings; fabricating a spacer along at least the first sidewall, the spacer being a dielectric material separate from the dielectric layer; and fabricating a conductive line in the trench, the conductive line electrically coupling the contacts and being electrically insulated from the conductors.