Patent ID: 8587992

Claim:
An SRAM system, comprising: a first circuit comprising: a first input voltage signal connected to a first voltage access unit; a second input voltage signal connected to a second voltage access unit wherein the first input voltage signal has a different value from the second input voltage signal; a first voltage access control unit, connected to a sleep signal, a selection signal, and a data input signal and outputs a first voltage control output signal to the first voltage access unit; a second voltage access control unit, controlled by the sleep signal, the selection signal, and the data input signal, and outputs a second voltage control output signal to the second voltage access unit; and a first output voltage signal connected to the first voltage access unit and the second voltage access unit; a second circuit comprising: the first input voltage signal connected to a third voltage access unit; the second input voltage signal connected to a fourth voltage access unit; a third voltage access control unit, connected to the sleep signal, the selection signal, and a complement of the data input signal, and producing a third voltage control output signal to the third voltage access unit; a fourth voltage access control unit controlled by the sleep signal, the selection signal, and the complement of the data input signal, and producing a fourth voltage control output signal to the fourth voltage access unit; and a second output voltage signal connected to the third voltage access unit and the fourth voltage access unit; and an SRAM cell comprising: a storage unit configured to receive the first output voltage signal generated by the first circuit and the second output voltage signal generated by the second circuit, and to maintain a first stored value signal and a second stored value signal, wherein when the first stored value signal is of value 0, the second stored value signal has a value equal to the second output voltage signal, and when the second stored value signal is of value 0 the first stored value signal has a value equal to the first output voltage signal; a first access unit connected to the first stored value signal and controlled by a word line signal, configured to read the first stored value signal to a first bit line signal or to write the value of the first bit line signal to the first stored value signal; a second access unit connected to the second stored value signal and controlled by the word line signal, configured to read the second stored value signal to a second bit line signal or to write the value of the second bit line signal to the second stored value signal.