Patent ID: 7968375

Claim:
A method of fabricating a semiconductor device, the method comprising: forming through die vias (TDVs) each extending from a first side of a first substrate towards a second side of the first substrate; forming conductive interconnect on the first side of the first substrate, the conductive interconnect being electrically coupled to the TDVs; patterning at least one metal layer on the second side of the first substrate to form at least one plate of at least one metal-insulator-metal (MIM) capacitor, the at least one MIM capacitor being electrically coupled to at least one of the TDVs; forming a second metal layer on a first side of a second substrate to form a second plate of the at least one MIM capacitor; patterning an insulator layer on one of the first side of the second substrate or the second side of the first substrate to form a dielectric of the at least one MIM capacitor; and mounting the first side of the second substrate to the second side of the first substrate to form a stacked integrated circuit.