Patent ID: 7606694

Claim:
A system for performing cycle accurate simulation of a circuit design comprising: a computer executing program code, wherein the computer: identifies a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function; executes a scheduler, wherein the scheduler: executes each said cycle accurate model at clock cycle boundaries during a simulation session in an order that is independent of dependencies among individual ones of the plurality of cycle accurate models; first determines, during the cycle accurate simulation, whether at least one of the plurality of cycle accurate models indicates a conflict relating to execution order between at least two of the plurality of cycle accurate models according to whether each cycle accurate model returns a flag, wherein the scheduler does not track data dependencies among cycle accurate models other than identifying whether a flag is returned in consequence of executing the plurality of cycle accurate models; and calls an asynchronous output function of each of the plurality of cycle accurate models for a selected clock cycle boundary of the simulation until each asynchronous output function indicates that no conflict exists.