Patent ID: 7196372

Claim:
A memory device, comprising: a substrate; an insulating layer formed on the substrate; a fin structure formed on the insulating layer, the fin structure having a first and second side surface and a top surface; a dielectric cap formed over the top surface of the fin structure; a first spacer formed adjacent the first side surface, the first spacer acting as a first floating gate for the memory device; a second spacer formed adjacent the second side surface, the second spacer acting as a second floating gate for the memory device; a gate dielectric layer formed on the first and second spacers and over the dielectric cap, the gate dielectric layer contacting the insulating layer and acting as an inter-gate dielectric for the memory device; a first gate contacting the insulating layer and disposed on a first side of the fin; and a second gate contacting the insulating layer and disposed on a second side of the fin opposite the first side, wherein the first and second gates are electrically isolated from each other.