Patent ID: 7539242

Claim:
A semiconductor integrated circuit device comprising: a first receiver including a first clock data recovery circuit capable of receiving serial data, recovering a clock from the received serial data, and changing a phase of a clock to be generated; a first transmitter including a first serializer which converts parallel data into serial data synchronized with a transmit clock in a first test operation, and which converts the parallel data into the serial data synchronized with the clock modulated by the first clock data recovery circuit with an external phase control, independent of the received serial data in the first clock data recovery circuit in a second test operation; a second receiver including a second clock data recovery circuit capable of receiving serial data, recovering a clock from the received serial data, and changing a phase of a clock to be generated; a second transmitter including a second serializer which converts parallel data into serial data synchronized with a transmit clock in the second test operation, and which converts the parallel data into the serial data synchronized with the clock modulated by the second clock data recovery circuit with an external phase control, independent of the received serial data in the second clock data recovery circuit in the first test operation, the first clock data recovery circuit being tested in the first test operation, the second clock data recovery circuit being tested in the second test operation.