Patent ID: 8564463

Claim:
A method for use with a digital-to-analog converter (DAC), the method comprising: (a) accepting an N bit digital input code at an input of the DAC; (b) selecting a first correction code from a first set of correction codes based on a portion of the N bit digital input code, wherein the first set of correction codes are used to reduce to a range of Integrated Non-Linearity (INL) values, to thereby improve linearity of the DAC; (c) selecting a second correction code from a second set of correction codes based on a portion of the N bit digital input code, wherein the second set of correction codes are used to ensure that all values of Differential Non-Linearity (DNL)>−1, and thereby ensure that the DAC is monotonic; (d) producing an N+M bit digital output code based on the N bit digital input code accepted at step (a), the first correction code selected at step (b), and the second correction code selected at step (c); and (e) converting the N+M bit digital output code to an analog output signal, wherein the analog output signal or a buffered version thereof is the analog output of the DAC.