Patent ID: 7073117

Claim:
An apparatus for testing sufficiency of power distribution in a forward error correction (FEC) system, the apparatus comprising: a bit sequence generator configured to generate bit sequences; an FEC encoder, the FEC encoder being configured to encode bit sequences generated by the bit sequence generator; an FEC error vector generator, the FEC error vector generator being configured to generate error vectors and to utilize the error vectors to insert a number of errors into the encoded bit sequences to produce encoded bit error sequences; an FEC decoder, the FEC decoder being configured to decode the encoded bit error sequences and to correct any errors in the decoded sequences when the power supply is sufficient and to not correct all of the errors when the power supply is insufficient; and a detector, the detector being configured to analyze the decoded sequences and determine whether bit errors exist in the decoded sequences; and an indicator for indicating insufficient power distribution when the detector determines bit errors exist in the decoded sequence.