Patent ID: 8530930

Claim:
A semiconductor device comprising: a plurality of insulated gate type switching cells, each insulated gate switching cell having a base layer, an emitter layer formed in the base layer and a gate electrode formed on the emitter layer through an insulated layer; an emitter electrode that is commonly provided to cover the plurality of insulated gate switching cells, the emitter electrode being formed on the emitter layer; a bonding wire connected to the emitter electrode, a gate driving voltage being applied to the gate electrode of each insulated gate switching cell so that emitter current flows through the emitter electrode, wherein the emitter layer is configured to have an emitter rate varied in accordance with a distance from a connection portion of the bonding wire to the emitter electrode so that the emitter current flowing through the emitter electrode is substantially equal among the plurality of insulated gate switching cells, the emitter rate being defined by a ratio of an area of the emitter layer to a unit area of the base layer; and wherein each insulated gate switching cell comprises a base layer, an emitter layer formed in the base layer, the gate electrode formed on the emitter layer through an insulated layer and the emitter electrode formed on the emitter layer, and the mutual conductance of each insulated gate switching cell is varied by varying the emitter rate of the emitter layer in the base layer.