Patent ID: 8237250

Claim:
A semiconductor package, comprising: a carrier having a die pad, and a plurality of leads, wherein the leads include a plurality of first leads disposed around the die pad, a plurality of second leads disposed around the first leads, and a connecting portion that directly connects one of the plurality of first leads with one of the plurality of second leads; a chip, disposed on the die pad; a wire that connects the chip to at least one of the plurality of first leads; and a molding compound, encapsulating the chip, the wire, and portions of the first leads, the second leads, and the connecting portion; wherein: the connecting portion has a lower surface at least a portion of which is substantially coplanar with a lower surface of the one of the plurality of first leads; a lower surface of the one of the plurality of first leads is substantially coplanar with a lower surface of the molding compound; and the one of the plurality of second leads protrudes from a lower surface of the molding compound.