Patent ID: 7941794

Claim:
An apparatus having data flow graph (DFG) processor, which processes a DFG necessary for configuration of a reconfigurable circuit capable of changing functions, comprising: a central processing unit; a dividing unit which divides a program describing target operations into two or more subprograms; a DFG generating unit which generates, using the central processing unit, a plurality of DFGs corresponding to the two or more subprograms in accordance with a description in the program, the DFGs representing dependency in execution between the target operations of the program carried out in sequence, wherein the generating unit generates, when a branching process is detected in the program, a first DFG of the plurality of DFGs indicating a process before the branching process, and a second DFG of the plurality of DFGs indicating a process after the branching process, and at least either one of the first DFG or the second DFG includes a process for determining a destination of the branching process; a flow data generating unit which generates flow data indicating the order of execution of the DFGs based on the generation by the DFG generating unit; and a configuration data generating unit which converts the DFGs into corresponding configuration data for mapping the DFGs into the reconfigurable circuit and defining the functions in the reconfigurable circuit.