Patent ID: 8533367

Claim:
A memory device comprising: a memory; and a controller configured to: receive a first command, a second command, and a third command, return a response indicating whether the memory device supports the third command in response to the second command, in response to the third command, execute a process in accordance with the third command and shift to a low power mode, not set a normal termination indicating flag when power supply to the memory device has been cutoff before completion of the shift to the low power mode, execute a first initializing process in response to (1) the first command received after supplying a power to the memory device and (2) a fail of the process in accordance with the third command being received before a power supply to the memory device was stopped a previous time prior to power again being supplied to the memory device, and execute a second initializing process in response to (1) the first command received after supplying the power to the memory device and (2) a success of the process in accordance with the third command being received before the power supply to the memory device was stopped the previous time prior to power again being supplied to the memory device; wherein the second initializing process is completed quicker than the first initializing process; and the first and second initializing processes are alternative processes executed for the memory device to be ready to be written and read by a request from a host.