Patent ID: 7932708

Claim:
A power converter, comprising: a delay control circuit; a power on reset (POR) circuit, receiving a power supply voltage for turning on the power converter, wherein the POR circuit enables the delay control circuit to operate and set a sampling time; a pulse width modulation (PWM) generator, having an output pin, the PWM generator being coupled to the delay control circuit, and the output pin being coupled to a resistance, wherein during the sampling time, the PWM generator suspends outputting signals, and a sampling current source outputs a sampling current to the resistance; a voltage sampling circuit, for detecting a voltage level of the output pin during the sampling time; an analog-to-digital converter (ADC), coupled to the voltage sampling circuit for receiving the voltage level and converting the received voltage level into an address selection signal; an address setting circuit, coupled to the ADC for receiving the address selection signal, and determining a setting of an SMBus slave address according to the address selection signal; and an SMBus slave device controller, coupled to the address setting circuit for receiving the setting of the SMBus slave address, and latching up the setting of the SMBus slave address, for subsequently communicating data with an SMBus master device controller, wherein when the sampling time terminates and the setting of the SMBus slave address is completed, the PWM generator outputs a PWM signal from the output pin.