Patent ID: 6892256

Claim:
A system for automatically updating the revision level of programmable devices comprising: a master programmable device having pulse receiving logic and a memory space operatively disposed therein, wherein said master programmable device is a one of group consisting of a field programmable gate array and an erasable programmable logic device and wherein said memory space includes a revision resister containing one or more memory locations, each one of said memory locations stores revision information for corresponding to one at least one particular slave programmable device, the revision information including the revision number of the software used to configure said at least one slave programmable device; and at least one slave programmable device having pulse generating logic operatively disposed therein, said slave programmable device coupled to said master programmable device through an interface and configured to send revision information to said master programmable device responsive to generating said revision information in response to receiving a reset signal wherein said at least one slave programmable device is a one of group consisting of a field programmable gate array and an erasable programmable logic device.