Patent ID: 7271056

Claim:
A method of fabricating a trench capacitor dynamic random access memory (DRAM) device, comprising: providing a semiconductor substrate having thereon a pad layer; forming an first opening in said pad layer; using said pad layer as an etching hard mask, dry etching said semiconductor substrate through said first opening to form a first trench; filling said first trench with insulating material to form a shallow trench isolation (STI) region; forming a mask layer over the semiconductor substrate, wherein said mask layer has at least a second opening that exposes a portion of said STI region and a portion of said pad layer; using said mask layer as an etching hard mask, dry etching exposed said STI region and pad layer through said second opening to form a second trench, wherein said second trench is a step trench; forming a trench capacitor within said second trench; performing a thermal oxidation process to oxidize a top portion of said trench capacitor, thereby forming an insulating oxide layer; stripping said pad layer to expose said semiconductor substrate; rowing a gate oxide layer on the exposed said semiconductor substrate; and forming a switch gate on said gate oxide layer, and a pass gate on said insulating oxide layer.