Patent ID: 8519482

Claim:
A method for forming a device comprising: providing a substrate prepared with first and second contact regions and a dielectric layer over the contact regions; forming first and second transistors over the substrate, wherein each of the transistors includes a gate conductor with first and second source/drain (S/D) regions; forming an etch stop layer over the transistors which causes a buried void to be formed in the dielectric layer; forming first and second vias in the dielectric layer, the first via is in communication with the first contact region and the second via is in communication with the second contact region, wherein the buried void provides a communication path between the first and second vias; at least partially filling the vias and buried void with a dielectric filler, wherein the dielectric filler fills the vias to at least a height of the etch stop layer, and wherein the partially filled buried void blocks the communication path between the first and second vias created by the buried void; removing the dielectric filler in the vias, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias; and forming contact plugs in the vias.