Patent ID: 8565341

Claim:
A power amplifier comprising: an envelope detector configured to sense an envelope component of an input signal; a limiter comprising a PMOS (Positive channel Metal Oxide Semiconductor) transistor configured to sense a first phase component of the input signal and an NMOS (Negative channel Metal Oxide Semiconductor) transistor configured to sense a second phase component of the input signal, the first phase component having a first second-order distortion controlled within a predetermined range with respect to the input signal, the second phase component having a second second-order distortion; a combiner configured to combine the envelope component sensed by the envelope detector and the phase component sensed by the limiter to generate an output signal; and a bias controller configured to control a bias of the limiter to cancel the first second-order distortion by the second second-order distortion, the bias controller comprising a current sensor configured to sense an operating current of the limiter, a controller configured to convert an analog signal indicating the operating current sensed by the current sensor into a digital signal and generate a control parameter based on the digital signal, and a bias generator configured to generate a bias current or a bias voltage based on the control parameter.