Patent ID: 7161961

Claim:
A device ( 100 ) for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, said device comprising at least two ports ( 102 to 108 )) for receiving said at least two data signals, a port scanning unit ( 110 ) for extracting data from the data signals received by said ports, characterized in that said port scanning unit ( 110 ) is configured to extract data from ports providing data streams having at least two different input data rates, a control logic unit functionally connected to said port scanning unit ( 110 ) for determining which of said at least two ports need to be handled within which clock cycle with regard to its input data rate, a central buffer connected to said port scanning unit ( 110 ) into which data from all ports are written, wherein the control logic unit is configured to control said port scanning unit ( 110 ) to read per access from all ports the same amount of data and writing the data from a port having a higher input data rate proportionally more often into said central buffer than from a port having a lower input data rate, and a byte alignment unit functionally connected to the central buffer to ensure that only frame byte aligned data are written into said central buffer.