Patent ID: 8652902

Claim:
A method comprising: providing a semiconductor-on-insulator substrate comprising: a semiconductor base layer, a dielectric layer on and in contact with the semiconductor base layer, and a monocrystalline semiconductor top layer on and in contact with the dielectric layer; forming at least two trenches in the semiconductor-on-insulator substrate, wherein the at least two trenches extend through the top layer and the dielectric layer and extend partially through the base layer; as a result of forming the at least two trenches, forming at least one elevated structure comprising: a base portion comprising a portion of the base layer, a dielectric portion comprising a portion of the dielectric layer, wherein the dielectric portion is on and in contact with the base portion, and a top portion comprising a portion of the top layer, wherein the top portion is on and in contact with the dielectric portion; forming isolation regions at a bottom of the at least two trenches, wherein forming the isolation regions comprises partially filling the at least two trenches; thermally oxidizing exposed sidewall surfaces of at least the top portion, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.