Patent ID: 7414458

Claim:
A power gating circuit of a signal processing system comprising: a low dropout linear regulator comprising: a first transistor having a gate, a source coupled to a first voltage, and a drain; an operational amplifier having a first input end coupled to a reference voltage circuit, a second input end, and an output end coupled to the gate of the first transistor; a first resistor having one end coupled to the drain of the first transistor, and the other end coupled to the second input end of the operational amplifier; a second resistor having one end coupled to the second input end of the operational amplifier and the first resistor, and the other end coupled to the ground; and an output end between the drain of the first transistor and the first resistor, for outputting a second voltage; an output circuit comprising: a fourth transistor having a gate, a source coupled to the first voltage, and a drain; and a step-down circuit coupled between the output end of the low dropout linear regulator, a control signal, and the drain of the fourth transistor, for outputting voltage; and a control circuit for controlling output voltage of the output circuit according to the control signal, the control circuit comprising: a control signal reception end for receiving the control signal; a second transistor having a gate, a source coupled to the first voltage, and a drain; an inverter having one end coupled to the control signal reception end, and the other end coupled to the gate of the second transistor, for inverting the control signal received by the control signal reception end and transmitting to the gate of the second transistor; and a third transistor having a gate coupled to the control signal reception end, a source coupled to the gate of the first transistor, and a drain coupled to the drain of the second transistor and the gate of the fourth transistor.