Patent ID: 7952147

Claim:
A semiconductor device comprising: an analog NMOS transistor disposed on a substrate; a compressively-strained-channel analog PMOS transistor disposed on the substrate; a first etch stop liner (ESL) covering the analog NMOS transistor and having a hydrogen concentration of less than 1×10 21 /cm 3 ; and a second ESL covering the compressively-strained-channel analog PMOS transistor, wherein the second ESL is a compressive strain liner, wherein relative measurements of flicker noise power for the analog NMOS transistor and the compressively-strained-channel analog PMOS transistor, as compared to corresponding measurements of flicker noise power for a reference unstrained-channel analog NMOS and PMOS transistors, respectively at a frequency of 500 Hz is less than 1, and the reference unstrained-channel analog NMOS and PMOS induce a stress of less than ±|2| Gdyne/cm 2 .