Patent ID: 8539209

Claim:
A microprocessor configured to perform a full breakpoint check on a cache line-crossing load/store operation (CLCLSO), the CLCLSO specifying a load/store virtual address of data, wherein a first piece of the data is within a first cache line and a second piece of the data is within a second cache line, the microprocessor comprising: a breakpoint register configured to store a breakpoint address; a queue of entries, wherein each of the entries includes first storage for storing an address associated with a respective load/store operation and second storage for storing an indicator that indicates whether there is a match between a page address portion of a load/store virtual address specified by the respective load/store operation and a page address portion of the breakpoint address, wherein the CLCLSO is one of the respective load/store operations; and a load/store unit pipeline coupled to the breakpoint register and the queue, wherein the load/store unit pipeline is configured to execute the CLCLSO during first and second passes through the load/store unit pipeline to access the first and second pieces of the data, respectively, with a cache memory; wherein during the first pass, the load/store unit pipeline performs a first piece breakpoint check using the load/store virtual address specified by the CLCLSO, populates the indicator in the second storage associated with the CLCLSO, and populates the first storage associated with the CLCLSO with a load/store physical address resulting from translation of the load/store virtual address specified by the CLCLSO; wherein during the second pass, the load/store unit pipeline performs a second piece breakpoint check using the indicator received from the second storage associated with the CLCLSO and an incremented version of a page offset portion of the load/store physical address received from the first storage associated with the CLCLSO; wherein the load/store unit pipeline is configured to access the cache memory and perform the full breakpoint check for the CLCLSO in no more than two passes through the load/store unit pipeline; and wherein the first storage in each of the queue entries is the only storage for storing an address associated with the respective load/store operation.