Patent ID: 7534720

Claim:
A method for fabricating a semiconductor device, the method comprising the steps of: sequentially forming an etch-stop layer and an inter-metal dielectric layer on a semiconductor substrate where lower metal wiring is formed; forming a first preliminary via hole for exposing portions of the etch-stop layer by selectively etching the inter-metal dielectric layer; forming a step in the etch-stop layer by removing portions of the exposed etch-stop layer, the step being formed at a boundary between a recessed portion exposed at a bottom surface of the first preliminary via hole and a raised portion covered with the inter-metal dielectric layer; forming a second preliminary via hole for exposing the portions of the recessed and raised portions by expanding the first preliminary via hole by removing lateral portions of the first preliminary via hole, the second preliminary via hole comprising an upper region and a lower region; forming a sacrificial layer within the second preliminary via hole; forming a trench in the upper region of the second preliminary via hole that is wider than and is connected to the lower region of the second preliminary via hole by selectively etching the inter-metal dielectric layer; removing the sacrificial layer to expose the raised portion and recessed portion at a bottom surface of the lower region of the second preliminary via hole; forming a via hole for exposing the lower metal wiring and forming a slope at lower sides of the via hole by anisotropically etching the exposed recessed and raised portions; forming a seed layer for covering the exposed tower metal wiring and the inter-metal dielectric layer having the via hole; forming a metal layer on the seed layer; and patterning the metal layer and the seed layer.