Patent ID: 7189998

Claim:
A thin film transistor array panel, comprising: an insulating substrate; a gate wire including a gate line formed on the insulating substrate and a gate electrode connected to the gate line; a gate insulating layer formed on the gate wire; a data line formed on the gate insulating layer and crossing the gate line, the data line comprising an amorphous silicon layer, a doped amorphous silicon layer and a metal layer; a channel portion formed of the amorphous silicon layer on the gate insulating layer over the gate electrode; a source electrode connected to the data line, wherein at least a portion of the source electrode is formed on the channel portion; a drain electrode formed on the channel portion and spaced apart from the source electrode; a passivation layer covering the data line, the channel portion and the gate insulating layer, and having a contact hole exposing at least a portion of the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole, wherein the amorphous silicon layer of the data line has a portion narrower than the metal layer of the data line, and wherein the passivation layer covering the data line has a groove formed under the metal layer of the data line.