Patent ID: 7213133

Claim:
A method for avoiding write-after-write (WAW) hazards while speculatively executing instructions on a processor in an execute-ahead mode, comprising: issuing instructions for execution in program order during a normal execution mode; upon encountering an unresolved data dependency during execution of an instruction, generating a checkpoint, deferring the instruction, and executing subsequent instructions in the execute-ahead mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, wherein other non-deferred instructions are executed in program order, and wherein dependency information is maintained for each register indicating whether or not a value in the register depends on an unresolved data dependency; if an unresolved data dependency is resolved during the execute-ahead mode, executing deferred instructions in a deferred mode, wherein deferred instructions that are able to be executed are executed in program order, and other deferred instructions that still cannot be executed because of unresolved data dependencies are deferred again; and while executing a deferred instruction, if dependency information for an associated destination register indicates that a WAW hazard potentially exists with a following non-deferred instruction, the method further comprises executing the deferred instruction to produce a result, and forwarding the result to be used by subsequent instructions in a pipeline andlor deferred queue for the processor, without committing the result to the architectural state of the destination register, thereby making the result available to the subsequent instructions without overwriting a result produced by the following non-deferred instruction.