Patent ID: 8791762

Claim:
A method, comprising: obtaining a phase lock loop device operable for coupling with an oscillator that generates an arbitrary frequency, wherein the phase lock loop device comprises a plurality of integer dividers without utilizing a fractional divider; accessing divider information utilizing a processor, the divider information comprising groups of integer divider settings and frequency deviations corresponding to each of the groups of integer divider settings, wherein the groups of integer divider settings are for at least three integer dividers of the phase lock loop device, and wherein each deviation of the frequency deviations is based on a frequency differential between a standard operating frequency and an output frequency for the phase lock loop utilizing one group of integer divider settings from the groups of integer divider settings; determining operating parameters for the phase lock loop device; selecting a desired group of integer divider settings from the groups of integer divider settings based on the frequency differential and the operating parameters of the phase lock loop device, wherein a first integer divider of the at least three integer dividers is coupled to an output of a voltage controlled oscillator of the phase lock loop device, wherein the phase lock loop device includes a feedback loop having a mixer and a second integer divider of the at least three integer dividers, wherein the feedback loop is coupled to the output of the voltage controlled oscillator and a phase frequency detector, wherein the phase lock loop device utilizes a pre-synthesizer circuit that is coupled between the oscillator and a third integer divider of the at least three integer dividers, wherein the pre-synthesizer circuit comprises an auxiliary voltage controlled oscillator, an auxiliary phase frequency detector and a single fourth integer divider without utilizing a fractional divider, wherein the single fourth integer divider is in a pre-synthesizer feedback loop coupled between the auxiliary voltage controlled oscillator and the auxiliary phase frequency detector, and wherein the pre-synthesizer circuit provides the third integer divider with an intermediate reference frequency; providing, from the phase lock loop device, a modified output frequency signal to a system according to configuring of the phase lock loop device based on the desired group of integer divider settings, wherein the system is coupled to an output of the phase lock loop device; receiving a radio frequency signal of known frequency; generating a tuning signal based on a comparison of the radio frequency signal with the modified out frequency signal; and providing the tuning signal to the oscillator to enable adjustment of the arbitrary frequency by the oscillator.