Patent ID: 7289369

Claim:
A DRAM array comprising: a plurality of rows of DRAM cells, each of said rows being selected by a word line; and a plurality of columns of said DRAM cells, each of said columns comprising: a plurality of column segments, each of said colunm segments including DRAM cells in two or more of said plurality of rows connected to a local bit line and a clamp device selectively gated by a hold enable and connected at a conduction terminal to said local bit line, said clamp device being gated off when one of said DRAM cells is selected, and a global bit line, contents on each said local bit line being coupled to said global bit line, wherein said global bit line is a global read bit line, each of said columns further includes a global write bit line, and each of said column segments further comprises a write device gated by a write select line and connected between said global write bit line and said local bit line.