Patent ID: 7035962

Claim:
A memory system comprising: a memory controller; a separate unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus; a separate bidirectional data bus coupled to the memory controller, the memory controller communicating data information to the bidirectional data bus for a write operation and receiving the data information from the bidirectional data bus during a read operation; a plurality of N memory modules, wherein each of the memory modules includes: a plurality M of memory devices, wherein each memory device internally contains a data in and a data out buffer, a column decoder and a row decoder; a first register directly connected between the separate unidirectional command and address bus and the plurality of memory devices, the first register receiving and latching the commands and addresses from the separate unidirectional command and address bus and driving the commands and addresses to the plurality of memory devices in the memory module; and a second, data register directly connected between the plurality of memory devices and the separate bidirectional data bus, the data register receiving and latching the data information from the separate bidirectional data bus and driving the data information to the data in buffers of the plurality of memory devices for a write operation, the data register receiving and latching the data information from the data out buffers of the plurality of memory devices and driving the data information to the separate bidirectional data bus for a read operation; a socket adapted to receive the memory module and to couple the memory module to the unidirectional command and address bus and to the bidirectional data bus; and wherein a first load on the command and address bus is equal to N devices and a second load on the data bus is equal to N devices where the total number of memory devices is N*M.