Patent ID: 8569838

Claim:
An integrated circuit formed at a semiconducting surface of a body, comprising: at least one active area at the semiconducting surface; a plurality of electrodes formed at a gate level in the integrated circuit, each electrode extending for a length in a common direction with others of the plurality of electrodes, each electrode having a width at about a critical dimension for the integrated circuit, the critical dimension corresponding to a minimum photolithographically patterned feature size for the integrated circuit, the plurality of electrodes disposed relative to one another at a substantially constant pitch within a preselected range; an isolation dielectric structure disposed at the surface, and defining the boundary of the at least one active area; and the at least one interconnect, formed at the gate level in the integrated circuit, and disposed over the isolation dielectric structure, the at least one interconnect having a width at about the critical dimension for the integrated circuit, the at least one interconnect having a portion disposed at a location overlying the isolation dielectric structure that has a length extending in a direction substantially perpendicular to the common direction of the plurality of electrodes; wherein the plurality of electrodes and the the at least one interconnect are formed by a process comprising the steps of: depositing a conductor layer over the at least one active area and isolation dielectric structure; photolithographically patterning and etching the conductor layer using a photomask defining features in the conductor layer in which, for each of the plurality of electrodes that has a portion disposed over the isolation dielectric structure having an end located closest to the at least one interconnect, that end is disposed at a distance from the at least one interconnect between about 1.00 and about 1.20 times the nominal spacing of photomask features defining the electrodes, or greater than about 1.80 times the pitch.