Patent ID: 6949783

Claim:
A memory cell transistor of a DRAM device, comprising: a gate stack pattern formed on a semiconductor substrate; a DC node and a BC node formed substantially under lateral sides of the gate stack pattern in the semiconductor substrate, the DC node and the BC node being electrically connected to a bit line and a storage electrode of a capacitor, respectively; a first source/drain junction region formed under the DC node and a second source/drain junction region formed under the BC node, wherein the first source/drain junction region has a profile which is different from that of the second source/drain junction region, and wherein the first source/drain junction region and second source/drain junction region are formed with a same first impurity, and wherein the source/drain junction regions comprise source/drain ion injection regions and plug ion injection regions formed under the DC node and the BC node; and a compensation ion injection region formed in the plug ion injection region under the DC node, wherein the compensation ion injection region is formed with a second impurity.