Patent ID: 7836290

Claim:
An apparatus comprising: a speculative execution processor pipeline; a first structure for maintaining return addresses relative to instruction flow at a first stage of the pipeline; a second structure for maintaining return addresses relative to instruction flow at a second stage of the pipeline which is deeper in the pipeline than the first stage; a third structure for maintaining return addresses relative to instruction flow at a third stage of the pipeline, wherein said third stage is deeper in the pipeline than the second stage; and circuitry, coupled to said first, second, and third structures, (1) to use return addresses in said second structure to restore return addresses in said first structure upon occurrence of at least a first event; and (2) to use return addresses in said third structure to restore return addresses in said first and second structures upon occurrence of at least a second event, wherein said second event is different from said first event, wherein: the second structure is configured to update when a structure-affecting instruction progressing through the pipeline is known to be non-speculatively executed; and the third structure is configured to update after a structure-affecting instruction reaches a point in execution in which all previous instructions relative to the structure-affecting instruction have executed without a particular event occurring.