Patent ID: 8307160

Claim:
An interface generation apparatus comprising: a stream converter to receive write addresses and write data, to store the received data in a buffer, and to sort the write data stored in the buffer in the order of the write addresses to output the write data as stream data; a cache memory to store received stream data in a storage device if a load signal is in a state of indicating that it is necessary that the stream data are loaded and to output data stored in the storage device corresponding to a cache address as cache data if the cache address is input; a controller to determine whether or not data allocated with address information on reading have already been loaded on the cache memory, to output the load signal instructing loading on the cache memory if the allocated data are not loaded on the cache memory as a result of the determination, and to output a load address indicating a load-completed address of the cache memory; at least one address converter to calculate a value representing which of storage devices of the cache memory the data allocated with the read address are stored in, by using the load address indicating the load-completed address of the cache memory, to output the calculated value as the cache address to the cache memory, and to output the cache data input from the cache memory as read data; and an interface generation configuration apparatus that determines a capacity of the cache memory by extracting values and equations output as address information on reading, calculates differences among combinations of extracted addresses and sets a value to the capacity by adding a predetermined value to a maximum value among the calculated differences.