Patent ID: 8420411

Claim:
A method for aligning a wafer stack, comprising: providing a wafer stack comprising a top wafer with a top mark and a bottom wafer with a bottom mark, wherein said top mark and said bottom mark are capable of corresponding to each other, wherein said top mark comprises a first pad, a second pad, a third pad and a fourth pad which are disposed on said top wafer and comprises at least one monitoring via which is disposed in said top wafer and electrically connected to said first pad and to said second pad, and said bottom mark comprises a first bottom pad and a second bottom pad which are electrically connected to each other, wherein said first bottom pad corresponds to said monitoring via and said second bottom pad corresponds to said third pad and to said fourth pad so that said monitoring via is capable of being simultaneously electrically connected to said third pad and to said fourth pad by means of said first bottom pad to obtain said electrical reading when said top mark and said bottom mark are aligned with each other; adjusting a relative position between said top wafer and said bottom wafer so that said top mark and said bottom mark are in direct contact with each other; applying an electrical signal on said top mark to obtain an electrical reading; and optimizing said electrical reading to substantially align said wafer stack.