Patent ID: 7023726

Claim:
A hybrid MRAM architecture adapted to a controlling device for accessing the specific bit of information, comprising: a plurality of first MRAM arrays composed of a plurality of MRAM cells each of which has a 1T1MTJ architecture; a plurality of second MRAM arrays composed of a plurality of MRAM cells each of which has an XPC architecture; an address line for transmitting an address signal from said controlling device; an access decoder for respectively connecting to said first MRAM arrays, said second MRAM arrays and said address line, in which said specific bit of information is accessed from either said first MRAM arrays or said second MRAM arrays selected in accordance with said address signal transmitted by said address line; a sensing and writing circuit connected to said access decoder to amplify said specific bit of information read from said access decoder; and at least one I/O bus connected to said sensing and writing circuit to transmit said specific bit of information to said controlling device.