Patent ID: 7203105

Claim:
A semiconductor memory device comprising a plurality of nonvolatile memories and a controller which controls read/write operations for said plurality of nonvolatile memories through a first memory bus and a second memory bus in accordance with read/write commands from a host apparatus, wherein when a case where a nonvolatile memory F 0 is connected to said first memory bus and a nonvolatile memory F 1 is connected to said second memory bus is referred to as a two-memory configuration and a case where two nonvolatile memories F 0 , F 2 are connected to said first memory bus and two nonvolatile memories F 1 , F 3 are connected to said second memory bus is referred to as a four-memory configuration, said controller comprises: a selection section which selects one of said two-memory configuration and said four-memory configuration; a sequential number conversion section which divides each nonvolatile memory into two regions to form a first half region and last half region, and converts a consecutive logical address specified by said host apparatus to a logic sequential number of a predetermined size; a modulo number generation section which generates a logic sequential modulo number of system of residues of 4 with respect to said logic sequential number; and a write control section which performs a write operation in a format that selectively and repeatedly circulates through the nonvolatile memories F 0 , F 1 , F 2 , F 3 in case of said four-memory configuration and performs the write operation in a format that selectively and repeatedly circulates through the first half region of F 0 , the first half region of F 1 , the last half region F 0 , and the last half region F 1 in case of said two-memory configuration based on said sequential modulo number when the write command to the consecutive logical address is made from said host apparatus.