Patent ID: 8094480

Claim:
A semiconductor device comprising: a plurality of memory cells including memory elements to store information by varying resistance values of the memory elements; and a reference system circuit enabling a measurement of distribution of the resistance values for the plurality of memory cells, wherein the reference system circuit comprises a resistance selection circuit in which a resistance value of a reference resistance to be compared with the resistance values of the memory elements is variable from a first resistance value lower than a minimum resistance value that the memory elements assume up to a second resistance value higher than a maximum resistance value that the memory elements assume, and wherein the resistance selection circuit comprises switches that are serially connected to a plurality of resistance elements having mutually different resistances via respective fuses to form serially-connected bodies, and these serially-connected bodies are connected in parallel, so that before disconnection of the fuses, the reference resistance is formed by selectively combining the plurality of resistance elements according to an externally input control signal, and after selective disconnection of the fuses, the reference resistance is formed by selectively combining the plurality of resistance elements according to the fuse state.