Patent ID: 7095644

Claim:
A re-writable memory, comprising: a substrate; a cross point memory array formed above the substrate, including a first conductive array line; second conductive array lines, each of the second conductive array lines oriented generally substantially perpendicular to the first conductive array line; two-terminal memory plugs, each memory plug having a first terminal in electrical communication with the first conductive array line and a second terminal in electrical communication with one of the second conductive array lines, and each memory plug configured to assume a first electrical resistance that corresponds to a first data state in response to a first voltage and a second electrical resistance that corresponds to a second data state in response to a second voltage; sensing circuits, each sensing circuit in electrical communication with one of the second conductive array lines and an associated one of the memory plugs, each sensing circuit further configured to sense an electrical current passing through said one of the second conductive array lines so as to read the first and second data states from the associated one of the memory plugs, and wherein the sensing circuits are configured to translate the first and second data states into binary information; and address circuits configured to identify selective ones of the sensing circuits for output of said binary information in page mode.