Patent ID: 7973581

Claim:
A flip-flop circuit comprising: a first latch circuit that receives input of a data signal and a rise delay clock signal obtained by delaying only rise of a clock signal, raises a signal of a first node according to the fall of the rise delay clock signal in a state in which the data signal falls, and lowers the signal of the first node according to rise of the rise delay clock signal; a second latch circuit that receives input of the signal of the first node and the clock signal and lowers a signal of a second node at timing when the clock signal falls in a state in which the signal of the first node rises; a third latch circuit that receives input of the signal of the second node and the clock signal and generates an output signal for maintaining the data signal in a state in which the clock signal rises; a pull-down circuit that pulls down the signal of the first node with the rise delay clock signal; and a clocked inverter circuit that is connected to the second node, and that receives the signal of the first node and the clock signal as input such that floating of the second node is prevented by the signal of the first node at a rise of the clock signal, wherein the rise delay clock signal is input to the pull-down circuit, and floating of the first node is prevented by the rise delay clock signal at rise of the clock signal, wherein the clocked inverter circuit includes a fifth p-channel transistor, a sixth p-channel transistor, a seventh n-channel transistor, and an eighth n-channel transistor connected in series, and wherein the first node signal is input to a gate of the fifth p-channel transistor, the signal of the second node is input to gates of the sixth p-channel transistor and the seventh n-channel transistor via an inverter, and the clock signal is input to a gate of the eighth n-channel transistor.