Patent ID: 8232821

Claim:
A clock data recovery circuit comprising: a voltage controlled oscillator configured to generate multi-phase clock signals including a plurality of clock signals, each having a frequency that corresponds to an input control voltage, and having phases shifted from one another such that they are positioned at regular intervals; a phase comparator configured to compare the phase of input data with the respective phases of the plurality of clock signals, and to generate a phase difference signal, including an up signal and a down signal, which represents the comparison result; and a charge pump circuit configured to generate the control voltage such that, when the up signal of the phase difference signal is asserted, the frequency of the voltage controlled oscillator is raised, and when the down signal of the phase difference signal is asserted, the frequency of the voltage controlled oscillator is lowered, wherein the phase comparator comprises a plurality of flip-flops severally arranged for the plurality of clock signals, and each configured to latch the input data at a time point of a corresponding clock signal, a plurality of first logical gates severally arranged for the odd-numbered flip-flops, and configured such that the i-th (i represents an integer) first logical gate generates an internal up signal which is asserted when an output signal of the (2×i−1)-th flip-flop does not match an output signal of the (2×i)-th flip-flop, a plurality of second logical gates severally arranged for the even-numbered flip-flops, and configured such that the j-th (j represents an integer) second logical gate generates an internal down signal which is asserted when an output signal of the (2×j)-th flip-flop does not match an output signal of the (2×j+1)-th flip-flop, a third logical gate configured to generate the up signal based upon the plurality of internal up signals generated by the plurality of first logical gates, and a fourth logical gate configured to generate the down signal based upon the plurality of internal down signals generated by the plurality of second logical gates.