Patent ID: 8138046

Claim:
A process of fabricating a vertical transistor structure of a transistor on a substrate, comprising: forming a first conductive layer over the substrate, the first conductive layer being arranged as one of a source or a drain of the vertical transistor structure; forming an insulating layer over the first conductive layer; forming a second conductive layer over the insulating layer; forming a third conductive layer over the second conductive layer; converting the third conductive layer into an insulating porous membrane; producing a membrane having a stack of porous layers that includes at least the insulating layer, the second conductive layer, and the insulating porous membrane by etching the insulating layer and the second conductive layer using the insulating porous membrane as a mask, said porous layers having substantially stacked pores, and the etched second conductive layer being arranged to form a gate electrode of the transistor; performing oxidization on sidewalls of the stacked pores; producing filaments inside at least some of the stacked pores of the porous layers; and producing an upper conductive layer over the stack of porous layers, the upper conductive layer being arranged as another one of the source or the drain of the vertical transistor structure, and the upper conductive layer and the first conductive layer are connected by the filaments formed inside the at least some of the stacked pores of the porous layers.