Patent ID: 7356745

Claim:
A semiconductor integrated circuit comprising; A. a substrate of semiconductor material; B. functional combinational logic formed on the substrate, the combinational logic including functional flip-flops; C. a group of parallel scan paths formed on the substrate, the group of scan paths including a scan input bus for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output bus for transmitting test response data obtained from the combinational logic, and a control bus for operating the parallel scan paths, each scan path including functional flip-flops of the combinational logic that, in a test mode, are connected in series: D. compare circuitry formed on the substrate, the compare circuitry including a first input bus coupled to the scan output bus to receive the test response data from the group of scan paths, a second input bus to receive expected data, and a fail flag output, the compare circuitry indicating the result of a comparison of the received test response data and the expected data at the fail flag output; and E. one of the scan paths including a scan cell having an input connected to the fail flag output.