Patent ID: 8450807

Claim:
A semiconductor structure comprising: at least one transistor located upon and within a semiconductor substrate, said at least one transistor including a gate stack located on an upper surface of the semiconductor substrate and a source region and a drain region located within the semiconductor substrate at the footprint of the gate stack, wherein at least one of said source region and said drain region has a textured surface that includes a hemispherical grained semiconductor material, said textured surface having at least one peak and at least one valley; a contiguous metal semiconductor alloy disposed on an entirety of the textured surface of the at least one source region and the at least one drain region including the entirety of the at least one peak and the entirety of the at least one valley and spanning the entire length of the at least one of said source region and said drain region, wherein a portion of said contiguous metal semiconductor alloy contacts a spacer located on a sidewall of said gate stack; and a conductively filled via contact formed atop the metal semiconductor alloy, wherein a bottommost surface of said conductively filled via contact is only in direct contact with a portion of said contiguous metal semiconductor alloy that is located in said at least one valley of said textured surface.