Patent ID: 7544533

Claim:
A method of forming a plurality of gate structures in an integrated circuit, the method comprising: providing a substrate; forming a first oxide layer on the substrate for a first plurality of gate structures to be located over a first area of the substrate; conducting a first nitridation process to form a first nitrided oxide layer for at least a portion of the first oxide layer; removing portions of the first oxide layer and first nitrided oxide layer over at least a second area of the substrate where a second plurality of gate structures are to be formed; forming a second oxide layer on the substrate in at least the second area; forming a conductive layer over the first nitrided oxide layer and the second oxide layer in the first and second areas in the first area; in the first and second areas, doping a portion of the conductive layer to a first conductivity type; in at least the first area, doping a portion of the conductive layer to a second conductivity type; in at least one of the first and second areas, maintaining substantially no active dopant concentration in a portion of the conductive layer; patterning the first oxide layer, the first nitrided oxide layer and the conductive layer to form a first plurality of gate stacks for a first plurality of devices; and in the second area, patterning the second oxide layer and the conductive layer to form a second plurality of gate stacks for a second plurality of devices.