Patent ID: 7642153

Claim:
A method of forming a complementary metal oxide semiconductor (CMOS) integrated circuit, comprising the steps of: providing a semiconducting substrate having respective regions for forming NMOS and PMOS devices; forming a plurality of gate stacks on said substrate surface in said NMOS and PMOS device regions, said gate stacks each comprising a polysilicon base layer and a silicon germanium (SiGe) capping layer on said base layer; forming spacers on sidewalls of said plurality of gate stacks; etching said SiGe capping layer, wherein said etching comprises selectively removing said SiGe capping layer simultaneously in said NMOS and PMOS device regions using an etchant that is selective to said polysilicon base layer; after removing said SiGe capping layer, removing at least a portion of said polysilicon base layer simultaneously in said NMOS and PMOS device regions to form a plurality of trenches; and after removing said at least a portion of said polysilicon base layer, forming metal gate electrodes in said trenches.