Patent ID: 8654490

Claim:
An electrostatic discharge (ESD) circuit comprising: a plurality of metal-oxide-semiconductor (MOS) devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors equal in number to the number of MOS devices in said stack of MOS devices and configured as a first resistor ladder, wherein each resistor in said first resistor ladder divides said supply voltage to a source and a drain of one MOS device of said plurality of MOS devices in said stack; a second plurality of resistors equal in number to the number of MOS devices in said stack of MOS devices and configured as a second resistor ladder, wherein each resistor in said second resistor ladder biases said supply voltage to one gate of one MOS device of said plurality of MOS devices in said stack; an inverter device operatively connected to said second plurality of resistors; a time lag circuit that turns said inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of said MOS devices in said stack to said supply voltage upon said inverter device turning off.