Patent ID: 7123057

Claim:
A self-biased comparator circuit comprising: (a) first and second inputs, first and second outputs and a reference voltage conductor; (b) first and second N-channel transistors and first and second current sources; (c) first, second, third and fourth P-channel transistors; (d) sources of the first and second N-channel transistors being coupled to the reference voltage conductor, a gate of the first N-channel transistor being coupled to the first output, a drain of the second N-channel transistor and a drain of the second P-channel transistor, a gate of the second N-channel transistor being coupled to the second output, a drain of the first N-channel transistor and a drain of the first P-channel transistor; and (e) a source and bulk electrode of the third P-channel transistor and a source and a bulk electrode of the second P-channel transistor being coupled to the first input, a source and a bulk electrode of the fourth P-channel transistor and a source and the bulk electrode of the first P-channel transistor being coupled to the second input, a first conductor being coupled to a gate of the first P-channel transistor, a gate and a drain of the third P-channel transistor, and a first terminal of the first current source, a second conductor being coupled to a gate of the second P-channel transistor, a gate and drain of the fourth P-channel transistor, and a first terminal of the second current source, a second terminal of the first current source and a second terminal of the second current source being coupled to the reference voltage conductor, wherein a channel-width-to-channel-length ratio of the first and second P-channel transistors is substantially greater than a channel-width-to-channel-length ratio of the third and fourth P-channel transistors.