Patent ID: 7747973

Claim:
A method of clustering circuit paths for use in modifying an electronic circuit design, the method comprising: identifying at least one group of plural circuit paths, the circuit paths included in the at least one group of circuit paths each including a sequential element or primary port at one end thereof and a sequential element or primary port at the opposite end thereof and also having no sequential element intermediate to the ends thereof, the sequential element being a clocked element, the circuit paths included in the group being connected to at least one other circuit path in the group by an interconnect or a combinational element; clustering a subset of circuit paths comprised of circuit paths from the at least one group of plural circuit paths which do not meet a timing threshold for the electronic circuit design adjusting the placement of circuit components in the clustered subset of circuit paths to modify the electronic circuit design of at least the clustered subset of circuit paths identifying a first circuit path in the at least one group of circuit paths which has a timing characteristic which does not meet the timing threshold; identifying at least one second circuit path in the at least one group of circuit paths which has a timing characteristic which does not meet the timing threshold; adjusting the length of the first and second circuit paths; and rechecking the timing characteristics of the first and second circuit paths.