Patent ID: 8832464

Claim:
A processor, comprising: an instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA); and a cryptographic unit configured to receive instructions for execution from the instruction fetch unit, wherein the instructions include hash instructions defined within the ISA, wherein each of the hash instructions includes opcode bits and is executable by the cryptographic unit to implement a respective hash that is compliant with a respective hash algorithm specification, wherein an opcode encoded in the opcode bits of a given respective hash instruction is sufficient when executed to implement the respective hash; wherein in response to receiving a particular hash instruction defined within the ISA, the cryptographic unit is further configured to retrieve a set of input data blocks from a predetermined set of architectural registers of the processor, and to generate a hash value of the set of input data blocks according to a hash algorithm that corresponds to the particular hash instruction.