Patent ID: 8089446

Claim:
A display device capable of being operated in a full screen refreshing mode and a partial refreshing mode, the display device comprising: a display substrate which comprises a gate line and a data line; and a gate driving unit coupled to the gate line of the display substrate, the gate driving unit being operative to provide a gate signal, the gate driving unit comprising a shift register having a plurality of stages sequentially connected one to the next, wherein at least one of the stages comprises: first and second clock input ports separated from each other and configured to respectively receive a first clock signal and a second clock signal, where the second clock signal is a partial clock signal; first and second control input ports, the first control input port being connected to a previous stage among said sequentially connected stages and the second control input port being connected to a next stage; first and second output ports; a first drive controller that is configured to generate a first control signal responsive to a carry signal received from the previous stage by way of the first control input port, a second drive controller that is configured to generate a second control signal responsive to a reset signal received from the next stage by way of the second control input port, a first drive unit, operatively coupled to the first output port, to the first clock input port and that is configured to output a respective reset signal to the previous stage by way of the first output port and to output a respective carry signal to the following stage also by way of the first output port and in response to the first control signal generated by the first drive controller and the first clock signal received by way of the first clock input port, and a second drive unit, operatively coupled to the second output port, to the second clock input port and that is configured to output a respective gate signal to the gate line by way of the second output port and in response to the first control signal generated by the first drive controller and the partial clock signal received by way of the second clock input port.