Patent ID: 8901655

Claim:
An electronic device, comprising: a semiconductor-on-insulator (SOI) wafer having a SOI layer over a buried oxide (BOX), at least one first set of nanowires patterned in the SOI layer and at least one first set of pads patterned in the SOI layer such that the first set of pads are attached at opposite ends of the first set of nanowires in a ladder-like configuration, and at least one second set of nanowires patterned in the SOI layer and at least one second set of pads patterned in the SOI layer such that the second set of pads are attached at opposite ends of the second set of nanowires in a ladder-like configuration; a conformal gate dielectric layer surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device; a first metal gate stack on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration, and wherein the first set of pads and portions of the first set of nanowires extending out from the first metal gate stack serve as source and drain regions of the transistor device; and a second metal gate stack surrounding, and in direct contact with, a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration, and wherein the second set of pads and portions of the second set of nanowires extending out from the second metal gate stack serve as source and drain regions of the diode device.