Patent ID: 7583559

Claim:
An apparatus, comprising: a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal, the wordline decoder output driver further comprising a first p-type transistor having a source coupled with a drain of a second p-type bank enable transistor and a gate coupled to receive a row decode signal; and a first n-type transistor having a drain coupled with the drain of the first p-type transistor and a gate coupled to receive the row decode signal, the first p-type transistor, the second p-type bank enable transistor, and the first n-type transistor being triple-well transistors; and a second n-type transistor to discharge a parasitic node upon deselection, the second n-type transistor having a source coupled with the source of a first p-type transistor in the wordline decoder output driver and a gate coupled with a gate of a second p-type bank enable transistor, the second n-type transistor being a triple-well transistor and being provided once for each bank of wordlines.