Patent ID: 8369514

Claim:
A method for the secure determination of data comprising: applying in a first processor a mathematical operation with a key to a point of an elliptical curve, wherein the key may be depicted as a binary number with a sequence of bits (b i ) with a first instruction (x) which, when communication to a second processor, leads to a first operation (X) on the contents of at least one register and a second instruction (y), when communicated to the second processor, leads to a second operation (Y), comprising: determining of at least one value (d) in dependence on the two instructions (x, y); initializing of a first auxiliary variable (R) and a second auxiliary variable (S); sequentially performing of the following steps s1-s4 for every bit (b i ) of the key: s1. communicating of the first auxiliary variable (R) to a first register and the second auxiliary variable (S) to a second register of the second processor, s2. assigning, in dependence on the value of the bit (b i ) and on the at least one value (d), of a instruction to an output variable (A) in such a way that either the first instruction (x) is assigned, or the second instruction (y) is assigned, s3. transmitting of the output variable (A) to the instruction register of the second processor, s4. determining of the first (R) and second (S) auxiliary variables updated in the second processor; and outputting, after the termination of the steps for the bit (b i ), of the first (R) and/or the second (S) auxiliary variable and determining a result of the mathematical operation from the first (R) and/or the second auxiliary variable (S) wherein the first operation (X) on register contents of the second processor, which is assigned to the first instruction (x), results in a transposition of the contents of the first and the second register, and in which the second operation (Y) on register contents of the second processor, which is assigned to the second instruction (y), does not result in a transposition of the contents of the first and the second register wherein the first processor communicates the instructions (x) and (y) to the second processor and the second processor performs the operations (X) and (Y) responsive to the instructions.