Patent ID: 7964494

Claim:
An method for producing an integrated circuit arrangement, the method comprising the steps of: forming a plurality of components in a main area of a substrate; producing an inner metallization stratum having a plurality of inner conductive structures, at least one inner conductive structure being formed as an interconnect conducting current parallel to the main area; adjoining the inner metallization stratum with a plurality of outer conductive structures, wherein at least one outer conductive structure adjoins an inner conductive structure in a contact zone, the outer conductive structure being arranged at least partly or completely in a cutout of an electrically insulating insulation layer; forming a contact area at the outer conductive structure; wherein the contact zone does not substantially overlap the contact area in a direction normal to the area of the inner conductive structure that adjoins a bottom of the cutout, and the bottom of the cutout in the normal direction being configured to overlap at least half of the contact area; wherein the outer conductive structure has at least one edge region which adjoins the insulation layer outside the cutout.