Patent ID: 7212450

Claim:
A non-volatile ferroelectric memory device comprising: a plurality of cell array block groups each including a first cell array block and a second cell array block, wherein the first cell array block and the second cell array block each has a hierarchy bit line architecture with one main bit line being selectively coupled to a plurality of sub bit lines to induce a sensing voltage on the main bit line, wherein the first cell array block including a plurality of first unit cells which store a true data, wherein the second cell array block including a plurality of second unit cells which store a complement data, wherein the complement data is opposite to the true data; a sense amp unit amplifying a first sensing voltage on a first main bit line of the first cell array block and a second sensing voltage on a second main bit line of the second cell array block; a common data bus transferring the first sensing voltage on the first main bit line of the first cell array block and the second sensing voltage on the second main bit line of the second cell array block to the sense amp unit; and a colunm selection control unit selectively transferring the first sensing voltage and the second sensing voltage to the common data bus in response to a first column selection signal and a second column selection signal, respectively.