Patent ID: 8294491

Claim:
A flip-flop comprising: a first RS latch including a first pair of NOR gates; and a second RS latch including a second pair of NOR gates; wherein each of the NOR gates employed in the first RS latch and the second RS latch comprises: a resistance connected between a ground and an output of the NOR gate; a fifth transistor to receive, as input, a first input through a gate of the fifth transistor, the fifth transistor being connected between a source power V ss and the output of the NOR gate; and a sixth transistor to receive, as input, a second input through a gate of the sixth transistor, the sixth transistor being connected between the source power V ss and the output of the NOR gate; an input transistor unit to receive, as inputs, an input data signal, an inverted input data signal, and a clock signal, and to provide two outputs to the first RS latch when being connected to an input port of the first RS latch, wherein the input transistor unit comprises: a first transistor to receive, as input, the clock signal through a gate of the first transistor, the first transistor being connected between the input data signal and a first output of the input transistor unit; and a second transistor to receive, as input, the clock signal through a gate of the second transistor, the second transistor being connected between the inverted input data signal and a second output of the input transistor unit; and an intermediate transistor unit to receive, as inputs, two outputs of the first RS latch and an inverted clock signal, and to provide two outputs to the second RS latch when being connected to an input port of the second RS latch, wherein the intermediate transistor unit comprises: a third transistor to receive, as input, the inverted clock signal through a gate of the third transistor, the third transistor being connected between a first output of the first RS latch and a first output of the intermediate transistor unit; and a fourth transistor to receive, as input, the inverted clock signal through a gate of the fourth transistor, the fourth transistor being connected between a second output of the first RS latch and a second output of the intermediate transistor unit.