Patent ID: 7127022

Claim:
A clock and date recovery (CDR) circuit, comprising: a serial data input terminal providing a data stream that includes an encoded transmit clock signal; a delay line phase and frequency detector having a first input terminal coupled to the serial data input terminal, a DCO clock input terminal, and a plurality of output terminals; a filter and control circuit having a plurality of input terminals coupled to the plurality of output terminals of the delay line phase and frequency detector, a DCO clock input terminal, and an output terminal; a dither circuit having an input terminal coupled to the output terminal of the filter and control circuit, a DCO clock input terminal, and an output terminal; and a digitally controlled oscillator (DCO) having an input terminal coupled to the output terminal of the dither circuit, and further having an output terminal coupled to the DCO clock input terminal of the delay line phase and frequency detector, the DCO clock input terminal of the filter and control circuit, and the dither circuit.