Patent ID: 8717057

Claim:
An integrated circuit (IC) package comprising: a plurality of tiers including one or more circuit chips, in which each circuit chip performs a different function; a plurality of circuits under test included in the one or more circuit chips, at least one of the plurality of circuits under test having logical components on different tiers; a tester chip on a different tier from the one or more circuit chips, the tester chip consisting of a test circuit operable to test each of the different functions of the one or more circuit chips within the IC package, the tester chip including an external pin for each of the plurality of circuits, through which each circuit of the IC package is tested, the tester chip operable to communicate with the plurality of circuits through vias, the tester chip including a standardized interface to the one or more circuit chips to test the different functions of the one or more circuit chips; and a memory separate from the tester chip and mounted on one of the plurality of tiers within the IC package, the memory configured to store a program designed to control the test circuit on the tester chip, the test circuit to perform validation testing on the plurality of circuits, the program downloaded to the memory after the memory is positioned in the IC package.