Patent ID: 6927117

Claim:
A method of forming a complementary metal oxide semiconductor structure comprising: providing a planarized structure comprising a plurality of patterned polysilicon gate regions, each having an exposed upper polysilicon-containing surface, located atop a substrate, said substrate having silicided source/drain contacts formed therein; forming a first bilayer comprising a first metal-containing layer, said first metal-containing layer in contact with the exposed upper polysilicon-containing surface of each patterned polysilicon gate region; patterning said first bilayer to provide a patterned structure in which the first bilayer is removed from preselected patterned polysilicon gate regions; forming a second bilayer comprising a second metal-containing layer over the patterned structure, said second metal-containing layer in contact with an exposed upper polysilicon-containing surface of each preselected patterned polysilicon gate regions; and performing a salicide process that converts the first and second metal-containing layers into metal silicides.