Patent ID: 7543205

Claim:
A digital system, comprising: a storage element to drive at least one of a data input and a scan input through the storage element in accordance with a state of a scan enable signal and a timing signal of a clock associated with the storage element, the storage element having a hold loop; a standard input transmission gate to apply the data input to the storage element based on a first input circuitry that considers the state of the scan enable signal and the timing signal of the clock associated with the storage element, the standard input transmission gate coupled to a first end of the hold loop; a scan input transmission gate to apply the scan input to the storage element based on a second input circuitry that considers the state of the scan enable signal and the timing signal of the clock associated with the storage element, the scan input transmission gate coupled to a second end of the hold loon; and a loop transmission gate in the storage element to synchronously close the hold loop in the storage element when the standard input transmission gate is opened upon the timing signal of the clock transitioning to a different state, wherein the loon transmission gate is controlled by the first input circuitry based on a predefined state of the scan enable signal and the timing signal of the clock.