Patent ID: 8443349

Claim:
A computer-implemented method, comprising: at a runtime system running at a parallel-processing computer system that includes multiple types of processing elements having at least two different instruction set architectures, wherein the multiple types of processing elements include two or more of: single-core central processing units, multi-core central processing units, graphics processing units, single-core co-processors and multi-core co-processors: receiving a sequence of operation requests from an application that includes one or more instructions; converting the sequence of operation requests into a sequence of intermediate representation entries, each entry corresponding to a respective instruction in the application; checking if the sequence of intermediate representation entries meets a predefined criterion; if the predefined criterion is met: selecting one of the multiple types of processing elements for performing operations defined by the sequence of intermediate representation entries; converting the sequence of intermediate representation entries into one or more compute kernels; and scheduling execution of the one or more compute kernels on the selected type of processing element.