Patent ID: 7707365

Claim:
A memory address monitoring device for monitoring a memory with a beginning address and an ending address, wherein a first process has a first process identification and issues a request address and an access instruction to access the memory, data of a second process is saved between the beginning address and the ending address, the second process has a second process identification, the memory address monitoring device comprising: an address determining module for receiving the request address and determining whether the request address is located between the beginning address and the ending address to generate an address determining result; an instruction determining module for determining whether the access instruction is the same as a code for a write-in instruction to output a write-in determining result; and an identification determining module for processing the address determining result, the write-in determining result, the first process identification and the second process identification to generate an identification determining result, wherein the identification determining module further comprising: a comparator for determining whether the first process identification and the second process identification are the same to generate an identification comparing result; an AND gate for performing an AND operation on the address determining result, the write-in determining result and the identification comparing result; and a multiplexer for choosing the first process identification or zero according to the output of the AND gate and outputting the identification determining result, wherein the multiplexer outputs the identification determining result according to the first process identification when the address determining result is true and the identification comparing result is false, and wherein the first process, the second process, and the memory are implement in a video player.