Patent ID: 8462167

Claim:
A memory access control circuit, comprising: a first internal register; an address transmitting unit that transmits a first address obtained based on a first value which is set in the first internal register based on a first state signal indicating a first state and transmits a second address obtained based on a second value which is set in the first internal register based on the first state signal indicating a second state; a second internal register; a data receiving unit that receives first data corresponding to the first address, performs data processing on the first data without delay using a third value which is set in the second internal register based on a second state signal indicating a third state, receives second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time using a fourth value which is set in the second internal register based on the second state signal indicating a fourth state; a first backup unit; and a second backup unit, wherein, in response to completion of transmission of the first address from the address transmitting unit or the second address from the address transmitting unit, the first value or the second value in the first internal register is stored in the first backup unit, respectively, and wherein, in response to completion of the data processing of the first data by the data receiving unit, the third value in the second internal register is stored in the second backup unit by utilizing the given delay time and the fourth value is set to the second internal register by the second backup unit.