Patent ID: 7601606

Claim:
A method for manufacturing a mutilayer semiconductor wafer having reduced interfacial trap densities, the method comprising: providing a multilayer wafer comprising a surface that includes a capping oxide layer, an active semiconductor layer underlying the capping layer, a first internal interface, and at least one second internal interface, each interface being between a semiconductor layer and an adjoining insulator layer, with the first interface located between the capping oxide layer and the underlying active semiconductor layer, the second interface of the multilayer wafer located between an active semiconductor layer and an underlying buried oxide layer, and the second interface being further removed from the surface of the multilayer wafer than is the first internal interface; introducing a controlled proportion of a species into a generally neutral atmosphere, wherein the species is an element that is different than the atmosphere; and exposing the wafer to the atmosphere and species at a selected temperature between about 800° C. and about 1200° C., wherein the introduced species migrates at least to the second interface, reducing the interfacial trap density at that interface.