Patent ID: 6927631

Claim:
A CMOS gain stage, comprising: first and second input nodes; first and second input CMOS transistors having gate terminals coupled to said first and second input nodes, respectively; first and second feedback-controlled CMOS transistors having drain terminals coupled to a supply node and source terminals coupled to drain terminals of said first and second input CMOS transistors, respectively; first and second output CMOS transistors having gate terminals coupled to said drain terminals of said first and second input CMOS transistors, respectively, and drain terminals coupled to said supply node, wherein said first and second output CMOS transistor drain terminals form first and second output nodes, respectively; and a bias network coupled between gate terminals of said first and second feedback-controlled CMOS transistors, wherein said bias network is configured to bias said first and second feedback-controlled CMOS transistors to insure saturation of an input device in a subsequent stage without use of a source-follower circuit.