Patent ID: 8310891

Claim:
An integrated circuit memory device, comprising: a memory cell electrically coupled to a bit line; a sense amplifier electrically coupled to the bit line during an operation to read data from the memory cell, the sense amplifier comprising: a precharge circuit configured to precharge the bit line to a precharged voltage level in response to a precharge signal that is active during a precharge time interval and inactive during a develop time interval that commences upon termination of the precharge time interval; a comparator having a first input terminal electrically coupled to the bit line during the precharge and develop time intervals; and a bias circuit electrically coupled to the first input terminal, the bias circuit comprising a pair of pull-up transistors electrically connected in series between the first input terminal and a reference voltage line, the pair of pull-up transistors comprising: a first pull-up transistor responsive to a first bias voltage that is held at a constant voltage level during the precharge and develop time intervals; and a second pull-up transistor responsive to a second bias voltage that is switched from an inactive level to an active level during the precharge time interval and held at the active level during the develop time interval so that the first and second pull-up transistors operate collectively to supply a pull-up current to the first input terminal during a portion of the precharge time interval and during the develop time interval.