Patent ID: 8078833

Claim:
A flexible data pipeline architecture for accommodating software computational instructions for varying application programs, comprising: a programmable embedded processor having a plurality of pipeline stages, at least some of the pipeline stages being mathematical execution units and at least some of the pipeline stages being memory units; and an interconnecting switch matrix, each of the pipeline stages having a direct connection to the interconnecting switch matrix, the interconnecting switch matrix being able to form direct interconnections between the pipeline stages, the direct interconnections between the pipeline stages being variable in response to varying application instruction sequences as fast as every clock cycle so as to interconnect the pipeline stages in any desired number and in any desired order, wherein each of the execution units includes a plurality of logic circuits, the logic circuits being interconnectable into different hierarchical architecture structures so as to perform operations at different precisions of multi-bit arithmetic and logic operations, and wherein each of the execution units includes a program RAM into which control settings can be loaded for configuration of the logic circuits into different hierarchical architecture structures in the execution unit.