Patent ID: 7348616

Claim:
A ferroelectric memory device, comprising: an underlying interlayer insulation layer formed on a semiconductor substrate; a plurality of ferroelectric capacitors arranged two-dimensionally on the underlying interlayer insulation layer in row and column directions, wherein each of the ferroelectric capacitors comprises a bottom electrode, a ferroelectric layer pattern, and a top electrode, all of which are stacked sequentially; an encapsulated barrier layer indirectly wrapping the ferroelectric capacitors with an oxygen penetration path being interposed therebetween; a top interlayer insulation layer formed on the encapsulated barrier layer; and a plurality of plate lines parallel to the row direction and each electrically connected to at least two adjacent rows of ferroelectric capacitors, wherein each of the plurality of plate lines directly contacts at least two adjacent rows of top electrodes; wherein the plate lines comprise local plate lines each of which directly contacts at least two adjacent rows of the top electrodes of the ferroelectric capacitors, a gap between the ferroelectric capacitors is filled with an oxygen penetration path layer pattern; and the oxygen penetration path comprises the oxygen penetration path layer pattern and an oxygen penetration path layer covering the top of the oxygen penetration path layer pattern and the local plate lines.