Patent ID: 8124466

Claim:
A process for manufacturing a voltage-controlled transistor, comprising: providing a substrate; forming a quasi-linked deep well in said substrate, wherein the quasi-linked deep well is a single and continuous deep well, and is configured with a recess at an interface between the quasi-linked deep well and the substrate, wherein a mouth of the recess at the interface between the quasi-linked deep well and the substrate has a width ranging from 2 μm to 20 μm; forming a well with complementary doping polarity to that of said quasi-linked deep well in said substrate; forming an oxide layer over said substrate for serving as isolation structures; forming a gate-oxide layer over said quasi-linked deep well; forming heavy doping regions in said well with complementary doping polarity to that of said quasi-linked deep well; forming a polysilicon gate layer over the gate-oxide layer; forming an auxiliary region in the quasi-linked deep well; forming an electrode layer connecting with the auxiliary region and the polysilicon gate layer; and forming a conduction region in said well with complementary doping polarity to that of said quasi-linked deep well underlying a gate of said voltage-controlled transistor and near said quasi-linked deep well, wherein the conduction region is formed next to one of heavy doping regions.