Patent ID: 7462902

Claim:
A non-volatile memory, comprising: a substrate; and a first memory cell, the first memory cell including a first transistor disposed on the substrate and a second transistor disposed next to the first transistor, and the first transistor further comprising: a first gate, disposed on the substrate; a single gate dielectric layer, disposed between the first gate and the substrate; and a first source/drain region and a second source/drain region, disposed on the substrate at two sides of the first gate, respectively, and the second transistor further comprising: a second gate, disposed on the substrate; a compound dielectric layer, disposed between the second gate and the substrate; and a third source/drain region and the second source/drain region, disposed on the substrate at two sides of the second gate, respectively wherein the second transistor and the first transistor share the second source/drain region, wherein the compound dielectric layer comprises a first charge trapping layer, and the first transistor is used to read storage information stored in the second transistor and transmit programming or erase information to the second transistor.