Patent ID: 7271492

Claim:
A semiconductor device having multi-layered interconnection lines, the semiconductor device comprising: lower interconnection lines disposed on a semiconductor substrate, the lower interconnection lines substantially coplanar, the lower interconnection lines aligned in a first direction and disposed parallel to one another, the lower interconnection lines including a first lower interconnection line, a second lower interconnection line, and a third lower interconnection line between the first and second lower interconnection lines, an end of the first lower interconnection line and an end of the second lower interconnection line disposed a substantially equal distance away from an end of the third lower interconnection line; an interlayer insulating layer disposed on a surface of the substrate having the lower interconnection lines; and upper interconnection lines disposed on the insulating layer, the upper interconnection lines substantially coplanar, the upper interconnection lines aligned in the first direction and disposed parallel to each other, the upper interconnection lines including a first upper interconnection line, a second upper interconnection line, and a third upper interconnection line, wherein the width of the upper interconnection lines is less than the width of the lower interconnection lines.