Patent ID: 7262722

Claim:
A binary arithmetic decoding apparatus comprising: a first pair of look-up tables; a first multiplexer to select between an output of a first look-up table of said first pair of look-up tables and an output of a second look-up table of said first pair of look-up tables; a second pair of look-up tables; a third pair of look-up tables; a second multiplexer to select between an output of a first look-up table of said second pair of look-up tables and an output of a first look-up table of said third pair of look-up tables; and a third multiplexer to select between an output of a second look-up table of said second pair of look-up tables and an output of a second look-up table of said third pair of look-up tables; wherein said first, second and third multiplexers are all controlled by a control signal that is common to said first, second and third multiplexers.