Patent ID: 6876023

Claim:
A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region each formed in a semiconductor substrate, and a control electrode formed over said semiconductor region for controlling conductance of said semiconductor region between said source region and said drain region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; and a write transistor structure formed on an insulating film of said semiconductor substrate, for either electrically charging or electrically discharging said charge accumulating region by a current flowing between a source and a drain of said write transistor and either the source region or drain region of said write transistor are electrically connected to said charge accumulating region, and said source and drain regions of said write transistor is isolated from said source or drain region of said read transistor by said insulating film; and a thickness of a channel region of said write transistor is thinner than a thickness of said source region or drain region of said write transistor and said thickness of said channel region is less than 8 nm, wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; and wherein a distance between a channel of said read transistor structure and said charge accumulating region is 7 nm at most.