Patent ID: 8131935

Claim:
A data processing system, comprising: an interconnect fabric; a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs); a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory, wherein each of the plurality of processing units includes: a processor core; and a cache memory coupled to the processor core, said cache memory including: a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory; and a cache controller that, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.