Patent ID: 7650557

Claim:
An apparatus comprising: a main cache memory coupled to a host bus; a removable expanded memory device having a victim cache memory associated with the main cache memory and coupled to the host bus by a host bus interface, wherein the removable expanded memory device comprises: a plurality of dual in-line memory modules (DIMMs); a tracker coupled to the DIMMs to identify a memory access request to an address in the DIMMs that is within a particular memory bank to be checked for errors; memory scrubbing circuitry coupled to the memory to request a plurality of reads of data stored at a plurality of addresses of the DIMMs, and to identify single-bit errors and double-bit errors in the reads of data, wherein at least one read request of the plurality of reads is to read data stored at an address in the particular memory bank and is appended to the memory access request identified by the tracker; a memory controller coupled between the DIMMs and the memory scrubbing circuitry; and a direct memory access (DMA) logic circuit coupled between the memory controller and the host bus interface.