Patent ID: 7844243

Claim:
A mux circuit for a receiver, wherein: the mux circuit is adapted to receive a plurality of input signals (e.g., PAD 1 , Vref 1 , . . . , Vrefn) and to select one of the plurality of input signals for application to the receiver; the mux circuit comprises: a transmission gate (e.g., 202 ) connected between a first pad (e.g., PAD 1 ) and an output of the mux circuit (e.g., MUXOUT), wherein the transmission gate comprises a p-type transistor connected (i) at its channel nodes between the first pad and the output of the mux circuit and (ii) to receive a control signal at its gate node; and control circuitry for the p-type transistor adapted to implement a threshold reduction filter that ensures that a maximum voltage level at the output of the mux circuit is at least a threshold below a power supply voltage for the mux circuit.