Patent ID: 7042269

Claim:
A method for dynamic balancing of a clock tree, comprising the steps of: inserting a controllable buffer in a level of the clock tree, the controllable buffer comprising a plurality of columns of PMOSs and NMOSs in combination, each column having two PMOSs and two NMOSs connected serially, a clock input signal being inputted through an inverter to the gates of a top PMOS and a bottom NMOS of each column respectively, an inverter being inserted between the gates of a central PMOS and NMOS of each column respectively, a clock output signal being presented at points of connection the central PMOSs and the central NMOS; providing a controller for accepting any two clocks; and controlling the controllable buffer by an output bus C[x: 0 ] of the controller wherein control signals C( 0 ), C( 1 ) C( 2 ) . . . C(x) of the output bus C[x: 0 ] are inputted to the gates of central PMOS and NMOS of each column respectively, wherein more current is generated at an output of the controllable buffer for compensating a time delay of a clock signal to a sink of the clock tree.