Patent ID: 7558127

Claim:
A semiconductor device including a data output circuit to output data read from memory cells, wherein the data output circuit comprises: a first pipeline stage receiving, in parallel, a plurality of data from the memory cells and storing the received plurality of data, in response to a plurality of first control signals; a second pipeline stage receiving, in parallel, at least two data among the plurality of data stored in the first pipeline stage and storing the received at least two data, in response to a plurality of second control signals; and a multiplexer receiving the data stored in the second pipeline stage, and sequentially outputting the received data in response to a third control signal, wherein the first pipeline stage comprises: first through m th switch units receiving, in parallel, m-bit data provided from the memory cells, and first through m th latch units disposed to correspond to the first through m th switch units and storing data transmitted through their corresponding switch units, wherein the second pipeline stage comprises: an (m+1) th switch unit coupled to some latch units among the first through m th latch units, and an (m+2) th switch unit coupled to other latch units among the first through m th latch units, wherein the plurality of second control signals are commonly provided to the (m+1) th switch unit and the (m+2) th switch unit such that the second pipeline stage stores simultaneously data through the (m+1) th switch unit and data through the (m+2) th switch unit, wherein m is an even integer greater than 2, wherein the plurality of first control signals comprise n pipeline control signals. and each of the first through m th switch units comprises n switches respectively controlled by the n pipeline control signals. and each of the first through m th latch units comprises n latches respectively storing data transmitted by the n switches, where n is an integer greater than 1, wherein the plurality of second control signals comprise n*m/2 distinct pipeline control signals that are sequentially activated, wherein m*n/2 switches included in the (m+1) th switch unit sequentially output their corresponding data as even data in response to the sequential activation of the n*m/2 pipeline control signals, and m*n/2 switches included in the (m+2) th switch unit sequentially output their corresponding data as odd data in response to the sequential activation of the n*m/2 pipeline control signals.