Patent ID: 8423719

Claim:
An apparatus, comprising: a processor which issues a plurality of commands including a data address and a first identifier of a plurality of identifiers individually, wherein said plurality of identifiers is assigned to an identical command for classifying each of said commands; and a cache memory which includes a plurality of ways to store a data corresponding to said command, wherein said cache memory comprises: a register to store a second identifier of the plurality of identifiers, said register corresponding to at least one of said ways being fixed, said fixed way exclusively stores said data corresponding to said command which includes said first identifier which is a same as said second identifier stored in said register, during which said register stores said second identifier; and a replacement controller which selects a replacement way based on a predetermined replacement algorithm in a case of a cache miss, and excludes said fixed way from a candidate of said replacement way when said register corresponding to said fixed way stores said second identifier, and wherein said fixed way is selected to exclusively store said data corresponding to said command based on a match between said first identifier and said second identifier.