Patent ID: 8736309

Claim:
A non-overlapping clock generator circuit comprising: a first trigger generation circuit configured to receive a main clock signal and to responsively generate first and second trigger signals; a second trigger generation circuit configured to receive an inverted main clock signal and to responsively generate third and fourth trigger signals; a first clock generation branch comprising a first plurality of digital logic elements that is configured to receive the first, second and fourth trigger signals and to responsively generate a first sampling cycle clock signal and a delayed first sampling cycle clock signal; a second clock generation branch coupled to the first clock generation branch, the second clock generation branch comprising a second plurality of digital logic elements that is configured to receive the first, second and third trigger signals and to responsively generate a second sampling cycle clock signal and a delayed second sampling cycle clock signal, wherein the first sampling cycle clock signal and the delayed first sampling cycle clock signal are non-overlapping with the second sampling cycle clock signal and the delayed second sampling cycle clock signal; a third clock generation branch coupled to the first and second clock generation branches, the third clock generation branch comprising a third plurality of digital logic elements that is configured to receive the second trigger signal and to responsively generate a first gain cycle clock signal and a delayed first gain cycle clock signal; and a fourth clock generation branch coupled to the first, second, and third clock generation branches and comprising a fourth plurality of digital logic elements that is configured to receive the first trigger signal and to responsively generate a second gain cycle clock signal and a delayed second gain cycle clock signal, wherein the first gain cycle clock signal and the delayed first gain cycle clock signal are non-overlapping with the second gain cycle clock signal and the delayed second gain cycle clock signal.