Patent ID: 7624235

Claim:
A cache comprising: a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data; a cache control unit coupled to the data memory, wherein the cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is being staged for retransmission on an interface to which the cache is coupled, and wherein the cache control unit comprises a free list, and wherein the cache control unit is configured to use the free list to track which data entries in the data memory are currently allocated and which are currently free, and wherein the cache control unit is configured to update the free list to indicate that the given data entry is currently allocated responsive to allocating the given data entry; and a tag memory coupled to the cache control unit, wherein the tag memory comprises a plurality of tag entries configured to store address tags corresponding to data in the data memory and validity indications, and wherein a combination of the free list value for the given data entry and the validity indication in the tag memory for the given data entry indicate a current state of the given data entry.