Patent ID: 7531388

Claim:
A method of fabricating an electrically programmable fuse for an integrated circuit, the method comprising: forming a fuse on a support structure, the fuse comprising a first terminal portion and a second terminal portion interconnected by an elongate fuse element; wherein the first terminal portion has a maximum width greater than a maximum width of the elongate fuse element and wherein the fuse includes a narrowed width region where the first terminal portion and elongate fuse element interface, the narrowed width region extending at least partially into and comprising part of the first terminal portion, and wherein a width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein; and wherein the method further comprises providing a polysilicon support structure, and wherein forming the fuse further comprises providing a blocking mask over a portion of the polysilicon support structure and siliciding exposed polysilicon of the polysilicon support structure to thereby define a silicide fuse having the narrowed width region at the interface of the first terminal portion and the elongate fuse element, thereby patterning the silicide fuse with a planar configuration different than a planar configuration of the polysilicon support structure.