Patent ID: 7656718

Claim:
A semiconductor device having at least two semiconductor memory devices, each of the semiconductor memory devices comprising: a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; a peripheral circuit writing data to a cell of the memory cell array and reading out and amplifying a written data; and an output buffer outputting cell data amplified by the peripheral circuit, wherein the output buffer comprises: an output buffer initialization circuit activating an output buffer reset signal in response to the power up or power down of the semiconductor memory device and deactivating the output buffer reset signal in response to a first command signal output from a controller of the semiconductor memory device; and an output driver generating output data based on a data signal in response to a clock signal, a data enable signal, and the output buffer reset signal, wherein the output buffer initialization circuit comprises: an output buffer reset circuit activating the output buffer reset signal based on a first set signal generated in response to the power up of the semiconductor memory device and a second set signal enabling the power down of the semiconductor memory device; and a latch circuit latching the output buffer reset signal, and wherein the output driver makes an output port in a high impedance state in response to the activation of the output buffer reset signal.