Patent ID: 6876569

Claim:
A semiconductor integrated circuit device comprising: a plurality of memory cells, each having a storage MOSFET holding an information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate of the storage MOSFET, and a capacitor having a first terminal and a second terminal; a plurality of word lines coupled with the plurality of the memory cells; and a plurality of data lines coupled with the plurality of the memory cells, wherein the first terminal of the capacitor is coupled with one of the plurality of word lines and the second terminal of the capacitor is coupled with the gate of the storage MOSFET, wherein, in a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage and wherein the first terminal of the capacitor and a gate of the write transistor are commonly coupled to the same one of the plurality of word lines.