Patent ID: 7831812

Claim:
A method of servicing load requests in a processor, comprising: generating, by a processor core, a plurality of load requests, each load request exhibiting an address; receiving, by a core interface unit, the load requests at an input of the core interface unit; storing, by a request queue in the core interface unit, the load requests in respective slots of the request queue; storing, by an age queue in the core interface unit, ID tags in respective slots of the age queue, each ID tag in the age queue identifying the address of a respective load request in the request queue, the age queue including a tail at which ID tags enter the age queue, the age queue further including a head; and advancing, by the age queue, ID tags from the tail of the age queue toward the head of the age queue by a fixed rate corresponding to a predetermined number of age queue slots per clock cycle, the positions of the ID tags within the age queue indicating the relative ages of respective load requests in the request queue.