Patent ID: 7110262

Claim:
An integrated circuit device adapted to be loaded in host equipment, comprising: a substantially rectangular main body unit; a first set of connection terminals provided at one end of said main body unit to enable electrical connection between said main body unit and the host equipment; a plurality of loading sections provided in said main body unit, each of said loading sections having an insertion opening along an edge of said main body unit transverse to said one end, a second set of connection terminals spaced from said insertion opening, and a pair of sidewalls disposed between said insertion opening and said second set of connection terminals; a plurality of substantially rectangular integrated circuit chips assembled in respective ones of said loading sections, each of said integrated circuit chips including a built-in integrated circuit unit forming a memory unit or a logic circuit and a third set of connection terminals for establishing electrical connection between said second set of connection terminals in said loading section and said integrated circuit unit; a guide support provided in each of said loading sections and extending in a direction transverse to said insertion opening for guiding the insertion of said integrated circuit chips into said loading section, each said guide support including a pair of guide recesses formed along said pair of sidewalls of said loading section; and a controller disposed in said main body unit for controlling the writing of information signals to and the readout of information signals from said plurality of integrated circuit chips loaded in said loading sections, said controller including: a memory controller for concurrently controlling data writing and reading to each of said integrated circuit chips assembled in said respective ones of said loading sections; an interface for enabling data exchange between said controller and the host equipment; a register logically associated with said memory controller and said interface and having a variety of parameters for data exchange; and a buffer logically associated with said memory controller and said interface for transient data storage.