Patent ID: 8495534

Claim:
A method for reworking a plurality of cells initially placed in a circuit design, the method comprising: a data processing system allocating cells to tiles, wherein some tiles have at least two cells; the data processing system determining a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles; the data processing system selecting a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile; the data processing system repositioning the selected cell to form a modified design based on the circuit design; the data processing system determining an aggregate routing cost for the selected tile based on the modified design and an aggregate routing cost for a target tile based on the modified design; the data processing system determining whether the aggregate routing cost for the selected tile is greater than the aggregate routing cost for a target tile; and the data processing system affirming the modified design for further processing, in response to a determination that the aggregate routing cost for the selected tile is greater than the aggregate routing cost for the target tile.