Patent ID: 6982221

Claim:
A method of forming a ⅔F pitch high density line array, where F is the minimum line width of a photolithographic process used to accomplish the method of the invention; comprising: preparing a wafer; depositing a conductive material on the wafer to function as contact pads and electrodes; depositing a layer of sacrificial material on the conductive material; applying and patterning a layer of photoresist on the sacrificial material; etching the sacrificial material to form a placeholder having width and space of F; depositing sidewall spacer material hard mask to a thickness of about ⅓F on the placeholder; applying and patterning a layer of photoresist on the hard mask; anisotropically etching the hard mask material; depositing a layer of silicon oxide and smoothing the silicon oxide by CMP; selectively removing the placeholder; depositing a second sidewall spacer layer to a thickness of about ⅓F; depositing another hard mask layer and smoothing the other hard mask layer by CMP; etching the silicon oxide and conductive material using the other hard mask lines as a pattern; applying and patterning a layer of photoresist; etching to form interconnect lines and contact pads; and selectively etching any remaining hard mask material to expose lines and contact pads.