Patent ID: 7576673

Claim:
An analog to digital converter circuit comprising: an input terminal to receive an analog input signal; an output terminal; and a plurality of stages connected in series, each stage to receive an input signal and an output signal, the output signal of the last stage to be provided to the output terminal, being a digital signal, and indicating a level of the analog input signal, the output signal of the last stage to be combined with the received analog input signal on the input terminal, the combined signal to be fed to a first of said plurality of stages, a measuring device coupled with the output terminal to determine when a level indicated by the output signal of the last stage exceeds a first predetermined level and to determine when the level indicated by the output signal of the last stage exceeds a second predetermined level, at least one of the plurality of stages comprising a variable delay stage to generate a time delayed signal by delaying its input signal a first predetermined time interval when the measuring device determines a level indicated by the output signal of the last stage exceeds a first predetermined level and by delaying its input signal a second predetermined time interval when the measuring device determines the level indicated by the output signal of the last stage exceeds a second predetermined level.