Patent ID: 8735050

Claim:
A method for fabricating an integrated circuit, the method comprising: creating a master pattern layout for a semiconductor device layer, the master pattern layout comprising a first adjacent cell and a second adjacent cell each configured for providing a particular logic function, the first adjacent cell having a first border pin with a first routing line extending therefrom and the second adjacent cell having a second border pin with a second routing line extending therefrom, wherein the first routing line has a first predetermined line width and the second routing line has a second predetermined line width, wherein the first and second predetermined line widths are about 40 nm or greater, and wherein the first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins, and wherein the edge-edge stitch has a width that corresponds to the first and second predetermined line widths; decomposing the master pattern layout into a first sub-pattern and a second sub-pattern, wherein the first sub-pattern comprises the first border pin with the first routing line and the second sub-pattern comprises the second border pin with the second routing line; generating a first set of mask data corresponding to the first sub-pattern; and generating a second set of mask data corresponding to the second sub-pattern.