Patent ID: 8761204

Claim:
An apparatus for processing received data packets into one or more packet reassemblies for transmission as output packets, the apparatus comprising: a shared system memory configured to receive data packets associated with each packet reassembly; a packet assembly processor configured to: determine an associated packet reassembly of processed data portions from a plurality of processing modules; enqueue an identifier for each processed data portion in one of a plurality of input queues, the one input queue corresponding to the packet reassembly associated with the processed data portion; maintain a state data entry corresponding to each packet reassembly, the state data entry having an active indicator that identifies whether the packet reassembly is actively processed by the packet assembly processor, wherein two or more concurrently active packet reassemblies are permitted; iteratively, until an eligible processed data portion is selected: select a given processed data portion from a non-empty input queue for processing by the packet assembly processor; determine if the active indicator of packet reassembly associated with the selected processed data portion is set, wherein (i) if the active indicator is set, the packet assembly processor is configured to set the selected processed data portion as ineligible for selection, otherwise, (ii) if the active indicator is not set, the packet assembly processor is configured to select the processed data portion for processing and modify the packet reassembly based on the selected processed data portion, thereby the packet assembly processor is configured to prevent back-to-back processed data portions associated with the same reassembly from head-of-line blocking processing of processed data portions for other reassemblies.