Patent ID: 8664722

Claim:
A semiconductor device comprising: a semiconductor film over an insulator, comprising a recessed portion at a portion corresponding to a channel formation region of the semiconductor device, and including a non impurity doped layer at least at a portion located at a bottom of the recessed portion; an insulating film covering at least the non impurity doped layer; a gate electrode overlapping the non impurity doped layer with the insulating film interposed therebetween; a first metal silicide layer and a second metal silicide layer on respective first region and second region of the semiconductor film each adjacent to the recessed portion, forming side surfaces of the recessed portion; and a first impurity doped layer and a second impurity doped layer under and in contact with the first metal silicide layer and the second metal silicide layer, forming a source region and a drain region of the semiconductor device, wherein the insulating film is continuous from over the first metal silicide layer to over the second metal silicide layer, wherein the first metal silicide layer and the second metal silicide layer comprise respectively a first edge and a second edge each facing the gate electrode, wherein the first impurity doped layer and the second impurity dosed layer comprise respectively a third edge and a fourth edge each facing the gate electrode, wherein the first edge and the second edge are farther from the gate electrode than the third edge and the fourth edge, respectively, and wherein the first impurity doped layer and the second impurity doped layer each have a same thickness in portions overlapping with one of the metal silicide layers and in portion not overlapping with one of the metal silicide layers.