Patent ID: 7757031

Claim:
A data transmission coordinating method for a central processing unit and a north bridge chip of a computer system, the north bridge chip being coupled to a south bridge chip, the method comprising steps of: issuing a read signal by the north bridge chip for reading a first transmission standard of the north bridge chip stored in a memory unit; issuing a data receiving signal by the south bridge chip in response to the reading signal to transmit the first transmission standard from the memory unit to the north bridge chip; issuing a first signal from the north bridge chip to the central processing unit to inform the central processing unit of the first transmission standard of the north bridge chip; issuing a second signal from the central processing unit to the north bridge chip to inform the north bridge chip of a second transmission standard of the central processing unit; and coordinating a commonly operable transmission standard for both the central processing unit and the north bridge chip according to the first transmission standard and the second transmission standard.