Patent ID: 7400134

Claim:
An integrated circuit device comprising: a first semiconductor chip comprising a plurality of first input/output pads which are arranged in matrix form having at least three rows and three columns, and a plurality of first test pads which are placed outside of the plurality of first input/output pads and which are larger than the first input/output pads; and a second semiconductor chip comprising a plurality of second input/output pads connected to the plurality of first input/output pads, and a plurality of second test pads connected to the plurality of first test pads, wherein at least one of the plurality of first test pads is electrically connected with at least one of the plurality of first input/output pads inside the first semiconductor chip, and wherein the second semiconductor chip further comprises a plurality of third input/output pads connected to an external terminal of the integrated circuit, and the first semiconductor chip is connected to the external terminal via the second semiconductor chip.