Patent ID: 7049694

Claim:
An integrated circuit comprising a semiconductor die for wire-bonding to a plurality of conductive traces comprising: a first substrate trace having a first end and a second end; a second substrate trace having a first end and a second end, said second substrate trace being laterally aligned with said first substrate trace; a first bonding pad located on said semiconductor die, said first bonding pad coupled to said first end of said second substrate trace using a first wire; a second bonding pad laterally aligned with said first bonding pad and located on said semiconductor die, said second bonding pad coupled to said first end of said first substrate trace using a second wire; a third substrate trace having a first end, said first end coupled to said second end of said second substrate trace using a third wire; and a fourth substrate trace having a first end, said fourth substrate trace being laterally aligned with said third substrate trace, said first end of said fourth substrate trace coupled to said second end of said first substrate trace using a fourth wire, wherein said third wire crosses said fourth wire.