Patent ID: 8044487

Claim:
A semiconductor device that comprises a high voltage element and a low voltage element, said device comprising: a semiconductor substrate having high voltage element region where said high voltage element is present, and a low voltage element region where said low voltage element is present; a first isolation structure present in said high voltage element region; and a second isolation structure present in said low voltage element region, wherein said first isolation structure comprises a first LOCOS oxide film present on a surface of said semiconductor substrate, an isolated CVD oxide film obtained by etching an oxide film deposited by CVD on said first LOCOS oxide film, and an electrode present on said isolated CVD oxide film, said second isolation structure consisting of: a n + diffusion layer buried in said semiconductor substrate; a n − epitaxial layer; a p − diffusion layer; a n + diffusion region present in the p − diffusion layer; a p + diffusion region present in the n − epitaxial layer; a polysilicon electrode present on an oxide film; at least one second LOCOS oxide film; an insulation layer; an aluminum electrode present on said insulation layer; and a silicon nitride protection film present on said aluminum electrode, where a thickness of the first LOCOS oxide film of said first isolation structure is approximately the same as a thickness of the second LOCOS oxide film of said second isolation structure.