Patent ID: 8471307

Claim:
A process of forming an integrated circuit containing a p-channel metal oxide semiconductor (PMOS) transistor, comprising the steps: providing a substrate; forming a PMOS gate dielectric layer on a top surface of said substrate; forming a PMOS gate on a top surface of said PMOS gate dielectric layer; forming p-channel source/drain (PSD) recesses in said substrate adjacent to said PMOS gate by a process of removing substrate material; forming a three layer PSD stack in said PSD recesses, by a process further including the steps; forming a first PSD layer of Si—Ge on exposed surfaces of said substrate in said PSD recesses using a process that includes no boron source, such that: a thickness of said first PSD layer on sidewalls of said PSD recesses is at least 10 nanometers; a germanium content of said first PSD layer is between 20 atomic percent and 35 atomic percent; and a carbon density of said first PSD layer is between 5×10 19 and 2×10 20 atoms/cm 3 ; forming a second PSD layer on exposed surfaces of said first PSD layer, such that: a germanium content of said second PSD layer is between 20 atomic percent and 35 atomic percent; a carbon density of said second PSD layer is between 5×10 19 and 1×10 20 atoms/cm 3 ; and a boron density of said second PSD layer is at least 5×10 19 atoms/cm 3 ; a boron density of said first PSD layer after forming the second PSD layer is between 0 and 10 percent of said boron density of said second PSD layer; and forming a third PSD layer on exposed surfaces of said second PSD layer, such that: said third PSD layer includes silicon; a germanium content of said third PSD layer is between zero and 35 atomic percent; a carbon density of said third PSD layer is less than 5×10 18 atoms/cm 3 ; and a boron density of said third PSD layer is at least 5×10 19 atoms/cm 3 ; forming metal silicide on a top surface of said third PSD layer; and forming PMOS contacts on said metal silicide.