Patent ID: 7975077

Claim:
A single chip data processor, comprising: a central processing unit to execute instructions; a first terminal to be coupled to a first external bus; a second terminal to be coupled to a second external bus which is different from the first external bus; an internal bus coupled to the central processing unit; a first interface circuit coupled to the first terminal and to the internal bus; a second interface circuit coupled to the second terminal and to the internal bus; and a signal path coupled to the first terminal and the second terminal, wherein the data processor includes a first condition and a second condition, wherein in the second condition, the first terminal is coupled to the second terminal via the signal path, and signals from the first terminal are provided to the second terminal via the signal path, and a clock supply to the central processing unit is stopped, wherein the central processing unit, the internal bus, the first interface circuit and the second interface circuit are allocated in a first area, wherein the signal path is allocated in a second area, wherein in the second condition, the first area is in a low consumption state, and wherein the first area and the second area are constructed on a single chip, wherein the second area where the signal path is arranged is adapted to operate in the second condition, wherein in the first condition, the signals from the first terminal are provided to the internal bus via the first interface circuit, and wherein in the second condition, the single chip data processor is adapted to receive information of time display control via the first terminal, and the data processor is adapted to provide the information of time display control to the second external bus via the signal path and the second terminal.