Patent ID: 7552252

Claim:
An interface circuit comprising: a plurality of bi-directional buffers, each of the plurality of bi-directional buffers having a clock input; a plurality of multiplexer circuits, wherein the plurality of multiplexer circuits are configured such that there is a one-to-one correspondence between the plurality of multiplexer circuits and the plurality of bi-directional buffers, whereby each of the plurality of multiplexer circuits has an output that is coupled to the clock input of the corresponding bi-directional buffer; a memory clock signal coupled to an input of each of the plurality of multiplexer circuits; a system clock signal coupled to another input of each of the plurality of multiplexer circuits; and buffer manager logic configured to generate control signals for the multiplexer circuits, which control signals independently control the multiplexer circuits to select either the memory clock signal or the system clock for the bi-directional buffers.