Patent ID: 7622976

Claim:
A sequential integrated circuit comprising: a master latch connected to an input, the master latch comprising one or more master logic gates adapted to be substantially maintained at a high voltage and a master resistor connected to the one or more master logic gates; a slave latch connected to the master latch, the slave latch comprising one or more slave logic gates adapted to be substantially maintained at the high voltage and a slave resistor connected to the one or more slave logic gates; a clock element connected to the master latch, the slave latch, and a power source, the clock element adapted to cause the master latch to transition between a first state and a second state; and a multiplexer connected to the clock element and the power source, wherein the multiplexer is adapted to select either the output of the master latch or the output of the slave latch in response to a phase of the clock element; wherein the power source is adapted to maintain the clock element at a clock low voltage and the multiplexer at a multiplexer low voltage, and wherein the clock low voltage and the multiplexer low voltage are less than the high voltage, and further wherein the clock low voltage and the multiplexer low voltage can be varied such that the clock element and the multiplexer can operate on substantially dissimilar low voltages.