Patent ID: 7440248

Claim:
A semiconductor integrated circuit device comprising: a protected circuit protected against electro-static discharge applied from outside the device; an SCR protection circuit having: a pnp bipolar transistor including an emitter connected to a power line and a collector connected to a trigger terminal; an npn bipolar transistor including an emitter connected to a ground line, a collector connected to a base of the pnp bipolar transistor, and a base connected to the trigger terminal; a first resistor having one terminal connected to the trigger terminal and the other terminal connected to the ground line; and a second resistor having one terminal connected to the power line and the other terminal connected to the collector of the npn bipolar transistor; and a trigger circuit connected to the trigger terminal and including an RC circuit connected between the power line and the ground line, the RC circuit having a fourth resistor and a capacitor; and a third resistor having one terminal connected to the trigger terminal and the trigger circuit and the other terminal connected to the ground line, wherein the trigger circuit includes: a p-transistor having one terminal connected to the power line and another terminal connected to the trigger terminal and the one terminal of the third resistor; a NAND gate having an output terminal connected to a gate of the p-transistor; the capacitor having one terminal connected to the power line and another terminal connected to a first input terminal of the NAND gate; the fourth resistor having one terminal connected to the first input terminal of the NAND gate and the other terminal connected to the ground line; and an inverter having an input terminal connected to the trigger terminal and an output terminal connected to a second input terminal of the NAND gate.