Patent ID: 7883970

Claim:
A method of fabricating a semiconductor device, comprising: preparing a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region; forming at least one channel trench in the cell region of the semiconductor substrate, forming at least one first capacitor trench in the first peripheral circuit region of the semiconductor substrate, and forming at least one second capacitor trench in the second peripheral circuit region of the semiconductor substrate; covering an inner wall of the channel trench with a gate dielectric layer, covering at least an inner wall of the first capacitor trench with a first dielectric layer, and covering at least an inner wall of the second capacitor trench with a second dielectric layer, wherein the first dielectric layer has the same thickness as the gate dielectric layer and a different thickness from the second dielectric layer; filling the channel trench covered with the gate dielectric layer with a gate electrode, filling the first capacitor trench covered with the first dielectric layer with a first upper electrode, and filling the second capacitor trench covered with the second dielectric layer with a second upper electrode; and implanting impurity ions into the semiconductor substrate to form a source region and a drain region in the cell region of the semiconductor substrate, the source region and the drain region being formed at opposite sides of the gate electrode.