Patent ID: 7588982

Claim:
A method of forming a semiconductor construction from a semiconductor substrate having a plurality of active area locations defined within a monocrystalline semiconductor material, and having isolation regions adjacent the active area locations and separating the active area locations from one another; the semiconductor substrate having a layer of gate dielectric over the active area locations, and having a layer of polycrystalline semiconductor material over the gate dielectric and between the isolation regions; the isolation regions comprising insulative material that extends above the active area locations and defines openings over the polycrystalline semiconductor material; the method comprising: forming spacers within the openings to narrow the openings; epitaxially growing electrically conductive gate material within the narrowed openings from the polycrystalline semiconductor material; and forming source/drain regions within the active area locations, the source/drain regions being gatedly coupled to one another through the electrically conductive gate material.