Patent ID: 8476680

Claim:
A semiconductor device comprising: a semiconductor substrate; a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween; a side wall spacer formed on a side wall of the gate electrode; source/drain regions formed in opposing portions of the semiconductor substrate with the gate electrode and the side wall spacer interposed therebetween; and a stress-applying insulating film covering the gate electrode, the side wall spacer, and an upper surface of the semiconductor substrate, wherein the side wall spacer includes a first side wall portion formed on the side wall of the gate electrode and on the semiconductor substrate and having an L-shaped cross section, and a second side wall portion formed on an upper end portion of the first side wall portion and having a gate-length-direction thickness at least larger than a gate-length-direction thickness of a middle portion of the first side wall portion in the height direction, and the side wall spacer further includes a third side wall portion interposed between the first side wall portion and the side wall of the gate electrode.