Patent ID: 8458540

Claim:
An integrated circuit comprising: a first selection circuit for selecting a first data from an input data or a scan data, and outputting the first data, the scan data composing a logic pattern that is used for performing a diagnosis of a combinational circuit, the input data being received from a combinational circuit; a first latch circuit for holding the first data as a first output data in accordance with a first signal; a second latch circuit for holding the first output data as a second output data in accordance with which of the first signal and a second signal, the second signal being used to force the second latch circuit to hold the first output data independently of the first signal; a third latch circuit for holding the first output data as a third output data in accordance with which of the first signal and a third signal, the third signal being used to force the third latch circuit to hold the first output data independently of the first signal; and a second selection circuit for selecting a second data from among a plurality of data which include the second output data and the third output data, and outputting the second data.