Patent ID: 7124391

Claim:
A method of reconfiguring a programmable logic device (PLD) programmed with modular logic circuits, the PLD having an array of programmable logic blocks, comprising: obtaining a selected partial reconfiguration bitstream from a database that includes a plurality of partial reconfiguration bitstreams, wherein each partial reconfiguration bitstream implements a modular logic circuit on the PLD, the bitstream having a first portion that implements a function of a modular logic circuit on a first subset of resources of the PLD and a second portion that implements an interface to the modular logic circuit on a designated second subset of resources of the PLD; wherein each modular logic circuit is constrained to an integral number of columns of programmable logic blocks, the second subset of resources is at least one of a plurality of programmable logic blocks contiguous in a column or a plurality of programmable logic blocks contiguous in a row, the second subset of resources forms a boundary on at least one side of the modular logic circuit between the modular logic circuit and other circuitry implemented on the PLD, and the first portion of the bitstream does not program the second subset of resources; modifying in the second portion of the selected partial reconfiguration bitstream, bits that configure programmable switches with configuration data to connect the interface to one or more of the modular logic circuits; and partially reconfiguring the programmable logic device using the selected partial reconfiguration bitstream as modified.