Patent ID: 8913442

Claim:
A circuit for sensing a multi-level cell (MLC) flash memory, the circuit comprising: a plurality of first decoding units each providing a timing information and including: a controlled transistor to allow a current to pass therethrough; a capacitor to be charged by the current or to discharge through the controlled transistor; a first current-capacitor circuit including: a first controlled transistor to allow a first current to flow therethrough; and a first capacitor to be charged by the first current; and a second current-capacitor circuit including: a second controlled transistor to allow a second current to flow therethrough; and a second capacitor to be charged by the second current; a second decoding unit providing a latch signal and including: a controlled transistor to allow a current to pass therethrough, the magnitude of the current being associated with data in an MLC; and a capacitor to be charged by the current or to discharge through the controlled transistor; and a data latch, in response to the timing information from each of the first decoding units and the latch signal from the second decoding unit, to determine the data in the MLC.