Patent ID: 7622326

Claim:
A method of fabricating a chip package, at least comprising the steps of: providing a support base plate having a top surface and a back surface; forming a multi-layered interconnection structure over the top surface of the support base plate, wherein the multi-layered interconnection structure has an inner circuit with a plurality of bonding pads on a surface of the multi-layered interconnection structure closest to the support base plate; attaching at least a die on a surface of the multi-layered interconnection structure furthest from the support base plate, wherein the die is electrically connected to the inner circuit within the multi-layered interconnection structure; forming a plurality of first openings in the support base plate, wherein each first opening exposes a corresponding bonding pad; and reducing a thickness of the support base plate, wherein the step of reducing the thickness of the support base plate is performed after the step of forming the multi-layered interconnection structure over the top surface of the support base plate but before the step of attaching the die to the surface of the multi-layered interconnection structure or after attaching the die to the surface of the multi-layered interconnection structure but before forming the plurality of first openings on the support base plate.