Patent ID: 7247555

Claim:
A method for fabricating IC's comprising the following steps: (a) providing a substrate with an insulating layer over the substrate; (b) providing a first level of conducting material defined and embedded in the insulating layer over the substrate; (c) depositing an intermetal dielectric layer over the insulating layer; (d) forming a bi-layered hard mask over the intermetal dielectric layer, the bi-layered hard mask comprising a first hard mask layer HM 1 overlying a second hard mask layer HM 2 ; (e) patterning the intermetal dielectric layer and hard mask layers, and CF 4 /N 2 /O 2 based reactive ion etching to form via openings extending through the intermetal dielectric layer and one of the hard mask layers; (f) forming a layer of via-fill material of bottom anti-reflective coating with photoresist over the intermetal dielectric layer, the via-fill material filling the via openings; (g) patterning the via-fill material, intermetal dielectric layer and hard mask layers, and etching to form trench openings using a reactive ion etch; and (h) stripping-off the via-fill material after forming the trench openings, thus forming open trench and open via regions for subsequent conducting metal fill.