Patent ID: 7321512

Claim:
A non-volatile memory device comprising: an array of memory cells organized into a plurality of array sectors, each array sector singularly addressable through an array wordline; at least one array of reference cells addressable through a reference wordline; a respective voltage ramp generator for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein; a respective row decoding circuit coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline; and a current generator for generating a current to be injected on a circuit node in a selected array sector and on a circuit node of said at least one array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp; and a respective local ramp generating circuit for each array sector and for said at least one array of reference cells, and comprising a switch controlled by a ramp starting signal for delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.