Patent ID: 6944755

Claim:
A circuit comprising: a source register with the plurality of bits divided into a plurality of first level subsets; means for identifying the bits in each subset which are transfer bits and non-transfer bits; arranger means for aligning the transfer data bits in each first level subset to a first side thereof to farm corresponding second level subsets of the transfer data bits; a destination register; and coupling means for loading the transfer data bits from the second level subsets into the destination register aligned to the first side of the destination resister; wherein the arranger means comprises a plurality of arrangers each for a receiving a set of mask bits, each set of mask bits corresponding to one of the arrangers, each arranger corresponding to a subset of the first level subsets, each arranger comprising: a first multiplexer having a first input coupled to receive a first bit from the subset of the first level subsets to which the arranger corresponds, a second input coupled to receive a second bit from the subset of the first level subsets to which the arranger corresponds, a control input for receiving a first mask bit from the set of mask bits to which thee arranger corresponds, and an output; a second multiplexer having a first input to receive the first bit, a second input coupled to the output of the first multiplexer, a control input for receiving a second mask bit from the set of mask bits to which the arranger corresponds, and an output; a third multiplexer having a first input coupled to the output of the first multiplexer, a second input coupled a third bit from the subset of the first level subsets to which the arranger corresponds, a control input for receiving the second mask bit, and an output; a fourth multiplexer having a first input coupled to the output of the third multiplexer, a second input coupled a fourth bit front the subset or the first level subsets to which the arranger corresponds, a control input for receiving a third mask bit from the set of mask bits to which the arranger corresponds, and an output as a first output of the arranger; a fifth multiplexer having a first input coupled to the output of the third multiplexer, a second input coupled to the output of the second multiplexer, a control input for receiving the third mask bit, and an output as a second output of the arranger; and a sixth multiplexer having a first input coupled to the output of the second multiplexer, a second input coupled to receive the first bit, a control input for receiving the third mask bit, and an output as a third output of the arranger.