Patent ID: 6847241

Claim:
A delay lock loop (DLL) circuit coupled between output and input terminals of a clock network, the DLL circuit comprising: an input clock terminal; a feedback clock terminal coupled to the output terminal of the clock network; a delay line having an input terminal coupled to the input clock terminal and having a plurality of output terminals providing a plurality of intermediate clock signals; a control circuit having a first input terminal coupled to the feedback clock terminal, a second input terminal coupled to the input clock terminal, and a plurality of control output terminals; and a bi-directional shift register and clock multiplexer having a plurality of data input terminals coupled to the output terminals of the delay line, a plurality of control input terminals coupled to the control output terminals of the control circuit, and an output terminal coupled to the input terminal of the clock network, wherein: the bi-directional shift register comprises a token bit shifted under control of the control circuit; the clock multiplexer selects one of the intermediate clock signals, as determined by a location of the token bit within the bi-directional shift register, to supply to the output terminal; the control circuit comprises a shift clock generator circuit and a shift enable circuit; the shift clock generator circuit provides a plurality of control signals to a first subset of the control input terminals of the bi-directional shift register and clock multiplexer; and the shift enable circuit provides a plurality of shift enable signals to a second subset of the control input terminals of the bi-directional shift register and clock multiplexer.