Patent ID: 7379521

Claim:
A delay circuit, comprising: a clock generator circuit; and a delay section; said clock generator circuit including a variable delay circuit delaying input clock and generating output clock to be supplied to an internal circuit, a phase comparator performing a phase comparison between said input clock and said output clock, and a delay control circuit outputting a control voltage for adjusting a delay amount of said variable delay circuit in response to a result of said phase comparison of said phase comparator; said delay section includes a first delay stage, a second delay stage, and a third delay stage, wherein: said first delay stage receives an input signal, delays said input signal for a prescribed period in accordance with said control voltage of said delay control circuit, and outputs a first delayed input signal, said second delay stage receives said input signal, delays said input signal for said prescribed period in accordance with said control voltage of said delay control circuit, and outputs a second delayed input signal, and said third delay stage receives said second delayed input signal from said second delay stage, delays said second delayed input signal for said prescribed period in accordance with said control voltage of said delay control circuit, and outputs a third delayed input signal, said variable delay circuit and said delay section each including a plurality of delay units formed of identical circuit elements, a unit delay amount of each of said delay units changing in accordance with said control voltage, and said delay control circuit including a clamp circuit for fixing lower limit of said control voltage to a reference voltage.