Patent ID: 7935579

Claim:
A method for fabricating a TFT array substrate, comprising: sequentially depositing a first metal layer and a transparent conductive layer on a substrate; forming a gate line, a gate electrode, a gate pad and a pixel electrode by patterning the first metal layer and the transparent conductive layer using a first mask; depositing an insulation layer, an amorphous silicon layer and a second metal layer over the substrate; forming a semiconductor layer, a data line, a data pad, a first open area in a pixel region, and a second open area in the gate pad by patterning the amorphous silicon layer and the second metal layer using a second mask; depositing a conductive material over the substrate; forming first and second masking layers and first and second oxidation-prevention layers by patterning the conductive material using a third mask; forming source and drain electrodes by etching the second metal layer exposed between the first and second masking layers using the first and second masking layers as a mask to define a channel region; and exposing the transparent conductive layer of the pixel electrode by etching the first metal layer exposed through the first open area, and wherein the first and second open areas are formed by patterning the insulation layer, the amorphous silicon layer and the second metal layer using the second mask, wherein the first masking layer covers the data line and the source electrode, wherein the second masking layer covers the drain electrode and a portion of the first metal layer of the first open area, and connects the drain electrode to the pixel electrode, and wherein the first metal of the first open area contacts the insulation layer under the drain electrode, and wherein the first and second oxidation-prevention layers respectively cover the gate pad and the data pad.