Patent ID: 7517757

Claim:
A method of fabricating a non-volatile memory cell comprising the steps of: forming a tunnel insulation layer, a trap insulation layer, a blocking insulation layer, a first gate conductive layer and a hard mask layer sequentially on a semiconductor substrate; forming a stepped groove exposing a predetermined region of the semiconductor substrate by patterning the hard mask layer, the first gate conductive layer, the blocking insulation layer, the trap insulation layer, and the tunnel insulation layer successively, wherein the tunnel insulation layer, the trap insulation layer, the blocking insulation layer and the first gate conductive layer form protruding portions of the stepped groove; forming a spacer-shaped selection gate electrode covering protruding portions of stepped groove and a gate insulation pattern, which is interposed between the selection gate electrode and an inner sidewall of the stepped groove, and between the selection electrode and the semiconductor substrate; and forming a control gate pattern having a sidewall that is self-aligned with a sidewall of the gate insulation pattern, wherein the control gate pattern comprises the tunnel insulation layer, the trap insulation layer, the blocking insulation pattern and the control gate electrode which are stacked sequentially.