Patent ID: 8086986

Claim:
A programmable logic device comprising: a plurality of logic blocks; a plurality of synchronized registers within the plurality of logic blocks, the synchronized registers representing a portion of a circuit design implemented by a user within the programmable logic device; configuration memory adapted to store configuration data for configuring the programmable logic device; a general routing network adapted to route signals among the logic blocks and having a plurality of routing wires; and a clock distribution network adapted to route clock signals among the logic blocks and having a plurality of routing wires, wherein: at least one clock signal path of the user-implemented circuit design is provided within the programmable logic device from a clock source to one of the synchronized registers via a routing wire of the clock distribution network and a routing wire of the general routing network; and the routing wire of the general routing network within the clock signal path is provided between an end of the routing wire of the clock distribution network and a clock input pin of the synchronized register.