Patent ID: 8335910

Claim:
An apparatus for extracting instructions from a stream of undifferentiated instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length, the apparatus comprising: a first queue, having a plurality of entries each configured to store a line of instruction bytes received from an instruction cache; decoders, configured to generate an associated start/end mark for each of the instruction bytes of a line of instruction bytes from the first queue; a second queue, having a plurality of entries each configured to store a line of instruction bytes received from the first queue along with the associated start/end marks received from the decoders; and control logic, configured to: detect a condition in which the length of an instruction having an initial portion within a first line of instruction bytes in the first queue is yet undeterminable because a remainder of the instruction resides in a second line of instruction bytes that has yet to be loaded into the first queue from the instruction cache; load the first line of instruction bytes and the corresponding start/end marks into the second queue and refrain from shifting the first line out of the first queue, in response to detecting the condition; and extract for subsequent processing by the microprocessor a plurality of instructions from the first line of instruction bytes in the second queue based on the corresponding start/end marks, wherein the plurality of extracted instructions excludes the yet undeterminable length instruction.