Patent ID: 8742495

Claim:
A power field-effect transistor (FET) comprising: a substrate of a first conductivity type; a pillar of semiconductor material disposed over the substrate and extending in a vertical direction from a bottom that adjoins the substrate to a top surface, the pillar extending in first and second lateral directions to form a closed loop having first and second linear fillet sections, and first and second semi-circular end sections, the first and second linear fillet sections each having a first width, and the first and second semi-circular end sections each having a second width narrower than the first width; a source region of the first conductivity type being disposed at or near the top surface of the pillar; a body region of a second conductivity type disposed in the pillar beneath the source region; an extended drain region of the first conductivity type in the pillar that extends in the vertical direction from the bottom that adjoins the substrate to the body region; first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar; first and second field plates respectively disposed in the first and second dielectric regions; and first and second gate members respectively disposed in the first and second dielectric regions, the first and second gate members extending in the vertical direction from adjacent the top surface of the pillar down to at least adjacent a bottom of the body region, the first and second gate members being separated from the body region by a gate oxide.