Patent ID: 8120096

Claim:
A power semiconductor device comprising: a conductive low concentration epitaxial layer; first conductive regions, extending from a top surface of the epitaxial layer down to a predetermined depth in the epitaxial layer, the first conductive regions comprising a plurality of linear first conductive layers laterally spaced from each other by a predetermined distance, a plurality of linear second conductive layers laterally spaced from each other by a predetermined distance, and a third conductive layer formed in a space defined between opposite ends of the first conductive layers and the second conductive layers to connect the first conductive layers and the second conductive layers, wherein the opposite ends of the first conductive layers and the second conductive layers are alternately arranged with respect to each other and are laterally spaced from each other by a predetermined distance; second conductive regions extending down to a predetermined depth in the first and second conductive layers and formed to a smaller lateral width and depth than the first and second conductive layers so that channels are formed in the first and second conductive layers; a gate oxide layer formed on the top surface of the epitaxial layer to define first windows having a smaller width than the first conductive layers and second windows having a smaller width than the second conductive layers; and a gate polysilicon layer formed on top of the gate oxide layer.