Patent ID: 7029967

Claim:
A method of forming metal silicide regions in integrated circuits, comprising: forming a first gate structure over a p-well region and a second gate structure over a n-well region wherein said n-well region and said p-well region are formed in a semiconductor substrate; forming first sidewall structures adjacent said first gate structure and second sidewall structures adjacent said second gate structure; forming germanium implanted regions by implanting germanium into said p-well region adjacent said first sidewall structures and into said n-well region adjacent said second sidewall structures; forming source and drain regions in said p-well region adjacent said first sidewall structure and in said n-well region adjacent said second sidewall structure wherein at least a portion of said source and drain regions overlap said germanium implanted regions; annealing said germanium implanted regions and said source and drain regions with a rapid thermal anneal at temperatures exceeding 1000° C.; forming a nickel metal layer over said source and drain regions and said germanium implanted regions; and annealing said metal layer to form nickel silicide regions over said source and drain regions and said germanium implanted regions.