Patent ID: 7902679

Claim:
A chip package comprising: a substrate; a semiconductor device comprising a polymer layer and a metal pad having a contact point aligned with an opening in said polymer layer; a copper pillar between said contact point and said substrate, wherein said copper pillar has a height between 10 and 100 micrometers, wherein said copper pillar is connected to said contact point through said opening; a titanium-containing layer between said contact point and said copper pillar, wherein said titanium-containing layer is on said contact point, on said polymer layer and in said opening, wherein said copper pillar is connected to said contact point through said titanium-containing layer; a solder between said copper pillar and said substrate, wherein said solder joins said substrate, wherein said solder is connected to said copper pillar; and an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate and covers a sidewall of said copper pillar.