Patent ID: 7279733

Claim:
A dual damascene interconnection structure with a metal-insulator-metal capacitor, the structure comprising: a via-level intermetal dielectric and a trench-level intermetal dielectric which are sequentially stacked on a substrate; a dual damascene interconnection formed in the via-level intermetal dielectric and the trench-level intermetal dielectric, the dual damascene interconnection including: a line trench extending substantially completely through the trench-level intermetal dielectric to contact the via-level intermetal dielectric, and a via extending through the via-level intermetal dielectric without extending through the trench-level intermetal dielectric; a metal-insulator-metal capacitor formed between the via-level intermetal dielectric and the trench-level intermetal dielectric to include a lower electrode, a dielectric layer, and an upper electrode, the dual damascene interconnection being substantially electrically isolated from the metal-insulator-metal capacitor; and an upper metal interconnection formed on and connected to the upper electrode.