Patent ID: 7227482

Claim:
A complex band-pass filter comprising first and second circuit parts for executing at least first-order complex band-pass filtering processing on an inputted complex signal including first and second signals orthogonal to each other respectively to output a filtered complex signal including third and fourth signals orthogonal to each other, wherein the first circuit part comprises: a first adder for adding the first signal to an output signal from a first multiplexer, and outputting an addition result signal; a first delay device for delaying the addition result signal from the first adder by a predetermined time interval, and outputting a delayed output signal; a first inverter for changing a sign of the output signal from the first delay device, and outputting an output signal having a changed sign; and the first multiplexer for selecting the output signal from the first inverter and outputting the selected output signal to the first adder for a first time interval out of the first and second time intervals different from each other and alternately occurring, and for adding the output signal from the first delay device to the first adder for the second time interval, wherein the second circuit part comprises: a second adder for adding the second signal to an output signal from a second multiplexer, and outputting an addition result signal; a second delay device for delaying the addition result signal from the second adder by a predetermined further time interval, and outputting a delayed output signal; a second inverter for changing a sign of the output signal from the second delay device, and outputting an output signal having a changed sign; and the second multiplexer for outputting the output signal from the second delay device to the second adder for first time interval, and for selecting the output signal from the second inverter and outputting the selected output signal to the second adder for the second time interval, and wherein the complex band-pass filter comprises: a third multiplexer for outputting the first signal to the first adder and outputting the second signal to the second adder for the first time interval, and for outputting the first signal to the second adder and outputting the second signal to the first adder for the second time interval; and a fourth multiplexer for outputting the output signal from the first delay device as the third signal and outputting the output signal from the second delay signal as the fourth signal for the first time interval, and for outputting the output signal from the first delay device as the fourth signal and outputting the output signal from the second delay signal as the third signal for the second time interval.