Patent ID: 7662720

Claim:
A method of fabricating a semiconductor device comprising: alternately forming silicon layers doped with impurities and oxide layers on a semiconductor substrate; patterning the oxide layers and the silicon layers to form an oxide layer pattern and a silicon layer pattern having a contact hole to expose a region of the semiconductor substrate; forming a single crystalline silicon layer on a wall of the contact hole; forming a charge storing layer on the single crystalline silicon layer; forming a gate in the contact hole; patterning the oxide layer pattern and the silicon layer pattern to form a trench to expose the semiconductor substrate and the silicon layer pattern, thereby forming a bit line from the silicon layer pattern; forming a trench isolation layer to bury the trench; and forming a source and a drain region in the silicon layer pattern, the source and the drain region being isolated from each other along a vertical direction, a channel region interposed between the source and the drain regions.