Patent ID: 8645117

Claim:
A method comprising: receiving a design file representative of a data processing device; receiving at a computer a first frequency value indicating a frequency of a first external clock signal to be provided to a first external interface of the data processing device; receiving at the computer a second frequency value indicating a frequency of a second external clock signal to be provided to a second external interface of the data processing device; identifying a plurality of internal clock signals corresponding to internal nodes of the data processing device, the internal clock signals generated internally by one or more modules of the data processing device; for each internal clock signal of the plurality of internal clock signals, determining a multiplier expressing a ratio between a frequency of the internal clock signal and the first frequency value, thereby determining a plurality of multipliers; determining at the computer a first least common multiple representing a least common multiple of the plurality of multipliers; determining at the computer a second least common multiple representing a least common multiple of the first frequency value and the second frequency value; determining at the computer a first pulse width of the first external clock signal based on the first least common multiple and the second least common multiple; and simulating operation of the data processing device based on the first external clock signal having the first pulse width.