Patent ID: 8779491

Claim:
A capacitor, comprising: an insulating layer on a substrate, said insulating layer including a via having sidewalls and a bottom; a first electrode overlying said sidewalls and at least a portion of said bottom of said via; a first high-k dielectric material layer overlying said first electrode; a first conductive plate over said first high-k dielectric material layer; a second high-k dielectric material layer formed to overlie the first conductive plate and to leave a remaining portion of said via unfilled; a second electrode formed in said remaining portion of said via, wherein said first conductive plate is substantially parallel to said first electrode and is not in contact with said first and second electrodes; a lower interconnect level between said substrate and said insulating layer, said lower interconnect level including a first dielectric layer having a first conductive feature embedded therein; and an upper interconnect level above said insulating layer, said upper interconnect level including a second dielectric layer having a second conductive feature embedded therein, wherein said first electrode is in contact with said second conductive feature and said second electrode is in contact with said first conductive feature, wherein said second high-k material layer has i) a portion substantially parallel with said substrate, ii) a portion substantially perpendicular with said substrate, and iii) a portion neither substantially perpendicular and neither substantially parallel with said substrate.