Patent ID: 7190067

Claim:
A semiconductor package with an exposed heat sink, comprising: a carrier having a first surface and a second surface; at least one chip mounted on the first surface of the carrier and electrically connected to the carrier; a heat sink comprising a flat portion having an exposed surface, and a support portion extended peripherally from the flat portion and attached to the first surface of the carrier, wherein the flat portion, the support portion and the carrier form a space where the chip is received, and the flat portion is peripherally formed with a stepped structure having a plurality of steps and at least one flash preventing groove located at a position adjacent to the exposed surface, wherein the flash preventing groove has a side wall, and the height of an edge of the side wall is lower than that of the exposed surface of the heat sink; and an encapsulant for encapsulating the chip, the heat sink, and a portion of the carrier, with the exposed surface of the flat portion being exposed from the encapsulant, wherein a portion of the encapsulant is formed on the steps, the steps having successively decreased elevations.