Patent ID: 7389101

Claim:
A parallel-configured image-reject receiver, comprising: a receiver input node; a receiver output node; a first quadrature downconversion mixer having an input electrically coupled to the receiver input node, a first output and receiving a first local oscillator (LO) signal from a first LO block; a second quadrature downconversion mixer having an input electrically coupled to the receiver input node, a second output and receiving a second LO signal from said first LO block, said second LO signal differing in phase from said first LO signal by 90 degrees; a third quadrature downconversion mixer having an input electrically coupled to said first output, a third output and receiving a third LO signal from a second LO block; a fourth quadrature downconversion mixer having an input electrically coupled to said second output, a fourth output and receiving a fourth LO signal from said second LO block, said fourth LO signal differing in phase from said third LO signal by 90 degrees; and a summing junction having a first input electrically coupled to said third output, a second input electrically coupled to said fourth output, and a summing junction output node connected to the receiver output node, said first, second, third and fourth quadrature downconversion mixers each including at least one floating gate, the charge on which adjusts the phase of the respectively received LO signal.