Patent ID: 7797516

Claim:
A device, comprising: means for receiving an arithmetic instruction; means for determining that the arithmetic instruction is a single Multiply-Accumulate (MAC) instruction, including detecting an appended code in the arithmetic instruction, the appended code operable to alter a function performed by the arithmetic instruction, wherein the appended code is a prefix to the arithmetic instruction and not part of the original arithmetic instruction; a first register operable for storing a first operand associated with the MAC instruction; a second register operable for storing a second operand associated with the MAC instruction; means for multiplying the first and second operands to form a current product; and means for adding the current product to one or more stored products previously generated by the multiplying means in accordance with the MAC instruction; wherein the first and second registers are 16-bit registers, each formed by combining two 8-bit registers of an 8051 architecture, wherein: the first register is formed by extending an accumulator of the 8051 architecture with an 8-bit register; and the second register is formed by extending a B register for the 8051 architecture with another 8-bit register.