Patent ID: 8448008

Claim:
An integrated circuit for clock control, comprising: a glitch-elimination module that generates a first glitch-free clock waveform for clock systems of a core logic circuit in a shift operation of a logic test of the core logic circuit; and a plurality of clock control modules that generate a plurality of glitch-free clock waveforms for the clock systems of the core logic circuit in a capture operation of the logic test of the core logic circuit, each of the plurality of clock control modules including: a clock control sub-module that generates clock enabling pulses based on a clock control signal and a clock signal; a glitch-elimination sub-module that generates, based on the clock enabling pulses, a second glitch-free clock waveform with 0 to k pulses for one of the clock systems of the core logic circuit in the capture operation; and a combination sub-module that combines the first glitch-free clock waveform and the second glitch-free clock waveform with 0 to k pulses.