Patent ID: 8071399

Claim:
A manufacturing method of a semiconductor integrated circuit device comprising the steps of: (a) providing a semiconductor wafer having a plurality of chip formation regions, each of the chip formation regions including a semiconductor integrated circuit and a plurality of electrodes electrically coupled to the semiconductor integrated circuit, and providing a semiconductor wafer, for which a reference sample image of a surface state of the semiconductor wafer including the chip formation regions is obtained; (b) providing a probe-card having a plurality of contact terminals that can contact with the electrodes of the semiconductor wafer; (c), by bringing tips of the contact terminals of the probe-card into contact with the electrodes of a first chip formation region selected from among the chip formation regions of the semiconductor wafer, testing electrically the semiconductor integrated circuit of the first chip formation region; (d), after the step (c), obtaining a first image of a surface state of the semiconductor wafer including the first chip formation region and a second chip formation region outside of the first chip formation region; and (e), after the step (d), comparing the first and second chip formation regions in the first image with the first and second chip formation regions in the reference sample image.