Patent ID: 8254184

Claim:
A semiconductor memory device including a latency controller, wherein the latency controller comprising: a clock generator configured to generate a plurality of transmission clock signals and to generate a plurality of sampling clock signals, each sampling clock signal delayed for a time corresponding to a set read latency with respect to the corresponding one of the transmission clock signals; a first-in first-out (FIFO) register configured to store an internal read signal in response to at least one sampling clock signal of the sampling clock signals and to generate a latency signal in response to a transmission clock signal corresponding to the sampling clock signal for storing the internal read signal; and a clock blocking unit configured to block application of the sampling clock signal to the FIFO register in response to a power-down signal and to block application of the transmission clock signal to the FIFO register when the power-down signal is applied to the clock blocking unit and a number of times the internal read signal is applied is equal to a number of times the latency signal is applied.