Patent ID: 7602215

Claim:
A shift register comprising: a plurality of stages of flip-flop circuits each of which includes a clocked inverter, said clocked inverter comprising: an inverter comprising a first transistor and a second transistor which are connected in series; a first compensation circuit comprising a third transistor and a fourth transistor which are connected in series; and a second compensation circuit comprising a fifth transistor and a switching element, wherein a drain of the first transistor and a drain of the second transistor are connected to an output terminal of the clocked inverter; wherein a source of the first transistor and a source of the fourth transistor are connected to a first power source; wherein a source of the second transistor and a source of the fifth transistor are connected to a second power source; wherein a gate of the third transistor and a gate of the fourth transistor are inputted with a signal outputted from the clocked inverter used in the flip-flop circuit of the preceding stage; wherein a gate of the fifth transistor and a control terminal of the switching element are inputted with a signal outputted from the flip-flop circuit of a succeeding stage; wherein an input terminal of the switching element is inputted with a clock signal; wherein an output terminal of the switching element and a drain of the fifth transistor are connected to a gate of the second transistor; wherein a drain of the third transistor is inputted with a signal outputted from the clocked inverter used in the flip-flop circuit of two stages before; and wherein a source of the third transistor and a drain of the fourth transistor are connected to a gate of the first transistor.