Patent ID: 7487482

Claim:
A method for evaluating a constraint of a sequential memory cell able to sample an input data item regulated by a clock signal, the constraint being dependent on the ramp of a first signal and on the ramp of a second signal, these two signals being delivered to the sequential memory cell and including the clock signal, the constraint being at least one of a setup time and a hold time of the data item, the method comprising a characterization phase comprising: a first determination of a first set of values of the constraint including a simulation using a model of the sequential memory cell wherein a value of the second ramp is fixed and a value of the first ramp is varied; a second determination, for each value of the second ramp wherein the value of the second ramp is varied, of a deviation with respect to a value of the constraint belonging to the first set of values and corresponding to a fixed value of the first ramp which is fixed at a value from the first determination; and a third calculation wherein the values of the constraint are calculated for all values of the first ramp and of the second ramp, by adding the determined deviations to the values of the first set of values.