Patent ID: 8185695

Claim:
A computing system comprising: a processor core; a shared cache memory subsystem comprising a plurality of shared entries for storing data accessible by one or more processor cores; a shared cache controller for the shared cache memory subsystem; and wherein the shared entries are configured to selectively store either processor data or directory entries comprising directory information for controlling a global coherence protocol; wherein the shared cache controller is configured to store a value to control whether at least some of the shared entries store processor data or directory information; and wherein an initially cached copy of processor data following a corresponding miss in the directory entries for any type of memory access request has an exclusive-modified (EM) state placed in its corresponding directory entry; wherein each cached copy of data corresponding to an address location mapped to a location in a first system memory has a corresponding directory entry, wherein said directory information indicates whether said cached copy is in an EM, owned, shared, a shared-one or invalid state, wherein the shared-one state indicates all cached copies of the corresponding data exist in a single node, and wherein directory entries with the shared-one state have a higher priority for eviction in a cache replacement algorithm than directory entries with owned or shared states.