Patent ID: 8394702

Claim:
A method for making a semiconductor device, comprising: a) providing a semiconductor substrate; b) applying a first mask on top of the semiconductor substrate; and forming trenches TR 1 , TR 2 with widths W 1 , W 2 , respectively, wherein W 1 is narrower than W 2 , wherein the trenches TR 2 include first and second gate runner trenches connected to the trenches TR 1 , wherein at least one of the first and second gate runner trenches abuts and surrounds the trenches TR 1 ; and forming trench T 3 with width W 3 , wherein W 1 is narrower than W 3 and wherein the trench TR 3 includes a termination trench that surrounds the trenches TR 1 and the gate runner trenches TR 2 ; c) forming a gate insulator on the bottoms and sidewalls of the trenches TR 1 , TR 2 , with corresponding thickness T 1 , T 2 wherein T 2 is greater than T 1 ; and forming gate insulator on the bottoms and sidewalls of the trenches TR 3 with corresponding thickness T 3 , wherein T 3 is greater than T 1 ; d) forming a conductive material in the trenches TR 1 to form gate electrodes and forming a conductive material in the trenches TR 2 , to form first and second gate runners and a termination structure, wherein the first and second gate runners are in electrical contact with the gate electrodes; and forming a conductive material in the TR 3 , to form a termination structure, wherein the termination structure is electrically isolated from the gate runners and the gate electrodes; e) forming a body layer in a top portion of the semiconductor substrate; f) forming a source layer in a top portion of the body layer; g) applying an insulator layer on top of the semiconductor substrate; h) applying a second mask on top of the insulator layer; i) forming electrical contacts through contact openings in the insulator layer using the second mask, wherein the contact openings include source openings to the source layer proximate each gate electrode, gate runner contact openings to the gate runners, termination contact openings to the termination structure, and a short contact opening to the source layer or body layer proximate a die edge, and wherein the contact openings include termination contact openings to the termination structure; and j) forming first and second metal regions on the insulator layer that are electrically isolated from each other, wherein the first metal region is in electrical contact with the gate runners and wherein the second metal region is in electrical contact with the source contact, wherein the thickness T 2 is thick enough to support a blocking voltage; and forming a third metal region on the insulator layer, wherein the third metal region is in electrical contact with the termination contact and the short contact, whereby the termination structure is shorted to the body region at the die edge, wherein the thickness T 3 is thick enough to support the blocking voltage.