Patent ID: 7813181

Claim:
In a nonvolatile memory having an array of storage elements accessible by word lines and bit lines, providing a selected group of storage elements accessible by a selected word line and an adjacent group of storage elements accessible by an adjacent word line, a method of sensing the page of storage elements in parallel, comprising: providing a first voltage having a first predetermined initial amplitude and a predetermined ramp rate; with the application of said first voltage to the adjacent word line, determining for each storage element of the adjacent group a time marker indicating when an associated storage element begins to conduct current, thereby encoding the state of each storage element in the time-domain; providing a second voltage having a second predetermined initial amplitude and a similar ramp rate to that of said first voltage; and while simultaneously applying said second voltage to the adjacent word line, sensing each storage element of the selected group at a time indicated by the time marker of a storage element of said adjacent group next to said each storage element.