Patent ID: 7555593

Claim:
A multi-pipelined content addressable memory (CAM) device, comprising: a first thread comprising a first search key and a first request; a second thread comprising a second search key and a second request; a CAM core including a plurality of CAM blocks, each CAM block including an individually searchable array of CAM cells; and control logic having a first input to receive the first thread, a second input to receive the second thread, and outputs coupled to the CAM blocks, the control logic configured to selectively enable simultaneous execution of first and second compare operations, wherein the first compare operation compares the first search key and data stored in a first number of CAM blocks selected by the first request, and the second compare operation compares the second search key and data stored in a second number of CAM blocks selected by the second request, wherein the control logic comprises: a first memory for storing the first search key and an associated first instruction; a second memory for storing the second search key and an associated second instruction; an arbiter having inputs to receive the first and second requests, having a first output to provide read and write control signals to the first memory, having a second output to provide read and write control signals to the second memory, and having a third output to generate a block select signal; and an input switch matrix having a first input to receive the first search key, a second input to receive the second search key, a plurality of outputs each coupled to a corresponding CAM block, and a control terminal to receive the block select signal.