Patent ID: 8654567

Claim:
A semiconductor memory device comprising: a bit line; a plurality of word lines; a memory cell comprising a plurality of sub memory cells, the sub memory cells each comprising a first transistor and a capacitor; a second transistor; a third transistor; an amplifier; a first selection line; a second selection line; and a sub bit line, wherein a gate of the second transistor is electrically connected to the first selection line, wherein one of a source and a drain of the second transistor is electrically connected to the bit line, wherein the other of the source and the drain of the second transistor is electrically connected to a first terminal of the amplifier, wherein one of a source and a drain of the first transistor in each of the plurality of sub memory cells is electrically connected to the first terminal of the amplifier, wherein a second terminal of the amplifier is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the bit line, wherein a gate of the third transistor is electrically connected to the second selection line, wherein the other of the source and the drain of the first transistor is electrically connected to the capacitor, wherein a gate of the first transistor is electrically connected to one of the plurality of word lines, and wherein capacitances of the capacitors in the plurality of sub memory cells are different from each other.