Patent ID: 8140738

Claim:
A memory interface module for interfacing between a host processor and a plurality of flash memories, the plurality of flash memories obeying a plurality of different protocols, said memory interface module comprising: a flash interface configured to be coupled between a host processor connection to the memory interface module and each of the plurality of flash memories, the flash interface supplying driving device control signals; a plurality of register files including: an address register configured to store an address of a memory read/write location in a particular one of the plurality of flash memories and a command register configured to store device commands to control operation of that particular one of the plurality of flash memories; a plurality of operation information registers configured to store a command received from the host processor to control flash memory operation; a finite state machine (FSM) configured to extract the command from the operation information registers, the FSM including a plurality of states relating to driving device control signals with respect to each of the plurality of flash memories, there being a sequence of states for interfacing with each of the plurality of flash memories, wherein transitions between the plurality of states in the sequence of states are controlled by software in the form of instruction-operand pairs executed in response to the extracted command, each instruction-operand pair controlling the generation of the device control signals supplied by the flash interface, wherein the operand of certain instruction-operand pairs identifies the address register within the register files which stores the memory read/write location address, and wherein the operand of certain other instruction-operand pairs identifies the command register within the register files which stores the device command.