Patent ID: 7602665

Claim:
A semiconductor memory circuit device comprising: a clock generating circuit including a delay circuit which receives first clock signals and outputs second clock signals by delaying the first clock signals by a predetermined delay time, a phase comparison circuit which compares a phase of third clock signals based on the second clock signals and a phase of the first clock signals and outputs control signals, and a control circuit which controls the delay circuit for coinciding the phase of the first clock signals and the phase of the third clock signals by the control signals; an internal circuit responding to the second clock signals and including a plurality of word lines, a plurality of pairs of complementary bit lines, a plurality of memory cells to maintain storage information and a plurality of amplifiers connected to the plurality of pairs of complementary bit lines and amplifying signals that appear in the pairs of complementary bit lines; a first lead receiving a first power source potential assumed to be a first potential which is supplied from outside of the semiconductor memory circuit device; a first supply unit receiving the first power source potential from the first lead; a second lead which is different from the first lead receiving a second power source potential assumed to be a first potential supplied from outside of the semiconductor memory circuit device; and a second supply unit receiving the second power source potential from the second lead, wherein the internal circuit is supplied the first potential from the first supply unit, and wherein the delay circuit is supplied the first potential from the second supply unit.