Patent ID: 7074664

Claim:
A method of forming gate electrodes in a semiconductor fabrication process, comprising: forming a gate dielectric overlying a semiconductor substrate; depositing a first gate electrode layer overlying the gate dielectric; removing portions of the first gate electrode layer thereby exposing portions of the gate dielectric; depositing a second gate electrode layer overlying the first gate electrode layer and exposed portions of the gate dielectric; and removing the second gate electrode layer where it overlies the first gate electrode layer wherein remaining portions of the first and second gate electrode layers have substantially the same thickness, wherein a majority of the first gate electrode layer overlies a first well region of the substrate and wherein a majority of the second gate electrode layer overlies a second well region of the substrate, and wherein the first well region is an NWELL region and the first gate electrode layer is TiN and wherein the second well region is an PWELL region and the second gate electrode layer comprises TaSiN, TaC, or Ta x C y N z .