Patent ID: 7478255

Claim:
A system comprising: a plurality of processing cells each having a plurality of processors; and each processing cell receiving an extracted clock for use in at least one of the following ways a) the extracted clock being replicated to provide a plurality of first clocks each being fed to a processor of the processing cell; b) the extracted clock being used as phase information in conjunction with a first clock source to provide a plurality of second clocks each being fed to a processor of the processing cell; wherein the extracted clock was extracted from an encoded clock being combined with data and sent to the processing cell over a link that allows at least two processing cells to communicate with one another via a switch; wherein the link is associated with a failed-over link, the encoded clock is associated with a failed-over encoded clock, the extracted clock is associated with a failed-over extracted clock, the first clock source is associated with a failed-over first clock source.