Patent ID: 7203860

Claim:
A clock recovery circuit comprising: a phase comparator circuit carrying out phase comparison between an input signal and an output signal, and outputting a phase control signal proportional to a phase difference between said input signal and said output signal, wherein said input signal and said output signal are each a differential signal; a phase adjusting circuit receiving said phase control signal from said phase comparator circuit, adjusting the phase of said input signal, and producing said output signal, wherein said phase adjusting circuit comprises a mixer circuit having a plurality of differential transistor pairs to which reference clocks of different phases are input, and a plurality of current sources controlling currents flowing through said respective differential transistor pairs, wherein each of said current sources applies a weight proportional to the output of said phase comparator circuit to said reference clock supplied to the differential transistor pair corresponding to said each current source, and producing said output signal by combining the weighted reference clocks at a node to which said plurality of differential transistor pairs are connected in common; and a duty cycle correction circuit receiving said output signal from said phase adjusting circuit, and correcting the duty cycle of said output signal, wherein said duty cycle correction circuit controls the center voltage of the node to which said plurality of differential transistor pairs are connected in common, and corrects the center voltage of said output signal.