Patent ID: 8539428

Claim:
A method for extracting information for a circuit design, comprising: dividing the circuit design into a plurality of dies; evaluating a weight to be assigned to each one of the plurality of dies, wherein the weight of a die of the plurality of dies represents a cost of extracting one or more design shapes from the die; receiving a rectangular region defining an area where information for the circuit design is to be extracted, wherein the information for the circuit design includes one or more electrical characteristics for the circuit design, wherein the one or more electrical characteristics comprises at least one of capacitance, resistance, and inductance; receiving a target number of partitions desirable for the rectangular region; iteratively dividing, by a processor, the rectangular region into a plurality of subregions until a sub-target number for each sub-region is one, comprising: determining a first sub-target number and a second sub-target number, the sum of the first and the second sub-target numbers equal the target number of partitions; dividing the rectangular region into a first sub-region and a second sub-region, the first sub-region having a first weight calculated based on the weight of dies in the first sub-region, the second sub-region having a second weight calculated based on the weight of dies in the second sub-region, where a ratio of the first weight to the second weight substantially matches a ratio of the first sub-target number to the second sub-target number; further dividing the first sub-region when the first sub-target number is greater than one; and further dividing the second sub-region when the second subtarget number is greater than one; and extracting information for at least two sub-regions in parallel.