Patent ID: 8035543

Claim:
An analog-to-digital conversion circuit comprising: a comparator array comprising a plurality of comparators for comparing a plurality of reference voltages with an analog signal, respectively, and for outputting logic signals based on results of the comparisons; and an averaging circuit comprising a plurality of metal routings for compensating an offset in at least one of the logic signals output from the plurality of comparators, wherein a length of a metal routing connected between an output terminal of a first comparator of the comparators to which a minimum reference voltage from among the plurality of reference voltages is input and an output terminal of a second comparator of the comparators to which a maximum reference voltage from among the plurality of reference voltages is input is less than a length of a metal routing connected between output terminals of the first comparator and a third one of the comparators receiving one of the reference voltages having a level closest in magnitude to the minimum reference voltage, wherein the second comparator is adjacent both the first and third comparators.