Patent ID: 7605877

Claim:
An array substrate for use in a liquid crystal display device, comprising: a gate electrode, a gate line and a gate pad on a substrate, wherein the gate electrode, the gate line and the gate pad have a double-layered structure including a first metal layer and a first barrier metal layer in series from the substrate, and wherein the first metal layer is one of aluminum and aluminum alloy; a gate insulation layer on the substrate covering the gate electrode, gate line and gate pad; an active layer and an ohmic contact layer sequentially formed on the gate insulation layer and over the gate electrode; a data line on the gate insulation layer perpendicularly crossing the gate line, source and drain electrodes contacting the ohmic contact layer, and a data pad on the gate insulation layer, wherein the data line, the source and drain electrodes and the data pad have a double-layered structure consisting of a second barrier metal layer and a second metal layer of copper, wherein the second barrier metal layer is interposed between the substrate and the second metal layer of copper; a passivation layer formed on the gate insulation layer to cover the data line, source and drain electrodes, and data pad, wherein the passivation layer has a drain contact hole exposing a portion of the drain electrode, a gate pad contact hole exposing a portion of the gate pad, and a data pad contact hole exposing a portion of the data pad; and a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer, all of which are formed of a transparent conductive material on the passivation layer, wherein a width of the gate pad contact hole is greater than a width of the gate pad, wherein the gate pad terminal contacts an upper surface of the first barrier metal layer of the gate pad and side surfaces of the first barrier metal layer and the first metal layer of the gate pad through the gate pad contact hole.