Patent ID: 7256136

Claim:
A dual damascene interconnect pattern created in a layer of insulation, comprising: a layer of conductive material having been provided over a semiconductor surface, a layer of Anti Reflective Coating (ARC) having been deposited over the layer of conductive material; a first layer of Photo-Active Dielectric (PAD) having been deposited over the layer of ARC, the first layer of PAD having been second patterned and developed, having created a via pattern of a dual damascene pattern therein; a second layer of Photo-Active Dielectric having been deposited over the first layer of Photo-Active Dielectric, the second layer of Photo-Active Dielectric comprising a Photo-Active Dielectric material having a different chemical composition than the first layer of Photo-Active Dielectric, the second layer of PAD having been first patterned and developed, having created a trench pattern of the dual damascene pattern therein aligned with the via pattern; the exposed ARC having been removed from underneath the dual damascene interconnect pattern; and the trench pattern and the via pattern having been filled with a conductive material.