Patent ID: 8724397

Claim:
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory string provided above the semiconductor substrate, and comprising a plurality of memory cells; a first select transistor having one end connected to a first end of the memory string; a second select transistor having one end connected to a second end of the memory string; and a control circuit configured to perform a read operation of reading data held in a selected memory cell among the memory cells; the memory string comprising: a semiconductor layer extending in a direction perpendicular to the semiconductor substrate, and functioning as a body of a memory cell; a charge accumulation layer configured to be capable of accumulating a charge; and a conductive layer sandwiching the charge accumulation layer with the semiconductor layer, and functioning as a gate of the memory cell, the control circuit performing, before the read operation, a refresh operation of rendering the selected memory cell and a non-selected memory cell conductive to conduct a current from the first end to the second end of the memory string, the control circuit rendering, during the refresh operation, the first select transistor, the selected memory cell, and the non-selected memory cell conductive, and then rendering the second select transistor conductive, and the control circuit performing the refresh operation when the number of a write operation of writing data to the memory cell and an erase operation of erasing data held in the memory cell reaches a first number.