Patent ID: 8773171

Claim:
A voltage buffer, comprising: a first transistor, having a first terminal, a control terminal and a second terminal, wherein the first terminal of the first transistor is coupled to a first reference voltage and the control terminal of the first transistor is coupled to a first bias voltage; a second transistor, having a first terminal, a control terminal, a second terminal and a bulk terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the first transistor, the control terminal of the second transistor is coupled to an input voltage, and the second terminal of the second transistor is coupled to an output voltage; a third transistor, having a first terminal, a control terminal and a second terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the second transistor, the control terminal of the third transistor is coupled to a second bias voltage, and the second terminal of the third transistor is coupled to a second reference voltage; and a voltage detector, coupled between the second terminal of the first transistor and the bulk terminal of the second transistor, receiving and detecting a voltage of the second terminal of the first transistor to generate a detection result and outputting the detection result to the bulk terminal of the second transistor.