Patent ID: 7840926

Claim:
A semiconductor device, comprising: a logic circuit; and one or more power gating transistor switches; wherein the logic circuit is connected between a power voltage and a ground voltage, wherein the logic circuit performs one or more logic operations, wherein the one or more power gating transistor switches include: a plurality of power gating transistors; and a plurality of poly resistors associated with the power gating transistors; wherein the one or more power gating transistor switches are turned on by a power gating enable signal having a different logic level according to an active mode, a sleep mode, or active and sleep modes of the logic circuit in order to switch application of the power voltage to the logic circuit in response to the power gating enable signal or an inversion signal of the power gating enable signal, wherein the one or more power gating transistor switches use the poly resistors to sequentially apply the power voltage to the logic circuit, to sequentially block the application of the power voltage to the logic circuit, or to sequentially apply the power voltage to the logic circuit and to sequentially block the application of the power voltage to the logic circuit, and wherein the poly resistors are between gates of adjacent power gating transistors.