Patent ID: 7335938

Claim:
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory unit including a plurality of memory cell transistors formed on the semiconductor substrate and aligned along a predetermined direction via a first diffusion layer formed in the semiconductor substrate, each of the memory cell transistors configured with a floating gate disposed on the semiconductor substrate via a first insulating film, a control gate disposed above the floating gate via a first inter-gate insulating film, respectively; and a select gate transistors, disposed at an end of the memory unit and aligned along the predetermined direction via a second diffusion layer formed in the semiconductor substrate, the select gate transistor configured with a lower gate disposed on the semiconductor substrate via a second insulating film and including a flat upper surface having a first region and a second region, an upper gate disposed on the first region via a second inter-gate insulating film and including a first side surface, a conductive oxide film disposed on the second region of the flat upper surface and the first side surface, and a sidewall gate disposed on the second region of the lower gate via the conductive oxide film and including a second side surface facing to the first side surface of the upper gate via the conductive oxide film.