Patent ID: 7093053

Claim:
A single memory bus multi-media computer system, comprising: a CPU/Sound/Graphic unit connected to a program and sound bus and a graphic bus; a bus arbitrator connected to said program and sound bus and said graphic bus on a first side, and a single memory bus on a second side, said bus arbitrator including an address bus multiplexer for receiving a program and sound bus address and a graphic bus address as inputs, and outputting a single memory bus address, and a first data register for storing memory data from said single memory bus, said memory data being controlled by a bus control signal OEB for being temporarily stored in said first data register or directly outputted to a graphics data bus; a program and sound and graphic memory connected to said single memory bus; and a TV/LCD signal unit for outputting audio and video signals; wherein said CPU/Sound/Graphic unit requests said program and sound and graphic memory by memory addresses, processes data returned from said program and sound and graphic memory, and sends signals to said TV/LCD signal unit for outputting, said bus arbitrator sits between said CPU/Sound/Graphic and said program and sound and graphic memory to arbitrate the memory requests from said CPU/Sound/Graphic unit to said program and sound and graphic memory.