Patent ID: 7838393

Claim:
Process for making a closed or semi-closed volume, involving a first and second semiconductor on insulator type wafers, each of these wafers comprising at least one semiconducting surface layer on an electrically insulating layer, this insulating layer being itself supported on a substrate, this process comprising: in the first semiconductor on insulator type wafer, etching of the semiconducting surface layer, the insulating layer forming an etch-stop layer, wherein a portion of the insulating layer in contact with the substrate is not removed, to make at least one cavity, in the second semiconductor on insulator type wafer, etching of the semiconducting surface layer, the insulating layer forming an etch-stop layer, wherein a portion of the insulating layer in contact with the substrate is not removed, to make at least one membrane, etching of the substrate and the electrically insulating layer of the first and second wafers, alignment of said two wafers, assembly of said two wafers, so as to position said membrane against said cavity, said membrane acting as a valve for said cavity, a thinning step performed on at least one of the two wafers, after assembly of these two wafers.