Patent ID: 7672326

Claim:
A double data rate serial media independent interface (SMII) circuit, comprising: a transmit circuit that, in response to a clock signal, samples serial transmit data on a clock rising edge to generate a first transmit serial stream, wherein the transmit circuit, in response to the clock signal, samples the serial transmit data on a clock falling edge to generate a second transmit serial stream; a receive circuit that, in response to the clock signal, generates a receive serial stream from two receive data streams, wherein the receive serial stream has a first operating frequency, wherein each of the two receive data streams have a second operating frequency, and wherein the first operating frequency is about twice the second operating frequency; a transmit port corresponding to the transmit circuit, wherein the transmit port includes a single terminal communicate the serial transmit data to the transmit circuit; and a receive port corresponding to the receive circuit, wherein the receive port includes a single terminal to communicate the receive serial stream from the receive circuit.