Patent ID: 7067390

Claim:
A method for forming an isolation layer of a semiconductor device, the method comprising the steps of: i) providing a semiconductor substrate having a predetermined isolation region; ii) sequentially forming a pad oxide layer and a pad nitride layer exposing the predetermined isolatIon region on the semiconductor substrate; iii) forming a trench through etching the semiconductor substrate by a predetermined thickness using the pad nitride layer as a mask; iv) forming a wall oxide layer at a side wall of the trench; v) sequentially forming a nitride layer and an oxide layer on a trench structure including the wall oxide layer; vi) forming an Al 2 O 3 layer on an entire surface of a resultant structure, wherein the Al 2 O 3 layer has a wet etch rate less than 0.5 Å /sec in HF solution having a ratio of 50:1 to prevent damage to the Al 2 O 3 layer during a subsequent wet etching step; vii) planarizing the Al 2 O 3 layer through polishing the Al 3 O 3 layer, and viii) removing the pad nitride layer and the pad oxide layer by one or more wet etching processes without damaging the Al 2 O 3 layer.