Patent ID: 7268400

Claim:
A structure, comprising: a buried P-type doped layer in a P-type silicon substrate, a top surface of said buried P-type doped layer extends a first distance below a top surface of said substrate; an N-well and a P-well, both said N-well and said P-well extending from said top surface of said substrate to said top surface of said buried P-type doped layer; a buried N-type doped layer in said P-well, a bottom surface of said buried N-type doped layer in contact with said top surface of said buried P-type doped layer, said buried N-type doped layer extending from said top surface of said buried P-type doped layer toward said top surface of said substrate a second distance, said second distance less than said first distance; a PFET formed in said N-well and an NFET formed in said P-well; a P-type contact formed in said P-well and an N-type contact formed in said N-well, both said P-type contact and said N-type contact extending from said top surface of said substrate into said substrate respective third and fourth distances, said third and fourth distances less than a fifth distance between said top surface of said buried N-type doped layer and said top surface of said substrate; and a gap in said buried N-type doped layer, said gap aligned under said P-type contact, said P-well contacting said top surface of said buried P-type doped layer in said gap.