Patent ID: 7298949

Claim:
A photonic bandgap (PBG) electro-optic device formed within a silicon-on-insulator (SOI) structure comprising a silicon substrate, an insulating layer disposed over the substrate and a relatively thin silicon surface layer (SOI layer) formed over the insulating layer, the SOI layer used, at least in part, for guiding the mode of an optical signal propagating therethrough, the PBG electro-optic device comprising: a relatively thin dielectric layer disposed over at least a portion of the SOI layer; a silicon layer disposed over at least a portion of the relatively thin dielectric layer in a manner such that overlapping portions of the relatively thin SOI layer, the relatively thin dielectric layer and the silicon layer define an active region of the device, the silicon layer and SOI layer exhibiting complementary doping within the active region; a plurality of columnar holes formed through the SOI structure and disposed in a predetermined pattern such that the spacing between adjacent holes defines a photonic bandgap structure including an optical waveguiding region within at least a portion of the SOI layer, the photonic bandgap structure providing lateral confinement of a propagating optical mode within the optical waveguiding region; and first and second electrical contacts disposed at locations disparate from the optical waveguiding region and substantially adjacent to the plurality of columnar holes on the SOI structure so as to absorb a minimum amount of the signal propagating along the optical waveguiding region, wherein upon application of an electrical signal between the first and second electrical contacts, free carriers move such that the optical field of said propagating optical signal is bounded, at least in part in the lateral dimension, by the photonic bandgap structure, the optical field thereby substantially overlapping the free carrier concentration modulation area in the active region of the electro-optic device, wherein the first electrical contact is coupled to the SOI layer and the second electrical contact is coupled to the silicon layer such that upon application of an electrical signal between the first and second electrical contacts, free carriers accumulate, deplete or invert within the SOI layer and the silicon layer on both sides of the relatively thin dielectric layer at the same time.