Patent ID: 7220651

Claim:
A method for manufacturing a transistor, the method comprising the steps of: sequentially forming a gate oxide film, a polysilicon film for gate electrode and a hard mask film on a semiconductor substrate; patterning the hard mask film and the polysilicon film for gate electrode via a photolithography process using a gate mask to form a stacked structure of a gate electrode having two sidewalls and a hard mask film pattern; performing a first thermal oxidation process to form a first thermal oxide film by oxidizing the two sidewalls of the gate electrode and an upper surface of the gate oxide film, wherein the first thermal oxide film has a protruding portion extending into a lower portion of the gate electrode; performing an ion implant process using the hard mask film pattern as an implant mask to form a source/drain region on the semiconductor substrate at both sides of the gate electrode; removing a portion of the first thermal oxide film and the gate oxide film therebelow so as to expose at least one sidewall and the lower portion of the gate electrode and the semiconductor substrate; performing a second thermal oxidation process to form a second thermal oxide film by oxidizing the exposed portion of the gate electrode and the semiconductor substrate; and forming an insulating film spacer on sidewalls of the stacked structure, wherein the insulating film spacer fills the space between the lower surface of the gate electrode and the upper surface of the semiconductor substrate.