Patent ID: 7464129

Claim:
Circuitry for carrying out a square root operation, said circuitry comprising: iteration circuitry for carrying out a plurality of iterations, wherein said iteration circuitry comprises a plurality of sets of iteration circuitry, at least one set of iteration circuitry being arranged to receive an output from a preceding one of said sets of iteration circuitry and provide input to a subsequent set of iteration circuitry, each of said sets of iteration circuitry comprising: root multiple circuitry for calculating from a positive quotient value and a negative quotient value received from a preceding iteration an output positive quotient value and negative quotient value for output to a subsequent iteration, wherein the output quotient values include calculated first root multiple bits, the root multiple circuitry further calculating second root multiple bits for separate output to the subsequent iteration; and remainder circuitry for calculating from an upper remainder and the second root multiple bits received from the preceding iteration an output upper remainder for the subsequent iteration, the remainder circuitry using the second root multiple bits to modify the received upper remainder and generate the output upper remainder.