Patent ID: 7876591

Claim:
A semiconductor memory device having a double-patterned memory cell array, the memory cell array comprising: a plurality of first bit lines spaced apart from each other and having a first pattern; a plurality of second bit lines spaced apart from each other and having a second pattern, the second bit lines being between the first bit lines to define an alternating array of first and second bit lines, the first and second patterns being different from each other; a first main memory cell array defined by a first portion of the alternating array; a second main memory cell array defined by a second portion of the alternating array, bit lines in the first main memory cell array having a substantially same regularity as bit lines in the second main memory cell array; and a dummy array between the first main memory cell array and the second main memory cell array, the dummy array including a plurality of dummy bit lines, wherein the first pattern has a first critical dimension distribution and the second pattern has a second critical dimension distribution, the first and second critical dimension distributions having different peak values.