Patent ID: 8339870

Claim:
A semiconductor memory device comprising: a plurality of memory banks configured to be separately accessible; a plurality of high voltage suppliers corresponding to the memory banks and configured to generate a high voltage; a high voltage generation control circuit configured to enable the high voltage suppliers corresponding to accessed memory banks of the plurality of memory banks during a normal operation and sequentially enable the high voltage suppliers to generate high voltage until the high voltage reaches a reference level during a CBR refresh operation; a pulse signal generator configured to be enabled, during the refresh operation, to output a pulse signal; and a counter configured to count the pulse signal and sequentially output a plurality of selection signals, wherein each of the plurality of high voltage suppliers includes, a transmitter configured to be enabled in response to an individual selection signal of the plurality of selection signals, and a pumper corresponding to the transmitter and configured to generate high voltage based on a transmitted pulse signal from the transmitter.