Patent ID: 7871876

Claim:
A method of forming a dual-plane complementary metal oxide semiconductor (CMOS) device, comprising: patterning a first fin on a {110} crystalline oriented surface of a first substrate; patterning a second fin on a {100} crystalline oriented surface of a second substrate, said second substrate being bonded and adjacent to said first substrate in said dual-plane CMOS device; forming a first tri-gate over said first fin and a second tri-gate over said second fin; forming a first spacer around said first tri-gate and portions of said first fin, and a second spacer around said second tri-gate and portions of said second fin; depositing a dielectric on portions of said first and second substrates not covered by said first and second fins and said first and second spacers; etching portions of said dielectric and said first and second fins to expose portions of said first and second substrates; forming first and second strain inducing source/drain regions, within said etched portions, on said first and second substrates, respectively, wherein said first strain inducing source/drain regions are not recessed into said first substrate and apply stress to said first fin of a p-type fin type field effect transistor (p-FinFET), and wherein said second strain inducing source/drain regions are not recessed into said second substrate and apply stress to said second fin of a n-type fin type field effect transistor (n-FinFET); and forming a tensile strain layer over at least said n-FinFET.