Patent ID: 8159209

Claim:
A digital signal delay measuring circuit for measuring a delay time of a digital signal of a scan-testable digital circuit inside a device to be tested, comprising: outputting means for outputting a delay time measuring signal as a digital signal; delay means for delaying a timing when a state of the delay time measuring signal is changed; at least two signal holding means, each receiving the delay time measuring signal, and holding the state of the delay time measuring signal at a holding-command input timing; and delay adjusting means for adjusting the delay time of the delay time measuring signal before the delay time measuring signal is delayed by the delay means in such a manner that the state of the delay time measuring signal in each of signal transmission paths is sequentially changed by the delay means within a given range having the holding-command input timing as a reference, wherein the digital signal delay measuring circuit is implemented in the device to be tested, and wherein the holding-command input timing is identical between the at least two signal holding means, and the timing when the state of the delay time measuring signal input to each of the signal holding means is changed is different depending on the delay means, and the delay time is obtained based on a difference in the state of the delay time measuring signal held by each of the signal holding means.