Patent ID: 7782141

Claim:
Circuitry for reducing power in a digital amplifying system, comprising: a first digital delay circuit for receiving and delaying a first incoming digital data signal which represents a first analog input signal; a first digital-to-analog conversion circuit for receiving the delayed first digital data signal from the first digital delay circuit and converting the delayed first data to a first analog signal; a first amplifier for amplifying the first analog signal to produce a first output voltage applied to a first load; a digital signal processing system for receiving the first incoming data signal, detecting first signal amplitude information contained in the first incoming digital data, and converting the first signal amplitude information to a first digital control signal to optimize power efficiency of the digital amplifying system; and power conversion circuitry for converting the first digital control signal to an adjustable maximum available supply current in a first supply conductor of the first amplifier circuitry of at least sufficient magnitude to avoid distortion during the amplifying of the first analog signal to produce the first output voltage, wherein the power conversion circuitry includes a charge pump for producing the adjustable maximum available supply current so as to maintain a first supply voltage on the first supply conductor, switching of the charge pump being controlled by a first clock signal.