Patent ID: 7573454

Claim:
A display driver that drives a plurality of data lines of an electro-optical panel, the electro-optical panel having a plurality of scanning lines and a plurality of pixels in addition to the data lines, the display driver comprising: a data input section, display data or setting data being input to the data input section; a latch circuit that fetches the display data or the setting data, each of the display data and the setting data having been input through the data input section; a display processing section having a data line driver section, the data line driver section driving the data lines by using the display data fetched in the latch circuit; a control register that is used for controlling the display processing section; buffer that fetches only the setting data fetched in the latch circuit based on an initial setting signal; a first delay circuit that delays an initialization signal for a first delay time; a second delay circuit that delays the initialization signal for a second delay time, the second delay time being longer than the first delay time; and a selector that selectively outputs an output from the first delay circuit or a clock signal, based on an output from the second delay circuit, the setting data fetched into the buffer being set in the control register after at least one of the display processing section and the control register has been initialized by the initialization signal, the display processing section being controlled based on the setting data set in the control register, the initial setting signal being the initialization signal, the latch circuit fetching the display data or the setting data input through the data input section based on an output from the selector, the display data being input to the data input section in synchronization with the clock signal, the data line driver section driving the data lines by using the display data fetched into the latch circuit based on the clock signal selectively output from the selector, the buffer holding the setting data based on the outputs from the first and second delay circuits, the setting data having been fetched into the latch circuit based on the output of the first delay circuit selectively output by the selector, and the setting data held by the buffer being set in the control register based on a horizontal synchronization signal specifying a horizontal scanning period or based on a vertical synchronization signal specifying a vertical scanning period.