Patent ID: 8566659

Claim:
A scan circuit comprising: A. a functional circuit formed on the semiconductor substrate of an integrated circuit, the functional circuit including logic circuits to be tested; B. scan path circuitry having plural scan paths, each scan path being formed of serially connected scan cells, each scan cell including a multiplexer having an enable input, a response data input, a scan data input, and an output, and a flip-flop having a data input connected to the output of the multiplexer, a clock input and an output providing stimulus data and scan data, each scan path having leads connected to the logic circuits to carry stimulus signals to the logic circuits and to receive response signals from the logic circuits, each scan path having a serial data input lead and a serial data output lead, each scan path being organized in at least first and second selectable and separate scan path parts, each scan path part having a serial input connected to the serial data input lead of that scan path, a serial output lead selectively coupled to the serial data output lead of that scan path, and a separate set of scan path part enable and clock input leads; C. test data generator circuitry having control inputs and a serial data output connected to the serial data input lead of each scan path; D. test data compactor circuitry having control inputs and a serial data input coupled to the serial data output lead of each scan path; E. controller circuitry having control outputs coupled with the control inputs of the test generator circuitry, control outputs coupled with the control inputs of the test data compactor, and enable and clock outputs for the scan paths; and F. adaptor circuitry having control inputs connected with the enable and clock outputs for the scan paths of the controller circuitry, the adaptor circuitry having a first set of scan path part enable and clock output leads connected with the separate set of scan path part enable and clock input leads of the first scan path parts and a second set of scan path part enable and clock output leads connected with the separate set of scan path part enable and clock input leads of the second scan path parts, the adaptor circuits including a state machine controlling the production of the separate sets of control signals for operating the respective separate scan path parts.