Patent ID: 8824196

Claim:
A static random access memory (SRAM) comprising: a column of SRAM memory cells having a global bit line to receive data from a SRAM memory cell of the column and a plurality of local cell groups, each local cell group having a copy bit line circuit, a local read bit line, and a local bit line to store data in a SRAM memory cell of the local cell group, the copy bit line circuit having an input coupled with the global bit line and an output coupled with the local bit line, the local read bit line coupled with the global bit line; wherein a value stored in any SRAM memory cell of a first local cell group is copied to any SRAM memory cell of a second local cell group in a single cycle of the SRAM via a local read bit line of the first local cell group, the global bit line, and a copy bit line circuit and a local bit line of the second local cell group.