Patent ID: 7126190

Claim:
A semiconductor structure, comprising: a semiconductor substrate; a well implanted in the substrate, the well having an opposite conductivity type with respect to the substrate; first and second dielectric spacers positioned on the substrate and defining opposite sides of an opening; a gate dielectric positioned on the substrate and in the opening; a gate electrode formed in the opening and on the gate dielectric, the gate electrode being limited by the dielectric spacers; first and second halos implanted in the well and under the first and second dielectric spacers, respectively, a channel being defined in the well by the halos; source and drain regions implanted in the substrate and adjacent to the first and second halos, respectively; a first contact coupled to a first one of the source and drain regions and positioned on a first portion of the gate electrode; a second contact coupled to a second one of the source and drain regions; and a dielectric layer positioned on a second portion of the gate electrode and being defined on opposite sides by the first and second contacts.