Patent ID: 7471128

Claim:
A delay signal generator generating a plurality of delay signals including a first delay signal used in recording data to a first-type disc media and a second delay signal used in recording data to a second-type disc media, the delay signal generator comprising: a delay circuit for delaying an input signal in a stepped manner and including a plurality of series-connected first delay elements, each controlling a delay amount in accordance with a control voltage; a delay amount control circuit, connected to the delay circuit, for generating the control voltage and supplying the plurality of first delay elements with the control voltage; and a selector, connected to the delay circuit, for selecting an output of one of the plurality of first delay elements and generating a delay signal with a predetermined delay amount; wherein the delay amount control circuit includes: a voltage controlled oscillator having a plurality of second delay elements connected in a ring-like manner, the second delay elements each having the same configuration as the first delay elements, and the quantity of the second delay elements being based on the quantity of the first delay elements; a first frequency divider, connected to the voltage controlled oscillator, for receiving a frequency dividing ratio setting signal generated depending on the type of the disc media and for dividing the frequency of an output signal of the voltage controlled oscillator by a first frequency dividing ratio according to the frequency dividing ratio setting signal to generate a first frequency-divided signal; a second frequency divider for receiving the frequency dividing ratio setting signal and a predetermined reference clock signal generated depending on the type of the disc media and for dividing the frequency of the predetermined reference clock signal by a second frequency dividing ratio according to the frequency dividing ratio setting signal to generate a second frequency-divided signal; a phase comparator, connected to the first and second frequency dividers, for comparing a phase of the first frequency-divided signal and a phase of the second frequency-divided signal to generate a comparison signal; and a filter circuit, connected to the phase comparator, for generating the control voltage in response to the comparison signal; wherein the delay amount control circuit changes the delay amount for one of the first delay elements included in the delay circuit by changing a frequency dividing ratio rate that is a ratio of the second frequency dividing ratio relative to the first frequency dividing ratio.