Patent ID: 7601983

Claim:
A transistor comprising: a semiconductor substrate having a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface and disposed at an angle with respect to the first and second surfaces; first heavily doped impurity regions formed under the second surface; a gate structure formed on the first surface; a heterogeneous epitaxial layer formed on the second surface and the third surface, wherein the epitaxial layer comprises a first crystalline structure growing from the third surface of the {111} crystal plane in a [111] direction, and a second crystalline structure growing from the second surface of the {100} crystal plane in a [100] direction; and second heavily doped impurity regions formed adjacent to both sides of the gate structure and within the heterogeneous epitaxial layer to form a source region and a drain region in combination with the first heavily doped impurity regions, wherein the second heavily doped impurity regions comprise side faces between the third surface of the semiconductor substrate and a central portion of the gate structure.