Patent ID: 8782446

Claim:
A cryptographic device comprising: a resistor, the first resistor having first and second terminals wherein the first terminal is directly connected to an accessible electrical node wherein the accessible electrical node provides power to the cryptographic device; an active shunt current regulator having first and second inputs wherein the first input is directly connected to the first terminal of the resistor and the second input is directly connected to the second terminal of the resistor; a low-pass filter having an input and an output wherein the input is directly connected to the second terminal of the first resistor; a linear voltage regulator having an input and an output wherein the input of the linear voltage regulator is directly connected to the output of the low-pass filter; an AES (advanced encryption standard) circuit having an input wherein the input is directly connected to the output of the linear voltage regulator; wherein current drawn from the accessible electrical node remains substantially constant; wherein a voltage on the input of the AES circuit remains substantially constant; wherein the linear voltage regulator comprises: a PFET (p-type field-effect transistor) having a gate, drain and source wherein the source is directly connected to the input of the linear voltage regulator and the drain is directly connected to the output of the linear voltage regulator; a capacitor having a first and a second terminal wherein the first terminal is directly connected to the output of the linear voltage regulator and the second terminal is directly connected to ground; a resistor having a first and a second terminal wherein the first terminal is connected to the output of the linear voltage regulator; a variable resistor having a first and a second terminal wherein the first terminal of the variable resistor is directly connected to the second terminal of the first resistor and the second terminal of the variable resistor is directly connected to ground; an operational amplifier having a first input, a second input and an output wherein the first input of the operational amplifier is directly connected to the second terminal of the resistor, wherein the second input of the operational amplifier is directly connected to a first voltage reference and wherein the output of the operational amplifier is directly connected to the gate of the PFET.