Patent ID: 7216216

Claim:
A processor configured to execute an instruction defined to change a current register window into a plurality of registers from a first register window to a second register window, to perform an operation on at least one source operand read from the first register window, and to store a result of the operation in the second register window, the processor comprising: a register file comprising the plurality of registers; a first execution unit coupled to the register file, wherein a first pipeline associated with the first execution unit has a first number of pipeline stages, wherein the first execution unit is configured to change the current register window from the first register window to the second register window in the register file in response to the instruction; and a second execution unit coupled to the register file, wherein a second pipeline associated with the second execution unit has a second number of pipeline stages, wherein the second execution unit is configured to perform the operation and write the result to the register file, wherein the second number exceeds the first number, whereby the second register window is established as the current register window in the register file prior to writing the result, and wherein the at least one source operand is read from the first register window prior to establishing the second register window as the current register window.