Patent ID: 8446903

Claim:
A system on chip (SoC) comprising: a plurality of cores; a protocol stack coupled to the plurality of cores, the protocol stack for a Peripheral Component Interconnect Express™ (PCIe™) communication protocol, the protocol stack including: a transaction layer and a link layer of the PCIe™ communication protocol; and a physical (PHY) unit coupled to the protocol stack to provide communication between the SoC and a device coupled to the SoC via a physical link, the PHY unit of a low power communication protocol different than a PHY unit of the PCIe™ communication protocol and including a physical unit circuit according to the low power communication protocol and a logical layer to interface the protocol stack to the physical unit circuit; a second PHY unit separate from the PHY unit to communicate via a sideband channel coupled between the SoC and the device separate from the physical link, the sideband channel comprising a serial link.