Patent ID: 8736063

Claim:
A semiconductor device comprising: a first wiring structure formed over a main surface of a substrate, the first wiring structure including first and second wiring patterns disposed with a first gap therebetween, first and second dummy patterns arranged in the first gap between the first and second wiring patterns and a first insulating layer covering the first and second wiring patterns and the first and second dummy patterns, the first and second dummy patterns being separated from each other; and a second wiring structure stacked with the first wiring structure in a vertical direction with respect to the main surface of the substrate, the second wiring structure including third and fourth wiring patterns disposed with a second gap therebetween, a third dummy pattern arranged in the second gap between the third and fourth wiring patterns and a second insulating layer covering the third and fourth wiring patterns and the third dummy pattern; the third dummy pattern of the second wiring structure being elongated in a horizontal direction with respect to the main surface of the substrate to overlap continuously both of the first and second dummy patterns of the first wiring structure.