Patent ID: 8401821

Claim:
A method of measuring a latency associated with a transaction between logic units, the transaction taking place over an on-chip interconnect, the method comprising: in response to a first transaction initiation event, the first transaction initiation event having an associated transaction identifier, adding a first time value to a first data queue, the first data queue being associated with the transaction identifier for the first transaction initiation event; in response to a second transaction initiation event, the second transaction initiation event having an associated transaction identifier, adding a second time value to a second data queue, the second data queue being associated with the transaction identifier for the second transaction initiation event; in response to a first transaction completion event, the first transaction completion event having an associated transaction identifier: outputting the first time value from the first data queue if the transaction identifier associated with the first transaction completion event corresponds to the transaction identifier associated with the first transaction initiation event, and outputting the second time value from the second data queue if the transaction identifier associated with the first transaction completion event corresponds to the second transaction identifier associated with the second transaction initiation event; and determining a first latency measurement using a time value corresponding to the first transaction completion event and the one of the first time value and the second time value that is output.