Patent ID: 7518419

Claim:
A power-on reset circuit comprising: a trigger circuit having: a first resistor connected to a node; a second resistor connected to the node, a first voltage being output at the node; a third resistor; and a transistor having a source, a gate connected to receive the first voltage, and a drain connected to the third resistor, a second voltage being output at the drain of the transistor; and a counter connected to the trigger circuit, the counter including: a first counting circuit having a first input connected to the trigger circuit, a second input connected to receive a first gated signal, and an output to generate a first count signal; a second counting circuit having a first input connected to the trigger circuit, a second input connected to receive a second gated signal, and an output to generate a second count signal; a first gate circuit having a first input to receive the first count signal, a second input to receive the second count signal, and a third input to receive a clock signal, and an output to generate the first gated signal; and a second gate circuit having a first input to receive the first count signal, a second input to receive the second count signal, and a third input to receive the clock signal, and an output to generate the second gated signal.