Patent ID: 8361811

Claim:
A method of manufacturing an electronic component, comprising: fabricating a capacitor on a substrate, the capacitor having a dielectric layer formed from a dielectric material comprising at least one of pyrochlore or perovskite, the dielectric layer being disposed between first and second electrodes; depositing a reactive barrier layer over the capacitor, the reactive barrier layer comprising an oxide having an element with more than one valence state; depositing a passivation layer over the reactive barrier layer, the passivation layer being deposited by a method that produces atomized hydrogen; providing a first metal interconnect comprising an upper portion formed over a lower portion, wherein the first metal interconnect is in contact with the first electrode of the capacitor, wherein the first metal interconnect passes through the reactive barrier layer and the passivation layer to enable a direct electrical contact for the first electrode of the capacitor; and providing a second metal interconnect comprising an upper portion formed over a lower portion, wherein the second metal interconnect is in contact with the second electrode of the capacitor, wherein the second metal interconnect passes through the reactive barrier layer and the passivation layer to enable a direct electrical contact for the second electrode of the capacitor, wherein the depositions of the reactive barrier and passivation layers comprise: depositing the reactive barrier layer and the passivation layer over a top surface of each of the lower portions of the first and second metal interconnects, and subsequently etching portions of the top surfaces of the lower portions of the first and second metal interconnects thereby enabling the upper portions of the first and second metal interconnects to be formed over the lower portions of the first and second metal interconnects, respectively, wherein the etching is performed such that the reactive barrier layer and the passivation layer cover outer portions of the top surfaces of the lower portions of the first and second metal interconnects.