Patent ID: 8799529

Claim:
An operating method of a direct memory access (DMA) controller including first and second DMA channels and a channel loop management memory device, comprising: (a) iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; (b) iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; (c) evaluating a whole channel loop number register indicating a number of remaining whole channel loops; (d) when the whole channel loop number register indicates one or more remaining whole channel loops, reconfiguring the transfer and loop information of the first and second DMA channels using data from the channel loop management memory device, updating the whole channel loop number register, and again performing the steps (a) through (d) based upon the reconfigured transfer and loop information of the first and second DMA channels; and performing step (d) only after both of steps (a) and (b) are ended.