Patent ID: 7711042

Claim:
A signal processing apparatus, comprising: a second-order Volterra filter configured to equalize an input signal, wherein, a quadratic section of said second-order Volterra filter configured to implement a quadratic term of said second-order Volterra filter includes a plurality of multiplication units configured to multiply a first input signal with a second input signal to produce a product signal, one of said plurality of multiplication units being configured to employ a signal not delayed from said first input signal, as said second input signal, a remaining one of said plurality of multiplication units being configured to employ a signal delayed a preset time from said first input signal, as said second input signal, the one of said plurality of multiplication units including, one or more delay units connected in series with one another and configured to delay a signal output from the one of said plurality of multiplication units, each by a unit time, a multiplier configured to multiply the signal output from the one of said plurality of multiplication units and a signal output from each of said one or more delay units, each with a preset coefficient, and an adder configured to sum outputs of said multiplier together, wherein a step gain parameter for updating each preset coefficient of a multiplier of the remaining one of said plurality of multiplication units is twice a step gain parameter for updating each preset coefficient of the multiplier of the one of said plurality of multiplication units.