Patent ID: 6894953

Claim:
A timing circuit for measuring time of arrival of an asynchronous event, said timing circuit comprising: a counter to provide a plurality of high-order binary bits; a latch connected to the counter to latch the plurality of high-order binary bits received from the counter; a register responsive to an event trigger signal that denotes an occurrence of an asynchronous event to provide a plurality of gray code bits; an event circuit connected to the latch, responsive to occurrence of the event trigger signal, and responsive to the plurality of gray code bits from the register to arbitrate results between the counter and the register to thereby compensate for a time of arrival error resulting from an occurrence of a capture of an event signal during a period of uncertainty; a gray code-to-binary converter, connected to the register, to convert the plurality of gray code bits to a plurality of low-order binary bits; and a cascade circuit connected to the gray code-to-binary converter and the latch to concatenate the plurality of high-order binary bits and low-order binary bits to form the time of arrival of the asynchronous event.