Patent ID: 7834396

Claim:
A lateral field effect transistor comprising a source region layer ( 4 ) and a drain region layer ( 5 ) laterally spaced in at least a portion of a single plane and of a first conductivity type, a channel layer ( 6 ) of the first-conductivity-type extending laterally and interconnecting the source region layer ( 4 ) and the drain region layer ( 5 ) for conducting a current between these layers in the on-state of the transistor, a gate electrode ( 7 ) arranged to control the properties of the channel layer ( 6 ) to be conducting or blocking by varying the potential applied to the gate electrode ( 7 ), and a second-conductivity-type base layer ( 8 ) arranged under the channel layer ( 6 ) at least partially overlapping the gate electrode ( 7 ) and laterally spaced from the drain region layer ( 5 ) in at least a portion of a single plane, said second-conductivity-type base layer ( 8 ) electrically-coupled to the source region layer ( 4 ), and a spacer layer ( 10 ) comprising semiconductor material adjacent to the channel layer ( 6 ) of separate composition and located between the channel layer ( 6 ) and gate electrode ( 7 ) at least in the vicinity of the gate electrode ( 7 ), said spacer layer ( 10 ) and date electrode ( 7 ) on the channel layer ( 6 ).