Patent ID: 7814251

Claim:
A data transfer control system comprising: a direct memory access (DMA) transfer apparatus sequentially reading, into a register, at least one transfer setting value for data transfer stored in a memory and to perform DMA transfer processing based on the read transfer setting value, the DMA transfer apparatus comprising: a unit receiving a No Operation (NOP) designation for designating no performance of DMA transfer as the transfer setting value; a unit generating, when the NOP designation has been performed with the transfer setting value read into the register, an NOP interrupt signal to end the DMA transfer processing without performing the DMA transfer; a unit decoding coded and compressed data and to transfer the decoded data to a transfer destination during the DMA transfer; and a central processing unit (CPU), wherein the CPU determines a transfer length of data to be transferred based on a threshold value, and sets the NOP designation to a predetermined address of the transfer setting value when the transfer length of data to be transferred is equal to or shorter than the threshold value; wherein the data transfer control system performs data decode and data transfer with the CPU using the DMA transfer apparatus; wherein the CPU is programmed to provide: a CPU data transfer unit performing transfer equivalent to a transfer function of the DMA transfer apparatus with processing by the CPU; an interrupt detection unit detecting the NOP interrupt signal from the DMA transfer apparatus; and a unit performing, when the NOP interrupt signal has been detected by the interrupt detection unit, data decode and data transfer with processing by the CPU based on the transfer setting value read into the register in the DMA transfer apparatus and, after that, restart the DMA transfer to the DMA transfer apparatus.