Patent ID: 7180766

Claim:
A semiconductor memory, comprising: a plurality of word lines; a plurality of normal memory cells each having a storage capacitor; a plurality of normal bit lines each connected to said respective normal memory cells; a reference memory cell having a reference capacitor to store prescribed data; and a reference bit line connected to said reference memory cell, wherein, when said word lines are selected, potential of said normal bit lines and said reference bit line changes according to charge on said storage capacitors and on said reference capacitor; the semiconductor memory further comprising a current mirror circuit, including a first transistor drain of which is connected to said reference bit line and a plurality of second transistors drains of which are respectively connected to said plurality of normal bit lines, and in which the gates of said first and second transistors are connected in common to said reference bit line; and a plurality of preamp circuits, provided for each of said normal bit lines, each of which amplifies the potential of said normal bit line based on the potential of said normal bit line and on the potential of said reference bit line.