Patent ID: 8735221

Claim:
A method of fabricating a stacked semiconductor package, the method comprising: providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature; providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature; and forming inter-package bonding units by bonding respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature, wherein in the forming of the inter-package bonding unit and performing annealing, the solder paste nodes are transformed into a material having a third melting temperature higher than the first melting temperature, and the inter-package bonding unit includes the transformed solder paste nodes and the first solders.