Patent ID: 8456992

Claim:
A port processor comprising: a register file comprising: a buffer length register; a low-power buffer threshold register; a timer expiration buffer threshold register; an aging timer register; an active buffer threshold register; a link utilization register; and a link utilization threshold register storing a link utilization threshold; an arithmetic/logical unit (ALU) configured to: update a buffer length stored by the buffer length register based on an amount of data stored for a port controlled by the port processor; compare the buffer length to the low-power buffer threshold; update a link utilization stored by the link utilization register based on a number of packets transmitted by the port over a link utilization time interval; compare the link utilization to the link utilization threshold; place the port into a low-power state based on the comparison of the buffer length to the low-power buffer threshold and the comparison of the link utilization to the link utilization threshold; and when the port is in the low-power state: remove the port from the low-power state based on either of the following conditions: comparing the buffer length to a timer expiration buffer threshold stored in the timer expiration buffer threshold register upon expiration of an aging timer stored by the aging timer register; and comparing the buffer length to an active buffer threshold stored in the active buffer threshold register.