Patent ID: 7924644

Claim:
A semiconductor memory device comprising a memory cell array including a plurality of memory cells, wherein each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state, wherein in write and read operations, a data “1” state corresponding to the steady state is written to and read from at least one selected memory cell of the memory cell array by flowing a first bipolar current through the at least one selected memory cell, and a data “0” state is written to and read from the at least one selected memory cell by flowing a second bipolar current which is smaller than the first bipolar current through the at least one selected memory cell, wherein in a refresh operation, memory cells of the memory cell array storing the data “0” state are refreshed, discharging the majority carriers from the floating body region of each of the memory cells storing the data “0” state to prevent accumulation of the majority carriers before the data “0” state changes to the data “1” state, and wherein the memory cells of the memory cell array storing the data “1” state are not affected by the refresh operation.