Patent ID: 7053632

Claim:
A circuit for predicting a dead time, comprising: a first integrator for performing a charging operation during a (N+1) th period (where N is a positive integer) of an externally provided reference signal; a second integrator for performing a charging operation during a N th period of the reference signal, and maintaining at a first voltage value during the (N+1) th period; a first comparator having input terminals coupled to the first integrator and the second integrator respectively, and generating a first comparison result signal when a charging voltage value of the first integrator exceeds the first voltage value; a third integrator for performing a charging operation during the N th period of the reference signal; a fourth integrator for performing a charging operation during a (N−1) th period of the reference signal, and maintaining at a second voltage value during the N th period of the reference signal; a second comparator having input terminals coupled to the third integrator and the fourth integrator respectively, and generating a second comparison result signal when a charging voltage value of the third integrator exceeds the second voltage value; and a logic circuit coupled to an output of the first comparator and an output of the second comparator for receiving the first comparison result signal and the second comparison result signal, and generating a reset signal based on a result of a logical operation on the first comparison result signal and the second comparison result signal, wherein, the charging operation is performed by the first integrator and the third integrator during the N th period and the (N−1) th period of the reference signal after delaying for a predetermined delay time.