Patent ID: 8117395

Claim:
A system on chip (SOC) comprising: a plurality of processing cores; a shared N-way cache configured to be accessed by one or more of the plurality of processing cores; and a command processing pipeline operatively coupled to the N-way cache and configured to process a sequence of cache commands, and wherein individual cache commands are either a hit or a miss, wherein a way of the N ways of the cache with which an address of a cache command matches is a hit way for the cache command in case the cache command is a hit, the command processing pipeline comprising: a first command processing stage configured to: receive a first cache command from one of the plurality of processing cores; select a way, from the N ways, as a potential eviction way, from which data is to be evicted in case the first cache command is a miss; and generate, based at least in part on the received first cache command, N selection signals corresponding to the N ways, wherein each selection signal is indicative of whether the corresponding way is: the hit way and/or the eviction way, or neither the hit way nor the eviction way.