Patent ID: 8223577

Claim:
A semiconductor memory circuit comprising: a first terminal which receives a first control signal; a second terminal which receives a second control signal; a third terminal; a power source terminal which receives a power source voltage; a first input circuit which is coupled to the first terminal and which outputs a first internal signal; a second input circuit which is coupled to the second terminal and the power source terminal and which outputs a second internal signal; a first processing circuit which includes a DRAM circuit and which outputs a first data signal in response to the first internal signal; a read circuit which outputs a second data signal in response to the first data signal; an output circuit which receives the second data signal and outputs an output signal to the third terminal; a first switch which is coupled to the power source terminal; a second switch which is coupled to the power source terminal and the read circuit; a power supply unit which is coupled to the first switch and the first processing circuit; wherein the first switch and the second switch is switched off when the second control signal is in a first level and the power supply unit stops supplying an internal voltage to the first processing circuit, and the second switch stops supplying the internal voltage to the read circuit, and wherein when the second control signal is in the first level (low level), the output circuit is an output high impedance state in accordance with the second internal signal.