Patent ID: 8203867

Claim:
An integrated circuit, comprising: an array of SRAM cells, said SRAM cells being arranged in rows and columns, each said SRAM cell further including: a pair of cross-coupled inverters, said cross-coupled inverters including a bit-side data node and a bit-bar-side data node; a bit-side passgate transistor, said bit-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, such that said gate node of said bit-side passgate transistor is connected to a word line, said first source/drain node of said bit-side passgate transistor is connected to said bit-side data node and said second source/drain node of said bit-side passgate transistor is coupled to a bit data line; a bit-bar-side passgate transistor, said bit-bar-side passgate transistor further including a gate node, a first source/drain node and a second source/drain node, such that said gate node of said bit-bar-side passgate transistor is connected to said word line, said first source/drain node of said bit-side passgate transistor is connected to said bit-bar-side data node and said second source/drain node of said bit-bar-side passgate transistor is connected to a bit-bar data line; and a read buffer, said read buffer including: a access transistor, said access transistor further including a gate node, a first source/drain node and a second source/drain node, such that said gate node of said access transistor is connected to said word line, and said first source/drain node of said access transistor is connected to a bit read line; and a read buffer driver transistor, said read buffer driver transistor further including a gate node, a drain node and a source node, such that said gate node of said read buffer driver transistor is connected to said bit-bar-side data node, and said drain node of said read buffer driver transistor is connected to said second source/drain node of said access transistor.