Patent ID: 7903490

Claim:
A semiconductor memory device comprising: a plurality of pairs of bit lines; a plurality of word lines; a plurality of static memory cells coupled to the plurality of pairs of bit lines and the plurality of word lines so that each of the static memory cells is coupled to a corresponding pair of bit lines of the plurality of pairs of bit lines and a corresponding word line of the plurality of word lines; a pair of first common lines; a writing amplifier coupled to the pair of first common lines; a plurality of pairs of first selection switches coupled between the plurality of pairs of bit lines and the pair of first common lines so that each of the plurality of pairs of first selection switches is respectively coupled to a corresponding pair of bit lines of the plurality of pairs of bit lines and the pair of first common lines; a plurality of pairs of second common lines; a plurality of pairs of second selection switches coupled between the plurality of pairs of bit lines and the plurality of pairs of second common lines so that each of the plurality of pairs of second selection switches is coupled between a corresponding pair of bit lines of the plurality of pairs of bit lines and a corresponding pair of second common lines of the plurality of pairs of second common lines; a plurality of sense amplifiers respectively coupled to the plurality of pairs of second common lines, and an output buffer circuit for selecting one of a plurality of output signals of the plurality of sense amplifiers, wherein the output buffer circuit includes a logic circuit for obtaining OR logic of signals output from the plurality of sense amplifiers via the plurality of pairs of second common lines.