Patent ID: 7420391

Claim:
A circuit arrangement comprising: a data input configured to apply a data signal; a set input configured to apply a set signal; an output configured to provide an output state, said output being coupled to the data input and to the set input such that the output state provided is set only when an input state of the data signal and the output state differ from one another and the set signal changes to a prescribed state; a buffer comprising a first latch register and a second, downstream latch register, said registers being coupled between a buffer data input and a buffer output, the first latch register being set when the set signal is in a first state, and the second latch register being set only when the set signal is in a second state and the input state differs from the output state; and a logic unit coupled to the buffer and configured to set the buffer such that the input state of the applied data signal is provided as an output state at the output.