Patent ID: 8253454

Claim:
A phase lock loop (PLL) comprising: a phase-interpolation controller for generating a phase-interpolation control signal from an input clock; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a phase interpolation by a first reference clock controlled by the phase-interpolation control signal and an oscillation condition controlled by the first control signal; a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer; and a variable delay module, coupled to the phase/frequency detector, for delaying the input clock by an amount controlled by a second control signal to generate the second reference clock.