Patent ID: 8050132

Claim:
A semiconductor device comprising a plurality of memory cell blocks that each contain a plurality of memory cells for storing a predetermined amount of data, wherein each of said memory cell blocks has four or more inputs and four or more outputs, and internally contains a read address decoder for said memory cells and a sense amplifier for amplifying a voltage for output operation to an exterior, each of said memory cell blocks being constructed to store truth table data in said memory cells so that a desired logic value is outputted in response to a specified address input, thereby operating as a logic circuit, wherein said memory cell has a read word line correspondingly to said read address decoder, and when a voltage is applied to the read word line, data that is held at that time is read from a read data line, and wherein said memory cell blocks are connected to each other such that the four or more outputs from one memory cell block are inputted to other four or more memory cell blocks through said sense amplifier.