Patent ID: 6930003

Claim:
A method of manufacturing a semiconductor device comprising a memory region in which non-volatile memory devices are arranged in a matrix form of a plurality of rows and a plurality of columns to form a memory cell array, the method of manufacturing a semiconductor device comprising the steps of: (a) forming a gate insulation layer above a semiconductor layer; (b) forming a first conductive layer above the gate insulation layer; (c) forming a stopper layer above the first conductive layer; (d) patterning the stopper layer and the first conductive layer, to form a stack of layers formed of that stopper layer and that first conductive layer; (e) forming a first insulation layer over the entire surface of the memory region; (f) forming a second conductive layer above the first insulation layer, then forming a first side-wall conductive layer on each of two opposed side surfaces of the first conductive layer, and on the semiconductor layer with the first insulation layer interposed, by anisotropic etching of the second conductive layer; (g) forming a third conductive layer over the entire surface of the memory region, then forming a second side-wall conductive layer on a side surface of the first conductive layer, and on the semiconductor layer with a second insulation layer interposed, by anisotropic etching of that third conductive layer; (h) forming first and second control gates by isotropic etching of the first and second side-wall conductive layers; (i) forming an impurity layer to be a source region or a drain region within the semiconductor layer; (j) forming a third insulation layer over the entire surface of the memory region then removing the third insulation layer so that at least part of the stopper layer is exposed; and (k) removing the stopper layer, then forming a fourth conductive layer and patterning the fourth conductive layer to form a word line.