Patent ID: 7356647

Claim:
A cache arrangement of a data processing system that includes an instruction processor, a system memory, and a maintenance processor, the cache arrangement comprising: a cache memory coupled to the instruction processor, wherein the cache memory stores information recently accessed by the instruction processor including information modified by the instruction processor; a mode register coupled to the maintenance processor, wherein the mode register stores a value from the maintenance processor; and a controller coupled to the maintenance processor, the cache memory, and the mode register, the controller configured to selectively write the information in the cache memory to the system memory and selectively invalidate information in the cache responsive to a command received from the maintenance processor, wherein all of the modified information is written responsive to the command, all of the information excluding the modified information bypasses invalidation responsive to the command if the mode register contains a first value, and all of the information is invalidated in the cache memory responsive to the command if the mode register contains a second value.