Patent ID: 8859356

Claim:
A method, comprising: forming a PMOS transistor and an NMOS transistor, each of said transistors comprising a gate electrode and at least one source/drain region formed in a semiconducting substrate; forming a first sidewall spacer adjacent each of said gate electrodes; forming a second sidewall spacer adjacent each of said first sidewall spacers, wherein forming said second sidewall spacer adjacent said first sidewall spacer comprises: forming a single second sidewall spacer adjacent said first sidewall spacer of said NMOS transistor; and forming a multi-part second sidewall spacer adjacent said first sidewall spacer of said PMOS transistor, said multi-part second sidewall spacer comprising an upper spacer and a lower spacer; forming a layer of material above and between said gate electrodes, said layer of material having an upper surface that is positioned higher than an upper surface of each of said gate electrodes; performing a first etching process on said layer of material to reduce a thickness thereof such that said upper surface of said layer of material is positioned at a desired level that is at least below said upper surface of each of said gate electrodes; after performing at least one first etching process, performing at least one second etching process to insure that a desired amount of said gate electrodes for said PMOS transistor and said NMOS transistor are exposed for a subsequent metal silicide formation process; and forming metal silicide regions on said gate electrode structures and on said at least one source/drain regions.