Patent ID: 7829936

Claim:
A method of making a memory cell comprising two split sub-lithographic charge storage nodes, comprising: providing a charge storage layer, a first poly layer, and a first mask layer on a semiconductor substrate; patterning the first mask layer; forming spacers adjacent side surfaces of the patterned first mask layer and on portions of the upper surface of the first poly layer; removing exposed portions of the first poly layer that are not covered with the patterned first mask layer and spacers, thereby forming first openings; forming a second mask layer at the first openings; removing the patterned first mask layer, thereby exposing portions of the patterned first poly layer; removing the exposed portions of the patterned first poly layer, thereby exposing portions of the charge storage layer and forming two sub-lithographic first poly gates; removing the exposed portions of the charge storage layer, thereby forming second openings; forming a third oxide layer on the spacers and second mask layer and in the second openings; removing portions of the third oxide layer on the spacers and second mask layer, thereby exposing upper portions of the spacers and second mask layer; removing the spacers and second mask layer, thereby exposing portions of the charge storage layer at the bottom of the first opening; removing at least a portion of exposed portions of the charge storage layer at the bottom of the first opening, thereby forming two split sub-lithographic charge storage nodes between the sub-lithographic first poly gates and the semiconductor substrate, and forming bit line openings; implanting portions of the semiconductor substrate through the bit line openings; forming fourth oxides in the bit line openings; and forming a third poly gate over the semiconductor substrate.