Patent ID: 8653520

Claim:
A semiconductor device comprising a first transistor; an insulating layer over the first transistor; and a second transistor over the insulating layer, wherein the first transistor comprises: a first channel formation region; a first gate insulating layer provided over the first channel formation region; a first gate electrode overlapping with the first channel formation region, over the first gate insulating layer; and a first source electrode electrically connected to the first channel formation region and a first drain electrode electrically connected to the first channel formation region, wherein the second transistor comprises: a second channel formation region including an oxide semiconductor; a second source electrode electrically connected to the second channel formation region and a second drain electrode electrically connected to the second channel formation region; a second gate electrode overlapping with the second channel formation region; and a second gate insulating layer provided between the second channel formation region and the second gate electrode, wherein the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, wherein the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm, and wherein a top surface of the first gate electrode is aligned with the surface of the insulating layer.