Patent ID: 7936020

Claim:
An electrostatic discharge (ESD) protection structure situated in an integrated circuit for providing the integrated circuit with damage protection against over-voltage between a pair of first and second terminals of the integrated circuit, a semiconductor body of the integrated circuit having a substrate region of a first conductivity type, the ESD protection structure comprising: a first semiconductor region of a second conductivity type connected to the first terminal, the second conductivity type being opposite to the first conductivity type; a second semiconductor region of the first conductivity type connected to the first terminal and continuous with the first semiconductor region; an electrically floating third semiconductor region of the second conductivity type continuous with the second semiconductor region and separated from the first semiconductor region by the second semiconductor region; a fourth semiconductor region of the first conductivity type connected to the second terminal, continuous with the third semiconductor region, spaced apart from the first semiconductor region, and separated from the second semiconductor region by the third semiconductor region, the second and fourth semiconductor regions being separated from the substrate region by the third semiconductor region; and a fifth semiconductor region of the second conductivity type connected to the second terminal, continuous with the fourth semiconductor region, spaced apart from the first and second semiconductor regions, and separated from the third semiconductor region by the fourth semiconductor region, the ESD protection structure being operative substantially only in response to appearance of a voltage of magnitude greater than a trigger value between the terminals for causing current produced by the voltage to automatically flow through the ESD protection structure so as to dissipate electrical energy associated with the voltage and thereby provide the integrated circuit with protection against being damaged by the voltage.