Patent ID: 7146591

Claim:
A method of selecting cells in an integrated circuit design suitable for use in logic restructuring of an original design, wherein the original design includes a parameter set, the method comprising: (a) forming a restructuring set having restructuring cells, wherein the restructuring set includes at least an initial cell; (b) forming a candidate set adapted to include candidate cells, where each candidate cell is connected to at least one of the restructuring cells; (c) if the number of restructuring cells is equal to or greater than a pre-selected limit number of restructuring cells, proceeding to (j), else proceeding to (d); (d) if the number of candidate cells is equal to zero, proceeding to (j), else proceeding to (e); (e) removing a selected candidate cell from the candidate set; (f) for each restructuring cell connected to the selected removed candidate cell, determining a corresponding cell pair parameter; (g) if the cell pair parameter is included in the parameter set proceeding to (h), else proceeding to (d); (h) placing the removed candidate cell into the restructuring set; (i) placing all cells connected to the removed candidate cell into the candidate set and proceeding to (c); and (j) returning a complete restructuring set.