Patent ID: 7342285

Claim:
A method of fabricating semiconductor devices, comprising: providing a substrate having at least a transistor area, at least a capacitor area and at least a resistor area, wherein each of the capacitor area and the resistor area has an isolation structure therein; forming a gate structure on the substrate in the transistor area, forming a first electrode in the capacitor area, and forming a second electrode in the resistor area; forming first spacers on the sidewalls of the gate structure, the first electrode and the second electrode; forming a source/drain region in the substrate on the sides of the gate structure; sequentially and conformably forming a dielectric layer and a first conductive material layer over the substrate; performing a first patterning process to define the first conductive material layer and simultaneously forming a third electrode on the dielectric layer in the capacitor area and forming a conductive layer on the dielectric layer in the resistor area; forming second spacers on the sidewalls of the third electrode and the conductive layer; removing the dielectric layer uncovered by the third electrode, the conductive layer and the second spacers; and performing a self-aligned silicide process to form a salicide layer on the surface of the gate structure, the source/drain regions, the first electrodes, the third electrodes, the conductive layer and the second electrode.