Patent ID: 8489804

Claim:
A system comprising: a selection module configured to select a plurality of memory blocks of a flash memory in response to (i) the plurality of memory blocks being partially written with first data and (ii) receiving a write command to write second data to the plurality of memory blocks; a control module configured to, prior to erasing the first data from the plurality of memory blocks in order to write the second data in the plurality of memory blocks, (i) collect the first data from the plurality of memory blocks, (ii) merge the first data collected from the plurality of memory blocks, and (iii) write the merged first data in a portion of a dynamic random access memory instead of writing the merged first data in the flash memory; an erasing module configured to erase the first data from the plurality of memory blocks subsequent to collecting the first data from the plurality of memory blocks; a read/write module configured to write the second data to the plurality of memory blocks based on the write command subsequent to erasing the first data from the plurality of memory blocks; and a location description module configured to generate a description table indicating whether data in memory locations in the flash memory and the portion of the dynamic random access memory is valid or invalid, wherein data initially written to a first memory location corresponding to a logical address is indicated as valid, and in response to new data being written to a second memory location corresponding to the same logical address, the data in the first memory location is indicated as invalid, and wherein in response to the control module writing additional data to the portion of the dynamic random access memory, a rate of adding data to the portion corresponds to a rate at which data in memory locations in the portion becomes invalid.