Patent ID: 7365576

Claim:
A binary memory latch, comprising: a circuit having a first and a second input and an output implementing a logical structure which is completely determined by a combination of a first and a second binary logic function, each binary logic function being determined by a truth table, wherein each binary logic function in the combination having a first input and a second input and an output of which a state is completely determined by a state of the first input and a state of the second input; the output of the first logic function is connected to the second input of the second logic function and the output of the second logic function is connected to the second input of the first logic function; and at least one of the first and the second binary logic function is determined by a truth table selected from the group consisting of: a first truth table wherein X represents a state of the first input, Y represents a state of the second input and OUT represents a state of the output of a binary logic function as provided by the following table: X Y OUT 0 0 0 0 1 0 1 0 1 1 1 0; a second truth table wherein X represents a state of the first input, Y represents a state of the second input and OUT represents a state of the output of a binary logic function as provided by the following table: X Y OUT 0 0 1 0 1 0 1 0 1 1 1 1; a third truth table wherein X represents a state of the first input, Y represents a state of the second input and OUT represents a state of the output of a binary logic function as provided by the following table: X Y OUT 0 0 1 0 1 1 1 0 0 1 1 1; and a fourth truth table wherein X represents a state of the first input, Y represents a state of the second input and OUT represents a state of the output of a binary logic function as provided by the following table: X Y OUT 0 0 0 0 1 1 1 0 0 1 1 ;0 and wherein the first input of the circuit is the first input of the first logic function; the second input of the circuit is the first input of the second logic function; and the output of the circuit is enabled to provide a binary signal, the output of the circuit being equivalent to either the output of the first logic function or the output of the second function.