Patent ID: 7049642

Claim:
A semiconductor device having a plurality of area sections defined therein, which device comprises: a semiconductor substrate; a basic multi-layered wiring arrangement provided on said semiconductor substrate, both the semiconductor substrate and the basic multi-layered wiring arrangement having an internal electronic circuit area section and an input/output (I/O) area section defined in each of said area sections, a plurality of internal electronic circuits being produced in said internal electronic circuit area section, and an input/output (I/O) buffer being produced in said I/O area section, said I/O buffer being suitably and electrically connected to said internal electronic circuits in said basic multi-layered wiring arrangement; and an external multi-layered wiring arrangement provided on said basic multi-layered wiring arrangement and having a power supply electrode pad, a ground electrode pad, at least one signal electrode pad formed and arranged on a top surface thereof, and a wiring-layout produced therein to establish electrical connections between said I/O buffer and said electrode pads, wherein said wiring-layout includes a plurality of power supply conductive paths for establishing the electrical connection between said I/O buffer and said power supply electrode pad, a plurality of ground conductive paths for establishing the electrical connection between said I/O buffer and said ground electrode pad, and a signal conductive path for establishing the electrical connection between said I/O buffer and said signal electrode pad, and all the conductive paths feature a same width as each other.