Patent ID: 8878769

Claim:
An electrophoretic display apparatus comprising: a display unit including: (i) a first substrate, (ii) a second substrate which faces the first substrate with a predetermined interval, (iii) at least one partition wall configured to form at least one boundary of at least one pixel space, the pixel space being surrounded by the partition wall, the first substrate and the second substrate, (iv) at least one first electrode formed on the first substrate in the pixel space, (v) a second electrode formed on the second substrate in the pixel space, (vi) positively-charged particles contained in the pixel space, (vii) negatively-charged particles contained in the pixel space, (viii) a thin film transistor including a source electrode, a gate electrode and a drain electrode, the source electrode being connected to the first electrode, (ix) a scanning line configured to supply, to the gate electrode, a scanning signal voltage for selectively turning the thin film transistor to an ON state, and (x) a signal line connected to the drain electrode to input a data signal voltage so as to cause the positively-charged particles and the negatively-charged particles to migrate; a scanning signal voltage application circuit configured to apply the scanning signal voltage to the scanning line; a data signal voltage application circuit configured to apply the data signal voltage to the signal line; and a common voltage application circuit configured to apply a common voltage to the second electrode, wherein the data signal voltage includes: (i) a pre-write signal voltage which alternately repeats a positive voltage with respect to the common voltage and a negative voltage with respect to the common voltage, (ii) a write signal voltage to display an image on the display unit, (iii) a post-write signal voltage which gradually decreases from the write signal voltage to a hold signal voltage, the hold signal voltage maintaining a display state of the display unit, and (iv) the hold signal voltage, wherein the data signal voltage application circuit applies the pre-write signal voltage during a prepulse operation period, applies the write signal voltage during a write operation period, applies the post-write signal voltage during a write end operation period, and applies the hold signal voltage during a hold operation period, and wherein the scanning signal voltage application circuit sequentially switches the scanning signal voltage to the scanning line from a gate off level voltage to a gate on level voltage for one horizontal period during the write operation period and the write-end operation period, and applies the gate off level scanning signal voltage for turning off the thin film transistor to the scanning line during a period between (i) a transition of the data signal voltage to the hold signal voltage, and (ii) a next transition of the data signal voltage to the pre-write signal voltage, the gate off level scanning signal voltage being lower in potential than the hold signal voltage.