Patent ID: 8872149

Claim:
A memory cell formed in a semiconductor device, the memory cell comprising: a first electrode formed in an opening in a first dielectric layer, the first dielectric layer being formed on a substrate including a metal layer, the opening being configured to allow physical contact between the first electrode and the metal layer, the first electrode having a first width W 1 and extending a distance beyond a region defined by the opening; a resistive layer formed on the first electrode and having substantially the first width W 1 ; a capping layer, having a second width W 2 less than the first width W 1 , formed on the resistive layer; a second electrode formed on the capping layer and having substantially the second width W 2 ; a first composite spacer region having at least two different dielectric layers formed on the resistive layer between the first width W 1 and the second width W 2 ; and a via coupled to the second electrode.