Patent ID: 8524568

Claim:
A method of manufacturing a semiconductor device comprising steps of: (a) forming a first interlayer insulating film over a semiconductor substrate; (b) forming a first capacitor recess and a wiring trench through the first interlayer insulating film; (c) embedding a lower electrode and a first wiring in the first capacitor recess and the wiring trench, respectively; (d) covering upper surfaces of the first interlayer insulating film, the lower electrode and the first wiring with a first etching stopper film; (e) forming a via layer insulating film over the first etching stopper film, the via layer insulating film being made of insulating material having an etching resistance different from an etching resistance of the first etching stopper film; (f) forming a first via hole through the via layer insulating film and the first etching stopper film to expose a portion of the first wiring; (g) embedding a first conductive plug in the first via hole; (h) after embedding a first conductive plug, forming a second capacitor recess in the via layer insulating film to expose a portion of the first etching stopper film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan; (i) forming a conductive film covering an inner surface of the second capacitor recess, an upper surface of the first conductive plug and an upper surface of the via layer insulating film; and (j) patterning the conductive film to leave an upper electrode in the second capacitor recess and a second wiring connected to the first conductive plug.