Patent ID: 8049703

Claim:
A flat display structure, comprising: a substrate; a plurality of gate lines G i , where i=1 to n, and a plurality of data lines disposed on the substrate, wherein the gate lines and data lines together form a pixel matrix having a plurality of pixel rows R i where i=1 to n; a plurality of voltage adapting devices D i , where i=1 to n, disposed on the substrate, wherein the i-th voltage adapting device D i comprises: an input terminal electrically connected to a first end of the i-th gate line G i corresponding to the i-th pixel row R i ; a first control terminal; and an output terminal adapted to receive a working voltage; and a driving circuit electrically connected to the gate lines, wherein the driving circuit comprises: a plurality of shift registers, respectively coupled to second ends of the gate lines, to provide a plurality of gate signals to the second ends of the gate lines; and a timing controller electrically connected to the first control terminals, to provide a plurality of first control signals to the first control terminals, wherein the first control signal applied to the j-th voltage adapting device D j and the first control signal applied to the (j+1)-th voltage adapting device D j+1 are in opposite phase, and each of the first control signals is at a frequency which is larger than frequency of the gate signals.