Patent ID: 8553467

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of memory strings arranged therein, each of the memory strings including memory cells connected in series, each of the memory cells comprising a charge storage film formed on a channel region via a gate insulating film, and a control gate formed on the charge storage film via an insulating film; and a control circuit configured to enable execution of a pre-erase stress application operation prior to an erase operation on the memory cells, the pre-erase stress application operation applies a first voltage within a certain voltage range to the control gate, while applying a second voltage having a value smaller than a value of the first voltage to the channel region, wherein the control circuit is configured to execute a first operation and a second operation as the pre-erase stress application operation is executed, the first operation applies the first voltage to even-numbered memory cells in the memory string, while applying a third voltage having a value smaller than a value of the first voltage to odd-numbered memory cells in the memory string, and the second operation applies the first voltage to the odd-numbered memory cells in the memory cell string, while applying the third voltage to the even-numbered memory cells in the memory cell string.