Patent ID: 7663135

Claim:
A memory cell on an integrated circuit substrate, comprising: a fill layer on the integrated circuit substrate, the fill layer having a top surface; a bottom electrode comprising a pillar-shaped element extending through the fill layer, and having a top contact surface with a maximum width; a bit line on the fill layer and over the top contact surface of the bottom electrode; a via through the bit line over the top contact surface of the bottom electrode, the via having an area at the top surface of the fill layer greater than the top contact surface of, and having greater maximum width than the maximum width of, the top contact surface of the bottom electrode, the via having an inside surface acting as a second electrode and being disposed so that the bottom electrode and the bit line are not in contact; and a memory element within the via having a first contact surface and a second contact surface, the memory element contacting the top contact surface of the bottom electrode at the first contact surface, and contacting at least part of the inside surface of the via at the second contact surface, wherein the memory element comprises memory material having at least two solid phases; and wherein the second contact surface faces laterally relative to the first contact surface.