Patent ID: 7989846

Claim:
A semiconductor device comprising: a first common source semiconductor layer configured to extend in a first direction; a second common source semiconductor layer configured to extend in the first direction; a first logic gate circuit composed of at least one three-dimensional P-type FET and a three-dimensional N-type FET; and a second logic gate circuit composed of at least one three-dimensional P-type FET and a three-dimensional N-type FET, wherein a source of the three-dimensional P-type FET in the first logic gate circuit and a source of the three-dimensional P-type FET in the second logic gate circuit are joined to the first common source semiconductor layer, a source of the three-dimensional N-type FET in the first logic gate circuit and a source of the three-dimensional N-type FET in the second logic gate circuit are joined to the second common source semiconductor layer, a drain of the three-dimensional P-type FET of the first logic gate circuit and a drain of the three-dimensional N-type FET of the first logic gate circuit are joined to each other, and a drain of the three-dimensional P-type FET of the second logic gate circuit and a drain of the three-dimensional N-type FET of the second logic gate circuit are joined to each other.