Patent ID: 8898612

Claim:
An electronic design automation (EDA) tool for inserting dummy tiles in a metal layer of an integrated circuit design, wherein the metal layer includes a plurality of interconnect lines, the EDA tool comprising: a memory that stores the integrated circuit design and includes a routing database including routing information of the plurality of interconnect lines; and a processor in communication with the memory, wherein the processor includes: means for identifying a first set of interconnect lines of the plurality of interconnect lines that are at different voltage levels, using the routing information; means for defining a blockage between first and second interconnect lines of the first set of interconnect lines, based on at least a length of the first and second interconnect lines being greater than a first predefined threshold and a spacing between the first and second interconnect lines being less than a second predefined threshold; means for inserting the dummy tiles between the plurality of interconnect lines excluding the first and second interconnect lines; means for removing the blockage between the first and second interconnect lines after the insertion of the dummy tiles is complete; and means for checking a density of the plurality of interconnect lines after the insertion of the dummy lines is complete.