Patent ID: 8193454

Claim:
A circuit substrate, having: a first conductive layer, comprising: at least one power/ground plane, having at least one plane edge and a plurality of grid lines, wherein each grid line has a width, the grid lines intersect each other to define a plurality of first grid holes, and the distance between the first grid hole that is closest to the plane edge and the plane edge is greater than 1.5 times the width, and a window; a second conductive layer, disposed under the first conductive layer and having a window, a plurality of second grid holes and a projection layout, wherein the projection layout is a region formed by projecting the layout of the first conductive layer onto the second conductive layer, the second grid holes are disposed outside the projection layout, and the window of the second conductive layer corresponds to the window of the first conductive layer; and a dielectric layer, disposed between the first conductive layer and the second conductive layer, and having a thickness, wherein the distance between the second grid hole of the second conductive layer that is closest to the projection layout and the projection layout is greater than the thickness of the dielectric layer.