Patent ID: 7149108

Claim:
A non-volatile RAM memory array comprising: a plurality of memory cells formed on a semiconductor substrate each cell capable of being selected through a select line and a data line, and having a single semiconductor device that controls access to the cell depending on a voltage of the select line; a memory element, the memory element including a complex metal oxide that changes its resistive state from a high resistive state to a low resistive state upon application of a first voltage pulse across the memory element; and changes its resistive state from the low resistive state to the high resistive state upon application of a second voltage pulse across the memory element, the second voltage pulse across the memory element being of opposite polarity to the first voltage pulse; maintains the resistive state even If power ceases to be supplied to the memory cell, wherein the resistive state of the memory cell determines the information stored in the memory cell; and at least one intermediary resistive state is used so that the memory cell is capable of storing more than one bit of information, whereby the memory element is placed in the various resistive states through voltage pulses of varying magnitude, polarity, an War duration.