Patent ID: 7509469

Claim:
A synchronizing circuit for resynchronizing output data of an asynchronous pipeline with a clock and in accordance to a predetermined latency, the circuit comprising: a latch enable signal generator responsive to the clock for sequentially generating and providing to a plurality of latches a plurality of latch input enable signals, each having an asynchronous delay in relation to the clock for enabling one of the plurality of latches to latch a corresponding portion of the output data, the plurality of latch input enable signals corresponding to respective control signals, and a plurality of latch output enable signals, each having a delay responsive to the predetermined latency for enabling a respective one of the plurality of latches to output the corresponding portion of the output data, the plurality of latch output enable signals corresponding to the respective control signals; and an output buffer for receiving the corresponding portions of the output data from the plurality of latches and resynchronizing each of the corresponding portions of the output data with the clock.