Patent ID: 7669170

Claim:
A method for developing a layout for fabricating a very large scale integrated circuit (IC) (VLSI) in a plurality of different layers in a given IC technology with a set of reduced ground rules for layout grids, wherein the size of an increment in a layout grid represents the smallest dimension that can be used by a designer in layout data for that given IC technology, comprising: using design rules for the given IC technology to establish a set of layer-specific layout grid increment values for at least some of the plurality of different layers; using a layout-optimization application to scale data and select the size of the layout grid increment value for at least some of the plurality of different layers of the VLSI layout; using a layout-optimization application to select minimum line widths and minimum line spaces for at least some of the plurality of different layers of the VLSI layout; using a shape-processing application to select via sizes, via locations, and via borders for at least some of the plurality of different layers of the VLSI layout.