Patent ID: 7453133

Claim:
An integrated circuit device comprising: a substrate formed of a first kind of semiconductor having a first energy bandgap; a gate dielectric on said substrate; a gate electrode on said gate dielectric; source and drain regions on the substrate and on opposite sides of the gate dielectric, the source and drain regions having at least a top portion formed of a second kind of semiconductor with a second energy bandgap, wherein the second energy bandgap is lower than the first energy bandgap; a metal on the top portion of at least one of the source and drain regions; a first dielectric layer comprising a source portion over said source region and a drain portion over said drain region on the metal, wherein said source portion and said drain portion of said first dielectric layer are interconnected through a portion of the first dielectric layer over said gate electrode; a second dielectric layer on the first dielectric layer, wherein in the second dielectric layer comprises a source portion over said source region and a drain portion over said drain region, and wherein said source portion and said drain portion of said second dielectric layer are interconnected through a portion of the second dielectric layer over said gate electrode, and wherein the first and the second dielectric layers compensate for stresses in said source and drain regions arising from a lattice mismatch between said top portion and said metal layer; an inter-level (ILD) over the second dielectric layer; and a conductive plug contacting the metal and disposed in said first and second dielectric layers.