Patent ID: 7594081

Claim:
A processor, comprising: at least one processor core; a system interface to cache coherent memory which directs memory access for ordinary load/store instructions executed by the at least one processor core to the cache coherent memory; and a low latency memory interface to a non-cache memory which directs memory access for non-ordinary load/store instructions executed by the at least one processor core to the non-cache memory, the low latency memory interface directly coupled to the at least one processor core over a dedicated bus, thereby bypassing the cache coherent memory, wherein the non-ordinary load/store instructions include an instruction type field, the instruction type field is related to moving data between the non-cache memory and a main register file, the instruction type field having a first instruction type for moving data between the non-cache memory and at least one holding register and a second instruction type for moving the data between the at least one holding register and the main register file; wherein the non-cache memory is accessed by the low latency memory interface via a two instruction sequence, the two instruction sequence comprising the first and second instruction types.