Patent ID: 7917826

Claim:
An error correction device, for connecting to a system bus managed by an arbitrator, comprising: a main memory, for storing data; a memory bus, coupled to the main memory; and a correction module, coupled to the system bus and directly connected to the memory bus, for reading an error data from the main memory, generating a correct data according to the error data, and writing the correct data into the main memory to update the error data; wherein the correction module directly accesses the main memory through the memory bus, and the correction module comprises: a data buffer, for temporarily storing at least an error value and at least an error address corresponding to the error value; and an error correction unit, coupled to the data buffer, for reading the error data according to the error address stored in the data buffer, generating the correct data according to the error data and the error value stored in the data buffer, and writing the correct data into the main memory according to the error address stored in the data buffer.