Patent ID: 7871927

Claim:
A method of forming an electrically-conductive via in a processed wafer, the method comprising: forming a first trench into a backside of the processed wafer; forming a second trench having a cross-sectional area into an end surface of the first trench; forming a via extending from an end surface of the second trench into the backside of the processed wafer to a first predetermined depth, wherein the via has a cross-sectional area that is smaller than the cross-sectional area of the second trench; depositing a seed layer over a full length of the via between the first predetermined depth and the end surface of the second trench; plating the seed layer to fill the via with an electrically-conductive material; thinning the backside of the processed wafer at least after said forming a second trench; and depositing a conductor within the second trench after said thinning the backside of the processed wafer.