Patent ID: 7145193

Claim:
A semiconductor integrated circuit device including, on a semiconductor substrate, a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with said memory cell selecting transistor, the semiconductor integrated circuit device comprising: a bit line and a first line formed in the same wiring layer over said semiconductor substrate; said information storage capacitive element provided over said bit line not through other wiring layers; and a second line provided over said information storage capacitive element, wherein in the region other than the region where said memory cell is formed, there are provided a first plug connected in direct contact with said first line, and a second plug connected in direct contact with said first plug and said second line between said first line and said second line, wherein said first line and said second line are electrically connected, wherein a contact portion between said first plug and said second plug is higher than a lower end portion of said information storage capacitive element, and wherein said contact portion between said first plug and aid second plug is lower than a higher end portion of said information storage capacitive element.