Patent ID: 6861304

Claim:
A method of manufacturing a semiconductor integrated circuit device having a plurality of insulated gate type semiconductor elements comprising the steps of forming a gate insulating film on the surface of a first semiconductor region of a first conductivity type, depositing a first Si—Ge mixed crystal gate electrode layer having a first composition and a second Si—Ge mixed crystal gate electrode layer having a second composition different from said first composition on different surfaces of said gate insulating film, forming a first and a second gate electrodes by respectively patterning said first and second gate electrode layers, and forming a plurality of semiconductor regions of a second conductivity type by introducing the second conductivity type determining impurities into said first semiconductor region not covered by said first and second gate electrodes, wherein Si layers thinner than said first and second Si—Ge mixed crystal gate electrode layers and substantially not containing Ge are respectively interposed between said first and second Si—Ge mixed crystal gate electrode layers and said gate insulating film, and wherein thicknesses of the Si layers are {fraction (1/10)}th or less than thicknesses of the first and second Si—Ge mixed crystal gate electrode layers.