Patent ID: 7640124

Claim:
A delay failure test circuit with which a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed, wherein the delay failure test circuit is configured to input, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data, wherein the delay failure test circuit is configured to generate only a launch edge and a capture edge from each operation clock of the clock domains, and to align, when an operation clock rate of the first clock domain is lower than that of the second clock domain, launch edges generated, the launch edge in the clock signal input to the first clock domain is a launch edge acquired from the operation clock of the first clock domain, and the capture edge in the clock signal input to the second clock domain is a capture edge acquired from the operation clock of the second clock domain.