Patent ID: 7633831

Claim:
A semiconductor memory, comprising: a memory core having memory cells, and a word line and a bit line connected to the memory cells; an enable terminal which receives a chip enable signal allowing access to said memory core; a command terminal which receives an access command for carrying out an access operation to said memory core; an address terminal which receives an address at once in accordance with said access command, the address being indicative of a memory cell to access; and an operation control circuit which, during activation of said chip enable signal, carries out a first access operation upon receipt of a first access command, and carries out a second access operation upon receipt of a next access command, a second access operation time being shorter than a first access operation time, wherein the operation control circuit includes: a first latency counter which, upon receipt of said first access command, counts a number of clocks corresponding to a first latency to generate a data control signal for controlling input or output of data to or from said memory core; and a second latency counter which, upon receipt of said next access command, counts a number of clocks corresponding to a second latency, which is less than the first latency, to generate the data control signal.