Patent ID: 7659569

Claim:
A memory device, comprising: a plurality of memory cells, each memory cell comprised of a stack formed over a substrate, the stack having a gate oxide layer and an overlying layer that acts as a tunneling barrier, the stack having at least one undercut region formed under the overlying layer and is adjacent to the gate oxide layer; and at least one charge storage element formed in the at least one undercut region, the overlying layer comprising at least one of a P+ polycrystalline silicon or a P-type metal that minimizes a number of electrons tunneling from the overlying layer to the at least one charge storage element, which is in at least one memory cell of the plurality of memory cells, during a Fowler-Nordheim (FN) erase operation to erase the at least one charge storage element, wherein each of the at least one charge storage element consists of a tunnel oxide layer formed over the substrate in the undercut region, a silicon rich nitride layer formed over the tunnel oxide layer and a layer of polysilicon.