Patent ID: 8908421

Claim:
A method, comprising: providing a first single port SRAM array on an integrated circuit, the first single port SRAM array comprising a plurality of first size bit cells each comprising: a cross coupled inverter pair for storing data on a storage node and a complementary storage node each inverter comprising a single fin finFET pull up and a single fin finFET pull down device; and a pair of pass gates each coupled between a bit line and a complementary bit line and a respective one of the storage node and the complementary storage node, each of the pass gates comprising a single fin finFET device having a gate coupled to a word line; outputting a first cell positive voltage supply CVdd to the first size bit cells from a first voltage control circuit; providing a second single port SRAM array on the integrated circuit, the second single port SRAM array comprising a plurality of second size bit cells each comprising: a cross coupled inverter pair for storing data on a storage node and a complementary storage node, each inverter comprising a single fin finFET pull up and a multiple fin finFET pull down device; and a pair of pass gates each coupled between a bit line and a complementary bit line and a respective one of the storage node and the complementary storage node, each of the pass gates comprising a multiple fin finFET device having a gate coupled to a word line; outputting a second cell positive voltage supply CVdd to the second size bit cells from a second voltage control circuit; coupling the first voltage control circuit and the second voltage control circuit to a peripheral voltage Vdd; and operating the first voltage control circuit to vary the first cell positive voltage supply CVdd during selected operations.