Patent ID: 7145195

Claim:
A semiconductor memory device with a capacitor on a bit line (COB) cell structure, comprising: a semiconductor substrate including an isolation region that defines an active area with a plurality of source/drain regions; a contact pad layer formed on the semiconductor substrate, said contact pad layer including gate line structures, first contact pads connected to parts of the source/drain regions, second contact pads connected to the other source/drain regions, and a first interlevel dielectric layer formed to cover the gate line structures and formed to laterally surround the first and second contact pads; a bit line contact plug layer on the contact pad layer, said bit line contact plug layer including lower storage node contact plugs connected to the first contact pads, bit line contact plugs connected to the second contact pads, a protective layer pattern that covers at least a portion of the second contact pads to prevent the second contact pads from contacting the lower storage node contact plugs, and a second interlevel dielectric layer formed to laterally surround the lower storage node contact plugs, the bit line contact plugs, and the protective layer pattern; and a bit line layer formed on the bit line contact plug layer, said bit line layer including upper storage node contact plugs connected to the lower storage node contact plugs, bit line structures connected to the bit line contact plugs, and a third interlevel dielectric layer formed to laterally surround the upper storage node contact plugs and formed to laterally surround and cover the bit line structures.