Patent ID: 7821829

Claim:
A nonvolatile memory device comprising: a memory array having a plurality of memory cells arranged in rows and columns; a plurality of first data lines transmitting data read from said memory array; a sense amplifier amplifying said read data transmitted through said plurality of first data lines; a control signal line provided along a direction same as a direction of said plurality of first data lines, and transmitting a control signal controlling said sense amplifier; a first power supply line provided along a direction same as the direction of said plurality of first data lines, and supplying a first voltage used for an operation of said sense amplifier; and a second power supply line provided along a direction same as the direction of said plurality of first data lines, and supplying said first voltage used for an operation of a peripheral circuit, wherein said plurality of first data lines are formed at an interconnection layer having said first and second power supply lines formed thereat, and are provided between said first and second power supply lines, said control signal line adjacent to said plurality of first data lines is formed at an interconnection layer different from said interconnection layer having said first and second power supply lines formed thereat, and said first power supply line and said second power supply line are electrically coupled with each other through a contact hole such that said different interconnection layer is used to cover said plurality of first data lines.