Patent ID: 7649222

Claim:
A semiconductor device comprising: a first conductivity type first semiconductor layer, formed on the upper surface of a substrate, having a first impurity concentration; a first conductivity type second semiconductor layer, formed on said first semiconductor layer, having a second impurity concentration higher than said first impurity concentration; a first conductivity type third semiconductor layer, formed on said second semiconductor layer, having a third impurity concentration lower than said second impurity concentration; a second conductivity type fourth semiconductor layer formed on said third semiconductor layer; a first conductivity type fifth semiconductor layer formed on said fourth semiconductor layer; and an electrode formed in a trench, so provided as to reach said second semiconductor layer through at least said fifth semiconductor layer, said fourth semiconductor layer and said third semiconductor layer, in contact with an insulating film, wherein the upper surface of said second semiconductor layer is arranged upward beyond the lower end of said electrode, the semiconductor device further comprising plugs arranged so as not to overlap said electrode in plan view and connected with said fifth semiconductor layer, wherein the width of said plugs in a direction intersecting with the extensional direction of said plugs is smaller than the width of said electrode in the direction intersecting with the extensional direction of said plugs.