Patent ID: 7861133

Claim:
A digital demodulating apparatus comprising: a plurality of circuit elements constituting a tuner that performs channel select processing to a received signal that has been interleaved, and a demodulator that performs demodulation processing to the received signal from the tuner; a deinterleaving section that performs deinterleave processing to the interleaved received signal from the tuner; an error correcting section that corrects errors included in the received signal that has been deinterleaved by the deinterleaving section; and a circuit element controlling section that controls an operation of at least one of the plurality of circuit elements, the circuit element controlling section estimating the quantity of hypothetical errors to be generated in the received signal due to a control of an operation of a circuit element, the circuit element controlling section judging from the estimated quantity of hypothetical errors whether or not the error correcting section can correct errors to be included in the received signal due to the control of the operation of the circuit element, the circuit element controlling section controlling the operation of the circuit element so as to decrease the quantity of errors to be generated in the received signal due to the control of the operation of the circuit element, when the circuit element controlling section has decided that the error correcting section can not correct the errors to be included in the received signal.