Patent ID: 7396758

Claim:
A method for generating an interconnect structure comprising: first depositing a via level interlayer dielectric; second depositing a buried etch stop layer having a composition Si v N w C x O y H z , where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1 atop said via level interlayer dielectric by a solvent based approach, said solvent based approach comprises a solution including a polymeric material precursor, an antistriation agent and an organic solvent selected from a group consisting of: propylene glycol methyl ether acetate (PGMEA), propylene glycol methyl ether (PGME), toluene, xylenes, anisole, mesitylene, butyrolactone, cyclohexanone, hexanones, ethyl lactate, and heptanones; third depositing a line level interlayer dielectric atop said buried etch stop layer; and annealing said via level interlayer dielectric, said line level interlayer dielectric, said buried etch stop layer, or a combination of said line level interlayer dielectric, said via level interlayer dielectric and said buried etch stop layer by a process selected from the group consisting of: thermal curing, electron irradiation, ion irradiation, or irradiation with ultraviolet or visible light.