Patent ID: 7996738

Claim:
An integrated circuit, comprising: a scan chain comprising pairs of circuit units and select units connected in series from a first circuit unit/select unit pair to a last circuit unit/select unit pair, each circuit unit of the pairs of circuit unit/select unit pairs containing a scannable storage element; an input of the scan chain directly connected to an input of a circuit unit of the first circuit unit/select unit pair; an input of each circuit unit of each circuit unit/select unit pair of the circuit unit/select unit pairs connected to a first input of a corresponding select unit of the circuit unit/select unit pair by a respective bypass wire; an output of each circuit unit of each circuit unit/select unit pair of the circuit unit/select unit pairs directly connected to a second input of the corresponding select unit of the circuit unit/select unit pair; outputs of first to next to last select units of respective first to next to last select units of the circuit unit/select unit pairs directly connected to inputs of subsequent circuit units of the of the circuit unit/select unit pairs; an output of the scan chain directly connected to an output of a last circuit unit of the last circuit unit/select unit pair; each circuit unit of the first to last circuit unit/select units pairs contained within and powered by a respective power domain; and each select unit configured to select its first input when the power domain containing its corresponding is circuit unit is deactivated and to select its second input when the power domain containing its corresponding is circuit unit is activated.