Patent ID: 7466078

Claim:
A plasma display panel, comprising: an upper substrate; an upper dielectric layer arranged under the upper substrate; plurality of sustain electrode pairs embedded within the upper dielectric layer; a lower substrate facing the upper substrate; a lower dielectric layer arranged over the lower substrate; a plurality of address electrodes embedded within the lower dielectric layer and crossing the plurality of sustain electrode pairs, the plurality of address electrodes crossing the plurality of sustain electrode pairs within an image producing display area; a plurality of main barrier ribs arranged on an upper surface of the lower dielectric layer and defining a plurality of discharge cells, the plurality of main barrier ribs being arranged within the image producing display area; a plurality of dummy barrier ribs arranged within a non-image producing dummy area external to a periphery of the image producing display area, the dummy barrier ribs defining a plurality of dummy cells, an outermost portion of the dummy barrier ribs having a height higher than a height of the main barrier ribs; and a phosphor layer arranged within the discharge cells and arranged within at least some of the plurality of dummy cells.