Patent ID: 8883646

Claim:
A method for forming a pattern on a semiconductor substrate comprising: providing a semiconductor substrate that includes a patterned sacrificial layer, the patterned sacrificial layer overlying a layer stack, comprising: a target layer overlying the semiconductor substrate; a first transition layer overlying the target layer; an intermediary layer overlying the first transition layer; a second transition layer overlying the intermediary layer; and the patterned sacrificial layer overlying the second transition layer; forming a first self-assembled monolayer (SAM) over the patterned sacrificial layer to form a first SAM cap over an upper surface of the patterned sacrificial layer and to form first SAM sidewalls about sidewalls of the patterned sacrificial layer; removing the first SAM cap to expose the upper surface of the patterned sacrificial layer while leaving the first SAM sidewalls in place; after the first SAM cap has been removed, removing the patterned sacrificial layer such that the first SAM sidewalls form a first pattern arrangement; patterning the second transition layer and the intermediary layer using the first SAM sidewalls as an etch mask, thereby defining pillars comprising intermediary layer portions, second transition layer portions, and first SAM caps; removing the first SAM caps and second transition layer portions, and leaving intermediary portions overlying the first transition layer; forming a second self-assembled monolayer (SAM) over the intermediary portions after removing the first SAM caps to form a second SAM cap over an upper surface of the intermediary portions and to form second SAM sidewalls about sidewalls of the intermediary portions; removing the second cap to expose the upper surface of the intermediary portions while leaving the second SAM sidewalls in place and then removing the intermediary portions such that the second SAM sidewalls form a second pattern arrangement; and patterning the first transition layer and the target layer using the second SAM sidewalls as an etch mask, wherein the patterned target layer comprises the pattern or the semiconductor substrate.