Patent ID: 7656186

Claim:
A calibration circuit for adjusting impedances of a pull-up circuit and a pull-down circuit included in an output buffer, comprising: a first replica buffer having a circuit configuration substantially identical to that of one of the pull-up circuit and the pull-down circuit; a second replica buffer having a circuit configuration substantially identical to that of an alternate one of the pull-up circuit and the pull-down circuit; a counter circuit that changes first and second impedance codes each defining impedances of the first and second replica buffers; first and second latch circuits each holding the first and second impedance codes; a first end-determining circuit that activates the first latch circuit in response to an impedance of the first replica buffer reaching a predetermined level and activates the second latch circuit in response to an impedance of the second replica buffer reaching a predetermine level; and a second end-determining circuit that activates at least one of the first and second latch circuits in response to a lapse of a predetermined period since issuance of a calibration command, irrespective of whether the impedance of the first or second replica buffer reaches the predetermined level.