Patent ID: 8531244

Claim:
A high frequency signal processing device, comprising: an oscillator circuit which outputs a first oscillation signal of which the oscillation frequency is controlled according to an analog control signal and a first modulation code signal; a divider which divides the first oscillation signal; an analog loop control circuit which, when a first control signal is in an active state, compares the phase of an output from the divider and the phase of a reference oscillation signal, which is generated from a reference signal oscillator, whose frequency is fixed in advance, generates the analog control signal according to the result of comparison and holds the value of the analog control signal when the first control signal is brought to an inactive state; a digital calibration circuit, which is electrically coupled to the reference signal oscillator which, when a second control signal is in an active state, searches for the value of a first digital code signal in which a difference between the phase of the output of the divider and the phase of the reference oscillation signal becomes a minimum, while updating the value of the first digital code signal according to the result of comparison between the phase of the output of the divider and the phase of the reference oscillation signal; a first modulation control circuit which outputs a second digital code signal having the value of the first digital code signal searched by the digital calibration circuit, according to input transmission data during a normal operation; a switch circuit, which is electrically coupled to the digital calibration circuit and the first modulation control circuit, which sets the value of the first modulation code signal to a predetermined initial value, the value of the first digital code signal or the value of the second digital code signal; and a calibration controller which, during the normal operation, controls the switch circuit in such a manner that the value of the first modulation code signal is brought to the second digital code signal, and which, during a calibration operation, performs the setting of a division ratio of the divider, control of the switch circuit, and control of activation/inactivation of the first and second control signals to thereby cause the digital calibration circuit to search for the value of the second digital code signal used during the normal operation.