Patent ID: 8120970

Claim:
A buffering system for improved reliability of non-Flash two-terminal memory elements, comprising: a plurality of memory layers that are vertically stacked upon one another and divided into partitions, each memory layer is in direct contact with an adjacent memory layer; a plurality of re-writable non-volatile memory elements included in each memory layer, each memory element having exactly two-terminals and is configured to retain stored data in the absence of electrical power, and each memory element operative to store at least one-bit of data as a plurality of conductivity profiles; a logic layer fabricated on a silicon substrate and including circuitry electrically coupled with the plurality of re-writable non-volatile memory elements in the plurality of memory layers, the plurality of memory layers are integrally fabricated directly on top of and in direct contact with the silicon substrate; at least one write buffer configured to facilitate writing to a first subset of partitions during a write cycle; and a write override circuit included in the circuitry and including a comparator electrically coupled with the write buffer and a read-before-write buffer electrically coupled with sense amp circuitry and the comparator, wherein during a first phase of a write cycle the sense amp circuitry communicates read data from at least one memory element to be written to during the write cycle to the read-before-write buffer, and during a second phase of the write cycle the comparator compares the read data with write data stored in the write buffer and generates a data miscompare signal if the read data and the write data are different, the data miscompare signal operative to allow the write data to be written to the at least one memory element.