Patent ID: 8533437

Claim:
A microprocessor, comprising: a cache memory; an instruction set having first and second prefetch instructions, each configured to instruct the microprocessor to prefetch a cache line of data from a system memory into the cache memory; and a memory subsystem, configured to execute the first and second prefetch instructions, wherein for the first prefetch instruction the memory subsystem is configured to forego prefetching the cache line of data from the system memory into the cache memory in response to a predetermined set of conditions, wherein for the second prefetch instruction the memory subsystem is configured to complete prefetching the cache line of data from the system memory into the cache memory in response to the predetermined set of conditions; wherein for the first prefetch instruction the memory subsystem is configured to forego prefetching the cache line of data from the system memory into the cache memory in response to a second predetermined set of conditions, wherein for the second prefetch instruction the memory subsystem is configured to cause an exception in response to the second predetermined set of conditions.