Patent ID: 8638139

Claim:
An apparatus comprising: a phase locked loop circuit configured to generate an output signal having a frequency that is a fractional multiple of an input reference signal, the phase locked loop circuit comprising a frequency divider that is configured to generate a saw-tooth wave frequency ramp with an incrementing frequency during a rising period and a decrementing frequency during a resetting period according to a division value received by the frequency divider; and a division value generator coupled to the phase locked loop circuit and configured to generate the division values such that the division value increments during the rising period and decrements during the resetting period, wherein the rising period is longer than the resetting period wherein the division value generator is configured to generate incrementing division values according to a plurality of rising steps from a start value to an end value, followed by a plurality of falling steps from the end value to the start value, wherein the plurality of falling steps have a step size, and wherein the step size of at least a portion of the plurality of falling steps is varied.