Patent ID: 8862859

Claim:
A method for improved support of multiple page size (“MPS”) segments in a microprocessor, the method comprising: receiving a first virtual address associated with a page of an MPS segment that supports a plurality of actual page sizes; generating a plurality of possible index values using the first virtual address and the supported plurality of actual page sizes; determining whether one or more of the plurality of possible index values correlate to one or more actual translation lookaside buffer (TLB) entries; in response to determining that one or more of the plurality of possible index values correlate to one or more of the actual TLB entries: identifying one of the correlated actual TLB entries that includes a first actual page size matching one of the supported actual page sizes, and also includes a second virtual address matching the first virtual address; and retrieving a real address from the identified actual TLB entry; and in response to determining that none of the plurality of possible index values correlate to one or more of the actual TLB entries: retrieving, from a page table entry, a second actual page size of the page associated with the first virtual address; and generating a new TLB entry and including the second actual page size in the new TLB entry.