Patent ID: 7949866

Claim:
Apparatus for processing data, said apparatus comprising: a processor operable in a plurality modes and a plurality of domains, said plurality of domains comprising a secure domain or a non-secure domain, said plurality of modes including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; said processor is responsive to one or more exception conditions for triggering exception processing using an exception handler, said processor configured to select said exception handler from among a plurality of possible exception handlers in dependence upon an exception vector value associated with said exception condition and stored within an active exception vector table for said exception condition and in dependence upon whether said processor is operating in said secure domain or said non-secure domain; wherein said active exception vector table is one of a plurality of exception vector tables, and at least two of said one or more exception conditions have respective programmable configurations associated therewith that control triggering of either a non-secure exception handler operating in a non-secure mode or a secure exception handler operating in a secure mode with any change of domain also being triggered when required.