Patent ID: 7161387

Claim:
A semiconductor device comprising: level conversion circuitry for converting an internal signal having a first logic level corresponding to a first power supply voltage to a level-converted signal having the first logic level corresponding to a second power supply voltage, said level conversion circuitry including means for cutting off a path of passing a through current in a particular operation mode between a node supplying said second power supply voltage and a node supplying a third power supply voltage different in level from the first and second power supply voltages; and power supply circuitry for stopping a supply of said first power supply voltage while supplying said second power supply voltage in said particular operation mode, wherein said level conversion circuitry includes: a latch circuit, formed of first and second CMOS inverters receiving said second power supply voltage as operating power supply voltages and having their inputs and outputs cross-coupled, for outputting said level-converted signal; first and second insulated gate field effect transistors respectively connected between the respective output nodes of said first and second CMOS inverters and the node supplying said third voltage, and receiving, at their respective gates, a signal corresponding to said internal signal, and said first and second insulated gate field effect transistors receiving complementary signals at their respective gates; a first feedback transistor responsive to a signal outputted from the first CMOS inverter, for fixing a potential of a gate of said first insulated gate field effect transistor; and a second feedback transistor responsive to a signal outputted from the second CMOS inverter, for fixing a potential of a gate of said second insulated gate field effect transistor.