Patent ID: 7889205

Claim:
A system, comprising: one or more graphic processors; and memory coupled to the one or more graphic processors, comprising: a frame buffer; and texture buffer configured as a texture atlas; wherein the memory is configured to store program instructions executable by the one or more graphic processors to: render a first graphic image to the frame buffer; copy a portion of the first graphic image from the frame buffer to the texture atlas; render a second graphic image to the frame buffer; copy the second graphic image to the texture atlas, wherein the portion of the first graphic image and the second graphic image are independently addressable in the texture atlas; and merge the portion of the first graphic image and second graphic image from the texture atlas onto the frame buffer; wherein said rendering the first graphic image, said copying the portion of the first graphic image, said rendering the second graphic image, said copying the first graphic image and said merging are performed using the same frame buffer and without performing a context switch between the frame buffer and any other frame buffer.