Patent ID: 7457164

Claim:
A semiconductor storage device, comprising: a memory cell array in which a plurality of nonvolatile memory cells are arrayed; word lines connected to control input terminals of the plurality of memory cells; bit lines connected to input/output terminals of the plurality of memory cells; a word line select circuit for selecting the word lines; a bit line charging/discharging section for performing charge and discharge of the bit lines; a cell current-related value read circuit for, with respect to all or a specified number of memory cells out of the plurality of memory cells, performing discharge or charge of the bit lines by the bit line charging/discharging section to read cell current-related values related to cell currents flowing through the individual memory cells; a reference value generation section for, based on a distribution of the cell current-related values read by the cell-current related value read circuit, generating a reference value to determine information stored in the memory cells; a data decision circuit for comparing the values related to cell currents read by the cell-current related value read circuit and the reference value derived from the reference value generation section with each other; and an output section for, based on a result of the comparison by the data decision circuit, outputting information stored in each of the plurality of memory cells.