Patent ID: 8185896

Claim:
A method, in a data processing system, comprising: coupling a plurality of processors to one another to create a plurality of processor books, wherein a subset of processors of the plurality of processors is associated with each processor book of the plurality of processor books, wherein each processor in the plurality of processors comprises a set of first buses, a set of second buses, and a set of third buses, and wherein each processor in the subset of processors is coupled to each individual other processor in the subset of processors in its respective processor book by the set of first buses; coupling the plurality of processor books together to create a plurality of supernodes, wherein a subset of processor books of the plurality of processor books is associated with each supernode of the plurality of supernodes, wherein each bus in the set of second buses couples the processor to at least two processor books in the subset of processor books within its respective supernode, and wherein the set of second buses are different buses from the set of first buses; and coupling the plurality of supernodes together, wherein data is transmitted from one processor to another processor based on an addressing scheme specifying at least a supernode and a processor book associated with a target processor to which the data is to be transmitted, wherein each bus in the set of third buses couples the processor to at least four other supernodes within the data processing system, wherein the set of third buses are different buses from the set of second buses and the set of first buses, wherein each processor of the plurality of processors has an integrated switch, and wherein the integrated switch in the processor implements the addressing scheme to route data from that processor to at least one other processor in the plurality of processors.