Patent ID: 8432002

Claim:
A method of forming a semiconductor structure comprising: providing a structure including a semiconductor substrate having at least one device region located therein, a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region, and an isolation region in contact with a sidewall surface of said doped semiconductor layer, wherein an uppermost surface of said doped semiconductor layer is coplanar with an uppermost surface of said isolation region; forming a sacrificial gate region having a spacer located on sidewalls thereof on an upper surface of the doped semiconductor layer; forming a planarizing dielectric material atop the doped semiconductor layer and adjoining the sacrificial gate region including the spacer; removing the sacrificial gate region to form an opening that exposes a portion of the doped semiconductor layer; extending the opening through a portion of the doped semiconductor layer to an upper surface of the semiconductor substrate; performing an anneal that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region and a drain region in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer; and forming a high k gate dielectric and a metal gate into the extended opening.