Patent ID: 8000430

Claim:
A delay locked loop for synchronizing an internal clock signal with an external clock signal, the delay locked loop comprising: a digital delay line circuit including a counter and a lock detector; an analog delay line circuit; a phase detector to detect a phase difference between the external clock signal and the internal clock signal; the counter being set to an initial value corresponding to an initial delay; a first detection circuit providing a first condition signal in response to first criteria being met, the first criteria based on first relative edge occurrences with respect to the internal and external clock signals; a second detection circuit providing a second condition signal in response to second criteria being met, the second criteria based on second relative edge occurrences with respect to the internal and external clock signals; the lock detector allowing the digital delay line circuit to increase delay by adding delay elements as the counter increases from the initial value, and in response to the lock detector circuit detecting that the first and second condition signals are present, the analog delay line circuit subsequently adjusting the delay locked loop; and an alignment between edges of the external clock signal and the internal clock signal disabling further incrementing of the counter to hold the digital delay line circuit at a fixed delay to permit adjustment of the delay locked loop by the analog delay line circuit.