Patent ID: 7218562

Claim:
An apparatus comprising: a plurality of memory cells; a first bit line coupled to the plurality of memory cells and a second bit line coupled to the plurality of memory cells; a first bit line precharge circuit coupled to the first bit line and the second bit line, wherein the first bit line circuit is configured to precharge the first bit line and the second bit line; a second bit line precharge circuit coupled to the first bit line and the second bit line, wherein the second bit line circuit is configured to precharge the first bit line and the second bit line; and a control circuit coupled to the first bit line precharge circuit and the second bit line precharge circuit, wherein the control circuit is coupled to receive an indication that one or more clocks are being restarted after a period of stopped clock operation, and wherein the control circuit is configured to activate both the first bit line precharge circuit and the second bit line precharge circuit responsive to the indication and independent of an operation to the memory that was interrupted by the period of stopped clock operation, if any.