Patent ID: 7450419

Claim:
A semiconductor device comprising: a memory cell array comprising a plurality of nonvolatile memory cells; a detection circuit detecting a number of bits to be written as division data that is divided from data to be programmed into the memory cell array and comparing the number of bits with a predetermined number of bits; a latch circuit latching inversion data, which is either the division data inverted or not inverted in accordance with a result of comparing the number of bits with the predetermined number of bits, wherein the latch circuit includes a pair of nodes operating in a complementary manner, and latches the inversion data that is either the division data inverted or not inverted by inputting the division data into either of the pair of nodes in accordance with the result of comparing the number of bits with the predetermined number of bits; a write circuit coupled to the latch circuit and programming the inversion data into the memory cell array; and a control circuit coupled to the detection circuit, the latch circuit, and the write circuit to cause the detection circuit to detect the number of bits to be written as next division data and to compare the number of bits of the next division data with the predetermined number of bits, while concurrently controlling the write circuit to program the inversion data into the memory cell array.