Patent ID: 7061294

Claim:
A clock processing logic for determining an average clock period and jitter for a first clock signal characterized by sample vectors taken on a per cycle basis of said first clock signal, wherein individual of said sample vectors indicate at least one edge of said first clock signal by a bit location varying from cycle to cycle according to reference voltage and temperature variations affecting said first clock signal and corresponding to a transition from one or more bits of a first value on one side of said bit location to one or more bits of a second value on another side of said bit location, comprising: an edge filter configured to generate filtered sample vectors by marking only bit locations corresponding to edges of said first clock signal as indicated in said sample vectors; sample accumulation logic configured to generate accumulative sample vectors by logically OR-ing a predefined number of said filtered sample vectors for individual of said accumulative sample vectors; and clock period and jitter processing logic configured to determine a clock period and jitter on said first clock signal for individual of said accumulative sample vectors.