Patent ID: 8347171

Claim:
A semiconductor memory device comprising: a plurality of banks, each bank including at least one block including a plurality of memory cells; a parity bank including a plurality of parity memory cells; a refresh unit configured to generate a refresh address to perform a self-refresh operation on the plurality of memory cells included in a selected block of each of banks designated by a mode register set (MRS) code, in response to a self-refresh mode signal; an address mapping unit configured to output a match signal and a parity address along with an externally applied address when the externally applied address is an address for designating the selected block during a read/write operation; and an error code generation/correction unit configured to generate an error correction code for externally applied data in response to the match signal and a write signal and store the error correction code in a parity memory cell of the plurality of parity memory cells corresponding to the parity address of the parity bank.