Patent ID: 6865135

Claim:
A synchronizing clock signal generator for generating an output synchronizing clock signal, comprising: a first delay-locked loop (DLL) generating a first synchronizing clock signal, the first DLL having an input clock signal terminal to which a first clock signal having a first frequency is applied and further having an output terminal at which the first synchronizing clock signal having the first frequency is provided; a second DLL generating a second synchronizing clock signal, the second DLL having an input clock signal terminal to which a second clock signal having a second frequency is applied and further having an output terminal at which the second synchronizing clock signal having the second frequency is provided; and a selection circuit having first and second input terminals coupled to the output terminals of the first and second DLLs and having an output clock signal terminal to which the first or second input terminal is coupled to provide the first or second synchronizing clock signal, respectively, as the output synchronizing clock signal, the selection circuit further having a selection terminal for receiving a selection signal on which selection of the first or second synchronizing clock signal is based.