Patent ID: 8497582

Claim:
A nonvolatile semiconductor memory comprising: cell units each having a first select gate transistor, a second select gate transistor, memory cells connected in series in a first direction and provided between the first and second select gate transistors; blocks, each comprising the cell units arranged in a second direction which crosses the first direction and having a first select gate line extending in the second direction and connected to the first select gate transistors, a second select gate line extending in the second direction and connected to the second select gate transistors, and word lines extending in the second direction, respectively connected to the memory cells; a first hookup area provided at a first side of the blocks, all word lines in a first block among the blocks extending to the first hook up area, respectively, having distal ends, and respectively connected to contact plugs in the first hook up area; a second hookup area provided at a second side of the blocks, all word lines in a second block among the blocks extending to the second hook up area, respectively having distal ends, and respectively connected to contact plugs in the second hook up area, the first side and the second side being opposed in the second direction, wherein, the first block is a j-th (j is an odd number) block, and the second block is a (j+1)-th block, all of the word lines in the second block are not connected to a contact plug at the first side of the blocks, and all of the word lines in the first block are not connected to a contact plug at the second side of the blocks.