Patent ID: 8843705

Claim:
A method, in a data processing system, for read- and write-aware cache, the method comprising: receiving a cache access request in a cache controller from a processing unit, wherein the cache access request includes an address comprising a tag; comparing the tag to entries in a read region of a tag and status array and to entries in a write region of the tag and status array, wherein the cache controller determines the cache access request results in a cache miss responsive to the tag not matching any entry in the read region of the tag and status array or any entry in the write region of the tag and status array; responsive to the cache access request being a load resulting in a cache miss, loading, by the cache controller, a cache line of data into a read-often region of a cache array, wherein the cache array comprises an array of banks and wherein the read-often region of the cache array comprises banks that are close in proximity to the processing unit; and responsive to the cache access request being a store resulting in a cache miss, storing, by the cache controller, the cache line of data into a write-often region of the cache array, wherein the write-often region of the cache array comprises banks that are far in proximity to the processing unit.