Patent ID: 8049339

Claim:
A semiconductor package primarily comprising: an encapsulant; a leadframe segment having a plurality of leads, an isolated inner lead, and an external lead, wherein the isolated inner lead is completely encapsulated inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant; wherein each lead has an internal portion encapsulated inside the encapsulant and an external portion extended outside the encapsulant and integrally connected with the internal portion, wherein at least one of the internal portions is located between the isolated inner lead and the external lead; a first chip disposed on the leadframe segment and encapsulated by the encapsulant, wherein the first chip has a plurality of first electrodes; wherein each internal portion has a first finger; wherein the isolated inner lead has a second finger and a third finger at two opposing ends thereof; wherein the external lead has a fourth finger; wherein the first fingers and the second finger are arranged along a first side of the first chip without covered by the first chip and the third finger and the fourth finger are arranged along a second side of the first chip without covered by the first chip; a plurality of first bonding wires encapsulated by the encapsulant, wherein the first bonding wires electrically connect the first electrodes of the first chip to the first fingers of the internal portions and to the second finger of the isolated inner lead; and a jumping wire encapsulated by the encapsulant, wherein the jumping wire electrically connects the third finger of the isolated inner lead to the fourth finger of the external lead overpassing the interposing one of the internal portions, wherein the isolated inner lead and the internal portions are formed from a horizontal layer of the leadframe segment; and wherein a back surface of the first chip is attached to the internal portions and the isolated inner lead.