Patent ID: 8536913

Claim:
An output driver time lock loop apparatus comprising: output driver circuitry coupled between a first output node and a second output node; and feedback circuitry coupled to the output driver circuitry, the feedback circuitry configured to generate a first analog bias voltage in response to a signal on the second output node, the feedback circuitry comprising: sensing circuitry coupled to the second output node, the sensing circuitry configured to sense a first characteristic of the signal on the second output node; reference pulse generation circuitry configured to generate a reference pulse having a pulse width equal to a desired signal characteristic, the reference pulse generation circuitry comprising a chain of inverting stages configured as a ring oscillator, a plurality of pulse samplers coupled to the ring oscillator, each of the pulse samplers configured to receive the transition time pulse and to receive input from a pair of consecutive inverting stages in the chain of inverting stages, each pulse sampler configured to trigger generation of the reference pulse when a rising edge of the transition time pulse is received between the input from the pair of consecutive inverting stages, and charge pump circuitry coupled to the sensing circuitry and coupled to the reference pulse generation circuitry, the charge pump circuitry configured to generate the first analog bias voltage in response to the first characteristic and the reference pulse; the output driver circuitry including a first current source biased by the first analog bias voltage.