Patent ID: 7476592

Claim:
A method for forming a semiconductor device, the method comprising: sequentially depositing a buffer insulation layer and a first insulation layer on a semiconductor substrate having a high voltage device region and a low voltage device region; removing portions of the buffer insulation layer and the first insulation layer to expose a portion of the high voltage device region; forming a second insulation layer thicker than the buffer insulation layer in the exposed portion of the high voltage device region; selectively removing the first insulation layer and the buffer insulation layer from the low voltage device region and the high voltage device region, while masking the second insulation layer and a portion of the buffer insulation layer adjacent to the second insulation layer in the high voltage device region, to expose a portion of the high voltage device region and the entire low voltage device region; forming a third insulation layer thinner than the buffer insulation layer in the low voltage region and on exposed substrate in the high voltage region; and forming transistor gates on the second insulation layer in the high voltage device region and on the third insulation layer in the low voltage device region.