Patent ID: 8058723

Claim:
A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip, comprising: a semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has a plurality of electrode pads thereon; a built-up structure having a first surface and an opposite second surface, wherein the built-up structure comprises at least one dielectric layer, at least one circuit layer stacked on the dielectric layer, and a plurality of conductive vias; the outermost circuit layer of the second surface of the built-up structure has a plurality of conductive pads; a first solder mask, which has a plurality of openings corresponding to the electrode pads of the semiconductor chip, disposed on the first surface of the built-up structure, wherein parts of the conductive vias in the built-up structure each respectively penetrate and completely fill the first openings of the first solder mask, and electrically connect to and directly contact the electrode pads of the semiconductor chip; and a second solder mask disposed on the second surface of the built-up structure, wherein the second solder mask has a plurality of second openings exposing the conductive pads of the built-up structure and an adhesive material wrapping and protecting the semiconductor chip, also enhancing the adhesion between the semiconductor chip and the built-up structure, therewith the inactive surface of the semiconductor chip is exposed to dissipate heat generated by the semiconductor chip during operation.