Patent ID: 8557621

Claim:
A method for manufacturing a thin film transistor array panel, comprising: forming a gate line on an insulating substrate, the gate line comprising a gate electrode; forming a gate insulating layer on the gate line; sequentially forming a first amorphous silicon layer, a second amorphous silicon layer, a lower data metal layer, and an upper data metal layer on the gate insulating layer; forming a first photosensitive film pattern on the upper data metal layer, the first photosensitive film pattern comprising a first part and a second part that is thicker than the first part; performing a first etching process to form a first lower data metal pattern and a first upper data metal pattern that comprises an outwardly extending protrusion disposed at the perimeter thereof, by etching the upper data metal layer and the lower data metal layer using the first photosensitive film pattern as a mask; performing a second etching process to form a first amorphous silicon layer pattern and a second amorphous silicon layer pattern, by etching the first amorphous silicon layer and the is second amorphous silicon layer using the first photosensitive film pattern as a mask; ashing the first photosensitive film pattern to form a second photosensitive film pattern; performing a third etching process to form a second upper data metal pattern, by etching the first upper data metal pattern using the second photosensitive film pattern as a mask; performing a fourth etching process to form a data line, a source electrode that extends from the data line, a drain electrode, a semiconductor, and ohmic contact layers disposed between the source and drain electrodes and the semiconductor, by etching the first lower data metal pattern, the first amorphous silicon layer pattern, and the second amorphous silicon layer pattern using the second photosensitive film pattern as a mask; forming a passivation layer on the data line, the drain electrode, and the gate insulating layer; and forming a pixel electrode on the passivation layer, such that the pixel electrode is connected to the drain electrode.