Patent ID: 7439153

Claim:
A method of manufacturing a semiconductor device comprising the steps of: a step of forming a first active region and a second active region which is separated from said first active region by an element isolator and provided at a position closer to a center of said memory cell region than said first active region, in a memory cell region on a substrate; a step of forming a first gate electrode which crosses said first active region, a second gate electrode which is separated from said first gate electrode and crosses said first active region and said second active region and a third gate electrode which is separated from said first gate electrode and said second gate electrode, an end of which is opposed to an end of said first gate electrode on said second active region side and retreated from said first gate electrode more than an end of said second active region opposed to said first gate electrode; a step of forming a first drain section between said first gate electrode and said second gate electrode in said first active region and a second drain section at the position of the same side of said first drain toward said second gate electrode in said second active region; a step of forming a first wiring which connects said first drain section and said second drain section; and a step of forming a second wiring which connects said second drain section and said third gate electrode.