Patent ID: 7868315

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a memory cell array including a plurality of memory cells, the memory cells including a plurality of memory transistors and an alternative of phase change film portions and resistance change film portions, the phase change film portions and resistance change film portions being formed above the memory transistors to correspond to the memory transistors respectively, and each of the memory transistors including a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film, a source region and a drain region formed apart from the source region in the semiconductor substrate; a plurality of first vias, each of the first via being formed between two adjacent ones of the memory transistors and between two adjacent ones of the alternative of the phase change film portions and the resistance change film portions in order to connect the memory transistors to each other electrically and in order to connect the alternative of the phase change film portions and the resistance change film portions to each other electrically, and each of the first vias being electrically connected to the source region of one of the two adjacent memory transistors and to the drain region of the other of the two adjacent memory transistors, wherein the memory transistors are connected in parallel respectively to the alternative of the phase change film portions and the resistance change film portions with the first vias, and the memory cells are connected in series to one another with the first vias; a reaction prevention film formed on the phase change film; and a heat buffer film formed on the reaction prevention film.