Patent ID: 7221024

Claim:
A chip, comprising: an active semiconductor region having a west edge, an east edge, a north edge and a south edge, said active semiconductor region having a longitudinal direction in a direction between said west and east edges and a transverse direction in a direction between said north and south edges, a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within said active semiconductor region, a length of said channel region being disposed in said longitudinal direction, and a width of said channel region being disposed in said transverse direction; a first dielectric stressor element underlying only a northwest portion of said active semiconductor region between said north and west edges, said first dielectric stressor element having a horizontally extending upper surface, said first dielectric stressor element sharing an edge with said active semiconductor region, said edge extending in a direction away from said upper surface; and a second dielectric stressor element underlying only a southeast portion of said active semiconductor region between said south and east edges, said second dielectric stressor element having a horizontally extending upper surface, said second dielectric stressor element sharing an edge with said active semiconductor region, said edge extending in a direction away from said upper surface, wherein said first dielectric stressor element applies a first stress to the channel region in a first direction and said second dielectric stressor element applies a second stress to the channel region in a second direction opposite to said first direction, such that said first and second stresses cooperate together to apply a magnified shear stress to said channel region.