Patent ID: 7007112

Claim:
A data transfer control device for data transfer through a bus, comprising: a buffer which includes a first storage area for a first information and a second storage area for a second information, the first and second storage areas being provided for one end point, when a plurality of types of informations including the first and second informations have been allocated as informations to be transferred through the one end point; and a buffer management circuit which reads information to be transferred from the end point to a host from the first storage area for the first information during a first phase in which the first information is transferred through the bus, and reads information to be transferred from the end point to the host from the second storage area for the second information during a second phase in which the second information is transferred through the bus, wherein the first information is a data packet; wherein the second information is a status block packet; wherein the second storage area comprises a third storage area into which is written a first status block packet for success status and a fourth storage area into which is written a second status block packet for non-success status; and wherein the first status block packet for success status is read from the third storage area when status is success, and the second status block packet for non-success status is read from the fourth storage area when status is non-success.