Patent ID: 6919647

Claim:
A SRAM cell, comprising: first and second internal PMOS transistors; and first and second internal NMOS transistors, wherein the first internal PMOS transistor is coupled to the first internal NMOS transistor and the second internal PMOS transistor is coupled to the second internal NMOS transistor, and wherein each internal transistor includes, a substrate, a bottom gate disposed on the substrate, a high resistivity layer disposed on the substrate, a channel disposed above the bottom gate, a source disposed on the high resistivity layer and having a source extension extending from a main body of the source and coupled to the channel, a drain disposed on the high resistivity layer and having a drain extension extending from a main body of the drain and coupled to the channel, a gate insulator disposed on the channel, a top gate disposed on the gate insulator, a first insulating spacer disposed between the top gate and the source and proximate to the source extension, and a second insulating spacer disposed between the top gate and the drain and proximate to the drain extension.