Patent ID: 8140945

Claim:
A memory controller comprising: a check bit encoder circuit coupled to receive a data block to be written to memory, wherein the check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits; and a check/correct circuit coupled to receive an encoded data block read from the memory, the check/correct circuit configured to detect an error in the encoded data block responsive to the first plurality of check bits, the second plurality of check bits, and the data block within the encoded data block, and wherein the encoded data block is logically arranged as an array of R rows and N columns, wherein R and N are positive integers, and wherein each of the first plurality of check bits covers a respective row of the array, and wherein the check/correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits, and wherein a presence of more than one binary one in the first syndrome indicates a multi-bit error; and a hard failure detection circuit coupled to the check/correct circuit wherein, responsive to detecting the multi-bit error, the hard failure detection circuit is configured to perform a plurality of memory read/write operations to the memory locations in which the encoded data block is stored to identify a hard error failure in the memory.