Patent ID: 8890108

Claim:
A memory device having a plurality of memory elements arranged in rows comprising: a semiconductor substrate having a first type conductivity and a plurality of parallel trenches separated by ridges that form sidewalls of said trenches therein, each of said trenches having a trench bottom and a pair of trench sidewalls; a plurality of parallel source lines having a second type conductivity opposite to said first type conductivity with one source line being formed in each trench bottom; a plurality of parallel gate electrodes formed on said trench sidewalls over a gate dielectric layer with each trench having a pair of gate electrodes disposed on opposite sides of said source line in said trench; and a plurality of drain regions having said second type conductivity formed in top regions of said ridges that form said trench sidewalls, each drain region being coupled to a resistive memory element with a row of said drain regions being formed adjacent to each of said trench sidewalls wherein each row of drain regions is coupled to a common channel that connects said row of drains to said one source line in said trench.