Patent ID: 7626257

Claim:
A method of fabricating a three dimensional (3D) integrated circuit (IC), the method comprising: forming a plurality of vias within a first workpiece; forming isolation trenches in the first workpiece; forming a plurality of trenches within the first workpiece; after forming the pluralities of vias and trenches, forming trench capacitors by filling the plurality of trenches with a first material stack within the first workpiece, the first material stack also filling the plurality of vias; after forming the trench capacitors, masking the plurality of vias within the first workpiece; after masking the plurality of vias, forming first active areas disposed between the isolation trenches in the first workpiece, the first active areas comprising CMOS devices; after forming the first active areas, opening the plurality of vias within the first workpiece; after opening the plurality of vias, filling the plurality of vias with a second material stack; after filling the plurality of vias with the second material stack, forming a first interconnect region over the first active areas and the plurality of vias and the trench capacitors; forming second active areas in a second workpiece; after forming the second active areas, forming a second interconnect region over the second active areas; and after forming the second interconnect region, vertically coupling the second workpiece to the first workpiece by direct bonding, wherein the plurality of vias provides vertical electrical connections for the 3D-IC.