Patent ID: 7750683

Claim:
A Phase/Frequency Detector (PFD), comprising: a rising signal module for generating a rising signal according to a second reference clock signal and a rising reset signal; a falling signal module for generating a falling signal according to a second fed-back clock signal and a falling reset signal; and a reset signal module, comprising: a rising reset signal module, comprising: a first NAND gate, comprising: a first input end for receiving a pre-trigger fed-back signal; a second input end for receiving the falling signal; and an output end for outputting result of NAND operation on signals received on the first and the second input ends of the first NAND gate; a first OR gate, comprising: a first input end for receiving an inverted signal of the rising signal; a second input end for receiving an inverted signal of the falling signal; and an output end for outputting result of OR operation on signals received on the first and the second input ends of the first OR gate; a second NAND gate, comprising: a first input end coupled to the output end of the first NAND gate; a second input end coupled to the output end of the first OR gate; and an output end for outputting result of NAND operation on signals received on the first and the second input ends of the second NAND gate as the rising reset signal; and a falling reset signal module, comprising: a third NAND gate, comprising: a first input end for receiving a pre-trigger reference signal; a second input end for receiving the rising signal; and an output end for outputting result of NAND operation on signals received on the first and the second input ends of the third NAND gate; a second OR gate, comprising: a first input end for receiving an inverted signal of the rising signal; a second input end for receiving an inverted signal of the falling signal; and an output end for outputting result of OR operation on signals received on the first and the second input ends of the second OR gate; a fourth NAND gate, comprising: a first input end coupled to the output end of the third NAND gate; a second input end coupled to the output end of the second OR gate; and an output end for outputting result of NAND operation on signals received on the first and the second input ends of the fourth NAND gate as the falling reset signal.