Patent ID: 7536509

Claim:
A method for fetching data from a non-volatile memory ( 602 ) embedded in an integrated circuit with a processor ( 603 ) and an interface ( 605 ) connecting said processor ( 603 ) to said non-volatile memory ( 602 ), comprising the following steps: when new data are requested from said non-volatile memory ( 602 ) by said processor ( 603 ), the address (ba[ . . . ]) corresponding to said new data will be directed simultaneously to said non-volatile memory ( 602 ) and to a cache ( 601 ) embedded in said interface ( 605 ) that serves as a cache for said non-volatile memory; determining if the requested address (ba[ . . . ]) is stored in said cache ( 601 ) within the same first half of the system clock cycle when simultaneously directing the address occurs; then if the requested address (ba[ . . . ]) is stored in said cache ( 601 ) the data will be provided from said cache ( 601 ) to said processor ( 603 ); otherwise a strobe signal within the system clock cycle during which said address (ba [ . . . ]) has changed will be directed to said non-volatile memory ( 602 ) to signal said non-volatile memory to provide the data at said address (ba[ . . . ]); and upon availability of said data in said non-volatile memory ( 602 ) corresponding to said address (ba[ . . . ]), said data (FlashOutQ[ . . . ]) will be directed to said processor ( 603 ).