Patent ID: 8110456

Claim:
A method for making a self aligning memory device, the memory device of the type comprising a memory element switchable between electrical property states by the application of energy, the method comprising: (a) forming first, second, third and fourth word line conductors on a substrate, each word line conductor having a word line top and word line sides; (b) forming dielectric sidewall spacers on the word line sides, the sidewall spacers spaced apart from one another by first, second and third gaps with the substrate exposed at the gaps; (c) forming first and second terminals of an access device within the substrate at the first, second and third gaps, the first terminal located directly under the second gap and the second terminal formed directly under each of the first and third gaps; (d) forming a source line in the first and third gaps electrically connected to respective ones of the second terminals; (e) forming a first electrode in the second gap electrically connected to the first terminal; (f) depositing a memory material in the second gap to form a memory element electrically connected to the first electrode, the memory material depositing step creating a first subassembly; (g) planarizing the first subassembly to create a second subassembly having a planarized upper surface; (h) forming a second electrode electrically connected to the memory element; the second electrode forming step comprising: depositing a second electrode material layer onto the planarized upper surface; forming second electrode masks on the second electrode material layer; forming trenches in the regions between the second electrode masks; and removing the second electrode masks; and (j) depositing a dielectric material into the trenches.