Patent ID: 7410835

Claim:
A method for fabricating a semiconductor package with a lead frame, comprising the steps of: preparing a lead-frame plate composed of a plurality of array-arranged lead frames and a plurality of connecting portions for interconnecting adjacent lead frames, each lead frame having a centrally-situated die pad and a plurality of leads that extend from periphery toward a center of the lead frame and surround the die pad, and leads of a lead frame being connected to leads of an adjacent lead frame by a corresponding connecting portion, wherein each lead has a top surface, a bottom surface opposed to the top surface, and an end that is situated at periphery of a lead frame and associated with a connecting portion, and wherein the end of the lead and the connecting portion are removed by a predetermined thickness to form a thickness-reduced portion, in a manner that a lead is removed from a top surface of a peripheral end thereof by the predetermined thickness to form a thickness-reduced portion, and an adjacent lead is removed from a bottom surface of a peripheral end thereof by the predetermined thickness to form a thickness-reduced portion, so as to allow the thickness-reduced portions to be smaller in thickness than the leads, and to allow the thickness-reduced portions of the adjacent leads to be disposed in a staggered manner; mounting at least a chip respectively on the die pad of each lead frame of the lead-frame plate; forming a plurality of conductive elements for electrically connecting the chip to the corresponding leads; forming an encapsulant on the lead-frame plate for encapsulating the lead frame, chips and conductive elements, wherein the bottom surfaces of the leads are exposed to outside of the encapsulant; and performing a singulation process for cutting away the connecting portions, so as to singulate the leads and form individual semiconductor packages.