Patent ID: 8677072

Claim:
A method of handling memory access requests in a digital memory system, said method comprising: receiving a memory read request for a first address and a memory write request with a write data value to a second memory address; simultaneously fetching a first read data item from said first address in a main memory, a second read data item from a first cache entry in a cache memory associated with said first address, a cache tag value associated with said first cache entry, and a third read data item from a write register containing information from a memory write data made in an earlier memory cycle; comparing said first address with said cache tag value to determine if said first address was represented in said cache memory; returning said third data item in response to said read request if said first address was currently represented in said write register said first data item in response to said read request if said first address was currently represented in said main memory or returning said second data item in response to said read request if said first address was currently represented in said cache memory; and resolving said memory write request to said second address in a later memory cycle by retrieving a cache data value from a second cache entry in said cache memory associated with said second address, flushing said write data value to said main memory if a write to second memory address does not conflict with a new read of said main memory occurring in said subsequent memory cycle, and flushing said cache data value to said main memory if a memory address associated with said cache data value does not conflict with said new read of said main memory occurring in said subsequent memory cycle.