Patent ID: 6861707

Claim:
A memory cell comprising: a data transfer element adapted to facilitate a read operation or a write operation involving a storage node of the memory cell; and a first negative differential resistance (NDR) element coupled to said data transfer element, said storage node and a first voltage potential, wherein said first NDR element is adapted to operate with a first NDR characteristic between said storage node and said first voltage potential; and a second NDR element coupled to said first NDR element, said data transfer element, said storage node and a second voltage potential wherein said second NDR element is adapted to operate with a second NDR characteristic between said storage node and said second voltage potential; said first NDR element and said second NDR element both including a trap layer in which charge traps are used to effectuate said first NDR characteristic and said second NDR characteristics; wherein said charge traps are distributed in said trap layer so as to cause the memory cell to achieve a soft error rate of approximately 1,000 failures-in-time (FITs)/Mbit or less.