Patent ID: 7600098

Claim:
A system for efficient implementation of a large store buffer within a processor of a computing system, comprising: a first component in the store buffer configured to hold one or more addresses and data corresponding to each of a plurality of stores, the plurality of stores in the first component include younger stores requested by the processor, the first component capable of handling store-to-load forwarding; and a second component within the store buffer communicatively linked to the first component, the second component configured to hold one or more addresses and data corresponding to each of a plurality of older stores, each of the plurality of older stores having been moved from the first component, wherein the second component further includes: a first-in-first-out (FIFO) buffer configured to hold one or more addresses and data corresponding to each of the plurality of older stores in program order; and an address disambiguator configured to hold one or more of the addresses corresponding to each of the plurality of older stores stored in the FIFO buffer, the address disambiguator providing store-to-load alias detection for one or more of the plurality of older stores stored in the FIFO buffer for store conflict resolutions, wherein the address disambiguator further comprising a counter to keep track of a number of stores in the FIFO buffer with addresses that fall within a range of addresses represented by disambiguator entries, the counter adjusted based on addition or removal of stores from the FIFO buffer that fall within a corresponding address range.