Patent ID: 8421193

Claim:
An integrated circuit device, comprising: a bottom wafer including: a first active element; a first trench isolation disposed next to the first active element; a first dielectric block penetrating through the first trench isolation; a first dielectric layer covering the first active element, the first trench isolation and the first dielectric block; a first connecting structure disposed on the first dielectric block and the first trench isolation; and at least one stacking wafer positioned on the bottom wafer and including: a second active element; a second trench isolation disposed next to the second active element; a second dielectric block penetrating through the second trench isolation and bottom side of the second dielectric block is exposed by wafer thinning removing backside conduction active element; a second dielectric layer covering the second active element, the second trench isolation and the second dielectric block; a second connecting structure disposed on the second dielectric block and the second trench isolation; and wherein the bottom wafer and the at least one stacking wafer are bonded by an intervening adhesive layer, no bump pad is positioned between the bottom wafer and the at least one stacking wafer, and at least one conductive via penetrating through the at least one stacking wafer and into the bottom wafer in a substantially linear manner, wherein the at least one conductive via is surrounded by the first dielectric block and the second dielectric block.