Patent ID: 8677172

Claim:
A system for detecting timing characteristics of generated clock signals in a communications device, the system comprising: a phase lock loop configured to generate a first clock signal to be tested; a test counter having a test input at which the generated first clock signal to be tested is received; a system clock running at a known frequency to produce a system clock signal, the system clock signal being of a lower accuracy than the generated first clock signal; a gating counter having an input arranged to receive the system clock signal; and a system controller operative to control the counters; wherein the system controller is operative to control the gating counter to count a predetermined number of system clock cycles to define a test period, and during the test period the test counter is operative to count the cycles of the generated first clock signal under test, whereby timing characteristics of the generated first clock signal may be found with reference to a time base defined by the system clock so as to detect errors in the generated first clock signal; wherein the system is configured so that, in response to an error being detected in the generated first clock signal, remedial action is taken to correct the error, the remedial action comprising causing the phase lock loop to re-acquire a lock.