Patent ID: 7536668

Claim:
A processor-implemented method for determining a plurality of networks of a tile module of a programmable logic device (PLD) design, the method comprising: inputting a netlist that describes the PLD design, the netlist including a plurality of instances of a plurality of modules and the instances including a plurality of tile instances of the tile module; inputting an identification of the tile module; inputting characterization data for each of at least one sub-module of the tile module, the characterization data specifying a plurality of modeled pins of the at least one sub-module, wherein each sub-module is one of a logic-site module and a switchbox module, and a logic-site module provides programmable logic resources; determining a plurality of connectivity pins of the tile module, wherein for each connectivity pin, the connectivity pin of one of the tile instances is connected in the netlist to one of the modeled pins of an instance of the at least one sub-module within one of the tile instances; determining each of a plurality networks of the tile module, wherein each network connects a respective first subset of the connectivity pins of the tile module and a respective second subset of the modeled pins of the at least one instance of the at least one sub-module within the tile module; and outputting for each of the networks a specification of the respective first subset of the connectivity pins and the respective second subset of the modeled pins.