Patent ID: 7269817

Claim:
A method for lithographic process window optimization of an integrated circuit layout on a wafer and of superimposable masks and mask levels for fabrication of the integrated circuit layouts that are illuminated by beams of light radiation from a range of directions, said method comprising: specifying a preliminary set of printed circuit feature edge locations, recentering a model region selected at each edge location upon the printed edge of said circuit layout reaching the exterior of said model region; specifying a set of linked constraints on allowable positions for the edges of said circuit features; wherein said allowable positions of said edges are shiftable within a range in which a variation of image intensity at sidewalls of the image is approximately linear or quadratic in nature; wherein said allowable shifts in the edges are implemented in parallel with trust region constraints on edge positions to effect said circuit layout optimization; initially centering trust regions at the preliminary locations of said circuit feature edges; computing models of intensities of images projected within said trust region; and adjusting shapes provided on said masks and said intensities of said light beams illuminating the masks to project images on the wafer which satisfy the linked set of constraints over as wide a range of exposures as possible based on the computing models.