Patent ID: 8634440

Claim:
A method of forming processing circuitry to provide processing corresponding to an integrated circuit comprising first processing circuitry coupled to N instances of further processing circuitry, said method comprising the steps of: forming said first processing circuitry clocked by a first clock signal with a first clock frequency of f 1 and configured to perform processing operations to generate N parallel output signals of said first processing circuitry; forming multiplexing circuitry coupled to said first processing circuitry and configured to receive said N parallel output signals of said first processing circuitry and to select as an output signal of said multiplexing circuitry one of said N parallel output signals of said first processing circuitry; forming second processing circuitry coupled to said multiplexing circuitry to receive and to perform processing operations upon said output signal of said multiplexing circuitry to generate an output of said second processing circuitry, said second processing circuitry being clocked by a second clock signal with a second clock frequency f 2 , where f 2 is N*f 1 and one clock period of said first clock signal corresponds to N clock periods of said second clock signal; forming demultiplexing circuitry coupled to said second processing circuitry and configured to receive and to select said output of said second processing circuitry as one of N parallel output signals of said demultiplexing circuitry; and forming switching control circuitry coupled to said multiplexing circuitry and to said demultiplexing circuitry and configured to: (i) control said multiplexing circuitry to select in turn each one of said N parallel output signals of said first processing circuitry to provide said output signal of said multiplexing circuitry for one clock period of said second clock signal while said second processing circuitry performs processing operations corresponding to one of said N instances of said further processing circuitry; and (ii) control said demultiplexing circuitry to select in turn each one of said N parallel outputs of said demultiplexing circuitry to be provided by said output signal of said second processing circuitry during one clock period of said second clock signal; wherein said second processing circuitry is formed to comprise N sets of storage elements, each of said N sets of storage elements being configured to store a set of state variables and to be exclusively available for access by other portions of said second processing circuitry during a respective different one of said N clock periods of said second clock signal, wherein said first processing circuitry, said multiplexing circuitry, said second processing circuitry and said demultiplexing circuitry are provided as part of a field programmable gate array.