Patent ID: 8686497

Claim:
A double-gate vertical channel (DGVC) memory cell array, comprising: a plurality of double-gate transistor cells each having a vertical channel within each double-gate vertical channel (DGVC) cell of a DGVC memory cell array, with said double-gate transistor cells arranged in an alternating gate-facing orientation; a common source junction at a first end of the vertical channels which is shared by each said DGVC cell; drain junctions formed at second ends of the vertical channels to which contact is made by bit lines, with one bit line for each row of DGVC cells within the DGVC memory cell array; gate lines oriented orthogonally to said bit lines, for gating said vertical channels located on either side of each of said gate lines; a front gate within each DGVC cell which is shared with a neighboring cell in a first direction along any given one of the bit lines; and a back gate within each DGVC cell which is shared with a neighboring cell in a second direction, opposite the first direction, along any given one of the bit lines; wherein said DGVC cell array is configured for injecting holes into a said DGVC cell during a write operation for retention to represent a first memory state, whereas a lack of holes in the DGVC cell represents a second memory state, as determined in a read operation on said DGVC cell.