Patent ID: 8484397

Claim:
An integrated circuit having an interconnect to communicate transactions between one or more initiator IP cores and one or more target IP cores coupled to the interconnect, comprising: a memory scheduler coupled to a first target memory core of the one or more target IP cores that includes a bank of memories, where address space in the first target memory core is addressable through the memory scheduler, and the memory scheduler has a multiple stage arbiter to determine which transaction will access the first target memory core, wherein two or more stages perform computations and those computations combine to determine a winner of an arbitration process, and where the multiple stage arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel selected from the group consisting of a Quality of Service (QoS) factor associated with each transaction, an absolute filter factor, a page-filter factor, a least recently serviced factor, a response valid factor, and a same chip filter, and where the first stage has logic configured to let a first transaction go through to be a candidate for arbitration when there is no other transactions whose current QoS level is higher than the QoS level of the first transaction.