Patent ID: 8896362

Claim:
A control circuit for generating a first control signal and a second control signal, comprising: an inverter, arranged for inverting an input clock to generate an inverted clock; a first delay circuit, arranged for delaying the first control signal to generate a first delay control signal; a second delay circuit, arranged for delaying the second control signal to generate a second delay control signal; a first mask circuit, coupled to the first delay circuit and the input clock, arranged for filtering out the first delay control signal not larger than a first time period to generate a first mask signal according to the input clock; a second mask circuit, coupled to the second delay circuit and the inverted input clock, arranged for filtering out the second delay control signal not larger than a second time period to generate a second mask signal according to the inverted input clock; a first logic determining circuit, arranged for generating the first control signal to the first delay circuit according to the second mask signal and the input clock; and a second logic determining circuit, arranged for generating the second control signal to the second delay circuit according to the first mask signal and the inverted input clock; wherein the first control signal is further transmitted to a gate of a P-type transistor, the second control signal is further transmitted to a gate of an N-type transistor, and the first time period and the second time period are larger than a summation of a largest delay time of the first delay circuit and the second delay circuit and a largest delay time of the P-type transistor and the N-type transistor.