Patent ID: 6892289

Claim:
A system comprising: multiple master devices that generate memory requests; multiple banks of memory where each bank includes multiple rows of memory locations; a memory controller coupled to said multiple banks of memory for controlling access to said multiple banks of memory; an arbiter associated with said memory controller and coupled to said multiple master devices for arbitrating among said master devices to apply said memory requests generated by said master devices to said memory controller; and a plurality of memory model circuits associated with said arbiter for generating signals applied to said arbiter wherein each memory model is associated with a corresponding bank of said multiple banks of memory and wherein said signals indicate readiness of said corresponding bank for application of a memory request generated by a master device, wherein said arbiter is adapted to arbitrate among said master devices in accordance with said signals generated by said plurality of memory model circuits, wherein each memory model circuit includes: a memory element for storing a last address generated by a master device of said multiple master devices; and a comparator for comparing a previously stored last address with a new address corresponding to a memory request generated by a master device of said multiple master devices wherein said comparator is operable to determine whether said new address is within the same region of memory as said last address and is further operable to generate an output signal indicating that said new address is within the same region of memory as said last address.