Patent ID: 8102705

Claim:
A non-volatile memory circuit, comprising: a memory array having a plurality of non-volatile memory cells formed along a plurality of word lines and a plurality of bit lines; read and write circuitry connectable to the memory array; and an input/output data bus connectable to the read and write circuitry for the transfer of data to and from the memory array, wherein the read and write circuitry includes: a plurality of read/write stacks each connectable to a corresponding subset of the bit lines and each having: a sense amp connectable to the corresponding subset of bit lines; a stack bus; a set of data latches connected to the bus; a stack processing circuit connected to the stack bus for controlling the transfer of data along the stack bus between the data latches and the sense amp; and an input/output module connected to the input/output bus and the stack bus to transfer data therebetween; and a local internal data bus connected between the stack buses of a subset of the plurality of read/write stacks whereby data can be transferred between the data latches of different ones of the subset of the plurality of read/write stacks.