Patent ID: 7928000

Claim:
A method for processing integrated circuit devices including forming self aligned contact regions, the method comprising: providing a partially completed semiconductor wafer, the wafer including one or more semiconductor chips, each of the chips including a plurality of MOS gate structures, each of the gate structures being formed on a substrate and having a first layer of silicon nitride formed overlying portions including a contact region between the gate structures, each of the chips having conformal layer of doped silicon glass of a predetermined thickness overlying the silicon nitride layer and the gate structures; applying a plasma etching process to the doped silicon glass to expose a portion of the first silicon nitride layer using an anisotropic etching component to vertically remove portions of the doped silicon glass; cleaning the exposed portion of silicon nitride using an isotropic component; forming a second silicon nitride layer on the exposed portion of the first silicon nitride layer; removing the second silicon nitride layer and exposed portion of the first silicon nitride layer to expose the contact region on the substrate; and processing the exposed contact region.