Patent ID: 7508246

Claim:
A circuit comprising: a ring oscillator; a frequency counter coupled to the ring oscillator, the frequency counter providing a count value which indicates a number of edges of predetermined direction of an output of the ring oscillator which occur during a period of a reference frequency; a decoder coupled to the frequency counter and which uses the count value to output a performance variation indicator, the performance variation indicator indicating a variation in at least one characteristic selected from a group consisting of process, voltage, and temperature, the decoder determining a difference between an actual count value and a minimum count value of the counter and dividing the difference by a total number of delay elements and driver circuits presently selected by the performance variation indicator; an input terminal which receives an input signal; a delay selection section coupled to the input terminal and which delays the input signal by a delay amount selected by the performance variation indicator to provide a delayed input signal; an impedance selection section coupled to the delay selection section and which outputs the delayed input signal as a compensated delayed signal, the impedance selection section using a driver impedance amount selected by the performance variation indicator; and an output terminal coupled to the impedance selection section and which outputs the compensated delayed signal.