Patent ID: 8643416

Claim:
A semiconductor device comprising a DLL (Delay Locked Loop) circuit, wherein said DLL circuit comprises: a delay unit generating a second clock signal by delaying a first clock signal; a phase comparator circuit comparing said first clock signal and a signal generated by further delaying said second clock signal; a counter circuit outputting a count value that determines a delay amount of said delay unit to said delay unit, and up/down operating in response to a result of the phase comparison by said phase comparator circuit; and an initial delay amount control circuit detecting a cycle of said first clock signal at the time of initial setting operation, and outputting an initial value of said count value depending upon the detected cycle to said counter circuit, wherein said initial delay amount control circuit comprises: a pulse signal generating unit generating a pulse signal having a pulse width proportional to the cycle of said first clock signal; a plurality of delay elements connected in series delaying said pulse signal; a detection unit detecting which of a plurality of delay elements said pulse signal is transmitted to during said pulse width of said pulse signal; and a code generation unit generating the initial value of said count value based on a result detected by said detection unit.