Patent ID: 8482951

Claim:
A semiconductor memory device having an open bitline memory structure, comprising: a memory block comprising a memory cell arrangement; an edge sense amplification block comprising a first sense amplifier comprising a first bitline, a first complementary bitline, and a first amplification circuit comprising first and third transistors having a first size, wherein the first transistor is connected to the first bitline and the third transistor is connected to the first complementary bitline; a central sense amplification block comprising a second sense amplifier comprising a second bitline, a second complementary bitline, and a second amplification circuit comprising second and fourth transistors having a second size smaller than the first size; and a capacitor block electrically connected to the edge sense amplification block, wherein each of the first and second amplification circuits respectively comprises a Metal Oxide Semiconductor (MOS) sense amplifier, an equalization circuit, and a column selection circuit.