Patent ID: 6858502

Claim:
A method for forming p-channel field effect transistors comprising the steps of: selecting a single crystalline substrate, forming a first layer of relaxed Si 1-x Ge x epitaxially on said substrate where Ge friction x is in the range from 0.35 to 0.5, forming a second layer of Si 1-x Ge x epitaxially on said first layer, forming a third layer of undoped Si epitaxially on said second layer, forming a fourth layer of undoped Si 1-x Ge x epitaxially on said third layer, forming a fifth layer of Ge epitaxially on said fourth layer whereby said fifth layer is under compressive strain and has a thickness less than its critical thickness with respect to said first layer, forming a sixth layer of Si 1-w Ge x epitaxially on said fifth layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w-x> 0.2 whereby said sixth layer is under compressive strain, and forming a seventh layer of Si 1-x Ge x epitaxially on said sixth layer.