Patent ID: 7344944

Claim:
A method for fabricating a non-volatile memory device, the method comprising: forming a device isolation layer on a semiconductor substrate to define a plurality of active regions; forming a first conductive layer on the plurality of active regions; patterning the first conductive layer to form a first conductive pattern on the active regions; forming an insulating layer on the first conductive pattern; patterning the insulating layer to form an opening extending therethrough, the opening exposing a portion of the first conductive pattern; forming a second conductive layer on the patterned insulating layer and on the exposed portion of the first conductive pattern through the opening; and forming a selection gate pattern according to a method comprising: sequentially patterning the second conductive layer and the first conductive pattern to form a top gate pattern; and after sequentially patterning the second conductive layer and the first conductive pattern, patterning the patterned insulating layer and the patterned first conductive pattern to form an inter-gate dielectric and a bottom gate pattern, respectively, wherein the width of the inter-gate dielectric is narrower than the width of the bottom gate pattern.