Patent ID: 7587692

Claim:
A method for performing thermal analysis of a semiconductor chip design, the semiconductor chip design comprising a plurality of elements, the elements including one or more embedded semiconductor devices and one or more embedded interconnects, the method comprising: receiving, for each of at least some of the plurality of elements, a respective at least one semiconductor chip design parameter; and calculating, using a processor, the power dissipated by the at least some of the plurality of elements, in accordance with the respective at least one semiconductor chip design parameter; distributing power dissipated by the at least some of the plurality of elements among the plurality of elements; and constructing using a processor a three-dimensional full-chip thermal model of the semiconductor chip design in accordance with the distributed power, the thermal model depicting computed temperatures for the at least some of the plurality of elements, wherein the constructing comprises: adaptively partitioning the thermal model in response to volumes of steep thermal gradients over the semiconductor chip design, wherein the volumes of steep thermal gradients are determined to be steep relative to other regions of an overall temperature gradient for the semiconductor chip design; wherein the at least some of the plurality of elements includes at least one of the one or more embedded interconnects, and wherein the one or more embedded interconnects are deployed, at least in part, to connect the one or more embedded semiconductor devices.