Patent ID: 7221617

Claim:
Memory module having: (a) at least one memory cell array, the memory cells each being addressable by at least one address and being organized in organization units comprising a predetermined number of memory cells which are jointly contemporaneously accessible; (b) a clocked read/write control device, which is clocked with a first clock signal and which is coupled to the memory cell array, for writing data to and reading data from the memory cells as a function of address signals; (c) a prefetch register unit, which is coupled to the read/write control device, for initial storage of data which is read from the memory cell array, the prefetch register unit having a plurality of prefetch registers, whose respective register size corresponds to the predetermined number of memory cells in the organization units; and (d) a controlled switching device, which is coupled to the prefetch register unit, for outputting the data which is initially stored in the prefetch registers at data input/output terminals of the memory module, wherein the switching device, in a first operating mode, is controlled by a second clock signal and successively couples the prefetch register to the data input/output terminals of the memory module, the number of said data input/output terminals corresponding to the predetermined number of memory cells in the organization units, and wherein the switching device, in a second operating mode, is controlled by at least one of the address signals and couples at least one of the prefetch registers to the data input/output terminals of the memory module.