Patent ID: 8214171

Claim:
A semiconductor memory device, comprising: a mode setting unit providing a mode register set signal, the mode register set signal corresponding to predetermined mode setting in response to an external command and a first address signal for a mode set; and a test mode circuit, in an initial operation, performing test mode enable in response to the mode register set signal and a second address signal for test enable control; when in the test mode enable state, outputting a test mode item signal in response to the mode register set signal and a third address signal for test item selection; and when in a subsequent operation, receiving the test mode item signal as a feed-back signal to maintain the test mode enable state, wherein when the mode setting unit is set as a test mode register by the external command and the first address signal, the mode setting unit provides a test mode register set signal; and when the mode setting unit is set as an extended mode register by the external command and the first address signal, the mode setting unit provides an extended mode register set signal, and wherein the test mode circuit comprises: an address shift unit, in response to the test mode register set signal, sequentially shifting the second address signal to be outputted as a plurality of address shift signals; an address latch unit, in response to the extended mode register set signal, latching the second address signal to be outputted as a test mode control signal; a test mode enable controller, in response to any one of the plurality of address shift signals, the test mode control signal and the test mode item signal, generating a test mode enable signal corresponding to the test mode enable; and a decoding unit, in response to the test mode register set signal and the test mode enable signal, decoding the third address signal to be outputted as the test mode item signal.