Patent ID: 7342463

Claim:
A timing circuit, comprising: a capacitance; a first resistance (R 1 ); an arbitrary voltage applied across R 1 such that R 1 has first and second endpoint voltages, thereby creating a first current; a first means for coupling said first current to said capacitance such that said capacitance is charged to a first endpoint voltage by a positive charging current which varies with said first current, and a second means for coupling said first current to said capacitance such that said capacitance is discharged to a second endpoint voltage by a negative charging current which varies with said first current, said first and second coupling means arranged such that the magnitudes of said positive and negative charging currents can be established independently; circuitry arranged such that said capacitance is charged until the voltage across said capacitance crosses a first threshold voltage which is proportional to one of R 1 's first and second endpoint voltages, and is discharged until the voltage across said capacitance crosses a second threshold voltage which is proportional to the other of R 1 's first and second endpoint voltages, such that said capacitance's endpoint voltages track R 1 's first and second endpoint voltages, said first and second coupling means enabling the time required to charge said capacitance to be different from the time required to discharge said capacitance.