Patent ID: 7584391

Claim:
Write circuitry for a memory array having a plurality of non-volatile storage elements programmable to store a multi-state data levels, comprising: program circuitry connected the memory array to selectively apply programming pulses to selected non-volatile storage elements of the memory array; sensing circuitry connected to the memory array to selectively determine the value of a parameter indicative of a state of the selected non-volatile storage elements; comparison circuitry connected to the sensing circuitry to perform a program verify operation, the program verify operation including comparing the value of the parameter indicative of the state of the selected storage elements resultant in response to a programming pulse with one or more target values for said parameter, where the one or more target values correspond to a subset of the multi-state data levels to which the storage elements are programmable; and logic circuitry connected to the comparison circuitry to a determination of which of the multi-state data levels to include in the subset, the determination including whether to add one or more of the multi-state data levels to the subset, wherein the adding of one or more of the multi-state data levels to the subset of the multi-state levels that are used in a given program verify operation of a write operation is determined based on results of a preceding program verify operation of the write operation.