Patent ID: 8860485

Claim:
A latch circuit comprising: a latch portion; and a data holding portion for holding data of the latch portion, the latch portion comprising: a first element; and a second element, wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, and wherein the input of the first element is electrically connected to a first wiring configured to be supplied with an input signal, and the output of the first element is electrically connected to a second wiring configured to be supplied with an output signal, the data holding portion comprising: a transistor; a capacitor; and an inverter, wherein a channel formation region of the transistor includes an oxide semiconductor layer, wherein an input of the inverter is electrically connected to the capacitor, wherein the inverter includes an n-channel transistor and a p-channel transistor, and wherein the oxide semiconductor layer contains indium, gallium, and zinc.