Patent ID: 8207575

Claim:
A semiconductor device, comprising: a semiconductor substrate having an epitaxial layer thereon; a first conductivity type well region comprising a lower well region in the semiconductor substrate and an upper well region in the epitaxial layer, the first conductivity type well region having irregularities therein in a gate width direction; a gate electrode formed in the irregularities via an insulating film; a second conductivity type upper source region in the upper well region on a first side of the gate electrode in an irregular longitudinal direction; a second conductivity type lower source region in the upper well region and the lower well region below and in contact with the second conductivity type upper source region; a second conductivity type upper drain region in the upper well region on a second side of the gate electrode in the irregular longitudinal direction; and a second conductivity type lower drain region in the upper well region and the lower well region below and in contact with the second conductivity type upper drain region.