Patent ID: 8024392

Claim:
An apparatus for performing exponentiations, comprising: a set of computational devices containing first and second subsets, wherein the first subset has a plurality of members which are chained together such that the devices of the first subset can operate both independently and as members of a first computational chain, and wherein the second subset has a plurality of members which are chained together such that the devices of the second subset can operate both independently and as members of a second computational chain distinct from said first computational chain; and a chaining controller adapted to instruct the first subset of devices to act as a first computational chain when the apparatus is required to perform an exponentiation of a first size, and being further adapted to instruct the second subset of devices to act as a second computational chain when the apparatus is required to perform an exponentiation of a second size distinct from said first size; wherein the set of computational devices is a set of exponentiators, wherein said chaining controller is a direct memory access controller which is adapted to load arguments and control information into the internal memory and registers of said plurality of exponentiators, wherein each of said plurality of exponentiators comprises a plurality of session controllers, and wherein each of said plurality of session controllers is adapted to process separate exponentiations concurrently.