Patent ID: 8341477

Claim:
A test board, wherein the test board comprises: a plurality of test modules, wherein each test module is configured to store a first control signal, a data signal, and a second control signal in response to a clock signal, wherein each test module is configured to test a corresponding device under test (DUT) using the first control signal and the data signal in response to the second control signal to generate an error judgment signal indicating whether the DUT is defective, wherein each test module is configured to output the first control signal, the data signal, and the second control signal to a test module in a next stage, wherein each test module of a subsequent stage is configured to receive the error judgment signal generated by a test module in a previous stage in response to the clock signal, wherein each test module comprises: a clock generator configured to output an internal clock signal in response to the clock signal; and a latch unit configured to receive and store the first control signal, the data signal, and the second control signal in response to the internal clock signal, and output the first control signal, the data signal, and the second control signal which are stored therein.