Patent ID: 7220662

Claim:
A method of forming a silicided field effect transistor, comprising the steps of: Providing a semiconductor wafer having a substrate and a device layer above the substrate; Forming a gate dielectric layer; Forming a gate layer on said gate dielectric layer; Forming a stack height layer having different etch properties than said gate layer; Patterning a gate stack including said gate layer and said stack height layer, stopping on said gate dielectric; Forming sidewall spacers on said gate stack; Implanting a Source and Drain adjacent to said sidewall spacers; Depositing sacrificial oxide; Removing sacrificial oxide to expose said stack height layer, except over S/D; Etching said stack height layer selective to said gate layer, stopping on said gate layer and said sacrificial oxide; Removing said sacrificial oxide over S/D; Depositing a conformal layer of refractory metal; Annealing to form silicides on exposed silicon in gate and S/D; and Stripping surplus metal.