Patent ID: 6849511

Claim:
A method for fabricating a semiconductor device comprising the steps of: forming a dummy gate electrode in a first region and a second region on a semiconductor substrate; forming a first insulation film for covering the side wall of the dummy gate electrode on the semiconductor substrate; etching the dummy gate electrode in the first region to form in the first region a first opening down to the semiconductor substrate; forming a second insulation film in the first opening; forming a first gate electrode in the first opening with the second insulation film formed on; etching the dummy gate electrode in the second region to form in the second region a second opening down to the semiconductor substrate; forming a third insulation film in the second opening; forming a second gate electrode which is different from the first gate electrode in the second opening with the third insulation film formed on; removing top parts of the first gate electrode, the third insulation film and the second gate electrodes to form a concavity; and burying in the concavity an interconnection electrode electrically interconnecting the first gate electrode and the second gate electrode.