Patent ID: 7524716

Claim:
A method for fabricating a semiconductor structure, comprising: providing a substrate that has therein a first well of a first conductivity type and a second well of a second conductivity type; forming a first gate structure on the second well; removing a portion of the substrate beside the first gate structure to form a first opening; performing a first epitaxy process with a first mixed gas to form in the first opening a first strained layer comprising silicon and a first IV-group element, wherein the first mixed gas comprises a first gas containing silicon and a second gas containing the first IV-group element and the percentage of the second gas in the first mixed gas is increased with time during the first epitaxy process; and forming a MOS transistor of the second conductivity type on the first well, comprising: forming a second gate structure on the first well; removing a portion of the substrate beside the second gate to form a second opening; and forming a source/drain region of the second conductivity type in the first well around and under the second opening.