Patent ID: 7504339

Claim:
A method of forming a shallow-trench-isolation structure in a silicon integrated-circuit wafer, comprising: a. providing a silicon wafer having a (100) crystallographic top surface and a bottom surface; b. providing a indicating means on the wafer of a [100] crystallographic direction; c. forming an approximately 100 Å thick pad silicon-oxide layer on the top surface; d. forming an approximately 1,200 Å thick silicon-nitride layer on the silicon-oxide layer; e. forming a photo-resist layer on the silicon-nitride layer; f. forming a shallow-trench-isolation (STI) pattern in the photo-resist layer, uncovering a portion of the top surface, the STI pattern having trench-edges aligned, within 10 degrees, to the <100> crystallographic directions of the silicon wafer; g. etching a portion of the silicon-nitride layer uncovered by the STI pattern, uncovering a portion of the pad silicon-oxide layer; h. etching the portion of the pad silicon-oxide layer uncovered by the nitride layer, uncovering a portion of the silicon wafer; i. removing the photo-resist layer from the surface of the wafer; j. etching the portion of the silicon wafer uncovered by the pad silicon-dioxide layer to form a trench with sidewalls, a portion of the sidewall near the top surface is within 15 degrees of being perpendicular to the top wafer-surface; k. removing a portion of the pad oxide layer to uncover a portion of the silicon surface near the sidewall by dipping the wafer in dilute hydro-fluoric acid; l. growing a silicon-dioxide-liner layer on the uncovered silicon top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the growth being in a oxidation furnace at about 850° C., the liner-oxide layer at the corner being over 50% thicker than at the sidewall adjacent to the corners; and m. filling the trench with silicon dioxide material.