Patent ID: 6897800

Claim:
An analog demultiplexer comprising: an input amplifier (A 1 ) having an inverting (−) input, a non-inverting (+) input and an output; output amplifiers (AMP 1 -AMP N ), each having an inverting (−) input, a non-inverting (+) input and an output, feedback capacitors (C 1 -C N ), each feedback capacitor connecting the inverting (−) input of one of the output amplifiers to its output; a first input capacitor having a first terminal, and having a second terminal connected to the non-inverting (+) input of the input amplifier (A 1 ); a second input capacitor having a first terminal, and having a second terminal connected to the inverting (−) input of the input amplifier (A 1 ); output feedback switches (S 2a , S 2b , etc.), each of the output feedback switches selectively connecting an output of one of the output amplifiers (AMP 1 -AMP N ) and the first terminal of the first input capacitor (C S1 ); amplifier connection switches (S 1a , S 1b , etc.), each of the amplifier connection switches selectively connecting the output of the input amplifier (A 1 ) and the inverting (−) input of one of the output amplifiers (AMP 1 -AMP N ); an input amplifier feedback switch (S 50 ) selectively connecting the inverting (−) input and output of the input amplifier (A 1 ); a reference connection switch (S 40 ) selectively connecting the non-inverting (+) input of the input amplifier (A 1 ) to a voltage reference supply (V REF ); a first input connection switch (S 30 ) for selectively connecting an input of the analog demultiplexer to the first terminal of the first input capacitor (C S1 ); and a second input connection switch (S 35 ) for selectively connecting the input of the analog demultiplexer to the first terminal of the second input capacitor (C S2 ).