Patent ID: 6996019

Claim:
A semiconductor device comprising: a sense amplifier which senses a voltage difference between a bit line and a complementary bit line; a dummy memory cell array which comprises a first dummy bit line and a first complementary dummy bit line; a second dummy bit line the voltage of which drops due to an off current; and a sense amplifier driver which buffers a clock signal and generates a sense amplifier enable signal for enabling the sense amplifier, the sense amplifier driver comprising: a plurality of inverters which are connected in series; a first power supply circuit which supplies a power supply voltage to the first complementary dummy bit line based on the voltage of the second dummy bit line; and a discharge circuit which discharges the first complementary dummy bit line to a ground voltage in response to a complementary clock signal, wherein at least a first inverter of the inverters generates a signal that swings between the voltage of the first dummy bit line and the ground voltage, and the second inverter inverts the output signal of the first inverter, an input terminal of the second inverter is connected to an output terminal of the first inverter, and an output terminal of the second inverter is connected to the first dummy bit line.