Patent ID: 7187590

Claim:
A method for operating a charge trapping memory cell, the memory cell having a first channel terminal acting as a drain or source, a second channel terminal acting as a source or drain, a charge trapping structure and a gate terminal, the method comprising: establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a threshold voltage for the cell above a high state threshold; and establishing a low threshold state in the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell below a specified value for the low threshold state, by applying a bias procedure including a first stage which reduces negative charge in the charge trapping structure at a rate responsive to the amount of negative charge in the charge trapping structure when the amount of negative charge in the charge trapping structure is above the low state threshold, and a second stage which increases negative charge in the charge trapping structure pulse when the amount of negative charge in the charge trapping structure is below the low state threshold, causing convergence of the threshold voltage in the low threshold state toward the specified value.