Patent ID: 7138722

Claim:
A semiconductor device comprising: an insulating base having a first surface and a second surface opposite to said first surface; a first semiconductor chip having a central processing unit and first connection terminals formed on a main surface thereof, said first semiconductor chip being disposed on said first surface of said insulating base; a second semiconductor chip having a memory circuit and second connection terminals formed on a main surface thereof, said second semiconductor chip being stacked on said first semiconductor chip; bump electrodes disposed on said second surface of said insulating base; first conductors electrically connected to second conductors so as to electrically connect said first connection terminals of said first semiconductor chip with said bump electrodes; third conductors electrically connected to said second conductors so as to electrically connect said second connection terminals of said second semiconductor chip with said bump electrodes; and a mold resin sealing said first and second semiconductor chips; wherein a total number of said first connection terminals of said first semiconductor chip is larger than that of said second connection terminals of said second semiconductor chip.