Patent ID: 6841985

Claim:
A circuit for measuring on-chip cycle-to-cycle jitter comprising: a) a programmable delay line with an input, an output, and control inputs; b) a programmable phase comparator with a first input, a second input, a programming input, a first output, and a second output; c) a first counter with an input and an output; d) a second counter with an input and an output; e) wherein a clock signal is connected to the input of the programmable delay line and to the first input of the programmable phase comparator; f) wherein the delayed clock signal of the programmable delay line is connected to the second input of the programmable phase comparator; g) wherein the first output of the programmable phase comparator is connected to the input of the first counter; h) wherein the second output of the programmable phase comparator is connected to the input of the second counter; i) such that the first counter counts the number of times the time difference between the period of the clock signal and the period of delayed clock signal is a positive value larger than a dead zone value programmed by the programmable phase comparator; j) such that the second counter counts the number of times the time difference between the period of the clock signal and the period of the delayed clock signal is a negative value whose absolute value is larger than a dead zone value programmed by the programmable phase comparator.