Patent ID: 7944298

Claim:
An amplifier having a first differential input node and a second differential input node, the amplifier comprising: a first transistor biased in a saturation region, wherein a gate of the first transistor is coupled to the first differential input node; a second transistor biased in the saturation region, wherein a gate of the second transistor is coupled to the second differential input node; a third transistor biased in a sub-threshold region, the third transistor having a gate that is capacitively coupled to a drain of the second transistor, wherein a first cancel signal on a drain of the third transistor cancels at least a part of a first distortion signal generated by the first transistor; and a fourth transistor biased in the sub-threshold region, the fourth transistor having a gate that is capacitively coupled to a drain of the first transistor, wherein a second cancel signal on a drain of the fourth transistor cancels at least a part of a second distortion signal generated by the second transistor.