Patent ID: 7139213

Claim:
A memory integrated circuit comprising: a plurality of independently accessible memory banks, wherein each of said plurality of independently accessible memory banks is associated with a sense amplifier, wherein said plurality of independently accessible memory banks are sequentially cycled for one of a READ and a WRITE at a system clock frequency; a read bus connected to each of said sense amplifiers associated with each of said plurality of independently accessible memory banks, wherein said read bus is configured to select one of said plurality of independently accessible memory banks to read; a write bus connected to each of said sense amplifiers associated with each of said plurality of independently accessible memory banks, wherein said write bus is configured to select one of said plurality of independently accessible memory banks to write, wherein said write bus is independent of said read bus; wherein the read bus and the write bus further operate to permit concurrent selective read and write functionality; and wherein a first bank of said plurality of independently accessible memory banks is read from and a second bank of said plurality of independently accessible memory banks is written to simultaneously.