Patent ID: 7352642

Claim:
A semiconductor memory device comprising: a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region; a memory cell array including a plurality of the memory cells; word lines connected to the memory cells arranged in rows of the memory cell array; a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines; an adder incrementing the number of times of activation of one of the word lines, the number of times of activation being read from the counter cell array in read operation of the data from the memory cell or in write operation of the data to the memory cell; a counter buffer circuit temporarily storing the number of times of activation of the word line and writing back the incremented number of times of activation of the word line to the counter cell array; a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation of the word line reaches a predetermined value; data bit lines connected to the memory cells in columns of the memory cell array; a data sense amplifier provided to correspond to the data bit lines and detecting data of the memory cell; a data buffer circuit provided to correspond to the data sense amplifier and amplifying the data detected by the data sense amplifier; a counter bit line connected to the counter cell in a column of the counter cell array; and a counter sense amplifier provided to correspond to the counter bit line and detects the data of the counter cell.