Patent ID: 7089408

Claim:
A processor having data and instruction storage, the processor being one of a plurality of processors in a multiprocessor system (MP) supporting a instruction set architecture in which the storage consistency provides instruction data operands to appear to have been accessed in sequential program execution order as observed by all sequential programs executing in the system, the processor comprising: means to re-fetch operand data that may have been returned out of order with respect to sequential program execution after cache line invalidation in the multiprocessor system that does not require the currently executing instruction to be killed and start execution again; operand fetch logic for making data operand fetch requests based on sequential program execution order and is configured to maintain information including the cache line address and offset in the cache line that is indicative of where the operand data is fetched from in storage to support operand data re-fetch at a time after the operand data has been invalidated and starting at a point past the beginning of the data operand; a cache storage for returning instruction data operands to an operand buffer out of order from that of the data operand fetch request order based on sequential program execution that also supports cache line invalidation due to storage update from a single or plurality of processors in the multiprocessor system that is also configured to maintain information about which cache line each eight byte block called a doubleword of operand data came from in order to indicate to the operand buffer when a given doubleword has been invalidated in the cache storage; and an operand buffer configured with operand buffer logic, the operand buffer logic configured to maintain information about the invalidation state of each operand buffer, which holds up to one doubleword of operand data, and the current point of execution in the data operand of the instruction currently executing and is configured to detect and signal which operand buffer needs to begin the operand re-fetch for a point where the data invalidation is detected to support architecture data consistency; wherein the providing operand re-fetch is configured for an instruction having operand longer that eight bytes in length.