Patent ID: 7689809

Claim:
A system, comprising: a master processor comprising first storage operable to maintain a first plurality of variables defining a state of the master processor, the first plurality of variables comprising a first return address; a slave processor comprising second storage operable to maintain a second plurality of variables defining a state of the slave processor, the second plurality of variables comprising a second return address; and a buffer memory, wherein the system is configured to perform, responsive to an interrupt or exception occurring in a parallel mode of operation wherein data are processed by the master processor and the slave processor, the steps of: saving at least a portion of the first plurality of variables and the second plurality of variables to the buffer memory and switching the system to a serial mode of operation wherein data are processed by the master processor; responsive to the interrupt or exception occurring in the slave processor, setting at least one of the first plurality of variables in the first storage to a value of at least one of the second plurality of variables in the second storage; and responsive to the interrupt or exception occurring in the master processor, saving the first return address and the second plurality of variables to the buffer memory and replacing the first return address with an address of a trampoline instruction and executing the trampoline instruction to perform the steps of switching the system to the parallel mode of operation and reading the second plurality of variables and the first return address from the buffer memory.