Patent ID: 6953719

Claim:
A process comprising: forming an n-type and p-type translator upon a semiconductor substrate, the n-type and p-type transistors comprising n-type and p-type polysilicon gates, respectively forming ILD 0 on top of the n-type and p-type transistors: etching the n-type polysillcon gate to form a first trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on the bottom of the first trench; depositing n-type metal into the first trench, wherein the n-type metal gate is to be doped by implanting n-type material after the metal gate has been deposited in the first trench; removing excess n-type gate material to expose the top of the n-type metal gate and the p-type polysilicon gate; etching the p-type polysilicon gate to form a second trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on the bottom of the second trench; depositing a p-type metal gate within the second trench; removing excess n-type gate material to expose the top of the n-type metal gate and the p-type metal gate.