Patent ID: 7080001

Claim:
A data processing system comprising: a central processing unit (CPU); a memory; an interface for transmitting and receiving data to and from external devices; a bus for connecting said CPU, memory, and interface; and a clock monitoring circuit for monitoring period of an operation clock signal of said CPU to stop operations of said CPU when the period of said operation clock signal goes out of a predetermined allowable range, wherein said clock monitoring circuit includes: a first pulse width detecting circuit for generating a first voltage depending on a pulse width of said operation clock signal; a discriminating circuit for discriminating the first voltage generated by said first pulse width detecting circuit with a predetermined threshold voltage; and a control circuit for detecting an output of said discriminating circuit in response to rise and fall of said clock signal and generating a signal to stop the operations of said CPU based on a result of detection of said output; and wherein said clock monitoring circuit includes a logical inverting circuit for inverting logic of outputs of said discriminating circuit, and said first pulse width detecting circuit includes a first flip-flop circuit for latching outputs of said discriminating circuit in a timing of rise or fall of the clock signal and a second flip-flop circuit for latching outputs of said logical inverting circuit in the timing of fall or rise of the clock signal, and wherein said signal generated by said control circuit is a reset signal for resetting operations of said CPU.