Patent ID: 7198980

Claim:
A method for assembling a multidie semiconductor device package, comprising: providing an interposer with a substantially planar substrate and a receptacle formed substantially through the substrate, the substrate having an upper surface and a lower surface, at least the upper surface having conductors thereon; positioning at least one first-level semiconductor device within the receptacle, a backside of the at least one first-level semiconductor device being substantially coplanar with the lower surface of the substrate or located within a plane which extends through the substrate an interstitial space remaining at least between peripheral edges of the at least one first-level semiconductor device and the substrate; positioning a second-level semiconductor device above the upper surface of the substrate, a portion of the second-level semiconductor device superimposed with the upper surface of the substrate; electrically connecting the at least one first-level semiconductor device to at least the conductors on the upper surface of the substrate by first-level conductive members that include laterally extending portions that are at least partially carried by a surface of the second-level semiconductor device; and electrically connecting the second-level semiconductor device to the conductors on the upper surface of the substrate by second-level conductive members.