Patent ID: 7991984

Claim:
A loop control system comprising: an instruction register operable to store an instruction word comprising a plurality of loop flags, each loop flag consisting of one bit, each loop flag associated with a different one of a plurality of nested program loops; a loop counter associated with each loop flag and operable to store and compute a number of times a program loop is to be executed, wherein each loop counter is further configured to store a Viterbi block size used during a Viterbi decoding operation that represents the number of times the program loop is to be executed; a start address register associated with each loop flag and operable to store a program loop starting address when the associated loop flag indicates a loop beginning, and wherein the program loop starting address comprises an address of an instruction word; and an end address register associated with each loop flag and operable to store a program loop ending address when the associated loop flag indicates a loop ending, and wherein the program loop ending address comprises the address of an instruction word, wherein each loop flag in the instruction word is assigned a first value when the instruction word is a beginning instruction or end instruction of the program loop associated with the loop flag and is assigned a second value when the instruction word is a middle instruction of the program loop associated with the loop flag.