Patent ID: 7821830

Claim:
An apparatus comprising: a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including a plurality of interleave groups of regular columns and a plurality of redundancy interleave groups of redundant columns; a plurality of interleave groups of data latches, each of the interleave groups of data latches being configured to store data read from a respective one interleave group of regular columns; a plurality of redundancy interleave groups of redundant data latches, each of the redundancy interleave groups of redundant data latches being configured to store data read from a respective one redundancy interleave group of redundant columns; and a multiplexer configured to selectively output data from the plurality of interleave groups of data latches and the plurality of redundancy interleave groups of redundant data latches, wherein the apparatus is configured to assign a redundant column in one of the redundancy interleave groups of redundant columns to replace a defective regular column in any one of the interleave groups of regular columns; wherein the apparatus is further configured to allow switching among two or more interleaved read schemes.