Patent ID: 7312470

Claim:
A thin film transistor array panel comprising: an insulating substrate; a gate wire formed on the insulating substrate and including a gate line, and a gate pad connected to one end of the gate line; a gate insulating layer formed on the insulating substrate while exposing the gate pad and a portion of the gate line close to the gate pad; a semiconductor pattern formed on the gate insulating layer; a data wire formed on the gate insulating layer and including a data line intersecting the gate line, a source electrode projecting from the data line and contacting the semiconductor pattern, a drain electrode facing the source electrodes and contacting the semiconductor pattern, and a data pad connected to one end of the data line; and a passivation layer formed on the gate insulating layer while exposing the data pad and a portion-of the data line close to the data pad, wherein the passivation layer further exposes a portion of the gate insulating layer formed close to the gate pad, and wherein the passivation layer comprises organic material.