Patent ID: 7117413

Claim:
A wrapped core linking module for accessing a system on chip test, comprising: a link control register that stores a link control configuration between cores in a scan path of the system on chip according to control signals applied from an outside boundary; a link control register controller that controls a shift and update link configuration by activating said link control register; a switch that switches the scan path between wrapped cores based on the link control configuration of said link control register; and an output logic that connects said link control register to a test data out (TDO) of a chip in case of testing on chip or cores of system on chip, the output logic comprising a flag register configured to load a flag bit, wherein said switch sets a test mode sequence (TMS) gate as “0” for controlled cores in scan path and maintains controlled cores as a RunTest/Idle state until returning the controlled cores onto the scan path, and the wrapped core linking module is configured to allow testing interconnections among system on chip and internal core boundaries.