Patent ID: 7769989

Claim:
A processor, comprising: hardware memory that stores audio data; an addressing unit that supplies an access address to the hardware memory and a first state signal indicative of whether the audio data associated with the access address is stereo audio data or mono audio data, and a second state signal indicative of whether the audio data associated with the access address is L-bits or 2L-bits in length; a first selection device that receives the audio data associated with the access address and the second state signal and outputs either most significant bits or least significant bits of the audio data associated with the access address as a first selection device output signal in response to the second state signal; a second selection device that receives the audio data associated with the access address and the first and second state signals, and outputs either the most significant bits or the least significant bits of the audio data associated with the access address as a second selection device output signal in response to a first Boolean combination of the first and second state signals; a first arithmetic logic unit that receives and processes the first selection device output signal and provides a first ALU output signal; a second arithmetic logic unit that receives and processes the second selection device output signal and provides a second ALU output signal; and means, responsive to the first and second ALU output signals and the first and second state signals, for selectively combining the first and second ALU output signals to provide write data to the hardware memory.