Patent ID: 7130211

Claim:
An interleave control device using a nonvolatile ferroelectric memory, comprising: a single chip FeRAM array comprising a plurality of single banks, wherein the signal chip FeRAM array controls access time differently in each address; a memory interleave controller including: a nonvolatile interleave program register configured to program a code for controlling the interleave using a nonvolatile ferroelectric memory, wherein the nonvolatile ferroelectric memory programs a code for differently controlling a memory interleave operation depending on an access latency time and a restore latency time which are set in a memory interleave region corresponding to lower address bits of row address bits, wherein the nonvolatile interleave program register includes: a program command processor configured to output a command signal for coding a program command in response to a write enable signal, a chip enable signal, an output enable signal and a reset signal; a program register controller configured to logically operate the command signal, input data and a power-up detecting signal, and to output a write control signal and a cell plate signal; and a program register array, including a nonvolatile ferroelectric memory device, configured to output a programmed code signal in response to the write control signal, the cell plate signal, a pull-up enable signal and a pull-down enable signal; and an interleave controller configured to output a control signal for changing an address path of the signal chip FeRAM array depending on the programmed code by the nonvolatile interleave program register; and a bus configured to transfer data between the single chip FeRAM array and the memory interleave controller.