Patent ID: 7678649

Claim:
A method of manufacturing a semiconductor device including a nonvolatile memory cell having a first gate electrode over a first region of a semiconductor substrate and a resistance element over a second region of the semiconductor substrate, comprising: (a) forming a first conductive film over the first and second regions, (b) forming a first insulating film over the first conductive film, (c) patterning the first insulating film and the first conductive film so as to form the first gate electrode over the first region while leaving the first insulating film over the first gate electrode and to form the resistance element over the second region while leaving the first insulating film over the resistance element, (d) after step (c), depositing a second insulating film over the semiconductor substrate, (e) anisotropically etching the first and second insulating films so as to leave the second insulating film over sidewalls of the first gate electrode and the resistance element while removing the first insulating film, (f) performing ion implantation of an impurity into the semiconductor substrate so as to form a first semiconductor region in the first region, (g) forming a third insulating film over the semiconductor substrate, after the step (f), and (h) patterning the third insulating film so as to leave the third insulating film over the first gate electrode and over the first insulating film while partially exposing an area over the resistance element, (i) forming a silicide layer over the first semiconductor region and in the partially exposed area over the resistance element, and (j) forming a fourth insulating film over the semiconductor substrate, the fourth insulating film having an etching selectivity ratio different from that of each of the second and third insulating films.