Patent ID: 7650545

Claim:
A reconfigurable system-on-chip, comprising: a first core having an output line; a reconfigurable logic core (RLC) having an input line and an output line, with the output line of the first core being electrically coupled, via a first switch, to the input line of the RLC; a first multiplexer having first and second inputs and an output, wherein: the output line of the first core is electrically coupled to the first input of the first multiplexer; and the output line of the RLC is electrically coupled to the second input of the first multiplexer; a second core having an input line electrically coupled to the output of the first multiplexer; a second multiplexer having first and second inputs and an output, wherein: the first core has an input line that is electrically coupled to the output of the second multiplexer; the second core has an output line that is electrically coupled to (i) the input line of the RLC via a second switch and (ii) the first input of the second multiplexer; and the output line of the RLC is electrically coupled to the second input of the second multiplexer; and a configuration memory that controls (i) the first multiplexer to selectively couple the input line of the second core to one of the output line of the first core and the output line of the RLC and (ii) the second multiplexer to selectively couple the input line of the first core to one of the output line of the second core and the output line of the RLC.