Patent ID: 8321609

Claim:
A register control circuit, comprising: a first-in-first-out (FIFO) register, having a plurality of record locations and storing a plurality of data into the record locations according to a writing sequence of the data; a first circuit module, coupled to the FIFO register, writing data in the record locations of the FIFO register, and generating and outputting a plurality of write pointers, wherein one of the write pointers corresponds to a record location of a last written data; a second circuit module, coupled to the first circuit module and the FIFO register, receiving the write pointers, and sequentially reading the data stored in the FIFO register according to the write pointers outputted from the first circuit module; and a logic circuit, coupled to the first circuit module and the second circuit module, receiving the write pointers and generating a plurality of read flags, and according to the read flags, turning on a pulse signal of the second circuit module to read the data stored in the FIFO register, and simultaneously receiving a plurality of read ended signals returned from the second circuit module to clear the read flags, wherein when the logic circuit turns on the pulse signal of the second circuit module, the second circuit module reads the data stored in the FIFO register, when the second circuit module has read the data stored in the FIFO register completely, all of the read flags are cleared, and then the logic circuit turns off the pulse signal of the second circuit module until the first circuit module writes new data in the record locations of the FIFO register, wherein the logic circuit comprises: a plurality of flip-flops, each of the flip-flops receiving one of the write pointers outputted from the first circuit module and generating the read flag when receiving the write pointer, wherein the write pointer points to one of the record locations in the FIFO register; wherein each of the flip-flops corresponds to one of the record locations of the FIFO register; and an OR gate, coupled to the flip-flops, receiving the read flags outputted from the flip-flops to generate the read enable signal according to states of the read flags, and outputting the read enable signal to the second circuit module so that the pulse signal of the second circuit module is turned on.