Patent ID: 8575604

Claim:
A semiconductor memory device comprising a memory cell, the memory cell comprising: a first transistor, the first transistor comprising: a first semiconductor layer in which a first impurity region and a second impurity region are formed; a first gate electrode formed over the first semiconductor layer; a first insulating layer formed between the first gate electrode and the first semiconductor layer; and a second insulating layer and a third insulating layer formed on a side wall portion of the first gate electrode; a second transistor, the second transistor comprising: a second semiconductor layer formed on the third insulating layer, wherein the second semiconductor layer is in contact with the first electrode and the first impurity region; a fourth insulating layer on the second semiconductor layer, the fourth insulating layer extending over an upper surface of the first gate electrode; and a second gate electrode formed over the second semiconductor layer with the fourth insulating layer interposed therebetween; and a capacitor comprising the first gate electrode, the fourth insulating layer over the first gate electrode, and an electrode formed over the first gate electrode with a portion of the fourth insulating layer interposed therebetween.