Patent ID: 8115291

Claim:
A semiconductor package comprising: a first substrate including at least one first substrate pad and at least one second substrate pad spaced apart from each other; at least one first semiconductor chip stacked on the first substrate and having a first side surface and a second side surface and including a cell region and a peripheral circuit region; at least one first chip pad on the at least one first semiconductor chip, the at least one first chip pad being arranged adjacent to the first side surface, and on the at least one first substrate pad so as to be electrically connected to the at least one first substrate pad; a second semiconductor chip adjacent to the second side surface and including at least one second chip pad and electrically connected to the at least one second substrate pad; a heat transfer member provided to the first substrate between the at least one first chip and the at least one second substrate pad; and at least one connection terminal on a bottom surface of the first substrate, and electrically connected to the at least one first substrate pad or the at least one second substrate pad, wherein the heat transfer member includes a first heat conduction pattern on a top surface of the first substrate between the second side surface and the at least one second substrate pad, and a second heat conduction pattern in the first substrate and connected to the first heat conduction pattern, and the at least one connection terminal includes a dummy connection terminal electrically insulated from the at least one first substrate pad and the at least one second substrate pad, and the dummy connection terminal is connected to the second heat conduction pattern.