Patent ID: 8198921

Claim:
A dynamic comparator with background offset calibration, comprising: a first input differential pair, comprising two first current branches, wherein one of the two first current branches has a first input referred offset; a second input differential pair, comprising two second current branches, wherein one of the two second current branches has a second input referred offset; a first back-to-back inverter, coupled to the first input differential pair and the second input differential pair, for determining which one of the two first current branches has the first input referred offset in response to a first clock signal and a second clock signal and generating two control signals correspondingly, and for determining which one of the two second current branches has the second input referred offset in response to the first clock signal and a third clock signal and generating another two control signals accordingly; an integrator, coupled to the first back-to-back inverter, for generating two calibration voltages for the first input differential pair in response to the two control signals, so as to calibrate the first input referred offset, and for generating another two calibration voltages for the second input differential pair in response to the another two control signals, so as to calibrate the second input referred offset; and a second back-to-back inverter, coupled to the first input differential pair and the second input differential pair, for determining a difference between four input signals received by the first input differential pair and the second input differential pair after the first input referred offset and the second input referred offset are calibrated in response to the second clock signal, the third clock signal, and a fourth clock signal and outputting two comparison signals accordingly.