Patent ID: 8716748

Claim:
A semiconductor device comprising: a substrate; a semiconductor stacked structure, provided over the substrate, comprising an electron transit layer and an electron supply layer; a gate electrode, a source electrode, and a drain electrode provided over the semiconductor stacked structure; a gate pad, a source pad, and a drain pad provided over the gate electrode, the source electrode, and the drain electrode, and connected to the gate electrode, the source electrode, and the drain electrode, respectively; and a conductive layer, wherein the conductive layer is provided under the gate pad, the source pad, and the drain pad, a distance between the gate pad and the source pad is a distance being capable of adding a gate pad-conductive layer capacitance and a source pad-conductive layer capacitance to a gate-source capacitance, a distance between the gate pad and the drain pad is a distance not being capable of adding a gate pad-conductive layer capacitance and a drain pad-conductive layer capacitance to a gate-drain capacitance, and a value of Cgs/Cgd, where Cgs is the gate-source capacitance and Cgd is the gate-drain capacitance, is set such that a self turn-on which is a phenomenon that a gate voltage exceeds a threshold voltage when a transistor is turned off does not occur.