Patent ID: 7694204

Claim:
An apparatus for detecting errors in a physical interface that facilitates data communications between integrated circuits (“ICs”), the apparatus comprising: a decoder configured to decode a subset of encoded data bits to yield decoded data bits, the subset including less than all of the encoded data bits; a physical interface (“PI”) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits, the physical interface error detection bit being used to determine whether the encoded data bits include at least one erroneous data bit as an error; and an error detector and an error corrector configured to operate within a physical layer, the error detector and error corrector, upon utilizing the physical interface error detection to detect the error within the encoded data bits, to correct the error; wherein the encoded data bits include an embedded asynchronous clock, the asynchronous clock to be utilized to provide clocking for the encoded data bits upon decoding; and wherein the subset of the encoded data bits includes N+m data bits and the decoded data bits include N application data bits, where m represents the number of extra bits used for at least embedding the asynchronous clock and the physical interface error detection bit in the encoded data bits.