Patent ID: 7965552

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array formed of multiple blocks, in which word lines and bit lines are arranged to cross to each other, electrically rewritable and non-volatile memory cells are arranged at respective cross-points of the word lines and the bit lines, and at least a portion of the memory cells arranged along the word line makes one page of simultaneously accessed memory cells in a selected block; a bad block position data register area defined in the memory cell array to store bad block position data; an address decoder circuit configured to select a block in the memory cell array; and bad block flag latches disposed in the address decoder circuit, bad block flags being set in the bad block flag latches in accordance with the bad block position data read out the bad block position data register area, wherein the memory cell array includes a plurality of block sets each including a plurality of the blocks, and wherein the bad block position data in the bad block position data register area are defined by such a bit position assignment scheme that one bit is assigned to one block under the condition that a column address for selecting the bit lines of the bad block position data register area corresponds to a block set, and a bit number of data read out via the bit line selected by the column address corresponds to a block position in the block set.