Patent ID: 7630238

Claim:
A page buffer for an electrically programmable memory including: a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group, at least one read/program unit having a coupling line operatively as sociable with selected memory cells, the read/program unit: being adapted to at least temporarily store data bits read from or to be written into selected memory cells; comprising programming state change enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, wherein said programming state change enabling means comprises: reading means for retrieving, from the selected memory cell, an indication of an existing data value already stored in the second group of data bits; receiving means for receiving an indication of a target data value to be stored in the first group of data bits of the selected memory cell; combining means activatable during a combining phase for combining the indication of the existing data value with the indication of the received target data value, so as to obtain a modified indication corresponding to a target programming state for the memory cell; and conditioning means for causing a potential of the coupling line to take the program enabling potential or the program inhibition potential depending on the modified indication, wherein the combining means includes a coupling electrical path between the reading means and the receiving means, said coupling line being kept isolated from the coupling electrical path during said combining phase, wherein the receiving means includes a first latch for at least temporarily storing the indication of the target data value, for providing the stored indication to a first circuit node and for providing the logic complement of the stored indication to a second circuit node, and wherein the reading means further includes a second latch for at least temporarily storing the indication of the existing data value retrieved from the selected memory cell, and providing it to a third circuit node.