Patent ID: 8208340

Claim:
A latency counter that counts a latency of an internal command, the latency counter comprising: a counter circuit that counts a clock signal; and a point-shift FIFO circuit, wherein the point-shift FIFO circuit includes: a plurality of first latch circuits that latch the internal command; an input selecting circuit that supplies the internal command to one of a plurality of signal paths based on a count value of the counter circuit; a shift circuit that supplies the internal command on one of the signal paths to a predetermined one of the first latch circuits based on a preset correspondence relation between the signal paths and the first latch circuits; and an output selecting circuit that outputs the internal command stored in one of the first latch circuits based on the count value of the counter circuit, wherein the input selecting circuit includes a plurality of timing control circuits, each of the timing control circuits being allocated to an associated one of the signal paths, and each of the timing control circuits includes: a second latch circuit that latches the internal command; and a first gate circuit that outputs the internal command stored in the second latch circuit to an associated one of the signal paths in response to activation of a corresponding count value of the counter circuit, and wherein each of the second latch circuits is an SR latch circuit that is set in response to activation of the internal command and is reset in response to deactivation of the corresponding count value of the counter circuit.