Patent ID: 8010802

Claim:
A cryptographic device having a session memory bus, comprising: an external session memory for storing cryptographic information on respective sessions; a cryptographic processor for encrypting or decrypting input data using the cryptographic information; an external session memory bus connected to the external session memory and the cryptographic processor; and a Central Processing Unit (CPU) for transferring and receiving data to and from the external session memory via the cryptographic processor, wherein the cryptographic processor comprises: an internal session memory for storing cryptographic information on the respective sessions; and an internal session memory bus connected to the internal session memory, wherein the cryptographic processor comprises: an Input/Output (I/O) interface for receiving the input data from the outside of the cryptographic processor and outputting encrypted or decrypted data; a cryptographic algorithm executer for encrypting or decrypting the input data using cryptographic information of a current session stored in the external session memory or the internal session memory; a CPU session memory buffer for receiving data from the CPU to transfer the data to the external session memory or the internal session memory, and transferring data of the external session memory or the internal session memory to the CPU; an external session memory bus arbiter for receiving a bus request from the cryptographic algorithm executer or the CPU session memory buffer, and allocating the external session memory bus according to the bus request; and an internal session memory bus arbiter for receiving a bus request from the cryptographic algorithm executer or the CPU session memory buffer, and allocating the internal session memory bus according to the bus request.