Patent ID: 7439099

Claim:
A process for fabricating an integrated circuit package, comprising: providing a substrate having opposing first and second surfaces and conductive traces extending therebetween, the substrate having a cavity therein; providing a ground ring on an inside of the cavity, the ground ring comprising, a first ground ring portion, accessible from the first surface of the substrate, a second ground ring portion, accessible from the second surface of the substrate, and a ground ring trace portion, to electrically connect the first ground ring portion to the second ground ring portion; fixing a heat slug in the form of a substantially flat plate to said first surface of said substrate, such that said heat slug spans said cavity; mounting a semiconductor die to said heat slug, said semiconductor die being disposed in said cavity; wire bonding said semiconductor die to ones of said conductive traces at said second surface of said substrate; encapsulating said wire bonds and said semiconductor die in an encapsulating material; and forming a ball grid array on said first surface of said substrate such that bumps of said ball grid array are in electrical connection with ones of said conductive traces; wherein the heat slug is fixed to the first surface of the substrate on which said ball grid array is formed; and wherein said substrate is substantially the same thickness as said semiconductor die.