Patent ID: 8108643

Claim:
A semiconductor memory system having a loop forward architecture, a command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to a first memory chip, to a second memory chip, to a third memory chip and to a fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller, the semiconductor memory system comprising: wherein each memory chip includes a rank select switching section; and with each command one of four memory chips is accessed for data processing, while the other three of the four memory chips have only to fulfill a simple re-drive of command/address/write data stream and read data stream; and a rank select signal not embedded in the frame from the memory controller, transferred to each memory chip at the rank select switching section receiving the separately transferred rank select signal and decoding therefrom signal states which are used to select whether a command/address/write data stream signal stream is to be sent to an own memory core and processed or re-driven to a next memory chip; command/address/write data stream input and output means, respectively arranged for receiving through a first command/address/write data stream signal lane a command, address and write data stream in form of signal frames according to a predefined protocol and driven from an external memory controller or re-driven from one or more preceding memory chip(s) and for transmitting through a second command/address/write data stream signal lane a command, address and write data stream to one or more memory chips succeeding in the propagation direction of the command, address and write data stream; a read data stream input and output means, respectively arranged for receiving through a first read data stream signal lane a read data signal stream in form of signal frames according to a predefined protocol and originating or re-driven from one or more preceding memory chip(s), and for transmitting through a second read data stream signal lane a read data signal stream originating from the own memory core and/or originating or re-driven from one or more memory chip(s) preceding in the propagation direction of the read signal stream either to the memory controller or to one or more memory chip(s) succeeding in the propagation direction of the read signal stream; wherein the memory interface further comprises register means for registering a memory chip number sent in a set-up procedure from the memory controller through the first command/address/write data stream signal lane to the memory chip; and the rank select decoder is adapted to decode the rank select signal according to the registered memory chip number.