Patent ID: 7593268

Claim:
A method for operating a non-volatile memory switch in an FPGA integrated circuit including a first p-well region coupled to ground; an n-channel MOS transistor disposed in the first p-well region, a second p-well region disposed within an n-well and electrically isolated from the first p-well region, and a non-volatile memory switch disposed in the second p-well region, the non-volatile memory switch having a source/drain region coupled to a drain of the n-channel MOS transistor, a source coupled to the second p-well, and a gate, the method comprising; coupling the second p-well to ground when the integrated circuit is in an operating mode and to V CC when the integrated circuit is in a mode in which the non-volatile memory switch is to be erased; and coupling the n-well containing the second p-well to a potential of at least V CC when the integrated circuit is in a mode in which the non-volatile memory switch is to be erased.