Patent ID: 7233179

Claim:
An output stage interface circuit for interfacing with a data bus, the interface circuit comprising: a first switch element coupled between a first rail and a data output terminal, the first rail being adapted for coupling to one of a high and a low voltage of a power supply, and the data output terminal being adapted for coupling to the data bus, the first switch element being responsive to a first control signal for selectively coupling the data output terminal to the first rail for determining one of a logic high state and a logic low state of the data output terminal during data output; and a second switch element coupled between a second rail and the data output terminal, the second rail being adapted for coupling to the other of the high and the low voltage of the power supply, the second switch element comprising a main MOS device having a gate for receiving a second control signal and being responsive to the second control signal for selectively coupling the data output terminal to the second rail for determining the other of the logic high state and the logic low state of the data output terminal during data output, the main MOS device having an independently configurable back gate selectively and alternately coupleable to one of the second rail and the data output terminal, the back gate of the main MOS device being coupled to the second rail in response to the voltage on the data output terminal being in a first state, and being coupled to the data output terminal in response to the voltage on the data output terminal being pulled by the voltage on the data bus to a second state from the first state across a voltage reference to lie to a side of the voltage reference opposite to that to which the voltage on the first rail lies for preventing current being conducted through parasitic components in the main MOS device coupled through the main MOS device to the data output terminal, thereby preventing current being sourced from one of the interface circuit and the data bus to the other of the interface circuit and the data bus through the said parasitic components in the main MOS device, and the gate of the main MOS device being coupleable to the data output terminal in response to the voltage on the data output terminal being pulled to the second state.