Patent ID: 7573095

Claim:
A semiconductor structure comprising: a semiconductor substrate comprising a first region and a second region; a memory cell in the first region, the memory cell comprising: a first gate electrode over the semiconductor substrate; a first gate spacer on a sidewall of the first gate electrode, wherein the first gate spacer comprises a storage on a tunneling layer; a first lightly doped source or drain (LDD) region in the semiconductor substrate and having at least a portion under the first gate spacer; and a first pocket region in the semiconductor substrate and adjacent the first LDD region; a logic MOS device in the second region, the logic MOS device comprising: a second gate electrode over the semiconductor substrate; a second gate spacer on a sidewall of the second gate electrode; a second LDD region in the semiconductor substrate and having at least a portion under the second gate spacer; and a second pocket region in the semiconductor substrate and adjacent the second LDD region, wherein at least one of the first LDD region and the first pocket region has a higher impurity concentration than an impurity concentration of the respective second LDD region and the second pocket region.