Patent ID: 7433911

Claim:
A data processing apparatus for adding n-bit significands of first and second floating point operands to produce an n-bit result, the data processing apparatus comprising: determination logic operable to determine the larger operand of the first and second operands; alignment logic operable to align the n-bit significand of the smaller operand with the n-bit significand of the larger operand; first adder logic operable to perform a first sum operation in order to generate a first rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition, the first adder logic comprising a single level of adder logic; second adder logic operable to perform a second sum operation in order to generate a second rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a second predetermined rounding position appropriate for an overflow condition, the second adder logic comprising a single level of adder logic; and selector logic operable to derive the n-bit result from either the first rounded result or the second rounded result.