Patent ID: 6925002

Claim:
A semiconductor memory having mutually crossing word and bit lines at which magnetoresistive memory cells are arranged, comprising: a first magnetic layer having a first magnetization axis; a second magnetic layer having a second magnetization axis, wherein the first magnetic layer is formed from hard ferromagnetic material, the second magnetic layer is formed from soft ferromagnetic material, and the first and the second magnetization axes intersect if projected into a plane spanned by the word and the bit line; an insulating layer arranged in between the first and second magnetic layers; and a circuit arrangement for evaluating the information content of at least one of the magnetoresistive memory cells, the circuit arrangement including an AC current source connected to the memory cell via a word line; and a voltage measuring device measuring the voltage to the word line and to the memory cell, via a bit line, the memory cell being connected with a magnetoresistive resistance between the word and the bit line.