Patent ID: 8144534

Claim:
A memory device, comprising: a memory array comprising a plurality of main sections of memory cells; a plurality of digit lines in each main section, at least one digit line being provided for each row of memory cells in the main section, each of the digit lines being configured to be selectively coupled to the memory cells in a respective one of the rows; a plurality of sense amplifiers, each of the sense amplifiers being coupled to a respective pair of the digit lines; a plurality of sets of input/output lines, each of the input/output lines in each set being configured to be coupled to a respective plurality of the sense amplifiers; a redundant section of memory cells arranged in rows and columns, the number of memory cells in the redundant section corresponding in number to the number of memory cells in each of the main sections; a plurality of digit lines in the redundant section, at least one digit line being provided for each row of memory cells in the redundant section, each of the digit lines being configured to be selectively coupled to the memory cells in a respective row in the redundant section; a plurality of redundant sense amplifiers, each of is the redundant sense amplifiers being coupled to a respective digit line in the redundant section; a plurality of redundant input/output lines, each of the input/output lines being configured to be coupled to a respective plurality of the redundant sense amplifiers; and an addressing circuit coupled to the memory array and the redundant section, the addressing circuit being configured to receive an address and to compare the received address with a record of a section determined to be defective, the addressing circuit being configured in the event of a match to redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.