Patent ID: 7958290

Claim:
An apparatus comprising: a plurality of bus devices, each bus device coupled to a first bus and to a corresponding one of a plurality of sets of output signal lines to receive signals therefrom, the signals independent of and unsynchronized to the first bus; a plurality of first shift registers, each coupled to at least one other first shift register by a point-to-point interconnect, and each to provide the corresponding signals to the set of output signal lines coupled to the corresponding bus device; the first bus coupled to each of the plurality of bus devices; and bus logic having a first bus interface coupled to the first bus and having an output shift register coupled to a first one of the plurality of first shift registers to transmit bit values unsynchronized to activity on the first bus, the output shift register having a plurality of bit positions to store bit values of states to be driven onto the sets of output signal lines, and when a number of the plurality of bus devices is less than a supported number of bus devices for the bus logic, the bit values of the bit positions for the plurality of bus devices are the last bit values to be transmitted from the output shift register.