Patent ID: 7898306

Claim:
A phase locked loop, comprising: a multiphase voltage controlled oscillator (VCO) operable to generate an output signal containing one or more phase signals; a programmable divider operable to divide a frequency of the output signal of the multiphase VCO to produce a divided frequency output signal; and a fractional divider to fractionally divide an input phase signal, the fractional divider including an integer divider operable to receive the input phase signal and divide the input phase signal in accordance with an integer divisor to produce a divided signal as an input to the multiphase VCO, and a phase interpolator in series with the integer divider, the phase interpolator operable to select a phase signal from among the one or more phase signals output by the multiphase VCO, the selected phase signal having a phase shifted relative to the divided frequency output signal of the programmable divider such that the phase interpolator produces an interpolated output signal having a desired frequency resolution.