Patent ID: 8578222

Claim:
A method comprising: using a (Serializer/Deserializer) SerDes circuit in a communication of information between a first SerDes device and a second SerDes device across a SerDes link comprising a first SerDes link and a second SerDes link, wherein the SerDes circuit is located within the first SerDes device and is taken from the group consisting of: a SerDes transmitter that transmits information across the first SerDes link, and a SerDes receiver that receives information from the second SerDes link; and controlling a power consumption of the SerDes receiver in the first SerDes device such that an error rate for transmissions from the second SerDes device to the first SerDes device across the first SerDes link is substantially maintained between a lower error rate bound and an upper error rate bound, and when the error rate for transmissions from the second SerDes device to the first SerDes device remains outside the lower error rate bound and the upper error rate bound, the first SerDes device is configured to transmit an indication to the second SerDes device to alter power consumption in the second SerDes device.