Patent ID: 7085971

Claim:
A method for identifying a failed memory element within an integrated circuit memory and for repairing said integrated circuit memory, comprising: providing an integrated circuit memory having a plurality of banks; automatically identifying and recording locations of failures within said integrated circuit memory by storing data bits and error correction code (“ECC”) check bits to individual locations of said integrated circuit memory; thereafter retrieving data bits and ECC check bits from said individual locations; recording at least single-bit failure locations in said integrated circuit memory based on ECC processing said retrieved data bits together with said retrieved ECC check bits; based on said recorded failure locations, using first logic circuits within said integrated circuit to automatically identify a failed memory element in one bank of said plurality of banks; and asserting a busy signal for said one bank; and while asserting said busy signal and servicing at least one of read or write access requests to banks of said plurality of banks other than said one bank, electrically activating fusible elements within said integrated circuit including elements selected from the group consisting of fuses and antifuses, to electrically alter circuit connections of said integrated circuit memory to automatically replace said failed memory element in said one bank with a redundancy element.