Patent ID: 8841952

Claim:
A data retention flip-flop, comprising: a first multiplexer having a first input terminal that receives a data input signal, a second input terminal that receives a scan input signal, and a select terminal that receives a test enable signal, wherein the first multiplexer outputs the data input signal at an output terminal thereof in a normal operation mode of the data retention flip-flop; a master latch having a data input terminal connected to the output terminal of the first multiplexer for receiving the data input signal, and a clock input terminal that receives a clock signal, wherein the master latch outputs the data input signal at an output terminal thereof at a first edge of the clock signal in the normal operation mode; a slave latch having a data input terminal connected to the output terminal of the master latch for receiving the data input signal, and a clock input terminal that receives the clock signal, wherein the slave latch outputs the data input signal at an output terminal thereof at the first edge of the clock signal in the normal operation mode; a data retention latch having a data input terminal connected to the output terminal of the slave latch for receiving the data input signal and a clock input terminal that receives an isolation (ISO) signal, wherein the ISO signal is asserted when the data retention flip-flop transitions from the normal operation mode to a scan testing mode such that the data retention latch stores the data input signal during the scan testing mode; and a second multiplexer having a first input terminal connected to an output terminal of the data retention latch for receiving the stored data input signal, a second input terminal connected to the output terminal of the slave latch for receiving the data input signal, and a select terminal that receives a propagation (PROP) signal, wherein the second multiplexer outputs the stored data input signal when the data retention flip-flop transitions from the scan testing mode to a reload mode, and outputs the data input signal during the normal operation mode.