Patent ID: 7342275

Claim:
A semiconductor device comprising: a semiconductor substrate; wirings formed on the substrate and separated from each other, each of the wirings including a first conductive layer pattern and an insulating mask layer pattern formed on the first conductive layer pattern; insulating spacers formed on sidewalls of the wirings; a self-aligned contact pad including a second conductive layer, the self-aligned contact pad being in contact with surfaces of the insulating spacers to fill a gap between the wirings; an interlayer dielectric layer formed on the contact pad, the wirings, and the substrate, the interlayer dielectric layer including a contact hole defined therein, wherein a sidewall of the contact hole extends from an upper surface of the insulating mask layer pattern to a height above the upper surface of the insulating mask layer pattern; and a selective epitaxial silicon layer formed within the contact hole, on the contact pad and covering the insulating mask layer pattern, wherein the sidewall of the contact hole is laterally adjacent to a lowermost portion of the selective epitaxial silicon layer covering the insulating mask layer pattern, and wherein an uppermost surface of the selective epitaxial silicon layer is lower than an uppermost surface of the interlayer dielectric.