Patent ID: 7834395

Claim:
An integrated circuit comprising: a field-effect transistor comprising: a source region, a drain region, and a channel region; a gate electrode having a lower edge below a lower edge of at least one of the source and drain regions; a gate dielectric arranged between the channel region and the gate electrode; a first insulator structure arranged between the gate electrode and at least a section of the source region, the first insulator structure not being present between the gate electrode and the drain region; and a second insulator structure arranged between the gate electrode and only at a section of the drain region, the second insulator structure not being present between the gate electrode and the source region, wherein at least one of the first and second insulator structures is structurally different from the gate dielectric and the first and the second insulator structures are asymmetric to each other with respect to a plane perpendicular to a line connecting the source and drain regions, and wherein the first insulator structure extends to a first depth within a semiconductor substrate and the second insulator structure extends to a second depth within the semiconductor substrate, the second depth differing from the first depth by at least 10 percent.