Patent ID: 7940589

Claim:
A bit line sense amplifier circuit for use in a semiconductor memory device, wherein the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a time when a sense amplifier enable signal to enable the bit line sense amplifier circuit is applied thereto, wherein the bit line sense amplifier circuit comprises: a sense amplifier for performing a sensing and amplification operation of data in response to the sense amplifier enable signal; and a sense amplifier controller for controlling a precharge state of the sense amplifier in response to a sense amplifier precharge signal, and wherein the sense amplifier comprises: a PMOS sense amplifier unit including a plurality of PMOS transistors cross-coupled with one another to amplify data; an NMOS sense amplifier unit including a plurality of NMOS transistors cross-coupled with one another to amplify data; and a PMOS transistor and an NMOS transistor for receiving respective sense amplifier enable signals to enable the respective PMOS and NMOS sense amplifier units.