Patent ID: 7017090

Claim:
A semiconductor module for operating at a second speed faster than a first speed and for shifting of semiconductor memory devices to an individual-device test mode, comprising: a PLL circuit for generating a clock signal of a frequency for achieving said second speed; a registered buffer circuit for converting an externally supplied input signal to an input signal formed of an internally used voltage level, and outputting the converted input signal in synchronization with said clock signal; a plurality of semiconductor memory devices for receiving said converted input signal from said registered buffer circuit and operating in synchronization with said clock signal; and a test mode entry circuit for producing, in accordance with a request for a shift to the test mode, a test mode shift signal for shifting said semiconductor memory devices to the test mode, said test mode being a test mode used for individually testing each of said plurality of semiconductor memory devices, and applying the produced test mode shift signal to each of said plurality of semiconductor memory devices; wherein each of said plurality of semiconductor memory devices includes a memory cell array including a plurality of memory cells, a peripheral circuit for inputting/outputting data to and from each of said plurality of memory cells, and a test mode circuit for generating a test mode signal for testing a special operation different from a normal operation, based on said test mode shift signal, and said peripheral circuit performs input/output of data used for testing said special operation to and from each of said plurality of memory cells in accordance with said test mode signal.