Patent ID: 7277337

Claim:
A downgraded memory module comprising: a substrate having wiring traces formed thereon for conducting signals; contact pads along a lower edge of the substrate, the contact pads for mating with a memory module socket on a motherboard; memory chips mounted to the substrate, the memory chips having address, data, and control inputs that are directly connected to the contact pads or are buffered from the contact pads by a buffer chip; wherein the memory chips have a depth of S/2 words that are accessible using the address inputs, and a width of W bits per word, wherein S and W are whole numbers and S is at least 2 20 ; wherein at least one of the memory chips is a downgraded memory chip that has a native depth of S words that are all accessible through pins of the downgraded memory chip when not soldered to the substrate, but only S/2 words are accessible through the contact pads; and first jumper means, mounted on the substrate, for connecting a dividing address pin of the downgraded memory chip to a fixed high voltage supply when the S/2 words are an upper half of the S words in the downgraded memory chip for an upper-half configuration, and for connecting the dividing address pin of the downgraded memory chip to a fixed low voltage supply when the S/2 words are a lower half of the S words in the downgraded memory chip for a lower-half configuration, whereby only half of the native depth of S words of the downgraded memory chip are accessible through the contact pads of the downgraded memory module.