Patent ID: 7742332

Claim:
A phase-change random access memory device comprising: a plurality of word lines arranged in parallel with each other; a plurality of bit lines arranged in parallel with each other above the word lines and orthogonal to the word lines; a plurality of memory cells arranged parallel to the word lines and parallel to the bit lines, and each of the memory cells including a phase-change element and a diode connected in series with the bit line; a plurality of first and second common drain lines arranged below the plurality of memory cells in parallel with the word lines, and commonly connecting a predetermined number of the memory cells that are orthogonal to the bit lines; a plurality of ground lines arranged below the first and second common drain lines and in parallel with the bit lines; a plurality of first switching transistors each having a gate connected to associated one of the word lines, a drain connected to associated one of the first common drain lines, and a source connected to associated one of the ground lines; and a plurality of second switching transistors each having a gate connected to associated one of the word lines, a drain connected to associated one of the second common drain lines, and a source connected to associated one of the ground lines, the first switching transistors and the second switching transistors being arranged in alternation with each other, and connected to different ground lines.