Patent ID: 7635890

Claim:
A semiconductor device comprising: a semiconductor substrate; a plurality of nonvolatile memory cells provided on the semiconductor substrate, each of the plurality of nonvolatile memory cells comprising: a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a control gate electrode provided above the charge storage layer, and a second insulating film provided between the control gate electrode and the charge storage layer, the second insulating film between adjacent charge storage layers including a first region having permittivity lower than that of the second insulating film on a top surface of the charge storage layer in a cross-section view of a channel width direction of the nonvolatile memory cell, the first region having composition differing from that of the second insulating film on the top surface of the charge storage layer, the first region being configured to connect the adjacent charge storage layers and be in direct contact with the control gate electrode.