Patent ID: 7461116

Claim:
In a computer comprising a memory and a floating point unit, a method implemented in a set of instructions executable by said computer, the method comprising: said computer receiving a program, a portion of said program comprising an operand (hereinafter “fixed-point operand”) represented in a fixed-point representation; wherein said fixed-point operand has at least one property selected from a group consisting of (signedness, precision, complexness); said computer expanding said fixed-point operand into a floating-point representation to obtain a floating-point equivalent; said computer storing a precision of the fixed-point operand; said computer further receiving in said portion an instruction comprising an operation to be performed on the fixed-point operand by a fixed point processor; said computer using said floating point unit to perform on the floating-point equivalent, at least one floating-point operation that corresponds to the fixed-point operation, yielding at least one floating-point result; said computer reducing said at least one floating-point result generated by the floating-point operation into a fixed-point result; said computer using the stored precision during reduction of the floating-point result into the fixed-point result; and said computer displaying said fixed-point result to a user to enable said portion of said program to be debugged without use of said fixed point processor.