Patent ID: 8027188

Claim:
A semiconductor memory device comprising: a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first lines which are parallel to one another; a plurality of second lines which are formed so as to intersect with the plurality of first lines, the second lines being parallel to one another; and a memory cell which is disposed in each intersection portion of the first line and the second line, one end of the memory cell being connected to the first line, the other end of the memory cell being connected to the second line, wherein the first line disposed between the adjacent memory cell arrays is shared by memory cells above and below the first line, first ends in a horizontal direction of the vertically-overlapping first lines are commonly connected through a first vertically extended line, second ends in the horizontal direction of the vertically-overlapping first lines are commonly connected through a second vertically extended line, each of the first ends of the vertically-overlapping first lines is directly connected to the first vertically extended line, and each of the second ends of the vertically-overlapping first lines is directly connected to the second vertically extended line.