Patent ID: 8516407

Claim:
A method for fabricating an integrated circuit comprising the steps of: providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of design elements; evaluating the plurality of design elements for the presence of each of the following design features: (1) oppositely colored features, (2) intra-mask density differences, (3) stitch enclosures, (4) via/stitch enclosures, (5) via/stitch keepouts, and (6) focus-sensitive topologies, wherein at least three of the design features (1) through (6) are present in the plurality of design elements; scoring the logical design of the plurality of design elements to produce a design score, wherein the design score comprises a composite of individual scores for each of the at least three of the design features (1) through (6) that are present, wherein: (1) an individual oppositely colored features score comprises a numerical score representing a spacing between the oppositely colored features, (2) an individual intra-mask density differences score comprises a numerical score representing a density balance among mask layers of the logical design, (3) an individual stitch enclosures score comprises a numerical score representing an overlap area of the stitch enclosures, (4) an individual via/stitch enclosures score comprises a numerical score representing an overlap area of the via/stitch enclosures, (5) an individual via stitch keepouts score comprises a numerical score representing a distance from a via to a stitching area of the via stitch keepouts, and (6) an individual focus-sensitive topologies score comprises a numerical score representing a total number of focus-sensitive topologies; modifying the design based at least in part on the design score, wherein modifying the design comprises altering at least one of the plurality of design elements such that an individual score for each of the at least three of the design features (1) through (6) with regard the at least one design element is increased, thereby increasing the composite of individual scores; generating a mask set implementing the modified logical design; and employing the mask set to fabricate the logical design in and on a semiconductor substrate.