Patent ID: 8461866

Claim:
A device for storing pulse latch with logic circuit, comprising: a data signal connecting a second signal channel; a scan data input signal connecting a first signal channel; a SAVE signal connecting said first signal channel, and connecting a first OR gate; a scan enable signal connecting a second OR gate, and connecting an AND gate; a time clock signal connecting a third OR gate, and connecting said AND gate; a restoring signal ( 206 ) connecting an inverter; said scan latch connecting said first signal channel, connecting said second signal channel, and connecting a first OR gate; said second signal channel connecting a data signal, connecting a scan latch, said pulse latch, and connecting said second OR gate; said pulse latch connecting said first signal channel, connecting said second signal channel, connecting said normal output signal, and connecting said third OR gate; and said first OR gate connecting said SAVE signal, connecting said latch, and connecting said AND gate; said second OR gate connecting said scan enable signal, connecting said second signal channel, connecting said third OR gate, connecting said AND gate, and connecting said inverter; said third OR gate connecting said time clock signal, connecting said second OR gate, connecting said AND gate, connecting said inverter; said AND gate connecting said scan enable signal, connecting said time clock signal, and connecting said third OR gate; and said inverter connecting said restoring signal, connecting said second OR gate, and connecting said third OR gate; wherein a data of said pulse latch being stored in said scan latch due to said SAVE signal being inputted when the device is switched off, and wherein said data of said scan latch being restored to said pulse latch due to a pulse signal being restored when the device is switched on.