Patent ID: 6853584

Claim:
A semiconductor memory device comprising: a memory array having a plurality of rows and columns for receiving a plurality of first signals, said plurality of first signals affecting the total amount of current flowing through a first group of said columns; a voltage source having an output; a conducting path connecting said output to said first group of said columns; a transistor in said conducting path, for controlling the current flow in said conducting path; said transistor having a control terminal; a current source having a first terminal and a second terminal, with said first terminal connected to said output, and said second terminal connected to said control terminal; a first plurality of current sources collectively connected to a node; said first plurality of current sources for receiving a plurality of second signals, each of said second signal being an inverse of said first signal, said plurality of second signals affecting the total amount of current flowing through said first plurality of current sources at said node; and a current mirror circuit having a first branch connected to said node, and a second branch mirroring current flowing in said first branch, with said second branch connected to said control terminal.