Patent ID: 8214668

Claim:
A synchronizing circuit, comprising: a power-supply-interruptible circuit section that can be subjected to a power supply interruption; a power supply interruption control circuit section configured to control the power supply interruption; and a gate circuit configured to output an output from the power-supply-interruptible circuit section as a fixed value when the power-supply-interruptible circuit section has been subjected to a power supply interruption; wherein: the power-supply-interruptible circuit section has a first data transmission register configured to output data for controlling the power supply interruption, and a clock enable control register configured to output a clock enable signal for performing control of a clock signal; and the power supply interruption control circuit section has a gated clock buffer configured to perform control of the clock signal based on the clock enable signal, and a first data reception register configured to take in the data that is output from the first data transmission register based on the clock signal that is controlled by the gated clock buffer.