Patent ID: 8921923

Claim:
A semiconductor memory device comprising: a substrate including a channel region in a surface; a tunnel insulating film provided on the channel region; a plurality of charge storage layers provided on the tunnel insulating film, and each including a lower portion and an upper portion provided on the lower portion and having a smaller width than the lower portion; a plurality of device isolation sections provided between the lower portions of adjacent ones of the charge storage layers; a plurality of intermediate insulating films provided on the upper portions of the charge storage layers and on sidewalls of the upper portions, and divided above the device isolation sections; and a control electrode including an upper portion provided on the intermediate insulating films, and a plurality of lower portions provided between adjacent ones of the intermediate insulating films and reaching the device isolation sections without the intermediate insulating films being interposed between the lower portions and the device isolation sections, wherein each of the intermediate insulating films has a stacked structure of dissimilar films, the dissimilar films include: a first film continuously provided on a bottom portion of a region between the sidewall of the upper portion of the charge storage layer and a sidewall of the lower portion of the control electrode, on the sidewall of the upper portion of the charge storage layer, and on the sidewall of the lower portion of the control electrode, and a second film provided on the first film, the second film and the first film are provided between the upper portion of the control electrode and a to of the upper portion of the change storage layer, and the first film is provided between the second film and the top of the upper portion of the charge storage layer.