Patent ID: 8001433

Claim:
A method of making a circuit for scan testing, comprising: providing a plurality of circuit elements on a chip, wherein the circuit elements include memory elements for storing values; configuring the circuit elements into a plurality of power domains with separate power-level controls, including an always-on domain whose power-level is in a power-on state in an operational mode of the circuit and at least one independent power domain whose power level is in power-on state or a power-off state in the operational mode of the circuit; configuring the circuit elements to form a plurality of scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments, wherein each scan segment intersects at most one independent power domain; providing a decompressor circuit that receives a decompressor input and is operatively connected to the scan-segment input ends, wherein the decompressor circuit decompresses the decompressor input to generate input values for the scan segments; providing a compressor circuit that is operatively connected to the scan segment output ends and generates a compressor output, wherein the compressor circuit compresses output values from the scan segments to generate the compressor output; and providing isolation circuits at scan-segment exits from the at least one independent power domain, wherein the isolation circuits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.