Patent ID: 8378403

Claim:
A semiconductor device comprising: a memory cell array comprising a first memory cell and a second memory cell; the first memory cell comprising: a first transistor having a first channel formation region electrically connected to a first bit line through a source or a drain of the first transistor; and a second transistor having a second channel formation region electrically connected to a gate of the first transistor through a source or a drain of the second transistor, and the second memory cell comprising: a third transistor having a third channel formation region electrically connected to a second bit line through a source or a drain of the third transistor; and a fourth transistor having a fourth channel formation region electrically connected to a gate of the third transistor through a source or a drain of the fourth transistor, and a driver circuit associated with the first memory cell and the second memory cell, wherein a first semiconductor material included in the first channel formation region is selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, and wherein the first memory cell and the second memory cell are stacked so as to overlap at least partly with each other.