Patent ID: 8533426

Claim:
An I/O access control apparatus, comprising: a command receiver operable to receive, from an external access requesting entity, a command for controlling data in a memory space of a processor, together with address information used to specify an address to be accessed and ID information used to identify the access requesting entity; an access decision unit operable to determine whether access of the access requesting entity to an address specified by the address information is permitted or not, by referring to an access permission/denial determination table that associates an address in the memory space with ID information on an access requesting entity which is to be permitted to access a region specified by the address; an address translation table memory containing an address translation table to translate a logical address into a physical address, wherein the address information is indicative of the logical address, which is a virtual address converted from an address of the memory space into a predetermined format, wherein said address translation table memory stores an index value generated by performing a logic operation of a predetermined base value on a segment address set by each access requesting entity, which is a predetermined part of the logical address specified in the address information, and the address translation table as a data table associating a physical address with the index value; an address translation unit operable to translate the logical address specified by the address information into a physical address by referring to the address translation table, wherein said address translation unit calculates the index value from the logical address specified by the received address information, and identifies a physical address by referring to the address translation table according to the index value thereof; and an access processing unit operable to execute access of the access requesting entity to the memory space if the access has been permitted by said access decision unit and based on the physical address identified by said address translation unit; and a cache processing unit which initializes the address translation table by loading a partial translation table, corresponding to a predetermined logical address range in the address translation table, into a cache memory from said address translation table memory, prior to address translation by said address translation unit, wherein when data necessary for converting a logical address specified by the address information into a physical address is contained in the partial translation table, said address translation unit performs address translation by referring to the partial translation table, and when the data necessary for converting a logical address specified by the address information into a physical address is not contained in the partial translation table, said cache processing unit loads a new partial translation table into the cache memory from said address translation table memory.