Patent ID: 8032332

Claim:
A semiconductor inspecting apparatus, comprising: a large-capacity data generation apparatus that images a wafer surface; a data transmission apparatus including at least one of a data transmission control unit that controls the transmission of the data generated by the large-capacity data generation apparatus and a data reception control unit that controls the reception of the data; and a processing apparatus that processes the transmitted data, wherein the data transmission control unit includes an equivalent transmission capacity conversion unit that equivalently converts data capacity transmitted from the large-capacity data generation apparatus, and a transmission control unit that transmits data transmitted from the equivalent capacity conversion unit to the outside, wherein the data reception control unit includes a data reception control unit that receives data transmitted from the transmission control unit, and an equivalent transmission capacity inverse conversion unit that equivalently inverse-converts the data transmitted from the data reception control unit, wherein the equivalent transmission capacity conversion unit includes: a buffer memory having a parallel bus clock of arbitrary speed and a serial bus clock of arbitrary speed matched to a greater of parallel bus width having a parallel bus of arbitrary width driven by the parallel bus clock and specified by a first parameter and the width of the number of serial lanes having the serial lane of arbitrary number driven by the serial bus clock and specified by a second parameter; a preceding stage bus switching unit that fills the buffer memory with input data from the parallel bus without making a free space; a following stage bus switching unit that fills data read from the buffer memory to the width of the number of serial lanes of arbitrary number without making a free space; and frame creation means for forming serial transmission frames by using data read from the buffer memory, wherein the equivalent transmission capacity inverse conversion unit includes: a buffer memory matched to the greater of the parallel bus width or the width of the number of serial lanes; means for receiving reception frame data from the serial lanes and disassembles reception frames; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; and a following stage bus switching unit that fills data read from the buffer memory to a parallel bus of arbitrary width without making a free space, and wherein the data transmission apparatus includes at least one of circuit modules that include an input unit inputting the first parameter and the second parameter from the outside and the data transmission control unit and the data reception control unit that can set the parallel bus width and the number of serial lanes to a desired value, based on the first parameter and the second parameter inputted from the input unit.