Patent ID: 7715261

Claim:
A semiconductor memory device, comprising: a first input/output sense amplifier area having a first plurality of input/output sense amplifiers; a memory bank including a first memory block and a second memory block, the memory bank configured to be fully addressed by a first row decoder and a first column decoder, the first input/output sense amplifier area being disposed between the first memory block and the second memory block, the first memory block having a first plurality of data lines, the second memory block having a second plurality of data lines, each of the first plurality of input/output sense amplifiers being associated with a corresponding one of the first plurality of data lines and a corresponding one of the second plurality of data lines; a peripheral circuit area adjacent to the first column decoder; and a parallel-to-serial transformer area coupled to the first input/output sense amplifier area, the parallel-to-serial transformer area being outside the peripheral circuit area.