Patent ID: 8294512

Claim:
A bootstrapped clock generator comprising: a boost capacitor connected between a boost node and a first node; a first p-type metal oxide semiconductor (PMOS) transistor, connected between a power supply voltage and the boost node, which has a gate receiving a first clock signal; a first switch that selectively connects an input voltage signal to the first node in response to the first clock signal and a second clock signal, the second clock signal being an inversion signal of the first clock signal; a second switch that selectively connects a reference voltage signal to the first node in response to the second clock signal, a level of the reference voltage signal being lower than a maximum level of the input voltage signal; a second PMOS transistor that transfers a boosting voltage to a second node in response to the second clock signal and generates the sampling control signal, the boosting voltage being a voltage at the boost node; and a third switch that resets the second node in response to the second clock signal.