Patent ID: 8067819

Claim:
A semiconductor wafer having a scribe line dividing the semiconductor wafer into a matrix of a plurality of semiconductor chips, the semiconductor wafer including a polysilicon layer, a poly-metal interlayer insulation film formed on the polysilicon layer, and a first metal wiring layer formed on the poly-metal interlayer insulation film, the semiconductor wafer comprising: a process-monitor electrode pad formed on a dicing area of the scribe line, the process-monitor electrode pad being formed of three metal wiring layers including the first metal wiring layer, a second metal wiring layer and a third metal wiring layer, the process-monitor electrode pad having a width greater than the width of the dicing area of the scribe line and at a same time being within the scribe line, and the process-monitor electrode pad including a plurality of contact holes formed in the poly-metal interlayer insulation film for connecting the first metal wiring layer to the polysilicon layer, wherein the second metal wiring layer is formed directly on the first metal wiring layer, wherein the first metal wiring layer is not formed in the dicing area, wherein the contact holes are not formed in the dicing area, wherein the poly-metal interlayer insulation film and first metal wiring layer of the semiconductor wafer, between (a) end parts of the process-monitor electrode pad along a width direction of the scribe line and (b) respective adjacent semiconductor chip, are removed, wherein the poly-metal interlayer insulation film is formed below the process-monitor electrode pad.