Patent ID: 7508709

Claim:
A flash memory device, comprising: a memory cell array including a plurality of multi-level cells, each cell being configured to store at least two bits of data and coupled to at least a bitline; and a page buffer circuit coupled to the memory cell array and including: a higher-bit register to detect a voltage of a sensing node, and store a first or second higher sensing data bit according to a result of the detection in response to a first or second higher read-control signal, and store a first or second internal data bit in response to the first or second higher read-control signal and an input data bit received through an input/output node; an output drive circuit to generate an output data bit in response to one of the first higher sensing data bit, the second higher sensing data bit, the first internal data bit, and the second internal data bit; a lower-bit register to detect a voltage of the sensing node and storing a first or second lower sensing data bit according to a result of the detecting in response to a first or second lower read-control signal; a first transmission circuit to transmit the output data bit to the sensing node in response to a first program control signal; and a second transmission circuit to transmit the first or second lower sensing data bit to the sensing node in response to a second program control signal.