Patent ID: 8401063

Claim:
A decision feedback equalizer comprising: a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit, said correction circuit comprising a first multiplexer to be controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference, a first pair of master latches to receive as input the received bit and being clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal, with the respective latched replicas being input to said first multiplexer; and a first pair of amplifiers coupled between said first pair of master latches and said first multiplexer, said first pair of amplifiers to amplify and saturate the latched replicas to be input to said first multiplexer.