Patent ID: 7106639

Claim:
A defect management enabled PIRM comprising: a data storage medium providing a plurality of stacked physical layers, each layer providing a plurality of cross point data storage arrays each providing a plurality of memory cells, the plurality of data storage arrays on each layer allocated into separate super arrays on each layer, the separate super arrays virtually aligned as sets; a controller capable of establishing the selection of a virtually aligned set of arrays and a virtually aligned set of memory cells; the controller being operable during a data write operation to receive a word of data bits and detect a defective cell in a defective array in a selected virtually aligned set of memory cells, the controller further directing the allocation of at least one data bit from the defective memory array to a spare memory array; wherein the controller is operable to perform Sparing on a Layer, moving the data bit allocated for the defective memory array to a spare memory array within the super array containing the defective array; wherein a first subset of the plurality of arrays are main arrays, and a second subset of the plurality of arrays are spare arrays; wherein the PIRM is operable such that the defective array is deactivated when the spare, array is activated; wherein activation and deactivation is performed with a matched set of connection lines; and wherein the same lines deactivating the defective main array activate the spare array.