Patent ID: 7917735

Claim:
A data processing apparatus comprising: processing circuitry configured to execute a sequence of instructions fetched from memory; pre-decoding circuitry configured to receive the instructions fetched from memory and to perform a pre-decoding operation to generate corresponding pre-decoded instructions; a cache configured to store the pre-decoded instructions for access by the processing circuitry; for a first set of instructions, each instruction comprising a plurality of instruction portions, and the pre-decoding circuitry generating a corresponding pre-decoded instruction comprising a plurality of pre-decoded instruction portions, the pre-decoded instruction portions are generated in a manner which allows the original instruction of the first set to be recreated from the pre-decoded instruction; if when applying the pre-decoding operation to an instruction in the first set, the pre-decoding circuitry does not have access to all of the plurality of instruction portions of that instruction, the pre-decoding operation performed being incomplete and the pre-decoding circuitry being arranged to provide in association with at least one pre-decoded instruction portion generated an indication that that pre-decoded instruction portion relates to an incomplete pre-decoding operation; the data processing apparatus further comprising: error detection circuitry, responsive to a pre-decoded instruction being accessed from the cache, configured to detect if at least one pre-decoded instruction portion of that pre-decoded instruction has said indication associated therewith, and on such detection to recreate the original instruction from the pre-decoded instruction and to cause the original instruction to be re-passed through the pre-decoding circuitry in order to generate corrected pre-decoded instruction portions for said pre-decoded instruction; the cache configured to store the corrected pre-decoded instruction portions generated by the pre-decoding circuitry.