Patent ID: 8508275

Claim:
A semi-dynamic flip-flop circuit configured to operate in a first phase and a second phase, said circuit comprising: a first stage having a first input lead, a second input lead and an output lead, the first input lead of the first stage coupled to receive a first signal and the second input lead of the first stage coupled to receive a second signal, the first stage comprising: a delay circuit having an input lead coupled to the second input lead of the first stage and an output lead, the delay circuit configured to delay the second signal; a logic gate having a first input coupled to the output lead of the delay circuit, a second input and an output; a first transistor stack circuit having a first input lead coupled to receive the second signal, a second input lead coupled to receive the first signal and a third input lead coupled to receive the output from the logic gate; a keeper circuit having a first input lead coupled to the second input of the logic gate and an output coupled to the output of the first stage, the keeper circuit configured to latch an output signal from the first stage; and a control transistor having a control input coupled to the output of the logic gate and an output lead coupled to a second input of the keeper circuit, the control transistor configured to provide a conductive path between the second input of the keeper circuit and a voltage source when, during the second phase, the output signal of the logic gate has a logic level equivalent to a predetermined logic level; and a second stage having a first input lead coupled to the output lead of the first stage, a second input lead coupled to the second input lead of the first stage, and an output lead, the second stage comprising: a second transistor stack circuit having a first input lead coupled to receive the second signal, a second input lead and a third input lead coupled to receive the output from the first stage and an output lead; and a latch circuit having an input lead coupled to the output lead of the second transistor stack and an output lead coupled to the output lead of the second stage.