Patent ID: 8558777

Claim:
A gate driver, comprising: a plurality of shift registers configured to output signals sequentially such that a current shift register is reset by an output signal of the shift register after the following shift register, the plurality of shift registers including a plurality of odd-numbered shift registers and a plurality of even-numbered shift registers; wherein one of a first clock and a second clock having opposite phases is inputted to the plurality of shift registers, wherein the first clock is provided to the odd-numbered shift registers, and the second clock is provided to the even-numbered shift registers, wherein the odd-numbered shift registers are performed to the first clock and the even-numbered shift registers are performed to the second clock, wherein a start time and duration of a high output signal of each of the odd-numbered shift registers is identical with a start time and duration of high period of the first clock, wherein a start time and duration of a high output signal of each of the even-numbered shift registers is identical with a start time and duration of high period of the second clock, and wherein each of the shift registers includes: a first transistor directly coupled to an output signal of a previous shift register and a first node; a second transistor directly coupled to the output signal of the previous shift register, a second node and a first power supply voltage; a third transistor directly coupled to the first node, the second node and the first power supply voltage; a fourth transistor directly coupled to the second node, the first node and the first power supply voltage; a fifth transistor directly coupled to the first node and one of clock signals having two or more phases; a sixth transistor directly coupled to the second node, the fifth transistor and the first power supply voltage; and a seventh transistor directly coupled to an output signal of a shift register after the following shift register, the first node and the first power supply voltage, wherein the current shift register charges a node with the output signal of the previous shift register during a first clock period, outputs an output signal of a high state from the current shift register by the charged node during a second clock period, discharges the output signal of a high state from the current shift register to a low state during a third clock period, and discharges the charged node by the output signal of the shift register after the following shift register during a fourth clock period, wherein the fifth transistor is kept in a turned on state by a voltage of the first node, and the output signal of the high state is rapidly discharged to the low state through the fifth transistor during the third clock period.