Patent ID: 7739097

Claim:
An electrically reconfigurable hardware emulation system reprogrammably implementing a user design, said user design utilizing at least one user clock signal, comprising: a logic board comprising a set of fixed electrical conductors, a plurality of programmable logic devices, and a plurality of programmable interconnect devices, the plurality of programmable logic devices on the logic board implementing the user design; a multiplexing clock signal source which generates a multiplexing clock signal, the logic board carrying the multiplexing clock signal; and a plurality of clock dividers, wherein each clock divider of the plurality of clock dividers generates a divider clock signal with reference to the multiplexing clock signal and a synch signal and the divider clock signal is asynchronous from each of said at least one user clock signal, wherein the plurality of programmable logic devices have a plurality of input/output pins electrically connected to circuitry having output multiplexing circuitry and input demultiplexing circuitry, said output multiplexing circuitry and said input demultiplexing circuitry controlled by said divider clock signal of a first clock divider of the plurality of clock dividers, wherein the plurality of programmable interconnect devices have a plurality of input/output pins electrically connected to circuitry having output multiplexing circuitry and input demultiplexing circuitry, said output multiplexing circuitry and said input demultiplexing circuitry controlled by said divider clock signal of a second clock divider of the plurality of clock dividers, the plurality of programmable logic devices being interconnected using at least one programmable interconnect device of the plurality of programmable interconnect devices, wherein said set of fixed electrical conductors of the logic board connects said input/output pins of the plurality of programmable logic devices to said input/output pins of the plurality of programmable interconnect devices in a partial crossbar interconnect arrangement, said set of fixed electrical conductors carrying time-multiplexed signals between said input/output pins of the plurality of programmable logic devices and said input/output pins of the plurality of programmable interconnect devices, and wherein the synch signal periodically resets the plurality of clock dividers to synchronize the plurality of logic devices and the plurality of interconnect device.