Patent ID: 8325074

Claim:
A continuous-time delta-sigma digital-to-analog converter (DAC), comprising: a first delta-sigma modulator configured to quantize a most significant bit or bits of a digital input signal and produce a first quantization error signal; a second multi-stage delta-sigma modulator configured to quantize less significant bits of the digital input signal, the second multi-stage delta sigma modulator comprising: a first quantization stage coupled to a difference of the first quantization error signal and a second quantization error signal and configured to quantize next most significant bits of the digital input signal and produce a third quantization error signal representing a difference between an input and an output of the first quantization stages; a second quantization stage with an input coupled to the third quantization error signal and configured to quantize least significant bits of the digital input signal and produce the second quantization error signal representing a difference between the input and an output of the second quantization stage; a first noise-shaping filter for filtering the second quantization error signal, the output of the first noise-shaping filter subtracted from the first quantization error signal to produce the input of the first quantization state; and a second noise-shaping filter having an input coupled to a sum of an output of the first quantization stage and an output of the second quantization stage; a first DAC coupled to an output of the first delta-sigma modulator; a second DAC coupled to an output of the second noise-shaping filter; and a low pass output filter coupled to a sum of an output of the first DAC and an output of the second DAC, wherein the second DAC has a greater resolution than the first DAC.