Patent ID: 8058566

Claim:
A packaging substrate structure, comprising: a carrier layer with a patterned circuit layer disposed on at least a surface thereof, the patterned circuit layer having a plurality of circuits and a plurality of first electrical connection terminals; at least a first dielectric layer disposed on the patterned circuit layer and the at least a surface of the carrier layer and formed with a plurality of first vias for exposing surfaces of the first electrical connection terminals; a second dielectric layer disposed on the first dielectric layer and defined with a plurality of small-dimension opening areas and at least a large-dimension opening area, allowing a portion of the first dielectric layer to be exposed from the opening areas and a portion of the opening areas to correspond in position to the first vias, wherein a plurality of dielectric pillars are disposed on the first dielectric layer exposed from the large-dimension opening area; and a first circuit layer comprising first conductive vias formed in the first vias and electrically connected to the first electrical connection terminals, first circuits formed on the first dielectric layer exposed from the small-dimension opening areas, and at least a conductive block disposed on the first dielectric layer exposed from the large-dimension opening area.