Patent ID: 7915692

Claim:
A semiconductor structure, comprising: a semiconductor substrate; a gateline extending along a first axis over the substrate; an array of openings formed within the gateline such that the gateline comprises two lines elongated and extending along the first axis on opposite sides of the openings, wherein the openings are spaced from one another by segments of the gateline along the first axis to thereby form a lattice, the segments connecting the two elongated lines to each other; and elevationally-elongated pillars formed within the openings in the gateline, the pillars forming pairs, wherein each pillar pair comprises one source region in a first pillar adjacent along the first axis to one drain region in a second pillar, wherein the gateline and pillar pairs together form a plurality of transistor constructions in which the source region in the first pillar and the drain region in the second pillar are gatedly connected to each other through the gateline, and wherein the two elongated lines are on opposite sides of the pillar pairs.