Patent ID: 7164174

Claim:
A vertical PNP bipolar transistor formed as part of a BiCMOS process, the transistor formed upon a wafer having a silicon substrate and comprising: a double diffused DWELL in a DNWELL formed within a P-epi layer formed across a substrate; a SPWELL in the DNWELL region formed adjacent the DWELL region; a layer of oxide material formed over the wafer and patterned so as to serve as a gate oxide in a CMOS/DMOS device; a layer of poly-silicon formed across the wafer and patterned so as to serve as part of a gate stack in a CMOS/DMOS device, the patterned poly-silicon serving as an emitter contact for the vertical PNP transistor, the patterned poly-silicon also comprising a P-type dopant that diffuses into a small portion of the DWELL, thereby establishing an emitter in the transistor; and PSD/NSD implants that establish a collector contact and a base contact, respectively, for the vertical PNP transistor.