Patent ID: 7764345

Claim:
A liquid crystal display device which is configured of first and second substrates arranged opposite to each other as well as liquid crystal filled in an interstice between the first and second substrates, and which includes a plurality of picture elements arrayed in a matrix, the liquid crystal display device comprising: a plurality of gate bus lines for supplying scanning signals respectively to the picture elements; a plurality of data bus lines for supplying display signals respectively to the picture elements; first and second sub-picture element electrodes formed in each of the picture elements; a buffer capacitance formed in each of the picture elements; a first transistor which is driven by a scanning signal of an nth gate bus line (n is an integer), and which transfers a display signal of an mth data bus line (m is an integer) to the first sub-picture element electrode in an nth row and an mth column while the first transistor is on; a second transistor which is driven by the scanning signal of the nth gate bus line, and which transfers the display signal of the mth data bus line to the second sub-picture element electrode in the nth row and the mth column while the second transistor is on; and a third transistor which is driven by a scanning signal of a gate bus line different from the nth gate bus line, and which transfers the scanning signal of the gate bus line different from the nth gate bus line to the first sub-picture element electrode in the nth row and the mth column through the buffer capacitance while the third transistor is on, the third transistor comprising: a gate formed integral with the gate bus line different from the nth gate bus line, a source connected to the first sub-picture element electrode, and a drain connected to the buffer capacitance, wherein the buffer capacitance is configured of first and second capacitance electrodes, the first capacitance electrode and the gate bus line different from the nth gate bus line being formed integrally, the second capacitance electrode and the drain of the third transistor being formed integrally, and the second capacitance electrode being arranged in a position opposite to the first capacitance electrode with an insulating film interposed in between.