Patent ID: 7571406

Claim:
A clock distribution system, comprising: a plurality of uniform adjustable buffers coupled between at least one root node and a plurality of destination nodes, wherein each of said plurality of uniform adjustable buffers is adjustable between a minimum delay and a maximum delay, wherein at least one of said plurality of uniform adjustable buffers comprises: a first plurality of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node and having a corresponding first plurality of control electrodes, wherein each of said first plurality of control electrodes is coupled to a selected one of an input node and a second voltage supply collectively forming a first plurality of selectable connections; and a first plurality of N-channel devices having current paths coupled in series between said first output node and said second voltage supply and having a corresponding second plurality of control electrodes, wherein each of said second plurality of control electrodes is coupled to a selected one of said input node and said first voltage supply collectively forming a second plurality of selectable connections; wherein said first and second plurality of selectable connections are made to adjust delay from said input node to said first output node; a first branch comprising a first set of said plurality of uniform adjustable buffers coupled in series between said at least one root node and a first destination node; and a second branch comprising a second set of said plurality of uniform adjustable buffers coupled in series between said at least one root node and a second destination node; wherein each of said plurality of uniform adjustable buffers of said first set is programmed with said minimum delay and wherein at least one of said plurality of uniform adjustable buffers of said second set is programmed with a larger delay than said minimum delay.