Patent ID: 8593449

Claim:
A reference voltage generation circuit comprising: a first amplifier circuit; and a second amplifier circuit; wherein the first amplifier circuit comprises: a first input stage including two npn transistors or NMOS transistors having base terminals or gate terminals to which a variable voltage and a predetermined lower limit voltage are inputted, respectively; a first output stage including a pnp transistor or a PMOS transistor having an emitter terminal or a source terminal connected to an output terminal for a reference voltage; and a first amplifier stage to control the first output stage for equalizing the higher one of the variable voltage and the lower limit voltage with the reference voltage; wherein the second amplifier circuit comprises: a second input stage including two npn transistors or two NMOS transistors having base terminals or gate terminals to which the reference voltage and a predetermined higher limit voltage are inputted, respectively; a second output stage including a pnp transistor or a PMOS transistor having an emitter terminal or a source terminal connected to an output terminal for the reference voltage; and a second amplifier stage to control the second output stage for equalizing the reference voltage with the higher limit voltage.