Patent ID: 7865674

Claim:
A memory system comprising: a memory hub device integrated in a memory module; a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces; a memory hub controller integrated into the memory hub device; a link interface integrated into the memory hub device, wherein the link interface provides a communication path between the memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the memory devices receive and send data via the link interface; a first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data from the first and second set of memory devices to the link interface based on a control signal from the memory hub controller; second multiplexer integrated into the memory hub device the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.