Patent ID: 8830774

Claim:
A semiconductor memory device comprising: a first and a second signal line forming a pair of signal lines; a third and a fourth signal line forming another pair of signal lines; a memory cell connected to the first and second signal lines; and a sense amplifier circuit provided between the first and second signal lines and the third and fourth signal lines, wherein the sense amplifier circuit includes a first transistor of a first conductivity type having a gate connected to a precharge signal, a source connected to a first power supply potential, and a drain connected to the first signal line, a second transistor of the first conductivity type having a gate connected to the precharge signal, a source connected to the first power supply potential, and a drain connected to the second signal line, a third transistor of the first conductivity type having a gate connected to the first signal line, a source connected to the first power supply potential, and a drain connected to the third signal line, a fourth transistor of the first conductivity type having a gate connected to the second signal line, a source connected to the first power supply potential, and a drain connected to the fourth signal line, a fifth transistor of a second conductivity type having a gate connected to the third signal line, a source connected to a second power supply potential, and a drain connected to the first signal line, and a sixth transistor of the second conductivity type having a gate connected to the fourth signal line, a source connected to the second power supply potential, and a drain connected to the second signal line.