Patent ID: 7688417

Claim:
A method for manufacturing a TFT array panel comprising: forming a gate line having a gate electrode on an insulating substrate; forming a gate insulating layer over the gate line; forming a semiconductor layer over the gate insulating layer; forming an ohmic contact layer over the semiconductor layer; forming a data line having a source electrode and a drain electrode apart from each other over the ohmic contact layer by photolithography using a negative photoresist pattern; forming a passivation layer over the data line and having a contact hole to expose the drain electrode; forming a pixel electrode connected to the drain electrode through the contact hole, wherein the negative photoresist pattern includes a first portion having a first thickness in the area corresponding to a channel area between the source electrode and the drain electrode, a second portion having a second thickness thicker than the first thickness in the area corresponding to the data line area, and a third portion having a third thickness thinner than the first thickness in an area other than the channel area and the data line area, and wherein portions of the negative photoresist pattern that are exposed to light remain and have an inverse tapered lateral side, wherein a boundary line of the data line and the drain electrode is located in a boundary line of the semiconductor within the range of 1.25 μm and less, except for the distance between the source electrode and the drain electrode.