Patent ID: 7002860

Claim:
Register-file bit-read apparatus comprising: a first decoder for receiving first address-bit signals and responsively asserting a set of select signals on one of N sets of M select lines; N multiplexers, each having Q output nodes and Q pull-ups coupled to the respective Q nodes, and having M selectors, each selector being coupled to a respective one of the N×M select lines and a respective one of N×M register-file cells, wherein the M selectors of such a multiplexer are arranged in Q groups coupled to respective ones of the multiplexer's Q output nodes; and output logic gates for the respective N multiplexers, such a logic gate having Q inputs coupled to respective ones of the Q output nodes of the gate's multiplexer; a second decoder for receiving second address-bit signals and responsively asserting a select signal on an N+1th set of N select lines; an N+1th multiplexer having R output nodes and R pull-ups coupled to the respective R nodes, and having N selectors, each coupled to a respective one of the select lines of the second decoder and a respective one of the N output logic gates of the N multiplexers, wherein the N selectors are in R groups coupled to respective ones of the R output nodes; and an N+1th output logic gate having R inputs, each input being coupled to a respective one of the R output nodes, wherein each multiplexer pull-up is operable to drive its respective multiplexer output node responsive to one of the address-bit signals, wherein such a pull-up includes a transistor having one conducting electrode coupled to a supply voltage having a certain voltage level, another conducting electrode coupled to the pull-up's respective one of the multiplexer output nodes and a gate directly coupled to one of the address-bit signals or a complement of one of the address-bit signals, the address bit signal turning on the transistor if the selected one of the register-file cells is not conductively coupled to the pull-up's node so that the pull-up drives its multiplexer output node toward the voltage level of the supply voltage, and wherein the multiplexer is not directly coupled to any cyclical timing signal.