Patent ID: 8570480

Claim:
A display device, comprising: a substrate having a display area and a border area, the border area being substantially surrounding the display area; a plurality of data lines disposed in the display area of the substrate; a plurality of gate lines disposed in the display area of the substrate and substantially crossed with the data lines perpendicularly, the plurality of gate lines comprising a first set of gate lines and a second set of gate lines; a plurality of first auxiliary gate lines disposed in the display area of the substrate, the first auxiliary gate lines being substantially parallel with the data lines, each first auxiliary gate line being electrically connected to a corresponding gate line of the first set of gate lines; a plurality of second auxiliary gate lines disposed in the border area of the substrate, each second auxiliary gate line being electrically connected to a corresponding gate line of the second set of gate lines; a driving module disposed in the border area of the substrate, the driving module being electrically connected to the data lines, the second auxiliary gate lines, and the first auxiliary gate lines; a plurality of pixel units disposed in the display area of the substrate; a plurality of common lines electrically coupled with the pixel units; an insulation layer disposed in the border area, the second auxiliary gate lines being covered with the insulation layer; and an adjust layer disposed in the border area to overlap at least one of the second auxiliary gate lines, at least a portion of the insulation layer being covered with the adjust layer, wherein a first couple capacitor is formed between the at least one of the second auxiliary gate lines and the adjust layer; wherein the adjust layer is electrically connected to the common lines wherein each first auxiliary gate line and the adjust layer are not overlapped, each first auxiliary gate line is not electrically connected to the second set of gate lines, and a second couple capacitor is formed between at least one of the second set of gate lines and at least one of the first auxiliary gate lines.