Patent ID: 8604857

Claim:
A power-supply-insensitive delay circuit, comprising: a first sub-circuit having a negative transition delay sensitivity to increases in a power supply voltage; and a second sub-circuit having a positive transition delay sensitivity to increases in the power supply voltage, wherein the first sub-circuit is coupled in parallel with the second sub-circuit to produce the power-supply-insensitive delay circuit having a reduced transition delay sensitivity to changes in the power supply voltage compared with the first sub-circuit or the second sub-circuit, wherein the first sub-circuit is coupled in parallel with the second sub-circuit at an input to the power-supply-insensitive delay circuit and at an output of the power supply-insensitive delay circuit such that the input to the power-supply-insensitive delay circuit is coupled to an input to the first sub-circuit and an input to the second sub-circuit and the output of the power supply-insensitive delay is coupled to an output of the first sub-circuit and an output of the second sub-circuit.