Patent ID: 7122901

Claim:
A semiconductor device comprising: an insulating base material; a plurality of wiring layers each patterned in a required shape and laminated over both surfaces of the insulating base material with at least one insulating layer interposed therebetween, the wiring layers being electrically connected to one another through at least one via hole, the via hole being formed to pierce the insulating layer in a direction of thickness; and a chip mounted in an embedded manner in the insulating layer over at least one surface of the insulating base material, the chip having at least one electrode electrically connected to one of the wiring layers, wherein at least one through hole is formed in a portion of the insulating base material, the portion corresponding to a mount area for the chip, and each via hole is formed on an outwardly extending portion of one of the wiring layers, the one wiring layer being electrically connected to a conductor layer formed at least on an inner wall of the through hole.