Patent ID: 6981087

Claim:
A system comprising: a master control processor; a bus controller connected to the master control processor and implementing a serial bus interface between the master control processor and a plurality of serial bus devices, the master control processor and the bus controller being on a first circuit board; a midplane connected to the bus controller on the first circuit board; and a plurality of additional circuit boards connected to the serial bus interface through the midplane, each of the plurality of additional circuit boards including one or more of the serial bus devices, a switch configured to electrically connect the circuit board corresponding to the switch to the first circuit board through the serial bus interface when the switch is controlled to be in a first state and to electrically isolate the circuit board corresponding to the switch from the serial bus interface on the first circuit board when the switch is controlled to be in a second state, and local control logic for outputting a signal for controlling the state of the switch, the local control logic controlling the switch to be in the first state when the switches on each of the other of the plurality of additional circuit boards are in the second state.