Patent ID: 8881117

Claim:
A method executable by a processor, comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by: (i) matching a plurality of the lower-level nodes and edges to at least first higher-level structure nodes representing internal structure, each higher-level structure node representing a group of one or more of the lower-level nodes and one or more associated edges, wherein each of said first higher-level structure nodes is restricted to being selected exclusively from a predetermined set of structure node patterns, each structure node pattern in the set having at most one entry point and at most one exit point, and to each of the first higher-level structure nodes, allocating a single respective execution time based on its component lower-level nodes, and then (ii) matching at least some of the first higher-level structure nodes and edges to at least second higher-level structure nodes, each of the second higher-level structure nodes representing a group of at least one or more of the first higher-level nodes and one or more associated edges, wherein each of said second higher-level structure nodes are restricted to being selected exclusively from said predetermined set of structure node patterns each having at most one entry point and at most one exit point, and to each of the second higher-level nodes, allocating a single respective execution time based on the single execution time ahead allocated to each of its component first higher-level nodes; and using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor, and making a modification affecting the timing property in dependence on said estimation, said estimation and said modification being based on the higher-level control flow structure as generated using said predetermined set of structure node patterns and the single execution time allocated to each of the second higher-level nodes; wherein the predetermined set of structure node patterns comprises a conditional-type pattern comprising a plurality of alternate edges resolving to a common exit point, and a loop-type pattern comprising one or more lower level repeating nodes and an associated looping edge; and wherein the single execution time allocated to the first and second higher-level structure nodes matched to each of the structure node patterns is a worst case execution time.