Patent ID: 8495275

Claim:
A list structure control circuit comprising: memory devices configured to individually store data and series connected as ordered stages so that data stored in each memory device has an order relation; selection circuits arranged for each memory device; and an update control circuit that is configure to: receive a position selection signal which specifies a position of a memory device from among the memory devices for at least one of data insertion or data removal, add the position selection signal to a fixed value, or subtract the position selection signal from a fixed value, and generate an enable signal based on the addition or the subtraction and controls data retention performed in the memory devices or data update performed in the memory devices using data of the memory devices in precedent stages based on the generated enable signal, wherein the selection circuits are controlled based on the position selection signal at a time of the data insertion, and data stored in a memory device located at the position specified by the position selection signal is updated with data to be inserted.