Patent ID: 8169027

Claim:
A multi-gate pMOS transistor comprising: a fin disposed on a semiconductor substrate, the fin having an upper portion disposed on a lower portion, said upper portion being of a first semiconductor having a first band gap and said lower portion being of a second semiconductor having a second band gap, larger than said first band gap to inhibit current leakage from said upper portion to said lower portion; a shallow trench isolation (STI) dielectric disposed on the semiconductor substrate adjacent to the fin, the fin extending from the semiconductor substrate through the STI dielectric; a gate structure electrically coupled with said upper portion and said lower portion to form a channel region in at least said upper portion, the gate structure including a gate dielectric in direct contact with a sidewall of the upper portion and in direct contact with a sidewall of the lower portion of the fin extending above the STI dielectric; and a source region and drain region in the fin on opposite sides of the channel region, wherein the source and drain regions are fully contained within the upper portion of the fin.