Patent ID: 8140820

Claim:
A data processing apparatus comprising: processing circuitry for performing data processing operations; a memory system for storing data for access by the processing circuitry when performing said data processing operations; address translation circuitry, responsive to an access request issued by the processing circuitry and specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in said memory system corresponding to the virtual address; a translation lookaside buffer (TLB) accessible by the address translation circuitry and having a plurality of entries, each entry storing address translation information for one or more virtual addresses, and each entry having a field which indicates whether the address translation information is consolidated address translation information enabling the address translation circuitry to generate the physical address, or is partial address translation information enabling the address translation circuitry to generate one of said at least one intermediate addresses; responsive to the access request issued by the processing circuitry, the address translation circuitry is configured to reference the TLB to determine whether one of said entries provides address translation information for the specified virtual address; if said one of said entries provides address translation information for the specified virtual address, and the field indicates that the address translation information is consolidated address translation information, the address translation circuitry is configured to produce the physical address directly from the consolidated address translation information; if said one of said entries provides address translation information for the specified virtual address, and the field indicates that the address translation information is partial address translation information, the address translation circuitry is configured to produce said one of said at least one intermediate addresses from the partial address translation information, determine from the field a stage of the multi-stage address translation process that was reached by the address translation circuitry when using the partial address translation information, and then perform the remainder of the multi-stage address translation process; and if none of said entries provides address translation information for the specified virtual address, the address translation circuitry is configured to perform all stages of the multi-stage address translation process.