Patent ID: 8426241

Claim:
A method for fabricating a diode, comprising the steps of: providing a substrate; forming a backside electrode on the substrate; electrodepositing one or more layers on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin by a) electrodepositing a copper-selenium layer on the backside electrode; b) annealing the copper-selenium layer at a temperature of from about 80° C. to about 100° C., for a duration of from about 30 minutes to about 60 minutes; c) electrodepositing a zinc-selenium layer on the copper-selenium layer; d) annealing the zinc-selenium layer at a temperature of from about 80° C. to about 100° C., for a duration of from about 30 minutes to about 60 minutes, and e) electrodepositing a tin metal layer on the zinc-selenium layer; annealing the layers in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode; forming an n-type semiconductor layer on the CZTS absorber layer; and forming a transparent conductive layer on the n-type semiconductor layer.