Patent ID: 8667217

Claim:
A system comprising: a selection module configured to select a plurality of memory blocks of a flash memory in response to (i) the plurality of memory blocks being partially written with first data and (ii) receiving a write command to write second data to the plurality of memory blocks; a control module configured to, prior to erasing the first data from the plurality of memory blocks in order to write the second data in the plurality of memory blocks, (i) collect the first data from the plurality of memory blocks and (ii) write the collected first data in a portion of a dynamic random access memory instead of writing the collected first data in the flash memory; and a location description module configured to generate a description table indicating whether data in memory locations in the portion of the dynamic random access memory are valid or invalid, wherein data initially written to a first memory location corresponding to a logical address are indicated as valid, and in response to new data being written to a second memory location corresponding to the logical address, the data in the first memory location are indicated as invalid, and wherein in response to the control module writing additional data to the portion of the dynamic random access memory, a rate of adding data to the portion becomes equal to a rate at which data in memory locations in the portion becomes invalid so that the collected first data is written in the portion without first merging the collected first data.