Patent ID: 8667377

Claim:
A block code decoder, comprising: a first decoder configured and arranged to decode Bose-Chaudhuri-Hochquenghem (BCH) coded data packets, the first decoder including: a first memory buffer configured and arranged to receive BCH encoded data; one or more BCH decoder circuits coupled to the first memory buffer and each BCH decoder circuit configured and arranged to decode in parallel a plurality of BCH encoded bits included in the BCH encoded data; and a second memory buffer coupled to the one or more BCH decoder circuits for storage of decoded BCH data, the decoded BCH data including Reed-Solomon (RS) encoded data; and a second decoder, including: a third memory buffer coupled to the second memory buffer and configured and arranged to receive the decoded BCH data from the first decoder; one or more RS decoder circuits coupled to the third memory buffer, each RS decoder circuit configured and arranged to decode in parallel a plurality of RS encoded bits included in the decoded BCH data; and a fourth memory buffer coupled to the one or more RS decoder circuits for storage of RS-decoded data.