Patent ID: 8026607

Claim:
A semiconductor apparatus having a configuration in which a plurality of copper wiring layers and a plurality of insulating layers are alternately layered, and including wiring formed occupying a predetermined region, wherein the wiring includes: a first wiring pattern formed in a first copper wiring layer, including a plurality of copper wiring members which are formed in parallel with predetermined intervals, and each of which has a rectangular shape extending in a first direction; and a second wiring pattern formed in a second copper wiring layer adjacent to the first copper wiring layer, including a plurality of copper wiring members which are formed in parallel with predetermined intervals, and each of which has a rectangular shape extending in a second direction orthogonal to the first direction, and wherein the region occupied by the first copper wiring pattern, the region occupied by the second copper wiring pattern, and the aforementioned predetermined region at least overlap, and wherein the first wiring pattern and the second wiring pattern are electrically connected to each other so as to have the same electric potential.