Patent ID: 8010716

Claim:
A multiprocessor system, comprising: a plurality of processors operatively coupled to one another over one or more communication busses; and a configurable interface circuit operating in a first mode and a second mode, either simultaneously or alternatively, in response to one or more control signals, where: (i) the first mode provides a coherent symmetric interface interconnecting the multiprocessor system and one or more external devices, and maintains cache coherency between one or more memories of the multiprocessor and one or more memories of the one or more external devices; and (ii) the second mode provides a non-coherent interface interconnecting the multiprocessor system and one or more external devices, and provides at least some memory protection of the one or more memories of the multiprocessor, wherein the configurable interface circuit includes a coherent bus having a logical extension with first and second interfaces, each interface operating in one of the first mode and the second mode in response to the one or more control signals.