Patent ID: 7479915

Claim:
A comparator to provide a comparison result of voltage levels of a first input signal and a second input signal, said comparator comprising: a capacitor having a first terminal and a second terminal; a transistor and a constant current sink together operating as a follower circuit, said transistor when ON providing a current path between a first terminal and a second terminal to said current sink, said transistor also having a control terminal coupled to said second terminal of said capacitor at a node; a latch having a first input terminal, a second input terminal and an output terminal; a first switch, a second switch, a third switch and a fourth switch, each having a first terminal and a second terminal, said first switch connecting said first input signal to said first terminal of said capacitor in a closed position and disconnecting said first input signal from said first terminal of said capacitor in a open position, said second switch connecting said second input signal to said first terminal of said capacitor in a closed position and disconnecting said second input signal from said first terminal of said capacitor in a open position, said third switch connecting said node to a first bias voltage in a closed position and disconnecting said node from said first bias voltage in an open position, said fourth switch connecting an output of said follower circuit to said first input terminal of said latch in a closed position and disconnecting said output of said followed circuit from said first input terminal of said latch in a open position, wherein said first switch and said third switch are closed in a first duration to charge said capacitor to a voltage equaling the difference of said first bias voltage and said first input, wherein said second switch is closed and said third switch and said first switch are opened in a second duration to cause a control voltage at said node to equal said bias voltage plus the difference of voltages of said first input signal and said second input signal, wherein said fourth switch is closed during said second duration to cause said control voltage minus a threshold voltage across said control terminal and said second terminal of said transistor to provided on said first input terminal of said latch, and whereby said output terminal of said latch provides said comparison result in the form of a binary value.