Patent ID: 8898529

Claim:
A circuit arrangement for controlling a masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs, wherein m is <N and wherein the masked test data are compacted by a compactor with N data inputs and n data outputs and m<N applies, the circuit arrangement comprising: a first circuit component for masking the test data, which comprises N data inputs for input of N-digit binary unmasked test data, N control inputs for input of the binary control signals for masking the corresponding digits of the test data and N outputs for outputting the values of the masked test data bits corresponding to the control signals; and a second circuit component with N binary inputs and N binary outputs for providing control signals, such that the N binary outputs are connected to the N control inputs of the first circuit component and wherein the first circuit component has a first serially loadable register with N memory elements, a second loadable register with likewise N memory elements for storing test pattern-dependent masking data and a third serially loadable register likewise with N memory elements for storing test-dependent masking data, wherein the following applies: the input of the ith memory element of the second register is connected, for i=1, . . . , N, logically directly with the ith input terminal of the second circuit component, if a first binary value is stored in the ith memory element, the input of the ith memory element of the second register is connected, for i=2, . . . , N, with the output of the (i−1)th memory element of the second register, if a value is stored in the ith memory element of the first register which is different from the first binary value, the output of the jth memory element of the second register is connected, for j=1, . . . , N−1, logically directly with the input of the (j+k)th memory element of this register, if the binary values b, b, . . . , b, −b are stored in the jth, (j+1)th, . . . , (j+k−1)th memory element of the third register, and for k=1, . . . , N the output of the kth memory element of the second register is connected with the first input in each case of a kth logic gate with two inputs and one output, of which the second input is connected with the output of the kth memory element of the third register, wherein the output of the kth gate with two inputs and one output conveys the kth binary digit of the masking signal and is connected with the kth control input of the first circuit component, and wherein the logic gate with two inputs and one output in each case has a controlling value.