Patent ID: 7936855

Claim:
An oversampling data recovery circuit for a receiver, comprising: a first sampling circuit for sampling an input data upon a first clock to generate a first sample data; a second sampling circuit for sampling the input data upon a second clock to generate a second sample data; a third sampling circuit for sampling the input data upon a third clock to generate a third sample data; an edge detector, coupled to the first, the second and the third sampling circuits, for determining an edge of the input data by monitoring the first, second and third sample data, to thereby generate a detection signal; a state machine, coupled to the edge detector, for generating a selection signal in response to the detection signal; and a multiplexer, coupled to the first, the second and the third sampling circuits, the edge detector and the state machine, the multiplexer being used for selecting one of the first, second and third sample data onto an output data of the oversampling data recovery circuit according to the selection signal; wherein the first clock leads the second clock a first time and the second clock leads the third clock a second time.