Patent ID: 7593251

Claim:
A method for using a memory device comprising a plurality of memory cells, each memory cell comprising: a field effect memory transistor comprising a nanowire covered by a type of memory molecules, a field effect access transistor comprising a nanowire covered by the same type of memory molecules, a source of the access transistor connected to a drain of the memory transistor, an access transistor gate connected to a word line, and a memory transistor gate connected to a write line; the method comprising: erasing data stored in the memory transistor by: simultaneously applying a zero voltage to a memory transistor source and an erase voltage to the memory transistor gate, and at the same time setting an access transistor drain and the access transistor gate to floating state, then applying a zero voltage to the memory transistor gate and to the access transistor gate, and then applying a zero voltage to the access transistor drain.