Patent ID: 8700807

Claim:
A baseboard management controller for monitoring a host, comprising: a baseboard management control module comprising: a microprocessor for performing data processing; at least one controller for performing management and control operations; and a microprocessor bus being connected with the microprocessor and each of the at least one controller; a memory controller being connected with the microprocessor bus for controlling accesses of program codes and data; and a video graphic array (VGA) module comprising: a video controller being connected with the memory controller for controlling inputs, outputs and displays of video data; a decoder being connected with a first local bus of the host for receiving a transaction signal from the first local bus and decoding a first address signal contained in the transaction signal to determine whether to transfer the transaction signal, wherein the transaction signal at least comprises the first address signal and a command; a select circuit for selectively transferring data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal; and a mapping circuit being connected with an output port of the decoder for mapping the first address signal and a predetermined second address signal to a third address signal, updating the first address signal and transferring an updated transaction signal to the microprocessor bus; wherein when the first address signal points to an aperture allocated in a VGA section of a memory space of the host, the decoder transfers the transaction signal to the mapping circuit; wherein when the first address signal points to a frame buffer address region allocated in the VGA section, the decoder transfers the transaction signal to the memory controller; wherein when the first address signal points to a video controller address region allocated in the VGA section, the decoder transfers the transaction signal to the video controller; wherein the aperture does not overlap with the frame buffer address region and the video controller address region in the VGA section; and wherein the predetermined second address signal points to a target block in a memory space of the microprocessor.