Patent ID: 7110484

Claim:
A method for selecting a clock signal from a plurality of parallel clock signals received from a plurality of parallel transmission paths in a digital data transmission, comprising the steps of: receiving, at a unit comprising a changeover device, parallel clock signals from at least two parallel transmission paths, the parallel clock signals being generated from a single originating signal, a first clock signal of the parallel clock signals being designated the selected clock signal and being transmitted to an output of the unit; requesting, by the changeover device, a change of the selected clock signal from the first clock signal to a second clock signal of the parallel clock signals based on an indication received from a phase locked loop of an unreliability in locking the first clock signal; determining whether the first and second clock signals are both in a predetermined mode and determining whether a polarity of a signal phase difference of the first and second clock signals is inverted, thereby indicating the same phase or a phase shift of 180°; generating a first signal when it is determined that the first and second clock signals are in the predetermined mode, initiating a time delay when it is determined that the polarity of the signal phase difference of the first and second clock signals is inverted, and generating a second signal after the time delay has elapsed; and changing the selected clock signal to the second clock signal in response to said step of requesting and when said first and second signals are present, whereby said step of changing occurs proximate a phase coincidence of the first and second clock signals.