Patent ID: 8659066

Claim:
An integrated circuit comprising: a transistor including: a first semiconductor layer; a gate stack located on the first semiconductor layer, the gate stack comprising a metal layer and a first high-k dielectric layer; a gate spacer located on sidewalls of the gate stack, the first high-k dielectric layer being located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer; first and second source/drain regions formed in a second semiconductor layer that is located on and in contact with the first semiconductor layer, the first and second source/drain regions being located on opposite sides of the gate stack; a first silicide region located on the first source/drain region; and a second silicide region located on the second source/drain region; and a capacitor including: a first terminal comprising a third silicide region located on a portion of the second semiconductor layer that is located on and in contact with the first semiconductor layer; a second high-k dielectric layer located on the third silicide region; and a second terminal comprising a metal layer that is located on the second high-k dielectric layer.