Patent ID: 7423456

Claim:
A circuit comprising: a phase decision circuit having first and second inputs coupled to receive first and second clock signals, respectively, the phase decision circuit operable to determine a phase relationship between the first and second clock signals and to provide a first logic signal corresponding to the determined phase relationship; a latch circuit coupled to the phase decision circuit, the latch circuit operable to store the logic state of the first logic signal responsive to a predetermined transition of both a first delayed clock signal and a second delayed clock signal; and a first delay line coupled to the first input terminal to receive the first input clock signal and a second delay line coupled to the second input terminal to receive the second input clock signal, the first and second delay lines configured to generate and provide to the latch circuit the first delayed clock signal relative to the first input clock signal and the second delayed clock signal relative to the second input clock signal to cause the latch circuit to store the logic state of the first logic signal responsive to a predetermined transition of both the first and second delayed clock signals.