Patent ID: 7915667

Claim:
An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising: a fin structure extending in a first direction, the fin structure comprising: a first memory cell structure comprising a plurality of first active regions of a first plurality of memory cells coupled with each other in serial connection in the first direction; a second memory cell structure comprising a plurality of second active regions of a second plurality of memory cells coupled with each other in serial connection in the first direction, wherein the second memory cell structure is disposed above the first memory cell structure; a memory cell contact structure configured to electrically couple the first memory cell structure and the second memory cell structure, wherein the memory cell contact structure has a staircase structure, a first step of which is configured to electrically contact the first memory cell structure, and a second step of which is configured to electrically contact the second memory cell structure; and wherein the first step and the second step each comprises a first doped region doped with doping atoms of a first conductivity type, wherein the memory cell contact structure further comprises second doped regions doped with doping atoms of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second doped regions are disposed next to the first doped regions in the first direction.