Patent ID: 7301178

Claim:
A pressed-contact type semiconductor device comprising: a first conductivity type of semiconductor substrate; a first diffusion layer formed by diffusing a second conductivity type of impurities on a first side of the semiconductor substrate; a fourth diffusion layer formed by diffusing a first conductivity type of impurities on the first side of the semiconductor substrate so as to be shallower than the first diffusion layer; a gate electrode provided on the first side of the semiconductor substrate so as to be in contact with the first diffusion layer; a first electrode provided on the first side of the semiconductor substrate so as to be in contact with the fourth diffusion layer; a second diffusion layer locally formed by diffusing the second conductivity type of impurities on a second side of the semiconductor substrate so as to be exposed on a lateral side of the substrate; a third diffusion layer locally formed by diffusing the second conductivity type of impurities on the second side of the semiconductor substrate so as not to be exposed on the lateral side of the substrate; and a second electrode provided on the second side of the semiconductor substrate so as to be in contact with the third diffusion layer, wherein a lifetime control region having a lifetime shorter than that of the semiconductor substrate is formed at a periphery along the lateral side of the substrate, and an internal interface of the lifetime control region is provided inward from a portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other, and wherein the portion where the internal interface of the second diffusion layer and the internal interface of the third diffusion layer intersect with each other is disposed outward from the most outer diameter of the second electrode, and a depth D 1 of the first diffusion layer from the first side of the semiconductor substrate, a depth D 2 of the second diffusion layer from the second side of the semiconductor substrate and a depth D 3 of the third diffusion layer from the second side of the semiconductor substrate have a relation of D 1 >D 2 >D 3 .