Patent ID: 8782584

Claim:
A method for reworking a plurality of cells initially placed in a circuit design, the method comprising: a computer ordering the plurality of cells of a circuit design to form an inflation cell set such that each cell of the circuit design is assigned a corresponding weight calculated from an aggregate routing cost of the cell divided by a cell width of the cell, wherein the aggregate routing cost is a weighted combination of at least two of the group consisting of a count of pins in the cell, pin area cost, and a cost based on a sum for all cells of the plurality of cells of a sum for each cell of each rectangular area that encloses each pair of pins of the cell; the computer arranging the plurality of cells by each corresponding weight, to form an ordered inflation cell set having a corresponding order; the computer adding to a subset of cells, each cell of the ordered inflation cell set in the corresponding order, until the cells in the subset of cells, as processed by an operation, exceed a predetermined proportion of an assigned semiconductor area, wherein the operation comprises: growing a cell to form a growth area summed to an accumulated growth, and comparing the accumulated growth to the predetermined proportion; and, in response to the accumulated growth exceeding the predetermined proportion; the computer legalizing the subset of cells to form overlap-free placement of the cells in the assigned semiconductor area.