Patent ID: 8806399

Claim:
A method comprising: receiving a high-level design language representation of an integrated circuit design; executing, using a processor, a design synthesis process on the high-level design language representation of the integrated circuit design to obtain a netlist for the integrated circuit design; controlling a flow of the design synthesis process using script commands provided to the design synthesis process in a script file, wherein the script commands comprise a plurality of retiming commands; and performing a retiming operation on the netlist of the integrated circuit design based on the plurality of retiming commands in the script file, wherein each of the plurality of retiming commands is associated with a different optimization of the netlist, wherein each of the different optimizations of the netlist is selected from a group consisting of handling of register power-up conditions, modifying asynchronous signals in registers, avoiding the creation of bad behavior in the integrated circuit design due to metastability, avoiding bad behavior in the integrated circuit design by retiming between unrelated clock domains, prohibiting user-specified types of retiming, creating options to prohibit user-specified types of retiming in the netlist, and inferring don't touch conditions on specific types of registers.