Patent ID: 7038946

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array with electrically erasable and programmable memory cells arranged therein: a read/write circuit configured to hold write data, which is to be written into the memory cell array, and read data of the memory cell array; and a controller configured to control data read and write of the memory cell array; wherein a data read operation for reading out data of the memory cell array to the read/write circuit is so performed as to interrupt a data write operation for writing data into the memory cell array, wherein the data write operation is performed by repeat of write voltage application and following write verify, wherein the data read operation interrupts the data write operation at a timing of switching the write voltage application and write verify, thereby suspending the data write operation, and wherein the data read operation is performed in response to read command and address inputs; a read data output operation is performed in response to a read enable signal; and when the data read operation is ended and a chip is ready to output the read data, the suspended data write operation restarts.