Patent ID: 8438363

Claim:
A system for virtualizing a processor and protecting paging cache, comprising: a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures; a Virtual Machine (VM) running guest code and having at least one set of guest paging structures that are mapped to guest physical pages in guest address space using linear addresses; and a plurality of paging trees maintained by a Virtual Machine Monitor (VMM) and stored in a paging cache, wherein the paging trees correspond to guest physical memory, wherein at least one paging tree is active and corresponds to an active control register value and is protected, and other paging trees are inactive and correspond to inactive control register values and are unprotected, wherein inactive paging trees are open for reads and writes, and wherein, upon a context switch, a Translation Lookaside Buffer (TLB) is flushed, and cached paging trees are validated for any changes prior to changing the active control register value.