Patent ID: 8307319

Claim:
A method of manufacturing an integrated circuit having reduced electromigration effect, wherein the integrated circuit comprises one or more interconnects, each interconnect of said one or more interconnects comprising a dielectric layer made of a material having a Young's modulus at a first defined value linked to the material of the dielectric layer, characterized in that said method comprises: identifying one or more characteristics of said each interconnect; determining, at a computer, a minimum process distance from said each interconnect for the application of one or more first metal dummies; calculating, at the computer, a required correction parameter which can correct the Young's modulus at said first defined value linked to the material of the dielectric layer; calculating, at the computer, a required number of the first metal dummies which have a Young's modulus at a second defined value linked to the material of the dummies, such that the second defined value provides the required correction parameter for the first defined value linked to the material of the dielectric layer by using the Blech product; and determining, at the computer, where to apply a plurality of said first metal dummies around the interconnect at said minimum process distance to provide a corrected Young's modulus at a combined value of the first defined value and the second defined value.