Patent ID: 7570537

Claim:
A memory device comprising: a first word line; and a first static random access memory (SRAM) cell comprising: first and second cross-coupled logic gates adapted to maintain voltages at a first node and a second node, wherein the voltages of the first and second nodes correspond to a logic state stored by the first and second cross-coupled logic gates, and a first power switch circuit comprising: a first switch connected with a power source and the first cross-coupled logic gate, the first switch is adapted to selectively connect the power source with the first cross-coupled logic gate in response to a first logic signal, a second switch connected with the power source and the second cross-coupled logic gate, the second switch is adapted to selectively connect the power source with the second cross-coupled logic gate in response to a second logic signal, and a third switch connected with the power source and the first cross-coupled logic gate, the third switch is adapted to selectively connect the power source with the first cross-coupled logic gate in response to a third logic signal applied to the first word line.