Patent ID: 8278709

Claim:
A high voltage metal-oxide-semiconductor (HVMOS) transistor, comprising: a gate, wherein a channel is formed in an area projected from the gate in a thickness direction when the HVMOS is activated; two carrier drain drift regions, adjacent to the area projected from the gate; and two carrier plus regions, respectively located within the two carrier drain drift regions, each carrier plus region is completely encompassed by each corresponding carrier drain drift region, wherein the two carrier plus regions and the two carrier drain drift regions are communicating with each other through the channel when the HVMOS is activated, wherein at least one of the carrier drain drift region comprises a first region, a second region and a third region, which are sequentially disposed from the channel to the carrier plus region, and the carrier drain drift region has a gradient doping concentration increased from the first region, the second region to the third region, wherein the carrier plus region directly contacts at least two of the first region, the second region and the third region.