Patent ID: 7139206

Claim:
A memory component, comprising: a memory cell array; a plurality of signal inputs; a plurality of input amplifiers, respectively connected to the plurality of signal inputs, for receiving, amplifying and outputting at least one of data signals, address signals and control signals; a data/address/control signal generator for the memory cell array; a first supply network for supplying power to the input amplifiers; a second supply network for supplying power to the data/address/control signal generator; a first external power input connected to the first supply network; and a second external power input connected to the second supply network; wherein the first supply network and the second supply network are constructed as separate supply networks; wherein the first supply network is connected to the first external power input via a first input inductance and the second supply network is connected to one of the first external power input and a second external power input via a second input inductance; and wherein signal paths via the signal inputs and a signal path via the first supply network and the first external power input have substantially identical transfer functions for a transmission of signals to the input amplifiers from outside the memory component.