Patent ID: 7935602

Claim:
A semiconductor processing method, comprising: providing a semiconductor material; forming a trench extending into the semiconductor material, the trench having a maximum cross-sectional width extending transversely across the trench at the widest portion of the trench of less than or equal to about 100 nanometers and the trench having a length extending orthogonally to the width; forming liner material containing an oxide over an entirety of both a lower periphery and an upper periphery of the trench by oxidation of the semiconductor material; anisotropically etching the liner material to remove the liner material from at least a portion of the lower periphery while leaving the liner material along the upper periphery of the trench as a liner protecting the upper periphery of the trench, the unlined portion of the trench including an entirety of a bottom of the trench; while protecting the upper periphery, etching through the unlined portion to form a bulbous extension of the trench; the etching utilizing an etch that is anisotropic, followed by an etch that is at least substantially isotropic; the isotropic etch using NF 3 and further using a HBr moderating agent that suppresses lateral etching; the bulbous extension being relatively circular along at least one cross-section, including smooth corners where the bulbous extension transitions with the trench, and having a maximum cross-sectional width that is at least 10 nanometers greater than the maximum width of the trench; controlling a ratio of NF 3 to HBr for the isotropic etching to control smoothness of the corners and to etch less than or equal to about 70% downward relative to the amount of etching laterally; after forming the bulbous extension, removing the liner from the trench; after removing the liner, substantially filling the trench with insulative material to form an isolation region extending into the semiconductor material, the isolation region comprising a bulbous bottom portion where the insulative material extends into the bulbous extension; and forming a pair of transistors to be supported by the semiconductor material; each of the individual transistors comprising a gate over the semiconductor material and comprising source/drain regions extending into the semiconductor material; one of the transistors being a first transistor comprising a first gate and first source/drain regions, and the other of the transistors being a second transistor comprising a second gate and second source/drain regions; one of the first source/drain regions being in contact with one side of the isolation region, and one of the second source/drain regions being in contact with a side opposing said one side of the isolation region; the isolation region thus electrically isolating the first and second transistors from one another; neither of the first transistor gate and the second transistor gate having any region directly over any portion of the bulbous bottom portion of the isolation region.