Patent ID: 7146597

Claim:
A computer-aided design method of interconnections of a semiconductor integrated circuit based upon a wiring grid, the wiring grid implemented by a plurality of regularly spaced first lines and a plurality of regularly spaced second lines intersecting with the first lines, comprising: determining a direction of a subject wiring level in a multi-level interconnection of semiconductor integrated circuit as a subject-level priority direction with reference to the wiring grid; designing a layout of the subject wiring level, by placing a subject-level strip extending along the subject-level priority direction in the subject wiring level; generating a subject-level extension extending in a different direction of the subject-level priority direction, from a termination of the subject-level strip, so that a dimension of the subject-level extension measured along the subject-level priority direction is larger than a width of the subject-level strip; allocating a plurality of via-holes in the subject-level extension at the intersecting points of the wiring grid along a direction in which the subject-level extension extend, leaving a margin along the subject-level priority direction; and designing a layout of a neighboring wiring level of the subject wiring level in the multi-level interconnection, by placing a neighboring-level strip extending along the same direction as the subject-level extension extends, so that a termination of the neighboring-level strip can include the via-holes.