Patent ID: 7046042

Claim:
A phase detector, comprising: a first bistable circuit, wherein the first bistable circuit is configured to receive a reference clock signal, and wherein an output of the first bistable circuit is in communication with a first inverter circuit; and a second bistable circuit, wherein the second bistable circuit is configured to receive a feedback clock signal, wherein an output of the second bistable circuit is in communication with a second inverter circuit, wherein an output of the first inverter circuit is in communication with a first conjunction circuit and a third inverter circuit, wherein an output of the second inverter circuit is in communication with a second conjunction circuit and a fourth inverter circuit, wherein an output of the third inverter circuit is in communication with the second conjunction circuit, wherein an output of the fourth inverter circuit is in communication with the first conjunction circuit, and wherein the first conjunction circuit is configured to output a first alignment signal when the feedback clock signal is earlier than the reference clock signal and the second conjunction circuit is configured to output a second alignment signal when the feedback clock signal is later than the reference clock signal.