Patent ID: 8015534

Claim:
A method for estimating the size of a core section of a semiconductor integrated circuit, wherein the core section includes a plurality of nets, each including a plurality of wires, the method comprising: calculating, by a processor, an average path length of the wires in each net based on cell quantity, average cell area, total macro area, and cell usage rate to calculate a total net length of the wires of the nets; estimating, by the processor, a core section area based on the cell quantity, the average cell area, the cell usage rate and Rent's exponent to calculate usable channel length of the core section, the total net length of the wires being the sum of the lengths of a plurality of first wires extending in a predetermined first direction within the core section and the lengths of a plurality of second wires extending in a second direction perpendicular to the first direction within the core section, and the usable channel length being the sum of a channel length in the first direction and a channel length in the second direction within the core section; calculating, by the processor, a total length of the first wires within the core section; calculating, by the processor, a total length of the second wires within the core section; and determining, by the processor, the size of the core section, which is the minimal area that satisfies conditions of the total net length of the wires being less than or equal to the usable channel length within the core section, the total length of the first wires being less than or equal to the channel length in the first direction within the core section, and the total length of the second wires being less than or equal to the channel length in the second direction within the core section.