Patent ID: 8006244

Claim:
A method for execution of multiple independent threads in a processor comprising: using a priority buffer for granting priority to one of the multiple independent threads; loading a thread number associated with one of the multiple independent threads in the priority buffer; using an arbiter to issue a grant to one of the plurality of independent threads; using a plurality of state machines wherein each one of the plurality of state machines controls one of the threads within the multiple independent threads by issuing a request to the arbiter, stop issuing the request when the thread stalls due to a latency event, wherein the arbiter issues the grant upon receiving the request and transferring the grant to another one of the threads within the multiple independent threads when the request stops; keeping the thread number, for said one of the threads within the multiple independent threads, at a current position in the priority buffer, if the latency event is a short type; and moving the thread number, for said one of the thread within the multiple independent threads, to a position lower than the current position, if the latency event is a long type.