Patent ID: 7382161

Claim:
A non-inverting dynamic register, comprising: a domino stage, for evaluating a logic function based on at least one input data signal and a pulsed clock signal, wherein said domino stage pre-discharges a pre-discharged node low when said pulsed clock signal is high and opens an evaluation window when said pulsed clock signal goes low, and pulls said pre-discharged node high if it evaluates, and keeps said pre-discharged node low if it fails to evaluate; a mux, coupled to said domino stage, responsive to said pulsed clock signal and said pre-discharged node, which pulls a feedback node high if said pre-discharged node goes high during said evaluation window, and which pulls said feedback node low if said pre-discharged node is low during said evaluation window, and which receives a delayed feedback signal having the same state as said feedback node, but lagging in time, wherein said delayed feedback signal is selected when said pulsed clock signal goes high; and an output stage, coupled to said pre-discharged node and said feedback node, which provides an output signal based on states of said pre-discharged and said feedback nodes.