Patent ID: 7093150

Claim:
An arrangement of integrated circuit cells comprising: at least one cell comprising a root clock source generating a root clock signal; at least one other cell having at least one clock domain, said at least one clock domain having a clock source generating a time-delayed clock signal which is a time-delayed version of the root clock signal, wherein the time delayed clock signal is delayed with respect to the root clock signal by a time corresponding to a data propagation delay for data to propagate from the root clock source to the clock source of the clock domain; at least one data line; and at least one delay element, wherein said integrated circuit cells are arranged in a row including a first cell situated at a first end of said row, wherein the at least one cell is said first cell, and wherein the at least one clock domain is associated with the root clock of the first cell, the row further comprising a second cell having a clock source and being situated at a second end of the row, wherein the at least one data line, and the at least one delay element electrically couple the first cell to the second cell, and are adapted to cause a time-delay to the electrical signals travelling therethrough to bring data signals in phase with the clock source of the second cell into phase at the first cell with the root clock source.