Patent ID: RE38720

Claim:
An image motion compensating address generator for a generating addresses of a memory, comprising: mode selector means for selecting a field mode or frame mode according to a video mode signal indicative of whether an input video signal is a frame unit or field unit and a slice position signal indicative of the position of a slice, to thereby control the video signal to be processed; address selection controller means for controlling the generation of the addresses according to the video mode signal and a motion coding type signal indicative of the video processing mode of a block to be processed; Y-direction read address generator means for producing a Y-direction read address the addresses in units of processed block by using the signal output from the mode selector means according to and the address selection controller means , a Y-direction motion vector signal, and a vertical field selection signal; X-direction read address generator means for dividing the processed block into four phases in the X direction and generating an X-direction read address by using a processed-block position signal indicative of the position of the processed block and an X-direction motion vector signal according to the address selection controller means; X-direction write address generator means for delaying the processed-block position signal and a field processed-block clock signal, and generating the X-direction write address of four phases, to thereby write read-out video data; Y-direction write address generator means for producing a Y-direction write address by using the signal output from of the mode selector means according to the address selection controller means and the X-direction write address generator means, to thereby write read-out video data ; and read & write controller means for selectively outputting the X-direction and Y-direction read and write addresses according to a read/write selection toggle signal and an X-direction a motion vector signal among the X-direction and Y-direction read and write addresses output from the Y-direction read address generator means , X-direction read address generator means, X-direction write address generator means and Y-direction write address generator means .