Patent ID: 7659165

Claim:
A method of fabricating a field effect transistor in which at least one vertically aligned semiconductor column of a diameter in the nanometer range is present between a source electrode and a drain electrode and is annularly surrounded by a gate electrode with an insulating space between them, the method comprising: free-standing semiconductor columns are grown vertically on a conductive substrate; a first insulating layer is deposited on the semiconductor columns; a first conductive metal layer and a second insulating layer are deposited thereon; the developing laminate is etched planar to the point of the portion of the first conductive metal layer covering the semiconductor columns is removed again; the end of the first conductive metal layer penetrating to the surface of the laminate are etched back in a metal-specific manner and a third insulating layer is deposited on the laminate with subsequent renewed planar etching; or the ends of the first conductive metal layer penetrating to the surface of the laminate are converted to an insulator by oxidizing or nitriding; and finally depositing a second conductive metal layer on the laminate.