Patent ID: 8513103

Claim:
A method for manufacturing a junction of a vertical transistor, comprising: forming a trench in a semiconductor substrate to form first and second wall bodies, wherein the trench has sidewalls comprising a first side surface of the second wall body and a second side surface of the first wall body; forming a one side contact mask having an opening that selectively exposes a portion of only the first side surface of the second wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer in the second wall body by diffusing impurities having different diffusivities into the second wall body through the exposed portion of the first side surface, wherein the impurity used for forming the first impurity layer comprises arsenic (As) and the impurity used for forming the second impurity layer comprises phosphorus (P), and wherein the concentration of phosphorus (P) in the second impurity layer is less than the concentration of arsenic (As) in the first impurity layer.