Patent ID: 8638006

Claim:
A semiconductor apparatus comprising: a master chip and at least one slave chip configured to be stacked one on top of another; and a through-silicon via (TSV) configured to penetrate and electrically couple the master chip and the at least one slave chip, wherein the at least one slave chip receives a reference voltage generated from the master chip via the TSV and independently trims the reference voltage and then generates an internal voltage with the trimmed reference voltage, wherein the master chip includes a reference voltage generating unit, and the reference voltage generating unit includes: a control voltage output unit configured to output a control voltage configured to have a level corresponding to a level of an external power supply voltage; a pull-up driving unit configured to pull up a reference voltage output terminal with a current amount corresponding to a voltage difference between the control voltage and the external power supply voltage; and a loading unit configured to be coupled between the reference voltage output terminal and a ground voltage terminal and form the reference voltage configured to have a level corresponding to its resistance value at the reference voltage output terminal.