Patent ID: 7471103

Claim:
A method of operating a logic gate, which includes a first input circuitry, a second input circuitry, an output drive circuitry, and a logic gate output node, for implementing complex logic within a memory array, wherein an output node is coupled to the first input circuitry and the second input circuitry, and wherein the output drive circuitry is coupled to the output node and the logic gate output node, the method comprising the steps of: receiving, by the first input circuitry, a first storage cell signal, a second storage cell signal, and a first external signal; receiving, by the second input circuitry, the first storage cell signal, the second storage cell signal, and a second external signal; wherein the same first storage cell signal and the same second storage cell signal are received by both the first input circuitry and the second input circuitry; performing, in the logic gate, one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal; wherein the first input circuitry includes: a first pull-up transistor connected to the first storage cell signal; a second pull-up transistor connected to the first external signal; a first pull-down transistor connected to the first external signal; and a second pull-down transistor connected to the second storage cell signal, wherein a drain of the first pull-up transistor is coupled to a source of the second pull-up transistor, wherein the first pull-down transistor is coupled to the second pull-down transistor, wherein the first pull-up transistor is coupled to a drain voltage, wherein the second pull-down transistor is coupled to a ground, and wherein the second pull-up transistor is coupled to the first pull-down transistor and to the output node; and wherein the second input circuitry includes: a first pull-up transistor connected to the second storage cell signal; a second pull-up transistor connected to the second external signal; a first pull-down transistor connected to the second external signal; and a second pull-down transistor connected to the first storage cell signal wherein a drain of the first pull-up transistor is coupled to a source of the second pull-up transistor, wherein the first pull-down transistor is coupled to the second pull-down transistor, wherein the first pull-up transistor is coupled to a drain voltage, wherein the second pull-down transistor is coupled to a ground, and wherein the second pull-up transistor is coupled to the first pull-down transistor and to the output node.