Patent ID: 7498216

Claim:
A method of forming an integrated circuit structure, said method comprising: providing a first semiconductor wafer comprising at least a first semiconductor layer, having a first crystalline orientation; providing a second semiconductor wafer comprising at least a second semiconductor layer, having a second crystalline orientation different from said first crystalline orientation; bonding said first semiconductor wafer to said second semiconductor wafer to form a laminated structure comprising at least: said first semiconductor layer; said second semiconductor layer; and an insulator layer between said first semiconductor layer and said second semiconductor layer; etching openings in said laminated structure through said first semiconductor layer and said insulator layer to said second semiconductor layer; forming insulating sidewall spacers in said openings; growing additional semiconductor material with said second crystalline orientation on said second semiconductor layer in said openings to fill said openings such that said additional material in said openings is positioned laterally adjacent to and isolated from remaining portions of said first semiconductor layer; patterning semiconductor fins in said remaining portions of said first semiconductor layer and in said additional semiconductor material in said openings; forming at least one first fin-type field effect transistor using said semiconductor fins patterned in said remaining portions of said first semiconductor layer; forming at least one second fin-type field effect transistor, having a different conductivity type than said first fin-type field effect transistor, using semiconductor fins patterned in said additional semiconductor material in said openings; and forming a straining layer on opposing sidewalls of said semiconductor fins.