Patent ID: 7671644

Claim:
A delay line comprising: a phase detector having two inputs and a single output, said first input of said phase detector connected to an input of said delay line, said second input of said phase detector connected to an output of said delay line, said output of said phase detector connected to a switch; a charge current source directly connected to a first terminal of said switch, a second terminal of said switch being directly connected to a voltage control node, such that said charge current source is selectively connected to a voltage-control node through said switch in response to the output of said phase detector to supply current to said voltage-control node; a control current source connected to said voltage-control node and to said second terminal of said switch constantly for withdrawing current from said voltage control node; a capacitor located in parallel with said control current source; and a voltage-controlled delay unit having two inputs and one output, said first input of said voltage-controlled delay unit connected to said voltage-control node, said second input of said voltage-controlled delay unit connected to said input of said delay line, and said output of said voltage-controlled delay unit being the output of said delay line.