Patent ID: 7510961

Claim:
A method for manufacturing an interconnect structure consisting essentially of: forming a recess within a dielectric material situated on a semiconductor substrate, the recess extending below a top surface of the dielectric material; forming a diffusion barrier layer substantially conformally on the top surface of the dielectric material and over an interior surface of the recess; forming a seed layer on the diffusion barrier layer over the top surface of the dielectric material and within the recess, wherein the seed layer comprises tungsten and wherein the diffusion barrier layer is a different material than the seed layer; forming an electrically conductive layer on the seed layer over the top surface of the dielectric material and substantially within the recess such that voids are present within the recess, the material of the diffusion barrier layer having a melting point greater than a melting point of a material of the electrically conductive layer, the material of the seed layer having a melting point greater than or equal to a melting point of the material of the electrically conductive layer; forming an energy absorbing layer on the electrically conductive layer, a material of the energy absorbing layer having a greater thermal absorption capacity than the thermal absorption capacity of the material of the electrically conductive layer; applying energy and pressure to the energy absorbing layer sufficient to cause the electrically conductive layer to fill the voids within the recess; and removing portions of the energy absorbing layer and the electrically conductive layer that are situated above the top surface of the dielectric material.