Patent ID: 6955958

Claim:
A method of manufacturing a semiconductor device, comprising: forming a P-poly gate and an N-poly gate on a P type element region and an N element region, respectively, of a semiconductor substrate electrically isolated by an element isolating layer; shielding the P type element region and lightly ion-doping the N type impurities selectively to a predetermined N-LDD region around the N-poly gate; forming an oxide layer for regulating the ion-implantation on the front face of the semiconductor substrate so as to cover the P-poly gate and the N-poly gate; shielding the N type element region and lightly ion-doping the P type impurities selectively to a predetermined P-LDD region around the P-poly gate using the oxide layer for regulating the ion-implantation as a buffer mask; removing the oxide layer for regulating the ion-implantation, forming spacers to the respective P-poly gate and the N-poly gate, and heavily ion-doping the P type and N type impurities selectively to a predetermined P-source/drain region and a predetermined N-source/drain region around the P-poly gate and the N-poly gate, respectively, using the respective spacers as buffer masks; and annealing the semiconductor substrate so as to diffuse the P type and N type impurities doped to the predetermined P-LDD and N-LDD regions and the predetermined P-source/drain and N-source/drain regions.