Patent ID: 7444448

Claim:
A dynamic source synchronized sampling adjust system for sampling a plurality of data packets distributed among a plurality of sequential data beats on a data bus during each of at least one cycle of a bus clock, wherein at least one data strobe is provided indicating validity of each of the plurality of data packets, said dynamic source synchronized sampling adjust system comprising: a plurality of first multiplexers, each having a first input for coupling to the data bus, a second input receiving a corresponding one of a plurality of latched data packets, a select input receiving a corresponding one of a plurality of select signals, and an output; a plurality of registers, each having an input coupled to an output of a corresponding one of said plurality of first multiplexers, an output providing a corresponding one of said plurality of latched data packets, and a clock input for receiving the at least one data strobe; at least one second multiplexer having a plurality of inputs coupled to corresponding outputs of said plurality of registers, an output providing a selected one of said plurality of latched data packets, and a select input receiving a read pointer; and timing logic having at least one input for receiving the at least one data strobe and a plurality of outputs providing said plurality of select signals.