Patent ID: 7326632

Claim:
A method for fabricating metal wirings of a semiconductor, comprising: forming an etch stop layer on a semiconductor substrate; forming an inter metal dielectric on the etch stop layer; forming a via hole in the inter metal dielectric so as to expose the etch stop layer; forming a trench on the inter metal dielectric so as to expose the via hole; removing the etch stop layer exposed through the via hole; removing any striations formed on an inner wall of the trench; thermally treating the semiconductor substrate in an environment of heavy hydrogen at a temperature in the range of 200 to 300 degrees Celsius for 10 to 30 seconds after the removing of any striations so as to remove polymer particles existing in the inner walls of the trench; and forming a metal wiring filled inside the via hole and the trench; wherein removing any striations includes wet etching in an etchant made by mixing alkalic solution, H2O2, and distilled water in a ratio of 1:4:4 to 20, at a temperature in a range of about 30 to about 45 degrees Celsius.