Patent ID: 7453298

Claim:
A PWM controller comprising: an input; a first PWM control channel configured to form a first PWM drive signal to control a first switch and form a first output voltage; the first PWM control channel including a first clock circuit configured to form a first clock signal that is used to form the first PWM drive signal wherein the first clock circuit is configured to adjust a frequency of the first clock signal responsively to a clock control signal; a second PWM control channel configured to form a second PWM drive signal to control a second switch and form a second output voltage; the second PWM control channel including a second clock circuit configured to form a second clock signal that is used to form the second PWM drive signal wherein the second clock circuit is configured to adjust a frequency of the second clock signal responsively to the clock control signal; a voltage to current converter circuit coupled to the input to supply a current to the input and form a control voltage; a capacitor coupled to selectively receive the control voltage to form the clock control signal; a first timing circuit configured to decouple the capacitor from receiving the control voltage responsively to the second clock signal; a second timing circuit configured to decouple the capacitor from receiving the control voltage responsively to the second PWM drive signal; and a control circuit configured to decouple the capacitor from receiving the control voltage responsively to the first drive PWM signal.