Patent ID: 8502324

Claim:
A semiconductor wafer comprising: at least a first die; at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die; and a first alignment mark group used for aligning the wafer to a tool used for patterning the wafer, the first alignment mark group located entirely within the area between the first die and the second die, wherein the first alignment mark group includes a first plurality of alignment lines and wherein each line of the first plurality of alignment lines is formed using a first plurality of discontinuous segments separated from each other by a first plurality of gaps filled with an insulating material; a second alignment mark group used for aligning the wafer to a tool used for patterning the wafer, the second alignment mark group located entirely within the area between first die and the second die, wherein the second alignment mark group includes a second plurality of alignment lines, and wherein each line of the second plurality of alignment lines is formed using a second plurality of discontinuous segments separated from each other by a second plurality of gaps filled with an insulating material; and a reference mark positioned between the first alignment mark group and the second alignment mark group that functions as a nominal alignment center.