Patent ID: 7823115

Claim:
A method of balancing delay in an integrated circuit using a computer, said method comprising: providing, using said computer, nodes to be joined into a wiring design, wherein requirements of said wiring design provide that the time needed for a signal to travel along a first wiring path be about the same time needed for a signal to travel along a second wiring path, and wherein said first wiring path and said second wiring path traverse multiple levels of said integrated circuit; and designing, using said computer, said first wiring path and said second wiring path to traverse wire segments of about the same length within in each wiring level of said integrated circuit, wherein said designing process further comprises selecting, using said computer, the order of vertical and horizontal line segments that make up said first wiring path and said second wiring path to avoid blockages and minimize average congestion along said first wiring path and said second wiring path.