Patent ID: 6957378

Claim:
A semiconductor memory device comprising: a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of said normal data section; a data buffer for temporal stage of read data from said cell array and write data into the cell array; and an error checking and correcting circuit for generating the check data to be stored in said parity data section from write data as input during data writing, and for performing error check and correction of data read out of said normal section based on the data read out of said normal data section and the check data read out of said parity data section during data reading, wherein n-bit parallel data transfer is performed between said data buffer and said normal data section of said cell array, whereas m-bit parallel data transfer is done between said data buffer and external input/output terminals (where m and n are integers satisfying m<n), n-bit data including m-bit data to be rewritten is read in parallel in a first half period of a data write cycle while letting error check and correction of the n-bit data be done at said error checking and correcting circuit, and a to-be-written m-bit data portion of the n-bit parallel data as has been corrected at said error checking and correcting circuit is replaced with m-bit parallel data as supplied from the external input/output terminals in a second half period of the data write cycle and then sent forth to said normal data section.