Patent ID: 8470685

Claim:
A method of forming a plurality of air cavity trenches in-between metal lines of an integrated circuit, said method comprising the steps of: forming a self-aligned barrier on a top surface of a metal line of a semiconductor interconnect structure and on a top surface of another metal line of the semiconductor interconnect structure, each self-aligned barrier forming a cap on its metal line; after forming the self-aligned barriers, depositing a dielectric liner on the semiconductor interconnect structure using a conformal deposition process; removing part of the dielectric liner on the semiconductor interconnect structure using a directional etching process; successively repeating at least once the steps of depositing the dielectric liner and removing part of the dielectric liner so as to achieve a desired width of the remaining dielectric liner on the interconnect structure based on the desired width of the air cavity trench in-between the metal lines; and forming at least one air cavity trench in-between the metal line of the semiconductor interconnect structure and the other metal line of the semiconductor interconnect structure by selectively etching an intertrack dielectric layer of the semiconductor interconnect structure using the self-aligned barriers on the top surfaces of the metal lines and the remaining dielectric liner on the interconnect structure as an etching mask, the intertrack dielectric layer being located between the metal lines of the semiconductor interconnect structure, wherein when the step of depositing the dielectric liner is first performed, the top surfaces of the metal lines are substantially coplanar with a top surface of the intertrack dielectric layer.