Patent ID: 7186612

Claim:
A method of making an integrated circuit in a semiconductor substrate, the method comprising: forming at least two isolation regions in the semiconductor substrate; forming a well between the two isolation regions, the well defining a body region; forming a first oxide layer above a first portion of the body region; forming a first dielectric layer above the first oxide layer; forming a first polysilicon layer above said first dielectric layer, said first polysilicon layer forming a control gate of a non-volatile device; forming a second dielectric layer above the first polysilicon layer; forming a first spacer above the body region and adjacent said first polysilicon layer; forming a second oxide layer above a second portion of the body region not covered by said first spacer; forming a second polysilicon layer above the second oxide layer, the first spacer and a portion of the second dielectric layer; said second polysilicon layer forming a guiding gate of the non-volatile device and a gate of an MOS transistor; forming lightly doped areas in the body region; forming a second spacer above the body region to define source and drain regions of the non-volatile device and source and drain regions of the MOS transistor; delivering second implants to the defined source and drain regions; forming a third polysilicon layer over portions of the lightly doped areas in the body region to form polysilicon landing pads; forming a third dielectric layer over the formed polysilicon landing pads; and forming a fourth polysilicon layer over the third dielectric layer.