Patent ID: 7528748

Claim:
A serial data receiving circuit detecting a k-bit (k being a natural number) synchronization pattern from serial data transmitted serially in successive m-bit (m being a natural number) data bit groups having an LSB first bit sequence or an MSB first bit sequence, and outputting the data bit groups that were correctly partitioned into m bits, the serial data receiving circuit comprising: a shift register circuit capturing the serial data consisting of at least (m+k−1) bits and outputting m different bit strings consisting of k bits, with bits from bit 1 to bit m each being handled as start points, every time the shift register circuit receives the serial data consisting of m bits; a comparison circuit performing a coincidence detection operation on each of the bit strings to detect coincidence with the synchronization pattern; a selector circuit that selecting and outputting the bit strings which were subjected to the coincidence detection operation in the comparison circuit; and a conversion circuit provided in a connection path between the shift register circuit and the comparison circuit or in an output path of the selector circuit, the conversion circuit performing a conversion operation in which a bit sequence of the bit strings is reversed every m-bits starting from a head bit.