Patent ID: 8809851

Claim:
A semiconductor device comprising: a plurality of memory cells each comprising a first transistor, a second transistor, and a capacitor, the first transistor comprising: a first channel formation region; a first insulating layer over the first channel formation region; a first gate electrode over the first channel formation region with the first insulating layer interposed therebetween; and a first electrode and a second electrode which are electrically connected to the first channel formation region, the second transistor comprising: an oxide semiconductor layer comprising a second channel formation region and an offset region in contact with the second channel formation region; a third electrode and a fourth electrode which are electrically connected to the oxide semiconductor layer; a second insulating layer over the oxide semiconductor layer, the third electrode, and the fourth electrode; and a second gate electrode over the second channel formation region with the second insulating layer interposed therebetween, and wherein the first gate electrode, the third electrode, and one electrode of the capacitor are electrically connected to one another.