Patent ID: 6884637

Claim:
An inspection pattern formed on a semiconductor wafer for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer, comprising: a plurality of lower-layer wiring portions arranged so as to be spaced at a distance; a plurality of upper-layer wiring portions arranged so as to be spaced at a distance; an insulating layer provided between the plurality of lower-layer wiring portions and the plurality of upper-layer wiring portions; a plurality of contact units which electrically connects the plurality of lower-layer wiring portions and the plurality of upper-layer wiring portions so as to form a contact chain including the plurality of lower-layer wiring portions and the plurality of upper-layer wiring portions alternately connected in series; and a pair of electrode terminals, one of the electrode terminals being electrically connected to one end of the contact chain, the other of the electrode terminals being electrically connected to the other end of the contact chain; wherein a length of each of the plurality of lower-layer wiring portions, a length of each of the plurality of upper-layer wiring portions, and a position of each of the plurality of contact units are set in such a way that an interval between ones of the plurality of contact units adjacent to each other in a longitudinal direction of the lower-layer wiring portion or the upper-layer wiring portion is no longer than 50 μm.