Patent ID: 8624641

Claim:
An apparatus comprising: a first switching circuit configured to receive a differential data signal and a first bias voltage, wherein the first switching circuit is configured to convert the differential data signal to a first PMOS drive signal and a second PMOS drive signal for a first PMOS driver transistor and a second PMOS driver transistor, respectively, wherein the first switching circuit is configured to change a state of the first and second PMOS drive signals in response to a change in state of the data signal, wherein a first state of the first or second PMOS drive signal turns on the corresponding PMOS driver transistor and has a voltage level of the first bias voltage, wherein a second state of the first or second PMOS drive signal turns off the corresponding PMOS driver transistor; a second switching circuit configured to receive the differential data signal and a second bias voltage, wherein the second switching circuit is configured to convert the differential data signal to a first NMOS drive signal and a second NMOS drive signal for a first NMOS driver transistor and a second NMOS driver transistor, wherein the second switching circuit is configured to change a state of the NMOS drive signal in response to a change in state of the data signal, wherein a first state of the first or second NMOS drive signal turns on the corresponding NMOS driver transistor and has a voltage level of the second bias voltage, and wherein a second state of the first or second NMOS drive signal turns off the corresponding NMOS driver transistor; a first multiplexer configured to select at least between a first signal input and a second signal input different from the first signal input by phase and/or delay to generate the differential data signal for the first switching circuit and the second switching circuit; a third switching circuit configured to receive a second differential data signal and configured to convert the second differential data signal to third and fourth PMOS drive signals for third and fourth PMOS driver transistors, respectively; a fourth switching circuit configured to receive the second differential data signal and configured to convert the second differential data signal to third and fourth NMOS drive signals for third and fourth NMOS driver transistors, respectively; and a second multiplexer configured to select at least between a first signal input and a second signal input different from the first signal input by phase and/or delay to generate the second differential data signal, wherein the first multiplexer and the second multiplexer select the same signal for normal operation and select different signals for a squelch mode.