Patent ID: 8000151

Claim:
A method of operating a plurality of memory cell transistors fabricated in a well to form an array of rows and columns in which the memory cell transistors in the same column are connected to each other in series and are selectively connected to a respective bit line, the method comprising: using a plurality of high voltage transistors to selectively isolate the bit lines from a memory device circuit during at least a portion of an erase operation, each of the high voltage transistors having reverse breakdown electrical characteristics that are substantially greater than reverse breakdown electrical characteristics of the plurality of memory cell transistors; applying an erase voltage to the well; biasing a bit line to a non-zero voltage less than the erase voltage, the difference in potentials between the bit line and the first well being less than a breakdown voltage of an additional transistor to which the bit line is connected that is fabricated in the well; and using each of the high voltage transistors to selectively couple a respective pair of adjacent bit lines to the memory device circuit.