Patent ID: 8006000

Claim:
An information processing apparatus in which a processor unit is connected with a peripheral device, wherein: the processor unit and the peripheral device are connected by a bridge, which relays an input and output bus of at least one peripheral device of a plurality of peripheral devices to an input and output bus of the processor unit by use of an upstream port and a downstream port, the processor unit includes an address converter having an address conversion table for converting an effective address into a physical address, the address conversion table storing the effective address of an area, in a memory of the processor unit, allocated to each peripheral device, in association with identification information defined to identify, in the processor unit, a peripheral device permitted to access the effective address, the peripheral device issues an access request packet, which designates the effective address corresponding to the peripheral device, when accessing the memory, the access request packet including device identification information by which the peripheral device can be uniquely identified and containing a number of bits larger than the bit length of the identification information stored in the address conversion table, the bridge acquires an access command from the access request packet such that the bridge acquires verification information from the device identification information and the effective address, the verification information having of a bit length that matches the bit length of the identification information and includes the verification information in the access command, and the address converter determines whether to permit access to the effective address under the condition that the verification information included in the access command matches the identification information included in the address conversion table and corresponding to the effective address designated by the access command.