Patent ID: 8438345

Claim:
A multi-priority encoder comprising: a highest-priority single-priority encoder configured to indicate only a first match output signal corresponding to a first match line input signal; and one or more lower-priority single-priority encoders arranged in descending priority order, each configured to indicate only a lower-priority match output signal corresponding to a lower-priority match line input signal, wherein each of the single-priority encoders is comprised of at least as many single-priority stages as there are match line input signals, the single-priority stages being arranged in descending order, each stage having a match line input, a NAND gate, an inverter, an OR gate and a NOR gate whose output is a match output so that each single priority encoder is configured to detect multiple simultaneous active match line input signals and to indicate via only one of the match outputs a match output signal corresponding to a match line input signal not indicated by any other single-priority encoder in the multi-priority encoder.