Patent ID: 8429578

Claim:
A method of verifying a logic circuit group including a decoder that decodes a selection signal that are inputted to the decoders and selects a selected output signal line among a plurality of signal lines, the method executed by a computer comprising: recognizing, by the computer, each of the signal lines in a circuit group based on design information regarding the circuit group; recognizing, by the computer, logic elements located on an input side of the circuit group based on the design information by using each of the recognized signal lines as a starting point; recognizing, by the computer, a circuit area including a logic element and an inverter as a decoder circuit area, the logic element and the inverter operating as an AND gate, the logic element and the inverter being able to output a signal having a logical value “1”; determining, by the computer, a combination of logical values of selection signals inputted to the recognized decoder circuit area when a logical value of the starting point is logical value “1”; determining, by the computer, whether a logical configuration of the recognized decoder circuit area is correct based on the number of the selection signals inputted to recognized decoder circuit area and the combination of logical values of the selection signals; and outputting, by the computer, a determination result, wherein the logical configuration of the recognized decoder circuit area is determined correct when the number of the selection signals inputted to the recognized decoder circuit area is the same as the number of bits represented by the selection signals for selecting the selected signal line, and when all of the combination of logical values of the selection signals inputted to the decoder circuit areas are different from one another, each of the combination of logical values of the selection signals causing anyone of the decoder circuit area to output a signal having a logical value “1”.