Patent ID: 8320209

Claim:
A memory circuit comprising: a first memory cell node comprising a first memory cell node capacitor electrically coupled to a first memory cell node transistor, a second memory cell node comprising a second memory cell node capacitor electrically coupled to a second memory cell node transistor, a pre-charging circuit that pre-charges said first memory cell node to a first voltage level and said second memory cell node to a second voltage level, respectively, a reference memory cell comprising a first reference cell transistor, a second reference cell transistor, and an equalizing transistor that is arranged between said first reference cell transistor and said second reference cell transistor, and a sense amplifier that detects a potential difference between a reference bit line from said reference memory cell and a bit line from said first or second memory cell node during a read operation of the memory circuit, wherein said first reference cell transistor, said second reference cell transistor and said equalizing transistor perform a first voltage equalization of said first memory cell node and said second memory cell node at a predetermined voltage and a second voltage equalization of said first memory cell node and said second memory cell node based on one of a first reference signal and a second reference signal that are respectively input to said first reference cell transistor and said second reference cell transistor.