Patent ID: 8456403

Claim:
A liquid crystal display, comprising: a liquid crystal display panel including a plurality of data lines, a plurality of gate lines crossing the data lines, and pixels arranged in m×n matrix, where m and n are positive integers; an EEPROM configured to store frame rotation reference information, line rotation reference information, and polarity pattern information; a timing controller configured to generate a polarity control signal to control polarities of data voltages charged in the data lines of the liquid crystal display panel based on the information read from the EEPROM; and source drive ICs configured to convert the polarities of the data voltages supplied to the data lines in response to the polarity control signal, wherein the timing controller comprises: a first counter configured to: count frame periods for which a vertical polarity control signal is repeated according to the frame rotation reference information from the EEPROM, and output a frame count value, a second counter configured to: count lines for which the vertical polarity control signal is repeated according to the line rotation reference information from the EEPROM, and output a line count value, a register configured to: store the polarity pattern information from the EEPROM, select a polarity pattern information synchronized with the frame count value from the first counter and the line count value from the second counter among the polarity pattern information, and output the selected polarity pattern information, and a polarity control signal generating unit configured to: detect a frame currently displayed on the liquid crystal display panel based on the frame count value from the first counter, detect a line for displaying current data on the liquid crystal display panel based on the line count value from the second counter, and invert a logic of the polarity control signal according to the selected polarity pattern information from the register.