Patent ID: 7689884

Claim:
An integrated circuit chip, comprising: a test input configured to receive test data; an expectation input for receiving expected result data; at least two circuitry cores, each core having a core test input and a core test output, each core being configured to receive test data from the test input at its core test input, to generate test result data according to the received test data, and further configured to provide the generated test result data at its core test output; comparator circuitry configured to compare for each core the test result data from the core test outputs and the received expected result data to detect for each core whether or not there is a mismatch between the test result data and the received expected result data; a mask logic unit which is configured to receive the received expected result data from the expectation input and to generate mask data from the expected result data by analyzing whether the values of expected mask data remain stable during a whole clock cycle, wherein the comparator circuitry is further arranged to receive mask data indicating for each of the circuitry cores whether or not the comparison of the test result data with the received expected result data is to be masked; and a memory configured to store for each core a mismatch indication.