Patent ID: 8276014

Claim:
Data processing circuitry for processing data, said data processing circuitry comprising: a plurality of synchronisation circuits for capturing and transmitting said data in response to a clock signal and a plurality of combinational circuits arranged between said synchronisation circuits for processing said data, said plurality of synchronisation circuits being arranged in at least two groups; an error detecting circuit for determining if said data input to one of said plurality of synchronisation circuits is stable during a predetermined time and for signalling an error if said data input is unstable; control circuitry responsive to said error detecting circuit signalling said error to transmit a control signal to at least one of said groups of synchronisation circuits that contains a subsequent synchronisation circuit that said synchronisation circuit with said unstable input is configured to transmit said data to; each of said group of synchronisation circuits being configured to respond to receipt of said control signal to transmit a stall signal to at least one further group of synchronisation circuits that said group of synchronisation circuits is configured to transmit data to or receive data from; each of said group of synchronisation circuits being configured to respond to receipt of said stall signal provided they have not stalled in the preceding clock cycle to stall for a clock cycle and to transmit a stall signal to said at least one further group of synchronisation circuits.