Patent ID: 8680652

Claim:
A stack package comprising: a first semiconductor chip including a first surface having a first pad and a second pad disposed thereon, and a second surface facing away from the first surface; a second semiconductor chip including a third surface having a third pad and a fourth pad disposed thereon, and a fourth surface which facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pad are electrically connected with the second pad; connection members electrically connecting the first pad with the third pad and the second pad with the fourth pad; a substrate including a fifth surface attached to the fourth surface of the second semiconductor chip and having a first connection pad and a second connection pad disposed thereon, and a sixth surface facing away from the fifth surface and having third connection pads disposed thereon; first redistribution line disposed on the third surface of the second semiconductor chip and having first end electrically connected with the third pad and second end extending to a first edge of the third surface; second redistribution line disposed on the third surface of the second semiconductor chip and having first end electrically connected with the fourth pad and second end extending to a second edge of the third surface opposite the first edge; a capacitor including a first electrodes electrically connected with the second end of the first redistribution line, a second electrode electrically connected with the first connection pad of the substrate, and a dielectric interposed between the first electrode and second electrode; and an interconnection member connecting the second end of the second redistribution line with the second connection pad of the substrate.