Patent ID: 7039667

Claim:
A compressor of a multiplier comprising: a first compressor, wherein said first compressor comprises: a first plurality of inputs; a first summation output; a first carry bit output; a first plurality of transistor paths connecting each of said first plurality of inputs to said summation output, wherein a first compressor critical transistor stage path level within said first compressor is less than seven; a second carry bit output; a second plurality of transistor paths connecting each of said first plurality of inputs to said second carry bit output; and a successive compressor, wherein said successive compressor comprises: a second plurality of inputs; a second summation output; and said compressor of a multiplier further comprising: a plurality of successive transistor paths connecting at least one of said first plurality of inputs to said first carry bit output of said first compressor, connecting said first carry bit output to at least one of said second plurality of inputs between said first compressor and said second compressor and connecting at least one of the second plurality of inputs to said second summation output of said successive compressor, wherein a successive compressor critical transistor stage path level within said successive compressor is less than eight; wherein each of said first plurality of transistor paths, each of said second plurality of transistor paths, and each of said plurality of successive transistor paths comprises a plurality of switches and a plurality of inverters; wherein said switches and said inverters form a plurality of logic stages for each of said first plurality of inputs; and wherein a first compressor critical logic stage path level is three within said first compressor and a successive compressor critical logic stage path level is three within said successive compressor.