Patent ID: 7210017

Claim:
An information processing apparatus comprising: a memory unit that has a predetermined burst length and is operable to transfer block data, using a wraparound method, to/from a memory block that is constituted by a plurality of consecutive memory cells in the memory unit and has a length equal to the predetermined burst length; and a memory control unit that is connected to the memory unit by a bus used for both address transfer and data transfer, wherein the memory control unit includes an output subunit operable to output a first command and a second command, when the transfer of the block data to/from the memory block starts with transfer of data to/from an intermediate memory cell in the memory block, the intermediate memory cell being a memory cell other than an initial memory cell in the memory block, the first command instructing the memory unit to transfer data to/from each of the plurality of memory cells in the memory block, except for a memory cell directly before the intermediate memory cell, the second command being output when a predetermined time has elapsed since the output of the first command, and instructing the memory unit to transfer data to/from the memory cell directly before the intermediate memory cell in the memory block, and the memory unit transfers the block data in accordance with the first command and the second command.