Patent ID: 7082482

Claim:
A data handling device comprising: a communication controller having a data gate provided for receiving data, a processor having an n-bit addressing capacity; a memory having a set of buffers; and a driving means provided for addressing the memory; wherein the communication controller, the processor, the memory and the driving means are connected to each other; and wherein the memory having a set of buffers further comprises: a first subset of buffers provided for storing data segments retrieved from the received data and is accessible to the processor through a buffer address indicating a buffer location in the memory, wherein the buffer address is generated by using a buffer descriptor stored in a buffer descriptor list; a second subset of buffers which is not accessible by the processor and is accessible by using a further buffer descriptor describing the second subset of buffers and where the further buffer descriptor is stored in the buffer descriptor list; and wherein the communication controller further comprises an interrupt generator provided for generating an interrupt signal upon transferring the received data segments into a buffer of the first subset of buffers; and wherein the processor further comprises a driver for passing the data segments to an application running on the processor ;and wherein the driving means manages the buffer descriptor list, and upon recognizing that an incoming data segment has been stored in a buffer of the second subset of buffers, transfers the data segment stored in the buffer of the second subset of buffers to a buffer of the first subset of buffers asynchronously while the application is running on the processor.