Patent ID: 7904700

Claim:
A circuit arrangement, comprising: processing logic configured to process instructions from an instruction stream, wherein the instructions in the instruction stream are selected from an instruction set that defines a vector instruction and a persistent swizzle instruction, and wherein the processing logic includes: a register file including a plurality of vector registers configured to store operand vectors, wherein each operand vector includes a plurality of words; vector execution logic configured to retrieve operand vectors from the register file and process the retrieved operand vectors responsive to vector instructions received by the processing logic; and at least one software-accessible swizzle special purpose register architected into the processing logic and configured to store state information for use in selectively shuffling words from operand vectors retrieved by the vector execution logic in connection with processing vector instructions received by the processing logic; and swizzle logic coupled to the processing logic and configured to selectively shuffle words from operand vectors retrieved from the register file by the vector execution logic in connection with processing of the retrieved operand vectors by the vector execution logic, wherein the swizzle logic is configured to, in response to a first persistent swizzle instruction received by the processing logic, persist state information for the swizzle logic in the at least one swizzle special purpose register, and wherein the swizzle logic is configured to, in response to a plurality of vector instructions received by the processing logic subsequent to reception of the first persistent swizzle instruction by the processing logic, selectively shuffle words from operand vectors retrieved from the register file by the vector execution logic in connection with processing the plurality of vector instructions using the state information persisted in the at least one swizzle special purpose register such that at least two vector instructions received by the processing logic subsequent to the first persistent swizzle instruction are processed using operand vectors selectively shuffled according to the state information persisted in the at least one swizzle special purpose register.