Patent ID: 7103790

Claim:
Memory controller driver circuitry ( FIG. 4 , 400 ), comprising: a data pad; FIG. 4 , DQ 4 ); N data propagation circuits (N≧2) ( FIG. 4 , 402 , 404 ); a multiplexing stage ( FIG. 4 , 406 ) which provides data to at least N−1 of the N data propagation circuits, said multiplexing stage enabling a coupling of a first data input stream ( FIG. 4 , 410 ) to each of the N data propagation circuits when the multiplexing stage is configured in a 1× mode, and said multiplexing stage enabling a coupling of different data input streams ( FIG. 4 , 410 , 412 ) to various of the N data propagation circuits when the multiplexing stage is configured in an M× mode (1<M≦N); and output merging circuitry ( FIG. 4 , 408 ) which alternately couples the N data propagation circuits to the data pad to thereby generate either a 1× or M× stream of data bits at the data pad.