Patent ID: 7622331

Claim:
A method comprising: forming a metal wiring layer over a semiconductor substrate; sequentially forming a diffusion barrier layer, an interlayer insulating layer, and a capping layer over the metal wiring layer; forming a hard mask layer over the capping layer; forming a photoresist layer over the hard mask layer; patterning the photoresist layer; forming a plurality of vias by sequentially etching the hard mask layer, the capping layer, and the interlayer insulating layer using the patterned photoresist layer as an etch mask until the diffusion barrier layer is exposed; performing plasma treatment process to remove byproducts which remain in the vias during the etching without damaging the capping layer due to the hard mask layer formed to suppress occurrences of tapering of the capping layer; depositing a metal layer in the plurality of vias to form contacts; and removing the metal layer and the hard mask layer until the capping layer is exposed.