Patent ID: 8406339

Claim:
A data processing apparatus configured to map input symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols, the data processing apparatus comprising: an interleaver configured to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and an address generator configured to generate the set of addresses, an address being generated for each of the input symbols for mapping the input data symbol on to one of the sub-carrier signals, the address generator comprising: a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit configured to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address, and a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately two thousand, the linear feedback shift register has ten register stages with a generator polynomial for the linear feedback shift register of R′ i [9]=R′ i-l [0]⊕R i-l [3], and the permutation code forms, with an additional bit, an eleven bit address, wherein the permutation circuit is configured to change the permutation code, which permutes the order of the bits of the register stages to form the addresses from one OFDM symbol to another.