Patent ID: 8415981

Claim:
An integrated circuit device comprising: at least one functional module arranged to receive at least one reference clock signal; at least one gating component configurable to perform gating of the at least one reference clock signal; and at least one synchronisation module; the at least one synchronisation module comprises: at least one trigger component arranged to receive at least one request for the at least one functional module, the at least one request being asynchronous with the at least one reference clock signal, and to set at least one enable signal for the at least one functional module in response to receiving the at least one request therefor; and at least one synchronisation component arranged to receive the at least one enable signal, and in response to the at least one enable signal being set to: configure the at least one gating component to un-gate the at least one reference clock signal; and synchronize an initial clock cycle of the reference clock signal received by the at least one functional module following the reference clock signal being un-gated.