Patent ID: 8450216

Claim:
A method for fabricating a field-effect transistor, comprising: providing a gate structure comprising sidewalls and a top surface over a substrate; forming a spacer adjacent to the sidewalls of the gate structure; forming silicide regions in the substrate on sides of the gate structure; depositing a first contact etch stop layer over the spacer and the top surface of the gate structure; depositing a first interlayer dielectric layer over the first contact etch stop layer; performing a chemical mechanical polishing on the first interlayer dielectric layer and first contact etch stop layer to expose the gate structure; depositing a second contact etch stop layer over the first interlayer dielectric layer and the top surface of the gate structure; and patterning the second contact etch stop layer to remove a portion of the second contact etch stop layer over the silicide regions, whereby the second contact etch stop layer remains over the gate structure but does not extend as far as up to the silicide regions.