Patent ID: 6943371

Claim:
A top-gate thin film transistor, comprising: a substrate; a buffer layer directly on the substrate: a patterned semiconductive layer formed directly on the buffer layer, wherein the patterned semiconductive layer comprises a channel region and source/drain regions adjacent to the channel region; a gate insulating layer formed on and completely covering the patterned semiconductive layer; a gate electrode formed on the gate insulating layer above the channel region; source and drain electrodes formed on the gate insulating layer adjacent to the semiconductive layer, wherein the gate, source and drain electrodes are formed simultaneously by one photolithography step; a dielectric layer formed on the gate insulating layer, the gate electrode, and the source/drain electrodes; first contact holes formed via the dielectric layer and the gate insulating layer exposing part of the surface of source/drain regions; second contact holes formed via the dielectric layer exposing part of the surface of source and drain electrodes: and a patterned conductive layer formed on predetermined parts of the dielectric layer electrically connecting the source/drain regions to the source/drain electrodes through the first and second contact holes.