Patent ID: 7539187

Claim:
A system for low-latency content-sensitive forward error correction comprising: a network; a first node selected from a group of nodes wherein said first node is coupled with said network and wherein said first node comprises: at least one packetizer; a checksum generator; a forward error correction module coupled with said checksum generator; a time clock to time stamp a first packet and a second packet wherein said time clock is coupled with said checksum generator; a packet multiplexer timestamper module coupled with said at least one packetizer and further coupled with said time clock and further coupled with said checksum generator and further coupled with said forward error correction module; said packet multiplexer timestamper module configured to filter packets based on a first packet type for processing by said forward error correction module and wherein said packet multiplexer timestamper is configured to transmit checksum packets based on a time obtained from said time clock; a plurality of second nodes selected from said group of nodes wherein said plurality of second nodes are coupled with said network and wherein said plurality of second nodes comprises: a receiver timestamper; a receiver time clock coupled with said receiver timestamper; a forward error correction processing and recovery module coupled with said timestamper comprising a packet filter coupled with at least one packet queue and at least one checksum queue wherein said forward error correction processing and recovery module further comprises a forward error correction engine coupled with said at least one packet queue and said at least one checksum queue; said forward error correction engine configured to output received packets in correct order with minimal latency; and, said first node configured to transmit to said plurality of said second nodes.