Patent ID: 6888840

Claim:
In a remodulator system, apparatus for controlling the bit rate of an output packet stream, comprising: a source of an input transport packet stream; an input packet buffer, coupled to the input transport packet stream source, for generating a status signal indicating whether the input packet buffer is: full, empty, or neither empty nor full; a control signal generator, responsive to the said status signal, and generating a control signal; a variable output clock signal generator, responsive to said control signal; and an output packet stream generator coupled to said input packet buffer, and responsive to a variable output clock signal, for generating said output packet stream in synchronism with said variable output clock signal wherein the variable clock signal generator is responsive to the control signal for varying the frequency of the output clock signal; and the control signal generator comprises circuitry to generate the control signal to condition the variable output clock signal generator to increase its frequency if the status signal indicates that the input packet buffer is full, and decrease its frequency if the status signal indicates that the input packet buffer is empty.