Patent ID: 7847616

Claim:
A balanced input inverter circuit comprising: a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output; a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential; a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor; a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit; a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor; and a second diode connected between the second power source potential and a second power source terminal of the second inverter circuit.