Patent ID: 6842864

Claim:
A method, comprising: writing a first set of data to a first address in a first memory device; writing a second set of data to a second address in a second memory device; reading the first set of data from the first memory device; reading the second set of data from the second memory device; determining a first access time corresponding to reading the first set of data from the first memory device; determining a second access time corresponding to reading the second set of data from the second memory device; and configuring at least one memory device of the first and second memory devices such that a difference between the first and second access times is reduced, wherein configuring the at least one memory device further comprises storing a first delay value in a first register and a second delay value in a second register in the at least one memory device, wherein the first and second delay values are summed to obtain a device delay value representing a delay for the at least one memory device.