Patent ID: 8871561

Claim:
A manufacturing method for manufacturing a variable resistance nonvolatile storage device, the method comprising: (a) forming plural lower lines above a substrate; (b) forming an interlayer insulating layer on the plural lower lines and above the substrate; (c) forming, in the interlayer insulating layer, plural memory cell holes penetrating to surfaces of the plural lower lines, an opening diameter of upper portions of the plural memory cell holes being smaller than an opening diameter of bottom portions; (d) forming a metal electrode layer at least on a bottom of each of the plural memory cell holes by sputtering; (e) embedding and forming a variable resistance layer in each of the plural memory cell holes, the variable resistance layer being connected to the metal electrode layer; and (f) forming, on the interlayer insulating layer and the variable resistance layer, plural upper lines connected to the variable resistance layer embedded and formed in each of the plural memory cell holes.