Patent ID: 8161469

Claim:
A method of comparing a first already-compiled programming file for a first programmable logic device to a second already-compiled programming file for a second programmable logic device different from said first programmable logic device, said method comprising: identifying, in said first already-compiled programming file, a representation of one or more functional features of said first programmable logic device, and identifying, in said second already-compiled programming file, a representation of one or more functional features of said second programmable logic device, said second programmable logic device being different from said first programmable logic device; establishing correspondence between one or more functional features of one programmable logic device selected from said first and second programmable logic devices, represented in one programming file selected from said first and second already-compiled programming files, and one or more functional features of another programmable logic device, selected from said first and second programmable logic devices, represented in another programming file selected from said first and second already-compiled programming files; and comparing each of one or more of said functional features of said one programmable logic device, selected from said first and second programmable logic devices, represented in said one programming file selected from said first and second already-compiled programming files, to a corresponding functional feature of said another programmable logic device selected from said first and second programmable logic devices represented in said another programming file selected from said first and second already-compiled programming files, said comparing comprising constructing binary description diagrams for each combinational logic block in a pair of combinational logic blocks to be compared, and comparing said binary description diagrams.