Patent ID: 6870789

Claim:
A retirement payload array comprised of modified column structures, each of said modified column structures comprising: a read bit line; a pre-charge device coupled to said read bit line; a sensing device coupled to said read bit line; at least one memory cell, said memory cell comprising an output coupled to said read bit line and an input; a gate, said gate comprising an output coupled to said input of said at least one memory cell and an input; a conditional read circuit, said conditional read circuit comprising a first input, a second input and an output, said conditional read circuit output being coupled to said input of said gate, a clock signal, said clock signal having a first or “A” phase and a second or “B” phase, said clock signal being coupled to said second input of said conditional read circuit; an advance pointer signal, said advance pointer signal having a first or inactive phase and a second or active phase, said second or active phase of said advance pointer signal corresponding to a shift in position of a read pointer, said advance pointer signal being coupled to said first input of said conditional read circuit, wherein; said conditional read circuit initiates a read of said retirement payload array only when, both: said clock signal is in said “B” phase; and said advance pointer signal is in said active phase wherein: said gate is a NOR-Gate comprising a first input, a second input and an output, further wherein; said conditional read circuit comprises: an inverter, said inverter having an input and an output; and a NAND-Gate having a first input, a second input, and an output, wherein; said inverter input is coupled to said clock signal and said inverter output is coupled to said NAND-Gate second input, further wherein; said NAND-Gate first input is coupled to said advance pointer signal and said NAND-Gate output is coupled to said NOR-Gate first input.