Patent ID: 7265707

Claim:
An A/D converter of an successive approximation type comprising: a sample hold circuit for retaining an input analog signal during a sampling period; a reference voltage generating circuit for generating a reference voltage compared to the retained input analog signal during a successive comparison period; a comparator for comparing the reference voltage generated by the reference voltage generating circuit to a value of the input analog signal retained in the sample hold circuit; a control circuit for successively controlling the reference voltage generating circuit so that a value of the reference voltage approximates to the value of the input analog signal retained in the sample hold circuit based on an output value of the comparator per bit; a buffering circuit for outputting an output value corresponding to an output voltage of the comparator; and a latch circuit for retaining the output value of the buffering circuit corresponding to the output value of the comparator per bit as a digital value, wherein a buffering control circuit for blocking a power supply to the buffering circuit during the sampling period is provided.