Patent ID: 8558383

Claim:
An integrated circuit chip comprising: a substrate; a MOS device on said substrate; a first contact pad over said substrate; a second contact pad over said substrate; a passivation layer over said substrate, wherein a first opening in said passivation layer is over a first contact point of said first contact pad, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second contact pad, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride; a patterned circuit layer over said passivation layer and on said first and second contact points, wherein said patterned circuit layer is connected to said first contact point through said first opening, and said patterned circuit layer is connected to said second contact point through said second opening, wherein said patterned circuit layer comprises a bottom metal layer over said passivation layer and on said first and second contact points, and electroplated copper directly over and in physical contact with said bottom metal layer; a first metal post on and in physical contact with said patterned circuit layer, wherein said first metal post is connected to said first contact point through said patterned circuit layer, wherein said first metal post is not vertically over said first contact point, wherein said first metal post comprises electroplated copper and has a height between 25 and 200 micrometers; a second metal post on and in physical contact with said patterned circuit layer, wherein said second metal post is connected to said second contact point through said patterned circuit layer, wherein said second metal post is not vertically over said second contact point, wherein said second metal post comprises electroplated copper and has a height between 25 and 200 micrometers, wherein a pitch between said first and second metal posts is less than 250 micrometers; a first polymer layer over said passivation layer and on said patterned circuit layer, wherein said first metal post is in said first polymer layer and has a top surface not covered by said first polymer layer, and wherein said second metal post is in said first polymer layer and has a top surface not covered by said first polymer layer, wherein said top surface of said first metal post and said top surface of said second metal post are substantially coplanar with a top surface of said first polymer layer; a UBM layer on said top surface of said first metal post and said top surface of said second metal post; a first electroplated solder bump on said UBM layer and vertically over said top surface of said first metal post; and a second electroplated solder bump on said UBM layer and vertically over said top surface of said second metal post.