Patent ID: 7310279

Claim:
A semiconductor memory device comprising: a memory cell provided at a point where a word line and bit lines intersect; a column selection switch for selectively connecting the bit lines to a data line; a bit line precharge circuit for precharging each of the bit lines to a predetermined level; high voltage precharge means for precharging a bit line selected by the column selection switch at a voltage of a level higher than a precharge voltage outputted by the bit line precharge circuit; a write amplifier connected to the bit lines via the column selection switch and which is for writing data into the corresponding memory cell through the bit line selected by the column selection switch, said write amplifier including the high voltage precharge means; and wherein the memory cell includes a storage section comprising an n channel type first MOS transistor and an n channel type second MOS transistor connected to each other, a p channel type third MOS transistor which is for connecting a drain electrode of the first MOS transistor and a gate electrode of the second MOS transistor to a first bit line, and a p channel type fourth MOS transistor which is for connecting a drain electrode of the second MOS transistor and a gate electrode of the first MOS transistor to the first bit line.