Patent ID: 7729195

Claim:
A semiconductor memory device, comprising: a block of sub-word line driver circuits (SWDB) disposed between a first block of memory and a second block of memory, wherein the SWDB comprises a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each comprising four SWD circuits extending in a first direction between the first and second blocks of memory, wherein two adjacent SWD columns comprises a SWD group for driving sub-word lines extending from the SWD group along the first direction into the first block of memory and for driving sub-word lines extending from the SWD group along the first direction into the second block of memory, wherein each of a first pair of SWD circuits in a first SWD column of the two adjacent columns and each of a first pair of SWD circuits in a second SWD column of the two adjacent columns share first common word line activation control signals, and wherein each of a second pair of SWD circuits in the first SWD column of the two adjacent columns and each of a second pair of SWD circuits in the second column of the two adjacent columns share second common word line activation signals.