Patent ID: 7962815

Claim:
A test access port formed in an integrated circuit on a substrate, comprising: A. a test access port controller having a test mode select input, a test clock input, and control outputs; B. a multiplexer having a test data output, a first input, and a second input; C. data registers having control inputs connected to the control outputs of the test access port controller, a test data input and a test data output, the test data output being connected to the first input of the multiplexer; D. an instruction register having control inputs connected to the control outputs of the controller, a test data input and a test data output, the instruction register being connected between the second input of the multiplexer and the test data input of the data registers, the instruction register having a select output; E. a scan cell separate from the instruction register connected in series with the instruction register between the second input of the multiplexer and the test data input of the data registers, the scan cell having a control input connected to the control inputs of the instruction register, and an address output; and F. a demultiplexer having a select input connected to the select output of the instruction register, a control input connected to the address output of the scan cell, a select output and a select one output, the demultiplexer including a first AND gate having one input connected with the select input, another input connected with the control input, and an output connected with the select output, an inverter having an input connected with the control input and an output, and a second AND gate having one input connected with the select input, another input connected with the output of the inverter, and an output connected with the select one output.