Patent ID: 6938176

Claim:
A processing device, including: at least two subsystems, including a first subsystem and a second subsystem; subsystem clock circuitry including at least a first subsystem clock branch coupled and configured to assert a first subsystem clock to the first subsystem and a second subsystem clock branch coupled and configured to assert a second subsystem clock to the second subsystem; and control circuitry coupled to the subsystem clock circuitry, wherein the control circuitry and the subsystem clock circuitry are configured to operate in a subsystem clock management mode in which the control circuitry prevents the first subsystem clock branch from asserting the first subsystem clock to the first subsystem when said first subsystem is idle, and the control circuitry prevents the second subsystem clock branch from asserting the second subsystem clock to the second subsystem when said second subsystem is idle; and wherein the control circuitry is further configured to cause either of the first or second subsystems to respond to an access even though the first or second subsystem is idle.