Patent ID: 7852690

Claim:
An electronic system comprising: a flash memory die comprising a plurality of flash memory cells, each flash memory cell having a storage resolution of at least four bits of data; a second die including a flash disk controller, wherein the flash disk controller comprises a nonvolatile memory, a processor, and a flash interface, wherein the nonvolatile memory comprises at least one cell resolution register configured to downwardly adjust the storage resolution of at least one of the plurality of flash memory cells to at least a single bit of data, wherein the processor is configured to receive and process commands for performing memory operations to manage the flash memory cells, and the flash interface is configured to access the flash memory cells according to the processor; a DRAM configured to temporarily store data for performing memory operations to manage the flash memory cells, wherein the DRAM is external to the flash memory die and the second die, and wherein the DRAM is accessible to at least the second die; and a multichip package that contains the flash memory die, the second die, and the DRAM.