Patent ID: 7736983

Claim:
A method of forming an NMOS transistor, comprising the steps of: providing a semiconductor substrate; forming a p-type well in and extending to a top surface of said semiconductor substrate; forming an NMOS gate dielectric layer on a top surface of said p-type well; forming an NMOS gate on a top surface of said NMOS gate dielectric layer; forming NMOS gate sidewall spacers on lateral surfaces of said NMOS gate; and forming n-type source-drain (NSD) regions in said p-type well adjacent to said NMOS gate sidewall spacers by a process comprising the steps of: ion implanting a species of an atomic weight greater than 27 in a region at said top surface of said p-type well adjacent to said NMOS gate sidewall spacers; ion implanting a carbon containing species in a region at said top surface of said p-type well adjacent to said NMOS gate sidewall spacers; and ion implanting a first dopant species, distinct from said species of an atomic weight greater than 27, in a region at said top surface of said p-type well adjacent to NMOS said gate sidewall spacers.