Patent ID: 7580519

Claim:
A security processing circuit for performing 3DES encryption or decryption services using a single DES engine, the security processing circuit comprising: the single DES engine operable to provide security processing, the single DES engine employing an intermediate result at a data output of the single DES engine, the single DES engine further comprising a data input node adapted to selectively process input data from a data input of the security processing circuit during a first DES processing operation, and subsequently to process the intermediate result data from the data output during a second and third DES processing operation, respectively; a select switch coupled to the data input of the security processing circuit, the data output, and the data input node of the single DES engine, the select switch adapted to selectively couple one of the data input and the intermediate result to the data input node of the single DES engine; a set of cipher keys selectively coupled to the single DES engine, wherein the security processing circuit is operable to select and load a different cipher key associated with each DES processing operation to the single DES engine during the three single DES processing operations of the 3DES security processing; and a clock input coupled to the single DES engine for timing clock cycles of the first, second and third single DES processing operations, wherein the 3DES processing is completed in eight clock cycles, or wherein the first, second and third DES processing operations have a duration comprising two clock cycles each.