Patent ID: 7284145

Claim:
A clock control circuit for supplying a valid clock signal to a target circuit in, characterized in that: if a valid input instruction signal changes from a disabled state to an enabled state, a supply of a clock signal to said target circuit starts in accordance with the system clock signal; and if a valid output instruction signal changes from the enabled state to the disabled state, a supply of said clock signal is stopped after a lapse of a period; counter setting signal generation means for setting a counter setting signal to an enabled state during a period from when a valid input instruction signal indicating timings of data input to said target circuit changes from a disabled state to an enabled state to when a valid output instruction signal indicating timings of data output from said target circuit changes from the disabled state to the enabled state; counter means being set with a continuation period count constant if said counter setting signal is in the enabled state immediately before said valid clock signal changes from a first state to a second state and for counting each time said valid clock signal changes from the first state to the second state; count detection means for setting a continuation period signal to the enabled state until said counter means completely counts a number corresponding to said continuation period count constant after said continuation period count constant is set to said counter means; enable signal generation means for setting a latch input signal to the enabled state if either said continuation period signal or said valid input instruction signal is in the enabled state; latch means for outputting said latch input signal itself as a latch output signal if said system clock signal is in said first state, and if said system clock signal is in the second state, outputting as the latch output signal said latch input signal immediately before said system clock signal changes from said first state to said second state; and valid clock output means for outputting said system clock signal as said valid clock signal if said latch output signal is in the enabled state.