Patent ID: 7285466

Claim:
A method of fabricating a unit cell of a metal oxide semiconductor (MOS) transistor comprising: forming a MOS transistor on an integrated circuit substrate, the MOS transistor having a source region, a drain region and a gate region, the gate region being between the source region and the drain region; forming first and second channel regions between the source and drain regions, the first and second channel regions being defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region, the first and second protrusions extending away from the integrated circuit substrate and upper surfaces of the first and second protrusions being substantially planar with upper surfaces of the source and drain regions; and forming a gate electrode in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.