Patent ID: 7508329

Claim:
A device for processing an N-bit digital input value generated by an analog-to-digital converter and generating a digital output signal, the digital input value being in a first unit being an arbitrary unit and the digital output signal being in a second unit being a natural unit of physical measurement and being related to the first unit by a first equation, the digital output signal for use by a host processor to process information captured by the analog-to-digital converter, the device comprising: a memory comprising a first memory portion and a second memory portion; the first memory portion having stored thereon Q delimiter values, the Q delimiter values dividing the range of the N-bit digital input value into Q+1 regions, at least a first region and a second region in the Q+1 regions being of unequal sizes; the second memory portion having stored thereon a look-up table storing Q+1 sets of coefficients for performing numerical value conversion of the digital input value in the first unit to the digital output value in the second unit, each set of coefficients comprising a coefficient pair of slope and offset coefficients and being associated with a respective one of the Q+1 regions of digital input values, the look-up table being indexed by a first indexing parameter to provide a selected coefficient pair of slope and offset coefficients, the first indexing parameter being selected to operate the device for non-linear conversion; and an arithmetic logic unit receiving the N-bit digital input value in the first unit and the selected coefficient pair of slope and offset coefficients from the look-up table in the second memory portion, the arithmetic logic unit performing numerical value conversion based on the first equation and computing the digital output value in the second unit using the N-bit digital input value and the selected coefficient pair, wherein the N-bit digital input value is compared with the Q delimiter values to determine a respective one of the Q+1 regions in which the N-bit digital input value lies and the first indexing parameter has a value indicative of the respective one of the Q+1 regions and being applied to the look-up table to provided the selected coefficient pair.