Patent ID: 8411506

Claim:
A non-volatile memory, comprising: a substrate; a plurality of first doped regions each having a stripe shape, disposed in the substrate and extending along a first direction; a plurality of second doped regions each having a stripe shape, disposed in the substrate and extending along the first direction, wherein the first doped regions and the second doped regions are arranged alternately; a charge-trapping structure, disposed on the substrate; a plurality of first gates each having a stripe shape, disposed on the charge-trapping structure and extending along the first direction, wherein each first gate is disposed on one of the first doped regions; a plurality of second gates each having a stripe shape, disposed on the charge-trapping structure, extending along a second direction and located on the second doped regions, wherein the second direction is different from the first direction; and an inter-gate insulating layer, disposed between the first gates and the second gates, wherein a first doped region, a second doped region adjacent to the first doped region, and a first gate, a second gate and the charge-trapped structure which are disposed between the first doped region and the second doped region define a memory cell.