Patent ID: 8081513

Claim:
A NAND flash memory, comprising: a NAND string made up of a plurality of memory cells connected in series to store information according to a threshold voltage corresponding to an amount of charge retained in a charge retaining layer, the memory cell including: the charge retaining layer which is formed on a well in a surface of a semiconductor substrate via a first insulating film and is isolated from a surrounding part by a plurality of insulating films including the first insulating film and a second insulating film; and a control gate provided on the charge retaining layer via the second insulating film, and a control circuit that controls operations of the memory cells by controlling voltages applied to the control gates and the well, wherein the control circuit injects charge into the charge retaining layer or removes charge from the charge retaining layer by applying a writing voltage between the control gate and the well during a writing operation, and then the control circuit releases charge having been trapped in the first insulating film provided between the well and the charge retaining layer, by applying a detrapping voltage between the control gate and the well before a verification reading operation, the detrapping voltage having a reversed polarity from the writing voltage and an absolute value smaller than an absolute value of the writing voltage, and wherein the well is a p-type semiconductor, the control circuit applies the writing voltage between the control gate of a selected memory cell in a selected NAND string and the well by applying a first voltage to the well and a positive second voltage higher than the first voltage to the control gate of the selected memory cell in the selected NAND string during the writing operation, and then the control circuit applies the detrapping voltage between the control gate of the selected memory cell in the selected NAND string and the well by applying a third voltage to the well and a negative fourth voltage lower than the third voltage to the control gate of the selected memory cell in the selected NAND string, and raises a potential of a control gate of an unselected memory cell in the selected NAND string close to the third voltage before the verification reading operation.