Patent ID: 8457021

Claim:
A repeater system, comprising: (a) a first antenna; (b) a first duplexer, wherein said first duplexer is operatively connected to said first antenna; (c) an uplink block, wherein said uplink block is operatively connected to said first duplexer; (d) a downlink block, wherein said downlink block is operatively connected to said first duplexer; (e) a second duplexer, wherein said second duplexer is operatively connected to said uplink block and to said downlink block; (f) a second antenna, wherein said second antenna is operatively connected to said second duplexer; (g) a mixed signal processor (MSP) comprising a first mixed-signal processor (MSP) operatively connected to said uplink block and a second mixed-signal processor (MSP) operatively connected to said downlink block; wherein said first mixed-signal processor (MSP) and said second mixed-signal processor (MSP) further comprise: (i) an analog-to-digital converter (ADC); (ii) a digital down-converter (DDC), wherein said digital down-converter (DDC) is operatively connected to said analog-to-digital converter (ADC); (iii) a receive (Rx) filter, wherein said receive (Rx) filter is operatively connected to said digital down-converter (DDC); (iv) an adder, wherein said adder is operatively connected to said receive (Rx) filter: (v) a configurable multi-band filter, wherein said configurable multi-band filter is operatively connected to said adder; (vi) a control central processing unit, wherein said control central processing unit is operatively connected to said configurable multi-band filter: (vii) a training signal generator; (viii) a splitting point; (ix) a switch, wherein said switch is operatively connected to said training signal generator, said configurable multi-band filter and to said splitting point; (x) a transmit (Tx) filter, wherein said transmit (Tx) filter is operatively connected to said splitting point; (xi) a digital up-converter (DUC), wherein said DUC is operatively connected to said transmit (Tx) filter; (xii) a digital-to-analog converter (DAC), wherein said digital-to-analog converter (DAC) is operatively connected to said digital up-down converter (DUC); (xiii) a cancellation filter, wherein said cancellation filter is operatively connected to said adder and to said splitting point; and, (xiv) an estimation algorithm execution unit, wherein said estimation algorithm execution unit is operatively connected to said adder, said cancellation filter and said training signal generator.