Patent ID: 8132133

Claim:
A method for testing a semiconductor chip design, wherein the chip includes a plurality of macros, each said macro including a respective pre-synthesized reusable circuit block having a respective at least one macro test input/output (I/O), and the method is included in a Design-For-Test (DFT) methodology, the method comprising: receiving as input in an electronic design automation (EDA) system a netlist for said semiconductor chip design and a respective set of parameters related to each of at least some of said plurality of macro test input/output (I/O)s, wherein each said respective set of parameters includes the respective macro test I/O name and a respective first set of attributes associated with the corresponding macro test I/O; responsive to receiving as input a netlist for said semiconductor chip design and a respective set of parameters related to each of at least some of said plurality of macro test I/Os, tracking using the EDA system each macro test I/O of said at least some of said plurality of macro test I/Os to a corresponding at least one chip test I/O, wherein each chip test I/O is included in the netlist; responsive to tracking each macro test I/O to a corresponding at least one chip test I/O, determining using the EDA system, for each macro test I/O of said at least some of said plurality of macro test I/Os, any mismatches between the respective first set of attributes associated with the corresponding macro test I/O and a respective second set of attributes associated with the corresponding at least one chip test I/O; and reporting using the EDA system the mismatches between a respective first set of attributes and the corresponding second set of attributes.