Patent ID: 7409162

Claim:
A method of reducing timing error in a quantum key distribution (QKD) system, comprising: a) providing with a clock having a periodic clock cycle a clock signal a clock signal period and a clock signal edge to a retimer; b) providing a digital timing signal from a programmable circuit to the retimer, wherein the digital timing signal has an amount of jitter; c) retiming the digital timing signal in the retimer and generating therefrom first and second retimed output signals; d) providing the first and second retimed output signals to respective first and second low-jitter logic delays; e) imposing a programmable relative delay to the first and second retimed output signals using the respective first and second delays, with the programmable relative delay being adjustable in increments and covering at least an entire clock signal period; and f) inputting the delayed first and second retimed output signals into an logic gate to form a low-jitter output signal that is selectively positioned finer than the clock signal edge between clock cycle periods, and that has a select signal width as defined by said first and second retimed output signals.