Patent ID: 8200892

Claim:
A memory controller for controlling access to one or more flash memories, in which data erasing is performed in physical blocks, comprising: a logical block management unit which forms plural logical blocks each composed of plural logical sectors to each of which a logical address for a host system is assigned; a program-erase cycles management unit which manages a number of program-erase cycles of each physical block; a first search unit which searches out a first physical block and a second physical block, which first physical block is a free physical block of which the number of program-erase cycles is the smallest among free physical blocks, which second physical block is a free physical block of which the number of program-erase cycles is the largest among free physical blocks; an assignment unit which assigns a logical block to a physical block, which logical block is composed of plural logical sectors to each of which a logical address for a host system is assigned; a second search unit which searches out a third physical block to which a logical block is assigned earliest among physical blocks to each of which a logical block is assigned; a data writing unit which, in response to a request issued by the host system, identifies a logical block including a logical sector corresponding to a logical address pertaining to the request and stores data provided from the host system in a physical block corresponding to the logical block identified; a determination unit which makes a determination whether or not the number of program-erase cycles of the first physical block is larger by a predetermined value or more than the number of program-erase cycles of the third physical block; and a data transfer unit which performs data transfer for transferring data stored in the third physical block to the second physical block; wherein, when the assignment unit assigns a logical block to a physical block, the determination unit makes the determination; and wherein, in a case where the determination is positive, the assignment unit assigns the logical block to the third physical block after completing the data transfer, wherein, in a case where the determination is negative, the assignment unit assigns the logical block to the first physical block.