Patent ID: 7223649

Claim:
A method of fabricating a transistor of a DRAM (dynamic random access memory) semiconductor device, comprising: forming a device isolation film on a semiconductor substrate; ion-implanting a channel adjusting impurity into an active region of a cell region and a circuit region, both defined by the device isolation film, to form respective channel impurity regions; forming a gate insulation layer on the semiconductor substrate by using a silicon oxide layer and a silicon oxide nitride layer, wherein the silicon oxide nitride layer is formed through an atomic-layer-deposition (ALD) system or a decoupled plasma nitridation (DPN) system; forming a first impurity-doped polysilicon layer on the gate insulation layer, and selectively ion-implanting a second impurity of a different type than the first impurity into the polysilicon layer to form a gate electrode comprising an N-type impurity-doped region adjacent to a P-type impurity region; forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and removing the gate upper insulation layer, the conductive metal layer and the gate electrode from above a source/drain region, to form a gate stack in a gate region; and forming a first impurity region in the source/drain region by using the gate upper insulation layer as an ion implantation mask, forming a spacer on a sidewall of the gate electrode, and forming a second impurity region included within the first impurity region by using the spacer and the gate upper insulation layer as an ion implantation mask.