Patent ID: 7498653

Claim:
A semiconductor structure for isolating a first circuit operating at a first voltage level and a second circuit operating at a second voltage level, comprising: an N-type isolation ring surrounding the first and second circuits on a semiconductor substrate; a P-type isolation ring surrounding the N-type isolation ring, the P-type isolation ring having a P-type impurity density higher than that of the semiconductor substrate; an N-type buried layer continuously extending underneath the first and second circuits on the semiconductor substrate, the N-type buried layer interfacing with the N-type isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate; a P-type ion enhanced isolation layer formed on the buried layer, the P-type ion enhanced isolation layer having a P-type impurity density substantially the same as that of the P-type isolation ring; and a set of N-type wells and P-type wells formed on the P-type ion enhanced isolation layer, wherein devices of the first and second circuits are formed on the set of N-type wells and P-type wells.