Patent ID: 6862563

Claim:
An integrated circuit, fabricated using the method comprising: creating a customized description language model of an integrated circuit design by: receiving one or more inputs from a user for at least one customized parameter of the integrated circuit; receiving an identification of a location of one or more library files that provide at least one prototype description and at least one extension logic description for the integrated circuit for which a model is being generated; and generating through an automated process a customized description language model based on at least one customized parameter, the at least one prototype description, and the at least one extension logic description, the automated process including the acts of reading at least one prototype description and modifying the at least one prototype description by substituting values in the at least one prototype description or merging additional descriptions based on the at least one customized parameter; generating a netlist which is descriptive of the circuitry of said integrated circuit; compiling said netlist and said hardware description model to produce a compiled integrated circuit design; fabricating at least one mask or FPGA configuration file representing said compiled integrated circuit design; and fabricating said integrated circuit using said at least one mask or FPGA configuration file; wherein said act of creating is performed at a high level of abstraction.