Patent ID: 7541256

Claim:
A method for fabricating a semiconductor device, comprising the steps of: providing a substrate comprising: an insulator layer, and an epitaxial layer substantially overlying the insulator layer; forming a plurality of alignment keys substantially overlying the epitaxial layer by: printing key patterns on a top portion of the epitaxial layer, etching the underlying epitaxial layer below the key patterns using a trench etch process until the etched away silicon is stopped by the underlying insulator layer, and filling the opened trenches with an electrically insulating material; forming a plurality of bond pads substantially overlying the epitaxial layer; fabricating a dielectric layer substantially overlying the epitaxial layer; providing a handle wafer; forming a plurality of conductive trenches in the handle wafer; forming a plurality of conductive bumps on a first surface of the handle wafer substantially underlying the conductive trenches; and bonding the plurality of conductive bumps to the plurality of bond pads.