Patent ID: 6986005

Claim:
A method of controlling access to a shared memory of a multiprocessor system, the multiprocessor system comprising a first bus and a second bus coupled to the shared memory, the first bus coupled to a first processor, and the second bus coupled to a second processor, the method comprising the steps of: requesting exclusive access to a first memory location of the shared memory by the first processor; granting exclusive access to the first memory location of the shared memory to the first processor; allowing access to a second memory location of the shared memory to the second processor while the first processor has exclusive access to the first memory location; and storing access request information associated with the exclusive access in a first register in a first memory controller and in a second register in a second memory controller, the step of requesting exclusive access comprising the steps of: asserting a lock signal on the first bus; sending a lock request from the first processor to the first memory controller coupled to the first bus, the second bus, and the shared memory; forwarding the lock request from the first memory controller to a switch; and signaling the first processor to retry the lock request, the step of granting exclusive access comprising the steps of: signaling the first memory controller by the switch to retry the lock request; assigning exclusive access to the first memory location by the switch; notifying the first memory controller of the exclusive access assigned in the assigning step; and granting exclusive access to the first memory location by the first memory controller responsive to a retry of the lock request by the first processor, the step of assigning exclusive access to the first memory location by the switch comprising the steps of: determining if the first memory location is currently assigned; saving the access request information in a register in the switch if the first memory location is not currently assigned; sending the access request information to the first memory controller; and sending the access request information to the second memory controller.