Patent ID: 8378420

Claim:
A semiconductor device comprising a vertical trench LDMOS transistor, the vertical trench LDMOS transistor comprising: a substrate of a first conductivity type; a semiconductor layer of the first conductivity type formed on the substrate; a first trench formed in the semiconductor layer, the first trench being filled with a trench dielectric, a trench gate being formed in the first trench and insulated from the sidewall of the first trench by a first gate dielectric layer; a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region, the source region being formed aligned to a first edge of the planar gate; a drain drift region of the first conductivity type formed in the semiconductor layer; and a drain electrode formed on a backside of the substrate, wherein the planar gate forms a lateral channel of the LDMOS transistor in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel of the LDMOS transistor in the body region along the sidewall of the first trench between the source region and the semiconductor layer.