Patent ID: 8091057

Claim:
A processor-implemented method for implementing a design of an integrated circuit to meet a performance objective, comprising: using one or more processors to perform operations including: inputting a specification of the design in a hardware description language; generating a timing analysis for the design, the timing analysis specifying a plurality of critical timing paths that do not meet the performance objective; determining a plurality of respective reasons for the critical timing paths not meeting the performance objective, wherein the respective reason for each critical timing path is one of excessive fanout, bad placement, and long routing; synthesizing the specification of the design into a netlist specifying a plurality of interconnections of a plurality of primitive elements, wherein the synthesizing includes controlling a fanout of one of the primitive elements on each of the critical timing paths in response to the respective reason of the critical timing path not meeting the performance objective being excessive fanout; placing the primitive elements at a plurality of respective positions, wherein the placing includes priority placing of one of the primitive elements on each of the critical timing paths in response to the respective reason for the critical timing path not meeting the performance objective being bad placement; routing the interconnections between the primitive elements at the respective positions, wherein the routing includes priority routing of one of the interconnections on each of the critical timing paths in response to the respective reason for the critical timing path not meeting the performance objective being long routing; and storing a specification of the primitive elements placed by the placing step and the interconnections routed by the routing step.