Patent ID: 8228943

Claim:
A system comprising: a fully integrated Layer 1/Layer 2 monolithic aggregation device, the device being a single integrated circuit on a single chip providing a System-on-Chip implementation for clear channel traffic in a first configuration and deeply Channelized TDM SONET/SDH traffic in a second configuration wherein each of the first configuration and the second configuration having total traffic transferring and processing bandwidth of up to 2.5 Giga bits per second where the system configuration can range from a first configuration carrying a single clear channel at 2.5 Gb/s, in which the entire channel traffic content comprises a single flow of communication not composed of multiple subchannels, or a second configuration carrying above 2000 independent or concatenated, clear or channelized service channels at a total bandwidth of 2.5 Gb/s, wherein each of the first configuration and the second configuration includes SONET/PDH and PDH interfaces for interfacing to a TDM network and a system packet interface (SPI) for interfacing to a data packets network; and a multi-rate SONET/SDH interface configured to operate at 2.5 Gbit/s, 622 Mbit/s and 155 Mbit/s and three multi-rate SONET/SDH interfaces configured to operate at 622 Mbit/s and 155 Mbit/s including integrated Clock Data Recovery (CDR), implemented on a line side of the device; a SONET/SDH interface configured to operate at 622 Mbit/s and 2.5 Gbit/s TDM fabric-to-frame interface (TFI-5) compliant mode having integrated CDR implemented on a system side of the device; and a SONET/SDH interface configured to operate at 622 Mbit/s and 2.5 Gbit/s TFI-5 compliant mode having integrated CDR implemented on a Mate side of the device.