Patent ID: 7005328

Claim:
A method of manufacturing a semiconductor device having a memory region in which non-volatile memory devices are arranged in a matrix of rows and columns to form a memory cell array, the method comprising the steps of: forming a first insulating layer to be formed into a first gate insulating layer over a semiconductor layer; forming a first conductive layer over the first insulating layer; forming a stopper layer over the first conductive layer; patterning the first conductive layer and the stopper layer to form a gate layer; forming a second gate insulating layer at least over the semiconductor layer; forming a side insulating layer on the opposite sides of the gate layer; forming a second conductive layer in the memory region; forming a mask on the second conductive layer over a region in which a common contact section is formed; forming first and second control gates in the shape of sidewalls and a second contact conductive layer by anisotropically etching the second conductive layer; forming a second insulating layer in the memory region; polishing the second insulating layer and the second conductive layer by a chemical mechanical polishing method so that the stopper layer is exposed; removing the stopper layer; forming an impurity layer which forms a source region or a drain region in the semiconductor layer; and forming a third conductive layer in the memory region and then patterning the gate layer and the third conductive layer to form first and third contact conductive layers in the region in which the common contact section is formed and to form a word gate and a word line connected to the word gate.