Patent ID: 8143677

Claim:
A transistor arrangement, comprising: a simulation higher-voltage transistor including a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line, and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the first gate line and the first device isolation layer; and a standard higher-voltage transistor including a standard device isolation layer defining a standard active region, a standard gate line having a standard gate width and crossing over the standard active region, a standard lower-concentration impurity-doped region formed in the standard active region at first and second sides of the standard gate line and a standard higher-concentration impurity-doped region formed in the standard lower-concentration impurity-doped region and not in contact with the standard gate line and the standard device isolation layer, wherein the first higher-concentration impurity-doped region includes at least two sub higher-concentration impurity-doped regions, wherein the first gate line includes at least two sub gate lines having sub gate widths, and wherein the sub gate lines are electrically connected to each other and the first gate width is substantially equal to a multiplication product of a number of the sub gate lines and the sub gate width.