Patent ID: 7683362

Claim:
A semiconductor device, comprising: a silicon substrate having a channel region; a gate electrode formed over the silicon substrate corresponding to the channel region with a gate insulating film in between; a first side wall insulating film formed on side walls of the gate electrode; a second side wall insulating film formed on side surfaces of the first side wall; a source extension region and a drain extension region formed from diffusion regions having a first conductivity, said diffusion regions being formed in the silicon substrate on sides of the gate electrode to sandwich the channel region; a source region and a drain region formed from diffusion regions having the first conductivity, said diffusion regions being formed in the silicon substrate outside the second side wall insulating film and in contact with the source extension region and the drain extension region, respectively; and a semiconductor mixed crystal layer formed in the silicon substrate outside the second side wall insulating film and epitaxially grown over the silicon substrate; wherein the semiconductor mixed crystal layer is formed from a SiGe mixed crystal when the first conductivity is p-type, or from a SiC mixed crystal when the first conductivity is n-type, the semiconductor mixed crystal layer includes an impurity having the first conductivity, the semiconductor mixed crystal layer is grown to a height different from an interface between the silicon substrate and the gate insulating film, and the semiconductor mixed crystal layer has an extended portion between a bottom surface of the second side wall insulating film and a surface of the silicon substrate, said extended portion being in contact with a portion of one of the source extension region and the drain extension region, said extended portion having a ton surface thereof in contact with the bottom surface of the second side wall insulating film, and the source extension region and the drain extension region include the same impurity as an impurity in the extended portion, and a concentration of the impurity in the source extension region and the drain extension region is a maximum at the extended portion and decreases from a surface of the silicon substrate along a depth direction of the silicon substrate.