Patent ID: 7078814

Claim:
A semiconductor device, comprising: a substrate; a first wiring level on a top surface of the substrate, said first wiring level comprising alternating layers of a first dielectric material and a second dielectric material, said layers of the first dielectric material comprising a plurality of layers of the first dielectric material, said layers of the second dielectric material comprising a plurality of layers of the second dielectric material; a first trench and a second trench each extending through the first wiring level, from a top surface of the first wiring level to the top surface of the substrate; a first layered structure comprising a portion of all of the alternating layers, said first layered structure being disposed between the first and second trenches and extending from the top surface of the first wiring level to the top surface of the substrate; and a dielectric liner conformally deposited on a bottom wall of the first trench, a sidewall of the first trench, a sidewall of the second trench, and a bottom wall of the second trench, wherein the first dielectric material within the first layered structure in each layer of first dielectric material is disposed between a first air gap and a second air gap within the first layered structure in each layer of first dielectric material, wherein the first and second air gaps within the first layered structure in each layer of first dielectric material are respectively bounded by the liner on the sidewall of the first and second trenches, wherein the second dielectric material within the first layered structure in each layer of second dielectric material is in direct mechanical contact with the sidewall of the first trench and the sidewall of the second trench.