Patent ID: 6885062

Claim:
A MOS transistor device, comprising: a semiconductor region having a trench structure formed therein extending substantially in a given direction; an avalanche breakdown region formed in a region selected from the group consisting of an end region of said trench structure, a lower region of said trench structure, and a bottom region of said trench structure resulting in a low on resistance for the MOS transistor device; a source region having a first conductivity type and formed in said semiconductor region; a drain region having said first conductivity type and formed in said semiconductor region; a gate electrode device formed substantially between said source region and said drain region in an interior of said trench structure; an insulation region disposed in said trench structure and insulating said gate electrode device; a region having a locally maximum dopant concentration of said first conductivity type disposed between said source region and said drain region in direct proximity to said insulation region and remote from said gate electrode device resulting in the low on resistance of the MOS transistor device; a body region of a second conductivity type disposed substantially between said source region and said drain region in a manner insulated from said gate electrode device; a body reinforcement region of said second conductivity type reinforcing said body region in a direction toward said drain region; and said drain region having a doping spur, and said region of local maximum dopant concentration of said first conductivity type being disposed in an area of a position located in a transition from one of said body region and said body reinforcement region to said doping spur of said drain region.