Patent ID: 7947532

Claim:
A method for producing a power semiconductor device, comprising: providing a leadframe, which has a chip carrier and a plurality of external leads, producing at least one power semiconductor chip, with a top side and a back side, at least one large-area contact area of a counter electrode and a smaller contact area of a control electrode being arranged on the top side, and a large-area contact area of a power electrode being arranged on the back side, said power electrode extending over substantially the entire power semiconductor chip, mounting the power semiconductor chip on the chip carrier, while establishing an electrical connection between the power semiconductor chip and the chip carrier, applying a first patterned layer of plastic of a plastic package with a planar surface, which at least partially embeds the chip carrier with the power semiconductor chip and has through-openings to external leads and to contact areas of the power semiconductor chip, depositing a patterned metal layer to produce connecting elements on the planar upper side of the first layer of plastic and filling through-openings to produce contact vias of the connecting elements for the external leads or the contact areas ( 36 , 46 ), and applying a second layer of plastic of the plastic package, while at least partially covering the connecting elements of the patterned metal layer.