Patent ID: 7459792

Claim:
A structure, comprising: a dielectric layer formed overlying an integrated circuit substrate; and a via pattern located in said dielectric layer and comprising a plurality of first via groups and a plurality of second via groups adjacent to each other; wherein each of said first via groups comprises at least two first line vias extending in a first direction, and each of said at least two first line vias has two opposite ends in said first direction, wherein each of said second via groups comprises at least two second line vias extending in a second direction different from said first direction, and each of said at least two second line vias in said second direction has two opposite ends in said second direction, wherein, said first via groups and said second via groups are placed in an interlocked arrangement, and a domain boundary along said first direction between said first via groups and said second via groups is not straight, and wherein an extension line extending along said first direction and from one of said opposite ends of each of said at least two first line vias of each of said first via groups crosses said at least two second line vias of a corresponding one of said second via groups. and an extension line extending along said second direction and from one of said opposite ends of each of said at least two second line vias of each of said second via groups crosses said at least two first line vias of a corresponding one of said first via groups.