Patent ID: 7622343

Claim:
A method of manufacturing a semiconductor memory device comprising: forming a gate dielectric on a semiconductor substrate; forming a floating gate and a control gate over the gate dielectric wherein the control gate is located over and insulated from the floating gate; oxidizing at least side surfaces of the floating gate and the control gate to form an oxide layer; forming a first impurity region in the semiconductor substrate to a first depth not larger than 0.1 μm using at least the floating gate, the control gate and the oxide layer as a mask wherein; and forming a second impurity region in the semiconductor substrate to a second depth larger than the first death wherein a channel forming region is formed in the semiconductor substrate below the floating gate between the first impurity region and the second impurity region, wherein a channel length of the channel forming region is not larger than 0.3 μm, and wherein said first impurity region is not overlapped with said control gate.