Patent ID: 8466518

Claim:
A semiconductor device manufacturing method comprising: forming a gate interconnect both in a first region and a second region of a semiconductor substrate, forming in the first region a first transistor including a first gate electrode which is a part of the gate interconnect, and forming in the second region a second transistor including a second gate electrode which is another part of the gate interconnect; forming over the semiconductor substrate a first stress film so as to cover the first transistor and the second transistor; forming a first etching stopper film over the first stress film; forming over the first etching stopper film a second etching stopper film whose etching characteristic is different from an etching characteristic of the first etching stopper film; forming a first mask layer covering the first region and exposing the second region; removing the second etching stopper film in the second region with the first mask layer as a mask and the first etching stopper film as the stopper, and isotropically etching the second etching stopper film located below the first mask layer; etching off the first etching stopper film and the first stress film in the second region with the first mask layer as a mask; forming over the semiconductor substrate the second stress film whose etching characteristic is different from an etching characteristic of the second etching stopper film, covering the second transistor, the first stress film, the first etching stopper film and the second etching stopper film; forming over the second stress film a second mask layer covering the second region, an end face of the second mask layer on the side of the first region being located over the second etching stopper film; etching the second stress film with the second mask layer as the mask so that a part of the second stress film overlaps a part of the first stress film and a part of the second etching stopper film; forming over the semiconductor substrate an insulation film, covering the first stress film, the second stress film, the first etching stopper film and the second etching stopper film; forming a contact hole through the insulation film, the second stress film, the first etching stopper film and the first stress film down to the gate interconnect at a border between the first region and the second region; and forming an electrically conductive plug in the contact hole.