Patent ID: 8890116

Claim:
A transistor device, comprising: a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric to form multiple carbon nanotube channels in the stack on the substrate, wherein for a first one of the device layers on the substrate, the first dielectric completely covers the surface of the substrate whereas the second dielectric and the top gate are local to the stack, and wherein for each of the device layers, the carbon nanotube channels are non-local to the stack and extend out laterally from the stack; a single source contact that envelopes portions of the carbon nanotube channels that extend out laterally from the device layers on a first side of the stack; and a single drain contact that envelopes portions of the carbon nanotube channels that extend out laterally from the device layers on a second side of the stack opposite the first side of the stack, whereby the source contact and the drain contact interconnect the carbon nanotube channels of the device layers in parallel, wherein the carbon nanotube channel in each of the device layers comprises an array of carbon nanotubes, wherein a density of the carbon nanotubes in a given one of the device layers determines a current capacity for the given device layer, and wherein the density of the carbon nanotubes in each of the device layers is from about 5 carbon nanotubes per micrometer to about 200 carbon nanotubes per micrometer.