Patent ID: 8605503

Claim:
A nonvolatile semiconductor memory device, comprising: a cell unit including a first and a second selection gate transistor and a memory string provided between said first and second selection gate transistors and including a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into said memory cells, wherein a number of program stages for at least one of memory cells on both ends of said memory string is lower than a number of program stages for other memory cells, said data write circuit executes a first stage program to said at least one memory cell having the number of program stages lower than the number of program stages for said other memory cells after a first stage program to at least one of said other memory cells, said memory string includes, as said plurality of memory cells, first to N-th memory cells (N=an integer of 3 or more) serially connected from said first selection gate transistor to said second selection gate transistor, the number of program stages for the first memory cell which is nearest to said first selection gate transistor is M 1 (M 1 =an integer of 1 or more), and the number of program stages for other memory cells is M 2 (M 2 =an integer larger than M 1 ), said data write circuit executes the m 1 -th stage (m 1 =an integer of 1 to M 1 ) program to the first memory cell after execution of the m 1 -th stage program to the second memory cell, and said data write circuit executes the m 2 -th stage (m 2 =an integer of 1 to M 2 ) program to the n-th (n=an integer of 3 to N) memory cell after execution of the m 2 -th stage program to the (n−1)-th memory cell.