Patent ID: 7447981

Claim:
An apparatus, comprising: a RS (Reed-Solomon) encoder that is operable to encode a first bit stream thereby generating a RS coded bit stream; a first interleaver that is operable to interleave the RS coded bit stream thereby generating an m-bit symbol sequence; an encoder that is operable to encode a second bit stream, using an LDPC (Low Density Parity Check) code or a turbo code, thereby generating an LDPC or turbo coded bit stream; a second interleaver that is operable to interleave the LDPC or turbo coded bit stream thereby generating an n-bit symbol sequence; and a symbol mapper that is operable to: receive the m-bit symbol sequence; receive the n-bit symbol sequence; combine selected m-bit symbols from the m-bit symbol sequence and selected n-bit symbols from the n-bit symbol sequence thereby generating an m+n bit symbol sequence; and symbol map the m+n bit symbol sequence according to a constellation having 2 (m+n) constellation points and a corresponding mapping of the 2 (m+n) constellation points thereby generating a sequence of discrete valued modulation symbols.