Patent ID: 8589666

Claim:
A computer implemented method for eliminating loop overshoot effects in a reconfigurable processor, the method comprising: configuring in a field programmable gate array a dataflow pipelined structure, wherein the dataflow pipelined structure includes a restore buffer in communication with, and interposed between, a First-In First-Out (FIFO) buffer and an iteration loop structure; fetching a data value from the restore buffer to the iteration loop structure, wherein the restore buffer replaces the data value fetched from the restore buffer with another data value from the FIFO buffer and wherein the restore buffer is configured to continually maintain a number of data values, the number of data values continually maintained based on the iteration loop structure of the dataflow pipeline structure; maintaining an accounting of how many data values are fetched from the restore buffer to the iteration loop structure; executing an iterative computation process on the iteration loop structure wherein each iteration failing to terminate the iterative computation process is a valid loop iteration; counting the valid loop iterations of the iterative computation process and preserving a total number of valid loop iterations; identifying termination of the iterative computation process; halting fetching data values from the restore buffer based on identification of termination of the iterative computational process; and restoring data values to the restore buffer that were fetched from the restore buffer between termination of the iterative computational process and halting fetching data values from the restore buffer based on identification of termination of the iterative computational process.