Patent ID: 7430673

Claim:
A computing platform, comprising: an interface to connect a central processing unit (CPU) to the platform; one or more device controllers interfaced to the platform by a host I/O bus; system clocking and interrupt generation circuitry to generate wakeup interrupts at specified wakeup intervals that periodically wake the CPU from a low power non-operational state and put the CPU in an operational state, the CPU then being returned to the non-operational state until the next wakeup interrupt or other interrupt; power management policy logic to define active and idle windows which substantially coincide with the operational and non-operational states, respectively, of the CPU during the interval between wakeup interrupts; and, circuitry incorporated into the device controller and interfaced to the power management policy logic to put the device controller into an idle state during an idle window, wherein an idle state is defined as a state in which the device controller generates no interrupts or bus traffic.