Patent ID: 8812893

Claim:
An apparatus comprising: a plurality of local synchronous divider circuits, each local synchronous divider circuit being configured to receive a serial clock signal and a reset signal and generate a local clock signal; a clock distribution network configured to distribute the serial clock signal to the plurality of local synchronous divider circuits; and a signal distribution network configured to distribute the reset signal to the plurality of local synchronous divider circuits, wherein each local synchronous divider circuit of the plurality of local synchronous divider circuits comprises an inverter configured to invert the serial clock signal to generate an inverted serial clock signal, and synchronizing circuitry configured to generate a synchronized reset signal by synchronizing the reset signal into either a first clock domain of the serial clock signal or a second clock domain of the inverted serial clock signal, wherein the synchronizing circuitry comprises a first latch which is configured to receive the reset signal and to be triggered by an edge of the inverted serial clock signal, a second latch which is configured to receive the reset signal and to be triggered by an edge of the serial clock signal, and logic and latch circuitry configured to synchronize the reset signal to the edge of the inverted serial clock signal if the first latch latches the reset signal before the second latch latches the reset signal and configured to synchronize the reset signal to the edge of the serial clock signal if the second latch latches the reset signal before the first latch latches the reset signal.