Patent ID: 7466787

Claim:
A phase-locked loop (PLL) for high data rate serial digital communications receiving serial data at a rate that exceeds one gigabits per second, the phase-locked loop comprising: a ring oscillator operating as a voltage controlled oscillator (VCO) that produces four differential clocks; a phase detector coupled to receive the four differential clocks and further coupled to receive at least one serial data input stream wherein the phase detector includes: a data buffer for receiving and driving the at least one serial data input stream to produce a buffered serial data stream; a plurality of buffers coupled to receive the buffered serial data stream for buffering and reducing loading of downstream elements of the phase detector for the data buffer wherein the plurality of buffers provide buffering for a plurality of data paths and phase paths; wherein each data path comprises a sample and hold module coupled serially with a dynamic latch that is further coupled serially with a logic module; wherein each phase path comprises a pair of sample and hold modules coupled serially and further coupled serially with a multiplexer; and wherein each multiplexer is coupled to receive a control signal produced by the logic module to cause the multiplexer to not produce an output voltage.