Patent ID: 6865704

Claim:
A method of storing information relating to integrated circuit (IC) scan testing using sequences of state data comprising the steps of: identifying a tester cycle rate of a scan tester that is used to exchange said state data with a device under test (DUT); identifying a device cycle rate of said DUT, said device cycle rate being greater than said tester cycle rate; grouping a plurality of said state data into a plurality of separately accessible memory locations, including multiplexing at least some of said state data into said memory locations such that multiple said state data reside within individual said memory locations, said multiplexing being based on (1) a storage capacity of said individual memory locations, and (2) enabling an effective state data exchange rate that is a multiple (m) of said tester cycle rate, where m is greater than one and is representative of a number of said state data in each said individual memory location.