Patent ID: 7042964

Claim:
A Viterbi decoder including a number of classical Add-Compare-Select units and a number of further Add-Compare-Select unit having a lower complexity butterfly unit ( 300 ) having only two adder means, such that the further Add-Compare-Select unit comprises: first adder means ( 310 ) for receiving a first path metric and a branch metric and for producing at its output the addition thereof; second adder means ( 320 ) for receiving a second path metric and said branch metric and for producing at its output the addition thereof; first comparator means ( 330 ) coupled to receive the output of the second adder means and coupled to receive the first path metric for comparing therebetween; second comparator means ( 340 ) coupled to receive the output of the first adder means and coupled to receive the second path metric for comparing therebetween; first selection means ( 350 ) for selecting between the second adder means output and the first path metric to produce a first survivor path metric in dependence on the first comparator means comparison; and second selection means ( 360 ) for selecting between the first adder means output and the second path metric signal to produce a second survivor path metric in dependence on the second comparator means comparison, for processing metric transitions via the lower complexity butteffly unit only where a second branch metric is zero.