Patent ID: 7109571

Claim:
A method of processing a wafer, the wafer having: a semiconductor material that has a top surface and a bottom surface; a doped region that contacts the top surface of the semiconductor material and is spaced apart from the bottom surface of the semiconductor material, the semiconductor material and doped region having opposite conductivity types; and a plurality of conductive structures that each extend from the top surface of the semiconductor material down through the semiconductor material, a bottom of each conductive structure lying below the doped region and above the bottom surface of the semiconductor material, the method comprising: removing the bottom surface of the semiconductor material to expose the bottom of each conductive structure; and segmenting the wafer to form two or more first dice after the bottom surface of the semiconductor material has been removed, each first die having a top side, a bottom side, and a number of side wall surfaces that each extends from the bottom side to the top side, no conductive structure contacting a side wall surface.