Patent ID: 8164555

Claim:
A display device comprising: a driver circuit comprising an output circuit for outputting pulses, the output circuit comprising a first transistor; a monitor circuit comprising a second transistor, a first switch, and a capacitor and configured to obtain a threshold voltage of the second transistor; a power supply control circuit electrically connected to a gate of the first transistor and to a gate of the second transistor wherein the power supply control circuit is configured to apply one of a forward bias voltage and a reverse bias voltage to both of the gate of the first transistor and the gate of the second transistor; a threshold control circuit operationally connected to the power supply control circuit and the monitor circuit wherein the threshold control circuit is configured to select the one of the forward bias voltage and the reverse bias voltage applied by the power supply control circuit and decide a time during which the reverse bias voltage is applied to both of the gate of the first transistor and the gate of the second transistor; and a second switch, wherein the gate of the second transistor, a first terminal of the first switch, and a first terminal of the second switch are electrically connected to each other, wherein a first terminal of the second transistor and a second terminal of the second switch are electrically connected to each other, wherein a second terminal of the first switch and a first terminal of the capacitor are electrically connected, wherein the first switch is configured to be turned off in a first period, to be turned off in a second period, to be turned on in a third period, and to be turned off in a fourth period, wherein the second switch is configured to be turned off in the first period, to be turned on in the second period, to be turned on in the third period, and to be turned off in the fourth period, wherein the forward bias voltage is applied to the gate of the first transistor and the gate of the second transistor in the first period, wherein the reverse bias voltage is applied to the gate of the first transistor and the gate of the second transistor in the fourth period, and wherein a time of the fourth period is determined by a voltage held in the capacitor in the third period.