Patent ID: 8890291

Claim:
A method of manufacturing a silicon epitaxial wafer which is provided to a semiconductor device manufacturing process having a thermal treatment process of which the highest temperature ranges from 1050° C. to the melting point of silicon and of which the temperature rising and falling rate ranges from 150° C./sec to 10000° C./sec, the method comprising: an epitaxial process to cause an epitaxial layer to grow on the surface of a substrate, which is doped with boron so as to have resistivity of 0.02 Ωcm to 0.001 Ωcm and of which the initial oxygen concentration Oi is in the range of 11.0×10 17 to 9.5×10 17 atoms/cm 3 (ASTM F 121, 1970-1979 published by American Society for Testing and Materials International), wherein the thermal treatment process is applied to only an outermost surface layer of the silicon epitaxial wafer, the oxygen precipitates density is equal to or less than 5×10 4 pcs/cm 2 in the silicon epitaxial wafer, an oxygen precipitation nuclei dissolution process is not performed before the epitaxial process, and wherein the wafer includes a front surface and a back surface, both having a flat main surface, a front sloped chamfered portion having an angle θ 1 , which is in the range of from 10° to 50°, a back sloped chamfered portion having an angle θ 2 , which is in the range of from 10° to 30°, and front and back curved portions, which connect the front and back chamfered portions to a peripheral edge of the wafer.