Patent ID: 8525092

Claim:
A data processing method that performs a differential processing between a first data signal and a second data signal based on an output of a delay circuit, the delay circuit including a plurality of inverting elements that are connected to each other, the data processing method comprising: a first data processing on the first data signal, the first data processing comprising: counting, by an upper counting unit, one of a plurality of clock signals output from the delay circuit with a first mode, the first mode being either one of a down-count mode and an up-count mode; counting, by a lower counting unit, clock signals based on a predetermined number of the plurality of clock signals output from the delay circuit with the first mode, to output a first clock signal to the upper counting unit every time a counter value becomes a first predetermined value; and counting, by the upper counting unit, the first clock signal from the lower counting unit with the first mode; a second data processing on the second data signal, the second data processing comprising: counting, by the upper counting unit, one of the plurality of clock signals output from the delay circuit with a second mode, the second mode being the other one of the either one of the down-count mode and the up-count mode, while the value counted with the first mode is considered as a first initial value; counting, by the lower counting unit, clock signals based on the predetermined number of the plurality of clock signals output from the delay circuit with the second mode, to output a second clock signal to the upper counting unit every time the counter value becomes a second predetermined value while the value counted with the first mode is considered as a second initial value; and counting, by the upper counting unit, the second clock signal from the lower counting unit with the second mode; and outputting the counter values counted by the upper counting unit and the lower counting unit with the second mode as difference data between the first data signal and the second data signal.