Patent ID: 8782377

Claim:
A system on a chip comprising: a memory; a memory controller coupled with the memory; a graphics controller; and a plurality of processors, one of the processors comprising: a plurality of registers; a cache; an instruction decoder to decode a shift right merge instruction indicating a first 32-bit source operand and a second 32-bit source operand, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source operand including a second four 8-bit byte data elements, wherein the 8-bit byte data elements are integers; and an execution unit that is part of a digital signal processor coupled with the instruction decoder and the plurality, of registers, the execution unit in response to the shift right merge instruction to: shift the second 32-bit source operand right by one byte, wherein the one byte amount to shift the second 32-bit source operand right by is fixed for a type of the shift right merge instruction; merge a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position of the shifted second 32-bit source operand to generate a result; and store the result in a 32-bit destination indicated by the shift right merge instruction, wherein the system on the chip implements a combination of instruction sets including a very long instruction word (VLIW) instruction set that includes the shift right merge instruction.