Patent ID: 8701058

Claim:
A method of analyzing at least one target netlist or a portion thereof from at least one first integrated circuit (IC), using a plurality of reference netlists or portions thereof front at least one reference IC, wherein higher than gate level functionality of said target netlist or a portion thereof is unknown and higher than gate level functionality of said reference netlist or portions thereof known, the method, implemented using a computer, comprising the steps of: a) characterizing said target netlist or a portion thereof to obtain a plurality of characterizations for said target netlist or said portion thereof; b) characterizing said plurality of reference netlists or portions thereof to obtain a plurality of characterizations for said plurality of reference netlists or portions thereof; c) matching the plurality of characterizations obtained in step a) with the plurality of characterizations obtained in step b), and d) extracting the matching information obtained from step c) and annotating the said target netlist or a portion thereof using the extracted matching information by associating the previously unknown higher than gate level functionality of said target netlist or a portion thereof with the higher than gate level functionality of the reference netlist or portion thereof having the matched characteristics.