Patent ID: 8902093

Claim:
An analog to digital converting system with a charge redistribution sampler, comprising: an analog to digital converter circuit including a plurality of analog to digital converters each incorporating a switched capacitor digital to analog converter; a conductive interconnect wiring pattern connecting inputs of said plurality of analog to digital converters in parallel, said conductive interconnect wiring pattern having a distributed parasitic capacitance; and a sample and hold circuit coupled to an input terminal for periodically sampling an analog voltage applied to said input terminal, said sample and hold circuit including a hold capacitor passively connected to said conductive interconnect wiring pattern and a sampling switch coupled between said input terminal and said hold capacitor, said sampling switch coupling an analog voltage at said input terminal to a hold capacitance responsive to a sampling clock signal and thereby charging said hold capacitance to a sampled voltage value corresponding to the analog voltage, said hold capacitance being formed by a combination of said hold capacitor of said sample and hold circuit and said distributed parasitic capacitance, said sampled voltage value held on said hold capacitance being secondarily sampled by said analog to digital converter circuit for conversion to a digital representation thereof.