Patent ID: 7151023

Claim:
A method of forming a semiconductor structure comprising: providing a structure comprising a gate stack in a first type MOSFET region and a gate stack in a second type MOSFET region, where said gate stacks each comprise a semiconductor layer, and said structure further comprising a planarized dielectric layer formed over said gate stacks in said first type MOSFET and said second type MOSFET regions; removing portions of said planarized dielectric layer to expose said semiconductor layers of said gate stacks; forming a metal-containing layer in contact with said exposed semiconductor layers of said gate stacks, wherein said metal-containing layer is thick enough to fully convert said semiconductor layer of said gate stack to a semiconductor metal alloy in said first type of said MOSFET region but not thick enough to fully convert said semiconductor layer to a semiconductor metal alloy in said second type of said MOSFET region; and forming a fully converted semiconductor metal alloy gate conductor from said metal-containing layer in contact with said semiconductor layer of said gate stack in said first type of said MOSFET region while forming a partially converted semiconductor metal alloy gate conductor from said metal-containing layer in contact with said semiconductor layer of said gate stack in said second type of said MOSFET region.