Patent ID: 7017810

Claim:
A system, comprising: a main unit; an IC card; and an interface connectable between said main unit and said IC card, including: a data transmission path, and a clock signal transmission path; said IC card being operable to receive a clock signal transmitted from the main unit over said clock signal transmission path and to return the clock signal to said main unit over said clock signal transmission path; said IC card including: a data transmission unit having a clock input operable to receive the clock signal that is received by said IC card and having a data output operable to transmit, over said data transmission path for delivery to said main unit, a data signal having a first timing delay with respect to a timing of the clock signal received at said clock input of said data transmission unit; said main unit including: a data receiving unit having a clock input operable to receive the returned clock signal, the clock signal received at said clock input of said data receiving unit having a second timing delay with respect to a timing of the clock signal being returned at said IC card, and having a data input operable to receive the data signal transmitted by said data transmission unit, the data signal when being received at said data input of said data receiving unit having a third timing delay with respect to the timing of the data signal when being transmitted at said data output of said data transmission unit; said main unit, said IC card, and said interface being configured such that the second delay is substantially equal to the third delay so that only the first delay affects a timing tolerance between the timing of the clock signal received at said clock input of said data receiving unit and the timing of the data signal received at said data input of said data receiving unit.