Patent ID: 7433259

Claim:
A semiconductor memory device comprising: a basic unit block column having a plurality of basic unit blocks each having a plurality of memory cells, a first bit line pair connected to the plurality of memory cells, a bit line precharge circuit connected to the first bit line pair, and a pair of transfer gate switch circuits connected to the first bit line pair, each of the plurality of basic unit blocks further includes a first differential sense amplifier connected between the first bit line pair and the pair of transfer gate switch circuits to sense and amplify a potential difference between the first bit line pair; a second bit line pair connected to the plurality of basic unit blocks via the pair of transfer gate switch circuits in the plurality of basic unit blocks, the second bit line pair being formed of a wiring layer located above the first bit line pair and constituting a layered bit line structure together with the first bit line pair, the second bit line pair being laid out to extend in the same direction as that of the first bit line pair, the second bit line pair being twisted once or more in the extending direction of the second bit line pair; and a second differential sense amplifier coupled to the second bit line pair to sense and amplify a potential difference between the second bit line pair.