Patent ID: 7525832

Claim:
A memory device, comprising: a first electrode layer including a plurality of first electrode lines extending parallel to each other; a state-variable layer lying on the first electrode layer, the state-variable layer including a plurality of state-variable portions, the plurality of state-variable portions being a plurality of state-variable portions formed of a state-variable material which exhibits a diode characteristic and a variable-resistance characteristic; and a second electrode layer lying on the state-variable layer, the second electrode layer including a plurality of second electrode lines extending parallel to each other, wherein the plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween, each of the plurality of state-variable portions is provided at an intersection of any one of the plurality of first electrode lines and any one of the plurality of second electrode lines when seen in the layer-stacking direction between the first electrode line and the second electrode line, each state-variable portion exhibiting a diode characteristic such that a forward direction is the direction extending from one of the first electrode line and the second electrode line to the other while a reverse direction is opposite to the forward direction, each state-variable portion exhibiting a variable-resistance characteristic such that a resistance value of the state-variable portion in the forward direction increases/decreases according to a predetermined pulse voltage applied between the first electrode line and the second electrode line.