Patent ID: 8495423

Claim:
A Flash-based memory system having data backup and recovery capability, comprising: a printed circuit board (PCB); a plurality of Flash memory devices mounted to the PCB, each Flash memory device having a physical memory space that is divided into blocks, each block being further divided into pages, each page representing an individually addressable memory location on which memory operations are performed, multiple memory locations being erased at the same time in one-block groupings; a Flash controller mounted to the PCB and communicating independently with each Flash memory device to perform the memory operations, the Flash controller configured to access a logical-to-physical translation table that associates a logical address of a memory operation with a physical address of a memory location; a power circuit mounted to the PCB and providing power to at least the Flash memory devices; and a central processing unit (CPU) mounted to the PCB and coupled to the power circuit and the Flash controller, the CPU connected to and in communication with a non-volatile backup memory separate from the Flash memory devices and configured to perform a controlled powering down procedure upon detecting a power failure, the controlled powering down procedure comprising: i) determining whether the Flash-based memory system was in normal operation when the power failure is detected; ii) removing power from the Flash memory devices without backing up data upon determining that the Flash-based memory system was not in normal operation when the power failure is detected; and iii) removing power from the Flash memory devices after backing up selected data upon determining that the Flash-based memory system was in normal operation when the power failure is detected, wherein the backing up of selected data comprises: a) storing the logical-to-physical translation table in pre-designated memory locations in the Flash memory devices; and b) storing system data in the non-volatile backup memory connected to the CPU, the system data including data reflecting bad blocks within the Flash memory devices, a pointer pointing to the pre-designated memory locations in the Flash memory devices where the logical-to-physical translation table is stored, and error correction information associated with the system data.