Patent ID: 7843522

Claim:
A thin film transistor array panel comprising: a substrate; a data line and a gate electrode formed above the substrate; an insulating layer formed above the data line and the gate electrode; a semiconductor layer formed above the insulating layer; a drain electrode and a source electrode formed above the semiconductor layer; a passivation layer formed above the drain electrode and the source electrode, wherein the passivation layer includes a first contact hole to expose a portion of the data line, a second contact hole to expose a portion of the source electrode, a third contact hole to expose a portion of the drain electrode, and a fourth contact hole to expose a portion of the gate electrode; a first connector formed above the passivation layer and connected to the data line and the source electrode through the first and the second contact holes; a gate line formed above the passivation layer and connected to the gate electrode through the fourth contact hole; and a pixel electrode connected to the drain electrode through the third contact hole.