Patent ID: 7906988

Claim:
A tolerant buffer circuit, comprising: a first P-channel MOS transistor and a second P-channel MOS transistor that are connected in series and that share a source between a power supply terminal and an output terminal; a first N-channel MOS transistor that is connected between the output terminal and a ground terminal; and a control circuit that outputs a first control signal, a second control signal and a third control signal to the first P-channel MOS transistor, the second P-channel MOS transistor and the first N-channel MOS transistor, respectively, and controls an on/off state of the first P-channel MOS transistor, the second P-channel MOS transistor, and the first N-channel MOS transistor, wherein: back gates of the first P-channel MOS transistor and the second P-channel MOS transistor are connected to the source, so that parasitic diodes produced in the first P-channel MOS transistor and the second P-channel MOS transistor are connected in a reverse direction with respect to a low voltage power supply; and the control circuit: (a) implements a push-pull operation in which the low voltage power supply and ground potential are output to the output terminal by: (i) driving the first control signal high and driving the second and third control signals low and high, or high and low, respectively, or (ii) driving the first, second and third control signals low, low, and high, or high, high and low, respectively; and (b) implements an open-drain operation for the output terminal by driving the first and second control signals low and driving the third control signal high or low.