Patent ID: 6966041

Claim:
A chip fabrication procedure with performance pre-testing, comprising steps of: providing a design of a chip; executing a set of design testing commands using a simulation environment to determine if said design of said chip is correct; applying a performance testing process to said design of said chip to determine in software if performance of said chip meets operational standards, executing a plurality of performance testing commands for each of a plurality of functions, said performance testing process being operable to monitor timing information corresponding to the execution of said performance testing commands, wherein said performance testing process comprises the steps of: a. recording a time at which a first command of said plurality of performance testing commands for a respective one of said plurality of functions is transmitted, b. recording a time at which a last command of said plurality of performance testing commands for said respective function is completed and determining whether a difference between said recorded times meet a required standard; c. repeating steps a. and b. for each of said plurality of functions; d. calculating a time for completing all of said plurality of performance testing commands for all of said functions and recording said calculated time; and e. comparing said recorded calculated time with a recorded calculated time of another design of a chip similarly tested to evaluate performance; and, proceeding with production of chips.