Patent ID: 7283392

Claim:
A NAND flash memory device comprising: a device isolation layer formed in a semiconductor substrate to define an active region; a cell gate group including a plurality of cell gate lines arranged in parallel with each other on the active region; a first selection gate line disposed on the active region of one side of the cell gate group, and including a first selection lower gate and a first selection upper gate sequentially stacked and connected with each other, and a first intergate pattern interposed between the first selection lower gate and the first selection upper gate; a second selection gate line disposed on the active region of one side of the first selection gate line, the first selection gate line disposed between the cell gate group and the second selection gate line; and first impurity diffusion layers respectively formed at the active region of both sides of each of the cell gate lines, a second impurity diffusion layer formed at the active region between the first selection gate line and the second selection gate line, and a third impurity diffusion layer disposed at the active region of one side of the second selection gate line wherein the second selection gate line is disposed between the second and third impurity diffusion layer, and the third impurity diffusion layer is one of a common source region and a common drain region.