Patent ID: 8526260

Claim:
A dynamic random access memory (DRAM) having storage cells for storing data, the data being refreshable in a sleep mode, the DRAM comprising: a voltage producer configured to provide an output voltage to be used for operation of the DRAM, the voltage producer including a pump circuit configured to provide the output voltage in response to a plurality of enable signals, the pump circuit including a plurality of pump circuit segments wherein each of the pump circuit segments is selectively activatable in response to a respective one of the plurality of enable signals; a voltage level detector configured to determine whether the output voltage reaches a predetermined level; and a controller configured to provide the plurality of enable signals in response to a refresh time in the sleep mode; wherein the controller is configured to receive a plurality of refresh time signals representing the refresh time; and provide the plurality of enable signals for selectively activating one or more of the plurality of pump circuit segments to be activated according to the refresh time represented by the plurality of refresh time signals.