Patent ID: 8222702

Claim:
A semiconductor device comprising: a semiconductor substrate having a first doped region of n-type conductivity and a second doped region of p-type conductivity with a third doped region located therebetween, wherein said third doped region has either n-type or p-type conductivity with a dopant concentration lower than that of the first or second region; a gate dielectric layer located over the semiconductor substrate; a first gate conductor of n-type conductivity, which is located on a first portion of the gate dielectric layer adjacent to the first doped region in the semiconductor substrate; and a second gate conductor of p-type conductivity, which is located on a second portion of the gate dielectric layer adjacent to the second doped region in the semiconductor substrate and which is spaced apart and isolated from the first gate conductor by a dielectric isolation structure therebetween, said dielectric isolation structure having a bottommost surface that is in direct contact with an uppermost surface of a third portion of said gate dielectric layer and an uppermost surface that has a non-planar thickness spanning the entirety of the third portion of said gate dielectric layer, wherein the first, second, and third doped regions and the first and second gate conductors are arranged and constructed to form an accumulation region and an underlying depletion region between the third doped region and the second or the first doped region and wherein said first and second gate conductors are located over a contiguous area in which a portion of said third region is in direct contact with said gate dielectric layer.