Patent ID: 8372704

Claim:
A manufacturing method for a semiconductor integrated device, said method comprising: forming a second impurity layer of a second conductivity type that is higher in an impurity concentration than a second well of the second conductivity type on a first impurity layer of a first conductivity type that is higher in an impurity concentration than an impurity concentration of a first well of the first conductivity type; forming an impurity region in the second impurity layer, the impurity region having the first conductivity type that is higher in an impurity concentration than the impurity concentration of the first well; forming the first well of the first conductivity type on the second impurity layer of the second conductivity type formed on the first impurity layer of the first conductivity type, the first well being supplied with a potential from the first impurity layer of the first conductivity type via the impurity region; forming the second well of the second conductivity type on the second impurity layer of the second conductivity type formed on the first impurity layer of the first conductivity type, the second well being supplied with a potential from the second impurity layer of the second conductivity type; and forming a supply voltage region electrically connecting the second impurity layer and a supply voltage terminal supplying a supply voltage to the second impurity layer, said supply voltage region comprising an opening in the first well that extends from an upper surface of the second impurity layer to an upper surface of the first well.