Patent ID: 7893490

Claim:
A semiconductor structure comprising: a substrate; a first high-voltage n-well (HVNW) region buried in the substrate; a p-type buried layer (PBL) horizontally adjoining the first HVNW region; a second HVNW region on the first HVNW region; a high-voltage p-well (HVPW) region over the PBL; a p-type region between the PBL and the HVPW region, wherein the p-type region has an impurity concentration lower than each of the impurity concentrations of the PBL and the HVPW region; an insulating region at a top surface of the second HVNW region; a gate dielectric extending from over the HVPW region to over the second HVNW region, wherein the gate dielectric has a portion over the insulating region; and a gate electrode on the gate dielectric.