Patent ID: 8867260

Claim:
A reading circuit for a resistive memory cell, the reading circuit comprising: a current source; a precharge switch coupled to the current source; a comparator circuit comprising a first input node, a second input node, an output node and an enable node; wherein the precharge switch is configured to couple the current source to the first input node of the comparator circuit such that the current provided by the current source is provided to the first input node to apply a precharge voltage at the first input node during a first reading time period, and to decouple the current source from the first input node during a second reading time period; wherein the comparator circuit is configured to operate during a third reading time period upon application of an enable signal at the enable node of the comparator circuit; at least one memory cell access switch to enable a current flow through a memory cell or to disable a current flow through a memory cell; wherein the at least one memory cell access switch is configured to allow a current flow at least partially during the second and the third reading time periods through the memory cell; wherein the comparator circuit is further configured to compare a voltage applied to the first input node with a reference voltage applied to the second input node and to determine a programming state of the memory cell based on the voltage present at the first input node during the third reading time period.