Patent ID: 8760927

Claim:
A solid-state memory in an integrated circuit formed at a semiconducting surface of a body, the memory comprising: a plurality of memory cells arranged in rows and columns within a generally rectangular bit array area of the semiconducting surface, each memory cell including two or more transistors, each having a channel region disposed in a first well region of the semiconducting surface doped to a first conductivity type; one or more bias conductors for applying a bias voltage routed within the bit array area, each physically contacting a doped region in one or more of the memory cells; one or more signal conductors routed within the bit array area, each physically contacting a doped region in one or more of the memory cells; and peripheral circuitry disposed in a peripheral area adjacent to the bit array area and coupled to the one or more signal conductors; wherein, within the bit array area, doped regions only of a second conductivity type, opposite the first conductivity type, are disposed within the first well region and are physically contacted by one of the bias conductors.