Patent ID: 8134186

Claim:
An integrated circuit, comprising: a substrate region; and a gate electrode level region formed above the substrate region, the gate electrode level region having a size of up to about 965 nanometers as measured in any direction parallel to the substrate region, the gate electrode level region including at least three linear-shaped conductive structures formed to extend lengthwise in a first direction, each of the at least three linear-shaped conductive structures having a lengthwise centerline, the at least three linear-shaped conductive structures positioned according to an equal pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the at least three linear-shaped conductive structures is an integer multiple of the equal pitch, wherein the at least three linear-shaped conductive structures include a first linear-shaped conductive structure including a gate portion that foil is a gate electrode of a first transistor of a first transistor type, the first linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the first linear-shaped conductive structure, wherein a length of the non-gate portion of the first linear-shaped conductive structure as measured in the first direction is greater than a length of the gate portion of the first linear-shaped conductive structure as measured in the first direction, wherein the gate portion of the first linear-shaped conductive structure that forms the gate electrode of the first transistor of the first transistor type is the only gate portion of the first linear-shaped conductive structure.