Patent ID: 8090958

Claim:
A semiconductor memory, comprising: a memory core having a predetermined storage region storing a check pattern, the check pattern including first key information and second key information; a security processing circuit including at least a security release circuit and a security protection circuit, said security release circuit being configured to release an address received at the semiconductor memory from scrambling subjected to first security protection from said first security protection based on the first key information obtained from the memory core when in a first testing mode, said security protection circuit being configured to provide second security protection to scramble data sent from said memory core based on the second key information obtained from the memory core when in the first testing mode; an address conversion circuit configured to convert the address released from the first security protection by the security release circuit to an address designating the predetermined storage region; a first path configured to allow an unprotected address received at said semiconductor memory to bypass said security processing circuit; a second path configured to allow the unprotected address received at the semiconductor memory to bypass the address conversion circuit; and a third path configured to allow the data sent from the memory core to bypass the security processing circuit.