Patent ID: 8160198

Claim:
A gate signal generation method for generating plural gate signals furnished to plural gate lines, the gate signal generation method comprising: providing a shift register circuit comprising a plurality of shift register stages, an Mth shift register stage of the shift register stages comprising: an input unit electrically connected to an (M−1)th shift register stage of the shift register stages; a first pull-up unit electrically connected to the input unit and an Nth gate line of the gate lines; a second pull-up unit electrically connected to the input unit and an (N+1)th gate line of the gate lines; a control unit electrically connected to the input unit; a pull-down unit electrically connected the control unit, the input unit, the Nth gate line and the (N+1)th gate line; and an auxiliary pull-down unit electrically connected to an (M+1)th shift register stage of the shift register stages, the input unit, the Nth gate line and the (N+1)th gate line; the input unit inputting an (N−1)th gate signal generated by the (M−1)th shift register stage to become a driving control voltage during a first interval; the first pull-up unit pulling up an Nth gate signal furnished to the Nth gate line according to the driving control voltage and a first clock signal during a second interval; the second pull-up unit pulling up an (N+1)th gate signal furnished to the (N+1)th gate line according to the driving control voltage and a second clock signal during a third interval; the auxiliary pull-down unit pulling down the driving control voltage according to a gate signal generated by the (M+1)th shift register stage during a fourth interval, wherein the fourth interval overlaps none of the first, second and third intervals; the control unit generating a pull-down control signal furnished to the pull-down unit according to the driving control voltage and a control signal during the fourth interval; and the pull-down unit pulling down the Nth gate signal and the (N+1)th gate signal according to the pull-down control signal during the fourth interval; wherein the gate signal generated by the (M+1)th shift register stage is an (N+2)th gate signal generated by the (M+1)th shift register stage, and wherein M and N are positive integers.