Patent ID: 8621157

Claim:
An apparatus, comprising: a processor configured to access a plurality of system memories with different respective performance characteristics, wherein each of the plurality of system memories stores a respective non-overlapping subset of system memory data; and caching logic configured to determine a portion of the system memory data to prefetch into a data cache based on one or more of the respective performance characteristics of the system memory that stores the portion of the system memory data; wherein the caching logic includes an arbiter configured to: receive prefetch requests targeting respective ones of the system memories; determine a next one of the requests to issue to a memory controller for execution, wherein the determining is dependent on the one or more respective performance characteristics of the system memory targeted by the determined next one of the requests; and permit more in-flight prefetch requests targeting a high-latency one of the system memories than in-flight prefetch requests targeting a low-latency one of the system memories.