Patent ID: 7656738

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array comprising memory cells disposed in a matrix; a plurality of word-lines arranged in the memory cell array, the word-lines being for selecting a memory cell in a row direction; a read bit-line pair arranged in a direction perpendicular to the word-line, the read bit-line pair being for reading data from the memory cell; a write bit-line arranged in the direction perpendicular to the word-line, the write bit-line being for writing data to the memory cell; and a sense amplifier amplifying a potential difference generated across the read bit-line pair, the read bit-line pair comprising a true and a complementary read bit-line, one of the true and complementary read bit-lines being connected to a memory cell connected to an even-numbered word-line, and the other one being connected to a memory cell connected to an odd-numbered word-line.