Patent ID: 7100020

Claim:
An integrated circuit comprising: a plurality of data stream inputs and/or outputs that receive and/or transmit streams of data; a plurality of data stream processors that process the streams of data, each data stream processor is programmable and being coupled to a data stream input and/or data stream output and each data stream processor processing a stream of data from the data stream input and/or output, the data stream processor is coupled to as the data stream is received from the data stream input and/or transmitted to the data stream output, each data stream processor including: a writeable instruction memory containing instructions, and a control data processor that controls the data stream processor by sequentially executing instructions from the writeable instruction memory; and the integrated circuit further comprising: an aggregator to perform receive aggregation to certain of the data stream processors that receive a data stream and to perform transmit aggregation to certain of the data stream processors that transmit a data stream, so that the aggregated data stream processors cooperate in processing a stream of data; a context processor that responds to information received from a given data stream processor that is processing a data stream to produce information about the given data stream's context and provide the context information to the given data stream processor; the given data stream processor using the context information to process the data stream; and wherein the integrated circuit being constructed on one chip.