Patent ID: 8607202

Claim:
A processor implemented method for implementing profiling in a multi-core processor, comprising the steps of: (A) configuring a first core of said multi-core processor to (a) communicate through a first input/output port and (b) initiate a testing application; (B) configuring a second core of said multi-core processor to (a) communicate through a second input/output port and (b) respond to said testing application; (C) configuring a bus matrix connected to said first input/output port and said second input/output port to transfer data between said first core and said second core; and (D) generating real-time statistics related to the execution of instructions by said second core, wherein (i) said first core is capable of executing tasks faster than an average change of instruction flow rates of said second core, (ii) said first core further comprises a direct memory access controller configured to read said data from said bus matrix, and (iii) second core further comprises (a) a trace buffer configured to store a stream of recorded events, (b) an on-chip emulator and (c) one or more read buffers configured to perform cycle stealing reads.