Patent ID: 8074047

Claim:
A memory controller apparatus for controlling computer memory input and output operations in a computing system having a physical memory and a cache memory, said apparatus comprising: a means for calculating a hash value of a memory block content when a block of memory is being accessed for content storage at a location in said physical memory; a hash table provided in said cache memory, for storing calculated hash values corresponding to said real memory block contents stored in said physical memory; a translation table for mapping all references for real memory blocks whose hashing values have been identified as identical, to a single shared reference corresponding to a shared block of physical memory in which only one copy of content is stored for identical content; a means operatively associated with said translation table for comparing a calculated hash value against said calculated hash table values corresponding to stored memory blocks when a block of said memory is accessed for content storage, wherein, in response to determining a matching hash value, said translation table providing said single reference of said identical content corresponding to said shared physical memory location for accessing said identical content; a means for maintaining a reference count for each physical block indicating the number of references in the translation table, said reference count of a physical memory block being incremented by one whenever a new reference to the block is added and, the reference count of a physical memory block being decremented by one when a reference to a physical block is removed; and, a means for maintaining a list of free memory blocks in said physical memory, wherein when a reference count of a physical memory block is zero, said controller adding said physical memory block to said list of free physical memory blocks.