Patent ID: 8513725

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate; first and second fin type stacked structures each comprising first to i-th memory strings (i is a natural number equal to or more than 2) that are stacked in a first direction perpendicular to a surface of the semiconductor substrate, the first and second fin type stacked structures which extend in a second direction parallel to the surface of the semiconductor substrate and which are adjacent in a third direction perpendicular to the first and second directions; a first portion used as one of a source region and a drain region, the first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure; and a second portion used as one of the source region and the drain region, the second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure, wherein the other end in the second direction of the first fin type stacked structure is located at the second portion side, and the other end in the second direction of the second fin type stacked structure is located at the first portion side, the first to i-th memory strings in the first fin type stacked structure uses the first portion as the drain region, and uses the ends of the first to i-th memory strings at the second portion side as the source region, the first to i-th memory strings in the second fin type stacked structure uses the second portion as the drain region, and uses the ends of the first to i-th memory strings at the first portion side as the source region, each of the first to i-th memory strings comprises memory cells connected in series in the second direction, and an assist gate transistor connected between the drain region and the memory cells, each of the memory cells comprises a semiconductor layer, and a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode that are disposed on side surfaces in the third direction of the semiconductor layer, the assist gate transistor comprises the semiconductor layer, and a gate insulating layer and an assist gate electrode that are disposed on the side surfaces in the third direction of the semiconductor layer, and the control gate electrode is shared by the first and second fin type stacked structures, and the assist gate electrode in the first fin type stacked structure is electrically isolated from the assist gate electrode in the second fin type stacked structure.