Patent ID: 7505533

Claim:
A clock data recovery circuit with feedback type phase decision, providing an output signal of B bits, comprising: a sampler, oversampling k*B bits per cycle from a serial input data stream according to a sampling clock signal; a phase region decision circuit, internally generating a plurality of binary up-down decision signals according to the oversampled serial input data stream and a current phase status signal; a phase status register, generating the current phase status signal according to the binary up-down decision signals; and a multiplexer, selecting data of B bits from the oversampled serial input data stream according to the current phase status signal; wherein the multiplexer selects the data sampled in at a phase Φn 5 , wherein n 5 is a modulus of nx 5 /k, and nx 5 is a sum of k and m, and the plurality of binary up-down decision signals comprise: a first up signal, having a value of 1 if a phase region of the oversampled serial input data stream is Rn 1 , wherein n 1 is a modulus of nx 1 /k, nx 1 is one of n+1,n+2, . . . and n+ny 1 , and ny 1 is one of 1, 2, . . . , and m; a first down signal, having a value of 1 if a phase region of the oversampled serial input data stream is Rn 2 , wherein n 2 is a modulus of nx 2 /k, nx 2 is one of n,n−1, . . . and n−ny 2 , and ny 2 is one of 0, 1, . . . , and m; a second up signal, having a value of 1 if a phase region of the oversampled serial input data stream is Rn 3 , wherein n 3 is a modulus of nx 3 /k, nx 3 is one of n,n+1, . . . and n+ny 3 , and ny 3 is one of 0, 1, . . . , and m; and a second down signal, having a value of 1 if a phase region of the oversampled serial input data stream is Rn 4 , wherein n 4 is a modulus of nx 4 /k, nx 4 is one of n−1, n−2, . . . and n−ny 4 , and ny 4 is one of 1, 2, . . . , and m; wherein a current region Rn is indicated by the current phase status signal and data transition of the serial input data stream occurs between Φn−1 and Φn, wherein n is one of 0, 1, . . . , k−1 and m is an integer of (k−1)/2.