Patent ID: 7191302

Claim:
A memory control device that controls transmission of data signals from a CPU to a memory device based on a synchronization clock that cyclically repeats a predetermined state, the CPU outputting a data signal and a write start signal, the memory control device comprising: a data controller including a data latch that latches the data signal from the CPU, the data controller outputting the data signal latched in the data latch as a latched data signal; a signal line for transmitting the data signal outputted from the data controller to the memory device; and a memory control signal generation unit that receives the write start signal from the CPU and the synchronization clock, the memory control signal generation unit, based on the write start signal and the predetermined state of the synchronization clock, generating and outputting an output controlling signal that controls the data controller to output the latched data signal to the signal line and a storage controlling signal that controls the memory device to store the data signal that the data controller outputted to the signal line, the memory control signal generation unit controlling timing of at least one of the output controlling signal that controls timing that the data controller outputs the latched data signal onto the signal line, and the storage controlling signal that controls timing that the memory device stores the data signal on the data signal line.