Patent ID: 7299394

Claim:
A method for determining an optimum initial value to be input to a test pattern generator for testing an integrated circuit, comprising the steps of: a) obtaining a first test length and a first minimum test length for detecting a predetermined fault number n by performing a fault simulation and a reverse-order fault simulation using an arbitrarily given first initial value; b) computing, based on said first initial value and on said first test length and said first minimum test length, a second initial value that can yield a test length shorter than said first minimum test length; c) obtaining a second test length for detecting said fault number n by performing a second fault simulation using said computed second initial value; d) comparing said second test length with said first minimum test length, and obtaining a second minimum test length by regarding said first minimum test length as said second minimum test length when said second test length is equal to or longer than said first minimum test length, or by performing a reverse-order fault simulation against said second fault simulation when said second test length is shorter than said first minimum test length; and e) obtaining the shortest test length by repeating said steps b), c), and d) by regarding said second initial value, said second test length, and said second minimum test length as said first initial value, said first test length, and said first minimum test length, wherein an initial value that yields the shortest test length obtained in said step e) is determined as the initial value to be input to said test pattern generator when testing said integrated circuit.