Patent ID: 8667597

Claim:
A computer system for providing tamper-resistant executable software code, comprising: an input/output unit for transferring commands to a computer from an operator; a processor for responding to commands from the operator; a memory comprising non-transitory computer memory media having stored therein a computer program, the computer program comprising a set of instructions that, when executed by the processor, cause the computer to provide tamper-resistant executable software code by performing the operations of: encoding a code segment being protected by rearranging its instructions in contiguous memory, formatting each instruction of an instruction set contained within the code segment being protected to use operand indirect addressing, each instruction comprising an opcode and one or more index values to a corresponding one or more tables of indirect address entries, one index value for each operand position or field of one or more operand positions or fields in each instruction in the instruction set, each table of the one or more tables of indirect address entries containing a plurality of indirect addresses of a corresponding plurality of operands in one of the one or more operand positions or fields for a corresponding plurality of instructions of the instruction set, storing each table of indirect address entries associated with the code segment in memory, and storing a plurality of next sequential instruction index values in a jump table, the jump table configured to be utilized to decode the encoded code segment during execution, the jump table being located in noncontiguous memory with respect to the rearranged instructions, the plurality of next sequential instruction index values comprising a corresponding plurality of offset values organized within the jump table to correspond with an organization of the rearranged instructions so that when a present instruction is not a branch instruction, or is a branch conditional instruction and its condition is false, and when referenced and added to a code segment base value, the respective offset value corresponding to the present instruction provides a program counter a memory location of the respective next sequential instruction.