Patent ID: 8258577

Claim:
A CMOS inverter, comprising: a first fin structure having source and drain regions of a first transistor in a first sidewall portion of the first fin structure, wherein the first sidewall portion of the first transistor faces away from a second fin structure, wherein a second sidewall portion of the first fin structure is directly opposite of at least one of the source and drain regions of the first fin structure and does not include a dopant used in the source and drain regions of the first fin structure; the second fin structure having source and drain regions of a second transistor in a first sidewall portion of the second fin structure, wherein the first sidewall portion of the second transistor faces away from the first transistor, wherein a second sidewall portion of the second fin structure is directly opposite of at least one of the source and drain regions of the second fin structure and does not include a dopant used in the source and drain regions of the second fin structure; a high-k dielectric layer covering at least part of the first sidewall portions of the first and second fin structures, wherein the dielectric layer physically connects the first fin structure to the second fin structure such that a thickness, in a direction perpendicular to top surfaces of the first and second fin structures, of an entire portion of the dielectric layer in a region between the first and second fin structures is greater than respective thicknesses of the first and second fin structures; and a mid-gap metal gate layer formed on a portion of the dielectric layer.