Patent ID: 8103861

Claim:
A computer system comprising: a first processor having a processor bus, the first processor configured to execute a program; a second processor having a processor bus, the second processor configured to execute a duplicate copy of the program in lock step with the first processor; and a logic device coupled to the processor bus of the first processor, and the processor bus of the second processor, the logic device configured to receive read operations from the first and second processors over the respective processor buses; wherein the logic device is configured to present an interrupt request to the processors when the processors are at substantially the same computational point in the program; wherein the logic device further comprises: a first buffer associated with the first processor; and a second buffer associated with the second processor; wherein the logic device presents the interrupt request to the processors when there are matched cached reads in the first and second buffers; and wherein the logic device is configured to request re-presentation (NACK) of the matched cached reads, and then present the interrupt request to the processors when the matched cached reads are found again in the first and second buffers within a predetermined period of time.