Patent ID: 8420488

Claim:
A method of fabricating a high voltage device, wherein the method comprises: forming two isolation structures in the substrate; forming a composite dielectric layer on a substrate, wherein the composite dielectric layer is a combination of at least one thermal oxide layer and at least one chemical vapor deposited layer, the step of forming the composite dielectric layer comprising: forming a patterned mask layer on the substrate, wherein the patterned mask layer comprises an opening that exposes the substrate; performing a thermal oxidation process to grow the thermal oxide layer on the substrate exposed by the opening; performing a chemical vapor deposition process to form a deposited silicon oxide layer on the thermal oxide layer forming a gate on the composite dielectric layer after the step of forming the composite dielectric layer; and forming a source region and a drain region in the substrate respectively beside two sides of the gate, wherein the chemical vapor deposited layer partially covers the isolation structures after formation of the source region and the drain region.