Patent ID: 8843873

Claim:
A method of estimating capacitive cell load in an integrated circuit design using an electronic design automation (EDA) tool, wherein the EDA tool includes a processor and a memory coupled to the processor, wherein the integrated circuit design is stored in the memory, comprising: a) using first maximum capacitive load values stored in the memory to calculate, using the processor, a risk of electromigration failure in cells of the integrated circuit design, and saving the first maximum capacitive load values for cells whose risk of electromigration failure is acceptable; b) for a failed cell from step a), calculating, using the processor, a revised maximum capacitive load value that is equal to the first maximum capacitive load value reduced as a function of an actual current relative to an electromigration current limit in a weakest element that has the smallest electromigration current limit in the electromigration calculation of step a) for the failed cell; c) calculating, using the processor, a revised actual current in the weakest element as a function of transition times with the revised maximum capacitive load value for the failed cell; and d) saving the revised maximum capacitive load value for the failed cell if the revised actual current is less than the electromigration current limit of the weakest element, or otherwise re-iterating steps b) to d); wherein the revised maximum capacitive load value of step b) is reduced relative to the first value of step a) for the first performance of step b) for a cell, and is further reduced relative to the previous revised maximum capacitive load value of step d) for a subsequent iteration of steps b) to d) for the failed cell.