Patent ID: 8141025

Claim:
A method for statistically analyzing the timing performance of an integrated circuit (IC) chip design given a predetermined slack filtering criterion, the method comprising: a) using a computer, performing a deterministic static timing analysis of said IC chip design to obtain deterministic values of timing parameters of said IC chip design; b) computing a deterministic edge or node slack for each timing edge or node of said IC chip design from said deterministic values of said timing parameters; c) approximating the deterministic value of at least one timing parameter to its statistical representation if said deterministic edge or node slack meets said filtering criterion; otherwise, computing an actual statistical representation of the at least one timing parameter; and d) conducting the statistical analysis of the timing performance of the IC chip design by propagating mixed-mode deterministic and said actual statistical timing parameters throughout said IC chip design, e) wherein said slack filtering criterion is determined by edge or a node slack of timing edge or a node compared to a predetermined lower threshold value.