Patent ID: 7712050

Claim:
In a design tool used to design an electronic circuit, a method comprising: displaying a top-level schedule, in a bar chart, for a design that includes one or more loops associated with the electronic circuit, the top-level schedule being divided into steps, where each step represents a clock cycle in a iteration of a loop, and wherein timing within the top-level schedule is presented relative to the top-level schedule; and displaying a first loop schedule, nested within the top-level schedule, for a first loop of the one or more loops, wherein timing within the first loop schedule is independent of top-level clock timing and is presented relative to the first loop schedule, with the first loop schedule being divided into sub-steps, wherein each sub-step represents a clock cycle in an iteration of the first loop and the first loop schedule, including the sub-steps, is presented within a step of the top-level schedule.