Patent ID: 7838345

Claim:
A process of forming an electronic device comprising: providing a base layer including a semiconductor material, an insulating layer overlying the base layer, and a semiconductor layer overlying the insulating layer; forming a first semiconductor fin from the semiconductor layer, wherein forming the first semiconductor fin comprises forming the first semiconductor fin spaced apart from the base layer and having a first length; forming a second semiconductor fin from the semiconductor layer and spaced-apart from the first semiconductor fin, wherein forming the second semiconductor fin comprises forming the second semiconductor fin spaced apart from the base layer and having a second length; forming a first bridge lying between the first semiconductor fin and the second semiconductor fin, wherein forming the first bridge comprises forming the first bridge such that the first bridge contacts the first semiconductor fin along only a portion of the first length, and the second semiconductor fin along only a portion of the second length; forming a first source/drain region within the first semiconductor fin and a second source/drain region within the second semiconductor fin, wherein the first and second source/drain regions are spaced-apart from and electrically coupled to each other; and forming a third source/drain region within the first semiconductor fin and a fourth source/drain region within the second semiconductor fin, wherein the third and fourth source/drain regions are spaced-apart from and electrically coupled to each other.