Patent ID: 8859371

Claim:
A method of manufacturing a semiconductor device, comprising: providing a substrate including a first region and a second region; forming a first gate dielectric layer having a first thickness on the substrate; forming an interlayer insulating layer on the substrate, the interlayer insulating layer including a first trench exposing the first gate dielectric layer of the first region and a second trench exposing the first gate dielectric layer of the second region; forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches; forming a mask pattern covering the second trench of the second region on the sacrificial layer; removing the sacrificial layer in the first region using the mask pattern as an etch mask to form a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench; removing the first gate dielectric layer of the bottom of the first trench to expose the substrate; removing the mask pattern; removing the sacrificial pattern; forming a second gate dielectric layer having a second thickness on the bottom of the first trench; and forming a gate electrode on each of the first gate dielectric layer and the second gate dielectric layer.