Patent ID: 7535273

Claim:
A phase-locked loop circuit comprising: feedback means for outputting an output signal which is a binary signal as a feedback signal; a phase comparator which receives the feedback signal and an input signal, and outputs a phase signal representing a lead or a lag of a phase of the feedback signal to the input signal; a counter which receives the phase signal, increases a value in the control signal when the phase signal has a value representing a lead of the phase, and decreases a value in the control signal when the phase signal has a value representing a lag of the phase; and a ring oscillator which receives the control signal, outputs the output signal, prolongs an oscillation cycle of the output signal as the value in the control signal is large, and shortens the oscillation cycle of the output signal as the value is small; wherein said phase comparator comprises a dynamic D flip-flop and a non-dynamic D flip-flop to which an output from the dynamic D flip-flop is inputted, where the dynamic D flip-flop has a structure in which dynamic latch circuits each of which is configured by combining an analog switch with a parasitic capacitance are connected with each other on two stages in a subordinate manner, and the non-dynamic D flip-flop has a structure in which latch circuits each of which is configured by combining an analog switch with an inverter are connected with each other on two stages in a subordinate manner.