Patent ID: 7774674

Claim:
A method for decoding a Low-Density Parity-Check (LDPC) encoded codeword, the LDPC code being represented by a bipartite graph between check nodes and variable nodes including first variable nodes, the method comprising: mapping the variable nodes and the check nodes on a partly parallel architecture clocked by a clock signal and including P processing units which update messages exchanged iteratively between the first variable nodes and check nodes through a shifting network controlled by shift values, and P main memory banks respectively associated with the P processing units, each main memory bank comprising at least two single port memory partitions and a buffer; updating messages including reading messages to be updated from P main memory banks at reading addresses and writing the updated messages at the same addresses and in view of the shift values; and within a same clock cycle and for each main memory bank, the updating further comprises reading and writing into two different memory partitions, or reading one memory partition and writing into the buffer.