Patent ID: 8275963

Claim:
A distributed data processing system comprising: a first node having: a processor; a modified instruction set architecture (ISA) that includes a specialized store operation for processing asynchronous memory move (AMM) store instructions; an instruction fetch unit that retrieves instructions from an instruction stream, where the instructions are provided by the ISA; a memory subsystem including at least a first memory coupled to the processor and including a plurality of physical locations having real addresses for storing data; an asynchronous memory mover coupled to the memory subsystem and separate from the processor, wherein the asynchronous memory mover receives information from the processor; and a network interface card (NIC) that enables a connection of the first node to and communication with remote devices via a network, wherein the NIC is coupled to the asynchronous memory mover, the memory subsystem, and the processor via a system interconnect; a second node having a second memory with at least one physical location with a real address for storing data; a connection mechanism for coupling said first node to said second node, wherein the connection mechanism includes a connection to the NIC; and processing logic executing on the processor for performing a cross-node AMM operation, the processing logic further comprising instructions that cause the processor to: receive an AMM store instruction, wherein the AMM store instruction comprises: a source effective address, a destination effective address, a count value for the amount of data to be moved, and an entry indicating a destination node identifier (ID) from among the first node and the second node; and responsive to receiving the AMM store instruction: perform a data move operation of data in virtual address space from a first effective address to a second effective address utilizing the effective addresses of the AMM store instruction, wherein the processor initiates the data move operation without translating the effective addresses; and trigger the asynchronous memory mover logic to complete a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address, wherein the data is transmitted independent of the processor via the asynchronous memory mover, the NIC and the connection mechanism coupling the first node and the second node, and wherein the asynchronous memory mover logic initiates the translation of the effective addresses to identify the first real address and the second real address.