Patent ID: 8619975

Claim:
A cipher processing apparatus for arithmetic operations of an FO function and an FL function in a cipher process, comprising: a first circuitry configured to generate a 2N-bit output by an arithmetic operation of the FL function based on a 2N-bit input and a first extension key; a second circuitry configured to generate an N-bit output by an arithmetic operation of a partial function of an FI function based on an N-bit input and second and third extension keys; an N-bit intermediate register configured to store an output of the second circuitry; a 2N-bit first data register configured to store data based on the output of the first circuitry; a controller configured to make the second circuitry perform six cycles of the arithmetic operation of the partial function, inputting an output of the N-bit intermediate register to the first circuitry, and storing the data based on the output of the first circuitry in the 2N-bit first data register, in a first case in which the FL function uses a result of an arithmetic operation of the FO function; and a third circuitry configured to generate a correction bit string of 2N bits based on the first extension key, wherein the controller makes the first circuitry perform the arithmetic operation of the FL function even numbers of times, executes an XOR operation between the correction bit string generated by the third circuitry and the output of the first circuitry, and stores a result of the XOR operation in the first data register, in the first case, wherein N is a number greater than 0.