Patent ID: 7069411

Claim:
A mapper circuit for providing associations between logical registers and physical registers, the mapper circuit comprising a memory, the memory comprising: a plurality of addressable units, each addressable unit addressed by a different logical register name (LRN) to which that addressable unit is statically assigned, and each addressable unit including a plurality of storage locations, wherein a first storage location of the plurality of storage locations is configured to store a current physical register name (PRN) currently assigned to the LRN, and wherein each other storage location of the plurality of storage locations is configured to store an additional PRN previously assigned to the LRN; and a control circuit coupled to the plurality of addressable units, wherein the control circuit is configured, responsive to a new PRN being assigned to a first LRN that addresses a first addressable unit of the plurality of addressable units, to cause the current PRN in the first storage location of the first addressable unit to be copied to a second storage location which is one of the other storage locations of the first addressable unit, wherein the second storage location corresponds to a current checkpoint of a plurality of checkpoints.