Patent ID: 7106643

Claim:
A method for manufacturing a memory device comprising the steps of: (a) preparing a semiconductor chip formed with a plurality of memory mats each having a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells, a plurality of bit line selection lines each coupled to said plurality of memory mats, a spare bit line selection line coupled to said plurality of memory mats, and a redundancy circuit having a pair of comparison circuits and programmable memory means, wherein, at a memory access, one of said plurality of memory mats is selected and one of said plurality of word lines in the selected memory mat is activated, wherein respective ones of the plurality of bit lines in said plurality of memory mats are selected when one of said plurality of bit line selection lines is activated, wherein the respective spare bit lines in said plurality of memory mats are selected when said spare bit line selection line is activated, wherein each of said pair of comparison circuits is configured so that its output is coupled to said spare bit line selection line, and so that information stored in said memory means is compared with input signals including address signals indicative of selections of memory mats and address signals indicative of selections of bit line selection lines in operation of the memory device; and (b) programming said programmable memory means, when a defect is found on said semiconductor chip, so as to store defect information indicative of one of the bit line selection lines associated with the defect and indicative of one of the plurality of memory mats associated with the defect thereby to activate said redundancy circuit in operation of the memory device.