Patent ID: 8487803

Claim:
A pipelined analog-to-digital converter (ADC) comprising: a first pipeline ADC stage configured to receive an analog input signal, sample the analog input signal at a first frequency, generate a first residue signal at the first frequency, wherein the residue signal is responsive to the sampled analog input signal; and a second pipeline ADC stage, coupled to receive the first residue signal from the first pipeline ADC stage, and comprising a first plurality of sample circuits each configured to sample the first residue signal at a second frequency, wherein the first plurality of sample circuits comprises N sample circuits wherein N is two or more, the second frequency is 1/N times the first frequency, each of the first plurality of sample circuits samples a unique portion of the first residue signal from each other of the first plurality of sample circuits, and the second pipeline ADC stage is configured to generate a second residue signal at the first frequency.