Patent ID: 7126375

Claim:
A core of an integrated circuit, comprising: a first region comprising a first plurality of cells organized along a first dimension and a second dimension, wherein a span of first region is less than a span of the core along the first dimension and the span of the first region is less than the span of the core along the second dimension; the first region further comprising: a first plurality of conductors spanning the first plurality of cells along the first dimension and the second dimension within the first region, wherein each conductor of the first plurality of conductors is configured to selectively couple to the cells of the first plurality of cells and other conductors of the first plurality of conductors through a plurality of switches and wherein each conductor of the first plurality of conductors is configured to selective couple to outputs of two cells of the first plurality of cells through independently controlled switches, wherein the first plurality of conductors comprise: a first conductor having a first span along the first dimension; and a second conductor having a second span along the second dimension, wherein the second conductor is configured to selectively couple to drive the first conductor, in sequence, through a first switch, a first driver and a second switch, and wherein the second conductor is configured to selectively couple to drive the first conductor, in sequence, through a third switch, a second driver and a fourth switch.