Patent ID: 7181664

Claim:
A method of reordering a scan chain for design of testability on VLSI with low power dissipation, comprising: (a) inputting scan chain register circuit data, including a name of each register, 2D coordinates, and power dissipation value(s); (b) inputting test pattern data on the scan chain; (c) inputting conditions of design specification including peak value of power dissipation at a time of potential conversion of register; maximum of total connection length of the scan chain; and maximum of connection distance between two adjacent registers; (d) determining whether a Feasible Solution meeting the maximum of connection distance between the two adjacent registers is provided; (e) creating a database of the two adjacent registers; (f) if an event meeting both the maximum of the total connection length and the maximum of connection distance, the total length of the scan chain being ignored; (g) for a given test pattern, re-ordering the registers on the scan chain for reduction of power dissipation, and whether determining peak value limit of power dissipation and the maximum of total connection length for the scan chain accord; and (h) outputting an updated scan chain arrangement and a corresponding scan chain test pattern data, wherein the event meeting the maximum of the total connection length of the scan chain is ignored in case of: (a) L lim <L min : no feasible solution given; (b) L min <=L lim <L max : at the time of the arrangement of the scan chain register at a next step, in addition to a search for a combination of the peak values in the adjacent registers so as to reduce power dissipation, a case beyond the total limit of length of the maximum scan chain also being taken into consideration so that the registers must be arranged to shorten the scan chain on the occasion; and (c) L lim <L max : at the time of arrangement of the scan chain registers at a next step, the total limit of length of the maximum scan chain not being taken into consideration but a search for a set of peak values in the adjacent registers to reduce power dissipation; wherein i stands for any of the registers, and the distance D i min indicates the distance of a register i closer to the other registers, the distance D i max indicates the distance of a register i further from the other registers, and the distance D i avg indicates the distance of a register i equidistant from the other registers are estimated, namely L min =Σ i D i min , L max =, Σ i D i max , and L avg =Σ i D i avg .