Patent ID: 8067291

Claim:
A manufacturing method of a MOS field-effect transistor, comprising steps of: forming a stressor composed of a compound having a lattice constant different from that of silicon in a portion inside an active region that is separated by an insulating film formed on a silicon substrate; forming a silicon channel layer formed with silicon above the stressor; wherein the stressor is formed in the active region that is separated by the insulating film formed inside the silicon substrate; forming a tensile stress layer so as to surround a gate electrode and a sidewall formed on the gate electrode, wherein the stressor is formed inside the tensile stress layer; etching the silicon channel layer and said stressor in a source/drain region of the MOS field-effect transistor; removing the remaining silicon stressor directly under the silicon channel layer to form a depletion area; and filling back a portion that has been etched, with silicon by chemical vapor deposition, the portion except the depletion area.