Patent ID: 8477545

Claim:
A semiconductor apparatus comprising: a first chip column control unit disposed in a first chip and configured to variably delay an internal column command to generate a first chip column control signal; and a second chip column control unit disposed in a second chip and configured to variably delay the internal column command to generate a second chip column control signal, wherein the first chip column control unit comprises a first delay control section configured to count a first number of times that a clock signal toggles during a first time period and to generate a first calibration signal, and a first variable delay section configured to variably delay the internal column command in response to the first calibration signal and to generate the first chip column control signal, and wherein the first delay control section comprises a first ring oscillator configured to generate an enable signal which is enabled during the first time period, and a first counting part configured to count the first number of times that the clock signal toggles in response to the enable signal and to generate the first calibration signal.