Patent ID: 8916958

Claim:
A semiconductor package, comprising: a set of first semiconductor chips arranged in a first array; a set of second semiconductor chips arranged in a second array having the same dimensions as the first array; a first substrate; a second substrate; and a metal cap, wherein the first semiconductor chips and the second semiconductor chips are electrically connected to the first substrate, the second substrate is disposed between the first semiconductor chips and the second semiconductor chips, wherein the second substrate comprises an insulating layer and a thermally conductive layer on a side of the second substrate facing the first semiconductor chips, and the first semiconductor chips and the second semiconductor chips and the second substrate are disposed within and sealed within a gas-filled cavity, wherein the first semiconductor chips are vertically aligned with the second semiconductor chips, wherein the second semiconductor disposed on and electrically connected to one or more conductive traces disposed directly on the second substrate, and wherein the first semiconductor chips are disposed on and electrically connected to one or more conductive traces disposed directly on the first substrate; one or more wire bonds extending from the one or more conductive traces disposed on the first substrate to the one or more conductive traces on the second substrate so as to electrically connect one or more of the first second semiconductor chips to a corresponding vertically aligned one of the second semiconductor chips; wherein the first substrate and the metal cap form a sealed enclosure with the gas-filled cavity, wherein heat from the first chip is dissipated to the metal cap by air convection via the second substrate.