Patent ID: 8248102

Claim:
An integrated circuit (IC) comprising: a plurality of configuration data storage elements for storing a plurality of configuration data sets; and a region comprising: an arrangement of configurable logic circuits of a particular type having a plurality of rows and a plurality of columns, wherein each configurable logic circuit is for performing one of a plurality of operations based on one of the plurality of configuration data sets, wherein at least one of the plurality of operations is a mathematical operation that produces propagate and generate signals for performing a larger mathematical operation; and a direct connection connecting first and second configurable logic circuits in said arrangement in order to enable the first and second configurable logic circuits to perform the larger mathematical operation, wherein the first configurable logic circuit and the second configurable logic circuit are not vertically or horizontally aligned and are separated by at least three rows and at least one column or at least three columns and at least one row of configurable logic circuits of the particular type, the direct connection comprising a plurality of wire segments and a plurality of intervening buffer circuits along the plurality of wire segments for relaying a signal from the first configurable logic circuit to the second configurable logic circuit.