Patent ID: 8085101

Claim:
A spread-spectrum clock generator comprising: a PLL; a spread spectrum controller controlling the PLL so that the PLL outputs a spread-spectrum processed clock signal; and a loop bandwidth controller changing a loop bandwidth of the PLL during operation of the spread spectrum controller; wherein the PLL includes: a voltage-controlled oscillator oscillating at a frequency according to an input voltage, a frequency divider dividing a frequency of an output of the voltage-controlled oscillator, a phase detector comparing phases of a reference clock signal and an output of the frequency divider, and a loop filter smoothing an output of the phase detector, and outputting a voltage for controlling the voltage-controlled oscillator, and the loop bandwidth controller controls at least one of the phase detector, the loop filter, the voltage-controlled oscillator, and the frequency divider to change the loop bandwidth of the PPL, and wherein the PLL further includes a second frequency divider dividing a frequency of an original clock signal to generate the reference clock signal, and the loop bandwidth controller also controls the second frequency divider when controlling the frequency divider.