Patent ID: 7082511

Claim:
An address translation unit performing address translation from a virtual address to a physical address, comprising: a data entry part holding data of said physical address; and a tag entry part storing an address space identifier and virtual address as a tag of said data entry part, said tag entry part comprising: an address space identifier hold part holding said address space identifier; an address space identifier comparison judgment part comparing an address space identifier hold value held in said address space identifier hold part with an address space identifier input value to be inputted newly; a virtual address hold part holding said virtual address; and a virtual address comparison judgment part comparing a virtual address hold value held in said virtual address hold part with a virtual address input value to be inputted newly, said virtual address comparison judgment part having a charge circuit for charging its output line and a charge inhibit circuit for inhibiting charge to said output line, wherein a potential state of said output line is controlled based on the comparison result between said address space identifier hold value and said address space identifier input value, to determine execution or non-execution of comparison operation between said virtual address hold value and said virtual address input value at the time of address translation, wherein said address space identifier hold part and said virtual address hold part are each configured by a content addressable memory, a content addressable memory cell configuring said address space identifier hold part is connected to an address space identifier comparison match line and also connected to said address space identifier comparison judgment part, a content addressable memory cell configuring said virtual address hold part is connected to a virtual address comparison match line and also connected to said virtual address comparison judgment part, and said virtual address comparison judgment part receives a comparison result signal obtained in said address space identifier comparison judgment part and, when said address space identifier hold value matches said address space identifier input value, maintains said virtual address comparison match line in a floating state and performs a comparison at least between said virtual address hold value and said virtual address input value.