Patent ID: 7750402

Claim:
A power semiconductor device comprising: a semiconductor substrate of a first conductivity type; a source region of a second conductivity type formed in a surface portion of said semiconductor substrate, said source region being formed in a well of said first conductivity type, said well having a higher impurity concentration than said semiconductor substrate; a drain drift region of said second conductivity type formed in the surface portion of said semiconductor substrate, said drain drift region being apart from said well containing said source region, as separated by said semiconductor substrate; a drain region of said second conductivity type formed in a surface portion of said drain drift region, said drain region having a larger impurity concentration than said drain drift region; a drain buried region of said second conductivity type formed immediately below said drain region in said drain drift region, said drain buried region having a larger impurity concentration than said drain drift region; a gate insulating layer formed on said semiconductor substrate between said source region and said drain drift region; and a gate electrode formed on said gate insulating layer, wherein a transverse size of said drain buried region, at each point along a longitudinal axis of said drain buried region, is smaller than a transverse size of said drain region.