Patent ID: 6865654

Claim:
A device for interfacing asynchronous data in which data transfer is performed between an external data processor and a data buffer, the device comprising: a data input unit for outputting an asynchronous data transfer request signal DREQ to the external data processor in a data receipt mode, for temporarily storing and outputting the asynchronous data input from the external data processor according to a transfer information signal DACK 13 I of the external data processor and a write signal of a FIFO, and for generating a transfer information signal DACK 13 IN which indicates that the asynchronous data is input to the data input unit; a data output unit for receiving a synchronous data signal ODATA from the FIFO while receiving the asynchronous data transfer request signal DREQ in a data transfer mode, thereby outputting an asynchronous data signal DATA 13 O and a transfer information signal DACK 13 O; the FIFO for storing the data output from one of the data buffer and the data input unit in correspondence with a write request signal, for outputting the data output from one of the data buffer and the data input unit in correspondence with a read request signal, and for generating state flag signals in correspondence with an amount of data remaining in one of the data buffer and the data input unit; and a control unit for generating a data buffer enable signal and signals for controlling read and write of the FIFO in correspondence with the transfer information signal DACK 13 IN and the state flag signals.