Patent ID: 7327820

Claim:
A method for reducing the phase noise generated by relative propagation delay in a fractional-N frequency synthesizer having a first phase detector and a second phase detector, the method comprising: dividing a voltage controlled oscillator (VCO) signal by one of an integer and one more than the integer based on a predetermined fractional value; generating a first phase signal as a first current responsive to a phase error between a reference signal and the divided VCO signal; generating a second phase signal as a second current responsive to a phase error between the reference signal and a delayed divided VCO signal; generating a swap signal having a first state and a second state; providing the first phase signal to a first phase detector and a second phase signal to a second phase detector when the swap signal is in the first state; providing the first phase signal to the second phase detector and the second phase signal to the first phase detector when the swap signal is in the second state; generating a first sum current by adding a first predetermined bias current to the first current; generating a second sum current by adding a second predetermined bias current to the second current; and combining the first and second sum currents.