Patent ID: 7746683

Claim:
A NOR memory arrangement comprising a plurality of resistive memory elements, each memory element comprising: a resistive memory cell comprising a resistive memory material; and a MOS memory cell selection transistor connected in series, via a source-drain path of the selection transistor, to the resistive memory cell; wherein each memory element is connected via the source-drain path of the selection transistor to a first current line that applies a reference voltage, each memory element is connected via the resistive memory cell to a second current line that applies an operating voltage, each memory element is connected to a third current line via a gate terminal of the MOS memory cell selection transistor, the first current line is disposed at a location between the second current line and the third current line, the first and third current lines extend in directions that are transverse a direction in which the second current line extends, and at least an isolation layer separates neighboring second current lines.