Patent ID: 8159862

Claim:
A circuit comprising: a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate configured to receive a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate configured to receive a second voltage, wherein the first PMOS transistor is configured to automatically turn off based on a first value of the first voltage and a first node voltage value at the first node; the first NMOS transistor is configured to automatically turn off based on a second value of the second voltage and a second node voltage value at the second node; when the first PMOS transistor, the first control transistor, and the first NMOS transistor are on, the first node voltage value is lowered while the second voltage value is raised; and the first control transistor is one of a second PMOS transistor or a second NMOS transistor and is configured to receive a control signal at a gate of the first control transistor.