Patent ID: 7354833

Claim:
A method for improving threshold voltage stability of at least one metal-oxide-semiconductor (MOS) device, comprising: forming at least one well on a semiconductor substrate; forming a gate dielectric layer on the well of the semiconductor substrate; forming a gate conductive layer on the gate dielectric layer; patterning the gate conductive layer and the gate dielectric layer; implanting ions into the well to form at least one first buried doped region beneath the gate dielectric layer, and one or more second buried doped regions within the well, wherein a shortest distance between the first buried doped region and the gate dielectric layer is no greater than about 1,500 angstroms; and forming one or more lightly doped drain (LDD) regions adjacent to the patterned gate conductive and dielectric layers, wherein the one or more second buried doped regions are located beneath the LDD regions.