Patent ID: 7176740

Claim:
A level conversion circuit for receiving an input signal changing between a first voltage level and a reference voltage and generating an output signal changing between a second voltage level, which is greater than the first voltage level, and the reference voltage, the level conversion circuit comprising: a first PMOS transistor including a drain and a gate; a second PMOS transistor including a drain and a gate; a first NMOS transistor including a drain, a gate, and a source, the drain of the first NMOS transistor being connected to the drain of the first PMOS transistor and the gate of the second PMOS transistor; a second NMOS transistor including a drain, a gate, and a source, the drain of the second NMOS transistor being connected to the drain of the second PMOS transistor and the gate of the first PMOS transistor; a third NMOS transistor including a gate for receiving the input signal and a drain connected to the source of the first NMOS transistor; a fourth NMOS transistor including a gate for receiving an inverted input signal and a drain connected to the source of the second NMOS transistor; and a bias circuit connected to the gates of the first and second NMOS transistors, the bias circuit generating a first bias potential that is supplied to the gates of the first and second NMOS transistors and that is greater than the first voltage level by a threshold voltage of the first and second NMOS transistors, the bias circuit further controlling current, which determines the first bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage level, wherein the bias circuit includes an NMOS transistor including a drain and a gate both connected to the gates of the first and second NMOS transistors and a source supplied with the first voltage level; and a power on reset circuit, connected to the bias circuit, for generating a reset signal that is supplied to the bias circuit when changing of the second voltage level from the reference voltage is detected, the bias circuit increasing the current flowing to the bias circuit in accordance with the reset signal.