Patent ID: 7439170

Claim:
A method of manufacturing a semiconductor package comprising: providing at least one ball limiting metallurgy layer; providing at least one final passivation layer having at least one final passivation layer via wherein the at least one final passivation layer via has a diameter, wherein the final passivation layer is below the ball limiting metallurgy layer; providing at least one aluminum layer in a via in a hard dielectric passivation layer; said aluminum layer having projections wherein a portion of the final passivation layer is above the projections and a portion of the final passivation layer is below the projections; said via in a hard dielectric passivation layer having a smaller diameter than the final passivation layer via diameter; providing at least one last metallization copper layer below the aluminum layer; providing at least one via below the last metallization copper layer with a reduced stress and strain in the semiconductor package.