Patent ID: 7436830

Claim:
A data packet classifier to classify a plurality of N-bit input tuples, said classifier comprising: a hash address generator to generate a plurality of M-bit hash addresses from said plurality of N-bit input tuples, wherein M is significantly smaller than N; a hash bucket memory having a plurality of memory entries, said memory being addressable by said plurality of M-bit hash addresses, each such address corresponding to a plurality of memory entries, each of said plurality of memory entries storing one of said plurality of N-bit tuples mapped to said M-bit hash address and at least an associated process flow information, wherein at least one of said memory entries corresponds to a full duplex process flow between first and second network nodes; and a comparison unit to determine if an incoming N-bit tuple of a packet can be matched with a stored N-bit tuple, wherein said associated process flow information is output if a match is found and wherein a new entry is created in the memory for the incoming N-bit tuple if a match is not found, said data packet classifier further making said comparison between said incoming N-bit tuple and said stored N-bit tuple so as to identify said full duplex process flow regardless of whether the packet flows upstream or downstream between said first and second network nodes.