Patent ID: 8504892

Claim:
A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder comprising: a channel memory arranged to store channel values initially corresponding to log-likelihood ratios of symbols received via a transmission channel; a metrics memory arranged to store metrics values; first and second operand supply paths each arranged to provide operands based on the channel values and the metrics values; a processor block comprising a plurality of processing units in parallel and arranged to receive operands from said first operand supply path and to determine updated metric values based on said operands; a buffer arranged to store at least one of said operands from said first operand supply path; an adder coupled to an output of the processor block and arranged to generate updated channel values by adding said updated metrics values to operands from a selected one of said buffer and said second operand supply path; and a first multiplexer having a first input coupled to the second operand supply path and a second input coupled to an output of the buffer, and an output coupled to an input of the adder.