Patent ID: 8120091

Claim:
A non-volatile memory device, comprising: an isolation layer pattern on a substrate, the isolation layer pattern extending in a first direction; a tunnel insulation layer pattern on the substrate between the isolation layer pattern, each portion of the tunnel insulation pattern extending along a first direction, adjacent portions of the tunnel insulation layer pattern being separated in a second direction that is substantially perpendicular to the first direction; and a gate structure formed on the tunnel insulation layer pattern, the gate structure comprising a floating gate formed on the tunnel insulation layer pattern, a first conductive layer pattern formed on the floating gate, the first conductive layer pattern being separated both in the first and second directions, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction, wherein an upper face of the isolation layer pattern has a level higher than an upper face of the first conductive layer pattern and lower than an upper face of the dielectric layer pattern, and wherein the first conductive layer directly contacts a bottom surface of the dielectric layer.