Patent ID: 8838665

Claim:
A microprocessor, comprising: fetch logic for retrieving an instruction; decode logic configured to identify a plurality of operands and a multiply operation specified in the instruction; and execution logic configured to receive the plurality of operands and the multiply operation, the execution logic including: a first logic path configured to perform the multiply operation on the plurality of operands and output a result; and a second logic path, arranged in parallel with the first logic path, configured to output metadata associated with the result of the multiply operation, where the metadata includes at least one condition code, and wherein the second logic path includes: a first encoder operable to perform a trailing-one encode operation on a first operand of the plurality of operands and output a first zero value indicating whether the first operand is zero or non-zero and a first encoded value representative of a number of trailing zeros in the first operand; a second encoder operable to perform a trailing-one encode operation on a second operand of the plurality of operands and output a second zero value indicating whether the second operand is zero or non zero and a second encoded value representative of a number of trailing zeros in the second operand; a carry look-ahead adder operable to receive the first encoded value and the second encoded value and output a carry out value indicating whether or not the number of trailing zeros of the result is greater than or equal to n; and a logic gate operable to receive the first zero value, the second zero value, and the carry out value and output a zero flag indicating whether the result is zero or non-zero.