Patent ID: 6847075

Claim:
A semiconductor integrated circuit apparatus, comprising: a substrate; a first element region being formed on said substrate, said first element region having a first conductive type; a second element region being formed on said substrate, said second element region having a second conductive type; a third element region being formed on said substrate, said third element region having the second conductive type; a first MOS transistor being formed in a transistor region of said first element region, said first MOS transistor having a second conductive type channel; a capacitor being formed in a capacitor region of said first element region; a second MOS transistor being formed on said second element region, said second MOS transistor having a first gate insulation film of a first film thickness and a first conductive type channel; and a third MOS transistor being formed on said third element region, said third MOS transistor having a second gate insulation film of a second film thickness greater than said first film thickness and the first conductive type channel, wherein said third MOS transistor has a channel region channel-doped under a first profile by using a second conductive type impurity element, said second MOS transistor has a channel region channel-doped under a second profile, which is a higher density profile, by using the second conductive type impurity element, and the second conductive type impurity element is imported in said capacitor region in the first element region under a profile substantially identical to a subtraction of a channel dope of said third MOS transistor from a channel dope of said second MOS transistor so as to form a diffusion region that serves as a lower electrode of said capacitor.