Patent ID: 7830739

Claim:
A semiconductor memory device in which a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines, comprising: a plurality of unit blocks connected in cascade into which the memory cell array is divided; a plurality of rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in said unit block and each including a plurality of sense amplifiers for amplifying data of the memory cells for each bit line pair; first switch means for switching a connection state between said unit block and said row of sense amplifiers attached to said unit block; two cache memories for storing two said rows of sense amplifiers attached to one of said unit blocks; second switch means for switching a connection state between unshared rows of sense amplifiers attached only to said unit block located at both ends of the memory cell array and said cache memories; and control means for controlling said first switch means and said second switch means so as to form a transfer path from said row of sense amplifiers attached to a predetermined said unit block leading to said cache memory using the plurality of bit lines, and for performing a transfer operation of data in said row of sense amplifier to said cache memory through the transfer path.