Patent ID: 7545168

Claim:
A clock tree distribution network for a field programmable gate array (FPGA) comprising: a clock-source selector providing a root signal selected from at least one of an external clock signal, an internal clock signal and at least one phase lock loop cell output signal; an array of programmable logic coupled to the clock-source selector, the logic array having a plurality of combinatorial logic modules having inputs and a plurality of sequential logic modules having clock inputs; a hardwired clock network that selects a signal from at least one of the root signal, a local signal from the array of programmable logic, a positive power supply signal, and a ground signal and routes the selected signal to the clock inputs of the plurality of sequential logic modules in the array of programmable logic; and a routed clock network that selects a signal from at least one of the root signal, a local signal from the array of programmable logic, a positive power supply signal, and a ground signal and routes the selected signal through at least one programmable element to at least one of the clock inputs of the plurality of sequential logic modules in the array of programmable logic.