Patent ID: 7392496

Claim:
A method of avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit comprising steps of: (a) receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer; (b) finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information; (c) identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer; (d) calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire; and (e) generating as output at least one of the wire width and the fracture interval for the dummy metal wire.