Patent ID: 8654823

Claim:
A data link interface comprising: a programmable delay chain configured to provide an amount of delay to a first clock signal, wherein the first clock signal clocks a first portion of a data path; a phase interpolator configured to provide an amount of phase offset to a second clock signal; a frequency divider coupled to an output of the phase interpolator and receiving the second clock signal, wherein the frequency divider is configured to generate a third clock signal being a frequency divided version of the second clock signal, and wherein the third clock signal clocks a second portion of the data path, wherein the first portion and the second portion of the data path are directly coupled; a latency detector coupled to the frequency divider and the programmable delay chain, wherein the latency detector is configured to measure a phase difference between the first and third clock signals and vary at least one of the amount of delay applied to the first clock signal or the amount of phase offset on the second clock signal responsive to the phase difference; and wherein the latency detector further comprises a delay and sample module configured to sample a first data signal derived from the first clock signal while being clocked according to the third clock signal and to sample a second data signal derived from the third clock signal while being clocked according to the first clock signal.