Patent ID: 8335440

Claim:
An apparatus, comprising: a finite impulse response (FIR) filter circuit configured to successively supply a plurality of symbols; a calculation circuit configured to provide a plurality of coefficients to the FIR filter circuit, the calculation circuit calculating the plurality of coefficients in accordance with a Constant Modulus Algorithm (CMA) and in response to first and second inputs to the calculation circuit, the first input including a first group of the plurality of symbols, and the second input being a plurality of sums; and an adder circuit configured to supply the plurality of sums to the calculation circuit, the adder circuit generating the plurality of sums by adding each kth symbol of a second group of the plurality of symbols to a product of each (k−1)th symbol times a number, where k is an integer greater than or equal to 2 and greater than or equal to n, and n is a number of symbols in the second group of the plurality of symbols.