Patent ID: 8569832

Claim:
A vertical transistor, comprising: a semiconductor substrate having a pillar-shaped active pattern over a surface thereof; a first tensile layer formed over the semiconductor substrate at a lower end portion of the pillar-shaped active pattern and a second tensile layer formed at an upper end portion of the pillar-shaped active pattern, the first and second tensile layers applying a tensile stress to the pillar-shaped active pattern in a vertical direction; a first junction region formed within the surface of the semiconductor substrate below the first tensile layer and the pillar-shaped active pattern; a gate surrounding at least a portion of the pillar-shaped active pattern; and a second junction region formed within the upper end portion of the pillar-shaped active pattern wherein the first tensile layer is formed only over the semiconductor substrate at a lower end portion of the pillar-shaped active pattern and the second tensile layer is formed only at an upper end portion of the pillar-shaped active pattern, the first and second tensile layers applying a tensile stress to a channel region of the pillar-shaped active pattern in a vertical direction.