Patent ID: 8866508

Claim:
A system for calibrating a chip in a 3D chip stack, the system comprising: a first and a second chip, each in said chip stack; said first chip comprising a receiver circuit, wherein said receiver circuit comprises: a first comparator circuit having a first input for receiving a VIH signal, a second input for receiving said VIH calibration signal, and an output for sending a VIH comparison signal; a second comparator circuit having a first input for receiving a VIL signal, a second input for receiving said VIL calibration signal, and an output for sending a VIL comparison signal; a duty generator counter having a first output for sending a VIH duty signal and a second output for sending a VIL duty signal; a third comparator circuit having a first input for receiving a first voltage signal representative of said VIH comparison signal, a second input for receiving a second voltage signal representative of said VIH duty signal, and an output for sending a VIH duty comparison signal; and a fourth comparator circuit having a first input for receiving a first voltage signal representative of said VIL comparison signal, a second input for receiving a second voltage signal representative of said VIL duty signal, and an output for sending a VIL duty comparison signal, wherein said second signal comprises said VIH and VIL duty comparison signals, and wherein said VIH and VIL duty comparison signals are input to said logic and driving control circuit; and said second chip comprising a transmission circuit having a first output operatively connected to a first input of said receiver circuit, and a second output operatively connected to a second input of said receiver circuit, and the inputs of said transmission circuit operatively connected to each of a first and a second output of said receiver circuit.