Patent ID: 8247280

Claim:
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first portion and a second portion; forming a first transistor of a first type in the first portion of the substrate, the first transistor being operable at a first voltage; forming a second transistor of a second type in the second portion of the substrate, the second type being opposite the first type, the second transistor being operable at a second voltage greater than the first voltage; wherein the forming the second transistor includes: forming an extended doped feature of the second transistor while simultaneously forming a doped channel region of the first transistor that is used to adjust a threshold voltage of the first transistor, wherein the extended dope feature and the channel region are of the second type; and forming a well of the first type in the semiconductor substrate under a gate of the second transistor, wherein the well does not extend directly under the extended doped feature and the extended doped feature does not extend directly under the well; and forming a third transistor of the second type in a third portion of the substrate, the third transistor being operable at the first voltage.