Patent ID: 7877713

Claim:
A method to produce an electrical model of an integrated circuit substrate comprising: providing multiple different tile definitions; wherein different tile definitions respectively specify multiple respective connection nodes in which at least one connection node is connectable to propagate noise between such connection node and a connection node of another tile instance and in which at least one connection node is connectable for use as at least one of a noise injection node or as a noise observation node and in which at least two respective connection nodes are electrically connected to propagate noise between them; wherein different tile definitions respectively correspond to different portions of the substrate having different physical characteristics; wherein different tile definitions respectively specify different electrical models for their different corresponding substrate portions having such different physical characteristics in terms of electrical behavior of noise propagation between the at least two respective connection nodes; and wherein different tile definitions respectively specify respective physical dimensions encompassed by the respective tile definitions; mapping, using a computer, respective tile instances specified by different tile definitions to respective portions of the substrate that correspond to such respective definitions; and connecting respective connection nodes of the mapped tile instances to each other to produce a tile grid to propagate noise between tile instances to model overall electrical behavior of the substrate; associating a voltage with a selected tile instance of the tile grid that is indicative of substrate noise injection to the selected tile instance.