Patent ID: 8462350

Claim:
A method for developing and evaluating semiconductor devices or wafers for manufacture by optically testing and displaying internal stresses of semiconductor devices or wafers and for testing semiconductor devices or wafers while being manufactured, the device or wafer under test being comprised a semiconductor conductor material having an interior surface and interior structures, comprising: using a holographic optical interference system with at least one light source, providing at least one light beam of coherent wavelength with a wavelength to which the semiconductor material is at least semi-transparent or transparent, splitting the light beam into a pair of beams, comprising a reference beam and an object beam, imposing the object beam on the exterior surface of the semiconductor material to generate a reflected object beam reflected from the interior structures of the semiconductor material and interior surfaces of the semiconductor material to generate a reflected beam reflected from the interior structures of the semiconductor material, adjusting the angle of incidence of the reference beam relative to the object beam between a plurality of angles with the semiconductor material being in a different state for each angle of the reference beam, imposing the reflected object beam and the reference beam onto one or more detection devices to create a plurality of interference patterns of the reflected object beam with the reflected reference beam, one interference pattern at each of the plurality of angles of the reference beam, varying the magnification of the reference beam relative to the magnification of the object beam, using one or more detection devices to physically record or digitally store the plurality of interference patterns, comparing the plurality of interference patterns to one another to determine and display stress or the effects of such stress and interior structure characteristics within the semiconductor material, device or wafer, and using the plurality of interference patterns to perform at least one of the following: (1) test, shape or determine semiconductor materials, devices, wafers or interior structures, (2) evaluate internal processes in semiconductor materials, devices or wafers, (3) test integrated circuits, devices or materials, (4) determine the effects of electromagnetic signals that act upon or within the semiconductor wafers, devices or processes, or (5) determine the effects of energies or signals acting upon or within the semiconductor materials, devices or wafers.