Patent ID: 8218770

Claim:
A server system for transmitting and receiving data packets corresponding to one or more streaming data sessions between one or more playback devices over at least one network connection, the server system comprising: a protocol accelerator adapted to, for received data packets corresponding to the one or more data sessions, (i) extract one or more header fields of the received data packets, (ii) perform a lookup, based on the extracted one or more header fields, to determine a destination for the received data packets, and (iii) provide the received data packets to the destination, and for data to be transmitted, (i) group the data to be transmitted into data packets, [ii) generate one or more header fields for the data packets, and (iii) provide the data packets to the at least one network connection; a control processor adapted to perform processing on (i) received data packets and (ii) data to be transmitted; a memory arbiter adapted to manage accesses to a shared memory, wherein the shared memory is adapted to (i) buffer received data packets and data to be transmitted, and (ii) store one or more keys corresponding to the one or more data sessions; a storage medium adapted to store media files corresponding to the one or more data sessions; a key manager comprising: (i) a first memory for storing at least one master key of the server, (ii) a second memory for storing one or more keys corresponding to the one or more data sessions, and (iii) an encryption/decryption processor adapted to encrypt and decrypt data packets, (iv) a direct memory access (DMA) processor, and (v) a bus arbiter adapted to exclusively couple a bus of the key manager to one of: (a.) the control processor, and (b) the DMA processor, wherein the DMA processor is adapted to (1) transfer the one or more keys between the encryption/decryption processor and the second memory and (2) provide a signal to the encryption/decryption processor when data is present for the encryption/decryption processor to decrypt, wherein file encryption/decryption processor is further adapted to: (i) responsive to the signal, perform the decryption, (ii) provide a signal to the bus arbiter, and (iii) provide, once the bus arbiter provides exclusive bus access to the encryption/decryption processor, decrypted data to the second memory.