Patent ID: 8410604

Claim:
A semiconductor device, comprising: a semiconductor die; a plurality of lead-free solder bumps disposed on a surface of the semiconductor die; a substrate including a plurality of metal layers and a plurality of dielectric layers, wherein one of the plurality of metal layers includes a plurality of contact pads corresponding to the plurality of lead-free solder bumps, and one of the plurality of dielectric layers is an exterior dielectric layer having a plurality of respective openings for the plurality of contact pads; a plurality of respective copper posts disposed on the plurality of contact pads, wherein the respective copper post for each contact pad extends from the contact pad through the respective opening for the contact pad; and wherein: the semiconductor die is mounted on the substrate with connections between the plurality of lead-free solder bumps and the plurality of copper posts; the surface of the semiconductor die has a respective silicon metal pad disposed at each of the plurality of lead-free solder bumps; each lead-free solder bump is reflow soldered to a first area of the respective silicon metal pad and to a second area of the respective copper post; and the first and second areas are equal in size and each size exceeds a cross-sectional area through an inner portion of the respective copper post, the inner portion between the contact pad and the second area.