Patent ID: 8664068

Claim:
A method of forming complementary transistors, the method comprising: providing a semiconductor device comprising a first gate electrode structure comprising a first spacer structure, and a second gate electrode structure comprising a second spacer structure; forming first and second drain and source extension regions in first and second active regions using said first and second gate electrode structures comprising said first and second spacer structures as implantation masks, respectively; forming first counter-doped regions in said first active region and second counter-doped regions in said second active region prior to forming said first and second deep drain and source regions; thereafter forming first deep drain and source regions by forming a first crystalline semiconductor material in first cavities located in said first active region laterally adjacent to said first gate electrode structure by performing a first epitaxial growth process, said first crystalline semiconductor material comprising a first drain and source dopant species; and forming second deep drain and source regions by forming a second crystalline semiconductor material in second cavities located in said second active region laterally adjacent to a second gate electrode structure by performing a second epitaxial growth process, said second crystalline semiconductor material comprising a second drain and source dopant species that differs from said first drain and source dopant species.