Patent ID: 8248849

Claim:
A semiconductor memory device comprising: a memory cell; a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells and a first selection gate transistor, at least two of the plurality of memory cells being connected in series; a word line formed by continuously extending control gates of the memory cells; a word line unit comprising a plurality of wirings which is formed of the same wiring layer as the word line, the plurality of wirings including a plurality of word lines connected to the plurality of memory cells included in one of the memory cell units; a first wiring included in the plurality of wirings and arranged on one end portion of the word line unit; and a first selection gate line formed by continuously extending gates of the first selection gate transistors, the first selection gate line being located adjacent to the first wiring; wherein a space between the first selection gate line and the first wiring is larger than a space between two wirings located adjacent to each other and included in the plurality of wirings.