Patent ID: 6998900

Claim:
A booster circuit including a plurality of capacitors, the booster circuit comprising: first to M-th power supply lines (M is an integer greater than three); first to (M−2)th boost capacitors, the j-th boost capacitor (1≦j≦M−2, j is an integer) being connected between the j-th power supply line and the (j+1)th power supply line in a first period, and connected between the (j+1)th power supply line and the (j+2)th power supply line in a second period which is subsequent to the first period; and first to (M−3)th stabilization capacitors, the k-th stabilization capacitor (1≦k≦M−3, k is an integer) being connected between the (k+1)th power supply line and the (k+2)th power supply line, and storing an electric charge discharged from the k-th boost capacitor in the second period, wherein a voltage obtained by multiplying a voltage between the first and second power supply lines (M−1) times is output between the first and M-th power supply lines.