Patent ID: 8164125

Claim:
A semiconductor device comprising: a substrate of a first conductivity type; a first well region of a second conductivity type disposed in the substrate; a second well region of the first conductivity type disposed in the substrate adjacent to the first well region; a first region of the second conductivity type disposed in the second well region, the first region being laterally separated by a channel region from a boundary where the first well region adjoins the second well region, the first region comprising a source of a MOSFET; a first conductive layer insulated from a first area of the substrate by a first dielectric layer, the first dielectric layer extending laterally over the channel region from the first region to at least just past the boundary over a first area of the first well region, the first conductive layer comprising a gate of the MOSFET and the first well region comprising a drift region of the MOSFET; a second conductive layer insulated from a second area of the first well region by a second dielectric layer, the first dielectric layer and the second dielectric layer being laterally separated at a surface of the substrate by a thick dielectric layer, the second conductive layer comprising a first capacitive plate, the second area of the first well region comprising a second capacitive plate, a third area of the first well region being disposed beneath the thick dielectric layer, the third area separating the first and second areas of the first well region; wherein the semiconductor device is programmed by application of a first voltage on the gate sufficient to turn on the MOSFET, and a second voltage on the first capacitive plate sufficient to destroy at least a portion of the second dielectric layer, thereby electrically connecting the source of the MOSFET to the first capacitive plate.