Patent ID: 7781264

Claim:
A fabrication method of a semiconductor package, comprising the steps of: preparing a lead frame having a plurality of leads, each of the leads being formed with an inner end directed toward the center of the lead frame; attaching a dam member to a predetermined position on each of the leads, so as to form a bonding area between the dam member and the inner end of the corresponding one of the leads, wherein the bonding area of each of the leads is formed with at least a recessed portion or a protruding portion; preparing at least a chip implanted with a plurality of solder bumps, and mounting the chip on the lead frame in a manner that the solder bumps are bonded to the bonding areas of the leads and completely cover the recessed portion or the protruded portion, so as to allow the chip to be electrically connected to the leads by the solder bumps; and forming an encapsulant for hermetically encapsulating the chip and the solder bumps, and encapsulating part of the leads.