Patent ID: 8688911

Claim:
A system on a chip (SOC) comprising: a processing core including a core bus agent; a bus interface unit (BIU); and a bridge module operatively coupling the processing core to the BIU, the bridge module comprising a first bridge unit and a second bridge unit, the first bridge unit including a first module and the second bridge unit including a second module, the second module including a multiplexer, the first module configured to (i) receive information from the core bus agent, and (ii) selectively route received information from the core bus agent to one or both of the multiplexer and a cache, the multiplexer having (i) a first input coupled to the first module, (ii) a second input coupled to the cache, and (iii) an output coupled to the BIU, the bridge module configured to: determine whether the cache is coupled to the bridge module, and based on determining whether the cache is coupled to the bridge module, selectively route information from the core bus agent to (i) the cache or (ii) to the BIU by bypassing the cache.