Patent ID: 7573939

Claim:
A memory device comprising one or more memory blocks, wherein each memory block includes multiple memory cells arranged in a matrix form, and multiple selection lines for selecting memory cell column extending in one direction of said matrix, each line corresponding to the memory cell column; wherein a domain of said multiple memory cells arranged in a matrix form has multiple divisional domains divided in said one direction of said matrix; wherein each of said multiple selection lines has multiple divisional selection lines divided corresponding to said multiple divisional domains; and wherein said memory block further includes switching mechanism for switching the divisional selection lines that are simultaneously activated in the associated divisional domains, further including: multiple bit lines; multiple word lines perpendicularly crossing said multiple bit lines; a reference data input line for receiving reference data, said reference data input line perpendicularly crossing said multiple bit lines or extending parallel along said multiple bit lines; an operation data output line for outputting operation data, said operation data output line perpendicularly crossing said multiple bit lines or extending parallel along said multiple bit lines; a cell selection line for receiving a cell selection signal, said cell selection line perpendicularly crossing said multiple word lines or extending parallel along said multiple bit lines; and multiple memory cells in said matrix array being connected with said bit lines, said word lines, said reference data input line, said operation data output line, and said cell selection line, wherein each said memory cell includes: a memory cell unit for storing data “1” or “0”; a reference data input unit for receiving reference data, said reference data input unit being connected with said reference data input line; an operation function unit for performing a logical operation using the data stored in said memory cell unit and reference data received from said reference data input unit; an operation data output unit for outputting operation data obtained in said operation function unit to said operation data output line, said operation data output unit being connected with said operation data output line; a cell selection signal input unit for receiving a cell selection signal and being connected with said cell selection line; and an output control unit for outputting to said operation data output unit said operation data based on said cell selection signal received by said cell selection signal input unit, wherein said multiple selection lines are said multiple cell selection lines; and wherein said one direction of said matrix is a direction along said cell selection line.