Patent ID: 7925217

Claim:
A receiving circuit comprising: a test signal generator to generate a test signal positioned in a guard frequency band; an IQ mixer to multiply an in-phase signal to a sum of the test signal and a received signal to output a first signal of an intermediate frequency or a base band and to multiply a quadrature signal to the sum of the test signal and the received signal to output a second signal of the intermediate frequency or the base band; a first filter and a second filter to respectively receive the first signal and the second signal; a first DAC and a second DAC to respectively receive outputs of the first filter and the second filter and to output a third signal and a fourth signal; an IQ mismatch detector to detect an IQ mismatch generated by the IQ mixer using the test signal included in the third signal and the fourth signal; and an IQ compensator to respectively input the third signal and the fourth signal and output a fifth signal and a sixth signal that compensate the third signal and the fourth signal for the IQ mismatch according to a result obtained by the IQ mismatch detector and transmitted to the IQ compensator.