Patent ID: 7120287

Claim:
An assembly method for a plurality of integrated circuit devices and a plurality of mounting substrates comprising: providing a plurality of integrated circuit devices in multiple lots for assembling in a manufacturing process, each lot of the multiple lots having a plurality of integrated circuit devices therein; mounting each integrated circuit device of the plurality of integrated circuit devices to a mounting substrate of the plurality of mounting substrates; placing a substantially unique identification code on each mounting substrate of the plurality of mounting substrates in a readable position thereon; placing an identification code on each integrated circuit device of the plurality of integrated circuit devices; correlating the identification code of each integrated circuit device mounted on the mounting substrate with the substantially unique identification code of the mounting substrate; reading the substantially unique identification code of the mounting substrate of each integrated circuit device of the plurality of integrated circuit devices in each lot of the multiple lots; performing a series of assembly steps in the manufacturing process on the plurality of integrated circuit devices in the multiple lots, the series of assembly steps including: generating data related to the series of assembly steps of each integrated circuit device of the plurality of integrated circuit devices through the series of assembly steps; associating the data generated for each integrated circuit device of the plurality of integrated circuit devices with the substantially unique identification code of an associated mounting substrate of the plurality of mounting substrates for tracking the multiple lots of the plurality of integrated circuit devices; and at least one assembly step including one of die attach, die cure, wire bond, molding, deflash, lead finish, trim and form, and opens/shorts testing.