Patent ID: 8022398

Claim:
A thin film transistor (TFT), comprising: a buffer layer and a semiconductor layer which are sequentially disposed on a substrate; a gate pattern including an insulating pattern and a gate electrode pattern which are sequentially disposed on the semiconductor layer; source and drain regions defining a portion of the semiconductor layer below the gate pattern as a channel area, formed by doping the semiconductor layer disposed at both sides of the gate pattern with impurities, and extending from both sides of the channel area; a passivation layer which covers the entire surface of the substrate having the gate pattern; a first metal electrode which penetrates a portion of the passivation layer disposed on the source area and a portion of the source region below the portion of the passivation layer to contact an exposed portion of the buffer layer and be electrically connected with the source region; and a second metal electrode which penetrates a portion of the passivation layer disposed on the drain area and a portion of the drain region below the portion of the passivation layer to contact an exposed portion of the buffer layer and be electrically connected with the drain region.