Patent ID: 8907463

Claim:
A method comprising: forming a plurality of semiconductor chips, each of the semiconductor chips comprising: a first surface and a second surface opposite to the first surface; a plurality of first terminals arranged apart from each other in substantially parallel to the first surface, the first terminals being provided on a side of the first surface; a plurality of first conductive lines each extending vertically with respect to the first surface, each of the first conductive lines being vertically aligned with a corresponding one of the first terminals and electrically isolated from the corresponding one of the first terminals; and a plurality of second conductive lines, each of the second conductive lines extending in substantially parallel to the first surface to electrically connect an associated one of the first conductive lines to a different one of the first terminals that is not vertically aligned with the associated one of the first conductive lines; and stacking the semiconductor chips with each other such that the first conductive lines of a lower one of the semiconductor chips are electrically connected to the first terminals of an upper one of the semiconductor chips, respectively, and that each of the first terminals of the lowermost one of the semiconductor chips and an associated one of the first conductive lines of the uppermost one of the semiconductor chips, that are vertically aligned with each other, are electrically connected through the second conductive lines.