Patent ID: 8037434

Claim:
A method comprising: providing a plurality of parameter options, the plurality of parameter options corresponding to a plurality of components for implementation on a programmable device, the plurality of components including a processor; receiving a plurality of parameter selections, the plurality of parameter selections corresponding to the plurality of components for implementation on the programmable device; and generating a logic description using the plurality of parameter selections by using a system processor to implement a plurality of parameterized components including a parameterized processor on the programmable device, wherein the logic description includes dynamically generated interconnection logic interconnecting the plurality of parameterized components and coupling the plurality of parameterized components to off-chip components and other modules implemented on the programmable device, wherein the plurality of parameterized components has a plurality of different bus widths, and wherein the dynamically generated interconnection logic is operable to modify the plurality of different bus widths such that the plurality of parameterized components operates in a single bus width environment.