Patent ID: 8618600

Claim:
An integrated circuit comprising: a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate; a gate wiring line buried below the main surface, wherein a section of the gate wiring line forms the gate electrode; a buried contact element in direct contact with the gate wiring line, wherein a top of the buried contact element is substantially flush with or recessed below the main surface; and a second active area formed in the semiconductor substrate adjacent to and in direct contact with the buried contact element; wherein the gate electrode is buried between a first and a second source/drain region of the field effect transistor that are formed within the first active area and adjacent to the main surface; wherein the second active area comprises a further first and a further second source/drain region of a second field effect transistor; and wherein the buried contact element is formed adjacent to and in direct contact with one of the further first or second source/drain regions.