Patent ID: 7930459

Claim:
An apparatus, comprising: a coherent system interconnect; an input output interface; a coherent input output device coupled between the coherent system interconnect and the input output interface, wherein the coherent input output device is to exchange data between the input output interface and the coherent system interconnect; a control status register region within the coherent input output device, wherein the control status register region is coupled to both (1) an external coherent path to the coherent system interconnect and (2) an internal non-coherent path and further wherein the control status region registers are accessible via a memory mapped aperture of cacheable memory and other input output resources are directly accessible by a processor via writeback memory apertures, and a first memory aperture is associated with a read/write attribute, a second memory aperture is associated with a write only attribute, and a third memory aperture is associated with a read only attribute; and a plurality of coherent input output buffers within the coherent input output device, wherein each of the coherent input output buffers are coupled to both (1) an external coherent path to the coherent system interconnect and (2) an internal non-coherent path and further wherein each of the plurality of coherent input output buffers are mapped to a system memory address map, and the processor uses a push input output model such that the processor directly pushes data onto the coherent input output device; wherein updates that occur via the internal non-coherent paths do not happen coherently, and the coherent input output device ensures that the state of a cacheline is compliant with a cache coherency protocol.