Patent ID: 7844843

Claim:
A power saving clock-gating circuit for implementing power savings in High Speed Serializer-deserializer (HSS) cores including output C 2 clocks, said power saving clock-gating circuit comprising: a clock gate signal used to initiate the starting and stopping of the output C 2 clocks; a clock gate aligner block receiving said clock gate signal; said clock gate aligner block including a plurality of latches, said clock gate aligner block providing a clock gate aligned signal; a C 2 clock generator receiving said clock gate aligned signal to synchronously start the output C 2 clocks; and a power savings logic circuit receiving said clock gate signal and said clock gate aligned signal, a power savings logic circuit generating a power down signal, and said power down signal being applied to said clock gate aligner block to turn off said plurality of current-mode latches after the C 2 clocks have been started, and responsive to a changed state of the clock gate signal to turn on said plurality of current-mode logic latches to begin another synchronous start operation.