Patent ID: 7188268

Claim:
A data register apparatus that can be loaded synchronously and unloaded out-of-phase, the apparatus comprising: a first data register comprising a data input coupled to a data signal, a clock input coupled to a clock signal, an enable input coupled to a periodic first load signal, and a data output; a second data register comprising a data input coupled to the data output of the first data register, a clock input coupled to the clock signal, an enable input coupled to a second load signal, and a data output; and a controller having a clock input coupled to the clock signal, a load data input coupled to the first load signal, and a read data input coupled to a periodic read signal, the controller having a capability for generating a first guard band signal in response to the first load signal and the clock signal and a second guard band signal in response to the read signal and the clock signal, the controller further having a capability for generating the second load signal in response to the first and second guard band signals.