Patent ID: 8427203

Claim:
Reconfigurable computing logic, comprising: a decoder having at least one input and at least two outputs; at least one power/reconfigure block; wherein said power/reconfigure block comprises: a power node being connected to a first terminal of a first resistance; a second terminal of said first resistance being connected to the drain of a first p-channel field effect transistor; a gate of said first p-channel field effect transistor being connected to a gate of a first n-channel field effect transistor and a signal node; a drain of said first n-channel field effect transistor being connected to ground; a source of said first n-channel field effect transistor being connected to a source of said first p-channel field effect transistor and to a first common node; a second p-channel field effect transistor having a drain connected to ground, a gate connected to said signal node, and a source connected to a second common node; a second n-channel field effect transistor having a drain connected to a threshold node, a gate connected to said signal node, and a source connected to said second common node; at least two programmable resistance blocks; and at least one logic output block; wherein a signal applied to said at least one input of said decoder is decoded and applied as an input to any of said at least two programmable resistance blocks according to a decoding scheme; a signal output from any of said at least two programmable resistance blocks in response to said applied signal into any of said at least two programmable resistance blocks, is input into said at least one output block; said at least one logic block corrects the voltage and logic state of said reconfigurable computing logic output; and wherein said at least one power/reconfigure block powers said reconfigurable computing logic; and selectively directs a voltage and current to reprogram any of said at least two programmable resistance blocks.