Patent ID: 6854096

Claim:
A computer-implemented method for facilitating physical synthesis of a circuit design, the circuit design comprising a plurality cell instances organized hierarchically, each cell instance corresponding schematically to one of a plurality of cell types, the method comprising: sizing transistors in each of the cell instances with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type, each cell subtype corresponding to a particular cell type differing from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension; and merging selected ones of the subtypes for at least one of the cell types thereby resulting in a second plurality of subtypes for the at least one of the cell types, the second plurality of subtypes being fewer than the first plurality of subtypes, wherein merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.