Patent ID: 8275977

Claim:
A system comprising: a first processor; a second processor; a first clock coupled to the first processor; a second clock coupled to the second processor; and a third clock coupled to the first processor and to the second processor, wherein the third clock is asynchronous with respect to the first clock, wherein the first processor comprises: debug circuitry coupled to receive the third clock; synchronization circuitry coupled to receive the first clock, the synchronization circuitry receiving a first request to enter a debug mode which is synchronous with respect to the third clock and providing a first synced debug entry request signal, wherein the first synced debug entry request signal is synchronized with respect to the first clock; and an input for receiving a second synced debug entry request signal from the second processor, wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted.