Patent ID: 8154932

Claim:
A computer system comprising: a central processing unit coupled to and configured to communicate with a memory controller by at least an address bus and a data bus, wherein the memory controller is further coupled to memory devices, the central processing unit operative to: output a memory address for a write access, output data for said write access, and the memory controller configured to receive the memory address and output data from the central processing unit and comprising a register for introducing a delay between the memory address and output data; a multi-bank memory device operative to remove said delay between said memory address and said data for said write access after receipt of said memory address and said data from said computer circuit, said memory device comprising first and second sets of registers pipelined to respectively receive said memory address and said data, said first set of registers pipelined to delay said address of said write access, and said second set of registers pipelined to delay said data of said write access, said second set of registers fewer in number than said first set of registers and an address translator capable of receiving addresses transmitted by the central processing unit and determining row and column portions of the transmitted addresses; said address bus operative to transfer said memory address from said central processing unit to said memory device; and said data bus operative to transfer said data from said central processing unit to said memory device and further comprising a comparator for comparing said address of said read access with said pipelined address of said write address to determine if there is a match and in response to determining a match, providing said pipelined data of said write access as data for said read access.