Patent ID: 7569879

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of semiconductor columns arranged in a matrix form on the semiconductor substrate; a plurality of first conductive areas which are formed in a stripe form in a column direction on the semiconductor substrate between the plurality of semiconductor columns and which function as word lines; a plurality of second conductive areas formed at tops of the plurality of semiconductor columns, respectively; a plurality of bit lines connecting the plurality of second conductive areas in a row direction; a plurality of channel areas which are respectively formed in the plurality of semiconductor columns between the first conductive areas and the second conductive areas and which contact the first conductive areas and the second conductive areas; a plurality of third conductive areas which are continuously formed via first insulating films above the semiconductor substrate and opposite to the plurality of channel areas in the column direction between the plurality of semiconductor columns and which function as control gates; and a plurality of charge accumulation areas respectively formed via second insulating films at an upper portion of the plurality of channel areas at a position higher than the plurality of third conductive areas; wherein the plurality of charge accumulation areas comprise fourth conductive areas formed to be enclosed by insulators within the plurality of channel areas.