Patent ID: 8493801

Claim:
A memory system comprising: a bidirectional data strobe; one or more memory chips coupled to the bidirectional data strobe; a host coupled to the bidirectional data strobe, the host further comprising: a receiver to receive signals from the bidirectional data strobe; a circuit to pass an output from the receiver to circuitry on the host only when the circuit is enabled by a receiver enable; a training control to, during a training period, transmit commands to the one or more memory chips and to determine a correct timing of the receiver enable, the training control further configured to ensure that the bidirectional data strobe has a particular voltage value during the training period; wherein the host is configured to send a first command to a memory chip, the memory chip, in response, configured to drive the data strobe to the particular value during the training period; and wherein the host is configured to send a first read command, subsequent to the first command, to the memory chip during the training period to cause the memory chip to transmit a normal toggle responsive to the read command.