Patent ID: 7383311

Claim:
A hardware device for concurrently processing a plurality of tasks associated with an algorithm which includes a number of processes some of which are dependant on binary decisions, said device comprising: a plurality of task units for processing data, making decisions and/or processing data and making decisions, including at least one source task unit and at least one destination task unit; a task interconnection logic means interconnecting the plurality of task units for communicating actions from the at least one source task unit to the at least one destination task unit; and each of said task units including: a processor for executing the steps of the associated task in response to a received request action; and a status manager for handling actions from the at least one source task units and building actions to be sent to the at least one destination task units, wherein each task unit of the plurality of task units is configured to perform only one task of the plurality of tasks associated with the algorithm.