Patent ID: 7061805

Claim:
A operating method of a p-type channel NAND flash memory, applicable for a memory cell array of a plurality of memory cell arrays, wherein the memory cells in each of the memory cell rows are connected in series between a p-type source region and a p-type drain region; each of the memory cells comprises a tunneling dielectric layer, a floating gate, and a control gate, while an erase gate is disposed between each of the two adjacent memory cells, and a p-type doping region is disposed under the erase gate, a select transistor is disposed between the p-type drain region and the memory cell nearest to the p-type drain region; a plurality of word lines are arranged in parallel as columns, and connected respectively to the control gates of the memory cells of each column; a plurality of source lines are connected respectively to the p-type source regions of each column; a plurality of bit lines are arranged in parallel as rows, and connected respectively to the p-type drain regions of each row; a plurality of select gate lines are connected respectively to the select transistors of each column; a plurality or erase gate lines are arranged in parallel as columns, and connected respectively to the erase gates of each column, the operating method comprising: during a programming operation, applying a first voltage to a selected bit line; applying a second voltage to the select gate line; applying a third voltage to a selected word line; and applying a forth voltage to unselected word lines, so as to program a selected memory cell via band-to-band tunneling induced hot electron injection.