Patent ID: 7356783

Claim:
A machine implemented method for minimizing an impact of process variation in an electronic circuit design of an integrated circuit, comprising: based on electrical impact analysis and a pattern dependent model of a semiconductor fabrication process, generating a dummy fill strategy for placement and sizing of dummy fill in the integrated circuit, in which the dummy fill strategy adds or removes a structure to the electronic circuit design of the integrated circuit; calibrating the pattern dependent model based upon an information from a patterned test wafer or a test semiconductor device; using the pattern dependent model and the electrical impact analysis to evaluate expected results of the placement and sizing of dummy fill in the integrated circuit, wherein the fabrication process for which the strategy is being generated comprising a polishing or planarization process in which more than one material is removed; and displaying a result of the using the pattern dependent model and the electrical impact analysis to evaluate expected results of dummy fill or storing the result in a tangible machine accessible medium.