Patent ID: 7271758

Claim:
A successive approximation register (SAR) analog-to-digital Converter (ADC) with variable gain having a SAR capacitor array with a plurality of switched capacitors therein with varying weights and a SAR controller for sampling an input voltage thereon in a sampling phase, and redistributing the charge stored thereon in a conversion phase in accordance with a SAR conversion algorithm, comprising: a gain adjust register for defining an amount of charge that, in a first gain change mode, is to be added to the capacitor array prior to the conversion phase relative to a predetermined amount of charge representing substantially unity gain and, in a second gain change mode, is to be subtracted from the capacitor array prior to the conversion phase relative to the predetermined amount of charge representing substantially unit gain; and a charge control device for varying the amount of charge stored in the array prior to the conversion phase in accordance with the contents of said gain adjust register such that the amount of charge redistributed during the conversion phase is adjusted.