Patent ID: 7656479

Claim:
A pixel structure disposed on a substrate, comprising: a gate disposed on the substrate; a patterned dielectric layer disposed on the substrate to cover the gate; a patterned semiconductor layer disposed on the patterned dielectric layer, the patterned semiconductor layer including a plurality of bumps and a channel disposed above the gate, wherein the gate is formed by patterning a gate material layer on the substrate, the gate material layer exposes a region of the substrate after being patterned, and the bumps are located in the region exposed by the patterned gate material layer; a patterned metal layer including a source, a drain and a reflective pixel electrode connected to the drain, wherein the source and the drain cover at least a portion of the channel, respectively, the reflective pixel electrode covers and contacts with the bumps, and wherein the gate, the patterned dielectric layer, the patterned semiconductor layer, the source and the drain together form a transistor; an overcoat layer disposed on the transistor, wherein the overcoat layer has a contact hole to expose a portion of the reflective pixel electrode; and a transparent pixel electrode disposed on the overcoat layer, the transparent pixel electrode electrically connecting the reflective pixel electrode through the contact hole.