Patent ID: 6917547

Claim:
A non-volatile memory comprising: a plurality of nonvolatile memory cells; and an error correcting circuit, wherein a program command accompanied with address information and first data are received from outside, wherein, in a program operation executed in response to said program command, first nonvolatile memory cells of said plurality of nonvolatile memory cells are selected in accordance with said address information and programmed with said first data, wherein, after said first nonvolatile memory cells are programmed with said first data in said program operation, second nonvolatile memory cells of said plurality of nonvolatile memory cells are selected and second data stored therein are read out, wherein said error correcting circuit judges whether said second data includes one or more errors and corrects said second data to create third data when said second data includes one or more errors, and wherein said second nonvolatile memory cells are programmed with said third data after said second data is corrected by said error correcting circuit.