Patent ID: 7028123

Claim:
A microcomputer comprising: a plurality of peripheral inputs and outputs (I/Os) that generate interrupt request signals; an interrupt controller that controls selection of the interrupt request signals from the peripheral I/Os; a central processing unit that performs interrupt processing by using one of the interrupt request signals selected by the interrupt controller; an interrupt request signal generator that generates a testing-purpose interrupt request signal whose generation timing is adjustable; an interrupt request selecting register that stores an interrupt request selection signal, for making an interrupt request during testing effective; and a plurality of selection circuits each of which selects either one of the interrupt request signals from the peripheral I/Os or the testing-purpose interrupt request signal from the interrupt request signal generator, based on the interrupt request selection signal from the interrupt request selecting register, wherein the testing-purpose interrupt request signals output from the selection circuits can be input to the interrupt controller, wherein the interrupt request signal generator adjusts the generation timing of the testing-purpose interrupt request signal by software.