Patent ID: 8581770

Claim:
A switched-capacitor circuit comprising: (a) a first stage receiving first and second input signals and including first, second, third, and fourth input capacitors and also including a first arrangement of switches configured, during a first phase, to couple i) the first input signal to a bottom plate of the first input capacitor and a top plate of the fourth input capacitor, ii) the second input signal to a bottom plate of the second input capacitor and a top plate of the third input capacitor, and iii) top plates of the first and second input capacitors to a first reference voltage, iv) bottom plates of the third and fourth input capacitors to the first supply voltage, the first and second input signals thereby being sampled during the first phase; (b) a second stage having first and second summing conductors coupled to the first stage for processing a first summing conductor signal and a second summing conductor signal to produce first and second output signals; (c) the first stage also including a second arrangement of switches configured, during a second phase, to couple: i) the bottom plates of the first and second input capacitors to a second reference voltage, ii) the top plate of the first input capacitor to the top plate of the third input capacitor and iii) the top plate of the second input capacitor to the top plate of the fourth input capacitor to: cancel at least a portion of a common mode component associated with the first and second input signals from the first and second summing conductor signals and establish a predetermined common mode voltage on the first and second summing conductors so as to keep the first and second summing conductor signals within a predetermined safe operating range as charge associated with the first input signal is transferred from the first and third input capacitors to the first summing conductor and charge associated with the second input signal is transferred from the fourth and second input capacitors to the second summing conductor.