Patent ID: 8209559

Claim:
A method comprising: indicating, in a first polling system for use by a first processor core, events that unhalt thread execution by the first processor core, the first processor core being one of a plurality of processor cores comprised in a processor, a second polling system being provided for use by a second processor core comprised in the plurality of processor cores, the second polling system being a replication of the first polling system; identifying by the first polling system any of the indicated events, wherein the identifying takes place while the thread is in a halt state and independent of execution of a routine by the first processor core to monitor for the events; and unhalting by the first polling system the thread execution by the first processor core in response to the identification of any of the indicated events; the first processor core, the first polling system, and a cache associated with the first processor core being comprised in a processor, the first processor core and the associated cache to be in a relatively lower power state while the thread is in the halt state, the relatively lower power state being relative to a fully powered on state; the first polling system to execute an instruction that results in the first polling system monitoring a non-cache register in the first polling system to determine whether any of the events that unhalt thread execution by the first processor core have actually occurred, the non-cache register to remain fully powered on when the first processor core and the associated cache are in the relatively lower power state.