Patent ID: 8429507

Claim:
A device comprising: an output configured to output encoded words, wherein each consecutive pair of the encoded words comprises a first encoded word and a second encoded word, for each of the consecutive pairs of the encoded words, the first encoded word has a predetermined number of bits with different values than bits in the second encoded word, each of the encoded words has an identifier, the identifiers of the encoded words are (i) binary numbers, and (ii) Gray code encoded, and each of the binary numbers is represented as {d 1 , d 2 , . . . d n−1 , d n }; and a processing circuit configured to (i) process the encoded words to enable a correction of at least one bit error in the encoded words, (ii) encode the identifiers with a cyclic code, and (iii) derive the cyclic code by listing cyclic code words of a predetermined weight in a matrix G′, wherein the matrix G′ includes A rows and n columns, where A is a number of the cyclic code words with the predetermined weight, and n is an integer.