Patent ID: 8269207

Claim:
A memory device comprising: a substrate; a memory cell array formed above the substrate to include first wiring lines and second wiring lines crossing each other, and memory cells disposed between the first wiring lines and the second wiring lines at crossing points thereof, each said memory cell having a stacked structure of a variable resistance element and a diode; and a sense amplifier formed on the substrate, wherein the sense amplifier comprises: a first current detecting circuit for comparing a current flowing in a selected first wiring line with a reference current when a positive logic pulse and a negative logic pulse are applied to the selected first wiring line and a selected second wiring line, respectively, to forward-bias the diode in a selected memory cell; and a second current detecting circuit for comparing a current flowing in a selected second wiring line with a reference current when a positive logic pulse and a negative logic pulse are applied to a selected first wiring line and the selected second wiring line, respectively, to forward-bias the diode in a selected memory cell.