Patent ID: 7327186

Claim:
A circuit for generating a voltage reference, comprising: a first stage comprising; a first resistor operatively coupled to a supply voltage Vcc, and a first transistor operatively coupled to the first resistor and to ground; a second stage comprising; an operational amplifier, a positive input terminal of which receives a first voltage V 1 from the first stage, a second transistor driven by the operational amplifier, a second resistor, a first end of which is operatively coupled to the second transistor and back to a negative input terminal of the operational amplifier, and a second end of which is coupled to ground, and a third transistor operatively coupled to the second transistor and to the supply voltage, where a second voltage V 2 is developed at the first end of the second resistor; and a third stage comprising; a fourth transistor operatively coupled to the third transistor of the second stage so as to establish a current mirror arrangement such that a third current I 3 developed in the third stage is a function of a second current I 2 developed in the second stage, and a fifth transistor operatively coupled to the fourth transistor and to ground, which outputs one or more voltage reference values that are a function of the third current I 3 , the current mirror arrangement comprising a cascode current mirror arrangement to further mitigate sensitivity to fluctuations in the supply voltage, the cascode current mirror arrangement comprising; a sixth transistor operatively coupled to the third transistor, and a seventh transistor operatively coupled to the fourth transistor as well as the sixth transistor; and a second current mirror arrangement for providing a bias current Ib to the operational amplifier.