Patent ID: 7611964

Claim:
A method of fabricating a semiconductor memory device, the method comprising: forming a tunnel insulating layer and a charge trap layer over a semiconductor substrate; forming an isolation trench by etching the charge trap layer, the tunnel insulating layer, and the semiconductor substrate; forming a passivation layer over the charge trap layer and within the isolation trench, the passivation layer coating the isolation trench; forming a first insulating layer at a bottom portion of the isolation trench, the first insulating layer exposing an portion of the passivation layer, the exposed portion of the passivation layer having been oxidized during the formation of the first insulation layer; etching the exposed portion of the passivation layer to reduce a thickness of the exposed portion of the passivation layer; and forming a second insulating layer at least within the isolation trench and over the first insulation layer to form an isolation structure including the first and second insulation layers.