Patent ID: 8195888

Claim:
A multiprocessor system comprising: a first processor core; a second processor core; a first prefetcher associated with the first processor core; a second prefetcher associated with the second processor core; an off-chip memory interface supporting prefetch operations associated with the first prefetcher and the second prefetcher; and a prefetch bandwidth allocator configured to partition a prefetch bandwidth reserved for prefetching operations via the off-chip memory interface into a first prefetch bandwidth partition associated with the first prefetcher and a second prefetch bandwidth partition associated with the second prefetcher, maintain prefetch efficacy scores associated with each respective processor core, wherein the prefetch efficacy scores indicate an effectiveness of prefetching with each respective processor core, and re-partition the prefetch bandwidth associated with the off-chip memory interface into a third prefetch bandwidth partition associated with the first prefetcher and a fourth prefetch bandwidth partition associated with the second prefetcher, wherein the third prefetch bandwidth artition and the fourth refetch bandwidth partition are in proportion with the prefetch efficacy scores.