Patent ID: 7427900

Claim:
A charge pumped phase locked loop circuit, comprising: a phase detector for detecting the phase error between a reference clock and an output clock to generate a phase error signal; a charge pump controlled by said phase error signal to either source current to an intermediate control node or to sink current therefrom; an isolation circuit to maintain said intermediate control node at a virtual AC reference voltage such that it remains at substantially the same voltage during the sourcing of current thereto or sinking of current therefrom, said isolation circuit generating a control voltage on the output thereof to control the frequency of said output clock; and a loop filter integral with said isolation circuit for filtering said control voltage, said isolation circuit with said integral loop filter including a first stage including an operational amplifier responsive to either the source current or the sinked current from said charge pump and a second stage in series therewith including an operational amplifier responsive to the other of the source current or the sinked current from said charge pump, and said loop filter having an impedance of R + 1 sC where s=jω, said loop filter including a capacitor “C 1 ” associated with said first stage and a capacitor multiplier formed by said second stage having a multiplication factor of β to multiply the capacitance of capacitor “C 1 ” thereby to provide a relationship for impedance of R + 1 s ⁢ ⁢ β ⁢ ⁢ C 1 such that a smaller physical capacitor can be utilized in said loop filter as a function of β.