Patent ID: 7826582

Claim:
A phase smoothing system, comprising: a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock, wherein said NCO is configured to receive said input clock and provide an accumulated value at an edge of said input clock and to continually sum said accumulated value with a frequency control input; a phase error calculation module coupled to said NCO configured to generate a phase error for each of said NCO clock pulses, wherein said phase error calculation module is configured to determine a phase error of each of said NCO clock pulses based on fractional bits of said accumulated value normalized by said frequency control input; and a clock phase selectable delay module coupled to said phase error calculation module and comprising: a delay-locked loop (DLL) configured to receive said input clock and lock said input clock to a number L of equal phases; a voltage controlled delay line (VCDL) configured to receive said NCO clock pulses and comprising a delay line comprising said number L of delay elements and said number L of tap points corresponding to said L equal phases, wherein each of said NCO clock pulses is adjusted by: i) selecting one of said tap points based on said phase error and an input to determine a respective phase delay, wherein said input comprises fractional bits of said accumulated value normalized by a frequency control input and scaled by said number L and wherein said input is changed only when each of said delay elements is at a same value, and ii) applying said respective phase delay to said NCO clock pulse, to generate an output clock at said selectable frequency; a multiplexer coupled to said phase error calculation module and configured to receive said input that is used to select said tap point based on said phase error.