Patent ID: 7826249

Claim:
A programmable resistance memory device comprising: a semiconductor substrate; at least one cell array, formed above the semiconductor substrate, which comprises a plurality of bit lines arranged in parallel with each other, a plurality of word lines arranged in parallel with each other in such a direction as crossing said bit lines, and memory cells connected between the bit lines and the word lines at cross points of the bit lines and word lines, each said memory cell comprising a programmable resistance element which stores a high resistance state or a low resistance state in a non-volatile manner; and a read/write circuit formed on the semiconductor substrate as underlying said cell array and connected to the bit lines and word lines through vertical wirings for data reading and data writing in communication with said cell array, said read/write circuit comprising a first select gate circuit for selecting one of said vertical wirings to apply a drive voltage to a selected bit line or a selected word line connected to a selected memory cell via the selected vertical wiring for data reading and writing, and a second select gate circuit for selecting non-selected vertical wirings to apply a hold voltage to non-selected bit lines or non-selected word lines via non-selected vertical wirings, said first select gate circuit being arranged on one side of a boundary which is formed by read/write circuit side contact ends of the vertical wirings, and said second select gate circuit being arranged on the other side of the boundary.