Patent ID: 7285456

Claim:
A method of fabricating a fin field effect transistor, comprising: forming a first hard mask pattern on a semiconductor substrate; forming an active region pattern by partially etching the semiconductor substrate using the first hard mask pattern as an etching mask layer; forming a second hard mask pattern by removing an outer edge portion of the first hard mask pattern to expose a top surface portion of the active region pattern; forming a first insulating layer on the second hard mask pattern and the active region pattern; planarizing the first insulating layer to expose a top surface portion of the second hard mask pattern; forming a dummy gate layer on the second hard mask pattern and the first insulating layer; forming a dummy gate pattern by partially removing the dummy gate layer, the first insulating layer, and the second hard mask pattern to partially expose a top surface portion of the active region pattern; forming a second insulating layer on the dummy gate pattern and the active region pattern; planarizing the second insulating layer to expose a top surface portion of the dummy gate pattern; removing the dummy gate pattern and the second hard mask pattern to partially expose a top surface portion of the active region pattern; forming a trench region in the active region pattern by partially etching the exposed portion of the active region pattern; partially etching the first insulating layer to form a plurality of vertically protruding channel structures in the active region pattern, at least one vertically protruding channel structure being on a front and a rear side of the trench region; forming a gate dielectric layer on the active region pattern having the plurality of protruding channels; and forming a gate electrode on the gate dielectric layer.