Patent ID: 6891228

Claim:
A method of fabricating a CMOS device, said method comprising: depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein said SOI wafer has a predetermined thickness; forming a gate dielectric over said SOI wafer; forming a shallow trench isolation (STI) region over said BOX substrate, wherein said STI region is configured to have a generally rounded corner; forming a gate structure over said gate dielectric; depositing an implant layer over said SOI wafer; performing one of N-type and P-type dopant implantations in said SOI wafer and said implant layer; and heating said device to form source and drain regions from said implant layer and said SOI wafer, wherein said source and drain regions have a thickness greater than said predetermined thickness of said SOI wafer, wherein said gate dielectric is positioned lower than said STI region.