Patent ID: 7729166

Claim:
A multiple-bit per cell (MBC) non-volatile memory apparatus comprising: a memory array including an electrically erasable block; the block including a reprogrammable page; the reprogrammable page comprising an upper and a lower page sharing a common word-line; the upper and lower pages including respective upper and lower data fields; the upper and lower data fields including respective virtual upper and lower cells of MBC memory cells; the MBC memory cells having respective threshold voltages programmable to a selected one of first level, second level, third level, or fourth level in order from the lowest voltage level, wherein programming the lower cells comprises programming the respective threshold voltages from the first threshold voltage level to the second threshold voltage level, and programming upper cells comprises programming the respective threshold voltages from the first threshold voltage level to the fourth threshold voltage level or from the second threshold voltage level to the third threshold voltage level; and a controller for writing data to the memory array, wherein the controller controls polarity by selectively inverting a data word to maximize a number of bits within a lower page to be programmed and selectively inverting a data to minimize a number of bits to be programmed in the respective upper page.