Patent ID: 7058557

Claim:
A method for functional verification of hardware design, comprising the steps of: providing a first memory region storing a test pattern; providing a second memory region storing interrupt instructions; accessing the first memory and hardware-simulating the test pattern stored in the first memory region; accessing the second memory region and hardware-simulating the interrupt instructions if an external interrupt is received during the hardware-simulation of the test pattern; self-testing the simulated result of the interrupt instructions to obtain a first verification result; verifying the hardware design according to the first verification result; reaccessing the first memory region and continuing to hardware simulate the test pattern if the hardware design is verified according to the first verification result; acquiring a first simulation result of the test pattern if the hardware-simulation of the test pattern is finished; software-simulating the test pattern stored in the first memory region by a software simulator to acquire a second simulation result; and verifying the hardware design according to the first simulation result and the second simulation result.