Patent ID: 7863616

Claim:
A TFT array structure, comprising: a substrate, divided into a gate line wiring area and a gate area; a stacked structure, disposed on the gate area and the gate line wiring area of the substrate, wherein the stacked structure comprises a gate electrode layer, a gate insulating layer and a silicon layer; a passivation layer, covering the substrate and exposing the stacked structure of the gate line wiring area, wherein the passivation layer disposed on the stacked structure of the gate area further has at least two contact holes for exposing the silicon layer; an ion implanting layer, covering the passivation layer and the stacked structure corresponding to the gate area, and covering the stacked structure of the gate line wiring area, wherein the ion implanting layer is further connected to the silicon layer; a metal layer, covering the ion implanting layer, wherein the metal layer disposed in the gate line wiring area serves as a second layer of the gate line wiring area, and the metal layer disposed in the gate area is respectively serves as a source and a drain; and a pixel electrode layer, covering the passivation layer and connected to the metal layer serving as the drain and the ion implanting layer, wherein the ion implanting layer and the metal layer are disposed on the gate line wiring area covering the stacked structure, and the ion implanting layer and the metal layer are electrically connected to the gate electrode layer of the stacked structure through side walls of the gate electrode layer.