Patent ID: 8675419

Claim:
A device comprising a plurality of memory cores formed on a single semiconductor chip, each of the memory cores comprising: a plurality of memory banks, each of the memory banks comprising: an address circuit configured to fetch and temporarily retain address information supplied thereto, a memory array, an access circuit coupled to the memory array and responding to the address information to perform a selected one of a data read operation and a data write operation on the memory array, and a first latch circuit coupled to the memory array to temporarily store in the data read operation read data that are read out from the memory array and in the write operation write data that are to be written into the memory array; a command and address unit receiving an access request that includes a command designating one of the data read and write operations, the access request further including an access address that comprises a bank address designating one of the memory banks and a cell address, designating one or more memory cells of the memory array; an address bus interconnecting the command and address unit to the address circuit of each of the memory banks so that the access address is conveyed onto the address bus from the command and address unit and that at least the cell address of the access address is fetched as the address information into the address circuit of one of the memory banks that is designated by the bank address of the access address; a data input/output unit comprising: a second latch circuit configured to temporarily store in the data read operation first data to be outputted to outside of the device and in the data write operation second data to be supplied from the outside of the device, and an input/output circuit receiving the first data from the second latch circuit and outputting the first data to the outside of the device in the data read operation, the input/output circuit further receiving the second data from the outside of the device and supplying the second data to the second latch circuit in the data write operation; and a data bus interconnecting the second latch circuit of the data input/output unit to the first latch circuit of each of the memory banks, the data bus being used in common to convey the read data from the first latch circuit of each of the memory banks to the second latch circuit of the data input/output unit as the first data and to convey the second data from the second latch circuit of the data input/output unit to the first latch circuit of each of the memory banks as the write data; the command and address unit further including a pipeline control circuit that is configured to respond to a plurality of access requests, which are consecutively supplied with respective commands and with respective access addresses including different bank addresses from one another, and to execute in pipeline manner the respective commands on respective memory banks designated by the different bank addresses.