Patent ID: 7870342

Claim:
A memory storage system that is accessed by a first central processing unit (CPU), comprising: a line cache including a plurality of pages that are accessed by the first CPU; a first memory device that stores data that is loaded into said line cache when a miss occurs, wherein when said miss occurs and before a second miss occurs, n pages of said line cache are loaded with data from sequential locations in said first memory device, wherein n is greater than one; a second memory device; and a line cache control system that controls data flow between said line cache, the first CPU, said first memory device and said second memory device, and that includes: a first line cache interface that is associated with the first CPU, that receives a first program read request from the first CPU and that generates a first address from said first program read request; a first memory interface that communicates with said first memory device; a second memory interface that communicates with said second memory device; and a switch that selectively connects said line cache to one of said first and second memory interfaces, wherein when said line cache receives said first address, said line cache control system compares said first address to stored addresses in said line cache, returns data associated with said first address if a match occurs, and loads said n pages of said line cache when said miss occurs.