Patent ID: 8288232

Claim:
A manufacturing method of a semiconductor device, comprising the step of: forming, in a semiconductor substrate, a first transistor and a second transistor which have respective gate insulating films of different thicknesses, wherein the step of forming the first transistor and the second transistor includes the steps of (a) forming a first insulating film over the semiconductor substrate; (b) abrading a surface of the first insulating film to reduce a thickness thereof; (c) forming, over the semiconductor substrate and in adjacent relation to the first insulating film, a second insulating film in a region other than a region where the first insulating film is formed; (d) after the step (c), successively forming a first silicon film and a protective silicone nitride film so as to cover the first insulating film and the second insulating film therewith; (e) after the step (d), forming, in a two-dimensional boundary portion between the first insulating film and the second insulating film, a trench portion for isolation extending in a direction of a depth of the semiconductor substrate; (f) after the step (e), forming an insulating film for isolation so as to fill the trench portion for isolation therewith; (g) after step (f), removing the insulating film for isolation deposited over a portion other than in the trench portion for isolation; and (h) after the step (g), removing the protective silicon nitride film, wherein, in the step (a), the first insulating film is formed by a thermal oxidation method so as to extend from an inside of a main surface of the semiconductor substrate to an outside thereof, wherein, in the step (c), the second insulating film is formed so as to be thinner than the first insulating film, wherein the first insulating film is formed as the gate insulating film of the first transistor, and the second insulating film is formed as the gate insulating film of the second transistor, wherein, by the steps (e) to (g), an isolation portion is formed by filling the trench portion for isolation with the insulating film for isolation, wherein the first transistor and the second transistor are formed to be spaced apart from each other by the isolation portion, wherein, in the step (e), the trench portion for isolation is formed so as to extend through the first silicon film and the protective silicon nitride film, wherein, in the step (g), CMP is performed with respect to the insulating film for isolation using the protective silicon nitride film as a CMP stop film to remove the insulating film for isolation, and wherein, in the step (h), etching is performed with respect to the protective silicon nitride film using the first silicon film as an etching stop film to remove the protective silicon nitride film.