Patent ID: 8159271

Claim:
A scan driver, comprising: a counter circuit for generating count data, the count data comprising K bit data, a value of the count data being increased by 1 or being changed every one fixed period, wherein K is a natural number; a first logic circuit for receiving the K bit data and correspondingly generating M first control signals, wherein M is a natural number greater than K; a dynamic decoder, which comprises: N nodes, corresponding to the N output terminals; a voltage setting circuit for setting N first voltage signals on the N nodes substantially to a first level in a precharge period; and a plurality of first transistors, which is arranged to form N rows of transistor circuits connected to the respective N nodes, and is further arranged to form M columns of transistor circuits, wherein the M columns of transistor circuits are controlled by the respective M first control signals in an evaluation period to determine levels of the N first voltage signals; N level shift circuits for lifting the levels of the N first voltage signals to generate respective N second voltage signals; and N output stage circuits for receiving the respective N second voltage signals and outputting respective N gate signals.