Patent ID: 8141024

Claim:
A method to optimize an integrated circuit comprising: receiving a description of a design of the integrated circuit; identifying two or more subsets of the design having similar functionality, but with one or more different input/output (I/O) signals, as candidates for sharing; generating a shared subset of the design resulting from sharing circuit resources among each of the candidates for sharing using a folding transformation, the folding transformation including folding the candidates for sharing onto a set of circuit resources common to each, and time-multiplexing among operations of each of the candidates for sharing; determining which of the candidates for sharing can be operated at a higher clock-frequency; and performing the time-multiplexing of the candidates for sharing at the higher clock-frequency in alternating micro-cycles delimited by cycles of a fast clock, wherein at least one of the receiving, identifying, generating, determining, and performing is performed by a processor.