Patent ID: 7000135

Claim:
A clock control method employed in an information processing device, the information processing device including: first and second processing circuits that perform processing in synchronization with a clock; and a clock supply control circuit that controls supply of the clock to the first processing circuit, wherein a result of the processing in the first processing circuit is inputted to the second processing circuit, in the case where first processing and second processing are executed successively in the first processing circuit, and the first processing circuit starts executing the second processing simultaneously when the second processing circuit starts executing third processing with respect to the result of the processing in the first processing circuit as an input thereto, the clock control method comprising: (1) extracting a first number of cycles required for the execution of the processing in the first processing circuit; (2) transferring the first number of cycles to the clock supply control circuit; (3) starting the supply of the clock when the processing is started in the first processing circuit; (4) determining whether or not the second processing circuit can start processing, when the supply of the clock with the first number of cycles is completed; (5) extracting a second number of cycles required for the execution of the second processing in the first processing circuit; (6) transferring the second number of cycles to the clock supply control circuit; (7) inputting a result of the processing in the first processing circuit to the second processing circuit in the case where it is determined at the operation (4) that the processing can be started; and (8) starting the supply of the clock with the second number of cycles to the first processing circuit so as to start the second processing in the first processing circuit, in the case where it is determined at the operation (4) that the processing can be started.