Patent ID: 7053801

Claim:
An apparatus connected to an Error Correcting Cads (ECC) generating a user bit sequence, the apparatus comprising: an encoder adding a bit, c 0 , at a beginning of c 1 , c 2 , . . , c q bit blocks output from the encoder to determine a reduced number of transitions of the user bit sequence; a precoder receiving and processing the c 0 , c 1 , c 2 , . . . , c q bit blocks and generating a corresponding outputs x 0 , x 1 , x 2 . . . x q using x i =c i ⊕x i−2 ; a channel filter receiving and processing the outputs x 0 , x 1 , x 2 . . . x q and generating data z 0 , z 1 , z 2 . . . z q , which is corrupted by an additive noise, n(i); a Viterbi detector receiving the data z 0 , z 1 , z 2 . . . z q and the additive noise, n(i), and generating bits {circumflex over (x)} 0 , {circumflex over (x)} 1 , {circumflex over (x)} 2 . . . {circumflex over (x)} q ; a filter filtering the bits {circumflex over (x)} 0 , {circumflex over (x)} 1 , {circumflex over (x)} 2 . . . {circumflex over (x)} q and generating bits ĉ 0 , ĉ 1 , ĉ 2 . . . ĉ q ; and a decoder decoding the bits ĉ 0 , ĉ 1 , ĉ 2 . . . ĉ q to produce an output bit sequence that is a reproduction of the user bit sequence.