Patent ID: 7477710

Claim:
A system, comprising: a receiver front end configured for receiving an analog signal and comprising a plurality of discretizers, wherein each of said plurality of discretizers is configured for converting the analog signal to a digital signal, wherein a first discretizer of said plurality of discretizers is configured to sample the analog signal at a first resolution to generate a first digital signal for processing by a receiver at a first bit width, wherein a second discretizer of the said plurality of discretizers is configured to sample the analog signal at a second resolution to generate a second digital signal at a second bit width, and wherein the first bit width is different from the second bit width; and a processing engine communicatively coupled to the second discretizer and configured for substantially canceling one or more interfering signals of the second digital signal, wherein the processing engine comprises a matrix generator configured for generating an interference matrix from at least one code of the one or more interfering signals.