Patent ID: 7538763

Claim:
A semiconductor device that generates an output voltage obtained from a voltage between first and second power supply lines, the semiconductor device comprising: third to (M+1)th power supply lines (M being an integer larger than 2); a first circuit that is connected with the first and second power supply lines and a boost power supply line, the first circuit generating a first voltage obtained by multiplying the voltage between the first and second power supply lines, the first circuit outputting the first voltage between the first power supply line and the boost power supply line; a second circuit that is connected with the first power supply line, the boost power supply line, and an output power supply line, the second circuit including a plurality of switching elements; a first terminal electrically connected with the first power supply line; and a second terminal electrically connected with at least one of the plurality of switching elements, the second circuit outputting a second voltage obtained by multiplying the first voltage between the first power supply line and the boost power supply line by a charge-pump operation using a capacitor and the plurality of switching elements, the second circuit outputting the second voltage between the first power supply line and the output power supply line, the capacitor being connected outside the semiconductor device between the first terminal and the second terminal, the first circuit including: first to (M−1)th boost capacitor, the j-th boost capacitor (1≦j≦M−1, j being an integer) being connected between the j-th power supply line and the (j+1)th power supply line in a first period, and connected between the (j+1)th power supply line and the (j+2)th power supply line in a second period, the second period being subsequent to the first period; and first stabilization capacitor when M being 3 or first to (M−2)th stabilization capacitors when M being an integer larger than 3, the k-th stabilization capacitor (1≦k≦M−2, k being an integer, M being an integer larger than 2) being connected between the (k1)th power supply line and the (k+2)th power supply line, and storing an electric charge discharged from the k-th boost capacitor in the second period.