Patent ID: 7131106

Claim:
A method of designing a circuit pattern of an integrated circuit comprising the following steps: calculating a window of lithography process on a substrate to be processed, the window being calculated at least in a partial data of a first design data for designing the circuit pattern of the integrated circuit, and the window also being calculated in consideration of physical specification values of an exposure mask for use in transfer of the circuit pattern; comparing the calculated window of lithography process and an actually required window of lithography process on the substrate to be processed; revising the partial data in response to said comparing and the calculated window of lithography process being smaller than the actually required window of lithography process, the partial data being revised such that a window of lithography process on the substrate, which is calculated based on the revised partial data, is equal to or larger than the actually required window of lithography process; and preparing a second design data, wherein the second design data is prepared by updating the first design data by using the revised partial data.