Patent ID: 7084455

Claim:
A power semiconductor device made in accordance with the method comprising the steps of: A. providing a substrate of a first conductivity type; B. forming a voltage sustaining region on said substrate by: 1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first or a second conductivity type; 2. forming at least one terraced trench in said epitaxial layer, said terraced trench having a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween; 3. depositing a barrier material along the walls and bottom of said trench; 4. implanting a dopant of a conductivity type opposite to the conductivity type of the epitaxial layer through the barrier material lining at said at least one annular ledge and at said trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region; 5. diffusing the dopant in said at least one annular doped region and said another doped region to cause said at least one annular doped region and said another doped region to overlap one another, whereby a continuous doped column is formed in said epitaxial layer; 6. depositing a filler material in said terraced trench to substantially fill said terraced trench; and C. forming over said voltage sustaining region at least one region of conductivity type opposite to the conductivity type of the epitaxial layer to define a junction therebetween.