Patent ID: 7382644

Claim:
A memory comprising: a substrate including address lines and active circuitry, the active circuitry including sensing circuitry and address decoding circuitry, the address decoding circuitry in communication with the address lines; and a stacked two-terminal cross point memory array positioned over the substrate and the active circuitry, the stacked two-terminal cross point memory including a plurality of memory layers vertically stacked upon one another, each memory layer including a plurality of addressable two-terminal memory plugs that are activated by the address decoding circuitry, each two-terminal memory plug operable to be reversibly written to a first resistive state at a first write voltage, reversibly written to a second resistive state at a second write voltage, and have its resistive state determined at a read voltage, each memory layer including at least one reference cell operative to contribute a reference level associated with its respective memory layer, wherein the sensing circuitry is operative to produce an output that is a function of the resistive state of the activated two-terminal memory plug and the reference level, and wherein the at least one reference cell is similar in structure to the plurality of two-terminal memory plugs.