Patent ID: 6947919

Claim:
A circuit for reversing the order of bits in a bit pattern comprising 2 N bits, N being a positive integer, the circuit comprising: a register to store the bit pattern; shifting logic configured to shift the bit pattern to the left or to the right by j bits to produce a shifted bit pattern, j being a positive-integer power of two less than or equal to 2 (N−1) , masking logic configured to bit-wise AND the shifted bit pattern with an alternating pattern of j logical 1's followed by j logical 0's to produce a first intermediate result, when the bit pattern is shifted to the left by j bits, and to bit-wise AND the shifted bit pattern with an alternating pattern of j logical 0's followed by j logical 1's to produce a second intermediate result, when the bit pattern is shifted to the right by j bits; and combining logic configured to bit-wise OR the first intermediate result with the second intermediate result to produce a combined result.