Patent ID: 6841455

Claim:
A method for fabricating an array of integrated circuit chips in a semiconductor wafer, while simultaneously fabricating seal structures in scribe streets bordering said circuit chips, comprising the steps of: depositing an electrically insulating layer onto said wafer to form an insulating portion of an active circuit component, while simultaneously forming an insulating portion of said seal structure; patterning said insulating layer within each said integrated circuit to form interconnect vias, while simultaneously creating continuous and discontinuous openings through an insulating layer of said seal structure from one surface to the opposite surface; depositing metal onto said insulating layer to form vertical component interconnections, while simultaneously filling said seal structure openings to form a portion of said seal structure; patterning said metal layer within each said integrated circuit to form lateral interconnections, while simultaneously forming lateral metal portions of said seal structure; repeating said simultaneous deposition and patterning steps of consecutive insulating and metal layers, until the circuit interconnections and said scribe street seals are completed.