Patent ID: 7645668

Claim:
A method of manufacturing a memory device, comprising: forming a charge trapping layer on a substrate; forming a protection layer and a buffer layer on the charge trapping layer; forming an insulating layer on the substrate adjacent to the charge trapping layer, wherein an upper surface of the charge trapping layer is exposed by the insulating layer, and forming the insulating layer includes: depositing an insulating material on the substrate to cover the charge trapping layer, the protection layer, and the buffer layer, and polishing the insulating material until it has a thickness in a range of about 50 Å to about 100 Å, wherein the polishing also exposes the protection layer; forming a dielectric layer on the exposed charge trapping layer and on the adjacent insulating layer; forming an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer; and forming an isolation layer in a trench in the substrate, wherein the isolation layer projects above the protection layer, removing the protection layer so as to expose the buffer layer, the buffer layer having a height lower than that of the insulating layer; and removing the buffer layer and partially removing the insulating layer and the isolation layer while maintaining an upper surface of the insulating layer at a height equal to or above a height of an upper surface of the charge trapping layer.