Patent ID: 7663414

Claim:
A prescaling stage for a resistive load comprising: a bistable latch circuit, comprising respective master and slave portions inserted between a first voltage reference and a second voltage reference and feedback connected to each other, each of the master and slave portions including: a differential stage supplied by said first voltage reference; a differential pair of cross-coupled transistors supplied by output terminals of said differential stage and connected by said transistor stage to said second voltage reference; and a transistor stage connecting the differential stage and the differential pair of cross-coupled transistors to said second voltage reference; a degeneration capacitance inserted in correspondence with respective emitter or source terminals of said transistors of said differential pair and adapted to increase a maximum working frequency of the bistable latch circuit; wherein said transistor stage of each of the master and slave portions comprises first and second transistors inserted, in parallel with each other, between said differential stage and an internal circuit node and having respective control terminals connected to each other, a third transistor inserted between a first end of said degeneration capacitance and said internal circuit node, and a fourth transistor inserted between a second end of said degeneration capacitance and said internal circuit node, said third and fourth transistor having common control terminals.