Patent ID: 7555424

Claim:
A method comprising: emulating a circuit design in a logic emulation system, the emulated circuit design comprising logic gates and an emulated memory having a plurality of memory locations, the logic emulation system having at least one log memory associated with the emulated memory, the log memory having a plurality of log memory locations, each of the plurality of log memory locations corresponding to a location of the associated emulated memory and being marked invalid at a predetermined time; receiving one or more memory write requests at the logic emulation system subsequent to the predetermined time, each memory write request of the one or more memory write requests specifying new data to be written to a specified memory location of the plurality of memory locations in the emulated memory; if a log memory location corresponding to the specified memory location is marked invalid, copying a pre-write content of the specified memory location to the corresponding log memory location and marking the corresponding log memory location as valid, prior to writing the new data at the specified memory location of the emulated memory in response to the memory write request; receiving a request to rewind the emulation of the circuit design at the logic emulation system; and restoring the emulated memory to the predetermined time in response to the rewind request.