Patent ID: 7235884

Claim:
A microelectronic circuit structure, comprising: a metal interconnect layer in a first inter-metal dielectric layer of a circuit structure; an etch stop layer on top of the first inter-metal dielectric layer; a second inter-metal dielectric layer on top of the etch stop layer; a metal via passing through the second inter-metal dielectric layer and the etch stop layer, the via having a bottom area contacting the metal interconnect layer; and a portion of the metal interconnect layer under the via bottom doped with first and second impurity elements to limit the growth of micro-voids between the metal interconnect layer and the via; wherein the first impurity element is hydrogen that is implanted into the portion of the metal interconnect layer under the via bottom; the second impurity element is alloyed with the portion of the metal interconnect layer under the via bottom by depositing the second impurity element on said portion and annealing the deposited impurity element; and the metal in the metal interconnect layer and the via includes copper, the hydrogen is implanted at an implant energy in a range between 1 and 1,000 KeV, and the hydrogen ion implant dose is in a range between 1×10 12 cm −2 and 1×10 17 cm −2 .