Patent ID: 8892958

Claim:
A processor comprising: an instruction sequencing unit that fetches instructions and dispatches instructions for execution; one or more execution units, coupled to the instruction sequencing unit, that execute instructions dispatched by the instruction sequencing unit, wherein the one or more execution units execute a first instruction in a multiphase operation including a sequential series of phases and execute a second instruction in a uniphase operation having a single phase; and a trace module coupled to the one or more execution units, the trace module including selection logic that, during instruction execution by the one or more execution units, receives a plurality of internal signals of the processor associated with the instruction execution, wherein the plurality of internal signals includes a phase signal that, for an instruction executed in a multiphase operation, indicates a current phase of the multiphase operation, and wherein the trace module, in response to an indication that execution of the first instruction is a multiphase operation: during a first phase of execution of the first instruction, dynamically selects and outputs as a trace signal a first signal of the plurality of internal signals based at least in part on the phase signal; and thereafter, during a second phase of execution of the first instruction, dynamically selects and outputs as the trace signal a different second signal of the plurality of internal signals based at least in part on the phase signal.