Patent ID: 7795926

Claim:
A phase detector, comprising: a sampling device, configured for sampling a data signal respectively according to a plurality of clock signals, so as to provide a plurality of corresponding sampling values, wherein the clock signals have a same frequency and different phases, the sampling device comprises: a plurality of double-edge triggered flip-flops (DETFFs), each of the DETFFs corresponding to two of the clock signals and two of the sampling values, and each of the DETFFs sampling the data signal according to the two corresponding clock signals so as to provide the two corresponding sampling values; a comparing device, coupled to the sampling device, and configured to provide a plurality of corresponding comparison values according to comparison results of each of the sampling values comparing with the next sampling value; a delay device, configured for delaying the clock signals for a predetermined delay time, and providing a plurality of corresponding delay clock signals; and an output device, coupled to the comparing device and the delay device, and configured to output two of the comparison values in response to transition edges of the delay clock signals, the two outputted comparison values serving as a first instruction signal and a second instruction signal respectively.