Patent ID: 7061271

Claim:
A six-input look-up table architecture comprising: sixty-four memory cells adapted to store sixty-four corresponding data values; a set of sixty-four transmission gates coupled to receive the sixty-four data values from the sixty-four memory cells; a first input line configured to provide a first input signal to the set of sixty-four transmission gates, wherein the set of sixty-four transmission gates is configured to route thirty-two of the sixty-four data values in response to the first input signal; a set of thirty-two transmission gates coupled to receive the thirty-two data values routed by the set of sixty-four transmission gates; a second input line configured to provide a second input signal to the set of thirty-two transmission gates, wherein the set of thirty-two transmission gates is configured to route sixteen of the thirty-two data values in response to the second input signal; a 16:1 multiplexer coupled to receive the sixteen data values routed by the set of thirty-two transmission gates; third, fourth, fifth and sixth input lines configured to provide third, fourth, fifth and sixth input signals, respectively, to the 16:1 multiplexer, wherein the 16:1 multiplexer is configured to route one of the sixteen data values in response to the third, fourth, fifth and sixth input signals; and a set of sixteen buffers coupled between the set of thirty-two transmission gates and the 16:1 multiplexer, wherein the sixteen buffers are configured to drive the sixteen data values routed by the set of thirty-two transmission gates.