Patent ID: 7372734

Claim:
A method of operating a memory cell of an electrically erasable and programmable nonvolatile memory device, the memory device comprising at least one memory cell, each memory cell having a substrate of semiconductor material of a p-type conductivity, a well of an n-type conductivity in the substrate, a storage transistor comprising a source and a drain formed in the well and having the p-type conductivity, a channel of the well between the source and the drain, and a charge storage region disposed over and insulated from the channel by an insulator, and an injector having a p-type region disposed adjacent to and isolated from the channel, the method comprising the steps of: applying a first voltage to the p-type region of the injector; applying a second voltage to the well; and applying a third voltage to at least one of the source and the drain to form an inversion layer in the channel; wherein the first voltage is sufficiently more positive with respect to the second voltage and the second voltage is sufficiently more positive with respect to the third voltage to injected holes from the injector to transport through the well, through the channel and through the insulator onto the charge storage region.