Patent ID: 7843718

Claim:
A non-volatile memory device, comprising: a substrate; an insulating layer on the substrate; a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string; and a bit line on the insulating layer and electrically connected to a last one of the plurality of resistive memory cells, wherein at least one of the plurality of resistive memory cells comprises: a switching device including a body pattern comprising a source region, a channel region, and a drain region stacked in the insulating layer, and a gate electrode on a sidewall of the body pattern; and a data storage element connected in parallel with the switching device, the data storage element comprising a lower electrode spaced apart from the body pattern of the switching device, a variable resistor on the lower electrode, and an upper electrode on the variable resistor, wherein the upper electrode of the first one of the plurality of resistive memory cells is on the lower electrode and the body pattern of the next one of the plurality of resistive memory cells in the NAND type memory cell string.