Patent ID: 7436019

Claim:
A floating gate memory cell on a substrate surface, comprising: a floating gate having a first floating gate portion and a second floating gate portion; the first floating gate portion bounded by a first shallow trench isolation structure and a second shallow trench isolation structure in a first direction; the first floating gate portion having a lower surface that extends across the substrate surface and an upper surface parallel to the lower surface, the upper surface bounded in a second direction that is perpendicular to the first direction by a first edge and a second edge; and the second floating gate portion extends upward from the upper surface of the first floating gate portion, the second floating gate portion has a first vertical surface that extends upward from the first edge of the upper surface of the first floating gate portion, the second floating gate portion has a second vertical surface that extends upward from a line on the upper surface of the first floating gate portion that is between and runs parallel to the first edge and the second edge, the second floating gate portion has a top surface.