Patent ID: 7476580

Claim:
A method of fabricating a MOS (metal oxide semiconductor) device comprising: providing a substrate including gate stacks comprising a gate dielectric atop a substrate, a single crystal Si lower gate conductor atop the gate dielectric, and a poly-SiGe upper gate conductor; removing the poly-SiGe upper gate conductor from at least one of the gate stacks to provide an exposed surface of the single crystal Si lower gate conductor of the at least one of the gate stacks, wherein the poly-SiGe upper gate conductor remains in a remaining portion of the gate stacks; forming strained SiGe on the exposed surface of the single crystal Si lower gate conductor of the at least one of the gate stacks; removing the polysilicon Si-Ge upper gate conductor from at least one of the remaining portion of the gate stacks to provide an exposed surface of the single crystal Si lower gate conductor of the at least one of the remaining portion of the gate stacks; and forming strained Si:C on the exposed surface of the single crystal Si lower gate conductor of the at least one of the remaining portion of the gate stacks.