Patent ID: 7545007

Claim:
An MOS varactor comprising a gate electrode isolated from a lower electrode by an insulator layer, the gate electrode comprising a first region and a second region abutting the first region, in which said first region comprises a material of a first conductivity type and said second region comprises a material of a second conductivity type opposite the first conductivity type, wherein said gate electrode further includes a third region comprising a material of the first conductivity type formed adjacent to said second region, whereby said second region is bracketed by said first and third regions, wherein said lower electrode extends substantially between and to a depth greater than a depth of a pair of adjacent isolation insulators, said lower electrode overlaps respectively with each of the pair of adjacent isolation insulators, the gate electrode located substantially between the pair of adjacent isolation insulators, and said lower electrode comprises a contact located entirely within a portion of said lower electrode, said contact located between a first side of the gate electrode and a first of said pair of adjacent isolation insulators, and said contact located adjacent to said first region of the gate electrode, said contact comprising the material of the first conductivity type.