Patent ID: 7843711

Claim:
A switching transistor driver circuit in which a series junction between a high-side switching transistor on a high potential side and a low-side switching transistor on a low potential side is an output terminal, and power supply to the output terminal is controlled, the switching transistor driver circuit comprising: a reset dominant latch circuit; a high side circuit which is switched based on a first input pulse signal fed to a high side input terminal and generates a control pulse signal for turning on/off the high side switching transistor; and a low side circuit which is switched based on a second input pulse signal fed to a low side input terminal and generates a control pulse signal for turning on/off the low side switching transistor, wherein the low side circuit comprises: a delay circuit which is disposed on a path from the low side input terminal to the low-side switching transistor to make a correction of a signal delay time in the high side circuit and contributes to formation of the control pulse signal for turning on/off the low-side switching transistor; and a reset pulse generation circuit for delaying the second input pulse signal fed from the low side input terminal and generating a reset pulse signal for preventing a malfunction for the high side circuit, the high side circuit comprises: a first edge detection circuit for detecting a leading edge of the first input pulse signal; a second edge detection circuit for detecting a trailing edge of the first input pulse signal; a first level shift circuit for changing a voltage level of a first edge signal outputted from the first edge detection circuit; and a second level shift circuit for changing a voltage level of a second edge signal outputted from the second edge detection circuit, the latch circuit has a minimum reference potential terminal connected to a low potential side of the high-side switching transistor, the latch circuit has a set terminal fed with a signal obtained by changing, in the first level shift circuit, the voltage level of the first edge signal, the latch circuit has a reset terminal fed with signals obtained by changing, in the second level shift circuit, the voltage level of the second edge signal and a voltage level of the reset pulse signal outputted from the reset pulse generation circuit, the high-side switching transistor is driven based on an output signal from the latch circuit, and the latch circuit is reset in one of a period during which a terminal voltage of the output terminal is inverted or a period immediately after the inversion.