Patent ID: 8779471

Claim:
A field-effect transistor comprising: a gate insulating layer; a first semiconductor crystal layer in contact with the gate insulating layer; a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer, the second semiconductor crystal layer being in contact with a source electrode and a drain electrode, and the source electrode and the drain electrode being in contact with only the second semiconductor crystal layer; and a third semiconductor crystal layer lattice-matching or pseudo lattice-matching the second semiconductor crystal layer, wherein the third semiconductor crystal layer is positioned between the first semiconductor crystal layer and the second semiconductor crystal layer, wherein the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of In x1 Ga 1-x1 As y1 P 1-y1 (0<x1≦1, 0≦y1≦1), the second semiconductor crystal layer is made of In x2 Ga 1-x2 As y2 P 1-y2 (0≦x2≦1, 0≦y2≦1, y2≠y1), the third semiconductor crystal layer is made of Al x3 In x4 Ga 1-x3-x4 As y3 P 1-y3 (0<x3<1, 0≦x4<1, 0<x3+x4<1, 0≦y3≦1), the electron affinity E a3 of the third semiconductor crystal layer is lower than the electron affinity E a2 of the second semiconductor crystal layer, and the electron affinity E a1 of the first semiconductor crystal layer is lower than the electron affinity E a2 of the second semiconductor crystal layer.