Patent ID: 7279370

Claim:
A method of fabricating a thin film transistor array substrate, comprising: forming a gate pattern on a substrate, the gate pattern including a gate electrode of a thin film transistor, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line; forming a gate insulating film on the substrate having the gate pattern; forming a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode and a lower data pad electrode connected to the data line, and a semiconductor pattern formed beneath the source/drain pattern there along; and forming a transparent electrode pattern and a passivation film pattern stacked on remaining areas except for areas at which the transparent electrode pattern is formed, wherein the transparent electrode pattern includes a pixel electrode directly contacting both the drain electrode and the semiconductor pattern and formed on the gate insulating film, and the pixel electrode directly contacts an upper gate pad electrode and the lower gate pad electrode along sides of the upper and lower gate pad electrodes, and the pixel electrode directly contacts an upper data pad electrode and the lower data pad electrode along sides of the upper and lower data pad electrodes.