Patent ID: 7290289

Claim:
Processor, comprising: a first calculating unit having a data input and an instruction input; a second calculating unit having a data input and an instruction input; and a controllable complementation means, which is connected to the data input of the second calculating unit on the output side, for receiving data and for outputting the received data in a switched-off state and for outputting the complement of the received data in a switched-on state; and a control means for controlling the two calculating units and such that they operate selectively in a high security mode of operation processing complementary data or in a parallel mode of operation processing independent data, wherein the control means is formed to put the complementation means in the high-security mode of operation to the switched-on state and to supply the same data to the data input of the first calculating unit and the complementation means, and the same instructions to the instruction input of the first calculating unit and the instruction input of the second calculating unit, such that the first and the second calculating unit process complementary data synchronously, and put the complementation means in the parallel mode of operation to the switched-off state and supply first data to the data input of the first calculating unit and second data being independent of the first data to the data input of the second calculating unit, and wherein the control means is further formed to set the high-security mode of operation for security-relevant program parts or programs, and to set the parallel mode of operation for comparatively less security-relevant program parts or programs.