Patent ID: 8354827

Claim:
A control circuit, comprising: a controller providing a master pulse-width-modulated signal indicative of a difference between a predetermined setpoint and a process feedback; a clock providing a clock signal; and a PWM splitter to receive the master pulse-width-modulated signal and the clock signal to provide a first pulse-width-modulated signal to control a first switch and a second pulse-width-modulated signal to control a second switch, the PWM splitter including: a PWM-to-digital converter to provide a first digital signal and a second digital signal, the first digital signal being a period of the master pulse-width-modulated signal and the second digital signal being a time at which the master pulse-width-modulated signal is zero; a control module to receive the first and second digital signals to provide a digital buck control signal and a digital boost control signal, wherein if the second digital signal is greater than first digital signal divided by 2, then the digital buck control signal is two times the first digital signal minus the second digital signal, otherwise the digital buck control signal is equal to the first digital signal, wherein if the second digital signal is less than the first digital signal divided by 2, then the digital boost control signal is two times the first digital signal divided by two minus the second digital signal, otherwise the digital boost control signal is equal to zero, a first digital-to-PWM module to receive the digital buck control signal, the first and second digital signals to provide the first pulse-width-modulated signal; and a second digital-to-PWM module to receive the digital boost control signal, the first and second digital signals to provide the second pulse-width-modulated signal.