Patent ID: 7111125

Claim:
A microprocessor apparatus, for performing a block memory copy operation, the apparatus comprising: translation logic, configured to translate a block allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first block of cache lines in an exclusive state and to copy the contents of a second block of cache lines to said first block of cache lines, wherein said block allocate and rename instruction comprises a modification to an existing prefetch instruction within an existing instruction set, and wherein said existing prefetch instruction does not otherwise provide for allocation and rename of said first block of cache lines, and wherein said block allocate and rename instruction comprises a repeat prefix and a prefetch opcode field within an extended address specifier entity, and wherein a specific value of said prefetch opcode field directs said microprocessor to allocate a first destination cache line in said exclusive state and to copy contents of a first source cache line to said first destination cache line, and wherein other values of said prefetch opcode field direct said microprocessor to execute other types of prefetch operations according to said existing instruction set, and wherein said prefetch opcode field comprises bits 5 : 3 within the ModR/M byte of an x86 prefetch instruction; and execution logic, coupled to said translation logic, configured to receive said micro instruction sequence, and configured to issue transactions over a memory bus that request said first block of cache lines in said exclusive state, and configured to copy said contents of said second block of cache lines to said first block of cache lines.