Patent ID: 7262093

Claim:
A method of forming a flash memory, comprising providing a substrate; forming a layer of gate dielectric; forming a plurality of composite structures above the gate dielectric, each composite structure including a first conductive pattern, a doped oxide pattern, and a nitride pattern; removing the nitride pattern in each composite structure; partially etching the first conductive patterns and the doped oxide patterns, thereby forming two control gates out of each first conductive pattern; forming a plurality of first spacers each on a first sidewall of one of the control gates, wherein each first spacer fully covers the first sidewall of the corresponding control gate; forming a plurality of second spacers each on a second sidewall of one of the control gates after the two control gates are formed; partially removing the plurality of second spacers to expose a side of the doped oxide pattern and a portion of each control gate; forming a plurality of third spacers on the exposed portions of the control gates; forming a plurality of floating gates on the third spacers; and forming each of a plurality of bit line contacts between every two control gates formed out of one first conductive pattern.