Patent ID: 7383145

Claim:
A circuit comprising: a multiphase clock register, multiple phases, an adjustable droop amplifier, and an error circuit with an error amplifier, wherein each phase of said regulator include a set register, gate driver, output FETs, a current sense circuit, an adjustable sense amplifier, and a pulse width moderator; and wherein: said multiphase clock register has N phases, where N is an integer from 1 to infinity; said multiple phases are N phases, where N is an integer from 1 to infinity; a phase of said multiphase clock generator drives the set input of said set register; said set register drives said gate driver and said output FETs; said output FETs drive the load of the circuit; said current sense circuit measures the current of said output FETs and feeds back to said set register via said adjustable sense amplifier and said pulse width modulator; said adjustable sense amplifier also feeds into said adjustable droop amplifier; said droop amplifier drives said error circuit; and said error circuit drives each pulse width modulator on each said phase.