Patent ID: 8838664

Claim:
A method for compressing a plurality of partial products comprising a last partial product during a fused multiply-and-accumulate operation executed on a fused multiply-and-accumulate unit of a processor, the method comprising: in the fused multiply-and-accumulate unit of the processor, performing operations for: compressing, during a first compression stage, the plurality of partial products except for the last partial product to generate first outputs; changing a particular bit of a selected one of the first outputs from a logical zero value to a logical one value to generate a modified first output; compressing, during a second compression stage, the modified first output and other unmodified ones of the first outputs to generate second outputs; compressing, during a third compression stage, the second outputs to generate third outputs; compressing, during a fourth compression stage, the third outputs to generate a fourth carry output and a fourth sum output; and generating an intermediate partial product based on the last partial product, wherein the intermediate partial product is the last partial product when a specific bit in the last partial product has a logical zero value, and when the specific bit in the last partial product has a logical one value, wherein the specific bit in the last partial product is changed to be a logical zero value during generation of the intermediate partial product.