Patent ID: 8143671

Claim:
A semiconductor structure, comprising: a semiconductor structure which includes a semiconductor substrate, wherein a top substrate surface of the semiconductor substrate defines a reference direction perpendicular to the top substrate surface; a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, wherein the first doped transistor region is not a portion of a Source/Drain region of the first transistor, and wherein the first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity; a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, wherein the second gate dielectric layer (i) is sandwiched between and (ii) electrically insulates the second gate electrode region and the semiconductor substrate; a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, wherein the first gate dielectric layer (i) is sandwiched between and (ii) electrically insulates the first gate electrode region and the semiconductor substrate, wherein the first gate electrode region of the first transistor is on and totally above the top substrate surface, and wherein the second gate electrode region of the second transistor is on the semiconductor substrate and totally below the top substrate surface; and a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate, wherein the second doped transistor region and the second doped Source/Drain portion comprise dopants of the first doping polarity, and wherein the second doped Source/Drain portion is in direct physical contact with the first doped Source/Drain portion.