Patent ID: 7659196

Claim:
A method, comprising: forming a hard mask directly on an interlayer dielectric layer wherein said hard mask has a thickness greater than 10 nanometers and less than 30 nanometers and wherein said hard mask comprises titanium; patterning said hard mask; etching said interlayer dielectric layer, wherein said etching forms a partial via that leaves a portion of said interlayer dielectric layer in said partial via; forming a trench before removing said hard mask including: further patterning said hard mask, and etching said interlayer dielectric layer to form said trench and to completely remove said interlayer dielectric layer that remains in said partial via, wherein said trench and said via form a dual damascene structure; and, subsequently, removing said hard mask during a post-etch clean with a wet etchant having a selectivity to etch said hard mask at a greater rate than said interlayer dielectric layer; and depositing a metal in said dual damascene structure to form an interconnect after removing said hard mask.