Patent ID: 7233635

Claim:
An apparatus for digital symbol synchronization, comprising: A/D converting means for over-sampling an analog signal to a digital signal according to an Analog/Digital (A/D) clock and outputting over-sampled symbols; symbol timing calculating means for calculating a symbol timing value based on the over-sampled symbols by receiving the over-sampled symbols, classifying the over-sampled symbols, accumulating absolute values of the classified symbols, and outputting the symbol timing value; symbol timing determining means for determining a best symbol timing based on the symbol timing value and outputting the best symbol timing; and A/D clock supplying means for receiving the best symbol timing and supplying the A/D clock to the A/D converting means, wherein the A/D clock is determined according to the best symbol timing; wherein the symbol timing calculating means includes: sample arranging means for classifying the over-sampled symbols of which phases are the same based on a phase of the over-sampled signal-symbols in a symbol interval into a sample unit and outputting classified symbols; and symbol integrating means for accumulating the absolute values of the classified symbols and outputting an integration value as the symbol timing value.