Patent ID: 8405018

Claim:
A semiconductor imager device being arranged for receiving a series of charge packets, comprising a charge-to-voltage conversion circuit arranged for receiving said charge packets on a reception capacitance, and having an interconnected arrangement of a floating diffusion, a first reset gate, a reset drain and, and a source follower for readout, characterized in that said device has a series arrangement of at least said first reset gate as a proximate reset gate and furthermore a distal reset gate, wherein said proximate reset gate and said distal reset gate are spatially separated by a region, wherein in a high-gain configuration said proximate reset gate is cyclically controlled and said distal reset gate is continuously on, thus limiting said reception capacitance to a relatively low value, whilst in a low-gain configuration said proximate reset gate is continuously on, thus extending said capacitance to a relatively high value corresponding to a low gain factor and in that said distal reset gate replaces said proximate reset gate as being cyclically controlled for conversion of said series of charge packets, wherein said region is dimensioned so that a ratio of the high gain factor to the low gain factor is tuned to a selected value of at least 1.5.