Patent ID: 7692263

Claim:
A multiple field plate transistor, comprising: an active region; a source electrode in electrical contact with said active region; a drain electrode in electrical contact with said active region; a gate, in electrical contact with said active region, between said source and said drain; a first insulating spacer layer disposed over said active region between said source and said gate; a second insulating spacer layer disposed over said active region between said drain and said gate; a first conducting field plate, disposed on said first spacer layer between said source and said gate, electrically connected to said gate and extending toward said source; a second conducting field plate, disposed on said second spacer layer between said drain and said gate, electrically connected to said gate and extending toward said drain; a third insulating spacer layer, disposed on said first spacer layer, said second spacer layer, said first field plate, said gate, and said second field plate, between said source and said drain; and a third conducting field plate, disposed on said third spacer layer over said gate, said second field plate, and said second spacer layer, electrically connected to said source and extending toward said drain, wherein said transistor has an L g length ranging from approximately 1.2 microns to approximately 1.5 microns, an L gd length ranging from approximately 13.3 microns to approximately 18 microns, a L ds length ranging from approximately 16 microns to 21.5 microns, an L fd1 length ranging from approximately 1.5 microns to 1.8 microns, and an L fd2 length of approximately 4.5 microns.