Patent ID: 7488644

Claim:
A method of manufacturing a semiconductor comprising: forming a first insulating layer on a semiconductor having capacitor contact regions; forming bit lines on the first insulating layer between the capacitor contact regions, wherein each of the bit lines includes a first conductive pattern and a bit line mask pattern; forming a second insulating layer comprising an oxide based material on the bit lines and on the first insulating layer; planarizing the second insulating layer until surfaces of the bit lines are exposed; forming contact patterns on the bit lines to open storage node contact hole regions, wherein each of the contact patterns comprises a material having an etching selectivity relative to the second insulating layer; forming first spacers on sidewalls of the contact patterns, wherein each of the first spacers comprises a material having an etching selectivity relative to the second insulating layer; etching the second and first insulating layers using the contact patterns and the first spacers as masks to form storage node contact holes exposing the capacitor contact regions and simultaneously forming second spacers comprising portions of the second insulating layer on sidewalls of the bit lines; and filling the storage node contact holes with a second conductive layer to form storage node contact pads.