Patent ID: 7314780

Claim:
A method of production of a semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, comprising: forming a capacitor structure in a topmost stacked structure of said multilayer interconnect structure, said forming a capacitor structure comprising: processing for forming at a bottommost layer of said topmost stacked structure a conductor layer for bottom electrodes of said capacitor structure, processing for forming on said bottom electrodes by electrodeposition using an electrolyte comprised of high dielectric constant inorganic filler and insulating resin dispersed in a colloidal state a mixed electrodeposited layer of said inorganic filler and said insulating resin as a dielectric layer of said capacitor structure, processing for forming on said dielectric layer a conductor layer for top electrodes of said capacitor structure, and processing for forming inside said capacitor structure chip connection pads for directly connecting said top electrodes and said bottom electrodes with electrodes of said semiconductor chip.