Patent ID: 8675407

Claim:
A semiconductor memory device comprising: a plurality of memory cell transistors provided in each block, and configured to be capable of holding data; a row decoder including transfer transistors, a voltage controller and a block selector in each block, the transfer transistors electrically connected to respective of the memory cell transistors, the voltage controller connected to gates of the respective transfer transistors and capable of transferring a desired voltage to the gates of the respective transfer transistors, the block selector electrically connected to gates of the respective transfer transistors and configured to select blocks; a voltage generator configured to generate the voltage to be supplied to the transfer transistors; and a controller configured to control the row decoder and the voltage generator, wherein when data is written, the gates of the respective transfer transistors are connected to the voltage controller in each non-selected block, and the gates of the respective transfer transistors are disconnected from the voltage controller in each selected block.