Patent ID: 7180313

Claim:
A test device for testing digital semiconductor circuits at wafer level, comprising: an interposer comprising a printed circuit board with contact pins on both sides; a needle or contact stud card; and a probe card which sends and receives digital test signals to and from a test head and distributes signal channels, carrying test signals, to respective locations on a wafer via the interposer; wherein: the interposer is arranged between the needle or contact stud card and the probe card so as to mechanically and thermally decouple an interface of the probe card with the test head and needles or contact studs disposed on the needle or contact stud card; all signal channels in the test device or signal channels which carry time-critical test signals in the test device comprise a respective logic signal amplifier mounted on the printed circuit board of the interposer; and each logic signal amplifier amplifies a respective signal received from the wafer or transmitted to the wafer using high and low signal levels.