Patent ID: 8829865

Claim:
A power factor correcting circuit having a positive input terminal, an output terminal and a ground terminal, comprising: a power factor inductor coupled in series between said positive input terminal and said output terminal, said power factor inductor comprising an output side coupled to a first node; a main switch configured to periodically connect said power factor inductor to said ground terminal; a snubber circuit coupled to said main switch, said snubber circuit comprising: a choke inductor and an auxiliary switch coupled in series across said main switch, said choke inductor and said auxiliary switch configured to provide zero voltage switching for said main switch; a clamping capacitor coupled to said power factor inductor at said first node, said clamping capacitor configured to provide zero turn-off loss for said main switch; a conducting diode coupled to said choke inductor and said auxiliary switch at a second node; a discharge diode coupled to said clamping capacitor and said conducting diode at a third node; and an output diode connected in series between said power factor inductor and said output terminal, wherein said output diode is connected to said power factor inductor and said output diode at said first node.