Patent ID: 7078278

Claim:
A method of forming a dual metal CMOS arrangement, comprising the steps: forming silicon regions on a gate dielectric layer to form gate electrodes in NMOS device regions and in PMOS device regions; depositing a first metal or metal alloy on the silicon regions in the NMOS device regions and a second metal or metal alloy on the silicon regions in the PMOS device regions; annealing to react the first metal or metal alloy with the silicon regions in the NMOS device regions to thereby form first silicide regions and first metal or metal alloy regions on the first silicide regions and to react the second metal or metal alloy with the silicon regions in the PMOS device regions to thereby form second silicide regions and second metal or metal alloy regions on the second silicide regions; and wherein the first silicide regions have a work function within +/−0.2V of the conduction band of silicon, and the second silicide regions have a work function that is within +/−0.2V of the valence band of silicon.