Patent ID: 6906365

Claim:
A ferroelectric memory device comprising: a semiconductor substrate; a transistor including a source, a drain and a gate formed at a surface of said substrate; an insulating layer formed to cover said transistor; a ferroelectric capacitor having a laminated structure, including at least a lower electrode, a ferroelectric film, an upper electrode, and an upper protection electrode formed over said upper electrode; a barrier layer disposed on said upper protection electrode; an interlayer insulation layer formed on said upper protection electrode; and a wiring layer formed on said interlayer insulation layer to contact said upper protection electrode through a contact hole in said interlayer insulation layer, wherein said upper protection electrode contains at least one material selected from a group consisting of Ir and Ru and is directly formed on an entire upper surface of said upper electrode, and wherein said barrier layer comprises Si 3 N 4 and is disposed so as to completely cover both an upper surface and a side surface of said ferroelectric capacitor to protect said ferroelectric capacitor against harmful conditions during both a deposition process of said interlayer insulation layer and said wiring layer and forming process of said contact hole.