Patent ID: 8316187

Claim:
A cache memory comprising: one or more cache lines of equal size, each said cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and a predict buffer, of size equal to the size of said cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous said access request to the same cache block in said cache memory, wherein said next block of data from said main memory having an address next to an address of said same cache block in said memory; wherein said predict-fetch signal is generated by comparing a number of successive cache hits generated by said access requests from said processor to said same cache block with a predetermined threshold and asserting said predict-fetch signal based on said comparison, wherein said generating further comprises comparing, if an access request by said processor generates a cache miss, an address of a requested cache block with an address of the cache block in said predict buffer and moving the cache block in the predict buffer to one of said cache lines based on said comparison, wherein if a predict-fetch from the main memory is in progress, the number of the successive cache hits is reset.