Patent ID: 7191366

Claim:
A method for implementing seamless error resumption in a shared memory bus structure utilizing a slave control unit coupled to the shared memory bus structure, said shared memory bus structure coupled to at least one master device and at least one slave device, and said slave control unit included in said at least one slave device, said slave control unit containing two main functional islands that are both implemented separately for both a write oath and a read path or read and write operations from and to the slave device, said method performed by said slave control unit comprising the steps of: storing interface controls and data for each read operation and each write operation; monitoring each read operation and each write operation to determine when an error has occurred for a read operation or a write operation; identifying when an error has occurred and capturing error conditions when said error can be suppressed for the read operation or the write operation; and suppressing said error; and gating said stored interface controls and data to continue the read operation or the write operation: and resuming without restarting the read operation or the write operation.