Patent ID: 7015101

Claim:
A method for manufacturing an integrated circuit structure, comprising: providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate, the gate dielectric layer being formed in a plurality of thicknesses in a plurality of devices over the semiconductor substrate; forming a second dielectric layer over at least one of the devices regions; forming a third dielectric layer over at least a portion of the second dielectric layer, selectively implanting ion traps in portions of the second dielectric layer; and the gate dielectric layer being formed in a plurality of thicknesses by: initially forming the gate dielectric layer over the semiconductor substrate in a substantially uniform thickness; forming the second dielectric layer over the gate dielectric layer; patterning and forming a photomask over at least one devices region; removing the second dielectric layer in other devices regions; removing at least portions of the gate dielectric layer in the other devices regions; and forming the third dielectric layer over a plurality of the devices regions including at least one of the other devices regions, the third dielectric layer combining with unremoved portions of the gate dielectric layer in the other devices regions to form a thicker dielectric layer therein.