Patent ID: 8618424

Claim:
A multilayer wiring substrate, comprising: a first insulating layer comprising a first surface and a second surface opposite to the first surface; a second insulating layer on the first surface of the first insulating layer; a first wiring pattern on the second surface of the first insulating layer; a second wiring pattern on a surface of the second insulating layer, the second wiring pattern being opposed to the first wiring pattern; a first via formed through the first insulating layer and electrically connected to the first wiring pattern; a second via formed through the second insulating layer and electrically connected to the second wiring pattern, the second via being opposed to the first via; and a third wiring pattern formed on the first surface of the first insulating layer and embedded in the second insulating layer, the third wiring pattern having a hole therethrough, and wherein the first via and the second via are connected to each other through a metal filled in the hole of the third wiring pattern, wherein the third wiring pattern comprises a first surface and a second surface opposite to the first surface, wherein a diameter of the first via is gradually decreased toward the first surface of the third wiring pattern, and the first via comprises: a top surface contacting the first wiring pattern; and a bottom surface opposite to the top surface and contacting the first surface of the third wiring pattern, wherein a diameter of the second via is gradually decreased toward the second surface of the third wiring pattern, and the second via comprises: a top surface contacting the second wiring pattern; and a bottom surface opposite to the top surface and contacting the second surface of the third wiring pattern, and wherein a diameter of the hole is smaller than the bottom surfaces of the first via and the second via.