Patent ID: 8688882

Claim:
A system on chip (SoC) comprising: a processor configured to process a task; a system bus; a plurality of modules operationally coupled to the processor through the system bus; an interrupt proxy processing unit operationally coupled to the processor and the plurality of modules, and the interrupt proxy processing unit configured to solely process an interrupt-related task associated with a first module of the plurality of modules, wherein the interrupt proxy processing unit is configured to release an interrupt from the first module as part of the interrupt-related task and the interrupt proxy processing unit includes, a status register configured to store interrupt status information regarding the interrupt received from the first module and store an interrupt release signal received from the processor if the processor releases the interrupt, the status register including, a first storage region configured to store the interrupt status information, a second storage region configured to store the interrupt release signal, and a third storage region configured to store transmission execution information based on the interrupt status information; a bus interface configured to supply the interrupt release signal to the first module; and a priority determination unit between the status register and the processor, and the priority determination unit configured to select information having a highest interrupt priority among the interrupt status information and supply the selected information to the processor.