Patent ID: 8918679

Claim:
A chip card or smart card security controller comprising a data processor having an arithmetic logic unit configured to calculate an output datum based on at least one an input datum, an error detector configured to check the output datum for an error based on the output datum and the at least one input datum, and, if an error is present, generates an error signal; and a controller configured to alternately switch between a normal operating mode and a checking mode, pass the error signal through to an error signal output in the normal operating mode, and blocks the error signal in a checking mode, in order to not let the error signal pass through to the error signal output; each time the controller switches to the checking mode, influences the arithmetic logic unit, the error detector or the input datum such that the error detector detects an error and, if no error signal is received in response to the influencing, output an alarm signal indicating an incorrect execution of the error detection functionality; and subsequently, cause the error detector to check the output datum with regard to an error without influencing the arithmetic logic unit, the error detector and the input datum, and output the alarm signal, if the controller receives a further error signal from the error detector in response to the causing, a circuit adapted to execute a security reset in response to receiving the alarm signal, and adapted to perform one of a termination of a program currently running on the chip card, a security reset and a renewal of an instruction initiating the calculation of the arithmetic logic unit, in response to receiving the error signal via the error signal output.