Patent ID: 8826215

Claim:
A method of placing and routing circuit components comprising: dividing a layout area of an integrated circuit (IC) design into an array of tiles, each tile having a plurality of edges that are common to adjoining tiles; placing of circuit components into the layout area of the IC design such that each tile including a plurality of circuit components, the placing of circuit components being performed for primarily routability without resort to a timing model, routability being measured by congestion of wiring nets at the tile edges; performing a virtual timing operation of the IC design with a virtual timing model assuming ideal buffering is done to test the placement of circuit components; performing a wire synthesis operation of the IC design for layer assignment, buffering and timing optimization while minimizing degradation in routability; and performing a plurality of timing optimizations of the IC design while minimizing degradation in routability; moving circuit components during the plurality of timing optimizations such that a disruptiveness of moving circuit components varies from more disruptive in early timing optimizations to less disruptive in later timing optimizations; wherein the placing of circuit components starts good routability and the following timing optimization steps maintain the good routability; and wherein the method is performed by one or more computing devices.