Patent ID: 8908419

Claim:
A method of fabricating a semiconductor device comprising at least two memory cells, wherein the at least two memory cells have first and second memory cells, each containing six transistors, which are two access transistors, two drive transistors, and two load transistors, comprising: forming a first poly-silicon wiring layer, a first part of which is structured as a gate of a first access transistor of the first memory cell, and a second part of which is structured as a gate of a second access transistor of the second memory cell; forming a second poly-silicon wiring layer, a first part of which is structured as a gate of a first drive transistor of the first memory cell, and a second part of which is structured as a gate of a first load transistor of the first memory cell; forming a third poly-silicon wiring layer, a first part of which is structured as a gate of a second load transistor of the first memory cell, and a second part of which is structured as a gate of a second drive transistor of the first memory cell; forming a fourth poly-silicon wiring layer, a first part of which is structured as a gate of a second access transistor of the first memory cell; forming a fifth poly-silicon wiring layer, a first part of which is structured as a gate of a first drive transistor of the second memory cell, and a second part of which is structured as a gate of a first load transistor of the second memory cell; forming a sixth poly-silicon wiring layer, a first part of which is structured as a gate of a second load transistor of the second memory cell, and a second part of which is structured as a gate of a second drive transistor of the second memory cell; forming a seventh poly-silicon wiring layer, a first part of which is structured as a gate of a second access transistor of the second memory cell, wherein steps of forming the first, second, third, fourth, fifth, sixth, and seventh poly-silicon wiring layers comprise: setting all distances between the first poly-silicon wiring layer and the third poly-silicon wiring layer, between the second poly-silicon wiring layer and the fourth poly-silicon wiring layer, between the second poly-silicon wiring layer and the fifth poly-silicon wiring layer, between the first poly-silicon wiring layer and sixth poly-silicon wiring layer, and between the fifth poly-silicon wiring layer and seventh poly-silicon wiring layer to be a same distance; setting all lengths of the first, second, third, fifth, and sixth poly-silicon wiring layers to be a same length; and setting all aspect ratios of the first, second, third, fifth, and sixth poly-silicon wiring layers to be more than 5.