Patent ID: 8383512

Claim:
A method, for use with a three-dimensional stacked IC device having a stack of at least 4 contact levels at an interconnect region, for creating interconnect contact regions aligned with and exposing landing areas at the contact levels, each contact level comprising a conductive layer and an insulation layer, the method comprising: removing at least a portion of any upper layer overlying the interconnect region to expose a first contact level and create contact openings for each contact level; selecting a set of N etch masks for creating a plurality of levels of interconnect contact regions at the stack of the contact levels, N being an integer equal to at least 2; using the N masks to etch the contact openings up to and including 2 N contact levels, the N masks using step comprising: using a first mask to etch one contact level for effectively half of the contact openings; using a second mask to etch two contact levels for effectively half of the contact openings; and the removing, selecting and using steps being carried out so that the contact openings extend to the 2 N contact levels; and whereby electrical conductors can be formed through the contact openings to contact the landing areas at the contact levels.