Patent ID: 7294854

Claim:
A thin film transistor array panel, comprising: an insulating substrate; a gate wire formed on the insulating substrate and including a gate line and a gate electrode connected to the gate line; a storage capacitor wire formed on the insulating substrate and having a storage capacitor electrode line and a storage electrode connected to the storage capacitor electrode line and located at an edge of a pixel area; a gate insulating film covering the gate wire and the storage capacitor wire; a semiconductor layer formed on the gate insulating film; a data wire formed on the gate insulating film or the semiconductor layer and including a data line intersecting the gate line to define the pixel area, a source electrode connected to the data line and located on the semiconductor layer, a drain electrode formed on the semiconductor layer and located opposite the source electrode with respect to the gate electrode, and a first storage capacitor conductor overlapping the storage electrode via the gate insulating film to form a storage capacitor; a pixel electrode electrically connected to the drain electrode and the first storage capacitor conductor; and, a protective layer formed between the pixel electrode and the drain electrode and the first storage capacitor conductor.