Patent ID: 7834406

Claim:
A high-voltage metal-oxide-semiconductor (MOS) device, comprising: a semiconductor substrate; a first ion well of first conductivity type formed in the semiconductor substrate; a first field oxide layer formed on the first ion well and enclosing a drain region of the high-voltage MOS device; a drain doping region with a second conductivity type being formed in the semiconductor substrate within the drain region; a second field oxide layer formed on the first ion well and enclosing a source region of the high-voltage MOS device, wherein a channel region is situated between the first and second field oxide layers; a source doping region with the second conductivity type being formed in the semiconductor substrate within the source region; a gate oxide layer provided on the channel region; a gate provided on the gate oxide layer; a third field oxide layer enclosing the first field oxide layer and the second field oxide layer, the third field oxide layer is not physically connected to both the first field oxide layer and the second field oxide layer with a device isolation region between the third field oxide layer and the first field oxide layer and between the third field oxide layer and the second field oxide layer; and a continuous, annular device isolation diffusion region of the first conductivity type formed in the first ion well within the device isolation region, the continuous, annular device isolation diffusion region comprising an extended portion bordering the channel region.