Patent ID: 7525141

Claim:
A memory array comprising: a semiconductive substrate; a plurality of conductive data/bit lines extending generally in a first direction and formed in an upper surface of the substrate; a plurality of access transistors extending generally upward from the upper surface of the substrate and aligned generally atop a corresponding data/bit line, wherein the access transistors comprise: a pillar extending generally upward from the upper surface of the substrate and generally aligned atop the corresponding data/bit line wherein a source region is formed generally at a lower portion of the pillar so as to be in electrical communication with the corresponding data/bit line and a drain region is formed generally at an upper portion of the pillar, wherein the pillar intermediate the source and drain regions is substantially fully depleted and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar such that the transistors are substantially off with no applied gate potential; and a plurality of conductive word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a lateral extent about the corresponding pillar via the surround gate structure.