Patent ID: 7934187

Claim:
A method of performing electrical rule checks (ERCs) on a circuit design, comprising: creating a hierarchy of cells from a schematic database or netlist for the circuit design; traversing the hierarchy to identify master nets, the master nets being associated with shorted nets in the circuit design; traversing the hierarchy to identify ERC nets, the ERC nets being associated with effectively shorted nets in the circuit design, the effectively shorted nets including the shorted nets and nets each of which is connected to a source of a transistor or a drain of the transistor but not connected to each other; and performing, using a computer, at least one ERC on the circuit design by analyzing properties of the master nets and ERC nets, wherein the ERC nets do not include a ground net, wherein each of the master nets includes combined attributes of the respective shorted nets associated therewith, and wherein each of the ERC nets includes combined attributes of the respective effectively shorted nets associated therewith; wherein the performing comprises: executing at least one hierarchical ERC using the root nets; wherein each of the root nets is a particular one of the master nets or a particular one of the ERC nets having only pin connections and no port connections.