Patent ID: 7676708

Claim:
A semiconductor integrated circuit with full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM) at internally doubled clock testing application comprising: a pulse generator having an output attached to a clear input of a self-toggling circuit, and having an input which is a write line from a memory controller, a synchronous multi-bit adder having N data input lines coupled to summation outputs through N feedback lines of said multi-bit adder, wherein said multi-bit adder having N additional inputs which are forced to (0, 0 . . . 1), a clock input and a clear input, an exclusive-OR circuit having one input which comes from said true output of said self-toggling circuit, having another input which is a select signal and having an output which is an external select signal, and a multiplexer circuit having one input which is the positive data input-bit, having another input which is the negative data-input bit which is the inverse of said positive data input bit, having a select line which is said external select line from said exclusive-OR circuit, having one output which is a data input-even bit and having another output which is a data input-odd bit, wherein said integrated circuit provides full-speed testing of said synchronous dynamic random access memory (SDRAM).