Patent ID: 7694035

Claim:
A parallel computer system comprising a network of interconnected compute nodes, wherein each compute node comprises: at least one processor a memory; and a DMA engine comprising a processor interface for interfacing with the at least one processor, DMA logic, a memory interface for interfacing with the memory, a DMA network interface for interfacing with the network, injection and reception byte counters, injection and reception FIFO metadata, and status registers and control registers; wherein the injection FIFO metadata maintains memory locations of the injection FIFO memory locations, including its current head and tail, and the reception FIFO metadata maintains the reception FIFO memory locations, including its current head and tail, wherein the injection byte counters and reception byte counters may be shared between messages, wherein a processor at the compute node increments the counter value maintained in the shared byte counter by the current message length, and the DMA engine atomically carries out the increment operation such that immediately after, the shared byte counter contains a sum of the number of bytes to be injected or received, minus the number of bytes already injected or received, and wherein to receive a long message at a target compute node, the target compute node's DMA engine operates first on at least one short protocol message received by the DMA engine and stored in its reception FIFO to establish protocol between the source compute node of the long message and the target compute node and to establish injection/reception byte counters in a DMA engine at the target compute node that will be used to maintain the long message base offsets.