Patent ID: 8352385

Claim:
A microchip performing a neural decoding algorithm, said microchip implemented using ultra-low power electronics comprises: a tunable neural decodable filter implemented using a plurality of amplifiers; a plurality of parameter learning filters; a multiplier, wherein linear capacitors at the output of said multiplier integrate output currents to form voltage signals which are used to set bias voltages through gain and time-constant biasing circuits, wherein said bias voltages set the gain and time constant of said tunable neural decodable filter; and analog memory, wherein said microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons into motor control parameters, said optimized translation being based on a modified gradient descent least square algorithm wherein update for a given parameter in a filter is proportional to an averaged product of an error in the final output that the filter affects and a filtered version of its input; and said microchip, in operational mode, issues commands to control a device using learned mappings.