Patent ID: 8411527

Claim:
A memory device, comprising: an array of memory cells coupled between a virtual ground node and a supply node; a first transistor and a second transistor coupled in source-drain parallel to one another between the virtual ground node and a ground bus; wherein the first transistor is substantially larger than the second transistor; a control circuit coupled to provide a first gate signal to a gate of the first transistor and further coupled to provide a second gate signal to a gate of the second transistor; wherein the control circuit includes: a first configuration memory cell coupled to provide a first control signal; an interconnect coupled to provide a second control signal; and first control logic coupled to receive the first control signal and the second control signal, and further coupled to provide the first gate signal; and wherein the array of memory cells has three modes responsive to the first gate signal and the second gate signal, the three modes including an active mode, a first sleep mode, and a second sleep mode.