Patent ID: 8710893

Claim:
A method for generating a low jitter low-speed clock, comprising: step A: selecting a time delay Δt for delaying the high-speed clock cycles; step B: according to the frequency f H of the high-speed clock cycles, the frequency f L of the current low-speed clock cycles, the frequency f Q of the targeted low-speed clock cycles to be obtained after the frequency division is performed, and the time delay Δt got from the step A, calculating the time interval T between two adjacent insertions of the time delay Δt in the high-speed clock cycles, the total number N of the time delay Δts required to be inserted, and times of the multiples of frequency division; step C: within each time frame corresponding to a low-speed clock cycle, inserting a time delay Δt in a single period of high-speed clock cycles at the time interval T until number N time delay Δts are inserted; step D: according to the times of the multiples of frequency division from the step B, performing the frequency division operation on the high-speed clock cycles from the step C to obtain the low jitter low-speed clock cycles.