Patent ID: 7395294

Claim:
An arithmetic logic unit that receives a plurality of operands, each of the plurality of operands being received from a single one of a plurality of operand registers, the unit that performs an arithmetic operation on the operands, that obtains a result of the arithmetic operation and that transmits the result to a result register, comprising: a plurality of logic elements; a first signal propagation path from at least a first one of the operand registers, through at least a first portion of the plurality of logic elements and into the result register, the first signal propagation path including no more than a single multiplexer between the at least one operand register and the result register, the single multiplexer being immediately adjacent to the at least one operand register, the first signal propagation path performing a first arithmetic operation on data received from the first one of the operand registers to produce a first processed result for storage in the result register; and a second signal propagation path from at least a second one of the operand registers through at least a second portion of the plurality of logic elements and into the result register, the second path including a plurality of multiplexers coupled in series, the second signal propagation path performing a second arithmetic operation on data received from the second one of the operand registers to produce a second processed result for storage in the result register; wherein the first and second paths are coupled to the result register via a single exclusive OR (XOR) gate.