Patent ID: 6971041

Claim:
A method comprising: retrieving a cache entry for a desired memory address, the cache entry including data and a stored error-correcting code (ECC) based at least on the data and a memory address; determining an ECC based on at least the data of the cache entry and the desired memory address; upon determining that the ECC based at least on the data of the cache entry and the desired memory address equals the stored ECC, concluding that the cache entry caches the desired memory address without error; otherwise, retrieving a second cache entry for the desired memory address the cache entry including second data and a second stored ECC based at least on the second data and a second memory address; determining a second ECC based at least on the second data of the second cache entry and the desired memory address; and, upon determining that the second ECC based at least on the second data of the second cache entry and the desired memory address equals the second stored ECC, concluding that the second cache entry caches the desired memory address without error.