Patent ID: 7724843

Claim:
A radio signal decoder comprising: a front-end module operably coupled to, when enabled, convert a received radio signal into digital data in accordance with a rate of a receive clock, wherein the received radio signal includes data at a transmit rate; and a baseband processing module operably coupled to process the digital data and to produce therefrom output digital data, wherein the baseband processing module includes: a processing module; and memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to: determine an error term between the rate of the receive clock and the transmit rate by: recovering a pilot tone from the received signal; generating a simulated pilot tone based on the receive clock; mixing the simulated pilot tone with the recovered pilot tone to produce a mixed signal; producing a difference of the simulated pilot tone and the recovered pilot tone based on the mixed signal; and producing the error term based on the difference; determine whether the error term is within an error tolerance; and when the error term is not within the error tolerance, adjust the rate of the receive clock based on the error term to produce an adjusted receive clock rate.