Patent ID: 8392630

Claim:
An information processing apparatus having a first control circuit including a first volatile memory and a first DMA controller, and a second control circuit including a second volatile memory and a second DMA controller, the first DMA controller and the second DMA controller being capable of respectively executing data transfers between the first volatile memory and the second volatile memory in both a first direction from the first volatile memory to the second volatile memory and a second direction from the second volatile memory to the first volatile memory, the apparatus comprising: an acquisition unit that acquires a request for a data transfer executed between the first volatile memory and second volatile memory; an analyzing unit that analyzes whether the data transfer should be executed in either the first direction or the second direction, based on the request acquired by the acquisition unit; a selecting unit that selects the first DMA controller, in a case where the first DMA controller has a data transfer rate that is faster than a data transfer rate of the second DMA controller, when the data transfer is executed between the first volatile memory and the second volatile memory in a direction analyzed by the analyzing unit, and that selects the second DMA controller, in a case where the second DMA controller has a data transfer rate that is faster than a data transfer rate of the first DMA controller when the data transfer is executed between the first volatile memory and the second volatile memory in a direction analyzed by the analyzing unit; and a control unit that exercises control in such a manner that the data transfer is executed by the first control circuit if the first DMA controller is selected by the selecting unit and is executed by the second control circuit if the second DMA controller is selected by the selecting unit.