Patent ID: 7372500

Claim:
An image signal processor configured to process a first image signal that is generated by a solid-state imaging device, and to generate a second image signal having a format, the image signal processor comprising: a first regulator configured to receive a power supply voltage that corresponds to an input level of an external device, and to generate a first regulated voltage that is lower than the power supply voltage and that corresponds to an output level of the solid-state imaging device; a signal processing circuit configured to operate with the first regulated voltage, the signal processing circuit being configured to perform signal processing on the first image signal and to generate the second image signal; an output circuit configured to operate with the power supply voltage, the output circuit being configured to receive the second image signal and to forward the second image signal along a path to the external device; wherein the image signal processor is on a chip semiconductor substrate, and wherein the first regulator is configured to stop generating the first regulated voltage during at least part of a time when (i) the solid-state imaging device stops operating and (ii) the output circuit receives the power supply voltage; and a second regulator configured to receive the power supply voltage and to generate a second regulated voltage; wherein the signal processing circuit comprises: an analog processing circuit configured to operate with the first regulated voltage, the analog processing circuit being configured to perform analog signal processing on the first image signal; and a digital processing circuit configured to operate with the second regulated voltage, the digital processing circuit being configured to generate the second image signal by performing digital signal processing on a digital first image signal that corresponds to the first image signal after analog signal processing; wherein the second regulator is configured to stop generating the second regulated voltage during at least part of a time when (i) the solid-state imaging device stops operating and (ii) the output circuit receives the power supply voltage.