Patent ID: 7767533

Claim:
A method of forming a semiconductor device, comprising: forming a gate pattern on a substrate including a device isolation pattern provided to define an active region, the gate pattern crossing over the active region and being disposed on the device isolation pattern; forming a first doped region and a second doped region in the active region adjacent to opposite sides of the gate pattern, respectively; sequentially forming a gate spacer and a sacrificial spacer on both sidewalls of the gate pattern; forming an interlayer dielectric on the entire surface of the substrate; planarizing the interlayer dielectric to expose the gate spacer and the sacrificial spacer; removing a portion of the sacrificial spacer to form a groove to expose the first doped region, forming the groove including: forming a mask pattern with an opening on the substrate, the opening being provided to expose a portion of the sacrificial spacer disposed on the first doped region and the mask pattern covering another portion of the sacrificial spacer disposed on the device isolation pattern; and removing the exposed portion of the sacrificial spacer by using the mask pattern as an etch mask; and forming a contact structure in the groove.