Patent ID: 7961012

Claim:
An apparatus for preventing a glitch in a clock switching circuit, the apparatus comprising: a clock gate unit having a plurality of clock gates; a select signal manager for generating a detect change signal (Detect_change) based on a level of a select signal SEL being input to the select signal manager, for providing the detect change signal to each clock gate as an input signal for generating the respective clock gate signal, and for generating a muxsel signal based on all the clock gate signals to a signal input to the select signal manager for toggling a logic value of the muxsel signal based on a comparison with the select signal, for selecting a particular clock for switching; and said each clock gate for gating a received clock, for generating the clock gate signal using a level of the detect change signal received as an input signal to said clock gate, and for providing the generated clock gate signal to the select signal manager according to the received detect change signal: and a clock selector for, prior to receiving the muxsel signal changed into a select signal from the select signal manager, outputting a clock gated by the clock gate unit and, when receiving the muxsel signal, switching to a clock based on the received muxsel signal; wherein an output of each respective clock gate of the plurality of clock gates is input to a respective input of the clock selector such that the select signal manager generates an updated muxsel signal having a same logic level as the select signal.