Patent ID: 7006387

Claim:
A memory device, comprising: a switch array comprising a plurality of first switches for connecting a lower byte region of a data I/O buffer to a lower byte region of a sense amplifier array, a plurality of second switches for connecting the lower byte region of a data I/O buffer to an upper byte region of the sense amplifier array, and a plurality of third switches for connecting an upper byte region of the data I/O buffer to the upper byte region of the sense amplifier array; and a switch controller for receiving external control signals to control activation of the data I/O buffer and on/off operations of the first through the third switches, wherein the switch controller turns on the first switch and activates the lower byte region of the data I/O buffer connected to an I/O port when a lower byte signal included in the external control signals is activated, and turns on the third switch and activates the upper byte region of the data I/O buffer connected to an I/O port when an upper byte signal included in the external control signals is activated.