Patent ID: 7143306

Claim:
A system interface comprising: (a) a cache memory; (b) a plurality of directors, each one of the plurality of directors comprising: (i) a data pipe coupled between an input of such one of the directors, such data pipe comprising: (A) a data pipe memory; (B) a data pipe memory controller for controlling the data pipe memory; and (ii) a microprocessor coupled to the data pipe memory controller; (c) a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors each one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.