Patent ID: 8153491

Claim:
A method of forming a memory cell comprising: providing a silicon substrate having a main surface; forming a source region in a portion of the silicon substrate proximate the main surface; forming a drain region in a portion of the silicon substrate proximate the main surface, the drain region being spaced apart from the source region; depositing a bottom oxide layer on the main surface of the substrate, the bottom oxide layer disposed on a portion of the main surface; forming a dielectric charge storage layer above the bottom oxide layer relative to the main surface of the silicon substrate; depositing a first dielectric oxide layer above, and contacting, the dielectric charge storage layer relative to the main surface of the silicon substrate; depositing a dielectric nitride layer above, and contacting, the first dielectric oxide layer relative to the main surface of the silicon substrate; depositing a second dielectric oxide layer above, and contacting, the dielectric nitride layer relative to the main surface of the silicon substrate; and forming a control gate above the second dielectric oxide layer relative to the main surface of the silicon substrate; wherein the bottom oxide layer is between about 30-90 Angstroms (Å) in thickness, the charge storage layer is between about 50-150 Å in thickness, and each of the first and second dielectric oxide layers and the dielectric nitride layer is between about 10-30 Å in thickness.