Patent ID: 7495295

Claim:
A semiconductor device comprising: a first insulated gate transistor; a second insulated gate transistor having a power source voltage higher than a power source voltage of the first insulated gate transistor; and a third insulated gate transistor having a power source voltage higher than a power source voltage of the second insulated gate transistor, wherein the first insulated gate transistor has a first gate insulating film formed on a first region of a semiconductor substrate of a first conductivity type, a first gate electrode formed on the first gate insulating film, first extension regions of a second conductivity type formed in parts of the first region of the semiconductor substrate which are located in both sides of the first gate electrode, and first source/drain regions of a second conductivity type provided in regions of the first region of the semiconductor substrate which are located externally of the first extension regions, the second insulated gate transistor has a second gate insulating film formed on a second region of the semiconductor substrate, a second gate electrode formed on the second gate insulating film, second extension regions of a second conductivity type formed in parts of the second region of the semiconductor substrate which are located in both sides of the second gate electrode, and second source/drain regions of a second conductivity type provided in regions of the second region of the semiconductor substrate which are located externally of the second extension regions, the third insulated gate transistor has a third gate insulating film formed on a third region of the semiconductor substrate, a third gate electrode formed on the third gate insulating film, LDD regions of a second conductivity type formed in parts of the third region of the semiconductor substrate which are located in both sides of the third gate electrode, and third source/drain regions of a second conductivity type provided in regions of the third region of the semiconductor substrate which are located externally of the LDD regions, a thickness of the second gate insulating film is larger than a thickness of the first gate insulating film and substantially the same as the thickness of the third gate insulating film, the deepest junction depth of the second extension regions measured from the surface of the semiconductor substrate is smaller than the deepest junction depth of the LDD regions measured from the surface of the semiconductor substrate, and substantially the same as the deepest junction depth of the first extension regions measured from the surface of the semiconductor substrate, a peak concentration of the second extension regions is higher than a peak concentration of the LDD regions and substantially the same as a peak concentration of the first extension regions, and the first region, the second region and the third region are isolated by isolation regions provided in the semiconductor substrate.