Patent ID: 7888981

Claim:
A semiconductor integrated circuit comprising a clock generating section having a digital control delay unit operable to delay a reference signal thereby to generate a delay clock signal, and a digital control part operable to control at least one of a phase and frequency of the delay clock signal generated by the digital control delay unit, wherein the clock generating section includes a comparator, a control register and an output buffer, when the delay clock signal generated by the digital control delay unit is supplied to an input terminal of the output buffer, an output clock signal arises from an output terminal of the output buffer, the reference signal is supplied to one input terminal of the comparator, and the output clock signal arising from the output buffer is supplied to the other input terminal of the comparator, when the control register is supplied with an output signal of the comparator, the control register stores two or larger bits of digital control information for controlling the digital control delay unit, the comparator, control register and digital control delay unit constitute a delay locked loop, when the control register stores digital control information having a predetermined value, at least one of a phase and frequency of the output clock signal at the other input terminal of the comparator is locked to at least one of a phase and frequency of the reference signal at the one input terminal of the comparator, the delay locked loop can work in two or more operation conditions by setting two or more frequencies for the reference signal or setting two or more delay amounts for the output buffer, the delay locked loop works in one operation condition selected from among the two or more operation conditions by setting one frequency selected from among the two or more frequencies for the reference signal, or setting one delay amount selected from among the two or more delay amounts for the output buffer, the clock generating section further includes a control data storing circuit connected with the control register, sets of initial set data for operation by the delay locked loop in the two or more operation conditions can be stored in the control data storing circuit in advance, operation select information for selecting the one operation condition is supplied to the control data storing circuit prior to an operation by the delay locked loop in the one operation condition, and initial set data for the operation in the one operation condition is stored at an upper bit of the control register from the control data storing circuit in response to the operation select information.