Patent ID: 8065536

Claim:
A data processing system comprising a high-performance computing subsystem having high power consumption (HP subsystem), a low-performance computing subsystem having lower power consumption (LP subsystem) than said HP subsystem, and a controller comprising a set of interfaces to said HP subsystem, said HP subsystem comprising a first operating system, a first main processor, a first graphical processor and a first storage; said LP subsystem comprising a second operating system, a second main processor, a second graphical processor and a second storage; and wherein said LP subsystem is operatively in close integration to said controller, and arranged to boot in an initial step from off ( 200 ) to power-on ( 205 ), keeping said HP sub-system powered-off ( 210 ) and to enter ( 215 ) a wait state ( 220 ), alternatively a state of standby ( 290 ) when an inactivity timeout occurs ( 289 ) and to return to said wait state ( 220 ) on a wake-up event ( 291 ); is configured to control said data processing system to act as a single computing device by moving software execution to one of a) said HP subsystem when high computing performance is needed ( 225 ) by booting said HP subsystem ( 230 , 235 ) into a booted state ( 240 ), transferring control of user interface means to said HP subsystem and running said software to be executed ( 245 , 250 , 255 , 260 ), b) said LP subsystem when low computing performance is sufficient, by transferring control of user interface means to said LP sub-system, stopping said software to be executed, releasing resources ( 270 , 275 ); allowing in case b) to put said HP subsystem into a power saving mode finally arriving at step ( 280 , 285 , 220 ).