Patent ID: 8823604

Claim:
A display device comprising: a pixel array part configured to include scan lines disposed along rows, signal lines disposed along columns, and pixels disposed at intersections of the scan lines and the signal lines; and a drive part configured to have at least a write scanner that sequentially supplies a control signal to the scan lines and a signal selector that supplies a video signal to the signal lines, wherein each of the pixels includes at least a sampling transistor, a drive transistor, a holding capacitor, and a light-emitting element, the sampling transistor is connected between the signal line and the drive transistor, the drive transistor is connected to the light-emitting element and a power supply, the sampling transistor is turned on in response to the control signal supplied to the scan line to thereby sample the video signal from the signal line and write the video signal to the holding capacitor, and the sampling transistor carries out negative feedback of a current that flows from the drive transistor to the holding capacitor to thereby write a correction amount dependent upon mobility of the drive transistor to the holding capacitor in a predetermined correction period until the sampling transistor is turned off in response to a control signal, the drive transistor supplies, to the light-emitting element, the current dependent upon the video signal and the correction amount written to the holding capacitor to thereby cause the light-emitting element to emit light, the write scanner supplies the control signal including at least double pulses to the scan line to thereby set a first correction period, a second correction period, and a correction intermediate period between the first correction period and the second correction period, the first correction period ends and the correction intermediate period starts at a first time and at a second time, the correction intermediate period ends and the second correction period starts, the sampling transistor is turned on during the first correction period and the second correction period, the sampling transistor is turned off throughout the correction intermediate period, the sampling transistor carries out writing of the correction amount to the holding capacitor in the first correction period and accelerates the writing of the correction amount to the holding capacitor in the correction intermediate period, and the sampling transistor settles the writing of the correction amount to the holding capacitor in the second correction period, and a difference between the first time and the second time is shorter for a correction for black level than for a correction for white level.