Patent ID: 8760381

Claim:
A display device comprising: an array substrate comprising pixels arranged in a matrix manner; and a plurality of gate control circuits that scan gate lines of the pixels that are provided on the array substrate such that each gate control circuit from the plurality of gate control circuits corresponds to a respective gate line of the pixels, wherein each gate control circuit from the plurality of gate control circuits comprises a first output terminal that outputs a signal to each of the gate lines, and a second output terminal that outputs a signal that is supplied to another gate control circuit from the plurality of gate control circuits wherein a first gate control circuit from the plurality of gate control circuits is cascade connected via the second output terminal to a second gate control circuit, wherein the second gate control circuit corresponds to a gate control circuit at a predetermined number of gate lines from the respective each of the gate control circuits, wherein the predetermined number of gate lines is based on state of a mode signal, and wherein when two gate lines are scanned simultaneously for writing image data by the signal output from the first output terminal of each of the gate control circuits, a gate on period is provided during which outputs from the first output terminals of two gate control circuits are the same.