Patent ID: 8168500

Claim:
A method of manufacturing a semiconductor structure comprising: forming a shallow trench including a first shallow trench portion and a second shallow trench portion in a semiconductor substrate, wherein said first shallow trench portion and said second shallow trench portion are separated by a first surface region of a semiconductor top surface; forming a stack of a body layer, a bottom electrode layer, and a primary isolation well layer, wherein said body layer is located directly beneath said first surface region, a second surface region directly adjoining said second shallow trench portion, and a bottom surface of said second shallow trench portion, and wherein said bottom electrode layer is located directly beneath said body layer, and wherein said primary isolation layer is located directly beneath said bottom electrode layer, and wherein said bottom electrode layer has a doping of a first conductivity type, and wherein each of said body layer and said primary isolation well layer has a doping a second conductivity type, and wherein said second conductivity type is the opposite of said first conductivity type; forming a shallow trench isolation (STI) structure including a first STI portion formed in said first shallow trench portion and a second STI portion formed in said second shallow trench portion; and forming a gate dielectric and a top gate electrode by patterning a stack of a gate dielectric layer and a gate electrode layer, wherein said gate dielectric is formed on a portion of said first surface region and said second STI portion.