Patent ID: 7514292

Claim:
A method for fabricating a semiconductor device including a semiconductor chip having first and second surfaces, comprising the steps of: forming an integrated circuit on said first chip surface, said circuit including active components, at least one metal layer, and a mechanically strong, electrically insulating protective overcoat; forming a plurality of vias through said overcoat to access said at least one metal layer; filling said vias by depositing a stack of metal films on said overcoat, said stack having at least one stress-absorbing film and an outermost film being non-corrodible and metallurgically attachable; patterning said films into a network of lines such that said lines are located substantially vertical over said active components, thus providing power current distribution while minimizing parasitic electrical losses between said network and said active components; forming a plurality of windows in said overcoat to expose circuit contact pads; providing a pre-fabricated leadframe comprising a chip mount pad, a first plurality of segments suitable for electrical signals, and a second plurality of segments suitable for electrical power and ground; attaching said chip to said chip mount pad; attaching electrical conductors to said circuit contact pads and said first plurality of segments; and attaching electrical conductors to said network of lines and said second plurality of segments.