Patent ID: 7880304

Claim:
An integrated circuit chip comprising: a silicon substrate; a first internal circuit in and on said silicon substrate; a second internal circuit in and on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, wherein said first interconnecting structure comprises a copper line and a first adhesion layer at a bottom and a sidewall of said copper line of said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a layer of nitrogen-containing compound; a first via in said passivation layer, wherein said first via is connected to said first internal circuit through said first interconnecting structure, wherein said first via comprises aluminum in said passivation layer; a second via in said passivation layer, wherein said second via is connected to said second internal circuit through said second interconnecting structure; and a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a thickness between 2 and 100 micrometers, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer and an electroplated metal layer on said seed layer, wherein said second adhesion layer is under a bottom of said electroplated metal layer, but is not at a sidewall of said electroplated metal layer.