Patent ID: 8207032

Claim:
A method of a forming a plurality of vertical transistors, comprising: forming a construction to comprise a plurality of spaced apart fins extending upwardly from a semiconductor substrate, each of said fins comprising vertical transistor pillars alternating with dielectric material pillars; the vertical transistor pillars comprising semiconductor material; each of the vertical transistor pillars having three segments along a vertical axis of the pillar with said three segments being a bottom source/drain segment, a channel segment over the bottom source/drain segment, and a top source/drain segment over the channel segment; and forming electrically conductive gate material along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain segments of the vertical transistor pillars; the oxide being an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature.