Patent ID: 7745274

Claim:
A method of forming a junction field effect transistor (JFET), comprising: forming a bottom gate region having a first electrical conductivity type in a semiconductor substrate; forming an epitaxial layer having a second electrical conductivity type over the semiconductor substrate; forming well regions having the first electrical conductivity type in the epitaxial layer down to the bottom gate region; forming a layer of gate dielectric material over the epitaxial layer; forming a layer of gate electrode material over the layer of gate dielectric material; patterning the layer of gate electrode material to form a plurality of patterned gate electrode material structures over the epitaxial layer over the bottom gate region; forming sidewall spacers adjacent to the patterned gate electrode material structures; forming a top gate region having the first electrical conductivity type in the epitaxial layer over the bottom gate region, in self-alignment between ones of the sidewall spacers of adjacent ones of the patterned gate electrode material structures; and forming source and drain regions having the second electrical conductivity type in the epitaxial layer over the bottom gate region, in self-alignment with respective other ones of the sidewall spacers of the patterned gate electrode material structures, the top gate region being situated between the source region and the drain region.