Patent ID: 7315574

Claim:
A system for generating a jittered signal, comprising: a jitter generator for providing a jittered test signal to a circuit under test, said jitter generator comprising: a) a jitter injector operatively configured to inject jitter into a reference signal having a first frequency so as to generate a first jittered signal, wherein said jitter injector comprises a timing error generator, a static delay generator and a switch operatively configured for switching between said timing error generator and said static delay generator; b) a frequency sealer operatively configured to multiply said first jittered signal by a frequency multiplier so as to generate said jittered test signal having a second frequency higher than said first frequency; and c) an output for providing said jittered test signal to a circuit under test when the circuit under test is in communication with said jitter generator and the circuit under test is being tested using said jitter generator.