Patent ID: 8064236

Claim:
A multi-rank memory module comprising: a module substrate; a data bus provided on said module substrate; a plurality of synchronous memory chips each including a data input/output pad connected via an interconnection to said data bus, an enclosed terminal resistance that terminates connection to said data bus, and a terminal resistance control pad for inputting a signal that controls the on/off of said enclosed terminal resistance; said synchronous memory chips being provided in terms of a rank as a unit of said memory chips to which a command is afforded independently from outside; a number of terminal resistance control terminals smaller than that of said ranks; and a number of terminal resistance control interconnects each provided on said module substrate in association with each of said terminal resistance control terminals; wherein a terminal resistance control pad for the memory chip out of said memory chips that has a shorter length of said interconnection is connected to a fixed potential to turn on said enclosed terminal resistance; and wherein a terminal resistance control pad of the memory chip out of said memory chips that has a longer length of the interconnection is connected to said terminal resistance control interconnect.