Patent ID: 7053614

Claim:
A controller for producing a sequence of states derived from an input bus, each said state comprising a plurality of independent variables realized as digital values, each said variable expressed in a corresponding digital precision and said state further characterized by duration, said controller comprising, (a) a plurality of latched registers for receiving and retaining corresponding datums from said input bus, (b) at least one latched mathematical register assembly for receiving and retaining corresponding datums from said input bus, said latched mathematical register assembly comprising a computational module for combining said datums in accord with a mathematical rule to yield a computed result datum, and a corresponding latched result register to retain said computed result datum, and (c) a plurality of FIFO portions, each portion in correspondence with one said latched register and latched result register, each said latched register and result register in corresponding relationship with one said FIFO portion, whereby a FIFO assembly comprising said FIFO portions contains a sequence of said states.