Patent ID: 7061286

Claim:
Circuitry comprising: a) a first sub-circuit clocked with a first clock and having an output; b) a second sub-circuit, clocked with a second clock having a frequency greater than the first clock, the second sub-circuit having an input; c) a synchronization circuit having an input coupled to the output of the first sub-circuit and an output coupled to the input of the second sub-circuit and a clock input coupled to the second clock, the synchronization circuit comprising: i) a clock divider producing a plurality of ordered clocks synchronized relative to the second clock, the plurality of ordered clocks having an order such that each clock has a longer period than the clock prior to it in the order; ii) a chain of latches having a data input and a data output and a plurality of clock inputs, each clock input coupled to a clock of the plurality of ordered clocks and the data input coupled to the output of the first sub-circuit.