Patent ID: 7634643

Claim:
A processor executing a plurality of instructions, comprising: an arithmetic logic unit (ALU); and a plurality of registers coupled to the ALU, each register programmable to store a register value; wherein said processor executes a routine having a test and skip instruction defined by an opcode, said test and skip instruction includes an immediate value and a register reference control bit contained within a source operand of the test and skip instruction, the test and skip instruction performs a comparison using the immediate value and the register value stored in the register referenced by the register reference control bit, and selectively skips a subsequent instruction that follows the test and skip instruction based on the comparison; wherein the register reference control bit specifies whether the register reference is to a register from a first group of registers or to a register from a second group of registers, and if a register from the first group of registers is specified by said register reference control bit, the comparison is performed by comparing the immediate value to the register value, and, if a register from the second group of registers is specified by said at least one register reference control bit, the comparison is performed by masking the register value with the immediate value and examining one or more bits in a masked version of the referenced register; and wherein the subsequent instruction jumps to another routine.