Patent ID: 7176758

Claim:
A multi-stage output buffer having a differential input and a differential output, comprising: an emitter follower circuit coupled to the differential input, and configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof; an emitter coupled pair circuit coupled to the output of the emitter follower circuit, wherein the emitter coupled pair circuit is configured to amplify the signal and further isolate an input circuit when coupled to the differential input of the multi-stage output buffer from an external load when coupled to the differential output thereof; a differential base-grounded configuration transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer, wherein the base-grounded configuration transistor circuit is configured to reduce a load impedance at the output of the emitter coupled pair circuit, thereby improving a speed and signal amplitude of the buffer; a bias current circuit coupled to the base-grounded configuration transistor circuit, and configured to provide a DC bias current to keep transistors in the base-grounded configuration transistor circuit from turning off when transistors in the emitter coupled pair circuit turn off, thereby further improving a speed, linearity and signal amplitude of the output buffer; and a first bias voltage generation circuit coupled to the emitter follower circuit, and configured to establish a first DC bias voltage at the input of the emitter follower circuit about which a differential signal varies.