Patent ID: 6927604

Claim:
A clock signal selector circuit, comprising: a synchronizer circuit coupled to receive a first clock signal and a first control signal corresponding to the first clock signal, and configured to synchronize the first control signal to the first clock signal thereby producing a second control signal; a first switching circuit coupled to receive the first clock signal and the second control signal, comprising an output terminal coupled to a first node, and configured to produce a first clock signal at the output terminal in the event the second control signal is asserted; a multiplexer coupled between the first node and a second node and to receive the second control signal, and configured to drive the second node with a signal at the first node in the event the second control signal is asserted; and a second switching circuit coupled between the first and second nodes and to receive the second control signal, and configured to form an electrical connection between the first and second nodes in the event the second control signal is deasserted.