Patent ID: 8301941

Claim:
A memory controller comprising: a write data buffer configured to store write data received from one or more write operations on an interconnect to which the memory controller is coupled, wherein the one or more write operations are sourced by one or more processors coupled to the interconnect; a plurality of drivers configured to drive first write data corresponding to a first write operation from the write data buffer to one or more memory modules that are capable of being coupled to the memory controller; a plurality of receivers configured to receive data from the one or more memory modules when the one or more memory modules are coupled to the memory controller during use, wherein each of the plurality of receivers is coupled to the respective one of the plurality of drivers; a first buffer; a controller that, in a loopback test mode of operation and in response to the first write operation, is configured to cause the first write data corresponding to the first write operation to be transmitted from the write data buffer through the plurality of drivers and the plurality of receivers, wherein the first write data is captured from the plurality of receivers in the first buffer, and wherein, in response to a first read operation sourced by the one or more processors and in response to a match in a comparison of a read address from the first read operation to addresses in the first buffer, the controller is configured to cause the first write data from the first buffer to be transmitted on the interconnect in response to the first read operation; a second plurality of drivers; and a second plurality of receivers, wherein the second plurality of drivers are configured to drive address bits to the one or more memory modules, and wherein the second plurality of receivers are configured to provide the address bits to the first buffer for storage in the loopback test mode, whereby a write address of the first write operation is stored in the first buffer in the loopback test mode after being driven through the second plurality of drivers and the second plurality of receivers.