Patent ID: 8442173

Claim:
A clock and data recovery system comprising: a sampler configured to sample a serial data stream having a plurality of data periods on at least one phase of a clock signal, wherein the sampler is configured to extract samples from the serial data stream, the samples comprising a data sample of one or more bits in the serial data stream and a transition sample of the one or more bits, wherein when the clock and data recovery system is in a locked state, the data sample is taken from a first interval into a data period and the transition sample is taken from a second interval into the data period, wherein the second interval is different from the first interval; a deserializer configured to convert at least one bit of the data sample to a deserialized data sample, and to convert at least one bit of the transition sample to a deserialized transition sample; a phase detector configured to receive the deserialized data sample and the deserialized transition sample, and to generate a phase error signal based at least partly on the deserialized data sample and the deserialized transition sample; and a frequency detector configured to receive the deserialized data sample and the deserialized transition sample, and to generate a frequency error signal based at least partly on the deserialized data sample and the deserialized transition sample, wherein the data sample comprises at least two bits taken from at least two data periods and the transition sample comprises at least two bits taken from the at least two data periods, and the deserializer is further configured to convert the at least two bits of the data sample to a deserialized data sample, and to convert the at least two bits of the transition sample to a deserialized transition sample.