Patent ID: 7902600

Claim:
A metal oxide semiconductor (MOS) device, comprising: a substrate having an N-type deep well and a plurality of isolation structures; a P-type well disposed in the N-type deep well, wherein the P-type well has a potential of ½ VDD; a gate structure disposed on the substrate and within the P-type well, wherein VDD is applied to the gate structure; a plurality of N-type extension region disposed in the P-type well, between the isolation structures and at either side of the gate structure; an N-type drain region and an N-type source region respectively disposed in the N-type extension regions and respectively disposed in the substrate at either side of the gate structure; and a P-type doped region disposed in the substrate and in the P-type well, wherein VDD is applied to the N-type drain region, the N-type source region and the P-type doped region are electrically connected to the P-type well having a potential of ½ VDD, so that the N-type source region and gate structure have a potential difference of ½ VDD, the N-type drain region and the N-type source region have a potential difference of ½ VDD, the N-type drain region and the P-type well have a potential difference of ½ VDD.