Patent ID: 7259049

Claim:
A method of forming a double-gate field effect transistor (DGFET) comprising: providing a structure which includes at least a doped back-plane region, a back-gate dielectric formed atop said doped back-plane region, a Si-containing layer formed atop said back-gate dielectric, a front gate dielectric formed atop said Si-containing layer, and a front gate formed atop said front gate dielectric, said structure having isolation trench regions adjacent to at least said doped back-plane region; forming first spacers having a first lateral width on exposed sidewalls of said front gate, said first spacers protecting portions of said underlying Si-containing layer from oxidation; forming isolation regions in regions of said structure which are adjacent to the back-gate dielectric and directly overlaying a portion of said doped back-plane region, whereby ledges are formed in said Si-containing layer under said first spacers; removing said first spacers and replacing the same with second spacers, said second spacers having a lateral width that is less than the first lateral width of said first spacers; selectively growing Si-containing regions above and in contact with said ledges, wherein said Si-containing regions are also above portions of the isolation regions; and forming source/drain regions in said Si-containing regions.