Patent ID: 6995058

Claim:
A method of manufacturing a semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor which comprises a vertically stacked structure having at least a lower electrode, a ferroelectric thin film, and an upper electrode, comprising the steps of: providing an adhesive layer containing a material on a principal surface of a substrate; stacking the lower electrode in its entirety on the adhesive layer, the lower electrode being polycrystalline such that (111) faces of crystal grains are oriented in a direction substantially perpendicular to a plane of the principal surface of said substrate; producing an initial nuclei layer of the material for promoting formation of micro-nuclei on an entire upper surface of the lower electrode by diffusing atoms of the material contained in the adhesive layer through the lower electrode from said adhesive layer, disposed between the lower electrode and the substrate, during a heat-treatment of the stacked layers including the lower electrode, after the lower electrode has been formed on the adhesive layer, said heat-treatment being performed at a temperature ranging from 300° C. to 1000° C.; forming crystal grains of said ferroelectric thin film on the entire upper surface of the lower electrode including said produced initial nuclei layer, wherein said crystal grains have columnar shapes elongated substantially in parallel to a thickness direction of said ferroelectric thin film and have (111) faces oriented substantially in said thickness direction by growing the crystal grains of said ferro electric thin film so as to succeed said (111) faces of crystal grains of the lower electrode based on said produced micro-nuclei; and forming said upper electrode on said formed crystal grains.