Patent ID: 8542535

Claim:
A method for performing an erase operation for erasing a set of non-volatile storage elements which is formed on a substrate, the set of non-volatile storage elements comprises one or more sets of series-connected non-volatile storage elements, each set of series-connected non-volatile storage elements is arranged between respective select gates, the method comprising: in a first time period, ramping up an erase voltage which is applied to the substrate from a non-zero initial level to a first level, and ramping up a voltage of at least one of the respective select gates from a non-zero starting level to a higher level in correspondence with the ramping up of the erase voltage, the ramping up the voltage of the at least one of the respective select gates comprises ramping up a voltage of a respective select gate driver of the at least one of the respective select gates from the non-zero starting level to the higher level while maintaining a pass gate which is between the respective select gate driver and the at least one of the respective select gates in a conductive state; and in a second time period which follows the first time period, driving the erase voltage at the first level while driving the voltage of the at least one of the respective select gates at the higher level, the driving the voltage of the at least one of the respective select gates at the higher level comprises driving the respective select gate driver at the higher level while maintaining the pass gate in the conductive state.