Patent ID: 7126858

Claim:
A method for emulating asynchronous clear on a read address register of a memory cell, comprising: connecting a first register to a read address input of a first memory cell, wherein the first register does not include an asynchronous clear connection; connecting a data output of the first memory cell to a first input of a multiplexer; connecting a read address input of a second memory cell to a ground signal; connecting a data output of the second memory cell to a second input of the multiplexer; generating a select signal to have a state opposite that of an asynchronous clear signal; and using the select signal to control the multiplexer, wherein a non-asserted state of the select signal causes the multiplexer to output data received at the second input of the multiplexer from the data output of the second memory cell, wherein an asserted state of the select signal causes the multiplexer to output data received at the first input of the multiplexer from the data output of the first memory cell.