Patent ID: 8560925

Claim:
A device configured to correct bad bit errors comprising: a solid-state nonvolatile memory device divided into a plurality of blocks, each block containing a plurality of pages, each page having a main area that stores substantive data and a spare area, and each spare area having a validity bit field indicating whether a bit in the main area is in an error state, a bad bit location field indicating the bit in the main area that is in the error state, a preferred value field indicating a likely value of the bit in the main area that is in the error state, and a user value field indicating a correct value of the bit in the error state; a main controller that performs at least one function of the device including: a bad bit detection module that receives an old page from the solid state nonvolatile memory device and determines whether a page has a detected bit in an error state; a bad bit correction module that: a) generates a new page to be written to the solid-state nonvolatile memory device, b) determines a location of the detected bit in the error state and records the location of the detected bit in the error state in a bad bit field of the new page, c) determines a preferred value of the detected bit in the error state and records the preferred value of the detected bit in the error state in a preferred value field of the new page, d) determines a user value of the detected bit in the error state and records the user value of the detected bit in the error state in a user value field of the new page, e) inserts the preferred value into a string of bits corresponding to substantive data recorded in a main area of the old page, and recording the string of bits with the preferred value inserted therein in a main area of the new page, and f) stores the new page at an address of the old page.