Patent ID: 8566524

Claim:
A computer implemented method for executing an atomic instruction group (AIG), the method comprising: executing, by a processor, an AIG instruction of the AIG of a thread, the AIG instruction configured to access data at a location in a memory of a computing system, the execution comprising: determining, by the processor, whether a flag associated with the location in the memory is enabled, wherein each increment of the memory has an associated flag, wherein an enabled flag indicates an associated memory is associated with an AIG; based on the flag not being enabled, performing: enabling the flag; storing information in a transaction table that is part of a real system memory of the computing system, the information identifying the location in the memory having the enabled flag; and accessing data at the location in the memory; and based on the flag being previously enabled, performing: absent the location being identified in the transaction table, preventing accessing data at the location in the memory; based on the location being identified in the transaction table, accessing data at the location in the memory, the accessing comprising: based on the accessing being a store to the memory, saving a current value of the memory as an old entry in a buffer and storing new data to the location in the memory, the buffer being any one of a cache entry of a cache or a transaction table entry of the transaction table, the saving the current value further comprising: based on the cache having an available location for the current value, saving the current value in the cache; and absent the cache having an available location for the current value, saving the current value in the transaction table as the old entry.