Patent ID: 8180820

Claim:
A circuit for generating a plurality of remainders from divisions of a corresponding plurality of dividend polynomials by a divisor polynomial, comprising: a plurality of first sub-circuits, each adapted to generate a respective intermediate polynomial as a function of a respective one of the dividend polynomials, and generate a respective first partial remainder for a polynomial division of the respective intermediate polynomial by a multiple of the divisor polynomial; a multiplexer adapted to select one of the first partial remainders along with a least significant portion of a corresponding one of the dividend polynomials; a first adder adapted to generate a sum of the least significant portion and a most signification portion of the one of the first partial remainders; a second sub-circuit adapted to generate a second partial remainder for a polynomial division by the divisor polynomial of a scaling of the sum; and a second adder adapted to generate the remainders by adding the second partial remainder and the one of the first partial remainders excluding the most significant portion.