Patent ID: 8558319

Claim:
A semiconductor memory device comprising: a substrate having a first surface and a second surface spaced apart from the first surface, wherein the substrate comprises a plurality of isolation structures, wherein a height of the central portion of each of the isolation structures with respect to the second surface of the substrate is lower than a height of side portions of each of the isolation structures, and each of the isolation structures comprises a dielectric material; and a plurality of active regions, wherein each of the active regions is spaced apart from another active region by one of the isolation structures; and a plurality of rows of memory cells provided on the first surface of the substrate, wherein the semiconductor memory device comprises a substantially continuous and smooth surface between the top of each of the active regions and the side portion of the adjacent isolation structures, and in a cross-section of the substrate between two rows of memory cells in a direction parallel to the two rows of memory cells, a maximum height of each isolation structure with respect to the second surface of the substrate is lower than or equal to minimum heights of active regions adjacent thereto.