Patent ID: 7250896

Claim:
A method for pipelining an analog-to-digital conversion of an analog input signal into an N-bit digital output signal, where N is a positive integer, comprising: generating digital approximation values through a plurality of adders and subtractors; pre-selecting a digital approximation value of the plurality of adders and a digital approximation value of the plurality of subtractors according to a comparison result; decoding the pre-selected digital approximation values; selecting one of the pre-selected decoded digital approximation values according to the comparison result, and converting the selected decoded digital approximation value into an analog approximation value; comparing the analog approximation value to an analog input signal, thereby providing a next comparison result, wherein the next comparison result is made available for a next pre-selecting and selection operations; and storing the value associated with the comparison result into a data register, wherein the selection of the decoded digital approximation values is performed after the decoding of the pre-selected digital approximation values.