Patent ID: 8772089

Claim:
A chip package structure, comprising: a leadframe, comprising: a die pad, having a first upper surface and a lower surface and comprising a chip mounting portion and a periphery portion, the die pad having a second upper surface lying between the first upper surface and the lower surface at the periphery portion; a plurality of leads, disposed around the die pad and having a top surface and a first bottom surface and each including a suspending portion and a terminal portion, wherein the leads have a second bottom surface lying between the top surface and the first bottom surface at the suspending portion, and each of the suspending portions connects to the terminal portion and extends from the terminal portion toward the die pad; and an insulating layer, disposed on the second upper surface of the periphery portion and connecting the suspending portions of the leads to the die pad; a chip, disposed on the chip mounting portion; a plurality of bonding wires, electrically connecting the chip to the suspending portions; and an encapsulant, covering the chip, the bonding wires, the insulating layer, and the leadframe.