Patent ID: 7039851

Claim:
In a system comprising two identical but independently operated parallel path closed rings of successively corrected and respectively clocked sequential data address generators, wherein a source of a stream of successively clocked data packets each provided with headers including error detection code facility flows along a first such path, a method of correcting data error in a packet and substituting therefor a correct data packet without interrupting the flow of the stream of data packets along said first path, that comprises, simultaneously flowing from said source a second identical stream of the successive data packets along a separate parallel second path; synchronizing the operation of said first and second data packet flow paths; at intervals along the separate data packet flows, convergingly linking the first and second flow paths at a common point of each of the respective rings and comparing the corresponding data packets from each flow path at such link point; in the event that one of the compared data packets of one of the flow paths has been determined by its error detection code to be an error, discarding such erroneous data packet and using the corresponding data packet of the other flow path in substitution therefore; and re-synchronizing the operation of the first and second data packet flow paths to continue an uninterrupted stream of data packet flow following such convergence.