Patent ID: 8854888

Claim:
An integrated circuit, comprising: a substrate; a base layer formed on the substrate and including discrete devices configured to operate within a first voltage range; an array of multiple layers of memory formed above the base layer and electrically coupled with the devices in the base layer, each layer including a plurality of conductive array lines, and a plurality of re-writable memory cells configured to operate within a second voltage range that is greater than the first voltage range, each memory cell including two terminals, configured to modify a conductivity profile of the memory cell in response to a first potential difference applied across the two terminals, and having one terminal electrically coupled with one of the plurality of conductive array lines; a first decoder including a first subset of the discrete devices that operate in the first voltage range; and a second decoder including a second subset of the discrete devices that operate in the first voltage range, wherein the first decoder and the second decoder are configured to collectively generate a voltage in the second voltage range but not in the first voltage range and to apply the voltage across the two terminals of at least one of the memory cells, whereby no single discrete device is subject to the second voltage range.