Patent ID: 7149143

Claim:
A decoder circuit, comprising: an address input having a control address and an offset address; a plurality of cells having a carry input and a carry output, wherein each cell is adapted to activate with a selected offset address and to decode a selected group of data words utilizing a coupled control address, where the carry input of each cell is coupled the carry output of a lower addressed previous cell of the plurality of cells, and where each data word in the group of data words is from a separate data word set of a plurality of data word sets of a column page; wherein the carry input of a first cell is coupled to a first logic state; wherein each cell is adapted to decode an input control address and select a data word of its assigned group of data words from a first data word set upon receiving a first logic state on its carry input; wherein each cell is adapted to decode an input control address and select a data word of its assigned group of data words from a second data word set upon receiving a second logic state on its carry input; and wherein each cell is adapted to select a data word of its assigned group of data words from a second data word set and invert the state of the input carry from logical first state to logical second state on its carry output upon matching its assigned input offset address.