Patent ID: 7875529

Claim:
A method for forming a CMOS device, the method comprising: forming a number of NMOS transistors on a first wafer using an NMOS process; forming a number of bond pads on the first wafer, the number of bond pads coupled to at least one of the number of NMOS transistors; forming a number of PMOS transistors on a second wafer using a PMOS process; forming a number of bond pads on the second wafer, the number of bond pads coupled to at least one of the number of PMOS transistors; bonding the first wafer and the second wafer to form at least one CMOS device; and providing relative alignment of corresponding bond pads on the first and second wafers, during bonding of the first and second wafers, via an initial alignment scheme that includes complementary coarse alignment structures formed on a surface of the first wafer and on a surface of the second wafer; wherein bonding the first wafer and the second wafer includes electrically coupling the first wafer to the second wafer with a number of reflowable interconnects.