Patent ID: 7443706

Claim:
A memory circuit comprising: at least one memory unit arranged in array, each memory unit has a corresponding row line and column line; a discharging module connected to the corresponding column line for discharging the column line of an objective memory unit, the discharging module comprising an N-type metal-oxide semi-transistor (NMOS) and an AND gate, wherein the AND gate determines whether to discharge the column line through the NMOS according to a discharging signal and a column selective signal of the column line; an auxiliary module connected to the discharging module; and a sense amplifier connected to the auxiliary module for accessing data stored in the memory unit by detecting an electrical level of the column line of the memory unit; wherein the memory circuit discharges the corresponding column line of the objective memory unit according to the discharging signal and the column selective signal; wherein when the objective memory unit is enabled, a voltage level of the corresponding column line is changed, and if the voltage level of the corresponding column line reaches a threshold voltage level, the auxiliary module enhances an increment of the voltage level of the column line.