Patent ID: 8923347

Claim:
A data transmission system, comprising: a first node configured to: receive at least two sets of input data signals, said at least two sets including at least two data signals each into which a clock signal is embedded; and format said sets for transmission according to a Time Division Multiplexing (TDM) structure; a transmission medium configured to transmit the TDM formatted signals as a bit stream having a line frequency; and a second node configured to: receive the bit stream and demultiplex the bit stream into at least two sets of output data signals, characterized in that the at least two sets input data signals include at least one first signal and at least one second signal, the at least one first signal being based on a synchronization source which is different from a synchronization source upon which the at least one second signal is based, wherein: the first node comprises: at least one clock extraction device configured to extract a respective clock signal representing each of said different synchronization sources from said at least one first and second signals, at least one sampling device configured to sample each of the extracted clock signals to a respective resulting sampled clock signal based on a sampling frequency which is synchronized with the line frequency, and a multiplexing device configured to incorporate each of the resulting sampled clock signals as a respective separate signal in the TDM; and the second node comprises: a demultiplexing device configured to demultiplex the received bit stream into at least two sets of output data signals and a set of demultiplexed clock signals representing the resulting sampled clock signals, at least one jitter attenuating device configured to, in each signal in the set of demultiplexed clock signals, reduce an amount of frequency jitter to below a predefined level and thus produce a respective clock signal having a synchronization quality being superior to the synchronization quality of the signals in the set of demultiplexed clock signals, and at least one interface device configured to combine each data signal in the at least two sets of output data signals with its associated clock signal into a respective resulting clock-carrying data signal in a data signal set.