Patent ID: 7434083

Claim:
A clock circuit for a data processing system, the circuit comprising: a phase locked loop (PLL) to generate a clock signal through phase locking to a reference signal; profile memory to store profile data comprising a plurality of entries, the profile memory capable of being updated in response to changes in nominal system frequency while the PLL generating the clock signal; and a profile state machine coupled to the profile memory and the PLL, the profile state machine to read the profile data in sequence from the profile memory and to control the PLL to adjust a frequency of the clock signal according to the profile data read in sequence from the profile memory; wherein a number of entries of a profile read by the profile state machine in sequence to control the PLL is adjustable; wherein a position of the profile in the profile memory, read by the profile state machine in sequence to control the PLL, is adjustable; and wherein the profile memory further stores address information about the profile, the address information specifying the number of entries of the profile and the position of the profile in the profile memory.