Patent ID: 8330512

Claim:
A clock generation circuit of a semiconductor apparatus, comprising: a first phase detection block configured to compare initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and output an initial phase difference detection signal corresponding to a comparison result; a second phase detection block configured to compare phases of the reference clock signal and the output clock signal, and output a phase detection signal corresponding to a comparison result; a variable unit delay block configured to determine a control range of the delay amount thereof in response to the initial phase difference detection signal, and to delay the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and output the output clock signal, wherein the control range of the delay amount has a delay amount corresponding to one half cycle or one cycle of the reference clock signal based on the initial phase difference detection signal; and a delay control block configured to generate the control voltage which has the voltage level corresponding to the phase detection signal.