Patent ID: 8263485

Claim:
A method for fabricating a semiconductor device, comprising: forming an N-type polysilicon layer and a P-type polysilicon layer over a substrate including an N-channel metal-oxide semiconductor (NMOS) region and a P-channel metal-oxide semiconductor (PMOS) region, the N-type polysilicon layer formed in the NMOS region and the P-type polysilicon layer formed in the PMOS region; forming a metal electrode layer over the N-type and P-type polysilicon layers; forming a gate hard mask over the metal electrode; forming a patterned buffer layer for defining gate pattern regions over the gate hard mask; forming a photoresist pattern exposing the PMOS region; trimming the patterned buffer layer in the PMOS region; removing the photoresist pattern; and etching the metal electrode layer and the N-type and P-type polysilicon layers to form gate patterns using the patterned and trimmed buffer layer.