Patent ID: 7813467

Claim:
A shift register, comprising a plurality of stages of shift register units, each stage of shift register unit generating a scan signal and comprising: a first level lifting unit, for controlling the scan signal to be equal to a first timing signal in response to a high level of a first control signal; a first level lowering unit, for controlling the scan signal to be equal to a first voltage in response to a high level of a second control signal; a first driving unit, for providing the first control signal to turn on the first level lifting unit in response to a rising edge of an input signal; and a level controller, for receiving the first control signal and accordingly outputting the second control signal at an output terminal, the level controller comprising: an input unit, for controlling a third control signal to be equal to the first voltage at a first node in response to a rising edge of the first control signal; a charge storage unit, having one end coupled to the first node and the other end for receiving a second timing signal, wherein the charge storage unit is for storing an electric charge induced by the second timing signal; a second level lifting unit, for controlling the second control signal to be substantially equal to the third control signal so as to turn on the first level lowering unit in response to a rising edge of the third control signal; and a second level lowering unit, for controlling the second control signal to be equal to the first voltage so as to turn off the first level lowering unit in response to the rising edge of the first control signal; wherein the input signal inputted to the first driving unit of the corresponding stage of shift register unit is a scan signal outputted by a previous stage of shift register unit; wherein the first level lowering unit comprises a first transistor, and the first transistor has a gate for receiving the second control signal, a drain coupled to the output terminal of the corresponding shift register unit, and a source for receiving the first voltage; wherein the first level lowering unit of the n-th stage of shift register unit further comprises a second transistor, and the second transistor has a gate for receiving the first control signal of the (n+2)-th stage of shift register unit, a drain coupled to the output terminal of the n-th stage of shift register unit, and a source for receiving the first voltage, wherein n is a natural number.