Patent ID: 8514637

Claim:
A device comprising: a three-dimensional cross point array memory comprising multiple stacks of memory cells; a first selection circuit comprising multiple first select devices in series and configured to selectively provide first and second voltages to respective first bit lines of a first subset of the multiple stacks, wherein the first subset comprises at least two stacks of the multiple stacks of memory cells having bit lines substantially parallel to one another, and wherein the first voltage is provided to a first stack of the at least two stacks and the second voltage is provided to a different second stack of the at least two stacks to select a particular memory cell; a second selection circuit comprising multiple second select devices in series and configured to selectively provide the first and second voltages to respective second bit lines of a second subset of the multiple stacks, wherein the second subset comprises at least one stack of the multiple stacks of memory cells having bit lines substantially perpendicular to the bit lines of the first subset; and a third selection circuit comprising at least one third select device configured to selectively provide a third voltage to a bit line of a stack in the multiple stacks, wherein the first voltage is greater than the second and third voltages and the third voltage is between the first and second voltages.