Patent ID: 7483506

Claim:
A bit synchronization circuit for retiming received burst data which is comprised of a preamble and a payload so as to output data synchronized with an internal reference clock, comprising: a multi-phase clock generator for generating multi-phase clocks with different phases and having the same frequency as said internal reference clock; an initial phase determining unit for detecting change points of received signal using said multi-phase clocks and outputting initial phase information including a phase number of a clock synchronized with the change points, during a period of receiving the preamble of the burst data; a clock switching unit for switching a data retiming clock and a phase detection clock to optimum phase clocks, respectively; a phase tracking unit for converting the received data into data retimed according to said data retiming clock, determining whether the phase of the signal change points of received signal is advanced or delayed relative to the phase detection clock, and outputting a phase correction signal corresponding to a result of the determination, during a period of receiving the payload of the burst data; and a data storage unit for temporarily storing the retimed data output from said phase tracking unit and outputting the data in synchronization with said internal reference clock, wherein said clock switching unit selects a first data retiming clock and a first phase detection clock to be supplied to said phase tracking unit from among said multi-phase clocks, based on the initial phase information output from said initial phase determining unit, and subsequently, switches the data retiming clock and the phase detection clock to be supplied to said phase tracking unit to optimum phase clocks according to the phase correction signal output from said phase tracking unit.