Patent ID: 7415599

Claim:
A processor circuit, comprising: a memory comprising a plurality of memory locations, the memory storing a first instruction and a second instruction in consecutive memory locations, wherein the first instruction includes an opcode portion and a portion that holds an indicator of a first operand, and wherein the second instruction includes an opcode portion but does not include any portion for holding an indicator of an operand; and a processor that executes the first instruction by performing a first operation using the first operand, wherein the first operand is stored at a first memory location in said memory identified by the indicator of the first operand of the first instruction, wherein the processor then executes the second instruction by performing a second operation, wherein the second operation is an operation of a type that is dependent upon the first instruction, wherein the second operation uses a second operand stored at a second memory location, wherein the second memory location is a memory location dependent upon the first memory location in said memory, and wherein the second operation is different than the first operation.