Patent ID: 8551809

Claim:
A method of fabricating a memory cell, the method comprising: forming a first electrode, the first electrode comprising a first material comprising a first element, the first electrode disposed atop a substrate; forming a semiconductor layer, the semiconductor layer disposed over the first electrode, the semiconductor layer comprising a second material having a bandgap of at least four electron volts; forming a second electrode, the second electrode disposed over the semiconductor layer, the second electrode and the first electrode having different work functions; forming a dielectric barrier layer, the dielectric barrier layer disposed between the semiconductor layer and the first electrode, the dielectric barrier layer being in substantially direct contact with the semiconductor layer, the dielectric barrier layer comprising the first element; annealing the memory cell comprising the semiconductor layer in a reducing environment; forming an array using the memory cell and voltage regulation circuitry in a form of an integrated circuit device, the voltage regulation circuitry being adapted to apply a set pulse to one of the first electrode or the second electrode while a remaining one of the first electrode or the second electrode being coupled to a voltage return path; and conditioning the memory cell using a forming process, the forming process comprising applying a pulse of opposite polarity to the set pulse, the forming process comprising applying a voltage pulse to the remaining one of the first electrode or the second electrode while the one of the first electrode or the second electrode is coupled to the voltage return path.