Patent ID: 8309395

Claim:
A method for fabricating a power semiconductor module comprising: providing a power semiconductor chip comprising a semiconductor bulk with a top side topped by a top chip metallization and a bottom side bottomed by a bottom chip metallization, said top chip metallization and said bottom chip metallization comprising copper or copper alloy; providing a substrate comprising a flat ceramic carrier with a top side topped by a top substrate metallization and a bottom side bottomed by a bottom substrate metallization, said top substrate metallization and said bottom substrate metallization comprising copper or copper alloy; coating the top chip metallization with a first anti-oxidation layer which comprises silicon nitride or silicon oxide so that the first anti-oxidation layer covers at least part of the side of the top chip metallization facing away from the semiconductor bulk; defining a chip mounting area on the top substrate metallization at which the power semiconductor chip is to be bonded to the top substrate metallization; coating the bottom substrate metallization with a first layer of precious metal so that the first layer of precious metal covers at least part of the side of the bottom substrate metallization facing away from the semiconductor bulk; positioning a tin comprising solder between the bottom chip metallization and the chip mounting area; producing a diffusion solder layer by melting and subsequently cooling the solder securely bonding the semiconductor chip to the top substrate metallization at the bottom chip metallization in the chip mounting area; providing a base plate comprising a top side; coating the top side of the base plate with a second precious metal layer; positioning a silver comprising paste between the second precious metal layer and the first precious metal layer applied to the bottom substrate metallization; producing a sinter bonding layer between the substrate and the base plate by urging the substrate against the base plate with a contact pressure over a predefined range of temperature and for a predefined time; providing a bonding element in the form of a bond wire or metal ribbon; and producing a direct bond between the bonding element and the top chip metallization by positioning a portion of the bonding element by means of a bonding tool on the first anti-oxidation layer and urging the bonding element into contact with the power semiconductor chip by locally breaking and penetrating the first anti-oxidation layer.