Patent ID: 6962851

Claim:
A method for fabricating an integrated circuit which comprises a nonvolatile memory which comprises an array of nonvolatile memory cells, the integrated circuit comprising an array area containing the array, each memory cell of the array having a conductive floating gate and a first conductive gate insulated from each other, the method comprising: (a) forming one or more substrate isolation regions in a semiconductor substrate between active areas of the semiconductor substrate, each substrate isolation region being a dielectric region protruding above the semiconductor substrate; (b) forming one or more conductive lines G 1 , each conductive line G 1 overlying at least one active area, wherein each first conductive gate comprises a portion of a line G 1 ; (c) forming a layer (“FG layer”) over the first conductive lines and the substrate isolation regions, wherein each floating gate comprises a portion of the FG layer; (d) partially removing the FG layer to expose the substrate isolation regions and to remove the FG layer from over at least a portion of each conductive line G 1 ; wherein the FG layer has a planar top surface in the array area at a time before the end of the operation (d); and the operation (d) comprises partially removing the FG layer after said time without a mask over the array.