Patent ID: 7964489

Claim:
A method of manufacturing a semiconductor device comprising: forming a first insulating layer on an n-type semiconductor layer, the first insulating layer containing silicon and oxygen; forming a second insulating layer on the first insulating layer, the second insulating layer containing hafnium, silicon, oxygen, and nitrogen; forming a third insulating layer on the second insulating layer, the third insulating layer containing aluminum and oxygen; performing a heat treatment to diffuse aluminum atoms from the third insulating layer into an interface between the second insulating layer and the first insulating layer; forming a gate electrode material layer above the second insulating layer after performing the heat treatment; etching the gate electrode material layer, the second insulating layer, and the first insulating layer to form a gate structure; and forming source and drain regions of p-type in the n-type semiconductor layer at both sides of the gate structure, wherein the first and second insulating layers have first and second regions respectively, the first region being in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer, the second region being in a 0.3 nm range in the film thickness direction from the interface between the first insulating layer and the second insulating layer, and each of the first and second regions including aluminum atoms with a concentration of 1×10 20 cm −3 or more to 1×10 22 cm −3 or less.