Patent ID: 8877651

Claim:
A method of manufacturing a semiconductor device, said method comprising: forming a contact etch stop layer on an active area of a semiconductor substrate, wherein a gate stack having a metal gate and a metal oxide on the metal gate is formed on said semiconductor substrate, said contact etch stop layer including a first silicon nitride layer overlying a silicon oxide layer, a second silicon nitride layer overlying the active area, the silicon oxide layer being sandwiched between the first and second silicon nitride layers; forming a contact hole extending through an interlayer dielectric layer overlying said first silicon nitride layer by etching using said first silicon nitride layer as a protective layer for said active area; removing a portion of said first silicon nitride layer being exposed at the bottom of said contact hole using said silicon oxide layer as a protective layer for said active area; and removing the metal oxide on said metal gate using said second silicon nitride layer as a protective layer for said active area, wherein part of said second silicon nitride layer that overlaps said active area has a reduced remaining thickness as a result of said removing the metal oxide.