Patent ID: 7437580

Claim:
A dynamic voltage scaling system, comprising: a monitoring block for sensing activity information and critical path delay information occurring within a microprocessor core; a control block for reading the activity information and the critical path delay information from the monitoring block, processing the activity information and the critical path delay information, and adjusting voltage that is supplied to the microprocessor core according to the results of processing the activity information and the critical path delay information; and wherein the monitoring block comprises at least one embedded delay checker (EDC) cell configured to receive a terminal register input signal, a terminal register output signal and a control signal, the EDC cell comprising: a plurality of delay elements; a multiplexer coupled to the plurality of delay elements, wherein the multiplexer is configured to select a subset of delay elements to place in the path of the terminal register input signal in accordance with the control signal; a register for storing an output of the multiplexer; and a logical element configured to detect a logical difference between the stored output of the multiplexer and the terminal register output signal.