Patent ID: 8307147

Claim:
An interconnect comprising: multiple (M) input ports; multiple (S) output ports; and multiple modular components coupled between the M input ports and the S output ports; wherein each modular component is adapted to support a certain point-to-point protocol, wherein at least one modular component comprises a sampling circuit and a first bypass circuit, the sampling circuit being selectively bypassed by the first bypass circuit, the multiple modular components comprising; multiple expanders, wherein each expander comprises: a sampler, wherein the sampler upgrades a transaction priority of a pending transaction request stored in the sampler by changing a priority attribute value of the transaction request, the sampler being selectively bypassed by a second bypass circuit; and a de-multiplexer; and multiple (S) arbiters and multiplexers, wherein different expanders are coupled to different masters, and wherein each expander is coupled in parallel to the S arbiters and multiplexers.