Patent ID: 7462534

Claim:
A method of forming memory circuitry, comprising: providing a substrate having a memory array circuitry area and a peripheral circuitry area, the memory array circuitry area comprising transistor gate lines having a first minimum line spacing, the peripheral circuitry area comprising transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing; forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area; and after forming said insulative sidewall spacers within the peripheral circuitry area and said insulative sidewall spacers within the memory array circuitry area, epitaxially growing semiconductive material adjacent said insulative sidewall spacers within the memory array circuitry area while not epitaxially growing semiconductive material adjacent said insulative sidewall spacers within the peripheral circuitry area.