Patent ID: 6875702

Claim:
A process for forming a conductive via in an integrated circuit structure, where the integrated circuit structure includes a first dielectric layer overlying a first conductive layer, the process comprising: (a) forming a via cavity in the first dielectric layer, the via cavity exposing the first conductive layer; (b) etching the via cavity with a hydrogen-containing plasma; (c) in a deposition reactor, forming a liner layer in the via cavity by; (i) depositing a portion of the liner layer in the via cavity, (ii) forming an isotropic plasma of hydrogen and nitrogen ions upstream from the integrated circuit structure, (iii) flowing the isotropic plasma to the integrated circuit structure, (iv) exposing the liner layer to the isotropic plasma, thereby densifying the liner layer, including sidewalls of the liner layer, and (v) repeating steps (c)(i) through (c)(iv) until the liner layer is formed, and (d) forming a second conductive layer adjacent the liner layer in the via cavity, the second conductive layer substantially filling the via cavity to form the conductive via.