Patent ID: 7525868

Claim:
A multiple-port static random access memory (SRAM) device having a plurality of cells, each of which comprises: a latch having a first node and a second node for retaining a value and a complementary value, respectively; a first NMOS transistor coupled between the first node and a read/write port bit line, with its gate controlled by a read/write word line; a second NMOS transistor coupled between the second node and a read/write port complementary bit line, with its gate controlled by the read/write word line; a third NMOS transistor having a gate coupled to the second node, and a source coupled to a complementary supply voltage; a fourth NMOS transistor having a source coupled to a drain of the third NMOS transistor, a drain coupled to a first read port bit line, and a gate coupled to a read word line; a fifth NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage; a sixth NMOS transistor having a source coupled to a drain of the fifth NMOS transistor, a drain coupled to a first read port complementary bit line, and a gate coupled to the read word line; a seventh NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage; an eighth NMOS transistor having a source coupled to a drain of the seventh NMOS transistor, a drain coupled to a second read port bit line, and a gate coupled to the read word line; a ninth NMOS transistor having a gate coupled to the first node, and a source coupled to the complementary supply voltage; and a tenth NMOS transistor having a source coupled to a drain of the ninth NMOS transistor, a drain coupled to a second read port complementary bit line, and a gate coupled to the read word line, wherein, in a layout view of the cell, the first read port bit line, first read port complementary bit line, second read port bit line, second read port complementary bit line, read/write port bit line and read/write port complementary bit line are separated by at least one supply voltage line, one or more complementary supply voltage lines, and one or more word line landing pads.