Patent ID: 8164959

Claim:
A non-volatile memory device, comprising: a signal bus; a bus interface operable to receive signals from the signal bus indicative of a memory command and a memory address, the bus interface further being operable to receive signals from the signal bus corresponding to write data and to output signals to the signal bus indicative of read data; an array of non-volatile memory cells, the memory cells in the array being programmable to multiple charge levels corresponding to different respective bit states; and a control logic unit coupled to the bus interface and the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address, the control logic unit further being operable to: read data from non-volatile memory cells in a row proximate a first row of memory cells; store in a temporary storage location the data read from the proximate memory cells; program the first row of memory cells; read data from the proximate memory cells; compare the data read from the proximate memory cells to the stored data read from the proximate memory cells; evaluate the comparison to determine the threshold voltages corresponding to respective bit states of the proximate memory cells; and based on the evaluation, apply additional charge to at least some of the proximate memory cells.