Patent ID: 7951704

Claim:
A method of fabricating an integrated circuit memory device comprising: depositing a first inter-level dielectric layer on a substrate; etching a contact opening in the first inter-level dielectric layer that extends to a component in the peripheral area of the substrate; forming a contact in the contact opening, in the peripheral area, from a first metal layer; depositing a second inter-level dielectric layer on the first inter-level dielectric layer; etching a via opening in the second inter-level dielectric layer that extends to the contact in the peripheral area; etching a dummy via opening in the second inter-level dielectric layer proximate the via opening; forming a via in the via opening and a dummy via in the dummy via opening, in the peripheral area, from a second metal layer; depositing an etch stop layer on the second inter-level dielectric layer; etching via opening windows in the etch stop layer; depositing a first metallization oxide layer on the second inter-level dielectric layer after forming the contact in the peripheral area; etching metallization layer openings in the first metallization oxide layer and the via opening and the dummy via opening through the via opening windows in the etch stop layer; and forming a metallization layer in the metallization layer opening, the via in the via opening and the dummy via in the dummy via opening from the second metal layer.