Patent ID: 8294241

Claim:
A semiconductor device, comprising: a first insulating layer; a wiring layer formed in the first insulating layer; a second insulating layer formed over the first insulating layer; a capacitive element including a lower electrode, an upper electrode, and a dielectric layer interposed between the upper electrode and the lower electrode, the lower electrode and the dielectric layer being larger than the upper electrode, the lower electrode being formed over the second insulating layer; a first layer formed over the upper electrode and the lower electrode, a portion of the first layer being in contact with a lower surface of the upper electrode; a third insulating layer formed over the second insulating layer and the first layer, the third insulating layer having an etching rate different from an etching rate of the second insulating layer and the first layer; a first contact via connected to the wiring layer; a second contact via connected to the upper electrode; and a third contact via connected to the lower electrode.