Patent ID: 8143707

Claim:
A semiconductor device, comprising: a circuit base including a chip mounting area, a first external terminal portion including first external terminals, a second external terminal portion including second external terminals opposed to the first external terminals via the chip mounting area, and an inner lead portion having first inner leads connected to the first external terminals, second inner leads connected to the second external terminals and third inner leads electrically independent of the first and second external terminals, at least part of the first, second, and third inner leads being routed inside the chip mounting area; a first semiconductor chip group, disposed on the chip mounting area in a first surface of the circuit base, including at least one first semiconductor chip having first electrode pads; a second semiconductor chip group, disposed on the chip mounting area in a second surface of the circuit base, including at least one second semiconductor chip having second electrode pads; first metal wires electrically connecting the first electrode pads of the first semiconductor chip and the inner lead portion; second metal wires electrically connecting the second electrode pads of the second semiconductor chip and the inner lead portion; and a resin sealing portion sealing the first and second semiconductor chip groups together with the first and second metal wires, wherein at least part of the first electrode pads of the first semiconductor chip are electrically connected to the second electrode pads of the second semiconductor chip via the third inner leads.