Patent ID: 7504654

Claim:
A ballistic logic gate, comprising: a silicon etched substrate frame including first, second, third, and fourth frame sides wherein the first and second frame sides intersect at a common corner of the frame; a pair of triangular silicon baffles etched from the silicon substrate frame wherein, the pair of baffles are spaced from the first and second frame sides to define first and second inputs and first and second input channels leading from respective first and second inputs and intersecting at the common corner of the frame, the pair of baffles are disposed against the third and fourth frame sides and spaced from one another to define an output channel there between and an output opposite the common corner of the frame wherein the output channel traverses between the pair of baffles from the common corner to the output; an output terminal disposed beyond the output for indicating a logical “OR” operation; a nano-deflector disposed in the common corner; and a parabolic nano-deflection surface on the nano-deflector for receiving an oncoming electron entering the silicon etched substrate frame through either the first or second inputs and for deflecting the electron into a fixed path within the output channel and toward the output terminal.