Patent ID: 7388777

Claim:
A semiconductor device comprising: a semiconductor substrate having a first main surface and a second main surface provided on the back surface side thereof; a main circuit forming area disposed in the first main surface of the semiconductor substrate; and a nonvolatile memory area disposed in the first main surface of the semiconductor substrate, wherein the nonvolatile memory area includes: a first well formed in a main surface of the semiconductor substrate; a second well disposed in the main surface of the semiconductor substrate along the first well and disposed in a state of being electrically isolated from the first well; a plurality of nonvolatile memory cells disposed in array form so as to be superimposed over both the first well and the second well on a plane basis; and a plurality of selection field effect transistors respectively electrically connected to the plurality of nonvolatile memory cells so as to be capable of selecting the plurality of nonvolatile memory cells, wherein each of the plurality of nonvolatile memory cells includes: a floating gate electrode disposed extending in a first direction so as to be superimposed over both the first well and the second well on a plane basis; a field effect transistor for writing data formed at a first position where the floating gate electrode is superimposed over the first well on a plane basis; a field effect transistor for reading data formed at a second position different from the first position, where the floating gate electrode is superimposed over the first well on a plane basis; and a control gate electrode formed at a portion to which the floating gate electrode is opposite in the second well, wherein the field effect transistor for writing data includes: a first gate electrode formed at the first position relative to the floating gate electrode; a first gate insulating film formed between the first gate electrode and the semiconductor substrate; and a pair of semiconductor areas formed at a position where the semiconductor areas interpose the first gate electrode therebetween in the first well, and wherein the field effect transistor for reading data includes: a second gate electrode formed at the second position relative to the floating gate electrode; a second gate insulating film formed between the second gate electrode and the semiconductor substrate; and a pair of semiconductor areas formed at a position where the semiconductor areas interpose the second gate electrode therebetween in the first well.