Patent ID: 7173980

Claim:
A receiver comprising: an in-phase mixer configure to translate an incoming signal to an in-phase intermediate frequency signal; an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate; an in-phase decimation filter configured to decimate the in-phase digital signal; a quadrature mixer configured to translate an incoming signal to an quadrature intermediate frequency signal; a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at a predetermined sampling rate; wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator; a quadrature decimation filter configured to decimate the quadrature digital signal; a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals; and a voltage controlled oscillator; wherein each of the in-phase and quadrature mixers translates the incoming signal by a local oscillator frequency of f LO derived from the voltage controlled oscillator; and the sampling rate of each of the in-phase and quadrature delta-sigma modulators is derived from the voltage controlled oscillator and equal to an integer sub-multiple of f LO ; and wherein each of the in-phase and quadrature intermediate frequency signals has an intermediate frequency equal to f LO divided by an integer that is a function of a decimation ratio of the each of the in-phase and quadrature decimation filters.