Patent ID: 8741743

Claim:
A method of making a semiconductor device, the method comprising: obtaining a semiconductor structure comprising (a) a first semiconductor layer having a first crystallographic orientation, (b) a second semiconductor layer having a second crystallographic orientation distinct from said first crystallographic orientation wherein the second semiconductor layer includes an active region and an inactive region, and (c) an electrically insulating layer disposed between said first semiconductor layer and said second semiconductor layer; forming epitaxy features including a set of epitaxy active features in the active region of the second semiconductor layer and a set of epitaxy dummy features in the inactive region of the second semiconductor layer and, wherein said forming includes: patterning a first mask overlying the second semiconductor layer to define a set of openings corresponding to the set of epitaxy dummy features; removing portions of the second semiconductor layer and the electrically insulating layer underlying the set of openings in the first mask to form a first plurality of trenches extending through said second semiconductor layer and said insulating layer to expose portions of said first semiconductor layer; and forming a sidewall dielectric layer on sidewalls of said first plurality of trenches; epitaxially growing the epitaxy features from said exposed portions of said first semiconductor layer, wherein each of the epitaxial features: extends from the first silicon layer through the buried dielectric layer and the second silicon layer; and is insulated from the second silicon layer by the sidewall dielectric layer; performing a first chemical mechanical polish; forming isolation features including a set of isolation dummy features in the inactive region and a set of isolation trench features in the active region, wherein said forming includes: patterning a second mask overlying the second semiconductor layer to define a second set of openings; removing portions of the second semiconductor layer underlying the second set of openings to form a second plurality of trenches extending through said second semiconductor layer and terminating at the electrically insulating layer; and forming an isolation dielectric material in the second plurality of trenches to form the isolation features; and performing a second chemical mechanical polish.