Patent ID: 7263621

Claim:
A circuit for reducing power consumption within a computer processor comprising: a first instruction decoder configured to decode instructions with 16-bit words; a second instruction decoder configured to decode instructions with 32-bit words; a word length select configured to indicate a present instruction's word length; a first selector coupled to the first instruction decoder, the first selector configured to receive the instruction, the first selector configured to receive a feedback signal from an output of the first selector, the first selector configured to route the instruction into the first instruction decoder when the present instruction is 16-bits long; a second selector coupled to the second instruction decoder, the second selector configured to route the instruction into the second instruction decoder when the present instruction is 32-bits long; and a third selector coupled to the first and second instruction decoders and configured to route the present instruction to execute stage of the processor from one of the 16-bit decoder and the 32-bit decoder.