Patent ID: 7629215

Claim:
A method of manufacturing a semiconductor device, comprising: forming first gate structures spaced apart from each other by regular intervals on a first region of a substrate, and forming second gate structures spaced apart from each by regular intervals other on a second region of the substrate, the intervals by which the second gate structures are spaced apart from each other being greater than the intervals by which the first gate structures are spaced apart from each other, respectively; forming a capping layer on the first gate structures, the second gate structures and the substrate so as to cover opposite side surfaces of each of the gates structures; forming over the capping layer a first spacer and a second spacer on each of the side faces of the second gate structures, and a third spacer on the side faces of each of the first gate structures, the first spacers comprising a first insulation material, and the second spacers and the third spacers each comprising an insulation material different from the first insulation material; etching the capping layer to form a first capping layer pattern on the side faces of the first gate structures and a second capping layer pattern on the side faces of the second gate structures; doping the substrate with impurities on opposite sides of the first gate structures to form first impurity regions in the first region of the substrate; and doping the substrate with impurities on opposite sides of the second gate structures to form second impurity regions in the second region of the substrate.