Patent ID: 8208305

Claim:
A memory cell array, comprising: a bitline contact connected to a first memory cell string and a second memory cell string; the first memory cell string including at least first and second dummy memory cells adapted to be programmed to share the bitline contact; the second memory cell string including at least first and second dummy memory cells adapted to be programmed to share the bitline contact; a first source line connected to the first memory cell string; and a second source line connected to the second memory cell string; wherein the first dummy memory cell of the first memory cell string and the second dummy memory cell of the second memory cell string are programmed in the following sequence: performing a coarse program operation to the first dummy memory cell of the first memory cell string; performing a coarse program operation to the second dummy memory cell of the second memory cell string; performing a fine program operation to the first dummy memory cell of the first string; performing a program verify operation on the first dummy memory cell of the first string performing a fine program operation to the second dummy memory cell of the second string; and performing a program verify operation on the second dummy memory cell of the second string.