Patent ID: 6918046

Claim:
A high speed interface device, comprising: a DRAM unit for generating first clock and first clock bar signals which do not have a phase difference from a main clock signal, and second clock and second clock bar signals having 90° phase difference from the first clock and clock bar signals during a write operation, storing an inputted 4 bit data in one period of the main clock signal according to the first and second clock and clock bar signals, synchronizing the stored data with data strobe signals according to the first and second clock and clock bar signals during a read operation, and outputting a 4 bit data during one period of the main clock signal; a controller for transmitting a command, address signal and data signal synchronized with the main clock signal to the DRAM unit during the write operation, and receiving data signals from the DRAM unit during the read operation; and, further including a circuit for generating the data strobe signals, comprising: a first delay unit for receiving the first clock signal; a first buffer unit connected between an output terminal of the first delay unit and an output terminal for outputting a first data strobe signal; a second delay unit for receiving the second clock signal; and a second buffer unit connected between an output terminal of the second delay unit and an output terminal for outputting a second data strobe signal.