Patent ID: 7679454

Claim:
A phase-locked loop (PLL) comprising: a digital phase/frequency detector (PFD), for generating a first detection signal according to a phase error or a frequency difference between an input signal and a feedback signal; a digital loop filter, coupled to the digital phase/frequency detector, for generating a first control signal according to the first detection signal; a decision circuit, coupled to the digital loop filter, for generating a divisor value according to the first control signal, wherein the decision circuit comprises: a sigma-delta modulator (SDM), coupled to the digital loop filter, for generating a modulation value according to the first control signal; and a calculation unit, coupled to the sigma-delta modulator, for generating the divisor value according to the modulation value and a predetermined value representing an initial divisor value; a fractional-N PLL, coupled to the decision circuit, for generating an oscillation signal according to the divisor value and a reference signal; and a frequency divider, coupled to the fractional-N PLL and the digital phase/frequency detector, for performing a frequency dividing operation upon the oscillation signal to generate the feedback signal; wherein the fractional-N PLL comprises a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.