Patent ID: 6967857

Claim:
A memory cell, comprising: a first bit line; a second bit line; a plurality of transistors configured to store a first bit of data at a first point and a second bit of data at a second point, the plurality of transistors being operatively coupled to the first bit line and the second bit line; a match transistor that is switchable to a first state and to a second state, the first state being in response to a first predetermined relationship between first and second bits and third and fourth bits transmitted on the first bit line and the second bit line, the second state being in response to a second predetermined relationship between the first and second bits and the third and fourth bits; a first p-channel transistor operatively coupled to the first bit line, the first point and the match transistor; and a second p-channel transistor operatively coupled to the second bit line, the second point and the match transistor.