Patent ID: 6937537

Claim:
A semiconductor memory, comprising: at least two memory banks each having a memory cell matrix; and an address decoding unit including a bank address decoding unit, a row address decoding unit, and a column address decoding unit; said bank address decoding unit having a control input for obtaining a bank address; said row address decoding unit having a plurality of address buffer memories and a plurality of address decoders, each one of said memory banks associated with a respective one of said plurality of address buffer memories connected in series with a respective one of said plurality of address decoders; said column address decoding unit having a plurality of address buffer memories and a plurality of address decoders, each one of said memory banks associated with a respective one of said plurality of address buffer memories of said column address decoding unit connected in series with a respective one of said plurality of address decoders of said column address decoding unit; at least one component selected from a group consisting of said row address decoding unit and said column address decoding unit having a demultiplexer connected upstream of said plurality of address buffer memories of said row address decoding unit and/or connected upstream of said plurality of said address buffer memories of said column address decoding unit; and said demultiplexer connected to said bank address decoding unit for activating a corresponding one of said plurality of said address buffer memories of said row address decoding unit and/or a corresponding one of said plurality of said address buffer memories of said column address decoding unit based on the bank address being applied to said control input and being decoded by said bank address decoding unit.