Patent ID: 7663928

Claim:
A sense amplifier circuit for a semiconductor memory device, comprising: a latch circuit having a first terminal and a second terminal; a first transistor having a first terminal electrically connected to the first terminal of the latch circuit, a second terminal electrically connected to a low bias supply, and a gate; a second transistor having a first terminal electrically connected to the second terminal of the latch circuit, a second terminal electrically connected to the low bias supply, and a gate for receiving a first control signal; and a current mirror circuit having a first terminal for receiving a first current, a second terminal electrically connected to the gate of the first transistor, a third terminal electrically connected to the low bias supply, and a fourth terminal electrically connected to the low bias supply wherein the latch circuit comprises: a first inverter having an input terminal electrically connected to he first terminal of the first transistor, and an output terminal electrically connected to the first terminal of the second transistor; and a second inverter having an input terminal electrically connected to the first terminal of the second transistor, and an output terminal electrically connected to the first terminal of the first transistor.