Patent ID: 6909132

Claim:
A semiconductor device including a DRAM memory cell and a peripheral MOS transistor, comprising: a first etching stopper layer covering at least one of an impurity diffusion layer and a gate electrode of said peripheral MOS transistor; a second etching stopper layer formed above at least a portion of said first etching stopper layer and separated from said first etching stopper layer by a distance; at least one of said impurity diffusion layer and said gate electrode of said peripheral MOS transistor being connected to a metal wiring layer formed in an upper level of a capacitor section of said DRAM memory cell by an electrode layer extending through said first etching stopper layer and said second etching stopper layer; said impurity diffusion layer being connected to said electrode layer at a boundary between said impurity diffusion layer and a device isolation insulating film; wherein a bottom portion of said electrode layer formed on said device isolation insulating film measured from a surface of said impurity diffusion layer has a length shorter than one of a junction depth of said impurity diffusion layer and a thickness of said first etching stopper layer.