Patent ID: 8242842

Claim:
A circuit comprising: a first transistor having a gate terminal and a drain terminal, the gate terminal of the first transistor being configured to receive a first voltage; a second transistor having a gate terminal and a drain terminal, the gate terminal of the second transistor being configured to receive a second voltage, and the drain terminal of the first transistor being connected with the drain terminal of the second transistor; a third transistor having a gate terminal and a drain terminal, the gate terminal of the third transistor being configured to receive a reference voltage; a fourth transistor having a gate terminal and a drain terminal, the gate terminal of the fourth transistor being connected with the drain terminal of the fourth transistor and the drain terminals of the first and second transistors; a fifth transistor having a gate terminal and a drain terminal, the gate terminal of the fifth transistor being connected with the drain terminal of the fifth transistor and the drain terminal of the third transistor; a sixth transistor having a gate terminal and a drain terminal, the gate terminal of the sixth transistor being connected with the gate terminal of the fourth transistor; a seventh transistor having a gate terminal and a drain terminal, the gate terminal of the seventh transistor being connected with the drain terminal of the seventh transistor and the drain terminal of the sixth transistor; an eighth transistor having a gate terminal and a drain terminal, the gate terminal of the eighth transistor being coupled with the gate terminal of the seventh transistor, and the drain terminal of the eighth transistor being coupled with the gate terminal of the first transistor; a ninth transistor having a gate terminal and a drain terminal, the gate terminal of the ninth transistor being coupled with the gate terminal of the fifth transistor, and the drain terminal of the ninth transistor being coupled with the gate terminal of the first transistor; a tenth transistor having a gate terminal and a drain terminal, the gate terminal of the tenth transistor being coupled with the gate terminal of the eighth transistor, and the drain terminal of the tenth transistor being coupled with the gate terminal of the second transistor; and an eleventh transistor having a gate terminal and a drain terminal, the gate terminal of the eleventh transistor being coupled with the gate terminal of the ninth transistor, and the drain terminal of the eleventh transistor being coupled with the gate terminal of the second transistor.