Patent ID: 7900025

Claim:
A processor, comprising: an issue unit; an execution unit coupled to the issue unit; and a vector register file coupled to the execution unit, wherein: the execution unit has floating point (FP) single instruction multiple data (SIMD) instruction set architecture (ISA) hardware logic that executes instructions that process floating point numbers in a SIMD arrangement from the vector register file, floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements, and the execution unit has hardware logic that uses an encoding scheme for a selection operation and Boolean logic operations that causes the selection operation and Boolean logic operations to be performed using a floating point vector data format for both the inputs and outputs of the selection operation and Boolean logic operations, wherein the processor does not provide support for integer encoding of data for the storage of comparison results, Boolean operations, performing selection operations, and performing data alignment operations.