Patent ID: 7245821

Claim:
An image processing apparatus, comprising: a front-end decoder which generates a first reproduced image data sequence by decoding a first coded data sequence including I picture, P picture and B picture coded in compliance with MPEG; a first frame memory, utilized for a decoding processing by said front-end decoder, which stores the first reproduced image data sequence; an encoder which generates a second coded data sequence by recoding the first reproduced image data sequence read out from said first frame memory; a back-end decoder which generates a second reproduced image data sequence by decoding the second coded data sequence; and a second frame memory, utilized for a decoding processing by said back-end decoder, which stores at least one picture included in the second reproduced image data sequence, said first frame memory, including: a first region which stores at least one I picture or one P picture to be front referred to for decoding P pictures or B pictures; a second region which stores at least one I picture or one P picture to be back referred to for decoding B pictures; and a third region, utilized for a decoding processing by said front-end decoder, which stores at least one B picture.