Patent ID: 7923372

Claim:
A method for fabricating a semiconductor device, comprising: forming a plurality of etch mask patterns over an etch target layer, each of the etch mask patterns including a first hard mask, a first pad layer, and a second pad layer stacked over the etch target layer; forming spacers on both sidewalls of the etch mask patterns, the spacers including a material substantially the same as that of the first pad layer; forming a second hard mask over the resulting structure until gaps between the etch mask patterns are filled, the second hard mask including a material different from that of the first hard mask but substantially the same as that of the second pad layer; performing a first planarization process onto the resultant structure in a manner that a portion of the second pad layer remains and a portion of the second hard mask and a portion of the spacer are removed; performing a second planarization process onto the resultant structure using the first pad layer as a planarization stop layer in a manner that a portion of the remaining second hard mask is removed; removing the first pad layer and the remaining spacers; and etching the etch target layer using the remaining first and second hard masks as an etch barrier layer.