Patent ID: 7219209

Claim:
An address translation filter for filtering a signal on a system bus that couples between a core processor and an external memory unit, the address translation filter comprising: a first interface operable under a first bus protocol to connect to the system bus and receive a virtual memory address from an external device connected to the bus; a second interface operable under a second bus protocol to connect to the system bus and transmit a physical memory address to the external memory unit; an input for receiving an input system clock signal; an output for transmitting an output system clock signal; and an address translation unit, comprising a translation lookaside buffer and a refresh logic unit operable to refresh the translation lookaside buffer if the virtual memory address is not matched by an entry in the translation lookaside buffer, the address translation unit being external to the core processor and coupled between the first and second interfaces, operable to determine the physical memory address from the virtual memory address, wherein the first bus protocol is the same as the second bus protocol, and wherein the output clock signal is paused while the translation lookaside buffer is being refreshed.