Patent ID: 8185686

Claim:
A memory system, comprising: a host having a storage space composed of a plurality of logical units for a user data to be accessed; a storage module including a storage space with a plurality of physical units, wherein each physical unit includes a plurality of physical blocks, the storage module reserves at least two physical blocks to respectively store a master table in which one of a start block address, a length, a cycle time, a logical to physical (L2P) table offset, and an associated segment or a combination thereof for each of the physical units is stored and a mapping relation between a logical block address of a logical block of the plurality of logical units and a physical block address of a physical block of one of the plurality of physical units; and a control module for adjusting the mapping relation between the logical block address and the physical block address according to erase cycles of the physical units wherein each of the physical units is associated with a segment table for indicating an allocation status of each physical unit, with an address of the segment table stored in the master table and the segment table defining an allocated flag field for indicating whether the corresponding physical unit is allocated for the user data to be accessed and an alternate segment flag field for indicating whether a physical block address of each physical block for the user data to be accessed is adjusted.