Patent ID: 7450120

Claim:
A method of forming information on chip for culling tiles of a graphics system, comprising: on a graphics processing unit, performing rendering of scenes, including performing a second pass of Z-culling on a frame-by-frame basis; on a coprocessor acting one frame ahead of said graphics processing unit to perform a first pass of Z-culling at a coarse level of resolution, including: performing a first step of vertex processing to calculate vertex data for rasterization of a current frame being processed by the coprocessor; performing a first step of rasterization to rasterize the current frame fame being processed by the coprocessor; constructing a surface of nearest and farthest objects being rendered and determining Z depth data for near and far objects; determining a Z depth threshold value to perform Z-culling to identify covered tiles to perform the first pass of Z-culling at a coarse level of resolution for the current frame; and providing coarse Z-cull information to said graphics processing unit to begin the second pass of Z-culling for the current frame; said coprocessor performing vertex processing, rasterization, and Z-culling on a frame-by-frame basis to process frames identical to those processed by said graphics processing unit but with said coprocessor working one frame ahead of said graphics processing unit and at a coarser level of resolution such that said graphics processing unit begins the processing of a new frame with an initial set of culling information generated by said coprocessor for the same frame.