Patent ID: 8183137

Claim:
A method for manufacturing a semiconductor device, comprising: forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate; patterning the layer of gate electrode material and the layer of gate dielectric material to form an NMOS gate structure, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode; forming n-type source/drain regions within the substrate proximate the NMOS gate structure; fully siliciding the NMOS gate electrode to form a silicided gate electrode; and placing a p-type dopant such that the p-type dopant is present within the NMOS gate electrode prior to or concurrently with the siliciding, wherein placing the p-type dopant includes siliciding the NMOS gate electrode using a layer of metal including the p-type dopant.