Patent ID: 7920406

Claim:
A method for forming a memory structure, the method comprising: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring a plurality of access transistors such that each of the plurality of access transistors is coupled to a rectifying element, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming, after configuring the plurality of access transistors, a common connection configured to short neighboring access transistors together along a word line direction, in groups of two or more, such that current passing through any single rectifying element passes through two or more access transistors.