Patent ID: 7226829

Claim:
A method for forming a storage node of a semiconductor device, comprising the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked over a surface of a substrate structure; (b) forming a first barrier layer and a first inter-layer insulation layer along a profile containing the bit line patterns and filling spaces between the bit line patterns; (c) etching the first inter-layer insulation layer to define a trench between the bit line patterns, so that at least a partial portion of the first inter-layer insulation layer remains below the trench and over the first barrier layer between the bit line patterns, wherein a portion of the first barrier layer provided below the trench and between the bit line patterns is not exposed by the etching-the-first-inter-layer-insulation-layer step; (d) forming a second barrier layer over the first inter-layer insulation layer and the first barrier layer; and (e) etching the first and the second barrier layers and the partial portion of the first inter-layer insulation layer to expose a surface of the substrate structure disposed between the bit line patterns.