Patent ID: 8426272

Claim:
A method of fabricating a non-volatile memory device, the method comprising: forming a plurality of field regions on a substrate in a first direction, where each of the field regions includes a homogeneous first field and a second field that is divided into two sub regions via a bridge region, the forming a plurality of field regions including, depositing first, second, and third insulating layers on the substrate; and etching the second and third insulating layers by performing a double patterning technology (DPT) process, the DPT process at least partially etching the third insulating layer using first mask patterns and etching any remaining third insulating layer and the second insulating layer using second mask patterns, the second mask patterns being different from the first mask patterns; growing a tunneling oxide layer on an active region defined as having a string structure by the field regions, where at least two strings are connected via one of the bridge regions; forming a plurality of bit line contacts in the bridge regions; and forming a plurality of shared bit lines on the field regions in the first direction.