Patent ID: 7132719

Claim:
A semiconductor gate device, comprising: a silicon substrate having a field region and an active region; a gate dielectric layer on an upper surface of the active region of the silicon substrate; a gate on the gate dielectric layer; first and second sidewall dielectric layers on sidewalls of the gate; epitaxial silicon layers at both sides of the gate in trenches in the silicon substrate; first LDD regions in the silicon substrata below the second sidewall dielectric layers; second LDD regions at one side of the first LDD regions in the epitaxial silicon layers; source/drain regions under the second LDD regions; silicide layers on the gate and the second LDD regions; and a field oxide layer in the field region, wherein a bottom surface of the silicide layers and an upper surface of the field oxide layer are higher than the upper surface of the silicon substrate under the gate dielectric layer, and an upper surface of the epitaxial silicon layers is higher than the upper surface of the field oxide layer.