Patent ID: 7057946

Claim:
A semiconductor integrated circuit comprising: circuits having a certain function; a plurality of input terminals which receive input data to said circuits from outside; a plurality of output terminals which output data output from said circuits to the outside; a plurality of first registers connected in series, said plurality of first registers shifting stored data to respective adjacent registers in sequence, and said plurality of first registers being connected in one-to-one correspondence to said plurality of input terminals or to said plurality of output terminals; a plurality of second registers connected in series, said plurality of second registers shifting stored data to respective adjacent registers in sequence, and said plurality of second registers being connected in one-to-one correspondence to said plurality of input terminals or to said plurality of output terminals; a first scan input terminal formed at one end of said plurality of first series-connected registers; a first scan output terminal formed at another end of said plurality of first series-connected registers, said first scan output terminal being placed at an end portion; a second scan input terminal formed at one end of said plurality of second series-connected registers, said second scan input terminal being placed at the end portion at which the first scan output terminal is placed; and a second scan output terminal formed at the other end of said plurality of second series-connected registers.