Patent ID: 8886920

Claim:
An apparatus, comprising: an instruction fetch unit configured to fetch instructions including a first control transfer instruction (CTI); a branch prediction unit configured to generate predicted target addresses for CTIs, wherein one or more of the predicted target addresses are definitively determined before performance of the corresponding CTI and wherein one or more of the predicted target addresses cross a page boundary, wherein the branch prediction unit is not configured to definitively determine predicted targets addresses that cross a page boundary before performance of the corresponding CTI; and a branch target array having a plurality of entries; wherein the apparatus is configured to: store a predicted target address for the first CTI in an entry of the branch target array and associate a tag with the first CTI that is usable to access the entry, in response to determining that the predicted target address is not definitively determined prior to performance of the first CTI; perform the first CTI to determine an actual target address; and retrieve the predicted target address using the tag and compare the predicted target address with the actual target address to determine whether the predicted target address was correctly predicted; wherein the apparatus is configured to store predicted target addresses in the branch target array only for CTIs whose predicted target addresses are not definitively determined prior to performance.