Patent ID: 8384458

Claim:
A phase interpolation circuit, comprising: a first multiplexer, receiving a plurality of even order signals; a second multiplexer, receiving a plurality of odd order signals; an interpolator, receiving a first reference signal composed of one of the even order signals through the first multiplexer, and receiving a second reference signal composed of one of the odd order signals through the second multiplexer, wherein the interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal; and a duty-cycle repeater, adjusting a duty cycle of the differential input signal to generate a differential output signal with 50% of the duty cycle, wherein the interpolator comprises: a bias generating unit, generating a plurality of first biases according to the digital control signal, and generating a plurality of second biases according to a complement of the digital control signal; a current source, receiving the first biases and the second biases to generate a first current and a second current; a load unit; and an input unit, electrically connected between the load unit and the current source, and switching paths that the first current and the second current are conducted to the load unit according to the first reference signal and the second reference signal, so as to generate the differential input signal.