Patent ID: 8176458

Claim:
A method of designing a structured ASIC-based integrated circuit, the method comprising: generating, by a computing apparatus, an ad hoc circuit design defining, at least in part and in conjunction with a base array of function blocks, a functionality of the structured ASIC-based integrated circuit, wherein the function blocks are organized into clusters of one or more of the function blocks, wherein at least some of the clusters include a plurality of sequential elements and one or more H-trees respectively over one or more of the clusters, wherein at least one H-tree of the one or more H-trees has a plurality of endpoints, and wherein at least some of the plurality of endpoints terminate near at least one corresponding sequential element of the plurality of sequential elements; and imposing, by the computing apparatus, design constraints on the ad hoc circuit design including a first design constraint that one or more of the H-trees correspond to the clusters having sequential elements and a second design constraint that one or more of the H-trees, in conjunction with one or more conducting layers over the H-trees, couple the sequential elements of the corresponding clusters to one or more associated one-shot pulse generators such that the coupled sequential elements emulate flip-flop functionality as observed by the ad hoc circuit design.