Patent ID: 7620135

Claim:
A data processing apparatus, for receiving a communication signal that comprises a message containing a sync break interval with a unique bit pattern, the message containing a sync field interval identified by the sync break interval, a timing property of the sync field interval specifying a length of bit periods of the message, the apparatus comprising: an input port for receiving the communication signal; a reception circuit for sampling and processing bits from the message; a clock source circuit for supplying a sampling clock signal to the reception circuit to define time points for said sampling, the clock source circuit being arranged to adapt a frequency of the sampling clock signal to the timing property of the sync field interval, the clock source circuit being arranged to search for potential sync break intervals that match the unique bit pattern for a range of bit period values, the clock source circuit verifying for each potential sync break interval whether the sync field interval identified by that potential sync break interval specifies a bit period with a duration so that the sync break interval matches the unique pattern for the specified bit period, as a condition prior to supplying the sampling clock signal at the adapted frequency specified by the sync field interval identified by the potential sync break interval, wherein the supply of the sampling clock signal is suppressed after an end of a preceding message until said condition is met.