Patent ID: 8762608

Claim:
In a system on a chip (SOC) having (i) a control logic block, (ii) a processor block, and (iii) a serial communication interface, the serial communication interface performing a method comprising: receiving, in parallel, multiple bits of a first parallel signal stream from the control logic block of the SOC; receiving a selection signal, wherein the SOC is configured to operate in one of a plurality of personality modes based at least in part on the selection signal; based at least in part on the selection signal, placing the SOC into a read channel only personality mode of the plurality of personality modes, to facilitate testing of a read channel block included in the control logic block; based at least in part on the selection signal, converting the first parallel signal stream to a first serial signal stream; based at least in part on the selection signal, transmitting the first serial signal stream from a first serial port of the SOC; in response to transmitting the first serial signal stream from the first serial port of the SOC, receiving a second serial signal stream via a second serial port of the SOC; based at least in part on the selection signal, converting the second serial signal stream to a second parallel signal stream; based at least in part on the selection signal, transmitting the second parallel signal stream to the control logic block; in response to transmitting the first serial signal stream from the first serial port of the SOC, receiving a signal stream; based at least in part on the selection signal, transmitting the signal stream to the control logic block; and subsequent to receiving the signal stream and prior to transmitting the signal stream to the control logic block, delaying the signal stream by a delay amount such that the delay amount accounts for a time taken to convert the second serial signal stream to the second parallel signal stream.