Patent ID: 7772911

Claim:
A timing control circuit comprising: a digital delay circuit that receives a first clock signal having a first period, a group of second clocks having a second period with phases spaced apart from each other at prescribed intervals, an activate signal, and a selection signal for setting a delay amount, the digital delay circuit generating a signal delayed by a prescribed multiple of the first period based upon the selection signal, with an effective edge of the first clock signal at the time when the activate signal is activated serving as a reference, sampling the signal delayed by the prescribed multiple of the first period in response to respective ones of the group of second clocks to produce a plurality of signals, adding a delay to the plurality of signals, based upon the selection signal, the delay being a prescribed multiple of a length of time corresponding to a phase interval between adjacent clocks of the group of second clocks, and generating a timing signal based upon the plurality of signals to which the delay has been added to output the generated timing signal.