Patent ID: 7120829

Claim:
A processor-readable medium incorporating a program for instructions that configure a processor to function as a failure propagation path estimate system for estimating a logic state and a failure propagation path in a logic circuit by repeating an assumption and an implication operation of logic values based on a failure output terminal in the logic circuit, the system comprising: a re-calculation judging unit for judging whether a present process is an initial estimate process or a re-calculation following a measurement, such that the re-calculation is performed when an initial failure location estimate process has already taken place to reflect a measurement result of the measurement on the result obtained from the failure location estimate process; a failure propagation path searching unit for searching the failure propagation paths obtained from the previous estimate process; a measurement point neighborhood implication operation unit for verifying measured values of nodes in the logic circuit for each of the searched failure propagation paths, including a path whose logic state is implicated upon confirming the measured value of the nodes and a path causative of propagating a failure state to the measured value; and a failure propagation path updating unit for updating the failure propagation path according to the verified values, wherein the failure propagation path estimate is then continued based on the verified values.