Patent ID: 7700946

Claim:
A test structure for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures, comprising: a plurality of lower trenches and a plurality of upper trenches formed in a kerf region of a semiconductor wafer; a plurality of vias formed between said lower and upper trenches; said vias formed in accordance with a critical dimension associated with corresponding vias in a circuit region of the semiconductor wafer; and said lower and upper trenches in the kerf region formed so as to have a greater width with respect to a width of corresponding lower and upper trenches in a circuit region of the semiconductor wafer, wherein the width of the lower and upper trenches in the circuit region correspond to a defined minimum ground rule dimension; wherein said greater width of said lower trenches of said test structure is a function of a defined overlay tolerance with respect to said lower trenches and said vias, and said greater width of said upper trenches of said test structure is a function of a defined overlay tolerance with respect to said vias and said upper trenches, determined in accordance with the expression; Mx trench width= Mx minimum spacing+ N*Mx to prior level overlay specification; wherein Mx trench width represents the x th level of metallization in the semiconductor wafer, Mx minimum spacing represents said minimum ground rule dimension associated with said corresponding trenches in a circuit region of the semiconductor wafer, and Mx to prior level overlay specification represents said overlay tolerance with respect to said vias and said lower and upper trenches, and N represents a factor of said overlay tolerance.