Patent ID: 7619277

Claim:
A flash memory, comprising: a substrate; a plurality of control gates aligned in a first direction on the substrate; a plurality of trenches aligned in a second direction on the surface of the substrate, wherein a row of memory cells are defined under a control gate and between the trenches; a plurality of common source regions aligned in the first direction, each disposed in the substrate and the trenches between a pair of neighboring control gates and shared by two rows of memory cells defined by the pair of neighboring control gates; a plurality of isolation structures filling the respective trenches between the common source regions; a plurality of rows of drain regions, wherein each row of drain regions are aligned in the first direction and disposed in the substrate between the isolation structures at a side of a pair of neighboring control gates with a common source region between them; one common source line aligned in the second direction, disposed in the substrate at a bottom of one of the trenches, and electrically connected to the common source regions, wherein the one trench at which the one common source line is disposed is wider than the other trenches; a plurality of floating gates disposed between the control gates and the substrate between the respective common source regions and drain regions; a plurality of tunneling dielectric layers disposed between the floating gates and the substrate; and a dielectric layer disposed between the floating gates and the control gates.