Patent ID: 8563394

Claim:
A method comprising: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region, wherein the structure includes a shallow trench isolation (STI) between the NFET region and the PFET region; forming a mask over the PFET region to leave the NFET region exposed, wherein the forming of the mask over the PFET region includes forming the mask over approximately half of the STI; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region while the mask remains over the PFET region; forming a silicon germanium (SiGe) channel in the PFET region after the performing of the DHF; and etching a portion of the STI proximate the PFET region to substantially planarize the STI profile of the NFET region and an STI profile of the PFET region after the forming of the silicon germanium (SiGe) channel in the PFET region.