Patent ID: 7769985

Claim:
A processor for handling a load address dependency, the processor comprising an instruction unit and an execution unit and including a computer program comprising: computer program code for receiving, by the execution unit from the instruction unit, a load instruction corresponding to a memory address; wherein the execution unit comprises a miss queue and an instruction execution module (IEM); computer program code for determining, by the execution unit, whether there is at least one unexecuted preceding instruction corresponding to the memory address in the IEM; computer program code for, in the event there is at least one unexecuted preceding instruction corresponding to the memory address in the IEM, indicating, by the execution unit to the instruction unit, a local cache miss corresponding to the load instruction; computer program code for storing the load instruction in the miss queue; computer program code for tagging the load instruction as a local miss; computer code for determining whether every one of the at least one unexecuted preceding instructions have been executed; and computer code for, in the event every one of the at least one unexecuted preceding instructions have been executed, storing the load instruction in the IEM for execution.