Patent ID: 8385133

Claim:
A memory apparatus for storing data written by a data source at a first data rate DR 1 , the memory apparatus comprising: an internal data bus for receiving the data from the data source; N write buffers each coupled to receive data from the internal data bus at a second data rate DR 2 ; N memory controllers; N memory devices each coupled to receive data from a respective one of the write buffers, and each coupled to be controlled by a respective one of the memory controllers, and each including, (i) M data registers each coupled to receive and store data at a third data rate DR 3 from the respective one of the write buffers, and (ii) M memory cores each coupled to receive and store data at a fourth data rate DR 4 from a respective one of the data registers; a control sequence unit coupled to control the write buffers; and output means for reading data from the memory cores; wherein, M>=1, N>1, DR 2 *N>=DR 1 , DR 3 *M>=DR 2 , and DR 4 *M>=DR 2 .