Patent ID: 8372721

Claim:
A method of manufacturing embedded DRAM comprising the steps of: providing a semiconductor substrate having a surface; defining a first area of the substrate for forming an array NFET, a second area of the substrate for forming a logic PFET and a third area of the substrate for forming a logic NFET; depositing a high-K dielectric layer on the surface of the substrate, in all three areas; depositing a first metal oxide layer (CD 1 ) on the high-K dielectric layer, in all three areas; removing the first metal oxide layer (CD 1 ) from the third (logic NFET) area of the substrate; depositing a TiN conductive layer on the first metal oxide layer deposited on the first metal oxide layer deposited in the first and second areas of the substrate and on the high-K dielectric layer deposited in the third area of the substrate; depositing a layer of polysilicon on the TiN conductive layer, in all three areas; and patterning the high-K dielectric, the first metal oxide and the TiN conductive layers to form a first gate stack for the array NFET in the first area of the substrate, and a second gate stack for the logic PFET in the second area of the substrate, and patterning the high-K dielectric and TiN conductive layers to form a third gate stack for the logic NFET in the third area of the substrate.