Patent ID: 7538007

Claim:
A semiconductor memory device having a cell area and a peripheral area, comprising: a capacitor formed on the cell area of a substrate; an insulation layer formed by stacking a flowable insulation layer and an undoped silicate glass layer over the cell area and the peripheral area; a metal interconnection line formed on the insulation layer; wherein the flowable insulation layer is formed by a low pressure chemical vapor deposition method using reaction sources of silicon tetrahydride (SiH 4 ) and hydrogen peroxide (H 2 O 2 ) at a temperature ranging from approximately −10° C. to approximately 40° C. under a pressure of less than approximately 100 Torr, wherein the flowable insulation layer covers whole regions of the cell area and the peripheral area with a thickness less than a height of the capacitor and the undoped silicate glass layer is formed over the flowable insulation layer by employing a plasma enhanced chemical vapor deposition, and wherein the flowable insulation layer is formed by a thermal process employing one of a furnace thermal process at a temperature ranging from 200° C. to 650° C. and a rapid thermal process at a temperature greater than 300° C.