Patent ID: 6940115

Claim:
A memory cell, comprising: semiconductor material; a capacitor formed in said semiconductor material and having an inner electrode and an outer electrode; a first transistor for performing an operation selected from the group consisting of reading an information item from said capacitor and writing an information item to said capacitor; an insulating layer electrically insulating said inner electrode from said outer electrode; and a second transistor formed in said semiconductor material; said second transistor having a first contact region disposed adjoining said inner electrode thereby being directly connected to said inner electrode; said second transistor having a control contact region formed by said inner electrode of said capacitor; said second transistor having a second contact region for connecting to a voltage source; said second transistor enabling charging of said capacitor from a charge provided by the voltage source; said insulating layer having a region running along said outer electrode, said second contact region, and up towards said first contact region, said region of said insulating layer having a constant thickness allowing said second transistor to go into a conductive state when said inner electrode carries a high logic level.