Patent ID: 8885305

Claim:
A circuit comprising: a resistor capacitor (RC) clamp circuit including a first NMOS transistor having a first source, a first drain, and a first gate; a current mirror circuit including a first PMOS transistor having a second source, a second drain, and a second gate, and a second PMOS transistor having a third source, a third drain, and a third gate; and a silicon controlled rectifier (SCR) circuit including a first P+ contact, wherein the first source is coupled to a ground rail, the first drain is coupled to the second drain, to the second gate, and to the third gate, the second source is coupled to a power rail, the third source is coupled to the power rail, and the third drain is coupled to the first P+ contact, wherein during an ESD event the first NMOS transistor and the first PMOS transistor turn on to discharge a first current to the ground rail, and wherein the current mirror is utilized to provide a second current to the first P+ contact for turning on the SCR.