Patent ID: 7596707

Claim:
A system for limiting power consumption in a memory attached to a multiprocessor chip comprising: a multiprocessor chip; a plurality of memory controllers inside the multiprocessor chip in communication with a memory, wherein each memory controller includes, a bank counter logic configured to increment a local bank counter in response to a read or write request, the local bank counter indicating how many memory banks are open in the memory by the each memory controller; total bank counter logic configured to increment a total bank counter value, the total bank counter value indicating a total number of banks open by all the memory controllers; a time counter logic configured to keep track of time in increments of a set time interval; and a throttling logic configured to block the read or write request received subsequent to the total bank counter logic reaching a threshold value, the blocking the read or write request including temporarily storing the read or write request, and when terminating the blocking, resuming the read or write requests beginning with the at least one temporarily stored read or write requests; wherein a signal is sent to the memory controllers to increment the total bank counter values each time a bank is open by any of the memory controllers.