Patent ID: 8261041

Claim:
A memory management device comprising: a first memory management unit converting a logical address for accessing a cache memory into a physical address for accessing the cache memory, and included in a processor; a cache controller accessing the cache memory based on the physical address for accessing the cache memory, and included in the processor; an access history storage storing access history data indicating an access state to a main memory outside the processor, and included in the processor, wherein the access history includes a rewrite frequency for each location in the main memory; an address relation storage storing address relation data indicating a relationship between a logical address and a physical address in the main memory, and included in the processor; and a second memory management unit converting a logical address for accessing the main memory into a physical address for accessing the main memory based on the access history data and the address relation data, and accessing the main memory based on the physical address for accessing the main memory, and further, included in the processor.