Patent ID: 6977556

Claim:
A phase lock loop device comprising: a voltage controlled oscillator (VCO) having an output frequency Fosc; a loop filter coupled to said VCO; a phase detector coupled to said loop filter and said VCO; a frequency ratio generator, FRG coupled to said phase detector, said FRG receiving a reference signal having a reference frequency Fref and generating a comparison frequency signal G 1 whose dominant frequency component Fc is a desired frequency Fosc based on a fraction expansion of a ratio P/Q of said desired frequency Fosc and said reference frequency Fref, wherein P and Q are integer numbers, said ratio P/Q being realized according to a mathematical expression 1±1/p 1 ±1/p 2 ± . . . 1/p n , or realized according to a mathematical expression 1±1/q 1 ·{1±1/q 2 ·[ . . . (1± . . . 1/q m ))) . . . ]}, or realized according to a combination of said mathematical expressions, wherein n, m, and coefficients p 1 , p 2 , . . . , p n , q 1 , q 2 , . . . q m are positive integer numbers, and whereby all additions in said mathematical expressions are realized by an upper side-band SSB mixer, all subtractions are realized by a lower-side-band SSB mixer, and all fractions 1/p 1 through 1/p n and 1/q 1 through 1/q m are realized by frequency dividers.