Patent ID: 7126874

Claim:
A memory system for coupling a command, address or data signal between a memory controller and a memory device, comprising: a communication path coupled between the memory controller and memory device; a first strobe generator circuit in one of the memory controller or the memory device, the first strobe generator circuit being operable to generate a first periodic strobe signal and a second periodic strobe signal, the first strobe signal having signal transitions that are offset from signal transitions of the second strobe signal by 90 degrees; a first output latch in the memory controller or the memory device containing the first strobe generator circuit, the first output latch having an input terminal coupled to receive the command, address or data signal, an output terminal coupled to the communications path, and a clock terminal coupled to receive the first strobe signal; a first input latch in the memory controller or the memory device not containing the first strobe generator circuit, the first input latch having an input terminal coupled to the communications path, an output terminal, and a clock terminal; and a first strobe signal path coupling the second strobe signal from the first strobe generator circuit to the clock terminal of the first input latch.