Patent ID: 7619435

Claim:
A system for testing a semiconductor wafer using an in-line process control, the system comprising one or more computer readable memories including a plurality of instructions that when executed by a processor causes the processor to perform a process, the plurality of instructions comprising: one or more codes directed to applying a selected operating voltage on a gate of a test pattern with an associated device on a semiconductor wafer; one or more codes directed to measuring a first leakage current associated with the selected operating voltage; one or more codes directed to determining if the measured first leakage current is higher than a first predetermined amount to indicate an initial failure related to the associated device; and one or more codes directed to determining if the measured first leakage current is below the first predetermined amount to indicate that the associated device is subjected to a second voltage; one or more codes directed to applying the second voltage on the gate of the test pattern on the semiconductor wafer; one or more codes directed to measuring a second leakage current associated with the second voltage; one or more codes directed to determine if the second measured leakage current is higher than a second predetermined amount to indicate that the associated device is an extrinsic failure; one or more codes directed to determine if the second measured leakage current is below the second predetermined amount to indicate that the device is a good device; one or more codes directed to determine a breakdown voltage associated with the second measured leakage current value; and one or more codes directed to determine if the breakdown voltage is within a predetermined value; one or more codes directed to determine if the second measured leakage current value is within a predetermined range to indicate if one or more processes is stable.