Patent ID: 7051133

Claim:
An arbitration circuit for arbitrating bus access requests presented from a plurality of bus masters connected through a shared bus, comprising: a priority check block configured to receive multiple pieces of priority information outputted respectively from said plurality of bus masters, for comparing said pieces of priority information and specifying masters with a highest priority so as to output a check result; and a round robin block, said round robin block comprising, a round robin control unit configured to determine, through a round robin algorithm, a priority order of the bus access requests from said plurality of bus masters, a round robin masking unit configured to mask data of said check result with mask data to output a masked check result, said mask data being generated on the basis of said priority order, and a final selection unit for selecting a bus master whose bus access request should be accepted on the basis of said masked check result and said check result, said masked check result and said check result being consecutive data.