Patent ID: 7889555

Claim:
A flash memory device comprising: a NOR memory cell array enabling a random access comprising a 1-wordline string memory cell array that is operable in a random access mode, an X-decoder, a Y-decoder, and a sense amplifier circuit; a NAND memory cell array comprising a 32-wordline string memory cell array, an X-decoder, a Y-decoder, and a page buffer circuit; and a random access mode selection circuit, comprising a plurality of block selection transistors, operating to select whether to utilize the flash memory device as a random accessible memory for conducting an execute-in-place function or as a flash memory for storing normal data, wherein the NOR memory cell array programs data by a page unit and reads data in the random access mode, and wherein the block selection transistors are turned on while programming data into the 1-wordline string memory cell array and the 1-wordline string memory cell array is programmed by the page buffer circuit, and the block selection transistors are turned off while reading data from the 1-wordline string memory cell array and the sense amplifier circuit reads data from the 1-wordline string memory cell array.