Patent ID: 7584374

Claim:
A system comprising: at least one processor on a platform; a chipset coupled to the at least one processor, the chipset to identify when the at least one processor is to be put into a low power state or raised from a low power state to a normal operational state; a volatile memory store coupled to the at least one processor to store drivers and configuration data associated with the at least one processor in a portion of the volatile memory, wherein the portion of volatile memory is reserved for firmware use and inaccessible to an operating system on the platform; means for shadowing a first stage boot block to the volatile memory at boot time; means for shadowing a plurality of drivers and configuration data to the volatile memory store at boot time; means for executing the first stage boot block directly from the volatile memory, in response to a request to restore the platform to a normal operational state from a low-power state; and means for accessing a plurality of drivers and configuration data in the volatile memory store by the first stage boot block, in response to the request to restore the platform to a normal operational state from a low-power state.