Patent ID: 7907437

Claim:
A method of programming a resistance variable memory cell to a given logic state among a SET logic state, and a RESET logic state, where a resistance of the resistance variable memory cell is greater in the RESET logic state than in the SET logic state, the method comprising: generating a first periodic signal comprising a series of SET pulses; generating a second periodic signal comprising a series of RESET pulses; generating a write data signal indicating which of the SET logic state and the RESET logic state is to be programmed into the resistance variable memory cell; when the write data signal indicates that the resistance variable memory cell is to be programmed to the SET logic state: during one of the SET pulses, generating a DC bit line SET voltage having a declining staircase profile, and in response thereto applying a SET programming current to the resistance variable memory cell to program the resistance variable memory cell to the SET logic state, the SET programming current having the declining staircase profile of the DC bit line SET voltage, and performing no read verification for the memory cell programmed to the SET logic state; and when the write data signal indicates that the resistance variable memory cell is to be programmed to the RESET logic state: during a first one of the RESET pulses, generating a first DC bit line RESET voltage pulse having a first magnitude and in response thereto applying a first RESET programming current to the resistance variable memory cell, executing a verify read of the resistance variable memory cell by sensing a logic state of the resistance variable memory cell, and when the sensed logic state is different than the RESET logic state: during a second one of the RESET pulses, generating a second DC bit line RESET voltage pulse having a second magnitude greater than the first magnitude, and in response thereto applying a second RESET programming current to the resistance variable memory cell, wherein the second RESET programming current is greater than the first RESET programming current.