Patent ID: 7041563

Claim:
A method of fabricating a semiconductor device, comprising: forming a trench isolation layer at a predetermined region of a semiconductor substrate to define an active region; forming a pair of preliminary lightly doped diffusion layers in the active region, the preliminary lightly doped diffusion layers crossing the active region in parallel with each other; forming an oxide pattern to cover at least the top of the preliminary lightly doped diffusion layers and to define a channel region at a predetermined portion of the active region; forming a gate oxide layer on the channel region; forming a gate electrode whose edge is overlapped with the oxide pattern, the gate electrode being parallel to the preliminary lightly doped diffusion layer and covering the entire surface of the gate oxide layer and crossing over the active region; implanting impurities in the active region using the gate electrode as an ion-implantation mask to form a lightly doped diffusion layer including the preliminary lightly doped diffusion layer in the active region on both sides of the gate electrode; and forming a heavy doped diffusion layer in the active region on both sides of the gate electrode, the heavy doped diffusion layer being shallower than the lightly doped diffusion layer; wherein the oxide pattern is thicker than the gate oxide layer.