Patent ID: 7149850

Claim:
A memory control apparatus which performs a reading operation on a memory device at a request of a plurality of masters, comprising: read means for pre-reading data subsequent to data which any of the plurality of masters requests to read; a prefetch buffer for holding a result of the pre-reading, said prefetch buffer storing one or more sets of information including data, an address of the data, and a flag indicating the validity of the data; set means for setting a specific master among the plurality of masters; and control means for determining whether or not a present master which issues a read request is the specific master set by said set means when the read request is issued from the present master, comparing a requested address with the address of data stored in said prefetch buffer, checking the flag of the data, returning the data as read data of the present master when the addresses match each other, and the flag is a valid flag, storing a result of the pre-reading in said prefetch buffer when there is no matching data and it is determined that the present master is the specific master, and refraining from changing the content of said prefetch buffer when it is determined that the present master is not the specific master.