Patent ID: 8904253

Claim:
A System on a Chip (SoC), comprising: a plurality of Input/Output (I/O) pins; a plurality of I/O interface/ports, each I/O interface/port operatively coupleable to a respective set of I/O pins from among the plurality of I/O pins, wherein a first portion of the plurality of I/O interface/ports is powered on by default and a second portion of the plurality of I/O interface/ports is not powered on by default; a boundary scan chain, comprising a plurality of boundary scan cells, wherein at least one portion of the boundary scan chain passes through the plurality of I/O interface/ports; and circuitry and logic configured to facilitate boundary scan testing of a system including a main board on which the SoC is configured to be installed, the main board having a plurality of integrated circuits (ICs) installed thereon and interconnect wiring connecting selected I/O pins of the ICs to selected I/O pins of the plurality of I/O pins on the SoC when the SoC is installed, wherein the boundary scan testing is performed when the second portion of the plurality I/O interface/ports is not powered.