Patent ID: 6887773

Claim:
A method for incorporating one or more germanium layers in a standard CMOS flow, comprising: providing a silicon-based substrate using a standard CMOS process; depositing a first silicon oxynitride (Si x O y N z , herein after referred to SON) layer overlying the silicon-based substrate that serves as a mask; etching the first SON layer onto the silicon-based substrate to form a trench in the SON, thereby forming a SON patterned substrate as defined by a first region of the SON spaced apart laterally from a second region of the SON and above the silicon-based substrate; and depositing a first germanium layer into a portion of the trench that is incorporated as part of a CMOS process, the trench being formed by the first region of SON, the silicon-based substrate, and the second region of SON.