Patent ID: 8504789

Claim:
A bridge device for controlling a plurality of discrete memory devices, the bridge device comprising: a first clock domain having first logic circuits and first control circuits to operate in synchronization with a memory clock for issuing local commands to the discrete memory devices; a frequency controller for generating the memory clock using one of at least two clock divide ratios of a system clock to be provided to the bridge device; and a second clock domain having second logic circuits and second control circuits to operate in synchronization with the system clock for converting-global commands to be received synchronously with the system clock into the local commands synchronized with the memory clock; and a plurality of sets of dedicated local input/outputs, each of the plurality of sets of dedicated local input/outputs being configured to couple a respective local command of the local commands and respective data between a respective one of the discrete memory devices and the bridge device, whereby each of the plurality of discrete memory devices has a respective input/output port that is independently accessible, to the bridge device, amongst input/output ports of the plurality of discrete memory devices.