Patent ID: 7404164

Claim:
A method of modeling for use with an integrated circuit (IC) design, the method comprising: partitioning an edge of a shape in the IC design into a plurality of intervals; and assigning at least one dimension to each interval; wherein the partitioning includes: generating a core Voronoi diagram for the shape, the core Voronoi diagram being generated based on a L∞ metric, the L ∞ metric defining a distance between two points in the shape as the maximum of a horizontal distance and a vertical distance between the two points; and partitioning the edge based on a core element for each vertex of the core Voronoi diagram, the core element being one of a largest possible core element and a smallest possible core element; and wherein in the case that the core element is the largest possible core element, the intervals are as large as possible, and wherein in the case that the core element is the smallest possible core element, the intervals are as small as possible.