Patent ID: 7424507

Claim:
A logic device comprising: an adder array having a plurality of adder cells, the plurality of adder cells including a half adder cell and a full adder cell, the half adder cell and the full adder cell both having a first data input, a second data input, a sum output, and a carry output, the full adder cell also having a carry input, the adder array further having: a first row of adder cells having a first adder cell and a second adder cell, the second adder cell in the first row being a full adder, the first adder cell is being a full adder cell; and a second row of adder cells having a third adder cell, a fourth adder cell, and a fifth adder cell, the third adder cell being a half adder, the fourth adder cell being a full adder, and the fifth adder cell being a full adder, the sum output of the first adder cell being connected to the first input of the third adder cell, and the carry output of the first adder cell being connected to the first input of the fourth adder cell.