Patent ID: 8665658

Claim:
A semiconductor memory, comprising: a memory array having at least one bit line; a tracking bit line configured to emulate a voltage transition of the at least one bit line; and a global tracking circuit coupled to the tracking bit line and configured to generate a timing signal for generating a negative voltage with respect to ground on the at least one bit line of the memory array, the global tracking circuit including a pulse generator configured to generate a first signal; a replica write multiplexer coupled to the tracking bit line; a replica write driver coupled to the replica multiplexer and to a first voltage supply; and a first transistor coupled to the tracking bit line and to a second voltage supply, wherein the replica write multiplexer and replica write driver are configured to selectively couple the tracking bit line to the first voltage supply in response to the first signal, and the first transistor is configured to selectively couple the tracking bit line to the second voltage supply based on the first signal.