Patent ID: 8044682

Claim:
A field programmable gate array (FPGA), comprising: carry logic unit having a logic portion configured to execute a carry bit generating operation, the carry logic unit comprising an empowerment portion having a power voltage supplying terminal and a power sinking terminal, the empowerment portion being structured to support flow therethrough of an empowering current flowing through and empowering the carry bit generating operations of the logic portion of the carry logic unit when said carry bit generating operations are active, the empowering current flowing from the power voltage supplying terminal to the power sinking terminal; wherein the empowerment portion of the carry logic unit includes a unit empowering/depowering switching transistor connected to the power sinking terminal of the carry logic unit and structured and disposed so as to support flow of the empowering current through the switching transistor; and a programmable, empowerment/depowerment control signal provider connected to a gate terminal of the switching transistor and programmably configurable to provide depowering control signal to the gate terminal which causes the empowering/depowering switching transistor to interrupt the flow of the empowering current through the logic portion of the carry logic unit such that flow of leakage current through the logic portion is disabled when the flow of the empowering current is interrupted in response to provision of the depowering control signal to the gate terminal.