Patent ID: 7861062

Claim:
An instruction controlled data processing device comprising: an instruction issue unit that is configured to issue respective ones of instructions of program code in successive instruction cycles, the instructions including at least a first type of instruction and a second type of instruction; a clocking circuit that is configured to clock the instruction cycles; a register file with a read port and a write port; a plurality of functional units, each functional unit having a control input coupled to the issue unit, an operand input coupled to the read port and a result output coupled to the write port; and a control unit coupled to the issue unit, that is configured to route the result output of a first functional unit to the write port of the register file in response to instructions of the first type, and to the operand input of a second functional unit during an instruction cycle in response to instructions of the second type; wherein the clock circuit is configured to vary a rate of clocking the instruction cycles in dependence upon whether a current segment of the program code includes one or more instructions of the second type.