Patent ID: 7570504

Claim:
A memory device comprising: a memory array including a number of memory cells; an even row decoder located on a first side of the memory array; an odd row decoder located on a second side of the memory array; a single column decoder connected to the memory array; a number of parallel wordlines local to the memory array coupled to gate regions of memory cells, including one or more even wordlines coupled to the even row decoder, and one or more odd wordlines coupled to the odd row decoder, the odd wordlines arranged alternately with the even wordlines; and a number of strapping lines having lower resistance than the wordlines and connected to bypass portions of the wordlines within the memory array, wherein a strapping line connected to an odd wordline bypasses only a portion of the odd wordline within the memory array nearer the odd row decoder, wherein a strapping line connected to an even wordline bypasses only a portion of the even wordline within the memory array nearer the even row decoder.