Patent ID: 8861289

Claim:
A multiple port static random access memory (SRAM), comprising: a first word line and a second word line of a plurality of word lines; a first bit line pair, a second bit line pair, a third bit line pair, and a fourth bit line pair of a plurality of bit line pairs; an array of bit cells coupled to the plurality of word lines and the plurality of bit line pairs, wherein the array of bit cells comprises: a first bit cell having a first storage latch, and coupled to the first word line and the first bit line pair to access a first storage latch, and coupled to the second word line and the second bit line pair to access the first storage latch; and a second bit cell having a second storage latch, and coupled to the first word line and the third bit line pair to access a second storage latch, and coupled to the second word line and the fourth bit line pair to access the second storage latch; a first read/write data line pair of a first plurality of read/write data line pairs for accessing the array of bit cells, and a second read/write data line pair of a second plurality of read/write data line pairs for accessing the array of bit cells, wherein: the first read/write data line pair is coupled to the first bit line pair via first switching logic and coupled to the third bit line pair via second switching logic; and the second read/write data line pair is coupled to the second bit line pair via third switching logic and coupled to the fourth bit line pair via fourth switching logic; and a match detector which provides a match indicator based on whether at least a portion of a first access address matches at least a portion of a second access address, and in response to the match indicator indicating a match, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second read/write data line pair.