Patent ID: 7619945

Claim:
A memory power management system, comprising: a non-volatile rewritable memory array including a plurality of logical partitions, the memory array being configured in at least one memory plane, the memory array is fabricated above and is in contact with a substrate, the substrate including circuitry components fabricated on the substrate and positioned below the memory array and an interconnect structure operative to electrically couple the circuitry components with the memory array, the memory array including memory cells, each memory cell including an electrolytic tunnel barrier and a mixed valence conductive oxide; at least two charge pumps included in the circuitry components and electrically coupled with the non-volatile rewritable memory array, wherein one charge pump provides a positive voltage and another charge pump provides a negative voltage; and logic configured to control delivery of the voltages generated by the at least two charge pumps to each logical partition such that each logical partition is controlled independently of each other logical partition.