Patent ID: 7732856

Claim:
A non-volatile memory device comprising: a semiconductor substrate; a device isolation layer on the semiconductor substrate separating first and second active regions of the semiconductor substrate on opposite sides of the device isolation layer; first and second tunnel insulating patterns on the first and second active regions; first and second charge-trap patterns on the respective first and second tunnel insulating patterns wherein portions of the device isolation layer between the first and second charge-trap patterns are free of the first and second charge-trap patterns; a first blocking insulating layer on the first and second charge-trap patterns and on portions of the device isolation layer between the first and second charge-trap patterns so that the first and second charge-trap patterns are between the first blocking insulating layer and the first and second tunnel insulating patterns; a word line on the first blocking insulating layer so that the first blocking insulating layer is between the wordline and the first and second charge-trap patterns and between the word line and the device isolation layer; third and fourth tunnel insulating patterns on the first and second active regions spaced apart from the first and second tunnel insulating patterns, wherein each of the first, second, third, and fourth tunnel insulating patterns comprises a first insulating material having a first dielectric constant; a second blocking insulating layer directly on the third and fourth tunnel insulating patterns and on portions of the device isolation layer between the third and fourth tunnel insulating patterns, wherein the second blocking insulating layer is spaced apart from the first blocking insulating layer, and wherein each of the first and second blocking insulating layers comprises a second insulating material having a second dielectric constant, and wherein the first and second dielectric constants are different; and a gate electrode line on the second blocking insulating layer so that the second blocking insulating layer is between the gate electrode line and the third and fourth tunnel insulating patterns and between the gate electrode line and the device isolation layer, wherein a separation between the selection line and the first and second active regions of the semiconductor substrate is less than a separation between the word line and the first and second active regions of the semiconductor substrate.