Patent ID: 7705642

Claim:
A delay locked loop comprising: a delay line comprising a plurality of differential delay elements having v nbias inputs and v pbias inputs; a biasing circuit comprising: an input for receiving a control voltage, a V nbias output for outputting a V nbias voltage for input to the v nbias inputs of the differential delay elements, and a v pbias output for outputting a v pbias voltage for input to the v pbias inputs of the differential delay elements; a direct connection between the input and the v pbias output such that the V pbias output tracks the control voltage; circuitry that produces the V nbias voltage from the control voltage such that the V nbias voltage is near a supply voltage V DD over a first control voltage range, sharply declines over a second control voltage range that follows the first control voltage range, and less sharply declines in a substantially linear manner over a third control voltage range that follows the second control voltage range; and the circuitry comprises: a pull-up network for pulling up the V nbias voltage when the control voltage is low; a pull-down network for pulling down the V nbias voltage when the control voltage is high; and a variable resistive element for impeding the pull-down network from pulling down the V nbias .