Patent ID: 8639992

Claim:
A soft error rate (SER) detector circuit comprising: a plurality of detector arrays; each of the plurality of detector arrays comprising a plurality of SER test structures coupled in series; each of the plurality of SER test structures comprising: a plurality of detector elements coupled in series to form a detector chain, wherein the detector chain has an output node; a counter comprising an input and a plurality of flip-flops coupled in series; and a scan multiplexer having an input coupled to the output node of the detector chain, and having an output coupled to the input of the counter, and configured to generate a multiplexer output that serves as a clock input of the counter, wherein the counter and the scan multiplexer are controlled to support a single event transient (SET) detect mode or a single event upset (SEU) detect mode of the SER detector circuit, wherein the detector chain serves as a radiation target and the counter is enabled to count SETs detected by the detector chain when the SER detector circuit is in the SET detect mode, and wherein the detector chain and the counter are disabled, and the plurality of flip-flops of the counter serve as the radiation target to detect SEUs, when the SER detector circuit is in the SEU detect mode; and control logic elements to control operation of the plurality of detector arrays.