Patent ID: 7206883

Claim:
An interruption control system for use with a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device and a second peripheral device, said interruption control system comprising: a first input/output interruption controller coupled to said first peripheral device and said south bridge chip, and asserting a wake-up signal to said south bridge chip in response to a first interrupt signal issued by said first peripheral device so as to deactivate a power-saving state of said computer system; a second input/output interruption controller coupled between said second peripheral device and said north bridge chip for communicating said second peripheral device with said north bridge chip, and in response to a second interrupt signal issued by said second peripheral device, asserting a third interrupt signal; and an interruption control device bus interconnecting said first input/output interruption controller, said second input/output interruption controller and said CPU, said first input/output interruption controller asserting said wake-up signal to deactivate said power-saving state of said computer system in response to said third interrupt signal asserted by said second input/output interruption controller and transmitted on said interruption control device bus.