Patent ID: 8750059

Claim:
A memory structure comprising: a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words; a plurality of first bits, each first bit of the plurality of first bits associated with a memory word of the plurality of memory words of the each row of the plurality of rows of the memory array, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit; a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words associated with a corresponding memory word of the plurality of memory words of the each row of the plurality of rows of the memory array; a plurality of second bits, each second bit of the plurality of second bits associated with a redundancy word of the plurality of redundancy words of the each row of the plurality of redundancy rows, wherein a logic state of the each second bit indicates whether the redundancy word associated with the each second bit has had a failed bit; and an error correction engine configured to generate an error-repair flag based on the logic state of a corresponding first bit associated with a memory word and presence of an error in the memory word; or to generate the error-repair flag based on the logic state of a corresponding second bit associated with a redundancy word and presence of an error in the redundancy word.