Patent ID: 8291173

Claim:
A logic device, comprising: first and second data bus interfaces configured to be coupled to a bidirectional data bus, the bidirectional data bus configured to transfer read data in a first direction between the first and second bus interfaces and to transfer write data in a second direction opposite of the first direction between the first and second bus interfaces; and a bypass circuit coupled to the first and second data bus interfaces and configured to store write data from the bidirectional data bus to transfer the write data from the first data bus interface to the second data bus interface in the second direction instead of over the bidirectional data bus to allow read data to be transferred on the bidirectional data bus from the second data bus interface to the first data bus interface in the first direction, the bypass circuit further configured to restore stored write data to the bidirectional data bus to complete the transfer of the write data, wherein the bypass circuit is configured to be controlled responsive to a bypass signal.