Patent ID: 7724063

Claim:
A pseudo-differential switched-capacitor circuit, comprising: a differential floating sampling (DFS) circuit that has a pseudo-differential architecture with a common-mode gain value of one (1), said DFS circuit having a differential positive input (V in +) and a negative input (V in −), and said DFS circuit having a first single-ended amplifier and a second single-ended amplifier, wherein the first single-ended amplifier has having a differential positive output (V out +) and the second single-ended amplifier has a differential negative output (V out −); and an integrator electrically coupled to the differential positive/negative outputs, the integrator controllably feeding back integrator output to inputs of the first single-ended amplifier and the second single-ended amplifier of the DFS circuit, and the integrator receiving common-mode voltage disturbance at the differential positive output (V out +) and negative output (V out −), thereby stabilizing output common-mode level of the differential positive output (V out +) and negative output (V out −) of the DFS circuit at a desirable level; wherein the integrator includes: an integrator amplifier having a positive input and a negative input; a first sample capacitor and a second sample capacitor which are connected in parallel; and an integrator capacitor which is connected between an output of the integrator amplifier and the negative input of the integrator amplifier; wherein the integrator amplifier is connected to the first and second sample capacitors via switches.