Patent ID: 8067283

Claim:
A method for fabricating a semiconductor device, comprising: providing a substrate having a first device region and a second device region; forming a first gate insulating layer and a second gate insulating layer in the first device region and the second device region, respectively; blanketly forming a gate layer; patterning the gate layer by removing a portion of the first gate insulating layer and the second gate insulating layer to form a first gate and a remaining first gate insulating layer in the first device region, and form a second gate and a remaining second gate insulating layer in the second device region, wherein the remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness; blanketly forming a spacer insulating layer having a third thickness; and performing an anisotropic etching process to remove a portion of the spacer insulating layer, a portion of the remaining first gate insulating layer, and a portion of the remaining second gate insulating layer, such that tops of the first gate and the second gate are exposed, a pair of first spacers and a pair of second spacers are left on sidewalls of the first gate and the second gate, and a portion of the substrate is exposed, wherein the anisotropic etching process is performed without masks shielding the first spacers and the second spacers; wherein the first spacers cover a portion of the remaining first gate insulating layer and the second spacers cover a portion of the remaining second gate insulating layer.