Patent ID: 6949451

Claim:
A method of fabricating a semiconductor-on-insulator chip, comprising the steps of: providing a donor wafer substrate; implanting ions into said donor wafer substrate to form an implanted layer and a semiconductor film overlaying said implanted layer; forming a recess-resistant layer of silicon nitride having an etch rate of less than 10 angstroms per minute in a wet cleaning solution, said recess-resistant layer overlying the semiconductor film, the recess-resistant layer forming the topmost layer of the a donor wafer; providing a target wafer comprising of a recess-resistant layer of silicon nitride having an etch rate of less than 10 angstroms per minute in a wet cleaning solution, said recess-resistant layer overlying a first dielectric layer, the first dielectric layer overlying a substrate, the target wafer having a top surface; beta bonding the top most recess-resistant layer of the donor wafer to the recess-resistant top surface of the target wafer; cleaving the semiconductor film from the donor wafer, the semiconductor film adhering to the target wafer so as to provide a substrate device comprising a the semiconductor film overlying a buried insulator stack, the buried insulator stack comprising the recess-resistant layer overlying the first dielectric layer; annealing the target wafer to strengthen the bond between semiconductor film and the target wafer after the semiconductor film adheres to the target wafer, and after the cleaving step forms the semiconductor film; patterning a portion of the semiconductor film to form semiconductor mesas; and forming active devices on the semiconductor mesas.