Patent ID: 7518186

Claim:
A vertical gate semiconductor device, comprising: a first conductivity type drain region formed on a substrate; a second conductivity type first body region provided on the drain region; a trench formed so as to pass through the first body region; a gate electrode formed in the trench with a gate insulting film interposed so as to form a recessed portion at an upper part of the trench; an insulating film formed on the gate electrode so as to occupy the recessed portion partway; a first conductivity type source region formed in at least a region of an upper part of the first body region which serves as a wall part of the trench so as to overlap in level with at least an upper part of the gate electrode; a second conductivity type second body region formed in a region of the upper part of the first body region other than the at least region thereof so as to be adjacent to the source region in a direction that the trench extends; a second conductivity type third body region formed in respective upper parts of the source region and the second body region; and a wiring layer in contact with the source region, the second body region, and the third body region.