Patent ID: 7945050

Claim:
An integrated circuit comprising: a transmit data path to transmit data transmissions to one or more memory devices coupled to the memory controller, the transmit data path including, scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other for each data transmission, XOR logic having as a first input the N pseudo random outputs of the scrambling logic and having as a second input M data bits, the XOR logic to output, in parallel, M scrambled bits for each data transmission, and a transmitter coupled with the XOR logic, the transmitter to transmit, for each data transmission, the M scrambled bits to the one or more memory devices via a memory interconnect, wherein the M scrambled bits have a pseudo random pattern, the one or more memory devices to store the M scrambled bits; and a receive data path to receive data transmissions from the one or more memory devices, the receive data path including, unscrambling logic to generate, in a first order for each data transmission to be received, N pseudo random outputs that are uncorrelated with each other in parallel, a receiver to receive, in parallel, transmissions of M scrambled bits from the memory interconnect in a second order, a reorder buffer to match the first order of the outputs of the unscrambling logic to the second order of the data received, and a second XOR logic having as a first input the M scrambled bits from the memory interconnect and having as a second input the N pseudo random outputs of the unscrambling logic from the reorder buffer, the second XOR logic to output, in parallel, M unscrambled bits.