Patent ID: 7376755

Claim:
A programmable TCP/IP processor engine, said processor having RDMA capability and used for processing Internet Protocol packets, said TCP/IP processor engine comprising: a checksum component for TCP/IP checksum verification and for new checksum generation; a data memory for storing said packets; an execution resource; a packet look-up interface for assisting an execution resource and an instruction sequencer for providing access to said data packets or predetermined data packet fields thereof; an instruction decoder to direct said TCP/IP processor engine operation based on the results of a classification processor; a sequence and window operation manager providing specific segmenting, sequencing and windowing operations for use in TCP/IP data sequencing calculations; and further comprising: a hash engine used to perform hash operations against predetermined fields of the packet to perform a hash table walk to determine the correct session entry for said packet; a register file for extracting predetermined header fields from said packets for TCP processing; pointer registers for indicating data source and destination; context register sets for holding multiple contexts for packet execution; said multiple contexts allowing, in response to a given packet execution stalling, another context to be invoked to enable said TCP/IP processor engine to continue the execution of another packet stream; said TCP/IP processor engine having a cache for holding recently or frequently used session entries, including connection IDs, for local use; and further having an interface for informing a packet scheduler of the connection IDs that are cached for each TCP/IP processor engine resource.