Patent ID: 8176380

Claim:
An apparatus, comprising: an input that receives an LDPC (Low Density Parity Check) coded signal; and an LDPC decoder that employs an LDPC matrix to decode the LDPC coded signal to make an estimate of an information bit encoded therein; and wherein: the LDPC matrix, composed of a plurality of sub-matrices each having a common size, is partitioned into a left hand side matrix and a right hand side matrix; each sub-matrix within the right hand side matrix is an all zero-valued sub-matrix except those sub-matrices identified below in (a), (b), and (c): (a) each sub-matrix located on a diagonal of the right hand side matrix is a CSI (Cyclic Shifted Identity) sub-matrix; (b) in every row between a first row and a second to bottom row, which is above and adjacent to a bottom row, of the right hand side matrix, inclusive, each sub-matrix located on a right hand side of and adjacent to a sub-matrix located on the diagonal of the right hand side matrix is also a CSI sub-matrix; and (c) a plurality of sub-matrices located within a left hand column of the right hand side matrix.