Patent ID: 8452985

Claim:
A circuit configuration apparatus that reconfigures a reconfigurable logic circuit so as to configure an execution circuit, the circuit configuration apparatus comprising: a non-transitory memory that (i) stores computer executable instructions and (ii) stores a first circuit configuration information set that defines a first cryptographic processing circuit for executing cryptographic processing in accordance with a first cryptosystem used for a first content; and a processor that executes the computer executable instructions to function as: a configuration unit operable to reconfigure the reconfigurable logic circuit in accordance with a circuit configuration information set input thereto so as to configure the execution circuit; a reading unit operable to read the first circuit configuration information set from the non-transitory memory, and to output the first circuit configuration information set to the configuration unit; an acquisition unit operable to acquire a second circuit configuration information set that has been subject to cryptographic processing according to the first cryptosystem and that defines a second cryptographic processing circuit for executing cryptographic processing in accordance with a second cryptosystem used for a second content, the second cryptosystem being different from the first cryptosystem; a control unit operable to cause the first cryptographic processing circuit to decrypt the second circuit configuration information set that has been subject to encryption processing in accordance with the first cryptosystem and that has been acquired by the acquisition unit; and a writing unit operable to write the second circuit configuration information set into the non-transitory memory, wherein each of the first circuit configuration information set and the second circuit configuration information set stored in the non-transitory memory includes encryption processing circuit information and decryption processing circuit information, the encryption processing circuit information indicating a structure of an encryption processing circuit that executes encryption processing in accordance with the corresponding cryptosystem, and the decryption processing circuit information indicating a structure of a decryption processing circuit that executes decryption processing in accordance with the corresponding cryptosystem, and wherein the processor further functions as a deletion unit operable to delete, from the non-transitory memory, encryption processing circuit information included in a circuit configuration information set that corresponds to a cryptosystem that has been broken, without deleting decryption processing circuit information included in the circuit configuration information set.