Patent ID: 7716623

Claim:
A method of selecting logic functions for implementation in a logic array block that includes (1) a plurality of logic elements, each of which is capable of performing one of the logic functions, and (2) a plurality of LAB line circuits, each of which is capable of selecting a LAB line signal from a plurality of signal sources and making that LAB line signal available for selection as an input to any of the logic elements, the method comprising: selecting a seed logic function to initiate the formation of a cluster of logic functions for implementation in the logic array block; identifying each remaining logic function that is attached to a net that has at least one terminal that is part of the cluster; for each logic function identified in the identifying, computing a value of gain that can be achieved by adding the identified logic function to the cluster, the gain value being incremented by a greater amount if the net is attached to an input of the identified logic function than if the net is attached to an output of that function; and using relative values of the gain as part of a process for selecting one of the remaining logic functions for addition to the cluster.