Patent ID: 7831882

Claim:
A memory controller adapted for communication with at least one memory device over a signal link, comprising: a transmitter coupled to the signal link to transmit data in a normal mode of operation to a memory device, the signal link comprising signal lines; error protection generator logic, coupled to the transmitter, configured to dynamically add an error detection code to at least a portion of the data to be transmitted; and a retry mechanism, operatively coupled to the signal link, comprising: an input to receive an error indication from the memory device, and an output to re-transmit the data in a remedial mode of operation, the retransmitted data having a modified transmission parameter in the remedial mode of operation as compared to the normal mode of operation, the modified transmission parameter selected from the group consisting of voltage, current, timing, and data rate in response to the error indication, wherein the memory controller is configured to exit the remedial mode of operation after retransmission of the data in the remedial mode of operation.