Patent ID: 8258020

Claim:
A method of forming a vertical interconnect for a memory device, comprising: providing a substrate having a surface region; defining a cell region, a first peripheral region, and a second peripheral region; forming a first thickness of dielectric material overlying the surface region; forming a first bottom wiring structure spatially configured to extend in a first direction overlying the first dielectric material for a first array of devices; forming a second thickness of a dielectric material overlying the first wiring structure; forming an opening region in the first peripheral region extending in a portion of at least the first thickness of dielectric material and the second thickness of dielectric material to expose a portion of the first wiring structure and to expose a portion of the substrate; depositing a second bottom wiring material overlying the second thickness of dielectric material and filling the opening region to form a vertical interconnect structure in the first peripheral region; and forming a second bottom wiring structure from the second wiring material for a second array of devices, the second bottom wiring structure being separated from the first bottom wiring structure by at least the second thickness of dielectric material, the second bottom wiring structure being spatially configured to extend in the first direction, the first wiring structure and the second wiring structure being electrically connected by the vertical interconnect structure in the first peripheral region to the substrate.