Patent ID: 7526593

Claim:
A bus interface device for transmitting data transfer requests from a plurality of clients as packets on a bus, the device comprising: a queue configured to store a plurality of data transfer requests from the plurality of clients, each data transfer request specifying a target address range; control logic configured to generate a send condition signal; packet forming logic configured to form a packet, in response to the send condition signal, from at least one of the data transfer requests in the queue, the packet forming logic being further configured to combine two or more of the data transfer requests in the queue into one packet in the event that the two or more data transfer requests being combined specify respective target address ranges that are mergeable, wherein the data transfer requests are write requests; output logic coupled to the packet forming logic and configured to drive the packet onto the bus; and dynamic holdoff timer logic coupled to the packet forming logic and the control logic and configured to determine a holdoff period for a next packet based on a level of bus activity and to detect expiration of the holdoff period, the dynamic holdoff timer logic being further configured to receive size information for a formed packet from the packet forming logic and to dynamically update the holdoff period for the next packet based at least in part on the size information, the size information representing an amount of write data included in the formed packet the control logic being configured to generate the send condition signal in response to expiration of the holdoff period.