Patent ID: 7613237

Claim:
A method of determining a failure of a clock signal of a differential serial link, the method including: providing a first integrated circuit having a phase generator constructed and arranged to provide a programmable shift of a clock signal based on selective interpolating between first and second phases of the clock signal relative to a digital phase value, providing a second integrated circuit constructed and arranged to receive the clock and digital data signals sent by the first integrated circuit, sending the clock and digital data signals substantially simultaneously through the link from the first integrated circuit to the second integrated circuit, determining, whether the digital data signals can be sampled reliably by the second integrated circuit relative to the digital phase value, shifting the clock signal, based on changing the digital phase value supplied to the phase generator to a selected one of a plurality of digital phase increments across a period of a single clock cycle, towards a transition of the data signals until a failure is detected relative to an identified phase value such that the digital data signals cannot be sampled reliably by the second integrated circuit, and based on the detection of the failure relative to the corresponding identified phase value, establishing a time margin of the clock signal wherein the digital data signals can be sampled reliably by the second integrated circuit.