Patent ID: 8392797

Claim:
An error correcting controller, comprising: a first flash memory interface, for connecting a host controller; a second flash memory interface, for connecting a flash memory; a micro-processor unit, electrically connected to the first flash memory interface and the second flash memory interface; an error creation unit, electrically connected to the micro-processor unit; and a first error correcting unit, electrically connected to the micro-processor unit, wherein when the host controller needs to write data into the flash memory, the first error correcting unit generates a first error correcting code and stores the data and the first error correcting code in the flash memory, wherein when the host controller needs to read the data from the flash memory, the micro-processor unit reads the data and the first error correcting code from the flash memory and the first error correcting unit determines according to the first error correcting code whether the read data contains at least one error bit and whether the at least one error bit is correctable, when the first error correcting unit determines that the read data has the at least one error bit and the at least one error bit is correctable, the error creation unit generates correctable error data and the micro-processor unit transmits the correctable error data to the host controller, wherein the correctable error data is generated according to the data that has been error corrected according to the first error correcting code and can be corrected by the host controller, wherein when the first error correcting unit controller determines that the read data contains the at least one error bit and the at least one error bit is not correctable, then the micro-processor unit transmits default error data to the host controller, and the host controller determines that the default error data contains a plurality of default error bits and the default error bits are not correctable, wherein when the host controller needs to write the data into the flash memory, the second error correcting unit corrects the data according to the second error correcting code, wherein the host controller further comprises a third error correcting unit, wherein the data further comprises a second error correcting code, further comprising a second error correcting unit electrically connected to the micro-processor unit, wherein the second error correcting unit has a maximum number of error correcting bits equal to the maximum number of error correcting bits of the third error correcting unit.