Patent ID: 7636828

Claim:
A processor-implemented method for automatic adjustment of timing of a write and read strobes of a memory having a double data rate (DDR) interface, the processor-implemented method comprising: performing sequentially a plurality of respective write-read operations for all combinations of a first plurality of values for the timing of the write strobe and a second plurality of values for the timing of the read strobe, each write-read operation of the sequence including writing write data to a location in the memory via the DDR interface with the timing of the write strobe set to one of the first plurality of values and subsequently reading read data from the location in the memory via the DDR interface with the timing of the read strobe set to one of the second plurality of values; determining a first range of the first plurality of values and a second range of the second plurality of values for which each combination of a value in the first range and a value in the second range has the read data match the write data for the respective write-read operation for the combination, wherein a largest possible value is obtained for a lesser of a magnitude of the first range and a magnitude of the second range; and setting the timing of the write strobe to a center of the first range and setting the timing of the read strobe to a center of the second range.