Patent ID: 7439130

Claim:
A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first insulating layer on a top surface of a semiconductor substrate; etching the first insulating layer to form a trench; depositing a first conductive layer on the insulating layer and filling the trench; performing a first planarization process to expose a top surface of the first insulating layer while leaving the first conductive layer in the trench; sequentially forming a second insulating layer, a third insulating layer, and a fourth insulating layer on the planarized first insulating layer; etching the fourth insulating layer to form a first pattern for a contact plug area and a capacitor area of the first conductive layer; depositing a fifth insulating layer on the fourth insulating layer having the first pattern and planarizing the fifth insulating layer; forming a second pattern on the fifth insulating layer to expose the fifth insulating layer on the contact plug area and the capacitor area; etching the exposed fifth insulating layer using the second pattern as a mask to expose the first pattern; etching the third insulating layer using the first pattern as a mask to expose the second insulating layer; etching the exposed second insulating layer to expose the first conductive layer in the contact plug area and the capacitor area; forming a second conductive layer on the exposed first conductive layer and inner sidewalls of the exposed second, third, fourth, and fifth insulating layers; forming a capacitor insulating layer on the second conductor formed in the capacitor area; and forming a third conductive layer in the contact plug area and the capacitor area.