Patent ID: 7877637

Claim:
A multicore abnormality monitoring device comprising: plural processor cores; and a first communication path connecting the plural processor cores to one another and integrated with the plural processor cores in one package, wherein each of the plural processor cores includes an arithmetic processing part, a temporary storage part mainly used by the arithmetic processing part, and a second communication path connecting the arithmetic processing part and the temporary storage part so that the arithmetic processing part accesses the temporary storage part, wherein at least two processor cores of the plural processor cores are respectively formed as a monitoring side core and a monitored side core, the monitoring side core being configured to monitor an operation state of the monitored side core, wherein, in the monitored side core, the arithmetic processing part is configured to access the temporary storage part through the second communication path to execute a first writing operation every predetermined time, and wherein, in the monitoring side core, the arithmetic processing part is configured to access the temporary storage part through the second communication path to execute a second writing operation corresponding to a result of the first writing operation in the monitored side core every predetermined time while monitoring the result of the first writing operation in the monitored side core through the first communication path, and determine that the operation state of the monitored side core is abnormal when a predetermined determination condition based on the result of the second writing operation is satisfied, characterized in that the monitoring side core further includes a first protection part configured with an access checking part and an address information storage part, wherein the address information storage part is configured to store, in advance through the arithmetic processing section of the monitoring side core, address information of the temporary storage part of the monitoring side core and an access prohibiting mode to the address concerned, wherein the access checking part is configured to check whether an address and an access made through the first communication path by the arithmetic processing part of the monitored side core and an access mode thereof are coincident with the address and the access prohibiting mode stored in the address information storage part, and wherein the first protection part is configured to prohibit an access to the temporary storage part of the monitoring side core by the monitored side core when coincidence of address is determined through the access checking part.