Patent ID: 8884341

Claim:
An integrated circuit comprising: a gate electrode disposed over a substrate; and a source/drain (S/D) region disposed adjacent to the gate electrode, the S/D region comprising: a diffusion barrier structure at least partially disposed in a recess of the substrate, wherein the diffusion barrier structure comprises an epitaxial layer, wherein the epitaxial layer comprises a first region and a second region, wherein the first region is thinner than the second region and is adjacent to the gate electrode, and the second region is distant from the gate electrode; and an N-type doped silicon-containing structure disposed over the diffusion barrier structure, wherein the first region of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate and the second region of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.