Patent ID: 8391060

Claim:
A nonvolatile memory comprising: a memory cell comprising a first memory transistor and a second memory transistor; and a drive circuit, wherein the first memory transistor and the second memory transistor are formed on a SOI substrate, wherein each of the first memory transistor and the second memory transistor comprises a floating gate and a control gate over the floating gate, wherein the control gate of the first memory transistor is electrically connected to a first word line, wherein the control gate of the second memory transistor is electrically connected to a second word line, wherein each of the first memory transistor and the second memory transistor is configured to store data of two bits or more, wherein one of a source and a drain of the first memory transistor is electrically connected to a source line, and wherein one of a source and a drain of the second memory transistor is electrically connected to a bit line, wherein the other one of the source and the drain of the first memory transistor is electrically connected to the other one of the source and the drain of the second memory transistor, wherein the first word line, the second word line, the bit line, and the source line are electrically connected to the drive circuit, wherein the memory cell is configured to erase data of the first memory transistor without erasing data of the second memory transistor by setting the bit line and the source line at a first voltage, the first word line at a second voltage, and the second word line at a third voltage, and wherein the memory cell is configured to erase data of the second memory transistor without erasing data of the first memory transistor by setting the bit line and the source line at the first voltage, the first word line at the third voltage, and the second word line at the second voltage.