Patent ID: 6967894

Claim:
A non-volatile semiconductor memory device comprising: a memory core circuit including a cell array in which electrically rewritable and non-volatile memory cells are arranged therein, decoders configured to select the memory cells, and sense amplifiers configured to perform data read and write of said cell array; and a peripheral circuit including a memory controller configured to control data read and write in communication with said memory core circuit, wherein said memory controller comprises: an oscillator configured to generate an internal clock signal; a timing control circuit configured to control timings of data read and write of said cell array as synchronous with said internal clock signal; and a merge clock generation circuit configured to generate based on an external timing signal and said internal clock signal a merge clock signal serving for timing controlling a circuit portion in said peripheral circuit, said merge clock signal being defined as having a first signal period in which said external timing signal serves as a clock source and a second signal period without overlapping said first signal period, in which said internal clock signal serves as a clock source.