Patent ID: 8154116

Claim:
A layered chip package comprising a plurality of layer portions stacked, each of the plurality of layer portions including a semiconductor chip, the layered chip package further comprising a heat sink and wiring, wherein: each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces; the heat sink has at least one first portion, and a second portion coupled to the at least one first portion; the at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions; the second portion is in contact with one of the side surfaces of each of at least two of the plurality of layer portions; any two or more layer portions among the plurality of layer portions are each configured to further include a plurality of electrodes, each of the electrodes being connected to the semiconductor chip and having an end face located in at least one of the four side surfaces of the layer portion that the second portion of the heat sink is not in contact with; and the wiring is connected to the end faces of the plurality of electrodes of the two or more layer portions.