Patent ID: 8883636

Claim:
A semiconductor process for forming special pattern features, comprising: sequentially forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate having two first predetermined regions and a second predetermined region, wherein said core bodies have the same width and said two first predetermined regions are respectively located at both sides of said second predetermined region; forming spacers on sidewalls of said core bodies, wherein adjacent spacers are spaced-apart by a recess; forming first photoresists respectively on said two first predetermined regions encompassing several said core bodies; removing said core bodies not covered by said first photoresists so that said spacers in said second predetermined region are spaced-apart on said hard mask layer; using said spacers and said remained core bodies as a mask to pattern said hard mask layer into a plurality of spaced-apart large and small hard mask bodies, wherein said hard mask bodies in said two first predetermined regions are larger than said hard mask bodies in said second predetermined region; forming second photoresists respectively on said two first predetermined regions covering said hard mask bodies; and using said second photoresists and said hard mask bodies as a mask to pattern said target layer.