Patent ID: 7074629

Claim:
A method for determining an effective vacancy diffusion area for a silicon-on-insulator structure comprising the steps of: forming two or more test substructures on the substrate, each test substructure comprising: a first metal structure disposed on a substrate, one or more intermediate layers disposed above the first metal structure; a second metal structure disposed above the one or more intermediate layers, wherein at least a portion of the second metal structure is above the first metal structure and the second metal structure is smaller than the first metal structure; a first via passing through the intermediate layers and connecting the first metal structure to the second metal structure; one or more third metal structures disposed above the one or more intermediate layers and the first metal structure, and separated from the second metal structure by a dielectric material; and one or more second vias passing through the intermediate layers and connecting the first metal structure to the third metal structures, each second via located outside of a radius from a center of the first via, which radius is different for each test substructure; measuring a resistance between the second metal structure and the third metal structure(s) of each test substructure before and after thermal stressing of the silicon-on-insulator structure; and determining the effective vacancy diffusion area based on a change in the resistance measurements.