Patent ID: 7430643

Claim:
A single chip multithreaded processor comprising: a plurality of processor cores, wherein each core supports processing of a plurality of threads by generating address translation requests for data and instructions related to processing of said plurality of threads and wherein each of the threads is associated with at least one of a plurality of contexts; and a memory management unit operable to control access to data and instructions for said plurality of threads based on at least one of the contexts associated with at least one of the plurality of threads, said memory management unit being operable to compare, for each thread seeking to access a translation table entry, a) each context associated with the thread with b) a context associated with the translation table entry and in the event of a match allow access to the translation table entry to complete an address translation request on behalf of the thread; wherein the processor is operable to perform writes and wherein a write associated with a first one of the plurality of contexts that is associated with a first one of the plurality of threads updates both the first context and a second one of the plurality of contexts that is associated with the first thread, and a write associated with the second context updates only the second context.