Patent ID: 8653644

Claim:
A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface; at least one packaging layer formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface, wherein an opening extends through the packaging layer to at least a portion of a first surface of a first bond pad of said plurality of first bond pads; a monolithic plated conductor formed over said surface of said at least one packaging layer and extending continuously through said opening and formed on said portion of the first surface of said first bond pad; a second conductor formed over a surface of said packaged device which is disposed at a distance from said first surface of said die greater than a distance from said first surface to said second surface of said die and being electrically connected to a second bond pad of said plurality of second bond pads by a third conductor extending through an opening in said die to at least a portion of a first surface of said second bond pad remote from said at least one packaging layer, wherein said first surface of said second bond pad faces said second surface of the die, wherein said second bond pad has a second surface opposite said first surface of the second bond pad, and said second surface of the second bond pad faces said at least one packaging layer; and a first compliant layer, formed over said packaging layer and underlying said monolithic plated conductor, wherein first conductors are formed over said first compliant layer and are underlying said monolithic plated conductor.