Patent ID: 7271049

Claim:
A method of forming a CMOS structure including a self-aligned low-k dielectric material atop at least a gate conductor comprising the steps of: forming a conformal low-k liner on exposed surfaces of a structure comprising at least one gate region including a gate conductor located atop a surface of a semiconductor substrate, said low-k liner having a dielectric constant of about 5 or less; forming a planarized polymeric material on said structure including said conformal low-k liner; recessing said planarized polymeric material to expose a portion of the structure including the low-k liner atop the gate conductor; treating the exposed portion to change etching properties thereof; removing the recessed planarized polymeric material selective to the treated portion; removing the low-k liner that is not protected with said treated portion; and removing said treated portion to provide a structure including a sleeve around the gate conductor which is comprised of the remaining low-k liner.