Patent ID: 8426300

Claim:
A method of forming a semiconductor structure comprising: forming a gate electrode and a planarization dielectric layer on a semiconductor substrate, wherein a top metallic surface of said gate electrode is coplanar with a top surface of said planarization dielectric layer; recessing a top surface of said gate electrode relative to said top surface of said planarization dielectric layer; forming an etch stop layer contiguously on said recessed top surface of said gate electrode and on said top surface of said planarization dielectric layer, wherein said etch stop layer includes a first portion located on said planarization dielectric layer and a second portion located on said gate electrode and having a vertically offset bottom surface relative to an interface between said planarization dielectric layer and said first portion; forming a contact-level dielectric layer over said etch stop layer; forming a via hole extending at least through said contact-level dielectric layer, said first portion of said etch stop layer, and a portion of said planarization dielectric layer, wherein said via hole is vertically spaced from said gate electrode by said second portion of said etch stop layer; wherein said gate electrode is a replacement gate electrode formed by: forming a disposable gate structure on said semiconductor substrate; and replacing said disposable gate structure with a gate dielectric and at least one conductive material, wherein said gate electrode is a remaining portion of said at least one conductive material after removing said at least one conductive material from above a top surface of said planarization dielectric layer.