Patent ID: 8885411

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including a source line, a plurality of bit lines, and a plurality of NAND cell units, the plurality of NAND cell units being each configured from a source side select gate, a plurality of memory cells, a drain side dummy cell, and a drain side select gate that are connected in series between the source line and the bit line, and the source side select gate, the plurality of memory cells, the drain side dummy cell, and the drain side select gate being each a transistor having a control gate and a charge storage layer; and a write/erase circuit configured to execute a select gate write operation, the select gate write operation executing a programming operation for setting a threshold voltage of the drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, and, when it is judged by the verify operation on the drain side select gate that the threshold voltage of said drain side select gate has not reached the certain value, repeatedly executing a programming operation for setting a threshold voltage of the drain side dummy cell connected to said drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, until the threshold voltage of said drain side dummy cell has reached the certain value.