Patent ID: 7907110

Claim:
A discrete display panel controller comprising: a first set of registers configured to hold data to be displayed; first logic circuitry connected to said first set of registers, said first logic circuitry configured to receive said data from said first set of registers, generate signal waveforms to be received by a discrete display panel according to said data, and provide said signal waveforms to said discrete display panel; second logic circuitry connected to said first logic circuitry, said second logic circuitry configured to generate timing signals for timing said first logic circuitry; and a resistor ladder connected to said second logic circuitry, said resistor ladder configured to generate intermediate voltages to drive said discrete display panel, and configured to receive said timing signals from said second logic circuitry, wherein said controller is configured to automatically and periodically disable said resistor ladder according to one of said timing signals, while preventing said signal waveforms from arriving at said discrete display panel by gating and clearing said signal waveforms after being generated by the first logic circuitry.