Patent ID: 8355282

Claim:
A non-volatile memory cell comprising: a floating gate; a coupling device located in a first conductivity region; a first select transistor serially connected with a first floating gate transistor, both of which are formed in a second conductivity region of a second conductivity type; a second select transistor serially connected with a second floating gate transistor, both of which are located in a third conductivity region of a first conductivity type; a control line electrically connected to the coupling device; a word line electrically connected to a gate electrode shared by the first select transistor and the second select transistor; a first bit line electrically connected to a drain region of the first floating gate transistor; a first source line electrically connected to a source region of the first select transistor; a second bit line electrically connected to a drain region of the second floating gate transistor; and a second source line electrically connected to a source region of the second select transistor; wherein the second conductivity region is a first well, and the third conductivity region is a second well and wherein the floating gate is shared by the first floating gate transistor, the second floating gate transistor, and the coupling device.