Patent ID: 8812810

Claim:
A memory control apparatus comprising: a plurality of setting output units each configured to output setting information for setting operation of each of a plurality of memory cells included in a memory array; and a plurality of selection units each configured to: select a memory area, from among a plurality of memory areas corresponding to program memory and data memory, to which each of the plurality of memory cells included in the memory array is assigned in accordance with the setting information, and stop the operation of a memory cell, from among the plurality of memory cells included in the memory array, that is not assigned to any of the plurality of memory areas; wherein the plurality of selections units include a plurality of first selection circuits, respectively, each of the plurality of first selection circuits configured to select supply or stop of the supply of a clock signal to each of the plurality of memory cells included in the memory array in accordance with the setting information; and for a memory cell, whose operation is to be stopped, of the plurality of memory cells included in the memory array, a first selection circuit of the plurality of first selection circuits stops the supply of the clock signal to the memory cell.