Patent ID: 8404578

Claim:
A method of forming a non-volatile memory device, comprising: forming a first interlayer insulating layer on a memory array having a plurality of strings of non-volatile memory cells therein at side-by-side locations in a semiconductor substrate, said plurality of strings of non-volatile memory cells comprising a row of ground select transistors, a plurality of rows of non-volatile memory cells and a row of string select transistors; patterning the first interlayer insulating layer to define at least one source region contact opening therein that exposes at least one source region of a ground select transistor, and also define a plurality of drain region contact openings therein that expose respective drain regions of corresponding string select transistors; depositing an electrically conductive layer that extends onto the first interlayer insulating layer and into the at least one source region contact opening and the plurality of drain region contact openings; patterning the deposited electrically conductive layer into a source plate that covers the plurality of strings of non-volatile memory cells and into a plurality of bit line contact plugs; forming a second interlayer insulating layer on the source plate and the plurality of bit line contact plugs; patterning the second interlayer insulating layer to define a plurality of bit line contact openings therein that expose corresponding ones of the plurality of bit line contact plugs; and forming a plurality of bit lines that extend on the second interlayer insulating layer and into the plurality of bit line contact openings.