Patent ID: 7494889

Claim:
A method of forming a semiconductor die interposer including at least one passive element, the method comprising: forming at least one conductive trace from an electrically conductive layer on a substrate including at least one dielectric layer and at least one electrically conductive layer at least partially superimposed with respect to one another, the at least one conductive trace having at least a portion thereof positioned in an overlapping relationship with an intended position of at least a portion of at least one recess; forming the at least one recess at least partially within the at least one dielectric layer and the at least one electrically conductive layer by removing a portion of the at least one dielectric layer and a portion of the at least one conductive trace at the intended position of the at least a portion of the at least one recess to define at least a portion of a side wall of the at least one recess with a portion of the at least one conductive trace; selecting at least one dimension of the at least one recess for at least one passive element formed therein to exhibit an intended magnitude of at least one electrical property; depositing conductive material at least partially within the at least one recess; and forming the at least one passive element from the conductive material wherein the at least one conductive trace is configured for electrically communicating with at least a portion of the at least one passive element.