Patent ID: 8446780

Claim:
A nonvolatile semiconductor memory device, comprising: a cell unit including a plurality of memory transistors; a first line connected to one end of the cell unit; and a control circuit configured to control a voltage applied to the cell unit, the cell unit comprising: a memory string configured having a plurality of electrically rewritable memory transistors connected in series; a dummy memory string having one end connected to one end of the memory string, and including a plurality of dummy memory transistors connected in series; and a first transistor provided between the other end of the dummy memory string and the first line, the memory string comprising: a semiconductor layer including a columnar portion extending in a perpendicular direction to a substrate, and configured to function as a body of the memory transistors; a charge storage layer surrounding a side surface of the columnar portion, and configured to store a charge; and a first conductive layer surrounding a side surface of the columnar portion via the charge storage layer, and configured to function as a gate of the memory transistors, and the dummy memory string comprising: the semiconductor layer configured to function as a body of the dummy memory transistors; the charge storage layer; and a second conductive layer surrounding a side surface of the columnar portion via the charge storage layer, and configured to function as a gate of the dummy memory transistors, the control circuit being configured to, during an erase operation, set a voltage of the first line connected to a selected cell unit to a voltage larger than a voltage of a gate of the first transistor included in the selected cell unit by an amount of a first voltage, the control circuit being configured to, during the erase operation, set a voltage difference between a voltage of the first line connected to an unselected cell unit and a voltage of a gate of the first transistor included in the unselected cell unit to a second voltage, the second voltage differing from the first voltage, and the control circuit being configured to, during the erase operation, apply in the selected cell unit and the unselected cell unit a third voltage to a gate of at least one of the dummy memory transistors in the dummy memory string, and apply a fourth voltage to a gate of another one of the dummy memory transistors in the dummy memory string, the fourth voltage being lower than the third voltage.