Patent ID: 8581629

Claim:
An apparatus comprising: an analog timing controller having an analog timing circuit and a glitch filter; and a digital state machine having: an input circuit that is configured to receive a plurality of analog input signals; an analog event circuit that is coupled to the analog timing circuit, the glitch filter, and the input circuit, wherein the analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit, and wherein the glitch filter is configured to receive the composite event signal; and a clock generator that is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal, and wherein the aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine, wherein the glitch filter further comprises: an input buffer that is coupled to the analog event circuit; a filter that is coupled to the input buffer; a Schmitt trigger that is coupled to the filter; and an output buffer that is coupled to the Schmitt trigger.