Patent ID: 7920400

Claim:
A semiconductor integrated circuit device comprising: a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including: first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction, the second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines; and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction, the third direction forming an acute angle with the first direction; a plurality of bitline contacts connecting the first junction area and the bitlines, wherein the unit active regions located on both sides of the respective first and second gate lines are separated into first regions and second regions, a plurality of contact pads being formed on the second regions, wherein a first epitaxial layer and a second epitaxial layer are formed in the first regions and second regions, respectively, and wherein: a first interlayer dielectric layer pattern is formed on the first and second gate lines such that the second regions are exposed through the first interlayer dielectric layer pattern and contact pads are formed in the first interlayer dielectric layer pattern, a second interlayer dielectric layer is formed on the first interlayer dielectric layer pattern and on the contact pads, a plurality of first contact holes are formed by patterning the second interlayer dielectric layer and the first interlayer dielectric layer pattern, the first contact holes exposing the first epitaxial layers, the bitline contacts being formed in the first contact holes, a third interlayer dielectric layer is formed on the bitlines and on the second interlayer dielectric layer pattern, and a plurality of second contact holes is formed by patterning the third interlayer dielectric layer and the second interlayer dielectric layer pattern, the second contact holes exposing the contact pads, the second contact holes being formed by enlarging the second contact holes by performing an isotropic etching operation, storage node contacts being formed in the second contact holes.