Patent ID: 7793080

Claim:
A processing device comprising: a first execution unit; a second execution unit; and a front-end unit coupled to the first execution unit via a first dispatch bus and coupled to the second execution unit via a second dispatch bus separate from the first dispatch bus, the first dispatch bus configured to concurrently transmit a first dispatch group of up to N microcode operations from the front-end unit to the first execution unit for a dispatch cycle and the second dispatch bus configured to concurrently transmit a second dispatch group of up to N microcode operations from the front-end unit to the second execution unit for the dispatch cycle; wherein the front-end unit comprises: a dispatch module coupled to the first dispatch bus and the second dispatch bus, the dispatch module comprising: a dispatch buffer configured to buffer microcode operations for dispatch; and a dispatch controller configured to select microcode operations from the dispatch buffer for inclusion in the first and second dispatch groups; and a decode module comprising a plurality of parallel decode paths, each decode path comprising: a microcode decoder comprising a microcode table, the microcode decoder configured to decode an instruction into a set of one or more microcode operations based on the microcode table; a first format decoder configured to format each microcode operation output by the microcode decoder according to a dispatch format and provide the resulting formatted microcode operation for storage in the dispatch buffer; a fastpath hardware decoder configured to decode an instruction into a set of one or more microcode operations; and a second format decoder configured to format each microcode operation output by the fastpath hardware decoder according to the dispatch format and provide the resulting formatted microcode operation for storage in the dispatch buffer.