Patent ID: 7476584

Claim:
A method of fabricating a semiconductor device comprising: forming a plurality of gate electrodes on a semiconductor substrate partitioned into a cell region, a core region, and a peripheral circuit region, wherein forming a gate electrode includes forming a gate spacer along both sidewalls of a stack of a gate insulating layer, a gate conductive layer, and a gate hard mask; forming a source/drain within the semiconductor substrate; forming a first interlayer insulating layer to fill a space between the gate electrodes; forming a first landing pad contacting the source/drain of the cell region within the first interlayer insulating layer, and a second landing pad contacting the source/drain of an NMOS transistor of the core region; forming a second interlayer insulating layer and a hard mask pattern on the first interlayer insulating layer, the gate electrode, the first landing pad and the second landing pad; forming a first contact hole that exposes the first landing pad, and a second contact hole that exposes the second landing pad by etching the second interlayer insulating layer using the hard mask pattern as an etch mask, forming a first trench by etching the second interlayer insulating layer and a portion of the first interlayer insulating layer on the upper surface of the source/drain of a PMOS transistor of the core region, and forming a second trench by etching the second interlayer insulating layer and a portion of the first interlayer insulating layer on the upper portion of the source/drain of a PMOS transistor of the peripheral circuit region; forming spacers respectively along inner walls of the first contact hole, the second contact hole, the first trench, and the second trench; further etching the first interlayer insulating layer using the hard mask pattern and the spacer as etch masks, and deepening the first trench until reaching the semiconductor substrate to form a third contact hole that exposes the source/drain of the PMOS transistor of the core region, and deepening the second trench until reaching the semiconductor substrate to form a fourth contact hole that exposes the source/drain of the PMOS transistor of the peripheral circuit region; and etching the second interlayer insulating layer and the first interlayer insulating layer to form a fifth contact hole that exposes the source/drain of an NMOS transistor of the peripheral circuit and to form a sixth contact hole that exposes the gate conductive layer of the peripheral circuit region.