Patent ID: 8861586

Claim:
A system comprising: a processor; and memory coupled to the processor, the system configured to execute a decoder that decodes frames of encoded data, the decoder comprising: a decoder first stage that is configured to decode encoded frames to produce decoded frames, the encoded frames comprising an encoded first frame and the decoded frames comprising a decoded first frame produced using the encoded first frame; and a decoder second stage coupled downstream of the first stage, the second stage comprising a first deblocker and a second deblocker that are configured to deblock decoded frames in parallel and concurrently, wherein the decoded first frame is classifiable as a type of frame and wherein one of the first and second deblockers is selected to deblock the decoded first frame depending on the type of frame; wherein the decoded first frame is identified as an in-order frame if macroblocks in the encoded first frame arrive at the decoder in a specified order and otherwise the decoded first frame is identified as an out-of-order frame, and wherein the decoded first frame is identified as a reference frame if another frame relies on information in the decoded first frame for decoding and otherwise the decoded first frame is identified as a non-reference frame; and wherein the second deblocker is selected to deblock the decoded first frame if the decoded first frame is classified as an out-of-order non-reference frame and otherwise the first deblocker is selected to deblock the decoded first frame.