Patent ID: 7554412

Claim:
A phase-locked loop circuit which generates a clock or analog frequency signal locked to an input signal, comprising: a voltage-controlled oscillator that oscillates and outputs said clock or frequency signal and changes the frequency of said clock or frequency signal corresponding to a control voltage; a first comparator that in a normal operation mode compares at least one of the frequency and phase of said input signal with the clock or frequency signal fed back from an output of said voltage-controlled oscillator, and outputs a first error signal corresponding to the comparison result; an active loop filter having an inherent offset voltage receiving said first error signal from said first comparator, and which integrates said first error signal and outputs said control voltage to said voltage-controlled oscillator; a second comparator that compares at least one of the frequency and phase of a reference signal with the clock or frequency signal fed back from an output of said voltage-controlled oscillator, and outputs a signal corresponding to the comparison result; and an offset voltage corrector, that feeds a second error signal corresponding to the output signal of said second comparator to said active loop filter when the input of said active loop filter is cut off from the output of said first comparator, generates an offset correction value based on said second error signal when said fed-back clock or frequency signal is locked to said reference signal, and feeds an offset correction signal having the offset correction value to said active loop filter when the input of said active loop filter is connected to the output of said first comparator; wherein both said first error signal and said offset correction signal are input to the active loop filter in the normal operation mode.