Patent ID: 7940545

Claim:
A Read Only Memory (ROM), comprising: a ROM array including a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of bit cells, wherein gate terminals of each of the plurality of bit cells are connected to a plurality of word lines; an address decoder for enabling at least one of the bit lines and at least one of the word lines for a read operation; a control circuit for generating at least one control signal; a precharge tracker for generating a programmable precharge signal by tracking a precharge of a reference precharge bit line; a precharge circuit, connected to the enabled bit line, for precharging the enabled bit line based on at least one of the programmable precharge signal and the at least one control signal; a reference word line that is enabled with a reference array based on at least one of the programmable precharge signal and the at least one control signal, the reference word line tracking the at least one enabled word line; a reference bit line that is enabled using a reference column based on at least one of the reference word line and the at least one control signal, the reference bit line tracking the enabled bit line; and a reference sense generator for generating a programmable sense signal based on at least one of the reference bit line, the programmable precharge signal and the at least one control signal, wherein the programmable sense signal is provided to a control logic circuit associated with the bit line for reading at least one bit cell corresponding to the enabled bit line and the at least one enabled word line.