Patent ID: 6930324

Claim:
An integrated circuit comprising: a vertical FET access transistor array formed into the depth of a substrate in active webs which run parallel in the lateral direction of the integrated circuit and are implemented as vertical trenches; an array of storage capacitors, wherein each storage capacitor is associated with a vertical FET access transistor and is formed in a deep trench on a face of a section of an active web which forms the vertical FET access transistor; a series of wordlines arranged along the active webs; a series of bitlines intersecting the wordlines; and an array process diagnosis test structure, wherein the process diagnosis test structure is connected to the wordlines and wherein the connection to the wordlines forms a wordline comb structure, wherein the comb structure comprises: a first wordline comb connected by a series of contacts to a first series of non-adjacent wordlines along a first edge of the transistor array, wherein the spacing between each successive wordline in the first series of non-adjacent wordlines is defined by a parameter n; and a second wordline comb connected by a series of contacts to a second series of non-adjacent wordlines along a second edge of the transistor array opposite to the first edge, wherein the spacing between each successive wordline in the second series of non-adjacent wordlines is defined by the parameter n, and wherein the first series and second series of wordlines are offset such that no wordlines are common to both the first and second series.