Patent ID: 7314807

Claim:
A method of manufacturing a metal-insulator-metal capacitor, comprising: forming a lower metal electrode layer pattern in a metal-insulator-metal capacitor region above an insulating layer above a semiconductor substrate; forming a lower metal line layer pattern in a metal line region above the insulating layer; forming an intermetal insulating layer above the lower metal electrode layer pattern and the lower metal line layer pattern; forming a first trench by removing a first portion of the intermetal insulating layer in the metal-insulator-metal capacitor region, a second portion of the intermetal insulating layer remaining above the lower metal electrode layer pattern in the metal-insulator-metal capacitor region; forming an insulating spacer layer on a sidewall of the first trench and removing the remaining intermetal insulating layer under the first trench to form a structure including a second trench exposing a portion of the lower metal electrode layer pattern; forming a dielectric layer above an upper surface of the structure; using a first mask layer pattern to form a via hole exposing the lower metal line layer pattern in the metal line region; forming an upper metal electrode layer on the dielectric layer within the second trench; and forming a via contact connected to the lower metal line layer pattern within the via hole.