Patent ID: 8039756

Claim:
A multilayered wiring board comprising: first and second electrodes disposed on a first surface and a second surface, respectively, of said multilayered wiring board; a plurality of insulation layers; a plurality of wiring layers disposed between said insulation layers; and vias that are disposed in an insulation layer and electrically connect the overlying wiring layer and the underlying wiring layer that sandwich the insulation layer, wherein said second electrode is embedded in the insulation layer exposed on said second surface, the wiring layer covered by the insulation layer exposed on said second surface does not have an adhesive layer that faces the insulation layer exposed on said second surface, and said first and second electrodes are exposed externally on said multilayered wiring board, wherein said second electrode and the wiring layer covered by the insulation layer exposed on said second surface are in direct contact, and wherein a top surface of said second electrode exposed externally on said multilayered wiring board is not covered with any insulation layers, and said second electrode and a conductive bump are in direct contact.