Patent ID: 7863949

Claim:
A signal synchronization circuit comprising: multiple signal paths, wherein each of said signal paths comprises: an input node; a first element that receives an input signal applied to said input node; a second element that receives an output signal from said first element; a multiplexor that receives said output signal from said first element and that further receives an output signal from said second element; a third element that receives an output signal from said multiplexor; and an output node that receives an output signal from said third element; multiple XOR gates, wherein each XOR gate corresponds to one of said signals paths, receives said output signal from said second element of said one of said signal paths and further receives said output signal from said third element of said one of said signal path; and an OR gate that receives output signals from all of said XOR gates, wherein an output signal from said OR gate controls said output signal from said multiplexor in each of said signal paths.