Patent ID: 8169203

Claim:
A low-drop out (LDO) regulator circuit with zero frequency compensation, comprising: a pass transistor having a gate coupled to an output of an operational transconductance amplifier (OTA), the LDO regulator exhibiting a dominant pole at the output of the OTA and a non-dominant pole at an output of the LDO; a dynamic zero-compensation circuit, coupled in parallel to the pass transistor; and a compensation control circuit coupled and configured to adjust a variable resistor of the dynamic zero-compensation circuit, the compensation control circuit including: a current mirror configured to mirror current flow of the pass transistor; a current scaling circuit coupled to receive current passing through the pass transistor and pass a fraction of current flow of the current mirror; and a bias voltage circuit coupled to the current scaling circuit and configured to generate a bias voltage proportional to current passed by the current scaling circuit which is proportional to the output current.