Patent ID: 8860108

Claim:
A semiconductor device comprising: a first wiring; a second wiring; a third wiring; a fourth wiring; and a fifth wiring, wherein a plurality of memory elements are supported by a substrate including a semiconductor material, and connected in series between the first wiring and the second wiring, each memory element comprising: a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode; a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode, wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other, wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other, wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other, wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other, wherein the fourth wiring and the second gate electrode are electrically connected to each other, and wherein the fifth wiring and the third gate electrode are electrically connected to each other.