Patent ID: 7816969

Claim:
A level shifter circuit, comprising: an input node for receiving a digital input signal characterized by a logical high state having a first high voltage level; an output node for driving a digital output signal characterized by a logical high state having a second high voltage level, wherein the output signal logical state mirrors the input signal logical state; a short circuit current reduction transistor, having a first source/drain terminal connected to a first internal node and a second source/drain terminal connected to a second internal node and a gate terminal connected to the output node, for charging the first internal node of level shifter circuit following a first transition of the input signal logical state; and a performance enhancement transistor having source/drain terminals connected between the first internal node and ground and having a gate terminal connected to the input node for discharging the first internal node of the level shifter circuit following a second transition of the input signal logical state, wherein the first transition and the second transition differ.