Patent ID: 8754798

Claim:
A SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, each capacitor comprising a top plate and a bottom plate, wherein all top plates of said capacitors are electrically connected to a common node; a switch controlled by a sampling signal for connecting the common node to a ground node when the sampling signal is asserted; a plurality of switching networks, each switching network associated with a respective capacitor of the plurality of capacitors and controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting the bottom plate of the respective capacitor to an analog input signal if the sampling signal is asserted, or else to the ground node if the respective grounding bit is asserted, or else to a first reference voltage if the respective data bit is one, or else to a second reference voltage; a comparator for detecting a polarity of a voltage at the common node and outputting a decision signal when a comparing signal is asserted; a logic gate for outputting a ready signal according to the decision signal; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the decision signal, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data.