Patent ID: 7368353

Claim:
A method for manufacturing a power semiconductor device comprising: forming a mask layer over a first surface of a semiconductor body; patterning said mask layer with a plurality of openings each opening extending to and exposing said first surface of said semiconductor body at the bottom thereof; etching a termination trench in said semiconductor body prior to patterning said mask layer, said termination trench including a side wall and bottom, extending to a depth below a first depth and defining an active area that includes said trenches: defining trenches in said semiconductor body by etching said semiconductor body through said openings, each trench including sidewalls and a bottom; forming an insulation layer on said sidewalls of said trenches; forming a gate electrode in each of said trenches, each gate electrode including a free end extending above said first surface into a respective opening in said mask layer to a height substantially co-planar with a top surface of said mask layer; siliciding each of said gate electrodes at its free end; removing said mask layer, whereby each gate electrode becomes proud and extends above said first surface of said semiconductor body; implanting continuous source implant regions of first conductivity in said semiconductor body between said trenches; forming spaced insulation interlayers over said free ends of said gate electrodes; etching through said source implant regions; implanting regions of second conductivity into said semiconductor body through spaces between said spaced interlayers to form implant regions of said second conductivity; and applying a diffusion drive to form source regions and high conductivity contact regions of said second conductivity.