Patent ID: 7456668

Claim:
A pulse width modulation circuit, comprising: a voltage control circuit for changing a voltage of a first integration circuit based on a current based on an input signal during a first period, being equal to half a cycle of a predetermined clock signal, changing the voltage of the first integration circuit based on a constant bias current in a direction opposite to an increase/decrease direction in the first period while changing a voltage of a second integration circuit being different from the first integration circuit based on a current based on the input signal during a second period shifted from the first period by half a cycle and following the first period, and changing the voltage of the second integration circuit based on the bias current during a third period shifted from the second period by half a cycle and following the second period in a direction opposite to an increase/decrease direction in the second period; a first detection circuit for detecting an amount of time from a start of the second period until the voltage of the first integration circuit reaches a predetermined reference voltage; a second detection circuit for detecting an amount of time from a start of the third period until the voltage of the second integration circuit reaches a predetermined reference voltage; a first voltage keeping circuit for keeping the voltage of the first integration circuit at the reference voltage from when the voltage of the first integration circuit reaches the reference voltage until the start of the third period; a second voltage keeping circuit for keeping the voltage of the second integration circuit at the reference voltage from when the voltage of the second integration circuit reaches the reference voltage until a start of a fourth period shifted from the third period by half a cycle and following the third period; and a pulse signal generation circuit for generating a pulse signal whose pulse width is equal to the amount of time, which is output alternately from the first detection circuit and the second detection circuit every half cycle of the predetermined clock signal.