Patent ID: 7962669

Claim:
A memory controller comprising: a data buffer configured to receive a transfer data transmitted from a transmission circuit by a first burst transmission of first burst times in which said transmission circuit transmits data having a first bit length, and to store said transfer data, an amount of said transfer data stored in said data buffer in said first burst transmission being a product of said first bit length and said first burst times; and a control circuit coupled to said data buffer to transmit said transfer data from said data buffer to a reception circuit capable of receiving said transfer data in a second burst transmission of second burst times in which said reception circuit receives data having a second bit length, an amount of said transfer data received by said reception circuit in said second burst transmission being a product of said second bit length and said second burst times, wherein said control circuit issues a command indicating an initiation of an access of said transmission circuit to said reception circuit before said amount of said transfer data stored in said data buffer in said first burst transmission becomes equal to said product of said first bit length and said first burst times, when said amount of said transfer data stored in said data buffer in said first burst transmission becomes equal to or more than said product of said second bit length and said second burst times, wherein said data buffer has already started to store said transfer data from said transmission circuit before said control circuit issues said command to said reception circuit.