Patent ID: 7257031

Claim:
A circuit arrangement for switching high-voltage signals with low-voltage signals, particularly for driving a semiconductor memory arrangement, comprising: a low-voltage logic device configured to generate at least one low-voltage signal with a first predetermined logic level (0) and with a second predetermined logic level (1); and a latch configured to receive and latch the at least one low-voltage signal and to generate an output signal having a voltage (vdd) dependent on the logic level of the received low-voltage signal, the latch comprising: a level shifter configured to increase the value of the voltage of the latched low-voltage signal to a voltage of a high-voltage signal, such that the voltage of the output signal substantially to the voltage of the high-voltage signal; and one or more high-voltage transistors; wherein the low-voltage logic device is operably connected only to one or more gates of one or more of the one or more high-voltage transistors when driving the latch with the low-voltage signals and the low-voltage logic device is connected to at least a drain or to a source of one or more of the one or more high-voltage transistors only when the latter is or are simultaneously operated in a common-gate configuration.