Patent ID: 7791377

Claim:
A time to digital converter having a hierarchical structure, comprising: a first time to digital converter including delay stages having a delay time of T 1 , compensating for a phase difference between two signals to be less than T 1 and generating a plurality of output signals, sequentially delaying a first signal of the two signals for a specific delay time, and outputting the output signals to a time to digital converter in a next stage, a plurality of flip-flops for comparing delay signals of the first signal delayed by the delay stages with a second signal of the two signals, and generating different outputs before and after a phase difference between the delay signals of the first signal and the second signal becomes smaller than a resolution of the time to digital converter, a selection signal generator for generating a selection signal for selecting a signal most similar to the second signal among the delay signals of the first signal from the outputs of the flip-flops, and a Multiplexer (MUX) for receiving the delay signals of the first signal and the selection signal, and outputting the signal most similar to the second signal among the delay signals of the first signal; and a second time to digital converter including delay stages having a delay time of T 2 , and detecting a phase difference of the output by the first time to digital converter, wherein T 1 is greater than T 2 .