Patent ID: 7941631

Claim:
An apparatus comprising: a first processor core to execute instructions; a first translation lookaside buffer (TLB) coupled to the first processor core, the first TLB to store a plurality of entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store a plurality of bits for a memory page associated with the VA-to-PA translation, the plurality of bits to indicate at least one attribute of information in the memory page, wherein the plurality of bits of the second portion for a plurality of memory pages are to be stored in a table stored in user level space of a memory and a first bit of the plurality of bits is of a first state to indicate that a corresponding memory page is an initialized heap region, and wherein a user-level exception is to be generated if a write access occurs to an uninitialized heap region and if so, a handler is to update the first bit to the first state.