Patent ID: 6930298

Claim:
A focal plane array processor comprising: a focal plane array including a plurality of pixels arranged in a matrix configuration for forming an image; computational circuitry for receiving a plurality of processed signals for computing a desired property of said formed image; and processing circuitry for receiving a plurality of signals from said focal plane array and transmitting said plurality of processed signals to said computational circuitry, herein the processing circuitry includes a first plurality of area-of-interest (AOI) circuits wherein each of said first plurality of area-of-interest (AOI) circuits receives at a first input a summed ith row current from an ith row of said focal plane array as one of said plurality of signals and receives at a second input a corresponding ith control signal from among a plurality of control signals stored in a row n-bit shift register, wherein said control signal is a binary signal set to one of a signal-passing and non-signal-passing value for respectively including and not including said summed ith row current in computing said desired property, wherein each of the first plurality of area-of-interest (AOI) circuits comprises at least a first transistor and a second transistor, the gates of said first and second transistors being coupled at a common node, said common node connected to said second input to receive said control signal from said row n-bit shift register.