Patent ID: 7470593

Claim:
A method for manufacturing a cell transistor of a semiconductor memory device having a threshold voltage adjust region on a semiconductor substrate, comprising the steps of: forming device isolation films and a well on a semiconductor substrate; forming a threshold voltage adjust region by ion-implanting a first conductive impurity dopant into the well of the semiconductor substrate; performing a first thermal annealing on the semiconductor substrate where the threshold voltage adjust region is formed, for first diffusing the first conductive impurity dopant; forming a gate insulating film and gate electrodes on top of the semiconductor substrate between the device isolation films; forming a halo ion implantation region by ion-implanting a first conductive impurity dopant into only a drain region of the semiconductor substrate exposed by the gate electrodes; performing a second thermal annealing on the semiconductor substrate for second additionally diffusing the first diffused first conductive impurity dopant in the threshold voltage adjust region to increase a threshold voltage of the cell transistor and diffusing the first conductive impurity dopant ion implanted in the drain region; and then ion-implanting a second conductive impurity dopant into the drain region of the semiconductor substrate to form a drain of the cell transistor and into a source region being positioned opposite to the drain region to form a source of the cell transistor.