Patent ID: 8461686

Claim:
A chip comprising: a silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a third internal circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first local signal distribution network over said silicon substrate and in said dielectric layer, wherein said first local signal distribution network is connected to said first internal circuit and to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said first local signal distribution network; a second local signal distribution network over said silicon substrate and in said dielectric layer, wherein said second local signal distribution network is connected to said third internal circuit; a passivation layer over said dielectric layer; a first via in said passivation layer, wherein said first via is connected to said first local signal distribution network; a second via in said passivation layer, wherein said second via is connected to said second local signal distribution network; and a global signal distribution network over said passivation layer, wherein said global signal distribution network is connected to said first and second vias, wherein said first internal circuit is connected to said third internal circuit through, in sequence, said first local signal distribution network, said first via, said global signal distribution network, said second via and said second local signal distribution network, and wherein said second internal circuit is connected to said third internal circuit through, in sequence, said first local signal distribution network, said first via, said global signal distribution network, said second via and said second local signal distribution network.