Patent ID: 7445987

Claim:
A method of forming a memory array comprising: etching a substrate to provide a first trench having an initial depth and a second trench having an intermediate depth to produce an offset in a vertical dimension between said first trench region and said second trench region; forming sacrificial sidewall spacers to said initial depth of said first trench and to said intermediate depth of said second trench; etching said first trench to a first collar depth and said second trench to a second collar depth, wherein said offset between said first trench and said second trench is maintained; forming collars within said first trench and said second trench, said collars positioned underlying said sacrificial sidewall spacers within said first trench and said second trench; forming capacitors in said first trench and said second trench, each of said capacitors extending above a bottom surface of said collars; recessing said collars below a top surface of said capacitors, wherein recessed collars in said first trench and said second trench are of equal length; forming buried straps atop said recessed collars in said first trench and said second trench, wherein said buried straps of said first trench are separated from said buried straps of said second trench by said offset in said vertical dimension; and forming transistors atop said capacitors in said first trench and said second trench.