Patent ID: 8320203

Claim:
An apparatus, comprising: a bit cell having a first storage node to store a value asserted on a write bit line, and a second storage node to store a value asserted via a second write bit line that is complementary to the first write bit line value; and a circuit, including: a pull up switch circuit to selectively apply an operating voltage to one of a first voltage node coupled to the first storage node and a second voltage node coupled to the second storage node, under control of the complementary write bit line values; and a voltage equalizer connected between the first and second voltage nodes, wherein, during a write to the bit cell, one of the first and second storage nodes into which a write bit line value of logic 1 is to be written is pulled up strongly to the operating voltage through the switch circuit, and the other of the first and second storage nodes into which a write bit line value of logic 0 is to be written is pulled up weakly through both the switch circuit and the voltage equalizer connected in series.