Patent ID: 8080983

Claim:
A low drop out (LDO) bypass voltage regulator in an integrated circuit device, comprising: a power pass element, the power pass element having a power input, a power output and a control input, wherein the power input is coupled to a voltage source and the power output is coupled to a load; a buffer having an input and an output, wherein the output of the buffer is coupled to the control input of the power pass element; an error amplifier having a positive input, a negative input and an output, wherein the output of the error amplifier is coupled to the input of the buffer, the negative input is coupled to a voltage reference and the positive input is coupled to a sampled voltage of the power output of the power pass element; and a voltage monitor and control circuit having a first control output, a second control output and a voltage sensing input, wherein the voltage sensing input is coupled to the voltage source, the first control output is coupled to the buffer and the second control output is coupled to the power pass element, wherein when the voltage source is above a first voltage value the buffer is enabled, and the power pass element, buffer and error amplifier regulate a load voltage, and when the voltage source is less than a second voltage value the buffer is disabled and the power pass element is placed into a pass-through state so that the load voltage follows the source voltage and is not regulated.