Patent ID: 8572329

Claim:
An apparatus for processing data, said apparatus comprising: a source of memory access requests to respective memory addresses within a memory address space; a programmable memory protection unit configured to store programmable data defining a plurality of programmable memory regions within said memory address space having associated programmable memory attributes, said programmable memory protection unit being operable to receive a memory access request to a target memory address from said source and, if said target address lies within one or more of said plurality of programmable memory regions, then to return an associated programmable memory attribute for said target address; and a default memory protection unit hard-wired to define a plurality of default memory regions within said memory address space having associated default memory attributes, said default memory protection unit being operable to receive said memory request to said target memory address from said source and, if said target address does not lie within one or more of said plurality of programmable memory regions, then to return an associated default memory attribute for said target address, wherein said default memory protection unit is controllable to be enabled or disabled and if said default memory protection unit is disabled, then if said target address does not lie within one or more of said plurality of programmable memory regions, then a memory protection violation signal is generated.