Patent ID: 7454590

Claim:
A processor comprising: a plurality of processor cores, wherein each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB); and an interconnect to which the plurality of processor cores are coupled; wherein a first processor core of the plurality of processor cores is configured to broadcast a demap command on the interconnect responsive to executing a demap operation in the first processor core, and wherein the demap command identifies one or more translations to be invalidated in each TLB in each of the plurality of processor cores, and wherein remaining processor cores of the plurality of processor cores are configured to invalidate the one or more translations in the respective TLBs and to transmit a response to the first processor core, and wherein the first processor core is configured to delay continued processing of the demap operation, including delaying invalidation of the one or more translations in the TLB in the first processor core, until the responses are received from each of the remaining processor cores.