Patent ID: 7369436

Claim:
A NAND architecture Flash memory device comprising: a NAND architecture memory array formed on a substrate having a plurality of pillars and associated intervening trenches; a plurality of floating gate memory cells, wherein the floating gate memory cells are formed vertically on the sidewalls of the plurality of pillars and trenches; wherein the plurality of floating gate memory cells are coupled into a plurality of NAND architecture memory strings by source/drain regions formed at the top of the plurality of pillars and at the bottom of the associated trenches; a control circuit; a row decoder; a plurality of word lines coupled to the row decoder, wherein each word line is coupled to one or more control gates of one or more floating gate memory cells, where each of the one or more floating gate memory cells is from a differing NAND architecture memory string of the plurality of NAND architecture memory strings; at least one bitline, wherein the at least one bitline is coupled to a drain of a first floating gate memory cell of each NAND architecture memory string of the plurality of NAND architecture memory strings through a first select gate; and at least one source line, wherein the at least one source line is coupled to a source of a last memory cell of each NAND architecture memory string of the plurality of NAND architecture memory strings through a second select gate.