Patent ID: 7994829

Claim:
An apparatus for generating an output clock, the apparatus comprising: a controlled oscillator, to generate the output clock according to a tuning signal; a frequency divider, to divide the output clock to generate a first clock and a third clock, wherein a frequency of the first clock is higher than a frequency of the third clock; a comparison circuit, to compare the first clock and a second clock to produce a comparison signal; a phase detector (PD), to detect a difference between the third clock and a fourth clock to generate a detection signal; a finite state machine (FSM), to generate a state signal according to at least one of the detection signal and the comparison signal; a filter, to produce a first control signal according to the detection signal and the state signal; and a first circuit, to produce a second control signal according to the comparison signal and the state signal; a control circuit, to produce the tuning signal according to the first control signal and the second control signal.