Patent ID: 7223663

Claim:
A method of manufacturing a MOS transistor, comprising steps of: forming a gate insulating layer pattern and a gate on a semiconductor substrate of a first conductivity type where an active region is defined by an isolation layer; forming an ion implanting buffer layer on the entire surface of the substrate; forming first source/drain extension regions of a second conductivity type first within the substrate at both sides of the gate by performing a first ion implanting process; forming second source/drain extension regions of the second conductivity type within the substrate under the first source/drain extension region by performing a second ion implanting process; forming halo impurity regions of the first conductivity type within the substrate under the edge of the gate by performing a third ion implanting process; forming a spacer on side walls of the gate; and forming source/drain regions of the second conductivity type within the substrate at both sides of the spacer by performing a fourth ion implanting process.