Patent ID: 7164293

Claim:
A circuit having first and second dynamic signals responsive to a clock signal, comprising: a first plurality of transistors of a first conductivity type in series coupled between a latch node and a power supply terminal, comprising: a first transistor for receiving the first dynamic signal; a second transistor for receiving the second dynamic signal; a third transistor for receiving a complementary signal that is complementary to the clock signal; a second plurality of transistors of a second conductivity type in series coupled between the latch node and a second power supply terminal, comprising; a fourth transistor for receiving the first dynamic signal; and a fifth transistor for receiving a first select signal; a third plurality of transistors of the second conductivity type in series coupled between the latch node and the second power supply terminal, comprising: a sixth transistor for receiving the second dynamic signal; and a seventh transistor for receiving a second select signal; and a latch having an input coupled to the latch node and an output coupled to the latch node.