Patent ID: 8411480

Claim:
A semiconductor device comprising: a write word line; a read word line; a bit line; a source line; a signal line; a memory cell comprising: a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and a third transistor comprising a third gate electrode, a third source electrode, a third drain electrode, and a third channel formation region; a first driver circuit comprising a delay circuit electrically connected to the signal line; and a second driver circuit, wherein the first channel formation region comprises a semiconductor material different from a semiconductor material of the second channel formation region, wherein the first gate electrode and the second drain electrode are electrically connected to each other, wherein the first drain electrode and the third source electrode are electrically connected to each other, wherein the source line is electrically connected to the first source electrode, wherein the first driver circuit is electrically connected to the third drain electrode through the bit line and electrically connected to the second source electrode through the delay circuit and the signal line, and wherein the second driver circuit is electrically connected to the third gate electrode through the read word line and electrically connected to the second gate electrode through the write word line.