Patent ID: 8233328

Claim:
A nonvolatile semiconductor memory comprising: a memory cell array in which a plurality of memory cell transistors capable of storing data according to a threshold voltage; a row decoder having a plurality of transfer MOS transistors connected at first ends to a plurality of word lines which are respectively connected to control gate electrodes of the plurality of memory cell transistors; a word line driver which selects supplied voltages and supplies the selected voltages to second ends of the plurality of transfer MOS transistors; a voltage generation circuit which supplies voltages to the word line driver; and a control circuit which controls operation of the row decoder, the word line driver and the voltage generation circuit, wherein the word line driver comprises: a first pump circuit which boosts a first voltage supplied to a first terminal and outputs a first boosted voltage obtained by the boosting; a first nMOS transistor connected at a first end thereof to the first terminal and connected at a second end thereof to a second end of a first transfer transistor included in the plurality of transfer transistors; a first switch circuit which is connected between an output of the first pump circuit and a gate of the first nMOS transistor, which in an on-state brings about conduction between the output of the first pump circuit and the gate of the first nMOS transistor, and which in an off-state brings about cutoff between the output of the first pump circuit and the gate of the first nMOS transistor; a second nMOS transistor connected at a first end thereof to a second terminal supplied with a second voltage and connected at a second end thereof to the second end of the first transfer transistor; and a second switch circuit which is connected between an output of the first pump circuit and a gate of the second nMOS transistor, which in an on-state brings about conduction between the output of the first pump circuit and the gate of the second nMOS transistor, and which in an off-state brings about cutoff between the output of the first pump circuit and the gate of the second nMOS transistor.