Patent ID: 7558145

Claim:
Apparatus, comprising: a supply node to receive a supply voltage of V DD ; a memory cell coupled to the supply node and including a storage node; decoder circuitry coupled to the memory cell to initiate an access cycle to transfer data; a first word line coupled to the memory cell to enable a transfer of data between the storage node and a bit line during the access cycle; at least one further word line coupled to the memory cell to enable a transfer of data between the storage node and a further bit line during the access cycle; and a control circuit responsive to the decoder circuitry to divide the access cycle into at least two time interval portions and to apply a first voltage, higher than the supply voltage, to the first word line during a first time interval portion of the access cycle and to apply a second voltage, lower than the first voltage, to the first word line during a second time interval portion of the access cycle and to apply the second voltage to the at least one further word line during the first time interval portion of the access cycle and to apply the first voltage to the at least one further word line during the second time interval portion of the access cycle.