Patent ID: 8599619

Claim:
A memory system comprising: a memory part comprising, a memory cell array including a plurality of memory cells, a plurality of word lines connected to control gates of the memory cells, a plurality of bit lines connected to the memory cells, including bit line pairs each composed of an even bit line and an odd bit line adjacent to each other, and sense amplifiers provided to the bit line pairs, respectively, and configured to detect data in selected memory cells connected to a selected word line among the word lines based on a current flowing through the selected memory cells; and a controller configured to control the memory part, when reading data is performed from first memory cells to which writing data is performed first in memory cell pairs each composed of two adjacent memory cells respectively connected to one of the even bit lines and one of the odd bit lines, so as to change a read level voltage applied to the selected word line depending on a data write state of second memory cells in the memory cell pairs to which writing data is performed later.