Patent ID: 8372713

Claim:
A method of producing a semiconductor device including a MOS transistor, comprising the steps of: forming a planar semiconductor layer on a dielectric film on a substrate and a plurality of pillar semiconductor layers on the planar semiconductor layer; isolating the planar semiconductor layer as an element; forming a drain or source region in the planar semiconductor layer; thereafter forming a first dielectric film on a surface of the resulting product; forming a conductive film on the first dielectric film to allow the pillar-shaped semiconductor layers to be buried therein; etching back the first dielectric film and the conductive film to allow each of the first dielectric film and the conductive film to have a height of a gate length; selectively removing by etching the remaining first dielectric film and the remaining conductive film including a portion of each of them corresponding to a portion in which the after-mentioned first silicide layer is formed, to form a gate electrode formed around each of the pillar-shaped semiconductor layers and a gate line integrated with the gate electrode; forming a source or drain region in an upper portion of each of the pillar-shaped semiconductor layers to have a same conductivity type as that of a portion of the drain or source region formed in the planar semiconductor layer beneath the pillar-shaped semiconductor layer; and forming a first silicide layer for connecting at least a part of a surface of the drain or source region formed in the planar semiconductor layer of each of first MOS transistors and at least a part of a surface of the drain or source region formed in the planar semiconductor layer of each of second MOS transistors, wherein each of the first and second MOS transistors is one of a plurality of MOS transistors corresponding to respective ones of the plurality of pillar-shaped semiconductor layers.