Patent ID: 8114687

Claim:
A method for manufacturing a semiconductor device, comprising: preparing two package substrates, each including a board body having a first surface and a second surface and also having a wiring formed in the interior thereof, a first land pad disposed in said first surface and a second land pad disposed in said second surface; electrically coupling a semiconductor wafer to an measuring apparatus, said semiconductor wafer having a large scale integrated circuit (LSI) formed therein, which is an object of a testing, and said measuring apparatus applying electrical signal to said LSI formed in said semiconductor wafer to measure electrical characteristics of said LSI formed in said semiconductor wafer; inspecting said semiconductor wafer by using a probe card having one of said prepared two package substrates; dicing said semiconductor wafer into semiconductor elements containing said LSI; and packaging said semiconductor element over the other of said prepared two package substrates, wherein said probe card includes: an adapter board including: said one of the package substrates; an insulating layer formed over said first surface of said one of the package substrates; a through hole formed in the position corresponding to said first land pad of said insulating layer; a conductive member formed in said through hole; a third land pad covering said through hole and having a bump side without being covered with the insulating layer; and an external coupling terminal formed in said second land pad; and a probe, being electrically coupled to said third land pad included in said adapter board and in contact with a land formed in said semiconductor wafer; wherein said inspecting the semiconductor wafer includes: electrically coupling said third land pad to said land by causing said probe into contact with the land provided in said semiconductor wafer; and applying electrical signal from said measuring apparatus to said semiconductor wafer to measure electrical characteristics of said semiconductor wafer, wherein said packaging the semiconductor element includes: installing said semiconductor element in said first surface of said other package substrate and providing an electric coupling of said semiconductor element with the first land pad of said other package substrate; and forming an external coupling terminal over said second land pad of said other package substrate.