Patent ID: 8453077

Claim:
A circuit designing method to design a design target circuit by a plurality of client computers configured to design a plurality of blocks forming the design target circuit in parallel, and a server configured to exchange information in real-time with each of the plurality of client computers, said circuit designing method comprising: first notifying, by each of the plurality of client computers to the server, information related to blocks corresponding to a request from the server, in response to the request; analyzing each of the blocks by an analyzing tool within the server, based on the information acquired from each of the plurality of client computers, and obtaining an analysis result; and second notifying, by the server to each of the plurality of client computers, the analysis result obtained by the analyzing, wherein, when the analysis result includes an error in one of the blocks, a modification ease computing tool within the server computes a design modification ease of the one of the blocks for suppressing the error thereof, and includes the design modification ease in the analysis result notified to each of the plurality of client computers by the second notifying, and wherein the design modification ease is at least one information selected from a group of information related to a modification ease for route modification, information related to a modification ease for signal timing correction, information related to a modification ease for noise analysis correction, and information related to a modification ease for power consumption correction.