Patent ID: 8923074

Claim:
A semiconductor memory device comprising: a memory cell array including a memory cell storing data in a non-volatile manner; a bit-line arranged in the memory cell array extending in a first direction, the bit-line supplying or reading a signal to/from the memory cell; a sense amplifier circuit connected to the bit-line, the sense amplifier circuit sensing and amplifying a signal read from the memory cell; a first data latch connected to the sense amplifier via a first bus; a second data latch connected to a second bus; and an input/output buffer inputting/outputting data from/to the outside, a plurality of circuit groups being repeatedly provided in the first direction, each circuit group including one sense amplifier circuit and one first data latch, the second data latch being provided between the circuit groups and the input/output buffer, and a length of the first data bus is shorter than a length of the second data bus.