Patent ID: 7424599

Claim:
An instruction stored in a computer readable storage medium for execution on a multithreading microprocessor having a plurality of thread contexts, wherein the instruction is in an instruction stream issuing from a first of the plurality of thread contexts, the instruction comprising: a first operand, for specifying a second of the plurality of thread contexts, wherein said second of the plurality of thread contexts is distinct from the first of the plurality of thread contexts; a second operand, for specifying one of a plurality of registers in a source thread context; a third operand, for specifying one of a plurality of registers in a destination thread context; and an opcode, for instructing the microprocessor to move a value from said register of said source thread context specified by said second operand to said register of said destination thread context specified by said third operand, wherein one of said source and destination thread contexts is said second of the plurality of thread contexts, wherein the other of said source and destination thread contexts is the first of the plurality of thread contexts; wherein said plurality of registers of each of the plurality of thread contexts comprises a program counter register and a general purpose register set.