Patent ID: 8659972

Claim:
An apparatus comprising: a rail having a supply voltage; a memory cell coupled to the rail; a voltage boost generator to generate a boosted supply voltage provided to the memory cell; a control circuit to provide a trigger signal and a reference-latch signal in response to a clock signal, wherein the reference-latch signal is delayed relative to the trigger signal; a delay circuit coupled to the control circuit to delay the trigger signal; an array of memory cells having a word-line input port coupled to the delay circuit to receive the delayed trigger signal, the array of memory cells to provide a set of read bit-line signals in response to the delayed trigger signal; a latch comprising a reference-latch input port to receive the reference-latch signal, a set of latch input ports to receive the set of read bit-line signals, and an output port to signal to the voltage boost generator when the boosted supply voltage is to be greater than the supply voltage.