Patent ID: 6962852

Claim:
A method for fabricating an integrated circuit which comprises a nonvolatile memory cell comprising a first conductive gate, a second conductive gate, and a conductive floating gate which are insulated from each other, the method comprising: (a) forming the first conductive gate over a semiconductor substrate, and forming a dielectric over a sidewall of the first conductive gate to insulate the first conductive gate from the floating gate; (b) forming an FG layer over the first conductive gate, wherein the floating gate comprises a portion of the FG layer; (c) removing the FG layer from over at least a portion of the first conductive gate; (d) forming a second conductive gate layer over the FG layer to provide at least a portion of the second conductive gate, the second conductive gate layer having a portion P 1 protruding above the first conductive gate; (e) forming a first layer L 1 over the second conductive gate layer such that the protruding portion P 1 is exposed and not completely covered by the first layer L 1 ; (f) partially removing the second conductive gate layer at the location of the portion P 1 selectively to the first layer L 1 to remove the second conductive gate layer from over at least a portion of the first conductive gate; (g) forming a second layer L 2 on the second conductive gate layer adjacent to the first conductive gate; and (h) removing at least parts of the first layer L 1 , the second conductive gate layer and the FG layer selectively to the second layer L 2 .