Patent ID: 7015539

Claim:
A nonvolatile semiconductor memory cell comprising: a semiconductor substrate; a stacked-gate structure that includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on the semiconductor substrate, the inter-electrode insulation film having a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer; and gate side-wall insulation films formed on both side surfaces of the stacked-gate structure, wherein a thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side, and the width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side, wherein a width (Q) of the floating gate electrode in the channel length direction is 50 nm or less on a surface of the tunnel insulation film, and a distance (S) between an end portion of one of the gate side-wall insulation films, which end portion is located on a side opposed to the floating gate electrode, and an end portion of the other gate side-wall insulation film, which end portion is located on a side opposed to the floating gate electrode, is 1.3 or more times as great as the width (Q) of the floating gate electrode in the channel length direction, and wherein a portion of the floating gate contacts the inter-electrode insulation film, and a length (P) of the portion of the floating gate satisfies: Q<P<S.