Patent ID: 8420452

Claim:
A fabrication method of a leadframe-based semiconductor package, comprising the steps of: preparing a leadframe and a chip, the lead frame having a plurality of leads, and the chip having an active surface defined with a first region and a second region surrounded by the first region, wherein a plurality of first conductive bumps are attached to the first region of the active surface of the chip and a plurality of second conductive bumps are attached to the second region of the active surface of the chip; bonding the first conductive bumps to top surfaces of the leads so as to electrically connect the chip to the leadframe; forming an encapsulant to encapsulate the chip, the first and second conductive bumps and the leadframe, wherein bottom surfaces of the leads and bottom ends of the second conductive bumps are exposed from the encapsulant and are flush with a lower surface of the encapsulant; and plating a solder layer on the bottom surfaces of the leads.