Patent ID: 7556899

Claim:
A method for manufacturing a semiconductor device, comprising: sequentially delineating a plurality of underlying patterns of underlying layers below a target layer on a reference semiconductor substrate; inspecting an overlay between the target layer and each of the underlying layers; providing a corrected control set value by: obtaining a processing data string describing a name of an exposure process for the target layer and an original control set value of overlays by an exposure tool between a target pattern in the target layer and the underlying patterns in the underlying layers; obtaining a plurality of inspection data strings describing a plurality of names of a plurality of inspection processes and a plurality of inspection values determined by the inspection processes, the inspection processes inspecting respective overlays between the target and the underlying patterns; creating a correction data table by combining the processing data string and each of the inspection data strings using a combining condition table, the combining condition table describing a relationship between the exposure process and each of the inspection processes; and calculating the corrected control set value of the exposure tool based on the inspection values of the correction data table; sequentially delineating the underlying patterns in respective underlying layers on the target semiconductor substrate; and transferring a pattern of the target layer onto the target semiconductor substrate by the exposure tool, using the corrected control set value.