Patent ID: 7577772

Claim:
A host bus adapter coupled to a network and a host computing system, comprising: a plurality of direct memory access (“DMA”) channels, each DMA channel identified by a unique identifier; an arbitration module that receives requests from the plurality of DMA channels for accessing a bus; wherein the arbitration module arbitrates between the requests and grants access to one of the plurality of DMA channels; and a direct memory access (“DMA”) mode detection module that receives the unique identifier of a first DMA channel that is granted access by the arbitration module at any given time; wherein the DMA mode detection module compares the unique identifier of the first DMA channel with a unique identifier from a previous request that was granted immediately before the first DMA channel grant; and if the unique identifiers match, then the DMA mode detection module increments a DMA counter value that maintains a count value for the DMA channel that has been consecutively granted access within a certain duration; wherein the DMA mode detection module compares the incremented DMA counter value with a pre-programmed threshold value; and if the incremented DMA counter value is at least equal to the pre-programmed threshold value and no other request from another DMA channel from among the plurality of DMA channels is pending, then the DMA mode detection module enables a single channel mode to transfer data for a certain duration; and during the single channel mode, standard transaction rules are ignored to determine DMA request lengths to transfer the data; and wherein the single channel mode is disabled when the DMA mode detection module detects a pending DMA request from another DMA channel besides the first DMA channel that was not granted access to the bus within the certain duration.