Patent ID: 7191383

Claim:
An architecture for generating an error control code capable of being appended to a data packet having a given byte width that is to be transmitted over a parallel data path for communicating up to 2 n bytes of data in parallel, the architecture comprising: a plurality of code-generation blocks, each comprising a logarithmically selected data path width and cascaded for providing error control code processing for a selectable parallel data width up to 2 n bytes of data, with a first one of said plurality of code-generation blocks generating code for 2 n bytes, and a second one of said plurality of code-generation blocks generating code for 2 n−1 bytes, wherein said code from said first code-generating block is selectively coupled to said second code generating block, and one or more of said first, second and remaining code-generation blocks of said plurality of code-generation blocks are selectively enabled for generating said error control code for a given data packet, depending on said given byte width of said given data packet.