Patent ID: 8271748

Claim:
An apparatus comprising: circuitry to at least one of: generate, at least in part, at least one request to access at least one portion of data and indicating, at least in part, at least one subset of the at least one portion of the data that is of relatively higher importance than one or more other subsets of the at least one portion of the data that are of relatively lower importance, the at least one request being to request, at least in part, that the at least one subset be accessed prior to the one or more other subsets being accessed, the at least one request being comprised, at least in part, in at least one packet in accordance with a protocol that permits variable packet size, both the at least one portion of the data that is to be accessed and the at least one subset of the at least one portion of the data that is of the relatively higher importance being indicated by one or more values furnished by one or more application layer processes, the one or more application layer processes to furnish the one or more values in one or more command descriptor block (CDB) fields of the at least one request in terms of predetermined fixed size data units in a storage device, the one or more CDB fields including one or more offset fields, one or more size fields, and one or more respective boundary information fields, the one or more offset fields comprising one or more respective address offsets relative to one or more logical block addresses (LBA) to one or more starting addresses of the at least one subset of the at least one portion that is of relatively higher importance, the one or more size fields indicating one or more respective sizes of the at least one subset of the at least one portion that is of relatively higher importance, and the one or more respective boundary offsets indicating one or more partial offsets relative to the one or more LBA, the one or more LBA also being indicated in the one or more CDB fields, the one or more application layer processes to be executed, at least in part, by both a controller comprised in the circuitry and by a host processor, the circuitry being comprised in a circuit card that is to be coupled to a circuit board in a host, the circuit board comprising the host processor, the one or more application layer processes to reside in both the circuit card and the circuit board, the one or more application layer processes being to determine, at least in part, the at least one portion of the data that is of the relatively higher importance and the one or more other subsets of the at least one portion of the data that are of the relatively lower importance, based at least in part upon whether stalling of the one or more application layer processes may occur pending receipt of the at least one portion of the data that is of the relatively higher importance and the one or more other subsets of the at least one portion of the data that are of the relatively lower importance; and receive, at least in part, the at least one request.