Patent ID: 8270743

Claim:
A discrete cosine transformation circuit comprising: a butterfly circuit with a pipeline comprising a fetch stage, a memory stage, and an arithmetic stage, wherein: the fetch stage receives and decodes butterfly instructions; the memory stage comprises memory repository for storing image data coefficients and intermediate calculated data output by the arithmetic stage, and outputs a first set of data stored in the memory stage in a first clock cycle of the butterfly circuit according to at least one decoded butterfly instruction; the arithmetic stage comprises a plurality of registers, a first arithmetic logic unit and a second arithmetic logic unit, the plurality of registers receive the first set of data from the memory repository as input data of the arithmetic stage, and each of the first arithmetic logic unit and the second arithmetic logic unit receives from the plurality of registers a set of input data, performs a first calculation on the set of input data, and outputs a calculation result of the first calculation in a second clock cycle of the butterfly circuit subsequent to the first clock cycle according to at least one decoded butterfly instruction; and the butterfly circuit further comprises a path for directing the calculation result of the arithmetic stage to the memory stage in the same clock cycle when the first calculation is performed, such that at least one of the plurality of registers is capable of selectively receiving the calculation result from the path or a subsequent set of data from the memory repository in a third clock cycle subsequent to the second clock cycle.