Patent ID: 7391840

Claim:
A phase locked loop (PLL) circuit comprising: a loop input; a phase detector section for detecting a phase difference between an input signal and a reference signal, said phase detector section having a detector input connected to said loop input, a reference input and a detector output for outputting a signal related to said phase difference; a controlled oscillator having an input communicatively connected to said detector output and an oscillator output connected to a loop output; and a feedback circuit connecting said oscillator output to said reference input, wherein said feedback circuit includes a device having a transfer function with at least one zero, and the phase locked loop circuit has a closed loop transfer function without zeros and wherein said feedback circuit further includes at least one frequency divider device and wherein said feedback circuit includes a first frequency divider device and a second frequency divider device, said second frequency divider device having a transfer function with a zero; and wherein an output of the second frequency divider device is connected to an first input of a second combiner device, a second input of the second combiner device is connected to the output of the phase detector, an output of the second combiner device is communicatively connected to the VCO, and wherein: the second divider device comprises a phase detector section and has a transfer function with said zero.