Patent ID: 8017442

Claim:
A method of fabricating a packaging structure, comprising: providing a complete panel of up-down paired packaging substrates, wherein a plurality of wire-bonding pads and an insulating protection layer are formed on each of two opposite outermost layers of the packaging substrate, and a plurality of openings are formed on each of the insulating protection layers, allowing the wire-bonding pads to be exposed from the openings; separating the complete panel of up-down paired packaging substrates and cutting the complete panel of packaging substrates, to form a plurality of packaging substrate blocks each including a first surface having the wire-bonding pads and the insulating protection layer and an opposite second surface having a dielectric layer and a plurality of conductive pads embedded in and exposed from the dielectric layer, each of the packaging substrate blocks having M×N packaging substrate units arranged in an array, wherein M and N are integers greater than one; installing a second carrier board on the conductive pads and the dielectric layer; mounting a semiconductor chip on the insulating protection layer of each of the packaging substrate units, to form a packaging structure block having a plurality of packaging structure units, the semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has a plurality of electrode pads thereon, the inactive surface is stuck on the insulating protection layer, and each of the electrode pads is electrically connected via a bonding wire to each of the wire-bonding pads correspondingly; forming a molding material on the insulating protection layer, the bonding wires and the semiconductor chips; removing the second carrier board; and cutting the packaging structure blocks into the packaging structure units.