Patent ID: 7671475

Claim:
A nonvolatile semiconductor memory comprising: a first cell unit having memory cells connected in series in a first direction, a first select gate transistor connected to one end of the memory cells, and a second select gate transistor connected to the other end of the memory cells; a memory cell array having the first cell unit; a first select gate line extending in a second direction that crosses the first direction and connected to the first select gate transistor; a second select gate line extending in the second direction and connected to the second select gate transistor; and word lines, each one of which is connected to each of the memory cells; wherein, an end of at least one word line at the first select gate transistor side among the word lines is bent to the first select gate line side and contact plugs each are connected between a first bent point and a distal end of the at least one word line at the first select gate transistor side, in a contact area at one end of the memory cell array, and an end of at least one word line at the second select gate transistor side among the word lines is bent to the second select gate line side and contact plugs each are connected between a second bent point and a distal end of the at least one word line at the second select gate transistor side, in the contact area, wherein the memory cell array has a second cell unit that is adjacent to the first cell unit at the first select gate transistor side, and the word line bent to the first select gate transistor side among the word lines extends at a distal end thereof to a center part in the first direction of the second cell unit.