Patent ID: 8446005

Claim:
A semiconductor device, comprising: a first transistor formed on a substrate, having first source/drain regions and second source/drain regions; a second transistor formed on the substrate, having third source/drain regions and fourth source/drain regions; an interlayer insulating film formed on the substrate to cover the first transistor and the second transistor; a first bus in a rectangular shape in plan formed on the interlayer insulating film and connected to the first source/drain regions; a second bus in a rectangular shape in plan formed on the interlayer insulating film with spacing from the first bus and connected to the third source/drain regions; an inter-bus interconnect formed between the first bus and the second bus for connecting the first bus with the second bus; a first contact pad provided on the first bus, to which a first wire is connected; and a second contact pad provided on the second bus, to which a second wire is connected, wherein the inter-bus interconnect is in contact with part of a side of the first bus facing the second bus and part of a side of the second bus facing the first bus, the first contact pad is in contact with part of the first bus, and the second contact pad is in contact with part of the second bus.