Patent ID: 7656008

Claim:
A semiconductor device comprising: a first doped region and a second doped region, both doped with dopants, spaced apart from each other, and defined within a same well of a semiconductor substrate; a gate insulating layer and a gate electrode stacked on a channel region between the first and second doped regions; spacers on opposite sidewalls of the gate electrode; a first surface metal silicide layer that extends across a top surface of the first doped region adjacent to the spacer; a second surface metal silicide layer that extends across a top surface of the second doped region adjacent to the spacer; at least one insulation layer that extends across the semiconductor substrate including the first and second surface metal silicide layers; a first contact plug that extends through the insulation layer and contacts the first surface metal silicide layer; and a second contact plug that extends through the insulation layer, the second surface metal silicide layer, and the second doped region into the well in the semiconductor substrate.