Patent ID: 8782376

Claim:
A processor comprising: a decode unit arranged to receive a sequence of instructions; a first and at least a second data processing channel each coupled to the decode unit, the second data processing channel comprising enable logic configured to selectively enable the second data processing channel; variable offset addressing logic coupled to the decode unit, configured to generate first and second storage addresses having a variable offset therebetween based on a same one or more address operands of a same storage access instruction; and storage access circuitry coupled to the variable offset addressing logic and to the first and second data processing channels, configured to transfer data between the first storage address and a register of the first data processing channel and to transfer data between the second storage address and a corresponding register of the second data processing channel based on a same one or more register specifier operands of the storage access instruction; wherein the decode unit is configured to supply a same opcode and a same one or more operands of a same data processing instruction to both the first and second data processing channels, such that the first data processing channel performs an operation specified by that opcode on data in one or more registers of the first data processing channel, and on condition of being enabled the second data processing channel performs the same operation on data in a corresponding one or more registers of the second data processing channel based on the same one or more operands of the data processing instruction; wherein each of said data processing channels is a vector processing channel, such that the data transferred to or from each of said first and second storage addresses is a respective vector comprising a plurality of data elements, and the operation performed within each of the first and second data processing channels comprises a vector processing operation performed on each of said plurality of data elements in response to said same opcode.