Patent ID: 7237209

Claim:
A method of testing an integrated circuit design to determine whether or not the design satisfies an electrostatic discharge protection specification, said circuit design comprising an active circuit and incorporating electrostatic discharge protection routes between top-level nodes of the design, the method comprising: a) defining an electrostatic discharge protection score for each of said electrostatic discharge protection routes, said score representing said electrostatic discharge protection route will conduct during an electrostatic discharge event; b) for each pair of said top-level nodes, calculating an electrostatic discharge score for every route through the active circuit between the top-level nodes, said score representing said route through said active circuit will conduct during said electrostatic discharge event; and c) identifying route in said active circuit between said pairs of top-level nodes for which the electrostatic discharge score is less than the electrostatic discharge protection score for the corresponding electrostatic discharge protection route, or lies within a predefined amount of that score.