Patent ID: 7934186

Claim:
A non-transitory computer readable storage medium, comprising executable instructions executed by a computer to cause the computer to: construct a shared delay element to replicate signal delay timing of gates forming a path within a segment of an asynchronous circuit, wherein signal rise and fall delay mismatch of the shared delay element is minimized using an inserted gate with opposite rise/fall polarity relative to a previous inserted gate; and Define shared delay element output nodes to include a globally shared node within the segment and a non-shared local node in the segment; wherein the executable instructions to construct include executable instructions to process the following information: (i) critical paths of the gates of the asynchronous circuit, along with statistics characterizing the critical paths, (ii) a list of required arrival times for outputs of the shared delay element, (iii) values for output loads of each of the outputs, (iv) a specification of a transition time for an input of the shared delay element, (v) a maximum transition time constraint for each net of the shared delay element, and (vi) a maximum rise/fall mismatch constraint.