Patent ID: 7589574

Claim:
A system for providing power-on reset and under-voltage lockout signals, the system comprising: a first transistor including a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage; a second transistor including a second gate, a third terminal, and a fourth terminal, the third terminal being configured to receive an input voltage; a first resistor associated with a first resistance, the first resistor including a fifth terminal and a sixth terminal, the fifth terminal being configured to receive the input voltage; a second resistor associated with a second resistance, the second resistor including a seventh terminal and an eighth terminal, the seventh terminal being coupled to the sixth terminal; a Zener diode associated with a Zener voltage, the Zener diode including a ninth terminal and a tenth terminal, the ninth terminal being biased to the predetermined voltage; and a third resistor associated with a third resistance, the third resistor including an eleventh terminal and a twelfth terminal, the twelfth terminal being biased to the predetermined voltage; wherein the first gate is coupled to the fourth terminal and the eleventh terminal to generate a first signal, the first signal capable of being associated with at least one selected from a group consisting of a power-on reset and an under-voltage lockout.