Patent ID: 7364997

Claim:
A method of forming a local interconnect from array circuitry to circuitry peripheral of the array circuitry, comprising: forming semiconductive material having an outermost surface which is higher in an array circuitry area than in a peripheral circuitry area; fabricating vertical transistors within the semiconductive material within the array circuitry area and horizontal transistors within the semiconductive material within the peripheral circuitry area; forming dielectric material over the array and peripheral circuitry areas, the dielectric material comprising conductive contacts extending outwardly from the horizontal transistors in the peripheral circuitry area, the dielectric material having a first outermost surface; removing a portion of the dielectric material and a portion of the conductive contacts to form a second outermost surface of the dielectric material which has greater degree of planarity than did the first outermost surface; and after forming the second outermost surface, forming a local interconnect over and in electrical contact with at least one of the conductive contacts in the peripheral circuitry area to at least one of the vertical transistors in the array circuitry area.