Patent ID: 8049312

Claim:
A semiconductor die package comprising: an assembly comprising: a lead frame; a clip structure; a power MOSFET semiconductor die coupled between the lead frame and the clip structure, the die having upper and lower surfaces, the upper surface of the die being attached to a bottom surface of the clip structure with a first layer of conductive solder and the lower surface of the die being attached to an upper surface of the lead frame with a second layer of conductive solder, the upper surface of the die having a first source terminal and a gate terminal and the bottom surface of the die having a second drain terminal, a heat sink attached to an upper surface of a portion of the clip structure, wherein the clip structure comprises a first source clip electrically coupled to the first source terminal and including a downset portion electrically coupled to a first source lead portion of the lead frame, wherein the second drain terminal is electrically coupled to a second drain lead portion of the lead frame; the clip structure further includes a gate clip electrically connected to the gate terminal including a downset portion electrically coupled to a gate lead portion of the lead frame; and a molding material partially encapsulating the assembly and side surfaces of the heat sink, wherein an upper surface of the heat sink and a lower surface of the lead frame are exposed through the molding material.