Patent ID: 7055022

Claim:
A microprocessor apparatus for performing an indirect near jump operation, comprising: paired operation translation logic, for receiving an indirect near jump macro instruction, and for generating a load-jump micro instruction, wherein said load-jump micro instruction directs pipeline stages in a microprocessor to perform the indirect near jump operation; load logic, coupled to said paired operation translation logic, for receiving said load-jump micro instruction, and for retrieving an offset from memory, wherein said offset indicates a jump destination that is relative to an instruction address corresponding to said indirect near jump macro instruction; and execution logic, coupled to said load logic, for receiving said offset, and for employing said instruction address and said offset to generate a target address specifying said jump destination for the near jump operation; wherein said load-jump micro instruction directs said load logic to retrieve said offset and directs said execution logic to generate said target address; and wherein said load logic comprises a first one of said pipeline stages and said execution logic comprises a second one of said pipeline stages, and wherein said second one of said pipeline stages immediately follows said first one of said pipeline stages.