Patent ID: 8174866

Claim:
A semiconductor storage device comprising: a memory cell array that comprises a plurality of word lines and data lines intersecting with each other and a plurality of memory cells each provided at an intersection of the word line and the data line, the memory cell having a cell transistor formed on a well subjected to application of a predetermined substrate potential; a memory cell array control circuit that controls the memory cell array; a substrate potential control circuit that controls the substrate potential; and an operation state switching circuit that generates/outputs a first control signal for switching the memory cell array control circuit between a normal operation state and a standby state in accordance with the operation state and a second control signal for switching the substrate potential control circuit between the normal operation state and the standby state in accordance with the operation state, wherein the memory cell array control circuit, in response to the first control signal, switches the number of memory cells, for use in storage of data of 1 bit in the normal operation state, to m (m is a natural number) and switches the number of memory cells, for use in storage of data of 1 bit in the standby state, to n (n is a natural number larger than m), and the substrate potential control circuit, in response to the second control signal, controls the substrate potential in the normal operation state to a first substrate potential and controls the substrate potential in the standby state to a second substrate potential (the second substrate potential>the first substrate potential).