Patent ID: 7492013

Claim:
An integrated circuit constrained by a gate pitch, the integrated circuit comprising: a substrate comprising gates pitched at the gate pitch, the gates comprising a first gate and a second gate with a contact between the gates, wherein the gate pitch is a distance between a centerline of the first gate and a centerline of the second gate that facilitates placement of the contact between the first gate and the second gate to contact a diffusion area of the substrate; a first set of metallization layers formed over the substrate comprising lines, the lines being substantially parallel to the gates, wherein the first set comprises an adjusted metallization layer comprising adjusted lines, the adjusted lines being substantially parallel to the gates, pitched at the gate pitch, and substantially vertically aligned with, the gates, and the first set comprises at least one other metallization layer, wherein the at least one other metallization layer comprises at least some of the lines pitched at a wire pitch, the wire pitch being different from the gate pitch, wherein the lines of the adjusted metallization layer connect to cell structures of the substrate with contacts; and a second set of metallization layers formed over the substrate comprising lines, the lines being orthogonal to the gates, wherein lines of the first set of metallization layers interconnect with lines of the second set of metallization layers with vias to form circuitry of the integrated circuit.