Patent ID: 8045407

Claim:
A method of calibrating timing offsets in a memory controller, the memory controller to control the operation of a plurality of memory devices that share a common control signal path, wherein each memory device of the plurality of memory devices includes a dedicated data signal path to receive write data from a corresponding port of the memory controller, the method comprising: for each memory device of the plurality of memory devices, the memory controller: generating a plurality of delayed versions of a timing signal that is used to indicate valid write data on the dedicated data signal path, wherein a rising edge transition of the timing signal indicates a valid first symbol of the write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data; and generating a selected timing signal of the plurality of delayed versions of the timing signal, such that the write data, the selected timing signal and the write command corresponding to the write data arrive, within a predetermined time period, at each memory device of the plurality of memory devices.