Patent ID: 7606955

Claim:
A master/slave system comprising: a single wire bus; a master device including a bus interface coupled to the bus; multiple slave devices each having a bus interface coupled to the bus; and a communication protocol implemented over the single wire bus and employed by the master device and the slave devices; the protocol includes bus transactions comprising bit signals; each bit signal belongs to a bit signal type from among a plurality of bit signal types; and each bit signal type has a time interval that is discernible from time intervals of all other bit signal types; wherein the bit signal types include: an attention request from at least one of the slave devices that causes the master device to query all of the slave devices, the attention request comprising driving the single wire bus to a specified level once for a first period of time, the first period of time longer than periods of time associated with driving the single wire bus to represent logical “1” and logical “0” data bits, a reset signal from at least one of the slave devices when the slave device is powered up, the reset signal comprising driving the single wire bus to a specified level once for a second period of time, the second period of time longer than the first period of time, and a start signal indicating the beginning of a transfer, the start signal comprising driving the single wire bus to a specified level once for a third period of time, the third period of time longer than the periods of time associated with driving the single wire bus to represent logical “1” and logical “0” data bits, the third period of time shorter than the first period of time, wherein the attention request, the reset signal, and the start signal each start with a bus inactive signal, wherein a level of the bus inactive signal is higher than each of the attention request, the reset signal, and the start signal.