Patent ID: 8570086

Claim:
A circuit comprising: a first delay latch circuit that includes a first internal signal generation portion and a first data hold portion, wherein the first internal signal generation portion includes a first NOR gate, the first NOR gate including a first input connected to a first data signal line and a second input connected to a clock signal line, and the first data hold portion includes a second NOR gate and a third NOR gate, the second NOR gate including a first input connected to an output node of the first NOR gate and a second input connected to an output node of the third NOR gate, and the third NOR gate including a first input connected to an inverted clock signal line and a second input connected to an output node of the second NOR gate, wherein the first NOR gate includes a first internal signal output circuit and a first delay transistor, the first delay transistor being configured to delay a signal output from the first inter signal output circuit.