Patent ID: 7692948

Claim:
A semiconductor memory device, comprising: a memory cell array with memory cells each including a ferroelectric capacitor and a selection transistor serially connected; a plate line connected to one end of the ferroelectric capacitor and supplied with a certain plate line voltage; a bit line connected to one end of the selection transistor; and a sense amp circuit operative to sense/amplify the voltage on the bit line, the sense amp circuit including: a first node given a first constant voltage having a positive value larger than a fixed potential before reading; a second node given a second constant voltage having a negative value smaller than the fixed potential before reading; a third node to be connected to the first and second nodes on reading; a first transistor connected between the first node and the bit line and operative to turn on when the potential on the bit line becomes smaller than the fixed potential; a second transistor connected between the second node and the bit line and operative to turn on when the potential on the bit line becomes larger than the fixed potential; a first capacitor connected between the first node and the fixed potential; a second capacitor connected between the second node and the fixed potential; and a differential amplifier circuit operative to amplify the potential on the third node in comparison with a reference potential.