Patent ID: 6914459

Claim:
A clock circuit comprising: an oscillator to receive a reference clock signal and to generate pulses having a frequency which is greater than that of a frequency of the reference clock signal; a latching device coupled to receive a clock control signal that is used to mask a clock output signal, the latching device also coupled to receive the pulses from the oscillator to synchronize the clock control signal with the pulses from the oscillator for output from the latching device; a logic gate counted to receive the synchronized clock control signal output from the latching device and also to receive the pulses from the oscillator and to output pulses from the oscillator as the clock output signal, but to mask the clock output signal if the clock control signal indicates a masked condition, the synchronizing of the clock control signal and the pulses from the oscillator to maintain constant pulsewidth of the pulses of the clock output signal independent of timing of the clock control signal; and a pulse counter circuit coupled to receive and count pulses of the clock output signal and to indicate when a selected number pulses of the clock output signal has occurred to initiate the masked condition of the clock control signal.