Patent ID: 7494859

Claim:
A method of manufacturing a semiconductor device comprising: forming a gate insulation layer on a semiconductor substrate having a first impurity region and a second impurity region; forming a metal layer having a first thickness on the gate insulation layer; forming a preliminary pattern having a second thickness substantially smaller than the first thickness by partially removing a portion of the metal layer over the second impurity region; forming a polysilicon layer on a resultant structure comprising the preliminary pattern; transforming the preliminary pattern into a metal silicide layer through a reaction between the preliminary pattern and the polysilicon layer; and, etching the polysilicon layer, the metal silicide layer, the metal layer, and the gate insulation layer to form a first gate pattern on the first impurity region and a second gate pattern on the second impurity region, wherein the first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having the first thickness, and a first polysilicon layer pattern and, wherein the second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a thickness less than the first thickness, and a second polysilicon layer pattern.