Patent ID: 8350310

Claim:
A semiconductor device manufacturing method comprising: forming, in a semiconductor substrate, grooves for defining active regions, each active region including a transistor region formed with a selection transistor of a memory cell, and a capacitor region formed with a capacitor of the memory cell; filling the grooves in with an element isolation insulating film; removing at least a part of the element isolation insulating film formed on both sides of the capacitor region to expose sidewalls of the active regions; sequentially forming a dielectric film and a first conductive film on the active regions and the sidewalls; patterning the first conductive film so that a gate electrode made of the first conductive film is formed in the transistor region, and that a counter electrode made of the first conductive film is formed in the capacitor region; forming a lower interlayer insulating film for covering the gate electrode and the counter electrode; forming a first metal wiring layer on the lower interlayer insulating film; patterning the first metal wiring layer to form a first bit line; forming a first interlayer insulating film for covering the first bit line; forming a second metal wiring layer on the first interlayer insulating film; and patterning the second metal wiring layer to form a second bit line.