Patent ID: 7444492

Claim:
A processor comprising: an address specifying unit that specifies an address range on a virtual storage area; an instruction code setting unit that sets an instruction code for a process of deciding data corresponding to the specified address range; a calculating unit that calculates the data corresponding to the specified address range, according to the instruction code set for the specified address range; a load instruction obtaining unit that obtains a load instruction for the specified address range; a data output unit that supplies the data calculated by the calculating unit corresponding to the specified address range indicated by the load instruction, as data for the load instruction; a data storing unit that stores the data calculated by the calculating unit in association with the specified address range; and a data managing unit that, when the load instruction is obtained, supplies the data stored into the data storing unit to the data output unit when the data corresponding to the specified address range indicated by the load instruction is stored in the data storing unit, wherein the data managing unit, when the load instruction is obtained, makes the calculating unit calculate the data corresponding to the specified address range when the data corresponding to the specified address range indicated by the load instruction is not stored in the data storing unit.