Patent ID: 8039896

Claim:
A semiconductor memory device comprising: a semiconductor substrate including a plurality of pillars arranged to be spaced apart from one another, each of the pillars including a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other; a gate electrode surrounding each of the pillar portions; a bitline disposed on the body portion to penetrate a region between the pair of pillar portions of each of the pillars arranged to extend in a first direction; a wordline disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode; a first doped region in the upper surface of each of the pillar portions of the pillars; a second doped region in the body portion of the pillars, between the pair of pillar portions, the second doped region being connected electrically to the bitline; and storage node electrodes connected electrically to the first doped region and disposed on each of the pillar portions.