Patent ID: 8924741

Claim:
A processor comprising: a plurality of SIMD registers; a decode stage to decode a first instruction for a SIMD (Single Instruction Multiple Data) secure hashing algorithm round slice, the first instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings; and one or more execution units coupled with the plurality of SIMD registers, responsive to the decoded first instruction, to: perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, wherein for each round iteration of the secure hashing round-slice set, a message-plus-constant for the round iteration is selected from the message-plus-constant operand set, a portion of the source data operand set is processed according to the round iteration, and the selected message-plus-constant is added to the processed portion of the source data operand set; and store a result of the first instruction in a SIMD destination register of the plurality of SIMD registers.