Patent ID: 7271451

Claim:
A memory cell comprising: a p-well area having a first portion and a second portion, the first portion having a first pass-gate transistor and a first pull-down transistor, the second portion having a second pass-gate transistor and a second pull-down transistor; and an n-well area positioned between the first portion and the second portion, the n-well area having a first pull-up transistor and a second pull-up transistor; wherein the memory cell has a long side and a short side, the long side being at least twice as long as the short side, the short side being less than 0.485 μm, and a longitudinal axis of the p-well being parallel to the short side the gate of the first pass-gate transistor is electrically coupled to a word line; the source of the first pass-gate transistor is electrically coupled to a bit line; the drain of the first pass-gate transistor is electrically coupled to the drain of the first pull-down transistor; the source of the first pull-down transistor is electrically coupled to a V ss line; the drain of the first pass-gate transistor, the drain of the first pull-up transistor, the drain of the first pull-down transistor, the gate of the second pull-down transistor, and second pull-up transistor are electrically coupled; the drain of the second pass-gate transistor, the drain of the second pull-up transistor, the drain of the second pull-down transistor, the gate of the first pull-down transistor, and first pull-up transistor are electrically coupled; the source of the first pull-up transistor is electrically coupled to a V cc line; the source of the second pull-up transistor is electrically coupled to the V cc line; the gate of the second pass-gate transistor is electrically coupled to the word line; the source of the second pass-gate transistor is electrically coupled to a bit line bar; the drain of the second pass-gate transistor is electrically coupled to the drain of the second pull-down transistor; the source of the second pull-down transistor is electrically coupled to the V ss line; and a longitudinal axis along the source-to-direction of each transistor is substantially parallel to the shorter side of the memory cell.