Patent ID: 8194485

Claim:
A semiconductor memory device, comprising: at least one sense amplifier including a PMOS sense amplifier and an NMOS sense amplifier configured to be respectively activated in response to a first supply voltage and a second supply voltage, and to sense and amplify a voltage difference between a corresponding bit line pair; a controller configured to set one of a normal read mode and a self-refresh mode in response to an external command, to control activation timing of a PMOS drive activation signal and an NMOS drive activation signal according to the set operating mode, and to output the PMOS drive activation signal and the NMOS drive activation signal; and a sense amplifier driver configured to apply the first and second supply voltages to the PMOS and NMOS sense amplifiers, respectively, in response to the PMOS drive activation signal and the NMOS drive activation signal, wherein, in the normal read mode, the activation timing of the PMOS drive activation signal is before the activation timing of the NMOS drive activation signal, and in the self-refresh mode, the activation timing of the PMOS drive activation signal is after or the same as the activation timing of the NMOS drive activation signal.