Patent ID: 7595676

Claim:
A comparator comprising: a first differential input stage including: a first tail current source conducting a first tail current; a first load circuit; a first input transistor having a control electrode coupled to receive a first input voltage, a first electrode coupled to the first tail current source, and a second electrode coupled to the load circuit; and a second input transistor having a control electrode coupled to receive a second input voltage, a first electrode coupled to the first tail current source, and a second electrode coupled to the first load circuit; a second differential input stage including: a second tail current source conducting a second tail current; a third input transistor having a control electrode coupled to receive a first reference voltage, a first electrode coupled to the second tail current source, and a second electrode coupled to the first load circuit; and a fourth input transistor having a control electrode coupled to receive a second reference voltage, a first electrode coupled to the second tail current source, and a second electrode coupled to the first load circuit; an output stage producing a comparator output voltage and having an input coupled to receive an output produced by the first and second differential input stages; a buffer that is coupled to the output stage; a first switch having an input electrode, a control electrode, a first output electrode, and a second output electrode, wherein the control electrode of the first switch is directly coupled to the buffer, and wherein the first input electrode of the first switch receives a first hysteresis voltage, and wherein the first output electrode of the first switch is coupled to the control electrode of the third input transistor; and a second switch having an input electrode, a control electrode, a first output electrode, and a second output electrode, wherein the control electrode of the second switch is directly coupled to the buffer, and wherein the first input electrode of the second switch receives a second hysteresis voltage, and wherein the first output electrode of the second switch is coupled to the control electrode of the fourth input transistor.