Patent ID: 8753901

Claim:
A method for post processing of a semiconductor wafer comprising: providing the semiconductor wafer comprising a plurality of semiconductor chips each having: a top side defining a plane; a passive first region and an active second region each including a silicon region with an insulation layer deposited over the silicon region, the passive first region and active second region being adjacent to and abutting one another in a direction lateral to the plane of the top side and being non-overlapping with one another in a direction perpendicular to the plane of the top side; an arrangement of contact areas and test areas on the insulation layer having respective top surfaces which are arranged in a common plane that is parallel to the plane of the top side of the semiconductor chip, wherein the top sides of the contact areas are square and have width and height dimensions, and the top sides of the test areas are rectangular with larger length dimensions than the width dimensions of the contact areas; a plurality of bonding balls arranged on the contact areas; the contact areas and the test areas being electrically conductively connected to one another via a conduction web that has a top surface that lies in the common plane, the contact areas being arranged in the passive first region of the semiconductor chip, the passive first region having no active components of an integrated circuit such that there are no active components below the contact areas in the passive first region, and the test areas being arranged in the active second region of the semiconductor chip, the active second region having active components of an integrated circuit, wherein the passive first region surrounds the active second region such that the contact areas are situated between the test areas and an outer edge of the semiconductor chips; through contacts extending through a portion of the insulating layer directly below the conduction web and extending from the conduction web to interconnects that are connected to electrodes of the components of the integrated circuit in the active second region, wherein portions of the insulating layer directly below the contact areas and the test areas are free from the through contacts; carrying out a functional test with a test device having test tips to determine defective semiconductor chips; marking the defective semiconductor chips; and sealing the test areas.