Patent ID: 6847582

Claim:
An input buffer, comprising: a first differential amplifier having a positive input adapted to receive an input signal, a negative input adapted to receive a complementary input signal, and an output, the differential amplifier operable to drive a buffer signal on the output from a first logic state to a second logic state at a first slew rate responsive to the input signal transitioning from a first logic state to a second logic state and the complementary input signal transitioning from the second logic state to the first logic state, and the differential amplifier operable to drive the buffer signal from the second logic state to the first logic state at a second slew rate responsive to the input signal transitioning from the second logic state to the first logic state and the complementary input signal transitioning from the first logic state to the second logic state; a second differential amplifier having a positive input adapted to receive the complementary input signal, a negative input adapted to receive the input signal, and an output, the differential amplifier operable to drive a buffer signal on the output from a first logic state to a second logic state at the first slew rate responsive to the input signal transitioning from a first logic state to a second logic state and the complementary input signal transitioning from the second logic state to the first logic state, and the differential amplifier operable to drive the buffer signal from the second logic state to the first logic state at the second slew rate responsive to the input signal transitioning from the second logic state to the first logic state and the complementary input signal transitioning from the first logic state to the second logic state; and an output circuit coupled to the outputs of the first and second differential amplifiers, the output circuit operable to generate a first edge of an output signal responsive to the buffer signal from the first differential amplifier transitioning from the first logic state to the second logic state and operable to generate a second edge of an output signal responsive to the buffer signal from the second differential amplifier transitioning from the first logic state to the second logic state.