Patent ID: 7373539

Claim:
A method for aligning parallel path data bit streams that may contain skewed data between bit streams, the method comprising for each bit stream: sampling P data presented on a positive edge of a clock; sampling N data presented on a negative edge of the clock; and delaying the sampled P and N data by one of zero, one-half, one, or other multiple of one-half clock cycle, wherein delaying the sampled P and N data by one of zero, one-half, one, or other multiple of one-half clock cycle is selected to remove any skew and aligns the sampled P and N data between bit streams, wherein delaying includes using first and second 2-to-1 multiplexors in conjunction with first and second flip-flops for providing inputs to third and fourth 2-to-1 multiplexors, wherein the third and fourth 2-to-1 multiplexors output the sampled P and N data to four register flip-flops in a sequential order, the sampled P and N data having been delayed by one of zero, one-half, or one clock cycle.