Patent ID: 7555690

Claim:
A device for testing an integrated circuit, said device comprising: a first connector coupled to receive an integrated circuit under test; a second connector coupled to receive compressed test data by way of test equipment at a first clock rate based upon a first clock signal; a clock generator coupled to receive said first clock signal and generate a second clock signal; a memory of said test equipment storing said compressed test data comprising test patterns for testing the functionality of said integrated circuit under test; a dual-port first-in first-out memory coupled to said memory of said test equipment and providing an empty signal to said test equipment to instruct said test equipment to send words of said compressed test data to a first port of said dual-port first-in first-out memory, wherein said empty signal is sent when the dual-port first-in first-out memory data count is less than or equal to a predetermined number; and a decompressor associated with said test equipment and coupled to receive said compressed test data from a second port of said dual-port first-in first-out memory, said decompressor coupling a read enable signal to said dual-port first-in first-out memory to enable reading words of compressed test data from said second port and coupling decompressed test data to said integrated circuit under test at a second clock rate based upon said second clock signal.