Patent ID: 8551830

Claim:
A method of manufacturing a semiconductor integrated circuit having a multi-layer structure, comprising: forming a first semiconductor layer transistor in a first semiconductor layer; depositing a second semiconductor layer on said first semiconductor layer; and forming a second semiconductor layer transistor in said second semiconductor layer, wherein said forming said second semiconductor layer transistor comprises: forming a source electrode and a drain electrode in said second semiconductor layer; forming a second semiconductor layer gate insulating film in said second semiconductor layer by at least one of radical oxidation and radical nitridation; and forming a gate electrode in said second layer, and said forming said first semiconductor layer transistor in said first semiconductor layer comprises forming a first semiconductor layer gate insulating film in said first semiconductor layer by thermal oxidation, wherein a size of said second semiconductor layer gate insulating film is larger than a size of said first semiconductor layer gate insulating film so that (i) an insulation of said second semiconductor layer gate insulating film is almost equalized with an insulation of said first semiconductor layer gate insulating film; and (ii) the electric characteristics of the first semiconductor transistor and the second semiconductor transistor are unified.