Patent ID: 8766376

Claim:
A semiconductor structure comprising: a first active area, a second active area, a third active area, a fourth active area, a fifth active area, and a sixth active area of a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, respectively, in a substrate, longitudinal axes of the active areas being parallel; and a first gate, a second gate, a third gate, a fourth gate, a fifth gate, and a sixth gate of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, respectively, on the substrate, the first gate, the second gate, the third gate, a fourth source/drain region of the fourth active area, a fifth source/drain region of the fifth active area, a sixth source/drain region of the sixth active area being all aligned, the fourth gate the fifth gate, the sixth gate, a first source/drain region of the first active area, a second source/drain region of the second active area, a third source/drain region of the third active area being all aligned.