Patent ID: 7219311

Claim:
A program storage medium that stores a development method for developing integrated circuits, the development method comprising: a core generating including generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, by a unit that selects optional blocks having a connection to group the blocks, wherein the core (logic core) in the HDL format includes an optional number of blocks of ports, the blocks having optional size and port connection information; creating a temporary chip design from chip terminal information by using the logic synthesis tool to generate a terminal in the temporary chip design; a design generating including generating a design identical to that created at the creating, as a cell within the design created; connecting a chip design port with a cell port, wherein a name of the design port is identical to a name of the cell port; inserting an I/O buffer, depending on a device technology, into a net between the connected chip design port and the cell port; and a netlist generating/expanding including generating a netlist by replacing the cell by the core (logic core) created at the core generating, and expanding a hierarchy of the design created at the design generating, being the top hierarchy.