Patent ID: 8415200

Claim:
A method for manufacturing a semiconductor package, comprising: (A) preparing a metal member in which a first metal layer, a barrier layer, and a second metal layer are stacked in sequence; (B) forming a metal post by selectively etching the second metal layer; (C) removing the exposed barrier layer from the metal post and laminating an insulating layer on the first metal layer through which the metal post is penetrated; and (D) patterning the first metal layer contacting one surface of the insulating layer to form a circuit layer: and, (E) after applying a solder resist to both surfaces of the insulating layer, forming a first opening by processing the solder resist so that a pad part of the circuit layer formed on one surface of the insulating layer is exposed and forming a second opening by processing the solder resist so that the metal post formed on the other surface of the insulating layer is exposed.