Patent ID: 8122451

Claim:
A method for dispatching threads to central processing units (CPUs) in a computer system, said method comprising the steps of: (a) determining that a target CPU of said computer system is available to execute a thread, said computer system being a non-uniform memory access (NUMA) computer system having a plurality of CPUs and a memory divisible into a plurality of discrete subsets, wherein each of said plurality of CPUs is associated with a respective one of said plurality of discrete subsets of memory, wherein a memory access by a CPU to its associated memory subset of said plurality of discrete subsets requires a first latency period, and a memory access by a CPU to a memory subset other that said its associated memory subset requires a latency period greater than said first latency period; (b) identifying a set of multiple threads which are eligible to execute on said target CPU, said set of multiple threads waiting on a common ready queue, said common ready queue being a ready queue from which respective threads are dispatched to each of said plurality of CPUs, wherein no CPU or subset of said plurality of CPUs receives preferential dispatching of threads from said common ready queue; (c) identifying at least one target subset of said plurality of discrete subsets of memory for each respective thread of said set of multiple threads, each target subset having a respective latency period for memory access by said target CPU to a location within the target subset, wherein said respective latency periods for memory access are not all identical; and (d) responsive to step (a), selecting a thread from said set of multiple threads for execution on said target CPU, said selecting step being based at least in part on said respective latency period of each target subset.