Patent ID: 8347130

Claim:
A system-on-chip comprising: a power-off domain block including a main CPU; and a power-on domain block including a low-power CPU and a memory; wherein the memory is used as an auxiliary memory of the power-off domain block at a power-on mode and as a memory storing programs and data for the low-power CPU at a power-off model, wherein when the system-on-chip satisfies a power-down condition, programs and data to be used by the low-power CPU are copied to the memory of the power-on domain block, the power-off domain block is powered down, and the low-power CPU is booted up, and wherein the power-on domain block analyzes externally transferred data during a power-down state of the power-off domain block to substitutes an operation of the power-off domain block, based on an analyzed result of the externally transferred data.