Patent ID: 7037821

Claim:
A method for forming a contact of a semiconductor device, comprising the steps of: forming a first interlayer dielectric (ILD) layer on a semiconductor substrate having a cell transistor and a lower poly silicon plug thereon; forming a stacked structure of a barrier layer, a conductive layer and a hard mask nitride film on the first ILD layer, and selectively etching the stacked structure to form a bit line; forming an oxide film spacer at a sidewall of the bit line; forming a second ILD layer on the semiconductor substrate including the bit line; polishing the second ILD layer using CMP slurry having high selectivity for oxide film to expose the hard mask nitride film; forming a third ILD layer on the exposed hard mask nitride film and the second ILD layer; and performing an etching process to form an opening for storage node contact exposing the lower poly silicon plug.