Patent ID: 8144500

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; a plurality of first lines stacked on the semiconductor substrate and parallel with one another; a plurality of second lines formed to intersect the plurality of first lines and parallel with one another; a memory cell array including memory cells provided at intersections of the first lines and the second lines and each including a variable resistance element and a selecting element connected in series to the variable resistance element; a first control circuit provided on a portion of the semiconductor substrate that is in a second region adjoining a first region located immediately under the memory cell array, and connected to ends of the first lines to select and drive the first lines; a second control circuit provided on a portion of the semiconductor substrate that is in the first region, and connected to ends of the second lines to select and drive the second lines; and dummy lines formed in a same wiring layer in which the second lines are formed, such that the dummy lines intersect the first lines in a region above the first control circuit, the first control circuit being configured to apply a first voltage to a selected one of the first lines such that a certain potential difference is applied to a selected memory cell provided at the intersection of the selected first line and a selected one of the second lines, the second control circuit being configured to apply a second voltage having a smaller voltage value than that of the first voltage to the selected second line, and applies, to the dummy lines, a third voltage having such a voltage value by which a potential difference to be applied to the memory cells provided at intersections of the selected first line and the dummy lines becomes lower than an on-voltage of the selecting element.