Patent ID: 7941637

Claim:
A method for operating an information system within an integrated circuit, the method comprising: generating a first packet of information by a first processor core of a multi processor core circuit of the integrated circuit, wherein the first packet of information is directed to a first partition of a memory; propagating the first packet of information from the first processor core to a second processor core, wherein the first processor core and the second processor core are in a first coherency group; propagating the first packet of information from the second processor core to a packet switch; propagating the first packet of information through the packet switch to the first partition of the memory; maintaining coherency among the first partition of the memory, the first processor core, and the second processor core; generating a second packet of information by a third processor core of the multi processor core circuit of the integrated circuit, wherein the second packet of information is directed to a second partition of the memory; propagating the second packet of information from the third processor core to a fourth processor core, wherein the third processor core and the fourth processor core are in a second coherency group; propagating the second packet of information from the fourth processor core to a packet switch; propagating the second packet of information through the packet switch to the second partition of the memory; and maintaining coherency among the second partition of the memory, the third processor core, and the fourth processor core.