Patent ID: 7211490

Claim:
A method of fabricating a thin silicon-on-insulator device comprising: providing a structure having at least a first device region and a second device region, each device region comprising at least one gate region located on an SOI layer and at least two intrinsic silicon surfaces of said SOI layer, wherein said at least one gate region has exposed sidewalls and said at least two intrinsic silicon surfaces are adjacent to said exposed sidewalls; forming a set of thin spacers on said exposed sidewalls of said each gate region; selectively growing epitaxial silicon on said at least two intrinsic silicon surfaces of said SOI layer to form an intrinsic raised source/drain regions on said SOI layer adjacent to said each gate region; forming a set of offset spacers abutting said set of thin spacers; blocking said second device region with a block mask and implanting dopants of a first conductivity type into said raised source/drain regions in said first device region to form a first dopant impurity region; removing the block mask from the second device region; blocking said first device region with another block mask and implanting dopants of a second conductivity type into said raised source/drain region in said second device region to form a second dopant impurity region; removing said another block mask; and activating said first dopant impurity region and said second dopant impurity region.