Patent ID: 8341509

Claim:
An apparatus, comprising: a matrix formatting module to: partition a plurality of bits into a plurality of bit groups, such each of the plurality of bit groups respectively includes a consecutive subset of the plurality of bits; and arrange the plurality of bit groups and at least one fill bit in accordance with a predetermined pattern to generate a plurality of matrix formatted bits that includes a predetermined plurality of bits such that at least one of the plurality of bit groups spans more than one matrix row of the plurality of matrix formatted bits; an encoder module, communicatively coupled to the matrix formatting module, to perform at least one of: encode bits within a plurality of rows of the plurality of matrix formatted bits to generate a first plurality of parity bits; and encode bits within a plurality of columns of the plurality of matrix formatted bits to generate a second plurality of parity bits; and a transmit driver, communicatively coupled to the encoder module, to arrange the plurality of matrix formatted bits and at least one of the first plurality of parity bits and the second plurality of parity bits to generate an output bit sequence.