Patent ID: 7317628

Claim:
A memory device, comprising: a plurality of memory cells arranged in rows and columns; a plurality of sense amplifier circuits each coupled to a different row of memory cells, wherein each sense amplifier circuit is coupled to a match line for receiving a match line voltage and to a low potential line for receiving a low potential voltage from the row of memory cells associated therewith, and wherein the sense amplifier circuit comprises: a charging portion, which is coupled between a power supply voltage and the match line; a discharging portion, which is coupled between the low potential line and a ground supply voltage; and an n-channel sensing device whose gate is coupled to the match line and whose source is coupled to the low potential line for detecting a potential difference between the match line voltage and the low potential voltage; and a reference generator coupled to one or more of the sense amplifier circuits for supplying a reference voltage to the charging portion within each of the one or more sense amplifier circuits.