Patent ID: 7861101

Claim:
A signal processor comprising: a plurality of processor elements, each including a computing unit, an input register disposed at an input portion of the computing unit and an output register disposed at an output portion of the computing unit; a bus, for connecting the plurality of processor elements; a switch unit, for changing a connection for the bus; a control circuit, for controlling the switch unit in accordance with software; and a memory, for storing scheduling information relating to an order to perform signal processes by the processor elements, wherein the signal processor is configured to operate in: a first operating mode, during which the processor elements sequentially perform signal processes; and a second operating mode, during which signal processes performed by the processor elements and a data transfer process from the output registers of the processor elements to the input registers are alternately performed, and connections for the plurality of processor elements are changed during a period in which the processor elements perform the signal processes, and the control circuit performs circuit reconfiguration in a time-sharing manner in accordance with the scheduling information.