Patent ID: 7441166

Claim:
A testing apparatus that concurrently tests a plurality of memories under test, comprising: a pattern generator that generates an address signal and a data signal to be supplied to each of the plurality of memories under test and an expectation signal to be output from each memory under test according to the address signal and the data signal; a plurality of logic comparators, each of which being provided corresponding to one of the memories under test and comparing an output signal output from the corresponding memory under test according to the address signal and the data signal with the expectation signal to generate fail data when the output signal is not identical with the expectation signal; a plurality of fail memories, each of which being provided corresponding to one of the memories under test and storing the fail data generated by the corresponding logic comparator in association with an address shown by the address signal; a plurality of memory controllers, each of which being provided corresponding to one of the memories under test and generating bad address information showing a bad address in the corresponding memory under test based on the fail data stored on the corresponding fail memory; a plurality of universal buffer memories, each of which being provided corresponding to one of the memories under test and storing the bad address information generated from the corresponding memory controller; and a plurality of bad information writing sections, each of which being provided corresponding to one of the memories under test and writing first bad information into the bad address in the corresponding memory under test, the bad address being shown by the bad address information stored on the corresponding universal buffer memory, the writing first bad information being performed concurrently for the plurality of memories under test.