Patent ID: 6947884

Claim:
A scan testable data processing apparatus comprising: at least one scannable circuit having a test reset input for resetting a scan test chain upon receipt of a test reset signal, at least one control signal input and at least one data transfer input/output; a scan interface adaptor having a first port connected to said at least one scannable circuit for supplying a test reset signal to said test reset input, supplying a corresponding control signal to each of said at least one control signal input and transferring data with said at least one scannable circuit via said at least one data transfer input/output, and a second port having a test reset pin adapted for connection to a emulator device for receiving a test reset signal, at least one further pin for connection to said emulation device, said scan interface adaptor connecting said test reset pin of said second port to said test reset input of said at least one scannable circuit and having a first mode wherein each of said at least one control signal input and each of said at least one data transfer input/output of said at least one scannable circuit is connected to a corresponding further pin of said second port, and a second mode wherein said at least one control signal input and said at least one data transfer input/output of said at least one scannable circuit are time division multiplexed on number of said further pins of said second port less than a number of said at least one control signal input and said at least one data transfer input/output of said at least one scannable circuit; and wherein said at least one scannable circuit and said scan interface adaptor are disposed on the same chip.