Patent ID: 7106083

Claim:
A testing system for testing a first DUT (device under test), a second DUT, a third DUT, and a fourth DUT on a wafer, each of the first, second, third, and fourth DUTs comprising a first testing end and a second testing end, the testing system comprising: a testing circuit formed on the wafer comprising: a first conducting line connected to the second testing ends of the first and the fourth DUTs; a second conducting line connected to the second testing ends of the second and third DUTs; a third conducting line connected to the first testing ends of the first and second DUTs; a fourth conducting line connected to the first testing ends of the third and fourth DUTs; a first testing pad coupled to the first conducting line; a second testing pad coupled to the second conducting line; a third testing pad coupled to the third conducting line; and a fourth testing pad coupled to the fourth conducting line; wherein the first, second, third, and fourth testing pads receive at least one testing signal to detect device characteristics of the first, second, third, and fourth DUTs, and when the first and second testing pads transfer a first testing signal, the third and fourth testing pads are floating.