Patent ID: 7501892

Claim:
An amplifier circuit comprising: a first differential amplifier circuit including a first transistor having a gate terminal forming a first input node, a second transistor having a gate terminal forming a second input node and having a dimensional ratio with respect to the first transistor of K:M (where K>M), and a first current source that supplies a first current to a source terminal of the first transistor and a source terminal of the second transistor, wherein K and M represent gate width; a second differential amplifier circuit including a third transistor having a gate terminal forming a third input node, a fourth transistor having a gate terminal forming a fourth input node and having a dimensional ratio with respect to the third transistor of M:K, and a second current source that supplies a second current to a source terminal of the third transistor and a source terminal of the fourth transistor, the second differential amplifier circuit having the same gain as the first differential amplifier circuit; and a third differential amplifier circuit including a fifth transistor having a gate terminal forming a fifth input node, a sixth transistor having a gate terminal forming a sixth input node and having a dimensional ratio with respect to the fifth transistor of 1:1, and a variable current source that supplies a third current to a source terminal of the fifth transistor and a source terminal of the sixth transistor, the third differential amplifier circuit combining the third current and the fifth transistor so that a gain of the third differential amplifier circuit is greater than a gain of the first differential amplifier circuit when the third current is a first magnitude, and the gain of the third differential amplifier circuit is lower than the gain of the first differential amplifier circuit when the third current is a second magnitude that differs from the first magnitude, wherein the first input node, the third input node and the fifth input node are mutually connected to form one node of a differential input node; the second input node, the fourth input node and the sixth input node are mutually connected to form an other node of the differential input node; a drain terminal of the first transistor, a drain terminal of the third transistor and a drain terminal of the fifth transistor are mutually connected to form one node of a differential output node; and a drain terminal of the second transistor, a drain terminal of the fourth transistor and a drain terminal of the sixth transistor are mutually connected to form an other node of the differential output node.