Patent ID: 7620764

Claim:
A reconfigurable logic array for implementing a reconfigurable data-path processor formed on a semiconductor substrate, the reconfigurable logic array comprising: a plurality of reconfigurable computational elements; and a plurality of silo routers, the plurality of silo routers including a silo router that includes a plurality of silo router circuits located between at least a first reconfigurable computational element from the plurality of reconfigurable computation elements and a second reconfigurable computational element from the plurality of reconfigurable computation elements, said plurality of silo routers configured to perform bit permutations on data being transmitted from said first reconfigurable computational element to said second reconfigurable computational element, the plurality of silo routers including the silo router having: a plurality of input terminals and a plurality of output terminals, said plurality of output terminals including a first output terminal and a second output terminal; a plurality of switches; and a plurality of configuration data terminals configured to select a subset of the plurality of switches such that the subset of the plurality of switches defines at least a portion of a data path between at least one of the plurality of input terminals and at least one of the plurality of output terminals, said second output terminal being separated from said first output terminal by a distance defined based on a bit vector applied to a subset of the plurality of configuration data terminals, said distance being a displacement in a quantity of output terminals from said first output terminal, the plurality of switches having a switch in a first stage of switches, the switch in the first stage of switches being at least a binary switch having at least a first input terminal configured to receive data from a first switch in a second stage of switches without the data being transmitted through another of the plurality of switches, the switch in the first stage switches having a second input terminal configured to receive data from a second switch in the second stage of switches without the data being transmitted through another of the plurality of switches, the second switch in the second stage of switches being in a row of switches located 2 M-k rows from a row of switches including the switch in the first stage of switches, M being a number representing a total number of stages of switches defined by the plurality of switches and k being a number representing an order of the first stage of switches within the total number of stages of switches.