Patent ID: 8891757

Claim:
A cryptographic integrated circuit comprising: a programmable main processor configured to execute cryptographic functions; an internal memory; a data transmission bus to which the main processor and the internal memory are electrically connected; and a programmable arithmetic coprocessor also electrically connected to the data transmission bus and being separate from the main processor, and comprising a plurality of specific hardware arithmetic units each configured to perform a predetermined arithmetical operation; a programmable sequencer that is electrically connected to each of the specific hardware arithmetic units and that includes additional arithmetic units; an input/output interface that can be connected to the data transmission bus; a command scheduler that interfaces between the input/output interface and the programmable sequencer; and a local memory that is electrically connected to the programmable sequencer and to each of the specific hardware arithmetic units, wherein the hardware architecture of at least one of the plurality of specific hardware arithmetic units is configured to perform modular arithmetical operations in a pipeline mode and to return several possible values from a requested single arithmetical operation, and also a parameter for selecting a single value from among said several possible values.