Patent ID: 7558137

Claim:
A semiconductor memory comprising: a plurality of memory cells; a word line connected to said memory cells; a plurality of bit lines connected to said memory cells respectively; a word driver connected to one end of said word line to drive said word line; a plurality of sense amplifiers connected to said bit lines respectively; a plurality of column switches disposed for said sense amplifiers respectively and selectively turned on according to a column address to connect said sense amplifiers to a common data line; and a sense amplifier control circuit which activates a sense amplifier activation signal to cause said sense amplifiers to operate, and during a test mode, changes a time interval from activation of the word line up to the activation of said sense amplifier, according to said column address in order to make constant a time interval after data is read from the test target memory cell to the bit line until the corresponding sense amplifier starts an amplifying operation, irrespective of a position of the memory cell.