Patent ID: 7435680

Claim:
A method of manufacturing a circuit substrate, comprising the steps of: forming, on a metal plate made of copper, a first wiring layer being a land having a multi-layer structure, a bottom side of said multi-layer structure being made of a metal layer having resistance to an etching liquid of the metal plate made of copper, an upper side of said multi-layer structure being made of a copper layer, the first wiring layer being electrically connected to the metal plate; forming, on the metal plate, an n-layered (n is an integer of 1 or more) wiring layer electrically connected to the first wiring layer through a via, the copper layer of the first wiring layer connected to the via, an uppermost wiring layer of the n-layered wiring layer having a connection pad area which is electrically connected to a semiconductor chip; forming a resin layer in which an opening portion is provided on the connection pad area of the uppermost wiring layer; forming an electroplating layer on the connection pad area of the uppermost wiring layer by an electroplating utilizing the metal plate and the wiring layer as a plating power-supply path; and removing the metal plate made of the copper selectively to the metal layer having resistance to the etching liquid of the metal plate, thereby exposing the metal layer, wherein the resin layer is left on the uppermost wiring layer.