Patent ID: 8638842

Claim:
An equalization device for receiving a signal transmitted from a signal transmission side as an input signal and for equalizing a degradation of a waveform of the received input signal, said qualization device comprising: a clock output section that outputs a clock signal; an equalizer that judges a bit value represented by said input signal on the basis of the waveform of the input signal according to said clock signal which is output from said clock output section, and outputs a judged signal that represents the judged bit value and that is made up of a plurality of bits; a phase detector that receives the judged signal output from said equalizer, detects a 2-bit transition signal, in which two successive bit values are identical to each other and in which bit values prior and subsequent to the two successive bit values are different from the two successive bit values, from the received judged signal, and output phase information representative of the phase of the detected 2-bit transition signal at a voltage threshold value which changes depending on a change in the phase of said clock signal; and a phase timing determiner that receives the phase information output from said phase detector, determines a timing to generate said clock signal based on the phase represented by the received phase information, and outputs timing information representative of the determined timing; wherein said clock output section generates said clock signal at the timing represented by the timing information output from said phase timing determiner.