Patent ID: 7088719

Claim:
A processor comprising: classification circuitry operative to identify for each of a plurality of packets received in the processor a corresponding packet flow identifier; control circuitry operatively coupled to the classification circuitry; and at least one operational unit operatively coupled to the control circuitry; wherein the control circuitry is operative to direct one or more packets having a given packet flow identifier to the at least one operational unit and maintains a desired function call sequencing over the one or more packets having the given packet flow identifier for one or more order-dependent processing tasks in the processor; the control circuitry comprising ordering logic, the ordering logic comprising: at least one ordering queue storing context identifiers in conjunction with respective function call identifiers and utilizing said context identifiers and said respective function call identifiers to maintain the desired function call sequencing for a designated set of functions; and at least one configuration register storing information specifying said set of functions that are ordered by the at least one ordering queue.