Patent ID: 7010637

Claim:
A system for interfacing over a bus, the system comprising: a single-ended control interface coupled with a first power supply, and a common supply, wherein the control interface comprises a control driver configured to output a control output current to drive a control output signal, the control driver including a resistive bias circuit configured to track the control output current supplied to a switching unit through a current source thereby adjusting the performance of the control driver; a plurality of single-ended memory interfaces coupled to a second power supply and the common supply, each memory interface including a memory driver configured to output current to drive a memory output signal, wherein the control and memory output signals are driven to the common supply to transfer a logic low; and the bus being coupled to the single-ended control interface, between the switching unit and the resistive bias unit, and to the plurality of single-ended memory interfaces, the control output signal being the voltage level common to the switching unit and the resistive bias unit.