Patent ID: 7385793

Claim:
A system, comprising: a memory circuit, comprising: an input/output (I/O) circuit; and an electrostatic discharge (ESD) shunt circuit coupled to the I/O circuit to shunt an ESD current to ground, the ESD shunt circuit comprising: a low voltage ESD transistor; a first high voltage ESD transistor in series with the low voltage ESD transistor; a gate clamp circuit coupled to the low voltage ESD transistor to clamp a gate-to-source voltage of the low voltage ESD transistor, the gate clamp circuit having an input, a low voltage output coupled to the gate of the low voltage ESD transistor and a ground reference coupled to the source of the low voltage ESD transistor, wherein the gate clamp circuit limits the low voltage output; and a trigger circuit coupled to the ESD shunt circuit to trigger the ESD shunt circuit in response to an ESD event.