Patent ID: 7408380

Claim:
A field programmable gate array (FPGA), comprising: a plurality of configurable interconnect resources coupled to a configuration memory and adapted to activate signal routes within the FPGA in response to data contained in the configuration memory; a first primary resource adaptively coupled to a first signal route in response to an affirmative test result for the first primary resource; and a first redundant resource adaptively coupled to the first signal route in response to a negative test result for the first primary resource, wherein the first primary resource is deactivated in response to the negative test result; wherein the first redundant resource comprises a first multiplexer coupled to the first primary resource and adapted to provide outbound signals to the first primary resource via the first multiplexer in response to the negative test result, and wherein the first primary resource comprises a second multiplexer coupled to the first redundant resource and adapted to provide outbound signals to the first redundant resource via the second multiplexer in response to the negative test result.