Patent ID: 7668988

Claim:
A bus inversion apparatus, comprising: a plurality of exclusive-OR gates, coupled to an instant data bus and a last data bus, said data buses having a corresponding plurality of bits, wherein said plurality of exclusive-OR gates is configured to perform a bitwise comparison of said data buses, and to provide an exclusive-OR bus, wherein the states of bits of said exclusive-OR bus indicate whether corresponding bits of said data buses are different; and an inversion detector; coupled to said exclusive-OR bus, configured to count the number of said corresponding bits that are different, and configured to indicate that said instant data bus should be inverted, wherein said inversion detector comprises: a plurality of left shift circuits, each configured to perform a logical left shift of input bits as directed by the states of shift bits, wherein outputs of said each of said plurality of left shift circuits indicate a number of a subgroup of said corresponding bits that are different.