Patent ID: 7158436

Claim:
A semiconductor memory device, comprising: a booster circuit for generating, according to an external power voltage, a predetermined power voltage exceeding the external power voltage; a global power line supplied with the predetermined power voltage from the booster circuit; and at least one memory block comprising: a plurality of word lines; a plurality of bit lines crossing the word lines; a plurality of memory cells corresponding to crossing points of the bit lines and the word lines; a local power line; a voltage control device, coupled between the global power line and the local power line, outputting the predetermined power voltage according to a select signal to the local power line in a first period and outputting a first voltage to the local power line in a second period, wherein the first voltage exceed the external power voltage but lower than the predetermined power voltage; and a plurality of word line drivers corresponding to the word lines, each comprising a power terminal coupled to the local power line and outputting the predetermined power voltage from the local power line to drive a corresponding word line in the first period.