Patent ID: 7707354

Claim:
A dual-boot caching flash microcontroller comprising: a flash bus for connecting to a flash-memory chip, the flash bus carrying address, data, and commands to the flash-memory chip; microcontroller boot code stored in the flash-memory chip in a first block; host boot code stored in the flash-memory chip in a host-boot block; a static random-access memory (SRAM) buffer; a central processing unit (CPU) for executing instructions read from the SRAM buffer; a host interface for connecting to an external host over a host bus; a flash-memory interface for generating flash-control signals and for buffering commands, addresses, and data to the flash bus, and for reading and writing the SRAM buffer; a boot-loader state machine, activated by a reset signal, for activating the flash-memory interface to read the microcontroller boot code from the flash-memory chip, the boot-loader state machine writing the microcontroller boot code to the first block in the SRAM buffer; a mapping table storing mapping entries each having a logical address from the external host and a physical address of corresponding data stored in the flash-memory chip; a tag portion of the SRAM buffer for storing tag portions of logical addresses from the external host; and a data portion of the SRAM buffer for caching data for locations in the flash-memory chip identified by the physical address in a matching entry in the mapping table, the matching entry also storing the logical address having a tag portion in a same cache line as data in the data portion.