Patent ID: 8140831

Claim:
A method for operating a superscalar processor, the method comprising: at a steering unit coupled between a first instruction issue queue and a second instruction issue queue of the superscalar processor: receiving at least first, second and third instructions of a plurality of ordered instructions that pass into instruction issue queue entries of the first instruction issue queue; determining that the first instruction and the second instruction of the plurality of ordered instructions are non-branching instructions, wherein the second instruction is subsequent to the first instruction; storing the first instruction and the second instruction in two non-branching instruction issue queue entries of the second instruction issue queue; determining whether or not the third instruction is a branch instruction, wherein the third instruction is subsequent to the second instruction; if the third instruction is a branch instruction, storing the third instruction in a branch entry of the second instruction issue queue; and if the third instruction is not a branch instruction, storing a no operation (NOP) instruction in the branch entry of the second instruction issue queue.