Patent ID: 8138028

Claim:
A method for manufacturing a plurality of memory cells, comprising: providing a substrate including access circuitry for the plurality of memory cells, and having a contact surface with an array of conductive contact plugs connected to the access circuitry; adding a layer of bottom electrode material on the contact surface of the contact plugs of the substrate; forming electrode pillar masks only partly covering the bottom electrode material, and isotropically trimming electrode pillar masks on the layer of bottom electrode material; removing material of the layer of bottom electrode material to form a pattern of electrode pillars on corresponding conductive contact plugs in the array of conductive contact plugs; forming a layer of dielectric material covering the pattern of electrode pillars and exposed portions of the contact surface; planarizing layer of dielectric material and electrode pillars to provide an electrode surface exposing tops of the electrode pillars in the pattern of electrode pillars, wherein the electrode pillars have pillar horizontal cross-sectional areas from the tops to bottoms of the electrode pillars; forming a layer of programmable resistive material on the electrode surface; forming a layer of top electrode material over the layer of programmable resistive material; and patterning the layer of programmable resistive material and the layer of top electrode material, the programmable resistive material having programmable resistive material horizontal cross-sectional areas from tops to bottoms of the patterned programmable resistive material, wherein all the pillar horizontal cross-sectional areas of a particular electrode pillar, are bounded by any of the programmable resistive material horizontal cross-sectional areas of a particular programmable resistive material element coupled to the particular electrode pillar.