Patent ID: 6985516

Claim:
A receiver unit, comprising: a first buffer operative to receive and store digitized samples comprising multiple instances of a received signal; a data processor coupled to the first buffer and operative to (a) retrieve different segments of the digitized samples one segment at a time from the first buffer, each of the retrieved different segments comprising one of the multiple signal instances, (b) process two or more of the retrieved different segments one segment at a time with one programmed despreading sequence to provide despread samples, (c) decover the despread samples with a channelization code of programmable length to provide decovered symbols, (d) demodulate the decovered symbols to provide demodulated symbols, and (e) combine the demodulated symbols from the multiple signal instances to provide processed symbols; a controller being operative to direct the data processor; a microcontroller coupled to the data processor and the controller, the microcontroller being operative to receive tasks from the controller, instantiate a state machine for each task, and direct the data processor to process the retrieved different segments; and an address generator coupled to the first buffer and the controller, the address generator being operative to implement a counter to control a write address for writing digitized samples to the first buffer, the counter being operative to send a signal to the controller to initiate processing of the stored samples by the data processor.