Patent ID: 7277346

Claim:
A method for repairing failures of a packaged integrated circuit system, the method comprising: providing a packaged integrated circuit system, the packaged integrated circuit system including a plurality of programmable logic devices, a plurality of random access memory devices associated with the plurality of programmable logic devices, a redundant circuit associated with a polysilicon fuse, a memory configured to store information associated with an operation configuration for the plurality of programmable logic devices and a test configuration for built-in self-test, and a controller associated with the memory and the plurality of random access memory devices; receiving, by the controller from the memory, information associated with the test configuration for built-in self-test; programming, by the plurality of random access memory devices, the plurality of programmable logic devices based on at least information associated with the test configuration for built-in self-test; providing at least an input to the programmed plurality of programmable logic devices; detecting at least an output from the programmed plurality of programmable logic devices in response to at least the input; comparing the detected output and a predetermined output; determining whether a circuit failure exists for the packaged integrated circuit system based on at least a result from the process for comparing the detected output and a predetermined output; if a circuit failure is determined to exist, repairing the circuit failure; wherein: the process for repairing the circuit failure includes activating the redundant circuit associated with the polysilicon fuse and deactivating a defective circuit associated with the circuit failure; the process for activating the redundancy circuit and deactivating the defective circuit includes providing a repair voltage to the polysilicon fuse and changing a conductivity state of the polysilicon fuse from a first state to a second state; the repair voltage is less than or equal to the highest operation voltage of the packaged integrated circuit system.