Patent ID: 7616207

Claim:
A graphics processing subsystem comprising: at least three graphics devices each adapted to be coupled to a system bus, the graphics devices including: a first graphics device configured to compute pixel data for a first portion of an image, wherein the first graphics device includes a pixel buffer configured to accept multiple parallel data requests; a second graphics device configured to compute pixel data for a second portion of the image; and a third graphics device configured to compute pixel data for a third portion of the image, wherein the first graphics device is further configured to supply pixel data from either of the first or second graphics devices to a display device, wherein the first, second, and third graphics devices are further configured such that the pixel data for the second and third portions of the image are transferred from the second and third graphics devices to the first graphics device via the system bus; wherein a size of the second portion of the image is determined at least in part by bandwidth of a first system bus connection between the second graphics device and the first graphics device, wherein a size of the third portion of the image is determined at least in part by bandwidth of a second system bus connection between the third graphics device and the first graphics device, and wherein the pixel data for the second portion of the image and the pixel data for the third portion of the image are communicated to the pixel buffer of the first graphics device in parallel.