Patent ID: 8219881

Claim:
A memory control method for converting a logical address from a CPU into a real address formed of a memory element selection address and a memory element address to access a plurality of memory elements, comprising: converting the logical address of the CPU having a logical address space divided into N areas into a real address with a selector corresponding to a way number W for accessing the plurality of memory elements by an interleave control and for reconfiguring a memory configuration by designation of a different way number W, recording, in real address utilization information, utilization prohibition information for an area of the logical address space that includes an abnormal portion, when abnormality of a memory element is detected, wherein the real address area utilization information is recorded with utilizable information for each area of the logical address space by dividing a real address space into areas (N×Wmax) by multiplying an area number N of the logical address space by a maximum way number Wmax of the interleave control, and generating logical address area utilization information recorded with the utilizable information or the utilization prohibition information for each area in the logical address space from the real address area utilization information, and deciding an area of the logical address space which is utilizable by the CPU.