Patent ID: 7825460

Claim:
A vertical field effect transistor array semiconductor structure comprising: a plurality of semiconductor pillars, where all vertical portions of each semiconductor pillar have a semiconductor pillar linewidth greater than a separation distance from an adjacent semiconductor pillar, and wherein at least one semiconductor pillar has a first linewidth and at least one other semiconductor pillar has a second linewidth different than the first linewidth, wherein said first linewidth of said at least one semiconductor pillar is equal to F+2s, where F is a minimum photolithographic resolvable dimension of a lithographic tool and s equals an annular linewidth of a spacer used to form at least one of said semiconductor pillars, and said second linewidth of said at least one other semiconductor pillar is equal to F+2s1+2s2, where F is as defined above, s1=s, and s2 equals a linewidth of a second spacer used in forming the at least one other semiconductor pillar; source/drain regions located within a top portion of each semiconductor pillar and within base portions of each semiconductor pillar, wherein each neighboring semiconductor pillar shares a common source/drain region at footprints thereof; a gate dielectric located on sidewalls and atop each semiconductor pillar, wherein a portion of said gate dielectric extends atop each common source/drain region; and a gate electrode annularly surrounding each of said semiconductor pillars, said gate electrode is absent from atop each semiconductor pillar and said gate electrode has a thickness ¼F, wherein F is as defined above.