Patent ID: 6868009

Claim:
An integrated circuit device, comprising: a memory array including a plurality of word lines and a plurality of bit lines, and configured to support vertical pages, vertical pages including a plurality of byte wide sets of memory cells, the byte wide sets of memory cells being coupled to respective word lines in the plurality of word lines, and coupled to bit lines in the plurality of bit lines in common with the other byte wide sets of memory cells of the vertical page; decoder circuitry coupled to the memory array, the decoder circuitry addressing one byte at a time by selecting one word line in the plurality of word lines, and the bit lines in common with the other byte wide sets of memory cells of the vertical page for erase processes; and a controller coupled to the decoder circuitry to control erasing of at least one selected byte within a selected page stored in memory cells coupled to a selected one word line, the controller including circuitry to map data stored in memory cells coupled to word lines in the selected page other than the selected one word line, to apply erase potentials to memory cells storing the at least one selected byte, and after applying erase potentials to memory cells storing the at least one selected byte, to verify that the memory cells in the selected page other than the memory cells coupled to the selected one word line have maintained thresholds indicated by the mapping, and to apply program potentials to memory cells in the selected page that do not pass verify.