Patent ID: 8299988

Claim:
A pulse signal delay circuit comprising: a first pulse edge delay circuit for generating a first delay timing signal for sequentially outputting a first edge detection delay timing gained by detecting a rising edge of an input pulse signal and delaying a detection timing of the rising edge by a preset delay time a predetermined number of times within one period of the input pulse signal; a second pulse edge delay circuit for generating a second delay timing signal for sequentially outputting a second edge detection delay timing gained by detecting a falling edge of the input pulse signal and delaying a detection timing of the falling edge by the delay time the predetermined number of times within one period of the input pulse signal; and a delay pulse signal generating circuit for generating delay pulse signals, of which a number is the same as the predetermined number of times of delays, from the first delay timing signal and the second delay timing signal for each combination of the first edge detection delay timing and the second edge detection delay timing delayed the same number of times, the delay pulse signals rising according to the first edge detection delay timing and falling according to the second edge detection delay timing, and for outputting the generated delay pulse signals, wherein the first pulse edge delay circuit comprises a first counter, the first counter starting a counting operation with a clock period of a system clock after the rising edge is detected, accepts the delay time as a delay counter value of a plurality of bits with one period of the system clock, as a unit time, generates the first edge detection delay timing whenever a counter value of the first counter coincides with the delay counter value, and at the same time, resets the counting operation of the first counter and repeats the counting operation the predetermined number of times, and the second pulse edge delay circuit comprises a second counter, the second counter starting a counting operation with the clock period of the system clock after the falling edge is detected, accepts the delay time as the delay counter value, generates the second edge detection delay timing whenever a counter value of the second counter coincides with the delay counter value, and at the same time, resets the counting operation of the second counter and repeats the counting operation the predetermined number of times.