Patent ID: 7073098

Claim:
A multi-phase clock generation circuit comprising: voltage controlled delay elements of N stages connected in cascade wherein N is an integer that is greater than 1; delay time control means for controlling a delay time of an output signal of each stage of said voltage controlled delay elements so that a phase of the output signal from the N-th stage of said voltage controlled delay elements matches a phase of a reference clock input in the first stage of said voltage controlled delay elements; delay time detection means for receiving time differences between said output signals of each stage and for generating delay time signals corresponding to time differences between output signals of consecutive ones of said stages; a delay time monitoring means for receiving said delay time signals and for monitoring the delay time of said voltage controlled delay elements based on said delay time signals; and a Locking condition control means for controlling a locking condition of the output signals of said voltage controlled delay elements based on a delay time monitoring result by said delay time monitoring means.