Patent ID: 7589379

Claim:
A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device, wherein said power semiconductor includes multiple electrically insulating layers between said semiconductor substrate and said power device, said electrically insulating layers having a combined thickness of at least 5 μm, wherein said insulating layers are at least partially defined by a plurality of interleaved metallization layers such that layers of each adjacent pair of said insulating layers are partially isolated from one another vertically by a corresponding interleaved metallization layer, wherein the plurality of metallization layers have metal fins extending into a plurality of said electrical insulating layers and have a via connection between layers of each adjacent pair of the metallization layers and between one of said electrical contact regions of said power device and the metallization layer adjacent thereto; and whereby said metallization layers having said metal fins and via connections form a heatsink extending from the one of said electrical contact regions of said power device through said plurality of metallization layers all the way to the last electrically insulating layer towards said semiconductor substrate to enhance thermal conduction from said power device to said semiconductor substrate.