Patent ID: 7872491

Claim:
A noise filter circuit comprising: a first inverter circuit that receives a signal based on an input signal, the first inverter circuit generating a first signal with a delay amount based on the input signal, a rise time of the first signal being longer than a fall time of the first signal; a second inverter circuit that receives a signal based on the input signal, the second inverter circuit generating a second signal with the delay amount based on the input signal, a rise time of the second signal being longer than a fall time of the second signal; a latch circuit that receives signals based on the first signal and the second signal as a set signal and a reset signal, the latch circuit removing a noise having a pulse width smaller than the delay amount; one of the first inverter circuit and the second inverter circuit including a P-type transistor and an N-type transistor, the capability of the P-type transistor being lower than the capability of the N-type transistor; and the other of the first inverter circuit and the second inverter circuit including a P-type transistor and an N-type transistor, the capability of the P-type transistor being lower than the capability of the N-type transistor.