Patent ID: 7707522

Claim:
A method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, comprising the actions of: a. using a computer, determining a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape; b. assigning a cost to each placement, the cost indicating an amount of undesirable jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater undesirable jog would be created in the masking process than would be created by a placement assigned a lesser cost, wherein the assigning a cost action comprises the actions of: i. assigning a zero cost to a placement when an outer edge of the wire is flush with the selected edge of the shape; ii. assigning a minimum non-zero cost to a placement when the outer edge of the wire is at least a minimum feature distance away from the selected edge of the shape; and iii. assigning a cost greater than the minimum non-zero cost to a placement when the outer edge of the wire is not flush with the selected edge of the shape and is less than the minimum feature distance away from the selected edge of the shape; and c. selecting a placement having a lowest cost of the plurality of possible placements.