Patent ID: 8225026

Claim:
A data packet access control apparatus, communicatively connected with an external Random Access Memory (RAM) having a plurality of external queues, the apparatus comprising: an ingress queue unit, configured with a plurality of ingress queues; an egress queue unit, configured with a plurality of egress queues; wherein each ingress queue is uniquely corresponding to an the egress queue, and each pair of ingress queue and egress queue is uniquely corresponding to an external queue in the external RAM; a memory control unit, adapted to respectively store data packets of the ingress queues into their corresponding external queues in the external RAM, and to respectively read data packets to be stored in the egress queues from the corresponding external queues in the external RAM; a Bypass FIFO, adapted to cache the data packets of the ingress queues and transmit the data packets to the corresponding egress queues; an ingress control unit, adapted to provide a data packet in an ingress queue to the memory control unit if the ingress queue is non-empty and a corresponding external queue has a data packet and is non-full; to write the data packet in the ingress queue into the Bypass FIFO if a corresponding external queue is empty and the Bypass FIFO and a corresponding egress queue are both non-full; to provide the data packet in the ingress queue to the memory control unit if the corresponding external queue is empty and the Bypass FIFO or the corresponding egress queue is afull or full; and to perform no reading/writing operation for the ingress queue if the external queue is full; and an egress control unit, adapted to read a data packet from the Bypass FIFO and store the data packet into an egress queue if the Bypass FIFO is non-empty; to request the memory control unit to read a data packet from a corresponding external queue and store the data packet into the egress queue if the Bypass FIFO is empty and the egress queue is non-full and the corresponding external queue is non-empty; and to perform no reading/writing operation for the egress queue if the Bypass FIFO is empty and the corresponding external queue has no data packet.