Patent ID: 8338929

Claim:
A stacked-type chip package structure, comprising: a substrate having a first surface and a second surface; a first chip having a back surface and an active surface, wherein the back surface of the first chip is disposed on the first surface of the substrate in a vertical direction; a spacer layer covering the active surface of the first chip; a second chip having a back surface and an active surface, the back surface of the second chip being disposed on the spacer layer in the vertical direction, wherein the spacer layer is directly in contact with the active surface of the first chip and the back surface of the second chip; two first conductive bumps disposed on the first surface of the substrate and being directly in contact with the substrate; two first flexible circuit boards respectively disposed on and being in contact with each of the two first conductive bumps in the vertical direction, each of the two first flexible circuit boards being electrically connected to the first chip by a first conductive wire, wherein the first chip is not in direct contact with each of the two first flexible circuit boards and is separated from the two first flexible circuit boards in a horizontal direction by a first gap; two second conductive bumps respectively disposed on each of the two first flexible circuit boards; and two second flexible circuit boards respectively disposed on each of the two second conductive bumps, each of the two second flexible circuit boards being electrically connected to the second chip by a second conductive wire, wherein the second chip is not in direct contact with each of the two second flexible circuit boards and is separated from the two second flexible circuit boards in the horizontal direction by a second gap.