Patent ID: 6968515

Claim:
A semiconductor circuit designing apparatus, comprising: a circuit design unit which executes a logical design of a semiconductor integrated circuit; and an inspection item database section in which a circuit feature of said semiconductor integrated circuit corresponds to at least one inspection item of an inspection to be executed before a layout design of said semiconductor integrated circuit is executed, wherein said circuit design unit generates circuit feature information indicating said circuit feature for said semiconductor integrated circuit for which said logical design should be executed, wherein said circuit design unit obtains a certain inspection item of said at least one inspection item corresponding to said target circuit feature information from said inspection item database section, and wherein said circuit design unit executes said logical design of said semiconductor integrated circuit in reference to said certain inspection item, and further comprising: a model development history database section in which ID data of said circuit design unit is stored corresponding to a number of times said circuit design unit failed said inspection of each one of said at least one inspection item previously, wherein said certain inspection item is determined such that an inspection item of said at least one inspection item for which said number of times is smaller than a predetermined value is withdrawn from said at least one inspection item.