Patent ID: 8489927

Claim:
A method for inspecting a central processing unit (CPU), the method being adapted for use in an inspection device, the inspection device being electrically connected to the CPU and comprising a receiving interface and a processor, the method comprising the following steps of: (a) enabling the receiving interface to receive a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval; (b) enabling the processor to set the first data stream as a good log; (c) enabling the receiving interface to receive a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval; (d) enabling the processor to set the second data stream as an erroneous log; (e) enabling the processor to compare the good log with the erroneous log to determine a segment of the erroneous log as an erroneous range; and (f) enabling the processor to determine a defect of the CPU according to the erroneous range; wherein the CPU comprises a CPU core, a cache, a memory management unit (MMU) and a code interface, the CPU is electrically connected to a dynamic random access memory (DRAM) and a hard disk, the reference hardware inspection program is stored in the hard disk, the CPU core is configured to load the reference hardware inspection program into the cache and the DRAM to execute the reference hardware inspection program, the MMU is configured to record an address mapping relationship of the reference hardware inspection program among the cache, the DRAM and the hard disk, the erroneous range is a linear address range, the first data stream comprises a first code data stream, the second data stream comprises a second code data stream, the step (a) is to enable the receiving interface to receive the first code data stream from the code interface, and the step (c) is to enable the receiving interface to receive the second code data stream from the code interface.