Patent ID: 6854083

Claim:
An electrically erasable and programmable memory (EEPROM) comprising: a memory array comprising word lines and a plurality of columns of bit lines, memory cells connected to the word lines and bit lines, read circuits connected to the memory cells via the bit lines, a programming line, and a plurality of programming latches each connecting one of the bit lines to the programming line; a plurality of switches each being connected in a bit line between the memory cells and the programming latches, the switches of one column of bit lines defining a group of switches for interrupting connections between memory cells of the column and associated read circuits of the column when data has been loaded into the programming latches of the column, without interrupting connections between the programming latches of the column and the read circuits of the column; and a plurality of memory circuits each for controlling one group of switches of one column of bit lines and providing a signal to open the switches of the group after a loading signal is received by the programming latches of the column.