Patent ID: 8515000

Claim:
A shift register circuit comprising: a plurality of shift registers, each of the shift registers being configured for outputting a corresponding start-pulse signal and a corresponding driving-pulse signal, and each of the shift registers comprising: a pull-up circuit receiving the corresponding start-pulse signal outputted from a nearest preceding shift register and a reference signal to charge a first node; a first driving circuit electrically coupled to the pull-up circuit at the first node and receive a corresponding clock signal, to generate the corresponding start-pulse signal according to a voltage on the first node; a second driving circuit electrically coupled to the pull-up circuit at the first node and receive a high reference voltage, to output the corresponding driving-pulse signal at an output terminal of the second driving circuit; and a discharging circuit comprising: a first transistor comprising a first control terminal, a first terminal and a second terminal, the first terminal being electrically coupled to the first node, the second terminal being electrically coupled to a low reference voltage and the first control terminal receiving a first control signal to discharge the first node during a first time period; and a second transistor comprising a second control terminal, a third terminal and a fourth terminal, the third terminal being electrically coupled to the output terminal of the second driving circuit, the fourth terminal being electrically coupled to the low reference voltage and the second control terminal receiving a second control signal to discharge the output terminal of the second driving circuit during a second time period; wherein a start point of the first time period is earlier than that of the second time period.