Patent ID: 8798038

Claim:
An apparatus, comprising: packetization logic is configured to generate an efficient header in packetized protocols for a flexible routing network for a Network on a Chip (NoC) architecture which connects disparate initiators and targets; wherein the packetization logic is located at an interface between at least a first initiator or a first target and the flexible routing network and a second initiator or a second target and the flexible routing network, and is configured to receive transmission traffic from the first and the second initiators or the first and second targets and packetize the transmission traffic into a first packet from the first initiator or the first target and a second packet from the second initiator or the second target for transmission to an input port of a downstream router element; wherein the first packet comprises a first header portion and a first body portion, and the second packet comprises a second header portion and a second body portion, wherein the first header portion and the second header portion are initially variable in length, and wherein the first header portion initially has a different length than the second header portion; wherein each of the first and the second header portions include a header payload and header control information which includes routing information and other types of control information; wherein the packetization logic is configured to dynamically customize the lengths of the first header portion and the second header portions by breaking the first header portion and the second header portion into a group of outgoing transmission units that all have a common width suitable for the width of the input port of the downstream router element; wherein each of the first and the second header portions and each of the first and the second body portions includes a type field to indicate either a head, a body, the head followed by another head, the head followed by the body, the head and also a tail, or the body and also the tail; and wherein the width of the header payload is determined based on orthogonal groups, with each of the orthogonal groups being associated with targets sharing an initiator thread, and wherein a maximum width of information accepted by the targets sharing the initiator thread is used as the common width of the header payload for a particular orthogonal group.