Patent ID: 8909907

Claim:
In a microprocessor with branch prediction, the microprocessor including a microprocessor pipeline having an instruction stream and a branch target buffer, a method for reducing branch prediction latency, the method comprising: reading most-recently-used information from a most-recently-used table associated with the branch target buffer where each most-recently-used entry in the most-recently-used table corresponds to one or more branch target buffer rows and specifies the ordering from least-recently-used to most-recently-used of branch target buffer columns in the one or more branch target buffer rows; selecting a row from the branch target buffer based on a current search address and simultaneously selecting an associated entry from the most-recently-used table identifying a most-recently-used column of the branch target buffer columns from the selected row from the branch target buffer; and speculating that there is a prediction corresponding to the current search address in the most-recently-used column of the branch target buffer columns from the selected row from the branch target buffer while determining whether one of the branch target buffer columns of the selected row contains the prediction corresponding to the current search address and prior to determining whether the most-recently-used column of the branch target buffer columns from the selected row from the branch target buffer correctly identified the prediction.