Patent ID: 8039811

Claim:
A CMOS TDI detector stage comprising: an integrating and summing amplifier having an integrating input terminal, a summing input terminal which may be joined to or may be separated from said integrating input terminal, an output terminal, an integration capacitor, and a reset switch; a photo-detector connecting to said integrating input terminal of said integrating and summing amplifier; a summing capacitor of which a first electrode is connected to output of prior TDI stage and a second electrode is connected to said summing input terminal of said integrating and summing amplifier; a correlated double sample and hold (CDS) circuit comprising a plural of switches and a plural of storage circuits, having an input terminal connected to said output terminal of said integrating and summing amplifier, and an output terminal connected to summing capacitor of the following TDI stage; and wherein said integrating and summing amplifier is first reset by closing said reset switch, and when said reset switch is subsequently open, the reset signal of said photo-detector and the reset signal stored in CDS circuit of said prior TDI stage are summed and immediately sampled and held by said CDS circuit; thereafter said integrating and summing amplifier starts integrating photo-signal of said photo-detector and simultaneously sums integrated photo-signal of said photo-detector and the photo-signal stored in said CDS circuit of said prior TDI stage into a combined photo-signal which is sampled and held by said CDS circuit; and consequently said combined photo-signal and said reset signal held in said CDS circuit are ready for transfer to said following TDI stage.