Patent ID: 7463640

Claim:
A self-synchronous FIFO memory device having a plurality of self-synchronous data transmission lines each composed of a self-synchronous signal control circuit and a data hold circuit, the self-synchronous FIFO memory device comprising: a parallel structure in which the plurality of self-synchronous data transmission lines are connected in parallel; an input control section for selecting one of the self-synchronous data transmission lines contained in the parallel structure and then outputting to the selected self-synchronous data transmission line a first transfer request signal inputted from a preceding-stage section, and for outputting to the preceding-stage section a first acknowledge signal outputted from the selected self-synchronous data transmission line, and further for, given a state that data transfer toward the selected self-synchronous data transmission line is enabled, outputting, to the selected self-synchronous data transmission line, input data inputted from the preceding-stage section; and an output control section for selecting one of the self-synchronous data transmission lines contained in the parallel structure and then outputting to a succeeding-stage section a second transfer request signal outputted from the selected self-synchronous data transmission line, and for outputting to the selected self-synchronous data transmission line a second acknowledge signal inputted from the succeeding-stage section, and further for, given a state that data transfer toward the succeeding-stage section is enabled, outputting, to the succeeding-stage section, output data outputted from the selected self-synchronous data transmission line.