Patent ID: 7376015

Claim:
A semiconductor device comprising a nonvolatile memory array and a central processing unit, wherein said nonvolatile memory array comprises a control circuit, a plurality of nonvolatile memory cells including a first nonvolatile memory cell and a second nonvolatile memory cell, a plurality of data lines including a first data line and a second data line, and a word line, wherein said word line is coupled to both of said first nonvolatile memory cell and said second nonvolatile memory cell, wherein said first data line is coupled to said first nonvolatile memory cell, and said second data line is coupled to said second nonvolatile memory cell, wherein said central processing unit is adapted to control a write operation by setting a control bit in a control register, wherein in said write operation, said control circuit performs control in accordance with said control bit in said control register, said word line is supplied with a program voltage, said first data line is supplied with a first voltage after said program voltage has been supplied to said word line, and said second data line is supplied with said first voltage after a start of suppling said first voltage to said first data line, and wherein said central processing unit is adapted to control a verify operation, for checking whether data has been written to said first nonvolatile memory cell and said second nonvolatile memory cell, after said first voltage has been supplied to said second data line.