Patent ID: 7679138

Claim:
A semiconductor device comprising a MOS transistor in a SOI layer of a first conductivity type in a SOI substrate, said SOI substrate including a semiconductor substrate, a buried insulating film on said semiconductor substrate and said SOI layer on said buried insulating film, wherein said MOS transistor includes first and second MOS transistors sharing a one-side common electrode region, said first MOS transistor includes: said one-side common electrode region and an other-side first electrode region of a second conductivity type selectively provided in said SOI layer, a region sandwiched between said one-side common electrode region and said other-side first electrode region being defined as a first body region of the first conductivity type; and a first gate electrode on said first body region, said second MOS transistor includes: said one-side common electrode region and an other-side second electrode region of the second conductivity type selectively provided in said SOI layer, a region sandwiched between said one-side common electrode region and said other-side second electrode region being defined as a second body region of the first conductivity type; and a second gate electrode on said second body region, said semiconductor device further comprising: one-side first and second insulative partial isolation regions provided in said SOI layer close to one-end region of said first and second gate electrodes; one-side first and second semiconductor regions which are a part of a lower portion of said SOI layer between said buried insulating film and said one-side first and second insulative partial isolation regions; a common active region including said one-side common electrode region, said other-side first electrode region, said first body region, said other-side second electrode region and said second body region, said one-side first and second insulative partial isolation regions being adjacent to said first and second body regions, respectively; an insulative full isolation region provided at least in a region except a region close to both end regions of each of said first and second gate electrodes and except a region between said first and second gate electrodes in a peripheral region of said common active region, said insulative full isolation region extending through said SOI layer; and one-side first and second body-fixing active regions of the first conductivity type adjacent to said one-side first and second semiconductor regions, respectively, said one-side first and second body-fixing active regions each being capable of receiving a fixed potential from outside.