Patent ID: 8484602

Claim:
A method comprising: providing a first integrated circuit design netlist; mapping groupings of cell instances within the first integrated circuit netlist as corresponding to a preferential set of cells in a first library of cells, stored on a nontransitory computer-readable medium; removing from the mapping instances of nonpreferable cells associated with a first nonpreferable cell, wherein the mapping will not include any cell mappings associated with the first nonpreferable cell wherein the removing from the mapping instances of nonpreferable cells associated with a first nonpreferable cell comprises: removing sizes of cell instances that are not used in the initial integrated circuit design netlist; and removing a cell instance when it is used fewer than X times, wherein X is a user-defined threshold parameter; and generating a second library comprising only the preferential set of cells identified in the mapping, wherein the second library does not include any cell mappings associated with the first nonpreferable cell and is stored on a nontransitory computer-readable medium, and the generating a second library includes performing a physical synthesis, not a logic synthesis, to obtain cells for the second library.