Patent ID: 7479676

Claim:
A transistor of a semiconductor memory device, comprising: a semiconductor substrate having a plurality of active regions and a device isolation region; a plurality of first and second trench device isolation layers arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height; a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between two adjacent second trench device isolation layers; and a plurality of gate insulation layers and gate stacks sequentially to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.