Patent ID: 6934191

Claim:
A nonvolatile semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction, wherein each of the memory cells includes a source region, a drain region, a channel region between the source region and the drain region, a word gate and a select gate disposed to face the channel region, and a nonvolatile memory element formed between the word gate and the channel region, wherein the memory cell array includes: a plurality of wordlines, each of the wordlines being connected in common with the word gates of the memory cells arranged in the row direction; a plurality of selectlines, each of the selectlines being connected in common with the select gates of the memory cells arranged in the row direction; a plurality of bitlines, each of the bitlines being connected in common with the drain regions or the source regions of the memory cells arranged in the column direction; a wordline-and-selectline driver section which drives the wordlines and the selectlines; and a bitline driver section which drives the bitlines, wherein the wordline-and-selectline-driver-section includes a plurality of unit wordline-and-selectline-driver-sections, and wherein each of the unit wordline-and-selectline driver sections drives the select gates and the word gates of the memory cells in each row at a single potential.