Patent ID: 8185570

Claim:
A three-term input floating-point adder-subtractor comprising: cancellation detection means, including comparators and gate circuits, for detecting that two out of the three terms cancel out each other in an operation; a selector for selectively outputting the three terms, wherein the two out of the three terms are output as zero when the cancellation detection means detects that the two terms cancel out each other; shifters for making a digit adjusting shift with a width of 2n+3 bits on a mantissa of a first term having an exponent of intermediate value and a mantissa of a second term having minimum exponent in the three terms, where n is a bit width of a mantissa of each term, and, for each shifted mantissa, updating a respective least significant bit as a sticky bit with a corresponding logical combination of bits that overflowed the 2n+3 bit width by the respective digit adjusting shift, an adder-subtractor for carrying out addition and subtraction on the three terms output by the selector having the 2n+3 bit width and outputting a result; a normalizer for normalizing the result; and a rounding circuit for carrying out rounding in a nearest value (RN) mode using an (n+3)th bit from a most significant bit of the result as a new sticky bit.