Patent ID: 7385426

Claim:
A buffer circuit ( 318 ), comprising: a first half circuit and a second half circuit, each half circuit comprising: a first MOS transistor (M 4 , M 9 ) of a first type having a gate terminal coupled to receive an input voltage, a first current handling terminal coupled to receive a first current (I 21 , I 22 ), a second current handling terminal coupled to receive a second current (I 11 , I 12 ) having a current value less than the first current, and a body terminal connected to the second current handling terminal; a second MOS transistor (M 23 , M 22 ) of a second type, opposite to the first type, having a gate terminal coupled to the second current handling terminal of the first MOS transistor, a first current handling terminal coupled to receive a third current (I 31 ), a second current handling terminal coupled to the first current handling current of the first MOS transistor; and a third MOS transistor (M 5 , M 8 ) of the first type having a gate terminal coupled to the first current handling terminal of the first MOS transistor, a first current handling terminal coupled to an output load device (M 26 , M 27 ) and providing a differential output voltage, a second current handling terminal coupled to receive the third current (I 31 ) and a body terminal coupled to the second current handling terminal; wherein the first half circuit receives a buffer input voltage as the input voltage and the second half circuit receives a reference voltage as the input voltage, the first and second half circuits providing a pair of differential output signals indicative of the buffer input voltage.