Patent ID: 8125844

Claim:
A semiconductor memory device, comprising: a first cell array including a plurality of unit cells, each of which has a PMOS transistor and a capacitor, and a plurality of bit line pairs, wherein the first cell array provides a data signal stored in a unit cell selected from the unit cells to a first bit line pair selected from the bit line pairs, the first bit line pair containing a first bit line and a first bit line bar; a bit line sense amplifier for sensing and amplifying a voltage difference between the first bit line and the first bit line bar after the data signal is provided to the first bit line pair; a first reference cell block for transmitting a reference signal to the first bit line bar when the data signal is loaded on the first bit line and for transmitting the reference signal to the first bit line when the data signal is loaded on the first bit line bar; and a first precharge block for equalizing voltage levels of the first bit line and the first bit line bar during a precharge period without supplying a precharge voltage to the first bit line pair.