Patent ID: 7327808

Claim:
A pipelined adaptive decision feedback equalizer for equalizing a signal received from a channel, comprising: a pre-processing unit (PP) comprising a plurality of PP coefficients for filtering the signal, and generating a PP output signal; a feedforward filter (FFF) comprising a plurality of FFF coefficients, coupled to the pre-processing unit to receive the PP output signal; an adder coupled to the feedforward filter and outputting an added signal; a slicer coupled to the output terminal of the adder, the slicer outputting a decision signal based on the added signal; a feedback filter (FBF) comprising a plurality of FBF coefficients, coupled to the slicer for receiving the decision signal, the feedback filter canceling post-cursor ISI and generating a FBF output signal; a delay unit coupled between the feedback filter and the second input terminal of the adder, the delay unit receiving the FBF output signal and generating a delayed FBF output signal to the adder, wherein the delay unit is a n 1 -tap delay block, n 1 is positive integer and n 1 ≧2; a first weight-update block for adapting the FBF coefficients to cancel the post-cursor ISI and selecting a plurality of mapping coefficients from the FBF coefficients; and a mapping circuit for translating the plurality of mapping coefficients by a predetermined method to generate the PP coefficients and outputting the PP coefficients to the pre-processing unit, wherein at least one element of the plurality of mapping coefficients is different from a corresponding element of the coefficients.