Patent ID: 8724375

Claim:
A method of operating an integrated circuit containing an SRAM cell array, comprising: writing a low data bit value to an addressed SRAM cell in said SRAM cell array, by the method further including the steps of: adjusting a bias potential on a first n-well in said addressed SRAM cell whereby a ratio of an on-state current of a bit passgate transistor in said addressed SRAM cell to an on-state current of a bit driver transistor in said addressed SRAM cell is increased; adjusting a bias potential on a second n-well in said addressed SRAM cell whereby a ratio of an on-state current of a bit-bar passgate transistor in said addressed SRAM cell to an on-state current of a bit-bar driver transistor in said addressed SRAM cell is increased; coupling a bit data line in said addressed SRAM cell to a low voltage; coupling a bit-bar data line in said addressed SRAM cell to a high voltage; and coupling a word line in said addressed SRAM cell to said low voltage; writing a high data bit value to said addressed SRAM cell, by a process further including the steps of: adjusting said bias potential on said first n-well in said addressed SRAM cell whereby said ratio of said on-state current of said bit passgate transistor in said addressed SRAM cell to said on-state current of said bit driver transistor in said addressed SRAM cell is increased; adjusting said bias potential on said second n-well in said addressed SRAM cell whereby said ratio of said on-state current of said bit-bar passgate transistor in said addressed SRAM cell to said on-state current of a bit-bar driver transistor in said addressed SRAM cell is increased; coupling said bit data line in said addressed SRAM cell to said high voltage; coupling said bit-bar data line in said addressed SRAM cell to said low voltage; and coupling said word line in said addressed SRAM cell to said low voltage; and reading a data bit value from said addressed SRAM cell, by a process further including the steps of: adjusting said bias potential on said first n-well in said addressed SRAM cell whereby said ratio of said on-state current of said bit passgate transistor in said addressed SRAM cell to said on-state current of said bit driver transistor in said addressed SRAM cell is decreased; adjusting said bias potential on said second n-well in said addressed SRAM cell whereby said ratio of said on-state current of said bit-bar passgate transistor in said addressed SRAM cell to said on-state current of a bit-bar driver transistor in said addressed SRAM cell is decreased; coupling said bit data line in said addressed SRAM cell to said low voltage; coupling said bit-bar data line in said addressed SRAM cell to said low voltage; floating said bit data line in said addressed SRAM cell; floating said bit-bar data line in said addressed SRAM cell; and connecting said word line in said addressed SRAM cell to said low voltage.