Patent ID: 8710890

Claim:
A delay circuit as a multi-stage switching-type delay circuit, comprising multiple stages, each of the stages including: a delay unit; and a selector unit, the delay unit having: a delay unit first input; a delay unit first output connected to the delay unit first input; a delay unit second input; a delay unit second output connected to the delay unit second input; and at least one delay element, each provided between the delay unit first input and the delay unit first output, or between the delay unit second input and the delay unit second output, the selector unit having: a selector unit first input connected to the delay unit first output; a selector unit first output; a selector unit second input; a selector unit second output connected to the delay unit second input; and selectors to switch connections between the selector unit first input and the selector unit second output, between the selector unit second input and the selector unit first output, between the selector unit first input and the selector unit first output, and between the selector unit second input and the selector unit second output, respectively, wherein an input of the delay circuit corresponds to the delay unit first input of a first stage of the multiple stages, wherein an output of the delay circuit corresponds to the delay unit second output of the first stage, wherein the selector unit first output of each stage is connected to the delay unit first input of a next stage of the multiple stages, wherein the selector unit second input of each stage is connected to the delay unit second output of the next stage, and wherein, if the selector unit in one stage of the multiple stages of the delay circuit selects the connection between the selector unit first input and the selector unit second output, and the connection between the selector unit second input and the selector unit first output, the selector unit second input is connected to the input of the delay circuit such that the selector unit first input, the selector unit first output, the selector unit second input, and the selector unit second output are identical in logic state to each other in the one stage.