Patent ID: 6917072

Claim:
A semiconductor memory device comprising: a semiconductor region having a first conductivity type; source and drain regions of an electrically programmable and erasable memory cell transistor, provided in the semiconductor region, having a second conductivity type; a gate insulating film structure provided on the semiconductor region between the source and drain regions, the gate insulating film structure being comprised of a first insulating film, a charge accumulation layer and a second insulating film, the charge accumulation layer being composed of one material selected from a silicon nitride film, a silicon oxynitride film, an alumina film and a stacked film of these films; a control gate electrode provided on the second insulating film; a gate sidewall provided on a side of the control gate electrode, the thickness thereof being thinner than that of the second insulating film in the central area of the control gate electrode; a third insulating film provided above the control gate electrode; and a fourth insulating film provided to cover the gate electrode sidewall and the third insulating film therewith, wherein the thickness of the gate sidewall is in the range from 0.6 nm to 6 nm.