Patent ID: 8478553

Claim:
A method for verifying the design of an electronic circuit represented in the form of masks and connections, the method comprising: using a computer to: (a) define the circuit, using one or more extraction programs, in the form of a first list of electrical components and connections between them, the first list identifying resistive and non-resistive components of the circuit from a layout obtained from lithographic masks or descriptions of lithographic masks of the electronic circuit; (b) identify entry ports and exit ports of said electronic circuit, said entry ports and exit ports being known from the layout of the circuit; (c) select from said list only the resistive components of said electronic circuit; (d) produce a matrix of resistances from the selected resistive components, the matrix of resistances using a resistance network tree representation having Nc vertices and Nb branches and comprising a set in matrix form of a value R TT representing a vector of branch resistors, a value R CT representing a vector of resistors of a co-tree connected in parallel, and a value R CC representing a vector of resistors of the co-tree; (e) calculate equivalent resistances of the matrix of resistances; and (f) use the calculated equivalent resistances to perform tests on the electronic circuit design, the method further comprising: modifying the electronic circuit design or commencing production of the electronic circuit depending on the outcome of the tests.