Patent ID: 7424019

Claim:
A packet processor for a network device that alters headers of packets, comprising: an incoming port; a first outgoing port; a control data processor of the packet processor that receives a first control portion of a first packet from said incoming port and that transmits said first control portion to said first outgoing port, wherein said control data processor receives said first control portion independent from a first portion of said first packet; a header altering device that strips, modifies and encapsulates said first portion of said first packet on egress based upon first protocol layering requirements of said first outgoing port, wherein said header altering device includes: a stripping stage that strips protocol layers from said first portion; a header manipulator stage that communicates with said stripping stage and that performs header manipulation on a header of said first portion; a tunneling stage that communicates with said header manipulator stage and that at least one of adds tunnels to said first portion and removes tunnels from said first portion; and an encapsulation stage that communicates with said tunneling stage and that adds protocol layering that is required by at least one outgoing port, wherein said stripping stage initiates a tunnel request to a first table that stores tunnel data for said first portion; and a tunnel sync stage that communicates with said stripping stage and that synchronizes tunnel data returned from said first table with said stripped first portion, wherein said header manipulator stage communicates with a second table that stores address resolution protocol (ARP) data.