Patent ID: 7210059

Claim:
A memory module for a memory system, comprising: a plurality of memory devices; and a memory hub, comprising: a link interface for receiving memory requests for access to at least one of the memory devices, the link interface having transmitter and receiver logic having adjustable timing and voltage levels adjusted according to link interface control signals; a memory device interface coupled to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices, the memory device interface having output buffers having adjustable slew rate and drive strength adjusted according to memory device interface control signals; a switch for selectively coupling the link interface and the memory device interface; and a memory hub diagnostic engine coupled to the switch for coupling to the link interface and the memory device interface to perform diagnostic testing of the memory system, the diagnostic engine having a maintenance port to provide access to results of the diagnostic testing and to receive diagnostic testing commands, the memory hub diagnostic engine configured to generate link interface control signals to adjust timing and voltage levels of the link interface and generate memory device interface control signals to adjust slew rate and drive strength of the memory device interface in response to corresponding diagnostic testing commands.