Patent ID: 7110029

Claim:
A data processing arrangement comprising: an input circuit for forming data items into successive groups of data and for generating a basic control data item and an additional control data item for each group of the successive groups of data the additional control data item indicating for each data item if this data item is valid or not valid; a data processing circuit, containing a plurality of terminals, for processing the data applied to the terminals in order to obtain an output data item; and an interconnection network comprising a plurality of logic circuits, each of which corresponds to one of said plurality of terminals, for supplying a plurality of final control values based on the basic control data item and the additional control data item, wherein the interconnection network applies selected ones of the data items in a selected one of the successive groups of data from said input circuit to corresponding ones of said plurality of terminals of said processing circuit if the corresponding final control value indicates the data item is valid and, wherein one of the plurality of logic circuit replaces a basic control value of the corresponding basic control data item if the corresponding final control value indicates the data item is not valid.