Patent ID: 7499322

Claim:
An integrated circuit device, comprising: a random access memory (RAM) array having a plurality of columns of RAM cells therein and a first plurality of bit lines electrically connected to the plurality of columns of RAM cells; a non-volatile memory array having a plurality of columns of non-volatile memory cells therein and a second plurality of bit lines electrically connected to a plurality of columns of non-volatile memory cells; a data transfer circuit electrically connected to the first and second pluralities of bit lines, said data transfer circuit configured to support direct bidirectional communication between the first and second pluralities of bit lines when transferring non-volatile memory data directly from the second plurality of bit lines to the first plurality of bit lines and transferring RAM data directly from the first plurality of bit lines to the second plurality of bit lines; and a page buffer electrically coupled to the second plurality of bit lines, said page buffer configured to drive the second plurality of bit lines with data read from said non-volatile memory array when said data transfer circuit is enabled to support transfer of non-volatile memory data from the second plurality of bit lines to the first plurality of bit lines.