Patent ID: 7449933

Claim:
A voltage level translator to convert a digital input signal lying between a ground voltage and a low voltage level to a digital output signal lying between the ground voltage and a high voltage level, comprising: a first n-channel transistor and a second n-channel transistor arranged to force to the ground voltage a first connection node and a second connection node, respectively, wherein said first n-channel transistor is driven by a voltage at a first control node, and said second n-channel transistor is driven by a voltage at a second control node, the voltages at said first and second control nodes being respectively controlled by complementary control signals derived from the digital input signal; a first p-channel transistor and a second p-channel transistor arranged to force to the high voltage level the first connection node and the second connection node, respectively, wherein said first n-channel transistor is driven by a voltage at the second connection node, said second p-channel transistor is driven by a voltage at the first connection node, and the digital output signal is read at one of the first and second connection nodes; boosting means for boosting the voltage of at least one of the first and second control nodes beyond the low voltage level; and for at least one of the first and second control node to be boosted preloading means having a control input coupled to receive a voltage at the first connection node to bring back the boosted voltage on said control node down to the low voltage level.