Patent ID: 7164734

Claim:
A decision directed phase locked loop circuit, comprising: a phase detector which receives an input sequence of baseband complex samples in a burst data communication system and current phase estimates and generates phase differences between said baseband complex samples and current phase estimates; an inner block decoder which decodes said baseband complex samples to generate decoded data; a phase error generation circuit which receives said baseband complex samples and said decoded data from said inner block decoder and which generates feedback phase error terms based on said baseband complex samples and said partially decoded data, wherein said inner block decoder and phase error generation circuit are adapted to selectively apply excess processing power to a burst in said burst data communication system; a selection circuit which identifies a burst to be demodulated with excess processing power, said selection circuit providing said identified burst to said inner block decoder and said phase error generation circuit so as to selectively apply excess processing power in order to re-process said burst; an outer block decoder which receives the associated codewords generated by said inner block decoder and which utilizes and corrects only codewords associated with baseband complex samples after the group of baseband complex samples consisting of the first baseband complex samples received by said phase detector; a loop filter which filters said phase error terms; and a phase accumulator that updates the current phase estimate on each iteration of the phase locked loop.