Patent ID: 8171362

Claim:
An apparatus comprising: a processor; a memory including computer program code, where the memory and computer program code are configured, with the processor, to cause the apparatus to receive communications in a wireless communications network, wherein the communications comprise multi-block original signals and retransmission signals; where the processor is configured to decode an original signal; to determine whether the original signal was received correctly and when it is determined that only a portion of the original signal was received correctly to save blocks corresponding to the correctly-received portion in a first buffer as hard bits and to save remaining blocks corresponding to an incorrectly received portion in a second buffer; to receive a retransmission signal; to decode only that portion of the retransmission which corresponds to the incorrectly-received portion of the original signal and to discard a portion which corresponds to the previous correctly received portion; to determine whether blocks corresponding to the decoded, retained portion have been correctly received; for blocks that have been received correctly to place the correctly received blocks in the first buffer and for blocks that have been incorrectly received to place the incorrectly received blocks in the second buffer; to continue receiving and performing operations on retransmitted signals until all the blocks have been correctly received; and when all blocks have been correctly received, to pass the correctly received blocks to a higher layer.