Patent ID: 8482105

Claim:
A semiconductor substrate having a plurality of groove portions formed along scribe lines, comprising: a unit region in contact with at least any one of the plurality of groove portions; a wiring electrode with a portion thereof arranged within the unit region; and an insulating layer formed by filling the plurality of groove portions with a resin with no space, wherein the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof; the wide width portions are formed in the entire length direction of the inlet ports thereof; the insulating layer has a double-layer structure in which a lower insulating layer formed inside of the groove lower portion and an upper insulating layer formed inside of the wide width portion are laminated; and the lower insulating layer is formed using a low-viscosity resin lower in viscosity than the resin forming the upper insulating layer.