Patent ID: 8710928

Claim:
A semiconductor power amplifier comprising: a plurality of unit FETs which are disposed in parallel in a direction of a substantially straight line connecting source electrodes of the unit FETs, each of the unit FETs including a gate electrode which is connected to gate finger electrodes and leads out the gate finger electrodes in a longitudinal direction thereof, a drain electrode which is connected to drain finger electrodes disposed facing the gate finger electrodes and leads out the drain finger electrodes in a longitudinal direction thereof, and two source electrodes which are connected to source finger electrodes disposed facing the gate finger electrodes and lead out the source finger electrodes to opposing sides in a widthwise direction thereof; a first via hole which connects both of the two source electrodes positioned between adjacent ones of the unit FETs in common and an RF ground electrode; and a second via hole which is adjacent to only one source electrode and which connects the only one source electrode and the RF ground electrode.