Patent ID: 7057218

Claim:
A semiconductor structure formed on a substrate, comprising: a first interlayer; a first opening through the first interlayer exposing a portion of the substrate; a local interconnect formed in the first opening and in contact with the substrate; a first plurality of slots through the first interlayer; a corresponding plurality of bottom plate members formed in a respective slot of the first plurality; a dielectric layer formed on the plurality of bottom plate members; a second interlayer formed over the first interlayer; a second opening through the second interlayer exposing a portion of the local interconnect; a contact plug formed in the second opening and in contact with the local interconnect; a second plurality of slots through the second interlayer exposing portions of the dielectric layer, the second plurality of slots oriented substantially orthogonally with respect to the first plurality of slots; and a corresponding plurality of top plate members formed in a respective slot of the second plurality.