Patent ID: 7024618

Claim:
A processor, comprising: a source function circuit configured to: receive an operand as input, perform a first function on the received operand to generate results, generate source parity bits for the results, send the results to a destination function circuit via a first forwarding bus prior to or while generating the source parity bits for the results, and send the source parity bits to the destination function circuit via a second forwarding bus after sending the results to the destination function circuit via the first forwarding bus; and a destination function circuit configured to: receive the results from the source function circuit via the first forwarding bus, generate destination parity bits for the results, prior to or while generating the destination parity bits, receive the source parity bits from the source function circuit via the second forwarding bus, prior to or while the destination parity bits are being generated, perform a second function using the received results, and compare the source parity bits and the destination parity bits to generate transmission error signals.