Patent ID: 8558729

Claim:
A solid-state imaging apparatus comprising: a pixel unit in which a plurality of pixels each having a photoelectric conversion element are arranged in a matrix; a reference signal generation unit configured to generate a reference signal that increases or decreases with the passage of time; a comparison unit configured to start a process of comparing a pixel signal to the reference signal at a timing related to an input of the pixel signal and ending the comparison process at a timing when the reference signal has satisfied a predetermined condition for the pixel signal; a delay circuit including a plurality of delay elements each having a first pulse input terminal and a pulse output terminal, wherein the first pulse input terminal of each of the plurality of delay elements is connected to the pulse output terminal of a corresponding one of the plurality of delay elements and one of the plurality of delay elements has a second pulse input terminal to which an external pulse signal is input; a low-order latch circuit configured to latch pulse signals output from the plurality of delay elements; a high-order counter circuit configured to count a clock output from the delay circuit; a state variation detection circuit configured to sequentially compare pulse signals output from two delay elements of the plurality of delay elements among the pulse signals latched by the low-order latch circuit and outputting a state variation detection signal when states of the two pulse signals are different; and an encode signal latch circuit configured to latch an encode signal when the encode signal having a state corresponding to a delay element outputting a pulse signal input to the state variation detection circuit is input and the state variation detection signal is input, wherein the delay circuit receives a pulse signal input to the second pulse input terminal at a timing related to the start of the comparison process, the low-order latch circuit latches the pulse signals output from the plurality of delay elements at a timing related to the end of the comparison process, the high-order counter circuit starts a count operation at the timing related to the start of the comparison process and ends the count operation at the timing related to the end of the comparison process, and the comparison unit, the low-order latch circuit, the high-order counter circuit, the state variation detection circuit, and the encode signal latch circuit are arranged in every column or every plurality of columns of the pixel unit.