Patent ID: 7177197

Claim:
For a nonvolatile memory having an array of memory cells, each memory cell having a control gate and a channel defined between a source and a drain, the array of memory cells further organized into an array of NAND chains, each NAND chain comprising a plurality of memory cells daisy-chained by their sources and drains, forming a combined channel region between a source terminal and a drain terminal, a group of NAND chains formed by having a plurality of word lines each coupling to the control gates of corresponding memory cells of the NAND chains across a page, a method of programming in parallel the page of memory cells sharing a common word line among the group of NAND chains, comprising: (a1) for each NAND chain of the group, coupling an associated voltage source to each combined channel region to bring it to a program-enabling or program-inhibiting voltage depending on whether each NAND chain of the page is designated to be programmed or program-inhibited; (a2) floating the combined channel region of each said NAND chain of the group while allowing the program-enabling or program-inhibiting voltage to be held dynamically at the combined channel region; and (a3) programming the group of memory cells by applying programming voltages to the control gates thereof via the common word line of the group of NAND chains.