Patent ID: 8574980

Claim:
A method comprising: forming an N-type gate over a semiconductor substrate, the N-type gate having a first thickness; forming a P-type gate over the semiconductor substrate, the P-type gate having a second thickness different than the first thickness; forming spacers on sidewalls of the N-type gate having the first thickness and sidewalls of the P-type gate having the second thickness, the spacers being formed simultaneously; forming source and drain regions adjacent to the spacers, the source and drain regions containing no silicide layer; forming a conformal cover layer over the semiconductor substrate; removing the conformal cover layer over the N-type gate and the P-type gate; performing a simultaneous silicidation of the N-type gate and the P-type gate after the step of forming the source and drain regions containing no silicide layer, the source and drain regions containing no silicide layer being protected by the conformal cover layer from the simultaneous silicidation of the N-type gate and the P-type gate; removing remaining portions of the conformal cover layer; and performing a simultaneous silicidation of all the source and drain regions after the step of removing remaining portions of the conformal cover layer; wherein each of the forming the N-type gate and forming the P-type gate further comprises: forming a first polysilicon layer over the semiconductor substrate; forming an oxide layer over the first polysilicon layer; removing the oxide layer over the first polysilicon layer of the N-type gate; and forming a second polysilicon layer over the oxide layer.