Patent ID: 7697628

Claim:
An apparatus for transmitting data signals, comprising: a logic unit configured to generate an encoded signal in response to a clock signal and a first data signal; a demultiplexer configured to receive the encoded signal, the first data signal, and a second data signal from the logic unit, and to output odd-numbered data signals of the received signals at a first edge of the clock signal and even-numbered data signals of the received signals at a second edge of the clock signal; a data state elimination block configured to receive the encoded signal and the first and second data signals, and to invert a logic level of one of the received signals if logic levels of the encoded signal, the first data signal and the second data signal are the same; a plurality of buffers, a respective one of which is configured to buffer a corresponding signal received from the data state elimination block; a multiplexer including a plurality of input terminals; and a plurality of capacitors, a respective one of which is connected between an output terminal of a corresponding buffer of the plurality of buffers and a corresponding input terminal of the plurality of input terminals of the multiplexer, wherein the multiplexer is configured to output signals received from corresponding capacitors of the plurality of capacitors in response to the clock signal.