Patent ID: 7934046

Claim:
A method of routing a data request within a system-on-a-chip design, the method comprising: determining whether to allocate a cache register to one of a first master component and a second master component, wherein the cache register is communicatively coupled to the first master component and to the second master component, and wherein the cache register is operable to receive data requests from the first master component and from the second master component; allocating the cache register to the first master component, wherein, upon allocation of the cache register to the first master component, the cache register is operable to route a data request that is received from the first master component and is not operable to route data requests that are received from the second master component; receiving the data request from the first master component at the cache register, wherein the cache register includes a plurality of entries; matching the data request to a first entry of the plurality of entries in the cache register, wherein the first entry includes first routing information; and routing the data request from the cache register to one of a first slave segment component and a second slave segment component based at least in art on the first routine, information.