Patent ID: 7356624

Claim:
A circuit for interfacing between a first component operating at a first clock rate and a second component operating at a second clock rate wherein said second clock rate is higher than said first clock rate, said circuit comprising: a first buffer coupled to said first component, said first buffer receiving and storing data received from said first component at said first clock rate; a second buffer coupled to said second component, said second buffer supplying data recalled therefrom to said second component at said second clock rate; a copy/access controller connected to said first buffer, said second buffer, and said second component, said copy/access controller including a counter operable to count each time data is stored in said first buffer, a comparator having a first input receiving said count of said counter and a second input receiving a buffer size signal indicative of a size of said first buffer, said comparator operable when said count equals said buffer size to generate a load signal to copy data from said first buffer to said second buffer and to prompt said second component to access said second buffer.