Patent ID: 8850169

Claim:
A method comprising: fetching and issuing instructions of a plurality of instruction execution threads for execution by an execution block; receiving a disable instruction to disable a first instruction execution thread of the plurality of instruction execution threads, wherein the disable instruction to disable the first instruction execution thread is received from one of (i) the first instruction execution thread or (ii) a second instruction execution thread of the plurality of instruction execution threads; in response to the disable instruction to disable the first instruction execution thread being received from the second instruction execution thread, (i) fetching and issuing at least one instruction of the first instruction execution thread, and (ii) subsequent to fetching and issuing the at least one instruction of the first instruction execution thread, disabling the first instruction execution thread; and in response to the disable instruction to disable the first instruction execution thread being received from the first instruction execution thread, disabling the first instruction execution thread without fetching and issuing any instruction of the first instruction execution thread.