Patent ID: 7336523

Claim:
A memory device using a nanotube cell, comprising: a cell array block comprising a nanotube sub-cell array which has a hierarchical bit line structure including a main bit line and a sub-bit line and includes a plurality of unit nanotube cells arranged in row and column directions between a word line and the sub-bit line; and a sense amplifier array, connected to the cell array block through the main bit line, for sensing and amplifying data applied from the cell array block, wherein each of the plurality of unit nanotube cells comprises: a capacitor whose one terminal is connected to a word line; and a PNPN nanotube switch, which includes at least two or more PNPN diode devices successfully connected in series and divided into two groups each connected in parallel between the sub-bit line and the other terminal of the capacitor, for being selectively switched depending on voltage applied to the word line and the sub-bit line.