Patent ID: 6940317

Claim:
A semiconductor integrated circuit, comprising: first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range; third and fourth field-effect transistors which are controlled by the on/off states of the first and second field-effect transistors; a node which is a drain of the first field-effect transistor and at which an output signal varying within a second potential range wider than the first potential range is obtained; and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal, wherein gate nodes of the first and second field-effect transistors are not directly connected to gate nodes of the third and fourth field-effect transistors, and wherein said control circuit is an NMOS transistor that has a first node thereof coupled to the substrate-bias potential of the first field-effect transistor, and has a second node and a gate node thereof coupled to the incoming signal.