Patent ID: 7035161

Claim:
A semiconductor integrated circuit, comprising: a plurality of banks, each having a plurality of memory cells, and capable of writing and reading n bits of data (where n is a positive integer) to and from the plurality of memory cells; a plurality of input/output means, each capable of receiving a plurality of bits of data from an external circuit and outputting a plurality of bits of data to the external circuit; an n/2-bit data bus, extending along the plurality of banks; n bits of first data line pairs, each first data line pair being associated with each bank to transmit data between the associated bank and the data bus; n/2 bits of second data line pairs, each second data line pair being associated with each first data line pair and each input/output means to transmit data between the data bus and the associated input/output means; and, a plurality of switching means for connecting one of the banks with a predetermined one of the input/output means via the associated first data line pair and associated second data line pair, and with other input/output means via the other associated first data line pairs, the n/2 bit data bus and other second data line pair based on a control signal.