Patent ID: 7161827

Claim:
A method of operating a SRAM memory including an SRAM memory cell, the memory cell includes a first storage node, a second storage node, and a cross coupled latch including a first primary source current path to the first storage node, a first primary sink current path to the first storage node, a second primary source current path to the second storage node, a second primary sink current path to the second storage node, a fifth primary current path to the first storage node, and a sixth primary current path to the second storage node, the method comprising: reading the memory cell; and writing to the memory cell, wherein during the writing to the memory cell, the fifth primary current path includes a first transistor and the sixth primary current path includes a second transistor, wherein one of the first transistor and the second transistor is conductive during a read of the memory cell and the first transistor and the second transistor are non-conductive during a write to the memory cell.