Patent ID: 8390489

Claim:
A background calibration method for calibrating a pipelined Analog-to-Digital Converter (ADC), the pipelined ADC having at least a first capacitor C 1 and a second capacitor C 2 , the method comprising: measuring a mismatch between C 1 and C 2 to determine a capacitor mismatch value that represents the mismatch, by passing a precalibration digital output D out of the pipelined ADC through a capacitor mismatch information extraction path in a background correlation loop and performing commutated feedback capacitor switching (CFCS) in the background correlation loop; and using the measured capacitor mismatch value to determine an error in D out that is caused by the capacitor mismatch, and calibrating out the error by subtracting the error from D out , in a digital calibration path within the background correlation loop.