Patent ID: 7123064

Claim:
A phase shift circuit for creating a second clock signal using a first clock signal, the phase shift circuit comprising: a phase detector suitable for coupling to the first and second clock signals, the phase detector configured to produce an output corresponding to a phase relationship between the first and second clock signals; a processor coupled to the phase detector and to a delay module, the processor configured to select, based at least partially on the output of the phase detector, a value corresponding to a given one of a plurality of delays, the processor further configured to communicate the value to the delay module; and the delay module coupled to the first clock signal and to the processor, the delay module configured to create, by using the value, the given delay on the first clock signal to produce the second clock signal; whereby the given delay creates a phase shift between the first and second clock signals; wherein the delay module comprises a plurality of configurable delay elements, wherein: a first of the delay elements is configured to provide one of a plurality of coarse delays; and a second of the delay elements is configured to provide one of a plurality of fine delays; a smallest of the coarse delays is larger than a smallest of the fine delays; and the first of the delay elements corresponds to a first portion of the value and the second of the delay elements corresponds to a second portion of the value.