Patent ID: 6919899

Claim:
An uninterrupted data display method for a computer system having a system memory directly accessed by a processor, for preventing disrupted data display from transmission break, before the processor goes into a non-responding period due to an execution of an economical process, said method comprising the steps of: a. comparing said non-responding period to a horizontal synchronization pulse width, if said non-responding period is shorter than said horizontal synchronization pulse width, jump to step b, otherwise, to step c; b. detecting said horizontal synchronization pulse or a vertical synchronization pulse, whichever comes first, then jump to step d which is being executed within a horizontal blank period when said horizontal synchronization pulse is detected first, otherwise, a vertical blank period is used for step d if said vertical synchronization pulse is detected prior to said horizontal synchronization pulse; c. detecting only said vertical synchronization pulse, then jump to step d, and said vertical blank period is used for step d once said vertical synchronization pulse is detected; and d. executing said economical process.