Patent ID: 7370184

Claim:
An apparatus comprising: a shift post processor; a shifter to shift an operand according to an offset parameter, generating a shifted operand; and a register coupled to the shift post processor capable of transferring a shift carry operand stored in the register to the shift post processor, and coupled to the shifter to store the shifted operand after any transfer of the shift carry operand; wherein the shift post processor is coupled to the shifter and the register to process the shifted operand to generate an output based on at least a control signal and a mask field; and wherein the shift post processor comprises a decoder to decode the offset parameter into the mask field, the mask field having a plurality of mask bits, each of the mask bits corresponding to a bit position of the shifted operand, and at least one bit formatter coupled to the decoder to format the shifted operand using the control signal and the mask field, the at least one bit formatter comprising (i) a gating circuit to gate the control signal using the mask bit, and (ii) a selector circuit coupled to the gating circuit to select one of a bit at the bit position of the shifted operand, the shift carry operand, and a most significant bit of the operand based on the gated control signal.