Patent ID: 7910978

Claim:
A method for the formation of a memory device integrated on a semiconductor substrate and comprising at least one nanocrystal memory and CMOS transistors, the method comprising: a first step suitable for forming, above said substrate, a first dielectric layer; a second step suitable for forming, above said first dielectric layer, a nanocrystal layer comprising a plurality of nanocrystals; a third step suitable for forming, above said nanocrystal layer, a second dielectric layer; a fourth masking and etching step suitable for removing said second dielectric layer, said nanocrystal layer and said first dielectric layer to define on said substrate a nanocrystal memory area and a circuitry area; and a fifth oxidizing step suitable to form on said circuitry area at least one gate oxide for at least one of said CMOS transistors; and wherein said third step comprises at least one controlled deposition step suitable for defining at least one nitride layer having an initial thickness, said initial thickness being such as to allow a complete transformation of said nitride layer into an oxide layer at the end of said fifth oxidizing step to form said second dielectric layer.