Patent ID: 8017472

Claim:
A method of fabricating a semiconductor device, the method comprising: forming at least one isolation region within a workpiece, the at least one isolation region comprising: a stress-altering material layer comprising a first stress-altering material and a second stress-altering material in contact with a trench within the workpiece so as to at least partially line, but not fill the trench, wherein a bottom surface of the trench comprises a first semiconductor material, and wherein the stress-altering material layer comprises a second semiconductor material different from the first semiconductor material, and wherein the second stress-altering material comprises a third semiconductor material different than the second semiconductor material, a layer of semiconductor material lining the stress-altering material layer, the layer of semiconductor material disposed over the stress-altering material layer, and an insulating material disposed over the layer of semiconductor material; forming a first active region proximate a first side of the at least one isolation region, the first stress-altering material lining the trench proximate the first active region; and forming a second active region proximate a second side of the at least one isolation region, the second stress-altering material lining the trench proximate the second active region, wherein the first stress-altering material is disposed proximate the first active region, but not proximate the second active region.