Patent ID: 6919637

Claim:
An interconnect structure for integrated circuit, comprising: a first plurality of spaced-apart, parallel conductors disposed at a first level above a substrate; a second plurality of spaced-apart, parallel conductors disposed at a second level above a substrate, the second conductors being disposed above the first conductors generally perpendicular to the first conductors, a projection of the second conductors on the first conductors defining a plurality of intersections; a plurality of vias providing a conductive path between selected ones of the first and second conductors at some of the intersections; a plurality of dielectric pillars formed entirely of dielectric extending between selected ones of the first and second conductors at other of the intersections for providing support for the second conductors from the first conductors; wherein each of the intersections of first conductors and second conductors includes either one of the vias or one of the pillars.