Patent ID: 7049194

Claim:
A method of forming a trench DMOS transistor device comprising: providing a substrate of a first conductivity type, said substrate acting as a common drain region for said device; depositing an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower majority carrier concentration than said substrate; forming a body region of a second conductivity type within an upper portion of said epitaxial layer; etching a trench extending into said epitaxial layer from an upper surface of said epitaxial layer; forming an insulating layer lining at least a portion of said trench; forming a low resistivity deep region of said first conductivity type below a portion of said trench previously formed, the deep region extending from an upper surface of the epitaxial layer into the substrate, said deep region acting to provide electrical contact with said substrate; forming a conductive region within said trench adjacent said insulating layer; and forming a region of said first conductivity type within an upper portion of said epitaxial layer over the deep region, wherein the region within the upper portion of said epitaxial layer completely overlies the deep region.