Patent ID: 8166266

Claim:
A system for controlling data operations access to a plurality of non-Flash embedded re-writable non-volatile vertically stacked memory layers in one or more memory devices, comprising: a silicon semiconductor substrate including active circuitry fabricated on a logic plane of the silicon semiconductor substrate; a plurality of vertically stacked memory layers that are in contact with one another and vertically fabricated in contact with and directly above the silicon semiconductor substrate, at least one of the memory layers in the plurality of vertically stacked memory layers is configured as an obfuscation layer operative to obstruct physical access to one or more memory layers positioned below the obfuscation layer; at least one two-terminal cross-point memory array embedded in each memory layer, each memory array including a plurality of conductive array lines that are electrically coupled with at least a portion of the active circuitry; a plurality of re-writeable non-volatile two-terminal memory elements operative to retain stored data in the absence of electrical power, each memory element positioned between a cross-point of a unique pair of the plurality of conductive array lines in its respective memory array; a device access determinator including determination logic configured to enable or disable data operations access to one or more of the plurality of vertically stacked memory layers in response to a signal; and a memory storage controller in electrical communication with the device access determinator and configured to control data operations access to one or more of the memory arrays, the memory storage controller including an obfuscation layer manager circuit in electrical communication with the obfuscation layer and configured to perform data operations on the obfuscation layer, wherein data operations to the one or more memory layers positioned below the obfuscation layer are enabled by the device access determinator only if a data operation is successfully performed on the obfuscation layer by the obfuscation layer manager circuit, and wherein the device access determinator, the memory storage controller, and the obfuscation layer manager circuit are included in the active circuitry.