Patent ID: 8817914

Claim:
A receiver circuit, comprising: a receiving stage coupled to a first supply voltage and an input signal, operative to generate a first intermediate signal from the input signal based on the first supply voltage; a compensation stage coupled to a second supply voltage and the first intermediate signal, operative to generate a second intermediate signal by adjusting duty cycle of the first intermediate signal upon detecting changes in the first supply voltage to compensate for the changes in the first supply voltage; and an outputting stage coupled to the second supply voltage and operative to generate an output signal based on the second supply voltage upon receiving the second intermediate signal, wherein a voltage of the output signal is adjusted to a level of the second supply voltage and the output signal has a 50% duty cycle, wherein the compensation stage comprises: a detection circuit, operative to generate a plurality of control signals upon detecting the change in the first supply voltage, wherein contents of the plurality of control signals reflect an amount of change in the first supply voltage; and a duty cycle adjusting circuit, operative to generate the second intermediate signal according to the first intermediate signal and the plurality of control signals upon receiving the first intermediate signal and the plurality of control signals and, wherein the second intermediate signal has a 50% duty cycle, wherein the detection circuit comprises: an increment detection circuit, operative to generate a plurality of first control signals as a portion of the plurality of control signals upon detecting increment in the first supply voltage; and a decrement detection circuit, operative to generate a plurality of second control signals as a portion of the plurality of control signals upon detecting decrement in the first supply voltage, wherein the increment/decrement detection circuit comprises: an analog to digital converter (ADC), coupled to the first supply voltage and operative to generate a plurality of digital signals by mapping a voltage level of the first supply voltage to the plurality of digital signals, wherein the ADC comprises: a voltage divider, operative to generate a plurality of comparing voltages by dividing the first supply voltage into the plurality of comparing voltages; and a plurality of comparators, each receiving a reference voltage and one of the plurality of comparing voltages and operative to generate one of the plurality of digital signals by comparing the reference voltage with the one of the plurality of comparing voltages.