Patent ID: 7149956

Claim:
A gray-code error corrector comprising: an input for receiving input gray-code words in a received sequence, the input gray-code words belonging to a full sequence of gray-code values, wherein successive gray-code values in the full sequence have only one bit difference, wherein the received sequence contains successively-received words that differ by a maximum of N bits, wherein N is a whole number of two or more, wherein the successively-received words differ in value by a maximum of 2 N −1, a received register, coupled to receive an input gray-code word received by the input, the received register having an upper received-register that stores upper received bits and a lower received-register that stores N lower received bits of the input gray-code word; a stored register that stores a corrected gray-code word, the stored register having an upper stored-register that stores upper stored bits and a lower stored-register that stores N lower stored bits of the corrected gray-code word; an upper comparator, coupled to the received register and to the stored register, for comparing the upper received bits to the upper stored bits; an upper loader, activated by the upper comparator when the upper received bits and the upper stored bits mis-match, for copying the upper received bits into the upper stored-register; a low-bit generator that generates lower stored bits for loading into the lower stored-register such that the stored register has a lowest-possible value within the full sequence of gray-code values after loading; and a full comparator, coupled to the received register and to the stored register, activated when the upper comparator determines that the upper received bits match the upper stored bits to compare the input gray-code word to the corrected gray-code word.