Patent ID: 8073987

Claim:
A peripheral apparatus, comprising: a storage unit that stores protocol identification information; a communication unit connected to a host apparatus for carrying out communication according to a specific protocol identified by the protocol identification information; and a configuration space that includes at least one configuration register, a first area, and a second area, the first area having first address information used for accessing the second area, the second area having a data register and an address register, wherein second address information used for accessing at least a part of the protocol identification information stored in the storage unit is set within the address register, an indication that respective parts of the protocol identification information are to be successively accessed, one part after another, according to the second address information is set within the data register, and the host apparatus and said peripheral apparatus are communicably connected via a PCI Express bus, said PCI Express bus is furnished with said configuration space which serves as an address space and which accommodates a plurality of such configuration registers, said configuration space includes a plurality of areas, one of said plurality of areas being a configuration space header, another of said plurality of areas constituting a vital product data capability structure, and an address register and a data register are accommodated in the area of said vital product data capability structure.