Patent ID: 8411853

Claim:
An apparatus comprising: a first circuit configured to (i) generate a second plurality of Galois Field elements by performing a first Galois Field inversion on a first plurality of Galois Field elements, said first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate a third plurality of Galois Field elements by multiplying said second Galois Field elements by an inverse of a first predetermined matrix; and a second circuit configured to (i) generate a fourth plurality of Galois Field elements by processing said third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate a fifth plurality of Galois Field elements by multiplying said fourth Galois Field elements by said first predetermined matrix and (iii) present said fifth Galois Field elements as updated versions of said first Galois Field elements in advance of a next encryption round.