Patent ID: 8369177

Claim:
An apparatus comprising: a first memory cell array comprising a first plurality of memory cells arranged in a matrix of rows and columns; a second memory cell array comprising a second plurality of memory cells arranged in a matrix of row and columns; a data sense amplifier latch circuitry comprising a first input node and a second input node; a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry; a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry; a precharge circuitry coupled to the first input node and the second input node for precharging the first input node and the second input node to a first pre-charged voltage level and a second pre-charged voltage level; and a keeper circuitry coupled to the first bit line input circuitry and the second bit line input circuitry for maintaining the first pre-charged voltage level at the first input node and the second pre-charged voltage level at the second input node, respectively.