Patent ID: 7384852

Claim:
A method of fabricating a semiconductor structure having a sub-lithographic channel length comprising: providing a structure including a patterned hard mask located above a sacrificial layer and a semiconductor substrate, wherein said patterned hard mask includes at least one lithographically defined opening exposing a surface of said sacrificial layer; providing a block copolymer having a single unit polymer block with a sub-lithographic width inside the at least one lithographically defined opening, wherein the single unit polymer block comprises a second polymeric block component which is embedded in a polymeric matrix that comprises a first polymeric block component of said block copolymer; selectively removing the second polymeric block component relative to the first polymeric block component to form a sub-lithographic opening in the polymeric matrix inside the at least one lithographically defined opening; transferring said sub-lithographic opening to said sacrificial layer; removing the block copolymer and the patterned hard mask; forming a gate dielectric and a gate conductor within said at least one lithographical defined opening; and removing the sacrificial layer.