Patent ID: 7471590

Claim:
A write control method for a memory array configured with multiple memory subarrays, the method comprising: multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to one associated memory subarray of the multiple memory subarrays, wherein the selectively enabling comprises outputting a write enable signal to the associated memory subarray, and wherein the multiple subarray write controllers are powered via a common switched power node and are connected between the common switched power node and ground, and wherein the common switched power node is driven by multiple drivers distributively implemented among the multiple subarray write controllers associated with the multiple memory subarrays; and gating each subarray write controller with a different subarray select signal of a plurality of subarray select signals, wherein only one select signal is active at a time, resulting in only one write enable signal being output from one subarray write controller to its associated memory subarray at a time.