Patent ID: 7537966

Claim:
A method for fabricating a board on chip semiconductor package comprising: providing a semiconductor die comprising a circuit side, a plurality of die contacts on the circuit side, an insulating layer on the circuit side, a plurality of planarized wire bonding contacts comprising wire bondable metal bumps having planar wire bonding surfaces bonded to the die contacts, and a planarized polymer layer on the circuit side completely covering the circuit side and encapsulating the planarized wire bonding contacts with the planarized wire bonding surfaces exposed; providing a substrate comprising a first surface, a second surface, a plurality of conductors on the first surface comprising a plurality of first bonding pads and a plurality of second bonding pads and an opening from the first surface to the second surface; attaching the circuit side of the die to the second surface of the substrate; bonding wires through the opening to the planarized wire bonding contacts and to the first bonding pads; encapsulating the die in a plastic material comprising at least one filler with the planarized polymer layer preventing physical contact between the plastic material and the circuit side of the die and stress defects on the die caused by the filler; and forming a plurality of terminal contacts on the second bonding pads.