Patent ID: 7670938

Claim:
A method, comprising: forming a feature above a semiconducting substrate; forming a plurality of stress-inducing layers above said substrate and said feature such that the stress-inducing layers overlap above said feature to form a layer stack above said feature, said layer stack having an original height that comprises at least a first overlapping portion and a second overlapping portion, each of the stress-inducing layers having a portion formed over said substrate for inducing a stress condition in said substrate; reducing said original height of said layer stack to thereby define a reduced height layer stack that comprises the first overlapping portion of the stress-inducing layers that overlap above said feature, wherein reducing said original height of said layer stack comprises removing the second overlapping portion of at least one of the stress-inducing layers in the layer stack while retaining the portions of the stress-inducing layers formed over said substrate in regions adjacent said feature; forming an opening in said reduced height layer stack for a conductive member that will be electrically coupled to said feature; and forming said conductive member in said opening in said reduced height layer stack.