Patent ID: 8334190

Claim:
A single step method for planarization of a wafer having a semiconductor surface including a multilayer film stack thereon comprising a silicon nitride (SiNx) layer on said semiconductor surface, and a silicon oxide layer on said SiNx layer, wherein trench access vias extend through said silicon oxide layer and said SiNx layer to trenches formed into said semiconductor surface, and wherein a polysilicon layer that fills said trench access vias and said trenches is on said silicon oxide layer, comprising: chemical mechanical polishing (CMP) said multilayer film stack with a slurry including slurry particles comprising at least one of silica particles and ceria particles, wherein said CMP provides a removal rate (RR) for said polysilicon layer is greater than a RR for said silicon oxide layer is greater than a RR for said SiNx layer, and wherein said CMP removes said polysilicon layer, said silicon oxide layer and a portion of said SiNx layer and stops on said SiNx layer.