Patent ID: 6937247

Claim:
A memory control device for controlling a memory unit, wherein the memory unit includes at least a memory bank and the memory bank includes graphic memory, the control device comprising: a command decoding device for receiving a memory access command and a bank address range signal, wherein the memory access command includes an access address and a command code, the command decoding device determines the memory bank range of the access address according to a bank address range signal and outputs a memory bank number signal, and the command decoding device outputs a partial write signal according to the command code; a compare logic device coupled to the command decoding device, wherein the compare logic device determines if the access address falls within a memory bank range with error-check-correction function according to the memory bank number signal and an error-check-correction bank number signal and outputs an error-check-correction bank signal; a frame buffer decode device for receiving the memory access command and a frame buffer range signal and determining if the access address falls within the graphic memory range and outputting a frame buffer access signal; a decision device coupled to the command decoding device, the compare logic device and the frame buffer decode device for outputting an error-check-correction calibration enable signal and a read-modify-write enable signal according to the partial write signal, the error-check-correction bank signal and the frame buffer access signal; and a command routing device coupled to the decision device for actually performing reading, modifying, and writing in sequence on the memory unit, according to the read-modify-write enable signal; wherein when the access address falls within a memory bank range with error-check-correction function and also within the graphic memory range, and the command code is a partial write command, then data read from the memory is not executed with error-check-correction function.