Patent ID: 8248127

Claim:
A Digital Phase-Locked Loop (DPLL) comprising: a reference clock input receiving a reference clock having a reference frequency; a digitally-controlled oscillator (DCO) that generates an output clock having an output frequency that is determined by a digital oscillator input, the digital oscillator input having most-significant-bits (MSBs) and a least-significant-bit (LSB); a feedback divider that divides the output clock by M to generate a feedback clock, wherein the output frequency is M times the reference frequency when the feedback clock is phase locked to the reference clock, wherein M is a whole number; a control divider that divides the output clock by C to generate a control clock, wherein the output frequency is C times a control frequency of the control clock, and wherein the control frequency is C/M times the reference frequency when the feedback clock is phase locked to the reference clock, wherein C and M/C are each whole numbers; a Time-to-Digital Converter (TDC) that receives the reference clock and the feedback clock, the TDC performing phase comparisons of the feedback clock to the reference clock using a coarse time resolution to generate a coarse phase compare signal and using a fine time resolution to generate a fine phase compare signal, wherein the fine time resolution represents a smaller amount of time than the coarse time resolution; a coarse digital loop filter that receives the coarse time resolution from the TDC and generates the MSBs to the DCO; a fine digital loop filter that receives the fine time resolution from the TDC and generates a fine loop filter value; and a Pulse-Width-Modulation (PWM) controller that generates M/C LSB bits for each period of the reference clock, the M/C LSB bits forming a pulse that has a pulse-width determined by the fine loop filter value from the fine digital loop filter, the PWM controller delivering one of the M/C LSB bits to the digital oscillator input of the DCO in response to each period of the control clock; wherein the PWM controller further comprises: a parallel-to-serial shift register that is loaded in parallel with the M/C LSB bits for each period of the reference clock, the parallel-to-serial shift register serially delivering the M/C LSB bits to the LSB of the digital oscillator input of the DCO in response to the control clock, wherein a different one of the M/C LSB bits is delivered for each period of the control clock, whereby the PWM controller generates LSB's to the digitally-controlled oscillator by modulating the pulse-width in response to the fine loop filter value.