Patent ID: 7745324

Claim:
A method of forming an interconnect structure, comprising: depositing a first dielectric layer of ultra low-k material; forming a sacrificial dielectric layer over said first dielectric layer; forming an interconnect feature in said sacrificial dielectric layer and first dielectric layer by: etching an opening in said sacrificial dielectric layer and first dielectric layer; depositing a liner over said sacrificial dielectric layer and within said opening; overfilling said opening with a conductive material; and, performing a chemical mechanical polishing process to remove a portion of said conductive material, a portion of said liner, and said sacrificial dielectric layer such that top surface of said conductive material filled opening is coplanar with said first dielectric layer; depositing a noble metal layer on top of said interconnect feature; annealing said interconnect feature such that an alloy layer forms in said conductive material adjacent said noble metal layer; removing said noble metal layer and a portion of said first dielectric layer using a gas cluster ion beam, leaving a portion of said liner and said alloy layer protruding from said first dielectric layer; and, depositing a second dielectric layer over said first dielectric layer and said protruding liner and alloy layer.