Patent ID: 7180180

Claim:
A stacked microelectronic device, comprising: a first substrate of silicon, said first substrate having a top surface; a first plurality of interconnect structures formed on at least a portion of the first substrate wherein at least one of said interconnect structures is vertically protruding with a flat horizontal surface at the apex of said structure's projection; a layer of nonconductive compliant material formed on at least a portion of the top surface of the first substrate of silicon, at least a portion of the layer of nonconductive compliant material having a top surface lower than a top surface of at least one of said first plurality of interconnect structures; and a second substrate of silicon with a second plurality of interconnect structures formed thereon wherein at least one of said second substrate's interconnect structures is vertically protruding with a flat horizontal surface at the apex of said structure's projection, said first and second substrates configured such that at least a portion of the interconnect structures of said first and second substrates respectively are in physical contact wherein at least one of said first substrate's interconnect structures' flat horizontal surface contacts at least one of said second substrate's interconnect structures' flat horizontal surface and the body of the said first substrate interconnect structure is in vertical alignment with the body of the said second substrate interconnect structure.