Patent ID: 7606368

Claim:
A block cipher hardware device for encrypting and decrypting information in a cryptographically secured digital communication system comprising: a key scheduler unit that is computationally a function of a key data block comprising: a first function unit that is computationally a function of a first portion of the key data block for producing a first key data sub-block; a second function unit that is computationally a function of a second portion of the key data block for producing a second key data sub-block; and an encryption stage that is computationally a function of the first and second key data sub-blocks where the encryption stage will not encrypt data if the first portion of the key data block is equal to the second portion of the key data block, and the first function unit is equal to the second function unit; and if the first portion of the key data block is not equal to the second portion of the key data block, and the first function unit is not equal to the second function unit, then the encryption stage will encrypt the data.