Patent ID: 7157951

Claim:
A delay structure for a clock generator generating a plurality of clock outputs, said delay structure comprising: a plurality of delay elements coupled in series for receiving a clock signal, each delay element comprising: a tap delay adapted to introduce a first delay to the clock signal, thereby creating a first delayed clock signal; a first buffer adapted to introduce a second delay to the first delayed clock signal, thereby creating a second delayed clock signal; a set of one or more clock lines coupled to receive the second delayed clock signal from the first buffer; and a trim unit coupled to the set of one or more clock lines, wherein the trim unit couples a capacitance to the set of one or more clock lines in response to control signals, thereby introducing a third delay to the second delayed clock signal and creating a third delayed clock signal, wherein the plurality of delay elements generates a plurality of output signals, each output signal being dependent upon a delay introduced by a trim unit of the delay element generating the output signal; a phase detector coupled to compare the output signals of at least two delay elements of the plurality of delay elements, the phase detector providing an error signal representative of a difference between the phases of the output signals of the at least two delay elements; an output generator coupled to receive the third delayed clock signal from each trim unit of the plurality of delay elements and provide an output clock signal of the delay structure; and a control circuit adapted to provide the control signals to the trim units of the plurality of delay elements and to provide output control signals to the output generator, the control signals provided to the trim units being based upon the error signal representative of the difference between the phases of the output signals of the at least two delay elements received from the phase detector.