Patent ID: 7343570

Claim:
A method of improving manufacturability of an integrated circuit on a semiconductor substrate using an unmodified plurality of cells, the method comprising: arranging the unmodified plurality of cells, wherein arranging the unmodified plurality of cells comprises arranging a hierarchical cell comprising a base cell and a modifiable cell, the base cell comprising configurable and non-configurable elements, the modifiable cell comprising a design-for-manufacturing programmable overlay template; defining routes of interconnecting conductive paths between the unmodified plurality of cells based on operation of the integrated circuit; evaluating the arrangement of the unmodified plurality of cells and the routes of the interconnecting conductive paths between the unmodified plurality of cells for a manufacturing improvement opportunity; and modifying at least one of the unmodified plurality of cells based on the manufacturing improvement opportunity to create a modified plurality of cells, wherein the modified plurality of cells are to be used to create the integrated circuit on the semiconductor substrate.