Patent ID: 8154025

Claim:
An integrated circuit on a semiconductor substrate, the integrated circuit comprising: at least one Schottky barrier NMOS device comprising: a first metal type source extension and drain extension; a second metal type source electrode and drain electrode, wherein the second metal type source electrode and drain electrode extend deeper into the semiconductor substrate than the first metal type source extension and drain extension; a first channel region that extends between the first metal type source extension and drain extension; a first type gate electrode; and a sidewall spacer, wherein the first metal type source extension and drain extension extend at least partially below the sidewall spacer; and at least one Schottky barrier PMOS device comprising: a third metal type source extension and drain extension; a fourth metal type source electrode and drain electrode, wherein the fourth metal type source electrode and drain electrode extend deeper into the semiconductor substrate than the third metal type source extension and drain extension; a second channel region that extends between the third metal type source extension and drain extension; a second type gate electrode; and a sidewall spacer, wherein the third metal type source extension and drain extension extend at least partially below the sidewall spacer.