Patent ID: 7262096

Claim:
A manufacturing method of a NAND flash memory cell row, comprising: forming a plurality of doping regions and a plurality of source/drain regions in a substrate, wherein the source/drain regions are disposed at outer sides of the doping regions; forming a plurality of stacked gate structures on the substrate, wherein some of the stacked gate structures are disposed on the doping regions and each of the stacked gate structures comprises at least an erase gate, and some of the stacked gate structures are disposed at a distance from the doping regions and beside the source/drain regions and each of the stacked gate structures comprises at least a select gate; forming a tunnel oxide layer on the substrate to cover the substrate, the erase gate and the select gate surface; forming a plurality of floating gates between the stacked gate structures, wherein a top surface of the floating gates is a concave surface and has a sharp edge, wherein an edge of the concave surface is lower than a top surface of the erase gates; forming an inter-gate dielectric layer on the floating gates; and forming a plurality of control gates on the inter-gate dielectric layer.