Patent ID: 6861874

Claim:
A feedback control I/O buffer driven by a system voltage, comprising: an input/output circuit comprising a first PMOS transistor and a first NMOS transistor and having an I/O port coupled to an I/O pad, wherein the first PMOS transistor has an N-well region, a gate of the first NMOS transistor receives a first gate control signal, and a drain of the first PMOS transistor serves as the I/O port; a P-gate control circuit receiving a second gate control signal and being output to the gate of the first PMOS transistor, wherein the P-gate control circuit comprises: a transmission gate having a second NMOS transistor and a second PMOS transistor, the sources of which are coupled to the second gate control signal, and the gates of which are coupled to the system voltage and the N-well control circuit respectively; and a third PMOS transistor having a drain and a source coupled to the gate and the floating N-well region of the first PMOS transistor respectively, and a gate coupled to the system voltage; and an N-well control circuit coupled to the I/O pad to control the voltage level at the N-well region of the first PMOS transistor according to a feedback signal output from an inverter, wherein the N-well control circuit comprises: a fourth PMOS transistor having a source coupled to the I/O pad, a gate coupled to the system voltage, and a drain coupled to the N-well region of the first PMOS transistor; a fifth PMOS transistor having a gate coupled to the system voltage, a source coupled to the I/O pad, and a drain; a sixth PMOS transistor having a gate coupled to the drain of the fifth PMOS transistor, a drain coupled to the system voltage, and a source coupled to the N-well region of the first PMOS transistor; and a third NMOS transistor having a source and drain coupled to the I/O pad and the gate of the sixth PMOS transistor, and a gate coupled to the system voltage.