Patent ID: 7408806

Claim:
A memory array comprising: a memory cell region including a plurality of unit memory cells arranged in a matrix configuration on a substrate, each of the unit memory cells including a first memory cell and a second memory cell separated by a non-charge trapping layer, each of the first and second memory cells including a memory layer and a gate, wherein predetermined numbers of the memory cells in a first direction are connected to form a plurality of memory strings, each memory string having a first end memory cell and a second end memory cell, and wherein the gates of the memory cells form a word line in a second direction; a plurality of first selection transistors and a plurality of second selection transistors alternately connected to the first end memory cell and second end memory cell each of the plurality of memory strings such that the first end memory cell of a particular memory string is connected to a different type of selection transistor than the second end memory cell of the particular memory string, wherein gates of the first and second selection transistors connected to the first end memory cells of the memory strings form a first selection line in the second direction, and gates of the first and second selection transistors connected to the second end memory cells form a second selection line in the second direction; and a plurality of bit lines connected to the first and second selection transistors of adjacent memory strings, wherein a first bit line is connected to the first and second selection transistors connected to the first end memory cells of adjacent first and second memory strings and a second bit line adjacent to the first bit line is connected to the first and second selection transistors connected to the second end memory cells of adjacent second and third memory strings.