Patent ID: 7003059

Claim:
A write controller for controlling memory storage operation of an Elastic Buffer, comprising: a comparator mechanism which detects if link data from a source contains an IDLE signal; a Jabber counter mechanism which counts each cycle of a link clock in which an IDLE signal is not detected, and resets said count each time said IDLE signal is detected, and which asserts a DISABLE signal for a single link clock cycle if said count reaches a programmed time-out value; and a logic gate which logically combines outputs from said comparator mechanism and said Jabber counter mechanism to generate a Write control signal for prohibiting a corresponding link data sequence from being stored in said memory storage of said Elastic Buffer so as to prevent data overflow in said memory storage; wherein said memory storage corresponds to one of a first-in, first-out (FIFO) register and a succession of D-type flip-flops having an elasticity required to synchronize said link data to a receiver clock subsequently used to retrieve said link data from said memory storage as receiver data; and wherein said memory storage comprises a plurality of addressable memory locations determined by the potential differences in frequencies of the link clock and the receiver clock, and non-IDLE characters included in said link data.