Patent ID: 7915917

Claim:
An integrated circuit having at least a first logic cell and a second logic cell, the first logic cell ( 800 , 900 ) comprising: a LUT ( 802 , 902 ) having a LUT output terminal, a circuit ( 803 , 905 ) having a first circuit input terminal and a second circuit input terminal, and a first input terminal (lutin); wherein the LUT output terminal of the LUT is connected to the first circuit input terminal and the first input terminal is connected to the second circuit input terminal; the second logic cell ( 800 , 900 ) comprising: a LUT ( 802 , 902 ) having a LUT output terminal, and a first output terminal (lutout), the first output terminal is connected to the LUT output terminal; the first output terminal of the second logic cell is connected to the first input terminal of the first logic cell, thereby a buddy logic is formed; and a third logic cell ( 1210 ), said third logic cell comprising a first output terminal (dlutout) and a LUT having a LUT output terminal; within the third logic cell, said LUT output terminal is connected to the first output terminal; the first logic cell ( 1220 ) has a second input terminal (ulutin), the circuit has a third circuit input terminal, which is connected to the second input terminal of the first logic cell; the second input terminal of the first logic cell is connected to the first output terminal of the third logic cell.