Patent ID: 7833837

Claim:
A method for manufacturing chip scale packages at the wafer-level, the method comprising steps of: providing a tape circuit including a plurality of contact pads on a lower surface of a tape; providing a wafer including a plurality of semiconductor chips wherein each semiconductor chip has a plurality of bonding pads on an active surface thereof; forming an anisotropic conductive adhesive layer onto the active surface of the wafer; attaching the tape circuit onto the wafer through the anisotropic conductive adhesive layer to form a tape-circuit/wafer assembly such that the contact pads are electrically coupled to the corresponding bonding pads on the semiconductor chip; removing the tape from the tape-circuit/wafer assembly and exposing the contact pads; forming an insulating layer above the anisotropic conductive adhesive layer and over the tape-circuit/wafer assembly; patterning the insulating layer to form a plurality of openings at locations corresponding to the contact pads after the tape being removed; forming a plurality of metal bumps in the openings of the insulating layer and mounted to the contact pads; and conducting a cutting step to obtain individual chip scale packages.