Patent ID: 8198923

Claim:
A harmonic suppression circuit comprising: a source voltage; two suppression modules being connected in parallel to the source voltage, and each suppression module comprising an input transistor having a drain being connected to the source voltage; a source; and a gate; and two harmonic suppression modules being mounted in series respectively with the input transistors, and each harmonic suppression module comprising two smoothing transistors in each harmonic suppression module being mounted in parallel, and each smoothing transistor having a drain, the drains being connected respectively to the sources of the input transistors; a gate; and a source; and a resistor being mounted between the gates of the smoothing transistors and having two ends, the end of the resistor connected to the smoothing transistor connected to the opposite suppression module being connected to the drain of the parallel transistor; two input terminals being connected respectively to the gates of the input transistors; two smoothed output terminals being connected respectively to the sources of the input transistors; and a ground being connected to the sources of the smoothing transistors.