Patent ID: 7951707

Claim:
An etching method for a semiconductor element, the etching method comprising: (a) providing a to-be-etched substrate comprising an insulating portion and a conductive portion, the insulating portion being positioned on the conductive portion; (b) forming a silicon-rich silicon oxide (SRO) layer on the to-be-etched substrate; (c) forming an anti-reflective layer on the silicon-rich silicon oxide layer; (d) forming a patterned photo resist layer on the anti-reflective layer; (e1) etching the anti-reflective layer and the silicon-rich silicon oxide layer so as to form at least a first opening corresponding to the patterned photo resist layer, the first opening only penetrating through the anti-reflective layer and the silicon-rich silicon oxide layer; (e2) removing the patterned photo resist layer after etching the anti-reflective layer and the silicon-rich silicon oxide layer; and (e3) etching the to-be-etched substrate so as to form at least a second opening exposing the conductive portion in one action, wherein the width of a top end of the second opening is near to that of a bottom end of the second opening, the width of the first opening which only penetrates through the anti-reflective layer and the silicon-rich silicon oxide layer is substantially near the width of a top end of the second opening, and the step (e3) is next to the step (e2).