Patent ID: 8131906

Claim:
A system, comprising: a five-level voltage comparator configured to identify voltages of a PCIXCAP pin bus, and to generate a voltage indicator signal based on the identified voltages; a first multiplexer coupled to the five-level voltage comparator and configured to generate a first multiplexer output based on the voltage indicator signal and an output of a first flip-flop, based on a first multiplexer select signal, the first multiplexer select signal asserted in response to assertion of a PCIXCAP sampling-done indicator signal; the first flip-flop coupled to the first multiplexer and configured to generate a first flip-flop output based on the first multiplexer output and a clock signal; a second multiplexer coupled to the first flip-flop and configured to generate a second multiplexer output based on the first flip-flop output and an output of a second flip-flop, based on a second multiplexer select signal; a counter coupled to the second multiplexer and configured to generate the second multiplexer select signal based on the clock signal; and the second flip-flop coupled to the second multiplexer and configured to generate a second flip-flop output based on the second multiplexer output and the clock signal.