Patent ID: 8766746

Claim:
A circuit comprising: a pMOS transistor having a source, a drain, and a gate, wherein the source of the pMOS transistor connects with a power supply; a nMOS transistor having a source, a drain, and a gate, wherein the drain of the nMOS transistor connects with the drain of the pMOS transistor, the gate of the nMOS transistor connects with the gate of the pMOS transistor, and the source of the nMOS transistor connects with ground; a resistor having a first end and a second end, wherein the first end of the resistor connects with the gate of the pMOS transistor and the gate of the nMOS transistor, and the second end of the resistor connects with the drain of the pMOS transistor and the drain of the nMOS transistor; and a voltage input connected to the drain of the nMOS transistor and the drain of the pMOS transistor.