Patent ID: 7557621

Claim:
A divider, comprising: a first flip-flop, being triggered by a frequency signal and being controlled by a mode control signal for enabling; a flip-flop array, comprising N second flip-flops, wherein N is an integer greater than 0, and a negative output terminal of each second flip-flop of the flip-flop array is coupled to an input terminal of an adjacent second flip-flop; a first NOT gate, having an input terminal coupled to a positive output terminal of the last second flip-flop of the flip-flop array, and an output terminal coupled to an input terminal of the first flip-flop, wherein the first NOT gate is controlled by the mode control signal for enabling; a second NOT gate, having an input terminal coupled to the positive output terminal of the last second flip-flop of the flip-flop array, wherein the second NOT gate is controlled by the mode control signal for enabling; and a circuit, wherein when N is an odd number, the circuit comprises a wire having a terminal coupled to an output terminal of the first flip-flop and an output terminal of the second NOT gate, and the other terminal coupled to an input terminal of the first second flip-flop of the flip-flop array; and when N is an even number, the circuit comprises a third NOT gate having an input terminal coupled to the output terminal of the first flip-flop and the output terminal of the second NOT gate, and an output terminal coupled to an input terminal of the first second flip-flop of the flip-flop array.