Patent ID: 6853029

Claim:
A semiconductor device comprising: a semiconductor substrate; at least one memory cell transistor provided on the semiconductor substrate; and at least one select transistor provided on the semiconductor substrate, the memory cell transistor including: first source and drain regions formed in the semiconductor substrate and including first impurities of a first conductivity type; a first channel region formed in the semiconductor substrate between the first source and drain regions and including second impurities of a second conductivity type at a first impurity concentration; a first gate insulating film provided on the first channel region; a charge storage layer provided on the first gate insulating film; a first inter-gate insulating film provided on the charge storage layer; and a control gate electrode provided on the first inter-gate insulating film, each select transistor including: second source and drain regions formed in the semiconductor substrate and including third impurities of the first conductivity type, so that the first drain region is connected to the second source region or the first source region is connected to the second drain region; a second channel region formed in the semiconductor substrate between the second source and drain region and including fourth impurities of the second conductivity type, the second channel region including a high-concentration channel region and a low-concentration channel region provided around the high-concentration channel region, the high-concentration channel region having a higher impurity concentration than the low-concentration channel region and the first channel region; a second gate insulating film provided on the second channel region and including the fourth impurities in at least a portion thereof; a first gate electrode provided on the second gate insulating film; and a second gate electrode provided on the first gate electrode, and electrically connected to the first gate electrode by a connection portion provided on a part of the first gate electrode, which is located immediately above at least a part of the region of the second gate insulating film including the fourth impurities, the high-concentration channel region being located underneath the connection portion.