Patent ID: 7388264

Claim:
A semiconductor device comprising: an insulated gate pattern having a top and sidewalls formed on a gate insulating layer on a semiconductor substrate, the insulated gate pattern including a gate electrode; LDD-type source/drain regions formed in the semiconductor substrate on both sides of the insulated gate pattern; a first conformal etch stop layer formed on the substrate having the insulated gate pattern and the LDD-type source/drain regions, wherein the first conformal etch stop layer is in direct contact with the sidewalls of the gate pattern from the gate insulating layer to the top of the gate pattern; an interlayer insulating layer formed on the first etch stop layer; a contact hole penetrating the interlayer insulating layer and the first etch stop layer, wherein the contact hole exposes the LDD-type source/drain region; and a device isolation layer neighboring the LDD-type source/drain regions, wherein the contact hole further exposes the device isolation layer.