Patent ID: 8072253

Claim:
A clock adjusting circuit comprising: a phase shifter circuit that receives a clock signal and that variably shifts and outputs a timing phase of both or one of a rising edge and a falling edge of a clock pulse, based on a control signal; and a control circuit that supplies the control signal at timing prior to a transition edge of the clock signal output from the phase shifter circuit, to the phase shifter; the clock adjusting circuit being able to output a clock signal that has at least one parameter out of a clock period, duty ratio, jitter, and skew changed on a clock cycle base; wherein the phase shifter circuit comprises: a first and a second phase shifter that receive an input clock signal in common; and a selector that receives outputs of the first and second phase shifters, and selectively outputs one thereof based on a selection control signal supplied thereto; the control circuit supplying a first and a second control signal to the first and second phase shifters, respectively; the first and second phase shifters variably shifting a rising edge and falling edge of the clock signal, respectively, and the selector selecting an output of the first phase shifter as a rising edge of the clock signal rising edge, and selecting an output of the second phase shifter as a falling edge of the clock signal; and wherein a signal generated from an output signal of the selector is used in the selection control signal.