Patent ID: 7996591

Claim:
A computing device, comprising: a peripheral bus having at least 2n data lines; a first expansion slot receiving a first peripheral card comprising 2n data line interconnects, and operable in a first mode using n of said 2n data lines, and in a second mode using 2n of said 2n data lines, said first expansion slot comprising a first set of n connectors, interconnected with n of said 2n data lines, and a second set of n connectors; and said first peripheral card configurable to disable use of n of said 2n data lines interconnected with said second set of n connectors of said first expansion slot when said first peripheral card is operating in said first mode; a second expansion slot receiving a second peripheral card comprising 2n data line interconnects, and operable in a first mode using n of said 2n data lines, and in a second mode using 2n of said 2n data lines, said second expansion slot comprising a first set of n connectors, interconnected with n further ones of said 2n data lines, and a second set of n connectors, wherein each of said second set of n connectors of said first expansion slot is interconnected to a corresponding one of said second set of n connectors of said second expansion slot; reset control lines for resetting said first and second peripheral cards in said first and second expansion slots, independently; a reset control circuit operable to initialize said first peripheral card in said first expansion slot, without concurrently initializing said second peripheral card in said second slot; and to reset said second peripheral card in said second expansion slot, after initialization of said first peripheral card in said first expansion slot, to train each of said first and second peripheral cards to operate in their first mode, each using n of said 2n data lines.