Patent ID: 7472255

Claim:
A method of addressing for performing an operation for reading or writing a symbol of k bits in a bank of memories linked to a processor by a data bus of p bits, the bank of memories being organized as words of p bits and employing word-based addressing, p being a positive integer greater than 4, and k being an integer lying between 1 and p, comprising: addressing a symbol with the aid of a word address designating a determined word of p bits which contains a first bit of the symbol, in combination with a bit pointer designating the first bit of the symbol in the word of p bits designated by the word address, a shift of bits being moreover performed, during the operation of reading or of writing, as a function of the value of the bit pointer, on the word of p bits read or written, such that processing time in the processor is reduced, and wherein the symbol comprises a variable length symbol corresponding to a fixed length word.