Patent ID: 7977229

Claim:
A method for fabricating a plurality of semiconductor apparatuses, each apparatus including a respective one of a plurality of semiconductor devices, a plurality of conductive posts electrically connected to the semiconductor device, a plurality of conductive bumps each provided on an outer end of each of the conductive posts so that the plurality of conductive bumps can be soldered onto a circuit board for mounting the semiconductor device thereon, and a molding resin covering a surface of the semiconductor device, the molding resin shaped to have a step at a peripheral edge of the semiconductor device entirely, the step having upper and lower level portions, the method comprising the steps of: providing a semiconductor wafer on which the plurality of semiconductor devices are formed, each semiconductor device having electrode pads thereon; for each semiconductor device, providing a plurality of conductive posts connected to the electrode pads thereof; sealing the semiconductor devices with a molding resin so that an upper surface of the molding resin is on the same plane with upper surfaces of the conductive posts, by covering all side surfaces of each of the conductive posts with the molding resin; removing a part of the molding resin to be located at a peripheral edge so that the peripheral edge of the molding resin has a step, the step of the molding resin having upper and lower level portions and contacting the side surfaces of each of the conductive posts, the removing exposing a portion of least one of the side surfaces of at least one of the conductive posts; providing conductive bumps on outer ends of the conductive posts; and dicing the semiconductor wafer to form a plurality of individual semiconductor apparatuses.