Patent ID: 8000156

Claim:
A memory device, comprising: a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, each sub-array comprising a plurality of memory cells arranged in a plurality of memory cell rows and at least one memory cell column; sub-array access circuitry associated with each sub-array, for detecting read data from a selected memory cell column of said associated sub-array during a read operation; and global access circuitry arranged to interface with said first end of said at least one sub-array column; each sub-array access circuitry comprising propagation circuitry for producing an output read data value, the propagation circuitry having a first input for receiving the read data detected from the selected memory cell column of said associated sub-array during said read operation and a second input for receiving an output read data value produced by a linked sub-array access circuitry associated with a sub-array in said sub-array column nearer said second end of the sub-array column, and the propagation circuitry receiving a control signal for identifying which of the first or second inputs is to be used to produce the output read data value; wherein an output read data value produced by any sub-array access circuitry is propagated to the global access circuitry via any linked sub-array access circuitry in the sub-array column between that sub-array access circuitry and the global access circuitry.