Patent ID: 8558576

Claim:
An output buffer comprising: a clamp output stage comprising a first clamp output part and a second clamp output part, wherein at least one of the first clamp output part and second clamp output part is configured to clamp a drain potential of a P-channel field effect transistor or a drain potential of an N-channel field effect transistor to an intermediate potential between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor by inserting a field effect transistor for potential clamp in series between the P-channel field effect transistor and the N-channel field effect transistor and inputting an intermediate level between the high potential and the low potential into a gate of the field effect transistor for potential clamp; an output equalizing circuit configured to average an output level of the first clamp output part and an output level of the second clamp output part per cycle; and a data input part configured to be connected to the front of the clamp output stage and to input a data signal into a gate of the P-channel field effect transistor and a gate of the N-channel field effect transistor based on an enable signal during data output, wherein the data input part comprises: a NAND circuit configured to output NAND by the data signal and the enable signal to the gate of the P-channel field effect transistor; and a NOR circuit configured to output NOR by the data signal and an enable inversion signal which is inverted from the enable signal to the gate of the N-channel field effect transistor.