Patent ID: 7385242

Claim:
A DRAM cell array region comprising: a semiconductor substrate; a trench isolation disposed in a predetermined region of the semiconductor substrate to define an active region; a plurality of first line patterns on an upper portion of the active region; a plurality of second line patterns, formed on an upper portion of the trench isolation layer adjacent to at least one side of the active region, wherein at least one second line pattern is formed in parallel with the first line pattern and on a side opposite to the first line pattern; line spacers formed on side walls of the first and second line patterns; a material layer covering the upper surface of the semiconductor substrate; an upper bit line opening located in a first region between the first line patterns, a first upper storage opening located in a second region between the first and the second line patterns, and a second upper storage opening located in a third region between the first and the second line patterns; barrier layers formed on the side walls defining the upper bit line opening, the first upper storage opening, and the second upper storage opening; a lower bit line opening, a first lower storage opening, and a second lower storage opening formed by penetrating the first region, the second region, and the third region to expose the first and second line patterns; and a bit line landing pad, a first storage landing pad, and a second storage landing pad which fill the lower and upper bit line openings, the first lower and upper storage openings, and the second lower and upper storage openings respectively; wherein the upper bit line opening, the first upper storage opening, and the second upper storage opening are formed so that their respective bottom surfaces are no higher than the upper surface of each of the first and second line patterns.