Patent ID: 8799713

Claim:
A system for self-test comprising: a processor that is arranged to execute a normal application for controlling a process that is external to the processor, wherein the normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots; and a built-in self-test (BIST) controller that is arranged to detect the presence of an idle timeslot, to use a scan chain to scan-in a first test pattern for a test application, to cause the first test pattern to be executed by the processor during the detected idle timeslot, to scan-out a first result pattern generated by the execution of the first test pattern, and to determine the presence of an error by evaluating the first result pattern; wherein the BIST controller is arranged to log an interrupt that occurs during execution of the first test pattern and to assert the logged interrupt after completion of the execution of the first test pattern and wherein the BIST controller is arranged to assert a non-maskable interrupt upon detection of the non-maskable interrupt during the execution of the first test pattern, and to restart the execution of the first test pattern when a subsequent idle timeslot is detected.