Patent ID: 8288256

Claim:
A method, comprising: performing a first implantation process to introduce a first dopant species of a first conductivity type into a semiconductor region to form drain and source extension regions adjacent a gate electrode; performing a second implantation process to introduce said first dopant species into said semiconductor region to form a first portion of drain and source regions deeper than said drain and source extension regions by using said gate electrode and a spacer structure formed on sidewalls thereof to mask said second implantation process; performing a first anneal process for activating said first dopant species and substantially adjusting an effective channel length of a transistor defined by said gate electrode and said semiconductor region; after performing the first anneal process, performing a third implantation process to introduce a second dopant species of said first conductivity type into said semiconductor region to form a second portion of said drain and source regions deeper than said first portion by using said gate electrode and said spacer structure to mask said third implantation process, wherein said third implantation process is performed using the same spacer structure used to perform said second implantation process; and performing a second anneal process for activating said first and second dopant species.