Patent ID: 7047506

Claim:
A method for optimizing design of a microelectronic circuit using a plurality of processors, the design having a plurality of timing paths, a subset of the timing paths being characterized as critical paths, each of the timing paths having an endpoint, the method comprising the steps of: constructing a list of the critical paths; constructing a set of endpoints of said critical paths; partitioning said set of endpoints in accordance with a first predetermined rule regarding timing independence of the critical paths and a second predetermined rule regarding geometric independence of the critical paths, thereby defining sub-sets of endpoints and critical paths associated therewith, wherein said first predetermined rule requires that all critical paths associated with a given endpoint are assigned to a same sub-set of paths and said second predetermined rule requires that all overlapping critical paths are assigned to a same sub-set of paths; and optimizing timing of the critical paths, wherein said optimizing is performed in parallel by the processors, each of the processors optimizing timing of the critical paths associated with the endpoints in respective sub-sets, and the microelectronic circuit includes a multiplicity of components, and said method is performed after placement of the components in the design.