Patent ID: 7576583

Claim:
A single-event effect tolerant latch circuit comprising: a dual-port inverter ( 6 IP 1 ) having two input nodes for receiving a pair of inputs, and two output nodes, wherein said pair of inputs are coupled to said dual-port inverter, respectively, via a first transmission gate ( 6 S 1 ) and a second transmission gate ( 6 S 2 ); a dual-port clocked inverter ( 6 IP 2 ) having two input nodes coupled to the two output nodes of said dual-port inverter ( 6 IP 1 ), and two output nodes; and an output node connected to at least one of the two output nodes of said dual-port inverter ( 6 IP 1 ) and the two output nodes of said dual-port clocked inverter ( 6 IP 2 ), wherein said dual-port inverter ( 6 IP 1 ) includes a first inverter ( 6 I 9 ) and a second inverter ( 6 I 11 ); said first inverter ( 6 I 9 ) includes a 1st transistor ( 6 P 16 ) and a 2nd transistor ( 6 N 16 ) which are connected to each other in series; said second inverter ( 6 I 11 ) includes a 3rd transistor ( 6 P 20 ) and a 4th transistor ( 6 N 20 ) which are connected to each other in series; each of said 1st and 3rd transistors ( 6 P 16 , 6 P 20 ) is a p-channel transistor; each of said 2nd and 4th transistors ( 6 N 16 , 6 N 20 ) is an n-channel transistor; a gate of said 1st transistor ( 6 P 16 ) is connected to a gate of said 4th transistor ( 6 N 20 ) to provide a first inverter input node; a gate of said 2nd transistor ( 6 N 16 ) is connected to a gate of said 3rd transistor ( 6 P 20 ) to provide a second inverter input node; said 1st and 2nd transistors ( 6 P 16 , 6 N 16 ) provide a first inverter output node; said 3rd and 4th transistors ( 6 P 20 , 6 N 20 ) provide a second inverter output node; said first and second inverter input nodes are adapted to receive identical inputs to provide a valid output at either said first inverter output node or said second inverter output node; a third inverter ( 6 I 6 ); and a fourth inverter ( 6 I 7 ) having an input node interconnected to an input node of said third inverter, wherein: said third inverter ( 6 I 6 ) has an output node connected to said first inverter input node via said first transmission gate ( 6 S 1 ); and said fourth inverter ( 6 I 7 ) has an output node connected to said second inverter input node via said second transmission gate ( 6 S 2 ).