Patent ID: 8418121

Claim:
A method for using a formal verification tool to verify a property of a circuit, the method comprising, with a computer: analyzing the behavior of the circuit for a number of cycles of operation starting from a seed state, the analyzing comprising verifying the property based at least in part on the value of a proof radius variable using the formal verification tool; checking whether a counterexample to the property is found; iteratively repeating one or more sequences of the analyzing and the checking to produce one or more proof radius values for the sequences for a respective starting seed state, the iteratively repeating comprising: if a counterexample is not found, then increasing the value of the proof radius variable, and if a counterexample is found, a stopping variable reaches a predetermined limit, or a counterexample is found and a stopping variable reaches a predetermined limit, then stopping the repeating the analyzing and the checking; and reporting a measure of analysis based on the proof radius values produced by the repeating, at least one of the proof radius values corresponding to a respective one of the seed states.