Patent ID: 8136009

Claim:
A circuit arrangement for generating at least one check bit that can be evaluated for error detection, the circuit arrangement comprising: a combinational circuit having n binary inputs E 1 , . . . , En for inputting n (n≧2) information bits x 1 , . . . , xn and m binary outputs for outputting m (m≧1) check bits c 1 , . . . , cm; wherein the combinational circuit is configured to realize a Boolean function ci=fi(xi 1 , . . . , xini) for i=1, . . . , m at the i-th output for determining a check bit ci, wherein the set {xi 1 , . . . , xini} at the ni information bits that determine the check bit ci is a subset of all n information bits {x 1 , . . . , xn}; and wherein the combinational circuit is furthermore configured to realize a first Boolean function f 1 (x 11 , . . . , x 1 n 1 ) of the form c 1 =f 1 (x 11 , . . . , x 1 n 1 )=f 11 (x 11 , x 12 ) XOR f 12 (x 13 , x 14 ) XOR . . . XOR f 1 k 1 (x 1 (n 1 −1), x 1 n 1 ) at a first output for outputting a first check bit c 1 , wherein n 1 is an even number where n 1 ≧2 and 2 k 1 =n 1 and the Boolean functions f 11 (x 11 , x 12 ), . . . , f 1 k 1 (x 1 (n−1), x 1 n 1 ) are each nonlinear Boolean functions of two variables that can be realized by logic gates having two inputs and one output, wherein the logic gates each have a controlling value c 11 , . . . , c 1 k 1 .