Patent ID: 7060572

Claim:
A method for forming a MOSFET with a short channel structure, the method comprising the steps of: performing a first ion implantation into a substrate resulting in the substrate having a first threshold voltage; forming a sacrificial layer on the substrate to define a channel region; forming a source/drain on the substrate, wherein the source/drain are coupled to the channel region; forming a first dielectric layer on the substrate and the sacrificial layer; removing a portion of the first dielectric layer to expose the sacrificial layer; removing the sacrificial layer to generate an opening in the first dielectric layer and to expose the channel region; forming a second dielectric layer on the first dielectric layer and the channel region; performing an anisotropic etching on the second dielectric layer to form a plurality of spacers adjacent to the opening, wherein a portion of the channel region of the substrate is defined as a first region and an exposed channel region; performing a second ion implantation on the exposed channel region, resulting in the exposed channel region having a second threshold voltage and being defined as a second region; removing the spacers of the first region, wherein the first threshold voltage of the first region is smaller than the second threshold voltage of the second region; forming a gate dielectric layer on the channel region; and forming a conductive layer on the gate dielectric layer and the first dielectric layer.