Patent ID: 8447954

Claim:
A method of vector reduction in a parallel processing data processing system, said method comprising: the data processing system building at least one data structure indicating a communication schedule for a plurality of processes each having a respective one of a plurality of equal length vectors formed of multiple equal size chunks; the data processing system, based upon the at least one data structure, communicating chunks of the plurality of vectors among the plurality of processes and performing partial reduction operations on chunks in accordance with the communication schedule; and the data processing system storing a result vector representing reduction of the plurality of vectors, wherein building at least one data structure includes: building at least one data structure indicating a binary representation of an integer rank of each of the plurality of processes; building at least one data structure indicating a distance in the binary representation to a bit of a given value; and building, when the plurality of processes is not an integer power of two, at least one data structure indicating the number of non-zero bits between the right most bit and a bit at a given position in the binary representation.