Patent ID: 7348235

Claim:
A method of manufacturing a semiconductor device having a memory cell and a peripheral circuit formed in a semiconductor substrate, said memory cell including a capacitor with a first electrode which is an impurity diffusion layer formed in said semiconductor substrate, said method comprising the steps of: (a) forming a trench in an upper portion of said semiconductor substrate in each of a memory cell area in which said memory cell is formed and a peripheral circuit area in which said peripheral circuit is formed in said semiconductor substrate; (b) forming an isolation insulation film in said trench in each of said memory cell area and said peripheral circuit area; (c) forming said impurity diffusion layer to be said first electrode on an inner wall of said trench in a capacitor region in which said capacitor is to be formed in said memory cell area; (d) removing said isolation insulation film in said capacitor region to create an opening by which the inner wall and bottom of said trench are exposed; (e) forming a dielectric layer on the inner wall and bottom of said trench exposed by said opening; and (f) forming a second electrode on said dielectric layer including the inside of said opening, wherein said step (a) is carried out by etching using a first mask pattern formed on said semiconductor substrate as a mask, and said step (d) is carried out without removing said first mask pattern.