Patent ID: 7977751

Claim:
An insulated gate field effect transistor comprising: (A) a source/drain region and a channel formation region; (B) a gate electrode formed above said channel formation region; (C) sidewall spacers between which said gate electrode is located; and (D) a gate insulating film; wherein, said gate electrode is composed of a first layer made of a first metallic material, a second layer made of a second metallic material different from the first metallic material, and a third layer made of a third metallic material different from the first metallic material, said first layer extends from a bottom surface portion of said gate electrode facing said channel formation region to a height H Mt-1 along said side surface of said gate electrode, said second layer and said third layer occupy a remaining portion of said gate electrode in a lamination state. a height of an interface between said second layer and said third layer is H Mt-2 with said surface of said channel formation region as the reference, H Mt-1 <H Gate , and H mt-1 ≈H Mt-2 , said gate insulating film is composed of a gate insulating film main body portion formed between said gate electrode and said channel formation region, and gate insulating film extension portion extending from said insulating film main body portion along side surface of said gate electrode, a height of said gate electrode is H Gate and a height of said gate insulating film extension portion is H Ins with a surface of said channel formation region as a reference, K Ins <H Gate , and above H Ins said gate electrode extends out to said sidewall spacers.