Patent ID: 7203128

Claim:
A ferroelectric memory device comprising: a voltage source for generating a predetermined voltage; a first bit line and a second bit line; a first ferroelectric capacitor having one end electrically connected to the first bit line; a first resistor provided between the first bit line and the voltage source; a first switch provided between the voltage source and the first bit line, for switching as to whether the predetermined voltage is to be supplied for a predetermined period to the first bit line through the first resistor; a second ferroelectric capacitor having one end electrically connected to the second bit line; a second resistor provided between the second bit line and the voltage source; a second switch provided between the voltage source and the second bit line, for switching as to whether the predetermined voltage is to be supplied for a predetermined period to the second bit line through the second resistor; and a sense amplifier that judges data written in the first ferroelectric capacitor based on a potential on the first bit line, according to a timing at which a potential on the second bit line changes when the predetermined voltage is simultaneously supplied to both the first bit line and the second bit line.