Patent ID: 6905928

Claim:
A method of manufacturing a MOS transistor comprising the steps of: providing a pair of impurity regions of a second conductivity type on a semiconductor substrate of a first conductivity type; providing an insulating film on said semiconductor substrate in between said impurity regions of a second conductivity type; and depositing a conducting film on said insulating film, including providing fine particles onto said insulating film, whereby said fine particles are incorporated in said conducting film, wherein said conducting film and said fine particles are in contact with said insulating film, wherein said insulating film is an oxide film said fine particles are silicon, and said conducting film is a polycrystalline silicon germanium film, wherein the step of layering said silicon film and polycrystalline silicon germanium film onto said oxide film by CVD comprises a step of forming said silicon film and said polycrystalline silicon germanium film consecutively by changing the mixture ratio of SiH4 and GeH4 as source gases, in a temperature range in which said silicon film is amorphous and said polycrystalline silicon germanium film is crystalline.