Patent ID: 7945086

Claim:
A method for evaluating the quality of structures on an integrated circuit wafer, comprising the steps of: exposing one or more test structures to an electron beam and an electron-beam activated chemical etching gas or vapor, wherein the one or more test structures are formed in a test wafer or on the integrated circuit wafer at one or more scribe lines between two or more die on the integrated circuit wafer, whereby the electron-beam activated chemical etching gas or vapor etches the one or more test structures; and analyzing the one or more test structures after etching to determine a measure of quality of the one or more test structures, wherein exposing the one or more test structures to the electron beam includes the use of a scanning electron microscope to provide the electron beam and to produce one or more images of the one or more test structures, wherein analyzing the one or more test structures further comprises performing a pattern recognition on the one or more images, wherein performing the pattern recognition includes determining a size of a void in each test structure and creating a histogram of the sizes of the voids.