Patent ID: 8022723

Claim:
An integrated circuit comprising: an input stage responsive to an input signal, an enabling signal, and a programmable bit; and an output stage generating an output signal and comprising: a pull-up circuit comprising a pull-up transistor responsive to the input signal, the enabling signal and the programmable bit, said enabling signal not being responsive to the output signal, a gate voltage of the pull-up transistor being independent of the output signal, the pull-up transistor being: in a conductive state when the input signal is in a first logic state and the enabling signal is in a second logic state; in a non-conductive state when both the input signal and the enabling signal are in the second logic state; in a non-conductive state when the programmable bit and the enabling signal are in the first logic state; and in a conductive state when the programmable bit is in the second logic state and the enabling signal is in the first logic state; a pull-down circuit comprising a pull-down transistor responsive to the input signal, the enabling signal and the programmable bit, a gate voltage of the pull-down transistor being independent of the output signal, the pull-down transistor being: in a non-conductive state when the input signal is in the first logic state and the enabling signal is in the second logic state; in a conductive state when both the input signal and the enabling signal are in the second logic state; in a non-conductive state when the programmable bit and the enabling signal are in the first logic state; and in a conductive state when the programmable bit is in the second logic state and the enabling signal is in the first logic state.