Patent ID: 7510927

Claim:
A method comprising: providing a silicon-on-insulator wafer, said silicon-on-insulator wafer comprising a buried oxide layer covered by a thin silicon body layer; forming a composite stack over said thin silicon body layer, said thin silicon body layer having a thickness of 3-40 nanometers, said composite stack comprising a pad oxide layer covered with a silicon nitride layer, said pad oxide layer having a thickness selected from a range of 3-8 nm, said silicon nitride layer having a thickness selected from a range of 65-150 nm, wherein a ratio of said silicon nitride layer thickness to said pad oxide layer thickness is about 20:1; forming a photoresist over said composite stack; forming an opening in said photoresist; removing said composite stack in said opening while passivating sidewalls of said opening wherein an etch selectivity of said silicon nitride layer and said pad oxide layer relative to said photoresist is 20:1 or greater; reducing by about 30% said thickness of said thin silicon body layer in said opening; removing said photoresist over said composite stack; forming a field oxide layer from said thin silicon body layer in said opening; and thinning down said field oxide layer while removing said composite stack over said thin silicon body layer by a dry etch process wherein an upper surface of said field oxide layer is relatively level or planar with an upper surface of said thin silicon body layer and a length of a modified bird's beak is about 30-60% of a thickness of said thin silicon body layer after removal of said composite stack.