Patent ID: 8898648

Claim:
A method for detecting a false sharing of a cache memory line in a multi-threaded computing environment, the method comprising: receiving, at a compiler, source code of a program written in a high-level programming language; generating, by the compiler, binary code of the received source code; identifying a code region, in the generated binary code, with a false sharing potential; classifying variables and arrays in the identified code region; monitoring all memory access instructions in the identified code region while a processor is running the identified code region; identifying memory addresses accessed by the memory access instructions in the identified code region while the processor is running the identified code region; identifying, based on the identified memory addresses and the classifying, one or more instructions at risk in the identified code region, the one or more instructions at risk associated with one class of the classified variables and arrays; aborting the running of the identified code region upon the one or more instructions at risk are identified; configuring the processor to re-run the identified code region; analyzing only the one or more instructions at risk in the identified code region while the processor is re-running the identified code region; determining, based on the analysis of the one or more instructions at risk, whether two different portions of the cache memory line are accessed by the generated binary code; and indicating a false sharing of the cache memory line if the two different portions of the cache memory line are accessed by the generated binary code.