Patent ID: 8664727

Claim:
A semiconductor integrated circuit device, comprising: a semiconductor substrate having a first conductivity type; a first well region having the first conductivity type and a plurality of second well regions having a second conductivity type, the first well region and the plurality of second well regions being provided in different regions immediately under a surface of the semiconductor substrate, each of the plurality of second well regions having a well region edge which corresponds to a boundary defining each second well region, wherein at least two adjacent second well regions of the plurality of second well regions are separated by the first well region; a plurality of first MOS transistors having the second conductivity type which are provided within the first well region having the first conductivity type; and a plurality of second MOS transistors having the first conductivity type, each of the plurality of second well regions containing only one second MOS transistor, each of the plurality of second MOS transistors having a channel region of the first conductivity type which defines a channel region edge, the channel region edge corresponding to an outer boundary of a channel region; a lateral distance and a longitudinal distance between the well region edge and the channel region edge in each of the plurality of second MOS transistors respectively measured in a lateral direction and in a longitudinal direction being substantially equal.