Patent ID: 7652499

Claim:
An integrated circuit (IC) comprising: a) a plurality of memory tiles each comprising a set of memory circuits and a first plurality of input select interconnects for receiving signals on a plurality of inputs and supplying the signals received on a selected set of the inputs to the memory circuits; b) a plurality of configurable computational tiles each comprising at least one configurable logic circuit and a second plurality of input select interconnects for receiving signals on a plurality of inputs and supplying the signals received on a selected set of the inputs to the configurable logic circuit; and c) a configurable routing fabric for passing data between said computational tiles and said memory tiles, the configurable routing fabric comprising: a first set of configurable routing elements located in a particular arrangement within each of the plurality of memory tiles, wherein said first set of configurable routing elements comprises a first set of outputs that provides data to said first plurality of input select interconnects; and a second set of configurable routing elements, matching said first set of configurable routing elements, located in the same particular arrangement within each of the plurality of configurable computational tiles, wherein said second set of configurable routing elements comprises a second set of outputs that provides data to said second plurality of input select interconnects.