Patent ID: 7403036

Claim:
An interface circuit comprising: a three-state buffer for outputting output data applied to an input thereof to a bi-directional bus when a control signal is at a first level, and bringing an output thereof into a high-impedance state when the control signal is at a second level; a buffer for fetching a signal on said bi-directional bus as input data; and a logical gate for outputting the control signal at the first level when an output enable signal is in an active state or when said hi-directional bus is enabled by a bus control signal which is set in accordance with an output state of a device connected to said bi-directional bus and a bus access signal indicates that said bi-directional bus is not in use, and outputting the control signal at the second level when the output enable signal is in an inactive state and said bi-directional bus is not enabled by the bus control signal or when the output enable signal is in an inactive state and the bus access signal indicates that said bi-directional bus is in use.