Patent ID: 7996595

Claim:
A method for handling interrupts within a multiprocessor computing system having a plurality of processors, the method comprising: receiving an interrupt associated with an interrupt handler at the multiprocessor computing system; establishing a list of eligible processors for executing the interrupt handler, the list of eligible processors comprising a subset of the plurality of processors; transmitting an interrupt message to the subset of the plurality of processors, the interrupt message comprising an interrupt identifier of the interrupt and an interrupt priority level of the interrupt; upon transmitting the interrupt message to the subset of the plurality of processors, receiving core response messages from the subset of the plurality of processors, each of the core response messages comprising an identifier of one of the subset of the plurality of processors, the interrupt identifier of the interrupt, a current task priority level of the one of the subset of the plurality of processors, and a decision message, the decision message indicating whether the one of the subset of the plurality of processors accepts or rejects the interrupt based on a comparison between the current task priority level and the interrupt priority level; identifying a processor in the list of eligible processors by evaluating the core response messages, the processor associated with the decision message indicating accept and having a lowest current task priority level; and assigning the processor associated with the decision message indicating accept and having the lowest current task priority level to execute the interrupt handler.