Patent ID: 7649395

Claim:
A scan flip-flop circuit comprising: a data input; a scan input; a data output; a flip-flop providing an output signal at said data output of said scan flip-flop circuit; a multiplexer, for selecting a signal at one of said scan input and said data input, for presentation at an input of said flip-flop; said multiplexer comprising a delay element, in a signal path between said scan input and said input of said flip-flop, to provide a signal propagation delay between said scan input and said input of said flip-flop, that is in excess of a signal propagation delay between said data input and said input of said flip-flop; and wherein said multiplexer comprises: (a) a first PMOS-AND structure comprising a plurality of PMOS transistors interconnected in series; and (b) a first NMOS-AND structure comprising a plurality NMOS transistors interconnected in series; and wherein said first NMOS-AND structure is connected between said first PMOS-AND structure and electrical ground; and said first PMOS-AND structure is interconnected between a supply voltage and said first NMOS-AND structure; and wherein said delay element comprises at least one of (i) a PMOS diode interconnected to two of said PMOS transistors in said first PMOS-AND structure; and (ii) an NMOS diode interconnected to two of said NMOS transistors in said first NMOS-AND structure.