Patent ID: 8811103

Claim:
A semiconductor memory circuit comprising: a memory circuit region including: a pair of bit lines; a plurality of word lines; a plurality of memory cells, each of which is coupled to one of the bit lines and to one of the word lines, and including a first transistor having a first gate electrode and a first gate oxide film; a sense amplifier circuit coupled to the pair of bit lines to amplify a potential difference between the pair of bit lines so as to provide the pair of bit lines with a high-level potential and a low level-potential respectively, and a precharging circuit, including a second transistor having a second gate electrode and a second gate oxide film, and adapted to set the bit lines at an intermediate level when the plurality of memory cells are in a non-selected state, wherein the intermediate level is between the high-level potential and the low-level potential; and a peripheral circuit region including a third transistor having a third gate electrode and a third gate oxide film, wherein the first gate oxide film has a first thickness which is thicker than that of the second gate oxide film, wherein the second gate oxide film and the third gate oxide film have substantially the same thickness, wherein a first voltage is applied to the first gate electrode to activate the first transistor, wherein a second voltage is applied to the second transistor to activate the second transistor, wherein a third voltage is applied to the third gate electrode to activate the third transistor, and wherein each of the first voltage and the second voltage is higher than the third voltage.