Patent ID: 8645891

Claim:
A device for generating wiring data indicating a connection wiring pattern extending over a substrate from each electrode of a semiconductor chip placed on said substrate, the device comprising: an error acquiring part that acquires a configuration error of said semiconductor chip relative to a certain reference position and a certain reference angle on said substrate; an area information acquiring part that acquires enclosing area information indicating an enclosing area enclosing said semiconductor chip on said substrate; and a wiring data generating part that generates enclosing area wiring data indicating an enclosing area wiring pattern based on a reference fan-out line established for a reference chip, the enclosing area wiring pattern being a part of said connection wiring pattern and covering said enclosing area, wherein said reference chip expresses the condition of said semiconductor chip placed in said reference position and said reference angle on said substrate, a reference wiring pattern free from faulty wiring is assigned to said reference chip as a pattern corresponding to said connection wiring pattern, said reference fan-out line is a part of said reference wiring pattern and routed on said reference chip, and said wiring data generating part generates said enclosing area wiring data such that the position and the angle of said reference fan-out line relative to said reference chip, and the position and the angle of a fan-out line for said semiconductor chip on said substrate relative to this semiconductor chip, agree with each other independently of said configuration error.