Patent ID: 8683185

Claim:
A computer-implemented method for processing instructions with loops during compile, the method comprising: creating, by a processor unit, a first group of instructions having a first set of loops and second group of instructions having a second set of loops from the instructions; placing, by the processor, the first group and the second group in an order, wherein the order is based on a history of the number of terminations associated with each set of loops, wherein the first set of loops have a different order of parallel processing from the second set of loops; processing, by the processor unit, the first group; monitoring, by the processor unit, terminations in the first set of loops during processing of the first group; determining, by the processor unit, whether a number of terminations being monitored in the first set of loops is greater than a selectable number of terminations; and responsive to a determination that the number of terminations is greater than the selectable number of terminations: i) ceasing, by the processor unit, processing the first group; and ii) processing, by the processor unit, the second group.