Patent ID: 8423944

Claim:
A design supporting method, comprising causing a computer processor to execute the operations of: partitioning a source path of circuit information into partitioned paths, the source path is partitioned in units of cell sequences of cells of the same type included in the source path; calculating a variation value of a first cell sequence of the cell sequences having a first cell type based on variation values of cells of the first cell sequence and the number of cells of the first cell sequence; calculating a variation value of a second cell sequence of the cell sequences having a second cell type based on variation values of cells of the second cell sequence and the number of the cells of the second cell sequence; judging whether partition of the first cell sequence and second cell sequence is preformed respectively based on the variation value of the first cell sequence and the variation value of the second cell sequence; partitioning at least one of the first cell sequence and second cell sequence based on said judging; calculating a variation value of each of the partitioned paths based on variation values on a delay of a cell included in the corresponding partitioned path; calculating a partition propagation delay time of each of the partitioned paths based on the variation value of the corresponding partitioned path; and calculating a source propagation delay time of the source path by merging the partition propagation delay time of each of the partitioned paths.