Patent ID: 8539164

Claim:
A multiprocessor computer system comprising: a host coherency domain including host main memory; a client coherency domain including, a client processor capable of accessing said host main memory, and a client cache device operative to store accesses by said client processor to said host main memory; said host coherency domain including a host filter tag cache device associated with said host main memory, said host filter tag cache device being operative to store information identifying ownership of data in said host main memory including ownership by coherency domains other than said host coherency domain, said host filter tag cache device being operative to selectively invalidate host filter tag cache entries when space is required in said host filter tag cache device for new cache entries; wherein said client cache device is configured to respond to an event indicating that a client cache entry has low value to said client processor by sending a downgrade-importance hint to said host filter tag cache device; and wherein said host filter tag cache device is configured to respond to receipt of said downgrade-importance hint by storing an indication that said entry has a low value to said client processor, said host filter tag cache device being adapted for selecting a filter tag cache entry marked as having a low value to said client processor to invalidate in favor of a client filter tag cache entry not marked as having a low value to said client processor or other remote processor that is remote with respect to said client coherency domain.