Patent ID: 6922770

Claim:
A memory controller comprising: a front-end module comprising; a page packet generator, for generating one or more page packets from each of a plurality of memory commands, wherein the order of receipt of said memory commands is preserved; and an address translation logic communicatively coupled to said page packet generator, for translating a logical address of each of said plurality of memory commands into a physical address of a corresponding one of said page packets; a back-end module communicatively coupled to said front-end module, for dynamically issuing a next one of said plurality of page packets while issuing a current one of said plurality of page packets, wherein said current page packet access a first bank and said next page packet access a second bank; and a physical interface module communicatively coupled to said back-end module, for causing a plurality of transfers according to said dynamically issued said current one and said next one of said plurality of page packets.