Patent ID: 7564134

Claim:
A semiconducter memory device comprising: a memory cell region, including first and second memory cells disposed adjacent to each other in a first direction and having a common word line, a peripheral circuit region proximate in a second direction to the memory cell region, comprising a plurality of field effect transistors (FETs) having their respective sources, channels and drains formed in a semiconductor layer; a first bit line and a first complementary bit tine connected to the first memory cell and extending in the second direction to the peripheral circuit region formed in a bit line metal layer; a second bit line and a second complementary bit line connected to the second memory cell and extending in the second direction to the peripheral circuit region formed in the bit line metal layer; a first equalization PET formed in the peripheral circuit region and electrically connected to and between the first bit line and the first complementary bit line, wherein a portion of the first equalization FET is overlapped by at least one of the second bit line and the second complementary bit line; a second equalization EEl formed in the peripheral circuit region and electrically connected to and between the second bit line and the second complementary bit line, wherein a portion of the second equalization EEl is overlapped by at least one of the first bit line and the first complementary bit line; a gate layer including the gate electrodes of the field effect transistors (FETs); and a first metal wiring line configured to transmit electrical signals in the second direction to the gate electrode of the first equalization FET; and a second metal wiring line configured to transmit electrical signals in the second direction to the gate electrode of the second equalization FET.