Patent ID: 7379516

Claim:
A data read receiver having an input terminal for receiving an input signal and producing an output signal at an output terminal, and comprising: an equalization and interpolated timing recovery circuit inserted between an input and an output terminal of the data read receiver; and a timer circuit coupled to the output terminal of the data read receiver and feedback connected to the equalization and interpolated timing recovery circuit; wherein said equalization and interpolated timing recovery circuit comprises a plurality of FIR equalization/interpolation stages inserted between the input terminal of the data read receiver and a MUX selection block driven by said timer circuit, in turn connected to the output terminal of the data read receiver, said FIR equalization/interpolation stages having preset filter FIR coefficients capable of being adapted in order to perform equalization and timing interpolation in a single phase, and in that the equalization and interpolated timing recovery circuit performs slow channel optimization independently over all of the stages by letting them adapt only when selected by the said timer circuit, the selected FIR equalization/interpolation stage being connected, through said MUX selection block, to the output terminal of the data read receiver at any given time in a sampling period.