Patent ID: 7071511

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate: a plurality of first cell transistors which are arranged in rows and columns on the semiconductor substrate; a plurality of first selection gates which are provided on the semiconductor substrate and select rows of first transistors; and element-isolating regions which are provided adjacent to columns of the first selection gates and columns of the first cell transistors and which isolate the first selection gates and the first cell transistors; each of the first cell transistors including: a floating gate which is formed on a gate insulating film provided on the semiconductor substrate; source-drain regions which are provided in the semiconductor substrate and formed on those sides of the floating gate which face each other in a column direction; an inter-gate insulating film which is provided on one side of the floating gate; and a control gate which is provided on the inter-gate insulating film and above those sides of the floating gate which face each other in the column direction, wherein each of the first selection gates is provided on the gate insulating film, has a mask layer made of insulating film and provided on the top, a trench made in the mask layer and a conductive member provided in the trench, and is connected to adjacent first selection gates by the conductive member.