Patent ID: 8124987

Claim:
A light-emitting element chip, comprising: a substrate; a light-emitting portion including a plurality of light-emitting elements each having a first semiconductor layer that has a first conductivity type and that is stacked on the substrate, a second semiconductor layer that has a second conductivity type and that is stacked on the first semiconductor layer, the second conductivity type being a conductivity type different from the first conductivity type, a third semiconductor layer that has the first conductivity type and that is stacked on the second semiconductor layer, and a fourth semiconductor layer that has the second conductivity type and that is stacked on the third semiconductor layer; a setting portion including a plurality of setting elements, the setting elements being respectively provided corresponding to the plurality of light-emitting elements, the setting elements each making the corresponding one of the light-emitting elements ready to emit light when the setting elements are turned on, and the setting elements each having the first semiconductor layer stacked on the substrate, the second semiconductor layer stacked on the first semiconductor layer, the third semiconductor layer stacked on the second semiconductor layer and the fourth semiconductor layer stacked on the third semiconductor layer; and a controller including a logical operation element that performs logical operation for causing the plurality of light-emitting elements of the light-emitting portion to perform a light-emitting operation, the logical operation element being formed by combining some sequential layers of the first semiconductor layer stacked on the substrate, the second semiconductor layer stacked on the first semiconductor layer, the third semiconductor layer stacked on the second semiconductor layer, and the fourth semiconductor layer stacked on the third semiconductor layer, wherein the controller includes, as the logical operation element, a NOT circuit including: an input electrode to which a signal is inputted; an output electrode from which a logical operation result is outputted; a reference potential electrode set to have a reference potential; and a direct current voltage electrode that supplies a direct current voltage for forward biasing a junction of the first semiconductor layer and the second semiconductor layer, the first semiconductor layer is connected to the reference potential electrode, the second semiconductor layer is connected to the direct current voltage electrode, the third semiconductor layer is connected to the input electrode, and the fourth semiconductor layer is connected to the output electrode.