Patent ID: 8223550

Claim:
A nonvolatile semiconductor memory apparatus, comprising: memory cell strings each including a plurality of memory cells including a charge accumulation layer and a control gate of which current pathways are connected in series; first and second bit lines each connected to the current pathway of one of the memory cells in one end side of the series connection; a first buffer connected to the first bit line and capable of holding first data of a first bit number; a second buffer connected to the second bit line and capable of holding second data of the first bit number; and a data transfer controlling unit including first and second latches and controlling timing to output the first and second data held in the first and second buffers to an external terminal according to a first internal signal generated based on a first external signal, a second internal signal generated at rising of the first external signal and a third internal signal generated at falling of the first external signal, and the data transfer controlling unit transferring a control signal synchronized with the timing of the first and second data to the external terminal, the data transfer controlling unit allowing the first latch to hold the first and second data held in the first and second buffers respectively, in synchronization with the first internal signal, and transferring the first data held in the first latch in synchronization with the second internal signal to the external terminal through the second latch, and thereafter transferring the second data to the external terminal through the second latch in synchronization with the third internal signal.