Patent ID: 7486578

Claim:
A test method for a ferroelectric memory including a cell block that includes: a block select transistor arranged between a bit line and a local bit line, which is turned on/off depending on a potential of a block select line; memory cells arranged between the local bit line and a plate line, each of the memory cells contains a cell transistor and a ferroelectric capacitor connected in series, and the cell transistor turned on/off depending on a potential of word lines; and a reset transistor arranged between the local bit line and the plate line, which is turned on/off depending on a potential of a reset line, the method comprising: applying a potential that allows the cell transistors to be ON to the word lines; applying a potential that allows the reset transistor to be OFF to the reset line; applying a potential that allows the block select transistor to be ON to the block select line; and applying a stress voltage between the bit line and the plate line.