Patent ID: 7504687

Claim:
A method, comprising: forming a first source/drain region and a second source/drain region separated by a channel region; forming a floating gate opposing the channel region and separated therefrom by a gate oxide; forming a control gate opposing the floating gate; and forming an asymmetrical low tunnel barrier intergate insulator by single layer deposition to separate the control gate from the floating gate, wherein forming the low tunnel barrier intergate insulator includes forming a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; wherein forming the floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator; and further comprising forming the metal layer of the same material as the asymmetrical low tunnel barrier intergate insulator.