Patent ID: 8125268

Claim:
A method of generating an output signal from differential input signals, comprising: converting the differential input signals into first and second full-differential signals using a first pair of differential amplifiers, the first pair of differential amplifiers including a first differential amplifier using differential FET transistors of a first type to receive the differential input signals, the differential FET transistors of the first type being connected in series with respective transistors of a second type that is different from the first type to produce the first full-differential signal, the first pair of differential amplifiers further including a second differential amplifier using differential FET transistors of the second type to receive the differential input signals, the differential FET transistors of the second type being connected in series with respective transistors of the first type to produce the second full-differential signal, the second full-differential signal being isolated from the first full-differential signal; applying said full-differential signals to a second pair of differential amplifiers to generate first and second differential outputs, the second pair of differential amplifiers including a third differential amplifier coupled between a first supply voltage and a second supply voltage and having differential FET transistors of the second type to which the first full-differential signal is applied, the differential FET transistors of the second type in the third differential amplifier being connected in series with respective transistors of the first type to generate the first differential output, the second pair of differential amplifiers further including a fourth differential amplifier coupled between the first supply voltage and the second supply voltage and having differential FET transistors of the first type to which the second full-differential signal is applied, the differential FET transistors of the first type in the fourth differential amplifier being connected in series with respective transistors of the second type to generate the second differential output; combining the first and second differential outputs to generate said output signal; generating a bias current; and supplying said bias current to said first and said second pair of differential amplifiers.