Patent ID: 8877619

Claim:
A method of manufacture of an integrated circuit, comprising the steps of: providing a substrate; fabricating at least a portion of first integrated structures in at least one first area of the substrate using a first process that includes forming at least one of a trench capacitor, at least a part of a flash memory cell structure, or a first shallow trench isolation structure; fabricating at least a portion of second integrated structures in at least one second area of the substrate, the fabricating of the portion of the second integrated structures comprising defining at least a first targeted dopant profile in the at least one second area and forming an epitaxial layer on the at least one second area, the first target dopant profile comprising a first section with a first doping concentration at a surface of the at least one second area defining a heavily doped screening layer and a second section below the first section with a second doping concentration less than the first doping concentration defining a well layer, wherein the fabrication of the portion of the second integrated structures includes using a second process that is at a reduced thermal budget compared with the first process; and completing the first and second integrated structures to form the integrated circuit.