Patent ID: 7120784

Claim:
In a processor that performs simultaneous multi-threading (SMT) and which includes branch processing logic that has at least one branch history table (BHT) and a predicted target address cache (count cache), a method for improving branch prediction within an SMT environment wit a first thread and a second thread sharing similar lower order addresses, the method comprising: updating said BHT and said count cache as unified arrays when said first thread and said second thread share a same code; and dynamically allocating a first contiguous half of said BHT and of said count cache to said first thread and a second contiguous half of said BHT and said count cache to said second thread, wherein the dynamically allocating to different contiguous halves is triggered only when said first tread and said second thread do not share the same code and wherein the BHT and count cache resume being updated as unified arrays when a next executed pair of threads shares the same code.