Patent ID: 8886696

Claim:
Digital signal processing (“DSP”) block circuitry comprising: first and second multiplier circuits; first circuitry for selectively shifting bit positions of output signals of the first multiplier circuit relative to bit positions of output signals of the second multiplier circuit; and first circuitry for selectively additively combining output signals of the first circuitry for selectively shifting and the second multiplier circuit, wherein the second multiplier circuit comprises: first and second sub-multiplier circuits; second circuitry for selectively shifting bit positions of output signals of the first sub-multiplier circuit relative to bit positions of output signals of the second sub-multiplier circuit; and second circuitry for additively combining output signals of the second circuitry for selectively shifting and the second sub-multiplier circuit; and wherein: said DSP block circuitry is part of a programmable integrated circuit device having general-purpose interconnect circuitry; said DSP clock circuitry further comprising: redundancy circuitry for selectably allowing outputs of each one of said first and second multiplier circuits to be routed to (1) another instance of said DSP block circuitry that is immediately adjacent to that DSP block circuitry, and (2) yet another instance of said DSP block circuitry that is not immediately adjacent to that DSP block circuitry, without using said general-purpose interconnect circuitry for said routing.