Patent ID: 8819509

Claim:
An integrated circuit comprising: a storing unit that retains data; and a tester that receives test information including a pair of address and data, and executes a write and read test on the storing unit based on the test information, the tester comprising: a first retain unit that retains, when first write data is written to a first write address in the storing unit based on the test information, the first write address and the first write data; a first generator that generates, based on the first write address retained in the first retain unit, a first read address used for reading first read data from the first read address in the storing unit simultaneously with writing second write data to a second write address in the storing unit based on the test information; and a second generator that generates, based on the first write data retained in the first retain unit, an expected value of the first read data that is read from the first read address in the storing unit.