Patent ID: 8890594

Claim:
A system for synchronizing a functional reset generated by a first chain of flip-flops that operate on a first clock signal, with a second chain of flip-flops that operate on a second clock signal, comprising: a first flip-flop having an input terminal for receiving a logic high signal, a clock terminal for receiving the second clock signal and a reset terminal for receiving a functional reset signal from the first chain of flip-flops, wherein the first flip-flop is reset when the functional reset signal is asserted; a second flip-flop having an input terminal connected to an output terminal of the first flip-flop and a clock terminal for receiving the second clock signal, wherein the second flip-flop generates a first logic low signal at an output terminal thereof, at a positive edge of the second clock signal; and a third flip-flop having an input terminal connected to the output terminal of the second flip-flop for receiving the logic low signal and a clock terminal for receiving the second clock signal, wherein the third flip-flop generates a second logic low signal at an output terminal thereof, at a positive edge of the second clock signal, wherein the output terminal of the third flip-flop is connected to reset terminals of the second chain of flip-flops for providing the second logic low signal thereto.