Patent ID: 8201055

Claim:
A semiconductor memory device comprising: a first cell array including a plurality of memory cells; a first sense amplifier circuit physically disposed adjacently to the first cell array on one side of a column direction of the first cell array and configured to read or write data of the memory cells in the first cell array; a second cell array physically disposed on one side of a row direction of the first cell array and including a plurality of memory cells; a second sense amplifier circuit physically disposed adjacently to the second cell array on the one side of the column direction of the second cell array and configured to read or write data of the memory cells in the second cell array; an input/output buffer configured to control input and external output of data; an ECC circuit physically disposed between the first cell array and the second cell array and configured to execute error processing of data read from the memory cells or written to the memory cells in the first cell array and the second cell array; a first data bus extending in the column direction and configured to transmit or receive data between the first sense amplifier circuit and the input/output buffer and between the ECC circuit and the input/output buffer; and a second data bus extending in the column direction and configured to transmit or receive data between the second sense amplifier circuit and the input/output buffer and between the ECC circuit and the input/output buffer, the first data bus and the second data bus being physically disposed between the first cell array and the second cell array, and the ECC circuit being physically disposed between the first data bus and the second data bus so that a longitudinal direction of the ECC circuit is in the column direction.