Patent ID: 7817771

Claim:
A shift register, comprising a plurality of stages, {S n }, n=1, 2, . . . , N, N being a positive integer, wherein each stage S n comprises: (a) a first input, IN 1 , for receiving one of a first clock signal, CK 1 , and a second clock signal, XCK 1 ; (b) a second input, IN 2 , for receiving a third clock signal, CK 2 , if the first input IN 1 receives the first clock signal CK 1 , or a fourth clock signal, XCK 2 , if the first input IN 1 receives the second clock signal XCK 1 ; (c) a third input, IN 3 , for receiving a supply voltage, VSS; (d) a fourth input, IN 4 ; (e) a fifth input, IN 5 ; (f) a sixth input, IN 6 ; (g) a seventh input, IN 7 ; (h) an eighth input, IN 8 ; (i) a first output, OUT 1 , for outputting an output signal, O n ; (j) a second output, OUT 2 , for outputting a pull-down signal, K n ; (k) a pull-up circuit electrically coupled between the first input IN 1 and the first output OUT 1 ; (l) a pull-up control circuit electrically coupled between the fifth inputs IN 5 and the pull-up circuit; (m) a first pull-down circuit electrically coupled to the pull-up circuit; (n) a first pull-down control circuit electrically coupled to the second input IN 2 , the second output OUT 2 , and the first pull-down circuit; (o) a second pull-down circuit electrically coupled to the fourth input IN 4 , the first pull-down control circuit and the pull-up circuit; and (p) a third pull-down circuit electrically coupled to the sixth input IN 6 , the second pull-down circuit and the pull-up circuit, wherein the plurality of stages {S n } is electrically coupled in serial such that the fourth input IN 4 of the n-th stage S n is electrically coupled to the second output OUT 2 of the (n−1)-th stage S n−1 , for receiving a corresponding pull-down output signal K n−1 therefrom, or the second output OUT 2 of the (n+1)-th stage S n+1 , for receiving a corresponding pull-down output signal K n+1 therefrom; the fifth input IN 5 of the n-th stage S n is electrically coupled to the first output OUT 1 of the (n−1)-th stage S n−1 , for receiving a corresponding output signal O n−1 therefrom; the sixth input IN 6 of the n-th stage S n is electrically coupled to the first output OUT 1 of the (n+1)-th stage S n+1 , for receiving a corresponding output signal O n+1 therefrom; the seventh input IN 7 of the n-th stage S n is electrically coupled to the first output OUT 1 of the (n+2)-th stage S n+2 , for receiving a corresponding output signal O n+2 therefrom; and the eighth input IN 8 of the n-th stage S n is electrically coupled to the first output OUT 1 of the (n−2)-th stage S n−2 , for receiving a corresponding output signal O n−2 therefrom.