Patent ID: 8468335

Claim:
A reconfigurable data processing platform, comprising: a reconfigurable universal data processing module containing a plurality of basic units each capable of being configured to perform a unit of at least one of a logic operation and an arithmetic operation; a configuration memory coupled to the reconfigurable universal data processing module to provide configuration information to be used to configure the plurality of basic units; and a reconfiguration control unit coupled to the reconfigurable universal data processing module and the configuration memory to provide control signals for configuration of the plurality of basic units, wherein a basic unit includes: a first multiplexer configured to selectively accept a first set of inputs and to output a one-bit first multiplexer output; a second multiplexer configured to selectively accept a second set of inputs and to output a one-bit second multiplexer output; a third multiplexer configured to selective accept a third set of inputs and to output a one-bit third multiplexer output; a carry logic coupled to the first multiplexer output, the second multiplexer output, and the third multiplexer output and to generate a one-bit carry output; and a sum logic coupled to the first multiplexer output, the second multiplexer output, and the third multiplexer output and to generate a one-bit sum output.