Patent ID: 7811866

Claim:
A method for forming an integrated circuit structure, the method comprising: providing a substrate; forming an interconnection structure over the substrate; forming a metal layer over and electrically connected to a top metallization layer of the interconnection structure; forming an anti-reflective coating (ARC) on the metal layer; patterning the ARC and the metal layer, wherein portions of the metal layer form a fusible fuse link and a bond pad by the step of patterning the ARC and the metal layer, and wherein remaining portions of the ARC comprise a first portion directly over the fusible fuse link and a second portion directly over the bond pad; blanket forming a dielectric layer; removing portions of the dielectric layer to expose the first portion and the second portion of the ARC; and performing a removal step to remove the second portion of the ARC to expose a top surface of the bond pad, wherein the first portion of the ARC is not removed by the removal step, and remains over the fusible fuse link.