Patent ID: 7592676

Claim:
A cell in a semiconductor device, comprising a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region and a second impurity diffusion region such that the first impurity diffusion region and the second impurity diffusion region are provided side-by-side in a gate length direction with a device isolation region interposed therebetween, wherein in at least one of the diffusion region pairs, the first impurity diffusion region forms part of a first transistor, and the second impurity diffusion region forms part of a second transistor, said second transistor having a gate width different in length from a gate width of the first transistor, and said first transistor includes a third impurity diffusion region, an edge of the first impurity diffusion region and an edge of the second impurity diffusion region, which are adjacent to one another, have an equal length in a gate width direction, and said length of said edge of the first impurity diffusion region in the gate width direction is different from a length of an edge of the third impurity diffusion region in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first impurity diffusion region and the second impurity diffusion region, has a separation length in the gate length direction equal to a separation length in the gate length direction of a first impurity diffusion region and a second impurity diffusion region of another one of the diffusion region pairs.