Patent ID: 7826291

Claim:
A precharge and evaluation circuit for a memory sense amplifier comprising: a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain; a second precharge-phase transistor having a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit; a first read-phase transistor having a source coupled to the power-supply potential, and a gate and drain coupled to a comparator; a second read-phase transistor having a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit; and a column decoder coupled to the sources of the second precharge-phase and second read-phase transistors.