Patent ID: 7868370

Claim:
A nonvolatile memory integrated circuit, comprising: a semiconductor substrate; a nonvolatile memory device on the semiconductor substrate, including: a transistor on the semiconductor substrate controlled by a gate region and by a source region and a drain region having a first doping type, comprising: first doping regions having the first doping type, the first doping regions positioned on both sides of the gate region, the first doping regions overlapping the source region and the drain region; second doping regions having a second doping type opposite to the first doping type, the second doping regions positioned on both sides of the gate region, the second doping regions overlapping the source region and the drain region; third doping regions having the first doping type, the third doping regions positioned on both sides of the gate region, the third doping regions overlapping the source region and the drain region; fourth doping regions having the first doping type, the fourth doping regions positioned on both sides of the gate region, the fourth doping regions defining the source region and the drain region; a capacitor on the semiconductor substrate controlled by a gate region; a shared floating gate connected to the gate region of the transistor and the gate region of the capacitor.