Patent ID: 7421619

Claim:
A method for performing in-memory hardware tracing using an existing first system bus in a data processing system, said data processing system including a first processor that includes a first plurality of processing units coupled together utilizing said first system bus, said first plurality of processing units including a first memory controller coupled to the first system bus that controls a first system memory, said data processing system also including a second processor that includes a second plurality of processing units coupled together utilizing a second system bus, said second plurality of processing units including a second memory controller coupled to the second system bus that controls a second system memory, said method comprising: transmitting information among said first and second plurality of processing units utilizing said first and second system buses when said first and second processors are in a normal, non-tracing mode, said information being formatted according to a standard system bus protocol, wherein said first and second system buses are coupled together; selecting a trace that generates hardware trace data, said trace being a particular type; determining a bandwidth for said particular type; determining a number of a plurality of write buffers that are needed in order to accommodate said bandwith; dynamically allocating said number of said plurality of write buffers to a hardware trace facility for storing said hardware trace data, wherein said plurality of write buffers are in said second processor and are external to said second system memory, wherein said plurality of write buffers are connected directly to said second system bus, and further wherein said second memory controller is connected directly to said second system bus and controls said plurality of write buffers, and still further wherein said hardware trace data is written from said ones of said plurality of write buffers to said second system memory without said hardware trace data being transmitted through another device; capturing said hardware trace data utilizing said hardware trace facility that is located in said first processor and that is connected directly to said first system bus, wherein information is transmitted directly between said hardware trace facility and said first system bus without being transmitted through another device; and transmitting, utilizing said first system bus, said hardware trace data to said second memory controller for storage in said second system memory, said second memory controller being coupled directly to said second system bus, said hardware trace data being formatted according to said standard system bus protocol for transmission via said second system bus.