Patent ID: 7736972

Claim:
A method of forming a storage electrode of a semiconductor memory device, the method comprising the steps of: forming an interlayer dielectric layer over a semiconductor substrate where a bit line and a contact pad connected to the semiconductor substrate are formed on the semiconductor substrate; patterning the interlayer dielectric layer to form a contact hole exposing the contact pad; forming a polysilicon layer on the resulting surface and within the contact hole; forming a storage node contact having a planarized surface in the contact hole by sequentially performing a first etching process for etching the polysilicon layer to a predetermined thickness, a second etching process for over-etching the polysilicon layer, and a third etching process for planarizing a surface of the polysilicon layer, wherein the first, second and third etching processes are performed in-situ in one chamber; forming a mold insulating layer which exposes an area where the storage node contact is formed; and forming a storage electrode coupled to the storage node contact.