Patent ID: 7477535

Claim:
Chip arrangement, comprising: a base substrate; at least one logic die located on the base substrate and comprising at least one subsystem; at least one memory die comprising at least one memory module; a memory management unit; a first data interface connecting the memory management unit with the at least one logic die; a second data interface connecting the memory management unit with the at least one memory die; a configuration interface connecting the memory management unit with the at least one memory die, the configuration interface comprising face-to-face connections; and a control interface connecting the memory management unit with the at least one logic die; wherein said at least one memory die and said at least one logic die are arranged in a stacked configuration on said base substrate, and wherein said memory management unit is adapted for managing memory accesses from said at least one subsystem by negotiating an allowed memory access with the at least one subsystem via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.