Patent ID: 8219761

Claim:
A device comprising: a plurality of processors, each processor coupled to a corresponding one of a plurality of level-one caches; and a multi-port high-level cache unit comprising: a plurality of paths, including at least two concurrently accessible interleaved cache paths and at least one non-cacheable path; a first modular interconnect comprising a plurality of splitters, a plurality of arbiter/multiplexors, and a plurality of expanders, wherein: each splitter of the plurality of splitters includes an output connected to an input of a corresponding one path of the plurality of paths and an input connected to a corresponding one arbiter/multiplexor of the plurality of arbiter/multiplexors, each splitter to receive information retrieval requests and to convert each request into one or more cache accesses based on request attributes associated with each request; each arbiter/multiplexer of the plurality of arbiter/multiplexors includes a plurality of inputs, each input of the plurality of inputs connected to an output of a corresponding one expander of the plurality of expanders, each arbiter/multiplexor to provide an information retrieval start indication and to receive an information retrieval acknowledgement signal from an associated splitter; and each expander of the plurality of expanders includes an input connected to a corresponding one of the plurality of processors, each expander to receive information retrieval requests from the corresponding one processor and to provide priority upgrading of the information retrieval requests; a second modular interconnect including a plurality of inputs, each input connected to an output of a respective one of the plurality of paths; a memory controller connected to an output of the second modular interconnect; and a memory connected to the memory controller.