Patent ID: 7098514

Claim:
A highly integrated semiconductor device comprising: a semiconductor substrate; a gate electrode disposed on a predetermined portion of the semiconductor substrate; an epitaxial layer formed on the semiconductor substrate on both sides of the gate electrode to overlap the gate electrode to a predetermined depth; a source region and a drain region formed in the epitaxial layer and predetermined upper portions of the semiconductor substrate below the epitaxial layer, wherein each of the source region and the drain region includes a lightly doped drain region adjacent to the sidewalls of the gate electrode and a heavily doped region formed beside the lightly doped drain region; an offset spacer formed between the sidewalls of the gate electrode and the lightly doped drain region to insulate the gate electrode from the source region and the drain region; and a silicide layer formed on the gate electrode, the source region, and the drain region, wherein the silicide layer is in contact with the lightly doped drain region and the heavily doped region of each of the source region and the drain region.