Patent ID: 8656376

Claim:
A method for providing intrinsic supports for a digital signal processing (DSP) processor with very long instruction word (VLIW) architectures and distributed register files, the DSP processor comprising a plurality of clusters, each cluster comprising a plurality of functional units, a plurality of local register files connected to one of the plurality of functional units, and at least one global register file, each of the at least one global register files comprising a plurality of global banks connected to one of the plurality of functional units, the method comprising the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations, wherein the step of performing register allocation comprises a sub-step of: performing register bank assignment for the plurality of local register files and the at least one global register file; performing data replication for paralleling accessing; and performing physical register assignment.