Patent ID: 8877581

Claim:
A method of fabricating an integrated circuit (IC) including a plurality of strained metal oxide semiconductor (MOS) devices, comprising: providing a substrate having a semiconductor surface that has a first doping type; forming a gate electrode stack over a portion of said semiconductor surface; etching to form source/drain recesses that extend into said semiconductor surface to form recesses on opposing sides of said gate electrode stack, wherein said source/drain recesses are framed by semiconductor surface interface regions; epitaxially depositing a first strained alloy layer including a strain inducing alloy element on said semiconductor surface interface regions in the source/drain recesses, wherein said first strained alloy layer is doped with said first doping type, and epitaxially depositing a second strained alloy layer including a strain inducing alloy element on said first strain layer in the source/drain recesses, wherein said second strained alloy layer is undoped or is doped with a second doping type that is opposite to said first doping type.