Patent ID: 7149269

Claim:
A receiver for clock and data recovery, comprising n sampling latches (SL 1 . . . SLn) for determining n sample values (SV 1 . . . SVn) of a reference signal (Ref 2 ) at n sampling phases (j 1 a . . . jna), having sampling latch inputs and sampling latch outputs, a phase position analyzer ( 5 ) connected to said sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (j 1 a . . . jna), if the sample value (SV 1 . . . SVn) deviates from a set point, a phase interpolator ( 9 ) for generating sampling phases (j 1 u . . . jnu), a sampling phase adjusting unit ( 6 ) connected with its inputs to the phase position analyzer ( 5 ) and the phase interpolator ( 9 ) and with its outputs to the sampling latches (SL 1 . . . SLn) for generating adjusted sampling phases (j 1 a . . . jna) depending on said sampling phases (j 1 u . . . jnu) and said adjusting signal (AS), a sample memory ( 4 ) for storing the sampled values (SV 1 . . . SVn) and connected between the sample latches (SL 1 . . . SLn) and the phase position analyzer ( 5 ), a data output (OUT) for delivering parallel data (DP) and connected to the sample memory ( 4 ), and an edge detection unit ( 8 ) for detecting edges in a serial data signal (DS) and connected between the sample memory ( 4 ) and a control input of the phase interpolator ( 9 ).