Patent ID: 7361950

Claim:
A Metal Insulator-Metal (MIM) capacitor formed on a semiconductor substrate comprising: a base comprising a semiconductor substrate having a top surface; a lower capacitor plate selected from the group consisting of: a silicide layer formed on a polysilicon layer formed on said top surface on an isolation region formed in said semiconductor substrate; a doped region formed in said top surface of said semiconductor substrate, with said doped region having an upper exterior surface coplanar with said semiconductor substrate; and a doped region formed in said top surface of said semiconductor substrate, with said doped region having a silicide region formed therein with an upper exterior surface coplanar with said semiconductor substrate; a capacitor High K (HiK) dielectric layer formed on said MIM capacitor lower plate, with said HiK dielectric layer consisting of a material selected from the group consisting of Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , and Al 2 O 3 ; a second capacitor plate formed on said capacitor HiK dielectric layer above said lower capacitor plate with said capacitor HiK dielectric layer and said second capacitor plate being narrower than said lower capacitor plate thereby leaving a surface of said lower capacitor plate exposed; said second capacitor plate being covered by either an etch stop layer alone or the combination of a second HiK dielectric layer, a third capacitor plate and an etch stop layer; a first set of vias extending through said etch stop layer formed in contact with said second capacitor plate; and a second set of vias formed in contact with said MIM lower capacitor plate aside from said capacitor HiK dielectric layer and said second capacitor plate.