Patent ID: 8680602

Claim:
A semiconductor device, comprising: a substrate including a first region and a second region; a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern; a first gate pattern disposed in the second region of the substrate; a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point; and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point, wherein the first inflection point is spaced apart from the gate group and the second inflection point is spaced apart from the first gate pattern, wherein a width of the group spacer decreases toward the first inflection point from the substrate and a width of the first pattern spacer decreases toward the second inflection point from the substrate, and wherein the gate group includes a plurality of air gaps disposed between the plurality of cell gate patterns and between the plurality of cell gate patterns and the at least one selection gate pattern.