Patent ID: 8667046

Claim:
A device for adding single or multiple columns of multi-bit first operands, the device comprising: an input configuration circuit adapted to receive said multi-bit first operands and output multi-bit second operands by zeroing one or more selected bits of at least one of said multi-bit first operands regardless of value of said one or more selected bits to eliminate said one or more selected bits; a configurable general parallel counter adapted to receive, from the input configuration circuit, said multi-bit second operands and output multi-bit third operands by altering one or more bits of said multi-bit second operands to be interpreted as belonging to a different rank, said input configuration circuit and said configurable general parallel counter working together to effect a summation of a subset of multiple ranks and a subset of bits within said ranks; a plurality of parallel counters each receiving, from the configurable general parallel counter, one or more said multi-bit third operands, said parallel counters arranged to compress said multi-bit third operands into a pair of resulting operands; and an adder adapted to receive and sum said resulting operands from the plurality of parallel counters and provide an adder output, the adder output comprising a sum for said single or multiple columns of the multi-bit first operands.