Patent ID: 7526595

Claim:
A method for writing to a memory slave on a target bus, comprising: initiating a write, the write requiring data processing, by a system master coupled to a first bus, the first bus coupled to an arbiter; receiving data from the system master by a data processing slave coupled to a second bus, the second bus coupled to the arbiter, wherein the data processing slave receives only data to be processed from the system master and transmits processed data to the system master wherein the data to be processed and the processed data is passed through the arbiter; transmitting by the data processing slave data to a data processing core; processing by the data processing core of the data; transmitting by the data processing core processed data to a data processing master coupled to the first bus; and transmitting by the data processing master processed data to the memory slave, wherein the data processing master receives only data to be processed from the memory slave and transmits processed data to the memory slave, wherein the data to be processed and the processed data is passed through the arbiter.