Patent ID: 7131055

Claim:
A decoding circuit, comprising: a first adder having a first state input, a first branch input, and a first adder output, the first adder adding the first state input and the first branch input to generate the first adder output; a second adder having a second state input, a second branch input, and a second adder output, the second adder adding the second state input and the second branch input to generate the second adder output; a comparator having a first adder input, a second adder input, and a comparator output, the comparator comparing the first adder input and the second adder input to generate the comparator output; a multiplexer having a first multiplexer input, a second multiplexer input, a select input, and a multiplexer output, the multiplexer selecting one of the first multiplexer input and the second multiplexer input based on the select input to generate the multiplexer output; a storage unit coupled to the multiplexer output, the storage unit storing the multiplexer output; and an inverter coupled between the second adder output and the second multiplexer input, the inverter inverting the second adder output.