Patent ID: 7590008

Claim:
A memory interface comprising: a clock output circuit to provide a first clock signal to a memory device; a write path to write data to the memory device, the write path comprising: a DQS output circuit comprising first and second flip-flops clocked by a second clock signal, and a first delay element to provide a first delay for a DQS output signal, where the second clock signal and the first delay are calibrated such that the first clock signal and DQS output signal are received in close temporal proximity at the memory device; and a DQ output circuit comprising a second delay element to provide a second delay for a DQ output signal, where the second delay is calibrated such that the DQ output signal is accurately received by the memory device; and a read path to read data from the memory device, the read path comprising: a DQS input circuit comprising a third delay element to provide a third delay for a DQS input signal; and a DQ input circuit comprising a fourth delay element to provide a fourth delay for a DQ input signal, an input register clocked by an output of the DQS input circuit, a resync register clocked by a third clock signal, and an internally clocked register, where the third delay and fourth delay are calibrated such that the DQ input signal is accurately received by the input register, and the second clock signal is calibrated such that data is accurately transferred from the input register to the internally clocked register.