Patent ID: 8286054

Claim:
A semiconductor memory, comprising: a plurality of regular memory cells to hold regular data written therein; a regular data control circuit to input or output the regular data to or from the regular memory cells; a parity memory cell to hold parity data of the regular data; a parity data control circuit to input or output the parity data to or from the parity memory cell; an error correction unit, coupled to the regular data control circuit and the parity data control circuit, to detect and correct an error of the regular data read from the regular memory cells using the regular data read from the regular memory cells and the parity data read from the parity memory cell in a write operation, to generate replaced regular data by replacing a part of corrected regular data with write data, to generate a parity write data using the replaced regular data, and to write the parity write data into the parity memory cell; and an access control circuit to generate regular access control signals to control the regular memory cells and the regular data control circuit to read the regular data from the regular memory cells and write the regular data into the regular memory cells when write commands are supplied, to generate parity access control signals to control the parity memory cell and the parity data control circuit to start a read of the parity data from the parity memory cell after the regular data starts to be read from the regular memory cells and during the read of the regular data, and to generate the regular access control signals to read the regular data from the regular memory cells in response to a following write command during the parity write data to be written into the parity memory cell is supplied to the parity memory cell.