Patent ID: 7170962

Claim:
A clock alignment circuit comprising: an input for receiving a first clock signal; an input for receiving a second clock signal having a period N times that of the first clock signal, N being an integer greater than or equal to two; an output for outputting a third clock signal also having a period N times that of the first clock signal; phase comparison means for providing an indication of whether the closest edge of a particular kind of the first clock signal to an edge of a particular kind of the second clock signal is earlier or later than that edge, the kinds of edges being positive going or negative going and the ones of the first and second clock signals being of the same kind or of different kinds; and third clock signal providing means, for providing the third clock signal from the second clock signal, comprising latching means, for latching the second clock signal, operable to latch and delay the second clock signal by such an amount, dependent on the indication from the phase comparison means, that the resulting third clock signal has an edge, either positive or negative going, aligned with the closest edge of the first clock signal.