Patent ID: 7821053

Claim:
An integrated structure comprising: a capacitor comprising: a semiconductor layer having doped end regions and a center region positioned laterally between said doped end regions, said center region further having a first surface, and a second surface opposite said first surface; and opposing gates on said first surface and said second surface adjacent to said center region, said opposing gates comprising: a first gate comprising a first gate dielectric layer on said first surface and a first gate conductor layer on said first gate dielectric layer; and a second gate comprising a second gate dielectric layer on said second surface and a second gate conductor layer on said second gate dielectric layer; a voltage source; and a device comprising any one of a digital-to-analog converter, a resistor and an inductor, said device being electrically connected in series between said voltage source and one of said doped end regions of said capacitor, wherein, in order to tune said capacitor, said device allows an amount of voltage applied by said voltage source to said one of said doped regions to alternate between a first voltage value that is above a predetermined threshold voltage value for both said opposing gates and a second voltage value that is below said predetermined threshold voltage value, said first voltage value configuring, within said capacitor, said first gate conductor layer and said second gate conductor layer as capacitor plates and, in combination, said first dielectric layer, said second dielectric layer and said semiconductor layer function as a single capacitor dielectric between said capacitor plates and said second voltage value configuring, within said capacitor, said first gate conductor layer as a first capacitor plate, said second gate conductor layer as a second capacitor plate, said semiconductor layer as an additional capacitor plate, said first gate dielectric layer as a first capacitor dielectric between said first capacitor plate and said additional capacitor plate and said second gate dielectric layer as a second capacitor dielectric between said additional capacitor plate and said second capacitor plate.