Patent ID: 8508970

Claim:
A method for biasing a direct injection semiconductor memory device comprising the steps of: applying a first voltage potential to a first N-doped region via a bit line; applying a second voltage potential to a second N-doped region via a source line; applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region, wherein the first N-doped region, the body region, and the second N-doped region form a bipolar transistor; and applying a fourth voltage potential to a P-type substrate via a carrier injection line; wherein the bit line extends from the first N-doped region in a direction that is perpendicular to a direction of at least a portion of at least one of the source line, the word line, and the carrier injection line.