Patent ID: 7679136

Claim:
A semiconductor device having a field-effect transistor with a trench gate structure on a semiconductor substrate, the semiconductor substrate having a first main surface and a second main surface on the reverse side thereof, the field-effect transistor with a trench gate structure comprising: a source region of first conductivity type, provided on the first main surface of the semiconductor substrate; a drain region of the first conductivity type, provided on the second main surface of the semiconductor substrate; a channel forming region provided between the source region and the drain region of the semiconductor substrate; a first trench that extends in a direction orthogonal to the first main surface of the semiconductor substrate so that the first trench extends from the first main surface of the semiconductor substrate, penetrates the source region and the channel forming region, and is terminated at the drain region; a gate insulating layer formed in the first trench; a gate electrode provided in the first trench via the gate insulating layer; an interlayer insulating layer provided over the gate electrode; and a source electrode that is provided over the first main surface of the semiconductor substrate with the interlayer insulating layer in-between, and is brought into contact with and electrically connected with the upper face of the source region, exposed from the interlayer insulating layer, wherein the upper face of the gate electrode is formed at a level lower than the first main surface of the semiconductor substrate, wherein the first main surface of the semiconductor substrate is formed with a second trench which extends in a direction orthogonal to the first main surface of the semiconductor substrate so that the second trench extends from the upper face of the source region, exposed from the interlayer insulating layer, wherein the second trench penetrates the source region, and is terminated at the channel forming region, wherein, letting the distance, wherein the upper face of the source region is exposed from the interlayer insulating film, between an end of the interlayer insulating layer over the upper face of the source region and an edge of the second trench, adjacent to said end of the interlayer insulating layer, be “a” and letting the length of the overlap between the interlayer insulating layer and the upper face of the source region be “b”, b≦a, wherein the source electrode is formed in the second trench; and wherein the source electrode is brought into contact with and electrically connected with the source region and the channel forming region through the second trench.