Patent ID: 8060708

Claim:
A method comprising: receiving, at a first interface of a circuit, a first volatile memory read request from a first processor coupled with the circuit and satisfying the first volatile memory read request through accessing SDRAM of the circuit, the SDRAM configured to be coupled with an SDRAM controller of the circuit; receiving, at the first interface, a first nonvolatile memory read request from the first processor and satisfying the first nonvolatile read request through accessing the SDRAM and NAND flash memory of the circuit, the NAND flash memory configured to be coupled with a NAND flash memory controller of the circuit; receiving, at a second interface of the circuit, a second volatile memory read request from a second processor coupled with the circuit and satisfying the second volatile memory read request through accessing the SDRAM; receiving, at a third interface of the circuit, a second nonvolatile memory read request from the second processor and satisfying the second nonvolatile memory read request through accessing the NAND flash memory; and carrying out interprocessor communication between the first processor and the second processor utilizing a dual port random access memory (RAM) of the circuit, the dual port RAM comprising an addressable memory location accessible to the first processor and the second processor, the first nonvolatile memory read request comprising NOR flash memory access signals, and the first volatile memory read request comprising static random access memory (SRAM) access signals.