Patent ID: 7449964

Claim:
A high speed bit stream data conversion circuit comprising: a data conversion circuit operable to: receive a plurality of first bit streams at a first bit rate and a corresponding first bit stream data clock; and produce at least one second bit stream at a second bit rate, wherein: the number of the plurality of first bit streams is greater than the number of the at least one second bit stream(s), the bit rate of the at least one second bit stream(s) is greater than the bit rate of the plurality of first bit stream(s), wherein the data conversion circuit comprises: a plurality of drivers used to drive signals based upon the plurality of first bit streams and/or the first bit stream data clock; and a clock circuit operable to: produce a Reference Clock Signal based upon the first bit stream data clock, wherein the Reference Clock Signal is operable to latch the plurality of first bit streams; and wherein the clock circuit comprises: a phase locked loop (PLL) having a phase detector operable to receive the first bit stream data clock and a loop output; a charge pump; a loop filter; a Voltage Controlled Oscillator (VCO); and a divider operable to produce the loop output; wherein the VCO is tuned at an operating frequency corresponding to at least one tuning setting; and wherein at least some of the plurality of drivers is tuned based upon the at least one tuning setting.