Patent ID: 8433855

Claim:
A method of synchronizing translation changes in a processor comprising a translation lookaside buffer (TLB) and a control register having translation related control bits configurable as architectural states, the method comprising: notifying an instruction cache by an instruction decode unit to start blocking of all fetch requests that miss the TLB based on decoding an instruction for initiation of a block translation state, the instruction configured to set a control bit to enable the blocking; notifying an instruction issue unit by the instruction decode unit of the initiation; based on the notifying of the initiation, stopping issuing of instructions by the instruction issue unit until all pending TLB misses have been processed; waiting for completion of all pending TLB misses to be processed by the processor; setting the control bit to enable the blocking of all fetch requests that miss the TLB, the setting performed by the processor without changing a translation state of a current process, the setting of the control bit directly performed by execution of at least one of software and firmware; based on the control bit being set, servicing incoming fetch requests by the processor that do not miss the TLB and preventing launching of TLB miss updates, the servicing of incoming fetch requests configured to service incoming fetch requests received subsequent to a blocked fetch request that misses the TLB; updating an architectural state by the processor to change a state of one or more of the translation related control bits while the control bit is set to enable the blocking of all fetch requests that miss the TLB, wherein illegal results of translations being installed in the TLB based on changing translation related fields are avoided; and resetting the control bit by the processor based on completion of the updating and dropping the block translation state by the instruction decode unit based on executing a reset block translation instruction, thereby disabling the blocking of all fetch requests that miss the TLB.