Patent ID: 8710553

Claim:
An integrated circuit comprising: a substrate comprising a plurality of diffusion lines, wherein the plurality of diffusion lines include impurities diffused into the substrate; a signal line layer comprising a first plurality of signal lines; a first metal layer comprising a second plurality of signal lines, wherein the second plurality of signal lines include a first metallic material; a second metal layer comprising a third plurality of signal lines, wherein the third plurality of signal lines include a second metallic material; a first plurality of contacts connecting the plurality of diffusion lines to (i) a first set of the second plurality of signal lines, or (ii) a first set of the third plurality of signal lines; and a second plurality of contacts connecting a first set of the first plurality of signal lines to a second set of the third plurality of signal lines, wherein each signal line in a first set of the second plurality of signal lines comprises first portions and second portions, wherein the first portions extend towards and are not connected to the second plurality of contacts, and wherein the first portions are not parallel to the second portions.