Patent ID: 7460396

Claim:
A semiconductor device, comprising: a semiconductor substrate having a first main surface and, on the back side thereof, a second main surface; a main circuit formation region placed over the first main surface of the semiconductor substrate; and a nonvolatile memory region placed over the first main surface of the semiconductor substrate, the nonvolatile memory region being equipped with: a first well having a first conductivity type and formed over the main surface of the semiconductor substrate; a second well having a second conductivity type, which type is opposite to the first conductivity type, and placed to be enclosed in the first well; a third well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well, and to be enclosed in the first well; a fourth well having the second conductivity type and placed to extend along the second well while being electrically separated from the second well and the third well, and to be enclosed in the first well; and a nonvolatile memory cell placed to two-dimensionally overlap with the second well, the third well and the fourth well, the nonvolatile memory cell being equipped with: a floating gate electrode placed to extend in a first direction so as to two-dimensionally overlap with the second well, the third well and the fourth well; an element for programming and erasing data formed at a first position where the floating gate electrode two-dimensionally overlaps with the second well; a field effect transistor for reading data formed at a second position where the floating gate electrode two-dimensionally overlaps with the third well; and a capacitor element formed at a third position where the floating gate electrode two-dimensionally overlaps with the fourth well, the element for programming and erasing data being equipped with: a first electrode formed at the first position of the floating gate electrode; a first insulating film formed between the first electrode and the semiconductor substrate; a pair of second-conductivity type semiconductor regions formed in the second well at a position where the first electrode is sandwiched therebetween; and the second well, the field effect transistor for reading data being equipped with: a second electrode formed at the second position of the floating gate electrode; a second insulating film formed between the second electrode and the semiconductor substrate; and a pair of first-conductivity-type semiconductor regions formed in the third well at a position where the second electrode is sandwiched therebetween, and the capacitor element being equipped with: a third electrode formed at the third position of the floating gate electrode; a third insulating film formed between the third electrode and the semiconductor substrate; a pair of second-conductivity-type semiconductor regions formed in the fourth well at a position where the third electrode is sandwiched therebetween; and the fourth well.