Patent ID: 8441241

Claim:
A system, comprising: a first resistor divider to reduce an input voltage by a first amount; a second resistor divider to reduce a reference voltage by second amount that is greater than the first amount; and a comparator system to receive the reduced input voltage, the reference voltage, and the reduced reference voltage, and to output a digital error indication of the reduced input voltage relative to a first range defined by the reference voltage and the reduced reference voltage, wherein the digital error indication is representative of an error of the input voltage relative to a second range centered substantially about the reference voltage, wherein the system further includes a plurality of additional first resistor dividers, each to reduce a corresponding additional input voltage, a parallel resistor network to receive the input voltages and to output an instantaneous average of the input voltages as the reference voltage, and a plurality of additional comparator systems, each to receive a corresponding one of the additional reduced input voltages, the reference voltage, and the reduced reference voltage, and to output a corresponding digital error indication.