Patent ID: 7888208

Claim:
A method of fabricating a non-volatile memory device, the method comprising: forming a tunnel insulating layer, a floating gate, and a pad nitride layer on a semiconductor substrate; forming a trench for device isolation by etching a device isolation region of the semiconductor substrate to a predetermined depth; forming a liner insulating layer on a resulting surface of the semiconducter substrate including the trench; filling the trench with an insulation layer on the liner insulating layer to form an isolation layer; performing a first etching process on the isolation layer and the liner insulating layer; recessing the isolation layer and the liner insulating layer by a second etching process, wherein the top surface of the recessed isolation layer is disposed below the surface of the semiconductor substrate; forming a capping layer on a surface of the result formed by the second etching process including the recessed isolation layer and liner insulating layer; and forming a first capping layer at a surface of the isolation layer and a second capping layer at both sidewalls of the floating gate by performing a third etching process on the capping layer.