Patent ID: 7545023

Claim:
A semiconductor transistor comprising: a substrate; a gate insulating layer positioned on the surface of the substrate; a gate positioned on the gate insulating layer; a channel region positioned in the substrate corresponding to the gate; and a source region and a drain region respectively positioned alongside the channel region, the source region and the drain region including a first material and a second material, the first material and the second material having a same lattice structure and different spacing, both the source region and the drain region comprising a main region and a peripheral region, wherein the main region of the source region comprises the first material and the second material, the main region of the drain region comprises the first material and the second material, a percentage of the second material in the main region of the source region and a percentage of the second material in the main region of the drain region are constant, and a percentage of the second material in the peripheral region of the source region and a percentage of the second material in the peripheral region of the drain region are graded, and wherein the peripheral region of the source region surrounds a bottom portion of the main region of the source region, and the peripheral region of the drain region surrounds a bottom portion of the main region of the drain region.