Patent ID: 7936013

Claim:
A vertically-conducting charge balance semiconductor power device, comprising: an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state; a non-active perimeter region surrounding the active area, wherein no current flows along the vertical dimension through the non-active perimeter region when the plurality of cells are biased in the conducting state; and strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p pillars having a depth extending along the vertical dimension, a width, and a length, the strips of p and n pillars extending through both the active area and the non-active perimeter region along a length of a die containing the semiconductor power device, the length of the die extending parallel to the length of the strips of p pillars, each of the strips of p pillars including a plurality of discontinuities forming portions of a plurality of strips of n regions, the plurality of strips of n regions extending adjacent to ends of the strips of p pillars in the non-active perimeter region perpendicular to the length of the die.