Patent ID: 8643068

Claim:
An integrated circuit, comprising: a first FET and a second FET, wherein the first FET is a power FET and the second FET is a sense FET having an area that is smaller than the area of the power FET, wherein at least one of a source, drain, or gate of the first FET is electrically connected to the corresponding one of a source, drain, or gate of the second FET, at least one further of the source, drain, or gate of the first FET and the corresponding one further of the source, drain, or gate of the second FET are connected to a circuit element, respectively; and a dopant concentration profile of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel, wherein a value of the dopant concentration profile of the body at the peak location of each of the first and second FETs is larger or at least equal to any value of the dopant concentration profile of the body in an extension region that extends into the source, wherein the dopant concentration profile of the body of the first FET and the dopant concentration profile of the body of the second FET follow substantially similar contours along the channel of the first and second FETs respectively.