Patent ID: 8558386

Claim:
A method of making a semiconductor chip package comprising: (a) providing a compliant layer over a first portion of a contact bearing face of a semiconductor chip, said compliant layer having a bottom surface adjacent the contact bearing face, a top surface facing away from the bottom surface, and at least one sloping surface between the top surface and the bottom surface, the compliant layer being spaced apart in a direction along the contact bearing face from at least one contact adjacent to the sloping surface and the compliant layer having a low modulus of elasticity; and (b) forming bond ribbons of conductive material deposited onto the compliant layer, and onto portions of the semiconductor chip between the compliant layer and the at least one contact, wherein each said bond ribbon electrically connects one of said contacts to an associated conductive terminal at said top surface of said compliant layer, wherein each of at least some of said bond ribbons is electrically connected to a respective contact of said contacts and includes a strip extending along said sloping surface of said compliant layer, said strips being spaced apart from one another on said sloping surface from said bottom surface to said top surface.