Patent ID: 7772066

Claim:
A method for fabricating a pair of vertical tunneling, ultra-thin body transistors on a substrate, the method comprising: forming an oxide pillar on the substrate surface; forming an amorphous silicon layer over the substrate surface and the pillar such that the amorphous silicon layer, on opposing sides of the pillar, forms ultra-thin silicon bodies; doping a p+ region into the substrate on a first side of the pillar and a first portion of the amorphous silicon layer on top of a second side of the pillar; doping an n+ region into a second portion of the amorphous silicon layer on top of the first side of the pillar and a region of the substrate on the second side of the pillar; forming an n-well in the substrate on the first side of the pillar such that the p+ region in the substrate resides in the n-well and the n+ region on the second side of the pillar does not reside in the n-well; forming a gate insulator over the amorphous silicon layer; and forming a gate structure over the gate insulator on each side of the pillar.