Patent ID: 7650585

Claim:
A processor-implemented method for generating an implementation of an electronic circuit design, the method comprising: compiling a first portion of the design into software that is executable by a hard processor disposed on a single semiconductor chip with resources of a programmable logic device (PLD); generating a first synthesized version of a hardware portion of the design, wherein the first synthesized version includes logic to be implemented on programmable logic and interconnect resources of the PLD and a memory to be implemented with random access memory (RAM) resources of the PLD; generating a synthesized memory scrubber having an empty block for an address counter; generating a synthesized triple modular redundant address counter; replacing the memory in the first synthesized version of the hardware portion of the design with the synthesized memory scrubber; generating a complete set of netlists including a triple modular redundant hardware portion of the design from the first synthesized version of the hardware portion of the design and a single instance of the synthesized memory scrubber; and generating and storing a configuration bitstream from the complete set of netlists.