Patent ID: 8817550

Claim:
A semiconductor device comprising: a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; power circuitry that provides power to the device upon power up, the power circuitry comprising a first power up circuit that outputs a first power up signal and a second power up circuit that outputs a second power-up signal; and an output buffer that outputs data from the memory cells or act output buffer pad sourced data selectively by a first control signal, wherein the output buffer includes level shifting circuitry comprising: a pull-up level shift circuit comprising a first cross-coupled pair of transistors and first circuitry coupled to the second power up signal that provides a pull up output signal when the pull-up level shift circuit has not been powered by the first power-up signal; and a DQ pull-down level-shift circuit comprising a second cross-coupled pair of transistors and second circuitry coupled to the second power up signal that provides a pull down output signal when the pull-down level shift circuit has not been powered by the first power-up signal.