Patent ID: 7240179

Claim:
A method of reclaiming a memory hole to increase memory available to a processor, the memory being divided into ranges of linear addresses associated with ranges of physical addresses and including a number of memory devices, the method comprising: identifying a memory hole that includes restricted addresses associated with a subset of physical addresses; adjusting a base of at least one of said ranges of linear addresses to form an adjusted range base corresponding to a base linear address defining said memory hole, wherein said adjusted range base is used to translate linear addresses into said subset of physical addresses; establishing a memory device base corresponding to said base linear address for specifying a physical address of said subset of physical addresses translated from a linear address of said linear addresses; wherein specifying said physical address comprises: identifying one of said number of memory devices to which said linear address translates; and determining which one of a number of partitions said memory device belongs; further comprising translating said linear address into said physical address, which otherwise is restricted from access by a processor as system memory; wherein translating said linear address comprises: decreasing a value representing a portion of said linear address by a value representing said adjusted range base to form a range offset; and increasing a value representing said range offset by a value representing said memory device base to form a memory device offset.