Patent ID: 7509643

Claim:
A method that facilitates favoring performance of a single-threaded application in a computer system that supports simultaneous multi-threading (SMT), wherein multiple threads of execution simultaneously execute in an interleaved manner on functional units within a processor in the computer system, the method comprising: maintaining a priority for each simultaneously executing thread; assigning a highest priority to a main thread of execution associated with the single-threaded application; and using these priorities in allocating a shared computational resource between the simultaneously executing threads, so that the main thread with the highest priority is given preferential access to the shared computational resource; wherein the shared computational resource includes an issue window within the processor, and a shared cache associated with the processor; wherein issuing instructions from the issue window for execution involves statically partitioning the issue queue into at least two sub-queues with the main thread occupying one sub-queue, and the remaining threads sharing any other sub-queues; and wherein when contention exists between threads to obtain access to the shared cache, an arbiter selects between accesses to the shared cache so that accesses associated with the main thread having the highest priority are given preferential access to the shared cache; and wherein this asymmetric treatment of the threads enables the computer system to favor the performance of the single-threaded application while performing simultaneous multi-threading.