Patent ID: 8326909

Claim:
A method of computing at least a first and a second tree of arithmetic or logical operations on a microprocessor comprising at least n parallel processing elements to execute n arithmetic or logical operations in parallel, each of the at least the first and the second tree of arithmetic or logical operations composed of arithmetic or logical operations organized according to a tree structure, the computation of each tree requiring a plurality of successive iterations, the result of each iteration being used during the computation of the next iteration, where n is a positive integer greater than four, the method comprising: executing n arithmetic or logical operations of a first iteration of the first tree in parallel using the n processing elements, then executing m arithmetic or logical operations in parallel to the results of the first iteration, using m processing elements chosen from the n processing elements used for the computation of the first iteration, the other n−m processing element being unused for the computation of a second iteration, where m is an integer strictly smaller than n, wherein in parallel with the computation of the second iteration of the first tree, the method comprises executing k arithmetic or logical operations of the second tree in parallel using k processing elements chosen from the n−m processing elements unused for the computation of the second iteration of the first tree, where k is an integer smaller than or equal to n−m.