Patent ID: 7859040

Claim:
A non-volatile memory unit, comprising: a substrate having a source region, a drain region and a channel region, the channel region separates the source region and the drain region; an electrically insulating layer adjacent to the source region, drain region and channel region layer; a floating gate electrode adjacent to the electrically insulating layer, the electrically insulating layer separates the floating gate electrode from the channel region, the floating gate electrode having a floating gate major surface comprising a carbon based electron field emitter or a tungsten based field emitter; a control gate electrode having a control gate major surface comprising a carbon based electron field emitter or a tungsten based field emitter, the control gate major surface opposing the floating gate major surface; and a vacuum layer at least partially separating the control gate major surface from the floating gate major surface; wherein the electrically insulating layer has a thickness value in a range from 1 to 5 nm separating the floating gate electrode from the substrate.