Patent ID: 8212610

Claim:
A digital loop filter comprising: a fine control circuit operable to adjust a phase of a feedback clock signal by a first phase adjustment in response to a first phase error signal indicative of a phase error between a reference clock signal and the feedback clock signal; a medium control circuit operable to adjust the phase of the feedback clock signal by a second phase adjustment in response to a second phase error signal, wherein the second phase adjustment is larger than the first phase adjustment, and the second phase error signal is indicative of a phase error between the reference clock signal and the feedback clock signal; a band control circuit operable to adjust a frequency of the feedback clock signal in response to a first frequency error signal; and a capacitor array comprising capacitors arranged in rows and columns, wherein bits stored in the band control circuit determine a selected row of capacitors in the capacitor array, and wherein bits stored in the medium control circuit control switches that are coupled to the capacitors in the selected row.