Patent ID: 7490221

Claim:
A data processing apparatus, comprising: a main processor that executes a sequence of instructions, the main processor comprising a first pipeline having a first plurality of pipeline stages; a coprocessor that executes coprocessor instructions in said sequence of instructions, the coprocessor comprising a second pipeline having a second plurality of pipeline stages, and each one of the coprocessor instructions being arranged to be routed through both the first pipeline and the second pipeline; and at least one synchronizing queue including a first-in-first-out (FIFO) buffer having a predetermined plurality of entries and coupling a predetermined pipeline stage in one of the first or second pipeline with a partner pipeline stage in the other one of the first or second pipeline, the predetermined pipeline stage placing a token in an entry of the synchronizing queue when processing one of the coprocessor instructions, the token including a tag which uniquely identifies said one of the coprocessor instructions to which the token relates, and the partner pipeline stage processing the corresponding one of the coprocessor instructions upon receipt of the token from the synchronizing queue, thereby synchronizing the first and second pipelines between the predetermined pipeline stage and the partner pipeline stage without passing signals with fixed timing between the first and second pipelines.