Patent ID: 7202502

Claim:
A thin film transistor (TFT) array panel, comprising: a substrate; a gate wire formed on the substrate and including a gate line, a gate electrode and a gate pad and; a gate insulating layer pattern formed on the gate wire and having a contact hole exposing the gate pad; a semiconductor layer pattern formed on the gate insulating layer pattern; an ohmic contact layer pattern formed on the semiconductor layer pattern; a data wire formed on the ohmic contact layer pattern, including a data line, a source electrode, a drain electrode and a data pad, and having a boundary line substantially the same as that of the ohmic contact layer pattern; a passivation layer pattern formed on the data wire, having contact holes exposing the gate pad, the data pad and the drain electrode; and a pixel electrode electrically connected to the exposed portion of the drain electrode, wherein the gate insulating layer pattern is formed along with at least one of the semiconductor pattern, the ohmic contact layer pattern, the data wire, the passivation layer pattern and the pixel electrode through a single photolithography process using a photoresist pattern having more than two different thickness that varies depending on positions.