Patent ID: 8536656

Claim:
A semiconductor structure comprising: a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate, wherein each gate stack comprises a high k gate dielectric layer, a work function metal layer and a conductive metal, wherein said high k gate dielectric layer, said workfunction metal layer and said conductive metal have upper surfaces that are coplanar with each other; a spacer located on sidewalls of each gate stack, each spacer having a base located entirely on the surface of the semiconductor substrate; a self-aligned dielectric liner present on an upper surface of each spacer, wherein a bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy, and wherein said semiconductor metal alloy has a sidewall portion in contact with an outer edge of said spacer; a contact metal located between neighboring gate stacks, said contact metal is separated from each patterned gate stack by at least the self-aligned dielectric liner; and another contact metal having a first portion that is located on and in direct contact with an upper surface of the contact metal and a second portion that is located on and in direct contact with the upper surface of the conductive metal, the upper surface of the workfunction layer and the upper surface of the high k gate dielectric layer of one of the gate stacks.