Patent ID: 8711016

Claim:
A binary-to-Gray converting circuit, comprising: a buffer unit configured to generate a data code of n bits, where n is a natural number equal to or greater than two, in response to a power supply voltage and a second binary bit signal through an n th binary bit signal except for a first binary bit signal, the first binary bit signal corresponding to a least significant bit of a binary code of n bits, the second through n th binary bit signals corresponding to other bits of the binary code; and a conversion unit configured to generate a Gray code of n bits based on the binary code and the data code, and configured to generate a k th Gray bit signal, where k is a natural number equal to or greater than one and equal to or less than n, by latching a k th data bit signal in response to a k th binary bit signal, a logic level of the k th Gray bit signal being determined corresponding to a logic level of the k th data bit signal, the k th Gray bit signal corresponding to a k th bit of the Gray code, the k th data bit signal corresponding to a k th bit of the data code, and the k th binary bit signal corresponding to a k th bit of the binary code.