Patent ID: 7217963

Claim:
A semiconductor integrated circuit device comprising plural flip-flops, plural logic circuits connected to output nodes of the plural flip-flops and first, second and third power lines, wherein: the flip-flops each comprise a first latch circuit including an output node which is connected with the output node of the flip-flop and a second latch circuit including an input node which is connected with the output node or an input node of the first latch circuit, an operation voltage for the first latch circuit and the logic circuit is supplied from the first and the second power lines, an operation voltage for the second latch circuit is supplied from the first and the third power lines, the first and the second power lines are wired in a mesh-like form and each have a first wiring resistance, the third power line has a second wiring resistance, a wiring for connecting the input node of the second latch circuit and the output node or input node of the first latch circuit has a third wiring resistance, and a difference between the first wiring resistance and the second wiring resistance is smaller than a difference between the second wiring resistance and the third wiring resistance.