Patent ID: 7285979

Claim:
An output buffer, comprising: a plurality of buffer circuits, each buffer circuit having an input circuit and an output circuit, and further having a termination circuit coupled to the input and output circuits, the termination circuit having an activation node to which an activation signal is coupled to enable and disable the termination circuit; and a control circuit coupled to the plurality of buffer circuits and having a mode select node to which a mode select signal is applied and a control node to which a control signal is applied, in response to a first state of the mode select signal and an active control signal, the control circuit configured to generate an active activation signal for the plurality of buffer circuits, and in response to a second state of the mode select signal and an active control signal, the control circuit further configured to generate an active activation signal for a first subset of the plurality of buffer circuits and an inactive activation signal for a second subset of the plurality of buffers circuit.