Patent ID: 8891761

Claim:
A block encrypting device comprising: a processor; memory storing executable instructions that, when executed by the processor, causes the processor to perform the steps of: inputting (n+m)-bit plaintext to be encrypted, when n is an integer equal to 1 or greater and m is an integer equal to 1 or greater and less than n; applying universal hash function-based permutation to the (n+m)-bit plaintext to generate a first intermediate variable of n bits and a second intermediate variable of m bits; encrypting the first intermediate variable by use of an encrypting function of an m-bit tweakable n-bit block cipher, using the second intermediate variable as the tweak to generate a third intermediate variable of m bits and a fourth intermediate variable of (n−m) bits; encrypting an n-bit intermediate variable formed by connecting the second intermediate variable and the fourth intermediate variable, by use of the encrypting function of an m-bit tweakable n-bit block cipher, using the third intermediate variable as the tweak to generate a fifth intermediate variable of n bits; applying universal hash function-based inverse-permutation to result obtained by connecting the third intermediate variable and the fifth intermediate variable to generate (n+m)-bit ciphertext; and outputting the (n+m)-bit ciphertext.