Patent ID: 8923052

Claim:
A semiconductor memory cell comprising: a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer, wherein said cell is configured so that one of said first and second storage locations interacts with said floating body so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.