Patent ID: 7096578

Claim:
A method of manufacturing a multi-layer wiring circuit substrate, comprising: providing a first metal layer having a first major surface with a patterned mask layer overlying and exposing first areas of said first major surface and covering second areas of said first major surface; selectively etching said first metal layer in said first areas of said first major surface to reduce a thickness of said first metal layer in said etched first areas and to form protrusions in said second areas, said protrusions extending above said etched first areas; forming an interlayer-insulating layer overlying said etched first areas of said first major surface, said interlayer-insulating layer having an inner surface confronting said etched first areas and an outer surface remote from said inner surface such that said protrusions extend through said interlayer-insulating layer and have ends exposed at said outer surface; providing a second metal layer in conductive communication with said exposed ends of said protrusions; selectively patterning said first metal layer from a second major surface of said first metal layer remote from said first major surface; and selectively patterning said second metal layer from an exposed major surface of said second metal layer remote from said interlayer-insulating layer.