Patent ID: 7663945

Claim:
A semiconductor device comprising a delay circuit, the delay circuit comprising: at least one circuit unit comprising: an inverter including: a first MOS transistor having a source thereof connected to a first power supply; and a second MOS transistor having a source thereof connected to a second power supply, having a gate thereof connected in common with a gate of said first MOS transistor to an input terminal, and having a drain thereof connected in common with a drain of said first MOS transistor to an output terminal, said second MOS transistor having a different conductivity type from a conductivity type of said first MOS transistor; a resistor having one terminal thereof connected to said output terminal of said inverter; and a MOS capacitor connected between the other terminal of said resistor and said first or second power supply, the delay circuit having a characteristic in which a delay time thereof decreases more when a provided power supply voltage is low than when the provided power supply voltage is high.