Patent ID: 8352836

Claim:
An error addition apparatus for receiving a data signal having a frame format having a specific signal inserted into its front, adding error bits to the data signal, and outputting a resulting signal, the error addition apparatus comprising: an error addition regulation unit for receiving a frame synchronization signal, indicative of a timing at which the front of a frame of the data signal has been inputted, and regulating the error bits such that the error bits are added to positions other than a region of the specific signal; wherein the error addition regulation unit comprises a gate signal generation unit and a gate circuit, and the gate signal generation unit receives the frame synchronization signal, generates a gate signal, including bit data having a predetermined number of bits at a timing at which the bit data, having the predetermined number of bits and including the region of the specific signal at the front of the data signal, are outputted based on frame information of the data signal, and outputs the generated gate signal to the gate circuit.