Patent ID: 7420834

Claim:
A semiconductor integrated circuit device provided with a SRAM memory comprising: a plurality of word lines; a plurality of complementation bit lines; a plurality of memory cells for allocated corresponding to the plurality of word lines and the plurality of complementation bit lines; a plurality of memory cell voltage lines for supplying an operational voltage to each of the plurality of memory cells; and a plurality of voltage means for supplying a power voltage to the plurality of memory cell voltage lines each, wherein each of the voltage means is a switch MOS which is turned OFF in a write state to the memory cell by a control signal basis of a memory cell write control signal and a memory cell selection signal for the corresponding complementation bit lines, wherein the power voltage is a positive voltage, wherein the switch MOS is a PMOS, and wherein the PMOS is allocated in parallel with an NMOS, and the gates of the PMOS and the NMOS are commonly connected.