Patent ID: 7764539

Claim:
A method of writing a “0” resistance state to a bit cell in a spin-transfer MRAM structure wherein the bit cell is comprised of two sub-cells each having a CPP cell formed above a MTJ cell and connected through a conductive spacer, each of said MTJ cells has a first free layer with near zero anisotropy, and each of said CPP cells has a second free layer with a substantial anisotropy and a top electrode contacting a bit line, and a first conductive spacer in first sub-cell and a second conductive spacer in a second sub-cell are connected through a transistor, comprising: (a) injecting a write current into a first bit line contacting a top electrode in the CPP cell in the first sub-cell, said write current passes through the first CPP cell and into the first conductive spacer and then into the second conductive spacer and out through a second CPP cell to a second bit line contacting the top electrode in the second CPP cell to form a “0” resistance state in the first CPP cell, a “1” resistance state in the first MTJ cell, a “1” resistance state in the second CPP cell, and a “0” resistance state in the second MTJ cell; and (b) simultaneously applying a current to a write word line that controls a voltage to said transistor and causes current to flow from the first conductive spacer to the second conductive spacer.