Patent ID: 6914834

Claim:
A system for functionally testing a semiconductor memory chip having memory cells subdivided into a plurality of spatially separate memory blocks, including a first memory block and a second memory block, the system comprising: test pattern loading means for externally loading a selected test pattern to the first memory block using one of low clock frequency and a low data rate and a selected address offset for the first memory block, the selected test pattern containing at least one of data signals and data strobe signals, said test pattern loading means subsequently disconnecting a connection to the semiconductor memory chip; data lines and data strobe lines connected to said test pattern loading means; first circuit means connected to said data lines and to said data strobe lines, said first circuit means upon activation of a functional test mode, divides at least one of said data lines and said data strobe lines between the first and second memory blocks of the semiconductor memory chip into two groups of equivalent size and connects them to one another; second circuit means connected to said data lines and said data strobe lines, said second circuit means by a first read-write cycle, shifts the selected test pattern previously loaded into the first memory block into the second memory block with one of a high clock frequency and a high data rate and subsequently, by a second read-write cycle, shifts the selected test pattern stored in the second memory block with one of the high clock frequency and the high data rate in an opposite direction back into the first memory block again; and test pattern read-out means for reading out and evaluating the selected test pattern shifted back into the first memory block.