Patent ID: 7728380

Claim:
A device comprising: a semiconductor substrate having a well region; a gate electrode formed within the well region at a prescribed depth; a cap gate insulating layer comprising an insulating material formed on a surface of the gate electrode, wherein an upper surface of the cap gate insulating layer is substantially level with a surface of the semiconductor substrate; an n-type impurity region and an insulating layer pattern formed between the gate electrode and the well region, wherein the insulating layer pattern is directly on both lateral sides of the gate electrode and the cap gate insulating layer and directly on a bottom surface of the gate electrode, and wherein the n-type impurity region entirely surrounds and contacts the insulating layer pattern; source/drain regions formed within the semiconductor substrate at sides of the gate electrode; and an interlayer dielectric layer formed over the semiconductor substrate and having metal interconnections formed therein configured to be electrically connected to the source/drain regions, respectively.