Patent ID: 6898561

Claim:
A method of modeling an integrated circuit device having an electrical path therein and first and second gate electrodes that overlie the electrical path, comprising the steps of: determining an electrical gate length of the first gate electrode by determining a simulated drain-to-source current (IDS sim ) through the electrical path; and determining an electrical gate length of the first gate electrode (L 1 ) by: evaluating a change in the simulated drain-to-source current (IDS sim ) through the electrical path relative to a change in an electrical gate length of the second gate electrode (L 2 ) as ∂IDS sim /∂L 2 ; and evaluating a change in the simulated drain-to-source current (IDS sim ) through the electrical path relative to a change in an electrical gate length of the first gate electrode as ∂IDS sim /∂L 1 .