Patent ID: 7183594

Claim:
A configurable gate array cell comprising: a doping zone of a first conduction type formed in a semiconductor substrate and a doping zone of a second conduction type, which are arranged along a preferred direction; and a poly-silicon gate terminal extending in plane parallel to the semiconductor substrate, the poly-silicon gate terminal having a plurality of contiguous sections, a first section extending along the preferred direction above the doping zones, a second section extending in the preferred direction and laterally offset from the doping zones, and a third section connecting the first and second sections to one another, a plurality of wiring tracks formed substantially transversely with respect to the preferred direction of the first and second sections of the poly-silicon gate terminal, wherein the first section of the poly-silicon gate terminal extends over all of the wiring tracks, and the second section of the poly-silicon gate terminal extends over fewer than all of the wiring tracks, and wherein the wiring tracks are formed in a different plane than the first, second or third sections of the poly-silicon gate terminal.