Patent ID: 8208309

Claim:
A semiconductor memory device, in which flag data read of a flag data region is performed during data write, comprising: a nonvolatile memory cell array formed from a plurality of nonvolatile memory cells, and having an ordinary data region and the flag data region allocated to a one page range in which read and write are simultaneously performed; and a sense amplifier circuit including a plurality of sense amplifiers, a number of the sense amplifiers corresponding to a number of the nonvolatile cells in a one page amount, and each of the sense amplifiers comprising a data latch for retaining write data, wherein, during read of the flag data by the sense amplifier circuit, in the case of one of the sense amplifiers corresponding to the flag data region, read flag data is transferred to the data latch, and in the case of one of the sense amplifiers corresponding to the ordinary data region, write data retained by the data latch is rewritten regardless of read cell data.