Patent ID: 8063679

Claim:
A DLL circuit comprising: a delay circuit that gives a delay amount of a prescribed value to an input signal of a prescribed frequency received at an input terminal of said DLL circuit, to be outputted as an output signal at an output terminal of said DLL circuit; a phase comparison circuit that compares phases of said input signal and said output signal, and outputs, as a comparison result signal, a comparison result showing a first state in which said phase of said output signal is advanced in comparison to said input signal and a second state in which said phase of said output signal is delayed in comparison to said input signal; and a control circuit that receives said comparison result signal as input and that controls delay amount of said delay circuit; wherein said control circuit changes said delay amount according to a number of comparison results, which show one state of either said first state and said second state, said number of comparison results being a number occupying in an overall number of comparison operations executed a plurality of times by said phase comparison circuit, being a prescribed number, wherein said control circuit includes first to third control operations with regard to said delay circuit, said first control operation controls one of either of increasing and decreasing said delay amount in response to said prescribed number being a first number, said second control operation holds present delay amount without changing said delay amount in response to said prescribed number being a second number larger than said first number, and said third control operation controls another of said either of increasing and decreasing said delay amount in response to said prescribed number being a third number larger than said second number.