Patent ID: 7057926

Claim:
A semiconductor memory comprising: a semiconductor substrate including a semiconductor film on a first insulating film; a memory cell that stores data by charging or discharging a body region formed in said semiconductor film, the memory cell including a source layer on one side of said body region and a drain layer on another side of said body region; a memory cell array in which a plurality of said memory cells are arranged in a matrix; a second insulating film provided on said body region of said memory cell; a first word line provided on said second insulating film; a bit line connected to the drain layer of said memory cell, and having a reference potential when said memory cell is in a data retaining state; a source line connected to the source layer of said memory cell, and having the reference potential; and a second word line buried in said first insulating film, and provided below said body region of said memory cell, wherein a potential V BWLH of said second word line when said memory cell is in the data retaining state is closer to said reference potential than a potential V BWLL of said second word line when a data read/write operation is executed.