Patent ID: 7095077

Claim:
A semiconductor memory, comprising: a p-type semiconductor film provided on a p-type semiconductor substrate, a p-type well region in a semiconductor substrate, or an insulator; a gate insulating film formed on the p-type semiconductor film provided on the p-type semiconductor substrate, the p-type well region in a semiconductor substrate, or the insulator; a single gate electrode formed on the gate insulating film; two charge storage sections formed on side walls of the gate electrode; a channel region provided below the gate electrode; and a first n-type diffusion layer region and a second n-type diffusion layer region provided to sides of the channel region, wherein: the charge storage sections are arranged to change an electric current flow between the first n-type diffusion layer region and the second n-type diffusion layer region under application of a voltage to the gate electrode according to a quantity of electric charge stored in the charge storage sections; and the first n-type diffusion layer region is set to a reference voltage, the second n-type diffusion layer region is set to a voltage greater than the reference voltage, and the gate electrode is set to a voltage greater than the reference voltage, so as to inject electrons to one of the charge storage sections near the second n-type diffusion layer region.