Patent ID: 8214677

Claim:
A system, comprising: a programmable power control system to control a switch-based regulator during each of multiple states of a processor system, including to operate the switch-based regulator in accordance with a first mode to provide power to the processor system when the processor is in a wake state, and in accordance with a second mode when the processor is in a reduced power-consumption state, wherein the programmable power control system includes a voltage regulator controller to provide voltage control configuration parameters, and a finite state machine (FSM) control system to implement one or more finite state machines (FSMs) to control one or more voltage regulation control parameters, including one or more of a ramp rate control parameter, a power throttle control parameter, and a load-line adjust current parameter, based on the voltage control configuration parameters, and to determine a target voltage, wherein the system is implemented to deactivate an input clock of the power control system when the processor system transitions to a sleep state to place the power control system in the second mode in which operation of at least a portion the power control system and operation of the switch-based regulator is suspended, the power control system is implemented to exit the second mode when a voltage of the processor system is below a threshold and operate the switch-based regulator to increase the processor system voltage, and the power control system is further implemented to return to the second mode when the processor system voltage meets the threshold and the processor system is in the reduced power-consumption state.