Patent ID: 7888193

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate having a plurality of element regions; (b) forming a resist laminate on the semiconductor substrate; (c) forming an upper opening through an upper region of the resist laminate in each of the plurality of element regions, the upper opening having a laterally broadening middle space; (d) applying an energy beam to a lower region of the resist laminate in at least some of the element regions at a dose corresponding to each element region; (e) forming a lower opening through the lower region of the resist laminate in each of the element regions, the lower opening communicating the upper opening, having a limited size along a first direction, and having generally vertical side walls; (f) performing a heat treatment of the resist laminate to deform the side walls of the lower opening in at least some of the element regions in accordance with doses so that the lower opening has a taper shape upwardly and monotonically increasing a size of the lower opening along the first direction; and (g) filling a conductive stem in the lower opening and forming a head in the upper opening, the head having an expanded size along the first direction; and wherein said step (d) applies an energy beam at different doses for different element regions, said step (f) forms the side walls of the lower openings having different taper angles, and said step (g) forms mushroom gate electrodes.