Patent ID: 8222742

Claim:
A semiconductor device, comprising: a lower semiconductor layer with first conductive regions, the first conductive regions including at least one dummy first conductive region; an upper semiconductor layer with second conductive regions on the lower semiconductor layer, the second conductive regions including at least one dummy second conductive region; a penetration hole in the upper semiconductor layer, the penetration hole penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region; a lower conductive line on the lower semiconductor layer, the lower conductive line being electrically connected to the first conductive regions; an upper conductive line on the upper semiconductor layer, the upper conductive line being electrically connected to the second conductive regions; a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower conductive line to the upper conductive line, and the first conductive plug being spaced apart from sidewalls of the penetration hole; a device isolation layer in the upper semiconductor layer, the device isolation layer separating each of the second conductive regions; first gate lines on the lower semiconductor layer on both sides of the lower conductive line; and second gate lines along a first direction on the upper semiconductor layer on both sides of the upper conductive line, the second gate lines being spaced apart from each other along a second direction, wherein the penetration hole penetrates a portion of the device isolation layer at both sides of the dummy second conductive region and the upper semiconductor layer under the portion of the device isolation layer.