Patent ID: 6910092

Claim:
A system comprising: a first ASIC (Application Specific Integrated Circuit) including a first substrate; a plurality of On Chip Macros mounted on said first substrate; a second ASIC including a second substrate positioned in spaced relationship to said first substrate; a plurality of On Chip Macros mounted on said second substrate; a Chip to Chip Non-Serial Bus Interface subsystem operatively positioned to provide communications between the first ASIC and the second ASIC; at least one on-chip non-serial ASIC bus coupled to at least one of the on-chip macros on the first and the second ASIC, respectively, wherein number of bit lines in the on-chip non-serial bus is greater than the number of bit lines in the non-serial Bus Interface subsystem; and a Chip to Chip Macro subsystem operatively mounted on the first ASIC and the second ASIC, said Chip to Chip Macro subsystem receiving data with a first footprint equivalent to number of bit lines in the on-chip non-serial ASIC bus reducing the first footprint so the data matches footprint of the chip to chip non-serial bus interface subsystem.