Patent ID: 8605029

Claim:
A shift register comprising a plurality of bistable circuits having a first state and a second state and connected in series with each other, the plurality of bistable circuits being sequentially placed in the first state based on two-phase clock signals including a first and a second clock signal, the first and second clock signals being provided from an external source of each bistable circuit and periodically repeating a high-level potential and a low-level potential, wherein each bistable circuit includes: an output node that outputs a state signal indicating either one of the first state and the second state; a first transistor having a second electrode to which a high-level potential is provided, and a third electrode connected to the output node; a second transistor having a first electrode to which the first clock signal is provided, and a third electrode connected to a first node connected to a first electrode of the first transistor; a second node charge portion for charging a second node based on a state signal outputted from a bistable circuit of a previous stage of the bistable circuit, the second node being connected to a second electrode of the second transistor; a second node discharge portion for discharging the second node based on a state signal outputted from a bistable circuit of a subsequent stage of the bistable circuit; a first node discharge portion for discharging the first node based on the second clock signal; and an output node discharge portion for discharging the output node based on the second clock signal.