Patent ID: 8631265

Claim:
A method for using a synchronization circuit that supports multiple parallel reads and writes, comprising: receiving a request to access two or more stages of the synchronization circuit from a first time domain, wherein the synchronization circuit comprises multiple data storage locations that synchronize data and control signals between the first time domain and a second time domain; using control logic in the synchronization circuit to determine whether a present state of the synchronization circuit can accommodate the request, wherein the control logic facilitates simultaneously accessing a variable number of synchronized data storage locations in a single clock cycle of the first time domain; and if so, simultaneously accessing two or more synchronized data storage locations in the synchronization circuit, wherein each synchronized data storage location in the synchronized data storage locations comprises a data-holding element that stores a FIFO word and two one-bit synchronizers that indicate to the first time domain and the second time domain whether the synchronized data storage location is empty or full.