Patent ID: 7345537

Claim:
A power amplifier circuit comprising: a first amplifier having a first subsection and a second subsection, the first amplifier configured to receive an input signal, and in response, provide a first path output signal; a first delay circuit configured to introduce a first delay to the input signal, thereby creating a second path delayed input signal; a second amplifier having a first subsection and a second subsection, the second amplifier configured to receive the second path delayed input signal, and in response, provide a second path delayed output signal, wherein the first subsection is enabled; an impedance inverter circuit configured to provide impedance inversion and introduce a first path delay to the first path output signal, thereby creating a first path delayed output signal; a node connecting an output of the impedance inverter and an output of the second amplifier, the node configured to combine the first path and second path delayed output signals, thereby creating an amplified output signal; and a bias control circuit configured to provide a first bias voltage that enables the first subsection of the first amplifier and the first subsection of the second amplifier, to causes the enabled subsections to operate in a linear mode during a low power mode, wherein the second subsection of the first amplifier and the second subsection of the second amplifier are disabled in the low power mode, and a second bias voltage that enables the second subsection of the first amplifier and the second subsection of the second amplifier, wherein the first subsection of the first amplifier and the first subsection of the second amplifier are enabled in the high power mode, to causes the enabled amplifier subsections to operate in a linear mode during a high power mode.