Patent ID: 6847236

Claim:
A buffer/voltage-mirror arrangement comprising: a plurality of stages, each comprising: electrically-parallel branches of a first transistor connected in series with a second transistor, and a third transistor connected in series with a fourth transistor said second and fourth transistors being of an inverse type to that of said first and third transistors, a gate interconnection electrically connecting gates of said first and second transistors to one another, and an intermediate electrical connection connecting all of the gates of said third and fourth transistors, an intermediate point between said first and second transistors and an intermediate point between said third and fourth transistors to one another; wherein said gate interconnection of a first stage represents an input, wherein said intermediate electrical connection of a preceding stage is electrically connected to said gate interconnection of a succeeding stage, and said intermediate electrical connection of a final stage represents an output, and wherein said buffer/voltage-mirror arrangement is adapted to cause an output voltage on said output to mirror an input voltage on said input by a predetermined factor; at least one stage of said plurality of stages comprising a switch for selectably enabling/disabling said at least one stage, said switch comprising: a series connection of a fifth transistor and a sixth transistor electrically connected between said first and second transistors, and a series connection of a seventh transistor and an eighth transistor electrically connected between said third and fourth transistors, said sixth and eighth transistors being of an inverse type to that of said fit and seventh transistors, a switch enabling interconnection electrically connected to gates of said fifth and seventh transistors and connected through an inverter to gates of said sixth and eighth transistors, with said intermediate point between said first and second transistors likewise serving as an intermediate point between said fifth and sixth transistors, and with said intermediate point between said third and fourth transistors likewise serving as an intermediate point between said seventh and eighth transistors.