Patent ID: 8587354

Claim:
A delay locked loop for an integrated circuit, comprising: a variable delay line for receiving a first clock and for producing a second clock delayed with respect to the first clock, wherein the delay between the first clock and the second clock is variable at least by adjusting a power supply voltage for the variable delay line; logic circuitry for producing a summed signal, wherein the logic circuitry adds or subtracts up or down signals from a phase detector to produce the summed signal, wherein an up signal adds to a value of the summed signal, and wherein a down signal subtracts from the value of the summed signal; and a regulator for providing the power supply voltage for the variable delay line, wherein the regulator receives the summed signal and regulates the power supply voltage as a function of the summed signal, and wherein the value of the summed signal can be a positive value or a negative value; the positive value of the summed signal corresponds to an entry point of the first clock into the variable delay line; and the negative value corresponds to entry of the first clock into a first entry point of the variable delay line.