Patent ID: 8363508

Claim:
A semiconductor device, comprising: a first FIFO counter that receives a first internal ODT signal and outputs a second internal ODT signal in response to counting a first clock signal by a first predetermined number after receiving the first internal ODT signal; a counter control circuit that controls the FIFO counter such that the first FIFO counter outputs the second internal ODT signal having a same logic value as a logic value of the first internal ODT signal at a time of changing from an asynchronous mode to a synchronous mode during a period until when the first FIFO counter receives the first clock signal by at least the first predetermined number after the changing; and a ODT circuit activated synchronously with a second clock signal generated based on the first clock signal during the synchronous mode and activated asynchronously with the second clock signal during the asynchronous mode, wherein the FIFO counter includes: a shift register in which a plurality of register circuits includes an initial stage register circuit are connected in cascade, each of the register circuits performing a latch operation synchronously with the first clock signal, and the first internal ODT signal being supplied to the initial stage register circuit of the shift register; and a multiplexer that extracts an output of any one of the register circuits as the second internal ODT signal, and wherein the counter control circuit sets or resets at least all the register circuits from the initial stage register circuit to a register circuit at a same number of stages as the first predetermined number, based on a logic value of the first internal ODT signal at the time of changing.