Patent ID: 8679941

Claim:
A method for manufacturing a semiconductor device, the method comprising the steps of: providing a wafer comprising a semiconductor substrate, a pad oxide layer atop the semiconductor substrate, and a pad nitride layer atop the pad oxide layer; forming at least one recessed shallow trench isolation (STI) feature in said wafer, said recessed STI feature comprising a trench filled with a third dielectric fill material, said third dielectric fill material having a top surface substantially coplanar with or recessed below the uppermost top surface of the semiconductor substrate, wherein said pad nitride layer and said pad oxide layer are exposed along sidewalls of said trench above the top surface of said third dielectric fill material; forming a thin wet etch resistant dielectric layer over the wafer, said thin wet etch resistant dielectric layer in contact with and completely covering at least the top surface of said third dielectric fill material, said thin wet etch resistant dielectric layer comprising a fourth dielectric material that is more resistant to a wet etch process than at least said pad oxide layer, said thin wet etch resistant dielectric layer having a thickness in the range from about 10 Å-100 Å; depositing a fourth dielectric fill material over said thin wet etch resistant dielectric layer; removing said fourth dielectric fill material and said thin wet etch resistant dielectric layer from the top surface of said pad nitride layer; removing said pad nitride layer using a wet etch method that is selective at least to said thin wet etch resistant dielectric layer; and removing portions of said thin wet etch resistant dielectric layer above said first dielectric pad oxide layer selectively to said pad oxide layer.