Patent ID: 7183606

Claim:
A method of fabricating a flash memory cell, comprising the steps of: providing a first conductive type substrate; forming a second conductive type first well region in the substrate; forming a stacked gate structure over the substrate, wherein the stacked gate structure comprises a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the substrate; forming a first conductive type pocket doped region in an area of the substrate designated for forming a drain region such that the first conductive type pocket doped region extends to an area underneath the stacked gate structure close to an area designated for forming the a source region; forming the source region and the drain region in the substrate on each side of the stacked gate structure; forming a pair of spacers on sidewalls of the stacked gate structure; forming a first conductive type doped region in the drain region, wherein the first conductive type doped region extends through a junction between the drain region and the first conductive type pocket doped region; forming an inter-layer dielectric layer over the substrate; removing a portion of the inter-layer dielectric layer and the spacer to form an contact hole, wherein the contact hole exposes the drain region and the first conductive type doped region such that the first conductive type doped region separates from the spacer by a distance; and forming a contact plug inside the contact hole, wherein the contact plug is connected to the first conductive type doped region electrically.