Patent ID: 7461232

Claim:
A translation look-aside buffer, comprising: a given number N of entries for storing N respective address translations which each associate a given virtual address portion with a given physical address portion, and which are usable in a first mode of operation of a processor incorporating said buffer for accessing data stored in a physical memory, each entry in the buffer comprising a first field for storing the virtual address portion, a second field for storing an intermediate address portion, and a third field for storing the physical address portion, the first and third fields being mutually associated via the second field; in a first mode of operation of the processor, the buffer is addressable by the content of the first fields, wherein the buffer is configured so that, in response to a request for access to external memory, it outputs the physical address portion stored in the third field of a given entry when it is addressed by an input value corresponding to the virtual address portion stored in the first field of said entry; and for each entry, the first field and the second field are at least write accessible in a second mode of operation of the processor in which the third field is not accessible; and, for each entry the second field is read accessible in a third mode of operation of the processor, and the third field is at least write accessible in the third mode of operation of the processor.