Patent ID: 8665661

Claim:
A semiconductor memory device comprising: a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a first selection gate transistor, a second selection gate transistor and a plurality of memory cells including a first memory cell, a second memory cell and a third memory cell, the plurality of memory cells being connected in series and being connected between the first selection gate transistor and the second selection gate transistor, the plurality of memory cells each being capable of storing data of at least one bit which can be electrically programmed and erased; and a plurality of word lines, control gates of the plurality of memory cells being connected to the plurality of word lines, each being selected according to a corresponding row address; wherein the first memory cell is located on one end portion of the plurality of memory cells, the second memory cell and the third memory cell are connected to each other and are located adjacent to each other, the first memory cell in a first memory cell unit is located between the second memory cell in the first memory cell unit and the first selection gate transistor in the first memory cell unit; and wherein a distance between the first memory cell in the first memory cell unit and the first selection gate transistor in the first memory cell unit is greater than a distance between the second memory cell in the first memory cell unit and the third memory cell in the first memory cell unit.