Patent ID: 7224179

Claim:
An apparatus for adjusting a slew rate in a semiconductor memory device, the apparatus comprising: a slew rate control signal generation block for outputting a plurality of slew rate control signals through combining control codes inputted from an external circuit in response to a command signal; and a data buffer for adjusting a slew rate of a data signal inputted by using the slew rate control signals, wherein the control codes are classified into a first control code group and a second control code group, wherein the slew rate control signal generation block includes: a first slew rate control signal generator for outputting a first slew rate control signal group by decoding the first control code group through the use of the command signal; and a second slew rate control signal generator for outputting a second slew rate control signal group by decoding the second control code group through the use of the command signal, wherein the data buffer includes: a first pre-driver for generating a driving signal with use of the inputted data signal; a first slew rate adjustment unit for adjusting a slope of the data signal by the first slew rate control signal group, the first slew rate adjustment unit being connected between one side of the first pre-driver and one of a ground and a supply voltage; an output driver for outputting the data signal with use of the driving signal; a second pre-driver for generating a driving signal with use of the inputted data signal; and a second slew rate adjustment unit for adjusting a slope of the data signal by the second slew rate control signal group, the second slew rate adjustment unit being connected between one side of the second pre-driver and one of a ground and a supply voltage.