Patent ID: 8405206

Claim:
A power semiconductor module, comprising: a module housing; at least one substrate having a dielectric insulation carrier and a plane topside metallization layer attached to the insulation carrier and which comprises a number of conductor tracks; a number N of at least two controllable power semiconductor chips arranged inside the module housing and one after another in a lateral direction, wherein each of the number of N controllable power semiconductor chips is arranged on the top metallization layer of one of the at least one substrate and comprises a first main electrode, a second main electrode, a load path formed between the first main electrode and the second main electrode, and a control electrode for controlling an electric current through the load path, and wherein the first main electrodes are electrically connected to one another, the second main electrodes are electrically connected to one another, and the control electrodes are electrically connected to one another; a single main load terminal arranged outside the module housing and electrically connected to the first main electrodes; an auxiliary terminal arranged outside the module housing and electrically connected to the first main electrodes via an auxiliary terminal connecting conductor, the auxiliary terminal connecting conductor being connected to one of the at least one topside metallization layer at a connection location of that topside metallization layer; and wherein the main load terminal is spaced distant from the connection location in the lateral direction at a distance that is less than or equal to a smallest repeat distance that occurs between any two adjacent ones of the power semiconductor chips in the lateral direction.