Patent ID: 6844578

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate; one or more horizontal MOS transistors formed in the semiconductor substrate each having a source region and a drain region arranged in a horizontal direction relative to a main surface of the semiconductor substrate and a P-type gate electrode; and a vertical MOS transistor formed in the semiconductor substrate and comprising a trench formed in the main surface of the semiconductor substrate, a gate insulating film covering a side surface and a bottom surface of the trench, a P-type gate electrode buried in the trench in contact with the gate insulating film, a high concentration source region formed in the main surface of the semiconductor substrate outside the trench and in contact with the trench, a body region formed in the semiconductor substrate in contact with the trench, surrounding the high concentration source region, deeper than the high concentration source region, shallower than the bottom surface of the trench and having a conductivity type opposite to that of the high concentration source region, and a high concentration drain region formed in the semiconductor substrate spaced apart from the trench, the high concentration source region, and the body region.