Patent ID: 7633787

Claim:
A ROM memory component comprising at least one memory cell array, each memory cell array comprising: a plurality of first ROM memory cells for storing a first logic level, each first ROM memory cell comprising a first terminal connected to a word line, a second terminal and a third terminal, wherein the second terminal is connected to a bit line and/wherein the third terminal is connected to a supply line for pre-charging the third terminal, a plurality of second ROM memory cells for storing a second logic level, each second ROM memory cell comprising a first terminal connected to a word line, a second terminal, and a third terminal, wherein either the second terminal is connected to a bit line or the third terminal is connected to a supply line, and wherein either the second terminal or the third terminal is floating, a plurality of word lines, a plurality of bit lines, a plurality of supply lines, wherein a first reference potential is in each case applied to the plurality of word lines, the plurality of bit lines and the plurality of supply lines of a memory cell array in a standby operating mode, such that for each first ROM memory cell the first reference potential is applied to all the terminals in the standby operating mode and for each second ROM memory cell the first reference potential is applied to the first terminal and to the terminal connected to the bit line or the supply line.