Patent ID: 6888190

Claim:
An electrically erasable programmable read only memory (EERPOM) with source line voltage stabilization mechanism, comprising: a semiconductor substrate of a first conductivity type having a memory region; a deep ion well of a second conductivity type formed in said semiconductor substrate; a cell ion well of said first conductivity type located within said memory region in said semiconductor substrate, said cell ion well being situated above said deep ion well; a shallow ion well of said second conductivity type serving as a buried bit line doped within said cell ion well, said shallow ion well being isolated by an STI layer, wherein said STI layer has a thickness greater than a well depth of said shallow ion well; at least one memory transistor comprising a stacked gate, a source, and a drain formed on said shallow ion well, wherein said source of said memory transistor is electrically coupled to said cell ion well to induce a capacitor between said cell ion well and said deep ion well during a read operation, thereby avoiding read current bounce or potential power crash; and a bit line overlying said memory transistor and electrically connected to said drain of said memory transistor via a bit line contact plug short-circuiting said drain of said memory transistor and said shallow ion well.