Patent ID: 7544613

Claim:
A method of manufacturing a semiconductor device including a plurality of word lines of memory cells and a pair of select gate lines, the method comprising: forming at least a first insulating film, a first conductive film, and a second insulating film above a semiconductor substrate sequentially; forming a first resist with a plurality of first patterns and a second pattern above the second insulating film, the first patterns being formed in a first region above the second insulating film and having almost the same width and interval as those of the word lines of the memory cells, and the second patterns being formed in a second region adjacent to the first region above the second insulating film and having a width substantially equal to the sum of the width of each of the select gate lines and the interval of the select gate lines; patterning the second insulating film and the first conductive film by use of the first resist to form the word lines of the memory cells; forming a second resist above the second insulating film in such a manner that the second resist is formed in a region excluding the space between the select gate lines in the second region; and patterning the second insulating film and the first conductive film by use of the second resist to form the select gate lines.