Patent ID: 7676655

Claim:
A multithreaded multicore processor comprising: a plurality of cores, each of said cores being configured to support two or more threads; and a shared thread control register shared by the plurality of cores, the shared thread control register including only a single bit for each of the threads in the plurality of cores; wherein setting a bit of the shared thread control register to a first value causes a corresponding thread in one of said cores to be reset, in response to detecting the processor is in a first state; and wherein setting the bit of the shared thread control register to the first value causes the corresponding thread to be unparked, in response to detecting the processor is in a second state; wherein each of said cores includes a trap logic unit configured to monitor bits of the shared thread control register, and wherein in response to detecting transitions of the monitored bits of the shared register, each trap unit is configured to convey one of a park, unpark, or reset signal for a corresponding thread; and wherein each trap logic unit includes a latch which indicates either said first state or said second state, wherein the latch assumes the first state in response to a reset signal.