Patent ID: 8499264

Claim:
A computer-based process of implementing a logic circuit for logical operations, comprising the steps of: a) selecting N as a number of variables for the logic circuit, b) designing the logic circuit with N max inputs, where N max is selected from the group consisting only of 33, 60, 109, 202, and 375, c) using the computer, selectively basing the logic circuit on only one of, i) a function x 0 & (x 1 (x 2 & (x 3 . . . x N−1 . . . ))), where N lo <N<N max , and setting inputs x i (i=N, N+1, . . . , N max −1) to a first binary value (0) for even values of i and to a second binary value (1) for odd values of i, and ii) a function x 0 (x 1 & (x 2 (x 3 & . . . x N−1 . . . ))), where N lo <N<N max , and setting inputs x i (i=N, N+1, . . . , N max −1) to a first binary value (0) for odd values of i and to a second binary value (1) for even values of i, d) removing gates that do not contribute to the function, and e) implementing the logic circuit with two-input gates to a depth of Z.