Patent ID: 7259421

Claim:
A NAND-type semiconductor flash memory device, comprising: a semiconductor substrate including a trench therein; first and second gate patterns on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench; a split source/drain region in the substrate between the first gate pattern and the second gate pattern and divided by the trench, the split source/drain region including a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench; a connecting region in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion; a third gate pattern on the surface of the substrate adjacent the second gate pattern, wherein the surface of the substrate that extends between the second gate pattern and the third gate pattern is substantially planar; and, a continuous source drain region in the substrate between the second gate pattern and the third gate pattern, wherein the first gate pattern comprises a select gate pattern, and wherein the second gate pattern comprises a storage gate pattern.