Patent ID: 8547741

Claim:
A memory device, comprising: a NAND string of a plurality of memory cells arranged in electrical series between a first end and a second end on a semiconductor body, including: a plurality of stacks of word lines, the word lines within a stack of the plurality of stacks being mutually electrically separated, the plurality of stacks extending out of the semiconductor body; and a semiconductor channel material covering the plurality of stacks of word lines and having multiple locations with conductivity controlled by different word lines in the plurality of stacks, the NAND string having an electrical series connection between the first end and the second end of the NAND string via the semiconductor channel material, the semiconductor channel material including a same type doping in between the first end and the second end, the semiconductor channel material arranged as a plurality of ridges extending out of the semiconductor body, wherein a ridge in the plurality of ridges covers multiple adjacent stacks in the plurality of stacks of word lines.