Patent ID: 7437393

Claim:
Signal processing apparatus comprising; cascade-connected n-staged accumulators, processing means for performing (m−1)th order differentiation of an overflow signal of an mth-stage accumulator (where 2≦m≦n), and adding means for adding an output of the first-stage accumulator and all results of said differentiation of the second to nth-stage accumulators and outputting an added result, wherein a signal input of p( 1 ) bits is inputted into the first accumulator of p( 1 ) bits, q(m−1) bits from the most significant bit (termed “higher bits”) (where 1≦q(m−1)≦p(m)) of an output of an (m−1)th-stage accumulator are inputted into higher bits of an mth-stage accumulator of p(m) bits (where p(m)≦p(m−1)), a logical operation result of at least a prescribed accumulator of (m+1)th-stage or later stage or stages, or an external {p(m)−q(m−1)} bit signal, which is a random signal, is inputted into the remaining less significant bits (termed “lower bits”) of said mth-stage accumulator, and p( 1 )>p(n) holds.