Patent ID: 7340656

Claim:
A logic analyzer system, comprising: a logic analyzer; a probe for acquiring data signals from a bus of a device under test, said probe being located in a given location on said device under test for the duration of a given test; and a preprocessor; said preprocessor being coupled between said probe and said logic analyzer, and including: a circuit for detecting a strobe phase inversion condition; and a circuit for correcting for said strobe phase inversion condition; wherein said correction of said strobe phase inversion is performed in real time; wherein said detection and correction circuitry causes said data signals to be received at said logic analyzer in the correct order whether or not a strobe phase inversion occurred; and wherein said received data is source synchronous data, and said reception of said data signals in said correct order allows said logic analyzer to correctly trigger on the source synchronous data regardless of whether or not a strobe phase inversion occurred.