Patent ID: 7688659

Claim:
A semiconductor memory, comprising: a plurality of memory blocks each having a memory cell and a bit line coupled to the memory cells; a decoder which activates one of block selection signals configured to select the memory blocks according to an address signal; a plurality of block control circuits provided corresponding to the memory blocks, the block control circuits each having a precharge circuit which couples the bit line to a precharge voltage line according to a precharge control signal; a plurality of program circuits provided corresponding to the memory blocks, the program circuits each having a non-volatile program unit, outputting an operating specification signal indicating a first operation specification when the program unit is not programmed, and outputting an operating specification signal indicating a second operating specification when the program unit is programmed; a plurality of specification changing circuits provided corresponding to the memory blocks, the specification changing circuits being set in response to activation of a corresponding block selection signal during a test mode, outputting the operating specification signal indicating the second operating specification while being set, and outputting the operating specification signal indicating the first operating specification when not being set; and a plurality of timing control circuits provided corresponding to the block control circuits, the timing control circuits each having a precharge generator which outputs the precharge control signal and changes an output timing of the precharge control signal according to the operating specification signal from the program circuit or the specification changing circuit.