Patent ID: 7250372

Claim:
A method for adjusting bottom anti-reflective coating over-etch time using real time process feedback to achieve a critical dimension CD final , comprising: providing a plurality of semiconductor wafers with each of said plurality of wafers, comprising: a first layer over a semiconductor, a bottom anti-reflective coating layer over said first layer, a patterned photoresist layer over said bottom anti-reflective coating layer wherein said patterned photoresist layer has a first pattern comprising a critical dimension CD resist ; selecting a first wafer from said plurality of semiconductor wafers; etching said bottom anti-reflective coating layer of said first wafer to a first critical dimension CD′ pre ; determining a first over-etch time t* from said CD resist of said first wafer; further etching said bottom anti-reflective coating layer of said first wafer from said first critical dimension CD′ pre to a second critical dimension CD′ post using said first over-etch time; using said further etched bottom anti-reflective coating layer, pattern said first layer and measure CD′ final for said first wafer; determine a second over-etch time t lot from said CD′ final ; etching said bottom anti-reflective coating layer of each of said remaining plurality of wafers to a first critical dimension CD pre (x), wherein CD pre (x) is a first critical dimension for a wafer x in said plurality of wafers; using said second over-etch time t lot , determine a bottom anti-reflective coating over-etch time t(x) for each of said plurality of wafers, wherein t(x) is a bottom anti-reflective coating over-etch time for a wafer x in said plurality of wafers; determining a slope S and an intercept I from a CD bias versus bottom anti-reflective coating over-etch time graph; and wherein said first over-etch time t* is determined using a relationship t*=(CD′ resist −CD target −I)/S.