Patent ID: 8614920

Claim:
A Flash memory device which includes a capability of outputting logic data in response to a set of logic read commands, comprising: an external signal input; an addressable Flash memory cell array; a data register coupled to the addressable Flash memory cell array for receiving and storing array data from the addressable Flash memory cell array; a plurality of registers for storing logic data; a command and control logic circuit comprising: pre-fetch logic coupled to the external signal input for pre-fetching logic data from one of the logic data registers in accordance with a particular one of the plurality of logic read commands when a first partial sequence of most significant bits of a command received on the external signal input is predictive of the particular logic data read command; and output control logic coupled to the external signal input for generating a predicted logic read command signal when a second partial sequence of most significant bits of a command received on the external signal input is predictive of any one of the plurality of logic data read commands; and an output pad circuit coupled to the data register, the pre-fetch logic, the output control logic, and the external signal line for selecting and outputting the logic data from the pre-fetch logic when the predicted logic read command signal and a portion of the command other than the first and second partial sequences resolve receipt of any one of the plurality of logic data read commands.