Patent ID: 8372710

Claim:
A method for forming a transistor for an integrated circuit, the method comprising: forming a U-shaped silicon pillar pair connected by a base portion, wherein the silicon pillar pair comprises a first pillar and a second pillar, the first and second pillars each having an inner wall, first and second outer sidewalls and an end wall, wherein the inner walls of the first and second pillars face each other, the end walls of the first and second pillars face away from each other, and the outer sidewalls connect the inner and end walls of each of the first and second pillars, and wherein the base portion has a first outer sidewall coplanar with the first outer sidewalls of the first and second pillars, and a second outer sidewall coplanar with the second outer sidewalls of the first and second pillars; forming a source region in the first pillar; forming a drain region in the second pillar; and forming a first gate line facing the first outer sidewalls of the first pillar, second pillar, and base portion, wherein the source region, the drain region, and at least a portion of the gate line form a U-shaped transistor.