Patent ID: 8129759

Claim:
A semiconductor integrated circuit (IC) package which comprises: a substrate having a die attachment area and having a first ground plane arranged thereon wherein the die attachment area has a die attached thereto, with the die having high speed circuitry and low speed circuitry, the low speed circuitry of the die is electrically connected exclusively with the first ground plane and a first set of I/O contacts that are separated from each other by a first spacing distance, and the high speed circuitry of the die is electrically connected exclusively with second ground plane and the second set of I/O contacts that are separated from each other by a second spacing distance; a plurality of electrical connections that electrically connect the first ground plane with electrical contacts that are to be connected with an external ground; a second ground plane that is spatially separated and electrically isolated from the first ground plane, wherein the high speed circuitry of the die is electrically connected exclusively with second ground plane and the second set of I/O contacts; a plurality of additional electrical connections that electrically connect the second ground plane with electrical contacts that are to be connected with an external ground; electrical I/O contacts connected with the die and enabling electrical connection of the package with external circuitry wherein the I/O contacts comprise: the first set of I/O contacts spaced and configured for electrical connection with low speed electronic circuitry; and the second set of I/O contacts spaced and configured for electrical connection with high speed electronic circuitry; and wherein the substrate includes a plurality of layers, and wherein; a first layer of the substrate includes, the first ground plane, and the second ground plane; a second layer of the substrate includes, a third ground plane configured for electrical connection with low speed electronic circuitry, and a fourth ground plane that is spatially separated and electrically isolated from the third ground plane, the third ground plane configured for electrical connection with high speed electronic circuitry; and at least one reference plane associated with each layer of the substrate and the ground planes included thereon; and wherein the first spacing distance includes a first dielectric material between the contacts of the first set of I/O contacts and the second spacing distance includes a second dielectric material between the contacts of the second set of I/O contacts, wherein the first dielectric material establishes the first differential impedance and wherein the second dielectric material establishes the second differential impedance, wherein the second differential impedance is greater than the first differential impedance.