Patent ID: 7180783

Claim:
A non-volatile semiconductor memory device, comprising: a cell array comprising a plurality of memory cells arranged in a plurality of rows and columns; a page buffer circuit comprising a plurality of page buffers corresponding to the plurality of columns, respectively, each page buffer comprising a first register that is configured to store programming data for a page memory cells and a second register that is configured to store contents of the first register and outside input data; a pass/fail check circuit that is configured to generate a programming verification result for the pages of memory cells responsive to the contents of the first registers; and a pass/fail check latch circuit that is configured to store the programming verification result, comprising: a first check latch configured to store the pronmniing verification result with respect to k-numbered page of memory cells (where, k=1, 2 . . . , n); a second check latch configured to store the programming verification result with respect to the k-1 numbered page of memory cells; and a third check latch that is configured to detect whether a page has been unsuccessfully programmed based on the programming verification result for that page stored in the first check latch, wherein if a page has been detected as having been unsuccessfully programmed once, then the third check latch maintains a “fail” state value until a successful program operation is performed with respect to all n pages.