Patent ID: 7018854

Claim:
A method for manufacturing a semiconductor device, comprising: depositing a lower electrode layer forming film, a ferroelectric layer forming film, and an upper electrode supporting layer forming film in this order on a semiconductor substrate; depositing an upper electrode supporting layer forming mask on the upper electrode supporting layer forming film; forming an upper electrode supporting layer in a region where a ferroelectric capacitor is formed by using the upper electrode supporting layer forming mask; depositing a lower electrode layer forming mask on the ferroelectric layer forming film in the presence of the upper electrode supporting layer forming mask; forming a ferroelectric layer and a lower electrode layer in a region where the ferroelectric capacitor is formed and in a region where the lower electrode layer is formed extending in a first direction including the region where the ferroelectric capacitor is formed, respectively, by using the upper electrode supporting layer forming mask and the lower electrode layer forming mask; forming an insulating layer on a whole upper surface of the semiconductor substrate from which the upper electrode supporting layer forming mask and the lower electrode layer forming mask have been removed; exposing an upper surface of the upper electrode supporting layer that is to be the region where the ferroelectric capacitor is formed to an upper surface of the insulating layer; and forming an upper electrode layer extending in a second direction on the insulating layer to which the upper surface of the upper electrode supporting layer has been exposed so as to include the region where the ferroelectric capacitor is formed; the lower electrode layer extending in the first direction and the upper electrode layer extending in the second direction being provided on the semiconductor substrate with the ferroelectric layer and the upper electrode supporting layer therebetween, and the ferroelectric capacitor being disposed at an intersection of the lower electrode layer and the upper electrode layer.