Patent ID: 7957183

Claim:
A memory control apparatus for programming SMT MRAM cells arranged in rows and columns within an array of an SMT MRAM device, the memory control apparatus comprising a plurality of single bit lines connecting columns of the SMT MRAM cells for receiving an in-phase data signal; a plurality of source lines connecting pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal; a plurality of out-of-phase switching devices, each out-of-phase switching device comprising a first port connected to at least one source line of the plurality of source lines for selectively transferring the out-of-phase signal to the at least one source line, a second port connected to receive the out-of-phase data signal, and a control port connected to receive a source line select signal for activating the switching device for transferring the out-of-phase data signal to the at least one source line; and a plurality of column select transistors, each of the plurality of column select transistors comprising a first port connected to one of the plurality of single bit lines, a second port connected to receive the in-phase data signal, and a control port connected to receive a column select signal for selecting one of the columns of the SMT MRAM cells.