Patent ID: 8914563

Claim:
An integrated circuit comprising: a shared synchronization bus including a plurality of channels assigned to one or more of a plurality of peripheral modules; and a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels to synchronize the first peripheral module and the second peripheral module to an event independent of a clock signal; and a programmable counter array (PCA) having a PCA controller, the PCA controller comprises: a multiplexer including a plurality of inputs to receive a respective plurality of periodic signals, a select input, a first output, and a second output; a clock divider including an input coupled to the first output of the multiplexer; and a counter including a first input coupled to an output of the clock divider, and a second input coupled to the second output of the multiplexer, and an output coupled to the shared synchronization bus.