Patent ID: 7202697

Claim:
An integrated circuit, comprising: an interconnect structure; a plurality of memory cells coupled together in series to form a shift register, each bit of the shift register comprising two paired memory cells implementing a master latch and a slave latch, the shift register being coupled to receive a shift clock signal; a multiplexer structure having a plurality of data input terminals, a plurality of select input terminals, and an output terminal coupled to the interconnect structure, each data input terminal being coupled to an output terminal of a corresponding one of the memory cells; and a bypass select multiplexer having an output terminal coupled to a first one of the select input terminals of the multiplexer structure, the first one of the select input terminals being coupled to select a signal from each pair of the memory cells, the bypass select multiplexer further having two data input terminals, one of the data input terminals being coupled to receive the shift clock signal.