Patent ID: 7277479

Claim:
A processing element for filtering an input digital signal according to a function defined by a series of coefficients, the processing element comprising: a series of connected digit processing units (DPUs), a first DPU of the series receiving the input digital signal, each DPU comprising: a delay unit receiving the input digital signal from an input of the processing unit or from the previous DPU for storing and delaying the input digital signal; a multiplexer capable of selecting a delayed digital input signal from the delay unit or an un-delayed digital input signal bypassing the delay unit, an output of the multiplexer for connecting to a delay unit and a multiplexer of a next stage DPU; a coefficient multiplier connected to the output of the delay unit for multiplying the delayed input digital signal by a coefficient and outputting a product; and a serial-in-parallel-out (SIPO) shift register capable of serially receiving control signals and outputting control signals to the coefficient multiplier and the multiplexer; an adder connected to the coefficient multipliers for summing the products of the coefficient multipliers, wherein the adder outputs a filtered digital signal; a second register connected to the adder for storing a number of negative products determined by the coefficient multipliers for performing two's complement arithmetic with the adder; and a sign extension generator connected to the adder for generating sign extension bits of the products of the coefficient multipliers; wherein a group of DPUs have multiplexers set so that the delay unit of each DPU stores a same part of the digital signal and processes a single coefficient of the series of coefficients.