Patent ID: 7310270

Claim:
A semiconductor memory device comprising: a memory cell array including NAND type cells each of which includes memory cells connected in series; an erasing circuit configured to erase data stored in at least one memory cell; an over-erasure detecting circuit configured to detect whether the at least one memory cell is over-erased after the erasing circuit erases the data stored in the at least one memory cell; a first signal line connected to first ends of the NAND type cells; a second signal line connected to second ends of the NAND type cells; and a read circuit configured to be connected to the first signal line and to read a threshold voltage of at least one memory cell, wherein the read circuit comprises a first switch configured to connect the first signal line to a first node, a sense amplifier configured to sense a voltage of the first node, and a capacitor connected between the first node and a second node, and the read circuit transfers a voltage of the first signal line to the first node through the first switch, turns off the first switch, changes the voltage of the first node by changing the voltage of the second node, and senses the voltage of the first node by the sense amplifier.