Patent ID: 7542030

Claim:
A display panel driving circuit, comprising: a shift register configured to store first video data corresponding to a size of one line of a panel in response to a first control signal; a memory configured to store second video data in response to a second control signal and output an amount of the second video data corresponding to the size of one line of the panel; a line packing circuit configured to control a size of the first video data output from the shift register and a position of the first video data on the display panel, and output the first video data and the second video data in a first output mode or a second output mode in response to a third control signal; a gate line sorting circuit configured to control an enabling sequence of first through nth gate line signals for enabling n gate lines of the panel in response to a fourth control signal according to whether the first video data and the second video data are output in the first output mode or second output mode; a gate driver circuit configured to enable gate lines of the display panel in response to the gate line signals output from the gate line sorting circuit and a fifth control signal; and a source driver circuit configured to provide the first video data and the second video data output from the line packing circuit to the display panel in response to a sixth control signal, wherein, in the first output mode, the first and second video data are alternately output, and in the second output mode, the first video data is output for a first predetermined period of time and then the second video data is output for a second predetermined period of time.