Patent ID: 8058176

Claim:
A method of forming an integrated circuit device, comprising: forming an integrated circuit substrate having an electrically insulating layer thereon; forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer; simultaneously etching first and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, at first and second different etch rates that yield a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening, by exposing the first and second portions of the electrically insulating layer to an etching gas comprising C x F y , where 2xâ‰§y, x>0 and y>0; and then simultaneously etching the first and second trenches to substantially the same depths using an etching process that compensates for the first and second different etch rates associated with etching the first and second portions of the electrically insulating layer, said etching process comprising exposing the first and second trenches to an etching gas comprising C xâ€² F yâ€² , where 2xâ€²â‰¦yâ€², xâ€²>0 and yâ€²>0; wherein a first width of the first openings is smaller than a second width of the second openings.