Patent ID: 8146035

Claim:
A method for estimating power consumption of a circuit from a circuit design to be analyzed, the method comprising: simulating a plurality of one or more sample circuit designs, wherein each sample circuit design includes circuit elements of one or more structural templates, and the simulating outputs toggle rates for the circuits elements of the sample circuit designs; determining for each structural template, from the output toggle rates, an equation for at least one of the one or more circuit elements of the structural template; establishing a database of the structural templates, each structural template having the equation as associated information descriptive of a toggle rate of the one or more circuit elements of the structural template; storing a representation of the circuit design to be analyzed, the representation specifying a plurality of circuit elements for implementing the circuit design to be analyzed; matching the circuit elements of the circuit design to be analyzed to the structural templates in the database by a computing arrangement; determining, by the computing arrangement, respective estimated toggle rates for the circuit elements of the circuit design to be analyzed based on the information descriptive of one or more toggle rates associated with the matched structural templates in the database; determining, by the computing arrangement, an estimated power consumption level of the circuit design to be analyzed as a function of the estimated toggle rates of the circuit elements; and outputting data indicative of the estimated power consumption level by the computing arrangement.