Patent ID: 8861648

Claim:
A receiving device, comprising: a reception section that receives an analog signal; a extraction section that extracts a clock signal having a same frequency as that of a symbol rate of the analog signal from the analog signal received by said reception section; a converter that samples the analog signal received by said reception section in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal; a controller that demodulates the digital signal converted by said converter and computes a phase of said sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal; and adjustment section that adjusts a phase of the clock signal extracted by said extraction section to the phase computed by said controller and generates the clock signal having the adjusted phase as said sampling clock signal; wherein said extraction section includes either: 1) a band pass filter that extracts a signal having the same frequency as that of the symbol rate of the analog signal as a basic clock signal from the analog signal received by said reception section; and a phase synchronous loop that locks a phase of the basic clock signal extracted by said band pass filter so as to generate the basic clock signal having the locked phase as said clock signal; or 2) an injection lock voltage control oscillator that locks its oscillation frequency at the same frequency as that of the symbol rate of the analog signal received by said reception section and generates a signal having the locked oscillation frequency as a basic clock component signal; and a phase synchronous loop that locks a phase of the basic clock component signal generated by said injection lock voltage control oscillator and generates the basic clock component signal having the locked phase as said sampling clock signal; or 3) a band pass filter that extracts a signal having the same frequency as that of the symbol rate of the analog signal as a basic clock signal from the analog signal received by said reception section; an injection lock voltage control oscillator that locks its oscillation frequency at the frequency of the basic clock signal extracted by said band pass filter and generates a signal having the locked oscillation frequency as a basic clock component signal; and a phase synchronous loop that locks a phase of the basic clock component signal generated by said injection lock voltage control oscillator and generates the basic clock component signal having the locked phase as said sampling clock signal.