Patent ID: 7714393

Claim:
A semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device comprising: a first insulating layer and a second insulating layer configured to be formed on the first insulating layer; and gate electrode contact plugs configured to penetrate the second insulating layer and be each connected to a respective one of gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor, and source/drain region contact plugs configured to penetrate the first insulating layer and the second insulating layer and be each connected to a respective one of source/drain regions, wherein each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer, the gate electrode of the N-channel insulated gate field effect transistor has a bottom part, a side part, and a center part surrounded by the bottom part and the side part, and at least the bottom part and the side part are composed of a first conductive material, the gate electrode of the P-channel insulated gate field effect transistor has a bottom part, a side part, and a center part surrounded by the bottom part and the side part, and at least the bottom part and the side part are composed of a second conductive material different from the first conductive material, protective layers having electric conductivity are each formed on a top surface of a respective one of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor, and the gate electrode contact plug for the N-channel insulated gate field effect transistor is connected via the protective layer to the top surface of the gate electrode of the N-channel insulated gate field effect transistor, and the gate electrode contact plug for the P-channel insulated gate field effect transistor is connected via the protective layer to the top surface of the gate electrode of the P-channel insulated gate field effect transistor.