Patent ID: 7574316

Claim:
A semiconductor test apparatus to test a semiconductor circuit, the semiconductor test apparatus comprising: a pattern generator which generates a test pattern for testing the semiconductor circuit; a waveform shaper which shapes a test signal to be supplied to the semiconductor circuit based on the test pattern; a pulse width adjusting circuit which generates a timing signal for determining a phase of the test signal by adjusting a pulse width of an input pulse signal, and outputs the timing signal to the waveform shaper, the pulse width adjusting circuit including: a first delay circuit which outputs a first delay signal generated by delaying the pulse signal by a certain delay time; a second delay circuit which outputs a second delay signal generated by delaying the pulse signal by a different delay time from the first delay circuit; and an output section which, in accordance with the first and second delay signals, generates and outputs the timing signal having a pulse width corresponding to a difference between the delay times respectively achieved by the first and second delay circuits; and a judging section which judges whether the semiconductor circuit is good or bad based on an output signal output from the semiconductor circuit.