Patent ID: 7411433

Claim:
A reset ramp control structure, comprising: a reset system element, coupled to the voltage to be monitored; and a fast ramp down detection element, which is coupled to the reset system element, and wherein during a ramp down condition of the voltage to be monitored the fast ramp down detection element forces an output of the reset system element to a known value and wherein during a slow ramp down condition of the voltage to be monitored the output of the reset system element is not forced by the fast ramp down detection element, and wherein the fast ramp down detection element further comprises: the voltage to be monitored is coupled to an anode of a diode; a first resistive element is coupled between a cathode of the diode and ground, and to an input terminal of an inverter; a gate of a transistor is coupled to an output of the inverter; a source of the transistor is coupled to ground; and a drain of the transistor is coupled to an output of the reset system element and to a capacitor.