Patent ID: 8861583

Claim:
An equalizer circuit for a data link, the equalizer circuit comprising: a continuous-time linear equalizer for receiving a received signal and outputting an equalized signal; a first circuit loop comprising an error sense-amplifier latch which receives the equalized signal and outputs an error signal, wherein the first circuit loop determines a first average signal amplitude, wherein the first average signal amplitude comprises an average signal amplitude of the equalized signal; a second circuit loop comprising a data sense-amplifier latch which receives the equalized signal and outputs a data signal, wherein the second circuit loop determines a second average signal amplitude, and wherein the second average signal amplitude comprises an average signal amplitude of a high-frequency portion of the equalized signal; a decision feedback equalization (DFE) adaptation circuit which receives the data signal from the data sense-amplifier latch and the error signal from the error sense-amplifier latch and which outputs a DFE gain signal; a signal multiplier which multiplies the data signal from the data sense-amplifier latch with the DFE gain signal to generate an adjustment signal; and a signal adder which adds the adjustment signal to the equalized signal from the continuous-time linear equalizer.