Patent ID: 7269047

Claim:
A memory addressing system for reducing number of times addressed memory cells are read in an array of memory cell rows and memory cell columns, wherein each memory cell includes a memory element and a switch, the system comprising: read/program lines, wherein each read/program line electrically connects read/program controls of memory elements of one row of memory cells, and wherein data is stored in the memory elements; row-select lines, wherein each row-select line electrically connects controls of switches of one row of memory cells; column-select lines, wherein each column-select line is connected, via switches, to the memory elements of one column of memory cells; a column decoder for decoding addresses of addressed memory cells, wherein the decoded addresses are used to connect a particular column-select line to an output circuit; a row decoder for decoding addresses of addressed memory cells, wherein the decoded addresses are used to apply a turn-on voltage to a particular row-select line and to apply a controlled voltage to a particular read/program line after the decoded address from the row decoder goes through a voltage translator for determination of an appropriate voltage; a voltage translator for applying an appropriate voltage to a read/program line determined by the decoded address, for programming or reading the memory elements of the memory cells of the corresponding row; an output circuit including a current limiter, a sense amplifier, and a latch, wherein data from a memory element, via a corresponding switch and a column-select line, passes through the current limiter and is evaluated by the sense amplifier and is stored as a digital data by the latch and is available at an output of the latch; and an address-transition decoder and comparator for monitoring the addresses of addressed memory cells and for sending control signals to the voltage translator and to the latch, or to the voltage translator, the sense amplifier, and to the latch, to read the addressed memory cell and latch its data content when the addressed memory cell has not been read in the previous read cycle, or to utilize the latched data in place of reading the addressed memory cell when the addressed memory cell data content had been read and latched in the previous read cycle.