Patent ID: 8921938

Claim:
A transistor comprising: a p-type well; an n-type well, wherein at least a part of the p-type well is extended into at least a part of the n-type well to form an overlapping region of the p-type well and the n-type well; a source region formed on the p-type well; a drain region formed on the n-type well; a gate region; a first shallow trench isolation region adjacent to the drain region; and a second shallow trench isolation region adjacent to the drain region, wherein at least a corresponding portion of each of (i) the first shallow trench isolation region and (ii) the second shallow trench isolation region is formed on the n-type well, wherein the overlapping region of the p-type well and the n-type well (i) at least partially covers the first shallow trench isolation region and (ii) covers an entire region underneath the gate region, and wherein the overlapping region of the p type well and the n type well does not cover the second shallow trench isolation region.