Patent ID: 7206802

Claim:
A binary adder circuit, comprising: a carry logic circuit configured to receive a plurality of first group generate signals, an associated plurality of second group generate signals, and a plurality of group propagate signals and configured to produce a plurality of pairs of associated complementary carry signals in response to the first group generate signal, the associated second group generate signal, and the group propagate signal; wherein the carry logic circuit comprises a plurality of gate combinations, wherein each of the plurality of gate combinations is configured to generate one of the plurality of pairs of associated complementary carry signals in response to one of the plurality of first group generate signals, one of the associated plurality of second group generate signals, and one of the plurality of group propagate signals; wherein each of the plurality of gate combinations is further configured as either a first gate combination or a second gate combination; wherein the first gate combination comprises a complex NAND/NOR gate combination; wherein the second gate combination comprises a complex AND-OR-INVERT (AOI)/OR-AND-INVERT (OAI) gate combination; and wherein the carry logic circuit further comprises at least one first gate combination and at least one second gate combination; and a first selection logic coupled to the carry logic circuit and configured to receive a first presum, a second presum, and a first pair of complementary carry signals, and configured to select either the first presum or the second presum as a summation, in response to the first pair of complementary carry signals; a carry look ahead (CLA) adder circuit coupled to the carry logic circuit and configured to receive a portion of an addend and a corresponding portion of an augend, and configured to produce one of the plurality of first group generate signals, one of the associated second group generate signals, and one of the group propagate signals; and wherein the portion of the addend and the portion of the augend comprise a plurality of ordered pairs of bits, and wherein the CLA adder circuit is configured to produce a local generate signal and a local propagate signal for each of the ordered pairs of bits, and wherein the group propagate signal is a product of the local propagate signals, and wherein the one of the plurality of first group generate signals and the one of the associated second group generate signals is a sum of products of the local generate and propagate signals.