Patent ID: 7185179

Claim:
A computer system having architecture of a parallel computer, comprising: a CPU module; a plurality of memory modules, each having a processor and RAM core; and a plurality of sets of buses that make (a) connections between the CPU module and memory modules or (b) connections among memory modules, or that make (a) and (b), wherein the processors of the plurality of memory modules operate on an instruction given by the CPU module to the processors of the memory modules, and wherein said architecture of a parallel computer manages at least one series of data having a stipulated relationship, each series of data being given a space ID, and the processor of each memory module manages a table that contains one or more sets of said space ID, the logical address of a portion of the series of data managed, the size of said portion and the size of the series of data, in which said processor of each memory module manages said portion of series of data such that said series of data is divided among the plurality of memory modules and, in response to an instruction including the space ID and the logical address from the CPU module, the processor of each memory module determines if the portion of the series of data managed is involved in the received instruction by reviewing the space ID and the logical address, reads data stored in the RAM core and sends data out on a bus, writes data given via the bus to the RAM core, performs (c) the necessary processing on the data or (d) updates said table, or performs (c) and (d).