Patent ID: 8369136

Claim:
A semiconductor memory comprising: a memory cell array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of bit lines, each bit line connected to a corresponding column of the memory cells; a column selection circuit configured to select at least one bit line of the plurality of bit lines in response to a column select signal; and a read circuit configured to precharge the selected at least one bit line in response to a precharge signal, apply a read bias to the precharged at least one bit line in response to a read bias provision signal, and read data from the memory cells connected to the precharged at least one bit line, wherein a resistance level of each memory cell of the plurality of memory cells varies according to data stored in the memory cell, the read circuit is configured to read data from a first memory cell of the plurality of memory cells in response to the precharge signal having a first pulse width and read data from a second memory cell of the plurality of memory cells in response to the precharge signal having a second pulse width, and a resistance of a bit line between the first memory cell and the read circuit is lower than a resistance of a bit line between the second memory cell and the read circuit, and the first pulse width of the precharge signal is smaller than the second pulse width of the precharge signal.