Patent ID: 8780574

Claim:
A double-sided printed circuit board comprising: a circuit plate comprising: a spacer layer comprising a first surface and an opposing second surface; a first multilayer structure arranged on the first surface, the first multilayer structure comprising a first wire layer formed on the first surface, a first middle layer formed on the first wire layer, and a second wire layer formed on the first middle layer, the second wire layer comprising a first grounding portion and a plurality of first conductive pattern portions; and a second multilayer structure arranged on the second surface, the second multilayer structure comprising a third wire layer formed on the second surface, a second middle layer formed on the third wire layer, and a fourth wire layer formed on the second middle layer, the fourth wire layer comprising a second grounding portion and a plurality of second conductive pattern portions; a first chip electrically mounted on the first grounding portion and electrically connected to the first conductive pattern portions; a second chip electrically mounted on the second grounding portion and electrically connected to the second conductive pattern portions; a plurality of first wires and a plurality of second wires, wherein the first chip comprises a first top surface and a plurality of first chip pads formed on the first top surface, the second chip comprises a second top surface and a plurality of second chip pads formed on the second top surface, the first chip pads are connected to the respective first conductive pattern portions through the first wires, and the second chip pads are connected to the respective second conductive pattern portions through the second wires; and a first protective layer and a second protective layer, wherein the first protective layer covers the first wires, the jointed portions between the first wires and the corresponding first chip pads, and the jointed portions between the first wires and the corresponding first conductive pattern portions, the first top surface comprises a first exposed region among the first chip pads and being free of the first protective layer, the second protective layer covers the second wires, the jointed portions between the second wires and the corresponding second chip pads, and the jointed portions between the second wires and the corresponding second conductive pattern portions, and the second top surface comprises a second exposed region among the second chip pads and being free of the second protective layer.