Patent ID: 8341487

Claim:
An apparatus, comprising: an LDPC (Low Density Parity Check) decoder circuitry for employing a plurality of configurations of a superimposed LDPC matrix for respectively decoding a plurality of LDPC coded signals, the superimposed LDPC matrix corresponding to LDPC codes of an in-place LDPC code set, wherein: each of the LDPC codes having a respective code rate; and each of the LDPC codes having a respective LDPC matrix; and a switching module for, based on a selected LDPC code of the in-place LDPC code set, selectively enabling or disabling sub-matrices of the superimposed LDPC matrix for within each of the plurality of configurations; and wherein: when the superimposed LDPC matrix being within a first of the plurality of configurations, the LDPC decoder circuitry decoding a first of the plurality of LDPC coded signals thereby generating a first plurality of information bit estimates; and when the superimposed LDPC matrix being within a second of the plurality of configurations, the LDPC decoder circuitry decoding a second of the plurality of LDPC coded signals thereby generating a second plurality of information bit estimates.