Patent ID: 8809179

Claim:
A semiconductor structure comprising: a substrate comprising a cell region and a non-cell region; a flash memory cell in the cell region, wherein the flash memory cell comprises a gate stack over the substrate, and a first gate over the substrate and comprising a vertical portion on a sidewall of the gate stack, the first gate being a selection gate; a metal-oxide-semiconductor (MOS) device in the non-cell region, wherein the MOS device comprises a second gate, with a top surface of the first gate and a top surface of the second gate substantially level with each other, wherein the first gate and the second gate are separate portions of a same patterned layer, and wherein any portion of the first gate directly over the gate stack of the flash memory cell has a first thickness less than a second thickness of the second gate; and a dummy gate over an insulation region in the substrate, wherein the dummy gate comprises same materials as the first and the second gates, and wherein the dummy gate has at least a top portion having a third thickness different from at least one of the first and the second thicknesses.