Patent ID: 8236703

Claim:
A method of fabricating an integrated circuit, comprising: forming a dielectric layer over a substrate; forming a metal layer comprising aluminum over the dielectric layer; patterning the metal layer to form a bond pad; forming a passivation layer over the dielectric layer and the bond pad; patterning the passivation layer, the patterning including depositing and patterning a photoresist layer over the passivation layer and dry etching the passivation layer through the patterned photoresist layer to form an opening to expose a part of a top surface of the bond pad; prior to removing the patterned photoresist layer from over the patterned passivation layer, etching to remove a minor portion of the thickness of the bond pad at the exposed part of the bond pad top surface using a wet etch solution comprising tetramethylammonium hydroxide (TMAH); and removing the patterned photoresist layer.