Patent ID: 7889832

Claim:
A bootstrap circuit which receives an input signal and a plurality of clock signals and generates an output signal, comprising: a first transistor that receives a first clock signal and that, when in a conductive state, outputs the first clock signal as the output signal; a first control unit that is connected to a control terminal of the first transistor and that renders the first transistor conductive, in response to the input signal; a second control unit that is connected to the control terminal of the first transistor and that renders the first transistor non-conductive in response to an input signal and to a second clock signal, the second clock signal having a phase lead by a half cycle or by one phase with respect to the first clock signal, with the plurality of clock signals constituting N-phase clocks, where N is an integer greater than or equal to two; and a third control unit that is connected to the control terminal of the first transistor and that renders the first transistor non-conductive, in response to a control signal, the control signal being different from the input signal.