Patent ID: 8140781

Claim:
A system comprising: a multi-level page-walk apparatus; an out-of-order memory controller coupled to the multi-level page-walk apparatus; and an Input/Output (I/O) device coupled to the multi-level page-walk apparatus and the out-of-order memory controller, the multi-level page-walk apparatus configured to receive a new page-walk request from the I/O device, the multi-level page-walk apparatus further configured to output the new page-walk request to the out-of-order memory controller, the out-of-order memory controller configured to fetch Page Table Entry (PTE) data from a system memory and output the PTE data to the multi-level page-walk apparatus and the I/O device; wherein the multi-level page-walk apparatus includes a demotion-based priority grant count arbiter coupled to the out-of-order memory controller, the demotion-based priority grant count arbiter configured to arbitrate between the new page walk request and at least one outstanding page-walk request.