Patent ID: 7492302

Claim:
In an analog-to-digital converter, an analog-to-digital conversion stage, comprising: a comparator operable to compare one of (a) an analog input signal and (b) a sample of the analog input signal with a threshold to generate a bit signal; and an analog residual signal generator operable to generate an analog residual signal from signals comprising the sample of the analog input signal and the bit signal, the analog residual signal generator comprising, in series: a summing element operable to sum a signal input thereto with a reference signal, a selective inverter preceding the summing element, the selective inverter operable in response to a first state of the bit signal to pass a signal input thereto and operable in response to a second state of the bit signal to invert the signal input thereto, and an amplifier, in which: the analog residual signal generator is operable to generate the analog residual signal such that, at a level of the analog input signal equal to the threshold of the comparator, the analog residual signal has a level independent of the state of the bit signal.