Patent ID: 8219833

Claim:
A method, in a data processing system, for two-level guarded predictive power gating of a set of units within the data processing system, the method comprising: for a monitoring interval, determining, by a success monitor of the data processing system, whether a unit within the set of units is power gated; responsive to the unit being power gated, determining, by the success monitor, whether a count of idle cycles for the unit is below a breakeven point; responsive to the count of the idle cycles being above the breakeven point, incrementing, by the success monitor, a success efficiency counter; responsive to the count of the idle cycles being below the breakeven point, determining, by the success monitor, whether the unit needs to be woke up; responsive to the unit needing to be woke up, incrementing, by the success monitor, a harmful efficiency counter; and responsive to the value of the harmful efficiency counter being less than the value from the success efficiency counter during the monitoring interval, enabling, by the success monitor, power gating for the unit via a first-level power-gating mechanism.