Patent ID: 8115550

Claim:
An apparatus comprising: a first amplifying unit including a first amplifier including a first NMOS transistor and a first PMOS transistor, which have a common source connecting the first NMOS transistor and the first PMOS transistor, and a second amplifier including a second PMOS transistor and a second NMOS transistor, which have a common drain connecting the second PMOS transistor and the second NMOS transistor, while being connected with the first amplifier in parallel; a second amplifying unit including a third amplifier including a third NMOS transistor and a third PMOS transistor, which have a common source connecting the third NMOS transistor and the third PMOS transistor, and a fourth amplifier including a fourth PMOS transistor and a fourth NMOS transistor, which have a common drain connecting the fourth PMOS transistor and the fourth NMOS transistor, while being connected with the third amplifier in parallel; and differential output nodes including a positive node connected to an output stage of the first amplifying unit, to which the common source of the first amplifier and the common drain of the second amplifier are connected, and a negative node connected to an output stage of the second amplifying unit, to which the common source of the third amplifier and the common drain of the fourth amplifier are connected.