Patent ID: 8558591

Claim:
A phase locked loop (PLL) comprising: a phase frequency detector powered by a first analog supply voltage; a charge pump coupled to the phase frequency detector, the charge pump powered by a second analog supply voltage, different from the first analog supply voltage; a voltage controlled oscillator (VCO) coupled to the charge pump, the VCO powered by a third analog supply voltage, different from the first analog supply voltage and different from the second analog supply voltage, wherein a frequency of the VCO is controlled by a control voltage; and a supply voltage provider having a first circuit node coupled to a fourth analog supply voltage, a second circuit node which provides the first analog supply voltage, a third circuit node which provides the second analog supply voltage, and a fourth circuit node which provides the third analog supply voltage, and a current compensator coupled to one of the second, third, or fourth circuit nodes, wherein the current compensator provides a variable current draw from the one of the second, third, or fourth circuit nodes based on the control voltage.