Patent ID: 8350272

Claim:
A semiconductor device having a plurality of standard cells, comprising: a semiconductor substrate having a main surface; a first conductive impurity region for functional elements which is formed over the main surface of the semiconductor substrate in at least one of the standard cells and forms functional elements; a second conductive impurity region for power potential which is formed over the main surface of the semiconductor substrate in the at least one of the standard cells and to which a power potential is applied; an insulating layer which is formed over the main surface of the semiconductor substrate and has throughholes reaching the main surface of the semiconductor substrate; and a conductive layer for contact which is formed in the throughholes of the insulating layer, wherein the conductive layer for contact is formed astride the impurity region for functional elements and the impurity region for power potential so as to electrically couple the impurity region for functional elements and the impurity region for power potential therethrough.