Patent ID: 7142544

Claim:
An ATM (Asynchronous Transfer Mode) PON (Passive Optical Network) ONU (Optical Network Unit) controlling apparatus, comprising: a cell receiving means for receiving an ATM cell from the PON downstream data and transferring the ATM cell through a receiving UTOPIA interfacing means to an external device and transferring a message in a PLOAM (Physical Layer Operation and Maintenance) cell to a message processing means by demultiplexing; a cell transmitting means for transmitting the ATM cell received through a transmitting UTOPIA interfacing means in a granted slot and transferring in upstream by loading the message being on standby in payload of the PLOAM cell when the PLOAM cell is transmitted; and the message processing means for setting internal signals by processing the received message or instructing operation of a plurality of functional blocks, and transferring the message requested by the plurality of functional blocks through the cell transmitting means; wherein an external transceiver generates from received bit stream a recovered byte clock and associates received byte stream by blindly gathering every 8 bits to byte for downstream data regardless of correct byte boundaries, and a following byte delineation logic selects correct byte stream out of 8 possible bits shifted byte streams by monitoring a cell delineation result; wherein the cell receiving means generates a pulse which indicates a start of a frame reference, and the pulse is delayed before setting a start point of counters governing an upstream frame timing, thus implementing desired amount of a relative phase difference between downstream frames and upstream frames; wherein an initial pulse delay is done for an initial delay amount before conducting ranging, but after ranging, an amount of time delay received from an optical line termination (OLT) is added to the delay amount so that a round trip time for the ONU becomes equal to a pre-defined round trip time used for all ONUs; and wherein the amount of the pulse delay also reflects the difference of from 0 to 7 bits between the recovered byte clock and the selected correct byte stream phase, and of total delay which is in unit of bits, the amount which can be delayed in byte processing with byte clock is applied in byte processing logic and a remaining bit delay of from 0 to 7 bits is applied in the cell transmitting means by shifting the data bit-wise, and also the remaining bit delay information is outputted from the chip so that the laser enable signal can also be equivalently delayed with external bit processing logic to thereby remove the uncertainty of measured RTT value arising from the blindness of the byte clock recovery after power-up and makes the RTT value to appear to be the same every time the ONU system is powered up or byte clock is newly recovered with different random phase with respect to the correct byte boundaries.