Patent ID: 8327168

Claim:
A power throttling method for a memory controller in a computer system comprising a power supply module including a plurality of power supplies, the method comprising: receiving, by a power output monitor from the plurality of power supplies, corresponding status signals indicative of status of the corresponding power supplies; responsive to the received status signals, the power output monitor determining whether a total power supply capacity of the power supply module is below a system power requirement, where at least one of the received status signals indicates that at least a corresponding one of the power supplies has a fault condition; responsive to determining that the total power supply capacity is below the system power requirement, the power output monitor driving a throttle control signal to the memory controller to a level indicative of an over-threshold state; storing plural throttle values in the memory controller, the plural throttle values for setting respective different rates of memory operation cycles issued by the memory controller to one or more memory devices; and responsive to the throttle control signal being driven to the level indicative of the over-threshold state, selecting by the memory controller a lower value of the plural throttle values to cause issuance of memory operation cycles to the one or more memory devices at a reduced rate.