Patent ID: 8247287

Claim:
A method for fabricating a power transistor device comprising: forming a buffer layer of a first conductivity type on a substrate of a second conductivity type opposite to the first conductivity type, the buffer layer having a top surface, a first thickness, and a first doping concentration; forming an epitaxial layer of the first conductivity type over the buffer layer, the epitaxial layer having a top surface, a second thickness which is greater than the first thickness, and a second doping concentration; forming first and second trenches in the epitaxial layer that define a mesa which comprises at least a portion of the buffer layer and the epitaxial layer, the mesa having first and second sidewall portions, and a first lateral width, the first and second trenches each having a second lateral width and a bottom; forming a dielectric material in each of the first and second trenches; forming a body region of the second conductivity type in the mesa, the dielectric material covering each of the first and second sidewall portions from at least just beneath the body region down to the bottom; forming first and second regions in the mesa, the first region being of the first conductivity type and the second region being of the second conductivity type, the first region laterally adjoining the second region, the body region separating the first and second regions from a drift region that extends from the body region to the top surface of the buffer layer; and forming a gate member in each of the trenches at or near the top surface of the epitaxial layer, the gate member being disposed adjacent to and insulated from the body region.