Patent ID: 7696025

Claim:
A method for fabricating a semiconductor structure, the method comprising: providing a substrate, a semiconductor region, a gate dielectric region, and a gate block, wherein the semiconductor region, the gate dielectric region, and the gate block are on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate block, wherein the semiconductor region is electrically insulated from the gate block by the gate dielectric region, wherein the semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate, and wherein the semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate; forming a channel cap region over a portion of the semiconductor region and over and in contact with only a first portion of a top surface of the gate block, said top surface of the gate block comprising a first portion and a second portion; forming a gate region from the gate block; and forming first and second source/drain regions in the semiconductor region, wherein the first and second source/drain regions are aligned with the gate region.