Patent ID: 8664981

Claim:
A semiconductor device comprising: a first wiring configured to be inputted a first input signal; a second wiring configured to be inputted a second input signal; a third wiring configured to be inputted a third input signal; a fourth wiring; a first transistor including a gate, a source and a drain; a second transistor including a gate, a source and a drain; a third transistor including a gate, a source and a drain; a fourth transistor including a gate, a source and a drain; a fifth transistor including a gate, a source and a drain; and a sixth transistor including a gate, a source and a drain, wherein one of the source and the drain of the fifth transistor is electrically connected to the first wiring; wherein one of the source and the drain of the sixth transistor is electrically connected to the first wiring; wherein the gate and one of the source and the drain of the first transistor are electrically connected to the other of the source and the drain of the fifth transistor, wherein the gate and one of the source and the drain of the second transistor are electrically connected to the other of the source and the drain of the sixth transistor, wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein one of the source and the drain of the third transistor are electrically connected to the second wiring, wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, wherein one of the source and the drain of the fourth transistor is electrically connected to the third wiring, wherein the fourth wiring is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor, and wherein a voltage which is given to the fourth wiring is a voltage of an output signal.