Patent ID: 7913204

Claim:
A high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description, comprising: a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description; a scheduling result inputting/outputting unit configured to extract a point to be allocated to a register from the data flow graph and output register information indicating the point, the scheduling result inputting/outputting unit being provided with dynamic analysis data that includes at least one of a number of times that data at the point has been substituted and a number of times that a value stored at the point has changed by a predetermined simulation; an allocating unit configured to consult dynamic analysis data and allocate circuit elements to the behavioral description; and an RTL description generating unit configured to generate the logic circuit based on the allocation of circuit elements by the allocating unit.