Patent ID: 7382670

Claim:
A semiconductor integrated circuit device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix shape; a plurality of bit lines connected to the memory cells; a plurality of column select transistors connected to the bit lines; a column decoder which selects the column select transistor; a first load circuit for write which is connected to even bit lines of the bit lines and supplies potential according to write data to the even bit lines at the time of writing data; and a second load circuit for write which is connected to odd bit lines in the bit lines and supplies potential according to write data to the odd bit lines at the time of writing data, wherein when a bit line stress test is carried out, in the case of an all bit-stress test, the column decoder selects all the column select transistors and supplies a high voltage for write from the first load circuit for write and the second load circuit for write to the even bit lines and the odd bit lines, in the case of an even bit-stress test, the column decoder selects all the column select transistors, supplies the high voltage for write from the first load circuit for write to the even bit lines, and supplies a lower potential than the above high voltage from the second load circuit for write to the odd bit lines, and in the case of an odd bit-stress test, the column decoder selects all the column select transistors, supplies the lower potential than the above high voltage from the first load circuit for write to the even bit lines, and supplies the high voltage for write from the second load circuit to the odd bit lines.