Patent ID: 7404059

Claim:
A method for managing state information in a processor, the method comprising: providing a lookup table including a number of memory circuits (“N M ”), each memory circuit having a plurality of entries, wherein entries in different ones of the memory circuits are accessible in parallel; storing a number of items of state information (“N S ”) belonging to a first state version in a first group of entries selected from the entries in the N M memory circuits, wherein each entry in the first group is in a different one of the N M memory circuits from each other entry in the first group; receiving an updated value for a first one of the N S items of state information while the first state version is in use by at least one thread executing in the processor; copying all of the N S items of state information in parallel from the first group of entries to a second group of entries selected from the entries in the N M memory circuits, thereby creating a second state version, wherein each entry in the second group is in a different one of the N M memory circuits from each other entry in the second group; and replacing the copy of the first one of the N S items in the second group of entries with the updated value.