Patent ID: 8683175

Claim:
A method of interfacing between a multi-threaded processing core and a hardware accelerator, wherein multiple threads are operating on the processing core, the method comprising: reserving in a buffer on the hardware accelerator a respective one or more entries for each of the multiple threads; copying from the multi-threaded processing core to the hardware accelerator memory address translations related to a specified operation for each of the multiple threads; and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the multiple threads in the one or more entries reserved for said each of the multiple threads in the buffer on the hardware accelerator; whereby when any one of the multiple threads operating on the multi-threaded processing core instructs the hardware accelerator to perform the specified operation related to said any one of the threads, the hardware accelerator has stored thereon one or more of the memory address translations for said any one of the multiple threads to facilitate starting said specified operation without memory translation faults.