Patent ID: 8522095

Claim:
An integrated circuit comprising: A. a test data in lead; B. a test clock in lead; C. a test mode select in lead; D. a test data out lead; E. an instruction register coupled with the test data in lead and the test data out lead, the instruction register having a control input and a control output; F. a data register coupled with the test data in lead and the test data out lead, the data register having a control input coupled to the control output of the instruction register; G. test access port circuitry including state machine circuitry having a test mode select input coupled with the test mode select in lead, an input coupled with the test clock in lead, and control outputs coupled with the control inputs of the instruction register and the data register; H. address circuitry that has an input coupled to the test data in lead, an input coupled to the test clock in lead, a control input, and an enable output; I. state monitor circuitry having an input coupled to the test clock in lead, an input coupled to the test mode select in lead, and a control output coupled to the control input of the address circuitry; and J. gating circuitry having an input connected to the enable output, an input connected with the test mode select in lead, and an output connected with the test mode select input of the state machine circuitry.