Patent ID: 7475377

Claim:
A method of manufacturing a semiconductor device that comprises determining parasitic resistance and capacitance from a layout of an LSI, comprising: providing a plurality of patterns of a wiring structure which contains a target interconnection; and producing a library configured to store a first parameter indicating said parasitic resistance and a second parameter indicating said parasitic capacitance in relation to said target interconnection to each of said plurality of patterns, wherein: said producing comprises calculating said parasitic resistance and said parasitic capacitance in each of a plurality of conditions to each of said interconnections contained in said layout by referring to said parameters stored in said library; each of said parameters being defined within a predetermined range; said parameters do not take a border value at a same time in manufacture of said wiring structure for each of said plurality of patterns; and generating a netlist with parasitic RC by adding the calculated parasitic resistance and the calculated parasitic capacitance to said netlist.