Patent ID: 7719313

Claim:
A buffer circuit comprising: a first differential signal input node; a second differential signal input node; a first differential signal output node; a second differential signal output node; a first field effect transistor (FET) having a source, a drain and a gate, wherein the gate is coupled to the first differential signal input node, and wherein the source is directly coupled to the first differential signal output node; a second field effect transistor (FET) having a source, a drain and a gate, wherein the drain is coupled to the drain of the first FET, wherein the gate is coupled to the second differential signal input node, and wherein the source is directly coupled to the second differential signal output node; and a latch having a first input node and a second input node, wherein the first input node of the latch is the first differential signal output node, and wherein the second input node of the latch is the second differential signal output node, wherein the latch further comprises: a third field effect transistor (FET) having a source, a drain, and a gate; a fourth field effect transistor (FET) having a source, a drain and gate, wherein the drain of the fourth FET is directly coupled to the source of the second FET and the drain of the third FET is directly coupled to the source of the first FET; a first resistor having a first terminal coupled to the source of the third FET and a second terminal coupled to ground; a second resistor having a first terminal coupled to the source of the fourth FET and a second terminal coupled to ground; and a capacitor having a first terminal and a second terminal, the first terminal being coupled to the source of the third FET and the first terminal of the first resistor, and the second terminal being coupled to the source of the fourth FET and the first terminal of the second resistor; wherein the drain of the third FET is coupled to the gate of the fourth FET, wherein the gate of the fourth FET is coupled to the first input node of the latch, wherein the drain of the fourth FET is coupled to the gate of the third FET, and wherein the gate of the fourth FET is coupled to the drain of the third FET.