Patent ID: 7538419

Claim:
A stacked-type chip package structure, comprising: a substrate, having a dielectric layer and a plurality of connection pads; a first chip disposed on the substrate, the first chip having a plurality of first bonding pads and a plurality of second bonding pads disposed on an active surface thereof, wherein the first chip further comprises a redistributed layer (RDL), and at least one of the first bonding pads is electrically connected to at least one of the second bonding pads through the RDL; a plurality of bonding wires, wherein the first bonding pads are electrically connected to the connection pads of the substrate through the bonding wires; a second chip disposed above the first chip, the second chip having a plurality of third bonding pads disposed on an active surface thereof; and a plurality of B-stage conductive bumps, wherein the third bonding pads of the second chip are electrically connected to the second bonding pads of the first chip through the B-stage conductive bumps respectively and at least one of the B-stage conductive bumps at least fully cover areas of a corresponding one of the second bonding pads and a corresponding one of the third bonding pads, wherein the B-stage conductive bumps also covers at least a portion of redistributed layer.