Patent ID: 7809927

Claim:
A processor, comprising: A. a plurality of reconfigurable calculation units coupled both in parallel wherein input data samples are fed in parallel thereto and in a pipelined configuration wherein results from one reconfigurable calculation unit are input to a reconfigurable calculation unit logically adjacent thereto; B. each reconfigurable calculation unit including: i. a feedback path to perform sequential functional processing of input data samples in which an input data sample is processed through various functions in sequential fashion and the results output of one function are used as input to the next function; and ii. a forward path to transfer processing results between logically adjacent reconfigurable calculation units; C. a hardware register file to store historical result values generated by a last reconfigurable calculation unit in the pipeline; and D. an instruction decoder to generate the same control and configuration signals for all reconfigurable calculation units but with a pipelined delay therebetween so that an upstream unit receives a control and configuration signal before a downstream unit.