Patent ID: 8255669

Claim:
A method of operating a processor, the method comprising: storing, by a memory array, a plurality of instruction threads; fetching, by a fetcher, a particular instruction thread from the memory array, the particular instruction thread including a particular branch instruction, the fetcher communicating with a thread priority controller; predicting, by a branch predictor, an outcome of the particular branch instruction of the particular instruction thread, thus providing a branch prediction; issuing, by an issue unit, the particular branch instruction of the particular instruction thread to a branch execution unit for execution and, while performing such issuing, sending by the issue unit branch issue information to the thread priority controller, the branch issue information including branch confidence information, branch issuance timing information and a thread ID of the particular branch instruction; changing, by the thread priority controller, a priority of the particular instruction thread in response to the branch issue information, wherein the thread priority controller speculatively increases the priority of the particular instruction thread that includes the particular branch instruction if the branch confidence information indicates low confidence in a predicted outcome of the particular branch instruction in the particular instruction thread, the particular branch instruction thus being a low confidence branch for which a branch redirect is likely; executing, by a branch unit, the particular branch instruction; sending, by the branch unit, branch prediction correct/incorrect status information to the fetcher; and determining by the fetcher, in the event that the branch prediction correct/incorrect status information indicates a branch mispredict, a next fetch address using the branch issue information that the thread priority controller received earlier when the issue unit sent the branch issue information to the thread priority controller.