Patent ID: 8487669

Claim:
A Radio Frequency (RE) quadrature clock divider comprising: a pair of latches, each comprising a cross-coupled PMOS transistor pair operative to force complimentary voltage values at the outputs of each latch, the latches connected between a positive voltage supply node and four central nodes; four NAND gates connected in a serial ring formation, each NAND gate comprising a pair of stacked NMOS transistors, the NAND gates connected between the central nodes and a ground node, and wherein each central node also connects to a gate of one transistor in a successive NAND gate in the ring; positive and negative differential RF clock inputs, the positive clock input connected to a gate of one transistor in each of half of the NAND gates and the negative clock input connected to a gate of one transistor in each of the other half of the NAND gates, such that the positive and negative inputs alternate at each successive NAND gate in the ring; wherein the latches are operative to maintain complimentary states of the central nodes when the NAND gates are inactive; and wherein during each phase of the input clock, one NAND gate is active and operative to invert the outputs of an associated latch.