Patent ID: 7173845

Claim:
A circuit, comprising: a memory array comprising a plurality of memory cells, the plurality of memory cells arranged in a plurality of groups, each memory cell having first and second p-channel transistors and first and second n-channel transistors in a cross-coupled latch configuration; and power control circuitry selectively coupled, one group at time, to source terminals of the n-channel transistors in the selected group, for providing to those source terminals a low voltage reference level during a normal mode of operation and transitioning those source terminals to a high voltage reference level and back to the low voltage reference level during a data corruption mode of operation, the power control circuitry comprising: a counter; a plurality of decoders, one decoder per group, each decoder coupled to receive a count value output from the counter and decode that count value to selectively transition that decoder's connected n-channel source terminal from the low voltage reference level to the high voltage reference level and back to the low voltage reference level.