Patent ID: 8521800

Claim:
An arithmetic logic stage in a graphics pipeline, the stage comprising: a plurality of arithmetic logic units (ALUs) comprising a first ALU, a second ALU, a third ALU and a fourth ALU, each of the ALUs comprising a first digital circuit operable for performing a first type of operation and a second digital circuit operable for performing a second type of operation; and circuitry interconnecting the ALUs, the circuitry operable for routing data that is output from the first digital circuit of the first ALU to both the second digital circuit of the second ALU and the second digital circuit of the third ALU, wherein the circuitry comprises: a first multiplexer coupled between the first digital circuit of the first ALU and the second digital circuit of the second ALU, wherein the first multiplexer is operable for selecting the data as an operand for the second digital circuit of the second ALU; and a second multiplexer coupled between the first digital circuit of the first ALU and the second digital circuit of the third ALU, wherein the second multiplexer is operable for forwarding the data to the second digital circuit of the third ALU.