Patent ID: 8838879

Claim:
A memory system comprising: a plurality of nonvolatile memory banks commonly coupled to a data input/output line, and capable of performing an interleaving operation, a data cache and a memory cell array disposed inside each of the plurality of nonvolatile memory banks, data being read out from the memory cell array by a page unit and then stored in the data cache; a first controller configured to generate a plurality of page read commands by dividing a read request by the page unit, and to allocate the plurality of page read commands, in accordance with bank addresses specified by the page read commands, to a plurality of read queues provided respectively for the plurality of nonvolatile memory banks; a second controller including a plurality of bank controllers respectively coupled with the plurality of read queues, each of the plurality of bank controllers configured to issue the page read commands to the corresponding nonvolatile memory bank in parallel, regardless of an order of logical addresses specified by the page read request; and a third controller configured to control the second controller so that data stored in the data caches of the plurality of nonvolatile memory banks are sequentially transferred to outside the memory system through the data input/output line in accordance with the order of logical addresses specified by the read request, wherein the data cache is used for separating the data transfer stage from the data reading stage, thereby a data reading operation is performed in parallel among the plurality of nonvolatile memory banks and a data transferring operation from the plurality of nonvolatile memory banks to outside the memory system is performed, without using another memory component, in accordance with the order of logical addresses specified by the read request.