Patent ID: 8368367

Claim:
A voltage regulator, comprising: a voltage divider circuit, comprising: a first PMOS transistor, a source thereof is coupled to an input voltage from a power supply, and a gate thereof is coupled to a drain thereof; a second PMOS transistor, a source thereof is coupled to the drain of the first PMOS transistor, and a gate thereof is coupled to a drain thereof; a third PMOS transistor, a source thereof is coupled to the drain of the second PMOS transistor, a gate thereof is coupled to a drain thereof, and the drain thereof is coupled to a referencing voltage; a first NMOS transistor, a source thereof is coupled to a drain thereof, a gate thereof is coupled to the source of the first PMOS transistor, and the drain thereof provides a dividing voltage; a pull down circuit, comprising a plurality of switches controlled by a pull down control signal, and providing a ground connected to the sources of the first, second, and third PMOS transistors when the power supply is disabled to provide the input voltage; and a switching capacitor circuit, controlled by a control pulse, comprising a capacitor, and providing the capacitor connected to the dividing voltage for a short period while the power supply starts up to provide the input voltage; and the power supply, comprising: a comparator, for comparing the dividing voltage and a reference voltage, and outputting a comparison result correspondingly; and a power voltage switch, controlled by the comparison result to provide the input voltage from a power voltage.