Patent ID: 7728638

Claim:
An electronic system comprising: a delay locked loop configured to be enabled and update lock state data and to be disabled and store the lock state data; and a control circuit configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period, wherein the control circuit is configured to control the length of the update interval and the length of the enable period to obtain partial lock state data corresponding to a partial lock state of the delay locked loop to adjust power consumption during the standby mode and to adjust lock state acquisition time for the delay locked loop in exiting the standby mode, wherein the delay locked loop comprises: a fine delay line that is switched into the delay locked loop in normal mode and switched out of the delay locked loop in the standby mode; and a coarse delay line that is switched into the delay locked loop in the standby mode to obtain the partial lock state data in the standby mode.