Patent ID: 8687304

Claim:
A write clock synchronization system comprising: a first module configured to generate a write clock signal; a second module configured to, based on a sensor signal received, detect a pattern of bit islands on bit-patterned media, wherein the second module is configured to determine a phase error of the write clock signal based on (i) the pattern of the bit islands, and (ii) a predetermined phase shift value; a third module configured to at least one of adjust or select a phase of the write clock signal based on the phase error; a fourth module configured to generate the predetermined phase shift value based on a test write; and a fifth module configured to write data to the bit islands, wherein during the test write the fourth module is configured to select the predetermined phase shift value from a plurality of phase shift values, the third module is configured to generate the write clock signal based on the predetermined phase shift value, and the fifth module is configured to write the data to the bit islands based on the write clock signal.