Patent ID: 8533646

Claim:
A designing apparatus, comprising: a register position determining module configured to determine a register position on a layout of a semiconductor integrated circuit from a hardware description; a net list generator configured to generate a net list according to the register position; a layout data generator configured to generate layout data based on the net list, the layout data indicating the layout of the semiconductor integrated circuit; and a compression logic generator configured to add a compression scan description to the hardware description, the compression scan description indicating a compression scan circuit, wherein the net list generator comprises: a scan synthesizer configured to perform scan synthesis with respect to the hardware description comprising the compression scan description to generate a first net list corresponding to a plurality of scan chains; and a compression logic changer configured to change a configuration of the compression scan circuit based on the register position to convert the first net list into a second net list, wherein the register position determining module determines the register position on the layout of the semiconductor integrated circuit corresponding to the first net list, and wherein the layout data generator generates the layout data indicating the layout of the semiconductor integrated circuit corresponding to the second net list.