Patent ID: 7561651

Claim:
A method for synchronizing an output signal of a device so as to be phase aligned with an input clock signal comprises the steps of: a) providing an oscillator signal having a period Πn of 1/(f 1 *2 n ), wherein n is an integer, wherein f 1 is the clock frequency, and wherein the oscillator signal is phase aligned with the input clock signal; b) generating a multiplicity of delayed signals sdk, where k is an integer, each delayed signal having the same period Πc as the input clock signal, wherein delayed signal sd 1 is delayed by one-half the oscillator period Πn from the input clock signal, and wherein delayed signal sd(k+1) is delayed by one-half the oscillator period Πn from delayed signal sdk for each value of k; c) measuring the phase difference ΔΦk between an unadjusted output signal and the delayed signal sdk for each value of k; d) determining which value of k, equal to km, resulted in the smallest positive value of ΔΦk measured; e) adding a coarse delay time Δτ 1 to the clock signal equivalent to the smallest positive value of ΔΦk measured, creating a delayed clock signal thereby; f) generating a new output signal, delayed by time Δτ 1 from the output signal, by use of the delayed clock signal.