Patent ID: 7883962

Claim:
A method of forming a DRAM array comprising: providing a silicon substrate; forming a first silicon layer of a first conductivity type on the substrate; forming a second silicon layer of a second conductivity type on the first silicon layer; forming a third silicon layer of the first conductivity type on the second silicon layer; defining a first set of trenches in the substrate an extending through the first, second and third silicon layers; defining a second set of trenches in the substrate which extend through the first, second and third silicon layers in a direction orthogonal to the first set of trenches to form vertical stacks of the first, second and third silicon layers; isotropic etching to deepen the second set of trenches wherein the isotropic etching undercuts the vertical stacks; creating an isolation layer under and between the vertical stacks; forming word lines in contact with a first side of the vertical stacks; and forming bit lines on top of the third silicon layer of the vertical stacks.