Patent ID: 7498250

Claim:
A method of manufacturing an integrated circuit, comprising: providing a dielectric layer having a bottom surface disposed over a semiconductor substrate; simultaneously forming a first trench and a multiplicity of second trenches in said dielectric layer, said first trench including dielectric pedestals within said first trench, said dielectric pedestals comprised of said dielectric layer; and simultaneously completely filling said first trench and said multiplicity of second trenches with a layer of metal to form respectively a wire having dielectric pedestals therein and a set of metal fill shapes, said metal fill shapes extending from a top surface of said dielectric layer toward said bottom surface of said dielectric layer, said metal fill shapes arranged in a first pattern, said dielectric pedestals extending from a top surface of said wire to a bottom surface of said wire, sides of said dielectric pedestals completely surrounded by said wire, said dielectric pedestals arranged in a second pattern, wherein said second pattern is an offset-grid, said offset grid having a pitch defined by a width of said wire.