Patent ID: 8543962

Claim:
A method comprising: generating a netlist representation of a logic circuit; tracing, by a computer, a signal path for a given input forward from an origin point in the netlist to a data input of each clocked state element in each signal path of a fanout of the given input; and for each of the clocked state elements in the fanout which have a clock input that is selectively disabled by a respective clock gate circuit, determining whether the signal path for the given input feeds an input of a cone of logic of any of the respective clock gate circuits; wherein in response to determining that the signal path for the given input feeds both the input of a cone of logic of a particular respective clock gate circuit and the data input of the clocked state element to which the particular respective clock gate circuit is coupled, replacing within the netlist a signal name corresponding to the given input with a reference voltage at an input pin of an input of a cone of logic of the data input of the clocked state element.