Patent ID: 7402889

Claim:
A semiconductor device comprising: a first metal pattern formed on a semiconductor substrate; a first interlayer insulating layer formed on the first metal pattern; a second metal pattern formed on the first interlayer insulating layer; a second interlayer insulating layer formed on the second metal pattern; a dielectric layer and conductive layer formed on sidewalls of a first trench formed in the second interlayer insulating layer, the first trench selectively exposing a significant portion of the second metal pattern, and the dielectric layer also being formed on the significant portion of the second metal pattern and on sidewall portions of a second trench formed in the first interlayer insulating layer, the second trench exposing a significant portion of the first metal pattern, and the dielectric layer also being formed on the significant portion of the first metal pattern; wherein the second trench is formed self-aligned using the second metal pattern as a mask;.and a third metal pattern formed on the dielectric layer and conductive layer.