Patent ID: 7119722

Claim:
A variable length decoding device comprising: a memory for laying out data which is identical to data memorized on a lower-bit side at an optional address on an upper-bit side at an address subsequent to the optional address and memorizing the layed-out data; a buffer register having a bit width at least equal to a bit width of the memory for storing data loaded from the memory; and an address register for storing a value of an address at which the memory is accessed (address value) on an upper-bit side and storing number of data which was referred to in the buffer register on a lower-bit side, characterized in that a data shift operation using the number of the data which was referred to and number of data which is currently referred to is executed to the buffer register so that data to be presently referred to is extracted from the buffer register for the variable length decoding, the number of the data which was referred to on the lower-bit side of the address register is renewed by adding thereto the number of the data which has been currently referred to in response to the extraction of the data from the buffer register, and the address value to be stored on the upper-bit side of the address register is maintained when the renewed number of the data which was referred to on the lower-bit side of the address register is not carried up, and the carry-up is used to renew the address value to be a next address value when the renewed number of the data is carried up.