Patent ID: 7355230

Claim:
An access transistor array, comprising: a plurality of substrate pillars extending outwardly from a bulk section of a semiconductor substrate and arranged in rows and columns, each substrate pillar forming an active area of a vertical channel access transistor; insulating trenches separating rows of pillars; columns of insulating plugs, each insulating plug separating adjacent pillars within each row of pillars, each column of insulating plugs having opposing first and second sides, the first side being adjacent to a first column of pillars and the second side being adjacent to a second column of pillars respectively; word lines for controlling access transistors, the word lines being arranged within the insulating trenches, each word line being disposed adjacent to the pillars of the respective row of pillars and being insulated from the respective pillars by a gate dielectric; and bit lines, each bit line extending between two neighboring columns of substrate pillars, being disposed below the insulating plugs, extending along the columns of insulating plugs, wherein each bit line is coupled to the active areas in the pillars of the first column of pillars via a respective single sided bit line contact and is insulated from the active areas of the pillars of the second column of pillars.