Patent ID: 8441048

Claim:
A substantially planar semiconductor device comprising: a substrate; and a device layer residing over the substrate along a first plane and having a first horizontally depleted metal semiconductor field effect transistor comprising: a drain region; a source region spaced apart from the drain region along the first plane; and a gate section residing between the drain region and the source region and comprising a first gate contact and a second gate contact that is spaced apart from the first gate contact along the first plane to provide a channel region between the first gate contact and the second gate contact and extending between the drain region and the source region, wherein when operated, voltages applied to the first gate contact and the second gate contact control vertical depletion regions in either side of the channel region to horizontally deplete the channel region and thus control current flow between the drain region and the source region; a drain contact associated with the drain region and a source contact associated with the source region, the drain contact residing along the first plane in the device layer and being spaced apart from the gate section by the drain region and the source contact residing along the first plane in the device layer and being spaced apart from the gate section by the source region; and wherein the first gate contact and the second gate contact are substantially surrounded by the source region and the drain region and the channel region.