Patent ID: 7467260

Claim:
A computer system comprising: a processor; an associative cache having N sets, each set having M classes, coupled to the processor, the cache further comprising: a cache replace mechanism having a deterministic replace scheme; an address mechanism; and a cache array; a main memory coupled to the processor; a cache flush routine residing, at least in part, in the main memory, the cache flush routine configured to activate a cache flush mode, the cache flush mode, when activated, configured to execute, once for each class in each set, a cache flush instruction that flushes a cache line having a particular address that maps to an instant set, the cache flush instruction ensuring that the cache line having the particular address does not exist in the instant set, the cache flush instruction being immediately followed by a fetch from the particular address, the fetch causing a replacement of a victim cache line in an instant class selected by the deterministic replace scheme.