Patent ID: 8395453

Claim:
An error compensation method for an ADPLL (All-digital phase-locked loop), comprising: determining a quantization error to generate a determined quantization error; determining a fractional error corresponding to a gain of a time-to-digital converter (TDC) within the ADPLL to generate a determined fractional error; determining a compensation error according to: e CTDC ⁡ [ k ] = ∑ n = 0 k - 1 ⁢ e Δ ⁢ ⁢ Σ ⁡ [ n ] · 2 · Δ ⁢ ⁢ N ( M + F ) ; and using the determined compensation error to compensate an error within the ADPLL; wherein e ΔΣ [n] indicates the quantization error; ΔN indicates the determined fractional error; M indicates a dividing ratio of a frequency divider; and F indicates a fractional number related to the quantization error.