Patent ID: 7492632

Claim:
An integrated circuit device comprising: a memory cell array including: a plurality of word lines; a plurality of source lines; a plurality of bit lines; and a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes an electrically floating body transistor, wherein the electrically floating body transistor includes: a first region coupled to an associated source line; a second region coupled to an associated bit line; a body region disposed between the first region and the second region, wherein the body region is electrically floating; a gate disposed over the body region and coupled to an associated word line; and wherein each memory cell includes a plurality of data states, including: (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor; and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor; first circuitry, coupled to each memory cell of a first row of memory cells, to perform a write operation with respect to memory cells of the first row of memory cells by concurrently applying: (i) write control signals to a first group of memory cells of the first row of memory cells to write one of the plurality of data states in each memory cell of the first group, and (ii) write de-select control signals to a second group of memory cells of the first row of memory cells to inhibit the write operation with respect thereto, and thereby inhibit writing any of the plurality of data states in the second group of memory cells during the write operation.