Patent ID: 7135744

Claim:
A semiconductor device comprising: a semiconductor substrate having a cell array region and a peripheral circuit region; a plurality of word line patterns placed on the cell array region, the word line patterns including a word line and a word line capping layer; at least one gate pattern placed on the peripheral circuit region; an interlayer insulating layer covering an upper surface of the semiconductor substrate having the word line patterns and the at least one gate pattern; a self-aligned contact hole formed in the interlayer insulating layer between the word line patterns; a self-aligned contact spacer covering a side wall of the self-aligned contact hole; gate spacers interposed between side walls of the at least one gate pattern and the interlayer insulating layer, a width of the gate spacers being substantially different from a width of the self-aligned contact spacer; word line spacers interposed between side walls of the word line patterns placed opposite to the self-aligned contact hole and the interlayer insulating layer, the word line spacers being formed of the same material layer as the gate spacer, a maximum width of the word line spacers substantially the same as a maximum width of the gate spacers; and a spacer etch stop layer disposed in contact with the word line spacers and the word line patterns in the cell array region, disposed in contact with the gate spacers and the at least one gate pattern in the peripheral circuit region, and disposed in contact with the self-aligned contact spacer and the word line patterns in the cell array region.