Patent ID: 7473957

Claim:
A floating gate non-volatile memory comprising: a substrate; a channel forming semiconductor region of a first conductivity type disposed in a substrate surface region of the substrate; a source region and a drain region each disposed in the substrate surface region, the source and drain regions being spaced from each other with the channel forming semiconductor region disposed therebetween; a gate insulating film disposed on the channel forming semiconductor region; a single crystal control region electrically separated from the channel forming semiconductor region and disposed in the substrate surface region; a control gate insulating film disposed on the single crystal control region; a floating gate disposed on the gate insulating film and extending onto the control gate insulating film so as to be capacitively coupled with the single crystal control region; a chemical-vapor-deposited shield insulating film formed in a gas atmosphere charge-balanced on the floating gate; and a shield conductive film disposed on the chemical- vapor-deposited shield insulating film and capacitively coupled with the floating gate.