Patent ID: 6925510

Claim:
A peripheral or memory device having a bus, and a bus switching circuit that comprises: a first bus decoder circuit coupled to the bus for decoding signals in a first format; a second bus decoder circuit coupled to the bus for decoding signals in a second format; a first bus snoop circuit coupled to the bus; a second bus snoop circuit coupled to the bus; a switch coupled to the first bus snoop circuit for receiving a first bus detect signal therefrom, and the switch coupled to the second bus snoop circuit for receiving a second bus detect signal therefrom; wherein the switch is coupled to the first bus decoder circuit for providing a first bus enable signal thereto, and the switch is coupled to the second bus decoder circuit for providing a second bus enable signal thereto, depending on the nature of the first and second detect signals; wherein the first bus decoder circuit is an ISA bus decoder circuit, and the second bus decoder circuit is an LPC bus decoder circuit; and wherein the first and second bus snoop circuits generate the first and second bus detect signals, respectively, based on a series of I/O writes.