Patent ID: 8102690

Claim:
A chip system that has reduced power consumption under specific operational modes, comprising: a DDR3 chip, comprising: a plurality of pads, disposed at a centre of the DDR3 chip; an array of banks surrounding the pads, each bank being divided into two half banks, each half bank having a logical address consisting of a bank logical address and a specific logical address where two half banks share a same bank logical address and have a different specific logical address; and an upper left spoke situated at an upper left side of the DDR3 chip and disposed between two banks, an upper right spoke situated at an upper right side of the chip and disposed between two banks, a downer left spoke situated at a down left side of the chip and disposed between two banks and a downer right spoke situated at a down right side of the chip and disposed between two banks, such that each spoke is shared by two physical banks; a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode so that two half banks corresponding to the same bank logical address are situated in a same bank or that two half banks corresponding to different bank logical addresses are situated in the same bank.