Patent ID: 7747974

Claim:
A computer-implemented method for optimizing body bias connections in a CMOS circuit substrate using a deep n-well grid structure, said method comprising: in a computer system: a) performing a circuit layout for said substrate; b) prioritizing a plurality of PFETs for placement in a plurality of body biased n-wells; c) selecting a set of dimensional parameters for said deep n-well grid structure from a set of available parameters; d) selecting an alignment between said deep n-well grid structure and said circuit layout for a set of available alignments; e) determining a score for said alignment; f) repeating d) through e) until said set of available alignments is exhausted; g) repeating c) through f) until said set of available parameters is exhausted; and h) performing a layout for said deep n-well grid structure using the dimensional parameters and alignment having a score which exceeds a predetermined threshold.