Patent ID: 6895061

Claim:
A synchronizer for receiving an incoming data signal of a first clock domain and for outputting a resolved data signal of a second clock domain, the synchronizer comprising: an input stage, the input stage receiving the incoming data signal of the first clock domain, the input stage comprising a clocked inverter, the input stage outputting an inverted data signal therefrom when the clocked inverter is clocked with a master clock signal M 1 ; a master latch coupled to the input stage, the master latch receiving the inverted data signal output from the input stage and storing the inverted data signal at a storage node of the master latch, the master latch having a resolve time associated therewith during which the master latch seeks to resolve the inverted data signal to a logic 0 or a logic 1; transfer logic coupled to the master latch, the transfer logic causing the signal stored in the master latch to be transferred out of the master latch when the transfer logic is clocked with a slave clock signal S 1 ; and a slave latch coupled to the transfer logic, the signal transferred out of the master latch being transferred into the slave latch, the slave latch comprising an output terminal for outputting the resolved data signal of the second clock domain; wherein the master latch comprises: a first feedback inverter having an input terminal and an output terminal, the input terminal of the first feedback inverter being coupled to an output node of the master latch; and a transmission gate being coupled on a first side of the transmission gate to the output terminal of the first feedback inverter, the transmission gate being coupled on a second side of the transmission gate to the storage node of the master latch, the transmission gate being controlled by a transmission gate clock signal CK, which is independent of the master clock signal M 1 and is substantially the inverse of the master clock signal M 1 .