Patent ID: 8853762

Claim:
A memory device, comprising: a substrate having a memory device region and a protection device region; a first dielectric layer formed on the substrate; a second dielectric layer formed on the first dielectric layer; an opening formed in the second dielectric layer of the memory device region; a cup type capacitor formed overlying the substrate of the memory device region, wherein the cup type capacitor comprises a bottom electrode, a capacitor dielectric layer and a top electrode having a first portion extending to the protection device region, and wherein the bottom electrode is formed on the second dielectric layer to directly line the bottoms and sidewalls of the opening; a diode formed in the substrate of the protection device region, wherein the diode is a PN junction diode and includes: a first semiconductor type well in the substrate; a second semiconductor type region above the first semiconductor type well; and a silicide region above the second semiconductor type region, wherein one of the first semiconductor type and the second semiconductor type is a p type, the other one of the first semiconductor type, and the second semiconductor type is an n type, and the substrate is of the second semiconductor type; a contact plug formed overlying the substrate of the protection device region and electrically connected to the diode; a via plug formed overlying the substrate of the protection device region and electrically connected to the first portion of the top electrode; and a conductive line formed on the contact plug and the via plug.