Patent ID: 7476588

Claim:
A method of forming a NAND cell unit, comprising: forming a stack of layers, the layers including a carbon-containing layer and an electrically conductive layer, with the carbon-containing layer being over the electrically conductive layer; forming a patterned mask over the stack of layers, the mask having openings extending therethrough defining regions corresponding to a select gate pattern and a plurality of string gate patterns, the string gate patterns being about the same width as one another; one of said string gate patterns being a first string gate pattern and being nearer said select gate pattern than others of the string gate patterns; etching through the openings in the mask to form the select gate pattern and string gate patterns in the carbon-containing layer, the etching causing the first string gate pattern in the carbon-containing layer to have a different width than at least some of the others of the string gate patterns; and transferring the select gate pattern and string gate patterns from the carbon-containing layer to the electrically conductive layer to incorporate the electrically conductive layer into a NAND cell unit comprising a select gate and string gates, the first string gate of the NAND cell unit having a different width than other string gates of the NAND cell unit.