Patent ID: 7951691

Claim:
A method for producing a thin semiconductor chip comprising an integrated circuit, the method comprising the steps of: providing a semiconductor wafer having a first and a second surface, the semiconductor wafer being composed of p-doped silicon in the region of the first surface, defining at least one wafer section in the region of the first surface, converting the p-doped silicon in the region of the defined wafer section into porous silicon having a plurality of pores by means of an anodic etching process, the porous silicon comprising an upper layer at the first surface and a lower layer below the upper layer, producing a wafer cavity below the at least one defined wafer section by thermally treating the porous silicon such that the pores of the upper layer are substantially closed by material from the lower layer, producing a circuit structure in the at least one defined wafer section, and releasing the defined wafer section from the semiconductor wafer, wherein the wafer section is freed in a first process sequence by etching trenches into the depth of the wafer such that it is held only via web connections arranged at the lateral periphery of the wafer section on the remaining semiconductor wafer, wherein the web connections are severed in a second process sequence, and wherein a plurality of local n-doped regions are produced in the p-doped silicon before the p-doped silicon is converted into porous silicon by means of the anodic etching process.