Patent ID: 7881138

Claim:
In a memory having a pre-amplifier for generating at least one output signal and at least one reference signal, the memory further comprising at least one comparator for comparing one of the at least one output signal to one of the at least one reference signal, the at least one comparator comprising: a bias stage comprising: a first transistor of a first conductivity type having a first current terminal coupled to a first supply, a control terminal coupled to the one of the at least one output signal, and a second current terminal; a second transistor of the first conductivity type having a first current terminal coupled to the first supply, a control terminal coupled to the one of the at least one reference signal, and a second current terminal directly connected to the second current terminal of the first transistor forming a biasing node; and a third transistor of a second conductivity type having a first current terminal directly connected to the biasing node, a control terminal coupled to the biasing node, and a second current terminal coupled to a second supply, wherein the first supply is different from the second supply; and a first output stage directly connected to the biasing node and a second output stage directly connected to the biasing node.