Patent ID: 7975082

Claim:
A method of deterministically transferring data across a first clock domain to a second clock domain comprising: receiving a resynchronize command in the first clock domain; initiating a corresponding one of a plurality of read delays in each one of a second plurality of devices in the second clock domain, wherein each one of the second plurality of devices are coupled a corresponding one of a first plurality of devices in the first clock domain by a corresponding one of a plurality of serial data lanes; counting down the plurality of read delays to zero; receiving a training pattern across the plurality of serial data lanes to each one of the second plurality of devices after the plurality of read delays count down to zero; recovering a clock data in each of the second plurality of devices including locking a PLL circuit in each one of the second plurality of devices to a corresponding PLL circuit in the corresponding one of the first plurality of devices; receiving a synch byte across the plurality of serial data lanes to each one of the second plurality of devices; selecting one of the plurality of serial lanes as a reference lane; wherein the plurality of serial lanes couple the first clock domain to the second clock domain; initiating a write pointer; writing n bytes of serial data to a buffer; and converting the n bytes of data from serial data to parallel data in a serial to parallel converter such that the serial n byte data in the buffer are aligned in time.