Patent ID: 8539407

Claim:
A method of analyzing a design of a circuit comprising the steps of: (A) generating a schematic view representative of a clock structure in with a processor, said schematic view being viewable by a user on a display device and includes (i) a source device of a clock signal in said clock structure, (ii) an end device receiving said clock signal and (iii) at least one intermediate device transferring said clock signal between said source device and said end device, wherein (i) at least one of said intermediate devices in said schematic view represents a plurality of respective devices clocked in parallel in said clock structure, (ii) said intermediate device and said respective devices are at a particular hierarchical level of said design and (iii) a timing of said clock signal in said schematic view matches said timing of said clock signal in said clock structure; (B) adding a plurality of timing constraints to said schematic view; and (C) verifying a static timing of said clock signal in said design based on said schematic view and said timing constraints.