Patent ID: 6842070

Claim:
A circuit to generate virtual multi-level output pulses for a Class-D Amplifier with only 2 physical levels, where the resulting time-voltage-area corresponds to a multiple of digital levels, comprising: means to convert the input signal into a PDM (Pulse Density Modulated) signal; means to generate the output of said PDM (Pulse Density Modulated) as a signal, representing the desired multiple of pulse areas values; means to determine the required length-ratio of positive and negative pulse portions within one sampling period, where said pulse length ratio represents said multiple pulse-area values; means to define a set of output pulse-area values, one for each step of said multiple pulse-area values; means to control the time of pulse phase changes within one sampling period; a pulse generator providing the virtual multi-level output pulses to a power driver, using said pulse length controlled signal; means for a Class-D power driver to drive voltage into an output load, controlled by said power driver pulses, typically a Complementary-Pair-Driver or an equivalent circuit; and means for an output load as the amplifier's output target.