Patent ID: 6930000

Claim:
A method of manufacturing a semiconductor device, which comprises a memory area having a non-volatile memory device and a logic circuit area including a peripheral circuit of the non-volatile memory device, the manufacturing method comprising the steps of: providing a semiconductor substrate, which has an element separating region formed on surface of a semiconductor layer to attain insulation between semiconductor elements, a first conductive layer formed above the semiconductor layer and patterned to give a word gate of the non-volatile memory device, a stopper layer formed above the first conductive layer, and control gates formed as side walls via an ONO membrane on both side faces of the first conductive layer in the memory area; patterning the first conductive layer in the logic circuit area to create a gate electrode of an insulated gate field effect transistor, which constructs the peripheral circuit, in the logic circuit area and to create a dummy gate electrode above the element separating region in the logic circuit area; forming an insulating layer over whole surface of the memory area and the logic circuit area on the semiconductor substrate; and polishing the insulating layer and the ONO membrane to make the stopper layer in the memory area exposed.