Patent ID: 7812632

Claim:
An apparatus for on-die termination of a semiconductor memory, comprising: a first ODT (On-Die Termination) voltage generating unit configured to output a first line voltage by calibrating an input voltage with a resistance ratio according to a first code having at least two bits; a first code calibrating unit that counts the first code according to the result of a comparison between the first line voltage and a reference voltage, stops the code count when the first code is one of two target values that are a maximum value and a minimum value, and stores the first code corresponding to the maximum value or the minimum value; a second ODT voltage generating unit that outputs a second line voltage by calibrating an input voltage with a resistance ratio according to the first code and a second code having at least two bits; and a second code calibrating unit that counts the second code according to the result of a comparison between the second line voltage and the reference voltage, stops the code count when the second code is one of two target values that are a maximum value and a minimum value, and stores the second code corresponding to the maximum value or the minimum value, wherein the first code calibrating unit includes a first XNOR gate that is configured to stop the code counting of the first code in response to the first code and the result of the comparison between the first line voltage and the reference voltage, and the second code calibrating unit includes a second XNOR gate that is configured to stop the code counting of the second code in response to the second code and the result of the comparison between the second line voltage and the reference voltage.