Patent ID: 7142012

Claim:
An integrated circuit, comprising: a first region comprising: a first plurality of cells; and a first conductor having a first span along a first dimension and a second conductor having a second span along a second dimension, wherein each of the first conductor and the second conductor is neither an input nor an output of any cell; a second region comprising: first, second, third and fourth replicated first regions, wherein the first replicated first region and the second replicated first region are located adjacent in a first row along the first dimension, wherein the third replicated first region and the fourth replicated first region are located in a second row along the first dimension; and a third conductor having a third span along the first dimension and a fourth conductor having a fourth span along the second dimension, wherein the third span of the third conductor is greater than the first span of the first conductor and the fourth span of the fourth conductor is greater than the second span of the second conductor and wherein each of the third conductor and the fourth conductor is neither an input nor an output of any cell; and a third region comprising: first, second, third and fourth replicated second regions, wherein the first replicated second region and the second replicated second region are located adjacent in a first row along the first dimension, wherein the third replicated second region and the fourth replicated second region are located in a second row along the first dimension; a first switch; and a fifth conductor having a fifth span along the first dimension and a sixth conductor having a sixth span along the second dimension, wherein the fifth conductor is configured to selectively couple to the sixth conductor through the first switch without requiring selectable connection through another conductor, wherein the fifth span of the fifth conductor is greater than the third span of the third conductor and the sixth span of the sixth conductor is greater than the fourth span of the fourth conductor and wherein each of the fifth conductor and the sixth conductor is neither an input nor an output of any cell.