Patent ID: 8394683

Claim:
A method of forming a NAND unit cell, comprising: forming vertical columns of a semiconductor material over a substrate, the columns comprising alternating n-type doped layers of the semiconductor material and p-type doped layers of the semiconductor material; each of the columns comprising at least four layers of the n-type doped semiconductor material and at least three layers of the p-type doped semiconductor material; each of the columns extending vertically away from the substrate with a first one of the doped layers being nearer to the substrate than the other doped layers and the other doped layers being above both the substrate and the first one of the doped layers; after forming the columns that comprise at least four layers of the n-type doped semiconductor material in alternating relationship with at least three layers of the p-type doped semiconductor material, lining the columns with, in sequential order, a layer of tunnel dielectric, a layer of charge-storage material, and a layer of charge-blocking material, the layer of tunnel dielectric forming an upward-opening container; and forming alternating layers of electrically insulative material and electrically conductive material between the lined columns and within the opening within the container; the layers of electrically conductive material forming a plurality of horizontally-spaced control gate structures within the opening within the container; at least some of the control gate structures being incorporated into string devices of the NAND unit cell, wherein a first control gate structure of the plurality of control gate structures within the container is spaced from a second control gate structure of the plurality of control gate structures within the container that is immediately adjacent the first control gate structure only by the electrically insulative material and wherein the forming of the alternating layers of electrically insulative material and electrically conductive material comprises forming the first control gate structure above the layer of charge-blocking material and forming the second control gate structure above the first control gate structure.