Patent ID: 8421435

Claim:
A power supply voltage controlling circuit for supplying a controlled output voltage to a subthreshold digital CMOS circuit as a controlled power supply voltage, the subthreshold digital CMOS circuit comprising a plurality of CMOS circuits each having a pMOSFET and an nMOSFET and operating in a subthreshold region with a predetermined delay time, wherein, in the subthreshold digital CMOS circuit, an absolute value of a difference between a threshold voltage of a typical value of the pMOSFET and a threshold voltage of a typical value of the nMOSFET is set to a value equal to or larger than a predetermined value so that one of the following conditions is satisfied: (A) a proportion w of the delay time of the CMOS circuit determined by a rise time of the pMOSFET becomes substantially one, and a proportion (1−w) of the delay time of the CMOS circuit determined by a fall time of the nMOSFET becomes substantially zero; or (B) the proportion w of the delay time of the CMOS circuit determined by the rise time of the pMOSFET becomes substantially zero, and the proportion (1−w) of the delay time of the CMOS circuit determined by the fall time of the nMOSFET becomes substantially one, where w is a weight coefficient, and wherein the power supply voltage controlling circuit comprises: a first minute current generator circuit for generating a predetermined minute current based on a power supply voltage of a power supply unit; and a controlled output voltage generator circuit for generating a controlled output voltage for correcting a variation in the delay time based on a generated minute current, and for supplying the controlled output voltage to the subthreshold digital CMOS circuit as a controlled power supply voltage, the controlled output voltage including a change in the threshold voltage of one of the pMOSFET and the nMOSFET.