Patent ID: 8143109

Claim:
A method for fabricating a damascene interconnect structure, the method comprising: providing a substrate; depositing a multilayer dielectric film on the substrate, wherein the multilayer dielectric film comprises a first, a second, and a third sub-dielectric layers, all three sub-dielectric layers are silicon nitride layers or silicon oxide layers, and a deposition rate of each of the first and the third sub-dielectric layers is greater than that of the second sub-dielectric layer; forming a patterned photoresist on the multilayer dielectric film; etching the multilayer dielectric film to form a plurality of trenches, a portion of each of the trenches having an enlarged width at each of sidewalls thereof; and filling the trenches with conductive metal to form conductive lines such that air is trapped in extremities of the enlarged width portions of the trenches between the second sub-dielectric layer and the conductive lines.