Patent ID: 7418644

Claim:
An error correction system for coding and decoding at least one information block, comprising: first and second encoders each configured to encode the at least one information block, wherein the first encoder generates first parity symbols during encoding of the at least one information block, and wherein the second encoder generates second parity symbols during encoding of the at least one information block, with a quantity of the second parity symbols being greater than a quantity of the first parity symbols; and first and second decoders configured to recover the at least one information block, wherein the first decoder and the second decoder are configured to operate sequentially in time with the first decoder acting first and the second decoder acting second; wherein the first decoder is configured to recover the at least one information block using the first parity symbols, and wherein the second decoder is configured to recover the at least one information block via the second parity symbols with the second decoder configured to remain inactive during operation of the first decoder and further remain inactive after operation of the first decoder unless the first decoder is unsuccessful in attempting to recover the at least one information block and until the first decoder provides an indication to the second decoder to recover the at least one information block.