Patent ID: 6992525

Claim:
An arrangement in a pulse amplifier implemented in standard CMOS, comprising a control circuit for controlling a driver stage for driving a class D output stage that comprises a first PMOS transistor and a first NMOS transistor with interconnected drain contacts constituting an output terminal of the pulse amplifier, the first PMOS transistor being connected with its source and bulk contacts to a first supply voltage terminal for receiving a first supply voltage, and the first NMOS transistor being connected with its source contact to a second supply voltage terminal for receiving a second supply voltage that is lower than the first supply voltage, wherein the driver stage comprises a first driver that is connected with its input terminal to a first output terminal of the control circuit and with its output terminal to a gate contact of the first NMOS transistor, and a second driver that is connected with its input terminal to a second output terminal of the control circuit and with its output terminal to a gate contact of a second NMOS transistor, the second NMOS transistor is connected with its source contact to said second supply voltage terminal and with its drain contact to a drain contact of a second PMOS transistor, the second PMOS transistor is connected with its source and bulk contacts to an interconnection point between a gate contact of the first PMOS transistor and a drain contact of a third PMOS transistor and to a drain contact of a fourth PMOS transistor and with its gate contact to a voltage node, the third PMOS transistor is connected with its bulk contact to said first supply voltage terminal, with its source contact to an interconnection point between a gate contact of the fourth PMOS transistor and a drain contact of a fifth PMOS transistor and with its gate contact to a first control voltage node, the fourth and fifth PMOS transistors are connected with their source and bulk contacts to said first supply voltage terminal, and wherein the fifth PMOS transistor is connected with its gate contact to a second control voltage node.