Patent ID: 8377790

Claim:
A method for fabricating an eFuse and a resistor, comprising: a) providing a substrate having insulating layers thereon; b) forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; c) thermally growing layers of oxide along the sides of the trenches, the layers of oxide having an approximately uniform equal thickness in a range of a approximately 20 nm to approximately 50 nm, the oxide being SiO 2 ; d) filling the first trench and the second trench with a polysilicon material, e) planarizing the polysilicon material; f) creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing, and then g) creating an eFuse in the first region and a resistor in the second region.