Patent ID: 8035225

Claim:
A semiconductor chip assembly comprising: a plurality of upper side pads provided on a substrate upper surface; a plurality of lower side pads provided on a substrate lower surface respectively corresponding to the upper side pads across the substrate; a first semiconductor chip joined to the upper side pads and having first bumps which bond to the upper side pads; and a second semiconductor chip joined to the lower side pads and having second bumps which bond to the lower side pads, wherein at least one of the first and second semiconductor chips is provided with a non-conducting pad that is not connected to a wiring circuit, a spacer is bonded between the non-conducting pad and the substrate, the spacer being formed of a combination of a dummy bump and a dummy pad, each of the upper side pads opposes one of the lower side pads or a dummy pad provided on the substrate lower surface, and each of the lower side pads opposes one of the upper side pads or a dummy pad provided on the substrate upper surface.