Patent ID: 8345481

Claim:
A reconfigurable integrated logic device comprising: an array of NAND-like NOR flash nonvolatile memory cells, each of the NAND-like NOR flash nonvolatile memory cell comprising: a plurality of charge retaining transistors arranged in rows and columns wherein said charge retaining transistors on each column form at least one pair of charge retaining transistors that is arranged in a series string such that one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the plurality of charge retaining transistors when the plurality of charge retaining transistors is not selected for determining a logic state of the reconfigurable integrated logic device; wherein a drain of a topmost charge retaining transistor of each NAND-like NOR flash nonvolatile memory cells is connected to a local bit line associated with and parallel to the column on which each NOR flash memory circuit resides; wherein a source of a bottommost charge retaining transistor of each of the NAND-like NOR flash nonvolatile memory cells is connected to a local source line associated with the associated NOR flash memory circuit and parallel with the associated bit line; and wherein each control gate of the charge retaining transistors on each row is commonly connected to a word line.