Patent ID: 7531401

Claim:
A method of applying a stress proximity technique process, the method comprising the steps of: forming a semiconductor device, said semiconductor device comprising a semiconductor substrate having a plurality of NFET and PFET devices disposed thereon, at least one of the NFET devices and at least one of the PFET devices having a first set of sidewall spacers and a second set of sidewall spacers, respectively, and an oxide liner disposed over the at least one of the NFET devices and over the at least one of the PFET devices; depositing a tensile stress layer over the at least one of the NFET devices and over the at least one of the PFET devices; removing at least a portion of the tensile stress layer over the at least one of the PFET devices; selectively removing at least a portion of the tensile stress layer over the at least one of the NFET devices, thereby forming a third set of sidewall spacers on the at least one of the NFET devices; and selectively removing the second set of sidewall spacers from the at least one of the PFET devices and the third set of sidewall spacers from the at least one of the NFET devices with the second set of sidewall spacers of the at least one of the NFET devices remaining substantially intact.