Patent ID: 7864912

Claim:
A clock recovery adjustment circuit, comprising: a clock phase adjustment circuit configured to receive clock phase information and provide a clock phase adjustment signal, said clock phase adjustment circuit comprising a first multiplier configured to receive said clock phase information and a clock phase adjustment coefficient; a clock frequency adjustment circuit comprising a second multiplier and a first integrator, said second multiplier configured to receive a frequency adjustment coefficient, said clock frequency adjustment circuit configured to receive clock frequency information and provide a clock frequency adjustment signal, wherein said clock frequency information comprises, relative to a bit length of a data stream, a frequency undershoot determination and a frequency overshoot determination; logic configured to sample said data stream at predetermined intervals, provide said clock frequency information and said clock phase information from sampled data and predetermined phases of one or more reference clock signals, compare data bit values at first and second phases of said reference clock signal, and at third and fourth phases of said reference clock signal; and provide said frequency overshoot determination when (i) the data bit values at said first and second sampled phases of said reference clock signal are not equal, (ii) the data bit values at said third and fourth sampled phases of said reference clock signal are not equal, and (iii) the data bit values of said second and third sampled phases are equal; and an adder circuit configured to receive said clock phase adjustment signal and said clock frequency adjustment signal, and provide a clock recovery adjustment signal.