Patent ID: 7528636

Claim:
A low differential output voltage circuit, comprising: a voltage generator, comprising: a first NMOS transistor, having a drain and a gate connected to the drain, wherein the drain of the first NMOS transistor receives a reference current, and a source of the first NMOS transistor is coupled to a common potential; a second NMOS transistor, having a source coupled to the common potential, and a gate coupled to the gate of the first NMOS transistor; a first PMOS transistor, having a source coupled to a source voltage, and a drain coupled to a drain of the second NMOS transistor; and a first amplifier circuit, having a positive input end coupled to the drain of the second NMOS transistor and the drain of the first PMOS transistor for clamping the voltages of the two drains at the reference voltage, a negative input end coupled to a reference voltage, and an output end coupled to a gate of the first PMOS transistor, wherein the reference voltage serves as the clamping voltage; a plurality of differential output units, each comprising: a first controlled current source, coupled to the output end of the first amplifier circuit, and providing a current of a value clamped within a first predetermined range according to the voltage of the above output end; a first switch, having a first end coupled to the first controlled current source, a second end, and a control end receiving a first sequence signal to determine whether or not to turn on; a second switch, having a first end coupled to the first controlled current source, a second end, and a control end receiving a second sequence signal to determine whether or not to turn on; a third switch, having a first end coupled to the second end of the first switch and outputting a first output signal, a second end, and a control end receiving a third sequence signal to determine whether or not to turn on; a fourth switch, having a first end coupled to the second end of the second switch and outputting a second output signal, a second end, and a control end receiving a fourth sequence signal to determine whether or not to turn on; a second controlled current source, coupled to the gate of the second NMOS transistor, the second end of the third switch, and the second end of the fourth switch, and providing a current of a value clamped within a second predetermined range according to the gate voltage of the second NMOS transistor; and a common mode voltage circuit, for clamping the common mode voltage of the first output signal and the second output signal within a third predetermined range according to the clamping voltage.