Patent ID: 7054225

Claim:
A semiconductor memory device comprising: an input pin row including a plurality of input pins; an output pin row including a plurality of output pins; a memory cell array including a plurality of cell plates in a plurality of cell columns between the input and output pin rows; a plurality of sense amplifiers in two amplifier columns disposed between the adjacent two of the plurality of cell columns; an address circuitry; an address transition detector (ATD) circuitry to provide an ATD pulse upon detecting a transition in the address circuitry: an ATD pulse synthesizer to provide a synthesized pulse in response to the ATD pulse; an output circuitry; and a delay circuitry to provide a sense amplifier data latch signal and an output data latch signal in response to the synthesized pulse from the ATD pulse synthesizer, at least the address, ATD and delay circuitries being disposed between the input pin row and the plurality of cell columns, the ATD pulse synthesizer being disposed between the two amplifier columns and spaced a predetermined signal transmission path from the ATD and delay circuitries.