Patent ID: 7840743

Claim:
A double network physical isolation circuit comprising: a bus switch circuit comprising a first bus switch chip comprising first input and first output pins and second input and second output pins, and a second bus switch chip; a first memory; a second memory; and a north bridge chip connected to the first memory through the first input and first output pins, and connected to the second memory through the second input and second output pins; wherein the first memory and the second memory are connected to different networks; upon a condition that the bus switch circuit receives a high level signal, the first input pin is electrically communicating with the first output pin, the first memory is activated, and the second memory is grounded through the second bus switch chip; upon a condition that the bus switch circuit receives a low level signal, the second input pin is electrically communicating with the second output pin, the second memory is activated, and the first memory is grounded through the second bus switch chip; the low level signal has a lower voltage than the high level signal.