Patent ID: 8521794

Claim:
A signal processing circuit comprising: a main path configured to transmit an input signal and output an actual signal; and a negative feedback path configured to feed back the actual signal to an input circuit of the main path, wherein the main path includes a main path circuit that receives the input signal and outputs the actual signal, the negative feedback path includes a negative feedback circuit that generates a control signal and supplies the control signal to an input side of the main path; a replica circuit that is supplied with the control signal of the negative feedback circuit to output a pseudo actual signal, and imitates the main path circuit; and a signal delay circuit that delays the pseudo actual signal of the replica circuit by a dead time of a loop, a first local negative feedback loop including a dead time is so formed as to include the negative feedback circuit, the replica circuit, and the signal delay circuit, a second local negative feedback loop including no dead time is formed by the negative feedback circuit and the replica circuit, and the first local negative feedback loop synthesizes a synthesized signal from an output signal of the signal delay circuit and the actual signal and inputs the synthesized signal to the negative feedback circuit.