Patent ID: 7523244

Claim:
A memory module comprising: a first signal line to carry a first signal that enters the memory module at a first end of the first signal line, and a second signal line to carry a second signal that enters the memory module at a first end of the second signal line, wherein each respective first end is coupled to receive a respective signal at a respective edge finger of a first plurality of edge fingers, wherein the first signal line and the second signal line each have a respective second end coupled to a termination; a first synchronous memory device disposed on a first side of the memory module, wherein the first synchronous memory device is connected to the first signal line and the second signal line; a second synchronous memory device disposed on a second side of the memory module, wherein the second side is positioned opposite to the first side, the second synchronous memory device is connected to the first signal line and the second signal line, and the first signal traverses the first signal line alongside the second signal; and wherein the first signal arrives at the first synchronous memory device before arriving at the second synchronous memory device and the first signal arrives at the second synchronous memory device before reaching the termination coupled to the second end of the first signal line, and wherein the second signal arrives at the first synchronous memory device before arriving at the second synchronous memory device and the second signal arrives at the second synchronous memory device before reaching the termination coupled to the second end of the second signal line.