Patent ID: 8687006

Claim:
A display device comprising: a display panel comprising pixels and divided into a first display region and a second display region; a first image interpolation chip which receives an original image signal and only outputs a previous (nâˆ’1)-th frame of the original image signal and one of a Â¼-th interpolated frame, a Â½-th interpolated frame and a Â¾-th interpolated frame, the one of the Â¼-th interpolated frame, the Â½-th interpolated frame and the Â¾-th interpolated frame being inserted between the previous (nâˆ’1)-th frame of the original image signal and a current n-th frame of the original image signal; a second image interpolation chip which receives the original image signal and outputs two of the Â¼-th interpolated frame, the Â½-th interpolated frame and the Â¾-th interpolated frame; a first timing unit which receives the previous (nâˆ’1)-th frame and the one of the Â¼-th interpolated frame, the Â½-th interpolated frame and the Â¾-th interpolated frame from the first image interpolation chip and outputs a first quadruple-speed image signal to the pixels in the first display region; and a second timing unit which receives the two of the Â¼-th interpolated frame, the Â½-th interpolated frame and the Â¾-th interpolated frame from the second image interpolation chip and outputs a second quadruple-speed image signal to pixels in the second display region, wherein the first timing unit transmits data corresponding to the previous (nâˆ’1)-th frame and the one of the Â¼-th interpolated frame, the Â½-th interpolated frame and the Â¾-th interpolated frame to the second timing unit, and the second timing unit transmits data corresponding to the two of the Â¼-th interpolated frame, the Â½-th interpolated frame and the Â¾-th interpolated frame to the first timing unit.