Patent ID: 7584389

Claim:
A memory buffer for receiving a frame comprised of sequential input symbols and providing the input symbols to an N-window mode Soft-In Soft-Out (SISO) decoder having a window size of W symbols, comprising: a first shift register having an input terminal, an output terminal and a clock input terminal, for sequentially shifting and storing 2NW serial symbols from the input terminal in a predetermined direction, and sequentially outputting the shifted symbols via the output terminal; and N second shift registers, wherein each of the second shift registers includes a clock input terminal, first and second input terminals, first and second output terminals, and select terminals, the second shift registers are sequentially activated or initialized at intervals of W symbols from serial symbols received at the input terminal of the first shift register, each of the second shift registers receives first NW symbols among the serial symbols after its activation, and shifts and stores the received symbols in the predetermined direction, thereafter, each of the second shift registers receives second NW symbols via its second input terminal, shifts and stores the received symbols in the opposite direction of the predetermined direction, and at the same time, serially outputs the stored first NW symbols via its first output terminal, thereafter, each of the second shift registers receives third NW symbols via the first input terminal, shifts and stores the received symbols in the predetermined direction, and at the same time, serially outputs the stored second NW symbols via its second output terminal, wherein N refers to an integer and a number of windows, W refers to an integer and a size of windows, NW refers to N times W and a length of data bit streams, and 2NW refers to two (2) times NW.