Patent ID: 8386967

Claim:
A method for scanning a semiconductor layout, the layout comprising objects with edges and corners, the method comprising: finding a pair of edges of the objects, where: a first edge and a second edge of the pair are not in contact with each other, the first edge and the second edge comprise a locally closest point pair comprising a first point on the first edge and a second point on the second edge, where a distance between the first point and the second point is the shortest distance between the first edge and the second edge, a convex area exists whose intersection with the objects consists only of a portion of the first edge and a portion of the second edge, thereby significantly reducing the number of edge pairs that will be found, and creating a proximity relation between the first edge and the second edge, the proximity relation being created only between directly neighboring edges and/or corners and the proximity relation being determined by the layout topology, and storing the proximity relation in a proximity relations table of a database together with a reference to the corresponding pair of edges.