Patent ID: 7454302

Claim:
A computer program product, comprising a computer readable medium having a computer readable program code embodied therein, said computer readable program code comprising an algorithm adapted to implement a method for inspecting integrated circuit chips during fabrication, said method comprising the steps of: storing coordinates of potential failures of an integrated circuit chip based on one or more risk of failure analyses performed ancillary to fabrication of said integrated circuit chip; automatically generating one or more enhanced defect inspection regions for inspecting images of said integrated circuit chip based on said coordinates; automatically selecting one or more enhanced defect inspection parameters for each of said one or more enhanced defect inspection regions based on said one or more risk of failure analyses; generating an enhanced defect inspection recipe, said enhanced defect inspection recipe including locations of said one or more enhanced defect inspection regions on said integrated circuit chip, an enhanced defect inspection parameter and a value for said enhanced defect inspection parameter for each of said one or more enhanced defect inspection regions; transferring a defect inspection recipe based on said enhanced defect inspection recipe to a defect inspection tool; and performing an analysis of an amount of time required to inspect said integrated circuit chip using said enhanced defect inspection recipe and modifying said enhanced defect inspection recipe if said amount of time exceeds a predetermined amount of inspection time.