Patent ID: 7456651

Claim:
An on-die termination (ODT) apparatus for a semiconductor memory, comprising: a first D/A converting unit that outputs a first voltage corresponding to a first code; a first comparing unit that compares the first voltage with a reference voltage and corrects comparison results between the first voltage and the reference voltage, to output first comparison signals, wherein an initial operating time of the first comparing unit is later than an initial operation time of the first D/A converting unit; a first counter that counts up or down the first code to correspond to the first comparison signals; a second D/A converting unit that outputs a second voltage corresponding to a second code; a second comparing unit that compares the second voltage with the reference voltage and corrects comparison results between the second voltage and the reference voltage, to output second comparison signals, wherein an initial operating time of the second comparing unit is later than an initial operation time of the second D/A converting unit; a second counter that counts up or down the second code to correspond to the second comparison signals; and a timing control unit that controls timings when the first D/A converting unit, the first comparing unit, the first counter, the second D/A converting unit, the second comparing unit, and the second counter start to operate.