Patent ID: 6993704

Claim:
A method of turbo decoding comprising the steps of: (A) initially (1) computing beta state metrics for a sliding window of data, (2) setting a current physical addressing order to a first physical addressing order, (3) storing said beta state metrics for the sliding window of data in a scratch memory in the first physical addressing order; (B) then repetitively for each sliding window (1) toggling the current physical addressing order for a current repetition between the first physical addressing order and a second physical addressing order, said second physical addressing order being opposite to said first physical addressing order, (2) computing alpha state metrics for the sliding window of data, (3) reading beta state metrics from the scratch memory in the current physical addressing order for the current repetition, (4) combining the computed alpha state metrics and the beta state metrics read from the scratch memory in an extrinsic block thereby producing extrinsic outputs, (5) computing beta state metrics for a next sliding window of data, (6) storing said beta state metrics for the next sliding window of data in a scratch memory in the current physical addressing order of the current repetition, until a frame of data including a plurality of sliding windows is decoded; wherein: the steps of (3) reading beta state metrics from the scratch memory in the current physical addressing order for the current repetition and (6) storing said beta state metrics for the next sliding window of data in a scratch memory in the current physical addressing order of the current repetition includes generating a virtual address and mapping the virtual address to a physical address; and the step of toggling the current physical addressing order for a current repetition includes toggling a digital state of an address flip bit controlling an order of mapping of the virtual address to the physical address, wherein storing said beta state metrics always occurs in a first virtual addressing order and is mapped to the first physical address order if the address flip bit has a first digital state and is mapped to the second physical address order if the address flip bit has a second digital state opposite to the first digital state, and reading said beta state metrics always occurs in a second virtual addressing order, the second virtual addressing order opposite to said third addressing order, and is mapped to the second physical address order if the address flip bit has the first digital state and is mapped to the first physical address order if the address flip bit has the second digital.