Patent ID: 8276270

Claim:
A method for manufacturing a printed circuit board in which a plurality of conductive layers forming wiring pattern are laminated with an insulting layer or layers being sandwiched and a portion or portions between the conductive layers is or are connected by a via fill or fills so that they electrically conduct to each other, the printed circuit board manufacturing method including: a step of forming a via fill to allow electroless copper plating liquid to be in contact with a surface of a wiring pattern exposed to a bottom part of a via hole formed at the insulating layer to laminate copper plating metallic film from the bottom part to an opening part of the via hole without applying catalyst; and a step of forming a wiring pattern to form electroless plating metallic film serving as the wiring pattern onto a substrate where the via fill is formed by the electroless copper plating, wherein the step of forming the wiring pattern comprises applying a palladium catalyst on the substrate, forming a resist pattern, and then reducing and activating the palladium catalyst.