Patent ID: 8218387

Claim:
A semiconductor storage device comprising: a memory cell array formed using a vertical transistor which has a structure where a drain, a gate, and a source are arranged in a vertical direction with respect to a pillar-shaped semiconductor layer and a gate electrode surrounds the pillar-shaped semiconductor layer; first bit lines formed by a first layer, said first bit lines being wired in a row direction so that each first bit line is connected to a sense amplifier; second bit lines formed by a second layer, said second bit lines being wired in the row direction so that each second bit line is connected to a sense amplifier; and a plurality of vertical transistors and a plurality of contacts formed on each first bit line, wherein each vertical transistor is a first transistor for selecting a memory cell, and a gate electrode of the first transistor is connected to a corresponding one of word lines wired in a column direction, wherein each first bit line and a corresponding second bit line are connected to one another through a corresponding contact formed on each first bit line.