Patent ID: 7844847

Claim:
A radio frequency integrated circuit comprising: a clock signal line coupled to a clock generator for carrying a first clock signal, wherein the first clock signal represents a first clock rate; a first gating block coupled to the clock signal line, and configured to slow the first clock rate to a second clock rate that is determined at least in part by a value M, the first gating block comprising a first counter having the first clock rate and the value M as inputs, the first counter configured to generate a first output signal each time the first counter counts M pulses of the first clock rate; a first processing block coupled to the first gating block, wherein the first processing block operates at the second clock rate; a second gating block coupled to the clock signal line, and configured to slow the first clock rate to a third clock rate that is determined at least in part by a value N, the second gating block comprising a second counter having the first clock rate and the value N as inputs, the second counter configured to generate a second output signal each time the second counter counts N pulses of the first clock rate; and a second processing block coupled to the first processing block and the second gating block, wherein the second processing block operates at the third clock rate, and wherein synchronicity is maintained between the first and second processing blocks by the first processing block changing a flag state when transmitting a data sample to the second processing block; and the values M and N are dynamically set by a processor that controls the integrated circuit.