Patent ID: 8863069

Claim:
A computer-implemented method comprising: receiving an executable, source graphical model configured to execute over one or more model steps, the model having at least one data path having a plurality of interconnected blocks, where data associated with the at least one data path has a first vector width; generating, by a first processor, an in-memory representation of the source graphical model, the in-memory representation having a plurality of functional components that relate to the plurality of interconnected blocks of the at least one data path; modifying the in-memory representation automatically to create a modified in-memory representation, the modifying including: adding at least one serializer component to the in-memory representation, the at least one serializer component configured to convert the data associated with the at least one data path to a second vector width, where the second vector width is smaller than the first vector width, adding at least one deserializer component to the in-memory representation, the at least one deserializer configured to convert the data associated with the at least one data path from the second vector width to a third vector width, configuring the plurality of functional components of the in-memory representation to operate on data corresponding to the second vector width, and configuring the plurality functional components of the in-memory representation to operate at a higher clock rate relative to a clock rate that corresponds to the one or more model steps; and generating from the modified in-memory representation, by the first or a second processor, one or more of an executable validation graphical model, a report, and a hardware description.