Patent ID: 7418686

Claim:
A processor-based method for floor planning an integrated circuit design, comprising: establishing in a memory arrangement a plurality of physical blocks in response to user input, wherein each physical block has associated data that indicates a physical area of an integrated circuit to be occupied by logic assigned to the physical block; assigning each logic block of a logic block hierarchy to one of the plurality of physical blocks in response to user input; in response to assigning a first logic block to one of the physical blocks, traversing the logic block hierarchy beginning at the first logic block and assigning all children logic blocks of the first logic block to the physical block; creating pins and nets that connect logic blocks assigned to the physical blocks as a function of locations of the physical blocks on the integrated circuit and connections defined by the logic block hierarchy reassigning, in response to user input, a child logic block of a first logic block that is assigned to a first physical block to a second physical block; de-assigning the first logic block from the first physical block in response to the first logic block having children logic blocks assigned to different physical blocks; wherein each physical block has associated data that indicates each logic block assigned to the physical block; determining from the logic block hierarchy children blocks of the first logic block; and determining from the physical blocks whether any children logic blocks of the first logic block are assigned to different physical blocks.