Patent ID: 7826581

Claim:
An apparatus, comprising: a phase lock and tracking logic circuit configured to detect a plurality of values, each indicating a position of an edge, and to add the plurality of values to generate a result; to adjust a clock signal if the result is greater than a predetermined value; to maintain the clock signal approximately between an end of a first data packet and a beginning of a second data packet: said phase lock and tracking logic circuit comprising: a phase detector to generate an acquisition phase signal including a coder to generate a plurality of values; and a tracking circuit coupled to the coder to generate a tracking phase signal corresponding to an relative linear phase signal with respect to the clock signal, including, an accumulator coupled to the coder to generate a phase modifier signal in response to a determination that an accumulation signal surpasses a threshold; and a decoder coupled to the accumulator to generate the tracking phase signal based on a comparison of the phase modifier signal and a current chosen phase; a multi-bit control bus coupled to the phase lock and tracking logic circuit; and a control circuit coupled to the multi-bit control bus, wherein the control circuit is configured to generate a hold control signal, a tracking control signal and an acquisition control signal, the multi-bit control bus to communicate at least one of the hold control signal, the tracking control signal, and the acquisition control signal to the phase lock and tracking logic circuit, wherein the control circuit comprises: a multiplexer coupled to the phase lock and tracking logic circuit to select from among a plurality of sampling phase signals and provide a single one of the plurality of phase signals to the phase lock and tracking logic circuit.