Patent ID: 7978001

Claim:
A microprocessor, comprising: a first supply node providing a first core voltage; a functional block having a plurality of power modes, comprising: a plurality of semiconductor devices, each having a substrate connection; and a first substrate bias rail routed within said functional block and coupled to said substrate connection of at least one of said plurality of semiconductor devices; a first charge node; first select logic which couples said first substrate bias rail to said first charge node when said functional block is in a low power mode and which clamps said first substrate bias rail at a first location of said first substrate bias rail to said first supply node when said functional block is in a full power mode; and substrate bias logic which charges said first charge node to a first bias voltage at a first offset voltage relative to said first core voltage when said functional block is in said low power mode, wherein said substrate bias logic comprises a bias generator which charges said first charge node when said functional block is in said low power mode and which drives said first charge node to said first core voltage when said functional block transitions to said full power mode.