Patent ID: 8334712

Claim:
A synchronizer comprising: a first set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of said first set responsive to a first edge of a common clocking signal to transfer a respective signal appearing at the respective latch input to the respective latch output and the penultimate latch of said first set responsive to a second edge of the common clocking signal to transfer a respective signal appearing at the respective latch input to the respective latch output, the second edge opposing the first edge; a second set of three serially coupled latches coupled to the common clocking signal, the first and the ultimate latch of said second set responsive to the second edge of the common clocking signal to transfer a respective signal appearing at the respective latch input to the respective latch output and the penultimate latch of said second set responsive to the first edge of the common clocking signal to transfer a respective signal appearing at the penultimate latch input to the penultimate latch output; an input lead arranged to receive an input signal to be synchronized, said input lead coupled to the input of the first latch of said first set and to the input of the first latch of said second set; and a filter arranged to pass the output of each of said first set and said second set responsive to the penultimate latch of the set exhibiting a consonant output for two consecutive opposing edges of the common clocking signal.