Patent ID: 7358129

Claim:
A method for producing a nonvolatile semiconductor for memory device, including plural memory cells which each comprise a field effect transistor comprising: a first gate insulator film which is formed over a main face of a semiconductor substrate of a first conductivity type; a selector gate which is formed over the first gate insulator film and has side faces and a top face covered with a first insulator film; one out of floating gates which are formed, in a side-wall form, over both sides of the selector gate and are electrically separated from the selector gate by the first insulator film; a second gate insulator film formed to cover the surface of the floating gate; and a control gate which is formed over the second gate insulator film, is electrically separated from the floating gate by the second gate insulator film, and is electrically separated from the selector gate by the second gate insulator film and the first insulator film, the memory cells being arranged in a matrix form along a first direction of the main face of the semiconductor substrate and along a second direction perpendicular to the first direction, wherein the control gates of the memory cells arranged in each row along the first direction are connected to each other to constitute a word line, and wherein the selector gates of the memory cells arranged in each column along the second direction are connected to each other, comprising the steps of: (a) forming the first gate insulator film over the main face of the semiconductor substrate, forming a first electroconductive film over the first gate insulator film, and then forming the first insulator film over the first electroconductive film; (b) patterning the first insulator film and the first electroconductive film, thereby forming the selector gates the top of which are covered with the first insulator film; (c) covering side faces and top faces of the selector gates with the first insulator film by oxidizing side walls of the selector gates thermally; (d) subjecting a second electroconductive film formed over the semiconductor substrate after the step (c), thereby forming the floating gates which are formed, in a side wall form, over both sides of each of the selector gates and are electrically separated from the selector gate through the first insulator film; (e) forming the second gate insulator film covering the surfaces of the floating gates and having portions being in contact with the surface of the semiconductor substrate; and (f) patterning a third electroconductive film formed over the second gate insulator film, thereby forming the control gates, wherein at the time of subjecting the second electroconductive film to anisotropic etching to form the floating gates, the gate length of the floating gate is made shorter than the gate length of the selector gate in each of the memory cells.