Patent ID: 8730723

Claim:
A non-volatile memory structure comprising: a MOSFET comprising: a storage layer for storing charge representing any one of P different values; and a control gate; a source of 2 n different voltage levels in sequence, wherein the MOSFET generates a corresponding response current in response to the 2 n different voltage levels in sequence from the source being applied to the control gate; a first determining circuit for comparing the response current, a low-bound current level and a high bound current level to determine whether to pass an n-bit data corresponding to the 2 n different voltage levels; and a second determining circuit for measuring the response current according to (2 m −1) different reference current levels to obtain an m-bit data and for determining whether to pass the m-bit data according to the result of comparing; wherein the n-bit data and the m-bit data form the P different values, where n≠0, m≠0, log 2 P=(m+n) and P is an integer greater than two.