Patent ID: 8549217

Claim:
A computer system, comprising: at least one processor; a volatile memory comprising a plurality of memory chips; chip select logic operatively connected to the memory chips of the volatile memory, wherein the chip select logic generates a plurality of chip select signals each enabling a respective one of the memory chips of the volatile memory to define a chip select; a memory controller operatively connecting the at least one processor to the volatile memory, the memory controller performing the steps of: generating periodic command requests on a per chip select basis, wherein the timing of each periodic command request is based on a timer reaching a predetermined time-out value; issuing periodic commands to the volatile memory, the periodic commands being issued on a per chip select basis in response to the periodic command requests; monitoring the periodic command requests for collisions between two or more of the periodic command requests; if a collision is detected between two or more of the periodic command requests, spacing the timing of subsequently generated periodic command requests corresponding to the colliding periodic command requests so that the subsequently generated periodic command requests are spaced apart with respect to one another by a timer offset applied on a chip select basis to the timer.