Patent ID: 8707230

Claim:
An integrated circuit (IC) simulation method, comprising (a) providing a device process model from at least one non-transitory machine readable storage medium into a programmed computer, the device process model including one or more device variables, each device variable defining a probability distribution of an active-device-level variation of devices in an IC; (b) providing at least one of the group consisting of a conductive line model and a multi patterning technology (MPT) model from the storage medium to the computer, the conductive line model including one or more conductive line variables, each conductive line variable defining a probability distribution of a conductive-line process-induced variation in the IC, the MPT model including one or more MPT variables, each MPT variable defining a probability distribution of a mask-misalignment-induced conductive line coupling variation in the IC; and (c) performing in the computer a Monte Carlo simulation of the IC including the device process model and the at least one of the group consisting of the conductive line model and the MPT model, to identify parasitic couplings in the IC.