Patent ID: 7054215

Claim:
A memory circuit comprising: (1) a node for serially providing data read out of memory cells; (2) circuitry comprising M stages S 1 , . . . S M , where M>1, for holding sets of N data bits (D 0 , D 1 , . . . D N-1 ) read out of memory cells before serially providing the data bits to said node in the order D 0 , D 1 , . . . , D N-1 , where N≧2, wherein each set of N data bits is read out of the memory cells in parallel, wherein each stage S i (i<M) has at least N outputs for providing each set in parallel; (3) a clock signal generator for generating one or more first clock signals and one or more second clock signals, wherein: the stage S M-1 is responsive to one or more of the first clock signals to provide the data bit D 0 of each set to said node; wherein the stage S M is responsive to the one or more second clock signals for serially providing the bits D 1 , . . . D N-1 to said node; wherein the one or more first clock signals are not a function of any second clock signal.