Patent ID: 7375561

Claim:
A timing adjustment circuit applied to adjust receiving timing of an output signal transmitted from a first chip and received by a second chip comprising: a timing adjustment unit for receiving a base clock, adjusting phase of the base clock, and generating a receiving-end clock signal while a second functional unit of the second chip receiving the output signal transmitted from a first functional unit of the first chip according to the receiving-end clock signal; a multistage sample circuit receiving the receiving-end clock signal to generate a plurality of sample clock signal and then sample the output signals according to the sample clock signals to produce a plurality of sampled signal; and a decision circuit receiving the sampled signals and making comparison of the sampled signals in accordance with the output signal to generate a second adjustment signal, wherein the second adjustment signal is transmitted to the timing adjustment unit for adjusting phase of the base clock and generating an adjusted receiving-end clock signal so as to adjust the receiving timing of the output signal received by the second functional unit.