Patent ID: 8441292

Claim:
Apparatus (e.g., 220 ) for delaying an incoming data signal (e.g., 215 ) by adjusting an incoming clock signal (e.g., 217 ) associated with the incoming data signal to generate an outgoing clock signal (e.g., 227 ), the apparatus comprising: first circuitry (e.g., 302 , 310 , 312 , 314 ) adapted to process the incoming data signal to generate an outgoing data signal (e.g., 225 ); second circuitry (e.g., 304 , 306 , 316 , 318 ) adapted to generate a first clock signal (e.g., ck 2 _del 1 ) and a second clock signal (e.g., ck 2 _del 2 ) based on the incoming clock signal; third circuitry (e.g., 308 , 320 , 322 , 324 , 326 , 328 , 330 , 332 ) adapted to process a delay control signal (e.g., 127 ) to generate a plurality of selection control signals (e.g., cka_, hi_, ckb_); and fourth circuitry (e.g., 334 ) adapted to receive (i) a plurality of input signals including the first and second clock signals and (ii) the plurality of selection control signals and to present one of the input signals as an output signal (e.g., ckdiv 2 _mux) from the fourth circuitry based on the selection control signals, wherein: the outgoing clock signal is based on the output signal from the fourth circuitry; and the adjustment applied to the incoming clock signal to generate the outgoing clock signal corresponds to a delay of the outgoing data signal relative to the incoming data signal.