Patent ID: 8494109

Claim:
A shift register configured such that a plurality of unit circuits are cascade-connected and operating based on a plurality of clock signals, wherein each unit circuit includes: an output transistor having one conducting terminal supplied with one of the clock signals and the other conducting terminal connected to an output node; an input transistor configured to apply an ON potential to a control terminal of the output transistor according to a set signal that has been supplied; an output reset transistor configured to apply an OFF potential to the output node according to an output reset signal that has been supplied; an additional output transistor having a control terminal and one conducting terminal connected in an identical configuration with that of the output transistor, and having the other conducting terminal connected to an additional output node; and a compensation circuit configured to apply a compensation potential to the additional output node at predetermined timing, a polarity of the compensation potential being opposite to that of the ON potential taking the OFF potential as a reference, and the output reset transistor is supplied with a signal outputted from an additional output node included in a next stage unit circuit as the output reset signal.