Patent ID: 7705645

Claim:
A timing generation circuit, comprising: a first loop circuit and a second loop circuit, each of which is supplied with a common reference clock signal and each of which outputs a clock signal delayed from the common reference clock signal; and a clock generation circuit for generating a delayed clock signal from the clock signals output from the first loop circuit and the second loop circuit, the delayed clock signal including any one of a rising edge and a falling edge with a delay from a rising edge of the common reference clock signal and including the other of the rising edge and the falling edge with a delay from a falling edge of the common reference clock signal, wherein: the first loop circuit outputs the clock signal whose logic level transitions with a delay from a rising edge of the common reference clock signal, the delay being equal to a half of an on-duty period of the common reference clock signal; and the second loop circuit outputs the clock signal whose logic level transitions with a delay from a falling edge of the common reference clock signal, the delay being equal to a half of an off-duty period of the common reference clock signal.