Patent ID: 8707242

Claim:
A method for optimizing a circuit design, the method comprising: receiving the circuit design; and optimizing, by computer, gate sizes in the circuit design, wherein said optimizing comprises iteratively performing a set of operations, the set of operations comprising: selecting a portion of the circuit design, selecting an input-to-output arc of a driver gate in the portion of the circuit design, selecting gates in the portion of the circuit design for optimization, modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, wherein said modeling uses a specific numerical delay model for the driver gate and generic numerical delay models for the selected gates, wherein the specific numerical delay model models the delay behavior of the selected input-to-output arc of the driver gate, and wherein, for each selected gate, the generic numerical delay model models an aggregated delay behavior of a library cell type associated with the selected gate, solving the gate optimization problem to obtain a solution, and discretizing the solution.