Patent ID: 8571044

Claim:
A gateway for data transfer between serial buses, comprising: multiple communication modules that are each provided for connection to a different serial bus, and that carry out a conversion between data packets (DP) and data words (DW); a bus master that, via an internal control bus, controls a word-based transfer of data via an internal data bus between two communication modules, wherein the bus master applies a source address (SA) via a source address bus to an internally transmitting first communication module, and a destination address (DA) via a separate destination address bus to an internally receiving second communication module; and data received in data packets (DP) by the first communication module via a first serial bus connected thereto being transferred from the first communication module directly without buffering outside the first and second communication modules, in word-based fashion in one or more data words, via the internal data bus to the second communication module, which transmits these transferred data, in data packets, via a second serial bus connected to the second communication module; wherein direct data transfer from the first communication module to the second communication module occurs within one clock cycle.