Patent ID: 7091545

Claim:
A memory device, comprising: a substrate with a plurality of deep trenches, wherein the deep trenches in adjacent rows are staggered; a plurality of deep trench capacitors disposed in the deep trenches of the substrate respectively; a plurality of control gates disposed on the deep trench capacitors respectively; a plurality of word lines disposed on the control gates respectively along a first direction, each word line being electrically coupled to the control gate thereunder; a plurality of diffusion regions disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors, wherein each diffusion region is electrically connected to the surrounding deep trench capacitor; a plurality of active areas disposed on the rows of the control gates respectively along a second direction, wherein the diffusion regions where each active area overlaps the control gates have at least one indentation; and a plurality of drains disposed in the active areas beside each word line.