Patent ID: 8400187

Claim:
A logic circuit comprising: a first thin film transistor comprising a first terminal which is electrically connected to a high power supply potential line; a second thin film transistor comprising a gate terminal which is electrically connected to an input terminal, and a first terminal which is electrically connected to a gate terminal and a second terminal of the first thin film transistor; a third thin film transistor comprising a gate terminal which is electrically connected to a pulse signal line, a first terminal which is electrically connected to a second terminal of the second thin film transistor, and a second terminal which is electrically connected to a low power supply potential line; a fourth thin film transistor comprising a gate terminal which is electrically connected to the pulse signal line, a first terminal which is electrically connected to the gate terminal and the second terminal of the first thin film transistor and the first terminal of the second thin film transistor, and a second terminal which is electrically connected to an output terminal; and a capacitor, wherein the second terminal of the fourth thin film transistor is electrically connected to a node which is brought into a floating state by turning off the fourth thin film transistor, wherein one terminal of the capacitor is electrically connected to the second terminal of the fourth thin film transistor, the node and the output terminal, and wherein a channel formation region of the fourth thin film transistor comprises an oxide semiconductor.