Patent ID: 8079019

Claim:
A data processing system, comprising: a processor; a storage system; first logic, coupled to the storage system and to a unit under test comprising a heap memory, a static memory and a stack, wherein the first logic when executed is operable to interface to the heap memory and the static memory; second logic which when executed is operable to perform: detecting one or more changes in a first state of the heap memory and the static memory; storing, in the storage system, as a state point of the unit under test, the one or more changes in the first state of the heap memory and the static memory; third logic which when executed is operable to perform: receiving a request to change the memory under test to a particular state point; in response to the request, loading the particular state point from the storage system and applying the particular state point to the heap memory and the static memory to result in changing the heap memory and the static memory to a second state that is substantially equivalent to the first state; wherein the second logic when executed is operable to further perform: causing the unit under test to write-protect all pages of the heap memory and the static memory; installing in the unit under test a first exception handler responsive to a first write exception of the heap memory and a second exception handler responsive to a second exception of the static memory, wherein the exception handlers are configured to respond to a particular write exception of a particular page by storing a second page that is a copy of the particular page, making the particular page writable, and restoring execution of the unit under test; comparing the second page to the particular page; creating and storing the one or more changes based on the comparing.