Patent ID: 7865695

Claim:
A system for data processing comprising: a host circuit; and an integrated circuit in communication with the host circuit, the host circuit being external to the integrated circuit, the integrated circuit comprising a host interface for receiving a host control signal and data from the host circuit, a crosspoint switch, and a plurality of programmable elements for data processing, each programmable element coupled to the host interface and the crosspoint switch and comprising a plurality of memory elements, an interconnect bus directly coupled to an output of each memory element, an element control module for generating an element control signal and communicating data to an input of a memory element, a memory write port for communicating data from the crosspoint switch to the interconnect bus, write selection circuitry for receiving data including a write value from all the programmable elements via the interconnect bus and selectively communicating the write value to the element control module according to the element control signal, read selection circuitry for receiving data including a read value from all the programmable elements via the interconnect bus and selectively communicating the read value to the crosspoint switch according to the element control signal, and a memory control module for controlling operation of the memory element according to the host control signal and the element control signal.