Patent ID: 8058105

Claim:
A method of fabricating a packaging structure, comprising: providing a panel of up-down paired packaging substrate, wherein two insulating protection layers having a plurality of openings are formed on two opposing outermost surfaces of the packaging substrate, respectively, and each of the openings has a metal bump installed therein; cutting the packaging substrate into a plurality of up-down paired packaging substrate blocks, each of the packaging substrate blocks having MÃ—N up-down paired packaging substrate units arranged in an array, wherein the metal bumps are formed on the packaging substrate units, and both M and N are an integer greater than one; installing a semiconductor chip on the metal bumps of each of the packaging substrate units, to form up-down paired packaging structure blocks having the packaging substrate units, each of the semiconductor chips having an active surface with a plurality of electrode pads formed thereon and electrically connected through solder bumps to the metal bumps; forming on the insulating protection layer and the semiconductor chips a packaging material, and filling a space between the semiconductor chips and the insulating protection layer with the packaging material to encapsulate the solder bumps; separating the packaging structure blocks, to form two independent packaging substrate blocks; and cutting the independent packaging structure blocks into a plurality of packaging structure units.