Patent ID: 7511377

Claim:
A semiconductor integrated circuit device comprising: a first first-channel MISFET and a second first-channel MISFET, each having a gate electrode; a first second-channel MISFET and a second second-channel MISFET, each having a gate electrode; a first insulating film formed on said gate electrodes of said first first-channel MISFET and said second first-channel MISFET and said first second-channel MISFET and said second second-channel MISFET; a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first first-channel MISFET, a drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET; a second conductive film formed on said first insulating film and being electrically connected to a drain region of said second first-channel MISFET, a drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET; a dielectric film formed on said first conductive film and said second conductive film; and a wiring line formed on said dielectric film and being electrically connected to a source region of said first first-channel MISFET and a source region of said second first-channel MISFET, wherein a first local wiring is comprised of a refractory metal film or a refractory metal silicide film, wherein the first conductive film has a thickness with a surface area of said first conductive film, said dielectric film, and said wiring line comprise a capacitor element, and wherein the second conductive film has a thickness with a surface area of said second conductive film, said dielectric film, and said wiring line comprise a capacitor element.