Patent ID: 7723748

Claim:
A semiconductor device, comprising: an electrostatic discharge protection circuit connected to an internal circuit, the electrostatic discharge protection circuit comprising: a SGPMOS transistor configured to connect a source and a gate to an input-output terminal, while connecting a drain to a ground terminal, the SGPMOS transistor comprising: a base including at least one of a N-type semiconductor substrate, a P-type semiconductor substrate, and a N-type well, and configured to form a channel; a P-type diffusion layer including a P-type source and a P-type drain provided on the base separated from each other; a gate electrode provided on the channel between the P-type source and the P-type drain across a gate insulator, at least the P-type drain comprising: a double diffusion structure comprising: a first P-type drain diffusion layer; and a second P-type drain diffusion layer provided on a surface of the first P-type drain diffusion layer, and configured to have a greater impurity density than that of the first P-type drain diffusion layer; and a LOCOS oxide film provided on a surface of the first P-type drain diffusion layer, and configured to have a greater thickness than that of the gate insulator and covered by an end of the gate electrode on a side of the P-type drain, the first P-type drain diffusion layer and the second P-type drain diffusion layer satisfying a relation of Y<Xj, in which Y represents a distance of the first P-type drain diffusion layer between the second P-type drain diffusion layer and the channel, and Xj represents a difference between depths of the second P-type drain diffusion layer and the first P-type drain diffusion layer, wherein the electrostatic discharge protection circuit comprises a thyristor connected to the SGPMOS transistor and the SGPMOS transistor is used as a trigger element for the thyristor.