Patent ID: 8269535

Claim:
A delay-locked loop (DLL), receiving an external clock signal and outputting an internal clock signal, comprising: a variable delay line, delaying the external clock signal for a specific delay time and outputting a delayed external clock signal; an inverting circuit, receiving the delayed external clock signal as input, outputting the delayed external clock signal directly as the internal clock signal in a high frequency mode, inverting the delayed external clock signal and outputting an inverted delayed external clock signal as the internal clock signal in a low frequency mode, wherein the high frequency mode and the low frequency mode are distinguished according to a comparison based on a period of the external clock signal and a maximum loop delay of the DLL; a phase detector, comparing a phase of the external clock signal and a phase of the internal clock signal, and outputting a result of the comparison of the phases; and a control circuit, adjusting the specific delay time of the variable delay line according to the result of the comparison of the phases in order to synchronize the internal clock signal with the external clock signal.