Patent ID: 8633591

Claim:
A electronic device comprising: an interconnect layer having a first main surface and a second main surface opposite the first main surface; a first semiconductor chip arranged above the first main surface and having a first obverse surface, a CPU circuit formed on the first obverse surface; a plurality of second semiconductor chips arranged above the first main surface and laminated to each other; a third semiconductor chip having a second obverse surface, an electrode formed on the second obverse surface; and a plurality of external electrodes formed on the second main surface of the interconnect layer, wherein each of the second semiconductor chips has an upper surface and a back surface opposite the upper surface, a memory circuit on the upper surface, and a through via plug formed from the upper surface to the back surface, wherein the second semiconductor chips are electrically connected each other through the through via plugs, wherein a first conductive plug connects the electrode with the through via plug, wherein the third semiconductor chip is arranged in vertical registration right under the second semiconductor chips and the third semiconductor chip is located within an outer perimeter of the second semiconductor chips in a plan view, and wherein, in a cross section view, the through via plug, the first conductive plug and the electrode are arranged vertically in a straight line in a middle part of the second semiconductor chips and the third semiconductor chip.