Patent ID: 7990974

Claim:
A method for packet processing on a multi-core processor having a plurality of processing cores, the method comprising: configuring a first set of one or more of the plurality of processing cores to include the capability to process packets belonging to a first set of one or more packet types; configuring a second set of one or more of the plurality of processing cores to include the capability to process packets at least belonging to a second set of one or more packet types, the second set of packet types being a subset of the first set of packet types; receiving a first packet; determining that the first packet belongs to the second set of packet types and processing the first packet at one of the first or second set of processing cores; receiving a second packet; determining that the second packet does not belong to the second set of packet types and processing the second packet at one of the first set of processing cores, wherein each packet being processed includes a plurality of processing phases each identifiable by a phase identifier, and upon each processing phase being completed for a particular packet, associating the corresponding phase identifier with that packet; receiving a third, fourth, and fifth packet, the third and fourth packet belonging to the same flow, wherein at least one of the processing phases of the processing of the third packet is required to be performed prior to one of the processing phases of the processing of the fourth packet; assigning the third and fourth packets to different ones of the plurality of processing cores; processing the at least one of the processing phases of the processing of the third packet and stalling the processing of the fourth packet; upon determining that processing of the fourth packet is stalled, de-scheduling the processing of the fourth packet and allowing the processing core that was assigned to process the fourth packet to process the fifth packet; and upon the completion of that at least one processing phase of the third packet, releasing the stalling of the processing of the fourth packet allowing one of the processing cores to process the fourth packet at the particular processing phase when de-scheduled.