Patent ID: 8196088

Claim:
A method of measuring PFET-to-NFET device performance offset in a CMOS process, the method comprising: automatedly determining first frequencies of a model of a first complementary ring oscillator design in which all transistors therein are PFETs, the first frequencies corresponding respectively to differing sets of parameter values of the CMOS process; automatedly determining second frequencies of a model of a second complementary ring oscillator design in which all transistors therein are NFETs complementary to the PFETs of the first complementary ring oscillator, the second frequencies corresponding respectively to the differing sets of the parameter values of the CMOS process; and defining test screening limits as a function of the first and second frequencies; wherein said defining of the test screening limits includes: defining a lower PFET ring oscillator screening limit boundary; defining an upper PFET ring oscillator screening limit boundary; defining a lower NFET ring oscillator screening limit boundary; defining an upper NFET ring oscillator screening limit boundary; defining a first PFET-to-NFET ratio screening limit boundary extending between the lower PFET ring oscillator screening limit boundary and the upper NFET ring oscillator screening limit boundary; and defining a second PFET-to-NFET ratio screening limit boundary extending between the upper PFET ring oscillator screening limit boundary and the lower NFET ring oscillator screening limit boundary; wherein: the first frequencies have a first statistical distribution having a first standard deviation and said defining of the lower and upper PFET ring oscillator screening limit boundaries is performed as a function of the first standard deviation; and the second frequencies have a second statistical distribution having a second standard deviation and said defining of the lower and upper NFET ring oscillator screening limit boundaries is performed as a function of the second standard deviation.