Patent ID: 8595668

Claim:
A method of designing an integrated circuit, comprising: performing a logical synthesis process to generate a gate level representation of an integrated circuit design using one or more component cells selected from a cell library, wherein the selected component cells included in the gate level representation of the integrated circuit design include macro cells and configurable delay cell circuits; performing a placement process to place a configurable delay cell circuit in proximity to a macro cell in the integrated circuit design; performing a signal distribution network synthesis process to build a signal distribution network that is connected to an input of the configurable delay cell circuit in the integrated circuit design; performing a routing process to add wiring to the integrated circuit design; performing a timing analysis to determine if timing constraints for the integrated circuit design are satisfied; when a given timing constraint is not satisfied, replacing the configurable delay cell circuit in the integrated circuit design with a new configurable delay cell circuit which has a same footprint as the replaced configurable delay cell circuit, but which has a different delay characteristic that is selected to meet the given timing constraint; and repeating the timing analysis with the new configurable delay cell circuit, wherein the timing analysis is repeated without having to repeat the placement, signal distribution network synthesis, and routing processes, wherein the logical synthesis, placement, signal distribution network synthesis, routing and timing analysis processes are performed using a computer.