Patent ID: 7190839

Claim:
A method for generating a plurality of abstract image tiles to represent a source image for an integrated circuit (IC) layout, said method comprising the steps of: generating a first level of abstract image tiles within the IC layout, said first level of abstract image tiles having a first grouping of elements, each element having an “on” state or an “off” state to represent the source image with a first resolution; generating a plurality of additional levels of abstract image tiles within the IC layout, based on said first level of abstract image tiles, wherein each particular level of additional abstract image tiles has a particular grouping of elements to represent the source image with a particular resolution, wherein each particular grouping of elements has at least an element, wherein for an integer n greater than 1, generating each of plurality of n additional levels of abstract image tiles includes the steps of: directly generating a plurality of mappings between said first grouping of elements from said first level of abstract image tiles to said particular grouping of elements from said level n of abstract image tiles; generating for an element in said particular grouping an “on” element if said first grouping of elements mapped from said first level of abstract image tiles comprises a threshold density of “on” elements; and generating for an element in said particular grouping an “off” element if said first grouping of elements mapped from said first level of abstract image tiles does not comprise a threshold density of “on” elements.