Patent ID: 7793025

Claim:
A method for implementing interrupts in a data processing system, comprising: receiving one or more interrupt requests from one or more interrupt sources; selectively masking the one or more interrupt requests to generate one or more pending interrupt signals; providing a plurality of interrupt priority storage devices comprising a first interrupt priority storage device for storing priority level information associated with a first system mode, and a second interrupt priority storage device for storing priority level information associated with a second system mode; and providing a plurality of interrupt priority storage devices comprising a first interrupt priority storage device for storing priority level information associated with a first system mode for each of the one or more interrupt requests, and a second interrupt priority storage device for storing priority level information associated with a second system mode for each of the one or more interrupt requests; and selectively coupling, in response to a mode control signal, one of the plurality of interrupt priority storage devices to provide logic circuitry with priority level information corresponding to the mode control signal, where the logic circuitry uses the provided priority level information to prioritize one or more of the pending interrupt signals and also provides an interrupt request signal which will cause an interrupt to occur in the data processing system.