Patent ID: 8578304

Claim:
A computer-implemented method for implementing multiple mask lithography timing variation mitigation of an integrated circuit design comprising: providing an application specific integrated circuit (ASIC) library including at least one circuit device on a first mask, and at least one circuit device on a second mask by using a computer; identifying first circuit devices from said ASIC library in critical early mode paths and second circuit devices from said ASIC library in critical late mode paths in a circuit design; for identified first circuit devices in the critical early mode paths, placing the first circuit devices in the critical early mode paths on a single mask of either the first mask or the second mask; and for identified second circuit devices in the critical late mode paths, providing the identified second circuit devices in the critical late mode paths from the first mask and the second mask by moving the identified second circuit devices in the late mode paths to provide an even distribution of the second circuit devices between the first mask and the second mask.