Patent ID: 8373473

Claim:
A dual-loop phase lock loop, comprising: a phase frequency detector for generating a switch signal according to a difference between a reference clock and a divided feedback clock, the phase frequency detector having a first input terminal for receiving the reference clock, a second input terminal for receiving the divided feedback clock, and an output terminal for outputting the switch signal; a first charge pump having a first terminal coupled to the output terminal of the phase frequency detector for receiving the switch signal, a second terminal for receiving a first voltage, and a third terminal for outputting a coarse control voltage; a second charge pump having a first terminal coupled to the output terminal of the phase frequency detector for receiving the switch signal, a second terminal for receiving the first voltage, and a third terminal for outputting a pre-fine control voltage; a first capacitor having a first terminal coupled to the third terminal of the first charge pump, and a second terminal coupled to ground; a filter for filtering a high frequency component of the pre-fine control voltage, the filter having a first terminal coupled to the third terminal of the second charge pump, and a second terminal coupled to the ground; a first adder for generating a fine control voltage according to the pre-fine control voltage and the coarse control voltage, the first adder having a first terminal coupled to the third terminal of the first charge pump for receiving the coarse control voltage, a second terminal coupled to the third terminal of the second charge pump for receiving the pre-fine control voltage, and a third terminal for outputting the fine control voltage; a voltage control delay line having a first input terminal coupled to the third terminal of the first charge pump for receiving the coarse control voltage, a second input terminal coupled to the third terminal of the first adder for receiving the fine control voltage, and an output terminal for outputting a feedback clock; and a frequency divider coupled to the voltage control delay line and the phase frequency detector for dividing the feedback clock to output the divided feedback clock.