Patent ID: 7894252

Claim:
A magnetic memory cell comprising: a semiconductor substrate having doped therein a pair of N+ channels; a gate acting as a bottom read line disposed above the semiconductor substrate and spans substantially between the pair of N+ channels thereby creating a read access transistor; a magnetic media bit positioned above the gate; a magnetic sensor positioned above the magnetic media bit, wherein the magnetic sensor is at a proximate distance from the magnetic media bit and is magnetically coupled to the magnetic media bit; a read lead positioned between the magnetic sensor and the magnetic media bit and is coupled to the magnetic sensor and the magnetic media bit; at least one conductor positioned between the read lead and at least one N+ channel of the pair of N+ channels thereby ensuring conductivity between the read lead and the at least one N+ channel; and a top read line positioned above the magnetic sensor and is coupled to the magnetic sensor, wherein the top read line is a Y write line as well; wherein during a read operation, the read access transistor is turned on and a read current is applied to the top read line such that the read current flows from the magnetic sensor to the read lead to the at least one conductors and further to the pair of N+ channels thereby preventing the read current to pass through the magnetic media bit.