Patent ID: 7429773

Claim:
A semiconductor apparatus forming an insulating isolation region on a silicon substrate of an SOI (Silicon On Insulator) structure, wherein: the semiconductor apparatus comprises: a perfectly depleted or close to being perfectly depleted partially depleted-type MIS transistor formed on an electrically insulated silicon substrate surrounded by the insulating isolation region; and a capacitor formed using an insulating film, wherein the capacitor is configured from a capacitance between metal within a trench formed within the insulating isolation region and the silicon substrate and/or an impurity diffusion layer; an electrode connected to a gate electrode of the MIS transistor and an impurity diffusion layer formed within the silicon substrate and diffused with the same impurities as the silicon substrate are connected via the capacitor; and a BJT (Bipolar Junction Transistor) where a drain of the MIS transistor corresponds to a collector, the silicon substrate corresponds to a base, and a source corresponds to an emitter is formed, and where, when gate voltage with respect to the source is V GS , gate capacitance of the MIS transistor is C G , capacitance of the capacitor is C C , parasitic capacitance is C P , clamp voltage of the BJT is V C , and silicon substrate potential immediately prior to change in gate potential is V B(I) , then V B(I) +(C G +C C )*V GS /(C G +C C +C P )>V C .