Patent ID: 8395200

Claim:
A method for manufacturing a capacitor on an integrated circuit, the integrated circuit being associated with a channel length of less than 0.13 um, the method comprising: providing a substrate; providing a layer of inter metal dielectric overlaying the substrate; providing a bottom layer including a first portion and a second portion, the first portion being characterized as electrically conductive; providing a first insulating layer overlaying the bottom layer, the first insulating layer including one or more via plug openings positioned above the first portion; providing a first plurality of via plugs disposed within the one or more via plug openings, the first plurality of via plugs includes a first via plug and a second via plug, the first plurality of via plugs being electrically coupled to the first portion of the bottom layer; providing a capacitor layer including a first barrier metal electrically coupled to the first via plug, the capacitor layer further including a capacitor dielectric layer overlying the first barrier metal and a second barrier metal overlying the capacitor dielectric layer; defining a first capacitor layer portion and a second capacitor layer portion, the first capacitor layer portion being above the first via plug, the first capacitor layer portion including a first side and a second side, the second capacitor layer portion being above the second via plug; removing a portion of the second capacitor layer portion; providing a first spacer positioned against the first side; providing a second spacer positioned against the second side; providing a first electrical connection coupled to the first via plug; and providing a second electrical connection coupled to the second via plug.