Patent ID: 7444602

Claim:
A method of generating an application specific integrated circuit (ASIC) design database using each piece of software of a simulation tool, a logic synthesis tool, a timing analysis tool, a logic simulation tool, and a power consumption calculation tool when a function design using description data comprising a header portion and an entity portion has been performed, comprising: executing, simulation by the simulation tool; generating a simulation result list of the simulation; extracting a simulation time from the simulation result list; writing the extracted simulation time in the header portion of the description data; inputting the entity portion of the description data to the logic synthesis tool and executing a logic synthesis; outputting a gate-level net list; inputting the net list to the timing analysis tool and executing a timing analysis; outputting an analysis report as an analysis result; comparing values in the analysis report with pre-input desirable specifications; extracting, if the compared values satisfy the desirable specifications, timing information and layout area information, and writing the timing and layout area information in the header portion of the description data; executing a logic simulation for the gate-level net list by the logic simulation tool; inputting simulation data to the power consumption calculation tool and carrying out a power consumption calculation process; outputting a power consumption calculation result list; extracting power consumption information from the power consumption calculation result list and writing the power consumption information in the header portion of the description data; and storing, as one file at a predetermined location, the description data comprising the header portion in which the information necessary for reuse is written, and the entity portion.