Patent ID: 7834684

Claim:
A circuit comprising: a first row of first circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor, a connection between the first circuit block and the first sleep transistor comprising a virtual ground node, the first sleep transistors all being n-channel metal-oxide-semiconductor (NMOS) transistors or all being p-channel metal-oxide-semiconductor (PMOS) transistors; a second row of second circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor, a connection between the second circuit block and the second sleep transistor comprising a virtual supply node, the second sleep transistors all being PMOS transistors if the first sleep transistors are NMOS transistors or all being NMOS transistors if the first sleep transistors are PMOS transistors, the first and second rows being consecutive; and a transmission gate (TG) or a pass transistor connecting each of one or more of the virtual ground nodes to each of one or more of the virtual supply nodes to enable charge recycling between first circuit blocks in the first row and second circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.