Patent ID: 8742582

Claim:
A chip package comprising: a semiconductor chip comprising a semiconductor substrate, a first conductive structure coupled to said semiconductor substrate, wherein said first conductive structure comprises a first conductive layer and a second conductive layer coupled to said first conductive layer, a dielectric layer between said first and second conductive layers, a separating layer coupled tosaid semiconductor substrate, said first conductive structure and said dielectric layer, wherein an opening in said separating layer exposes a contact point of said first conductive structure, and said contact point is within said opening, and a second conductive structure on said contact point, wherein said second conductive structure is coupled to said contact point through said opening, wherein said second conductive structure comprises a first copper layer; a circuit substrate; a conductive interconnect between said second conductive structure and a conductive contact of said circuit substrate and coupled to said contact point, wherein said second conductive structure is coupled to said conductive contact through said conductive interconnect, wherein said conductive interconnect comprises tin, wherein from a first perspective view said conductive interconnect extends a distance greater than a width of said conductive interconnect, wherein a first contact area between said conductive contact and said conductive interconnect is greater than 30,000 square micrometers; and a first polymer layer and a second polymer layer between said semiconductor chip and said circuit substrate, wherein said first polymer layer contacts said semiconductor chip, said conductive structure, and a sidewall of said conductive interconnect, wherein said second polymer layer is directly coupled to said circuit substrate, directly on said first polymer layer, and directly coupled to said conductive interconnect at a sidewall of said conductive interconnect.