Patent ID: 7308530

Claim:
An architecture for a data storage device, comprising: a first data storage device control circuit that includes a first input/output (I/O) interface; and an application circuit including a buffer that stores application data and data storage device control data, a mapping driver that maps logical addresses to physical addresses, and a second I/O interface that communicates with at least one of said buffer and said mapping driver, wherein said physical addresses and data are transmitted by said second I/O interface to said first I/O interface, wherein said first data storage device control circuit includes a data storage device controller (DSDC), a data storage device processor, a spindle motor driver, a read/write arm driver, and a read channel driver, wherein said DSDC communicates with said first I/O interface and with at least one of said data storage device processor, said spindle motor driver, said read/write arm driver, and said read channel driver, wherein said application circuit includes at least one of an application specific integrated circuit (ASIC) and an application processor that communicates with said buffer, wherein at least one of said application processor and said ASIC sends a data request to said mapping driver, wherein said mapping driver periodically receives at least one of head location and sector location status from said DSDC, and wherein said mapping driver sends an estimated response time for said data request to said at least one of said application processor and said ASIC.