Patent ID: 7296124

Claim:
A device, comprising: an interface controller capable of controlling data transfers involving at least one memory, the data transfers comprising multiple streams of transactions, each stream comprising transactions associated with sequential blocks of memory locations, each transaction associated with at least one of the blocks of memory locations and with a starting address in the at least one memory, the interface controller comprising: a plurality of address buffers, each address buffer capable of storing at least one of: one or more of the starting addresses and one or more incremented addresses, wherein the one or more incremented addresses are obtained by incrementing one or more of the starting addresses at least once, wherein at least some of the address buffers store addresses associated with different streams of transactions, and wherein each different stream of transactions identifies one of the address buffers associated with that stream of transactions; wherein the interface controller is capable of using only a single starting address for each stream of transactions and interleaving at least two of the streams of transactions that are associated with different starting addresses, the single starting address associated with one stream of transactions stored and incremented in one of the address buffers, the single starting address associated with another stream of transactions stored and incremented in a different one of the address buffers.