Patent ID: 8174309

Claim:
A reference voltage circuit, comprising: a first depletion type NMOS transistor including: a gate connected to a first terminal; and a drain connected to a power supply terminal; a second depletion type NMOS transistor including: a gate connected to the gate of the first depletion type NMOS transistor; a source connected to a second terminal; and a drain connected to the power supply terminal; a first NMOS transistor including: a drain connected to the first terminal; and a source connected to a ground terminal; a second NMOS transistor including: a gate connected to a drain thereof, a gate of the first NMOS transistor, and the second terminal; and a source connected to a reference voltage output terminal, the second NMOS transistor having a threshold voltage lower than a threshold voltage of the first NMOS transistor; and a voltage generation circuit including a third depletion type NMOS transistor, for generating a reference voltage between the reference voltage output terminal and the ground terminal.