Patent ID: 8595660

Claim:
A method of automatically identifying level shifter circuits in a specification of a netlist of a circuit of a complex integrated circuit chip comprising a plurality of nets, said method comprising: obtaining a representation of said netlist in a computer readable form; using at least one computer processor, software, and memory to analyze said nets from said netlist, and for each analyzed net: determining at least one pair of directly cross-coupled PFET devices, and for each one pair of said directly cross-coupled PFET devices: using two netlist locations of said one pair of directly cross-coupled PFET devices as two PFET starting locations, tracing those nets that are coupled to each of said one pair of directly cross-coupled PFET devices and are also ultimately coupled to ground nets by way of intermediate NFET devices, thus determining two PFET to NFET to ground pathways (stacks); determining if said two PFET to NFET to ground pathways (stacks) are also cross-coupled and parallel: and if said two PFET to NFET to ground pathways (stacks) are also cross-coupled and parallel, then determining that said one pair of directly cross-coupled PFET devices and two PFET to NFET to ground pathways (stacks) are formed as a level shifter, thus making a level shifter determination; and storing said level shifter determination in said memory as a first level shifter determination.