Patent ID: 7082587

Claim:
A method for generating path delay data representing an estimated signal path delay through each of a plurality of signal paths within an integrated circuit (IC), wherein the IC includes a plurality of cells and a plurality of nets for conveying signals between the cells, the method comprising the steps of: a. selecting one of the nets; b. reading RC extraction data indicating an estimated impedance of each section of the net selected at step a from a database storing RC extraction data indicating an estimated impedance of each section of each of the plurality of nets, and computing as a function of the read RC extraction data, an estimated path delay through each section of the net selected at step a that is included in at least one of the plurality of signal paths; and c. adjusting the path delay data for each one of the plurality of signal paths that includes a section of the net selected at step a by incrementing an estimated signal path delay that the path delay data represents by an amount of the estimated path delay through that section of the net computed at step b.