Patent ID: 6944082

Claim:
A semiconductor memory device having a memory cell array in which dynamic memory cells are arranged in a matrix, the semiconductor memory device comprising: an external access timing signal generation module that generates a pulse signal, which changes to an active level in response to a variation of an external address supplied from an external device, as an external access timing signal representing a reference timing of an access operation requested from the external device; a refresh timer that generates a refresh timing signal representing a reference timing of a refresh operation of the memory cell array; and an access control module that controls execution of a read access, a write access, and a refresh operation of the memory cell array, even in the case of generation of a write access request or a refresh request in advance, the access control module preferentially executing a read access operation in response to a read access request generated by a change of the external access timing signal to an inactive level while a write enable signal supplied from the external device is at an inactive level.