Patent ID: 7342579

Claim:
A thin film transistor array plate, comprising: a substrate, having a display region and a peripheral circuit region; a plurality of pixel structures, disposed inside the display region; a plurality of switching devices, disposed inside the peripheral circuit region; a plurality of lead lines, disposed on the substrate, wherein each one of the lead lines electrically connects to the corresponding pixel structures and one of the switching devices; and a plurality of electrostatic discharge (ESD) protection circuits, disposed inside the peripheral circuit region, wherein each one of the ESD protection circuits is electrically connected to the corresponding switching devices, wherein the ESD protection circuits comprises: a first electrostatic discharge protection circuit, electrically connected to odd numbered gate lines; a second electrostatic discharge protection circuit, electrically connected to even numbered gate lines; a third electrostatic discharge protection circuit electrically connected to odd numbered source lines; and a fourth electrostatic discharge protection circuit, electrically connected to even numbered source lines.