Patent ID: 7391249

Claim:
A multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit, comprising: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode, wherein the feedback circuit comprises: a first inverter for inverting and outputting the signal output from the signal control circuit; a first p-channel metal oxide semiconductor (PMOS) transistor having a source for receiving the signal output from the signal control circuit, a gate for receiving the signal output from the first inverter, and a drain connected to an output; and a first n-channel metal oxide semiconductor (NMOS) transistor having a drain connected to a logic gate of the signal control circuit, a gate for receiving the signal output from the first inverter, and a source connected to ground.