Patent ID: 7501321

Claim:
A process of manufacturing a memory cell array, comprising the steps of: forming a layer of dielectric material on a substrate, forming a first charge storage layer on the dielectric material, forming a second layer of dielectric material on the charge storage layer, forming a first layer of conductive material on the second layer of dielectric material, anisotropically removing portions of the conductive material, the dielectric material, and the charge storage layer to form a select gate and a first group of spaced apart memory cells which are arranged in a row with each of the cells having a memory gate positioned above a charge storage gate, forming an additional layer of dielectric material on exposed portions of the substrate between the cells in the first group and on the side walls of the select gate and the memory gates, depositing a second charge storage layer on the additional layer of dielectric material, depositing a further layer of dielectric material on the second charge storage layer, depositing a second layer of conductive material on the dielectric material on the second charge storage layer, removing portions of the second layer of conductive material and the second charge storage material above the memory cells in the first group to form a second group of memory cells having memory gates and charge storage gates positioned between the memory cells in the first group, forming a bit line diffusion in the substrate next to the select gate at one end of the row, forming a common source diffusion in the substrate at the end of the row opposite the bit line diffusion, and forming a bit line which overlies that row of cells and a bit line contact which interconnects the bit line and the bit line diffusion.