Patent ID: 6903407

Claim:
A dielectric memory cell comprising: a) a substrate comprising a source region, a drain region, and a channel region positioned there between; b) a multilevel charge trapping dielectric positioned on the surface of the substrate; and c) a control gate positioned on the surface of the multilevel charge trapping dielectric and positioned over and aligned with the channel region; and d) wherein the multilevel charge trapping dielectric includes: i) a tunneling dielectric layer adjacent to the substrate comprising a first dielectric material of a tunnel dielectric layer thickness; ii) a top dielectric layer adjacent to the control gate comprising a second dielectric material of a top dielectric thickness which is less than the tunnel dielectric thickness; iii) a charge trapping layer positioned between the tunneling dielectric layer and the top dielectric layer, wherein the control gate has a control gate conduction band Fermi level and a control gate valance band Fermi level; and wherein the difference between the control gate conduction band Fermi Level and a conduction band Fermi level of the top dielectric layer is less than the difference between the control gate valance band Fermi level and a valance band Fermi level of the top dielectric layer.