Patent ID: 7579233

Claim:
A method of fabricating a semiconductor device, comprising the steps of: preparing a semiconductor substrate having buried contact landing pads and direct contact landing pads; forming a lower interlayer insulating layer having direct contact holes that expose the direct contact landing pads on the semiconductor substrate; forming parallel bit line patterns that fill the direct contact holes on the lower interlayer insulating layer; forming a conformal passivation layer on the semiconductor substrate having the bit line patterns; forming a sacrificial insulating layer that fills a space between the bit line patterns on the semiconductor substrate having the passivation layer; forming buried contact holes that expose the buried contact landing pads by sequentially patterning the sacrificial insulating layer, the passivation layer, and the lower interlayer insulating layer; forming insulating spacers that cover side walls of the buried contact holes; forming buried contact plugs that fill the buried contact holes; selectively removing the sacrificial insulating layer; and forming an upper interlayer insulating layer having poor step coverage on the resulting structure from which the sacrificial insulating layer is selectively removed, thereby forming voids between the bit line patterns.