Patent ID: 7642553

Claim:
A thin film transistor array panel, comprising: a substrate including a display region, a chip region, and a pad region; a plurality of signal lines formed on the substrate for electrically connecting the pad region to the chip region and the display region, wherein the signal lines include pad portions located in the pad region; an insulating layer covering the signal lines, the insulating layer including a plurality of contact holes exposing portions of the signal lines; a plurality of contact assistants formed on the insulating layer, wherein the contact assistants are connected to the pads through the contact holes; and a plurality of connection members formed on the insulating layer and being connected to an associated contact assistant for selectively commonly electrically connecting the signal lines, wherein the insulating layer has a boundary line having a first portion which extends beneath the plurality of connection members at a first distance from an edge of the pad region, and at least one second portion adjacent to any outermost one of the plurality of connection members, the at least one second portion being positioned a second lesser distance from the edge of the pad region.