Patent ID: 7817767

Claim:
In a signaling system for transmitting data between a master integrated circuit (IC) device and a slave IC device in which the master and slave IC devices are clocked by reference clocks of the same frequency but arbitrary phase, a method of accounting for drift between the reference clock of the slave device and the reference clock of the master device, the method comprising: performing a digital phase comparison in which the reference clock of the slave device is determined to have a first state or a second state according to whether a first clock signal leads or lags transitions of a data signal, and generating a difference value in response to plural of the digital phase comparisons that indicates a difference between a number of phase error signals having the first state and a number of the phase error signals having the second state; transferring the difference value to a processor in response to at least one enable signal from the processor, the processor including circuitry to fetch programming instructions from program memory and to execute the programming instructions to determine whether the difference value exceeds a first threshold; and outputting an updated phase control value from the processor to adjust the phase of the first clock signal if the difference value exceeds the first threshold; wherein the processor adjusts the phase of the first clock signal at a rate that is slower than a bitrate represented by the data signal.