Patent ID: 8166085

Claim:
A system for calculating a decoded shift amount to reduce latency of a hardware shifter, comprising: at least one hardware sum decoder, wherein the at least one hardware sum decoder gets one of a plurality of bit groups from each of a plurality of input numbers that are distributed over the at least one hardware sum decoder, wherein the plurality of input numbers are partitioned into the plurality of bit groups, and wherein the at least one hardware sum decoder is employed to decode at least one decoded shift amount for one of a plurality of shifter stages; at least one hardware adder, wherein the at least one hardware sum decoder and the at least one hardware adder are coupled in parallel, wherein the at least one hardware adder generates a plurality of group carry signals as a function of a copy of the plurality of bit groups that are conveyed to a carry network; at least one hardware multiplexer coupled to the at least one hardware adder and the at least one hardware sum decoder, wherein the at least one hardware multiplexer corrects the at least one decoded shift amount from the at least one hardware sum decoder as a function of the plurality of group carry signals provided by the at least one hardware adder thereby forming a corrected output signal, wherein the at least one hardware multiplexer rotates the at least one decoded shift amount by one bit; and the hardware shifter coupled to the at least one decoder and the at least one hardware multiplexer, wherein the hardware shifter employs the corrected output signal as a select signal in a set of select signals for one of the plurality of shifter stages in the hardware shifter, wherein the plurality of shifter stages computes a value using the set of select signals thereby reducing the latency of the hardware shifter and wherein the value is used to shift a fraction of an operand by the value so that the operand aligns with a fraction of an intermediate product.