Patent ID: 8019805

Claim:
A floating point multiplier circuit configured for performing extended-precision multiplication of an N-bit multiplicand value by an M-bit multiplier value, wherein N and M are positive integers, said floating point multiplier circuit comprising: partial product generation logic configured to generate a plurality of partial products from said multiplicand value and said multiplier value, wherein said plurality of partial products corresponds to a first portion of said multiplier value during a first partial product execution phase, and wherein said plurality of partial products further corresponds to a second portion of said multiplier value during a second partial product execution phase; a plurality of carry save adders coupled to said partial product generation logic and configured to accumulate said plurality of partial products generated during said first partial product execution phase into a redundant product during a first carry save adder execution phase, and further configured to accumulate said plurality of partial products generated during said second partial product execution phase into said redundant sum during a second carry save adder execution phase; and a first carry propagate adder coupled to said plurality of carry save adders and configured to reduce a first portion of said redundant product to a multiplicative product during a first carry propagate adder phase, and further configured to reduce a second portion of said redundant product to said multiplicative product during a second carry propagate adder phase; wherein said first carry propagate adder phase begins after said second carry save adder execution phase completes.