Patent ID: 7979818

Claim:
A method of validating a design for a packet processing circuit, comprising: inputting from a memory to a processor, a high-level language specification of a first format of an input packet, wherein the specification defines a plurality of fields of the input packet and a respective set of one or more possible values for each of the fields; generating by the processor from the input specification, a plurality of high-level input packets having the first format, wherein each field of each input packet has a value from the respective set; simulating the circuit using a first model of the design on the processor, wherein the first model inputs the high-level input packets and outputs a first plurality of high-level output packets; translating the high-level input packets into a plurality of low-level input packets by the processor; simulating with the processor, the circuit using a second model that inputs the low-level input packets and outputs a plurality of low-level output packets; translating by the processor, the low-level output packets into a second plurality of high-level output packets; comparing by the processor, the first plurality of high-level output packets for equivalence to corresponding expected output packets, and comparing the second plurality of high-level output packets for equivalence to the corresponding expected output packets; and storing by the processor in the memory, data indicative of whether or not the first plurality of high-level output packets is equivalent to the corresponding expected output packets, and whether or not the second plurality of high-level output packets is equivalent to the corresponding expected output packets.