Patent ID: 6877123

Claim:
A scan clock circuit comprising: a clock generator for receiving a reference clock having a first frequency and providing a high frequency operating clock having a second frequency that is higher than the first frequency; and clock control circuitry coupled to the clock generator for receiving the high frequency operating clock, the clock control circuitry comprising: a first storage device for providing a shift/capture clock signal that is in phase with the reference clock by having first predetermined stored bits that are clocked to provide the shift/capture clock signal; a second storage device for providing a launch clock signal for scan testing having a same frequency as the shift/capture clock frequency, the second storage device having second predetermined stored bits that provide a clock pulse so that when a period of the launch clock signal is followed by the shift/capture clock signal, a pulse-to-pulse delay between the launch clock signal and the shift/capture clock signal is equal to a nominal clock period of a predetermined clock domain to permit scan test launching and capturing in a domain-specific at-speed period much shorter than a period of the reference clock; and a third storage device for providing a second launch signal for scan testing in another predetermined clock domain, the third storage device having third predetermined stored bits that provide another clock pulse so that the pulse-to-pulse delay between the second launch signal and the shift/capture clock signal is equal to a corresponding nominal clock period of the another predetermined clock domain.