Patent ID: 7863963

Claim:
A circuit comprising: a first inverter having an input terminal for receiving a first input signal, an output terminal, a first supply terminal, and a second supply terminal; a second inverter having an input terminal for receiving a second input signal, an output terminal, a first supply terminal, and a second supply terminal; a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to the output terminal of the second inverter, and a second current electrode coupled to the first supply terminal of the first inverter; a second transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the output terminal of the first inverter, and a second current electrode coupled to the first supply terminal of the second inverter; a third transistor having a first current electrode coupled to the second supply terminal of the first inverter, a control electrode, and a second current electrode coupled to a second power supply voltage terminal; a fourth transistor having a first current electrode coupled to the second supply terminal of the second inverter, a control electrode, and a second current electrode coupled to the second power supply voltage terminal; and an enabling circuit having a first output terminal coupled to the control electrode of the fourth transistor, a second output terminal coupled to the control electrode of the third transistor, the enabling circuit for controlling the third and fourth transistors to reduce a leakage current in the circuit, wherein the enabling circuit comprises: a first connection for coupling the control electrode of the third transistor to the output terminal of the second inverter; and a second connection for coupling the control electrode of the fourth transistor to the output terminal of the first inverter.