Patent ID: 7667252

Claim:
A semiconductor nonvolatile storage element, which is a ferroelectric nonvolatile storage element comprising: a semiconductor substrate defining a source region, a drain region and a channel region between the source region and the drain region; a first insulator layer extending over the entire channel region; a first conductor layer formed on the first insulator layer and forming a gate over the channel region having a gate length extending in a direction from the source region to the drain region, the first conductor layer having first and second side walls; a second insulator layer formed on the first conductor layer and including a second insulator first portion on the first side wall and a second insulator second portion on the second side wall; a ferroelectric layer formed on the first conductor; a second conductor layer formed on the ferroelectric layer; the channel region, the first insulator layer and the first conductor layer forming a first capacitor which has an electrostatic capacitance C 1 ; the second conductor layer, the ferroelectric layer, and the first conductor layer forming a second capacitor which has an electrostatic capacitance C 2 ; a third conductor layer formed on the source region, and the second insulator first portion being provided between the third conductor layer and the first side wall of the first conductor layer such that the third conductor layer, the second insulator first portion and the first conductor layer form a third capacitor which has an electrostatic capacitance C 3 ; and a fourth conductor layer formed on the drain region, and the third insulator second portion being provided between the fourth conductor layer and the second side wall of the first conductor layer such that the fourth conductor layer, the second insulator second portion and the first conductor layer form a fourth capacitor which has an electrostatic capacitance C 4 , wherein: a composite capacitance CI=C 1 +C 3 +C 4 and a coupling ratio (CI/(CI+C 2 )) is set such that distributed voltage is effectively applied to the second capacitor including the ferroelectric layer; a distance from a bottom face of the first conductor layer to an upper face of the third conductor is greater than one tenth of said gate length; a distance from the bottom face of the first conductor layer to an upper face of the fourth conductor is greater than one tenth of said gate length; the second insulator first and second portions have a thickness in a direction normal the first and second side walls less than one tenth of said gate length; and C MIS equals C 1 , C MIM equals C 3 +C 4 , and (C MIS +C MIM )/C MIS is equal to 2 or greater.