Patent ID: 8345738

Claim:
A multi-phase partial response equalizer circuit, comprising: sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases; a first multiplexer circuit that selects one of the sampled signals as a first sampled bit to represent the input signal; a first storage circuit coupled to an output of the first multiplexer circuit that stores the first sampled bit in response to a first clock signal; a second multiplexer circuit that selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit without storing the first sampled bit in a storage circuit in the path between the output of the first multiplexer circuit and a select input of the second multiplexer circuit; and a second storage circuit that stores a sampled bit selected from the sampled signals in response to a second clock signal, wherein the first multiplexer circuit selects the first sampled bit based on the sampled bit that is transmitted from an output of the second storage circuit to a select input of the first multiplexer circuit, wherein a time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.