Patent ID: 7694176

Claim:
A fault-tolerant computer comprising: duplex systems; each of said duplex systems comprising: a CPU subsystem operable based on a common clock of said duplex systems, for controlling access to a CPU and a storage unit; and an IO subsystem operable either asynchronously or based on a clock of a counter in the IO subsystem, for controlling data which are input to said CPU subsystem from an external circuit and output from said CPU subsystem to the external circuit; said IO subsystem comprising: transmitting means for assigning a transmission time to data to be transmitted to a paired IO subsystem and transmitting the data to the paired IO subsystem; and receiving means for asynchronously receiving data transmitted from the paired IO subsystem and recording a reception time of the received data; wherein a clock shift with respect to the paired IO subsystem is calculated from an ideal reception time calculated using the transmission time assigned to the data to be transmitted and the reception time recorded by said receiving means, the counter in the IO subsystem is changed based on the calculated clock shift, and data is received using the changed counter, wherein said IO subsystem calculates said clock shift with respect to each of data in one cyclic period of at least said counter, and the counter in the IO subsystem is changed to keep the calculated clock shift in a predetermined allowable range, wherein said common clock of said duplex systems is separate from said clock of a counter in the IO subsystem.