Patent ID: 8730249

Claim:
A graphics processor comprising: a multithreaded core array including a plurality of processing clusters; and a crossbar configured to connect the plurality of processing clusters to a frame buffer configured to store data associated with pixels of an image, the frame buffer being partitioned into a plurality of partitions, wherein each processing cluster includes: at least one processing core operable to execute programs; a pixel module configured to receive coverage data and to direct at least one of the processing cores to execute a pixel shader program on the received coverage data to generate pixel values; and a raster operations unit configured to receive the pixel values generated by the at least one processing core included in the same processing cluster as the raster operations unit and to update the pixel data stored in the frame buffer based on the received pixel values, and wherein the raster operations unit of each processing cluster is coupled to the crossbar such that every partition of the frame buffer is accessible to every one of the raster operations units.