Patent ID: 8493813

Claim:
A row decoder circuit, comprising: a decoding unit configured to generate a first driving signal and a second driving signal based on a selection signal and wordline voltages, wherein a voltage level of the first driving signal and a voltage level of the second driving signal depend on an operation mode; a first wordline driving unit connected to a first wordline and configured to output one of the first driving signal and the second driving signal as a first wordline driving signal based on first driving control signals; and a second wordline driving unit connected to a second wordline and configured to output one of the first driving signal and the second driving signal as a second wordline driving signal based on second driving control signals, wherein the first driving control signals each have a voltage level that is lower than the voltage level of the first driving signal or is about the same as the voltage level of the second driving signal depending on whether the first wordline is selected, and the second driving control signals each have a voltage level that is lower than the voltage level of the first driving signal or is about the same as the voltage level of the second driving signal depending on whether the second wordline is selected.