Patent ID: 8021948

Claim:
A method for manufacturing a non-volatile memory device, comprising: providing a substrate comprising a channel between two doped regions; applying a first dielectric on top of said channel, said first dielectric having predetermined properties for functioning as a tunnel dielectric; applying a charge storage layer on top of said tunnel dielectric, said charge storage layer having predetermined properties for enabling storage of charge in said layer and comprising an upper layer containing silicon dioxide; applying a second dielectric, comprising a layer in a siliconoxide consuming material, on top of the upper layer of the charge storage layer on top of said charge storage layer, said second dielectric having predetermined properties for minimizing charge currents through the second dielectric; applying a control gate on top of said second dielectric; and subjecting the device to a post deposition thermal treatment in which a predetermined thermal budget is applied, such that said siliconoxide consuming material consumes at least part of the upper layer of the charge storage layer.