Patent ID: 7911852

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate having a main surface; a first impurity region of a first conductivity type formed at the main surface of said semiconductor substrate; a second impurity region of a second conductivity type located under said first impurity region; a first insulating layer formed on the main surface of said semiconductor substrate and on said first impurity region; a charge-storage insulating layer formed on said first insulating layer; and a gate electrode layer formed on said charge-storage insulating layer; a second insulating layer formed between said charge-storage insulating layer and said gate electrode layer and made of a material having a larger energy bandgap than said charge-storage insulating layer; and a third insulating layer formed between said second insulating layer and said gate electrode layer and made of a material having a smaller energy bandgap than said second insulating layer, said nonvolatile semiconductor memory device being configured to be able to perform an erase operation by applying a forward bias to said first impurity region and said second impurity region to generate a hot carrier and inject the hot carrier into said charge-storage insulating layer.