Patent ID: 7504296

Claim:
A method for fabricating a semiconductor memory device, the method comprising: forming a plurality of gate structures on a substrate; forming a storage node contact junction region extending below an upper surface of the substrate, the storage node contact junction region provided between two adjacent gate structures; forming a trench by etching a portion of the storage node contact junction region, the trench having a given thickness, the trench including: trench sidewalls offset from sides of the two adjacent gate structures such that a first distance between the trench sidewalls is less than a second distance between the two adjacent gate structures, wherein the trench sidewalls extend from the upper surface of the substrate to a bottom surface of the trench contacting the storage node contact junction region; forming a dopant diffusion barrier layer on the trench sidewalls such that the dopant diffusion barrier layer covers the trench sidewalls; and forming a contact plug within a space created between the gate structures and inside of the trench, the contact plug substantially filling the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.