Patent ID: 7663526

Claim:
A circuit comprising: at least one conversion stage having a non-integer N.5 bit resolution, wherein N is greater than or equal to 2, each stage further comprising an amplifier module having at least one active input coupled to at least three capacitor devices; and a plurality of switches coupled to each respective capacitor device; a switch of said plurality of switches coupled to said each capacitor device being also coupled to an output of said amplifier module, such that said each capacitor device can be selectively coupled to said output of said amplifier module; at least one switch of said plurality of switches coupled to said each capacitor device being also coupled to a reference voltage source to receive at least one reference voltage signal; at least one switch of said plurality of switches coupled to said each capacitor device being also coupled to receive an input voltage signal; and a plurality of comparator modules, a state of each comparator module of said plurality of comparator modules defining a plurality of operating regions; wherein said each capacitor device, except one predefined capacitor device, is coupled to said output of said amplifier module in two operating regions of said plurality of operating regions.