Patent ID: 8203877

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells for storing two-or-more-bit data are arranged in a matrix, the plurality of memory cells being connected to a plurality of bit lines and a plurality of word lines; a data memory circuit which is connected to each of the plurality of bit lines and stores data to write to the plurality of memory cells; a voltage generation circuit which generates a write voltage and a step-up voltage to step up the write voltage; and a controller, wherein when data is written to all memory cells connected to selected word lines, the controller performs a write operation with a write voltage obtained by adding the step-up voltage to the write voltage until a write count indicating a number of times by which writing is performed reaches a first write count, and when the first write count is exceeded, the controller controls whether the step-up voltage is to be added or not, for each write operation, and the controller performs a verify operation whether the step-up voltage is added to the write voltage or not.