Patent ID: 7167890

Claim:
A computational random access memory comprising: a memory comprising N columns, N being an integer; and an arithmetic logic unit, in communication with the N columns in the memory, the arithmetic logic unit comprising: M multipliers, M being an integer divisible into N, each of the M multipliers being configured to multiply two N/M-bit numbers; and an adder stage, in communication with the M multipliers to receive outputs of the M multipliers, for forming and outputting calculation results in accordance with the outputs of the M multipliers, wherein the arithmetic logic unit is configured to multiply two N-bit numbers by: (a) multiplying, in the M multipliers, a plurality of combinations of N/M bits of the two N-bit numbers to form a plurality of partial products; and (b) accumulating, in the adder stage, the plurality of partial products to provide a product of the two N-bit numbers, wherein the arithmetic logic unit is configured to add two N-bit numbers by multiplication by one in the multipliers and forming a sum in the adder stage.