Patent ID: 7778105

Claim:
A method of writing to a memory, the method comprising: responsive to a first edge of clock signal, latching first data received from a first data path onto one or more bit lines each coupled between a write data port and a corresponding one of one or more bit cells of a first memory location, wherein each of the one or more bit lines are further coupled between the write data port and a corresponding one of one or more bit cells of a second memory location; subsequent to the first edge, and during a first phase of a cycle of the clock signal, providing a first pulse on a first word line coupled to each of the bit cells of the first memory location, thereby capturing the first data into the first memory location; responsive to a second edge of the clock signal, latching second data received from a second data path onto the one or more bit lines; and subsequent to the second edge and during a second phase of the cycle of the clock signal, providing a second pulse on a second word line coupled to each of the bit cells of the second memory location, thereby capturing the second data into the second memory location.