Patent ID: 6869840

Claim:
A method of fabricating an ESD protection device for an integrate circuit, comprising: forming isolation oxide structure at selected location of a semiconducting surface of a substrate; ion implanting dopant corresponding to a first conductivity type at selected locations of the surface to form wells of the first conductivity type; ion implanting dopant corresponding to a second conductivity type at selected locations of the surface to form wells of the first conductivity type; wherein a selected location of the surface is implanted with dopant of both the first conductivity type and the second conductivity type, to form a compensated well portion of a first well of the first conductivity type having a lower net number of impurities than other wells of the first conductivity type; the method further comprising the steps of: forming doped regions of the first conductivity type at the surface, the doped regions including a first doped region within the first well of the first conductivity type; and forming doped regions of the second conductivity type at the surface, the doped regions including a second doped region within the first well of the first conductivity type, and overlying at least a portion of the compensated well location, wherein one of the steps of forming doped regions forms a ground doped region within a portion of the surface of the second conductivity type, near the well of the first conductivity type; the method further comprising the step of: forming overlying conductors to connect the second doped region to a terminal, and to connect the ground doped region to a device ground region.