Patent ID: 8666735

Claim:
An integrated circuit comprising: A. a processor circuit having an interface for a microphone and an interface for a packet switched network; and B. a memory on said single-chip integrated circuit holding bits defining a process of: i. converting audible speech from the microphone interface into digital data representing the audible speech in each of successive frames, for each frame the converting including forming Linear Prediction Coding data, Long Term Prediction lag data, parity check data, adaptive and fixed codebook gain data, and fixed codebook pulse data; ii. placing the digital data representing the audible speech for the frames into sequential packets, with each packet having a primary stage and a secondary stage, the placing including: a. arranging data from a first frame of speech in the primary stage of a first packet; and b. arranging data from the first frame of speech in the secondary stage of a second packet, which follows immediately after the first packet, the data in the secondary stage including only Linear Prediction Coding data, Long Term Prediction lag data, parity check data, and adaptive and fixed codebook gain data; and C. sending the first and second packets of data sequentially over the packet switched network interface.