Patent ID: 8482323

Claim:
A decoupling circuit comprising: a first inverter that is coupled between a first power supply and a second power supply having a voltage lower than that of the first power supply to be supplied with a power, wherein the first inverter includes: i (i is an integer of 1 or more) first transistor(s) that are coupled between an output end of the first inverter and the first power supply; j (j is an integer of 0 or more) second transistor(s) that are coupled in parallel to the first transistor(s) and have the same conduction type as that of the first transistor(s); m (m is an integer of 1 or more) third transistor(s) that are coupled between the output end of the first inverter and the second power supply and have a conduction type different from that of the first transistor(s); and n (n is an integer of 0 or more) fourth transistor(s) that are coupled in parallel to the third transistor(s) and have the same conduction type as that of the third transistor(s), wherein control terminals of the first to fourth transistor(s) are coupled to an input end of the first inverter, and wherein a total of gate areas of the first transistor(s) and the second transistor(s) is different from a total of gate areas of the third transistor(s) and the fourth transistor(s); and a second inverter that is coupled between the first power supply and the second power supply to be supplied with the power, wherein the second inverter includes: m of the first transistor(s) that are coupled between an output end of the second inverter and the first power supply; n of the second transistor(s) that are coupled in parallel to the first transistors) of the second inverter; i of the third transistor(s) that are coupled between the output end of the second inverter and the second power supply; and j of the fourth transistor(s) that are coupled in parallel to the third transistor(s) of the second inverter, wherein control terminals of the first to fourth transistor(s) in the second inverter are coupled to an input end of the second inverter, and wherein a total of gate areas of the first transistor(s) and the second transistor(s) in the second inverter is different from a total of gate areas of the third transistor(s) and the fourth transistor(s) in the second inverter.