Patent ID: 7433440

Claim:
A jitter-detecting circuit for detecting jitter from a binary-equalizing-data signal including a synchronization clock, said synchronization clock being extracted from said binary-equalizing-data signal by a clock extracting circuit that supplies the synchronization clock as an input to the jitter-detecting circuit, said jitter-detecting circuit comprising: phase-delaying means for delaying a phase of the synchronization clock by a predetermined value to output a phase-delayed clock; flip-flop means for sampling the phase-delayed clock at a leading edge or trailing edge of the binary-equalizing-data signal; average-value-detecting means for detecting and outputting an average value of outputs of the flip-flop means; and control means for controlling any one or a plurality of receiving-sensitivity control parameters in accordance with a jitter value detected from the average value, wherein the jitter-detecting circuit separately receives as input each of the binary-equalizing data signal and the synchronization clock extracted from the binary-equalizing data signal, wherein the phase-delaying means receives the synchronization clock as input and outputs the phase-delayed clock and wherein the flip-flop means separately receives as input each of the phase-delayed clock and the binary-equalizing data signal.