Patent ID: 7764731

Claim:
An equalizer comprising: a low-pass filter for receiving a reception signal; a subtraction unit for subtracting from said reception signal an output signal from said low-pass filter; an addition unit for adding said reception signal to an output signal from said subtraction unit; an amplifier for amplifying an output signal from said addition unit; a bit error rate tester for receiving an output signal from said amplifier to measure a bit error rate of said reception signal, or an eye pattern detector for receiving the output signal from said amplifier to detect an eye pattern of said reception signal, wherein said bit error rate tester or said eye pattern detector transmits a resistance value adjustment signal for adjusting the resistance value of said resistor, said bit error rate tester generates said resistance value adjustment signal so as to minimize said bit error rate, said eye pattern detector generates said resistance value adjustment signal so as to maximize the area of said eye pattern; and a resistor, wherein one end of said resistor is connected to an input end of said amplifier, the other end of said resistor is supplied with a power supply potential, and a resistance value of said resistor is variable, and wherein said low-pass filter includes, a receiving node receiving said reception signal, an output node outputting said output signal, a first transistor coupled between said receiving node and said output node, and a second transistor having a gate connected to said output node, a source being supplied a ground potential, and a drain being supplied said ground potential.