Patent ID: 7856421

Claim:
A system comprising: (A) a first processing node comprising a first wiretap circuitry and a first memory, wherein the first memory comprises a primary portion; (B) a second processing node comprising a second memory, wherein the second memory comprises a replica portion, wherein the second node is coupled to the first node via an interconnect; wherein the first wiretap circuitry is configured to: (C) detect all memory accesses which cause changes to data stored in the primary portion initiated by a processing unit within the first node; and (D) convey a first indication for writing back dirty cache lines within one or more caches within the processing unit to the first memory, wherein one or more of the dirty cache lines correspond to the primary portion, in response to detecting a the memory access corresponding to a checkpoint function; wherein the second node is configured to: (E) store within a replica portion included in the second memory data indicative of said all memory accesses, thereby maintaining an up to date copy of data stored in the primary portion; (F) wherein in response to the second processing node receiving data indicative of the memory access operation to the primary portion, the second node is configured to: modify the replica portion in a manner equivalent to a modification of the primary portion by the memory access operation, thereby maintaining an up to date copy of data stored in the primary portion; and (G) update an undo log in the second memory to reflect said modification to the replica portion; (H) wherein the second node is further configured to utilize the undo log to undo said modification to the replica portion, and (I) wherein the second node is operable to continue execution of a software application corresponding to the primary portion in response to detection of a fault during execution of the software application on the first processing node.