Patent ID: 8566378

Claim:
A sync mark detection circuit, wherein the circuit further comprises: a storage circuit operable to store a data input as a stored input; a plurality of noise predictive filters operable to receive a processing input, wherein at least one of the noise predictive filters is selectably modifiable between increasing the probability of finding a sync mark in the processing input and maintaining a baseline probability of finding the sync mark in the processing input; and a controller circuit, wherein the controller circuit is operable to determine an operational mode selected from a group consisting of: a standard operational mode, a bit flipping mode, and a filter modification mode, and wherein: upon selecting the standard operational mode the controller circuit is further operable to: select the data input as the processing input; and selectably modify the at least one of the noise predictive filters to maintain a baseline probability of finding the sync mark in the processing input; upon selecting the bit flipping mode the controller circuit is further operable to: modify at least one bits in the stored input to yield a modified input; select the modified input as the processing input; and selectably modify the at least one of the noise predictive filters to maintain a baseline probability of finding the sync mark in the processing input; and upon selecting the filter modification mode the controller circuit is further operable to: select the stored input as the processing input; and selectably modify the at least one of the noise predictive filters to increase the probability of finding a sync mark in the processing input.