Patent ID: 8803302

Claim:
A method of packaging a semiconductor device (SD), comprising: (a) placing a first component comprising a die mounted to a first flange on an adhesive substrate with a first surface of the die on the adhesive substrate and with the first flange extending from a second surface of the die opposite the first surface, wherein the die is mounted to the first flange with a die attach material having a melting point in excess of 240° C.; (b) placing a second flange on the adhesive substrate adjacent to but spaced apart from the first component, wherein the die and the second flange have surfaces that are co-planar; (c) electrically interconnecting the die and the second flange; (d) housing at least portions of the flanges by encapsulation to form an assembly surrounding the flanges; (e) adding an additional conductive layer of material to surfaces of the flanges opposite the die to form a termination surface with terminations configured to be surface mounted to a circuit board without leads external to the assembly; and (f) housing the flanges and electrical interconnect such that the packaged SD has a power capacity of greater than about 30 W.