Patent ID: 8775892

Claim:
A system comprising: a plurality of first forward error correction (FEC) code encoders, each of said first FEC code encoders being configured to encode an associated input signal using a first FEC code and provide an associated first FEC code encoded output; an interleaver coupled to said plurality of first FEC code encoders and configured to provide a plurality of interleaved outputs, each of said interleaved outputs comprising at least a portion of said associated first FEC code encoded output of said at least one of said plurality of first FEC code encoders; a second FEC code encoder coupled to said interleaver and configured to encode a first group of said interleaved outputs with a second FEC code and provide an associated plurality of second FEC code encoder outputs; a mapper coupled to said second FEC code encoder and configured to map said plurality second FEC code encoder outputs and a second group of said interleaved outputs to symbols for establishing a mapped output, said second group of interleaved outputs being ones of said plurality of interleaved outputs that are not encoded with said second FEC code; and a modulator coupled to said mapper and configured to modulate an optical signal in response to said mapped output to provide a modulated output signal.