Patent ID: 7898514

Claim:
A liquid crystal display, comprising: a liquid crystal display panel having liquid crystal cells arranged in a matrix defined by data lines and gate lines that cross each other, wherein a thin film transistor is provided in each respective cell adjacent to a crossing of a data line and a gate line for the respective cell; a scanning voltage generator to generate scanning voltages that have different values, wherein the scanning voltages include a gate high voltage that is more than a threshold voltage of the thin film transistor, a plurality of middle voltages that is lower than the gate high voltage, and a gate low voltage that is lower than all the plurality of middle voltages and the threshold voltage of the thin film transistor; a plurality of gate driving integrated circuits to generate scanning pulses using the scanning voltages and to supply the scanning pulse to the gate lines; and a switching circuit to switch the plurality of middle voltages from the scanning voltage generator and to apply the plurality of middle voltages to the plurality of gate driving integrated circuits, respectively; and a line-on-glass-type (hereafter, LOG-type) voltage line provided on a glass substrate of the liquid crystal display panel to apply the scanning voltage to the gate driving integrated circuits, wherein the scanning voltage generator generates the plurality of middle voltages that have different levels according to the plurality of gate driving integrated circuits, respectively, wherein the plurality of middle voltages are set to be different according to line resistance of the LOG-type voltage line connected with the plurality of gate driving integrated circuits, wherein the plurality of middle voltages increase as it increases the line resistance of the LOG-type voltage line for supplying the scanning voltage to each of the gate driving integrated circuits, and wherein the switching circuit divides a period, which is total a scanning time of all the gate lines, into a plurality of times corresponding to the plurality of gate driving integrated circuits, respectively, and supplies each middle voltage to the each gate driving integrated circuit during each time, which is a driving time of the each gate driving integrated circuit.