Patent ID: 7907465

Claim:
A programmable read only memory circuit configured to be a part of a multi-bit memory block, the memory circuit comprising: a single-bit core memory cell comprising at least a select device, a high-voltage protection device, and a fuse device in series, wherein data is programmed in the cell through permanently altering at least one physical characteristic of the fuse device by turning on the select device and applying a controlled high voltage to the gate of the fuse device for a predetermined period of time; a single-bit latch for latching an output of the single-bit core memory cell or an externally provided data bit; a set and a reset input line for controlling the single-bit latch content; a block-select input line for selecting a memory block among a plurality of memory blocks; multiple address input lines for selecting a memory circuit among a plurality of memory circuits of a memory block; and a programming input line for enabling programming of memory circuits of a selected memory block.