Patent ID: 7919376

Claim:
A method for manufacturing a CMOS transistor, comprising: preparing a silicon substrate provided with a first buried layer, a second buried layer and a body; selectively implanting a first conductive-type impurity into the body, and vertically diffusing the impurity into the first buried layer to form a first diffusion region; selectively implanting a second conductive-type impurity into the body, and vertically diffusing the impurity into the second buried layer to form a second diffusion region; vertically forming device-isolation films inside the body; forming a first-type well inside the body arranged over the first buried layer, and vertically forming a first source and drain region inside the first-type well; forming a second-type well inside the body arranged over the second buried layer, and vertically forming a second source and drain region inside the second-type well; and vertically forming a recessed gate between the first-type well and the second-type well.