Patent ID: 6954866

Claim:
A system for smoothing current consumption in a digital logic module comprising: a processing circuit configured to receive an input and manipulate the input; a counter coupled to the processing circuit and configured to track a processing time period during which the processing circuit manipulates the input in order to create an output wherein the counter is further configured to generate a last-cycle signal indicating the end of the processing time period, the last-cycle signal and the start signal combining to form a store signal; an output port coupled to the processing circuit and configured to convey the output while the processing circuit continues to operate during a non-processing time period, wherein the processing time period is followed by the non-processing time period, which ends as soon as a new processing time period begins; a start line coupled to the counter and configured to convey a start signal to the counter when the input is available to the processing circuit, wherein the start signal triggers the beginning of the processing time period; and an interrupt line coupled to the counter and configured to convey an interrupt signal from the counter when the output is available at the output port, wherein the interrupt signal coincides with the end of the processing time period and the beginning of the non-processing time period; and a storage circuit coupled to the output port and configured to store the output upon receipt of the store signal, and during the non-processing time period transmit the output to the output port.