Patent ID: 8207926

Claim:
A liquid crystal display device comprising a plurality of pixels that are arranged in columns and rows so as to form a matrix pattern, each said pixel including a liquid crystal layer and a plurality of electrodes for applying a voltage across the liquid crystal layer, wherein each said pixel includes a first subpixel SP 1 and a second subpixel SP 2 , having liquid crystal layers to which mutually different voltages are applicable in displaying a certain grayscale, and wherein each of the first and second subpixels SP 1 and SP 2 includes a liquid crystal capacitor formed by a counter electrode and a subpixel electrode that faces the counter electrode through the liquid crystal layer, and a storage capacitor formed by a storage capacitor electrode that is electrically connected to the subpixel electrode, an insulating layer, and a storage capacitor counter electrode that is opposed to the storage capacitor electrode with the insulating layer interposed between them, and wherein the counter electrode is a single electrode provided in common for the first and second subpixels SP 1 and SP 2 , while the storage capacitor counter electrodes of the first and second subpixels SP 1 and SP 2 are electrically independent of each other, and wherein every vertical scanning period V-Total of an input video signal, a common display signal voltage is applied to the respective subpixel electrodes of the first and second subpixels SP 1 and SP 2 , and storage capacitor counter voltages applied independently to the storage capacitor counter electrodes of the first and second subpixels SP 1 and SP 2 are varied within each said vertical scanning period of the input video signal, whereby each said vertical scanning period V-Total of the input video signal includes a first subframe SFA in which the first and second subpixels SP 1 and SP 2 have luminances Y_SP 1 _A and Y_SP 2 _A, respectively, and a second subframe SFB in which the first and second subpixels SP 1 and SP 2 have luminances Y_SP 1 _B and Y_SP 2 _B, respectively, where Y_SP 1 _A≠Y_SP 2 _A, Y_SP 1 _B≠Y_SP 2 _B, and Y_SP 1 _A≠Y_SP 1 _B or Y_SP 2 _A≠Y_SP 2 _B are satisfied, wherein the storage capacitor counter voltages are oscillating voltages, and wherein the storage capacitor counter voltages applied to the storage capacitor counter electrode of the first subpixel in the first and second subframes SFA and SFB of a vertical scanning period V-Total of the input video signal have mutually different amplitudes.