Patent ID: 7028163

Claim:
A digital data processor, comprising: a stack storage including a plurality of locations, wherein each of the locations of said stack storage are assigned to one of a first bank and a second bank; a main stack pointer for pointing to a top location of said stack storage; a first bank stack pointer for pointing to a location assigned to said first bank; a second bank stack pointer for pointing to a location assigned to said second bank; an instruction decoder for decoding a stack-based instruction and generating a plurality of decoding signals, each of the plurality of decoding signals denoting one of a one-word push operation, a one-word pop operation, a two-word push operation and a two-word pop operation; and a stack pointer control logic circuit for controlling said first and second bank stack pointers in response to at least one of the decoding signals to insert bank address data into the first and second bank stack pointers based on the content of the main stack pointer to perform a multi-word push or multi-word pop operation, wherein said stack pointer control logic circuit includes: an adder for adding one of plurality of predetermined integers to a content of said main stack pointer in response to a first decoding signal from said instruction decoder; a first selector for selecting for output one of the content of the main stack pointer and a content of said adder in response to a second decoding signal from said instruction decoder, wherein the output of said first selector comprises a high-order bit portion and a low-order bit portion; a first control logic for generating a first control signal in response to the low-order bit portion of the output from said first selector and a third decoding signal from said instruction decoder; a second control logic for generating a second control signal in response to the low-order bit portion of the output from said first selector and a fourth decoding signal from said instruction decoder; an increment logic for incrementing the high-order bit portion of the output from said first selector; a second selector for selecting one of the high-order bit portion of the output from said first selector and the output of said increment logic in response to the first control signal; end a third selector for selecting one of the high-order bit portion of the output from said first selector and the output of said increment logic in response to the second control signal; wherein the outputs of said second and third selectors are provided to said second and first bank stack pointers, respectively.