Patent ID: 7217643

Claim:
A process for fabricating a transistor, the process comprising: depositing a first amorphous dielectric layer overlying a substrate, said first amorphous dielectric layer comprising Hf X Zr i-X O 2 , wherein 0≦X≦1; forming an amorphous interlayer overlying said first amorphous dielectric layer, said amorphous interlayer having a net dielectric constant approximately no less than the dielectric constant of HfZrO 4 , wherein said amorphous interlayer is formed such that a chemical composition at a first surface of said amorphous interlayer is different from a chemical composition at a second surface of said amorphous interlayer; depositing a second amorphous dielectric layer overlying said amorphous interlayer to form a stacked dielectric structure, said second amorphous dielectric layer comprising HfZr 1-Y O 2 , where 0≦Y≦1, wherein the stacked dielectric structure has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO 4 ; forming a source region within said substrate; and forming a drain region within said substrate.