Patent ID: 7502969

Claim:
A method, comprising: operating a second hardware representation of a digital circuit design in a time-delayed manner with respect to a first hardware representation of said digital circuit design, wherein said digital circuit design comprises a first design portion to be operated with a first design clock signal and a second design portion to be operated with a second design clock signal other than said first design clock signal; upon occurrence of a predetermined abort state in said first hardware representation, analyzing an operational behavior of said digital circuit design on the basis of a state of said second hardware representation by simulating an operation of said digital circuit design on the basis of said delayed state of said second hardware representation using a simulation model of said digital circuit design; and generating a reference clock signal having a frequency that is at least twice the frequency of a higher one of the first and second design clock signals, which is used to correlate the time-shifted operation, and correlating said time-shifted operation of said first and second hardware representations with said reference clock signal.