Patent ID: 7173472

Claim:
An input buffer for interfacing a high voltage input signal received at an input node to a low voltage circuit comprising low voltage devices, the input buffer comprising: a threshold adjustment circuit comprising an inverter coupled to a threshold adjusted output node, said inverter comprising low voltage devices and coupled between a high voltage supply node and a ground node, said inverter comprising a first and second transistors having biasing nodes coupled to a low voltage supply node of said low voltage circuit and coupled to said threshold adjusted output node, said threshold adjustment circuit providing at said threshold adjusted output node an inverted signal of said high voltage input signal; and a level shifting circuit comprising low voltage devices and coupled to said threshold adjusted output node, said level shifting circuit providing a low voltage signal corresponding to said high voltage input signal in response to said inverted signal, wherein said level shifting circuit comprises a level shift circuit inverter coupled to said threshold adjusted output node through a pass gate transistor, wherein said level shifting circuit inverter comprises a p-channel and n-channel transistor pair having respective biasing nodes coupled to said threshold adjusted output node through said pass gate transistor, said level shifting circuit further comprising a p-channel transistor coupled in a stack with the p-channel transistor of said p-channel and n-channel transistor pair and having a biasing node coupled to said threshold adjusted output node.