Patent ID: 6879277

Claim:
An analog to digital conversion system, comprising: a plurality of cascaded successive approximation register subconverter stages, the subconverter stages individually comprising: a switched capacitor system receiving an analog subconverter stage input voltage at a switched capacitor system input node and an intermediate digital signal, the switched capacitor system providing an analog switched capacitor system output signal at a switched capacitor system output node, wherein the switched capacitor system comprises: a plurality of capacitors, individual capacitors comprising a first terminal coupled to a switched capacitor system intermediate node, and a second terminal; and a switching system coupled to the second terminals of the plurality of capacitors, the switching system selectively coupling individual capacitors to one of the switched capacitor system input node, the switched capacitor system output node, a first reference voltage, and a second reference voltage; wherein in a sample mode, the switched capacitor system stores the subconverter stage input voltage in the plurality of capacitors; wherein in a conversion mode, the switched capacitor system applies the intermediate digital signal to the plurality of capacitors and provides the switched capacitor system output signal representative of a difference between the subconverter stage input voltage and a value of the intermediate digital signal; and wherein in a residue amplification mode, the switched capacitor system provides the switched capacitor system output signal representative of a difference between the subconverter stage input voltage and a final value of the intermediate digital signal.