Patent ID: 7159047

Claim:
A circuit comprising: a plurality of processing blocks on a first chip; and an interconnect network comprising a plurality of network nodes arranged in a two-dimensional array on said first chip, each network node having a plurality of adjacent network nodes and being connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that bus; each network node comprising: a plurality of communication ports, each communication port comprising an input port for receiving digital signals and an output port for transmitting digital signals on a bus connected to that communication port; a programmable switch that selectively connects one of said input ports to one of said output ports in response to connection information stored in a memory in that network node, wherein; each processing block is connected to one of said communication buses and sends and/or receives data on that bus, each processing block performing a predetermined processing function, said processing block being located within said two-dimensional array of network nodes.