Patent ID: 7098096

Claim:
A method of fabricating a multi-bit flash memory, comprising: providing a substrate; forming a tunneling oxide layer on the substrate; forming a conductive layer on the tunneling oxide layer; forming an isolation layer in the conductive layer to partition the conductive layer into more than two conductive blocks arranged in an array with a plurality of rows extending from a region predetermined for forming one bit line to another region predetermined for forming another bit line and a plurality of columns, wherein each row comprises tow conductive blocks, and each column comprises more than two conductive blocks, wherein the step of forming the isolation region further comprises: forming a patterned photoresist layer on the conductive layer to expose a part of the conductive layer predetermined for forming the isolation region; performing an ion implantation step to implant dopant into the exposed conductive layer; and performing an annealing process to react the dopant with the silicon of the conductive layer to form the isolation region; forming a gate dielectric layer on the conductive layer; patterning the gate dielectric layer and the conductive layer to form a floating gate comprising a predetermined number of conductive blocks arranged in an array having pluralities of rows and columns, wherein each row comprises a plurality of conductive blocks and each column comprises a plurality of conductive blocks, and wherein the patterned gate dielectric layer is formed vertically above the predetermined number of blocks arranged in the array; forming the bit lines in the substrate at two sides of the floating gate; forming a control gate on the floating gate so that each multi-bit cell of the multi-bit flash memory comprises said control gate, said patterned gate dielectric layer and said floating gate comprising said plurality of conductive blocks arranged in said array; and performing a step of threshold voltage adjustment to result in different threshold voltages of the channel regions under the conductive blocks of different rows.