Patent ID: 7367005

Claim:
A layout designing apparatus comprising: a net-list input unit that receives an input of an arbitrary net list: an arranging unit that arranges a cell obtained from the arbitrary net list; a net extracting unit that extracts an arbitrary net from the cells arranged; a storing unit that stores correlation information indicating a correlation between first information and second information, the first information being on a driving capacity of each of cells included in a circuit model that is created based on a delay time caused by a crosstalk occurred as a result of a circuit simulation for a predetermined circuit model, the second information being on a wire length of a wiring that connects the cells in the circuit model; a detecting unit that detects whether the delay-time suppressing cell is included in the arbitrary net in advance; a deleting unit that deletes, when the detecting unit detects that the delay-time suppressing cell is included in the arbitrary net, the delay-time suppressing cell from the arbitrary net; an information extracting unit that extracts, based on the correlation information stored in the storing unit, the first wire-length information or the second wire-length information for the arbitrary net; a calculating unit that calculates third wire-length information between a driver cell and a receiver cell that are included in the arbitrary net; a determining unit that determines, based on the first wire-length information and the second wire-length information, whether the crosstalk occurs in the arbitrary net; and an inserting unit that inserts, based on a result of determination by the determining unit, a delay-time suppressing cell to suppress a delay time in the arbitrary net.