Patent ID: 8860329

Claim:
A control circuit arranged to generate a control signal (Vc) for controlling at least one transistor of a switched mode power supply (SMPS) during first, second and third successive time periods (t 1 , t 2 , t 3 ) based on a feedback voltage (VF), wherein during the first and third time periods the control circuit is adapted to regulate the output voltage of the SMPS to a first voltage level, and during the second time period the control circuit is adapted to control the SMPS to output a low voltage (VL), the control circuit comprising: a memory adapted to store an indication (dL(n)) of the control signal generated by the control circuit at the end of the first time period (t 1 ); a digital controller adapted to output on successive cycles digital values (d(n)), wherein the digital controller comprises a further memory arranged to store an indication (Ve L (n)) of the feedback voltage at the end of the first time period; and a digital pulse width modulation (DPWM) block arranged to receive the digital values (d(n)) from the digital controller and to generate said control signal based on said digital values, wherein the control circuit is adapted to output a control signal based on said stored indication of the control signal for N cycles of the digital controller at the start of the third time period until said feedback voltage reaches a determined value.