Patent ID: 8898408

Claim:
A method of memory controller-independent memory mirroring in an information handling system (IHS), comprising: providing a mirroring association between a first memory segment and a second memory segment that are located in a system memory and that are coupled to a memory buffer, wherein the mirroring association is independent of a memory controller that is associated with the system memory and the second memory segment is unknown to the memory controller; receiving, by the memory buffer from the memory controller, write data that is directed to a first memory location in the first memory segment; writing, independent of the memory controller with the memory buffer, the write data to both the first memory segment and the second memory segment according to the mirroring association such that the first memory segment includes primary write data and the second memory segment includes mirrored write data that is a copy of the primary write data; receiving, by the memory buffer from the memory controller, a plurality of read commands directed to the first memory location in the first memory segment, and, in response: retrieving read data by reading the write data from an alternating one of the first memory segment and the second memory segment in response to the plurality of read commands; and storing the read data in the memory buffer such that the memory buffer includes both first read data that is the primary write data that was read from the first memory segment in response to the plurality of read commands and second read data that is the mirrored write data that was read from the second memory segment in response to the plurality of read commands; and performing, by the memory controller without knowledge of the mirroring association between the first memory segment and the second memory segment, a patrol scrubbing process using the first read data and the second read data in the memory buffer such that each of a plurality of addresses in both the first memory segment and the second memory segment are subject to the patrol scrubbing process over the plurality of read commands, wherein a patrol scrub rate is set in the memory controller such that each of the plurality of addresses in both the first memory segment and the second memory segment are subject to the patrol scrubbing process over the plurality of read commands within a predetermined amount of time.