Patent ID: 8904154

Claim:
A processing method comprising: processing instructions for tasks at each of a plurality of processing circuit elements of a multiple processor system, the instructions including memory access instructions for accessing a memory having a plurality of disjoint regions, each region corresponding to a different processing circuit element of the plurality of processing circuit elements and corresponding to a different range of memory addresses of the memory, wherein the processing includes, processing instructions for a first task by a first processing circuit element of the plurality of processing circuit elements, including processing memory access instructions, each memory access instruction for accessing data stored at a memory address in the memory, wherein at least some of the memory access instructions reference memory addresses in memory regions having a range of memory addresses other than the range of memory addresses corresponding to the first processing circuit element and at least some of the memory access instructions reference memory addresses in a memory region having a range of memory addresses corresponding to the first processing circuit element, determining, by a memory access circuit of the first processing circuit element, a locus of execution of each of the memory access instructions before issuing the memory access instruction, the determining including, for each memory access instruction, comparing the memory address of the data accessed by the memory access instruction to the range of memory addresses corresponding to the region of the memory corresponding to the first processing circuit element, and for at least some of the memory access instructions determined to have a locus of execution other than the first processing circuit element, transferring a locus of execution of the first task from the first processing circuit element to a different processing circuit element associated with the determined locus of execution.