Patent ID: 7609539

Claim:
A nonvolatile programmable read only memory cell with continuously available data content without decoding or addressing, the memory cell comprising: a select transistor having a source, a drain, and a gate, wherein the source or the drain of the select transistor is connected to a first voltage and the other of the source and the drain forms a first connection point; and a fuse transistor having a source, a drain, and a gate, wherein: the source, the drain, or the source and the drain of the fuse transistor forms a second connection point, wherein the second connection point is an output port of the memory cell; the first and the second connection points are electrically connected; and data of certain logic level is programmed in the cell through permanently altering at least one physical characteristic of the fuse transistor by turning on the select transistor and applying a controlled high voltage to the gate of the fuse transistor for a predetermined period of time, wherein in CMOS implementation of the memory cell, the fuse and the select transistors are “Native.”