Patent ID: 8193572

Claim:
An electronic device comprising: a substrate including a portion that defines a first trench having a first bottom, a first wall, and a second wall opposite the first wall; a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench; a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench, wherein the first gate electrode lies between the first wall and the second gate electrode; a first set of discontinuous storage elements, wherein the first set of discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench; a third gate electrode within the first trench and adjacent to the second wall and overlying the first bottom of the first trench; a fourth gate electrode within the first trench and adjacent to the third gate electrode and overlying the first bottom of the first trench, wherein the third gate electrode being between the second wall and the fourth gate electrode; a second set of discontinuous storage elements, wherein the second set of discontinuous storage elements lies between (i) the third gate electrode or the fourth gate electrode and (ii) the first bottom of the first trench; and wherein a first memory cell comprises the first gate electrode, the second gate electrode, and the first set of discontinuous storage elements; a second memory cell comprises the third gate electrode, the fourth gate electrode, and the second set of discontinuous storage element; and the second gate electrode being between the first gate electrode and the fourth gate electrode.