Patent ID: 8140739

Claim:
A storage device comprising: flash memory; a host interface for communicating with a host device; a processor that receives commands from the host device via the host interface and coordinates at least one of addressing, programming, erasing and reading of data to or from the flash memory; a buffer electrically connected between the host interface and the flash memory; and a high write volume magnetoresistive random access memory (MRAM) electrically connected between the host interface and a flash controller, wherein the processor compares a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table, causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table and a size of the data file is less than or equal to an available space in the high write volume MRAM, and causes the data file to be written to the flash memory when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table and the size of the data file is greater than the available space in the high write volume MRAM memory.