Patent ID: 8461905

Claim:
An adaptive switch circuit using voltage sources VDD and VSS, the adaptive switch circuit comprising: a CMOS switch comprising a first PMOS transistor coupled to a first NMOS transistor, the CMOS switch further comprising a PMOS gate, an NMOS gate, an input Vin and an output Vout; an off-level voltage generator providing, via a first output, a first voltage level and, via a second output, a second voltage level, the off-level voltage generator comprising a second PMOS transistor and a second NMOS transistor, the second PMOS transistor being series connected between VDD and a first bias source and the second NMOS transistor being series connected between VSS and a second bias source, the first output being from a node between the series connected second PMOS transistor and first bias source and the second output being from a node between the series connected second NMOS transistor and the second bias source; a booster circuit coupled to the off-level voltage generator, between the first output and the second output thereof, and coupled to the PMOS gate and to the NMOS gate of the CMOS switch for facilitating gating of the CMOS switch, the booster circuit capacitively storing during off level a first boost voltage and a second boost voltage, the first boost voltage being coupled to the PMOS gate and the second boost voltage being coupled to the NMOS gate, and the first boost voltage and the second boost voltage being offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type, and each providing a capacitive boosting of the gate voltage at the respective PMOS gate or NMOS gate of the CMOS switch by the threshold voltage of the corresponding transistor type.