Patent ID: 6954510

Claim:
A phase-locked loop (PLL) lock detector circuit for detecting a lock or unlock state of a PLL circuit, the PLL lock detector circuit comprising: a synchronization circuit for synchronizing a lock window signal with a reference frequency signal, the lock window signal resulting from dividing the reference frequency signal by a predetermined number; a rising edge detection circuit for receiving an output signal of the synchronization circuit and an error signal, and for outputting a state of the error signal at a rising edge of the output signal of the synchronization circuit, the error signal indicating a phase difference between the lock window signal and a signal resulting from dividing an output signal of the PLL circuit by a predefined number; a falling edge detection circuit for receiving the error signal and an inverted lock window signal and for outputting a state of the error signal at a rising edge of the inverted lock window signal; and a logic circuit for performing an AND operation on the output signal of the rising edge detection circuit and the output signal of the falling edge detection circuit, and for outputting a signal indicating the lock or unlock state of the PLL circuit.