Patent ID: 7130953

Claim:
In a system on a chip (SOC) comprising a system bus with a first complexity, apparatus for enabling communication among a plurality of devices comprising: at least a first device; at least a second device; and a bus interface directly connected to the system bus, coupled to the first device through a first bus with a second complexity less than the first complexity and coupled to the second device through a second bus with a third complexity less than the first complexity, the bus interface comprising a third bus, a fourth bus, a fifth bus, a first bridge coupled to the second device over the second bus and coupled to the system bus over the third bus with a fourth complexity less than the first complexity, and a second bridge coupled to the first device over the first bus, coupled to the first bridge over a the fourth bus with a fifth complexity less than the first complexity and coupled to the system bus over the fifth bus with a sixth complexity less than the first complexity, wherein the system bus does not need a back off or retry mechanism to resolve conflicts, and wherein the first device, the second device, the bus interface and the system bus are integrated onto a single chip.