Patent ID: 8114750

Claim:
A method manufacturing a semiconductor structure comprising: forming a gate dielectric and a gate electrode on a semiconductor substrate including a substrate semiconductor region having a doping of a first conductivity type, wherein said gate dielectric contacts said substrate semiconductor region; forming a drift region having a doping of a second conductivity type on a drain side of said gate electrode by implanting dopants of said second conductivity type into a portion of said substrate semiconductor region, wherein said second conductivity type is the opposite of said first conductivity type; forming a first gate spacer on sidewalls of said gate electrode, wherein said first gate spacer is not present above said gate electrode; forming a second gate spacer laterally surrounding said first gate spacer on said first gate spacer and on a surface of said drift region; removing a first portion of said second gate spacer on a source side of said gate electrode; forming a source region having a doping of said second conductivity type in said remaining substrate semiconductor region within said semiconductor substrate on said source side of said gate electrode after removal of said first portion of said second gate spacer; forming a drain region having a doping of said second conductivity type within said drift region in said semiconductor substrate on said drain side of said gate electrode, wherein said drain region is spaced from said remaining substrate semiconductor region; and removing a second portion of said second gate spacer on said drain side of said gate electrode after formation of said drain region.