Patent ID: 7648879

Claim:
A method of fabricating a power transistor comprising: forming an epitaxial layer on a semiconductor substrate, the epitaxial layer and the semiconductor substrate being of a first conductivity type, the epitaxial layer being formed with first and second sections having respective first and second doping concentration gradients that differ by at least 10%, the first and second sections being formed below an upper surface of the epitaxial layer, the first section being formed above the second section, doping concentration in each of the first and second sections increasing with distance from the upper surface; forming first and second trenches in the epitaxial layer that extend vertically from the upper surface down into the substrate to define a mesa having first and second sidewalls, the first and second sections comprising a drift region of the mesa; forming a dielectric layer over the first and second sidewalls; forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from the first section of the drift region; and forming a gate embedded within the dielectric layer adjacent the body region.