Patent ID: 8181003

Claim:
A method of clock cycle synchronized flexible programmable execution of a data processing program, the method comprising: providing a processor containing a plurality of functional units, each functional unit being a computation unit, memory unit, full access switch unit for interconnecting execution units with memory units, or a control unit, each functional unit having its own program counter, its own instruction fetch and decode unit, and its own dedicated local program memory for storing instructions that control the functional unit during program execution; dividing the data processing program into one or more data processing modules; connecting different functional units to form predetermined control paths and data pipelines in a hierarchical manner; using a common instruction set to program at least some of the functional units, wherein the instruction set directly codes instruction sequencing and directly or indirectly codes hardware controls; setting up distributed program sequencing in the dedicated local program memories of each of the programmed functional units, the dedicated local program memory in each programmed functional unit being loaded before execution of each processing module with all instructions required during execution of that processing module; generating control vectors that control the control paths and data pipelines of said functional units every clock cycle; configuring multiple memory units to operate in different memory access modes and connecting them to the computation units through said switch units to maximize programmability; and executing the processing modules.