Patent ID: 7187209

Claim:
A non-inverting domino register, comprising: a domino stage for evaluating a logic function based on at least one input data signal and a clock signal, wherein said domino stage pre-charges a pre-charged node high when said clock signal is low, pulls said pre-charged node low if it evaluates, and keeps said pre-charged node high if it fails to evaluate; a write stage, coupled to said domino stage and responsive to said clock signal, which pulls a first preliminary output node high if said pre-charged node goes low and which pulls said first preliminary output node low if said pre-charged node stays high; an inverter having an input coupled to said first preliminary output node and an output coupled to a second preliminary output node; a high keeper path which keeps said first preliminary output node high when enabled, wherein said higher keeper path is enabled when said clock signal and said second preliminary output node are both low and which is otherwise disabled; a low keeper path which keeps said first preliminary output node low when enabled, wherein said low keeper path is enabled when said second preliminary output node and said pre-charged node are both high and which is otherwise disabled; and an output stage which provides an output signal based on states of said pre-charged node and said second preliminary output node.