Patent ID: 7640414

Claim:
A processor comprising: a decoder operable to decode an instruction; a plurality of execution units operable to respectively execute a decoded instruction from the decoder, the plurality of execution units including, a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations; a store queue operable to buffer one or more store memory operations prior to the one or more memory operations being completed, the store queue operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis; a data cache; and one or more data selection multiplexers operable to be controlled to provide data stored in the data cache along with store data of one or more store memory operations buffered in the store queue responsive to a load memory operation on a byte-by-byte basis such that at least one byte for the load memory operation is provided from at least one store memory operation buffered in the store queue and at least one other byte for the same load memory operation is provided simultaneously from the data cache.