Patent ID: 7561461

Claim:
A non-volatile semiconductor memory device comprising: a cross-point cell array; a plurality of word lines extended in a first direction; a plurality of bit lines extended in a second direction different from the first direction; a first decoding circuit for selecting a selected word line from the plurality of word lines; a second decoding circuit for selecting a selected bit line from the plurality of bit lines; a first reference signal generating circuit for generating a first reference signal; a second reference signal generating circuit for generating a second reference signal different from the first reference signal; and a read circuit, wherein the cross-point cell array includes a plurality of cells, each of the plurality of cells is interposed between one of the plurality of word lines and one of the plurality of bit lines, a selected cell is interposed between the selected word line and the selected bit line, based on a detection signal corresponding to a detection current which is caused to flow through the selected bit line by applying a voltage between the selected word line and the selected bit line, the read circuit compares a first difference signal corresponding to a difference between the detection signal and the first reference signal with a second difference signal corresponding to a difference between the detection signal and the second reference signal, thereby determining data stored in the selected cell.