Patent ID: 7895489

Claim:
A system comprising: an automatic test engine operable to output a test output, to receive a resultant input, to receive a debug input, to monitor the debug input and to compare the test output with the resultant input; a decompressor arranged to receive a decompressor input based on the test output, to output a first decompressor output and to output a second decompressor output; a first scan chain arranged to receive a first scan chain input based on the first decompressor output, said first scan chain comprising a first flip-flop and a second flip-flop, said first flip-flop being arranged to receive a first flip-flop input based on the first scan chain input and to generate a first flip-flop output, said second flip-flop being arranged to receive a second flip-flop input based on the first flip-flop output and to generate a second flip-flop output; a second scan chain arranged to receive a second scan chain input based on the second decompressor output, said second scan chain comprising a third flip-flop and a fourth flip-flop, said third flip-flop being arranged to receive a third flip-flop input based on the second scan chain input and to generate a third flip-flop output, said fourth flip-flop being arranged to receive a fourth flip-flop input based on the third flip-flop output and to generate a fourth flip-flop output; a compactor arranged to receive a first compactor input based on second flip-flop output, to receive a second compactor input based on the fourth flip-flop output and to output a compactor output; and a debug output line arranged to receive the second flip-flop output, wherein the resultant input is based on the compactor output, and wherein said second flip-flop is arranged to additionally receive the fourth flip-flop output.