Patent ID: 7432734

Claim:
A programmable logic device, comprising: a plurality of logic array blocks arranged in an array, one of the logic array blocks in the array including: a first subset of a plurality of routing lines, each of the first subset of the plurality of routing lines coupled to a first subset of a plurality of input pins of a logic element to produce at least one connection on each one of the first subset of the plurality of routing lines; and a second subset of the plurality of routing lines, each of the second subset of the plurality of routing lines coupled to a second subset of the plurality of input pins of the logic element to produce at least one connection on each one of the second subset of the plurality of routing lines; wherein the at least one connection of each of the first subset of the plurality of routing lines is distinct from connections of other ones of the first subset of the plurality of routing lines and connections of the first subset of the plurality of routing lines together provide connections to all of the plurality of input pins, and the at least one connection of each of the second subset of the plurality of routing lines is distinct from the at least one connection of each of the first subset of the plurality of routing lines.