Patent ID: 8704288

Claim:
A memory device comprising: a substrate extending in a horizontal direction; a plurality of insulation layers on the substrate; a plurality of conductive patterns, each of at least two of the conductive patterns between a neighboring lower insulation layer and a neighboring upper insulation layer; a plurality of vertical channels of semiconductor material extending in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels; the at least two of the conductive patterns having a conductive contact region, conductive contact regions of the at least two of the conductive patterns being in a stepped configuration so that a contact region of a neighboring lower conductive pattern extends in the horizontal direction beyond a contact region of a neighboring upper conductive pattern; and an etch stop layer on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.