Patent ID: 7169661

Claim:
A process of fabricating a high resistance CMOS resistor, comprising the steps of: providing a p-type silicon substrate; forming an n-well in said p-type silicon substrate; forming a p-well in a non-active area of said p-type silicon substrate; forming a pad oxide layer on the surface of said p-type silicon substrate; forming a first p-field region into said p-well and a second p-field region into said n-well, wherein said second p-field region forms a CMOS resistor; forming a field oxide layer over said CMOS resistor; forming an n-type contact region in said n-well; forming two p-type contact regions respectively as a first ohmic contact and a second ohmic contact of said CMOS resistor respectively; forming a patterned BPSG layer to build two contact openings exposing a portion of said n-type contact region and said two p-type contact regions; forming two metal contact plugs in said contact openings to electrically connect to said first ohmic contact and said second ohmic contact of said CMOS resistor, and depositing a passivation layer over said contact plugs covering said CMOS resistor.