Patent ID: 8604858

Claim:
A gate driving circuit, comprising: a first clock generator to output n (n being a natural number equal to or greater than 2) output control clock pulses having different phases; a second clock generator to create m*n (m being a natural number) output clock pulses having different phases and partially overlapped with one another in high periods thereof, to arrange the m*n output clock pulses in sequence of phase, to bind the m*n output clock pulses arranged in sequence of phase in units of n to generate m groups, each of which has n output clock pulses, and to output the m*n output clock pulses so that a rising edge of an output clock pulse having a k-th sequence of phase included in each group is located in a high period of an output control clock pulse having a k-th sequence of phase among the n output control clock pulses; and a shift register to receive the n output control clock pulses from the first clock generator and the m*n output clock pulses from the second clock generator and to sequentially output a plurality of scan pulses, wherein the n output control clock pulses and the m*n output clock pulses each comprise a plurality of impulses which is periodically generated, and wherein a rising edge of an impulse included in an output clock pulse having a k-th sequence of phase and belonging to a j-th (j is natural number equal to or less than m) group is located in a high period of an impulse having a k-th sequence of phase.