Patent ID: 6968306

Claim:
A computer implemented method for utilizing a signal delay model for determining an interconnect delay at a node in an interconnect modeled as a resistive-capacitive (RC) tree having a plurality of nodes, said method comprising: determining an equivalent effective capacitance value for a downstream load seen at said node, wherein said determining an equivalent effective capacitance includes: utilizing a pi-model to model said downstream load; and determining an Elmore delay value for said node; wherein said equivalent effective capacitance (Ceff) is characterized by: Ceff=Cfi (1 −e −T/τdj ) wherein Cfj is a far-end capacitance of said pi-model at said node, T is the Elmore delay at said node and τdj is a resistance of said pi-model (Rdj) multiplied by Cfj; and utilizing said equivalent effective capacitance value to calculate said interconnect delay at said node.