Patent ID: 8671367

Claim:
A method of designing a circuit, comprising: providing a first set of design data associated with a design, wherein the first set of design data is in a first technology node; simulating the design with the first set of design data to generate a simulated design, the simulating being performed with a simulation model having an embedded scaling factor; generating a layout from the simulated design, the layout being in the first technology node; performing a design for manufacturability (DFM) analysis on the layout, wherein the DFM analysis includes: extracting a parameter from the layout in the first technology node with an electronic design analysis (EDA) tool having the embedded scaling factor; converting the parameter to the second technology node with the embedded scaling factor; providing the parameter to a DFM equation to produce a resultant parameter; and reverting the resultant parameter back to the first technology node with the embedded scaling factor; and generating a second set of design data with the layout, wherein the second set of design data is in the second technology node, and wherein the second technology node is an optical shrink of the first technology node.