Patent ID: 7250343

Claim:
A method for fabricating a power transistor arrangement, the method comprising: providing a cell array in a semiconductor substrate, the semiconductor substrate defining a substrate surface; providing an edge region adjoining the cell array in the semiconductor substrate; introducing a plurality of cell array trenches and at least one connection trench within the cell array, the at least one connection trench crossing the plurality of cell array trenches; introducing at least one edge trench in the edge region, the at least one edge trench adjoining the cell array trenches, and the at least one edge trench being wider than each of the plurality of cell array trenches and the at least one connection trench; applying an insulation layer; applying a first conductive layer to the insulation layer, the plurality of cell array trenches and the at least one connection trench being substantially completely filled with the first conductive layer, and the at least one edge trench not being completely filled with the first conductive layer; removing the first conductive layer from the at least one edge trench and causing the first conductive layer to recede in the cell array substantially to the substrate surface; applying a mask that covers the edge region and the at least one connection trench; causing the first conductive layer to recede in the cell array trenches in sections not covered by the mask; providing a gate insulation layer in the cell array trenches in the sections not covered by the mask, the gate insulation layer provided above the first conductive layer that has been caused to recede and forms a field electrode structure; and implementing a contact connection of the field electrode structure in the region of the connection trench.