Patent ID: 7755953

Claim:
A semiconductor memory device comprising: a memory cell array; an FIFO block that latches and outputs m-bit data via a data input/output terminal in a burst manner by performing a parallel serial conversion; a transfer circuit that transfers n-bit data in parallel to/from the memory cell array, the n-bit data being burst received from the data input/output terminal or to be burst outputted via the data input/output terminal; m data buses that are used to perform a data transfer operation between the transfer circuit and the FIFO block; and a mode register for setting a burst length; wherein the transfer circuit performs the data transfer operation using the data buses in units of m bits irrespective of the burst length where m is a minimum burst length settable in the mode register, the minimum burst length m is less than a minimum value of a prefetch number n, wherein the memory cell array is divided into a plurality of groups; the semiconductor memory device further comprises a main amplifier that outputs the n-bit data from each of the plurality of groups of the memory cell arrays; the transfer circuit selects m-bit data by each group out of the n-bit data outputted from the main amplifier; and the transfer circuit sequentially supplies via the data buses to the FIFO block the n-bit data read from the memory cell array belonging to a first group by each m bits, or sequentially supplies via the data buses to the FIFO block the m-bit data read from the memory cell array belonging to the first group and the m-bit data read from the memory cell array belonging to a second group, based on a content of the mode register.