Patent ID: 8131791

Claim:
An integrated circuit, comprising: a decision feedback equalizer (DFE) formed on said integrated circuit operable to receive a received stream of bits and provide a stream of sign bits, said DFE comprising: a first digital equalizer logic comprising, adder circuitry, and sign bit detection circuitry operable to compensate a first portion of bits in said received stream of bits and provide first sign bits for said stream of sign bits; and a second digital equalizer logic comprising, adder circuitry, and sign bit detection circuitry running concurrently with said first equalizer logic and connected in parallel relative to said first equalizer logic, said second equalizer operable to compensate at least a portion of said received stream of bits other than said first portion of bits and provide other sign bits for said stream of sign bits, wherein said second equalizer logic comprises: a low sign bit pipeline circuitry operative to provide a first conditional sign bit by assuming a low sign bit for a one of said first bits being concurrently processed by said first equalizer logic, and a high sign bit pipeline circuitry operative to provide a second conditional sign bit output by assuming a high sign bit for said concurrently processed one of said first bits, and a sign bit selection element coupled to receive said first and said second conditional sign bits and a sign bit outcome for said concurrently processed one of said first bits and operable to select between said first and second conditional sign bits based on said sign bit outcome; wherein said first equalizer logic, said low sign bit pipeline circuitry, and said high sign bit pipeline circuitry each compensate said received bits using one of a plurality of compensation weights, and wherein said used one of said compensation weights is chosen based on most recent ones of said first conditional sign bit, said second conditional sign bit, and said sign bit outcome.