Patent ID: 7981748

Claim:
A method for fabricating a vertical field effect transistor array semiconductor structure comprising: forming a plurality of identically sized mask layers located upon a semiconductor substrate; annularly augmenting each of the plurality of identically sized mask layers to provide a plurality of annularly augmented mask layers upon the semiconductor substrate; etching at least an initial portion of the semiconductor substrate while using the plurality of annularly augmented mask layers as an etch mask to provide a plurality of semiconductor pillars within an etched semiconductor substrate, wherein each semiconductor pillar has a semiconductor pillar linewidth greater than a separation distance from an adjacent semiconductor pillar; completely removing each of the plurality of annularly augmented mask layers to expose a bare upper surface of each semiconductor pillar; forming source/drain regions within the bare upper surface of each semiconductor pillar and within base portions of the etched semiconductor substrate, where each neighboring semiconductor pillar shares a common source/drain region at footprints thereof; forming a conformal gate dielectric on sidewalls and directly on said bare upper surface of each semiconductor pillar, wherein a portion of said conformal gate dielectric extends atop each common source/drain; and forming a gate electrode annularly surrounding each semiconductor pillar, wherein said gate electrode has an upper surface that is planar with an upper surface of the conformal gate dielectric that is located directly on the bare upper surface of each semiconductor pillar.