Patent ID: 7319632

Claim:
A pseudo-dual port memory, comprising: an array of memory cells, wherein each memory cell in the array is a six-transistor memory cell; a first port comprising a first plurality of address input leads and a clock input lead, wherein a first low-to-high transition of a first clock input signal on the clock input lead of the first port causes an address on the first plurality of address input leads to be latched into the pseudo-dual port memory and initiates a first memory access of the array of memory cells; and a second port comprising a second plurality of address input leads and a clock input lead, wherein: in a first case: a low-to-high transition of a second clock input signal on the clock input lead of the second port during a first time period would cause an address on the second plurality of address input leads to be latched into the pseudo-dual port memory and would cause a second memory access of the array of memory cells to be initiated following completion of the first memory access and before a second low-to-high transition of the first clock input signal, and in a second case: a low-to-high transition of the second clock input signal on the clock input lead of the second port during a second time period would cause the second memory access of the array of memory cells to be delayed until after the second low-to-high transition of the first clock input signal, wherein an end of the first time period coincides with a beginning of the second time period.