Patent ID: 7081417

Claim:
A method of manufacturing multilevel wiring for an electronic device provided with wiring layer patterns which hold an insulation layer between them and are partially connected, comprising in the following order: (a) a process for producing a substrate where a patterned wiring layer is formed on a flat insulation layer or an insulation layer provided with a via hole for partially connecting upper and lower wiring layer patterns; (b) a process for forming an insulation layer overall on the substrate so that the height of the top face of the insulation layer for burying a region without a wiring layer pattern is equal to the height of the top face of the wiring layer pattern; (c) (c-1) a process for forming a photoresist pattern provided with an opening on the wiring layer pattern on the insulation layer formed overall on the substrate; (d) a process for etching the insulation layer exposed from the photoresist pattern until the surface of the wiring layer is exposed; (e) a process for removing the convex insulation layer left in the vicinity of a boundary of the wiring layer pattern, and/or the convex insulation layer left on the wiring layer buried in the via hole and/or the convex insulation layer left in the vicinity of the boundary of a Josephson junction using bias sputtering or CMP or using both; and (f) a process for forming a second insulation layer provided with a via hole for partially connecting upper and lower wiring layer patterns on the wiring layer formed in the process or on the wiring layer partially including the insulation layer, wherein: further, the processes (a) to (f) are repeated.