Patent ID: 7339861

Claim:
A PLL clock generator for generating an output signal, of which the frequency is N times (where N is a natural number equal to or greater than 1) as high as that of an input signal, the clock generator comprising: a frequency divider for counting a clock signal and dividing the frequency of the clock signal by N so as to output a frequency-divided clock signal; a phase comparator for detecting a phase difference between the input signal and the output signal of the frequency divider so as to output a phase difference signal including information representing the phase difference; a low pass filter for smoothing the phase difference signal; a voltage-controlled oscillator for generating the clock signal, of which the frequency is determined by the output of the low pass filter, and outputting the clock signal to the frequency divider; a time width detector for outputting a positive phase difference signal and a negative phase difference signal based on the phase difference signal; and a phase shifter for advancing the count of the frequency divider if the amplitude of the positive phase difference signal is equal to or greater than a first predetermined value and delaying the count of the frequency divider if the amplitude of the negative phase difference signal is equal to or greater than a second predetermined value so as to change the phase of the output signal of the frequency divider.