Patent ID: 7411411

Claim:
A system for hardening a clocked latch against single event effects, the system comprising: a first three-input OR gate; a first NAND gate that (i) includes a first input and second input and (ii) produces a first output signal; a second three-input OR gate; and a second NAND gate that (i) includes a third input and fourth input and (ii) produces a second output signal, wherein the first three-input OR gate receives as inputs a clock signal, a first signal, and a redundant first signal, and wherein an output of the first three-input OR gate is connected to the first input of the first NAND gate, wherein the second three-input OR gate receives as inputs the clock signal, a second signal, and a redundant second signal, and wherein an output of the second three-input OR gate is connected to the third input of the second NAND gate, and wherein the first output signal is connected to the fourth input of the second NAND gate, and wherein the second output signal is connected to the second input of the first NAND gate.