Patent ID: 8531903

Claim:
A memory apparatus comprising: a memory block comprising (i) a plurality of memory cells and (ii) a plurality of pilot cells, wherein each of the plurality of memory cells and each of the plurality of pilot cells is configured to store at least two bits of corresponding data; and a channel block coupled to the memory block, wherein the at least two bits of data stored in each of the plurality of pilot cells is known to the channel block, and wherein the channel block is configured to receive, from each pilot cell of the plurality of pilot cells, a corresponding pilot signal that is based on the at least two bits of data stored in the pilot cell, such that a plurality of pilot signals are respectively received from the plurality of pilot cells, and calibrate a parameter based on the plurality of pilot signals, wherein the parameter, as calibrated by the channel block, is usable by the channel block to read the at least two bits of data stored in one or more of the plurality of memory cells.