Patent ID: 8145851

Claim:
An integrated device comprising: at least one processing module including at least one input/output port; and a plurality of memory systems accessible by the processing module; wherein each memory system includes a memory macro having a boundary and including a plurality of memory banks; and a memory interface connected to the processing module and each memory bank; the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnects being arranged in a first direction and a second direction so as to shape a matrix form within the boundary of the memory macro such that the processing module and each memory system is configured to interface and access each memory bank of the memory macro; the connection interconnects include instruction information interconnects and data interconnects being arranged in multiple layers; the instruction information interconnects are formed by private interconnects; at least a portion of the data interconnects are formed by private interconnects; and wherein memory macros of the plurality of memory systems are arranged in parallel in the second direction, the second direction substantially perpendicularly intersecting the first direction, the first direction being a direction connecting the processing module and the memory interface.