Patent ID: 8407392

Claim:
A cache unit comprising: a first memory tower, having a first way sub-tower and a second way sub-tower; a second memory tower, having a first way sub-tower and a second way sub-tower, wherein a first cache line of the cache unit includes a first plurality of data segments in the first way sub-tower of the first memory tower and a second plurality of data segments in the first way sub-tower of the second memory tower; a first way multiplexer having a first input port coupled to the first way sub-tower of the first memory tower, a second input port coupled to the first way sub-tower of the first memory port, and an output port; a second way multiplexer having a first input port coupled to the first way sub-tower of the second memory tower, a second input port coupled to the first way sub-tower of the second memory port, and an output port; and a data aligner coupled to the output port of the first way multiplexer and the output port of the second way multiplexer, wherein the data aligner comprises a first data aligner multiplexer and a second data aligner multiplexer, and output data from second way multiplexer are applied to the logic high input port of the second data aligner multiplexer and the logic low input port of the first data aligner multiplexer, and output data from first way multiplexer are applied to the logic high input port of first data aligner multiplexer and the logic low input port of second data aligner multiplexer.