Patent ID: 8615063

Claim:
A level transition determination circuit comprising: a multi-phase clock generator for receiving an input clock signal and generating S×N clock signals, wherein each clock signal is synchronized to the input clock signal and has a different delay time, and S and N are integers; an oversampling unit for performing N-times oversampling on M bit periods of a serial input data according to the clock signals so as to generate M×N sampled values in parallel during the M bit periods; and a state detection circuit for receiving (M×N)+1 sampled values and for generating N detection signals by detecting level transitions between adjacent sampled values in the (M×N)+1 sampled values and the level transition results; wherein the state detection circuit comprises: M groups of logic circuits, wherein each group of logic circuits comprises N Exclusive-OR (XOR) circuits, and each XOR circuit is used for performing an XOR operation on adjacent sampled values in the serial input data; and N probability circuits each for receiving an output signal from a different group of logic circuits and for generating a detection signal according to M output signals, wherein the M output signals are spaced from each other by a fixed time interval; wherein each of the probability circuits comprises: an AND array for receiving the M output signals and for generating a plurality of logic operation signals; and an OR circuit for receiving the logic operation signals and for generating the detection signal.