Patent ID: 8520440

Claim:
A semiconductor memory device comprising: a memory array configured to have memory cell strings including a first memory cell group having memory cells connected in series; a second memory cell group having memory cells connected in series, wherein the second memory cell group is not selected in case that the first memory cell group is selected for an erase operation and the first memory cell group is not selected in case that the second memory cell group is selected for an erase operation; a first and a second dummy elements connected in series between the first memory cell group and the second memory cell group, wherein the first and the second dummy elements are configured to electrically connect the first memory cell group to the second memory cell group during a program operation or a read operation of a selected memory cell; and a drain select transistor and a source select transistor connected to the first memory cell group and the second memory cell group, wherein the first memory cell group and the second memory cell group are arranged between the drain select transistor and the source select transistor, wherein one of the first dummy element and the second dummy element adjacent to the memory cell group selected for an erase operation is selected during the erase operation of the memory cell group selected for an erase operation.