Patent ID: 8384452

Claim:
A PLL (Phase Locked Loop) circuit comprising: an input to receive a reference clock signal; a digital phase detector operatively coupled to the input; a digital loop filter operatively coupled to the digital phase detector to digitally filter an output of the digital phase detector; a fractional synthesizer operatively coupled to the digital loop filter to synthesize a PLL output signal under control of an output of the digital loop filter; and a feedback path operatively coupled to the fractional synthesizer and to the digital phase detector, to provide a feedback signal, based on the PLL output signal, as an input signal for the digital phase detector, the fractional synthesizer comprising: an input to receive a second reference clock signal; a phase detector operatively coupled to the input; a loop filter operatively coupled to the phase detector to filter an output of the phase detector; a VCO (Voltage Controlled Oscillator) operatively coupled to the loop filter to generate the PLL output signal under control of an output of the loop filter; and a fractional N divider operatively coupled to the VCO, to the phase detector, and to the digital loop filter, to generate a feedback signal as an input signal for the phase detector by dividing a frequency of the PLL output signal by a variable modulus.