Patent ID: 7308522

Claim:
A system, comprising: a CPU; a memory coupled to the CPU via a host bus; and an adapter unit that couples a first peripheral bus to the host bus or a second peripheral bus, wherein the adapter unit comprises a multi-entry write buffer and also comprises a multi-entry read buffer in which read transactions can be stored pending execution, said adapter unit also has first and second interfaces that handle split transactions and wherein the adapter unit implements ordering rules to support multi-threading and the selective ordering of read transactions, write transactions and split transactions, wherein the adapter unit also comprises a read context register associated with each entry of the read buffer, each read context register comprising a plurality of write contingency bits, each write contingency bit being associated with a separate entry in the write buffer, and each write contingency bit indicating whether a write transaction is present in the write buffer and ahead of a read buffer read transaction corresponding to that write transaction.