Patent ID: 6920531

Claim:
A system for reducing latency or computer operations, comprising: a first processing pipeline comprising a prevalidated cache translation lookaside buffer (TLB), the prevalidated cache TLB comprising virtual address (VA) content addressable memory (CAM), wherein the VA CAM receives virtual address information for integer load operations; and a second processing pipeline, independent of the first processing pipeline, the second processing pipeline comprising: a cache tag array that holds physical addresses of cache lines, a master TLB that receives virtual address information for store operations and generates a physical address, a bypass around the master TLB, wherein if a store address is a physical address, the physical address bypasses the master TLB, and a comparator that compares physical address from one of the bypass and the master TLB to a physical address from the cache tag array, wherein if the physical addresses match, a store/invalidate cache way hit is generated.