Patent ID: 7085152

Claim:
A DRAM IC comprising: a first external connection to receive a first power supply voltage; a second external connection to receive a second power supply voltage that is lower in voltage than the first power supply voltage; a plurality of memory cells organized into a two-dimensional array to store data, wherein the memory cells are powered by the first power supply voltage, receive and output data through a plurality of bit lines coupled to the plurality of memory cells, and are controlled through a plurality of word lines coupled to the plurality of memory cells; a first logic directly coupled to the memory cells to at least transmit signals to the memory cells, wherein the first logic is powered by the first power supply voltage; and a second logic coupled to the first logic to provide an external interface to receive commands and addresses to select memory cells from among the plurality of memory cells for access, and to both receive data to store within and output data retrieved from the selected memory cells, wherein the second logic is powered by the second power supply voltage; wherein the first logic includes refresh logic to operate the plurality of word lines to carry out refresh operations to preserve data stored within the plurality of memory cells while the DRAM IC is placed in a lower power state in which the second logic is deprived of power as a result of the second power supply voltage being removed.