Patent ID: 8884650

Claim:
A high-frequency semiconductor switching circuit comprising: a semiconductor substrate; one common input-output terminal, three or more individual input-output terminals, and three or more control terminals corresponding to the three or more individual input-output terminals, these terminals being formed on the semiconductor substrate; three or more path switching FET stages formed on the semiconductor substrate and each provided between the common input-output terminal and a corresponding one of the three or more individual input-output terminals; one or more shunt FET stages formed on the semiconductor substrate and each provided between ground and at least one of the three or more individual input-output terminals; and a diode-switch logic circuit including diodes and switches formed on the semiconductor substrate such that a group of a part of the diodes and a part of the switches corresponds to each of the one or more shunt FET stages, the diode-switch logic circuit being configured to control the three or more path switching FET stages and the one or more shunt FET stages, wherein: the diode-switch logic circuit is configured to respectively apply control voltages, respectively input to the three or more control terminals, to gates of the three or more path switching FET stages in order that at least one of high-frequency signal paths between the common input-output terminal and the respective individual input-output terminals is caused to become a conducting state, and the other high-frequency signal paths are caused to become a cutoff state; the diode-switch logic circuit is configured to respectively apply logic synthesis voltages to gates of the one or more shunt FET stages, each of the logic synthesis voltages being obtained by logic synthesis of the control voltages respectively input to the three or more control terminals; and the diode-switch logic circuit is configured such that in a case where the one or more shunt FET stages are three or more shunt FET stages corresponding to the three or more path switching FET stages, the logic synthesis voltage corresponding to one of the three or more shunt FET stages is generated as a logical product of a logical negation of the control voltage applied to the one of the three or more shunt FET stages and a logical sum of the control voltages respectively applied to the remaining shunt FET stages other than the one of the three or more shunt FET stages.