Patent ID: 8624377

Claim:
A semiconductor package comprising: a substrate; a first chip mounted on the substrate, wherein a first surface of the first chip faces away from the substrate; a wire bonding the substrate to a first bump pad located on the first surface of the first chip; a first layer disposed on at least a portion of the first surface of the first chip; a via formed in the first layer, wherein the via extends to a second bump pad located on the first surface of the first chip; a second chip disposed on the first layer, wherein a first surface of the second chip faces towards the first layer, wherein the second chip includes a third bump pad located on the first surface of the second chip, and wherein the third bump pad is aligned with the via formed in the first layer; and an interconnect material between (i) the second bump pad located on the first surface of the first chip and (ii) the third bump pad located on the first surface of the second chip, wherein the interconnect material is formed inside the via, and wherein a height of the interconnect material is at least as large as a height of the first layer.