Patent ID: 8017435

Claim:
A method for packaging electronic components comprising: a) providing at least one support substrate ( 1 ) comprising a layer of material selected from a group consisting of silicon, gallium arsenide, InP, SiGe, sapphire or a semiconductor having a an energy gap between 2.5 and 10.0 eV, b) producing at least one recess ( 7 ) in a top side ( 1 a ) of said support substrate ( 1 ) comprising one stair ( 11 ) at one side of and within the recess using a subtractive process selected from the group consisting of etching, lapping and sandblasting, c) placing at least one first electronic device ( 61 ) partially onto said stair ( 11 ) to space said first electronic device ( 61 ) from a bottom ( 71 ) of said recess ( 7 ); and d) covering at least partially said top side ( 1 a ) of said support substrate ( 1 ) with a lid ( 4 ).