Patent ID: 7512742

Claim:
A method of data processing in a cache coherent data processing system including at least first and second coherency domains, said method comprising: in a first cache memory within said first coherency domain of said data processing system, holding a memory block in a storage location associated with an address tag and a coherency state field; determining if a home system memory assigned an address associated with said memory block is within said first coherency domain, wherein said home system memory resides at a lowest level of a volatile memory hierarchy of the data processing system; in response to determining said home system memory is not within said first coherency domain, setting said coherency state field to a first coherency state that indicates that said address tag is valid, that said storage location does not contain valid data, that said first coherency domain does not contain said home system memory, and that, following formation of said first coherency state, said memory block is cached outside of said first coherency domain; and in response to determining that said home system memory is within said first coherency domain, setting said coherency state field to a second coherency state that indicates that said address tag is valid, that said storage location does not contain valid data, said first coherency domain contains said home system memory, and that, following formation of said second coherency state, said memory block is cached outside of said first coherency domain.