Patent ID: 7865637

Claim:
A hardware object, comprising: one or more input interfaces each coupled to a respective sending object and structured to accept one or more message packets from the respective sending object over a parallel communication bus that includes dedicated and permanent channels for simultaneously carrying a data channel for data, a separate validity channel for describing a validity of the data, and a separate packet channel for indicating whether the data is a component member of the one or more message packets, each of the input interfaces including data storage registers corresponding to the channels of the communication bus to simultaneously store one or more elements of data, a valid indicator, and a packet indicator received from the communication bus; an object core coupled to the one or more input interfaces and to no other control elements, the object core structured to generate an input accept signal that causes the object core to determine when a new execution instruction is accepted, to generate a data valid signal, change execution states only after receiving execution instruction data in any message packet from the one or more input interfaces, and to operate completely independent from any information outside of the object core; and an output interface coupled between the core and a receiving object structured to send one or more message packets to such a receiving object, along with the data valid signal generated by the object core.