Patent ID: 8601240

Claim:
A method for executing instructions in a processor, comprising: while executing instructions in an execute-ahead mode, encountering a store instruction for which a destination address is unknown; deferring the store instruction; updating an entry in a store queue for the processor to include a record indicating that the store instruction has been deferred, wherein the store queue comprises a memory for buffering stores which is divided into two or more banks and which is separate from cache for the processor, and wherein updating the entry in the store queue comprises determining a bank in which the entry for the store queue is located and updating the entry in the determined bank; upon encountering a load instruction while the store instruction with the unknown destination address is deferred, determining if the load instruction is to continue executing or is to be deferred by: determining if the load instruction would retrieve data from the bank in which the entry for the store queue is located; when the load instruction would retrieve data from the bank, deferring the load instruction; and when the load instruction would not retrieve data from the bank, continuing executing the load instruction.