Patent ID: 8055960

Claim:
A computing system having a system configuration, said computing system comprising: a plurality of processors, each processor of said processors having a service element (SE) and having a cache memory, the cache memory including a plurality of independently configurable subdivisions, each subdivision including a memory array; said service element (SE) for each of said processors operable to cause a built-in-self-test (BIST) to be executed to test said cache memory, said BIST operable to determine whether any of said subdivisions is defective, such that: (a) said SE is operable to logically delete one of said subdivisions determined defective by said BIST when said one subdivision is non-repairable and said SE is operable to permit its processor to operate without said logically deleted subdivision, and (b) said SE is operable to determine that its processor is a defective one processor when a number of said defective subdivisions exceeds a threshold, wherein said cache memory is an N-way set associative cache memory, and said subdivision is a set of said cache memory, and wherein said computing system includes a spare processor and said SE is operable to replace its said defective one processor of said computing system with said spare processor and said SE is operable to automatically delete a defective one of said sets without intervention by a user, said SE being operable to logically delete said defective set only after said BIST is completed for said cache memory, and wherein said SE is operable, upon said BIST determining that two or more of said sets of one processor are defective, to remove said one defective processor from said system configuration.