Patent ID: 6915322

Claim:
A multiply unit comprising: a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier; an adder having input ports which are larger than output ports of the multipliers, wherein an output port of the first multiplier is coupled to least significant bits of an input port of the adder, output ports of the second and third multipliers are coupled to input ports of the adder but not least or most significant bits of the input ports, and an output port of the fourth multiplier is coupled to an input port of the adder but not the least significant bits of the input port; an output circuit that provides output signals from the multipliers when the multiplier circuit operates in a first mode, and provides an output signal from the adder when the multiply unit operates in a second mode; and an operand selection circuit coupled to the first, second, third, and fourth multipliers, wherein: in the first mode, the operand selection circuit applies a first portion of a first operand signal and a first portion of a second operand signal to the first multiplier, applies a second portion of the first operand signal and a second portion of the second operand signal to the second multiplier, applies a third portion of the first operand signal and a third portion of the second operand signal to the third multiplier, and applies a fourth portion of the first operand signal and a fourth portion of the second operand signal to the fourth multiplier; and in the second mode, the operand selection circuit applies the first portion of the first operand signal and the first portion of a second operand signal to the first multiplier, applies the second portion of the first operand signal and the first portion of the second operand signal to the second multiplier, applies the second portion of the first operand signal and the first portion of the second operand signal to the third multiplier, and applies the second portion of the first operand signal and the second portion of the second operand signal to the fourth multiplier.