Patent ID: 8035218

Claim:
A microelectronic package comprising: a first substrate having a first surface area and containing a first plurality of electrically conductive traces, where adjacent ones of the first plurality of electrically conductive traces are separated by a first space, the first substrate comprising a first set of interconnects having a first pitch at a first surface thereof and a second set of interconnects having a second pitch at a second surface thereof; and a second substrate having a second surface area and containing a second plurality of electrically conductive traces, where adjacent ones of the second plurality of electrically conductive traces are separated by a second space that is larger than the first space, the second substrate coupled to the first substrate using the second set of interconnects and comprising: a third set of interconnects having a third pitch; and first and second internal electrically conductive layers that are connected to each other with a microvia, wherein: the first pitch is smaller than the second pitch; the second pitch is smaller than the third pitch; and the first surface area is smaller than the second surface area.