Patent ID: 7592219

Claim:
A method of fabricating a lower electrode of a capacitor, comprising: providing a substrate having at least one active region and an isolation region surrounding the active region; forming a plurality of word lines on the substrate crossing over the active region; forming a plurality of landing plug contacts (LPC) between the word lines; simultaneously forming at least one capacitor-terminal lower contact on the landing plug contact on the active region and forming at least one bit line contact on the landing plug contact on the isolation region; simultaneously forming a capacitor-terminal upper contact on each capacitor-terminal bottom contact and forming a bit line on the bit line contact; forming an inter-layer dielectric layer on a surface of the substrate to cover the bit line and the capacitor-terminal upper contact; forming a capacitor opening in the inter-layer dielectric layer, wherein the capacitor opening exposes the capacitor-terminal upper contact; and forming a conductive layer on a surface of the capacitor opening.