Patent ID: 7547941

Claim:
A NAND non-volatile two-bit memory cell comprising: a cell stack and two select stacks disposed on an active area of a substrate, each select stack respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stack; wherein the cell stack comprises a first dielectric layer disposed over the substrate, a charge accumulation layer holding charge in a portion thereof to store information disposed over the first dielectric layer, a second dielectric layer disposed over the charge accumulation layer and a control gate disposed over the second dielectric layer, and the select stack comprises a third dielectric layer disposed over the substrate and a select gate disposed over the third dielectric layer, wherein the memory cell has a first state having no source or drain region, and a second state that the select gate inverts an underneath channel region in the active area to function as a source or a drain of the memory cell.