Patent ID: 8898601

Claim:
A computer-implemented method of generating a net list, the method comprising: generating logical data for each of portions corresponding to blocks of a register transfer level description relevant to operation of a gate logic circuit, accounting for an order of priority in the register transfer level description, based on a source code comprising the register transfer level description; generating one or more constraint conditions designating circuit data which satisfies a condition among a plurality of gate level circuit data logically equivalent to the logical data for each of the portions, based on the source code, the generating the one or more constraint conditions comprising setting a fixing attribute for at least one of the portions describing an AND logic operation on an asynchronous signal or a multi-cycle signal, and an enable signal or a select signal, the fixing attribute configured to exclude performance of optimization on the at least one of the portions; and generating the net list based on optimization of the logical data under the one or more constraint conditions including the fixing attribute, the method performed programmatically by a design system that comprises one or more computers.