Patent ID: 8704144

Claim:
A dual speed readout integrated circuit comprising: a native pixel array with associated high resolution integration circuits for each pixel wherein each native pixel in the native pixel array comprises: a detector; a first integration capacitor connected to the detector and a second integration capacitor connected to the detector; and, a sample and hold capacitor selectably connectable to the first integration capacitor; a superpixel array created from the entire native pixel array by combination of native pixels in superpixels for charge sharing integration in reduced resolution integration circuits simultaneously with the integration of the high resolution integration circuits wherein each superpixel in the superpixel array includes a second sample and hold capacitor selectively connectable to the second integration capacitor in each native pixel combined for the superpixel; switching control for readout of the high resolution integration circuits at a first frame rate; and switching control for readout of the reduced resolution integration circuits at a second frame rate.