Patent ID: 7403051

Claim:
A method for determining voltage level validity for a power-on reset condition, comprising: applying a supply voltage to an integrated circuit; receiving the supply voltage in a first power-on reset circuit of the integrated circuit; generating an oscillating signal responsive to the supply voltage applied, the oscillating signal having a frequency which is a function of the first supply voltage level; counting oscillations of the oscillating signal; storing a first count of the oscillations of the oscillating signal; outputting the first count in response to a first change in output state of the first power-on reset circuit; selecting a target count of oscillations of the oscillating signal, the target count being greater than the first count and indicating that the supply voltage has reached at least a first minimum level specified for the supply voltage; triggering a first power-on reset responsive to reaching a first voltage level of the supply voltage for the power-on reset condition; receiving the supply voltage in a second power-on reset circuit; storing a second count of the oscillations of the oscillating signal; outputting the second count in response to a second change in output state of the second power-on reset circuit; triggering a second power-on reset responsive to reaching a second voltage level of the supply voltage for the power-on reset condition; receiving the first count and the second count; determining a rate of change between the first voltage level and the second voltage level responsive to a difference between the first count and the second count; and selecting a third count greater than the second count, the third count indicating an amount of additional time to wait to reach a third voltage level for the supply voltage.