Patent ID: 7439813

Claim:
An RF clock generator of the type that uses a PLL for enabling generation of first, second and third carrier frequencies of 3432 MHz, 3960 MHz and 4488 MHz respectively, for use in a wireless transmission system, comprising: first and second PLLs configured to generate 6336 MHz and 2640 MHz signals respectively with only in-phase components; frequency dividers to divide the 6336 MHz signal severally by 2, 4 and 12 to obtain a first set of intermediate frequency-divided outputs having both in-phase and quadrature components, and to divide the 2649 MHz signal by 2 after passing it through a multiplexer to obtain a second intermediate frequency-divided output; and, a single side band mixer for inputting said first set of intermediate frequency-divided outputs and said second intermediate frequency-divided output to obtain the first, second and third carrier frequencies to contain both in-phase and quadrature components, wherein said frequency dividers are configured to divide in half, a signal obtained from combining the second predetermined frequency signal with another signal derived from divisions of the first predetermined frequency signal before feeding the single side band mixer.