Patent ID: 7986292

Claim:
A liquid crystal display device comprising: a liquid crystal display panel having a first substrate, a second substrate, and a liquid crystal material sandwiched between the first substrate and the second substrate; an image line driving circuit; and a scanning line driving circuit, wherein the liquid crystal display panel further has: an (m×n)-number of sub pixels respectively having thin-film transistors; an m-number of scanning lines for inputting selected scanning voltages to gates of the thin-film transistors of the (m×n)-number of sub pixels; and an n-number of image lines for inputting image voltages to first electrodes of the thin-film transistors of the (m×n)-number of sub pixels, the image line driving circuit has: an n-number of switching elements for sampling a k-number of gradation voltages inputted from outside and then sequentially supplying the gradation voltages to groups of the k-number of image lines into which the n-number of image lines are divided (where k is smaller than n), the groups including first to (n/k)-th groups; a shift register circuit for sequentially inputting sampling voltages to groups of a k-number of switching elements into which the n-number of switching elements are divided to thereby sequentially turn on the groups of a k-number of switching elements, the groups including first to (n/k)-th groups; and a pre-charge circuit supplying a pre-charge voltage to the image lines before the gradation voltages are supplied to the respective image lines within one scanning period, the gradation voltages are supplied to the respective image lines during (n/k) clocks, the pre-charge voltage is supplied to the respective image lines after 24 clocks from each (n/k)-th clock, the scanning line driving circuit is a liquid crystal display device sequentially supplying selected scanning voltages to the m-number of scanning lines, the image line driving circuit and the scanning line driving circuit are circuits built in a semiconductor chip mounted on the first substrate, the thin-film transistor has a semiconductor layer formed of amorphous silicon, and when voltage levels of the k-number of gradation voltages inputted from outside are at 0 to 5V, the selected scanning voltages inputted to the gates of the thin-film transistors are 20V or more.