Patent ID: 8431431

Claim:
A manufacturing method comprising: (1) obtaining a structure comprising: a planar insulating layer having a first planar surface and a second planar surface opposite to the first planar surface; a first semiconductor layer having a planar surface contacting the first planar surface of the planar insulating layer; and a second semiconductor layer having a planar surface contacting the second planar surface of the planar insulating layer; (2) removing part of the first semiconductor layer to form one or more first vias through the first semiconductor layer, the one or more first vias not passing through the planar insulating layer; (3) removing part of the second semiconductor layer to form one or more second vias through the second semiconductor layer, the one or more second vias not passing through the planar insulating layer; (4) forming one or more through-holes in the planar insulating layer to join each second via with a respective first via to form a respective through via passing through the first and second semiconductor layers and the planar insulating layer; and (5) forming a conductor in each through via, the conductor providing a conductive path in the through via between the first and second semiconductor layers.