Patent ID: 8842675

Claim:
A data processing appliance (DPA) comprising: an input configured to receive a plurality packets; a demultiplexor configured to append metadata to the plurality of packets, wherein the metadata indicates an order in which the plurality of packets were received; a plurality of processing cores, each of the plurality of processing cores configured to process a portion of the plurality of packets independent of the other processing cores; and a multiplexor configured to: multiplex the plurality of packets after the plurality of packets are output from the plurality of processing cores based on the appended metadata, and prior to sending a given packet to an output, ensure the output of the given packet is delayed by at least a predetermined amount of time relative to an arrival time of the given packet using metadata corresponding to the given packet, wherein the metadata corresponding to the given packet comprises a timestamp value, and the predetermined amount of time exceeds an expected maximum processing delay for a maximum packet size given the processing task implemented by the plurality of processing cores.