Patent ID: 7526635

Claim:
A programmable processor comprising: an instruction path; a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a register file operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction and data paths and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction for writing data to memory based on a mask and data contained in at least one register, the mask consisting of N independently selectable mask bits, N being an integer multiple of eight, each of the mask bits corresponding to a data bit contained in the at least one register, each of the mask bits being independently selectable as either a write-enabled mask bit or a write-disabled mask bit, the execution unit is operable to: (i) detect some of the mask bits of the mask as being selected as write-enabled mask bits to identify corresponding data bits of the data contained in the at least one register as write-enabled data bits; and (ii) cause the write-enabled data bits to be written to a specified memory location.