Patent ID: 7088624

Claim:
A system of multiplexed data lines in a DRAM integrated circuit, comprising: (a) a switching circuit having a first switching state and a second switching state; (b) a first data path associated with a first memory portion of the DRAM integrated circuit, the first data path comprising a first plurality of master data lines for the first memory portion of the DRAM integrated circuit; (c) a second data path associated with a second memory portion of the DRAM integrated circuit, the second data path comprising a second plurality of master data lines for the second memory portion of the DRAM integrated circuit; (d) a plurality of read-write data lines of the DRAM integrated circuit, wherein the first data path is in communication with the plurality of read-write data lines when the switching circuit is in the first switching state, and wherein the second data path is in communication with the plurality of read-write data lines when the switching circuit is in the second switching state; (e) a first plurality of transmission gates between the first data path and the plurality of read-write data lines, wherein the first plurality of transmission gates conduct in the first switching state and do not conduct in the second switching state; and (f) a second plurality of transmission gates between the second data path and the plurality of read-write lines, wherein the second plurality of transmission gates conduct in the second switching state and do not conduct in the first switching state.