Patent ID: 7989891

Claim:
A method for fabricating an MOS structure, the method comprising the steps of: providing a semiconductor layer having a first portion at least partially surrounded by an isolation region, the first portion having a length, and a second portion extending from the first portion and surrounded on three sides by the isolation region, the second portion having a length less than the length of the first portion; forming a first gate stack and a second gate stack on the first portion of the semiconductor layer, wherein the first gate stack and the second gate stack are substantially parallel; depositing an insulating material overlying the first portion and the second portion of the semiconductor layer and at least a portion of the isolation region; and forming a conductive contact through the insulating material to the second portion and outside an entire space between the first gate stack and the second gate stack, as viewed from a plan view, such that the conductive contact is in electrical communication with the first gate stack and the second gate stack via a portion of the semiconductor layer within the space.