Patent ID: 7889513

Claim:
A semiconductor device, comprising: a wiring substrate having a front surface, a back surface opposed to the front surface, and a plurality of bonding leads formed on the front surface and arranged along sides of the front surface in a plan view; a semiconductor chip mounted on the front surface of the wiring substrate such that the bonding leads are arranged around the semiconductor chip in a plan view; a plurality of wires electrically connecting electrodes of the semiconductor chip with the bonding leads of the wiring substrate, respectively; and a plurality of external connection terminals formed on the back surface of the wiring substrate, wherein the wires are electrically connected with the bonding leads via first wire connecting portions, respectively, wherein the wires are formed by electrically connecting a part of each of the wires with each of the bonding leads before electrically connecting another part of each of the wires with each of the electrodes, wherein first parts of the wires are located at a first portion, respectively, wherein the first portions are arranged to be farther from an edge of the semiconductor chip in a first direction than the first wire connecting portions, respectively, and wherein the first portions are located between the first wire connecting portions and the sides of the front surface of the wiring substrate in the first direction, respectively.