Patent ID: 7535260

Claim:
A logic gate electrically connected to a first power source and a second power source having a lower voltage than the first power source, the logic gate comprising: a first driver connected to the first power source, and controlling a connection of a first node to the first power source based on a plurality of externally supplied input signals; a first control transistor connected between the first node and the second power source to control a voltage of the first node; a second driver connected between a gate electrode of the first control transistor and the second power source; a third driver connected between the first power source and the second power source, and driven by a voltage applied to the first node; a second control transistor connected between the third driver and the second power source, and having a first electrode connected to an output terminal; and a fourth driver arranged between a gate electrode of the second control transistor and the second power source, and controlling a connection between the gate electrode of the second control transistor and the second power source, wherein each of the first driver, the second driver, the third driver and the fourth driver includes at least one transistor, and each of the transistors of the first driver, the second driver, the third driver and the fourth driver, the first control transistor and the second control transistor are PMOS transistors.