Patent ID: 7342278

Claim:
A two-transistor non-volatile memory cell including: a semiconductor body; a memory-transistor well disposed within the semiconductor body; a switch-transistor well disposed within the semiconductor body and electrically isolated from the memory transistor well; a memory transistor formed within the memory-transistor well and including spaced-apart source and drain regions; a switch transistor formed within the switch-transistor well region and including spaced-apart source and drain regions; a floating gate insulated from and self aligned with the source and drain regions of the memory transistor and the switch transistor; and a control gate disposed above and self aligned with respect to the floating gate and with the source and drain regions of the memory transistor and the switch transistor, wherein the memory-transistor well is optimized for memory-transistor characteristics and the switch-transistor well is optimized for switch-transistor characteristics.