Patent ID: 7170115

Claim:
A semiconductor integrated circuit device comprising a plurality of gate array type logic cells composed of CMOS-type base cells arranged on a semiconductor substrate, m wiring layers, m being a natural number, and at least one power supply cell comprising the CMOS-type base cell, wherein: horizontal wiring connection within each logic cell and between the logic cells is constituted only in n upper wiring layers among the m wiring layers, n being a natural number with n<m; lower (m−n) wiring layers comprise first contact vias and first wiring patterns connected to respective first contact vias; the lower (m−n) layers of the at least one power supply cell comprise third contact vias disposed at positions corresponding to at least one grid of a power supply in the base cells and third wiring patterns connected to the third contact vias; third wiring patterns of neighboring power supply cells are connected to each other; and the at least one power supply cell is positioned adjacent to at least one of the logic cells.