Patent ID: 7466013

Claim:
A semiconductor die on a packaging structure, comprising: a width in the Y direction of said semiconductor die smaller than the length in the X direction of said semiconductor die; traversing rows of bonding pad structures wherein each row is comprised of individual bonding pad structures all aligned vertically in a Y direction, wherein a first vertical row and a second vertical row of bonding pad structures are located on each side of the semiconductor die, and wherein a third vertical row of bonding pad structures is located in the center of said semiconductor die; conductive lead structures on said packaging structure wherein each conductive lead structure is located adjacent to a bonding pad structure component of either said first vertical row, or of said second vertical row of bonding pad structures; four polyimide organic tape structures each located in a quadrant of said semiconductor die, and with each organic tape structure located on a portion of said semiconductor die not occupied by said rows of bonding pad structures; lead on chip (LOC) structures with each LOC structure comprised of a first portion located on said packaging structure and with a second portion located on a polyimide organic tape structure, wherein second portion of said LOC structure terminates adjacent to a bonding pad structure component of said third vertical row of bonding pad structures located in the center of said semiconductor die; a first group of conductive wires wherein each wire of said first group of conductive wires connects a bonding pad structure of said first vertical row; or of said second vertical row of bonding pad structures to a conductive leads structure; and a second group of conductive wires wherein each wire of said second group of conductive wires connects a bonding pad structure of said third vertical row of bonding pad structures to a LOC structure.