Patent ID: 7342802

Claim:
A multiple level circuit assembly, including: a first insulating film having a first major surface and a first patterned metal wiring film extending along said first major surface; a second insulating film having a second major surface and a second patterned metal wiring film extending along said second major surface, said second insulating film overlying said first insulating film and at least said second patterned metal wiring film contacting said first insulating film; a first plurality of etched metal bump interconnects having a first height, conductively connecting said first patterned metal wiring film to said second patterned metal wiring film, said first etched metal bump interconnects extending through at least one of said first and second insulating films in a direction transverse to said first and second major surfaces; a semiconductor chip having a thickness of about 50 micrometers (μm) or smaller, said semiconductor chip disposed between said first and second patterned wiring films, said semiconductor chip having bond pads conductively connected to said first patterned metal wiring films; a second plurality of etched metal bump interconnects having a second height, conductively connecting said semiconductor chip and said second patterned wiring film, wherein said first height is greater than said second height; and a plurality of external contacts exposed at one or more external surfaces of said circuit panel assembly, said contacts conductively connected to at least one of said first and second patterned metal wiring films.