Patent ID: 7363604

Claim:
An integrated circuit noise analysis method comprising the steps of: for each gate type in the integrated circuit calculating an equivalent output resistance, calculating an equivalent output capacitance, calculating a noise immunity, and identifying aggressor nodes for each gate including aggressor coupling capacitance and aggressor series resistance; and for all gates in the integrated circuit applying a preselected aggressor noise pulse to a gate output, comparing the gate output noise response to corresponding noise immunity, identifying gates where output noise response exceeds corresponding noise immunity; and calculating an equivalent of output resistance from the ratio of a required slew rate to the calculated equivalent output capacitance, wherein said step of calculating the equivalent output resistance further includes comparing the calculated equivalent output resistance to an ideal DC static output resistance realized from the specific transistor size for each gate, and validating the calculated equivalent output resistance if it exceeds the corresponding ideal DC static output resistance by a prescribed margin.