Patent ID: 8253680

Claim:
A shift register comprising a plurality of stages for sequentially outputting scan pulses to drive a plurality of gate lines, wherein each of the stages comprises: a set node; a pull-up switching device that outputs a scan pulse according to a logic state of the set node; at least two reset nodes; at least two pull-down switching devices, each of the pull-down switching devices being connected to a corresponding reset node to output an off voltage according to a voltage level of the corresponding reset node; and a node controller that controls logic states of the nodes of a corresponding stage along with logic states of the nodes of stages different from the corresponding stage, wherein the node controllers of the stages control an output order of the scan pulses from the stages according to a forward voltage and reverse voltage having opposite phases; wherein each of the stages comprises a first reset node, a first pull-down switching device connected to the first reset node, a second reset node, and a second pull-down switching device connected to the second reset node; wherein each of the stages is further supplied with: one of a plurality of clock pulses having different phases, a discharging voltage, and one of first and second alternating current (AC) voltages having opposite phases; wherein the first reset node of a (2k−1)th stage and the second reset node of a (2k)th stage are directly connected to each other, and the second reset node of the (2k−1)th stage and the first reset node of the (2k)th stage are directly connected to each other; and wherein the set node of a (2k−2)th stage is connected to a gate terminal of a switching device of the (2k−1)th stage, and the set node of the (2k−1)th stage is connected to a gate terminal of a switching device of the (2k−2)th stage.