Patent ID: 8114747

Claim:
A method for creating a 3-D (Three Dimensional) single gate inverter on a semiconductor substrate comprising: creating a gate having a first gate dielectric on a first surface of the gate and a second gate dielectric on a second surface of the gate, the first and second surfaces of the gate being parallel to the semiconductor substrate; creating first source/drain regions in a semiconductor substrate for a first FET; electrically isolating a third surface of the gate and a fourth surface of the gate, the third and fourth surfaces of the gate being perpendicular to the semiconductor substrate; growing a first epitaxial layer from the source/drain regions, the first epitaxial layer being doped opposite to the source/drain regions, the first epitaxial layer grown high enough to extend above the second gate dielectric, the first epitaxial layer serving as second source/drain regions for a second FET; and growing a second epitaxial layer from the first epitaxial layer, the second epitaxial layer being doped opposite the first epitaxial layer, the second epitaxial layer covering a top surface of the second gate dielectric.