Patent ID: 8904045

Claim:
A processor comprising: first logic to detect one or more bits in a message that are to be transmitted on behalf of an input/output (I/O) device, wherein the one or more bits are to indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device; and second logic to access a MMIO region in memory based on the MMIO information, wherein a switch, coupled between the I/O device and the first logic, is to generate the message on behalf of the I/O device and wherein the one or more bits are to be transmitted by the I/O device in response to a request received at the I/O device, wherein a MMIO range attribute bit is to indicate whether the message is a completion message, wherein, in response to return of the completion message indicating one or more MMIO range attributes are to differ from a default uncached behavior, the MMIO information is to be modified for future access to the MMIO region in the memory.