Patent ID: 7499464

Claim:
For use in a network system having a line card that generates data packets, a buffered crossbar switch having multiple buffers and a linear buffer to port relationship, where the number of buffers is less than the number of ports squared, where the number of buffers of the switch is linearly related to the number of ports of the switch, comprising: an internal buffer address decoder and control module, where the decoder is configured to receive address information from a line card scheduler and to decode the address information and generate a decoded address and wherein the control module negotiates the transfer of data from the line card to internal buffers; an input configured to receive data packets from the line card and to deserialize the data packets to generate a deserialized output; and a plurality of buffer structures, one for each port, each configured to receive a deserialized output from the input and to control an internal buffer system, where the each buffer structure includes a buffer read/write control configured to receive decoded addresses from the internal buffer address decoder and negotiate data transfers with the address decoder based on an internal buffer status; a plurality of multiplexers that route the received deserialized data from the input control by the buffer read/write control; a plurality of buffers, where each buffer is configured to receive data packets from the an associated multiplexer and to send a report signal, indicating whether the buffer is full, to the buffer read/write control; and a central buffer configured to receive outputs from the plurality of buffers and to generate an output.