Patent ID: 8171335

Claim:
A clock timing calibration circuit for calibrating a phase difference between a first clock signal and a second clock signal, comprising: a clock timing adjusting unit, configured for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate the first clock signal according to a calibration control signal, wherein the incoming reference clock has a predetermined phase and a predetermined frequency; and a calibration control unit, coupled to the clock timing adjusting unit, for checking if the phase difference between the first clock signal and the second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion, wherein the predetermined criterion is to check if the phase difference between the first clock signal and the second clock signal falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal.