Patent ID: 7542353

Claim:
A flash memory device comprising: a plurality of memory cell blocks, each of the plurality of cell blocks including a plurality of pages, each of the plurality of pages having a plurality of memory cells; an X-decoder for decoding block address signals, page address signals, and block size change signals in response to one of a program command, a read command, and an erase command, generating a plurality of block selection signals and word line bias voltages according to the decoding result, and outputting the word line bias voltages to a plurality of global word lines, respectively; and a plurality of block selection units, each of the plurality of block selection units connected to one of the plurality of memory cell blocks and connecting the plurality of global word lines, a global drain select line, and a global source select line to each of the plurality of memory cell blocks, in response to one of the plurality of block selection signals, wherein during an erase operation of the flash memory device, at least one of the plurality of block selection units selects at least one of the plurality of memory cell blocks, and the X-decoder outputs the word line bias voltages such that at least two of the plurality of pages included in at least one memory cell block are selected during the erase operation.