Patent ID: 7247578

Claim:
A method of forming integrated circuit comprising: forming a sacrificial gate electrode over a first channel region of a semiconductor substrate and forming a second sacrificial gate electrode over a second channel region of said semiconductor substrate; altering said first sacrificial gate electrode and/or said second sacrificial gate electrode such that said first sacrificial gate electrode can be etched with an etchant without etching said second sacrificial gate electrode; forming a dielectric layer over said first sacrificial gate electrode and over said second sacrificial gate electrode; planarizing said dielectric layer so as to exposed the top surface of said first sacrificial gate electrode and said second sacrificial gate electrode; after altering said first sacrificial gate electrode and/or said second sacrificial gate electrode etching said first sacrificial gate electrode with said etchant without etching said second sacrificial gate electrode to form a first opening and expose said first channel region of said semiconductor substrate; depositing a first metal film over said first channel region of said semiconductor substrate and on the top surface of said dielectric film; removing said first metal film from the top of said dielectric to form a first metal gate electrode; removing said second sacrificial gate electrode material to form a second opening; forming a second metal film different than said first metal film over said dielectric layer and into said second opening; and removing said second metal film from the top surface of said dielectric layer to form a second metal gate electrode.