Patent ID: 7339393

Claim:
A circuit arrangement comprising: an insulated gate power transistor provided in a chip housing, the power transistor including a gate terminal and a gate oxide; a gate drive circuit provided in the chip housing, the gate drive circuit being configured for operation in a test mode adapted to test the quality of the gate oxide of the power transistor, the gate drive circuit connected to the gate terminal of the power transistor to supply a gate drive signal to the power transistor; the gate drive circuit comprising: a first switch configured to apply a test voltage pulse to the gate terminal of the power transistor during a particular period of time, the voltage amplitude of the test voltage pulse being higher than the amplitude of a gate voltage pulse applied during normal operation of the power transistor; and an internal pulse generator operable to generate the test voltage pulse, wherein the gate drive circuit is operable to activate the first switch and the internal pulse generator during operation in the test mode in response to a test mode signal applied externally to the gate drive circuit.