Patent ID: 7573093

Claim:
An array of non-volatile memory cells including: a semiconductor body; a plurality of memory-transistor wells disposed within the semiconductor body; for each of the memory-transistor wells a first switch-transistor well disposed within the semiconductor body to a first side of the memory transistor well and electrically isolated from the memory transistor well and a second switch-transistor well disposed within the semiconductor body to a second side of the memory transistor well opposite the first side and electrically isolated from the memory transistor well; a memory transistor formed within each memory-transistor well and including spaced-apart source and drain regions; a first switch transistor formed within each first switch-transistor well region and including spaced-apart source and drain regions; a second switch transistor formed within each second switch-transistor well region and including spaced-apart source and drain regions; a floating gate segment insulated from and self aligned with the source and drain regions of each memory transistor and the first and second switch transistors with which it is associated; and a control gate disposed above and self aligned with respect to the floating gate segments and with the source and drain regions of the memory transistors and the switch transistors.