Patent ID: 7469365

Claim:
A multi-stage interleaving device comprising: (a) N units of processing parts arranged in tiers of N from a bottom to a top, wherein N is an integer greater than 1, each processing part comprising: an operating memory configured to provide a matrix of storage areas having columns and rows; first and second input terminals configured to receive a first stream of bits and a second stream of bits, respectively; a data writer configured to write the first stream of bits in storage areas in the matrix, starting from a top row of the matrix towards a bottom thereof, in a row direction from a left most storage area to right; and write the second stream of bits to fill unfilled storage areas in the matrix, starting from a left most column to right, in a column direction from a top unfilled storage area of each column towards the bottom; a data reader configured to read the bits of the first and second streams written in the matrix, starting from the left most column to right, in the column direction from a top storage area of each column towards the bottom to output a third steam of bits in which the bits of the first stream are scattered into the second stream at intervals; and an output terminal configured to output the third stream of bits, and (b) a plurality of connections for inputting and outputting streams of bits in and from the processing parts, comprising: N+1 lines of input connections configured to provide two streams of input bits to the first and second input terminals of the processing part located at the bottom tier and provide N−1 streams of input bits respectively to the first input terminals of the remaining processing parts located above the bottom tier; and N−1 lines of output connections configured to provide the third steam of bits from the output terminal of a processing part to the second input terminal of the processing part located one tier above.