Patent ID: 6897681

Claim:
A signal adapter for a multiplexed serial signal line, comprising: an OR gate for connecting a plurality of line drivers to said multiplexed signal line, comprising an output attached to the input of said multiplexed signal line, wherein said OR gate further comprises: a first driver input, connected to a first line driver of said plurality of line drivers, that receives a signal from said first line driver; a second driver input connected to a second line driver of said plurality of line drivers; a first power rail connected to said first line driver; and a second power rail connected to said second line driver, wherein each of said first line driver and said second line driver is allocated to one or more time-slots to drive data onto said multiplexed signal line, wherein, when said first and second line drivers connect to said corresponding first and second power rails at low impedance, said connected drivers drive the data, comprising either logic ones or logic zeros, to said output line of said signal adapter, and when said first and second line drivers are not driving the data, said corresponding first and second line drivers connect to said corresponding first and second power rails at high impedance, and wherein, when an off state of said second line driver is maintained at a logic zero, said OR gate reproduces the data driven by said first line driver onto said output.