Patent ID: 7023368

Claim:
A direct-digital-frequency synthesizer adapted to receive a frequency code and adapted to output an analog current, the direct-digital-frequency synthesizer comprising: a first latch adapted to receive the frequency code; an accumulator adapted to receive the latched frequency code and a previously accumulated digital word and adapted to output a currently accumulated digital word, wherein the currently accumulated digital word upon output replaces the previously accumulated digital word for a next cycle; a waveform determiner adapted to receive the currently accumulated digital word and output a digital data input; a first clock signal distribution module adapted to transmit a first clock signal to the accumulator and a second clock signal to a digital-to-analog converter (DAC); and the digital-to-analog converter (DAC) adapted to receive the digital input data and the second clock signal and adapted to output an analog current, the DAC comprising: an expansion code generator adapted to output a first digital expansion code; a second latch adapted to receive the digital input data and hold the digital input data; a multiplexer adapted to generate output by selecting the first digital expansion code from the expansion code generator during a first fraction of a clock cycle, the clock cycle comprising a plurality of cycle fractions, and by selecting the digital input data held by the second latch in a second fraction of the clock cycle, wherein the clock cycle is driven by a multiplexer clock signal; a third latch adapted to receive the generated output of the multiplexer and adapted to hold the generated output of the multiplexer; a current switch array adapted to receive the held multiplexer output and adapted to output analog current, and a second clock distributor adapted to receive the second clock signal and adapted to provide a second latch module clock signal, a third latch module clock signal, and the multiplexer clock signal.