Patent ID: 7582966

Claim:
A semiconductor chip comprising: a silicon substrate; at least one active device in or over said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said at least one active device, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure; a polymer bump over said passivation layer and over said at least one active device, wherein said polymer bump has a thickness of between 5 and 25 micrometers and a width between 5 and 40 micrometers; an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump; a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer, wherein the material of said third metal layer is the same as that of said seed layer.