Patent ID: 7088796

Claim:
A phase detector circuit for a phase looked loop (PLL) circuit used in a clock synthesis unit (CSU), said PLL having a voltage controlled oscillator (VCO) at its output, said VCO operating at a VCO frequency, comprising: (a) a REFCLK input for receiving an input clock signal operating at a REFCLK frequency equal to said VCO frequency divided by N, where N is an even integer greater than or equal to 2; (b) a FBCLK input for receiving a feedback clock signal taken from an output of said VCO and operating at a FBCLK frequency equal to said VCO frequency divided by N/(2^J), where J is an integer greater than or equal to 1, and N/(2^J)=N/2, N/4, . . . , N/N is an integer; (c) a logic circuit coupled to said REFCLK input and said FBCLK input and operative to produce UP pulses and DOWN pulses delayed by 2^J half clock cycles of said FBCLK input such that said UP and DOWN pulses substantially overlap when in a phase-locked condition; wherein one of: (i) positive edges of said UP pulses are fixed and movement of positive edges of said DOWN pulses relative to said positive edges of said UP pulses; and (ii) negative edges of said UP pulses are fixed and movement of negative edges of said DOWN pulses relative to said negative edges of said UP pulses, creates an incremental charge to or from a charge storage circuit and a correction of a loop filter voltage Vc on both positive and negative transitions of REFCLK input.