Patent ID: 6889268

Claim:
A synchronous semiconductor memory device that includes a burst read mode of operation having a plurality of internal burst cycles, comprising: a memory cell array that stores data information; an address generating circuit that operates synchronized with a clock signal and sequentially generates an internal address for the burst read mode of operation in response to an external address; a data read circuit that reads out burst data from the memory cell array based on a part of the internal address, the burst data being outputted during the respective internal burst cycles; a read control circuit that operates responsive to a read enable signal and controls a read operation of the data read circuit at a transition of either one of the external address and the internal address; a burst control circuit that operates responsive to a burst enable signal and generates a latch enable signal synchronized with the clock signal; a data register that latches the burst data read out through the read circuit in response to the latch enable signal and sequentially outputs the latched burst data in response to another part of the internal address; and a detection means that detects whether the internal address reaches a burst address set corresponding to the last one of the internal burst cycles and generates the burst enable signal and the read enable signal for controlling the burst control circuit and the read control circuit based on a detection result.