Patent ID: 6981127

Claim:
Method for providing a plurality of aligned instructions from an instruction stream having variable-width instructions provided by a memory unit for execution within a pipelined microprocessor comprising a prefetch buffer, said method comprising the steps of: for each instruction cycle in which the microprocessor issues one or more instructions, in case said prefetch buffer contains invalid data: a) requesting an instruction stream from the memory unit and storing a plurality of instructions from said instruction stream in said prefetch buffer; b) storing a size value in said prefetch buffer indicating the number of unissued words remaining in the prefetch buffer; c) issuing a requested number of instructions from said memory unit and using the validity value to control an aligner that is coupled to the prefetch buffer and the memory unit to align the requested instructions; d) depending on the number and size of instructions that are issued in the instruction cycle, adjusting the size value in said prefetch buffer; e1) storing a validity value in said prefetch buffer indicating that said prefetch buffer contains valid data if not all instructions from said prefetch buffer have been issued; e2) storing a validity value in said prefetch buffer indicating that the prefetch buffer contains invalid data if all instructions from said prefetch buffer have been issued; in case said prefetch buffer contains valid data: f) issuing a requested number of instructions from said prefetch buffer and using the validity value and size value to control the aligner to align the requested instructions; g) depending on the number and size of instructions that are issued in the instruction cycle, adjusting the size value in said prefetch buffer, respectively; h) changing said validity value to indicate that the prefetch buffer contains invalid data if all instructions from said prefetch buffer have been issued.