Patent ID: 7200740

Claim:
An apparatus in a processor for speculatively performing a return instruction, comprising: a first call/return stack, configured for pushing thereon a plurality of return addresses of a corresponding plurality of call instructions in response to fetching from an instruction cache a plurality of cache lines predicted to include said corresponding plurality of call instructions, and for popping therefrom a first return address in response to fetching from said instruction cache a cache line predicted to include a return instruction, wherein said first return address is a top one of said plurality of return addresses simultaneously stored in said first call/return stack as a result of said pushing, wherein each of said plurality of return addresses is pushed onto said first call/return stack prior to decoding said corresponding call instruction; a second call/return stack, configured to provide a second return address in response to decoding said return instruction, subsequent to said first call/return stack popping therefrom said first return address; a comparator, coupled to said first and second call/return stacks, for comparing said first and second return addresses prior to the return instruction reaching an execution stage of a pipeline of the processor, wherein said execution stage is configured to finally resolve the return instruction; and control logic, coupled to said comparator, for controlling the processor to branch to said first return address, said control logic subsequently controlling the processor to branch to said second return address if said comparator indicates said first and second return addresses do not match.