Patent ID: 7752398

Claim:
An apparatus comprising: a memory circuit having a plurality of memory locations identified by addresses 0 through P−1, wherein P is a positive integer of at least four, said memory locations being arranged as N memory banks and each of said memory banks having at least two of said memory locations; and a logic circuit configured, for a particular integer pε{0, . . . , P−1}, a particular positive integer R≦N and a particular positive integer C≦N, to (i) receive a plurality of said addresses in parallel at a plurality of input ports and (ii) decode each of said addresses into a corresponding one of said memory banks, wherein (i) each address p+(c−1), for cε{1, . . . , C}, of said addresses decodes into a respective one of said memory banks for all 0≦p+(c−1)<P, and (ii) each address p+N(r−1) , for rε{1, . . . , R}, of said addresses decodes into a respective one of said memory banks for all 0p+N(r−1)<P.