Patent ID: 7369446

Claim:
A non-volatile memory having one or more high-voltage CMOS latches, each high-voltage CMOS latch comprising: a first CMOS inverter connected between a HV terminal and a ground terminal and having an input terminal and an output terminal; a second CMOS inverter connected between the HV terminal and a switch node C and having an input terminal and an output terminal; the input terminal of the second CMOS inverter and the output terminal of the first CMOS inverter are connected to a latch input node A for the high voltage latch circuit; a DATA IN input terminal connected to the latch input node A through a NMOS load input NMOS transistor, at a gate terminal of which is provided a DATA LOAD signal to turn on the NMOS load input NMOS transistor; the input terminal of the first CMOS inverter and the output terminal of the second CMOS output terminal are connected to a latch output node B; a switching circuit that is connected between all of the one or more switch nodes C of the one or more latches and the ground terminals; during an INPUT DATA LOAD mode of operation, the switching circuit provides a LOW impedance in series with the one or more second CMOS inverters when the HV terminal has a LOW voltage applied to it; and during a HIGH-VOLTAGE WRITE mode of operation, the switching circuit provides a HIGH impedance in series with the one or more second CMOS inverters to limit leakage current caused by punch-through when the HV terminal has a HIGH voltage applied to it.