Patent ID: 6907520

Claim:
A microprocessor comprising: an instruction buffer, wherein said instruction buffer is configured to store a plurality of instructions; a load prediction unit coupled to said instruction buffer, wherein said load prediction unit comprises a load prediction table with a plurality of entries and circuitry which supports load address prediction and new thread creation, wherein the plurality of entries in the load prediction table comprise a valid field, an instruction address field, an effective address field, a stride field, and a threshold field; wherein the load prediction unit is configured to: detect a first load instruction of said plurality of instructions; predict said first load instruction will miss, in response to detecting contents of a threshold field which corresponds to the first load instruction equals a threshold value; predict a first load address of said first load instruction; and identify a first instruction of a new thread in response to predicting said first detected load instruction will miss, wherein identifying said first instruction comprises comparing a destination register of said first detected load instruction with a destination register of instructions in said instruction buffer, wherein said destination register of said first instruction is the same register as said destination register of said first detected load instruction, wherein said instructions in said instruction buffer are subsequent in program order to said first detected load instruction; and a data cache coupled to said load prediction unit, wherein said data cache is configured to: receive said first load address; and fetch data corresponding to said first load address in response to detecting said data is not present in said data cache.