Patent ID: 7882324

Claim:
A system, comprising: a memory controller configured to issue a first command to a first memory device and a second command to a second memory device; the first memory device comprising first logic, and configured to: receive the first command issued to the first memory device, receive the second command issued to the second memory device, process the first command and the second command using the first logic of the first memory device, wherein the first logic includes command decoding logic and first read/write logic that communicates data between the first memory device and the memory controller, and initiate a communications exchange between the first memory device and the second memory device based on the second command; the second memory device comprising second logic including command decoding logic and second read/write logic, whereby the second logic is bypassed for purposes of processing the second command by the first logic of the first memory device; and synchronization circuitry configured to: determine a first time difference for the first memory device as a difference between the time when the first memory device receives the first command and the time when the first memory device asserts a first ready signal indicating the first memory device has data ready for output to the first read/write logic, determine a second time difference for the second memory device as a difference between the time when the second memory device receives the second command and the time when the second memory device asserts a second ready signal indicating the second memory device has data ready for output to the first read/write logic, determine a timing skew between the first memory device and the second memory device based on the first time difference and the second time difference, and introduce a delta time difference to at least one of the first ready signal and the second ready signal, wherein the delta time difference adjusts the timing skew.