Patent ID: 7548047

Claim:
A voltage regulator comprising: a first comparator adapted to receive a first reference voltage; a second comparator adapted to receive a second reference voltage; a counter configured to be set in a count-down mode if an output voltage signal generated by the voltage regulator raises above the first reference voltage, and to be set in a count-up mode if the output voltage signal falls below the second reference voltage, wherein said counter is not incremented or decremented if the output voltage signal falls between the first and second reference voltages; wherein said counter's count is decremented with each transition of a clock signal if said counter is set in the count-down mode and wherein said counter's count is incremented with each transition of the clock signal if said counter is set in the count-up mode; and a control circuit configured to receive the counter's count and to change, in accordance therewith, a duty cycle of a first signal to which the output voltage signal is responsive, wherein said clock signal has a frequency that is 1/N times a frequency of the first signal, and wherein N is greater than 1; wherein the control circuit comprises a duty cycle converter configured to vary one of charging time and discharging time of a capacitor in response to the counter's count, and the duty cycle converter comprises M legs, each leg adapted to supply a current to the capacitor when a first switch disposed in that leg is selected to be closed, each leg further adapted to sink a current from the capacitor when a second switch disposed in that leg is selected to be closed, wherein said first and second switches in each leg are adapted so as not to be closed concurrently.