Patent ID: 7991610

Claim:
A hardware implemented compression unit for compression of parameters, the parameters including a first set of parameters including a representation of a first portion of an original signal, the parameters further including a second set of parameters including a representation of a second portion of the original signal, the second portion neighboring the first portion, comprising: a supplier for supplying a first tuple and all remaining tuples of a first sequence of tuples using only tuples having parameters from one single set of parameters, and to supply a first tuple and all remaining tuples of a second sequence of tuples using only tuples having at least one parameter from the first set of parameters and at least one parameter from the second set of parameters, wherein the first portion is a frequency range or a time frame, or the second portion is a frequency range or a time frame, wherein the supplier is configured to supply: the first tuple of the first sequence consisting of an odd number of neighboring parameters of the representation of the original signal from one set of parameters; and the first tuple of the second sequence consisting of a majority of neighboring parameters of the representation of the original signal from one set of parameters and of a minority of neighboring parameters of the representation of the original signal from the other set of parameters, wherein the majority of parameters is alternately taken from the first and from the second set of parameters for consecutive tuples of the second sequence of tuples; a bit estimator for estimating a number of bits necessary to encode the sets of parameters using the first sequence of tuples and to encode the sets of parameters using the second sequence of tuples, based on an encoding rule; and a provider for providing encoded blocks, the provider being operative to provide the encoded blocks using the sequence of tuples resulting in a lower number of bits, and for providing a single sequence indication for one encoded block indicating the sequence of tuples from which the encoded blocks are derived; wherein at least one component selected from the group consisting of the supplier, the bit estimator, and the provider is implemented in hardware.