Patent ID: 8143173

Claim:
A method for manufacturing a semiconductor device, comprising: (a) forming a stress relaxation layer on a first surface of a semiconductor substrate on which an electrode is formed; (b) forming a wiring line so as to cover the electrode and the stress relaxation layer after the step (a), wherein the step (b) includes: (b-1) forming a conductive film so that the conductive film contacts and completely covers the stress relaxation layer and the electrode; (b-2) forming a plating resist layer on the conductive film so that the plating resist layer has a first opening that exposes a first part of the conductive film; (b-3) forming a metal layer on the first part of the conductive film by electrolytic plating by applying a current to the conductive film; (b-4) removing the plating resist layer; and (b-5) etching a second part of the conductive film where the metal layer is not formed; (c) forming a first resin precursor layer as a solder resist layer on the wiring line after the step (b); (d) forming a second resin precursor layer as a protective layer on a second surface opposite to the first surface of the semiconductor substrate after the step (c), wherein the step (d) includes curing the second resin precursor layer while the first resin precursor layer is maintained in an uncured state, and wherein the step (d) is performed with a supporter on which the semiconductor substrate is placed so that the solder resist layer makes direct contact with the supporter; (e) providing a second opening in the solder resist layer to expose the wiring line; and (f) forming an external terminal made of solder in the second opening after the step (d), wherein: the first resin precursor layer is patterned and cured after the step (d).