Patent ID: 8159479

Claim:
A pixel circuit for driving an electro-optic element with a luminance changing according to a flowing current, comprising: a drive transistor forming a current supply line between a first terminal and a second terminal and controlling a current flowing through said current supply line in accordance with the potential of a control terminal; a first node; a power source voltage source; two reference power sources located on to opposite sides of the pixel circuit from each other along a first direction, each of the reference power sources including circuitry configured to generate a reference power voltage; a reference power source interconnect; a first circuit for connecting said first node to said reference power source interconnect for making a potential of said first node change to a fixed potential while said electro-optic element is not emitting light; a data line through which a data signal in accordance with luminance information is supplied; a second node; a first control line; a second control line; a third control line; a pixel capacitance element connected between said first node and said second node; and a first switch between said data line and said second node and controlled in conduction by said first control line, wherein said current supply line of the drive transistor, said first node, and said electro-optic element are connected in series between said power source voltage source and reference potential, the power source voltage source interconnect and said reference power source interconnect are laid out in a second direction perpendicular to the first direction so as not to have intersecting parts, said drive transistor comprises a field effect transistor with a drain connected to said power source voltage source or reference potential and a gate connected to said second node, and said first circuit includes a second switch connected between a source of said field effect transistor and said electro-optic element and controlled in conduction by said second control line and a third switch connected between said first node and said reference power source interconnect and controlled in conduction by said third control line.