Patent ID: 8558301

Claim:
A semiconductor device, comprising: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures, wherein the element isolation insulating layer includes at least one of SiO 2 , SiN, and SiON; wherein the upper insulating layer is an oxide containing Al, and at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si; and wherein respective lengths L charge , L top , and L gate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “L charge <L top and L gate <L top ”; and wherein a ratio N Al /N M of the number N Al of Al to the number N M of metal M is equal to or higher than a ratio which suppresses crystallization of an oxide of the metal M by operation of Al and is equal to or lower than a ratio which suppresses crystallization of Al 2 O 3 by operation of the metal M.