Patent ID: 8759878

Claim:
A nitride semiconductor device comprising: a first semiconductor layer including a nitride semiconductor; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a band gap not less than a band gap of the first semiconductor layer, and the second semiconductor layer including a nitride semiconductor; a third semiconductor layer provided on the second semiconductor layer, the third semiconductor layer being GaN; a fifth semiconductor layer provided on the third semiconductor layer and having an interspace over a part of the third semiconductor layer, the fifth semiconductor layer including an n-type nitride semiconductor; a fourth semiconductor layer provided on the fifth semiconductor layer, the fourth semiconductor layer having a band gap not less than a band gap of the second semiconductor layer, and the fourth semiconductor layer including a nitride semiconductor; a first electrode provided on the third semiconductor layer; a second electrode provided on one side of the first electrode on the fourth semiconductor layer and joined to the fourth semiconductor layer by ohmic junction; and a third electrode provided on another side of the first electrode on the fourth semiconductor layer and joined to the fourth semiconductor layer by ohmic junction, wherein the second, third, and fourth semiconductor layers cause a two-dimensional electron gas to be formed at an interface of the first semiconductor layer and the second semiconductor layer if a thickness of any one of the three, or a combined thickness of the three, is greater than a predetermined thickness, and the thicknesses of the second and third semiconductor layers are such that the second and third semiconductor layers do not cause a two-dimensional electron gas to be formed at an interface of the first semiconductor layer and the second semiconductor layer, and a thickness of the fourth semiconductor layer is such that a two-dimensional electron gas is caused to be formed at a portion of the interface of the first semiconductor layer and the second semiconductor layer that is underneath the fourth semiconductor layer.