Patent ID: 8198684

Claim:
A power semiconductor device with drain voltage protection, comprising: a semiconductor substrate with a first conductive type, a first device region and a second device region being defined in the semiconductor substrate, a upper surface of the semiconductor substrate having at least a first trench and a second trench, wherein the first trench is disposed in the first device region, and the second trench is disposed in the second device region; at least a trench gate transistor device disposed in the first device region, wherein the trench gate transistor device comprises: a first insulating layer disposed on a surface of the first trench; a gate conductive layer disposed in the first trench; a doped base region with a second conductive type, the doped base region disposed in the semiconductor substrate at a side of the first trench; and a source doped region with the first conductive type, the source doped region disposed in the doped base region of the first device region; a source metal layer disposed on the upper surface of the semiconductor substrate and electrically connected to the source doped region; a gate metal layer disposed on the upper surface of the semiconductor substrate and electrically connected to the gate conductive layer; a drain metal layer disposed on a lower surface of the semiconductor substrate; and at least a trench ESD protection device disposed in the second trench of the second device region, the trench ESD protection device comprising a first doped region, a second doped region, and a third doped region, and the first doped region, the second doped region and the third doped region being disposed in a same semiconductor layer, wherein the first doped region is disposed between the second doped region and the third doped region, the second doped region is electrically connected to the drain metal layer, and the third doped region is electrically connected to the gate metal layer.