Patent ID: 8565020

Claim:
A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells respectively having a gate connected to one of the word lines; a word line driver configured to drive voltages of the word lines; and a sense amplifier configured to detect data of the memory cells via the bit lines, wherein the memory cells are connected in series between one of the respective bit lines and a source to constitute a cell string, the word line driver increases a verification voltage of any of non-selected word lines connected to non-selected memory cells in the cell string at a time of a verify operation in a certain writing loop of a writing stage, to be higher than a previous verification voltage of the non-selected word line at a time of a verify operation in a previous writing loop of the writing stage, the writing stage comprises a plurality of writing loops, and the writing loops respectively comprises a write operation to write data in a selected memory cell in the cell string and a verify operation to verify that the data are written in the selected memory cell.