Patent ID: 6897504

Claim:
A structure of a salicided MOS device and a one-sided salicided MOS device, comprising: a semiconductor substrate; a first MOS device and a second MOS device formed on the substrate, wherein the first MOS device comprises a first gate structure formed on the substrate, first and second doped regions formed in the substrate, and the second MOS device comprises a second gate structure formed on the substrate, and third and fourth doped regions formed in the substrate; a spacer formed on a sidewall of the second gate structure, wherein the spacer is located on part of the fourth doped region; a conformal insulation layer formed over the fourth doped region and a side of the second gate structure near the fourth doped region, wherein part of the conformal insulation layer overlies the spacer; a salicided layer formed on the first gate structure, the first doped region, the second doped region, the second gate structure and the third doped region but not the fourth doped region; and a capacitor electrically coupled to the fourth doped region, wherein part of the conformal insulation layer overlies the capacitor.