Patent ID: 8207976

Claim:
A circuit comprising: an output buffer comprising an input and an output; a data interface for transmitting and receiving data, the data interface being coupled to the output of the output buffer; a command/address interface coupled to the input of the output buffer; a memory core coupled to the input of the output buffer; a second output buffer comprising an input and an output, the output of the second output buffer being coupled to the data interface or to a further output pin; an EDC circuit having an output coupled to the input of the second output buffer; and a controller circuit adapted to cause data stored within the output buffer to be output to the data interface upon reception of a first signal, further adapted to cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal so that the data is stored within the output buffer, further adapted to cause provision of data received at the command/address interface via an address portion thereof to the input of the output buffer upon reception of a third signal so that the data is stored within the output buffer, further adapted to cause data which is stored within the second output buffer to be output to the data interface or the further output pin, further being adapted to cause data which is provided by the EDC circuit to be stored within the second output buffer, and further being adapted to cause data which is received at the command/address interface to be stored within the second output buffer.