Patent ID: 7396717

Claim:
A method of forming a MOS transistor, comprising: providing a substrate having a gate thereon, a source region and a drain region therein with a channel region under the gate therebetween; thereafter pre-amorphizing the source region and the drain region to form amorphized regions; thereafter performing a first ion implantation to implant a first dopant in the source region and the drain region to form a first doped region; thereafter forming at least a spacer on the sidewalls of the gate; thereafter performing a second ion implantation to implant a second dopant in the source region and the drain region to form a second doped region; thereafter annealing the source region and the drain region to activate the first dopant, regrow the amorphized regions to a substantially crystalline form, and form a junction profile; and performing a co-implantation process, after pre-amorphizing the source region and the drain region and before annealing the source region and the drain region, to implant an co-implant in the source region and the drain region, wherein the co-implant comprises C x H y + or (C x H y ) n + , wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000, and the first dopant comprises B, BF 2 ,B w H z + , or (B w H y ) m + , wherein w is a number of 2 to 30, z is a number of 2 to 40, and m is a number of 10 to 1000.