Patent ID: 8519934

Claim:
A gate driver circuit usable in a liquid crystal display (LCD), comprising: (a) a gate IC internal circuit for generating scanning signals; (b) a gate IC output buffer circuit for modifying said scanning signals according to a linear function; and (c) a gate line loading circuit having N channels for respectively receiving said modified scanning signals from said gate IC output buffer circuit, N being an integer greater than 1, wherein said gate IC output buffer circuit has N sets of circuit components, each circuit component set having an output node connected to a corresponding channel of said gate line loading circuit for outputting a corresponding one of said modified scanning signals to said corresponding channel of said gate line loading circuit, and comprising: (i) a PMOS transistor having a source end coupled to a VGG voltage, a gate end receiving signal from said gate IC internal circuit, and a drain end connected to said corresponding channel of said gate line loading circuit, (ii) a first NMOS transistor having a source end coupled to a VEE voltage, a gate end receiving signal from said gate IC internal circuit, and a drain end connected to said drain end of said PMOS transistor, and (iii) a second NMOS transistor having a source end, a gate end, and a drain end connected to said drain end of said PMOS transistor, wherein said source end of said second NMOS transistor of each of said N sets of circuit components is connected to a common node that is not directly connected to any one of said output nodes of said N sets of circuit components, and wherein said common node has a Vbias voltage.