Patent ID: 7898837

Claim:
A process of reading a programmable data storage component of an integrated circuit, comprising: cycling a bias on a first plate node coupled to a first data ferroelectric capacitor of said programmable data storage component, so as to recall a first programmed data value to a first state node and a second programmed data value to complementary second state node of a state circuit of said programmable data storage component, said first data ferroelectric capacitor being coupled to said first state node, and one of said first state node and said second state node being coupled to a second ferroelectric capacitor; applying power to said state circuit so that said first and second programmed data values stabilize on said first state node and said second state node; reading said first and second programmed data values from said state circuit; and removing power from said state circuit prior to any subsequent read or write step on said state circuit, so that a polarization orientation of said first data ferroelectric capacitor is preserved.