Patent ID: 8354347

Claim:
A method for forming interconnections in an integrated circuit (IC) comprising: providing a substrate with a trench isolation region comprising an isolation material, the trench isolation region having a planar top surface, and a circuit region having a circuit component with a contact region, wherein the contact region is on a surface of the substrate; forming an etch stop stack over the substrate, covering the circuit component and the substrate, the etch stop stack comprises primary and secondary etch stop layers, the secondary etch stop layer includes a bottom surface which contacts the contact region on the surface of the substrate and the planar top surface of the trench isolation region and the primary etch stop layer is disposed above a top surface of the secondary etch stop layer, wherein the secondary etch stop layer, which is below the primary etch stop layer, comprises a high k material which is different from the isolation material of the trench isolation region; forming an interlayer dielectric (ILD) layer over the etch stop stack; and patterning the ILD layer to form a contact via therein to the contact region, wherein the patterning the ILD layer comprises performing a first anisotropic etch comprising a first etch chemistry, wherein the first anisotropic etch etches the ILD and primary etch stop layers above the secondary etch stop layer by the first anisotropic etch and stops at about the top surface of the secondary etch stop layer, and performing a second etch comprising a second etch chemistry after performing the first anisotropic etch to remove exposed portion of the secondary etch stop layer to expose the contact region, wherein removing the exposed portion of the secondary etch stop layer can be achieved with high selectivity to materials, including the isolation material of the trench isolation region, disposed below the secondary etch stop layer.