Patent ID: 8758984

Claim:
A method of forming gate conductor structures, comprising: providing a substrate having thereon a gate electrode layer comprising a first layer and a second layer overlying the first layer; forming a multi-layer hard mask overlying the gate electrode layer, the multi-layer hard mask comprising a first hard mask, a second hard mask overlying the first hard mask, and a third hard mask overlying the second hard mask; forming a photoresist pattern on the multi-layer hard mask; performing a first etching process to etch the third hard mask, using the photoresist pattern as a first etch resist mask, thereby forming a patterned third hard mask; performing a second etching process to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist mask, thereby forming a patterned first hard mask, wherein the patterned third hard mask is totally consumed during the second etching process; performing a third etching process to etch the second layer of the gate electrode layer, using the patterned first hard mask as a third etch resist mask, thereby forming a patterned second layer; forming a patterned spacer encapsulating the patterned first hard mask and the patterned second layer, wherein the patterned spacer also covers a top surface of the patterned first hard mask; and using the patterned spacer and the patterned first hard mask as a fourth etch resist mask, performing a fourth etching process to etch the first layer of the gate electrode layer in a self-aligned manner.