Patent ID: 8392488

Claim:
An integrated circuit comprising: a plurality of regions of logic array block circuitry, each of which includes a plurality of subregions of logic module circuitry, each of the subregions being capable of producing (1) a redundant form sum bit signal from addition of a respective group of three input bit signals, and (2) a redundant form carry bit signal from said addition, and each of the subregions including ripple carry adder circuitry for adding (a) a ripple carry bit signal output by a next less arithmetically significant ripple carry adder circuitry, (b) the redundant form sum bit signal produced by said each subregion, and (c) the redundant form carry bit signal produced by a next less arithmetically significant subregion; and each of the regions including (i) a first register for registering the ripple carry bit signal having greatest arithmetic significance of the ripple carry bit signals of said each region, and (ii) a second register for registering the redundant form carry bit signal having greatest arithmetic significance of the redundant form carry bit signals of said each region.