Patent ID: 7790577

Claim:
A method, comprising: (a) for one or more integrated circuit chips of an array of integrated circuit chips on a semiconductor substrate, forming a first or next wiring level over said substrate; (b) for predetermined first or next wiring levels of each integrated circuit chip of said one or more integrated circuit chips, forming a corresponding first or next void in said first or next wiring level, said first or next void extending in a continuous ring parallel and proximate to a perimeter of said integrated circuit chip, a void of a subsequently formed wiring level stacked directly over but not contacting a void of a previously formed level; (c) repeating steps (a) and (b) multiple times to form in each integrated circuit chip of said one or more integrated circuit chips a respective crack stop comprising a stack of voids; and after (c), (d) dicing said array of integrated circuit chips into individual integrated circuit chips, each individual integrated circuit chip of said one or more integrated circuit chips including a respective crackstop.