Patent ID: 7073100

Claim:
A method of testing an embedded DRAM, comprising: generating a test data pattern in a processor based built-in self test system, said built in self test system coupled to said embedded DRAM on a same integrated circuit chip, said embedded DRAM comprised of DRAM blocks; for each DRAM block of said embedded DRAM, performing a write of said test data pattern into said DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from said DRAM block; wherein for each DRAM block, said performing said write of said test data pattern into said DRAM block is performed before said performing said pause for said predetermined period of time, and said performing said read of said resulting data pattern from said DRAM block is performed after said performing said pause for said predetermined period of time; wherein at least a portion of said pause for said predetermined period of time of two or more said DRAM blocks overlap in time; and for each DRAM block comparing a data pattern based on said test data pattern to said resulting data pattern.