Patent ID: 6861882

Claim:
A semiconductor integrated circuit comprising: a first flip-flop circuit which has an input terminal supplied with a first input signal and which has a clock signal input terminal supplied with a first control signal which is generated for a half period of a clock signal when the first input signal is supplied to the first flip-flop circuit, said first flip-flop circuit holding said first input signal in response to said first control signal; and a combination circuit having first, second and third input terminals, the first input terminal connected to an output terminal of said first flip-flop circuit, the second input terminal supplied with a second input signal, and the third input terminal supplied with a second control signal which is generated for one period of a clock signal when the first control signal is supplied to the first flip-flop circuit, said combination circuit being set to an active state in response to said second control signal, and holds data according to a signal fed from said first flip-flop circuit and the second input signal supplied to the second input terminal.