Patent ID: 7919390

Claim:
A method for fabricating an isolation structure in a memory device, the method comprising: forming a first trench in a cell region of a semiconductor substrate and forming a second trench in a peripheral region of the semiconductor substrate; forming a liner layer comprising a silicon nitride layer on the first and second trenches by forming a wall oxide layer by oxidizing surfaces of the first and second trenches, depositing the silicon nitride layer on the wall oxide layer, depositing a silicon oxide layer on the silicon nitride layer, and removing a portion of the silicon oxide layer disposed at the second trench when removing the portion of the first isolation layer filling the second trench; forming a first isolation layer comprising a flowable dielectric layer on the liner layer to fill the first and second trenches; removing a portion of the first isolation layer filling the second trench to expose the silicon nitride layer disposed on the second trench; oxidizing a portion of the exposed silicon nitride layer disposed on the second trench; and forming a second isolation layer to fill the second trench.