Patent ID: 8473934

Claim:
A method of determining an optimal mapping of application code, enabling efficient execution of the code on a digital system comprising a plurality of computation units and a plurality of memories arranged in a hierarchy connected by a network, the method comprising: loading a representation of application code, describing the functionality of the application, wherein the code comprises data access instructions on array signals, the representation of the code being partitioned in a plurality of code threads and the representation comprising information on data access dependencies between the code threads; determining for at least one array signal and for at least one data access instruction on the array signal a graph having a plurality of data groupings, the data groupings comprising portions of the array signals that are copied from one layer of memory to a lower layer of memory within the hierarchy of memories, the one layer of memory consumes more power than the lower layer of memory, and the graph indicating for each data grouping of the plurality of data groupings, whether the data grouping is assignable to more than one of the code threads; evaluating combinations of the data groupings using an evaluation criterion; and selecting the combination of the data groupings with an optimum evaluation criterion within a pre-determined tolerance, and wherein the selection defines the optimal mapping of data groupings within the hierarchy of memories, the selection is based on a tradeoff between size of a data grouping and energy costs for copying the data grouping from one layer of memory to a lower layer of memory, while taking into account inter-thread data access dependencies and cost of inter-thread synchronization when a data grouping is assignable to more than one of the code threads, the selection resulting in a memory reuse that reduces power consumption of the digital system.