Patent ID: 7642607

Claim:
A semiconductor device comprising: a substrate; a gate structure overlying the substrate, the gate structure comprising a gate dielectric over the substrate and a gate electrode over the gate dielectric; a lightly doped drain/source (LDD) region substantially aligned with an edge of the gate structure; a sidewall spacer on a sidewall of the gate structure; a doped source/drain region formed into the substrate spaced apart from the sidewall spacer having a depth into the substrate substantially greater than about 30 nanometers; a recessed region having a recess depth of substantially less than about 30 Å in the substrate, wherein at least a portion of the recessed region is under the sidewall spacer; and a silicon alloy region extending into and contained by the doped source/drain region and adjacent the recessed region, wherein the silicon alloy region has a substantially greater lattice constant than the substrate, and a thickness of substantially greater than about 30 nm; wherein the silicon alloy region is spaced apart from the LDD region by a portion of the doped source/drain region.