Patent ID: 8072409

Claim:
A liquid crystal display (LCD), comprising: (a) a common electrode; (b) a plurality of scanning lines, {G n }, n=1, 2, . . . , N, N being an integer greater than zero, spatially arranged along a row direction; (c) a plurality of data lines, {D m }, m=1, 2, . . . , M, M being an integer greater than zero, spatially arranged crossing the plurality of scanning lines {G n } along a column direction perpendicular to the row direction; (d) a plurality of pixels, {P n,m }, spatially arranged in the form of a matrix, each pixel row, defined between two neighboring scanning lines G n and G n+1 , having an auxiliary common electrode ACE n , each pixel P n,m , defined between two neighboring scanning lines G n and G n+1 and two neighboring data lines D m and D m+1 , comprising: (i) a pixel electrode; (ii) a transistor, T 0 , having a gate, a source and a drain electrically coupled to the scanning line G n , the data line D m and the pixel electrode, respectively; (iii) a liquid crystal capacitor, Clc, electrically coupled between the pixel electrode and the common electrode; and (iv) a charge storage capacitor, Cst, electrically coupled between the pixel electrode and the auxiliary common electrode ACE n , and (e) a plurality of common voltage driving circuits {CT n }, each common voltage driving circuit CT n , electrically coupled between the scanning line G n and the corresponding auxiliary common electrode ACE n , comprising: a first transistor, T 1 , a second transistor, T 2 , a third transistor, T 3 , and a fourth transistor, T 4 , each transistor having a gate, a source and a drain, wherein the gate of each of the first transistor T 1 , the second transistor T 2 and the third transistor T 3 is electrically coupled to the gate scanning line G n , and the gate of the fourth transistor T 4 is electrically coupled to a fourth voltage, SWC n , that is inverse to a corresponding scanning signal, g n to be applied to the gate scanning line G n .