Patent ID: 7563649

Claim:
A method for manufacturing a pin grid array for electronic chip packaging, comprising the steps of: (a) creating a frame comprising a multiplicity of flattened wires integrally formed therewith, each having a longitudinal axis, and a multiplicity of corresponding electrically conducting frame pads, each flattened wire electrically connecting to a corresponding flattened pin and to a corresponding frame pad, and all disposed within the same plane; (b) rotating each of the flattened wire approximately 90 degrees about its longitudinal axis so that it remains substantially within the plane of the frame, so that each pin is disposed at an angle normal to the plane of the frame; (c) disposing the frame in proximity to a chip comprising chip pads, aligning the chip pads with the corresponding frame pads; (d) electrically connecting each chip pad to the corresponding frame pad; and (e) encapsulating the frame and chip with the pins extending through the encapsulation, so that the pins may be electrically connected to another electronic or electrical assembly.