Patent ID: 8599983

Claim:
A clock and data recovery circuit, comprising: a first transmission line including a plurality of first segments of a first predetermined length, the first transmission line being configured to facilitate propagation of a clock signal through the plurality of first segments to provide a plurality of delayed clock signals corresponding to propagation of the clock signal through the plurality of first segments; a second transmission line including a plurality of second segments of a second predetermined length, the second transmission line being configured to facilitate propagation of a data signal including a serial bit stream through the plurality of second segments to provide a plurality of delayed data signals corresponding to propagation of the data signal through the plurality of second segments; and a first sampling circuit configured to sample a first delayed data signal from among the plurality of delayed data signals at a sampling rate corresponding to a first delayed clock signal from, among the plurality of delayed clock signals, wherein a time to propagate the clock signal through the first predetermined length and a time to propagate the data signal through the second predetermined length each correspond to a partial period of a transmission bit time within the serial bit stream.