Patent ID: 7257723

Claim:
A system for optimizing power for an embedded system, the system comprising: means for partitioning a single chip implementation of the embedded system into power domains, wherein at least one power domain includes a plurality of critical paths; means for selecting at least one critical path in each power domain; and means for adjusting voltages of the power domains based on timing margins associated with the critical paths, wherein the means for adjusting includes: a time delay circuit for each critical path; means for comparing an output signal of each critical path to propagated signals associated with stages on each time delay circuit, thereby generating a timing margin vector for each critical path; and means for generating a combined result vector based on the timing margin vectors, wherein the means for comparing includes: an XOR gate for receiving the output signal of the critical path and one of the propagated signals; and means for storing a designation of whether the output signal and the propagated signal are different values, wherein the designations from the stages form the timing margin vector, wherein the means for storing includes: an OR gate for receiving an output of the XOR gate; and a flip-flop for receiving an output of the OR gate and providing an output to another input terminal of the OR gate.