Patent ID: 8122413

Claim:
A method for designing an integrated circuit, the method comprising: mapping, by a computing apparatus, a gate-level netlist onto a target implementation architecture of at least a portion of an integrated circuit including implementing a storage function of the gate-level netlist via a respective logic block having integral design-for-testability (DFT) functionality, wherein said logic block comprises: a D-type flip-flop including a first output, a first data input, and a first clock input, wherein the first data input is selectively coupled to one of a user data input or a scan data input, and wherein the first clock input is selectively coupled to one of a core clock input or a scan clock input; a D-type latch having a second output, a second data input coupled to a third output of the logic block, and a third input coupled to an enable signal; and an output selector configured to receive the first output and the second output and to selectively output the third output based on the enable signal.