Patent ID: 7955921

Claim:
A method of fabricating a structure including an n-type field effect transistor (“NFET”) and a p-type field effect transistor (“PFET”), comprising: a) defining an NFET gate, a PFET gate, source regions and drain regions, each of the NFET gate and the PFET gate including a semiconductor element, the source and drain regions being disposed adjacent to the NFET gate and the PFET gate; b) forming a dielectric stressor layer overlying edges of the NFET gate and PFET gate, the source regions and the drain regions, the dielectric stressor layer having an opening exposing tops of the NFET gate and the PFET gate, the dielectric stressor layer having a compressive stressor layer at least overlying the source region of the PFET, overlying the drain region of the PFET and overlying the NFET; c) removing portions of at least one of the semiconductor elements of the NFET gate and PFET gate selectively with respect to the dielectric stressor layer to reduce a thickness of the at least one semiconductor element; and d) depositing and reacting a metal with the semiconductor elements of the NFET gate and the PFET gate to form silicide gates of the NFET and of the PFET, wherein, at least after step (d) is performed, the dielectric stressor layer applies a compressive stress having a magnitude of at least 1 GPa to a channel region of the PFET; (e) removing a portion of the compressive stressor layer overlying the NFET after step (d); and forming a second dielectric stressor layer overlying the NFET, the second dielectric stressor layer having a tensile stress.