Patent ID: 8316071

Claim:
A multiplier-adder comprising: a multiplier having first and second inputs for receiving first and second operands, a first output for providing a sum signal, and a second output for providing a carry signal; a biased addend generator having first and second inputs for receiving sign bits of said first and second operands, a third input for receiving a third operand, a first output for providing a biased addend signal, and a second output for providing a signal representative of a sign of a product of said first and second operands, wherein said biased addend signal includes the same number of bits as said sum and carry signals; an adder having first and second inputs coupled to said first and second outputs of said multiplier, a third input for receiving said biased addend signal, and an output for providing a signal representative of a sum of said first, second, and third inputs; a multiplexer having a first input coupled to said first output of said adder, a second input for receiving a saturated minimum value, a third input for receiving a saturated maximum value, a control input, and an output for providing a multiply-add result with saturation signal; and select logic having a first input coupled to said second output of said bias generator and a second input for receiving a signal representative of a sign of said sum, and an output coupled to said control input of said multiplexer.