Patent ID: 7639764

Claim:
A memory controller comprising: a command decoder operable to receive a multi-bit command in accordance with a first clock domain; and synchronization logic operable to synchronize the multi-bit command to a second clock domain that is different from the first clock domain, wherein the synchronization logic includes, a first synchronization flop; a second synchronization flop coupled to the first synchronization flop, the first and second synchronization flops operable to prevent metastability associated with synchronizing the multi-bit command to the second clock domain; a comparator operable to compare a value of the multi-bit command in the first synchronization flop to a value of the multi-bit command in the second synchronization flop to determine if all bits of the multi-bit command have transferred to the second clock domain; and a command lookup table operable to determine whether the multi-bit command is a valid command.