Patent ID: 8415741

Claim:
A semiconductor device comprising: a substrate having first and second active regions that are isolated by a device isolation; first and second unit transistors disposed in the first active region; third and fourth unit transistors disposed in the second active region; and an interconnection layer extending over the first, second, third and fourth unit transistors and crossing over the device isolation, the first unit transistor comprising a first pillar providing a first channel region, a first gate insulating film formed on a side surface of the first pillar, a first gate electrode formed on the first gate insulating film, a first upper diffusion region disposed near a top part of the first pillar, a first lower diffusion region disposed near a bottom part of the first pillar, a first contact plug provided in contact with the first upper diffusion region, the second unit transistor comprising a second pillar providing a second channel region, a second gate insulating film formed on a side surface of the second pillar, the first gate electrode formed on the second gate insulating film, a second upper diffusion region disposed near a top part of the second pillar, the first lower diffusion region disposed near a bottom part of the second pillar, a second contact plug provided in contact with the second upper diffusion region, the third unit transistor comprising a third pillar providing a third channel region, a third gate insulating film formed on a side surface of the third pillar, a second gate electrode formed on the third gate insulating film, a third upper diffusion region disposed near a top part of the third pillar, a second lower diffusion region disposed near a bottom part of the third pillar, a third contact plug provided in contact with the third upper diffusion region, the fourth unit transistor comprising a fourth pillar providing a fourth channel region, a fourth gate insulating film formed on a side surface of the fourth pillar, the second gate electrode formed on the fourth gate insulating film, a fourth upper diffusion region disposed near a top part of the fourth pillar, the second lower diffusion region disposed near a bottom part of the fourth pillar, a fourth contact plug provided in contact with the fourth upper diffusion region, the first lower diffusion region performing as a common lower diffusion region for the first and second unit transistors in the first active region, the second lower diffusion region performing as a common lower diffusion region for the third and fourth unit transistors, the interconnection layer having a first end and a second end, the first end being in contact with the second contact plug and the second end being in contact with the third contact plug so that the second upper diffusion region and the third upper diffusion region are electrically connected in series to each other.