Patent ID: 7176071

Claim:
A semiconductor device fabrication method, comprising: forming an insulating layer on a substrate; forming a semiconductor layer on a part of the insulating layer, the semiconductor layer having a top surface, side surfaces, and a bottom surface, the bottom surface being in contact with the insulating layer; forming a diffusion region in the semiconductor layer; etching the insulating layer, using the semiconductor layer as an etching mask, by an etching process that etches laterally to remove at least part of the insulating layer below the diffusion region, thereby exposing part of the bottom surface of the semiconductor layer; depositing an etch stop film on at least the top surface and the side surfaces of the semiconductor layer, the etch stop film also replacing the part of the insulating layer that was removed from below the semiconductor layer; etching the etch stop film to expose the top surface of the semiconductor layer, leaving the etch stop film covering the side surfaces and said part of the bottom surface of the semiconductor layer; depositing an interlayer dielectric film on at least the exposed top surface of the semiconductor layer; etching a contact hole in the interlayer dielectric film above the diffusion region, using an etchant that etches the interlayer dielectric film more rapidly than the etch stop film; and filling the contact hole with a conductive material, wherein the deposited etch stop film also covers the top surface and the side surfaces of the gate electrode, and said etching the etch stop film includes removing the etch stop film from the top surface of the gate electrode, leaving the side surfaces of the gate electrode covered by sidewalls.