Patent ID: 8237475

Claim:
A circuit comprising: a first locked loop operable to control a first delay in the first locked loop; and a phase offset circuit operable to delay an input signal by a second delay, wherein the phase offset circuit comprises a second locked loop, wherein the second locked loop comprises first and second variable delay circuits and a phase detector operable to compare a signal delayed by the first variable delay circuit to a signal delayed by the second variable delay circuit for adjusting a delay of the first variable delay circuit, and wherein the second variable delay circuit has a fixed delay, wherein the phase offset circuit is operable to adjust the second delay provided to the input signal based on changes the first locked loop provides to the first delay and based on changes the second locked loop provides to the delay of the first variable delay circuit, and wherein the phase offset circuit is operable to compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.