Patent ID: 8853860

Claim:
A transistor for reduced device parasitics and improved thermal impedance, comprising: a base input terminal for receiving an input current; a collector output terminal for outputting an output current; a plurality of first metal layers positioned along a first x-y plane and including a metal layer connected to the base input terminal and another metal layer connected to the collector output terminal; a plurality of first interconnect metal vias positioned below one or more of the plurality of first metal layers and connected to one or more of the plurality of first metal layers; a plurality of second metal layers positioned along a second x-y plane and below one or more of the plurality of first interconnect metal vias, and connected to one or more of the plurality of first interconnect metal vias; a plurality of second interconnect metal vias positioned below one or more of the plurality of second metal layers and connected to one or more of the plurality of second metal layers; a plurality of third metal layers positioned along a third x-y plane and below one or more of the plurality of second interconnect metal vias and connected to one or more of the plurality of second interconnect metal vias; a plurality of third interconnect metal vias positioned below one or more of the plurality of third metal layers and connected to one or more of the plurality of third metal layers; a plurality of fourth metal layers positioned along a fourth x-y plane and below one or more of the plurality of third interconnect metal vias and connected to one or more of the plurality of third interconnect metal vias; a plurality of fourth interconnect metal vias positioned below one or more of the plurality of fourth metal layers and connected to one or more of the plurality of fourth metal layers; one or more transistor metal layers positioned along a fifth x-y plane and below one or more of the fourth interconnect metal vias and connected to one or more of the fourth interconnect metal vias; a transistor semiconductor portion of the transistor connected to the one or more transistor metal layers; a transistor base-contact metal positioned along a transistor base x-y plane that is below one or more of the plurality of fourth interconnect metal vias, and connected to one or more of the plurality of fourth interconnect metal vias and the transistor semiconductor portion, the transistor base-contact metal having a width along an x-axis and an opening; and a first metal emitter finger positioned within the opening of the transistor base-contact metal and spaced apart from the transistor base-contact metal, the first metal emitter finger having a width along an x-axis that is shorter than the width of the transistor base-contact metal.