Patent ID: 8374247

Claim:
A system for image processing, the system comprising: one or more circuits configured to: generate subsampled image frames from input image frames, the generated subsampled image frames corresponding to hierarchical pixel resolution levels, a plurality of the hierarchical pixel resolution levels corresponding to subsampling levels differing from one another in subsampled pixel resolution; for one of the subsampling levels at a first subsampled pixel resolution: select a first image processing block of a first image frame and a second image processing block of a current image frame, the second image processing block selected based on a first correlation computation between the first image processing block and first plural pixel blocks of the current image frame; interpolate pixel locations of the first and second image processing blocks to a first subpixel resolution; and determine first motion vectors based on the interpolated versions of the first and second image processing blocks; and for another of the subsampling levels at a second subsampled pixel resolution greater than the first subsampled pixel resolution: determine locations of a third image processing block and a fourth image processing block of the first and current image frames, respectively, based on the determined first motion vectors; select the third image processing block and the fourth image processing block, the fourth image processing block based on a second correlation computation between the third image processing block and second plural pixel blocks of the current image frame; interpolate pixel locations of the third and fourth image processing blocks to a second subpixel resolution; determine second motion vectors based on the interpolated versions of the third and fourth image processing blocks; and provide the second motion vectors for processing at another of the hierarchical pixel resolution levels.