Patent ID: 6915410

Claim:
A system for producing an IC for parallel processing of logic equations and arithmetic operations comprising: a plurality of sequencer means operating continuously, synchronously and independently of each other, said plurality of sequencer means having at least a first sequencer and a second sequencer; each sequencer of said plurality of sequencer means having a single bit processor, input multiplexer, a program memory, a machine instruction decoder and data memory; a first output signal line of said first sequencer being connected to said input multiplexer of said second sequencer, said first output signal line carrying output data provided by said single bit processor of said first sequencer; a first computer program subroutine for producing logic constructs from hardware description languages; a second computer program subroutine being responsive to the first computer program subroutine and converting logic constructs into machine instructions for maid plurality of sequencer means; a third computer program subroutine for dividing said machine instructions produced by said second computer program subroutine between said plurality of sequencer means in approximately equal proportions; a fourth computer program subroutine for calculating time of execution of logic constructs in said sequencer means, a fifth computer program subroutine for producing an output data read instruction and inserting it into the program memory of said second sequencer at such position in said program memory that it will execute when the specified output data is produced and temporarily available on the output of said first sequencer, said output data read instruction directly capturing and operating upon the said output data from said first sequencer via said input multiplexer of said second sequencer.