Patent ID: 7491589

Claim:
A method for forming a semiconductor structure, the method comprising the steps of: (a) providing a semiconductor region directly on an underlying electrically isolating layer, the semiconductor region being covered on top by a mandrel and a spacer, wherein the semiconductor region and the underlying electrically isolating layer are in direct physical contact with each other via an common interfacing surface that defines a reference direction perpendicular to the common interfacing surface, and wherein the spacer overlaps the semiconductor region in the reference direction; (b) forming a back gate region separated from the semiconductor region by a back gate isolating layer and covered by an inter-gate isolating layers, wherein the inter-gate isolating layer overlaps the back gate region in the reference direction; (c) removing a portion of the semiconductor region beneath the mandrel so as to form an active region adjacent to the removed portion of the semiconductor region; and (d) forming a main gate region in place of the removed portion of the semiconductor region and on the inter-gate isolating layer, the main gate region being separated from the active region by a main gate isolating layer and being separated from the back gate region by the inter-gate isolating layer, wherein the main gate region overlaps the inter-gate isolating layer in the reference direction.