Patent ID: 8349528

Claim:
A method of designing a lithography mask set, the method comprising: designing a layout for a semiconductor device, the layout including a plurality of first features in a first region of a workpiece and a second feature in a second region of the workpiece, the plurality of first features and the second feature of the layout comprising a first lateral dimension; designing a first lithography mask adapted to pattern a workpiece with the plurality of first features in the first region of the workpiece and the second feature in the second region of the workpiece, the first lithography mask including a first pattern for the first features in the first region of the workpiece that is optimized to produce the plurality of first features in the first region of the workpiece comprising the first lateral dimension or less, the first lithography mask including a second pattern for the second feature that is adapted to produce the second feature in the second region of the workpiece having a second lateral dimension, the second lateral dimension being greater than the first lateral dimension; and designing a second lithography mask adapted to mask the first region of the workpiece while the second lateral dimension is reduced without removing the second feature.