Patent ID: 7269805

Claim:
A system for testing an integrated circuit comprising: an embedded microprocessor located in the integrated circuit, the integrated circuit being a field programmable logic device, the embedded microprocessor being designed apart from the integrated circuit as an embeddable core; the field programmable logic device including programmable logic capable of being configured as programmable test circuitry; a plurality of assembly language instructions stored in a memory internal to the integrated circuit, the plurality of assembly language instructions for substantially exercising a critical path or a path close to the critical path in the embedded microprocessor; the programmable test circuitry comprising a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the plurality of assembly language instructions; the programmable clock circuit not being part of the programmable logic but being a digital clock tile of the field programmable logic device, the programmable clock circuit capable of receiving an input clock signal for multiplication to provide the multiplied clock signal for testing of the embedded microprocessor; the programmable test circuitry including a memory controller and an address decoder both of which are instantiated in the programmable logic responsive to configuring the field programmable logic device for a configured-in self-testing mode; the programmable clock circuit configured for providing a test system clock signal responsive in part to receiving the input clock signal, the test system clock signal capable of being less in frequency than the multiplied clock signal; the memory controller and the address decoder coupled to receive the test system clock signal for synchronous operation with the embedded microprocessor, the embedded microprocessor being coupled to the programmable test circuitry via an arbitrated bus; the programmable test circuitry including a reset circuit coupled to receive a lock signal from the programmable clock circuit and configured to provide a release from reset state signal to the memory controller, the address decoder, and the embedded microprocessor for the synchronous operation thereof.