Patent ID: 8711625

Claim:
A method of operating a non-volatile memory circuit having an array of non-volatile memory cells formed along columns of multiple bits, the method comprising: organizing the columns to include a plurality of regular columns and one or more redundancy columns; performing a plurality of first column test operations to determine which columns are defective, each of the first column test operations including: writing and reading back an externally supplied data pattern to the columns; and comparing the externally supplied data pattern as read back with an expected data pattern, wherein said first column test operations are performed by circuitry on the memory circuit and each of the first column test operations uses a different data pattern; recording addresses of any of the regular columns determined defective; for any of the regular columns determined defective, setting a latch associated therewith to a value indicating that the associated column is defective; subsequent to performing the first column test operations, performing a plurality of second column test operations on the regular columns determined defective to determine individual bits therein that are defective, each of the second column test operations including: writing and reading back an externally supplied data pattern to the regular columns determined defective; and comparing the externally supplied data pattern as read back with an expected data pattern, wherein said second column test operations are performed by circuitry on the memory circuit and each of the second column test operations uses a different data pattern; and recording addresses of any of the individual bits of the columns determined defective that are determined defective in the column redundancy data table.