Patent ID: 7642634

Claim:
A chip package, comprising: a dielectric layer, having a first surface, a second surface, and a plurality of lateral surfaces joined between the first surface and the second surface, wherein one of the lateral surfaces has at least a groove and the groove is exposed from the lateral surfaces; at least a conductive layer, disposed in the groove and exposed from the groove of the lateral surfaces; a first chip, inserted in the dielectric layer, wherein the first chip has an active surface with at least a pad and a back surface, and the dielectric layer covers the active surface except for the pad; a first wiring layer, located on the first surface and electrically connected to the conductive layer; at least a first conductive via, located in the dielectric layer for electrically connecting the first chip to the first wiring layer; at least a second chip: and at least a third conductive via, wherein the second chin and the third conductive via are located in the dielectric layer, wherein the third conductive via electrically connects the first wiring layer to the second chip.