Patent ID: 8773345

Claim:
A shift register including field-effect transistors of the same polarity, the shift register comprising a plurality of cascaded identical stages, the stages of even rank receiving a first clock signal and the stages of odd rank receiving a second clock signal complementary to said first clock signal, and the stages being sequenced through an input signal applied on an input node of a stage to transmit, one after the other, a clock pulse to an output node of said stage during a corresponding line selection phase for said stage, each respective stage comprising: an output transistor, a gate of which is connected to an internal node, a source of which forms said output node of the stage, and a drain of which receives one of said first and second clock signals, wherein a first capacitor is connected between the gate of the output transistor and the source of the output transistor, a first control transistor having a source connected to said internal node, a gate connected to the input node of the stage, said input node connected to an output node of an immediately preceding stage, and said first control transistor configured to bring said internal node to a precharging voltage in a precharging phase corresponding to the line selection phase of said immediately preceding stage, whereby the output transistor is passing during said line selection phase of the respective stage, a second control transistor having a drain connected to said internal node, wherein the second control transistor is configured to bring said internal node to an output transistor blocking voltage, in a deselection phase following said line selection phase, and a second capacitor connected to said internal node and controlled by the other of said first and second clock signals, wherein said respective stage comprises an additional transistor of the same technology and of the same polarity as said output transistor, said additional transistor mounted as a diode with a drain and a gate permanently connected together to said internal node, and a source connected to one of the source of the output transistor, the drain of the output transistor or a blocking biasing voltage.