Patent ID: 7183202

Claim:
A method of forming metal wiring in a semiconductor device, comprising: forming a first stopping layer on a semiconductor substrate on which a conductive layer is formed; forming an insulating interlayer on the first stopping layer; forming a second stopping layer on the insulating interlayer; forming a preliminary layer on the second stopping layer; partially removing the preliminary layer to form a preliminary pattern, the preliminary pattern defining a trench region by exposing a top surface of the second stopping layer, wherein the trench region has a first width; partially removing the second stopping layer and a portion of the insulating interlayer using the preliminary pattern, thereby forming a trench of first width; forming a first mask layer on the second stopping layer, wherein the first mask layer fills the trench; forming a second mask layer on the first mask layer; forming a third mask layer on the second mask layer; partially removing the third mask layer to form a third mask pattern, the third mask pattern defining a via-hole region by exposing a top surface of the second mask layer, wherein the via-hole region has a second width smaller than the first width; partially removing the second mask layer using the third mask pattern, thereby forming a second mask pattern; partially removing the first mask layer using the second mask pattern, thereby forming a first mask pattern; partially removing the insulating interlayer using the first mask pattern, thereby forming a via-hole of second width partially exposing the first stopping layer.