Patent ID: 7447862

Claim:
A memory system, comprising: a memory module having a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively, each of the plurality of memories having a pattern data generating circuit for generating a pattern data; a switching circuit controlled by a control signal from the memory module; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation and receiving the pattern data from each of the plurality of memories in response thereto, calculating data reaching time differences among data reaching each of the plurality of memories by using either the pattern data outputted from each of the memories or read data from each of the memories of the memory module, as selected by the switching circuit in response to the control signal, and receiving and outputting data using the calculated data reaching time differences, so that reaching times of data output from the plurality of memories are controlled to be identical in the memory controller, wherein the memory controller, when the data reaching time difference is calculated, outputs data having a time difference according to the calculated reaching time difference to each of the plurality of memories, receiving data outputted from each of the plurality of memories to compensate the time difference of data according to the calculated data reaching time differences, and determining whether or not each calculated data reaching time difference is accurate and upon determining that the data reaching time difference is inaccurate, the memory controller recalculates the data reaching time difference, wherein the pattern data generating circuit toggles the pattern data in response to a control signal and a toggle interval of the pattern data is greater than a time difference between earliest data reaching the memory controller and latest data reaching the memory controller among the data outputted from each of the plurality of memories.