Patent ID: 6924522

Claim:
An integrated circuit transistor, comprising: an electrically isolated floating gate comprising a gate region having a gate electrode connected to a first portion of a patterned and etched conductive layer through a first buried contact opening in an insulating layer formed over at least a portion of the gate electrode that is outside the active region directly beneath the floating gate; a dielectric layer formed on the conductive layer; a conductive top plate layer formed on the dielectric layer; and wherein a second portion of the conductive layer serves as a dynamic random access memory (DRAM) cell storage capacitor bottom plate electrode of a DRAM cell array wherein a second buried contact region in the DRAM cell array connects the DRAM cell storage bottom plate electrode and a DRAM cell access transistor source/drain diffusion and wherein the first and second portions of the conductive layer are of an identical material and formed simultaneously.