Patent ID: 8572147

Claim:
A method comprising: receiving a first instruction at an input of a processor and storing the first instruction in an instruction storage circuit; providing a specifier that indicates both a first portion of a value and a second portion of the value, the first portion of the value is identified to be modified by the processor and the second portion of the value is identified to remain unchanged, wherein a first change in bit value from a first bit value to a second bit value in the specifier when the specifier is traversed from a highest order bit down towards a lowest order bit defines a boundary between the second portion and the first portion, wherein the specifier includes a same number of bits as the value and includes at least one higher order bit that has the first bit value; decoding the first instruction and in response to the decoding the processor modifying the first portion of the value by performing a bit-reversed increment to form a modified first portion, using all bits of the specifier to form a first intermediate value representative of the modified first portion, and using all bits of the specifier to form a second intermediate value representative of the second portion; combining the modified first portion with the second portion of the value which remained unchanged to form a first address, wherein the step of combining is performed such that a final operation used to form the first address is a bit-wise OR operation of the first intermediate value and the second intermediate value; storing the first address in a first storage circuit; receiving a second instruction at the input of the processor; and decoding the second instruction and in response to the decoding, the processor accessing data located at the first address which is assigned to a second storage circuit.