Patent ID: 7982218

Claim:
A TFT array substrate having data lines and scan lines, a TFT and a storage capacitor, the data lines and the scan lines being arranged to intersect one another to define pixel regions, the storage capacitor comprising a pixel electrode, a common electrode and an insulator disposed therebetween, the array substrate comprising: an insulator base; a first metal layer on the insulator base, a first portion of the first metal layer forming a gate electrode of the TFT and the scan line electrically connected with the gate electrode; a gate insulating layer overlying the first metal layer and the insulator base; an amorphous silicon layer and a first layer of conductive transparent material ( 208 ) both positioned on the gate insulating layer; a doped amorphous silicon layer positioned on the amorphous silicon layer and forming a semiconductor layer of the TFT with the amorphous silicon layer collectively; a second metal layer positioned on the doped amorphous silicon layer and the first layer of conductive transparent material, a first portion of the second metal layer forming a source electrode and a drain electrode of the TFT, the source electrode being electrically connected with the data line; a passivation layer on the second metal layer acting as the insulator; and a second layer of conductive transparent material on the passivation layer, a first portion of the second layer of conductive transparent material forming the pixel electrode, the pixel electrode being electrically connected with the drain electrode, wherein the first layer of conductive transparent material forms a portion of the common electrode.