Patent ID: 8411523

Claim:
A system comprising: a dynamic random access memory (DRAM) device to execute a self-refresh mode, the DRAM device including a plurality of banks, each bank to include a plurality of rows, the self-refresh mode to include a plurality of commands, each command to refresh rows of one of the banks; a memory controller operatively coupled to the DRAM device; and logic, operatively coupled to the DRAM device and the memory controller, to: determine the number of banks included in the DRAM device, determine characteristics of power supplied to the DRAM device, and determine a plurality of subsets of banks or rows to be concurrently refreshed in the self-refresh mode, wherein determining the plurality of subsets to be concurrently refreshed is based, at least in part, on the characteristics of power supplied to the DRAM device; the DRAM device to execute the self-refresh mode for each of the plurality of subsets in a staggered fashion.