Patent ID: 8786112

Claim:
A semiconductor device, comprising: a die pad comprising a first surface and a second surface opposite to the first surface; a first chip arranged in a first area on the first surface, the first chip comprising a first side and a second side crossing to the first side; a second chip arranged in a second area on the first surface, the second chip comprising a third side and a fourth side crossing to the third side; a plurality of first marks formed on the first surface, the first marks comprising a third mark and a fourth mark; a plurality of second marks formed on the first surface, the second marks comprising a fifth mark and sixth mark; a wire, one end of the wire connected to the first chip; a resin encapsulating the first chip, the second chip, and the wire; a lead, one end of the lead connected to a second end of the wire, and a part of the lead encapsulated by the resin, wherein the first area is defined as an area surrounded by a first imaginary line, a second imaginary line, a third imaginary line, and a fourth imaginary line in a plan view, wherein the first imaginary line crosses to the third mark and is parallel to the first side of the first chip, wherein the second imaginary line crosses to the third mark and is parallel to the second side of the first chip, wherein the third imaginary line crosses to the fourth mark and is parallel to the first side of the first chip, wherein the fourth imaginary line crosses to the fourth mark and is parallel to the second side of the first chip, wherein the second area is defined as an area surrounded by a fifth imaginary line, a sixth imaginary line, a seventh imaginary line, and a eighth imaginary line in the plan view, wherein the fifth imaginary line crosses to the fifth mark and is parallel to the third side of the second chip, wherein the sixth imaginary line crosses to the fifth mark and is parallel to the fourth side of the second chip, wherein the seventh imaginary line crosses to the sixth mark and is parallel to the third side of the second chip, and wherein the eighth imaginary line crosses to the sixth mark and is parallel to the fourth side of the second chip.