Patent ID: 8378713

Claim:
A digital filter circuit, comprising: an EXOR circuit to receive an input signal and a feedback-inputted output signal, the EXOR circuit to generate a clock gating enable signal of an enable state once receiving the output signal and the input signal having a phase reverse to that of the output signal; a clock gating circuit to receive a clock signal and the clock gating enable signal, the clock gating circuit to capture and output the clock signal as a clock gating signal while the clock gating enable signal is in the enable state; a reset control circuit to receive the clock signal and the clock gating enable signal, the reset control circuit to generate a first signal of the enable state once the clock gating enable signal changes from the enable state to a disable state; a counter to receive the first signal and the clock gating signal, the counter to be synchronously reset when the first signal is in the enable state, the counter to perform a count operation to generate a count signal each time the counter receives the clock gating signal while the first signal is in the disable state; a filter time setting circuit to receive the first signal, the clock gating signal and the count signal, the filter time setting circuit to latch the count signal when the first signal is in the enable state, the filter time setting circuit to output a latched count value as a second signal; a comparator to receive the count signal and the second signal, the comparator to output a third signal of the enable state when the value of the count signal and the value of the second signal match each other; and a decoder to receive the feedback-inputted output signal, the first signal and the third signal, the decoder to generate a fourth signal resulting from decode processing, wherein the input signal is subjected to digital signal processing.