Patent ID: 7757067

Claim:
A system comprising: A. a memory containing instructions; B. a main processor unit coupled to the memory and executing instructions obtained from the memory; C. a stack machine, separate from the main processor unit, coupled to the memory and executing instruction bytecodes obtained from the memory, the stack machine including: i. a program counter containing an address of a first instruction bytecode to be decoded; ii. a program counter calculator coupled to the program counter and providing the program counter with the address of the first instruction bytecode to be decoded, the program counter calculator including a match input; iii. a register containing instruction bytecodes including the first instruction bytecode and a second instruction bytecode following the first instruction; iv. decode logic coupled to the register and to the program counter calculator and decoding the first instruction bytecode from the register; v. pre-decode logic having a match output connected with the match input of the program counter calculator and being coupled to the second instruction bytecode in the register, the pre-decode logic decoding the second instruction bytecode while the decode logic is decoding the first instruction bytecode and selectively providing a match signal to the program counter calculator to increment the program counter past the second instruction bytecode and vi. the register having instruction sections, each section containing an instruction bytecode, the pre-decode logic includes sets of comparator logic, each comparator logic set has inputs coupled with one instruction section and an output, and the pre-decode logic includes multiplexer circuitry having inputs connected to the outputs of the comparator logic sets and a match output connected with the program counter calculator.