Patent ID: 6871329

Claim:
A design system of an integrated circuit, comprising: a timing test portion testing timing of the integrated circuit, based on circuit information and delay information indicating a circuit structure of the integrated circuit; a circuit modification portion modifying the circuit information, based on timing error recognized in said timing test portion; a delay presumption portion presuming the delay information from the modified circuit information without designing layout with the circuit information modified in said circuit modification portion; and an information update portion updating the circuit information and delay information of the integrated circuit based on the circuit information modified in said circuit modification portion and the delay information presumed in said delay presumption portion, to provide to said timing test portion, wherein when a timing error is recognized in the timing test portion, based on the timing error, the circuit information is modified to insert or delete circuit elements that delay a signal in a signal propagation path relating to the timing error, and wherein delay circuit models represent a signal propagation path between circuit elements composing the integrated circuit of one resistance and two capacitance.