Patent ID: 7181718

Claim:
A method of modifying a programmable logic device (PLD) including columns of block random access memory (BRAM) blocks and columns of programmable logic blocks programmably interconnected by a general interconnect structure, each BRAM block including a RAM and a plurality of terminals coupling the RAM to the general interconnect structure, the method comprising, for each BRAM block in a first column of BRAM blocks: widening the BRAM block to create a specialized logic block wider but having the same height as the BRAM block, wherein the terminals of the specialized logic block have corresponding locations to the terminals of the BRAM block; modifying the specialized logic block to include a processor; and modifying the specialized logic block to include a dedicated interface coupled to the RAM from the BRAM block and to the processor, and further coupled to the general interconnect structure via the terminals of the specialized logic block.