Patent ID: 7428654

Claim:
A data transfer circuit configured to transfer data between a first circuit block and a second circuit block, the second circuit block operating at a power supply voltage different from a power supply voltage for the first circuit block, the data transfer circuit comprising: a first transfer circuit configured to receive a first transfer signal from the first circuit block; a second transfer circuit configured to receive a second transfer signal from the first circuit block; a third transfer circuit configured to receive the first transfer signal transmitted from the first transfer circuit, and an inverted first transfer signal from the first transfer circuit, and transfer the first transfer signal to the second circuit block in response to a reply signal from the second circuit block; and a fourth transfer circuit configured to receive the second transfer signal transmitted from the second transfer circuit, and an inverted second transfer signal from the second transfer circuit, and transfer the second transfer signal to the second circuit block in response to the reply signal, wherein a transfer control signal is generated from the first transfer signal and the inverted first transfer signal, both of which are transferred from the third transfer circuit, and the second transfer signal and the inverted second transfer signal, both of which are transferred from the fourth transfer circuit; the first transfer circuit transmits the first transfer signal and the inverted first transfer signal in response to the transfer control signal; the second transfer circuit transmits the second transfer signal and the inverted second transfer signal in response to the transfer control signal; and a reply signal is generated to be transferred to the first circuit block using the inverted first transfer signal transmitted from the first transfer circuit and the inverted second transfer signal transmitted from the second transfer circuit.