Patent ID: 8271736

Claim:
A method for increasing cache memory performance and utilization, comprising: combining a data block frequency map generated by a data de-duplication mechanism with a page prefetching and eviction process; using said data block frequency map to provide weights that are directly proportional to a corresponding frequency count of a data block in a dataset; creating a set of de-duplicated data blocks in the cache memory with the data de-duplication mechanism; ordering the set of de-duplicated data blocks in the cache memory according to the corresponding frequency count for each of the de-duplicated data blocks; ordering de-duplicated data blocks having a same frequency count in the cache memory into a least recently used order according to an average value of a cache residence term for each de-duplicated data block; influencing a caching algorithm controlling said page prefetching and eviction process with said weights; evicting the data block from the cache memory when the frequency count for the data block is greater than zero; and evicting all data blocks having a same frequency count that is less than or equal to the frequency count of other data blocks from the cache memory, with data blocks having a same frequency count evicted in the least recently used order according to an average value of a cache residence term, before evicting any data block with a higher frequency count.