Patent ID: 8519770

Claim:
A circuit arrangement configured to limit a voltage between a first clamping point and a second clamping point, the circuit arrangement comprising: a first electronic component, a second electronic component and a third electronic component; a first series arm and a second series arm, an operating voltage being applied between the first and second series arms; the third electronic component coupled between the first and second series arms, the third electronic component having an input to which a first reference voltage is connected and an output and being configured to connect and amplify the first reference voltage; the first electronic component coupled between the first and second series arms to permit a current to flow through a current path from the first series arm through the first and second clamping points, the first electronic component a first resistor and a load resistor is arranged between the first and second clamping points, the first electronic component having an input connected by a second resistor to the output of the third electronic component; the second electronic component being configured to connect and amplify an electrical voltage and coupled between the first and second series arms, an input of the second electronic component being connected by a third resistor to the output of the third electronic component; and a device configured to produce a second reference voltage and arranged between the second series arm and the second electronic component, the second reference voltage of the device being configured to lower the voltage at the first clamping point occurs when a flow of current through the load resistor is interrupted.