Patent ID: 7613186

Claim:
An apparatus comprising: a data unit configured to (i) receive an input signal and a data valid signal, said input signal comprising a series of frames, each said frame having a header and a payload comprising a series of words, said data valid signal configured to indicate that said input signal is ready, and (ii) generate an output signal in response to a first word and a second word from said input signal, wherein said output signal comprises a third word comprising a number of bits selected from one or both of the first and the second words in response to a first control signal, and wherein the number of bits and position of the bits in the third word are (i) configured to be varied according to a current format of said frames and (ii) arranged in one of a plurality of formats based upon a second control signal; a memory configured to (a) store said output signal in response to one or more memory control signals and (b) provide an interface between said data unit and a device; and a control unit configured to generate (i) said first control signal, (ii) said second control signal, (iii) a third control signal presented to said data unit and (iv) said one or more memory control signals to control said memory all in response to both a start of frame signal and said data valid signal.