Patent ID: 7005319

Claim:
A method for producing at least two different chips with a controlled total chip thickness such that when these chips are placed into a corresponding pocket of a plurality of pockets located in a wafer chip carrier wherein each of said plurality of pockets have a total pocket depth (Tdp) at least substantially equal to one another, a substantially planarized top surface of said wafer chip carrier is achieved, comprising: forming at least a first chip on a first dummy carrier and at least a second chip different from said first chip on a separate second dummy carrier using partial wafer bonding and partial wafer dicing; and using a chip thickness control mechanism in conjunction with said partial wafer bonding and partial wafer dicing in forming said at least a first chip and at least a second chip different from said first chip, such that said at least two different chips formed from each carrier each have a final total chip thickness (FTC) which is substantially equal to one another, said at least two different chips formed also each have a FTC which is substantially equal to the total pocket depth (Tdp) of each of said plurality of pockets of said wafer chip carrier, minus the final thickness of an attaching material (FTG) used within said each respective pocket.