Patent ID: 8441133

Claim:
A semiconductor device comprising: a first wiring substrate having a first surface and a second surface on an opposite side of the first surface; a plurality of first mounting pads formed on the first surface of the first wiring substrate and configured to mount a first semiconductor element on the first surface of the first wiring substrate; a plurality of first connection pads formed on the first surface of the first wiring substrate and positioned on a periphery of the plurality of first mounting pads; a second wiring substrate formed on the first wiring substrate and having a first surface and a second surface on an opposite side of the first surface of the second wiring substrate, the second wiring substrate having a second penetrating electrode which has a protruding portion protruding from the second surface of the second wiring substrate such that the protruding portion of the second penetrating electrode has a post configuration extending into a space between the second wiring substrate and the first wiring substrate; a plurality of second mounting pads formed on the first surface of the second substrate and configured to mount a second semiconductor element; and a conductive member formed on one of the first connection pads and electrically connecting an end portion of the second penetrating electrode and the one of the first connection pads, wherein the second wiring substrate includes a surface insulation layer formed on the second penetrating electrode such that the surface insulation layer extends along the post configuration of the second penetrating electrode.