Patent ID: 8357604

Claim:
A method of forming transistors of different threshold voltages, the method comprising: forming a dielectric base layer and a high-k dielectric material above a plurality of semiconductor regions, a thickness of at least one of said dielectric base layer and said high-k dielectric material being different for each of said plurality of semiconductor regions; forming a first metal-containing layer comprising a first work function metal species above said high-k dielectric material in at least a first region of said plurality of semiconductor regions; performing a first heat treatment so as to diffuse said first work function metal species from said first metal-containing material into at least said high-k dielectric material above said at least said first region of said plurality of semiconductor regions; forming a second metal-containing layer comprising a second work function metal species that is different from said first work function metal species above said high-k dielectric material in at least a second region of said plurality of semiconductor regions; after performing said first heat treatment, performing a second heat treatment so as to diffuse said second work function metal species from said second metal-containing material into at least said high-k dielectric material above said at least said second region of said plurality of semiconductor regions; forming an electrode material above said high-k dielectric material above each of said plurality of semiconductor regions; forming a gate electrode structure on each of said plurality of semiconductor regions from said electrode material, said dielectric base layer and said high-k dielectric material; and forming drain and source regions in each of said plurality of semiconductor regions.