Patent ID: 7757054

Claim:
A memory control system, comprising: a microprocessor for outputting a plurality of addresses, wherein the plurality of addresses comprises at least a first address and a second address, and optionally a third address; a storage device for storing data corresponding to the plurality of addresses; a first buffer for temporarily storing a first data or a third data; a second buffer for temporarily storing a second data; a memory control unit for receiving the first address to read a first data corresponding to the first address from the storage device and for receiving the second address to read a second data corresponding to the second address from the storage device or for receiving the third address to read a third data corresponding to the third address from the storage device; wherein the memory control unit generates a select signal when both of the first and the second buffers contain any of the above mentioned data; and a multiplexer for receiving the first data and the second data or the third data and outputting the first data, the second data, or the third data to the microprocessor according to the select signal, wherein the multiplexer outputs the first data during a first duration and the second data during a second duration according to the select signal, when the first address and the second address are arrayed in continuous order, wherein the memory control unit provides at least one dummy command to delay the microprocessor for a third duration until the first buffer stores the first data and the second buffer stores the second data, when the microprocessor starts to read the data from the storage device during the initiating stage of the microprocessor, and wherein the memory control unit provides at least one dummy command to delay the microprocessor for a third duration until the first buffer stores the third data and the second buffer stores the second data, when the first address and the second address are not arrayed in continuous order.