Patent ID: 8862653

Claim:
A processing element configured for sparse matrix-vector multiplication (SpMV) processing, comprising: a vector cache storing a subset of input vector data; a shifter configured to receive matrix data and provide serial output matrix values; a multiply accumulator configured to compute a dot product value from the matrix data and the input vector data, the multiply accumulator comprising a reduction circuit having an input configured to receive an incoming value of an accumulation set of the matrix data, the incoming value having an associated accumulation set id, the reduction circuit further comprising an adder configured to sum input values provided to the adder and provide the summed value to an adder output, at least one buffer in operable communication with the input and the adder output, the at least one buffer configured to provide a buffered value to the adder, the reduction circuit further comprising a plurality of data paths arranged to selectively deliver one or more of the incoming value, the buffered value, and the summed value to the adder and to the at least one buffer; and a controller configured to control delivery of the incoming value, the buffered value, and the summed value to the adder or to the at least one buffer based on an accumulation set id associated with one or more of the incoming value, the buffered value and the summed value.