Patent ID: 7557439

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein: the main body includes a plurality of layer portions stacked; the plurality of layer portions include: a plurality of first-type layer portions each including a first-type semiconductor chip; and a second-type layer portion including a second-type semiconductor chip; the first-type semiconductor chip includes a plurality of memory cells; the second-type semiconductor chip includes a circuit that controls writing and reading on and from the plurality of memory cells included in the plurality of first-type layer portions; each of the first-type semiconductor chip and the second-type semiconductor chip has a top surface, a bottom surface and four side surfaces; each of the plurality of layer portions includes: an insulating portion covering at least one of the four side surfaces of the first-type or second-type semiconductor chip; and a plurality of electrodes connected to the first-type or second-type semiconductor chip; the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed; each of the plurality of electrodes has an end face surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions.