Patent ID: 7581160

Claim:
A Viterbi decoder for decoding a string of data, a trellis structure in the Viterbi decoder containing N trellis states with two-branches and K trellis states with only one branch, wherein N and K are positive integers, the Viterbi decoder comprising: a branch metric generator for calculating and outputting branch metrics for each branch; an add-compare-select unit for receiving the branch metrics and previous candidate state metrics respective to the trellis state in the trellis structure and outputting N comparison signals; wherein the add-compare-select unit comprises: (2N+K) registers for storing the previous candidate state metrics respective to the trellis state; N add-compare-select processors for receiving values stored in the 2N first registers and corresponding branch metrics, and outputting N candidate state metrics and the N comparison signals; and wherein each add-compare-select processor comprises: a first adder for adding a first value stored in one of the registers and a first branch metric to generate a first addition result; a second adder for adding a second value stored in another of the registers and the first branch metric to generate a second addition result; a comparator for comparing the first value and the second value, and outputting a comparison signal; and a selector for selecting either the first addition result or the second addition result as the candidate state metric according to the comparison signal; wherein each add-compare-select processor is configured with the registers being located before the comparator.