Patent ID: 8065459

Claim:
A multi-processor circuit, comprising a plurality of processing elements each configured to execute at least a respective task comprising execution of a series of instructions; a shared resource coupled to the plurality of processing elements; an arbitration circuit coupled to the processing elements and configured to arbitrate conflicting access requests to the shared resource from the plurality of processing elements dependent on priorities assigned to the processing elements; priority setting circuitry configured to measure an indication of a speed of progress of execution of respective ones of the tasks and to set the priority for each processing element that executes a particular one of the tasks dependent on the measured indication of the speed of progress of execution of the series of instructions of the particular one of the tasks, wherein the priority setting circuitry is configured to determine the indication of the speed of progress of the particular one of the tasks at a particular one of the instructions in the particular one of the tasks using a count of instruction execution cycles that have occurred before reaching said particular one of the instructions from a reference instruction execution cycle that has a predetermined relation to a start of execution of the particular one of the tasks and a count of stalled instruction execution cycles between the reference instruction cycle and execution of the particular one of the instructions.