Patent ID: 7924202

Claim:
An integrated circuit device comprising: an amplifier circuit that includes first to Nth (N is an integer equal to or larger than two) amplifiers and receives an input signal, the first to Nth amplifiers being cascaded; an A/D converter that performs an A/D conversion process on a signal amplified by the amplifier circuit; first to Nth D/A converters that are provided corresponding to the first to Nth amplifiers and used to perform an offset adjustment of the first to Nth amplifiers; and a control circuit that sets an offset adjustment of the first to Nth amplifiers using the first to Nth D/A converters and sets a gain adjustment of the first to Nth amplifiers, an output range QR 1 of an ith (i is an integer that satisfies 1≦i<N) D/A converter among the first to Nth D/A converters being wider than an output range QR 2 of an (i+1)th D/A converter among the first to Nth D/A converters that is provided in a subsequent stage of the ith D/A converter.