Patent ID: 7867887

Claim:
A method of forming a bond pad structure for an integrated circuit, comprising the steps of: depositing a first insulating layer over an underlying region of semiconductor device; lithographically forming a first pattern of multiple first pads on said first insulating layer; etching said first pattern of said multiple first pads from said first insulating layer; filling said etched first pattern of said multiple pads with a first conducting material; removing a first conducting material from above an upper surface of said first insulating layer; depositing a second insulating layer over said first insulating layer and over said first conducting material; lithographically forming a second pattern of multiple vias on said second insulating layer, wherein each of said multiple vias is located within one of said multiple first pads; etching said second pattern of said multiple vias into said second insulating layer; exposing a first conducting material from under each of said etched second pattern; filling said etched second pattern of said multiple vias with a second conducting material; lithographically forming a third pattern of a first metal pad over said multiple vias, wherein all of said multiple vias are within the shape of said first metal pad; and etching said second conducting material from outside the area of said first metal pad.