Patent ID: 8853759

Claim:
A resistive memory device comprising: a first electrode; a first insulation layer arranged on the first electrode, a first portion of the first electrode being exposed through a first hole in the first insulation layer; a first variable resistance layer contacting the exposed first portion of the first electrode and extending onto the first insulation layer; a first switching device electrically connected to the first variable resistance layer; a first intermediate electrode interposed between the first variable resistance layer and the first switching device; and a second electrode on the first switching device; wherein portions of the first insulation layer are between the first electrode and portions of the first variable resistance layer extending onto the first insulation layer, the first variable resistance layer and the first switching device have a same cross-sectional width at a level higher than the first insulation layer, a width of a contact region between the first variable resistance layer and the first electrode is smaller than a width of the first switching device, and the first switching device is arranged on the first variable resistance layer.