Patent ID: 7432752

Claim:
A duty cycle stabilizer circuit ( 50 ) receiving an input clock signal and generating an output clock signal having a first duty cycle, the duty cycle stabilizer circuit comprising: a leading edge pulse generator ( 52 ) receiving the input clock signal and generating a first clock pulse (V 1 ) having a leading edge triggered by the leading edge of the input clock signal, transitions of the first clock pulse having signal polarities opposite to transitions of the input clock signal, the first clock pulse having a first pulse width being a function of a first control signal (Ax); a pulse width extender circuit ( 54 ) receiving the first clock pulse and generating a second clock pulse (V 2 ) having a leading edge triggered by the leading edge of the first clock pulse, transitions of the second clock pulse having signal polarities opposite to transitions of the first clock pulse, the second clock pulse having a pulse width being the sum of the first pulse width and a second pulse width, the second pulse width being a function of a second control signal (Bx); a buffer ( 64 ) receiving the second clock pulse and generating the output clock signal having the first duty cycle; a charge pump ( 56 ) receiving the output clock signal, the charge pump being coupled to drive a first low-pass filter ( 58 ) and a second low-pass filter ( 60 ); and a differential amplifier ( 62 ) receiving a first voltage at the first low-pass filter and a first reference voltage, the differential amplifier generating an output signal indicative of the difference between the first voltage and the first reference voltage, the first and second control signals being indicative of the output signal.