Patent ID: 7408482

Claim:
An integrated circuit device having a plurality of data inversion circuits, comprising: a first data inversion circuit receives an initial ordered group of data and a first ordered group of data compares between corresponding bits in the initial and first ordered group of data, generates a first external parity signal when a number of bit differences between the version of the initial ordered group of data and the first ordered group of data is greater than one-half the number of bits of the first ordered group of data, and generates a version of the first ordered group of data in response to the first external parity signal; and a second data inversion circuit receives the first ordered group of data and a second ordered group of data, compares between corresponding bits in the first and second ordered group of data, generates a first internal parity signal when a number of bit differences between the version of the first ordered group of data and the second ordered group of data is greater than one-half the number of bits of the second-ordered group of data, generates a second external parity signal which is inverted or non-inverted version of the first internal parity signal in response to the first external parity signal, and generates a version of the second ordered group of data in response to the second external parity signal, wherein the initial ordered group of data is output data output during a previous clock cycle.