Patent ID: 7960096

Claim:
A method of implementing sub-lithographic patterning of a semiconductor device feature, the method comprising: forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto; wherein a final of the subsequent sets of patterned features following the one or more subsequent iterations are characterized by a sub-lithographic dimension with respect to equipment used in the single lithography step; and for each iteration of sidewall spacer formation, forming an associated layer stack over a semiconductor substrate prior to the single lithography step; each layer stack comprising a first layer of a first material and a second layer of a second material, with a photoresist layer initially formed over a topmost layer stack.