Patent ID: 7709388

Claim:
A method of fabricating a semiconductor device, comprising the steps of forming an lower wiring layer including a first insulation film and a Cu wiring which is formed in said first insulating film and includes copper; depositing a second insulating film on said first insulating film and said Cu wiring; depositing a third insulating film on said second insulating film; forming an upper hole in said second and third insulation films, said upper hole reaching said Cu wiring; wet-etching an interior of said upper hole to form a lower hole in said Cu wiring, said lower hole communicating with said upper hole; depositing an upper conductive film covering an inner wall surface of said upper hole and a bottom of said lower hole; physically etching said upper conductive film and said Cu wiring which are present at said bottom of said lower hole to provide a lower conductive film on an inner wall surface of said lower hole; and depositing a conductive film containing copper and filling said upper and lower holes.