Patent ID: 7508244

Claim:
An apparatus comprising: a control block configured to provide a control signal; a voltage-controlled oscillator configured to receive the control signal and to output an output signal; a divider block configured to receive the output signal from the voltage-controlled oscillator and configured to divide a frequency of the output signal by a predetermined number; a detector block configured to receive a frequency-divided output signal from the divider block, receive a reference frequency signal, and provide a feedback control signal to the voltage-controlled oscillator in a phase-locked loop, wherein the voltage-controlled oscillator is further configured to include a frequency offset in the voltage-controlled oscillator output signal, wherein the control block is further configured to control the frequency offset included in the voltage-controlled oscillator output signal based on fractional division ratio information and actual division state information received from the phase-locked loop, and the phase-locked loop further comprising one or more resettable delay components configured to remove incorrect frequencies from the voltage-controlled oscillator output signal.