Patent ID: 8313993

Claim:
A dual work function semiconductor device comprising: a first transistor on a first substrate region; and a second transistor on a second substrate region, wherein the first transistor comprises a first gate stack having a first effective work function and the second transistor comprises a second gate stack having a second effective work function, wherein the first gate stack and the second gate stack comprise each a host dielectric in contact with the substrate, a gate electrode comprising a metal layer, and a second dielectric capping layer in between the host dielectric and the gate electrode and in contact with the metal layer of the gate electrode, and the second gate stack comprises further a first dielectric capping layer and a dielectric buffer layer, the first dielectric capping layer being located in between the host dielectric and the metal layer of the gate electrode and being in contact with the host dielectric, the dielectric buffer layer being sandwiched in between the first dielectric capping layer and the second dielectric capping layer on the second substrate region, wherein the dielectric buffer layer is selected to prevent intermixing between the first and the second dielectric capping layer, wherein the metal layer is selected to determine in combination with the second dielectric capping layer and the host dielectric the first effective work function of the first gate stack, and wherein the first dielectric capping layer is selected to determine in combination with the second dielectric capping layer, the host dielectric and the metal layer the second effective work function of the second gate stack.