Patent ID: 8601430

Claim:
A method comprising: identifying at a data processing computer a first instantiation of a device design of an integrated circuit and a second instantiation of the device design of the integrated circuit as matched devices, wherein the first instantiation and the second instantiation each include respective layout features corresponding to a set of layout features, including a first layout feature, wherein the first instantiation includes an instantiation of the first layout feature and the second instantiation includes an instantiation of the first layout feature; determining a region of interest (ROI) of the first instantiation based upon the first layout feature of the first instantiation; determining a region of interest (ROI) of the second instantiation based upon the first layout feature of the second instantiation; determining that a performance mismatch is to occur between an electrical performance characteristic of the first instantiation and of the second instantiation based upon a difference in an environmental condition proximate the first instantiation and the environmental condition proximate the second instantiation, wherein the environmental condition is exclusive of any layout features of the first and second instantiations; and changing a first layout feature, of the set of layout features, of the first instantiation in response to determining that the performance mismatch exists.