Patent ID: 7683423

Claim:
A semiconductor memory device, comprising: a memory cell transistor having a composite gate structure that overlies a memory cell transistor channel region, wherein the composite gate structure includes: a trapped-charge gate electrode; a first insulating film; and a control gate electrode separated from the trapped-charge gate electrode by the first insulating film, wherein the conductivity of the trapped-charge gate electrode is different from the conductivity of the control gate electrode; and a peripheral transistor having a single gate structure that overlies a peripheral transistor channel region, wherein the single gate structure includes: a gate electrode comprising an upper conductive film that is disposed over a lower conductive film, wherein the upper and lower conductive films have different conductivities in the peripheral transistor channel region, wherein the upper and lower conductive films are in substantial conductive contact with each other outside the peripheral transistor channel region, and wherein the upper conductive film has a conductivity substantially equal to the conductivity of the control gate electrode.