Patent ID: 6950150

Claim:
A method for processing respective first and second digital video data signals in a video signal processor, wherein the first video data signal is clocked by a first clock signal, and the second video data signal is clocked by a second clock signal, the first and second clock signals being of identical frequency and having a constant phase relationship, the method comprising the steps of: clocking the first video data signal into an interface circuit by the first clock signal on either the rising edges or the falling edges thereof, clocking the second video data signal into the interface circuit by the second clock signal on either the rising edges or the falling edges thereof, clocking the first video data signal from the interface circuit to the video signal processor by the first clock signal on either the rising edges or the falling edges thereof, clocking the second video data signal from the interface circuit to the video signal processor by the first clock signal on the ones of the rising edges or falling edges thereof similar to the edges of the first clock signal on which the first video data signal is clocked from the interface circuit to the video signal processor so that interpolation of both the first video data signal and the second video data signal can be carried out in the video signal processor with a frequency multiple of the first clock signal.