Patent ID: 7719115

Claim:
A semiconductor integrated circuit including a multi-level interconnect, the multi-level interconnect comprising: a subject wiring layer assigned as one of wiring layers implementing the multi-level interconnect, including a subject wire area placing a subject wire extending along a first direction and a subject diagonal wire area, provided above a localized area, placing a subject diagonal wire being connected to the subject wire and extended diagonally to the first direction, the subject diagonal wire area covering an area corresponding to the localized area in which a circuit element is provided; a first insulating film on the subject wiring layer; a first upper wiring layer as another one of the wiring layers provided on the first insulating film including a first upper wire area placing a first upper wire extending along the first direction and a first upper diagonal wire area, provided above the localized area, placing a first upper diagonal wire connected to the first upper wire and extended diagonally to the first direction, the first upper wire area being provided above the subject wire area, the first upper diagonal wire area being overlapped with the subject diagonal area and covering an area corresponding the localized area; a second insulating film on the first upper wiring layer; and a second upper wiring layer as another one of the wiring layers provided on the second insulating film including a second upper wire area placing a second upper wire extending along the first direction and a second upper diagonal wire area, provided above the localized area, placing a second upper diagonal wire connected to the second upper wire and extended diagonally to the first direction, the second upper wire area being provided above the first upper wire area, the second upper diagonal wire area being overlapped with the subject diagonal area and with the first upper diagonal wire area, the second upper diagonal wire area covering an area corresponding to the localized area, wherein planar dimensions of the subject diagonal wire area, and the first and second upper diagonal wire areas are different from each other.