Patent ID: 7681097

Claim:
A test system comprising: a tester connected to a device under test (DUT) through a test controller, the test controller receiving a first clock signal and m-bit serial data output from the DUT, compressing the m-bit serial data in response to a second clock signal to generate a signature signal, and outputting the signature signal to the tester, wherein the test controller comprises: a shift register including m first flip-flops connected in series, sequentially receiving bits of the m-bit serial data in response to a first clock signal, and respectively providing outputs from the m first flip-flops to m comparators; and a data compressing circuit compressing the m-bit serial data into the signature signal and comprising: m second flip-flops initially storing m-bit initial seed data and respectively receiving outputs from the m comparators in response to the second clock signal generated at a pulse of the first clock signal at which an m th serial bit of the m-bit serial data is input, wherein an output of a last flip-flop of the second flip-flops feedback connected to a first comparator of the m comparators is output as the signature signal, the m comparators respectively compare (n+1) th outputs of the first flip-flops to n th outputs of the second flip-flops, m is greater than or equal to 4, and n is an integer ranging from 1 to (m−1).