Patent ID: 8169235

Claim:
A receiver circuit comprising: an input stage coupled to receive a first input signal and a second input signal, wherein the input stage is configured to generate an output indicating whether or not the first input signal is greater than the second input signal; a first current source coupled to the input stage and configured to supply current to the input stage; and a second current source coupled in parallel with the first current source and having an enable input, wherein the second current source is configured to supply current to the input stage responsive to an assertion of the enable input; wherein, in a differential mode, the first input signal and the second input signal are a differential pair corresponding to an input, and wherein the enable signal is deasserted in the differential mode; and wherein, in a single-ended mode, the first input signal is the input and the second input signal is a reference voltage for the input, and wherein the enable is asserted in the single-ended mode.