Patent ID: 8116129

Claim:
A variable resistance memory device comprising: a silicon substrate; a plurality of active lines which are formed on the silicon substrate, are uniformly separated, and extend in a first direction; a plurality of switching devices which are formed on the active lines and are separated from one another; a plurality of variable resistance devices which are respectively formed on and connected to the switching devices; a plurality of local bit lines which are formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices; a plurality of local word lines which are formed on the local bit lines, are uniformly separated, and extend in the first direction; and a plurality of contacts which are formed for each group of variable resistance devices in the first direction and connect the plurality of active lines and the plurality of local word lines, a plurality of global word lines; and a plurality of global bit lines, wherein the local bit lines, the local word lines, the global bit lines, and the global word lines are formed in different interconnection layers.