Patent ID: 7003696

Claim:
A fault management system for a switching equipment which includes a circuit section connected to an external terminal equipment over a communication circuit, a switch section for communicating data with said circuit section, and a processor for performing setting and control of said circuit section, protocol processing of a transmission/reception packet and other processing over a processor bus, comprising: a clock fault detection section for supervising the normality of an oscillator for supplying a clock signal to said processor and detecting whether or not supply of the clock signal from said oscillator is interrupted, and a concentrated fault management section connected to said clock fault detection section and said processor bus for supervising the normality of said processor bus and for continuously signaling, if a fault notification of the interruption of the supply of the clock signal is received from said clock fault detection section, a reset signal to said processor and said circuit section utilizing signal lines separate and distinct from said processor bus so that data in a data link layer or an upper layer may not flow from said processor or said circuit section and issuing a notification of occurrence of a fault to a central control section connected to an external console.