Patent ID: 7354838

Claim:
A method, comprising: forming a transistor element comprising a gate electrode structure including at least an inner spacer element and an outer spacer element, wherein forming said transistor element comprises: forming a gate electrode above a semiconductor region; forming said at least one inner spacer element adjacent the sidewalls of said gate electrode; forming an etch stop layer to separate said at least one inner spacer element and said outer spacer element; and forming drain/source regions using said inner and outer spacer elements as the implantation mask; and wherein forming said outer spacer element comprises depositing said etch stop layer, depositing a spacer material layer, anisotropically etching said spacer material layer to form said outer spacer element and etching said etch stop layer using said outer spacer element as an etch mask; removing said outer spacer element; forming a contact liner layer above said transistor element; and forming a silicide region on said gate electrode and said drain/source region prior to forming said contact liner layer, wherein said outer spacer element is removed prior to forming said silicide region.