Patent ID: 8222050

Claim:
A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) supplying a plurality of chips divided in individual chip regions while being arranged substantially in their original two-dimensional layout upon a wafer, to a chip treating apparatus with their back surfaces fixed to an adhesive tape; and (b) vacuum-chucking a surface of a first chip out of the chips with a chucking collet and peeling the adhesive tape from the back surface of the first chip in a state in which the adhesive tape over the back surface of the first chip is vacuum-chucked to an upper surface of a lower base; the step (b) further comprising the following sub-steps of: (b1) monitoring a bent state of the first chip before complete separation of the first chip from the adhesive tape by measuring the flow rate of a vacuum chucking system of the chucking collet; and (b2) determining an optimum speed of the peeling operation on the basis of the monitor information obtained in the sub-step (b1), the method further comprising a following step of: (c) after the step (b), vacuum-chucking a surface of a second chip out of the chips with the chucking collet and, in a state in which the adhesive tape over the back surface of the second chip is vacuum-chucked to the upper surface of the lower base, carrying out the peeling operation at the optimum speed to peel the adhesive tape from the back surface of the second chip.