Patent ID: 7576421

Claim:
A semiconductor device comprising: multi-layered semiconductor substrates each formed with integrated circuits, a pair of power supply lines, signal lines correspondingly connected to said integrated circuits, and through-holes crossing the semiconductor substrate in the thickness direction; inter-chip electrodes arranged vertically to said semiconductor substrates through said through-holes, at least two of said inter-chip electrodes being connected to said power supply lines, at least one other of said inter-chip electrodes being connected to said signal lines and arranged adjacent to, but closely spaced from, at least one of said power supply lines, a respective one of said inter-chip electrodes that is connected to a signal line being between corresponding inter-chip electrodes that are connected to said power supply lines; an interface semiconductor substrate assembled by being stacked up with said multi-layered semiconductor substrates and interfacing transmission of signals via the inter-chip electrode connected to said signal lines; and a plurality of external electrodes electrically connected to said inter-chip electrodes.