Patent ID: 8742497

Claim:
A semiconductor device comprising a high voltage tolerant transistor, wherein the high voltage tolerant transistor includes: a semiconductor substrate having a main surface; a well region of a first conductivity type formed over the main surface; a plurality of first impurity regions of a second conductivity type, each of which is formed over the main surface in the well region and from each of which a source electrode is extracted; and a second impurity region of a second conductivity type formed over the main surface so as to be adjacent to each of the first impurity regions, from which a drain electrode is extracted, and wherein the semiconductor device comprises: a third impurity region of the first conductivity type formed over the main surface located, in planar view, between a pair of the first impurity regions and in the well region, from which a potential of the well region is extracted, and a gate electrode for isolation formed over the main surface between the first impurity region and the third impurity region.