Patent ID: 7279927

Claim:
A method for reducing power consumption in an integrated circuit having a main power domain on a first portion of the integrated circuit and a first switched power domain on a second portion of the integrated circuit, separated by at least a first buffer cell, the method comprising the steps of: receiving, at the first buffer cell, a first set of one or more data signals from the main power domain; receiving, at the first buffer cell, a first buffer control signal; in response to the first buffer control signal, either (a) passing the first set of one or more data signals to the first switched power domain or (b) restricting the first set of one or more data signals from reaching the first switched power domain; receiving a first power-down control signal; and disconnecting the first switched power domain from a power supply in response to the first power-down control signals; wherein the step of disconnecting the first switched power domain from a power supply is performed a predetermined time interval after the step of receiving the first buffer control signal.