Patent ID: 8223541

Claim:
A non-volatile semiconductor memory device, comprising: a non-volatile memory cell array for recording multiple values by setting a plurality of different threshold voltages to each memory cell transistor, wherein each memory cell transistor is connected in series between selection transistors on two terminals of a selected bit line; and a control circuit for controlling programmed data of the memory cell array, wherein the control circuit records two values for at least a plurality of first memory cell transistors respectively adjacent to the selection transistors on the two terminals, and records more than three multiple values for a plurality of second transistors other than the first memory cell transistors, and sets a programming/verifying voltage of the first memory cell transistors recorded by the two values to a voltage which is lower than a verifying voltage for recording the data, and the verifying voltage for recording the data has a maximum threshold voltage level for a plurality of recorded data recorded by the multiple values.