Patent ID: 7626433

Claim:
A flip-flop circuit comprising input terminals to provide a differential clock signal; output terminals to provide a differential output signal; differential amplifiers, each of the differential amplifiers comprising at least two transistors, the at least two transistors comprising collectors, each collector being part of one of plural series circuits containing a resistor, the series circuits being positioned between a power supply potential terminal and a first shared emitter node and/or a second shared emitter node, sets of the collectors being interconnected to form a D flip-flop structure, the output terminals being at an output of at least one differential amplifier; a first current source to connect the first shared emitter node to a reference potential terminal; a second current source to connect the second shared emitter node to the reference potential terminal; a first switch directly connected to the power supply potential terminal and directly connected to the first shared emitter node, the first switch having a first control terminal that comprises part of the input terminals; and a second switch directly connected to the supply potential terminal and directly connected to the second shared emitter node, the second switch having a second control terminal that comprises part of the input terminals.