Patent ID: 8593175

Claim:
A device, comprising: at least one chip comprising: a state machine lattice comprising: a plurality of blocks each comprising a plurality of rows, each of the rows comprising a plurality of programmable elements, wherein a particular one of the programmable elements is configured to output a signal based on a detection of a condition; and at least one of the rows of a particular one of the blocks further comprising a Boolean logic cell configured to be selectively coupleable to any of the programmable elements in any of the plurality of rows of the particular one of the blocks, wherein the Boolean logic cell is configured to output a result of a logical function, wherein the logical function is determined by programming an input of the Boolean logic cell to be either inverted or non-inverted, programming an output of the Boolean logic cell to be either inverted or non-inverted, and programming either an AND gate or an OR gate as a final output of the Boolean logic cell; wherein the Boolean logic cell comprises a mask input configured to receive a masking input signal that masks the input of the Boolean logic cell.