Patent ID: 8214418

Claim:
A method of combining binary numbers, comprising: (a) receiving a first binary number having a first sign bit and a predetermined number N 1 of magnitude bits; (b) receiving a second binary number having a second sign bit and a predetermined number N 2 of magnitude bits; (c) combining said N 1 magnitude bits with a third binary number having predetermined number M 1 bits to thereby form a fourth binary number in a first combining device; (d) combining said N 2 magnitude bits with a fifth binary number having predetermined number M 2 bits to thereby form a sixth binary number in a second combining device; (e) decoding said first and second sign bits to thereby form a control signal; (f) combining said fourth binary number with said sixth binary number as a function of said control signal to thereby form a seventh binary number in a third combining device; (g) selectively applying a two's complement negation to said seventh binary number as a function of said first sign bit to thereby provide an eighth binary number; and (h) providing said eighth binary number to a digital processing device to thereby modify the output of said digital processing device.