Patent ID: 6867636

Claim:
A circuit arrangement for controlling a resistance between a first and a second terminal, which circuit arrangement comprises a first and second pair of transistors, characterized in that the emitter of the first transistor in the first pair of transistors and the collector and the base of the first transistor in the second pair of transistors am connected to the first terminal forming a first point of connection, and the emitter of the second transistor in the first pair of transistors and the collector and the base of the second transistor in the second pair of transistors are connected to the second terminal forming a second point of connection in that the two collectors of the first pair of transistors and the two bases of the first pair of transistors are connected to a third point of connection, and in that the two emitters of the second pair of transistors are connected to a fourth point of connection, and characterized in that the respective first transistor in the first and second pairs of transistors is arranged to be larger by an area factor than the respective second transistor in the first and second pairs of transistors.