Patent ID: 7065629

Claim:
A GPS receiver comprising: address translation logic adapted to provide a plurality of translated addresses each based on an address from memory access logic; said memory access logic adapted to provide each said address to said address translation logic; memory adapted to store data in a plurality of memory locations corresponding to said plurality of translated addresses; and circuitry adapted to provide said data to said memory based on a signal received by the GPS receiver, wherein said data comprises a plurality of subsets each having a plurality of data elements; wherein said address translation logic provides said plurality of translated addresses based on organizing said data such that each of said plurality of data elements associated with each of said plurality of subsets are grouped together in said memory, each of said plurality of subsets corresponds to results of a correlation of said signal with a generated frequency and a generated code at a one of a plurality of time offsets, and each of said plurality of data elements in each of said plurality of subsets corresponds to a partial correlation sample from a time limited accumulation of data from the results of the correlation of said signal with said generated frequency and said generated code at said one of said plurality of time offsets.