Patent ID: 8875070

Claim:
A method for checking for reliability problems, comprising: receiving, by a computer system and storing on a non-transitory medium, a netlist of a circuit having at least one MOS transistor that includes a first MOS transistor, the first MOS transistor having a channel length; based on a parameter associated with said first MOS transistor, selecting the first MOS transistor to be simulated as at least a first transistor and a second transistor in series, the first transistor and the second transistor having a first channel length and a second channel length, respectively, the first channel length and the second channel length being less than the channel length of the first MOS transistor; simulating the circuit with the first transistor and the second transistor in place of the first MOS transistor; based on the results of the simulation, determining a device degradation for the first transistor and a device degradation for the second transistor; creating a degraded netlist having the first transistor degraded by the device degradation for the first transistor and having the second transistor degraded by the device degradation for the second transistor; storing the degraded netlist on the non-transitory medium; and, simulating the circuit with the first transistor degraded by the device degradation for the first transistor and the second transistor degraded by the device degradation for the second transistor in place of the first MOS transistor.