Patent ID: 7354855

Claim:
A manufacturing method of a semiconductor integrated circuit device, comprising the steps of: (a) forming a semiconductor element over the main surface of a semiconductor substrate and forming at least one first-level interconnect over the semiconductor element; (b) forming a first interlayer insulating film over the first-level interconnect and forming a first stopper film in the first interlayer insulating film; (c) forming a first antireflective film over the first interlayer insulating film and forming thereover a first photoresist film; (d) etching the first antireflective film, the first interlayer insulating film and first stopper film with the first photoresist film as a mask to form a first via hole in the first interlayer insulting film; (e) removing the first photoresist film and first antireflective film and then filling a first filler inside of the first via hole; (f) after the step (e), forming a second photoresist film over the first interlayer insulating film without using an antireflective film; (g) etching, with the second photoresist film as a mask, the first interlayer insulating film in a region including a region in which the first via hole has been formed, thereby forming a first interconnect trench in the first interlayer insulating film over the first stopper film; (h) removing the second photoresist film and first filler and then filling a metal film in the first interconnect trench and first via hole to form a second-level interconnect, wherein the first stopper film is made of a material having a low optical reflectance and utilized as an antireflective film when the second photoresist film formed over the first interlayer insulating film is exposed and a pattern of the first interconnect trench is transferred thereto.