Patent ID: 7483319

Claim:
An apparatus, comprising: a dynamic memory comprising a plurality of data storage blocks configured to store data, wherein the plurality of data storage blocks comprises a plurality of faultless data storage blocks and one or more faulty data storage blocks, each faulty data storage block having one or more faulty storage locations, and wherein the data to be stored in each faulty data storage block has an error correction code that is associated with an error correction method selected based at least in part on the amount of faulty storage locations in the faulty data storage block; and a memory management module coupled to the dynamic memory and configured to: read back data stored in an addressed one of the plurality of data storage blocks; determine whether the addressed data storage block is a faulty data storage block, and if the addressed data storage block is determined to be a faulty data storage block, further: determine the selected error correction method for the faulty data storage block, and correct the read back data using the associated error correction code and in accordance with the determined error correction method.