Patent ID: 7803682

Claim:
A semiconductor memory device comprising a plurality of memory transistors each having: a floating gate electrode including, in a cross section taken along a bit line direction, a first conductive film in contact with a gate insulating film, first sidewall insulating films opposed to each other across the first conductive film, a second conductive film provided on the first sidewall insulating films and the first conductive film, and a first antioxidation film provided between the first and second conductive films, the first antioxidation film being in contact with the first and second conductive films; an interelectrode insulating film provided on the second conductive film; and a control gate electrode including a third conductive film provided on the interelectrode insulating film, a fourth conductive film provided on the third conductive film, and a second antioxidation film provided between the third and fourth conductive films, the second antioxidation film being in contact with the third and fourth conductive films, dimensions of the second and third conductive films along the bit line direction in a cross section being larger than a dimension of the first conductive film along the bit line direction in the cross section.