Patent ID: 8587101

Claim:
A power quad flat no-lead (PQFN) semiconductor package comprising: a leadframe comprising a plurality of die pads; a driver integrated circuit (IC) coupled to a first die pad of the leadframe; a plurality of vertical conduction power transistors including a first group of vertical conduction power transistors coupled to a common die pad of the leadframe separated from the first die pad, and a second group of vertical conduction power transistors individually coupled to separate die pads of the leadframe; the common die pad and the separate die pacts being exposed at a bottom surface of the PQFN semiconductor package for increased thermal conductivity; a top surface electrode of one of the first group of vertical conduction power transistors being electrically connected to a bottom surface electrode of one of the second group of vertical conduction power transistors; at least one wirebond providing direct electrical connection between the driver IC and one of the plurality of vertical conduction power transistors.