Patent ID: 8105897

Claim:
A method for fabricating flash memory devices, the method comprising: providing a semiconductor substrate; forming a plurality of isolation regions on portions of the semiconductor substrate; forming a plurality of floating gate structures from at least a first polysilicon layer overlying the semiconductor substrate, the plurality of floating gate structures including a first floating gate structure, a second floating gate structure, and a third floating gate structure, the first floating gate structure being spaced from the second floating gate structure by at least a first isolation region, the second floating gate structure being spaced from the third floating gate structure by at least a second isolation region, the first isolation region and the second isolation region being from the plurality of isolation regions; forming a second polysilicon layer overlying the first floating gate structure, the second floating gate structure, and the third floating gate structure; causing formation of an upper surface provided on the second polysilicon layer, the upper surface having a first recessed region having a first depth within a first vicinity overlying the first isolation region and a second recessed region having a second depth within a second vicinity overlying the second isolation region, the first recessed region being between a first elevated region within a vicinity overlying the first floating gate structure and a second elevated region within a vicinity overlying the second floating gate structure, the second recessed region being between the second elevated region and a third elevated region within a vicinity overlying the third floating gate structure; depositing a dielectric material overlying the upper surface provided on the second polysilicon layer to fill the first recessed region and the second recessed region to form an upper surface region and cover the first elevated region, the second elevated region, and the third elevated region; subjecting the upper surface region to a chemical mechanical polishing process to remove a first thickness of the dielectric material while maintaining a first portion of the dielectric material within the first recessed region and while maintaining a second portion of the dielectric material within the second recessed region to form an exposed region of the dielectric material, and maintaining attachment of the second polysilicon layer to the first floating gate structure, second floating gate structure, and third floating gate structure; and subjecting the exposed region of the dielectric material to the chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the dielectric material.