Patent ID: 7203106

Claim:
An integrated semiconductor memory, comprising: a memory cell array with memory cells arranged in a first and a second memory area of the memory cell array along row and column lines, the row and column lines in the first and second memory areas of the memory cell array each being addressed using an address for read and write access to the memory cells arranged along the row and column lines, a faulty row and column line in the first memory area being replaced with a row and column line in the second memory area; an addressing circuit for addressing the row and column lines in the first and second memory areas; a data generator circuit connected to the memory cell array for generating data, the data generated by the data generator circuit being stored in the memory cells of the memory cell array, the addressing circuit addressing one of the row and column lines in the first memory area and the second memory area, or, upon detection of one of the faulty row and column lines in the first memory area, addressing the one of the row and column lines in the second memory area replacing the one of the faulty row and column lines in the first memory area, the data generator circuit generating an initialization data item to initialize the memory cells in the first and second memory areas, the data generator circuit generating identification data to identify the row and column lines; and an evaluation circuit connected to the memory cell array for generating an output data item, the evaluation circuit receiving data from memory cells arranged along the addressed row and column lines in the first and second memory areas, and generating the output data item with a data value stored most often in the memory cells arranged along the addressed row and column lines.