Patent ID: 8664113

Claim:
A method for forming an integrated circuit (IC) having a multilayer interconnect structure, comprising: supplying a substrate having thereon an N th dielectric, in or on which it is desired to form a multi-layer interconnection having lower conductor M N , upper conductor M N+1 and interconnecting via V N+1/N ; forming the lower conductor M N on the substrate with an upper surface of the lower conductor M N recessed below an upper surface of the N th dielectric; providing an (N+1) th dielectric above the N th dielectric and the upper surface of the lower conductor M N ; etching an (N+1) th cavity through the (N+1) th dielectric from a desired location of the upper conductor M N+1 and exposing the upper surface of the lower conductor M N ; filling the (N+1) th cavity with an electrical conductor adapted to form the upper conductor M N+1 and the connecting via V N+1/N , and make electrical contact with the upper surface of the lower conductor M N ; and determining whether or not a desired multilevel interconnection stack having N=Q total interconnection levels is complete, and if not: optionally removing conductor material in the (N+1) th cavity to lower an upper surface of the upper conductor M N+1 below an upper surface of the (N+1) th dielectric; and then incrementing N by one and repeating providing, etching, filling, querying, and removing for any or all desired successive interconnection level N up to N=Q−1.