Patent ID: 8250342

Claim:
A digital signal processing engine architecture, comprising: instruction memory for storing a plurality of instructions including a first instruction; the first instruction having at least one first opcode; the at least one first opcode being selected from a group consisting of a first control opcode, a first digital signal processing opcode, and a first memory opcode; a digital signal processing engine including a control block, a digital signal processing core, and a memory interface; the control block coupled to the instruction memory to obtain the first control opcode; the digital signal processing core coupled to the instruction memory to obtain the first digital signal processing opcode, the digital signal processing core configurable at least for multiplication of two operands; the memory interface coupled to the instruction memory to obtain the first memory opcode, the memory interface comprising a plurality of memory control blocks, wherein each memory control block corresponds to a predetermined memory opcode of a Very Large Instruction Word stored in the instruction memory, and the plurality of memory control blocks are greater or equivalent in number to a maximum number of memory opcodes in any of the plurality of instructions stored in the instruction memory; and the control block, the digital signal processing core, and the memory interface are separate pipelines at least two of which have different numbers of stages.