Patent ID: 8675443

Claim:
A memory structure for a display device, comprising: a data display memory, comprising; N sub-memories, each comprising M memory blocks divided according to an address, N being a positive integer, M being a positive integer greater than 2; N×M arbiters, each M arbiters respectively coupled to the M memory blocks in each of the sub-memories; and a memory controller, coupled to the N×M arbiters, for generating N×M sets of output request signals and output address signals according to an input signal set of an input request signal and an input address signal, and transmitting to the N×M arbiters to sequentially control the N×M arbiters, wherein the memory controller is responsive to said input signal set when the input request signal is a series-in pulse signal, to sequentially generate pulses in the N×M output request signals, so that a cycle period of each of the N×M output request signals is longer than a cycle period of the input request signal.