Patent ID: 8248130

Claim:
A duty cycle correction circuit for correcting the duty cycle of an input clock signal, comprising: a pulse-width control block for generating an adjusted clock signal, wherein the pulse-width control block receives the input clock signal and a control signal, wherein pulse-width of the input clock signal is adjusted based on the control signal to generate the adjusted clock signal; a first buffer chain for generating a first clock signal using the adjusted clock signal, wherein the first buffer chain comprises an even count of inverters and a pass transistor; and a second buffer chain for generating a second clock signal using the adjusted clock signal, wherein the second buffer chain comprises an odd count of inverters; a first duty cycle-to-voltage converter, connected to the first buffer chain, for generating a first duty cycle signal representing the duty cycle of the first clock signal; a second duty cycle-to-voltage converter, connected to the second buffer chain, for generating a second duty cycle signal representing the duty cycle of the second clock signal; a first level shifter, connected to the first duty cycle-to-voltage converter, for level shifting the first duty cycle signal by a predetermined value to generate a first level shifted signal; a second level shifter, connected to the second duty cycle-to-voltage converter, for level shifting the second duty cycle signal by the predetermined value to generate a second level shifted signal; a differential amplifier, connected to the first and second level shifters for receiving the first and second level shifted signals and generating the control signal; and a self-bias generator, connected to the first and second level shifters for receiving the first and second level shifted signals, and generating a self-bias signal used to bias the differential amplifier.