Patent ID: 7564059

Claim:
An electronic equipment having a semiconductor device, said semiconductor device comprising: a semiconductor layer formed over a substrate having an insulating surface, the semiconductor layer comprising at least a first channel region, a first impurity region and a second impurity region with the first channel region therebetween, a third impurity region, a second channel region between the second and third impurity regions, a fourth impurity region between the first impurity region and the first channel region, a fifth impurity region between the first channel region and the second impurity region, a sixth impurity region between the second impurity region and the second channel region and a seventh impurity region between the second channel region and the third impurity region wherein the second impurity region is contiguous to the fifth impurity region and the sixth impurity region; and a first gate electrode and a second gate electrode formed over the semiconductor layer with a gate insulating film interposed therebetween wherein each of the first gate electrode and the second gate electrode has tapered portions, wherein the first impurity region, the second impurity region and the third impurity region contain an impurity at a first concentration, wherein the fourth impurity region, the fifth impurity region, the sixth impurity region and the seventh impurity region contain the impurity at a lower concentration than the first concentration, wherein the first gate electrode overlaps the first channel region and the second gate electrode overlaps the second channel region; wherein the fourth impurity region is partially overlapped with the first gate electrode; wherein the fifth impurity region is completely overlapped with the first gate electrode; and wherein the sixth impurity region is completely overlapped with the second gate electrode.