Patent ID: 8028254

Claim:
A method for determining manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device, comprising: selecting a plurality of target edge pairs from mask layout data of the lithographic mask, for determining a manufacturing penalty in making the lithographic mask, the mask layout data comprising a plurality of polygons, each polygon having a plurality of edges, each target edge pair defined by two of the edges of one or more of the polygons; determining the manufacturability of the lithographic mask by a computer, including determining the manufacturing penalty in making the lithographic mask, where determining the manufacturing penalty is based on the target edge pairs as selected, and where determining the manufacturability of the lithographic mask comprises using continuous derivatives characterizing the manufacturability of the lithographic mask on a continuous scale; and, outputting the manufacturability of the lithographic mask by the computer, where the manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask, wherein determining the manufacturability of the lithographic mask, including determining the manufacturing penalty in making the lithographic mask, comprises: for a selected target edge pair having a first edge and a second edge that belong to a same polygon and that are at least substantially parallel to one another, determining a manufacturing shape penalty resulting from the selected target edge pair, the manufacturing shape penalty related to a penalty incurred in manufacturing the lithographic mask due to a shape of the same polygon, wherein determining the manufacturing shape penalty comprises evaluating P shape =P gap — size ×P jog — stair ×P aspect — ratio — i — a ×P aspect — ratio — j — a ×P overlap , where P shape denotes the manufacturing shape penalty, P gap size denotes a manufacturing penalty owing to a size of a gap between the first and the second edges, P jog — stair denotes a manufacturing penalty owing to whether the first and the second edges define a jog shape or a stair shape, P aspect — ratio — i — a denotes a manufacturing penalty owing to an aspect ratio of the first edge denoted as i relative to a size of a gap between the two edges i and j, P aspect — ratio — j — a denotes a manufacturing penalty owing to an aspect ratio of the second edge denoted as j relative to the size of a gap between the two edges i and j, and P overlap denotes a manufacturing penalty owing to a degree of overlap between the first and the second edges, and wherein P shape , P gap — size , P jog — stair , P aspect — ratio — i — a , P aspect — ratio — j — a , and P overlap are smoothly varying continuous functions, as opposed to non-smoothly varying discontinuous functions.