Patent ID: 7859910

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of word lines which connect a plurality of memory cells; a parameter storage part which stores a parameter related to a programming voltage which is applied to a word line connected to a memory cell to be programmed with data; a word line selection circuit which selects a word line among said plurality of word lines which is connected to a memory cell to be programmed with data; a voltage application circuit which applies a programming voltage to a word line according to said parameter, said word line being selected by said word line selection circuit; a verify circuit which performs verification of data which is programmed to a plurality of memory cells which are connected to said word line selected by said word line selection circuit; a control part which outputs a signal for selecting a word line to said word line selection circuit, and repeats the operations of said voltage application circuit until said verification by said verify circuit is successful; a calculation circuit which calculates an average value of the number of times said control part repeats said operations of said voltage application circuit per each word line; and a parameter setting circuit which sets said parameter using said average value calculated by said calculation circuit.