Patent ID: 6914471

Claim:
A method for controlling a dual-slope integrator circuit, the integrator circuit having an integrating capacitor, a reset input for receiving a reset signal that is used in maintaining a reset state of the integrating capacitor, and an integrator input for receiving a signal to be integrated, said method comprising the steps of: a) in response to an original input signal, generating the reset signal that is provided to the reset input and that has a predetermined reset time period; b) simultaneous with step a), generating a delayed input signal by introducing a predetermined delay period into the original input signal, the delay period being longer than the reset time period; and c) with reference to the original input signal and the delayed input signal, generating a trigger signal that is provided to the integrator input for enabling charging operation of the integrating capacitor during a charging period that starts from the end of the reset time period and that terminates at a lagging edge of the delayed input signal.