Patent ID: 8546207

Claim:
A method for fabricating a semiconductor wafer comprising an active silicon layer and having a structure of group III-V layers for the integration of silicon components comprising high electron mobility transistors using the structure of group III-V layers, the method comprising the steps of: providing a substrate wafer whereon the active silicon layer, the active silicon layer comprising a first region and a second region, and having an isolation trench positioned therebetween to electrically insulate the first and second regions; fabricating a patterned layer stack having an intermediate layer for lattice parameter adaptation and positioned on the active silicon layer over at least a part of the first region, the isolation trench, and at least a part of the second region; a III-V semiconductor layer positioned above the intermediate layer; and a III x III 1-x -V semiconductor layer positioned above the III-V semiconductor layer; forming an electrode over a part of the III x III 1-x -V semiconductor layer; wherein the substrate wafer comprises a buried insulation layer on which the active silicon layer is formed, such that the first and second regions are delimited by the buried insulation layer and the isolation trench.