Patent ID: 8202773

Claim:
A process of forming an integrated circuit comprising the steps of: forming PMOS transistor by a process further including the steps of: forming a PMOS nitrogen containing barrier layer on a top surface of a PMOS gate dielectric layer; forming a PMOS low oxygen metal layer with a work function greater than 5 electron volts and an oxygen concentration less than 2 percent, on a top surface of said PMOS nitrogen containing barrier layer; forming a PMOS oxygen rich metal layer with a work function greater than 5 electron volts and an oxygen concentration greater then 10 percent, on a top surface of said PMOS low oxygen metal layer; and forming a PMOS top metal layer with a work function greater than 5 electron volts, on a top surface of said PMOS oxygen rich metal layer; and forming an NMOS transistor by a process further including the step of forming a metal gate layer with a work function less than 5 electron volts and an oxygen concentration less than 2 percent, on a top surface of an NMOS gate dielectric layer.