Patent ID: 7480755

Claim:
A system, comprising: a first interrupt vector table configured to facilitate locating an interrupt service routine associated with handling one of a first set of interrupt types; a first address register configured to provide an address associated with the first interrupt vector table and to facilitate locating an entry in the first interrupt vector table; a second interrupt vector table configured to facilitate locating an interrupt service routine associated with handling one of a second set of interrupt types; a second address register configured to provide an address associated with the second interrupt vector table and to facilitate locating an entry in the second interrupt vector table; a trap mode register operably connected to a computer system, the trap mode register being configured: to receive, upon the occurrence of a trap in the computer system, a trap data associated with the trap, where the trap data includes an address associated with one or more of, a device responsible for causing the trap, and a memory location responsible for causing the trap, and to facilitate selecting between the first address register and the second address register to provide an address associated with an interrupt vector table, where the selecting is based, at least in part, on the address in the trap data; and an initialization logic configured to initialize the trap made register, the second interrupt vector table, and the second address register. and to provide a signal for controlling, at least in part, an operating system initialization logic operably connected to the computer system.