Patent ID: 8767762

Claim:
An apparatus comprising: physical medium dependent (PMD) sublayer logic that is configured to communicate with a communications medium; physical medium attachment (PMA) sublayer logic that is coupled to the PMD logic; forward error correction (FEC) sublayer logic that is coupled to the PMA sublayer logic; and physical coding (PCS) sublayer logic that is configured to communicate with an interface, wherein the PCS sublayer logic includes gearbox circuitry having: a transmit path that is configured to receive data in a first clock domain and that is coupled to transmit data in a second clock domain to the FEC sublayer logic; a first read pointer circuit that is coupled to the transmit path; a write pointer circuit that is coupled to the transmit path; a receive path that is coupled to receive data in the second clock domain from the FEC sublayer logic and that is configured to output data in the first clock domain; and a second read pointer circuit that is coupled to the receive path, wherein the first read pointer circuit, the second read pointer circuit, and the write pointer circuits are each configured to detect gaps between the first and second clock domains.