Patent ID: 7384843

Claim:
A method of fabricating a flash memory device, the method comprising: forming a trench region defining a plurality of parallel active regions in a semiconductor substrate; forming an isolation layer in the trench region; forming floating gate patterns separated by a first width on the active regions; forming a capping layer on exposed surfaces of the isolation layer and the floating gate patterns; anisotropically etching the capping layer to expose the isolation layer between the floating gate patterns, wherein sidewall and upper surfaces of the floating gate patterns remain covered by a residual etched portion of the capping layer; anisotropically etching the exposed isolation layer using the residual etched portion of the capping layer as an etch mask to form a recessed region between the floating gate patterns having a maximum width less than the first width; removing the residual etched portion of the capping layer to expose the floating gate patterns; forming an inter-gate dielectric layer over the recessed region and the floating gate patterns; forming a control gate conductive layer on the inter-gate dielectric layer; and, sequentially patterning the control gate conductive layer, the inter-gate dielectric layer, and the floating gate patterns to form a plurality of control gate electrodes across the active regions; and a plurality floating gates between the control gate electrodes and the active regions; wherein each of the control gate electrodes comprises a control gate extension formed between the floating gate patterns.