Patent ID: 8283714

Claim:
A semiconductor memory device, comprising: a first active region and a second active region, wherein each of the first active region and the second active region has a first side surface and a second side surface, and the first side surface of the first active region faces at least a portion of the second side surface of the second active region; a gate electrode disposed between the first side surface of the first active region and the second side surface of the second active region; a word line connected to the gate electrode; and a bit line going across any one of the first and second active regions, wherein the first active region and the second active region are spaced apart in a widthwise direction and the first active region and the second active region, which shares the gate electrode with the first active region, are staggered in a lengthwise direction, and wherein the first active region and the second active region are staggered in the lengthwise direction in that the first active region extends from a first lengthwise position in the lengthwise direction to a second lengthwise position and the second active region extends from the second lengthwise position in the lengthwise direction to a third lengthwise position, wherein the second lengthwise position lies between the first lengthwise position and the third lengthwise position in the lengthwise direction.