Patent ID: 7158425

Claim:
A memory circuit, comprising: an output data bus; a memory array receiving a memory address and providing output data from a memory access using the memory address, the memory array comprising a plurality of memory blocks, and a control circuit providing a timing signal that is asserted at a first predetermined time earlier than a second predetermined time when the output data from the memory access is expected to be ready at the output data bus; a redundant memory circuit receiving the memory address and the timing signal, and providing output data when the memory address corresponds to a stored memory address in the redundant memory circuit, the output data being provided at the first predetermined time, in accordance with the timing signal; and a selection circuit selecting, for output at the second predetermined time on the data output bus, between the output data of the memory array and the output data of the redundant memory circuit; wherein the memory array provides a second timing signal which is asserted to indicate the second predetermined time.