Patent ID: 7544522

Claim:
A fabrication method of a semiconductor integrated circuit device comprising the steps of: (a) preparing a wafer in which a wafer process is substantially completed, and bonding pad openings or bump electrodes over bonding pads are formed in a plurality of chip regions respectively in a process of fabricating a semiconductor integrated circuit; (b) performing an appearance test for at least the bonding pad openings or the bump electrodes and peripheries of them in each of the chip regions over the wafer; and (c) performing the probe test for a second group of chip regions that do not belong to the first group using the membrane probe, without performing the probe test for a first group of one or more chip regions, which are inappropriate to be subjected to the probe test using the membrane probe, among the chip regions, based on a result of the appearance test when the chip regions are subjected to a probe test using a membrane probe, wherein the appearance test of the step (b) comprises the following subordinate steps of: (1) performing the appearance test to the bonding pad openings or the bump electrodes and peripheries of them at a first accuracy; and (2) performing the appearance test to portions other than the bonding pad openings or the bump electrodes and the peripheries of them at a second accuracy rougher than said first accuracy.