Patent ID: 7618899

Claim:
A method of fabricating a semiconductor integrated circuit device, the method comprising: forming a hard mask layer on a base layer; forming a sacrificial hard mask layer on the hard mask layer; forming a line sacrificial hard mask layer pattern by patterning the sacrificial hard mask layer, wherein the line sacrificial hard mask layer comprises a plurality of lines parallel to a first direction having spaces defined therebetween; planarizing an upper surface of the line sacrificial hard mask layer pattern by coating a high molecular organic material layer on the line sacrificial hard mask layer pattern; patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in the form of a plurality of lines parallel to a second direction having spaces defined therebetween, the second direction not parallel to the first direction; forming a matrix sacrificial hard mask layer pattern arranged in a matrix shape by removing the high molecular organic material pattern; forming a hard mask layer pattern arranged in a matrix shape by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask; and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask.