Patent ID: 8078797

Claim:
A memory storage system, comprising: a nonvolatile memory unit having storage locations organized into two or more sub-blocks, each sub-block configured to store one or more sectors of information and each sub-block being individually addressable and erasable, two or more sub-blocks defining a block; and a memory controller coupled to the non-volatile memory unit for receiving user data and overhead of sectors of information from a host, the received user data of sectors of information being identified by addresses of a predetermined order; wherein the memory controller is configured to program first user data of first sectors of the sectors of information to storage locations of one or more first sub-blocks of a particular block, the particular block identifiable by a virtual physical block address, the virtual physical block address correlated to a predetermined set of host-provided logical block addresses and selectable based upon identification of a free storage location within the non-volatile memory unit; wherein the memory controller is configured to program second user data of second sectors of the sectors of information to storage locations of one or more second sub-blocks of the particular block; wherein the memory controller is configured to program the overhead for both the first user data of the first sectors of the sectors of information and the second user data of the second sectors of the sectors of information to the one or more second sub-blocks; and wherein the memory controller is configured to program two or more sectors of information to the storage locations of the particular block substantially concurrently.