Patent ID: 8723254

Claim:
A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed in a surface portion of said first semiconductor layer on one thickness direction side; a third semiconductor layer of the first conductivity type selectively formed in a surface portion of said second semiconductor layer on the one thickness direction side; a gate electrode buried in a gate trench passing through said second and third semiconductor layers to reach said first semiconductor layer, with a gate insulating film interposed therebetween; a fourth semiconductor layer of the second conductivity type formed in a portion of said second semiconductor layer, the fourth semiconductor layer forming a bottom of a contact trench, the contact trench passing through said third semiconductor layer to reach said second semiconductor layer, said fourth semiconductor layer having a higher concentration of the second conductivity type impurity than said second semiconductor layer, said fourth semiconductor layer and said first conductor layer interfacing along a horizontal plane surface, and said second semiconductor layer and said third semiconductor layer interfacing along the same horizontal plane surface; and a contact electrode buried in said contact trench and in contact with said third and fourth semiconductor layers, said gate electrode including: an internal gate electrode buried in a part of said gate trench including its bottom; and a low-resistance gate electrode buried in a remaining part of said gate trench and in contact with said internal gate electrode, said low-resistance gate electrode having a lower resistance than said internal gate electrode, and said contact electrode including: a first conductor layer buried in said contact trench; and a second conductor layer that is in contact with said first conductor layer and covers said third semiconductor layer and said gate electrode with an interlayer insulating film interposed therebetween, said first conductor layer and said second conductor layer being made of different materials, and said low-resistance gate electrode and said first conductor layer being made of a same material.