Patent ID: 8008775

Claim:
A circuit component connected to a wirebond, comprising: a silicon substrate; a MOS device in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a contact pad over said silicon substrate; a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said contact pad, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises an insulating nitride; a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said first polymer layer is over said contact point; a coil on said first polymer layer; an interconnect on said first polymer layer and on said contact point, wherein said interconnect is connected to said contact point through said second opening and to said wirebond, wherein said coil and said interconnect are provided by a patterned circuit layer on said first polymer layer and on said contact point, wherein said patterned circuit layer has a sheet resistance smaller than 7 milliohms per square, wherein said patterned circuit layer comprises a glue layer, a seed layer on said glue layer, and an electroplated metal layer on said seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated metal layer; and a second polymer layer over said first polymer layer and over said patterned circuit layer.