Patent ID: 8618855

Claim:
A semiconductor device comprising a flip-flop circuit, the flip-flop circuit comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a first wiring; a second wiring; a third wiring; and a fourth wiring, wherein a first terminal of the first transistor is electrically connected to the first wiring, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, and a gate terminal of the first transistor is directly connected to a gate terminal of the fourth transistor, wherein a first terminal of the second transistor is electrically connected to the second wiring, and a gate terminal of the second transistor is directly connected to a second terminal of the third transistor, wherein a first terminal of the third transistor is electrically connected to the third wiring, and a gate terminal of the third transistor is directly connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor, wherein a first terminal of the fourth transistor is electrically connected to the second wiring, wherein a first terminal of the fifth transistor is electrically connected to the fourth wiring, and a gate terminal of the fifth transistor is electrically connected to the fourth wiring, wherein the gate terminal of the first transistor is electrically connected to a first terminal of a transistor for making the gate terminal of the first transistor into a floating state, wherein a second terminal of the transistor is electrically connected to the third wiring, wherein the first terminal of the third transistor is configured to receive a first signal through the third wiring, wherein the first terminal of the fifth transistor is configured to receive a second signal through the fourth wiring, wherein the first terminal of the first transistor is configured to receive a third signal through the first wiring, wherein the third signal is an inverted signal of the first signal, and wherein the third wiring is not electrically connected to the fourth wiring.