Patent ID: 7114062

Claim:
A central processing unit comprising, a first processor for executing program instructions a program counter and registers shared by said first processor, said program counter containing an indicator of the address of the next said program instruction to be performed, a function lookup unit sharing said program counter and registers, said first processor and said functional lookup unit sharing parallel access to said program counter and registers, said function lookup unit having, a lookup cache with a tag field, and a function indicator field, said lookup cache communicating with said program counter to determine the presence of a match between the contents of said tag field and said program counter indicator, upon finding a match between said tag field and said program counter indicator said function lookup unit assumes control of execution at said program instruction indicated by said program counter and upon finding no match said first processor assumes control of execution at said program instruction indicated by said program counter, a reconfigurable combinational array having logic functions available which provide a mapping from a beginning state on entry to a block of program instructions to an ending state on exit from said block of program instructions, said logic functions having identifiers in said function indicator field, said reconfigurable combinational array receiving a function indicator identifier from said lookup cache upon finding a match between said tag field and said program counter indicator, said functional indicator identifier causing said logic function to be executed in place of said block of program instructions starting at said program counter indicator.