Patent ID: 6927128

Claim:
A method of manufacturing a low voltage flash memory for integration into a single chip together with a logic circuit, the method comprising the steps of: growing a gate oxide layer by thermally oxidizing a semiconductor substrate in which element regions are defined, depositing a first polysilicon layer over an entire surface of the gate oxide layer, and patterning the first polysilicon layer to form a floating gate; depositing a dielectric layer on the semiconductor substrate and the floating gate, depositing a second polysilicon layer on the dielectric layer, and forming a gate pattern on the second polysilicon layer at a position corresponding to above the floating gate; etching exposed portions of the second polysilicon layer to form a control gate, etching portions of the dielectric layer exposed as a result to remove the same, and etching portions of the gate oxide layer that are, in turn, exposed as a result, after which the gate pattern is removed; performing ion injection directly into the gate oxide layer at an energy level sufficiently low whereby the ion injection is limited to a corner portion of the gate oxide layer at a predetermined angle to form an ion trap region and to decrease an operation voltage of the flash memory such that the operation voltage of the flash memory conforms with an operation voltage of the logic circuit, where the ion injection is performed with impurities selected from the group consisting of phosphorus, boron and arsenic; performing ion injection of impurities on exposed portions of the semiconductor substrate at a low concentration to form an LDD; depositing an insulating layer over the entire surface of the semiconductor substrate, and isotropically etching the insulating layer to form a spacer on the LDD and along side walls of the gate oxide layer, the floating gate, the dielectric layer, and the control gate; and forming a source/drain region on exposed regions of the semiconductor substrate by performing ion injection of impurities at a high concentration.