Patent ID: 6941257

Claim:
A data structure stored on a computer-readable medium for use in a computer-aided design and verification system for interconnecting instrumentation logic in a simulation model of a compiled digital circuit design that includes one or more design entities described utilizing a hardware description language (HDL), said data structure comprising: a first instrumentation entity descriptor field containing data representing a first instrumentation entity, the data representing said first instrumentation entity including a non-conventional HDL comment port mapping syntax processed by a post-compiler instrumentation load tool to instantiate said first instrumentation entity within at least one of said one or more design entities, wherein said non-conventional HDL comment port mapping syntax is recognized by an HDL compiler such that the HDL compiler does not instantiate said first instrumentation entity into the digital circuit design, said data representing said first instrumentation entity using the non-conventional comment port mapping syntax further including simulation event descriptor field containing data representing a simulation event having a designated event name and that is generated by said first instrumentation entity responsive to one or more input signals from said at least one of said design entities; and a second instrumentation entity descriptor field containing data representing a second instrumentation entity instantiated within at least one of said one or more design entities utilizing said non-conventional comment port mapping syntax, said second instrumentation entity descriptor field comprising an input port mapping field containing data for referencing the generated simulation event to an input port of said second instrumentation entity utilizing an extended event identifier, said extended event identifier including an event type identifier field that specifies a simulation event type and an event name field that includes said designated event name.