Patent ID: 6895519

Claim:
A system LSI having a plurality of ordinary operation modes and a plurality of special modes in response to clock frequencies supplied to a central processing unit, comprising: a first memory that stores a clock control library for controlling a clock frequency transition between said ordinary operation modes; a system control circuit which has a register, wherein said system control circuit carries out the clock frequency transition between said ordinary operation modes and said special modes in response to a change of a value in said register, and also carries out the clock frequency transition among said ordinary operation modes in response to said clock control library; a clock generation circuit that receives a plurality of standard clocks, wherein said clock generation circuit generates a clock supplied to said central processing unit according to control by said system control circuit; and a second memory that stores an application program, wherein calling of said clock control library and changing of said register value are programmably controlled by said application program to enable user selectable clock frequency transitions, wherein said special modes comprise a first special mode in which clock supply to principal constituents of said central processing unit is halted, a second special mode in which clock supply to an entirety of said central processing unit is halted, and a third special mode in which supply of power to the entirety of said central processing unit is halted.