Patent ID: 8426280

Claim:
A method of fabricating a charge trap type non-volatile memory device, comprising: forming a tunnel insulation layer over a substrate; forming a charge trap layer over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; forming a charge barrier layer over the charge trap layer; forming a gate electrode conductive layer over the charge barrier layer; etching the gate electrode conductive layer, the charge barrier layer, the charge trap layer, and the tunnel insulation layer to form a charge trap structure; and forming an oxide-based spacer over sidewalls of the etched charge trap layer using an oxidation process so that the charge trap polysilicon thin layer has a recess portion and the oxide-based spacer extends inwardly to the recess portion of the charge trap polysilicon thin layer, wherein a lower surface of the charge trap nitride-based layer exposed by the recess portion slopes towards the charge trap polysilicon thin layer.