Patent ID: 8416576

Claim:
An integrated circuit card ( 100 ) including: a laminate ( 10 ) including: a core board ( 11 ) including an upper side ( 111 ), a lower side ( 112 ) and a plurality of apertures ( 14 ) defined therein from the upper side ( 111 ) to the lower side ( 112 ); a first conductive layer ( 12 a ) coated on an upper side ( 111 ) of the core board ( 11 ) and a plurality of apertures ( 13 ) are defined in the first conductive layer ( 12 a ), wherein some of the apertures ( 13 ) of the first conductive layer ( 12 a ) are in communication with the apertures ( 14 ) of the core board ( 11 ); a second conductive layer ( 12 a ) coated on a lower side ( 112 ) of the core board ( 11 ); a solder resist ( 15 ) coated on the first conductive layer ( 12 a ) and a plurality of apertures ( 16 ) are defined in the solder resist ( 15 ), wherein some of the apertures ( 16 ) are in communication with some of the apertures ( 14 ), wherein some regions of an upper side of the first conductive layer ( 12 a ) are exposed via the apertures ( 16 ); an upper metal finish ( 17 a ) coated on each of the regions of the upper side of the first conductive layer ( 12 a ) exposed through some of the apertures ( 16 ) that are not aligned with the apertures ( 14 ), wherein each of these metal finishes ( 17 a ) is used as a ball pad ( 17 a ), wherein the upper metal finish ( 17 ) also coated on each of the regions of the upper side of the first conductive layer ( 12 a ) exposed through the other apertures ( 16 ); and a lower metal finish ( 17 ) coated on regions of the second conductive layer ( 12 b ) exposed through the apertures ( 14 ) of the core board ( 11 ); a solder bump ( 20 a ) provided on each of the upper metal finishes ( 17 a ) located in the apertures ( 16 ) of the solder resist ( 15 ) that are not in communication with the apertures ( 14 ) of the core board ( 11 ), wherein each of the solder bumps ( 20 a ) includes a die-mount face ( 201 a ); and a solder bump ( 20 b ) provided on each of the lower metal finishes ( 17 ) located in the apertures ( 16 ) of the solder resist ( 15 ) that are in communication with the apertures ( 14 ) of the core board ( 11 ) and the upper metal finishes ( 17 ) located in the apertures ( 14 ) of the core board ( 11 ); wherein the solder bumps ( 20 a ) and the solder bumps ( 20 b ) are made simultaneously via one printing step; a semiconductor die ( 30 ) provided on the die-mount faces ( 201 a ); and a package ( 40 ) provided on the semiconductor die ( 30 ) and a region of the solder resist ( 15 ) around the semiconductor die ( 30 ).