Patent ID: 6950340

Claim:
A method for operating a plurality of adjacent nonvolatile memory cells, comprising: simultaneously erasing the plurality of nonvolatile memory cells from the high threshold nonconducting state (1) to the low threshold conducting state (0) by applying a positive programming pulse to a plurality of control gates of the plurality of adjacent nonvolatile memory cells while pulling a substrate common to all of the plurality of adjacent nonvolatile memory cells to a ground potential, wherein the positive programming pulse induces an erase primary charge transport of holes from the control gate to a floating charge-storage region of each of the cells; and simultaneously writing the plurality of nonvolatile memory cells from a low threshold conducting state (0) to a high threshold nonconducting state (1) by tying the substrate common to all of the plurality of adjacent nonvolatile memory cells to a plurality of drain nodes of the plurality of adjacent nonvolatile memory cells and applying a positive programming pulse to the drain nodes to capacitively pull the substrate of the plurality of cells to a positive potential while pulling the control gate of the cells to be written to a ground potential, wherein the positive programming pulse induces a write primary charge transport of holes from the floating charge-storage region of the plurality of cells to the control gate of the cells to be written.