Patent ID: 8055881

Claim:
A first computation node, comprising: an input port configured to be coupled to a first direct channel to directly couple the first computation node to a second computation node of a plurality of computation nodes, to enable the input port to directly receive input data from the second computation node, wherein the plurality of computation nodes are directly interconnected using direct channels, and preselected to execute a subset of a group of instructions partitioned from a program, and the plurality of preselected computation nodes include at least the first and second computation nodes; a first store configured to receive an instruction from an external source, and store the instruction, wherein the first store together with at least a second store of a third of the computation nodes form a frame of buffers spanning the plurality of computation nodes to store the subset of instructions prior to availability of operands of the subset of instructions; at least one execution unit configured to execute the instruction using the input data to produce output data; a first output port and a second output port configured to be respectively coupled to a second direct channel and a third direct channel to directly couple the first computation node to respective ones of the second computation node and the third computation node, to enable the output data to be selectively, but directly, provided to either the second computation node or the third computation node, via a corresponding one of the second or third direct channel, for execution of another one of the subset of instructions; and a router coupled with the at least one execution unit to route the output data to either a third output port or a fourth output port, for alternative selective provision to either the second computation node or the third computation node, via a transport channel, wherein the plurality of computation nodes are further interconnected via the transport channel.