Patent ID: 8872161

Claim:
An integrated circuit IC comprising: a substrate having a metal-oxide-semiconductor (MOS) region; first gate, source and drain regions of a first device in the MOS region, wherein the first gate region has a first length; a first nanowire set disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a first feature in the first source region and the first feature in the first drain region; second gate, source and drain regions of a second device in the MOS region, wherein the second gate region has a second length; and a second nanowire set disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a second feature in the second source region and the second feature in the second drain region, wherein if the first length is greater than the second length, the first diameter is less than the second diameter; and wherein if the first length is less than the second length, the first diameter is greater than the second diameter.