Patent ID: 8656214

Claim:
An apparatus comprising: a first memory array operable to store data and operable to connect to a next higher hierarchical level of memory; a second memory array operable to store a copy of the data and operable to connect to the next higher hierarchical level of memory; a first multiplexer coupled to the first memory array and operable to send the data to the first memory array to store therein, wherein the first memory array is operable to bypass the first multiplexer in response to outputting a requested data of a first read operation; and a second multiplexer coupled to the second memory array and operable to send the copy of the data to the second memory array to store therein, wherein the second memory array is operable to bypass the second multiplexer in response to outputting a requested copy of data of a second read operation, wherein the first and second multiplexers are operable to maintain coherence between the data in the first memory array and the copy of the data in the second memory array.