Patent ID: 6987412

Claim:
A method for latching and amplifying a capacitively coupled inter-chip communication signal, comprising: receiving an input signal on a capacitive receiver pad from a capacitive transmitter pad; feeding the input signal through an inverter to produce an output signal; feeding the output signal through a weakened inverter to produce a feedback signal; adjusting an RC time constant for the feedback signal so that the time constant for the feedback signal is significantly larger than the time constant for the transmitted signal from the capacitive transmitter pad, thereby ensuring that the feedback signal does not mask transitions of the transmitted signal; feeding the feedback signal back into an input of the inverter so as to form a latch for the input signal between the inverter and the weakened inverter; and establishing a high bias voltage, V H , with a high bias voltage generator and establishing a low bias voltage, V L , with a low bias voltage generator; wherein the high bias voltage generator includes a mechanism for adjusting the high bias voltage, V H ; wherein the low bias voltage generator includes a mechanism for adjusting the low bias voltage, V L ; wherein the weakened inverter is biased to produce the feedback signal that swings between the high bias voltage, V H , and the low bias voltage, V L ; and wherein V H is slightly higher than a switching threshold of the inverter, and V L is slightly lower than the switching threshold of the inverter, whereby the feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal received on the capacitive receiver pad.