Patent ID: 8320159

Claim:
A nonvolatile memory device comprising: a plurality of first wires extending in parallel with each other in a first direction within a first plane; a plurality of second wires extending in parallel with each other in a second direction within a second plane parallel to the first plane such that the plurality of second wires three-dimensionally cross the plurality of first wires, respectively; and memory cells provided to respectively correspond to three-dimensional cross-points of the first wires and the second wires; each of the memory cells including one resistance variable element and only one transistor; the transistor including a first main terminal, a second main terminal and a control terminal; the resistance variable element including a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode; the memory cells including a plurality of memory cells which are arranged along the first direction and configured such that a first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path extending in the first direction and sequentially connecting main terminals of the plurality of memory cells in series; and each of the memory cells being configured such that: the control terminal is connected to a first wire associated with the memory cell; the second electrode is a part of a second wire associated with the memory cell or is connected to the second wire associated with the memory cell; and the first electrode is a part of a series path associated with the memory cell or is connected to the series path associated with the memory cell.