Patent ID: 7195964

Claim:
A method for fabricating an integrated circuit comprising a nonvolatile memory cell comprising a first conductive gate and a conductive floating gate, wherein the floating gate overlies a channel region of the memory cell, wherein the channel region is part of a semiconductor region having a top surface, and the floating gate overlies a first surface portion of the top surface of said semiconductor region, the first surface portion being defined as an entire surface portion lying under the floating gate, the method comprising: (1) providing a first gate surface which is a surface of the first conductive gate; (2) forming a first dielectric on the first gate surface and a second dielectric on the entire first surface portion, the entire first surface portion having a first conductivity type, wherein at least a portion of the first dielectric and at least a portion of the second dielectric are formed simultaneously; and (3) forming the floating gate on the second dielectric; wherein the first dielectric is used to insulate the first gate from the floating gate and/or from another element of the integrated circuit.