Patent ID: 7577171

Claim:
A multiple bit stream interface that interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit, the multiple bit stream interface comprising: an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate; a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate; wherein the first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication Application Specific Integrated Circuit (ASIC) at a first bit rate; wherein the second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate; wherein the interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines; and wherein the transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines to minimize skew between the transmit data clock and each of the first group of lines and the second group of lines.