Patent ID: 7165231

Claim:
A method for an incremental behavioral validation of a digital design expressed in a hardware description language, comprising the steps of: (a) receiving a digital design expressed in a hardware description language; (b) providing means for; (1) permitting a user to classify testable parts of the design by inserting special comments, (2) permitting the user to observe results of a behavioral simulation of a testable part and to decide whether the testable part correctly implements the user's understanding of an informal design specification, and (3) permitting the user to modify the design in an attempt to correctly implement his understanding of the informal design specification; (c) selecting a classified testable part and creating a demonstration sequence for the testable part; (d) performing a behavioral simulation of the selected testable part by driving the simulation with the created demonstration sequence; (e) observing the results of the behavioral simulation and deciding whether the testable part correctly implements the user's understanding of the informal design specification; (f) if the testable part is a correct implementation, then continuing with step (g), else, continuing from step (h); (g) determining whether there are more as yet unselected classified testable parts, and if so, selecting a next classified testable part and creating a demonstration sequence for the selected testable part, and continuing from step (d), else, terminating the method; (h) modifying the design in an attempt to correctly implement the user's understanding of the informal design specification, and creating a demonstration sequence for the selected testable part of the modified design, and continuing from step (d).