Patent ID: 7172948

Claim:
A method for avoiding a step height over a readable laser marked portion of a process wafer comprising the steps of: providing a process wafer comprising active area trenches and at least one inactive area trench formed overlying at least a portion of a laser marked portion at the process wafer periphery; forming a filling layer over the active area trenches and the at least one inactive area trench to substantially fill the respective trenches; forming a resist layer comprising first patterned portions and second patterned portions, said first patterned portions overlying the active area trenches and second patterned portions disposed between the active area trenches and the at least one inactive area trenches, said first and second patterned portions formed separately from one another; removing the filling layer portions not covered by the resist layer; removing the resist layer to expose remaining filling layer portions; and, planarizing the wafer process surface including removing said remaining filling layer portions according to chemical mechanical polish (CMP) process wherein the active area trenches and the at least one inactive area trench including said laser marked portion are substantially co-planar.