Patent ID: 7524697

Claim:
A manufacturing method of a semiconductor integrated circuit device, comprising the steps of: (a) forming ordinary interconnections on a first major surface of a wafer; (b) forming re-interconnections including plural first metal film regions and plural second metal film regions over the ordinary interconnections; (c) forming a polymeric resin film over the re-interconnections; (d) forming plural first metal pad regions and plural second metal pad regions by forming openings through portions of the polymeric resin film which correspond to the first metal film regions and the second metal film regions, respectively, by a lithography technique; (e) forming bumps on the respective first metal pad regions; (f) after the step (e), dividing the wafer into plural semiconductor integrated circuit chips; (g) causing a bump formation surface, corresponding to the first major surface of the wafer, of a first semiconductor integrated circuit chip among the plural divisional semiconductor integrated circuit chips to be opposed to an electrode surface of a burn-in test socket, and performing a burn-in test in a state that the plural bumps on the bump formation surface and plural metal projection electrodes on the electrode surface are pressed against each other; and (h) after the step (g), separating the metal projection electrodes and the bumps of the first semiconductor integrated circuit chip from each other by pushing at least one of the plural second metal pad regions on the bump formation surface in such a direction that the first semiconductor integrated circuit chip and the electrode surface go away from each other by bringing at least one pushing member whose contact surface is narrower than the at least one second metal pad region into contact with the at least one second metal pad region.