Patent ID: 7721034

Claim:
A method for managing system management interrupt in a multiprocessor system, wherein the multiprocessor system comprises two or more processors, comprising: prior to all of the two or more processors entering a system management mode: initiating an interrupt handling sequence at a first processor in the system; initiating a timer in the system, wherein the expiration of the timer causes each of the processors of the system to enter the system management mode; and writing a code to a storage location to identify if the interrupt was caused by a reason code; causing all of the processors to enter system management mode following the expiration of the timer; and if it is determined that the interrupt was caused by a reason code and it is determined that a threshold level of errors has occurred: handling the interrupt at a processor of the system; and transmitting a signal to the processors of the system that are not handling the interrupt to cause these processors to exit system management mode.