Patent ID: 8737155

Claim:
An apparatus comprising: a first voltage generator to generate a first voltage to apply to a line used to access a memory cell of a memory device, wherein the first voltage is applied to the line used to access the memory cell when the memory cell is not being accessed; a second voltage generator to generate a second voltage to apply to the line used to access the memory cell when the memory cell is being accessed; a third voltage generator to generate a third voltage to apply to a line used to transfer data with the memory cell, wherein the line used to transfer data with the memory cell includes a bit line; a driver to selectively apply at least one of the first and second voltages to the line used to access the memory cell; a power controller to cause the first voltage generator to increase a value of the first voltage during a time interval after a refresh operation of the memory device, to cause the second voltage generator to reduce a value of the second voltage during the time interval after the refresh operation, and to cause the third voltage generator to increase a value of the third voltage after the refresh operation from a first positive value during the refresh operation to a second positive value immediately after the refresh operation; and a fourth voltage generator to generate a fourth voltage to apply to a substrate of the memory device, wherein the power controller causes the fourth voltage generator to increase a value of the fourth voltage during the time interval after the refresh operation.