Patent ID: 8330765

Claim:
A circuit arrangement, comprising: hardware logic configured to host a multithreaded rendering software pipeline using a plurality of parallel threads of execution, the multithreaded rendering software pipeline including a plurality of stages configured to process a plurality of image elements to render an image in a buffer; a rolling context data structure accessible by the plurality of stages in the multithreaded rendering software pipeline, the rolling context data structure configured to store a plurality of contexts, each context configured to store state data for at least one image element as the at least one image element is processed by the plurality of stages of the multithreaded rendering software pipeline; and control logic configured to associate each image element with a context in the rolling context data structure such that state data in a first context that is associated with a first image element is unaltered responsive to a change made to state data in a second context that is associated with a second image element during processing of the second image element by the multithreaded rendering software pipeline.