Patent ID: 7685554

Claim:
A processor-based method for determining data rates and data types at inputs and outputs of a plurality of functional blocks that are connected by a plurality of nets in an electronic design, wherein at least one of the functional blocks has a user-specified output data rate and output data type, comprising: generating in a computing system a directed graph of nodes and edges from the electronic design, wherein the directed graph has a node for each functional block, a node for each net, and an edge for each connection of a net with a functional block; decomposing the directed graph into an acyclic subgraph and at least one strongly connected subgraph, wherein the acyclic subgraph includes a corresponding subgraph for each strongly connected subgraph and each node of the directed graph has a corresponding node in one of the acyclic graph and the at least one strongly connected subgraph; assigning to an input data rate and an input data type of each node corresponding to each functional block coupled via a net to an output of the at least one functional block, the output data rate and output data type of the at least one functional block, respectively; and for each functional block, determining an output data rate and output data type from the input data rate and the input data type of the functional block; wherein determining the output data rate and the output data type of data output from the functional block includes: determining a data rate and a data type for each node in the acyclic subgraph using a search of the acyclic subgraph, and for each strongly connected subgraph, determining an output data rate and an output data type for each node in the strongly connected subgraph using at least one search of the strongly connected subgraph; and assigning, by the computing system, the output data rates and output data types to the plurality of functional blocks.