Patent ID: 7375583

Claim:
A differential biquad filter, comprising: first and second power supply terminals; a positive single ended circuit that includes: a first input terminal; a first transistor having a control terminal, and first and second main terminals; a first output terminal corresponding to the control terminal of said first transistor; first and second conductances connected between said single input terminal and the control terminal of said first transistor and connected to each other at a first node; a first current source connected between said first power supply terminal and the first main terminal of said first transistor; a second current source connected between the second main terminal of said first transistor and said second power supply terminal; a first capacitance connected; and a second capacitance connected between the first node and said second main terminal of said first transistor; a negative single ended circuit that includes: a second input terminal; a second transistor having a control terminal, and first and second main terminals; a second output terminal corresponding to the control terminal of said second transistor; third and fourth conductances connected between said single input terminal and the control terminal of said second transistor and connected to each other at a second node; a third current source connected between said first power supply terminal and the first main terminal of said second transistor; a fourth current source connected between the second main terminal of said second transistor and said second power supply terminal; a third capacitance connected between the control terminal of said second transistor and the second main terminal of the first transistor; and a fourth capacitance connected between the second node and said second main terminal of said second transistor; said first main terminal of the second transistor being further connected to the first node, wherein the first capacitance is connected between the control terminal of said first transistor and the second main terminal of the second transistor, the second capacitance is connected between the first node and said second main terminal of said first transistor, and said first main terminal of the first transistor being coupled to the second node; and a third capacitance connected between the second main terminal of the first transistor and the second main terminal of the second transistor.