Patent ID: 8266620

Claim:
A multiprocessing system, comprising: a multithreading microprocessor, comprising: a plurality of thread contexts (TCs); and a virtual processing element (VPE), configured to receive a plurality of interrupt requests, wherein said interrupt requests are non-specific to said plurality of TCs, wherein said VPE is configured to select one of said plurality of TCs to execute a thread to service an active one of said interrupt requests and to set a control bit to disable said VPE from servicing any of said interrupt requests, said VPE comprising a first register for globally masking individual ones of said interrupt requests and their sources that are active from being serviced by any of said plurality of TCs of said VPE and wherein each of said plurality of TCs comprise a second register; and a multiprocessor operating system (OS), comprising said interrupt service thread, for execution on said selected TC, configured to save information indicating which ones of said plurality of interrupt requests is active in said second register of said TC selected by said VPE to execute said interrupt service thread and to write to said first register to globally mask said active one of said interrupt requests, prior to clearing said control bit, in order to prevent said VPE from selecting a different one of said plurality of TCs to redundantly service said active interrupt request between clearing said control bit and clearing the sources of said active interrupt requests.