Patent ID: 8213240

Claim:
A method for performing a page erase operation in a nonvolatile memory array having plural strings of memory cells on a substrate, and plural wordlines across the strings to pages of memory cells; and associated with plural pass transistors, each of which is configured to apply a voltage to a respective one of the wordlines, the memory array being divided into plural blocks, the method comprising: selecting at least one of the blocks; selecting any one or ones of the wordlines of the selected block; enabling each of the pass transistors associated with the selected block; applying a select voltage to the selected one or ones of the wordlines of the selected block; applying an unselect voltage to unselected one or ones of the wordlines that are other than the selected one or ones of the wordlines of the selected block; and applying a substrate voltage to the substrate of the selected block, the voltage difference between the substrate voltage and the select voltage causing the page or pages of memory cells coupled to the selected one or ones of the wordlines to be erased, and the voltage difference between the substrate voltage and the unselect voltage not causing the page or pages of memory cells coupled to the unselected one or ones of the wordlines of the selected block to be erased.