Patent ID: 8924804

Claim:
An integrated circuit comprising: A. functional logic having stimulus inputs and response outputs; B. a first parallel scan path having a serial data input, a serial data output, parallel stimulus outputs coupled to a first set of stimulus inputs, parallel response inputs coupled to a first set of the response outputs, and a first strobe signal input; C. a second parallel scan path having a serial data input, a serial data output, parallel stimulus outputs coupled to a second set of stimulus inputs, parallel response inputs coupled to a second set of the response outputs, and a second strobe signal input; D. state machine controller circuitry having a protocol input, a clock input, and a shift parallel scan path output; E. synchronizer circuitry having a shift parallel scan path input connected to the shift parallel scan path output, a signal input, and a strobe output coupled to the first strobe signal input; and F. first buffer circuitry having an input coupled to the strobe output and having an output connected to the second strobe signal input.