Patent ID: 8537597

Claim:
A semiconductor memory device, comprising a memory cell, the memory cell comprising: a first driving transistor connected to a first storage node; a first load transistor connected to the first storage node; a first read transfer transistor between the first storage node and a first read node; a first write transfer transistor between the first storage node and a first write node; a second driving transistor connected to a second storage node; a second load transistor connected to the second storage node; a second read transfer transistor between the second storage node and a second read node; a second write transfer transistor between the second storage node and a second write node; and one or more variable resistance elements having a resistance that changes depending on a direction of a bias applied to both terminals, wherein the one or more variable resistance elements are in one of a portion between the first storage node and the first write transfer transistor and a portion between the second storage node and the second write transfer transistor, but not in the other.