Patent ID: 7834866

Claim:
A display panel driver for a display panel on which an image frame is formed of a plurality of scan lines, comprising: a drive timing signal generating circuit for generating a drive timing signal for driving the display panel, said drive timing signal based on a horizontal reference signal which will become a horizontal reference of a display period of every scan line and a vertical reference signal which will become a vertical reference of a vertical period as a display period of the image frame, said vertical reference signal being selected from between an internally generated signal and an external vertical synchronizing signal; a controller which, when a frequency of the vertical reference signal has changed as a result of a selecting of said vertical reference signal, calculates a frequency of the horizontal reference signal that can keep a number of scan lines to be displayed during one vertical period at a predetermined count based on the changed frequency of the vertical reference signal, and which controls the frequency of the horizontal reference signal so as to be equal to the calculated frequency; a clock generator for generating a clock signal; a first frequency divider for dividing a frequency of the clock signal supplied from said clock generator to output a frequency-divided clock signal as the horizontal reference signal; a second frequency divider for dividing a frequency of the frequency-divided clock signal supplied from said first frequency divider and outputting said divided frequency; a switch circuit having one input terminal to which an external vertical synchronizing signal is supplied and having another input terminal to which the divided frequency signal from the second frequency divider is supplied and which selectively outputs one of said input terminals as the vertical reference signal; and a frequency detecting circuit for detecting a frequency of the external vertical synchronizing signal, wherein said controller, when a switching between the input terminals of said switch circuit is performed, alters one of an oscillation frequency of said clock generator and a frequency division ratio at said first frequency divider, and wherein, in a state where the external vertical synchronizing signal has been selected by said switch circuit, when said frequency detecting circuit detects changes in the frequency of the external vertical synchronizing signal, said controller then alters the oscillation frequency of said clock generator or the frequency division ratio at said first frequency divider.