Patent ID: 7930669

Claim:
A computer system for mitigating effects of interconnect variability during a design stage of a chip and prior to manufacturing of the chip, comprising: a routing system for performing global and detailed routing of interconnects of the chip; a dummy fill estimation system for performing dummy fill estimation that estimates the maximum amount of locations available for metal dummy fills based on the global and detailed routing of the interconnects; a density estimation system for performing grid based metal density estimation by estimating density of metal in each grid cell; a variable mapping system for obtaining a variable map of metal thicknesses; a net identification system for identifying wiring nets of the chip that are sensitive to metal variability based on the variable map of metal thicknesses and the dummy fill estimation; and an optimization system for re-routing the wiring nets during the design stage and prior to the manufacturing of the chip for metal density based optimization of the chip, the re-routing being performed to substantially maintain a length of the sensitive nets.