Patent ID: 8537586

Claim:
A memory arrangement having a semiconductor body, comprising: a first memory transistor for non-volatile storage of a first bit in such a manner that the first memory transistor is arranged in a first well which the semiconductor body comprises, wherein the first well is configured to be supplied with a well voltage by a first well terminal; a second memory transistor for non-volatile storage of the first bit in inverted form in such a manner that the second memory transistor is arranged in a second well which the semiconductor body comprises, wherein the second well is configured to be supplied with a second well voltage by a second well terminal, wherein the first well comprises the first memory transistor exclusive of the second memory transistor and the second well comprises the second memory transistor exclusive of the first memory transistor; a word line that is connected to a control terminal of the first memory transistor and to a control terminal of the second memory transistor; and a read amplifier including a first input that is coupled to the first memory transistor for supplying a first bit line signal, a second input that is coupled to the second memory transistor for supplying a second bit line signal, and an output for providing an output signal as a function of the first bit line signal and the second bit line signal, wherein: the first well comprises, for storing a second bit, a third memory transistor that is coupled to the first input of the read amplifier, and for storage of the second bit in inverted form, the second well comprises a fourth memory transistor that is coupled to the second input of the read amplifier.