Patent ID: 8878765

Claim:
A gate shift register comprising: a plurality of stages configured to receive a plurality of gate shift clocks and sequentially output a scan pulse, wherein a k-th stage of the plurality of stages includes: a scan direction controller configured to convert a shift direction of the scan pulse in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals; a node controller configured to control charging and discharge operations of each of a Q 1 node, a Q 2 node, a QB 1 node, and a QB 2 node, the node controller including a discharge thin film transistor (TFT) configured to discharge the QB 1 node or the QB 2 node to a low potential voltage in response to a shift direction conversion signal; a floating prevention unit configured to apply the low potential voltage to a gate electrode of the discharge TFT based on a high potential voltage of the QB 1 node or the QB 2 node; a degradation prevention strengthening unit configured to apply the low potential voltage to the gate electrode of the discharge TFT based on a high potential voltage of the first output node or the second output node while the QB 1 node or the QB 2 node maintains the low potential voltage in order to elongate a period of the low potential voltage of the gate electrode of the discharge TFT, wherein a time when a voltage of the first output node or the second output node rises to the high potential voltage is prior to a time when the discharged QB 1 node or the QB 2 node is charged to the high potential voltage; and an output unit configured to output a first scan pulse through a first output node and a second scan pulse through a second output node based on voltages of the Q 1 , Q 2 , QB 1 , and QB 2 nodes, wherein the voltage of the Q 1 node controls a first pull-up transistor for charging the first output node, the voltage of the Q 2 node controls a second pull-up transistor for charging the second output node, and the voltages of the QB 1 and QB 2 nodes control first and second pull-down transistors for discharging the first output node and control third and fourth pull-down transistors for discharging the second output node.