Patent ID: 7650488

Claim:
An apparatus comprising: a first memory address space exclusively and coherently accessible by a first processor core partition in a platform, the first processor core partition including one or more processor cores; a second memory address space exclusively and coherently accessible by a second processor core partition in the platform, the second processor core partition including one or more other processor cores; and a third memory address space in the platform that is accessible, at least in part, by both the first and second processor core partitions and permitting communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet, the at least one descriptor indicating, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet, the third address space including single-reader/single-writer queues, at least one of the queues to store the at least one descriptor, the queues including first and second single-reader/single-writer queues, the first processor core partition being exclusively permitted to read from the first single-reader/single-writer queue, the second processor core partition being exclusively permitted to read from the second single-reader/single-writer queue.