Patent ID: 8472695

Claim:
A method of analyzing a failure of a semiconductor integrated circuit chip, said method comprising: inspecting a physical defect in a semiconductor wafer, by a visual inspection apparatus, at a time of manufacture of a semiconductor integrated circuit chip, acquiring, by the visual inspection apparatus, a chip position with respect to the semiconductor wafer identifying information of said physical defect and in-chip coordinates of the physical defect in an inspection step; subjecting the semiconductor integrated circuit to a logic test by a chip selecting unit, wherein the logic test comprises test data input into a chip under test; extracting, by the chip selecting unit, a malfunctioning chip and a position of said malfunctioning chip on the semiconductor wafer based on the logic test; analyzing, by a signal detecting unit, a detected signal observed from the malfunctioning chip based on the test data input into the malfunctioning chip; acquiring, by the signal detecting unit, circuit coordinates and a layer of the detected signal; extracting, by a circuit extracting unit, a layer and circuit coordinates in a design layout, with regard to a cell in which the detected signal was detected and a net connected to said cell, or a net in which the detected signal was detected and a cell connected to said net, using design data and the circuit coordinates and layer of the detected signal; collating, by a collating unit, the chip position with respect to the semiconductor wafer, the layer of the circuit in the design layout, the in-chip coordinates of the physical defect from the inspection step and the circuit coordinates in the design layout from the extracting unit; and identifying, by the collating unit, the physical defect associated with the malfunctioning chip from the collating.