Patent ID: 7163855

Claim:
A method for manufacturing a semiconductor device, comprising: a step of forming a first impurity layer that becomes a first well in a high breakdown voltage transistor forming region in a semiconductor layer; a step of forming a second impurity layer that becomes an offset region in the high breakdown voltage transistor forming region; a step of forming the first well and the offset region by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; a step of forming an element isolation region by a trench element isolation method in the semiconductor layer, after the step of forming the first well and the offset region; a step of forming a first gate dielectric layer in the high breakdown voltage transistor forming region; a step of forming a second well in a low voltage driving transistor forming region in the semiconductor layer; a step of forming a second gate dielectric layer in the low voltage driving transistor forming region; and a step of forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving transistor forming region.