Patent ID: 7035340

Claim:
A modulation device for modulating an input data string to output a communication signal, comprising: a data string number converting circuit for converting the input data string into an input data signal of a binary signal of 4p+1 bits (p is an integer equal to or more than 3); a first data converting circuit for inputting and converting the input data signal; a second data converting circuit for inputting the input data signal and an output signal from the first data converting circuit to convert into four signals each having p+1 bits; a parallel/serial converting circuit for time-division multiplexing the four signals of p+1 bits outputted from the second data converting circuit; and a modulator for modulating an output signal from the parallel/serial converting circuit to output a communication signal, wherein: the first data converting circuit outputs an output signal standing at one of values from 1 to (5/4)×2 p according to a value of the input data signal; and in response to the output signal from the first data converting circuit and based on the input data signal, when the output signal from the first data converting circuit stands at one of values from 1 to 4×2 (p−3) , the second data converting circuit outputs the output signal from the first data converting circuit as a first output signal, and outputs second, third and fourth output signals that stand at predetermined one of (5/4)×2 p different values, respectively; when the output signal from the first data converting circuit stands at one of values from 1+4×2 (p−3) to 4×2 (p−3) +3×2 (p−3) , the second data converting circuit outputs the output signal from the first data converting circuit as a first output signal, and outputs second, third and fourth output signals that stand at predetermined one of (5/4)× 2 p different values, one of (5/4)×2 p different values, and one of 2 p different values, respectively; when the output signal from the first data converting circuit stands at one of values from 1+4×2 (p−3) +3×2 (p−3) to 4×2 (p−3) +3×2 (p−3) +2×2 (p−3) , the second data converting circuit outputs the output signal from the first data converting circuit as a first output signal, and outputs second, third and fourth output signals that stand at predetermined one of (5/4)×2 p different values, one of 2 p different values, and one of 2 p different values, respectively; or when the output signal from the first data converting circuit stands at one of values from 1+4×2 (p−3) +3×2 (p−3) +2×2 (p−3) to 4×2 (p−3) +3×2 (p−3) +2×2 (p−3) +2 (p−3) , the second data converting circuit outputs the output signal from the first data converting circuit as a first output signal, and outputs second, third and fourth output signals that stand at predetermined one of 2 p different values, respectively.