Patent ID: 8510612

Claim:
An integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a point-to-point channel, the integrated circuit comprising: an inbound redrive circuit to receive and redrive signals on an inbound path of the point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the point-to-point channel; an outbound redrive circuit to receive and redrive signals on an outband path of the point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the point-to-point channel; a pattern generator coupled with the inbound redrive circuit, the pattern generator to provide a permuting alert pattern, wherein the permuting alert pattern is generated by a 12-bit linear-feedback shift register (LFSR) with a polynomial of x 12 +x 7 +x 4 +x 3 +1; and a double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit.