Patent ID: 7772700

Claim:
A semiconductor device comprising: a semiconductor substrate; MOS transistors formed on said semiconductor substrate; a plurality layers of wiring structure positioned over said MOS transistors and each wiring structure comprising a first insulating film, a second insulating film formed over said first insulating film, a first wiring layer formed in said first insulating film, and a second wiring layer comprising copper material, formed in said second insulating film; and a rewiring interconnection positioned over said plurality layers of wiring structure, having an outer lead connection in a part thereof; wherein an uppermost wiring structure among said plurality layers of said wiring structure has a third insulating film formed between said first insulating film and said second insulating film of said uppermost wiring structure, having a dielectric constant higher than a dielectric constant of said second insulating film of said uppermost wiring structure, said outer lead connection is positioned over said second insulating film of said uppermost wiring structure in cross-sectional view, and said second insulating film of a lowermost wiring structure has lower dielectric constant than that of said second insulating film of said uppermost wiring structure.