Patent ID: 7773447

Claim:
A memory circuit comprising: N (N is an integer equal to or larger than two) look-up tables for implementing a desired logic function of L (L is an integer equal to or larger than one) inputs/M (M is an integer equal to or larger than one) outputs by partitioning a memory cell array including a plurality of memory cells into portions each corresponding to at least a predetermined number of input/output paths; a decode circuit for selecting one of said N look-up tables by decoding a look-up table select signal and for selecting M memory cells to be accessed included in the selected look-up table by decoding an L-bit logic input signal of the logic function; and a select connect circuit for selectively connecting the input/output paths of the M memory cells to be accessed with an input/output bus for transmitting an M-bit logic output signal of the logic function in response to a decoded result of said decode circuit.