Patent ID: 7103622

Claim:
A method for reducing unwanted harmonics in direct digital synthesizer (DDS) output, the method comprising the acts of: (a) providing a set of phase-shifted clock signals; (b) examining, in succession, each DDS accumulator state; (c) determining whether the DDS accumulator state has a defined transition-state; (d) for each DDS accumulator state having a defined transition-state, performing an interpolation based upon the value of the preceding DDS accumulator state; (e) selecting an element of the set of phase-shifted clock signals based upon the interpolation; (f) repositioning the DDS accumulator most significant bit (MSB) using the selected element of the phase-shifted clock signals and; (g) wherein the act of determining whether the DDS accumulator state has a defined transition-state further comprises the acts of: (c1) selecting a reference level LMT; (c2) determining whether the value of the current DDS accumulator state is grater than or equal to LMT and, if so, assigning a positive transition-state to the current DDS accumulator state if the value of the preceding DDS accumulator state is less than LMT; or (c3) determining whether the value of the current DDS accumulator state is less than LMT and, if so, assigning a negative transition-state to the current DDS accumulator state if the value of the preceding DDS accumulator state is greater than or equal to LMT.