Patent ID: 8856718

Claim:
A computer readable storage medium storing computer readable instructions that when executed perform a method of estimating signal congestion in routing resources of a programmable logic device (PLD), wherein the routing resources comprise common interface blocks (CIBs) and wires of different types supported by the CIBs, the method comprising: identifying, from a representation of a PLD stored within a computer system, components of the PLD to be connected in a configuration of the PLD; selecting, within the computer system, a CIB associated with an identified PLD component; selecting, within the computer system, a wire type supported by the selected CIB; determining, within the computer system, a number of wires of the selected wire type needed at the selected CIB to implement the PLD configuration, a number of wires of the selected wire type already allocated at the CIB, and a provided number of wires of the selected wire type provided by the CIB; and determining, within the computer system, a congestion index at the selected CIB for the selected wire type from at least the needed number of wires, the number of wires already allocated, and the provided number of wires.