Patent ID: 8312340

Claim:
An information processing apparatus comprising: a data transmitting device that transmits data with N-bit width (N: positive integer); a data receiving device that receives the data with N-bit width; and a system monitoring device connected to the data transmitting device and the data receiving device, wherein the data transmitting device includes a first data-with-parity generating circuit that generates first data with parity in which a parity is added to first data with X-bit width (X: positive integer satisfying N>X) of the data with N-bit width; a second data-with-parity generating circuit that generates second data with parity in which a parity is added to second data with (N−X)-bit width of the data with N-bit width; a first ECC generating circuit that generates first ECC data for the first data; a second ECC generating circuit that generates second ECC data for the second data; a selection-signal generating circuit that generates and outputs a first selection signal and a second selection signal based on a first or a second error notification signal for the first or the second data with parity received from the data receiving device; a first selecting circuit that selects and outputs either one of the first data with parity and the second ECC data based on the first selection signal; a second selecting circuit that selects and outputs either one of the first ECC data and the second data with parity based on the second selection signal; and a data processing unit that degenerates the data with N-bit width to either the first data or the data with (N−X)-bit width based on a data-width degeneration notification signal received from the system monitoring device, and outputs degenerated data, and the data receiving device includes a first parity checking circuit that detects a parity error for the first data with parity and outputs the first error notification signal when an error occurs; a second parity checking circuit that detects a parity error for the second data with parity and outputs the second error notification signal when an error occurs; a first ECC correcting circuit that detects and corrects an ECC error for the first ECC data; and a second ECC correcting circuit that detects and corrects an ECC error for the second ECC data.