Patent ID: 7290161

Claim:
An apparatus comprising: a processor including: a processor core to receive a first clock signal having at least a first clock frequency; a bus interface to generate and sample signals on a bus coupled to the bus interface, the bus interface coupled to the processor core to receive at least a second clock signal having at least a second clock frequency, wherein the first clock frequency is constrained to be no less than a multiple of a lowest one of the at least second clock frequency; and at least one clock frequency divider to divide the at least second clock frequency, so as to maintain a substantially fixed ratio between the core and bus clock frequencies regardless of changes in the frequency of the first clock signal or at least the second clock signal; and an interface controller to generate and sample signals on the bus, the interface controller including a second bus interface to receive a plurality of third clock signals having third clock frequencies and a plurality of clock frequency dividers to generate the third clock signals from an intermediate signal generated from a system clock signal.