Patent ID: 6954395

Claim:
A memory device comprising: a plurality of memory cells arranged in rows and columns in NOR configuration, each one of the plurality of memory cells configured to accept a data bit at a programming input in the presence of an enable voltage at a program enable input, and configured to store the bit of data as one of a plurality of logic levels; a string programming selection circuit, configured to receive, in the presence of a read enable signal at a first enable input during one clock cycle, a first bit of data at a data input and hold the first bit of data as one of a plurality of logic levels, to receive, in the presence of a read enable signal at the first enable input during a succeeding clock cycle, a second bit of data at the data input and hold the second bit of data, as one of a plurality of logic levels, and further configured, in the presence of a write enable signal at a second enable input, to present the first and second bits of data at first and second outputs; a connection circuit configured to couple the first and second outputs to the programming inputs of first and second ones of the plurality of memory cells; a data source for supplying a stream of data bits to the input of the string programming selection circuit; and a circuit configured to provide the write enable signal at the second enable input of the string programming selection circuit and simultaneously providing the enable voltage at the program enable input of each of the plurality of memory cells.