Patent ID: 7227870

Claim:
An apparatus comprising: a first receive circuit configured to couple to a first interface to receive a first plurality of packets, wherein the first receive circuit is configured, for each packet of the first plurality of packets, to select a destination from one of a plurality of destinations and wherein the first receive circuit is further configured to select, for each packet, one of the plurality of virtual channels on a destination of that packet; a second receive circuit configured to couple to a second interface to receive a second plurality of packets, wherein the second receive circuit is configured, for each packet of the second plurality of packets, to select a destination from one of the plurality of destinations and wherein the second receive circuit is further configured to select, for each packet, one of a plurality of virtual channels on the destination of that packet; a plurality of transmit circuits configured to transmit packets on respective interfaces, wherein the plurality of destinations comprises the plurality of transmit circuits; a packet direct memory access (DMA) circuit, wherein the packet DMA circuit is configured to communicate packets to and from a memory controller, and wherein the packet DMA circuit is one of the plurality of destinations; and a switch coupled to the first receive circuit, the second receive circuit, and the plurality of destinations, wherein the switch is configured to couple the first receive circuit and the second receive circuit to select ones of the plurality of destinations to convey packets from the first receive circuit and the second receive circuit to the select ones of the plurality of destinations; wherein the first receive circuit, the second receive circuit, the plurality of destinations, and the switch are integrated onto an integrated circuit.