Patent ID: 8583714

Claim:
A direct digital synthesis (DDS) system, comprising: a read only memory (ROM) for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values; a digital-to-analog converter (DAC) for converting the digital amplitude values into corresponding analog amplitude values; delay circuitry responsive to a control signal and operatively coupled to the ROM, the delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system such that timing of data coming out of the ROM is matched to timing of the DAC, the delay circuitry including a plurality of delay elements that can be selected alone or in combination to adjust the timing of the data output by the ROM; and a processor for generating the control signal, wherein the control signal can change automatically during operation of the DDS system in response to a change in a monitored DDS operating parameter set, thereby providing a variable delay, wherein the DDS operating parameter set includes a frequency control word input to the DDS system, a clock signal having a cycle and for clocking one or more pipeline registers of the ROM, and an environmental variable; wherein the DAC and ROM operate in conjunction with the clock signal, and propagation delay through the ROM is larger than one clock cycle.