Patent ID: 6890808

Claim:
A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type transistor and a p-type transistor having a polysilicon gate, the method comprising: depositing oxide fill on the n-type transistor and the p-type transistor and chemical/mechanical polishing the deposited oxide fill such that a gate stack of the n-type transistor and a gate stack of the p-type transistor, the n-type transistor and the p-type transistor each having spacers are surrounded with oxide; etching a portion of the polysilicon from the gate of the p-type transistor; depositing a low-resistance material on the p-type transistor and the n-type transistor; and heating the integrated circuit such that the deposited low-resistance material reacts with the polysilicon of the p-type transistor and the polysilicon of the n-type transistor, such that compressive mechanical stresses are formed along a longitudinal direction of a channel of the p-type transistor.