Patent ID: 7372444

Claim:
A semiconductor integrated circuit that outputs a plurality of display signals showing two-dimensional images of different sizes from a plurality of output terminals in accordance with a mode signal, comprising: a select signal shift circuit with a plurality of select signal supply terminals, the select signal shift circuit synchronizing with one of a rise-up or a fall of a clock signal and sequentially supplying a select signal to each of the plurality of select signal supply terminals in a first mode, and synchronizing with the rise-up and the fall of the clock signal and sequentially supplying the select signal to two of the plurality of select signal supply terminals in a second mode; a first group of latch circuits that hold image data sequentially supplied to a data bus in response to the select signal being sequentially supplied to the plurality of select signal supply terminals; a second group of latch circuits that hold image data outputted from the first group of latch circuits in response to a line pulse; a display signal generating circuits that generate a plurality of display signals based on the image data being held by a second group of latch circuits; and a timing control circuit that supplies the line pulse of a first cycle to the second group of latch circuits in the first mode and the line pulse of a second cycle which is double the first cycle to the second group of latch circuits in the second mode, the select signal shift circuit including: a group of flip-flops in which there are alternately connected a plurality of sets of first flip-flops synchronizing with one of the rise-up or the fall of the clock signal and sequentially shifting the select signal and second flip-flops synchronizing with the one of the rise-up or the fall of the clock signal and sequentially shifting the select signal in the first mode and synchronizing with the other of the rise-up or the fall of the clock signal and sequentially shifting the select signal in the second mode, wherein the group of flip-flops including a plurality of two-way flip-flops; and a group of selectors that make a switchover between supplying select signals outputted from respective flip-flops to respective select signal supply terminals and supply select signals outputted from every other flip-flop to two of adjacent select signal supply terminals according to a mode signal.