Patent ID: 7262645

Claim:
A method for adjusting the phase of a frequency locked clock signal, comprising: (a) receiving a target phase offset; (b) setting a remaining phase offset equal to the target phase offset; (c) determining whether providing the sum of the remaining phase offset and a frequency control word to a numerically controlled oscillator would cause the numerically controlled oscillator to overflow, (d) if the numerically controlled oscillator would overflow using the remaining phase offset, computing a phase adjustment factor that is a fraction of the remaining phase offset that will prevent the numerically controlled oscillator from overflowing and computing a new remaining phase offset that equals the present remaining phase offset less the phase adjustment factor, then proceeding to step (f); (e) if the numerically controlled oscillator would not overflow using the remaining phase offset, setting a phase adjustment factor to be equal to the remaining phase offset; (f) adding the phase adjustment factor to a frequency control word to create a modified frequency control word; (g) providing the modified frequency control word to a numerically controlled oscillator; (h) generating an output signal of the numerically controlled oscillator based on the modified frequency control word; and (i) if the phase adjustment factor was set to a value other than the remaining phase offset in step (e), repeating steps (c) through steps (i).