Patent ID: 8416163

Claim:
A liquid crystal panel comprising: a plurality of gate lines; a plurality of data lines defining pixel regions at crossings of the gate lines; and a plurality of pixels at regions defined by crossings of the plurality of gate lines and the plurality of data lines, wherein the plurality of pixels include first pixels defined by crossings of a first gate line of the plurality of gate lines and the plurality of data lines and second pixels defined by crossing of remaining gate lines of the plurality of gate lines and the plurality of data lines, wherein the first pixels include liquid crystal cells with an electrode directly connected to a reference voltage line and a drain electrode of a thin film transistor connected to the first gate line, wherein the second pixels include liquid crystal cells connected between a thin film transistor connected to the remaining gate lines and a drain electrode of the thin film transistor connected to the previous gate lines, wherein the liquid crystal cells of the first pixels arranged along the data lines are serially connected to the reference voltage line, wherein the liquid crystal cells of the second pixels arranged along the data lines are connected to the reference voltage line in cascade, thereby forming a serial circuit, wherein a reference voltage is supplied to the reference voltage line from a reference voltage generator, wherein a level of the reference voltage is varied at each frame, wherein the liquid crystal cells of the first pixels are charged with difference voltages between the reference voltage and a pixel voltage signal of the corresponding data lines.