Patent ID: 8165864

Claim:
In a processor simulator for simulating a processor having an instruction pipeline and an address generation (AGEN) bypass-bus, a verification method, comprising: propagating a first set of general purpose register values from a first instruction to a second instruction, wherein a simulation monitor is coupled to a simulated first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, wherein the AGEN bypass-bus is simulated in the simulation monitor and wherein AGEN results are sent by way of the simulated AGEN bypass bus to the instruction pipeline; in response to a computation of an expected AGEN result in the simulated instruction object, selecting a second set of general purpose register values; updating the first set of general purpose register values with the second set of general purpose register values; and placing the second set of general purpose register values on a simulated bus, wherein at a dispatch time of the second instruction in the pipeline, general purpose register values for the first instruction are known, wherein an AGEN result for the second instruction is determined from the general purpose register values associated with an instruction object associated with the first instruction, the determining independent of whether at least one of address generation interlock (AGI) and AGI bypass occurs.