Patent ID: 8081705

Claim:
A digital visual interface system configured to transmit data, control, and BIT signals, said system comprising: (a) a clock channel ( 150 ) transmitting a clock signal at a predetermined rate; (b) a first data channel ( 151 ) transmitting data as a sequence of blocks of multi-level symbols being sent at a fixed multiple of the clock rate; (c) a second data channel ( 152 ) transmitting data as a sequence of blocks of multi-level symbols being sent at said fixed multiple of the clock rate; (d) a third data channel ( 153 ) transmitting data as a sequence of blocks of multi-level symbols being sent at said fixed multiple of the clock rate; (e) wherein each block of multi-level symbols within said first, second, and third data channels is aligned with reference to the clock channel; (f) wherein each block of multi-level symbols comprises a sequence of at least three multi-level symbols; (g) wherein each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, said predetermined number being an integer greater than two; and (h) wherein said fixed multiple of the clock rate being an integer greater than one.