Patent ID: 8378737

Claim:
A charge pump circuit comprising: an input end; an output end; and at least one stage coupled between the input end and the output end, the at least one stage comprising a first complementary metal-oxide-semiconductor (CMOS) transistor pair configured to electrically connect to a first timing signal, a first capacitor coupled with the first CMOS transistor pair, a second CMOS transistor pair configured to connect to a second timing signal, and a second capacitor coupled with the second CMOS transistor pair, a first transistor having a first gate being coupled with the first CMOS transistor pair and a source coupled with a gate of an n-type metal-oxide-semiconductor (NMOS) transistor of the first CMOS transistor pair during an entire period of operation, and the source of the first transistor is configured to connect to the second CMOS transistor pair, wherein the first transistor is configured to connect to a third timing signal; a second transistor having a second gate being coupled with the second CMOS transistor pair and a source coupled with a gate of an NMOS transistor of the second CMOS transistor pair, wherein the second transistor is configured to connect to a fourth timing signal, and the first timing signal, the second timing signal, the third timing signal and the fourth timing signal have an amplitude substantially equal to an operating voltage.