Patent ID: 7663220

Claim:
A semiconductor device module structure comprising: a high-resistance layer of a first conductive type; a base layer of a second conductive type formed in an upper part of the high-resistance layer of the first conductive type; an emitter region of the first conductive type formed in an upper part of the base layer of the second conductive type; an emitter electrode connected to the emitter region; an insulated gate electrode adjacent to the base layer of the second conductive type; a guard ring part formed around a cell region including the emitter region; a buffer layer of the first conductive type formed on an underside of the high-resistance layer of the first conductive type; a collector layer of the second conductive type formed on an underside of the buffer layer of the first conductive type; a collector electrode connected to the collector layer; and a metal flat plate upper heat-sinking part connected to the emitter electrode, wherein the guard ring part comprises: a semiconductor layer of the second conductive type disposed on the upper part of the high-resistance layer of the first conductive type and located around the emitter region; an insulating layer formed on an upper part of the semiconductor layer of the second conductive type; and a passivation layer covering the insulating layer without covering the cell region, wherein a gap is formed between the passivation layer and the upper heat-sinking part such that the passivation layer does not directly contact the upper heat-sinking part.