Patent ID: 8310298

Claim:
A design structure embodied in a machine readable medium used in a design process, the design structure comprising a non-transitory computer readable storage medium that stores therein a current mirror circuit, that includes: a. a reference current source, having an output, that generates a reference current; b. a reference transistor, having a first node having a first node voltage that is coupled to the output of the reference current source, a gate that is coupled to the first node, a second node coupled to a common voltage, and a body; c. at least one mirror transistor, having a gate coupled to the first node, a source, a drain and a body; and d. a ratioed body bias feedback unit, directly responsive to the first node voltage, that generates a body bias voltage coupled to the body of the reference transistor and the body of the at least one mirror transistor, the ratioed body bias feedback unit configured to adjust the body bias voltage in relationship to the common voltage so that the reference transistor and the at least one mirror transistor each have a threshold voltage within a predefined range.