Patent ID: 8709898

Claim:
A method of fabricating a semiconductor device, comprising: forming a gate insulation film on a silicon substrate defined with a device region by a device isolation trench and a gate electrode on said gate insulation film; forming a source extension region and a drain extension region in said silicon substrate portion respectively at a first side and a second side opposite to said first side of said gate electrode by introducing an impurity element of a first conductivity type; forming sidewall insulation films respectively on a sidewall surface at said first side and on a sidewall surface at said second side of said gate electrode; etching said silicon substrate while using said sidewall insulation films as a mask to form first and second trenches respectively at said first side and said second side of said gate electrode at respective outer sides of said sidewall insulation films as viewed from said gate electrode; forming a first semiconductor layer which has etching selectivity against silicon in said first and second trenches and a silicon layer on said first semiconductor layer in said first and second trenches by consecutively and epitaxially growing; exposing, after forming said first semiconductor layer and said silicon layer, said first semiconductor layer by causing a recession in a device isolation insulation film constituting said device isolation region of STI type; removing said first semiconductor layer selectively to form a void between said silicon substrate and said silicon layer; forming a buried insulation film in at least a part of said void, forming a source region and a drain region by introducing an impurity element of said first conductivity type into said silicon layer respectively at said first side and said second side of said gate electrode.