Patent ID: 7115905

Claim:
A semiconductor device comprising: source and drain regions formed in a first silicon layer, separated from each other, and having a concentration of cobalt atoms less than or equal to 1×10 19 cm −3 , a depth of a pn junction formed by said first silicon layer and either of said source and drain regions being not greater than 100 nm; a gate insulating film formed between said source and drain regions on said first silicon layer; a gate electrode formed on said gate insulating film; and a cobalt silicide layer formed on said source and said drain regions by forming a first cobalt silicide layer having a first compound phase on said source and drain regions and said gate electrode, forming an amorphous second silicon layer on said first cobalt silicide layer, said amorphous second silicon layer being adapted to react with said first cobalt silicide layer, and forming a second cobalt silicide layer having a second compound phase by reacting said amorphous second silicon layer and said first cobalt silicide layer in a range of temperature from a first temperature at which a phase transition reaction between said first cobalt silicide layer and said second amorphous silicon layer starts to occur to a second temperature at which a phase transition reaction between said first cobalt silicide layer and said first silicon layer starts to occur, and not less than 17/35 of the film thickness of said second cobalt silicide layer being located over the surface of said first silicon layer.