Patent ID: 7501297

Claim:
A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line on a substrate; forming a first insulating layer on the gate line; forming a semiconductor layer on the flint insulating layer; forming a conductive layer; forming a data line and a drain electrode from the conductive layer and on the semiconductor Layer; depositing passivation layer on the data line and the drain electrode; forming a photoresist on the passivation layer; etching the passivation layer and the first insulating layer using the photoresist as a mask to expose portions of the conductive layer and at least a part of the substrate; partially removing an exposed portion of the conductive layer; depositing a conductive film on the photoresist, and exposed portions of the conductive layer and the substrate; and removing the photoresist and the conductive film deposited on the photoresist, to form a pixel electrode connected to the exposed portion of the drain electrode.