Patent ID: 7660164

Claim:
A method for estimating a threshold voltage of a semiconductor nonvolatile memory device, the method including: measuring threshold voltages of sample semiconductor nonvolatile memory devices over a range of pulse widths, the sample semiconductor nonvolatile memory device comprising first source/drain regions in a first semiconductor substrate and a first charge storage layer sequentially comprising a first oxide layer, a nitride layer and a second oxide layer on the first semiconductor substrate; computing a threshold voltage of a manufactured semiconductor nonvolatile memory device according to inputted pulse width values through an equation: V th ⁡ ( P w ) = V tho - V d ⁢ ⁢ g 1 + ( P w X o ) P + V d ⁢ ⁢ g ( 1 ) the manufactured semiconductor nonvolatile memory device comprising second source/drain regions in a second semiconductor substrate and a second charge storage layer sequentially comprising a first oxide layer, a nitride layer and a second oxide layer on the second semiconductor substrate; and estimating a state of the nitride layer in the second charge storage layer using the computed threshold voltage; wherein V th0 is an ideal threshold voltage of the manufactured nonvolatile memory device, V dg is an ideal drain-to-gate voltage drop of the manufactured nonvolatile memory device, X 0 is a determined pulse width, p is a determined non-linear fitting or optimizing factor, and P w is the applied pulse width.