Patent ID: 8266471

Claim:
A memory block comprising: a memory circuit including a memory core configured to output read data in response to receiving a read command; wherein the memory circuit is configured to output the read data from the memory core in response to being clocked by a clock signal having a selectable delay; wherein the delay is dependent upon a time taken for the read data to be output by the memory core after the read command is received at the memory block; a clock generation unit configured to capture the read data from the memory circuit and to cause the read data to be provided as an output of the memory block in response to being clocked by a selected version of a data clock signal; wherein the selected version of the data clock signal is selected from one of a plurality of clock edges generated by one of a plurality of clock edges of a system clock such that regardless of an operating frequency of the system clock, the read data is provided as the output of the memory block a predetermined amount of time after the read command is received at the memory block.