Patent ID: 7488630

Claim:
A method for preparing a semiconductor structure comprising: providing a first structure including at least one material stack on a semiconductor substrate, said semiconductor substrate including at least a buried insulating layer; forming a dielectric liner covering said at least one material stack and said semiconductor substrate; forming at least one via opening in said first structure which extends below the surface of said semiconductor substrate using said dielectric liner as an etch mask, and said buried insulating layer as an etch stop layer; providing a planarized dielectric material which fills said at least one via opening and extends above said at least one material stack; bonding a second structure including at least one semiconductor device to a surface of said semiconductor substrate that is opposite a surface of said first structure including said at least one material stack; selectively etching preselected areas of said planarized dielectric material which are located above and within said at least one interlayer via opening to extend said at least one interlayer via opening stopping on an upper surface of said second structure; and filling said extended at least one interlayer via opening with a conductive material.