Patent ID: 8723295

Claim:
A semiconductor device comprising: a semiconductor substrate; an n-type drain layer formed in said semiconductor substrate and located on the bottom face side of said semiconductor substrate; a p-type base layer formed in said semiconductor substrate and located over said n-type drain layer; a recess formed in said p-type base layer so that the bottom end of said recess may be located lower than said p-type base layer; a gate insulation film formed over the inner wall of said recess; a gate electrode embedded into said recess; and an n-type source layer formed in said p-type base layer so as to be shallower than said p-type base layer and located next to said recess in a planar view, wherein said p-type base layer includes, in an impurity profile in the thickness direction, a first peak, a second peak being located closer to the bottom face side of said semiconductor substrate than said first peak and being higher than said first peak, and a third peak located between said first peak and said second peak, and wherein said third peak is higher than said first peak and lower than said second peak.