Patent ID: 7800427

Claim:
A switched capacitor circuit comprising: an amplifier that is a single-ended inverter with a single input and a single output; a charging unit, coupled between an input node and a first node, for accumulating charge corresponding to an input signal during a sampling mode; an offset unit, coupled between the first node and the single input of the inverter, for maintaining the first node to be a virtual ground during an integrating mode; and an integrating unit, coupled between the first node and the single output of the inverter, for receiving charge from the charging unit during the integrating mode; wherein the charging unit includes: a first switch having a first switch node that is said input node with the input signal applied thereon and having a second switch node; and a sampling capacitor having a first sampling capacitor node coupled to the second switch node and having a second sampling capacitor node that is said first node; and wherein the offset unit includes: an offset capacitor having a first offset capacitor node coupled to the second sampling capacitor node and having a second offset capacitor node coupled to the single input of the inverter; and wherein the charging unit further includes: a second switch coupled between the second switch node and a ground node; and a third switch coupled between the second sampling capacitor node and the ground node; and wherein the integrating unit includes: a feedback capacitor having a first feedback capacitor node coupled to the single output of the inverter and having a second feedback capacitor node; and a fourth switch coupled between the second sampling capacitor node and the second feedback capacitor node; and wherein the first and third switches are controlled according to a first signal, and wherein the second and fourth switches are controlled according to a second signal.