Patent ID: 8722475

Claim:
A method for forming a variable capacitor, the method comprising: providing a semiconductor substrate comprising a surface region, the substrate being characterized by a first conductivity type; forming an active region within the substrate, the active region being characterized by a second conductivity type; forming a first dielectric layer overlying the active region; forming a conductive gate layer over the first dielectric layer; forming a plurality of discrete holes in the conductive gate layer, each of the discrete holes having a predetermined perimeter length, and two adjacent discrete holes being separated by a predetermined spacing; implanting impurities of the second conductivity type into the active region through the plurality of discrete holes in the conductive gate layer; after implanting impurities of the second conductivity into the active region, forming a second dielectric layer overlying the conductive gate layer; patterning the second dielectric layer to form a first plurality of contact holes extending through the discrete holes in the conductive gate layer to expose the active region; patterning the second dielectric layer to form a second plurality of contact holes to expose the conductive gate layer; forming a first plurality of conductive contact structures in the first plurality of contact holes, the first plurality of conductive contact structures being in physical contact with the active region; and forming a second plurality of conductive contact structures in the second plurality of contact holes, the second plurality of conductive contact structures being in physical contact with the conductive gate layer, wherein a portion of the conductive layer having the discrete holes formed therein is a single electrode.