Patent ID: 7412591

Claim:
An apparatus for switchable conditional execution (CE) in a very long instruction word (VLIW) processor, said apparatus comprising: one or more instruction decoders being involved in a decode stage for loading and decoding instructions from a fetch unit, said one or more instruction decoders decoding conditional instructions for conditional execution in an energy-saving mode or a high-performance mode; one or more arithmetic logic units (ALU) with control units, for executing the decoded instructions from said one or more instruction decoders; and a register file including a plurality of registers for storing and forwarding the executed results of said ALU with control units to said one or more instruction decoders to support said conditional execution; wherein said apparatus has a special instruction for switching said apparatus between said energy-saving mode and said high-performance mode for scheduling and executing conditional instructions in an in-order-scheduling fashion in said energy-saving mode and in an out-of-order-scheduling fashion in said high-performance mode.