Patent ID: 7800111

Claim:
A trench silicon-on-insulator (SOI) dynamic random access memory (DRAM) cell, comprising: a substrate; an oxide layer, covering the substrate, and having a plurality of trenches those extend approximately towards a first direction; a semiconductor conductive layer, covering the oxide layer and the trenches, having a main body, a source, and a drain, wherein the main body covers the trenches to form a plurality of semiconductor conductive units, the source and the drain are formed on two different sides of the main body, and surfaces of the two sides are approximately parallel to the first direction; a gate group, having a gate dielectric layer and a gate, wherein the gate dielectric layer covers the main body, and the gate covers the gate dielectric layer; a spacer, covering two opposite lateral sides of the gate group those are approximately parallel to the first direction; an oxide protective layer, covering the source, the drain, the spacer, and the gate, and having a first through hole, a second through hole, and a third through hole that are respectively formed at positions above and corresponding to the gate, the source, and the drain, so as to expose a part of the gate, a part of the source, and a part of the drain; and an electrode group, having a first electrode, a second electrode, and a third electrode, respectively disposed in the first through hole, the second through hole, and the third through hole, and respectively electrically connected to the gate, the source, and the drain.