Patent ID: 7420428

Claim:
A phase lock loop (PLL) comprising a voltage controlled oscillator (VCO) for providing a VCO output signal, based on first and second voltage tuning signals inputted to the VCO, a filter network for outputting the first and second voltage tuning signals to the VCO, a first phase/frequency detector (PFD) for inputting a first signal to the filter network for forming the first and second voltage tuning signals, a second phase/frequency detector (PFD) for inputting a second signal to the filter network for forming the first and second voltage tuning signals, wherein the first and second voltage tuning signals provide, respectively, first and second gains of frequency per volt for controlling a frequency of the VCO output signal, and when the first PFD is active, the filter network (a) receives the first signal from the first PFD, and responsively outputs the first voltage tuning signal to the VCO and (b) outputs a DC voltage as the second voltage tuning signal to the VCO, and when the second PFD is active, the filter network (a) receives the second signal from the second PFD, and responsively outputs the second voltage tuning signal to the VCO and (b) outputs another DC voltage as the first voltage tuning signal to the VCO.