Patent ID: 7616063

Claim:
A frequency synthesizer comprising: a phase-locked loop (PLL) with a feedback loop and a frequency output; said PLL having a phase and frequency detector, said phase and frequency detector with a reference divider input path and an integer divider input path; said integer divider input path being in said feedback loop of said PLL; a reference oscillator connected to said reference divider input path; a single side band (SSB) mixer having an intermediate frequency (IF) input and a local oscillator (LO) input and producing a signal frequency (RF) output signal; said RF output signal forming at least a portion of a signal path for said integer divider input path; a reference divider in said reference divider input path, said reference divider connected to said reference oscillator and providing input to said phrase and frequency detector; an intermediate divider connected to said reference divider input path, said intermediate divider providing said IF input to said SSB mixer; said frequency output providing said LO input to said SSB mixer; said RF out signal and said LO input comprising a portion of said integer divider input path; said SSB mixer, in turn, further comprising: a first inverter with an LO input and a first inverter output; a second inverter with an IF input and a second inverter output; a first T-type flip-flop having a first clock (CK) input, and a second T-type flip-flop having a second CK input, said LO input and said first inverter output connected respectively to said first and second CK inputs; a “1” logic signal connected respectively to said first T-type flip-flop T input and to said second T-type flip-flop T input; said first and second T-type flip-flop in combination producing LO quadrature outputs; a third T-type flip-flop having a third CK input, and a fourth T-type flip-flop having a fourth CK input, said IF input and said second inverter output connected respectively to said third and fourth CK inputs; said “1” logic signal connected respectively to said third T-type flip-flop T input and to said fourth T-type flip-flop T input; said third and fourth T-type flip-flop in combination producing IF quadrature outputs; and, a mixer-splitter circuit interconnected to said first, second, third and fourth T-type flip-flops, said mixer-splitter circuit, in turn, comprising: a first mixer circuit connected to said first T-type flip-flop LO quadrature outputs and said third T-type flip-flop IF quadrature outputs, producing a first RF output; a second mixer circuit connected to said second T-type flip-flop LO quadrature outputs and said fourth T-type flip-flop IF quadrature outputs, producing a second RF output; and, a 2-way 0 degree splitter connected to said first RF output and said second RF output and producing a mixer RF output signal proportional to a signal from the group consisting of the sum of the frequencies of said IF input and said LO input, and the difference of the frequencies of said IF input and said LO input.