Patent ID: 7746181

Claim:
A circuit configured for calibrating an oscillator included with a phase locked loop (PLL) device, the circuit comprising: a calibrate enable signal supplied to the PLL device, wherein the calibrate enable signal causes the PLL device to enter a calibration mode without disconnecting the oscillator from a control voltage generated by other PLL device components; an analog comparison block coupled for receiving a reference clock signal and a feedback clock signal from the PLL device when operating in the calibration mode, wherein the analog comparison block is configured for using the reference and feedback clock signals to determine whether an operating frequency of the oscillator should be increased or decreased; a digital control block coupled for supplying a calibration signal to the oscillator based on the determination made by the analog comparison block; and a calibrate enable control block coupled for receiving the calibrate enable signal and a clocking signal having a preset number of cycles, wherein the calibrate enable control block is configured for clocking the digital control block once for every cycle of the clocking signal and for disabling the digital control block after the preset number of cycles is complete.