Patent ID: 6978329

Claim:
A bus arbiter for arbitrating bus access requests from N bus requestor devices, said bus arbiter comprising: N one-hot registers, each of said N one-hot registers associated with a corresponding one of said N bus requestor devices, wherein said each of said N one-hot registers contains N priority bits rank-ordered from a lowest priority bit to a highest priority bit, and wherein only one of said N priority bits is enabled to indicate a priority of said corresponding one of said N bus requestor device; and N AND gate arrays, each of said N AND gate arrays associated with a corresponding one of said N one-hot registers, wherein said each AND gate array comprises N two-input AND gates, each of said N two-input AND gates having 1) a first input coupled to one of N priority bits of said corresponding one of said N one-hot registers and 2) a second input coupled to a request line associated with said corresponding one of said N bus requestor devices, and wherein said each AND gate array produces a request vector comprising N rank-ordered bits such that only one of said N rank-ordered bits in each request vector is enabled when said request line is enabled.