Patent ID: 7112499

Claim:
A method of fabricating a MOSFET device with shallow source/drain extension junctions comprising the steps: forming a pre-amorphized implant layer in between shallow trench isolation regions and adjacent to gate electrode structure on a semiconductor substrate; performing ion implantation of dopants in said pre-amorphized implant layer to form source/drain extension regions; and performing a sequential dual step anneal of said source/drain extension regions comprising: a) a first low energy multiple-pulse laser anneal step in the sub-melt regime to activate the dopants in the source/drain extension regions followed by b) a second rapid thermal anneal step to heal residual damage from the ion implantation and to cause the out-diffusion of the dopants in the source/drain extension regions to yield shallower source/drain extension junctions than the just-implanted source/drain extensions.