Patent ID: 8441112

Claim:
A method of manufacturing a plurality of layered chip packages, each of the layered chip packages comprising: a main body having a top surface, a bottom surface, and four side surfaces; and wiring that includes a plurality of wires disposed on at least one of the side surfaces of the main body, wherein: the main body includes: a main part that includes a first layer portion and a second layer portion stacked, the main part having a top surface and a bottom surface; a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the plurality of wires; and a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the plurality of wires; each of the first and second layer portions includes a semiconductor chip and a plurality of electrodes, the semiconductor chip having a first surface and a second surface opposite to the first surface; the plurality of electrodes are disposed on a side of the semiconductor chip opposite to the second surface; the first layer portion and the second layer portion are bonded to each other such that the respective second surfaces face each other; the plurality of first terminals are formed by using the plurality of electrodes of the first layer portion; and the plurality of second terminals are formed by using the plurality of electrodes of the second layer portion, the method comprising the steps of: fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, each of the preliminary layer portions being configured as one of the first and second layer portions, the substructures being configured for dicing at positions of boundaries between every adjacent ones of the preliminary layer portions; and cutting the layered substructure so that the plurality of layered chip packages are formed, wherein: each of the two substructures has a first surface on which the plurality of electrodes are disposed, and a second surface opposite to the first surface; in the step of fabricating the layered substructure, the two substructures are stacked on each other such that their respective first surfaces face toward opposite directions; the layered substructure includes: an array of a plurality of pre-separation main bodies that are configured for being separated from each other into individual main bodies; and a plurality of preliminary wires disposed between every adjacent two of the pre-separation main bodies; and in the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the plurality of wires are formed by the preliminary wires.