Patent ID: 8436647

Claim:
A method of reducing leakage current comprising: waking a first plurality of gates coupled between first source storage elements and second destination storage elements, to allow current flow in the first plurality of gates, in response to assertion of any of one or more first source clock enable signals associated with the first source storage elements; waking a second plurality of gates coupled between second source storage elements and second destination storage elements plurality, to allow current flow in the second plurality of gates, in response to assertion of any of one or more second source clock enable signals associated with the second source storage elements; and waking a third plurality of gates, in response to assertion of any of the one or more first source clock enable signals and waking the third plurality of gates in response to the assertion of the any of the one or more second source clock enable signals; and sleeping the third plurality of gates to reduce leakage current in the third plurality of gates in response to, at least in part, all of the one or more first and second source clock enable signals being deasserted.