Patent ID: 7759787

Claim:
A packaging substrate for mounting a semiconductor chip, said packaging substrate comprising: a core comprising an organic material, silicon, or a ceramic; a front metal interconnect layer containing patterned pieces of metal and an insulator material and located on and above a top surface of said core; and a back metal interconnect layer containing patterned pieces of said metal and said insulator material and located on and below a bottom surface of said core, wherein a conformal one-to-one mapping exists between said front metal interconnect layer and said back metal interconnect layer, wherein a positive correlation exists between a pattern of said back metal interconnect layer and a pattern of said front metal interconnect layer, wherein at least one of said patterns is modified to provide a matching 3D distribution of coefficient of thermal expansion of the corresponding front and back metal interconnect layers, a probability to detect presence of the metal at a corresponding point location in said front metal interconnect layer, obtained by said conformal one-to-one mapping of a randomly selected point location in said back metal interconnect layer at which the metal is present, is greater than a ratio of a total area of metal within said front metal interconnect layer to a total area of said front metal interconnect layer.