Patent ID: 7126838

Claim:
A readout circuit comprising: a signal readout unit comprising a line memory comprising a plurality of memory units for holding signals, first switches for transferring the signals, a first common signal line for transferring the signals by a predetermined number of said first switches, and a second switch for transferring the signals from said first common signal line to a second common signal line, so as to selectively read out signals to be held in each memory unit of said line memory on said second common signal line via at least one of said first switches, said first common signal line, and said second switch; and a control unit for on/off controlling said first and second switches, wherein said readout circuit comprises a first wiring provided between an electrode of said second switch and said second common signal line, and a second wiring for applying a signal from said control unit to at least one of said first and second switches, said second wiring has a non-inversed signal apply wiring and an inversed signal apply wiring to which non-inversed and inversed signals of which logical levels are reversed with respect to each other are applied, and said non-inversed signal apply wiring and said inversed signal apply wiring are arranged respectively at opposite sides of said first wiring.