Patent ID: 7495418

Claim:
A semiconductor apparatus, comprising: a plurality of parallel monitor circuits each configured to control charge to a capacitor by controlling a transistor that bypasses, if the voltage of the capacitor exceeds a predetermined reference voltage, charge current provided to the capacitor; a plurality of high voltage side IC connection output terminals each connected to an open drain of a corresponding N channel transistor; a plurality of high voltage side IC connection input terminals each connected to a terminal of a corresponding first high resistance component, an opposite terminal of each first high resistance component being connected to a minus power supply of the semiconductor apparatus, and to a corresponding inverter input terminal; a plurality of low voltage side IC connection output terminals each connected to an open drain of a corresponding P channel transistor; and a plurality of low voltage side IC connection input terminals each connected to a terminal of a corresponding second high resistance component, an opposite terminal of each second high resistance component being connected to a plus power supply of the semiconductor apparatus, and to a corresponding inverter input terminal, wherein when the open drain of the N channel transistor of one of the high voltage side IC connection output terminals is turned on, the high voltage side IC connection output terminal becomes the minus power supply voltage of the semiconductor apparatus; when a low signal is input to one of the low voltage side IC connection input terminals, a little current flows to the corresponding second high resistance component connected to the plus power supply of the semiconductor apparatus, and a low signal is input to the corresponding inverter input; and the first and second high resistance components are distinct elements from the N channel and P channel transistors.