Patent ID: 7296141

Claim:
An apparatus comprising: a control unit of a processor to receive fetched instructions and to assign a first tag to identify which of the instructions are in a same basic block of instructions preceding a particular branch instruction within a program, the control unit to change the first tag to a second tag to be used with instructions following the particular branch instruction, including a delay slot instruction immediately following the branch instruction, when the delay slot instruction is a conditional instruction, but the control unit to retain the first tag for the delay slot instruction and change the first tag to the second tag for instructions following the branch delay slot instruction, when the delay slot instruction is an unconditional instruction; and an instruction queue to store the fetched instructions with corresponding assigned tags for issuance to an execution unit of the processor and in which if the particular branch instruction is mispredicted, instructions having the second tag are to be cancelled in the execution unit, including the delay slot instruction when the delay slot instruction is conditional.