Patent ID: 8173493

Claim:
A manufacturing method of a thin film transistor array panel comprising: forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a plurality of conducting films on the ohmic contact, wherein the plurality of conducting films comprises a first conducting film and a second conducting film, the second conducting film is disposed between the first conducting film and the ohmic contact, and the first conducting film has a better contact characteristic with at least one of ITO and IZO than the second conducting film; forming a first photoresist pattern on the plurality of conducting films; etching the plurality of conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the plurality of conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.