Patent ID: 8108622

Claim:
A memory management system, comprising: a plurality of processors; a shared memory that can be accessed from the plurality of processors; and a cache memory that is provided between the shared memory and each processor of the plurality of processors, and wherein invalidation and write back of a specified region in the shared memory can be commanded from programs running on each of the processors based on data stored in the cache memory; wherein at least one of the programs: invalidates, as a first processing batch, an input data region storing input data in the cache memory using an invalidation command of a specified region immediately before execution of the at least one program; and writes back, as a second processing batch, an output data region that stores output data in the cache memory to the shared memory using a write back command for a specified region immediately after execution of operations of the at least one program except for the writing back; wherein the programs operating on each processor of the plurality of processors each individually determines an input data region and an output data region of a third processing batch in the cache memory on the basis of an input/output relationship of a dependency information table that controls an execution sequence of the programs.