Patent ID: 7018886

Claim:
A method for controlling stress in silicon active areas comprising: providing a stop layer on a substrate; etching a plurality of trenches through said stop layer and into said substrate; depositing a first layer over said stop layer and filling said trenches wherein said first layer comprises a dielectric material having a thermal coefficient higher than that of silicon; planarizing said first layer to said stop layer leaving said first layer within said trenches; thereafter removing said first layer from a subset of said trenches wherein said subset of said trenches surround second silicon active areas and wherein remaining said trenches surround first silicon active areas; depositing a second layer over said stop layer and within said subset of trenches wherein said second layer comprises a dielectric material having a thermal coefficient lower than that of silicon; and planarizing said second layer to said stop layer leaving said second layer within said subset of trenches wherein controlled tensile stress is applied to said first silicon active areas and wherein controlled compressive stress is applied to said second silicon active areas.