Patent ID: 6867070

Claim:
A method of forming a bonding pad structure for binding deposition layers in an integrated circuit having a plurality of electrical elements and a plurality of conductive layers, comprising the steps of: A. forming an etch stop pattern in a bonding pad region of the integrated circuit; B. forming a interlayer dielectric above the etch stop pattern; C. forming at least one contact hole in the interlayer dielectric above the etch stop pattern; D. depositing a conductive material to fill the at least one contact hole; E. removing the conductive material above the interlayer dielectric; F. forming a first conductive interconnection layer pattern above the contact hole; G. depositing an intermetallic dielectric layer; H. forming a plurality of via holes in the intermetallic dielectric layer above the first conductive interconnection layer pattern, thereby exposing the first conductive interconnection layer pattern; I. forming a second conductive interconnection layer pattern in and above the plurality of via holes exposing the first conductive interconnection layer pattern to form the bonding pad contacting the first conductive interconnection layer pattern; J. depositing a passivation layer above the second interconnection layer pattern; and K. exposing the bonding pad by removing a portion of the passivation layer above the bond pad region.