Patent ID: 7160777

Claim:
A method of manufacturing a split-gate nonvolatile semiconductor memory device, the method comprising: forming insulating patterns on a semiconductor substrate, the insulating patterns separated by an opening; forming undercuts in lower portions of the insulating patterns, each undercut positioned on a side of the insulating pattern opposite to the opening; forming a gate insulating layer on a surface of the semiconductor substrate between the semiconductor substrate and the insulating patterns; forming a spacer-type floating gate and a spacer-type dummy pattern on sidewalls of the insulating patterns; removing the insulating patterns; forming a lightly doped region by implanting impurities into the semiconductor substrate via the opening; forming a pair of insulating spacers on a sidewall of the floating gate and a sidewall of the dummy pattern which face each other; forming a tunnel insulating layer on the pair of insulating spacers; forming a control gate in a self-aligned manner between the pair of insulating spacers; forming a source and drain region by implanting impurities into the semiconductor substrate outside the floating gate; and forming a lightly-doped-drain-type source and drain region by forming a heavily doped region that overlaps the lightly doped region.