Patent ID: 8164130

Claim:
A nonvolatile memory device comprising: a substrate; a transistor formed on the substrate; and a data storage unit connected to a drain of the transistor, wherein the data storage unit includes a nonvolatile, unipolar data storage material layer having different and reversible resistance characteristics in different voltage ranges, wherein the nonvolatile, unipolar data storage material layer has a first resistance when a write voltage V 3 (V 3 >V 2 ) is applied to the nonvolatile, unipolar data storage material layer, the first resistance representing a first data state, wherein the nonvolatile, unipolar data storage material layer has a second resistance different from the first resistance when a write voltage V w1 (0<V 1 <V w1 <V 2 ) is applied to the nonvolatile, unipolar data storage material layer, the second resistance representing a second data state, wherein the first and second data states are readable from the nonvolatile, unipolar data storage material layer upon application of a read voltage V R (V R <|V 1 |) to the nonvolatile, unipolar data storage material layer without altering the data state of the nonvolatile, unipolar data storage material layer, wherein V 1 is a first voltage, and wherein V 2 is a second voltage.