Patent ID: 7032061

Claim:
A multimaster bus system for devices, a plurality of which are bus master devices, comprising: a bus having connection points at which the devices are connected to said bus and having bus segments selectively connectable to one another, said bus adapted to connect at least one of the devices to at least another of the devices, said bus having at least one of data and signal paths, each of said paths having a respective configurable course; nodes disposed at said connection points and between said bus segments; and a central multimaster bus controller connected to said bus, to each bus master device and to each of said nodes, said multimaster bus controller adapted to control at least one of said bus and allocation of said bus and, pursuant to a request from a bus master device, to configure said courses of said paths by selecting the path through said nodes, and by setting each of said nodes of said path in order to connect said bus segments and create the selected path through said nodes.