Patent ID: 7901956

Claim:
A method of manufacturing a semiconductor device, comprising: providing a substrate having a bond pad disposed on a top surface of the substrate; forming a first passivation layer over the substrate and bond pad, the first passivation layer having an opening to expose the bond pad; forming an under bump metallurgy over the first passivation layer, wherein a first portion of the under bump metallurgy is disposed over the bond pad and a second portion of the under bump metallurgy extends beyond an end of the bond pad, the first passivation layer having a first thickness over a portion of the substrate below the second portion of the under bump metallurgy and second thickness over the bond pad which is less than the first thickness; forming a second passivation layer over the under bump metallurgy, the second passivation layer having a first opening to expose the first portion of the under bump metallization; etching a second opening in the second passivation layer away from the first opening to expose the second portion of the under bump metallurgy while maintaining the second passivation layer around the first opening; and connecting a test probe to the second portion of the under bump metallurgy to perform an electrical test.