Patent ID: 8643802

Claim:
A pixel array, comprising: a plurality of scan lines; a plurality of data lines, intersected with the scan lines to define a plurality of sub-pixel regions; a plurality of sub-pixels, disposed in the sub-pixel regions, each of the sub-pixels electrically connected to two adjacent scan lines and one of the data lines, wherein each of the sub-pixels arranged in an n th row comprises: a first switch; a first pixel electrode, electrically connected to the first switch; a second switch, wherein the first switch and the second switch are electrically connected to an n th scan line and an m th data line, and the second switch has a first signal output terminal; a third switch, electrically connected to an (n+i) th scan line, wherein the third switch has a signal input terminal electrically connected to the first signal output terminal and a second signal output terminal, and i is a positive integer; a second pixel electrode, electrically connected to the second signal output terminal, wherein the first signal output terminal is electrically insulated from the first pixel electrode and the second pixel electrode, and the first signal output terminal extends to an underneath of the second pixel electrode such that a coupling capacitance is generated between the first signal output terminal and the second pixel electrode, wherein the first signal output terminal extends to an underneath of the first pixel electrode such that a first parasitic capacitance is generated between the first signal output terminal and the first pixel electrode; and at least one coupling conductor electrically connected to the first pixel electrode, wherein the coupling conductor extends to the underneath of the second pixel electrode such that a second parasitic capacitance is generated between the coupling conductor and the second pixel electrode.