Patent ID: 8124482

Claim:
A process of forming an integrated circuit containing an MOS transistor, comprising the steps: providing a semiconductor substrate; forming a drift region in said substrate, such that said drift region has a first conductivity type and so that said drift region extends to a top surface of said substrate; forming an isolation dielectric layer at said top surface of said substrate over said drift region, such that said isolation dielectric layer does not overlap a gate region of said transistor; forming a gate trench in said substrate so that said gate trench abuts said isolation dielectric layer; forming a body well in said substrate adjacent to said drift region, such that said body well overlaps a first portion of the bottom surface of said gate trench, and such that said body well has an opposite conductivity type from said drift region; forming a gate dielectric layer on exposed surfaces of said substrate in said gate trench; forming a gate on said gate dielectric layer in said gate trench; and forming a source diffused region in said body well, such that said source diffused region abuts said gate dielectric layer in said gate trench and overlaps a second portion of said bottom surface of said gate trench, said second portion of said bottom surface of said gate trench being within said first portion of said bottom surface of said gate trench, and such that said source diffused region has a same conductivity type as said drift region.