Patent ID: 7630431

Claim:
A data message decoder for high-speed serial bus applications, comprising: a sync pattern decoder adapted to find a first valid sync pattern in a first data message; and a message bit decoder adapted to decode a first bit message following said first valid sync pattern in said first data message upon said sync pattern decoder finding said first valid sync pattern in said first data message, wherein said message bit decoder is operated in parallel with said sync pattern decoder, said sync pattern decoder looking for a second valid sync pattern in a second data message while said message bit decoder decodes said first bit message in said first data message; wherein said sync pattern decoder detects said second valid sync pattern in said first data message, said message bit decoder aborts decoding said first bit message, and upon said message bit decoder aborting decoding said first bit message, said message bit decoder starts decoding a second bit message in said second data message following said detected second sync pattern.