Patent ID: 7532722

Claim:
An apparatus for performing cryptographic operations, comprising: a cryptographic instruction, received by a microprocessor device as part of an instruction flow executing on said microprocessor device, wherein said cryptographic instruction also prescribes an encryption operation to be executed on a plurality of input text blocks that are in memory to generate a corresponding plurality of ciphertext blocks, and to store said corresponding plurality of ciphertext blocks in said memory, and wherein said cryptographic instruction also prescribes one of a plurality of block cipher modes to be employed in accomplishing said one of the cryptographic operations, wherein said microprocessor device comprises; and execution logic, operatively coupled to said cryptographic instruction, configured to execute said one of the cryptographic operation, wherein said execution logic comprises: a cryptography unit, configured execute a plurality of cryptographic rounds on each of said plurality of input text blocks to generate a corresponding one of said plurality of cryptographic rounds are prescribed by a control word that is provided to said cryptography unit, and wherein said plurality of input text blocks are retrieved from said memory, and wherein said corresponding plurality of ciphertext blocks are stored to said memory; wherein said encryption operation comprises: indicating whether said encryption operation has been interrupted by an interrupting event.