Patent ID: 7649381

Claim:
A level conversion circuit comprising: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit generating the control voltage to be inputted to the second transistor, wherein the control-voltage generating circuit comprises: a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparison circuit controlling the control voltage so as to equalize an output voltage of the replica of the source follower circuit and a threshold voltage of a next-stage CMOS circuit; and wherein the threshold voltage of a next-stage CMOS circuit is VDD/2+(Vthn−Vthp)/2 when assuming that a source voltage to be applied to the source follower circuit is VDD, a threshold voltage of the first transistor is Vthp, and a threshold voltage of the second transistor is Vthn.