Patent ID: 7341906

Claim:
A method of forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit, comprising: forming a first sidewall spacer adjacent a word line structure in said memory array, said first sidewall spacer having a first thickness; and forming a second sidewall spacer adjacent a transistor structure in said at least one peripheral circuit, said second sidewall spacer having a second thickness that is greater than said first thickness, wherein said first and second sidewall spacers are formed from a single layer of spacer material, wherein forming said first and second sidewall spacers comprises: forming said layer of spacer material above said word line structure in said memory array and above said transistor structure in said at least one peripheral circuit; forming a masking layer above said layer of spacer material in said at least one peripheral circuit; performing an anisotropic etching process on said layer of spacer material formed above said word line structure to thereby define said first sidewall spacer having said first thickness; removing said masking layer; forming a layer of material above said layer of spacer material adjacent said transistor structure and above said word line structure in said memory array, said layer of material being selectively etchable with respect to said layer of spacer material; and performing an anisotropic etching process on said layer of material to define a masking spacer comprised of said layer of material adjacent said layer of spacer material that is adjacent said transistor structure in said peripheral circuit.