Patent ID: 7379283

Claim:
An electrostatic discharge (ESD) protection circuit comprising: a snapback device connected to a control node, the snapback device having a snapback voltage; a first transistor connected to the control node, the first transistor having a gate, the first transistor to source a pull-up current to the control node when the first transistor turns on, a net inflow of current into the control node to raise a voltage on the control node to lower the snapback voltage; a second transistor having a gate connected to the gate of the first transistor, the second transistor to source a time-out current when the second transistor turns on; a timing control circuit connected to the second transistor, the timing control circuit to sink the time-out current, and generate a timing voltage in response to the time-out current; and a third transistor connected to the timing control circuit and the control node, the third transistor to receive the timing voltage, and sink a pull-down current from the control node when the third transistor turns on, a net outflow of current from the control node to lower a voltage on the control node to raise the snapback voltage.