Patent ID: 8174073

Claim:
A device comprising: a semiconductor substrate; Shallow Trench Isolation (STI) regions at a surface of the semiconductor substrate, wherein the STI regions comprise a flat top surface; a semiconductor strip between opposite sidewalls of the STI regions, wherein a portion of the semiconductor strip over the flat top surface of the STI regions forms a semiconductor fin, wherein the semiconductor fin forms a channel region of a Fin field-effect transistor (FinFET), and wherein the semiconductor strip is connected to the semiconductor substrate to form a continuous semiconductor region; a gate dielectric on sidewalls and a top surface of the semiconductor fin; a gate electrode on the gate dielectric; a source/drain region of the FinFET connected to an end of the semiconductor fin, wherein the source/drain region has a source/drain junction; and a source/drain silicide region on sidewalls and a top surface of the source/drain region, wherein the source/drain junction is higher than the flat top surface of the STI regions a spacer vertically between the source/drain silicide region and the flat top surface of the STI region, wherein the spacer comprises an inner edge adjoining the semiconductor fin, and a curved outer edge opposite the inner edge.