Patent ID: 8359419

Claim:
A system LSI comprising: first and second memories; first and second buses; a bus bridge that performs signal transfer between the first and second buses; a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses, first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories, a first access path that connects the first bus-side input/output terminal and the first memory-side input/output terminal, a second access path that connects the second bus-side input/output terminal and the second memory-side input/output terminal, a third access path that connects the first bus-side input/output terminal and the second memory-side input/output terminal, a fourth access path that connects the second bus-side input/output terminal and the first memory-side input/output terminal, an address region managing portion that receives an access destination address in the first or second memory, which is output by the first or second bus; and outputs a signal that designates the first or second memory address in accordance with a path-selection-mode setting signal to the first or second memory-side input/output terminal, wherein the memory access circuit performs signal transfer through the first to fourth access paths; and for memory access by the first or second bus, selects at least one of the first to fourth access paths in accordance with a path-selection-mode setting signal from the first or second bus, wherein the first or second bus has an access destination address space including a first address space in the first memory and a second address space, which is continuous to the first address space, in the second memory; and if the path-selection-mode setting signal indicates a one-all mode, the address region managing portion identifies either first or second memory to access on the basis of the access destination address space, converts the access destination address to an address in the first or second address space and outputs the result, and the memory access circuit selects one of the first to fourth access paths in accordance with the identification result by the address region managing portion.