Patent ID: 7698533

Claim:
A system comprising: a central processing unit (CPU); a coprocessor; and a coprocessor interface, comprising: a first instruction path for transferring a first group of instructions from the CPU to the coprocessor; a second instruction path for transferring a second group of instructions from the CPU to the coprocessor, wherein one or both of the first and second group of instructions includes one or more CPU conditional instructions; a first condition code path to transfer condition codes from the coprocessor to the CPU upon evaluation of one or more CPU conditional instructions in the first instruction group by the coprocessor; a second condition code path to transfer condition codes from the coprocessor to the CPU upon evaluation of one or more CPU conditional instructions in the second instruction group by the coprocessor; and an order path for transferring an order signal from the CPU to the coprocessor, wherein the order signal indicates an order of execution, wherein the order of execution is independent of a type of the instruction transferred.