Patent ID: 7542479

Claim:
A device for implementing convergence of multi-port services with arbitrary speeds, comprising an uplink transmitting unit and a downlink transmitting unit, wherein the uplink transmitting unit comprises at least a clock & data recovery module for extracting clock frequency information from service data of each of branches, an encapsulation module for encapsulating the service data into data packets without discarding any bit of the original service data and without discarding any bit of the overhead or filling characters associated with the original service data including bits for the idle signal and clock frequency information, and a mapping module for mapping the data packets to a container of high-speed channel which are connected sequentially in series, the downlink transmitting unit comprises a de-mapping module for restoring data packets mapped from the container of high-speed channel and a decapsulating module for decapsulating data packets de-mapped and restoring branch data, and the downlink transmitting unit further comprises: a branch clock generating and adjusting part, for determining a transmitting clock frequency of the service data decapsulated, and adjusting a local branch clock frequency based on the transmitting clock frequency so as to make the local branch clock frequency be consistent with the transmitting clock frequency; the de-mapping module, the decapsulating module and the branch clock generating and adjusting part in the downlink transmitting unit being connected sequentially in series, said clock & data recovery module in the uplink transmitting unit supporting services with arbitrary speeds; wherein the branch clock generating and adjusting part adjusting the local branch clock frequency based on the transmitting clock frequency so as to make the local branch clock frequency be consistent with the transmitting clock frequency comprises: writing the service data decapsulated into a buffer according to the transmitting clock frequency, reading the service data decapsulated from the buffer according to the local branch clock frequency, obtaining waterline value of the buffer indicating the difference between writing speed and reading speed, and adjusting the local branch clock frequency according to the waterline value.