Patent ID: 8595439

Claim:
A device comprising: a multi-core processor communicatively coupled to one or more caches, each core, of the multi-core processor, to: execute application code in a first cache environment to obtain a first result, the first cache environment being based on a first cache configuration that is associated with the application code, the first result including a first execution time associated with executing the application code in the first cache environment, determine a second cache configuration based on the first result, execute the application code in a second cache environment to obtain a second result, the second cache environment being based on the second cache configuration, the second result including a second execution time associated with executing the application code in the second cache environment, compare the first result, including the first execution time, with the second result including the second execution time, select one of the first cache configuration or the second cache configuration as a selected cache configuration for the application code based on comparing the first result with the second result, the first cache configuration being selected as the selected cache configuration for the application code when the first execution time is less than the second execution time, and the second cache configuration being selected as the selected cache configuration for the application code when the second execution time is less than the first execution time, and configure the one or more caches based on the selected one of the first cache configuration or the second cache configuration.