Patent ID: 8530144

Claim:
A method for fabricating source/drain electrodes of a thin film transistor, comprising: providing a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected thereto, wherein the first and second gate electrodes are successively covered by a gate dielectric layer, a semiconductor layer, and a metal layer; coating a photoresist layer on the metal layer; performing an exposure process on the photoresist layer by a photomask comprising: a transparent substrate having a U-shaped channel-forming region and a rectangular channel-forming region corresponding to the first and second gate electrodes, respectively; a translucent layer disposed on the transparent substrate and covering the U-shaped and rectangular channel-forming regions; a first light-shielding layer and a second light-shielding layer disposed on the translucent layer and located at the outer and inner sides of the U-shaped channel-forming region, respectively, to serve as a pair of first source/drain-forming regions; a third light-shielding layer and a fourth light-shielding layer disposed on the translucent layer and located at opposite sides of the rectangular channel-forming region, respectively, to serve as a pair of second source/drain-forming regions, wherein an end of the third light-shielding layer extends to the first light-shielding layer; and a plurality of first light-shielding islands disposed on the translucent layer and located within the rectangular channel-forming region; performing a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, wherein the photoresist pattern layer corresponding to the U-shaped and rectangular channel-forming regions has a thickness less than that of the photoresist pattern layer corresponding to the pairs of first and second source/drain-forming regions; and etching the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode.