Patent ID: 7219193

Claim:
A FIFO control circuit for passing receive data and transmit data in a first-in first-out system, respectively, the FIFO control circuit comprising: a receiving circuit; a transmitting circuit; a FIFO buffer for temporarily storing receive data received by the receiving circuit and transmit data to be transmitted by the transmitting circuit; a free space management circuit for managing free space of the FIFO buffer; a first address storage unit for storing an address range in which the receive data is stored in the FIFO buffer; a second address storage unit for storing an address range in which the transmit data is stored in the FIFO buffer; a write pointer control circuit, in the case where receive data is received by the receiving circuit, for querying the free space management circuit about free space in the FIFO buffer, writing the receive data in free space designated by the free space management circuit, and storing an address range in which the receive data has been written in the first address storage unit, and, in the case where the transmit data is received from a transmission source, for querying the free space management circuit about free space in the FIFO buffer, writing the transmit data in free space designated by the free space management circuit, and storing an address range in which the transmit data has been written in the second address storage unit; and a read pointer control circuit for taking the address range from the first address storage unit in a first-in order and reading out the receive data stored in the address range from the FIFO buffer to output the data to a reception destination, and for taking the address range from the second address storage unit in a first-in order and reading out the transmit data stored in the address range from the FIFO buffer to output the data to the transmitting circuit.