Patent ID: 7642539

Claim:
A memory device, comprising: a substrate; an electrode layer on the substrate, the electrode layer including an array of electrode pairs, an electrode pair in the array of electrode pairs having a first electrode having a top surface, a second electrode having a top surface, and an insulating member between the first electrode and the second electrode, the insulating member extending outwardly from the top surfaces of the first and second electrodes to define a wall of insulating material having a top side, and an array of bridges, respective bridges in the array of bridges crossing the insulating member of a corresponding electrode pair in the array of electrode pairs, a bridge in the array of bridges comprising first and second thermally insulating pads contacting the top surfaces of the first and second electrodes of the corresponding electrode pair, and an active layer of memory material on the first and second thermally insulating pads and the top side of the wall of insulating material of the corresponding electrode pair, the memory material having at least two solid phases.