Patent ID: 6873552

Claim:
A nonvolatile memory comprising: a plurality of nonvolatile memory cells; a controller; a plurality of latch circuits; a plurality of bit lines; and a plurality of word lines, wherein each of said plurality of nonvolatile memory cells has a first terminal and a second terminal, wherein each of said word lines are coupled to said first terminals of corresponding ones of said plurality of nonvolatile memory cells, wherein each of said bit lines are coupled to said second terminals of corresponding ones of said plurality of nonvolatile memory cells in parallel, and to a corresponding one of said latch circuits, wherein each of said plurality of nonvolatile memory cells coupled to one word line belongs to an arbitrary one of first ones and second ones, wherein nonvolatile memory cells belonging to said first ones have already stored first data therein, and each of said nonvolatile memory cells belonging to said first ones has one of a first state and a second state according to said first data, wherein each of nonvolatile memory cells belonging to said second ones have said first state, and wherein prior to a program operation of said first ones and said second ones, first latch circuits coupled to said first ones via first bit lines and second latch circuits coupled to said second ones via second bit lines are set with first data and second data, respectively, and wherein after setting of the first and second latch circuits with said first and said second data, said program operation of said first and said second ones are programmed in parallel bit by bit in response to said first data and said second data set in said first and second latch circuits.