Patent ID: 7539840

Claim:
A method for handling concurrent address translation cache misses and hits under those misses while maintaining command order comprising the steps of: storing commands and maintaining ordering of the commands in a command processing unit; assigning a command buffer index (CBI) to each address being sent from said command processing unit to an address translation unit; issuing said address and said CBI to said address translation unit for each address translation request; sending a first memory fetch request when a first address translation cache miss occurs in said address translation unit; sending another memory fetch request when another cache miss occurs while the first memory fetch request for the first address translation cache miss is outstanding; said command processing unit, responsive to a predefined number of outstanding address translation misses for a virtual channel, stops issuing address translation requests to said address translation unit for said virtual channel; said address translation unit, responsive to each memory fetch request being completed, sending the CBI with a signal to said command processing unit to indicate each respective memory fetch request has completed; said command processing unit, responsive to the CBI with said signal, using the CBI to locate the command and address in said command processing unit to reissue the address translation request for the previous address translation cache miss, to said address translation unit; and said command processing unit, responsive to reissuing the address translation request for a previous address translation cache miss, reissues address translation requests to said address translation unit for hits under a previous address translation cache miss with a same virtual channel, I/O Bus and I/O device.