Patent ID: 7599998

Claim:
A data processing apparatus comprising: at least one destination processor core; at least one source processor core operable to generate a message to at least two specified destination cores; a message handler having a plurality of message-handling modules; and a bus arrangement providing a data communication path between said source processor core, said destination processor core and said message handler; wherein at least one message-handling module associated with a respective specified source processor core has: a message receipt indicator being modifiable by each of said at least two specified destination processor cores to indicate through an indicator value that said message has been received at the corresponding specified destination processor core; a transmission completion detector operable to detect, in dependence upon said indicator value, that said message has been received by all of said at least two specified destination cores; and message acknowledgement generation logic responsive to said transmission completion detector detecting that said message has been received by all of said at least two specified destination cores, to initiate transmission of an acknowledgement signal to said source processor core.