Patent ID: 7664930

Claim:
A computer-implemented method comprising: identifying a type in a data processing instruction by a main processor, the type indicating one of coprocessors attached to the main processor for executing a coprocessor instruction embedded in the data processing instruction; executing the coprocessor instruction conditionally when a conditional flag of the main processor matches a condition associated with the coprocessor instruction; decoding the coprocessor instruction by the coprocessor, the coprocessor instruction that specifies an operation type including at least an add-subtract operation, a first operand stored in a first source register and having a first real component and a first imaginary component, a second operand stored in a second source register and having a second real component and a second imaginary component, and a saturation type indicating whether saturating operations are enabled and if enabled saturating with one of at least unsigned byte, signed byte, unsigned half word, signed half word, unsigned word, signed word, unsigned double word, and signed double word; executing by the coprocessor the add-subtract operation when the operation type includes the add-subtract operation to generate a first result by adding the first real component to the second imaginary component and to generate a second result by subtracting the second real component from the first imaginary component; saturating the first and second results when saturating operations are enabled; and storing the first result and the second result in a first destination register.