Patent ID: 7142473

Claim:
A semiconductor device comprising: a memory cell array having a plurality of memory cells; a first bit line connected to the memory cells and applied with a voltage read from each of the memory cells; a second bit line complementary to the first bit line, the second bit line being supplied with a first reference voltage; a sense amplifier which compares the voltage, read to the first bit line, with the first reference voltage supplied to the second bit line, and amplifies the difference between the voltage and the first reference voltage; and a plate line connected to the memory cells and supplied with a plate line voltage; and a plate line voltage generating circuit which generates the plate the plate line voltage generating circuit being supplied with a second reference voltage having temperature dependence, the plate line voltage generating circuit controlling the plate line voltage by using the second reference voltage having temperature dependence line voltage supplied to the plate line, such that a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative “1” data does not have temperature dependence.