Patent ID: 7764092

Claim:
A phase locked loop, comprising: a charge pump configured to generate a pump current based on a bias voltage and a phase difference detection signal, the pump current configured to adjust a control voltage; a self-biased voltage-current converter configured to generate the bias voltage, and configured to convert the control voltage to a converter current; and a current controlled oscillator configured to generate an oscillator current based on the bias voltage, and configured to generate an output signal that has a frequency corresponding to the oscillator current, wherein each of the charge pump, the self-biased voltage-current converter, and the current controlled oscillator includes a MOS transistor having a gate configured to receive the bias voltage, and wherein the bias voltage includes a first bias voltage and a second bias voltage, the self-biased voltage-current converter including: a bias unit configured to generate the first bias voltage and a first current that mirrors a current of the bias unit; an amplifying unit configured to generate the second bias voltage based on the first current by comparing the control voltage with a feedback voltage; and an output unit configured to generate the converter current and the feedback voltage based on the second bias voltage.