Patent ID: 6879511

Claim:
A SRAM comprising a network of rows and columns of 6T memory cells with two inverters and two switch transistors formed in a substrate of silicon-on-insulator type, the inputs of the two inverters ( 1 , 2 ) of each memory cell being connected to two bit lines (BL 0 , {overscore (BL 0 )}) via the two switch transistors ( 3 ) controlled by a signal provided by a word line (WL 0 , WL 1 ), each memory cell comprising six transistors (N 1 , P 1 , A 1 , N 2 , P 2 , A 2 ) having their gates (GN 1 , GP 1 , GA 1 , GN 2 , GP 2 , GA 2 ) corresponding to a same level of a first conductive material and having their interconnections formed by conductive tracks of at least one second conductive material distributed over three levels, each inverter comprising a first transistor (N 1 , N 2 ) of a first conductivity type and a second transistor (P 1 , P 2 ) of a second conductivity type, each switch comprising a third transistor (A 1 , A 2 ) of the first conductivity type, wherein each memory cell comprises two first regions ( 48 , 54 ) of the first conductivity type, each first region comprising the drains or the sources of a first (N 1 , N 2 ) and a third (A 1 , A 2 ) transistors, and being in contact with a second region ( 49 , 52 ) of the second conductivity type comprising the drain or the source of a second transistor (P 1 , P 2 ), the first and second associated regions being short-circuited by a third conductive material covering said first and second regions, the word line and the bit lines corresponding to conductive strips of levels higher than the first level, the conductive tracks ( 42 , 43 , 44 , 45 ) of the first level taking part in the interconnections between the inverters, and in the interconnections between the switch transistors and the word line being parallel to the bit lines.