Patent ID: RE39510

Claim:
A field programmable gate array (FPGA) device comprising: (a) a first plurality, P1 of repeated logic units wherein: (a.1) each said logic unit is user-configurable to acquire and process at least a second plurality, P2 of input logic bits and to responsively produce result data having at least a third plurality, P3 of output logic bits, (a.2) said logic units are distributed among a plurality of horizontal rows, with each row of the plurality of rows having a fourth plurality, P4 of said logic units; (b) a fifth plurality, P5 of horizontal interconnect channels (HIC's) correspondingly distributed adjacent to said horizontal rows of logic units, wherein: (b.1) each said horizontal interconnect channel (HIC) includes at least P3 interconnect lines, and (b.2) each said horizontal row of P4 logic units is configurably couplable to at least a corresponding one of the P5 HIC's at least for acquiring input logic its from the corresponding HIC and for outputting result data to the corresponding HIC; (a.3) wherein each of said logic unit can internally process its respective second plurality of input logic bits without using said horizontal interconnect channels or other general interconnect for such internal processing: and (c) an embedded memory subsystem, wherein said embedded memory subsystem includes: (c.1) a sixth plurality, P6 of independently-useable memory blocks, and wherein: (c.1a) each said independently-useable memory block is embedded within one of said rows of logic units and is configurably couplable to the corresponding HIC of said row for transferring storage data by way of the corresponding HIC of that row of P4 logic units; and (c.1b) each of said memory blocks includes at least a first address-capturing register that is programmably couplable to at least one of said HIC's for receiving and capturing in synchronism with a supplied address-strobing signal, an address signal supplied on said at least one HIC; (c.1c) each of said memory blocks includes at least a first data-capturing register for capturing said storage data in synchronism with a supplied first data-strobing signal; and (c.1d) each first address-capturing register is clockable by a first address-strobing signal that is independent of the first data-strobing signal.