Patent ID: 7454535

Claim:
An N:1 bidirectional data multiplexer, comprising: a plurality of N I/O terminals; another I/O terminal; a plurality of N data buffers each having an input coupled respectively to one of said plurality of N I/O terminals, and each having an output; N:1 Select logic having N inputs and one output, each input coupled respectively to one said output of said N data buffers, and a plurality of select lines coupled respectively to select terminals, whereby the coupling between the selected input and the output is responsive to signals present on said select terminals; a bidirectional control circuit having a first input coupled to said output of said N:1 Select logic, a first output, a second input, and a second output; an inverting comparator, having an inverting input coupled to said another I/O terminal, an output coupled to said second input of said bidirectional control circuit, and a non-inverting input coupled to a voltage Vt, wherein said voltage Vt is high enough to be above a logic “low” voltage input to said another I/O terminal by the open-drain data transceiver coupled to said another I/O terminal; a first transistor having a gate coupled to said first output of said bidirectional control circuit, a drain coupled to said another I/O terminal, and a source coupled to a voltage Vp, wherein said voltage Vp is low enough to appear as a low logic level at said another I/O terminal, yet is higher than voltage Vt so that said inverting comparator is not triggered when a logic “low” is present at one of said plurality of N I/O terminals; 1:N selection logic, having 1 input and N outputs, each output coupled respectively to one of said N outputs, and said plurality of select lines coupled respectively to said select terminals, whereby the coupling between said input and the selected output is responsive to signals present on said select terminals, and whereby further the N:1 and 1:N selection logic circuits are synchronized by coupling respective select terminals of the N:1 and 1:N logic circuits; and next N transistors, each respectively having a source coupled to ground, a gate coupled to one of said N outputs of said 1:N select logic, and a drain connected respectively to one I/O terminal of said plurality of N I/O terminals.