Patent ID: 7710427

Claim:
An arithmetic logic unit stage for use in a graphics pipeline, said arithmetic logic unit stage comprising: a plurality of scalar arithmetic logic units, each unit for performing a resultant arithmetic logic operation in the form of [a*b “op” c*d] on a set of input operands a, b, c and d and for producing a result based thereon, wherein “op” represents a programmable operation and wherein further said resultant arithmetic logic operation is software programmable to implement a plurality of different graphics functions, and wherein selection of said input operands and selection of said programmable operation for each scalar arithmetic logic unit are controlled by an instruction identifier in pixel data received by each scalar arithmetic logic unit, and each of said plurality of scalar arithmetic logic units is for determining whether to set a bit of said pixel data that will disable processing of said pixel data, wherein said determining comprises a comparison between a first subset of the input operands and a second subset of the input operands.