Patent ID: 7366270

Claim:
A dual loop synchronization system comprising: a phase lock loop (PLL) having a phase/frequency detector (PFD), a voltage controlled oscillator (VCO), and a phase shifter coupled to said VCO configured in a feedback loop with said PFD, and receiving a local reference clock signal; a first-in first-out (FIFO) register receiving a parallel data input; a write counter receiving a write clock signal and providing an output to said FIFO register; a read counter receiving a read clock signal and providing an output to said FIFO register; a comparison module receiving output signals from said write counter and said read counter to generate the fill level of said FIFO register; and a delayed lock loop (DLL) having detector coupled to the output of said FIFO register for detecting the fill level and a digital loop filter coupled between said detector and said phase shifter of said PLL to produce a phase shift in the phase shifter of said PLL.