Patent ID: 7752513

Claim:
An integrated circuit enabling a scan test using scan latches that selectively receive a scan input or a system input according to a mode selection signal, and comprising a plurality of clock domains where clocks for a test are supplied from a separate clock generation circuit, respectively, wherein in given clock domains, scan latches at a clock domain boundary configured to receive an output from other clock domains comprise a master latch configured to respond to a first clock signal and to latch an input; a slave latch configured to respond to a second clock signal and to latch an output of said master latch; a selector configured to supply a scan input to said master latch when a mode selection signal is at a first level, and to supply a system input to said master latch when said mode selection signal is at a second level; and a clock control circuit configured to turn off said first clock signal when said mode selection signal transits from said first level to said second level, wherein the clock control circuit comprises: an inverting circuit configured to invert said second clock signal, an AND gate configured to receive an output of said inverting circuit to a first input, a gate control circuit configured to disable a second input of said AND gate when said mode selection signal transits from said first level to said second level; and an output of said AND gate becomes said first clock signal.