Patent ID: 7226855

Claim:
A wiring layout method for a semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, comprising: generating data for an orthogonal wire having a first minimum wire width, which is formed in a first wiring layer and extends horizontally or vertically; generating data for a diagonal wire having a second minimum wire width which is substantially equal to said first minimum wire width, formed in a second wiring layer which differs from said first wiring layer and extending in a diagonal direction in relation to said orthogonal wire; and generating data for a via figure at point at which said orthogonal wire and said diagonal wire overlap, said via figure being constituted by a via having a size which is no greater than said first or second minimum wire width, a first via cushion conductive layer which is larger than said via and formed in said first wiring layer, and a second via cushion conductive layer which is larger than said via and formed in said second wiring layer, wherein said first or second via cushion conductive layer is larger than the minimum wire width of said orthogonal wire or said diagonal wire.