Patent ID: 7211484

Claim:
A method of manufacturing a flash memory device, comprising: providing a semiconductor substrate in which a cell region, a high-voltage transistor region and a low-voltage transistor region are defined; forming gate oxide films in the high-voltage transistor, cell and low-voltage transistor regions where the gate oxide films in the high-voltage transistor region is thicker than the gate oxide films in the low-voltage transistor and cell regions; forming a first polysilicon layer on the gate oxide films and a nitride film on the first polysilicon layer; forming a plurality of trenches for isolating the respective regions; forming field oxide films in the trenches of the cell and the low-voltage transistor and high voltage transistor regions, wherein the cell and the low voltage transistor regions have a high EFH and the high voltage transistor region has a low EFH; forming a photoresist pattern on top of the nitride film and the field oxide films in the high-voltage transistor region that has the low EFH; and performing an etching process to etch selectively the field oxide films in the low-voltage transistor and cell regions having the high EFH to reduce differences in the EFHs of the high-voltage transistor region and the low-voltage transistor and cell regions by a given thickness using a BOE solution and the photoresist pattern as an etch mask thereby, the field oxide films of the cell and the low-voltage and high voltage transistor regions have a different height.