Patent ID: 8151040

Claim:
A memory device comprising: a memory array having a plurality of memory cells arranged in a plurality of data groups, wherein each data group is identified by a data group identification and contains a version data field comprising a version number that indicates a version of a particular data group identification, wherein the version number is configured to indicate more than two versions; and a control circuit, wherein the control circuit is configured to access a data group by translating a logical address of the data group to a physical sector address of the memory array using a version number stored in the version number data field of the data group, wherein the control circuit is further configured to store one or more frequently updated logical sectors separately from non-frequently updated logical sectors and to store the one or more frequently updated logical sectors in one or more frequently updated random sector clusters, where each one or more frequently updated random sector clusters contains a version number data field and a plurality of physical blocks for storage of a single logical sector, such that each new update of the stored logical sector is written to a new unused physical block of the cluster.