Patent ID: 7510924

Claim:
A method for manufacturing a memory on a substrate having a plurality of shallow trench isolations formed therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure, the method comprising: shrinking a width of the vertical fin structure of the substrate; forming a cap layer on a top surface of the vertical fin structure of the substrate; forming a carrier trapping layer over the substrate; forming a conductive layer on the carrier trapping layer; patterning the conductive layer and the carrier trapping layer to form a straddle gate structure, wherein the straddle structure straddles over the vertical fin structure of the substrate; and forming a first source/drain region and a second source/drain region in a portion of the vertical fin structure of the substrate exposed by the straddle gate structure, wherein the straddle gate structure possesses a first carrier storage region and a second carrier storage region located on opposite sidewalls of the vertical fin structure of the substrate between the first source/drain region and the second source/drain region.