Patent ID: 7843421

Claim:
A gate driver for driving a plurality of gate lines in a liquid crystal display, the gate driver comprising: a first circuit unit for outputting a first driving signal to one odd gate line of the gate lines, comprising: a first signal output unit for receiving a first odd start signal and a first input signal to generate the first driving signal corresponding to the first input signal; and a first shift register unit for receiving the first odd start signal and a first clock signal to generate a second odd start signal, the first clock signal being different from the first input signal; a second circuit unit for outputting a second driving signal to another odd gate line of the gate lines, the second circuit unit electrically coupling to the first circuit unit and comprising: a second signal output unit for receiving the second odd start signal and the first input signal to generate the second driving signal corresponding to the first input signal; and a second shift register unit for receiving the second odd start signal and the first clock signal to generate a third odd start signal; a third circuit unit for outputting a third driving signal to one even gate line of the gate lines, comprising: a third signal output unit for receiving a first even start signal and a second input signal to generate the third driving signal corresponding to the second input signal; and a third shift register unit for receiving the first even start signal and a second clock signal to generate a second even start signal, the second clock signal being different from the second input signal; and a fourth circuit unit for outputting a fourth driving signal to another even gate line of the gate lines, the fourth circuit unit electrically coupling to the third circuit unit and comprising: a fourth signal output unit for receiving the second even start signal and the second input signal to generate the fourth driving signal corresponding to the second input signal; and a fourth shift register unit for receiving the second even start signal and the second clock signal to generate a third even start signal.