Patent ID: 8604854

Claim:
A pseudo single-phase flip-flop (PSP-FF) comprising: a master section comprising: a pre-dissipation stage having an input to accept a D 1 signal with a binary value, an input to accept a second clock (CK 2 ) that has a second delay, and is in phase with respect to a base clock signal (CLK), and an output to supply a mDb signal with a binary value in a master pass mode, in response to the D 1 and CK 2 ; a first keeper circuit connected to the pre-dissipation stage output to maintain the mDb signal binary value during a master hold mode; a slave section comprising: a pre-charge stage having an input to accept the mDb signal, an input to accept CLK and CK 2 , and an output to charge a DbMF signal with a first binary value during a slave hold mode; a second keeper connected to the pre-charge stage to maintain the DbMF first binary value in a slave pass mode when the mDb signal has a second binary value opposite in polarity to the first binary value, and to support a DbMF second binary value in the slave pass mode when the mDb signal has the first binary value; a post-dissipation stage having an input to accept the DbMF signal, an input to accept CK 2 , and an output to supply a Q signal with a binary value equal to an inverse of the DbMF binary value in the slave pass mode, in response to the DbMF and CK 2 ; a third keeper connected to the post-dissipation stage to maintain the Q signal binary value during the slave hold mode and, wherein the pre-charge stage charges the second keeper with the first binary value in response to a first phase of the base and second clocks, and dissipates the second keeper to the second binary value in response to a combination of a second phase of the base clock and the mDb first binary value; and the pre-dissipation stage discharges the first keeper to the mDb second binary value in response to the D 1 first binary value, and selectively charges the first keeper to the mDb first binary value in the master pass mode, and the pre-dissipation stage is a clocked inverter that supplies the mDb first binary value in the master pass mode when D 1 has the second binary value, and has a floating output in the master hold mode when D 1 has the second binary value.