Patent ID: 6941533

Claim:
A method of synthesizing a clock tree comprising: partitioning a circuit design into a set of memory cells and a set of non-memory cells; constructing a first clock tree having a first root vertex with a corresponding initial skew for the set of memory cells; constructing a second clock tree having a second root vertex with a corresponding initial skew for the set of non-memory cells; balancing delay between the first root vertex and the second vertex; and inserting a clock buffer at a midpoint between the first root vertex and the second root vertex; wherein partitioning a circuit design comprises partitioning the set of memory cells into segments wherein each segment satisfies the following constraints: (1) the segment includes a number of clocked cells that does not exceed an upper threshold; (2) the segment has a width that does not exceed a selected horizontal threshold; and (3) the segment has a height that does not exceed a selected vertical threshold.