Patent ID: 7836326

Claim:
A processing apparatus in which logic circuits are connected in series by pipeline registers and which performs pipeline processing, the apparatus comprising: instruction-execution-number measurement means for measuring an instruction execution number, which is the number of instructions executed per unit time; target-instruction-execution-number setting means for setting a target instruction execution number, which is a target number of instructions to be executed per unit time; control value calculation means for calculating a control value by performing proportional and integral processing on a deviation of the target instruction execution number set by the target-instruction-execution-number setting means from the instruction execution number measured by the instruction-execution-number measurement means; stage number changing means for changing the number of stages of the pipeline by performing unification processing or unification cancellation processing in accordance with the control value calculated by the control value calculation means, the unification processing being adapted to stop supply of clocks to selected pipeline registers and control the pipeline such that a signal passes through the pipeline registers, so as to partially connect the stages of the pipeline to thereby reduce the number of stages of the pipeline, and the unification cancellation processing being adapted to resume the supply of clocks to the selected pipeline registers and control the pipeline such that the pipeline registers latch the signal in synchronism with the clocks, so as to separate the connected stages of the pipeline to thereby increase the number of stages of the pipeline; and clock frequency changing means for changing a frequency of clocks supplied to the pipeline registers in accordance with the number of stages changed by the stage number changing means.