Patent ID: 8406366

Claim:
A synchronization circuit comprising: a first phase-locked loop circuit configured to output, based on a received signal being input, a first phase control signal representing a first phase control amount of said received signal; a second phase-locked loop circuit configured to output, given the same input received signal as that input to said first phase-locked loop circuit, a second phase control signal representing a second phase control amount of said received signal; a first output circuit configured to control a phase of said received signal based on said first phase control signal in order to output a first phase-controlled signal; a second output circuit configured to control the phase of said received signal based on said second phase control signal in order to output a second phase-controlled signal; a first detection circuit configured to detect a phase control error of said first phase-locked loop circuit based on the first phase-controlled signal output from said first output circuit; a second detection circuit configured to detect a phase control error of said second phase-locked loop circuit based on the second phase-controlled signal output from said second output circuit; and a control circuit configured such that if the phase control error of said first phase-locked loop circuit detected by said first detection circuit is larger than the phase control error of said second phase-locked loop circuit detected by said second detection circuit, then said control circuit sets a loop gain of a first loop filter included in said first phase-locked loop circuit to be the same as a loop gain of a second loop filter included in said second phase-locked loop circuit.