Patent ID: 6850105

Claim:
Circuitry for preserving a logic state, comprising: first circuitry for: in response to a first transition of a clock signal, receiving an information signal having a logic state; and in response to a second transition of the clock signal, latching a logic state of a first signal that indicates the received information signal's logic state; second circuitry coupled to the first circuitry for: in response to the second transition of the clock signal, receiving the first signal from the first circuitry; and in response to a third transition of the clock signal, latching a logic state of a second signal that indicates the received first signal's logic state; and third circuitry coupled to the first and second circuitry for: during a first mode of operation, supplying power to the first and second circuitry; and during a second mode of operation, reducing power to the first circuitry, while supplying power to the second circuitry, so that the first signal's logic state is lost, while the second signal's logic state is preserved.