Patent ID: 7834794

Claim:
An A/D converter comprising: a comparison circuit which compares an analog input value with a predetermined value during a first period when a first clock is at a first predetermined level, and holds the comparison result during a second period when the first clock is at a second predetermined level; a coding circuit which is reset during the first period when the first clock is at the first predetermined level, and encodes the comparison result of the comparison circuit during the second period when the first clock is at the second predetermined level; an operation period detection circuit which is operated according to an external input clock, and outputs an operation period detection signal obtained by detecting the operation period of the A/D converter; and a synthesis circuit which receives the external input clock and the operation period detection signal outputted from the operation period detection circuit, and generates the first clock; wherein the first period when the first clock is at the first predetermined level is a period equal to or longer than the period when the external input clock is at the first predetermined level.