Patent ID: 7372733

Claim:
A non-volatile semiconductor memory device, comprising: a memory array comprising a plurality of memory sectors, wherein each memory sector has a separate bulk region; an erase verifier adapted to evaluate data stored in the memory sectors of the memory array and generate an erase verification signal, wherein when the erase verifier evaluates the data stored in any one of the memory sectors, the logic state of the erase verification signal depends on the number of failed cells in the one memory sector; and, a plurality of bank voltage controllers corresponding to the respective memory sectors, wherein each of the bank voltage controllers is adapted to provide a bank voltage with a level that is sequentially controlled in response to the erase verification signal, to the bulk region of a corresponding one of the memory sectors, such that an erase pass voltage can be separately determined for each of the memory sectors in relation to the corresponding bank voltages and the erase verification signal.