Patent ID: 7711534

Claim:
A method for design verification implemented on storage medium resident on a computer infrastructure comprising: extracting resources required to run a discrete test case or set of associated test cases on a design using a processor of the computer infrastructure; building a simulation model based on the extracted resources using the processor of the computer infrastructure; executing the simulation model using only the extracted resources, exclusive of an entire design, to test a specific function or group of interrelated functions represented by the discrete test case or set of associated test cases for design verification using the processor of the computer infrastructure; parsing the resources for the test case or set of test cases associated with an upcoming simulation run using the processor of the computer infrastructure; and combining the parsed resources with common elements to produce a BOM model build file for compilation using the processor of the computer infrastructure, wherein: the BOM model build file creates “stub” files for compiling the simulation model, the stub files instruct a model build process to install a fully functional model and an empty model into the simulation model, the fully functional model behaves accurately in simulation and is synthesized for one partition or a particular group of partitions associated with the specific function or interrelated group of functions, respectively, to be verified, and the empty model is representative of remaining portions of the design which are not to be simulated and verified, and providing tie-offs using the processor of the computer infrastructure to assert all outputs of the empty model representation to an inactive state thereby ensuring that the empty model representation is not otherwise used in the simulation model.