Patent ID: 8184492

Claim:
A signal driver circuit for generating an output signal at an output in response to an input signal, the signal driver circuit comprising: an input stage including a delay line having a plurality of delay stages, the delay line configured to receive the input signal and each of the delay stages configured to add incremental delay to the input signal to provide a delayed input signal having a delay relative to the input signal and in response to the same; and an output stage coupled to the input stage to receive the delayed input signal and configured to receive the complement of the input signal, the output stage configured to couple the output to a first voltage in response to a complement of the input signal having a first logic level and to couple the output to a second voltage in response to the complement of the input signal having a second logic level, the output stage further configured to decouple the output from the first or second voltage in response to receiving the delayed input signal, wherein the output stage comprises a resistance coupled to the output to maintain the logic level of the output after decoupling of the output in response to the delayed input signal.