Patent ID: 7973337

Claim:
A semiconductor device comprising: a substrate; a PMOS source/drain region of a PMOS transistor within the substrate including: a first lightly doped sub-layer in a first trench in the PMOS source/drain region, the first trench having a first sidewall proximate a PMOS gate structure and having a second sidewall opposite from the first sidewall, the first lightly doped sub-layer extending from the first sidewall to adjoining the second sidewall, the first lightly doped sub-layer being lightly doped with an n-type dopant or a p-type dopant; a first strained layer in the first trench and over the first lightly doped sub-layer; and a first capping layer over the first strained layer; and an NMOS source/drain region of a NMOS transistor within the substrate including: a second strained layer in a second trench in the NMOS source/drain region; and a second capping layer over the second strained layer.