Patent ID: 8503252

Claim:
A sense amplifier comprising: a first inverter configured to provide a first trigger point during a pre-charge stage of a READ operation of a memory cell and provide a second trigger point different from the first trigger point during a sense stage of the READ operation of the memory cell; a pre-charge device having a first terminal coupled to a voltage potential, a second terminal coupled to a first control signal and a third terminal coupled to both an input of the first inverter and the memory cell; and a trigger level adjusting apparatus comprising: a first MOS device connected in series with the first inverter, wherein a gate terminal of the first MOS device is coupled to: the first control signal when the first MOS device is a PMOS device; and a second control signal when the first MOS device is an NMOS device, and wherein the second control signal is opposite to the first control signal; a second MOS device and a third MOS device connected in series, wherein: a gate terminal of the third MOS device is coupled to the input of the first inverter; and a gate terminal of the second MOS device is coupled to: the second control signal when the second MOS device is a PMOS device; and the first control signal when the second MOS device is an NMOS device.