Patent ID: 8379175

Claim:
A TFT array substrate comprising: a plurality of scanning lines, an insulating film covering the plurality of scanning lines, a plurality of signal lines placed on the insulating film, each of which has an intersection with a scanning line via the insulating film, a plurality of pixel electrodes, each of which is disposed adjacent to a scanning line and a signal line, a plurality of thin film transistors, each of which has a semiconductor layer, a gate insulating film, a gate electrode connected to the scanning line, a drain electrode, and a source electrode; and a plurality of relay electrodes, each of which is provided with a first overlapped portion located at the intersection with the signal line and having the same or longer length than that of the intersection, a second overlapped portion formed on the drain electrode, and a connecting portion that connects the first and the second overlapped portions, to electrically connect the signal line to the drain electrode, wherein the respective relay electrodes are formed of an electroconductive layer that is different from a layer of the drain electrodes and the source electrodes of the respective thin film transistors and the respective signal lines, and wherein the pixel electrodes are electrically connected to the source electrodes of the respective thin film transistors.