Patent ID: 6960828

Claim:
An electronic structure comprising: a conductive pad on a substrate; an insulating layer on the substrate and on the conductive pad, the insulating layer having a via therein so that a portion of the conductive pad opposite the substrate is free of the insulating layer; a seed layer on the portion of the conductive pad free of the insulating layer, on sidewalls of the via, and on a surface of the insulating layer opposite the substrate; a conductive shunt layer on the portion of the conductive pad free of the insulating layer, on sidewalls of the via, and on surface portions of the insulating layer surrounding the via opposite the substrate and the conductive pad, wherein the conductive shunt layer has a thickness of at least approximately 0.5 μm and wherein the conductive shunt layer comprises copper and wherein the seed layer is between the conductive shunt layer and the insulating layer and between the conductive shunt layer and the conductive pad; a conductive barrier layer on the conductive shunt layer wherein the conductive barrier layer comprises at least one of nickel, platinum, palladium, and/or combinations thereof; and a solder layer on the conductive barrier layer wherein the conductive shunt layer and the solder layer comprise different materials, wherein the conductive barrier layer is between the conductive shunt layer and the solder layer, wherein the conductive shunt layer, the conductive barrier layer, and the solder layer are on portions of the seed layer, and wherein portions of the seed layer are free of the conductive shunt layer, the conductive barrier layer, and the solder layer.