Patent ID: 7127657

Claim:
A data processor for processing digital data while buffering the digital data in a buffer memory, the data processor comprising: a first interface which stores the digital data in the buffer memory; a detection code processing circuit which receives the digital data when read from the buffer memory in a block unit and which generates an error detection code, wherein the detection code processing circuit adds the error detection code to the read digital data; a correction code processing circuit which generates an error correction code with the digital data and the error code, wherein the correction code processing circuit adds the error correction code to the digital data; an internal memory circuit which stores the digital data, the error detection code and the error correction code with the error detection code and the error correction code are added to the digital data; and a second interface which outputs the digital data, to which the error detection code and the error correction code are added, stored in the internal memory circuit in a block unit.