Patent ID: 7650479

Claim:
A data processing apparatus having a secure and non-secure domain, a processing device operating in said secure domain having access to secure data that is not accessible to a processing device operating in said non-secure domain, said data processing apparatus comprising: at least one processing device; a cache arranged to store data for processing by said at least one processing device, said cache comprising: a plurality of entries, each entry being arranged to store one or more data items, said data items including a status field, said status field being arranged to store a security value indicative of whether said one or more data items are secure data, non-secure data or aliased data, wherein said secure data are only accessible in response to a secure data access request, said non-secure data are accessible in response to a non-secure data access request and said aliased data are accessible in response to either a secure or a non-secure data access request; and a bus fabric arranged to transfer data between components of said data processing apparatus, said bus fabric arranged to provide security data in response to a bus access request, said security data being indicative of whether said bus access request is to a storage location designated as secure, non-secure or aliased; wherein at least one of said security values stored in said status fields are derived from security data provided by said bus access request, wherein said status field further comprises a verification flag associated with each entry, said verification flag being indicative of whether said security value of said status field has been confirmed from security data provided by said bus fabric in response to said bus access request to correspond to a security level of a corresponding entry in said memory unit, and wherein in response to a data access request to said cache where said security value does not match a security level of said data access request, said cache is arranged to signal a cache miss if said security value is a verified security value, or to access a corresponding memory location via said bus fabric if said security value if not verified, and to update said security value with security data provided by said bus fabric and to mark said updated security value as verified.