Patent ID: 6930921

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cell blocks arranged in a column direction and n control gate lines provided for each of the plurality of memory cell blocks, each of the memory cell blocks including a plurality of memory cell units arranged in a row direction and each connected to the n control gate lines provided for the memory cell block, each of the plurality of memory cell units including n (n is an integer not smaller than 3) electrically data programmable and erasable memory transistors which are arranged in the column direction and whose current paths are serially connected, a first selection gate transistor having a current path connected at one end to one end of a current path of the series-connected memory transistors and connected at the other end to a bit line, and a second selection gate transistor having a current path connected at one end to the other end of the current path of the series-connected memory transistors and connected at the other end to a source line, and each of the n control gate lines being commonly connected to control gates of those of the memory transistors which are arranged on a corresponding one of rows in the memory cell units of each of the memory cell blocks; and a programming circuit configured to program data by holding channel voltage of a selected memory transistor in a selected memory cell unit at a low level when high positive voltage is applied to a selected control gate line and simultaneously to inhibit programming data into all non-selected memory transistors connected to the same selected control gate line by self-boosting channel voltages using capacitive coupling with at least one of the control gate lines, wherein a voltage is applied to a (k+j)th (j is an integer of not smaller than 2) non-selected control gate line to cut off the memory transistors connected to the (k+j)th non-selected control gate line when the selected control gate line is a kth line (k is an integer of 1 to n) from the bit line side.