Patent ID: 8780666

Claim:
A decoupling capacitance (decap) calibration method for a DRAM, comprising: a plurality of parallel decoupling capacitors receiving a supply voltage, the plurality of capacitors being electrically connected to logic circuitry and the plurality of capacitors exhibiting a plurality of different capacitance values, wherein individual capacitors are independently turned on or off according to a plurality of bitstate inputs; decap bitstate calibration circuitry selectively updating the plurality of bitstate inputs in response to a determination signal; a voltage detector electrically connected to the plurality of capacitors and the decap bitstate calibration circuitry receiving a reference voltage and a voltage at an output of the plurality of capacitors and comparing the voltages to enable generating the determination signal, wherein when the voltage at the output of the plurality of capacitors is less than the reference voltage, an output of the voltage detector will undergo a level transformation; and fail determination circuitry electrically connected between the voltage detector and the decap bitstate calibration circuitry, the fail determination circuitry generating a ‘fail’ determination signal in response to the level transformation.