Patent ID: 7672395

Claim:
A predistorter, comprising: a divider that divides an input signal and supplies the divided input signals to a linear transmission path and a distortion generating path; a (2k−1)th-order distortion generator that raises the divided input signal supplied to said distortion generating path to the (2k−1)th power to generate a distortion component, where k denotes an integer equal to or greater than 2; a first vector adjusting means that adjusts the amplitude and phase of an output signal of said (2k−1)th-order distortion generator; and addition means that sums up an output signal of said first vector adjusting means and an output signal of said linear transmission path and outputs the predistorted input signal, wherein said (2k−1)th-order distortion generator comprises: a (2k−1)th-order multiplier that raises the divided input signal supplied to said distortion generating path to the (2k−1)th power; a (2J−1)th-order multiplier that raises said divided input signal to the (2J−1)th power, where J denotes an integer falling within a range of k>J≧1; a first vector adjuster that adjusts the amplitude and phase of an output of said (2J−1)th-order multiplier; and a first adder that sums up the output of said first vector adjuster and an output of said (2k−1)th-order multiplier and outputs the sum result as an output of said (2k−1)th-order distortion generator, and said first vector adjuster is configured to perform the amplitude and phase adjustments of the output of said (2J−1)th-order multiplier so as to suppress a lower-than-(2k−1)th-order component produced by said (2k−1)th-order multiplier in the output of said first adder.