Patent ID: 7763515

Claim:
A method, comprising: providing a base comprising a biaxially strained first semiconductor material and a second semiconductor material laterally adjacent said first semiconductor material, said second semiconductor material having a different strain state than said biaxially strained first semiconductor material; bonding said base including said first and second semiconductor materials to a substrate; exposing at least a first portion of said biaxially strained first semiconductor material and a second portion of said second semiconductor material at a surface opposite said substrate; embedding a third semiconductor material in said biaxially strained first semiconductor material such that a portion of said third semiconductor material defines at least a portion of a plurality of source/drain regions of a first transistor, wherein said source/drain regions have a channel region therebetween, said channel region comprising said biaxially strained first semiconductor material, said biaxial strain in said first semiconductor material acting to influence a lattice mismatch at an interface portion between the first semiconductor material in the channel region and the third semiconductor material so as to increase a strain transfer into the channel region; and forming a second transistor in said second semiconductor material.