Patent ID: 8881081

Claim:
A delay parameter extracting apparatus, comprising: a schematic composing unit configured to: facilitate design of a schematic circuit; and generate a first net list based on the design of the schematic circuit; a layout composing unit configured to: facilitate design of a layout based on the schematic circuit; and generate a second net list based on the design of the layout; a verification unit configured to verify the layout by comparing the first net list to the second net list; and a parameter extracting unit configured to: extract capacitance (C) values from the layout; and extract delay parameters based on the C values with respect to respective nets according to types of delay parameters associated with the respective nets, wherein the parameter extracting unit comprises: a critical value setting unit configured to: set critical values for dividing the C values into sectors; and determine a first sector for extracting resistance-capacitance (RC) values, a second sector for extracting only C values, and a third sector for ignoring corresponding nets; and an RC extracting unit configured to: extract RC values with respect to nets comprising C values corresponding to the first sector; extract only C values with respect to nets comprising C values corresponding to the second sector; and ignore nets comprising C values corresponding to the third sector.