Patent ID: 7376802

Claim:
A memory arrangement comprising: a controller and a plurality of memory devices, wherein data signals, control signals and address signals are transferred between the controller and the memory devices; and data signal lines, each data signal line for transferring the data signals as well as the control signals or the address signals between the controller and the memory devices such that the data signals, the control signals and the address signals are transferred between the controller and the memory devices via the data signal lines, wherein said memory devices are adapted to both, to store data in memory cells thereof and to read out data stored in said memory cells, whereby said data to be stored and to be read out is transferred via said data signal lines, wherein the memory devices are individually connected to the controller via the data signal lines carrying the data signals, the control signals and the address signals, and wherein the memory arrangement is adapted to transferring said signals in a Simultaneous Bi-directional Signaling Mode such that all of the data signals, all of the address signals, and all of the control signals are transferable via the data signal lines within one single cycle, wherein the number of memory devices is chosen such that the total number of data signals that can be transferred between the controller and the memory devices, together with the associated data signal lines, is at least equal to the total number of lines required for transferring the address signals and the control signals between the controller and an individual one of the memory devices, wherein the total number of data signals that can be transferred between the controller and the individual one of the memory devices, together with the associated data signals, is less than the total number of lines required for transferring the address signals and the control signals between the controller and the individual one of the memory devices, and wherein the memory devices are configured such that a portion of the control signals and/or of the address signals can be transferred directly between the memory devices.