Patent ID: 8625353

Claim:
An apparatus, comprising: a plurality of flash memory devices, wherein each flash memory device of the plurality of flash memory devices is arranged to be powered by a power supply voltage, wherein each flash memory device of the plurality of flash memory devices includes a random access memory, wherein a first subset of the plurality of flash memory devices is configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory device of the first subset of flash memory devices performs actions, including: loading the random access memory with instructions for the each flash memory device of the first subset of flash memory devices, executing a first portion of the instructions for the each flash memory device of the first subset of flash memory devices, after executing the first portion of the instructions for the each flash memory device of the first subset of flash memory devices, employing a countdown timer to wait for a first delay period after executing the first portion of the instructions for the each flash memory device of the first subset of flash memory devices, and after waiting for the first delay period, executing a second portion of the instructions for the each flash memory device of the first subset of flash memory devices, and wherein a second subset of the plurality of flash memory devices is configured such that, upon the power supply voltage reaching the pre-determined level, each flash memory device of the second subset of the plurality of flash memory devices performs actions, including: loading the random access memory with instructions for the each flash memory device of the second subset of flash memory devices, executing a first portion of the instructions for the each flash memory device of the second subset of flash memory deivces, after executing the first portion of the instructions for the each flash memory device of the second subset of flash memory devices, employing another countdown timer to wait for a second delay period after executing the first portion of the instructions for the each flash memory device of the second subset of flash memory devices, wherein the second delay period is different than the first delay period, and after waiting for the second delay period, executing a second portion of the instructions for the each flash memory device of the second subset of flash memory devices.