Patent ID: 8183639

Claim:
A dual port static random access memory cell having pull-down transistors, pull-up transistors, and pass transistors, comprising: a first active region having a first pull-down transistor coupled to a first data node, a second pull-down transistor coupled to a complementary data node that is complementary to the first data node; a first pass transistor coupled to the first data node, the first pass transistor having a current electrode coupled to a contact for contacting a first bit line, and a second pass transistor coupled to the complementary data node, the second pass transistor having a current electrode coupled to a contact for contacting a first complementary bit line for carrying data complementary to data carried by the first bit line; a second active region having the same size and shape as the first active region having a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the first data node, the third pass transistor having a current electrode coupled to a contact for contacting a second bit line, and a fourth pass transistor coupled to the complementary data node, the fourth transistor having a current electrode coupled to a contact for contacting a second complementary bit line for carrying data complementary to data carried by the second bit line; and a first pull-up transistor and a second pull-up transistor located between the first and second active regions.