Patent ID: 8084802

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells, a first select gate transistor and a second select gate transistor, plurality of memory cells being connected in series, the plurality of memory cells being located between a source of the first select gate transistor and a drain of the second select gate transistor; a first source line located along a first direction in the memory cell array, the first source line being connected to a source of the second select gate transistor; a word line located along the first direction, a gate electrode of one of the plurality of memory cells being connected to the word line; a bit line located along a second direction perpendicular to the first direction, the bit line being connected to a drain of the first select gate transistor; and wherein the first source line is located above the word line and the first source line is located below the bit line.