Patent ID: 8136106

Claim:
A system, comprising: at least one processor; a main memory operatively connected to the at least one processor; at least one cache operatively connected to the main memory and the at least one processor; a program software to be executed by the at least one processor, the program software includes at least one marker, wherein each marker is a computer instruction and marks distinct computer code sections in the software; and a marker management engine operatively connected to the at least one processor, the main memory, and the at least one cache; wherein the marker management engine (a) determines whether one of the at least one marker has been executed during the execution of the program software, (b) monitors data accesses by the at least one processor to the at least one cache and the main memory, (c) stores at least one of the monitored data accesses in a pre-defined location in the main memory, and (d) optimizes only the computer code section indicated by the determined marker of the program software executed by the at least one processor based on the stored data accesses to reduce stalls of at least one of the processors associated with the section, wherein the engine optimizes by: monitoring data access patterns in executing the computer code section; storing information related to the data access patterns; retrieving the information related to the data access patterns when the at least one marker is reached; and executing one of a cache state update operation or a prefetch instruction operation using the retrieved information.