Patent ID: 7875915

Claim:
An integrated circuit, comprising: at least one photodiode associated with a read transistor, said photodiode comprising a stack of three semiconductor layers including a buried layer, a floating substrate layer and an upper layer, wherein the upper layer incorporates a drain region of the read transistor, wherein the buried layer is electrically isolated from the drain region in the upper layer and wherein the buried layer is adapted to receive a bias voltage independent of any voltage on the upper layer; and further including a semiconductor contact region of a same conductivity type as the buried layer and a structure for electrically isolating the semiconductor contact region from the upper layer, said semiconductor contact region being formed in electrical connection with the buried layer so as to support application of the bias voltage to said buried layer; wherein the semiconductor contact region comprises an upper region, an intermediate region which has a lower dopant concentration than the upper region, and a lower region which has a lower dopant concentration than the intermediate region, the lower region being in contact with the buried layer.