Patent ID: 6870771

Claim:
A nonvolatile semiconductor memory device comprising: a control circuit for controlling at least an erasure operation of said nonvolatile semiconductor memory device: a memory cell array having a plurality of memory cells arranged in a matrix, said memory cell array being divided into a plurality of memory blocks, each said memory cell including a memory element that can store data in a nonvolatile manner, each said memory element including a first node and second node, and configured for erasing stored data in response to application of a predetermined voltage across at least said first and second nodes; a plurality of power supply lines, provided corresponding to said memory blocks, respectively, for supplying in common a first potential to said first node of a plurality of said memory elements in a corresponding memory block; a plurality of word lines provided corresponding to a row in said memory cell array, each word line coupled with said second node of said memory element belonging to a corresponding row; a row select circuit for supplying a second potential having said predetermined voltage with respect to said first potential selectively to each of said plurality of word lines under control of said control circuit; and a potential drive circuit for supplying said first potential selectively to each of said plurality of power supply lines under control of said control circuit, wherein said row select circuit is configured for supplying a verification potential selectively to each of said plurality of word lines under control of said control circuit, said nonvolatile semiconductor memory device further comprising: a plurality of bit lines provided for every column in said memory cell array, each bit line for reading out data from said memory element belonging to a corresponding column, and a sense amplifier for detecting a data level read out via said bit line, wherein said control circuit is configured for determining for every word line an erased state of said memory element in an amplification of said verification potential according to a detected result of said sense amplifier.