Patent ID: 8086914

Claim:
A system for storing data on a low-latency random read memory (LLRRM) device, the system comprising: the LLRRM device comprising a plurality of memory chips for storing data, each chip comprising a plurality of erase units, each erase unit (EU) having an EU identifier, each chip comprising a set of reserve EUs; and a storage operating system engine configured for: maintaining, for each chip, a remapping data structure for storing remapping data for remapping defective EUs to reserve EUs in the chip; detecting a defective EU having a first EU identifier in a “marked” chip, the remaining chips comprising “non-marked” chips; remapping the defective EU to a selected reserve EU of the marked chip by updating the remapping data structure for the marked chip, the selected reserve EU having a second EU identifier; receiving at least one data block for storing to the LLRRM device; and striping each received data block across the plurality of chips in a non-aligned manner, the striping comprising: sub-dividing the data block into a plurality of data sub-blocks; in the marked chip, storing a data sub-block to the selected reserve EU having the second EU identifier; and in each non-marked chip, storing a data sub-block to an EU having the first EU identifier.