Patent ID: 8804446

Claim:
A semiconductor device comprising: a memory cell array including a plurality of bit lines having at least a pair of bit lines, a plurality of sub word lines, and a plurality of memory cells disposed at intersections of the bit lines and the sub word lines; a sense amplifier including a first drive circuit that drives one of the pair of bit lines to a first potential, a second drive circuit that drives other one of the pair of bit lines to a second potential higher than the first potential, and an equalizing circuit that equalizes the pair of bit lines to substantially a same potential; a timing control circuit that generates an equalizing signal and a timing signal having an amplitude ranging from the first potential to a third potential higher than the first potential; an equalizing control circuit that converts a level of the equalizing signal into a fourth potential higher than the second and third potentials and supplies the equalizing signal having the fourth potential to the equalizing circuit; and a word driver that controls the sub word lines based on the timing signal, wherein the word driver including a timing adjustment circuit that changes an operation timing of the sub word lines in accordance with a level of the fourth potential.