Patent ID: 7376685

Claim:
An apparatus for computing a SHA-1 hash function to allow compression of a message, the apparatus comprising: a first register unit including a plurality of registers that store a first bit string of predetermined lengths for generation of a hash function value; a second register unit storing input data in units of second bit strings with predetermined lengths, and sequentially outputting the second bit strings; a third register unit performing an operation on the first bit string of the plurality of registers and the second bit strings output from the second register unit so as to generate and store a third bit string, and updating first-bit string of the plurality of registers based on the third bit string; and an adding unit combining the first bit string stored in the first register unit, the first bit string of the third bit string stored in the third register unit, and the original initial values stored in the first register unit so as to obtain a hash function value, wherein the second register unit comprises: a shift register dividing the input data into units of 32 bits to obtain first through sixteenth W data, outputting the first W data that is the most significant 32 bit data, and shifting the input data by 32 bits in the left direction; and a feedback unit performing an exclusive OR (XOR) operation on a result of performing the XOR operation on the first and third W data and a result of performing the XOR operation on the ninth and fourteenth W data, shifting a final result of the XOR operation by a 1 bit, and feeding back a result of shifting.