Patent ID: 6845028

Claim:
A semiconductor device, comprising: a first memory block having a plurality of first memory cells coupled to a plurality of first data lines and a first word line; a second memory block having a plurality of second memory cells coupled to a plurality of second data lines and a second word line; and a first block provided between the first and second memory blocks and including a plurality of sense amplifiers, wherein each of said plurality of sense amplifiers is coupled to one of said plurality of first data lines and one of said plurality of second data lines, wherein each sense amplifier has a first P type MISFET, a second P type MISFET, a first N type MISFET, and a second N type MISFET, wherein gates of said first P type MISFET and said first N type MISFET are electrically coupled together, and drains of said second P type MISFET and said second N type MISFET are electrically coupled together, wherein gates of said second P type MISFET and said second N type MISFET are electrically coupled together, and drains of said first P type MISFET and said first N type MISFET are electrically coupled together, and wherein a first semiconductor region forming said drain of first P type MISFET is more than half surrounded by a first layer forming said gate of said first P type MSFET.