Patent ID: 8022741

Claim:
A digital electronic device, comprising: a first sequential logic unit and a second sequential logic unit for receiving an input signal and for outputting a first output signal and a second output signal, respectively, a comparator unit for comparing the first and second output signals, wherein the comparator unit comprises a first NMOS transistor and a second NMOS transistor, wherein the first and second NMOS transistors are configured to receive the first and second output signals and complements of the first and second output signals, and an adaptive clock generator unit for generating a first internal clock signal and a second internal clock signal for the first and second sequential logic units based on a first clock signal, respectively, wherein in a self-tuning mode the adaptive clock generator unit is configured to delay the first or second internal clock signal with respect to the second or first internal clock signal, wherein the delay induced by the adaptive clock generator unit is dependent on the result of the comparator unit, and wherein in a normal operation mode the adaptive clock generator unit is configured to maintain the delay between the first and second internal clock signals constant.