Patent ID: 7383424

Claim:
A computer system, comprising: a first processor; a second processor for use as a coprocessor to the first processor; a coprocessor controller; a memory; a buffer memory from which the second processor loads data and to which the second processor stores data, wherein the buffer memory is adapted to load data from the memory and store data to the memory; a first decoupling element; and a second decoupling element, wherein computations are passed to the second processor from the first processor through the first decoupling element, such that the second processor executes computations passed from the first processor through the first decoupling element, and wherein the second processor receives data from and writes data to the memory, and wherein the coprocessor controller controls the activity of the second processor to ensure execution of the second processor is correctly ordered with respect to loads from memory, whereby the execution of computations by the second processor is decoupled from the operation of the first processor such that the second processor executes computations passed from the first processor through the first decoupling element while the first processor is providing further instructions to the first decoupling element, and further wherein memory instructions relating to movement of data between the buffer memory and the memory are passed to the buffer memory from the first processor through the second decoupling element, such that the buffer memory consumes instructions derived from the first processor through the second decoupling element, whereby the processing of memory instructions by the buffer memory is decoupled from the operation of the first processor.