Patent ID: 8129200

Claim:
A method for manufacturing a nonvolatile ferroelectric memory device having a cell array block including a plurality of unit cells, the method comprising: forming cell transistors on a semiconductor substrate; forming contact nodes for connecting cell capacitors to the cell transistors; forming a first insulating film over the cell transistors and the contact nodes; selectively etching the first insulating film to form trenches, wherein each of the trenches exposes a plurality of contact nodes; forming a plurality of storage nodes connected to the plurality of contact nodes on an inner surface of each of the trenches, wherein the storage nodes are separated from each other and the plurality of storage nodes that are separated from each other are formed on an inner surface of each of the trenches, each storage node formed to be L-shaped on an inner surface of each of the trenches; forming a ferroelectric layer over the storage nodes; and forming a plate line over the ferroelectric layer.