Patent ID: 7372392

Claim:
A method for charge balancing in a current input ADC, the current input ADC comprising a charge balancing modulator formed by an integrator providing an integrator output voltage at an integrator output node and a plurality of active device switches, the modulator being configured by active device switches to operate in alternate integration and autozero phases, the method comprising: maintaining a low capacitance value at the integrator output node where the capacitance value is independent of the integrator output voltage and does not vary operating conditions of the current input ADC; generating a first voltage pedestal at the integrator output node by a first active device switch at the end of the autozero phase of the modulator, the first voltage pedestal having a first voltage polarity and having a first magnitude; generating a second voltage pedestal at the integrator output node by a second active device switch at the end of the integration phase of the modulator, the second voltage pedestal having a second voltage polarity, opposite to the first voltage polarity, and having the first magnitude; and summing the first voltage pedestal with the second voltage pedestal at the integrator output node, the difference between the first voltage pedestal and the second voltage pedestal resulting in a net voltage error; wherein the first and second voltage pedestals have the first magnitude under all operating conditions of the current input ADC and the two voltage pedestals cancel to yield a near zero net voltage error at the integrator output voltage.