Patent ID: 8368578

Claim:
An analog-to-digital converter (ADC) circuit configured to convert an analog input voltage signal (Vin) into a digital code representative of said analog input voltage signal (Vin), said ADC circuit comprising: at least one input node configured to apply an analog input voltage signal (Vin); a means for sampling said analog input voltage signal (Vin), yielding a sampled analog input voltage signal; a first array of capacitors of substantially the same size configured to receive said sampled analog input voltage signal at the first terminals of said capacitors; a digital delay line comprising a plurality of stages whereby the interconnections between consecutive stages form the second terminals of said capacitors of said first array, said digital delay line configured to be enabled by a clock generator and configured to generate a slope or staircase function by means of said first array of capacitors and said sampled analog input voltage signal; and a comparator configured to compare a converted signal with a reference voltage (Vref), said converted signal being said sampled analog input voltage converted according to said staircase or slope function, wherein the comparator is further configured to generate a stop signal to latch said delay line based on the comparison result, and wherein a digital code representative of said analog input voltage signal (Vin) is obtained from said digital delay line.