Patent ID: 7191291

Claim:
A variable latency cache memory, comprising: an input, for specifying a type of an instruction requesting to read data from the cache memory, wherein said type is one of a plurality of predetermined instruction types; and a plurality of storage elements, coupled to said input, configured as a last-in-first-out (LIFO) memory, and configured to store data exclusively specified by push instructions, wherein each of said push instructions implicitly specifies a data memory address based on a value stored in a microprocessor stack pointer register rather than explicitly specified by the push instruction, and for providing said requested data in a first number of clock cycles if said input specifies a pop instruction type of said plurality of predetermined instruction types, and for providing said requested data in a second number of clock cycles if said input specifies a load instruction type of said plurality of predetermined instruction types, wherein said first and second number of clock cycles is different.