Patent ID: 6894332

Claim:
A DRAM circuit comprising: a substrate having an active region thereon and a capacitor structure disposed above the active region, the capacitor structure including a storage node, a dielectric layer overlying the storage node, and a conductive cell plate overlying the dielectric layer, each of the dielectric layer and the conductive cell plate having an end portion proximate a conductive contact, the conductive contact extending downward and adjacently beside the capacitor structure, the end portion of the dielectric layer extending closer to the conductive contact than the end portion of the conductive cell plate; a first TEOS layer disposed proximate the storage node; a second TEOS layer disposed over the capacitor structure and encasing the end portions of the dielectric layer and the conductive cell plate, the second TEOS layer disposed between the capacitor structure and the conductive contact; and a doped BPSG layer disposed over the second TEOS layer, the conductive contact extending through the BPSG layer and the second TEOS layer.