Patent ID: 8413102

Claim:
A method comprising: receiving a design description of an integrated circuit and a description of one or more scan chains in the integrated circuit, each scan chain comprising a serial connection of clocked storage devices, the serial connection formed by connecting scan in inputs and scan out outputs of the clocked storage devices; assigning probabilities to each possible state transition for each clocked storage device in the one or more scan chains based on a scan test pattern of alternating binary one and binary zero values, wherein the scan test pattern is serially shifted through the scan chains during a scan test using the serial connection; responsive to the probabilities and the design description, identifying instance voltage drop (IVD) failures the would occur during scan testing in the integrated circuit, wherein the IVD failures are identified prior to tapeout of the integrated circuit; identifying a plurality of clocked storage devices that experience the IVD failures; and excluding the plurality of clocked storage devices during scan test pattern generation by an automated test pattern generation tool.