Patent ID: 7336748

Claim:
A method of synchronizing a DDS circuit clocked at a DDS frequency to a first clock, with a first phase increment of the DDS being specified for a period of the first clock, comprising: a) generating a clock at the DDS frequency from the first clock, the DDS frequency being a non-integer multiple of the frequency of the first clock; b) producing a DDS phase increment by scaling the first phase increment in proportion to the ratio between the DDS frequency and the frequency of the first clock; c) accumulating the DDS phase increment in a DDS accumulator within the DDS circuit that is clocked by the clock at the DDS frequency; d) accumulating the first phase increment in a second accumulator, the second accumulator clocked by the first clock; and e) periodically replacing the value in the DDS accumulator with the value in the second accumulator at an interval determined by the ratio between the DDS frequency and the frequency of the first clock, wherein the interval is an integer multiple of the product of the period of the first clock and the frequency of the first clock divided by the greatest common multiple of the first clock frequency and the DDS frequency.