Patent ID: 8462096

Claim:
A shift register comprising: a first output circuit controlled by a first clock signal to output a signal to a first output signal line; a second output circuit controlled by a second clock signal with a phase different from a phase of the first clock signal to output a signal to a second output signal line; a first control signal line connected to the first and second output circuits; and a second control signal line connected to the first and second output circuits, wherein each of the first and second output circuits comprises first and second transistors; the first transistor of the first output circuit includes a gate connected to the first control signal line, a first terminal connected to a power supply, and a second terminal connected to the first output signal line; the second transistor of the first output circuit includes a gate connected to the second control signal line, a first terminal connected to a signal line for the first clock signal, and a second terminal connected to the first output signal line; the first transistor of the second output circuit includes a gate connected to the first control signal line, a first terminal connected to the power supply, and a second terminal connected to the second output signal line; and the second transistor of the second output circuit includes a gate connected to the second control signal line, a first terminal connected to a signal line for the second clock signal, and a second terminal connected to the second output signal line.