Patent ID: 6859109

Claim:
A phase-aligning phase-locked loop (PLL) comprising: a phase-frequency detector having a reference input and a feedback input, for determining phase differences between the reference input and the feedback input; a loop filter for generating a control voltage; a charge pump, controlled by the phase-frequency detector, for charging and discharging the loop filter to adjust the control voltage; a voltage-controlled oscillator (VCO) generating multi-phase output clocks having an output frequency controlled by the control voltage from the loop filter; an analog divider, receiving at least two of the multi-phase output clocks from the VCO, and generating a divided analog feedback clock having a feedback frequency that is the output frequency divided by a positive power of two; a clock buffer, receiving the divided analog feedback clock, for generating a digital feedback clock; a feedback digital divider, receiving the digital feedback clock, for generating a final feedback clock having a final feedback frequency that is the feedback frequency divided by a positive power of two; and a feedback flip-flop, receiving the final feedback clock and clocked by the digital feedback clock, for generating a phase-aligned feedback clock to the feedback input of the phase-frequency detector; whereby the analog divider and digital divider are in a feedback path.