Patent ID: 6838339

Claim:
A method of forming a capacitor for use with an integrated circuit comprising the steps of: providing a substrate having an electrical contact area and covered by an insulating layer having a top surface, said insulating layer defining a via extending from said top surface to said electrical contact area; forming a patterned hard mark structure over said insulating layer; depositing a layer of a-Si (amorphous silicon) over said patterned hard mask structure and said insulating layer, said layer of a-Si having an exposed textured surface; forming a layer of conductive material over said layer of a-Si to form a bottom plate, said bottom plate in electrical contact with said electrical contact area of said substrate and having an inside surface that conforms to said textured surface of said a-Si layer; removing said patterned hard mask and said layer of a-Si to form a free standing bottom electrode; depositing a layer of dielectric material over said free standing bottom electrode; and depositing a conductive capacitor plate layer over said layer of dielectric material.