Patent ID: 6978027

Claim:
In a reverb processor that includes delay lines implemented in delay line memory and having delay taps implemented by read pointers into the delay line memory, a method, comprising: for each delay line having a read pointer to be moved: providing a level control variable having an initial amplitude; selecting a first delay line: prior to moving the read pointer of the first delay line, ramping down the amplitude of the level control variable for the first delay line to a target amplitude; moving the read pointer of the first delay line when the amplitude level control variable for the first delay line has reached the target amplitude; ramping the amplitude of the level control variable of the first delay line back to the first initial level subsequent to moving the read pointer of the first delay line; subsequent to ramping the amplitude of the level control variable of the first delay line back to the first initial level, selecting a second delay line: prior to moving the read pointer of the second delay line, ramping down the amplitude of the level control variable for the second delay line to a target amplitude; moving the read pointer of the second delay line when the amplitude level control variable for the second delay line has reached the target amplitude; ramping the amplitude of the level control variable of the second delay line back to the second initial level subsequent to moving the read pointer of the second delay line.