Patent ID: 7663408

Claim:
A dynamic circuit latch comprising: a domino component, for receiving a clock signal and an input signal, and for producing an output signal; and a state component, coupled to the domino component, for retaining the output signal, wherein an output of said state component is coupled to an output of said domino component, comprising: a first tri-state buffer, wherein the first tri-state buffer is coupled to a first scan clock signal; a second tri-state buffer coupled to the first tri-state buffer, wherein the second tri-state buffer is coupled to the clock signal, and wherein the domino component and the state component are configured to assume a tri-state when induced by the clock signal, such that the output signal is held at the state component, and wherein the input signal cannot alter the output signal while so held, and wherein the first tri-state buffer and the second tri-state buffer are configured to function as an exposed, scannable latch when the domino component is in the tri-state, and wherein the first scan clock signal and the clock signal are separate clock signals; and a slave latch configured for monitoring the output signal, wherein the slave latch is coupled to a second scan clock signal.