Patent ID: 7208419

Claim:
A method for fabricating a semiconductor device, which comprises the steps of: forming a gate line on a semiconductor substrate; forming successively a buffer layer, a spacer nitride film, and a spacer oxide film on the entire surface of the substrate including the gate line; selectively etching the buffer layer and the spacer nitride film in such a manner that they remain on both sides of the gate line; performing an ion implantation process using the remaining buffer layer and spacer nitride film as a barrier film to form junction regions in the semiconductor substrate at both sides of the gate line; subjecting the entire upper portion of the substrate including the junction regions to a rapid thermal annealing (RTA) process; forming an interlayer insulating film on the entire upper portion of the resulting substrate; selectively removing the interlayer insulating film to form contact holes exposing the upper surface of the junction regions; and forming contact plugs in the contact holes.