Patent ID: 7493430

Claim:
An apparatus comprising a first serial-to-parallel interface bridge that presents a serial data storage device mode interface to a data storage host adapter; a second serial-to-parallel interface bridge that presents a serial host mode interface to a removable data storage unit; a task file register; a command data buffer; a processor; a memory; and executable instructions physically stored in a tangible medium and, when executed, operable to cause the processor and the apparatus to interpret a command stored in the command data buffer; conditionally transmit at least one command to the removable data storage unit based on the command stored in the command data buffer; and a data flow control circuit operably connected to the first serial-to-parallel interface bridge and the second serial-to-parallel interface bridge, wherein the data flow control circuit; writes commands received on the task file register via the first serial-to-parallel interface bridge to the command data buffer; and conditionally connects, responsive to a command transmitted by the processor, the second serial-to-parallel interface bridge to the task file register to enable direct transfer of data between the first serial-to-parallel interface bridge and second serial-to-parallel interface bridge.