Patent ID: 7884009

Claim:
A method for fabricating a stacked semiconductor device, comprising the steps of: fabricating a first semiconductor device including the steps of: providing a substrate having first and second surfaces, further having at least one semiconductor chip assembled on the first substrate surface; the substrate having a first plurality of copper contact pads in positions surrounding the assembled at least one chip on the first substrate surface, and a second plurality of copper contact pads on the second substrate surface; fabricating a second semiconductor device including the steps of: providing a substrate having first and second surfaces, further having at least one semiconductor chip assembled on the first substrate surface; the substrate having copper contact pads on the second substrate surface, positioned to match the first pad plurality of the first device; selecting solder bodies as substantially uniform alloys of: tin of a first weight percent; silver of a second weight percent; and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements in the amount of about 0.01 to about 0.5 weight percent; attaching and reflowing a solder body to each pad on the second semiconductor device to create a layer of intermetallic compounds between each copper pad and solder body, the compounds including grains of copper and tin compounds and copper, silver, and tin compounds; the compounds containing the at least one transition metal; aligning the second device with the first device so that each solder body is in contact with the corresponding first plurality pad of the first device; reflowing the solder bodies; attaching a alloy solder body to each second plurality pad of the first device; and reflowing the solder bodies.