Patent ID: 8889509

Claim:
A method for manufacturing a memory cell, the method comprising: forming a semiconductor substrate having a surface with a source region and a drain region in the substrate and separated by a channel region; forming a multilayer stack over the channel including a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers sufficient to suppress direct tunneling disposed on the surface of the substrate above the channel region, a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region, a dielectric charge trapping structure disposed above the conductive layer and above the channel region, and a top dielectric structure disposed above the charge trapping structure and above the channel region; and forming a word line disposed above the top dielectric structure and above the channel region; wherein the conductive layer in the multilayer stack has an area over the channel region equal within manufacturing limitations to an area of the channel region beneath the word line and between the source and drain, wherein the multilayer stack has an effective oxide thickness and the channel region has a length between the source and the drain, and a width orthogonal to the length less than 1.5 times the effective oxide thickness of the multilayer stack.