Patent ID: 7936000

Claim:
A DRAM array, comprising: a substrate; M polysilicon digit lines formed in the substrate, wherein M is a positive integer; an M×N array of vertical transistors formed on the plurality of digit lines, wherein N is a positive integer and N transistors are formed on each digit line and are aligned with the transistors formed on adjacent rows to define N columns of transistors, and wherein each transistor comprises: a polysilicon pillar epitaxially grown from one of the polysilicon digit lines, the pillar having a top end, a top portion, a central portion, and a bottom portion, a first source/drain region defined in the top portion of the pillar, a transistor channel region defined in the central portion of the pillar, a second source/drain region defined in the bottom portion of the pillar, a dielectric layer formed on and surrounding the central portion of the pillar in alignment with the transistor channel region, a transistor gate surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor, and a spacer layer formed around only the top portion of the pillar and the first source/drain region; N conductive paths formed of the same material as the transistor gates, wherein each conductive path connects the transistor gates along a respective column, and is formed as an extension of the transistor gates along the column; and M×N capacitors, wherein each capacitor is stacked on the top end of the pillar of a respective transistor.