Patent ID: 7631162

Claim:
A memory system for connection to a host processor wherein data is identified by a logical address, the system comprising: a non-volatile memory circuit for storing user and system data, comprising a plurality of physical sectors, each having multiple memory cells, that are individually addressable by a physical address and structured into multi-sector physical blocks that are the physical unit of erase; and a controller circuit that controls accessing of the memory circuit by the host processor for the writing of data structures thereto and reading data structures therefrom, wherein the controller is configured to manage the allocation of physical addresses to logical addresses and the storage of data identified by the logical addresses in the physical areas corresponding to the allocated physical addresses, wherein the controller includes: logic circuitry that adjusts the management method of said logical addresses according to the frequency of updating of the allocation of said logical addresses to said physical addresses, managing the more frequently updated logical addresses according to a second method that is different than a first method by which other ones of the logical addresses are managed, wherein the first method manages logical addresses using logically contiguous multi-block data structures and the second method manages logical addresses on a sector level basis.