Patent ID: 8832393

Claim:
Apparatus for aligning data write and read operations between different buffers, the apparatus comprising: a master logic circuit configured to, based on a control signal, assert a read clock stop signal and generate a write reset enable signal from the read clock stop signal; a plurality of first-in, first-out (FIFO) buffers coupled to the master logic circuit, wherein each of the plurality of FIFO buffers comprises: a local buffer configured to i) accept write data in accordance with a write pointer and a write clock, and ii) provide data based on a read pointer and a read clock, the local buffer placed in a suspended state when the master logic circuit asserts the read clock stop signal, a local logic circuit configured to generate i) a write pointer reset signal based on the read clock stop signal and the write reset enable signal, and ii) a read pointer reset signal based on the presence of the read clock stop signal and a predefined input value, write pointer logic configured to generate and update the write pointer based on the write clock, wherein, based on a presence of the write pointer reset signal, the write pointer logic suspends movement of the write pointer, and read pointer logic configured to generate and update the read pointer based on the read clock, wherein, based on a presence of the read pointer reset signal, the read pointer logic suspends movement of the write pointer; wherein, when the master logic circuit asserts the read clock stop signal, each of the plurality of FIFO buffers suspends movement of each write pointer and each read pointer, and, when the master logic circuit de-asserts the read clock signal, each of the plurality of FIFO buffers enables movement of each write pointer, then the read pointer to align data write and read operations of the plurality of FIFO buffers.