Patent ID: 7429703

Claim:
An integrated circuit device comprising: a die having a top surface with a peripheral region and an interior region surrounded by the peripheral region: a plurality of bond pads disposed in the peripheral region of the die; at least one internal bus, disposed in the interior region of the die, that distributes power to a plurality of internal node points of the die; and at least one bond wire connecting at least one of the plurality of bond pads with the at least one internal bus; wherein the at least one internal bus further comprises at least three separate parallel pairs of internal buses; a first one of the pairs of internal buses being arranged adjacent and parallel to a first side of the peripheral region; a second one of the pairs of internal buses being arranged adjacent and parallel to a second side of the peripheral region opposite the first side of the peripheral region; and a third one of the pairs of internal buses being disposed between and parallel to the first and second pairs.