Patent ID: 7689944

Claim:
A computer-implemented method for improving a design for a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package, the semiconductor chip comprising a power supply pad and a ground pad, the semiconductor package comprising, in addition to the semiconductor chip, a power supply terminal, a ground terminal and electrical paths electrically connecting between the power supply pad and the power supply terminal and between the ground pad and the ground terminal, respectively, the method comprising: receiving design data, the design data including specifications for an adjustment target; calculating a target variable for the adjustment target on the basis of target information about the adjustment target, the target variable being represented in frequency domain, the adjustment target comprising at least the electrical paths; comparing the target variable with a predetermined constraint represented in frequency domain to identify a problematic section of the adjustment target corresponding to a frequency region at which the target variable exceeds the predetermined constraint; and deciding design guidelines, for use with the design data, to solve the identified problematic section of the adjustment target, wherein the above steps are performed by one or more computers programmed to perform the above steps.