Patent ID: 7205627

Claim:
A semiconductor structure, comprising: (a) a semiconductor substrate; (b) a charge collection well on the substrate, the charge collection well comprising a first semiconductor material doped with a first doping polarity; (c) a surface pinning layer on and in direct physical contact with the charge collection well, the surface pinning layer comprising a second semiconductor material doped with a second doping polarity opposite to the first doping polarity; and (d) an electrically conductive push electrode being in direct physical contact with the surface pinning layer but not being in direct physical contact with the charge collection well, wherein in response to the surface pinning layer and the charge collection well being in a path of light, the charge collection well is adapted for accumulating charges, wherein a P-N junction between the surface pinning layer and the charge collection well is adapted for becoming reverse-biased in response to the electrically conductive push electrode being at a charge pushing potential, wherein the charge pushing potential is lower than a potential of the substrate if the first doping polarity is an N-type, and wherein the charge pushing potential is higher than the potential of the substrate if the first doping polarity is a P-type; and (e) a transfer transistor on the semiconductor substrate, wherein the transfer transistor includes (i) a first source/drain region, (ii) a second source/drain region, and (iii) a channel region being disposed between and in direct physical contact with the first and second source/drain regions, wherein the first and second source/drain regions comprise dopants of the first doping polarity, wherein the first source/drain region is in direct physical contact with the charge collection well, and wherein the channel region comprises dopants of the second doping polarity.