Patent ID: 8212830

Claim:
An image converting apparatus comprising: a first frame memory, which holds an image rendered through an image rendering process performed by a graphics processor at a given vertical synchronous frequency; an image converter, which performs an image conversion process on the image held in the first frame memory into an image compatible with the specification of a display; a second frame memory, which holds the image converted by the image converter by switching a plurality of frame buffers, one of the frame buffers being selected in accordance with a vertical synchronous frequency of the display to scan out the image; and a switch instruction issuing unit, which issues a frame buffer switch instruction for designating a frame buffer to scan out from subsequently, in synchronization with the vertical synchronous frequency of the display, instead of immediately after the execution of an image converting process by the image converter, the timing of the switch instruction based on the timing of the vertical synchronous frequency of the display so as to be disassociated from the timing of the image rendering process and the timing of image conversion process, wherein the image converter converts the frame rate of the image rendered by the graphics processor to be compatible with the specification of the display, by synthesizing two images held in the first frame memory with a coefficient for synthesis based on a time difference between an assumed vertical synchronizing signal for the graphics processor expected to follow the completion of an image converting process applied to the image rendered by the graphics processor, and a vertical synchronizing signal for the display occurring immediately after the assumed vertical synchronizing signal.