Patent ID: 7026668

Claim:
A high-breakdown-voltage semiconductor device comprising: a high-resistance semiconductor layer of a first conductivity type having a first main surface and a second main surface, a plurality of first trenches being formed on the first main surface of the high-resistance semiconductor layer in a longitudinal plane shape and in parallel with each other and second trenches being formed so as to communicate with the plurality of first trenches at both ends of longitudinal sides thereof; a plurality of first semiconductor regions of the first conductivity type formed on the first main surface of the high-resistance semiconductor layer, each of the plurality of first semiconductor regions being surrounded by adjacent trenches of the plurality of first trenches and the second trenches, and having an impurity concentration higher than that of the high-resistance semiconductor layer; a second semiconductor region of a second conductivity type continuously disposed in a sidewall and a bottom portion of each of the plurality of first trenches; a sidewall insulating film disposed on the second semiconductor region of the sidewall of each of the plurality of first trenches; a third semiconductor region of the second conductivity type disposed in a surface region of the second semiconductor region of the bottom portion of each of the plurality of first trenches and having an impurity concentration higher than that of the second semiconductor region; a fourth semiconductor region disposed on the second main surface of the high-resistance semiconductor layer, and having an impurity concentration higher than that of the high-resistance semiconductor layer; a first electrode formed on each of the plurality of first semiconductor regions so as to cover entire upper surfaces thereof sandwiched between adjacent trenches of the plurality of first trenches; a second electrode filling each of the plurality of first trenches and in contact with the third semiconductor region; and a third electrode formed on the fourth semiconductor region.