Patent ID: 6871155

Claim:
A sensing circuit for sensing the logic data stored in a memory cell, the memory cell being electrically connected to a bit line, the sensing circuit comprising: a first pre-charging module, electrically connected to the bit line, for pre-charging the bit line; a selecting module, electrically connected to the bit line and a first data line, for transmitting signals of the bit line to the first data line according to a first controlling signal and isolating the capacitance of the bit line and the first data line; a second pre-charging module, electrically connected to the first data line, for pre-charging the first data line; a first voltage keeping module, electrically connected to the first data line, for maintaining the signal on the first data line at a high voltage level when a logic value “1” is stored in the memory cell; an isolating module, electrically connected between the first data line and a second data line, for transmitting signals from the first data line to the second data line according to a second controlling signal and isolating the capacitance of the first data line and the second data line; and a third pre-charging module, electrically connected to the second data line, for pre-charging the second data line.