Patent ID: 8823398

Claim:
A method for making a differential capacitive transducer system capable of sensing a physical quantity, the method comprising: obtaining a first capacitive core for generating a first core output based on the physical quantity, the first capacitive core including a first variable capacitor, a second variable capacitor, a first core input coupled to the first variable capacitor, a second core input coupled to the second variable capacitor, and a first core output coupled to a first common node between the first variable capacitor and the second variable capacitor; obtaining a second capacitive core for generating a second core output based on the physical quantity, the second capacitive core including a third variable capacitor, a fourth variable capacitor, a third core input coupled to the third variable capacitor, a fourth core input coupled to the fourth variable capacitor, and a second core output coupled to a second common node between the third variable capacitor and the fourth variable capacitor; switchably coupling a single differential amplifier to the first and second common nodes for receiving the first and second core outputs, the differential amplifier having a pair of differential inputs and a pair of differential outputs, the differential outputs providing the transducer output; switchably coupling the transducer output to the first and second common nodes of the first and second capacitive cores; controlling the opening and closing of switches coupling components of the differential capacitive transducer system using a main clock having a first phase and a second phase; wherein when the main clock is in the first phase, coupling the first core input of the first capacitive core to a positive reference voltage, coupling the second core input of the first capacitive core to a negative reference voltage, the negative reference voltage having substantially the same magnitude and opposite polarity as the positive reference voltage; coupling the first common node of the first capacitive core to the transducer output, coupling the third core input of the second capacitive core to the positive reference voltage, coupling the fourth core input of the second capacitive core to the negative reference voltage, and coupling the second common node of the second capacitive core to the transducer output; and when the main clock is in the second phase, coupling the first, second, third and fourth core inputs of the first and second capacitive cores to a common mode voltage, and coupling the common nodes of the first and second capacitive cores to the differential inputs of the differential amplifier.