Patent ID: 8138832

Claim:
An amplifier, comprising: at least a block, each block comprising: an input circuit receiving a digital input and converting the digital input to a differential pair of a positive input signal and a negative input signal; an integrator having two differential receiving nodes, two differential feedback nodes and two differential output nodes; the two differential receiving nodes coupled to the input circuit respectively receiving the positive input signal and the negative input signal; the two differential feedback nodes respectively receiving a positive feedback signal and a negative feedback signal; wherein the integrator provides a positive error signal according to the positive input signal and the negative feedback signal, and provides a negative error signal according to the negative input signal and the positive feedback signal, and outputs the positive error signal and the negative error signal to the two differential output nodes; a comparator, coupled to the two differential output nodes of the integrator, comparing magnitudes of the positive error signal and the negative error signal and generating a corresponding comparison signal; a driving circuit coupled to the comparator; the driving circuit generating a driving output signal to a driving output node according to the comparison signal; and two feedback circuits, each of the feedback circuits having a node coupled to the driving output node and another node coupled to one of the differential feedback nodes; the two feedback circuits respectively providing the positive feedback signal and the negative feedback signal according to the driving output signal.