Patent ID: 7759977

Claim:
A buffering circuit, which is operated between a first supply voltage and a second supply voltage, comprising: a first field effect transistor, comprising a gate terminal coupled to an input signal, for buffering the input signal to generate an output signal under an operating current; a second field effect transistor, cascoded with the first field effect transistor, for generating the operating current for the first field effect transistor according to a control signal at a gate terminal of the second field effect transistor; and a control circuit, comprising a first terminal coupled to the gate terminal of the first field effect transistor and a second terminal coupled to a reference source, the control circuit for adjusting the control signal according to the input signal and the reference source, wherein when a voltage level of the input signal varies, the control circuit is arranged to adjust a voltage level of the control signal such that the adjusted voltage level of the control signal varies inversely proportional to the varied voltage level of the input signal, the control circuit further comprises: a third field effect transistor, comprising a gate terminal coupled to the gate terminal of the first field effect transistor, and a drain terminal coupled to the reference source; and a fourth field effect transistor, comprising a drain terminal coupled to a source terminal of the third field effect transistor, a source terminal coupled to the second supply voltage, and a gate terminal coupled to the reference source and the gate terminal of the second field effect transistor.