Patent ID: 7702822

Claim:
A process for operating a system module configured to be connected with a bus, comprising: generating allocated check bits based on a data record; emitting the data record and the allocated check bits if operating the system module in a first operating mode, wherein the first operating mode comprises a normal operating mode, and wherein a data error can be detected by the system module based on the emitted data record and the allocated check bits; transforming the allocated check bits into transformed check bits according to a predetermined algorithm, the predetermined algorithm comprising inverting the allocated check bits, if operating the system module in a second operating mode; and emitting the data record and the transformed check bits if operating the system module in the second operating mode, wherein the bus comprises a Local Interconnect Network Bus, the second operating mode further comprises a programming mode, the programming mode comprising writing to a program memory in the system module from the bus, a data error can be detected by the system module based on the transformed check bits in the second operating mode, and the system module comprises a micro-processor or a micro-controller.