Patent ID: 7849430

Claim:
A method for generating a reverse donut model (RDM) for an IC chip (IC) with a computer-aided design tool (CAD tool) for running a timing analysis, the method comprising: flattening a design model of the IC, the flattening of the design model reducing a hierarchical model of the IC to a single level flat model, the design model of the IC including a plurality of circuit elements arranged in a plurality of blocks and sub-blocks; identifying a block from the plurality of blocks in the single level flat model of the IC; and generating the RDM for the identified block, the generated RDM including connectivity information associated with an outer boundary of the identified block and at least one layer of interface connection between the outer boundary of the identified block and at least one external circuit element of the IC interfacing with the outer boundary of the identified block, the generated RDM preserving essential performance characteristics of the identified block and acting as a blackbox for the identified block, the generated RDM used in place of the identified block for running the timing analysis, wherein the generating of the RDM further includes pruning the single level flat model of the IC, and wherein the method operations are performed using a processor.