Patent ID: 8032709

Claim:
A processor in a multi-processor environment having a storage controller (SC) and multiple processing units having cache memory involving various ownership states as to a cache line, which states include a read-only or shared state and an exclusive state for holding the cache line exclusively, for ensuring forward progress in shared cache line usages, the processor comprising: a cross interrogate (XI)-reject counter; and a mechanism for performing a method comprising: setting a XI-rejected state when an exclusive XI is rejected by the processor; resetting the XI-rejected state when the exclusive XI is acknowledged; incrementing the XI-reject counter when an instruction is completed while the XI-rejected state is active, and resetting the XI-rejected state afterwards; setting a XI-threshold-stall state if the XI-reject counter hit a preset threshold value; resetting the XI-threshold-stall state and XI-reject counter if the exclusive XI is acknowledged; and blocking further instruction issue and prefetching attempts to obtain and hold the cache line exclusively when the XI-threshold-stall state is active.