Patent ID: 7158560

Claim:
For use in a CDMA receiver, a noise reduction circuit for improving a signal-to-noise ratio of a received signal comprising a predetermined sequence of chips, each of said chips having a value corresponding to Logic 0 or Logic 1, said noise reduction circuit comprising: a sampling circuit capable of generating a first sequence of samples from said received signal; and a controller capable of identifying samples in said first sequence of samples corresponding to Logic 0 chips and identifying samples in said first sequence of samples corresponding to Logic 1 chips, wherein said controller is further capable of generating a second sequence of samples by at least one of: shifting positions within said first sequence of samples of at least some of said identified samples corresponding to Logic 0 chips, wherein each of said shifted samples corresponding to Logic 0 chips is shifted from a first position corresponding to a Logic 0 chip to a second position corresponding to a Logic 0 chip; and shifting positions within said first sequence of samples of at least some of said identified samples corresponding to Logic 1 chips, wherein each of said shifted samples corresponding to Logic 1 chips is shifted from a first position corresponding to a Logic 1 chip to a second position corresponding to a Logic 1 chip.