Patent ID: 7131044

Claim:
A scan circuit comprising: A. a functional circuit formed on the semiconductor substrate of an integrated circuit, the functional circuit including logic circuits to be tested; B. a scan path circuit on the integrated circuit formed of serially connected scan cells, the scan path circuit having leads connected to the logic circuits to carry stimulus signals to the logic circuits and to receive response signals from the logic circuits, the scan path circuit having a serial data input lead coupled to a test data input terminal of the integrated circuit and a serial data output lead coupled to a test data output terminal of the integrated circuit, the scan path circuit having control input leads for receiving control signals to control operation of the scan path circuit, the scan path circuit being organized in selectable, separate scan path parts, each scan path part having a serial input connected to the serial data input lead, a serial output lead selectively coupled to the serial data output lead and a separate set of control input leads; C. scan control interface means on the integrated circuit having control input leads coupled to test control input terminals on the integrated circuit and a separate set of control output leads for each scan path part, each set of control output leads being coupled to a respective one of the separate sets of control input leads of the scan path parts, the scan control interface means for, in response to signal inputs on said control input leads, outputting control on said separate set of control output leads such that: i. the scan path parts are operated sequentially to input stimulus data from the test data input terminal and to output response data to the test data output terminal; and ii. the scan path parts are operated simultaneously to capture response data from the functional circuit.