Patent ID: 8062936

Claim:
A method of fabricating an array substrate for a display device, comprising: forming a gate line and a gate electrode on a substrate, where a pixel region including switching region is defined; forming a gate insulating layer and an intrinsic amorphous silicon layer on the gate line and a gate electrode; forming an oxide semiconductor layer on the intrinsic amorphous silicon layer; increasing a conductive property of the oxide semiconductor layer such that the oxide semiconductor layer has an ohmic property; forming a metal layer on the oxide semiconductor layer having the ohmic property; forming first and second photoresist patterns on the metal layer, the first photoresist pattern having a first thickness, the second photoresist pattern having a second thickness thinner than the first thickness; forming a data line, a source drain pattern, an oxide semiconductor pattern and an active layer by patterning the metal layer, the oxide semiconductor layer and the intrinsic amorphous silicon layer using the first and second photoresist patterns as an etching mask, wherein the active layer is disposed over the gate electrode in the switching region, the oxide semiconductor pattern is disposed on the active layer, the data line crosses the gate line to define the pixel region, and the source drain pattern is connected to the data line and disposed on the oxide semiconductor pattern; removing the second photoresist pattern and exposing the source drain pattern; wet-etching the source drain pattern exposed by removing the second photoresist pattern using a first etchant, thereby forming source and drain electrodes and exposing the oxide semiconductor pattern; wet-etching the oxide semiconductor pattern exposed by wet-etching the source and drain pattern using a second etchant, thereby forming ohmic contact layers and exposing the active layer; removing the first photoresist pattern and exposing the source and drain electrodes; forming a passivation layer on the source and drain electrodes exposed by removing the first photoresist pattern and the active layer exposed by wet-etching the oxide semiconductor pattern, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole, wherein the active layer has a uniform thickness in the switching region.