Patent ID: 7280628

Claim:
A data communication system, comprising: a first integrated circuit; and a second integrated circuit coupled for source synchronous communication with the first integrated circuit; the second integrated circuit including a recapture circuit, the recapture circuit configured to perform internally timed transfers of data, the data obtainable from the first integrated circuit in association with a source clock domain, the internally timed transfers of the data being from the source clock domain into an internal clock domain of the second integrated circuit; wherein the internally timed transfers of data are responsive to a timing signal of the source clock domain from the first integrated circuit and an internal clock signal of the internal clock domain of the second integrated circuit wherein the recapture circuit comprises: a first data registration stage configured to capture the data in the source clock domain; a data valid signal generator configured to provide a valid data signal responsive to the internal clock signal and a derived signal from the timing signal; and a second data registration stage configured to recapture the data in the internal clock domain responsive to the data valid signal and the internal clock signal wherein the derived signal is provided by dividing frequency of the timing signal.