Patent ID: 7420565

Claim:
A computer system comprising: a central processing unit; an integrated graphics subsystem adapted to generate display data in response to a set of rendering information; a graphics connector adapted to communicate with an auxiliary graphics subsystem; a core logic controller adapted to coordinate communications between the central processing unit, the integrated graphics subsystem, and the graphics connector; and a data communications bus controlled by the core logic controller, the data communications bus including: a first bus connection coupled to provide a bidirectional communication path between the core logic controller and the integrated graphics subsystem; a second bus connection coupled to provide a bidirectional communication path between the core logic controller and the graphics connector; and a third bus connection coupled to provide a bidirectional communication path between the integrated graphics subsystem and the graphics connector, wherein the integrated graphics subsystem includes: a normal operation mode adapted to receive a first portion of a set of rendering information from the core logic controller via the first bus connection, to receive a second portion of the set of rendering information from the core logic controller via a data path that includes the third bus connection and the second bus connection; and a data forwarding mode adapted to forward a first portion of a set of rendering information received via the first bus connection to the graphics connector via the third bus connection.