Patent ID: 7861147

Claim:
An add-compare-select (ACS) unit, generating first path metrics having a first bit-pair and a most significant bit-pair (MSB), wherein each bit-pair is in redundant number representation having a high bit and a low bit, the ACS unit comprising: a first ACS circuit producing the first bit-pair of the first path metrics and a first carry; a limiting circuit coupled to the first ACS circuit, generating the MSB of the first path metrics based on the first carry, and limiting the MSB of the first path metrics to a first predetermined value; an MSB maximum select (MS) unit coupled to the limiting circuit and another ACS unit, receiving an MSB of second path metrics from the other ACS unit, and comparing the MSBs of the first and the second path metrics to determine MSB decision signals based on maximum likelihood selection; an MSB storage unit coupled to the MSB maximum select unit, storing the MSB of the first path metrics as an MSB of a previous first path metric; and a reset unit coupled to the MSB maximum select unit and the MSB storage unit, resetting the MSB of the first path metrics to a second predetermined value when the high bits of the MSBs of the first and the second path metrics reach the first predetermined value.