Patent ID: 6897700

Claim:
A DC offset cancellation architecture for an amplifier circuit, said DC offset cancellation architecture comprising: an amplifier arrangement configured to receive an input data signal and to amplify said input data signal into an output data signal, said amplifier arrangement including a positive output node and a negative output node and incorporating a digitally-controlled DC offset cancellation structure; a receiver component connected to said amplifier arrangement and configured to process a receiver input signal based on said output signal and to generate a receiver output signal in response to said receiver input signal; an error monitor connected to said receiver component and configured to measure an error metric associated with said receiver output signal; a digital control component connected to said error monitor and to said amplifier arrangement, said digital control component being configured to generate a digital control signal in response to said error metric; and the DC offset cancellation structure including: a first transistor for generating a positive component of a DC offset cancellation voltage, said first transistor having a control signal node and a first current input node connected to said positive output node; a second transistor for generating a negative component of said DC offset cancellation voltage, said second transistor having a control signal node and a second current input node connected to said negative output node; and a bias current architecture connected to said control signal node of said first transistor and to said control signal node of said second transistor, said bias current architecture being configured to set said positive component of said DC offset cancellation voltage and said negative component of said DC offset cancellation voltage in response to an analog DC offset control signal; and a digital-to-analog converter (“DAC”) configured to receive said digital control signal and to convert said digital control signal into said analog DC offset control signal utilized by said DC offset cancellation structure.