Patent ID: 7501900

Claim:
A circuit, comprising: a phase-locked loop circuit forming a negative feedback loop, the phase-locked loop circuit comprising a phase frequency detector to receive a reference signal and a feedback signal, the feedback signal comprising a feedback phase; and loop bandwidth calibration logic to measure a bandwidth of the negative feedback loop and to modify the feedback phase, the loop bandwidth calibration logic comprising: adjust logic to adjust a phase of a signal entering the phase frequency detector; phase overshoot detection logic coupled to detect a change in a voltage pulse sent by the phase frequency detector after the phase has been adjusted, wherein the voltage pulse change indicates that the phase-locked loop circuit has left a recovery stage and entered an overshoot stage; a counter coupled to an adjustable clock, the counter to increment at each cycle of the clock, wherein the counter is reset when the adjust logic adjusts the phase of the signal entering the phase frequency detector; and an inverter to receive the feedback phase and generate an adjust phase, wherein the adjust phase is shifted relative to the feedback phase by 180 degrees; wherein the loop bandwidth calibration logic measures a closed loop bandwidth of the phase-locked loop circuit based on a time difference between when the adjust logic adjusts the phase and the phase overshoot detection logic detects the voltage pulse change.