Patent ID: 7990208

Claim:
A semiconductor integrated circuit device comprising: a first power line whose potential is a first potential; a second power line whose potential is a second potential lower than the first potential; a third power line whose potential is a third potential lower than the second potential; a first MOS transistor connected between the second power line and the third power line; a circuit block connected between the first power line and the second power line; and a drive control circuit comprising a first drive circuit and a second drive circuit, wherein the drive control circuit controls a voltage supplied to a gate of the first MOS transistor, wherein the first MOS transistor is off in a standby state, wherein the first MOS transistor is on in a operation state; wherein during a shift from the standby state to the operation state, the drive control circuit changes the voltage supplied to the gate of the first MOS transistor at a first rate, and then, changes the voltage supplied to the gate of the first MOS transistor at a second rate faster than the first rate, wherein a driving performance of the first drive circuit is smaller than the driving performance of the second drive circuit, wherein an output of the first drive circuit and an output of the second drive circuit are commonly connected to the gate of the first MOS transistor, and wherein the first MOS transistor is a NMOS transistor.