Patent ID: 7780862

Claim:
A method for multi-chamber plasma etching to form high-k dielectric flash memory devices on a wafer, the method comprising: a) etching an upper conductive material layer in a first plasma chamber with a cathode temperature below about 100 degrees Celsius to define a control gate; b) transferring the wafer from the first plasma chamber to a hot cathode chamber without breaking vacuum; c) etching a high-k dielectric layer with a plasma using a BCl 3 and hydrocarbon passivation gas in the hot cathode chamber with a temperature in a range from about 100 degrees Celsius and to about 300 degrees Celsius so as to allow up to 700% overetch of the high-k dielectric layer in the hot cathode chamber; d) transferring the wafer from the hot cathode chamber to the first plasma chamber without breaking vacuum; and e) etching a lower polysilicon layer in the first plasma chamber with a cathode temperature below about 100 degrees Celsius to define a floating gate electrode.