Patent ID: 7567629

Claim:
A digital clock recovery system operating with multiple mutually phase shifted clock signals defining a set of clock phases, said clock recovery system comprising: a set of individual transition detectors for processing an input data sample representation obtained by sampling an input data signal with said multiple mutually phase shifted clock signals, each transition detector being adapted for determining whether input data samples within a detection window associated with a respective one of said clock phases includes an input data transition; a set of clock selection controllers, each of which is connected to a respective one of said transition detectors, associated with a unique clock phase and adapted for: requesting clock master control only if an input data transition is detected by the associated transition detector; continuously monitoring whether any of a predetermined group of said cluck selection controllers requests clock master control, and releasing possible clock master control by the monitoring clock selection controller if such a request is detected; and acquiring clock master control only when no clock selection controller is in clock master control; and means for dynamically extracting, from said phase shifted clock signals, a clock signal that has a clock phase associated with the clock selection controller currently in clock master control as an output clock signal.