Patent ID: 8180968

Claim:
A method for reducing cache flush time of a cache connected to a main memory of a computer system by a system interconnect, comprising: setting a capacity of a dirty line directory (DLD) residing on a first side of the system interconnect, wherein the capacity defines a maximum number of directory entries in the DLD, and wherein the DLD stores only directory entries corresponding to dirty lines in the cache, wherein the main memory resides on the first side of the system interconnect, and wherein the cache resides on a second side of the system interconnect; identifying a first modification to the cache; populating, in response to the first modification, a directory entry of a plurality of directory entries in the DLD, wherein the directory entry comprises an address field and a processor field, and wherein the DLD is populated to the capacity after populating the directory entry; identifying a second modification to the cache after the DLD is populated to the capacity; de-populating a pre-determined number of the plurality of directory entries in response to identifying the second modification and the DLD being populated to the capacity; and sending, by the DLD and in response to de-populating the pre-determined number of the plurality of directory entries, a snoop request to the cache over the system interconnect to initiate a write-back from the cache to the main memory.