Patent ID: 8470705

Claim:
A method of forming a chip pad of an integrated circuit, the method comprising: patterning a plurality of interconnect metal layers to form a plurality of stacked metal features and surrounding metal rings, the metal rings being isolated from the metal features within each respective interconnect metal layer, but being coupled to one or more metal traces connected to the gate electrodes of one or more MOS transistors; forming main stacking vias coupling the stacked metal features together to form a main pad portion; forming ring stacking vias coupling the stacked metal rings together to form a ring pad portion; and after the patterning and the forming the main and ring stacking vias, forming a pad bonding surface and one or more bridges in an upper conductive layer, the pad bonding surface being separated from the one or more bridges, wherein the one or more bridges couple the ring pad portion to the main pad portion.