Patent ID: 8453083

Claim:
A computer-implemented method of modifying integrated circuit (IC) designs, the method comprising: automatically receiving a reference IC design, a retimed IC design, and a plurality of logical relationships in a memory of a computer; wherein said plurality of logical relationships comprise at least one logical relationship indicative of at least one combinational logic cell across which movement of at least a first specific instance of a sequential cell in the reference IC design results in at least a second specific instance of said sequential cell in the retimed IC design; automatically transforming the reference IC design into a transformed reference design without retiming at least by adding therein a white box comprising the combinational logic cell indicated in said logical relationship and a black box defined to be functionally inverse of the white box; and at least said computer automatically transforming the retimed IC design into a transformed retimed design in said memory, by adding therein said white box and said black box in a second arrangement relative to one another in an order of flow of signals from the white box's output to the black box's input opposite to a first arrangement of said white box and said black box in the transformed reference design; and automatically supplying the transformed reference design and the transformed retimed design to a combinational equivalence checker.