Patent ID: 8481387

Claim:
A method of manufacturing a semiconductor device, comprising: forming isolation layer patterns on a substrate, each of the isolation layer patterns having a lower portion buried in the substrate and an upper portion protruding from the substrate; forming an insulation structure on a portion of the substrate between the isolation layer patterns, the insulation structure comprising at least one oxide layer formed by at least one oxidation process and at least one nitride layer formed by at least one nitration process; forming a floating gate on the insulation structure; forming a dielectric layer on the floating gate; and forming a control gate on the dielectric layer, wherein forming the insulation structure includes, performing a first oxidation process to form a first preliminary oxide layer on the substrate by partially oxidizing the substrate; performing a first nitration process to form a preliminary nitride layer on the substrate by changing a lower portion of the preliminary oxide layer, and a second preliminary oxide layer from the first preliminary oxide layer on the preliminary nitride layer; and performing a second oxidation process to form a lower nitride layer from the preliminary nitride layer on the substrate, a lower oxide layer from the second preliminary oxide layer on the lower nitride layer, and a first upper oxide layer from the second preliminary oxide layer on the lower oxide layer.