Patent ID: 8615542

Claim:
A digital circuit configured as an arithmetic pipeline, said circuit comprising: a two input adder module, said module being controllable to add a first single precision floating point number to a second single precision floating point number and to output a resulting single precision floating point number, said module comprising: means for inputting mantissa portions of the first and second single precision floating point numbers, said mantissa inputting means determining a larger number and a smaller number, and outputting a mantissa portion of the larger number and a mantissa portion of the smaller number; means for inputting exponent portions of the first and second floating point numbers, said exponent portions inputting means determining and outputting a larger exponent; means for inputting sign-bits of the first and second floating point numbers, said sign-bits inputting means determining and outputting a sign-bit for said resulting floating point number; carry-in generation means for outputting carry-in data based on sign-bits of the first and second floating point numbers and the mantissa portion of the smaller number; addition logic receiving the carry-in data, mantissa of the larger number, mantissa of the smaller number, and a difference between the larger and smaller exponents, said addition logic shifting the mantissa of the smaller number to align with the mantissa of the larger number, calculating and outputting a normalized mantissa output and exponent modifier; and output logic receiving the sign-bit result, the normalized mantissa output and the exponent modifier, said output logic outputting the resulting single precision floating point number based on the normalized mantissa output and exponent modifier, wherein when the sign-bit of the first floating point number is different from the sign-bit of the second floating point number, the exponent portion of the first floating point number is different from the exponent portion of the second floating point number, and the mantissa portion of the smaller number has been rounded toward zero, the carry-in data is set to cause the rounded mantissa portion of the smaller number to be added to the two's complement of the mantissa portion of the larger number, wherein when the sign-bit of the first floating point number is different from the sign-bit of the second floating point number and the exponent portion of the first floating point number is the same as the exponent portion of the second floating point number, the carry-in data is set to cause the rounded mantissa portion of the smaller number to be added to the inverse of the mantissa portion of the larger number, and wherein when the sign-bit of the first floating point number is the same as the sign-bit of the second floating point number, the carry-in data is set to cause the rounded mantissa portion of the smaller number to be added to the mantissa portion of the larger number.