Patent ID: 8738979

Claim:
An integrated circuit comprising: a functional block of circuitry operable to generate internal operational signals for performing designated functions, the block of circuitry comprising a test clock operable to generate clock signals; a test signal selection hierarchy coupled with the block of circuitry, the test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals towards a testing element; a control unit operable to receive the clock signals from the test signal selection hierarchy, operable to determine a delay between received clock signals routed via the different signaling pathways of the test signal selection hierarchy, and operable to associate each of the received clock signals with one or more of the internal operational signals; and a delay line operable to receive one or more of the internal operational signals from the test signal selection hierarchy and to delay application of a subset of the received internal operational signals to the testing element by a programmed delay amount, the control unit further operable to program the delay line based upon the delay between the clock signals and based upon the subset of the received internal operational signals.