Patent ID: 8895992

Claim:
A semiconductor structure comprising: a first III-V compound layer; a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer; a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature, wherein a fluorine region is embedded in the second III-V compound layer under the gate electrode; a third III-V compound layer disposed over the second III-V compound layer, wherein a diffusion barrier layer is located between the second III-V compound layer and the third III-V compound layer; and a gate dielectric layer disposed over portions of the second III-V compound layer and over an entire top surface of the third III-V compound layer.