Patent ID: 8133783

Claim:
A method to form an integrated circuit, the method comprising: forming a first portion of an active device wherein the active device is a higher voltage higher frequency non-symmetrical analog transistor and comprises a plurality of doped regions in a semiconductor material; forming a first portion of a lower voltage digital CMOS device; forming a first portion of a passive device; forming a first portion of a memory device; and forming a dielectric structure; wherein the first portion of the active device, the first portion of the lower voltage digital CMOS device, the first portion of the passive device, or the first portion of the memory device, or combinations thereof, are formed simultaneously or nearly simultaneously; wherein the higher frequency of the active device is based at least in part on a relatively shorter channel length of the active device, wherein the channel length of the active device is a function of a deposition thickness of a gate material of the active device; wherein the dielectric structure extends from a surface of the semiconductor material to a distance below all of the doped regions of the plurality of doped regions of the active device; wherein the memory device has a doped region; wherein the dielectric structure is between the plurality of doped regions of the active device and the doped region of the memory device and the dielectric structure surrounds the plurality of doped regions of the active device; and wherein at least a portion of the passive device is disposed over the dielectric structure.