Patent ID: 7723796

Claim:
A semiconductor device, comprising: a semiconductor substrate; a first ring-shape gate formed on a surface of the semiconductor substrate; a second ring-shape gate formed on the surface of the semiconductor substrate; a first diffusion layer formed in the semiconductor substrate around the first ring-shape gate and the second ring-shape gate; a second diffusion layer formed in the semiconductor substrate inside the first ring-shape gate; a third diffusion layer formed in the semiconductor substrate inside the second ring-shape gate; an interconnect line electrically connecting the first ring-shape gate and the second ring-shape gate to a same potential; and an STI area formed in the semiconductor substrate around the first diffusion layer, wherein a first transistor corresponding to the first ring-shape gate and a second transistor corresponding to the second ring-shape gate; a third transistor having an end of a channel thereof coupled to a drain of the first transistor; a fourth transistor having an end of a channel thereof coupled to a drain of the second transistor; a fifth transistor connected both to another end of the channel of the third transistor and to another end of the channel of the fourth transistor; and gates of dummy transistors that do not function as transistors, the gates being situated between the STI area and the first and second ring-shape gates, and being arranged both in a first direction parallel to the surface of the semiconductor substrate and in a second direction parallel to the surface and substantially perpendicular to the first direction, wherein the dummy transistors have a drain and a source thereof connected to a same potential.