Patent ID: 8102997

Claim:
A processor for performing a plurality of rounds of ciphering or deciphering of an initial state matrix formed of a plurality of bytes of data to obtain a resulting matrix of a same size as the initial state matrix, each round using a matrix of bytes of ciphering or deciphering keys, the processor comprising: a first input register configured to contain a column of round input data bytes; an output register configured to contain a column of transformed round output data bytes or a column of intermediary data bytes; a second input register configured to contain either a column of key bytes, or the column of intermediary data bytes of the output register; a substitution element based on a substitution box table loaded into a memory, said substitution element configured to receive individual round input data bytes selected from the first register and to provide, for each individual round input data byte, a column of substituted bytes; a controllable permutation element configured to perform circular permutation of the column of substituted bytes provided by the substitution element, providing a permuted byte column; and an XOR element configured to perform XOR bit-to-bit combination of the permuted byte column provided by the permutation element with the content of the second register, resulting in the column of intermediary data bytes or transformed round output data bytes that is loaded into the output register.