Patent ID: 7912172

Claim:
A programmable divider apparatus receiving an input signal to execute a frequency division operation for the input signal, the programmable divider apparatus comprises: a first divider providing a frequency division operation of division by at least three predetermined integers; a second divider providing a frequency division operation of division by two integers m and n, and cascading to the first divider; a feedback control unit coupled to between an output of the second divider and an input of the first divider; and a plurality of control signals comprising: a first selection control signal controlling the first divider to execute a frequency division operation of division by a specific integer in the at least three predetermined integers; a second selection control signal controlling the second divider to execute a frequency division operation of division by m and n; and at least a feedback control signal controlling the feedback control unit to provide the output or inverted output of the second divider to the input of the first divider, or to provide a logic 1 or logic 0 level.