Patent ID: 7135398

Claim:
The method for forming an interconnect structure on a substrate, the method comprising the steps of: depositing a first dielectric layer on the substrate; depositing a first hardmask layer on said first dielectric layer; forming at least one via opening in said first dielectric layer and said first hardmask layer; filling said via opening with a conductive material, thereby forming at least one conductive via embedded in said first dielectric layer and said first hardmask layer; depositing a via-level cap layer on said first hardmask layer; depositing a second dielectric layer on said via-level cap layer, wherein said second dielectric layer is formed of a material different from said first dielectric layer; depositing a second hardmask layer on said second dielectric layer, said second hardmask layer having a top surface; forming at least one trench opening in said via-level cap layer, said second dielectric layer and said hardmask layer, wherein said trench opening overlies said first conductive via; and filling said trench opening with a conductive material, thereby forming at least one conductive line embedded in said via-level cap layer, said second dielectric layer and said second hardmask layer, said conductive line having a top surface co-planar with the top surface of said second hardmask layer, wherein said via-level cap layer is formed of SiCNH.