Patent ID: 7091751

Claim:
A CDS (correlated double sampling) comparator, comprising: a first switch that inputs a reference signal to a first node in response to a first switch control signal; a first capacitor connected between the first node and a second node; an inverter having an input terminal connected to the second node and an output terminal connected to a third node, wherein the inverter comprises a plurality of elements connected in series between a first source voltage and a second source voltage to invert an input signal applied to the input terminal of the inverter and output an inverted signal to the output terminal of the inverter, wherein the plurality of elements include a first PMOSFET connected to the first source voltage and a first NMOSFET connected to the second source voltage, wherein the input terminal of the inverter is connected to a gate of the first PMOSFET and a gate of the NMOSFET, and wherein the plurality of elements further include a plurality of elements connected in series between the first PMOSFET and the first NMOSFET; a second switch connected between the second node and the third node, wherein the second switch is activated by a second switch control signal to short circuit the second and third nodes, a third switch that inputs a ramp signal to a fourth node, in response to a third switch control signal; and a second capacitor connected between the first and fourth nodes.