Patent ID: 8217824

Claim:
A clock generation circuit comprising: a clock input, two output terminals, two flip-flops, four logic NOR gates, two logic AND gates, and an inverter; the first flip-flop is connected with its inverting output back to the input of both the first and the second flip-flop; a non-inverting output of the first flip-flop being connected to the first input of the first NOR gate and the clock input being connected to the second input of the NOR gate; an output of the first NOR gate being connected to the first input of the second NOR gate; an inverting output of the second flip flop being connected to the first input of the first AND gate; a clock input being connected to the second input of the first AND gate; an output of the AND gate being connected to the second input of the second NOR gate; a non-inverting output of the second flip-flop being connected to the first input of the second AND gate and a clock input being connected to the second input of the second AND gate; an output of the second AND gate being connected to the second input of the fourth NOR gate; an inverting output of the first flip-flop being connected to the first input of the third NOR gate; the clock input being connected to the second input of the third NOR gate; an output of the third NOR gate being connected to the first input of the fourth NOR gate; a clock input being connected to the clock input of the first flip-flop and to the input of the inverter; an output of the inverter being connected to the clock input of the second flip-flop; and an output of the second NOR gate being connected to the first output terminal and the output of the fourth NOR gate being connected to the second output terminal.