Patent ID: 6877090

Claim:
A branch predictor for a multi-processing computer, able to execute multiple processes, each process having a designated process reference, comprising: a global history register for storing a branch history of previous sequential branch instructions for a plurality of the multiple processes; a hash logic for creating an index from a combination of a process reference of a process corresponding to a current branch instruction, an address of the current branch instruction, and the branch history for the plurality of the multiple processes; a branch prediction table for storing branch prediction reference data, and for outputting branch prediction reference data corresponding to the index created by the hash logic; an address selection circuit for selecting one of a target address known from the current branch instruction and a next address of the current branch instruction to generate a branch prediction address, in response to the branch prediction reference data output from the branch prediction table; and a branch prediction result tester generating a control signal for updating the branch history stored in the global history register and the branch prediction reference data stored in the branch prediction table, in response to a comparison between a real branch address and the branch prediction address, wherein the address selection circuit generates the branch prediction address further in response to a state of the control signal generated by the branch prediction result tester.