Patent ID: 7498668

Claim:
A lower module of a stacked semiconductor device comprising: a first semiconductor chip having a plurality of first chip terminals; and a first substrate having a first chip holding surface with a larger plan size than that of the first semiconductor chip and holding the first semiconductor chip above the first chip holding surface, wherein the first substrate includes: a plurality of first chip connection terminals provided on the first chip holding surface and electrically connected to the first chip terminals, respectively; a plurality of upper module connection terminals which are provided on a portion of the first chip holding surface located outside a region where the first semiconductor chip is held and which are electrically connectable to an upper module provided with a second semiconductor chip; and a plurality of external substrate connection terminals provided on a surface thereof opposite to the first chip holding surface, the first chip connection terminals are electrically connected to the external substrate connection terminals, respectively, the upper module connection terminals are electrically connected between the first chip connection terminals and the associated external substrate connection terminals, respectively, and the first chip connection terminals and the upper module connection terminals are connected by an interconnect channel passing through a non-through conductor formed not to penetrate the first substrate, and separated from each other on the first chip holding surface.