Patent ID: 8400807

Claim:
A system comprising: a first semiconductor chip that comprises: a first terminal supplied with a first voltage; a second terminal supplied with first control information; a first circuit electrically coupled to the second terminal, the first circuit being configured to output a first control signal in response to the first control information; a second circuit electrically coupled to the first terminal and the first circuit, the second circuit being configured to operate on the first voltage and generate a second voltage in response to the first control signal; and a third circuit electrically coupled to the second circuit, the third circuit being configured to operate on the second voltage; a second semiconductor chip that comprises: a third terminal supplied with the first voltage; a fourth terminal supplied with second control information; a fourth circuit electrically coupled to the fourth terminal, the fourth circuit being configured to output a second control signal in response to the second control information; a fifth circuit electrically coupled to the third terminal and the fourth circuit, the fifth circuit being configured to operate on the first voltage and generate a third voltage in response to the second control information; and a sixth circuit electrically coupled to the fifth circuit, the sixth circuit being configured to operate on the third voltage; and a controller chip including an information circuit generating the first and second control information; the controller and the first and second semiconductor chips being stacked with one another.