Patent ID: 7130175

Claim:
An integrated circuit arrangement comprising a low-side driver stage (LS) including at least one stage terminal (ALS), an n-channel MOSFET (NM) allocated to said at least one stage terminal (ALS) for connecting said at least one stage terminal to a reference potential in response to a trigger signal received at a gate terminal of said n-channel MOSFET (NM), a protecting circuit for protecting said at least one stage terminal against transient voltages, said protecting circuit comprising a first diode pair including a first Zener-diode (ZD 1 ) and a first diode (D 1 ) connected in series with each other between said at least one stage terminal (ALS) and said reference potential, wherein said first Zener-diode (ZD 1 ) has an anode connected with said at least one stage terminal (ALS) and a cathode connected with a cathode of said first diode (D 1 ), and wherein an anode of said first diode (D 1 ) is connected to said reference potential, said protecting circuit further comprising a second diode pair including a second Zener-diode (ZD 2 ) and a second diode (D 2 ), wherein said second Zener-diode (ZD 2 ) has an anode connected to said reference potential and a cathode connected to a tab of said n-channel MOSFET (NM) and wherein said second diode (D 2 ) has a cathode also connected to said tab and an anode connected to said at least one stage terminal (ALS), said first and second diode pairs forming said protecting circuit for said at least one stage terminal (ALS).