Patent ID: 7387932

Claim:
A method for manufacturing an integrated circuit memory device, comprising: providing a semiconductor body having a first conductivity type; forming a continuous charge storage structure on the semiconductor body; depositing a first gate conductor layer over the charge storage structure; patterning the first gate conductor layer to define a first plurality of gates over the continuous charge storage structure, the first plurality of gates arranged in series with spaces between them over a continuous, multiple-gate channel region between a first terminal location and a second terminal location in the semiconductor body; forming an isolation layer of material on sidewalls of the first plurality of gates; depositing a second gate conductor layer over the isolation layer on the sidewalls and over the continuous charge storage structure in the spaces between the first plurality of gates, and isolated from the first plurality of gates by the isolation layer; to define a second plurality of gates over the continuous charge storage structure on the semiconductor body, the first plurality of gates and the second plurality of gates arranged in series over the continuous, multiple-gate channel region between the first terminal location and the second terminal location in the semiconductor body to form a multiple-gate memory cell.