Patent ID: 7060580

Claim:
A method of fabricating a field effect transistor, comprising: forming a doped poly silicon pattern on a substrate; forming a first insulating layer spacer on a sidewall of the poly silicon pattern; forming a source junction in the substrate beneath both the poly silicon pattern and the first insulating layer spacer by diffusing impurity ions doped in the poly silicon pattern; forming a gate insulating layer on an entire surface of the structure; forming a conductive layer spacer on the gate insulating layer at a sidewall of the first insulating layer spacer; forming a second insulating layer spacer on a sidewall of the conductive layer spacer; forming a third insulating layer spacer on a sidewall of the second insulating layer spacer; forming a drain extending region beneath the third insulating layer spacer and in an exposed region of the substrate; forming a gate electrode formed of the conductive layer spacer, a source layer formed of the poly silicon pattern, and a drain layer formed of the poly silicon layer after forming and planarizing the doped poly silicon layer on an entire surface of the structure; and forming a drain junction in the substrate by diffusing impurity ions doped in the drain layer downward.