Patent ID: 7026717

Claim:
A semiconductor device comprising: a substrate; first topographic patterns deposited over said substrate; second topographic patterns deposited over said substrate, where said first and second topographic patterns define active lead lines and dummy fills, respectively; an array over said substrate, said array comprising a plurality of valleys circumscribing first and second topographic patterns, said array configured such that: a substantially straight-edged periphery around said array is defined by said plurality of dummy fills, said active lead lines, or a combination of both; and no portion of any of said plurality of dummy fills extends laterally beyond said periphery; a grid disposed within said array such that: the longest linear dimension of each of said plurality of valleys making up said grid is no longer than the longest lateral dimension of any of said dummy fills; and no intersection defined by a crossing between any two of said plurality of valleys includes uninterrupted linear dimensions; and a substantially planar layer of insulative material deposited over said plurality of valleys, said planar layer having a thickness sufficient to render a top surface thereof substantially co-planar with a top surface of said first and second topographic patterns.