Patent ID: 8316340

Claim:
A method comprising: providing an integrated circuit comprising a plurality of flip-flops, wherein the plurality of flip-flops is represented by a substantially same circuit diagram; providing a first flip-flop layout for the plurality of flip-flops, wherein the first flip-flop layout has a first hold constraint; providing a second flip-flop layout for the plurality of flip-flops, wherein the second flip-flop layout has a second hold constraint smaller than the first hold constraint, and wherein the first flip-flop layout and the second flip-flop layout have a substantially same cell delay; designing a first circuit layout for the integrated circuit using the first flip-flop layout to implement the plurality of flip-flops; analyzing the first circuit layout to identify a first flip-flop in the plurality of flip-flops having a hold violation; and replacing the first flip-flop layout of the first flip-flop with the second flip-flop layout to form a second circuit layout for the integrated circuit, wherein the step of replacing the first flip-flop layout with the second flip-flop layout is performed by a computer.