Patent ID: 8014166

Claim:
A system for stacking Integrated Circuits vertically to create a three dimensional chip package, said system comprising: silicon dies; one or more redistribution layers; one or more through silicon vias through said silicon dies; one or more contact pads; serial circuits; wherein said silicon dies comprise said serial circuits; wherein said serial circuits are staggered on said silicon dies; wherein said silicon dies are stacked vertically on top of each other in such a way that said serial circuits of said stacked silicon dies do not block each other; wherein one or more fiducials are placed to optically align said silicon dies that are stacked vertically on top of each other; wherein said one or more through silicon vias are placed in said serial circuits; wherein at least one of said one or more redistribution layers is placed between two of said silicon dies; wherein said silicon dies along with said one or more redistribution layers are stacked on top of a substrate; wherein said one or more contact pads are placed on said substrate; wherein said one or more redistribution layers are positioned to interconnect said one or more through silicon vias belonging to said two of said silicon dies and to interconnect said one or more through silicon vias to said one or more contact pads.