Patent ID: 7386081

Claim:
A timing control circuit, comprising: a synchronous pattern detecting portion that detects a synchronous pattern data of a received signal that has been demodulated based on a control signal, and that generates a detection result; a first counter portion that generates a first signal at each first cycle based on the detection result; a second counter portion that generates a second signal at each second cycle based on the detection result; and a control portion that generates the control signal based on the first and second signals, wherein said control portion includes a first logic operation circuit that carries out a logic operation of said first and second signals, and that outputs a first logic operation result, a second logic operation circuit that carries out a logic operation of said first logic operation result and a first external signal, and that outputs a second logic operation result, a third logic operation circuit that carries out a logic operation of said first signal and a second external signal, and that outputs a third logic operation result, and a fourth logic operation circuit that carries out a logic operation of said second and third logic operation results, and that outputs said control signal.