Patent ID: 8787075

Claim:
A semiconductor memory comprising: memory cells each including a pair of cross-couple connected inverters with the respective outputs connected to paths leading to a pair of respective bit lines disposed in correspondence to a column of the memory cells, a pair of switch units provided between the bit lines and the outputs of the inverters, and a single word line for controlling the conduction of the switch units; and a mode control switch unit and a single mode control line for controlling the conduction of the mode control switch unit provided between data holding nodes of adjacent memory cells, the semiconductor memory providing dynamic switching, using the mode control line, between a mode in which one bit is allocated to one memory cell (1-bit/1-cell mode) and a mode in which one bit is allocated to n (where n is two or more) coupled memory cells (1-bit/n-cell mode), the semiconductor memory further comprising: a mode control line selector for dividing the mode control line into word units and selecting among the respective divided word-unit mode control lines; and a word line selector for dividing the word line into word units for controlling the conduction of the switch unit and selecting upon data readout the word line of a memory cell with a word having a larger operating margin as a result of a word-unit memory cell comparison.