Patent ID: 8487676

Claim:
A device for generating at least one clock signal, comprising: a distributed network of phase-locked loops which are interconnected and synchronised with one another, wherein each phase-locked loop comprises: a controlled oscillator capable of delivering the clock signal at an output; a plurality of phase comparators capable of comparing a phase of the clock signal delivered by the controlled oscillator with a plurality of clock signal phases delivered at outputs of the adjacent phase-locked loops, and applied at inputs of the phase-locked loop; means for weighted summation of output signals of the plurality of phase comparators such that one of the weighting coefficients applied to one of the output signals has an absolute value higher than the sum of the absolute values of other weighting coefficients applied to other output signals and/or such that the sum of the absolute values of the weighting coefficients applied to a part of the output signals is greater than the sum of the absolute values of the other weighting coefficients applied to the other output signals; and means for filtering the weighted sum of the output signals of the plurality of phase comparators, and configured to deliver at an output a control signal to the controlled oscillator, and in which, when the sum of the absolute values of the weighting coefficients applied to a part of the output signals is greater than the sum of the absolute values of the other weighting coefficients applied to the other output signals, the clock signals, delivered at the outputs of the adjacent phase-locked loops, and the phases of which compared to the phase of the clock signal delivered by the controlled oscillator correspond to the output signals to which are applied the weighting coefficients, the sum of the absolute values of which is greater than the sum of the absolute values of the other weighting coefficients, are propagated in the distributed network of phase-locked loops without forming a closed loop.