Patent ID: 8205206

Claim:
A data processing apparatus comprising: multi-threaded processing circuitry for executing, under control of an operating system, multiple program threads including at least one high priority program thread and at least one lower priority program thread; at least one storage unit shared between the multiple program threads and comprising multiple entries for storing information for reference by the multi-threaded processing circuitry when executing said multiple program threads; thread control circuitry for detecting a condition indicating an adverse effect caused by a first lower priority program thread being executed by the multi-threaded processing circuitry and resulting from sharing of the at least one storage unit between the multiple program threads, and on detection of said condition to issue as an alert signal an exception signal to the operating system; and a scheduler provided by the operating system and responsive to the alert signal to cause execution of the first lower priority program thread to be temporarily halted, wherein said at least one lower priority program thread comprises said first lower priority program thread and additional lower priority program threads, and wherein the scheduler is configured to maintain a record of the additional lower priority program threads awaiting allocation to the multi-threaded processing circuitry and to temporarily halt execution of the first lower priority program thread by de-allocating said first lower priority program thread and allocating in its place one of the additional lower priority program threads.