Patent ID: 8174423

Claim:
A sub-converter stage for a pipelined analog-to-digital converter, the sub-converter stage comprising: an amplifier with a dc gain A, a sub analog-to-digital converter with comparators and a digital unit, a first capacitor with capacitance C, a second capacitor with capacitance C−ΔC, and wherein said first capacitor is selectively connected between an analog input node and input of said amplifier or between one of customized reference signals (−V refk , 0, or V refk ) and the input of said amplifier; said second capacitor is selectively connected between the analog input node and the input of said amplifier or between the input of said amplifier and output of said amplifier, and wherein Δ ⁢ ⁢ C C = 4 A + 2 ⁢ and ⁢ V refk = V ref ⁡ ( 1 - Δ ⁢ ⁢ C 2 ⁢ C ) , in which ΔC is the capacitance mismatch and V ref is the nominal reference signal in conventional pipelined analog-to-digital converter.