Patent ID: 7929357

Claim:
A data output buffer circuit comprising: a pre-driver configured to adjust a slew rate of an input signal; a main driver configured to drive an output unit in response to an output signal from the pre-driver; and a calibration circuit configured to generate an m-bit binary code based on a variation in an operation voltage and decode the m-bit binary code into an n-bit signal, the calibration circuit configured to control the pre-driver so as to decrease the slew rate if the operation voltage increases, and increase the slew rate if the operation voltage decreases, wherein the pre-driver includes a first pre-driver and a second pre-driver, each of the first and second pre-drivers including, an inverter configured to invert the input signal; a plurality of tri-state inverters configured to provide the inverted input signal to the main driver; and a first inverter drive circuit configured to invert the n-bit signal, wherein the tri-state inverters are selectively activated in response to the n-bit signal and the inverted n-bit signal.