Patent ID: 7563670

Claim:
A method of forming a transistor portion over a capacitor in a vertical DRAM device comprising: providing a partially formed vertical DRAM structure having a lower trench portion filled with polycrystalline or amorphous semiconductor for a capacitor, the polycrystalline or amorphous semiconductor having an exposed upper surface, and an upper trench portion having exposed sidewalls of single-crystal semiconductor above the upper surface of the polycrystalline or amorphous semiconductor fill; etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the polycrystalline or amorphous semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the polycrystalline or amorphous semiconductor fill; depositing a trench top insulating layer on the bottom portion of the upper trench, over the upper surface of the polycrystalline or amorphous semiconductor fill and over the regions of single-crystal semiconductor adjacent to the upper surface of the polycrystalline or amorphous semiconductor fill; forming on the etched single-crystal semiconductor sidewalls of the upper trench portion a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer; and subsequently forming a vertical MOSFET to complete the vertical DRAM.