Patent ID: 8817513

Claim:
A semiconductor device comprising: a first nonvolatile semiconductor memory; a second nonvolatile semiconductor memory; a third nonvolatile semiconductor memory; a fourth nonvolatile semiconductor memory; a substrate that includes: a front surface layer that includes a wiring pattern formed on a front surface of the substrate, a rear surface layer that includes a wiring pattern formed on a rear surface of the substrate, a first inner wiring layer, provided between the front surface layer and the rear surface layer, on which a wiring pattern is formed, a second inner wiring layer, provided between the front surface layer and the rear surface layer, on which a wiring pattern is formed, and a connector that includes electrodes, to be connected with a host device, formed on the rear surface layer of the substrate; a controller configured to control operations of the first, second, third, and fourth nonvolatile semiconductor memories, wherein the controller is mounted on the front surface layer of the substrate; and a first signal line configured to connect the controller with the connector, the first signal line including: a first portion disposed on the front surface layer of the substrate and extending from the controller to a vicinity of the connector, a second portion that penetrates through the substrate from the front surface layer to the rear surface layer in the vicinity of the connector, and a third portion disposed on the rear surface layer of the substrate and connected with the electrodes of the connector.