Patent ID: 8743044

Claim:
A semiconductor device comprising: a pixel portion formed over a substrate; a scan line driver circuit formed over the substrate, the scan line driver circuit comprising: a shift register comprising: an output terminal; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; and an eighth transistor; a first switch formed over the substrate; and a second switch formed over the substrate, wherein one of a source and a drain of the first transistor is directly connected to the output terminal, wherein one of a source and a drain of the second transistor is directly connected to the output terminal, wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, wherein a gate of the fourth transistor is directly connected to a gate of the second transistor, wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor, wherein a gate of the sixth transistor is directly connected to the one of the source and the drain of the third transistor, wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the eighth transistor is directly connected to the one of the source and the drain of the third transistor, wherein a gate of the eighth transistor is directly connected to the gate of the first transistor, wherein a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor, wherein a clock signal is input to a gate of the third transistor, wherein the output terminal is operationally connected to a scan line, wherein a wiring is electrically connected to a first signal line via the first switch, wherein the wiring is electrically connected to a second signal line via the second switch, wherein the wiring is electrically connectable to a driver IC, and wherein the second transistor comprises a channel region comprising an oxide semiconductor.