Patent ID: 8835933

Claim:
A recessed gate-type silicon carbide field effect transistor, comprising: a substrate ( 1 ) including a one-conductivity-type silicon carbide semiconductor region ( 2 ) having one main face; a source region and a drain region ( 3 , 4 ) of an opposite-conductivity-type to the one-conductivity-type that each have an approximately same impurity concentration, and are formed in contact with the one main face and spaced from each other in the one-conductivity-type silicon carbide semiconductor region ( 2 ); a recess ( 5 ) formed in the one main face side of the one-conductivity-type silicon carbide semiconductor region ( 2 ) sandwiched between facing edges of the spaced source and drain regions ( 3 , 4 ), the recess comprising a first side face in contact with the source region ( 3 ), a second side face in contact with the drain region ( 4 ), and a bottom face that is located at a predetermined depth from the one main face, continues to the first and second side faces, and connects the spaced source and drain regions ( 3 , 4 ), to extend over the source and drain regions ( 3 , 4 ); an insulating layer ( 6 ) covering a portion of the one main face with which the source and drain regions ( 3 , 4 ) are in contact, and formed on the first and second side faces and the bottom face of the recess ( 5 ); a gate electrode ( 7 ) formed on the insulating layer ( 6 ); and a source electrode and a drain electrode ( 11 , 12 ) electrically connected to the source and drain regions ( 3 , 4 ), wherein a channel forming region is constituted at a portion of the silicon carbide semiconductor region adjacent to the main portion of the bottom face connecting the source and drain regions ( 3 , 4 ), and wherein portions extended over the source and drain regions ( 3 , 4 ) in the vicinity of both ends of the bottom face of the recess ( 5 ) are in contact with thin regions ( 3 a, 4 a) of the source and drain regions have the approximately same impurity concentration.