Patent ID: 7843906

Claim:
A system comprising: a switch fabric having a plurality of physical ports; a plurality of physical partitions of a physically partitionable symmetric multiprocessor, each physical partition coupled to the switch fabric via at least one respective partition input/output controller, each physical partition comprising links between processors of the physically partitionable symmetric multiprocessor, the links being programmatically configurable to selectively isolate subsets of the processors with respect to respective shared memory coherency and cache memory coherency transactions; wherein at least a first one of the physical partitions is enabled to execute a mass storage control process to control mass storage traffic, the mass storage control process enabled to provide software-process-visible state via one or more dedicated hardware registers for each of a plurality of logical storage interfaces; wherein at least a second one of the physical partitions is enabled to execute a program to process the mass storage traffic; and wherein the partition input/output controllers are enabled to communicate the mass storage traffic between a plurality of processes executing on the physical partitions and a mass storage input/output controller coupled to the switch fabric, at least in part by addressing cells to physical port addresses corresponding to physical ports of the switch fabric, and each of the partition and the mass storage input/output controllers is associated with a respective unique one of the physical ports.