Patent ID: 7342272

Claim:
A memory device comprising a substrate; two source/drain regions coupled to the substrate adjacent a surface of the substrate; at least one recess access gate formed with a first portion which extends beneath the substrate surface into the substrate and a second portion which extends above the substrate surface by a selected distance and so as to be interposed between the two source/drain regions wherein the at least one recessed access gate defines a conductive channel between the two source/drain regions that is recessed from the surface in the substrate and wherein the at least one recessed access gate device has an upper surface proximate the surface of the substrate wherein the at least one recessed access device defines at least one floating gate structure having an upper surface and wherein variation of the selected distance of the second portion of the recess access gate above the substrate modifies a capacitive coupling between the recess access gate, the substrate, and the control gate structure to thereby affect an ability of a charge to be stored or removed from the floating gate structure; at least one control gate structure formed on the upper surface of the at least one floating gate structure wherein the at least one control gate structure and the at least one floating gate structure are formed so as to allow charge to be selectively stored and removed from the at least one floating gate structure to selectively change a state of the conductive channel to thereby provide an indication of a memory state of the memory device.