Patent ID: 7797121

Claim:
A test apparatus constructed and arranged to test a device under test comprising: first and second comparators configured and arranged to measure, at a sampling rate determined by a sampling clock, a measured signal that is output from the device under test; a deciding section that decides a quality of the device under test on the basis of a measurement result provided by the first and second comparators; a jitter injecting section configured to inject jitter into a test signal to be provided to the device under test and to provide to the first and second comparators an adjustment signal having the same jitter injected into the test signal; a skew computing section configured to compute a skew between the first comparator and the second comparator on the basis of a sampling result in the first comparator and a sampling result in the second comparator; and a phase adjusting section constructed and arranged to adjust a phase of at least one of the measured signal and the sampling clock on the basis of an amount of skew computed by the skew computing section, wherein the skew computing section includes: a first phase computing section configured to compute, from a sampling result of the first comparator, a phase of the adjustment signal to be provided to the first comparator; and a second phase computing section configured to compute, from a sampling result of the second comparator, a phase of the adjustment signal to be provided to the second comparator, and wherein the skew computing section is configured to compute the skew on the basis of a difference between phases computed by the first phase computing section and the second phase computing section, respectively.