Patent ID: 7301197

Claim:
An EEPROM transistor comprising: a substrate of semiconductor conductivity having a grounded conductive contact in an active area bound by isolation regions, a gate stack structure disposed on the substrate, the gate stack structure having a nanocrystal layer disposed in an insulative manner over the substrate and an overlying control layer insulated from the nanocrystal layer, source and drain regions in the active area of the substrate flanking the gate stack structure, both of a first conductivity type, an injector region having two spaced apart portions in the active area of the substrate of a second conductivity type, both injector portions in contact with one of the source and drain regions, the two portions of the injector region overlapping the active area at spaced apart locations, thereby forming a p-n junction in the substrate, and reversible bias means not exceeding five volts associated with the p-n junction for causing charge carriers of a first polarity to flow into the grounded conductive contact of the substrate causing space charge in the substrate with charge carriers of a second polarity impacting upon the source and drain regions thereby causing hot electrons to become trapped in the nanocrystal layer thereby programming the nanocrystal layer with bias in one voltage polarity and electrically erasing the nanocrystal layer with bias in another voltage polarity.