Patent ID: 7783870

Claim:
A processor, comprising: at least one execution unit that executes instructions; and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including a branch logic that outputs predicted branch target addresses for use as instruction fetch addresses, said branch logic including a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address; wherein said branch logic accesses the level one BTAC and the level two BTAC in parallel with at least a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC and a second predicted branch target address from the level two BTAC; wherein the instruction sequencing logic fetches instructions from the memory system utilizing the first predicted branch target address as a second instruction fetch address in a first processor clock cycle and fetches instructions from the memory system utilizing the second predicted branch target address as a third instruction fetch address in a second processor clock cycle subsequent to the first processor clock cycle.