Patent ID: 7036000

Claim:
An apparatus comprising: a digital signal processor including a pipeline having a plurality of pipeline stages; a valid bit generator in a first pipeline stage to generate a valid bit; a signal generator to generate and transmit stall signals and kill signals to a plurality of said pipeline stages; a first valid bit qualifier in a second pipeline stage to set the valid bit to an invalid value in response to receiving at least one of a stall signal and a kill signal; a first latch to store the valid bit output from the first valid bit qualifier; a first latch enable circuit connected to the first latch, said first latch enable circuit adapted to hold the valid bit in the first latch in response to receiving a stall signal; and a second valid bit qualifier in a third pipeline stage to set the valid bit output from the first latch to an invalid value in response to receiving at least one of a stall signal and a kill signal.