Patent ID: 7200030

Claim:
A semiconductor memory device comprising a memory cell array in which a plurality of static type memory cells comprised of a latch circuit including a pair of driver MOSFETs and a load device and two transfer MOSFETs accessing to the latch circuit are arranged, the semiconductor memory device comprising: a switch for controlling a source line connected to a source electrode of a said driver MOSFET and a ground potential line so that the source line and the around potential line are connected in an operational state of said memory cells and not connected in a standby state of said memory cells; a source potential control circuit connected between said source line and said ground potential; wherein, in the standby state of said memory cells, a source potential is set to an intermediate potential between the ground potential and the supply potential by said source potential control circuit; and wherein said source potential control circuit includes at least first and second elements connected in parallel with each other, said first element having a resistance less than a resistance of said second element and predetermined according to a value of Vth of said driver MOSFETs and said transfer MOSFETs.