Patent ID: 8082417

Claim:
A microprocessor, comprising: a micro-processing core circuit, which comprises a higher bit address bus and a lower bit address/data bus, for generating a first address latching signal, a read/write control signal and an access enable signal; a delaying circuit, for delaying the first address latching signal by a default time and then outputting a second address latching signal, wherein, when the first address latching signal is changed from a first logic potential to a second logic potential, the second address latching signal is changed from the first logic potential to the second logic potential, wherein, when the first address latching signal is changed from the second logic potential to the first logic potential, the second address latching signal is held at the second logic potential by the default time and then changed to the first logic potential; a multiplexer, which is coupled to the higher bit address bus and the lower bit address/data bus, and comprises a common bus, wherein the multiplexer electrically connects the lower bit address/data bus to the common bus according to the second address latching signal when the second address latching signal is enabled, and the multiplexer electrically connects the higher bit address bus to the common bus according to the second address latching signal when the second address latching signal is disabled; a common bus port, having a plurality of pins connected to the common bus of the multiplexer, wherein the number of the pin of the common bus port is the same as the number of signal lines of the common bus of the multiplexer; a first address latch pin, for outputting the first address latching signal; a second address latch pin, for outputting the second address latching signal; a read/write control pin, for outputting the read/write control signal; and an access enable pin, for outputting the access enable signal wherein, the micro-processing core circuit, the delaying circuit, the multiplexer, the common bus port, the first address latch pin, the second address latch pin, the read/write control pin, and the access enable pin are disposed of an integrated circuit, wherein, when the integrated circuit accesses a external memory circuit, the microprocessor sequentially outputs a high bit address carried by the higher bit address bus and a lower bit address carried by the lower bit address/data bus to the external memory circuit through the pins of the common bus port.