Patent ID: 7096581

Claim:
A method for fabricating an integrated circuit, comprising the steps of: fabricating a portion of the integrated circuit, the portion comprising at least one active circuit area; fabricating a redistribution metal layer over the at least one active circuit area; depositing a polyimide layer over at least a portion of the redistribution metal layer; and etching the polyimide layer to leave at least one portion of the redistribution metal layer open to receive at least one solder bump; wherein fabricating the portion of the integrated circuit and the redistribution metal layer comprises the steps of: fabricating the active circuit area and an associated metal pad on a base substrate; fabricating a vertical plug in electrical connection with the metal pad; depositing an undoped silicon oxide layer on the active circuit urea and on a portion of the metal pad; depositing a phosphosilicate glass layer on the undoped silicon oxide layer; depositing a silicon oxynitride layer over the phosphosilicate glass layer; and depositing a flat metal layer over the silicon oxynitride layer and in electrical connection with the vertical plug.