Patent ID: 8417844

Claim:
An apparatus comprising: a host including at least one address space mapped to a memory system of the host, the host including a data buffer; a direct memory access (DMA) controller coupled to the host and the data buffer, wherein the DMA controller is configured to read DMA data from the host, and wherein the host is configured to write the DMA data into the data buffer; a peripheral interface controller coupled to the data buffer and configured to control transfers on a peripheral interface, wherein the peripheral interface controller is configured to read the DMA data from the data buffer and transfer it on the peripheral interface in response to the DMA data being data targeted to the peripheral interface, and wherein the DMA data does not pass through the DMA controller when the DMA data is targeted to the peripheral interface; and at least one media access control (MAC) unit coupled to the DMA controller, wherein the DMA controller is further configured to read the DMA data from the data buffer to be transferred by the MAC unit in response to the DMA data being packet data targeted to a network to which the MAC unit is coupled, and wherein the DMA data passes through the DMA controller when the DMA data is targeted to the network.