Patent ID: 7977733

Claim:
A non-volatile semiconductor storage device comprising: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors are formed, the transistors configuring peripheral circuits to control the memory cells, the memory cell area comprising: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to the semiconductor substrate, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers; and the peripheral circuit area comprising: a plurality of dummy wiring layers each formed on the same plane as each of the plurality of conductive layers and electrically separated from the conductive layers, wherein the transistors are planar-type transistors with impurity diffusion areas in the semiconductor substrate, a transistor conductive layer is formed between a lowermost layer of the plurality of dummy wiring layers and the semiconductor substrate, so as to be sandwiched between the impurity diffusion areas, wherein the transistor conductive layer functions as gate electrodes of the planar-type transistors, the transistor conductive layer is connected to a first contact, wherein the first contact is formed to penetrate the dummy wiring layers and extend in the lamination direction, and each of the impurity diffusion areas is connected to a second contact formed to penetrate the dummy wiring layers and extend in the lamination direction.