Patent ID: 7522461

Claim:
A memory device having a plurality of memory cells, the memory device comprising: a pre-charge driver having an input for receiving a pre-charge triggering signal and an output, the pre-charge driver operable to output a pre-charge signal when activated by the pre-charge triggering signal; a pre-charge line coupled to receive and supply the pre-charge signal to a plurality of bitlines, each of the bitlines coupled to a plurality of the memory cells, wherein the pre-charge line is further operable to supply a pre-charge output signal; a timing controller having an input coupled to receive the pre-charge output signal and an output, the timing controller operable to provide a wordline triggering signal based upon the received pre-charge output signal; a wordline driver having an input for receiving a wordline triggering signal and an output, the wordline driver operable to output a wordline signal when activated by the wordline triggering signal; and a wordline coupled to receive and supply the wordline signal to a plurality of the memory cells.