Patent ID: 7827355

Claim:
A data processor comprising: a first cache comprising a first line, wherein the first line includes a first field that stores a first data representative of a set of one or more instructions and a second field that stores bits representing branch prediction information for the set of one or more instructions; and a compressor configured to: obtain a first set of bits representing a first branch prediction information for the set of one or more instructions, wherein the first branch prediction information represents, for each branch instruction of the set of one or more instructions, a branch type of the branch instruction and taken or not taken history information, the branch type comprising one selected from a call instruction type; a return instruction type; a static branch type; and a dynamic branch type; and compress the first set of bits to generate a second set of bits for storage in the second field, the second set of bits representing a second branch prediction information for the set of one or more instructions, the second branch prediction information comprising only a subset of the first branch prediction information and the second set of bits comprising fewer bits than the first set of bits, wherein the second branch prediction information represents, for each branch instruction of the set of one or more instructions, whether the branch instruction is a static branch or a dynamic branch.