Patent ID: 8369472

Claim:
A semiconductor integrated circuit device comprising: a phase locked loop; an interpolator; a first divider; a pointer; a phase comparator; a filter; a second divider; and a third divider, wherein the phase locked loop generates multi-phase clocks having the same frequency and different phases, wherein the interpolator composes the multi-phase clocks to generate a composite clock having a phase that is designated by the pointer, wherein the first divider divides the composite clock at a predetermined first division ratio to generate a first recovery cock, wherein the phase comparator compares the phase of input data with the phase of the first recovery clock, outputs a phase delay signal when the phase of the first recovery clock lags the phase of the input data, and outputs a phase advance signal when the phase of the first recovery clock leads the phase of the input data, wherein the pointer updates the phase in response to the phase delay signal or the phase advance signal, and designates the updated phase to the interpolator, wherein the second divider divides the first recovery clock at a predetermined second division ratio to generate a second recovery clock, wherein the third divider divides the first recovery clock at a predetermined third division ratio to generate a third recovery clock, wherein the phase comparator operates using the first recovery clock as an operation clock, wherein the filter operates using the second recovery clock as an operation clock, and wherein the pointer operates using the third recovery clock as an operation clock.