Patent ID: 7485961

Claim:
A semiconductor device substantially impervious to the effects of buckling, said device comprising: a) a single first planarization layer disposed on a semiconductor substrate, the single first planarization layer having a first reflow temperature and a first thermal coefficient of expansion; b) a barrier film disposed on the single first planarization layer; and c) a single second planarization layer disposed on the barrier film, the single second planarization layer having a second reflow temperature and a second thermal coefficient of expansion, wherein the barrier film does not reflow at the first or second reflow temperatures and retains its structural integrity to isolate the single first planarization layer from the single second planarization layer, thereby preventing the single first planarization layer and the single second planarization layer from interacting, and enabling the single first planarization layer and the single second planarization layer to uniformly reflow.