Patent ID: 7224190

Claim:
An integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit including a precharge node at an input of said logic function implementation, an output latch connected to an output node of said logic function for stabilizing the result of the evaluation of said logic function, in order to avoid switching the latch due to a precharge pulse imparted to said precharge node, said integrated circuit comprising: (a) a gate of a switching transistor device connected to an input node for receiving a clock signal shared with said logic function, the drain thereof being connected to the input node of said output latch; (b) a gate of a second transistor device being connected to said precharge node, with the source of said transistor device being connected directly to ground and with a drain thereof being connected to a source input of said switching transistor; (c) time-delay-controlling elements connected between said clock signal input node and the control input of said switching transistor device; and (d) said time-delay controlling elements being dimensioned such that a predetermined delay is imparted to the control input of said switching transistor device, wherein time control of the switching transistor device is implemented such that it stabilizes the bit value present on the latch input node against its instability caused by the switching delay of said logic function.