Patent ID: 8410813

Claim:
A circuit on an integrated circuit comprising: a first resistor having an input and an output, said first resistor input coupled to receive an input; a first n-channel transistor having a drain, a gate, and a source, said first n-channel gate connected to said first resistor input, and said first n-channel drain connected to said first resistor output; a second resistor having an input and an output, said second resistor input connected to said first n-channel transistor source; a second n-channel transistor having a drain, a gate, and a source, said second n-channel transistor drain connected to said second resistor output; a first p-channel transistor having a source, a gate, and a drain, said first p-channel transistor gate connected to said first resistor input, and said first p-channel transistor drain connected to said first resistor output; a third resistor having an input and an output, said third resistor input connected to said first p-channel transistor source; and a second p-channel transistor having a source, a gate, and a drain, said second p-channel transistor drain connected to said third resistor output.