Patent ID: 7127002

Claim:
A system for multiplying data throughput in a SCSI bus comprising: a transmitter including: an data input; a modulator; a first phase locked loop (PLL) circuit, the first PLL for stabilizing a clock signal, the stabilized clock signal being coupled to the modulator; logic for identifying a plurality of phases within a bandwidth of a SCSI bus; logic for assigning a binary value to each one of the plurality of phases; logic for selecting one of the plurality of phases wherein the assigned binary value of the selected phase corresponding to a plurality of bits to be transmitted during a first sampling cycle; and logic for transmitting the selected phase on the SCSI bus during the first sampling cycle; a receiver, the receiver being coupled to the transmitter by a SCSI bus, the receiver including: a demodulator; an adding circuit having a first input coupled to an output of the demodulator; a second PLL circuit having an input coupled to the stabilized clock signal from the first PLL circuit and having an output coupled to a second input to the adding circuit; logic for receiving the selected phase in a receiver during the first sampling cycle; logic for identifying the selected phase; logic for determining the corresponding assigned binary value of the selected phase; and logic for outputting the corresponding assigned binary value of the selected phase.