Patent ID: 7388224

Claim:
A test structure used to determine reliability performance of a semiconductor chip structure, comprising: a patterned metallization structure having a plurality of interfaces, which provide stress risers, the metallization structure including at least one of: a via chain formed through layers of the semiconductor chip structure such that a plurality of widths of vias are used to adjust strain in different layers, and a dummy structure formed to provide a via density in an area of the semiconductor chip structure to adjust strain in adjacent structures of the test structure; and a dielectric material surrounding the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist, wherein the mismatch in CTE between the metallization structure and the dielectric material is greater than about 20 ppm/° C. such that the test structure includes a thermal strain value to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.