Patent ID: 7598515

Claim:
A semiconductor device comprising: a strained superlattice layer comprising a plurality of stacked groups of layers; non-superlattice regions for causing transport of charge carriers through said strained superlattice layer in a parallel direction relative to the stacked groups of layers; and a stress layer above said strained superlattice layer; each group of layers of said strained superlattice layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and a single non-semiconductor monolayer constrained inside a crystal lattice of adjacent base semiconductor portions in the stacked base semiconductor monolayers, at least some semiconductor atoms from opposing base semiconductor portions in the stacked base semiconductor monolayers being directly chemically bound together, and the chemical bonds traversing the single non-semiconductor monolayer therebetween, wherein the non-superlattice regions form source and drain regions with the strained superlattice layer therebetween.