Patent ID: 8848446

Claim:
A nonvolatile semiconductor memory device comprising: a first bit line; a second bit line; a third bit line; a first unit including first memory cells connected in series and a first select gate transistor, one end of the first select gate transistor being connected to the first bit line; a second unit including second memory cells connected in series and a second select gate transistor, one end of the second select gate transistor being connected to the second bit line; a third unit including third memory cells connected in series and a third select gate transistor, one end of the third select gate transistor being connected to the third bit line; a plurality of word lines connected to gates of the first to third memory cells; a select gate line connected to gates of the first to third select gate transistors; and a controller configured to perform a first writing operation in a first period and a second writing operation in a second period different from the first period, the controller being configured to apply a first voltage to a select gate line when the controller is configured to apply a second voltage to the first bit line, to apply a third voltage to the second bit line, and to apply a program voltage to a selected word line in the first writing operation, the second voltage being higher than the third voltage, and the controller being configured to apply a fourth voltage to the select gate line when the controller is configured to apply the second voltage to the first bit line, to apply the third voltage to the second bit line, to apply a fifth voltage to the third bit line, and to apply the program voltage to the selected word line in the second writing operation, the fifth voltage being higher than the third voltage and being lower than the second voltage, and the fourth voltage being different from the first voltage.