Patent ID: 6849490

Claim:
A method of manufacturing a semiconductor device, comprising: selectively forming in a semiconductor substrate first, second, third, fourth, fifth and sixth diffusion regions apart from one another, said first and second diffusion regions constituting a first memory cell having a first floating gate over a first channel region sandwiched between said first and second diffusion regions and a first control gate over said first floating gate, said second and third diffusion regions constituting a second memory cell having a second floating gate over a second channel region sandwiched between said second and third diffusion regions and a second control gate over said second floating gate, said fourth and fifth diffusion regions constituting a third memory cell having a third floating gate over a third channel region sandwiched between said fourth and fifth diffusion regions and a third control gate over said third floating gate, said fifth and sixth diffusion regions constituting a fourth memory cell having a fourth floating gate over a fourth channel region sandwiched between said fifth and sixth diffusion regions and a fourth control gate over said fourth floating gate; forming a mask layer to cover a surface of said second region with leaving top surfaces of said first, second, third and fourth control gates and surfaces of said first, third, fourth and sixth diffusion regions uncovered; forming a silicide layer on said top surface of said first, second, third and fourth control gates and said surfaces of said first, third, fifth and sixth diffusion regions, said surfaces of said second region being free from formation of said silicide region by existence of said mask layer.