Patent ID: 7098694

Claim:
An electronic circuit comprising: a buffer; a first N-channel device (M 5 ); a first P-channel device (M 7 ); a second N-channel device (M 8 ); a second P-channel device (M 9 ); the first N-channel device (M 5 ), the first P-channel device (M 7 ), the second N-channel device (M 8 ) and the second P-channel device (M 9 ) configured as pass gates; said first N-channel device (M 5 ) and the first P-channel device (M 7 ) coupled between an input point (PAD) and an input (N 2 ) of the buffer; and the second N-channel device (M 8 ) and the second P-channel device (M 9 ) arranged in parallel, coupled from the input point (PAD) to a gate of the first P-channel device (M 7 ).