Patent ID: 8810498

Claim:
A gate driving circuit including a plurality of stages which are connected to each other one after another and each stage of the plurality of stages outputs a gate voltage to a corresponding gate line of a plurality of gate lines in response to at least one clock signal, each stage of the plurality of stages comprising: a voltage output part which outputs the gate voltage; an output driving part which drives the voltage output part; a holding part which holds the gate line at an off-voltage; and a discharge part arranged at a first end of the gate line to discharge the corresponding gate line to the off-voltage in response to the gate voltage output from the voltage output part, wherein the discharge part comprises: a first discharge circuit which receives the gate voltage output from the voltage output part to discharge the gate voltage to the off-voltage; and a second discharge circuit which discharges the gate voltage output from the voltage output part to the off-voltage in response to a discharge control signal, and wherein each stage of the plurality of stages receives the at least one clock signal comprises a first clock signal and a second clock signal, each of the first clock signal and the second clock signals has a duty ratio that is larger than 0% and smaller than 50%, wherein the discharge control signal is generated based on states of the first clock signal and the second clock signal, and wherein the discharge control signal is in a high state when both of the first clock signal and the second clock signal are in a low state.