Patent ID: 7952140

Claim:
A semiconductor device having a multiple channel transistor comprising: a semiconductor substrate having first and second isolation regions, the first and second isolation regions defining an active region; a first semiconductor pillar having sidewalls in the active region, a portion of the sidewalls of the first semiconductor pillar in contact with the first isolation region; second and third semiconductor pillars in the active regions, the second and third semiconductor pillars being spaced apart from the first semiconductor pillar respectively; a first recessed region between the first and second semiconductor pillars; a second recessed region between the second and third semiconductor pillars; a buffer insulating layer pattern in the second recessed region, wherein a top surface of the buffer insulating layer pattern is at substantially a same level as top surfaces of the second and third semiconductor pillars; a gate dielectric layer on the surface of the first semiconductor pillar, the second semiconductor pillar, the third semiconductor pillar, the first recessed region, and the buffer insulating layer pattern; and a gate electrode on the gate dielectric layer.