Patent ID: 7659172

Claim:
A method for forming a field effect transistor (FET) device, the method comprising: forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, said semiconductor wafer including a buried insulating layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over said buried insulator layer; forming source and drain extensions in said semiconductor-on-insulator layer, adjacent opposing sides of said gate conductor; forming source and drain sidewall spacers adjacent said gate conductor; removing remaining portions of said semiconductor-on-insulator layer adjacent said sidewall spacers; forming additional sidewall spacers adjacent said source and drain sidewall spacers; removing exposed portions of said buried insulator layer by a vertical etch thereof, followed by a horizontal, recess etch thereof, so as to expose portions of said bulk substrate, wherein a remaining portion of said buried insulator layer below said gate conductor has a length so as to expose only a bottom surface of said source and drain extensions; epitaxially growing a semiconductor layer on said exposed portions of said bulk substrate and said bottom surface of source and drain extensions; forming source and drain implants in said epitaxially grown semiconductor layer.