Patent ID: 7000094

Claim:
An apparatus for processing data, said apparatus comprising: (i) a processor core having a register bank containing a plurality of registers and being operable to execute operations upon register operands held in said registers as specified within instructions of a first instruction set; and (ii) an instruction translator operable to translate instructions of a second instruction set into translator output signals corresponding to instructions of said first instruction set, instructions of said second instruction set specifying operations to be executed upon stack operands held in a stack; wherein (iii) said instruction translator is operable to allocate a set of registers within said register bank to hold stack operands from a portion of said stack; (iv) said instruction translator has a plurality of mapping states in which different registers within said set of registers hold respective stack operands from different positions within said portion of said stack; (v) said instruction translator is operable to change between said plurality of mapping states in dependence upon operations that add or remove stack operands held within said set of registers; and (vi) wherein said instruction translator uses a plurality of instruction templates for translating instructions from said second instruction set to instructions from said first instruction set and wherein an instruction from said second instruction set including one or more stack operands has an instruction template comprising one or more instructions from said first instruction set in which register operands are mapped to said stack operands in dependence upon a currently adopted mapping state of said instruction translator.