Patent ID: 7558136

Claim:
A memory device, comprising: at least one test memory cell comprising a symmetric storage latch including a first inverter stage and a second inverter stage with an output of the first inverter stage providing an input to the second inverter stage and an output of the second inverter stage providing an input to the first inverter stage whereby a state of the at least one test memory cell is statically maintained; a plurality of other memory cells coupled to at least one bitline to form a column; and an asymmetric pair of power supply connections, a first connection to a first power supply input of said first inverter stage and a second connection to a second power supply input of said second inverter stage, whereby a stability of said at least one test memory cell can be evaluated by varying the asymmetry between said pair of power supply connections by varying a power supply voltage provided to the first power supply input and observing operation of said at least one test memory cell, and wherein the asymmetry is not applied to the other memory cells.