Patent ID: 6898739

Claim:
A method for testing a memory circuit, the method which comprises: providing the memory circuit with a cell array and an access device, the cell array including a plurality of cells for storing a binary data item as one of two defined states, the access device being configured to selectively address the cells and to one of apply a write signal to an addressed one of the cells in order to produce a desired state in the addressed one of the cells and read out the addressed one of the cells by sensing and analyzing a state of the addressed one of the cells; successively selecting all cells in at least one region of the cell array as target cells and carrying out a test cycle on each of the target cells, the test cycle including: A) selecting a target cell together with a set of neighboring cells, the set of neighboring cells including at least those cells for which a possibility of an operation having a fault-producing interaction with an operation of the target cell cannot be ruled out; B) writing a data item to the target cell in order to produce one of the two defined states, and applying a write signal to the neighboring cells in order to produce in the neighboring cells an undefined state which lies between the two defined states; C) reading the target cell and the neighboring cells; and D) checking whether there is any interaction between an operation of the target cell and an operation of the neighboring cells by using a result of the step of reading the target cell and the neighboring cells.