Patent ID: 6931462

Claim:
A memory controller comprising: a first port and a second port which receive and transmit an N-bit data value, respectively; a third port receiving and transmitting a 2N-bit data value; and a fourth port and a fifth port, each receiving and transmitting an N-bit data value; wherein during a first operation, two N-bit data values are simultaneously fetched from a memory device corresponding to the first port via the first port and from a memory device corresponding to the second port in response to a command signal and an address input received via the third port, the two fetched N-bit data values are combined into a 2N-bit data value, and the 2N-bit data value is transmitted to the third port, and wherein during a second operation, the N-bit data value is fetched from at least one of the corresponding memory devices via the at least one corresponding first port and second port in response to a command signal and address input via at least one of the fourth port and fifth port, and the fetched N-bit data value is transmitted to the at least one of the fourth port and fifth port.