Patent ID: 7304901

Claim:
An integrated circuit ( 10 ) comprising: a memory array ( 14 ) having a plurality of memory elements ( 18 , 20 ) including: at least one redundant memory element ( 20 ) for exchanging with a failed memory element in the plurality of memory elements; a built-in memory self test unit ( 12 ) including: a test unit ( 21 ) for determining whether a memory element is failing and generating a fail signal in response thereto; a redundancy enablement activator ( 23 ) for timing the enablement of redundancy via a load-enable signal; and a failing address register ( 16 ) for controlling enablement of a corresponding redundant memory element when the fail signal is active based on the load-enable signal, wherein each failing address register ( 26 ) includes: a set of address bits (A 0 -An) for containing an address location of a failing memory element to be replaced by a redundant memory element ( 20 ) an enable bit (EN) for controlling whether the memory element whose address location is contained in the address bits is to be replaced with a corresponding redundant memory element; a bad-redundancy bit (BR) for overriding the enable bit; a temporary enable bit (TB) for holding a value to be loaded into the enable bit in response to the load-enable signal; and a temporary bad-redundancy bit (TB) for holding a value to be loaded into the bad-redundancy bit in response to the load-enable signal.