Patent ID: 7650523

Claim:
An interface apparatus for synchronous interchange of a data word between two circuit blocks comprising: a data input configured to receive a data word, and a data output configured to output the data word; a first register device and a second parallel-connected register device, each having an input coupled to the data input, a selection input, and an output, and each configured to store a data word applied on the input side and to emit the data word at the respective output; a selection circuit, connected to the output of the first register device and to the output of the second register device, and configured to selectively couple the output of the first or the second register device to the data output as a function of a control signal provided thereto; a first clock input configured to receive a first clock signal; a second clock input configured to receive a second clock signal; a synchronization circuit, coupled to the first and the second clock input and having a control output coupled to the selection circuit, and configured to emit a selection signal that is derived from the first clock signal for selection of the first or the second register device for storage of a data word applied to the data input, and wherein the synchronization circuit further comprises a sampling apparatus which is clocked with the second clock signal and is configured to emit the control signal at the control output, wherein the control signal is derived from the selection signal and the second clock signal, and wherein the sampling apparatus is configured to detect a change in the selection signal, and wherein the sampling apparatus comprises a first and at least one second flipflop circuit having data inputs configured to receive the selection signal, with a clock input of the first flipflop circuit being connected to the second clock input, and a clock input of the at least one second flipflop circuit being connected via at least one first delay element in order to delay the second clock signal in time, to the second clock input.