Patent ID: 8012820

Claim:
A method for forming FET devices comprising: a) forming an Ultra-Thin Silicon On Insulator (UTSOI) layer atop a buried layer of insulator material region within a semiconductor substrate, b) forming (Shallow Trench Isolation) STI regions to isolate active SOI regions for forming a respective NFET device and PFET device; c) forming atop said active UTSOI layer a gate electrode structure for each respective NFET and PFET device in a respective isolated active UTSOI region, said gate including a gate dielectric layer formed atop said active UTSOI layer and a corresponding gate conductor formed atop said gate dielectric layer for each respective NFET and PFET device; d) forming thin disposable spacers on each sidewall of the gate electrodes for each respective NFET and PFET device; e) removing portions of the UTSOI layer at respective source region and drain region at each side of said gate electrode of said PFET device to create a recess at the active UTSOI region of the PFET device while leaving a thin UTSOI layer under said gate electrode defining a gate channel region for the PFET device; f) epitaxially growing embedded semiconductor extensions in each respective recess corresponding to said source and drain regions of the PFET device; g) depositing a layer of dielectric material over both NFET and PFET devices; h) performing etching of said dielectric layer to form thick disposable gate sidewall spacers at both NFET and PFET devices; i) forming raised source/drain (RSD) structures on top of respective epitaxially grown embedded semiconductor extensions of the PFET device and, forming raised source/drain (RSD) structures on top of said UTSOI layer at respective source region and drain region at each side of said gate electrode of said NFET device; and, j) removing said thick SiN disposable sidewall spacers at both NFET and PFET devices, wherein said epitaxially grown embedded semiconductor extensions create compressive stress in the UTSOI channel layer of said PFET device thereby enhancing device performance.