Patent ID: 8245390

Claim:
A method of manufacturing a printed wiring board (PWB), comprising: providing a first substrate; providing at least two alternating layers of a second substrate and a metal layer; providing, as a layer 2 metallization of the PWB, a CTE-matching layer of an engineered material having a configurable coefficient of thermal expansion (CTE) to provide substantial CTE matching with respect to the first substrate and a non-metal PWB layer or component to be mounted to the CTE matching layer; drilling holes in the CTE-matching layer where electrically isolated vias are intended, said holes having a diameter larger than that of the intended electrically isolated vias; and filling said holes with non-conductive epoxy so that when the holes for the electrically isolated vias are drilled and plated through on the PWB, they will be electrically isolated from the CTE-matching layer by the remaining epoxy.