Patent ID: 7283420

Claim:
A multi-port memory device, comprising: a global data bus; a plurality of banks, each including a first transmitter and a first receiver, the transmitter and the receiver for each bank exchanging a data with the global data bus; a plurality of ports, each including a second transmitter and a second receiver for exchanging data with the global data bus; a plurality of switches, each provided between the transmitter and the receiver in each bank and the global data bus for selectively connecting the transmitter and the receiver of the bank with the global data bus; and a switching controller for generating a switch signal for each of the switches in response to a drive pulse and a data signal at the input of the first transmitter of the bank, wherein the switch signal turns on/off the switches corresponding to the banks and when a first transmitter of a bank transmits data to the global data bus, a switch corresponding to the bank is turned on and switches corresponding to the other banks are turned off.