Patent ID: 7493436

Claim:
A method for managing interrupts on an information processing system, the method comprising the steps of: placing at least one physical processor of the information processing system in a simultaneous multi-threading mode; partitioning at least a first logical processor and a second logical processor associated with the at least one physical processor; assigning the first logical processor to manage interrupts and the second logical processor to dispatch runnable user threads; receiving an external interrupt; changing a state of the first logical processor from a dormant state to an active state in response to an interrupt; calling, by the first logical processor, an interrupt handler for handling the external interrupt; determining, in response to the calling, if at least one blocked user thread exists in a waiting queue, wherein the at least one blocked user thread can become runnable as a result of the interrupt; if the at least one blocked user thread exists in the waiting queue, setting a machine state save area associated with the first logical processor to a save area associated with the at least one blocked user thread; and directly executing an instruction stream of the previously blocked user thread on the first logical processor.