Patent ID: 7568054

Claim:
A duplicate synchronization system comprising: a first system; and a second system configured to operate in synchronization with said first system, wherein said first system and said second system are connected to each other through a plurality of data link paths, said first system includes: a first memory; a first controller controlling a read/write for said first memory; and a first DMA (Direct Memory Access) engine accessing said first controller, said second system includes: a second memory; a second controller controlling a read/write for said second memory; and a second DMA engine accessing said second controller, wherein when sending a read command in which a source is indicated to any of said first controller and said second controller, each of said first DMA engine and said second DMA engine sets said source to any of said first DMA engine and said second DMA engine, said first controller reads out a data from said first memory in response to said read command, and sends said read data back to said source, and said second controller reads out a data from said second memory in response to said read command, and sends said read data back to said source.