Patent ID: 7392275

Claim:
A computer implemented method comprising: responsive to a first single instruction, identifying a first operand including four packed data elements, (r 3 , r 2 , r 1 and r 0 ), and identifying a second operand including four packed coefficients, (w 3 , w 2 , w 1 and w 0 ), generating four packed first products, (r 3 w 3 , r 2 w 2 , r 1 w 1 and r 0 w 0 ) and storing said four packed first products at a first destination identified by said first single instruction; responsive to a second single instruction, identifying a third operand including four packed data elements, (s 3 , s 2 , s 1 and s 0 ), and identifying a fourth operand including four packed coefficients, (w 7 , w 6 , W 5 and w 4 ), generating four packed second products, (s 3 w 7 , s 2 w 6 , s 1 w 5 and s 0 w 4 ) and storing said four packed second products at a second destination identified by said second single instruction; and responsive to a third single instruction, identifying a fifth operand including the four packed first products and identifying a sixth operand including the four packed second products, generating four packed sums, (s 2 w 6+ s 3 w 7 , s 0 w 4+ s 1 w 5 , r 2 w 2+ r 3 w 3 , and r 0 w 0+ r 1 w 1 ) and storing them at a third destination identified by said third single instruction.