Patent ID: 8706936

Claim:
An integrated circuit comprising: a plurality of devices; and a bus network configured to transfer messages between said plurality of devices, said bus network comprising a plurality of bus interfaces for connecting said devices to said bus network, and at least one bus connecting said plurality of bus interfaces; wherein: said bus network is configured to transfer a message specifying a target device that is connected to a target bus interface; said plurality of bus interfaces are configured to continue passing said message from bus interface to bus interface until said message is downloaded from said target bus interface by said target device; said message is associated with at least one download control flag which is transferred along with said message via said bus network; said at least one download control flag is settable to a priority state indicating that said message has passed said target bus interface at least once without said message being downloaded by said target device; and said target bus interface is configured to control selection of messages to be downloaded by said target device, with messages for which said at least one download control flag is set to said priority state having a greater probability of being selected than messages for which said at least one download control flag is not set to said priority state, wherein said bus network comprises at least two buses connecting said plurality of bus interfaces, said at least one download control flag comprises a priority flag; and on receiving multiple messages specifying the same target device from said at least two buses in a same processing cycle, said target bus interface is configured to control download arbitration between said multiple messages in dependence on said priority flag for said multiple messages.