Patent ID: 8377778

Claim:
A method of designing an integrated circuit, the method comprising: identifying a target transistor with high analog gain in the integrated circuit; designing a first transistor comprising a first threshold voltage, a first gate length and a first width; designing a second transistor comprising a second threshold voltage, a second gate length and a second width; replacing the target transistor with the first transistor and the second transistor, wherein a drain of the first transistor and a source of the second transistor are electrically coupled, and wherein a gate of the first transistor is electrically coupled to a gate of the second transistor; calculating an output analog voltage gain of the combined first and second transistor; determining an error between the calculated output analog voltage gain and a target analog voltage gain; and redesigning the first threshold voltage and a second threshold voltage to lower the error below an acceptable level, wherein after the redesigning, the first threshold voltage is higher than the second threshold voltage.