Patent ID: 7981724

Claim:
A manufacturing method for a semiconductor device embedded substrate, comprising: a first step of preparing a semiconductor device that has a semiconductor integrated circuit, a connection terminal electrically connected to the semiconductor integrated circuit, a first insulating layer configured to expose a part of the connection terminal; a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body so that an exposed portion of the connection terminal, which is exposed from the first insulating layer, faces the one surface of the support body; a third step of forming a second insulating layer on the one surface of the support body to fill at least a space portion adjoining a side surface of the semiconductor device arranged on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a third insulating layer on a surface of each of the semiconductor device and the second insulating layer, each of which is set so that the surface thereof is opposite to an exposed portion from the fourth step; a sixth step of preparing a wiring substrate which has a first wiring pattern, and fixedly mounting the wiring substrate on a surface of each of the semiconductor device and the second insulating layer, each of which is set so that the surface thereof is opposite to the exposed portion, via the third insulating layer; a seventh step of forming a first via-hole, from which the first wiring pattern is exposed, in the second insulating layer and the third insulating layer; and an eighth step of forming a second wiring pattern to be electrically connected via the first via-hole to the first wiring pattern in the second insulating layer and the third insulating layer.