Patent ID: 7792895

Claim:
A system configured to compute partial dot products for a matrix multiplication operation, the system comprising: a global memory configured to store a first source matrix, a second source matrix and a result matrix; a processing unit configured to execute a cooperative thread array, wherein the processing unit includes hardware logic configured to synchronize the threads of the cooperative thread array by pausing one or more of the threads at a specific instruction until all threads in the cooperative thread array reach the specific instruction; a local memory coupled to the processing unit and configured to store at least one tile of the first source matrix and at least one tile of the second source matrix; and a plurality of local registers coupled to the processing unit, wherein the cooperative thread array is configured to: copy a first tile from a first row of the first source matrix from the global memory to the local memory, copy a first tile from a first column of the second source matrix from the global memory to the local memory, wherein the first tile copied from first column of the second source matrix corresponds to the first tile copied from first row of the first source matrix, compute partial dot products for elements of a first tile of the result matrix based on elements of the first tile copied from the first row of the first source matrix and elements of the first tile copied from the first column of the second source matrix, and store the partial dot products for the elements of the first tile of the result matrix in the plurality of local registers, and wherein the hardware logic synchronizes the threads of the cooperative thread array after the first tile from the first row of the first source matrix and the first tile from the first column of the second source matrix are copied to the local memory but before the cooperative thread array begins computing the partial dot products for the elements of the first tile of the result matrix.