Patent ID: 7105407

Claim:
A method of fabricating a semiconductor device made up of memory cells each having a control gate formed above a floating gate, said method comprising the step of: forming a resist pattern having a group of openings disposed at a plurality of spots, respectively, on an electrically conductive film, serving as the floating gates, formed across a substrate; baking the resist pattern to thereby cause deformation due to thermal flow to occur thereto and causing the group of the openings to be linked with each other; etching a portion of the electrically conductive film, in the group of the openings linked with each other, and forming end faces of the respective floating gates, along the direction of a gate width thereof, at respective linkage parts; forming the control gate, extended in the direction of the gate width of the respective floating gates, above a portion of the electrically conductive film, defining the end faces of the respective floating gates, with an insulating film interposed therebetween; and selectively etching the electrically conductive film using the control gates as masks to thereby form the floating gate under the respective control gates.