Patent ID: 8229049

Claim:
A monitor circuit, comprising: a first delay line circuit having a plurality of delay taps for receiving data from a data channel; a second delay line circuit having a plurality of points for sampling said data received from said first delay line circuit, wherein said plurality of points comprises an input point, a middle point and an output point; a voltage control circuit for providing a control voltage to said second delay line circuit; and a data compare circuit for comparing a data value of said input point and a data value of said middle point to produce a first out-of-bounds signal, and for comparing said data value of said middle point and a data value of said output point to produce a second out-of-bounds signal, wherein said first out-of-bounds signal and said second out-of-bounds signal are used to select one of said plurality of delay taps of said first delay line circuit or to adjust said control voltage provided to said second delay line circuit.