Patent ID: 7786777

Claim:
A circuit arrangement for the provision of a clock signal with an adjustable cycle comprising: an input for connecting an oscillator; an amplifier circuit with a first input that is coupled to the input of the circuit arrangement; with a second input; with a comparator whose inputs constitute the first and second input of the amplifier circuit; and with a buffer that comprises at least a first inverter and couples an output of the comparator to an output of the amplifier circuit; an output which is connected to the output of the amplifier circuit and at which a clock signal with a duty cycle is available; a low-pass filter, an input of which is connected to the output of the amplifier circuit; and an integrator circuit, an input of which is connected to the low-pass filter and an output of which is connected to the second input of the amplifier circuit for the provision of an adjustable threshold value for controlling the duty cycle (f); wherein the integrator circuit comprises a loop filter that is connected to the output of the integrator circuit; and wherein the loop filter comprises a first capacitor that connects the output of the integrator circuit to the ground potential terminal and a series circuit comprising a resistor and a second capacitor that connect the output of the integrator circuit to the ground potential terminal.