Patent ID: 8229993

Claim:
A method for performing decimal division, the method comprising: receiving a scaled divisor and a scaled dividend into input registers; storing a subset of multiples of the scaled divisor in a plurality of multiples registers; calculating quotient digits in response to the scaled divisor and the scaled dividend, wherein each quotient digit is calculated in three clock cycles by a pipeline mechanism, wherein the pipeline mechanism includes a two cycle adder, a latching multiplexer connected to the multiples registers and the two cycle adder, a remainder register connected to the two cycle adder, remainder selection circuitry connected to the remainder register, quotient selection circuitry connected to the multiplexer, the remainder selection circuitry and the remainder register, and a quotient accumulator connected to the two cycle adder, the calculating including: selecting a new quotient digit; and calculating a new remainder, wherein input to the calculating a new remainder includes data from one or more of the multiples registers.