Patent ID: 8375196

Claim:
A data processing apparatus comprising: a vector register bank comprising a plurality of vector registers, each vector register comprising a plurality of storage cells such that said plurality of vector registers provide a matrix of storage cells, each storage cell arranged to store a data element; a vector processing unit for executing a sequence of vector instructions and having access, to the vector register bank in order to read data elements from, and write data elements to, vector registers of the vector register bank during execution of said sequence of vector instructions; responsive to a vector matrix rearrangement instruction specifying a predetermined rearrangement operation to be performed on the data elements in said matrix of storage cells, the vector processing unit being arranged to issue a set rearrangement enable signal to the vector register bank; the vector register bank having a write interface for writing data elements into the vector registers of the vector register bank, the write interface having a first input for receiving data elements generated by the vector processing unit during execution of said sequence of vector instructions, and having a second input coupled via a data rearrangement path to the matrix of storage cells via which the data elements currently stored in the matrix of storage cells are provided to the write interface in a rearranged form representing the arrangement of data elements that would be obtained by performance of said predetermined rearrangement operation; and when the rearrangement enable signal is set by the vector processing unit, the write interface being arranged to perform a write operation to the storage cells of said matrix using the data elements received at the second input, wherein said write interface comprises, for each storage cell in said matrix, multiplexer circuitry having a first input for receiving a data element generated by the vector processing unit for storage in the associated storage cell, and a second input for receiving via the data rearrangement path a data element currently stored in one of the storage cells of the matrix, said data element received via the data rearrangement path being the data element that needs to be stored in said associated storage cell to represent the outcome of said predetermined rearrangement operation.