Patent ID: 7002208

Claim:
A MOS transistor, comprising: a semiconductor substrate having a top surface; isolation regions formed in said substrate; a gate structure formed over said substrate having sidewalls disposed on both sides of said gate structure; a source region having a source lightly doped region and a source heavily doped region, wherein an impurity concentration of said source lightly doped region is lower than an impurity concentration of said source heavily doped region, each of which having an upper portion in contact with the side wall, wherein the source lightly doped region is formed below one of said sidewalls and said impurity concentration decreases as a depth from the top surface of the substrate increases, said source heavily doped region being disposed between said source lightly doped region and said isolation region, and wherein a portion of said source lightly doped region extends beneath a gate oxide of said gate structure; a drain region having a drain lightly doped region and a drain heavily doped region, wherein an impurity concentration of said drain lightly doped region is lower than an impurity concentration of said drain heavily doped region, wherein the drain lightly doped region is formed below one of said sidewalls, wherein said drain heavily doped region is disposed between said drain lightly doped region and said isolation region and wherein a portion of said drain lightly doped region extends beneath a gate oxide of said gate structure; and metallic silicide layers respectively formed on said source heavily doped regions and said drain heavily doped regions, said metallic silicide layers being in contact with said sidewalls and said isolation regions, and extending onto said isolation regions, wherein undersides of said metallic silicide layers are substantially coplanar with respective undersides of said sidewalls in contact with said top surface.