Patent ID: 8487448

Claim:
A chip package comprising: an embedded semiconductor chip; wherein the semiconductor chip has first connection pads which are electrically connected to second connection pads on a dielectric layer above the semiconductor chip; wherein the electrical connections between the first connection pads and the second connection pads are realized in the wafer assemblage; and wherein a pitch of the second connection pads is greater than a pitch of the first connection pads; wherein a layer composed of dielectric lies above the second connection pads and has vias through which metal lines running above the dielectric are electrically connected to the second connection pads, and wherein the area of a second connection pad extends both beyond the area of the via and beyond the area of the metal line in the contact region with the via; wherein the width of the via amounts to 30% to 70% of the width of the second connection pad; and wherein the width of the metal line in the contact region amounts to 130% to 200% of the width of the second connection pad.