Patent ID: 7493447

Claim:
A system for executing a sequential program, the system comprising: a NAND flash configured to store the sequential program; a processor configured to execute the sequential program; a cache configured to store instructions received from the NAND flash, the cache having a size related to the maximum offset of a conditional jump of the sequential program, the size being at least twice the maximum offset of a conditional jump of the sequential program; a cache controller configured to control the instructions stored in the cache, wherein the cache controller is further configured to maintain in the cache instructions with addresses within the range of the program counter minus the maximum offset of a conditional jump to the program counter plus the maximum offset of a conditional jump; wherein the cache controller is configured to determine, in response to a jump command received from the processor, if a target address is stored in the cache; and the cache controller is configured to delay fetching additional instructions from the NAND flash if the jump command is a backward jump command and the address is stored in the cache.