Patent ID: 8097535

Claim:
A method for fabricating an interconnect element on a substrate surface between a first metal structure and a second metal structure, comprising the steps of providing a semiconductor substrate with a pn junction formed by a first doped substrate region of a first conductivity type, and a second doped substrate region of an opposite second conductivity type; fabricating a layer structure on the semiconductor substrate, the layer structure comprising the first metal structure, which is conductively connected with the first doped substrate region, and further comprising the second metal structure, which is conductively connected with the second doped substrate region, the layer structure allowing transmission of photons with an energy suitable for creating free charge carriers in the first and second doped substrate regions; defining an interconnect surface region on the layer structure, which connects the first and second metal structures and which is designated for self-assembly of the metal interconnect element; providing an ambient environment adjacent to the interconnect surface region and suitable for allowing growth of at least one metal dendrite between the first and second metal structures; initiating and sustaining self-assembly of a third metal structure comprising at least one metal dendrite in the interconnect surface region between the first and second metal structures until the third metal structure forms the desired interconnect element, by irradiating the pn junction with photons of an energy suitable for creating free charge carriers in the first and second doped substrate regions and thus creating an electric potential difference between the first and second metal structures, which is suitable for electrolysis of metal from at least one of the first and second metal structures.