Patent ID: 7280710

Claim:
A hardware pipeline for 3D image registration, comprising: a first memory module for storing volumetric data comprising a first three dimensional image; a second memory module for storing volumetric data comprising a second three dimensional image; a third memory module for storing MH data; an address generator/first image controller; an interpolator; a second image controller; and an accumulator/MH controller, wherein each of the first, second and third memory modules are configured for computational access independently of the other two memory modules, wherein the address generator/first image controller is operable to access the first memory module for first image data and mask data, and to send first image address and control data to the first memory module, and to send interpolation data and second image address data to the interpolator and second image controller, respectively, and to send first image data to the accumulator/MH controller, wherein the second image controller is operable to receive second image data and mask data from the second memory module, and to send second image address and control data to the second memory module, and to send second image data to the accumulator/MH controller, wherein the accumulator/MH controller is operable to send MH address and control data to the MH RAM, and to send MH data to and receives MH data from the third memory module, wherein the interpolator is operable to send interpolation weights to the accumulator/MH controller.