Patent ID: 8502576

Claim:
A charge pump (CP) circuit, comprising: a main CP, comprising: a first complementary switch pair, configured to be selectively turned on according to an UP signal and a complementary UP signal; a second complementary switch pair, configured to be selectively turned on according to a DOWN signal and a complementary DOWN signal; a first current source, coupled between a power supply and the first complementary switch pair; a second current source, coupled between a common node and the second complementary switch pair; and a unity gain buffer amplifier, coupled between the first complementary switch pair and the second complementary switch pair; a replica circuit, configured to generate a first voltage, wherein the first voltage is in response to current values of the first current source and the second current source of the main CP; and a tracking circuit, configured to adjust the current values of the first current source and the second current source of the main CP according to the first voltage and a second voltage, wherein the second voltage is in response to a voltage of an output node of the main CP, wherein the tracking circuit comprises: an n-Mental-Oxide-Semiconductor (NMOS) transistor, having a source coupled to the common node and a gate connected to a drain, the drain being configured to receive a first bias current; a p-Mental-Oxide-Semiconductor (PMOS) transistor, having a source coupled to the power supply and a gate connected to a drain, the drain being configured to receive a second bias current; a first operational amplifier, having a first input end for receiving the first voltage, a second input end for receiving the second voltage, and an output end connected to the gate of the PMOS transistor; and a second operational amplifier, having a first input end for receiving the first voltage, a second input end for receiving the second voltage, and an output end connected to the gate of the NMOS transistor.