Patent ID: 7701007

Claim:
A thin film transistor (TFT) for a displaying device, comprising: a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region formed on the gate insulation layer and disposed above the gate electrode; a doped a-Si region formed on the a-Si region; a source metal region and a drain metal region, separately formed on a top surface of the doped a-Si region, each of the source and drain metal regions being disposed within the top surface of the doped a-Si region as an island, wherein the source metal region and drain metal region are separated from the a-Si region by the doped a-Si region, and a total area defined by the sum of a bottom area of the source metal region added to a bottom area of the drain metal region, is smaller than a bottom area of the a-Si region; a data line (DL) metal region formed on the gate insulation layer and spaced apart from the source metal region; a passivation layer formed on the gate insulation layer for covering the source metal region, the drain metal region and the DL metal region, the passivation layer having a first via, a second via and a third via for exposing partial surfaces of the drain metal region, partial surfaces of the source metal region and the DL metal region, respectively; and a conductive layer formed on the passivation layer for filling the first via, the second via and the third via, so that the DL metal region and the source metal region are electrically connected.