Patent ID: 7301196

Claim:
An integrated circuit comprising a nonvolatile memory cell, the integrated circuit comprising: a semiconductor substrate; a first dielectric region on the semiconductor substrate; a first conductive gate on the first dielectric region, the first conductive gate being part of the memory cell; a second dielectric region on the semiconductor substrate; a conductive floating gate on the second dielectric region, the floating gate being part of the memory cell; a dielectric layer comprising a continuous feature overlying the floating gate and also overlying the first conductive gate; and a second conductive gate overlying the continuous feature of the dielectric layer and also overlying the floating gate but not overlying the first conductive gate, wherein the continuous features of the dielectric layer is present between the floating gate and the second conductive gate, the second conductive gate being part of the memory cell, the second conductive gate being insulated from the first conductive gate; wherein the memory cell further comprises two source/drain regions of a first conductivity type in the semiconductor substrate, and a channel region of a second conductivity type in the semiconductor substrate, the channel region extending under the first conductive gate and the floating gate between the two source/drain regions.