Patent ID: 8533648

Claim:
A method for providing clock-gating for a circuit, comprising: using a processor to receive a description of the circuit, wherein the circuit includes a plurality of clock-gated memory elements and a plurality of clocked memory elements; identifying a sender memory element in the plurality of clocked memory elements by identifying a sender path from an output of the sender memory element to a data input for a seed memory element, wherein the sender path does not pass through other clocked memory elements in the circuit; identifying an enable-generating memory element in the plurality of clocked memory elements by identifying an enable-signal path from an output of the enable-generating memory element to an enable signal which is used to gate a clock signal input for the seed memory element; providing clock-gating for the identified sender memory element by generating an enable signal for the sender memory element using a data input for the enable-generating memory element; and gating a clock signal for the sender memory element using the enable signal for the sender memory element.