Patent ID: 8316206

Claim:
A memory control module, comprising: a format module in communication with a memory array, wherein the memory array comprises B memory blocks configured to store user data, wherein each of the B memory blocks of the memory array comprises P physical pages and Q logical pages, and wherein the format module is configured to in each of the B memory blocks, i) select X predetermined locations, and ii) write pilot data into the X predetermined locations, wherein read-back pilot signals are generated based on reading the pilot data written into the X predetermined locations, wherein the X predetermined locations are distributed in each of the B memory blocks according to a first predetermined pattern, wherein the X predetermined locations according to the first predetermined pattern are selected based on i) a page structure of the P physical pages and ii) a page structure of the Q logical pages, wherein the page structure of each given page of the P physical pages and the Q logical pages includes a total number of memory cells in the given page, a number of bits per memory cell, a first number of memory cells associated with a data portion of the given page, and a second number of memory cells associated with an ECC/overhead portion of the given page, where the total number of memory cells is a sum of the first number of memory cells and the second number of memory cells, wherein B, P, Q, and X are integers greater than or equal to 1, and wherein the pilot data includes a second predetermined pattern that is different than the user data; and a signal processing module configured to, for each of the B memory blocks, compare the pilot data written into the X predetermined locations to the read-back pilot signals, and determine, based on the comparison, variations between the pilot data written into the X predetermined locations and the read-back pilot signals.