Patent ID: 7992069

Claim:
An error correction coding apparatus which implements error correction coding for every predetermined number of frames and in a predetermined frame format, characterized in that said apparatus comprises: a subframe division means for dividing transmission information sequences in n subframes (n is an arbitrary natural number) into n1 subframes (n1 is a natural number smaller than n) and n2 subframes (n2 is a natural number which satisfies n1+n2=n); a first error correction code generating means for block-coding said n1 subframes for every m1 subframes (m1 is a factor of n1) so as to generate a first error correction code, and for adding the generated first error correction code as redundant information; and a second error correction code generating means for block-coding said n2 subframes for every m2 subframes (m2 is a factor of n2) so as to generate a second error correction code, and for adding the generated second error correction code as redundant information.