Patent ID: 7081676

Claim:
An electrical contact to a region of a silicon-containing substrate comprising: a substrate having an exposed region of a silicon-containing semiconductor material, said silicon-containing semiconductor material being doped with an impurity to provide carriers of holes, electrons or both holes and electrons; and a first layer of CoXSi 2 , wherein X is an alloying additive selected from the group consisting of C, Al, Sc, Ti, V, Cr, Mn, Fe, Cu, Ge, Y, Zr, Nb, Mo, Ru, Rh, Pd, In, Sn, La, Hf, Ta, W, Re, Ir, Pt, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof, said alloying additive being present in said first layer in an amount of from about 0.01 to about 50 atomic %, said first layer and said silicon-containing semiconductor material forming an interface having a predetermined roughness and being substantially free of Co silicide spikes descending into said silicon-containing semiconductor material.