Patent ID: 8522182

Claim:
A non-transitory computer-readable storage medium storing machine executable instructions for a processor, wherein execution of the instructions cause the processor to: load unit timing data from a timing simulation of an integrated circuit into a memory, wherein the unit timing data is descriptive of the timing at the upper hierarchy unit level, and wherein the unit comprises a plurality of macros; load a selection of a unit timing path through the integrated circuit from the memory; load macro timing data from the timing simulation into the memory, wherein the macro timing data is descriptive of timing within each of the plurality of macros during the simulation; replace at least a first portion of a unit timing end point report with the macro timing data along the unit timing path, wherein the unit timing report comprises the unit timing data, wherein the macro timing data replaces at least a first portion of the unit timing data, and wherein at least a second portion of the unit end point report is not replaced with the macro timing data; compute arrival times, slacks, and slews for the unit timing path using the replaced unit tithing data; compute path statistics in accordance with the arrival times, slacks and slews; and generate an end point report for the unit timing path including the path statistics.