Patent ID: 7649604

Claim:
A liquid crystal display device, comprising: first and second substrates; a liquid crystal layer formed between the first and second substrates; a plurality of pixel regions defined in a matrix configuration on the first substrate; a plurality of gate lines extending along a first direction on the first substrate and dividing each of the pixel regions into first and second sub-pixel regions that are adjacent to each other along a second direction substantially perpendicular to the first direction; a plurality of data lines extending along the second direction and crossing the gate lines; a plurality of common and pixel electrodes for generating an in-plane electric field in the first and second sub-pixel regions, the common and pixel electrodes being disposed to be substantially parallel to the gate line; common electrode connection lines connected electrically to the common electrodes, the common electrode connection lines being parallel to the data line; common lines connected to the common electrode connection lines, the common line being parallel to the gate line; pixel electrode lines connected electrically to the pixel electrodes, the pixel electrode lines being parallel to the data line; and a switching device formed at the crossing the gate and data lines and driving the first and second sub-pixel regions, wherein the switching device includes a gate electrode, a semiconductor layer, and source and drain electrodes, and the drain electrode includes a second drain electrode connected with the pixel electrodes of the first sub-pixel region and a third drain electrode connected with the pixel electrodes of the second sub-pixel region, the source electrode including first and second source electrodes extruded from the data line and the drain electrode including a first drain electrode disposed between the first and the second source electrodes over the gate electrode and the second and third drain electrodes branched from the first drain electrode to the first and second sub-pixel regions through the gate electrode, wherein the common electrode connection lines are partially overlapped with the pixel electrode lines at both sides of the first sub-pixel region and the second sub-pixel region to form a first storage capacitor at the first sub-pixel region and a second storage capacitor at the second sub-pixel region and a common electrode connection line adjacent to the data line is extended from a pixel electrode line toward the data line so that the side of the common electrode connection line is facing with the side of the data line.