Patent ID: 8110454

Claim:
A method of forming a drain extended transistor, comprising: forming a first well region of a first n-type or p-type conductivity; forming a second well region of second n-type or p-type conductivity, opposite to the first conductivity type; forming a source region of the second conductivity type in the first well region; forming a drain region of the second conductivity type in the second well region; forming a gate oxide layer over portions of the first and second well regions; forming a gate electrode over the gate oxide layer; and forming a well tap in contact with the second well region at a position laterally located between the drain region and an interface of the first and second well regions; whereby, when the transistor is biased into an off state, a voltage at the well tap will be determined by the location of the well tap relative to a voltage gradient created in the second well region between the drain region and the interface.