Patent ID: 7965118

Claim:
A method for achieving a desired duty cycle on an output of a PLL comprising: generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle; receiving, via a low pass filter, the single ended clock signal; generating, via the low pass filter, a single ended measurement of the duty cycle of the single ended clock signal; receiving, via at least one gate terminal of a second differential amplifier different than the limiting differential amplifier, the single ended measurement of the duty cycle of the single ended clock signal; generating, using the second differential amplifier, a differential bias current signal in response to the single ended measurement of the duty cycle of the single ended clock signal; and correcting the duty cycle of the single ended clock signal to a desired duty cycle by via applying the differential bias current signal from the second differential amplifier to the limiting differential amplifier.