Patent ID: 7745943

Claim:
The A microelectronic package comprising: a substrate having a top surface and a bottom surface; a microelectronic element overlying the top surface of said substrate; a plurality of conductive traces extending along at least one of the top or bottom surfaces of said substrate and conductively connected with said microelectronic element; a plurality of substantially rigid frustoconical conductive posts exposed at the bottom surface of said substrate, at least some of said posts having bases directly connected with said traces, said conductive traces and said posts being formed integrally by subtractively patterning a layered metal structure into said conductive traces and said posts, said bases defining maximum dimensions of said conductive posts in at least one direction in which said traces extend; and an encapsulating mold material in contact with said microelectronic element and overlying the top surface of said substrate, wherein said encapsulating mold material extends to an outer edge of said substrate and defines outermost edges of said microelectronic package.