Patent ID: 8271255

Claim:
A computer-implemented method of calculating a delay of a gate based on a crosstalk effect due to capacitive coupling in a digital integrated circuit (IC), the method comprising: a generating using a computer a gate model of a Thevenin equivalent circuit with regard to a gate in the digital IC under a condition that there is no noise current source, and calculating an output waveform with regard to an input voltage; generating using the computer an output resistance library based on the input voltage and an output voltage of the gate wherein an output resistance of the gate is measured by using a function of the input voltage and the output voltage of the gate and is divided into a plurality of regions by boundaries identifying characteristics of the output resistance, wherein the output resistance library of the gate includes a representative resistance value for each of the plurality of the regions and the boundaries for dividing the plurality of the regions; c generating using the computer a linear time-varying output resistance model with regard to the gate by using the output waveform and the output resistance library; d generating using the computer a modified Thevenin equivalent gate model of the gate under the condition that there is no noise current source by using the linear time-varying output resistance model, and calculating an output waveform that sums a waveform output by using the modified Thevenin equivalent gate model and an output waveform calculated in response to the noise current source with regard to the linear time-varying output resistance model; and e repeatedly applying the output waveform calculated using the computer in operation d to operation c, if the output waveform calculated in operation d does not converge; and, if the output waveform calculated in operation d converges, calculating the delay of the gate by using the converged output waveform.