Patent ID: 8525356

Claim:
A wiring substrate comprising: a plurality of wiring layers; a plurality of insulating layers; an alignment mark embedded in an outermost insulating layer of the plurality of insulating layers, the outermost insulating layer being a surface of the wiring substrate; a pad embedded in the outermost insulating layer of the plurality of insulating layers; and a via forming a part of the wiring layers, the via being provided in the outermost insulating layer, the via being connected to a back surface of the pad, wherein a front face of the alignment mark is exposed on a surface of the outermost insulating layer, side and back faces of the alignment mark are coated by the outermost insulating layer, a front face of the pad is exposed on the surface of the outermost insulating layer, side and back faces of the pad are coated by the outermost insulating layer, and the front face of the alignment mark and the front face of the pad are roughened.