Patent ID: 7774658

Claim:
A translation look-aside buffer operable in a first mode of operation to translate a first set of elements to a second set of elements and operable in a second mode of operation to check for errors in entries of the translation look-aside buffer, the translation look-aside buffer comprising: a content addressable memory operable to receive an element of the first set of elements and control a first set of word lines; a random access memory operable to store the second set of elements; a first logic circuit operable to control the content addressable memory during the first mode of operation; a second logic circuit operable to control a second set of word lines during the second mode of operation: a selector operable to couple the first set of word lines to the random access memory during the first mode of operation and to couple the second set of word lines to the random access memory during the second mode of operation and thereby access an entry of the random access memory; and an error checking circuit operable to detect an error in the accessed entry of the random access memory; wherein, during the second mode of operation, the second logic circuit is operable to purge a translation look-aside buffer entry corresponding to the accessed entry of the random access memory if an error is detected in the accessed entry of the random access memory.