Patent ID: 8258925

Claim:
A frequency synthesizer applied to a first band transceiver and a second band transceiver, the first band transceiver being a first radio frequency identification reader, and the second band transceiver being a second radio frequency identification reader, the frequency synthesizer comprising: a phase-locked loop module, comprising a single voltage controlled oscillator which generates a primary clock signal with frequency ranging from 4.8 GHz to 5 GHz; a first frequency divider, disposed between the phase-locked loop module and the first band transceiver and coupled to an output of the single voltage controlled oscillator, for frequency-dividing the primary clock signal into a first clock signal with a first frequency with frequency range from 2.4 GHz to 2.5 GHz for the first band transceiver; and a second frequency divider, coupled to an output of the first frequency divider, for frequency-dividing the first clock signal into a second clock signal with a second frequency with frequency range from 860 MHz to 960 MHz for the second band transceiver, the second frequency being lower than the first frequency, wherein the second frequency divider comprises a 3/2 frequency conversion part for performing 3/2 frequency conversion, a high-pass filter and a divide-by-4 frequency-dividing circuit; a third frequency divider, coupled to an output of the second frequency divider, for frequency-dividing the second clock signal into a third clock signal with a third frequency lower than the second frequency; and a fourth frequency divider, coupled to the output of the second frequency divider, for frequency-dividing the second clock signal into a fourth clock signal with a fourth frequency lower than the second frequency, the fourth frequency being different from the third frequency; wherein the third frequency of the third clock signal and the fourth frequency of the fourth clock signal cover 13.56 MHz and 125 kHz, respectively.