Patent ID: 8906737

Claim:
A method for manufacturing a transistor comprising an oxide semiconductor layer, at least one of a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gallium oxide layer, a gate electrode, and a protective insulating film, the method comprising the steps of: forming the one of the source electrode and the drain electrode over the oxide semiconductor layer; forming the gallium oxide layer over the one of the source electrode and the drain electrode, the gallium oxide layer being on and in contact with the oxide semiconductor layer; forming the gate electrode over the gallium oxide layer; forming the protective insulating film over the gallium oxide layer and the gate electrode; forming a resist mask over the protective insulating film; and forming a contact hole by dry etching the protective insulating film and the gallium oxide layer using the resist mask, wherein a width of the contact hole in the gallium oxide layer is smaller than a width of the contact hole in the protective insulating film, and wherein the contact hole includes a stepped shape.