Patent ID: 6907539

Claim:
An apparatus comprising: a first input configured to receive a clock signal; a second input configured to receive a data signal having a first setup/hold window with respect to a transition of said clock signal; a first circuit configured to (i) receive said data signal from said second input and (ii) present a delayed data signal having a second setup/hold window with respect to said transition of said clock signal, wherein (i) a difference between said first setup/hold window and said second setup/hold window is configured in response to one or more of a plurality of delay times, (ii) each of said plurality of delay times is less than a period of said clock signal and (iii) said plurality of delay times provides a user configurable delay of said second setup/hold window relative to said transition of said clock signal; and a second circuit configured to receive said delayed data signal from said first circuit and said clock signal from said first input.