Patent ID: 7191257

Claim:
A system, comprising: data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, wherein a subset of said plurality of addressable locations is configured as a data event buffer; a direct memory access (DMA) transfer engine coupled to said data capture logic and to said system memory and configured to perform a DMA transfer operation of said captured data events from said data capture logic to a region of said data event buffer as portions of said captured data events become available from said data capture logic; and an application configured to retrieve captured data events from said region of said data event buffer without said DMA transfer operation of said captured data events from said data capture logic to said region being stopped, such that said application is configured to display said retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on said nondeterministic data bus.