Patent ID: 7195965

Claim:
A method for fabricating LDMOS or bipolar integrated circuits having transistor and diode curved junction radii of one micron or less in a silicon substrate wafer of a first conductivity type, wherein said diodes include multi-fingered power diodes, comprising the steps of: growing screen oxide on said wafer about 20 to 30 nm thick for surface protection; depositing a layer of photoresist on said wafer in a thickness suitable for shielding against ion implant, and soft-baking said photoresist; aligning a mask to said wafer defining the extent of the deep well of the opposite conductivity, for high voltage operation; exposing the masked photoresist to ultraviolet light, and baking said photoresist; developing said photoresist to pattern it by removing the portions exposed to said light; hard-baking said photoresist; implanting at high energy and medium dose ions of the opposite conductivity type; stripping said patterned photoresist layer; and diffusing said implanted ions to define the outline of said well of opposite conductivity and to create a region of light doping and thus high resistivity for the curved junction portions of the intended devices.