Patent ID: 8407405

Claim:
A semiconductor storage device, comprising: a plurality of flash memories; and a controller for the flash memories, wherein each of the flash memories includes a data cache operable to hold data for at least one record page in writing, each of the flash memories includes a plurality of erasure blocks each having a plurality of record pages, each of the record pages is classified into a first record page and a second record page of which write time is longer than a write time of the first record page, and the controller for the flash memories is configured to: register alignment information on the plurality of record pages divide the plurality of flash memories into at least two groups; perform write control for each record page by interleaving data between the groups; determine whether a page to be written data is the first record page or the second record page based on the alignment information; and when it is determined that the page to be written data is the first record page, after a lapse of a first predetermined time from start of writing data of one of the groups, the controller starts writing data of another one of the groups, and when it is determined that the page to be written data is the second record page, after a lapse of a second predetermined time being longer than the first predetermined time from start of writing data of one of the groups, the controller starts writing data of another one of the groups.