Patent ID: 7541870

Claim:
An LNA (Low Noise Amplifier) circuitry, the circuitry comprising: a differential input that corresponds to a first node of a first capacitor and a first node of a second capacitor; first and second n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs); third and fourth N-MOSFETs, wherein: each of a gate of the third N-MOSFET and a gate of the fourth N-MOSFET is connected to a bias voltage; a drain of the first N-MOSFET couples to a source of the third N-MOSFET; and a drain of the second N-MOSFET couples to a source of the fourth N-MOSFET; a third capacitor having a first node coupled to a second node of the first capacitor and having a second node coupled to a gate of the first N-MOSFET; a fourth capacitor having a first node coupled to a second node of the second capacitor and having a second node coupled to a gate of the second N-MOSFET; and fifth and sixth N-MOSFETs, wherein: a drain of the fifth N-MOSFET couples to a source of the first N-MOSFET; a drain of the sixth N-MOSFET couples to a source of the second N-MOSFET; and each of the fifth N-MOSFET and the sixth N-MOSFET is implemented in a tri-well configuration such that each of a source of the fifth N-MOSFET and a source of the sixth N-MOSFET is connected to the substrate of the circuitry.