Patent ID: 8183691

Claim:
A semiconductor device, comprising: a semiconductor substrate; an isolation portion formed over the semiconductor substrate; a plurality of semiconductor regions formed in the semiconductor substrate, each surrounded with the isolation portion; a plurality of first wirings formed over the semiconductor regions; a plurality of first dummy wirings formed of a same layer as that of the first wirings; a plurality of second wirings formed over the first wirings; a plurality of second dummy wirings formed of a same layer as that of the second wirings; and a plurality of pads formed over the second wirings and the second dummy wirings, wherein the first dummy wirings and the second dummy wirings are in a floating state, and wherein a respective one of the semiconductor regions, a respective one of the first wirings, a respective one of the first dummy wirings, a respective one of the second wirings and a respective one of the second dummy wirings are formed under each of the pads in a plan view.