Patent ID: 7259089

Claim:
A semiconductor device manufacturing method comprising the steps of: laminating a first insulation film and a second insulation film on a substrate provided with a first wiring, to form an insulation film; sequentially laminating a first mask layer, a second mask layer, and a third mask layer on said insulation film; forming a wiring groove pattern for processing a wiring groove in said third mask layer; selectively processing into a tapered shape said third mask layer formed in the state of projecting to the inside of said wiring groove pattern; forming a contact hole pattern for forming a contact hole in said second mask layer and said first mask layer, and removing said tapered shape portion of said third mask layer; and forming a wiring groove pattern in said second mask layer and said first mask layer by etching using said third mask layer as an etching mask, forming a wiring groove in said second insulation film, and forming a contact hole in said insulation film by etching using said second mask layer and said first mask layer as an etching mask.