Patent ID: 7902898

Claim:
A delay circuit, comprising: a plurality of current sources; a plurality of switches each for receiving an enable signal to activate and convey one of the current sources; a transistor switch activated for pulling down voltage of an operating node coupled to the switches; a charging unit for providing an operating voltage for the operating node based on one of the current sources when the transistor switch being deactivated and one of the switches being activated to convey one of the current sources to the charging unit; a comparator for comparing the operating voltage with a reference voltage; and a tri-state logic gate having a logic input and three logic outputs each for outputting the enable signal to activate one of the switches, the tri-state logic gate further comprising: a first pull-up unit coupled to the logic input, for generating a low-level signal when the logic input is at low level; a first inverter coupled to a first of the logic outputs, for converting the low-level signal from the first pull-up unit into a high-level signal as the enable signal; a first pull-down unit coupled to the logic input, for generating a low-level signal when the logic input is floated or at low level; a second pull-up unit coupled to the logic input, for generating a high-level signal when the logic input is floated or at high level; a second inverter for converting the high-level signal from the second pull-up unit into a low-level signal; and a logic unit coupled to a second of the logic outputs, for performing NAND operation of the low-level signals from the first pull-down unit and the second inverter to generate a high-level signal as the enable signal.