Patent ID: 7539069

Claim:
A semiconductor memory device comprising: a memory cell including a floating body in an electrically floating state and storing data according to number of majority carries in the floating body; a first bit line and a second bit line connected to the memory cell and transmitting data with reversed polarities from each other; a first sense node and a second sense node transmitting the data on the first bit line and the data on the second bit line, respectively; a first transfer gate provided between the first bit line and the first sense node; a second transfer gate provided between the second bit line and the second sense node; a latch circuit provided between the first sense node and the second sense node; a write signal line activated when the data is written or written back to the memory cell; and a gate circuit connecting the write signal line to the first bit line and the first sense node to the second bit line, or connecting the write signal line to the second bit line and the second sense node to the first bit line, when the data is written or written back to the memory cell.