Patent ID: 6946886

Claim:
A device comprising: a receiving shift register for receiving input serial data synchronously with a communication clock signal; a reception completion determination means coupled to the receiving shift register, the reception completion determination means for also receiving the communication clock signal and for outputting a reception completion signal when detecting that the receiving shift register has received a predetermined number of bits of the serial data based on the communication clock signal; a pulse-signal generation means for generating a timing pulse signal, which comprises only a predetermined number of timing pulses required for processing the input serial data, in accordance with generation of the reception completion signal by the reception completion determination means; and a data processing means for processing the input serial data synchronously with the timing pulse signal, wherein the reception completion determination means includes a counter for counting a number of input pulses included in the communication clock signal, and for outputting the reception completion signal when a count value of the counter reaches a predetermined number.