Patent ID: 8451671

Claim:
A multiplexing circuit comprising: a plurality of first circuits; and a second circuit coupled to outputs of the plurality of first circuits; wherein a first circuit of the plurality of first circuits comprises a first sub-circuit and a second sub-circuit both coupled to the second circuit and is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output; after the first circuit is selected, the clock signal, the first sub-circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; or the second sub-circuit is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line; and the first data logic level differs from the second data logic level and the first output logic level differs from the second output logic level.