Patent ID: 7061280

Claim:
A signal detection circuit, comprising: first and second power supply terminals; first and second input terminals; a first output terminal; a first resistor coupled between the first input terminal and a first level-shifted input signal node; a first transistor having a drain coupled to the first level-shifted input signal node, a gate coupled to a common node, and a source coupled to the first power supply terminal; a second resistor coupled between the second input terminal and a second level-shifted input signal node; a second transistor having a drain coupled to the second level-shifted input signal node, a gate coupled to the common node, and a source coupled to the first power supply terminal; a third resistor coupled between the first input terminal and the common node; a fourth resistor coupled between the second input terminal and the common node; a third transistor having a gate and a drain coupled to the common node and a source coupled to the first power supply terminal; a first voltage source coupled between the common node and a first threshold node; a second voltage source coupled between the common node and a second threshold node; and a first comparator comprising: a fourth transistor having a drain coupled to a first node, a gate coupled to the first threshold node, and a source coupled to the first power supply terminal; a fifth transistor having a drain coupled to the first node, a gate coupled to the second threshold node, and a source coupled to the first power supply terminal; a sixth transistor having a gate and a drain coupled to the first node, and a source coupled to the second power supply terminal; a seventh transistor having a drain coupled to the first output terminal, a gate coupled to the first node, and a source coupled to the second power supply terminal; an eighth transistor having a drain coupled to the first output terminal, a gate coupled to the first level-shifted input signal node, and a source coupled to the first power supply terminal; and a ninth transistor having a drain coupled to the first output terminal, a gate coupled to the second level-shifted input signal node, and a source coupled to the first power supply terminal.