Patent ID: 8482503

Claim:
A liquid crystal display comprising: a liquid crystal display panel including a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of liquid crystal cells arranged at each crossing of the data lines and the gate lines in a matrix format; and a timing controller that supplies digital video data and a plurality of data timing control signals to a data drive circuit, and a plurality of gate timing control signals to a gate drive circuit, the gate driving circuit is dividedly attached between a first side and a second side of the liquid crystal display panel; wherein the plurality of gate timing control signals include a plurality of first gate line timing control signals for controlling a driving of the plurality of liquid crystal cells of the liquid crystal display panel in a sequential direction during a first frame period and a plurality of second gate line timing control signals for controlling a driving of the plurality of liquid crystal cells of the liquid crystal display panel in both a reverse sequential direction and in the sequential direction during a second frame period, wherein the data drive circuit supplies a data voltage to the plurality of data lines to the plurality of liquid crystal cells, wherein the gate drive circuit supplies a gate pulse to each of the plurality of gate lines to the plurality of liquid crystal cells, respectively, while a driving direction of the plurality of liquid crystal cells changes in response to a first and a second scan direction signals of the plurality of first and the second gate line timing control signals, respectively, wherein the gate drive circuit supplies the gate pulse to each of the plurality of gate lines in the sequential direction in response to the first scan direction signal to shift the gate pulse to the next adjacent gate line sequentially during the first frame period, wherein the gate drive circuit supplies the gate pulse to each of the plurality of gate lines in the sequential direction in response to the second scan direction signal while shifting the gate pulse by n (n is an integer) gate lines during the second frame period, and supplies the gate pulse to each of the plurality of gate lines in the reverse sequential direction in response to the second scan direction signal while shifting the gate pulse by m (m is an integer) gate lines during the second frame period, wherein the plurality of second gate line timing control signals comprises a gate shift clock signal which includes multiple pulses within a horizontal period, and wherein the gate drive circuit shifts the gate pulse to a non-adjacent gate line during the second frame period, a shift corresponding to the number of multiple pulses.