Patent ID: 8605489

Claim:
A memory device, comprising: one or more dynamic memory cells, each of the memory cells having a corresponding bit line and a corresponding word line connected thereto for individually accessing the memory cells; a word line circuit coupled with at least one word line; a bit line circuit coupled with at least one bit line; at least one control circuit coupled with the bit and word line circuits, the control circuit being operative, via the bit line circuit, the word line circuit, and the bit and word lines, to cause state information to be stored in the memory cells; and at least one switching element operative to selectively connect the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal; wherein the control circuit is operative to generate the at least one control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.