Patent ID: 7325021

Claim:
A dual-tapped buffer ladder comprising: a pair of D-type flip flops having D and L inputs; a plurality of cascaded upper buffers having a predetermined delay d 1 and respective output taps; a plurality of cascaded lower buffers having a predetermined delay d 2 , and respective output taps, wherein d 1 ≠d 2 ; a first one of the pair of D-type flip flops having its D and L inputs connected to a respective output tap of the upper buffer and a respective output tap of the lower buffer; a second one of the pair of D-type flip flops having its D and L inputs connected to a respective output tap of one of the lower buffers and a respective output of one of the upper buffers; a common clock input connected to an input of the first buffers of both the plurality of cascaded upper buffers and the plurality of cascaded lower buffers; wherein a delay difference between the cascaded upper buffers n*d 1 and cascaded lower buffers n*d 2 changes along different positions of the ladder circuit.