Patent ID: 7852121

Claim:
A domino logic circuit comprising: an input circuit configured to precharge a dynamic node at a first phase of a clock signal and configured to determine a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal; and an output circuit coupled between an output node and the dynamic node, the output circuit being configured to determine a logic level of the output node in response to the clock signal and the logic level of the dynamic node and to maintain the logic level of the output node while the logic evaluation is performed, wherein the output circuit comprises: a cut-off transistor having a first terminal coupled to the dynamic node, a second terminal coupled to an intermediate node, and a gate terminal receiving the clock signal, and a first transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the dynamic node; a second transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the intermediate node, and a gate terminal coupled to the output node; a third transistor having a first terminal coupled to the output node, a second terminal coupled to a ground voltage, and a gate terminal coupled to the intermediate node; and a fourth transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the intermediate node.