Patent ID: 7355206

Claim:
A thin film transistor array panel comprising: an insulating substrate including edges; a plurality of gate lines formed on the insulating substrate and including gate pads, wherein a first edge of the insulating substrate is nearest from the gate pads among the edges of the insulating substrate; a gate insulating layer formed on the gate lines; a semiconductor layer formed on the gate insulating layer; a plurality of data lines formed at least in part on the semiconductor layer and including data pads, wherein a second edge of the insulating substrate is nearest from the data pads among the edges of the insulating substrate; a plurality of drain electrodes formed at least in part on the semiconductor layer; a plurality of pixel electrodes connected to the drain electrodes; and a plurality of discharging units, each of the discharging units located between the first edge and the gate pad, or between the second edge and the data pad.