Patent ID: 7472051

Claim:
A fault-robust microcontroller, comprising: a central processing unit including registers and an arithmetic logic unit; a system bus and one or more functional parts comprising interfaces and peripherals; a fault processing unit configured to perform validation of operations of said central processing unit; and an interface between said central processing unit and said fault processing unit, wherein: said fault processing unit is external and different with respect to said central processing unit, said fault processing unit comprises at least one module configured to detect, during operation of said central processing unit, faults causing differences between said central processing unit and said fault processing unit, said fault processing unit configurable by a failure modes and effects analysis performed as part of a design and verification procedure of said microcontroller, said fault processing unit differing from said central processing unit in that said fault processing unit includes one or more modules configured to perform data shadowing operations and arithmetic logic unit integrity checking operations applied to said central processing unit, wherein said one or more modules are reduced with respect to said registers and said arithmetic logic unit of said central processing unit by covering a reduced set of operations of an integer core of said central processing unit selected by said failure modes and effects analysis, said reduced set of operations included in an arithmetic logic unit module representing a reduced copy of said integer core, and by operating with coded data values from a coded copy of shadowed registers of said registers of said central processing unit, said coded data values having a lesser number of bits than said shadowed registers, said coded copy of shadowed registers obtained in a shadow register module, and said interface between said central processing unit and said fault processing unit being a dedicated bus connected only between said fault processing unit and said integer core of said central processing unit, said shadow register module and said arithmetic logic unit module being adapted to use said interface to access said integer core of said central processing unit at least by accessing an arithmetic logic unit write port of said central processing unit.