Patent ID: 8707220

Claim:
A method of forming an integrated circuit, comprising the steps of: executing a lot flow control program on a first computer system, said lot flow control program performing the steps of: confirming that a number of wafers in a first partial lot is less than a capacity of wafer carriers used by process tools for a first plurality of sequential process steps; identifying values of process parameters of said first partial lot for said first plurality of sequential process steps; and examining lots in work in process (WIP) upstream of said first plurality of sequential process steps and identifying a second partial lot with values of said process parameters which are compatible with said values of said process parameters of said first partial lot; combining said wafers of said first partial lot and said second partial lot in a first wafer carrier; and iterating through each instant process step of said first plurality of said sequential process steps, wherein each iteration comprises the steps of: processing said wafers of said first partial lot and said second partial lot through said instant process step; placing said wafers of said first partial lot and said second partial lot into a same wafer carrier as each said wafer completes said instant process step; and executing a multi-lot verification program on a second computer system, said multi-lot verification program performing the steps of: determining if all of said wafers in said first partial lot and said second partial lot have completed said instant process step; determining if any of said wafers in said first partial lot and said second partial lot are on hold; and determining if all of said wafers in said first partial lot and said second partial lot are in said same wafer carrier.