Patent ID: 7661050

Claim:
A method for permitting the verification of Built In Self Test (BIST) structures within an integrated circuit of a logical interface group of circuits having an output, comprising: determining that at least one node of the integrated circuit comprises a point of equivalence wherein the output of the logical interface group comprises at least one fence gating signal and one or more interface signals; building two ternary models with a first ternary model comprising a wrapper schematic including a Design Under Test (DUT) along with a Model 1 testbench driver and a second ternary model comprising the wrapper schematic, the DUT and a Model 2 testbench driver; building a composite equivalence model which is a union of the first ternary model and the second ternary model wherein all interfaces specified in the first ternary model are driven using the Model 1 testbench driver and all interfaces specified in the second ternary model are driven using the Model 2 testbench driver and any interface not specified in either the Model 1 testbench or the Model 2 testbench driver is driven identically in both the first ternary model and the second ternary model; and identifying nodes in the DUT to serve as points of equivalence which are asserted to be mathematically equivalent.