Patent ID: 7725899

Claim:
An apparatus that provides direct read and write communications between lock step processors, wherein two or more processors operate in a lock step mode, wherein each of the two or more processors comprises a processor logic to execute a code sequence, and wherein an identical code sequence is executed by the processor logic of each of the two or more processors, the apparatus, comprising: a lock step logic block operable to allow each of the two or more processors to read data from and write data to each of the other two or more processors, the lock step logic block, comprising: a processor-specific resource referenced by the code sequence, and a multiplexer coupled to a write side of each of the two or more processors, wherein the multiplexer is controlled to write data based on an identification of the processor-specific resource, the identification of the processor-specific resource determining which processor provides the data, wherein the two or more processors operating in the lock step mode can perform inter-processor read and write operations without resorting to load and store instructions that cause a loss of lock step.