Patent ID: 7332927

Claim:
A system for testing an integrated circuit chip, comprising: means for forming a liquid polyalphaolefine layer on a bottom surface of said integrated circuit chip, a top surface of said integrated circuit chip having signal and power pads and said bottom surface of said integrated circuit having no signal or power pads; means for placing a surface of a heat sink into physical contact with said bottom surface of said polyalphaolefine layer; means for electrically coupling said integrated circuit chip to a tester; means for electrically testing said integrated circuit chip; means for electrically de-coupling said integrated circuit chip from said tester; means for removing said heat sink from contact with said polyalphaolefine layer, all or a portion of said polyalphaolefine layer remaining on said bottom surface of said integrated circuit chip; and means for removing said polyalphaolefine layer from said bottom surface of said integrated circuit chip.