Patent ID: 7710776

Claim:
A method for determining a SONOS V T window in a non-volatile SRAM having a volatile portion and a non-volatile portion, said method comprising: creating a first current path from a first tri-gate structure to a first location, said first tri-gate structure having a first recall transistor, a first store transistor and a first SONOS transistor, each transistor having a gate node, a source node and a drain node, said first current path including a first data node within said volatile portion, said first location having a current monitoring means for detecting current on said first current path; creating a second current path from a second tri-gate structure to a second location, said second tri-gate structure having a second recall transistor, a second store transistor and second SONOS transistor, each transistor having a gate node, a source node and a drain node, said second current path including a second data node within said volatile portion, said second location having a current monitoring means for detecting current on said second current path; ramping a voltage applied to said gate nodes of said first and second SONOS transistors; detecting current on said first current path to determine an erase threshold voltage; detecting the presence of current on said second current path to determine the program threshold voltage; and determining the V T window of said first and second SONOS transistors based upon said erase threshold voltage and said program threshold voltage.