Patent ID: 7545933

Claim:
A logic cell, comprising: a decryption circuit, comprising: a single-rail technology interface configured to receive an encrypted data signal on a data input line; a generator configured to generate a decrypted data signal from the encrypted data signal and a key, and to generate a complementary decrypted data signal; and a dual-rail technology interface configured to output the decrypted data signal on a first data line, and the complementary decrypted data signal on a second data line; an encryption circuit, comprising: a dual-rail technology interface configured to receive a logic signal on a first logic line, and a complementary logic signal on a second logic line; a generator configured to generate an encrypted logic signal from the logic signal and/or from the complementary logic signal and from a key; and a single-rail technology interface configured to output the encrypted logic signal on a data output line; and a performer configured to perform a linkage specification, which is connected to the decryption circuit via the first data line and the second data line, and is connected to the encryption circuit via the first logic line and the second logic line, wherein the performer is implemented in dual-rail circuit technology and is configured to perform a linkage specification to generate the logic signal and the complementary logic signal in accordance with the linkage specification from the decrypted data signal and the complementary decrypted data signal.