Patent ID: 8416605

Claim:
A non-volatile semiconductor storage device, comprising: a memory cell array having a plurality of first wiring lines, a plurality of second wiring lines disposed to intersect the first wiring lines, and a plurality of electrically rewritable memory cells disposed at intersections of the first and second wiring lines, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner; and a data writing unit that has a voltage supply circuit which supplies a voltage needed to write data to the plurality of memory cells through the first and second wiring lines, and a resistance state detecting circuit which detects a resistance state of the variable resistive element at the time of writing the data, the data writing unit stopping the supply of the voltage to the memory cell where a resistance state of the variable resistive element becomes a desired resistance state, among the plurality of memory cells, according to the detection result of the resistance state detecting circuit, wherein the data writing unit includes, for each of the memory cells where the data is simultaneously written: a set voltage supply circuit which supplies a set voltage to change the resistance state of the variable resistive element from a high resistance state to a low resistance state; and a set state detecting circuit which detects that the variable resistive element is in the low resistance state.