Patent ID: 7776659

Claim:
A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method comprising: forming an active region on a surface layer of a semiconductor substrate; forming a first conductive type channel region in the active region; forming a gate insulating film on the semiconductor substrate in the channel region; forming a first word line extending in a first direction on the gate insulating film in the first memory cell array region, and forming a second word line extending in a second direction crossing the first direction on the gate insulating film in the second memory cell array region; forming a resist pattern covering part of an upper surface of the first word line so as to put, in an exposed state, one side surface of the first word line and a bit contact region of the semiconductor substrate; and ion-implanting an impurity having the same conductive type as the first conductive type into the active region of the bit contact region side using the resist pattern as a mask, wherein the ion implantation into the active region is performed from a direction that is inclined from a direction vertical to the surface of the semiconductor substrate and is oblique with respect to both the first direction and the second direction.