Patent ID: 8345498

Claim:
A sense amplifier comprising: a first PMOS transistor having a first PMOS drain, a first PMOS source, and a first PMOS gate; a second PMOS transistor having a second PMOS drain, a second PMOS source, and a second PMOS gate; a third PMOS transistor having a third PMOS drain, a third PMOS source, and a third PMOS gate; a fourth PMOS transistor having a fourth PMOS drain, a fourth PMOS source, and a fourth PMOS gate; a first NMOS transistor having a first NMOS drain, a first NMOS source, and a first NMOS gate; a second NMOS transistor having a second NMOS drain, a second NMOS source, and a second NMOS gate; a third NMOS transistor having a third NMOS drain, a third NMOS source, and a third NMOS gate; a fourth NMOS transistor having a fourth NMOS drain, a fourth NMOS source, and a fourth NMOS gate; a control signal line; a first supply voltage node; a second supply voltage node; a first data line; and a second data line; wherein the first PMOS source, the second PMOS source, and the second supply voltage node are coupled together; the first NMOS source, the third PMOS source, the fourth PMOS source, the second NMOS source, and the first supply voltage node are coupled together; the third NMOS gate, the fourth NMOS gate, the third PMOS gate, the fourth PMOS gate are coupled together and to the control signal line; the first data line, the first PMOS drain, the first NMOS drain, the fourth NMOS drain, and the second PMOS gate are coupled together; the second data line, the second PMOS drain, the second NMOS drain, the third NMOS drain, and the first PMOS gate are coupled together; the first NMOS gate, the third NMOS source, and the third PMOS drain are coupled together; and the second NMOS gate, the fourth NMOS source, and the fourth PMOS drain are coupled together.