Patent ID: 8331188

Claim:
A semiconductor storage device comprising: a plurality of memory macros coupled in series, each of the plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit provided for each of the plurality of memory cell arrays, the low-potential power supply boosting circuit provided between a low-potential power supply and a ground, the low-potential power supply boosting circuit being configured to couple the low-potential power supply to the ground in a normal mode and couple the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuit provided for each of the plurality of memory cell arrays, the virtual power control circuit including a plurality of switches provided in parallel with the low-potential power supply boosting circuit, each of the plurality of switches supplying an output to the low-potential power supply boosting circuit independent of every other one of the plurality of switches, the plurality of switches being configured to be turned on when a mode control signal indicates to switch from the sleep mode to the normal mode and configured to be turned off when the mode control signal indicates to switch from the normal mode to the sleep mode; and a sleep cancellation detecting circuit configured to receive the mode control signal and to output the subsequent mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros when the mode control signal supplied to the plurality of switches of one of the plurality of memory arrays in one of the plurality of memory macros indicates to switch from the sleep mode to the normal mode.