Patent ID: 8817434

Claim:
An ESD protection device, adapted for a high-voltage tolerant I/O circuit, comprising: a stacked transistor; and a gate-grounded transistor; wherein the stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit, wherein the gate-grounded transistor is a non-stacked transistor; a layout structure of the stacked transistor comprises a plurality of first finger transistor structures, each of the plurality of first finger transistor structures comprising two first gate fingers; a layout structure of the gate-grounded transistor comprises a plurality of second finger transistor structures, each of the plurality of second finger transistor structures comprising a second gate finger; and the plurality of first finger transistor structures and the plurality of second finger transistor structures are arranged intervally along a first direction.