Patent ID: 7355913

Claim:
A semiconductor memory device having a folded bit line structure and operating with a source voltage and a ground voltage, comprising: a first first-type well including a first cell array for providing data to a first bit line or a first bit line bar selected among a plurality of bit lines, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of the first bit line and the first bit line bar during a precharge period; a first second-type well including a first sense amplifying MOS transistor having a first-type channel among a plurality of sense amplifying MOS transistors for sensing and amplifying a signal difference between the first bit line and the first bit line bar, and a first connection MOS transistor having a first-type channel for connecting or disconnecting the first bit line and the first bit line bar to or from the first sense amplifying MOS transistor; and a second first-type well including a second sense amplifying MOS transistor having a second-type channel among the plurality of sense amplifying MOS transistors for sensing and amplifying the signal difference between the first bit line and the first bit line bar.