Patent ID: 7511333

Claim:
An integrated circuit comprising: a semiconductor region comprising a first surface, the semiconductor region comprising two source/drain regions of a nonvolatile memory extending from the first surface into the semiconductor region, the two source/drain regions having a first conductivity type, the two source/drain regions being separated by a channel region in the semiconductor region; a plurality of conductive floating gates formed over the semiconductor region adjacent to the first surface and the channel region; a conductive gate overlying each of the floating gates; and dielectric insulating the floating gates from the conductive gate and the semiconductor region; wherein the channel region comprises: a plurality of channel sub-regions of a second conductivity type opposite to the first conductivity type, each channel sub-region being adjacent to a respective one of the floating gates; and a connection region of the first conductivity type extending from the first surface into the semiconductor region, the connection region interconnecting two of the channel sub-regions, and at least one of the conditions (A) and (B) holds true: (A) the connection region has a lower net doping concentration at the first surface than each of the two source/drain regions; (B) the connection region is more shallow than each of the two source/drain regions.