Patent ID: 8521463

Claim:
An integrated circuit, comprising: a plurality of functional circuits including a first functional circuit and a second functional circuit; a plurality of input/output (I/O) pads coupled to the plurality of functional circuits; a plurality of single-channel I/O interfaces for performing one or more read/write operations to the integrated circuit by way of the first and second functional circuits; a capture flip-flop for capturing data at the plurality of single-channel I/O interfaces; and a test circuit for performing electrical characterization of the plurality of single-channel I/O interfaces, wherein the test circuit includes at least one of an address register, a command register and a data register for simulating the one or more read/write operations, and wherein the test circuit is configured for: simulating the one or more read/write operations by way of the at least one of the address register, the command register and the data register, such that the read/write operations bypass the first and the second functional circuits, and driving data from the data register to at least one of the plurality of single-channel I/O interfaces in order to perform transmit channel electrical characterization; configuring a first single-channel interface in an input mode for receiving test data from an external tester, capturing the test data by way of the capture flip-flop, wherein the capture flip-flop samples the test data, and driving the sampled test data to at least one of the plurality of I/O pads in order to perform receive channel electrical characterization.