Patent ID: 7701755

Claim:
A memory device, comprising: a plurality of SRAM cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit, each cell coupled between a first power supply node for receiving a cell power supply voltage and a second power supply node for selectively receiving one of a negative read voltage, a positive write voltage and a ground voltage, and a plurality of word lines supplied by a word line voltage, wherein said word line voltage is a suppressed power supply voltage for a word line coupled to a cell selected for a read or write operation; and a switch circuit coupled to the second power supply node of each cell, said switch circuit selectively coupling either the positive write voltage or the negative read voltage to the second power supply node of cells in a column of cells containing the selected cell, and simultaneously coupling the ground voltage to the second power supply node of cells in columns of cells sharing the word line coupled to the selected cell.