Patent ID: 8570822

Claim:
A semiconductor memory comprising: a memory cell array in which memory cells are arranged in matrix; a word line commonly connected to memory cells for each of rows; a bit line commonly connected to memory cells for each of columns; a write circuit connected to one ends of the bit lines configured to write data to the memory cells via the bit lines; a read circuit connected to the other ends of the bit lines configured to read data from the memory cells via the bit lines; a write control circuit configured to make test data to be sent from the write circuit to the bit lines for testing the bit lines and configured to make data to be written from the write circuit to the memory cells for data writing; and a read control circuit configured to make the test data sent to the bit lines to be read out when testing the bit lines and configured to make the data stored in the memory cells to be read out by the read circuit when reading out the data, wherein the word line is inactivated during testing the bit lines.