Patent ID: 8749413

Claim:
A digital correction circuit for a pipelined analog-to-digital converter (ADC), the pipelined ADC including N stages of first sub-circuits, each of which outputting a 2-bit code, the 2-bit code output by the n-th-stage of first sub-circuit being expressed as D 2(N+1-n) and D 2(N+1-n)-1 , where N is an integer greater than 3 and n is an integer satisfying 1≦n≦N, the digital correction circuit comprising N stages of second sub-circuits, among which: the first-stage of second sub-circuit is configured to receive the 2-bit code D 2N and D 2N−1 output by the first-stage of first sub-circuit; the i-th-stage of second sub-circuit is configured to receive both the 2-bit code D 2(N+1-i) and D 2(N+1-i)-1 output by the i-th-stage of first sub-circuit and an output from the (i−1)-th-stage of second sub-circuit, where i is an integer satisfying 2≦i≦N−1; and the N-th-stage of second sub-circuit is configured to receive D 2 ; wherein the digital correction circuit outputs N+1 quantized bits, including a first quantized bit Q 1 that equals to D 1 and second to (N+1)-th quantized bits Q 2 to Q N+1 that are output by the N-th-stage of second sub-circuit, among which: the quantized bit Q N+1 is expressed as Q N+1 =A N+1,2 +B N+1,2 D 2 , where A N+1,2 and B N+1,2 are coefficients of an (N−1)-th-stage of intermediate value that is output by the (N−1)-th-stage of second sub-circuit and corresponds to the quantized bit Q N+1 , coefficients of the respective stages of intermediate values that are output by the respective stages of second sub-circuits and correspond to the quantized bit Q N+1 satisfying the following recurrence relations: A N + 1 , m = { A N + 1 , m + 1 + B N + 1 , m + 1 ⁢ D 2 ⁢ m ( m = 2 , 3 , … ⁢ , N - 2 ) D 2 ⁢ N + D 2 ⁢ N - 1 ⁢ D 2 ⁢ N - 2 ( m = N - 1 ) ⁢ ⁢ B N + 1 , m = { B N + 1 , m + 1 ⁢ D 2 ⁢ m _ ⁢ D 2 ⁢ m - 1 ( m = 3 , 4 , … ⁢ , N - 2 ) B N + 1 , 3 ⁢ D 3 ( m = 2 ) D 2 ⁢ N - 1 ⁢ D 2 ⁢ N - 2 _ ⁢ D 2 ⁢ N - 3 ( m = N - 1 ) the quantized bit Q k is expressed as Q k =A k,2 D 2 +B k,2 +E k,2 D 2 where k is an integer satisfying 3≦k≦N, A k,2 , B k,2 , and E k,2 are coefficients of an (N−1)-th-stage of intermediate value that is output by the (N−1)-th-stage of second sub-circuit and corresponds to the quantized bit Q k , coefficients of the respective stages of intermediate values that are output by the respective stages of second sub-circuits and correspond to the quantized bit Q k satisfying the following recurrence relations: ⁢ A k , m = { D 2 ⁢ m + 1 ⁢ D 2 ⁢ m _ ( m = k - 1 ) A k , m + 1 ⁢ D 2 ⁢ m _ ( m = 2 , 3 , … ⁢ ⁢ k - 2 ) ⁢ ⁢ B k , m = { D 2 ⁢ m + 1 ⁢ D 2 ⁢ m _ ⁢ ⁢ D 2 ⁢ m - 1 _ + D 2 ⁢ m + 1 _ ⁢ D 2 ⁢ m ( m = k - 1 ) A k , m + 1 ⁢ D 2 ⁢ m _ ⁢ ⁢ D 2 ⁢ m - 1 _ + B k , m + 1 + E k , m + 1 ⁢ D 2 ⁢ m ( m = 2 , 3 , … ⁢ ⁢ k - 2 ) ⁢ ⁢ ⁢ E k , m = { D 2 ⁢ m + 1 _ ⁢ ⁢ D 2 ⁢ m _ ⁢ D 2 ⁢ m - 1 ( m = k - 1 ) E k , m + 1 ⁢ D 2 ⁢ m _ ⁢ D 2 ⁢ m - 1 ( m = 3 , 4 , … ⁢ ⁢ k - 2 ) E k , 3 ⁢ D 3 ( m = 2 ) ; and the quantized bit Q 2 is expressed as Q 2 =D 3 D 2 + D 3 D 2 .