Patent ID: 7543204

Claim:
A method for designing logic scan chains for matching gated portions of a clock tree comprising the steps of: identifying a total number T of scannable latches and a number N of scan chains; designing logic including said total number T of scannable latches; and grouping said total number T of scannable latches into N latch groups of substantially equal size, designating a respective one of said N latch groups to define each said respective scan chain of said plurality of scan chains including choosing a physical centroid location for each respective scan chain of said plurality of scan chains, and swapping cells between respective scan chains to minimize a distance between each cell and said physical centroid location of an assigned scan chain for each cell causing said scannable latches to be grouped by proximity to said physical centroid location of said assigned scan chain; designing a clock tree including designing a plurality of N balanced sections, each said section including a gate receiving inputs of a global clock and a respective chain-specific clock control signal for a particular scan chain; connecting a plurality of latches to a corresponding chain-specific clock tree section to define each respective scan chain of a plurality of scan chains; and building a scan chain for each of said plurality of latches defining said respective scan chain.