Patent ID: 7522085

Claim:
An apparatus for reducing error at a plurality outputs of a plurality of sample and hold circuits having substantially a same input analog signal, when said input analog signal is changing with time, and when said plurality of sample and hold circuits have differing delays, comprising: a first sample and hold having a first delay, having said input analog signal as an input, and having a first clock signal; a next sample and hold having a next delay longer than said first delay, having same said input analog signal as an input, and having a second clock signal; and a clock edge delay circuit, having said first clock signal as an input, having a delay adjust signal input, and generating said second clock signal as an output whose delay with respect to said first clock signal input is responsive to said delay adjust signal, with said second clock signal output coupled to said second clock input of said next sample and hold; wherein the delay of said second clock signal is adjusted to compensate for the difference in delay between said first and next sample and holds, so as to cause the held outputs of both said sample and holds to be substantially equivalent even when said input analog signal is changing with time, thus minimizing dynamic error in said data output and said analog residue voltage output.