Patent ID: 7382230

Claim:
A method, comprising: providing an electrical circuit comprising a first counter circuit A, a second counter circuit B, a flip-flop circuit, a first OR gate, a second OR gate, and a logic circuit, wherein an output of said first counter circuit A is electrically connected to a first input of said logic circuit, wherein an output of said second counter circuit B is electrically connected to a second input of said logic circuit, wherein an output of said logic circuit is electrically connected to an enable input E on said flip-flop circuit, wherein said first OR gate is electrically connected to an input PRE of the flip-flop circuit, and wherein said second OR gate is electrically connected to an input RST of the flip-flop circuit; receiving by said first counter circuit A, a first enable signal INC_A; generating by said first counter circuit A, a first output signal SIG_A; receiving by said second counter circuit B, a second enable signal INC_B; generating by said second counter circuit B, a second output signal SIG_B; comparing by said first enable signal INC_A and said second enable signal INC_B said first output signal SIG_A to said second output signal SIG_B; generating by said flip-flop circuit, a first status signal defining a first relationship between said first output signal SIG_A and said second output signal SIG_B; generating by said logic circuit, a second status signal defining a second relationship between said first output signal SIG_A and said second output signal SIG_B; receiving by said first OR gate, a signal PRE_A and a signal RST_B; generating, by said first OR gate from said signal PRE_A and said signal RST_B, a first ORed signal; applying by said first OR gate, said first ORed signal to said input PRE of the flip-flop circuit; receiving by said second OR gate, a signal PRE_B and a signal RST_A; generating by said second OR gate from said signal PRE_B and said signal RST_A a second ORed signal; and applying by said second OR gate, said second ORed signal to said input RST of the flip-flop circuit.