Patent ID: 7265011

Claim:
A method of manufacturing a transistor, comprising: sequentially forming a dummy gate oxide layer, a dummy gate electrode, and a dummy gate upper insulation layer on a semiconductor substrate; ion-implanting first impurities into source/drain regions provided on both sides of the dummy gate electrode to form first impurity regions; forming spacers on sidewalls of the dummy gate electrode; ion-implanting first impurities using the spacer as an ion implantation mask to form second impurity regions that are overlapped by the first impurity regions; depositing pad polysilicon layers on the second impurity regions, the pad polysilicon layers in contact with the spacers; removing the dummy gate upper insulation layer and an upper portion of the spacer; removing the dummy gate electrode; annealing the semiconductor substrate; ion-implanting second impurities into a gate region of the semiconductor substrate to form a third impurity region, the second impurities having a conductivity type opposite that of the first impurities; removing the dummy gate oxide layer; forming a gate insulation layer; and forming a gate electrode on the gate region.