Patent ID: 8154134

Claim:
A packaged electronic device, comprising: a package comprising a leadframe and a first integrated circuit (IC) die; said leadframe including a die pad and a plurality of lead pins including a first, second, and a third lead pin surrounding said die pad; the first integrated circuit (IC) die assembled in a face-up configuration on said lead frame, said IC die including: a substrate having an active top semiconductor surface and a bottom surface, said top semiconductor surface including integrated circuitry having an input pad, an output pad, a power supply pad, and a ground pad; a plurality of through-substrate vias (TSVs) having an electrically conductive filler material extending from said top semiconductor surface through said substrate, including: a first TSV coupling said input pad to said first lead pin, a second TSV coupling said output pad to said second lead pin, a third TSV coupling said power supply pad to said third lead pin or a first portion of said die pad, said first TSV, said second TSV and said third TSV including a dielectric liner surrounding said electrically conductive filler material; and a fourth TSV coupling said ground pad to said die pad or a second portion of said die pad.