Patent ID: 7863751

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate, on which conductive layers are formed; a first wiring layer formed above the semiconductor substrate to be electrically connected to a first conductive layer on the semiconductor substrate via one or more first via-contacts; and a second wiring layer formed above the first wiring layer to be electrically connected to a second conductive layer on the semiconductor substrate via plural sets of second via-contacts and relaying pads stacked alternately; and a plurality of wiring layers stacked in a direction perpendicular to the semiconductor substrate, each of the wiring layers being electrically connected to the conductive layers via plural sets of via-contacts and relaying pads stacked alternately, wherein a number of the second via-contacts constituting a set provided at a lowermost portion just above the second conductive layer is greater than that of the first via-contacts just above the first conductive layer, and wherein with respect to a certain wiring layer at the second layer or upper layer, the number of via-contacts constituting a set underlying a lower relaying pad near the semiconductor substrate is set to be greater than that of another set of via-contacts underlying an upper relaying pad.