Patent ID: 8248167

Claim:
A method for locking a phase lock loop (PLL) frequency by compensating a voltage controlled oscillator (VCO) control voltage, comprising: providing a VCO with a first analog tuning input port and a second analog tuning input port; providing a first digital-analog converter (DAC) coupled to said first analog tuning input port via a first switch; generating a first control signal by said first DAC; providing said first control signal to said first analog tuning input port; providing a preload voltage generator circuit coupled to said second analog tuning input port via a second switch; generating a second control signal from selecting a coarse band by said preload voltage generator circuit based on a selected channel frequency; providing said second control signal to said second analog tuning input port; providing a differential amplifier coupled to said second analog tuning input port via a third switch; providing a processing circuit coupled to said first analog tuning input port via a fourth switch, and further coupled to said differential amplifier; generating said VCO control voltage by said processing circuit according to a VCO output signal of said VCO and a first reference signal; providing said VCO control voltage to said first analog tuning input port; generating a third control signal from comparing said VCO control voltage to a second reference signal by said differential amplifier; and providing said third control signal to said second analog tuning input port.