Patent ID: 7649239

Claim:
An electronic structure with a plurality of interconnects, comprising: a first dielectric layer; a first interconnect, wherein said first interconnect is above said first dielectric layer; a second interconnect, wherein said second interconnect is above said first dielectric layer, and wherein said second interconnect is spaced apart from said first interconnect; a first dielectric spacer, wherein said first dielectric spacer is adjacent to a sidewall of said first interconnect, and wherein said first dielectric spacer is in between said first and said second interconnects; a second dielectric spacer, wherein said second dielectric spacer is adjacent to a sidewall of said second interconnect, wherein said second dielectric spacer is in between said first and said second interconnects, and wherein said first and said second dielectric spacers are discontiguous from one another with a first gap in between said first and said second dielectric spacers; a third interconnect, wherein said third interconnect is above said first dielectric layer, wherein said third interconnect is spaced apart from said second interconnect; a third dielectric spacer, wherein said third dielectric spacer is adjacent to a sidewall of said second interconnect, and wherein said third dielectric spacer is in between said second and said third interconnects; a fourth dielectric spacer, wherein said fourth dielectric spacer is adjacent to a sidewall of said third interconnect, wherein said fourth dielectric spacer is in between said second and said third interconnects, wherein said third and said fourth dielectric spacers are discontiguous from one another with a second gap in between said third and said fourth dielectric spacers, and wherein the width of said second gap is greater than the width of said first gap in between said first and said second dielectric spacers; a second dielectric layer, wherein said second dielectric layer is above said first, said second and said third interconnects, wherein said second dielectric layer is above and not in said first gap in between said first and said second dielectric spacers, and wherein said second dielectric layer is in said second gap in between said third and said fourth dielectric spacers.