Patent ID: 7673093

Claim:
A computer system comprising a memory system, the memory system further comprising: a memory controller; and a daisy chain of memory chips, the daisy chain of memory chips further comprising a first memory chip and a second memory chip; wherein the memory controller is configured to create an address/command word and further configured to transmit the address/command word on a first point to point interconnection to the first memory chip; if the address/command word is not directed to the first memory chip, the first memory chip is configured to transmit the address/command word to the second memory chip on a second point to point interconnection; the address/command word further comprising: a command; a packet ID assigned by the memory controller; and an address; each memory chip is further configured to receive and re-transmit a data word on a serially connected point to point data bus, the data word further comprising a packet ID assigned by the memory controller, each memory chip in the daisy chain of self timed memory chips is able to associate the address/command word and the data word using the packet ID in the address/command word and the packet ID in the data word.