Patent ID: 6990570

Claim:
A digital system having a processing engine, the processing engine comprising: an execution mechanism, for repeatedly executing an instruction sequence including a repeat instruction and at least one instruction immediately subsequent to the repeat instruction in the instruction sequence; a repeat count register for specifying a number of times that the execution mechanism is to execute the at least one subsequent instruction upon executing the repeat instruction; a repeat count index register, having an input for receiving the contents of the repeat count register upon executing the repeat instruction; and circuitry for adjusting the content of the repeat count index register responsive to each execution of the subsequent instruction; wherein the execution mechanism executes the repeat instruction, prior to executing the at least one subsequent instruction, by modifying the content of said repeat count register by an operand value responsive to each execution of the repeat instruction, so that the repeat count index register is initialized with modified contents of the repeat count register each time the repeat instruction is executed.