Patent ID: 8181089

Claim:
A method for auto-correction of errors in an array of a plurality of solid-state storage devices, said array being arranged in a plurality of storage channels, the method comprising the steps of: (a) dedicating at least a portion of a plurality of solid-state storage devices to storing parity data to provide a fault tolerance for a loss of at least two of said plurality of solid-state storage devices; (b) performing a read operation from said array of a plurality of solid-state storage devices, said read operation including respectively transferring data read from each said plurality of storage channels to a corresponding channel memory; (c) reading said data from said channel memories and performing a parity check of said data read from said channel memories; (d) responsive to a failure of said parity check in an unidentified storage channel, testing said data to identify one of said plurality of storage channels as being in error; and (e) responsive to identifying said one storage channel as being in error, using the remaining other of said plurality of storage channels to provide valid data to a processor requesting said data.