Patent ID: 7626434

Claim:
An apparatus comprising a low leakage latch to store a state of a circuit during inactive modes, wherein the state is to be transferred to the low leakage latch upon receipt of an inactive pulse, wherein the low leakage latch includes pass transistors to receive the inactive pulse, wherein the pass transistors are to pass the state from the circuit upon receipt of the inactive pulse; a buffer to receive the state from an output of the low leakage latch and to isolate the state; and state restore circuitry to restore the state to the circuit when the circuit returns to an active mode, wherein the state restore circuitry is to receive the isolated state from the buffer and is to restore the state upon receipt of an active pulse, wherein the state restore circuitry includes a first, second and third transistor, wherein the first and second transistors are to receive the isolated state and the second and third transistors are to receive the active pulse, wherein the second transistor is to provide a restore signal when the isolated state is low and wherein the first and third transistors are to provide the restore signal when the isolated state is high.