Patent ID: 6940338

Claim:
A semiconductor integrated circuit comprising: a bias circuit that has a first current source for generating a first current and a load circuit connected in series with the first current source, and that generates a first voltage at a first node that is a connecting node between the first current source and the load circuit; a second current source that generates a power supply current in accordance with the first voltage; an internal circuit that has a plurality of first transistors and is connected to said second current source in order to operate the first transistors; and a correcting circuit that includes a correcting transistor receiving a constant voltage at a gate, and that generates, in accordance with the constant voltage, a correcting current at a second node electrically connected to a drain of the correcting transistor, the second node being electrically connected to the first node, wherein: the drain of the correcting transistor is connected to each gate of a pair of second transistors forming a first current mirror circuit; and a drain of one of the second transistors that is not connected to the correcting transistor is connected to the second node.