Patent ID: 7956778

Claim:
A analog-to-digital converter comprising: a dither generation circuit which generates dither; an input polarity switching unit which an input signal with the dither is inputted to and switches a polarity of the input signal; an integrator which integrates the input signal with the dither outputted from the input polarity switching unit; an integrator output regulator circuit which regulates an output voltage of the integrator; a window comparator which includes a high-voltage-side comparator having a first reference voltage and a second reference voltage higher than the first reference voltage, and a low-voltage-side comparator having a third reference voltage and a fourth reference voltage lower than the third reference voltage, as well as compares an output voltage of the integrator with the first to fourth reference voltages; and a control circuit which uses the comparison result of the window comparator to control the input polarity switching unit, the integrator output regulator circuit, and the window comparator as well as to generate a digital signal, wherein the control circuit controls such that when the output voltage of the integrator reaches the first reference voltage or the third reference voltage, a clock signal is inverted, and when the output voltage of the integrator reaches the second reference voltage or the fourth reference voltage, a sign is inverted, and a count value is generated based on the clock signal and the sign, and the dither generation circuit generates dither in such a manner that a cycle in which the digital signal is read is an integral multiple of one cycle of the dither as well as that the number of times the count value is generated in the first half of one cycle of the dither is different from the number of times the count value is generated in the second half of the one cycle of the dither.