Patent ID: 8270479

Claim:
A single-chip audio/video encoder device comprising, on a single integrated circuit: first encoder circuitry, second encoder circuitry, multiplexer circuitry, controller circuitry, and at least one bus interface; wherein the first encoder circuitry comprises: a first video encoder that receives first uncompressed video data from a first video source external to the device and produces first compressed video, a first audio encoder that receives first uncompressed audio data from a first audio source external to the device, and that produces first compressed audio, and a first memory interface that interfaces directly with first storage external to the device; wherein the second encoder circuitry comprises: a second video encoder that receives second uncompressed video data from a second video source external to the device and that produces second compressed video, a second audio encoder that receives second uncompressed audio data from a second audio source external to the device and that produces second compressed audio, and a second memory interface that interfaces directly with second storage external to the device; wherein the multiplexer circuitry operating in a first mode, multiplexes the first compressed video, the first compressed audio, the second compressed video, and the second compressed audio to form a first multiplexed stream operably coupled via a first output to circuitry external to the device; wherein the multiplexer circuitry operating in a second mode, multiplexes the first compressed video and the first compressed audio to form the first multiplexed stream operably coupled via the first output to circuitry external to the device, and multiplexes the second compressed video and the second compressed audio to form a second multiplexed stream operably coupled via a second output to circuitry external to the device; wherein the controller circuitry synchronizes operation of the first encoder circuitry, the second encoder circuitry, and the multiplexer circuitry; and wherein the at least one bus interface operably couples the controller circuitry and at least one processor external to the device.