Patent ID: 8843860

Claim:
A semiconductor processing method, comprising: establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer, each shot including a respective shot area defined by a length and a width, and at least one frame structure segment that enables the shot to be shifted relative to an adjacent shot area by a distance that is less than the length of the shot being shifted; shifting at least one of a row of shots or a column of shots relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout; selecting one of the initial shot layout and the at least one additional shot layout as a final shot layout; and exposing the semiconductor wafer to light in accordance with the final shot layout using a lithographic device.