Patent ID: 7968460

Claim:
A method of fabricating a semiconductor device comprising: etching a via into a silicon substrate from a first side toward a second side of the silicon substrate; forming a conductive interconnect in the etched via by filling the via with a metal material, the conductive interconnect having a first end proximate the first side of the silicon substrate and a second end proximate the second side of the silicon substrate; insulating the conductive interconnect with a dielectric material proximate the first side of the silicon substrate; forming a metal routing structure on the dielectric material, the metal routing structure being at least partially in the dielectric material; and removing material from the second side of the semiconductor substrate to expose the second end of the conductive interconnect; wherein: the metal routing structure is a first metal routing structure; the dielectric material is a first dielectric material; the method further includes: insulating the conductive interconnect and the first metal routing structure with a second dielectric material; forming a plurality of openings in the second dielectric material, the openings including a first opening generally corresponding to the first metal routing structure, a second opening generally corresponding to the conductive interconnect, and a third opening generally corresponding to a second metal routing structure; and filling the plurality of openings with a conductive material, thereby forming a first conductive path between the first and second metal routing structures, a second conductive path between the second metal routing structure and the conductive interconnect, and the second metal routing structure.