Patent ID: 7052965

Claim:
A method of fabricating a MOSFET with pocket regions, comprising: forming a gate electrode layer on a semiconductor substrate; forming lightly doped drain regions in the semiconductor substrate adjacent the gate electrode layer; forming a device isolation region on the semiconductor substrate surrounding the lightly doped drain regions adjacent the gate electrode layer; forming a blocking pattern on the semiconductor substrate, the blocking pattern being adjacent and spaced apart from the gate electrode layer a predetermined distance and exposing portions of the semiconductor substrate adjacent sidewalls of the gate electrode layer and extending over the device isolation region and onto the lightly doped drain regions adjacent the gate electrode layer; and forming pocket regions in the semiconductor substrate by implanting impurity ions at an oblique tilt angle into a surface of the semiconductor substrate between the blocking pattern and the gate electrode layer using the gate electrode layer and the blocking pattern as an ion implantation mask to define a width of the pocket regions.