Patent ID: 7908536

Claim:
A computer program product comprising a non-transitory computer readable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to: input test pattern data into a first set of latches associated with a first clock domain of the asynchronous clock boundary of the integrated circuit device; run functional boundary logic, associated with the asynchronous clock boundary of the integrated circuit device, in a functional mode of operation to move the test pattern data to a second set of latches associated with a second clock domain of the asynchronous clock boundary of the integrated circuit device; obtain results data from the second set of latches; and verify an operation of the functional boundary logic based on the results data obtained from the second set of latches, wherein the computer readable program causes the computing device to run functional boundary logic of the integrated circuit device in a functional mode of operation by running functional boundary logic present in the first clock domain using a first clock native to the first clock domain, and running functional boundary logic present in the second clock domain using a second clock, different from the first clock, and which is native to the second clock domain.