Patent ID: 7576412

Claim:
A wafer comprising: chips having respective surface areas and chip boundaries; and elongate separating zones between the chips for breaking through the wafer and separating off the chips, wherein each chip includes at least one conductive connection line that projects from the boundary of the chip into a separating zone adjoining the chip, that is electrically conductive before a separation of the wafer in the adjoining separating zone, and that is interrupted upon a separation of the wafer in the adjoining separating zone, each of the conductive connection lines having two mutually adjoining conductor portions that are electrically interconnected by a connecting portion, and wherein each chip is covered with a planar protecting layer and the surface area of the planar protecting layer corresponds to the chip surface area, and wherein the wafer includes a protecting strip for each of the conductive connection lines, each of the protecting strips projecting from the planar protecting layer of the respective chip and covering the two mutually adjoining conductor portions, and each of the protecting strips having a portion that is wider than the remaining portion of the protecting strip at at least one side of the protecting strip in its region that adjoins the planar protecting layer.