Patent ID: 7315995

Claim:
A semiconductor integrated circuit designing method employing: a first cell library that contains a plurality of standard cells, and; a second cell library that contains cells which, unlike the cells that are contained in the first cell library and share the same circuitry, include numerous channels and have rules for designing loosened; the designing method comprising the steps of: arranging and interconnecting cells selected from the first cell library; calculating a wiring density, which is, a ratio of an area occupied by wiring to an area of each of first cells that are selected from the first cell library and arranged and interconnected, and recognizing a first cell as an object-of-wiring thinning cell according to the wiring density; replacing the object-of-wiring thinning cell with a second cell, which is selected from the second cell library, so that the object-of-wiring thinning cell will be separated from an adjoining cell by a predetermined pitch; and performing reconnection.