Patent ID: 7254088

Claim:
A semiconductor memory device having a plurality of memory cells accessible from a plurality of ports, comprising: first access transistors for electrically connecting bit lines of a first port among the plurality of ports to the memory cells in response to a first activation signal; second access transistors for electrically connecting bit lines of a second port among the plurality of ports to the memory cells in response to a second activation signal, the first access transistors and the second access transistors being connected to respective same nodes of the memory cells; a first row decoder for sending the first activation signal to the first access transistors via first word lines; a second row decoder for sending the second activation signal to the second access transistors via second word lines; a first control circuit for outputting a first control signal based on a first external control signal supplied externally to control the output of the first activation signal from the first row decoder with the first control signal; and a second control circuit for outputting a second control signal based on a second external control signal supplied externally to control the output of the second activation signal from the second row decoder with the second control signal, wherein when the memory cells receive access from the first port, the second control circuit delays the second control signal in response to the first control signal output from the first control circuit or a signal based on the first control signal, to delay the second activation signal output from the second row decoder to the second access transistors behind the output of the first activation signal by a predetermined time.