Patent ID: 8135767

Claim:
A cell for an arithmetic logic unit comprising: a mirror adder circuit comprising: a first masked input a*; a second masked input b*; a masked carry bit input ci*; a first control input xe 0 and a second control input xe 1 ; and a circuit connected to the first masked input a*, the second masked input b*, the masked carry bit input ci*, the first control input xe 0 , and the second control input xe 1 , the circuit having a first output co*_n and a second output s*_n, wherein the mirror adder circuit comprises a plurality of transistors, wherein the masked carry bit input ci*, the first control input xe 0 and the second control input xe 1 are applied to different ones of the transistors of the mirror adder circuit; and a control unit connected to the circuit, the control unit having a first mask bit input k p , a second mask bit input k p−1 , a first control bit input n 0 , and a second control bit input n 1 , wherein the control unit is configured to generate values for the masked carry bit input ci*, the first control input xe 0 and the second control input xe 1 as a function of values of the first mask bit input k p , the second mask bit input k p−1 , the first control bit input n 0 and the second control bit input n 1 , wherein, to implement a first operation, the control unit is configured to generate the values of the first control input xe 0 and the second control input xe 1 to correspond to the value of the masked carry bit input ci* so that the second output is an inverted masked sum bit s*_n of a masked arithmetic addition of the first masked input a*, the second masked input b* and the masked carry bit input ci*, and the first output co*_n is a masked inverted carry-out bit.