Patent ID: 8082482

Claim:
A memory system comprising: a memory hub device integrated in a memory module; and a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises: a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices, wherein the memory hub device transmit and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel; and first error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices; and second error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices, wherein data read out of the set of memory devices, thereby forming read data, includes a first error correction codeword previously generated for the data, wherein the second error correction logic generates check bits based on the read data and the first error correction codeword in the read data, the check bits indicating if the read data is correct, and wherein if the second error correction logic determines that the read data contains errors that are not correctable, then the read data is output from the memory hub device to the external memory controller along with an error signal indicating the read data to be invalid.