Patent ID: 6996026

Claim:
A device for synchronizing clock signals comprising: a first delay unit with variably controllable delay time, an input of the first delay unit being connected to an output of an input circuit having a first delay time, the input circuit receiving a first clock signal, wherein the first delay unit outputs at its output a second clock signal that is to be synchronized with the first clock signal; a second delay unit having a fixed delay time portion corresponding approximately to the first delay time, and an additional variably controllable delay time portion, and which is connected at its input to the output of the first delay unit; a first phase comparison unit, a first input of which is connected to the output of the input circuit, and a second input of which is connected to an output of the second delay unit, and an output signal of which controls the delay time of the first delay unit; a copy of the input circuit, an input of which is connected to the output of the first delay unit; and a second phase comparison unit, a first input of which is connected to the output of the input circuit, and a second input of which is connected to an output of the copy of the input circuit, and an output signal of which controls the variable delay time portion of the second delay unit.