Patent ID: 7884674

Claim:
A clock and data recovery circuit, comprising: a phase detector receiving a data signal and a clock signal to output a first phase difference signal and a second phase difference signal; a pre-accumulator to accumulate the first phase difference signal and the second phase difference signal to generate a first accumulator value; a register storing a second accumulator value, to receive and temporally store the first accumulator value from the pre-accumulator during a first cycle of a first clock signal; an accumulator storing a third accumulator value, to output the third accumulator value during a second cycle of a second clock signal, and receive and temporally store the second accumulator value from the register during the first cycle of the first clock signal, wherein the second cycle of the second clock signal lags behind the first cycle of the first clock signal by 90 degree phase; and a digital controlled oscillator to adjust the frequency and the phase of the clock signal according to the first accumulator value and the third accumulator value.