Patent ID: 7659583

Claim:
A semiconductor structure comprising: a p-type field effect transistor (PFET) including a PFET active area, wherein said PFET active area contains a PFET channel and is located directly on a buried insulator layer of a semiconductor-on-insulator substrate; an n-type field effect transistor (NFET) including an NFET active area, wherein said NFET active area contains an NFET channel and is located directly on said buried insulator and is disjoined from said PFET active area; a thermal silicon oxide layer located directly on sidewalls and a bottom peripheral surface of said PFET active area, wherein a portion of said thermal silicon oxide layer on said sidewall of said PFET active area has a first thickness; and another thermal silicon oxide layer located directly on sidewalls of said NFET active area, wherein a portion of said thermal silicon oxide layer on said sidewall of said NFET active area has a second thickness, and wherein said first thickness is greater than said second thickness.