Patent ID: 7388769

Claim:
A semiconductor memory device comprising: plural memory cells arranged in a matrix; plural bit lines and plural plate voltage supply lines extending in a row direction; plural word lines and plural plate lines extending in a column direction; plural sense amplifier circuits that are arranged in the column direction, and we electrically connected to the respective bit lines; plural plate line voltage supply circuits that are arranged in the column direction; means for electrically connecting each of the plural plate voltage supply lines with each of the plural plate lines; and means for electrically connecting each of the plural plate voltage supply lines with each of the plural plate line voltage supply circuits; wherein each of the plural bit lines is commonly connected to the plural memory cells arranged in the same row; each of the plural word lines and each of the plural plate lines are commonly connected to the plural memory cells arranged in the same column; each of the plural memory cells is electrically connected to the bit line through a selection transistor having a gate electrode connected to the word line, and has a capacitor electrically connected to the plate line; and the respective plate voltage supply lines are electrically connected to the plate lines at different positions on the same plate line.