Patent ID: 6888769

Claim:
A memory array, comprising: a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory cell capacitor and an access transistor coupled to the memory cell capacitor, the access transistors being fabricated in a simiconductor substrate; a digit line for each column of memory cells in the memory array, each digit line being coupled to a plurality of access transistors in a respective column of memory cells; a word line for each row of memory cells in the memory array, each word line being coupled to the gates of a plurality of access transistors in a respective row of memory cells; a sense amplifier for each column of memory cells, each sense amplifier being coupled to the digit line for a respective column of memory cells, each sense amplifier having a power input and being operable to couple a supply voltage applied to the power input to the digit line to which the sense amplifier is coupled responsive to sensing a predetermined voltage level on the digit line; and a voltage regulator coupled to the power input of the sense amplifiers for a plurality of columns of memory cells, the voltage regulator having at least one bipolar transistor coupled to the power inputs of the sense amplifiers, the at least one bipolar transistor being fabricated in a well formed in the substrate that is electrically isolated from the substrate, the voltage regulator being operable to generate the supply voltage and to regulate the magnitude of the supply voltage responsive to variations in current coupled from the voltage regulator to the sense amplifiers.