Patent ID: 8415783

Claim:
A testable wafer structure, comprising: a wafer having a plurality of parent integrated circuit (IC) dice formed thereon; wherein each parent IC die has a front side, a backside, and a via extending to a pad on the backside of the parent IC die; a plurality of daughter IC dice, each daughter IC die being stacked on the backside of a respective one of the parent IC dice and electrically connected to the one of the parent IC dice through the pad of the one of the parent IC dice; a plurality of silicon wafer portions, each wafer portion disposed on edge on the backside of a respective one of the plurality of parent IC dice, and further disposed between adjacent ones of the daughter dice; and backside fill material disposed on the backsides of the plurality of parent IC dice on the wafer, wherein the backside fill material in areas between a plurality of pairs of the plurality of daughter dice forms a continuous planar surface.