Patent ID: 7120046

Claim:
A memory access array comprising: a semiconductive substrate; a plurality of local data/bit lines extending in a first direction and formed in an upper surface of the substrate at a first pitch; a plurality of access transistors extending generally upward from the upper surface of the substrate and aligned generally atop a corresponding local data/bit line, wherein the access transistors comprise: a pillar extending upward from the upper surface of the substrate and generally aligned atop the corresponding local data/bit line wherein a source region is formed at a lower portion of the pillar so as to be in electrical communication with the corresponding local data/bit line and a drain region is formed at an upper portion of the pillar with a capacitor contact surface defined at an upper surface of the pillar and an opposed gate structure engaging the pillar in at least two opposed lateral directions and extending substantially the entire vertical extent of the pillar; a plurality of conductive word lines extending in a second direction and formed at a second pitch and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a lateral extent about the corresponding pillar via the surround gate structure and wherein the cell access transistors are arranged in a plurality of columns along the second direction; and a plurality of global data/bit lines extending in the first direction, wherein the access transistors in at least one column are interconnected between corresponding global data/bit lines and local data/bit lines so as to define local data/bit access transistors between the corresponding global data/bit lines and local data/bit lines and such that remaining columns of access transistors define cell access transistors.