Patent ID: 8344772

Claim:
An all digital phase-locked loop (ADPLL) comprising: a phase counter configured to accumulate a phase of a frequency setting word and a phase of a digitally controlled oscillator (DCO) clock and detect a fine phase difference between a reference clock and a retimed clock; a phase detector configured to compensate for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference between the reference clock and the retimed clock to detect a digital phase error value; a digital loop filter configured to filter the digital phase error value and control PLL operational characteristics; a lock detector configured to detect a point in time at which an output from the digital loop filter becomes uniform to generate a lock indication signal; a digitally controlled oscillator configured to change a frequency of the DCO clock according to an output from the digital loop filter while changing an operation mode according to the lock indication signal; and a retimed clock generator configured to generate the retimed clock by retiming the DCO clock at a low frequency.