Patent ID: 7669035

Claim:
A processing system, comprising: individually reconfigurable units that are part of a single chip, wherein each of the reconfigurable units includes a plurality of logic gates that during runtime can be further partitioned into a first processing element and a second processing element or re-combined with a second plurality of logic gates of another reconfigurable unit to form a third processing element, wherein the first, second, and third processing elements have quantities of logic gates based on processing tasks, at least one of the processing elements being reconfigurable during runtime and operating independently of other processing elements in the system, and at least two of the processing elements being logically separate and not interacting directly with each other; one or more common data buses to facilitate data exchange between the reconfigurable units and an input/output (I/O) module; and one or more local data buses in electrical communication among the reconfigurable units, the one or more local data buses being reconfigurable during runtime to dynamically reallocate bandwidth among the processing elements based at least in part on said partitioning or re-combination of the logic gates, each local bus, when configured, being dedicated to interconnecting two or more of the processing elements.