Patent ID: 8085598

Claim:
A non-volatile semiconductor device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a plurality of word lines, arranged corresponding to the memory cell rows, each connecting to the memory cells on a corresponding memory cell row; and a sub decode circuit including a sub decoding element arranged corresponding to each word line, for setting voltages on the word lines; each sub decoding element including first and second transistors of a common conductivity type each having a gate, source and drain, the first and second transistors receiving first and second gate signals at their respective gates, the first and second transistors receiving first and second source signals at their respective sources, the first and second transistors having their drains connected commonly to a corresponding word line, the sub decoding elements being arranged in columns supplied with the gate signals of different sets, for each sub decoding element column, an active region for forming transistors being arranged, and the sub decoding elements commonly supplied with the second source signal, said active region including first and second regions of geometrical features symmetric with respect to a first impurity region receiving said second source signal, the first and second transistors being formed in the first and second regions, respectively, and the sub decoding elements formed on a common active region sharing the first impurity region.