Patent ID: 7082075

Claim:
A memory device, comprising: a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device; a column address circuit operable to receive and decode colunm address signals applied to the external address terminals; a plurality of banks of memory cells arranged in rows and columns, each of the memory cells being operable to store a data bit written to or read from the banks at a location determined by the decoded row address signals and the decoded column address signals, a first one of the banks of memory cells containing a number of memory cells that differs from the number of memory cells contained in a second bank of memory cells; a data path circuit operable to couple data signals corresponding to the data bits between the banks of memory cells and external data terminals of the memory device; a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals; bank control logic that is operable to select the bank to which data are to be written or from which data are to be read; and a mode register that may be programmed to select the length of data bursts when the memory device is operating in a burst mode, the bank control logic being coupled to the mode register to select the bank to which data are to be written or from which data are to be read based on the length of data burst programmed in the mode register.