Patent ID: 7904436

Claim:
A data processing system having one or more processors, a memory and a communication pathway between the one or more processors and the memory, said system being adapted perform realtime-safe grace detection of a grace period for deferring removal of a shared data element until pre-existing references to the data element are removed, and comprising: a pair of counters for each of said one or more processors; a global counter selector that determines which counter of each per-processor counter pair is a current counter; a reader adapted to read a shared data element at a processor; a counter incrementer adapted to: increment the current counter of said processor's counter pair that corresponds to said global counter selector; test for reversal of said processor's counter pair to ensure that the incremented counter is still the current counter corresponding to said global counter selector; and responsive to said counter pair reversal occurring such said incremented counter has become the non-current counter, incrementing the other counter of said processor's counter pair that has become the current counter; a data referencer adapted to reference said shared data element; a counter decrementer adapted to decrement whichever counter of said processor's counter pair remains incremented; and a subsystem adapted to process the destruction of a pre-update version of said shared data element following updating thereof in a manner that preserves a pre-update version of said data element, said subsystem including: a counter switch adapted to switch said global counter selector to establish a new current counter of each per-processor counter pair; a counter monitor adapted to test the non-current counter of each per-processor counter pair for zero; and a callback processor adapted to destroy said shared data element's pre-update version upon the non-current counter of each per-processor counter pair being zero.