Patent ID: 8059670

Claim:
A processor for managing packet-based communications, comprising: an addressable memory for storing packet descriptors and data packets, each data packet associated with one of the packet descriptors; a queue manager coupled to the memory, comprising: queue manager logic circuitry; a first queue control register; linking memory, coupled to the queue manager and having a plurality of entries, each entry mapped to one of a plurality of descriptor index values, each descriptor index value mapped to a memory address in the addressable memory, and each entry of the linking memory having a field for storing a next descriptor index value; wherein the queue manager is operable to add a packet descriptor to first queue associated with the first queue control register by performing a sequence of operations comprising: receiving a push request including a pointer to the location in memory of the packet descriptor to be added; mapping the pointer to a descriptor index value; updating an entry in the linking memory to include the descriptor to be added in the first queue, comprising: reading a current value of a head descriptor index field in the first queue control register; writing the current value of the head descriptor index into the entry in the linking memory associated with the descriptor to be added; and updating the first queue control register with the mapped descriptor index value by writing the mapped descriptor index value to the head descriptor index field of the first queue control register.