Patent ID: 8879670

Claim:
A configurable Turbo-Low Density Parity Check (LDPC) decoder comprising: A set of P>1 Soft-Input-Soft-Output decoding units (DP 0 -DP P-1 ; DP i ) for iteratively decoding both Turbo- and LDPC-encoded input data, each of said decoding units having first (I i i ) and second (I 2 i ) input ports and first (O 1 i ) and second (O 2 i ) output ports for intermediate data; First and second memories (M 1 , M 2 ) for storing said intermediate data, each of said first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of said decoding units to the output and input ports of said first memory, and the second input and output ports of said decoding units to the output and input ports of said second memory, wherein each of said P>1 Soft-Input-Soft-Output decoding units (DP 0 -DP P-1 ; DP i ) has: a first input port (I 1 i ) for input reliabilities (λ) used in Turbo-decoding, and for check-to-variable metrics (c2v) used in LDPC-decoding; a second input port (I 2 i ) for extrinsic reliabilities (Λ) used in Turbo-decoding and for intermediate soft outputs (SO) used for LDPC-decoding; a first output port (O 1 i ) for check-to-variable metrics updated during LDPC-decoding; and a second output port (O 2 i ) for extrinsic reliabilities obtained as intermediate or final results of Turbo-decoding, and for soft outputs obtained as intermediate or final results of LDPC-decoding; and said configurable switching network comprises: A first and second P×P permutation network (PN 1 , PN 2 ); A P×P circular switching network (PSN); First switching means (SW 1 ) connecting the input ports of said first memory with either the first output ports of said decoding units or with a first input port (ID 1 ) of the Turbo-LDPC decoder; Second switching means (SW 2 ) connecting the input ports of said second memory with either the second output ports of said decoding units through said first P×P permutation network, or with a second input port (ID 2 ) of the Turbo-LDPC decoder; Third switching means (SW 3 ) connecting the output ports of said first memory with the first input ports of said decoding units either directly or through said P×P circular switching network; and Fourth switching means (SW 4 ) connecting the output ports of said first memory with either the second input ports of said decoding units through said second P×P permutation network, or with an output port (OD) of the Turbo-LDPC decoder.