Patent ID: 8599228

Claim:
An image processor for sequentially outputting image signals respectively corresponding to at least two kinds of images, comprising: a memory storing image data respectively of the at least two kinds of images inputted thereto, the at least two kinds of images including a first image and a second image, wherein each of the image signals includes a sequence of pulses for displaying an image corresponding to image data on a display device of a PWM drive scheme expressing luminance grayscale by subdividing one frame into a plurality of subfields, the first and second images having a relationship in which when luminance values of the image data are added to each other for each pixel, resultant image data is image data of a third image not having a correlation with the first image; a data allocator unit allocating, on the basis of the image data of the at least two kinds of images stored in the memory, a said sequence of pulses including the image data of the first image to each of the subfields so that a period for displaying the first image is shorter than one-third of one frame period, and allocating another said sequence of pulses including the image data of the second image whose pulse width is the same as that of the image data of the first image to each of the subfields in order to be included in a remaining period of the one-third of the one frame period, wherein periods for displaying the first and second images are a same length and wherein a remainder of the one frame period is allocated to data write periods, to the third image, and to optional blanking periods; and a shutter control unit outputting a shutter control signal for shutter glasses only during a period in which the image signal corresponding to the first image is outputted so that the first image is seen through the shutter glasses.