Patent ID: 7883990

Claim:
A method of fabricating a semiconductor-on-insulator (SOI) substrate comprising: subjecting a semiconductor base wafer having a first resistivity to a thermal annealing process to create a surface layer of a second resistivity that is greater than the first resistivity within the semiconductor base layer; providing a second semiconductor wafer for subsequent bonding with said semiconductor base wafer having said surface layer of said second resistivity; and bonding said second semicoductor wafer to said semiconductor base wafer, wherein prior to bonding an insulating layer is formed on at least one of said wafers, and said insulating layer forms an interface with the surface layer of said second resistivity forming a patterned sacrificial layer on said semiconductor base layer prior to said thermal annealing process, said patterned sacrificial layer having a sufficient thickness to prevent formation of said surface layer of second resistivity within remaining portions of said semiconductor base wafer that lay beneath said patterned sacrificial layer.