Patent ID: 7539923

Claim:
A circuit for transmitting a block of data, said circuit comprising: a memory array having a plurality of memory locations coupled to receive data; a first data source coupled to said memory array, said first data source providing data to be stored at sequential addressable memory locations of said plurality of memory locations on a first in, first out basis; a second data source coupled to said memory array, said second data source providing data to be stored in a predetermined memory location of said sequential addressable memory locations; a selection circuit coupled to said first data source and said second data source for selecting data to be stored in said plurality of memory locations; and a control circuit coupled to said selection circuit, said control circuit controlling said selection circuit to enable the selection of data and control signals for storing data from said first data source at each memory location of said sequential addressable memory locations and for overwriting data of said sequential addressable memory locations by storing data from said second data source at said predetermined memory location of said sequential addressable memory locations.