Patent ID: 7821754

Claim:
Circuit arrangement for generating a defined output signal in a CMOS circuit, comprising a sensor signal conditioning switch with an output to emit an output signal, wherein the output is connected to a first connector of a load resistor and a second connector of the load resistor is connected to a VDD potential, the output of the sensor signal conditioning switch is connected to a drain connection of a first N-channel depletion transistor, a source connection of a second N-channel depletion transistor and an output of the CMOS circuit, a gate connection of the first and the second N-channel depletion transistors are connected to an output of a control switch and a first connection of a shunt resistor, a second connection of the shunt resistor and a source connection of the first N-channel depletion transistor are connected to a VSS potential, and a drain connection of the second N-channel depletion transistor is connected to the VDD potential.