Patent ID: 8883601

Claim:
A method of manufacturing a semiconductor device, comprising: forming a sacrificial interlayer insulating film over a substrate; forming a plurality of cylinder holes in the sacrificial interlayer insulating film positioned in each of a memory cell forming region and a compensation capacitance forming region having different planar surface areas; forming a plurality of lower electrodes in the cylinder holes, respectively; removing the sacrificial interlayer insulating film so that each of the lower electrodes includes an inner surface and an outer surface; forming a capacitance insulating film on the inner and outer surfaces of each of the lower electrodes; forming an upper electrode on the capacitance insulating film, thereby a memory cell capacitor is formed in the memory cell forming region and a compensation capacitance is formed in the compensation capacitance forming region, respectively; forming at least a metal film as a plate electrode to cover the upper electrode; and performing a selective etching on the plate electrode to remove respective portions of the plate electrode which are formed over a region other than the memory cell forming region and the compensation capacitance forming region; wherein the memory cell capacitor and the compensation capacitance have a same structure, and are simultaneously formed by a same process.