Patent ID: 7892967

Claim:
A method comprising: forming at least one first inter metal dielectric (IMD) layer over a semiconductor substrate; and then forming a first aperture in the first IMD layer to expose the semiconductor substrate; and then forming a first copper-plated layer over the first IMD layer and in the first aperture; and then forming at least one second IMD layer over the first copper-plated layer; and then forming a second aperture in the second IMD layer to expose the first copper-plated layer; and then forming a second copper-plated layer over the second IMD layer and in the second aperture by performing an electroplating process using the exposed first copper-plated layer as a seed layer; and forming at least one metal pad over the exposed portion of the first copper-plated layer located at the edge of the semiconductor substrate, wherein the metal pad comes into contact with at least one electroplating pin during the electroplating process.