Patent ID: 8610655

Claim:
A gate driving circuit comprising: an m-th stage(wherein ‘m’ is an integer) comprising a pull-up section including a switch having a first control terminal receiving a first clock signal at a first terminal and outputting an m-th gate signal at a second terminal; an (m+1)-th stage connected to the m-th stage, the (m+1)-th stage comprising a pull-up section including a switch having a second control terminal receiving a second clock signal at a third terminal and outputting an (m+1)-th gate signal at a fourth terminal, wherein the second clock signal is opposite in phase to the first clock signal; and a noise removing circuit electrically disconnecting the first control terminal of the pull-up section of the m-th stage and the second control terminal of the pull-up section of the (m+1)-th stage in response to the m-th gate signal and the (m+1)-th gate signal and electrically connecting the first control terminal of the pull-up section of the m-th stage and the second control terminal of the pull-up section of the (m+1)-th stage in response to the first and second clock signals.