Patent ID: 6960950

Claim:
A circuit comprising: an oscillator circuit including a plurality of selectable delay circuits, the oscillator circuit to generate a clock signal having a frequency; a control circuit to receive a reference signal, to receive the clock signal, and to provide a control signal to the oscillator circuit to activate one or more of the plurality of selectable delay circuits to change the frequency of the clock signal, wherein each of the plurality of selectable delay circuits has a propagation delay value substantially equal to one of two different propagation delay values; wherein the two different propagation delay values include a first propagation delay value and a second propagation delay value and the plurality of selectable delay circuits includes one or more selectable delay circuits having the first propagation delay value and one or more selectable delay circuits having the second propagation delay value and the one or more selectable delay circuits having the second propagation delay value have a total propagation delay value of about twice the first propagation delay value; wherein the control circuit includes a counter circuit to count edges of the clock signal and to generate a measured count signal; and wherein the control circuit includes a decision circuit to receive the measured count signal having a value and to generate an increase delay signal when the measured count signal is greater than a target value.