Patent ID: 7605612

Claim:
A clock gating system, comprising: a control register configured to store multiple values, the multiple values including first, second, and third values, wherein the first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed; a counting circuit coupled to the control register, wherein the counting circuit is configured to selectively load one of the first, second, and third values from the control register and count from the loaded one of the first, second, and third values to a transition value; and a control state machine coupled to the counting circuit, wherein the control state machine is configured to receive a compare signal from the counting circuit that indicates the counting circuit has reached the transition value and, based on a current state of the control state machine, provide a load signal to the counting circuit to cause the counting circuit to load an appropriate one of the first, second, and third values from the control register when an enable signal is asserted.