Patent ID: 8394716

Claim:
A method of forming a three-dimensional semiconductor device, the method comprising: forming a thin film structure on wiring and contact regions of a substrate, wherein the thin film structure includes a plurality of alternating sacrificial layers and inter-layer insulating layers, and wherein the thin film structure defines a terraced structure in the contact region; forming an insulating layer on the terraced structure in the contact region; forming sacrificial contact patterns through the insulating layer in the contact region in a direction perpendicular with respect to a surface of the substrate, wherein each of the sacrificial contact patterns is connected to a respective one of the sacrificial layers; removing the sacrificial layers and the sacrificial contact patterns to define recess regions between the inter-layer insulating layers and through the insulating layer; and forming wiring patterns in the recess regions between the inter-layer insulating layers and through the insulating layer.