Patent ID: 7709315

Claim:
A method of manufacturing a semiconductor device comprising a plurality of memory cells arrayed on a semiconductor substrate of a first conductivity type, wherein each of the memory cells includes a select gate formed on the semiconductor substrate with a first gate insulating film interposed therebetween; a memory gate formed on one sidewall of the select gate and insulated from the select gate and the semiconductor substrate via a second gate insulating film; a semiconductor region of a second conductivity type that operates as a source region in a writing operation and is formed in the semiconductor substrate adjacent to the select gate; and a semiconductor region of the second conductivity type that operates as a drain region in a writing operation and is formed in the semiconductor substrate adjacent to the memory gate, wherein the second gate insulating film is configured to include at least a potential barrier film and a charge-holding film stacked on the potential barrier film, wherein a process to form the memory cell includes the steps of: (a) forming the select gate on the semiconductor substrate with the first gate insulating film interposed therebetween by etching, wherein an amount of overetching of the substrate is suppressed to approximately 1 to 3 nm; (b) forming the second gate insulating film including at least the potential barrier film and the charge-holding film so as to cover a surface of the semiconductor substrate and a surface of the select gate; (c) forming the memory gate on one sidewall of the select gate by patterning a conductive film formed on the second gate insulating film; (d) leaving the second insulating film between the sidewall of the select gate and the memory gate and between the semiconductor substrate and the memory gate by patterning the second gate insulating film; and (e) forming the source region formed of the semiconductor region of the second conductivity type in the semiconductor substrate adjacent to the select gate and forming the drain region formed of the semiconductor region of the second conductivity type in the semiconductor substrate adjacent to the memory gate by introducing an impurity into the semiconductor substrate, and wherein, in the step (b), the second gate insulating film is formed so that an interface between the potential barrier film and the charge-holding film in a neighborhood of a bottom part of the select gate is located at a position as high as or higher than an interface between the semiconductor substrate and the first gate insulating film.