Patent ID: 8896030

Claim:
An integrated circuit device, comprising: a first nMOS transistor disposed over a first portion of a substrate, wherein the first MOS transistor comprises: a first semiconductor channel region; and a first gate electrode having a first bottom electrode surface proximate to a first gate dielectric disposed over the first semiconductor channel region and having a first top electrode surface at a first height from the first bottom gate electrode surface, the first gate dielectric having a first top gate dielectric surface at a third height from the first bottom gate electrode surface; and a second MOS transistor disposed over a second portion of the substrate, wherein the second MOS transistor comprises: a second semiconductor channel region; and a second gate electrode having a second bottom electrode surface proximate to a second gate dielectric disposed over the second semiconductor channel region and having at least a portion of a second top electrode surface at a second height from the second bottom electrode surface that is different than the first height, the second gate dielectric having a second top gate dielectric surface at a fourth height from the second bottom gate electrode surface that is different than the third height.