Patent ID: 8683483

Claim:
A method for load-balancing threads among a plurality of processor cores, comprising: a first processor core executing a plurality of software threads using a respective plurality of hardware strands, wherein the plurality of hardware strands share at least one hardware resource, wherein each of the at least one hardware resource is a component within the first processor core; monitoring the at least one hardware resource, wherein, for each respective hardware strand, said monitoring comprises: for each respective hardware resource of the at least one hardware resource: maintaining information for a first number of clock cycles, wherein the first number of clock cycles is a length of time for monitoring the respective hardware resource, wherein said maintaining information comprises: storing the first number in a register; decrementing the first number on each clock cycle until the first number equals zero; during said decrementing: incrementing a second number if the respective hardware resource was in use when the respective hardware strand requested use of the respective hardware, wherein the second number is a number of times that the respective hardware resource was in use when the respective hardware strand requested use of the respective hardware resource; comparing the second number to a threshold; and generating an interrupt if the second number exceeds the threshold; and performing one or more load-balancing operations in response to the interrupt, wherein said performing the one or more load-balancing operations comprises moving a software thread associated with the respective strand to a different one of the plurality of processor cores.