Patent ID: 8077602

Claim:
A processor chip, comprising: at least one processor; a plurality of communication ports for directly coupling the processor chip to a plurality of other processor chips via bus connections; and heartbeat signal generation logic for generating a heartbeat signal for broadcasting over the plurality of communication ports to the plurality of other processor chips, wherein the heartbeat signal generation logic transmits queue depth information associated with the plurality of communication ports of the processor chip in the heartbeat signal broadcast over the plurality of communication ports to the plurality of other processor chips, wherein: the heartbeat signal is a signal broadcast by the processor chip to the plurality of other processor chips at a regular interval that is synchronized with a master processor chip through a synchronization process, and the queue depth information comprises queue depth information for the communication ports of the processor chip and queue depth information for communication ports of each of the plurality of other processor chips to which the processor chip is directly coupled, queue depth information for communication ports of other processor chips to which the processor chip is indirectly coupled and which are present in a same processor book or different processor books of a same supernode, and queue depth information of additional processor chips in other supernodes that are indirectly coupled to the current processor chip via the other processor chips in the same processor book and different processor books of the same supernode.