Patent ID: 8583072

Claim:
An integrated circuit comprising: a clock buffer configured to buffer a received clock signal and generate a buffered clock signal; a multiphase local oscillator core coupled to the clock buffer and configured to generate a plurality of oscillator signals in response to the buffered clock signal, each of the plurality of oscillator signals being mutually phase shifted; and a plurality of output buffers, each configured to receive one of the plurality of oscillator signals and to produce an output signal suitable for use in a broadband tuner circuit in response to the one of the plurality of oscillator signals, wherein at least one of: the clock buffer is configured to reduce spurious and harmonic anomalies in the received clock signal; the clock buffer is configured to generate a clock signal output having a stable common-mode voltage; the clock buffer comprises a feedback control mechanism for regulating a common-mode voltage level of the clock buffer output with a reference voltage source; or the clock buffer comprises: a driver stage having a plurality of AC-coupled differential transistor pairs; and an output stage AC-coupled to the driver stage, wherein the output stage is configured to generate the buffered clock signal without introducing DC offsets.