Patent ID: 8551796

Claim:
A manufacturing method of a semiconductor device, comprising the steps of: forming a first conductive layer over a substrate; forming a scan line in a pixel portion and a first wiring in a driving circuit by patterning the first conductive layer; forming a first insulating layer over the scan line and the first wiring; forming a semiconductor layer over the first insulating layer; etching the semiconductor layer to form a region; forming a second insulating layer over the semiconductor layer and the first insulating layer, the second insulating layer having an opening; forming a second conductive layer over the second insulating layer; forming a data line in the pixel portion and a second wiring in the driving circuit by patterning the second conductive layer; and forming a third insulating layer over the data line and the second wiring, wherein the second wiring is electrically connected to the first wiring through the opening, wherein a transistor in the driving circuit comprises the first wiring, the region including a channel formation region, and the second wiring, and wherein the first wiring, the second wiring, and the channel formation region are overlapped with each other.