Patent ID: 7964896

Claim:
A semiconductor heterostructure comprising: a III-V compound semiconductor buffer layer having a first band gap; a III-V compound semiconductor channel layer having a second band gap located on an upper surface of said buffer layer; a III-V compound semiconductor barrier layer having a third band gap located on an upper surface of the III-V compound semiconductor channel layer, wherein said III-V compound semiconductor barrier layer includes a doped region which is located in a lower region of said III-V compound semiconductor barrier layer but is not in direct contact with an interface with the III-V compound semiconductor channel layer, wherein said first and third band gaps are larger than the second band gap; a III-V compound semiconductor cap layer located atop the III-V compound semiconductor barrier layer having an opening providing an exposed portion of the III-V compound semiconductor barrier layer; a dielectric material having a dielectric constant of greater than 4.0 located on sidewalls of said opening, the exposed portion of the III-V compound semiconductor barrier layer and on an upper surface of said III-V compound semiconductor cap layer; a gate conductor located on a portion of said dielectric material filling the opening in the III-V compound semiconductor cap layer; and a source contact and a drain contact which are in contact with at least said III-V compound semiconductor channel layer.