Patent ID: 7800948

Claim:
A semiconductor memory device comprising: a memory cell array having nonvolatile memory cells each including a first electrode, a pair of second electrodes, and an electric charge retention part capable of accumulating and retaining an electric charge, in which stored contents can be read according to a conductive state between the second electrodes that changes depending on a potential of the first electrode and an electric charge amount of the electric charge retention part, and arranged in a row direction and a column direction in a form of a matrix, wherein the first electrodes of the memory cells on the same row are connected to a common word line, one of the second electrodes is connected together between the two adjacent memory cells in the row direction, one of the second electrodes of each of the memory cells on the same column is connected to a common first bit line, the other of the second electrodes of each of the memory cells on the same column is connected to a common second bit line, and the first bit line and the second bit line are alternately arranged; a program row voltage application circuit for selecting a word line connected to a selected memory cell to be programmed in the memory cells and applying a predetermined program row voltage to the selected word line at the time of programming in the selected memory cell; a program column voltage application circuit for selecting a pair of the first bit line and the second bit line connected to the selected memory cell and applying a ground voltage to one of the pair of selected bit lines and applying a predetermined program column voltage to the other of the pair of selected bit lines at the time of programming; and a counter voltage application circuit for applying a counter voltage of an intermediate voltage between the ground voltage and the program column voltage, to an adjacent unselected bit line of the first bit lines and second bit lines, the adjacent unselected bit line not connected to the selected memory cell and adjacent to the selected bit line to which the program column voltage is applied.