Patent ID: 7300868

Claim:
A method of fabricating a damascene interconnection, the method comprising: (a) forming on a substrate a first dielectric layer; (b) forming a capping layer on the first dielectric sublayer; (c) forming a resist pattern over the capping layer to define a first interconnect opening; (d) etching the capping layer and the dielectric layer through the resist pattern to form the first interconnect opening; (e) removing the resist pattern; (f) applying a barrier layer over the capping layer and in the first interconnect opening; (g) forming an interconnection by filling the first interconnect opening with conductive material; (h) planarizing the interconnection to remove excess material; (i) selectively etching a portion of the first dielectric layer damaged by the planarizing step (h); and (j) applying a second dielectric layer to replace the damaged portion of the first dielectric.