Patent ID: 8921191

Claim:
A method for fabricating an integrated circuit comprising: forming a first fin and a second fin adjacent to each other extending from a semiconductor substrate; selectively epitaxially growing a silicon-containing material on the first and second fins to form a first epi-portion overlying a first upper section of the first fin and a second epi-portion overlying a second upper section of the second fin, wherein the first and second epi-portions are spaced apart from each other; forming a first silicide layer overlying the first epi-portion and a second silicide layer overlying the second epi-portion, wherein the first and second silicide layers are spaced apart from each other to define a lateral gap; depositing a dielectric material overlying the first and second silicide layers to form a dielectric spacer that spans the lateral gap; removing the dielectric material that overlies portions of the first and second silicide layers laterally above the dielectric spacer while leaving the dielectric spacer intact; and depositing a contact-forming material overlying the dielectric spacer and the portions of the first and second silicide layers.