Patent ID: 7408393

Claim:
A master-slave flip-flop, comprising: a master latch and a slave latch having respective data inputs, data outputs, and clock inputs, the data output of said master latch connected to the data input of said slave latch, the data input of said master latch being said flip-flop's data input and the data output of said slave latch being said flip-flop's data output, said master and slave latches receiving clock signals (CKM) and (CKS) at their respective clock inputs, each latch arranged to be transparent such that it transfers a logic signal applied to its data input to its data output when its clock signal is in a first state, and to latch a logic signal applied to its data input when its clock signal is in a second state; and a clock buffer arranged to provide clock signals (CKM) and (CKS) such that (CKM) and (CKS) are nominally complementary, said buffer further arranged to skew (CKS) with respect to (CKM) such that said slave latch is made transparent earlier than it would without said skew.