Patent ID: 7629630

Claim:
A memory cell comprising: a transistor including a gate fabricated on a semiconductor substrate and including a source/drain region in said semiconductor substrate disposed adjacent to said gate; an insulating layer provided over said substrate; and a container capacitor including a first metal barrier layer, a lower electrode over said first metal barrier layer, a dielectric layer over said lower electrode, and an upper electrode over said dielectric layer, said upper electrode comprising doped polysilicon, and said lower electrode having a surface aligned over said source/drain region, wherein said lower electrode comprises an electropolished patterned metal layer which is situated fully within said insulating layer, wherein said first metal barrier layer is fully within said insulating layer, wherein said electropolished patterned metal layer has a thickness of about 50 to about 300 Angstroms, and wherein said dielectric layer is in contact with said insulating layer.