Patent ID: 8356144

Claim:
A system comprising: a plurality of floating point execution units compatible with operation according to a plurality of execution threads; a plurality of memory channels each enabled to access at least one Dynamic Random Accessible read/write Memory (DRAM) element; a memory buffer switch unit coupling the floating point execution units to the memory channels; an instruction control unit enabled to control the floating point execution units according to a stream of vector instructions; a processor interface compatible with an x86 processor and enabled to receive the stream of vector instructions from the x86 processor; and wherein the memory buffer switch unit is enabled to consolidate at least two memory requests from the floating point execution units into a single memory access operation directed to one of the memory channels and the at least two memory requests are processed according to a coherency domain implemented by the x86 processor, and wherein respective parts of multiple vector instructions are executed independently by respective ones of the floating point execution units.