Patent ID: 8046567

Claim:
An apparatus, comprising: (a) H hardware contexts, each of which is capable of storing the execution state of one thread in a multi-threaded processor; (b) a context controller for: (i) activating each of A hardware contexts, wherein each of said A active hardware contexts has a priority, (ii) maintaining the E highest priority of said A active hardware contexts as executing hardware contexts, wherein E equals the lesser of A and C, and wherein C equals the maximum number of concurrently executing hardware contexts in said multi-threaded processor, (iii) initiating a context switch in said multi-threaded processor among said E executing hardware contexts on a time-sequenced basis, and (iv) maintaining a table for each of said H hardware contexts that indicates whether each said hardware context is vacant or populated, active or inactive, and executing or not executing; wherein C and H are positive integers and 2<C<H; and wherein A and E are non-negative integers and E≦A≦H; and (c) a memory configured as C memory banks, wherein the access time of said memory is less than or equal to the time required by said multi-threaded processor to execute C instructions, and the instructions and data for each thread are stored in a different one of the C memory banks so that there is no contention between threads for data in the same bank.