Patent ID: 8143933

Claim:
A semiconductor integrated circuit, comprising: a mixer circuit unit configured to receive a first voltage signal having a first frequency, a second voltage signal of a phase inverted from a phase of the first voltage signal, a third voltage signal of a phase orthogonalized to the phase of the first voltage signal, and a fourth voltage signal of a phase inverted from the phase of the third voltage signal, and receive a fifth voltage signal having a second frequency, a sixth voltage signal of a phase inverted from a phase of the fifth voltage signal, a seventh voltage signal of a phase orthogonalized to the phase of the fifth voltage signal, and an eighth voltage signal of a phase inverted from the phase of the seventh voltage signal, and add the second frequency to or subtract the second frequency from the first frequency to make four current signals by performing mixing and voltage-current conversion using the first to eight voltage signals, to output the four current signals from a predetermined output channels; and a ½-frequency divider unit configured to carry out ½-frequency division by using the four current signals from the mixer circuit unit, and output a first to a fourth output signal of four phases obtained by dividing into two the four signals which are obtained by frequency addition or subtraction of the first frequency and the second frequency in the mixer circuit unit, the four phases of the first to fourth output signals comprising two phases orthogonalized to each other, and an other two phases obtained respectively by inverting the the orthogonalized phases, wherein the predetermined output channels of the mixer circuit unit are directly connected to input channels of the ½-frequency divider unit and a bias current flows on the predetermined output channel.