Patent ID: 7987389

Claim:
A system for testing sleep and wake functions of a computer comprising a motherboard, the system comprising: a test device communicating with the motherboard, the test device comprising a timing module, a counting module, and a switch module; and a test software installed on the motherboard, the test software comprising: an initialization unit to set the number of test cycles and a delay time, write the delay time into the timing module, and reset a value stored in the counting module to zero; a signal transmission unit to transmit a timing signal to the timing module, wherein the timing module begins to count down the delay time after receiving the timing signal, and transmits a counting signal to the counting module and a closing signal to the switch module after the delay time, the counting module increments the value by one after receiving the counting signal, and sends out the incremented value; and a comparison unit to use integer division to divide the value received from the counting module by 2 to obtain a quotient, and compare the quotient to the number of test cycles, wherein if the quotient is less than the number of test cycles, the signal transmission unit transmits a timing signal to the timing module again, and if the quotient is equal to the number of test cycles, the test ends; wherein the switch module is connected to a first signal pin and a second signal pin of the motherboard, and an operation system of the computer sets that receiving a control signal means executing an operation of putting the computer to sleep or waking the computer up; and wherein the switch module executes a closing operation after receiving the closing signal, the first signal pin is electrically connected to the second signal pin to generate the control signal, the computer enter a sleep state or wakes up from a sleep state after receiving the control signal.