Patent ID: 7822110

Claim:
A system comprising: a transmitter; a receiver coupled to the transmitter, wherein the receiver is configured to compare a received data stream to an expected data stream and record errors; a digital communications link including a plurality of lanes through which the transmitter is coupled to the receiver; and a processor coupled to each of the transmitter and the receiver, wherein in response to the receiver detecting an error in a selected lane of the plurality of lanes, the processor is configured to: switch the selected lane from an operating mode to a test mode; perform an eye scan of the selected lane; analyze the eye scan to determine a resulting sample phase, a high voltage threshold, and a low voltage threshold; convey an indication to each of the transmitter and the receiver to remove the selected lane from service, in response to determining measured voltage and/or time margins of the eye scan found during said analyzing do not satisfy predetermined conditions; and convey the resulting sample phase, high voltage threshold, and low voltage threshold to the receiver if the selected lane is not removed from service; wherein the receiver is configured to: receive the resulting sample phase, high voltage threshold, and low voltage threshold conveyed from the processor; sample the selected lane at the received sample phase to obtain a resulting voltage sample; and compare the resulting voltage sample to the received high and low voltage thresholds to determine whether the resulting voltage sample represents a logic “0” or a logic“1”.