Patent ID: 8730072

Claim:
A device, comprising: an interleaved analog to digital converter (ADC) having: a first switching circuit coupled to an input line of the ADC; a first sub-converter coupled to the first switching circuit; a second sub-converter coupled to the first switching circuit; calibration circuitry configured to adjust a bandwidth of at least one of the first and the second sub-converter, the calibration circuitry including: a test signal generator configured to generate a test signal to test the bandwidth of at least one of the first and the second sub-converter, the test signal having a test frequency and configured to be applied to at least one of the first and second sub-converter; and a first control circuit configured to adjust a bulk voltage of a transistor in the first switching circuit in response to the test of the bandwidth of at least one of the first and the second sub-converter; and a calculation block configured to compare test data of the first and second sub-converters, and to provide a control signal to said first control circuit based on said comparison, wherein the first control circuit is configured to adjust the bulk voltage based on the control signal.