Patent ID: 8645893

Claim:
A method of generating a layout of an integrated circuit, the layout incorporating standard cells defining functional components of the integrated circuit and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit, the method comprising: providing the memory compiler with a memory architecture specifying a definition of circuit elements and data defining rules for combining those circuit elements in order to generate memory instances conforming to the memory architecture; receiving input data specifying one or more properties of a desired memory instance; employing the memory compiler to generate the desired memory instance based on said input data such that the desired memory instance conforms to said memory architecture; providing a standard cell library, each standard cell within the standard cell library defining a corresponding functional component; in an integration enhancement mode of operation of the memory compiler, causing the memory compiler to reference at least one property of the standard cell library in order to generate the desired memory instance in a form that will reduce an area overhead associated with a boundary between that desired memory instance and surrounding standard cells when that desired memory instance is integrated into the layout; and generating the layout by populating standard cell rows extending in a first direction with standard cells selected from said standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.