Patent ID: 7289307

Claim:
An ESD protection circuit comprising: a first ESD detection circuit comprising three terminals, the first terminal of the first ESD detection circuit coupled to a first input terminal, the second terminal of the first ESD detection circuit coupled to a ground terminal, the third terminal of the first ESD detection circuit outputting a first ESD detection signal; a second ESD detection circuit comprising three terminals, the first terminal of the second ESD detection circuit coupled to a second input terminal, the second terminal of the second ESD detection circuit coupled to said ground terminal, the third terminal of the second ESD detection circuit outputting a second ESD detection signal; a trigger current generating circuit comprising five terminals, the first terminal of the trigger current generating circuit coupled to said first input terminal, the second terminal of the trigger current generating circuit coupled to said ground terminal, the third terminal of the trigger current generating circuit receiving said first ESD detection signal, the fourth terminal of the trigger current generating circuit receiving said second ESD detection signal, the fifth terminal of the trigger current generating circuit outputting a trigger signal; a lateral bipolar junction transistor receiving said trigger signal through its base terminal; and a stacked MOS circuit comprising a first NMOS, a second NMOS and a first resistor, wherein the drain of said first NMOS is coupled to both said first input terminal and the collector of said lateral bipolar junction transistor, the gate of said first NMOS is coupled with the first terminal of said first resistor, the source of said first NMOS is coupled with the drain of said second NMOS, the source of said second NMOS is coupled to both said ground terminal and the emitter of said lateral bipolar junction transistor, the gate of said second NMOS is also coupled to said ground terminal, the base terminals of said first NMOS and said second NMOS are also coupled together to said ground terminal, and the second terminal of said first resistor is coupled to said second input terminal; wherein as an ESD voltage coupled to said first input terminal is greater than a specific level, said trigger current generating circuit will output said trigger signal such that said stacked MOS circuit is turned into an ESD path to discharge said ESD voltage.