Patent ID: 7349276

Claim:
A readout circuit comprising: a sense amplifier circuit configured to sense a data stored in a memory cell transistor based on a current flowing through said memory cell transistor and a reference current flowing through a dummy cell transistor; and a voltage control circuit configured to apply a first voltage to a gate of said dummy cell transistor in a read operation, wherein said memory cell transistor has a control gate and a floating gate, and said voltage control circuit sets said first voltage such that a voltage between said gate and a source of said dummy cell transistor is lower than a second voltage between said control gate and a source of said memory cell transistor, wherein a capacitance between said control gate and said floating gate is C 1 , a capacitance between said floating gate and a substrate surface is C 2 , and said voltage control circuit sets said first voltage to be (C 1 /(C 1 +C 2 )) times said second voltage.