Patent ID: 7087532

Claim:
A method of forming an integrated circuit structure in a structure layer disposed above a substrate comprising the steps of: Forming a hardmask layer disposed above said structure layer; Forming a protective layer above said hardmask layer; Forming a temporary layer above said protective layer; Patterning said temporary layer in a set of pillars in positions related to positions of said structures; Forming a conformal layer over said set of pillars, said conformal layer having a top portion on top of said pillars, sidewalls adjacent to sides of said set of pillars and a horizontal portion extending between members of said set of pillars and disposed directly on top of said protective layer; Removing at least said top portion of said conformal layer; Removing said set of pillars, whereby said protective layer in locations beneath said set of pillars is exposed; Etching said protective layer, using said sidewalls as a mask, thereby defining a first set of hardmask regions in said protective layer; Etching said hardmask layer using said first set of hardmask regions in said protective layer as hardmask, thereby defining a second set of hardmask in said hardmask layer that are symmetric on opposite sides of said sidewalls; and Etching said structure layer using said second set of hardmask, thereby forming said structures.