Patent ID: 7205216

Claim:
A method of fabricating semiconductor wafers, comprising: providing a plurality of semiconductor wafers, wherein the plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer, and wherein the first semiconductor wafer is located directly adjacent to the second semiconductor wafer such that no additional semiconductor wafers of said plurality of semiconductor wafers are located between a topside of the first semiconductor wafer and a backside of a portion of the second semiconductor wafer; providing a relationship between a plurality of values for an electrical characteristic and a plurality of materials; choosing a material from the plurality of materials existing in said relationship; forming a substructure comprising the material placed directly between said topside of the first semiconductor wafer and said backside of a portion of the second semiconductor wafer, wherein a gas occupies an entire space between said topside of said first semiconductor wafer and a first side of said material; and placing the plurality of semiconductor wafers into a furnace for processing, wherein the furnace comprises an elevated temperature that in combination with said material results in a value for the first semiconductor wafer of the electrical characteristic that corresponds to said material in said relationship.