Patent ID: 7652904

Claim:
A semiconductor memory device having a square planar shape, and having first and second sides extending in a first direction and third and fourth sides extending in a second direction intersecting with the first direction, the semiconductor memory device comprising: first and second bus regions extending in the first direction; a third bus region laid out along a center line separating the semiconductor memory device into two in the first direction; a first cell region laid out between the first side and the first bus region; a second cell region laid out between the second side and the second bus region; a third cell region laid out between the first bus region and the second bus region and located at the third side seen from the third bus region; a fourth cell region laid out between the first bus region and the second bus region and located at the fourth side seen from the third bus region; and a data input/output pad string laid out along the third bus region, wherein the data input/output pad string includes first and second groups each including n data input/output pads, the semiconductor memory device performs a data input operation or a data output operation using the first group without using the second group, when an input/output data width is set to n bits, and the semiconductor memory device performs the data input operation or the data output operation using the first and second groups in parallel, when the input/output data width is set to 2n bits.