Patent ID: 8281272

Claim:
A method to produce an integrated circuit layout design comprising: providing in non-transitory storage a pPar parent cell that includes one or more pPar instances and that specifies one or more corresponding input parameter values; producing a graphical representation on a computer display screen of a first schematic design that includes a pPar parent instance; instantiating in non-transitory storage a parameterized cell supermaster that corresponds to the pPar parent cell; determining whether a core layout cell is stored in non-transitory storage that corresponds to the parameterized cell supermaster and the one or more corresponding input parameter values; in response to determining that such a core layout cell is stored, filling a first parameterized cell submaster with an instance of the stored core layout cell; and in response to determining that such a core layout cell is not stored, using program code associated with the parameterized cell supermaster, to generate one or more geometries associated with the one or more pPar instances, and to generate a core layout cell that specifies layout of the one or more generated geometries, and to fill the first parameterized cell submaster with an instance of the generated core layout cell; and in response to generating the core layout cell, storing the generated core layout cell in non-transitory storage.