Patent ID: 8015231

Claim:
A data processing apparatus for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result, the data processing apparatus comprising: multiplier logic circuitry for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors; half adder logic circuitry for receiving a plurality of most significant bits of the pair of 2n-bit vectors and to produce a corresponding plurality of carry and sum bits representing said plurality of most significant bits; first adder logic circuitry for performing a first sum operation in order to generate a first rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition, the first adder logic circuitry being arranged to use as the m most significant bits of the pair of 2n-bit vectors the corresponding m carry and sum bits, and to take the remaining 2n-m least significant bits of the pair of 2n-bit vectors directly from the 2n-bit vectors, with the least significant of the m carry bits replaced with a rounding increment value prior to the first adder logic performing the first sum operation, wherein n and m are integers and 2n is greater than m; second adder logic circuitry for performing a second sum operation in order to generate a second rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment injected at a second predetermined rounding position appropriate for an overflow condition, the second adder logic circuitry being arranged to use as the m−1 most significant bits of the pair of 2n-bit vectors the corresponding m−1 carry and sum bits, and to take the remaining 2n-m+1 least significant bits of the pair of 2n-bit vectors directly from the 2n-bit vectors, with the least significant of the m−1 carry bits replaced with the rounding increment value prior to the second adder logic performing the second sum operation; and selector logic circuitry for deriving the n-bit result from either the first rounded result or the second rounded result.