Patent ID: 8183895

Claim:
A clock dividing circuit comprising: a control logic unit which receives a clock signal and outputs an enable signal and a data signal based on a division ratio; and a flip-flop which generates a divided clock signal based on the clock signal, the enable signal and the data signal, the flip-flop comprising: a first inverter which inverts the data signal at a first edge of the clock signal; a first latch which inverts an output signal of the first inverter and latches the output signal of the first inverter at a second edge of the clock signal; a second inverter which inverts an output signal of the first latch at the second edge of the clock signal; and a second latch which inverts an output signal of the second inverter to output the divided clock signal and latches the output signal of the second inverter based on the enable signal and the first edge of the clock signal, wherein the control logic unit comprises a counter which outputs a count value based on the first edge of the clock signal and has a maximum count value corresponding to the division ratio, wherein when the division ratio is an even number, the control logic unit sets the enable signal to a high level; and when the division ratio is an odd number, the control logic unit sets the enable signal according to a relationship between the count value and the division ratio.