Patent ID: 8601355

Claim:
A decoding circuit, comprising: a turbo decoder configured to receive a plurality of input systematic bit soft information values and a plurality of input parity bit information values, and to generate a plurality of output systematic bit soft information values and a plurality of hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the plurality of input systematic bit soft information values, the plurality of input parity bit soft information values, and the plurality of output systematic bit soft information values; to determine a plurality of initial forward metrics; to determine a plurality of initial backward metrics; to determine a plurality of branch metrics as a function of the plurality of input parity bit soft information values and the plurality of output systematic bit soft information values; to determine a plurality of output parity bit soft information values based on the branch metrics, the plurality of initial forward metrics, and the plurality of initial backward metrics; and to provide the plurality of output parity bit soft information values as a signal output.