Patent ID: 7563687

Claim:
Process for manufacture of a MIM capacitor in an interconnection layer of an integrated circuit, comprising: Deposition of a first metallic layer on one of a lower interconnection dielectric layer or a substrate; Deposition of a first insulator layer on the first metallic layer; Deposition of a second metallic layer on the first insulator layer; Formation of an upper electrode of the MIM capacitor by removing part of the second metallic layer and expose a top surface of the first insulator layer; Deposition of a second insulator layer covering the upper electrode and top surface of the first insulator layer; Etching of the second insulator layer to uncover the upper surface of the first insulator layer except at a corner location adjacent the upper electrode where second insulator layer material remains to form a spacer surrounding the upper electrode; Formation of a lower electrode and a dielectric of the MIM capacitor by removing part of the first metallic layer and that part of the first insulator layer not covered by the upper electrode or the spacer; Deposition of a third metallic layer and formation of an interconnection line by removing part of this third metallic layer; and Deposition of a passivation layer which covers the MIM capacitor, spacer and the interconnection line.