Patent ID: 8253468

Claim:
A clock generating circuit comprising: a first current generating circuit configured to generate a first current; a first voltage generating circuit configured to generate a first voltage which increases or decreases according to a phase of a clock signal as time advances by the first current; a first comparing circuit configured to compare the first voltage with a first threshold voltage to generate a first comparison result; a second current generating circuit configured to generate a second current; a second voltage generating circuit configured to generate a second voltage which increases or decreases according to the phase of the clock signal as time advances by the second current; a second comparing circuit configured to compare the second voltage with a second threshold voltage to generate a second comparison result; a clock output circuit configured to generate the clock signal whose phase inverts in synchronization with timing when the first and the second comparison results change; and a control circuit configured to generate a random number and configured to variably control at least one of the first current, the second current, the first threshold voltage and the second threshold voltage according to the random number.