Patent ID: 6878996

Claim:
An integrated MOS power transistor, comprising: a p-conducting substrate region; an n-conducting semiconductor region disposed in said p-conducting substrate region; at least one p-conducting source electrode zone disposed in said n-conducting semiconductor region; at least one p-conducting drain electrode zone disposed in said n-conducting semiconductor region; at least one n-conducting gate electrode zone; at least one p-conducting doped bulk zone disposed in a manner isolated from said source electrode zone; said source electrode zone, said drain electrode zone, said gate electrode zone and said doped bulk zone formed in a lateral direction such that said gate electrode zone lies between said source electrode zone and one of said drain electrode zone and said doped bulk zone; said source electrode zone, said drain electrode zone, said gate electrode zone, and said doped bulk zone define a PMOS transistor; a PMOS source-bulk switching transistor being driven separately from said PMOS transistor and having a control gate, said PMOS source-bulk switching transistor is integrated between said doped bulk zone and said source electrode zone in said n-conducting semiconductor region; switch-on means connected to said control gate of said PMOS source-bulk switching transistor, during normal operation of said PMOS transistor where said PMOS transistor having a source-drain voltage higher than a voltage at said doped bulk zone, said switch-on means applying a gate voltage being less than the voltage at said doped bulk zone to said control gate of said PMOS source-bulk switching transistor; and switch-off means connected to and switching off said PMOS source-bulk switching transistor, said switch-off means switches off said PMOS source-bulk switching transistor in a reverse operation of said PMOS transistor, when the source-drain voltage of said PMOS transistor being lower than the voltage at said doped bulk zone.