Patent ID: 8575716

Claim:
An integrated circuit device, comprising: memory array circuitry trench isolation within a memory array region and peripheral circuitry trench isolation within a region peripheral to the memory array region, the memory array trench isolation comprising a first silicon dioxide-comprising liner and a second silicon dioxide-comprising material laterally inward of the first silicon dioxide-comprising liner, the peripheral trench isolation comprising a third silicon dioxide-comprising liner and a fourth silicon dioxide-comprising material laterally inward of the third silicon dioxide-comprising liner; and the second silicon dioxide-comprising material of the memory array trench isolation having an elevationally outermost portion of greater density than an elevationally inner portion, the fourth silicon dioxide-comprising material of the peripheral trench isolation being of uniform density that is the same as the density of the elevationally outermost portion of the second silicon dioxide-comprising material of the memory array trench isolation.