Patent ID: 7149915

Claim:
A microcomputer comprising: a CPU; a watch-dog timer for outputting an abnormality detection signal when a clear signal input from the CPU stops over a predetermined supervisory time; a sleep control timer for outputting a recovery command signal for recovering the CPU to a normal operation mode when a predetermined recovery time passes after the CPU changes to a low power-consumption mode; a common counter for counting an operation clock inputted in both the low power-consumption mode and the normal operation mode, a count value of the common counter being cleared based on the clear signal input; a supervisory time register for holding a count setting value of the operation clock according to the predetermined supervisory time; a recovery time register for holding a count setting value of the operation clock according to the predetermined recovery time; a supervisory comparing means which is activated in the normal operation mode and outputs the abnormality detection signal based on a result of comparison between the count value of the common counter and the count setting value of the supervisory time register; and a recovery comparing means which is activated in the low power-consumption mode and outputs the recovery command signal based on a result of comparison between the count value of the common counter and the count setting value of the recovery time register.