Patent ID: 8612500

Claim:
Method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal arithmetic logic unit structure comprises an inverter, a first adder, a second adder, a first pre-sum logic, a second pre-sum logic, a first multiplexer, a second multiplexer, a third multiplexer, a digit end around carry network (DEACN), and an XOR gate, wherein the decimal operands are in hexadecimal sign magnitude format with each decimal digit of the operands represented by a code of four bits, said method comprising: preparing, by the inverter, the first adder, and the first multiplexer, the two decimal operands for a mathematic operation; generating, by the first pre-sum logic, preliminary result digits by digitwise adding the digits of the prepared operands, under an assumption that digit carry-ins is zero; generating, by the second pre-sum logic, preliminary result digits by digitwise adding the digits of the prepared operands, under an assumption that digit carry-ins is one; determining, by the DEACN, digit carry-outs, which digit carry-outs are digit carry-ins for the next higher digits respectively, wherein an end around carry is generated that is the digit carry-out of the most significant digit that simultaneously is the carry-in of the least significant digit; digitwise selecting, by the second multiplexer, preliminary result digits to generate an intermediate result, wherein the preliminary result digits are selected, whose digit carry-in assumptions match the digit carry-ins; selectively bitwise inverting, by the XOR gate, said intermediate result in case of a subtraction, wherein said selectively bitwise inversion depends on said end around carry; and selectively correcting, by the second adder and the third multiplexer, digits of said selectively inverted intermediate result to obtain the magnitude result of the mathematic operation, wherein said selectively correction in case of a subtraction depends on the value of the end around carry and the value of the digit carry-out of the particular digit, and in case of an addition depends on the value of the digit carry-out of the particular digit.