Patent ID: 8665653

Claim:
A device comprising a plurality of channels that are configured to output respective data signals independently of each other; and the device further comprising: a plurality of sets of first terminals, the sets being allocated to the channels, respectively, and receiving control information for respective channels independently of each other, the control information for each of the channels including a read command indicative of a read operation and an address designating at least one memory cell to be subject to the read operation; a plurality of second terminals that are allocated to the channels, respectively; a plurality of data output circuits that are allocated to the channels, respectively, and coupled to respective ones of the second terminals; and a plurality of output timing adjustment circuits that are allocated to the channels, respectively, and temporarily store respective adjustment data independently of each other, each of the output timing adjustment circuits being configured to control, when an associated one of the data output circuits drives an associated one of the second terminals in response to data read out from an associated memory cell, the associated one of the data output circuits to initiate driving the associated one of the second terminals at an individually adjustable timing responsive to an associated one of the adjustment data.