Patent ID: 8441067

Claim:
A power device with low parasitic transistor, comprising: a substrate including a body, a first semiconductor layer, and a second semiconductor layer disposed on the substrate in sequence, wherein the substrate is divided into an active region and a peripheral region; a trench type transistor located in the active region of the substrate, and the trench type transistor comprising: a first recessed gate structure embedded into the second semiconductor layer and extending into the first semiconductor layer; and a source doped region located at two sides of the first recessed gate structure, wherein the first semiconductor layer serves as a drain doped region of the trench type transistor; a first heavily doped region disposed in the second semiconductor layer within the active region, and the first heavily doped region being disposed at one side of the source doped region, wherein the first heavily doped region and the second semiconductor layer have the same conductive type, and the first heavily doped region does not contact with the source doped region; a first contact plug disposed in the second semiconductor layer, and the bottom of the first contact plug contacting the first heavily doped region; and a source wire contacting the top of the drain doped region within the active region and the top of the first contact plug.