Patent ID: 7702004

Claim:
An integrated circuit, comprising: a transmitter including a transmitter buffer input, wherein the transmitter is configured to transmit a first signal; a receiver including a receiver buffer output; a differential buffer coupled between the transmitter buffer input and the receiver buffer output, wherein the differential buffer is configured to accept a second signal from the transmitter buffer input and to adjust the second signal in phase and amplitude to reduce the first signal at the receiver buffer output; and a training circuit configured to set phase and gain characteristics of the differential buffer by determination of which phase and amplitude characteristics reduce peak-to-peak noise at the receiver buffer output in response to introduction of a training signal to the transmitter and wherein the training circuit further comprises: one or more analog-to-digital converters coupled between the finite state machine and the differential buffer; and a peak detector coupled to the receiver buffer output, and a finite state machine coupled to the peak detector and configured to vary the gain characteristics of the differential buffer by reading a parameter from the peak detector, via the analog-to-digital converters, and is configured to set a value on the analog-to-digital converters to control one or more variable current sources of the differential buffer based, at least in part, on the read parameter.