Patent ID: 7956669

Claim:
An apparatus comprising: circuitry to be power-gated; a transistor configured to operate as a switch having a double gating arrangement, said transistor comprising two gates, a first drain-source terminal, and a second drain-source terminal, a first of the two gates being configured to perform a power switch function, a second of the two gates being configured to perform a clamping function, said first drain-source terminal being coupled to said circuitry to be power-gated; and a voltage supply coupled to said first and second gates, said voltage supply being configured to: activate said first gate to turn said transistor ON in an active mode; deactivate said first gate in a standby mode; deactivate said second gate in said active mode; and activate said second gate to perform said clamping function in said standby mode; wherein said second of the two gates is electrically interconnected with said first drain-source terminal to form one of a virtual ground and a virtual voltage supply.