Patent ID: 7366023

Claim:
A flash memory device comprising: first to n th banks sharing an I/O line; a page buffer unit commonly connected to a bit line of the first to n th banks, for buffering data to be transmitted to the first to n th banks; a first X-decoder connected to a word line of the first banks, for applying a driving voltage to the word line of the first banks; a n th X-decoder connected to a word line of the n th banks, for applying a driving voltage to the word line of the n th banks; a program/erase pump for generating a program voltage/erase voltage applied to the first to n th banks; a first switch unit that switches the program voltage/erase voltage and transmits the voltage to the first banks and the first X-decoder; and a n th switch unit that switches the program voltage/erase voltage and transmits the voltage to the n th banks and the n th X-decoder.