Patent ID: 7215597

Claim:
A memory device, comprising: an array of memory cells; a control logic for writing data to and reading data from the array of memory cells, the control logic comprising a first interface; an input/output section for exchanging data, address and control signals with a circuit external to the memory device, the input/output section comprising a second interface for sending signals to and receiving signals from the first interface of the control logic; and a synchronizing facility connected to the first interface of the control logic and to the second interface of the input/output section for synchronizing a clock signal of the first interface of the control logic and a clock signal of the second interface of the input/output section, wherein the control logic comprises a third interface, the array of memory cells comprises a fourth interface for sending signals to and receiving signals from the third interface of the control logic, and the synchronizing facility is connected to the third interface of the control logic and to the fourth interface of the of the array of memory cells for synchronizing a clock signal of the third interface of the control logic and a clock signal of the fourth interface of the array of memory cells.