Patent ID: 8873307

Claim:
A device comprising: at least one bit line coupled to at least one memory cell; at least one data line; a first transistor coupled between the bit line and the data line, the first transistor forming, when turned ON, an electrical path between the bit line and the data line; a control circuit supplying an active signal to the first transistor to turn the first transistor ON, the active signal taking a first level in a data read mode and a second level in a data write mode, the first level being different from the second level, the data read mode being such that data stored in the memory cell is read out onto the data line via the bit line and the first transistor; and a write driver including an output node that is coupled to the data line, the write driver being configure to drive, in the data write mode without assertion of data masking, the output node to write data into the memory cell through the data line, the first transistor and the bit line, and configured to bring, in the data write mode with assertion of the data masking, the output node into a high-impedance state.