Patent ID: 8122231

Claim:
A method of processing a Single Instruction Multiple Data (SIMD) instruction when the SIMD instruction requires a data path width greater than an active data path width in a SIMD data processor, comprising: executing one or more operations in parallel in at least two arithmetic logic units of the data processor, so as to process data of a first width; upon execution of a mode change instruction, placing a first one of the two arithmetic logic units into a reduced power state; and while the first arithmetic logic unit is in the reduced power state, executing one or more instructions in a second one of the two arithmetic logic units, so as to process data of a second width smaller than the first width; receiving a SIMD instruction calling for processing of data of the first width; expanding the SIMD instruction in response to the received SIMD instruction calling for processing of data of the first width to at least two instructions calling for processing of data of the second width; and executing the at least two instructions resulting from expansion in sequence through the second arithmetic logic unit.