Patent ID: 7605017

Claim:
A method of manufacturing a semiconductor device including a semiconductor substrate, a hetero semiconductor region formed of a semiconductor material having a band gap width different from that of the semiconductor substrate and hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, a first electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate, the method comprising: forming a first mask layer on the hetero semiconductor region; forming the first electric field alleviation region and the heterojunction driving end using at least a portion of the first mask layer, the first electric field alleviation region contacting the semiconductor substrate and the gate insulation layer and implanting impurities in a portion of the semiconductor substrate not covered by the first mask layer through an ion implantation process when the first electric field alleviation region is formed.