Patent ID: 7968387

Claim:
A method of fabricating a thin film transistor (TFT) comprising: forming a polysilicon active layer on a substrate; forming a gate insulating layer to cover the polysilicon active layer; forming a first gate electrode on the gate insulating layer; doping a first impurity into the polysilicon active layer to form a channel region on which the first gate electrode is superposed and a pair of first lightly doped drain (LDD) regions disposed at the both sides of the channel region; forming a second gate electrode on the first gate electrode to completely cover the first gate electrode; doping a second impurity into the polysilicon active layer to form a pair of second LDD regions having an impurity concentration higher than an impurity concentration of the first LDD regions, and source and drain regions opposite to each other interposing the channel region, the first LDD regions and the second LDD regions between them; and forming source and drain electrodes connected to the source and drain regions, respectively.