Patent ID: 7982471

Claim:
A passive capacitance measurement system comprising: a successive approximation register (SAR) analog-to-digital conversion circuit (ADC) including a comparator, an output of the comparator being coupled to an input of SAR logic and switch circuitry which produces a digital output on a digital bus; and a passive network for coupling to a capacitor to be measured to the SAR ADC, the passive network including: a measurement conductor coupled to a first terminal of the capacitor; a first switching circuit included in both the passive network and the SAR ADC for coupling the measurement conductor to a plurality of conductors included in both the passive network and the SAR ADC; a divider/capacitive digital-to-converter (CDAC) included in both the passive network and the SAR ADC, the divider/CDAC including a plurality of weighted capacitors each having a first terminal coupled to a corresponding one of the plurality of conductors, respectively, and each having a second terminal coupled by a first conductor to a first input of the comparator; a first switch having a first terminal coupled the first input of the comparator, wherein the SAR logic and switch circuitry being coupled to control the plurality of conductors during a SAR conversion.