Patent ID: 7190541

Claim:
A trans-resistance circuit for rapidly enabling one of a pair of transistors of a write driver and disabling the other of the pair of transistors of the write driver responsive to a data signal, comprising: circuitry for charging a first node responsive to a first state of the data signal and actively discharging the first node responsive to a second data signal; and circuitry for charging a second node responsive to the second state of the data signal and actively discharging the second node responsive to the first data signal. wherein said circuitry for charging the first node comprises: a first current source; a second current source coupled to the first node; a third current source; a fourth current source coupled between the second node, where each current source supplies the same amount of current; a first transistor for selectively providing a path between the first current source and the first node, responsive to the data signal; a first resistor coupled between the third current source and the first node; a second transistor for selectively providing a path between the second node, responsive to the data signal, such that the data signal enables one of the first and second transistors and disables the other of said first and second transistors; and a second resistor coupled between the third current source and the second node, such that current is drawn through said first resistor when said first transistor is disabled and the second transistor is enabled, thereby charging the first node, and current is drawn through the second resistor when said first transistor is enabled and the second transistor is disabled ,thereby charging the second node.