Patent ID: 7433239

Claim:
A memory with reduced bitline leakage current comprising: a plurality of bitlines; a plurality of wordlines; a plurality of access transistors each having a control terminal coupled to one of the wordlines, and an output terminal coupled to one of the bitlines; a plurality of memory cells each having outputs coupled to an input terminal of one of the access transistors so that the access transistors coupled to the outputs from one of the memory cells share one of the wordlines and are coupled to different bitlines; a plurality of wordline drivers each being coupled to a respective wordline and generating a variable voltage at an output based upon wordline driver control inputs and a variable reference voltage received at a reference supply node; a group of voltage supply lines being coupled to a group of the wordline drivers for inducing the variable reference voltage on the reference supply node; and a voltage switching circuit for generating the variable reference voltage in response to a reference control input.