Patent ID: 7003704

Claim:
A Built In Self Test (BIST) circuit for testing memory in an integrated circuit, said integrated circuit implementing a row and column redundancy calculation for enabling replacement of a defective row or column of memory cells, the BIST circuit comprising: means for testing rows comprising memory cells in said memory and for detecting for a first single memory cell failure in a row; encoder device for determining a bit location of a first single memory cell failed and storing an encoded value representing said bit location of said failed memory cell; means for detecting whether more than one single cell failure has occurred for a tested row, and, in response to detecting more than one single cell failure for said tested row, said means generating a bit indicating that row as a defective row to be replaced; and, means for comparing said encoded value of said location determined for a failed memory cell detected in a subsequent tested row, with said stored encoded value associated with said first single memory cell failed, said means generating a bit indicating defective column to be replaced when said encoded bit value location for a failed memory cell of that subsequent row is equal to said stored encoded value associated with said first single memory cell failed, whereby given the indication of defective bits set, the defective column corresponding to the encoded bit location of the detected failed memory cell and the defective row of memory is replaced.