Patent ID: 7269707

Claim:
A memory system for storing data to be used by a central processing unit, comprising: a cache memory for caching data, said cache memory responsive to a fetch address for supplying data corresponding to said fetch address if data for said fetch address is stored within and generating a cache miss response if data for said fetch address is not stored within; a read only memory for storing data at a predetermined set of addresses within an address space; a patch address comparator connected to said cache memory and said read only memory, said patch address comparator including at least one writable comparison address register storing an alterable comparison address, a comparator connected to each comparison address register and receiving said fetch address, said comparator determining if said fetch address matches said comparison address of any comparison address register, and an address translator corresponding to each comparison address register for translating a fetch address into a translated address within said address space when said comparator determines said fetch address matches a corresponding comparison address; and circuitry, operable independent of and without interrupting said central processing unit, for supplying said translated address to a memory.