Patent ID: 8119486

Claim:
A method of manufacturing a semiconductor device, comprising: forming at least one isolation region in a substrate, the at least one isolation region defining at least one active region; recessing a desired region of the at least one active region and the at least one isolation region to form a recessed channel trench of a desired depth, the recessed channel trench having a first region in contact with the at least one active region and a second region in contact with the at least one isolation region, and a width of a bottom surface of the recessed channel trench being less than a width of a top surface of the recessed channel trench; annealing the at least one active region and the at least one isolation region wherein the bottom surface of the recessed channel trench, is uplifted the annealing resulting in an increase in an area of the bottom surface of the first region, a reduction in a depth of the bottom surface of the first region, and a width of a bottom surface of the first region being substantially similar to a top surface of the first region, and the annealing process resulting in no change in the second region; and forming a buried gate electrode in the recessed channel trench.