Patent ID: 7184357

Claim:
A decoding circuit in a memory device, the decoding circuit receiving either a specified or unspecified address signal having one or more binary digits, and outputting a control signal having one or more binary digits to control the memory device, wherein the specified address signal is a predetermined address signal for generating a predetermined one of the control signals and wherein the unspecified address signal is not one of the predetermined address signals for generating predetermined control signals, the decoding circuit comprising: gates receiving the specified or unspecified address signal and outputting a control signal to control a CAS latency (CL) or a write recovery time (tWR) of the memory device, wherein, when the specified address signal is inputting to the decoding circuit, the one control signal outputted is corresponding one of the control signals predetermined by the specified address signal, and wherein, when the unspecified address signal is inputted to the decoding circuit, the one control signal outputted is one control signal predetermined for output in case the unspecified address signal is received by the decoding circuit such that the memory device is capable of functioning without substantial reduction of performance characteristics even when the unspecified address signal is received by the decoding circuit.