Patent ID: 7613909

Claim:
A processor having interface circuitry and internal circuitry, the interface circuitry comprising at least one port and the internal circuitry comprising: an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the internal circuitry and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal; wherein the at least one port is arranged to transfer data between the port and circuitry external to the processor in dependence on a second timing signal, and to alter a ready signal in dependence on said second timing signal to indicate a transfer of data with the external circuitry; and the thread scheduler is configured such that said scheduling comprises: starting execution of one or more threads each including one of an input instruction and an output instruction which when executed performs a transfer of data between the at least one port and the internal circuitry, then suspending execution of said one or more threads, and then continuing execution of said one or more threads in dependence on the ready signal.