Patent ID: 7536560

Claim:
An apparatus for performing cryptographic operations, comprising: an x86-compatible microprocessor; a control word, configured to prescribe one of a plurality of cryptographic key sizes to be employed during execution of one of the cryptographic operations, wherein said control word is stored in memory, and wherein a memory location of said control word is prescribed by contents of a register that is referenced by a single atomic cryptographic instruction, wherein said single atomic cryptographic instruction is arranged according to the instruction format for execution on said x86-compatible microprocessor; fetch logic, disposed within said x86-compatible microprocessor, configured to receive said single atomic cryptographic instruction as part of an instruction flow executing on said x86-compatible microprocessor, wherein said single atomic cryptographic instruction prescribes said one of the cryptographic operations, and wherein said single atomic cryptographic instruction references said control word; translation logic, coupled to said fetch logic, configured to translate said single atomic cryptographic instruction into a sequence of micro instructions that directs said x86-compatible microprocessor to perform said one of the cryptographic operations; and execution logic, disposed within said x86-compatible microprocessor and operatively coupled to said single atomic cryptographic instruction, configured to execute said one of the cryptographic operations, said execution logic comprising: a cryptography unit, configured to execute a plurality of cryptographic rounds on each of a plurality of input text blocks to generate a corresponding each of a plurality of output text blocks, wherein said one of a plurality of cryptographic key sizes is provided to a key size controller within said cryptography unit, and wherein said key size controller employs said one of a plurality of cryptographic key sizes during execution of said one of the cryptographic operations.