Patent ID: 7432190

Claim:
A method of manufacturing a semiconductor device, comprising: preparing a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed; forming a first via plug and a first metal line by filling the first via hole and the first trench with a first metal; performing a first CMP process of planarizing the first metal line and the first interlayer insulation layer; forming a second etch stop layer on the first metal line and the first interlayer insulation layer; performing a CMP process of planarizing the second etch stop layer; forming a second interlayer insulation layer on the planarized second etch stop layer; performing a second CMP process of planarizing the second interlayer insulation layer; forming a second via hole and a second trench in the second interlayer insulation layer; forming a second via plug and a second metal line by filling the second via hole and the second trench with a second metal; and performing a third CMP process of planarizing the second metal line and the second interlayer insulation layer.