Patent ID: 7027099

Claim:
A digital image processor comprising: a digital processing unit; an input operable to receive an interlaced video stream; a digital memory unit for storing portions of the interlaced video signal; an output operable to transmit a deinterlaced video stream; a deinterlacing processor implemented upon said digital processing unit, said deinterlacing processor coupled to said input, said output, and said digital memory unit, said deinterlacing processor operable to perform frequency analysis upon said received interlaced video stream in order to generate said deinterlaced video stream having reduced motion artifacts; wherein the deinterlacing processor performs frequency analysis upon a plurality of vertically aligned pixels of a video frame, said video frame including two adjacent video fields to detect a motion artifact; wherein a frequency being analyzed is a spatial frequency; wherein the deinterlacing uses the results of the frequency analysis to reduce the visibility of the motion artifact in the video frame and wherein the deinterlacing processor determines a plurality of motion artifact detection values from the motion artifact; and wherein the deinterlacing processor determines an ultimate detection value for each of the plurality of motion artifact detection values wherein the ultimate detection value is based upon a predetermined digital that has a spatial frequency of 0.5 cycles/line and a number of elements equal to the plurality of vertically aligned pixels.