Patent ID: 7569893

Claim:
A semiconductor device comprising: a semiconductor substrate having a cell region, a core n-channel metal oxide semiconductor (NMOS) region, and a core p-channel MOS (PMOS) region; an isolation layer disposed in the semiconductor substrate to define a cell active region, an NMOS active region, and a PMOS active region in the cell region, the core NMOS region, and the core PMOS region, respectively; a cell gate pattern, an NMOS gate pattern, and a PMOS gate pattern that cross the cell active region, the NMOS active region, and the PMOS active region, respectively; an interlayer-insulating layer disposed on the gate patterns, the interlayer-insulating layer having a storage node contact hole and a bit line contact hole that expose regions of the cell active region adjacent to the cell gate pattern, having NMOS interconnection contact holes that expose regions of the NMOS active region adjacent to the NMOS gate pattern, and having PMOS interconnection contact holes that expose regions of the PMOS active region adjacent to the PMOS gate pattern; a storage node landing pad, a bit line landing pad, and NMOS landing pads having top surfaces lower than a top surface of the interlayer-insulating layer, the storage node landing pad, the bit line landing pad, and the NMOS landing pads contacting the active regions through the storage node contact hole, the bit line contact hole, and the NMOS interconnection contact holes, respectively; a bit line and NMOS metal interconnections disposed on the interlayer-insulating layer, covering top surfaces of the bit line landing pad and the NMOS landing pads, and contacting the bit line landing pad and the NMOS landing pads, respectively; and PMOS metal interconnections disposed to cover top surfaces of the PMOS interconnection contact holes on the interlayer-insulating layer, and having PMOS metal interconnection contacts that protrude downwards to be physically contact the PMOS active region above the PMOS interconnection holes.