Patent ID: 7183600

Claim:
A semiconductor device comprising: a semiconductor substrate disposed in a cell array region and including a plurality of active regions; a plurality of gate trenches formed in each of the plurality of active regions, each of the gate trenches having first inner walls, which face each other in a first direction, which is perpendicular to a second direction in which the active regions extend, and second inner walls, which face each other in the second direction in which the active regions extend; a plurality of gate insulating layers disposed on the first and second inner walls of each of the plurality of gate trenches; a plurality of gate electrodes, each of which extends in the first direction and includes a bottom gate portion, which fills one of the gate trenches, and a top gate portion, which is disposed over the semiconductor substrate; an isolation layer, which contacts the gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches; a plurality of source/drain regions disposed in the semiconductor substrate at both sides of each of the gate electrodes; and a plurality of channel regions disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.