Patent ID: 8406033

Claim:
A memory device, comprising: an array of programmable resistance memory cells; a sense amplifier coupled to the array, which senses changes of voltage or current on bit lines coupled to a selected memory cell; timer circuitry coupled to the array, which measures a time interval which correlates with resistance of the selected cell; and logic responsive to the time interval for the selected cell, to enable refresh logic if the time interval has a duration that falls within a pre-specified range; said refresh logic including logic to determine a data value stored in the selected cell, and to refresh the data value in the selected cell, wherein said logic to determine a data value stored in the selected cell executes a process including storing a first parameter indicating length of the time interval for the selected cell, writing a reference data value to the selected cell, measuring a second time interval which correlates with resistance of the selected cell after said writing, storing a second parameter indicating length of the second time interval, and comparing the first parameter to the second parameter.