Patent ID: 8338967

Claim:
A stress buffering package for a semiconductor component, comprising: at least one electrical element; I/O pads, which are electrically connected to the element; a passivation layer, which protects the electrical element and at least partially exposes the I/O pads, which passivation layer has an upper side that faces away from the electrical element; solder balls, which are electrically connected to the I/O pads; a stress buffering means for absorbing stresses, which is provided between the I/O pads and the solder balls; characterized in that the stress buffering means comprises individual stress buffering elements, in which each stress buffering element substantially absorbs mechanical stresses that are set up in a group comprising at least one solder ball, so that the absorption of stresses by a stress buffering element does not influence a stress buffering effect of the other stress buffering elements.