Patent ID: 7381574

Claim:
A method of forming dual interconnects in manufacturing a magnetoresistive memory cell, the method comprising: providing an intermediate product comprising: a semiconductor substrate including active structures on a surface thereof at least one metallization layer comprising a plurality of metallic lines disposed above the active structures of the semiconductor substrate; a first non-conductive layer comprising a non-conductive material disposed above the metallization layer and including a via contact for conductively contacting a first one of the metallic lines; a magnetoresistive junction element disposed above the first non-conductive layer and conductively connected to the via contact; a metallic hard mask disposed on the magnetoresistive junction element and conductively connected therewith; a second non-conductive layer comprising a non-conductive material disposed above the first non-conductive layer at least in a region over the hard mask and at least in a region over a second one of the metallic lines of the metallization layer; a third non-conductive layer comprising a non-conductive material having etch-selectivity as to the second non-conductive layer disposed at least in a region above the hard mask; and a fourth non-conductive layer disposed at least on the third non-conductive layer; partially opening a first trench to uncover the second non-conductive layer at least above a portion of the hard mask and partially opening a second trench to uncover the second non-conductive layer at least above a portion of the second metallic line in a same opening operation; fully opening the first trench to uncover the hard mask; fully opening the second trench to uncover the second metallic line, wherein fully opening the first trench and fully opening the second trench are performed in a same opening operation; filling the first trench with conductive material; and filling the second trench with conductive material.