Patent ID: 7517807

Claim:
A method for fabricating a semiconductor structure, the method comprising: forming a carbon masking layer on a semiconductor layer; forming a protective layer on the carbon masking layer; forming an opening in the protective layer and the carbon masking layer; processing the semiconductor layer through the opening to form a first processed region in the semiconductor layer; enlarging the opening in the carbon masking layer; performing an additional processing step on the semiconductor layer through the enlarged opening to form a second processed region in the semiconductor layer; performing an additional process to further enlarge the opening in the carbon masking layer; performing an additional processing step on the semiconductor layer through the further enlarged opening to form at least one additional processed region in the semiconductor layer; removing the protective layer; forming a carbon capping layer on the semiconductor layer in the enlarged opening; annealing the semiconductor structure; etching the carbon capping layer, wherein the etching leaves a spacer extending over a channel formed in the additional processed region; depositing a field oxide layer on the semiconductor structure; planarizing the field oxide layer; removing the carbon masking layer and the spacer; and forming a gate dielectric layer on the semiconductor structure.