Patent ID: 8765585

Claim:
A method of forming a semiconductor structure comprising: forming at least one gate structure on a semiconductor substrate, wherein each of said at least one gate structure includes, from bottom to top, a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric; forming a second etch stop layer on said at least one gate structure; forming a stack of a first contact-level dielectric layer and a second contact-level dielectric layer over said second etch stop layer; forming at least one gate contact via hole and at least one source/drain contact via hole within said stack of said first and second contact-level dielectric layers; simultaneously extending said at least one gate contact via hole and said at least one source/drain contact via hole, wherein said at least one source/drain contact via hole is extended through said first contact-level dielectric layer stopping on said second etch stop layer and said at least one gate contact via hole is extended through one of said at least one gate cap dielectric stopping on one of said at least one first etch stop layer, respectively, during said simultaneous extension; and etching exposed portions of said at least one first etch stop layer in said at least one gate contact via hole and etching exposed portions of said second etch stop layer in said at least one source/drain contact via hole.