Patent ID: 8902960

Claim:
An eye diagram scan circuit for a receiver circuit; said receiver circuit providing a first data signal and a primary phase data in response to a received signal, said primary phase data being associated with a data timing of said first data signal; said eye diagram scan circuit being arranged to provide a plurality of eye diagram scan results for synthesizing an eye diagram, and comprising: a control module for providing a phase offset data; a phase interpolator, coupled to said control module and said receiver circuit, for providing an offset timing in response to said phase offset data and said primary phase data; and an access circuit, coupled to said phase interpolator, for providing a second data signal in response to said received signal based on triggering of said offset timing; wherein said first data signal comprises a plurality of first data, said second data signal comprises a plurality of second data, and said control module further provides a said eye diagram scan result for said phase offset data by comparing said first data signal and said second data signal, including: comparing a predetermined number of said first data and said second data.