Patent ID: 7702832

Claim:
An interconnect bus comprising: a bidirectional clock line; and a bidirectional data line configured to carry USB data; wherein a clock signal transmitted over the bidirectional clock line is source synchronous with data transmitted over the bidirectional data line, wherein the clock signal is transmitted over the bidirectional clock line when the interconnect bus is operating in data transmission mode, and wherein the clock signal is not transmitted over the bidirectional clock line when the interconnect bus is operating in static state mode; wherein the data is sampled at least at a rising edge of the clock signal, and wherein the data is not transmitted over the bidirectional data line when the interconnect bus is operating in static state mode; and wherein the interconnect bus is configured to convey USB command/control state information over the clock line and the data line when the interconnect bus is operating in static state mode, and wherein when the interconnect bus is operating in static state mode, respective combinations of static states of the clock line and the data line are driven states that correspond to respective USB command/control state information.