Patent ID: 8399345

Claim:
A method for manufacturing a semiconductor device, comprising: forming an isolation region for defining a plurality of active regions in a silicon substrate; doping p-type impurities in at least one of said plurality of active regions to form a p-type well; forming an NMOS gate electrode above said p-type well via a gate insulating film, traversing said p-type well; implanting n-type impurity ions into said p-type well on both sides of said NMOS gate electrode to form n-type extension regions; forming NMOS gate side wall spacers on side walls of said NMOS gate electrode; implanting n-type impurity ions into said p-type well outside said NMOS gate side wall spacers to form n-type source/drain regions; forming nickel silicide layers in surface regions of said n-type source/drain regions; and implanting Al ions toward said n-type source/drain regions to dope Al in surface regions of said nickel silicide layers.