Patent ID: 8183886

Claim:
A device comprising: multiple interfaces including a physical interface having a D+ lead and D− lead; a first transistor directly coupled between a power supply and the D+ lead; a second transistor directly coupled between the power supply and the D− lead; a detection status register; and a level detector coupled to the D+ and D− leads and configured to detect whether a low signal level or a high signal level is present on the D+ and D− leads, wherein the level detector is further configured to (i) determine a connection status of a universal serial bus (USB) host to the physical interface based upon the detection of the low signal level or the high signal level, and (ii) set a value of the detection status register based upon the determination of the connection status of the USB host to the physical interface, wherein the level detector further includes a detection counter that is configured to count a number of times the level detector detects whether the low signal level or the high signal level is present on the D+ and D− leads.