Patent ID: 7129157

Claim:
A method for fabricating an integrated circuit, the method comprising: fabricating a first circuit part and at least one second circuit part, which is assigned to a specific functionality of the first circuit part, in mutually separate and non-overlapping regions of a common silicon wafer, and forming connecting elements or lines for connecting the first and the at least one second circuit part to one another, wherein during the fabrication of the first and second circuit parts for each exposure plane, with the exception of one or more exposure planes used for fabricating the connecting elements or lines, use is made in each case of a first exposure mask intended for the first circuit part and a second exposure mask intended for the second circuit part, which belong in each case to a first mask and a second mask set, respectively intended for the first and second circuit parts, and wherein the respective exposure masks intended for the first and second circuit parts are arranged on a common reticle, at least for a portion of the exposure planes, and the mask region for the second circuit part is masked out on the reticle, when only exposure steps for fabricating the first circuit part are performed.