Patent ID: 8614483

Claim:
An insulated gate semiconductor device comprising: a first conductivity-type semiconductor substrate; a second conductivity-type base layer formed on a first surface side of the semiconductor substrate; a trench that penetrates the base layer and reaches the semiconductor substrate to divide the base layer into a first base layer and a second base layer, the trench having a predetermined longitudinal direction; a first conductivity-type emitter region formed in the first base layer and in contact with a side surface of the trench in the first base layer; a gate insulation layer formed on a surface of the trench; a gate electrode formed on the gate insulation layer in the trench; an emitter electrode electrically connected to the emitter region; a second conductivity-type collector layer formed in the semiconductor substrate; and a collector electrode formed on the collector layer, wherein the first base layer, where the emitter region is formed, serves as a channel layer, the second base layer, where the emitter region is not formed, serves as a floating layer, the emitter electrode is electrically connected to both the emitter region and the floating layer, an impurity concentration of the floating layer is lower than an impurity concentration of the channel layer, the floating layer has a first conductivity hole stopper layer that is located at a predetermined depth from the first surface of the semiconductor substrate and separated from the first surface of the semiconductor substrate, and the hole stopper layer is at least partially spaced from the gate insulation layer.