Patent ID: 8575987

Claim:
A level shift circuit comprising: a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential; a latch circuit that operates on a power supply of a second potential which is higher than the first potential, the latch circuit having one end thereof connected to an output end of the CMOS inverter circuit and outputting from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal; a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit, and functions to limit the power supply when the input pulse signal assumes at least a ground level; and an initialization circuit that allows the one end of the latch circuit to be short-circuited to the power supply of the second potential by an initialization signal, wherein the power supply circuit comprises a reverse current blocking circuit, the reverse current blocking circuit comprises a blocking MOS transistor inserted between a power supply side of the CMOS inverter circuit and the power supply supplied to the CMOS inverter circuit, a gate of the blocking MOS transistor is coupled to the output pulse signal.