Patent ID: 7928790

Claim:
A programmable delay comprising: a plurality of single delay cells; wherein any of the delay cells comprises a first input and a second input and a first output; wherein the delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell; wherein the first inputs of any delay cells are configured to receive an input signal to be delayed; wherein one of the delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path comprising any of the delay cells arranged downstream of the starting point; wherein the first output of the last delay cell in the chain forms an output of the programmable delay; and wherein any delay cell comprises a second output, wherein the second output of any delay cell out of the plurality of delay cells located downstream of the starting point is configured to assume a first logical state and the second output of any delay cell out of the plurality of delay cells located upstream of the starting point is configured to assume a second logical state.