Patent ID: 7664205

Claim:
A frequency-shift-keying demodulator comprising: a phase shifter configured to shift a phase of an input signal (i(t)) by a predetermined degree and to output a shifted signal (Id(t)); a combining unit configured to combine the input signal (i(t)) and the shifted signal (Id(t)) and to output a corresponding signal (r(t)); and a low-pass filter configured to filter the corresponding signal (r(t)) and to output a low-pass filtered signal (r LP (t)), wherein the bandwidth of said low-pass filter is matched with the bandwidth of a data signal included in said input signal (i(t)); said combining unit including a first, a second and a third adder, and a first and a second square law detector, wherein the first adder is configured to add the input signal (i(t)) and the shifted signal (Id(t)) and to output the first added signal to the first square law detector, the first square law detector being configured to receive the first added signal and to output a first squared signal (r 1 (t)) which is the square of the first added signal, the second adder is configured to subtract the input signal (i(t)) from the shifted signal (Id(t)) and to output the second added signal to the second square law detector, the second square law detector being configured to receive the second added signal and to output a second squared signal (r 2 (t)) which is the square of the second added signal, the third adder is configured to subtract the second squared signal (r 2 (t)) from the first squared signal (r 1 (t)) and to output a third added signal, and the combining unit is configured to output the third added signal as the corresponding signal to the low-pass filter.