Patent ID: 6872999

Claim:
A semiconductor storage device comprising: a plurality of memory cells formed on or over a surface of a semiconductor substrate; a plurality of word lines formed on or over the surface of the semiconductor substrate, each of the word lines being connected to some of the memory cells and selecting memory cells connected to the word line upon application of a select signal to the word line; a plurality of bit lines disposed in a second wiring layer above a first wiring layer in which the word lines are disposed, the bit lines extending along a direction crossing the word lines, each of the bit lines being connected to some of the memory cells and applied with a signal read from the memory cell selected by the word line; a plurality of signal wiring lines partially superposed upon the bit lines and disposed in a third wiring layer above the second wiring layer; and a conductive shield layer disposed in a fourth wiring layer between the second and third wiring layers, the conductive shield layer including there-inside the bit lines in a first area including an area where the bit lines and the signal wiring lines are superposed upon each other, as viewed along a direction vertical to the surface of the semiconductor substrate, openings being formed through the conductive shield layer in areas where the bit lines are not disposed.