Patent ID: 7417567

Claim:
A trace receiver receiving a plurality of signals comprising: a first data path including a plurality of first variable delays, each receiving a corresponding one of said plurality of signals, a first multiplexer having a plurality of inputs each connected to a corresponding one of said first variable delays and having at least one output, said first multiplexer connecting a selected one of said inputs to a corresponding one of said at least one output, a second multiplexer having a plurality of inputs each receiving a corresponding one of said plurality of signals and having at least one output, said second multiplexer connecting a selected one of said inputs to a corresponding one of said at least one output, said first and second multiplexers controlled whereby said first multiplexer selects at least one of said plurality of signals for use as a clock signal and said second multiplexer selects all other of said plurality of input signals as data input signals, and a plurality of first data extraction circuits, one connected to each output of said second multiplexer for detecting a data input from said corresponding selected input signal; a second data path including a plurality of second variable delays, each receiving a corresponding one of said plurality of signals, a third multiplexer having a plurality of inputs each connected to a corresponding one of said plurality of second variable delays and having at least one output, said third multiplexer connecting a selected one of said inputs to a corresponding one of said at least one output, a fourth multiplexer having a plurality of inputs each receiving a corresponding one of said plurality of signals and having at least one output, said fourth multiplexer connecting a selected one of said inputs to a corresponding one of said at least one output, said third and fourth multiplexers controlled whereby said third multiplexer selects at least one of said plurality of signals for use as a clock signal and said fourth multiplexer selects all other of said plurality of input signals as data input signals, and a plurality of second data extraction circuits, one connected to each output of said fourth multiplexer for detecting a data input from said corresponding selected input signal; a comparison unit connected to said plurality of first and second extraction units for comparing corresponding detected data inputs; and a fifth multiplexer connected to said plurality of first and second extraction units operable to select for output of said data input detected by said plurality of first data extraction circuits or said plurality of second data extraction circuits.