Patent ID: 7046067

Claim:
An input/output (I/O) circuit for outputting an output signal of a first voltage in response to an input signal of a second voltage lower than the first voltage, comprising: a pull-down module having one or more NMOS transistors serially coupled between ground and an output node; a pull-up module having one or more PMOS transistors serially coupled between an I/O voltage and the output node; and a level shifter responsive to the input signal for generating a set of differential biases selectively enabling or disabling the pull-down and pull-up models to pull the output node to the I/O voltage or ground, wherein the differential biases are separately set for each of the PMOS transistors so that a voltage difference across each of the PMOS transistors does not exceed a predetermined value, thereby preventing the same from damage, wherein the level shifter further comprises: a first PMOS transistor coupled to the I/O voltage; a first group of one or more voltage dropping PMOS transistors each of which has its gate connected to its drain, serially coupled to a dram of the first PMOS transistor; a first NMOS transistor serially coupled between the first group of the voltage dropping PMOS transistors and ground, having a gate controlled by the input signal; a second PMOS transistor coupled to the I/O voltage in parallel to the first PMOS transistor, wherein the gate of the second PMOS transistor is coupled to the drain of the first PMOS transistor, and the gate of the first PMOS transistor is coupled to the drain of the second PMOS transistor; a second group of one or more voltage dropping PMOS transistors each of which has its gate connected to its drain, serially coupled to a drain of the second PMOS transistor; and a second NMOS transistor serially coupled between the second group of voltage dropping PMOS transistors and ground, having a gate controlled by a complement of the input signal, wherein the drains of the first and second PMOS transistors and the first and second groups of the voltage dropping PMOS transistors provide the differential biases.