Patent ID: 8171233

Claim:
A multiport semiconductor memory device comprising: a plurality of port units; a plurality of processors, each of which corresponds to and is coupled to one of the plurality of port units; a memory cell array comprising a shared memory area which can be directly accessed by each of the plurality of processors through the corresponding port units; a data path control unit controlling a data path between the shared memory area and each of the plurality of port units to perform data transmission/reception between each of the plurality of processors through the shared memory area; and an access authority information storage unit positioned outside of the memory cell array and comprising a first semaphore area and a second semaphore area, the first semaphore area storing access authority information for the shared memory area, the second semaphore area storing access authority information for accessing a nonvolatile memory, and the access authority information storage unit providing the stored access authority information to each of the plurality of processors.