Patent ID: 7213180

Claim:
A bus bridge circuit, which issues a read request to a first device in response to a read request from a second device, receives data from said first device via a first bus, and transfers the data to said second device via a second bus, comprising: a data buffer, which receives and stores the data of said first device, and error detection information generated from said data and from byte enable signals specifying, in units of a prescribed number of bits, the parallel data from said bus bridge circuit on said first bus to be enabled; an error detection information generation circuit, which generates new error detection information from byte enable signals specifying, in units of a prescribed number of bits, the parallel data from said second device on said second bus to be enabled, and from error detection data received in said data buffer; and a controller, which transfers to said second device via said second bus the data of said data buffer and said new error detection information, in response to said byte enable signals of said second device.