Patent ID: 8357936

Claim:
An array substrate for a liquid crystal display (LCD) device, comprising: a gate line crossing a data line on a substrate to define a pixel region; a thin film transistor (TFT) including a gate electrode connected to the gate line, an insulating layer directly on the gate electrode, an active layer on the insulating layer, a source electrode connected to the data line and a drain electrode spaced apart from the source electrode; an auxiliary common electrode having a horizontal portion spaced from the gate electrode and disposed in the pixel region, the auxiliary common electrode having a first horizontal portion disposed adjacent to and parallel to the gate line in a plan view, wherein the insulating layer is formed directly on the auxiliary common electrode; a metal layer that overlaps the insulating layer and contacts the horizontal portion of the auxiliary common electrode through a first contact hole defined through the insulating layer, wherein the metal layer is formed directly on the insulating layer; a passivation layer disposed on the TFT and the metal layer, wherein the passivation layer covers the source and drain electrodes; and a pixel electrode having a horizontal portion overlapping the metal layer with the passivation layer therebetween to form a storage capacitor, the horizontal portion of the pixel electrode disposed parallel to the gate line in the plan view and overlapping the first horizontal portion of the auxiliary common electrode, the metal layer overlapping and disposed between the first horizontal portion of the auxiliary common electrode and the horizontal portion of the pixel electrode and not extending outside the first horizontal portion of the auxiliary common electrode and the horizontal portion of the pixel electrode, the metal layer with the passivation layer there between to form a storage capacitor, the pixel electrode connected to the drain electrode through a second contact hole defined through the passivation layer, wherein the storage capacitor includes a first capacitor electrode having the metal layer that is formed of the same layer as the source and drain electrodes and is connected to the auxiliary common electrode formed of the same layer as the gate line and a second capacitor electrode having the pixel electrode across the passivation layer.