Patent ID: 6972230

Claim:
A method for fabricating a device having a twin bit floating gate memory cell, comprising the steps of: providing a material including a substrate having a memory area, the substrate having formed thereon within the memory area a composite charge storage structure and a protective liner layer over the composite charge storage structure, the material further including, within the memory area, buried diffusion oxide features least partially overlying respective buried diffusion regions in the substrate and extending vertically through the composite charge storage structure at least down through all charge storage sublayers of the composite charge storage structure, the buried diffusion oxide features having sidewalls extending higher than the top surface of the composite charge storage structure adjacent to the buried diffusion oxide features, the composite charge storage structure further having a subject segment extending laterally between two of the buried diffusion oxide features, the material further including spacer features over the composite charge storage structure against the sidewalls of the buried diffusion oxide features; etching a trench through the subject segment of the composite charge storage structure, at least down through all charge storage sublayers of the composite charge storage structure, using the spacer features as a mask; forming an insulator in the trench, at least to an elevation above the top surface of the highest charge storage sublayers of the composite charge storage structure; and forming a gate conductor overlying at least a portion of the subject segment of the composite charge storage structure.