Patent ID: 7334206

Claim:
A method for adding a cell to a circuit, comprising the steps of: (A) generating an initial layout of said cell utilizing an initial layer stack, said initial layer stack having a subset of a plurality of physical layers available in a fabrication technology; (B) generating a first final layout of said cell utilizing a first layer stack, (i) said first layer stack including more of said physical layers than said initial layer stack, (ii) said first final layout of said cell having an area of interest in at least one upper layer, (iii) said at least one upper layer belonging to said first layer stack and not said initial layer stack, and (iv) said first final layout residing in a library; (C) placing said first final layout of said cell in a circuit layout of said circuit; and (D) routing a network of said circuit through said first final layout of said cell using said at least one upper layer and avoiding said area of interest according to at least one rule of a plurality of rules, (i) said at least one rule defining a characteristic of said area of interest, and (ii) said circuit layout residing in a computer medium.