Patent ID: 6861301

Claim:
A method of forming a thin film transistor on a transparent plate, comprising the steps of: (a) providing a semiconductor layer having an active area; (b) forming a gate insulation layer on the semiconductor layer; (c) forming a shielding layer on part of the gate insulation layer, wherein the width of the shielding layer is wider than the width of the active area; (d) performing a first ion implantation to form a shallower doped region in the semiconductor layer; (e) removing the shielding layer; (f) performing a second ion implantation with the shielding layer as a mask, to form a deeper doped region in part of the semiconductor layer; (g) forming a gate layer on part of the gate insulation layer; (h) forming a source region and a drain region in the semiconductor layer located at both sides of the gate layer; (i) forming a first insulation layer on the gate layer and the gate insulation layer; (j) forming a first conductive layer on part of the first insulation layer; (k) forming a second insulation layer on the first conductive layer and the first insulation layer; (l) removing part of the second insulation layer, the first insulation layer and the gate insulation layer to form a first opening hole, a second opening hole and a third opening hole, wherein the first opening hole, exposes part of the surface of the source region, the second opening hole exposes part of the surface of the drain region and the third opening hole exposes part of the surface of the first conductive layer; (m) filling a conductive material in the first opening hole, the second opening hole and the third opening hole to form a first plug, a second plug and a third plug; (n) forming a second conductive layer and a third conductive layer on part of the second insulation layer, wherein the second conductive layer electrically connects the first plug and the third conductive layer electrically connects the second plug and the third plug; (o) forming a third insulation layer on the second conductive layer, the third conductive layer and the second insulation layer; (p) forming a shade pattern on part of the third insulation layer, wherein the shade pattern is not over the first conductive layer or is over part of the first conductive layer; (q) forming a silicon oxide layer on the shade pattern and the third insulation layer; (r) forming a transparent plate on the silicon oxide layer; (s) performing an annealing process to peel the semiconductor layer from the deeper doped region and the shallower doped region, to form a semiconductor thin film adhered to the gate insulation layer; (t) removing part of the semiconductor thin film to expose part of the gate insulation layer, and to leave a remaining semiconductor thin film adhered to the gate insulation layer located at the active area; and (u) removing part of the gate oxide layer and part of the first insulation layer to form a fourth opening hole, wherein the fourth opening hole exposes the first conductive layer.