Patent ID: 7474722

Claim:
A system comprising: a clock source; a first counter coupled to receive a clock signal from the clock source and configured to count cycles of the clock signal in a sample period corresponding to a first digital data stream; a second counter coupled to receive the clock signal from the clock source and configured to count cycles of the clock signal in a sample period corresponding to a second digital data stream; and a data processor coupled to the first and second counters and configured to read a first number of cycles counted by the first counter and a second number of cycles counted by the second counter, and convert at least one of the first and second digital data streams from a corresponding input sample rate to a predetermined sample rate based on the number of cycles counted in the corresponding digital data stream, wherein the first counter is configured to count cycles corresponding to the first digital data stream by incrementing once for each cycle after a frame sync signal is received in the first digital data stream and wherein the second counter is configured to count cycles corresponding to the second digital data stream by incrementing once for each cycle after a frame sync signal is received in the second digital data stream.