Patent ID: 8564262

Claim:
A circuit structure for power gating a voltage regulator, comprising: first control circuitry, in a first circuit of the voltage regulator, configured to remove frequency components of an output voltage in a first frequency range, wherein the first control circuitry receives a first signal to power gate the output voltage of the first circuit, wherein by the first control circuitry power gating the output voltage of the first circuit causes substantially no voltage to be output by the first circuit to a primary output node, and wherein the first control circuitry comprises: a N-FET transistor having a source terminal, a drain terminal, and a gate terminal; a first P-FET transistor having a source terminal, a drain terminal, and a gate terminal; and a second P-FET transistor having a source terminal, a drain terminal, and a gate terminal, wherein: the source terminal of the N-FET transistor is electrically coupled to the source terminal of the first P-FET transistor, the source terminal of the N-FET transistor and the source terminal of the first P-FET transistor are electrically coupled to an output terminal of an operational amplifier of the first circuit, the drain terminal of the N-FET transistor is electrically coupled to the drain terminal of the first P-FET transistor, the drain terminal of the N-FET transistor and the drain terminal of the first P-FET transistor are further electrically coupled to the drain terminal of the second P-FET transistor, the drain terminal of the N-FET transistor, the drain terminal of the first P-FET transistor, and the drain terminal of the second P-FET transistor are electrically coupled to a gate terminal of a P-FET transistor of the first circuit, the gate terminal of the N-FET transistor is electrically coupled to an output terminal of an inverter, the inverter having an input terminal and the output terminal, the gate terminal of the N-FET transistor and the output terminal of the inverter are electrically coupled to the gate terminal of the second P-FET transistor, the gate terminal of the first P-FET transistor is electrically coupled to the input terminal of the inverter, the gate terminal of the first P-FET transistor and the input terminal of the inverter are electrically coupled to the first signal, and the source terminal of the second P-FET transistor is electrically coupled to the voltage source; and second control circuitry, in a second circuit of the voltage regulator, electrically coupled to the primary output node of the first circuit, the second circuit configured to remove frequency components of the output voltage in a second frequency range, wherein the second frequency range being greater than the first frequency range, wherein the second control circuitry receives the first signal to power gate the output voltage of the second circuit, and wherein by the second control circuitry power gating the output voltage of the second circuit causes substantially no voltage to be output by the second circuit to the primary output node.