Patent ID: 8560892

Claim:
A readable and writable memory configured to store a plurality of memory bits, comprising: a data storage element having: a plurality of lines, each of said plurality of lines having a plurality of segments, each of said plurality of segments having a plurality of data bits; a plurality of error correction codes each associated with one of said plurality of lines: a plurality of validity bits, each one of said plurality of validity bits being associated with one of said plurality of lines, configured to indicate that one of said plurality of error correction codes associated with said one of said plurality of lines is valid or invalid; said plurality of data bits associated with one of said plurality of segments of one of said plurality of lines being separately storable without affecting a remainder of said plurality of data bits associated with others of said plurality of segments associated with said one of said plurality of lines, wherein all of said plurality of data bits associated with one of said plurality of lines being activated when any of said plurality of data bits associated with one of said plurality of segments is read; and a processor configured to generate one of said plurality of error correction codes for all of said plurality of data bits in said plurality of segments associated with one of said plurality of lines.