Patent ID: 7667513

Claim:
A method for correcting the duty cycle of a clock signal, the method comprising the steps of: receiving the clock signal at an input node, wherein the clock signal comprises a plurality of clock rising edges and a plurality of clock falling edges; estimating the duty cycle of the clock signal, wherein estimating the duty cycle of the clock signal comprises sampling a voltage level of the output node to estimate a duty cycle at the output node; triggering a rising edge at an output node in response to a rising edge of the clock signal; producing a delayed clock signal by delaying the clock signal by a time period, wherein the delayed clock signal comprises a plurality of delayed rising edges and a plurality of delayed falling edges, wherein each of the plurality of delayed rising edges occurs substantially the time period after each of the plurality of clock rising edges, wherein each of the plurality of delayed falling edges occurs substantially the time period after each of the plurality of clock falling edges; and producing a falling edge at the output node in response to each of the plurality of delayed rising edges.