Patent ID: 7046564

Claim:
A semiconductor memory with a memory subunit, comprising: a memory cell in which a data value is stored and adapted to be connected with a bit line to which a complementary bit line is assigned; a precharge/equalize circuit assigned to the memory cell, the precharge/equalize circuit serving to charge, prior to reading out of the memory cell, the bit line and the complementary bit line in a region of the memory cell to a same voltage level, and being switched off during the reading out of the memory cell; a control circuit connected with the precharge/equalize circuit for switching on and off the precharge/equalize circuit, wherein the control circuit for switching on and off the precharge/equalize circuit is designed such that it outputs a control signal with a first maximum voltage level to a control gate of the precharge/equalize circuit for switching on the precharge-/equalize circuit and for precharging the bit lines in a memory cell self-refresh mode, and outputs a control signal with a second maximum voltage level to the control gate of the precharge/equalize circuit for switching on the precharge/equalize circuit and for precharging the bit lines in a normal memory cell access mode, the second maximum voltage level differing from the first maximum voltage level and being selected such that a period of time between a start of the output of the respective control signal and completion of the precharging of the bit lines in the memory cell self-refresh mode is larger than in the normal memory cell access mode.