Patent ID: 8713221

Claim:
A system comprising: a memory; and one or more processors to: use a producer clock domain, operating at a first clock frequency, to generate data and to write the data to a plurality of first in, first out (FIFO) queues; use a plurality of clock dividers, each connected to receive a read clock signal from a respective one of a plurality of consumer clock domains that are used to read the data, to reduce a frequency of the read clock signal; read the data, at a second clock frequency, from the plurality of FIFO queues; maintain count values relating to an amount of the data read at the second clock frequency; determine that at least one of the count values satisfies a threshold; and issue, based on determining that the at least one of the count values satisfies the threshold, a write pulse signal to the producer clock domain, the write pulse signal causing the producer clock domain to perform a write operation to each of the plurality of FIFO queues.