Patent ID: 7366828

Claim:
Memory control apparatus connectable with a first memory which requires refresh, and a second memory which shares part of a bus with the first memory and does not require refresh, the apparatus comprising: a first memory controller that conducts access control and auto-refresh control for the first memory; a second memory controller that conducts access control for the second memory; and an arbiter that adjusts a timing of outputting a signal that is generated for the first memory by the first memory controller and another signal that is generated for the second memory by the second memory controller to a bus that is connected to at least one of the first memory and the second memory, the arbiter judging whether a signal from the first memory controller is an auto-refresh request signal the memory controllers communicating with the first and second memories by a plurality of bus signals; the plurality of bus signals including: a plurality of first bus signals that control a first process by which the first memory controller accesses the first memory; a plurality of second bus signals that control a second process by which the second memory controller accesses the second memory; and a plurality of third bus signals that are shared by the first and second memories, the plurality of third bus signals including a data bus signal and an address bus signal, the first process including a refresh request from the first memory controller to the first memory, and the first memory being refreshed during access of the second memory.