Patent ID: 7149104

Claim:
A memory circuit, comprising: a latch having a first node and a second node configured to be bi-stable with a potential of the first node inverse to a potential of the second node; a word selecting line; a first MIS transistor having one of source/drain nodes thereof coupled to the first node of said latch, another one of the source/drain nodes thereof coupled to a predetermined node, and a gate node thereof coupled to said word selecting line; a second MIS transistor having one of source/drain nodes thereof coupled to the second node of said latch, another one of the source/drain nodes thereof coupled to said predetermined node, and a gate node thereof coupled to said word selecting line; and a control circuit configured to subject in a write mode, one of said first MIS transistor and said second MIS transistor to bias conditions that cause a lingering change in transistor characteristics thereof, and to subject in a recovery mode both said first MIS transistor and said second MIS transistor for equal amount of time to equal bias conditions that cause a lingering change in transistor characteristics thereof.