Patent ID: 7875886

Claim:
A semiconductor device comprising: a gate wiring formed over an insulating surface; an insulating film formed over the gate wiring; a first amorphous semiconductor film formed over the insulating film; a source region and a drain region each provided in a second amorphous semiconductor film containing an impurity element of one conductivity type, formed over the first amorphous semiconductor film; a source wiring provided on the source region and an electrode provided on the drain region; and a pixel electrode formed so as to partially overlap and be in contact with the electrode, wherein at least an outer end of the first amorphous semiconductor film has a tapered shape, wherein at least an outer end of the second amorphous semiconductor film has a tapered shape, wherein a taper angle of the second amorphous semiconductor film is different from that of the first amorphous semiconductor film, wherein an outer side edge of a top surface of the second amorphous semiconductor film is aligned with an outer side edge of a bottom surface of the source wiring, wherein the first amorphous semiconductor film has a depression between the source region and the drain region, wherein an inner side surface of the second amorphous semiconductor film is aligned with a first side surface of the source wiring, which faces the electrode, and wherein a film thickness of the insulating film is thinner than a film thickness of the gate wiring.