Patent ID: 7339257

Claim:
A semiconductor device comprising: a lead frame having at least a plurality of first inner leads having distal end portions and parallel to each other, and a plurality of second inner leads having distal end portions opposing the distal end portions of the first inner leads, longer than the first inner leads, and parallel to each other; a semiconductor chip having an element formation surface and a plurality of bonding pads arranged along one side of the element formation surface, and mounted on surfaces of said plurality of second inner leads using an insulating adhesive; a plurality of first bonding wires which electrically connect the distal end portions of said plurality of first inner leads to some of said plurality of bonding pads; a plurality of second bonding wires which electrically connect the distal end portions of said plurality of second inner leads to the rest of said plurality of bonding pads; and at least one lead fixing tape adhered, across said plurality of second inner leads, on surfaces of said plurality of second inner leads opposite to the surfaces on which the semiconductor chip is mounted, the at least one lead fixing tape overlapping with the semiconductor chip and protruding from the semiconductor chip in a direction to the distal end portions of the plurality of second inner leads in a plane view.