Patent ID: 8312248

Claim:
An integrated circuit system, comprising: a memory processor configured to receive logical memory addresses from a host and output physical addresses in response thereto; and a non-volatile memory in communication with the memory processor to receive the physical addresses from the memory processor to access memory locations of the non-volatile memory corresponding to respective ones of the physical addresses, wherein the integrated circuit system is configured to receive a parameter value to adjust a user usable capacity, as viewed by the host, of the non-volatile memory, and configured to store, in the integrated circuit system, an updated partitioning parameter in response to the parameter value, and wherein the memory processor is configured to receive a command by the host to adjust the user usable capacity of the non-volatile memory, wherein the integrated circuit system is responsive to the stored updated partitioning parameter to adjust a partitioning ratio of the user usable capacity and a reserved memory capacity, to modify the reserved memory capacity of the non-volatile memory in response to the updated partitioning parameter.