Patent ID: 7298570

Claim:
An apparatus comprising: an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal; a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal; a discrete time sequence detector operable to examine the equalized signal; and a control circuit that provides a coefficient adjustment to the asymmetry correction circuit to affect the asymmetry compensation based on an estimate of non-linearity derived from the equalized signal and an output of the discrete time sequence detector; wherein the coefficient adjustment comprises one or more values received by the asymmetry correction circuit to control the asymmetry compensation, the one or more values being generated according to an equation, q N, t+1 =q N,t +μ·(y R −y A )·y 1^N , where q N,t is an asymmetry correction coefficient of order N at time t from one or more asymmetry correction coefficients, μ is a step size, y R corresponds to the equalized signal, y 1 corresponds to an estimated ideal channel output derived from the output of the discrete time sequence detector, and y A corresponds to an estimated real equalized channel output with asymmetry taken into account, y A being derived utilizing the output of the discrete time sequence detector and the one or more asymmetry correction coefficients.