Patent ID: 8139072

Claim:
A method, comprising: segregating changed image pixels from a primary data stream and a secondary data stream for use in video data compression, the segregating including: outputting the primary data stream and the secondary data stream from a dual head video controller's two phase locked video stream outputs from a primary scan engine and a secondary scan engine, respectively, such that the primary data stream from the primary scan engine is output as a current frame and the secondary data stream from the secondary scan engine is output as an old frame, the outputting including; storing the current frame, with a delay, in a memory of the secondary scan engine in the video controller via a zoom video input port, the delay of sufficient duration to prevent the current frame stored via the zoom video input port in the memory of the secondary scan engine from overwriting the old frame output from the memory of the secondary scan engine; and outputting the secondary data stream, as the old frame, from the memory of the secondary scan engine one frame time later than a time frame of the current frame; comparing the phase locked primary and secondary data streams in real-time in an FPGA, to segregate any of the changed image pixels from the primary data stream and the secondary data stream; and using an on-board general purpose micro processor in the dual head video controller in conjunction with the FPGA to count vertical syncs to thus create a local software interrupt event and updating start address registers in the primary and secondary scan engines and a write-start address register in the zoom input port to step through a series of start memory locations in a round-robin fashion to create up to 16 separate image data flows.