Patent ID: 8890261

Claim:
A field effect transistor device comprising: a source region; a drain region; a plurality of fins connecting the source region and the drain region, the fins having a pitch of between about 40 nanometers and about 200 nanometers and each of the fins having a width of between about ten nanometers and about 40 nanometers, and wherein each of the fins has a height variation of less than or equal to about five nanometers with the height variation in a given one of the fins being measured as a difference between a highest height value and a lowest height value throughout the given fin; a gate stack over at least a portion of the fins, wherein the source region and the drain region are self-aligned with the gate stack; and spacers present between the source region and the gate stack and between the drain region and the gate stack, wherein the spacers are formed from silicon dioxide, and wherein the spacers i) cover fin extension regions between the source region and the gate stack and between the drain region and the gate stack and ii) extend over and are in direct contact with a top surface of each of the source region and the drain region such that the spacers offset the gate stack from the source region and the drain region as well as cover a portion of each of the source region and the drain region.