Patent ID: 7282402

Claim:
A method of forming a semiconductor device comprising: forming trench isolation in a wafer to separate an NMOS region from a PMOS region of the wafer, the wafer having a semiconductor on insulator (SOI) configuration that comprises a semiconductor layer over an insulator, wherein the trench isolation extends at least to the insulator through the semiconductor layer; forming a first channel region in the NMOS region, the first channel region having a first strain characteristic; and forming a second channel region in the PMOS region, the second channel region having a second strain characteristic, wherein the second strain characteristic is less tensile than the first strain characteristic and wherein the first and second strain characteristics enable a simultaneous performance enhancement in NMOS and PMOS device structures to be formed in respective NMOS and PMOS regions, wherein prior to forming the isolation trench, the method further comprising: forming a protective layer overlying the semiconductor layer; and forming a nitride layer overlying the protective layer, wherein the trench isolation extends at least to the insulator through the nitride layer, the protective layer, and the semiconductor layer.