Patent ID: 8009498

Claim:
A memory refresh system, comprising: a comparative detection circuit, detecting a voltage of a storage capacitor of a memory cell of a memory, and generating a corresponding digital code by comparing the voltage with a reference voltage, each of the memory cell having a corresponding digital code, the combination of the digital codes of the memory cells forming a first state, after a specific period of time, the voltages of the storage capacitors of the memory cells being once detected by the comparative detection circuit, and corresponding digital codes being generated and combined to form a second state; a logic circuit, comparing the first state and the second state to determine whether or not to change a refresh period of a refresh period detecting process for refreshing data stored in the memory cell; and a timing circuit, selectively changing the refresh period or terminating the refresh period detecting process according to a determination result of the logic circuit; wherein the refresh period is increased by two or more times if the first state and the second state have the same combination of digital codes, the refresh period is constant if the first state and the second state have a different combination of digital codes, and the logic circuit terminates the refresh period detecting process for refreshing data if the voltage of all memory cell are lower than the reference voltage.