Patent ID: 7610526

Claim:
A system, comprising: a first circuit operably connected to a bus to be electrically validated, the first circuit comprising: a first logic configured to selectively produce a test sequence of electrical signals that may be driven onto the bus; a second logic configured to produce one or more bus protocol signals that may be driven onto the bus; a bus interface logic operably connected to the first logic and the second logic, the bus interface logic being configured to drive the test sequence and the bus protocol signals onto the bus; and a test logic operably connected to one or more of the first logic, the second logic, and the bus interface logic, the test logic being configured to control the first circuit to select which of, the bus protocol signals, and the test sequence are driven onto the bus; and a second circuit operably connected to the bus, the second circuit comprising: a third logic configured to receive from the bus a received sequence of electrical sequences produced by the bus interface logic driving the test sequence onto the bus; a fourth logic configured to produce a check sequence of electrical signals related to the test sequence; and a bus verification logic operably connected to the third logic and the fourth logic, the bus verification logic being configured to determine whether the bus is correctly transmitting digital data based, at least in part, on comparing the received sequence and the check sequence, and to produce a miscompare data configured to record information concerning parameters associated with determining that the bus is not correctly transmitting digital data, where the miscompare data comprises a bus line on which a miscompare occurred, where the miscompare data comprises a seed value employed by the fourth logic.