Patent ID: 8006008

Claim:
Apparatus for processing data comprising: two or more devices each having parallel signal interface operating in accordance with a parallel signal protocol; an interconnect coupled to said two or more devices and operating to pass signals therebetween; wherein said interconnect comprises: a serializing circuit coupled to a parallel signal interface of a first device of said two or more devices and a serial data path and configured: (i) to sample from said parallel signal interface of said first device a first set of parallel signals forming a transaction in accordance with said parallel signal protocol; (ii) to serialize said first set of parallel signals to form a serial stream of data; and (iii) to transmit said stream of data via said serial data path; and a deserializing circuit coupled to a parallel signal interface of a second device of said two or more devices and said serial data path and configured: (i) to receive said serial stream of data from said serial data path; (ii) to deserialize said serial stream of data to form a second set of parallel signals corresponding to said first set of parallel signals; and (iii) to apply said second set of parallel signals to said parallel signal interface of said second device to reform said transaction in accordance with said parallel signal protocol, wherein: said serializing circuit is responsive to one or more predetermined patterns of values for signals of said first set of parallel signals to form one or more short codes representing said one or more predetermined patterns and to transmit said one or more short codes as part of said serial data stream in place of said one or more predetermined patterns, said serializing circuit transmitting said first set of parallel signals without use of said one or more short codes when said first set of parallel signals does not match any of said one more predetermined patterns; and said deserializing circuit is responsive to said one or more short codes within said serial data stream to form corresponding patterns of values of said second set of parallel signals.