Patent ID: 8749020

Claim:
An integrated circuit structure comprising: a planar base layer over a semiconductor substrate; a dielectric layer on the planar base layer; a metal fuse, having a first thickness from a top surface of the planar base layer to a top surface of the metal fuse, in the dielectric layer; a dummy pattern, having a second thickness from the top surface of the planar base layer to a top surface of the dummy pattern, adjacent the metal fuse in the dielectric layer; and a metal line, having a third thickness from the top surface of the planar base layer to a top surface of the metal line, in the dielectric layer, the metal line being spaced apart from the metal fuse, laying outside the dummy pattern, and electrically isolated from the metal fuse, wherein the first thickness and the second thickness are each less than the third thickness, wherein the first thickness, the second thickness and the third thickness are measured in a direction perpendicular to an upper surface plane of the semiconductor substrate.