Patent ID: 8314000

Claim:
A method for fabricating a Laterally Diffused MOS (LDMOS) transistor formed in a P-epitaxial layer on an N+ substrate comprising: forming a P body region in said P-epitaxial layer, overlapped with a conductive gate padded with a gate oxide; forming an N+ source region encompassed in said P body region thus forming a channel region underneath said conductive gate; forming a drain contact trench filled with a conductive plug extending from the top surface of said P-epitaxial layer to contact with said N+ substrate and an N+ highly doped region formed along a sidewall of said contact trench; forming a first LDD-N1 N type doped region by ion implantation thus forming an N type drift region between said channel region and said N+ highly doped region; forming a second LDD-N2 N type doped region by ion implantation with a lower energy than that of said first LDD-N1 region but with a higher dose than said first LDD-N1 region wherein said second LDD-N2 region is encompassed in said first LDD-N1 region and contacts said highly doped N+ region, wherein said second LDD-N2 N type region is formed by using a same mask as said first LDD-N1 N type region.