Patent ID: 7863092

Claim:
A method of fabricating an integrated circuit assembly, comprising: forming a mother die in a first surface of a semiconductor wafer, wherein the mother die comprises a plurality of through-die vias and wherein the mother die is one of a plurality of mother dice in the semiconductor wafer; wherein the semiconductor wafer in which the plurality of mother dice is formed is un-singulated; attaching a substrate to the first surface of the un-singulated semiconductor wafer; exposing an end of a through-die via of the plurality of through-die vias at a second surface of the un-singulated semiconductor wafer; mounting a plurality of daughter dice to the second surface of the un-singulated semiconductor wafer such that each daughter die is electrically coupled to a respective one of the mother dice by way of a through-die via of the plurality of through-die vias; and forming a level face on the second surface of the un-singulated semiconductor wafer by depositing packaging material over and around the plurality of daughter dice.