Patent ID: 7376021

Claim:
A data retrieval circuit, comprising: an array of memory cells; a pre-fetch unit for storing data that was pre-fetched from the memory cells into a plurality of data buffers including a first plurality of data buffers and a second plurality of data buffers; an output switching unit coupled to the plurality of data buffers, the output switching unit structured to substantially simultaneously output data from at least one of the first plurality of data buffers and at least one of the second plurality of data buffers in response to a control signal; a first node coupled to the output switching unit, the first node connecting output signal lines from the first plurality of data buffers such that the data output from the first plurality of data buffers through the output switching unit is output over a first common output line; a second node coupled to the output switching unit, the second node connecting output signal lines from the second plurality of data buffers such that the data output from the second plurality of data buffers through the output switching unit is output over a second common output line; a data extractor coupled to the first and second common output lines, the data extractor including a plurality of latches structured to temporarily store data outputted from the output switching unit through the first and second node in parallel; and a parallel to serial data converter structured to, upon receiving a clock signal, generate a serial output signal of the data stored in the data extractor.