Patent ID: 8302098

Claim:
A system for managing threads in a processor having a plurality of multithreaded cores, comprising: a processor comprising the plurality of multithreaded cores; a system memory comprising a thread monitor; the thread monitor, when executing on the processor, is configured to: determine a hardware resource usage characteristic of a thread executing on a first core of the plurality of multithreaded cores, wherein the first core comprises a first hardware resource; a thread scheduler configured to: select a subset of the plurality of multithreaded cores as a hardware resource active proper subset, wherein the hardware resource active proper subset comprises a second hardware resource on a second core of the plurality of multithreaded cores and wherein the second core is in the hardware resource active proper subset; and assign, the thread to the second core, in response to a determination that the hardware resource active proper subset does not comprise the first hardware resource and a determination that the hardware resource usage characteristic of the thread will not cause a significant hardware resource contention on the second core, wherein the significant hardware resource contention is caused when an aggregate quantity of hardware resource usage of threads, including the thread, that are running on the second core, exceeds a dynamically selectable hardware resource usage threshold of the second core; and a power manager configured to: reduce power to the first hardware resource after assigning the thread to the second core.