Patent ID: 7863096

Claim:
A method of forming an embedded multi-chip package comprising the steps of: forming a carrier having a plurality of cavities; placing an electrical device in each of said cavities; forming a first dielectric layer around and over each of said electrical devices and over the upper surfaces of said carrier; forming first level vias through said first dielectric layer to selected bonding pads on each of said electrical devices; forming a plurality of first metal conductors, each of which is in contact with a selected bond pad and extends a distance away from one of said first level vias, and one or more first metal conductors in contact with two selected bond pads; forming a second dielectric layer over said plurality of first metal conductors; forming second level vias in said second dielectric layer over said plurality of first metal conductors; forming a plurality of second metal conductors in said second level vias, each of said second metal conductors to contact one of said first metal conductors; and forming a plurality of solder bumps each of which is coupled to one of said plurality of second metal conductors.