Patent ID: 7802156

Claim:
A circuit for stabilizing soft bits in a bit stream, the circuit comprising: a comparator adapted to receive a first read of voltage differentials from a series of bit cells and compare the first read to a positive voltage offset of a given magnitude, and set bits in a first bit stream to values that are dependent upon whether the voltage differential from the first read of a given bit cell is greater than the positive voltage offset, and store the first bit stream in a first register, the comparator also adapted to receive a second read of the voltage differentials from the series of bit cells and compare the second read to a negative voltage offset of the given magnitude, and set bits in a second bit stream to values that are dependent upon whether the voltage differential from the second read of a given bit cell is less than the negative voltage offset, and store the second bit stream in a second register, the comparator further adapted to compare the first bit stream to the second bit stream, and set bits in a mask string dependent upon whether the bits in a given position of the first bit stream and the second bit stream are identical, a third register adapted to receive the mask string, and the comparator additionally adapted to receive a subsequent read of the voltage differentials from the series of bit cells and compare the subsequent read to a zero voltage offset, and set bits in a subsequent bit stream to values that are dependent upon whether the voltage differential from the subsequent read of a given bit cell is greater than the zero voltage offset, compare the subsequent bit stream to the mask string, and correct bits of the subsequent bit stream disposed in positions set in the mask string.