Patent ID: 7937568

Claim:
In a data processing system having a processor pipeline with a number of functional stages, a method comprising: prefetching instructions for execution; determining when a threshold number of first-type instructions are scheduled to be executed, wherein the threshold number is greater than one (1); wherein the first-type instructions are complex arithmetic instructions, including multiply instructions and the number of functional stages include stages within a complex execution pipeline which processes complex arithmetic instructions; and in response to the threshold number of first-type instructions being schedule for execution, automatically changing an execution cycle frequency of one of the functional stages from a first cycle frequency to a second, pre-established higher cycle frequency, which enables more efficient execution and higher execution throughput of the first-type instructions, wherein the cycle frequency of only the one functional stage is switched to the higher cycle frequency independent of the cycle frequency of the other functional stages in the processor pipeline which remain at the first cycle frequency during execution of the first type and other types of instructions.