Patent ID: 8806135

Claim:
A method for reading data with a plurality of load instructions from a memory system having a level one cache and a level two memory sub-system, comprising: storing a first missed load instruction in a primary entry of an outstanding load miss buffer; storing a first data unit requested by the first missed load instruction in a load miss result buffer; in response to determining that a second missed load instruction requests a same memory address as the first missed load instruction, storing the second missed load instruction in a dependent entry of the outstanding load miss buffer, wherein the dependent entry is associated with the primary entry; storing a second data unit requested by the second missed load instruction in the load miss result buffer; reading the first data unit from the load miss result buffer for the first missed load instruction in response to the first missed load instruction being re-issued; and reading the second data unit from the load miss result buffer for the second missed load instruction in response to the second missed load instruction being re-issued.