Patent ID: 8848326

Claim:
A circuit comprising: a first power clamp coupled to a first power rail and a first ground rail; a first NMOS transistor having a first source, a first drain, and a first gate, wherein the first source is coupled to a second ground rail; a first PMOS transistor having a second source, a second drain, and a second gate, wherein the second source is coupled to the first power rail, and the first power clamp provides a signal to turn on the first NMOS transistor during an ESD event that occurs at the first power rail; a second NMOS transistor having a third source, a third drain, a third gate, and a body, wherein the body is coupled to the second ground rail, and the second NMOS transistor is turned on during the ESD event; and a second PMOS transistor having a fourth source, a fourth drain, and a fourth gate, wherein the third source is coupled to the second drain, and the third drain is coupled to a second power rail, and the fourth source is coupled to the first ground rail, the fourth drain is coupled to the third gate, and the fourth gate is coupled to the second ground rail.