Patent ID: 8072821

Claim:
A semiconductor memory device comprising: a memory cell array that includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the word lines with the bit lines; an input/output circuit that includes a write path to which a write data to be written in the memory cell array is supplied and a read path to which a read data read from the memory cell array is supplied; and a first data line and a second data line that connect the input/output circuit to the memory cell array, wherein the input/output circuit further includes: a write buffer that supplies the write data on the write path to the first data line; a read amplifier that supplies the read data on the second data line to the read path; a detection circuit that detects matching between a write address that the write data is to be written to and a read address that the read data is to be read from; and a bypass circuit that supplies the write data on the write path to the read path in response to matching detected by the detection circuit.