Patent ID: 7447948

Claim:
A method, comprising: performing a first parity check calculation to determine a parity of a first subset of a plurality of bits of an instruction word and a second parity check calculation to determine a parity of a second subset of the plurality of bits of the instruction word, wherein the first subset of bits and the second subset of bits collectively include all instruction bits in the plurality of bits of the instruction word; detecting that an error is present in the instruction word based on the parity check calculations for the first and second subsets of bits; and in response to the detecting that the error is present in the instruction word, stopping a state machine for a processor on which the instruction word is to be executed, saving machine state data for the state machine, and performing further error processing of the instruction word, including performing a third parity check calculation to determine a parity of a third subset of the plurality of bits of the instruction word.