Patent ID: 7543256

Claim:
A method of designing an integrated circuit (IC) device having desired electrical characteristics, said method comprising: providing an initial IC device design; generating a layout representation corresponding to the initial IC device design; simulating how structures within the layout representation will pattern on a wafer; based on the simulating step, determining whether actual electrical characteristics associated with the initial IC device design sufficiently match the desired electrical characteristics, wherein the desired electrical characteristics include at least one of gain and switching speed; and if the actual electrical characteristics associated with the initial IC device design do not sufficiently match the desired electrical characteristics, modifying the initial IC device design; wherein the initial IC device design includes a desired relationship between at least two structures within the IC device design; further comprising: determining an amount of process-related variation associated with at least two structures within the layout representation of the IC device design; wherein determining an amount of process-related variation associated with at least two structures within the layout representation includes: simulating how structures within the layout representation will pattern on a wafer; and measuring a feature of the simulated structures, said feature being indicative of process-related variation; wherein the feature indicative of process-related variation is at least one of (i) slope of edge intensity and (ii) logarithm of slope of edge intensity; and wherein: a larger slope of edge intensity or logarithm of slope of edge intensity is indicative of a smaller process-related variation; and a smaller slope of edge intensity or logarithm of slope of edge intensity is indicative of a larger process-related variation.