Patent ID: 7479705

Claim:
A semiconductor device comprising: a base material having a main surface and a rear surface opposing to the main surface; a plurality of bonding electrodes formed along a peripheral portion of the main surface of the base material; a plurality of wirings respectively connected with each of the plurality of bonding electrodes and formed only inside of the plurality of bonding electrodes such that the bonding electrodes are located between the plurality of wirings and the peripheral portion of the main surface of the base material; a first dummy pattern formed at a central portion of the main surface of the base material; a first insulating film formed over the main surface of the base material such that both the plurality of wirings and the first dummy pattern are substantially covered with the first insulating film; a plurality of bump lands formed on the rear surface of the base material; a second dummy pattern formed at a central portion of the rear surface of the base material; a second insulating film formed on the rear surface of the base material such that each of the plurality of bump lands is exposed from the second insulating film and the second dummy pattern is covered with the second insulating film; a semiconductor chip mounted over the first insulating film by way of a paste material, the semiconductor chip having a main surface and a plurality of pads formed on the main surface, wherein the first insulating film separates the semiconductor chip from the plurality of wirings; a plurality of wires electrically connecting the plurality of pads of the semiconductor chip with the plurality of bonding electrodes formed on the main surface of the base material, respectively; a sealing body sealing the semiconductor chip, the plurality of wires and the main surface of the base material; and a plurality of external terminals formed on the plurality of bump lands, respectively; wherein the first insulating film is not formed between each of the plurality of bonding electrodes and the closest peripheral edges of the peripheral portion of the base material; wherein a concaved portion is formed at the first insulating film located between each of the plurality of bonding electrodes and the semiconductor chip; and wherein the peripheral portion of the main surface of the base material, which is not covered with the first insulating film, is contacted with the sealing body.