Patent ID: 7864585

Claim:
A method of programming memory cells of a NAND memory device each memory cell having a desired data state, comprising: biasing a first channel region to a first voltage; biasing a second channel region to a second voltage, wherein the first voltage is higher than the second voltage; applying a programming voltage to a control gate of a selected memory cell coupled to the second channel region; biasing the first channel region to a third voltage that is higher than the first voltage; biasing the second channel region to a fourth voltage that is higher than the second voltage, wherein the third voltage is higher than the fourth voltage; decreasing the voltage of the second channel region while continuing to apply the programming voltage, wherein the selected memory cell experiences an effective programming potential while a memory cell coupled to the first channel region and having a control gate coupled to the control gate of the selected memory cell is substantially inhibited from experiencing the effective programming potential; and at least partially in response to the selected memory cell approaching its desired data state, increasing the voltage of the second channel region, wherein a programming rate of the selected memory cell is thereby reduced.