Patent ID: 6992505

Claim:
A multiplexer circuit, comprising: a first plurality of circuit input terminals providing a first plurality of input signals; a second plurality of circuit input terminals providing a second plurality of input signals having complementary values to the first plurality of input signals; a circuit output terminal; a first multiplexer having a plurality of input terminals coupled to the first plurality of circuit input terminals, at least one select terminal, and an output terminal; a second multiplexer having a plurality of input terminals coupled to the second plurality of circuit input terminals, at least one select terminal coupled to the at least one select terminal of the first multiplexer, and an output terminal; an output circuit having a first input terminal coupled to the output terminal of the first multiplexer, a second input terminal coupled to the output terminal of the second multiplexer, and an output terminal coupled to the circuit output terminal; and a plurality of inversion circuits, each inversion circuit being coupled between one of the first circuit input terminals and a corresponding one of the second circuit input terminals, each inversion circuit comprising a memory cell, wherein the first and second multiplexers are configured to select a corresponding one of their respective input terminals in response to equivalent signals received at their respective select terminals.