Patent ID: 8375172

Claim:
A method, in a cache access memory, for enabling a proper write through during a write-through operation, the method comprising: determining, by first circuitry in the cache access memory, whether a memory access for a memory cell in a plurality of memory cells in the cache access memory is either a read operation or the write-through operation; responsive to determining that the memory access is the write-through operation, determining, by the first circuitry, whether a data input signal is in a first state or a second state; responsive to the data input signal being in the second state, outputting, by the first circuitry, a global write line signal in the first state; responsive to the global write line signal being in the first state, outputting, by second circuitry, a column select signal in the second state; and responsive to the column select signal being in the second state, keeping, by third circuitry, a downstream read path of the cache access memory at the first state such that data output by the cache access memory is in the first state.