Patent ID: 8531882

Claim:
A semiconductor memory device comprising a plurality of semiconductor memory chips stacked, each of the semiconductor memory chips comprising: a pad commonly connected to the semiconductor memory chips and configured to receive an enable signal that enables access to each of the semiconductor memory chips; a memory cell array comprising a plurality of memory cells; a chip address memory configured to store a chip address indicating an address of the semiconductor memory chip itself; a determining part configured to compare a select address externally inputted through the pad to the chip address in order to determine whether or not they match each other; a control-signal setting part configured to set the control signal inputted to the semiconductor memory chip itself to be valid or invalid, depending on a determination made by the determining part; and a chip-address setting part configured to determine whether the chip address is stored in the chip address memory or not, depending on number of fail bits in a specified area of the semiconductor memory chip itself, wherein the semiconductor memory device comprises a memory controller configured to allocate respectively different ones of the chip addresses to the semiconductor memory chips, depending on the number of fail bits.