Patent ID: 8460960

Claim:
A method for fabricating an integrated circuit, comprising: providing a conductive substrate with a logical circuit region and a MEMS region; forming a first interconnect structure comprising a plurality of first dielectric layers and a plurality of first conductive patterns on the MEMS region of the conductive substrate, the first dielectric layers and the first conductive patterns alternately stacked on the MEMS region of the conductive substrate; forming an interlayer to cover the first conductive patterns on the first interconnect structure; forming a poly-Si mask layer corresponding to the first conductive patterns and exposing a portion of the interlayer on the interlayer; removing the portion of the interlayer exposed by the poly-Si mask layer and corresponding portions of the first dielectric layers through using the poly-Si mask layer as a mask for forming a plurality of openings within the first interconnect structure; and removing a portion of the conductive substrate in the MEMS region.