Patent ID: 8728907

Claim:
A method for fabricating an integrated circuit arrangement, the method comprising: forming an isolating trench in a substrate; introducing a first electrically insulating material into the trench; introducing a first electrically conductive material into the isolating trench after the first insulating material has been introduced to the trench; patterning the first conductive material; applying a second conductive material adjacent to the already patterned first conductive material; patterning the second conductive material to make the first and second conductive material function as a gate electrode for a field effect transistor, applying an auxiliary layer before the patterning the first conductive material; patterning the auxiliary layer together with patterning the first conductive material; isotropically etching back the auxiliary layer so that a remaining area of the auxiliary layer is not completely removed; applying a second insulating material before applying the second conductive material, exposing a remainder of the auxiliary layer after applying the second insulating material; removing subareas of the auxiliary layer; and producing an isolating layer on areas which are not covered by the auxiliary layer.