Patent ID: 8570064

Claim:
A system comprising: first differential input buffer circuitry configured to output a first input buffer circuitry output signal by comparing a first signal level at an input/output pad with a second signal level; termination circuitry configured to provide a controllably variable impedance associated with the input/output pad; control circuitry configured to control the controllably variable impedance provided by the termination circuitry based at least in part on a voltage level of the first differential input buffer circuitry output signal; and second differential input buffer circuitry configured to output a second differential input buffer circuitry output signal by comparing the first signal level associated with the input/output pad with a third signal level, wherein: the third signal level is different from the second signal level, the control circuitry is further configured to control the impedance provided by the termination circuitry based at least in part on the second differential input buffer circuitry output signal, the first differential input buffer circuitry comprises high speed transceiver logic (HSTL) circuitry, and the second differential input buffer circuitry comprises low voltage differential buffer (LVDS) circuitry.