Patent ID: 8073090

Claim:
A method of performing clock calibration and de-skew on a multi-lane high speed serial interface, comprising: receiving a plurality of first data frames on a plurality of serial lane transceivers, wherein each of the plurality of first data frames includes a training sequence header pattern; generating a plurality of event signals based on each of the first data frames; and aligning a core clock, having a first phase, with the first data frame of the plurality of first data frames associated with a slowest bit lane based on the plurality of event signals, wherein aligning the core clock comprises: detecting a change in status of a composite event signal, wherein the composite event signal is active when all of the plurality of event signals are asserted; initiating a counter based on the change in status, wherein the counter has the same period as the core clock and a maximum value based on a period of the training sequence training sequence header pattern; and increasing the first phase based on a core clock phase control signal until the counter equals 0 and the composite event signal becomes inactive.