Patent ID: 8352772

Claim:
A receiver comprising: a signal node to receive an input signal at a first bit rate, the input signal expressed as a sequence of multi-bit words; a clock node to receive a reference clock signal having a plurality of reference-clock edges, a respective one of the plurality of reference clock edges aligned to a corresponding bit of each of the multi-bit words and an edge rate less than the first bit rate; a locked loop coupled to the clock node, the locked loop to derive from the reference clock signal a bit-recovery clock signal exhibiting a first sampling rate equal to the first bit rate, and to derive from the reference clock signal a word clock signal having respective word-clock edges aligned to each of the corresponding bits of the words; and a deserializer having a deserializer input node coupled to the signal node, a first deserializer clock node coupled to the locked loop to receive the bit-recovery clock signal, and a second deserializer clock node coupled to the locked loop to receive the word clock signal, the deserializer to sample the input signal with the bit-recovery clock signal at the first sampling rate to recover the multi-bit words, and to deserialize the multi-bit words to produce parallel words synchronized to the word clock signal.