Patent ID: 8417836

Claim:
A method for controlling a serial peripheral interface, comprising: detecting initiation of one of a data read and a data write operation according to one of a first and a second protocol in response to one or more signals on one or more of a data signal line, a clock signal line, and a select signal line; performing the data read operation upon a register identified by address bits received serially on the data signal line following detection of the initiation of the data read operation; and performing the data write operation upon a register identified by address bits received serially on the data signal line following detection of the initiation of the data write operation, performing the data write operation including storing first data bits received serially on the data signal line following first address bits received serially on the data signal line in a configuration register identified by the first address bits, and storing second data bits received serially on the data signal line following a number of second address bits received serially on the data signal line in a register identified by the second address bits, at least one of the first data bits being an address length mode bit, and the number of second address bits being based on a value of the address length mode bit.