Patent ID: 7592224

Claim:
A method of fabricating a storage device in an array of storage cells, comprising: forming first and second trenches in a semiconductor layer, wherein the first and second trenches are immediately adjacent trenches; forming first and second source/drain regions underlying the first and second trenches, respectively; forming first and second select gates in the first and second trenches, respectively; forming a charge storage stack overlying the first and second select gates, wherein the charge storage stack includes a layer of discontinuous storage elements (DSEs), wherein, within a storage cell, a plurality of DSEs lies within at least one of the first and second trenches and over a first portion of the semiconductor layer between the first and second trenches; forming a control gate overlying the charge storage layer; and forming third source/drain regions that are spaced apart from each other and lie within second portions of the semiconductor layer between the first and second trenches.