Patent ID: 8283248

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a plurality of preliminary gate structures on a substrate; forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures and on a top surface of the substrate between the preliminary gate structures; forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed between the blocking layer and the capping layer pattern; removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, a lower portion of the capping layer pattern remaining on lower sidewalls of the preliminary gate structures; forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures; reacting the conductive layer with the preliminary gate structures to form a plurality of gate structures; and forming a second insulation layer on the substrate to cover the gate structures, the second insulation layer having an air gap therein between the plurality of gate structures.