Patent ID: 7746121

Claim:
A low voltage differential signaling (LVDS) output stage circuit comprising: a first supply voltage port for receiving of a first potential; a second supply voltage port for receiving of a second potential that is lower than the first potential; a differential input port, comprising a first input port and a second input port, for receiving of a differential input signal having transitions between the first and second potentials; a follower output stage formed with a thin oxide semiconductor manufacturing process comprising first and second NMOS pull-up FET devices and first and second PMOS pull-down FET devices disposed between the first and second supply voltage ports for being biased between the first and second potentials; a differential output port formed between junctions of the first NMOS pull-up FET device and the first PMOS pull-down FET device and the second NMOS pull-up FET devices and the second PMOS pull-down FET devices for providing of a low voltage differential signal therefrom; a first set of coupling capacitors disposed between the first input port and gate terminals of the first NMOS pull-up FET device and the first PMOS pull-down FET device; a second set of coupling capacitors disposed between the second input port and gate terminals of the second NMOS pull-up FET device and the second PMOS pull-down FET device; and DC restoration circuitry formed with a thick oxide semiconductor manufacturing process and coupled with each of the gate terminals of the FET devices for providing of a DC potential thereto.