Patent ID: 7848318

Claim:
Serializer circuitry on an integrated circuit comprising: a source of parallel data; first multiplexer circuitry for receiving bits from even-bit positions in the parallel data and for outputting those even bits one after another in succession; second multiplexer circuitry for receiving bits from odd-bit positions in the parallel data and for outputting those odd bits one after another in succession; third multiplexer circuitry for receiving successive bits output by the first and second multiplexer circuitries and for alternately outputting those bits from the first and second multiplexer circuitries to produce a serial data output signal of the serializer circuitry, wherein each of the first and second multiplexer circuitries is controllable, by an output signal of memory circuitry on the integrated circuit, with respect to how many bits that first or second multiplexer circuitry receives in parallel from the source of parallel data; a further source of parallel data, having width greater than the source of parallel data; and fourth multiplexer circuitry for applying parallel data from the further source to the source, the fourth multiplexer circuitry being controllable by a further output signal of the memory circuitry, if the width of the further source data is greater than the source, to subdivide the data from the further source to subdivisions that the fourth multiplexer circuitry applies one after another in succession to the source.