Patent ID: 7629817

Claim:
An apparatus, comprising a latch and a sense amplifier wherein: the latch comprises: a first transistor connected at the gate to a first input signal voltage; a second transistor connected at the gate to a second input signal voltage; a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors; and wherein: activating the first or second transistor transmits a signal sample from the latch to the sense amplifier; and deactivating the first and second transistors prevents the signal sample from being transmitted from the latch; and the sense amplifier comprises: a first sense amplifier transistor configured to receive at the gate a first input signal sample voltage; a second sense amplifier transistor configured to receive at the gate a second input signal sample voltage; a third sense amplifier transistor configured to receive at the gate a first output signal sample voltage; a fourth sense amplifier transistor configured to receive at the gate a second output signal sample voltage; wherein: the first, second, third, and fourth sense amplifier transistor are coupled together and operable to simultaneously compare the input signal sample voltages and the output signal sample voltages; and a pair of reset transistors, the reset transistors being operable to reset the first output signal sample voltage and the second output signal sample voltage to a common level; wherein: the first, second, third, and fourth sense amplifier transistors are activated by a first clock signal; the reset transistors are activated by a second clock signal; and the first clock signal is complementary to the second clock signal.