Patent ID: 8365044

Claim:
A memory device comprising: a memory array comprising a plurality of memory cells configured to store data; and error correction circuitry coupled to the memory array and configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to at least one predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the at least one bit position corresponding to the predetermined defect location in the memory array; wherein the predetermined defect location in the memory array is determined to be defective before the data word is retrieved from the memory array; wherein the error correction circuitry is configured to identify said at least one bit position corresponding to a predetermined defect location in the memory array by: determining at least one stored defective word address identifying a word of the memory array comprising the predetermined defect location; and determining at least one stored output address corresponding to the at least one stored defective word address; and wherein determining the at least one stored defective word address comprises comparing a read address used to retrieve the data word from the memory array to the at least one stored defective word address; and wherein the at least one stored output address identifies the at least one bit position corresponding to the predetermined defect location within the word identified by the corresponding at least one stored defective word address.