Patent ID: 7525352

Claim:
A memory device comprising: a memory array; and a differential buffer operatively coupled to the memory array, the differential buffer comprising: a differential pair including a first transistor and a second transistor, the differential pair configured to receive a plurality of input signals and to generate a plurality of output signals; a third transistor and a fourth transistor coupled in series with the first and second transistors, respectively; adjustment circuitry coupled to the differential pair and configured to enable adjustment of a level of current dissipated by the differential buffer, the adjustment circuitry including a fifth transistor coupled in parallel to the third transistor and a sixth transistor coupled in parallel to the fourth transistor; and current pulse circuitry coupled to the differential pair and the adjustment circuitry, wherein the current pulse circuitry is configured to generate a current pulse that is coincident with switching of the differential pair, and wherein the current pulse circuitry includes a seventh transistor coupled in series with an eighth transistor, and a ninth transistor coupled in series with a tenth transistor; wherein the gate of the seventh transistor and the gate of the eighth transistor are coupled to the gate of the first transistor, wherein the gate of the ninth transistor and the gate of the tenth transistor are coupled to the gate of the second transistor, wherein the seventh and the eighth transistors include an n-channel and a p-channel transistor, and wherein the ninth and the tenth transistors include an n-channel and a p-channel transistor.