Patent ID: 7103857

Claim:
A method for implementing enhanced performance with reduced quiescent power dissipation using mixed threshold CMOS devices in latch circuit designs including level sensitive scan design (LSSD) latches comprising the steps of: identifying logic blocks in critical data and data clock paths of a L 1 latch and a L 2 latch of a LSSD latch; substituting a low voltage threshold (LVT) transistor to replace each regular voltage threshold (RVT) transistor used in said identified logic blocks in the critical data and data clock paths of said L 1 latch and said L 2 latch of said LSSD latch; and selectively implementing non-critical sections of said L 1 latch and said L 2 latch of said LSSD latch including scan input and scan clock paths only with RVT transistors, or low leakage (LLD) transistors.