Patent ID: 7105881

Claim:
A DRAM construction, comprising: a substrate comprising an upper surface; a first transistor gate structure over the substrate; a pair of source/drain regions within the substrate and on opposing sides of the first transistor gate structure from one another, the source/drain regions being gatedly connected to one another through the first transistor gate structure; one of the source/drain regions being a first source/drain region and the other of the source/drain regions being a second source/drain region, the first source/drain region comprising a plurality of conductivity-enhanced regions wherein at least two of the plurality of the conductivity-enhanced regions extend into the substrate an equal distance from the upper surface; a capacitor electrically connected with the first source/drain region; a bitline electrically connected with the second source/drain region; a halo region comprising at least a portion of the second source/drain region, and the first source/drain region comprising no halo region, and wherein the halo region extends into the substrate elevationally below a remainder of the second source/drain region; and a conductive interconnect providing the electrical connection between the capacitor and the first source/drain region.