Patent ID: 7296201

Claim:
A method for testing a circuit when in the course of said testing information is developed that indicates that an error is present in one or more signals S j,l (k), where j is an index that distinguishes different ones of said signals, l is a level indicator that is initially set at 0, and k indicates a number of operational clock periods following a given condition when said error signals appear, said method starting with a variable m equal to k, and comprising the steps of: for at least one of the signals S j,i (m), (a) identifying an associated fanin cone; (b) re-testing said circuit, and capturing input signals of said fanin cone; (c) processing information about said fanin cone to (1) identify an error within said fanin cone, or (2) identify a collection of input signals of said fanin code that potentially are at in error, and further identify said collection of input signals to be (i) input signals of the circuit, or (ii) internal signals of said circuit S j,i (k), with index l incremented by 1, that are output signal of memory elements of said circuit, each storing associated p logic values, and each having been subjected to an input signal S j,i (m−p); (d) setting m to m−p, thus forming signals S j,i (m), and with respect to each of the formed signals S j,l (m) returning to step (a); and (e) terminating said method when no input signals of any fanin code is identified as an output signal of a memory element of said circuit.