Patent ID: 8266566

Claim:
A computer-implemented method of placing spare cells in an integrated circuit design, comprising: receiving a description of the integrated circuit design which includes at least one logic cone in a layout and a stability value associated with the logic cone, by executing first program instructions in a computer system; assigning a desired spare cell utilization rate to the logic cone based on the stability value, by executing second program instructions in the computer system; calculating an actual spare cell utilization rate for a bounding box of the logic cone, by executing third program instructions in the computer system; determining that the actual spare cell utilization rate is less than the desired spare cell utilization rate, by executing fourth program instructions in the computer system; computing additional area required in the bounding box for attaining the desired spare cell utilization rate, by executing fifth program instructions in the computer system; and inserting, in the description of the integrated circuit design, one or more spare cells within the bounding box to completely fill the additional area, by executing sixth program instructions in the computer system.