Patent ID: 8838938

Claim:
In a microprocessor that has an instruction set architecture in which the instructions may include a variable number of prefix bytes, an apparatus for extracting instructions from a stream of undifferentiated instruction bytes, the apparatus comprising: decode logic, configured to determine which byte is an opcode byte for each instruction of a plurality of instructions within the stream of undifferentiated instruction bytes, wherein the opcode byte is the first non-prefix byte of the instruction, the decode logic further configured, for each instruction byte of the instruction byte stream, to accumulate prefix information from any preceding prefix bytes into a corresponding bit array to accompany the instruction byte; a queue, coupled to the decode logic, configured to hold the stream of undifferentiated instruction bytes and the accumulated prefix information, including the accumulated prefix information bit arrays; and extraction logic, coupled to the queue, configured to extract the plurality of instructions from the queue in one clock cycle independent of the number of prefix bytes included in each of the plurality of instructions; and wherein the extraction logic is configured to extract the plurality of instructions from the queue in one clock cycle independent of the number of prefix bytes included in each of the extracted instructions by extracting the accumulated prefix information rather than extracting the prefix bytes included in each of the plurality of instructions, and forwarding each instruction, not including its prefixes, together with the accumulated prefix information associated with the opcode byte of the instruction, to a subsequent pipeline stage of the processor.