Patent ID: 8108821

Claim:
A computer-implemented method for reducing logic and delay within a logic structure in a circuit the method comprising: searching, by using a computer, logic structures to be analyzed; finding a plurality of latches within a logic structure to be analyzed; determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed; when there is at least one remaining latch to be analyzed, determining whether inverters are disposed within an input path and an output path of the at least one remaining latch; obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found; modifying the logic functions using DeMorgan's Theorems, wherein the modifying simplify the logic functions; determining whether timing violations exist with the modified logic functions; and annotating hardware description language based on the modified logic functions when no timing violations exist; and wherein modifying the logic functions using Demorgan's Theorems comprises modifying the logic function at the input path such that the modified logic function is a complement of the logic function at the input path prior to being modified and with a reversed latch output polarity the logic function at the output path remains a same logic function as the logic function at the output path prior to being modified.