Patent ID: 7696559

Claim:
A semiconductor memory device comprising: a semiconductor substrate; an impurity diffusion layer formed in a cell array area of the semiconductor substrate to serve as a common source line in the cell array; a gate wiring stack body formed on the cell array area of the substrate with an elongate pattern, in which multiple gate wirings are stacked and separated from each other with insulating films interposed therebetween; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; a plurality of pillar-shaped semiconductor layers arranged in the elongated direction of the gate wiring stack body at a certain pitch, at least one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, other side surfaces thereof being in contact with a device isolating dielectric film, each the pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer and a lower impurity concentration than the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings, the gate wiring stack body and one of the pillar-shaped semiconductor layers opposed to the gate wiring stack body via the gate insulating film comprising a NAND cell unit, the NAND cell unit including vertical select gate transistors formed at the lowest portion and the uppermost portion of the pillar-shaped semiconductor layer with the gate wirings serving as select gate lines and vertical memory cells stacked between the vertical select gate transistors with the gate wirings serving as word lines, wherein one side surface of each pillar-shaped semiconductor layer is opposed to the gate wiring stack body while the remaining three side surfaces thereof are in contact with a device insulating film.