Patent ID: 8581302

Claim:
A semiconductor device comprising: a semiconductor chip having a main surface; a plurality of input/output circuit cells formed along the periphery of the main surface; an internal circuit formed in the main surface so that the internal circuit is surrounded with the input/output circuit cells; and a plurality of electrode pads placed in areas corresponding to each of the input/output circuit cells, wherein the input/output circuit cells include: a first input/output circuit cell and a second input/output circuit cell placed adjacently to each other; and a first electrode pad and a second electrode pad placed in areas respectively corresponding to the first and second input/output circuit cells with a predetermined distance in between, wherein the first and second input/output circuit cells include a first inverter circuit and a second inverter circuit that output complementary signals different in phase from each other according to an identical signal outputted from the internal circuit, wherein the output of the first inverter circuit of the first input/output circuit cell and the output of the first inverter circuit of the second input/output circuit cell are coupled in common to the first electrode pad through a first wiring located below a wiring layer comprising the first electrode pad, wherein the output of the second inverter circuit of the first input/output circuit cell and the output of the second inverter circuit of the second input/output circuit cell are coupled in common to the second electrode pad through a second wiring formed in the same layer as the first wiring, wherein the first electrode pad is placed between the output of the first inverter circuit of the first input/output circuit cell and the output of the first inverter circuit of the second input/output circuit cell in a direction along the periphery of the semiconductor chip, wherein the second electrode pad is placed between the output of the second inverter circuit of the first input/output circuit cell and the output of the second inverter circuit of the second input/output circuit cell in a direction along the periphery of the semiconductor chip, wherein the first wiring coupling together the first electrode pad and the output of the first inverter circuit of the second input/output circuit cell is so formed that the first wiring is astride areas where the first and second input/output circuit cells are formed, and wherein the second wiring coupling together the second electrode pad and the output of the second inverter circuit of the first input/output circuit cell is so formed that the second wiring is astride areas where the first and second input/output circuit cells are formed.