Patent ID: 8373450

Claim:
A method for generating an error voltage across a coupling capacitor in a switching circuit device and for amplifying and integrating said error voltage, said method being used in a system comprising the switching circuit device and a clock generator to control the switching circuit device, said switching circuit device further comprising a reference voltage terminal connectable to a reference voltage, a switched capacitor, a bias current terminal connectable to a bias current for charging the switched capacitor, an amplifier to receive the error voltage via the coupling capacitor and an integrating capacitor on which to integrate the amplified error voltage, said method comprising: executing a charge phase comprising the steps: charging the switched capacitor; auto-zeroing the amplifier whereby its input is allowed to establish a quiescent operating voltage corresponding to a quiescent operating point of the amplifier; executing a hold phase at an end of the charge phase the hold phase comprising the steps: holding the switched capacitor at a charged voltage reached at the end of the charge phase; connecting the switched capacitor to the coupling capacitor; maintaining the auto-zeroing configuration of the amplifier; executing a discharge phase comprising the steps: discharging the switched capacitor; disconnecting the switched capacitor from the coupling capacitor and connecting the reference voltage to the coupling capacitor thereby storing the error voltage across the coupling capacitor, said error voltage being the difference between the reference voltage and the charged voltage; amplifying the error voltage using the amplifier and integrating the amplified error voltage onto the integrating capacitor in order to obtain an integrated amplified error voltage; wherein the charge, hold and discharge phases are cycled sequentially on a continuous basis.