Patent ID: 8133777

Claim:
A method of fabricating a memory, the method comprising: providing a substrate including a memory region and a periphery region, wherein a plurality of gates is formed on the substrate and a sidewall of each of the gates has a first spacer, wherein the gates in the memory region have a plurality of first openings therebetween; forming a first material layer on the substrate in the memory region, wherein the first material layer covers the gates in the memory region and fills the first openings; forming a barrier layer on the substrate to cover the gates in the periphery region and the first material layer in the memory region; forming a second material layer on the substrate in the periphery region to cover the barrier layer on the gates in the periphery region; removing the barrier layer covering the first material layer; removing the first material layer partially to form a plurality of second openings, wherein each of the second openings is disposed on a top of each of the gates in the memory region; forming a first pattern in each of the second openings; removing a remaining of the first material layer to form a plurality of contact openings in the memory region; and forming a contact plug in each of the contact openings, wherein the first patterns are disposed between the contact plugs.