Patent ID: 8330506

Claim:
A frequency multiplier circuit, comprising: a first stage including a first differential pair of amplifier elements having respective current conduction paths connected in parallel between first and second nodes and respective control terminals connected to receive input signals of opposite polarity at an input frequency in the radio frequency range, said first and second nodes being connected to respective bias voltage supply terminals through first and second impedances respectively so that current flowing differentially in said current conduction paths of said first differential pair of amplifier elements produces a voltage difference across said first and second nodes at a frequency which contains a harmonic of said input frequency; a second stage including a second differential pair of amplifier elements; radio frequency connections for applying said voltage difference across said first and second nodes at the frequency of said harmonic to said second differential pair of amplifier elements to amplify differentially said voltage difference and produce an output signal at said harmonic of said input frequency, said radio frequency connections blocking direct current; and direct current connections for connecting said second differential pair of amplifier elements across said bias voltage supply terminals separately from, and in parallel with, direct current connections for said first differential pair of amplifier elements.