Patent ID: 8859945

Claim:
A data processing circuit, comprising: a data processing unit comprising first and second signal conversion circuits, each having a signal input and a signal output, and a plurality of controlled switches connected to the inputs and outputs of the conversion circuits, wherein the data processing unit further comprises a binary signal input and a binary signal output, a memory unit comprising a plurality of capacitors connected to a memory bus arrangement via a plurality of switches, each capacitor storing a binary datum, wherein the bus is connected to the processing unit, a plurality of inputs for control signals of the controlled switches, wherein the data processing unit is capable of carrying out at least the following operations in response to control signal data sequences: writing in a capacitor a binary datum applied to an input line, reading in a capacitor a binary datum that is stored therein, and applying the read binary datum to an output line, and logically combining binary data stored in at least two capacitors.