Patent ID: 7592217

Claim:
A method for fabricating a capacitor, comprising: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO 2 ) layer and an aluminum oxide (Al 2 O 3 ) layer; performing a low temperature annealing process on a substrate structure including the storage node and the multi-layered dielectric structure to remove impurity, oxygen defect and surface roughness in the multi-layered dielectric structure; after performing the low temperature annealing process, performing a rapid thermal process (RTP) of a high temperature annealing on the substrate including the storage node and the multi-layered dielectric structure to increase dielectric constants of the ZrO 2 layer and the Al 2 O 3 layer using an ambient gas selected from the group consisting of N, Ar and He; and forming a plate electrode on the multi-layered dielectric structure, wherein the ambient gas flows in an amount of approximately 5 sccm to approximately 5 slm.