Patent ID: 7650598

Claim:
A method for allocating registers for a processor, said processor comprising a first cluster and a second cluster, each cluster comprising a first functional unit, a second functional unit, a first local register file connected to said first functional unit, a second local register file connected to said second functional unit, and a global register file having a ping-pong structure formed by a first register bank and a second register bank, said global register file being connected to the first and second functional units, said method comprising steps of: (a) building a graph comprising nodes, circles and first edges, wherein each node is labeled with at least one of said first functional unit and said second functional unit, each circle indicating whether the register is allocated, each first edge being connected between two of the circles indicating data dependency therebetween; (b) allocating one of the first and second functional units to the nodes labeled with the first and second functional units concurrently in said graph; (c) allocating the first, second and global register files to unallocated circles based on the corresponding nodes of the unallocated circles allocated by the first functional unit or the second functional unit; (d) allocating said first register bank and said second register bank to the circles allocated to the global register file based on whether the circles allocated to the global register file are linked through only one node in the graph; and (e) adding at least one node to communicate between the first cluster and the second cluster or between the global register file and the first and second local register files.