Patent ID: 7876313

Claim:
A display controller configured for use within a display panel, the display controller comprising: low response-time (LRT) compensation logic; and processing circuitry to receive either an interleaved pixel stream or a non-interleaved pixel stream from a graphics controller, the interleaved pixel stream comprising pixels of a current frame interleaved with pixels of a prior frame, the interleaved pixel stream provided over a display cable from the graphics controller to the display controller, the non-interleaved pixel stream comprising pixels of a current frame without pixels of a prior frame, wherein when an interleaved pixel stream is received, the processing circuitry is to instruct the LRT compensation logic to apply LRT compensation for each pixel of the current frame based on values of pixels of the current frame and corresponding pixels of the prior frame, wherein when a non-interleaved pixel stream is received, the processing circuitry is either to instruct the LRT compensation logic to refrain from applying LRT compensation to the pixel values of the current frame or to bypass the LRT compensation logic, wherein the LRT compensation logic is to generate compensated pixel values for a display, wherein when a non-interleaved pixel stream is received, the display controller is to receive pixels of the non-interleaved pixel stream from the graphics controller at a frame-refresh pixel rate, wherein when an interleaved pixel stream is received, the display controller is to receive pixels of the interleaved pixel stream at twice the frame-refresh pixel rate, and wherein receiving the interleaved pixel stream over the display cable allows the display controller to operate without a need for a frame buffer to buffer pixels of prior frames when LRT compensation is applied.