Patent ID: 8115878

Claim:
A Thin Film Transistor (TFT) array substrate, comprising: a plurality of scanning lines, a plurality of data lines and a plurality of pixel regions, wherein each pixel region is defined by an intersection of two adjacent scanning lines and two adjacent data lines, and comprises a pixel electrode, a first TFT for controlling the pixel electrode, a pull alignment electrode, a second TFT for controlling the pull alignment electrode, a first push alignment electrode and a second push alignment electrode; a projection of the pull alignment electrode on the TFT array substrate is located within the pixel electrode and is electrically insulated from the pixel electrode; and projections of the first push alignment electrode and the second push alignment electrode on the TFT array substrate are respectively located at two opposite sides of the pixel electrode, when a voltage is applied to the TFT array substrate, a transverse pull electric field is formed between the pull alignment electrode and the pixel electrode, and transverse push electric fields are formed respectively between the first push alignment electrode and the pixel electrode and between the second push alignment electrode and the pixel electrode.