Patent ID: 7864149

Claim:
A display panel, comprising: a plurality of pixels, each pixel comprising: a gate line to receive a gate pulse that is maintained at a gate-on voltage during one horizontal scanning period (a 1 H period); a data line insulated from and crossing the gate line to receive a data voltage; a main storage electrode to receive a first common voltage, the first common voltage varying with the gate pulse and the polarity of the data voltage; a sub storage electrode to receive a second common voltage that is maintained at a constant voltage level; a main pixel electrode capacitively coupled to the main storage electrode; a sub pixel electrode capacitively coupled to the sub storage electrode; a first thin film transistor connected to the gate line, the data line, and the main pixel electrode; and a second thin film transistor connected to the gate line, the data line, and the sub pixel electrode; wherein the main pixel electrode receives the data voltage from the first thin film transistor during the 1 H period and then its voltage is changed into a main pixel voltage different from the data voltage in response to a variation of the first common voltage, and the sub pixel electrode receives the data voltage from the second thin film transistor during the 1 H period and then its voltage is maintained as a sub pixel voltage until it receives the next data voltage from the second thin film transistor.