Patent ID: 8338893

Claim:
An isolation structure for a semiconductor device comprising: a semiconductor substrate having at least one trench formed in an active area of the semiconductor substrate, the semiconductor substrate is characterized by a first conductivity type; a buffered oxide layer overlying the semiconductor substrate; a pad nitride layer overlying the buffered oxide layer; an implanted region around a perimeter of the trench, the implanted region having dopants of the first conductivity type and a higher dopant concentration than the semiconductor substrate; a P-well region surrounding a perimeter of the at least one trench region; and a channel region within the P-well region and adjacent to the trench wherein the at least one trench includes a bottom width of less than 0.13 microns and an upper width of less than 0.13 microns; and wherein the at least one trench includes a periphery having a rounded edge having a radius of curvature greater than about 0.02 um.