Patent ID: 8237869

Claim:
An apparatus comprising: a first analog-to-digital converter (ADC) to receive a first intermediate frequency (IF) signal of a first digital video broadcast (DVB) standard and to convert the first IF signal to a first digital IF signal; a second ADC to receive a second IF signal of a second DVB standard and to convert the second IF signal to a second digital IF signal; a shared front end to receive a selected one of the first and second digital IF signals and to convert the selected digital IF signal to a baseband signal; a first digital demodulator to digitally demodulate the baseband signal according to the first DVB standard if the baseband signal is from the first IF signal; a second digital demodulator to digitally demodulate the baseband signal according to the second DVB standard if the baseband signal is from the second IF signal; a first equalizer to perform equalization on the demodulated signal output from the first digital demodulator to obtain a first equalized signal; a second equalizer to perform equalization on the demodulated signal output from the second digital demodulator to obtain a second equalized signal; a third equalizer to perform equalization on the demodulated signal output from the first digital demodulator to obtain a third equalized signal; a shared forward error correction (FEC) circuit to perform forward error correction on the selected one of the first, second, and third equalized signals, wherein the shared FEC circuit includes a first input port to receive the first equalized signal at a beginning location of a signal processing path of the shared FEC circuit, a second input port to receive the second equalized signal at a second location of the signal processing path downstream of the beginning location, and a third input port to receive the third equalized signal at a third location of the signal processing path downstream of the second location; and a transport stream interface to receive and output a FEC-corrected signal received from the shared FEC circuit, wherein at least the shared front end, the first and second digital demodulators, the first second and third equalizers, and the shared FEC circuit are integrated on a single semiconductor die.