Patent ID: 8008781

Claim:
An electronic chip package comprising: an electronic chip having a first contact pad and a second contact pad thereon, the electronic chip being free of an intervening contact pad between the first and second contact pads; a first dielectric layer coupled to the electronic chip over the first and second contact pads, the first dielectric layer having a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto; a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed between a top surface of the first dielectric layer and a bottom surface of the second dielectric layer, the second dielectric layer having a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad; a first cover pad having a cover pad aperture therethrough and positioned along the dielectric layer boundary at a location corresponding to the first contact pad; a second cover pad coupled to a top surface of the second dielectric layer at a location corresponding to the second contact pad; and a second metal interconnect positioned in the second contact pad multi-layer via and extending from the second cover pad down to the second contact pad.