Patent ID: 7736915

Claim:
A charge neutralizing method, comprising: presetting a limit sufficient for a trapped charge in a charge accumulation layer to cause a semiconductor structure to malfunction if the limit is exceeded by the trapped charge, wherein the semiconductor structure comprises (a) a semiconductor layer, (b) the charge accumulation layer on top of the semiconductor layer, (c) a doped region in direct physical contact with the semiconductor layer, and (d) a device layer on top of and in direct physical contact with the charge accumulation layer, wherein the device layer comprises a plurality of device regions electrically insulated from each other, wherein the charge accumulation layer comprises trapped charges of a first sign, and wherein the doped region and the semiconductor layer form a P-N junction diode; after said presetting the limit, generating free charges in the P-N junction diode, wherein the free charges are of a second sign opposite to the first sign; after said generating free charges in the P-N junction diode, ascertaining that the trapped charge in the charge accumulation layer exceeds the limit that had been preset; and responsive to said ascertaining, applying a first voltage to the doped region and applying a second voltage to the semiconductor layer and applying a third voltage to the device layer, wherein the third voltage exceeds the first voltage and the second voltage and causing acceleration of the free charges toward the device layer, resulting in some of the free charges entering the charge accumulation layer and neutralizing some of the trapped charges in the charge accumulation layer.