Patent ID: 7681078

Claim:
A method for operating a processor in a data processing system, the method comprising: asserting a debug control signal to cause the processor to enter a debug operating mode; initializing a plurality of shared processor resources with debug configuration information, wherein the plurality of shared processor resources are shared between a normal operating mode and the debug operating mode; executing instructions with the processor while in the debug operating mode; re-initializing the processor in response to a reset event; and preventing the reset event from re-initializing a predetermined portion of the debug configuration information in the plurality of shared processor resources by writing a first predetermined control value to at least one reset blocking control bit of a debug control register, preventing a first reset event from re-initializing the predetermined portion of the debug configuration information, re-writing the at least one reset blocking control bit with a second predetermined control value in response to the first reset event, and re-initializing the predetermined portion of the debug configuration information in response to a second reset event.