Patent ID: 7826270

Claim:
A nonvolatile semiconductor memory device, comprising: a first MOS transistor used as a memory element and having a low ON withstanding voltage that is a drain withstanding voltage when a gate thereof is turned on; and a second MOS transistor having a high ON withstanding voltage, the first MOS transistor and the second MOS transistor being arranged on a same substrate, wherein: a first voltage that is higher than or equal to a threshold voltage of the first MOS transistor, and a second voltage that is higher than or equal to the ON withstanding voltage of the first MOS transistor and is lower than or equal to the ON withstanding voltage of the second MOS transistor are applied respectively to a gate electrode and a drain of the first MOS transistor so that a short-circuit occurs in a PN junction between the drain and the substrate of the first MOS transistor to write data; and the second voltage is applied to a drain of the second MOS transistor to read the data.