Patent ID: 7522000

Claim:
A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: an apparatus comprising: a differential amplifier circuit comprising a coupled pair of field effect transistor semiconductor devices, the differential amplifier circuit being employed in an environment where a minimum output amplitude must be met for compliance with a communication protocol; a biasing circuit; a coupling circuit operatively connected to said differential amplifier circuit and said biasing circuit, the coupling circuit comprising a field effect transistor semiconductor device coupled with the source and body terminals of the coupled pair of field effect transistor semiconductor devices; said coupling circuit recognizing a powering down event for said differential amplifier circuit and applying a biasing voltage from said biasing circuit to said differential amplifier circuit during the recognized powering down event, the biasing voltage protecting the differential amplifier circuit against degradation otherwise possible due to voltages imposed during the powering down event.