Patent ID: 8558368

Claim:
A method of packaging an integrated circuit having a first vertical MOSFET and a second vertical MOSFET, the method comprising: encapsulating the integrated circuit within a package body, the package body having an outer surface with a first dimension and a second dimension longer than the first dimension; and disposing a first plurality of pin connections and a second plurality of pin connections along a length of the second dimension on respective opposite sides of the package body, such that: each of the first plurality of pin connections are electrically connected to one of a first plurality of contacts disposed on a single side of a semiconductor die in which the first vertical MOSFET is disposed, the first plurality of contacts comprising a drain contact, a gate contact, and a source contact of the first vertical MOSFET; and each of the second plurality of pin connections are electrically connected to one of a second plurality of contacts disposed on a single side of a semiconductor die in which the second vertical MOSFET is disposed, the second plurality of contacts comprising a drain contact, a gate contact, and a source contact of the second vertical MOSFET.