Patent ID: 7127594

Claim:
A multiprocessor system comprising: a plurality of processors; and an instruction storage section for storing instructions in a program, wherein the system has a first program control mode for operating the plurality of processors under a single program control and a second program control mode for operating the plurality of processors under a plurality of independent program controls, each of the plurality of processors includes a program controller having a program synchronization flag, the program synchronization flag holding program synchronization information indicating either the first or second program control mode, and one of the plurality of processors serving as a master processor performs program control over the entire multiprocessor system and notifies the instruction storage section of updated program synchronization information when the program synchronization information is updated, and wherein the instruction storage section has instruction memories of the same number as that of the plurality of processors, when the program synchronization information from the master processor indicates the first program control mode, the instruction memories are operated as a single memory bank, and an instruction address output from the master processor is sent to the instruction memories and a single item of instruction data is output, and when the program synchronization information indicates the second program control mode, the instruction memories are operated as a plurality of individual memory banks, and instruction addresses output from the processors are sent to the corresponding instruction memories and a plurality of items of instruction data are output.