Patent ID: 8131909

Claim:
A field programmable gate array (FPGA) system, comprising: a programmable logic fabric including a logic and routing block having a plurality of dedicated logic cells, each dedicated logic cell having a first logic and routing cell and a second logic and routing cell; a signal processing unit comprising a floating point unit for computing information, the floating point unit having a based-based input and a bus-based output; a plurality of configurable dedicated connection circuits, the plurality of configurable dedicated connection circuits being interconnected with one another through bus-based connections to form a bus architecture, each configurable dedicated connection circuit having a plurality of bus-based inputs, a plurality of bus-based outputs, and a multiplexer, the multiplexer having configuration bits for routing a first bus-based input in the plurality of bus-based inputs via a first bus to a first bus-based output in the plurality of bus-based outputs each configurable dedicated connection circuit being directly connected to one signal processing unit; a configurable bus-based dedicated connection circuit having one or more bus-based input and one or more bus-based outputs a first bus-based input of the configurable bus-based dedicated connection circuit coupled to the bus-based output of the floating point unit, a first bus-based output of the configurable bus-based dedicated connection circuit coupled to the bus-based input of the floating point unit; one or more first dedicated lines connecting from the first logic and routing cell in a first dedicated logic cell of the logic and routing block to the floating point unit of the signal processing unit; and one or more second dedicated lines connecting from the floating point unit of the signal processing unit to the first logic and routing cell in the first dedicated logic cell of the logic and routing block.