Patent ID: 8103984

Claim:
A computer-aided design system configured to generate photolithographic data for patterning a circuit design onto a semiconductor wafer, comprising: a design tool having a processor, a memory connected to the processor, and a non-transitory computer readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of: receiving target layout data for the circuit design; performing optical proximity correction on the target layout data to generate post-OPC layout data; generating contour layout data from post-OPC layout data; and calculating differences between the contour layout data and the target layout data to generate contour bias data; and a manufacturing tool having a processor, a memory connected to the processor, and a non-transitory computer readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of: receiving the target layout data for the circuit design and the contour bias data from the design tool; applying the contour bias data to the target layout data to regenerate contour layout data at the manufacturing tool; and performing optical proximity correction on the regenerated contour data to generate second post-OPC layout data.