Patent ID: 7202703

Claim:
A circuit comprising: an evaluate clock trace to receive an evaluate clock signal; a precharge clock trace to receive a precharge clock signal; sample circuitry coupled to a first signal trace, a second signal trace, the precharge clock trace and the evaluate clock trace, the sample circuitry to facilitate a detection of a transition on the first signal trace from a first voltage level to a second voltage level; latch circuitry coupled to the first signal trace, the second signal trace, the precharge clock trace and the evaluate clock trace to utilize at least a portion of the sample circuitry to maintain voltage levels on the first and the second signal traces when an evaluate clock and a precharge clock are inactive; and wherein the sample circuitry comprises: evaluate circuitry coupled to a third signal trace, a fourth signal trace and the evaluate clock trace to facilitate coupling the third and the fourth signal traces to the first and the second signal traces, respectively; and precharge circuitry coupled to the first signal trace, the second signal trace and the precharge clock trace independent of the evaluate circuitry to precharge the first and the second signal traces to the first voltage level independent of the evaluate circuitry.