Patent ID: 6841875

Claim:
A semiconductor device having a semiconductor substrate formed with a plurality of electrode pads, and wiring electrically connecting said electrode pads to external electrodes to be connected to conductive patterns formed on an external circuit board, said wiring formed as a plurality of layers, said semiconductor device comprising: insulating layers interposed between the layers of said wiring, and between a lowermost layer of said wiring and said semiconductor substrate, thereby to ensure insulation therebetween; each of said layers of said wiring having depressed portions located at via holes formed in said insulating layers, said depressed portions being connected to the lowermost layer of said wiring or said electrode pads, and having flat portions located on said insulating layers and serving as lateral conductors to other electrical connections on said insulating layers; bump electrodes formed on said depressed portions of an uppermost layer of said wiring; external electrodes formed on the top surfaces of said bump electrodes; and a sealing layer formed over said uppermost layer of said wiring so as to expose the top surface of said bump electrodes.