Patent ID: 7864832

Claim:
A reconfigurable multi-code correlation unit for correlating a sequence of chip samples, comprising: a memory for storing said sequence of chip samples; a plurality of add-subtract cells, wherein each of said add-subtract cells is capable of receiving a plurality of real bits, a, from a first chip sample in said memory and a plurality of imaginary bits, b, from said first chip sample, and wherein each of said add-subtract cells is capable of storing each real bit, a, and each imaginary bit, b, N times in an N-deep first input/first output (FIFO) data store, wherein N is determined by dividing a spreading factor by the number of add-subtract cells in the plurality of add-subtract cells; and a processing unit comprising: a plurality of sign select units, each of said plurality of sign select units capable of receiving from one of said plurality of add-subtract cells a plurality of first inputs equal to a sum (a+b) of said plurality of real bits, a, and said plurality of imaginary bits, b, and a plurality of second inputs equal to a difference (aâˆ’b) of said plurality of real bits, a, and said plurality of imaginary bits, b, and wherein said each sign select unit generates a plurality of real outputs and a plurality of imaginary outputs, wherein each of said real outputs and said imaginary outputs is equal to one of 1) said sum (a+b) multiplied by one of +1 and âˆ’1 and 2) said difference (aâˆ’b) multiplied by one of +1 and âˆ’1.