Patent ID: 8581630

Claim:
A memory system, comprising: a plurality of memory cells; a data path coupled to the array of memory cells, the data path operable to couple read data from the plurality of memory cells and to couple write data to the plurality of memory cells; a signal driver circuit coupled to the data path to drive an output signal on the data path having a logic level according to an input signal, the signal driver circuit comprising: a driver circuit configured to provide a first logic level signal having a first voltage or a second logic level signal having a second voltage according to the input signal; and a voltage controlled voltage supply coupled to the driver circuit and configured to provide the first voltage for the first logic level signal, the voltage controlled voltage supply configured to provide the first voltage having a magnitude according to a bias voltage, wherein the bias voltage comprises a voltage equal to the sum of a voltage representing a threshold voltage of a voltage controlled impedance circuit and the first voltage; and a bias voltage, generator coupled to the voltage controlled voltage supply and configured to provide the bias voltage to the voltage controlled voltage supply.