Patent ID: 7076719

Claim:
A bus system comprising: a slave interface provided between a slave unit and a bus, said slave interface being equipped with a retry set value storage circuit that stores a retry set value uniquely set for said slave unit and a pseudo-random number generator that generates a pseudo random number, and said slave interface transmitting, when negating a transmission request from a master unit, a non-acknowledgement response and non-acknowledgement response incidental information, said non-acknowledgement response incidental information including said retry set value and said random number generated by said pseudo-random number generator to the master unit via said bus; and a master interface provided between said master unit and said bus, said master interface including: a retry information extraction circuit that inputs said non-acknowledgement response incidental information from said bus and extracts and output said retry set value and said random number value, an adder that calculates a retry interval value by adding said retry set value and said random number value, a retry interval counting unit that begins counting clock pulses upon reception of said non-acknowledgement response and outputs a retry time notification signal upon detection that the counted value has reached said retry interval value, a retry count counting unit that begins counting the number of times said non-acknowledgement response is received once said transmission request is received from said master unit and outputs an overflow signal upon detection that the counted value has exceeded a preset permissible retry count, and a retry request circuit that activates resending of a transmission request upon detection that said overflow signal is inactive level and said retry time notification signal is active level.