Patent ID: 8769234

Claim:
An integrated-circuit memory device comprising: an input to receive memory-width configuration value; data terminals to exchange data with another device; a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; and a data control circuit coupling the physical banks with the data terminals, the data control circuit supporting first and second width configurations responsive to the configuration value; wherein: in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data terminals, and the plurality of physical banks collectively provide a first memory depth, and in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks per read operation and the data terminals, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operation in the first width configuration and loads a second page of sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page.