Patent ID: 8880927

Claim:
A time synchronization method for a multi-core system, comprising the following steps of: A, establishing at least one clock synchronization domain, and respectively allocating each core of the multi-core system to each clock synchronization domain; B, selecting a core with a lowest load in each clock synchronization domain as a master clock synchronization device in the clock synchronization domain, and other cores as slave clock synchronization devices in the clock synchronization domain; selecting the clock synchronization domain having the master clock synchronization device with a lowest load among various master clock synchronization devices as a master clock synchronization domain, while other clock synchronization domains being selected as slave cock synchronization domains; C, the master clock synchronization domain sending a synchronization deviation detection message to each slave clock synchronization domain, and calculating a time deviation value between each slave clock synchronization domain and the master clock synchronization domain; D, when the time deviation value is greater than a permitted deviation value, the master clock synchronization domain calculating a time adjustment quantity of each slave clock synchronization domain and releasing the time adjustment value to each slave clock synchronization domain, and each slave clock synchronization domain making adjustment based on the time adjustment quantity thereof, thereby completing clock synchronization; wherein, said step C further comprises the following steps of: C1, constructing the master clock synchronization domain and each slave clock synchronization domain into an annular synchronization network, and each slave clock synchronization domain registering at the master clock synchronization domain; C2, the master clock synchronization domain sending the synchronization deviation detection message, the synchronization deviation detection message flowing through each clock synchronization domain in a sequence of registering of each clock synchronization domain and then returning to the master clock synchronization domain, and each slave clock synchronization domain returning a relative time deviation thereof to the synchronization deviation detection message, wherein the relative time deviation refers to a time deviation of each slave clock synchronization domain relative to a last slave clock synchronization domain in a flow direction of the synchronization deviation detection message; C3, the master clock synchronization domain calculating a time deviation value between each slave clock synchronization domain and the master clock synchronization domain according to the returned synchronization deviation detection message.