Patent ID: 7382157

Claim:
An integrated circuit (IC), comprising: a plurality of logic circuits; and a plurality of self-resetting interconnect driver circuits coupled between the logic circuits, each self-resetting interconnect driver circuit comprising: a multiplexer circuit having a plurality of input terminals coupled to receive input signals from the logic circuits and further having an output terminal; and a buffer circuit having an input terminal coupled to the output terminal of the multiplexer circuit and further having an output terminal coupled to provide an output signal to one or more of the logic circuits, wherein in a first state the buffer circuit drives a first value onto the output terminal of the buffer circuit; wherein in a second state the buffer circuit first drives a second value onto the output terminal of the buffer circuit and then returns to the first state; and wherein the buffer circuit comprises: an input terminal coupled to the multiplexer output terminal; an output terminal; first and second internal nodes; a first pullup coupled to the input terminal of the buffer circuit and having a gate terminal coupled to the first internal node; a first inverter having an input terminal coupled to the input terminal of the buffer circuit and an output terminal coupled to the first internal node; a second pullup coupled between the first inverter and a power high, the second pullup having a gate terminal coupled to the second internal node; a pulldown coupled between the first internal node and a ground, the pulldown having a gate terminal coupled to the second internal node; a second inverter having an input terminal coupled to the first internal node and an output terminal coupled to the output terminal of the buffer circuit; and a reset circuit having an input terminal coupled to the output terminal of the second inverter and further having an output terminal coupled to the second internal node.