Patent ID: 7656183

Claim:
A method to extract gate to source/drain and overlap capacitances, comprising: providing a first test key and a second test key, wherein, the first test key comprises: at least a first gate formed on a semiconductor substrate, at least a first gate dielectric layer formed between the semiconductor substrate and the first gate, a first spacer formed on a sidewall of the first gate, a first doping region comprising a dopant of first type formed in the semiconductor substrate on a side of the first gate, at least a first contact formed on the first doping region, and a first metal layer formed on the first contact; and the second test key comprises: at least a second gate formed on the semiconductor substrate, at least a second gate dielectric layer formed between the semiconductor substrate and the second gate, a second spacer formed on a sidewall of the second gate, a second contact formed on the semiconductor substrate on a side of the second gate, wherein the semiconductor substrate under the second contact is doped with a dopant of second type, and a second metal layer formed on the second contact; measuring a first capacitance between the first gate and the first metal layer; measuring a second capacitance between the second gate and the second metal layer; and deducting the second capacitance from the first capacitance to obtain a resultant capacitance.