Patent ID: 7539897

Claim:
A fault tolerant system including a plurality of systems constituted by the same computer hardware components, each of the systems comprising: a processor section that can operate in a lock-step synchronous state between own system and other system; an input/output section to be connected to the processor section; a controller to be connected between the processor section and input/output section; and a signal transmission path that connects the own system and other system through the controller, the controller comprising: tag assignation means for assigning tag information to access data that are transmitted from the processor section to the input/output section, the tag information including: identifying information of the access source and destination; and synchronization information indicating whether the access data is synchronous access data that has been issued when the processor section is in a lock-step synchronous state; buffer means for separately retaining the access data of the own system and other system that are transmitted from the processor section; synchronization determination means for determining whether the access data is synchronous access data based on the tag information assigned to the access data in the buffer means; and processing means for outputting the access data from one of the plurality of systems to the input/output section and discarding the access data from other systems in the case where the access data is synchronous access data.