Patent ID: 7816219

Claim:
A semiconductor structure fabrication method, comprising: providing a semiconductor structure comprising: (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, wherein the channel region is disposed between and in direct physical contact with the first and second S/D extension regions, wherein the first S/D extension region is disposed between and in direct physical contact with the first S/D region and the channel region, and wherein the second S/D extension region is disposed between and in direct physical contact with the second S/D region and the channel region, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region; and forming (i) a first shallow contact region in direct physical contact with the first S/D extension region, and (ii) a first deep contact region in direct physical contact with the first S/D region and the first shallow contact region, wherein the first shallow contact region is physically isolated from the semiconductor layer by the first S/D region and the first S/D extension region, wherein the first shallow contact region is thinner than the first deep contact region in the reference direction, wherein the first shallow contact region comprises a first silicide material, wherein the first deep contact region comprises a second silicide material, wherein the first silicide material is different from the second silicide material.