Patent ID: 8650270

Claim:
A system comprising: one or more processors; and one or more memories including a plurality of instructions that, when executed by the one or more processors, cause the one or more processors to: group information regarding a plurality of components into a plurality of planes, based on one or more operations that are performed by the plurality of components, each of the plurality of components being implemented at least partially in hardware, one or more first particular components, of the plurality of components, performing a same operation being grouped with one or more second particular components, of the plurality of components, that perform the same operation and not being grouped with one or more third particular components, of the plurality of components, that do not perform the same operation, the plurality of components collectively performing functions of the system, the plurality of planes including: a system plane, a content plane, a session plane, an access plane, and a transfer plane, each of the plurality of planes being different from one another, components, of each of the plurality of planes, operating at a time scale that is temporally independent of a time scale of the components of other ones of the plurality of planes, the system plane, the content plane, and the session plane each being associated with one or more non-real-time operations, the access plane and the transfer plane each being associated with one or more real-time operations, the session plane bridging the non-real-time operations and the real-time operations, and the components, of each of the plurality of planes, having temporal requirements that are different from temporal requirements of the components of other ones of the plurality of planes.