Patent ID: 8325751

Claim:
A communication system comprising: at least one communication port amongst a plurality of ports to receive data to be processed via a plurality of operation stages; a hardware subsystem to perform a hardware operation associated with the received data; a software subsystem to perform a software operation associated with the received data; an operation determining logic to determine at least one of the operation stages to be performed by at least one of the hardware subsystem or the software subsystem, the operation determining logic configured to determine the operation stage to be performed based on a first, a second, and a third number of instructions per second (MIPs), or a first, a second, and a third number of gates or transistors or gates and transistors, or a first, a second, and a third number of number of MIPs per gates or MIPs per transistors or MIPS per gates and MIPS per transistors, or a first, a second, and a third number of instructions, or a first, a second, and a third amount of power consumption to perform the operation stage; and each of the plurality of ports having a clock rate amongst a plurality of clock rates respectively, wherein the communication system further includes an internal clock device for generating an internal clock, wherein the rate of the internal clock is faster than the rate of each of the clocks associated with the ports respectively.