Patent ID: 6989707

Claim:
A semiconductor circuit, comprising: at least one supply voltage generating fuse and at least one redundancy element activating fuse; and a read-out circuit including: a first read-out device coupled to and reading out the supply voltage generating fuse, said first read-out device starting the read out operation of the supply voltage generating fuse when a supply voltage has reached a first voltage value, said first read-out device including a first comparator and a first pulse shaper circuit, said first comparator generating a first start signal at a specific instant during an initialization phase of the semiconductor circuit, said first start signal being forwarded to said first pulse shaper circuit and to a first input of a logic AND gate; a second read-out device coupled to and reading out the redundancy element activating fuse, said second read-out device starting the read out operation of the redundancy element activating fuse when a supply voltage has reached a second voltage value, said second voltage value being higher than said first voltage value, said second read-out device including a second comparator and a second pulse shaper circuit, said second comparator generating a second start signal at a later instant during the initialization phase of the semiconductor circuit, said second start signal being forwarded to a second input of said logic AND gate, said logic AND gate forwarding a third start signal to said second pulse shaper circuit when said first and second start signals are present; and said second read-out device subsequently reading out the redundancy element activating fuse in a manner time-shifted with respect to the supply voltage generating fuse.