Patent ID: 8473667

Claim:
An method for maintaining cache coherency on a network on chip (‘NOC’) with invalidation messages, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising: sending, from an invalidating module to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory; responsive to receiving the invalidation message, invalidating, by the selected IP blocks, the contents of the cached memory; determining, by each of the selected IP blocks in dependence upon information in the invalidation message, whether to forward the invalidation message; and if the message is to be forwarded, forwarding the invalidation message.