Patent ID: 7233523

Claim:
A nonvolatile semiconductor storage device in which a plurality of threshold voltage levels are set to store data of two or more bits in each of a plurality of memory cells, comprising: a plurality of memory banks, each of which is comprised of a memory array of said memory cells; and for each said memory bank: a respective sense latch arranged along one longer side of said memory bank to hold information sensed from memory cells being subjected to writing; a respective first arithmetic circuit arranged along one shorter side of said memory bank to determine a threshold voltage level to be written to first memory cells of said memory bank by performing multilevel arithmetic operations on data to be written to the first memory cells; a respective second arithmetic circuit arranged along an other shorter side of said memory bank to determine a threshold voltage level to be written to second memory cells of said memory bank by performing multilevel arithmetic operations on data to be written to the second memory cells; a respective first buffer arranged along said shorter side of said memory bank to store the data to be written to the first memory cells; and a respective second buffer arranged along the other shorter side of said memory bank to store the data to be written to the second memory cells.