Patent ID: 7074667

Claim:
A method of manufacturing a semiconductor memory device comprising: forming an interlayer insulation layer on a semiconductor substrate, the semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer on the interlayer insulation layer; forming storage node contact plugs in the memory cell array area, the storage node contact plugs arranged non-linearly in at least one direction, the storage node contact plugs passing through the first etch stop layer and the interlayer insulation layer; forming a first conductive layer on the first etch stop layer in the memory cell array area and in the core/perimeter area; forming a second etch stop layer on the first conductive layer; etching the second etch stop layer to form a second etch stop layer pattern that is arranged non-linearly in at least one direction in the memory cell array area; etching the first conductive layer using the second etch stop layer pattern as an etch mask to form landing pads that are electrically connected with the storage node contact plugs and to form resistors in the core/perimeter area; and forming storage nodes on the such that an entire outer surface of the storage nodes is exposed.