Patent ID: 8030740

Claim:
A microelectronic structure comprising a layerstack, the layerstack comprising: a first layer comprising semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration; a second layer comprising semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer comprises heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant concentration, the second-layer after-anneal dopant concentration exceeding the second-layer before-anneal concentration; a third layer comprising semiconductor material that is above and in contact with the second layer and that is not heavily n-doped before or after being annealed, the third layer having a third-layer dopant concentration; and a fourth layer comprising a semiconductor material that is above and in contact with the third layer; wherein: the first, second, and third layers are portions of a vertically oriented junction diode; the diode is a p-i-n diode, the third layer is undoped or lightly doped, and the third layer comprises germanium; and the fourth layer comprises silicon, the fourth layer is heavily p-doped, and the fourth layer is a portion of the vertically oriented junction diode.