Patent ID: 8073002

Claim:
A method, comprising: identifying a data structure involving at least one bit of a first register capable of being used to determine whether a hardware network interface is operating in a first mode where packets are processed utilizing a processor, or in a second mode where the packets are processed utilizing the hardware network interface; writing the packets to a socket receive buffer; determining, based on the at least one bit of the first register, whether the hardware network interface is operating in the first mode or the second mode, the hardware network interface coupled between a network and the processor; if it is determined that the hardware network interface is operating in the second mode, processing the packets utilizing the hardware network interface, the processing of the packets utilizing the hardware network interface including the hardware network interface reading the packets from the socket receive buffer, the hardware network interface copying the read packets to a temporary buffer in a memory space of the hardware network interface, and the processor reading the packets from the temporary buffer in the memory s ace of the hardware network interface; and if it is determined that the hardware network interface is operating in the first mode; writing a memory address to a second register utilizing the hardware network interface, the memory address being that which the processor is attempting to access for reading from the memory address, when the processor attempts to access the memory address for reading from the memory address, sending information to the processor from the hardware network interface, the information indicating an amount of the packets to be read, granting permission to the processor to use the first mode, and processing the packets utilizing the processor, the processing of the packets utilizing the processor including the processor reading the packets directly from the socket receive buffer at the memory address in the second register and avoiding use of the temporary buffer in the memory space of the hardware network interface for reading by the processor.