Patent ID: 7463321

Claim:
A thin film transistor array panel comprising: a first insulating substrate; a plurality of gate lines formed on the first insulting substrate; a gate insulating layer covering the gate line; a plurality of data lines formed on the gate insulating layer and intersecting the gate lines to define first to third pixel areas; a plurality of thin film transistors electrically connected to the gate lines and the data lines; a protective layer covering the thin film transistors and the data lines and having a plurality of contact holes exposing a plurality of drain electrodes of the thin film transistors; and a plurality of pixel electrodes connected to the drain electrodes through the contact holes, wherein the protective layer and the gate insulating layer have openings in the first and the second pixel areas, but not in the third pixel area, the openings overlapping the pixel electrodes and the openings in the protective layer and the gate insulating layer have saw-toothed edges.