Patent ID: 7567425

Claim:
A multilayer chip capacitor comprising: a capacitor body having a plurality of dielectric layers laminated therein, the capacitor body comprising first and second capacitor units having capacitances different from each other; and first to fourth outer electrodes formed on an outer surface of the capacitor body, wherein the first capacitor unit comprises at least one pair of first and second inner electrodes opposing each other while interposing a corresponding one of the dielectric layers, the first and second inner electrodes connected to the first and second outer electrodes, respectively to have polarities different from each other, the second capacitor unit comprises at least one pair of third and fourth inner electrodes opposing each other while interposing another corresponding one of the dielectric layers, the third and fourth inner electrodes connected to the third and fourth outer electrodes, respectively to have polarity identical to the first and second inner electrodes, an alternate laminated portion is formed in one area within the capacitor body, the alternate laminated portion having the first to fourth inner electrodes sequentially laminated therein, and a capacitance adjusting portion is formed in another area within the capacitor body, the capacitance adjusting portion having at least one of the one pair of first and second inner electrodes and the one pair of third and fourth inner electrodes laminated repeatedly.