Patent ID: 7265421

Claim:
A semiconductor thin film Gated-FET device, comprising: a semiconductor thin film layer positioned on a first insulator, said first insulator adequately thick to minimize or eliminate any influence of voltages from below; and a channel region formed in a fairly uniformly doped portion of said semiconductor thin film layer, the thickness of the channel comprising the entire thin film thickness; and a gate terminal coupled to a single gate region formed above said channel region, said gate region formed on a gate material deposited over a gate insulator layer, said gate insulator layer further deposited over the semiconductor thin film layer; wherein: a first voltage level at the gate fully depletes all of the majority carriers from the entire thin film layer in said channel region to create a non-conductive channel; and a second voltage level at the gate accumulates the majority carriers near the gate surface of the thin film layer in said channel region to create a conductive channel.