Patent ID: 7600221

Claim:
A trace processor configured to support parallel execution of multiple instructions, the trace processor comprising: a trace detector that identifies traces in a segment of code including successive instructions, each of multiple identified traces in the segment of code including a set of instructions capable of being executed on an execution unit; a dependency detector that, prior to parallel execution of multiple identified traces on corresponding execution units, analyzes the traces identified in the segment of code to determine a dependency order for executing the traces, the dependency order identifying at least one of the traces associated with the segment of code that cannot be property executed in parallel with another trace in the segment of code; a trace scheduler coupled to the dependency detector and the trace detector, the trace scheduler receiving a set of traces and, based on the dependency order, causing the corresponding execution units to execute traces within the set of traces in parallel, the execution taking place in an execution order that is based on the identified dependency order, at least two traces being executed in parallel and if the dependency order indicates that a second trace is dependent upon a first trace, the first trace being executed prior to the second trace; multiple execution units to execute multiple traces in parallel based on the dependency order; a buffer to temporarily store results associated with execution of multiple executed traces; and a comparator circuit that, at run time of executing the multiple traces in parallel, identifies an out-of-order memory dependency condition associated with parallel executed traces resulting in an error; and the comparator circuit, in response to identifying the out-of-order memory dependency condition: squashes execution of latter traces in the segment of code that depend on results from earlier traces; and clears results in the temporary buffer associated with the squashed traces.