Patent ID: 7479426

Claim:
A method of manufacturing a non-volatile memory cell, the method comprising: providing a substrate, the substrate comprising a first region and a second region; forming a plurality of isolation structures on the substrate, the isolation structures comprising a first isolation structure positioned in the first region and a second isolation structure surrounding the second region; forming a control gate on the first isolation structure in the first region; forming a first insulating layer on the control gate; forming a second insulating layer on the portion of the substrate in the second region; and forming a floating gate on the first insulating layer and the second insulating layer comprising forming a doped polysilicon layer on the substrate, removing a portion of the doped polysilicon layer, and remaining a portion of the doped polysilicon layer on the first insulating layer and the second insulating layer to be the floating gate, wherein an opening is formed above the first insulating layer after removing the portion of doped polysilicon layer, the opening being used to form a wire therein to connect to the control gate.