Patent ID: 8643113

Claim:
An integrated circuit, comprising: a substrate; a PMOS transistor, said PMOS transistor further including: a PMOS gate dielectric layer formed on a top surface of said substrate; a PMOS gate work function metal layer formed on a top surface of said PMOS gate dielectric layer, wherein said PMOS gate work function metal layer includes oxygen such that an effective work function of said PMOS gate work function metal layer is above 4.85 eV; a PMOS metal fill gate formed over and in electrical connection with said PMOS gate work function metal layer; a PMOS etch stop layer between the PMOS gate work function metal layer and the PMOS metal fill gate; and an oxygen diffusion barrier between the PMOS gate work function metal layer and the PMOS metal fill gate; and an NMOS transistor, said NMOS transistor further including: an NMOS gate dielectric layer formed on a top surface of said substrate; an NMOS gate work function metal layer formed on a top surface of said NMOS gate dielectric layer, wherein said NMOS gate work function metal layer includes additional metal atoms relative to said PMOS gate work function metal layer such that an effective work function of said NMOS gate work function metal layer is below 4.25 eV; an NMOS metal fill gate formed over and in electrical connection with said NMOS gate work function metal layer, the NMOS transistor not including the oxygen diffusion barrier; and an NMOS etch stop layer between the NMOS gate work function layer and the NMOS metal fill gate.