Patent ID: 7308553

Claim:
A processor device capable of cross-boundary alignment of plural register data, comprising: a decoder, which decodes a multiple shift instruction; a register unit consisting of a plurality of N-bit registers, which inputs external data through its input terminal to one of the N-bit registers in accordance with a third address, reads register contents in accordance with a first address and a second address respectively, and outputs the register contents read through a first and a second output terminals of the register unit, where N is a positive integer; a shifter connected to the first and the second output terminals of the register unit, which combines the register contents outputted by the first and the second output terminals of the register unit to form a 2N-bit word and shifts the 2N-bit word by w (positive integer) bits, thereby extracting first N bits from the shifted word as the external data to output; and a controller coupled between the decoder and the register unit, which sets the first address, the second address, the third address and the w value in accordance with the decoded multiple shift instruction, to accordingly output the register contents read by the register unit to the shifter for shifting w bits and write the external data as an output of the shifter to the register unit.