Patent ID: 7809894

Claim:
A computer program product for executing a machine instruction in a central processing unit, the computer program product comprising: a storage medium readable by a processor and storing instructions for execution by the processor for performing a method comprising: fetching a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising an opcode field, a first field comprising a first base field (B 1 ) for identifying a first register and a first displacement field (D 1 ) the content of which is added to the content of the first register to form the address of a first operand in a storage, a second field comprising a second base field (B 2 ) for identifying a second register and a second displacement field (D 2 ) the content of which is added to the content of the second register to form the address of a second operand in the storage, and a third field for identifying a third register (R 3 ) containing a third operand; executing said fetched machine instruction, the execution comprising: 1) determining the address of the first operand in the storage; 2) fetching the first operand from the storage using an interlocked update reference that prevents other central processing units from making interfering accesses to the first operand in the storage until an interlocked update release is performed; 3) fetching the third operand contained in the third register; 4) comparing the first operand with the third operand; 5) responsive to the comparing the first operand with the third operand, if the first operand is equal to the third operand performing a) through c) comprising: a) storing a replacement value at the address of the first operand; b) performing an interlock-update-release thereby permitting other central processing units to access the first operand in the storage; c) storing a retrieved store value at the address of the second operand; and 6) responsive to the comparing the first operand with the third operand, if the first operand is not equal to the third operand, performing d) through e) comprising: d) storing the first operand in the third register; and e) performing an interlock-update-release thereby permitting other central processing units to access the first operand in the storage; wherein the machine instruction can be intermixed with a compare and swap instruction that utilizes an interlocked update operation.