Patent ID: 8441296

Claim:
A timing generator that outputs a timing signal, comprising: a logic section operable to receive a reference clock and output, in synchronization with the reference clock, setting data indicating one or more delay amounts and a plurality of rate signals; a first period delay section and a second period delay section each operable to receive setting data and a rate signal from among the setting data and the plurality of rate signals output by the logic section, output a delayed rate signal obtained by delaying the received rate signal by a delay amount, from among the one or more delay amounts indicated by the received setting data, corresponding to an integer multiple of a period of an operation clock supplied thereto, and output the setting data in synchronization with the delayed rate signal; a first high-accuracy delay section operable to delay a signal input thereto by a delay amount, indicated by the setting data, that is less than the period of the operation clock and output the resulting delayed signal as the timing signal; and a mode switching section operable to switch between a low-speed mode, in which the delayed rate signal output by the first period delay section is input to the first high-accuracy delay section as the signal input thereto, and a high-speed mode, in which a signal obtained by interleaving the delayed rate signal output by the first period delay section and the delayed rate signal output by the second period delay section is input to the first high-accuracy delay section as the signal input thereto.