Patent ID: 8344426

Claim:
A semiconductor device, comprising: a plurality of first cells having a first cell height, and a plurality of second cells having a second cell height, wherein the first cells and the second cells are formed on the same semiconductor substrate, each of the first cells has a first element isolation region formed so as to define a first element formation region in the semiconductor substrate, a first MIS transistor of a first conductivity type including, over the semiconductor substrate, a first gate electrode that is formed so as to extend across the first element formation region in a direction of the first cell height, and a first source region and a first drain region of the first conductivity type that are formed in regions extending laterally below the first gate electrode in the first element formation region, and a substrate contact region of a second conductivity type formed in the direction of the first cell height so as to face the first element formation region with the first element isolation region interposed therebetween, the second conductivity type is opposite in polarity to the first conductivity type, each of the second cells has a second element isolation region formed so as to define a second element formation region in the semiconductor substrate, a second MIS transistor of the first conductivity type including, over the semiconductor substrate, a second gate electrode that is formed so as to extend across the second element formation region in a direction of the second cell height, and a second source region and a second drain region of the first conductivity type that are formed in regions extending laterally below the second gate electrode in the second element formation region, a power supply region of the first conductivity type formed in the direction of the second cell height so as to face the second element formation region with the second element isolation region interposed therebetween, and a first extended region of the first conductivity type silicidated at a surface thereof, and provided between the power supply region of the first conductivity type and the second source region and interposed between portions of the second element isolation region, so as to connect the power supply region of the first conductivity type to the second source region, and the first cell height is greater than the second cell height.