Patent ID: 8054697

Claim:
A semiconductor storage device comprising: a memory cell array in which a plurality of memory cells storing data are arranged; a plurality of word lines that selectively drive one of the memory cells in the memory cell array; a plurality of pairs of bit lines that transmit/receive data to/from the memory cell that is selected; a precharge circuit that precharges a bit line pair to about half of a power supply potential by equalizing potential of the bit line pair; a sense amplifier that is provided in accordance with each of the bit line pairs; and a level shift unit that shifts level of potential of the bit lines when the sense amplifier starts to read potential of the bit line pair, wherein the level shift unit comprises: level shifting capacitors, each of which having one electrode connected to each bit line, and forming one pair by two level shifting capacitors for each bit line pair; and a timing generator that is connected to each of the other electrodes of the level shifting capacitors in common, supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.