Patent ID: 6999360

Claim:
A method for controlling a shift redundancy circuit that selectively connects a plurality of selection lines and at least one redundancy selection line, each of which commonly shares a plurality of memory blocks, to a plurality of decode selection lines, and remedies a deficiency relating to each of the plurality of selection lines for each memory block, the method comprising the steps of: decoding a deficiency address indicating a deficient location to generate a decode signal; generating a shift signal for determining the plurality of decode selection lines to be selectively connected to the plurality of selection lines and the at least one redundancy selection line based on the decode signal for each memory block having a deficiency to be remedied; selecting a shift signal corresponding to a selected memory block having a deficiency to be remedied based on a memory block selection signal; and selectively connecting the plurality of decode selection lines to the plurality of selection lines and the at least one redundancy selection line based on the selected shift signal.