Patent ID: 7183949

Claim:
An analog baseband processor for use in a communication device, the analog baseband processor comprising: an analog-to-digital converter configured to alternately sample a first mode input signal to output a first digital signal at a first sampling rate, and to sample a second mode input signal to output a second digital signal at the first sampling rate, wherein the first mode input signal has a first symbol frequency (FS 1 ), and the second mode input signal has a second symbol frequency (FS 2 ); a first decimator configured to reduce the first sampling rate of the first digital signal with a conversion factor of R 1 , R 1 being an integer; a first sample rate converter configured to convert the reduced sampling rate of an output signal of the first decimator with a conversion factor of M 1 /L 1 , M 1 and L 1 being integers; a second decimator configured to reduce the first sampling rate of the second digital signal with a conversion factor of R 2 , R 2 being an integer; and a second sample rate converter configured to convert the sampling rate of an output signal of the second decimator with a conversion factor of M 2 /L 2 , M 2 and L 2 being integers; wherein the first sampling rate×M 1 /(R 1 ×L 1 ) equals the first symbol frequency (FS 1 ) of the first mode input signal times a first oversampling factor; wherein the first symbol frequency (FS 1 ) of the first mode input signal conforming to a GSM/EDGE standard times a first oversampling factor, equals about 1.625/N 1 Msps (Mega samples per second), wherein N 1 is an integer greater than one; wherein the first sampling rate×M 2 /(L 2 ×R 2 ) equals the second symbol frequency (FS 2 ) of the second mode input signal times a second oversampling factor; and wherein the second symbol frequency (FS 2 ) in conformity to a W-CDMA standard times the second oversampling factor equals about 3.84×N 2 Msps (Mega samples per second).