Patent ID: 8138836

Claim:
An emitter-follower bias circuit supplying a bias voltage to a base of an amplification transistor, the emitter-follower bias circuit comprising: a depletion mode FET boosting a reference voltage; an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET; and first and second resistors having different resistance values, wherein the reference voltage includes complementary first and second reference voltages, the depletion mode FET includes a first depletion mode FET boosting the first reference voltage, and a second depletion mode FET boosting the second reference voltage, the first reference voltage boosted by the first depletion mode FET is input to the emitter-follower circuit via the first resistor, and the second reference voltage boosted by the second depletion mode FET is input to the emitter-follower circuit via the second resistor.