Patent ID: 8558313

Claim:
An integrated circuit comprising: a semiconductor wafer comprising a semiconductor on insulator (SOI) device region including a semiconductor substrate, a first SOI semiconductor layer over the semiconductor substrate, and a buried insulating layer formed between the semiconductor substrate and the first SOI semiconductor layer, and said semiconductor wafer comprising a bulk device region; an SOI field effect transistor (FET) formed in said SOI device region comprising: an SOI gate stack comprising an SOI gate dielectric atop said first SOI semiconductor layer and an SOI gate conductor atop said SOI gate dielectric; and SOI source/drain regions in said first SOI semiconductor layer adjacent said SOI gate stack; a bulk FET formed in said bulk device region comprising: a bulk gate stack comprising a bulk gate dielectric over said semiconductor substrate and a bulk gate conductor atop said bulk gate dielectric, wherein said bulk gate dielectric has a top surface that is substantially coplanar with a top surface of said buried insulating layer in said SOI device region; and bulk source/drain regions in said semiconductor substrate adjacent said bulk gate stack.