Patent ID: 8713294

Claim:
A method for memory access checking on a processor in a computer system including a data storage device having a memory device, the memory device including a first level cache memory (level-1 cache), the computer system including a program stored in the data storage device and steps of the program being executed by a processor, said method comprising: invalidating memory ranges within a first level cache memory in the memory device, the invalidated first level cache memory ranges in the memory device corresponding to a guard page, and said guard page being moved subject to a top of heap size change, the invalidating of memory ranges being executed by an operating system; configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers; selecting one of the plurality of WAC registers using the operating system; setting up the selected WAC register related to the invalidated memory ranges corresponding to said guard page using the operating system; configuring a wakeup unit to interrupt on access of the selected WAC register using the operating system; detecting access of the memory device between said level-1 cache and a second level cache memory using the wakeup unit when a guard page is violated; generating an interrupt to the core using the wakeup unit; querying the wakeup unit using the operating system when the interrupt is generated to determine the source of the interrupt; detecting the activated WAC registers assigned to the violated guard page; and initiating a response using the operating system after detecting the activated WAC registers.