Patent ID: 7351666

Claim:
A method for fabricating integrated circuits, comprising: forming a first mandrel mask pattern including a first structure and a second structure, each structure having a line portion and a flag portion, wherein the first and second structures are arranged on a first layer such that the line portions are adjacent and run parallel to each other and the flag portions of the first and second structures are oppositely disposed and overlap an end of the line portion of the other structure; transferring the first mandrel mask pattern to the first layer; forming first spacers on the first mandrel pattern and removing the first mandrel pattern from between the first spacers; transferring a pattern formed by the first spacers to a second layer to form a second mandrel pattern; forming second spacers on the second mandrel pattern and removing the second mandrel pattern from between the second spacers; and transferring a pattern formed by the second spacers to a third layer to form sub-lithographic conductive lines and contact landing segments in that third layer.