Patent ID: 7439081

Claim:
A method of making an integrated circuit chip, comprising the steps of: providing a relatively broad, flat chip substrate having a planar orientation; forming a plurality of active devices on said substrate; forming at least one dielectric layer over said substrate and said active devices, said dielectric layer containing a plurality of electrically conductive vias for making electrical connections to said active devices; forming a conductive layer over said at least one dielectric layer, said conductive layer being substantially parallel to said planar orientation of said chip substrate, said step of forming a conductive layer comprising: (a) forming a first sublayer of carbon nanotubes oriented in a first direction substantially parallel to said planar orientation of said chip substrate; and (b) forming a second sublayer of carbon nanotubes oriented in a second direction substantially parallel to said planar orientation of said chip substrate, said first direction and said second direction forming a non-zero angle.