Patent ID: 7248500

Claim:
A nonvolatile semiconductor memory device, comprising: a memory array having a plurality of nonvolatile memory cells, arranged in rows and columns, each storing information in a nonvolatile manner; at least one row of a plurality of dummy cells, arranged at an end side of said memory array in a row direction in alignment with the memory cells, each for storing fixed data; a plurality of bit lines disposed corresponding to the respective columns of the memory cells so as to be provided on both sides of each column of the memory cells; a plurality of word lines disposed corresponding to the rows of the memory cells; at least one dummy word line disposed corresponding to said at least one row of the dummy cells; row selection circuitry for selecting a word line from said plurality of word lines corresponding to an addressed row in response to an address signal and selecting a dummy word in said at least one dummy word line in data reading, selected memory and dummy cells on a same column sharing a first bit line; and column selection/voltage supply circuitry for supplying a read voltage to a second bit line to which a memory cell on a column addressed according to an address signal is connected, and supplying voltages the same in voltage level to the first bit line and to a third bit line to which the dummy cell is connected in the data reading, the first bit line being supplied with the voltage from a side opposite to a side supplying the voltage to the third bit line with respect to the memory array.