Patent ID: 7486126

Claim:
A semiconductor integrated circuit comprising: a clock generator; a clock wiring which propagates a clock signal outputted from the clock generator to ends thereof via a plurality of branches; a plurality of sequence circuits connected to the ends of the clock wiring, said plurality of sequence circuits including at least level sense sequence circuits; and a pulse generator to vary a timing to change the clock signal, which defines an endpoint of an input operating period of each said level sense sequence circuit, said pulse generator being coupled to the clock wiring, wherein said pulse generator includes: a first pulse generation section to generate a first pulse signal synchronized with a rising edge of the clock signal; a second pulse generation section to generate a second pulse signal synchronized with a falling edge of the clock signal; and a logic circuit which combines the first pulse signal and the second pulse signal together and outputs the result of combination, wherein the first pulse generation section includes a first variable delay circuit to adjust a pulse width of the first pulse signal, wherein the second pulse generation section includes a second variable delay circuit to adjust a pulse width of the second pulse signal, and wherein the second pulse generation section further includes a third variable delay circuit to adjust the amount of delay of the second pulse signal.