Patent ID: 7310756

Claim:
An electrical circuit, comprising: A. a test bus of test signals; B. a target circuit; and C. a test interface coupled between the test bus and the target circuit, the test interface including: i. a select signal lead; ii. an enable signal lead; iii. first state machine circuitry coupled to the test signals, having an enable signal input connected to the enable signal lead, and having first state output signals indicating a sequence of states in response to changes in the enable input and the test signals, the first state output signals enabling a select signal on the select signal lead; and iv. second state machine circuitry coupled to the test signals, having a select signal input coupled to the select signal lead, and having second state output signals indicating a sequence of states in response to changes in the select input and the test signals, the second state output signals enabling an enable signal on the enable signal lead.