Patent ID: 8640004

Claim:
A method comprising: receiving at least one data sample over a predetermined number of clock cycles; writing the received at least one data sample to a memory comprising one or more memory slots during the last clock cycle of each predetermined number of clock cycles such that first parts of a predetermined one or more memory slots are filled in an ascending order of addresses and, after the predetermined one or more memory slots are filled in respect of the first part, second parts of the predetermined one or more memory slots are filled in a descending order of addresses, wherein a part of a memory slot stores the at least one data sample received over the predetermined number of clock cycles; reading the written data samples from the predetermined one or more memory slots in a descending order of addresses once the first part and the second part of at least one memory slot are written, wherein the reading takes place during the clock cycles when data is not being written to the memory; and forwarding the read data samples from the predetermined one or more memory slots.