Patent ID: 7920435

Claim:
A semiconductor memory device, comprising: a plurality of memory cells connected to a bit line; and a sense amplifier of current sense type including an initial charging circuit capable of initially charging said bit line with a suppressed value of current only for a certain starting period during an initial charging period, said sense amplifier operative to detect a value of current flowing in said bit line to decide data read out of each of said memory cells, said initial charging circuit including: a current control circuit connected to a power source and operative to provide a restricted current, a first transistor connected to the output terminal of said current control circuit and operative to supply the current output from said current control circuit to said bit line only for the certain starting period during the initial charging period of charging said bit line, and a second transistor connected to said power source and operative to supply current to said bit line for a period subsequent to the certain starting period during the initial charging period of charging said bit line.