Patent ID: 8134206

Claim:
A semiconductor device comprising at least a surface isolation region between two surface high-voltage devices implemented on the surface of a lightly doped substrate of a first conductivity type, the potential of a neutral region of said substrate under an externally applied reverse biasing voltage being taken as reference, each of said surface devices consisting of at least a surface region of semiconductor of a second conductivity type having the largest voltage and another surface region of semiconductor of the first conductivity type having the smallest voltage, wherein a surface region between said region having the largest voltage and said region having the smallest voltage is a surface voltage-sustaining region, where the bottom of said voltage-sustaining region is a semiconductor region of said second conductivity type; each said surface voltage-sustaining region of both surface high-voltage devices is fully depleted under a maximum reverse voltage applied to said largest voltage region and smallest voltage region and said surface high-voltage device then emits an effective electric flux density of second conductivity type to said substrate; said surface voltage-sustaining region has a thickness, said thickness being smaller than the depletion thickness of a one-sided abrupt parallel plane junction made by said substrate under its breakdown voltage; wherein the potential difference between both largest voltage regions of said two devices and the potential difference between both smallest voltage regions of said two devices are much smaller than said maximum reverse voltages applied to said largest voltage region and smallest voltage region of both devices; said two surface high-voltage devices are implemented separately in two surface areas, and a surface isolation region is between said two areas, wherein the directions from said largest voltage region to smallest voltage region of both devices and of said surface isolation region are identical; said isolation region has two widths perpendicular to each other and perpendicular to said direction, said widths being smaller than the depletion width of a one-sided abrupt parallel plane junction made by said substrate under its breakdown voltage; said isolation region has at least two semiconductor layers of second conductivity type, one being contacted to one of said surface devices and another being contacted to another of said surface devices, wherein when the semiconductor region(s) of the isolation region is fully depleted, its effective flux density of second conductivity type emitted to the substrate is of a value between the values of its adjacent surface voltage-sustaining regions of said two surface semiconductor devices; said effective electric flux density of said second conductivity type is produced by the amount of ionized impurities in a surface area divided by the area; said largest voltage is positive when said first conductivity type is a p-type, or negative when said first conductivity type is n-type.