Patent ID: 8298877

Claim:
A method for manufacturing an array substrate, the method comprising: sequentially disposing a first metal layer and a second metal layer on a base substrate on which a gate line, a gate electrode and a channel layer are disposed; sequentially etching the second metal layer and the first metal layer to form a metal line pattern, the metal line pattern including a first line pattern, a second line pattern and a first electrode pattern, the first electrode pattern including a first element pattern and a second element pattern; partially etching the second element pattern to form a second electrode pattern, the second electrode pattern comprising the first element pattern and a partially etched second element pattern; partially etching the second line pattern to form a data line, the data line comprising the first line pattern and a partially etched second line pattern; converting an oxide layer to a fluoride layer by contacting the oxide layer with a reactive gas, the reactive gas comprising a fluoride containing compound, the oxide layer being naturally formed on the first element pattern when forming the second electrode pattern; etching the fluoride layer and an exposed portion of the first element pattern to form a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode; and disposing a pixel electrode to electrically contact the drain electrode.