Patent ID: 7814387

Claim:
A circuit state scan-chain provided in a design being tested, said design comprising: a plurality of registers, and input terminal combinational logic and output terminal combinational logic respectively corresponding to each register, an output port of each register connecting with an input port of a corresponding output terminal combinational logic, wherein said circuit state scan-chain further comprises a plurality of first multiplex modules and a plurality of second multiplex modules respectively in correspondence with said plurality of registers, wherein each register is associated with a corresponding one of the plurality of first multiplex modules and a corresponding one of the plurality of second multiplex modules, each of the first multiplex modules and the second multiplex modules having two input ports and one output port, and wherein a first input port of each of the first multiplex modules connects with the output port of a corresponding register, and a second input port of each of the first multiplex modules connects with the output port of an immediately previous register, a first input port of each of the second multiplex modules connects with the output port of the input terminal combinational logic of a corresponding register, a second input port of each of the second multiplex modules connects with the output port of a corresponding one of the first multiplex modules, and the output port of each of the second multiplex modules connects with the input port of a corresponding register, and the output port of the last register of the scan-chain connects with the second input port of the first multiplex modules corresponding to the first register of the scan-chain.