Patent ID: 8223171

Claim:
An image processing apparatus, comprising: a combining unit configured to combine each of plural subframes of original image data, each divided from one frame, with a corresponding one of plural subframes of OSD image data; a storage unit configured to store plural subframes of the OSD image data, each of the plural subframes being divided in a same manner as the original image data are divided; a load storage unit configured to load and store the plural subframes of the OSD image data stored in the storage unit; a reading unit configured to read out in parallel the plural subframes of the OSD image data stored in the storage unit; and a controlling unit configured to control loading of the plural subframes of the OSD image data read out in parallel from the storage unit so as to write the OSD image data in parallel in the load storage unit and to read out in parallel the OSD image data from the load storage unit so as to transmit the OSD image data to the combining unit, wherein the storage capacity per address in the storage unit is equal to or larger than double the data length of one pixel, and accordingly, two or more subframes of the image data are stored according to a prescribed sequence at a single address of the storage unit, and the reading unit is configured to read out the OSD image data in parallel with respect to each address from the storage unit.