Patent ID: 8824236

Claim:
A memory access control device comprising: a logical address receiving unit configured to receive a logical address specifying a range in a storage area of an external memory; a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length; and an output unit configured to generate a second bit sequence composed of bits that are equal in number to the bits stored in the range specified by the logical address, by using the one or more bit sequences extracted by the bit sequence extracting unit and output the generated second bit sequence.