Patent ID: 7548103

Claim:
A device, comprising: a power control module comprising a control input to receive a mode control signal and an output, the power control module configured to provide a first voltage reference at the output in response to the mode control signal being in a first state and to provide a second voltage reference at the output in response to the mode control signal being in a second state; a clock control module comprising a control input to receive the mode control signal, a first clock input, and a first output, the first output configured to provide a clock signal when the mode control signal is in the first state and configured to provide a constant signal level at the first output in response to the mode control signal being in the second state; and a first latch comprising: a first pass gate comprising a first control input coupled to the first output of the clock control module and a first output; and a first storage element comprising a first data input coupled to the first output of the first pass gate, a first clock input coupled to the first output of the clock control module, and a power input coupled to the output of the power control module.