Patent ID: 7411855

Claim:
A semiconductor device comprising: a first memory array adapted to be selected by a first control signal and including a plurality of first memory cells and a plurality of first sense amplifiers; a second memory array adapted to be selected by a second control signal which is different from said first control signal and including a plurality of second memory cells and a plurality of second sense amplifiers; a power supply line provided in a mesh manner above said first and second memory arrays; a first power supply circuit having a first output node connected to said power supply line, and adapted to receive a first voltage and to generate a second voltage; and a second power supply circuit having a second output node connected to said power supply line, and adapted to receive said first voltage and to generate said second voltage; wherein, during a first period in which said first memory array is selected, said first power supply circuit is adapted to output said second voltage from said first output node, and wherein, during a second period in which the second memory array is selected after said first memory array is selected, said first power supply circuit is adapted not to output said second voltage to said first output node.