Patent ID: 8461639

Claim:
A nonvolatile memory device comprising: a plurality of cell gate patterns and plurality of inter-gate insulating patterns stacked alternately on a substrate; an upper selection gate pattern disposed on an uppermost of the inter-gate insulating patterns; a lower selection gate pattern between a lowermost of the inter-gate insulating patterns and the substrate; an active pattern extending upward along sidewalls of the lower selection gate pattern, the cell gate patterns, and the upper selection gate pattern on the substrate; a data storage pattern between the lower selection gate pattern, the cell gate patterns, and the upper selection gate pattern and the active pattern; an upper dopant region disposed at an upper portion of the active pattern and having a lower surface at a level higher than a top surface of the upper selection gate pattern; a lower dopant region disposed at a lower portion of the active pattern and having an upper surface located at a level lower than a bottom surface of the lower selection gate pattern; and a semiconductor region that is more lightly doped than the lower dopant region and is on the lower dopant region, the semiconductor region comprising a bottom surface that is below the bottom surface of the lower selection gate pattern.