Patent ID: 8026599

Claim:
A Wafer Level Chip Scale Package (WLCSP) comprising: a substrate comprising: an active face; a non-active face opposing the active face; an active silicon area between the active face and the non-active face, wherein contacts to the active silicon area are provided on the active face; and a plurality of sides between the active face and the non-active face, wherein at least one side comprises a step, wherein the step extends along a vertical axis from the non-active face towards the active face to a depth that does not reach a level of the active silicon area, and wherein at least a portion of the step extends over the active silicon area along a horizontal axis; a side coating of an encapsulant provided in the step, wherein an outer wall of the side coating is defined by a singulation cut that separates the active silicon area from a wafer; and a layer of the encapsulant covering the non-active face, wherein the layer and the side coating protect at least a portion of the active silicon area.