Patent ID: 7246219

Claim:
A processor comprising: an instruction retirement unit; a first set of functional blocks to process a first set of instructions having a first instruction type; a second set of functional blocks to process a second set of instructions having a second instruction type; and a controller to enable the first set of functional blocks to process an instruction allocated to the instruction retirement unit if the type of the instruction is the first type, and to disable the first set of functional blocks after the instruction is retired by the instruction retirement unit, the controller comprising: a tracking counter to reset a first predetermined value if the processor is in a reset state, and the tracking counter is set to a second predetermined value if the instruction is allocated to the instruction retirement unit and the type of the instruction is the first type; and a tracking state machine to generate a control signal to enable the first set of functional blocks, the tracking state machine comprising: the tracking counter; a counter reset unit; a tracking comparator; and an enable generator.