Patent ID: 7571422

Claim:
A method for generating a design rule map having a spatially varying design rule overlay budget, the method comprising: providing a design data file that characterizes a fabrication process used for forming a pattern on a semiconductor substrate where information contained in the design data file includes pattern information concerning patterns formed on a first layer of a semiconductor substrate and pattern information concerning patterns formed on a second layer that is formed over the first layer of a semiconductor substrate; processing the information contained in the design data file to generate a design map that includes a spatially varying overlay error budget for the design map using a computer processor, comprising: characterizing the design map as a set of user defined regions, including characterizing a first portion of the map as having a first pattern density and second portion of the map as having a second pattern density, and characterizing the first portion having the first pattern density as comprising a portion of the design map were a minimum distance between polygons comprises a first minimum distance and characterizing the second portion having the second pattern density as comprising a portion of the design map were a minimum distance between polygons comprises a second minimum distance; and defining the localized tolerance to overlay errors for each region in the set of user defined regions including defining a first local tolerance to overlay errors for the first portion of the map having a first pattern density and defining a second local tolerance to overlay errors for the second portion of the map having a second pattern density, and defining a first local tolerance to overlay errors as said first minimum distance for the first portion of the map and defining a second local tolerance to overlay errors as said second minimum distance for the second portion of the map, where the spatially varying overlay error budget defines a localized tolerance to overlay errors for different spatial locations on the design map, with portions of the map having a pattern that is relatively tolerant of overlay error having a relatively larger overlay error budget and portions of the map having a pattern that is relatively intolerant of overlay error having a relatively smaller overlay error budget, thereby defining an design map having a spatially varying overlay error budget.