Patent ID: 7654466

Claim:
A semiconductor memory card used by being connected to an access unit, comprising: a host interface section which sends a control signal and data to said access unit and receives a signal from said access unit; a nonvolatile memory which includes a plurality of nonvolatile memory chips and in which a plurality of continuous sectors is grouped to be a block as a minimum unit of data erasing; a memory controller which is connected to each of said plurality of nonvolatile memory chips with a bidirectional bus and controls erasing, writing, and reading of data; and a host information memory which temporarily stores a write speed mode given by said access unit, wherein said memory controller performs, in parallel, writing with respect to said plurality of nonvolatile memory chips when the write speed mode stored in said host information memory is a high speed mode, and sequentially performs writing with respect to said plurality of nonvolatile memory chips when the write speed mode stored in said host information memory is a low speed mode.