Patent ID: 8120573

Claim:
A color sequential timing controlling circuit, applied on a color sequential display and of activating multi-gate lines in cooperation with data arrangement for loading data, the color sequential timing controlling circuit comprising: a line data sorting unit, for buffering and loading a plurality of pixels, the line data sorting unit comprising: a line buffer, for buffering the plurality of pixels in a matrix form; and an insertion sorting circuit, for segmenting the plurality of pixels buffered by the line buffer into a plurality of first equal partitions according to a first segment divisor, so as to simultaneously load pixels of each of the plurality of first equal partitions, and for segmenting each of the first equal partitions into a plurality of second equal partitions according to a second segment divisor, so as to loads pixels in each of the second equal partitions according to a pixel loading sequence; and a color data sorting unit, for classifying and sorting sub-pixels of the plurality of pixels loaded and buffered by the line data sorting unit, according to colors of the sub-pixels; wherein the color sequential timing controlling circuit outputs the sub-pixels sorted by the color data sorting unit according to a time variation, so as to generate a full-color frame; wherein the pixel loading sequence indicates simultaneously loading a pixel from each of a plurality of third equal partitions segmented from the second equal partition, and a number of the plurality of third equal partitions in the second equal partition is corresponding to a number of simultaneously activated gate lines of a scan driving unit of the color sequential display.