Patent ID: 7064621

Claim:
A synchronous clock generation circuit, comprising: an oscillation circuit providing an output clock signal having an oscillation frequency varied in a discrete manner in accordance with digital control information and providing said output clock signal having an oscillation frequency continuously varied in accordance with analog control information; and a control circuit; wherein said control circuit temporarily fixes said analog control information to a prescribed value and controls said digital control information in accordance with said output clock signal so as to achieve a first lock state in which a phase difference between said output clock signal and an input clock signal attains at most a first prescribed value, and after said first lock state is established, said control circuit fixes said digital control information and controls said analog control information in accordance with said oscillation frequency so as to achieve a second lock state in which a phase difference between said output clock signal and said input clock signal attains at most a second prescribed value; and wherein said oscillation circuit includes a plurality of delay circuits connected in series, a selection circuit selecting one of outputs from said plurality of delay circuits as a selected output in accordance with said digital control information, and an inversion delay circuit inverting said selected output and providing the inverted selected output to an input of a delay circuit at a first stage among said plurality of delay circuits, and at least one of said plurality of delay circuits and said inversion delay circuit has a delay amount varied in accordance with said analog control information.