Patent ID: 7401283

Claim:
A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal that is generated according to an LDPC code having a corresponding LDPC bipartite graph that includes bit nodes and check nodes selectively connected via edges, the decoder comprising: a bit node processor that is operable to: receive a metric that corresponds to a bit of the LDPC coded signal; scale the metric using an amplification factor; compute soft bit information, corresponding to the bit of the LDPC coded signal, using the scaled metric and a plurality of edge messages with respect to the plurality of check nodes; and update a plurality of edge messages with respect to a plurality of bit nodes using the soft bit information and the plurality of edge messages with respect to the plurality of check nodes; and a check node processor that is operable to update the plurality of edge messages with respect to the plurality of check nodes using the updated plurality of edge messages with respect to the plurality of bit nodes.