Patent ID: 8595919

Claim:
An apparatus for use in a wafer-level test of a wafer, comprising: a printed circuit board (PCB) for a tester interface of the wafer-level test; a multi-layer ceramic and/or organic space transformer coupled to and in signal communication with the PCB; and a silicon chicklet pedestal, comprising: a silicon wafer having first and second opposing faces and a main body through which an array of vias each extend between the first and the second faces; an insulating layer formed on sidewalls of each of the vias; a conductive layer formed on the insulating layer; a cured filling, including conductive material, disposed in remaining spaces in each of the vias; and a pair of leads associated with each of the vias at the first and second faces, the leads of each pair being electrically connectable by the conductive material of the associated via wherein the silicon chicklet pedestal is interposed between and coupled to the multi-layer ceramic and/or organic space transformer and the wafer at the first and second faces, respectively.