Patent ID: 6988172

Claim:
An apparatus in a microprocessor having a cache, a store buffer, and a plurality of response buffers, for alleviating the need to maintain coherency between cache line status of the store buffer and cache line status of one of the plurality of response buffers if the response buffer holds the same cache line address, the apparatus comprising: a plurality of match bits, for specifying an association, if any, between the store buffer and one of the plurality of response buffers holding a same cache line address, if any; and control logic, coupled to said plurality of match bits, for updating the cache in response to a store operation, wherein if said plurality of match bits specifies an association between the store buffer and one of the plurality of response buffers, then said control logic updates the cache with cache line status stored in said associated one of the plurality of response buffers, and otherwise updates the cache with cache line status stored in the store buffer.