Patent ID: 8575698

Claim:
A semiconductor structure comprising: a semiconductor substrate; a buried oxide layer having a thickness of from 10 to 50 nm within the semiconductor substrate; a gate stack on the semiconductor substrate, wherein a channel region having a thickness of from 5 to 10 nm is provided between the gate stack and the buried oxide layer; a dielectric layer adjacent to the buried oxide layer; a first epitaxially-grown region adjacent to the dielectric layer; wherein the first epitaxially-grown region has a lattice constant different from the lattice constant of the semiconductor substrate; and a second epitaxially-grown region adjacent to the channel region and adjacent to the first epitaxially-grown region; wherein the first epitaxially-grown region is undoped or has a dopant concentration of less than 1·10 18 atoms/cm 3 and the second epitaxially-grown region has a dopant concentration of more than 1·10 19 atoms/cm 3 .