Patent ID: 8890141

Claim:
A transistor, comprising: an oxide semiconductor layer including a source region, a drain region and a channel region, the channel region between the source and drain regions; a gate electrode on the channel region; a gate insulating layer between the channel region and the gate electrode, the gate insulating layer on the channel layer, and the gate insulating layer only partially covering a surface of the source region and only partially covering a surface of the drain region; insulating spacers on the gate insulating layer and on at least one surface of the gate electrode; and an interlayer insulating layer on the oxide semiconductor layer, the gate insulating layer, the gate electrode, and the insulating spacers, the interlayer insulating layer directly contacting at least a side surface of the oxide semiconductor layer, wherein a portion of the source and drain regions which is covered by the gate insulating layer and another portion of the source and drain regions which is not covered by the gate insulating layer have the same resistance, and wherein a width of the gate insulating layer is the same as or greater than a combined width of the gate electrode and the insulating spacers.