Patent ID: 8558240

Claim:
A thin film transistor display panel, comprising: a substrate; a gate wire arranged on the substrate and comprising a gate line extending in a first direction and a gate electrode protruding from the gate line; a gate insulating layer disposed on the gate wire; a semiconductor layer arranged on the gate insulating layer; a data wire comprising: a source electrode disposed on the semiconductor layer; a drain electrode disposed on the semiconductor layer and opposing the source electrode with respect to the gate electrode; and a data line extending in a second direction and intersecting the gate line; a passivation layer disposed on the data wire and comprising a contact hole exposing a portion of the drain electrode; and a pixel electrode disposed on the passivation layer and connected to the drain electrode through the contact hole, wherein the gate wire comprises a first region where the gate line is positioned and a second region where the gate electrode is positioned, the thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region, and the gate insulating layer is disposed on an uppermost surface of the gate wire in the first region.