Patent ID: 6920061

Claim:
A bistable memory cell, comprising: a first and second data terminal; a first and second storage node; an activation terminal; a first access transistor connected between the first data terminal and the first storage node, wherein a gate terminal of the first access transistor is connected to the activation terminal; a second access transistor connected between the second data terminal and the second storage node, wherein a gate terminal of the second access transistor is connected to the activation terminal; a first pull-down transistor, connected between the first storage node and ground, wherein a gate terminal of the first pull-down transistor is connected to the second storage node; and a second pull-down transistor, connected between the second storage node and ground, wherein a gate terminal of the second pull-down transistor is connected to the first storage node; wherein the first and second access transistor have a first threshold voltages that are substantially the same, and wherein the first and second pull-down transistors have second threshold voltages that are substantially the same, wherein the second threshold voltages are greater than the first threshold voltages.