Patent ID: 8326903

Claim:
A method for indicating whether an n-bit vector contains at least two logic high values, comprising: receiving an n-bit vector, wherein each bit indicates a state of an associated entity; arranging the n-bit vector into a plurality of first subsets, wherein each bit is a member of only one of the plurality of first subsets; adding the members of each first subset together, to generate a plurality of first sum signals and a plurality of first carry signals, each first sum signal associated with only one of the plurality of first subsets, and each first carry signal associated with only one of the plurality of first subsets; arranging the plurality of first sum signals into a plurality of second subsets, wherein each first sum signal is a member of only one of the plurality of second subsets; adding the members of each second subset together, to generate a plurality of second sum signals and a plurality of second carry signals, each second sum signal associated with only one of the plurality of second subsets, and each second carry signal associated with only one of the plurality of second subsets; generating a first OR signal based on the results of a logic OR operation using the plurality of first carry signals as inputs; adding the plurality of second sum signals together, to generate a final carry signal; generating a second OR signal based on the results of a logic OR operation using the plurality of second carry signals as inputs; and generating a signal indicating whether the n-bit vector includes at least two logic high values, based on the first OR signal, the second OR signal, and the final carry signal.