Patent ID: 8743595

Claim:
A semiconductor device, comprising: a first memory cell; a second memory cell adjacent to said first memory cell; first and second write bitlines; and a common bitline, wherein said first memory cell includes: a first magnetization fixed layer having a magnetization fixed in a first direction; a first magnetic recording layer coupled to said first magnetization fixed layer and formed of ferromagnetic material; a first reference layer disposed opposed to said first magnetic recording layer; a first tunnel barrier film disposed between said first magnetic recording layer and said first reference layer; and a first transistor connected between said first magnetization fixed layer and said first write bitline, wherein said second memory cell includes: a second magnetization fixed layer having a magnetization fixed in said first direction; a second magnetic recording layer coupled to said second magnetization fixed layer and formed of ferromagnetic material; a second reference layer disposed opposed to said second magnetic recording layer; a second tunnel barrier layer disposed between said second magnetic recording layer and said second reference layer; and a second transistor connected between said second magnetization fixed layer and said second write bitline, wherein said first and second reference layer each have a magnetization fixed in said first direction or in a second direction opposite to said first direction, wherein a common magnetization fixed layer having a magnetization fixed in said second direction is coupled to said first and second magnetic recording layers, and wherein said common magnetization fixed layer and said common bitline is connected so that said common magnetization fixed layer and said common bitline are unable to be electrically unconnected.