Patent ID: 7781238

Claim:
A method for making a testable sensor assembly, comprising: forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate; coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array; thinning one of the second side of the first substrate or the second side of the first semiconductor wafer; coupling a second semiconductor wafer having a first side and a second side to the sensor assembly, wherein the second semiconductor wafer comprises a plurality of cavities disposed on the first side, and wherein the first side having the plurality of cavities is coupled to the thinned wafer thinning the second side of one of the second semiconductor wafer or the other of the first substrate to expose the free internal membranes; and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.