Patent ID: 6970996

Claim:
For use in a data processor, a floating point unit comprising: a buffer capable of storing operands and comprising a forwarding array of addressable memory locations; a plurality of floating point processing units capable of executing floating point instructions that write operands to an external memory and capable of executing floating point instructions that read operands from said external memory; and an operand queue capable of storing a plurality of operands associated with one or more operations being processed in said floating point unit, wherein said operand queue stores a first operand written by a floating point write instruction executed by a first one of said plurality of floating point processing units and wherein said operand queue supplies said first operand to a floating point read instruction executed by a second one of said plurality of floating point processing units when said floating point read instruction requires said first operand; wherein said first operand is virtually committed by writing the first operand from said operand queue to the buffer and by writing an operand queue address of the first operand into the memory location in the forwarding array that is associated with the floating point write instruction; wherein said first operand is supplied to the floating point read instruction by writing the operand queue address of the first operand into the memory location in the forwarding array that is associated with the floating point read instruction, the operand queue address in the memory location associated with the floating point read instruction used to retrieve the first operand from the operand queue; and wherein a second operand is written directly to the buffer bypassing the operand queue in response to a slot in the operand queue, where the second operand was to be stored, already being virtually committed.