Patent ID: 8753963

Claim:
A method of manufacturing a multi-trench termination structure for a semiconductor device consisting of an active structure region and a termination structure region, the method comprising: (a) providing a semiconductor substrate of the semiconductor device; (b) forming a mask layer on the semiconductor substrate; (c) forming a multi-trench structure with a plurality of trenches by etching the semiconductor substrate with respect to the mask layer; (d) forming a gate insulation layer on the multi-trench structure; (e) forming an electrically conductive layer on the gate insulation layer, and etching back the electrically conductive layer until a top face of the electrically conductive layer is lower than a top face of the mask layer, the electrically conductive layer being higher than the gate insulation layer and in contact with the mask layer at edge of the trench; (e1) removing part of the mask layer at the active structure region such that the mask layer is remained on location corresponding to the termination structure region only; (f) forming a metal layer covering the electrically conductive layer at the active structure region, and covering the mask layer and the electrically conductive layer at the termination structure region; and (g) forming a passivation layer covering the metal layer at the termination structure region only, wherein the passivation layer is in direct contact with the mask layer and the electrically conductive layer at a peripheral of the termination structure region.