Patent ID: 8443168

Claim:
A microcontroller comprising: a plurality of primary registers operable for storing primary data, wherein each instance of said primary data has a first width; a secondary register comprising said at least two of said primary registers and operable for storing secondary data, wherein said secondary data has a second width, wherein said second width is an integer multiple of said first width; and a central processing unit (CPU) that is operable for executing a first instruction set in a first mode in which an instance of said primary data is fetched and that also is operable for executing a second instruction set in a second mode in which an instance of said secondary data is fetched; wherein said first instruction set comprises a first instruction, wherein a result of executing said first instruction is written to one of said primary registers constituting said secondary register; and wherein said second instruction set comprises a second instruction, wherein a result of executing said second instruction is written to more than one of said primary registers constituting said secondary register.