Patent ID: 7873775

Claim:
A memory system, comprising: a plurality of memory requestors; and a first rank containing a plurality of memory modules each of which comprises: a plurality of memory devices; a memory hub coupled to a plurality of the memory requestors, to a port, and to the memory devices in the memory module, the memory hub in each of the memory modules being configured to allow any of the memory requesters to access the memory devices to which it is coupled and to communicate with the port of the memory hub; and a second rank containing a plurality of memory modules each of which comprises: a plurality of memory devices; and a memory hub coupled to the memory devices in the memory module and to the respective port of the memory hub in each of a plurality of the memory modules in the first rank, the memory hub in each of the memory modules in the second rank being configured to allow any of the memory requestors to access the memory devices to which it is coupled through at least one memory module in the first rank.