Patent ID: 7093109

Claim:
The use of multiple threads in association with a network processor and accessible data available in a tree search structure, including the steps of: a) providing multiple instruction execution threads as independent processes in a sequential time frame; b) encoding a processor instruction to select an event from the group consisting of a short latency event and a long latency event; c) queuing the multiple execution threads to have overlapping access to the accessible data available in said tree search structure; d) executing a first thread in a queue; e) transferring control of the execution to the next thread in the queue upon the occurrence of an event that causes execution of the first thread to stall; and f) when the stall is due to the short latency event, returning control to the first thread when the event is completed, and when the stall is due to the long latency event, retaining full control by the next thread until the next thread becomes blocked.