Patent ID: 7135884

Claim:
An integrated circuit comprising: a voltage mode transmit driver comprising: (1) first and second resistor network circuits configured for outputting respective first and second differential signals via respective first and second signal nodes onto first and second differential signal transmission lines having a transmission line impedance, the first and second resistor network circuits each comprising: (1)(a) pull-up circuits configured for selectively changing an impedance on the corresponding signal node of the corresponding resistor network circuit based on respective pull-up gate signals, the pull-up circuits having respective binary weighted resistance values relative to each other, (1)(b) pull-down circuits configured for selectively changing an impedance on the corresponding signal node of the corresponding resistor network circuit based on respective pull-down gate signals, the pull-down circuits having the respective binary weighted resistance values relative to each other, and (2) a driver controller configured for controlling each of the pull-up gate signals and the pull-down gate signals based on a data input signal, a clock signal, and a binary code representing an output impedance correction factor, the driver controller configured for causing the first and second resistor network circuits to match an output impedance of the first and second nodes to the transmission line impedance based on the binary code; and a calibration circuit having a replica of the pull-up circuits and a replica of the pull-down circuits, the calibration circuit configured for determining the binary code, at prescribed intervals for calibration of the binary weighted resistance values, based on comparing a first voltage to a second voltage across a range of the binary code, the first and second voltages generated by respective first and second potential dividers formed between first and second external precision resistors and the replicas of the pull-up circuits and the pull-down circuits, respectively, the first and second external precision resistors each having a precision resistance representing an ideal transmission line impedance.