Patent ID: 7904675

Claim:
A system comprising: a first processor; a first primary cache memory used by said first processor; a second processor; a second primary cache memory used by said second processor; and a secondary cache memory used by said first and second processors, wherein said secondary cache memory has a set associative scheme, said secondary cache memory including: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among said plurality of ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on at least one entry by prioritizing a way whose priority attribute held by said first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from said processor, (ii) all of the following attributes match: the data attribute of the entry of the first way that holds valid data; the data attribute outputted from said processor; and at least one priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry of the way other than the first way being one of the entries that belong to the selected set, said control unit is further operable to store data into the entry of the way other than the first way.