Patent ID: 7099404

Claim:
An integrated circuit comprising: first and second transmitter circuits disposed on a chip, each transmitter circuit having a respective output operating frequency of at least 1 GHz and configured to output a respective output signal corresponding to a respective sequence of input bits in a respective input signal, each output signal having a bandwidth greater than 100 MHz and a single output bit corresponding to each input bit of the respective input signal, the single output bit having a digital value selected from at least a first digital value and a second digital value, when the single output bit has the first digital value, the transmitter circuit driving the single ouput bit to one of a first plurality of signal levels using the corresponding input bit and at least one previous input bit in the sequence of input bits; and when the single output bit has the second digital value, the transmitter circuit driving the single output bit to one of a second plurality of signal of levels, different from the first plurality of signal levels, using the corresponding input bit and at least one previous input bit in the sequence of input bits.