Patent ID: 7649405

Claim:
A leakage current control circuit with a single low voltage power supply, operating in a sleep mode or an active mode in response to an internal sleep mode signal, comprising: a first power supply line connected to a plurality of first components, the plurality of first components including one of a plurality of flip-flops and a plurality of combinational circuits; a second power supply line connected to a plurality of second components, the plurality of second components including an other of the plurality of flip-flops and the plurality of combinational circuits, each of the plurality of first components and the plurality of second components being connected to different ones of the first and second power supply lines, respectively; a first ground line; a high-voltage generating circuit for generating an output voltage in response to the internal sleep mode signal; a power transistor having a first end, a second end and a gate electrode, wherein the first end is connected to the said first power supply line, the second end is connected to the second power supply line, the gate electrode is connected to the output of the said high-voltage generating circuit; and a control circuit connected to the first power supply line, the second power supply line, and the first ground line for generating the internal sleep mode signal in response to an external sleep mode signal and controlling a clock signal.