Patent ID: 8331153

Claim:
A nonvolatile memory apparatus configured to be used as a storage unit, comprising: a system bus interface; a nonvolatile memory; and a control logic device for controlling writing data and reading data to and/or from the nonvolatile memory, wherein the system bus interface is configured for coupling with a system bus, and for receiving an address, a command code, and/or a control signal from the system bus, wherein the nonvolatile memory includes plural memory blocks each including plural memory cells, each of which is configured for storing plural bits of data therein by shifting a threshold voltage thereof to one of plural threshold voltage ranges, wherein, in performing a first page writing, the threshold voltage of a first memory cell of said plural memory cells remains in a first threshold voltage range or shifts into a second threshold voltage range in accordance with data to be written into the first memory cell, wherein, in performing a second page writing, the threshold voltage of the first memory cell remains in the first threshold voltage or the second threshold voltage, or shifts into a third threshold voltage range from the first threshold voltage range or into a fourth threshold voltage range from the second threshold voltage range, wherein, before performing the second page writing, the nonvolatile memory reads data from the first memory cell for generating the second page writing data, and wherein a shifting direction of the threshold voltage of the first memory cell from the first threshold voltage range to the second threshold voltage range is the same with a shifting direction from the first threshold voltage range to the third threshold voltage range.