Patent ID: 7554375

Claim:
A delay locked loop, comprising: a first initial delay unit that receives an external clock signal and is configured to generate a first time delayed signal from the external clock signal; a second initial delay unit that receives the first time delayed signal and is configured to generate a second time delayed signal from the first time delayed signal; a first mixing unit that receives the first time delayed signal and the second time delayed signal and is configured to generate a first mixed output signal based upon the first time delayed signal and the second time delayed signal, wherein an internal propagation time of the first mixing unit is controlled based upon a value of a weight parameter; a second mixing unit that receives the first time delayed signal and the second time delayed signal and is configured to generate a second mixed output signal based upon the first time delayed signal and the second time delayed signal, wherein an internal propagation time of the second mixing unit is controlled based upon the value of the weight value; a plurality of serially-coupled delay line units, each of the plurality of delay line units including first and second input nodes, wherein the second input node is coupled to receive either the first or second mixed output signal; and a shift register unit that selectively enables the delay line units.