Patent ID: 8203142

Claim:
A memory device comprising: a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region, wherein each of the first impurity region and the second impurity region has one of an n-type conductivity and a p-type conductivity and includes a first impurity for imparting the one of the n-type conductivity or the p-type conductivity; a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region; a memory element electrically connected to a first terminal of the diode; and a wiring electrically connected to a second terminal of the diode; wherein the n-type impurity region or the p-type impurity region of the diode includes a second impurity for imparting the same conductivity as that of the first impurity, and wherein a concentration of the first impurity included in at least one of the first impurity region and the second impurity region is the same or substantially same as a concentration of the second impurity included in the one of the n-type impurity region and the p-type impurity region of the diode.