Patent ID: 8913431

Claim:
A three-dimensional stacked non-volatile memory device, comprising: a substrate; a plurality of sets of memory cells above the substrate in multiple physical levels, each set of memory cells comprising an active area comprising a channel that extends vertically through the physical levels, the sets of memory cells are associated with pseudo blocks, each pseudo block comprises a portion of each of the sets of memory cells, each of the sets of memory cells is a member of each of the pseudo blocks, wherein each of the memory cells is characterized by a memory hole size, the memory cells are associated with pseudo blocks based on memory hole size; and circuitry associated with operation of the plurality of sets of memory cells, the circuitry is in communication with the plurality of sets of memory cells, the circuitry operates in a pseudo block operation mode that performs operations associated with the plurality of sets of memory cells on a pseudo block level for the three-dimensional stacked non-volatile memory device.