Patent ID: 8765578

Claim:
A method of edge protecting bonded semiconductor wafers comprising: providing a second semiconductor wafer having a first surface and a second surface opposite to the first surface; attaching the first surface of the second semiconductor wafer to a first semiconductor wafer by using a bonding layer/interface; thinning the second semiconductor wafer from the second surface to a first predetermined dimension; forming a first protective layer to entirely cover the second semiconductor wafer and at least a portion of an edge of the first semiconductor wafer; thinning the second semiconductor wafer from the second surface to a second predetermined dimension while maintaining the first protective layer on an edge only of the second semiconductor wafer and the edge only of the first semiconductor wafer; providing a third semiconductor wafer having a first surface and a second surface opposite to the first surface; attaching the first surface of the third semiconductor wafer to the second surface of the second semiconductor wafer by using a bonding layer/interface, the third semiconductor wafer, second semiconductor wafer and first semiconductor wafer forming a semiconductor wafer stack; thinning the third semiconductor wafer from the second surface to a third predetermined dimension; forming a second protective layer to entirely cover the third semiconductor wafer and the first protective layer; thinning the third semiconductor wafer to a fourth predetermined dimension while maintaining the second protective layer on an edge only of the third semiconductor wafer and on the first protective layer; and dicing the semiconductor wafer stack with the maintained second protective layer and first protective layer into a plurality of three dimensional chip stacks, each of the three dimensional chip stacks being devoid of the second protective layer and the first protective layer.