Patent ID: 7768127

Claim:
A semiconductor device comprising: a semiconductor substrate; a multi-layer wiring portion including insulating layers and wiring layers alternately stacked one on another on a main surface of the semiconductor substrate, all of the wiring layers being made of a same basis metal, at least one of the wiring layers containing an additive element, and a concentration of the additive element being lower on an upper layer side than that on a lower layer side, the upper and lower layer sides are that of the multi-layer wiring portion; and upper diffusion inhibiting layers formed on the top of the wiring layers, a film thickness of an upper diffusion inhibiting layer on an upper side of an adjacent pair of the upper diffusion inhibiting layers is thicker than or equal to that of an upper diffusion inhibiting layer located on a lower side of the adjacent pair, wherein a specific inductive capacity of an insulating layer located on an upper side of an adjacent pair of insulating layers included in the multi-layer wiring portion is equal to or higher than that of an insulating layer located on a lower side of the adjacent pair, and the specific inductive capacity of the lowermost layer is lower than that of the uppermost layer.