Patent ID: 7115920

Claim:
An integrated circuit, comprising: a first transistor comprising: a first source and a first drain; a single-crystal first fin having first and second opposing ends and first and second opposing sidewalls and extending along a first longitudinal axis from said first to said second end of said first fin, said first end of said first fin in contact with said first source and said second end of said first fin in contact with said first drain, said first longitudinal axis aligned to a crystal plane; a single-crystal second fin having first and second opposing ends and first and second opposing sidewalls and extending along a second longitudinal axis from said first to said second end of said second fin, said first end of said second fin in contact with said first source and said second end of said second fin in contact with said first drain, said second longitudinal axis aligned in a plane rotated away from said crystal plane; and a first conductive gate in contact with a gate dielectric formed on said first and second sidewalls of said first fin and on said first and second sidewalls of said second fin; and a second transistor comprising: a second source and a second drain; a single-crystal third fin having first and second opposing ends and first and second opposing sidewalls and extending along a third longitudinal axis from said first to said second end of said third fin, said first end of said third fin in contact with said second source and said second end of said first fin in contact with said second drain, said third longitudinal axis aligned to said crystal plane; and a second conductive gate in contact with a gate dielectric formed on said first and second sidewalls of said third fin and on said first and second sidewalls of said third fin.