Patent ID: 8086988

Claim:
A chip design and fabrication method comprising: calculating, by a computer and based on a design of a chip, a first joint probability distribution as a function of first values for a first metric and, based on said first joint probability distribution, generating a first yield curve; calculating, by said computer and based on said design of said chip, a second joint probability distribution as a function of second values for a second metric that is different from said first metric and, based on said second joint probability distribution, generating a second yield curve; associating monetary values with said first values and with said second values, said monetary values indicating profits associated with said first values and said second values; using said monetary values to combine said first yield curve and said second yield curve into a combined yield curve; and modifying said design, based on said combined yield curve, in order to simultaneously optimize yield as a function of both said first values and said second values and maximize profit potential by considering said monetary values for said first values and said second value.