Patent ID: 7220637

Claim:
A method of manufacturing a semiconductor device comprising the steps of: (a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a first PMOS region for forming a first PMOS transistor; (b) selectively forming a first gate insulating film in both said first NMOS region and said first PMOS region and forming both a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and said first PMOS region, respectively; and (c) ion implanting an N-type impurity using at least said first gate electrode of said first NMOS region as part of an implant mask to form a pair of first extension layers in the surface of said semiconductor substrate outside a side surface of said first gate electrode of said first NMOS region, and ion implanting a P-type impurity using at least said second gate electrode of said first PMOS region as part of an implant mask to form a pair of second extension layers in the surface of said semiconductor substrate outside a side surface of said second gate electrode of said first PMOS region, said step (c) including the step of: (c- 1 ) forming a pair of first ion-implanted layers by ion implantation of said N-type impurity in said first NMOS region and forming a pair of second ion-implanted layers by ion implantation of said P-type impurirty in said first PMOS region, wherein a spacing between said second ion-implanted layers is wider than a spacing between said first ion-implanted layers, said first and second ion-implanted layers grow into said first and second extension layers respectively through heat treatment when forming source and drain layers of both said first NMOS transistor and said first PMOS transistor, and said step (c- 1 ) includes the steps of: (c- 1 - 1 ) forming a first offset sidewall with a silicon oxide film on side surface of said first and second gate electrodes; (c- 1 - 2 ) ion implanting said N-type impurity into said first NMOS region using said first gate electrode and said first offset sidewall as implant masks to form said first ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said first gate electrode; (c- 1 - 3 ) forming a second offset sidewall on a side surface of said first offset sidewall; and (c- 1 - 4 ) ion implanting said P-type impurity into said first PMOS region using said second gate electrode and said first and second offset sidewalls as implant masks to form said second ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said second gate electrode.