Patent ID: 7295038

Claim:
A level shifter comprising a first switching circuit configured to perform a switching operation in response to a first input signal swinging between a first voltage level and a second voltage level; a second switching circuit configured to perform a switching operation in response to a second input signal having an inverted phase of the first input signal; a level control circuit, coupled to a power voltage having a third voltage level, the level control circuit including an output terminal coupled to the second switching circuit and outputting a first output signal swinging between the first voltage level and the third voltage level to the output terminal based on the switching operations of the first switching circuit and the second switching circuit; and a power compensation circuit configured to provide the power voltage having the third voltage level to the level control circuit in response to the first output signal to turn off an operation of the level control circuit; wherein the level control circuit comprises: a first PMOS transistor having a source coupled to the power voltage, a drain coupled to the first switching circuit and a gate coupled to the drain; and a second PMOS transistor having a source coupled to the power voltage, a drain coupled to the output terminal and a gate coupled to the gate of the first PMOS transistor.