Patent ID: 8742596

Claim:
A semiconductor device comprising: a first laminate having a wiring layer formed on a substrate; a second laminate having a wiring layer formed on a substrate, a principal surface of the second laminate being bonded to a principal surface of said first laminate; a functional element disposed in at least one of said first laminate and said second laminate; an air gap penetrating an interface between said first laminate and said second laminate, the air gap being disposed on an outside of a circuit formation region including said functional element in at least one of said first laminate and said second laminate as viewed from a direction perpendicular to the principal surfaces of said first laminate and said second laminate, wherein said air gap is a groove penetrating said second laminate; a seal ring enclosing the circuit formation region of said first laminate and said second laminate as viewed from a direction perpendicular to said principal surface of said first laminate, wherein said groove is disposed on an outside of said seal ring, and a bottom surface of said groove coincides with a surface of wiring within said first laminate; and a penetrating metallic member penetrating said substrate of said second laminate and said interface, wherein said penetrating metallic member is connected to wiring in a same layer as said wiring coinciding with the bottom surface of said groove.