Patent ID: 8258513

Claim:
A thin film transistor matrix device comprising: an insulating substrate; a plurality of lines arranged on said substrate, said lines being defined as odd-number-th lines alternating with even-number-th lines; a first connection line extending in a direction transverse to said plurality of lines, said first connection line and said odd-number-th lines being configured and arranged to be electrically connected to each other; and a second connection line extending in a direction transverse to said plurality of lines, said second connection line and said even-number-th lines being configured and arranged to be electrically connected to each other, wherein said first connection line and said second connection line are both formed on the same side of an image display region, when considered in plan view, wherein said first connection line and said second connection line are both located on the insulating substrate, in an area between the image display region and an edge of the insulating substrate, and wherein said plurality of lines are associated, respectively, with drain bus lines and/or gate bus lines.