Patent ID: 8653571

Claim:
A semiconductor device comprising: a semiconductor substrate; a semiconductor region formed on the semiconductor substrate, the semiconductor region having an upper face and side faces forming a saddle-like shape, the semiconductor region comprising convex portions formed at both ends of a region including a saddle point in the upper face, the both ends lying in a first direction; a gate insulating film formed on the upper face of the semiconductor region except upper faces of the convex portions, on side faces of the semiconductor region extending in the first direction, and on side faces of the convex portions on a side of the region including the saddle point in the upper face, the side faces of the convex portions extending in a second direction perpendicular to the first direction, the second direction being parallel to the upper face of the semiconductor region; a gate electrode formed on the gate insulating film, the gate electrode including: a main body portion including a first portion and second portions, the first portion located above the region including the saddle point in the upper face, a width in the second direction of the first portion being greater than a width in the second direction of the region including the saddle point in the upper face, the second portions being connected to the first portion, covering the side faces of the semiconductor region extending in the first direction and located in higher position than the region including the saddle point in the upper face, a first length of the first portion in the first direction being smaller than a second length of each of the second portions in the first direction; and leg portions connected to the second portions of the main body portion and covering the side faces of the semiconductor region extending in the first direction, a third length of each of the leg portions in the first direction being greater than the first length of the first portion and being substantially the same as the second length of each of the second portions; and first and second impurity regions formed in portions of the semiconductor region, the portions being located on both sides of the gate electrode, each of first and second impurity regions including a third portion and a fourth portion connected to the third portion, the third portion being formed at the convex portions in the semiconductor region and located in higher position than upper faces of the second portions of the gate electrode, the fourth portion being located between the third portion and the semiconductor substrate, a length of the third portion in the first direction is greater than a length of the fourth portion in the first direction.