Patent ID: 8024695

Claim:
A method for optimization of a library for use in circuit design, the method comprising: providing an initial circuit netlist; providing one or more sets of existing cells; providing one or more sets of additionally admissible cells additional to the one or more sets of existing cells; using at least one computer processor, analyzing the initial circuit netlist to find cells that reduce implementation costs considering the initially existing set of cells and the additional set of admissible cells, wherein the analyzing comprises remapping the circuit while considering the initially existing set of cells and the additional set of admissible cells; outputting one or more new cell library specifications and descriptions comprising a subset of the preexisting cells and a subset of the admissible cells which potentially reduce design costs; and outputting a new remapped netlist, wherein the additional set of admissible functions is implicitly defined by the maximum allowed number of switches in the exact lower bounds for the number of switches in series in both transistor plans to implement a combinational logic function.