Patent ID: 7676647

Claim:
A processor device comprising: a control register including a combined condition code register for scalar and vector operations; a plurality of instruction execution units to execute scalar and vector instructions that utilize the combined condition code register, wherein the plurality of execution units use a vector multiplexer to selectively swap source operands to support signed and unsigned vector comparisons including compare-for-equal, compare-for-signed-for, and compared-for-unsigned-greater-than instructions; a memory unit; a sequencer responsive to the memory unit; wherein the plurality of instruction execution units are responsive to the sequencer; wherein the sequencer is adapted to fetch a plurality of instructions from the memory unit and to group the plurality of instructions into packets of instructions of different types to be executed in parallel by the plurality of instruction execution units; wherein the memory unit includes an instruction for a scalar operation that utilizes the combined condition code register and an instruction for a vector operation that utilizes the combined condition code register; and wherein the scalar operation is a scalar compare that sets each bit in a predicate register as a first value for a true compare and that sets each bit in the predicate register as a second value for a false compare.