Patent ID: 8253205

Claim:
An integrated circuit (IC) including at a plurality of compressively strained PMOS transistors, comprising: a substrate having a semiconductor surface, wherein each of said plurality of compressively strained PMOS transistors comprise: a gate stack formed in or on said semiconductor surface comprising a gate electrode on a gate dielectric, wherein a channel region is located in said semiconductor surface below said gate dielectric; a source and a drain region on opposing sides of said gate stack; at least one compressive strain inducing region comprising at least one specie selected from Ge, Sn and Pb located in at least a portion of said source and drain regions, wherein said strain inducing region provides ≦10 10 dislocation lines/cm 2 and an active concentration of said compressive strain inducing specie is above a solid solubility limit for said compressive strain inducing specie in said compressive strain inducing region.