Patent ID: 8552561

Claim:
A semiconductor device comprising: a semiconductor chip; a plurality of internal circuits; a corresponding plurality of output circuits disposed in a row in the semiconductor chip, each said output circuit including a first MISFET and a second MISFET coupled to each other; a plurality of bonding pads for outputting output signals in response to outputs of said plurality of internal circuits disposed in the semiconductor chip, each said bonding pad being overlapped with only one of said first MISFET and said second MISFET in each of said output circuits in cross sectional view; a plurality of wirings, each said wiring being coupled to said first and second MISFETs in each of said output circuits; a plurality of conductor plugs, each said conductor plugs being disposed between one of said bonding pads and one of said wirings, each said conductor plug being coupled to a corresponding one of said bonding pads and to a corresponding one of said wirings; a grounding wiring different than said wirings disposed in a lower layer than said plurality of bonding pads and coupled to said first MISFET in each of said output circuits; and a power supply wiring different than said wirings disposed in a lower layer than said plurality of bonding pads and coupled to the second MISFET in each of said output circuits, wherein a gate electrode of each first MISFET and a gate electrode of each second MISFET each receive a signal from a corresponding internal circuit to output the corresponding output signal, wherein each of said wirings and each of said conductor plugs are located between the first MISFET and the second MISFET in each of said output circuits in cross sectional view, and wherein each of said wirings and each of said conductor plugs are located between the grounding wiring and the power supply wiring in cross sectional view.