Patent ID: 8891272

Claim:
A content addressable memory (CAM) system comprising: an address register that includes a first row and a second row; a row decoder that specifies a first address of a first row in a data retention CAM array that is coupled to the first row of the address register, specifies a second address of a second row in the data retention CAM array that is coupled to the second row of the address register, and writes data to the first address and the second address; and a priority encoder that receives a first result of a comparison between data stored in the first row in the data retention CAM array and search data, receives a second result of a comparison between data stored in the second row in the data retention CAM array and the search data, and outputs, based on the first result and the second result, an address of a row in the data retention CAM array that matches a comparison result; wherein the row decoder and the priority encoder share addresses corresponding to data stored in the first row in the data retention CAM array and data stored in the second row in the data retention CAM array.