Patent ID: 7663954

Claim:
A semiconductor memory device comprising: a memory cell array including a first bit line pair and a plurality of memory cells connecting to said first bit line pair, a selected one of said memory cells delivering data to or receiving data from said first bit line pair; a sense amplifier including therein a second bit line pair and an amplifying element amplifying a potential difference between bit lines of said second bit line pair; and a transfer gate for controlling coupling of said first bit line pair and said second bit line, wherein: after said sense amplifier amplifies, upon selection of one of said memory cells by activating a corresponding word line of the semiconductor memory device, the potential difference between bit lines of said second bit line pair coupled to said first bit line pair by said transfer gate, said transfer gate isolates said second bit line pair from said first bit line pair while said corresponding word line remains activated, and said sense amplifier is inactivated.