Patent ID: 8072410

Claim:
An impulsive type liquid crystal driving device, comprising: a liquid crystal panel comprising: a plurality of gate bus lines arranged in a first direction; and a plurality of data bus lines arranged in a second direction substantially perpendicular to the first direction; a gate driver section for sequentially scanning the plurality of gate bus lines during an active address interval in response to a vertical starting signal, a vertical clock signal, and an output enable signal and for scanning the plurality of gate bus lines during a vertical blanking interval in a unit of a predetermined number of lines; and a current boosting section for increasing current amount supplied to the gate bus lines during the vertical blanking interval in response to a pulse width modulation signal, wherein the supplied current amount is adjustable according a duty ratio of the pulse width modulation signal, and wherein the current boosting section comprises: a plurality of current booster circuits for receiving a plurality of gate on/off signals outputted from the gate driver section and a pulse width modulation signal, respectively; an operational amplifier having a non-inverting terminal and an inverting terminal; a first resistor coupled between the non-inverting terminal and a ground; a first capacitor coupled in parallel to the first resistor; a second capacitor coupled between a first input terminal and the ground; a second resistor of which one end is coupled to the first input terminal; a first bipolar transistor coupled between the other end of the second resistor and a ground, and turned on according to an output signal of the operational amplifier; a third resistor of which one end is coupled to the first input terminal; a second bipolar transistor coupled between other end of the third resistor and the non-inverting terminal, and turned on according to an output signal of other end of the second resistor; a fourth resistor coupled between the first input terminal and the non-inverting terminal; a third capacitor coupled between the inverting terminal of the operational amplifier and an output terminal; a fifth resistor coupled between a second input terminal and the inverting terminal; a sixth resistor coupled between the inverting terminal and a ground; and a fourth capacitor coupled in parallel to the sixth resistor.