Patent ID: 8866227

Claim:
A semiconductor device comprising: a substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon-doped-with-carbon layer; at least one low power semiconductor device including a first n-type semiconductor device and a first p-type semiconductor device on the silicon layer within the first device region of the substrate; a second p-type semiconductor device on the silicon germanium layer of the second device region of the substrate, wherein the second p-type semiconductor device has a threshold voltage that is 0.05 V to 0.5 V less than a threshold voltage of the first p-type semiconductor device of the at least one low power semiconductor device; and a second n-type semiconductor device on the silicon-doped-with-carbon layer of the third device region of the substrate, wherein the second n-type semiconductor device has a threshold voltage that is 0.05 V to 0.3 V less than a threshold voltage of the first n-type semiconductor device of the at least one low power semiconductor device.