Patent ID: 8578084

Claim:
A data storage device comprising: a first memory board; a second memory board, wherein: the first memory board and the second memory board each comprise multiple memory chips; and a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, wherein the controller board comprises: an interface, and a controller that is arranged and configured to receive commands from a host using the interface and to execute the commands, wherein the controller comprises: multiple channels, wherein each of the channels is associated with one or more of the memory chips and each of the memory chips is associated with one of the channels, and multiple channel controllers, wherein each channel controller is assigned to one of the multiple channels and is configured to process commands designated for the memory chips associated with the assigned channel, wherein the first memory board and the second memory board are each separately removable from the controller board and the first memory board, the second memory board and the controller board are assembled together to form a form factor that is sized to fit in a drive bay of a computing device with the first memory board connected to a top side of the controller board using a ball grid array connector and the second memory board connected to a bottom side of the controller board using a ball grid array connector such that the first memory board, the controller board and the second memory board form the form factor.