Patent ID: 8447902

Claim:
A circuit comprising: an input register having an input register data input, an input register clock input, and an input register output; a buffering logic block having a buffering logic block input, a buffering logic block non-inverted output, and a buffering logic block inverted output, said buffering logic block input in communication with said input register output; a timing logic block having a timing logic block input and a timing logic block output, said timing logic block input in communication with said input register clock input; a control logic block having a control logic block input and a control logic block output, said control logic block input in communication with said timing logic block output; a switching logic block having a switching logic block first input, a switching logic block second input, a switching logic block output, and a switching logic block control input, said control logic block input in communication with said control logic block output, said switching logic block first input in communication with said buffering logic block non-inverted output, said switching logic block second input in communication with said buffering logic block inverted output, and said switching logic block output capable of communicating a signal.