Patent ID: 7142004

Claim:
A system for hardening a logic circuit against at least one of a single-event upset and single-event transient condition, the system comprising in combination: a logic circuit outputting independently-obtained first and second redundant signals; first and second feed-forward devices, wherein each of the first and second feed-forward devices is operable to receive both of the first and second redundant signals, and wherein when the first and second redundant signals are in expected states, then (i) the first feed-forward device responsively provides a first feed-forward signal and (ii) the second feed-forward device responsively provides a second feed-forward signal, and wherein when at least one of the first and second redundant signals is in an unexpected state, then both the first and second feed-forward devices continue to provide their respective feed-forward signals consistent with the last expected state of the redundant signals; and first and second feedback devices, wherein each of the first and second feedback devices is operable to receive both of the first and second feed-forward signals, and wherein when the first and second feed-forward signals are in expected states, (i) the first feedback device responsively feeds a first feedback signal back to the first redundant signal and (ii) the second feedback device responsively feeds a second feedback signal back to the second redundant signal, and wherein when at least one of the first and second feed-forward signals is in an unexpected state, then both the first and second feedback devices continue to provide their respective feedback signals consistent with the last expected state of the feed-forward signals.