Patent ID: 8654488

Claim:
An integrated circuit device comprising: a primary electrostatic discharge (ESD) circuit connected between a power supply pad and a ground pad of the integrated circuit device, and configured to couple an ESD pulse from the power supply pad to ground in response to a voltage level at the power supply pad achieving a main trigger voltage level; a buffer circuit coupled and configured and arranged to receive regulated power from the power supply pad and being susceptible to activation in response to an ESD pulse at which the main trigger voltage level is reached; and a secondary ESD circuit coupled to a node between the buffer circuit and the primary ESD circuit, the secondary ESD circuit including a field-effect transistor (FET) including gate, source and drain electrodes, the source and drain electrodes being connected respectively at first and second nodes across the buffer circuit, with the first and second nodes configured and arranged to provide regulated power, relative to the power supply pad and ground pad, to the buffer circuit, and a trigger circuit connected to the FET gate, the trigger circuit being configured to detect electrostatic pulses and, in response to detecting an ESD pulse at a secondary trigger voltage level, to turn on the FET to pass current through the FET and limit a voltage drop across the buffer circuit.