Patent ID: 6886151

Claim:
A design method for a multilayer wiring board having a via hole which interconnects adjacent layers, comprising the steps of: reading each parameter of a via hole size, a shift direction, and a via hole pitch of each layer of each via hole; storing said parameters in a memory; accepting a designation of a start layer and a last layer from among a plurality of layers of said multilayer wiring board to be designed; and routing of said multilayer wiring board based on said information indicated by said parameters stored in said memory in said storing step and said designation, wherein said routing step includes: a signal net selecting step of selecting a signal net by a user-input instruction; a wiring layer selecting step of selecting wiring layers based on said designation of said start layer and said last layer; a via hole selecting step of selecting one of said via holes by said user-input instruction; a parameter reading step of reading said parameters of said selected one of said via holes regarding said selecting wiring layers; a via hole/routing forming step of forming a via hole and routing for said signal net selected, based on said read parameters; a design error absence/presence determining step of checking for an error relative to a design; a reselecting step of returning to said via hole selecting step in a case where it is determined that there is an error relative to the design, and again reading said parameters including a reselecting of a shift direction; and a design completion determining, step of determining whether or not formation of a via hole and routing is completed for said signal net included in the multilayer wiring board.