Patent ID: 7818656

Claim:
A circuit comprising: a first combinatorial circuit configured to implement a combinatorial function f, wherein the first combinatorial circuit is configured to receive inputs x[1](t), . . . , x[n](t) and x′[1](t), . . . , x′[n](t), and to output y[1](t), . . . , y[n](t), wherein the combinatorial function f determines outputs y[1](t), . . . , y[n](t) such that outputs y[1](t), . . . , y[n](t) are indicative of a bit-by-bit comparison of inputs x[1](t), . . . , x[n](t) and x′[1](t), . . . , x′[n](t); a controllable register, comprising: n flip-flops, FF1, . . . , FFn, configured to assume binary states z[1](t), . . . , z[n](t), and n multiplexers, MUX1, . . . , MUXn each comprising: a first data input, wherein for j=1, . . . , n the first data input of the multiplexer MUXj is connected to the j-th output y[j](t) from the first combinatorial circuit, a second data input, wherein for k=1, . . . , n−1, the second data input of the multiplexer MUXk is the binary state z[k+1](t), and wherein the second data input of the multiplexer MUXn is an external signal E(t), and a first control input configured to carry a binary control signal s; and a second combinatorial circuit configured to implement a combinatorial function g, wherein the second combinatorial circuit is configured to receive binary states z[1](t), . . . , z[n](t), and output a value u(t), wherein the combinatorial function g determines output u(t) as a function of binary states z[1](t), . . . , z[n](t).