Patent ID: 8327073

Claim:
A method of data processing in a data processing system including a plurality of lower level caches coupled by an interconnect fabric, wherein the plurality of lower level caches includes first, second and third lower level caches, wherein the first lower level cache is associated with a first processing unit having a first processor core and an associated first upper level cache and the second lower level cache is associated with a second processing unit having a second processor core and an associated second upper level cache, said method comprising: receiving via the interconnect fabric at the second lower level cache a lateral castout (LCO) command issued by the first lower level cache, wherein the LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates the second lower level cache as a single intended destination of the victim cache line out of the plurality of lower level caches; in response to receiving the LCO command, the second lower level cache determining whether to accept the victim cache line from the first lower level cache based at least in part on whether or not the address of the victim cache line indicated by the LCO command falls within a guest LCO address region including addresses assigned to multiple different congruence classes of the second lower level cache; in response to determining not to accept the victim cache line, providing a coherence response to the LCO command refusing the identified victim cache line; and in response to determining to accept the victim cache line, updating an entry of the second lower level cache corresponding to the identified victim cache line.