Patent ID: 8325518

Claim:
A multi-level cell (MLC) NOR flash memory device, comprising: a plurality of gate lines separated from a semiconductor substrate by a gate insulating layer, wherein the gate lines each have a metal silicide layer; a plurality of source regions and a plurality of drain regions formed in the semiconductor substrate and between the gate lines; a plurality of source lines connected to a portion of the source regions and each being of a sheet resistance of 100 to 300 ohm/sq; a plurality of bitlines perpendicular to the source lines and each electrically connected to the drain regions through a plurality of drain contacts; and a plurality of power lines parallel to the bitlines and each electrically connected to the source lines through a plurality of source contacts, wherein 16 said bitlines are disposed between two adjacent ones of the power lines; a plurality of NOR flash memory cells, each of the NOR flash memory cells having a high transconductance and reduced parasitic capacitance.