Patent ID: 7257698

Claim:
An instruction buffer for a pipeline processor comprising: a sequence of instructions arranged in an order determined beforehand, wherein respective instructions of said sequence of instructions may include dependencies on other instructions of said sequence of instructions and wherein respective ones of said dependencies may be canceled upon issuance or execution of corresponding ones of said other instructions of said sequence of instructions; a first buffer including entries arranged in a preselected entry number order for storing respective instructions of said sequence of instructions; and a second buffer including other entries for storing instructions, wherein an instruction having no uncanceled dependencies, and thus capable of execution, stored in any one of said other entries earlier than other instructions is issued earlier than said other instructions stored in entries of said second buffer, wherein any one instruction of said sequence of instructions stored in any one of the entries of the first buffer designated by a relatively lower entry number than another instruction in another entry is prior, in order, to another instruction stored in another entry of the first buffer and containing an instruction designated by a relatively higher entry number than said one instruction of said sequence of instructions; and wherein said first and second buffers are each operable to concurrently issue, in said storage entry number order in a respective one of said first buffer and said second buffer, instructions having no uncanceled dependencies and which are thus capable of execution, wherein the entries of the first buffer each show whether or not the instruction stored therein is ready to be issued, and wherein the instruction first issued from among the entries of the first buffer whose instructions are ready to be issued is the entry having a lowest storage entry number among said entries of the first buffer whose instructions are ready to be issued.