Patent ID: 8158984

Claim:
A thin film transistor (TFT), comprising: a buffer layer on a substrate; a crystalline semiconductor pattern on the buffer layer; a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein; a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes; an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein; and source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes, wherein: the semiconductor pattern access hole partially exposes the crystalline semiconductor pattern, and the exposed crystalline semiconductor pattern is in contact with the interlayer insulating layer through the semiconductor pattern access hole.