Patent ID: 7579968

Claim:
A data processing circuit, comprising an encoder circuit for encoding an input data word that comprises a plurality of digits wherein each digit has a value selected from at least three available digit values for controlling a signal level in multi-level encoding scheme that uses more than two levels, the encoder circuit being arranged to define at least two digit maps, each digit map defining assignments of each of the available digit values to a respective output digit value, each digit map mapping to a common set of output digit values; select at least two groups of digits within the input data word, each group associated with a respective one of the digit maps, the groups being selected under a constraint that each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values, which occur in the data word wherein the data word will satisfy predetermined criteria; generate a data signal that represents the input data word by information that identifies the selected groups and an output data word obtained by mapping the digits of each group in the input data word according to the digit map for that group.