Patent ID: 7277341

Claim:
A semiconductor memory device, comprising: first and second sense nodes which are provided corresponding to first and second bit lines; and a sense amplifier which is connected to the first and second sense nodes and senses data read out from a memory cell, wherein the sense amplifier includes: an initial sense circuit which increases a potential difference between the first and second sense nodes in a first period after beginning sense operation; and a latch circuit which increases and holds the potential difference between the first and second sense nodes in a second period after the first period, wherein the initial sense circuit includes: first and second transistors of first conductive type, of which both gates are connected to each other and which forms a current mirror circuit which flows current in proportion to each other to the first and second sense nodes; third and fourth transistors of first conductive type, of which both gates are connected to each other and which forms a current mirror circuit which flows current in proportion to each other to the first and second sense nodes; and fifth and sixth transistors of first conductive type, of which both gates are connected to each other and which forms a current mirror circuit which controls operation of the first to fourth transistors, wherein the latch circuit includes: seventh and eighth transistors of first conductive type which are connected in cascade between the first and second sense nodes, of which one gate is connected to the second sense node, and of which the other gate is connected to the first sense node; and ninth and tenth transistors of second conductive type which are connected in cascade between the first and second sense nodes, of which one gate is connected to the second sense node, and of which the other gate is connected to the first sense node.