Patent ID: 7289371

Claim:
A semiconductor memory device, comprising: a memory cell array in which a plurality of nonvolatile memory cells are arranged, the nonvolatile memory cells each having input and output terminals and a control terminal; bit lines connected with the input and output terminals of the plurality of memory cells by a virtual grounding scheme; word lines connected with the control terminals of the memory cells; a word line selecting circuit selecting one of the word lines; a write voltage applying circuit applying voltages to the bit lines associated with the memory cells; and a write voltage control circuit controlling the write voltage applying circuit such that for each of memory cells, to which writing is to be carried out at the same time, of all the memory cells connected with the word line selected by the word line selecting circuit, different voltages are applied to two bit lines associated with the memory cell, while for each of other memory cells, to which writing is not to be carried out, a same voltage is applied to two bit lines associated with the memory cell.