Patent ID: 7036002

Claim:
An unpredictable microprocessor or microcomputer comprising: three distinct locations each for receiving memory; in a first location, a main memory including an operating system, a main program, and a secondary program, wherein said secondary program is not related to the main program; in a second location, a first RAM-type working memory; in a third location, a second RAM-type working memory; a processor adapted to execute instructions from one or more of said main memory, said first working memory and said second working memory; a bus connecting the processor to the main memory, the first working memory and the second working memory; switching means for making said processor unpredictable, said switching means unpredictably jumping, while the programs are running, from one of the two working memories to the other working memory while saving the contents of the two working memories, said switching means comprising: access registers associated with each of the main memory, the first working memory and the second working memory; at least one first block of registers that stores the operating context of the programs in the main memory; and a switching circuit that enables one of the working memories and controls the access registers associated with each of the main memory, the first working memory and the second working memory.