Patent ID: 7254075

Claim:
An integrated circuit memory device, comprising: a storage array having a first and second row of storage cells; and a row of sense amplifiers including a first plurality of sense amplifiers and a second plurality of sense amplifiers, coupled to the storage array, to access the first and second rows of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein: during the first mode of operation, the integrated circuit memory device has a first bank count and a first page size, and a first plurality of data is transferred from the first row of storage cells to the row of sense amplifiers, and during the second mode of operation, the integrated circuit memory device has a second bank count and a second page size, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers, and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers, wherein the second bank count is greater than the first bank count and the first page size is larger than the second page size.