Patent ID: 7229890

Claim:
A method for forming an integrated circuit, comprising: forming at least one transistor within a substrate; forming at least one capacitor in an insulative layer supported by the substrate, comprising: forming a first electrode comprising: removing a first portion of the insulator layer to form an opening; forming a first layer of undoped silicon in the opening, the first layer depositing on a bottom interface and a sidewall interface in the opening; forming a layer of doped silicon on the first layer of undoped silicon; forming a second layer of undoped silicon on the doped layer of silicon; removing selected portions of the insulative layer to expose at least a portion of the sidewall interface of the first layer of undoped silicon; seeding the first and second undoped silicon layers using an environment that includes a hydride gas and a seeding species to form a seeded silicon coating; preventing silicon buildup on the insulative layer during seeding by adding chlorine to the environment after stabilization of the hydride flow; annealing the seeded silicon layers to convert the first and second undoped silicon layers to HSG; forming a second electrode separated from the first electrode by a dielectric region; and coupling at least one capacitor to at least one transistor.