Patent ID: 7199413

Claim:
A memory device, comprising: an array of memory cells, wherein each memory cell comprises: a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed in a substrate having a second conductivity type opposite the first conductivity type; a control gate formed overlying the ferroelectric layer; a first source/drain region having the first conductivity type formed in the first well region; a second source/drain region having the first conductivity type formed in the first well region; a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions; and a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate; a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates; a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions; a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their second well regions; a row decoder coupled to the array of memory cells; and a column decoder coupled to the array of memory cells.