Patent ID: 8189792

Claim:
An apparatus comprising: a processor having dedicated logic including first and second datapaths each of a first bit width, wherein the first and second datapaths are to execute a cryptographic algorithm of a second bit width at least twice the first bit width, wherein each datapath includes: input logic to receive input data of the first bit width and to provide at least some of the input data to the input logic of the other datapath; first selection logic coupled to the input logic to receive and select a first byte or a second byte of the input data; a plurality of substitution boxes (SBox) coupled to the first selection logic to receive a pair of columns of the input data and to perform non-linear substitutions; second selection logic coupled to the SBoxes to receive and select an output from a corresponding SBox or a byte of the input data; mix logic coupled to the second selection logic and the SBoxes to mix the pair of columns to generate a mixed pair of columns; key operation logic coupled to the mix logic to receive the mixed pair of columns and a round key and to transform the mixed pair of columns into a temporary result using the round key; and a bus coupled between the first datapath and the second datapath, wherein the bus is of a third bit width, the third bit width less than the first bit width, wherein the bus is to transfer data of a fourth bit width from the first datapath to the second datapath and vice versa and the dedicated logic is to perform an advanced encryption standard (AES) algorithm of at least the second bit width.