Patent ID: 7655554

Claim:
A method of processing an integrated circuit wherein a loading effect is reduced, the method comprising: providing a substrate, the substrate being characterized by a first thickness; forming an inter metal dielectric layer overlaying the substrate, the inter metal dielectric layer being characterized by a second thickness; forming a first photoresist layer overlaying the inter metal dielectric layer, the first photoresist layer being associated with a first pattern; forming a first opening positioned at least partially inside the inter metal dielectric layer, the first opening being characterized by a first depth; removing the first photoresist layer; forming a via plug, the via plug being positioned in side the first opening, the via plug being characterized by a first plurality of dimensions, the first plurality of dimensions comprising a first height and a first width, the first height being less than or equal to the first depth; forming a first filling layer overlaying the first opening; forming a second photoresist layer overlaying the first filling layer, the second photoresist layer being associated with a second pattern; forming a second opening positioned at least partially inside the inter metal dielectric layer, the second opening being characterized by second plurality of dimensions, the second plurality of dimensions comprising a second depth and a second width, the second depth being less than the first depth, and removing the via plug and the second photoresist layer.