Patent ID: 8581399

Claim:
A semiconductor device, comprising: a substrate comprising a major surface; and a plurality of metal bumps on the major surface, wherein each of the plurality of metal bumps comprises: a metal via on the major surface, and a metal pillar on the metal via, the metal pillar electrically connected to the metal via, each of the metal bumps of the plurality of metal bumps having an overlay offset between the metal pillar and the metal via, wherein the overlay offset is a distance between a centroid of the metal pillar and a centroid of the metal via, wherein the overlay offset of a first metal bump of the metal bumps is a first overlay offset, the overlay offset of a second metal bump of the metal bumps is a second overlay offset, the second metal bump is farther than the first metal bump to a centroid of the substrate, the second overlay offset is greater than the first overlay offset, and a difference between the second overlay offset and the first overlay offset ranges from about 1 to 20 μm.