Patent ID: 8835990

Claim:
A three-dimensional memory array, comprising: a plurality of word line layers, each having a plurality of word lines and a plurality of gaps arranged alternately along a first direction, the gaps comprising a first group of gaps and a second group of gaps arranged alternately; a first bit line layer, disposed above the word line layers and having a plurality of first bit lines arranged along a second direction, the second direction being perpendicular to the first direction; a first conductive pillar array, extending through the word line layers and electrically connected to the first bit line layer, the first conductive pillar array comprising a plurality of first conductive pillars disposed in the first group of gaps, wherein a first memory element is disposed between a first conductive pillar and a word line of the word line layer adjacent to the first conductive pillar; a second bit line layer, disposed below the word line layers and having a plurality of second bit lines arranged along the second direction; and a second conductive pillar array, extending through the word line layers and electrically connected to the second bit line layer, the second conductive pillar array comprising a plurality of second conductive pillars disposed in the second group of gaps, wherein a second memory element is disposed between a second conductive pillar and a word line of the word line layer adjacent to the second conductive pillar, wherein the three-dimensional memory array further comprises a plurality of conductive plugs each disposed on the corresponding first conductive pillar and located between the corresponding first conductive pillar and the first bit line layer, wherein the first conductive pillar array is electrically connected to the first bit line layer through the conductive plugs.