Patent ID: 8203897

Claim:
A semiconductor device, comprising: a plurality of test mode control units; a plurality of test mode signal transmission lines interlaced between data input/output lines and coupled to the plurality of test mode control units, wherein the plurality of test mode signal transmission lines are configured to transmit respective test-mode signals to respective ones of the plurality of test mode control units; a plurality of internal circuits configured to perform test operations or normal operations by controlling respective ones of the plurality of test mode control units; and a test-off signal transmission line configured to transmit test-off signals to respective ones of the plurality of test mode control units, the plurality of test mode control units configured to control the test operations of respective ones of the plurality of internal circuits to be disabled in response to a test-off signal received through the test-off signal transmission line; wherein, in response to the test-off signal being activated, the plurality of test mode control units disable the test operations of respective ones of the plurality of internal circuits regardless of logic levels of the test mode signals.