Patent ID: 7937570

Claim:
A data processing system comprising: a processor; a memory coupled to the processor and including a plurality of physical locations having real addresses for storing data; an instruction fetch unit (IFU) that provides instructions, from within an instruction set architecture (ISA) supported by the processor, to the processor for execution, wherein said instructions include: (1) an asynchronous memory move (AMM) store (ST) instruction that the processor executes to perform the following functions: initiating an AMM operation that moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) performing a move of the data in virtual address space utilizing a source effective address that is memory mapped to the first memory location and a destination effective address that is memory mapped to the second memory location; and (b) when the move in virtual address space is completed, triggering a memory controller to complete a physical move of the data to the second memory location, wherein the physical move occurs independent of the processor; and (2) an AMM terminate ST instruction for stopping an ongoing AMM operation before completion of the AMM operation.