Patent ID: 7253755

Claim:
An analog-to-digital converter (“ADC”) architecture comprising: an ADC comprising a positive input for a composite analog signal having a predictable strong signal component combined with a weak signal component, a negative input for a second analog signal, and an ADC output, said ADC being configured to generate a first digital output at said ADC output, said first digital output being generated in response to said composite analog signal and said second analog signal, and said first digital output being a digital representation of the weak signal component; a processor having an input coupled to said ADC output, and having a first output for a digital adjustment signal, said processor comprising a waveform prediction module configured to determine predictable signal characteristics of said strong signal component, to generate a digital representation of the strong signal component for combining with said first digital output, and to generate said digital adjustment signal in response to said predictable signal characteristics; and a digital-to-analog converter (“DAC”) coupled between said first output of said processor and said negative input of said ADC, said DAC being configured to generate said second analog signal in response to said digital adjustment signal.