Patent ID: 8661370

Claim:
A computer system having a processor operatively interconnected to a memory device, a graphical display device, a user input device, and a graphical user interface displayed in the graphical display device, allowing the computer system to implement the method of optimization of a manufacturing process of an integrated circuit or IC layout, the method comprising: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns; wherein the steps of receiving input and organizing IC patterns are performed prior to selecting IC patterns and the step of organizing IC patterns includes a condition to be satisfied of the IC patterns and said IC patterns are organized in clusters of similar patterns such that at least one pattern is selected from each cluster; and the input upon which said clusters are organized comprises: a set P of IC patterns S 1 , . . . S P extracted from the IC layout and a set F of features F 1 , . . . F P , respectively associated to the IC patterns of the set P; and a distance function D(F i , F j ) for evaluating a distance d=D(F i , F j ) between two IC patterns S i , S j , based on respective features F i , F j thereof, such that a distribution of pairs I 0 (d) can be determined, wherein the pairs I 0 (d) are of IC patterns of the set P with respect to a distance d between the pairs.