Patent ID: 7707560

Claim:
A computer-implemented method comprising: retrieving an instruction; determining whether the instruction is ready to execute; storing performance characteristics that include an instruction cycle counter value and a line location value in response to determining that the instruction is ready to execute, wherein the instruction cycle counter value is a last digit of an instruction clock cycle, and wherein the line location value signifies a location on a page line at which to display the instruction cycle counter value; storing performance characteristics that include a stalled instruction identifier and the line location value in response to determining that the instruction is not ready to execute; and generating a performance graph using the performance characteristics, wherein the generation comprises: displaying the instruction cycle counter value at the location on the page line corresponding to the line location value in response to the instruction being ready to execute; and displaying the stalled instruction identifier at the location on the page line corresponding to the line location value in response to the instruction failing to be ready to execute.