Patent ID: 8173539

Claim:
A method for fabricating a metal redistribution layer, comprising: providing a semiconductor structure with a dielectric layer formed thereon; forming a first opening and a second opening in the dielectric layer over a first region and a second region thereof, respectively, wherein the second region is outside of the first region; forming a plurality of third openings in the dielectric layer exposed by the first opening in the first region and a plurality of fourth openings in portions of the dielectric layer exposed by the second opening in the second region; forming a metal material over the dielectric layer and in the first, second, third and fourth openings, wherein the metal material fills the third and fourth openings, and substantially fills the first and second openings, and a plurality of recesses are formed in the metal material overlying the third and fourth openings; and patterning the metal material in the first region by using the recesses formed in the metal material overlying the fourth openings in the second region as an alignment mark, forming a metal redistribution layer over the dielectric layer and in the first and third openings in the first region.