Patent ID: 7161830

Claim:
A nonvolatile memory apparatus comprising: a nonvolatile memory array; a command terminal; a data terminal; a clock terminal; a first circuitry; and a control circuit which is coupled to a program memory which stores a program, wherein said command terminal is coupled to said first circuitry and receives commands which include a read command, a program command and an erase command, wherein said clock terminal receives a clock signal, wherein said data terminal, which is a different terminal from said command terminal, inputs data in response to said clock signal and outputs data in response to said clock signal, wherein said program includes a plurality of operation steps, wherein first operation steps have a plurality of instructions for performing a read operation in response to said read command, wherein second operation steps have a plurality of instructions for performing a program operation in response to said program command, wherein third operation steps have a plurality of instructions for performing an erase operation in response to said erase command, wherein said first circuitry issues a signal for selecting one of said plurality of operation steps in accordance with a received command received from said command terminal, wherein in said read operation in response to said read command, said control circuit controls, based on said first operation steps, reading data from said nonvolatile memory array, and outputting said data via said data terminal, wherein in said program operation in response to said program command, said control circuit controls, based on said second operation steps, receiving data via said data terminal, and storing said data into said nonvolatile memory array, and wherein in said erase operation in response to said erase command, said control circuit controls, based on said third operation steps, erasing data stored in said nonvolatile memory array.