Patent ID: 7698666

Claim:
A computer implemented method for model-based layout of an integrated circuit design, comprising: using computer system which comprises at least a processor and is programmed for: identifying a layout object to process for a least a portion of the integrated circuit design; accessing one or more models relating to manufacturing of the integrated circuit design; analyzing the layout object using the one or more models to identify a plurality of configurations for the layout object; optimizing the layout based at least in part upon the act of analyzing the layout object to ensure compliance with one or more design rules without requiring performing design rule checking for the at least the portion of the integrated circuit design, wherein the act of optimizing the layout comprises modifying a first design rule for the at least the portion of the integrated circuit to allow for a layout characteristic that is not permitted by the first design rule before modification; and storing at least some of the plurality of configurations in a computer readable storage medium or a computer storage device or displaying the at least some of the plurality of configurations on a display device of the computer system.