Patent ID: 7557605

Claim:
A system comprising: a plurality of programmable logic blocks; a plurality of special-purpose blocks; a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, wherein the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system; a memory controller operatively connected to the plurality of special-purpose blocks and the plurality of programmable logic blocks using the high-speed mesh interconnect fabric, wherein the memory controller is configured to transfer data between an external memory and at least one selected from a group consisting of the plurality of special-purpose blocks and the plurality of programmable logic blocks; and a general purpose input/output block operatively configured to transfer data between the external memory and at least one selected from a group consisting of the memory controller, the plurality of special-purpose blocks, and the plurality of programmable logic blocks, wherein the general purpose input/output block comprises: a converter for executing a double data rate to single data rate conversion of the transferred data; a transmit delay lock loop for de-skewing source-synchronous signals associated with the transferred data; a receive delay lock loop for de-skewing source-synchronous signals associated with the transferred data; and error correcting code logic for error detection and error correction of the transferred data.