Patent ID: 7289373

Claim:
A memory device comprising: a memory array having a plurality of memory cells; a plurality of word lines and a plurality of bit lines via which the plurality of memory cells are accessed; multiplexer logic having a plurality of inputs and an output, each input connected to one of said plurality of bit lines, and said output being connected to one of said inputs dependent on a multiplexer control signal; decoder logic, responsive to an address, for producing said multiplexer control signal and for selecting one of said word lines, whereby a particular memory cell in said memory array identified by the address has its associated bit line connected to said output of the multiplexer logic; sense amp logic coupled to said output of the multiplexer logic and having a precharge node used during a sensing operation to detect a stored data state of said particular memory cell; control logic for initiating the sensing operation and for causing the precharge node of the sense amp and at least the bit line associated with the particular memory cell to be precharged in a precharge operation prior to said sensing operation; and isolation logic provided between said output of the multiplexer logic and said precharge node of the sense amp logic to isolate said precharge node from the capacitance of said output of the multiplexer logic during said sensing operation.