Patent ID: 8255752

Claim:
A clock domain check method which performs a clock domain check in a circuit to be checked using a central processing unit, the method comprising: a first step of allowing a stationary signal defined as a signal whose logic value does not change in an asynchronous transfer to propagate through the circuit to be checked; a second step of extracting a combination in which different asynchronous transfers occur between a transmitting side register and a receiving side register; a third step of extracting a circuit to be checked from the combination of asynchronous transfers extracted in the second step by back-tracing for each of the receiving side registers toward the transmitting side and searching the transmitting side register, a circuit that leads to the transmitting side register, and a stationary signal, and excluding a synchronization circuit of a plurality of signals from the circuit to be checked; a fourth step of allowing a stationary signal for each combination among all combinations of logic values “1” and “0” of the stationary signal to propagate through the circuit to be checked; a fifth step of checking, from the connection relation, whether or not there exists one asynchronous transmitting side register to which signal change logically reaches, in the combination of logic values of the stationary signal propagated in the fourth step; and a sixth step of determining, based on the check result in the fifth step, whether or not the circuit configuration relating to asynchronous transfer is appropriate as a synchronization circuit for a single-signal transfer, wherein the first to sixth steps are executed by the central processing unit.