Patent ID: 7570100

Claim:
An integrated circuit comprising: A. a first power output lead at a first voltage, the first power lead carrying power to operate the integrated circuit; B. a second power output lead at a second voltage different from the first voltage; C. operating circuitry having a power input lead receiving power to operate the circuitry; and D. header switch circuitry including: i. a PMOS transistor switch having source/drain leads connected to the first power output lead and the power input lead and having a gate lead, when conductive the PMOS transistor conducting power from the first power output lead to the power input lead; ii. potential adjust circuitry having a first lead connected to the first power output lead, a control input, an output lead connected to the gate lead of the PMOS transistor switch, and a second lead connected to the second power output lead, the adjust circuitry including a series connection of a PMOS transistor, a first NMOS transistor, and a second NMOS transistor between the first and second power output leads, the control input being connected to the gates of the series connected transistors, and the output lead being connected to the connection between the PMOS transistor and the first NMOS transistor; and iii. rate adjust circuitry including a third NMOS transistor having source/drain leads connected between the connection of the second and third NMOS transistors and the second power output lead, and having a gate lead connected to the power input lead.