Patent ID: 8639860

Claim:
A data transfer system comprising: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein, in a case in which an interrupt factor occurs in the peripheral device, the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Direct Memory Access) transfer, and the processor reads out the data transferred by the DMA transfer to the memory region without accessing the peripheral device in response to an interrupt request signal from the peripheral device requesting execution of a predetermined interrupt operation, wherein after storing transfer notification data that notifies the DMA transfer has been performed in the register set, the peripheral device transfers data stored in the register set and including the transfer notification data to the memory region by the DMA transfer, and the processor reads out the transfer notification data transferred to the memory region by the DMA transfer, determines whether the peripheral device has performed the DMA transfer or not, based on the read out transfer notification data, and does not read out other data transferred to the memory region by the DMA transfer, when the peripheral device has not performed the DMA transfer, and wherein when reading out the data transferred to the memory region by the DMA transfer ends, the processor performs control to reset the transfer notification data stored in the memory region, and sends an end notification signal that notifies the end to the peripheral device, and in response to the end notification signal, the peripheral device resets the transfer notification data stored in the register set.