Patent ID: 7882338

Claim:
A system for performing an implicit predicted return from a predicted subroutine in a processor, the system comprising: a branch history table/branch target buffer (BHT/BTB) to hold branch information, wherein the branch information includes a target address of a predicted subroutine and a branch type; instruction buffers to buffer fetched instructions; and instruction fetch controls (IFC) for performing a method comprising: fetching a branch instruction at a branch address and a return-point instruction at an address subsequent to the branch address; receiving the target address of the predicted subroutine and the branch type associated with the branch address via the BHT/BTB; fetching a fixed number of instructions starting at the target address of the predicted subroutine in response to the branch type indicating that the predicted subroutine is a fixed-length subroutine; and referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction: and wherein the fixed-length subroutine is associated with only a single row in the BHT/BTB.