Patent ID: 8407714

Claim:
An arithmetic device, comprising: an instruction execution circuit configured to execute a multi-thread mode in which the instruction sequences of a plurality of threads are concurrently executed and a single thread mode in which the instruction sequence of a single thread is executed, configured to reassign hardware resources to a single thread when executing in the single thread mode and divide the hardware resources between the threads active when executing in the multi-thread mode, and configured to place in an offline state an erroneous thread in which a hardware error has occurred during the execution of instruction sequence of the thread when the error is detected; and a switch indication circuit having a thread mode control circuit configured to store a state of a thread in the offline state as an inactive state in a state storage device for storing a state of a thread, and further configured to issue an indication to the instruction execution circuit to switch between the multi-thread mode and the single thread mode depending on the change of the number of threads in the active state, the switch indication circuit including, for each thread an offline control circuit configured to instruct the instruction execution circuit to place the erroneous thread in the offline state upon receipt of an error notification from the instruction execution circuit that a hardware error has been detected, for each thread a suspend control circuit configured to instruct the instruction execution circuit to place a thread that has executed a suspend instruction in a suspend state upon receipt of a suspend notification from the instruction execution circuit that the suspend instruction has been executed, the thread mode control circuit configured to receive an offline notification from the offline control circuit that the erroneous thread has been placed in the offline state and stores a state of the thread that has entered the offline state as an inactive state in the state storage device, and configured to instruct the instruction execution circuit to switch from the multi-thread mode to the single thread mode when the number of threads in the active state changes from 2 or more to 1 or less, the thread mode control circuit further configured to store a state of the thread in the suspend state as an inactive state in the state storage device upon receipt of a suspend notification from the suspend control circuit that the thread has been placed in the suspend state when executing in the multi-thread mode, and the thread mode control circuit further configured to store a state of the thread in the suspend state as an active state in the state storage device upon receipt of a suspend notification from the suspend control circuit that the thread has been placed in the suspend state when executing in the single thread mode to keep in an active state a thread which has executed a suspend instruction in the single thread mode and has been placed in the suspend state.