Patent ID: 7477046

Claim:
A circuit of an output stage of an LDO voltage regulator implemented with low-voltage devices and still allowing higher voltage levels is comprising: a low-voltage NMOS pass device having its source connected to its bulk and to an output port of said LDO, its gate is controlled by said LDO voltage regulator, its drain is connected to a means of controllable resistance; said means of controllable resistance protecting actively a voltage level at the drain of said NMOS pass device is implemented between the drain of said first NMOS pass device and V DD voltage; a first voltage limiting means implemented in parallel to said NMOS pass device; and a second voltage limiting means implemented in parallel to said means of controllable resistance wherein said second voltage limiting means is a Zener diode and wherein said Zener diode has a maximal threshold voltage corresponding to a maximal tolerble voltage level of said pass device.