Patent ID: 7718546

Claim:
A method for fabricating a 3-D monolithic memory device, comprising: patterning a first silicon-oxynitride layer in a layered structure to provide a first patterned silicon-oxynitride layer, the layered structure includes a first amorphous carbon layer below the first silicon-oxynitride layer, and a first oxide layer below the first amorphous carbon layer; patterning the first amorphous carbon layer using the first patterned silicon-oxynitride layer to provide a first patterned amorphous carbon layer; patterning the first oxide layer using the first patterned amorphous carbon layer to provide a first patterned oxide layer; forming a first set of conductive rails in the first patterned oxide layer, the first set of conductive rails is in a particular level of the 3-D monolithic memory device; forming a first polycrystalline layer above the first set of conductive rails; patterning the first polycrystalline layer to provide a first plurality of pillars which are electrically coupled from below to the first set of conductive rails, the first plurality of pillars comprise diodes in the particular level of the 3-D monolithic memory device; forming a second oxide layer above the first plurality of pillars, a second amorphous carbon layer above the second oxide layer, and a second silicon-oxynitride layer above the second amorphous carbon layer; patterning the second silicon-oxynitride layer to provide a second patterned silicon-oxynitride layer; patterning the second amorphous carbon layer using the second patterned silicon-oxynitride layer to provide a second patterned amorphous carbon layer; patterning the second oxide layer using the second patterned amorphous carbon layer to provide a second patterned oxide layer; and forming a second set of conductive rails in the second patterned oxide layer, the first plurality of pillars are electrically coupled from above to the second set of conductive rails.