Patent ID: 7795072

Claim:
A computer-implemented method for modeling a high-performance, high I/O ball grid array substrate, intended for integrated circuit flip-chip assembly and having a first and a second metal layer and one intermediate insulating layer, all of substantially equal areas comprising the steps of: modeling the structure of said first metal layer as electrical ground potential, said layer having a plurality of electrically insulated openings for electrical contacts; modeling the structure of said second metal layer as a plurality of electrical signal lines, a plurality of first electrical power lines operable at a first potential, and a plurality of second electrical power lines operable at a second potential; configuring said power lines so wide that their combined inductances approximate the inductance of a metal having the size of the total substrate; concurrently distributing said first power lines among said signal lines in order to provide at least minimum inductive coupling between signal and power lines, thereby obtaining high mutual inductances and minimizing effective self-inductance.