Patent ID: 8183112

Claim:
A method for fabricating a semiconductor device with a vertical channel, the method comprising: providing a substrate having a plurality of hard mask patterns arranged in a first direction and a second direction crossing the first direction; etching the substrate using one hard mask pattern as an etch mask to form an upper pillar portion; forming a spacer on a sidewall of the upper pillar portion; etching the substrate using one hard mask pattern and the spacer as an etch mask to form a lower pillar portion connected to the upper pillar portion, wherein the upper pillar portion and the lower pillar portion constitute a pillar, a plurality of pillars being arranged in the first and the second directions; recessing a sidewall of the lower pillar portion using the spacer as an etch barrier; forming a gate electrode surrounding a circumferential surface of the recessed lower pillar portion; forming a bit line impurity region in the substrate between a pair of neighboring pillar lines, each pillar line including pillars arranged in the first direction; forming a trench penetrating the bit line impurity region in the substrate between the pair of neighboring pillar lines to define a buried bit line which extends in the first direction and surrounds the pillars of the pair of neighboring pillar lines, wherein a first resultant structure is formed; forming a word line which extends in the second direction and is connected to the gate electrode, wherein a second resultant structure is formed; forming a fourth insulation layer over the second resultant structure; planarizing the fourth insulation layer until the upper pillar portion is exposed; and forming a storage electrode over the exposed upper pillar portion, wherein the storage node directly contacts the exposed upper pillar portion.