Patent ID: 7957178

Claim:
An integrated circuit (IC) including an array of memory cells, each memory cell in said array comprising: a core storage element having at least a first storage node, and a first pass gate coupled to said first storage node; a single bitline (BL) coupled to said each memory cell, said BL also coupled to a node in a source drain path of said first pass gate; said BL for both Reading data from and Writing data to said first storage node; wherein said core storage element includes a complementary second storage node or said cell includes inversion circuitry for outputting an inverted voltage relative to a voltage at said first storage node; a buffer circuit comprising a second pass gate and a driver transistor, wherein said second pass gate and said driver transistor are coupled to said source drain path of said first pass gate, wherein said second pass gate is coupled between said BL and said driver transistor, and wherein a gate of said driver transistor is coupled to said second storage node or an output of said inversion circuitry, and at least a first wordline (WL) coupled to said first pass gate and said second pass gate.