Patent ID: 7912169

Claim:
A synchronization device comprising a plurality of receiver circuits on a plurality of channels, each receiver circuit receiving input serial data on an associated channel, subjecting the received serial data to a serial-to-parallel conversion, and outputting parallel data, wherein said receiver circuit on each of the plurality of channels includes: a circuit for bringing a phase of a clock signal used at least in the serial-to-parallel conversion into conformity with a phase of an internal clock signal, said internal clock signal is supplied to said receiver circuit and adjusted for skew at a clock input terminal of said receiver circuit on each of the plurality of channels, to attain synchronization among the plurality of channels; a clock-and-data recovery circuit for generating a data signal and a recovery clock signal from received serial data and a serial-to-parallel converter circuit for subjecting the data signal output from said clock-and-data recovery circuit to a serial-to-parallel conversion based upon a frequency-divided clock signal obtained by frequency-dividing the recovery clock signal; and a register array for holding the parallel data signal, which has been obtained by a conversion in said serial-to-parallel converter circuit, from a moment of detection of a frame pattern in said receiver circuit to a moment of detection of a frame pattern on a channel on which the frame pattern was detected last, and byte-aligned or word-aligned parallel data signals are output in unison from said receiver circuits on the plurality of channels in synchronization with a timing at which the frame pattern was detected on the channel on which the frame pattern was detected last.