Patent ID: 8452006

Claim:
A cryptography processor comprising: one or more arithmetic logic units (ALUs); and a plurality of data registers, wherein the processor is adapted to: receive an a-bit-long block of data, wherein the block of data is organized as a/n n-bit words; store the a/n n-bit words as a state in the data registers, wherein the state is a matrix having b>1 rows and c>1 columns of p-bit state elements, wherein: a, n, p, b, c, and a/n are positive integers; p≧9; p>n; a/n>1; each n-bit word of data is stored in a corresponding p-bit state element; and b*c*n=a; and perform a column-mixing transformation on the state using the one or more ALUs, wherein the column-mixing transformation involves generating finite-field products using bit-shifting and XOR operations.