Patent ID: 8629702

Claim:
A clock regenerator for generating a stabilized output clock signal (CLK out ), the clock regenerator comprising: a sampling unit ( 110 ) configured to receive an input clock signal (CLK in ) having a varying period time, receive a sampling clock signal (CLK smpl ) and sample the input clock signal (CLK in ) based on the sampling clock signal (CLK smpl ) to produce a respective period length value (PL) for each period of the input clock signal (CLK in ), the sampling clock signal (CLK smpl ) having a frequency being substantially higher than an average frequency of the input clock signal (CLK in ); an averaging unit ( 120 ) configured to receive a number of period length values (PL) from the sampling unit ( 110 ) and based thereon produce an average period length value (PL avg ) representing an average period time for the input clock signal (CLK in ) over an averaging interval including a number of periods equivalent to said number of period length values (PL); an output unit ( 150 , 151 ) configured to produce the stabilized output clock signal (CLK out ) based on the average period length value (PL avg ) and the sampling clock signal (CLK smpl ); and an accumulator unit ( 130 ) configured to receive each average period length value (PL avg ) and based thereon produce a value (TPV) indicating a time point at which a given pulse of the stabilized output clock signal (CLK out ) shall be generated.