Patent ID: 6913980

Claim:
A method of forming a transistor comprising: forming a first oxide layer over a gate structure and portions of a substrate not covered by the gate structure, where portions of the substrate not covered by the gate structure have source/drain extension regions and halo regions formed therein; forming a nitride layer over the first oxide layer; forming a second oxide layer over the nitride layer; processing the second oxide layer and nitride layer to form oxide sidewall spacers having a portion of nitride material there-under adjacent the gate structure; processing the oxide sidewall spacers such that they are reduced in size relative to the underlying portions of nitride material; doping regions of the substrate adjacent the gate structure with a first dopant to form source and drain regions within the substrate, the first dopant being substantially blocked by the oxide sidewall spacers and the underlying portions of nitride material; and doping regions of the substrate adjacent the gate structure with a second dopant to form first and second compensation regions within the substrate, the second dopant being substantially blocked by the oxide sidewall spacers.