Patent ID: 7362634

Claim:
A memory device, comprising: a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals; a memory array from which data are read and to which data are written at locations corresponding the address signals responsive to the memory control signals; a data path extending between a plurality of externally accessible data bus terminals and the memory array, the data path including a data input register through which write data signals are coupled from the data bus terminals to the memory array and a data output register through which read data signals are coupled from the memory array to the data bus terminals, the read data signals being coupled to the data bus terminals and a data strobe signal being coupled to a data strobe terminal responsive to a clock signal being coupled though a clock tree; and a built-in test system for determining a timing parameter of the memory device, the test system comprising: an oscillator generating a periodic clock signal, the clock signal being applied to the clock tree; a test signal generator generating a plurality of test signals, the test signals being coupled to respective ones of the data bus terminals and to the data strobe terminal responsive to respective ones of the clock signals coupled through the clock tree; a selector coupled to at least one of the data bus terminals and the data strobe terminal of the memory device, the selector being operable responsive to a control signal to output one of the test signals applied to the respective data bus terminal or the data strobe terminal; a selector control device operable to generate the control signal for the selector; a multi-phase signal generator coupled to receive the test signal output from the selector, the multi-phase signal generator being operable to output a plurality of multi-phase signals that are delayed from the received test signal by respective delay times that are different from each other; and a plurality of phase detectors each of which is coupled to receive a first one of the test signals coupled to the data bus terminals and the data strobe terminal of the memory device and a respective one of the multi-phase signals from the multi-phase signal generators, each of the phase detectors being structured to generate an output signal having a logic level corresponding to the logic level of one of the received signals at a predetermined transition of the other of the received signals.