Patent ID: 7043516

Claim:
In a floating-point processor, an addition pipeline, adapted for application thereto of first and second operand signals, each of which represents the sign, exponent, and mantissa of a respective floating-point input operand, for performing an effective addition or subtraction on the input operands and generating an addition-pipeline ouput signal representing the result, the addition pipeline comprising: A) a main mantissa adder adapted for application thereto of first and second processed mantissa signals and representing respective mantissa values, the main mantissa adder being operable selectively to perform addition and subtraction on the mantissa values and generate a mantissa-adder output, representative thereof, from which the addition pipeline generates the addition-pipeline ouput; and B) mantissa-processing circuitry for so generating from respective ones of the input operands' mantissas and applying to the main mantissa adder respective processed mantissa signals that, for at least some pairs of mantissas, the mantissa signals applied to the main mantissa adder when the main mantissa adder is to subtract a pair of mantissas are offset to the left by one position from the mantissa signals applied thereto when the main mantissa adder is to add the same pair of mantissas.