Patent ID: 7193446

Claim:
A dynamic logic circuit comprising: a dynamic logic tree formed from one or more transistors coupled between a summing node and a first power supply rail corresponding to a first logical state, and wherein gates of said transistors are coupled to one or more logical input signals; a precharge circuit connected to said summing node and a second power supply rail for setting said summing node to a precharge voltage level corresponding to a second logical state opposite from said first logical state, said precharge circuit having an input coupled to a precharge clock signal, whereby said summing node is held in said second logical state while said precharge clock signal is asserted; an inverter having an input coupled to said summing node and an inverter output providing an output signal of said dynamic logic circuit; an inverter foot device coupled to a given one of said first power supply rail and said second power supply rail, and further coupled to a power supply rail input of said inverter, whereby conduction through said inverter to said given power supply rail is disabled in response to assertion of a power control signal coupled to an input of said inverter foot device; and a keeper circuit connected between said inverter output and said given power supply rail, and having a control input coupled to said summing node for conducting current from said inverter output to said given power supply rail when said conduction through said inverter to said given power supply rail is disabled.