Patent ID: 7298655

Claim:
A semiconductor memory device which is operative in a read mode to read a memory cell of the device, comprising: a first memory cell array including a first memory cell to be read, a first bit line pair and a first word line, wherein a charge contained in the first memory cell to be read is applied to the first bit line pair when a word line select signal applied to the first word line becomes active during the read mode; a second memory cell array including a second memory cell, a second bit line pair and a second word line; a sense amplifier operatively interposed between the first and second memory cell arrays; a first isolation circuit which isolates the sense amplifier from the first bit line pair when a first isolation signal is active and which couples the first bit line pair and the sense amplifier when the first isolation signal is inactive; a second isolation circuit which isolates the sense amplifier from the second bit line pair when a second isolation signal is active, and which couples the second bit line pair and the sense amplifier when the second isolation signal is inactive; wherein, during the read mode, the first isolation signal is held active and the second isolation signal is held inactive prior to the word line select signal becoming active.