Patent ID: 8041989

Claim:
A memory system comprising: a memory controller; a plurality of memory modules connected to the memory controller and including a plurality of memory devices, the plurality of memory devices including at least one memory device for storing checkbits that are computed using data stored in memory devices located on at least two of the plurality of memory modules, and at least two of the memory devices located on at least two of the memory modules are accessed in parallel, wherein all of the memory modules are read from during every read operation; a decoding mechanism for detecting that one of the memory modules has failed and for allowing the memory system to continue to run unimpaired in the presence of the memory module failure, the memory module failure occurring on a memory module without prior failure information, wherein the detecting is responsive to the stored checkbits and includes identifying the memory module that has failed and an additional single memory device failure coincident to the memory module failure, the additional single memory device failure occurring on a memory device on an other of the memory modules and the detecting includes identifying the memory module that has failed when the memory module failure is not coincident with a single memory device failure on a memory device on an other of the memory modules; and a correction mechanism for correcting the memory module failure coincident to the additional single memory module failure without redirecting memory requests to a spare memory module.