Patent ID: 6952752

Claim:
A storage apparatus to be coupled with a system bus for receiving a write request accompanied with a plurality of block data through said system bus from an information processing system, wherein each of said plurality of block data includes a first predetermined number of bits, said storage apparatus comprising: a plurality of nonvolatile flash semiconductor memories each of which includes a plurality of memory blocks erasable in units by flash erase operations; and an interface and controller unit which is coupled with said system bus and said plurality of nonvolatile flash semiconductor memories, and which carries out write operations of said plurality of block data into said plurality of nonvolatile flash semiconductor memories in response to said write request, wherein each of said plurality of nonvolatile flash semiconductor memories includes a flash data bus, having a width of a second predetermined number of bits, for inputting data to be written into each nonvolatile flash semiconductor memory, wherein said interface and controller unit has a system data bus having a width of a third predetermined number of bits which is a product of multiplying said second predetermined number of bits by a number of said plurality of nonvolatile flash semiconductor memories, wherein said write operations of said plurality of block data into said plurality of nonvolatile flash semiconductor memories are carried out simultaneously in response to said write request, and wherein said interface and controller unit carries out a read operation of said plurality of block data from said plurality of nonvolatile flash semiconductor memories in response to a read request through said system bus from said information processing system.