Patent ID: 7791327

Claim:
A voltage converter, comprising: a pulse width modulation controller chip comprising: a plurality of pins, the plurality of pins comprise a Vcc pin connected to a first power supply, a BOOT pin connected to the Vcc pin via a diode for receiving power from the first power supply, a PHASE pin connected to the BOOT pin via a capacitor, a OCSET pin connected to the PHASE pin via a first resistor, a UGATE pin, and a LGATE pin; a gate control logic circuit for outputting a first drive signal and a second drive signal that is the inverse of the first drive signal; an enabling comparator for generating an enable signal when a voltage at the OCSET pin is higher than a first reference voltage; a first gate driver comprising an input terminal for receiving the first drive signal, a positive power supply terminal connected to the BOOT pin, a negative power supply terminal connected to the PHASE pin, and an output terminal for outputting a third drive signal; a second gate driver comprising an input terminal for receiving the second drive signal, a positive power supply terminal connected to the Vcc pin, a negative power supply terminal electrically grounded, and an output terminal for outputting a fourth drive signal that is the inverse of the third drive signal; a current source connected to the OCSET pin which is also connected to the cathode of a zener diode, and the anode of the zener diode is grounded; a first comparator for generating a control signal when a voltage at the OCSET pin is higher than a second reference voltage; a power-on reset circuit for generating a power-on reset signal in response to the control signal; an inductor current sensor for detecting a first current flowing through the OCSET pin; a counter and current step generator for generating a control signal when the voltage converter is in a discontinuous current mode according to the first current; and an oscillator for reducing a frequency outputted to signal the gate control logic circuit to reduce frequencies of the first and second drive signal; an enabling transistor comprising a source connected to the OCSET pin, a drain that is grounded, and a gate serving as an enabling pin of the voltage converter; a pull-up transistor comprising a gate connected to the UGATE pin for receiving the third drive signal, a source connected to a second power supply, and a drain connected to the PHASE pin; a pull-down transistor comprising a drain connected to the PHASE pin, a gate connected to the LGATE pin for receiving the fourth drive signal, and a source that is grounded; and a low pass filter comprising an input terminal connected to the PHASE pin, and an output terminal serving as an output terminal of the voltage converter; wherein the gate control logic circuit generates the first and second drive signals for the first and second gate driver to respectively switch on and off the pull-up transistor and the pull-down transistor in response to the enabling signal and the power-on reset signal.