Patent ID: 8181058

Claim:
A receiver circuit, comprising: a first input node configured to receive a data signal; an analog-to-digital converter (ADC), electrically coupled to the first input node, configured to generate first samples of the data signal based on a first clock signal; a clock-data-recovery (CDR) error-detection circuit, electrically coupled to the first input node, configured to generate second samples of the data signal based on a second clock signal, and configured to estimate intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples; and a CDR circuit, electrically coupled to the CDR error-detection circuit, configured to generate the first clock signal, the second clock signal and a third clock signal based on the second samples and the estimated ISI, wherein the first clock signal and the second clock signal are generated from the third clock signal.