Patent ID: 7328311

Claim:
A memory controlling method for an information processing system having a CPU, a memory controller being supplied a read request from the CPU, and a memory unit controlled by the memory controller and being provided with a memory bank and a plurality of cache memories allocated against the memory bank, one of the plurality of cache memories being not subiect to a hit check operation, the method comprising the steps of: reading out data from the memory bank to the one of the plurality of cache memories which is not subject to the hit check operation; writing back data stored in another one of the plurality of cache memories which is subject to the hit check operation to the memory bank; and changing the one of the plurality of cache memories which is not subject to the hit check operation so as to be subject to the hit check operation and the another one of the plurality of cache memories which is subject to the hit check operation so as to be not subject to the hit check operation.