Patent ID: 7704870

Claim:
An interconnection process, comprising: providing a substrate having a conductive region; forming a dielectric layer on the substrate; forming a patterned metal hard mask layer having a trench opening on the dielectric layer; conformally forming a dielectric hard mask layer on the patterned metal hard mask layer, wherein the dielectric hard mask layer lines a surface of the trench opening; defining a photoresist pattern to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer in the trench opening to form an opening, wherein the opening exposes the conductive region; forming a passivation layer in the opening; removing the photoresist pattern; performing a first etching process with use of the patterned metal hard mask layer as a mask to form a trench in the dielectric layer, wherein the dielectric hard mask layer is removed during the first etching process; removing the passivation layer; and forming a conductive layer in the trench and in the opening.