Patent ID: 8031747

Claim:
An apparatus, comprising: a packet delay determination module configured to determine each of a plurality of packet delay values based on time values associated with a first electronic component and a second electronic component; a packet delay selection module configured to select a subset of the plurality of packet delay values based on a maximum frequency drift of the first electronic component; a statistical parameter determination module configured to evaluate a first parameter based on a first portion of the subset of packet delay values, and a second parameter based on a second portion of the subset of packet delay values; a validation module configured to validate the first parameter and the second parameter when the first portion and the second portion of the subset of packet delay values each include a minimum number of packet delay values, the minimum number being at least two; and an adjustment module configured to compensate for at least one of a frequency variation or a phase variation of the first electronic component based on the first parameter and the second parameter if the first parameter and the second parameter are both validated; at least one of the packet delay determination module, the packet delay selection module, the statistical parameter determination module, the validation module, or the adjustment module being implemented in at least one of a memory or a processing device.