Patent ID: 7936330

Claim:
A liquid crystal display comprising: a timing controller; N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2; N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner; a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another; and a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller, wherein the timing controller serially transfers a preamble signal, in which a plurality of bits having a high logic level are successively arranged and then a plurality of bits having a low logic level are successively arranged, to each of the N source drive ICs through each of the N pairs of data bus lines, transfers a lock signal indicating that a phase of an internal clock pulse output from each of the N source drive ICs is locked to the first source drive IC through the lock check line, serially transfers a plurality of dummy source control packets, a real source control packet, and a last dummy source control packet in the order named to each of the N source drive ICs through each of the N pairs of data bus lines if the timing controller receives a feedback signal of the lock signal from the last source drive IC through the feedback lock check line, and serially transfers at least one RGB data packet to each of the N source drive ICs through each of the N pairs of data bus lines.