Patent ID: 6861864

Claim:
A method of locating a fault within an array of integrated circuits comprising: establishing a first propagation speed for a signal passing through a first self timed circuit within said array of interconnect modules containing a first row of serially connected interconnect modules; establishing row propagation speeds for signals passed through a number of rows of serially connected interconnect modules of a subarray within said array of interconnect modules; comparing said row propagation speed to said first propagation speed to establish a row fault criteria; establishing a second propagation speed for a signal passing through a second self timed circuit within said array of interconnect modules containing a first column of serially connected interconnect modules; establishing column propagation speeds for signals passing through a plurality of columns of serially connected interconnect modules of said subarray within said array of interconnect modules; comparing said column propagation speed with said first propagation speed to establish a column fault criteria; generating a matrix of row and column fault conditions based upon said row and column fault criteria; locating a fault within said array of interconnect modules by utilizing said row and column fault conditions within said matrix that correspond to an array location.