Patent ID: 7911063

Claim:
A semiconductor device comprising: a first interconnection layer that includes a bonding pad exposed from an opening provided in a surface protective film; a first via layer that is provided below said first interconnection layer; a second interconnection layer that is provided below said first via layer; a second via layer that is provided below said second interconnection layer; a third interconnection layer that is provided below said second via layer and disposed in a stripe shape; a third via layer that is provided below said third interconnection layer; a fourth interconnection layer that is provided below said third via layer and disposed in a stripe shape; and a fourth via layer that is provided below said fourth interconnection layer, wherein said first interconnection layer, said first via layer, said second interconnection layer, said second via layer, said third interconnection layer, said third via layer, said fourth interconnection layer, and said fourth via layer are laminated, the bonding pad overlaps the first via layer, the second interconnection layer, the third interconnection layer, and the fourth interconnection layer in plan view, the first via layer is formed in a stripe shape and is disposed in parallel to the third interconnection layer, a first width of the first via layer is equal to or smaller than a second width of the third interconnection layer, and the second width of the third interconnection layer is equal to or smaller than a third width of the fourth interconnection layer, a direction in which said third interconnection layer extends is orthogonal to a direction in which said fourth interconnection layer extends, said first interconnection layer, said first via layer, said second interconnection layer, said second via layer, said third interconnection layer, said third via layer, said fourth interconnection layer, said fourth via layer, and a semiconductor layer are laminated on a semiconductor chip having a rectangular shape in a planar view, said first via layer is provided in parallel to an outer peripheral edge of said semiconductor chip while being disposed in a stripe shape, said third interconnection layer is provided in parallel to an outer periphery of said semiconductor chip, a gate electrode layer is disposed in a stripe shape in said semiconductor layer, and a direction in which said gate electrode layer extends is parallel to said direction in which said fourth interconnection layer extends.