Patent ID: 7212744

Claim:
A receiver circuit, comprising: a synchronous circuit that recovers and outputs a clock signal having a frequency of f 1 /n Hz (n:2 or larger natural number) synchronized with input one data signal the data rate of which is f 1 b/s (f 1 : positive real number); “j” pieces of multipliers that output each clock signal acquired by multiplying a clock signal output from the synchronous circuit by predetermined multiple ratio via “j” pieces of interconnects (j: one or larger natural number); and a synchronous digital circuit that has “j” pieces of parallel input terminals including one common to the input of the synchronous circuit, “j×k” pieces of parallel output terminals and “j” pieces of parallel clock input terminals, decides and recovers “j” pieces of data signals the data rate of each of which is f 1 b/s and which are input to the “j” pieces of parallel input terminals using the “j” pieces of multiplied clock signals applied to the “j” pieces of parallel clock input terminals via (j+1) th to (2×j) th interconnects as a criterion of timing, demultiplexes the data in the ratio of “1:k” and converts to “j×k” pieces of data signals the data rate of each of which is f 1 /k b/s, wherein: the “j” pieces of parallel terminals to which data signals are input of the synchronous digital circuit function as the input terminal of the receiver circuit and the “j×k” pieces of parallel terminals from which the data signals are output function as the output terminal of the receiver circuit; and first to “j”th interconnects connecting the output. terminal of the synchronous circuit and the input terminals of the “j” pieces of multipliers and “j+1”th to “2×j”th interconnects connecting the “j” pieces of multipliers and the “j” pieces of parallel clock input terminals of the digital circuit are arranged so that delays t 2 max are smaller out of the maximum value t 1 max s of delays caused on the first to the “j”th interconnects and the maximum value t 2 max s of delays caused on the “j+1”th to the “2×j”th interconnects and the delays t 2 max are equivalent to 1/10 or less of a clock cycle 1/f 1 s output from each multiplier.