Patent ID: 7064739

Claim:
A liquid crystal display, comprising: a transistor board having a plurality of transistors each including a gate, a source and a drain; a common board including a common electrode and provided to oppose said transistor board via liquid crystal; a gate driver for driving the gates of said plurality of transistors; and a source driver with a plurality of source driver units being cascaded, for driving the sources of said plurality of transistors, wherein each of said source driver units comprises: flip-flops each with a wire of a clock signal inputted from the source driver unit in a previous stage or an outside being connected to a clock terminal, a wire of an input signal inputted from the source driver unit in the previous stage or the outside being connected to an input terminal, and a wire for outputting an output signal to the source driver unit in a next stage or the outside being connected to an output terminal; inverters each with the wire of the clock signal inputted from said source driver unit in the previous stage or the outside being connected to an input terminal, and the wire for outputting the clock signal to the source driver unit in the next stage or the outside being connected to an output terminal; and an output circuit for outputting a signal to the source of the transistor of said transistor board correspondingly to the input signal inputted from said source driver unit in the previous stage or the outside, the liquid crystal display further comprising: a first output wire for outputting an inverting clock signal outputted by said inverter to the source driver unit in the next stage or the outside; and a second output wire for outputting a non-inverting clock signal of the clock signal inputted from said source driver unit in the previous stage or the outside to the source driver unit in the next stage or the outside, wherein in said flip-flop, the first output wire of the source driver unit in the previous stage or the wire of the clock signal inputted from the outside is connected to the clock terminal.