Patent ID: 8078843

Claim:
A computer system for stalling processing, said computer system comprising: a memory; and a hardware processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising: obtaining for execution an extended DRAIN instruction, said extended DRAIN instruction having an architected definition comprising an opcode field identifying said extended DRAIN instruction, a stall field separate from the opcode field specifying a processing stage to stall, the processing stage being selected from a plurality of processing stages at which the extended DRAIN instruction may stall processing, a cycles field indicating a number of additional cycles to stall processing, and a conditions field to specify one or more conditions to satisfy before processing continues, wherein the opcode field, the stall field, the cycles field and the conditions field are each separate architected fields of the extended DRAIN instruction; and executing said extended DRAIN instruction, the executing comprising: determining at which processing stage to stall, said determining using the stall field of the extended DRAIN instruction; and stalling processing at the determined processing stage, wherein the stalling comprises stalling processing at the determined processing stage for at least the number of additional cycles as specified within the cycles field of the extended DRAIN instruction, and wherein the stalling the number of additional cycles specified within the cycles field begins after the one or more conditions specified in the conditions field of the extended DRAIN instruction have been satisfied, wherein stalling continues even after the one or more conditions are satisfied that would have allowed processing to continue absent the additional cycles.