Patent ID: 7983071

Claim:
An integrated circuit (IC) including an array of memory cells, said memory cell comprising: a core storage element having a first storage node and a complementary second storage node; a first cell pass transistor coupled to said first storage node and a second cell pass transistor coupled to said second storage node, wherein a first bitline is coupled to a first BL node in a source drain path of said first cell pass transistor, and wherein a second BL is coupled to a second BL node in a source drain path of said second cell pass transistor; a first buffer circuit comprising a first buffer pass transistor and a first buffer driver transistor, wherein said first buffer pass transistor and said first buffer driver transistor are coupled to said source drain path of said first cell pass transistor, wherein said first buffer pass transistor is between said first BL node and said buffer driver transistor, and wherein a gate of said first buffer driver transistor is coupled to said second storage node; a second buffer circuit comprising a second buffer pass transistor and a second buffer driver transistor, wherein said second buffer pass transistor and said second buffer driver transistor are coupled to a source drain path of said second cell pass transistor, wherein said second buffer pass transistor is between said second BL node and said buffer driver transistor, and wherein a gate of said first buffer driver transistor is coupled to said second storage node; and a first wordline coupled to said first and second cell pass transistors; wherein said first cell pass transistor and first buffer pass transistor are connected in series between said first storage node and said first BL node, and said first cell pass transistor is between said first buffer driver transistor and said first storage node, and wherein said second cell pass transistor and second buffer pass transistor are connected in series between said second storage node and said second BL node, and said second cell pass transistor is between said second buffer driver transistor and said second storage node.