Patent ID: 8245014

Claim:
A network processor having a multithreaded pipeline, comprising: an upper pipeline comprising an instruction unit for fetching instructions and a decode unit, the instruction unit having an input coupled to receive a signal indicative of an instruction queue depth corresponding to a plurality of threads from the decode unit, and the decode unit having an input coupled to an output of the instruction unit to receive instruction data from the instruction unit; a lower pipeline, the lower pipeline comprising a thread interleaver and an execution unit, the thread interleaver having a first input to receive a plurality of decoded instructions corresponding to the plurality of threads from the upper pipeline, and a second input to receive a thread conditions signal from the execution unit, and the execution unit generating a branch misdirects signal; the thread interleaver determining a thread execution sequence based on the thread conditions signal, the thread conditions signal indicative of an execution stall corresponding to the plurality of threads; and the instruction unit determines a fetch instruction sequence for the plurality of threads based on the instruction queue depth signal and the branch mispredicts signal.