Patent ID: 7663918

Claim:
A nonvolatile memory device comprising: a first bitline group having a plurality of first bitlines; a plurality of source selection transistors, wherein a gate of each source selection transistor is coupled to a source selection line; a first memory block provided between the first bitline group and the source selection transistors; a plurality of first drain selection transistors coupled between the first bitline group and the first memory block, wherein a gate of each first drain selection transistor is coupled to a first drain selection line; a second bitline group having a plurality of second bitlines that are different from the first bitlines; a second memory block provided between the second bitline group and the source selection transistors; and a plurality of second drain selection transistors, wherein a gate of each second drain selection transistor is coupled to a second drain selection line, one terminal of each second drain selection transistor being coupled to each second bitline of the second bitline group and another terminal of each second drain selection transistor being coupled to the second memory block, wherein in the event that the first memory block is selected, the first memory block uses the second bitline group as a common source line, and wherein in the event that the second memory block is selected, the second memory block uses the first bitline group as a common source line.