Patent ID: 7996712

Claim:
A data transfer controller for controlling a data transfer to a cache memory when the data transfer to the cache memory can be executed discontinuously, the data transfer controller comprising: a check data creation module for creating check data for detecting a data error in received data; a check data storage module for temporarily storing the created check data; a data consistency determination module for determining a consistency of data stored in the cache memory, based on the created check data, which determines whether or not the data stored in the cache memory matches a specified size, which is specified beforehand, and whether or not a continuity of the data is maintained; and a first data transfer control circuit configured to execute the check data creation module, the check data storage module and the data consistency determination module; wherein the data consistency determination module determines whether or not data read out from the cache memory matches a different specified size, which is specified beforehand, and whether or not the continuity of the read-out data is maintained; and wherein the data consistency determination module compares third check data, which is created when data of the different specified size is read out from the cache memory, against fourth check data, which is created when the data of the different specified size is sent to the outside, and determines that the data read out from the cache memory and the sent data has consistency when the third check data matches the fourth check data.