Patent ID: 7570660

Claim:
A multi-port network element, comprising: a plurality of segments, each of which includes a port; a configurable input-output device coupled to said port; a circuit to recover a clock signal from a user signal received through said port; and a programmable logic device that handles protocol-specific functions relative to said user signal, which device is adapted to handle any protocol agreed to by a party managing said network element and a user providing said user signal; wherein said circuit to recover a clock signal is adapted to operate with said protocol agreed to by said party managing said network element and said user; wherein said protocol-specific functions of said programmable logic device comprise circuitry for creating time slots in an Optical Transport Unit level-1 (OTU1) and inserting said received signal into said time slots and timing circuitry for adapting said received signal into said time slots, wherein said timing circuitry configured to compensate for timing impairments introduced end-to-end by mapping and unmapping processes and for timing impairments introduced by pointer adjustments from previous nodes; and wherein said timing circuitry is further configured to write phase-offset information to a frame overhead area, said phase-offset information enables an egress node to regenerate an accurate clock for the user signal.