Patent ID: 8822287

Claim:
A method of manufacturing a semiconductor device, comprising: forming an integrated structure, a first insulating interlayer pattern, a first stopping layer pattern, a second insulating interlayer pattern and a second stopping layer pattern in a first region of a substrate, the substrate including the first region and a second region; forming a third insulating interlayer pattern in the second region of the substrate with an upper surface at about a same level as an upper surface of the second stopping layer pattern; removing the second stopping layer pattern; forming a preliminary channel layer pattern penetrating a portion of the second insulating interlayer pattern, the first stopping layer, the first insulating interlayer pattern and the integrated structure; removing a portion of the preliminary channel layer pattern; removing residue at a step portion, the step portion including the second and third insulating interlayers; and polishing a remainder of the preliminary channel layer pattern, the second insulating interlayer pattern and the third insulating interlayer pattern to expose an upper surface of the first stopping layer pattern and to form a channel pattern structure.