Patent ID: 8838935

Claim:
A micro page table engine apparatus comprising: logic to receive a memory page request for a memory page, wherein the memory page request includes a linear address of the memory page; a translation lookaside buffer (TLB) to store one or more memory page address translations configured to translate linear addresses to platform physical addresses that map to micro physical addresses of a memory; a page miss handler tag table configured to store a plurality of entries configured to index platform physical addresses to micro physical addresses, wherein each entry, in addition to an index indexing a platform physical address to a micro physical address, includes state information of a memory page associated with the micro physical address; a page miss handler logic to perform a micro physical address lookup in the page miss handler tag table in response to the TLB not storing the memory page address translation for the memory page referenced by the memory page request; and a memory management logic to implement rank shedding of the memory, including updating the state information in the entries of the page miss handler tag table to reflect results of rank shedding related operations performed on the memory.