Patent ID: 7917703

Claim:
An invalidate method for maintaining cache coherency on a network on chip (‘NOC’), the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block coupled to a router via a memory communications controller and the network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through the routers, the method comprising: receiving, through a port on the router of a network, an invalidate command, the invalidate command including an identification of a cache line and a mask specifying which IP blocks are to receive the invalidate command, the invalidate command representing an instruction to invalidate the cache line, including sending the invalidate command to an IP block served by the router if the IP block is specified by the mask; if the port is a vertical port, sending the invalidate command horizontally and vertically to neighboring routers; if the port is a horizontal port, sending the invalidate command only horizontally to neighboring routers: and bypassing, by each IP block, the IP block's memory communications controller and sending, by each IP block, inter-IP block, network addressed communications directly to the network through the IP block's network interface controller.