Patent ID: 6940937

Claim:
A clock generation circuit, comprising: a phase-locked loop for generating a plurality of clock phases; a first frequency synthesis circuit, comprising: a first multiplexer, for forwarding a selected one of the plurality of clock phases responsive to a first select signal; a second multiplexer, for forwarding a selected one of the plurality of clock phases responsive to a second select signal; a first adder leg, having an input for receiving a frequency select word having an integer portion and a fractional portion, for generating the first select signal corresponding to an accumulation of the frequency select word; a second adder leg, having an input for receiving a portion of the frequency select word, for generating the second select signal corresponding to a sum of the portion of the frequency select word with an accumulation of the frequency select word; a toggle multiplexer, having first and second inputs coupled to the outputs of the first and second multiplexers, for toggling a selection of its inputs in sequence; and a multivibrator, having a clock input coupled to an output of the toggle multiplexer, for inverting an output of the multivibrator responsive to a transition at its clock input.