Patent ID: 7840924

Claim:
An apparatus for verifying a circuit operating with a plurality of different clock signals, the apparatus comprising: a clock domain crossing (CDC) detector that finds CDC paths between circuit elements operating with different clocks in the circuit; a delay generator inserter that produces a delay-insertable version of the circuit by embedding a delay generator into each CDC path found in the circuit, wherein the delay generators, when activated, give a signal delay to the corresponding CDC paths; a simulator that performs a simulation of the delay-insertable circuit by using a specified simulation pattern; a potential CDC path finder that extracts CDC paths that could encounter metastability from among the CDC paths of the delay insertable circuit, together with time points when that metastability could occur, based on results of the simulation and the delay-insertable circuit; a delay pattern generator that generates a delay pattern that affects an output signal of the delay-insertable circuit, from the results of the simulation and the delay-insertable circuit, along with the extracted CDC paths that could encounter metastability and the time points when the metastability could occur; and a verifier that generates a delay according to the generated delay pattern that affects the output signal of the delay-insertable circuit, and tests immunity from metastability that affects the output signal of the delay-insertable circuit.