Patent ID: 7116133

Claim:
A synchronous memory device comprising: an array of memory cells; at least one clock input for receiving at least one clock signal and for producing first and second internal clock signals; and a circuit for reducing skew between the first and second internal clock signals, said circuit comprising: first and second clock signal input/output lines for receiving and transmitting first and second internal clock signals, respectively; and at least first and second inverters each having an input and an output, said input of said first inverter connected to said output of said second inverter and to said first clock signal input/output line and said input of said second inverter connected to said output of said first inverter and to said second clock signal input/output line; and first and second input buffer circuits for receiving first and second external signals, wherein each of said first and second input buffer circuits comprises: an input for receiving an external signal; an input for receiving a reference voltage signal; a differential amplifier coupled to said input, said differential amplifier having an output terminal for providing a latch signal in response to the external signal in comparison to the reference voltage signal, the latch signal having a first or second state; a buffer circuit inverter connected to said output terminal of said differential amplifier, said buffer circuit inverter generating a first internal signal when the latch signal is in a first state, and a second internal signal when the latch signal is in a second state; and an input line for transmitting said first or second internal signal, said input line connected to one of said first and second signal input/output lines.