Patent ID: 8432199

Claim:
A fractional digital phase locked loop with an analog phase error compensator, comprising: an arithmetic phase error detector configured to detect digital phase error values by accumulating a frequency command word and a DCO clock and sampling the accumulated values of the frequency command word and the DCO clock synchronized and accumulated with rising edges of a reference clock by a retimed clock; an analog phase error compensator configured to detect and compensate fractional phase error values of the reference clock and the DCO clock according to a fractional phase difference between the reference clock and the retimed clock; a digital loop gain controller configured to filter the digital phase error values and to control loop operation characteristics; a digital controlled oscillator configured to vary a frequency of the DCO clock according to an output value of the digital loop gain controller and the fractional phase error values compensated by the analog phase error compensator; and a retimed clock generator configured to synchronize the reference clock with the rising edges of the DCO clock to output the retimed clock.