Patent ID: 7107393

Claim:
An asynchronous first-in, first-out (FIFO) buffer communicating between first and second clock domains, the FIFO buffer comprising: a. an input clock terminal receiving an input clock signal of an input clock frequency associated with the first clock domain; b. an output clock terminal receiving an output clock signal of an output clock frequency associated with the second clock domain; c. clock-comparison and write logic having: i. a first clock-comparison-circuit input node receiving the input clock signal; ii. a second clock-comparison-circuit input node receiving the output clock signal; and iii. a write-control node; iv. wherein the clock-comparison and write logic compares the input clock signal with the output clock signal to produce a write signal on the write-control node; and d. a shift register having: i. a shift-register input port; ii. a shift-register output port; and iii. a write terminal connected to the write-control node of the clock-comparison and write logic, wherein the clock-comparison and write logic provides an address pointer to the shift register, the address pointer having a address value that varies based on the comparing of the input and output clock signals.