Patent ID: 7200062

Claim:
A method of refreshing memory cells in a memory system having a plurality of dynamic random access memory (“DRAM”) devices, the method comprising: programming a plurality of the DRAM devices in the memory system with respective delay configurations, at least some of the DRAM devices being programmed with different delay configurations, wherein the act of programming the plurality of DRAM devices in the memory system with respective delay configurations comprises: programming each of the DRAM devices with a respective base delay value; programming each of the DRAM devices with a respective delay adjustment value; and combining the respective base delay value with the respective delay adjustment value in each of the DRAM devices to provide the respective delay configuration; applying a refresh command to the plurality of the DRAM devices in the memory system; and initiating a refresh of the memory cells in each of the plurality of the DRAM devices responsive to the refresh command after respective delays corresponding to the programmed delay configurations of the DRAM devices.