Patent ID: 7802217

Claim:
A method of modifying a design of a block of a chip to reduce a net power consumption of the block, comprising operations of: (1) read in design data of the block; (2) run a static timing engine to calculate path delays and a power estimation tool to calculate power consumption on the design data of the block; (3) select an instance of the block, wherein the selected instance has not been selected before the method starts; (4) determine if the instance is on at least one critical path, if the instance is on the at least one critical path, return to step (3), if the instance is not on the at least one critical path, obtain an activity factor (AF) from the power estimation tool and a slack from the static timing engine and move to step (5); (5) determine if the instance meets a criteria of low-AF and a first criteria of high-slack, if the instance meets the criteria of low-AF and the first criteria of high-slack, the instance is replaced with a gate-length bias (GBIAS) cell, if the instance does not meet the criteria of low-AF and the first criteria of high-slack, determine if the instance meets a criteria of high-AF and a second criteria of high-slack if the instance meets the criteria of high-AF and the second criteria of high-slack, the instance is replaced with a high threshold voltage (HVT) cell if the instance does not meet the criteria of high-AF and the second criteria of high-slack, move to step (6); (6) determine if all instances in the block has been selected, if all instances in the block have been selected, stop the method, wherein a revised design of the block has been created by the method and the revised design of the block reduces the net power consumption of the block, if not all instances have been selected, go to step (3), wherein each operation of the method is executed by computer.