Patent ID: 7176765

Claim:
A device comprising: a capacitor coupled to a charge node, wherein a node voltage is present on the charge node; a current controller with an inverter sink output lead and a trigger voltage source lead, wherein the current controller receives an inverter sink current on the inverter sink output lead; a programmable temperature trim register containing temperature trim bits; and a comparator with a non-inverting input lead and a comparator sink lead, wherein the non-inverting input lead is coupled to the charge node, and the comparator sink lead is coupled to the inverter sink output lead, wherein the comparator outputs a digital signal that inverts at an end time, wherein the node voltage reaches a first trigger voltage at a start time, wherein a delay period begins at the start time and ends at the end time, wherein a remainder period begins at the end time and ends when the node voltage reaches a second trigger voltage, wherein the second trigger voltage is a first voltage at a first temperature and a second voltage at a second temperature, wherein the delay period is dependent on the inverter sink current, wherein the inverter sink current is dependent on the temperature trim bits, and wherein the sum of the delay period plus the remainder period remains substantially constant at the first temperature and at the second temperature.