Patent ID: 7796135

Claim:
A method of synchronizing buffer transitions among a plurality of graphics processors using a central processing unit, the method comprising: with the central processing unit, transmitting a stream of rendering commands to the plurality of graphics processors, the stream of rendering commands including one or more commands directing each of the graphics processors to write pixel data for a portion of a current image associated with the respective one of the graphics processors to a respective first frame buffer; with the central processing unit, receiving from each of the graphics processors a first signal, each first signal indicating completion of writing of the pixel data for the portion of the current image associated with the respective one of the graphics processors; and after receiving the respective first signals from all of the graphics processors, with the central processing unit, transmitting a second signal to each of the graphics processors instructing each of the graphics processors to write pixel data for a respective portion of a next image to a respective second frame buffer, wherein transmitting the second signal includes modifying a value stored in a control register in each of the graphics processors from a stall value to a different value, wherein the rendering process in each of the graphics processors is paused while the stall value is stored in the control register.