Patent ID: 7827348

Claim:
A high performance flash memory device (FMD) comprising: a FMD interface configured to provide data input and output to a host computer system; at least one non-volatile memory module having one or more non-volatile memory chips that are arranged in a plurality of vertical groups and in a plurality of horizontal rows such that each of the vertical groups and each of the horizontal rows having one of said one or more non-volatile memory chips overlapped, wherein number of the non-volatile memory chips in said each of the vertical groups is equal to number of the plurality of horizontal rows; and a FMD controller configured to control data transmission between said at least one non-volatile memory module and the host computer system via said FMD interface, said FMD controller comprises a microcontroller, a plurality of parallel data buffers and a plurality of independent data channels, each of the parallel data buffers is divided into a plurality of sub-buffers, each of the sub-buffers is connected to corresponding one of the parallel data channels, wherein each of the data channels connects to respective one of the horizontal rows and wherein said data transmission is conducted in parallel via the independent data channels in one of at least one data interleaving scheme.