Patent ID: 8296345

Claim:
A microprocessor, comprising: a random number generator, configured to generate random numbers based on random electrical characteristics of the microprocessor; wherein the instruction set architecture of the microprocessor defines the instructions that may be included in a program to be executed by the microprocessor, wherein at least one of the instructions defined by the instruction set architecture is related exclusively to operation of the random number generator; wherein the random number generator is selectively available to the at least one of the instructions defined by the instruction set architecture of the microprocessor related exclusively to operation of said random number generator depending upon results of a self-test of the random number generator performed in response to a reset; a self-test unit, coupled to said random number generator, configured to perform said self-test of said random number generator for proper operation in response to a reset; and an instruction translator, coupled to said self-test unit, configured to translate program instructions defined by the instruction set architecture, including the at least one of the instructions defined by the instruction set architecture of the microprocessor related exclusively to operation of said random number generator, wherein the microprocessor generates a fault defined by the instruction set architecture in response to execution of the at least one of the instructions defined by the instruction set architecture of the microprocessor related exclusively to operation of said random number generator if said self-test unit previously determined said random number generator is not operating properly.