Patent ID: 7523545

Claim:
A method of manufacturing a printed circuit board having a plurality of circuit layers with at least one z-axis interconnect using a single lamination cycle, the method comprising: attaching a plurality of one-metal layer carriers with each other after parallel processing each of the plurality of one-metal layer carriers, wherein the parallel processing of at least one of the plurality of one-metal layer carriers comprises: imaging at least one photo resist onto a substrate having at least one copper foil formed on at least one side of the substrate; etching off the at least one copper foil from the substrate with exception of at least one part of the at least one copper foil covered by the at least one photo resist; stripping off the at least one photo resist to expose the at least one part of the at least one copper foil to form at least one copper foil pad for one of the plurality of circuit layers; applying a lamination adhesive on the substrate; applying a protective film on the lamination adhesive; forming at least one micro via into the substrate to expose the at least one copper foil pad at a side of the substrate opposite to the at least one side of the substrate; filling at least one conductive paste into the at least one micro via formed in the substrate; and removing the protective film to expose the lamination adhesive on the substrate for attachment.