Patent ID: 7803675

Claim:
A method of manufacturing a gate-all-around type semiconductor device, the method comprising: providing a semiconductor substrate; forming a preliminary sacrificial layer, disposed lengthwise in a first direction, over the semiconductor substrate; forming a preliminary channel layer over the preliminary sacrificial layer; forming a first mask pattern over the preliminary channel layer semiconductor substrate, wherein the preliminary sacrificial layer and the preliminary channel layer have a width greater than a width of the first mask pattern; forming a first insulation layer on the semiconductor substrate to cover the first mask pattern, the preliminary channel layer and the preliminary sacrificial layer, the first insulation layer having a first opening exposing a portion of the first mask pattern; forming a second insulation layer over the first insulation layer and the first mask pattern; forming a second and a third mask pattern over the second insulation layer, wherein the second and third mask patterns, disposed in a second direction approximately perpendicular to the first direction, are located toward the distal ends of the preliminary sacrificial layer; forming a second opening by removing an exposed portion of the second insulation layer and first mask pattern, and by removing the portion of the preliminary channel layer directly under the first mask pattern, such that a channel layer and a sacrificial layer are formed; forming a third opening by partially removing portions of the first insulation layer left exposed by the second mask pattern; transforming the channel layer to a preliminary nanowire channel by removing the sacrificial layer; forming a gate conductive layer on the semiconductor substrate to cover the second and third opening; removing the second and third mask patterns, and removing the first insulation layer; forming a gate electrode by partially removing the gate conductive layer to detach the gate electrode from the preliminary channel layer; forming a third insulation layer on the semiconductor substrate to cover the sides of the gate electrode, the preliminary nanowire channel, the preliminary channel layer, and the preliminary sacrificial layer, and implanting impurities into the preliminary channel layer to convert the preliminary channel layer and the preliminary nanowire channel into a source/drain layer and a nanowire channel, respectively.