Patent ID: 7215179

Claim:
A booster circuit connecting and boosting basic charge pump cells disposed respectively at N stages, the booster circuit comprising: said basic charge pump cells each including at least a first MISFET, a second MISFET, a third MISFET, and a first capacitor, a fourth MISFET, and a second capacitor, wherein a back gate of said first MISFET is connected to a first node, and a source-drain path thereof is connected between a second node and a third node, a back gate of said second MISFET is connected to said first node, and a source-drain path thereof is connected between said first node and said second node, a back gate of said third MISFET is connected to said first node, and a source-drain path thereof is connected between said first node and said third node, one end of said first capacitor is connected to said third node, and a first clock with an amplitude of an operating voltage is inputted to the other end thereof, said third node is connected to a second node of said basic charge pump cell at a next stage, one end of said second capacitor is connected to a gate of said first MISFET, and a second clock, having a voltage amplitude larger than that of a sum of said operating voltage and a threshold voltage of said first MISFET and being a reversed phase to said first clock, is inputted to the other end thereof, and a back gate of said fourth MISFET is connected to said first node, a source-drain path thereof is connected between said second node and the gate of said first MISFET, and, for each of the N stages other than a first stage, a gate thereof is connected said one end of said second capacitor configuring said basic charge pump cell at a preceding stage.