Patent ID: 7795917

Claim:
A buffer circuit, wherein at least one part is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor, which circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge, and which circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of said second CMOS inverter being connected to the output of the circuit, and wherein the circuit also includes a first loop between the output of said second CMOS inverter and the input of said first CMOS inverter, wherein the first loop includes first means for creating an overvoltage on the two CMOS inverters, and/or a second loop between the output of said second CMOS inverter and the input of said first CMOS inverter, and wherein the second loop includes second means for creating an overvoltage on the two CMOS inverters.