Patent ID: 7286126

Claim:
An apparatus for processing a display signal in a display device, the apparatus comprising: an analog-to-digital converter converting analog R, G, and B signals into digital R, G, and B image data according to sampling clocks; a data enable signal generating portion determining a start and an end of valid data output from the analog-to-digital converter and generating a data enable signal; a scaler converting the digital R, G, and B image data output from the analog-to-digital converter into signals for a predetermined resolution wherein the scaler is synchronized, with the data enable signal generated by the data enable signal generating portion; a phase locked loop portion providing the sampling clocks to the analog-to-digital converter and the data enable signal generating portion; and a control portion providing the control signal to the phase locked loop portion and controlling the data phase of the scaler according to the data enable signal generated by the data enable signal generating portion, wherein the data enable signal generating portion comprises: a comparing portion comparing a level of input data output from the analog-to-digital converter with a threshold value, a clock counting portion counting a number of sampling clocks when a level of the input data is greater or smaller than the threshold value, and a data enable edge signal generating portion generating a rising edge of the data enable signal corresponding to the start of the valid data and a falling edge of the data enable signal corresponding to the end of the valid data, based on the counted number of sampling clocks.