Patent ID: 7256445

Claim:
An integrated circuit comprising: a semiconductor substrate of a first conductivity type having a surface; first, second and third spaced-apart lightly doped second conductivity type dopant regions in the substrate surface that form first, second, and third source-drain regions; first and second spaced-apart gates, the first gate located above and between the first and second source-drain regions and spaced therefrom by an oxide layer interrupted by a thinner tunnel oxide region, with a higher conductivity dopant region in the substrate below the tunnel oxide region, the second gate above and between the second and third source-drain regions and spaced therefrom by the oxide layer, the first and second spaced-apart gates forming portions of an EEPROM cell; and first and second highly doped second conductivity type emitter regions located above the first and third source-drain regions, the two emitter regions each forming portions of bipolar transistor devices.