Patent ID: 7627711

Claim:
A memory controller for a daisy chain of memory chips comprising a processor bus control configured to receive a request from a processor for a memory access to a memory and further configured to receive a data from the processor when the request is a write, and to transmit data to the processor when the request is a read; an address/command bus port; a data bus port; a bus clock port; an address/command generator configured to transmit an address/command word from the address/command bus port, the address/command word further comprising: a command; a packet id; and an address; and a data send/receive configured to transmit a data word to a daisy chain of memory chips, the data word containing the data sent by the processor the data word further comprising a packet ID; the data send/receive further configured to receive a data word on the data bus port from the daisy chain of memory chips; wherein the memory controller fills in a value in a packet ID in an address/command word for a write and a value in a packet ID in a data word such that a memory chip is able to associate the address command word and the data word.