Patent ID: 7126385

Claim:
An improved differential inverter ( 100 ) comprising a differential inverter ( 30 ) having a differential input for receiving a first vector of signals comprising a first input signal (DIN 1 ) and a second input signal (DIN 2 ) a differential control input for receiving a second vector of input signals comprising a first a first control signal (DC 1 ) and a second control signal (DC 2 ), a differential output for transmitting a third vector of differential signals comprising a first output signal (OUT 1 ) and a second output signal (OUT 2 ) said improved differential inverter ( 100 ) being characterized in that it further comprises a controlled bias generator ( 10 ) generating the second vector of input signals in response to a bias control signal (Cin) which is generated at an output of a voltage divider coupled to the differential output of the differential inverter ( 30 ) said bias control signal being indicative of a DC voltage of the of the differential output wherein the differential inverter ( 30 ) comprises a first transistor pair and a second transistor pair each of the transistor pairs comprising a n-type MOS transistor (T 2 ) coupled to a p-type MOS transistor (T 1 ) via a drain to drain connection, the n-type transistor (T 2 ) having a first control terminal (G 2 ) for receiving the second control signal (DC 2 ) via a third resistor means (R 3 ), the p-type transistor (T 1 ) having a second control terminal (G 1 ) for receiving the first control signal (DC 1 ) via a fourth resistor means (R 4 ).