Patent ID: 7827021

Claim:
A tool for simulating operation of a computer having a system for modeling a behavior of an LPAR operating in a time slice dispatch mode, the modeling system comprising: a system for calculating a resource percentage, wherein the resource percentage represents a percentage of total resources allocated to the LPAR, wherein the resource percentage is equal to: 100%−a percentage of resources allocated to all other LPARs running in the simulated computer; a system for calculating a time slice percentage for the LPAR based on the resource percentage and CP (central processor) data, wherein: time ⁢ ⁢ slice ⁢ ⁢ percentage = ( resource ⁢ ⁢ percentage ) × ( # ⁢ ⁢ of ⁢ ⁢ physical ⁢ ⁢ CPs ) ( # ⁢ ⁢ of ⁢ ⁢ logical ⁢ ⁢ CPs ) ; a system for determining a CP (central processor) percentage, wherein the CP percentage represents a percentage of time that all physical CPs in the computer being modeled have been allocated to the LPAR; a system for determining causing the computer simulation not to dispatch CPs to the LPAR for a current modeling interval if the CP percentage is greater than the time slice percentage; and a system for outputting and displaying the behavior of the modeling.