Patent ID: 7429507

Claim:
A method of manufacturing a semiconductor device comprising, in the recited order, the steps of: preparing a semiconductor substrate having a memory cell area and a logic circuit area defined on a principal surface of the semiconductor substrate; forming an element separation structure made of insulating material in a partial area of the principal surface of the semiconductor substrate to define active regions; forming first gate insulating films in areas of the principal surface of the semiconductor substrate where the element separation structure is not formed; forming a first conductive film covering the element separation structure and the first gate insulating films; removing the first conductive film in the memory cell area; forming a capacitor dielectric film on a surface of the first conductive film; forming a second conductive film on the capacitor dielectric film and on the semiconductor substrate; patterning the second conductive film to leave an upper electrode over the element separation structure and to leave a plurality of word lines serving as gate electrodes in the memory cell area; patterning the capacitor dielectric film and the first conductive film to leave a lower electrode made of the first conductive film, in which the lower electrode is left in a pattern inclusive of the upper electrode as viewed along a direction normal to the semiconductor substrate, a gate electrode made of the first conductive film is left over the active region in the logic circuit area, and the capacitor dielectric film is left between the upper and lower electrodes; depositing an insulating film over the whole surface of the semiconductor substrate; etching the insulating film to leave side wall insulating films on side walls of the gate electrodes in the logic circuit area and leave an embedding insulating member embedding spaces between the word lines; implanting impurities into a substrate surface layer on both sides of the gate electrode in the logic circuit area using the side wall insulating films and the gate electrodes in the logic circuit area as a mask; forming a metal silicide film on an upper surface of the gate electrode in the logic circuit area and on a surface of the semiconductor substrate on both side of the gate electrode.