Patent ID: 8180919

Claim:
A method of employing a processor in an integrated circuit implemented in a data communication network, said method comprising: loading configuration data associated with a plurality of framers including a Synchronous Digital Hierarchy (SDH) framer; configuring said SDH framer in programmable circuits of said integrated circuit based upon said configuration data associated with said SDH framer; configuring a plurality of soft processors in said programmable circuits of said integrated circuit, wherein each said soft processor of said plurality of soft processors is associated with a framer of said plurality of framers; providing an embedded processor on said integrated circuit; controlling said plurality of framers with said plurality of soft processors; generating SDH output data based upon said controlling said plurality of framers with said plurality of soft processors; monitoring, by each said soft processor of said plurality of soft processors, alarm conditions of an associated framer; aggregating, by said embedded processor, said alarm conditions; and outputting said aggregated alarm conditions by way of a host interface to a host processor of a circuit board having said integrated circuit.