Patent ID: 7522458

Claim:
A memory comprising: a memory array: and an access control circuit for controlling access to said memory array, wherein said access control circuit comprises: an access command circuit that receives a first and a second input signal and outputs an access command signal enabling commencement of memory access; and a command discriminating circuit that receives said first and second input signals, a third and a fourth input signals, and a clock signal, and that outputs a command discriminating signal for specifying a read or a write access command signal; said third and fourth input signals comprise an output enabling (OE) signal and a write enabling (WE) signal; said command discriminating circuit outputs a signal selected from a write signal and a read signal, as said command discriminating signal; wherein said first and second input signals comprise a chip enabling (CE) signal and an address valid (ADV) signal; and said command discriminating circuit outputs a signal selected from said write signal and said read signal at a timing at which said ADV signal changes and according to an active state of said OE signal and said WE signal.