Patent ID: 7208829

Claim:
A semiconductor component arrangement, comprising: a semiconductor chip; a lower, first main electrode layer formed on a first side of the semiconductor chip; a lower control electrode layer formed on the first side; an insulation layer formed on the first side between the lower, first main electrode layer and the lower control electrode layer and which partly covers the lower, first main electrode layer; an upper first main electrode layer formed on the lower, first main electrode layer; an upper control electrode layer formed on the lower control electrode layer and the insulation layer and extends on the insulation layer partly above the lower, first main electrode layer; a second main electrode layer formed on a second side of the semiconductor chip; a first connection device having a first conductive terminal region soldered to the upper, first main electrode layer of the semiconductor component via a first solder layer; a third conductive terminal region soldered to the upper control electrode layer of the semiconductor component via a third solder layer; and a second connection device having a second conductive terminal region soldered to the second main electrode layer of the semiconductor component via a second solder layer; wherein at least one of the first connection device and the second connection device is a ceramic substrate having metal layers as conductive terminal regions on both sides, the ceramic substrates being DBC substrates.