Patent ID: 8704557

Claim:
A non-integer frequency divider circuit for use in generating frequencies in a communication device, comprising: at least four bi-stable memory devices, each having an input terminal, a clock terminal and an output terminal for outputting an output signal; wherein the at least four bi-stable memory devices are arranged in a cascaded chain, such that each bi-stable memory device following the first bi-stable memory device receives the output signal of a previous bi-stable memory device in the cascaded chain at its input terminal and such that at least one output signals of the bi-stable memory devices is used to control the input terminal of the first bi-stable memory device; and wherein the frequency divider circuit further comprises a clocking arrangement configured to provide an in-phase clock signal, a quadrature clock signal, an inverse of the in-phase clock signal, and an inverse of the quadrature clock signal, to the clock terminals of each of the at least four bi-stable memory devices, such that a combination of the output signals from the at least four bi-stable memory devices produces a frequency divided output signal of the frequency divider circuit having a frequency division ratio of fourths of the frequency of the in-phase clock signal.