Patent ID: 7330385

Claim:
An integrated semiconductor memory device that adapts evaluation performance of sense amplifiers, the device comprising: an output terminal to output a data item; a plurality of memory cells, each memory cell being configured to have a cell voltage depending on a memory state; a plurality of bit line pairs, each bit line pair comprising a first bit line and a second bit line; a plurality of sense amplifiers, each sense amplifier being configured to evaluate the cell voltage of one of the memory cells, wherein: a first memory cell is connected to a first sense amplifier via one of the bit lines of a first bit line pair, a second memory cell is connected to a second sense amplifier via one of the bit lines of a second bit line pair, the first sense amplifier is configured to evaluate the cell voltage of the first memory cell during a read access of the first memory cell, the data item at the output terminal is generated at a first level when the cell voltage of the first memory cell is evaluated by the first sense amplifier to be above a first threshold voltage, and the data item is generated at a second level at the output terminal when the cell voltage of the first memory cell is evaluated by the first sense amplifier to be below the first threshold voltage; and a second sense amplifier is configured to evaluate the cell voltage of a second memory cell during a read access of the second memory cell, the data item is generated at the first level at the output terminal when the cell voltage of the second memory cell is evaluated by the second sense amplifier to be above a second threshold voltage, and the data item is generated at the second level at the output terminal when the level of the cell voltage of the second memory cell is evaluated by the second sense amplifier to be below the second threshold voltage, the level of the second threshold voltage differing from the level of the first threshold voltage; a first controllable voltage generator to generate a first precharging voltage; and a second controllable voltage generator to generate a second precharging voltage, wherein a level of the first precharging voltage differs from a level of the second precharging voltage; wherein the first precharging voltage is supplied to the bit lines of the first bit line pair, and the second precharging voltage is supplied to the bit lines of the second bit line pair.