Patent ID: 7943454

Claim:
A method of fabricating a semiconductor device structure, comprising: forming a first field effect transistor (“FET”) and a second FET, the first FET having a first gate conductor and the second FET having a second gate conductor, the first and second gate conductors being portions of a single elongated conductive member; forming a first stressed film overlying said first and second FETs, said first stressed film applying a stress having a first value to a channel region of said first FET to enhance performance of said first FET; forming a stop layer to overlie said first stressed film; removing a portion of said first stressed film which overlies said second FET; forming a second stressed film to overlie said second FET, said second stressed film applying a stress having a second value to said second FET to enhance performance of said second FET; planarizing said first and second stressed films until said stop layer is exposed, such that said first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at said common boundary.