Patent ID: 7778104

Claim:
A semiconductor memory apparatus comprising: a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first bit line equalize signal; a column selecting unit configured to connect the positive sensing line and the negative sensing line to a first data bus and a second data bus, respectively, in response to a column selection signal; and a share control unit configured to connect the positive sensing line and a positive first bit line of the first bit line pair or a positive second bit line of the second bit line pair in response to a second bit line equalize signal, a positive share control signal and a negative share control signal, wherein, when the first bit line equalize signal is disabled, the sense amplifier configured to apply a first sense amplifier power supply voltage and a second sense amplifier power voltage or the second sense amplifier power supply voltage and the first sense amplifier power supply voltage to the positive sensing line and the negative sensing line, respectively, and when the first bit line equalize signal is enabled, the sense amplifier configured to precharge the positive sensing line and the negative sensing line with a bit line precharge voltage level.