Patent ID: 7298189

Claim:
A delay locked loop circuit comprising: a clock buffer for receiving an external clock signal; a delay selection part for receiving an output signal of the clock buffer, delaying the output signal by a predetermined time, and outputting the output signal; a delay line for receiving an output signal of the delay selection part, delaying the output signal by a predetermined time, and outputting the output signal; a first clock divider for dividing a frequency of the output signal of the clock buffer at the ratio of 1/n (n=a natural number of at least two); a second clock divider for dividing a frequency of the output signal of the delay line at the ratio of 1/n; a replica delay part for delaying an output signal of the second divider by a predetermined time; a phase comparator for comparing a phase of an output signal of the first divider with a phase of an output signal of the replica delay part; a delay controller for adjusting a delay time of the delay line in response to an output signal of the phase comparator; and a clock period detector for receiving the output signal of the first clock divider and the output signal of the replica delay part and outputting a first control signal group and a second control signal group, wherein the first control signal group is applied to the first clock divider and the second clock divider so as to delay signals applied to the first clock divider and the second clock divider, and wherein the second control signal group is applied to the delay selection part so as to adjust a delay time of the delay selection part.