Patent ID: 8193065

Claim:
A method comprising: depositing impurities into a substrate to form at least one semiconductor channel region bordered by shallow trench isolation regions below an upper surface of said substrate; forming a gate dielectric on said upper surface of said substrate over said semiconductor channel region; patterning a gate conductor on said gate dielectric over said semiconductor channel region, said gate conductor having sidewalls; forming sidewall spacers on said sidewalls of said gate conductor; patterning trenches within said semiconductor channel region using said sidewall spacers as an alignment guide, said trenches comprising interior trench sidewalls immediately below said gate conductor and exterior trench sidewalls adjacent said shallow trench isolation regions; performing an angled implant that implants a different amount of implanted material into a first interior trench sidewall on a first side of said gate conductor relative to a second interior trench sidewall on a second side of said gate conductor that is opposite said first side of said gate conductor; performing a material removal process that removes material from said first interior trench sidewall at a different rate relative to said second interior trench sidewall because of said different amount of implanted material that is implanted into said first interior trench sidewall relative to said second interior trench sidewall, such that one of said trenches is positioned closer to a midpoint of said gate conductor relative to the other of said trenches regions, said trenches comprising asymmetric trenches; and epitaxially growing source and drain regions within said asymmetric trenches, one region of said source and drain regions being positioned closer to said midpoint of said gate conductor relative to the other region of said source and drain regions, and said source and drain regions comprising a material that induces physical stress upon said semiconductor channel region.