Patent ID: 6928128

Claim:
A clock alignment circuit comprising: delay line having a plurality of delay elements, wherein each delay element of the plurality of delay elements includes a supply electrode to receive a supply voltage, to generate a delayed clock signal with respect to a reference clock signal; a comparator, coupled to the delay line, to compare the delayed clock signal and the reference clock signal and to output delay differential information, wherein the delay differential information is representative of a correction information between the reference clock signal and the delayed clock signal; charge pump circuitry, coupled to the comparator, to convert the delay differential information to a control signal, wherein the control signal is proportional to the delay differential information; an amplifier coupled to the charge pump circuitry, wherein the amplifier includes: a first input to receive the control signal; a second input to receive a feedback signal; and an output to provide the supply voltage and the feedback signal; a capacitor coupled between the supply voltage and a secondary power supply, wherein the amplifier further includes: a current mirror load having a first and a second load transistor coupled in parallel, the first and the second load transistors each having a supply electrode coupled to a first supply voltage; a bias transistor coupled to a second supply voltage, the bias transistor responding to a bias voltage to provide a bias current at a drain electrode; a first differential input transistor having a source coupled to the drain electrode of the bias transistor, wherein the first differential input transistor is coupled in series with the first load transistor; and a second differential input transistor having a source coupled to the drain electrode of the bias transistor, wherein the second differential input transistor is coupled in series with the second load transistor.