Patent ID: 7595659

Claim:
A reconfigurable chip, comprising: a plurality of data modification units that are interconnected at least two-dimensionally and runtime reconfigurable in function and interconnection, wherein at least some of the data modification units are arithmetic logic cells that each: has three inputs A, B, and C adapted for feeding to the respective arithmetic logic cell respective ones of three data words A, B, and C on respective ones of the three inputs A, B, and C; and is adapted for performing within the respective arithmetic logic cell an operation of the data word A× the data word B+ the data word C; registers adapted for receiving output data of one of the plurality of modification units and feeding the output data back for further processing in the modification unit; registers adapted for delaying arrival of data at respective ones of the plurality of modification units to synchronize the arrival of the data with an arrival of other data at the respective modification units; and multiplexers adapted for selectively bypassing registers of the reconfigurable chip to allow for an orderly data processing in runtime-delayed data; wherein the chip is one of a processing chip and a Field Programmable Gate Array chip.