Patent ID: 7112984

Claim:
A system LSI comprising: a plurality of circuit blocks including a specified block as a test object; a clock tree buffer for distributing a clock signal to the plurality of circuit blocks; a clock delay circuit provided on a clock supply route from the clock tree buffer to the specified block so as to delay the clock signal in accordance with a delay control signal; a first selector for either transferring a delay adjustment signal supplied from an outside to the clock delay circuit as the delay control signal when a test operation mode is designated by a mode signal, or supplying an internal delay setting signal to the clock delay circuit when a normal operation mode is designated by the mode signal; a second selector for either supplying a test signal to the specified block when the test operation mode is designated by the mode signal, or supplying a normal operation signal to the specified block when the normal operation mode is designated by the mode signal; and a delay setting circuit for memorizing and issuing a value of the delay adjustment signal as the internal delay setting signal, wherein the value of the delay setting signal is obtained when the specified block operates properly during a test for the specified block, and the test is carried out by sequentially changing the delay adjustment signal.