Patent ID: 7941791

Claim:
A method comprising: compiling, with a computing system, a source code program for a heterogeneous processor having a first instruction sequencer, having a first instruction set architecture; and an accelerator to the first instruction sequencer, wherein the accelerator comprises a heterogeneous sequencer with respect to the first instruction sequencer, the heterogeneous sequencer having a second instruction set architecture; the source code program having specified therein a specification for parallel execution of a region of source code for the first instruction set architecture of the processor for the first sequencer and a region of source code for the second instruction set architecture of the processor for the heterogeneous sequencer, wherein the region of source code for the second instruction set architecture is specified by a demarcation of the source code for the second instruction set architecture for parallel execution; wherein the demarcation further comprises: specification of the second instruction set architecture for the source code by an identifier for the second instruction set architecture; specification of a number of user-level threads to be spawned; definition of private and shared variables for each user-level thread; definition of actions to be taken by each user-level thread in a block of code; and definition of the descriptor for the shared variables.