Patent ID: 7470967

Claim:
A semiconductor device comprising: a SiC substrate layer; a buffer layer of a p-type SiC on the SiC substrate layer; a channel layer of n-type SiC on the buffer layer and having an upper surface opposite the buffer layer; a recess in the upper surface of the channel layer, wherein the recess comprises a first sidewall, a second sidewall opposite the first sidewall and a bottom surface; a source/drain layer of n-type SiC on the upper surface of the channel layer, wherein the source/drain layer is more heavily doped with an n-type dopant than the channel layer; a source metal contact on the source/drain layer adjacent the first sidewall of the recess, the source metal contact having an edge adjacent the first sidewall; a drain metal contact on the source/drain layer adjacent the second sidewall of the recess, the drain metal contact having an edge adjacent the second sidewall; a Schottky metal on the bottom surface of the recess, wherein the Schottky metal has a first edge adjacent the first sidewall and a second edge adjacent the second sidewall; and one or more layers of a dielectric material on the sidewalls of the recess; wherein the Schottky metal forms a rectifying junction with the channel layer; wherein the Schottky metal is aligned between the first and second sidewalls of the recess; wherein there is no lateral spacing between the first edge of the Schottky metal and the edge of the source metal contact adjacent the first sidewall; and wherein there is no lateral spacing between the second edge of the Schottky metal and the edge of the drain metal contact adjacent the second sidewall.