Patent ID: 8626996

Claim:
A solid state memory comprising: a nonvolatile storage medium comprising a first a nonvolatile memory (NVM) comprising single level cells and a second NVM comprising multi-level cells; a controller comprising a CPU, a memory, a host interface, and NVM interface, wherein the host interface is configured to receive a write command, an address, and data from a host system, the CPU is configured to perform a first assessment before the data is stored in the nonvolatile storage medium to determine whether the data is hot or, the first NVM is configured to store the data if the data is determined to be hot in the first assessment, and the second NVM configured to store the data if the data is determined to be cold in the first assessment, and the CPU is further configured to perform a second assessment, if the data is stored in the first NVM, to determine whether the stored data is hot or cold, and to migrate the data from the first NVM to the second NVM upon determining that the data is cold in the second assessment, wherein the NVM interface is operatively connected to the first NVM and the second NVM, the NVM interface and the first NVM connected through a first channel and the NVM interface and the second NVM connected through a second channel, the first channel and the second channel being separated from each other, and wherein the second assessment is performed according to a periodic interval or an idle state of the solid state memory.