Patent ID: 6960941

Claim:
A latch circuit for complementary dynamic logic, said latch circuit comprising: a first logic gate having a first input and a second input, wherein said first input is connected to a first precharged internal node of said complementary dynamic logic, and said second input is connected to a first differential output of said complementary dynamic logic; a second logic gate having a first input and a second input, wherein said first input is connected to a second precharged internal node of said complementary dynamic logic, and said second input is connected to a second differential output of said complementary dynamic logic; a third logic gate having a first input connected to an output of said first logic gate to provide a first output for said latch circuit; and a fourth logic gate having a first input connected to an output of said second logic gate to provide a second output for said latch circuit, wherein said second output is connected to a second input of said third logic gate, and said first output is connected to a second input of said fourth logic gate.