Patent ID: 8464017

Claim:
A data processing apparatus in a Massively Parallel Process Array (MPPA) system, the apparatus comprising: a scheduling processor for initiating a process for performing a task, determining an array processor and an initial memory corresponding to the process, requesting a halt release to the array processor, and requesting return of the initial memory to an address conversion table, upon receipt of a termination signal from the array processor; the array processor for performing a program of the process, determining whether allocation of an additional memory or return of a used memory is needed, and requesting allocation of the additional memory or return of the used memory to an address conversion controller according to the determination of whether allocation of the additional memory or return of the used memory is needed; the address conversion controller for, upon receipt of a request for the initial memory or allocation of the additional memory from the scheduling processor or the array processor, controlling an address converter to convert a base address of the initial memory or the additional memory to a physical address, and deleting registered information about the used memory from the address conversion table according to the request for return the used memory; and a memory pool having at least one memory with a physical address.