Patent ID: 8766836

Claim:
A sigma delta modulator comprising: a loop filter; an adder configured to accept an output of the loop filter and a dither input signal, and to combine the output of the loop filter and the dither input signal into a combined output signal; a quantizer configured to accept the combined output signal from the adder, and quantize the combined signal into a quantizer output signal; a first subtractor configured to accept the quantizer output signal and subtract the dither input signal from the quantizer output signal; a first digital-to-analog converter configured to accept an output from the first subtractor via a feedback path of the sigma delta modulator, and to convert the output from the first subtractor into an analog signal; and a second subtractor configured to accept the analog signal from the first digital-to-analog converter, and output to the loop filter a signal representing the difference of an input signal and the analog signal.