Patent ID: 8314499

Claim:
A semiconductor die package comprising: a patterned metal conductive layer having a first planar surface, a second planar surface parallel to the first planar surface, a first thickness between its first and second surfaces, and at least one conductive trace, the at least one conductive trace having a first surface at the first surface of the patterned conductive layer, a second surface at the second surface of the patterned conductive layer, and a patterned shape at the first surface of the patterned conductive layer and that extends through the first thickness of the patterned conductive layer to the second surface of the patterned conductive layer; a semiconductor die disposed over the first surface of the patterned conductive layer and electrically coupled thereto; a plurality of conductive bodies disposed at the second surface of the patterned conductive layer and electrically coupled thereto, each conductive body having a thickness that is greater than the first thickness; and a body of electrically insulating material disposed on the semiconductor die and a portion of the first surface of the patterned conductive layer, and wherein the patterned shape of the at least one conductive trace has a first portion disposed under the semiconductor die and electrically coupled to a conductive region of the semiconductor die by a conductive solder ball or conductive stud bump, wherein solder ball or conductive stud bump directly contacts both the first portion of the patterned shape and said conductive region of the semiconductor die, wherein the patterned shape further has a second portion over at least one of the conductive bodies and metallurgically bonded thereto for an electrical connection thereto, and wherein the second portion of the patterned shape is disposed away from the semiconductor die such that the second portion is not under the semiconductor die.