Patent ID: 8884300

Claim:
A semiconductor device comprising: a semiconductor layer; a first gate electrode over the semiconductor layer with a first insulating film interposed therebetween; a second gate electrode over the semiconductor layer with the first insulating film interposed therebetween; a first conductive layer over the semiconductor layer; and a second conductive layer over the semiconductor layer, wherein the semiconductor layer comprises: a first source region, a second source region, and a drain region interposed between the first source region and the second source region; a first channel region overlapping with the first gate electrode, the first channel region being interposed by and in contact with a first pair of low concentration impurity regions which are sandwiched by and in contact with the first source region and the drain region; and a second channel region overlapping with the second gate electrode, the second channel region being interposed by and in contact with a second pair of low concentration impurity regions which are sandwiched by and in contact with the drain region and the second source region, wherein the first conductive layer is electrically connected to the drain region, wherein the second conductive layer is electrically connected to the first source region and the second source region, and wherein the second conductive layer and the first gate electrode do not overlap with each other over the semiconductor layer.