Patent ID: 7769983

Claim:
A method of operating a processor operates in a plurality of states, the processor operating only in one state at a time, the method comprising: retrieving a first copy of a block of instructions from memory while the processor is operating in an initial state; pre-decoding via a first pre-decoder the first copy of the block of instructions in accordance with the initial state of the processor, producing first pre-decoded instructions; loading the first pre-decoded instructions into a cache; loading state information associated with the first pre-decoded instructions into the cache, the state information indicating that the first pre-decoded instructions were pre-decoded in accordance with the initial state of the processor; when one pre-decoded instruction of the first pre-decoded instructions in the cache is requested by the processor, determining whether a current state of the processor is the same state of the processor as the initial state of the processor by comparing the current state of the processor to the state information loaded in the cache; retrieving the one pre-decoded instruction from the cache; pre-decoding the one pre-decoded instruction via a second pre-decoder in accordance with the current state of the processor when the current state of the processor is different from the initial state of the processor; and executing the one pre-decoded instruction.