Patent ID: 7952506

Claim:
A ΔΣ-type A/D converter comprising: a first ΔΣ modulator receiving a first analog input signal and outputting a first digital signal; a second ΔΣ modulator receiving a second analog input signal based on a second clock signal into and outputting a second digital signal; and a decimation filter filtering and thinning on each of the first and second digital signal, the first ΔΣ modulator including: a first quantizer quantizing a first signal to generate the first digital signal; a first sampling stage oversampling the first analog input signal based on a first clock signal and providing a first node with an oversampled signal of the first analog input signal, a first digital-to-analog converter converting the first digital signal into a first analog feedback signal and providing the first node with the first analog feedback signal; a first dither circuit generating a first DC addition voltage and providing the first node with the first DC addition voltage; and a first integrating circuit integrating a signal on the first node to generate the first signal, the second ΔΣ modulator including: a second quantizer quantizing a second signal to generate the second digital signal; a second sampling stage oversampling the second analog input signal based on a second clock signal and providing a second node with an oversampled signal of the second analog input signal, a second digital-to-analog converter converting the second digital signal into a second analog feedback signal and providing the second node with the second analog feedback signal; a second dither circuit generating a second DC addition voltage which is different from the first DC addition voltage and providing the second node with the first DC addition voltage; and a second integrating circuit integrating a signal on the second node to generate the second signal.