Patent ID: 7594074

Claim:
A storage system, comprising: a plurality of protocol transformation units each including an interface to an external equipment, the interface converts, into a protocol within the storage system, a protocol for read and write of data exchanged with the external equipment; and a plurality of disk control units each logically including: a plurality of interface units to hard disk devices, each of the interface units converts, into a protocol within the storage system, a protocol for read and write of data exchanged with the hard disk devices, and a plurality of data caching control units having: a cache memory which stores data read from or written to the hard disk devices, a microprocessor that controls the cache memory, and a management information memory unit that stores management information of said storage system, wherein the protocol transformation units and the disk control units are connected to each other through a first interconnection, wherein the disk control units and the hard disk devices are connected to each other through a second interconnection, wherein each protocol transformation unit, upon receipt of a data write command from the external equipment, conducts a command analysis of the data write command to select a certain logical unit, in which data corresponding to data to be written as requested by the external equipment is recorded, from a plurality of logical units configured in the hard disk devices and select a certain microprocessor and a corresponding cache memory included in the data caching control unit from the plurality of data caching control units, and issues a data write request to the selected microprocessor in the data caching control unit that manages the selected certain logical unit, wherein each interface unit and each data caching control unit can be attached or detached independently of each other, wherein the microprocessor, upon receipt of the data write request, determines whether the data corresponding to the data to be written is in the cache memory by conducting a cache-hit and cache-miss function, and wherein the microprocessor, in response to a cache-hit indicating that the data corresponding to the data to be written is in the cache memory, writes the data to be written in the cache memory, thereby updating the data corresponding to the data to be written in the cache memory, and notifies the protocol transformation unit that issued the data write request of completion of the data write command.