Patent ID: 8754477

Claim:
A semiconductor device, comprising: a gate structure overlying a top surface of a semiconductor substrate; a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate; a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer; a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material; a first stressor region disposed in the semiconductor substrate; a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material; a first dislocation disposed in the first stressor region; and a second dislocation disposed in the second stressor region, wherein the first stressor region has a first horizontal distance from a center line of the gate structure and the second stressor region has a second horizontal distance from the center line of the gate structure, the second horizontal distance being greater than the first horizontal distance, and wherein the second dislocation is disposed under the first and second gate spacers and within the semiconductor substrate and the crystallized semiconductor material.