Patent ID: 7256087

Claim:
A method of fabricating an integrated circuit, the method comprising: forming a PMOS transistor, the PMOS transistor including a gate stack that includes a P+ doped gate polysilicon layer formed over a nitrided gate oxide layer, the nitrided gate oxide layer of the PMOS transistor being over a substrate; forming an NMOS transistor that is complementary to the PMOS transistor, the NMOS transistor including an N+ doped gate polysilicon layer formed over a nitrided gate oxide layer; forming a dielectric over the PMOS transistor and the NMOS transistor; forming a first level metal interconnect line over the dielectric, the first level metal interconnect line comprising a hydrogen getter material; annealing the substrate after forming the first level metal interconnect line over the dielectric but prior to encapsulating the first level metal interconnect line with a hydrogen diffusion barrier layer; and forming the hydrogen diffusion barrier layer over the first level metal interconnect to prevent hydrogen from diffusing into the nitrided gate oxide layer.