Patent ID: 7471575

Claim:
A non-volatile memory device, comprising: an array of memory cells; a plurality of read/write stacks for operating on a group of memory cells of said array in parallel, each read/write stack comprising: a stack of sense amplifiers; a set of data latches associated with each sense amplifier; a processor for processing data between any one of the stack of sense amplifiers and the associated set of data latches; and wherein said processor further comprising: an input logic selectively coupled to either a selected sense amplifiers or the associated set of data latches to retrieve data thereform, said input logic responsive to the retrieved data and a first set of control signals to generate first resultant data; a processor latch coupled to store the first resultant data; and an output logic coupled to the processor latch to receive the first resultant data and responsive to a second set of control signals to generate second resultant data, said processor selectively coupled to either the selected sense amplifier or the set of data latches to store said second resultant data thereto.