Patent ID: 7145903

Claim:
A bus architecture system on an integrated circuit comprising: a plurality of pairs of data ports, each pair of data ports defines a data in port and a data out port, and each pairs of data ports correspond to a either a bus master or a bus slave; a plurality of multiplexers in communication with each data in port; a plurality of isolated data paths connecting the data out port corresponding to a bus master to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus slave, and a plurality of isolated data paths connecting the data out port corresponding to a bus slave to each multiplexer, of said plurality of multiplexers, in communication with a data in port corresponding to a bus master, thereby providing concurrency on the system on chip design; an arbiter in communication with each multiplexer that is in communication with a data in port corresponding to a bus slave; and an address decoder in communication with each multiplexer that is in communication with a data in port corresponding to a bus master.