Patent ID: 8440508

Claim:
A process for forming an integrated circuit, comprising: providing a substrate having transistors, a first pre-metal dielectric, and a contact photoresist pattern for a contact wall seal surrounding a FeCap array; forming at least one contact wall seal that partially surrounds sides of the FeCap array that is at least partially filled with a first hydrogen barrier material wherein said first hydrogen barrier material covers the walls of said at least one contact wall seal; forming at least one metal-1 wall seal that is at least partially filled with a second hydrogen barrier material wherein said second hydrogen barrier material covers the walls of said at least one metal-1 wall seal; forming at least one metal-1 signal lead that crosses one of said at least one metal-1 wall seal; said at least one metal-1 signal lead being at least partially filled with a third hydrogen barrier material wherein said third hydrogen barrier material covers the walls of said at least one metal-1 signal lead; forming at least one via wall seal that is at least partially filled with a fourth hydrogen barrier material wherein said fourth hydrogen barrier material covers the walls of said at least one via wall seal; and forming a top plate seal over said FeCap array, said top plate seal being over and in contact with one of said at least one via wall seal.