Patent ID: 7701008

Claim:
A semiconductor-on-insulator chip comprising: multiple-gate transistors formed on an insulator layer, each multiple gate transistor comprising: a semiconductor fin having an orientation in a first direction, a gate electrode formed adjacent a channel region portion of the semiconductor fin, the gate electrode having a gate length of less than about 30 nm, and a source region and a drain region disposed within the semiconductor fin such that the channel region portion is disposed between the source region and the drain region, wherein the channel region portion is doped to a first conductivity type and the source and drain regions are doped to a second conductivity type that is different than the first conductivity type; wherein the multiple gate transistors include all of the multiple-gate transistors on the semiconductor-on-insulator chip that have the gate length of less than about 30 nm and the channel region portion of the first conductivity type; and wherein a ratio of a doping concentration in a top surface region of the semiconductor fin to a doping concentration in a sidewall region of the semiconductor fin is between about 1 and about 4.