Patent ID: 7464242

Claim:
A method for detecting load/store dependencies of load/store operations in a memory system containing at least one pipeline of operations, comprising: determining whether address value of an incoming load operation is a cache hit or a cache miss; upon a determination that the incoming load operation is the cache hit, comparing the address value of the incoming load operation to the operations in the at least one pipeline to determine an address match by using a specific address width wherein the specific address width is a quadward boundary address width; upon a determination that the incoming load operation is the cache miss, comparing the address value of the incoming load operation to the operations in the at least one pipeline to determine the address match by using a smaller address width wherein the smaller address width is a cacheline boundary address width; executing the incoming load operation if the load operation is the cache hit and shows no address match; storing the incoming load operation if the load operation is the cache miss and the address match; and executing the stored load operation after the load/store dependencies and cache dependencies have been resolved.