Patent ID: 7433980

Claim:
A method of rearranging the order of data in a circuit comprising a memory having asymmetric input and output ports, said method comprising the steps of: providing an input port of said memory having an input width and output port having an output width, wherein said output width is greater than said input width; receiving a plurality of data words in a predetermined order at an input port of said circuit, wherein each of said plurality of data words has a width corresponding to said input width and said plurality of data words is to be stored in a row of said memory over a plurality of write cycles; rearranging the order of said plurality of data words; and generating an output word based upon said rearranged plurality of data words and having a width corresponding to said output width, wherein said output word comprises said plurality of data words in an order which is different than said predetermined order and is generated during a single read cycle.