Patent ID: 7465621

Claim:
A method of fabricating a transistor having a source, drain, and a gate on a substrate, the method comprising: implanting, into a surface of the substrate, a first impurity region ( 1904 ) with a first volume and a first surface area, the first impurity region being of a first type; implanting, into a drain region of the transistor, a second impurity region ( 1912 ) with a second volume and a second surface area in the first surface area of the first impurity region, the second impurity region being of an opposite second type relative to the first type; forming a gate oxide ( 1920 ) between a source region and the drain region of the transistor, the gate oxide of the transistor being formed after implantation of the second impurity region; covering the gate oxide with a conductive material ( 1922 ); implanting, into the source region of the transistor, a third impurity region ( 1916 ) with a third volume and a third surface area and a fourth impurity region ( 1918 ) with a fourth volume and a fourth surface area in the first surface area of the first impurity region, the third impurity region being of the opposite second type, the fourth impurity region being of the first type; and implanting, into the drain region of the transistor, a fifth impurity region ( 1910 ) with a fifth volume and a fifth surface area in the second surface area of the second impurity region, the fifth impurity region being of the opposite second type.