Patent ID: 8377827

Claim:
A method for forming a gate, comprising the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer, wherein convex and concave shaped portions are formed on the sidewalls of the etched polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer with mixed gases containing oxygen and a fluorine-based gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate, wherein the isotropic plasma etching process is performed using an inductive coupled plasma process with a zero bias power, in which no electrical field and no orientation movement of the plasma are generated at the sidewalls of the etched polysilicon layer, and height differences between the top of the convex portions and the bottom of the concave portions are reduced.