Patent ID: 7456060

Claim:
A method for fabricating a nonvolatile memory device, said method comprising the steps of: forming a tunnel oxide layer on a semiconductor substrate; forming a floating gate pattern having a first and second openings on the tunnel oxide layer, the first opening having a width greater than a width of the second opening; forming an inter-gate insulating layer on the floating gate pattern; forming a drain region in the substrate adjacent to one side of the floating gate pattern, the drain region being overlapped with the floating gate pattern; forming a source region in the substrate adjacent to another side of the floating gate, said source region being apart from the floating gate; forming a gate oxide layer on a portion of an active region between the source region and the floating gate and on a sidewall of the floating gate directing toward the source region, as well as on a sidewall of the floating gate directing toward the drain region; forming field oxide layers on the source and drain regions; forming a word line passing across the floating gate; and forming a floating gate under the word line by etching the floating gate pattern with self aligned to the word line.