Patent ID: 8230382

Claim:
A method of simulating a circuit, the method comprising: representing a plurality of elements of the circuit by device models including pass/fail criteria; executing a circuit simulation program on a hardware implemented processor, the circuit simulation program configured to perform a plurality of sweeps to obtain simulation results from the device models in response to applied parameters; identifying with the circuit simulation program in the simulation results a plurality of failed elements that have failed and a second of marginally-passing elements that are about to fail based on the pass/fail criteria of the device models; identifying parameter values for each of the sweeps of the circuit simulation program; sorting the plurality of failed elements with the circuit simulation program according to a respective failure margin associated with a comparison of the parameter values with the pass/fail criteria; identifying with the circuit simulation program a first list of the plurality of failed elements ranked according to the respective failure margin; and identifying with the circuit simulation program a second list of the plurality of marginally-passing elements.