Patent ID: 8738995

Claim:
A system comprising: a memory subsystem having at least one memory device; and a memory controller to control access of the memory subsystem, wherein the memory controller is configured to store data with error correction code (ECC) information in a first portion of the memory subsystem, and to store data without ECC information in a second portion of the memory subsystem, and wherein the memory controller is configured to further: receive a request to access the memory subsystem from a requestor; convert the request into at least one memory command that is sent to the memory subsystem; and translate an address of the request into an address of the memory subsystem to include in the at least one memory command, wherein translation of the address of the request into the address of the memory subsystem is based on mapping information that accounts for a reduction in available space for data in the memory subsystem due to storage of the ECC information in the first portion.