Patent ID: 7898839

Claim:
A method of writing into a semiconductor memory device comprising: writing a low resistance state at once in resistance memory elements of memory cells to be written connected to one of a plurality of word lines; and writing a high resistance state selectively in the resistance memory element of the memory cell connected to the one of the plurality of word lines which the low resistance state has been written in and the high resistance state is to be written in, wherein the semiconductor memory device includes: a plurality of memory cells laid out in a matrix each including the resistance memory element which memorizes the high resistance state and the low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, and a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage; a plurality of bit lines which are a plurality of signal lines extended in a first direction and in parallel with each other, the respective signal lines being connected to the other ends of the resistance memory elements of the memory cells laid out in the first direction; the plurality of word lines which are a plurality of signal lines extended in a second direction intersecting the first direction and in parallel with each other, the respective signal lines being connected to gate terminals of the first transistors of the memory cells laid out in the second direction; and a plurality of second transistors which are a plurality of transistors respectively connected to the plurality of bit lines, the respective transistors having a source terminal connected via the bit line to the other ends of the resistance memory elements of the memory cells laid out in the first direction and a drain terminal a write voltage is applied to.