Patent ID: 8741708

Claim:
A method for forming a transistor, comprising: providing a substrate, wherein the substrate comprises a first region and a plurality of second regions on opposite sides of the first region; forming a first SiGe layer on the substrate; forming a first silicon layer on the first SiGe layer; forming a second SiGe layer on the first silicon layer; forming a hard mask layer on the second SiGe layer, the hard mask layer exposing the second SiGe layer within the plurality of second regions; removing the second SiGe layer and the first silicon layer within the plurality of second regions; removing the first silicon layer between the first SiGe layer and the second SiGe layer within the first region; forming an isolating layer between the first SiGe layer and the second SiGe layer within the first region; removing the hard mask layer; forming a second silicon layer within each of the plurality of second regions, wherein the second silicon layer has a top surface leveling with a top surface of the second SiGe layer; and forming a gate structure on the second SiGe layer within the first region.