Patent ID: 8665636

Claim:
A semiconductor storage device comprising: a memory cell accessible independently from a port A and a port B; a clock generating unit that generates a third clock from a first clock of the port A and a second clock of the port B; an address comparator that compares a row address of the port A with a row address of the port B; a word line control unit that, when the row address of the port A matches the row address of the port B, makes the memory cell to be accessed only from the port A by controlling a word line potential of the port A based on the third clock; and a column selector that, when the row address of the port A matches the row address of the port B, makes data to be exchanged between a bit line of the port A and the port A based on the first clock and makes data to be exchanged between the bit line of the port A and the port B based on the second clock.