Patent ID: 7340565

Claim:
A multiprocessor system conforming to a cache coherency protocol, the system comprising: a plurality of processor cores, at least two processor cores being operative to generate a source request for desired data of a cache line in response to a cache miss at a local cache; a shared cache structure that receives at least one speculative data fill by a given one of the processor cores of the multi-processor system that did not generate the source request for the desired data of the cache line and a coherent data fill in response to the source requests from the at least two processor cores for the desired data of the cache line and provides the at least one speculative data fill and the coherent data fill of the desired data to the at least two processor cores, wherein at least one speculative data fill has an undetermined coherency state; and a processor scoreboard that arbitrates the requests for the desired data amongst the plurality of processor cores, wherein a speculative data fill of the desired data is provided to each of the at least two processor cores and the coherent data fill of the desired data is provided to each of the at least two processor cores in a determined order wherein a given processor core executes program instructions employing a speculative data fill until a coherent data fill is received, and the processor core re-executes the program instructions if the coherent data fill is different from the speculative data fill.