Patent ID: 8895386

Claim:
A method of forming a semiconductor structure, comprising: providing a substrate, the substrate having a cell area and a logic circuit area; sequentially forming an oxide material layer and a first conductive material layer on the substrate in the cell area and in the logic circuit area; performing a patterning step to form a first stacked structure on the substrate in the cell area and form a second stacked structure on the substrate in the logic circuit area; forming a first spacer on a sidewall of the first stacked structure, and forming a second spacer on a sidewall of the second stacked structure; forming three first doped regions in the substrate beside the first stacked structure, and forming two second doped regions in the substrate beside the second stacked structure, wherein one of the first doped regions is at a distance from the first stacked structure; and forming a dielectric layer and a second conductive layer on the first stacked structure, wherein the dielectric layer and the second conductive layer further extend, along the sidewall of the first stacked structure, to the substrate at one side of the first stacked structure in the cell area, wherein the first stacked structure, a portion of the dielectric layer and a portion of the second conductive layer on the first stacked structure constitute a charge storage structure and the portion of the second conductive layer serves as a control gate, and another portion of the dielectric layer and another portion of the second conductive layer directly on the substrate in the cell area constitute a select transistor and the another portion of the second conductive layer serves as a select gate, and the second stacked structure is a logic transistor.