Patent ID: 8379457

Claim:
A flash memory controller comprising: a controllable delay circuit configured to receive a read strobe signal from a flash memory device and to delay the read strobe signal; a data latch, coupled to the controllable delay circuit, configured to receive the delayed read strobe signal, and to capture data from the flash memory device using the delayed read strobe signal; and a calibration circuit coupled to the controllable delay circuit, configured to instruct the controllable delay circuit to delay the read strobe signal at one of a first plurality of delay settings, receive data captured at the data latch using the read strobe signal delayed at the one of the first plurality of delay settings, select an intermediate adjustment factor from the first plurality of delay settings for the controllable delay circuit, based on an accuracy of the data captured at the data latch, determine a second plurality of delay settings based on the intermediate adjustment factor, instruct the controllable delay circuit to delay the read strobe signal at one of the second plurality of delay settings, and select a final adjustment factor for the controllable delay circuit from the second plurality of delay settings based on data captured at the data latch using the read strobe signal delayed at the one of the second plurality of delay settings.