Patent ID: 7224628

Claim:
A magnetic random access (MRAM) memory circuit comprising: one or more memory sub arrays which interface with address registers and sense amps, one or more adaptive current generators, one or more row drivers which interface with said memory sub arrays, one or more column drivers which interface with said memory sub arrays, said address registers which interface with said memory sub arrays, data registers which interface with said memory sub arrays, address buffers which interface with address multiplexers, address multiplexer which interface with said memory sub arrays, said sense amps which interface with said memory sub arrays, I/O buffers which interface with said memory sub arrays, an algorithm controller, which resides internal to said memory circuit wherein said algorithm controller is designed to test and find said MRAM memories which can be used as static random access memories, SRAMs or alternatively as electrically erasable programmable read only memories, EEPROMs or Flash EEPROMs, or an algorithm controller which resides external to said memory circuit wherein said algorithm controller is designed to test and find said MRAM memories which can be used as one time programmable, OTP, EEPROMs.