Patent ID: 8043928

Claim:
A method for determining a layout of a semiconductor wafer which includes a plurality of device chip areas arranged in matrix form, scribe lines separating the device chip areas from each other, and alignment cells formed on the scribe lines for positioning of the semiconductor wafer, said method comprising: arranging, in an X-axis direction and a Y-axis direction on a surface of the semiconductor wafer, multi chip areas each including two or more device chip areas; providing scribe lines extending in the X-axis direction and in the Y-axis direction; and arranging one or more alignment cells in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment cells being fewer than the device chip areas in each of the multi chip areas, each of the one or more alignment cells being disposed between two opposing straight edges of two adjacent ones of the device chip areas, said each of the one or more alignment cells including (a) a first alignment mark configured to have a longitudinal direction coinciding with the X axis and (b) a second alignment mark configured to have a longitudinal direction coinciding with the Y axis, the two opposing straight edges of the two adjacent ones of the device chip areas being parallel to at least one of the scribe lines, and each of the one or more alignment cells having a size smaller than a width of the scribe lines measured in a width direction of the scribe lines.