Patent ID: 7768768

Claim:
A semiconductor device, comprising: a plurality of basic power supply wirings laid in a first direction; a plurality of local power supply wirings laid in a direction crossing the first direction; a plurality of ordinary power switch cells disposed corresponding to each crossings of the plurality of basic power supply wirings and the plurality of local power supply wirings, and each of the plurality of ordinary power switch cells coupled between corresponding one of the plurality of basic power supply wirings and corresponding one of the plurality of local power supply wirings; a plurality of circuit cells coupled to one of the plurality of local power supply wirings; and a power reinforcement cell disposed correspond to specific one of the plurality of circuit cells, the power reinforcement cell including a power switch, the power switch coupled to corresponding one of the local power supply wirings, said one of the local power wiring coupled to said specific one of the plurality of circuit cells, wherein the specific circuit cell comprises a clock buffer cell.