Patent ID: 8885761

Claim:
A data processing apparatus for mapping symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream, the data processing apparatus comprising: a de-interleaver configured to read-into a memory the predetermined number of data symbols from the OFDM sub-carrier signals, and to read-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and an address generator configured to generate the set of addresses, an address being generated for each of the received data symbols for mapping the data symbol received from the OFDM sub-carrier signal into the output symbol stream, the address generator comprising a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit configured to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address of one of the OFDM sub-carriers, and a control unit configured in combination with an address check circuit to regenerate an address when a generated address exceeds a predetermined maximum valid address, wherein the permutation circuit is configured to change the permutation code, which permutes the order of the bits of the register stages to form the set of addresses from one OFDM symbol to another.