Patent ID: 7956387

Claim:
An integrated circuit comprising a transistor formed in a semiconductor substrate having a top surface, the transistor comprising: first and second source/drain regions, the first and second source/drain regions having a first conductivity type; a channel disposed between the first and second source/drain region, the channel having a second conductivity type, the second conductivity type being opposite to the first conductivity type; a gate groove defined in the top surface of the semiconductor substrate and comprising an upper and a lower groove portion; and a gate electrode for controlling an electrical current flowing in the channel in a first direction between the first and second source/drain regions, wherein the gate electrode is disposed in the lower groove portion of the gate groove and an uppermost surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate, the upper groove portion being filled with an insulating material, wherein, in a cross section perpendicular to the first direction and perpendicular to the top surface of the semiconductor substrate, the gate electrode encloses the channel at a top side and two lateral sides of the channel.