Patent ID: 7836118

Claim:
A method for mapping one or more cooperative thread arrays (CTAs) to result tiles of a result matrix to perform a matrix multiplication operation, wherein each CTA includes one or more thread groups, and each thread group in a given CTA includes a plurality of threads that are concurrently executable on a given processor core of one or more processor cores, the method comprising: defining a result tile size that specifies the number of elements in each result tile; dividing the result matrix into one or more result tiles or a combination of one or more result tiles and one or more partial result tiles based on the result tile size; determining a CTA size based on the number of threads in each thread group; defining a CTA grid based on a number of CTAs that are concurrently executable on the one or more processor cores; creating a different CTA for each position within the CTA grid to generate an array of CTAs within the CTA grid; issuing each CTA in the array of CTAs for execution on the one or more processor cores; and for each issued CTA, generating a set of tile positions within the result matrix that the CTA will traverse to compute the elements of the result matrix, wherein each tile position corresponds to a different result tile or partial result tile into which the result matrix is divided.