Patent ID: 7439626

Claim:
A chip comprising: a silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a third internal circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first local ground distribution network over said silicon substrate and in said dielectric layer, wherein said first local ground distribution network is connected to said first internal circuit and to said second internal circuit, and wherein said first internal circuit is connected to said second internal circuit through said first local ground distribution network; a second local ground distribution network over said silicon substrate and in said dielectric layer, wherein said second local ground distribution network is connected to said third internal circuit; a passivation layer over said dielectric layer; a first via in said passivation layer, wherein said first via is connected to said first local ground distribution network; a second via in said passivation layer, wherein said second via is connected to said second local ground distribution network; and a global ground distribution network over said passivation layer, wherein said global ground distribution network is connected to said first and second vias, and wherein said first and second internal circuits are connected to said third internal circuit through, in sequence, said first local ground distribution network, said first via, said global ground distribution network, said second via and said second local ground distribution network.