Patent ID: 7397697

Claim:
A non-volatile semiconductor memory comprising: an array of memory cells; drivers and decoders coupled to apply voltages to the array to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage corresponding to a range of threshold values that identifies a multibit data value written in the memory cell, wherein the ranges of threshold values that identify data values are separated from each other by at least one range of threshold values corresponding to errors in the threshold voltages of memory cells storing data; an error detection circuit that detects errors in threshold voltages of memory cells storing data, wherein in response to detecting an error in the threshold voltage of a memory cell, the error detection circuit signals for a refresh operation; a control circuit coupled to control the drivers and decoders, wherein during the refresh operation, the control circuit writes a corrected threshold voltage that corrects the error that the error detection circuit detected.