Patent ID: 8890321

Claim:
A method for fabricating a semiconductor integrated circuit (IC), the method comprising: depositing a first dielectric layer on a substrate; forming a patterned photoresist layer on the first dielectric layer to have a plurality of opaque regions with a first width and open regions with a second width; trimming the opaque region to a third width; etching the first dielectric layer through the patterned photoresist layer having the third width to form a dielectric feature; depositing a sacrificing energy decomposable layer (SEDL) on the dielectric feature; etching the SEDL to form a SEDL spacer on sides of the dielectric feature; depositing a second dielectric layer on the SEDL spacer; etching the second dielectric layer to form a dielectric spacer on sides of the SEDL spacer; and decomposing the SEDL to remove the SEDL spacer to form a trench.