Patent ID: 7437543

Claim:
A method for reducing the normal fetch time of a predicted taken branch instruction comprising the steps of: accessing an instruction cache to fetch an instruction; indexing into an entry in a buffer using bits from said instruction fetched from said instruction cache, wherein said buffer comprises a plurality of entries, wherein each of said plurality of entries comprises an address of a branch instruction, a plurality of instructions beginning at a target address of said branch instruction, prediction information for any of said plurality of instructions that are branch instructions and an address of a next fetch group; comparing an address of said instruction fetched from said instruction cache with said address of said branch instruction in said indexed entry of said buffer; selecting said plurality of instructions beginning at said target address of said branch instruction in said indexed entry of said buffer if said address of said instruction fetched from said instruction cache matches with said address of said branch instruction in said indexed entry of said buffer; determining if any of said plurality of instructions selected is a branch instruction; and loading a displacement and an address of a first of said plurality of instructions selected in a first and a second register, respectively, wherein said first of said plurality of instructions selected is a branch instruction predicted taken.