Patent ID: 8766665

Claim:
A reconfigurable logic cell, comprising: a plurality of one-bit buffers, each buffer configurable for asynchronous communication with a neighboring logic cell, each buffer capable of having a plurality of buffer states, wherein each buffer state is selected from the group consisting of logical one, logical zero, and empty, wherein the logical one and logical zero states occur when the buffer contains a data bit and the empty state occurs when the buffer does not contain a data bit, and wherein each buffer is functionally configured for receiving an input state token from the neighboring logic cell or for transferring an output state token to the neighboring logic cell; and a one-bit processor, the processor being configurable to perform a logic operation, utilizing at least one input state token received from at least one of the buffers as at least one input for the logic operation, and to produce an output state token reflecting the result of the logic operation, wherein the processor is configured to trigger performance of the logic operation whenever all buffers configured to receive input tokens are not in the empty state and all buffers configured to transfer output tokens are in the empty state, and wherein the logic operation performed by the processor and the functional configuration of the buffers is reconfigurably programmable.