Patent ID: 8108807

Claim:
A manufacturing method of a semiconductor integrated circuit, said method comprising: storing a relation between a plurality of sizes and a plurality of voltage values in a relation table, as tangibly embodied in a machine-readable storage medium on a computer; forming a plurality of macros on a chip, wherein each of the plurality of macros includes a transistor and a setting voltage generation circuit designed to apply a setting voltage to the transistor; generating a process data indicating a size of the transistor of each of the plurality of macros, using a measurement device that provides output data as input data to the computer; selecting, using a processor on the computer, a voltage value corresponding to the size of the transistor of each of the plurality of macros indicated in the process data from the plurality of voltage values as an optimum voltage value which is related to the size in the relation table; and setting the setting voltage of the setting voltage generation circuit of each of the plurality of macros to the optimum voltage value, using a delay adjustment device controlled by the computer.