Patent ID: 8612907

Claim:
An electronic design automation (EDA) system, comprising: a computer readable storage medium; and a processor in signal communication with the computer readable storage medium, the processor configured to: receive a first design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors, calculate a threshold voltage (V th ) for each of the first and second MOS transistors in the first design of the SRAM array, calculate a threshold voltage (V th ) for a third MOS transistor of a second design of an SRAM array, the second design including an SRAM cell having a read port cell including the first MOS transistor and the third MOS transistor, the third MOS transistor having at least one of a gate channel width (W g ) dimension or a gate channel length dimension (L g ) that differs from a W g or an L g dimension of the second MOS transistor, wherein the other dimensions of the other transistors in the second design of the SRAM array are the same as the dimensions in the first design of the SRAM array, simulate a response of the second design for the SRAM array if the threshold voltage of the third MOS transistor is above a threshold level, and generate a data file representing a physical layout of the SRAM array on a semiconductor wafer.