Patent ID: 7745294

Claim:
A method of fabricating an integrated circuit including at least one drain extended MOS (DEMOS) transistor, comprising: providing a substrate having a semiconductor surface, said semiconductor surface comprising at least a first surface region that provides a first dopant type; forming a patterned masking layer on said first surface region, wherein at least one aperture in said masking layer is defined; etching said first surface region to form at least one trench region corresponding to a position of said aperture; implanting a dopant of said first dopant type to raise a concentration of said first dopant type in a first dopant type drift region of said first surface region located below said trench region; after said implanting, filling said trench region with a dielectric fill material; forming a body region having a second dopant type in a portion of said first surface region; forming a gate dielectric over a surface of said body region and said first surface region; forming a patterned gate electrode layer over said gate dielectric; forming a source region of said first dopant type in said body region; and forming a drain region of said first dopant type in said first surface region on a side of said at least one trench region opposite to said source region.