Patent ID: 8258878

Claim:
A phase-locked loop (PLL), comprising: a first phase detecting circuit, for detecting a first phase difference between an input data signal and a first feedback signal, and generating a detection output signal according to the phase difference; a first loop filter, coupled to the first phase detecting circuit, for generating a first voltage-controlled oscillator (VCO) control signal according to the detection output signal; a first voltage-controlled oscillator (VCO), coupled to the first loop filter, for generating an output data signal according to the first VCO control signal; a clock generating circuit, for generating a first clock signal; a first mixer, coupled to the first VCO and the clock generating circuit, for mixing the output data signal and the first clock signal to generate the first feedback signal; and a control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal and calculating a gain of the first VCO according to the first VCO control signal, comprising: a first comparator, for comparing the first VCO control signal with a first reference voltage to generate a first comparison result; a second comparator, for comparing the first VCO control signal with a second reference voltage to generate a second comparison result; and an adjusting circuit, for adjusting the first clock signal according to the first comparison result to obtain a first reference frequency when the first VCO control signal approximately equals to the first reference voltage, adjusting the first clock signal according to the second comparison result to obtain a second reference frequency when the first VCO control signal approximately equals to the second reference voltage, and calculating the gain of the first VCO according to the first reference voltage the second reference voltage, the first reference frequency, and the second reference frequency.