Patent ID: 7495957

Claim:
A nonvolatile semiconductor memory device comprising: a nonvolatile memory cell that can be electrically programmed, read-out and erased and which is divided into a plurality of blocks; a block address decode section for selecting one of the plurality of blocks; a selected block data storage section which is provided in the block address decode section, the selected block data storage section storing erasure block data, in an operation for simultaneously erasing the plurality of blocks in a well of the nonvolatile memory cell, or defective block data in operations other than the operation for simultaneously erasing the plurality of blocks in the well of the nonvolatile memory cell; and a set section and a reset section, which control stored data in the selected block data storage section according to operations so that the selected block data storage section stores either the defective block data or the erasure block data; wherein: the reset section erases the defective block data stored in the selected block data storage section depending on operation timing for simultaneously erasing the plurality of blocks; and the set section sets the defective block data in the selected block data storage section after the data selected block data storage section is erased, depending on a timing of an operation other than the operation for simultaneously erasing the plurality of blocks.