Patent ID: 7573535

Claim:
An image data processing circuit comprising: data writing means for writing received image data into an image data memory in turn; data reading means for reading image data from said image data memory in response to read addresses; and error detection means for detecting a receive error, wherein said data reading means selectively performs a still image reading mode and a video reading mode, said still image reading mode causing said data reading means to read the image data while temporarily fixing the read addresses within an error occurrence interval, and said video reading mode causing said data reading means to read the image data while changing the read addresses in the order of writing the image data into said image data memory, said image data processing circuit further comprising: error history storage means for storing, as error history information, a status of occurrence of a receive error based on the detection results of said error detection means; and control means for detecting recovery from the receive error based on the detection results and controlling said data reading means based on the error history information stored in said error history storage means in response to the detection.