Patent ID: 6995049

Claim:
A method for forming a silicon-on-insulator FET having a contact that provides a fixed potential to a substrate, the method comprising: providing an insulating layer on the substrate; forming a silicon layer on the insulating layer; forming a first through-hole that passes through the silicon layer and the insulating layer; filling the first through-hole with a first conductive contact layer, the first conductive contact layer being electrically connected to the substrate; forming an isolating layer in the silicon layer and surrounding the first conductive contact layer, the isolating layer being spaced apart from the first conductive contact layer with the silicon layer therebetween; forming a transistor in the silicon layer after said filling the first through-hole; forming an interlayer-insulating layer overlying the silicon layer, the first conductive contact layer, and the transistor; forming a second through-hole in the interlayer-insulating layer to expose the first conductive contact layer; and filling the second through-hole with a second conductive contact layer.