Patent ID: 7391672

Claim:
A method for sequentially accessing a memory having (m+1) bit lines and at least one row of transistors, wherein m is a positive integer, the at least one row of transistors comprises m transistors, the x th transistor has a first terminal coupled to the x th bit line and a second terminal coupled to the (x+1) th bit line, and x is a positive integer smaller than or equal to m, the method comprising the steps of: equalizing voltage levels of the first terminals and the second terminals of the transistors to a ground voltage in a pre-discharge period; transforming the voltage level of the first terminal of the n th transistor into a source voltage, transforming the voltage level of the second terminal of the n th transistor into a drain voltage, and transforming the voltage level of the second terminal of the (n+1) th transistor into an isolation voltage in an n th reading period, wherein n is a positive integer smaller than m; and transforming the voltage level of the first terminal of the m th transistor into the source voltage, and transforming the voltage level of the second terminal of the m th transistor into the drain voltage in an m th reading period, wherein the source voltage is equal to the ground voltage.