Patent ID: 7615436

Claim:
A method of making a floating gate transistor, comprising: providing a semiconductor active area; forming a tunnel dielectric layer over the active area; forming a floating gate layer over the tunnel dielectric layer; forming a first photoresist mask over the floating gate layer; patterning the floating gate layer using the first photoresist mask to form a floating gate rail; doping the active area using the floating gate rail as a mask to form source and drain regions in the active area; forming an intergate insulating layer adjacent to lower portions of side surfaces of the floating gate rail; forming a control gate dielectric layer over and adjacent to upper portions of the side surfaces of the floating gate rail; forming a control gate layer over the control gate dielectric layer; forming a second photoresist mask over the control gate layer; and patterning the control gate layer, the control gate dielectric layer, the floating gate rail, the tunnel dielectric layer and the active area using the second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.