Patent ID: 6924680

Claim:
A delay locked loop (DLL) circuit for phase matching of a periodic input signal, comprising: a variable delay unit; a delay element; a regulation unit having a regulation device for setting an input signal delay in the delay unit and a comparator unit for generating a phase signal in each signal cycle, wherein the state of the phase signal indicates a lead-lag relation between the input signal and a delayed signal which has been delayed by the variable delay unit and the delay element, the phase signal is provided to the regulation device during a steady-state operating phase, and the regulation device adjusts the delay of the variable delay unit during an initial transient phase until a change in the sate of the phase signal is detected indicating a change in the lead-lag relation between the input signal and the delayed signal; and a filter circuit for providing a filtered phase signal to the regulation device during the initial transient phase, wherein the filter circuit changes the state of the filtered phase signal to the state of the phase signal only when a different state of the phase signal with respect to the state of the filtered phase signal has been detected for a predetermined number of successive signal cycles.