Patent ID: 8577948

Claim:
An apparatus comprising: multiply accumulate (MAC) unit to perform a multiply and accumulate operation on first, second and third operands, the MAC unit including: an exponent compute datapath to determine a difference based on an exponent portion of the first, second, and third operands, the exponent compute datapath having a first compressor to receive the first, second and third operands and to output a first difference having a first portion and a second portion, an adder coupled to the first compressor to generate the difference using the first and second portions of the first difference, a first shifter to shift a mantissa of the third operand by a first amount if the difference is within a threshold range, a second shifter to shift the third operand mantissa by a second amount, and a third shifter to shift the third operand mantissa by a third amount, if the difference is outside the threshold range; a multiplier including a multiplication tree, wherein the exponent compute datapath is to provide the shifted third operand mantissa to the multiplier if the difference is within the threshold range; a second compressor to compress an output of the multiplier and the shifted third operand mantissa if the difference is outside the threshold range, wherein the multiplier output is not to be compressed in the second compressor if the difference is within the threshold range; a first normalizer to normalize the multiplier output if the difference is within the threshold range; a second normalizer to normalize the second compressor output if the difference is outside the threshold range; a computation unit to receive the first and second normalizer outputs and to generate a final value for the multiply and accumulate operation therefrom.