Patent ID: 7682977

Claim:
A method of forming trench isolation, comprising: providing isolation trenches within a semiconductor substrate; depositing and solidifying a liquid within the isolation trenches to form a solidified dielectric within the isolation trenches, the solidified dielectric comprising carbon and silicon, the solidified dielectric comprising an elevationally outer portion and an elevationally inner portion within the isolation trenches; removing carbon from the outer portion of the solidified dielectric and not from the inner portion of the solidified dielectric to form the inner and outer portions to be of different compositions; after the removing, using the different compositions of the inner and outer portions in etching the solidified dielectric outer portion selective to and effective to expose the solidified dielectric inner portion, the solidified dielectric inner portion being retained; after the etching, depositing dielectric material over the solidified dielectric inner portion to within the isolation trenches; and forming floating gate transistors of NAND unit cells of an array of NAND memory circuitry intermediate adjacent pairs of the isolation trenches.