Patent ID: 8004297

Claim:
An isolation circuit, comprising: a first transistor configured for connection to a supply voltage via a first terminal; a register connected to the first transistor; a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register; and wherein the resistor is connected to the second terminal and the second terminal is coupled to testing circuitry; and wherein the status of the register controls a state of the second transistor such that: a first amount of current is drawn, in response to a particular potential applied to the first terminal, when a die to which the isolation circuit is connected is a good die; and a different amount of current is drawn, in response to the particular potential applied to the first terminal, when the die to which the isolation circuit is connected is a bad die.