Patent ID: 7885115

Claim:
A method of operating a NAND-type non-volatile memory device, the NAND-type non-volatile memory device having a plurality of memory transistors coupled with a plurality of bit lines and a plurality of word lines, the method comprising: determining a selected bit line for programming and unselected bit lines for preventing programming from the plurality of bit lines; applying an inhibiting voltage to at least one inhibiting word line chosen from the plurality of word lines, wherein the at least one inhibiting word line includes a first word line positioned nearest to a string selection line; and applying a programming voltage to a selected word line chosen from the plurality of word lines such that data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit lines, wherein the memory transistor coupled with the selected word line and the selected bit line and the memory transistors coupled with the unselected bit lines are chosen from the plurality of transistors.