Patent ID: 7570087

Claim:
A switching drive circuit for full-bridge switching circuit, comprising: an input circuit receiving an input signal; a divide-by-two circuit coupled to the input circuit to generate a divided signal in response to the input signal; a first delay circuit coupled to the input circuit to generate a first delay signal with a first delay time in response to the enable of the input signal; a second delay circuit coupled to the input circuit to generate a second delay signal with a second delay time in response to the disable of the input signal; a switching signal generator coupled to the input circuit, the divide-by-two circuit, the first delay circuit and the second delay circuit to generate a first switching signal, a second switching signal, a third switching signal and a fourth switching signal in response to the input signal, the first delay signal, the second delay signal and the divided signal; and a delay terminal programming a value of the first delay time; wherein the pulse width of the first switching signal and the third switching signal are generated in proportion to the pulse width of the input signal, when the divided signal is turned on, the first switching signal is enabled after the first delay time once the input signal is enabled, the fourth switching signal is disabled in response to the enable of the input signal, the fourth switching signal is enabled after the second delay time once the first switching signal is disabled; when the divided signal is turned off, the third switching signal is enabled after the first delay time once the input signal is enabled, the second switching signal is disabled in response to the enable of the input signal, the second switching signal is enabled after the second delay time once the third switching signal is disabled.