Patent ID: 7149877

Claim:
A byte execution unit, comprising: a plurality of byte units, wherein each byte unit comprises: a plurality of population counters each coupled to receive a portion of a first operand and configured to produce a population output signal indicative of a number of logic ones in the corresponding portion of the first operand; a first compressor unit coupled to receive a portion of the first operand and configured to produce a first plurality of compressor output signals dependent upon the first operand; a second compressor unit coupled to receive a portion of the second operand and configured to produce a second plurality of compressor output signals dependent upon the second operand; adder input multiplexer logic coupled to receive the population output signals and the first and second pluralities of compressor output signals as data input signals, and a first plurality of control signals, and configured to produce a portion of the data input signals as output signals dependent upon the first plurality of control signals; adder logic coupled to receive the output signals produced by the adder input multiplexer logic and configured to produce a plurality of adder output signals dependent upon the output signals produced by the adder input multiplexer logic; and result multiplexer logic coupled to receive the adder output signals as data input signals, and a second plurality of control signals, and configured to produce a portion of the data input signals as a result signal dependent upon the second plurality of control signals; wherein the byte execution unit is coupled to receive byte instruction information, and wherein the first and second pluralities of control signals are indicative of the byte instruction information, and wherein the byte instruction information specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation.