Patent ID: 8461894

Claim:
An integrated circuit having a configurable delay element for generating an output signal as a delayed version of an input signal, the delay element comprising: a first stage including: a first delay chain having N buffers connected to receive the input signal and to generate N differently delayed versions of the input signal; and an (N×1) first mux connected to receive the N versions of the input signal from the buffers and to output one of the N versions as a first-stage output signal; and a second stage including: a second delay chain having M sub-chains of buffers connected to receive the first-stage output signal and to generate M differently delayed versions of the first-stage output signal, wherein each sub-chain has a first buffer implemented with logic circuitry that receives a sub-chain control signal that selectively disables the sub-chain; and a second mux connected to receive the M versions of the first-stage output signal from the M sub-chains and to output one of the M versions as a second-stage output signal.