Patent ID: 7015093

Claim:
A method of fabricating an integrated circuit, comprising the steps of: providing a semiconductor body having a top metal interconnect level formed thereon, said top metal interconnect level having a first and a second metal interconnect line; depositing a material over said top metal interconnect level; patterning and etching said material to expose a portion of said top metal interconnect level; forming a capacitor on said exposed portion of said top metal interconnect level, wherein said first metal interconnect line is protected by said material during said step of forming said capacitor, wherein the step of forming said capacitor comprises the steps of: depositing a bottom electrode material on said exposed portion of said top metal interconnect level; forming a capacitor dielectric over said bottom electrode material; depositing a top electrode material over said capacitor dielectric; and patterning and etching said top electrode material, said capacitor dielectric, and said bottom electrode material to form said capacitor; forming a protective overcoat over said top electrode and said top metal interconnect level; and forming a cap partially over said protective overcoat, said cap electrically connecting said top electrode material and said second metal interconnect line.