Patent ID: 7074721

Claim:
A method for forming an ultra thick dual damascene copper feature comprising the steps of: providing a semiconductor process wafer comprising via openings formed in a first dielectric insulating layer including an overlying etch stop layer; forming a second dielectric insulating layer thicker than the first dielectric insulating layer having a thickness of greater than about 1.0 microns over the first silicon oxide dielectric insulating layer; photolithographically patterning and anisotropically etching a trench opening having a width of greater than about 1 micron extending through the second dielectric insulating layer to the first dielectric insulating layer to encompass and expose at least one of said via openings to form a dual damascene opening; forming a barrier layer to line the dual demascene opening; forming a copper seed layer; carrying out an electrochemical copper deposition process to fill the dual damascene opening with a copper layer, wherein the ECD process comprises sequential deposition followed by partial removal of a portion of the copper layer deposition to reversed current flow; carrying out a first atmospheric ambient annealing process to anneal the copper layer; carrying out a CMP process to remove the copper layer and the barrier layer above the trench level; and, carrying out a second annealing process in an oxygen-free ambient to anneal the copper layer.