Patent ID: 8381150

Claim:
A method for efficiently performing a multithreaded analysis of a timing graph of a circuit comprising: a. using a computer, identifying a plurality of timing analysis tasks comprising performing a common path pessimism removal and computer critical paths for timing reports and identifying associated sub-graphs of said timing graph of said circuit upon which each timing analysis task is to be performed; b. creating a plurality of child computational threads and assigning thereto at least one of said identified timing analysis tasks; c. creating in each of said plurality of child threads a thread-specific graph replica (TSGR) of said associated sub-graph of said timing graph of said circuit on which said at least one timing analysis task assigned thereto is to be performed; d. performing in each child thread said at least one timing analysis task assigned thereto, wherein all timing data generated and stored in said performance is stored in said TSGR of said associated sub-graph of said timing graph; and e. transferring results from each of said timing analysis task performances in said child threads back onto said timing graph.