Patent ID: 8363448

Claim:
A semiconductor memory device comprising: a memory cell comprising a variable resistance element whose resistance varies by application of a voltage; a power supply circuit which outputs the voltage to be applied to the memory cell; an interconnection which is formed between the power supply circuit and the memory cell and supplies the voltage output from the power supply circuit to the memory cell; wherein the interconnection further comprises at least a first segment between a selection circuit and the power supply; a discharging circuit connected to the interconnection; a sense amplifier which detects information stored in the memory cell according to the voltage of the interconnection; and the selection circuit which switches a state between the interconnection, the sense amplifier, and the memory cell to one of a connection state and a disconnection state, wherein, in a first discharge operation, the discharging circuit discharges electric charge accumulated in the interconnection after a first operation of applying the voltage to the memory cell is ended and, in a second discharge operation, before a second operation of applying the voltage to the memory cell next is started, wherein the discharging circuit discharges electric charge accumulated in the interconnection when the selection circuit sets the connection state, and then the discharging circuit discharges the electric charge accumulated in the first segment when the selection circuit sets the disconnection state.