Patent ID: 8647948

Claim:
A method of manufacturing a trench-gate power MOSFET comprising: (a) a semiconductor substrate having a first main surface and a second main surface; (b) a drift region having a super junction structure in which a plurality of column regions each of a first conductivity type and a plurality of column regions each of a second conductivity type which are provided in the semiconductor substrate are alternately formed; (c) a drain region of the first conductivity type provided in a semiconductor back surface area of the semiconductor substrate closer to the second main surface; (d) a metal drain electrode provided over the second main surface of the semiconductor substrate; (e) a body region of the second conductivity type provided in a semiconductor top surface area of the semiconductor substrate closer to the first main surface; (f) a trench extending from within each of the plurality of column regions each of the first conductivity type through the body region and reaching the first main surface of the semiconductor substrate; (g) a source region of the first conductivity type which is the semiconductor top surface area of the semiconductor substrate closer to the first main surface and provided in the body region; (h) a trench gate electrode provided in the trench via a gate insulating film; (i) a SiGe epitaxial region of the second conductivity type provided closer to the first main surface of the semiconductor substrate so as to oppose the trench gate electrode with the body region being interposed therebetween; and (j) a metal source electrode provided over the first main surface of the semiconductor substrate so as to be electrically coupled to the source region, the method of manufacturing the trench-gate power MOSFET comprising the steps of: (x1) forming the super junction structure on the top surface side of the silicon-based wafer of the first conductivity type; (x2) forming the body region of the second conductivity type over the super junction structure on the top surface side of the silicon-based wafer; (x3) forming a trench to be filled with the SiGe epitaxial region in the body region so as to leave the body region between the trench to be filled with the SiGe epitaxial region and the trench gate electrode; and (x4) filling the trench to be filled with the SiGe epitaxial region by selective epitaxial growth.