Patent ID: 7795644

Claim:
A method for fabricating a semiconductor device with selective stress memory effect thereon, comprising: providing a semiconductor substrate with a first device region and a second device region, both the first device region and the second device region having a first doped region and a second doped region separated by an insulation; forming a PMOS transistor and an NMOS transistor on both the first and second device regions respectively, the PMOS transistor having an oxide-nitride-oxide (ONO) structure on sidewalls of a gate electrode on the first doped region and the NMOS transistor having an oxide-nitride-oxide (ONO) structure on sidewalls of a gate electrode on the second doped region; forming a silicon oxide layer covering the NMOS transistor and the PMOS transistor on both the first and second device regions; forming a silicon nitride layer on the silicon oxide layer on both the first and second device regions; thinning part of the silicon nitride layer overlying the PMOS transistor on both the first and second device regions such that the silicon nitride layer on the NMOS transistor is thicker than that on the PMOS transistor, thereby causing the selective stress memory effect on the NMOS and PMOS transistors respectively; removing the silicon oxide layer and the silicon nitride layer over the second device region, while retaining the silicon oxide layer and the silicon nitride layer over the first device region; and silicidizing the PMOS transistor and the NMOS transistor over the second device region.