Patent ID: 7701253

Claim:
A circuit for decreasing latency of a logic gate having an input, an output and a nominal latency, the circuit comprising: a pull-up booster circuit that assists the logic gate in a logic zero to a logic one transition on the output comprising: an input node configured to receive a logic state transition; a first switch element configured to chance to a conductive state in response to the logic state transition; a first node having a stored charge arranged to transfer the stored charge to an output node through the first switch element in response to the logic state transition, the transfer of stored charge decreasing the nominal latency of the logic gate; a second switch element coupled to the first node and configured to precharge the first node prior to the logic state transition; a third switch element coupled to the first node and configured to provide an additional charge to the output node during the logic state transition; and the logic gate electrically coupled in parallel with the pull-up booster circuit, wherein the logic gate comprises one of the following logic gates: a plurality of serially coupled inverters; an AND gate; or a latch.