Patent ID: 7605665

Claim:
A phase-locked loop (PLL), configured to receive a reference signal, comprising: a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal; a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal; and a fractional frequency divider configured to arrange the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π, wherein the fractional frequency divider is configured to generate the divided feedback signal by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs, and wherein a phase offset of the first voltage controlled oscillator output is greater than a phase offset of the second voltage controlled oscillator output.