Patent ID: 7111155

Claim:
A computation unit comprising: a register file for storing operands; first and second operand buses coupled to said register file, each simultaneously carrying a high operand and a low operand; a first execution unit for performing a first operation on first and second operands of a specified word width in response to an instruction, the specified word width of the first and second operands being less than a width of each operand bus; a first data selector, responsive to a first operand select value contained in a first field of the instruction, for selecting the first operand from the high operand and the low operand on said first operand bus and for supplying the first operand to said first execution unit; a second data selector, responsive to a second operand select value contained in a second field of the instruction, for selecting the second operand from the high operand and the low operand on said second operand bus and for supplying the second operand to said first execution unit; a second execution unit for performing a second operation on third and fourth operands of the specified word width in response to the instruction, the specified word width of the third and fourth operands being less than the width of each operand bus; a third data selector, responsive to a third operand select value contained in a third field of the instruction, for selecting the third operand from the high operand and the low operand on said first operand bus and for supplying the third operand to said second execution unit; and a fourth data selector, responsive to a fourth operand select value contained in a fourth field of the instruction, for selecting the fourth operand from the high operand and the low operand on said second operand bus and for supplying the fourth operand to said second execution unit, wherein each of the data selectors selects a subset of bits from a single operand bus, wherein the first and third data selectors select respective subsets of bits from the first operand bus and wherein the second and fourth data selectors select respective subsets of bits from the second operand bus.