Patent ID: 7330993

Claim:
A computer system comprising: a bus; and a chipset, coupled to the bus, having: an input/output (I/O) buffer, coupled to the bus, to transmit an output signal from the chipset via the bus; a slew rate detection mechanism, coupled to the bus, to receive the output signal transmitted from the I/O buffer, to detect a slew rate of the output signal and to generate a signal indicating a status of the slew rate, including: a reference current generator to generate a reference current; a comparator to compare the received signal current to the reference current a first converter to convert the signal current to a signal voltage; and a second converter, coupled to the reference current generator and the comparator to convert the reference to a reference voltage; and control logic, coupled to the slew rate detection mechanism, to receive the signal and to adjust the slew rate based upon the state of the signal.