Patent ID: 7648908

Claim:
A method for forming an inlaid interconnect, comprising the steps of: (a) forming a groove for an interconnect in an insulating layer formed on a semiconductor substrate; (b) forming a barrier metal layer on the insulating layer by an atomic layer deposition process so as to cover side walls and a bottom of the groove; (c) forming an impurity layer in or on a surface of the barrier metal layer, the impurity layer containing an impurity element; (d) alloying the barrier metal layer and the impurity layer; (e) forming a Cu seed layer on the alloyed barrier metal layer and then forming a Cu plating layer so as to fill the groove; (f) removing part of the Cu plating layer, part of the Cu seed layer, and part of the alloyed barrier metal layer located on the insulating layer so as to expose a surface of the insulating layer, thereby forming, in the groove, an inlaid interconnect layer including the Cu seed layer and the Cu plating layer; and (g) causing thermal diffusion of the impurity element existing in the alloyed barrier metal layer into the inlaid interconnect layer.