Patent ID: 8476943

Claim:
A semiconductor device, comprising: a clock input unit configured to receive a system clock and a data clock externally; a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference; a phase detecting unit configured to detect phase differences between one of the plurality of multi-system clocks and the data clock to generate a training information signal in response to the detection result; and a signal transmitting unit configured to transmit the training information signal, wherein the phase detecting unit includes: a plurality of phase comparing units configured to compare phases between each of the plurality of multi-system clocks and the data clock, respectively, to output a plurality of comparison signals; and a logic level changing unit configured change a logic level of the training information signal in response to the plurality of comparison signals, wherein the data clock and the plurality of multi-system clocks have the same frequency.