Patent ID: 8111540

Claim:
A semiconductor memory device comprising: a first bit line and a second bit line provided in the same level layer above a semiconductor substrate, and extending in a first direction so as to be adjacent to each other; a first MOSFET provided on the semiconductor substrate and disposed under the first bit line; a second MOSFET provided on the semiconductor substrate and disposed under the second bit line; a first variable-resistance element disposed under the first bit line, comprising one terminal electrically connected to one end of a current path of the first MOSFET, and comprising a resistance which changes according to stored data; a substantially vertical first contact configured to electrically connect the one terminal of the first variable-resistance element to the one end of the current path of the first MOSFET, wherein the first variable-resistance element is provided directly on one end of the first contact and a source or drain region of the first MOSFET is provided directly on another end of the first contact; a second variable-resistance element disposed under the second bit line and comprising one terminal electrically connected to one end of a current path of the second MOSFET; a substantially vertical second contact configured to electrically connect the one terminal of the second variable-resistance element to the one end of the current path of the second MOSFET, wherein the second variable-resistance element is provided directly on one end of the second contact and a source or drain region of the second MOSFET is provided directly on another end of the second contact; and a first interconnect layer provided on the first variable-resistance element, configured to electrically connect the first bit line to another terminal of the first variable-resistance element, and configured to electrically connect the first bit line to another end of the current path of the second MOSFET.