Patent ID: 7521298

Claim:
A method of fabricating a thin film transistor (TFT) array panel, comprising: providing an insulating substrate with a first metal layer formed thereon; defining a plurality of gate electrodes, a plurality of lower electrodes of storage capacitors, a plurality of scan lines, and a plurality of scan line pads with a first mask; forming a gate insulator layer, an a-Si layer, and an N+ a-Si layer on the first metal layer; defining patterns of the a-Si layer and the N+ a-Si layer with a second mask to form a plurality of island regions on the gate electrodes; forming a transparent electrode layer and a second metal layer on the N+ a-Si layer and the gate insulator layer; defining a plurality of drain electrodes, a plurality of source electrodes, a plurality of upper electrodes of storage capacitors, a plurality of pixel electrodes, a plurality of data lines, and a plurality of data line pads with a third mask, wherein the data lines and the scan lines define a plurality of pixel display regions; fracturing the N+ a-Si layer between each pair of the drain/source electrodes at the middle with the second metal layer as an etching mask; forming a passivation layer to cover the second metal layer, the a-Si layer, and the gate insulator layer; and defining a pattern of the passivation layer with a fourth mask, so as to remove the passivation layer for exposing the scan line pads and the data line pads.