Patent ID: 8604831

Claim:
An integrated circuit comprising: a functional circuit configured to operate in response to an operational clock signal having an operational clock frequency; clock distribution circuitry configured to distribute a distribution clock signal across said integrated circuit at a distribution clock frequency, said distribution clock frequency being less than said operational clock frequency; and a clock converter configured to convert said distribution clock signal distributed by said clock distribution circuitry into said operational clock signal for controlling operation of said functional circuit; wherein said clock distribution circuitry comprises: an upstream distribution portion for distributing said distribution clock signal across said integrated circuit at said distribution clock frequency; an intermediate clock gating circuit for receiving said distribution clock signal from said upstream distribution portion; and a downstream distribution portion for distributing said distribution clock signal from said intermediate clock gating circuit to at least said clock converter at said distribution clock frequency; said intermediate clock gating circuit is configured to control whether or not a clock transition of said distribution clock signal is propagated to said downstream distribution portion; said intermediate clock gating circuit comprises an intermediate clock converter configured to convert said distribution clock signal received from said upstream distribution portion into an intermediate operational clock signal having said operational clock frequency; and said intermediate clock gating circuit is configured to generate, in response to said intermediate operational clock signal and an enable signal, a gated distribution clock signal, and to output said gated distribution clock signal to said downstream distribution portion at said distribution clock frequency.