Patent ID: 7958390

Claim:
A memory device comprising: a memory array; a temporary storage area; and circuitry operative to: store, in the temporary storage area: (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N−1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array; write the first data in row N in the memory array; and in response to an error in writing the first data in row N in the memory array: write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device; and add addresses of rows N−1, N, and N+1 to a table stored in the memory device, wherein the table indicates which rows in the repair area should be used instead of rows N−1, N, and N+1; wherein the circuitry is operative to write the first data, the second data, if any, and the third data, if any, in respective rows in the repair area such that there are intervening blank rows between the respective rows.