Patent ID: 7940566

Claim:
A NAND flash memory device comprising: at least one memory block comprising a plurality of first NAND strings and a second NAND string, wherein the second NAND string is arranged between a pair of adjacent NAND strings among the plurality of first NAND strings; a common source line respectively electrically connected to the plurality of first NAND strings and the second NAND string; a plurality of first bit lines respectively electrically connected to the plurality of first NAND strings; a second bit line corresponding to the second NAND string and comprising a first bit line segment electrically connected to the common source line through a first contact, and a second bit line segment electrically connected to the second NAND string and electrically separated from the first bit line segment; a strapping line electrically connected to the common source line through the first bit line segment and the first contact; and, a first bias circuit biasing the second bit line segment with a power supply voltage during a program operation of memory cells in the plurality of first NAND strings to prevent memory cells in the second NAND string from being programmed.