Patent ID: 8829666

Claim:
A semiconductor package comprising: at least one die stack having first and second surfaces, the second surface of the die stack includes a plurality of conductive die pads; an integrated package substrate having first and second major surfaces, wherein the package substrate includes a first patterned substrate layer comprising first and second major surfaces, the first major surface of the package substrate includes a die attach region and a non-die attach region, the die attach and non-die attach regions are defined by the first major surface of the same first patterned substrate layer, wherein the die attach region is disposed in a different plane than the non-die attach region and the second surface of the die stack directly contacts the first major surface of the first patterned substrate layer in the die attach region, and substrate via contacts disposed therein, wherein a top surface of the via contacts is coplanar with the first major surface of the package substrate, the via contacts are directly coupled to and contact the die pads; and a cap having first and second surfaces to encapsulate the at least one die stack, wherein the second surface of the cap is disposed at a different plane than the second surface of the die stack, such that a cavity is enclosed by the second surface of the die stack and sidewalls of the cap in between the die attach and non-die attach regions, wherein the substrate via contacts are disposed within the cavity and extend from a plane below the second surface of the die stack to the second major surface of the first patterned substrate layer, and wherein the first surface of the cap is substantially coplanar with the first surface of the die stack which is opposite the second surface of the die stack such that the first surface of the die stack is exposed and not covered by the cap.