Patent ID: 6937067

Claim:
A signal balancing circuit for capacitively coupled signaling between transmitting and receiving devices both receiving a synchronizing clock signal, the signal balancing system comprising: a plurality of capacitively coupled signal lines on which data signals are transmitted from the transmitting device to the receiving device, the data signals representing streams of binary data having a data interval to which each binary digit corresponds; an encode circuit having an output at which a balancing signal is provided, the encode circuit coupled to each capacitively coupled signal line to monitor each data signal over a respective time interval for a change in logic states, the encode circuit inverting a data signal for a data interval in response to the data signal maintaining the same logic state throughout the time interval and further generating a balancing signal having a logic level and a timing relative to the time intervals of the respective data signals indicative of inversion of a particular data signal; and a decode circuit coupled to the encode circuit to receive the balancing signal and further coupled to the capacitively coupled signal lines to invert the data signals for the data interval according to the logic level and timing of the balancing signal.