Patent ID: 8339178

Claim:
A level shifter, outputting a first output signal and a second output signal respectively from a first output node and a second output node according to a first input signal and a second input signal, wherein the first input signal and the second input signal operate between a first voltage and a common voltage, the first output signal and the second output signal operate between a second voltage and the common voltage, and the first voltage is between the second voltage and the common voltage, the level shifter comprising: a first transistor, comprising a first drain, a first source and a first gate, and the first source being coupled to the second voltage, a second transistor, comprising a second drain, a second source and a second gate, and the second source being coupled to the second voltage, a third transistor, comprising a third drain, a third source and a third gate, the third source being coupled to the first gate, the third drain being coupled to the second output node, and the third gate being coupled to a first bias voltage, a fourth transistor, comprising a fourth drain, a fourth source and a fourth gate, the fourth source being coupled to the second gate, the fourth drain being coupled to the first output node, and the fourth gate being coupled to a second bias voltage, a fifth transistor, comprising a fifth drain, a fifth source and a fifth gate, the fifth drain being coupled to the first output node, the fifth source being coupled to the common voltage, and the fifth gate being coupled to the first input signal, and a sixth transistor, comprising a sixth drain, a sixth source and a sixth gate, the sixth drain being coupled to the second output node, the sixth source being coupled to the common voltage, and the sixth gate being coupled to the second input signal, wherein the first transistor and the second transistor are matched, the third transistor and the fourth transistor are matched, and the fifth transistor and the sixth transistor are matched, and when the first input signal equals the first voltage, the fifth transistor conducts the common voltage to the first output node, the fourth transistor conducts to turn on the second transistor so the second voltage is conducted to the second output node, and the third transistor conducts the second output node to the first gate so the first transistor is turned off.