Patent ID: 8615015

Claim:
An apparatus, comprising: a memory, the memory configured to store a plurality of route descriptors as a tree, each route descriptor from the plurality of route descriptors including a next hop destination associated with a route associated with that route descriptor, each route descriptor including a next hop indicator having a value associated with a quantity of routes represented by that route descriptor, each route descriptor from the plurality of route descriptors being a node from a plurality of nodes of the tree; a communications interface configured to be in communication with an access switch; and a processor operatively coupled to the memory and the communications interface, the processor configured to access a first route descriptor from the plurality of route descriptors, the first route descriptor having a first child route descriptor from the plurality of route descriptors, the first route descriptor having a second child route descriptor from the plurality of route descriptors, the processor configured to define, at a first time, a value of the next hop destination of the first route descriptor based on a value of the next hop destination of the first child route descriptor and a value of the next hop destination of the second child route descriptor, the processor configured to send, at a second time after the first time, the value of the next hop destination of the first route descriptor to the access switch via the communications interface in response to a next hop identifier request from the access switch.