Patent ID: 7068080

Claim:
A logic device for reducing power consumption, comprising: a clock gate having a clock enable terminal and a clock terminal; and a flip-flop coupled to the clock gate, the flip-flop having an input terminal, an output terminal, and a configuration terminal, the flip-flop configured to trigger on at least one of a rising edge and a falling edge of a clock signal provided to the clock terminal; wherein output from the clock gate is synchronous with the clock signal and follows the clock signal when a clock enable signal is in a first state and is logically low when the clock enable signal is in second state; and wherein the flip-flop comprises: a first latch coupled to the input terminal and the clock gate: a first multiplexer coupled to the first latch, the input terminal, and the configuration terminal: a second latch coupled to the first multiplexer and the clock gate; and a second multiplexer coupled to the first latch, the second latch, and the clock gate.