Patent ID: 8307260

Claim:
An error correction circuit coupled to a plurality of memory cells in a memory device, comprising: an error correcting code (“ECC”) generator coupled to the memory cells, the ECC generator operable to generate a respective correction code for each data bit string in a first direction and generate a respective correction code for each data bit in a second direction; and an ECC controller coupled to the memory cells and the ECC generator, the ECC controller operable to cause a data bit share by an identified data bit string in the first direction and the identified data bit string in the second direction to be changed from a respective existing value to a respective new value different than the respective existing value responsive to the identified bit string having more than one data bit in error,and wherein the ECC controller is further operable to determine whether or not at least one of the data bits is still in error after each of the shared data bits has been changed to the respective new value.