Patent ID: 7943967

Claim:
A semiconductor device, comprising: a substrate having a portion of the substrate formed to include a plurality of diffusion regions, wherein the plurality of diffusion regions respectively correspond to active areas of the portion of the substrate within which one or more processes are applied to modify one or more electrical characteristics of the active areas of the portion of the substrate, wherein the plurality of diffusion regions are separated from each other by one or more non-active regions of the portion of the substrate; a gate electrode level region formed above and over the portion of the substrate, the gate electrode level region including six linear-shaped conductive features defined to extend lengthwise in a first parallel direction, wherein each of the six linear-shaped conductive features is defined to include one or more gate electrode portions which extend over one or more of the plurality of diffusion regions, wherein each gate electrode portion and a corresponding diffusion region over which it extends together define a respective transistor device, wherein the six linear-shaped conductive features include, a first linear-shaped conductive feature defined to form both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, a second linear-shaped conductive feature defined to form a gate electrode of a second transistor of the first transistor type, a third linear-shaped conductive feature defined to form a gate electrode of a second transistor of the second transistor type, a fourth linear-shaped conductive feature defined to form a gate electrode of a third transistor of the first transistor type, a fifth linear-shaped conductive feature defined to form a gate electrode of a third transistor of the second transistor type, a sixth linear-shaped conductive feature defined to form a gate electrode of both a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type, wherein a region within the gate electrode level extending perpendicularly between the first linear-shaped conductive feature and the second linear-shaped conductive feature is devoid of a conductive structure that physically contacts a diffusion region formed below the gate electrode level, and wherein the first and second transistors of the first transistor type are formed to share a first active area of the portion of the substrate corresponding to at least one of the plurality of diffusion regions.