Patent ID: 8580620

Claim:
A method of manufacturing a semiconductor device comprising the steps of: (a) providing a wiring substrate having a top surface and an under surface opposite to the top surface, the wiring substrate having first lands and second lands on the top and under surfaces respectively, the first and second lands are each formed of a copper layer; (b) mounting a semiconductor chip on the top surface of the wiring substrate such that the semiconductor chip is connected to the first lands via first lead-free solder bumps formed between the wiring substrate and the semiconductor chip in a face-down manner at a first heat treatment higher than a melting point of the first lead-free solder bumps; and (c) after step (b), connecting second lead-free solder bumps to the second lands of the wiring substrate, wherein the first heat treatment in step (b) is performed under a condition such that a solder pre-coat layer is formed on each of the second lands of the wiring substrate, thereby preventing the second lands from oxidation due to the first heat treatment.