Patent ID: 7516453

Claim:
In a system in which a hardware target computer system, which has a target instruction set architecture (ISA), executes a target instruction sequence corresponding to a source instruction sequence of a source system, which has a source ISA and is running on the target computer system, a method for handling exceptions comprising the following steps: converting the source instruction sequence into the target instruction sequence by binary translation, each instruction in the source instruction sequence being converted into a corresponding translated target instruction sequence, which may consist of a single target instruction; determining beginning and ending addresses of each source instruction and each corresponding translated target instruction; generating a mapping between the beginning and ending addresses of each source instruction and its corresponding translated target instruction sequence; executing the translated target instruction sequence; at any point in the translated target instruction sequence, sensing the presence of an exception and determining whether each sensed exception is synchronous or asynchronous, a synchronous exception being defined as an exception resulting from attempted execution of a target instruction, in which synchronous exceptions are of either of two types, namely, transparent and non-transparent, a transparent exception being defined as an exception requiring processing action wholly within the target computer system, and a non-transparent exception being defined as an exception requiring processing that alters a visible state of the source system; and an asynchronous exception being defined as an exception resulting from an event unrelated to the execution of a target instruction; if the sensed exception is asynchronous, resuming to completion the execution of the target instruction sequence in binary translation from the point in the translated target instruction sequence at which the asynchronous exception was sensed before handling the asynchronous exception and thus delaying handling of each asynchronous sensed exception until, and no later than, completion of execution of the target instruction sequence corresponding to the current source instruction when the asynchronous exception is sensed; determining whether the sensed synchronous exception is transparent or non-transparent; handling each transparent synchronous exception externally from the source system, the visible state of the source system thereby remaining unaltered; and forwarding to the source system for processing each non-transparent synchronous exception.