Patent ID: 8421211

Claim:
A semiconductor package, comprising: a first semiconductor chip with a first conductive redistribution layer directly formed thereon; a second semiconductor chip with a smaller size than the first semiconductor chip, said second semiconductor chip mounted on the first semiconductor chip; a molding layer formed directly on the first semiconductor chip and around the second semiconductor chip; a plurality of conductive posts electrically connected to the first conductive redistribution layer, said conductive posts penetrating the molding layer; a warpage control barrier line directly formed on the first semiconductor chip, said warpage control barrier line being arranged at the outside of the second semiconductor chip, a second conductive redistribution layer formed on the molding layer and electrically connected to the conductive posts; and an outer connecting part electrically connected to the second conductive redistribution layer, wherein the warpage control barrier line and the molding layer have different Young's modulus with each other, wherein the warpage control barrier line takes the shape of a continuous ring.