Patent ID: 8304782

Claim:
An array substrate, comprising: a substrate comprising a pixel region, wherein the pixel region is defined by a gate line, a first segment of a data line, and a second segment of the data line, wherein the first segment of the data line terminal electrically connects to the second segment of the data line, and the second segment of the data line intersects the gate line; a thin film transistor comprising a gate electrode electrically connected to the gate line, a semiconductor channel layer, and source/drain electrodes; a first insulation layer disposed on the first segment of the data line and the gate electrode, wherein the first insulation layer is disposed between the second segment of the data line and the gate line in an overlapping area of the second segment of the data line and the gate line; a second insulation layer disposed on the second segment of the data line, the first insulation layer, the source/drain electrodes, and a part of the semiconductor channel layer, wherein the second insulation layer exposes a part of the drain electrode; a shielding electrode disposed on the first segment of the data line and/or the second segment of the data line, wherein the first and second insulation layers are disposed between a part of the shielding electrode and the first segment of the data line; a third insulation layer covering the shielding electrode and the second insulation layer, wherein the third insulation layer exposes a part of the drain electrode; and a pixel electrode covering a part of the third insulation layer in the pixel region and electrically connected to the drain electrode.