Patent ID: 8502594

Claim:
A circuit comprising: a switch comprising a first MOSFET and a second MOSFET, a gate terminal of the first MOSFET being connected to a gate terminal of the second MOSFET, a source terminal of the first MOSFET being connected to a source terminal of the second MOSFET, a drain terminal of the first MOSFET being an input terminal of the switch, and a drain terminal of the second MOSFET being an output terminal of the switch; a driver circuit controlled by a clock generator; and a bootstrap circuit coupled to the driver circuit, the bootstrap circuit comprising: a capacitor selectively connected via switchable connectors in the driver circuit to a charging voltage source for charging the capacitor to a bootstrap voltage during an off state of the switch, the switchable connectors in the driver circuit being controlled by the clock generator; a latching circuit coupled to the capacitor and the switch, wherein, during an on state of the switch, the latching circuit is in a latched conductive state connecting the capacitor across the gate terminals and source terminals of the first MOSFET and second MOSFET, wherein the latching circuit comprises a first PMOS transistor and a first NMOS transistor, a gate terminal of the first PMOS transistor being connected to a drain terminal of the first NMOS transistor, a gate terminal of the first NMOS transistor being connected to a drain terminal of the first PMOS transistor, and wherein the capacitor is coupled between a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor, wherein the switchable connectors in the drive circuit are substantially non-conductive during the on state of the switch, whereby the latching circuit operates independently from the drive circuit during the on state of the switch to maintain the switch in its on state.