Patent ID: 7865670

Claim:
An apparatus comprising: a translation lookaside buffer (TLB) in a processor, the TLB having a plurality of TLB entries, each TLB entry being associated with a virtual machine extension (VMX) tag word; a TLB virtual machine extensions (TLBVMX) control word and a mask control word; and a hardware-managed stack to hold one or more values for at least the mask control word; wherein each VMX tag word is to include one or more bits in combination with the TLBVMX control word to indicate the associated TLB entry is to be invalidated according to a processor mode when an invalidation operation is performed, the invalidation operation belonging to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.