Patent ID: 7015733

Claim:
A phase-locked loop based spread-spectrum clock generator comprising: a first input terminal receiving a first signal at an input frequency; a plurality of second input terminals receiving a plurality of modulation frequency control inputs; a third input terminal receiving a dither control signal; a plurality of fourth input terminals receiving a plurality of frequency deviation control inputs; an output terminal outputting a signal at an output frequency; an input divider circuit connected to the first input terminal to generate an output signal at the reference frequency, equal to the input frequency divided by a first integer M; a prescaler circuit connected to the output terminal for generating at an output node a frequency equal to the output frequency divided by a fixed second integer P; a second divider circuit connected to the output node of the prescaler circuit for generating an output signal at the output of the prescaler frequency divided by a variable third integer N; a phase detector having a first input node connected to an output node of the input divider circuit and a second input node connected to an output node of the second divider circuit, and generating an output signal which is a function of the difference between the phases of the first divider and second divider output signals; a charge pump connected to the phase detector; a loop filter connected to an output node of the charge pump; a voltage-controlled oscillator connected to an output node of the loop filter, which generates a signal at the output terminal; a modulation frequency generator circuit connected to the first input terminal, to the second input terminals and to the third input terminal, which generates a first modulation frequency; a modulation sequence generator circuit connected to an output node of the modulation frequency generator, which generates a main modulation bitstream sequence reflecting a modulation waveform with a given amplitude; a bitstream processor connected to an output node of the modulation sequence generator, which generates a plurality of bitstream signals with scaled-down amplitudes with respect to the main modulation bitstream sequence; a multiplexer circuit connected to output nodes of the bitstream processor, which selects one of these outputs to be replicated at an output node, under control of the frequency deviation control input terminals; means to connect the output of the multiplexer to an input of the second divider, in order to select the variable third integer N.