Patent ID: 7443943

Claim:
A shift register comprising a plurality of stages for sequentially outputting output pulses and supplying them to gates lines in a display region, each of the stages comprising: a first node controller disposed at one side of the non-display region, the first node controller controlling a signal state of a first node, wherein the first node controller comprises: a first switching device for supplying a charging voltage to the first node in response to an external start pulse or the output pulse from a previous stage; a second switching device for supplying the discharging voltage to the first node in response to the output pulse from the next stage; and a third switching device for electrically connecting the first node with an output terminal of the pull-up switching device in response to an external clock pulse; at least one pull-up switching device disposed at the one side of the display region, the pull-up switching device outputting an output pulse according to the signal state of the corresponding first node and supplying it to a corresponding gate line; a second node controller disposed at the other side of the display region, the second node controller controlling a signal state of a second node, wherein the second node controller comprises: a fourth switching device for supplying the charging voltage to the second node in response to the output pulse from the next stage; a fifth switching device for supplying the discharging voltage to the second node in response to the start pulse or the output pulse from the previous stage and a sixth switching device for supplying the discharging voltage to the second node in response to the output pulse from the corresponding stage; and a first pull-down switching device disposed at the other side of the display region, the first pull-down switching device outputting a discharging voltage according to the signal state of the second node and supplying it to the other side of the corresponding gate line.