Patent ID: 7514800

Claim:
A semiconductor device, comprising: a plurality of first bond pads arranged in a first line along a first edge of a semiconductor chip; a plurality of first conductive traces formed on a substrate; and each first bond pad is electrically connected to one of the first conductive traces with a respective first bond wire; wherein the first bond wires are divided into a first bond wire group and a second bond wire group and the first bond wire group consists of first bond wires having bonding points on respective first bond pads that are offset toward the first edge of the semiconductor chip as compared to bonding points on all respective first bond pads electrically connected to first bond wires in the second bond wire group, the first bond wires from the first bond wire group and the first bond wires from the second bond wire group are arranged in order along the first line such that at least two adjacent ones of the plurality of first bond pads are from the same bond wire group, and each first bond pad includes a probe mark in an area away from the bonding point on the first bond pad and an area of the bonding point on the first bond pad does not include a probe mark, the probe marks on first bond pads connected to the first bond wire group are offset away from the first edge of the semiconductor chip and the probe marks on first bond pads connected to the second bond wire group are offset toward the first edge of the semiconductor chip.