Patent ID: 8892971

Claim:
An output control circuit comprising: a first scan flip-flop that captures first data in a first mode and second data in a second mode in synchronization with a clock signal to output the data that is captured, the second data being supplied through a signal path different from a signal path of the first data; a second scan flip-flop that captures the data output from the first scan flip-flop in the second mode in synchronization with a clock signal to output the data that is captured; and a gating circuit that generates the data output from the first scan flip-flop in the first mode as output data, and generates output data having a flip rate of a logic value lower than a flip rate of a logic value of the data output from the first scan flip-flop based on the data output from each of the first scan flip-flop and the second scan flip-flop in the second mode.