Patent ID: 8773185

Claim:
A calibratable delay chain comprising: a delay chain comprising a plurality of delay stages and adjustment circuitry configured to vary a delay of each of said plurality of delay stages in response to an input value; and calibration circuitry configured to calibrate a delay of said delay chain, wherein said calibration circuitry comprises: calibration control circuitry for controlling said calibration and supplying said input value to said adjustment circuitry; output selection circuitry configured to select an output from a predetermined point along said delay chain; a bypass path for bypassing said delay chain; a digital comparator configured to compare an output from said delay chain and an output from said bypass path; an analogue comparator configured to compare an output from said delay chain and an output from said bypass path; wherein said calibration control circuitry is configured to control said output selection circuitry to output a signal from one point on said delay chain to said digital comparator and to change said input value to said adjustment circuitry in a first direction at a first rate until a change in an output value of said digital comparator value is detected; said calibration control circuitry is configured to respond to said detected change in output value of said digital comparator to control said output selection circuitry to output a signal from a further point on said delay chain to said analogue comparator and to change said input value in a second direction at a second rate starting from a value determined by said input value at which said digital comparator's output value changed value, said second rate being slower than said first rate, a change in value output from said analogue comparator indicating an input value that provides a calibrated delay.