Patent ID: 7470571

Claim:
A method of producing a thin film transistor array substrate which includes: an insulating substrate; a display pixel formed on the insulating substrate, the display pixel having a pixel electrode connected to a drain electrode of a thin film transistor; a gate wiring for scanning the thin film transistor; and a source wiring for giving a signal potential supplied to the pixel electrode, the gate wiring and the source wiring being formed perpendicular to each other with an insulating film interposed therebetween, the method comprising: forming a first thin metal multi-layer film, an upper layer of which includes aluminum, on the insulating substrate, and then spreading a photo-resist over the first thin metal film; forming the photo-resist on the first thin metal film to a thickness less in an area connected to a second thin metal film made of a transparent electrically-conductive film than in an area which is not connected to the second thin metal film; patterning the first thin metal film with the photo-resist; reducing a thickness of the photo-resist layer and removing the photo-resist in the area on the first thin metal film connected to the second thin metal film; removing the upper layer of the first thin metal film exposed by removing the photo-resist in the area on the first thin metal film connected to the second thin metal film to expose a lower layer of the first thin metal film; forming an interlayer insulating film on the first thin metal film and then patterning the interlayer insulating film such that the lower layer of the first thin metal film is exposed in the area on the first thin metal film connected to the second thin metal film; and patterning the second thin metal film thus formed such that the area on the first thin metal film connected to the second thin metal film is included whereby the lower layer of the first thin metal film and the second thin metal film are connected to each other.