Patent ID: 8539216

Claim:
A system-on-a-chip comprising: a processor; a first one-time-programmable memory; a second memory; a test interface configured to be enabled or disabled, wherein the test interface is in communication with the processor only while the test interface is enabled to permit debugging of the system-on-a-chip; and an input circuit configured to receive data transmitted from a third memory to the system-on-a-chip, wherein the processor is configured to, while booting up the system-on-a-chip, determine whether the first one-time-programmable memory has been previously programmed, wherein in response to the first one-time-programmable memory not having been previously programmed, enable the test interface to permit debugging the system-on-a-chip, and wherein based on the first one-time-programmable memory having been previously programmed, disable the test interface, and subsequent to enabling the test interface or disabling the test interface, load the data from the third memory into the second memory.