Patent ID: 7388416

Claim:
A latch circuit comprising: a data reading unit that reads both a first input data and a second input data, and outputs both a first output data and a second output data based on both the first input data and the second input data, wherein both the first input data and the second input data are differential signals, and both the first output data and the second output data are differential signals that have phases that are inverted; and a data holding unit that holds both the first output data and the second output data, wherein the latch circuit operates based on a clock signal that is supplied from an outside source, both the data reading unit and the data holding unit are voltage driven type, and the data reading unit includes: a first pair of PMOS and NMOS transistors whose gates are directly connected to a first input node to which the first input data is input, and whose drains are directly or indirectly connected to a first output node from which the second output data is output; a second pair of PMOS and NMOS transistors whose gates are directly connected to a second input node to which the second input data is input, and whose drains are directly or indirectly connected to a second output node from which the first data is output; a timing control transistor that, based on the clock signal, controls a timing of reading both the first input data and the second input data that has a phase that is inverted with respect to the first input data; a first inverter circuit that includes the first pair and reads the first input data based on the timing, inverts the first input data into a first inverter output data, and outputs the first inverter output data as the first output data; and a second inverter circuit that includes the second pair and reads the second input data based on the timing, inverts the second input data into a second inverter output data, and outputs the second inverter output data as the second output data, and the data holding unit includes: a third inverter circuit that reads the second inverter output data, inverts the second inverter output data into a third inverter output data, and outputs the third inverter output data; and a fourth inverter circuit that reads the first inverter output data, inverts the first inverter output data into a fourth inverter output data, and outputs the fourth inverter output data, and the fourth inverter circuit reads the third inverter output data while the third inverter circuit reads the fourth inverter output data.