Patent ID: 6985379

Claim:
A semiconductor memory device having a memory cell region in which a statistic memory cell is formed, comprising: a first inverter formed of a first driver transistor of a first conductive type and a first load transistor of a second conductive type; a second inverter formed of a second driver transistor of the first conductive type and a second load transistor of the second conductive type, an output terminal of said first inverter and an input terminal of said second inverter being electrically connected to each other, thereby forming a first storage node, and an output terminal of said second inverter and an input terminal of said first inverter being electrically connected to each other, thereby forming a second storage node; a first access transistor of the first conductive type having a source electrically connected to said first storage node, a gate electrically connected to a word line for writing, and a drain electrically connected to a bit line for writing; and a second access transistor of the first conductive type having a gate electrically connected to a word line for reading, and a drain electrically connected to a bit line for reading, said first access transistor being disposed on one side of a region in which said first and second load transistors are formed, and said second access transistor being disposed on the other side of the region in which said first and second load transistors are formed, and gates of all of the transistors disposed in said memory cell region extend in the same direction.