Patent ID: 7557602

Claim:
A pre-emphasis circuit comprising: a first buffer buffering first and second main input signals having phases opposite to each other, outputting first and second main output signals, and controlling slew rates of the first and second main output signals using at least one main control signal; a second buffer buffering first and second sub-input signals having phases opposite to each other, outputting first and second sub-output signals, and controlling slew rates of the first and second sub-output signals using at least one sub-control signal; and an output driver generating first and second output signals having opposite phases using at least two output control signals and the first and second main output signals of the first buffer and the first and second sub-output signals from the second buffer, wherein the first sub-input signal is delayed from the first main input signal by one bit and the second sub-input signal is delayed from the second main input signal by one bit, and wherein the first buffer comprises: a first main input signal processor processing the first main input signal to generate at least two first group gate signals in response to the at least one main control signal; a second main input signal processor processing the second main input signal to generate at least two second group gate signals in response to the at least one main control signal; a first input stage controlling current flowing through the first load resistor connected to a first terminal thereof in response to the first main input signal and the first group gate signals; a second input stage controlling current flowing through the second load resistor connected to a first terminal thereof in response to the second main input signal and the second group gate signals.