Patent ID: 7346750

Claim:
A memory interleave system comprising: M (M is 2 p where p is a natural number) memory banks each including a plurality of memories; N (a natural number) computing means for outputting memory requests as access requests to said M memory banks, each of said memory requests containing a first bank address which comprises an address of said memory bank and a first intra bank address which comprises an address of a memory in said memory bank; N address generating means respectively corresponding to said N computing means; and M memory control means respectively corresponding to said M memory banks, wherein said N address generating means receive a memory request from said corresponding computing means, and newly generates and outputs a second intra bank address and a second bank address by using said first intra bank address and said first bank address which are contained in said memory request, wherein said M memory control means perform memory bank access control on a basis of said second intra bank address output from said N address generating means, and each of said M memory control means performing such access control being selected on a basis of said second bank address output from said address generating means, wherein said N address generating means generate said second intra bank address and said second bank address in accordance with a bank interleave mode setting value, wherein said N address generating means generate said second intra bank address and said second bank address by rearranging said first intra bank address and said first bank address for at least 0 bit in accordance with said bank interleave mode setting value, and wherein when said bank interleave mode setting value indicates a ½ q bank interleave mode (q comprises an integer of not less than 0 and not more than p) and said first bank address and said first intra bank address respectively include x bits and y bits (x and y comprise integers of not less than q), said address generating means sets, as said second intra bank address, a bit string comprised of(y−q) bits of the first intra bank address excluding upper q bits and upper q bits of the first bank address, and also sets, as said second bank address, a bit string comprised of an upper q bits of said first intra bank address and (x−q) bits of said first bank address excluding said upper q bits.