Patent ID: 6966012

Claim:
A memory circuit, comprising: a memory core having an array of core cells, the core cells being defined by a plurality of rows and columns; a redundant column containing core cells, the redundant column juxtaposing the memory core and extending substantially parallel with the plurality of columns of the memory core; an X decode circuitry region for addressing rows of the memory core and the redundant column, the X decode circuitry region extending with and adjacent to the redundant column; Y decode circuitry for addressing columns within an IO bit of the memory core, the Y decode circuitry including pre-charge circuitry; a control circuit; input/output (IO) circuitry associated with each IO bit, the IO circuitry directly being configured to route an access request intended for a defective core cell to the redundant column, a select signal activating an enable buffer and multiplexer of the IO circuitry to read from or write to a core cell of the redundant column; and sense amplifier circuitry coupled to each IO bit and the redundant column.