Patent ID: 7424557

Claim:
A method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus architecture, comprising, interlocking the at least two FIFO buffers, wherein interlocking comprises defining a transaction correspondence between the buffers, the act of defining a transaction correspondence comprising: (a) defining a plurality of data structures in each of the at least two FIFO buffers; (b) assigning an identification to each of the data structures, the data structure identification in one FIFO corresponding to one or more data structure identifications in the other of the at least two FIFO buffers; and (c) ensuring that a data structure having an assigned identification in one FIFO buffer will have or has information that is transactionally-related to information that is contained or will be contained in a corresponding data structure in another of the at least two FIFO buffers.