Patent ID: 6973539

Claim:
A multiprocessor write-into-cache data processing system comprising: A) a memory; B) at least first and second shared caches; C) a system bus coupling said memory and said first and second shared caches; D) at least first, second, third and fourth processors having, respectively first, second, third and fourth private caches, each of said first, second, third and fourth processors incorporating respective first and second delay means; E) said first and second private caches being coupled to said first shared cache by a first internal bus, and said third and fourth private caches being coupled to said second shared cache by a second internal bus; F) a plurality of gatewords stored in said memory, each said gateword governing access to different common code/data sets, each common code/data set being shared by processes running in a plurality of said processors; G) first means for each given processor to read and test each of said gatewords by performing successive swap operations between said memory and said given processor's shared cache and between said given processor's shared cache and private cache; H) second means for a first given processor finding a first tested gateword stored in memory OPEN to write said first tested gateword CLOSEd in its private cache, and, thereafter, successive swap operations are carried out between: 1) the first given processor's private cache and the first given processor's shared cache; and 2) the first given processor's shared cache and memory to flush the first given processors shared cache of a block containing said first tested gateword and thereby write said first tested gateword CLOSEd in memory; I) third means by which said first given processor starts said first delay means in all processors to institute first delays to temporarily prevent any processor from reading and testing said first gateword; J) fourth means, when said first given processor completes use of the common code/data governed by said first tested gateword, writing said first gateword OPEN in its private cache, and, thereafter, successive swap operations are carried out between: 1) the first given processors private cache and the first given processor's shared cache; and 2) the first given processor's shared cache and memory to flush the first given processors shared cache of the block containing the first tested gateword and thereby write said first tested gateword OPEN in memory; K) fifth means for starting said second delay means in any processor which is seeking ownership of a gateword other than said first tested gateword; and L) sixth means for truncating said delay started by said third means in all said processors which are seeking ownership of a gateword other than said first tested gateword by subtracting the elapsed delay indicated in said second delay means from the elapsed delay indicated in said first delay means.