Patent ID: 7746134

Claim:
A digitally controlled delay-locked loop comprising: a phase detector; a counter that generates digital signals in response to an output signal of the phase detector, wherein the counter adjusts a binary value of the digital signals in one of first and second directions in response to the output signal of the phase detector; a delay chain generating a delay that varies in response to the digital signals; and a delay circuit that delays a feedback signal derived from the delay chain to generate a delayed feedback signal, wherein the delayed feedback signal is transmitted to an input of the phase detector, wherein the delay of the delay chain varies by a discrete time period in response to changes in logic states of the digital signals, and wherein the delay of the delay circuit is less than the discrete time period, and wherein the counter maintains logic states of the digital signals constant in response to an enable signal to maintain the delay of the delay chain constant in a lock mode of the digitally controlled delay-locked loop, and wherein the enable signal is generated in response to the output signal of the phase detector.