Patent ID: 8644062

Claim:
A multi-level memory device comprising: an insulating layer including an opening; a multi-level cell (MLC) formed in the opening; and a write circuit that is configured to store one of a plurality of data values in the MLC by applying a respective one of a plurality of write pulses to the MLC, wherein each of the plurality of write pulses has the same pulse height and a different pulse width, wherein the MLC is configured to have a resistance level that varies with the width of the write pulse that is applied thereto so that the write pulses having different widths may be used to store different data values in the MLC, wherein each of the plurality of write pulses includes a rising edge period, a write pulse width period and a falling edge period, and wherein the pulse width is the write pulse width period, which is a period of time during which the write pulse maintains the pulse height, wherein each of the plurality of write pulses has the same falling edge period, wherein the MLC includes a chalcogenide alloy phase change material which is deposited in the opening, wherein a ratio of a crystalline area to an amorphous area in the chalcogenide alloy phase change material increases as the pulse widths of the write pulses increase, and the crystalline area in the chalcogenide alloy phase change material includes a plurality of chalcogenide alloy sub-crystalline areas throughout the entire area of the chalcogenide alloy phase change material.