Patent ID: 7827337

Claim:
An application processor in a digital processing apparatus, said digital processing apparatus comprising a main processor, said application processor, a first memory and a second memory, said application processor performing a predetermined function in accordance with a control of said main processor, said first memory and said second memory being coupled to said application processor, said application processor comprising: a processing unit operatively coupled to said main processor, said first memory, and said second memory, said processing unit performing said predetermined function, and generating a route control signal to set a path to said first memory or said second memory; a route controller coupled to said first memory and second memory, said route controller setting said path for data communication with one of said first memory and second memory, said path being set through a shared memory interface for said first memory and said second memory in accordance with a control of said processing unit; a first memory controller, said first memory controller communicating information with said first memory through a first memory interface and said route controller; a second memory controller, said second memory controller communicating information with said second memory through a second memory interface and said route controller; and a bus controller, said bus controller performing bus control in accordance with said control of said processing unit, and activating said first memory controller or said second memory controller in accordance with said path set to said first memory or said second memory according to said route control signal, wherein said first memory is a removable memory and said second memory is an internal memory, and said first memory interface includes at least one pin for transmitting a clock (CLK) signal and said second memory interface includes at least one pin for transmitting a chip select (CS) signal, and when the number of pins for interfacing with said first memory is n (a natural number) and the number of pins for interfacing with said second memory is m (a natural number larger than n), said shared memory interface comprises k (a natural number) pins between 1 and n-1, said first memory interface comprises n-k pins, and said second memory interface comprises m-k pins.