Patent ID: 7809928

Claim:
An instruction decoder included within a graphics shader, the instruction decoder configured to generate event signals based on specially configured instructions, each of the specially configured instructions being inserted into the sequence of instructions running on the graphics shader and identifying one of a plurality of events caused by the execution of an instruction in the sequence in the graphics shader, and that does not affect a sequence of instructions running on the graphics shader, the instruction decoder comprising: an instruction parser configured to process a first one of the specially configured instructions and to generate a first event signal corresponding to the execution of an instruction in the graphics shader, wherein each one of the specially configured instructions is specified using an identifier of a non-operative (NOP) instruction, a first bit field indicating that one of the plurality of events will be triggered, and a second bit field identifying the one of the plurality of events; a first event multiplexer configured to receive the first event signal from the instruction parser, to select the first event signal from one or more event signals based on the second bit field and to transmit the first event signal to an event logic block for recording an event occurring in a functional unit of the graphics shader, wherein the first event multiplexer is configured by a software driver to select the first event signal from the one or more event signals based on the second bit field; and a performance register that is configured to perform the recording of the event, and wherein the graphics shader is configured to modify behavior of a program executed by the graphics shader based on contents of the performance register and modify a color comment of pixel data stored in the memory when contents of the performance register is greater than a threshold.