Patent ID: 8484589

Claim:
A method comprising: performing, by one or more computers each comprising at least a processor and a memory: receiving a hardware description language (HDL) representation of a circuit block of an integrated circuit (IC), wherein the circuit block comprises a plurality of cells disposed at different hierarchies; performing a pop phase until a selected cell is at a desired hierarchy, wherein performing the pop phase comprises: identifying a first list of cells that includes all cells within a current hierarchy that includes the selected cell; dissolving the current hierarchy; removing the selected cell from the first list of cells to obtain a new first list of cells; re-forming the previously dissolved current hierarchy with the new first list of cells, to pop the selected cell to a next higher level of hierarchy; and moving to the next higher level of hierarchy; once the selected cell is at the desired hierarchy, performing a push phase until the selected cell is at a destination hierarchy, wherein performing the push phase comprises: identifying a second list of cells within a next lower level of hierarchy; dissolving the next lower level of hierarchy; adding the selected cell to the second list of cells to obtain a new second list of cells; and re-forming the previously dissolved next lower level of hierarchy with the new second list of cells, to push the selected cell to the next lower level of hierarchy.