Patent ID: 7698508

Claim:
A method for cache management in a data processing system, wherein said data processing system includes a processor and a memory hierarchy, wherein said memory hierarchy includes at least an upper level cache having a lower access latency, at least a lower level cache having a higher access latency, and a write-back data structure, said method comprising: in response to a need to evict a victim cache line from a set of cache lines in said upper level cache, the upper level cache preferentially selecting the victim cache line from among the set of cache lines based upon said write-back data structure indicating said lower level cache holds a copy of the victim cache line; in response to selecting as said victim cache line a cache line among the set that said write-back data structure indicates as having a copy in the lower level cache, replacing said victim cache line in said upper level cache without writing data of the victim cache line to said lower level cache and without accessing a memory directory of said lower level cache; prior to selecting the victim cache line, determining whether or not information in said write-back data structure is to be utilized to select the victim cache line; and in response to determining said information is not to be utilized to select the victim cache line, the upper level cache selecting the victim cache line according to access chronology of the cache lines in the set.