Patent ID: 6855967

Claim:
A wiring structure of buffer cells in power line areas between macro cells in a semiconductor device; comprising: a) a substrate with a macro block area and a standard cell area; macro cells in said macro block area; said macro cells separated by power line areas; providing a driver located in said standard cell area; b) at least a buffer cell in said power lines area; c) a plurality of interconnect layers over said substrate; said interconnect layers interconnecting devices within said macro cells and said standard cells and providing sublevel power lines; d) a power level layer over said plurality of interconnect layers; said power level layer comprised of VDD and VSS lines running in parallel over said power line area between said macro cells; said power level layer comprised of a pin to connect to said buffer cell; said pin located in said power line area wherein said VDD and VSS lines have notch areas where said VDD and VSS lines do not contact said pin, wherein said notch area is less than five percent of said VDD or VSS line in width; e) a signal line over said power level layer and said macro block area; said signal line having contacts to said pin and are connected to said buffer cell; said signal line connected to said driver located in said standard cell area.