Patent ID: 8486829

Claim:
A method for making a semiconductor element having a conductive via, comprising the following steps: (a) providing a silicon chip comprising a silicon substrate and an active circuit layer, the silicon substrate having a first surface and a second surface, the active circuit layer being disposed on the second surface of the silicon substrate, and having at least one metal layer; (b) removing part of the silicon substrate and part of the active circuit layer from the first surface of the silicon substrate, to form at least one columnar groove and at least one opening, respectively, the columnar groove penetrating the silicon substrate, and the opening exposing part of the metal layer; (c) forming a conductive metal in the columnar groove and the opening, the conductive metal being electrically connected to the metal layer of the active circuit layer, and a surface of the conductive metal exposing to outside of the first surface of the silicon substrate; (d) removing part of the silicon substrate from the first surface of the silicon substrate, to form at least one annular groove, the annular groove penetrating the silicon substrate and surrounding the conductive metal; and (e) forming a first insulation layer in the annular groove, so that the conductive metal and the first insulation layer forming at least one conductive via.