Patent ID: 7139184

Claim:
A memory cell array comprising: memory cells, each of the memory cells comprising a storage element and an access transistor; bit lines running along a first direction; word lines running along a second direction substantially perpendicular to the first direction; and a semiconductor substrate, continuous active area lines and isolation trenches being formed in the semiconductor substrate, the isolation trenches being adjacent to the active area lines, and the isolation trenches being adapted to electrically isolate neighboring active area lines from each other, the access transistors being at least partially formed in the active area lines and electrically coupling corresponding storage elements to corresponding bit lines via bit line contacts, the transistors being addressed by the word lines; wherein the bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line; and wherein neighboring bit line contacts, each of which is connected to an active area line, are connected with neighboring bit lines.