Patent ID: 8293599

Claim:
A method of fabricating a semiconductor device having a dual gate, the method comprising: forming a gate insulating layer on a semiconductor substrate comprising a first region and a second region, on which devices having different threshold voltages are to be formed; selectively injecting a diffusion inhibiting material into the gate insulting layer in one of the first region and the second region; forming a diffusion layer on the gate insulating layer; directly diffusing a work function controlling material from the diffusion layer into the gate insulating layer using a heat treatment, wherein the gate insulating layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region; entirely exposing the gate insulating layer by removing the diffusion layer; forming a gate electrode layer on the exposed gate insulating layer; and respectively forming a first gate and a second gate having different work functions in the first region and the second region by etching the gate electrode layer and the gate insulating layer.