Patent ID: 8713502

Claim:
A computer-implemented method for determining timing constraint analyses of an integrated circuit (IC), said method comprising: defining, by a computer, a sequence of sample points for timing constraint analyses in an n×n matrix, each sample point corresponding to a timing arc of said IC that includes a data slew and a reference slew, which is analyzed by one of: simulation and interpolation; simulating, by said computer, corner sample points of said matrix, according to said sequence, by: substituting minimum and maximum timing constraints from files of said IC, for time values of said data slews; establishing a step size based on said minimum and maximum timing constraints for a starting bisection point of a binary search; and conducting said binary search from said starting bisection point and using a result from said binary search to simulate said timing constraint analyses for each of said corner sample points; and interpolating, by said computer, other sample points, according to said sequence, each of said other sample points having a starting bisection point that results from linear interpolation of said timing constraint analyses from adjoining sample points, which were simulated.