Patent ID: 7606013

Claim:
A low leakage ESD protection circuit comprising: a first power supply configured to operate at a first voltage; a second power supply configured to operate at a second voltage, said second voltage being less than said first voltage; one or more inverters, each of said one or more inverters having an input and an output; a clamping device positioned between said first and second power supplies, said clamping device joined with said output of at least one of said one or more inverters; and a timing element for triggering said one or more inverters, said timing element configured to not allow current flow from said first power supply to said second power supply through said timing element, said timing element including: a first transistor having a first terminal and a second terminal, said first terminal being in electrical communication with said first power supply; and a second transistor having a first gate, a third terminal, and a fourth terminal, said third terminal being in electrical communication with said second power supply, said fourth terminal being in electrical communication with said input of an initial one of said one or more inverters via a first node, said second gate being in electrical communication with said second terminal via a second node, said second node being decoupled from said second power supply.