Patent ID: 7088629

Claim:
A semiconductor memory device comprising: a memory cell including a floating body region assuming an electrical floating state, and storing data by storing charge in the floating body region or by discharging therefrom; memory cell arrays including a plurality of the memory cells arranged along a column and a row; a plurality of bit lines respectively provided in columns of the memory cell array and connected to the memory cells disposed along the respective columns; a plurality of word lines respectively provided in rows of said memory cell array and connected to the memory cells disposed along the respective rows; a column selection line to select a bit line to read/write data from/into the memory cells; and a sense amplifier connected to a first bit line and a second bit line in a memory cell array via transfer gates, the sense amplifier comprising a first sense node connected to the first bit line via a transfer gate, a second sense node connected to the second bit line via a transfer gate, a first cross couple including two switching elements of first conduction type connected in series between the first sense node and the second sense node, and a second cross couple including two switching elements of second conduction type connected in series between the first sense node and the second sense node, a first node between the two switching elements in the first cross couple and a second node between the two switching elements in the second cross couple being respectively connected to different power supplies via a plurality of routes, the sense amplifier selecting the routes on the basis of a potential on the column selection line.