Patent ID: 7200831

Claim:
A method of designing wiring of a semiconductor integrated circuit including as a wiring design base: at least two of basic wiring pattern layers constituting a multilayer structure, each basic wiring pattern layer having a plurality of wiring traces in a strip shape; a basic via array layer located between the two basic wiring pattern layers, having a plurality of vias relaying and connecting the wiring traces of the two basic wiring pattern layers; and another basic via array layer located at a side of one of the two basic wiring pattern layers, including a plurality of vias connecting predetermined ones of the wiring traces of the one of the two basic wiring pattern layers with circuit elements, the method comprising: preparing the basic wiring pattern layers so as to have the wiring traces extending in a predetermined direction and arranged with regularity to form a repetitive pattern in wiring regions of the basic wiring pattern layers; preparing the basic via array layer so as to have the vias arranged in an array form with regularity to form a repetitive pattern in a wiring region of the basic via array layer; forming processed wiring pattern layers having been subjected to design processing from the basic wiring pattern layers by selecting predetermined wiring traces, and cutting the selected wiring traces at some intermediate portions to form a plurality of wiring trace pieces in consideration of a need for wiring traces serving as signal wiring traces, and a need for wiring traces serving as dummy wiring traces; forming a processed via array layer having been subjected to design processing from the basic via array layer by eliminating unnecessary vias, with the vias serving as connections vias and dummy vias being left in consideration of a need for connection vias and dummy vias; and forming desired wiring lines by relaying and connecting the wiring traces and the wiring trace pieces of the two processed wiring pattern layers with remaining connection vias in the processed via array layer, and leaving the wiring traces, the wiring trace pieces, and the dummy vias not related to the wiring lines to form a dummy pattern.