Patent ID: 8026550

Claim:
An integrated circuit, comprising: N planar metal layers, where N is an integer greater than one; a first planar metal layer that includes M contact portions configured to communicate with respective ones of the N planar metal layers, where M is an integer greater than one, and wherein the first planar metal layer and the N planar metal layers are located in separate planes; a first drain region having a generally rectangular shape; first, second, third and fourth source regions that i) have a generally rectangular shape and ii) are arranged adjacent to sides of the first drain region; wherein the first drain region and the first, second, third and fourth source regions are configured to communicate with at least two of the N planar metal layers; a first gate region that is arranged between the first, second, third and fourth source regions and the first drain region; and first, second, third and fourth substrate contact regions that are arranged adjacent to corners of the first drain region.