Patent ID: 7082558

Claim:
A method of measuring a delay of a path of interest contained in an integrated circuit, said integrated circuit comprising a plurality of memory elements and a plurality of combinatorial blocks forming a plurality of paths, wherein said plurality of paths comprise said path of interest and wherein said path of interest has a longest delay in said plurality of paths, said path of interest being located between a first start memory element and a target memory element, said plurality of memory elements being connected in sequence, said method comprising: scanning-in a non-robust test pattem into said plurality of memory elements; shifting said non-robust test pattern, wherein said shifting of said non-robust test pattern causes a transition to occur in both of said first start memory element and a second start memory element, wherein said second start memory element is at one end of an off-path intersecting with said path of interest, wherein said second start memory element is also comprised in said plurality of memory elements; and measuring said delay of said path of interest by examining a signal received at said target memory element, said signal containing said transition propagated from both of said first start memory element and said second start memory element, wherein said signal is generated in response to said shifting.