Patent ID: 7627795

Claim:
A pipelined data processing system, comprising: functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry; at least one staging storage element associated with a pipeline stage of a pipeline of the pipelined data processing system, the at least one staging storage element coupled to receive test data directly from the plurality of test points; a multiple input shift register (MISR) coupled to receive test data from the at least one staging storage element and provide a MISR result, the MISR having a clock enable input for receiving an enabling clock that enables and disables the MISR, the enabling clock permitting execution results of at least one non-interrupt instruction in an execution stage of the pipeline to be clocked into the MISR while an interrupt signal is being fetched and at least a portion of non-interrupt instruction execution is discarded from the pipeline by being flushed and nulled out to a predetermined value.