Patent ID: 8918445

Claim:
A multiplier circuit comprising: a first source input receiving a plurality of N bits of a first instruction specified operand; a second source input receiving a plurality of N bits of a second instruction specified operand; a multiply cluster including a first multiplier having a first input receiving N/2 lower half bits of said first instruction specified operand and a second input receiving N/2 lower half bits of said second instruction specified operand (L×L), a first output generating a first Wallace tree output of a product of said first multiplier (L×La) and a second output generating a second Wallace tree output of said product of said first multiplier (L×Lb), a second multiplier having a first input receiving N/2 upper half bits of said first instruction specified operand and a second input receiving N/2 upper half bits of said second instruction specified operand (H×H), a first output generating a first Wallace tree output of a product of said second multiplier (H×Ha) and a second output generating a second Wallace tree output of said product of said second multiplier (H×Hb), a third multiplier having a first input receiving N/2 lower half bits of said first instruction specified operand and a second input receiving N/2 upper half bits of said second instruction specified operand (L×H), a first output generating a first Wallace tree output of a product of said third multiplier (L×Ha) and a second output generating a second Wallace tree output of said product of said third multiplier (L×Hb), a fourth multiplier having a first input receiving N/2 upper half bits of said first instruction specified operand and a second input receiving N/2 lower half bits of said second instruction specified operand (H×L), a first output generating a first Wallace tree output of a product of said fourth multiplier (H×La) and a second output generating a second Wallace tree output of said product of said fourth multiplier (H×Lb), first, second, third, fourth, fifth and sixth multiplexers, each having inputs connected to said first and second outputs of each of said first, second, third and fourth multipliers and an output, each selecting for output an instruction specified set of bits of said first and second outputs of each of said first, second, third and fourth multipliers, and a first 6:2 compressor having inputs connected to said outputs of said six multiplexers for adding said outputs of said six multiplexers, generating on a first output a first Wallace tree output of an instruction specified product and generating on a second output a second Wallace tree output of said instruction specified product; a second compressor having inputs connected to said first and second outputs of said first 6:2 compressor, having an output of a sum of said first Wallace tree output and said second Wallace tree output forming said desired product.