Patent ID: 7787585

Claim:
A shift register operating in an active period and a blanking period, comprising a plurality of substantially cascaded shift register units, each controlled by a first clock signal and a second clock signal for generating an output signal, wherein the output signal is periodically activated, and each of the shift register units comprises: a first switch device for providing the output signal through an output node; a first driving device for driving the first switch device according to a first input signal to activate the output signal in the active period; a second driving device, coupled to a voltage signal, for providing the voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal in the active period; and a second switch device, coupled to the voltage signal, for providing the voltage signal to the output node according to the second clock signal when the first switch device de-activates the output signal, wherein in the active period, the voltage signal is at a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other, and wherein in the blanking period, the voltage signal is at a high level, and each of the first and second clock signals is set as a direct-current signal.