Patent ID: 7318209

Claim:
A method of altering a duty cycle of a first clock signal in an integrated circuit having a plurality of switches, comprising: receiving, by at least a first portion of the switches, the first clock signal, wherein the first clock signal has a first pulse width; in response to the first clock signal transitioning from a first logical state to a second logical state at time t: gating a second portion of the switches to transition a second clock signal to the second logical state at substantially time t; at substantially time t, propagating a signal in the first logical state through a delay element, wherein the delay element has a propagation delay time t 1 ; in response to the propagation delay time t 1 being less than the first pulse width of the first clock signal, at substantially the end of time t+t 1 , gatng a third portion of the switches to transition the signal to the second logical state; and in response to the signal transitioning to the second logical state, at substantially the end of time t+t 1 , transitioning the second clock signal to the first logical state; and in response to the clock signal transitioning from the second logical state to the first logical state at time t 2 : gating a fourth portion of the switches such that the second clock signal is in the first logical state at substantially time t 2 ; at substantially time t 2 , propagating the signal in the second logical state through the delay element; and in response to the propagation delay time t 1 of the delay element being less than the first pulse width of the first clock signal, at substantially the end of time t 2 +t 1 , gating a fifth portion of the switches such that the second clock signal does not transition to the second logical state at substantially the end of time t 2 +t 1 .