Patent ID: 7417283

Claim:
A CMOS device comprising: a silicon substrate having a cell area and a peripheral circuit area, the silicon substrate having a device isolation layer between a P-well region and a N-well region in the peripheral circuit area; n+ polycide gate having at least a first metal silicide layer formed on the P-well region of the substrate; p+ polycide gate having at least a second metal silicide layer formed on the N-well region of the substrate, wherein the n+ polycide gate and the p+ polycide gate are separated from each other; an interlayer dielectric layer formed on a predetermined portion of the n+ polycide gate and a predetermined portion of the p+ polycide gate and on a portion of the substrate between the separated n+ and p+ polycide gates; and a bit-line having a first end and a second end formed on the interlayer dielectric layer, wherein the first end is connected to the n+ polycide gate and the second end is connected to the p+ polycide gate such that a bridge structure is formed over the interlayer dielectric layer, thereby simultaneously contacting the separated n+ polycide gate and the p+ polycide gate.