Patent ID: 7493446

Claim:
A processor chip for utilization within a data processing system having a memory hierarchy, said processor chip comprising: a processor core; a store queue having multiple entries, each entry including registers for storing address and data of store operations issued by the processor core and multiple byte-enable bits, one for each smallest storage granule of data that may be stored by a store operation, wherein each byte enable bit corresponds to one of the smallest storage granule among the multiple storage granules within the entry and each bye enable bit is set to a logical high value when the storage granule is updated by a store operation, wherein the byte enable bit retains a logical low value when no update occurs to the corresponding storage granule, wherein each of multiple byte enable bits corresponding to the multiple storage granules are set to the logical high value when all the storage granules within the entry have been updated; a store queue (STQ) controller that monitors and controls said store queue; arbitration logic associated with said STQ controller that selects an entry from among multiple eligible entries available for dispatch to be stored in a lower level cache; and a read claim (RC) mechanism that performs updates to cache lines within said lower level cache utilizing data from the entry selected for dispatch; and first logic for determining when all storage granules within a store queue entry have received data from said processor core before said entry is selected for dispatch, wherein said first logic comprises AND logic associated with each of said entries that receives as input a value of each of said multiple byte-enable bits and provides a single AND output that indicates when all of said multiple byte-enable bits for the entry are set, indicating a full entry; and second logic within an RC machine of said RC mechanism assigned to update a target cache line with data of said entry for completing said update of the target cache line without initiating a data tenure on the system bus, wherein said update is completed regardless of whether said cache line is present in said lower level cache or said cache line data is stale, wherein said second logic includes logic for: receiving at said RC mechanism an entry select identifying the entry for dispatch; receiving at said RC mechanism a signal indicating that the entry is full; assigning the cache line update operation to the RC machine of said RC mechanism; providing an indication to the RC machine that the entire cache line is being updated; and responsive to a receipt by said RC machine of the full signal indicating that the entry being dispatched is full, activating a cache update mechanism that enables the completion of the cache line update without requiring a copy of the cache line or current data within the cache line, wherein cache line updates from entries that are not full are completed with a current copy of the cache line within the cache and write permission to the cache line.