Patent ID: 8179181

Claim:
A clock tree in an integrated circuit, comprising: at least two function modules, wherein each of the at least two function modules comprises a sub clock tree, wherein the sub clock tree transmits a delayed clock signal to different elements in each of the at least two function modules respectively; a system control circuit, coupled to the at least two function modules, providing at least two power information to the at least two function modules respectively, wherein a power mode of each of the at least two function modules is determined according to the power information respectively; and at least two power-mode-aware (PMA) buffers, each of the at least two PMA buffers coupled to the sub clock tree in each of the at least two function modules and the system control circuit, for determining a delay time of a system clock signal according to the power information respectively, delaying the system clock signal, and outputting respectively the delayed system clock signal to the sub clock tree in each of the at least two function modules as the delayed clock signal.