Patent ID: 7475104

Claim:
A system for performing decimal floating point addition, the system comprising: input registers for inputting a first and second operand for an addition operation; a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand, wherein output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits and wherein the calculating is performed during a first clock cycle; an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle; a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing during the first clock cycle; an incrementer for adding one to each of the sums stored in the intermediate result register, the incrementing occurring during a second clock cycle; and a mechanism for selecting between each of the sums and the sums incremented by one, wherein input to the mechanism includes the carry chain, the output includes the final sum of the first operand and the second operand, and the selecting occurs during the second clock cycle.