Patent ID: 7119389

Claim:
A DRAM cell array region comprising: an isolation layer in a predetermined region of a semiconductor substrate to define an active region; a first and a second MOS transistor in the active region and serially connected to each other, the first MOS transistor having a first impurity region at one end of the active region to act as a source region of the first MOS transistor and the second MOS transistor having a second impurity region at another end of the active region to act as a source region of the second MOS transistor; and a first and a second storage nodes disposed on the substrate including the first and second MOS transistors, the first and second storage nodes being electrically connected to the first and second impurity regions respectively, and central axes of the first and second storage nodes passing through a first position and a second position that are spaced apart from central points of the first and second impurity regions, respectively, toward a single direction parallel to a length direction of the active region by predetermined distances, such that the central axes of the first and second storage nodes do not extend toward one another and do not extend away from one another, relative to the respective central points of the first and second impurity regions.