Patent ID: 8013392

Claim:
A semiconductor circuit comprising a substrate; a plurality of field effect transistors comprising pFETS and nFETS formed on the substrate, the plurality of field effect transistors including a first portion of field effect transistors and a second portion of field effect transistors; a first stress layer having a first thickness and being configured to impart a first determined stress to the first portion of the plurality of field effect transistors; and a second stress layer having a second thickness and being configured to impart a second determined stress to the second portion of the plurality of field effect transistors, wherein the first thickness is different than the second thickness, wherein the first determined stress is different than the second determined stress, wherein: the first portion of the plurality of field effect transistors have spacings between adjacent field effect transistors that fall within a first defined spacing range; and the second portion of the plurality of field effect transistors have spacings between adjacent field effect transistors that fall within a second defined spacing range, wherein the first defined spacing range is different than the second defined spacing range, and wherein at least one of: the first stress layer is applied over an entire surface containing the plurality of field effect transistors; the first stress layer imparts the first determined stress to a channel region of the first portion of the plurality of field effect transistors; and the first stress layer is formed on top of the first portion of the plurality of field effect transistors and the second stress layer is formed on top of the second portion of the plurality of field effect transistors.