Patent ID: 7742323

Claim:
A memory device, comprising: a first cladded conductor including a first core conductor and a first outer cladding in contact with and completely surrounding the first core conductor; a first electrode in contact with a portion of the first outer cladding and including a substantially planar surface; a second cladded conductor including a second core conductor and a second outer cladding in contact with and partially surrounding the second core conductor; a memory element operative to store data as a plurality of conductivity profiles and including a plurality of substantially planar thin-film layers, the thin-film layers including, a layer of a conductive metal oxide (CMO) including a selectively crystallized portion in contact with the substantially planar surface of the first electrode and having a polycrystalline structure and an amorphous portion having an amorphous structure, and a layer of a first electrically insulating material including a first tunnel barrier in contact with the selectively crystallized portion; and a non-ohmic device including, a second electrode in contact with the first tunnel barrier, a second tunnel barrier made from a second electrically insulating material and in contact with the second electrode, and a third electrode in contact with the second tunnel barrier and a portion of the second outer cladding, wherein the memory element and the non-ohmic device are electrically in series with the first and second cladded conductors.