Patent ID: 7079423

Claim:
A method for programming a selected bit in a memory cell of a non-volatile dual bit flash memory device comprising: pulsing said selected bit, and wherein said pulsing comprises: applying a first positive voltage to a first bit line associated with said selected bit; and applying a second positive voltage to a word line associated with said selected bit; performing a counter erase on a complementary bit, wherein said performing a counter erase further comprises: applying a third positive voltage to a second bit line associated with a complementary bit that shares said memory cell with said selected bit; applying a fourth positive voltage to a third bit line, adjacent to said second bit line and separated from said first bit line by said second bit line, said fourth positive voltage for preventing erasure of a non-selected bit in an adjacent memory cell, and said non-selected bit sharing said second bit line with said complementary bit; and erasing said complementary bit by applying a negative voltage to said word line; verifying that said selected bit is sufficiently programmed, wherein said verifying further comprises: applying fifth positive voltage to said second bit line; applying a sixth positive voltage to said word line; and repeating said programming until the read current of said verifying reaches a value less than a reference level value.