Patent ID: 7439768

Claim:
A dedicated logic cell having a configurable logic function (LL), comprising: a first look-up table having a plurality of inputs for receiving a set of inputs (I 0 ) and at least one output; a second look-up table having a plurality of inputs for receiving the set of inputs (I 1 ) and at least one output; a third look-up table having at least one input (I 2 ) and at least one output; a fourth-look-up table having at least one input (I 3 ) and at least one output; a 4-to-1 multiplexer having a first input coupled to the at least one output of the first look-up table, a second input coupled to the least one output of the second look-up table, a third input coupled to the least one output of the third look-up table, and a fourth input coupled to the at least one output of the fourth look-up table, a first select input pin (S 0 ) and a second select input (S 1 ); a first multiplexer having a select input, an input (I 5 ), a configuration pin, and an output coupled to 13 the first select input pin of the 4-to-1 multiplexer; and a second multiplexer having a select input, an input (I 6 ), a configuration pin, and an output coupled to the second select input pin of the 4-to-1 multiplexer; where in the configuration pin of the first multiplexer selects the select input or the input (I 5 ) and generates to the first select input pin of the 4-to-1 multiplexer, the configuration pin of the second multiplexer selecting the select input or the input (I 6 ) and generating to the second select input pin of the 4-to-1 multiplexer.