Patent ID: 8159055

Claim:
A semiconductor device comprising: (1) an element mounted portion on which a semiconductor element is internally arranged, (2) a group of back-inner terminals coupled with at least one of the electrode pads of said semiconductor device through bonding wires and arranged in an area array shape so as to be exposed inside of a bottom; (3) a group of back-outer terminals arranged outside the group of back-inner terminals; (4) a group of front-outer terminals located immediately above the back-outer terminals to be exposed from the front surface, which are electrically coupled with the back-outer terminals located immediately therebelow through conductor plates, respectively; and (5) a sealing resin which seals said semiconductor element and bonding wires and non-exposed portions of said back-inner terminals, back-outer terminals and front-outer terminals, wherein on at least the respective terminal faces of said back-inner terminals, said back-outer terminals and said front-outer terminals, a noble-metal plated layer is formed, wherein connection between said back-outer terminals and said conductor plates and connection between said conductor plates and said front-outer terminals are made by diffusion connection through said noble-metal plated layer.