Patent ID: 7897508

Claim:
A method for manufacturing integrated circuit devices including metal interconnect structures, the method comprising: providing a first dielectric material overlying a surface of a semiconductor substrate, the first dielectric material defining a trench; forming a conductor within the trench and over the first dielectric material, the first dielectric material including low K dielectric materials, the conductor having a surface region; subjecting the conductor to thermal energy at a first temperature for a first duration of time to anneal the conductor; removing the conductor outside of the trench by a first chemical mechanical polishing (CMP) step; subjecting the conductor inside the trench and a surface of the first dielectric material to thermal energy at a second temperature for a second duration of time to provoke migration of the conductor, the thermal energy causing one or more void formation, the second temperature being higher than the first temperature, the second duration of time being shorter than the first duration of time, the second temperature being at least 250° C., the second duration of time being less than 90 seconds; and then planarizing the conductor by performing a second CMP step on the surface region of the conductor, the second CMP step removing the void formation.