Patent ID: 7202520

Claim:
A multiple-state memory cell, comprising: a first electrode coupled to a first voltage line; a second electrode coupled to a second voltage line; a multiple layer data state stack in which multiple data states are stored, the data-state stack including: a first portion of a metal-doped chalcogenide material adjoining the first electrode and being located between the first and second electrodes, the first portion having a first thickness; a third electrode of a conductive material adjoining the first portion; and a second portion of a metal-doped chalcogenide material adjoining the third electrode, the second portion having a second thickness, a fourth electrode of a conductive material adjoining the second portion; and a third portion of a metal-doped chalcogenide material adjoining the fourth electrode, the third portion having a third thickness, wherein application of a programming voltage to the first electrode induces a resistance change within at least one of the first, second and third portions.