Patent ID: 6888203

Claim:
A power chip set for a switching mode power supply, comprising a high voltage chip, having a junction field effect transistor, a switching power MOS transistor, and a current sense transistor, and further comprising: a N + drift layer epitaxially grown on a N + substrate forming a plurality of P âˆ’ wells; a first P âˆ’ well having a first P âˆ’ base, a first N + region and a first P + region formed on said first well; a second P âˆ’ well having a second P âˆ’ base, a second N + region and a second P + region formed on said second well; a third P âˆ’ well having a third P âˆ’ base, a third N + region and a third P + region formed on said third well; a first planar gate is formed on the first and second N + regions or said first and second P âˆ’ wells, wherein said first planar gate is positioned above said N drift layer thus forming a first dielectric layer between the first planar gate and the N âˆ’ drift layer; a first channel which is controlled by the first planar gate and is comprised of a surface layer of the first and second P âˆ’ bases between the first and second N + regions below the first dielectric layer; wherein the switching power MOS transistor is comprised of the N âˆ’ substrate, the N âˆ’ drift layer, the first and second P âˆ’ wells, the first and second P âˆ’ bases, the first and second N + regions, the first and second P + regions, the first planar gate and the first dielectric layer; a surface portion of the N âˆ’ drift layer between the second and third P âˆ’ wells is formed with a second N + region, a first and second insulation layer formed on the N âˆ’ drift layer between the second N + region and the second and third P + regions; wherein the junction field effect transistor is comprised of the N + substrate, the N âˆ’ drift layer, the second and third P âˆ’ wells, the second and third P + regions, the second N + region, and a Zener diode, wherein the Zener diode is comprised of the N âˆ’ drift layer, the second N + region and the second and third P âˆ’ wells; a second planar gate is formed on the third P âˆ’ base, the third N + region and the N âˆ’ drift layer, thus forming a second dielectric layer between the second planar gate and the third P âˆ’ base; a second channel which is controlled by the second planar gate is comprised of a surface of the third P âˆ’ base below die second planar gate; wherein a current sense transistor is comprised of the N + substrate, the N âˆ’ drift layer, the third P + region, the third N + region, the third P âˆ’ well, the third P âˆ’ base, the second planar gate, and the second dielectric layer.