Patent ID: 8374820

Claim:
A test circuit for testing a network interface, the test circuit comprising: a connector connected to the network interface; two probes connected to a measuring device; a first load board; first to third switch chips, two output pins of the second switch chip connected to first and second input pins of the third switch chip, two output pins of the third switch chip connected to the probes, first to fourth switch pins of each of the first and second switch chips connected to the first load board; a bus switch chip, first to sixth output pins of the bus switch chip connected to the first load board; a high speed switch chip, first to seventh input pins of the high speed switch chip connected to pins of the connector, first and second output pins of the high speed switch chip connected to two input pins of the first switch chip; and a microcontroller, a first output pin of the microcontroller connected to a control pin of the high speed switch chip, two control pins of the first and second switch chips connected to a second output pin of the microcontroller, two control pins of the third switch chip connected to a third output pin of the microcontroller, first to third input pins of the bus switch chip connected to fourth to sixth output pins of the microcontroller; wherein the microcontroller and the high speed switch chip output control signals to selectively control the first and second switch chips and the bus switch chip to turn on, to connect different loads of the first load board to the test circuit, the microcontroller outputs a control signal to control the third switch chip to turn on by the second switch chip, to display a test result through the measuring device.