Patent ID: 7572721

Claim:
A method of fabricating a semiconductor device, comprising: forming a lower interlayer dielectric layer on a semiconductor substrate; forming first and second landing pads to penetrate the lower interlayer dielectric layer and contact the semiconductor substrate, the first and second landing pads being spaced apart from each other; forming an interconnection pattern to cover the second landing pad and a portion of the lower interlayer dielectric layer; forming an etch stop layer to cover a surface of the substrate having the interconnection patterns; forming an upper interlayer dielectric layer to fill a gap region adjacent to the interconnection pattern on the etch stop layer; patterning the upper interlayer dielectric layer to form a preliminary contact hole to expose a portion of the etch stop layer in the gap region; extending the preliminary contact hole; and removing the etch stop layer exposed by the extended preliminary contact hole to form a first contact hole exposing the first landing pad.