Patent ID: 8629026

Claim:
A method of fabricating a semiconductor device, comprising: forming an implant mask layer over a substrate, the implant mask layer having a plurality of mask components separated by a plurality of openings, wherein the openings are aligned with a plurality of first regions of the substrate, respectively, and the mask components are aligned with a plurality of second regions of the substrate, respectively: implanting first dopant type ions into the first regions through the openings; annealing the substrate to cause the implanted first dopant type ions to diffuse from the first regions into the second regions in a manner such that dopant concentration levels of the first regions are approximately equal to dopant concentration levels of the second regions after the annealing: after annealing the substrate to cause the implanted first dopant type ions to diffuse from the first regions into the second regions, forming a doped extension region in the substrate that extends into the first and second regions, the doped extension region being formed of a second dopant type and the first and second regions being formed of the first dopant type that is opposite the second dopant type; and forming a source/drain region of the semiconductor device in the substrate over the doped extension region such that a portion of the substrate is interposed between the source/drain region and the first and second regions, wherein the source/drain region is formed of the first dopant type and the portion of the substrate is formed of the second dopant type, wherein the portion of the substrate is different than the doped extension region and is between a top surface of the substrate and the doped extension region.