Patent ID: 7732288

Claim:
A method for fabricating a semiconductor structure, said method comprising: providing a semiconductor layer and a gate stack on the semiconductor layer, wherein the semiconductor layer comprises (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions; removing the first and second semiconductor regions; and doping regions directly beneath the removed first and second semiconductor regions so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region; wherein said removing the first and second semiconductor regions comprises: doping the first and second semiconductor regions of the semiconductor layer with first dopants; and etching away the first and second semiconductor regions but leaving essentially intact the gate stack and regions of the semiconductor layer which are not doped with the first dopants, wherein said doping the first and second semiconductor regions with the first dopants is performed such that each region of the first and second semiconductor regions of the semiconductor layer has a thickness in a first direction perpendicular to a top surface of the channel region that increases discontinuously when moving in a second direction away from the gate stack, and wherein the second direction is parallel to the top surface of the channel region.