Patent ID: 7042266

Claim:
A delay circuit for delaying a logic signal having two logic levels consisting of a low level and a high level, comprising: an inverter chain containing not less than four inverters; a p-channel metal-oxide-semiconductor transistor and an n-channel metal-oxide-semiconductor transistor, known as MOS transistors, to comprise each of the at least four inverters, wherein a gate threshold voltage of each gate of said p-MOS and n-MOS transistors is shifted in mutually opposing directions; low threshold voltage n-MOS transistors of each of a first and a third inverter connected to ground by a high threshold voltage n-MOS transistor; and low threshold voltage p-MOS transistors of each of a second and a fourth inverter connected to a power source line by a high threshold voltage p-MOS transistor; wherein, when an input logic signal is fixed at a low level during a standby state, said high threshold voltage n-MOS transistor is set to an off-state in response to a chip select signal controlling said standby state, and said high threshold voltage p-MOS transistor is set to an off-state in response to said chip select signal that is negated.