Patent ID: 8541311

Claim:
A method for fabricating an integrated circuit, comprising: depositing a dielectric layer over a semiconductor device; forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, wherein forming the plurality of trimmed hardmask structures comprises: depositing a trimmable hardmask layer over the dielectric layer including depositing polycrystalline silicon over the dielectric layer; patterning the trimmable hardmask layer to form a plurality of intermediate hardmask structures; and trimming the plurality of intermediate hardmask structures using a trimming process that selectively removes polycrystalline silicon over the dielectric layer to produce a plurality of trimmed hardmask structures over the dielectric layer; embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, wherein embedding the plurality of trimmed hardmask structures in the surrounding hardmask layer comprises depositing an organic planarizing layer over the plurality of trimmed hardmask structures; removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer; and etching the dielectric layer through the plurality of openings to form a plurality of etch features in the dielectric layer.