Patent ID: 8372755

Claim:
A method for manufacturing an integrated circuit device, the method comprising: forming gate material layers over a semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of dual films stacked together, each dual film having a first material film having a high resistance to an oxygen plasma process and a second material film having a high resistance to an etching process, each material film have a thickness less than about 10 angstrom; patterning the gate material layers utilizing the multi-layer hard mask layer; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein the multi-layer hard mask layer has a thickness less than about 450 angstrom; thereafter performing, to the semiconductor substrate, various processes including etching and oxygen plasma treatment; and thereafter performing an epitaxy growth to the semiconductor substrate while the multi-layer hard mask layer has a thickness greater than about 200 angstrom, wherein performing the epitaxy growth process to the semiconductor substrate forms an epitaxial source region and an epitaxial drain region, the gate structure interposing the epitaxial source region and the epitaxial drain region.