Patent ID: 7986045

Claim:
A semiconductor device comprising: a first wafer ( 1 WA) and a second wafer ( 1 WB) that are bonded together at a bonding surface ( 30 a ); a plurality of first electrical signal connection parts ( 9 ), extending from within the first wafer ( 1 WA), across the bonding surface ( 30 a ) between the first wafer ( 1 WA) and the second wafer ( 1 WB), and into the second wafer ( 1 WB); a plurality of second electrical signal connection parts ( 26 ), provided on a bonding surface ( 30 b ) within the second wafer ( 1 WB), and forming a plurality of inter-wafer connection parts ( 30 c ) at a central portion thereof that electrically connect to each of the first electrical signal connection parts ( 9 ); wherein: each of the first electrical signal connection parts ( 9 ) is enclosed by a penetrating isolation part ( 5 ) which electrically insulate the inter-wafer connection parts ( 30 c ) from each other, each of the penetrating isolation parts ( 5 ) having walls arranged in a rectangular shape and which extend from the bonding surface ( 30 b ) within the second wafer ( 1 WB), across the bonding surface ( 30 a ) between the first wafer ( 1 WA) and the second wafer ( 1 WB), and into the first wafer ( 1 WA); and a junction face shape (A 3 , A 4 ) of each of the second electrical signal connection parts ( 26 ) is larger than a shape (A 2 ) of a positioning margin face that is formed by an outer shape (A 2 ) when a minimum junction shape (A 1 ), which has an area that is half of a junction area of the first electrical signal connection part ( 9 ), is enclosed by a same width dimension (M 1 ) as a positioning margin dimension between (M 1 ) the first wafer ( 1 WA) and the second wafer ( 1 WB).