Patent ID: 6975309

Claim:
A display driver which drives a display section based on display data read from a built-in random access memory (RAM) in a given read cycle, comprising: a first-in-first-out (FIFO) memory circuit for sequentially storing compressed data which is obtained by compressing display data and is inputted to the FIIFO memory circuit on a cycle longer than the read cycle, and for outputting the compressed data according to the order of storage; a decompression circuit which decompresses the compressed data outputted from the FIFO memory circuit on a cycle substantially equivalent to the read cycle; the RAM which stores the display data of at least one frame, the display data having been outputted from the decompression circuit on the read cycle, wherein the same display data is repeatedly and sequentially read from the RAM during at least two continuous frames; and a display driver circuit which drives the display section based on the display data stored in the RAM, wherein the decompression circuit outputs the display data to a target circuit irrespective of a buffering state of the display data in the target circuit.