Patent ID: 7023064

Claim:
An integrated circuit formed on a substrate, comprising: an NFET device having a first gate structure including a first gate dielectric on the substrate; and a first metal nitride layer overlying the first gate dielectric and in contact therewith, said first metal nitride layer being characterized as MN x , where M is one of W, Re, Zr, and Hf, and x is less than about 0.7; and a PFET device having a second gate structure including a second gate dielectric on the substrate; and a second metal nitride layer overlying the second gate dielectric and in contact therewith, said second metal nitride layer being characterized as MN x , where M is one of W, Re, Zn and Hf, and x is in the range of about 0.7 to about 1.5, wherein the second gate structure further includes a layer of polysilicon overlying the second metal nitride layer, and said polysilicon layer is effective to render the second gate structure substantially stable with respect to temperature at temperatures up to about 1000° C.