Patent ID: 8304885

Claim:
A semiconductor device comprising: an IC chip body including a first circuit section to which noisy signal lines that are likely to emit noise are connected, a second circuit section to which noise-susceptible signal lines that are susceptible to noise are connected, and a multiplicity of IC-side pads arranged in a rectangular configuration on one side of said IC chip body along the periphery thereof; and a rewiring layer including an insulating substrate serving as an insulating layer, a multiplicity of bumps that individually penetrate through a multiplicity of through holes in said insulating substrate from one side to the other side thereof and that, on said one side of said insulating substrate, face and are connected to said IC-side pads respectively, a multiplicity of external electrodes arranged in a grid configuration and surrounded by said bumps, and a multiplicity of lead wires that, on said other side of said insulating substrate, connect said multiplicity of bumps to said multiplicity of external electrodes respectively, wherein said noisy signal lines are respectively connected to, among said multiplicity of IC-side pads, a first group of IC-side pads, and said noise-susceptible signal lines are respectively connected to, among said multiplicity of IC-side pads, a second group of IC-side pads, said first group of IC-side pads are respectively connected to, among said multiplicity of external electrodes, a first group of external electrodes, and said second group of IC-side pads are respectively connected to, among said multiplicity of external electrodes, a second group of external electrodes, and said first group of IC-side pads are separated and spaced apart from said second group of IC-side pads, and said first group of external electrodes are separated and spaced apart from said second group of said external electrodes.