Patent ID: 7301811

Claim:
A nonvolatile memory cell comprising: an inverter, the inverter comprising: a first transistor coupled to an input of the inverter; a second transistor coupled in series to the first transistor; a floating gate at the input of the inverter, the floating gate formed in a first polysilicon layer and coupled to gates of the first and second transistors, and a tunnel window formed in a tunnel oxide area over a channel region of the second transistor, wherein the tunnel oxide area is covered by at least a portion of the floating gate; an access gate coupled to the inverter for controlling access to the nonvolatile memory cell; wherein the access gate includes a third transistor coupled in series to the second transistor; and a control gate for controlling charge on the floating gate, wherein the control gate is formed in a second polysilicon layer, and wherein the second polysilicon layer is above the first polysilicon layer.