Patent ID: 7350054

Claim:
An arrayed processor comprising: a plurality of processing elements arranged in a matrix, each of said processing elements having: an instruction memory configured to store instruction codes, an instruction decoder, an mb (m-bit) arithmetic logic unit and an nb (n-bit) arithmetic logic unit, where “m” represents a natural number equal to or greater than 2 and “n” represents a natural number smaller than “m”; a plurality of switch elements interconnecting said plurality of processing elements; a state transition controller configured to generate instruction pointers for said processing elements in response to object codes supplied to the state transition controller from an external circuit and to supply the generated instruction pointers to said respective processing elements, said generated instruction pointers designating instruction codes stored in each said instruction memory of said plurality of processing elements; and a data distributor configured to divide a series of processing data received from an external circuit into mb data and nb data, said mb data and nb data being input selectively to certain ones of said plurality of processing elements through mb and nb buses having connections controlled by said plurality of switch elements; wherein said instruction decoder of each said plurality of processing elements is configured to decode instruction codes designated by said instruction pointers in order to control the processing operation of said mb and nb arithmetic logic; and wherein said mb arithmetic logic unit processes in parallel mb data from said series of processing data, and said nb arithmetic logic unit processes nb data from said series of processing data according to said object codes.