Patent ID: 7296203

Claim:
A test apparatus for testing a device-under-test, comprising: a master channel provided in correspondence to one of output pins of said device-under-test to sample an output signal of said corresponding output pin; and a slave channel provided in correspondence to a different output pin from that of said master channel to sample an output signal of said corresponding output pin; wherein said master channel has; a frequency divider for generating a frequency-divided clock by dividing a source synchronous clock outputted from said device-under-test so that the frequency-divided clock has a period of the source synchronous clock multiplied by a predetermined ratio; a sampling section for sampling said corresponding output signal based on said frequency-divided clock; and a distributing section for distributing said frequency-divided clock to said slave channel; and said slave channel has a sampling section for sampling said corresponding output signal based on said frequency-divided clock received from said master channel.