Patent ID: 6894540

Claim:
A glitch removal circuit, comprising: a delay circuit that receives an input signal and generates first and second delayed input signals, wherein the delay circuit includes first and second inverters connected in series, the first inverter receiving the input signal and the second inverter generating the first delayed input signal and a third inverter having an input connected to the output of the second inverter, the third inverter generating the second delayed input signal; a glitch blocking circuit, coupled to the delay circuit, for removing both positive and negative glitches from the input signal, the glitch blocking circuit comprising: a first PMOS transistor receiving the input signal; a first NMOS transistor receiving the input signal; a second PMOS transistor receiving the first delayed input signal; and a second NMOS transistor receiving the first delayed input signal; and a latch circuit, having an input coupled to an output of the glitch blocking circuit, for providing a generally glitch free signal.