Patent ID: 8127184

Claim:
A system comprising: a processor comprising: a cache memory; a Built-In Self Test (BIST) circuit configured to test the cache memory; a non-volatile storage device comprising an E-fuse array to store one or more indicators, wherein each indicator identifies a corresponding memory address of a failed location of the cache memory that has been detected by the BIST circuit, wherein an accessible size of the cache memory is reduced by excluding access to each memory address of the cache memory identified by a corresponding indicator stored in the E-fuse array, and wherein the cache memory is identified as unusable when a count of the indicators stored in the non-volatile storage device exceeds a threshold; a comparison circuit coupled to the non-volatile storage device, wherein the comparison circuit is configured to perform a comparison of a memory access request with the one or more indicators in the E-fuse array; and a processing unit to: execute a portion of an instruction in parallel with the comparison, wherein the instruction includes the memory access request; and delay committing results of the instruction until the comparison is performed.