Patent ID: 7653845

Claim:
An integrated circuit chip comprising: on-chip memory; and test circuitry configured to perform operational testing of said on-chip memory, wherein said test circuitry comprises a controller configured to perform a selection out of a plurality of test algorithms to perform said operational testing, wherein said plurality of test algorithms include a fault detection test algorithm to perform operational testing of said on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault, wherein said plurality of test algorithms further include a fault location test algorithm to perform operational testing of said on-chip memory in order to detect and locate a memory fault; wherein said plurality of test algorithms comprise at least one dual-port RAM (Random Access Memory) test algorithm configured to assert all combinations of “toggle to 0”, “toggle to 1”, “read 0” and “read 1” in concurrent accesses to both ports, wherein said at least one dual-port RAM test algorithm includes an algorithm for RAM devices having two read-ports, said algorithm being configured to concurrently read from same addresses from both read-ports.