Patent ID: 6944836

Claim:
A method of testing a mixed-fabric programmable logic device (PLD), the PLD including a one-time programmable logic portion, a re-programmable logic portion, a first multiple input signature register (MISR) circuit coupled to receive output data from the re-programmable logic portion, and a programmable clock manager circuit, the method comprising: programming the re-programmable logic portion of the PLD to implement a test circuit; programming the clock manager circuit to receive a first clock signal at a first clock frequency, to provide a second clock signal at a second clock frequency, and to apply the second clock signal to the re-programmable logic portion and to the first MISR circuit; applying a test pattern to the PLD wherein the test pattern is applied at the first clock frequency and the re-programmable logic and the first MISR circuit function at the second clock frequency; and receiving signature data from the first MISR circuit at the first clock frequency, the signature data being derived from output data from the re-programmable logic portion.