Patent ID: 7804705

Claim:
A semiconductor device comprising: a circuit block, which has an m (m is an integer of not smaller than two) sets of first through m-th transistor columns where two or more transistors are connected in series and in which the first through m-th transistor columns have an identical or a varied number of transistors, one terminal of the first through m-th transistor columns is connected to a first output node, and the other terminal of the first through m-th transistor columns is connected to a second output node, wherein the circuit block comprises an intermediate node interconnection transistor for interconnecting at least two intermediate nodes of different transistor columns among the intermediate nodes of the first through m-th transistor columns, and a control signal for substantially simultaneously making all the transistors of the first through m-th transistor columns and the intermediate node interconnection transistor on-state or off-state is inputted to a control input terminal of the transistors of the first through m-th transistor columns and a control input terminal of the intermediate node interconnection transistor.