Patent ID: 8324110

Claim:
A method of forming a field effect transistor, said method comprising: providing a semiconductor layer, having a first top surface; forming a gate stack on said first top surface, said gate stack having a second top surface and opposing sidewalls; depositing a spacer material layer such that said spacer material layer comprises: a first horizontal portion that covers and is immediately adjacent to said first top surface of said semiconductor layer adjacent to said gate stack; a second horizontal portion that covers and is immediately adjacent to said second top surface of said gate stack; and vertical portions that cover and are immediately adjacent to said opposing sidewalls of said gate stack; anisotropically etching said first horizontal portion, said second horizontal portion and said vertical portions of said spacer material layer and further stopping said anisotropically etching prior to exposing said first top surface of said semiconductor layer and said second top surface of said gate stack such that, after said anisotropically etching, said first horizontal portion and said second horizontal portion are relatively thin as compared to said vertical portions; after said anisotropically etching, isotropically etching said first horizontal portion, said second horizontal portion and said vertical portions of said spacer material layer and further stopping said isotropically etching upon complete removal of said first horizontal portion and said second horizontal portion and prior to complete removal of said vertical portions such that said vertical portions form gate sidewall spacers; growing an epitaxial silicon layer on at least one of exposed portions of said first top surface; and before said growing, performing at least one of the following: performing an ex-situ pre-cleaning process after said isotropically etching; and performing an in-situ pre-cleaning process during said isotropically etching.