Patent ID: 8466066

Claim:
A method for forming a micro-pattern in a semiconductor device, comprising: forming a hard mask layer and a sacrificial layer over an etch target layer; forming a plurality of openings having a hole shape in the sacrificial layer; forming spacers over inner sidewalls of the openings to form first hole patterns inside the openings; etching the sacrificial layer outside of the sidewalls of the openings using the spacers in a manner that the sacrificial layer in a first area remains partially and the sacrificial layer in a second area is removed to form second hole patterns in the second area, wherein a space between adjacent ones of the spacers in the first area is smaller than a space between adjacent ones of the spacers in the second area; and etching the hard mask layer using the remaining sacrificial layer and the spacers including the first and second hole patterns, wherein the etching of the sacrificial layer is performed by using an etch rate difference that occurs due to differences in distances between adjacent ones of the spacers, wherein a first etch rate for etching the sacrificial layer in the second area is greater than a second etch rate for etching the sacrificial layer in the first area when the sacrificial layer is exposed for etching in both the first and second areas.