Patent ID: 8259858

Claim:
A receiver comprising: a mixer configured to down convert an analog signal from a higher frequency to a lower frequency; an analog processing block containing gain and filter stages configured to operate on the down converted analog signal; an analog-to-digital converter (ADC) configured to digitize the signal from the analog processing block; a digital processing and formatting (DPF) block configured to process and format the digitized signal, the DPF block comprising: a DC Offset Correction (DCOC) block configured to provide DC offset correction of residual DC distortion artifacts, a carrier detect (CD) state machine, a DCOC sequence manager responsive to the CD state machine and configured to control digital training sequences, and a sequence trigger responsive to the CD state machine; and a digital signal processor (DSP) configured to demodulate and arithmetically process samples from the DPF block; and a host controller configured to receive signals from the DSP and adjust parameters to an earlier stage of the receiver, processing by the DSP and host controller configured to be suspended and restarted by the sequence trigger depending on whether or not an on-channel signal is detected as having been received by the receiver.