Patent ID: 6965520

Claim:
A delay system for generating control signals in a ferroelectric memory device, comprising: a plurality of series connected delay elements comprising a first delay element, a last delay element, and one or more intermediate delay elements, the delay elements individually comprising: a signal input, a signal output, and a delay circuit that receives an input signal from the signal input and provides an output signal to the signal output delayed in time after the input signal; wherein the signal inputs of the intermediate delay elements and the last delay element are coupled with the signal output of the immediately preceding delay element, and the signal input of the first delay element is coupled with a system input, wherein at least one of the delay elements is a trimmable delay element comprising at least one trim input and a variable delay circuit that receives an input signal from the signal input of the trimmable delay element and provides an output signal to the signal output of the trimmable delay element a variable delay time after the input signal to the trimmable delay element, the variable delay time being set according to the at least one trim input; and a trim select circuit comprising at least one trim output coupled with the at least one trim input of the trimmable delay element, the trim select circuit providing at least one trim signal to the at least one trim input to control the variable delay time.