Patent ID: 7124388

Claim:
A method for establishing an m-th order even-length-order (ELO) reduction circuit model and its time-domain state space model of an even RC interconnect or transmission line for simulation, performance analysis or circuit design including the steps of (a) assigning an original order n to the even RC interconnect or transmission line with its even distributed resistance R and even distributed capacitance C for its n resistors and n capacitors respectively; (b) setting a reduced order m where m<n and a factor r with r=n/m; (c) forming the even RC interconnect or transmission line as an m-th reduced order circuit model having m sections in series from a source input terminal down to a final sink terminal with a source input terminal and m nodes, where m−1 nodes are conjunction nodes between the neighbor sections, and one end node is the final sink terminal, each section (say i, i=1, . . . , m) has an even distributed resistor with a resistance rR between two neighbor nodes and an even distributed capacitor with a capacitance rC between its downward node (say i) and ground; (d) building an m×m system matrix A, where its m−1 super-diagonal line entries and m−1 sub-diagonal line entries are the same as 1 r 2 ⁢ RC , its diagonal line has m−1 entries as - 2 r 2 ⁢ RC and one corner entry as - 1 r 2 ⁢ RC , and all other entries are zero; (e) building an m×1 input matrix B with only one non-zero entry as 1 r 2 ⁢ RC ; (f) building an 1×m output matrix C with only one non-zero value 1; (g) building a zero direct output matrix (scalar) D; (h) forming the m-th order time-domain state space model {A,B,C,D} by said four matrices A, B, C and D; whereby a system equation {dot over (x)}(t)=Ax(t)+Bu(t) and an output equation y(t)=Cx(t)+Du(t) determine the reduction model behavior, where x(t) denotes a state variable vector consisting of m node voltage variables, u(t) denotes the source voltage, and y(t) denotes the final sink terminal node voltage, thus the even interconnect or transmission line has its m-th ELO reduction circuit model and its time-domain state space model with a closed form, the method has a minimal computation complexity O(1), making a basis for simulation, performance analysis, model reduction, optimization or circuit design.