Patent ID: 7045882

Claim:
A semiconductor package comprising: a semiconductor chip defining opposed first and second surfaces and including a plurality of input/output pads disposed on the first surface thereof; a plurality of leads, each of the leads defining first and second surfaces and including: a pad portion; and at least one connecting bar portion integrally connected to and extending from the pad portion; at least some of the leads each having a bump land formed on the second surface upon the pad portion thereof and at least some of the leads each having a bump land formed on the second surface upon the connecting bar portion thereof; each of the bump lands being positioned underneath the second surface of the semiconductor chip, the number of the bump lands formed upon the connecting bar portions exceeding the number of the bump lands formed upon the pad portions; a plurality of conductive bumps electrically connecting the input/output pads to respective ones of the bump lands; and an encapsulant portion covering the semiconductor chip, the conductive bumps, and the second surfaces of the leads such that at least portions of the first surfaces of the leads are exposed in the encapsulant portion.