Patent ID: 7032080

Claim:
A system for sharing memory data of a plurality of stations in which packets are transferred between the plurality of stations connected to a communication line ( 33 ) characterized: in that each station is a memory-type station device ( 31 ) which comprises a memory ( 38 ), a user interface ( 32 ) for enabling said memory to be accessed from the exterior of said station, a transmission state machine ( 36 ) for transmitting a packet, a reception state machine ( 35 ) for receiving a packet, a cyclic internal clock ( 39 ) for tracking specific time instants assigned to each station and for tracking time instants when a packet is transmitted from a station to said communication line, an allowable time-error determination circuit ( 34 ) and an arbitration circuit ( 37 ) for arbitrating accesses from said transmission and reception state machines ( 36 , 35 ) and from said user interface ( 32 ); in that specific station address values 00 , 01 , . . . , 0 N are set to said stations, respectively; in that a sum of a time required to transmit a packet onto said communication line ( 33 ) and a time required for said packet to propagate on said communication line ( 33 ) is selected to be a unit of time between time instants indicated by said internal clock ( 39 ); in that each time instant (T 00 , T 01 , T 02 , . . . , T 0N ) is assigned to a respective one of said station address values; in that said internal clocks ( 39 ) in said stations of said system all indicate the same time, instant and each advances from the time instant T 00 to a maximum time instant T M cyclically; in that, when said internal clock ( 39 ) indicates a time instant which corresponds to the station address value of a given station, data in that memory address location of said memory which corresponds to the station address value of said given station is read through said arbitration circuit ( 37 ) and embedded in a packet which is then transmitted over said communication line ( 33 ); in that, when a packet is received successfully, its transmission source is determined from the received packet, whereupon said data in the received packet is written through said arbitration circuit ( 37 ) into that memory address location which corresponds to the station address value of said transmission source; and in that said allowable time-error determination circuit ( 34 ) corrects the time instant of said internal clock based on the difference between: a) a correct time instant of said internal clock; b) a time instant which is the sum of a time instant of the station specified by the station address included in the packet actually transmitted by the other station, and time required for said transmission.