Patent ID: 7442621

Claim:
A semiconductor fabrication process, comprising: patterning a photoresist layer over a semiconductor substrate to expose an isolation region of the substrate, wherein the substrate is a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer overlying a substrate bulk and an active semiconductor active layer overlying the BOX layer; forming a trench in the isolation region; forming a first dielectric in the trench to partially fill the trench wherein the first dielectric is a flowable dielectric; depositing a capping dielectric overlying the first dielectric to create a trench isolation structure; forming a material adjacent a first sidewall of the trench to create stress in the substrate adjacent the first sidewall, wherein the trench isolation structure prevents the stress adjacent the first sidewall from causing stress adjacent a second sidewall of the trench; and prior to patterning the photoresist layer, forming a hard mask layer overlying the substrate, wherein the hard mask comprises silicon nitride.