Patent ID: 8031827

Claim:
A shift register, comprising a plurality of stages, {S n }, n=1, 2, . . . , N, N being a positive integer, wherein each stage S n comprises: (a) a pull-up circuit having an input for receiving a corresponding clock signal Cn, an output for responsively outputting an output signal, O n , and an input node, Q n , between the input and the output; (b) a pull-up control circuit electrically coupled to the input node Q n of the pull-up circuit and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is identical to the first input signal and is provided to the input node Q n of the pull-up circuit to turn on the pull-up circuit; (c) a first pull-down circuit electrically coupled to the input node Q n and the output of the pull-up circuit and configured to receive a pull-down signal K n ; (d) a second pull-down circuit electrically coupled to the input node Q n and the output of the pull-up circuit, and configured to receive a second input signal; (e) a third pull-down circuit electrically coupled to the input node Q n and the output of the pull-up circuit and configured to receive a third input signal; and (f) a first pull-down control circuit configured to receive a fourth input signal and responsively generate the pull-down signal K n that is provided to the first pull-down circuit of the stage S n and the second pull-down circuit of one of the stage S n−1 and the stage S n+1 , respectively.