Patent ID: 7915943

Claim:
A mixer circuit that, upon the receipt of a single-ended first signal input to a first input terminal and a second signal pair input differentially to two second input terminals, multiplies the first signal and the second signal pair and then outputs differentially from two output terminals, comprising: an N-channel first MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a P-channel second MOSFET where their first terminals are connected to each other and their second terminals are connected to each other; an N-channel third MOSFET and a P-channel fourth MOSFET where their first terminals are connected to each other and their second terminals are connected to each other; a first capacitor provided between a gate of the first MOSFET and one of the second input terminals; a second capacitor provided between a gate of the second MOSFET and the other one of the second input terminals; a third capacitor provided between a gate of the third MOSFET and the other one of the second input terminals; a fourth capacitor provided between a gate of the fourth MOSFET and said one of the second input terminals; a first impedance element, whose one end is connected to the gate of the first MOSFET, that receives a first voltage at the other end; a second impedance element, whose one end is connected to the gate of the second MOSFET, that receives a second voltage at the other end; a third impedance element, whose one end is connected to the gate of the third MOSFET, that receives a first voltage at the other end; a fourth impedance element, whose one end is connected to the gate of the fourth MOSFET, that receives a second voltage at the other end; a fifth capacitor provided between the first terminals of the first, second, third, and fourth MOSFETs and the first input terminal; a fifth impedance element, whose one end is connected to the second terminals of the first and second MOSFETs, that receives a third voltage at the other end; and a sixth impedance element, whose one end is connected to the second terminals of the third and fourth MOSFETs, that receives a third voltage at the other end, wherein the second terminals of the first and second MOSFETs are connected to one of the output terminals and the second terminals of the third and fourth MOSFETs are connected to the other one of the output terminals.