Patent ID: 7601579

Claim:
A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the following steps: (A) forming gate parts, channel regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate; (B) forming a first insulation film having a tensile stress on a whole surface and forming a second insulation film on said first insulation film; (C) selectively removing said second insulation film and said first insulation film present on an upper side of the region of said N channel type field effect transistor constituting said logic part; (D) forming a third insulation film having a compressive stress on the whole surface; and (E) selectively removing said third insulation film present on the upper side of the region of said P channel type field effect transistor constituting said logic part, wherein between any two of said steps (B) to (D), ion implantation for relaxation of the compressive stress is applied to said first insulation film present on the region of said N channel type field effect transistor constituting said memory array part.