Patent ID: 8232148

Claim:
A method of forming a semiconductor device comprising: forming a first sacrificial stack and a second sacrificial stack on a semiconductor substrate, the first sacrificial stack and the second sacrificial stack each including a gate dielectric layer, wherein the gate dielectric layer comprises a high-k dielectric layer that is deposited in direct contact with the semiconductor substrate, and a metal nitride gate dielectric layer that is deposited directly on an upper surface of the high-k dielectric layer, wherein the first sacrificial stack is present in a first device region of the semiconductor substrate between an n-type source region and an n-type drain region, and the second sacrificial stack is present in a second device region of the semiconductor substrate between a p-type source region and a p-type drain region; forming an interlevel dielectric having an upper surface that is coplanar with an upper surface of the first sacrificial stack and the second sacrificial stack; removing an portion of the first sacrificial stack and the second sacrificial stack to expose the gate dielectric layer; forming a p-type work function metal layer on the gate dielectric layer, wherein the forming of the p-type work function metal layer comprises depositing an etch stop metal nitride layer on the metal nitride gate dielectric layer in the first device region and the second device region; depositing the p-type work function metal layer on the etch stop metal nitride layer in the first device region and the second device region, and forming a thermal dielectric on the p-type work function metal layer in the first device region and the second device region; forming a via to each of the n-type source region, the n-type drain region, the p-type source region and the p-type drain region; removing the p-type work function metal layer from the first device region, wherein the p-type work function metal layer remains in the second device region; forming a metal layer comprising titanium and aluminum on the gate dielectric layer in the first device region, the n-type source region, the n-type drain region, the p-type work function metal layer in the second device region, the p-type source region and the p-type drain region; and forming a metal fill comprising aluminum on the metal layer comprising titanium and aluminum.