Patent ID: 7804731

Claim:
A semiconductor memory device comprising: a plurality of memory cells including floating bodies in electrically floating state and storing therein logic data according to the number of carriers accumulated in the floating bodies; a plurality of bit lines connected to the memory cells; a plurality of word lines connected to the memory cells; a plurality of sense amplifiers connected to the bit lines, and one of the sense amplifiers reading data stored in one of the memory cells selected by one of the bit lines and one of the word lines or writing data to the one of the memory cells selected by the one of the bit lines and the one of the word lines; a refresh controller instructing a refresh operation for restoring deteriorated storage states of the memory cells; a refresh interval timer setting a refresh interval between one refresh operation and a next refresh operation to a first interval in a data read mode or a data write mode, and setting the refresh interval to a second interval longer than the first interval in a data retention mode, the data read mode being a mode in which the data stored in the selected memory cell is read to an outside of the device, the data write mode being a mode in which data from the outside is written to the selected memory cell; and an operation detection timer outputting a mode signal for deciding the refresh interval to the refresh interval timer, wherein the operation detection timer sets a logic of the mode signal to a first logic for setting the refresh interval to the first interval when an operation signal indicating the data read mode or the data write mode is active, and sets the logic of the mode signal to a second logic opposite to the first logic for setting the refresh interval to the second interval when the operation signal is inactive for a predetermined period.