Patent ID: 7145922

Claim:
An apparatus comprising: (1) a first integrated circuit for transmitting a first series of r-bit words and a second series of r-bit words; (2) a second integrated circuit for receiving a third series of r-bit words and a fourth series of r-bit words; (3) a third integrated circuit comprising: (a) a first serializer for serializing said first series of r-bit words to generate a first series of s-bit words, (b) a first deserializer for deserializing a second series of s-bit words to generate a fifth series of r-bit words, and (c) a first multiplexor for selecting said third series of r-bit words from said first series of r-bit words and said fifth series of r-bit words; and (4) a fourth integrated circuit comprising: (a) a second serializer for serializing said second series of r-bit words to generate a third series of s-bit words, and (b) a second descrializer for deserializing a fourth series of s-bit words to generate a sixth series of r-bit words, and (c) a second multiplexor for selecting said fourth series of r-bit words from said second series of r-bit words and said sixth series of r-bit words; wherein r and s are both positive integers and r>s.