Patent ID: 7057922

Claim:
A nonvolatile semiconductor memory device comprising: an array of nonvolatile memory cells arranged in both rows and columns; and a combination of word lines and bit lines arranged to extend in the row and column directions respectively so that they can select one of or a group of the memory cells for operation, wherein the memory cell has a variable resistance element, in which data is stored through a change in electric resistance, connected at one end to a source of a selection transistor, the selection transistor is connected at a drain to the bit line extending commonly along the column direction and at a gate to the word line extending commonly along the row direction while the variable resistance element is connected at the other end to a source line in the memory cell array, a write operation on the memory cell can be electrically executed by a predetermined voltage applied to the selected word line to turn the selection transistor conductive and a predetermined writing voltage or current applied between the selected bit line and the selected source line, and the reset operation on the memory cell can be electrically executed on the sector-by-sector basis, each sector including the plurality of memory cells connected to the common source line, by a predetermined voltage applied to the selected word line to turn the selection transistor conductive and a predetermined resetting voltage or current applied between the selected bit line and the selected source line.