Patent ID: 7052999

Claim:
A method for fabricating a semiconductor device, the method comprising: (a) forming a plurality of conductive patterns arranged with a predetermined spacing distance on a substrate; (b) forming a planarized inter-layer insulation layer on an entire surface of the resulting structure from the step (a); (c) etching the inter-layer insulation layer through the use of a wet etching process or a dry etching process to thereby expose a whole upper portion of the conductive patterns; (d) forming an etch stop layer on an entire surface of a resulting structure from the step (c); (e) etching the etch stop layer and the inter-layer insulation layer until a surface of a partial portion of the substrate disposed within the predetermined spacing distance is exposed to thereby form a self-aligned contact hole; and (f) forming a self-aligned contact structure by filling the self-aligned contact hole with a conductive material.