Patent ID: 6865101

Claim:
A memory system comprising: a non-volatile memory having a plurality of circuit blocks operated by inputting a first signal; another memory having a plurality of circuit blocks operated by inputting a second signal; a data latch circuit retaining at least one of output timings and cycles of the first signal and at least one of output timings and cycles of the second signal, wherein said at least one of output timings and cycles of the first signal is diffrent from said at least one of output timings and cycles of the second signal and at least one of output timings and cycles of the first and second signals are adjusted by a first and second variable delay circuit, respectively; and a timing generating circuit outputting the first signal to the non-volatile memory and outputting the second signal to the other memory according to at least one of the output timings and the cycles of the first signal and the second signal which are retained in the data latch circuit.