Patent ID: 7111217

Claim:
A method for flexibly nesting JTAG TAP controllers for IP cores in a FPGA-based system-on-chip (SoC), the method comprising: selecting an IP core JTAG TAP controller to be coupled in series with a host JTAG TAP controller; selecting at least one available bit from a selectable bit register of said host JTAG TAP controller, said selectable bit register having a plurality of available bits; and extending an apparent length of an instruction register of said host JTAG TAP controller by using said at least one available bit from said selectable bit register, wherein the apparent length of said instruction register of said host JTAG TAP controller comprises a combination of the length of said instruction register of said host JTAG TAP controller, the length of an instruction register of said selected IP core JTAG TAP controller, and optionally, the length of the selectable bit register.