Patent ID: 7532499

Claim:
A semiconductor integrated circuit device comprising: a plurality of memory cells each of which includes a cell transistor having a gate terminal connected to a word line and a source terminal and a drain terminal, a ferroelectric capacitor having a first terminal and a second terminal connected to the drain terminal of the cell transistor, a first cell terminal connected to one of the source terminal of the cell transistor and the first terminal of the ferroelectric capacitor, and a second cell terminal connected to other one of the source terminal of the cell transistor and the first terminal of the ferroelectric capacitor; and a plurality of memory cell block each of which includes a block selecting transistor having a source terminal connected to a bit line and a drain terminal connected to local bit line, and a reset transistor having a source terminal connected to a plate line and a drain terminal connected to the local bit line, wherein each of the plurality of memory cells has the first cell terminal connected to the local bit line, and the second cell terminal connected to the plate line.