Patent ID: 7426087

Claim:
An information recording apparatus comprising: a plurality of interface signals fed from an external host; a write control circuit for controlling write operation against a recording medium according to the plurality of interface signals; and a write canceling circuit for monitoring a plurality of predetermined signals among the plurality of interface signals as input signals to permit or inhibit write operation against the recording medium according to a result of the monitoring, wherein, when the write canceling circuit recognizes at least predetermined input signals among the input signals to be active simultaneously, the write canceling circuit inhibits write operation against the recording medium and thereafter, when the write canceling circuit recognizes all of the input signals to be inactive simultaneously, the write canceling circuit permits write operation against the recording medium, wherein the predetermined input signals are a write gate signal used to permit or inhibit write operation against the recording medium and a step pulse signal used to move stepwise a head serving as writing means against the recording medium, and wherein the write canceling circuit comprises: a first AND circuit that outputs a signal represent an AND of, among the input signals, a plurality of signals that are likely to be connected to different power supply line; a differentiating circuit for differentiating an output signal of the first AND circuit; a first delay circuit for giving a predetermined delay to the write gate signal; a second delay circuit for giving a predetermined delay to an output signal of the first delay circuit; a third delay circuit for giving a predetermined delay to the step pulse signal; a fourth delay circuit for giving a predetermined delay to an output signal of the third delay circuit; a second AND circuit that output a signal representing an AND of an inverted signal of the output signal of the first delay circuit and an output signal of the second delay circuit; a third AND circuit that outputs a signal representing an AND of an inverted signal of the output signal of the third delay circuit and an output signal of the fourth delay circuit; a fourth AND circuit that outputs a signal representing an AND of output signals of the second and third AND circuits; an RS flip-flop circuit that receives at a reset terminal thereof an output signal of the fourth AND circuit and that receives at a reset terminal thereof an output signal differentiating circuit; a timing adjustment circuit for performing predetermined timing adjustment on the write gate signal; and an OR circuit that outputs a signal representing an OR of an output signal of the RS flip-flop circuit and an output signal of the timing adjustment circuit, wherein write operation against the recording medium is permitted or inhibited according to an output signal of the OR circuit.