Patent ID: 7680142

Claim:
A communications chip comprising: a plurality of ports, each port providing an interface for attachment to an external communications facility to exchange data traffic therewith; a switching matrix for routing data traffic on the chip between said plurality of ports; a plurality of logic analyzers, each logic analyzer being associated with a corresponding one of said plurality of ports, wherein each logic analyzer monitors data traffic passing through its corresponding port and triggers when one or more predetermined conditions relating to the monitored data traffic occurs; a control interface, wherein the control interface configures the predetermined conditions and specifies selected fields of header data from packets of the monitored data traffic to be stored when a predetermined condition occurs; a multiplexer for each logic analyzer, wherein the multiplexer extracts the selected fields of header data from the packets of the monitored data traffic; and memory in each logic analyzer, wherein each logic analyzer stores in the memory the selected fields of header data extracted from the packets of the monitored data traffic when the logic analyzer is triggered by the predetermined conditions, wherein each logic analyzer stores in the memory the selected field of header data without storing in the memory other header data.