Patent ID: 8405154

Claim:
An integrated circuit, comprising: a symmetric MOS transistor formed at said surface of said integrated circuit, said symmetric MOS transistor further comprising: a first MOS gate, said first MOS gate having a first longitudinal axis; a first source area, said first source area being located adjacent to said first MOS gate; a first drain area, said first drain area being located adjacent to said first MOS gate opposite from said first source area; a first source side implanted region in said first source area, wherein said first source side implanted region has a first source side lateral overlap with said first MOS gate; and a first drain side implanted region in said first drain area, wherein said first drain side implanted region has a first drain side lateral overlap with said first MOS gate, such that said first drain side lateral overlap is substantially equal to said first source side lateral overlap; and an asymmetric MOS transistor formed at said surface of said integrated circuit, said asymmetric MOS transistor further comprising: a second MOS gate, said second MOS gate having a second longitudinal axis perpendicular to said first longitudinal axis; a second source area, said second source area being located adjacent to said second MOS gate; a second drain area, said second drain area being located adjacent to said second MOS gate opposite from said second source area; a second source side implanted region in said second source area, wherein said second source side implanted region has a second source side lateral overlap with said second MOS gate; and a second drain side implanted region in said second drain area, wherein said second drain side implanted region has a second drain side lateral overlap with said second MOS gate, such that said second drain side lateral overlap is different from said second source side lateral overlap.