Patent ID: 7888196

Claim:
A method of fabricating an integrated circuit, comprising: forming a first layer of dielectric material of a first thickness over a first type MOS transistor region of a semiconductor substrate; forming a second layer of dielectric material of a second thickness less than the first thickness over a second type MOS transistor region of the semiconductor substrate and over the first type MOS transistor region; forming a patterned hard mask over the first and second layers of dielectric material over the first type MOS transistor region and over the second layer of dielectric material over the second type MOS transistor region; selectively etching the first and second layers of dielectric material through the patterned hard mask layer to form an isolation trench in the semiconductor substrate to isolate the first and second type MOS transistor regions; filling the isolation trench with trench isolation material; removing the hard mask; forming a patterned gate electrode over the first and second layers of dielectric material over the first type MOS transistor region and over an adjacent corner part of the isolation trench filled with trench isolation material; and after forming the patterned gate electrode, selectively etching a portion of at least one of the first or second layers of dielectric material not covered by the patterned gate electrode, the patterned gate electrode protecting the adjacent corner part of the filled isolation trench from the etching.