Patent ID: 8081502

Claim:
Circuitry comprising: a memory cell comprising: an address transistor with a body terminal; and first and second cross-coupled inverters, each inverter having an n-channel metal-oxide-semiconductor transistor, a p-channel metal-oxide-semiconductor transistor, and an input, wherein the address transistor is coupled to the input of the first inverter, wherein each of the n-channel metal-oxide-semiconductor transistors has a respective body terminal and wherein each of the p-channel metal-oxide semiconductor transistors has a respective body terminal; and body bias control circuitry that is operable to supply a dynamic time-varying body bias voltage to the body terminal of the address transistor, wherein the body bias control circuitry is configured to supply body bias voltages to the body terminals of the n-channel metal-oxide-semiconductor transistors, wherein the body bias control circuitry is configured to supply body bias voltages to the body terminals of the p-channel metal-oxide-semiconductor transistors, and wherein the body bias control circuitry is configured to supply a reverse bias to the body bias terminal of the n-channel metal-oxide-semiconductor transistor of the second inverter during write operations into the memory cell.