Patent ID: 8473658

Claim:
A system comprising: a memory; a first bridge unit for processor access with the memory coupled with an input-output bus and the memory, the first bridge unit comprising a first arbitration unit, the first arbitration unit coupled with the input-output bus, a memory free notification unit (“MFNU”), and the memory, the first arbitration unit configured to receive requests from the input-output bus to read or write data and receive requests from the MFNU to free memory and choose among the requests from the input-output bus and from the MFNU to send to the memory on a first memory bus; and a second bridge unit for packet data access with the memory coupled with a packet input unit, packet output unit, and the memory, the second bridge unit including a second arbitration unit, the second arbitration unit coupled with the packet input unit, the packet output unit, and the memory, the second arbitration unit configured to receive requests to write packet data from the packet input unit and receive requests to read packet data from the packet output unit, and choose among the requests from the packet input unit and the packet output unit to send to the memory on a second memory bus.