Patent ID: 7751418

Claim:
An apparatus for controlling the transmission of data, comprising: first and second integrated circuit (IC) chips, and data transmission means including a data bus for transmitting data from said first integrated circuit chip to said second integrated circuit chip; the first integrated circuit chip having a memory for receiving data for transmission to said second integrated circuit chip, and said second integrated circuit chip having a scheduler and a data output port, said scheduler being arranged to control, through a control bus interconnecting the first IC chip and the second IC chip, the transfer of data from said memory to said data output port via the data transmission means; wherein said second IC includes departure request transmission means for transmitting a departure request from said second IC to said first IC identifying a part of said memory from which a data packet is to be output to the second IC, and said data transmission means is responsive to said departure request for transferring data from said identified part of said memory to said second IC.