Patent ID: 7977227

Claim:
A method of manufacturing a non-volatile semiconductor memory device, comprising: providing a substrate having a charge-trapping stack and a first polysilicon layer formed thereon; selectively patterning through the charge-trapping stack and the first polysilicon layer to expose the substrate and form a gate structure; forming an insulating layer and a second polysilicon layer on the exposed substrate; selectively patterning the second polysilicon layer to form a sub-gate structure; forming a third polysilicon layer over the gate structure and sub-gate structure; patterning the charge-trapping stack and the first polysilicon layer in a first direction; forming a metal silicide over the third polysilicon layer; and patterning the metal silicide, the first polysilicon layer, and the third polysilicon layer in a second direction, wherein the second direction is perpendicular to the first direction.