Patent ID: 7653789

Claim:
A method for reducing coherence traffic in a multiprocessor system by supporting both coherent memory accesses and non-coherent memory accesses, the method comprising: receiving a request to perform a memory access; obtaining a page table entry (PTE) associated with the memory access; determining if the memory access is a coherent memory access or a non-coherent memory access by examining an indicator bit in the PTE, wherein during a coherent memory access, memory is accessed using a cache-coherence protocol, which generates coherence traffic, and wherein during a non-coherent memory access, memory is accessed without performing a cache-coherence operation, which does not generate coherence traffic; if the indicator bit indicates that the memory access is a coherent memory access, performing the memory access using a coherence protocol; and if the indicator bit indicates that the memory access is a non-coherent memory access, performing the memory access without generating coherence traffic, which further involves: determining if the request to perform the memory access is directed to a local memory or a remote memory; if the request is directed to a local memory, performing the memory access without generating coherence traffic; and if the request is directed to a remote memory, disallowing the memory access, or converting the associated page to be coherent and proceeding with the memory access.