Patent ID: 7960792

Claim:
A non-volatile memory, comprising: a silicon on insulation (SOI) substrate, comprising a first conductive type silicon body layer; a memory cell, disposed on the SOT substrate, the memory cell comprising: a first gate, disposed on the SOT substrate, the first gate comprising: a first portion; and a second portion, disposed at an end of the first portion, and the first portion being substantially perpendicular and connecting with the second portion; a charge storage structure, disposed between the first gate and the SOI substrate; a bottom dielectric layer, disposed between the charge storage structure and the SOI substrate; and a second conductive type first source/drain region and a second conductive type second source/drain region disposed in the first conductive type silicon body layer at two sides of the first portion; a selecting transistor, disposed on the SOI substrate, the selecting transistor comprising: a second gate, disposed on the SOI substrate; a gate dielectric layer, disposed between the second gate and the SOI substrate; and the second conductive type second source/drain region, disposed in the first conductive type silicon body layer at one side of the second gate, wherein the selecting transistor and the memory cell share the second conductive type second source/drain region in common; and a second conductive type third source/drain region disposed in the first conductive type silicon body layer at another side of the second gate; and a first conductive type first doped region disposed in the first conductive type silicon body layer at one side of the second portion, and interspaced by the second portion to be opposite to the second conductive type first source/drain region and the second conductive type second source/drain region.