Patent ID: 7657798

Claim:
A semiconductor integrated circuit, comprising: a cell array having a plurality of memory cells; a redundancy control circuit configured to perform control for replacing a defective memory cell with a redundancy cell; a plurality of first fuses programmed in accordance with identification information for specifying a chip mounting the cell array; a plurality of second fuses programmed in accordance with redundancy information for replacing the defective memory cell with the redundancy cell and various setting information of the chip; a plurality of third fuses programmed in accordance with a CRC (Cyclic Redundancy Check) code generated based on the redundancy information, various setting information of the chip and the identification information; a first shift register configured to hold states of the plurality of first fuses; a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses; a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses; a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division; and a CRC determination part configured to output information indicative of whether the first to third fuses are correctly programmed.