Patent ID: 7420641

Claim:
A method of forming an array substrate for use in an in-plane switching liquid crystal display device, comprising; forming gate lines, common lines, gate electrodes, and common electrodes, wherein the common line is disposed between two gate lines, the gate electrode extends from the gate lines toward the common line, and the common electrode extending from the common line is arc shaped; forming a gate insulating layer on the gate lines, common lines, gate electrodes, and common electrodes; forming a semiconductor layer on the gate insulating layer, the semiconductor layer including a first layer of pure amorphous silicon and a second layer of doped amorphous silicon; forming data lines, source electrodes and drain electrodes, wherein the data lines are substantially perpendicular to and cross the gate and common lines, each of the source electrodes extending from the data lines over a first end portion of the semiconductor layer, each of the drain electrodes being spaced from a corresponding source electrode and overlapping a second end portion of the semiconductor layer, and pairs of the gate and data lines defining a pixel region, wherein the pixel region is divided into a plurality of sub pixels; forming a passivation layer on the data lines, the source electrodes and the drain electrodes, the passivation layer having drain contact holes exposing a portion of the drain electrodes; and forming capacitor electrodes and pixel electrodes, the capacitor electrodes being disposed over a portion of the common electrodes and in contact with the drain electrodes through the drain contact holes in each of the sub pixels, wherein the pixel electrodes are connected to the capacitor electrodes in each of the sub pixels through a pixel connecting line, wherein the common electrodes and the pixel electrodes are arc shaped within the pixel region.