Patent ID: 8106912

Claim:
A control method of a parallel image processing system having a smaller number of element processors than number of images to be processed, each element processor being controlled by a command fetching/decoding part to process plural images to be processed, the parallel image processing system including: a repetitive-execution specifying register for specifying a number of repetitions NR when performing repetitive execution of a command assigned to each element processor according to a ratio of the number of element processors to a number of pixels in a width direction of an image to be processed; a height-of-image-to-be-processed register for holding a number of pixels NH in a height direction of the image to be processed, where the number of pixels NH is used to calculate an offset value of an address storing the image to be processed in the repetitive execution of a memory access command assigned to one of the element processors; and a repetitive-execution counter CR used when the command is repetitively executed by the number of times specified by the repetitive-execution specifying register; the method comprising: determining whether or not the command requires operand conversion by an operation code input from the command fetching/decoding part; if the operand conversion is necessary, dividing a number of registers in a register group of the element processors by the number of repetitive-executions NR stored in the repetitive-execution specifying register; multiplying each divided number of registers by a value from 0 to (NR−1) stored in the repetitive-execution counter to obtain an offset value used in switching a register position; and outputting the offset value to the command fetching/decoding part; performing, if the operation code input from the command fetching/decoding part is a read/write command of a local memory of one of the element processors, address conversion of adding a value obtained by multiplying the NH of the height-of-image-to-be-processed register and the CR of the repetitive counter to an input address; and outputting the converted address to the command fetching/decoding part; and calculating, if the operation code input from the command fetching/decoding part is an acquisition command of an adjacent pixel value, a pixel position in a plurality of pixels assigned to each element processors of a pixel, which is a current execution target, by the CR and NR of the repetitive-execution counter and the repetitive-execution specifying register; determining whether the adjacent pixel value to be acquired is held in the register of its element processor or is held in the register of an adjacent element processor; and outputting an operation code converted so as to be read from the register of its element processor or the register value is transferred from the adjacent element processor, to the command fetching/decoding part.