Patent ID: 7831774

Claim:
A memory component comprising: a first pipeline path for selecting a least recently used (LRU) victim member from a congruence class; a mechanism for biasing a faulty member of the memory component against being selected as the victim member by the first pipeline path, said faulty member corresponding to a cache line that is unable to provide proper caching operation, wherein the mechanism includes a second pipeline path, separate from the first pipeline path, for routing information about which member is a faulty member; an MRU update logic that includes logic for separately making the faulty member MRU without affecting a directional pointer of LRU selection chronology vectors for a multi-level chronology vector LRU selection mechanism; and logic for generating a make MRU vector from an index indicating one or more locations of faulty member(s) and forwarding the make MRU vector to the MRU update logic independent of pipelining and processing of member protection bits for generating a final make MRU vector.