Patent ID: 6924670

Claim:
A muxed-decoder circuit, comprising: a plurality of complementary input dynamic circuits, each associated with a corresponding one of a plurality of multi-bit encoded addresses and with a corresponding one of a plurality of decoded bits, each complementary input dynamic circuit comprising: a complementary P-logic AND dynamic circuit, having an output coupled to a corresponding one of a plurality of output evaluation nodes, that evaluates bits of an address value corresponding to one of said plurality of encoded addresses and bits of a digital select value having a logic state for selecting said corresponding encoded address in response to a clock signal; a complementary N-logic AND dynamic circuit, having an output coupled to a corresponding one of a plurality of preliminary evaluation nodes, that evaluates inverted bits of said address value and inverted bits of said digital select value in response to said clock signal; and a pass device, coupled between said corresponding second evaluation node and said corresponding first evaluation node, that drives said corresponding second evaluation node low if said complementary N-logic AND dynamic circuit fails to evaluate; and an AND logic gate having a plurality of inputs, each coupled to a corresponding one of said plurality of output evaluation nodes and an output for providing a corresponding one of said plurality of decoded bits.