Patent ID: 7340592

Claim:
A method of translating instructions, said method comprising: translating a first block of instructions executable in a first processor architecture into a translated first block of instructions executable in a second processor architecture, said translated first block of instructions operating with a stack of data entry positions; during the translating, generating an expected Top of Stack (TOS) position in said stack for said first block of instructions; during the translating, adding at least one instruction to said translated first block of instructions to determine if a first expected TOS is equal to an actual TOS position in said stack at a time of executing said translated first block of instructions; and executing said translated first block of instructions without restarting the translating, wherein during the executing said at least one instruction to branch to correction code if said expected TOS is not equal to said actual TOS, said correction code to generate a delta of said expected TOS and said actual TOS and to adjust said stack for said first block of instructions by said delta at the time of executing said translated first block of instructions; wherein said translated first block of instructions to continue executing after said at least one instruction adjusts said stack.