Patent ID: 8154905

Claim:
A semiconductor memory comprising: first and second bit lines; a word line not parallel to either the first or second bit line; a resistive memory element comprising a first end and a second end, the first end being connected with the first bit line; a selective switch element comprising a current path and a control terminal, a first end of the current path being connected with the second end of the resistive memory element, a second end of the current path being connected with the second bit line, the control terminal being connected with the word line; a first column switch connected with the first bit line; a second column switch connected with the second bit line; a first common line connected with the first bit line through the first column switch; and a second common line connected with the second bit line through the second column switch, wherein while starting writing or reading data with respect to the resistive memory element, after a bit line to be set to a high level in the first and second bit lines is activated and charged from a low level to a high level, the word line is configured to be activated.