Patent ID: 8381163

Claim:
A circuit comprising: a master latch of a master-slave flip-flop, wherein the master latch is coupled to a first global voltage node and a virtual voltage node, wherein the master latch is configured to receive a data input signal; a slave latch of the master-slave flip-flop, wherein the slave latch is coupled to receive the data input signal from the master latch, wherein the slave latch is coupled to the first global voltage node and a second global voltage node, and wherein the slave latch is configured to provide a data output signal based on at a state dependent on a state of the data input signal; a power-gating circuit coupled between the virtual voltage node and the second global voltage node, wherein the power-gating circuit is configured to, when active, couple the virtual voltage node to the second global voltage node, wherein the virtual voltage node and the second global voltage node are decoupled when the power-gating circuit is inactive; and a power control circuit is configured to place the master-slave flip-flop in a sleep mode by deactivating the power-gating circuit to power down the master latch and inhibiting a clock signal from being provided to each of the master and slave latches, and wherein the slave latch is configured to retain power when in the sleep mode.