Patent ID: 6933557

Claim:
A block alterable memory cell, comprising: a substrate layer including an active region having a source implant region, a buried implant region essentially contiguous with said source implant region, a tunnel window region overlaying said buried implant region, and a drain implant region spaced apart from the buried implant, all in the active region; a tunnel oxide layer overlaying the tunnel window and a portion of said buried implant region; a floating gate oxide layer overlaying said tunnel window region; a floating gate layer overlaying said tunnel oxide layer and said floating gate oxide layer; an interpoly layer having a first region overlaying said floating gate layer, said interpoly layer having a second region extending continuously from the first region and overlaying an edge of said source implant region to an edge of said drain implant region; and a control gate layer extending continuously over said interpoly layer, said control gate layer extending from an edge of said source implant region to an edge of said drain implant region, whereby the control gate controls a first transistor having said floating gate and simultaneously controls a second adjacent select transistor having said source and drain.