Patent ID: 8482987

Claim:
An apparatus, comprising: a memory array of an integrated circuit, including a plurality of erase sectors of nonvolatile memory cells; a plurality of word lines accessing the nonvolatile memory cells; and control logic of the integrated circuit, wherein the control logic is responsive to an erase command by performing a multi-phase erase procedure on an erase sector of the plurality of erase sectors of the memory array, and wherein the control logic is responsive to an erase suspend command by performing an erase suspend procedure suspending the multi-phase erase procedure and allowing a non-erase command to perform a non-erase procedure on the memory array, and the erase suspend procedure applies a bias arrangement to at least one of the plurality of word lines accessing the erase sector during the non-erase procedure, the bias arrangement decreasing leakage from over-erased nonvolatile memory cells of the erase sector.