Patent ID: 7872295

Claim:
An integrated circuit, comprising: a memory cell region having a plurality of memory cell transistors, each memory cell transistor including a tunnel barrier layer formed on a substrate, and a charge storage layer formed above the tunnel barrier layer and a blocking layer formed above the charge storage layer, and its transistor gate electrode formed above the blocking layer; a first trench isolation (TI) formed in the memory cell region for isolating at least one of the memory cell transistors; a peripheral region outside of the memory cell region including low voltage transistors and high voltage transistors, wherein each of the low voltage transistors (LVT) and the high voltage transistors (HVT) includes the tunnel barrier layer; a second trench isolation (TI) formed in the peripheral region for isolating at least one of the low voltage transistors; and a third trench isolation (TI) formed in the peripheral region for isolating at least one of the high voltage transistors, wherein the tunnel barrier layer includes a first dielectric layer and a second dielectric layer.