Patent ID: 8373444

Claim:
A time-domain voltage comparator for an analog-to-digital converter, comprising: a first voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; a second voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; and a phase detector configured to determine a difference between times outputted from the first voltage-to-time converter and the second voltage-to-time converter, wherein, in order to control a transition time of a rising edge by controlling a pull-up path, the time delay cell comprises: a first PMOS having a source terminal which is connected to a power supply terminal, and a gate terminal which is connected to a clock signal terminal; a first NMOS having a drain terminal which is connected to a drain terminal of the first PMOS, a gate terminal which is connected to the clock signal terminal, and a source terminal which is connected to a ground terminal; a second PMOS having a gate terminal which is commonly connected to the drain terminals of the first PMOS and the first NMOS; an input PMOS having a source terminal which is connected to the power supply terminal, a gate terminal which is connected to a positive input voltage terminal or a negative input voltage terminal, and a drain terminal which is connected to a source terminal of the second PMOS; and a second NMOS having a drain terminal which is connected to a drain terminal of the second PMOS, a gate terminal which is commonly connected to the drain terminals of the first PMOS and the first NMOS, and a source terminal which is connected to the ground terminal.