Patent ID: 8843871

Claim:
A method for optimizing a circuit design, the method comprising: receiving the circuit design; and optimizing, by using a computer, gate sizes in the circuit design in a reverse-levelized processing order, wherein a level associated with a logic gate is greater than the highest level associated with logic gates that are electrically coupled to a fan-in of the logic gate, wherein optimizing logic gates in reverse-levelized processing order comprises optimizing gates in decreasing order of their associated levels, and wherein sizes of a set of gates at a given level in the circuit design are optimized by: collecting circuit information, wherein the circuit information includes generic logical effort values of each gate in the set of gates, an input capacitance value and a specific logical effort value of a driver gate that drives one or more inputs of each gate in the set of gates, and a wire resistance value of a net that electrically connects an output of the driver gate with one or more inputs of each gate in the set of gates, wherein a specific logical effort value is a logical effort value of a timing arc of a library cell or an average of logical effort values of multiple timing arcs of the library cell, and wherein a generic logical effort value is a logical effort value a timing arc of a library cell type or an average of logical effort values of multiple timing arcs of the library cell type, and determining gate sizes for the set of gates by substituting values from the collected circuit information into a set of closed-form expressions.