Patent ID: 7915921

Claim:
A circuit comprising: a clocked latch having a first input to receive a digital data signal, a second input to receive a complement of the digital data signal, and a third input to receive a clock signal; a second latch having a first input, a second input, a first output, and a second output; a first capacitor having a first terminal coupled to a first output of the clocked latch and a second terminal coupled to the first input of the second latch; and a second capacitor having a first terminal coupled to a second output of the clocked latch and a second terminal coupled to the second input of the second latch, wherein the first output and second output of the second latch are responsive, synchronously, to the digital data signal, the complement of the digital data signal, and the clock signal received by the clocked latch, wherein the clocked latch receives a first power supply voltage and a second power supply voltage, wherein the first power supply voltage is greater than the second power supply voltage, wherein the second latch receives a third power supply voltage and a fourth power supply voltage, wherein the third power supply voltage is greater than the fourth power supply voltage, and wherein the first power supply voltage is different than the third power supply voltage and the second power supply voltage is different than the fourth power supply voltage.