Patent ID: 7318214

Claim:
A method of compensating a target layout design for use in manufacture of integrated circuit devices, said method comprising: deriving a systematic variability signature, on a full reticle field-wide basis, based on process and equipment conditions applicable to the manufacturing process, generating compensation models or rules from the systematic variability signature, wherein the effects of said models or rules encompass the whole reticle field and are field location dependent, and applying the compensation models or rules to the target layout design, in a field location dependent manner, to produce a compensated layout design, and wherein the process and equipment conditions are specific to a mask making stage of the manufacturing process, the target layout design describes the physical layout of a fabrication layer of multiple mutually adjacent instances of an integrated circuit design within a reticle field, the step of deriving the variability signature comprises dividing the reticle field into multiple compensation zones, whereby each compensation zone contains features of the target layout design, and the step of generating compensation models or rules from the variability signature comprises generating compensation models or rules for the compensation zones respectively.