Patent ID: 8730712

Claim:
A static random access memory (SRAM) device comprising: a bit cell connected with a word line, connected between a bit line and a complementary bit line, and receiving an internal voltage from a write assist circuit, wherein the write assist circuit comprises; a power control circuit that charges/discharges an internal voltage line to provide the internal voltage in response to at least one control signal, and a compensation circuit that controls a level of the internal voltage, the compensation circuit comprising: a P-type metal oxide semiconductor (PMOS) transistor having a first terminal connected with the internal voltage line; a first N-type metal oxide semiconductor (NMOS) transistor having a first terminal connected with a second terminal of the PMOS transistor, a second terminal connected with a bit line, and a gate connected with the complementary bit line; and a second NMOS transistor having a first terminal connected with the second terminal of the PMOS transistor, a second terminal connected with the complementary line, and a gate connected with the bit line.