Patent ID: 7864579

Claim:
An integrated circuit comprising: a memory cell arrangement, the memory cell arrangement comprising a plurality of memory cell blocks, each memory cell block comprising a plurality of memory cells; means for storing information about a quality characteristic of the memory cells of an assigned one of the memory cell blocks; and means for controlling a read operation on memory cells of a memory cell block out of the plurality of memory cells, wherein the means for controlling is further configured to change the information about the quality characteristic depending on a quality of a read operation, wherein the means for controlling a read operation is further configured to control an erase operation on memory cells of a memory cell block out of the plurality of memory cell blocks such that a current erase characteristic of the memory cells of the memory cell block is determined, and such that further depending on the determined current erase characteristic of the memory cells of the memory cell block, a predefined second action is carried out for the memory cell block.