Patent ID: 7904705

Claim:
A pipelined instruction microprocessor system with a repairable speculative global history prediction record, the system comprising: a pipeline including a plurality of sequential stages for parallel processing microprocessor instructions, each microprocessor instruction including a plurality of consecutive operations, the pipeline including a first stage for processing a first conditional branch operation from a first microprocessor instruction; a sequencer with an interface for accessing the pipelined stages and processing the operations; a first address register containing a first branch address associated with the first conditional branch operation; a speculative global history record (SGHR) to provide a first vector representing a combination of resolved branch decisions and predicted branch decisions executed immediately before the first conditional branch operation; a non-speculative global history record (NSGHR) of branch resolutions having an input to accept a first branch resolution and an output for updating the SGHR in response to a first branch prediction being incorrect; a hashing circuit having an input to accept the first vector from the SGHR and an input to accept the first branch address, the hashing circuit performing an exclusive-OR (XOR) operation between a value representing the first vector and a value representing the first branch address, to provide a first hash result at an output; and, a branch history table (BHT) having an input to accept the first hash result, the BHT indexing previous first branch resolutions prediction, wherein the BHT increments a count in response to the first branch resolution being a branch taken and decrements the count in response to the first branch resolution being a branch not taken, and wherein the BHT clamps the count to a maximum value of m=2 n −1 and clamps the count to a minimum value of zero, where N is an integer value greater than one.