Patent ID: 7855930

Claim:
A power-on management circuit for a memory device, comprising: a first external power-on voltage detector having a first voltage threshold, receiving a first external voltage, and generating a first control signal when the first external voltage is higher than the first voltage threshold; a second external power-on voltage detector having a second voltage threshold, receiving a second external voltage, and generating a second control signal when the second external voltage is higher than the second voltage threshold; a delay unit coupled to the first external power-on voltage detector, and generating a third control signal by delaying the first control signal for a pre-determined time; a logic circuit coupled to the second external power-on voltage detector and the delay unit, receiving the second control signal and the third control signal, and generating a first enabling signal; an internal power-on voltage detector having an input coupled to the first external power-on voltage detector, receiving the first control signal, and generating a fourth control signal based upon the first control signal; a voltage control circuit receiving the fourth control signal, and generating a second enabling signal based upon the fourth control signal; a plurality of first electric pumps coupled to the logic circuit, and activating one of an on and an off actions based upon the first enabling signal; and a second electric pump coupled to the voltage control circuit, and activating one of an on and an off actions based upon the second enabling signal.