Patent ID: 7561023

Claim:
An electrical circuit, comprising: a first counter circuit A for receiving a first enable signal INC_A and generating a first output signal SIG_A; a second counter circuit B for receiving a second enable signal INC_B and generating a second output signal SIG_B, wherein the first enable signal INC_A and the second enable signal INC_B are for comparing the first output signal SIG_A to the second output signal SIG_B; a flip-flop circuit for generating a first status signal defining a first relationship between said first output signal SIG_A and said second output signal SIG_B; a logic circuit for generating a second status signal defining a second relationship between said first output signal SIG_A and said second output signal SIG_B, wherein the logic circuit electrically connects said first counter circuit A and said second counter circuit B to said flip-flop circuit, wherein an output of said first counter circuit A is electrically connected to a first input of said logic circuit, wherein an output of said second counter circuit B is electrically connected to a second input of said logic circuit, and wherein an output of said logic circuit is electrically connected to an enable input E on said flip-flop circuit; a first OR gate electrically connected to an input PRE of the flip-flop circuit, wherein said first OR gate is for receiving a signal PRE_A and a signal RST_B, Oring said signal PRE_A and said signal RST_B to generate a first ORed signal, and applying said first ORed signal to said input PRE of the flip-flop circuit; and a second OR gate electrically connected to an input RST of the flip-flop circuit, wherein said second OR gate is for receiving a signal PRE_B and a signal RST_A, Oring said signal PRE_B and said signal RST_A to generate a second ORed signal, and applying said second ORed signal to said input RST of the flip-flop circuit.