Patent ID: 7364784

Claim:
A method of manufacturing a semiconductor device package comprising: preparing a lead frame blank from a conductive material, the lead frame blank having a substantially uniform blank thickness T B ; removing a portion of the conductive material from a mounting region to form a recess of substantially uniform depth T R0 , a substantially planar thinned region having thickness T P and a terminal region having a thickness T T , wherein T B is substantially equal to T R0 +T P and T T is substantially equal to T B ; repositioning a central portion of the thinned region within the recess to form a substantially planar paddle region having a upper surface and a lower surface, such that an overall thickness of the lead frame is substantially equal to T B and to form a second recess having a depth T RU between the upper surface of the paddle region and an upper surface of the terminal region and a third recess having a depth T RL between the lower surface of the paddle region and a lower surface of the terminal region, wherein T RU >T RL ; removing a central region of the paddle region; forming leads preparing a semiconductor chip having an active surface and a backside surface, a plurality of bonding pads being arrayed on the active surface; mounting a portion of the active surface to the paddle region with the bonding pads exposed, which includes forming an adhesive region on an upper surface of the paddle region; removing a central region of the paddle region, and mounting the active surface of the semiconductor chip on the adhesive region; providing bonding wires between the bonding pads and corresponding leads to establish a plurality of electrical connections; and encapsulating the semiconductor chip, the bonding wires and a portion of the lead frame with a polymeric material, the polymeric material having a maximum thickness approximately equal to T B and exposing upper and lower surfaces of the terminal region to form the semiconductor device package.