Patent ID: 8451651

Claim:
A semiconductor device comprising: a write word line; a read word line; a bit line; a signal line; a first memory cell; a first driver circuit; and a second driver circuit, wherein the first memory cell comprises: a first transistor comprising a first channel formation region; a second transistor comprising a second channel formation region comprising an oxide semiconductor; and a capacitor, wherein a gate of the first transistor is electrically connected to one of two electrodes of the capacitor and one of a source and a drain of the second transistor, wherein the capacitor is configured to hold a voltage between the two electrodes of the capacitor by turning off the second transistor, wherein the first driver circuit is electrically connected to one of a source and a drain of the first transistor through the bit line and electrically connected to the other of the source and the drain of the second transistor through the signal line, wherein the second driver circuit is electrically connected to the other of the two electrodes of the capacitor through the read word line and electrically connected to a gate of the second transistor through the write word line, and wherein the second driver circuit is configured to delay a signal input to the signal line relative to a signal input to the write word line.