Patent ID: 8779825

Claim:
A signal processing apparatus comprising: a delaying unit that inputs an output signal output continuously from an arithmetic circuit, delays the output signal input, and outputs the output signal delayed as a delayed signal; a comparing unit that inputs the output signal from the arithmetic circuit and inputs the delayed signal from the delaying unit in parallel with the input of the output signal from the arithmetic circuit, compares signal values between the output signal and the delayed signal input at same timing, and outputs one of a match signal and a mismatch signal as a comparison result signal, the match signal notifying that the compared signal values of the output signal and the delayed signal match each other, and the mismatch signal notifying that the compared signal values of the output signal and the delayed signal mismatch each other; a determining unit that inputs a clock signal and inputs the comparison result signal from the comparing unit in parallel with the input of the clock signal, and determines, every time determination timing comes, whether the comparison result signal input in parallel at the determination timing is a match signal or a mismatch signal, the determination timing being at least one of clock rise timing and clock fall timing; and an output unit that inputs the output signal from the arithmetic circuit, and outputs the output signal from the arithmetic circuit when the determining unit inputs the match signal at determination timing, and outputs a specific fixed value instead of the output signal from the arithmetic circuit after the determining unit inputs the mismatch signal at the determination timing.