Patent ID: 8456409

Claim:
A gate drive circuit in which stages of the gate drive circuit are connected one after another to each other, the stages outputting gate signals, an m-th stage, ‘m’ being a natural number, comprising: a pull-up section that outputs a first clock signal as a gate signal of the m-th stage to an output terminal in response to a high voltage of a first node signal which is converted into a high level in accordance with a vertical start signal or a carry signal of one of previous stages of the m-th stage; a pull-down section that applies a low voltage to the output terminal in response to a high voltage of the gate signal of one of next stages of the m-th stage; a carry section that outputs the first clock signal as a carry signal of the m-th stage in response to the high voltage of the first node signal; a first carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to the high voltage of the first clock signal when the gate signal of the m-th stage is maintained at the low voltage; a second carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to a high voltage of a second clock signal having a different phase from the first clock signal, and a third carry holding section that maintains the carry signal of the m-th stage at the low voltage in response to the gate signal of the one of the next stages of the m-th stage, wherein a gate of a transistor of the third carry holding section is directly connected to a terminal that provides the gate signal of the one of the next stages of the m-th stage.