Patent ID: 8369054

Claim:
A protection circuit comprising: a clamping transistor, coupled to shunt current from an electrostatic discharge (ESD) pulse applied to an ESD node, having a control gate coupled to a gate node; a filter capacitor coupled to a filter node; a filter resistor coupled to the filter node; a first inversion stage, receiving the filter node as an input, and driving a first node as an output; a second inversion stage, receiving the first node as an input, and driving a second node as an output; a third inversion stage, receiving the second node as an input, and driving the gate node as an output; a feed-forward resistor coupled between the filter node and the second node, for extending the charging time of the second node during the ESD pulse; and a sub-threshold-conducting transistor, in the first inversion stage, and receiving the second node on a control gate, for limiting a first current to the first node through the first inversion stage during the ESD pulse, whereby the clamping transistor remains on while the sub-threshold-conducting transistor conducts sub-threshold current.