Patent ID: 7080297

Claim:
A memory circuit, comprising: a memory cell array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, said plurality of memory cells being addressable via said plurality of word lines and bit lines; a plurality of primary sense amplifiers for reading out, via said plurality of bit lines, data from said plurality of memory cells in accordance with a read-out address; a plurality of secondary sense amplifiers, each of said plurality of secondary sense amplifiers including a latch; a plurality of switching devices, a group of said plurality of primary sense amplifiers being connected to an assigned one of said plurality of said secondary sense amplifiers via a group of said plurality of switching devices for applying a datum from one of said plurality of primary sense amplifiers of said group to said assigned one of said plurality of secondary sense amplifiers via one of said plurality of switching devices selected by a read-out address; and a test control unit configured for reading out data by connecting some of said plurality of switching devices in parallel depending on a test mode signal and depending on the read-out address, so that in each case, one of said group of primary sense amplifiers is connected to said assigned one of said plurality of secondary sense amplifiers.