Patent ID: 8443313

Claim:
A computer-implemented method, comprising: generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration; wherein the first configuration comprises a first master latch, a first fanout path, and a logic cone; the first master latch coupled to the first fanout path; the first master latch configured to receive a first data input signal; wherein the first fanout path comprises a plurality of output sinks, each of the plurality of output sinks coupled to the logic cone; modifying the first behavioral model to generate a second behavioral model, the second behavioral model describing the physical circuit in a second configuration; wherein the second configuration comprises an error circuit and an abstract latch clone; wherein the abstract latch clone is based on the first master latch; and generating a configuration file based on the second behavioral model; wherein the configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone; wherein the instantiated latch clones are each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks; and wherein the second behavioral model and the configuration file are together configured for input to a synthesis tool.