Patent ID: 7535058

Claim:
A lateral DMOS structure comprising a light doped p-type region beneath and near a gate at one side of a drain, the surface electric field near the gate being reduced, wherein lateral DMOS has a source which is formed as follow: defining an N-layer on a P-substrate; forming an N-well on the N-layer; forming a P-body in the N-well; forming an N+ diffusion region on the P-body and forming an N-LDD structure at one side of the N+ diffusion region; and forming a P+ diffusion region in the N+ diffusion region and forming the lateral DMOS source through a metal contact running through a contact hole; wherein the drain of the lateral DMOS is formed as follow: defining an N-layer on the P-substrate; forming an N-well on the N-layer; forming an N+ diffusion region in the N-well; and forming the lateral DMOS drain through a metal contact running through a contact hole in the N+ diffusion region; and wherein the gate of the lateral DMOS is formed as follow: defining an N-layer on the P-substrate; forming an N-well on the N-layer; forming the DMOS gate in the N-well through a poly-silicon layer wrapped by an isolation layer; wherein the gate region covers the P-body of the DMOS source and also covers the N+ diffusion region formed in the P-body and the N-LDD structure; and the gate region also covers the N+ diffusion region of the DMOS drain; the light doped p-type region is formed in the N-well adjacent to the N+ diffusion region of the drain of the lateral DMOS.