Patent ID: 8924823

Claim:
A system comprising: a parity bit encoder configured to encode successive blocks of n bits with a parity bit to provide successive blocks of n+1 bits; a Gray mapper coupled to said parity bit encoder and configured to map each one of said blocks of n+1 bits to an associated plurality of quadrature amplitude modulated (QAM) symbols; a modulator coupled to said Gray mapper and configured to modulate an optical signal in response to an output of said Gray mapper to provide a modulated optical signal comprising said associated plurality of QAM symbols; a detector for receiving said modulated optical signal and providing an electrical signal representative of said optical signal; and a de-mapper configured to provide a de-mapper output representative of said blocks of n bits in response to said electrical signal, said de-mapper being further configured to cause correction of cycle slip using parity indicated by said parity bit.