Patent ID: 8127187

Claim:
A first card for attachment to test load boards containing one or more devices under test (DUTs), the first card being attachable to custom-built test load boards to relieve automated test equipment (ATE) from scanning of scan-test vectors into and out of the DUTs, the first card comprising: a first connector for connection to outside circuitry other than the ATE, the outside circuitry being for providing scan-test input vectors to the first card; a second connector for connection to the test load boards; a memory for storing the scan-test input vectors received through the first connector; circuitry for: (a) transferring the scan-test input vectors from the first connector to the memory; (b) transferring the scan-test input vectors from the memory to the second connector in scanning the scan-test input vectors into the one or more DUTs through one or more of a predefined maximum number of scan chains; (c) receiving scan-test output vectors from the second connector in scanning the scan-test output vectors out of the one or more DUTs through one or more of the scan chains; (d) providing test results derived from the scan-test output vectors to the ATE through the second connector; wherein the circuitry comprises a scan-clock circuit for providing a scan clock for the scanning in (b) and (c); wherein the first card is for NOT providing a clock signal to the one or more DUTs during ATE-controlled at-speed operation of the DUTs, the clock signal to be provided by the ATE; wherein at least one of conditions (A) and (B) is true: (A) the memory capacity is unrelated to ATE capacity to store scan test input vectors; (B) the predefined maximum number of scan chains is unrelated to a maximum number of scan chains supported by the ATE.