Patent ID: 7351631

Claim:
A method for fabricating a flash memory comprising: sequentially forming a first tunneling oxide layer and a floating gate on a semiconductor substrate; etching portions of the floating gate and the first tunneling oxide layer to form a window exposing the semiconductor substrate; forming a second tunneling oxide layer on inner side walls of the window; injecting impurity ions in the semiconductor substrate exposed through the window to form a common source; filling a conductive material into the window; chemical mechanical polishing to remove the conductive material, expose the floating gate, and form a common source line having a same height as the second tunneling oxide layer; selectively etching the floating gate to leave floating gates on outer side walls of the second tunneling oxide layer, the floating gates having a predetermined width; sequentially forming a dielectric layer and a control gate over the floating gates; and forming drains by injecting impurity ions into the semiconductor substrate using the control gate and the common source line as a mask.