Patent ID: 7392270

Claim:
A method, in a data processing device, for calculating a decoded shift amount to reduce latency of a hardware shifter, comprising: partitioning a plurality of input numbers into a plurality of bit groups; conveying the plurality of bit groups to at least one hardware sum decoder, wherein the plurality of bit groups of each of the plurality of input numbers gets distributed over the at least one hardware sum decoder and wherein the at least one hardware sum decoder gets one of the plurality of bit groups from each of the plurality of input numbers; conveying a copy of the plurality of bit groups to a carry network; employing the at least one hardware sum decoder to decode at least one decoded shift amount for one of a plurality of shifter stages; generating a plurality of group carry signals as a function of the copy of the plurality of bit groups; correcting the at least one decoded shift amount from the at least one hardware sum decoder as a function of the group carry signals thereby forming a corrected output signal; and employing the corrected output signal as a select signal in a set of select signals for one of the plurality of shifter stages in the hardware shifter wherein the plurality of shift stages compute a value using the set of select signals thereby reducing the latency of the hardware shifter and wherein the value is used to shift a fraction of an operand by the value so that the operand aligns with a fraction of an intermediate product.