Patent ID: 8285919

Claim:
A memory controller, comprising: a plurality of processors of a first type each configured to be coupled to at least one memory channel of a solid state memory device, each of the plurality of processors of the first type configured to determine a bad block rate of the at least one memory channel to which it is configured to be coupled; and a processor of a second type in signal communication with each of the plurality of processors of the first type, the processor of the second type configured to: receive the bad block data rates from each of the plurality of processors of the first type, and report one of a total capacity or a bad block rate of the solid state memory device to a host device, the total capacity and the bad block rate of the solid state memory device based on the bad block rates received from each of the plurality of processors of the first type, wherein the bad block rate of the solid state memory device is determined by calculating an average of the bad block rates received from each of the plurality of processors of the first type.