Patent ID: 7588977

Claim:
A method of fabricating a MOSFET (metal oxide semiconductor field effect transistor) having a plurality of channels, the method comprising: sequentially forming, at least one time, a first material layer and a semiconductor layer that have an etching selectivity with respect to each other on a semiconductor substrate; forming a first mask layer pattern extending in a first direction and having a predetermined width, on the semiconductor layer; etching the semiconductor layer and the first material layer using the first mask layer pattern as an etch mask to form recess regions where the first material layer is exposed by the first mask layer pattern; forming at least one first reduced mask layer pattern having a width smaller than the width of the first mask layer pattern; forming a filling material layer on the surface of the semiconductor substrate, and performing a surface planarization to expose the upper surface of the first reduced mask layer pattern; forming at least one pair of second mask layer patterns extending in a second direction perpendicular to the first direction and spaced apart so as to expose the upper surface of the first reduced mask layer pattern between the at least one pair of second mask layer patterns; etching the first reduced mask layer pattern, the semiconductor layer, and the first material layer using the second mask layer pattern and the filling material layer as an etch mask so as to form a first opening which exposes the first material layer; etching the filling material layer using the second mask layer pattern as an etch mask so as to form a second opening which exposes the first material layer; removing the exposed first material layer to expose a corresponding portion of the semiconductor layer; and forming a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer.