Patent ID: 7003747

Claim:
A method of achieving the timing convergence of one of a digital integrated circuit and a functional unit of a digital integrated circuit comprising of the steps of: partitioning a design into macros; apportioning a timing and area budget to each of said macros; creating an objective function for an optimization of the at least one of said macros having contributions from a plurality of primary output signals in said macro; improving the timing characteristics of each of the at least one selected macros by attempting to minimize said objective function; timing the overall design; and re-apportioning the timing and area budgets and repeating the said improving and timing steps until the required specifications are met; and in which the objective function comprises a summation of penalty contributions from each primary output siqnal, each of said penalty contributions being a non-decreasing penalty function of the the amount by which a timing requirement is violated in which said penalty function is a weighted and shifted exponential function of said violation amount.