Patent ID: 8361854

Claim:
A manufacturing process of a fin field-effect transistor structure, the manufacturing process comprising steps of: providing a substrate; forming a fin channel on the substrate; forming a polysilicon pseudo gate layer on a surface of the fin channel; forming a polysilicon pseudo gate structure by defining the polysilicon pseudo gate layer; performing a first implantation process by using the polysilicon pseudo gate structure as a mask, so that a source/drain region is formed in the fin channel; successively forming a contact etch stop layer and a first dielectric layer over the fin channel having the source/drain region, the polysilicon pseudo gate structure and the substrate; performing a first planarization process on the substrate having the first dielectric layer and the contact etch stop layer until the polysilicon pseudo gate structure is exposed; removing the polysilicon pseudo gate structure to form a receiving space; successively forming a high-k dielectric layer and a metal gate layer on the substrate having the receiving space; and performing a second planarization process on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.