Patent ID: 8782287

Claim:
A processing system comprising: first processing circuitry operative to perform a first function; first reassembly circuitry, associated with the first processing circuitry, operative to reassemble segments of received packets into reassembled packets, wherein the segments reassembled by the first reassembly circuitry are related to the first function; first memory circuitry, associated with the first processing circuitry, operative to store the packets reassembled by the first reassembly circuitry, wherein the reassembled packets stored by the first memory circuitry are used by the first processing circuitry in accordance with the first function, wherein the first function comprises a post-reassembly function to process the reassembled packets stored in the first memory circuitry; second processing circuitry operative to perform a second function; second reassembly circuitry, associated with the second processing circuitry, operative to reassemble at least a portion of the same segments of packets reassembled by the first reassembly circuitry into reassembled packets, wherein the segments reassembled by the second reassembly circuitry are related to the second function; and second memory circuitry, associated with the second processing circuitry, operative to store the packets reassembled by the second reassembly circuitry, such that at least a portion of the reassembled packets stored in the first memory circuitry and the second memory circuitry are the same, wherein the reassembled packets stored in the second memory circuitry are used by the second processing circuitry in accordance with the second function, wherein the second function comprises a post-reassembly function to process the reassembled packets stored in the second memory circuitry, wherein the first reassembly circuitry, the first memory circuitry, and the first processing circuitry are configured to implement a first processing path; wherein the second reassembly circuitry, the second memory circuitry, and the second processing circuitry are configured to implement a second processing path; and wherein the first and second processing paths are distinct and operate in parallel.