Patent ID: 7920017

Claim:
A programmable clock booster system comprising: a clock booster circuit including at least one boost capacitor connected between a first node and a second node for sampling an input voltage in a first phase and applying a boosting voltage to said second node during a second phase; a programmable attenuator capacitor circuit connected to said first node for sampling the input voltage in the first phase and providing a programmable boosted voltage having a voltage level between the input voltage and the sum of the input voltage and the boosting voltage on said first node during said second phase; a series-pass switch connected to said programmable attenuator capacitor circuit for preventing said programmable boosted voltage to pass to an output node in said first phase and allowing said programmable boosted voltage to pass to said output node in said second phase, said series-pass switch includes a voltage controlled switch responsive to a control voltage that enables or disables said series-pass switch; and a gate drive circuit including at least first and second switched capacitors connected to a gate of said series-pass switch for adjusting the voltage at said gate to a first predetermined voltage that disables said series-pass switch in said first phase and for adjusting the voltage at said gate to a second predetermined voltage that enables said series-pass switch in said second phase, wherein the first and second switched capacitors adjust the voltage at said gate to track the boosting voltage based on the programmable attenuator capacitor circuit.