Patent ID: 7672177

Claim:
A memory device, comprising: a single-port memory array; and a control module generating a plurality of control signals according to a clock signal, a read command signal and a write command signal; wherein the single-port memory array is accessed according to the control signals; wherein the single port-memory array is accessed at least once a clock cycle, wherein the control module comprises: a master circuit for generating a primary pre-charge signal and a primary enable signal according to the clock signal; a read clock generating circuit for generating a read clock signal according to the clock signal and the read command signal; and a write gating circuit for generating a write gating signal according to the clock signal and the write command signal; wherein the read command signal is triggered while a read command is asserted, and the write command signal is triggered while a write command is asserted; and wherein the primary pre-charge signal and the primary enable signal are triggered twice a clock cycle.