Patent ID: 6925086

Claim:
A packet memory system comprising: a memory cell array for storing a predefined number of packets; each packet including a predetermined number of segments; each of said segments for defining a starting point of a read/write memory access; a packet decoder coupled to said memory cell array and receiving packet select inputs for selecting a packet; a segment decoder coupled to said memory cell array and receiving segment select inputs for selecting a segment of said selected packet; a data flow multiplexer coupled to said memory cell array for transferring data between a data bus and said memory cell array for said read/write memory access; command and mode registers receiving command, read/write (R/W) and chip select (CS) inputs for opening said selected packet for said read/write memory access; and responsive to said selected packet being opened, a read/write segment command being issued for said selected segment of said selected packet for said read/write memory access, and on said packet select inputs a length of said read/write memory access being inputted.