Patent ID: 7240263

Claim:
An apparatus for performing level-sensitive scan design (LSSD) tests, said apparatus comprising: a first select register for generating a set of true encoded select signals from a set of select signals; a second select register for generating a set of complement encoded select signals from said set of select signals; a decoder, coupled to said first and second select registers, for receiving said set of true encoded select signals and said set of complement encoded signals, wherein said decoder includes a plurality of outputs, and one of said plurality of outputs is activated based on either said set of true encoded select signals or said set of complement encoded signals; and a plurality of multiplexors connected in series to form a delay chain to provide appropriate delays for an input signal during an LSSD test, wherein each of said plurality of multiplexors is connected to one of said plurality of outputs from said decoder, wherein one of said plurality of multiplexors is selected based on said activated output during said LSSD test.