Patent ID: 7523247

Claim:
A memory module comprising: a first edge finger and a second edge finger disposed along an edge of the memory module; a first signal line to carry a first signal between a first end of the first signal line and a second end of the first signal line, wherein the first signal enters the memory module at the first end of the first signal line, wherein the first end of the first signal line is coupled to the first edge finger, the first signal traversing the first signal line until reaching a first termination at the second end of the first signal line; a clock line to carry a clock signal between a first end of the clock line and a second end of the clock line, wherein the first end of the clock line is coupled to the second edge finger, wherein the clock signal enters the memory module at the first end of the clock line and traverses the clock line alongside the first signal until the clock signal reaches a second termination at the second end of the clock line; a first synchronous memory device connected to the first signal line at a first segment of the first signal line that is routed parallel to the edge of the memory module, wherein the first synchronous memory device is connected to the clock line at a first segment of the clock line that is routed parallel to the edge of the memory module, wherein the first signal and the clock signal arrive at the first synchronous memory device at substantially the same time; and a second synchronous memory device connected to the first signal line at the first segment of the first signal line, wherein the second synchronous memory device is connected to the clock line at the first segment of the clock line such that the first signal and the clock signal arrive at the second synchronous memory device at substantially the same time and after the first signal and the clock signal arrive at the first synchronous memory device.