Patent ID: 8443326

Claim:
A method for reordering a scan chain segment of a plurality of scan chains in an electronic circuit design using an electronic design automation (EDA) tool executing on a processor, wherein each scan chain includes a plurality of scan cells, the method comprising: accessing the integrated circuit design stored in the memory and generating a congestion map using the EDA tool executing on the processor; identifying a plurality of congestion areas in the plurality of scan chains, based on the congestion map generated by the EDA tool, wherein the plurality of congestion areas is marked by the EDA tool on the congestion map and wherein each congestion area includes at least one congestion portion; determining a routing preference for the at least one congestion portion; assigning routing preference attributes to scan cells of the at least one congestion portion; forming the scan chain segment of a first set of scan cells from the at least one congestion portion, wherein scan cells therein have identical routing preference attributes; and re-ordering the scan chain segment based on the routing preference attributes of the first set of scan cells, wherein re-ordering the scan chain segment includes connecting scan cells of scan chain segments associated with different scan chains in the same congestion area.