Patent ID: 7031194

Claim:
A nonvolatile semiconductor memory, comprising: a memory cell array including a plurality of memory cells provided in matrix form, a plurality of word lines, a plurality of bit lines, and a plurality of source lines; a word line control circuit to control the plurality of word lines; and a line control circuit to control the plurality of bit lines and the plurality of source lines; each of the plurality of memory cells including a gate electrode coupled to the word lines, a first impurity region coupled to the bit lines, a second impurity region coupled to the source lines, and an electron trap region provided in between the gate electrode and a substrate, the electron trap region being provided at least on the first impurity region side of the first impurity region side and the second impurity region side; and the word line control circuit, during a write operation in a selected memory cell, supplying a selection voltage to a selected word line coupled to the selected memory cell and supplying an erase-error preventing voltage to a non-selected word line coupled to each non-selected memory cell commonly coupled to a bit line that is coupled to the selected memory cell.