Patent ID: 6963949

Claim:
A memory system comprising: a memory controller; a separate unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus; a separate bidirectional data bus coupled to the memory controller, the memory controller communicating data information to the bidirectional data bus for a write operation and receiving the data information from the bidirectional data bus during a read operation; and a plurality N of pipelined memory subsystems, wherein each memory subsystem includes: a plurality M of memory devices wherein each memory device internally contains a data in and a data out buffer, a column decoder and a row decoder; a command buffer directly connected between the separate unidirectional command and address bus and the plurality of memory devices, the command buffer receiving and latching the commands and addresses from the separate unidirectional command and address bus and driving the commands and addresses to the plurality of memory devices, wherein the command buffer is shared by the plurality of M memory devices in the memory subsystem; and a data buffer directly connected between the plurality of M memory devices and the separate bidirectional data bus, the data buffer receiving and latching the data information from the separate bidirectional data bus and driving the data information to the plurality of M memory devices for a write operation, the data buffer receiving and latching the data information from the plurality of M memory devices and driving the data information to the separate bidirectional data bus for a read operation, wherein the data buffer is shared by the plurality of M memory devices in the memory subsystem.