Patent ID: 7460411

Claim:
A method for erasing a Flash memory array, the method comprising: in a Flash memory cell comprising a select transistor and a double gate transistor, the select transistor including a drain terminal coupled to a bitline, a gate terminal coupled to a word line, and a source terminal coupled to a drain terminal of the double gate transistor, the double gate transistor further including a control gate terminal coupled to a select line and a source terminal coupled to an array VSS line, the array VSS line being configured to electrically float during a portion of a programming operation until a potential V AVSS of the array VSS line approximately matches a reference voltage V ref , applying a potential of approximately zero volts to the select line; applying a word line potential V WL to the word line in order to bias the select transistor into conduction; applying a bitline potential V BL of approximately zero volts to the bitline; fixing the array VSS potential V AVSS at approximately zero volts; increasing a select line potential V SL applied to the select line from approximately zero volts to an erasing potential in a controlled time interval; maintaining the select line potential V SL at the erasing potential for an erase time interval; and returning the select line potential V SL to approximately zero volts in a controlled time interval.