Patent ID: 8076708

Claim:
An integrated circuit, comprising: a memory array in a first area of a substrate, the memory array including a plurality of word lines comprising a conductive material including a silicide layer, a plurality of bit lines comprising doped substrate regions, and a plurality of memory cells, the memory cells in the plurality comprising source and drain regions in the plurality of bit lines and a multilayer charge trapping structure having a first thickness, and including a top layer of dielectric, a bottom layer of dielectric and a charge trapping layer or charge trapping layers between the top layer and the bottom layer; an interlayer dielectric layer and conductor structure overlying the memory array; bit line contacts, connecting the conductor structure to the bit lines in the plurality of bit lines through the interlayer dielectric, in areas between groups of word lines in the plurality of word lines, wherein material deposited during formation of the charge trapping structures overlies the substrate beneath the interlayer dielectric between bit line contacts; transistors on the substrate having gate dielectric layers with a second thickness; and transistors on the substrate having gate dielectric layers with a third thickness, wherein the third thickness is greater than the second thickness.