Patent ID: 7519774

Claim:
A data processor comprising: a memory control unit being capable of controlling, in response to a clock, an external memory having plural banks and a plurality of bank caches, each bank cache corresponding to one of the external memory banks; a plurality of buses coupled to the memory control unit; circuit modules capable of accessing the external memory, each circuit module coupled to a respective one of the buses; a CPU as one of the circuit modules; and a cache memory located between the CPU and one of the buses, wherein each of the bank caches is capable of storing part of data of the corresponding external memory bank by using corresponding bank addresses as associative keys, and wherein the memory control unit validates the bank caches in response to an access request for a cache area of the bank caches that is not an objective area of the cache memory, and when the memory control unit validates the bank caches to a read access request for the external memory from the circuit modules, if the read access request is an associative miss to the bank caches, the memory control unit issues a read command that reads data relating to the read access request for the external memory, and stores the data read by this read command in a corresponding bank cache and outputs the data to a source of the read access request.