Patent ID: 7134069

Claim:
A memory system comprising: a memory comprising first and second groups of dynamic memory cells, each cell storing a bit; an access circuit connected to the memory to access, during an access cycle, a selected one of: a first set of the bits stored in said first group of said memory cells; and a second set of the bits stored in said second group of said memory cells; an error detection circuit connected to the access circuit and said memory to detect an error in a bit accessed during said access cycle, comprising: a first error detection circuit to detect an error in a bit of said first set of accessed bits; and a second error detection circuit to detect an error in a bit of said second set of accessed bits; and a scrub circuit connected to the memory to scrub, during a scrub cycle, a selected one of: said first set of the bits stored in said first group of said memory cells; and said second set of the bits stored in said second group of said memory cells.