Patent ID: 7391662

Claim:
A semiconductor device comprising: a memory cell array having a plurality of word lines, a plurality of bit lines and a plurality of memory cells each of which is located at an intersection between one of the word lines and one of the bit lines, wherein the bit lines includes a redundant bit line; a row decoder connected to the word lines, the row decoder selecting one of the word lines in response to a row address; a column decoder connected to the bit lines, the column decoder selecting one of the bit lines in response to a column address, the column address decoder selecting the redundant bit line when a second replacement signal is received thereto; a column address redundancy circuit storing a redundant column address, the column address redundancy circuit providing a replacement signal when the redundant column address corresponds to an address received thereto; and a mode setting circuit connected to the column address redundancy circuit and the column decoder for receiving a mode signal having a normal mode and a test mode, the mode setting circuit outputting the replacement signal received from the column address redundancy circuit to the column decoder when the mode signal is in the normal mode, and prohibiting the replacement signal received from the column address redundancy circuit to be outputted to the column decoder when the mode signal is in the test mode, wherein the fuse circuit includes: a main fuse circuit having a first fuse for indicating whether the redundant bit line is used, and a sub fuse circuit having a plurality of second fuses for storing the redundant column address.