Patent ID: 7138293

Claim:
A method of fabricating an integrated microdevice, comprising: providing a first silicon wafer; forming a first metal sealing ring on said first silicon wafer around a zone to be sealed; forming at least one bond pad outside said sealing ring and electrically connected to components inside said zone for establishing external electrical connections to said components; forming a first layer of gold or gold alloy on a surface of said first sealing ring; providing a second silicon wafer; forming a second metal scaling ring on said second silicon wafer; forming on a surface of said second metal sealing ring an under-layer of gold or gold alloy, and a solder over-layer selected from the group consisting of bismuth, cadmium, and tin; aligning said first and second sealing rings; and diffusion bonding said first and second silicon wafers together under pressure at said first and second metal sealing rings at a sufficient temperature to form a solution of gold or gold alloy and said solder at an interface between said first and second metal sealing rings such that said solder becomes consumed by said gold or gold alloy of said first layer and said under-layer to form a new layer comprising an alloy of said solder and said gold or gold alloy.