Patent ID: 8395425

Claim:
A system for generating one or more ramp signals, the system comprising: an oscillator configured to generate at least a clock signal; and a ramp signal generator configured to receive at least the clock signal and generate a first ramp signal, the ramp signal generator being coupled to a first resistor including a first terminal and a second terminal; wherein the first resistor being configured to receive an input voltage at the first terminal and being coupled to the ramp signal generator at the second terminal, the first resistor being associated with a first resistance value; wherein: the clock signal is associated with at least a predetermined frequency; the predetermined frequency does not change if the input voltage changes from a first magnitude to a second magnitude, the first magnitude being different from the second magnitude; the first ramp signal is associated with at least the predetermined frequency and a first slope, the first slope being related to an increase of the first ramp signal; and the first slope changes if the input voltage changes from the first magnitude to the second magnitude; wherein: the oscillator is coupled to a second resistor, the second resistor being associated with a second resistance value; the predetermined frequency depends at least in part on the second resistance value; and the predetermined frequency is independent of the input voltage in a substantial range.