Patent ID: 7755928

Claim:
A semiconductor device, comprising: a first CMOS inverter including a first n-channel MOS transistor and a first p-channel MOS transistor connected in series at a first node; a second CMOS inverter including a second n-channel MOS transistor and a second p-channel MOS transistor connected in series at a second node, said second CMOS inverter forming a flip-flop circuit together with said first CMOS inverter; a first transfer transistor provided between a first bit line and said first node, said first transfer transistor having a first gate electrode connected to a word line, said first transfer transistor being activated by a selection signal on said word line; and a second transfer transistor provided between a second bit line and said second node, said second transfer transistor having a second gate electrode connected to said word line, said second transfer transistor being activated by the selection signal on said word line, said first transfer transistor and said second transfer transistor being formed respectively in first and second device regions defined on a semiconductor substrate by a device isolation region of a STI structure so as to extend in parallel with each other, said first transfer transistor contacting with said first bit line at a first bit contact region on said first device region, said second transfer transistor contacting with said second bit line at a second bit contact region on said second device region, wherein said first and second device regions have respective first and second parts extending parallel with each other, said first transfer transistor being formed on said first part of said first device region, said second transfer transistor being formed on said second part of said second device region, said first part having an increased width over a remaining part of said first device region, such that that said first transfer transistor has an increased width, said second part having an increased width over a remaining part of said second device region, such that said second transfer transistor has an increased width.