Patent ID: 7627842

Claim:
A computer implemented method for verifying a circuit design, the circuit design having a portion corresponds to an encoded carry-save signal, comprising: decoding by a decoder the encoded carry-save signal to produce a decoded carry-save signal; determining a correspondence between the decoded carry-save signal of the circuit design and a second signal of a second circuit design; comparing by a processor the decoded carry-save signal to the second signal to perform verification upon the circuit design, in which decoding logic and encoding logic are inserted into one or more paths of the carry-save signal, in which the decoding logic and the encoding logic are explicitly inserted by an actual modification to a circuit representation of the circuit design or are implicitly inserted without actual modification to the circuit representation of the circuit design but causing realization of the encoding and the decoding logics; and storing the decoded carry-save signal in a volatile or non-volatile computer readable medium or displaying the decoded carry-save signal on a display device.