Patent ID: 8407515

Claim:
A logically partitioned computer system comprising: a plurality of processors; a memory coupled to the plurality of processors having a plurality of logical partitions designated by a partition manager; a first logical partition with an operating system; a memory block with a mirrored memory partner block having the same data in the first logical partition where the memory block and the mirrored memory partner block are allocated on physical memory chips; a memory error detection mechanism that monitors the occurrence of correctable and uncorrectable memory errors in the physical memory chips; when the memory error detection mechanism determines a number of correctable memory errors above a predetermined threshold occur in the first logical partition when accessing one of the physical memory chips that contains a memory block, a memory relocation mechanism in a hypervisor relocates transparently to the operating system data from the memory block to a first newly allocated memory block, wherein the memory relocation mechanism transparently relocates dedicated memory by placing the processors of the first logical partition with the correctable memory errors above the predetermined threshold in a virtual partition memory mode, disabling arbitration into the memory block for direct memory access, copying the memory block page to a new memory block, and updating a page table; and when the memory error detection mechanism determines an uncorrectable error occurs in the memory block and when there is a mirrored memory partner block with no uncorrectable errors, the memory relocation mechanism uses the mirrored memory partner block as a data source for data for the memory block with the uncorrectable error and then relocates the data to a second newly allocated memory block to replace the memory block with the uncorrectable error.