Patent ID: 7868439

Claim:
A chip package, comprising: a substrate comprising a plurality of first pads, a plurality of second pads, a plurality of third pads and at least one first interconnecting structure, wherein the first pads are located on a first surface of the substrate, and the second pads and the third pads are located on a second surface of the substrate, and projections of the second pads on the second surface and projections of the third pads on the second surface does not overlap, and the first interconnecting structure is deposited within the substrate; at least one first chip disposed on the first surface of the substrate, wherein projections of the first pads on the first surface and a projection of the first chip on the first surface does not overlap, the first interconnecting structure is directly coupled with the first chip, one of the first pads and one of the second pads, and one of the first pad and the second pad acts as an input/output terminal of the first chip while the other one as a test terminal of the first chip; and a second package coupled to the substrate through the third pads.