Patent ID: 7822911

Claim:
An integrated circuit memory device, comprising: at least one bank of memory cells; an addressing circuit coupled between external terminals and the at least one bank of memory cells; a data path coupled between external terminals and the at least one bank of memory cells; a command decoder coupled to external terminals, the command decoder being operable to generate control signals to control an operation of the memory device; and a cache system integrated with the at least one bank of memory cells, addressing circuit data path and command decoder and coupled to the at least one bank of memory cells, the cache system being configured to cache data stored in the at the least one bank of memory cells regardless of where cached data are stored in the at least one bank of memory cells, the integrated circuit memory device being configured to allow data to be transparently accessed through the command decoder, addressing circuit, and data path regardless of whether the data are stored in the at least one bank of memory cells or the cache system.