Patent ID: 7124159

Claim:
A decimation circuit for decimating waveform data on a data acquisition system, comprising: a sample counting circuit having N registers connected in series with one of N−1 adders positioned between each register pair, where N is the number of data lines on a data bus; the sample counting circuit determining N outputs on the basis of a decimation factor value and a decimation phase value, each output indicating a position of a data sample within the waveform data to remain after decimation; the first of the registers being set to the decimation phase value as its indicated position, each adder adding the decimation factor value to the output of the preceding register to produce the output for the next register as its indicated position; and a multiplexing circuit having N parallel multiplexers, each being connected in series to one of N corresponding parallel output registers; each multiplexer having N parallel inputs connected with the data lines of said data bus and being controlled in accordance with a predetermined one of the outputs from said sample counting circuit to select data samples from one of the data lines of the data bus as indicated by said predetermined one of the outputs; each of said N output registers being enabled by an enable bit to receive data samples selected by the corresponding multiplexer.