Patent ID: 6839295

Claim:
A semiconductor memory device, comprising: a precharging unit for charging a plurality of bit lines, a plurality of reference lines, a plurality of discharge lines and an enable line; a dummy word line unit for discharging the discharge lines and the enable line to a first logic state; a bit cell array unit for storing bit cell data and for reading out the stored bit cell data; a reference cell array unit for outputting a precharge voltage to charge a selected reference line; a bit cell replica array unit for outputting the state of a signal transferred to the enable line; an enable signal generation unit for checking the state of the enable signal and for outputting an enable signal; and a sense amplifying unit for sensing the read-out bit cell data when the enable signal is activated, for comparing the read-out bit cell data with the reference signal, and for outputting a logic state corresponding to the read-out bit cell data.