Patent ID: 8158483

Claim:
A manufacture method for a semiconductor device comprising the steps of: (a) forming first and second active regions of a first conductivity type and third and fourth active regions of a second conductivity type in a semiconductor device; (b) forming a gate insulating film having a first thickness on said first and third active regions; (c) forming a gate insulating film having a second thickness on said second and fourth active regions, the second thickness being significantly thinner than the first thickness; (d) forming first to fourth gate electrodes on the gate insulating films in said first to fourth active regions and leaving said gate insulating films; (e) performing a first ion implantation of impurities of the first conductivity type into said first and fourth active regions under conditions that the impurities penetrate through the gate insulating film having the second thickness and do not penetrate through the gate insulating film having the first thickness; (f) performing a second ion implantation of impurities of the second conductivity type into said first and fourth active regions under conditions that the impurities penetrate through the gate insulating films; (g) performing a third ion implantation of impurities of the second conductivity type into said second and third active regions under conditions that the impurities penetrate through the gate insulating film having the second thickness and do not penetrate through the gate insulating film having the first thickness; (h) performing a fourth ion implantation of impurities of the first conductivity type into said second and third active regions under a condition that the impurities penetrate through the gate insulating films; (i) depositing an insulating layer on a whole surface of said semiconductor substrate, and anisotropically etching said insulating layer to form side wall spacers on side walls of the gate electrodes and remove exposed gate insulating films; (j) performing a fifth ion implantation of impurities of the second conductivity type into said first and second active regions, by using said side wall spacers as a mask; and (k) performing a sixth ion implantation of impurities of the first conductivity type into said third and fourth active regions, by using said side wall spacers as a mask.