Patent ID: 8273601

Claim:
A method of fabricating a multi-chip package structure, comprising: providing a first wafer having an active surface and a back surface opposite to the active surface, a plurality of bonding pads being disposed on the active surface; patterning a first insulating layer disposed on the active surface, such that a plurality of openings exposing the bonding pads is formed on the first insulating layer; forming a plurality of cavities on a predetermined cutting line of the first wafer by partly removing the first insulating layer and the first wafer; forming a first circuit layer on the first insulating layer, wherein the first circuit layer has a plurality of first pads; providing a second wafer and forming a plurality of conductive bumps on the second wafer; electrically connecting the conductive bumps of the second wafer to the first circuit layer; forming a second circuit layer having a plurality of second pads on the back surface of the first wafer; and cutting the first wafer and the second wafer along the predetermined cutting line to form a plurality of separated multi-chip package structures.