Patent ID: 7289542

Claim:
A method for operating a PLL frequency synthesis circuit for a TDMA/FDMA data transmission device, which comprises the steps of: operating the PLL frequency synthesis circuit in an active state for transmitting data during a first period using a first output frequency synthesized by the PLL frequency synthesis circuit; carrying out no data transmission activity by the TDMA/FDMA data transmission device during an intermediate period following the first period; reprogramming the PLL frequency synthesis circuit from the first output frequency to a stabilization basic frequency, located in a suitable manner in a usable frequency band, after the first period has elapsed from which a stabilization process to a second output frequency being carried out; and operating the PLL frequency synthesis circuit to transmit further data during a second period using the second output frequency, not being equivalent to the first output frequency, following the intermediate period, the PLL frequency synthesis circuit synthesizing the second output frequency.