Patent ID: 8405129

Claim:
A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a plurality of bit line structures; a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding one of said bit line structures under control of a corresponding one of said word line structures, each of said cells in turn comprising a logical storage element having at least a first pull-down device, at least a first access device, and at least a first pull-up device; wherein: said at least first is pull-down device and said at least first access device are formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures; and said at least first pull-up device is formed with a relatively thin buried oxide layer.