Patent ID: 7739567

Claim:
An integrated circuit, comprising: functional logic relating to a primary function of the integrated circuit; parallel-scan chain logic for integrated circuit structural testing; boundary scan logic for boundary scan testing; and serializer/de-serializer (SerDes) logic, the SerDes logic comprising serializer logic and de-serializer logic, the serializer logic comprising multiplexing logic responsive to control signals, and the de-serializer logic comprising selection logic responsive to the control signals, wherein: the multiplexing logic couples a first multiplexing logic input to the functional logic to receive functional data in response to a first control signal state; the multiplexing logic couples a second multiplexing logic input to the boundary scan logic to receive boundary scan data in response to a second control signal state; the multiplexing logic couples a third multiplexing logic input to the parallel-scan chain logic to receive parallel-scan data in response to a third control signal state; the selection logic couples a first selection logic output to the functional logic to provide functional data in response to the first control signal state; the selection logic couples a second selection logic output to the boundary scan logic to provide boundary scan data in response to the second control signal state; and the selection logic couples a third selection logic output to the parallel-scan logic to provide parallel-scan data in response to the third control signal state; at least one serial data output pad element coupled to an output of the multiplexing logic; and at least one serial data input pad element coupled to an input of the selection logic.