Patent ID: 8069025

Claim:
A logic simulation apparatus configured to check an operation of a logical circuit which comprises a plurality of input nodes including a clock input node configured to receive a clock signal, and a plurality of internal nodes; a timing network configured to transmit a logical value change of an input signal applied to the input node other than the clock input node in correspondence with an elapse of time or in correspondence with number of cycles of a logical value change of the clock signal; and a specific logical device configured to receive a timing network output signal that appears at an exit node of the timing network as one of the internal nodes, and to receive a logical value change corresponding to the clock signal or a logical value obtained after changing the corresponding clock signal, the logic simulation apparatus comprising: a simulation executor configured to execute a simulation of a multi-cycle path circuit operation of the logical circuit in synchronization with the clock signal, the simulation executor being configured to check if the timing network output signal given to the specific logical device violates a predetermined constraint information, the predetermined constraint information being represented by (a) a timing constraint regarding a demanded number of clock cycles, the timing constraint being satisfied when the demanded number of clock cycles, to be used to pass a signal level change transition through a signal path in the timing network, is equal to or less than a predetermined value, or the predetermined constraint information being represented by (b) a timing constraint regarding a demanded number of clock cycles, the timing constraint being satisfied when the demanded number of clock cycles, to be used to pass a signal level change transition through a signal path in the timing network, is equal to or larger than a predetermined value; and an information holder configured, at a specific point of the elapse of time or at a specific point of cycle-number regarding the logical value change of the clock signal, to hold as transition information the logical value and/or the logical value change at the input node and the internal nodes.