Patent ID: 8659075

Claim:
A memory device, comprising: an array of pillars arranged in a plurality of rows and a plurality of columns, wherein individual pillars include a semiconductor post having a proximal portion, a distal portion, and an intermediate section therebetween, wherein the plurality of rows are spaced apart by a row spacing, and wherein the plurality of columns are spaced apart by a column spacing greater than the row spacing; a plurality of gate lines, wherein individual gate lines surround the intermediate sections of semiconductor posts along a corresponding column of pillars, and wherein the gate lines span across the row spacing but do not span across the column spacing; and self-aligned openings over the distal portions of corresponding semiconductor posts, wherein the self-aligned openings include drain contacts electrically connected to corresponding drains at the distal portions of the semiconductor posts, wherein individual gate lines are formed from a metal having a thickness, wherein the row spacing is less than twice the thickness of the metal, and wherein the column spacing is greater than twice the thickness of the metal.