Patent ID: 7332936

Claim:
A semiconductor circuit comprising: a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit, comprising: a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted; a first terminal of the first n-channel transistor to which a timing control signal is inputted; a first terminal of the first p-channel transistor to which an inverted timing control signal is inputted; a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor electrically connected to the second terminal of the first n-channel transistor; wherein the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to an input terminal of the inverter circuit; a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the inverter circuit is inputted; a first terminal of the second p-channel transistor which the timing control signal is inputted; a first terminal of the second n-channel transistor which the inverted timing control signal is inputted; a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor electrically connected to the second terminal of the second n-channel transistor; and wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the inverter circuit.