Patent ID: 7225092

Claim:
An apparatus for measuring duty cycle in a processor, comprising: a variable duty cycle clock means for generating a clocking signal and an inverted clock signal; a first frequency divider responsive to said clocking signal; wherein the first frequency divider comprises a plurality of latches coupled in serial, comprising at least a first latch and a last latch, each latch comprising an input and an output, wherein the input of each latch comprises only the output of the previous latch, and wherein the input of the first latch comprises only an inverted output of the last latch; a second frequency divider responsive to said inverted clocking signal; a plurality of AND gates each having a different pair of inputs, with each input of each of said pair corresponding to a different signal from said first frequency divider and said second frequency divider; a first multiport switch interconnected to said first frequency divider; and a second multiport switch interconnected to said plurality of AND gates.