Patent ID: 7788423

Claim:
An apparatus for invalidating cache lines during a direct memory access (DMA) Write operation by a peripheral device in a multiprocessor system, said apparatus comprising: a peripheral device for issuing a multi-cache line DMA request, wherein said peripheral device is associated with a multiprocessor system having a plurality of processors; a plurality of cache memories, each associated with one of said processors, for snooping said multi-cache line DMA request; means for determining whether or not any of said cache memories includes a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed; means for, in response to a determination that one of said cache memories includes a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed, consecutively invalidating a plurality of cache lines within said one of said cache memories, and means for, in response to a determination that none of said cache memories includes a copy of data stored in a plurality of system memory locations to which said multi-cache line DMA request are directed, generating a separate coherence response by each portion of each of said cache memories.