Patent ID: 6914849

Claim:
A method for a memory array, wherein the memory array has a storage unit with a number of sections and a number of decoders coupled by word lines to respective ones of the sections, and wherein each decoder is coupled to an associated local clock buffer, the method comprising the steps of: a) receiving, by the local clock buffers, a clock signal and an address signal including M most-significant bits of the N-bit address signal; and b) generating respective timing signals by the local clock buffers, wherein generating the timing signal by such a local clock buffer includes the steps of: evaluating a state of the M bits of the address signal; and selecting between holding such a timing signal in a deasserted state and enabling the timing signal to follow the clock signal responsive to the state of the M bits of the address signal; c) receiving the timing signals from the local clock buffers by the respective decoders; d) holding a precharging state by a number of the decoders responsive to the decoders's local clock buffers holding their respective timing signals in a deasserted state; and e) evaluating the N-bit address signal and responsively asserting a signal on a selected one of the word lines by one of the decoders responsive to the decoder's local clock buffer timing signal following the clock signal.