Patent ID: 7858482

Claim:
A method of forming a semiconductor device comprising: providing a semiconductor substrate; forming an n-channel transistor structure overlying and within the semiconductor substrate, wherein the n-channel transistor structure includes a gate dielectric overlying a channel region within the semiconductor substrate, a gate stack overlying the gate dielectric, a sidewall spacer adjacent a sidewall of the gate stack and overlying a portion of the semiconductor substrate proximate the channel region, and source and drain implant regions within the semiconductor substrate proximate the channel region; forming a p-channel structure overlying and within the semiconductor substrate, wherein the p-channel transistor structure includes a gate dielectric overlying a channel region within the semiconductor substrate, a gate stack overlying the gate dielectric, a sidewall spacer adjacent a sidewall of the gate stack of the p-channel transistor structure and overlying a portion of the semiconductor substrate proximate the channel region of the p-channel transistor structure, and source and drain implant regions within the semiconductor substrate proximate the channel region of the p-channel transistor structure; forming a stress memorization technique (SMT) layer over the n-channel transistor structure and the p channel structure; removing the SMT layer from over the p-channel transistor structure and leaving the SMT layer over the n-channel transistor structure; transferring a stress from the SMT layer into the channel of the n-channel transistor structure, wherein transferring the stress excludes any appreciable gate dielectric degradation; removing the SMT layer overlying the n-channel transistor structure subsequent to the stress transfer; and activating dopants of the source and drain implant regions of the n-channel transistor structure after removing the SMT layer overlying the n-channel transistor structure.