Patent ID: 6842436

Claim:
A multiport RAM memory device, comprising: a RAM memory unit having an address/control, a read port and a write port for a first time division multiplex system; an address serial/parallel converter for converting a multiplicity of serial address signals of a second time division multiplex system into a multiplicity of parallel address signals of the first time division multiplex system; a selection serial/parallel converter for converting a multiplicity of serial selection signals of the second time division multiplex system into a multiplicity of parallel selection signals of the first time division multiplex system; a data input serial/parallel converter for converting at least one serial data input signal of the second time division multiplex system into at least one parallel data input signal of the first time division multiplex system; a first time slot assignment unit for selectively feeding the parallel address signals, lying in predetermined time slots of the first time division multiplex system, to the address/control port of the RAM memory unit; a second time slot assignment unit for assigning parallel data output signals, read out at the read port of the RAM memory unit, into predetermined time slots of the first time division multiplex system; a parallel/serial converter for converting the multiplicity of parallel data output signals of the first time division multiplex system into a multiplicity of serial data output signals of the second time division multiplex system; and a control unit for controlling the first and second time slot assignment units in a manner dependent on the multiplicity of parallel selection signals, wherein the control unit drives the second time slot assignment unit so as to compensate for a temporal delay during read-out of the parallel data output signals from the RAM memory unit.