Patent ID: 7485917

Claim:
A method of fabricating a split gate flash memory cell, comprising: providing a semiconductor substrate; forming a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a cap layer on the semiconductor substrate in sequence; performing a first etching process to remove a portion of the cap layer, a portion of the second conductive layer and a portion of the second insulating layer to expose a portion of the surface of the first conductive layer, wherein the etched cap layer, the etched second conductive layer and the etched second insulating layer have coplanar sidewalls; forming a first sidewall spacer and a second sidewall spacer on the sidewalls of the etched cap layer, the etched second conductive layer and the etched second insulating layer, respectively; performing a second etching, with the first sidewall spacer and the second sidewall spacer as a mask, to remove a portion of the first conductive layer and a portion of the first insulating layer, and thus, a portion of a surface of the semiconductor substrate is exposed, wherein the etched first conductive layer and the etched first insulating layer have coplanar sidewalls; striping the first sidewall spacer and the second sidewall spacer; forming a third insulating layer on the semiconductor substrate and the sidewalls of the etched first conductive layer and the etched first insulating layer; and forming a third conductive layer on the third insulating layer.