Patent ID: 6973594

Claim:
A system, comprising: a bus including a power line; a bus bridge device including an internal logic unit; and a power regulator to deliver power to the power line, the power regulator further to assert a fault signal to the bus bridge device if a power fault is detected on the bus, the bus bridge device to disconnect the internal logic unit from the bus in response to an assertion of the fault signal to prevent the internal logic unit from being corrupted with invalid data from the bus, wherein the bus is a secondary PCI bus, wherein the bus bridge device is a PCI/PCI bridge bridging the secondary PCI bus to a primary PCI bus coupled to a processor via a system logic device, and wherein in response to the fault signal, the PCI/PCI bridge is configured to assert an error signal to the system logic device regarding a fault condition associated with the fault signal, the system logic device is configured to generate an interrupt to the processor, and in response to the interrupt, the processor is configured to invoke system software to perform a predetermined operation, including at least one of scheduling a system shutdown and alerting a system administrator regarding the fault condition.