Patent ID: 7967184

Claim:
A semiconductor package, comprising: a substrate, including: a dielectric core, and first and second rows of flat, planar metal contacts formed into a conductance pattern on a surface of the dielectric core, the first and second rows of flat, planar metal contacts affixed to, and residing in a plane parallel to, the dielectric core, the first and second rows of flat, planar metal contacts together defining a bare space on the dielectric core in between the first and second rows; a semiconductor die supported on the core within the bare space and having a plurality of electrical contacts on a surface of the semiconductor die adjacent the core, the plurality of electrical contacts juxtaposed to the first and second rows of flat, planar metal contacts of the substrate; and solder paste, deposited directly on the dielectric core in the space between each juxtaposed pair of flat, planar metal contact on the substrate and electrical contact on the semiconductor die, for electrically coupling each juxtaposed pair of flat, planar metal contact on the substrate and electrical contact on the semiconductor die in a solder reflow process.