Patent ID: 6871307

Claim:
A test system comprising: a test wafer having a plurality of dies to be tested and a first set of pads exposed in a first pattern at a first surface of the test wafer, the first set of pads providing electrical connections to the dies; a probe wafer having an auxiliary test circuit fabricated thereon, a second set of pads exposed in a second pattern at a first surface of the probe wafer, a third set of pads exposed in a third pattern at a second surface of the probe wafer, and an interconnect structure for connecting the auxiliary test circuit, the second set of pads and the third set of pads; a prober configured to align the first set of pads of the test wafer with the second set of pads of the probe wafer, place the first set of pads of the test wafer into contact with the second set of pads of the probe wafer.