Patent ID: 7872289

Claim:
A semiconductor device comprising: element regions each of which is surrounded by an element isolation region; MOS transistors each of which is formed on a first one of the element regions, each of the MOS transistors having a source, a drain, and a gate; capacitor elements each of which is formed on a second one of the element regions; a voltage generating circuit in which current paths of the MOS transistors are series-connected and each of the capacitor elements is connected to either of the source and the drain of each of the MOS transistors, the voltage generating circuit outputting a voltage from a first one of the MOS transistors in a final stage of the series connection, the voltage generating circuit inputting a voltage from a second one of the MOS transistors in the initial stage in the series connection; a contact plug which is formed on at least either of the source and the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements, a distance between the gate and the contact plug both for the first one of the MOS transistors being larger than that for the second one of the MOS transistors; and a memory cell which is capable of holding data, the voltage output by the voltage generating circuit is applied to the memory cell.