Patent ID: 8310431

Claim:
An image display apparatus, comprising: a Phase Locked Loop (PLL) unit for multiplying a horizontal synchronizing signal and generating a regenerative dot clock for displaying an inputted video signal; a synchronization detecting unit for detecting a total number of vertical lines which is a total number of lines per frame of the video signal from the horizontal synchronizing signal and from a vertical synchronizing signal; a video detecting unit for measuring a horizontal display width which is a number of horizontal video signal data as a display subject included in the video signal by using the regenerative dot clock generated by the PLL unit; a frame memory for holding the video signals in units of frames; and a Central Processing Unit (CPU) for estimating a format of the inputted video signal based on the total number of vertical lines, provisionally setting a frequency dividing ratio of the PLL unit at a predetermined value corresponding to the estimated format, calculating the frequency dividing ratio so that a measured value of the horizontal display width measured by the video detecting unit matches a capture width which is the horizontal display width capturable by the frame memory, converting the calculated frequency dividing ratio to a multiple of 4, performing a phase adjustment of the regenerative dot clock against the video signal based on the converted frequency dividing ratio by using the regenerative dot clock generated by the PLL unit, recalculating the frequency dividing ratio so that the measured value of the horizontal display width measured by the video detecting unit matches the capture width by using the regenerative dot clock after finishing the phase adjustment, and resetting the calculated frequency dividing ratio to the PLL unit.