Patent ID: 8346100

Claim:
A received power monitoring (RPM) apparatus for use in an optical receiver for monitoring optical power received in the optical receiver, the apparatus comprising: an amplifier circuit configured to receive an electrical signal produced by an optical detector in response to light received by the optical detector, the amplifier circuit being configured to amplify the electrical signal and to output the amplified electrical signal; an adjustable resistor circuit configured to receive the amplified electrical signal at an input terminal of the adjustable resistor circuit and to produce an analog voltage signal, V MON , at an output terminal of the adjustable resistor circuit, the adjustable resistor circuit providing a resistance value that is adjustable between at least a first resistance value, R L1 , and a second resistance value, R L2 , wherein R L1 is greater than R L2 ; and a controller having an analog-to-digital converter (ADC), the ADC having an input port that receives the analog V MON signal and an output port that outputs a multi-bit digital value, V MON — DIG , the ADC having ADC circuitry that converts the analog V MON signal into the digital V MON — DIG value that is output from the output port of the ADC, wherein the controller is configured to perform a received power monitoring (RPM) algorithm that analyzes the digital V MON — DIG value output from the output port of the ADC to determine whether or not the digital V MON — DIG value indicates that the resistance value provided by the adjustable resistor circuit needs to be adjusted, wherein if the RPM algorithm determines that the digital V MON — DIG value indicates that the resistance value of the adjustable resistor circuit needs to be adjusted, the RPM algorithm causes the adjustable resistor circuit to be adjusted to provide one of the first resistance value R L1 and the second resistance value R L2 , wherein adjusting the resistance value of the adjustable resistor circuit between one of the first resistance value R L1 and the second resistance value R L2 results in an amplitude of the analog V MON signal being adjusted between a first analog V MON value and a second analog V MON value, respectively, wherein the first analog V MON value is greater than the second analog V MON value, and wherein the ADC circuitry of the ADC converts the first and second analog V MON values into first and second digital V MON — DIG values, respectively, the first digital V MON — DIG value being greater than the second digital V MON — DIG value, and wherein the controller further comprises scaling circuitry that multiplies the second digital V MON — DIG value by a scaling factor greater than one.