Patent ID: 8298947

Claim:
A method for assembling a semiconductor device comprising the steps of: providing a semiconductor chip having a plurality of gold studs; providing a tape having a first substrate surface and a second substrate surface; the first substrate surface having a plurality of first copper contact pads in locations matching the gold studs on the chip; each of the plurality of first copper pads covered by a first continuous and conformal first nickel layer having a first thickness, and a first gold layer covering the first nickel layer; the second substrate surface having a plurality of second copper contact pads; each of the plurality of second copper pads covered by a second continuous and conformal second nickel layer having the first thickness, and a second gold layer covering the second nickel layer; attaching the chip to the first substrate surface by the steps of: putting the tape to a frame; pressing the plurality of gold studs onto the gold covered plurality of first copper contact pads; applying ultrasonic energy to create gold-to-gold interdiffusion contact; and attaching reflow bodies to the second substrate surface by the steps of: attaching each of the plurality of second contact pads with a solder body; applying thermal energy to reflow the solder body, thereby creating an alloy layer including gold, copper-nickel-tin alloy and a dominant alloy portion comprising (Cu, Ni, Au)6Sn 5 intermetallic compound; and substantially consuming the entire thickness of the nickel layer on the second copper contact pads.