Patent ID: 8680907

Claim:
A delay circuit, comprising: a plurality of delay elements connected together in a series configuration, each of the plurality of delay elements being connected to at least another of the plurality of delay elements, and each of the delay elements having a prescribed delay and an output associated therewith; and a controller connected to each of the respective outputs of the plurality of delay elements, the controller being configured such that signal paths between each of the respective outputs of the plurality of delay elements and an output of the controller have corresponding delays associated therewith that are substantially equal to one another, the controller comprising a plurality of tri-statable switching elements, each of the signal paths having a given one of the tri-statable switching elements associated therewith, each of the tri-statable switching elements having an input connected to a corresponding one of the outputs of the delay elements and an output, each of the respective outputs of the plurality of delay elements being connected to a corresponding one of the inputs of the tri-statable switching elements, wherein the respective outputs of each of the tri-statable switching elements are connected together at a single node, wherein each of the plurality of delay elements comprises a differential delay element and each of the respective outputs of the delay elements comprises first and second complementary outputs from each differential delay element, the plurality of delay elements forming a differential delay chain, and wherein each differential delay element comprises two complementary inputs.