Patent ID: 8030649

Claim:
A method for testing an integrated circuit, the integrated circuit including multiple cores, each core being a processor core, each core including a plurality of registers configured to form at least one scan chain in each core, the method comprising: coupling inputs of the scan chains together such that the inputs of the scan chains are electrically connected in a parallel circuit; coupling outputs of the scan chains to a verification unit; performing, at the integrated circuit, at least one computational operation on data provided to the integrated circuit via the scan chains; providing a reference signal to the integrated circuit, the reference signal originating outside the integrated circuit and configured to indicate an expected output; comparing, at the integrated circuit, the outputs of the scan chains against the reference signal; comparing the outputs of the scan chains to each other to determine the validity of the outputs; determining of the validity of the outputs of the scan chains at the verification unit, wherein a valid output indicates a functional core and an invalid output indicates a non-functional core; indicating a malfunction of the integrated circuit if at least one of the outputs of the scan chains is determined not to be valid; using the outputs of the scan chains to determine the functionality of one or more individual cores in the integrated circuit; and recording, at the integrated circuit, an identity of one or more cores having outputs of the scan chains that are determined to be malfunctioning; wherein the outputs of the scan chains are not used for verification when, for a specific set of outputs, a possibility exists that the outputs will differ from each other on a correctly functioning integrated circuit due to intentional differences between the cores of the integrated circuit.