Patent ID: 8575007

Claim:
A method for designing a flip chip, the method comprising the steps of: providing the flip chip, wherein the flip chip comprises: a semiconductor substrate comprising one or more semiconductor materials; a device coupled to the semiconductor substrate; a first and second wiring level, separated by a dielectric layer, wherein at least one of the first and second wiring levels is electrically connected to the device, and wherein the first and second wiring levels are interconnected through the dielectric layer by a conductive via; a plurality of input/output (I/O) contact pads on a surface of the flip chip, wherein at least one of the plurality of I/O contact pads is electrically connected to one of the first and second wiring levels, and wherein the plurality of I/O contact pads are capable of receiving an electrical current to the flip chip and sending an electrical current from the flip chip; a plurality of controlled collapse chip connection (C4) bumps for connecting the plurality of I/O contact pads to off-chip conductive paths; and receiving a plurality of maximum electrical currents that may flow through the plurality of C4 bumps, wherein each maximum electrical current of the plurality of maximum electrical currents corresponds to one or more C4 bumps of the plurality of C4 bumps; determining a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility for one or more C4 bumps of the plurality of C4 bumps corresponding to a certain maximum electrical current of the plurality of maximum electrical currents, wherein the level of susceptibility is based on a ratio determined by dividing a failure rate for a C4 bump of the plurality of C4 bumps corresponding to the certain maximum electrical current by a sum of failure rates for a C4 bump of the plurality of C4 bumps corresponding to each maximum electrical current of the plurality of maximum electrical currents; in response to determining the level of susceptibility, plating a conductive structure with a high electrical current carrying capacity onto one or more I/O contact pads of the plurality of I/O contact pads, wherein the one or more I/O contact pads correspond to the one or more C4 bumps of the plurality of C4 bumps corresponding to the certain maximum electrical current; and adding a solder ball to a top portion of each plated conductive structure.