Patent ID: 7080333

Claim:
A method of verifying a logic synthesizer comprising: for each of a plurality of HDL models: generating a second synthesizer from a first synthesizer by modifying a circuitry of the first synthesizer to generate a circuitry of the second synthesizer, wherein respective modeled functions of the circuitry of the first synthesizer and corresponding circuitry of the second synthesizer are the same; generating a first netlist from an HDL model using the first synthesizer; simulating the first netlist using a plurality of test vectors to generate a first plurality of output vectors; generating a second netlist from the HDL model using the second synthesizer; simulating the second netlist using the plurality of test vectors to generate a second plurality of output vectors; comparing the first plurality of output vectors with the second plurality of output vectors; and determining if any mismatch between the first plurality of output vectors and the second plurality of output vectors is from corresponding circuitries of the first synthesizer and the second synthesizer, wherein the corresponding circuitries each provides a corresponding netlist having different output vectors.