Patent ID: 8839055

Claim:
An apparatus including a test sequence processor for coordinating issuances of test commands among multiple test equipment hardware modules, comprising: a hardware module monitor and command processor configured to receive one or more sets of test commands for a plurality of test equipment hardware modules, receive data indicative of availability of a portion of said plurality of test equipment hardware modules, separate portions of each of said one or more sets of test commands to provide respective subsets of test commands for corresponding ones of said plurality of test equipment hardware modules by parsing each of said one or more sets of test commands into ordered subsets of commands for respective intended ones of the plurality of test equipment hardware modules, and provide a test execution command following reception of data confirming availability of a portion of said plurality of test equipment hardware modules corresponding to one of said subsets of test commands; and a hardware module controller configured to communicate with said hardware module monitor and command processor, and store said respective subsets of test commands, and convey, following reception of said test execution command, said stored respective subsets of test commands.