Patent ID: 7160795

Claim:
A method of reducing parasitic capacitance in an integrated circuit having n, where n≧3, metal levels, comprising: forming a bond pad on M(n), the number n metal level, at least partially exposed at a top surface of the integrated circuit; forming a metal pad below and continuously underlying the bond pad on M(n−1), the number n−1 metal level; forming n−2 metal pads, one on each of n−2 lower metal levels, such that an area of at least a lowermost metal pad of the n−2 underlying metal pads is less than about 30% of an area of the bond pad and an area of the metal pad on M(n−1); forming an interlevel dielectric layer between each pair of adjacent metal levels; and forming a plurality of conductive contacts between the bond pad and the metal pad on the number n−1 metal level; and forming conductive contacts between the metal pad on the number n−1 metal level and the n−2 underlying metal pads.