Patent ID: 7353401

Claim:
A device for data protection by scrambling address lines in a processor core, the processor core executing instructions of the processor and accessing data through an address bus and a data bus, the device comprising: a redundancy area-setting unit, which sets addresses of a first data area and addresses of a redundancy area of the memory corresponding to the first data area; a redundancy area-mapping rule unit, which provides rule for converting addresses of the first data area into addresses of the redundancy area; an area check unit, which is connected to the redundancy area-setting unit and the address bus for comparing an address on the address bus with addresses of the redundancy area stored in the redundancy area-setting unit and generating a comparison result; an address-mapping unit, which is connected to the redundancy area-mapping rule unit and the address bus for converting the address of the address bus into an address of the redundancy area; and a multiplexer, which is controlled by the comparison result and a switch control signal in order to output the address of the redundancy area when the comparison result is matched and the switch control signal is a special logic or otherwise output the address of the address bus.