Patent ID: 7002983

Claim:
A device for data stream analyzing, comprising: a processor means, a program memory, and a multiplexable data stream delayline for receiving a data stream; said device for enabling parsing of said data stream in a way that is controlled by an interchangeable program; and a multiplexing means for connecting different parts of said data stream to said processor means, wherein the multiplexing means include a multiplexing control means for automatically keeping track of where specific data is located in the delayline and for enabling at least one program to start executing once the data is received in the delayline; wherein the multiplexing control means automatically keeps track of where specific data is located in the delayline by the use of a first and second position register that change in a predetermined way when a packet is forwarded in the delayline, and wherein values of the position registers are changed in the following way: when a packet arrives, the first register starts to increment for every byte; when the packet has come to its end, where the packets DV (data valid) signal becomes false again, the first register stops counting and the second register starts to increment.