Patent ID: 7719342

Claim:
An input latch circuit comprising: a setup time adjusting unit configured to selectively delay an inputted clock signal; and a latch unit configured to latch an input signal according to an output signal of the setup time adjusting unit, wherein the setup time adjusting unit selectively delays the clock signal according to whether a fuse of the setup time adjusting unit is cut or not, wherein the setup time adjusting unit passes the clock signal to the latch unit without a delay when the fuse is not cut, and delays the clock signal for a given period of time and outputs the clock signal to the latch unit and setup time becomes longer than a hold time when the fuse is cut, wherein the setup time adjusting unit includes: a setup fuse unit configured to activate a setup adjusting signal when the fuse is cut; and a setup adjusting unit configured to pass the clock signal to the latch unit without a delay when the setup adjusting signal is deactivated, and to delay the clock signal for a given period of time and output the delayed clock signal to the latch unit when the setup adjusting signal is activated.