Patent ID: 7633159

Claim:
A chip-scale package, comprising: a semiconductor device; a redistribution layer over an active surface of the semiconductor device; a peripheral dielectric coating covering at least a portion of an outer periphery of the semiconductor device, the peripheral dielectric coating including an edge adjacent to a junction between a periphery and a back side of the semiconductor device; a back side dielectric coating on at least a portion of the back side of the semiconductor device and including a peripheral edge abutting and forming a discernable boundary with a major surface of the peripheral dielectric coating; at least one peripheral conductive element carried by the peripheral dielectric coating, spaced apart from the back side dielectric coating by the peripheral dielectric coating, and including an end adjacent to a bottom edge of the peripheral dielectric coating; and at least one bottom contact carried partially by the back side dielectric coating, the edge of the peripheral dielectric coating and the end of the at least one peripheral conductive element abutting and forming a discernable boundary with a major surface of the at least one bottom contact.