Patent ID: 7169677

Claim:
A method for fabricating a spacer structure, the method comprising: a) forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, wherein the gate deposition-inhibiting layer and the covering deposition-inhibiting layer include at least one of a nitride layer and an oxynitride layer; b) patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks; and c) depositing an insulation layer selectively with respect to the deposition-inhibiting layers to form the spacer structure; d) carrying out an implantation in order to form connection doping regions in the semiconductor substrate; e) depositing a further insulation layer selectively with respect to the deposition-inhibiting layers in order to form a widened spacer structure; and f) carrying out a further implantation in order to form source/drain regions in the semiconductor substrate.