Patent ID: 8134229

Claim:
A layered chip package comprising: a main body having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; and a wiring disposed on the first side surface of the main body, wherein: the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes a semiconductor chip having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; the second, third and fourth side surfaces of the semiconductor chip are respectively located at the second, third and fourth side surfaces of the main body; the first side surface of the semiconductor chip faces toward the first side surface of the main body; each of the plurality of layer portions further includes: an insulating portion covering the first side surface of the semiconductor chip; and a plurality of electrodes connected to the semiconductor chip; the insulating portion has an end face located at the first side surface of the main body; each of the plurality of electrodes has an end face located at the first side surface of the main body and surrounded by the insulating portion; the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions; and an entirety of the first side surface of the main body on which the wiring is disposed is flat without the wiring.