Patent ID: 8441386

Claim:
A successive-approximations-register analog-to-digital converter (SAR ADC) comprising: a digital-to-analog converter (DAC) including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage of the SAR ADC; a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted by the SAR ADC when the common node is connected to a reference voltage; and a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to the reference voltage when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from the reference voltage during a first of a plurality of successive approximations.