Patent ID: 8564523

Claim:
A shift register including a plurality of stages, each of the plurality of stages receiving at least one of a plurality of clock signals and a plurality of control signals, each of the plurality of stages comprising: a pull-up section to output the received one of the plurality of clock signals to an output terminal; a pull-up driving section to turn on the pull-up section in response to a first one of the plurality of control signals and to turn off the pull-up section in response to a second one of the plurality of control signals; a pull-down section to output a first power voltage to the output terminal; a first pull-down driving section to output a third control signal based on turn-on and turn-off of the pull-up section; and a second pull-down driving section to turn on the pull-down section based on the third control signal received from the first pull-down driving section, wherein the first pull-down driving section includes a first transistor and a second transistor in series, wherein the second pull-down driving section includes a first transistor and a second transistor in series, wherein the first power voltage is applied to an end portion of the first transistor of the first pull-down driving section and an end portion of the first transistor of the second pull-down driving section, wherein a second power voltage is applied to an end portion of the second transistor of the first pull-down driving section and an end portion of the second transistor of the second pull-down driving section, and wherein a current electrode of the first transistor of the first pull-down driving section is connected to a control electrode of the first transistor of the second pull-down driving section to output the third control signal.