Patent ID: 7682914

Claim:
A method of forming a fully salicided Metal Oxide Semiconductor Field Effect Transistor (MOSFET), comprising: (a) providing a substrate having a channel bounded by doped source/drain (S/D) regions formed in an active area defined by isolation regions, and having a patterned gate stack with sides formed thereon that is bounded on said sides by a spacer comprised of an inner silicon oxide layer and an outer silicon nitride layer, said gate stack is comprised of sequentially forming a gate dielectric layer, gate electrode, silicon oxide hard mask and silicon nitride hard mask on the substrate above the channel; (b) forming an insulator block mask having sidewalls and a top surface on the substrate above the isolation regions that leaves a substantial portion of said S/D regions exposed; (c) forming a silicidation stop layer on the patterned gate stack, spacers, insulator block mask sidewalls and top surface, and on exposed S/D regions of the substrate; (d) forming a conductive layer on the silicidation stop layer that has a top surface at a higher level than any portion of the silicidation stop layer; (e) performing a planarization of said conductive layer that also removes said silicon nitride hard mask and silicidation stop layer above the insulator block mask, said planarization forms a raised S/D element comprised of said conductive layer on either side of the gate stack; (f) removing the silicon oxide hard mask to form a recessed gate electrode between the spacers; and (g) depositing a metal layer on the insulator block mask and over the active area and performing a silicidation to form fully silicided, raised S/D elements and a fully silicided gate electrode.