Patent ID: 8629489

Claim:
A nonvolatile memory device comprising: a string selection transistor having a channel region and source/drain regions; a plurality of memory cell transistors, each of the memory cell transistors having a channel and source/drain regions; a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors, the ground selection transistor having a channel region and source/drain regions; first impurity layers formed at boundaries of the channels and the source/drain regions of the memory cell transistors; and second impurity layers formed at boundaries between the channel and the drain region of the string selection transistor and between the channel and the source region of the ground selection transistor, wherein the first impurity layers are doped with p conductivity type impurities and wherein the second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.