Patent ID: 7319271

Claim:
A semiconductor device having a multi-layer wiring structure comprising a plurality of wiring layers, said wiring layers each comprising a buried wiring and a via formed by filling with a conductive material the inside of a wiring trench formed in a layer of insulation film and a contact hole provided at a bottom portion of said wiring trench, wherein said layer insulation films of said plurality of wiring layers are so configured that said layer insulation films are changed in a magnitude of mechanical strength alternately in a lamination direction of said wiring layers, wherein said multi-layer wiring structure has a configuration in which a first group of said wiring layers are comprised of a low-dielectric-constant film having an elastic modulus of less than 10 GPa and a second group of said wiring layers are comprised of an insulation film having an elastic modulus of not less than 10 GPa as a principal material and one member of each group is alternately laminated.