Patent ID: 7045409

Claim:
A method of manufacturing a semiconductor device having active regions connected together by an interconnect layer comprising: forming first and second device regions in a semiconductor substrate so that they are isolated from each other by an isolation region formed in the semiconductor substrate; forming at least one slit in the surface of the isolation region so that the first and second device regions communicate with each other through it, the slit having inner walls and a predetermined width; depositing a conductive layer, which includes a material that can form a nucleus for epitaxial growth, over the entire surface of the semiconductor substrate and then selectively removing the conductive layer so that it is left on the surface of a portion of each of the first and second device regions and on the inner walls of the slit; and covering a periphery of the conductive film left on the portion of each of the first and second device regions with a material serving as a block for epitaxial growth and then epitaxially growing a conductive film so as to form an interconnect layer having first and second portions respectively located on the first and second device regions and a third portion located on the isolation region to run along the slit, the first, second and third portions being made integral with one another, wherein a plurality of slits is formed in the isolation region in parallel with one another.