Patent ID: 6875697

Claim:
A process for forming trench isolation in a semiconductor memory device, said process comprising the steps of: forming a photoresist material over a silicon substrate; forming a photoresist pattern from said photoresist material to form a first, second and third level into said photoresist pattern, said first level defining active areas within said silicon substrate, said second level defining an intra-well width, an intra-well depth, a first inter-well width and a first inter-well depth, said third level defining a second inter-well width and a second inter-well depth; etching said silicon substrate by transferring said photoresist pattern thereto to form an inter-well trench having an overall combined width and depth comprising said first inter-well width, said first inter-well depth, said second inter-well width and said second inter-well depth, said step of etching simultaneously forming intra-well trenches on opposing sides of said inter-well trench; forming isolation material in said intra-well trenches and said inter-well trench; forming conductive wells having a common boundary but having opposite conductivity types within said define active areas, said isolation material interposed at said common boundary of said conductive wells.