Patent ID: 7554205

Claim:
A semiconductor package comprising: a semiconductor device having a plurality of electrode terminals provided and arranged on a top surface of said semiconductor device, and a sealing resin layer formed on the top surface of said semiconductor device such that said electrode terminals are completely covered with said sealing resin layer; and a substrate having a plurality of electrode terminals provided and arranged on a top surface of said substrate, the arrangement of the electrode terminals of said substrate having a mirror image relationship with respect to the arrangement of the electrode terminals of said semiconductor device, wherein said semiconductor device is mounted on said substrate such that the electrode terminals of said substrate penetrate into said sealing resin layer, and are directly connected to the respective electrode terminals of said semiconductor device, wherein said semiconductor device further includes a protective layer formed on the top surface of said semiconductor device except for the electrode terminals of said semiconductor device, with said protective layer being completely covered with said sealing resin layer, a top surface of the electrode terminals of said semiconductor device being lower than a top surface of said protective layer.