Patent ID: 7401307

Claim:
A method of improving a probability of an integrated circuit (IC) design meeting timing requirements, the method comprising the steps of: a) determining a reference slack using a reference run, and determining a sensitivity of slack to a variation in at least one parameter for each of a plurality of timing endpoints of the design, including: determining a first slack at each timing endpoint for a reference parameter value for each parameter, wherein the reference parameter value is substantially equivalent to one of: a first extreme value of a value range of the parameter, and a nominal value plus a multiple of a standard deviation of the parameter; determining a second slack at each timing endpoint for a different parameter value than the reference parameter value for each parameter; and calculating the sensitivity of the slack to the variation in the at least one parameter, including dividing a difference between the first slack and the second slack by a difference between the reference parameter value and the different parameter value; b) calculating a failure coefficient from the reference slack and the sensitivity of slack for each of the timing endpoints; c) determining whether each timing endpoint fails a threshold test; d) prioritizing any timing endpoints that fail the threshold test according to respective failure coefficients; and e) modifying the design to improve a slack of at least one of the timing endpoints.