Patent ID: 8255748

Claim:
A device comprising: a data input to receive a data signal; a clock input to receive a clock signal to latch information based on the data signal; a first signal path including the data input and a first latch, the first signal path having a first delay between the data input and a first data node for a given transition at the data input; and a second signal path including the data input and a second latch, the second signal path including a first data node at a same location relative to the second latch as the first data node of the first signal path is located relative to the first latch, the second signal path having a second delay between the data input and the first node of the second signal path for the given transition, the second delay being substantially different that the first delay; wherein the first signal path further comprises a first pass gate comprising a first current electrode coupled to receive information from the data input, and a second current electrode coupled to provide the information to the first latch, the first pass gate having a third delay between the first current electrode and the second current electrode for the given signal; and wherein the second signal path further comprises a second pass gate comprising a first current electrode coupled to receive information from the data input, and a second current electrode coupled to provide information to the second latch, the second pass gate having a fourth delay between the first current electrode and the second current electrode for the given signal, the difference between the first delay and the second delay is substantially the same as the difference between the third delay and the fourth delay.