Patent ID: 8201127

Claim:
A method of optimally placing load components within an integrated circuit to reduce power consumption within the integrated circuit, the method comprising: selecting an initial placement for a plurality of load components within the integrated circuit, the integrated circuit including a plurality of vertical spines configured to route clock signals to the plurality of load components in the initial placement; selecting, for each of one or more of the clock signals, one or more of the vertical spines used to route the clock signal as corresponding anchor spines; and for each load component of the plurality of load components initially placed, evaluating, using a processor, a power cost for the initial placement; determining, in an alternative placement, a distance from the load component to the anchor spine corresponding to the clock signal received by the load component; evaluating a power cost for the alternative placement as a function of the determined distance; and in response to determining that the power cost of the initial placement is greater than the power cost of the alternative placement, moving the load component to the alternative placement.