Patent ID: 7897428

Claim:
A method of fabricating a three-dimensional integrated circuit, comprising the steps of: forming a bottom device layer by forming a digital CMOS circuitry layer adjacent to a first substrate and depositing a first bonding oxide layer over a side of the digital CMOS circuitry layer opposite the first substrate; forming a top device layer by forming an analog CMOS and photonics circuitry layer in a SOI layer adjacent to a second substrate, the SOI layer having a BOX with a thickness of greater than or equal to about one micrometer and depositing a second bonding oxide layer over a side of the analog CMOS and photonics circuitry layer opposite the second substrate; forming an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer; and removing the second substrate from the top device layer so as to expose the BOX.