Patent ID: 8244791

Claim:
A carry lookahead circuit for a fast carry adder comprising: a carry-in signal node; first, second, and third carry-input signal nodes; first, second, and third propagate signal nodes; first, second, and third local carry-out signal nodes; a carry-out signal node; a first buffer having an input and an output, the input coupled to the carry-in signal node and the output coupled to the first local-carry out signal node; a first multiplexer having a first data input coupled to the first carry-input signal node, a second data input coupled to the output of the first buffer, a control input coupled to the first propagate signal node, and an output coupled to the second local carry-out signal node; a second multiplexer having a first data input coupled to the second carry-input signal node, a second data input coupled to the first carry-input signal node, a control input coupled to the second propagate signal node, and an output; a first AND gate having a first input coupled to the first propagate signal node, a second input coupled to the second propagate signal node, and an output; a third multiplexer having a first data input coupled to the output of the second multiplexer, a second data input coupled to the carry-in signal node through the first buffer, a control input coupled to the output of the first AND gate, and an output coupled to the third local carry-out signal node; a fourth multiplexer having a first data input coupled to the third carry-input signal node, a second data input coupled to the output of the second multiplexer, a control input coupled to the third propagate signal node, and an output; a second AND gate having a first input coupled to the first propagate input node, a second input coupled to the second propagate input node, a third input coupled to the third propagate input node, and an output; a fifth multiplexer having a first data input coupled to the output of the fourth multiplexer, a second data input coupled to the carry-in signal node, a control input coupled to the output of the AND gate, and an output coupled to the carry-out signal node.