Patent ID: 8173492

Claim:
A method of manufacturing a thin film transistor (TFT) substrate, the method comprising: forming a gate wire on an insulating substrate, the gate wire comprising a gate line extending in a first direction and a gate electrode connected to the gate line; forming a data wire on the insulating substrate, the data wire insulated from the gate wire and comprising a data line extending in a second direction to intersect the gate line having a pixel disposed at the intersection, a source electrode connected to the data line, and a drain electrode separated from the source electrode; and forming a pixel electrode connected to the drain electrode at each pixel, wherein forming the gate wire or the data wire includes forming a barrier layer on a lower structure, forming a copper conductive layer comprising copper or copper alloy on the barrier layer, forming an intermediate layer comprising copper nitride on the copper conductive layer, forming a capping layer comprising Mo, MoN, MoW, MoTi, MoNb, MoZr, IZO, ITO, amorphous ITO, or a compound thereof on the intermediate layer, etching the capping layer, the intermediate layer, and the copper conductive layer to expose the barrier layer, and etching the barrier layer, wherein an upper surface of the intermediate layer of the drain electrode is fully covered by the capping layer.