Patent ID: 7446578

Claim:
A Spread Spectrum Clock Generator (SSCG) comprising: a Phase/Frequency Detector (PFD) comprising: a first input end for receiving an objective clock signal; a second input end for receiving a feedback clock signal; and an output end for selectively outputting a first control signal or a second control signal; a voltage controller coupled to the output end of the PFD for outputting a corresponding voltage according to the first control signal and the second control signal; a Voltage Control Oscillator (VCO) coupled to the output end of the voltage controller for outputting a plurality of clock signals; wherein the plurality of the clock signals have a same frequency according to the voltage output from the voltage controller; wherein phases of the plurality of the clock signals are different to each other; a multiplexer comprising: a plurality of input ends, each input end receiving a corresponding clock signal from the plurality of the clock signals; a control end for receiving a third control signal; and an output end coupled to the second input end of the PFD; wherein the multiplexer couples one of the input ends of the multiplexer to the output end of the multiplexer for generating a combination clock signal according to the third control signal; a pattern generator comprising: a first input end for receiving a second reference clock signal; a second input end for receiving the combination clock signal; and an output end coupled to the control end of the multiplexer for outputting the third control signal; and a counter coupled to the output end of the multiplexer for counting the number of cycles of the combination clock signal; wherein the pattern generator controls one of the plurality of the input ends of the multiplexer to couple to the output end of the multiplexer according to the second reference clock signal, the combination clock signal, and the number of the counter.