Patent ID: 8531890

Claim:
A nonvolatile semiconductor memory device comprising: a memory string having a plurality of memory cells; and a driving unit connected to the memory cells, each memory cell including: a semiconductor layer having a source region, a drain region and a channel provided between the source region and the drain region; a first insulating film provided on the channel; a charge retention layer provided on the first insulating film; and a gate electrode provided on the charge retention layer, in sequentially reading data stored in the memory cells by sequentially applying a first signal to each memory cell, a second signal being applied to a second cell when applying the first signal to a first cell, the first cell being one of the memory cells, the second cell being the memory cell of the memory cells except the first cell, prior to application of a fifth signal and a sixth signal, the driving unit being configured to apply a seventh signal to the gate electrode of a third cell, the fifth signal programming data in the third cell, the sixth signal verify-reading the programmed data, the third cell being at least one of the memory cells in the memory string, the seventh signal having a seventh signal voltage and a seventh signal time duration, an absolute value of the seventh signal voltage being smaller than an absolute value of a voltage of the fifth signal, the seventh signal time duration being equal to or more than a time duration during which the fifth signal and the sixth signal are applied to the third cell.