Patent ID: 6873830

Claim:
A bias circuit for supplying a bias voltage to a gate of a first FET, comprising: a monitoring circuit having a second FET and a resistance connected to a drain of the second FET for monitoring a drain current of said first FET; a differential circuit including a third FET having a gate supplied with a reference voltage, a fourth FET having a gate connected to the drain of said second FET, sources of the third FET and the fourth FET being connected to a common point, and resistances connected to drains of the third FET and the fourth FET, respectively; and a fifth FET having a drain connected to a common source of said third FET and said fourth FET; wherein a drain voltage of said third FET is fed back to the gate of said first FET and a gate of said second FET, and a drain voltage of said fourth FET is fed back to a gate of said fifth FET.