Patent ID: 6963625

Claim:
An arrangement for selecting the largest of a plurality of input currents and adding a further current to the selected current, the arrangement comprising: a plurality of inputs for receiving said input currents; a further input for receiving said further current; an output for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, each of the transistors having its control electrode connected to a common point; a respective follower transistor connected between the input and the common point; a mirror transistor having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current; a summing arrangement for adding the largest of the input currents or a current proportional thereto to the further current or a current proportional thereto, said summing arrangement having a first input for receiving the current from the mirror transistor, a second input for receiving the further current, and an output; and means for coupling the output of the summing arrangement to the output of the arrangement.