Patent ID: 7129130

Claim:
A method for forming a transistor comprising: forming at least one trench in a silicon-on-insulator substrate, said at least one trench is formed to a depth extending through an insulating layer of said silicon-on-insulator substrate; forming a node dielectric and collar in said at least one trench, said collar being positioned above said node dielectric; forming a capacitor node in a lower portion of said at least one trench; recessing said collar below a top surface of said capacitor node to expose a portion of said insulating layer and laterally etching said insulating layer to provide a divot; forming strap diffusion regions, said strap diffusion regions comprising a lower strap diffusion region partially positioned on said collar and an upper strap diffusion region partially positioned in said divot; depositing a trench top oxide on said capacitor node; and forming a gate region atop said trench top oxide, wherein said transistor is in an upper portion of said at least one trench and said transistor in electrical contact to said silicon-on-insulator substrate through said upper strap diffusion region.