Patent ID: 8832364

Claim:
A system for controlling a storage device, the system comprising: a semiconductor chip of the storage device, the semiconductor chip including a first memory, wherein the first memory corresponds to a first type of memory, and wherein the first memory i) is configured to perform random access memory functions and ii) is not configured to perform direct memory access functions; and a second memory external to the semiconductor chip, wherein the second memory is configured to interface with the semiconductor chip, wherein the second memory corresponds to a second type of memory that is different than the first type of memory, wherein the second memory (i) is configured to perform direct memory access functions and (ii) is not configured to perform random access memory functions, and wherein the second memory comprises: a memory cell; and an interface configured to interface between (i) components of the second memory including the memory cell and (ii) the semiconductor chip, wherein the interface comprises a byte-wide communication path having a plurality of bit lines, wherein the interface is further configured to, using same ones of the plurality of bit lines of the byte-wide communication path, communicate, between the components of the second memory and the semiconductor chip, each of i) commands, ii) addresses, and iii) data, wherein the data is stored in the memory cell or read from the memory cell of the second memory.