Patent ID: 7739095

Claim:
A computer implemented circuit simulation method, comprising the steps of: inputting layout data representing a layout of at least a part of a circuit design, the circuit design including a plurality of interconnects; estimating, using a computer, a particular signal propagation delay value for each of the interconnects in the plurality, the particular signal propagation delay value being, for all of the interconnects in the plurality, a member of the group consisting of a minimum propagation delay value being a propagation delay value determined for assumed best-case propagation conditions, and a maximum signal propagation delay value being a propagation delay value determined for assumed worst-case propagation conditions; and outputting the estimated signal propagation delay values, wherein the step of estimating a particular signal propagation delay value, for each particular one of the interconnects in the plurality, comprises the steps of: making a particular approximate determination of whether or not a signal propagation delay time for the particular interconnect is dominated more by an interconnect capacitance than by a product of the interconnect capacitance and an interconnect resistance; and estimating the particular signal propagation delay value for the particular interconnect in dependence upon the step of making a particular approximate determination.