Patent ID: 6990015

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of tunneling magnetoresistive elements laid out in a hierarchical matrix form; a plurality of bit lines for letting a current to flow in those memory cells which are aligned in one direction; a plurality of word lines for letting a current to flow in those memory cells which are aligned in the other direction in such a way as to cross said bit lines; an X decoder for selecting a word line with respect to a selected memory cell; a Y decoder for selecting a bit line with respect to said selected memory cell, whereby data is written in said selected memory cell located at an intersection of said selected word line and said selected bit line by a combined magnetic field generated by letting a current to flow in said selected word line and bit line; and main bit lines which supply a write current from a write current source to said bit lines and are laid out in such a way as to cross said bit lines perpendicularly.