Patent ID: 7949883

Claim:
A cryptographic CPU architecture comprising: an ALU; a control flag; a plurality of registers for normally receiving output of the ALU in response to an arithmetic instruction; an additional register for receiving output of the ALU, in lieu of one of the plurality of registers, in response to an arithmetic instruction when the control flag is set; a first program counter; a second program counter; wherein the first and second program counters are responsive to a state of said control flag so that the first program counter is enabled where said control flag is not set and so that the second program counter is enabled where said control flag is set; wherein an enabled one of said first and second program counter fetches the arithmetic instructions; wherein either at least one first arithmetic instruction with the control flag set and at least one second arithmetic instruction with the control flag not set are combined into a substitution-permutation box such that the substitution-permutation box has a number of shifting instructions that is equal to a value set such that all substitution-permutation boxes generated by the cryptographic CPU architecture have the same number of shifting instructions, or at least one first arithmetic instruction with the control flag set and at least one second arithmetic instruction with the control flag not set are combined into a substitution-permutation box such that the substitution-permutation box has a number of shifting instructions that is equal to a randomly generated value such that all substitution-permutation boxes generated by the cryptographic CPU architecture are separated by a random time interval.