Patent ID: 7739472

Claim:
A memory device, comprising: at least one memory chip with a first set of memory and communication characteristics; a connector for coupling to a legacy host; said legacy host designed to operate with a legacy memory device having a second set of memory and communication characteristics and not designed to operate directly with said at least one memory chip; an interface circuit coupled between said connector and said at least one memory chip to enable said memory device to emulate said legacy memory when said legacy host is coupled to said connector; and wherein said interface circuit resolves at least one difference that exists between the first and second sets of memory and communication characteristics, said at least one difference selected from the group consisting essentially of error correction code, memory block size, number of bits stored in each memory cell, and status information; and said at least one difference includes a status bit indicating a memory operating condition among said first set of operating characteristics; and said interface circuit includes: a directory stored in said at least one memory chip; and a circuit for storing one or an alternative state of said status bit in said directory responsive to the presence or absence of said memory operating condition.