Patent ID: 7701232

Claim:
A semiconductor tester adapted for testing a semiconductor wafer including a plurality of integrated circuits arranged in a lattice, the semiconductor tester comprising: a wafer-interface probe having at least three contact patterns arranged in a non-rectangular, two-dimensional array, each contact pattern adapted to interface with a corresponding bonding pad pattern of a respective one of a plurality of integrated circuits disposed in a lattice on the semiconductor wafer, the two-dimensional array of contact patterns covering at least a 90 degree sector and no more than a 180 degree sector of the semiconductor wafer; and a rotary wafer handler rotating the semiconductor wafer relative to the wafer-interface probe between tests, bringing each of the at least three contact patterns into simultaneous alignment with a bonding pad pattern of a respective one of a plurality of integrated circuits, each of the at least three contact patterns providing electrical interconnection with a respective one of the aligned bonding pad patterns.