Patent ID: 7264995

Claim:
A method for manufacturing a wafer level chip scale package, the method comprising: (a) producing a redistribution substrate having a transparent insulating substrate and redistribution lines formed on the transparent insulating substrate; (b) providing a wafer having a semiconductor substrate having an active surface and at least one non-active surface, the wafer further having chip pads formed on the active surface; (c) bonding the redistribution substrate to the wafer so that first parts of the redistribution lines are connected with the chip pads; (d) forming holes extended from the active surface to the non-active surface in the wafer so that the second parts of the redistribution lines are exposed to the holes; (e) forming conductive lines in the holes and on the non-active surface; (f) forming external connection terminals on the conductive lines formed on the non-active surface; and (g) dividing both the redistribution substrate and the wafer along a scribe line.