Patent ID: 8288225

Claim:
A method of forming a memory array, comprising: forming a conductive polysilicon floating gate layer; forming a plurality of masking portions over the floating gate layer, the plurality of masking portions extending in a first direction and separated in a second direction; subsequently performing a first etch to remove portions of the floating gate layer that are exposed by the plurality of masking portions, the removed portions extending to a depth that is less than the thickness of the floating gate layer; subsequently oxidizing the polysilicon floating gate layer to form a silicon dioxide layer; subsequently forming, from the silicon dioxide layer, a plurality of sidewall spacers that extend in the first direction on the floating gate layer; and subsequently performing a second etch to form a plurality of trenches in a substrate, an individual one of the plurality of trenches extending in the first direction and having an extent in the second direction defined by ones of the plurality of sidewall spacers.