Patent ID: 8455300

Claim:
A method of manufacture of an integrated circuit package system comprising: providing a through-silicon-via die having conductive vias therethrough; forming a first redistribution layer on a bottom of the through-silicon-via die coupled to the conductive vias wherein forming the first redistribution layer includes forming a first insulator between and coplanar with a first interconnect layer; forming a second redistribution layer on the top of the through-silicon-via die coupled to the conductive vias; fabricating an embedded die superstructure on the second redistribution layer including: mounting an integrated circuit die to the second redistribution layer, forming a core material layer on the second redistribution layer to be coplanar with the integrated circuit die, forming a first build-up layer, having contact links coupled to the integrated circuit die, on the core material layer, forming a second build-up layer on the first build-up layer includes forming a substrate redistribution layer having contacts and traces, and coupling component interconnect pads to the contact links through the substrate redistribution layer; forming system interconnects on the first redistribution layer for coupling the through-silicon-via die, the integrated circuit die, the component interconnect pads, or a combination thereof; and mounting embedded discrete components in the core material layer including coupling the contact links between the embedded discrete components and the substrate redistribution layer.