Patent ID: 7176764

Claim:
A phase locked loop comprising: a phase detection unit for generating a phase error signal representing a phase error between an input signal and an output clock; a loop filter, coupled to the phase detection unit, for filtering the phase error signal and generating a first control signal; a cycle slip detector, coupled to the phase detection unit, for detecting whether a cycle slip has occurred according to the phase error signal and generating a slip indication signal; a toggling unit, coupled to the cycle slip detector for toggling the selection between a first value and a second value as a compensation signal according to the slip indication signal; an accumulator for accumulating the compensation signal and generating a second control signal; an adder for adding the first control signal and the second control signal and generating a third control signal; a controllable oscillator, coupled to the adder, for generating the output clock at a frequency based on the third control signal; wherein the first value and the second value have different signs.