Patent ID: 7271844

Claim:
A frame signal phase adjuster comprising: first means ( 21 ) comprising: means for inputting a SDI video signal and a frame reset pulse signal; means for generating a parallel clock from the SDI video signal; means for generating parallel data based on the SDI video signal and the parallel clock; means for using the frame reset pulse signal as video output timing to output the parallel data with the parallel clock; and means for outputting the parallel clock, and second means ( 22 ) comprising: means for inputting the parallel clock and a reference signal; means for generating a frame signal from the reference signal; means for adjusting a phase of the frame signal; means for generating an adjusted frame signal synchronized by the parallel clock from the parallel clock and the adjusted frame signal; means for generating a frame reset pulse signal based on the parallel clock and the adjusted frame signal synchronized by the parallel clock; and means for outputting the frame reset pulse signal.