Patent ID: 7463653

Claim:
A method of compressing a timing trace stream which has a logic signal associated with each clock cycle of a target device, comprising: determining that, during an instance of a preselected number of consecutive clock cycles, at least one logic signal at a first logic level and at least one logic signal at a second logic level are associated with respective ones of said clock cycles, and thereafter transmitting a first number of packets containing logic signals respectively associated with the preselected number of clock cycles; and determining that, during a further instance of said preselected number of consecutive clock cycles, the logic signals associated with the respective clock cycles all have a same logic level, and thereafter, instead of transmitting a corresponding said first number of packets, transmitting a compressed representation of the corresponding said first number of packets, wherein said compressed representation is formatted within a second number of said packets and contains an indication of said same logic level and an indication of said preselected number, and wherein said second number of packets is less than said first number of packets.