Patent ID: 7171539

Claim:
A data processing apparatus, comprising: a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, multiples of said plurality of modes being replicated in said secure domain and said non-secure domain for providing multiple non-secure modes comprising modes in the non-secure domain, and multiple secure modes comprising modes in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; a memory operable to store data required byte processor and comprising secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required; at least one memory management unit, upon receipt of the memory access request from the processor, for performing conversion of a virtbal address specified by the memory access request to a physical address; a first set of tables, each table in the first set containing a number of first descriptors, each first descriptor containing at least a virtual address portion and a corresponding intermediate address portion; a second set of tables, each table in the second set containing a number of second descriptors, each second descriptor containing at least an intermediate address portion and a corresponding physical address portion, the second set of tables being managed by the processor when operating in a privileged mode which is not a non-secure mode; the at least one memory management unit causing predetermined tables in said first and second set to be referenced to enable the conversion of the virtual address specified by the memory access request to a physical address, when said memory access request pertains to said non-secure domain, the predetermined table in said first set of tables comprises a table managed by the processor when operating in one of said non-secure modes, but the predetermined table in said second set of tables preventing access to physical addresses forming said secure memory.