Patent ID: 6869839

Claim:
A method of fabricating a semiconductor device comprising: forming a gate pattern on a transistor region of a semiconductor substrate including the transistor region and a resistor region; forming sequentially a buffer insulating layer, a first insulating layer and a second insulating layer on the gate pattern and on a portion of a surface of the semiconductor substrate; etching the second insulating layer to form a disposable spacer on a portion of the first insulating layer adjacent to sidewalls of the gate pattern; forming a deeply doped region in the semiconductor substrate that is aligned with the disposable spacer of the transistor region as a deeply doped source/drain region, and in the semiconductor substrate of the resistor region; removing the disposable spacer and the first insulating layer; forming a shallowly doped source/drain region in the semiconductor substrate aligned to the sidewalls of the gate pattern and adjacent to the deeply doped source/drain region of the transistor region; forming sequentially a third insulating layer and a fourth insulating layer on the buffer insulating layer; forming simultaneously an L-shaped spacer adjacent to the sidewalls of the gate pattern of the transistor region by patterning the fourth insulating layer, the third insulating layer, and the buffer insulating layer and forming a silicide formation protecting layer pattern on the resistor region; and forming a metal silicide on the deeply doped region of the transistor region, the resistor region, and an upper surface of the gate electrode.