Patent ID: 8229725

Claim:
A method of designing a circuit model having a processor system and custom circuits, comprising: generating a bus adapter coupled to a bus of the processor system; generating a shared memory interface between the custom circuits and the bus adapter, the shared memory interface including a first shared memory and a memory map for the processor system; and on a computer, generating a clock wrapper having the processor system, custom circuits, a first clock input and a second clock input for simulation on a programmable device, the first clock input driving the custom circuits and the first shared memory of the shared memory interface with a first clock signal, and the second clock input driving the processor system with a second clock signal; wherein the first clock signal is controllable as a gated clock signal in response to a single step control signal by a co-simulation module executing on the computer, or the first clock signal is controllable as a free-running clock signal in response to a free-running control signal by the co-simulation module, and wherein the second clock signal is another free-running clock signal, and wherein the gated clock signal at the first clock input, in response to the single step control signal, single steps the custom circuits on the programmable device simultaneously while the second clock signal free runs the processor system on the programmable device.