Patent ID: 8407561

Claim:
An apparatus, comprising: a plurality of turbo decoders; a plurality of memories; and a processing module, connected to the plurality of turbo decoders and the plurality of memories, for performing a plurality of mappings of a collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories; and wherein: during each respective decoding cycle of a plurality of decoding cycles, each of the plurality of turbo decoders retrieving respective information from a respective one of the plurality of memories in accordance with a respective one of the plurality of mappings of the collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories, decoding the respective information thereby generating respective updated information, and writing the respective updated information over the respective information in the respective one of the plurality of memories; the plurality of turbo decoders employing most recently updated information within the plurality of memories thereby generating a best estimate of at least one bit encoded within a turbo coded signal; and when performing turbo decoding, at least one of the plurality of turbo decoders performing quadratic polynomial permutation (QPP) de-interleaving on extrinsic information thereby generating “a priori probability” (app) information for use in subsequent decoding processing.