Patent ID: 7624389

Claim:
A design evaluation system comprising: a source code memory block configured to store a source code of a model simulating a system large-scale integrated circuit; and a central processing unit including: a static analyzer configured to analyze the source code by sampling a plurality of functions and a plurality of variables related to the functions from the source code; a compiler configured to compile the source code into an executable code; a dynamic analyzer configured to analyze each life start time and each life end time of the variables in case where the executable code is executed; and a memory load calculator configured to calculate for each variable a memory load by multiplying a life time of the variable by a size of the variable obtained from results of the analysis of the source code, to determine a number of memories or registers of the system large-scale integrated circuit based on the memory load for each of the variables, the life time being a difference between the life start time and the life end time, the size of the variable defined as a number of bytes of data stored in the variable.