Patent ID: 7526634

Claim:
A method, comprising: executing a first set of thread arrays in a processor, wherein the first set of thread arrays comprises a first set of thread groups, wherein thread groups from the first set of thread groups execute, in parallel, instructions associated with the first process, and wherein a first set of thread groups is associated with a first reference counter that increments upon completion of execution of each thread group from the first set of thread groups; specifying a second set of thread arrays as dependent on a status of execution of the first set of thread arrays; and delaying execution of the second set of thread arrays in the processor based on the status of execution of the first set of thread arrays, wherein delaying execution of the second set of thread arrays further comprises: counting a number of thread groups that have completed execution in the first set of thread arrays; and delaying until the number of thread groups that have completed execution equals a number of thread groups in the first set of thread arrays.