Patent ID: 7244642

Claim:
A method of fabricating a microelectronics device, comprising: depositing a protective layer over a spacer material located over gate electrodes and a doped region located between the gate electrodes; removing a portion of the spacer material and the protective layer located over the gate electrodes, a remaining portion of the spacer material remaining over the top surface of the gate electrodes and over the doped region, and a portion of the protective layer remaining over the doped region wherein removing a portion of the spacer material and the protective layer comprises plasma etching the spacer material and the protective layer; removing the remaining portion of the spacer material to form spacer sidewalls on the gate electrodes, expose the top surface of the gate electrodes, and leave a remnant of the spacer material over the doped region; forming source/drains adjacent the gate electrodes and through the remnant of the spacer material; and incorporating a metal into the gate electrodes.