Patent ID: 7827513

Claim:
A method in the design of an integrated circuit device, wherein the device includes child logical entities having physical areas located within a physical area of a parent logical entity and having parent placement areas for placement of buffers associated with the parent for wiring among ones of the child entities, the method comprising: a) placing wiring buffers in initial locations in ones of the placement areas; b) detecting a first wiring buffer associated with the parent entity and having an initial location in a first one of the parent placement areas within the child physical area; c) detecting geometric orientations of the parent placement areas, wherein detecting the geometric orientations comprises detecting lack of geometric orientations of ones of the placement areas; d) detecting a data flow orientation for the first wiring buffer; and e) changing, using a computer system, the location of the first wiring buffer responsive to detecting correspondence between the geometric orientation of the first one of the parent placement areas and the data flow orientation of the first wiring buffer, wherein changing the location of the first wiring buffer comprises selecting a second placement area for the changed location from among ones of the placement areas having no detected geometric orientation or having geometric orientations not corresponding to the data flow orientation of the first wiring buffer.