Patent ID: 7184013

Claim:
A semiconductor circuit system comprising: a first signal line; and n circuit sections, where n is an integer greater than 2, each of which includes an input terminal and an output terminal, wherein said input terminals of only predetermined k ones of said n circuit sections are connected to said first signal line, where k is an integer equal to or greater than 2 and less than n, and said output terminal of an m th one of said n circuit sections is connected to said input terminal of an (m+k) th one of said n circuit sections, where m is an integer varying between 1 and n−k, thereby k of said n circuit sections are activated at a given time, and wherein each of said n circuit sections comprises: a plurality of differential input circuits; a plurality of register circuits connected to output terminals of said plurality of differential input circuits, respectively; and a control circuit including a latch circuit, said control circuit connected with at least one of said plurality of register circuits as a specific register circuit and said plurality of differential input circuits, wherein said specific register circuit executes a predetermined operation using a first signal outputted from a corresponding one of said plurality of differential input circuits, and outputs a second signal to said latch circuit when the operation ends, and said control circuit activates said plurality of differential input circuits in response to a third signal to operate and stops the operations of said plurality of differential input circuits in response to said second signal.