Patent ID: 7254793

Claim:
A method for performing formal verification of an integrated circuit (IC) design, the method comprising: identifying a set of remodeling-eligible latches in a synthesized layout of sequential logic for the IC design, each of the set of remodeling-eligible latches exhibiting flip flop output behavior; replacing each of the set of remodeling-eligible latches in the synthesized layout with a flip flop to form a remodeled layout; and performing clock modeling on the remodeled layout, wherein identifying the set of remodeling-eligible latches comprises: applying cone partitioning to the synthesized layout to determine a data fan-in cone and a first clock net for a test latch in the synthesized layout, wherein cone partitioning starts at a latch pin and expands out recursively to compile upstream logic until one of a primary input and a sequential logic gate is reached; and including the test latch in the set of remodeling-eligible latches if: the data fan-in cone does not include a primary input to the synthesized layout; the data fan-in cone does not include a first sequential logic gate driven by a second clock net that is not functionally equivalent to the first clock net; and the data fan-in cone does not include a second sequential logic gate that exhibits a first phase behavior that is equivalent to a second phase behavior of the test latch.