Patent ID: 7580311

Claim:
A memory circuit, comprising: a supply node, a ground node, and a first high voltage (HV) node distinct from the supply node; at least one memory cell adapted to store data, the memory cell readable by coupling with at least the supply node and the ground node; and an HV circuit interposed between the first HV node and the at least one memory cell, the HV circuit comprising: a first and a second Field Effect Transistor (FET), each having a gate and a first and a second terminal, each respective first terminal coupled to the first HV node, the gate of the first FET coupled with the second terminal of the second FET at a first reference node, and the gate of the second FET coupled with the second terminal of the first FET at a second reference node; a third FET and a fourth FET, each having a gate and a first and a second terminal, each of their gates coupled to a second HV node, the first terminal of the third FET coupled to the first reference node, the first terminal of the fourth FET coupled to the second reference node, the second terminal of the third FET configured to provide a first output voltage to the memory cell, the second terminal of the fourth FET configured to provide a second output voltage to the memory cell; and a fifth FET and a sixth FET, each having a gate and two terminals, each of their gates coupled to the supply voltage, the first terminal of the fifth FET coupled to the second terminal of the third FET, the first terminal of the sixth FET coupled to the second terminal of the fourth FET, the second terminal of the fifth FET adapted to be driven by a first driving circuit, the second terminal of the sixth FET adapted to be driven by a second driving circuit, and in which the first output voltage and the second output voltage are provided by thus driving the second terminals of the fifth FET and the sixth FET, wherein the first driving circuit comprises: a first driving FET having a gate and two terminals, its gate adapted to receive a SET signal, its first terminal coupled with the second terminal of the fifth FET; a second driving FET having a gate and two terminals, its gate adapted to receive the SET signal, its first terminal coupled with the first terminal of the first driving FET, and its second terminal coupled to the ground node; a first reset FET having a gate and two terminals, its gate adapted to receive a RESET signal complementary to the SET signal, its first terminal coupled with the first terminal of the first driving FET, and its second terminal coupled to the ground node; and a second reset FET having a gate and two terminals, its gate adapted to receive the RESET signal, its first terminal coupled with the second terminal of the first driving FET, and its second terminal coupled to one of the supply node and the first (HV) node.