Patent ID: 8654556

Claim:
A registered Dual In-line Memory Module, comprising: a printed circuit board having a plurality of electrical contacts for connection to a data bus; a plurality of memory chips mounted on the printed circuit board, the memory chips having pins for address and control signals, and data pins that are separate from the pins for address and control signals; a control buffer having a register buffer configured to receive, buffer and re-drive address and control signals to the memory chips, and a control signal generator configured to generate an encoded control signal based on address and control signals received in the register buffer; and an electrical load reduction circuit coupled between the electrical contacts and the data pins of the memory chips and configured to at least one of receive first data via the electric contacts from the data bus and write the first data via the data pins into the memory chips, and read second data via the data pins from the memory chips and place the second data via the electric contacts onto the data bus; wherein the electrical load reduction circuit is coupled between the electric contacts and the data pins of the memory chips to cause an electrical load of the memory chips on the data bus being smaller with the memory chips being coupled to the data bus via the electrical load reduction circuit than connecting the memory chips directly to the data bus; and wherein the electrical load reduction circuit includes a buffer or switch array coupled between the electrical contacts and the data pins of the memory chips, and a decoder configured to receive the encoded control signal from the control signal generator, and decode the encoded control signal to control the buffer or switch array of the electrical load reduction circuit to communicate data to or from the data pins of the memory chips.