Patent ID: 8918684

Claim:
A semiconductor device comprising: a plurality of memory arrays each including a plurality of memory cells; a plurality of input/output lines each provided for an associated one of the memory arrays, each of the input/output lines being operatively coupled to a selected one of the memory cells of an associated one of the memory arrays; a bus line; a plurality of write amplifiers, each of write amplifiers being configured to drive, when activated, an associated one of the input/output lines in response to a first data signal supplied from the bus line; a plurality of read amplifiers each including an input port, each of the read amplifiers being configured to drive, when activated, the bus line in response to a second data signal supplied to the input port; a plurality of relief memory elements; a plurality of first switch circuits, each of the first switch circuits being connected between an associated one of the input/output lines and the input port of an associated one of the read amplifiers; a plurality of second switch circuits, each of the second switch circuits being connected between an associated one of the input/output lines and an associated one of the relief memory elements; and a plurality of third switch circuits, each of the third switch circuits being connected between an associated one of the relief memory elements and the input port of an associated one of the read amplifiers.