Patent ID: 7256415

Claim:
An integrated circuit structure comprising: a single memory cell comprising: a memory element having a first top electrical contact and a first bottom surface, wherein said memory element comprises: a first conductive layer; a bi-stable layer on said first conductive layer, wherein said bi-stable layer comprises a material with a bi-stable, programmable, electrical resistance and wherein said programmable electrical resistance of said bi-stable layer is adapted to allow information to be repeatedly stored in and erased from said memory element; and a second conductive layer on said bi-stable layer; a conductive section having a second top electrical contact and a second bottom surface and comprising a conductive material, wherein said conductive section is parallel to said memory element and wherein said bottom surface of said memory element is electrically connected to said bottom surface of said conductive section; a series of said single memory cells separated by an insulating material; and a cross point wire array connecting said single memory cells in said series, wherein said cross point wire array comprises first direction wires connecting said first top electrical contacts of said single memory cells in said series and second direction wires connecting said second top electrical contacts of said single memory cells in said series.