Patent ID: 7382649

Claim:
A nonvolatile semiconductor memory comprising: a bit line; a source line being perpendicular to the bit line; a memory cell unit array including a first memory cell unit and a second memory cell unit connected to the first memory cell unit in series along to the bit line, the first memory cell unit including first and second select gate transistors and a plurality of memory cell transistors arranged between the first and second select gate transistors in series, the second memory cell unit including third and fourth select gate transistors and a plurality of memory cell transistors arranged between the third and fourth select gate transistors in series, the second select gate transistor of the first memory cell unit connected to the third select gate transistor of the second memory cell unit via an inter-unit diffusion layer, a length of the first memory cell unit being equal to a length of the second memory cell unit; a bit line contact connecting the first select gate transistor of the first memory cell and the bit line; and a source line contact connecting the fourth select gate transistor of the second memory cell unit and the source line; wherein, the memory cell unit array is located having a shift length equal to the integral multiple length of the memory cell units aligned in a bit line direction so as to be staggered from each other as compared with adjacent memory cell unit arrays aligned in a source line direction.