Patent ID: 8024553

Claim:
A method of operation within an integrated-circuit processing device having a plurality of execution lanes, the method comprising: receiving an instruction to exchange data between the plurality of execution lanes; examining, in response to the instruction, respective requests from the plurality of execution lanes to determine a set of the execution lanes that is to send data to one or more others of the execution lanes during a first interval; signaling each execution lane within the set of the execution lanes to indicate that each execution lane is to send data to the one or more others of the execution lanes; determining, based on the set of the execution lanes, each of the one or more others of the execution lanes to which data is to be sent during the first interval; outputting, to each of the one or more others of the execution lanes to which data is to be sent during the first interval, a source lane identifier that identifies which execution lane within the set of the execution lanes from which to receive data during the first interval; and selecting, for each of the one or more others of the execution lanes to which data is to be sent during the first interval via an associated multiplexing circuit, a signal path coupled to the execution lane identified by the source lane identifier, wherein the associated multiplexing circuit comprises a plurality of multiplexers each having an output coupled to a respective one of the plurality of execution lanes, and inputs coupled to others of the plurality of execution lanes, and wherein each of the one or more others of the execution lanes to which data is to be sent during the first interval outputs a value that corresponds to the source lane identifier to a control input of a respective one of the plurality of multiplexers to switchably couple, to the output of the multiplexer, the signal path coupled to the execution lane identified by the source lane identifier.