Patent ID: 8169851

Claim:
A memory device with pseudo double clock signals, comprising: a memory cell array; a control signal generator configured to generate a control signal in response to an input command signal; a clock generator, configured to generate an even clock signal and an odd clock signal, wherein clock rates of both the even clock signal and the odd clock signal are half that of an input clock signal, and the even clock signal is inverse to the odd clock signal; an even clock controller receiving the control signal and the even clock signal; an odd clock controller receiving the control signal and the odd clock signal; and a functional block operated under a clock rate half that of the input clock signal and configured to control the access of the memory cell array; wherein the even clock controller is configured to provide the even clock signal to the functional block if a logic level of the even clock signal is one when the even clock controller receives a trigger of the control signal; wherein the odd clock controller is configured to provide the odd clock signal to the functional block if a logic level of the odd clock signal is one when the odd clock controller receives another trigger of the control signal.