Patent ID: 6984557

Claim:
Method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a non-volatile memory comprising a memory cell with a gate structure with an access gate and a gate structure with a control gate and a charge storage region situated between the control gate and the semiconductor body, in which method on the surface of the semiconductor body a first one of said gate structures is formed with side walls extending substantially perpendicular to the surface, a conductive layer is deposited on and next to said first gate-structure, the conductive layer is subjected to a planarizing treatment until the first gate structure is exposed and the so planarized conductive layer is patterned so as to form at least a part of the other gate structure adjoining only a first one of the side walls of the first gate structure, characterized in that, to perform said patterning of the planarized conductive layer, an etch mask is formed on the first gate structure and the planarized conductive layer which etch mask leaves the planarized conductive layer next to said first side wall uncovered and covers the planarized conductive layer next to the side wall opposite to the first side wall, after which the planarized conductive layer is etched back so as to expose an upper portion of said first side wall, the etch mask is removed, a spacer is formed on the exposed upper portion of said first side wall and the conductive layer is etched anisotropically using the spacer as a mask, whereby the conductive layer next to the spacer and next to the side wall of the first gate structure opposite to said first side wall is removed.