Patent ID: 7843034

Claim:
A capacitor comprising: a device region formed on a semiconductor substrate; a device isolation region formed outside the device region on the semiconductor substrate; a lower electrode formed in the device region, and formed of an impurity diffused layer, the lower electrode having an upper surface and an edge thereof; a dielectric film formed of a thermal oxide film formed over the lower electrode; an upper electrode formed over the dielectric film; an insulation layer formed over the semiconductor substrate, covering the upper electrode; a first conductor plug buried in a first contact hole which is connected to the lower electrode; and a second conductor plug buried in a second contact hole which is connected to the upper electrode, wherein a cavity is formed in the device isolation region adjacent to the edge of the lower electrode, wherein the dielectric film has a first part covering the upper surface of the lower electrode, and a second part covering the edge of the lower electrode, the second part including a portion having a thickness smaller than that of the first part, the thickness of the first part being measured in a direction perpendicular to a primary surface of the semiconductor substrate, the thickness of the second part being measured in a direction parallel to the primary surface of the semiconductor substrate, the first part and the second part being formed of one and the same dielectric film, and wherein the upper electrode is formed over the first part of the dielectric film, while the upper electrode is not formed directly over the second part of the dielectric film, wherein a peak value of an impurity concentration in the lower electrode is more than 1×10 20 cm −3 , wherein an entire upper surface of the lower electrode except a portion connected to the first conductor plug is covered with the dielectric film.