Patent ID: 7385427

Claim:
An electronic device, cornprising: a field effect transistor (FET) configured to receive a signal at a source terminal thereof and selectively provide the signal to a drain terminal thereof responsive to a switching signal at a gate terminal thereof; a capacitor electrically connected to the drain terminal of the FET; and a voltage offset circuit electrically connected to the source terminal and the gate terminal of the FET and configured to maintain a substantially constant voltage differential therebetween while the signal is provided to the drain terminal of the FET and substantially independent of a voltage level of an input signal, wherein the voltage offset circuit comprises: a first voltage offset circuit electrically connected to the gate terminal of the FET and configured to offset a voltage level of the input signal by a first predetermined voltage level to provide the switching signal to the gate terminal; and a second voltage offset circuit electrically connected to the source terminal of the FET and configured to offset the voltage level of the input signal by a second predetermined voltage level to provide the signal to the source terminal.