Patent ID: 7362826

Claim:
A receiver circuit comprising: an oscillator circuit including an oscillator configured to generate an oscillator signal, wherein the oscillator signal is divided by a first amount to generate a calibration tone and by a second amount to generate a phase locked loop (PLL) reference signal; a phase locked loop circuit configured to generate a PLL output signal that is phase locked in relation to the PLL reference signal; a quadrature generator configured to generate quadrature mixer local oscillator (LO) signals derived from the PLL output signal; and an in-phase/quadrature (IQ) mixer configured to mix the calibration tone with the quadrature mixer LO signals; a first switch coupled to selectively provide the calibration tone to the IQ mixer during a calibration mode of operation; and a second switch coupled to selectively provide the PLL reference signal to the phase locked loop circuit during the calibration mode of operation, and to provide a different reference signal to the phase locked loop circuit during a normal mode of operation.