Patent ID: 8441178

Claim:
An organic light emitting diode display device comprising: a pixel portion on a substrate, the pixel portion comprising a light generation region that generates light, and a pixel separating region around the light generation region; a thin film transistor in the light generation region; an insulating pattern on the substrate, the insulating pattern covering the thin film transistor and exposing a portion of the thin film transistor, wherein the insulating pattern has a via hole corresponding with the exposed portion of the thin film transistor and the via hole is removed of the insulating pattern; a conductive pattern being electrically connected to the thin film transistor through by the exposing and being on the pixel portion and being formed on a whole area of the light generation region; a pixel separating pattern comprising a first pixel separating portion and a second pixel separating portion, the first pixel separating portion having a lateral side of a undercut shape and disposed on the pixel separating region, and the second pixel separating portion extending from the first pixel separating portion and being disposed on the upper surface of the insulating pattern that corresponds to a periphery of the pixel portion; a first electrode electrically connected with the thin film transistor, the first electrode being disposed on the conductive pattern of the light generation region and naturally patterned for each pixel by the undercut of the pixel separating pattern; an organic emission layer on the first electrode; and a second electrode on the organic emission layer, wherein the pixel separating pattern has an opening that is exposing the light generation region, wherein the first pixel separating portion being separated from an upper surface of the conductive pattern and having a space between the first pixel separating portion and the upper surface and a sacrificial pattern is formed in the space of the first pixel separating portion to form the undercut of the pixel separating pattern, and wherein the conductive pattern is formed on the insulating pattern that includes a passivation pattern covering the thin film transistor, a planar pattern on the passivation pattern, and a buffer pattern on the planar pattern, wherein the buffer pattern is formed on an inner surface of the via hole and the conductive pattern is formed on the buffer pattern in the inner surface of the via hole, wherein the second electrode and the residual layer of the first electrode are formed on the pixel separating pattern and wherein the first electrode is formed on the conductive pattern such that the buffer pattern, the conductive pattern and the first electrode are stacked on the inner surface of the via hole.