Patent ID: 8631370

Claim:
A computer-implemented method comprising: creating a list of a plurality of ports and a physical location of the plurality of ports specified in a circuit design; determining a plurality of physically adjacent port pairs within the list of the plurality of ports that are physically adjacent in the circuit design; and for each respective physically adjacent port pair within the plurality of physically adjacent port pairs, performing calculating a timing window overlap for a current port and a next port in the respective physically adjacent port pair, wherein the respective physically adjacent port pair comprises the current port and the next port, computing a timing window overlap for the current port and each following port that is within a predetermined physical distance of the current port, and if the timing window overlap between the respective physically adjacent port pair is not smaller than the timing window overlap for the current port and each following port, swapping a physical location of the adjacent port in the circuit design with a physical location of the following port in the circuit design that has a smallest timing window overlap with the current port, wherein the timing window overlap for the current port and the next port comprises an amount of time where the current port and the next port are active at a same time.