Patent ID: 8614589

Claim:
A method of fabricating a semiconductor device, comprising: forming a plurality of semiconductor chips on semiconductor wafers, each of the semiconductor chips having a test circuit electrically connected to an input pad and an output pad, the input pad having a first pad located on a first principal surface of the semiconductor chip and a second pad located on a second principal surface of the semiconductor wafer opposite to the first principal surface, and electrically connected to the first pad; placing the plurality of semiconductor wafers on a stage of an inspection apparatus, each input pad of the semiconductor chips of the semiconductor wafer brought into contact with each input pad of the semiconductor chips of adjacent semiconductor wafer; bringing each of probing tips of the inspection apparatus into contact with each input pad of the semiconductor chips of an uppermost or lowermost semiconductor wafer in the semiconductor wafers placed on the stage; performing a test on the plurality of semiconductor chips in one batch by using each test circuit of the semiconductor chips and an input signal input from the inspection apparatus so as to obtain result data of the test; and storing the result data in the semiconductor chips.