Patent ID: 7327658

Claim:
A wobble signal processing apparatus comprising: a pickup for reading information recorded on an optical disc medium on/from which data can be recorded/reproduced, and outputting a wobble binary signal, a wobble signal and a RF signal; a Wobble (WBL) binarization circuit for smoothing edges of the wobble binary signal outputted from said pickup; a Front End Processor (FEP) for performing band limitation and gain control to the wobble signal outputted from said pickup; an Analog-to-Digital Converter (ADC) for converting the wobble signal outputted from said FEP into a digital signal; an address detection circuit for detecting an Address In Pre-Groove (ADIP) signal as address information of the data based on the digital signal outputted from said ADC; a waveform shaping circuit for generating a wobble binary signal waveform based on the RF signal outputted from said pickup; a phase control circuit for controlling the phase of the wobble binary signal outputted from said WBL binarization circuit with reference to the wobble binary signal waveform generated by said waveform shaping circuit, and outputting phase controlled data; and a Phase Locked Loop (PLL) circuit, which is connected to said phase control circuit, for generating a sync clock based on the phase controlled data outputted from said phase control circuit; wherein said address detection circuit and said waveform shaping circuit are digitally configured; wherein said address detection circuit comprises: a digital filter for filtering the digital signal outputted from the said ADC; and a Partial Response Maximum Likelihood (PRML) circuit for correcting errors in the signal outputted from said digital filter, and detecting the ADIP signal by using the corrected signal; and wherein a PRML system that is implemented by said PRML circuit is a PR(a,b) system.