Patent ID: 8467216

Claim:
A semiconductor memory device, comprising: first and second memory cell arrays each comprising at least one word line, at least three bit lines disposed in a direction perpendicular to the at least one word line, and memory cells disposed at intersections between the at least one word line and the at least three bit lines; and a sense amplifier area disposed between the first and second memory cell arrays and comprising a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction in the sense amplifier area and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction in the sense amplifier area, and wherein a first bit line of the at least three bit lines of the first memory cell array is connected to a data line of a middle data line pair of the data lines and a first bit line of the at least three bit lines of the second memory cell array is connected to another data line of the middle data line pair, a second bit line of the at least three bit lines of the first memory cell array is connected to a data line of an outer data line pair of the data lines and a second bit line of the at least three bit lines of the second memory cell array is connected to another data line of the outer data line pair, and a third bit line of the at least three bit lines of the first memory cell array is connected to a data line of an inner data line pair of the data lines and a third bit line of the at least three bit lines of the second memory cell array is connected to another data line of the inner data line pair.