Patent ID: 7859042

Claim:
A nonvolatile memory device comprising: first and second device isolation layer patterns in first and second regions of a semiconductor substrate that define respective first and second active regions; a first lower conductive pattern disposed on the first active region and having a bottom portion and an extended portion extending upward from the bottom portion and having a smaller width than the bottom portion; a second lower conductive pattern disposed on the second active region that is thicker than the bottom portion of the first lower conductive pattern; first and second upper conductive patterns on the first and second lower conductive patterns and crossing over the respective first and second active regions; and a gate interlayer insulating layer interposed between the first lower conductive pattern and the first upper conductive pattern, wherein the second lower conductive pattern includes a stacked first conductive layer pattern and second conductive layer pattern, wherein the first conductive layer pattern has a same thickness as the bottom portion of the first lower conductive pattern, and wherein a continuous top surface of the second conductive layer pattern in the second active region is substantially flat.