Patent ID: 7951678

Claim:
A method of forming an integrated circuit structure, said method comprising: providing a substrate; forming, on said substrate, a first semiconductor body for a first field effect transistor and a second semiconductor body for a second field effect transistor having a same conductivity type as said first field effect transistor, said first semiconductor body and said second semiconductor body each having a same conduction band energy and valence band energy; and forming different gate structures on said first semiconductor body and said second semiconductor body to achieve different threshold voltages in said first field effect transistor and said second field effect transistor, said forming of said different gate structures comprising: forming a first gate structure, having a first effective work-function that is near said conduction band energy, on a first center portion of said first semiconductor body, said forming of said first gate structure comprising forming, on said first center portion, a first high-k gate dielectric layer; and forming a second gate structure, having a second effective work-function different from said first effective work function and near said valence band energy, on a second center portion of said second semiconductor body, said forming of said second gate structure comprising forming a second high-k gate dielectric layer comprising a different high-k dielectric material than said first high-k gate dielectric layer, said first high-k gate dielectric layer and said second high-k gate dielectric layer having different charge fixed contents, said forming of said first gate structure further comprising forming a first gate conductor layer, having a first work function, on said first high-k dielectric layer and said forming of said second gate structure further comprising forming a second gate conductor layer, comprising a different gate conductor material than said first gate conductor layer and having a second work function different from said first work function, on said second high-k gate dielectric layer, and said forming of said first gate conductor layer comprising forming an n-doped polysilicon layer on said first high-k gate dielectric layer and said forming of said second gate conductor layer comprising forming a p-doped polysilicon layer on said second high-k gate dielectric layer.