Patent ID: 8625343

Claim:
A memory, comprising: a plurality of memory cells arranged in series in a semiconductor body, the series having a first end and a second end, memory cells in the plurality of memory cells having a threshold voltage in one of a first threshold voltage distribution associated with a first data value and a second threshold voltage distribution associated with a second data value, the first threshold voltage distribution having a first minimum and a first maximum and the second threshold voltage distribution having a second minimum and a second maximum, the first threshold voltage distribution being a lower voltage distribution than the second threshold voltage distribution; a plurality of word lines, word lines in the plurality of word lines coupled to corresponding memory cells in the plurality of memory cells; and a control circuit coupled to the plurality of word lines, wherein the control circuit applies a read bias arrangement to the plurality of word lines to read a selected data value stored on the plurality of memory cells by measuring current flowing between the first end and the second end of the series, wherein the read bias arrangement applied to word lines of the plurality of word lines applies only word line voltages less than the second maximum of the second threshold voltage distribution.