Patent ID: 7849373

Claim:
A memory module, comprising: p memory chips; a hub to be converted into a control mode; a differential input circuit configured to receive differential pairs of packet signals through input terminals in a first mode in response to a mode control signal; a single ended input circuit configured to receive single ended input signals through the input terminals in a second mode in response to the mode control signal; a signal processing circuit configured to decode the differential pairs of packet signals outputted from the differential input circuit to control the p memory chips in the first mode; and a test circuit configured to test the p memory chips based on the single ended input signals received at the single ended input circuit, the test circuit includes: a first data path through which data are transferred between the signal processing circuit and the p memory chips in the first mode; a data writing circuit configured to allow test data provided from the single ended input circuit to be concurrently stored in the p memory chips in the second mode; and a comparison circuit configured to sequentially access the stored test data in the p memory chips, and configured to compare each of the accessed test data with expected data provided from the single-ended input circuit to generate a comparing result in the second mode, the comparison circuit includes: a multiplexer configured to access p×q bits of data of the p memory chips twice and to sequentially multiplex the accessed p×2×q bits of data in a unit of 2×q bits of data, the 2×q bits of data corresponding to the respective p memory chips; and a comparator configured to sequentially compare the multiplexed 2×q bits of data with 2×q bits of expected data provided from the single ended input circuit to generate the comparing result, wherein the differential input circuit and the single ended input circuit are disabled or enabled in response to the mode control signal.