Patent ID: 7741697

Claim:
An anti-fuse, comprising: a semiconductor substrate; a gate dielectric layer formed on said semiconductor substrate; a gate electrode formed on said gate dielectric layer; a first doped region formed in said semiconductor substrate; a second doped region formed from a predetermined distance to said gate electrode, wherein said predetermined distance is larger than the distance between said first doped region and gate electrode and the coupling capacitance formed between said second doped region and said gate electrode is less than the coupling capacitance formed between said first doped region and said gate electrode; a metal-semiconductor compound formed on at least one of said gate electrode and said first and second doped regions; a conductive plug formed onto said metal-semiconductor compound; an isolation layer formed between said gate electrode and said conductive plug; and a resistance formed between said first and second doped regions wherein said resistance can be alternated by a predetermined electric signal.