Patent ID: 7788430

Claim:
An enhanced single-node protocol for data, address and control operations between digital devices, said protocol comprising the steps of: providing a master device having a bidirectional serial clock, and data and control input-output (SCIO) terminal; providing at least one slave device having a bidirectional SCIO terminal, wherein the master device SCIO terminal and the at least one slave device SCIO terminal are coupled together; generating a standby pulse from the master device SCIO terminal; generating a start header from the master device SCIO terminal; generating a master acknowledge from the master device SCIO terminal; generating a device address from the master device SCIO terminal; generating the master acknowledge from master device SCIO terminal; generating a slave acknowledge from the slave device SCIO terminal; generating a command from the master device SCIO terminal; generating the master acknowledge from the master device SCIO terminal; generating the slave acknowledge from the slave device SCIO terminal; generating an information byte from the master device SCIO terminal when sending information to the slave device SCIO terminal; generating an information byte from the slave device SCIO terminal when sending information to the master device SCIO terminal; generating a termination master acknowledge from the master device SCIO terminal; and generating the slave acknowledge from the slave device SCIO terminal.