Patent ID: 8129793

Claim:
A semiconductor integrated device, comprising: a semiconductor substrate; a first impurity layer of a first conductivity type formed in the semiconductor substrate; a second impurity layer of a second conductivity type formed above the first impurity layer; a first well of the first conductivity type formed above the second impurity layer and supplied with potential from the first impurity layer via an impurity region of the first conductivity type selectively formed in a part of the second impurity layer; a second well of the second conductivity type formed above the second impurity layer and supplied with potential from the second impurity layer, wherein impurity concentrations of the first impurity layer and the impurity region are higher than that of the first well, and an impurity concentration of the second impurity layer is higher than that of the second well; and a supply voltage region electrically connecting the second impurity layer, said supply voltage region comprising an opening in the first well that extends from an upper surface of the second impurity layer to an upper surface of the first well.