Patent ID: 7126835

Claim:
A semiconductor memory device comprising: a plurality of word lines each extending in a first direction; a plurality of bit lines each extending in a second direction crossing said first direction; a straight active region extending in a direction different from said first and second directions, said active region crossing three or more word lines and three or more bit lines; a plurality of memory cells formed in said active region, wherein each said memory cell includes a data storage capacitor, a first switching element connected to said data storage capacitor, and a second switching element connected to said data storage capacitor; a capacitor contact connected to the data storage capacitor and formed on said active region between the adjacent first and second word lines; a first bit line contact connected to a first one of said bit lines and arranged such that said first word line is sandwiched between said capacitor contact and said first bit line contact; and a second bit line contact connected to a second one of said bit lines and arranged such that said second word line is sandwiched between said capacitor contact and said second bit line contact.