Patent ID: 7948069

Claim:
A semiconductor package comprising: a flat substrate, said substrate including a first major surface and a second major surface opposite said first major surface, and an opening therethrough; a first electrical terminal on said first major surface of said substrate; a second electrical terminal attached to said second major surface of said substrate and being wider than said opening such that said second electrical terminal closes said opening; a semiconductor die disposed in said opening and having a first electrode electrically connected to said first electrical terminal and a second electrode disposed opposite said first electrode and electrically and mechanically connected to said second electrical terminal by a layer of conductive adhesive; a hermetically sealed cover attached to said first major surface and closing said opening; wherein said first electrical terminal and said second electrical terminal each have a surface for external electrical connection outside said package; wherein said second electrical terminal being wider than said opening enables said package to pass a current of approximately 200 A and withstand a voltage between said electrical terminals of approximately 2 kV.