Patent ID: 8134859

Claim:
A non-volatile memory cell comprising: an antifuse element having a programming node and a control node, the antifuse element being configured to have changed resistivity after the programming node is subjected to one or more voltage pulses, the change in resistivity representing a change in logic state; a capacitor element coupled to the programming node of the antifuse element and configured to provide the one or more voltage pulses to the programming node; a precharge element coupled to the programming node of the antifuse element and the capacitor element and configured to increase the one or more voltage pulses provided to the programming node; an access element coupled to the control node of the antifuse element, the access element configured to allow determination of the logic state of the antifuse element based on current flow through the access element; and a leakage element coupled to the control node of the antifuse element and the access element, the leakage element configured to modify the current flowing through the access element when the resistivity of the antifuse element has not been changed.