Patent ID: 7445993

Claim:
A method of fabricating non-volatile memory, comprising the steps of: providing a substrate having a memory cell region and a peripheral circuit region; forming a plurality of first memory cells on the substrate in the memory cell region, wherein every pair of adjacent first memory cells has a gap; forming a first composite layer over the substrate, wherein the first composite layer includes a second charge storage layer; forming a first conductive layer over the substrate to cover the first memory cells and fill up the gaps; removing the first conductive layer and the first composite layer in the peripheral circuit region and removing a portion of the first conductive layer in the memory cell region so that a plurality of second gates is formed to fill the gaps in the memory cell region, wherein the second gates and the first composite layer form a plurality of second memory cells and the second memory cells and the first memory cells form a first memory cell column; forming a gate dielectric layer over the substrate in the peripheral circuit region; forming a second conductive layer over the substrate to cover the gate dielectric layer in the peripheral circuit region and to cover the first memory cell column in the memory cell region; forming a dielectric layer over the second conductive layer; patterning the dielectric layer and the second conductive layer to form a plurality of gate structures in the peripheral circuit region and removing the dielectric layer the second conductive layer in the memory cell region; and forming source/drain regions in the substrate on the respective sides of the first memory cell column.