Patent ID: 7283547

Claim:
A switch comprising: a port card for receiving packets from and sending packets to a network; and a plurality of fabrics connected to the port card for switching the packets, each fabric having memory controllers which perform logical functions and in which portions of the packets are stored, each fabric having stages for switching the portions of the packets, each fabric having a mechanism for propagated lockdown of each stage wherein each stage is idle a correct number of logical cycles and each memory controller performs a same logical function at a corresponding same logical cycle for each fabric, the stages are arranged so that if any given stage is idle at a given logical cycle, a following stage to the given stage is idle a following logical cycle to the given logical cycle, the stages form a pipeline, and each stage in each logical cycle has an output which is a count based on a number of packets processed by the memory controller in the logical cycle, the lockdown mechanism includes a buffer mechanism in which the count of the stage is stored when the stages are idle during the logical cycle, the lockdown mechanism keeps track at each logical cycle if each stage is idle, and stores the count of the stage that is idle in the buffer mechanism if the following stage to the stage is not idle, maintains each count stored in the buffer mechanism when the stage and the following stage are idle for the logical cycle, and releases an earliest count stored in the buffer mechanism when the stage is not idle for the logical cycle.