Patent ID: 8464007

Claim:
A memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations, the memory manager comprising: a plurality of banks, wherein each bank includes a bank queue for storing read and write requests from each of a plurality of processors; a request arbiter connected to the plurality of banks, wherein the request arbiter removes read and write requests from the bank queues for presentation to the memory device; and a memory sequencer connected to the bank queue of each of the plurality of banks, wherein the memory sequencer arbitrates requests going to the memory device so that requests associated with a retry operation take precedence over all other requests for data directed to the memory device; wherein the request arbiter includes a read phase of operation and a write phase of operation and wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation but will select write requests for servicing when no read requests are available while remaining in the read phase of operation until a predetermined number of read requests have been serviced, and preferentially selects write requests for servicing during the write phase of operation but will select read requests for servicing when no write requests are available while remaining in the write phase of operation until a predetermined number of write requests have been serviced.