Patent ID: 7538625

Claim:
A phase-locked loop (PLL) circuit comprising: a phase frequency detector receiving a reference signal and a feedback signal of an output signal of the PLL circuit, said phase frequency detector generating a differential signal, a charge pump coupled to said phase frequency detector receiving said differential signal, said charge pump generating either negative or positive charge pulses responsive to said reference signal and said output feedback signal, a low-pass filter coupled to said charge pump, said low-pass filter generating a tuning voltage, a voltage controlled oscillator coupled to said low-pass filter receiving said tuning voltage, said voltage controlled oscillator generating a VCO output signal, a first divider coupled to the voltage controlled oscillator receiving and dividing down said VCO output signal, said first divider providing the output signal of the PLL circuit; a second divider receiving the output signal of the PLL circuit and providing said feedback signal to said phase frequency detector; and the output signal of the PLL circuit being applied to a clock tree, and wherein said first divider is configured to allow the phase-locked loop VCO output signal to vary in a frequency range much greater than a maximum frequency at the clock tree.