Patent ID: 8050374

Claim:
A semiconductor memory device comprising: a delay locked loop circuit configured to produce first and second delay locked clock signals through a delay locking operation, wherein the first delay locked clock signal is used to output data to an external circuit, and the second delay locked clock signal is used to prepare the data to be outputted to the external circuit; a tAC control unit, separate from the delay locked loop circuit, configured to receive the first delay locked clock signal from the delay locked loop circuit, adjust a delay value of the first delay locked clock signal in order to control a tAC timing, and output a delay-adjusted clock signal; a reference signal generating unit configured to generate a reference signal in response to the second delay locked clock signal; and a data output block configured to produce a data strobe signal in response to the delay-adjusted clock signal, and latch and output the data in response to the delay-adjusted clock signal and the reference signal, wherein the data output block includes: a data output timing control unit configured to generate a data output enable signal and a control signal indicative of preamble and postamble in response to the delay-adjusted clock signal; a data latch unit configured to latch the data, which are provided by a memory core area, in response to the delay-adjusted clock signal and the reference signal; a data output unit configured to output the data latched in the data latch unit in response to the data output enable signal: and a data strobe signal generating unit configured to generate the data strobe signal in response to the data output enable signal.