Patent ID: 8440515

Claim:
A method of forming a field effect transistor having laterally spaced elevated source/drains on a substrate comprising: forming and laterally spacing elevated source/drain material of the transistor prior to final patterning which defines the lateral peripheral outline of active area where such physically contacts field isolation and which defines the lateral peripheral outline of the field isolation where such physically contacts the active area; forming conductive material of a gate of the transistor after forming the laterally spaced elevated source/drain material, and forming the conductive material of the gate and the elevated source/drain regions to have planar elevationally outermost surfaces that are coplanar; and etching the conductive material of the gate and the elevated source/drain regions elevationally inward, and thereafter forming a conductor material onto each of the conductive material and elevated source/drains, the conductor material being of higher conductivity than the conductive material and the elevated source/drains.