Patent ID: 7129859

Claim:
A method of minimizing pulse distortion in a silicon-on-insulator (SOI) first circuit receiving data over a data channel from a second circuit separated from the first circuit comprising the steps of: generating an N bit scramble bit pattern at the second circuit having a predetermined ratio of logic one states to logic zero states; generating a scrambled data pattern as a first logic exclusive OR (XOR) combination of first data from the second circuit and the N bit scramble bit pattern synchronized as a synchronized N bit scramble bit pattern; transmitting the scrambled data pattern over the data channel through the first circuit to an output of the first circuit; generating the synchronized N bit scramble bit pattern at the first circuit with a propagation delay time; and recovering the first data from the transmitted scrambled data pattern as detected first data by a second logic XOR combination of the scrambled data pattern coupled from the output of the first circuit and the synchronized N bit scramble bit pattern generated at the first circuit.