Patent ID: 7160772

Claim:
A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device, the method comprising: forming an isolating layer over a lower wiring level; forming a bottom electrode of the capacitor on said isolating layer; forming an interlevel dielectric material on said isolating layer and said bottom electrode; patterning said interlevel dielectric material so as to define a capacitor trench, said capacitor trench stopping on said bottom electrode: forming a capacitor dielectric in said capacitor trench and on said bottom electrode, forming a protective liner over said capacitor dielectric and forming a top electrode of the capacitor on said capacitor dielectric, said protective liner further comprising a portion of said top electrode; wherein said top electrode is formed concurrently with an upper wiring level, said upper level being the next successive wiring level with respect to said lower wiring level, and wherein said bottom electrode is patterned and said interlevel dielectric is formed prior to forming said capacitor dielectric and said top electrode.