Patent ID: 7214601

Claim:
A process for manufacturing a power junction field-effect transistor (JFET), comprising steps of: (a) providing a substrate having an epitaxy layer formed thereon; (b) forming an oxide layer on said epitaxy layer; (c) patterning said oxide layer by a first photolithography and etching procedure to define a gate runner window and a guard ring window; (d) performing a first implanting procedure to implant a first dopant in said epitaxy layer through said gate runner window and said guard ring window; (e) patterning said oxide layer by a second photolithography and etching procedure to define a pair of gate windows; (f) performing a second implanting procedure to implant a second dopant in said epitaxy layer through said gate runner window and said gate windows, thereby forming a pair of gate regions and a gate runner in said epitaxy layer; (g) forming an inter-layer dielectrics layer on said oxide layer; (h) patterning said inter-layer dielectrics layer and said oxide layer by a third photolithography and etching procedure to define a source window; (i) performing a third implanting procedure to implant a third dopant through said source window, thereby forming a source layer overlying said gate regions; (j) patterning said inter-layer dielectrics layer and said oxide layer overlying the gate runner by a fourth photolithography and etching procedure to define a gate runner/metal layer junction window; and (k) depositing a metal layer on the resulting structure, and patterning said metal layer by a fifth photolithography and etching procedure to form a gate runner metal layer and a source metal layer, which are connected to said gate runner and said source layer, respectively.