Patent ID: 8225263

Claim:
A design method of a semiconductor integrated circuit carried out by a computer, comprising: a DRC step, performed by the computer, of performing a design rule check (DRC) with reference to layout information on an internal wiring in a capacitor cell and layout information on a signal wiring in said semiconductor integrated circuit, said DRC adapted to determine whether said capacitor cell can be laid out in an area of said semiconductor integrated circuit or not; an integration step, performed by the computer, of integrating layout information on said internal wiring into layout information on said signal wiring when being determined in said DRC step that there is an error; and an elimination step, performed by the computer, of eliminating an error portion in said internal wiring from said integrated layout information, wherein said internal wiring is connected to a power supply terminal and a grounding(GND) terminal in said capacitor cell, wherein said method further comprises a step of preparing a substitution cell in which said internal wiring is eliminated from said capacitor cell, wherein said integration step comprises: a step of performing temporary arrangement of said capacitor cell in said semiconductor integrated circuit; a step of integrating layout information on internal wiring of said capacitor cell into layout information on a signal line in an area where temporary arrangement of said capacitor cell has been performed; and wherein said elimination step comprises: a step of substituting said substitution cell for said capacitor cell for which temporary arrangement has been performed; and a step of eliminating layout information corresponding to said error portion from layout information on an area where said substitution cell has been arranged.