Patent ID: 7489176

Claim:
A circuit, comprising: a plurality of output pairs; a clock generator to provide a clock signal; and a clock distribution circuit coupled to the clock generator and the plurality of output pairs, wherein the clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of clock signal pairs in accordance with the clock signal, a respective adjustment circuit in the plurality of adjustment circuits to provide a respective clock signal pair in the plurality of clock signal pairs to a respective output pair in the plurality of output pairs, the respective clock signal pair including a first clock signal and a second clock signal, wherein the first clock signal is a complement of the second clock signal, and wherein the respective adjustment circuit includes at least one register to store at least one value that corresponds to adjustments for duty-cycle and skew errors in the first clock signal and the second clock signal, wherein the skew error corresponds to a phase difference other than 180° between the first clock signal and the second clock signal.