Patent ID: 7890676

Claim:
A memory system comprising: a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller; and at least two layers of memory, each memory layer further comprising at least two memory buffer devices, each layer of memory connected for communication of memory signals by at least one outbound link to at least one memory buffer device in the memory layer, each layer of memory connected for communication of memory signals by at least one inbound link from at least one memory buffer device in the memory layer, the inbound links characterized by an inbound link speed, the outbound links characterized by an outbound link speed, the inbound link speed dependent upon the outbound link speed.