Patent ID: 6897801

Claim:
An A/D converter, comprising: a first array of sampling capacitors weighted in binary code, each connected between a first circuit node and a central terminal of a controlled switching device associated therewith, said device having a multiplicity of terminals selectively connectable with the central terminal; a second array of sampling capacitors weighted in binary code, each connected between a second circuit node and a central terminal of a controlled switching device associated therewith, said device having a multiplicity of terminals capable of being selectively connected with the central terminal; reference voltage generator means comprising a common reference terminal, a first and a second differential reference terminal, and a common mode reference terminal; an input terminal for analog signals referred to the voltage of the common reference terminal; first and second controlled connection means connected, respectively, to the first and the second circuit node for selective connection to the common mode reference terminal; a voltage comparator having a first and a second input terminal connected, respectively, to the first and the second circuit node, and an output terminal; processing, control, and register means connected to the output of the comparator, to the controlled switching devices, associated with the capacitors and to the controlled connection means to operate said switching devices and said connection means in accordance with a predetermined timing program and as a function of the output of the comparator, to memorize the states of at least some of the switching devices associated with the capacitors and to furnish output signals corresponding to the analog signals applied to the input terminal; wherein the multiplicity of selectively connectable terminals of each of the switching devices of the first capacitor array comprises a first terminal connected to the input terminal and a second and a third terminal connected, respectively, to the first and the second differential reference terminal; and the multiplicity of selectively connectable terminals of each of the switching devices of the second array comprises a first terminal connected to the common reference terminal and a second terminal connected to the second differential reference terminal.