Patent ID: 7425855

Claim:
A method for implementing enhanced noise immunity performance in a latch circuit including an L1 latch and an L2 latch coupled to the L1 latch, said method comprising: latching data in the L1 latch during a first half clock cycle and providing a latched data state at an L1 latch output node and then latching data in the L2 latch during a second half clock cycle and providing a latched data state at an L2 latch output node; connecting a plurality of gated transistors between said L1 latch output node and ground, and between said L1 latch output node and a voltage supply for gating off a path from said L1 latch output node to ground with a high latched data state at said L1 latch output node; connecting a plurality of gated transistors between said L2 latch output node and ground, and between said L2 latch output node and said voltage supply for gating off a path from said L2 latch output node to ground with a high latched data state at said L2 latch output node; and connecting predefined L2 nodes to selected gates of said plurality of gated transistors in the L1 latch.