Patent ID: 8693260

Claim:
A memory device, comprising: an array of memory cells, including a plurality of columns and rows; a plurality of data lines coupled to columns in the array; a plurality of word lines coupled to rows in the array; a precharge circuit to precharge a data line in the plurality of data lines in a precharge interval, having a first phase and a second phase; a clamp circuit, coupled to the data line in the plurality of data lines; a bias circuit that provides a bias voltage which turns on the clamp circuit with a first bias level during the first phase of the pre-charge interval, and with a second bias level higher than the first bias level during the second phase of the pre-charge interval, the bias circuit being responsive to at least one timing signal to set the first bias level during the first phase and the second bias level during the second phase; and a sense amplifier coupled to the data line.