Patent ID: 7809921

Claim:
An address translation mechanism for translating a virtual address in a virtual address space to a real address for accessing memory of a digital data processing system, comprising: a block accessing mechanism which uses a first portion of a virtual address to be translated to select at least one block from among a plurality of equal-sized blocks, each said block containing a respective plurality of page table entries; wherein each said page table entry within each said block corresponds to a respective page of said virtual address space, wherein all said pages of virtual address space corresponding to page table entries in the same said block are contiguous, all said pages of virtual address space corresponding to page table entries in the same said block sharing a common high-order portion of a virtual address corresponding to the respective block; a selector for selecting a page table entry from among said plurality of page table entries within a said block selected by said block accessing mechanism, said selector using a second portion of said virtual address to be translated, said second portion and said first portion having no bit positions of said virtual address in common; and a comparator for comparing a third portion of said virtual address to be translated with at least part of said common high-order portion of a virtual address corresponding to a said block selected by said block accessing mechanism and generating a signal indicating whether said third portion of said virtual address to be translated and said portion of a virtual address corresponding to the block selected by said block accessing mechanism are identical.