Patent ID: 8811430

Claim:
A system on a chip (SoC) comprising: a plurality of processor cores coupled via a ring and configured on a first semiconductor die; a fabric coupled to the plurality of processor cores and to communicate with at least one agent on the first semiconductor die according to an on-chip protocol, the on-chip protocol a native non-packetized protocol; and a packetization logic configured on the first semiconductor die and coupled to the fabric to receive command information from the fabric on a command link and data information from the fabric on a data link and to generate packets for transmission from the first semiconductor die to a second semiconductor die coupled thereto, each of the packets including one of the command information, the data information, and credit information in a multiplexed manner in which the command information and the data information are sent in different clock periods, wherein the packetization logic includes an arbiter to select one of the packets to enable the transmission from the first semiconductor die to the second semiconductor die if the second semiconductor die has a sufficient number of credits to receive the packet.