Patent ID: 7940575

Claim:
A memory device, comprising: a plurality of memory cell arrangements, each memory cell arrangement comprising a plurality of memory cells and a control circuit to control access to the memory cells of the respective memory cell arrangement; a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit arrangement is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals; a connecting circuit arrangement controller configured to control the connecting circuit arrangement to simultaneously provide a plurality of logic connections to the memory cell arrangements using the controllable connections; and wherein the plurality of memory cell arrangements comprise a first memory cell arrangement and a second memory cell arrangement; wherein the connecting circuit arrangement controller is configured to control the connecting circuit: to provide a logic connection between the first memory cell arrangement and the second memory cell arrangement using the controllable connections; and to transfer data stored in the first memory cell arrangement to the second memory cell arrangement via the logic connection.