Patent ID: 8910092

Claim:
A method, comprising: receiving a target layout design having a geometric pattern thereon; using a computing unit to apply a set of fast-bias contour (FBC) rules to the target layout design to provide an electronic photomask having FBC-edits that differentiate the electronic photomask from the target layout design, wherein the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design; and performing a lithography process check on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design; wherein the lithography process check includes a Monte-Carlo process where a plurality of device parameters are randomly varied for a plurality of simulations to characterize how semiconductor devices are expected to be manufactured based on the electronic photomask, which includes the FBC-edits.