Patent ID: 8035036

Claim:
A complementary mirror image embedded planar resistor architecture, comprising: an embedded planar resistor, located on a first plane; a first electrode and a second electrode, located on the first plane, wherein the embedded planar resistor completely covers the first electrode, the first electrode is used to connect the embedded planar resistor to a first via hole, so as to further connect the embedded planar resistor to circuit elements on other planes above or below the embedded planar resistor, and the second electrode is used to connect the embedded planar resistor to a second conductive wire, so as to further connect the embedded planar resistor to circuit elements on other planes above or below the embedded planar resistor; a conductive layer, located on a second plane; and a dielectric layer, made of at least one material, and sandwiched between the first plane and the second plane, wherein a hollow structure is formed in the conductive layer at the mirror image location corresponding to the embedded planar resistor, and the shape and area of the hollow structure are designed corresponding to the shape and area of the embedded planar resistor; wherein the hollow structure is an entirely hollow structure, with an area of about 0.5-1.5 times of that of the embedded planar resistor.