Patent ID: 7073049

Claim:
A dual language processor structure comprising: at least one instruction fetching unit for fetching stack-based instructions from stack-based programs and register-based instructions from register-based programs; at least one decoding unit for decoding the fetched stack-based instructions and register-based instructions, wherein the at least one decoding unit is a switching type decoder having a stack-based instruction decoder and a register-based instruction decoder, and one of the two decoders is selected based on status of a status flag for decoding the respective stack-based instructions or register-based instructions; at least one operand access unit for accessing operands corresponding to the fetched stack-based instructions and register-based instructions, the operand access unit having a register set, a data stack and a selector, the register set having a plurality of registers, the data stack having a plurality of stack items and a stack pointer, the selector being connected to each stack item of the data stack and at least one register of the register set for being switched to make a stack item pointed by the stack pointer communicate with the at least one register; at least one execution unit for performing operations corresponding to operators decoded by the decoding unit and the operands accessed by the operand access unit; and at least one memory access unit for accessing executing result from the execution unit.