Patent ID: 7020000

Claim:
A method for detecting a mismatch in a content addressable memory (CAM), the method comprising: charging a matchline of a match detection circuit of said CAM to a first voltage level lower than a supply voltage level; comparing a logic state of a first bit stored in said CAM with a logic state of a second bit received at said CAM, said comparison comprising receiving said logic state of said first bit at a gate of a first transistor, and receiving said logic state of said second bit at a gate of a second transistor in series with said first transistor, wherein if said logic state of said first bit does not match said logic state of said second bit, said first and second transistors are activated and conducting; and changing the voltage level of said matchline to a ground voltage level through said first and second transistors if the logic state of the first bit does not match the logic state of the second bit.