Patent ID: 6952050

Claim:
A semiconductor package comprising: a chip having an active surface and an outside surface, the chip having a plurality of electrode bumps formed on the active surface thereof; a package substrate having an upper surface and a lower surface opposite the upper surface, the chip being electrically connected to the upper surface of the substrate; a lid thermally connected to and disposed over the upper surface of the chip for emitting heat generated from the chip; a thermal interface material (TIM) interposed between the chip and the lid for transferring heat generated from the chip to the lid; and a heat dissipation cover also interposed between the chip and the lid for dissipating heat, the heat dissipation cover adjacent the TIM, wherein the heat dissipation cover is formed around a back surface of the chip opposite the active surface of the chip and also directly on side surfaces of the chip, and wherein the lid, the substrate, and the heat dissipation cover form an empty space therein.