Patent ID: 7280091

Claim:
An analog front-end (AFE) circuit of a digital display, comprising: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal; wherein the first circuit comprises: a frequency divider for dividing a vertical sync signal to generate a selection signal; and a control signal outputting unit for outputting the working clock or an inverted signal of the working clock to be the control signal according to the selection signal.