Patent ID: 7602043

Claim:
A coupling capacitor of a semiconductor memory device, which is disposed on an interlayer insulating layer and includes a plurality of serially connected capacitors, the serially connected capacitors respectively including lower electrodes, dielectric layers, and upper electrodes, the coupling capacitor comprising: a first capacitor among the serially connected capacitors formed on, and including one of the lower electrodes in contact with, a first conducting pad disposed on the interlayer insulating layer; a second capacitor among the serially connected capacitors formed on, and including one of the lower electrodes in contact with, a second conducting pad adjacent to the first conducting pad, and electrically connected to the first capacitor through a common upper electrode; and a third capacitor among the serially connected capacitors formed on, and including one of the lower electrodes in contact with, the second conducting pad and electrically connected to the second capacitor through the second conducting pad, wherein a lower electrode of the coupling capacitor is the first conducting pad and an upper electrode of the coupling capacitor is the upper electrode of the third capacitor, wherein the coupling capacitor is formed on the same interlayer insulting layer as a storage capacitor of the semiconductor memory device, and wherein each of the first, second, and third capacitors has substantially the same structure as the storage capacitor.