Patent ID: 7935587

Claim:
A method of forming a semiconductor device, the method comprising: forming a MOS device in a substrate, the MOS device comprising a source, a drain, a channel region between the source and the drain, a gate electrode over the channel region, and a pair of sidewall spacers adjacent opposite sides of the gate electrode, the pair of sidewall spacers having sidewall spacer surfaces; forming a stressor layer over the MOS device; forming a mask layer over the stressor layer; patterning the mask layer so that a portion of the stressor layer overlying the gate electrode and a portion of the stressor layer adjacent the sidewall spacers are exposed, while a portion of the stressor layer overlying the source and the drain regions spaced apart from the sidewall spacers remains covered by the mask layer; substantially completely removing the stressor layer from over the gate electrode; and selectively removing the stressor layer from a portion of the sidewall spacer surfaces, the selectively removing the stressor layer not thinning the portion of the stressor layer covered by the mask layer overlying the source and the drain regions; and removing the mask layer while leaving the stressor layer intact overlaying the source and the drain regions.