Patent ID: 8924767

Claim:
An integrated circuit chip comprising: timestamp generator circuitry coupled to a clock signal and generating sequential count timestamp data synchronous to the clock signal, each datum having most significant bits and least significant bits, the toggle rate of the most significant bits being slower than the toggle rate of the least significant bits, and the most significant bits having a next value at a rollover of the least significant bits; a unidirectional parallel data bus connected to the timestamp generator and having data lines transmitting in parallel the least significant bits of each sequential timestamp datum; a series data bus connected to the timestamp generator and having a single data line transmitting in series the most significant bits of each timestamp datum having the next value at the rollover of the least significant bits; and client circuitry including: a parallel register connected to the parallel data bus receiving in parallel and storing the least significant bits of one timestamp datum, a series register connected to the series data bus receiving in series and storing the most significant bits of another timestamp datum, and a merged register connected to the parallel register and the series register and storing a merged timestamp datum by concatenation of the least significant bits of the one timestamp datum stored in the parallel register and the most significant bits of the another timestamp datum stored in the series register.