Patent ID: 8198935

Claim:
A capacitive voltage divider having an input and an output and including at least a first switched capacitor circuit, the capacitive voltage divider comprising: a) a substrate material comprising a semiconductor material; b) a well, deposited in the substrate material comprising an opposite semiconductor material to the substrate; c) a first source, comprising a semiconductor material of an opposite type as the well material, deposited in the well; d) a first drain, comprising a semiconductor material of an opposite type as the well material, deposited in the well; e) a first dielectric deposited on the substrate material proximal to the first source and the first drain; f) a conductive material, deposited on the dielectric material to form a gate of a first metal-oxide-semiconductor field-effect transistor (MOSFET); g) a first capacitor having a first and second terminal, the first terminal being coupled to the drain of the first MOSFET and the second terminal being coupled to the input to the capacitive voltage divider; h) a first circuit coupled to the drain of the first MOSFET, the first circuit configured to pull down the drain of the first MOSFET and thus apply a reverse bias to a first junction diode internal to the first MOSFET, the first junction diode being between the drain of the first MOSFET and the bulk of the first MOSFET, the reverse bias being applied when the first MOSFET is off and the first circuit being coupled to short the first junction diode in the first MOSFET when the first MOSFET is on; i) a second source, comprising a semiconductor material of an opposite type as the substrate material, deposited in the substrate; j) a second drain, comprising a semiconductor material of an opposite type as the substrate material, deposited in the substrate; k) a second dielectric deposited on the substrate material proximal to the second source and the second drain; l) a conductive material, deposited on the dielectric material to form a gate of a second MOSFET; m) a second capacitor having a first and second terminal, the first terminal of the second capacitor being coupled to the source of the first MOSFET and the second terminal of the second capacitor being coupled to the drain of the second MOSFET; and n) a second circuit, configured to reverse bias a second junction diode being between the drain of the second MOSFET and the bulk of the second MOSFET, the reverse bias being applied when the second MOSFET is off and the second circuit configured to short the first junction diode in the second MOSFET when the second MOSFET is on.