Patent ID: 7863878

Claim:
A push-pull voltage regulator comprising: (a) a voltage-up regulator, the voltage-up regulator having a plurality of inputs, an amplifier stage, and a biasing transistor, wherein the voltage-up regulator provides a reference voltage to an SRAM array; (b) a voltage-down regulator, wherein the voltage-down regulator controls removal of excess charge from the SRAM array; (c) a reference voltage source having an output; (d) an offset voltage source having an output coupled between the output of the reference voltage source and an input of the voltage-down regulator; (e) an output node of the push-pull voltage regulator coupled to the SRAM array through a voltage level switch; and (e) a NMOS drainage transistor, a gate terminal of the NMOS drainage transistor coupled to an output of the voltage-down regulator, a first output terminal of the NMOS drainage transistor coupled to an output node of the push-pull voltage regulator, a second output terminal of the NMOS drainage transistor coupled to ground, wherein the NMOS drainage transistor transfers excess charge from the SRAM array to ground.