Patent ID: 8427485

Claim:
An information processing device comprising: a first processing unit which asserts a first chip select signal or a second chip select signal in accordance with an address space to access; and a second processing unit accessible by the first processing unit by a first access method or a second access method, the second processing unit including: a control register accessible by the first processing unit, a data buffer accessible by the first processing unit, a host controller that has a plurality of interface circuits connected with a serial bus, and an arbiter that arbitrates transmission of read data or write data between the control register, the data buffer, and the host controller; wherein when asserting the first chip select signal, the first processing unit accesses the second processing unit by the first access method, when asserting the second chip select signal, the first processing unit accesses the second processing unit by the second access method, the data buffer buffers data transmitted via the serial bus connected with respective interface circuits included in the plural interface circuits; and serial/parallel conversion or parallel/serial conversion of the data transmitted via the serial bus connected with the interface circuits included in the plural interface circuits and arbitrated by the arbiter is performed.