Patent ID: 8280936

Claim:
An apparatus comprising: a memory to store eight bit floating point data structures, each of said eight bit floating point data structures including one sign bit, three exponent bits, and four fraction bits; and logic to populate exponent bits of an expanded data structure with multiple instances of an inversion of an exponent bit not having a value of zero in one of the eight bit floating point data structures unless a group of remaining bits of the one of eight bit floating point data structures all have a value of zero, and to populate the exponent bits of the expanded data structure with multiple instances of an inversion of an exponent bit having a value of zero in one of the eight bit floating point data structures unless the group of remaining bits of the one of eight bit floating point data structures all have the value of zero, the logic including: an inverter with an input of one of the three exponent bits of the eight bit floating point data structure; an OR gate with inputs of a remaining two of the three exponent bits and the four fraction bits of the eight bit floating point data structure; and an AND gate with inputs of an output of the inverter and an output of the OR gate.