Patent ID: 8194413

Claim:
A head substrate on which a plurality of driver ICs are to be mounted, the driver ICs selectively driving a plurality of driving elements which are formed on the head substrate in a row, the head substrate comprising: a plurality of external connection terminals including a plurality of contacts to which a clock signal and a logic power for the driver ICs are supplied; a plurality of first pad arrays and a plurality of second pad arrays wherein each of the first pad arrays includes a plurality of pads formed at one side in regions on which the driver ICs are respectively mounted and each of the second pad arrays includes a plurality of pads formed at another side in the regions on which the driver ICs are respectively mounted, the pads of each of the first pad arrays including output pads which are connected to terminals provided on each of the driver ICs and outputs driving signals to the driving elements, the pads of each of the second pad arrays including ground pads which are connected to terminals provided on each of the driver ICs and ground each of the driver ICs; and an input signal wiring pattern electrically connecting the external connection terminals with the pads in the first pad arrays and the second pad arrays; wherein the input signal wiring pattern includes a clock signal line connected to a plurality of clock pads for supplying the clock signal to the driver ICs and a logic power line connected to a plurality of logic power pads for supplying the logic power to the driver ICs; wherein an entirety of the clock signal line that connects the clock pads in adjacent regions on which adjacent driver ICs are mounted is disposed between the first pad arrays and the second pad arrays of the adjacent regions; and wherein an entirety of the logic power line that connects the logic power pads in adjacent regions on which adjacent driver ICs are mounted is disposed between the first pad arrays and the second pad arrays of the adjacent regions.