Patent ID: 7934081

Claim:
A program product comprising: a computer readable medium, and instructions stored on said medium which are effective, when executing on a computer system coupled to layered memory which has a plurality of layers of cache including a level one cache; to store standard cache lines in the level one cache; following an initial delay, to selectively store in interchangeable locations of the level one cache of the layered memory both standard cache lines and trace lines; to partition an instruction(s) address presented to the level one cache; to index the instruction(s) address into a tag array of the level one cache; to compare the instruction(s) address with the tag array a first time to determine whether a match is found; if a match is found on the first comparison, then to determine whether the match is a trace line; if the match is a trace line, to check the trace length parameter, access the required partitions, and forward the instruction(s) for execution by the central processor; if the match is a conventional cache line, then to check the target address, access the required partitions, force the leading instruction(s) to NOP, and forward the instruction(s) to execution by the central processor, then to build a new trace line, select a cache line to be replaced and replace the selected cache line with the new trace line; if no match is found on the first comparison, then masking the least significant bits of the instruction(s) address; and comparing the masked instruction(s) address with the tag array a second time to determine whether a match is found; if a match is found on the second comparison; then if the match is trace line, to declare a miss in the level one cache and fetch instruction(s) from a further level cache, forward the instruction(s) for execution by the central processor, build a new trace line, select a cache line to be replaced and replace the selected cache line; if the match is not a trace line, to check the trace address, access the required partitions, force the leading instruction(s) to NOP, and forward the instruction(s) for execution by the central processor; then to build a new trace line, select a cache line to be replaced and replace the selected cache line with the new trace line.