Patent ID: 8741770

Claim:
A method, comprising: defining a lateral position of an interlayer connection between a first metal layer and a second metal layer of a semiconductor device by a first mask; forming a second mask configured to define a trench in a dielectric material formed between said first and second metal layers, said trench corresponding to a metal line of said second metal layer, wherein defining said lateral position comprises forming said first mask above said dielectric material; and forming an opening for said interlayer connection and said trench in said dielectric material in a common etch process, wherein performing said common etch process comprises etching material of said dielectric material on the basis of said first and second masks, removing said first mask and continuing etching material of said dielectric material on the basis of said second mask, wherein said first mask is formed so as to expose an area of said dielectric material corresponding to said opening and covering the remaining portion of said dielectric material and wherein said first mask is comprised of a material having a reduced etch rate compared to said dielectric material during said common etch process so as to generate an etch lag in said remaining portion.