Patent ID: 7885101

Claim:
A method for multilevel reading of a phase change memory cell, comprising: selecting a bit line and a PCM cell coupled to the selected bit line; applying a first bias voltage (V BL , V 00 ) to the selected bit line; comparing a first read current (I RD00 ), that flows through the selected bit line in response to the first bias voltage (V BL , V 00 ), with a first reference current (I 00 ), wherein the first reference current (I 00 ) is such that the first read current (I RD00 ) is in a first relationship with the first reference current (I 00 ), when the selected PCM cell is in a reset state, and the first read current (I RD00 ) is in a second relationship with the first reference current (I 00 ) otherwise; determining whether the selected PCM cell is in the reset state, based on comparing the first read current (I RD00 ) with the first reference current (I 00 ); characterized by applying a second bias voltage (V BL , V 01 ) to the selected bit line if the selected PCM cell is not in the reset state, the second bias voltage (V BL , V 01 ) being greater than the first bias voltage (V BL , V 00 ).