Patent ID: 7281117

Claim:
A SIMD processor for executing SIMD instructions, the SIMD processor comprising: a first register operable to store data; a second register operable to store data; a flag storage unit operable to store a first flag; a decoding unit operable to decode an instruction; and an execution unit operable to execute the instruction based on a result of the decoding performed by the decoding unit, wherein the execution unit, when the decoding unit decodes an instruction for performing a SIMD operation, the instruction including operands specifying the first register and the second register, refers to the first flag stored in the flag storage unit, and performs the SIMD operation (i) only on the operand held in the first register when the first flag stored in the flag storage unit indicates a first status even in a case where the operands specify different registers for the first register and the second register, and (ii) on the operands held in the first register and the second register when the first flag indicates a second status.