Patent ID: 8707011

Claim:
A memory access system comprising: a processor; a first computing device-readable medium, communicatively coupled to the processor, and including a page table data structure including a page directory and one or more page tables, wherein the page directory includes addresses of the one or more page tables indexed by corresponding page directory index values; and a memory management unit, communicatively coupled to the first computing device-readable medium and the processor; wherein the memory management unit receives virtual addresses including a first set of bits that specify a page directory index, a second set of bit that specify a page table index, and a third set of bits that specify a byte index; wherein the memory management unit comprises a second computing device-readable medium including a translation lookaside buffer data structure; and wherein the translation lookaside buffer data structure comprises a set-associative translation lookaside buffer and a page size table; wherein the page size table includes a plurality of page directory index values to data including corresponding page size values; and wherein the set-associative translation lookaside buffer includes a plurality of mappings of virtual addresses to physical addresses arranged in one or more sets; wherein the memory management unit determines a given mapping in the page size table including a page directory index value matching the page directory index in a received virtual address, generates a set index utilizing the page size from the given mapping, retrieves the mappings of virtual addresses to physical address in the set corresponding to the generated set index, and compares the page directory index in the received virtual address to the retrieved mappings of virtual addresses to physical address to determine a physical address if a match between the page directory index in the received virtual address and a given retrieved mapping in the translation lookaside buffer is found.