Patent ID: 8860124

Claim:
A nonvolatile memory device comprising: a semiconductor substrate having a particular conductivity type; a plurality of semiconductor fins integral with the semiconductor substrate, the semiconductor fins including buried-channel regions doped for depletion mode operation having a first conductivity type opposite said particular conductivity type; a doped isolation region in the semiconductor fins having said particular conductivity type to separate the buried-channel regions from the semiconductor substrate, and wherein a first region of the semiconductor fin between the semiconductor substrate and the doped isolation region is more lightly doped than the doped isolation region; a storage structure on the plurality of semiconductor fins, including a tunnel insulating layer on the buried-channel regions of the semiconductor fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer; a plurality of word lines on the storage structure and crossing over the buried-channel regions of the semiconductor fins, whereby memory cells lie at cross-points of the word lines and the semiconductor fins; and a controller and biasing voltage supply circuits, adapted to execute an erase operation including applying voltage across the word line and the buried-channel regions.