Patent ID: 7587539

Claim:
An inter-integrated circuit (I 2 C) compatible apparatus comprising: a serial data pin that is configured to be coupled to a serial data line of an I 2 C bus; a serial clock pin that is configured to be coupled to a serial clock line of the I 2 C bus; a program input pin that receives encoding data; an addressing register having an address identifier code that is configured to be modified by the encoding data; logic coupled between the program input pin and the address register; a controller that is coupled to the serial data pin, the serial clock pin, and the logic, wherein the controller is configured to decode an unlock signal, and wherein the controller provides control signals to enable the logic to transmit the encoding data from the program input pin to the address register based on at least a portion of the decoded unlock signal, and wherein the controller is configured to provide DONE and BYPASS signals to the logic to select and de-select the apparatus based on at least a portion of the decoded unlock signal.