Patent ID: 7417895

Claim:
A NOR flash memory comprising: a plurality of main cells electrically connected to a bit line and arranged in a pattern; a plurality of main word lines, each electrically connected to a respective one of the plurality of main cells; a plurality of dummy cells electrically connected to the bit line and located adjacent to outermost ones of the plurality of main cells in the pattern; and a plurality of dummy word lines, each electrically connected to a respective one of the plurality of dummy cells, wherein at least some of the plurality of dummy word lines form a first group that is supplied with a first erase voltage and at least some other ones of the plurality of dummy word lines form a second group that is supplied with a second erase voltage that is different from the first erase voltage, wherein the first group of dummy word lines are electrically connected to first ones of the dummy cells that are adjacent to the outermost ones of the plurality of main cells, and the main word lines and the first group of dummy word lines are both supplied with the first erase voltage.