Patent ID: 7397881

Claim:
An erroneous phase lock detection circuit incorporated in a phase comparator that detects a phase difference between data and a clock, comprising: a first phase detection unit that detects a phase difference by measuring a difference between the leading edge of the data and the phase of the clock and transmits an average of phase differences; a second phase detection unit that detects a phase difference by measuring a difference between the trailing edge of the data and the phase of the clock and transmits an average of phase differences; an erroneous phase lock verification unit that, when the difference between the average phase difference sent from the first phase detection unit and the average phase difference sent from the second phase detection unit exceeds a predetermined range, verifies an erroneous phase lock; and a control unit that controls or reverses a clock to be transferred to the phase comparator, wherein when the erroneous phase lock verification unit verifies erroneous phase lock, the control unit reverses the clock.