Patent ID: 7769015

Claim:
A network adapter, comprising: an array of downstream packet processors, each downstream packet processor being configured to process an incoming data packet received from a network, and an upstream packet processor, the upstream packet processor being configured to process an outgoing data packet to be transmitted over the network, the upstream packet processor including: a direct memory access (DMA) engine configured to read the outgoing data packet from a memory of a processor and to transfer the read outgoing data packet; a packet buffer, and a reassembly state machine (RSM) configured to receive the transferred outgoing data packet from the processor as a plurality of out-of-order fragments and to store the received plurality of out-of-order fragments in the packet buffer in a correct sequential order as a reassembled outgoing data packet; wherein the DMA engine is further configured to transfer the read outgoing data packet such that the out-of-order fragments are received by the RSM in reverse order, relative to the order in which the outgoing data packet was stored in the memory of the processor.