Patent ID: 7310402

Claim:
A shift register circuit adapted to receive a first negative voltage level from a first voltage source, a second negative voltage level form a second voltage source, and a first clock signal, wherein the second negative voltage level is more negative than the first negative voltage level, the circuit comprising: an input terminal to receive an input pulse; an output terminal to provide an output pulse; a pull-up section having: an input end adapted to receive the first clock signal, a control end adapted to receive the input pulse, and an output end to provide the output pulse in response to the input pulse and the first clock signal; a first pull-down module including: a first pulse source adapted to receive the first clock signal, a second clock signal complementary to the first clock signal, and the second negative voltage level, a first output pull-down section operatively connected to the first pulse source and the first voltage source, and a first control-end pull-down section operatively connected to the first pulse source and the first voltage source; and a second pull-down module including: a second pulse source adapted to receive the first clock signal, the second clock signal and the second negative voltage level, a second output pull-down section operatively connected to the second pulse source and the first voltage source, wherein the first and second output pull-down sections are operated in a cooperative fashion such that a voltage level at the output end of the pull-up section is alternately pulled down to the first negative level in an output pull-down period, and a second control-end pull-down section operatively connected to the second pulse source and the first voltage source, wherein the first and second control-end pull-down sections are operated in a cooperative fashion such that a voltage level at the control end of the pull-up section is alternately pulled down to the first negative level in a control-end pull-down period.