Patent ID: 7986253

Claim:
A method for correcting decision errors in a successive approximation (SAR) analog to digital converter (ADC), the method comprising: controlling a digital to analog converter (DAC) with multiple sub-DACs of which one or more elements are shared by adjacent sub-DACs; obtaining Most Significant Bits (MSBs) from a corresponding sub-DAC and its shared DAC element in the adjacent sub-DAC in such a way that the shared DAC element provides an intended offset while MSB-segment DAC (sub-DAC for MSBs) decides MSBs by a following binary decision algorithm; making redundant decision after said obtaining the MSBs in such a way for a new DAC level to be a center of a determined analog range in a procedure for said obtaining MSBs by switching back the shared DAC element to the initial position (V CM ) and by re-arranging sub-DAC elements for said obtaining MSBs by using V CM as well as V REF and 0 as reference voltages; obtaining Least Significant Bits (LSBs) from a LSB-segment DAC (sub-DAC for LSBs) by a following binary decision SAR process; and adding digital codes obtained from a MSB-segment and a LSB-segment with code overlap to generate a final digital output code.