Patent ID: 7342568

Claim:
A shift register circuit having a series of cascading shift registers, comprising: a first transistor having a gate, a first source/drain, and a second source/drain, wherein the gate and the first source/drain of the first transistor is adapted to receive a output signal of a pre-stage shift register; a second transistor having a gate, a first source/drain, and a second source/drain, wherein the gate of the second transistor is coupled to the second source/drain of the first transistor, the first source/drain of the second transistor is coupled to a first clock signal and the second source/drain of the second transistor is coupled to a output terminal; a first pull-down module, coupled to the output terminal, for receiving the first clock signal, wherein the output terminal is coupled to a first voltage level when the output signal of the pre-stage shift register and the first clock signal is at a low voltage level; and a second pull-down module, coupled to the output terminal, for receiving a second clock signal, wherein the output terminal is coupled to the first voltage level when the output signal of the pre-stage shift register and a second clock signal is at the low voltage level.