Patent ID: 7864627

Claim:
A circuit configured to be mounted on a memory module so as to be electrically coupled to a first number of double-data-rate (DDR) memory devices arranged in a first number of ranks on the memory module, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and chip-select signals, the set of input signals corresponding to a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks, the circuit comprising: a logic element configurable to receive the set of input signals; a register; and a phase-lock loop circuit configurable to be operatively coupled to the first number of DDR memory devices, the logic element, and the register, wherein the circuit is configurable to generate a set of output signals in response to the set of input signals, the set of output signals corresponding to the first number of DDR memory devices arranged in the first number of ranks, wherein the circuit is configurable to further respond to the set of input signals from the computer system by generating and transmitting the set of output signals to the first number of DDR memory devices.