Patent ID: 8648290

Claim:
A data selection circuit, comprising: a delay section that includes delay units of n stages (n is a natural number equal to or more than 3) that are connected to each other, delays signals input to the delay units, and outputs the delayed signals from the delay units; a delay control section that controls delay amounts of the delay units; and an output section that performs a logical operation on signals output from i-th and j-th (i and j are natural numbers that are different from each other and equal to or more than 1 and equal to or less than n) delay units to generate a signal, which has a predetermined logical state at a predetermined timing, and outputs the generated signal to a k-th (k is a natural number equal to or more than 1 and equal to or less than m) first data selection pulse input terminal of a functional circuit having m (m is a natural number equal to or more than 2) first data selection pulse input terminals, wherein the delay section configures an annular delay circuit in which the delay units are connected in the form of a ring so that a signal output from an n-th stage delay unit is input to a first stage delay unit.