Patent ID: 7692969

Claim:
A semiconductor memory device comprising: a memory cell array having a block including a plurality of memory cell units formed in a well, each memory cell unit including a plurality of electrically rewritable nonvolatile memory cells connected in series, a first select gate transistor coupled to a bit line, a first dummy cell coupled to one end of the memory cell unit between the memory cell unit and the first select gate, and a second dummy cell coupled to another end of the memory cell unit; plural word lines each coupled to a corresponding one of the memory cells in he memory cell units; first dummy word line coupled to the first dummy cell; a second dummy word line coupled to the second dummy cell; a first selection gate line coupled to the first select gate transistor; and a control circuit configured to control a block erase operation that includes applying a first voltage to the word lines, the first dummy word line, and the second dummy word line, and applying to the well an erase voltage greater than the first voltage, and the control circuit is further configured to control a write operation that includes applying a write voltage to a word line of one memory cell in one of the memory cell units, applying a second voltage to word lines of at least two memory cells other than the one memory cell in the one of the memory cell units, and applying the second voltage to the first dummy word line and the second dummy word line, wherein at the write operation mode, the first and second dummy cells are configured to be out of use for data storage.