Patent ID: 7183592

Claim:
A semiconductor structure, comprising: a III–V substrate structure having an enhancement mode transistor device disposed in a first region of the structure and depletion mode transistor device disposed in a internally displaced second region of the structure, such structure having a channel layer for the depletion mode and enhancement mode transistor devices, such structure having; an enhancement mode transistor device InGaP etch stop Schottky contact layer disposed over the channel layer; an first layer disposed on the InGaP layer; a depletion mode transistor device etch stop layer disposed on the first layer a second layer disposed on the depletion mode transistor device etch stop layer; wherein; the depletion mode transistor device has a gate recess passing through the second layer, the depletion mode transistor device etch stop layer and terminating in the first layer; the enhancement mode transistor device has a gate recess passing through the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer; and the material of the first layer is different from InGaP; and wherein the depletion mode transistor device includes a gate electrode in Schottky contact with the first layer and the enhancement mode device includes a gate electrode in Schottky contact with the InGaP layer.