Patent ID: 7869262

Claim:
A static random access memory (SRAM) device comprising: a first inverter; a second inverter cross-coupled with the first inverter; a first pass gate transistor connecting the first inverter to a bit line through its source contact; and a second pass gate transistor connecting the second inverter to a complementary bit line through its source contact, wherein the first or second pass gate transistor has a layout structure where a first distance between its gate conductive layer and its source contact is purposefully designed to be substantially different from a second distance between its gate conductive layer and its drain contact for improving stability of the SRAM device, and wherein the first inverter further comprises a pull-up transistor whose source contact is connected to a power supply voltage (Vcc), the pull-up transistor having a layout structure where a third distance between its gate conductive layer and its source contact thereof is substantially the same as the second distance.