Patent ID: 8035206

Claim:
A process for fabricating an semiconductor assembly, comprising: forming a leadframe having plurality of electrical contacts associated therewith and having a portion thereof for receiving a semiconductor die thereon, at least one of said contacts of said leadframe having a thickness dimension associated therewith and having a recess-like tub formed therein, said tub having at least first and second opposed wall surfaces, one of said wall surfaces having a larger surface area than the other wall surface; attaching a semiconductor die to the said leadframe portion; inserting a first portion of an electrically conductive clip into said tub with solder-paste thereon or therein and connecting another portion of said electrically conductive clip to a portion of the die; and subjecting the leadframe and clip to a solder-reflow step whereby the solder paste within said tub liquefies to wet the larger surface area of said tub to create a net force pulling the first surface portion of said first portion of the electrically conductive clip toward and into substantial engagement with the larger surface area wall surface.