Patent ID: 8548111

Claim:
A sampler circuit operative to detect one or more transition edges of an input signal applied to the sampler circuit, comprising: a signal input; a sampling clock input; one or more serially-connected stages of sampler cells, each comprising: two parallel branches of series-connected clocked inverters, each clocked inverter operative to output an inverted representation of an input applied to the clocked inverter during one phase of a sampling clock, and further operative to render a high impedance at its output during the other phase of the sampling clock; and wherein the clocked inverters in each branch are alternatively clocked by the sampling clock and an inverted sampling clock; wherein each sampler cell is operative to sample a signal applied to the input of the sampler cell at a frequency determined by the sampling clock, and to output two parallel streams of samples at half the sampling clock frequency, the samples in each stream being de-multiplexed from the input signal; and a detector circuit operative to detect, from the outputs of the last sampler cells in the serially-connected stages of sampler cells, one or more transition edges of a signal applied to the sampler cell input.