Patent ID: 8637987

Claim:
A semiconductor assembly, comprising: a semiconductor die having a bond site in a connection region; a substrate carrying the semiconductor die, the substrate including— a first non-conductive core, a second non-conductive core, a first routing level disposed between the first and second non-conductive cores, a second routing level spaced apart from first routing level by the second non-conductive core, and a conductive via between the first and second routing levels, the conductive via extending through the second non-conductive core and having a first end proximate the first routing level and a second end proximate the second routing level, wherein— the first routing level includes a terminal and a first trace electrically connected between the terminal and the first end of the conductive via, the second routing level includes a second trace electrically connected between the second end of the conductive via and a ball site, the first non-conductive core is stacked relative to the second non-conductive core, and the first and second non-conductive cores have the same composition of material; and a wirebond extending between the bond site in the connection region of the semiconductor die and the terminal of the first routing level.