Patent ID: 7260688

Claim:
Apparatus for controlling access to memory circuitry among a plurality of bus interfaces of a data processing system, comprising: a plurality of ports respectively coupled to said plurality of bus interfaces; arbitration logic, in communication with said plurality of ports, for arbitrating access to said memory circuitry among said plurality of bus interfaces on a time-shared basis; a data bus and an address bus, each of said data bus and said address bus coupled to said plurality of ports; data path logic configured to communicate signals between said data bus and said memory circuitry; address path logic configured to communicate signals between said address bus and said memory circuitry; a control bus coupled to said plurality of ports and said arbitration logic; and control logic coupled to said arbitration logic and configured to couple signals to said memory circuitry; and wherein said data path logic comprises: a read interface having a pair of first-in-first-out (FIFO) memories for each of said plurality of ports; a write interface having a pair of FIFO memories for each of said plurality of ports; a multiplexer configured to select one pair of FIFO memories in said write interface; and a first memory interface configured to communicate data between a data interface of said memory circuitry and each of said read interface and said selected pair of FIFO memories in said write interface; and a second memory interface configured to communicate data between said selected pair of FIFO memories and a data mask interface of said memory circuitry.