Patent ID: 7159169

Claim:
An apparatus comprising: an instruction decoder; at least one control register coupled to the instruction decoder; an add-compare-select (ACS) engine coupled to the at least one control register, said ACS engine including; a plurality of ACS units to perform ACS operations; a branch metric register coupled to the ACS units to supply branch metric data to the ACS units; and a plurality of accumulators coupled to the ACS units to store results of the ACS operations performed by the ACS units; and a memory coupled to the ACS units, to the branch metric register, and to the accumulators; wherein the instruction decoder is operative to control the ACS engine to perform a first Viterbi decoding mode in response to the instruction decoder receiving a first instruction, the instruction decoder is further operative to control the ACS engine to perform a second Viterbi decoding mode different from the first Viterbi decoding mode in response to the instruction decoder receiving a second instruction, and the instruction decoder is further operative to control the ACS engine to perform turbo decoding in response to the instruction decoder receiving a third instruction; and wherein in the first Viterbi decoding mode path metrics are updated from the accumulators and in the second Viterbi decoding mode path metrics are updated from the memory.