Patent ID: 8765604

Claim:
A method of fabricating an interconnection structure of an integrated circuit, comprising: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; exposing a first connection surface of the first conductive element by forming an opening in the first etch stop layer; after forming the opening in the first etch stop layer, depositing a second dielectric layer above the etch stop layer and directly on the first connection surface of the first conductive element; forming a hole in the second dielectric layer by etching the second dielectric layer, the hole exposing at least a portion of the first connection surface and a portion of the first etch stop layer; and forming a second conductive element by filling the hole with a conductive material, the second conductive element being in electrical contact with the first conductive element and the first etch stop layer.