Patent ID: 7745921

Claim:
A semiconductor device comprising: (a) a package substrate comprising an upper surface, a back surface opposing to the upper surface, a plurality of bonding pads formed on the upper surface, and a plurality of lands formed on the back surface; wherein the upper surface includes pairs of first edges, and pairs of second edges intersecting with the first edges; and wherein the plurality of bonding pads are arranged along the first and second edges; (b) a first semiconductor chip mounted over the upper surface of the package substrate; wherein the first semiconductor chip comprises an analog circuit, a first main surface, a first rear surface opposing to the first main surface, and a plurality of first bonding pads formed on the first main surface; wherein the plurality of first bonding pads of the first semiconductor chip includes a plurality of bonding pads for analog signals electrically connecting with the analog circuit; wherein the first main surface includes pairs of third edges, and pairs of fourth edges intersecting with the third edges; wherein the plurality of bonding pads for analog signals are arranged along one of the third edges; and wherein the first semiconductor chip is mounted over the upper surface of the package substrate such that the fourth edges of the first semiconductor chip are arranged next to the second edges of the package substrate; (c) a second semiconductor chip mounted over the first semiconductor chip; wherein the second semiconductor chip comprises an output buffer circuit, a second main surface, a second rear surface opposing to the second main surface, and a plurality of second bonding pads formed on the second main surface; wherein the plurality of second bonding pads of the second semiconductor chip includes a plurality of bonding pads for high-voltage signals; wherein the second main surface includes pairs of fifth edges, and pairs of sixth edges intersecting with the fifth edges; wherein the plurality of bonding pads for high-voltage signals are arranged along one of the sixth edges; and wherein the second semiconductor chip is mounted over the first semiconductor chip such that the sixth edges of the second semiconductor chip are arranged next to the fourth edges of the first semiconductor chip; (d) a plurality of first bonding wires electrically connecting the plurality of first bonding pads of the first semiconductor chip with the plurality of bonding pads of the package substrate; (e) a plurality of second bonding wires electrically connecting the plurality of second bonding pads of the second semiconductor chip with the plurality of bonding pads of the package substrate; (f) sealing resin for sealing the first semiconductor chip, the second semiconductor chip, the plurality of first bonding wires and the plurality of second bonding wires; and (g) a plurality of external terminals formed over the plurality of lands, respectively.