Patent ID: 8333842

Claim:
A wafer pedestal of a semiconductor apparatus, the wafer pedestal capable of supporting a substrate, the wafer pedestal comprising: an upper surface, the upper surface having purge openings configured to allow a flow of a purge gas and chucking openings configured to allow chucking of the substrate over the pedestal; a sealing band disposed on the upper surface and configured to contact the substrate, wherein the sealing band is disposed between the purge openings and the chucking openings; and a recessed region surrounding the sealing band, wherein the purge openings are disposed within the recessed region, and the recessed region is configured to provide a gap between the upper surface of the pedestal and the substrate such that when the substrate is supported by the wafer pedestal, the sealing band contacts the substrate inward from an edge of the substrate and the edge of the substrate extends over the recessed region.