Patent ID: 8614661

Claim:
A shift register unit, comprising: a first thin film transistor, the drain of which is connected to a first clock signal input terminal and the source of which is connected to a first signal output terminal; a second thin film transistor, the drain of which is connected to the first signal output terminal, the gate of which is connected to a reset signal input terminal, and the source of which is connected to a low level signal input terminal; a third thin film transistor, the drain of which is connected to the first clock signal input terminal, the gate of which is connected to the gate of the first thin film transistor, and the source of which is connected to a second signal output terminal; a fourth thin film transistor, the drain of which is connected to the drain of the third thin film transistor, the gate of which is connected to a second clock signal input terminal, and the source of which is connected to the low level signal input terminal; a fifth thin film transistor, the gate and the drain of which are both connected to a start signal input terminal, and the source of which is connected to the gate of the first thin film transistor; and a capacitor, two terminals of which are connected to the gate and the source of the first thin film transistor respectively; the first clock signal input terminal is used for inputting a clock signal; the second clock signal input terminal is used for inputting a clock signal inverted with respect to the signal input by the first clock signal; the reset signal input terminal is used for inputting a reset signal; the start signal input terminal is used for inputting a start signal; the low level signal input terminal is used for inputting a low level signal; the first signal output terminal is used for outputting a gate driving signal; and the second signal output terminal is used for providing a control signal for the next neighboring shift register unit.