Patent ID: 8116153

Claim:
A Read Only Memory (ROM) device operating at a supply voltage, comprising: a ROM array including a plurality of bit line columns connected to a plurality of bit lines, each of the plurality of bit line columns comprising a plurality of bit cells, wherein a gate terminal of each of the plurality of bit cells is connected to a plurality of word lines, and wherein the plurality of word lines operate at a level shifted voltage that is higher than the supply voltage; a row address decoder connected to the ROM array, wherein for a read operation, the row address decoder selects at least one of the plurality of word lines; a column address decoder connected to the plurality of bit lines, wherein for the read operation, the column address decoder generates a column address signal for enabling at least one of the plurality of bit lines, and wherein the column address signal operates at the level shifted voltage; one or more sense amplifiers connected to the plurality of bit lines for sensing the plurality of bit lines; one or more column multiplexers connected to the plurality of bit line columns, wherein the one or more column multiplexers comprise: a plurality of transmission gates connected to the plurality of bit lines for transferring data stored in the plurality of bit cells to the one or more sense amplifiers, wherein the column address signal is supplied to a gate terminal of an n-channel metal oxide semiconductor field effect transistor (n-MOSFET) of the plurality of transmission gates; an inverter circuit for receiving the column address signal and generating a pull-down bit line signal to discharge the at least one enabled bit line, wherein the pull-down bit line signal operates at the level shifted voltage; and a control circuit connected to the row address decoder, the one or more column multiplexers, and the one or more sense amplifiers, wherein the control circuit generates a pull-up bit line signal for pre-charging the plurality of bit lines, wherein the pull-up bit line signal operates at the level shifted voltage, and generates a sense amplifier enable signal for enabling the one or more sense amplifiers, wherein the sense amplifier enable signal operates at the level shifted voltage, and the one or more sense amplifiers perform the read operation.