Patent ID: 6850535

Claim:
A system for transferring data from a peripheral device to a CPU in a telecommunications hub operating under UTOPIA protocol, comprising: a data buffer having data inputs coupled to data outputs of the peripheral device, having data outputs connected to an UTOPIA read data bus and having a control input for receiving a output enable signal; address detection logic comprising a register for storing the address of the peripheral device, an input for receiving a read address from an UTOPIA address bus, and an output for providing an indication of when the UTOPIA bus address matches the stored address; a first DFF having a data input coupled to the address detection logic output, a clock input coupled to an UTOPIA bus clock line, and an output indicating the state of the address detection logic output during the preceding clock cycle; a second DFF having a data input coupled to an UTOPIA bus receive enable line, a clock input coupled to the UTOPIA bus clock line, and an output indicating the state of the UTOPIA bus receive enable line during the preceding clock cycle; and a first AND gate, having inputs coupled to the outputs of the first DFF and second DFF, said inputs to a read cell available signal output of the peripheral device, said inputs and to an UTOPIA bus read enable line and having an output coupled to the data buffer control input.