Patent ID: 8497207

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a plurality of metal contacts that pass through a first interlayer insulating layer that is formed on a substrate, and forming a plurality of landing pads on upper surfaces of the plurality of metal contacts by electroless plating; forming a single etching prevention layer directly on the plurality of landing pads and the first interlayer insulating layer; forming a second interlayer insulating layer on the etching prevention layer; forming a hole in the second interlayer insulating layer and the etching prevention layer that exposes an upper surface of one of the plurality of landing pads; and forming a plug by burying the hole using a damascene process; wherein the plurality of the metal contacts are arranged on the substrate in a zigzag arrangement; and wherein forming the hole comprises forming the hole, which surrounds a lower portion of the plug, using a blocking SiN hole (BSH) scheme.