Patent ID: 8544013

Claim:
A system comprising: a processor; one or more memory storage units; software code stored in the one or more memory storage units, where the software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with a plurality of process threads, where each of the plurality of adaptive partitions has a corresponding processor budget and the process threads comprise: a mutex holding thread associated with a first adaptive partition of the plurality of adaptive partitions, where the mutex holding thread is configured to gain exclusive access to a mutex object, a mutex waiting thread associated with a second adaptive partition of the plurality of adaptive partitions, where the mutex waiting thread waits for access to the mutex object when the mutex object is held by the mutex holding thread, where the software code further comprises a scheduling system executable by the processor for selectively allocating the processor to run the process threads based, at least in part, on the processor budget of the associated adaptive partitions, and where the scheduling system bills processor allocation used to run the mutex holding thread to the processor budget of the second adaptive partition when the processor budget of the first adaptive partition has been exhausted.