Patent ID: 7870317

Claim:
A storage processor, comprising: a target interface; an initiator interface; and a controller connected to the target interface and to the initiator interface to control operations of the respective interfaces, the controller being operative: to control the target interface to exchange messages with an initiator and to control the initiator interface to exchange messages with at least one target of a plurality of targets, to negotiate one or more operational parameters with the initiator and with the at least one target, the one or more operational parameters indicating at least one data segment size and at least one data burst size acceptable to the at least one target, wherein the at least one target comprises a storage device operable to receive and respond to an input/output command, and wherein a negotiation comprises the initiator proposing a value for the one or more operational parameters and the at least one target proposing a different value for the one or more operational parameters; and to control the target interface to accept a first input/output command directed to a virtual storage device and to control the initiator interface to issue a corresponding second input/output command to the at least one target, each of the first and second input/output commands conforming to the one or more negotiated operational parameters, wherein the plurality of targets is presented as the virtual storage device, and wherein the controller requests no more data from the initiator than can be transmitted to a target of the plurality of targets that has a smallest outstanding unsatisfied data request; the target interface being operative to receive, from the initiator, data segments corresponding to the first input/output command; and the initiator interface being operative to transmit, to the at least one target, each received data segment corresponding to the second input/output command, each received data segment being transmitted to the at least one target as the data segment is received over the target interface, without first buffering in the storage processor, a plurality of received data segments corresponding to the first input/output command.