Patent ID: 7675790

Claim:
A packaged semiconductor device that includes a low voltage memory circuit and a plurality of input pins, the input pins not including pins dedicated to a high-voltage stress test function, the packaged semiconductor device comprising: an operating voltage input pin for receiving an operating voltage; a primary function circuit electronically coupled to the operating voltage input pin, the primary function circuit operating at a normal operating voltage range; a secondary function circuit electronically coupled to the operating voltage input pin, the secondary function circuit for performing a high-voltage stress test on the low voltage memory circuit; a semaphore signal input pin electronically coupled to the primary function circuit for receiving a signal voltage; a comparator circuit electronically coupled to the semaphore signal input pin for comparing the signal voltage to the operating voltage, the comparator circuit enabled to disable the primary function circuit and to cause the secondary function circuit to perform the high-voltage stress test on the low voltage memory circuit as long as the signal voltage is greater than the operating voltage; and a voltage regulator electronically coupled to the operating voltage input pin for providing a voltage lower than the operating voltage to the low voltage memory circuit.