Patent ID: 8904254

Claim:
A combo dynamic flop with scan circuit, driven by a source clock signal, comprising: a flip-flop circuit comprising: a dynamic latch circuit comprising: a dynamic latch storage node, and a static latch circuit comprising: a static storage node, and wherein the static latch is operatively driven from the dynamic latch, wherein a scan clock provides a control signal for writing to the static storage node, wherein the dynamic latch and static latch are written simultaneously, and wherein the dynamic latch is precharged while scan data is preserved in the static latch until a next clock cycle, a scan control circuit comprising: a scan slave feed-forward circuit providing a control signal for writing scan data to the static storage node, a scan latch circuit comprising: a scan feed-back circuit comprising a scan storage node, a scan feed-forward circuit operatively driven from the static latch, wherein the scan feed-forward circuit provides control signal for writing to the scan storage node, and a scan driver, with a scan output port, operatively driven by the scan feed-back circuit, and an output buffer circuit comprising: a dynamic latch driver, with a dynamic latch output port, operatively driven from the dynamic latch, and a static driver, with a static output port, operatively driven from the static latch.