Patent ID: 6864715

Claim:
An alignment circuit for aligning a data signal with a clock signal, the alignment circuit comprising: a. a clock input node receiving the clock signal; b. a data input node receiving the data signal; c. data-windowing circuit comprising: an adjustable first delay circuit having a first delay-circuit input terminal connected to the data input node and a first delay-circuit output terminal; and ii. an adjustable second delay circuit having a second delay-circuit input terminal connected to the first delay-circuit output terminal and a second delay-circuit output terminal; d. a first sequential storage element having a first storage-element input terminal connected to the first delay-circuit output terminal, a first clock terminal connected to the clock input node, and a first synchronous output terminal; and e. a second sequential storage element having a second storage-element input terminal connected to the second delay-circuit output terminal, a second clock terminal connected to the clock input terminal; and a second synchronous output terminal.