Patent ID: 8832362

Claim:
A memory system comprising: a board; a package for a memory mounted on the board; a first nonvolatile memory in the package; a second nonvolatile memory in the package; a first signal line electrically connected to the first nonvolatile memory; a second signal line electrically connected to the second nonvolatile memory; an interface configured to communicate with a host; a first controller configured to control power applied to the memory system which includes the first nonvolatile memory and the second nonvolatile memory; and a second controller configured to control a load capacity of the first nonvolatile memory and the second nonvolatile memory according to a command from the host by controlling the first signal line and the second signal line, wherein the second controller controls the load capacity of the first nonvolatile memory to be increased and the load capacity of the second nonvolatile memory to be reduced, when the first nonvolatile memory is accessed, while the power controlled by the first controller is applied, and the second controller controls the load capacity of the first nonvolatile memory to be reduced and the load capacity of the second nonvolatile memory to be increased, when the second nonvolatile memory is accessed while the power controlled by the first controller is applied.