Patent ID: 8639946

Claim:
A system comprising: a processor; a volatile memory accessible to the processor; a first nonvolatile memory accessible to the processor, the first nonvolatile memory including: a first portion of memory that is protected and that is accessible during power up of the system when a shield bit indicates an unshielded mode of operation, but, after the first portion of memory is accessed and before execution of program code by the processor, the first portion of memory is inaccessible when the shield bit indicates a shielded mode of operation; and a second portion of memory that is unprotected and that is readable regardless of a value of the shield bit; a second nonvolatile memory, the second nonvolatile memory including the program code to be transferred to the volatile memory; and external test interface protection logic responsive to an external test clock input, wherein the shield bit is set to the shielded mode of operation after detection that a number of cycles of the external test clock input exceeds a threshold; wherein a key set is stored within the first portion of memory, the key set comprising an authentication key to authenticate the program code and a decryption key to decrypt the program code when the program code is encrypted.