Patent ID: 6975152

Claim:
A device, comprising: a master portion of a flip-flop operable to latch at least one of an input signal and an inverted input signal; and a slave portion of the flip flop operable to latch at least one of the signal latched by the master portion and an inverted signal latched by the master portion in response to a first phase of a clock signal, the slave portion also operable to be reset in response to a second phase of the clock signal, the slave portion comprising; a NAND gate operable to generate a value associated with an output signal in response to the first phase and to reset the value in response to the second phase; a first inverter operable to invert the clock signal and supply the inverted clock signal to the NAND gate; a second inverter operable to invert the signal latched by the master portion and provide the inverted signal to the NAND gate; a third inverter operable to invert the value generated by the NAND gate and produce the output signal; and a transmission gate coupled to an output of the NAND gate and an input of the third inverter.