Patent ID: 6868518

Claim:
A circuit for decoding input data, comprising: a decoder implementing the maximum a posteriori probability decoding algorithm, said decoder using a first table for computing the function log(e x 1 +e x 2 ) or ln(e x 1 +e x 2 ) where x 1 and x 2 are first and second argument values, each derived from said input data, said first table having N entries and storing a first data field including a plurality of table index values and a second data field including a plurality of computed table values corresponding to said plurality of table index values, said plurality of table index values are selectod from a predefined range of |x 1 −x 2 | argument values. said table index values of said first data field arc separated by one or more intervals, and said plurality of computed table values are computed based on the equation log(1+e −|x 1 −x 2 | ) or 1n(1+e −|x 1 −x 2 | ) for each of said |x 1 −x 2 | argument values selected for said table index values; and said decoder using a second table having κN entries and storing a first data field including a plurality of table index values and a second data field including a plurality of computed table values corresponding to said plurality of table index values; wherein said plurality of table index values of said second table are selected from said predefined range of |x 1 −x 2 | argument values and have a second interval derived from a first interval selected from said one or more intervals of said first table, said second interval being a value represented by an n-bit binary number; and said plurality of computed table values of said second table are derived from said computed table values of said first table, and wherein said second table is addressed by using address bits in an index value z and said address bits are data bits more significant than the (n-1)th bit of said index value z.