Patent ID: 8074131

Claim:
An integrated circuit to support debug and validation activity comprising: a core area comprising a plurality of processing cores, a graphics processing unit coupled to the plurality of processing cores, and an uncore area coupled to the core area and the graphics processing unit, wherein the uncore area further comprises a generic debug external connection logic, wherein the generic debug external connection logic is to capture internal signals that occur between the plurality of cores, between the core area and the uncore area, and within the uncore area, wherein the generic debug external connection logic is coupled to a port, wherein the generic debug external logic is to transfer the internal signals to external analysis tools through the port, wherein the generic debug external connection logic is coupled to an end point of a first interface structure provisioned to transfer signals between the core area, the graphics processing unit, and the uncore area, wherein the port is provisioned on a surface of a packing, which encloses the integrated circuit, wherein the integrated circuit does not expose buses provisioned between the uncore area and peripherals to capture the internal signals, wherein the integrated circuit further comprises one or more interface agents, wherein the one or more interface agents are to transfer the internal signals occurring on one or more second interface structures provisioned between the plurality of cores and the first interface structure to the generic debug external connection logic, wherein the internal signals comprise signals transferred on the first interface structure, wherein the internal signals comprise power management sequences generated by a power management block.