Patent ID: 7135353

Claim:
A method for manufacturing a semiconductor package, the method comprising: providing a first wafer and a second wafer, the first wafer having a first adhesive layer on a bottom surface thereof and including a plurality of first semiconductor chips, the second wafer having a second adhesive layer on a bottom surface thereof and including a plurality of second semiconductor chips; loading the first wafer on a first table and the second wafer on a second table; picking up a first semiconductor chip and attaching the first semiconductor chip onto a second semiconductor chip; repeating the attachment of the first semiconductor chips to form a plurality of multi-chips having a vertical stack configuration; unloading a first remainder of the first wafer from the first table and loading a substrate panel including a plurality of substrates on the first table; picking up the multi-chip and die-attaching the multi-chip on the substrate; wire-bonding the multi-chip to the substrate for interconnection, forming solder balls on the bottom surface of the substrate and singulating the substrate panel.