Patent ID: 7310276

Claim:
A memory device data path, comprising: a storage device storing data; a first bus coupled to the storage device; a second bus coupled to the storage device; a first set of parallel-to-serial converters coupled to the first bus, each of the parallel-to-serial converters in the first set having input terminals coupled to receive respective data bits from the first bus, the parallel-to-serial converters in the first set having respective serial output terminals coupled to respective data bus terminals in a first set, each of the parallel-to-serial converters in the first set being operable in a first operating mode to receive from the storage device through the first bus at least one set of parallel data each containing a first plurality of the data bits and apply a burst containing the received data bits to the respective data bus terminal in the first set; and a second set of parallel-to-serial converters coupled to the first and second buses, each of the parallel-to-serial converters in the second set having input terminals coupled to receive respective data bits from the first bus and respective data bits from the second bus, the parallel-to-serial converters in the second set having respective serial output terminals coupled to respective data bus terminals in a second set, each of the parallel-to-serial converters in the second set being operable in the first operating mode to receive from the storage device through the second bus at least one set of parallel data each containing the first plurality of the data bits and apply a burst containing the received data bits to the respective data bus terminal in the second set, the parallel-to-serial converters in the second set being operable in a second operating mode to receive from the storage device through the first and second buses at least one set of parallel data each containing a second plurality of the data bits and to apply a burst containing the received data bits to the respective data bus terminal in the second set, the number of data bits in the second plurality being different from the number of data bits in the first plurality.