Patent ID: 8576939

Claim:
A method for processing a communication signal comprising a first signal segment that represents a first symbol and that immediately precedes a second signal segment representing a second symbol, the method comprising: processing the first signal segment with a front end of a flash converter that comprises a plurality of comparators connected to a corresponding plurality of references, each comparator producing a respective output signal, wherein the flash converter comprises the front end coupled to a logic circuit and is modified to form a slicer by replacing the logic circuit with a summation node; setting a signal to a discrete intensity in response to performing a signal summation of the respective output signals with the summation node; delaying and scaling the signal; and applying the delayed and scaled signal to the second signal segment to correct interference on the second signal segment, wherein the front end of the flash converter coupled to the summation node form the slicer having a propagation delay that is less than or equal to a symbol period of the communication signal.