Patent ID: 7327627

Claim:
A semiconductor memory comprising: three or more memory blocks each of which has dynamic memory cells and which are arranged in one direction and operate at different timings from each other; control circuits each of which is arranged between memory blocks adjacent to each other and shared by the adjacent memory blocks and operates in synchronization with an operation of one of the adjacent memory blocks; control circuits arranged respectively on outer sides of said memory blocks arranged at both ends of the one direction, and operating in synchronization with operations of the respective memory blocks; switching circuits each connecting each of said control circuits to an adjacent memory block; and an operation control circuit which constantly keeps, during a partial refresh mode, the switching circuits ON which are corresponding to the control circuits positioned on the outer sides of the memory blocks arranged at the both ends, the partial refresh mode being to retain data of at least one of said memory blocks, wherein a partial area is set to include said memory blocks arranged at the both ends, the partial area representing the memory block for which a refresh operation is executed during said partial refresh mode.