Patent ID: 6989696

Claim:
An integrated circuit, comprising: (a) a clock divider circuit comprising: (i) a counter operatively configured to generate a plurality of first signals from a second signal, each one of said plurality of first signals having a first phase and said second signal having a second phase; and (ii) a mux in electrical communication with said counter and operatively configured to output a selected one of said plurality of first signals; (b) a phase detector operatively configured to detect an offset between said first phase of said selected one of said plurality of first signals and said second phase of said second signal and generate a third signal representing said offset; and (c) a clock mesh having a mesh delay and delay circuitry, wherein said selected one of said plurality of first signals propagates to said phase detector through said clock mesh and said delay circuitry is operatively configured to simulate said mesh delay, said second signal propagating to said phase detector through said delay circuitry.