Patent ID: 8278974

Claim:
A divider circuit comprising: a shift register configured to output 2X pulse signals in accordance with a first clock signal and a second clock signal, wherein X is a natural number greater than or equal to 2; and a divided signal output circuit configured to output a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals, wherein the divided signal output circuit comprises: X first transistors each having a source, a drain, and a gate, wherein the shift register is configured to separately supply the respective gates of the X first transistors with the first to X-th pulse signals among the 2X pulse signals, and wherein the X first transistors are configured to control whether voltage of a signal to be the third clock signal is set to first voltage; and X second transistors each having a source, a drain, and a gate, wherein the shift register is configured to separately supply the respective gates of the X second transistors with (X+1)-th to 2X-th pulse signals among the 2X pulse signals, and wherein the X second transistors are configured to control whether voltage of a signal to be the third clock signal is set to second voltage.