Patent ID: 8427894

Claim:
A method for implementing single bit redundancy with a dynamic Static Random Access Memory (SRAM) circuit and any bit decode comprising: providing a series of merged bit column select and redundancy steering multiplexers; each of said merged bit column select and redundancy steering multiplexers having a plurality of inputs and one output; connecting each of a plurality of bitline columns and a pair of redundancy columns to a respective input of said series of said merged bit column select and redundancy steering multiplexers with an adjacent pair of bitline columns connected to a respective adjacent pair of inputs of a next adjacent one of said series of merged bit column select and redundancy steering multiplexers; applying a respective select signal input to control each of said merged bit column select and redundancy steering multiplexers; applying a redundancy steering signal and a respective one-hot bit select signal to select signal generation logic, generating the respective select signal input.