Patent ID: 8912822

Claim:
A semiconductor integrated circuit, comprising: a plurality of input wires comprising: a first input wire; and a second input wire; a first look-up table (LUT) comprising: a first memory group comprising a plurality of first memories; a first output terminal; and a first multiplexer comprising a first number of first switches connected to the first input wire and a second number of second switches connected to the second input wire, the second number being less than the first number, the first multiplexer being configured to transfer information from one of the first memories to the first output terminal according to signals input from the input wires; and a second LUT comprising: a second memory group comprising a plurality of second memories; a second output terminal; and a second multiplexer comprising a third number of third switches connected to the second input wire and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second multiplexer being configured to transfer information from one of the second memories to the second output terminal according to the signals input from the input wires.