Patent ID: 8811061

Claim:
A memory device, comprising: a substrate; a plurality of first electrodes, a second electrode, and a third electrode that are stacked above the substrate; a variable resistance layer formed in an island shape between the first electrodes and the second electrode; and a non-conductive layer formed between the second electrode and the third electrode, wherein the variable resistance layer includes a high-concentration variable resistance layer located closer to the first electrodes, and a low-concentration variable resistance layer located closer to the second electrode, the low-concentration variable resistance layer having an oxygen concentration lower than an oxygen concentration of the high-concentration variable resistance layer, the second electrode, the non-conductive layer, and the third electrode comprise a diode, the second electrode, the third electrode, the variable resistance layer, and the non-conductive layer are formed across the first electrodes, the first electrodes, the variable resistance layer, and the second electrode comprise a plurality of variable resistance elements, a total number of which is equal to a total number of the first electrodes, and each of the variable resistance elements has a resistance value that independently changes according to a voltage applied between the first electrodes and the second electrode.