Patent ID: 8305879

Claim:
A peripheral component switch assembly having automatic link failover, comprising: first and second peripheral component switches, each of the first and second switches having first and second primary ports and a plurality of secondary ports; a bus line connecting the second primary port of the first switch with the first primary port of the second switch; wherein the switch assembly has a normal mode, in which each switch routes data through the switch from one or more of the primary ports of the switch to the secondary ports of the switch, and a failover mode, in which a failover path is defined and data are routed from the second primary port of the first switch to the first primary port of the second switch and then to one of the secondary ports of the second switch; and wherein the switch assembly changes from the normal mode to the failover mode in response to a detection of a predefined fail condition; wherein, in use, the first and second switches send data packets to a processor node; and wherein, when said predefined fail condition is detected, said second switch sends a group of the data packets to the first switch, over the failover path, for sending to the processor node.