Patent ID: 8519470

Claim:
A semiconductor chip comprising: a semiconductor substrate; a passivation film disposed on the semiconductor substrate; a plurality of pseudo bumps disposed on the passivation film; an interconnect disposed in the semiconductor substrate; at least one pad electrically connected to the interconnect and exposed through at least one opening of the passivation film; and at least one through-bump disposed to be electrically connected to the pad through the at least one opening of the passivation film, wherein the at least one through-bump is directly connected to at least one of the pseudo bumps, wherein the plurality of pseudo bumps are directly connected to each other to form at least one redistribution interconnect, wherein the plurality of pseudo bumps each comprises: a first under bump metallurgy (UBM) layer disposed on the passivation film; and a first solder layer disposed on the first UBM layer, wherein a plurality of first UBM layers have intervals therebetween, such that a plurality of first solder layers are disposed to cover the plurality of first UBM layers and the intervals therebetween to directly connect adjacent ones among the plurality of first solder layers, wherein the at least one through-bump each comprises a second UBM layer disposed on the at least one pad, and a second solder layer disposed on the second UBM layer, and the second UBM layer is disposed separated from the plurality of first UBM layers, and the second solder layer is directly connected to at least one of the plurality of first solder layers.