Patent ID: 7172981

Claim:
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) linking an internal space of a sealed type semiconductor-accommodating container which accommodates and is filled with a plurality of wafers grounded, to a local clean chamber of a first wafer treatment apparatus with cleanliness kept in internal space of said local clean chamber; (b) transporting said wafers accommodated in said sealed type semiconductor-accommodating container under said linking state by means of a transport mechanism disposed in said local clean chamber through said local clean chamber, and thereby accommodating the wafers in a wafer treatment section of said first wafer treatment apparatus through a load lock and unload lock mechanism disposed between said wafer treatment section and said local clean chamber; (c) performing a first treatment to said wafers accommodated in said wafer treatment section; (d) after step (c), transporting treated wafers by said transport mechanism through said load lock and unload lock mechanism from said wafer treatment section, and thereby accommodating said treated wafers grounded in said sealed type semiconductor-accommodating container through said local clean chamber; (e) eliminating static charge of said treated wafers in step (d); and (f) releasing the linking state between said sealed type semiconductor-accommodating container and said local clean chamber after said step (d), and thereby returning said sealed type semiconductor-accommodating container to a sealed state.