Patent ID: 7002191

Claim:
A semiconductor comprising: a plurality of first building blocks arranged in one or more first rows, each of said first building blocks having a first layer, a second layer and a third layer, said first layer having a first metal portion and a second metal portion, said first metal portion being larger than said second metal portion; and a plurality of second building blocks arranged in one or more second rows, each of said second building blocks having a first layer, a second layer and a third layer, said first layer of said second building blocks having a first metal portion and a second metal portion, said first metal portion being larger than said second metal portion, wherein (i) said first metal portion and said second metal portion in said first layer of said second building blocks are arranged complementary to said first metal portion and said second metal portion in said first layer of said first building blocks, (ii) said one or more second rows are interleaved with said one or more first rows and (iii) said first building blocks and said second building blocks each provide a single segment of horizontal routing and a single segment of vertical routing.