Patent ID: 7139789

Claim:
A circuit for adding a first binary number to a second binary number and conditionally generating an incremented sum of the first and second binary numbers, the circuit comprising: a carry chain of logic circuits for producing two sets of summation carry terms relative to bit positions of a sum of the first and second binary numbers; at least one output stage logic circuit, coupled to outputs of the carry chain, for logically processing the two sets of summation carry terms with respect to a value of a conditional increment signal and an intermediate carry term, to selectively output either one of: the sum of the first and second binary numbers, and the incremented sum of the first and second binary numbers based on the value of the conditional increment signal; and a carry-logic gate for logically processing the value of the conditional increment signal and a predetermined bit of at least one of the two sets of summation carry terms from the carry chain, to produce a carry output signal dependent on a carry result if any is generated by incrementing of the sum of the first and second binary numbers.