Patent ID: 8748246

Claim:
A method, comprising: forming a semiconductor substrate which has p-well and n-well; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a hard mask over the gate electrode; patterning and etching the hard mask and gate electrode stack to define the NMOS and PMOS electrodes over the p-well and n-well regions respectively of the substrate; masking with photo resist the NMOS electrode; removing the hard mask over the PMOS electrode; implanting a p-type Group IIIa series dopant into the PMOS electrode; removing the photo resist over the NMOS electrode; masking with photo resist the PMOS electrode; removing the hard mask over the NMOS electrode; implanting a n-type lanthanide series dopant into the NMOS electrode; removing the photo resist over the PMOS electrode; depositing nickel; and siliciding the nickel, wherein the p-type Group IIIa series dopant includes Ga that interacts with oxygen to form a layer of Ga 2 O 3 proximate an interface between the gate dielectric and the Ga implanted gate electrode.