Patent ID: 8900958

Claim:
A method of forming an integrated circuit, the method comprising: forming a plurality of gate structures over a substrate; removing portions of the substrate to form respective recesses adjacent to the plurality of gate structures; depositing a first epitaxial silicon-containing layer in the recesses, wherein depositing the first epitaxial silicon-containing layer uses a cyclic deposition etching (CDE) process, wherein the CDE process has a CDE unit cycle, wherein the CDE unit cycle has a deposition process and an etch process, wherein the CDE unit cycle uses an etch temperature of the etch process that is different from a deposition temperature of the deposition process in the CDE unit cycle; and wherein the CDE process includes a deposition, a pump after deposition, an etch, and a pump after etch in each deposition and etch cycle, and wherein the CDE process is performed in the same process chamber; and depositing a second epitaxial silicon-containing layer over the first epitaxial silicon-containing layer to form respective source and drain regions next to the plurality of gate structures.