Patent ID: 8456975

Claim:
A phase error detection apparatus comprising: a sampling block configured to sample an input signal digitally; a first phase error calculation block configured to calculate a phase error using a first operation expression based on A k−1 +A k , where A k denotes a sampling value of said input signal after a zero cross and A k−1 represents] a sampling value of said input signal before the zero cross; a second phase error calculation block configured to calculate the phase error using a second operation expression based on min(A k , A k−1 ), where min(x, y) denotes an operator for selecting either x or y, whichever is the smaller of the two; and a selective output block configured to determine whether or not an absolute value |A k −A k−1 | of the difference between the sampling value A k of said input signal after the zero cross, and the sampling value A k−1 of said input signal before the zero cross, is equal to or smaller than a predetermined first threshold value, said selective output block further outputting selectively as phase error detection information either a calculated value from said first phase error calculation block or a calculated value from said second phase error calculation block depending on a result of the determination.