Patent ID: 8867277

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array having memory strings arranged therein, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines connected to control gates of the memory cells; and a control circuit operative to control data write to the memory cells, when executing a write operation to the memory cells, the control circuit being operative to apply a program voltage to a selected word line connected to a selected memory cell, apply a first write pass voltage smaller than the program voltage to a first non-selected word line including a word line adjacent to the selected word line, and apply a second write pass voltage smaller than the program voltage to a second non-selected word line which is a non-selected word line excluding the first non-selected word line, and the control circuit being configured to, in the write operation, raise the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raise the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times, the first voltage rise width being larger than the second voltage rise width, and X times being fewer than Y times.