Patent ID: 8415836

Claim:
A microcomputer system comprising: a microcomputer including N (N≧2) input ports; and M (2≦M≦2 N −1) push-down switches; wherein any one of (2 N −1) kinds of combination patterns with respect to the combination of said N input ports (including the case of a single input port) is allocated to each of said M push-down switches with the different combination pattern from each push-down switch, each of said M push-down switches includes three electric conductors, a first electric conductor and a second electric conductor are coupled to corresponding input ports of said N input ports and a third electric conductor is coupled to a ground voltage, and inverts the input levels of said input ports in allocated said combination pattern when the switch turns to be on state, and said microcomputer detects each state of said M push-down switches on the basis of the inputs levels of said N input ports.