Patent ID: 8612828

Claim:
A method comprising: generating an 8-bit checksum value corresponding to a 64-bit data value using a polynomial equation; concatenating the 8-bit checksum value and the 64-bit data value to form a 72-bit data block; storing the 72-bit data block in a memory; reading the 72-bit data block from the memory; generating a new checksum value for the 72-bit data block read from memory using the polynomial equation; and initiating error correction operations on either 1-bit persistent faults from one dynamic random access memory (DRAM or 8-bit permanent faults from the one DRAM if the new checksum value indicates an error, wherein the 8-bit checksum provides single-bit error correction and ×8 Single Data Device Correction (SDDC) for permanent faults, and one-bit transient faults are removed utilizing a look up table and data inversion testing, and wherein nine 8-bit wide memory chips are utilized for ×8 SDDC.