Patent ID: 7952516

Claim:
An integrated circuit device comprising: a primary signal synthesizer including a primary frequency accumulator in series with a primary phase accumulator, the primary frequency accumulator being configured to generate a primary digital modulation signal based on a predetermined modulation format and a primary frequency, the primary phase accumulator being configured to increment in response to a digital clock signal to thereby generate a free-running primary digital signal in accordance with the primary modulation signal; at least one secondary signal synthesizer disposed in parallel with the primary signal synthesizer, the at least one secondary signal synthesizer including at least one secondary frequency accumulator in series with a corresponding one of at least one secondary phase accumulator, the at least one secondary frequency accumulator being configured to generate at least one secondary digital modulation signal based on at least one secondary frequency, the at least one secondary phase accumulator being configured to increment in response to the digital clock signal to thereby generate a free-running at least one secondary digital signal in accordance with the at least one secondary digital modulation signal; and a switch element including a first switch input coupled to the primary signal synthesizer and at least one second switch input coupled to the at least one secondary signal synthesizer, the switch element being configured to select a switch output that provides either the primary digital signal or the at least one secondary digital signal based on a switch control input, a latter switch element output of the primary digital signal provided after the switch element output the at least one secondary digital signal being phase coherent with a former switch output of the primary digital signal provided before the switch element output the at least one secondary digital signal.