Patent ID: 8050148

Claim:
An apparatus comprising: a clock input; an event signal input; a time stamp output; a delay lock loop (DLL) that is coupled to the clock input, wherein the DLL includes a plurality of delay elements; a plurality of latches, wherein each delay element has an output that is coupled to a data input on a corresponding one of the plurality of latches, and wherein each of the plurality of latches includes an enable input that is coupled to the event signal input, and wherein each of the plurality of latches includes an output that is coupled to the time stamp output, and wherein the apparatus is adapted to produce a value on the time stamp output indicating a point at which the event signal input transitions between transitions on the clock input; and a detector that is coupled between the plurality of latch outputs and the time stamp output, wherein the detector includes a plurality of NOR gates, and wherein each of the plurality of NOR gates has a plurality of inputs coupled to a number of contiguous ones of the plurality of latches.