Patent ID: 7465975

Claim:
An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure and exposes said first contact point, and a second opening in said passivation layer is over a second contact point of said first metallization structure and exposes said second contact point, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip; a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers; and a second metallization structure over said polymer layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure comprises a sputtered metal structure and an electroplated metal structure over said sputtered metal structure, wherein said electroplated metal structure comprises copper.