Patent ID: 8368444

Claim:
A delay locked loop (DLL) unit comprising: a delay line configured to receive a reference clock at an input of the delay line and to provide a delayed version of the reference clock as a feedback clock; a phase detector coupled to the delay line and configured to provide an output signal that is dependent upon a phase difference between the reference clock and the feedback clock and that is indicative of a change in a delay associated with the delay line; and a step size controller coupled to the phase detector and configured to selectably provide one or more step size indications that control a delay step size of the delay line; wherein during a lock acquisition, in response to detecting the output signal indicating a first change in delay, the step size controller is configured to provide one or more step size indications corresponding to a first step size, and in response to detecting the output signal indicating a second change in delay, the step size controller is configured to provide one or more step size indications corresponding to a second step size, wherein the first step size is larger than the second step size; and wherein in response to detecting the output signal continuing to indicate a first change in delay, the step size controller is configured to provide one or more step size indications corresponding to a third step size, wherein the third step size is larger than the second step size.