Patent ID: 7633100

Claim:
A phase-change random access memory device comprising: a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines connected to a plurality of phase-change memory cells; and a plurality of column select transistors, each column select transistor selectively connecting the global bit line with one of the plurality of local bit lines, the plurality of column select transistors comprising at least first and second column select transistors, the first column select transistor being located closer to the write circuit and the read circuit than the second column select transistor, wherein a resistance of the first column select transistor, when selectively connecting a corresponding local bit line and the global bit line, is greater than a resistance of the second column select transistor, when selectively connecting a corresponding local bit line and the global bit line, and wherein a concentration of impurities doped into a channel region of the second column select transistor is higher than a concentration of impurities doped into a channel region of the first column select transistor.