Patent ID: 8166339

Claim:
An information processing apparatus, comprising: a plurality of nodes, the nodes comprising memories and processors connected to corresponding system buses; an interconnection bus configured to interconnect the nodes; a device configured to perform data processing, the device being connected to a first one of the system buses; and a memory selecting unit configured to: select a first one of the memories, the first memory being associated with the first system bus; determine whether the first memory is accessible to the device; select a second one of the memories, when the first memory fails to be accessible to the device, wherein the second memory is associated with a second system bus different from the first system bus; determine whether cache coherency is maintained between the nodes associated with the first and second system buses; invalidate a cache corresponding to the node associated with the second system bus, when cache coherency fails to be maintained; and enable the device to access the second memory associated with the second system bus.