Patent ID: 7155370

Claim:
A method comprising: testing a computer system using electrical stimuli that are under control of a plurality of test units located in a processor package, a chipset package, and memory subsystem hardware that make up the computer system and that are separate from processor, chipset and memory core function circuitry, the test units that are in the processor and chipset packages to conduct at-speed interconnect testing of the computer system, without requiring a processor core of the processor package to execute an operating system program for the computer system, to determine whether specified requirements of a component interconnect bus of the system are satisfied; and wherein one of the test units that is located on-chip with the processor core further issues bus transactions, that are in accordance with a bus protocol used by the processor core, to determine whether an I/O subsystem of the computer system meets a specification, without requiring the processor core to execute the operating system program.