Patent ID: 7635886

Claim:
A semiconductor memory, comprising: a semiconducting substrate comprising an electrically conductive region buried in the substrate; word lines, first bit lines, and a second bit line; first cells and second cells; each first cell comprising a control terminal connected to one of the word lines, a first terminal, and a second terminal connected to the electrically conductive region, and a selection transistor with a path controlled via the control terminal; a respective one of the first cells connected to one of the first bit lines via its first terminal thereof, and comprising a series circuit comprising the controlled path of the selection transistor and a storage capacitor, wherein the series circuit is arranged between its first terminal and its second terminal thereof; each second cell comprising a control terminal connected to one of the word lines, a first terminal, and a second terminal connected to the electrically conductive region, and a selection transistor with a path controlled via the control terminal; a respective one of the second cells connected to the second bit line via its first terminal thereof, and comprising a series circuit comprising the controlled path of the selection transistor and a resistance element, wherein the series circuit is arranged between its first terminal and its second terminal thereof.