Patent ID: 7834639

Claim:
A jitter injection circuit that generates a jittery signal including jitter, comprising: a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount, wherein the plurality of delay circuits are disposed to correspond to the plurality of edges of the jittery signal generated in the single bit of the reference signal, and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit, wherein the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period to be included in the jittery signal, and wherein the signal generating section generates a plurality of edges of the jittery signal to generate a plurality of bits of the jittery signal for each single bit of the reference; a delay setting section that sets for each delay circuit the delay amount according to the jitter to be injected at each edge of the jittery signal, wherein a maximum delay amount from among the delay amounts generated by the plurality of delay circuits is less than the single bit of the reference signal, and wherein the delay setting section sets for each delay circuit a delay amount obtained by adding timing jitter to be included in the corresponding bits of the jittery signal to an integer multiple of the average period of the jittery signal.