Patent ID: 7842567

Claim:
A method of forming metal gate transistors, comprising: forming a layer of metal nitride material over a dielectric layer overlying a semiconductor substrate, the metal nitride having a first work function; selectively masking off the metal nitride so that the metal nitride is covered in a first region and exposed in a second region; adding at least one of oxygen and carbon to the exposed metal nitride in the second region to establish a second work function in the second region; then, forming a layer of polysilicon material over the metal nitride material in the first and second regions; and forming one or more first transistor types in the first region and one or more second transistor types in the second region, wherein at least one of: the first metal comprises at least one of TaN and TiN, adding at least one of oxygen and carbon facilitates establishing at least one of metal oxy nitride, metal carbide nitride or metal oxy carbide nitride in the second region, the first work function is between about 3.5 eV and about 4.3 eV, the second work function is between about 4.8 eV and about 5.5 eV, the first metal is selectively masked off with a patterned layer of a capping material, the dielectric layer has a thickness of less than about 5 nanometers, the dielectric comprises at least one of silicon oxynitride (SiON) and a high k dielectric material, the at least one of oxygen and carbon are added by at least one of thermal, plasma and implantation processing, and the polysilicon is formed to a thickness of about a few hundred nanometers or less.