Patent ID: 8110415

Claim:
A method for fabricating a chip package comprising: prefabricating a silicon carrier to form both liquid cooling microchannels and through silicon vias for electrical interconnections to integrated circuits; prefabricating a silicon substrate; forming a dielectric layer between the silicon substrate and a layer of Tungsten (W); affixing a first array of small, highly thermally conductive metallic balls between the silicon carrier and the silicon substrate; placing the silicon carrier in contact with the first array of metallic balls; affixing one or more chips or chip stacks to the silicon carrier using a second array of small, highly thermally conductive metallic balls; wherein the metallic balls in the first and second arrays range in size from 2.0 to 20 microns in diameter for very high density interconnections; forcing a liquid coolant through the liquid cooling microchannels; introducing a plurality of through silicon vias to provide vertical electrical interconnections; and connecting a cap over the chips using an epoxy-based adhesive.