Patent ID: 8390052

Claim:
A nonvolatile semiconductor memory device comprising a nonvolatile memory cell of a split-gate structure having a floating gate, wherein the memory cell comprises: a first memory cell unit including a first diffusion region, a second diffusion region, a first gate electrode adjacent to the first diffusion region, and a second gate electrode adjacent to the second diffusion region, the first diffusion region and the second diffusion region being formed on a surface of a first semiconductor substrate, the first gate electrode and the second gate electrode being formed on a first channel region between the first diffusion region and the second diffusion region through a gate insulation film so as to be separated in a direction from the first diffusion region to the second diffusion region, a conductivity type of a region, including the first channel region, under a space between the first and second gate electrodes on the surface of the first semiconductor substrate being same as that of the first semiconductor substrate; a second memory cell unit including a third diffusion region, a fourth diffusion region, and a third gate electrode, the third diffusion region and the fourth diffusion region being formed on the surface of the first semiconductor substrate, the third gate electrode being formed on a second channel region between the third diffusion region and the fourth diffusion region through a gate insulation film; and a control terminal, the first gate electrode, the second gate electrode, and the third gate electrode are formed of a same electrode material layer, the second gate electrode and the third gate electrode are electrically connected to form the floating gate, and the floating gate is capacitively coupled to the control terminal.