Patent ID: 8405118

Claim:
A multichip package structure, comprising: a substrate unit including a substrate body having a first chip-placing region and a second chip-placing region formed on the top surface of the substrate body; a light-emitting unit including a plurality of light-emitting chips electrically connected to and disposed on the first chip-placing region; a current-limiting unit including at least one current-limiting chip electrically connected to and disposed on the second chip-placing region, wherein the current-limiting chip is electrically connected between the light-emitting unit and a constant voltage power supply, and a constant voltage generated by the constant voltage power supply is transmitted to the light-emitting unit through the current-limiting chip; a frame unit including a first annular colloid frame and a second annular colloid frame surroundingly formed on the top surface of the substrate body, wherein the first annular colloid frame surrounds the light-emitting chips to form a first colloid position limiting space corresponding to the first chip-placing region, and the second annular colloid frame surrounds the current-limiting chip to form a second colloid position limiting space corresponding to the second chip-placing region; and a package unit including a first package colloid body filled into the first colloid position limiting space to cover the light-emitting chips and a second package colloid body filled into the second colloid position limiting space to cover the current-limiting chip.