Patent ID: 8115535

Claim:
A leakage current suppressing circuit adapted to be coupled to a power source and an output terminal, comprising: a bias generating unit adapted to be coupled to the power source and the output terminal, and generating a bias voltage substantially equal to a voltage at the power source when the power source is turned on, and substantially equal to a voltage at the output terminal when the power source is turned off, and a switch unit including a first P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal adapted to be coupled to the output terminal, a gate terminal, and a body terminal coupled to the bias generating unit for receiving the bias voltage therefrom, wherein the bias generating unit includes: a second P-type transistor having a first terminal adapted to be coupled to the output terminal, a second terminal coupled to the first P-type transistor of the switch unit for outputting the bias voltage thereto, a gate terminal adapted to be coupled to the power source, and a body terminal coupled to the second terminal thereof; a third P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal coupled to the second terminal of the second P-type transistor, and a body terminal coupled to the second terminal of the second P-type transistor; and a fourth P-type transistor having a first terminal adapted to be coupled to the output terminal and a second terminal coupled to the gate terminal of the third P-type transistor.