Patent ID: 7080337

Claim:
A method of selecting decoupling capacitors for a packaged semiconductor chip, comprising: grouping at least some chip leads on the packaged semiconductor chip into at least two regions; for each of the regions, determining a first lead count for the chip leads in a first lead category in that region; for each of the regions, determining a second lead count for the chip leads in a second lead category, if any, in that region; for each of the regions, determining a third lead count for the chip leads in a third lead category, if any, in that region; for each lead category in each of the regions, determining a total switching current for that lead category in that region based on the lead count for that lead category in that region; for each lead category in each of the regions, determining a total decoupling capacitance value for that lead category in that region based on the total switching current for that lead category in that region, a maximum allowable voltage ripple selected for that lead category, and a voltage rise time selected for that lead category; determining how many decoupling capacitors may be allocated to each of the regions; for each of the regions, allocating a number of the decoupling capacitors for that region to each lead category; for each lead category in each of the regions, dividing the total decoupling capacitance value for that lead category in that region by the number of the decoupling capacitors allocated for that lead category in that region to obtain a desired individual capacitance value for each of the decoupling capacitors allocated for that lead category in that region; and for each lead category in each of the regions, selecting an actual decoupling capacitor for each of the decoupling capacitors allocated for that lead category in that region, wherein each of the actual decoupling capacitors has an actual individual capacitance corresponding to the desired individual capacitance value for that allocated decoupling capacitor of that lead category in that region, and wherein each of the actual decoupling capacitors of that lead category has a self-resonance frequency selected based on an operating frequency of the chip leads in that lead category.