Patent ID: 7838413

Claim:
A method of manufacturing a phase-change memory device, comprising: patterning a first insulating layer on a semiconductor substrate; sequentially forming a barrier metal and a lower electrode metal on the patterned first insulating layer; planarizing the lower electrode metal by chemical mechanical polishing (CMP) to expose the barrier metal on an uppermost surface of the patterned first insulating layer, and patterning the barrier metal by photolithography and etching to form a lower electrode of the phase-change memory device, wherein the patterned barrier metal includes a first portion surrounding a remaining portion of the lower electrode metal except for an upper surface of the lower electrode metal and a second portion on the insulating layer; after patterning the barrier metal, depositing a second insulating layer on the lower electrode and forming a hole in the deposited second insulating layer over the barrier metal on an uppermost surface of the patterned first insulating layer; depositing a phase-change material in the hole contacting the second portion of the patterned barrier metal and on the second insulating layer to a predetermined thickness; depositing an upper electrode material on the phase-change material; patterning the upper electrode material and the phase-change material to a predetermined width wider than the hole; depositing a third insulating layer on the upper electrode and forming a via therein exposing the upper electrode, such that the via overlaps a same vertical plane as the hole in the second insulating layer; and forming a contact plug in the via in contact with the upper electrode and forming a metal interconnection on the third insulating layer, connected to the lower electrode through the phase change material.