Patent ID: 7501319

Claim:
A method to fabricate a semiconductor device, comprising: forming a block dielectric layer and a sacrificial layer on a semiconductor substrate; forming trenches by etching the sacrificial layer; forming sidewall floating gates on lateral faces of the trenches; forming a block oxide layer on the sidewall floating gates; forming polysilicon gate electrodes on the resulting structure using a patterning process; removing the sacrificial layer; forming source/drain areas by implanting impurity ions into the resulting structure; injecting carriers or electric charges into the sidewall floating gates; and forming sidewall spacers adjacent to the polysilicon gate electrodes and the sidewall floating gates, wherein the sidewall floating gates have an amount or concentration of electrons or holes under side portions of the polysilicon gate electrodes sufficient to adjust a threshold voltage of the device and form an inversion layer in the substrate under the sidewall floating gates without application of a bias to the sidewall floating gates.