Patent ID: 6967378

Claim:
A semiconductor integrated circuit device comprising: a first MOS transistor having a first backgate region, a first conductive region, and a second conductive region, and having the first backgate region and the first conductive region thereof connected together; a second MOS transistor, of a same conductivity type as the first MOS transistor, having a second backgate region, a third conductive region, and a fourth conductive region, having the second backgate region and the third conductive region thereof connected to the first backgate region and the first conductive region of the first MOS transistor, and receiving at the fourth conductive region thereof a first direct-current voltage; a voltage setting circuit setting a second direct-current voltage fed to a gate of the second MOS transistor; an anti-reverse-current element receiving the first direct-current voltage or a third direct-current voltage produced from the first direct-current voltage, and connected to the voltage setting circuit in such a way as to prevent a reverse current from flowing through the voltage setting circuit; and a feedback circuit outputting to a gate of the first MOS transistor a value obtained by comparing a voltage at the second conductive region of the first MOS transistor with a reference voltage, wherein the voltage setting circuit produces, according to the first direct-current voltage or the third direct-current voltage, the second direct-current voltage within a withstand voltage range of the second MOS transistor, wherein a load is connected to the second conductive region of the first MOS transistor, and wherein, between the first backgate region and the second conducting region of the first MOS transistor, a first parasitic diode is formed and, between the second backgate region and the fourth conducting region of the second MOS transistor, a second parasitic diode is formed.