Patent ID: 6979856

Claim:
A semiconductor memory device comprising: a semiconductor substrate; and a plurality of unit cells constituting a cell array, wherein each adjacent two memory cells in said cell array comprise: first, second and third diffusion regions formed in said semiconductor substrate and separated from one another; a first insulating film formed on said semiconductor substrate and covering a region between said first diffusion region and said second diffusion region; a first gate electrode formed on and overlying said first insulating film; a second insulating film formed on said substrate and covering a region between said diffusion region and said third diffussion region; and a second gate electrode formed on and overlying said second insulating film; wherein a first one of said adjacent two memory cells comprises a first memory cell transistor including said first and second diffusion regions, said first insulating film, and said first gate electrode; wherein a second one of said adjacent two memory cells comprises a second memory cell transistor including said second and third diffusion regions, said second insulating film, and said second gate electrode; and wherein said semiconductor memory device further comprises: first, second, and third bit lines provided, respectively, on first, second, and third layers provided over said semiconductor substrate and connected via associated contacts to said first, second and third diffusion regions respectively; a word line connected in common to said first and second gate electrodes, or first and second word lines connected respectively to said first and second gate electrodes; and an impurity region having a polarity opposite that of said second diffusion region and formed at an end portion of said second diffusion region in the semiconductor substrate immediately under at least one gate electrode of said first and second gate electrodes.