Patent ID: 7555692

Claim:
A method for detecting an error in an execution pipeline of a processor, comprising: obtaining a first result after executing a first instruction instance, wherein the first result comprises a first plurality of bits; partitioning the first plurality of bits into a first plurality of groups, wherein each of the first plurality of groups comprises a subset of consecutive bits of the first plurality of bits; calculating a first plurality of residues for the first plurality of groups, wherein each of the first plurality of residues corresponds to one of the first plurality of groups; storing the first result, a full size residue of the first result, and the first plurality of residues in a working register file (WRF); summing the first plurality of residues to generate a first sum after storing the first result in the WRF; calculating a residue of the first sum; comparing the residue of the first sum and the full size residue of the first result to generate a first comparison; and detecting the error based on the first comparison.