Patent ID: 8129831

Claim:
An apparatus including a chip arrangement, comprising: a first semiconductor chip having a first chip surface presenting a first chip conductive region; a second semiconductor chip having a second chip surface presenting a second chip conductive region; an electrically insulating layer including: a layer body comprised of a material; a first layer surface disposed on a side of the layer body having a first layer conductive region; and a second layer surface disposed on an opposing side of the layer body having a second layer conductive region, wherein the layer body electrically insulates the first layer conductive region from the second layer conductive region, wherein the first layer conductive region is electrically coupled with the first chip conductive region and the second layer conductive region is electrically coupled with the second chip conductive region; and a first electrical conductor comprising a first lower section, a first upper section and a first angled section connecting the first lower and first upper sections, wherein the first lower section is located in the plane of a substrate and the first upper section comprises an upper surface which is coplanar with an upper surface of the first semiconductor chip and the first upper section is electrically coupled to the first layer conductive region of the electrically insulating layer.