Patent ID: 7626423

Claim:
An output circuit for an integrated circuit (IC) device, the output circuit having an output terminal for providing an output signal having a programmable slew rate, the output circuit comprising: an output driver including an output transistor coupled between a first supply voltage and the output terminal; and a pre-driver circuit having an input to receive a logic signal, having an output coupled to a gate of the output transistor, and having an input to receive a mode control signal comprising a plurality of control signals, wherein the pre-driver circuit selectively adjusts a series resistance between the gate of the output transistor and a second supply voltage in response to the mode control signal by selectively enabling one or more paths of a plurality of paths between the gate of the output transistor and the second supply voltage, wherein the output transistor is a PMOS output transistor, wherein the pre-driver circuit is a first pre-driver circuit, wherein the second supply voltage is ground potential, and wherein the output driver includes an NMOS output transistor coupled between the output terminal and the ground potential, the output circuit further comprising: a second pre-driver circuit having an input to receive the logic signal, having an output coupled to a gate of the NMOS output transistor, and having an input to receive the mode control signal, wherein the second pre-driver circuit selectively adjusts a series resistance between the gate of the NMOS output transistor and the first supply voltage in response to the mode control signal, and wherein the first pre-driver circuit comprises: a first pull-up transistor coupled between the first supply voltage and the gate of the PMOS output transistor and having a gate to receive the logic signal; a first pull-down transistor coupled between the gate of the PMOS output transistor and a first control node and having a gate to receive the logic signal; and a plurality of selectable pull-down transistors coupled in parallel between the first control node and the ground potential, wherein each of the selectable pull-down transistors has a gate to receive a corresponding one of the plurality of control signals; and the second pre-driver circuit comprises: a second pull-down transistor coupled between the ground potential and the gate of the NMOS output transistor and having a gate to receive the logic signal; a second pull-up transistor coupled between the gate of the NMOS output transistor and a second control node and having a gate to receive the logic signal; and a plurality of selectable pull-up transistors coupled in parallel between the second control node and a third supply voltage, wherein each of the selectable pull-up transistors has a gate to receive a corresponding one of the plurality of control signals.