Patent ID: 7468316

Claim:
A process for fabricating a chip, comprising: providing a silicon substrate, a dielectric layer over said silicon substrate, a contact pad over said dielectric layer, and a passivation layer over said dielectric layer, wherein an opening in said passivation layer is over said contact pad and exposes said contact pad, and wherein said passivation layer comprises a nitride; and forming a metal bump over said silicon substrate, wherein said metal bump is connected to said contact pad through said opening in said passivation layer, and wherein said forming said metal bump comprises forming a first metal layer over said silicon substrate, wherein said first metal layer comprises a barrier metal layer and a seed layer over said barrier metal layer, wherein said seed layer is formed using a sputter chamber and a copper source, followed by forming a photoresist layer on said first metal layer, wherein an opening in said photoresist layer is over said first metal layer, followed by electroplating a copper pillar in said opening in said photoresist layer, wherein said copper pillar has a height between 10 micrometers and 100 micrometers, followed by forming a nickel layer on said copper pillar in said opening in said photoresist layer, wherein said copper pillar has a sidewall continuously connecting with that of said nickel layer, followed by removing said photoresist layer, followed by reducing a transverse dimension of said copper pillar by a process comprising wet etching, followed by removing said first metal layer not under said copper pillar.