Patent ID: 8867683

Claim:
A receiver for providing symbols at a second clock rate from an incoming stream comprising an input sequence of symbols clocked at a first clock rate comprising: a first buffer for storing symbols in said incoming stream at said first clock rate; a first buffer control circuit for providing a re-clocked stream of symbols at said second clock rate, said re-clocked stream comprising symbols of said input sequence stored in said first buffer and placeholder symbols inserted between symbols of said input sequence, and a signal identifying placeholder symbols in said re-clocked stream, wherein said placeholder symbols are inserted in said re-clocked stream when insufficient symbols are stored within said first buffer, wherein said re-clocked stream and said incoming stream are plesiochronous; a second buffer for storing corresponding symbols, said corresponding symbols corresponding to said symbols provided from said first buffer; a second buffer control circuit for receiving said signal and inhibiting placeholder symbols in said re-clocked stream as identified by said signal from entering said second buffer, and providing said corresponding symbols from said second buffer at said second clock rate.