Patent ID: 7202527

Claim:
A MOS transistor, comprising: a substrate; a drain zone of a first conductivity type formed in said substrate; a source zone of the first conductivity type formed in said substrate, and a channel region formed between said drain zone and said source zone; a gate electrode and a gate oxide region disposed above said channel region; said gate electrode, said drain zone, and said source zone together forming a transistor structure with a lateral breakdown voltage and a vertical breakdown voltage, and said transistor structure having an adjustable voltage ratio between a value of the lateral breakdown voltage and a value of the vertical breakdown voltage, the adjustable voltage ratio being dependent on a variation in a dopant concentration in said drain zone and said source zone, the variation in the dopant concentration being adjustable such that: a first highly doped zone of the first conductivity type being disposed between said gate oxide region and a first LDD region, and a second highly doped zone of the first conductivity type being disposed between said gate oxide region and a second LDD region; and a third zone of the first conductivity type being disposed between said source zone and said substrate in a form of a well around said source zone, and a fourth zone of the first conductivity type being disposed between said drain zone and said substrate in a form of a well around said drain zone.