Patent ID: 7323349

Claim:
A method of fabricating a self-aligned, cross point resistor memory array for incorporation into an integrated circuit, comprising: preparation of a silicon substrate as a memory wafer; implanting ions into the silicon substrate to form a top P+ layer and a buried N+ layer; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on the P+ layer; masking and patterning the hard mask layer defining a pattern in a first direction; etching to remove an unmasked portion of the hard mask, an unmasked portion of the sacrificial material an unmasked portion of the bottom electrode, and over etching to remove an unmasked portion of the N+ layer; depositing a layer of silicon oxide, having thickness of about 1.5 times that of the total thickness of hard mask and the sacrificial material and the bottom electrode; smoothing the silicon oxide by CMP, stopping at the level of the hard mask; masking and patterning the remaining hard mask layer defining a pattern in a second direction which is substantially perpendicular to the first direction; etching to remove an unmasked portion of the hard mask, an unmasked portion of the sacrificial material an unmasked portion of the bottom electrode, and over etching to remove an unmasked portion of the N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide having thickness of about 1.5 times that of the total thickness of hard mask and the sacrificial material and the bottom electrode; smoothing the silicon oxide by CMP, stopping at the level of the hard mask; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material to a thickness of about 1.5 times of the thickness of the sacrificial material and the hard mask material; smoothing the CMR material by CMP, stopping at the level of the last deposited silicon oxide; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.