Patent ID: 6964918

Claim:
A process for fabricating an integrated circuit package, comprising: establishing a plating mask on a first surface of a metal carrier, the plating mask defining a plurality of components including at least one die attach pad, at least one row of contact pads and at least one additional electronic component; depositing a plurality of metallic layers on exposed portions of said first surface of said metal carrier, thereby forming said plurality of components; stripping said plating mask from said metal carrier and leaving said plurality of metallic layers in the form of said plurality of components; mounting at least one semiconductor die to a respective one of said at least one die attach pad such that each die attach pad has a respective semiconductor die mounted thereon and pads of each said respective semiconductor die are electrically connected to ones of said contact pads and to said at least one additional electronic component; overmolding said first surface of said metal carrier to encapsulate said plurality of components and said at least one semiconductor die; and etching away said metal carrier.