Patent ID: 7659754

Claim:
A power switching circuit in CMOS technology, the circuit comprising: a first voltage rail; a second voltage rail a power MOS transistor that coupled to the first voltage rail; a pair of driver MOS transistors coupled in series with one another between the first and second voltage rails, wherein the gate of the power MOS transistor is coupled to a node between the driver MOS transistors; a pair of buffers that are each coupled to the gate of one of the driver MOS transistors and that each receive a clock signal; a pair of first resistors that are each coupled between the first voltage rail and the gate of one of the driver MOS transistors; and a pair of impedance branches that are each coupled between the first voltage rail and the gate of one of the driver MOS transistors, wherein each impedance branch includes a second resistor coupled in series with a non-linear component, and wherein the resistance value of each second resistor is substantially smaller than the resistance value of its corresponding first resistor.