Patent ID: 7834615

Claim:
A built-in-self-test (BIST) circuit for a double data rate memory interface circuit for a system on a chip comprising: A. a signal multiplier for receiving a first clock signal from a tester and outputting a multiplied clock signal; B. a first multiplexer for selecting between a test clock input and a data strobe signal inputs and providing as an output an internal data strobe input signals; C. a delay magnitude generator coupled to the signal multiplier for receiving the multiplied clock signal and providing a second clock signal and a phase control signal; D. plural digitally controlled delay line blocks, each block receiving the second clock signal, the phase control signal, and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal; E. a second multiplexer selecting one of the internal data strobe input signals; and F. a third multiplexer selecting the phase shifted data strobe output signal corresponding to the selected internal data strobe input signal; and G. a phase detector for determining a phase difference between the selected internal data strobe input signal and the phase shifted data strobe output signal and outputting a phase difference value.