Patent ID: 8094507

Claim:
A command latency system comprising: a flip-flop pipeline configured to receive a command signal for a memory, the command signal transmitted in accordance with a first clock signal and output a delayed command signal after a certain number of cycles of the first clock signal, the flip-flop pipeline including a number of flip-flops coupled in series, the number of series coupled flip-flops being less than the certain number of cycles of the first clock signal, wherein at least a first and second flip-flop of the series coupled flip-flops being clocked with a second clock signal, wherein the second clock signal is slower than the first clock signal; and storage circuitry configured to receive and store phase information associated with the received command signal indicating a cycle of the clock signal corresponding to receipt of the command signal, wherein a third flip-flop of the series coupled flip-flops is coupled to the storage circuitry and configured to output the delayed command signal in accordance with the second clock signal based in part on said phase information being received by the storage circuitry.