Patent ID: 8418009

Claim:
A tangible computer-readable recording medium storing therein a delay fault testing program causing a computer to execute: acquiring for each chip, first delay values of paths included in a plurality of chips manufactured using circuit information concerning a circuit-under-test; building a function model representing a delay value of a path, based on the acquired first delay values for the paths and on the circuit information; calculating a second delay value of a path included in and having the same configuration in each of the chips, using the function model built at the building and the circuit information; comparing for each of the chips, the second delay value and the first delay value of a path having a configuration identical to that of the path for which the second delay value has been calculated; determining based on a comparison result obtained at the comparing, the path having a configuration identical to that of the path for which the second delay value has been calculated, to be a path that includes a delay error occurring irregularly according to chip; and outputting a determination result obtained at the determining.