Patent ID: 7669105

Claim:
A reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding duo-binary code data and binary code data, the reconfigurable MAP calculation circuit comprising: a gamma calculation block for calculating a branch metric value for each branch of a trellis associated the MAP calculation circuit, wherein the gamma calculation block receives: in duo-binary mode: i) duo-binary inputs (a, b) from a first time interval; ii) parity information generated from the duo-binary inputs (a,b); and iii) extrinsic information associated with previous nodes in the trellis; and in binary mode: i) a first binary input x i from a first time interval and a second binary input x i+1 from a second time interval; ii) first parity information generated from the first binary input x i and second parity information generated from the second binary input x i+1 ; and iii) extrinsic information associated with previous nodes in the trellis; and a first arithmetic logic unit (ALU) stage for calculating alpha values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives alpha values for previous nodes in the trellis and branch metric data from the gamma calculation block.