Patent ID: 7700986

Claim:
A chip package carrier, comprising: a first circuit layer; a second circuit layer; a core layer, disposed between the first circuit layer and the second circuit layer and having at least a first through-hole; a third circuit layer, disposed above the first circuit layer and comprising at least a die pad; a first dielectric layer, disposed between the first circuit layer and the third circuit layer; a fourth circuit layer, disposed under the second circuit layer and comprising at least a solder ball pad; and a second dielectric layer, disposed between the second circuit layer and the fourth circuit layer; and at least a capacitor device, disposed in the first through-hole, wherein the capacitor device comprises: a first pillar electrode, covering the wall of the first through-hole and connected between the first circuit layer and the second circuit layer; a cylindrical capacitor material, disposed in the first pillar electrode and extended from the first circuit layer to the second circuit layer, and having a first blind hole with an extension direction the same as the axis direction of the first through-hole, wherein the first blind hole does not go through the second dielectric layer and the fourth circuit layer; and a second pillar electrode, disposed in the first blind hole and connected to the die pad.