Patent ID: 7620926

Claim:
A computer-implemented method of designing an integrated circuit (IC), comprising: selecting a power management block from a library of interchangeable power management blocks based on power and performance requirements of a target application; providing, by a computer, a plurality of columns of logic blocks; providing, by the computer, a plurality of columns of power management blocks, wherein the columns of logic blocks and the columns of power management blocks are alternately disposed across the IC; coupling each logic block to at least one logic block in at least one other column of logic blocks; and coupling each power management block to a respective logic block in an adjacent column of logic blocks, wherein: providing the plurality of columns of power management blocks comprises providing a plurality of columns of the selected power management blocks, and the library of interchangeable power management blocks comprises a plurality of power management blocks each having a power gate coupled between a global power rail and a local power rail, wherein: the global power rail is shared by a plurality of the power management blocks, and for each power management block, the local power rail is coupled to the respective logic block coupled to the power management block.