Patent ID: 7978721

Claim:
A memory system, comprising: a plurality of memory vaults comprising a stacked plurality of tiled memory arrays, each memory vault comprising a stacked plurality of memory array die sections; a plurality of memory vault controllers (MVCs), each MVC coupled to a corresponding one of the plurality of memory vaults in a one-to-one relationship to communicate with the corresponding memory vault independently from communications between others of the plurality of MVCs and memory vaults corresponding to the others of the plurality of MVCs; a plurality of configurable serialized communication link interfaces (SCLIs) configured for concurrent operation to communicatively couple the plurality of MVCs to at least one of an originating device or a destination device; a switch coupled to the plurality of SCLIs and to the plurality of MVCs to cross-connect a selected SCLI to a selected MVC; and a packet decoder coupled to the switch to receive an outbound packet sent from the originating device across an outbound one of the plurality of SCLIs, to extract at least one of an outbound memory command, an outbound memory address, or an outbound memory data field from the outbound packet and to present a set of memory vault select signals to the switch; and a packet encoder coupled to the switch to receive at least one of an inbound memory command, an inbound memory address, or inbound memory data from one of the plurality of MVCs and to encode the inbound memory address or the inbound memory data into an inbound packet for transmission across an inbound one of the plurality of SCLIs to the destination device.