Patent ID: 8190821

Claim:
A cache control apparatus comprising: a speculative fetch output section that outputs a speculative fetch which is a memory fetch request output before it becomes clear whether data requested by a CPU is stored in a cache provided in the CPU; a table that retains information concerning the speculative fetch and statuses of the speculative fetch; a tag information search section that searches tag information including a list of information concerning data stored in the cache for cache hit information; a status update section that updates, at the time of completion of the search by the tag information search section, the status of the speculative fetch in the table to a predetermined status in the case where the search results in a cache miss; a status update determination section that determines, when acquiring data acquired by the speculative fetch output from the speculative fetch output section, whether the status of the speculative fetch retained in the table has been updated to the predetermined status by the status update section within a time period obtained by adding up a time period from when the speculative fetch is output to when the speculative fetch reaches a memory controller for controlling data communication between a memory and a device outside the memory and a time period from completion of writing of data to the memory which is specified by a data write command that has been issued before issuance of the speculative fetch, for the same address as that for which the speculative fetch is issued to when a response of the data write command is returned; and a data adoption determination section that determines whether to adopt or not the data acquired by the speculative fetch output by the speculative fetch output section based on a result of the determination by the status update determination section.