Patent ID: 8421162

Claim:
A field effect transistor structure having a gate dielectric under a gate with length Lg, comprising: a substrate, a well in the substrate doped to have a first concentration of a dopant, an undoped channel under the gate dielectric and extending to a source and a drain, a screening region positioned in the well and under the gate dielectric, the screening region extending to the source and drain and having a second concentration of dopant greater than 5×10 18 dopant atoms per cm 3 , at least one punch through suppression region having a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant, with the punch through suppression region positioned in the well under the gate dielectric and beneath the screening region, a threshold voltage set region having a fourth dopant concentration intermediate between the second concentration and 5×10 17 dopant atoms per cm 3 , with the threshold voltage set region positioned under and spaced from the gate dielectric, the threshold voltage set region extending to the source and drain.