Patent ID: 7333358

Claim:
A memory element comprising: a first logic component having a first input, a second input, and an output; and a second logic component having a first input, a second input, and an output, wherein the first input of the first logic component is connected to the output of the second logic component, the first input of the second logic component is connected to the output of the first logic component, the second input of the first logic component and the second input of the second logic component are connected to a control line, and wherein the first logic component and the second logic component are embodied such that when a control signal having a first level is applied to the control line, at the respective output, a signal is output which has an output level that is inverted with respect to the level of the signal present at the respective first input, and when a control signal having a second level is applied to the control line, at the respective output a signal is output which has a predetermined level independent of the level of the signal present at the respective first input.