Patent ID: 7171543

Claim:
A processor comprising: means for executing an instruction of an application of a first bit size ported to a second bit size environment, the second bit size being greater than the first bit size; and means for confining the application to an address space subset of the first bit size, said means for confining comprising: means for truncating generated address references of the second bit size to the first bit size; means for determining that the address space subset of the first bit size is signed address space or unsigned address space based on a setting of an address format control signal, the address format control signal having a first setting to indicate unsigned address space and a second setting to indicate signed address space; and means for extending to the second bit size the truncated generated address references based on results from said means for determining, zero-extending the truncated generated address references if the address space subset of the first bit size is unsigned and sign-extending the truncated generated address references if the address space subset of the first bit size is signed.