Patent ID: 7809899

Claim:
An apparatus comprising: a control circuit configured to generate command signals, a read data path control signal, a read data valid signal, a signal indicating an owner of the read data, and one or more write data path control signals in response to an integrity protection control signal, a first input signal indicating read data is available from an external memory, a second input signal communicating data owner information, and one or more control signals, wherein said command signals include a first signal communicating commands to said external memory and an arbitration acknowledgment signal; a write data path circuit configured (i) to receive write data to be written to said external memory and (ii) to present the write data alone in a first mode and the write data followed by integrity protection data in a second mode, wherein said first and second modes are selected based upon said one or more write data path control signals; a read data path circuit configured to receive read data from said external memory, wherein (i) in said first mode said read data path circuit presents the read data received from the external memory and (ii) in said second mode said read data path circuit presents the read data after correction based upon integrity protection data also received from said external memory, wherein said first and second modes are selected based upon said read data path control signal; and an address generator circuit configured to generate one physical memory address in response to a logical address in said first mode and two physical addresses in response to said logical address in said second mode, wherein (i) in said first mode said write data is written and said read data is read without integrity protection, (ii) in said second mode said write data is written and said read data is read with integrity protection, (iii) said integrity protection data is written to a separate location from said write data and read from a separate location from said read data, and (iv) said address generator switches between said first and second modes based upon said integrity protection control signal.