Patent ID: 8130562

Claim:
A semiconductor memory device comprising: a shift register including first latch circuits and second latch circuits being disposed alternately, repeatedly and adjacently to one another, the shift register receiving an input signal and outputting an output signal, wherein each of the second latch circuits is disposed to have a configuration reversed from configurations of the first latch circuits, the input signal is inputted to one of the first latch circuits arranged on an input end side, an output side of the one of the first latch circuits provided on the input end side is electrically connected to an input side of one of the first latch circuits which is disposed through one of the second latch circuits and which is provided on an end side opposite to the input end side, an output side of the one of the first latch circuits provided on the end side is electrically connected to an input side of one of the second latch circuits provided on the end side, an output side of the one of the second latch circuits provided on the end side is electrically connected to an input side of one of the second latch circuits which is disposed through one of the first latch circuits provided on the input end side, and the output signal is serially accessed and is outputted to the input end side from the one of the second latch circuits provided on the input end side.