Patent ID: 7440476

Claim:
An apparatus comprising: a video multiplexer to receive a plurality of data streams, each with its own source clock that has nominally, but not exactly, the same frequency, and to generate a multiplexed video signal clocked by a common clock, the common clock having the same frequency as one of the source clocks; a synchronization circuit to align the plurality of data streams prior to multiplexing, wherein the synchronization circuit includes an asynchronous first-in first-out (FIFO) buffer having as an input a first stream of the plurality of data streams, said input being clocked by a source clock of the first stream, the FIFO buffer having an output clocked by the common clock, which is one of the data stream source clocks other than the source clock of the first stream, and wherein the synchronization circuit determines a sign of a difference between frame rates of the first stream and a second stream of the plurality of data streams, wherein each of the frame rates of the first stream and the second stream are determined based on the frequency of the source clock of the second stream; and an underflow/overflow detector to detect an overflow condition or an underflow condition in the FIFO based on the sign of the difference between frame rates.