Patent ID: 7459383

Claim:
A method of fabricating a gate structure, comprising the steps of: providing a substrate; forming a gate dielectric layer over the substrate; forming a first conductive layer over the gate dielectric layer; forming an opening in the first conductive layer; forming a second conductive layer over the first conductive layer such that part of the second conductive layer fills up the opening completely and a portion of the second conductive layer is disposed on the surface of the first conductive layer outside the opening; forming a patterned cap layer over the second conductive layer, wherein the cap layer above the opening has a width smaller than the width of the opening in the first conductive layer; removing a portion of the second conductive layer to form a patterned second conductive layer that exposes the first conductive layer, wherein the patterned second conductive layer above the opening has a width smaller than the width of the opening in the first conductive layer; forming a first insulating spacer on the respective sidewalls of the cap layer so that the first insulating spacer and the patterned cap layer cover over the second conductive layer; and removing the first conductive layer not covered by the first insulating spacer.