Patent ID: 8542514

Claim:
A memory structure, comprising: a first memory cell having a first plurality of non-volatile Semiconductor-Oxide-Nitride-Oxide-Semiconductor type (SONOS-type) devices coupled with a first Six Transistor (6-T) Static Random Access Memory (SRAM) cell; a second memory cell having a second plurality of non-volatile SONOS-type devices coupled with a second 6 -T SRAM cell, wherein the first plurality of non-volatile SONOS-type devices are interdigitated with the second plurality of non-volatile SONOS-type devices; a store gate line, a non-volatile gate line, and a recall gate line, wherein the store gate line, the non-volatile gate line, and the recall gate line overlap diffusion areas of both the first and second pluralities of non-volatile SONOS-type devices; and wherein each of the first and the second pluralities of non-volatile SONOS-type devices comprises an interconnect and a set of dummy interconnects.