Patent ID: 7995404

Claim:
A semiconductor IC device, comprising: an internal clock generator configured to buffer an external clock signal to generate an internal clock signal; a core strobe signal generator configured to latch a read command signal in response to the internal clock signal to generate a core strobe signal; a core block configured to output data stored in a memory cell in response to the core strobe signal; a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order; and a controller configured to generate the plurality of control signals in response to the core strobe signal and the internal clock signal, wherein the controller includes: a data output interval signal generator generating a data output interval signal in response to the core strobe signal and the internal clock; a reference clock generator generating reference clock signals in response to the data output interval signal and the internal clock signal; a data latch signal generator generating a data latch signal in response to the core strobe signal and the internal clock signal; a data shift clock generator generating a data shift clock signal in response to the reference clock signal and the data latch signal; a data selection signal generator generating data selection signals in response to the data latch signal and the reference clock signals; and a data output clock generator generating data output clock signals in response to the reference clock signal and the data selection signals.