Patent ID: 7829403

Claim:
A method for fabricating a semiconductor device, comprising: providing a substrate; defining a first active region and a second active region in the substrate; forming an electrode on the substrate, covering the first active region and the second active region; forming a first sacrificial layer on the second active layer and performing a first doping process to a portion of the electrode to form a first work function electrode on the first active layer; removing the first sacrificial layer and forming a second sacrificial layer on the first active layer, and performing a second doping process to a portion of the electrode to form a second work function electrode on the second active layer; removing the second sacrificial layer, and etching a portion of the first work function electrode and the second work function electrode to form a patterned first work function electrode with a first bulge portion and a patterned second work function electrode with a second bulge portion, wherein the patterned first and second work function electrodes further comprise flat portions over the first active region and the second active region of the substrate; forming a hard mask layer, covering the first bulge portion and the second bulge portion and extending to cover the flat portions of the patterned first and second work function electrodes; forming a third sacrificial layer on the second active region, covering the patterned second work function electrode; removing a portion of the patterned first work function electrode to leave the first bulge portion under the hard mask layer to be a first work function gate structure using the third sacrificial layer covering the patterned second work function electrode as a first etching mask; removing the third sacrificial layer and forming a fourth sacrificial layer on the first active region, covering the patterned first work function electrode; removing a portion of the patterned second work function electrode to leave the second bulge portion under the hard mask layer to be a second work function gate structure using the fourth sacrificial layer covering the patterned first work function electrode as a second etching mask; and removing the fourth sacrificial layer.