Patent ID: 8575986

Claim:
A level shift circuit, comprising: an input port configured to receive an input signal; a first signal amplifying unit configured to amplify the received input signal; a node at the first signal amplifying unit to output the amplified signal; a level shift input port configured to receive a level shift voltage for controlling a DC level of the node; a first supply voltage configured to drive the first signal amplifying unit; a level shift voltage generation circuit configured to generate the first supply voltage and the level shift voltage, wherein the first signal amplifying unit comprises: first conductive type first and second transistors connected between a reference potential and the first supply voltage, and disposed at the reference potential side to form a pair of differential transistors, the first and second transistors having the input port to receive the input signal: second conductive type third and fourth transistors connected between the first supply voltage and the reference potential, disposed at the first supply voltage side to form a pair of cross-link transistors, the third and fourth transistors having the node form which the amplified signal is output; and second conductive type fifth and sixth transistors electrically connected between the pair of differential transistors and the pair of cross-link transistors, the fifth and sixth transistors having the level shift input port to which the level shift voltage is applied, wherein the amplified signal includes first and second output signals obtained by amplifying the input signal and the node include first and second output ports configured to output the first and second output signals, respectively; a second signal amplifying unit including a seventh transistor to which the first output signal is input, an eighth transistor to which the second output signal is input, and ninth and tenth transistors connected to the seventh and eighth transistors so as to be cross-linked; and an output port configured to output a level-shifted output signal from the ninth or tenth transistor side.