Patent ID: 7198969

Claim:
A method of assembling a plurality of semiconductor chips, comprising the steps of: (a) providing a portion of a semiconductor wafer containing the plurality of chips thereon, each of the plurality of chips having a contact pattern area including a pattern of contacts on a surface of the chip; (b) assembling a respective section of a dielectric interposer to each respective one of the plurality of chips individually, without detaching the plurality of chips from the portion of the semiconductor wafer, each section of interposer having a plurality of bonding pads near an outer periphery of the section, such that each bonding pad lies near the contact pattern area of the corresponding one of the plurality of chips; (c) wire bonding each bonding pad to a respective one of the contacts on the front surface of the corresponding one of the plurality of chips; (d) applying an encapsulant to encapsulate the wires on each of the plurality of chips; and (e) cutting the encapsulated chips from the semiconductor wafer.