Patent ID: 7956400

Claim:
An integrated circuit device comprising: an upper wiring layer and a lower wiring layer, and a metal-insulator-metal (MIM) capacitor in an inter-layer dielectric layer between said upper and lower wiring layers, the MIM capacitor comprising a top plate, a bottom plate and a dielectric layer between the top and bottom plates; wherein the MIM capacitor top plate has a region which does not face the MIM capacitor bottom plate; wherein the MIM capacitor bottom plate has a region which does not face the MIM capacitor top plate; and conductive vias extend from said upper wiring layer to the MIM capacitor top and bottom plates, including a conductive via contacting and extending through the MIM capacitor top plate at said region thereof which does not face the bottom plate, and a conductive via contacting and extending through the MIM capacitor bottom plate at said region thereof which does not face the top plate, said conductive via that contacts the top plate terminates at a first dielectric portion within the inter-layer dielectric layer between the MIM capacitor and the lower wiring layer, and the conductive via that contacts the bottom plate terminates at a second dielectric portion within the inter-layer dielectric layer between the MIM capacitor and the lower wiring layer.