Patent ID: 7202724

Claim:
A flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal, comprising: a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal; and a pulse generator including a NAND gate, a variable delay, a first inverter, a second inverter, and a transistor circuit, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal, wherein the NAND gate receives the clock signal and an output signal of the variable delay and outputs the first clock pulse signal; the first inverter receives the first clock pulse signal and outputs the second clock pulse signal; the variable delay receives the clock signal and the second clock pulse signal, and an output signal of the variable delay feeds back to the NAND gate; the second inverter receives the output signal of the variable delay; and the transistor circuit is connected to the output signal of the variable delay and receives an output of the second inverter.