Patent ID: 7030498

Claim:
A semiconductor device comprising: a silicon substrate having an n-type region; a gate insulating film formed on the n-type region, using nitrogen-containing silicon oxide; a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon; p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode; side wall spacers formed on side walls of said gate electrode, said side wall spacer comprising a lamination of a silicon oxide layer and a silicon nitride layer; a lower interlayer insulating film having a planarized surface and covering said gate electrode and side wall spacers; an intermediate interlayer insulating film formed above said lower interlayer insulating film, and having a planarized surface: a wiring trench formed in said interlayer insulating film from the planarized surface to an inside thereof; and a copper wiring pattern including an underlying barrier layer of Ta or Ti formed on inner surfaces of the wiring trench, and an upper level copper region formed on the underlying barrier layer, said copper wiring pattern being filled in said wiring trench, while being separated from the lower and intermediate interlayer insulating film.