Patent ID: 8440534

Claim:
A method, comprising: forming a layer of spacer material above a first structure of a first transistor formed above a first active region of a semiconductor device and a second structure of a second transistor formed above a second active region of said semiconductor device; selectively reducing a thickness of said layer of spacer material above said first active region; after selectively reducing said thickness of said layer of spacer material above said first active region, forming a first spacer element having a first width on sidewalls of said first structure and a second spacer element having a second width that is different than said first width on sidewalls of said second structure; and after forming said first and second spacer elements, performing an implantation sequence comprising a first implantation process performed at a first non-zero tilt angle to introduce a first dopant species into said first active region and a second implantation process performed at a second non-zero tilt angle that is different than said first non-zero tilt angle to introduce a second dopant species into at least said second active region.