Patent ID: 7273807

Claim:
A method for fabricating a semiconductor device, the method comprising: (a) stacking a lower dielectric layer and an upper dielectric layer on a semiconductor substrate; (b) etching the upper dielectric layer, thereby forming dielectric layer patterns that define damascene recesses, wherein an upper portion and a lower portion of each dielectric layer pattern has a first width; (c) etching the lower dielectric layer between the dielectric layer patterns to form first contact holes and etching the upper portion of each dielectric layer pattern to define a first upper portion and a second upper portion, wherein the first upper portions of the dielectric layer patterns have a second width and wherein the second upper portions of the dielectric layer patterns have the first width, wherein the second width is less than the first width; (d) filling the first contact holes with a first conductive material to form first contact plugs, filling the damascene recesses between the lower portions of the dielectric layer patterns with the first conductive material to form damascene interconnections on the first contact plugs and etching the first and second upper portions of the dielectric layer patterns so that only a portion of the second upper portions of each dielectric layer patterns protrudes above the damascene interconnections; (e) covering the damascene interconnections with a mask layer and planarizing the mask layer until the top surface of the dielectric layer patterns remaining after (d) are exposed; (f) selectively removing the exposed dielectric layer patterns and the lower dielectric layer under the exposed dielectric layer patterns to form second contact holes; and (g) filling the second contact holes with a second conductive material to form second contact plugs therein.