Patent ID: 7601622

Claim:
A method of forming a gate, the method comprising: forming a plurality of sidewall buffer patterns over a gate insulating layer formed on a substrate, wherein the plurality of sidewall buffer patterns are spaced apart from each other by a predetermined distance; depositing a sidewall layer on the sidewall buffer patterns and directly on the gate insulating layer; etching the sidewall layer such that sidewall patterns remain on sidewalls of the sidewall buffer patterns, wherein during the step of etching the sidewall layer, a critical dimension (CD) of a gate pattern is determined by a distance between the sidewall patterns, wherein the distance between the sidewall patterns is determined by both a width of a sidewall pattern of the sidewall patterns and a height of a sidewall buffer pattern of the sidewall buffer patterns; forming a gate by depositing a conductive layer on the gate insulating layer between the sidewall patterns; and etching all the sidewall buffer patterns and the sidewall patterns, wherein the sidewall buffer patterns are formed of a first insulator and the sidewall layer is formed of a second insulator, and wherein the gate insulating layer remains after etching the sidewall buffer patterns and the sidewall patterns.