Patent ID: 7231009

Claim:
A retiming circuit for transferring synchronous digital signals across an asynchronous boundary, the retiming circuit comprising: a first flip-flop having a first data input, a first clock input, and a first output, the first data input coupled to an external clock line, the first clock input coupled to a first phase of an internal clock, the first flip-flop operative to sample a signal on the external clock line according to the first phase of the internal clock; a second flip-flop having a second data input, a second clock input, and a second output, the second data input coupled to the external clock line, the second clock input coupled to a third phase of the internal clock, the second flip-flop operative to sample the signal on the external clock line according to the third phase of the internal clock; an inverter having an input and an output, the input coupled to the output of the first flip-flop; a NAND gate having at least one output providing an output signal and at least two inputs, a first input coupled to the output of the inverter, a second input coupled to the output of the second flip-flop, a third flip-flop having a third data input, a third clock input, and a third output, the third data input coupled to receive an incoming data signal, the third clock input coupled to a second phase of the internal clock, the third flip-flop operative to sample the incoming data signal according to the second phase of the internal clock; and a MUX having at least two data inputs, a control input, and an output, a first input coupled to directly receive the incoming data signal, while a second input is coupled to the output of the third flip-flop, and the control input is coupled to the output of the NAND gate, wherein the output of the MUX operative to produce an output signal as an unaltered incoming data signal or an incoming data signal sampled on a rising edge of the second phase of the internal clock depending on the output signal of the NAND gate.