Patent ID: 6927104

Claim:
A method of forming a double-gated transistor, comprising the steps of: a) providing a substrate having an SOI structure formed thereover; the SOI structure including a lower SOI oxide layer and an upper SOI silicon layer; b) forming a top oxide layer over the SOI structure; c) forming a first top dummy layer over the top oxide layer; d) patterning: I) the first top dummy layer; II) the top oxide layer; and III) the upper SOI silicon layer to form a patterned first top dummy layer/top oxide layer/upper SOI silicon layer stack having exposed side walls; the patterned upper SOI silicon layer including a source region and a drain region connected by a channel portion; e) forming a rounded oxide layer over the exposed side walls of the patterned upper SOI silicon layer; the formation of the rounded oxide layer also rounding the patterned upper SOI silicon layer; f) removing the patterned first top dummy layer exposing the patterned top oxide layer; g) forming a second patterned dummy layer over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer; the second patterned dummy layer having an opening that defines a gate area exposing: I) a portion of the oxide layer within the gate area; II) portions of the upper surface of the lower SOI oxide layer within the gate area; and III) a portion of the rounded oxide layer within the gate area; h) etching the exposed gate area portions of the upper surface of the lower SOI oxide layer into the lower SOI oxide layer to: I) form an undercut into the undercut lower SOI oxide layer exposing a bottom portion of the patterned upper SOI silicon layer within the gate area; II) remove the exposed gate area portion of the oxide layer exposing a top portion of the patterned upper SOI silicon layer within the gate area; and III) remove the portion of the rounded oxide layer within the gate area exposing a portion of the side walls of the patterned upper SOI silicon layer within the gate area; i) forming a conformal oxide layer over: I) the exposed bottom portion of the patterned upper SOI silicon layer within the gate area; II) the exposed top portion of the patterned upper SOI silicon layer within the gate area; and III) the exposed portion of the side walls of the patterned upper SOI silicon layer within the gate area; j) forming a gate within the second patterned dummy layer opening; the gate including an upper gate above the patterned upper SOI silicon layer within the gate area and a lower gate under the upper SOI silicon layer within the gate area; and k) removing the second patterned dummy layer to form the double-gated transistor.