Patent ID: 8593188

Claim:
A circuit, comprising: a phase frequency detector (PFD); an up current switch coupled to an output of the comparative phase detector; a down current switch coupled to an output of the comparative phase detector; a current source coupled through the up current switch to a node, a down current sourced coupled through the down current switch to a node, the node coupled to: a) a voltage controlled oscillator (VCO) wherein an output of the VCO is coupled to an input of the PFD, and b) a loop filter resistor bypass circuit, comprising: a loop filter resistor coupled to the node; a capacitor coupled in series with the loop filter resistor, the capacitor also coupled to ground; and a first bypass switch coupled to the node, and a second bypass switch coupled in series to the first bypass switch, the second bypass switch also coupled to an anode of the capacitor, wherein the first bypass switch and the second bypass switch in series are coupled in series with each other and in parallel to the loop filter resistor, wherein the loop filter resistor is employed to create a zero in the circuit to create a zero pole when the first and second bypass switches are not closed, and a first control line coupled from the up current switch to the first bypass switch; and a second control line coupled from the up current switch to the second bypass switch, wherein the first and second bypass switches are a complementary CMOS pair, wherein the loop filter resistor is employed to create a zero in the circuit and create the zero pole when the first and second bypass switches are not closed, and a noise of a loop filter resistor is bypassed when the loop filter resistor is bypassed.