Patent ID: 8325864

Claim:
A receiver circuit, comprising: an equalization circuit equalizing an input signal; a data decision circuit making a decision on an output signal of the equalization circuit in synchronization with a data decision clock signal; a first boundary decision circuit making a decision on the output signal of the equalization circuit based on a first boundary decision clock signal; a first phase adjustment circuit adjusting phases of the data decision clock signal and the first boundary decision clock signal according to a phase adjustment amount based on an output signal of the data decision circuit and an output signal of the first boundary decision circuit; a second boundary decision circuit making a decision on the output signal of the equalization circuit based on a second boundary decision clock signal; a second phase adjustment circuit adjusting a phase of the second boundary decision clock signal according to a result of adding the phase adjustment amount and a phase adjustment amount offset; and an adaptive equalization control circuit adjusting an equalization coefficient of the equalization circuit according to a data width of the output signal of the equalization circuit based on a logical comparison result between the output signal of the data decision circuit and an output signal of the second boundary decision circuit when the phase adjustment amount offset is changed, wherein the first phase adjustment circuit adjusts the phases of the data decision clock signal and the first boundary decision clock signal irrespective of the output signal of the second boundary decision circuit.