Patent ID: 7718500

Claim:
A method for forming a semiconductor device comprising the steps of: providing a N-doped field effect transistor (NFET) gate structure over a NFET region in a substrate and a P-doped field effect transistor (PFET) gate structure over a PFET region, wherein a gate structure comprises first and second spacers on sidewalls and a cap layer; providing NFET source drain extension (SDE) regions adjacent to said NFET gate; and providing PFET SDE regions adjacent to said PFET gate; forming recesses in said PFET region in the substrate adjacent to said PFET second spacers; forming a PFET embedded Source/drain stressor in the recesses; forming a NFET source drain (S/D) epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor, wherein the NFET S/D epitaxial layer comprises a faster growth rate than the PFET S/D epitaxial Si layer; removing the cap layer on the PFET and NFET gate structures and reducing second spacers of the gate structures to form reduced second PFET spacers and reduced second NFET spacers; and performing a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D epitaxial Si layer to form the raised NFET source/drains.