Patent ID: 8627044

Claim:
A method for issuing instructions with unresolved data dependencies in a processor, comprising: adding an entry for each in-flight instruction in the processor to a scoreboard; within an issue unit in the processor, keeping a record of each instruction that is directly or indirectly dependent on a base instruction by asserting a speculative not-there indicator in each entry in the scoreboard for an instruction that is directly or indirectly dependent on the base instruction; and upon determining that the base instruction has been deferred, monitoring instructions that are being issued from an issue queue to an execution unit for execution; and upon determining that an instruction from the record has reached a head of the issue queue, immediately issuing the instruction from the issue queue, wherein determining that the instruction from the record has reached the head of the issue queue comprises determining that the instruction from the record is an instruction for which the speculative not-there bit was set.