Patent ID: 8898553

Claim:
A method comprising: performing a plurality of read cycles on a plurality of memory cells of a memory; based on performing the plurality of read cycles on the plurality of memory cells of the memory, constructing a plurality of bin histograms, wherein each bin histogram of the plurality of bin histograms is associated with two corresponding threshold voltages, and wherein each bin histogram of the plurality of bin histograms reflects a count of memory cells of the memory that stores a voltage that is within the two corresponding threshold voltages associated with the corresponding bin histogram; identifying a first bin histogram of the plurality of bin histograms, wherein the plurality of bin histograms comprises (i) the first bin histogram and (ii) a plurality of neighboring bin histograms that neighbors the first bin histogram; and based on the plurality of neighboring bin histograms that neighbors the first bin histogram, determining a first log-likelihood ratio (LLR) for the first bin histogram, wherein the first LLR for the first bin histogram reflects a probability of the memory cells of the memory, which stores the voltage that is within the two corresponding threshold voltages associated with the first bin histogram, storing bit 0 or bit 1 .