Patent ID: 7295574

Claim:
A system adapted for coupling to a switch fabric and a central processor, the system comprising: a first integrated circuit having a first bus interface, a second bus interface, and a control interface, a data path extending from the first bus interface, through segmentation circuitry on the first integrated circuit, through reassembly circuitry on the first integrated circuit, and to the second bus interface; a second integrated circuit that is substantially structurally identical to the first integrated circuit, the second integrated circuit having a first bus interface, a second bus interface, and a control interface, the second integrated circuit having a data path extending from the first bus interface, through segmentation circuitry on the second integrated circuit, through reassembly circuitry on the second integrated circuit, and to the second bus interface; and a control integrated circuit having a first control interface coupled to the control interface of the first integrated circuit, having a second control interface coupled to the control interface of the second integrated circuit, and having a third interface adapted for coupling to the central processor, the control integrated circuit controlling a first flow of network information out of the first integrated circuit, the first flow passing over the data path of the first integrated circuit, the control integrated circuit controlling a second flow of network information out of the second integrated circuit, the second flow passing over the data path of the second integrated circuit, wherein in operation either the first bus interface of the first integrated circuit and the second bus interface of the second integrated circuit are coupled to the switch fabric or the second bus interface of the first integrated circuit and the first bus interface of the second integrated circuit are coupled to the switch fabric, wherein network information of the first flow is stored by the first integrated circuit in a plurality of first buffers, all of the first buffers having the same size, the control integrated circuit controlling the first flow of network information out of the first integrated circuit by supplying an indication of a first buffer to the first integrated circuit via the control interface of the first integrated circuit such that the first integrated circuit retrieves the contents of the first buffer and outputs the contents from the first integrated circuit, and wherein network information of the second flow is stored by the second integrated circuit in a plurality of second buffers, all of the second buffers having the same size, the control integrated circuit controlling the second flow of network information out of the second integrated circuit by supplying an indication of a second buffer to the second integrated circuit via the control interface of the second integrated circuit such that the second integrated circuit retrieves the contents of the buffer and outputs the contents from the second integrated circuit.