Patent ID: 8194792

Claim:
A clock and data recovery circuit (CDR) for recovery of an inputted analog signal, said circuit comprising: a data detector adapted to receive said inputted analog signal; a phase detector coupled to said data detector; a digital loop filter, coupled to said phase detector, comprising a low latency look-ahead path and a non-look-ahead path; a phase selection circuit (PSC), coupled to said digital loop filter, producing a recovered sampling clock signal that is inputted to the data detector; a threshold processor that is positioned at a location in the CDR circuit that is intermediate said phase detector and said PSC, said threshold processor receiving a threshold processor input signal and producing a threshold processor output; and an adjustment calculating means for converting said threshold processor output into a look-ahead timing adjustment that is supplied to the PSC over said low latency look-ahead path, wherein said look-ahead timing adjustment from said low latency look-ahead path is applied to said PSC prior to a non-look ahead timing adjustment from said non-look-ahead path for a given inputted analog signal, wherein said digital loop filter further comprises a higher latency path and wherein said circuit further comprises: remainder calculating means for calculating a remainder term based on inputted data comprising the threshold processor input signal and the threshold processor output; a multiplexer for selecting between the threshold processor input signal and the remainder term to yield a multiplexer output, which multiplexer output is processed by said higher latency path to yield said non-look-ahead timing adjustment; and, a circuit for combining said look-ahead timing adjustment and said non-look-ahead timing adjustment to provide a final timing adjustment that is supplied to the PSC.