Patent ID: 7782082

Claim:
A memory module comprising: a plurality of data inputs to couple to signal lines of an external data path; a first plurality of memory ICs; and a buffer integrated circuit (IC) including: a first interface coupled to the plurality of data inputs, a second interface coupled to the first plurality of memory ICs, a first termination circuit having a first load element and a first switch element to switchably couple the first load element to a first data input of the plurality of data inputs, a second termination circuit having a second load element and a second switch element to switchably couple the second load element to the first data input, and a configuration circuit to store, in response to control information from a memory controller, a first digital value and a second digital value, the first digital value being supplied to the first termination circuit to control an impedance of the first load element and the second digital value being supplied to the second termination circuit to control an impedance of the second load element.