Patent ID: 8160858

Claim:
A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit, comprising: (a) determining a plurality of vectors for a plurality of arcs, each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate; (b) selecting a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs; (c) performing circuit pruning for each of the plurality of substantially distinct vectors taking each one substantially distinct vector at a time, the circuit pruning includes identifying an active circuit for each vector, the active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors, wherein performing includes identifying one or more inactive nodes by performing a single circuit simulation to capture a switching behavior of the plurality of nodes; (d) performing circuit simulations limited to a plurality of transistors in the active circuit; (e) repeating (c) and (d) for remaining ones of the plurality of substantially distinct vectors; and (f) storing results of the circuit simulations on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.