Patent ID: 8321728

Claim:
An integrated circuit comprising: A. a TDI lead, a TDO lead, a TMS lead, and a TCK lead; B. test access port circuitry having a TDI input coupled to the TDI lead, a TDO output coupled to the TDO lead, a TMS input coupled to the TMS lead, and a TCK input coupled to the TCK lead; C. a data source having a data output; D. a data destination having a data input; and E. serial I/O circuitry having a TMS input coupled to the TMS lead, a TCK input and a TCK output coupled to the TCK lead, an input enable input, an output enable input, a data input connected to the data source data output, coupled to the TCK output, and being separate from the TDO lead, a data output connected to the data destination data input, coupled to the TCK input, and being separate from the TDI lead, the serial I/O circuitry including an I/O controller connected to the TMS input, the input enable input, and the output enable input, and the I/O controller having a load output connected to the data source and an update output connected to the data destination.