Patent ID: 8694812

Claim:
A method for providing reduced power consumption in a computer memory system, comprising: calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, wherein the second operating speed is higher than the first operating speed; operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system; and operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory, wherein the backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system; if cached write data is in the volatile memory when the backup power source provides power to the memory controller and the volatile memory, flushing cached write data from the volatile memory to a non-volatile memory by the memory controller, wherein the non-volatile memory is coupled to the memory controller, wherein the memory controller controls a buffer, wherein flushing cached write data from the volatile memory to the non-volatile memory by the memory controller comprises transferring data from the volatile memory to the non-volatile memory through the buffer, wherein the non-volatile memory receives power from the backup power source when there is a loss of main power to the computer memory system, wherein flushing cached write data comprises: transferring partial cached write data from the volatile memory to the buffer, wherein the partial cached write data has not been previously written to the non-volatile memory, wherein the partial cached write data is not greater than the size of the buffer, wherein the buffer receives power from the backup power source when the main power source does not provide power to the computer memory system; placing the volatile memo into a self-refresh mode; writing the partial cached write data from the buffer to the non-volatile memory; and determining if cached write data remains in the volatile memory that has not been written to the non-volatile memory; if cached write data that has not been written to the non-volatile memory remains in the volatile memory, taking the volatile memory out of the self-refresh mode and repeating the transferring, placing, writing, and determining steps; and if cached write data that has not been written to the non-volatile memory does not remain in the volatile memory, then foregoing providing power from the backup power source to the volatile memory, the buffer, the non-volatile memory, and the memory controller.