Patent ID: 7554621

Claim:
A nanostructured integrated circuit comprising: a substrate having a surface; a plurality of nanostructured elements coupled to the surface of the substrate, each nanostructured element including: an inner semiconductor material including a source portion and a drain portion; and an outer insulating layer formed on the inner semiconductor material; a thin film transistor (TFT) formed on the surface of the substrate, the TFT including: a first subset of the plurality of nanostructured elements arrayed together on the surface of the substrate; a source electrode electrically coupled to the source portion of the inner semiconductor material of each nanostructured element of the first subset of nanostructured elements; a drain electrode electrically coupled to the drain portion of the inner semiconductor material of each nanostructured element of the first subset of nanostructured elements; and a gate electrode formed on a gate portion of the outer insulating layer of each nanostructured element of the first subset of nanostructured elements; and a capacitor formed on the surface of the substrate, the capacitor including: a second subset of the plurality of nanostructured elements arrayed together on the surface of the substrate; a first capacitor electrode electrically coupled to one of the source electrode, the gate electrode, or the drain electrode; and a second capacitor electrode formed on a capacitor portion of the outer insulating layer of each nanostructured element of the second subset of nanostructured elements.