Patent ID: 8605500

Claim:
A multilevel nonvolatile semiconductor memory system comprising: a nonvolatile semiconductor memory; a controller which controls an operation of the nonvolatile semiconductor memory in a data program; and a data bus which connects the nonvolatile semiconductor memory to the controller; wherein the nonvolatile semiconductor memory comprises: a memory cell array with memory cells which have a bit assignment to 2 x (x is an integer number of 3 or more) threshold distributions, each memory cell storing x bits; and a control circuit which controls the data program of x bits to the memory cells; wherein the controller is configured to: execute the data program by first, second, and third steps; generate 2 y threshold distributions (y is an integer number and y<x) by the first step; and generate 2 x threshold distributions from 2 y threshold distributions by the second and third steps; wherein the controller comprises a data conversion circuit which generates y bit which indicates a write inhibition/permission from x bits by executing a logical operation of x bits in the first step; wherein the controller is further configured to: generate the 2 y threshold distributions based on y bit by transferring y bit to the nonvolatile semiconductor memory in the first step.