Patent ID: 8116165

Claim:
An integrated circuit comprising: at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells; a plurality of bit lines, each of said plurality of bit lines coupled to a respective column of said memory cells; a plurality of word lines each carrying a respective word line signal, each of said plurality of word lines coupled to a respective row of said memory cells to control coupling of said respective row of memory cells to said plurality of bit lines in dependence on said respective word line signal; word line driver circuitry configured to group together the word lines of at least three rows of memory cells, such that said word lines of said at least three rows of memory cells share a common word line signal, such that in a write operation a written data value written into said array of memory cells is written to at least three memory cells in said at least three rows of memory cells, said at least three memory cells having a shared bit line; and read circuitry coupled to said plurality of bit lines, said read circuitry configured such that in a read operation, in which said at least three memory cells are all coupled to said shared bit line by means of said common word line signal, a read data value is determined in dependence on a voltage of said shared bit line, wherein said voltage of said shared bit line is dependent on data values stored in said at least three memory cells, wherein if, at a time of said read operation, one of said at least three memory cells holds a complement value of said written data value, said voltage of said shared bit line nonetheless has a value such that said read data value is determined with the same value as said written data value.