Patent ID: 6850881

Claim:
A device for Connection Admission Control for an ATM switch, intended for admitting to the switch a requested ATM connection of the DBR type, such that the “Quality of service” of all ATM connections of the DBR type in said switch continues to satisfy certain conditions, in which a single buffer with capacity B is available for the composite traffic stream of DBR connections at an output port with capacity C, while as a boundary condition it holds that a total average load of the output port does not amount to more than ρ×C, where ρ is a constant with a value between 0 and 1, wherein the device comprises two first and second sub-devices which each emit a positive or negative admission signal, admission to the switch only being granted to the new ATM connection if both sub-devices issue a positive admission signal, wherein said first sub-device comprises: a first arithmetic unit which calculates a sum (ΣPCR) of nominal traffic parameters Peak cell Rate (PCR i ) of each of the ATM connections of the DBR type at a related output port, including a newly requested connection; and a second arithmetic unit which compares the calculated sum (ΣPCR) with the value of ρ×C, the result of the first sub-device being negative if ΣPCR is greater than ρ×C, and the result of the first sub-device being positive if ΣPCR is less than or equal to ρ×C; and wherein said second sub-device comprises: for each of the ATM connections of the DBR type at the related output port, including the newly requested connection, a third arithmetic unit, which calculates a buffer capacity b S,i , the value of b S,i being equal to zero if the product of the nominal Peak Cell Rate (PCR i ) and Cell Delay Variation Tolerance (CDVT i ) of the related connection is less than or equal to a constant K, and the value of b S,i , being equal to said product minus the value of K if said product is greater than K; a fourth arithmetic unit which calculates a sum (B S ) of the calculated values b S,i for all ATM connections at the related output port; a fifth arithmetic unit which calculates a buffer capacity B N , such that upon multiplexing of N independent, identical and ideal (CDVT=0) traffic streams, using a single buffer with a buffer capacity of B N , and assuming a maximum link load having a value of ρ, the average probability of cell loss as a result of buffer overflow will not exceed a given value of ε; a sixth arithmetic unit which calculates a product (B NK ) of the value of B N and the constant value K; a seventh arithmetic unit which determines a sum (B R ) of the calculated values for B S and B NK ; a comparison device which compares the calculated sum B R with the given capacity B of the output buffer, a positive admission signal being emitted if the value of B R is less than or equal to B, and a negative admission signal being emitted if the value of B R is greater than B.