Patent ID: 8023644

Claim:
A hardware architecture implemented in a monolithic integrated circuit for a block cipher comprising functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode, wherein the functional units comprise: a state register pipeline including a first given number of state registers, a block cipher pipeline including a second given number of block cipher modules, auxiliary data path arithmetic units and storage units for supporting the block cipher modes that need such units, and a commutation unit for receiving results from both the state register pipeline and the block cipher pipeline, and additionally for feeding results that are incomplete back into both the state register pipeline and the block cipher pipeline, until the results are complete, where the results are considered to be complete when one of, an input block of clear text is completely encrypted into cipher text according to at least one of the block cipher modes, and an input block of cipher text is completely decrypted into clear text according to at least one of the block cipher modes, wherein the block cipher modes comprise at least electronic code book, counter mode, cipher block chaining mode, output feedback mode, cipher feedback mode, and advanced encryption standard hash.