Patent ID: 7436231

Claim:
A memory device, comprising: a row address circuit coupled to receive and decode row address signals; a column address circuit coupled to receive and decode column address signals; a memory cell array structured to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals; a data path circuit structured to couple data signals corresponding to the data between the array and a respective data latch, each of the data latches being structured to couple the respective data signal between the data latch and an external data terminal of the memory device responsive to a data strobe signal, the data strobe signal based in part on an output clock signal; a command decoder structured to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being structured to generate control signals corresponding to the decoded command signals; and a phase-lock loop generating the data strobe signal responsive to an input clock signal, the phase-lock loop comprising: a phase detector comprising an first terminal coupled to receive the input clock signal and a second terminal coupled to receive a feedback clock signal, the phase detector structured to compare the input clock signal and the feedback clock signal and further structured to generate a phase error signal based on the comparison; a ring oscillator coupled to the phase detector, the ring oscillator comprising a plurality of delay elements, the plurality of delay elements coupled to each other structured to oscillate at a ring oscillation frequency, the ring oscillator coupled to receive the input clock signal and the phase error signal and generate a plurality of intermediate output clock signals, each of the plurality of delay elements structured to generate one of the intermediate output clock signals, each of the intermediate output clock signals having a different phase with respect to the input clock signal; and a clock serializer coupled to the ring oscillator, the clock serializer comprising a plurality of input terminals, each of the plurality of input terminals coupled to receive a respective intermediate output clock signal, the clock serializer being structured to generate an output clock signal having a frequency that is a multiple of the ring oscillation frequency, the feedback clock signal based at least in part on the output clock signal.