Patent ID: 8743633

Claim:
An integrated semiconductor device comprising: first and second semiconductor devices, wherein the first semiconductor device includes: a clock generation section adapted to generate a clock, first data storage sections adapted to store input data as transfer data to be transferred to the second semiconductor device in synchronism with the clock, data output terminals provided, one for each of the first data storage sections, to output the transfer data, and a clock output terminal adapted to output the clock as a transfer clock, and the second semiconductor device includes: data input terminals connected to the data output terminals to receive the transfer data, a clock input terminal connected to the clock output terminal to receive the transfer clock, second data storage sections each of which is associated with one of the data input terminals to store input data in synchronism with the transfer clock, and selection sections each of which is associated with one of the second data storage sections and selects either the transfer data received from the data input terminal or data shifted and output to the associated second data storage section in a first series circuit, the first series circuit being formed by successively connecting the second data storage sections in series, each of the selection sections supplying the selected data to the associated second data storage section, wherein the clock generation section generates the clock at a data transfer frequency for a predetermined data transfer speed so that the transfer data is transferred to the second semiconductor device at the predetermined data transfer speed, and wherein the first semiconductor device includes a first transfer data shift circuit formed by successively connecting in series one or more third data storage sections in a transmission path of the transfer data from the first data storage section to the data output terminal, the third data storage sections adapted to store input data in synchronism with the clock, wherein the clock generation section generates the clock that includes the number of pulses set based on the number of the third data storage sections so that the data stored in the first data storage section is shifted to and stored in the third data storage section at the final stage of the first transfer data shift circuit.