Patent ID: 8856579

Claim:
A method, comprising: (a) setting a read latency associated with a memory device to a first value, the read latency is a period of time between transmitting a read command and a beginning of a read window during which a memory controller captures data from the memory device; (b) changing a burst length of the memory device such that a data sequence transmitted by the memory device is greater than the amount of data that can be captured during the read window; (c) after changing the burst length, transmitting the read command to retrieve data from a predefined location in the memory device, wherein, in response to receiving the read command, the memory device transmits to the memory controller the data sequence; (d) capturing only a portion of the data sequence during the read window of the memory controller; (e) upon determining that the captured portion is different from predefined read data, adjusting the read latency by at least one clock cycle to shift the read window and to alter the portion captured at step (d); (f) repeating steps (c)-(e) until the captured portion is equal to the predefined read data; and (g) upon determining that the captured portion is equal to the predefined read data, performing normal operation of the memory device using the adjusted read latency and changing the burst length such that subsequent data sequences transmitted to the memory controller are equal to or less than the read window.