Patent ID: 7880173

Claim:
A CMIS device, comprising: a substrate having a (000-1) face or a face inclined from the (000-1) face; a first-conductive-type silicon carbide layer formed on said substrate; a high concentration impurity region formed in said first-conductive-type silicon carbide layer to provide an n-channel MISFET and a p-channel MISFET; a gate insulation film containing 1×10 19 /cm 3 to 1×10 22 /cm 3 of hydrogen formed on the first-conductive-type silicon carbide layer or on the first-conductive-type silicon carbide layer with a high concentration impurity region, wherein a hydrogen content in an interface between the gate insulation film and the first-conductive-type silicon carbide layer is 1×10 20 /cm 3 to 1×10 22 /cm 3 ; a gate electrode formed on said gate insulation film; and an ohmic electrode provided for the n-channel MISFET and the p-channel MISFET, the ohmic electrode being formed by heat treatment in an inert atmosphere containing hydrogen at a temperature in a range of 800° C. to 1000° C.