Patent ID: 7706113

Claim:
An electrostatic discharge (ESD) protection circuit for an integrated circuit device having overshoot and undershoot voltage protection during a power supply ramp-up of the integrated circuit device, the ESD protection circuit comprising a plurality of individual ESD protection circuits and each of the individual ESD protection circuits comprising: an ESD discharge circuit coupled between a power supply node and a ground supply node; a trigger circuit coupled to the ESD discharge circuit, the trigger circuit to transmit a turn-on signal to the ESD discharge circuit in the presence of a voltage spike during the power supply ramp-up and to transmit a turn-off signal to the ESD discharge circuit in the absence of a voltage spike during the power supply ramp-up; a delay circuit coupled between the ESD discharge circuit and the trigger circuit, the delay circuit to slow down the turn-off of the ESD discharge circuit to prevent an overshoot or undershoot voltage condition during the power supply ramp-up of the integrated circuit device; and a turn-off delay circuit coupled to the trigger circuit to establish a delay time for the transmission of the turn-off signal and wherein the delay time is different for each of the plurality of individual ESD protection circuits such that the turn-off signal transmission for each of the plurality of individual ESD protection circuits is staggered.