Patent ID: 8786081

Claim:
A semiconductor device, comprising: a substrate that contains a plurality of electronic components; an interconnect structure disposed over the substrate, the interconnect structure including a plurality of vias and interconnect lines; a passivation layer disposed over the interconnect structure; a plurality of conductive pads disposed between the interconnect structure and the passivation layer, the conductive pads being at least partially sealed by the passivation layer; a polymer layer disposed over the passivation layer; a plurality of post-passivation interconnect (PPI) components disposed between the passivation layer and the polymer layer; a first conductive component and a second conductive component each disposed over the polymer layer, wherein a material composition of the first conductive component is substantially similar to a material composition of the second conductive component; a solder component that is disposed on the first conductive component, the solder component being electrically coupled to the first conductive component; wherein the second conductive component is free of a formation of any solder component thereon.