Patent ID: 8304915

Claim:
A semiconductor device comprising: at least a semiconductor element comprising electrode terminals on a surface thereof; and a coreless substrate including enclosed therein said semiconductor element; said coreless substrate including a plurality of stacked interconnect layers and a plurality of stacked insulation layers, interconnects formed in said interconnect layers, vias formed in each one of said insulation layers and that electrically interconnect said interconnects above and below each of said insulation layers, and external connection terminals on a surface thereof; wherein said semiconductor element is embedded in one of said insulation layers; each of said external connection terminals and each of said electrode terminals are electrically interconnected via at least one of said interconnects or said via; said insulation layers and said interconnect layers are stacked on one side of said semiconductor element; and at least one of said vias has a cross-sectional shape different from that of the via provided in another one of said insulation layers or at least one of said interconnects has a cross-sectional shape different from that of the interconnect provided in another one of said insulation layers.