Patent ID: 7859885

Claim:
A phase change memory device, comprising: a substrate; a plurality of cell arrays stacked above said substrate and each including a matrix layout of a plurality of memory cells, each of said memory cells storing therein as data a resistance value determinable by a phase change; a write circuit configured to write to a pair cell constituted by two neighboring memory cells within said plurality of cell arrays to write into one cell of said pair cell a high resistance value state and write into the other cell a low resistance value state; and a read circuit configured to read complementary resistance value states of said pair cell as one bit of data, wherein each of said cell arrays has a plurality of mutually parallel first wiring lines and a plurality of second wiring lines disposed to cross said first wiring lines while being insulatively isolated from said first wiring lines, and each of said memory cells has a chalcogenide and a diode being stacked at each cross portion of said first wiring lines and said second wiring lines.