Patent ID: 7545046

Claim:
A semiconductor device comprising: a first and a second conducting line pattern disposed on a semiconductor substrate, each conducting line pattern including a conducting line having a sidewall and a conducting line capping layer pattern having a sidewall, the conducting line capping layer stacked thereon; a first and a second conducting line spacer disposed on each of the conducting line patterns, the first conducting line spacer covering a portion of the sidewall of the first conducting line pattern, and the second conducting line spacer covering a portion of the sidewall of the second conducting line pattern; a landing pad disposed between the first and the second conducting line patterns and protruding upward from upper surfaces of the first and the second conducting line patterns, wherein the landing pad is disposed to contact the conducting line capping layer pattern and spaced from the conducting line with a predetermined distance, and each of the first and the second conducting line patterns has a trench with an open end that faces towards a sidewall of the landing pad, the trench being between the conducting line capping layer pattern and the conducting line.