Patent ID: 8826087

Claim:
An integrated circuit comprising: scan test circuitry comprising at least one scan chain having a plurality of scan cells; additional circuitry subject to testing utilizing the scan test circuitry; and control circuitry associated with the scan test circuitry and coupled to at least a given one of a primary input of the integrated circuit and a primary output of the integrated circuit; wherein the scan test circuitry is configurable by the control circuitry so as to permit testing of both an input functional path associated with the given one of the primary input and the primary output and an output functional path associated with the given one of the primary input and the primary output; wherein one of: (i) the given one of the primary input and the primary output is the primary input, wherein the scan test circuitry is configurable by the control circuitry in a first state in which the input functional path associated with the primary input is tested and in a second state in which the output functional path associated with the primary input is tested; and (ii) the given one of the primary input and the primary output is the primary output, wherein the scan test circuitry is configurable by the control circuitry in a first state in which the output functional path associated with the primary output is tested and in a second state in which the input functional path associated with the primary output is tested.