Patent ID: 7772881

Claim:
An integrated circuit (IC) having in-system programmability (ISP) capability for updating a logic block of the IC, comprising: a first memory region for receiving an in-system update to a configuration of the IC; a second memory region for storing user non-configuration data; and a core logic region in communication with the first memory region, the core logic region including, interface logic for communicating with the first memory region; an ISP detection block in communication with the interface logic; and a controller in communication with the interface logic and the logic block, wherein when the first memory region receives the in-system update, a trigger signal is transitioned to cause the controller to read data within the logic block and store the read data into the second memory region and wherein the update to the configuration is transmitted into the core logic region and upon completion of the transmission, the ISP detection block triggers the logic block to reload register data from the second memory region through the controller when the device's registers have been cleared.