Patent ID: 7898036

Claim:
A semiconductor device comprising: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; source and drain extension regions formed in the semiconductor substrate on a first and a second side corresponding to a first sidewall surface and a second sidewall surface of the gate electrode; a first piezoelectric material pattern formed on the semiconductor substrate that continuously covers the first sidewall surface of the gate electrode from the first side of the gate electrode; a second piezoelectric material pattern formed on the semiconductor substrate that continuously covers the second sidewall surface of the gate electrode from the second side of the gate electrode; source and drain regions formed in the semiconductor substrate outside the source extension region and the drain extension region, respectively; and a contact for applying a voltage to the first and the second piezoelectric material patterns, wherein a source contact is formed in the source region, a drain contact is formed in the drain region, and a gate contact is formed on the gate electrode, and the source contact is in contact with the first piezoelectric material pattern, the drain contact is in contact with the second piezoelectric material pattern, and the gate electrode is in contact with the first and the second piezoelectric material patterns.