Patent ID: 7126839

Claim:
A nonvolatile ferroelectric memory cell which has multi write and multi read ports, comprising: a pull-up regulator for providing a power voltage in response to a pull-up enable signal; a first latch unit, cross-coupled between both storage nodes of the cell, for latching a power voltage applied from the pull-up regulator; a write port selector for selectively outputting data applied through a plurality of write bitline pairs into both storage nodes in response to each wordline driving signal applied through a plurality of write port wordlines; a ferroelectric capacitor unit for generating a voltage difference in both storage nodes in response to a cell plate signal, and for storing the data; a read port selector for selectively outputting data stored in the ferroelectric capacitor unit into a plurality of read bitline pairs in response to each wordline driving signal applied through a plurality of read port wordlines; a pull-down regulator for providing a ground voltage in response to a pull-down enable signal; and a second latch unit, cross-coupled between both storage nodes, for latching the ground voltage applied from the pull-down regulator.