Patent ID: 7973302

Claim:
A memory comprising: a substrate; segmented heaters over said substrate; first stop layer edge portions positioned respectively on respective first edges of the heaters; second stop layer edge portions positioned respectively on respective second edges of the heaters, each first stop layer edge portion being spaced apart from each second stop layer edge portion; first sidewall spacers positioned respectively over the first stop layer edge portions, each first stop layer edge portion being positioned between a corresponding one of the first sidewall spacers and a corresponding one of the first edges of said segmented heaters; second sidewall spacers positioned respectively over the second stop layer edge portions, each second stop layer edge portion being positioned between a corresponding one of the second sidewall spacers and a corresponding one of the second edges of said segmented heaters, respective pairs of the first and second sidewall spacers and respective pairs of the first and second stop layer edge portions defining respective sublithographic pores, each pore being defined on a first side by a respective one of the first stop layer edge portions and the corresponding one of the first sidewall spacers, and each pore being defined on a second side opposite to the first side, by a respective one of the second stop layer edge portions and the corresponding one of the second sidewall spacers; and chalcogenide memory regions in said pores.