Patent ID: 7908402

Claim:
An integrated circuit (IC) comprising: one or more terminals configured to couple to respective predefined voltage levels to define a prescribed operation of the IC; a bus interface configured to couple to a bus to transmit and receive data to and from the bus; an address register configured to store a first address uniquely identifying the IC, wherein a first portion of the first address identifies a first group; and a mask register configured to leave the first portion of the first address unmasked while masking a remaining portion of the first address to identify the IC as a member of the first group; wherein the IC is configured to operate as a bus master as part of its prescribed operation, and initiate a first bus operation on the bus by transmitting the first address onto the bus through the bus interface; and wherein the IC is further configured to receive data from the bus through the bus interface in response to the first bus operation, wherein the received data comprises status information indicative of the operation of one or more point-of-load (POL) regulators that are members of the first group.