Patent ID: 8452824

Claim:
A circuit comprising: a logic unit for performing any selected Boolean operation in parallel on respective bits of a first multi-bit operand input and a second multi-bit operand input, the selected Boolean operation being defined by a particular combination of well defined binary control signals (ctl 0 , ctl 1 , ctl 2 , ctl 3 ) provided to said logic unit, said logic unit containing a plurality of binary logic units, each applying the selected Boolean operation to a respective bit input signal (va) of said first operand input and a respective bit input signal (vb) of said second operand input, each binary logic unit comprising: three 2:1 multiplexers, a first multiplexer and a second multiplexer arranged in parallel to each other and a third multiplexer arranged in series to the first multiplexer and second multiplexer, wherein the respective bit input signal (va) of said first operand input and its inverting (!va) are applied on the control inputs of the first multiplexer and second multiplexer, said control signals ctl 0 and ctl 1 are applied on the signal inputs of the first multiplexer and said control signals ctl 2 and ctl 3 are applied on the signal inputs of the second multiplexer, wherein the respective bit input signal (vb) of said second operand and its inverting (!vb) are applied on the control inputs of the third multiplexer, wherein the output signal (vo 1 ) of the first multiplexer is applied on a first data input of the third multiplexer, wherein the output signal (vo 2 ) of the second multiplexer is applied on a second data input of the third multiplexer, and wherein the output (vo) of the third multiplexer represents the respective bit result of the selected Boolean operation specified by the four control signals (ctl 0 , ctl 1 , ctl 2 , ctl 3 ) that is applied on the two respective bit input signals (va, vb).