Patent ID: 8461884

Claim:
A programmable delay circuit to delay a first digital value by a delay magnitude, said programmable delay circuit comprising: a phase lock loop (PLL) operable to generate a plurality of clock signals, wherein each clock signal within said plurality of clock signals has a same frequency and a different relative phase; a clock selection block operable to select one of a said plurality of clock signals as a selected signal; a synchronization circuit operable to provide said first digital value synchronized with an edge of said selected signal, wherein said first digital value comprises a sequence of digital values received according to an input clock signal and wherein said synchronization circuit comprises a first pair of sequential circuits, each operable to store alternate values of said sequence of digital values, and wherein said synchronization circuit comprises a second pair of sequential circuits, each operable to receive a digital value stored by one of said first pair of sequential circuits, associated therewith, using said selected signal; and a control unit operable to cause said clock selection block to select one of said plurality of clock signals based on said delay magnitude.