Patent ID: 8742584

Claim:
A semiconductor device comprising: a semiconductor substrate; a first metal layer being a pad metal la er of the semiconductor device; a second metal layer disposed between the first metal layer and the semiconductor substrate; a third metal layer disposed between the first metal layer and the second metal layer; a first interlayer insulation film disposed between the second metal layer and the third metal layer; and a plurality of first vias penetrating the first interlayer insulation film for electrically connecting the second metal layer to the third metal layer, the plurality of first vias disposed outside of a plane defined by an outer periphery of the first metal layer extending below the first metal layer; a second interlayer insulation film provided between the first metal layer and the third metal layer; and a plurality of second vias penetrating the second interlayer insulation film, wherein two of the first vias are aligned so that a shortest distance therebetween passes directly under the first metal layer, and an interval between the two of the first vias is larger than a width of the first metal layer, and an interval between two of the second vias not having others of the second vias electrically connecting the first metal layer to the third metal layer therebetween.