Patent ID: 8306173

Claim:
A clock regeneration circuit that generates a clock signal that is synchronized to an input signal, comprising: a detection section which detects points at which the input signal transitions; a histogram generation section which associates a plurality of partial periods with the transition points, and generates a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal; a calculation processing section which extracts a portion of the partial periods from the partial periods constituting the first histogram based on the incidence of the transition points, the calculation processing section generating a second histogram indicating the incidence of the transition points only for each of the portion of the partial periods, and the calculation processing section calculating a phase adjustment value of the clock signal based on a temporal location of the partial period corresponding to a center of a temporal range, among the portion of the partial periods constituting the second histogram; and a phase adjustment section which adjusts a phase of the clock signal based on the phase adjustment value.