Patent ID: 8806397

Claim:
A semiconductor manufacturing method of generating a layout for a device, comprising: for each of a plurality of active regions of a first layout, defining a plurality of elongate mandrels that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction, each active region of the plurality of active regions having sides; for each adjacent pair of partially-parallel active regions of the plurality of active regions having a minimum distance less than a specified minimum spacing, connecting at least a portion of nearest ends of pairs of elongate mandrels, each mandrel of a pair from a different active region of the adjacent pair of partially-parallel active regions; and, generating a second layout using a layout-generating machine, said second layout including the plurality of active regions, a plurality of elongate mandrels in the plurality of active regions, and connective elements between active regions of at least one adjacent pair of partially-parallel active regions.