Patent ID: 7719334

Claim:
An apparatus comprising: a module configured to receive a clock signal having a first frequency and to generate a first intermediate signal and a second intermediate signal having edges delayed from first edges of the clock signal, each of the first and second intermediate signals having a second frequency that is half of the first frequency, the first and second intermediate signals having a phase difference of about 180° from each other; a first delay element configured to delay the first intermediate signal by a first delay amount to generate a first phase clock signal; a second delay element configured to delay the first intermediate signal by a second delay amount different than the first delay amount to generate a second phase clock signal, wherein the first and second phase clock signals have a phase difference of about 90° from each other; a third delay element configured to delay the second intermediate signal by a third delay amount to generate a third phase clock signal, the third delay amount being substantially the same as the first delay amount, wherein the first and third phase clock signals have a phase difference of about 180° from each other; and a fourth delay element configured to delay the second intermediate signal by a fourth delay amount to generate a fourth phase clock signal, the fourth delay amount being substantially the same as the second delay amount, wherein the first and fourth phase clock signals have a phase difference of about 270° from each other.