Patent ID: 7551514

Claim:
A semiconductor memory device comprising: a plurality of counters configured to count the number of data bits and flag information data bits having a first logic state in a first data group including at least one data bit and second through nth data groups each including at least one data bit and a flag information data bit; and a data coding unit communicating with said plurality of counters, said data coding unit selectively applying a first operation mode and a second operation mode to each of the first through nth data groups, said data coding unit coding data of each of the first through nth data groups wherein the first operation mode codes the data of each of the first through nth data groups to minimize the number of data bits in the first logic state in each of the first through nth data groups, and the second operation mode codes the data of each of the first through nth data groups to minimize the difference between the number of data bits and flag information data bits in the first logic stage and the number of data bits and flag information data bits in a second logic state associated with the first through nth data groups.