Patent ID: 7486541

Claim:
A memory cell for reducing soft error rate comprising: a first bit line signal (BL); a second bit line signal complementary to the first bit line signal (BLB); a first pass gate coupled to the BL; a second pass gate coupled to the BLB; a first inverter whose output node receives the BL through the first pass gate; a second inverter whose output node receives the BLB through the second pass gate; a first instrument coupled between the output node of the first inverter and an input node of the second inverter; and a second instrument coupled between the output node of the second inverter and an input node of the first inverter; wherein the first and second instruments increase voltage discharge time of the memory cell when voltages at the output nodes of the inverters accidentally discharge; and wherein the first and second instruments are located adjacent to respective PMOS portions of said first and second inverters, said PMOS portion of said first inverter being located between the first instrument and an NMOS portion of said first inverter, said PMOS portion of said second inverter being located between the second instrument and an NMOS portion of said second inverter, said first and second instruments operable for providing a resistor capacitor delay time for reducing soft error rate.