Patent ID: 8184029

Claim:
A phase interpolation interface circuit, comprising: a first supply-coupled node; a second supply-coupled node; a first group of transistors having first source/drain nodes and second source/drain nodes, wherein the first source/drain nodes are coupled together at the first supply-coupled node; a second group of transistors having third source/drain nodes and fourth source/drain nodes, wherein the third source/drain nodes are coupled together at the second supply-coupled node; wherein each of the first group of transistors are coupled to a corresponding one of the second group of transistors at a corresponding second source/drain node and a corresponding fourth source/drain node to form a corresponding one of a plurality of transistor pairs; a current source network coupled to ground and also to the second source/drain nodes of the first group of transistors and the fourth source/drain nodes of the second group of transistors; and wherein the current source network includes a plurality of current sources associated with the plurality of transistor pairs for providing multiple channels; and wherein at least two of the current sources are coupled to receive respective bias strength signals that are provided by a single digital-to-analog converter (“DAC”).