Patent ID: 7380076

Claim:
An information processing apparatus that can access an address in a memory which address is specified by a row address set using an active command and a column address set by a read command or a write command, wherein if at least either read commands or write commands are successively issued for data at the same row address, a succeeding read command or write command is issued without issuing a precharge command or an active command after a preceding read command or write command, and if a read instruction and then a write instruction are indicated on data at the same row address, a read command is issued during a cycle immediately after a write command has been completely issued, by replacing the read instruction with the write instruction, characterized in that the information processing apparatus comprises: an address delay section for outputting an input memory address of a rewrite target after a delay of predetermined cycles; an address selecting section for selectively outputting the memory address delayed by the address delay section or an input current memory address; a rewrite target data holding section for reading and holding data in the memory which is to be rewritten; a data calculating section for rewriting the data to be rewritten where the data is held in the rewrite target data holding section; and a control section for causing the data calculating section to output the data rewritten by the data calculating section to the memory, while simultaneously causing the address selecting section to select the memory address delayed by the address delay section, and causing the rewrite target data holding section to read data from the memory, while simultaneously causing the address selecting section to select the input current memory address.