Patent ID: 7074656

Claim:
A method of forming multiple-gate transistors of the same conductivity type, the method comprising: providing a first semiconductor fin with a first orientation and a second semiconductor fin with a second orientation overlying an insulator layer, each of the first and second semiconductor fins having a top surface and two sidewall surfaces; masking the second semiconductor fin; doping the first semiconductor fin by implanting dopant ions of a first conductivity type thereby forming source/drain regions of the first conductivity type in the second semiconductor fin; masking the first semiconductor fin; and doping the second semiconductor fin by implanting dopant ions of the first conductivity type thereby forming source/drain regions of the first conductivity type in the first semiconductor fin; wherein the source/drain regions of the first conductivity type in the first semiconductor fin comprise source/drains region of a transistor of the first conductivity type and wherein the source/drain regions of the first conductivity type in the second semiconductor fin comprise source/drain regions of a transistor of the first conductivity type.