Patent ID: 7246197

Claim:
A method for use in a processor having multiple multi-threaded programmable engines integrated within the processor: at a first thread of a one of the multiple multi-threaded engines: performing a first thread lookup of a tag in a content addressable memory (CAM) within the one of the multiple multi-threaded engines; if the first thread lookup results in a lookup miss of the tag in the CAM: initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines into locations in storage internal to the one of the multiple multi-threaded engines: writing an entry for the tag into the CAM; and if the first thread lookup results in a lookup hit of the tag in the CAM: modifying data at at least one of the locations in the storage internal to the one of the multiple multi-threaded engines without initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines; at a second thread of the one of the multiple multi-threaded engines: performing a second thread lookup of the tag in a content addressable memory (CAM) within the one of the multiple multi-threaded engines; if the second thread lookup results in a lookup miss of the tag in the CAM: initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines into locations in storage internal to the one of the multiple multi-threaded engines; writing an entry for the tag into the CAM; and if the second thread lookup results in a lookup hit of the tag in the CAM: modifying data at at least one of the locations in the storage internal to the one of the multiple multi-threaded engines without initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines.