Patent ID: 8027825

Claim:
A design structure embodied in a machine readable storage device, wherein the design structure is loaded from the storage device into a computer for designing, manufacturing, or testing integrated circuitry, the design structure comprising: a first data structure that when executed generates a general purpose computational resource for performing general purpose operations; and a second data structure that when executed generates a special purpose computational resource coupled to the general purpose computational resource, for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry, wherein the test patterns specify an expected value of the simulated operation; executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns; determining whether the expected value is different from a measured value of the simulated operation; and modifying the test patterns in response to a determination that the expected value is different from the measured value.