Patent ID: 8493102

Claim:
An apparatus comprising: a first current buffer comprising: a first input configured to receive a non-inverted input signal current; a second input configured to receive an inverted input signal current; a first transistor of a first type, the first transistor having a base, an emitter, and a collector or a gate, a source, and a drain, wherein the base or gate of the first transistor is coupled to the first input; a second transistor of the first type, the second transistor having a base, an emitter, and a collector or a gate, a source, and a drain, wherein the base or gate of the second transistor is coupled to the second input; a first current source having an end coupled to the emitter or source of the first transistor; a second current source having an end coupled to the emitter or source of the second transistor; a first resistor having a first end coupled to the base or gate of the first transistor and a second end coupled to a reference voltage; a second resistor having a first end coupled to the base or gate of the second transistor and a second end coupled to the reference voltage; a third transistor of a second type different from the first type, the third transistor having a base, an emitter, and a collector or a gate, a source, and a drain, wherein the base or gate of the third transistor is coupled to the emitter or source of the first transistor, wherein the emitter or source of the third transistor is coupled to the base or gate of the second transistor, wherein the collector or drain of the third transistor is configured to provide a non-inverted output current signal; and a fourth transistor of the second type, the fourth transistor having a base, an emitter, and a collector or a gate, a source, and a drain, wherein the base or gate of the fourth transistor is coupled to the emitter or source of the second transistor, wherein the emitter or source of the fourth transistor is coupled to the base or gate of the first transistor, wherein the collector or drain of the fourth transistor is configured to provide an inverted output current signal.