Patent ID: 8661225

Claim:
A method of handling vector instructions within a data processing apparatus comprising a register data store having a plurality of registers arranged to store data elements, and a vector processing unit for executing a sequence of vector instructions, the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of said sequence of vector instructions, the method comprising the steps of: maintaining within a skip indication storage a skip indicator for each of said lanes of parallel processing; responsive to a vector skip instruction within said sequence of vector instructions, performing an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes of said plurality of lanes; responsive to a vector operation instruction within said sequence of vector instructions, performing an operation in parallel on data elements input to said plurality of lanes of parallel processing, but excluding from the performance of said operation any lane whose associated skip indicator is set; each said skip indicator comprising a skip count value which is considered set when having a non-zero value and is considered not set when having a zero value; responsive to the or skip instruction, setting the skin count value for said determined one or more lanes to a predetermined non-zero value; and for each vector instruction within said sequence, if said skip count value is set at the time that vector instruction is executed, decrementing the skip count value instead of performing the operation specified by that vector instruction.