Patent ID: 7079412

Claim:
A programmable metal-oxide-semiconductor (MOS) memory circuit comprising: a data read module having a first output and a second output based on a voltage difference between a first input and a second input; a first polycrystalline resistor having a first end connectable to a first control voltage level, and a second end connected to a second control voltage level; a second polycrystalline resistor having a first end connectable to a first control voltage level, and a second end connected to a second control voltage level; and a connection module for connecting the first ends of the first and second resistors to the first and second inputs respectively, wherein the first and second control voltage levels are imposed to program either the first or second resistor by causing a current stress across the resistor, and wherein the first and second outputs of the data read module produce voltage results representing the programmed value of the first or second resistor when the connection module is enabled.