Patent ID: 7397880

Claim:
A synchronization circuit, comprising: a reference pulse signal line to receive a reference pulse signal; a frequency dividing circuit to divide a frequency of the reference pulse signal according to a predetermined frequency dividing ratio, to output a frequency-divided reference pulse signal; a first variable delay circuit to generate a first pulse signal to be synchronized with the frequency-divided reference pulse signal outputted from the frequency dividing circuit; a first phase comparing circuit to compare the frequency-divided reference pulse signal with the first pulse signal; a frequency dividing/distributing circuit to divide the frequency of the reference pulse signal and to generate multiphase clocks according to the predetermined frequency dividing ratio; a second variable delay circuit which is configured to have a substantially identical structure to that of the first variable delay circuit, and which includes a plurality of stages to respectively delay the multiphase clocks outputted from the frequency dividing/distributing circuit; a waveform combining circuit to generate a second pulse signal corresponding to the reference pulse signal in response to receipt of a delayed output from the plurality of stages in the second variable delay circuit; and a control voltage generating circuit to generate control voltages to control the first variable delay circuit and the second variable delay circuit in response to receipt of a comparison output of the first phase comparing circuit, wherein a frequency of the first pulse signal and a frequency of the multiphase clocks are divided into a lower frequency than that of the reference pulse signal so as to prevent deformation or disappearance of outputs of the first variable delay circuit and the second variable delay circuit.