Patent ID: 7649761

Claim:
A semiconductor memory device, comprising: a memory cell array arranged in a memory cell array region and including a plurality of memory cells formed at intersections of word lines extending in a first direction and bit lines extending in a second direction orthogonal to said first direction; a data cache array arranged in a data cache array region and including data caches arrayed to temporarily store data read out of said memory cells; a plurality of shunt regions formed at certain intervals in said memory cell array region as extending in said second direction and each including a contact formed to connect said word line or a signal line wired in the same direction to another metal wire; a plurality of extension regions each formed of an extension of said shunt region into said data cache array region; a plurality of data input/output lines formed extending in said first direction and arranged to simultaneously transfer data on said simultaneously selectable bit lines via said data cache array; and a plurality of sense circuits arranged around said data cache array and connected to said plurality of data input/output lines respectively, wherein said data input/output lines are divided at a certain interval in said first direction, wherein said divided portions are connected to respective leads formed in said extension region in the longitudinal direction thereof and connected to said sense circuits via said leads.