Patent ID: 8549448

Claim:
A method of designing a circuit layout, the circuit layout for use in forming a lithographic mask set for use in fabricating an integrated circuit, the method for use by a computer system having a processor and memory, the method comprising: the computer system determining critical paths in a synthesized circuit design of the integrated circuit; the computer system dividing the synthesized circuit design of the integrated circuit into a plurality of cell partitions along the critical paths of the synthesized circuit design of the integrated circuit; the computer system associating pins of the plurality of cell partitions along the critical paths of the synthesized circuit design of the integrated circuit with normalized pin timing values, the normalized pin timing values storing magnitude differences between a reference timing slack and timing slacks of the plurality of pins; after optimizing the synthesized circuit design of the integrated circuit, the computer system re-determining the critical paths in the synthesized circuit design of the integrated circuit, and repeating said dividing and said associating, and then the computer system determining whether to further optimize the plurality of cell partitions by comparing: (i) pre-optimization normalized pin timing values of the plurality of cell partitions with (ii) post-optimization normalized pin timing values of the plurality of cell partitions.