Patent ID: 8218705

Claim:
An interpolating phase detector array for comparing a phase of a reference clock signal with phases of a set of K phase shifted clock signals and generating a phase error output signal, the interpolating phase detector array comprising: a plurality of N phase detector columns, each column including: a plurality of M exclusive-OR (XOR) blocks, each block having: inputs for receiving the reference clock signal, receiving two of the phase shifted clock signals, receiving “coarse” control signals for enabling said received phase shifted clock signals; and a phase error output; a steerable current source having first and second current sink outputs for delivering a bias current to two distinct sets of XOR blocks, and having an input to receive a “fine” control signal for directing the bias current to one of said distinct sets; and a current output IOUT for delivering the phase error output signal formed by joining phase error outputs of the plurality of M XOR blocks; wherein M and N are natural numbers, which are equal or greater than 2, and K=2M.