Patent ID: 8832343

Claim:
A system comprising: an inter-integrated circuit (I2C) master device coupled to a master I2C bus; an I2C multiplexer coupled to the master I2C bus; a plurality of slave I2C busses coupling the I2C multiplexer to a plurality of I2C slave devices, wherein each of the slave I2C busses comprises a bidirectional serial data (SDA) line and bidirectional serial clock (SCL) line, wherein each of the slave I2C busses has a first channel and a second channel, wherein the first channel puts bidirectional serial data on the bidirectional SDA line and clock signals on the bidirectional SCL line, wherein the second channel puts bidirectional serial data on the bidirectional SCL line and clock signals on the bidirectional SDA line, and wherein each of the slave I2C busses is coupled to two I2C slave devices; and a channel selector associated with the I2C multiplexer, wherein the channel selector selectively couples the I2C master device to one of the two I2C slave devices via the first channel or the second channel.