Patent ID: 7566603

Claim:
A method for manufacturing a semiconductor device comprising: forming a plurality of gate stacks over a semiconductor substrate having a cell region and a peripheral region; forming a gate spacer layer around a sidewall of each gate stack in the cell region and forming the gate spacer layer over a surface of the semiconductor substrate and around a sidewall of each gate stack in the peripheral region; filling an insulation layer between the gate stacks; removing the insulation layer in the cell region, and forming a plurality of landing plugs between the gate stacks in the cell region; removing the insulation layer in the peripheral region by using a mask layer pattern as an etching mask, the mask layer pattern being configured to expose the peripheral region while covering the cell region; forming a sacrificial insulation layer throughout the cell region having the plurality of landing plugs and the peripheral region having no insulation layer; removing the sacrificial insulation layer formed over the cell region and the sacrificial insulation layer over the substrate in the peripheral region, to expose the gate spacer layer formed over the surface of the semiconductor substrate in the peripheral region; removing the exposed gate spacer layer in the peripheral region, to expose the semiconductor substrate between the gate stacks in the peripheral region; and forming a metal silicide layer over an exposed surface of the semiconductor substrate in the peripheral region.