Patent ID: 7895399

Claim:
A computer system, comprising: a main memory that stores: a program including one of a prefetch command and a load command; and data used in the program; and a processor that reads the program and the data from the main memory and executes the program, wherein: the processor includes: a plurality of processor cores that execute the program; a shared cache that stores the data on the main memory in predetermined units of data storage; and a prefetch unit that pre-reads the data into the shared cache from the main memory on the basis of a request for prefetch from a first processor core of the processor cores; the prefetch unit includes: shared cache management information including: a first area in which a respective storage state is held for each predetermined unit of data storage of the shared cache; and a second area for reserving the request for prefetch; and a prefetch control unit that instructs the shared cache to perform one of reserving the request for prefetch and executing the request for prefetch from the first processor core on the basis of the respective storage states held for the predetermined units in the shared cache, the prefetch command includes a first address of data on the main memory and a number indicating a quantity of two or more of the processor cores that share the data of the first address on the main memory; the shared cache includes: a data storage area in which the data on the main memory and the number of processor cores are stored for each of the predetermined units of data storage that correspond to the first address; and a shared cache control unit that reads the data from the first address on the main memory and stores the data of the first address on the main memory into the predetermined units of data storage that correspond to the first address based on the request for prefetch sent from the prefetch control unit; one of the processor cores instructs, upon the load command being executed, the shared cache control unit to read out an address included in the load command; the shared cache control unit stores the number of processor cores indicated by the request for prefetch in the data storage area in association with the data read from the first address on the main memory; and the shared cache control unit includes: a readout unit that, when data of the address included in the load command is stored in the data storage area of the shared cache, transfers the data of the address included in the load command to the instructing processor core and reduces the number of processor cores that share the data of the first address in the data storage area; and an updating unit that caches out the data of the first address on the data storage area when the number of processor cores that share the data reaches a predetermined value.