Patent ID: 8346201

Claim:
An asynchronous first in first out (FIFO) interface having a readout clock asynchronous with a write clock, comprising: a buffer for receiving a digital signal from an analog-to-digital converter (ADC) according to the write clock and outputting the digital signal to a processor according to the readout clock; a clock controller for outputting a clock control signal according to an amount of data stored in the buffer; a reference source for providing a reference clock with an oscillation frequency; and a signal source for dividing the frequency of the reference clock with the oscillation frequency by a first integer divisor to generate a frequency-divided reference clock with a reference frequency, dividing the frequency of the readout clock by a second integer divisor to generate a frequency-divided readout clock with an input frequency, and outputting a control signal by comparing the reference frequency with the input frequency to adjust the readout clock, wherein the second integer divisor is determined by the clock control signal.