Patent ID: 8503218

Claim:
A nonvolatile memory device comprising: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the write global bit line and disposed on a first side of the memory array; and a read circuit connected to the read global bit line and disposed on a second side of the memory array opposite the first side of the memory array, wherein each of the memory banks extends in a second direction different from the first direction and comprises a plurality of nonvolatile memory cells, each of the nonvolatile memory cells having a variable resistive element whose resistance value varies according to data stored therein, wherein any one of the memory banks comprises a first memory block and a second memory block, and further comprising: a local bit line extending in the first direction to be shared by the first memory block and the second memory block; and a read local path circuit interposed between the first memory block and the second memory block and connected to the read global bit line and the local bit line.