Patent ID: 7037782

Claim:
A method of manufacturing a transistor, comprising the steps of: (a) implanting an impurity into a primary surface of a one-conductivity type semiconductor substrate to form a first region with lower impurity concentration and a second region with higher impurity concentration in an order from the primary surface in a depth direction of the substrate; (b) forming trenches in the primary surface to a depth at which the trench has a bottom reaching the second region to form a projection having a pair of side walls opposite to each other; (c) implanting a counter-conductivity type impurity in the bottom of the trench to form a source/drain region at the bottom; (d) forming a first insulation layer on the source/drain region and the side walls of the trench; (e) forming a floating gate at least partially on the side walls of the projection and the source/drain region via the first insulation layer; (f) forming a second insulation layer on a top of the projection; (g) forming a third insulation layer on the floating gate; and (h) forming a control gate on the second and third insulation layers.