Patent ID: 8008141

Claim:
A method of fabricating a semiconductor device with multiple channels comprising: sequentially forming a sacrificial layer and a first semiconductor layer on a semiconductor substrate, the sacrificial layer and the first semiconductor layer extending in a first direction and having a predetermined width in a second direction that is at an angle relative to the first direction; forming a second semiconductor layer on the semiconductor substrate and the sacrificial layer such that the second semiconductor layer covers the sacrificial layer; forming a mask layer defining an active region on the second semiconductor layer; removing portions of the second semiconductor layer, the sacrificial layer and the semiconductor substrate using the mask layer as an etch mask to form a recess region; removing the sacrificial layer; filling a space created by removing the sacrificial layer to form a partial insulation layer and filling the recess region to form a device isolation layer; removing the mask layer to a predetermine width in the second direction to form an opening exposing an upper portion of the second semiconductor layer; removing the exposed upper portion of the second semiconductor layer to provide a channel layer in the form of at least two bridges contacting the partial insulation layer, the at least two bridges being spaced apart from each other in the first direction and connecting the conductive regions with each other in the second direction; forming a gate insulation layer on the channel layer; and forming a gate electrode layer on the gate insulation layer.