Patent ID: 8472257

Claim:
A method of programming in parallel a group of memory cells of a nonvolatile memory, comprising: providing the memory cells with a threshold window partitioned into a plurality of threshold subranges by a set of increasing demarcation threshold values (V 1 , V 2 , . . . , V N ) so that each subrange represents a different memory state; applying a programming voltage as a series of incrementing voltage pulses in a programming pass to program in parallel memory cells of the group from an erased memory state to respective target memory states; providing a test reference threshold having a value offset from a designate demarcation threshold value V i among the set by a predetermined margin, so that when a memory cell is expected to have programmed past V i but has not verified relative to the test reference threshold value, the memory cell will have a threshold with an overshoot past V i within the predetermined margin, and when the memory cell is expected to have programmed past V i and has also verified relative to the test reference threshold value, the memory cell will have a threshold with an overshoot past V i more than the predetermined margin; verifying the memory cells of the group under programming relative to the test reference threshold value in between voltage pulses until the overshoot of each memory cell under programming is determined; and in a subsequent portion of the programming pass, slowing a rate of programming of any memory cell under programming that was determined to have an overshoot more than the margin.