Patent ID: 7362641

Claim:
A dynamic random access memory (“DRAM”) comprising: an array of memory cells arranged in rows and columns, each row of memory cells having a respective word line that is activated to couple the memory cells in the row to one of a respective pair of complimentary digit lines; a row decoder coupled to receive a row address and being operable to activate a word line corresponding thereto; a column decoder coupled to receive a column address and being operable to select a memory cell in a column corresponding thereto; an input/output control circuit including a sense amplifier for each column of memory cells in the array, the input/output control circuit coupling data between the memory cells in the array and a data bus; a row address counter coupled to the row decoder, the row address counter being operable to increment by a first value in a relatively higher density mode and to increment by a plural number in a relatively lower density mode, the row address counter being operable to generate row addresses corresponding to the count of the row address counter; a refresh control circuit operable in either the relatively higher density mode or a relatively lower density mode, the refresh control circuit being operable to cause data to be transferred from memory cells in each row of the array in which data are stored to another row of memory cells when switching from operation in the relatively higher density mode to operation in the relatively lower density mode, the refresh control circuit further being operable to refresh each row of memory cells selected by a row address from the row address counter in the relatively higher density mode and to simultaneously refresh multiple rows of memory cells selected by a row address from the row address counter in the relatively lower density mode; and a refresh timer operable to control the rate at which the rows of memory cells are refreshed in the relatively higher density mode and in the relatively lower density mode.