Patent ID: 7184352

Claim:
A method of refreshing an array of memory cells in a memory device of the type requiring the memory cells to be refreshed, the method comprising: alternately refreshing the memory cells in the array in either a normal operating mode or a reduced power refresh mode; refreshing a first plurality of the memory cells at a first rate in the normal operating mode; refreshing a second plurality of the memory cells at a second rate in the reduced power refresh mode, the second rate being slower than the first rate; prior to transitioning from the normal operating mode to the reduced power refresh mode: reading data from a third plurality of the memory cells; generating error checking bits for the data read from the third plurality of memory cells; and storing the error checking bits; and after transitioning from the reduced power refresh mode to the normal operating mode: reading data from a fourth plurality of the memory cells; obtaining the stored error checking bits; using the obtained error checking bits to check for errors in the data read from the memory cells; using the obtained error checking bits to correct any data read from the memory cells that have been found to be in error thereby providing corrected data; and writing the corrected data to the memory cells in the array.