Patent ID: 7468530

Claim:
An analytic structure for semiconductor failure analysis, comprising: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein first and second analytic fields of the plurality of analytic fields each has a first layer comprising a first bitline structure, and wherein the second analytic field has a second layer comprising a second bitline structure conductively coupled to the first bitline structure of the first layer of the second analytic field, and wherein the first bitline structure of the second analytic field is configured in a different pattern than the first bitline structure of the first analytic field.