Patent ID: 8367473

Claim:
A method of manufacturing chip packages, comprising: providing a superstrate including an array of substrates, each substrate including: a single patterned metal layer including an upper surface and a lower surface; and a patterned dielectric layer adjacent to the upper surface of the single patterned metal layer and including a lower surface; wherein a part of the lower surface of the single patterned metal layer forms a plurality of lower contact pads for electrical connection externally; wherein the patterned dielectric layer exposes a part of the upper surface of the single patterned metal layer to form a plurality of upper contact pads; and wherein at least a part of the lower surface of the single patterned metal layer and a part of the lower surface of the patterned dielectric layer define a lower surface of the substrate; electrically connecting a die to the plurality of upper contact pads; forming a molded structure on the patterned dielectric layer to cover the patterned dielectric layer and the die; and performing a full-cutting of the molded structure and the superstrate to form a plurality of chip packages, each of the plurality of chip packages including a package body and one of the array of substrates, such that the package body, the patterned dielectric layer, and the single patterned metal layer of each of the plurality of chip packages are laterally aligned, wherein providing the superstrate comprises: providing a carrier with a metal layer formed adjacent to the carrier; forming the patterned dielectric layer adjacent to the metal layer to form the plurality of upper contact pads; re-orienting the metal layer and the patterned dielectric layer such that the patterned dielectric layer is between the metal layer and the carrier; and patterning the metal layer to form the single patterned metal layer, and to form the plurality of lower contact pads.