Patent ID: 7725686

Claim:
A system comprising: a buffer having a plurality of entries; and retirement logic coupled to the buffer; wherein the retirement logic is configured to concurrently evaluate all of the retirement conditions associated with each of two or more of the entries and thereby determine whether the entries can be retired, wherein a minimum time greater than one processor clock cycle is required for signals associated with the retirement conditions associated with each entry to propagate through the retirement logic, and wherein the signals associated with the retirement conditions are not clocked during the minimum time during which the signals propagate through the retirement logic, wherein the retirement logic comprises a first retirement unit and a second retirement unit, wherein the first retirement unit is associated with an even-numbered unique subset of the entries and the second retirement unit is associated with an odd-numbered unique subset of the entries, wherein the retirement logic further comprises selection logic configured to alternately select the first retirement unit or the second retirement unit for evaluation of retirement conditions for of one of the entries in the associated subset, wherein the retirement logic is configured to retire the entries in the buffer at a rate of substantially one entry per clock cycle.