Patent ID: 7515481

Claim:
A memory system comprising: a controller that generates system signals; and a memory device, coupled to the controller, that operates in response to the system signals, the device comprising: an array of memory cells arranged in a plurality of memory blocks, each memory block having a plurality of memory cells that are arranged in rows and columns such that the rows are coupled to word lines and the columns are coupled to bit lines; and a control circuit that is adapted to execute an erase operation on a first memory block of the plurality of memory blocks, perform an erase verify operation to determine if any of the plurality of memory cells is unerased, the erase verify operation comprising: performing a single simultaneous read of all the memory cells in the first memory block, a result of the simultaneous read indicating that all memory cells are erased successfully or at least one memory cell of the first memory block remains unerased, perform a memory read operation, and not an erase verify operation, if at least one unerased memory cell is found in order to determine which of the plurality of memory cells is unerased wherein the memory read operation is performed in response to the erase verify operation if at least one unerased memory cell is found, and perform a selective erase operation only on the unerased memory cells such that only those word lines comprising unerased memory cells are biased to be erased, wherein the memory read operation biases only a selected word line at 0V and begins at a bottom word line of the array and progresses upward and further wherein each word line is read twice such that only alternate bit lines are enabled for each read.