Patent ID: 7783947

Claim:
An integrated circuit comprising: A. a first serial data input, a first serial data output, a clock input, and a mode select input; B. an access port that includes a first state machine connected with the clock input and the mode select input and having port control outputs indicating a CAPTURE-DR state, a SHIFT-DR state, a PAUSE-DR state, and an UPDATE-DR state; C. an instruction register connected with the first serial data input and the port control outputs and selectively coupled with the first serial data output, the instruction register having instruction control outputs; D. serializer circuitry having an input connected with the first serial data input, an instruction control input connected to the instruction control outputs, and a port control input connected to the port control outputs, the serializer circuitry including a second state machine providing serializer control outputs; E. an input switch having a functional/test data input, a serial data input connected to the first serial data input, an instruction control input connected to the instruction control outputs, and a test data output; F. an output switch having a functional/test data output, a serial data input selectively coupled to the first serial data output, and an instruction control input connected to the instruction control outputs; and G. a data register having a serial data input connected with the test data output of the input switch, a serial data output connected with the serial data input of the output switch, an instruction control input connected to the instruction control outputs, and a serializer control input connected to the serializer control outputs.