Patent ID: 8264476

Claim:
An active matrix type semiconductor device, comprising: an active matrix region including a plurality of signal lines and a plurality of scanning lines being arranged in matrix and switch devices, which are controlled through the signal lines and the scanning lines, being disposed at intersection points of the signal lines and the scanning lines, and loads being coupled to said switch devices; a coupling terminal group used for electrically coupling a scanning line driving circuit for driving the scanning lines and a signal line driving circuit for driving the signal lines with outside; and a power supply circuit for converting supply voltage inputted from a supply voltage input terminal within the coupling terminal group into a prescribed output voltage and supplying the output voltage, by boosting it with a charge pump circuit, to at least the signal line driving circuit, wherein: the power supply circuit is disposed adjacent to both the signal line driving circuit and the coupling terminal group, wherein the power supply circuit and the signal line driving circuit are disposed in a side of the substrate defined by a first side of said active matrix region, and the signal line driving circuit is disposed between the coupling terminal group and the active matrix region, the power supply circuit includes a level shift circuit for driving the charge pump circuit, an area of the level shift circuit is 1/9 to ½ of an area of the charge pump circuit, the level shift circuit includes a plurality of inverter stages beginning from a first inverter stage to an n-th inverter stage, the inverters in the n-th inverter stage drive the charge pump circuit, an area size of the inverters in the n-th inverter stage is 1/10 to ⅓ of an area size of the charge pump circuit determined by adding area sizes of switches making up the charge pump circuit, and an area size of the inverters in the first inverter stage to the (n−1)th inverter stage is 1/10 to ⅓ of the area size of the inverters in a next stage of the first inverter stage to the n-th inverter stage, respectively.