Patent ID: 7868809

Claim:
A digital to analog converter comprising: a first and second reference voltage (VREF 1 , VREF 2 ); a voltage output (DACOUT); a plurality of resistors ( 305 ) coupled in series between the first and the second reference voltages; a plurality of voltage divider nodes ( 310 ) located between each one of the resistors; a first plurality of gates ( 365 a , 340 a , 350 a ) arranged hierarchically to generate a plurality of hierarchical structures ( 325 , 345 ), are located between a first portion of the plurality of voltage divider nodes ( 310 a - 310 c ) and the voltage output; and at least one of a second plurality of gates ( 370 a ) coupling at least one of a second portion of the voltage divider nodes ( 310 d ) to the voltage output to generate a fastpath ( 375 a ), wherein at least one of the plurality of voltage divider nodes ( 510 d ) is coupled to the voltage output (DACOUT) by both the fastpath ( 575 a ) and a hierarchical path; wherein the hierarchical path comprises at least one of the plurality of hierarchical structures ( 525 a and 540 a ).