Patent ID: 7489168

Claim:
A clock synchronization apparatus comprising: a delay-correcting circuit configured to receive an initial voltage, compare a phase of an external clock with a phase of an internal clock output from a clock synchronizing unit, generate a control signal for correcting the phase of the internal clock on the basis of a difference between the phases of the external clock and the internal clock, and supply the control signal to a replica delay unit of the clock synchronizing unit, wherein the delay-correcting circuit includes: a phase-detecting unit configured to receive the external clock and the internal clock, compare the phases of the internal and external clocks, and generate a pumping-up signal or a pumping-down signal according to a result of the comparison of the internal and external clocks; a pumping control unit configured to charge or discharge the initial voltage in response to the pumping-up signal or the pumping-down signal output from the phase-detecting unit and output the pumping signal from an output terminal; and an analog-to-digital (A-D) converting unit configured to receive the pumping signal output from the pumping control unit, convert the pumping signal into the control signal, and output the control signal to the replica delay unit, wherein the pumping control unit includes: a first MOS transistor coupled between a power supply voltage terminal and a bias signal input terminal and driven by a bias signal; a second MOS transistor coupled between the power supply voltage terminal and a first node and driven by the bias signal; a third MOS transistor coupled between the power supply voltage terminal and a second node and driven by the bias signal; a fourth MOS transistor coupled between the second node and the output terminal for the pumping signal and driven by the pumping-up signal; a transmission gate coupled between an input terminal for the initial voltage and the output terminal for the pumping signal and driven by a reset signal; a fifth MOS transistor coupled between the first node and a ground terminal and driven by a signal applied to the first node; a sixth MOS transistor coupled between the output terminal for the pumping signal and a third node and driven by the pumping-down signal; a seventh MOS transistor coupled between the third node and the ground terminal and driven by a signal supplied to the first node; and a capacitor coupled between the output terminal for the pumping signal and the ground terminal and configured to charge or discharge a voltage applied to the output terminal for the pumping signal.