Patent ID: 8433859

Claim:
A buffer management apparatus, coupled between a memory and circuit blocks accessing the memory, wherein the buffer management apparatus comprising: an arbiter, operating with a low frequency, selecting the circuit blocks, passing access request signals generated by the selected circuit blocks to buffers respectively, and delivering access response signals retrieved from the corresponding buffers to the selected circuit blocks in reply to the access request signals; wherein the buffers are arranged to buffer the access request signals generated by the selected circuit blocks, and-to buffer the access response signals sent to the selected circuit blocks; and a multiplexer, operating with a high frequency which is higher than that of the arbiter, alternately retrieving the access request signals from the buffers to generate a memory access signal, sending the memory access signal to a memory controller of the memory, receiving a memory response signal generated by the memory controller in reply to the memory access signal, and distributing the memory response signal to the buffers as the access response signals.