Patent ID: 8227922

Claim:
A semiconductor device, comprising: a lower layer wiring made of a conductive material; an etching stopper film laminated on the lower layer wiring and having a laminated structure including an SiCO layer and an SiCN layer; an interlayer insulating film laminated on the etching stopper film; an intermediate film laminated on the interlayer insulating film and made of a material having an etching selectivity with respect to a material of the etching stopper film, the intermediate film having a thickness such that etching time of the intermediate film is longer than that of the etching stopper film when the intermediate film and the etching stopper film are simultaneously subjected to etching; an upper wiring layer laminated on the intermediate film and having an upper groove formed in a top surface thereof; an upper layer wiring embedded in the upper groove and made of a metal material having Cu as a main component; and a via electrically connecting the lower layer wiring and the upper layer wiring, made of the same material as the material of the upper layer wiring, and disposed in a via hole penetrating through the interlayer insulating film and the intermediate film so that the via is integral with the upper wiring layer.