Patent ID: 7143388

Claim:
A method for generating a hardware description language (HDL) specification of a circuit design from a high level programming language (HLL) specification, comprising: generating a flow graph in a computer memory arrangement, wherein the flow graph includes nodes and edges, each node represents at least one instruction in the HLL specification, and the edges represent data flow and control flow between the nodes; determining from the HLL specification instances that are allocated; generating a first memory model in a memory model for fields of the allocated instances; determining for each field in each allocated instance whether a node in the flow graph reads from or writes to the field and whether access to field is determinate, wherein a field has determinate access if all reads from and writes to the field are resolvable to an instance prior to runtime; eliminating unneeded fields from the memory model, and removing references to the unneeded fields from the flow graph; determining access control logic for the memory model; and generating an HDL specification from the flow graph, each memory model, and the access control logic.