Patent ID: 6964897

Claim:
A method of making an integrated circuit containing a DRAM array having DRAM cells with deep trench capacitors in an SOI wafer comprising the steps of: providing an SOI substrate having a uniform BOX and an SOI layer above the BOX; etching deep trenches in the DRAM array through the BOX; forming buried plates surrounding the deep trenches; forming a dielectric on the inner surfaces of the deep trench up to at least the bottom of the BOX; depositing a conductive material as the center electrode in the capacitor; recessing the center electrode of the capacitor below the top surface of the BOX, thereby forming a capacitor aperture; etching contact vias down to a contact level below the bottom of the BOX; filling the capacitor aperture and the contact vias simultaneously with conductive material, thereby forming conductive plate bias plugs in the contact vias; implanting a buried plate contact layer in the substrate in the array, extending vertically to overlap the buried plates; making contact with the plate bias plugs and with the buried plate contact layer, thereby establishing a conductive path between the buried plates and the plate bias contacts; forming FETs with floating bodies in the SOI layer, connecting a cell contact with the center electrode; and completing the circuit.