Patent ID: 7995144

Claim:
A method of determining a sample phase location within periods of an input signal, comprising the steps of: sampling the input signal at a current sample clock phase within a period of the input signal to obtain a current sample value; sampling the input signal at a first sample clock phase prior in time to the current sample clock phase within the period of the input signal to obtain a first sample value; sampling the input signal at a second sample clock phase later in time to the current sample clock phase within the period of the input signal to obtain a second sample value; determining first and second difference voltages corresponding to the difference between the first sample value and the current sample value, and to the difference between the second sample value and the current sample value, respectively; counting a first number corresponding to the number of times the first difference voltage exceeds a threshold voltage over a selected number of repetitions of the sampling and determining steps; counting a second number corresponding to the number of times the second difference voltage exceeds the threshold voltage over the selected number of repetitions of the sampling and determining steps; and adjusting the position of the current sample clock phase within the period of the input signal responsive to the first and second numbers.