Patent ID: 6861748

Claim:
A test structure for an integrated circuit, the test structure comprising: a first underlying electrically conductive layer, a first electrically nonconductive layer disposed over the first underlying electrically conductive layer, a first overlying electrically conductive layer disposed over the first electrically nonconductive layer and the first underlying electrically conductive layer, first electrically conductive vias forming electrical connections through the first electrically nonconductive layer between the first underlying electrically conductive layer and the first overlying electrically conductive layer, a second overlying electrically conductive layer disposed over the first electrically nonconductive layer and the first underlying electrically conductive layer, the second overlying electrically conductive layer not making electrical connections through the first electrically nonconductive layer to the first underlying electrically conductive layer, a second underlying electrically conductive layer, a second electrically nonconductive layer disposed over the second underlying electrically conductive layer, a third overlying electrically conductive layer disposed over the second electrically nonconductive layer and the second underlying electrically conductive layer, the third overlying electrically conductive layer not making electrical connections through the second electrically nonconductive layer to the second underlying electrically conductive layer, a fourth overlying electrically conductive layer disposed over the second electrically nonconductive layer and the second underlying electrically conductive layer, second electrically conductive vias forming electrical connections through the second electrically nonconductive layer between the second underlying electrically conductive layer and the fourth overlying electrically conductive layer, first electrically conductive traces forming electrical connections between the first overlying electrically conductive layer and the third overlying electrically conductive layer, and second electrically conductive traces forming electrical connections between the second overlying electrically conductive layer and the fourth overlying electrically conductive layer.