Patent ID: 8136060

Claim:
A computer implemented method for extracting connectivity for a hierarchical configuration of shapes representing an integrated circuit design, comprising: using at least one processor that is configured or programmed for performing a process, the process comprising: identifying a hierarchical level in the hierarchical configuration of shapes, wherein the hierarchical configuration comprises the hierarchical level and one or more other hierarchical levels; and extracting nets for the hierarchical level without fully flattening the integrated circuit design to unfold all instantiations of one or more shapes, which are placed in the integrated circuit design by a placement tool, to extract the nets, wherein the hierarchical level includes one or more instantiations of but not one or more actual copies of a shape from at least one of the one or more other hierarchical levels in the hierarchical configuration of shapes, and the integrated circuit design maintains a hierarchical characteristic of at least some shapes in the hierarchical configuration during the action of extracting the nets.