Patent ID: 7489174

Claim:
A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, comprising: a first control stage configured to output, within a period within which the clock has a second level, a signal having a level inverted from that of the digital data signal; a second control stage configured to output, within the period within which the clock has the second level, a signal of a first level, and to output, within another period within which the clock has the first level, a signal of a level based on the signal outputted from said first control stage; a third control stage configured to output, within a period within which the signal outputted from said second control stage has the second level, an output signal of the first level which makes the output signal of said dynamic flip-flop circuit; and a phase adjustment circuit configured to adjust the phase of the clock to produce a second clock and supply the second clock to said third control stage.