Patent ID: 7440457

Claim:
A network apparatus comprising: a network interface for transmitting and receiving packets to and from a network; a network processor for transferring the received packets to a next transfer destination; a table memory for storing a table referred for the transfer of packets; and a network-processor accelerator for transferring the received packets; wherein the network-processor accelerator transfers the received packets having the destination addresses which are identical to that of the received packets already processed with the network processor, and wherein the network-processor accelerator, comprises: an interface unit for temporarily storing the received packet; a packet analysis unit for obtaining the extracted information by extracting the necessary domain from the received packets; a cache memory for storing the process result required for transfer process of the received packets; an address generation means for referring to the cache memory from the extracted information; a means for determining whether the relevant information exists or not in the cache memory as the result of reference to the cache memory from the extracted information; a means for reassembling the packets from the relevant information when the relevant information exists in the cache memory; a primary table for management of the packets as cache miss packets when the relevant information does not exist in the cache memory; a secondary table for management of the second and subsequent packets that are containing the relevant information not existing in the cache memory and are expected to provide the process result which is identical to that of the packets recorded in the primary table; an interface unit for transmitting the packets and necessary information to the network processor for implementing, with a programmable manner, the processes of cache miss packet recorded to the primary table; an interface unit for receiving the processed packets and added information from the network processor; a means for recording the process result information of the processed packets to the cache memory; a means for applying the process result to the relevant packets recorded to the secondary table; a means for releasing the entries of the primary and secondary tables having completed the processes; a means for generating the transmitting packets from the processed packets or the process result information; and an interface unit for transmitting the processed packets.