Patent ID: 7655872

Claim:
A substrate of ball grid array package, comprising: a first signal layer formed successively thereon a first insulating layer, a power layer, a second insulating layer, a ground layer, a third insulating layer, and a second signal layer, wherein said substrate has a chip-interposed region having an array of vias and an array of ball pads formed on said first signal layer and said second signal layer, and said array of vias are arranged mutually shifted with said array of ball pads by ½u, and ½v, said u and v being a distance between two adjacent columns and a distance between two adjacent rows of said vias, respectively, in said chip-interposed region except an outmost ring and a sub-outmost ring; and wherein said distance between two adjacent columns and said distance between two adjacent rows of vias at the outmost ring is double at least at a right hand side or a left hand side of said vias; and said distance between two adjacent columns and said distance between two adjacent rows of vias at the sub-outmost ring is double at least at a right hand side or a left hand side of said vias so as to provide more heat dissipation areas at the outmost ring and the sub-outmost ring than an inner portion of said chip-interposed region; and wherein said vias at the outmost ring and the sub-outmost ring within said chip-interposed region are filled with conductive material but provided as clearances of through holes at said power layer so that said clearances of through holes are electrically disconnected with both of said power layer and said first and said second signal layers.