Patent ID: 6964924

Claim:
A method of monitoring polishing process parameter for an integrated circuit structure on a substrate, the method comprising: constructing a first metrology site on the substrate, the first metrology site representing a design extreme of a high density integrated circuit structure, the first metrology site formed by placing a relatively small horizontal surface area trench within a relatively large surface area first field of a polish stop material, constructing a second metrology site on the substrate, the second metrology site representing a design extreme of a low density integrated circuit structure, the second metrology site formed by placing a relatively large horizontal surface area trench within a relatively small surface area second field of the polish stop material, where the first field is a separate field from the second field, covering the substrate with a layer of an insulating material, thereby at least filling the trenches, calculating a target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the fields of polish stop material, polishing the substrate until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness, measuring a second thickness of the insulating material in the trench of the second metrology site, and monitoring values based on the first thickness and the second thickness as the polishing process parameters for the integrated circuit structure.