Patent ID: 8652892

Claim:
A method for forming a device comprising: providing a substrate having a device region; forming a p-type transistor on the device region of the substrate, wherein the transistor comprises a gate, source and drain (S/D) regions adjacent to the gate, wherein a bottom of the S/D regions is disposed below a bottom of source-drain extension (SDE) regions, and a channel region under the gate between the S/D regions; forming at least one recess in the substrate; and forming a stressor region in at least a portion of the recess in the substrate to apply a stress on the channel region, the stressor region comprises a carbon doped silicon germanium (SiGe) stressor layer having EOR defects resulting from ion implantation to form the S/D regions, wherein a bottom of the stressor layer is disposed at least below the EOR defects, and wherein the carbon doped SiGe stressor layer comprises an amount of carbon to reduce the amount of EOR defects in order to reduce relaxation of the stress in the stressor layer from subsequent annealing of the substrate.