Patent ID: 8614487

Claim:
A semiconductor device with at least two gate regions, the device comprising: a substrate region including a surface, the substrate being characterized by a first conductivity type; a source region in the substrate region; a drain region in the substrate region, the drain region and the source region being separate from each other, the drain region and the source region being characterized by a second conductivity type opposite the first conductivity type; three channel regions disposed in parallel between the source region and the drain region and forming a contiguous region having a same doping concentration, wherein a first channel region and a second channel region are disposed on either side of a third channel region, each of the three channel regions having a first end region contacting the source region and a second end region contacting the drain region, wherein the first channel region, the second channel region, and the third channel region are characterized by a same width; a gate dielectric region on the substrate region, the gate dielectric region overlying the three channel regions; a first gate region overlying a first portion of the gate dielectric region that overlies the first channel region; a second gate region overlying a second portion of the gate dielectric region that overlies the second channel region; an insulation region overlying a third portion of the gate dielectric region that overlies the third channel region, the insulation region being disposed between the first gate region and the second gate region, the insulation region extending from the source region to the drain region, the insulation region having a first side surface perpendicular to the surface of the substrate region and in direct contact with the first gate region and a second side surface perpendicular to the surface of the substrate region and in direct contact with the second gate region; a first control voltage signal coupled to the first gate region; a second control voltage signal coupled to the second gate region, the second control voltage signal being different from the first control voltage signal; and a threshold voltage modulated by the first and second control voltage signals; whereby the first gate region and the second gate region are configured to be controlled independently to determine a current between the source region and the drain region.