Patent ID: 7720664

Claim:
A method of generating a simulation model comprising: generating a net list containing circuit information of an electronic circuit using a functional block that includes first and second logic circuits; deleting said circuit information based on said net list; and generating a gate simulation model containing no circuit information of the functional block according to the deleting for carrying out a timing simulation, including logic information and delay information between input/output of said functional block, wherein said gate simulation model expresses said delay information of said functional block of said net list using an input buffer or an output buffer of said functional block; said first and second logic circuits are first and second flipflops respectively including a clock terminal, an input terminal and an output terminal; in said net list, a first clock signal is input to said clock terminal of said first flipflop, and a second clock signal is input to said clock terminal of said second flipflop, said first and second clock signal branched from a same clock signal; and in said gate simulation model, a third clock signal is input to said clock terminals of said first and second flipflops, said delay information between said first and third clock signals is distributed to an input buffer or an output buffer respectively connected to said input terminal or said output terminal of said first flipflop, and said delay information between said second and third clock signals is distributed to an input buffer or an output buffer respectively connected to said input terminal or said output terminal or said second flipflop.