Patent ID: 7177966

Claim:
A microcomputer comprising: an edge detecting circuit detecting a change in input level of an externally applied synchronous signal, and providing an edge detection signal notifying of the change in input level; a data latch unit receiving said edge detection signal, and providing a data latch signal by latching externally applied external data; an address generating circuit generating an address signal; a local bus receiving said data latch signal and said address signal; a write control unit receiving said edge detection signal, and activating a write control enable signal; a central processing unit providing a read enable signal and a write enable signal; a data bus receiving data for input/output to or from said central processing unit; a storage device storing said external data; a memory bus receiving data for input/output to or from said storage device; and an arbitration circuit connected to said local bus, said data bus and said memory bus, monitoring said write control enable signal, said read enable signal and said write enable signal, and detecting a cycle executed without accessing to said memory by said central processing unit.