Patent ID: 7879703

Claim:
A method of fabricating a semiconductor device, comprising: preparing a substrate including a cell array region and a peripheral circuit region, the cell array region and the peripheral circuit region having a cell active region and peripheral active regions; forming a cell gate pattern on the cell active region and peripheral gate patterns on the peripheral active regions; forming first cell impurity regions in the cell active region, the first cell impurity regions being formed adjacent to the cell gate pattern; forming a first insulating layer on the cell array region and a sacrificial insulating layer on the peripheral circuit region to surround the cell gate pattern and the peripheral gate patterns respectively; forming cell conductive pads in the first insulating layer of the cell array region to electrically connect the first cell impurity regions; wholly removing the sacrificial insulating layer adjacent to the peripheral gate patterns from the substrate; sequentially forming first and second peripheral impurity regions in the peripheral active regions to be apart from the peripheral gate patterns; and forming a second insulating layer in the peripheral circuit region to surround the peripheral gate patterns, wherein the method comprises performing a first temperature process step at a first temperature more than about 700° C. on the first insulating layer and the sacrificial insulating layer before the removing of the sacrificial insulating layer, and performing a second temperature process step at a second temperature less than the first temperature on the second insulating layer after the wholly removing of the sacrificial insulating layer; and wherein the first and second peripheral impurity regions are diffused toward the peripheral gate patterns through the second temperature process to align with the peripheral gate patterns.