Patent ID: 8766371

Claim:
A semiconductor structure, comprising: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions respectively formed on both sides of the channel region and embedded in the semiconductor substrate, wherein the gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer, without a spacer formed on sidewalls of the gate stack; and wherein for an nMOSFET, the conductive layer has a compressive stress and is configured to release the compressive stress due to lack of the spacer so as to apply a more tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress and is configured to release the compressive stress due to lack of the spacer so as to apply a more compressive stress to the channel region.