Patent ID: 8558607

Claim:
A charge-domain filter, comprising: a switched-capacitor network, having an input terminal receiving an input signal, and the switched-capacitor network sampling the input signal according to a plurality of clock signals, wherein the clock signals have different phases; and a clock generator, coupled to the switched-capacitor network for providing the clock signals, wherein the clock generator adjusts phase differences of the clock signals according to a first control signal or adjusts pulse widths of the clock signals according to a second control signal, and the clock generator comprises: N unit pulse cells UPC_ 1 -UPC_N, connected in series, wherein an i th unit pulse cell UPC_i samples an (i−1) th delay clock output by an (i−1) th unit pulse cell UPC_(i−1) according to a first frequency, so as to obtain an i th pulse signal, the i th unit pulse cell UPC_i delays the i th pulse signal according to the first control signal to obtain an i th delay clock, and the i th unit pulse cell UPC_i outputs the i th delay clock to an (i+1) th unit pulse cell UPC_(i+1); and N programmable width cells PWC_ 1 -PWC_N, wherein an i th programmable width cell PWC_i is coupled to the i th unit pulse cell UPC_i for receiving the i th pulse signal, the i th programmable width cell PWC_i adjusts a pulse width of the i th pulse signal according to the second control signal, so as to obtain an i th clock signal clk i of the clock signals, and the i th programmable width cell PWC_i outputs the i th clock signal clk i to the switched-capacitor network.