Patent ID: 7698677

Claim:
An article of manufacture comprising machine-readable medium including program logic embedded therein that when executed by a machine cause a method of reducing the dynamic noise of a power network of a semiconductor circuit ( 100 ), comprising the steps of: a) dividing a semiconductor circuit ( 100 ) design into a plurality of tiles ( 105 ); b) determining a violation group of said plurality of tiles ( 105 ) forming a violation region ( 120 ), whereby said violation region ( 120 ) includes circuitry having a violation voltage level ( 225 ) which is less than a specified threshold voltage level ( 220 ); c) determining wire constraints for wires ( 420 ) to be added between said tiles ( 105 ) of said semiconductor circuit ( 100 ); d) determining decap constraints for a value of decap to be added to circuitry within said determined violation region ( 120 ) of tiles ( 105 ); e) determining an optimal decap/wire value which determines a value of decap and a value of wire enhancement, where said decap and wire enhancement values are used to add power/ground wires ( 420 ) and decap within at least a portion of said semiconductor circuit ( 100 ) within said determined violation region ( 120 ) of said plurality of tiles ( 105 ) to reduce said dynamic noise; and f) modifying the semiconductor circuit design based on said decap and wire enhancement values to add power/ground wires and decap within at least a portion of said semiconductor circuit within said determined violation region of said plurality of tiles to reduce said dynamic noise.