Patent ID: 7296252

Claim:
A method of designing a layout of an integrated circuit using a computer system, comprising: calculating by said computer system respective clustering scores for different pairs of objects in the layout wherein the clustering score d(u, v) for a pair of objects u and v is defined as d ( u, v )=Σ e ( w e )/[ a ( u )+ a ( v )] k , where k≧1, a(u) and a(v) are the areas of u and v respectively, and w e is the connection weight for a given hyperedge e of the pair of objects; grouping by said computer system at least one of the pairs of objects into a cluster based on the clustering scores; and partitioning by said computer system the objects as clustered and ungrouping the cluster after partitioning; and storing data representing the ungrouped, partitioned objects in said computer system.