Patent ID: 7195935

Claim:
A method for manufacturing a semiconductor device, comprising: (a) mounting a plurality of first semiconductor chips in a manner not to overlap with one another on a substrate having a plurality of wiring patterns formed thereon, and electrically connecting each of the first semiconductor chips to any one of the wiring patterns; (b) conducting an electrical examination on a plurality of mounted bodies each including one of the first semiconductor chips and any one of the wiring patterns electrically connected to each other; (c) stacking a second semiconductor chip on the first semiconductor chip of any one of the mounted bodies that pass the electrical examination, excluding any of the mounted bodies that fail the electrical examination; and thereafter (d) cutting the substrate so as to divide the wiring patterns, wherein the electrical examination in step (b) includes a test on each of the wiring patterns, a test on each of the first semiconductor chips, and a test on an electrical connection state between each of the first semiconductor chips and a corresponding one of the wiring patterns, and wherein the electrical examination is a success when passing all of the tests, and the electrical examination is a failure when failing at least one of the tests.