Patent ID: 8264018

Claim:
A semiconductor memory device comprising: a gate of a first wordline transistor disposed in a first region of a semiconductor substrate; a gate of a bitline transistor disposed in a second region of the semiconductor substrate; at least one first wordline channel pillar penetrating the gate of the first wordline transistor and insulated from the gate of the first wordline transistor; at least one bitline channel pillar penetrating the gate of the bitline transistor and insulated from the gate of the bitline transistor; a local bitline extending in a first direction substantially vertical to an upper surface of the semiconductor substrate and electrically connected to the bitline channel pillar; a first local wordline disposed at one side of the local bitline, extending in a second direction substantially perpendicular to the first direction so as to intersect the local bitline, and electrically connected to the first wordline channel pillar; and a first memory cell formed at an intersection between the local bitline and the first local wordline.