Patent ID: 8117420

Claim:
A buffer management structure comprising: a storage module, wherein the storage module comprises: a first write entry storing a first transaction request and a first bit, the first bit indicating a valid state for the first transaction request; a second write entry storing a second transaction request and a second bit, the second bit indicating whether the second transaction request is associated with a valid state, wherein the second write entry is located adjacent to the first write entry; and a third write entry storing a third transaction request and a third bit, the third bit indicating whether the third transaction request is associated with a valid state, wherein the third write entry is located adjacent to the second write entry; and a priority encoder configured to identify a closest transaction request associated with a valid state to a multiplexer based on the second bit and the third bit; wherein, in response to the second bit indicating an invalid state and the third bit indicating a valid state, the multiplexer is configured to move the third transaction request and the third bit to the first write entry after the first transaction request is output, and wherein the multiplexer is further configured to retain the second transaction request and the second bit in the second write entry.