Patent ID: 7902552

Claim:
A semiconductor device comprising: a semiconductor substrate having an active region comprising a gate area, a bit line contact area and a storage node contact area, a recess being formed in the gate area and the bit line contact area; a gate formed over the gate area, wherein the gate comprises the recess and a portion of an isolation layer, the gate having a main gate in the gate area and a passing gate over the isolation layer, wherein the main gate comprises a laminate structure of a gate insulation layer formed over a surface of the recess, a first gate conductive layer formed over the gate insulation layer to fill the recess, and a second gate conductive layer and a hard mask layer sequentially formed over the first gate conductive layer, and wherein the passing gate comprises a laminate structure of a buffer insulation layer, a first gate conductive layer, a second gate conductive layer and a hard mask layer sequentially formed over a surface of the isolation layer; a first junction area formed in the storage node contact area of the semiconductor substrate; a second junction area formed in the bit line contact area of the semiconductor substrate, wherein the second junction area formed in the bit line contact area has a lower doping concentration relative to the first junction area formed in the storage node contact area, the lower doping concentration of the second junction area preventing leakage current in the bit line contact area; and a first landing plug and a second landing plug formed over the first junction area and the second junction area, respectively.