Patent ID: 8050121

Claim:
A semiconductor memory comprising: a plurality of memory blocks being accessed independently during a normal operation mode, being accessed simultaneously during a test mode in order for common data to be written to the plurality of memory blocks, and including real memory cells and redundancy memory cells; a block control unit selecting one of the memory blocks according to a block address signal specifying one of the memory blocks during the normal operation mode, and selecting the plurality of memory blocks irrespective of the block address signal during the test mode; and a redundancy access unit accessing the redundancy memory cells of one of the memory blocks corresponding to the block address signal when an external address signal matches a defect address during the normal operation mode, and simultaneously accessing the redundancy memory cells of the plurality of memory blocks when a forced redundancy signal indicates a first level during the test mode, the forced redundancy signal being supplied to one of a block address terminal receiving the block address signal and a part of external address terminals receiving the external address signal.