Patent ID: 7546568

Claim:
A method for designing an integrated circuit, comprising the steps of: (A) splitting a design layout of said integrated circuit into a plurality of tiles, wherein (i) said tiles each have a respective boundary, (ii) said design layout comprises a plurality of logic gates and (iii) said logic gates of a given set each have a respective logic input to be fixed at a first logical level; (B) generating a list of said tiles; (C) deleting from said list each of said tiles that does not contain at least one of said logical gates having at least one tied-to input; (D) adding a plurality of tie-to cells to said design layout, wherein (i) said tie-to cells of a first set each generate a respective first tie-to signal at said first logical level, (ii) said first tie-to signals are intentionally current limited by said tie-to cells to prevent gate damage and (iii) said logic inputs of said given set of said logic gates outnumber said tie-to cells of said first set; and (E) routing said first tie-to signals from said tie-to cells of said first set to said logic inputs of said given set without crossing said boundaries.