Patent ID: 8136056

Claim:
A computer-implemented method for analyzing suitability of an Integrated Circuit (IC) layout for manufacture, comprising: using a computer system which comprises at least one processor and is configured for: receiving an IC layout; performing design rules checking (DRC) using design rules on the IC layout to generate a DRC result; consulting a pattern library, wherein the pattern library comprises at least a pattern that corresponds to one or more patterns in the IC layout and statistics associated with a probability that the pattern will function as designed after manufacturing; analyzing the IC layout based at least in part upon the DRC result and the pattern to determine one or more exceptions to the design rule, wherein the act of analyzing the IC layout comprises determining an impact on a component in the IC layout caused by at least one non-neighboring circuit component of the component, which is not neighboring the component; making a determination, based at least in part upon the act of analyzing the IC layout and the pattern, of the suitability of the IC layout for manufacture, wherein the act of making the determination comprises: performing statistical analysis using at least in part the one or more exceptions and the statistics to determine whether the manufactured IC layout is suitable; and storing the determination of the suitability of the IC layout for manufacture in a volatile or non-volatile computer usable storage medium or displaying the determination on a display device.