Patent ID: 8742969

Claim:
A first analog to digital converter comprising: a first reference ladder including a plurality of first resistors and a plurality of first taps, wherein the plurality of first resistors are configured to receive a supply voltage, and wherein the plurality of first taps are configured to, based on the supply voltage, provide a plurality of first voltage references to a second analog to digital converter; a second reference ladder including a plurality of second resistors and a plurality of second taps, wherein the plurality of second taps provide a plurality of second voltage references, and wherein one of the plurality of second voltage references is selected to be provided to a third analog to digital converter; and a third reference ladder including a plurality of third resistors and a plurality of third taps, wherein the plurality of third resistors are configured to receive the supply voltage, wherein the plurality of third taps are configured to, based on the supply voltage, provide a plurality of third voltage references, wherein the second reference ladder is configured to (i) receive a selected one of the plurality of third voltage references, and (ii) based on the selected one of the plurality of third voltage references, provide the selected one of the plurality of second voltage references.