Patent ID: 8836021

Claim:
A semiconductor device, comprising: an active region including a drain region, a channel region stacked on the drain region, and a source region stacked on the channel region, the active region being formed of a silicon semiconductor layer; a gate conductor embedded within a trench, the trench formed from the source region to the drain region penetrating through the channel region; a source electrode configured to come in contact with the source region, the source electrode including an adhesion layer formed of a metal layer having a film thickness of 150 Å or smaller, an interface between the source electrode and the source region being silicidized; a plurality of the trenches formed at intervals; and an insulating layer buried in a region on the gate conductor within the trench, wherein the active region between adjacent trenches has a width of 0.18 μm to 0.30 μm and wherein the active region has a protrusion protruded in a depth direction of the trench by a protrusion amount of 25 nm to 125 nm higher than a surface of the insulating layer.