Patent ID: 8736371

Claim:
A semiconductor device comprising: a first input terminal to which an input potential is input; a second input terminal to which a reference potential is input; a first output terminal from which an output potential is output; a differential amplifier electrically connected to the first input terminal and the second input terminal; and a gain stage comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, and electrically connected to the first output terminal; wherein the differential amplifier is electrically connected to a first power supply potential line and a second power supply potential line, wherein a potential of the first power supply potential line is higher than that of the second power supply potential line, wherein a first terminal of the first transistor is electrically connected to a second output terminal of the differential amplifier, wherein a second terminal of the first transistor is electrically connected to a gate of the third transistor, wherein a first terminal of the second transistor is electrically connected to the second input terminal, wherein a second terminal of the second transistor is electrically connected to a gate of the fourth transistor, wherein a first terminal of the third transistor is electrically connected to the first power supply potential line, wherein a second terminal of the third transistor and a first terminal of the fourth transistor are electrically connected to the first output terminal, wherein a second terminal of the fourth transistor is electrically connected to the second power supply potential line, and wherein the first transistor and the second transistor are each a transistor whose leakage current in an off state per micrometer of a channel width is lower than or equal to 1×10 −17 A.