Patent ID: 7465999

Claim:
A semiconductor device comprising: a SOI substrate having a uniform thickness and comprising a first silicon layer formed over an insulating layer, the insulating layer formed over a second silicon layer; a high dielectric constant gate oxide layer over said first silicon layer; a fully-depleted SOI NMOS transistor as part of a memory array, said fully-depleted SOI NMOS transistor comprising first source and drain regions provided in said first silicon layer, said first source and drain regions being of n-type conductivity, said first source and drain regions disposed below said gate oxide layer, and a first gate structure over said high dielectric constant gate oxide layer and between said first source and drain regions, said first gate structure being of a p-type conductivity and comprising a doped silicon/germanium layer; and a partially-depleted SOI NMOS transistor as part of a periphery array, said partially-depleted SOI NMOS transistor comprising second source and drain regions provided in said first silicon layer, said second source and drain regions being of n-type conductivity, said second source and drain regions disposed below said gate oxide layer, and a second gate structure over said high dielectric constant gate oxide layer and between said second source and drain regions, said second gate structure being of a n-type conductivity, wherein said high dielectric constant gate oxide layer extends past an edge of said first gate structure.