Patent ID: 8551831

Claim:
A method for forming an integrated circuit semiconductor device comprising: providing a semiconductor substrate; forming a dielectric layer overlying the semiconductor substrate; forming a gate layer overlying the dielectric layer; patterning the gate layer to form a gate structure including edges; forming a second dielectric layer overlying the gate structure to protect the gate structure including the edges; patterning the second dielectric layer to form sidewall spacer structures on the edges of the gate structure; etching a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer; etching a portion of the gate structure to form a recessed region within the sidewall spacer structures; depositing a silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region and into the recessed region in the gate structure; and causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region; wherein etching a source region and a drain region and etching a portion of the gate structure are performed simultaneously, wherein the silicon germanium material filled in the recessed region forms an integrated gate structure, the integrated gate structure has a lower sheet resistance than a polysilicon layer, and wherein the gate structure has a remaining thickness of 100 Angstroms and greater after forming the recessed region.