Patent ID: 8183905

Claim:
A system to provide a low-power clock signal or a low-noise clock signal, comprising: a low-dropout voltage regulator (LDO); a low-power bandgap voltage reference generator coupled to the LDO and configured to provide a low-power voltage reference to the LDO; a low-noise bandgap voltage reference generator coupled to the LDO and configured to provide a low-noise voltage reference to the LDO; a switch configured to switch a voltage reference input of the LDO to the low-noise bandgap voltage reference or to the low-power bandgap voltage reference; and a crystal oscillator coupled to the LDO and configured to provide a low-power clock signal or a low-noise clock signal based on whether a low-noise voltage reference or a low-power voltage reference is selected as a voltage reference input to the LDO.