Patent ID: 7193882

Claim:
A semiconductor memory device having a 2T2C type memory cell structure, comprising: word line drive means capable of collectively driving word lines of all of memory cells; plate line drive means capable of collectively driving plate lines of all of said memory cells; switch means for switching a plate line potential; and control means for controlling said word line drive means, said plate line drive means and said switch means, wherein at a time of conducting a probing test of said semiconductor memory device, said plate line potential is changed to a supply voltage by said switch means, all of said word lines are driven based on a control signal from said control means and all of said plate lines are driven with said supply voltage to make all of said memory cells accessible after which data “1” is written in all of said memory cells under control of said control means, then said plate line potential is changed to a predetermined potential by said switch means and all of said memory cells are driven with said predetermined potential for a predetermined time with a potential of a bit line pair being 0 V, thereby collectively setting all of said memory cells in a non-polarization state.