Patent ID: 6879184

Claim:
A programmable logic device (PLD) having one or more enhanced generic logic blocks (EGLBs), each EGLB comprising: (a) a LUT-based Boolean term (LBT) array connected to receive a plurality of array input signals and generate one or more array output signals, each array output signal corresponding to a combinatorial function of one or more of the array input signals; and (b) one or more sum terms, each sum term connected to receive one or more of the array output signals and generate a combinatorial sum of its input signals, wherein: the LBT array comprises a plurality of selection elements and a plurality of LBTs; each selection element is adapted to selectively provide one or more of the array input signals to an LBT; each LBT comprises P product terms and a P-input look-up table (P-LUT); P is an integer greater than one; each product term is adapted to generate a combinatorial product of one or more array input signals selectively provided by a corresponding selection element; and each P-LUT is connected to receive the combinatorial products from the corresponding P product terms and generate a programmable combinatorial function of the P product terms.