Patent ID: 8390061

Claim:
A semiconductor device, comprising: a which is which is formed of a high resistance first conductivity type semiconductor at a predetermined depth from a surface of a semiconductor substrate; a plurality of trenches extending from a surface to a midway depth of the well region; a gate insulating film formed on surfaces of a concave portion and a convex portion formed by each of the trenches; a first gate electrode embedded inside the trenches; a second gate electrode formed on the surface of the semiconductor substrate in contact with the first gate electrode in regions of the concave portion and the convex portion, the regions excluding vicinities of both ends of the trenches; a third gate electrode embedded inside the trenches in the vicinities of the both ends of the trenches in contact with the first gate electrode and the second gate electrode so that a surface of the third gate electrode is located at a position deeper than the surface of the semiconductor substrate; and a source region and a drain region formed as low resistance second conductivity type semiconductor layers from a part of a surface of the high resistance first conductivity type semiconductor that is out of contact with the third electrode so that the source and drain regions are formed electrode, so as to be deeper in a side surface of the concave portion of each of the trenches than in the surface of the convex portion of each of the trenches and shallower than the depth of the well region.