Patent ID: 8914586

Claim:
An apparatus comprising: a processor coupleable to a shared memory that is shared by one or more other processors, wherein the processor is configured to execute transactional memory access operation to the shared memory; and the processor comprising executable code for resolving conflicts between a first thread and a second thread, the executable code comprising instructions for: setting a lock indication during execution of a transaction, the transaction acquiring access to a large region of the shared memory, the lock indication indicating to the first thread and the second thread that the first thread has protected the large region of the shared memory; determining whether the lock indication is set during execution of the transaction; on a condition that the second thread detects the set lock indication when executing another transaction, performing, by the second thread, one operation of a plurality of operations comprising aborting execution of the transaction executing on the first thread by creating a conflict between the first thread and the second thread or aborting execution of the another transaction of the second thread; and, resetting the lock indication after execution of the transaction is committed.