Patent ID: 8228737

Claim:
A nonvolatile semiconductor memory comprising: a first memory cell transistor including a first control gate electrode and first source/drain impurity diffusion layers, the first control gate electrode being formed on a main surface of a first semiconductor layer of a first conductivity type with a first electric charge accumulating portion being interposed in between, the first source/drain impurity diffusion layers being of a second conductivity type and being formed to sandwich the first control gate electrode in between; and a second memory cell transistor including a second control gate electrode and second source/drain impurity diffusion layers, the second control gate electrode being formed on a main surface of a second semiconductor layer of the first conductivity type, the second source/drain impurity diffusion layers being of the second conductivity type and being formed to sandwich the second control gate electrode in between, the second semiconductor layer being formed on the first semiconductor layer with an insulating film being interposed in between in an area other than that in which the first memory cell transistor is formed, the insulating film being thicker than the first electric charge accumulating portion.