Patent ID: 8278169

Claim:
A manufacturing method of a semiconductor device by forming a first nonvolatile memory cell in a first region of a semiconductor substrate and a second nonvolatile memory cell in a second region of the semiconductor substrate, comprising the steps of: (a) depositing an insulating film over the whole surface of the semiconductor substrate including the first region and the second region to form a first gate insulating film in the first region and a third gate insulating film in the second region; (b) depositing a first conductor film over the first gate insulating film and the third gate insulating film; (c) patterning the first conductor film to form a first control gate electrode of the first nonvolatile memory cell in the first region and a second control gate electrode of the second nonvolatile memory cell in the second region; (d) introducing an impurity into the semiconductor substrate in alignment with the first control electrode and into the semiconductor substrate in alignment with the second control electrode; (e) forming a film stack of insulating films over the whole surface of the semiconductor substrate covering the first control gate electrode formed in the first region and the second control gate electrode formed in the second region; (f) depositing a second conductor film over the film stack; (g) anisotropically etching the second conductor film to form a sidewall comprised of the second conductor film over the side surfaces on both sides of the first control gate electrode in the first region and over the side surfaces on both sides of the second control gate electrode in the second region; (h) removing the sidewall formed over the side surface on one side of the first control gate electrode in the first region; and (i) removing the film stack exposed from the semiconductor substrate, wherein a first memory gate electrode is formed by the sidewall remaining over the side surface on one side of the first control gate electrode, thereby forming the first nonvolatile memory cell which is a binary memory cell in the first region, and wherein a second memory gate electrode and a third memory gate electrode are formed by the sidewall remaining over the side surfaces on both sides of the second control gate electrode, thereby forming the second nonvolatile memory cell which is a multivalued memory cell in the second region.