Patent ID: 8836401

Claim:
A data retention device comprising: a logic circuit configured to generate at least one retention enable signal before a chip enters a reduced power mode; a retention control cell circuit configured to latch the generated retention enable signal, and to output a retention enable control signal based on a first power signal of the logic circuit and a detection result of a second power signal for input/output (I/O); and an I/O cell circuit configured to latch data based on the retention enable control signal, wherein the retention control cell circuit comprises, a latch configured to, latch the generated retention enable signal, and output the retention enable control signal of a first level based on a level of the second power signal when a retention control operation is performed; a detector configured to generate a first detection signal for the first power signal of the logic circuit and a second detection signal for the second power signal for I/O; a controller configured to control the latch based on the first detection signal and the second detection signal; and an initializer configured to set the retention enable control signal to disable the retention control operation of the I/O cell circuit during a power-on mode of the chip based on the second detection signal.