Patent ID: 7598785

Claim:
A slew-rate adjusting apparatus for use in a semiconductor memory device, comprising: a slew-rate modulation signal generator for generating a slew-rate modulation signal by using a switching unit having a plurality of first switching elements turned on according to a plurality of control codes, which exclusively have a first logic level, wherein the control codes are programmable at an external; and a pre-driver for adjusting a slew rate of a data signal according to a number of second switching elements turned on in response to the slew-rate modulation signal, wherein the slew-rate modulation signal generator further includes a logic level changing unit for changing logic levels of the control codes and outputting a control signal and the logic level changing unit includes a first inverter for inverting a first control code, a second inverter for inverting a second control code, and a third inverter for inverting a third control code, wherein the switching unit generates the slew-rate modulation signal used to select the second switching elements by using the first switching elements turned on in response to the control signal and includes: a first PMOS transistor of the first switching elements configured to be turned on in response to an output of the first inverter; a second PMOS transistor of the first switching elements configured to be turned on in response to an output of the second inverter; a third PMOS transistor of the first switching elements configured to be turned on in response to an output of the third inverter; a first NMOS transistor of the first switching elements configured to be turned on in response to the first control code; a second NMOS transistor of the first switching elements configured to be turned on in response to the second control code; and a third NMOS transistor of the first switching elements configured to be turned on in response to the third control code.