Patent ID: 8088655

Claim:
A method for manufacturing a thin film transistor comprising: forming a lamination layer by laminating a first conductive film, a first insulating film, a second conductive film over an insulating surface in sequence; etching the lamination layer; laminating a semiconductor film, a second insulating film, and a third conductive film over a side surface of the lamination layer in sequence so as to form a gate insulating film over the semiconductor film and a gate electrode over the gate insulating film, and so that the semiconductor film overlaps with only a part of the second conductive film; forming a third insulating film over both the gate electrode and the second conductive film; and forming a fourth conductive film over the third insulating film so as to be electrically connected to the second conductive film through a hole of the third insulating film, and so as not to be in contact with the semiconductor film.