Patent ID: 7361951

Claim:
A semiconductor memory device comprising: a semiconductor substrate; an element isolation region provided in the semiconductor substrate, including a thick element isolating insulation film, and isolating an element region; a resistance element provided on the element isolation region and formed of a conductive film; a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region; and a second gate electrode provided on the first gate electrode with a first insulation film interposed therebetween, the second gate electrode having a first portion provided on the first gate electrode with the first insulation film interposed therebetween and a second portion extending on the element isolating insulation film, the second portion having a thickness different from that of the first portion; wherein the semiconductor substrate under the resistance element has an impurity concentration that decreases as a position gets closer to a surface of the semiconductor substrate, the resistance element and the second gate electrode are formed of substantially a same material, the resistance element and the second portion of the second gate electrode have substantially a same thickness, and the resistance element does not extend on the element region.