Patent ID: 8098972

Claim:
A reproduced signal processor for extracting recording timings from a reproduced signal, comprising: a clock generating circuit for outputting a clock having a frequency corresponding to a set digital value; a quantization circuit for quantizing and outputting the reproduced signal at timings of the output clock of the clock generating circuit; a frequency ratio calculating circuit for calculating a frequency ratio between a reproduction frequency of the reproduced signal and a frequency of the output clock of the clock generating circuit based on the reproduced signal quantized by the quantization circuit; a phase correction value calculating circuit for calculating a phase correction value based on the reproduced signal quantized by the quantization circuit; a pseudo-synchronous clock generating circuit for generating a pseudo-synchronous clock pseudo-synchronous with the recording timings and a phase of the pseudo-synchronous clock, depending on the frequency ratio calculated by the frequency ratio calculating circuit and the phase correction value calculated by the phase correction amount calculating circuit; and a modulation circuit for generating a modulation component using the output clock of the clock generating circuit and updating the set digital value with the modulation component, when the frequency ratio of the frequency ratio calculating circuit satisfies a preset condition.