Patent ID: 7484042

Claim:
A cache memory for a data processing system including an interconnect fabric and at least first and second coherency domains each containing at least one processing unit, said cache memory comprising: a data array; a cache directory of contents of said data array; and a cache controller including a prefetch predictor that determines a predicted scope of broadcast on the interconnect fabric for a first prefetch operation having a first target address based upon a scope of a previous second prefetch operation having a different second target address, wherein said cache controller issues said first prefetch operation on the interconnect fabric with said predicted scope; wherein: said cache memory belongs to said first coherency domain; and said prefetch predictor selects a first scope of broadcast including both said first and second coherency domains in response said previous second operation being serviced by a memory in said second coherency domain and selects a second scope of broadcast including said first coherency domain and excluding said second coherency domain in response to said second previous operation being serviced by a memory outside said second coherency domain.