Patent ID: 8094047

Claim:
An apparatus comprising: an output line; clock nodes to receive clock signals, wherein the clock signals are out of phase with each other; selector circuits to receive data in parallel, the selector circuits being responsive to the clock signals to transfer the data serially to the output line wherein one of the selector circuits includes: a first transistor coupled between a supply node and a circuit node, the first transistor having a gate to receive a first clock signal of the clock signals; a second transistor coupled in series with the first transistor between the supply node and the circuit node, the second transistor having a gate to receive a second clock signal of the clock signals, wherein the first and second clock signals have a phase difference; a third transistor coupled between the circuit node and a second supply node, the third transistor having a gate to receive the second clock signal; and a fourth transistor coupled in parallel with the third transistor between the circuit node and the second supply node, the fourth transistor having a gate to receive the first clock signal; and a control unit to influence at least a portion of a data at the output line.