Patent ID: 8184493

Claim:
A semiconductor memory device, comprising: a memory cell array including primary word lines and one or more redundant word lines; a timing signal generating circuit configured to generate a refresh timing signal comprised of a series of pulses arranged at constant intervals; and a refresh-target selecting circuit configured to successively select all the primary word lines and all the one or more redundant word lines one by one in response to the respective pulses of the refresh timing signal, wherein a refresh operation is performed with respect to the word lines that are successively selected by the refresh-target selecting circuit, wherein the refresh-target selecting circuit is configured to be switchable between a first mode and a second mode to successively select, in the first mode, word lines one by one that are equal in number to the primary word lines, and to successively select, in the second mode, all the primary word lines and all the one or more redundant word lines one by one.