Patent ID: 7782654

Claim:
A static random access memory device comprising: an SRAM cell comprising: a first CMOS inverter comprising a first PMOS transistor and a first NMOS transistor, drains of said first PMOS and NMOS transistors being coupled to a first node, gates of said first PMOS and NMOS PMOS transistors being coupled to a second node; a second CMOS inverter comprising a second PMOS transistor and a second NMOS transistor, a drain of said second PMOS and NMOS transistors being coupled to said second node, gates of said second PMOS and NMOS transistors being coupled to said first node; a first access transistor comprising one of source/drain coupled to said first node, and the other of source/drain coupled to a first bit line; a second access transistor comprising one of source/drain coupled to said second node, and the other of source/drain coupled to a second bit line; a first additional transistor comprising one of source/drain coupled to said first node, and a gate coupled to said second node; and a second additional transistor comprising one of source/drain coupled to said second node, and a gate coupled to said first node; and an additional transistor control circuit coupled to the others of source/drain of said first and second additional transistors, wherein said additional transistor control circuit is configured to receive a write enable signal, a column select signal, and a data input signal, and to generate each control signal for said first and second additional transistors.