Patent ID: 7256084

Claim:
A method of fabrication of a semiconductor device structure comprising the steps of: a) providing a substrate having a PFET region and a NFET region, a PFET gate over said PFET region, and a NFET gate over said NFET region; said PFET gate having PFET gate sidewalls; said NFET gate having NFET gate sidewalls; b) forming NFET source/drain regions adjacent to said NFET gate; then c) forming tensile PFET spacers over the PFET gate sidewalls and tensile NFET spacers over the NFET gate sidewalls; d) implanting first ions into the tensile PFET spacers to form neutralized PFET spacers whereby the first ions reduce a stress in the neutralized PFET spacers and reduce a stress in the PFET region; and e) forming PFET source/drain regions adjacent to said PFET gate.