Patent ID: 7412561

Claim:
An apparatus, comprising: control logic comprising a plurality of logic cells, at least one of the plurality of logic cells configured to receive an A operand and a B operand and perform the following logic operations comprising ĀB, A B , and AB; and switch circuitry coupled to receive input data, the switch circuitry coupled to the control logic to receive a result of the AB logic operation from each of the plurality of logic cells and selectively enable the output of one or more bits of the input data based on the results of the AB logic operations; wherein the control logic is coupled to receive a first plurality of enable signals, each of the first plurality of enable signals corresponding to a first plurality of one or more bits of a first segment of the input data, and wherein the control logic is coupled to receive a second plurality of enable signals, each of the second plurality of enable signals corresponding to a second plurality of one or more bits of a second segment of the input data.