Patent ID: 7235481

Claim:
A method of manufacturing a semiconductor device comprising: forming a gate electrode on a substrate including an active region and a field region; forming a gate spacer on sidewalls of the gate electrode; forming a silicidation blocking layer pattern on the substrate and the gate electrode, wherein the silicidation blocking layer pattern is formed to extend from the gate spacer to cover the field region and a portion of the active region, and the extended portion of the silicidation blocking layer pattern has a width of below about 10 percent of a width of the active region; forming a silcide layer on the portion of the active region not covered by the silicidation blocking layer pattern by reacting metal with silicon from the active region; forming an insulation layer on the substrate including the silicide layer; selectively etching the insulation layer to form an opening exposing the silicide layer under a condition having an etching selectivity between the silicidation blocking layer pattern and the insulation layer; and forming a conductive material to fill the opening.