Patent ID: 8458394

Claim:
A storage device, comprising: a buffer memory having N queues configured in parallel, each queue configured to store pages of data; a flash memory having N flash chips configured in parallel; a channel configured to concurrently convey a page of data from each of the N queues to a different one of the N flash chips; and a processor configured to concurrently program, during a programming operation, a page of data from each of the N queues to a different one of the N flash chips, via the channel, wherein: during each programming operation, the processor concurrently programs a page of data from each of the N queues that has a page of data inqueued to a different one of the N flash chips but does not so program a page of data from any of the N queues that does not have a page of data inqueued, and N is a natural number greater than 1.