Patent ID: 6946706

Claim:
An LDMOS transistor array structure comprising: an array that includes a plurality of alternating source regions and a plurality of alternating drain regions formed in a semiconductor substrate to define a checkerboard pattern of said alternating source and drain regions, wherein at least a first source region of the alternating source regions includes a first source region outer face which is orientated toward a first drain region face of a first drain region of the plurality of alternating drain regions, and wherein the first drain region face has a drain region face length and the source region outer face has a source region face length, and wherein the drain region face length is greater than the source region face length, wherein the first source region is disposed between the first drain region and a second drain region, and the first source is the only source region between the first drain region and the second drain region and the first source region is a contiguous region having a first conductivity type; a conductive source region interconnect structure formed in electrical contact with each of the plurality of alternating source regions in the array to electrically connect said source regions in parallel; and a conductive drain region interconnect structure formed in electrical contact with each of the plurality of alternating drain regions in the array to electrically connect said drain regions in parallel.