Patent ID: 8865546

Claim:
A method for manufacturing a semiconductor device, comprising: forming a tunnel insulation film on a semiconductor substrate; forming a first conductive film on the tunnel insulation film; forming an intermediate insulating film on the first conductive film; forming a second conductive film over the intermediate insulating film; patterning the first conductive film, the intermediate insulating film and the second conductive film to form a floating gate and control gate of a flash memory cell in a first region and to form a first gate electrode of a MOS transistor on a part of the tunnel insulation film in a second region; forming a first impurity diffusion region and a second impurity diffusion region, that is located between the flash memory cell and the first gate electrode in a plan view, as source/drain regions of the flash memory cell in the first region; thermally oxidizing surfaces of each of the semiconductor substrate and the floating gate after forming the first impurity diffusion region and the second impurity diffusion region, a thickness of the tunnel insulation film in the first region being larger than a thickness of the tunnel insulation film in the second region after thermally oxidizing; removing the tunnel insulation film located on a partial region of the first impurity diffusion region after thermally oxidizing; forming a first metal silicide layer on the partial region of the first impurity diffusion region; forming an interlayer insulating film covering the flash memory cell and the MOS transistor; forming a first hole in the interlayer insulating film over the partial region; and forming a conductive plug connected to the first metal silicide layer in the first hole.