Patent ID: 7795710

Claim:
A package ( 38 ) for encasing at least one semiconductor device ( 28 ), comprising: a lead frame including an electrically conductive substrate and having opposing first and second sides, said first side of said lead frame having a planar first side surface and an array of lands ( 14 ), each of said lands protruding from said first side surface, said lands adapted to be bonded to external circuitry and being arranged in a first pattern, and said second side of said lead frame having a planar second side surface and an array of chip attach sites ( 24 ), each of said chip attach sites protruding from said second side surface, said chip attach sites being arranged in a second pattern and being directly electrically interconnected by interconnections ( 30 ) to input/output pads on said at least one semiconductor device ( 28 ), said chip attach sites disposed opposite said input/output pads, and a plurality of electrically isolated routing circuits ( 26 ) electrically interconnecting individual combinations of said array of lands ( 14 ) and said array of chip attach sites ( 24 ); a first molding compound ( 18 ) disposed on said first side surface and between individual lands of said array of lands ( 14 ); and a second molding compound ( 36 ) encapsulating said at least one semiconductor device ( 28 ), said array of chip attach sites ( 24 ) and said routing circuits ( 26 ), wherein the lands and chip attach sites are formed from a monolithic electrically conductive structure, and the array of lands has a larger lateral extent than the array of chip attach sites.