Patent ID: 7774549

Claim:
A processor comprising: a first processor core unit including a first processor core capable of processing first data and a first cache memory adapted to store first data; and a second processor core unit including a second processor core capable of processing second data and a second cache memory adapted to store at least second data; wherein the processor includes logic adapted to receive a selection of a first victim line from the first cache memory, to identify a candidate line in the second cache memory, and to store the first victim line in the candidate line in the second cache memory, wherein the logic adapted to identify the candidate line in the second cache memory includes logic adapted to evaluate a cache priority rule to select the candidate line from a set of potential candidate lines, wherein the cache priority rule is based on an estimated performance gain of the processor associated with storing the first victim line in the selected candidate line, wherein the logic adapted to evaluate a cache priority rule includes logic adapted to determine at least one estimated performance gain for the first processor core in response to storing the first victim line in at least one of the set of potential candidate lines, wherein the logic adapted to determine at least one estimated performance gain for the first processor core includes a plurality of incremental gain counters, wherein each incremental gain counter is associated with a portion of the first cache memory and adapted to count cache hits in the associated portion of the first cache memory, wherein the logic adapted to determine at least one estimated performance gain for the first processor core includes an allocation counter adapted to output an allocation value based on the size of the portion of the first cache memory storing data associated with the first processor core, wherein the logic adapted to determine at least one estimated performance gain is adapted to use the allocation value to select one of the plurality of incremental gain counters, wherein the value of the selected incremental gain counter represents the estimated performance gain of the first processor core.