Patent ID: 6992941

Claim:
A semiconductor memory device, comprising: a memory cell array in which memory cells are arranged in a matrix; a plurality of word lines connecting gate terminals of memory cells commonly in a row direction; a plurality of bit lines connecting drain terminals of memory cells commonly in a column direction; a determination circuit for determining data of the memory cells; a column selection circuit for selectively connecting the bit lines to the determination circuit; a charging circuit for charging the bit line selected by the column selection circuit and an input terminal of the determination circuit; and a charge signal generation circuit for controlling the charging circuit, wherein the charging circuit includes: a first charging subcircuit that is operated when an output signal of the charge signal generation circuit is in an active state; and a second charging subcircuit that is operated when the output signal of the charge signal generation circuit is in an active state and a voltage of the selected bit line is lower than a predetermined voltage.