Patent ID: 8053841

Claim:
A semiconductor device, comprising: a substrate including first, second and third regions having respective active regions which are separated from one another by an isolation layer, the active region of the first region being provided as a fin active region; a gate insulation layer formed over the active regions of the first through third regions, the gate insulation layer being provided as a first resultant structure; and first, second and third gate electrodes disposed over the substrate of the first through third regions respectively, wherein a fin transistor is provided in the first region, and work functions of the first through third gate electrodes are different from one another, the first gate electrode having the work function between those of the second and third gate electrodes, and wherein the first through third gate electrodes are formed by a process comprising the steps of: forming a silicon germanium (SiGe) layer over the first resultant structure where the gate insulation layer is formed; removing the SiGe layer of the second and third regions through masking and etching processes, thereby forming a second resultant structure; forming an undoped polysilicon layer along a surface profile of the second resultant structure of the first through third regions; performing a planarization until the surface of the SiGe layer of the first region is exposed; and selectively implanting n-type impurities onto the second region, and p-type impurities onto the third region.