Patent ID: 8716861

Claim:
A semiconductor package having electrical connecting structures, comprising: a conductive layer with a plurality of traces, the traces each having a trace body, a contact pad formed at an end of the trace body and positioned proximate to a chip, and a trace end formed at another end of the trace body and positioned distal to the chip; the chip connected to the contact pads in a flip-chip manner; an encapsulant for encapsulating the chip and the conductive layer, wherein the encapsulant has a plurality of cavities for embedding the conductive layer therein, the cavities being of a depth larger than a thickness of the conductive layer and allowing a surface of the conductive layer to be exposed therefrom; a solder mask layer formed on the exposed surface of the conductive layer and a bottom surface of the encapsulant and having a plurality of openings for exposing the trace ends, respectively; and a plurality of solder balls formed in the openings of the solder mask layer so as to be electrically connected to the trace ends, respectively.