Patent ID: 7109566

Claim:
A semiconductor device comprising: a device isolation layer disposed in a substrate to define an active region; source and drain regions formed in the active region; a gate electrode formed on the active region between the source and drain regions; a gate insulation layer interposed between the gate electrode and the active region; a resistor pattern formed on the device isolation layer; resistor spacers disposed on sidewalls of the resistor pattern; an interlayer dielectric layer disposed over the resistor pattern; and resistor electrodes connected to both ends of the resistor pattern, respectively, wherein the gate electrode includes a polysilicon layer and a silicide layer that are sequentially stacked on the gate insulation layer, wherein the resistor pattern includes a single-layer polysilicon layer, wherein substantially the entire resistor pattern does not have a silicide layer disposed thereon, wherein the resistor spacer protrudes above the resistor pattern, and wherein the interlayer dielectric layer contacts a portion of the resistor spacer.