Patent ID: 8295419

Claim:
A clock generator circuit comprising: a chip level reference clock input, with the chip level reference clock input providing a signal to: a) logic circuitry, and b) a synchronization signal generation circuit for generating a synchronization signal, the logic circuitry having a delayed reference clock output as input with a feedback clock signal to a phase locked loop, the phase locked loop providing an input to a global clock generation circuit for generating a global clock, the global clock being an input to: c) at least one local clock buffer and latch, d) a mimic circuit feedback path including a mimic local clock buffer, one or more mimic receivers, and mimic logic circuitry; wherein an output of one of the one or more mimic receivers is input to the synchronization signal generation circuit; wherein an output of one of the one or more mimic receivers is input to the mimic logic circuitry; and wherein an output of the mimic logic circuitry is input to the phase locked loop as the feedback clock signal.