Patent ID: 8793700

Claim:
A processing resource apparatus comprising: one or more processor cores; a scan chain comprising a first set of stateful elements and a second set of stateful elements; a reference processing module to perform a first data processing operation based on state information stored at the first set of stateful elements; a target processing module to perform a second data processing operation based upon state information stored at the second set of stateful elements; a synchronization circuit to perform a synchronization operation, in a synchronization mode, the synchronization circuit comprising an enable input, in response to the enable input being asserted the synchronization circuit selectively couples an output of the first set of stateful elements to a scan input of the first set of stateful elements and to a scan input of the second set of stateful elements, and counting circuitry to control clocking the scan chain a predetermined number of times to synchronize the state information stored at the second set to the state information stored at the first set, wherein the first and second data processing operations are synchronized in response to the state information stored at the first and second sets being synchronized; and a manufacturing testing circuit to perform a manufacturing test operation, in a testing mode, the manufacturing testing circuit comprising a test enable input, in response to the test enable input being asserted the manufacturing testing circuit selectively couples the scan input of the first set of stateful elements to a scan data input and couples the scan input of the second set of stateful elements to the scan data input.