Patent ID: 7729185

Claim:
Apparatus for performing a test sequence to detect address decoder open faults in a memory device, comprising: base address generation circuitry for generating a plurality of base addresses; derived address generation circuitry, responsive to a base address portion of each base address generated by the base address generation circuitry, to generate an associated series of derived addresses for that corresponding base address, each derived address being different to any other derived address in said associated series and having a derived address portion differing from the corresponding base address portion by a single address bit value; and read/write sequence generator circuitry, responsive to each base address in turn, to write in said memory device a first data value at that base address and a second data value at each derived address in said associated series of derived addresses for that base address, the read/write sequence generator circuitry being arranged to read a data value stored at the base address each time the second data value is written to one of said derived addresses in said associated series, and to detect an address decoder open fault if said read data value is said second data value.