Patent ID: 7659159

Claim:
A method of fabricating a flash memory device, the method comprising: providing a semiconductor substrate in which a tunnel insulating layer and a first conductive layer are stacked on an active region and a trench is formed in an isolation region; forming a first insulating layer on a surface of the trench and on a surface of the first conductive layer; forming a second insulating layer over the first insulating layer so that the trench is filled; removing portions of the first and second insulating layers to expose a first portion of the sidewalls of the first conductive layer, the first insulating layer and the second insulating layer remaining on the sidewalls of the trench and on a second portion of the sidewalls of the first conductive layer, wherein a height of the second insulating layer is lower than a height of the first insulating layer remaining on the second portion of the sidewalls of the first conductive layer; forming a third insulating layer over the first and second insulating layers so that a space defined by the first conductive layer is filled, wherein the third insulating layer contacts the first insulating layer remaining on the second portion of the sidewalls of the first conductive layer; removing a portion of the third insulating layer so that a height of the third insulating layer is lowered and a portion of the first insulating layer remains on the second portion of the sidewalls of the first conductive layer; and forming a dielectric layer and a second conductive layer for a control gate over the semiconductor substrate including the first conductive layer.