Patent ID: 6912179

Claim:
A cue delay circuit for an ink jet printing system, wherein the cue delay circuit comprises: a. a state machine comprising a plurality of sequenced logic circuits adapted to receive a start pulse for initializing the state machine, and wherein the state machine receives a tachometer input and generates a plurality of buffered control signals; b. a counter comprising a plurality of sequenced logic circuits to count one of the buffered control signals from the state machine forming a read address; c. an adder adapted to receive the read address and a cue delay value, wherein the adder adds the read address to the cue delay value and generates a write address; d. a comparator adapted to compare the cue delay value to the read address to determine if the read address is greater than the cue delay value, wherein the comparator forms a comparator output; e. a multiplexer (MUX) adapted to receive the read address, the write address, and one of the buffered control signals and forms a multiplexer output; f. a read-access memory (RAM) adapted to receive the multiplexer output, wherein the multiplexer output serves as an address for the RAM and provides a RAM output signal; g. at least one flip flop adapted to latch to the comparator output forming a latched comparator output; h. a gate circuit for receiving the latched comparator output and the RAM output signal, wherein the gate circuit forms a gated cue signal; and i. a logic circuit adapted to receive one of the buffered control signals, the gated cue signal, wherein the logic circuit outputs a delayed cue signal to the printing system.