Patent ID: 8470663

Claim:
A method of manufacturing a semiconductor device, comprising: forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region; forming a first preliminary insulating interlayer on the integrated structures, an upper surface of the first preliminary insulating interlayer being higher than an upper surface of the hard mask patterns; performing a first polishing of the first preliminary insulating interlayer until at least one upper surface of the hard mask patterns is exposed, forming a second preliminary insulating interlayer; etching the second preliminary insulating interlayer until the upper surfaces of the hard mask patterns are exposed, forming a third preliminary insulating interlayer; and performing a second polishing of the hard mask patterns and the third preliminary insulating interlayer until the polysilicon patterns are exposed, forming an insulating interlayer.