Patent ID: 7523292

Claim:
An array-type processor, comprised of a plurality of processor elements that individually perform data processing in accordance with instruction codes provided by a plurality of state control units, and having switch-controlled connections between the processor elements, wherein the processor elements are arranged in rows and columns; and wherein the processor elements are further arranged in a plurality of element areas, each element area comprising a plurality of processor elements and a respective one of the plurality of state control units connected to the plurality of processor elements on a same plane as the plurality of processor elements and providing instruction codes to the plurality of processor elements, wherein the state control units issue instruction codes to the plurality of processor elements in each respective element area in every cycles, wherein buffer regions are formed between adjacent ones of said plurality of element areas; wherein transfer moderation circuits are arranged in said buffer regions for moderating data transfers of said processor elements of said plurality of element areas on both sides of said buffer regions; wherein a central control unit is arranged at a central position with respect to the buffer regions, wherein the central control unit intercommunicates with the plurality of state control units to control operations of said transfer moderation circuits; wherein said transfer moderation circuits each comprise a pair of buffer circuits that are arranged in parallel and that have reciprocal directions of data transfer, wherein a first subset of said buffer regions form a single column in which said central control unit is also disposed, and wherein a second subset of said buffer regions form a single row in which said central control unit is also disposed.