Patent ID: 8842464

Claim:
An integrated circuit memory device, comprising: an array of static random access memory (SRAM) cells arranged as a plurality of columns of SRAM cells electrically coupled to corresponding plurality of pairs of bit lines and a plurality of rows of SRAM cells electrically coupled to a corresponding plurality of word lines; a word line driver electrically coupled to the plurality of word lines, said word line driver configured to drive a selected word line with a positive voltage and a plurality of unselected word lines with a negative voltage during an operation to write data into a selected one of the SRAM cells; and a column decoder comprising a plurality of pairs of selection switches electrically coupled to corresponding ones of the plurality of pairs of bit lines, said column decoder configured to drive control terminals of a first of the plurality of pairs of selection switches coupled to the selected one of the SRAM cells with positive voltages concurrently with driving control terminals of a second of the plurality of pairs of selection switches coupled to an unselected one of the SRAM cells with negative voltages during the operation to write data; wherein the selection switches are NMOS pass gate transistors; wherein the control terminals of the selection switches are gate electrodes of respective NMOS pass gate transistors; and wherein the gate electrodes of the NMOS pass gate transistors associated with the second of the plurality of pairs of selection switches receive the negative voltages during the operation to write data.