Patent ID: 7471132

Claim:
An electronic pulse width modulator circuit operating from a system supply voltage and having an output terminal, the circuit comprising: a multiplexer having select terminals, input terminals, a common pre-charge node, and a pre-charge device configured to provide a voltage for the common pre-charge node, the voltage being less than the system supply voltage; a state machine coupled to the output terminal and to a tap select register, the tap select register further coupled to the multiplexer select terminals; a clock delay chain having a plurality of delay chain elements and delay chain taps, each delay chain tap coupled to one of the input terminals; and a pre-charge control circuit coupled to the pre-charge device and to the output terminal, the pre-charge control circuit being configured to operate by delaying an output signal from the output terminal, adjusting the logic polarity of the delayed output signal, and coupling the delayed and adjusted output signal to the pre-charge device.