Patent ID: 8421250

Claim:
A semiconductor device comprising: an alignment mark formation region; and an integrated circuit formation region; the semiconductor device including: (a) a semiconductor substrate; (b) a MISFET formed over the semiconductor substrate, the MISFET being formed in the integrated circuit formation region; (c) a first wiring layer formed over the MISFET, the first wiring layer formed in the integrated circuit formation region; (d) a plurality of first patterns formed over the semiconductor substrate and in the same layer as the first wiring layer, the plurality of first patterns being formed in the alignment mark formation region; (e) a first interlayer insulating film formed over the semiconductor substrate to cover the first wiring layer and the plurality of first patterns; (f) a second wiring layer formed over the first interlayer insulating film, the second wiring layer being formed in the integrated circuit formation region; (g) a plurality of second patterns formed over the first interlayer insulating film and in the same layer as the second wiring layer, the plurality of second patterns being formed in the alignment mark formation region; (h) a second interlayer insulating film formed over the semiconductor substrate to cover the second wiring layer and the plurality of second patterns; (i) an alignment mark formed over the second interlayer insulating film, the alignment mark being formed in the alignment mark formation region; and (j) an insulating film formed over the semiconductor substrate to cover the alignment mark, wherein the plurality of first patterns and the plurality of second patterns are formed so as to be shifted from each other in a plan view, and wherein the plurality of first patterns and the plurality of second patterns are not electrically connected to the MISFET.