Patent ID: 7217579

Claim:
A method for electrically testing a semiconductor wafer during integrated-circuit fabrication process, the method comprising: scanning a zone on a surface of the semiconductor wafer, while the semiconductor wafer is kept stationary, with a scanning charged-particle microscope (SCPM) having a scanning window, which has a given maximum size; the surface having one or more test structures including one or more patterns comprised of interconnected conducting segments conductively coupled to one or more clusters of mutually isolated pads where each pad is conductively connected with a corresponding distinct point on the one or more patterns and all the pads in any one cluster are sized and arranged so that at least a significant portion of each pad falls within the zone; wherein the zone is sized such that it does not exceed the given maximum size of the scanning window of the SCPM; and obtaining information about the electrical state of the one or more test structures associated with each pad.