Patent ID: 7689818

Claim:
A method for centralized dynamic link configuration (CDLC), performed by a processor and a chipset, comprising: notifying the chipset of CDLC enablement by the processor; issuing a command to the processor by the chipset after receiving the notification of CDLC enablement; broadcasting a preparation completion signal by the processor after receiving the command; asserting a signal and activating a timer to start counting by the chipset after receiving the preparation completion signal; configuring devices of the processor, corresponding to a bus, by the processor according to one of a plurality of sets of first link management mode (LMM) configuration parameters in a first LMM register of the processor, indicated by first link management action field (LMAF) code in a first LMAF register of the processor, after detecting that the signal is asserted; configuring devices of the chipset, corresponding to the bus, by the chipset according to one of a plurality of sets of second LMM configuration parameters in a second LMM register of the chipset, indicated by second LMAF code in a second LMAF register of the chipset, when asserting the signal; and de-asserting the signal by the chipset when the timer reaches a predetermined value.