Patent ID: 7324374

Claim:
An architecture that facilitates a reference voltage in a multi-bit memory, comprising: a multi-bit memory core including a plurality of data cells for storing data; first and second reference arrays fabricated adjacent to each other and associated with one of a plurality of sectors comprising multi-bit data cells, the first and second reference arrays each comprised of a plurality of multi-bit reference cells fabricated on the memory core, wherein reference cells within the first reference array have a first voltage level and reference cells within the second reference array have a second voltage level, the second voltage level different than the first voltage level, the first and second reference arrays precharged before being averaged; a first bit value of a first reference cell of the first reference array averaged with a second bit value of a second reference cell of the second reference array to arrive at the reference voltage employed during a data cell read operation; and a redundancy array located at least one of proximate and adjacent to groups of data sectors.