Patent ID: 7629212

Claim:
A method of fabricating dual metal gate structures in a semiconductor device, the method comprising: forming a gate dielectric layer in PMOS and NMOS regions above a semiconductor substrate; forming a work function adjusting layer on the dielectric gate layer in the PMOS region; depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region; depositing a tungsten germanium gate electrode layer above the gate dielectric layer in the NMOS region; annealing the semiconductor device; depositing a metal nitride barrier layer on the tungsten germanium layer in the PMOS region and on the tungsten germanium layer in the NMOS region; depositing a polysilicon layer over the metal nitride barrier layer; patterning the polysilicon layer, the metal nitride barrier layer, the tungsten germanium layer in the PMOS region, the tungsten germanium layer in the NMOS region, the work function adjusting layer, and the gate dielectric layer to form gate structures with different work functions in the NMOS and PMOS regions; and forming source/drains on opposite sides of the respective gate structures.