Patent ID: 7808075

Claim:
An integrated circuit, comprising: a) a first semiconductor die comprising a first plurality of exposed terminals and a plurality of features having a first minimum feature size less than or equal to 0.13 μm; and b) a second semiconductor die comprising: i) a second plurality of exposed terminals, wherein at least one of said second plurality of exposed terminals is in electrical communication with one or more of said first plurality of exposed terminals, ii) a plurality of input and/or output (I/O) circuits, wherein at least one of said I/O circuits is in electrical communication with said at least one of said second plurality of exposed terminals, and iii) a plurality of I/O terminals, wherein at least one of said I/O terminals is in electrical communication with said at least one of said I/O circuits, wherein all features on the second die have a second minimum feature size greater than or equal to 0.18 μm.