Patent ID: 7544612

Claim:
A method for fabricating a multilayer semiconductor structure, said method comprising steps of: forming first and second patterned segments, a sidewall of said first patterned segment that faces a sidewall of said second patterned segment being separated from said sidewall of said second patterned segment by a first gap; forming a first conformal layer over said first and second patterned segments and said first gap, said first conformal layer being in direct contact with said first and second patterned segments without any intervening layer therebetween, said first conformal layer forming a depression having substantially vertical sidewalls over said first gap; forming a third patterned segment in said depression having said substantially vertical sidewalls such that a sidewall of said third patterned segment is separated from a substantially vertical sidewall of said depression by a second gap; and forming a second conformal layer over said first conformal layer, said third patterned segment, and said second gap, a dip being formed in said second conformal layer over said second gap; wherein said step of forming said third patterned segment includes forming said third patterned segment at a location in said depression having said substantially vertical sidewalls so that said sidewall of said third patterned segment that faces said sidewall of said first patterned segment is laterally separated from said sidewall of said first patterned segment by a distance that is less than or equal to a thickness of a sum of said first and second conformal layers to reduce a size of said dip in said second conformal layer.