Patent ID: 8397030

Claim:
A method of controlling region coherence in a clustered shared-memory multiprocessor system, the method comprising: generating a request by a processor for a line of data storable in a system memory; determining, via examination of at least one entry in a plurality of entries of a region coherence array, at least one level of a multi-level interconnect hierarchy which has recently cached at least one line of data of a region of the system memory, such that the region includes the requested line of data, wherein each entry in the region coherence array has one or more of a valid bit, one or more parity bits, a region address tag, and a plurality of line-count bits, and a non-zero bit, and wherein each entry in the region coherence array also has a region coherence state field, the region coherence state field having one region coherence state bit per level of the multi-level interconnect hierarchy; and updating the at least one entry in the region coherence array associated with the requesting processor responsive to determining the at least one level of the multi-level interconnect hierarchy.