Patent ID: 7401189

Claim:
In a memory component, a method comprising: selecting, within a first pipelined path, a least recently used (LRU) victim member from a congruence class; and biasing a faulty member of the memory component against being selected as the victim member by the first pipeline path, said faulty member corresponding to a cache line that is unable to provide proper caching operation; separately making the faulty member MRU without affecting a directional pointer of LRU selection chronology vectors for a multi-level chronology vector LRU selection mechanism; and receiving information about which member is a faulty member from a directory via a second pipeline path, separate from the first pipeline path; generating a make MRU vector from an index indicating one or more locations of faulty member(s) and forwarding the make MRU vector to an MRU update logic that performs a make MRU operation, independent of a pipelining and processing of member protection bits for generating a final make MRU vector.