Patent ID: 6954093

Claim:
A method for generating a clock signal in a monolithic integrated circuit, said method comprising: generating a basic clock signal; processing said basic clock signal through a series of nominally equal delays to generate a plurality of intermediate clock signals which are delayed relative to each other, the individual delays being distributed within a period T of the basic clock rate, wherein the time period for each of said delays is time-modulated by a random signal (s 2 ); receiving at each of a plurality of data-processing blocks at least one of said plurality of intermediate clock signals, wherein said plurality of data-processing blocks includes a transmitting data-processing block (D 2 ) and a receiving data-processing block (D 1 ), and the delay of a second intermediate clock (c 2 ) assigned to the transmitting data-processing block is greater than the delay of a first intermediate clock (c 1 ) assigned to the receiving data-processing block.