Patent ID: 8009463

Claim:
A multi-port static random access memory (SRAM) cell comprising: first and second cross-coupled inverters having a data storage node and a data bar storage node, each inverter comprising a pull-up transistor and a pull down device, wherein each pull down device comprises at least a pair of pull down transistors having commonly connected source, drain and gate terminals; and first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the data storage node and a second pass gate transistor coupled to the data bar storage node, each pass gate transistor being coupled to a respective bit line conductor, wherein the pull down transistors of the first inverter are formed in a first active region, the pull down transistors of the second inverter are formed in a second active region, the pass gate transistors coupled to the data storage node are formed in a third active region and the pass gate transistors coupled to the data bar storage node are formed in a fourth active region.