Patent ID: 7616568

Claim:
A process to generate packets, comprising: defining a first packet stream comprising a first plurality of packets; composing and transmitting the first plurality of packets at a first packet frequency, wherein the transmission of the first plurality of packets is controlled by a first series of interrupts from a hardware timer, and each packet of the first plurality of packets is comprised of a first background data field and one or more user defined fields that overlay the first background data field; defining a second packet stream comprising a second plurality of packets; composing and transmitting the second plurality of packets at a second packet frequency different from the first packet frequency, wherein the first packet stream and the second packet stream are transmitted, at least in part, concurrently, and the transmission of the second plurality of packets at the second packet frequency is controlled by a second series of interrupts interleaved with the first series of interrupts from the hardware timer; and generating a time reference signal controlled by a third series of interrupts interleaved with the first series of interrupts and second series of interrupts from the hardware timer.