Patent ID: 7466605

Claim:
A nonvolatile semiconductor memory device comprising: a plurality of non-volatile memory cells divided into sectors; a first decoder including a pull-up transistor for selecting and driving a word line connected to the plurality of non-volatile memory cells; a first voltage generating circuit generating a first voltage applied to a source terminal of the pull-up transistor; a vertical word line connecting the sectors in a vertical direction and carrying the first voltage from the first voltage generating circuit to the source terminal of the pull-up transistor; a second voltage generating circuit generating a second voltage that is applied to a gate terminal of the pull-up transistor and is higher than the first voltage; a global word line connecting the sectors in a lateral direction and carrying the second voltage from the second voltage generating circuit to the gate terminal of the pull-up transistor; a second decoder selecting and driving the global word line; and a third decoder selecting and driving the vertical word line.