Patent ID: 7342520

Claim:
A serializer for converting N-bit wide parallel input data words with rate B into a serial data bit stream with rate NB of out-going serial words, comprising: a first multiplexer with ratio N:L for conversion of the N-bit wide parallel input data words with rate B into L-bit wide data words with rate NB/L; a converter for generating encoded data words from the L-bit wide data words; a second multiplexer with ratio L:1 for conversion of the encoded data words with rate NB/L into a serial data bit stream with rate NB; a multilevel buffer for generating a multilevel output signal with marking pulses using the serial bit data stream and a synchronization signal; and a timing circuit for generating the synchronization signal, wherein the multilevel buffer further comprises: a retiming sub-block for conversion of L-bit long synchronization pulses into 1-bit long retimed synchronization pulses; and a single-ended current-switching stage for generating a multilevel serial data signal in which an amplitude of a bit coincident with a synchronization pulse and having a preselected logic value is increased.