Patent ID: 7102958

Claim:
A memory system comprising: a command/address bus including a plurality of command/address lines; a first integrated circuit memory device comprising a first plurality of command/address pins coupled to the command/address lines of the command/address bus, a first mode register configured to store information defining an operational characteristic of the first memory device, and a first command decoder configured to accept a mode register set command responsive to an enable signal received on a first predetermined pin of the first integrated circuit memory device and to reject a mode register set command responsive to a disable signal received on the first predetermined pin so that information of a mode register set command is saved to the first mode register when the enable signal is received on the first predetermined pin during a mode register set operation; a second integrated circuit memory device comprising a second plurality of command/address pins coupled to the command/address lines of the command/address bus, a second mode register configured to store information defining an operational characteristic of the second memory device, and a second command decoder configured to accept a mode register set command responsive to an enable signal received on a second predetermined pin of the second integrated circuit memory device and to reject a mode register set command responsive to a disable signal received on the second predetermined pin so that information of a mode register set command is saved to the second mode register when the enable signal is received on the second predetermined pin during a mode register set operation; and a memory controller coupled to the command/address bus wherein the memory controller is configured to transmit a first mode register set command over the command/address bus to the first and second pluralities of command/address pins of the first and second integrated circuit memory devices during a first mode register set operation, the memory controller being further configured to transmit a first enable signal to the first predetermined pin of the first integrated circuit memory device and to transmit a first disable signal to the second predetermined pin of the second integrated circuit memory device during the first mode register set operation.