Patent ID: 7812352

Claim:
A thin film transistor array substrate, comprising: a substrate, having a pixel region and a bonding pad region located surrounding the pixel region; a patterned polysilicon layer, disposed within the pixel region on the substrate and comprising a source and a drain; a first patterned insulating layer, covering the patterned polysilicon layer; a first patterned transparent conductive layer, disposed on the first patterned insulating layer; a first metal layer, partially disposed on the first patterned transparent conductive layer and comprising a gate, a scan line electrically connected to the gate and a common line disposed within the pixel region, wherein a part of the first patterned transparent conductive layer is disposed under the common line; a second patterned insulating layer, covering the first metal layer, wherein the first patterned insulating layer and the second patterned insulating layer have a first contact hole to expose the drain; a second patterned transparent conductive layer, disposed on the second patterned insulating layer, wherein a part of the second patterned transparent conductive layer is electrically connected to the drain via the first contact hole; a second metal layer, partially disposed on the second patterned transparent conductive layer; wherein the second metal layer comprises a data line electrically connected to the source, and a part of the second patterned transparent conductive layer is disposed under the data line; a third patterned insulating layer, covering the second metal layer and having a second contact hole to expose the second patterned transparent conductive layer electrically connected to the drain; and a third patterned transparent conductive layer, disposed on the third patterned insulating layer and comprising a pixel electrode located within the pixel region, wherein the pixel electrode is electrically connected to the second patterned transparent conductive layer via the second contact hole.