Patent ID: 7885109

Claim:
A memory, comprising: a current generator, generating a control current; at least one bit line, coupled or dis-coupled to the current generator by a bit line selector; at least one memory cell, coupled to the bit line and comprising a transistor and a storage element that are coupled in series, wherein the transistor is turned on or off by a word line signal and the storage element is switched between a plurality of states according to current flowing therethrough; and a current leakage suppressor, comprising: an inverter, having an input terminal receiving an enable signal and an output terminal outputting an opposite phase signal of the enable signal; a first transmission gate, coupled between a ground and the power supply input terminal of the current source, and having a first control terminal and a second control terminal coupled to the input and output terminals of the inverter, respectively; and a second transmission gate, coupled between the voltage source and the power supply input terminal of the current source, and having a first control terminal and a second control terminal coupled to the output terminal and the input terminal of the inverter, respectively.