Patent ID: 7119583

Claim:
A phase detector operable to generate either a first control signal or a second control signal responsive to a difference in phase between a first input signal and a second input signal, the phase detector comprising: a signal comparator operable to compare the phase of the first input signal to the phase of the second input signal, the signal comparator comprising: a first delay circuit having an output and an input coupled to receive the first input signal, the first delay circuit being operable to delay the first input signal by a first delay value and couple the delayed first input signal to the output; a second delay circuit having an output and an input coupled to receive the second input signal, the second delay circuit being operable to delay the second input signal by a second delay value and couple the delayed second input signal to the output; a third delay circuit having an output and an input coupled to receive the first input signal, the third delay circuit being operable to delay the first input signal by a third delay value and couple the delayed first input signal to the output; a fourth delay circuit having an output and an input coupled to receive the second input signal, the fourth delay circuit being operable to delay the second input signal by a fourth delay value and couple the delayed second input signal to the output; a first flip-flop having a set input coupled to the output of the first delay circuit, a reset input coupled to the output of the second delay circuit, and a pair of complimentary first and second outputs; and a second flip-flop having a set input coupled to the output of the third delay circuit, a reset input coupled to the output of the fourth delay circuit, and a pair of complimentary first and second outputs; and a signal generator coupled to the first and second flip-flops of the signal comparator, the signal generator being operable to generate the first control signal responsive to signals from the first and second flip-flops indicative of the phase of the first input signal being greater than the phase of the second input signal by at least a first phase difference, and to generate the second control signal responsive to signals from the first and second flip-flops indicative of the phase of the first input signal being less than the phase of the second input signal by at least a second phase difference, the signal generator further being operable to generate neither the first control signal nor the second control signal responsive to either signals from the first and second flip-flops indicative of the first input signal being greater than the phase of the second input signal by less than the first phase difference or signals from the first and second flip-flops indicative of the first input signal being less than the phase of the second input signal by less than the second phase difference.