Patent ID: 7039146

Claim:
A clock selection device adapted to select one of a pair of clock sources onto an output clock line, comprising: a first input clock line coupled to a first clock source; a second input clock line coupled to a second clock source, the second clock source asynchronous to the first clock source; a clock selection logic adapted to select from the first input clock line and the second input clock line, producing an internal clock line coupled to the output clock line; and a clock synchronization logic coupled to the first input clock line, the second input clock line, and the clock selection logic, adapted to synchronize the first input clock line, the second input clock line, and the clock selection logic, such that the internal dock line is glitch free, the clock synchronization logic triggering the clock selection logic to select from the first input clock line and the second input clock line, the clock synchronization logic comprising: an OR gate coupled to a clock select line and an internal feedback line of the clock synchronization logic; a first plurality of flip-flops coupled to the output of the OR gate and the second input clock line, producing a clock switch line adapted to cause the clock selection logic to switch between the first clock source and the second clock source; an AND gate coupled to the clock select line and the clock switch line; and a second plurality of flip-flops coupled to the output of the AND gate and the first input clock line, the output of the second plurality of flip-flops coupled to the internal feedback line, wherein the clock synchronization logic is independent of the internal clock line, wherein the first clock source has a first frequency, and wherein the second clock source has a second frequency, the second frequency independent of the first frequency.