Patent ID: 8106458

Claim:
A semiconductor device comprising: a first complementary metal-oxide-semiconductor (CMOS) circuit located on a semiconductor-on-insulator (SOI) substrate, wherein said first CMOS circuit comprises at least one first n-FET and at least one first p-FET; a second CMOS circuit located on said SOI substrate, wherein said second CMOS circuit comprises at least one second n-FET and at least one second p-FET, wherein said SOI substrate includes: a semiconductor device layer containing source and drain regions of said at least one first n-FET, said at least one first p-FET, said at least one second n-FET, and said at least one second p-FET; a second buried insulator layer contacting said semiconductor device layer; a first substrate region contacting said second buried insulator layer and underlying said at least one first n-FET and said at least one first p-FET of said first CMOS circuit, wherein said second buried insulator layer electrically isolates said semiconductor device layer from said first substrate region; a second substrate region contacting said second buried insulator layer and underlying said at least one second n-FET and said at least one second p-FET of said second CMOS circuit, wherein said second buried insulator layer electrically isolates said semiconductor device layer from said second substrate region, wherein said second substrate region is electrically isolated from said first substrate region; a first buried insulator layer contacting said first and second substrate regions; and a base semiconductor layer located directly beneath said first buried insulator layer, wherein said first buried insulator layer electrically isolates said first and second substrate regions from said base semiconductor layer; a first voltage applicator configured to electrically bias said at least one first n-FET and said at least one first p-FET by applying a first common substrate bias voltage to said first substrate region; and a second voltage applicator configured to electrically bias said at least one second n-FET and said at least one second p-FET by applying a second common substrate bias voltage to said second substrate region, wherein said first common substrate bias voltage and said second common substrate bias voltage are different.