Patent ID: 7546512

Claim:
An apparatus, comprising: a first stage to include a first set of computation elements, a first multiplexer and a second multiplexer; a latch to connect to said first stage; a second stage to connect to said latch, said second stage to include a second set of computation elements and a third multiplexer, wherein a first computation element from said second set of computation elements is to perform cyclic redundancy checks for one byte, a second computation element from said second set of computation elements is to perform cyclic redundancy checks for two bytes, and a third computation element from said second set of computation elements is to perform cyclic redundancy checks for three bytes; and wherein said first stage and said second stage perform cyclic redundancy check computations for a packet, with said first set of computation elements to perform cyclic redundancy check computations for a first set of bytes of input data from said packet, and said second set of computation elements to perform cyclic redundancy check computations for a second set of bytes of input data from said packet.