Patent ID: 7408218

Claim:
A semiconductor device comprising: a plurality of Dynamic Random Access Memory (DRAM) memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines; and a logic circuit, wherein said DRAM memory cell comprises: a capacitor having a first metal electrode, a second metal electrode formed at a first metal wiring layer and a first dielectric film provided between said first and second metal electrodes, and a first Metal Insulator Semiconductor Field Effect Transistor (MISFET), wherein said logic circuit uses a wiring line formed at said first metal wiring layer, wherein said DRAM cell further comprises: a second MISFET, wherein gates of said first MISFET and said second MISFET are connected to a first word line of said plurality of word lines, and a source-drain path of said first MISFET is connected to a first bit line of said plurality of bit lines while a source-drain path of said second MISFET is connected to a second bit line, and wherein said capacitor is connected between the source-drain path of said first MISFET and the source-drain path of said second MISFET.