Patent ID: 7586807

Claim:
A semiconductor memory device, comprising: a memory cell array; an address control circuit block configured to perform an access control to the memory cell array; a data I/O circuit block configured to transmit and receive data to and from the memory cell array; a mode register; a main control circuit changing at least one of the address control circuit block and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to the mode register; a main power supply wiring configured to supply a power to the address control circuit block and the data I/O circuit block; and a pseudo power supply wiring configured to correspond to each of the address control circuit block and the data I/O circuit block, wherein the main control circuit is configured to disconnect the pseudo power supply wiring from the main power supply wiring if a corresponding one of the address control circuit block and the data I/O circuit block is in the standby state, and to connect the pseudo power supply wiring to the main power supply wiring if the corresponding one of the address control circuit block and the data I/O circuit block is in the active state.