Patent ID: 8429496

Claim:
A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells that stores therein coded data to which an error correction code is added and that are arranged at intersections of a plurality of first data lines and a plurality of second data lines; an enabling unit that enables one of the first data lines in the memory cell array that is designated from an external device; a reading unit that reads a plurality of coded data from memory cells on an enabled first data line; a decoding unit that corrects an error in the coded data read by the reading unit using the error correction code and generates decoded data by decoding the coded data; a storage unit that stores therein the decoded data generated by the decoding unit in association with a second data line corresponding to a position of a memory cell from which the decoded data is read; an output unit that outputs, from among the decoded data stored in the storage unit, decoded data associated with a second data line designated from the external device, to the external device; an overwriting unit that overwrites decoded data associated with the enabled first data line and the second data line that are designated from the external device with target data to be written; a coding unit that codes entire decoded data including the decoded data overwritten by the overwriting unit, and generates coded data by adding the error correction code to coded decoded data; and a write-back unit that writes back the coded data generated by the coding unit to the memory cells on the enabled first data line in the memory cell array that is enabled by the enabling unit.