Patent ID: 8000826

Claim:
A method for predicting a manufacturing yield for a die within a semiconductor wafer, the method comprising: receiving a physical layout of the die; partitioning the die into an array of tiles; computing systematic variations for a quality indicative parameter across the array of tiles based on the physical layout of the die, which includes: performing a physical layout extraction across the array of tiles; and determining values for the quality indicative parameter based at least on results of the physical layout extraction; applying a random variation for the quality indicative parameter to each tile in the array of tiles; iteratively placing instances of a window in the die until the die is covered with instances of the window, wherein each iteration includes, selecting a tile from the array of tiles which satisfies a criterion and is not covered by an instance of the window, and placing an instance of the window around the selected tile; computing spatial correlations for the random variations between the selected tiles; and computing the manufacturing yield for the die based at least on the systematic variations, the random variations, and the spatial correlations for the random variations.