Patent ID: 8856602

Claim:
A circuit arrangement, comprising: a plurality of processing cores disposed on a multi-core integrated circuit device, each processing core including a scan chain; and scan logic disposed on the multi-core integrated circuit device and configured to communicate a test pattern to the scan chains of the plurality of processing cores and compare test results output by the scan chains of the plurality of processing cores in response to the test pattern, wherein the scan logic is further configured to identify a faulty processing core among the plurality of processing cores based upon the test result output by the scan chain of the faulty processing core differing from a majority of the test results output by the plurality of processing cores, wherein the plurality of processing cores comprises a plurality of subsets, wherein each subset among the plurality of subsets includes at least three processing cores from among the plurality of processing cores, the scan chains of the at least three processing cores in each subset among the plurality of subsets configured to output test results to the scan logic in parallel with one another and in response to the test pattern, and wherein the scan logic is configured to perform a plurality of comparisons in parallel with one another, wherein each comparison compares the test results output in parallel by the scan chains of the at least three processing cores in a respective subset among the plurality of subsets such that the plurality of comparisons of test results for the processing cores in each of the plurality of subsets are performed in parallel, and wherein the plurality of subsets are tested in parallel.