Patent ID: 7142476

Claim:
A refresh counter circuit generating a row address of a memory device during refresh operation for said memory device which has a normal area for storing data bits, and a parity area for storing parity bits used for detection and correction of error bits among said data bits, comprising; n-stage counter which generates said row address corresponding to an address space of said normal area represented by n bits and to an address space of said parity area represented by m (m<n) bits included in said n bits; an area discriminating circuit which is connected to said n-stage counter and generates an area discriminating signal for discriminating between count operation in said normal area and that in said parity area; a first switching circuit which controls switching between a first connected state in which all stages of said n-stage counter are connected, and a second connected state in which a counter portion corresponding to (n−m) bits which, among said n bits, are not included in said m bits, is disconnected from a path of said n-stage counter to form a m-stage counter; and an automatic reset circuit which generates a reset signal for resetting a state of said discriminating signal so that said count operation in said normal area is discriminated by said discriminating signal, and supplies said reset signal to said area discriminating circuit, when stopping of said refresh operation is instructed under a situation that said first switching circuit controls switching to said second connected state.