Patent ID: 7061040

Claim:
A memory device, comprising: a plurality of isolation structures disposed in a substrate, defining a plurality of active regions in the substrate; a plurality of pairs of word lines, substantially parallel to one another, disposed on and in a direction vertical to the plurality of the isolation structures and the plurality of the active regions, wherein the active regions that are covered by the plurality of pairs of the word lines are defined as a plurality of first channel regions; a plurality of first gates disposed on the plurality of the first channel regions and between the substrate and the plurality of word lines; a plurality of pairs of source lines, substantially parallel to the plurality of pairs of the word lines, each pair of source lines being between each pair of word lines, wherein the plurality of the source lines are disposed in a direction vertical to the plurality of the isolation structures and the plurality of the active regions, and wherein the active regions that are covered by the plurality of pairs of the source lines are defined as a plurality of second channel regions; a plurality of second gates disposed on the plurality of the second channel regions and between the substrate and the plurality of the source lines; a first dielectric layer disposed between the plurality of the active regions and the plurality of the first gates, and between the plurality of the active regions and the plurality of the second gates; a second dielectric layer disposed between the plurality of the word lines and the plurality of the first gates, and between the plurality of the source lines and the plurality of the second gates; a third dielectric layer disposed over the substrate and covering the plurality of the word lines and the plurality of the source lines; a plurality of source/drain regions disposed in the active regions beside the first gates and the second gates; a plurality of source line contacts, through the third dielectric layer, connecting to the source/drain regions that are between each pair of the source lines and electrically connecting to at least one of each pair of the source lines; and a plurality of insulating layers disposed between the plurality of the second gates and the plurality of the source line contacts.