Patent ID: 7925948

Claim:
A system embodied in a hardware system, comprising: a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain, each latch being associated with a corresponding bit position; a don't-care analysis module configured to identify absolute don't-care latches within the DUT; wherein the don't-care analysis module is further configured to assign a weighted value to the corresponding bit positions of the identified absolute don't-care latches; wherein the don't-care analysis module is further configured to identify absolute don't-care bits within a general test pattern; wherein the circuit analysis module is further configured to replace identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, to generate a weighted test pattern; a test vector module configured to generate a test vector based on the weighted test pattern; and an input module configured to apply the test vector to the DUT.