Patent ID: 8253498

Claim:
A phase-locked loop circuit comprising: a phase and frequency comparing section configured to compare a phase of an external reference clock signal with a phase of a comparison clock signal, and generate an error signal corresponding to a result of comparison; an oscillating section configured to generate an internal clock signal of an oscillation frequency corresponding to said error signal; a frequency dividing section configured to generate said comparison clock signal by frequency-dividing said internal clock signal by a predetermined frequency dividing ratio; an oscillator control section configured to generate an oscillation control signal for controlling frequency of said internal clock signal output from said oscillating section on a basis of said error signal; and a frequency divider control section configured to generate a frequency division control signal for controlling a bias current of said frequency dividing section on a basis of said error signal; wherein said oscillator control section and said frequency divider control section are configured such that said oscillation control signal and said frequency division control signal respond having a predetermined relation to each other on a basis of said error signal both in a pull-in process and at a time of locking.