Patent ID: 8093642

Claim:
A semiconductor memory device including a memory cell portion and a peripheral circuit portion, wherein the memory cell portion comprises: a first insulating portion extending in a predetermined direction; a capacitor including a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of the first insulating portion; a plate electrode electrically connected to the upper electrode; and a transistor including a source region and a drain region, one of which is electrically connected to the lower electrode, and the peripheral circuit portion comprises: a plate electrode extending in the same direction as the predetermined direction; a capacitor including an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode, the side surface of the plate electrode being parallel to the predetermined direction; and a transistor including a source region and a drain region, one of which is electrically connected to the lower electrode, wherein the memory cell portion comprises a plurality of arrays including a plurality of the first insulating portions each with the lower electrode and the dielectric film formed on the side surface thereof arranged at regular intervals in a particular direction, wherein the adjacent arrays are located such that the first insulating portions in one of the arrays are staggered with respect to the first insulating portions in the other array, and wherein the upper electrode is formed by filling a conductive material between the first insulating portions each formed with the lower electrode and the dielectric film.