Patent ID: 7339827

Claim:
A non-volatile semiconductor memory device including at least a memory cell group of a plurality of interconnected memory cells, each of said memory cells comprising: a first impurity diffusion region and a second impurity diffusion region both provided on a semiconductor substrate; a channel region sandwiched in between said first and second impurity diffusion regions; a first gate electrode provided over said channel region on a side close to said first impurity diffusion region at least through a charge storage layer; and a second gate electrode provided over said channel region on a side close to said second impurity diffusion region through a gate insulating film; wherein a direction in which plural said first gate electrodes are connected and a direction in which plural said first impurity diffusion regions are connected are the same, each of said memory cells performs an operation of changing a potential of said first gate electrode between a first predetermined level and a second predetermined level higher than said first predetermined level, and in connection with an application of the potential to said first gate electrode and the application of a potential to said first impurity diffusion region, at least one of the potential (Vmg) applied to said first gate electrode and the potential (Vs) applied to said first impurity diffusion region is increased, and before arrival at predetermined levels required of both said potentials, the potential not having been subjected to the potential change out of the potential applied to said first gate electrode and the potential applied to said first impurity diffusion region is increased, thereby obtaining predetermined potential states in the memory cell concerned.