Patent ID: 7415602

Claim:
Apparatus for processing a sequence of instructions, which are stored at different memory addresses in a physical address space, wherein the apparatus is formed to address a logical address space by a predetermined number of logical addresses, and wherein the physical address space is larger than the logical address space, wherein a jump instruction comprises a physical address to address an instruction, which is positioned outside of a physical memory window defined, by the logical address space, and wherein a return jump instruction is provided to terminate a sub-sequence of instructions started by the jump instruction, comprising: a reader for reading in an instruction of the sequence of instructions; an examiner for examining the read instruction, wherein the examiner is formed to determine and store return jump information on a stack, when the examined instruction is a jump instruction, the return jump information referring to the presently current physical memory window, and to retrieve a predetermined amount of stored return jump information from a stack, when the examined instruction is a return jump instruction; and a decoder for decoding the predetermined amount of stored return jump information retrieved from the stack to determine whether the predetermined amount comprises a reference to a physical address outside of a current physical memory window, wherein the decoder is formed to activate the examiner, when the predetermined amount comprises a reference to a physical address outside of a current physical memory window, and wherein the examiner is formed to retrieve another amount of stored return jump information from the stack to identify the physical address outside of a current physical memory window for a return jump, when the examiner is activated by the decoder.