Patent ID: 8122078

Claim:
An arithmetic unit having at least four levels, the arithmetic unit comprising: multiplier circuitry to generate, according to a combined arithmetic operation indicated by an instruction, a partial result comprising either a dot-product of first and second operands, a sum of the first and second operands, or a multiplication-product of the first and second operands, the multiplier circuitry including: a first level including Booth-encoded multipliers configured to generate respective first-level carry/save results; a second level including a first multiplier component operable to receive first-level carry/save results from a first portion of the Booth-encoded multipliers, and a second multiplier component operable to receive first-level carry/save results from a second portion of the Booth-encoded multipliers; summing circuitry to add the partial result to an accumulated value in response to the instruction, the summing circuitry including: a third level including combining circuits configured to combine outputs of the first and second multiplier components with each other and with the accumulated value to generate respective third-level carry/sum results; and a fourth level including a first full propagate adder to receive third-level carry/sum results from a first portion of the combining circuits, and a second full propagate adder to receive third-level carry/save results from a second portion of the combining circuits.