Patent ID: 7606104

Claim:
A semiconductor device comprising: a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell array having a larger capacity than the second memory cell array; a plurality of word lines and a plurality of bit lines connected to said plurality of memory cells; a data program and read control section including a plurality of decoders for read or erasure with respect to a corresponding memory cell among the plurality of memory cells, selecting a corresponding word line and a corresponding bit line among said plurality of word lines and said plurality of bit lines and applying a voltage to said corresponding word line and said corresponding bit line when performing data programming; and a power supply circuit for supplying power to said data program and read control section, wherein when said power supply circuit is to supply power to said second memory cell array, said power supply circuit is to supply power to at least one of said plurality of decoders connected to said first memory cell array and said one of said plurality of decoders connected to said first memory cell array is electrically disconnected from said corresponding word line.