Patent ID: 7236339

Claim:
An integrated circuit having ESD protection, comprising: an output pad for communicating external to the integrated circuit; a resistive element having a first terminal coupled to the output pad and having a second terminal; a first transistor having a first current electrode coupled to the second terminal of the resistive element, a second current electrode coupled to a first voltage supply node, and a first control electrode, wherein the first transistor comprises an output buffer transistor to be protected during an ESD event, wherein during the ESD event the control electrode of the first transistor is coupled to the first voltage supply node via a biasing circuit, and wherein during the ESD event, said biasing circuit applies a voltage to the first control electrode of the first transistor that is approximately equal to a voltage at a circuit node located between the first current electrode of the first transistor and the second terminal of the resistive element, and wherein said ESD circuit is used to provide ESD protection on an integrated circuit, and wherein said biasing circuit is disabled during normal operation of the integrated circuit; a first diode having a first terminal coupled to the second terminal of the resistive element and a second terminal coupled to a second voltage supply node; a second diode having a first terminal coupled to the output pad and a second terminal coupled to the second voltage supply node; a second transistor having a first current electrode coupled to the second voltage supply node, a second current electrode coupled to the first voltage supply node, and a second control electrode; and a trigger circuit coupled to the second control electrode.