Patent ID: 7992122

Claim:
A method of placing and routing, comprising: a) dividing a layout area of an integrated circuit (IC) into an array, said array comprising a plurality of user-defined layout partitions, and said IC comprising at least six metallization layers; b) using a computer or data processing system, routing portions of a plurality of signal paths in one or more upper metallization layers to within a layout partition spacing of at least one of a plurality of circuit blocks in one of said layout partitions, said plurality of signal paths coupling to said plurality of circuit blocks in said layout partitions, and substantially finalizing said upper metallization layer signal path portions, wherein when the IC comprises at least eight metallization layers, the upper metallization layers consist of the four uppermost metallization layers, and when the IC comprises less than eight metallization layers, the upper metallization layers consist of the three uppermost metallization layers; c) extracting actual characteristics of said one or more upper metallization layer signal path portions and determining estimated characteristics for portions of said plurality of signal paths in one or more lower metallization layers, said lower metallization layers consisting of those metallization layers of the IC other than the upper metallization layers, wherein said characteristics comprise one or more members of the group consisting of: resistance, inductance, and capacitance; d) after finalizing said upper metallization layer signal path portions, adjusting said plurality of circuit blocks in response to said actual characteristics of said upper metallization layer signal path portions and said estimated characteristics of said lower metallization layer signal path portions; and e) routing said lower metallization layer signal path portions between said plurality of circuit blocks and said one or more upper metallization layers.