Patent ID: 8054703

Claim:
A memory device comprising: a plurality of externally-accessible input terminals; a memory array, at least a portion of the memory array coupled to receive command, address or data signals from the plurality of externally-accessible input terminals; a plurality of active termination circuits, each coupled to a respective one of the plurality of externally-accessible input terminals, the plurality of active termination circuits each comprising a respective control input receiving a first impedance control signal, each respective active termination circuit configured to establish an input impedance of the respective externally-accessible input terminal based, at least in part, on the first impedance control signal; and a control unit coupled to all of the plurality of active termination circuits, the control unit generating the first impedance control signal, the control unit comprising: first and second control circuits wherein the first control circuit is coupled to a plurality of PMOS transistors connected in parallel and the second control circuit connected to a plurality of NMOS transistors connected in parallel and first and second control circuit comprising first and second voltage elements that establish a deadband range, a reference impedance element and a counter that increments or decrements the number of respective PMOS or NMOS transistors in an ON state if a feedback voltage is outside the deadband range of the respective first and second control circuits whereby the first and second control circuits are operable to select the first impedance control signal suitable to set the input impedance of the plurality of externally-accessible input terminals to a predetermined impedance value relative to the reference impedance element.