Patent ID: 8151030

Claim:
A method for optimizing data transfer between memory modules and at least one memory controller using at least one memory module, the at least one memory module containing firmware and a plurality of double date rate (DDR) integrated circuit chips, each of said integrated circuit chips supporting page mode access, a bank activate command having associated therewith a row access strobe (RAS)-to-column access strobe (CAS) delay, a read command having associated therewith a CAS latency, and a precharge command having associated therewith a precharge latency, the method comprising the step of: setting the firmware for high-speed access including: setting the CAS latency to a CAS latency value that is greater than a minimum CAS latency value supported by said integrated circuit chips at a selected frequency; and setting at least one of the RAS-to-CAS delay and the precharge latency to a RAS-to-CAS delay value and a precharge latency value, respectively, lower than the set CAS latency value to minimize access times of consecutive accesses in which a subsequent access is out-of-page from an immediately previous access; using said precharge command to close a first page where the immediately previous access occurred; and using said bank activate command to open a second page different than the first page to access data within said second page using the read command.