Patent ID: 7626525

Claim:
A cascaded delta-sigma modulator comprising: (a) a first stage converter including a first stage delta-sigma modulator including first and second adders, first and second integrators, a gain circuit, and a quantizer, first and second inputs of the first adder being coupled to an input signal and an output of the quantizer, respectively, an output of the first adder being coupled to an input of the first integrator, an output of the first integrator being coupled to an input of the second integrator and an input of the gain circuit, first and second inputs of the second adder being coupled to an output of the second integrator and an output of the gain circuit, respectively, an output of the second adder being coupled by means of a digital to all analog converter to an input of the quantizer; (b) a second stage converter having a transfer function represented by the expression OUT(z)=z −n IN(z)+G(z)E2(z), where n can be any number, wherein OUT(z) and IN(z) are an output and input, respectively, of the second stage converter in the frequency domain, wherein z −n represents delay, G(z) represents a noise transfer function, and E2(z) represents noise in the second stage converter; (c) a first interstage circuit including a first interstage gain circuit having an input coupled to the output of the second integrator of the first stage delta-sigma modulator, an adder of the first interstage circuit having a first input coupled to the output of the second integrator of the first stage delta-sigma modulator, a second input coupled to an output of the first interstage gain circuit, and an output coupled to an input of a second interstage gain circuit having an output coupled to the input of the second stage converter; and (d) an error cancellation circuit for canceling quantization error, including a first input coupled to the output of the quantizer of the first stage delta-sigma modulator, a second input coupled to the output of the second stage converter, and an output producing an output signal so as to provide a flat transfer function of the cascaded first and second stage converters and the error cancellation circuit in combination despite non-flatness in a transfer function of the first stage second order delta-sigma modulator.