Patent ID: 7930586

Claim:
A controller that interacts with a plurality of N memories, where (a) data to be stored is divided and stored in blocks, (b) the data of a block comprises N-i data strips, i being either 1 or 2, and i redundant-data strips that are associated with said N-i data strips and which, together with the N-i data strips, form a stripe of N strips, (c) the N strips of a stripe are stored in said N memories, respectively, (d) the i redundant-data strips of a stripe being adapted to be used in handling up to i errors that are discovered when an error arises upon reading at least said N-i data strips of a stripe, and (e) the controller includes a module, in response to a request from a user to provide a block of data, for reading N-i data strips from said N memories, the improvement comprising: the module adapted to read, in response to every request for data, said N-i data strips and at least one of said i redundant data strips when reading a block data, even when there is no indication of any error in any of the N-i data strips that are read from said N memories; when processing said N-i read data strips and the at least one of said i redundant data strips indicates an error condition in information contained in one of said N-i read data strips, taking corrective action.