Patent ID: 7663917

Claim:
A memory device comprising, in a single integrated circuit package: a static memory means defining at least first and second nodes communicatively connected with read and/or write data lines, wherein the static memory means comprises a pair of cross-coupled inverters, each of the cross-coupled inverters including first and second transistors that are connected in series, sources of the first transistors of the cross-coupled inverters being connected to each other; and at least one non-volatile memory means associated with said static memory means, and writing data stored therein to said static memory means; said non-volatile memory means comprising a first non-volatile element having a control gate connected to a first node and a source connected to a second node, and a second non-volatile element having a control gate connected to the second node and a source connected to the first node, the drain of each non-volatile element being connected by means of a respective transistor to a supply means; characterized in that said respective transistors are arranged to isolate the drains of the first and second non-volatile elements from the supply means during a program cycle of the memory device, the drains of the first and second non-volatile elements being connected to drains of the respective transistors, the supply means being connected to sources of the respective transistors, the sources of the respective transistors being also connected to the sources of the first transistors of the cross-coupled inverters.