Patent ID: 7817460

Claim:
A semiconductor memory device, comprising: a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a high cell power supply voltage and a low cell power supply voltage with a lower voltage potential than the high cell power supply voltage to the memory cell, wherein the memory cell power supply circuit supplies: a predetermined first power supply voltage supplied as the high cell power supply voltage in a case where the high cell power supply voltage is supplied in a data read cycle and in a case where data is not written to the memory cell to which the high cell power supply voltage is supplied in a write cycle, and a second power supply voltage lower than the first power supply voltage supplied as the high cell power supply voltage in a case where data is written to the memory cell to which the high cell power supply voltage is supplied in a write cycle, further comprising: a leak compensation circuit for compensating a leak voltage of the memory cell, and a peripheral circuit power supply circuit for supplying a power supply voltage to a peripheral circuit of the memory cell, wherein the memory cell power supply circuit further supplies the first power supply voltage, when the power supply voltage to the peripheral circuit is turned off, and the leak compensation circuit always operates, when the power supply voltage to the peripheral circuit is turned off.