Patent ID: 7103816

Claim:
A method for generating test patterns for testing logic products on a test system, comprising: generating an initial sequence of test vectors having a plurality of bits comprising care bits and non-care bits; forming a set of filled test vectors by: for a selected test vector in said initial sequence, filling said non-care bits of said selected test vector with preselected values; and for each subsequent test vector in said initial sequence, filling each of said non-care bits of said subsequent test vector with a value of an associated bit of a preceding test vector immediately preceding said subsequent test vector in said initial sequence; removing at least one redundant test vector from said filled test vectors to form a minimum set of said filled test vectors; compressing said minimum set of said filled test vectors to form a compressed vector data set; transmitting said compressed vector data set to the test system along with restoration information for restoring said at least one redundant test vector; recovering said care bits of said test vectors in said initial sequence from said compressed vector data set in accordance with said restoration information; and loading said care bits recovered from said compressed vector data set into input latches of the test system.