Patent ID: 6953962

Claim:
A nonvolatile memory device having a gate electrode comprising: a non volatile memory cell configured to store data, and having a first gate electrode, first and second diffusion layers, the first gate electrode having a first top surface and a first side surface; a peripheral transistor having a second gate electrode, third and fourth diffusion layers, the second gate electrode having a second top surface and a second side surface, and a width between the third and fourth diffusion layers of the second gate electrode being wider than that between the first and second diffusion layers of the first gate electrode; a first contact layer connected to the second top surface of the second gate electrode of the peripheral transistor; and a silicon nitride layer formed above the first side surface of the first gate electrode in the non volatile memory cell and the second side surface of the second gate electrode in the peripheral transistor, the silicon nitride layer not being contact with the first contact layer, a thickness of the silicon nitride layer that is formed above the first and second side surfaces of the first and second gate electrodes being uniform approximately.