Patent ID: 7643577

Claim:
A carrier and symbol timing apparatus usable with a Vestigial Side Band (VSB) receiver, the apparatus comprising: an analog-to-digital converter (ADC) to receive a VSB-modulated signal and to convert the received VSB-modulated signal to a digital signal using a predetermined sampling clock; a multiplier to multiply the digital signal by a carrier signal of a predetermined frequency and to convert a result of the multiplication to a baseband VSB signal; an error detector to perform a predetermined algorithm on an upper sideband and a lower sideband of the baseband VSB signal, respectively, and to generate upper error information and lower error information based on a difference between phase information of the received VSB-modulated signal and a predetermined reference phase information; a carrier generator to combine the upper error information and the lower error information to generate a frequency offset-corrected carrier; and a sample clock generator to combine the upper error information and the lower error information to generate a symbol clock error-corrected sampling clock.