Patent ID: 8658514

Claim:
A manufacturing process for preparing a semiconductor on insulator structure (SeOI) that exhibits type reduced electrical losses, the substrate successively comprising a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and having a polycrystalline silicon layer interleaved between the support substrate and the oxide layer, which process comprises: oxidizing a donor substrate made of semiconductor material to form an oxide layer on a surface thereof; implanting ions in the donor substrate to form an embrittlement zone therein; bonding the donor and support substrates together with the oxide layer being located therebetween at a bonding interface, the substrate support having a high resistivity that is greater than 500 Ω·cm, and having the polycrystalline silicon layer on its upper face which is bonded to the donor substrate; fracturing the donor substrate at the embrittlement zone to transfer to the support substrate the thin layer of semiconductor material from the donor substrate and form the SeOI structure; and conducting at least one thermal stabilization treatment of the SeOI structure, wherein the thermal stabilization treatment is an annealing treatment conducted over three steps, with the second step requiring heating to a temperature not exceeding 950° C., and for a time of at least 10 minutes, and with the temperature of the second step being less than the temperature of the first and third steps.