Patent ID: 7764090

Claim:
A semiconductor device comprising: a first circuit block including a transmitter circuit; a second circuit block including a receiver circuit; and a wiring pair between blocks for transferring complementary current signals from paired first and second output terminals of the transmitter circuit to paired first and second input terminals of the receiver circuit, wherein the transmitter circuit has output impedance lower than wiring resistance of each wiring of the wiring pair between blocks, the transmitter circuit receives one pair of complementary signals of the first circuit block, converts the pair of complementary signals of the first circuit block to one pair of complementary current signals, and outputs the pair of complementary current signals to the wiring pair between blocks via the first and second output terminals, and the receiver circuit comprises: a current receiver block; and a level shifter circuit, the current receiver block comprising: first and second constant current sources respectively connected to the first and second input terminals; a first NMOS transistor connected at a source thereof to a connection node between the first input terminal and the first constant current source and connected at a drain thereof to a first power supply via first load means; a second NMOS transistor connected at a source thereof to a connection node between the second input terminal and the second constant current source and connected at a drain thereof to the first power supply via second load means; third and fourth output terminals formed of the drains of the first and second NMOS transistors to output voltage signals to inside of the second circuit block; and input impedance lower than wiring resistance of each wiring of the wiring pair between blocks, the level shifter circuit connecting a signal which is the same in phase with the voltage signal at the third output terminal to a gate of the second NMOS transistor and connecting a signal which is the same in phase with the voltage signal at the fourth output terminal to a gate of the first NMOS transistor.