Patent ID: 8598026

Claim:
A method of manufacturing a semiconductor device, comprising: forming a second conductivity type buried layer in a predetermined region on a first conductivity type semiconductor substrate; forming a first conductivity type, epitaxial growth layer on the second conductivity type buried layer and the first conductivity type semiconductor substrate; forming a plurality of trenches in the first conductivity type epitaxial growth layer so as to be arranged side by side in a gate width direction of a transistor to be formed and so that an entire bottom surface of each of the plurality of trenches is entirely surrounded by and disposed in contact with the second conductivity type buried layer; forming a gate insulating film; forming a gate electrode inside and on a top surface of each of the plurality of trenches and on a surface of the first conductivity type epitaxial growth layer adjacent to each of the plurality of trenches via the gate insulating film; and forming a second conductivity type high concentration source diffusion layer on one side of the gate electrode and a second conductivity type high concentration drain diffusion layer on another side of the gate electrode.