Patent ID: 7721024

Claim:
An information handling system, comprising: a plurality of processors coupled to a processor bus; and a memory; wherein an interrupt handling processor of the plurality of processors is assigned to perform processing tasks associated with an interrupt, wherein each of the non-interrupt handling processors is configured to enter an interrupt mode and be serially released from the interrupt mode so as to reduce contention by the non-interrupt handling processors for system resources upon release from the interrupt mode, wherein the non-interrupt handling processors are configured to be serially released from the interrupt mode according to a predetermined time delay following the release of each successive non-interrupt handling processor from the interrupt mode, wherein the predetermined time delay is associated with a time sufficient to permit a processor to exit from an interrupt mode without contention for a processor bus or memory in the computer system, wherein the interrupt handling processor assigned to perform the processing tasks associated with the interrupt initiates the release of the non-interrupt handling processors from the interrupt mode on a timed release basis following the completion by the interrupt handling processor of the processing tasks associated with the interrupt, and wherein the interrupt handling processor assigned to perform the processing tasks associated with the interrupt exits from interrupt mode following the release of the non-interrupt handling processors from interrupt mode.