Patent ID: 7348817

Claim:
A circuit for generating a power on reset signal, comprising: a delay-stage circuit comprising a first charging path limiting device, a first capacitor, a first discharging path limiting device and a common discharging path limiting device, wherein the first capacitor has a first end connected to a ground and a second end, the first charging path limiting device receives a direct current (DC) power voltage and charges the first capacitor at the first end thereof with a first charging current to generate a first control voltage signal having a disactivated level, a second control voltage signal and a third control voltage signal smaller than the second control voltage signal, and the first capacitor has a first discharging current flown only through the first and common discharging path limiting devices; and an output-stage circuit comprising a second charging path limiting device, a second capacitor and a second discharging path limiting device, wherein the second capacitor has a first end and a second end connected to the ground, the second control voltage signal charges the second capacitor at the first end thereof via the second charging path limiting device when the first control voltage signal has an activated level, the second charging path limiting device outputs a transitional power on reset signal directly as the power on reset signal, and the second capacitor has a second discharging current flown only through the second and common discharging path limiting devices.