Patent ID: 8648398

Claim:
A transistor comprising: a first layer having a primary surface; a well region including a channel region of the transistor, wherein the channel region is adjacent to the primary surface; a buried doped region spaced apart from the primary surface and underlying the well region, wherein the buried doped region includes a drain region of the transistor; a gate electrode of the transistor disposed over the primary surface; a trench extending towards the buried doped region, wherein the trench has a sidewall, and the trench is spaced apart from the channel region; a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region, and wherein when viewed from the top, the sidewall doped region is below the well region; and a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region, wherein the conductive structure physically contacts either the buried doped region or a doped region located below the trench.