Patent ID: 8271997

Claim:
An embedded processor, comprising A. a plurality of virtual processing units, each executing one or more processes or threads (which one or more processes or threads are collectively referred to as “threads”), wherein each thread is any of constrained or not constrained to execute on a same processing unit during a life of that thread, B. a plurality of execution units, C. a pipeline control that is in communication coupling with the plurality of processing units and with the plurality of execution units, the pipeline control launching instructions from plural ones of the threads for concurrent execution on plural ones of the execution units, D. an event delivery mechanism that is in communication coupling with the plurality of processing units and that delivers events to respective threads with which those events are associated without execution of instructions by said processing units, where the events include any of (i) loading of cache memory following a cache miss by the thread to which that event is delivered, (ii) filling of a memory location by a thread, other than the thread to which that notification is delivered, in response to a memory instruction issued by the thread to which that notification is delivered, E. wherein a thread to which such an event is delivered processes that event without execution of instructions outside that thread.