Patent ID: 8161443

Claim:
A sensitivity analysis system comprising: a memory device in which an interconnect structure data indicating an interconnect structure included in a semiconductor device is stored, wherein said interconnect structure comprises: a main interconnection formed in an interconnection layer; and a contact structure electrically connected to said main interconnection and extending from said main interconnection toward a semiconductor substrate, wherein a plurality of parameters contribute to parasitic capacitance of said interconnect structure, and variation of each of said plurality of parameters from a design value caused by manufacturing variability is represented within a predetermined range; a parameter setting unit configured to set said variation to a plurality of conditions within said predetermined range; a capacitance calculation unit configured to calculate said parasitic capacitance of said interconnect structure in each of said plurality of conditions; and a sensitivity analysis unit configured to analyze, based on said calculated parasitic capacitance, response of said parasitic capacitance to variation of said each parameter, wherein said sensitivity analysis unit calculates variation of said parasitic capacitance from a design value in each of said plurality of conditions, and said sensitivity analysis unit makes a comparison between the variation of said parasitic capacitance and a predetermined threshold value to analyze degree of contribution of said each parameter to said parasitic capacitance.