Patent ID: 7447110

Claim:
A dual data rate (DDR) output circuit, comprising: a latch unit configured to latch in first data with a first level of a clock signal having a 50% duty cycle; a flip-flop configured to latch-in second data in-synch with a first edge of the clock signal and pass the second data to an output thereof in-synch with a second edge of the clock signal; and a buffer circuit electrically coupled to an output of said latch unit and an output of said flip-flop, said buffer circuit configured to generate the first data at an output terminal of the DDR output circuit in-synch with one edge of the clock signal and further configured to generate the second data at the output terminal in-synch with another edge of the clock signal; wherein the first edge of the clock signal is a high-to-low edge of the clock signal and the second edge of the clock signal is a low-to-high edge of the clock signal; and wherein the one edge of the clock signal is a low-to-high edge of the clock signal and the another edge of the clock signal is a high-to-low edge of the clock signal.