Patent ID: 8115512

Claim:
An integrated circuit, comprising: a logic fabric; and at least one input/output interface coupled to the logic fabric, wherein the at least one input/output interface comprises: a plurality of input/output sites; and an edge detector coupled to the plurality of input/output sites for detecting an edge in an input signal received by the integrated circuit, wherein at least one output of the edge detector is coupled to an input of the logic fabric, wherein the plurality of input/output sites comprises: a first input/output site comprising: a first delay line having an input for receiving the input signal; a first sampling flip flop having an input coupled to an output of the first delay line, wherein an output of the first sampling flip flop is coupled to a first input of the edge detector; and a first input serializer/deserializer having an input coupled to the output of the first sampling flip flop; and a second input/output site comprising: a second delay line having an input for receiving the input signal; and a second sampling flip flop having an input coupled to an output of the second delay line, wherein an output of the second sampling flip flop is coupled to a second input of the edge detector.