Patent ID: 7069352

Claim:
A serial peripheral interface comprising: a memory coupled to at least one data bus and an address bus, said memory for storing data from the at least one data bus associated with a plurality of peripheral devices based upon respective data addresses on the address bus, said memory having a respective transmit data section and a respective receive data section for each peripheral device and also having a configuration command section for storing configuration commands for use in communicating with each of the peripheral devices; a data pointer for pointing to transmit and receive data section addresses; a control register for controlling said data pointer based upon at least one configuration command associated with a selected peripheral device; a data transfer circuit for serially transferring data between said memory and the selected peripheral device based upon the at least one configuration command; and a configuration pointer for pointing to an address at which the at least one configuration command is stored in the configuration command section based upon a data address on the at least one data bus.