Patent ID: 7113423

Claim:
A semiconductor structure comprising: a semiconductor substrate; and a dielectric layer located on said semiconductor substrate, such that an interface region is formed between semiconductor substrate and said dielectric layer; a channel located proximate to said interface region, which channel is capable of carrying a current that varies from a first current value associated with a conducting condition, to a second current value associated with a non-conducting condition, said second current value being substantially less than said first current value; a plurality of carrier trapping sites within said interface region, said carrier trapping sites being configured for trapping carriers that are electrically biased by an electrical control field to move from said channel into said interface region; wherein said trapping sites are characterized by an energy level that is higher than a conduction band of said channel and lower than a conduction band of said dielectric layer and said trappings sites have a concentration and arrangement so that said current in said channel can be varied between said first current value and said second current value by the action of said trapping sites adjusting said current in accordance with a value of said electrical control field; further wherein a ratio of said first current value to said second current value exceeds ten (10) over a temperature range greater than 0° C. and spanning at least 50° C.