Patent ID: 8422315

Claim:
A memory chip comprising: a control unit for receiving an input address signal and at least one command signal, determining and controlling an operation mode of the memory chip according to the input address signal and the at least one command signal, and generating a first control signal according to the determination result; a wait controller, coupled to a wait pad, for receiving the first control signal and changing a state of a wait signal at the wait pad according to the first control signal; and a wait receiver, coupled to the wait pad, for receiving the wait signal and detecting the state of the wait signal to generate a second control signal; wherein when the control unit determines that the memory chip, operating in an active mode, will be changed to operate in an inactive mode according to the input address signal and the at least one command signal, the wait controller changes the state of the wait signal from a de-asserted state to an asserted state according to the first control signal; and wherein when the wait receiver detects that the state of the wait signal has been changed from the de-asserted state to the asserted state, the control unit determines whether the memory chip, operating in the inactive mode, will be changed to operate in the active mode according to the input address signal and the second control signal.