Patent ID: 8344781

Claim:
A power amplification device comprising: a first orthogonal signal generating circuit for generating a first orthogonal signal by performing vector subtraction between a first fundamental signal and a second fundamental signal having the same amplitude and a phase difference δθ (0 degrees<δθ<180 degrees) therebetween, the first fundamental signal and the second fundamental signal being generated based on an input signal having an envelope variation; a second orthogonal signal generating circuit for generating a second orthogonal signal by performing vector addition between the first fundamental signal and the second fundamental signal; a variable gain amplifier circuit for amplifying the first orthogonal signal to generate a first constant envelope vector generation signal and a second constant envelope vector generation signal having phases opposite to each other; a first adder circuit comprising a first terminal to which the second orthogonal signal is input and a second terminal to which the first constant envelope vector generation signal is input, for performing vector addition between signals input from the first terminal and the second terminal to generate a first constant envelope signal; a second adder circuit comprising a third terminal to which the second orthogonal signal is input and a fourth terminal to which the second constant envelope vector generation signal is input, for performing vector addition between signals input from the third terminal and the fourth terminal to generate a second constant envelope signal; an amplitude control circuit for generating, based on an amplitude of the first constant envelope signal and an amplitude of the second constant envelope signal, an amplitude control signal for controlling a gain in the variable gain amplifier circuit; a first amplifier circuit for amplifying the first constant envelope signal to generate a first amplified signal; a second amplifier circuit for amplifying the second constant envelope signal to generate a second amplified signal; and an output adder circuit for performing vector addition between the first amplified signal and the second amplified signal to generate an amplified output signal having an envelope variation.