Patent ID: 7332766

Claim:
A semiconductor integrated circuit device comprising: a first nonvolatile semiconductor memory which includes memory cells arranged in a matrix, each memory cell including a first and a second select transistor and a plurality of first memory cell transistors which have current paths connected in series between the first and second select transistors, each of the first memory cell transistors having a first stacked gate including a first floating gate formed on a semiconductor substrate with a first gate insulating film interposed therebetween and a first control gate formed on the first floating gate with a first inter-gate insulating film interposed therebetween; and a second nonvolatile semiconductor memory which includes memory cells arranged in a matrix, each memory cell including a third select transistor and a second memory cell transistor which has a current path connected to a current path of the third transistor in series, the second memory cell transistors having a second stacked gate including a second floating gate formed on the semiconductor substrate with a second gate insulating film interposed therebetween and a second control gate formed on the second floating gate with a second inter-gate insulating film interposed therebetween, the first and second gate insulating films having the same film thickness, the first and second floating gates having the same film thickness, the first and second inter-gate insulating films having the same film thickness, and the first and second control gates having the same film thickness.