Patent ID: 7394638

Claim:
A system for electrostatic discharge (ESD) protection of a semiconductor integrated circuit having first and second supply voltage rails, the system comprising: a clamp transistor coupled to the first and second supply voltage rails; and first and second ESD-sensing circuits, wherein each ESD-sensing circuit, responsive to an ESD potential on a first power terminal with respect to a second power terminal, is operable to turn on the clamp transistor to create a low-impedance path between the first and second supply voltage rails, wherein: the first and second power terminals of the first ESD-sensing circuit are electrically connected, respectively, to the first and second supply voltage rails, the first and second power terminals of the second ESD-sensing circuit are electrically connected, respectively, to the first and second supply voltage rails, the first ESD-sensing circuit, responsive to an ESD potential on its first power terminal with respect to its second power terminal, is capable of improving an ‘on-time’ of the clamping transistor by inhibiting the second ESD-sensing circuit, and the second ESD-sensing circuit, responsive to an ESD potential on its second power terminal with respect to its first power terminal, is capable of improving the “on-time’ of the clamping transistor by inhibiting the first ESD-sensing circuit.