Patent ID: 8559227

Claim:
A nonvolatile memory device comprising: a plurality of global word lines; a plurality of first local word lines corresponding to a plurality of memory cells included in a first cell block; a plurality of second local word lines corresponding to a plurality of memory cells included in a second cell block; a plurality of first transistors configured to be turned on to transfer voltages of the global word lines to the first local word lines when the first cell block is selected among the first and second cell blocks; a plurality of second transistors configured to be turned on to transfer the voltages of the global word lines to the second local word lines when the second cell block is selected among the first and second cell blocks; and a voltage control unit configured to charge a bulk region of the plurality of transistors with a second negative voltage before a first negative voltage is applied to a global word line of the plurality of global word lines, wherein the voltage control unit is configured to, when the first negative voltage is applied to the global word line of the plurality of global word lines, apply a third negative voltage to gates of the first or second transistors of the unselected one of the first and second cell blocks, respectively, and turn off the transistors applied with the third negative voltage.