Patent ID: 7778812

Claim:
A method to test a hardware device model comprising: using a processor for: forming a first mask comprising a bit pattern in a first computer memory location; writing data to a location in a node, the node comprising an address in the computer memory, a plurality of data locations, a data valid field associated with each data location, and a data verified field associated with each data location; marking valid data items as a function of the data written to the node data locations by setting a bit value in the data valid field; reading a portion of said written data; marking verified data items as a function of the data read from the node data locations by setting a bit value in the data verified field; identifying valid data items that have not been verified by examining the bit value in the data valid field and the bit value in the data verified field, thereby quantifying an amount of newly verifiable data items; and storing the quantification of the amount of newly verifiable data items in a storage location; wherein the first mask is used to determine which locations to write to or read from; and wherein the locations are determined by: determining numeric bit positions of the bit pattern in the first mask that have value set; adding said address to the numeric bit positions of the bit pattern in the first mask that have value set.