Patent ID: 7529995

Claim:
An integrated circuit comprising: A. functional circuitry; B. a serial data input, a serial data output, a clock input, and a mode select input; C. an access port that includes a first state machine connected with the clock input and the mode select input and having first control outputs indicating a CAPTURE-DR state, a SHIFT-DR state, a PAUSE-DR state, and an UPDATE-DR state; D. an instruction register connected with the serial data input and the first control outputs and selectively coupled with the serial data output, the instruction register having instruction control outputs; E. a data register connected with the serial data input and selectively coupled with the serial data output, the data register being coupled with the functional circuitry and having control inputs connected with the instruction control outputs; F. control circuitry connected with the serial data input, the first control outputs, and the instruction control outputs, and selectively coupled with the serial data output, the control circuitry including: i. multiplexer circuitry having first inputs connected with the first control outputs, second inputs, a control input connected with the instruction control inputs, and outputs connected with the control inputs of the data register; ii. shift register sections connected with the serial data input; iii. a second state machine having control inputs connected with the first control outputs and the instruction control outputs, having third control outputs connected with the second inputs of the multiplexer circuitry, and having program inputs coupled with the shift register sections, the third control outputs being active when the second state machine receives a first control signal indicating that the first state machine is in a SHIFT-DR state.