Patent ID: 7015149

Claim:
A simplified dual damascene process, comprising: providing a semiconductor substrate with MOS devices having a first metal layer, an etch stop layer, and a dielectric layer in sequence formed thereon; forming a first patterned photoresist layer on the dielectric layer, forming a via by using the first patterned photoresist layer as a mask, and removing the first patterned photoresist layer; forming an organic layer on the dielectric layer to fill the via; forming a second patterned photoresist layer on the organic layer to define a size of a trench by etching in the organic layer and the dielectric layer, the trench being larger than the via, using the second patterned photoresist layer as a mask, over-etching an exposed organic layer with a higher selective ratio of organic versus dielectric layer until the surface of the organic layer is lower than the dielectric layer; performing a trench etching in the dielectric layer using the second patterned photoresist layer as a mask until the surface of the dielectric layer is lower than the organic layer; and removing the second patterned photoresist layer and the remaining organic layer to form a dual damascene structure profile.