Patent ID: 7133314

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of blocks, each of the blocks including memory cells arranged in rows and columns; a block selector configured to select one of the blocks of the memory cell array; wherein each of the blocks includes a plurality of word lines to be applied voltages which a plurality of drive lines receive, the plurality of word lines are classified into an arbitrary word line determined arbitrarily, secondary adjacent word lines located adjacent to both word lines adjacent to the arbitrary word line, and residual word lines other than the arbitrary word line and the secondary adjacent word lines; and wherein the block selector controls a plurality of transfer transistors by outputs, the plurality of transfer transistors having current paths thereof connected between the drive lines and the word lines of each block, among the plurality of transfer transistors, transfer transistors for the residual word lines are arranged at both adjacent locations and an opposite location around a transfer transistor for the arbitrary word lines, wherein applying a first voltage to the arbitrary word line, the residual word lines are applied a second voltage smaller than the first voltage, and the secondary adjacent word lines are applied a third voltage smaller than the second voltage.