Patent ID: 7570664

Claim:
A synchronization correction circuit comprising: a synchronization signal generator for detecting a synchronization word contained in a received packet to generate a packet synchronization signal synchronized with the received packet; a period error detector for measuring a period of the packet synchronization signal generated in said synchronization signal generator to calculate a period error with respect to a reference interval; a cumulative error counter for cumulating the period error as calculated by said period error detector every plural periods of the packet synchronization signal to calculate a cumulative period error; a correction value calculator for calculating a period correction value per one clock signal and a number of clock signals to be corrected for a clock period so that a sum of the period correction values per one clock signal will be coincident with the cumulative period error; and a clock signal generator for generating clock signals of a predetermined reference period when the period correction value is zero, and for generating, when the period correction value is different than zero, a number calculated in said correction value calculator of clock signals, a period of which has been corrected based on the period correction value.