Patent ID: 7786758

Claim:
A tristate buffer circuit operable to be switched into a high impedance state in response to a first configuration signal (CSI) comprising: a tristate buffer (TBUF) having an input, an output and a tristate control input, said tristate buffer (TBUF) outputting a signal (BUF OUT) corresponding to said signal on said input in a normal mode and outputting a high impedance signal in a high impedance mode as controlled by said tristate control input; a delay stage (DEL) having a input receiving an input signal (BUF IN) and an output connected to said input of said tristate buffer (TBUF) for delaying said input signal (BUF IN); a gating stage (GS) having inputs receiving said input signal (BUF IN), a delayed signal (BUF IN DEL, BUF OUT) by said delay stage (DEL) and an asynchronous tristate signal (3ST) indicating that the buffer (TBUF) is to be switched into the high impedance state, and an output connected to said tristate control input of said tristate buffer (TBUF) providing a configuration signal (CSI), said gating stage (GS) operable to set said configuration signal (CSI) to select said high impedance mode only when said tristate signal (3ST) is set and said input signal (BUF IN) and said delayed signal (BUF IN DEL, BUF OUT) have the same logic levels indicating that no signal transition of said input signal (BUF IN) propagates within said delay stage (DEL); wherein said gating stage (GS) includes a latch, which is only set if said tristate signal (3ST) is set and said input signal (BUF IN) and said output signal (BUF OUT) have the same logic levels.