Patent ID: 7652501

Claim:
A Programmable Logic Device (PLD), comprising: a plurality of multi-state drivers, each multi-state driver configured to generate a first signal having a positive polarity and a second signal having a negative polarity, the first signal being substantially simultaneous to the second signal; a routing line configured to select at least one of the first and second signals of at least one of the plurality of multi-state drivers; a plurality of switches, at least one of the plurality of switches configured to couple the at least one of the first and second signals with the routing line; a non-volatile register, the non-volatile register configured to control the at least one of the plurality of switches; a memory element including a first end and a second end; and register logic connected with the first end and the second end of the memory element, the register logic being configured to be positioned at a different vertical layer than the memory element.