Patent ID: 7157985

Claim:
A PLL modulation circuit comprising: a PLL section having: a voltage controlled oscillator; a frequency divider that frequency divides an output signal of the voltage controlled oscillator; a phase comparator that compares an output signal of the frequency divider with a reference signal; a loop filter that equalizes an output of the phase comparator; and an adder that adds an output of the loop filter to a second modulation input signal and sends a result of adding to the voltage controlled oscillator; a first modulation signal generator that, based on a modulation signal inputted, generates a first modulation input signal to input to the frequency divider in the PLL section; a second modulation signal generator that, based on said modulation signal inputted, generates the second modulation input signal to input to the adder in the PLL section; a first calibration signal generator that generates a first calibration signal within a PLL bandwidth to input to the frequency divider in the PLL section; a second calibration signal generator that generates a second calibration signal outside the PLL bandwidth to input to the adder in the PLL section; a demodulator that demodulates an output signal of the voltage controlled oscillator upon adjustment of a modulation level and a time gap between the first calibration signal and the second calibration signal; a low pass filter that blocks a high frequency component of the demodulation signal demodulated in the demodulator; a high pass filter that blocks a low frequency component of the demodulation signal a modulation signal control circuit that compares an amplitude and a phase of an output of the low pass filter and an output of the high pass filter and generates control information; and a modulation signal adjustor that adjusts the first modulation input signal and the second modulation input signal in accordance with the control information.