Patent ID: 6944054

Claim:
A non-volatile bit addressable memory array comprising a plurality of memory cells, each cell having: a first control circuit having a transistor and receiving a bit line signal and word line signal, the first control circuit communicates with a select node based on the bit line signal and word line signal; a second control circuit having a transistor and receiving the bit line signal and a release line signal, the second control circuit communicates with a restore node based on the bit line signal and the release line signal; and an electromechanically deflectable three terminal switch comprising: a first terminal connected to the select node; a second terminal connected to the restore node; and a third terminal connected to a reference signal and a deflectable nanotube article, the nanotube article being electromechanically deflectable to contact the select node when a predetermined voltage difference is applied between the first and third terminals and being releasable from such contact when a predetermined voltage difference is applied between the second and third terminals.