Patent ID: 7221028

Claim:
A high voltage transistor comprising: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region which have the channel region interposed therebetween and are formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; a second metal silicide layer which is formed on the high concentration drain region; and asymmetric first and second spacers each having first sides abutting sidewalls of the gate top portion and the gate bottom portion of the gate electrode, wherein the first spacer has a second side that is positioned between the low concentration source region and the first metal silicide layer and the second spacer has a second side that is positioned between the low concentration drain region and the second metal silicide layer.