Patent ID: 7436217

Claim:
Apparatus, comprising: a first device comprising: (a) a first clock input port for receiving a first clock input signal; (b) a first clock output port at which a first clock output signal is provided; and (c) a first clock circuit coupled between the first clock input port and the first clock output port for processing the first clock input signal to provide the first clock output signal having a period that is substantially equal to a period of the first clock input signal and a duty cycle that is independent of a duty cycle of the first clock input signal; and a second device serially coupled to the first device, the second device comprising: (a) a second clock input port the first clock output port of the first device for receiving the first clock output signal as a second clock input signal; (b) a second clock output port at which a second clock output signal is provided for coupling to at least one other device; and (c) a second clock circuit coupled between the second clock input port and the second clock output port for processing the second clock input signal to provide the second clock output signal having a period that is substantially equal to a period of the second clock input signal and a duty cycle that is independent of a duty cycle of the second clock input signal.