Patent ID: 7495976

Claim:
An integrated circuit comprising: at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of memory cells; a plurality of bit lines, each of said plurality of bit lines being coupled to a respective column of said memory cells; a plurality of word lines carrying respective word line signals, each of said plurality of word lines being coupled to a respective row of said memory cells to control coupling of said respective row of memory cells to said plurality of bit lines so as to provide access to data bits stored therein; an address decoder responsive to input memory addresses to generate said word line signals; and repair control circuitry responsive to a repair signal to control said address decoder during a memory access operation to an memory input address such that: in a normal mode, a single row of memory cells is selected for access by one word line signal on one word line such that for each column of memory cells one memory cell is coupled to a corresponding bit line of said plurality of bit lines to provide access to a data bit as stored within said one memory cell; in a repair mode, a plurality of rows of memory cells are selected for access by a plurality of word line signals on a plurality of word lines such that for each column of memory cells a plurality of memory cells are coupled to said corresponding bit line of said plurality of bit lines to provide access to said data bit as stored within said plurality of memory cells; and a plurality of arrays of memory cells, said repair control circuitry independently controlling different ones of said plurality of arrays of memory cells to operate in said normal mode or said repair mode.