Patent ID: 8601420

Claim:
A method for static timing analysis of integrated circuit designs, the method comprising: reading a netlist of an integrated circuit design including a signal path from an input terminal to an output terminal; constructing a first stage of the signal path between the input and output terminals, the first stage including a first gate model to model one or more logic gates of a first cell and a first interconnect model to model interconnect and noise sources in the first stage; forming a first equivalent waveform model in the first stage of the signal path in response to a receiving gate in the first stage, the first equivalent waveform model adapted to receive a noisy input waveform and generate a smooth equivalent waveform in response to the noisy input waveform; calculating first noisy waveforms in a first input signal coupled into the first equivalent waveform model; generating a first smooth equivalent waveform in response to the first calculated noisy waveforms and the first equivalent waveform model; and calculating first timing information from the first smooth equivalent waveform for the first stage of the signal path; wherein one or more of the reading, constructing, forming, calculating, and generating are performed with a processor.