Patent ID: 7185178

Claim:
A processor comprising: a plurality of instruction buffers, each of the plurality of instruction buffers corresponding to a respective thread of a plurality of threads; and a fetch generator circuit configured to generate at least a first fetch request to fetch at least one instruction from a first thread of the plurality of threads for storage in a first instruction buffer of the plurality of instruction buffers corresponding to the first thread, the fetch generator circuit configured to speculatively generate the first fetch request responsive to: (i) the fetch generator circuit detecting at least one condition for each thread of the plurality of threads that is defined to inhibit the thread from being fetched; and (ii) the first thread being selectable to be fetched except for the condition that the first instruction buffer of the plurality of instruction buffers is unable, in a clock cycle in which the first fetch request is generated, to store at least one instruction to be fetched in response to the first fetch request, and wherein the fetch generator circuit is configured to maintain a plurality of fetch program counters (PCs), each of the plurality of fetch PCs corresponding to a respective thread of the plurality of threads, and wherein the first fetch request comprises a first fetch PC of the plurality of fetch PCs that corresponds to the first thread.