Patent ID: 8785980

Claim:
A semiconductor memory device comprising a memory cell array which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that a height of an upper surface of the first wiring line in a memory cell array region where the memory cell array is formed is higher than a height in a peripheral region around the memory cell array region, the first wiring line includes a main wiring line layer formed over the memory cell array region and the peripheral region, and a lower wiring line layer formed in the peripheral region on a lower surface of the main wiring line layer, a height of an upper surface of the main wiring line layer in the peripheral region is lower than a height in the memory cell array region, a dummy cell is provided on a portion of the first wiring line immediately above an end portion of the lower wiring line layer close to the memory cell array region, and the step is formed in the first wiring line so that the a height of an upper surface of the first wiring line in the region from the end portion of the dummy cell toward the peripheral region is lower than the height in the memory cell array region.