Patent ID: 7485525

Claim:
A method of manufacturing a memory cell having multiple ports for permitting read and write access to a data bit, comprising: a) etching a plurality of trenches into a substrate including a single-crystal semiconductor region; b) forming a plurality of trench capacitors having capacitor dielectric layers extending along walls of said plurality of trenches, said plurality of trench capacitors having first capacitor plates and second capacitor plates opposite said capacitor dielectric layers from said first capacitor plates, said first capacitor plates being conductively tied together through buried strap outdiffussions (“BSODs”) extending outwardly from said trench capacitors into said substrate and said second capacitor plates are conductively tied together, such that said first capacitor plates are adapted to receive a same variable voltage and said second capacitor plates are adapted to receive a same fixed voltage; c) forming a plurality of access transistors, each access transistor having a drain region conductively connected to one of said plurality of trench capacitors; and d) forming a plurality of conductors operable to carry a plurality of control signals to operate said plurality of access transistors and to carry a plurality of data bit signals each representing a state of a data bit for a purpose of at least one of reading said data bit when said data bit is stored in said memory cell or writing said data bit when said data bit is to be stored to said memory cell, wherein said BSODs are overlapped and conductively connected and said plurality of access transistors are conductively connected to said plurality of trench capacitors through said BSODs.