Patent ID: 7305599

Claim:
An integrated circuit configured for testing signal propagation delay, comprising: a ring oscillator having a first sequential element, a second sequential element, and a shift register circuit, the shift register circuit coupled in series between the first sequential element and the second sequential element, the shift register circuit including at least one shift register and combinational logic coupled to the at least one shift register; the first sequential element and the second sequential element being part of another shift register circuit in which the shift register circuit is inserted; an initial sequential element of the other shift register circuit, the initial sequential element preceding the first sequential element; the at least one shift register configured to store a test data pattern of alternating logic ones and zeros; the combinational logic coupled to receive a data signal from the first sequential element of the ring oscillator and coupled to receive a shift output signal from the at least one shift register, the combinational logic configured to provide an exclusive OR or an exclusive NOR function; the at least one shift register coupled to receive output from the combinational logic to clock the at least one shift register; the at least one shift register coupled to receive the shift output signal from the at least one shift register as a fed back shift input signal; and the second sequential element coupled to receive the shift output signal to clock the second sequential element.