Patent ID: 8252489

Claim:
A method comprising: retrieving a layout of an integrated circuit design from a non-transitory computer-readable storage medium; generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions comprising patterns separated to a first mask and a second mask of a double patterning mask set; determining a maximum shift between the first and the second masks, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer; and for each of the plurality of double patterning decompositions, simulating a worst-case performance value, wherein the step of simulating is performed using mask shifts within a range defined by the maximum shift, and wherein the step of simulating comprises: calculating a capacitance of patterns from a spacing between the patterns, wherein the step of calculating is performed using a high-order equation or a piecewise equation, and wherein the high-order equation represents capacitances of the patterns as a high-order function of the spacings, and wherein the piecewise equation represents the capacitances as a piecewise function of the spacings.