Patent ID: 7557612

Claim:
A hierarchical interconnect architecture for a field programmable gate array integrated circuit including a plurality of logic function blocks, the architecture including: a third level including: a plurality of third groups of functional logic blocks at the third level, wherein: each third group spans a third length and a third width, and a set of third routing resources that includes: a plurality of freeway routing channels associated with each third group of functional logic blocks, each freeway routing channel associated with one of the third groups including a plurality of interconnect conductors configured to make programmable connections to functional logic blocks in other ones of the third groups; and a second level including: a plurality of second groups of functional logic blocks at the second level, wherein: each second group spanning a second length and a second width, and the number of functional logic blocks in the third groups is greater than the number of functional logic blocks in the second groups, a set of second routing resources that includes: a plurality of expressway routing channels including a plurality of interconnect conductors configured to make programmable connections between different ones of the functional logic blocks in the second group and to interconnect conductors in the set of third routing resources; and a first level including: a plurality of first groups of functional logic blocks at the first level, wherein: each first group spans a first length and a first width, the number of functional logic blocks in the second groups is greater than the number of functional logic blocks in the first groups, each of the plurality of groups of functional blocks comprises a plurality of clusters, each cluster comprising at least one LUT and at least one DFF; and a set of first routing resources; a block connect routing channel including a plurality of interconnect conductors configured to make programmable connections between different ones of the functional logic blocks in the second group and to interconnect conductors in the set of second routing resources; a local mesh routing channel including a plurality of interconnect conductors configured to make programmable connections between adjacent ones of the functional logic blocks in a single one of the first groups of the functional logic blocks; a direct connect routing channel including a plurality of interconnect conductors configured to make programmable connections between selected elements of adjacent ones of the functional logic blocks in a single one of the first groups of the functional logic blocks.