Patent ID: 8433534

Claim:
An electronic device, comprising: at least one processor operable to execute program instructions; and a storage system operable to store the program instructions executable by the at least one processor, for performing steps of: setting a global timer and a series of feature test timers, assigning a total test time for the global timer, and arranging the feature test timers in a sequence, wherein the total test time is a mean time between failure (MTBF) and each of the feature test timers corresponds to one or more features of the electronic device; activating the global timer; activating the feature test timers one by one according to the sequence, testing the one or more features of the electronic device corresponding to each of the feature test timers, and obtaining a feature test result in each testing process, until the global timer times out; and obtaining a total test result by integrating all the feature test results, and outputting the total test result to an output device of the electronic device.