Patent ID: 8045357

Claim:
A semiconductor memory device comprising: a memory cell array configured by two-dimensionally arranging destructive read-out type memory cells that stored data is degraded by data read; a decoder configured to select a memory cell in the memory cell array; a sense amplifier configured to detect the data stored in the selected memory cell; and a read and write controller configured to control a read operation for reading data externally from the memory cell and a write operation for writing external data in the memory cell, wherein the read and write controller outputs a logical value of a write enable signal at the start of the read operation in a first period and makes the write enable signal invalid after the read operation starts during the first period, on the basis of the write enable signal and a restore signal keeping an activated state during the first period, the write enable signal being a signal allowing the write operation, the first period being a period from when the read operation starts to when a restore operation for writing the data back to the memory cell is completed.