Patent ID: 7505318

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cell units in which a plurality of electrically rewritable memory cells are connected in series; a plurality of word lines respectively connected to control gates of said plurality of electrically rewritable memory cells; a plurality of bit lines each being connected to one end of said plurality of memory cell units; and a plurality of source lines each being connected to another end of said plurality of memory cell units, wherein said plurality of electrically rewritable memory cells which are connected to each of said plurality of word lines constitute a unit called a page, wherein said page has a flag cell area, and when said flag cell area is written with data, in said plurality of electrically rewritable memory cells within said flag cell area, every other memory cell among said plurality of electrically rewritable memory cells which are arranged in a bit line direction are written with said data, and also every other memory cell among said plurality of electrically rewritable memory cells which are arranged in a word line direction are written with said data.