Patent ID: 6992343

Claim:
A semiconductor memory device comprising: a plurality of folded-type bit-line pairs arranged in parallel to each other; a plurality of word lines orthogonal to said plurality of bit-line pairs; and dynamic memory cells each composed of one transistor and one capacitor and arranged in matrix at positions corresponding to the intersections between said plurality of bit-line pairs and said plurality of word lines, wherein one electrode of said capacitor is connected to a common electrode together with each one electrode of other plurality of capacitors arranged in matrix, and the other electrode of said capacitor is connected to one side of a source-drain path of said transistor, the other side of the source-drain path of said transistor is connected to said bit-line pair, and a gate electrode of said transistor is connected to said word lines, wherein a circuit for performing writing of memory information to said memory cell, or readout of memory information from said memory cell, or refresh of memory information of said memory cell in response to said plurality of bit-line pairs is connected, and wherein when a half pitch of said word line is defined as F, the pitch of each bit line of said bit-line pairs is larger than 2F and smaller than 4F.