Patent ID: 6886145

Claim:
A method for verifying a testbench for an integrated circuit (IC) design, the IC design including a chain of scan circuits having a memory characteristic, said method comprising: dividing the chain of scan circuits and creating a plurality of partitions, each partition including at least one logic cone output, each scan circuit belonging to one of the partition as a logic cone output; generating a partitioned netlist for each partition from a full netlist for the IC design, the partitioned netlist including at least one logic cone, the logic cone extending from the logic cone output to at least one logic cone input; generating a partitioned testbench for each partition from the full testbench based on the partitioned netlists; and performing verification for the testbench by simulating the partitioned testbenches on the corresponding partitioned netlists; wherein said generating the partitioned netlist includes: creating a logic cone for each partition, including: defining the logic cone with an output signal thereof; defining a specific type of logic gates providing logic cone inputs; determining a first logic gate for which the output signal is an output; tracing back an input signal of the first logic gate to a second logic gate driving the input signal; recursively tracing back an input signal of the second logic gate until the input signal is a primary input to the IC design or a third logic gate driving the input signal to the second logic gate is of the specific type; and collecting all of the logic gates and signals traced back from the first logic gate to the primary input or to the logic gate of the specific type.