Patent ID: 7856609

Claim:
A computer program product, comprising: a computer readable storage medium; and computer executable instructions, stored by the computer readable storage medium, for generating a constraint for use in the verification of an integrated circuit design, said computer executable instructions including: instructions for identifying a target in a netlist representation (N) of the integrated circuit design, wherein N includes sequential gates, random gates, and combinational logic; instructions for creating an over-approximate abstraction (N′) of the netlist representation (N) by modifying the netlist representation (N) through replacement of a sequential gate in N with a random gate; instructions for computing a state space S′ of N′, said instructions for computing including instructions for enumerating the states of N′ from which the identified target may be asserted; instructions for deriving a constraint space C′ from the state space S′, wherein C′ is the complement of S′; and instructions for synthesizing a constraint from constraint space C′ and applying said constraint to a constraint node appended to said integrated circuit design to limit a set of one or more states for which the target is asserted during verification.