Patent ID: 8089108

Claim:
A semiconductor memory cell, comprising: an Independently-Double-Gated (IDG) field effect transistor (FET) configured to store data in a data storage capacitance, wherein the IDG FET includes a substrate, a substrate dielectric disposed on the substrate, a bottom gate disposed on the substrate dielectric, a source disposed above the substrate dielectric and having a source extension extending from a main body of the source, a drain disposed above the substrate dielectric and having a drain extension extending from a main body of the drain, a channel confined by being coupled between the source extension and the drain extension, the channel creating a junction contact with the bottom gate to form a JFET, a top gate disposed above the channel, a first local interconnect coupled to the top gate, a first insulating spacer disposed between the top gate and the source and proximate to the source extension, and a second insulating spacer disposed between the top gate and the drain and proximate to the drain extension; and a first control signal line coupled to the top gate, and a capacitor coupled between the source of the IDG FET and a common plate, wherein the drain of the IDG FET is coupled to a data signal line, and wherein the data storage capacitance is the capacitor, whereby a One-Transistor, One-Capacitor (1T-1C) DRAM is formed.