Patent ID: 7320100

Claim:
An information-processing apparatus comprising: a first memory having a plurality of addressed locations, each location holding a plurality of bits; and a first control circuit, the first control circuit including: a first memory controller, the first memory controller including: an address-range detector that specifies a range spanning an incrementally variable-length subset of the plurality of addressed locations, wherein the detector allows a plurality of non-power-of-two subset sizes for the range, and that, for each memory request, determines whether an address of the memory request is within the specified range; and a read-data bit-swap circuit coupled to receive fetched data including a plurality of data bits and one or more spare bits from the first memory and operatively coupled to the address-range detector, and based on an indication from the address-range detector as to whether a memory request address is within the range, to swap one or more, but fewer than all, of the bits of the data, such that one or more spare bits are used for data bits in the read data, and a corresponding number of data bits are not used in the read data.