Patent ID: 7260797

Claim:
A method for estimating a parasitic capacitance, the method comprising: receiving an integrated circuit design and a set of Green's functions; and choosing a conductor within the integrated circuit; constructing a Gaussian surface that contains the conductor, but does not contain any other conductor; selecting a set of locations on the Gaussian surface; and estimating the electric field at each location in the set of locations, wherein estimating the electric field at a location involves: constructing a first closed surface that encloses the location, wherein the first closed surface can touch a conductor, but cannot contain a conductor, and wherein the dielectric composition of the first closed surface corresponds to a dielectric configuration for which an electric field Green's function is available in the pre-computed set of Green's functions; estimating the electric potential at one or more locations on the first closed surface; estimating the electric field at each location in the set of locations from the estimated electric potential; and estimating the parasitic capacitance from the estimated electric field at each location in the set of locations.