Patent ID: 7539902

Claim:
A method of performing computer system operations, comprising: allocating memory; binding a controller thread to a first microprocessor core; binding a target thread to a second microprocessor core; filling the allocated memory with data; synchronizing the controller thread and the target thread to execute a sequence of read operations and write operations on a target instruction cache; and reporting errors generated as a result of performing the read operations and write operations, wherein the read operations and write operations on the target instruction cache comprise: reading a value and writing the value read to a memory location within the allocated memory corresponding to an instruction cache line; setting a value of an index to the memory location within the allocated memory corresponding to the instruction cache line; enabling the target instruction cache to execute the instruction cache line corresponding to the memory location within the allocated memory corresponding to the instruction cache line identified by the value of the index; incrementing the index to correspond to a second memory location within the allocated memory corresponding to the instruction cache line; writing a data background pattern to a memory location within the allocated memory corresponding to the instruction cache line; setting the value of the index to the memory location within the allocated memory corresponding to the instruction cache line; enabling the target instruction cache to execute the instruction cache line corresponding to the memory location within the allocated memory corresponding to the instruction cache line identified by the index; and incrementing the index to correspond to another memory location within the allocated memory corresponding to an instruction cache line.