Patent ID: 8522183

Claim:
A method for performing static timing analysis of a design of an integrated circuit, the method comprising: determining, by a computer, aging factors for arcs in standard cells in a standard cell library comprising a plurality of cells, wherein an arc represents a path from a specified input of a specified cell to a specified output of the specified cell; determining state profiles for cell instances in the design, wherein a cell instance represents an instantiation of a standard cell within the design and wherein a state profile for the cell instance indicates instance-specific probabilities for possible states that the standard cell may occupy; determining, from the state profiles and the aging factors, an instance-specific aging factor for each of the cell instances; converting the instance-specific aging factors into instance-specific aging effect timing values wherein converting the instance-specific aging factors into instance-specific aging effect timing values includes interpolating at least one instance-specific aging effect timing value from a predetermined aging effect timing value; and based on the instance-specific aging effect timing values, generating instance-specific static timing models, suitable for use in performing static timing analysis, for each of the cell instances.