Patent ID: 7733687

Claim:
A memory circuit comprising: a bit line; a first word line; a second word line adjacent the first word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; an additional WAK device coupled between the first and the second power supply lines; a first static random access memory (SRAM) cell connected to the bit line, the first word line, and the second power supply line; and a second SRAM cell connected to the bit line, the second word line, and the second power supply line.