Patent ID: 7145817

Claim:
A memory system, comprising: a memory array having memory locations arranged in addressable rows and columns, the memory array partitioned into a plurality of blocks of memory; a corresponding plurality of sets of programmable elements, each set of programmable elements operable to store memory addresses of defective memory locations of a respective block of memory; a redundant memory having memory locations to which memory addresses of defective memory locations of the memory array are mapped; and an address decoder coupled to the memory array, the redundant memory, and the plurality of sets of programmable elements, the address decoder operable to compare a first portion of a memory address to the memory addresses stored by a selected set of programmable elements, the set of programmable elements selected in accordance with a second portion of the memory address, the address decoder further operable to access memory locations of the redundant memory in response to the memory address matching a stored memory address in the selected sets of programmable elements.