Patent ID: 8898503

Claim:
A method of transferring data from a first clock domain to a second clock domain, the method comprising: writing the data from the first clock domain into a first buffer for a data transfer from the first clock domain to the second clock domain and into a second buffer for the data transfer from the first clock domain to the second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency not exceeding the clock frequency of the second clock domain, the first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and the first clock domain and the second clock domain operate in an asynchronous mode when the variable frequency is lower than the fixed frequency, wherein the first buffer has a first time delay for the data transfer from the first clock domain to the second clock domain, wherein the second buffer has a second time delay for the data transfer from the first clock domain to the second clock domain, the second delay time is longer than the first delay time, the first buffer and the second buffer being connected in parallel to each other and in series with the first clock domain and the second clock domain, wherein the first and the second buffers being connected to a multiplexor in the second clock domain; forwarding the data from the first buffer via the multiplexor into the second clock domain based on the first clock domain and the second clock domain operating in the synchronous mode; and forwarding the data from the second buffer via the multiplexor into the second clock domain based on the first clock domain and the second clock domain operating in the asynchronous mode.