Patent ID: 7851316

Claim:
A fabrication method of a semiconductor device which has a P channel type MIS transistor including a gate insulating film, a gate electrode, source/drain regions composed of first source/drain regions and second source/drain regions, and a metal silicide layer, the fabrication method comprising: (a) preparing a semiconductor substrate including an N type well surrounded by an isolation region; (b) forming the gate electrode on the N type well, with the gate insulating film interposed therebetween; (c) forming the first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; (d) forming the second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and (e) forming the metal silicide layer on the source/drain regions.