Patent ID: 8817538

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array comprising a memory string including a plurality of memory cells, the memory cells being stacked above the semiconductor substrate; a plurality of word lines electrically connected to the plurality of memory cells; a bit line electrically connected to one end of the memory string; a source line electrically connected to the other end of the memory string; a drain-side select transistor electrically connected to both one end of the memory string and the bit line; a source-side select transistor electrically connected to both the other end of the memory string and the source line; and a control circuit configured to perform an erase operation, the erase operation including a first phase and a second phase performed after the first phase, the control circuit being configured to perform the erase operation on the condition that a first voltage is applied to at least one of a gate of the drain-side select transistor and a gate of the source-side select transistor in a selected memory string during the first phase and the second phase, a second voltage is applied to a first word line during the second phase, and a third voltage is applied to a second word line during the second phase, the first word line being electrically connected to a gate of a first memory cell in the selected memory string, the second word line being electrically connected to a gate of a second memory cell in the selected memory string, and the third voltage being smaller than the second voltage.