Patent ID: 8717801

Claim:
A semiconductor memory device comprising: a memory-cell array that includes a first line, a second line intersecting the first line, and a memory cell including a variable resistive element provided in the intersection of the first and the second lines; a data-write unit configured to apply a voltage pulse to the memory cell through the first and the second lines, the voltage pulse to set and/or reset data; and a detector unit configured to compare a cell current that flows through the memory cell by the voltage pulse at the time of setting and/or resetting the data with a reference current generated from an initial value of the cell current, and to control the data-write unit in accordance with a result of comparison, wherein the data-write unit repeatedly applies the voltage pulse to the memory cell until data is set and/or reset, and the reference current is generated from the cell current that flows through the memory cell in a previous voltage pulse which immediately precedes the voltage pulse.