Patent ID: 7960214

Claim:
A fabricating process of a chip package structure, comprising: providing a first substrate having a plurality of first bonding pads; providing a second substrate having a plurality of second bonding pads; forming a plurality of bumps on the first bonding pads of the first substrate; forming a first two-stage adhesive layer on the first substrate or on the second substrate; B-stagizing the first two-stage adhesive layer to form a first B-staged adhesive layer; forming a second two-stage adhesive layer on the first B-staged adhesive layer after the first B-staged adhesive layer is formed; B-stagizing the second two-stage adhesive layer to form a second B-staged adhesive layer on the first B-staged adhesive layer, wherein a glass transition temperature of the first B-staged adhesive layer is greater than or equal to a glass transition temperature of the second B-staged adhesive layer; and bonding the first substrate and the second substrate via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.