Patent ID: 6927613

Claim:
A mono-cycle generating circuit comprising: a multiplexer receiving data, determining whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputting clock signals; a pulse generating circuit, coupled to the multiplexer, receiving the clock signals and generating a first series of pulses comprising an up-pulse preceding a down-pulse, or a second series of pulses comprising a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer; and a buffer circuit, coupled to the pulse generating circuit, comprising: a switch circuit generating the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit, and a common mode buffer circuit coupled to the switching circuit and reducing noise generated by the switch circuit.