Patent ID: 8557661

Claim:
A method of manufacturing a semiconductor device comprising steps of: forming a plurality of memory cells on a memory cell region in a substrate; alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing a plurality of wirings configured to electrically connect the plurality of memory cells; forming an etching mask pattern including a plurality of etching mask pattern elements on a top sacrificial layer; forming blocking sidewalls on either sidewalls of each of the etching mask pattern elements; forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, the first photoresist pattern exposing a predetermined portion of the top sacrificial layer; etching the exposed top sacrificial layer and an insulating interlayer below the exposed top sacrificial layer to expose a second sacrificial layer; forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, the second photoresist exposing the predetermined portion of the top sacrificial layer; and etching the exposed top and second sacrificial layers and the insulating interlayers below the respective top and second sacrificial layers using the second photoresist pattern to form a staircase shaped side edge portion.