Patent ID: 7065517

Claim:
A data processor comprising: (a) a correlation matrix memory arranged to store data; (b) input means arranged to receive sets of input data to be stored in the correlation matrix memory; (c) a sampler arranged to derive, from each set of input data, a respective set of tuples; (d) a coder arranged to code each of the tuples by tensoring; (e) a combiner arranged to combine the coded tuples for a respective set of input data; (f) a separator generator arranged to generate for each set of input data a respective, associated, unique separator; (g) storage means arranged to store the association of each separator with its respective set of input data; and (h) addressing means arranged to applying to the correlation matrix memory, for each set of input data, the respective combined coded tuples as a row address and the respective unique separator as a column address, or vice-versa: wherein said correlation matrix memory comprises a plurality of sub-correlation matrix memories; said addressing means is arranged to access a first one of said sub-correlation matrix memories and apply the combined coded tuples of a respective set of input data to that sub-correlation matrix memory unless a respective row (or column) of that sub-correlation matrix memory will become saturated by application of those tuples; and in the event of such prospective saturation, access successive ones of the sub-correlation matrix memories until those tuples can by applied to a respective one of the sub-correlation matrix memories without such saturation.