Patent ID: 7701784

Claim:
A semiconductor memory device comprising: a memory cell unit in which a plurality of memory cells are connected in series, each of the memory cells including a charge accumulation layer and a control gate formed above the charge accumulation layer; word lines each connected to the control gate of each of the corresponding memory cells; a driver circuit which selects one of the word lines and applies voltages to a selected word line and unselected word lines during a data write operation and a data read operation; and a voltage generator which includes a first charge pump circuit and second charge pump circuits and which outputs a voltage generated by the first and second charge pump circuits to the driver circuit, the first charge pump circuit being exclusively used to generate a voltage for a first word line, the first word line being one of the unselected word lines located adjacent to the selected word line, the second charge pump circuits generating a voltage for second word lines, the second word lines being the unselected word lines which are not located adjacent to the selected word line, wherein the driver circuit applies a first voltage and a second voltage to the second word lines, the second charge pump circuits generate the first voltage and the second voltage, and the number of second charge pump circuits generating the first voltage and the number of second charge pump circuits generating the second voltage each varies depending on a ratio of the number of second word lines to which the first voltage is to be applied to the number of second word lines to which the second voltage is to be applied.