Patent ID: 8819515

Claim:
An apparatus for non-binary decoding of low density parity check encoded data comprising: a message processing circuit in a low density parity check decoder operable to process variable node messages and check node messages in a log domain; a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain, wherein the check node calculation circuit comprises: a Fast Fourier Transform circuit operable to perform a Fast Fourier Transform on variable node values for a current layer in the real domain: a first inverse Fast Fourier Transform circuit operable to perform an inverse Fast Fourier Transform to yield check node values for a connected layer in the real domain; and a second inverse Fast Fourier Transform circuit operable to perform an inverse Fast Fourier Transform to yield check node values for the current layer in the real domain; and wherein the message processing circuit and the check node calculation circuit are operable to perform iterative layer decoding.