Patent ID: 8324020

Claim:
A method of fabricating an electronic module comprising: forming a chip layer including: obtaining at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface; and one of pouring, dispensing, or molding an encapsulant around and physically contacting the at least one side surface of each chip of the chip layer, the encapsulant having an upper surface substantially co-planar with or parallel to the upper surface of the at least one chip and defining at least a portion of a front surface of the chip layer, and a lower surface substantially co-planar with or parallel to a lower surface of the at least one chip and defining at least a portion of a back surface of the chip layer; forming a Faraday shield structure configured and positioned to suppress RF noise for a chip of the at least one chip of the chip layer when coupled to a ground, the forming the Faraday shield structure comprising embedding at least partially the Faraday shield structure within the encapsulant of the chip layer, and wherein forming the Faraday shield structure comprises: selectively positioning at least one RF suppression structure of the Faraday shield structure within the encapsulant relative to the chip to facilitate suppression of RF noise for the chip, the at least one RF suppression structure being surrounded by and extending through the encapsulant between the front surface and the back surface of the chip layer, wherein the at least one RF suppression structure is formed of a conductive material and is structurally configured and selectively positioned within the encapsulant to suppress RF noise for the chip of the chip layer.