Patent ID: 6867094

Claim:
A method of fabricating a stacked capacitor, comprising: forming an inter-layer insulation layer on a semiconductor substrate having at least one contact hole in which a contact pad is formed; sequentially forming a first etching stop layer on the inter-layer insulation layer, a first insulation layer on the first etching stop layer, a second etching stop layer on the first insulation layer, and a second insulation layer on the second etching stop layer; forming an opening that exposes the contact pad; forming a first conductive layer on an entire surface of a first resultant structure formed over the semiconductor substrate; forming a third insulation layer on the first conductive layer; etching the first conductive layer and the third insulation layer to expose the second insulation layer under conditions where the etching rates of the first conductive layer and the third insulation layer are substantially equal; removing the second insulation layer and the third insulation layer, thereby producing a storage node formed by the first conductive layer; forming a dielectric layer on an entire surface of a second resultant structure formed over the semiconductor substrate; and forming a second conductive layer on the dielectric layer, the second conductive layer acting as a plate node.