Patent ID: 7906385

Claim:
A method, comprising: forming an etch stop layer above a P-channel transistor and an N-channel transistor; forming a cap layer above said etch stop layer; forming a mask above said cap layer, said mask exposing a first portion of said cap layer located above said P-channel transistor and covering a second portion of said cap layer located above said N-channel transistor; removing at least a part of said first portion by using said etch stop layer and by using said mask as an etch mask; implanting a P-type dopant species into said P-channel transistor using said mask as an implantation mask; removing said mask; forming a further implantation mask covering said P-channel transistor and exposing said second portion of said cap layer; introducing an N-type dopant species through said second portion of said cap layer formed above said etch stop layer and into said N-channel transistor on the basis of said further implantation mask; and annealing said P-channel transistor and said N-channel transistor in the presence of said second portion of said cap layer formed above said etch stop layer after introducing said N-type dopant species through said second portion of said cap layer and into said N-channel transistor on the basis of said further implantation mask.