Patent ID: 7087954

Claim:
An in-service programmable logic array, comprising: a first logic plane that receives a number of input signals, the first logic plane having a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs; a second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function; and wherein each of the logic cells includes a floating gate transistor, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate and including a polysilicon layer and a metal layer; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator, the low tunnel barrier intergate insulator contacts the metal layer of the control gate and the floating gate.