Patent ID: 6893935

Claim:
A method for fabricating a semiconductor component having an integrated capacitor, which comprises the steps of: applying a passivation to a topside of a component structure; forming a bottom electrode by depositing a specially provided metal layer of TiN onto the passivation, the metal layer functioning as the bottom electrode of the integrated capacitor; removing the metal layer except for a portion forming the bottom electrode; depositing a dielectric layer of Si 3 N 4 with a relatively high dielectric constant on the metal layer; depositing a metallization plane on the dielectric layer; structuring the metallization plane to form at least one of interconnects and contact areas, and forming a top electrode of the integrated capacitor as a part of the metallization; forming the bottom electrode with a surface having less roughness than a surface of the top electrode; depositing the metal layer before depositing the metallization plane; depositing at least one covering dielectric; forming contact holes for at least one of the bottom electrode and the top electrode in the covering dielectric; filling the contact holes with an electrically conductive material; producing further contact holes in the passivation before performing the step of depositing the metal layer; and filling the further contact holes with contact hole fillings formed from an electrically conductive material for producing an electrically conductive connection to a contact area situated below the passivation and for electrically connecting the bottom electrode, the metal layer being deposited above the contact hole fillings during the step of depositing the metal layer and being produced independently of further interconnects except for the electrical connecting of the bottom electrode, being located in the same metallization plane.