Patent ID: 7687351

Claim:
A method of manufacturing a semiconductor device, comprising: forming, on a surface of a semiconductor substrate, a plurality of active regions of a first conductive type isolated from one another by shallow-trench isolation regions; forming a plurality of silicon pillars including channel silicon pillars in the active regions with a silicon nitride film as a mask; forming first semiconductor regions of a second conductive type on bottom ends of the silicon pillars with the silicon nitride film remaining on the silicon pillars; forming a sacrificial insulating film by spin coating over the silicon pillars and the semiconductor substrate; removing the sacrificial insulating film on circumferences of the silicon pillars excluding the channel silicon pillars; forming capacitance-increase-prevention insulating films on portions where the sacrificial insulating film is removed to form gate-voltage-supply silicon pillars; removing residuals of the sacrificial insulating film; forming gate insulating films on circumferences of the channel silicon pillars; forming gate voltage-supply electrodes surrounding the capacitance-increase-prevention insulating films, and gate electrodes surrounding the gate insulating films so that the gate voltage-supply electrodes and the gate electrodes are connected; forming a first inter-layer insulating film over the gate voltage-supply electrodes and the gate electrodes; removing the silicon nitride film on a top end of at least one of the channel silicon pillars so as to expose the one of the channel silicon pillars; lowering a height of the one of the channel silicon pillars by etching; exposing top ends of the channel silicon pillars excluding the one of the channel silicon pillars; and forming second semiconductor regions of the second conductive type on the exposed top ends of the channel silicon pillars.