Patent ID: 7030445

Claim:
A power MOSFET packaged device comprising: a power MOSFET comprising: a semiconductor substrate having a first surface and a second surface opposite to each other, the semiconductor substrate having a source electrode and a gate electrode provided on the first surface and a drain electrode provided on the second surface; a source terminal layer disposed on the first surface and joined to the source electrode; a gate terminal layer disposed on the first surface and joined to the gate electrode; and a drain terminal layer disposed on the second surface and joined to the drain electrode; wherein the source terminal layer and the gate terminal layer are respectively disposed on the first surface with such sizes as to fall within the area of the first surface, and the drain terminal layer is disposed with such a size as to fall within the area of the second surface, and a circuit board, wherein the power MOSFET is packaged in such a manner that the respective first and second surfaces of the semiconductor substrate in the power MOSFET are substantially normal to the circuit board.