Patent ID: 8344485

Claim:
An integrated circuit die, comprising: a device layer comprising a plurality of semiconductor devices; an interconnect layer comprising a plurality of interconnect paths connecting the semiconductor devices and embedded in a dielectric material; a plurality of hard nanoparticles embedded in the dielectric material of the interconnect layer, the hard nanoparticles having a hardness greater than a hardness of the dielectric material and of a hardness of the interconnect paths; and an x-ray blocking material having a mass attenuation coefficient below a predetermined noise threshold and having an x-ray attenuation coefficient above a predetermined attenuation threshold; wherein the x-ray blocking material is disposed between the interconnect paths and an exterior of the integrated circuit die; and wherein the x-ray blocking material comprises a first layer of a first material having the mass attenuation coefficient below the predetermined noise threshold and a second layer of a second material having the x-ray attenuation coefficient above the predetermined attenuation threshold.