Patent ID: 7372740

Claim:
A semiconductor memory device, comprising: a plurality of non-volatile memory circuits in one chip, each of the non-volatile memory circuits executing a data erase operation in response to receiving a control signal to execute the data erase operation, and after the data erase operation has completed, outputting a local completion signal distinct from the control signal; a continuous erase control circuit outputting a continuous erase start signal in response to an inputted continuous erase command; and a shift circuit outputting the control signal to a first one of the plurality of non-volatile memory circuits and receiving from the first one of the plurality of non-volatile memory circuits the local completion signal, and then outputting the control signal to the rest of the plurality of non-volatile memory circuits sequentially upon receiving the local completion signal from the preceding non-volatile memory circuit, and outputting a continuous erase completion signal upon receiving the local completion signal from the last of the plurality of non-volatile memory circuits, based on the continuous erase start signal outputted from the continuous erase control circuit.