Patent ID: 8126041

Claim:
A method of measuring clock signal jitter, said method comprising: receiving a clock signal from an on-chip phase locked loop; dividing a frequency of said clock signal by two in order to produce a feedback clock signal; coarsely tuning a circuit using a delay locked loop, said coarsely tuning comprising delaying said clock signal until a delayed clock signal with a predetermined phase shift from said clock signal is achieved and locking in said delayed clock signal such that said clock signal and said delayed clock signal are out of phase, said predetermined phase shift comprising a one-half cycle delay and said clock signal being two times said feedback clock signal providing for said one-half cycle delay to be sufficient to allow for a cycle-to-cycle jitter measurement; finely tuning said circuit using a Vernier delay line, said finely tuning comprising acquiring data indicating phase differences between said clock signal and said delayed clock signal; and processing said data to measure cycle-to-cycle jitter of said clock signal.