Patent ID: 7456654

Claim:
A level translator, comprising: a first stage coupled to receive a first phase of an input signal operating between first and second voltage levels, the first stage being adapted to provide a first output signal operating between a third voltage level and the second voltage level, the first output signal being provided at a first node, the first stage comprising: a first transistor of a first conductivity type coupled to receive the first phase of the input signal at a control terminal of the first transistor; a second transistor of a second conductivity type coupled to receive the first phase of the input signal at a control terminal of the second transistor, the second transistor having a first conduction terminal coupled to a first conduction terminal of the first transistor; and a third transistor of the second conductivity type having a control terminal coupled to the second node and a first conduction terminal coupled to a second conduction terminal of the second transistor; a second stage coupled to receive a second phase of the input signal operating between first and second voltage levels, the second stage being adapted to provide a second output signal operating between the third voltage level and the second voltage level, the second output signal being provided at a second node; and a booster stage coupled to the first and second nodes, the booster stage being activated by a control signal to increase a magnitude of the third voltage level of the first and second output signals, wherein the control signal activates the booster stage when a power supply signal magnitude providing the third voltage level is below a threshold value.