Patent ID: 7248082

Claim:
A sample-hold circuit comprising a preamplifier to which an input analog signal is applied, comprising: a core section to which the amplified output of the input analog signal by said preamplifier is applied as an input, for outputting a voltage corresponding to the variation in the input analog signal, during the sampling period of the input analog signal, and for holding and outputting the value of the voltage corresponding to the amplified output at the time of the transition of a sample clock signal during the hold period; and a current switching circuit which is connected to the output pin of the preamplifier, for enabling a current flowing into a first transistor, comprised within the preamplifier during the sampling period, to flow into a second transistor to apply a constant potential as an input to the core section during the hold period, wherein said current switching circuit comprises: a third transistor which is connected to said first transistor and to the gate terminal of which said sample signal is applied; a fourth transistor which is connected to said second transistor and to the gate terminal of which a potential, which maintains said transistor ON in DC, is applied; and wherein the inverted signal of said sample clock signal is applied to the gate terminal of said second transistor.