Patent ID: 8456200

Claim:
A gate signal line driving circuit comprising: 2n clock signal lines (n is a natural number of 2 or more) where 2n-phase clock signals, which have different phases at a predetermined cycle and sequentially become at a high voltage, are input in the normal order of the sequence in normal-directional scanning and in the inverse order of the sequence in inverse-directional scanning, respectively; and a plurality of basic circuits, each being connected with at least some of the 2n clock signal lines and outputting a gate signal, which becomes at a high voltage at a signal-high period and becomes at a low voltage at a signal-low period that is a period other than the signal-high period, from an output terminal, wherein each of the basic circuits comprises: a high-voltage applying switching circuit where one clock signal line out of the 2n clock signal lines is connected to an input side and applies a voltage applied to the clock signal line to the output terminal at on-state, and an off-signal applying switching circuit that applies an off-voltage to a switch of the high-voltage applying switching circuit at on-state, and a clock signal line where a clock signal having an inverse phase of the clock signal input to the clock signal line is input is connected to a switch of the off-signal applying switching circuit.