Patent ID: 8281208

Claim:
A receiver with capability of correcting error, comprising: a signal processor configured to generate an equalized signal according to a receiver input signal; a soft slicer configured to generate quantized data and associated soft data according to the equalized signal; a decoder with error recovery configured to generate decoded quantized data according to the quantized data and generate a soft sequence according to the soft data, wherein the decoder with error recovery is configured to correct one bit of the quantized data; a de-scrambler configured to generate a de-scrambled data bit according to the decoded quantized data and the soft sequence; a serial-to-parallel (S/P) converter with code corrector configured to generate parallel data according to the de-scrambled data bit, wherein the S/P converter with code corrector is configured to correct two bits of the de-scrambled data bits; and a code group alignment finite state machine (FSM) configured to detect code boundary and packet boundary on the parallel data, thereby generating code data.