Patent ID: 8320165

Claim:
An integrated circuit containing an SRAM array, comprising: a substrate of said integrated circuit; an SRAM cell row disposed in said SRAM array, said SRAM cell row containing a plurality of rows of SRAM cells; a strap row disposed in said SRAM array and located adjacent to said SRAM cell row; a layer of field oxide disposed at a top surface of said SRAM array; a first instance of a first polarity well of a first conductivity type disposed in said substrate, said first instance of said first polarity well extending through said SRAM cell row and said strap row; a second instance of said first polarity well of said first conductivity type disposed in said substrate, said second instance of said first polarity well extending through said SRAM cell row and said strap row; a second polarity well of a second conductivity type disposed in said substrate at a location between said first instance of said first polarity well and said second instance of said first polarity well, said second conductivity type being opposite from said first conductivity type; a substrate tap active area located in said strap row and disposed within an opening in said layer field oxide, said substrate tap active area also coupled to said second polarity well; a tap layer having said second conductivity type and disposed in said substrate tap active area, said tap layer partially overlapping said second polarity well so as to provide an electrical connection to said second polarity well; and a substrate contact plug located on a top surface of said tap layer, so that a combination of said tap layer and said substrate contact plug forms a substrate contact structure.