Patent ID: 7890826

Claim:
An asynchronous data pipeline comprising: a first plurality of pipeline stages and a second plurality of pipeline stages in alternating sequence with the first plurality of pipeline stages, wherein each of the stages includes: a control circuit, wherein the control circuits of the first plurality of the pipeline stages are each coupled to receive a first enable signal, and wherein the control circuits of the second plurality of pipeline stages are each coupled to receive a second enable signal; a latch circuit configured to latch data responsive to a pulse signal received from an output of the control circuit; and a combinational logic circuit coupled to receive data from an output of the latch circuit; wherein each of the latch circuits is scannable and, wherein the latch circuits of the first and second plurality of pipeline stages form a data scan chain configured to load test data into the combinational logic circuits during testing of the asynchronous data pipeline; and wherein the asynchronous data pipeline further includes a control scan chain configured to load control data for operating the control circuits during said testing of the data pipeline, wherein the control scan chain comprises a plurality of scannable keeper circuits each configured to hold a state of a signal line coupling corresponding adjacent ones of the control circuits, wherein control circuits of adjacent pipeline stages are coupled to communicate with each other over a single signal line.