Patent ID: 8363495

Claim:
A non-volatile memory, comprising: a memory array of non-volatile storage units partitioned into an user array portion and a redundant array portion, the redundant array portion having redundant locations for storing data slated for any defective location in the user array portion as relocated data; a first group of data latches for latching data of the user array portion and a second group of data latches for latching data or the redundant array portion; a defect map buffer storing addresses of defective locations of the user array portion; a redundant data buffer for buffering relocated data from the data latches of the redundant array portion; a one-to-many comparator for comparing a current address of the user array portion with any address of defective locations of the defect map buffer; and control circuits enabling transfer of data with said user portion data latches when the current address of the user array portion does not compare with any address of defective locations and enabling transfer of data with said redundant data buffer when the current address of the user array portion compares with an address of a defective location.