Patent ID: 8412971

Claim:
A method comprising: changing the operating point of a processor from a first operating point to a second operating point; reading a committed instructions per second (CIPS) value; calculating a sum of a threshold value and a guard band value; comparing the CIPS value to the threshold value and the sum; selectively removing power from one or more ways of a cache memory responsive to changing to the second operating point if the CIPS value is less than the threshold value; powering on all ways of the cache memory if the CIPS value is greater than the sum; wherein no additional ways of the cache memory are powered on or off if the CIPS value is greater than the threshold value and less than the sum; and processing one or more instructions in the processor subsequent to altering power of the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was altered.