Patent ID: 8269352

Claim:
A multi-chip stack package structure, comprising: a substrate, having an upper surface and a lower surface, said upper surface having a chip placement area being defined and a plurality of contacts being disposed thereon, said plurality of contacts being located outside said chip placement area; a first chip, having an active surface and a rear surface opposite to said active surface, said first chip being disposed in said chip placement area with said rear surface, a plurality of first pads being disposed on said active surface and a plurality of first bumps each being formed on one of said plurality of first pads; a second chip, having an active surface, a rear surface opposite to said active surface and a plurality of through silicon vias, said plurality of through silicon vias penetrating through said second chip interconnecting said active surface and said rear surface, a plurality of second bumps being formed on said active surface and respectively connected to said plurality of through silicon vias, wherein said second chip is mounted to said first chip with said rear surface of said second chip facing said active surface of said first chip and said plurality of through silicon vias being correspondingly connected to said plurality of first bumps respectively; a plurality of metal wires, connecting said plurality of second bumps to said plurality of contacts; a third chip, having an active surface, a rear surface opposite to said active surface and a plurality of through silicon vias, said plurality of through silicon vias penetrating through said third chip interconnecting said active surface and said rear surface, a plurality of third bumps being formed on said active surface and respectively connected to said plurality of through silicon vias, wherein said third chip is mounted to said second chip with said active surface of said third chip facing said active surface of said second chip and said plurality of third bumps being correspondingly connected to said plurality of metal wires and said plurality of second bumps respectively; a fourth chip, having an active surface and a rear surface opposite to said active surface, a plurality of second pads being disposed on said active surface and a plurality of fourth bumps each being formed on one of said plurality of second pads, said fourth chip being mounted to said third chip with said active surface of said fourth chip facing said rear surface of said third chip and said plurality of fourth bumps being correspondingly connected to said plurality of through silicon vias of said third chip respectively; and an encapsulant, encapsulating said substrate, said first chip, said second chip, said third chip, said fourth chip, and said plurality of metal wires.