Patent ID: 8762689

Claim:
A data processor of Reduced Instruction Set Computer type, comprising: an instruction execution unit configured to execute instructions of an instruction set, wherein the instruction set includes a first instruction which causes execution of a first operation process on a small data size operand and a second operation process on a large data size operand, wherein the instruction execution unit is configured to execute the first operation process on a small data size operand and the second operation process on high-order bits and on low-order bits of the large data size operand in association with a flag selected out of a first flag and a second flag according to a result of decode of the first instruction, wherein the first flag and the second flag are generated by an execution of another instruction, and where the first flag is one of a plurality of flags corresponding to the small data size operand and the second flag is one of a plurality of flags corresponding to the large data size operand of said instruction, wherein the first operation and the second operation on the low-order bits are identical processes, wherein the instruction set has a prefix instruction which modifies a subsequent instruction, and wherein the modification to the subsequent instruction includes designating a flag out of the first and the second flags to be updated by the subsequent instruction.