Patent ID: 8760936

Claim:
An apparatus, comprising: a memory controller configured to address a first number of ranks of memory, the first number of ranks being greater than one, each rank having a rank width; a memory bus coupled to the memory controller, the memory bus comprising a data bus and a control bus, the data bus having a number of data signals corresponding to the rank width; and a plurality of memory modules coupled to the memory controller through the memory bus, wherein a first memory module of the plurality of memory modules comprises: a plurality of memory circuits grouped into a second number of ranks of memory, the plurality of memory circuits having a first number of data pins; and one or more buffer circuits connected to the first number of data pins of the plurality of memory circuits, the one or more buffer circuits having a second number of data pins, wherein each of the data pins of the second number of data pins is connected to a different one of the data signals of the memory bus, and wherein the second number of data pins corresponds to a module width that is less than the rank width, wherein a sum of the module widths of the plurality of memory modules is equal to the rank width.