Patent ID: 8324917

Claim:
An integrated circuit comprising: A. a semiconductor substrate; B. functional circuits formed on the substrate; C. a first bond pad formed on the substrate to input serial test input data; D. a second bond pad separate from the first bond pad formed on the substrate to input serial test input data; E. a third bond pad separate from the first and second bond pads formed on the substrate to input serial test input data; F. plural scan path circuits formed on the substrate, each of the scan path circuits having a serial input to receive test data, and parallel outputs coupled to the functional circuits; and G. logic circuitry formed on the substrate, the logic circuitry having a first serial input coupled to the first bond pad to receive serial test input data from the first bond pad and plural parallel outputs, each of the parallel outputs being coupled to the serial input of a scan path circuit, the logic circuitry having a second serial input coupled to the second bond pad to receive serial test input data from the second bond pad and plural parallel outputs, each of the parallel outputs being coupled to the serial input of a scan path circuit, the logic circuitry having a third serial input coupled to the third bond pad to receive serial test input data from the third bond pad and plural parallel outputs, each of the parallel outputs being coupled to the serial input of a scan path circuit, the logic circuitry adapted to load a multi-bit test stimulus data pattern into each of the plural scan paths in parallel by repeatedly both receiving the serial test input data from the first, second, and third bond pads on the first, second, and third serial inputs and applying data bits to the serial inputs of the plural scan path circuits in parallel.