Patent ID: 7447105

Claim:
A memory row decoder, comprising: a first depletion NMOS transistor having a first source/drain, a second source/drain coupled to a first partially decoded signal, and a gate coupled to a second partially decoded signal; a first enhancement PMOS transistor having a first source/drain, a second source/drain coupled to the second partially decoded signal, and a gate coupled to the first source/drain of the first depletion NMOS transistor; a first enhancement NMOS transistor having a first source/drain coupled to the first source/drain of the first enhancement PMOS transistor, a second source/drain coupled to a first reference voltage, and a gate coupled to the first partially decoded signal; and a second enhancement NMOS transistor having a first source/drain coupled to the first source/drain of the first enhancement PMOS transistor, a second source/drain coupled to the first reference voltage, and a gate coupled to a reset signal, wherein the first source/drain of the first enhancement PMOS transistor acts as an output terminal of the row decoder to connect to a word line of a memory.