Patent ID: 7693001

Claim:
A Static Random Access Memory (SRAM), comprising: first and second bit lines for communicating data signals; first and second word lines for communicating enable signals; first, second, third, and fourth SRAM memory cells each including a delay component and an associated pair of feedback elements, the delay, in operation, increasing a response time of its associated pair of feedback elements an amount of time greater than a recovery time associated with a single event upset, wherein the response time is characterized by a switching time of an inverter in a pair of cross coupled inverters, and wherein the recovery time is characterized by an amount of time it takes for a radiation induced charge to dissipate, the first and second memory cells coupled to the first word line, the third and fourth memory cells coupled to the second word line, the first and third memory cells coupled to the first bit line, and the second and fourth memory cells coupled to the second bit line; and first, second, third, and fourth write-word lines for communicating delay and bypass signals, the first write-word line coupled to the delay of the first memory cell, the second write-word line coupled to the delay of the second memory cell, the third write-word line coupled to the delay of the third memory cell, and the fourth write-word line coupled to the delay of the fourth memory cell.