Patent ID: 7334110

Claim:
In a computer system having a scalar processing unit and a vector processing unit, wherein the vector processing unit includes a vector dispatch unit and wherein the vector dispatch unit includes a predispatch queue and a dispatch queue, a method of decoupling operation of the scalar processing unit from that of the vector processing unit, the method comprising: dispatching vector instructions from the scalar processing unit to the vector dispatch unit, wherein dispatching includes sending the vector instructions from the scalar processing unit to the vector dispatch unit even if all scalar operands are not ready and even if all scalar instructions issued prior to the vector instructions are not scalar committed; queueing up the vector instructions received from the scalar processing unit in the vector dispatch unit's predispatch queue; reading scalar operands from the scalar processing unit, wherein reading includes transferring the scalar operands from the scalar processing unit to the vector dispatch unit; predispatching the vector instructions from the predispatch queue to the dispatch queue in the order received, wherein predispatching includes determining if all scalar instructions issued prior to the vector instruction at the head of the predispatch queue are scalar committed and transferring the vector instruction from the predispatch queue to the dispatch queue only if all scalar instructions issued prior to the vector instruction at the head of the predispatch queue are scalar committed; dispatching the predispatched vector instruction from the dispatch queue if all required scalar operands are ready; and executing the vector instruction dispatched from the dispatch queue as a function of the scalar operands.