Patent ID: 8762436

Claim:
In a frequency synthesis device, a method for synthesizing signal frequencies using low resolution rational division, the method comprising: in a processor executing the following acts: accepting a reference frequency value; accepting a synthesized frequency value; in response to dividing the synthesized frequency value by the reference frequency value, determining an integer value numerator (n) and an integer value denominator (d); reducing a ratio of n/d to an integer (I) and a ratio of N/D, where n/d=I(N/D)=I+N/D=(I+1)−(D−N)/D), and where N/D<1; in a first flexible accumulator, creating a binary first sum of (D−N) and a binary first count from a previous cycle, in a low resolution mode; creating a binary first difference between the first sum and the denominator D ; comparing the first sum with the denominator D ; in response to the comparing, generating a first carry bit; in the low resolution mode, adding the complement of the first carry bit to a first binary sequence; using the first binary sequence to generate a k-bit quotient; and, subtracting the k-bit quotient from (I+1), to generate a divisor, in the low resolution mode.