Patent ID: 8691099

Claim:
A process of fabricating a MEMS device in or on a substrate comprised of at least two silicon layers, defining an upper semi-conductor layer and an intermediate semi-conductor layer, and at least one additional semiconductor layer, defining a bottom semiconductor layer; the upper semiconductor layer and the intermediate semiconductor layer and the bottom semiconductor layer being separated by at least two insulator layers defining an upper buried insulator layer and a lower buried insulator layer; said process comprising the steps of: A) applying a hardmask material to the upper semi-conductor layer and etching the hardmask material utilizing a first photoresist pattern to form overwidth hardmask portions for etching full height comb teeth, B) forming a second photoresist pattern on the overwidth hardmask portions to define location and a cross section of the full height comb teeth and on portions of the upper semi-conductor layer between the overwidth hardmask portions to define location and a cross section of fractional height comb teeth and to define distances between the full height and fractional height comb teeth, C) removing excess portions of the overwidth hardmask portions utilizing the second photoresist pattern and then etching away the unmasked portions of the upper semi-conductor layer utilizing the second photoresist pattern forming deep gaps in the upper semi-conductor layer with the upper buried insulator layer acting as an etch stop material for the upper semi-conductor layer etch to define exposed portions of the upper buried insulator layer, and then removing the exposed portion of the upper buried insulator layer; and D) after removal of the exposed portion of the upper buried insulator layer and the second photoresist pattern, etching exposed regions of the upper and second intermediate semiconductor layers, defining: (i) the full height comb teeth comprising portions of the upper semiconductor layer and the intermediate semiconductor layer separated by portions of the upper buried insulator layer and (ii) the fractional height comb teeth comprising portions of the intermediate semiconductor layer with vertical gaps between the full height comb teeth and the fractional height comb teeth.