Patent ID: 7401271

Claim:
Testing system for use in testing a system-under-test (SUT), the testing system comprising: a first logic section that transmits one or more test-related signals for use during a test mode of the SUT; a second logic section that transmits one or more other signals during a normal operating mode of the SUT; and a third logic section that selectively couples the first logic section or the second logic section to the SUT based upon respective states of two control signals, one of the two control signals being transmitted to the third logic section from a source that is external to the SUT, the first logic section, the second logic section, and the third logic section, the other of the two control signals being transmitted to the third logic section from the first logic section; wherein: when the third logic section couples the first logic section to the SUT, the first logic section transmits the one or more test-related signals to the SUT, and when the third logic section couples the second logic section to the SUT, the second logic section transmits the one or more other signals to the SUT; wherein the first logic section comprises built-in-self-test (BIST) logic and the one or more test-related signals comprise test input signals for use in testing the SUT.