Patent ID: 8792284

Claim:
A semiconductor device comprising: a selection transistor, a first memory cell, and a second memory cell which are electrically connected in series between a bit line and a source line, each of the first and second memory cells comprising: a first transistor including a first gate, a first source, and a first drain; a second transistor including a second gate, a second source, and a second drain; and a capacitor having one terminal electrically connected to the first gate and the second source; a first signal line electrically connected to the second drain of the first memory cell and the second drain of the second memory cell; a second signal line electrically connected to the second gate of the first memory cell and the second gate of the second memory cell; a first word line electrically connected to the other terminal of the capacitor of the first memory cell; a second word line electrically connected to the other terminal of the capacitor of the second memory cell; and a selection line electrically connected to a gate of the selection transistor, wherein the bit line is electrically connected to the first drain of the first memory cell through the selection transistor, wherein the first source of the first memory cell and the first drain of the second memory cell are electrically connected to each other, wherein the source line is electrically connected to the first source of the second memory cell, and wherein the second transistor includes an oxide semiconductor layer.