Patent ID: 8521801

Claim:
Hybrid adder circuitry on an integrated circuit, comprising: a plurality of ripple carry adders that produce sum signals from two input words and a carry input signal and that produce propagate and generate signals, wherein each ripple carry adder of the plurality of ripple carry adders comprises a plurality of full adders connected in a chain and wherein each full adder of the plurality of full adders produces a respective portion of the propagate and generate signals, and wherein each full adder of the plurality of full adders produces a carry output signal; a plurality of carry look-ahead units, wherein each carry look-ahead unit of the plurality of carry look-ahead units receives the propagate and generate signals from a respective one of the plurality of ripple carry adders and produces output signals; a carry computation unit that receives the carry input signal and the output signals from each carry look-ahead unit of the plurality of carry look-ahead units and that produces a carry out signal from the carry input signal and the output signals from the plurality of carry look-ahead units, wherein the sum signals from the ripple carry adders and the carry out signal from the carry computation unit form an arithmetic sum of the two input words; and a carry signal path for the carry output signals, wherein the carry signal path conveys the carry output signals through the plurality of ripple carry adders and wherein the carry signal path bypasses the plurality of carry look-ahead units.