Patent ID: 8842766

Claim:
An integrated circuit (IC) comprising: a digital circuit comprising: a derived clock circuit configured to receive a root clock having a frequency D*f and a single phase, wherein D is a divide factor for the root clock, wherein the derived clock circuit is configured to divide the root clock by D and generate multiphase clocks having N phases, N and D being positive integers, wherein the multiphase clocks cause a shift in interference signals to have a frequency N*f and harmonics thereof; N circuits configured to receive a corresponding one of the multiphase clocks, wherein edges of the multiphase clocks provided to the N circuits are spread over the N phases, wherein the interference signals having the frequency N*f and harmonics thereof, are generated by a reduced periodic peak current drawn by the N circuits; and an analog circuit configured to receive an in-band range of signals, wherein a value of N is configured to cause the interference signals corresponding to the frequency N*f and harmonics thereof, to be shifted outside the in-band range of signals; wherein the multiphase clocks have the frequency f and the N phases, wherein D=N′P, P being equal to a separation between the N phases; wherein the derived clock circuit further comprises: a Gray counter configured to divide the root clock and generate the multiphase clocks having multiple frequencies, wherein no two bits of the Gray counter toggle at a time.