Patent ID: 8304813

Claim:
An integrated circuit chip comprising: a core region having metal layers; an I/O region between the core region and an edge of the chip, wherein the I/O region includes a first conductor in a first metal layer and a second conductor in a second metal layer; a bonding pad within the I/O region, the bonding pad comprising a metal conductor at each of the metal layers, wherein the first conductor is connected to a first metal conductor of the bonding pad and the second conductor is connected to a second metal conductor of the bonding pad; a first circuit within the I/O region, wherein the first circuit is connected to the first conductor at an input of the first circuit; a second circuit within the core region and below all of the metal layers, wherein the second circuit is connected to the second conductor at an output of the second circuit; and wherein a portion of the first circuit occupies a portion of the first metal layer of the I/O region between the first conductor and the core region so as to preclude a third conductor in the first metal layer of the I/O region from extending from the first conductor to the core region; and wherein the first circuit is configured to receive a signal from the second circuit via the first and second conductors and the bonding pad.