Patent ID: 6975979

Claim:
A method of calculating, by the use of a computer, pin-to-pin delay time T iopath — aged , which is delay time of a signal passing between an input pin and an output pin of a logic block, and block-to-block delay time T connect — aged , which is delay time of a signal passing between two said logic blocks connected to each other, comprising: (a) calculating an amount of stress S in cast by the input pin and an amount of stress S out cast by the output pin according to the following expression: S = α ⁡ ( C W ) β where a load capacitance is represented by C[pF], constants depending on change of inputted waveform are represented by α and β, and width of channel of a transistor connected to a pin is represented by W[μm]; (b) calculating an aged delay time of the input pin δ in [%] and an aged delay time of the output pin δ out [%] according to the following expression: δ = γ ⁡ ( τ ⁢ ⁢ Sf ɛ 1 ⁢ ⅇ κ ⁢ ⁢ T ) 1 ɛ 2 where a constant depending on physical structure of the pin is represented γ, the term of guarantee of a LSI is represented by τ[hour], constants depending on process are represented by ε 1 , ε 2 and κ, working frequency is represented by f[Hz], and absolute temperature is represented by T[K]; (c) calculating and outputting for use as values representative of circuit properties of a logic level circuit the pin-to-pin delay time T iopath — aged and the block-to-block delay time T connect — aged according to the following expressions: T iopath — aged =T iopath — fresh (1+λ in δ in +λ out δ out ) T connect — aged =T connect — fresh (1+λ out δ out ) where pin-to-pin delay time and block-to-block delay time calculated ignoring aging caused by hot carrier effect are represented by T iopath — fresh [ps] and T connect — fresh [ps], and ratios of delay times occurred at an input stage and an output stage to whole delay time occurred from the input pin to the output pin are represented by λ in and λ out .