Patent ID: 6946919

Claim:
A frequency-adjustable oscillator suitable for digital signal clock synchronization, the oscillator comprising: a crystal oscillator circuit for generating a driving signal and having a voltage-variable control input for adjusting a frequency of the driving signal, the crystal oscillator circuit including a voltage variable capacitive element responsive to the control input, an AT-cut quartz resonator operably linked to the voltage variable capacitive element, and a gain stage for energizing the quartz resonator; a phase detector circuit for generating a phase offset signal; a filter which operates on the phase offset signal to produce a VCO control signal; a voltage controlled oscillator circuit operably linked to the filter and responsive to the VCO control signal for generating an analog controlled-frequency signal; a frequency divider circuit having a preselected divider ratio operably linked between the voltage controlled-frequency oscillator circuit and the phase detector circuit for generating a reduced frequency feedback signal in response to the controlled-frequency signal, the phase detector circuit being responsive to the feedback signal and the driving signal such that the phase offset signal varies according to a phase difference between the feedback signal and the driving signal; a double-sided package including a platform having a central portion and an outer portion, sidewalls extending substantially upwardly and substantially downwardly from the outer portion of the platform; the upwardly extending sidewalls and the platform forming a first cavity adapted to receive and electrically connect the quartz resonator; the downwardly extending sidewalls and the platform forming a second cavity adapted to receive and electrically connect at least one electronic component; a cover coupled with the first cavity defining a hermetic environment for containing the quartz resonator; and a sinewave-to-logic level translator circuit operably linked to the voltage controlled oscillator for generating a digital output signal responsive to the controlled-frequency signal, wherein the translator circuit is a differential receiver adapted to generate the digital output signal at voltage levels conventional for positive-referenced emitter coupled logic (PECL).