Patent ID: 7579866

Claim:
An apparatus, comprising: a programmable logic device having an array of interconnected logic regions, each of the logic regions further comprising: a plurality of logic elements; a plurality of logic region wide control signals, the plurality of logic region wide control signals being configured to be applied to each of the plurality of logic elements in the logic region in parallel; and a plurality of programmable tie-off circuits configurable for register packing associated with each of the plurality of logic elements respectively, each including a logic gate coupled to receive a configuration bit, the programmable tie-off circuits being set to selectively override one or more of the plurality of logic region wide control signals when the configuration bit is set to a register packing state without enabling any other logic region wide control signal and to allow the one or more logic region wide control signal to be applied to the associated logic element when the configuration bit is set to a second state; wherein each of the plurality of programmable tie-off circuits selectively and independently overrides the logic region wide control signal when the configuration bit is set to the register packing state.