Patent ID: 8610236

Claim:
An integrated circuit, comprising: an active area having a length and width that extend across a semiconductor substrate in different directions, and the active area being bounded by and disposed entirely between a shallow trench isolation region formed in the semiconductor substrate; a first plurality of spaced apart fingers disposed over the active area, each of the first plurality of fingers having a length that extends across the width of the active area, the first plurality of fingers forming at least one gate of at least one first transistor having a source and a drain formed by a first portion of the active area; a second plurality of spaced apart fingers disposed over the active area, each of the second plurality of fingers having a length that extends across the width of the active area, the second plurality of fingers forming at least one gate of at least one second transistor having a source and a drain formed by a second portion of the active area; a first dummy polysilicon structure disposed between an outer one of the first plurality of spaced apart fingers and a first edge of the semiconductor substrate, a portion of the first dummy polysilicon structure disposed over the active area; a second dummy polysilicon structure disposed between the first dummy polysilicon structure and the first edge of the semiconductor substrate a third dummy polysilicon structure disposed between a second outer one of the plurality of spaced apart fingers and a second edge of the semiconductor substrate, a portion of the third dummy polysilicon structure disposed over the active area; and a fourth dummy polysilicon structure disposed between the third dummy polysilicon structure and the second edge of the semiconductor substrate.