Patent ID: 8319266

Claim:
A memory device comprising: a substrate; a first dielectric layer formed on a portion of the substrate; a floating gate formed on the first dielectric layer; a second dielectric layer formed on the floating gate; a control gate formed on the second dielectric layer; a first spacer and a second spacer formed on the substrate on opposite sides of the first dielectric layer, the floating gate, the second dielectric layer, and the control gate; a first film directly contacting: a top surface of the control gate, the first spacer, the second spacer, and the substrate, the first film comprising a conformal silicon nitride film having a substantially uniform thickness, the conformal silicon nitride film filling gaps and crevices along the first dielectric layer, the floating gate, the second dielectric layer, the control gate, and interfaces associated with the first spacer and the second spacer, the conformal silicon nitride film filling the gaps and the crevices to improve memory cell data retention of the memory device, the conformal silicon nitride film being deposited using a low pressure chemical vapor deposition (LPCVD) process or using an atomic layer deposition (ALD) process; and a second film formed directly on the first film, the second film comprising a non-conformal silicon nitride film having a non-uniform thickness, a portion of the non-conformal silicon nitride film formed over the top surface of the control gate being thicker than another portion of the non-conformal silicon nitride film formed adjacent the first spacer and the second spacer, and the non-conformal silicon nitride film being deposited over the conformal silicon nitride film using a plasma enhanced chemical vapor deposition (PECVD) process.