Patent ID: 8411782

Claim:
A method comprising: in an entirely digital CMOS circuit: receiving a plurality of input data bits at a collective data rate, the plurality of input data bits being grouped into a plurality of input data words, the plurality of input data bits of each of the input data words being received from a plurality of n parallel input-data-bit streams that are different from each other, each of the plurality of n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits from the plurality of parallel input-data-bit streams; and generating a k-bit deskew channel with the selected input data bits in parallel with the plurality of input-data-bit streams, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words, each of the frames further comprising one or more framing bits.