Patent ID: 8446769

Claim:
A memory device comprising: a plurality of memory cells serially connected between a bit line and a common source line; a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells; and a common source line compensation circuit configured to generate a compensated bias voltage on the bit line or at least one of the plurality of word lines responsive to a common source line voltage on the common source line, wherein the common source line compensation circuit comprises: a common source line detector circuit coupled to the common source line and configured to generate a digital value indicative of the common source line voltage; a compensation logic circuit configured to receive the digital value and to generate a bias voltage command signal responsive thereto; and a voltage generator circuit configured to generate the compensated bias voltage responsive to the bias voltage command signal, wherein the compensation logic circuit comprises: a memory configured to store information pertaining to the plurality of memory cells; an arithmetic circuit; and a control circuit configured to cause the arithmetic unit to process the digital value responsive to the information stored in the memory and to generate the bias voltage command signal responsive to the computation.