Patent ID: 7948028

Claim:
A DRAM device, comprising: a semiconductor substrate having a memory array region and a support circuit region; a first recess gate transistor in the memory array region, comprising a first recess gate inlaid into a first gate trench, a first source doping region at one side of the first gate trench, a first drain doping region at the other side of the first gate trench opposite to the first source doping region, a first U-shaped channel at a bottom of the first gate trench, and a first gate dielectric layer formed between the first recess gate and the semiconductor substrate, wherein the first gate dielectric layer has a uniform thickness; a second recess gate transistor in the support circuit region, comprising a second recess gate inlaid into a second gate trench, a second source doping region at one side of the second gate trench, a second drain doping region at the other side of the second gate trench opposite to the second source doping region, a second U-shaped channel at a bottom of the second gate trench, and a second gate dielectric layer formed between the second recess gate and the semiconductor substrate, wherein the second recess gate transistor is a high-voltage NMOS transistor and the second gate dielectric layer has variable thicknesses; and a low-voltage PMOS transistor within the support circuit region, wherein the low-voltage PMOS transistor is a planar-channel PMOS transistor.