Patent ID: 8904252

Claim:
A scan test circuit, comprising: a functional path, comprising: a D-type latch, for receiving an input and generating an output, the D-type latch including a feedback node and being clocked by pulses generated according to a system clock signal, comprising: a first inverter for receiving the input; a transmission gate coupled to the first inverter and clocked by the pulses; a latch tri-state inverter coupled to the transmission gate, the first tri-state inverter comprising the feedback node and being clocked by the pulses; and a second inverter, coupled to the first tri-state inverter, for generating the output; a test path, comprising: a scan latch, for receiving a test input according to a test enable signal and generating an output, the scan latch being clocked by a test clock signal, comprising: a first test inverter for receiving the test input; a first transmission gate coupled to the first test inverter and clocked by the test clock signal; a second test inverter coupled to the first transmission gate; a tri-state buffer coupled to the second test inverter and clocked by the test clock signal; and a second transmission gate, coupled in parallel to the first transmission gate and coupled to the tri-state buffer, and clocked by the test clock signal, for generating the output to the feedback node of the functional path and the tri-state inverter; and a tri-state inverter, coupled to the test path and the functional path; wherein the output of the test path is input to the feedback node of the D-type latch and the tri-state inverter, and when the test enable signal is enabled, the generation of the pulses is disabled.