Patent ID: 6959351

Claim:
A data processing apparatus, comprising: a processor operable to execute instructions; a first master logic unit and a second master logic unit operable to process access requests generated during execution of said instructions, said access requests specifying accesses to a slave device, the first master logic unit being operable to access the slave device via a first bus, and the second master logic unit being operable to access the slave device via a second bus; routing logic operable to determine, for each access request, which master logic unit is to process that access request, the first master logic unit being arranged to process access requests of a first type, and the second master logic unit being arranged to process access requests of a second type; at least one of said instructions being a multi-access instruction executable to cause both an access request of the first type and an access request of the second type to be generated, the multi-access instruction requiring that the accesses to the slave device specified by the access requests of the first and second type are made without any intervening accesses to the slave device taking place; the routing logic being arranged in the event of execution of the multi-access instruction to cause both the access request of the first type and the access request of the second type specified by the multi-access instruction to be processed by said first master logic unit; the first master logic unit being arranged, when processing the access request of the first type and the access request of the second type specified by the multi-access instruction, to issue a lock signal used to ensure that the first master logic unit is granted sole access to the slave device whilst the first master logic unit is processing the access requests of the first and second type.