Patent ID: 7958315

Claim:
A data processing system, comprising: a system memory including a page frame table containing mappings between effective addresses in a plurality of virtual memory pages and physical addresses in the system memory, the plurality of virtual memory pages including large pages each including multiple sub-pages; a processor, coupled to said system memory via an interconnect, wherein said processor includes: a pre-fetcher; and a data memory management unit (DMMU) having a first-level cache memory for storing only mappings for sub-pages and a second-level cache memory for storing only mappings for the large pages, the first-level cache memory including a plurality of entries each containing a mapping for a respective one of the sub-pages, wherein the DMMU, after detecting a first access sequence including different first, second, and third addresses, wherein said first and second addresses belong to a first sub-page, said third address belongs to a second sub-page, and a first stride between said first and second addresses does not equal a second stride between said second and third addresses, determines if a second access sequence accesses a fifth address in said second sub-page immediately after accessing a fourth address in said first sub-page, and wherein the DMMU, responsive to said determination, instructs said pre-fetcher to pre-fetch from at least said second sub-page upon a third access sequence accessing a sixth address in said first sub-page.