Patent ID: 8565008

Claim:
A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory coupled to the processor bus adapted to allow data to be stored, the dynamic random access memory comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address responsive to a command word; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to the command word; a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to the command word; a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to the command word; and a command data latch circuit for storing a command data packet at a time determined from a command clock signal, the command data latch comprising: a latch circuit configured to receive the command data and receive a selected internal clock signal appropriate to latch the command data, the latch circuit operable to latch the command data in accordance with the selected internal clock signal; a clock generator configured to receive a master clock signal based on the command clock signal, the clock generator operable to generate a plurality of internal clock signals, including the selected internal clock signal and a reference clock signal, each internal clock signal having a different phase relative to the command clock signal and the reference clock signal having a phase relative to the command clock signal, the clock generator further configured to receive a select signal, the clock generator operable to couple the selected internal clock signal to the latch circuit responsive to the select signal; a select circuit coupled to the latch circuit and the clock generator, the select circuit operable to identify the selected internal clock signal from the plurality of internal clock signals and generate the select signal for the clock generator; a first locked loop operable to lock the phase between a first one of the plurality of internal clock signals and the reference clock signal; and a second locked loop operable to lock the phase between the master clock signal and the reference clock signal.