Patent ID: 7142467

Claim:
A synchronous semiconductor memory device comprising: a clock buffer for buffering an external clock; a plurality of command buffers for buffering a plurality of external commands; a plurality of address buffers for buffering a plurality of external addresses; a command decoder for generating a plurality of internal commands in response to output signals from the plurality of command buffers synchronously with respect to an internal clock; a clock driving unit for driving a clock outputted from the clock buffer to generate the internal clock and generating a latch clock, wherein a specific level of the latch clock is maintained from a time point when one of the plurality of internal commands is applied to a time point when a next one of the plurality of internal commands is applied; and a plurality of address latches for generating a plurality of latch addresses in response to a plurality of internal addresses outputted from the plurality of address buffers synchronously with respect to the latch clock.