Patent ID: 7159145

Claim:
A test system for testing an embedded memory core on a semiconductor chip having built in self test (BIST) circuitry, the test system comprising: a simulated test program having a control interface for initializing and clocking the BIST circuitry on the semiconductor chip; an address generator for generating a first address sequence matching a second address sequence generated by the BIST circuitry during a built in self test of the embedded memory care, wherein the address generator receives clocking information from the simulated test program for synchronizing the first address sequence with the second address sequence; and data input nodes for receiving data out bus signals from the BIST circuitry during the built in self test of the embedded memory core, wherein the data out bus signals indicate whether individual memory cells failed the built in self test, and wherein the test system is adapted to correlate a specific memory cell failure with a corresponding address generated by the address generator.