Patent ID: 7479809

Claim:
A system for detecting an input voltage level, the system comprising: an input node configured to receive an input signal; first and second diode-connected transistors having respective drain terminals coupled to the input node, wherein the first and second diode-connected transistors are operable to set an intermediate voltage at the input node when the input node is in an open state; first and second inverting stages having respective inputs coupled to the input node, wherein the first and second inverting stages are operable to provide an indication of a present state of the input node being one of: a high state for a high-level input signal, a low state for a low-level input signal, and an open state; and first and second latches having respective outputs, the first latch having an input coupled to an output of the first inverting stage and the second latch having an input coupled to an output of the second inverting stage, wherein the first and second latches are operable to latch the present state of the input node; wherein the system is operable to cease conducting current after the present state of the input node has been latched.