Patent ID: 7313053

Claim:
A device comprising: a multiplicity of sensors arranged along generally parallel lines; a multiplicity of bus lines, a first multiplicity of switches for selectively electrically connecting sensors to bus lines, wherein each switch of said first multiplicity is of a type that can memorize data representing its current switch state, each sensor having at least a respective switch of said first multiplicity associated therewith; a second multiplicity of switches for selectively electrically connecting sensors to each other, wherein each switch of said second multiplicity is of a type that can memorize data representing its current switch state, each sensor having at least a respective switch of said second multiplicity associated therewith; data generator circuitry for generating switch state data representing the state of switches of said first and second multiplicities to be programmed; address generator circuitry for generating address data identifying said switches of said first and second multiplicities to be programmed; and a multiplicity of control logic circuits for outputting switch state control data to said switches of said first and second multiplicities to be programmed in response to receipt of said switch state data, each sensor having a respective control logic circuit associated therewith, said switch state control data controlling the state of said switches and being derived from said switch state data, and each sensor having a respective control logic circuit associated therewith.