Patent ID: 7567196

Claim:
A method for generating a digital-to-analog converter reset voltage, said method comprising: applying a first control signal to each of a first digital-to-analog converter and a second digital-to-analog converter, said step of applying a first control signal comprising, applying the first control signal to a first reference selector of the first digital-to-analog converter, wherein the first reference selector, in response to the first control signal, generates the first analog reference voltage and applies said first analog reference voltage to a first capacitor and a second capacitor of the first digital-to-analog converter, and inverting the first control signal and applying the inverted first control signal to a second reference selector of the second digital-to-analog converter, wherein the second reference selector, in response to the inverted first control signal generates the second analog reference voltage, and applies the second analog reference voltage to a third capacitor and a fourth capacitor of the second digital-to-analog converter; applying a second control signal to each the first digital-to-analog converter and the second digital-to-analog converter, said step of applying a second control signal comprising, applying the second control signal to the first reference selector, wherein the first reference selector generates the second analog reference voltage, and applies the second analog reference voltage to the first capacitor of the first digital-to-analog converter, and inverting the second control signal and applying the inverted second control signal to the second reference selector, wherein the second reference selector generates the first analog reference voltage, and applies the first analog reference voltage to the third capacitor of the second digital-to-analog converter; charge sharing said first capacitor and second capacitor to generate a first analog reset voltage at the first digital-to-analog converter; and charge sharing said third and fourth capacitors to generate a second analog reset voltage at the second digital-to-analog converter.