Patent ID: 7127552

Claim:
An initialization circuit, comprising: a non-volatile memory including a plurality of words, each word including a first transfer bit having a first stored value that is a predetermined one of a programmed value and an erased value, the non-volatile memory having an input port, an output port, and a control input port; wherein each word in the non-volatile memory further includes a plurality of data bits in addition to the first transfer bit, and the first transfer bit is a control bit; a sensing array having an input port coupled to the output port of the non-volatile memory and an output port, the output port of the sensing array including a first terminal on which a sensed first transfer bit is placed; a volatile memory having an input port coupled to the output port of the sensing array and a control input port; a control circuit coupled to the first terminal of the sensing array and the control input ports of the non-volatile and volatile memories; and wherein the control circuit is configured to transfer the data bits of the plurality of words from the non-volatile memory to the volatile memory, monitor the value of each first transfer bit at the first terminal of the output port of the sensing circuit, restart the transfer responsive to the predetermined value of a first transfer bit being the programmed value and the value of the first transfer bit at the first terminal being the erased value, and restart the transfer responsive to the predetermined value of a first transfer bit being the erased value and the value of the first transfer bit at the first terminal being the programmed value.