Patent ID: 6941497

Claim:
A method for selecting an optimal test sequence from a sequence of N tests for detecting faults in digital integrated circuits (IC's) comprising: for each test of the sequence of N tests, compiling test results for L defective dice, wherein said N tests comprise one or more redundant tests and one or more inefficient tests; representing each test of the sequence of N tests as a correlation vector of length L, such that the sequence of N tests is represented as N correlation vectors, wherein element j of correlation vector for test i is zero if device j passed test i; finding a first correlation vector of the N correlation vectors that has the most non-zero components and initializing a vector W to be the complement of the first correlation vector; selecting a first test in the optimal test sequence to be the test represented by the first correlation vector; for each correlation vector of the remaining N-1 correlation vectors, calculating a product of the complement of each correlation vector and the vector W; calculating a length of a projection of each calculated product vector onto a unit vector; finding a next correlation vector that is the correlation vector of the N-1 correlation vectors that has a smallest value of the projection length; selecting a next test in the optimal test sequence to be the test represented by the next correlation vector; updating the vector W to be a product of vector W and a compliment of the determined correlation vector in the previous step; and repeating the previous five elements, until the length of the projection of vector W onto the unit vector is zero.