Patent ID: 8503511

Claim:
Receiver apparatus for determining a correlation value of a predetermined repetitive chip sequence in a receive signal, the chip sequence comprising a chip sequence duration and a chip sequence repetition cycle, comprising a receive unit for receiving the receive signal; a segmenter for providing receive signal segments from the receive signal, two receive signal segments representing the same chip sequence in different repetition cycles and comprising at least one repetition cycle time spacing; a frequency corrector for determining sets of frequency corrected receive signal segments based on sets of correction frequencies, the correction frequencies being based on the chip sequence duration and the chip sequence repetition cycle; a chip sequence generator for generating the predetermined chip sequence; a correlator for correlating the predetermined chip sequence with the frequency corrected receive signal segments of a set to acquire a set correlation value; and a selector for selecting one of the set correlation values meeting a predetermined condition as the correlation value, wherein the frequency corrector is adapted for determining one set of correction frequencies per frequency of a coarse grid of frequencies between a minimum coarse frequency and a maximum coarse frequency with a coarse step size being based on the chip sequence duration; the frequency corrector is adapted for determining one set of correction frequencies per frequency of a fine grid of frequencies around a correction frequency of the coarse grid, the fine grid comprising a minimum fine frequency offset from the coarse correction frequency, a maximum fine frequency offset from the coarse correction frequency and a fine step size; and the minimum fine frequency is greater than or equal to −0.5 divided by the chip sequence repetition cycle, the maximum fine frequency offset is less than or equal to 0.5 divided by the chip sequence repetition cycle and the fine step size is less than or equal to one-third divided by the chip sequence repetition cycle.