Patent ID: 7630375

Claim:
A data transfer control device that controls data transfer, the data transfer control device comprising: a link controller that analyzes a packet received from a host-side data transfer control device through a serial bus; and an interface circuit that generates an interface signal and outputs the interface signal to an interface bus, the data transfer control device being a target-side data transfer control device, the packet received from the host-side data transfer control device including an address automatic update field an address field, and a data field, the interface circuit performing address automatic update processing M times to generate a first automatically updated address to a (M)th automatically updated address by increment or decrement of a start address in the case that the address automatic update field indicates that an address automatic update mode is set to ON, the address field includes the start address and the data field includes K bits of data, K=L×(M+1), and K, L, and M are integers of two or more, and the interface signal including the start address and the first automatically updated address to the (M)th automatically updated address as well as a first L-bit-data to an (M+1)th L-bit-data of the K bits of data, and the start address and the first automatically updated address to the (M)th automatically updated address respectively corresponding to the first L-bit-data to the (M+1)th L-bit-data of the K bits of data.