Patent ID: 6990036

Claim:
A memory device comprising: a first subarray of memory cells organized into rows and columns; a first plurality of bit lines, each coupled to a column of memory cells; a first set of subarray isolators to selectively couple the first plurality of bit lines to a first row of sense amplifiers; a first set of common isolators to selectively couple the first row of sense amplifiers to a plurality of global I/O lines; and isolator control logic to coordinate the operation of the first set of common isolators to allow data received from outside the memory device and present on the plurality of global I/O lines to be latched by the first row of sense amplifiers, to store an indication that the data latched by the first row of sense amplifiers is dirty, to coordinate the operation of the first set of subarray isolators to allow data latched by the first row of sense amplifiers to be written back to a row of memory cells within the first subarray, and to remove an indication that the data latched by the first row of sense amplifiers is dirty.