Patent ID: 8018420

Claim:
A liquid crystal display device comprising: a first and second substrate facing each other; a plurality of pairs of data lines formed in a display section of the first substrate, each pair of data lines including first and second data lines adjacent to each other wherein there is no pixel area between each different pair of data lines; a plurality of gate lines formed on the first substrate and intersecting the plurality of pairs of data lines, the gate lines defining pixel areas between the first and second data lines; a plurality of pixel electrodes formed in the pixel areas; a gate driver for applying a gate signal to the gate lines, wherein the gate driver applies a gate high signal such that during a first half period, the gate high signal is applied to a previous gate line and a current gate line, and during a second half period, the gate high signal applies to the current gate line and a subsequent gate line, and the previous gate line and the subsequent gate line are disposed longitudinally adjacent the current gate line; a source driver for outputting the same data voltage charged in different polarities to the first and second data lines of each pair of data lines, wherein the application of the data signal to the second data line is delayed by a half-period of the gate high signal after the data signal is applied to the first data line; a first thin film transistor in a pixel area between a corresponding gate line and the first data line; a second thin film transistor in a pixel area between the corresponding gate line and the second data line; and a latch circuit for storing the data signal output from an output terminal of the source driver, the latch circuit transmitting a relevant data signal to a first pixel electrode and a second pixel electrode formed between the first and second data lines of each pair of data lines, wherein a data voltage is sufficiently charged on each pixel electrode when the gate driver is operated at a high speed and application time of the gate high signal to each gate line is twice as much as a value to divide one frame into the number of the gate lines.