Patent ID: 8310040

Claim:
A semiconductor device package comprising: a semiconductor device including a substrate composed of a semiconductor material and a plurality of metallic connection pads formed on the substrate, the plurality of metallic connection pads being formed on each of first and second opposing surfaces of the substrate with edges of the semiconductor device extending between the first and second surfaces; a first passivation layer applied on the semiconductor device, the first passivation layer being applied so as to cover the semiconductor device including the plurality of metallic connection pads formed on the substrate; a base dielectric laminate sheet affixed to the first surface of the semiconductor device, the base dielectric laminate sheet having a thickness greater than that of the first passivation layer; a second passivation layer applied over the first passivation layer and the semiconductor device and having a thickness greater than that of the first passivation layer, with the second passivation layer covering the second surface and the edges of the semiconductor device; and a plurality of metal interconnects electrically coupled to the plurality of metallic connection pads of the semiconductor device, each of the plurality of metal interconnects extending through a respective via formed through the first and second passivation layers or through the base dielectric laminate sheet to form a direct metallic connection with one of the plurality of metallic connection pads.