Patent ID: 8456887

Claim:
A nonvolatile semiconductor memory device, comprising: a cell array having plural memory cells, said each memory cell including a variable resistor having a resistance reversibly variable in response to certain voltage or current supply to store data corresponding to the resistance of said variable resistor; a selection circuit operative to select a memory cell to be erased or written data from said cell array; and a write circuit operative to execute certain voltage or current supply to said memory cell selected by said selection circuit to vary the resistance of a variable resistor in said selected memory cell to erase or write data, wherein said write circuit includes a constant current circuit operative to supply a constant current for data erase to a current path for supplying current to said selected memory cell, and terminates said voltage or current supply to said selected memory cell when current flowing in said selected memory cell reaches a certain level after said data erase or write, wherein said write circuit further includes: a first current path for supplying current from said constant current circuit to said selected memory cell; a second current path for current monitor provided in parallel with said first current path and supplied with current from said constant current circuit; and a resistor circuit copied with a parasitic resistance of said first current path to said second current path; and wherein said resistor circuit inserts a resistor into said second current path, said resistor corresponding to the first current path selected by said selection circuit.