Patent ID: 8736022

Claim:
A semiconductor device, comprising: a semiconductor chip having a peripheral region; an internal circuit region arranged on an inner side of the semiconductor chip; a bonding pad region arranged adjacently to the internal circuit region, an entirety of the peripheral region of the semiconductor chip being arranged outside of the internal circuit region and the bonding pad region; and a diode-type ESD protection circuit arranged continuously along the entirety of the peripheral region of the semiconductor chip, the diode-type ESD protection circuit being formed of a junction between a first conductivity type diffusion layer for fixing a substrate potential of the semiconductor chip and a pair of second conductivity type diffusion layers having the second conductivity type different from the first conductivity type and arranged on an inner side of the first conductivity type diffusion layer, one of the pair of second conductivity type diffusion layers comprising a diffusion layer for breakdown adjustment at a junction portion with the first conductivity type diffusion layer, the first conductivity type diffusion layer and at least one of the pair of second conductivity type diffusion layers completely surrounding the internal circuit region, and the bonding pad region being disposed between the internal circuit region and the first conductivity type diffusion layer.