Patent ID: 8605514

Claim:
A nonvolatile semiconductor memory device comprising: a first memory cell connected to a first word line; a second memory cell connected to a second word line which is adjacent to the first word line and has a width different from a width of the first word line; and a control circuit which applies a first voltage to the first word line and a second voltage different from the first voltage to the second word line, wherein at least one of the first voltage and the second voltage is a voltage corrected by the control circuit based on loop counts of the first memory cell and the second memory cell in an nth-write (n is natural number) operation of the first memory cell and the second memory cell, and the control circuit applies the first voltage to the first word line in an mth-write operation (m is natural number larger than n) of the first memory cell after the nth-write operation of the first memory cell and the second memory cell or applies the second voltage to the second word line in the mth-page write mth-write operation of the second memory cell after the nth-write operation of the first memory cell and the second memory cell.