Patent ID: 7668276

Claim:
A phase adjustment device comprising: an input-output (I/O) interface; a transmit phase adjuster, coupled to said I/O interface and configured to receive a plurality of phase vector clock signals; and a receiver phase adjuster coupled to said I/O interface and configured to receive said plurality of phase vector clock signals; the transmit phase adjuster comprising: a transmit clock phase interpolator configured to generate a transmit clock with a phase determined in accordance with a digitally stored transmit phase value, the digitally stored transmit phase value comprising a transmit phase-select value programmed to select a pair of said phase vector clock signals and a transmit phase-blend value programmed to control interpolation of the selected pair of said phase vector clock signals; an output circuit configured to time transmission of transmit data in accordance with the transmit clock; and the receiver phase adjuster comprising: a receiver clock phase interpolator configured to generate a receive clock with a phase determined in accordance with a digitally stored receiver phase value; and an input sampling circuit configured to time receiving of receive data in accordance with the receive clock; wherein the output circuit includes a transmit data phase adjuster configured to transmit the transmit data with a phase determined by the transmit clock; and the input sampling circuit includes a receiver data phase adjuster configured to sample the receive data with a phase determined by the receive clock.