Patent ID: 8027214

Claim:
A sense amplifier comprising: an imbalanced cross-coupled latch (ICL) coupled to a bit line (BL) and a bit line inverse (BLB), the ICL configured to output a logic low value if a difference between a value on the BL and a value on the BLB exceeds a threshold and to output a logic high value if the difference does not exceed the threshold, the ICL comprising, a first pull down field effect transistor (FET) with its channel coupled between a first output node and electrical ground by way of a channel of an enable FET, and a second pull down FET with its channel coupled between a second output node and electrical ground by way of the channel of the enable FET; a first pull up FET with its channel coupled between a supply voltage and the first output node and having a gate terminal; a second pull up FET with its channel coupled between the supply voltage and the second output node and having a gate terminal; a precharge circuit configured to couple a supply voltage to the first output node and to couple the supply voltage to the second output node and to couple the gate terminals of the first pull up FET and the second pull up FET to each other, responsive to a precharge control signal; a first gate FET with its channel coupled between the BL and the first output node; and a second gate FET with its channel coupled between the BLB and the second output node; wherein a gate terminal of the first pull down FET is coupled to the second output node; wherein a gate terminal of the second pull down FET is coupled to the first output node; wherein a width of the channel of the second pull down FET is wider than a width of the channel of the first pull down FET; and wherein a width of the channel of the second gate FET is wider than a width of the channel of the first gate FET.