Patent ID: 6965164

Claim:
An electronic device comprising: a semiconductor substrate in which an integrated circuit is formed; an insulating layer which is formed on the semiconductor substrate and has a first upper surface; an elastically deformable section formed on the first upper surface, the elastically deformable section formed at a position closer to one of edges of the semiconductor substrate than a center of the semiconductor substrate, the elastically deformable section having a second upper surface; first and second electrodes which are electrically connected with an inside of the semiconductor substrate, the first electrode being formed on the first upper surface, the second electrode being formed on the second upper surface; a first substrate on which a first interconnect pattern is formed, the first interconnect pattern facing the first electrode and being electrically connected with the first electrode; and a second substrate on which a second interconnect pattern is formed, the second interconnect pattern facing the second electrode and being electrically connected with the second electrode, wherein the elastically deformable section is elastically deformed in a manner to be depressed under the second electrode, and presses the second electrode against the second interconnect pattern due to elasticity.