Patent ID: 7523297

Claim:
A method for processing a shadow scan instruction in a multi-threaded microprocessing environment, comprising: reading a shadow scan instruction that includes a thread identifier and a plurality of core identifiers, the plurality of core identifiers being assigned a state to identify microprocessor cores of a multi-core structure in which a shadow scan operation is to be executed, the thread identifier defined to select a thread running in the identified core, and processing through the selected thread of the identified cores is defined through the shadow scan instruction; processing the plurality of core identifiers, each of the plurality of core identifiers being analyzed to determine if the shadow scan operation is to be executed through a selected thread running in each identified core; and sequentially examining the plurality of core identifiers, if the examination indicates that the identified core is active, proceeding with executing the shadow scan operation of the identified core through the selected thread running in the identified core, and moving to the examination of the next core identifier of the shadow scan instruction; and if the examination indicates that the identified core is not active, moving to the examination of the next core identifier of the shadow scan instruction.