Patent ID: 7940089

Claim:
A peak detect-and-hold circuit using ramp sampling technique for detecting and holding a peak voltage of an input voltage, wherein the peak detect-and-hold circuit comprises: a sampling signal generator producing at least a first sampling signal and a second sampling signal, wherein the first sampling signal and the second sampling signal are rising waveforms, and the slope of the first sampling signal is greater than that of the second sampling signal; a first comparator receiving the first sampling signal generated by the sampling signal generator and the input voltage; a first sample-and-hold circuit wherein the first comparator controls the first sample-and-hold circuit to keep a first tracking voltage tracking the input voltage when the first sampling signal is less than the input voltage, and to sample the input voltage and hold the first tracking voltage at the sampled input voltage when the first sampling signal is equal to the input voltage; a second comparator receiving the second sampling signal generated by the sampling signal generator and the input voltage; a second sample-and-hold circuit wherein the second comparator controls the second sample-and-hold circuit to keep a second tracking voltage tracking the input voltage when the second sampling signal is less than the input voltage, and to sample the input voltage and hold the second tracking voltage at the sampled input voltage when the second sampling signal is equal to the input voltage; and a third comparator receiving the second tracking voltage and the input voltage, wherein when the second tracking voltage is smaller than the input voltage the third comparator triggers the sampling signal generator to generate another of the first sampling signal and another of the second sampling signal; and when the second tracking voltage is greater than the input voltage, the first tracking voltage is taken as the peak voltage.