Patent ID: 7320114

Claim:
A method for verifying soft error detection and correction in an integrated circuit (IC) design, the method comprising: generating a diagnostic program using a diagnostic program generator that inserts a plurality of random program instructions and periodically inserts an error directive into the diagnostic program, each error directive causing injection of a soft error of a particular type, the type of the soft error being randomly selected by the diagnostic program generator at the time the diagnostic program is generated; executing the diagnostic program on a virtual IC based on the IC design using a simulator; injecting the soft error into the virtual IC to trigger hardware error correction in the virtual IC and a software exception, the injecting being in response to one of the error directives; creating a record, the record including a type of the soft error and a location of the soft error; and comparing an error log generated by hardware error correction with the record of injected error, the hardware error correction being part of the virtual IC; and identifying an IC design flaw when a discrepancy exists between the error log and the record of the injected error.