Patent ID: 7378678

Claim:
A method of forming a memory device, said method comprising: simultaneously forming a series of single memory cells, wherein forming of each of said single memory cells in said series comprises: forming two parallel holes in an insulating layer; forming a memory element with a first top electrical contact in one of said two parallel holes by filling said one of said two parallel holes with a first conductive layer, a transition metal oxide layer on said first conductive layer, and a second conductive layer on said transition metal oxide layer, forming a conductive section with a second top electrical contact in another of said two parallel holes by filling said other of said two parallel holes with a conductive material; and electrically connecting said memory element and said conductive section; simultaneously conditioning all of said transition metal oxide layers of said memory elements of said single memory cells in said series, wherein said conditioning causes said transition metal oxide layers to exhibit a bi-stable electrical resistance, wherein said process of simultaneously conditioning all of said transition metal oxide layers comprises: connecting said first top electrical contacts of said memory elements of each of said single memory cells in said series to said second top electrical contacts of said conductive sections of an adjacent single memory cell in said series with a temporary conductor, connecting said temporary conductor at an end of said series to a power source adapted to output a current through said series of said single memory cells.