Patent ID: 8825415

Claim:
An estimation unit for estimating a nonlinearity error of a conversion circuit, the conversion circuit being configured to receive a continuous-time input signal and output a digital output signal, wherein the continuous-time input signal is bandlimited to an angular frequency band [ω 1 , ω 2 ], where ω 1 >(L−1)π/T, ω 2 <Lπ/T, L is a positive integer, and T is a sample period of the conversion circuit, the estimation unit comprising: an input port configured to receive a digital input signal having a first sample rate 1/T, wherein the digital input signal is an approximation of the continuous-time input signal to the conversion circuit; an output port configured to output a digital estimated error signal having the first sample rate, wherein the digital estimated error signal is an estimate of the nonlinearity error of the conversion circuit; a computational branch for each integer P_k in a set of integers, each integer corresponding to a desired model for estimating the nonlinearity error, the computational branch including, a first linear filter unit configured to generate a first signal s 1 (n) as a linear function of the digital input signal, wherein n is a first sequence index, an interpolation unit configured to interpolate the first signal s 1 (n) to generate a second signal s 2 (m) having a second sample rate which is a factor L·R_k higher than the first sample rate, wherein m is a second sequence index and R_k is a value selected so that L·R_k≧T·ω 2 ·P_k/π, a nonlinearity unit configured to generate a third signal s 3 (m) as (s 2 (m)) P — k , and a second linear filter unit configured to generate a component of the estimated error signal based on the third signal s 3 (m), wherein said component has the first sample rate; and an adder circuit configured to generate the estimated error signal as a sum of the components of the estimated error signal.