Patent ID: 7203114

Claim:
A semiconductor memory comprising: a memory core which has dynamic memory cells; an oscillator which generates a refresh request signal periodically for refreshing said dynamic memory cells; a storing circuit which includes a holding part holding a stored value, changes the stored value by a predetermined value so that it goes away from an initial value, in response to said refresh request signal, and changes the stored value by one so that it approaches to the initial value, in response to a refresh operation corresponding to said refresh request signal; a state detecting circuit which detects a change of the semiconductor memory from a first state to a second state and from the second state to the first state; a store control circuit which increases said predetermined value used by said storing circuit in response to the detection of the change from the first state to the second state by said state detecting circuit, and decreases said predetermined value used by said storing circuit in response to the detection of the change from the second state to the first state by said state detecting circuit; a refresh decision circuit which receives the stored value held in said holding part and outputs a number of refresh signals until the stored value returns to the initial value, the number corresponding to the stored value; and a core control circuit which allows said memory core to perform the refresh operation in response to each of said refresh signals and allows said memory core to perform an access operation in response to an external access request.