Patent ID: 7561458

Claim:
A ferroelectric memory device, comprising: an array of ferroelectric memory cells arranged in rows along a wordline direction and columns along a bitline direction, the ferroelectric memory cells individually comprising a ferroelectric cell capacitor having first and second terminals and a cell transistor adapted to selectively couple the first cell capacitor terminal to an array bitline associated with an array column according to an array wordline, wherein rows of the memory cells are coupled with a corresponding array wordline and a corresponding array plateline; a zero cancellation circuit coupled with an array bitline, the zero cancellation circuit comprising a zero cancellation capacitor having first and second terminals, and a zero cancellation switching device coupled with the zero cancellation capacitor, the zero cancellation switching device selectively coupling the first zero cancellation capacitor terminal with the array bitline according to a zero cancellation wordline signal; and a control system coupled with the zero cancellation circuit, the control system providing the zero cancellation wordline signal to the zero cancellation switching device and providing a negative zero cancellation plateline pulse of a pre-determined magnitude to the second zero cancellation capacitor terminal while a cell plateline signal is activated to provide a voltage across a target ferroelectric cell capacitor; wherein the zero cancellation circuit is substantially identical to the individual ferroelectric memory cells, and wherein the ferroelectric memory cells and the zero cancellation circuit are formed in a multi-layer structure with conductive contacts formed between layers, and wherein at least one layer of the zero cancellation circuit is identical to that of the individual ferroelectric memory cells.