Patent ID: 8539406

Claim:
A computer-implemented method for performing formal verification, the method comprising: accessing a first electronic design; accessing a second electronic design, the second electronic design having been synthesized from the first electronic design using a synthesis process that did not include any retiming operations; accessing a third electronic design, the third electronic design having been synthesized from the first electronic design using a synthesis process that included one or more retiming operations; receiving a retiming guidance file corresponding to the one or more retiming operations; implementing a first formal verification process on the first electronic design and the second electronic design, wherein a first result is obtained; modifying the second electronic design based in part upon the retiming guidance file; implementing a second formal verification process on the modified second electronic design and the third electronic design, wherein a second result is obtained; comparing the first result to the second result to generate a comparison result; and saving the comparison result to one or more memory storage locations.