Patent ID: 8402352

Claim:
A method for performing multi-bit error correction based on a BCH code using a processor device, comprising: performing repeatedly the following operations on the BCH code on which error correction is to be performed, including: shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0; calculating syndrome values corresponding to the shifting of the BCH code; determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code; and further including, in the case where the first error number is not equal to 0: calculating modified syndrome values corresponding to the shifting of the BCH code, wherein the modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to an inverse value, determining a second error number in the BCH code under the shifting based on the modified syndrome values corresponding to the shifting of the BCH code, and determining whether the current rightmost bit of the BCH code under the shifting contains an error according to whether the second error number is smaller than the first error number by 1.