Patent ID: 7994476

Claim:
A method for electrically testing a semiconductor wafer, the method comprising: scanning a first de-focused scan area of the wafer by a de-focused charged particle beam along a first de-focused scan line so as to affect a charging of the first de-focused scan area, said de-focused scan area encompassing a first plurality N of focused scan lines; scanning a first number of the plurality of focused scan lines within the de-focused scan area by a focused charged particle beam while detecting electrons scattered from the wafer, said scanning of the first number of focused scan lines following a sequence 1, n+1, 2n+1, . . . <N, where n is such that the charging of a line an+1 does not adversely impact the charging of line (a+1)n+1; wherein, the scanning by the focused charged particle beam along the first number of focused scan lines occurs while the first number of focused scan lines remain affected by charging introduced by the scanning of the first de-focused scan area by the de-focused charged particle beam; scanning a second de-focused scan area of the wafer by the de-focused charged particle beam along a second de-focused scan line so as to affect a charging of the second de-focused scan area, said second de-focused scan area encompassing a second plurality N focused scan lines incremented by one focused scan line from the first plurality N of focused scan lines; scanning a second number of the second plurality of focused scan lines within the second de-focused scan area by the focused charged particle beam while detecting electrons scattered from the wafer, said scanning of the second number of focused scan lines following a sequence different than that used for scanning the first number of focused scan lines; and continuing to iteratively scan the wafer using the de-focused charged particle beam and the focused charged particle beam until to designated portion thereof has been scanned by the focused charged particle beam.