Patent ID: 8524532

Claim:
A method comprising: providing a first field effect transistor (FET) module, the first module comprising a first FET encased in a first dielectric substrate, the first FET having opposing top and bottom surfaces, there being a multiplicity of metallic posts on the top and bottom surfaces of the first FET, the dielectric substrate formed from a first plurality of dielectric layers that are laminated together around the first FET, the first module further comprising a plurality of metallic foil layers including first and second foil layers, the dielectric substrate and the encased first FET being sandwiched between the first and second foil layers; forming a multiplicity of holes through the dielectric substrate and the first and second foil layers to expose the multiplicity of metallic posts on the top and bottom surfaces of the first FET; electroplating a metal into each hole to form a conductive via that electrically connects one of the foil layers with the via, thereby electrically and physically connecting the top surface of the first FET with the second foil layer and the bottom surface of the first FET with the first foil layer; positioning a second FET on the first FET module such that metallic posts on the second FET are electrically and physically connected with at least one of the metallic posts on the first FET via the second foil layer, thereby electrically connecting a drain of the first FET with a source of the second FET; positioning a second plurality of dielectric layers around the second FET; positioning a third foil layer over the second plurality of dielectric substrate and the second FET wherein the second FET, the second plurality of dielectric layers and the third foil layer cooperate to form a second FET module; and laminating the first module and the second module together to form an integrated circuit package.