Patent ID: 7487194

Claim:
A scrambler for scrambling a sequence of n-valued symbols with n≧2, each n-valued symbol able to assume one of n states, into a sequence of scrambled n-valued symbols, comprising: an n-valued Linear Feedback Shift Register (LFSR) in Galois configuration, the n-valued LFSR having an n-valued shift register that includes a plurality of n-valued data storage elements and a first device implementing an n-valued reversible logic function having a first input and an output connected between two directly neighboring n-valued register elements of the plurality of n-valued data storage elements; a second device implementing an n-valued scrambling function with a first input of the second device being connected to an output of the shift register, a second input of the second device able to receive the sequence of n-valued symbols, and an output of the second device being connected to an input of the n-valued shift register and to a second input of the first device; and a scrambler output not being an output of the second device that provides the sequence of scrambled n-valued symbols.