Patent ID: 8531891

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array having an electrically rewritable non-volatile memory cell arranged therein; and a control unit configured to perform controlling of repeating an erase operation to apply an erase pulse voltage to the memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed, the control unit being configured to, when controlling of repeating the erase operation, and the erase verify operation and the step-up operation is performed, generate a first erase pulse voltage in a first one of the erase operations as an initial pulse voltage, and thereafter generate a second erase pulse voltage in a second one of the erase operations, the control unit being configured to control the erase pulse voltage such that: at least a voltage wave shape of the first erase pulse voltage in which a vertical axis thereof denotes a voltage and a lateral axis denotes time has a blunted wave-shape portion that is continuous to a saturation value thereof; the first erase pulse voltage is longer than the second erase pulse voltage with respect to a width of the blunted wave-shape portion; and a gradient of the blunted wave-shape portion of the first erase pulse voltage is such that a gradient at a first point in time is not larger than a gradient at a second point in time before the first point in time through the width of the blunted wave-shape portion.