Patent ID: 8766356

Claim:
A semiconductor device, comprising: a semiconductor substrate having a cell region and a peripheral region; a cell transistor including a cell gate electrode in a gate trench in the semiconductor substrate and first and second cell source/drain regions in the cell region; a peripheral transistor including a peripheral gate electrode and first and second peripheral source/drain regions in the peripheral region; a bit line conductive pattern electrically coupled to the first cell source/drain region; a bit line insulating capping pattern disposed on the bit line conductive pattern; a cell contact structure on the second cell source/drain region; a first conductive pattern on the cell contact structure; and a second conductive pattern electrically coupled to the bit line conductive pattern and the peripheral transistor, wherein an upper surface of the first conductive pattern is disposed at substantially a same height above an upper surface of the bit line insulating capping pattern as an upper surface of the second conductive pattern.