Patent ID: 8050073

Claim:
A semiconductor memory device comprising: a sub memory cell array block having memory cells connected between first and second word lines extending in a first direction and bit lines extending in a second direction perpendicular to the first direction; a first word line driver region disposed at a side of the sub memory cell array block in the first direction, and configured to drive the first word lines; a second word line driver region disposed at another side of the sub memory cell array block in the first direction, and configured to drive the second word lines; a sensing region disposed at a side of the sub memory cell array block in the second direction, and configured to control the bit lines in response to signals transferred through drive signal lines; a first conjunction region disposed at an intersection of the first word line driver region and the sensing region, and including a first drive signal driver configured to drive the drive signal lines in response to signals transferred through control signal lines when the first word line driver region drives the first word lines; and a second conjunction region disposed at an intersection of the second word line driver region and the sensing region, and including a second drive signal driver configured to drive the drive signal lines in response to signals transferred through the control signal lines when the second word line driver region drives the second word lines.