Patent ID: 7518903

Claim:
A semiconductor memory device, comprising: a resistance change memory device with a first node and a second node, for performing a set operation for data and a reset operation for the data by application of a forward bias voltage and a reverse bias voltage across the first and second nodes; a first selection line connected with the first node of the resistance change memory device; a second selection line connected with the second node of the resistance change memory device; a precharge circuit for precharging the first and second nodes of the resistance change memory device to a reference potential when the resistance change memory device is in standby mode; a bias applying circuit for applying a set high potential to one of the first and second nodes of the resistance change memory device and a set low potential to the other of the first and second nodes when the set operation for writing the data is performed, and applying the set low potential to the one node of the resistance change memory device and the set high potential to the other node when the reset operation for the written data is performed; and a read circuit for applying the reference potential to the first or second node of the resistance change memory device when a read operation for reading the data is preformed.