Patent ID: 8410526

Claim:
A semiconductor integrated circuit device comprising: a first diffusion layer of a P-type arranged in a P-type semiconductor region in a semiconductor substrate so as to extend in a first direction, and configured to supply a first potential; a second diffusion layer of an N-type arranged in an N-type semiconductor region in the semiconductor substrate so as to extend in the first direction, and configured to supply a second potential higher than the first potential; a standard cell arranged between the first and second diffusion layers in a plan view, including an N-channel type transistor having a pair of third diffusion layers and a gate electrode arranged between the pair of third diffusion layers in plan view, and a P-channel type transistor having a pair of fourth diffusion layers and a gate electrode arranged between the pair of fourth diffusion layers in plan view; and a first wiring line provided in a first layer of wiring lines and connecting one of the pair of third diffusion layers to one of the pair of fourth diffusion layers, wherein a width along a second direction perpendicular to the first direction, in a plan view between a center of the first diffusion layer along the second direction and a center of the second diffusion layer along the second direction, is equal to (N+0.5) times a wiring pitch of a second layer of wiring lines higher than the first layer of wiring lines with respect to the semiconductor substrate, N representing an integer value.