Patent ID: 8839057

Claim:
An integrated circuit comprising: a plurality of memory units; at least one memory test module, each memory test module having at least one associated memory unit from said plurality of memory units; each memory test module comprising: a set of test registers for each associated memory unit; a test engine is configured, for each associated memory unit, to perform a test operation on that associated memory unit dependent on the status of the set of test registers provided for that associated memory unit; a transaction interface for receiving a transaction specifying a register access operation, the transaction providing a first address portion and a second address portion, the first address portion having encodings allowing individual memory units to be identified and groups of memory units to be identified, and the second address portion identifying one of the test registers within said set to be an accessed register for the register access operation; and a decode circuitry is configured to selectively perform the register access operation in response to the transaction by: (i) if an individual memory unit is identified by the first address portion, then determining whether that individual memory unit is one of said at least one associated memory units and, if so, performing the register access operation on the accessed register within the set of test registers provided for that individual memory unit; and (ii) if a group of memory units is identified by the first address portion, then determining whether any of said at least one associated memory units is a memory unit within said group, and, if so, performing the register access operation on the accessed register within the set of test registers provided for each associated memory unit within said group.