Patent ID: 8542033

Claim:
A domino logic circuit comprising: a first evaluation unit configured to precharge a first dynamic node and configured to discharge a footer node in a first phase of a clock signal, and configured to evaluate a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal; a second evaluation unit connected to the first dynamic node and the footer node, the second evaluation unit configured to precharge a second dynamic node in the first phase of the clock signal, and configured to determine a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal; and an output unit connected to the first and second dynamic nodes, the output unit configured to provide an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node, wherein the second evaluation unit includes, a first p-type metal-oxide semiconductor (PMOS) transistor, the first PMOS transistor connected to a power supply voltage and the second dynamic node, the first PMOS transistor configured to precharge the second dynamic node in response to the clock signal, a first n-type metal-oxide semiconductor (NMOS) transistor having a drain connected to the second dynamic node, a gate connected to the footer node, a second NMOS transistor having a drain connected to a source of the first NMOS transistor, a source connected to a ground voltage and a gate configured to receive the clock signal, a third NMOS transistor having a drain connected to the footer node, a source connected to the ground voltage and a gate connected to the second dynamic node, and a second PMOS transistor having a source connected to the first dynamic node, a gate connected to the footer node and a drain connected to the second dynamic node.