Patent ID: 8129790

Claim:
A semiconductor device comprising: a logic region; and an SRAM region in which SRAM nFETs and SRAM pFETs are formed, the logic region including a pFET region and an nFET region the pFET region including a substrate; an epitaxial layer on the substrate, wherein pFETs are formed in the epitaxial layer; the nFET region including a substrate; a buried oxide layer on the substrate; a silicon layer on the buried oxide layer, wherein nFETs are formed in the silicon layer; the SRAM region including a substrate; a buried oxide layer on the substrate; a silicon layer on the buried oxide layer, wherein the SRAM pFETs and the SRAM nFETs are formed in the silicon layer, such that the SRAM pFETs and the SRAM nFETs are positioned above the buried oxide layer of the SRAM region, wherein the SRAM pFETs and the SRAM nFETs are separated by shallow trench isolation, wherein the shallow trench isolation extends at least to a top of the buried oxide layer and not extend to the substrate, and wherein a top dimension of the shallow trench isolation is smaller than that of the epitaxial layer.