Patent ID: 8321747

Claim:
A QC-LDPC code decoder, comprising: a general-purpose processor configured for: distributing storage space for data memory area based on the structure of the QC-LDPC code check matrix; establishing an index for data addressing; controlling the QC-LDPC code decoding process; scheduling information processing operations during the decoding process; and realizing part of the information processing operations during the decoding process including parity check, check node updating, and variable node updating; a data memory area configured for storing the information needed for the decoding process block by block, wherein the information includes initial information of the variable nodes, check node information and variable node information during iteration; and a hardware accelerator configured for conducting all or part of the information processing operations during the decoding process including parity check, check node updating, and variable node updating, and wherein, when the hardware accelerator is used to accomplish part of the information processing functions during the decoding process including parity check, check node updating, and variable node updating, the remaining information processing functions are completed by the general-purpose processor.