Patent ID: 8379461

Claim:
A data cache in a memory device comprising: a plurality of dynamic data caches configured to store multi-level data and coupled to a data cache input; a first primary data cache coupled to the data cache input and configured to store data sensed from memory cells coupled to a first plurality of data lines of the memory device; a second primary data cache coupled to the data cache input and configured to store data sensed from memory cells coupled to a second plurality of data lines of the memory device; a first secondary data cache coupled to the data cache input and configured to store data input for programming to the memory cells coupled to the first plurality of data lines; a second secondary data cache coupled to the data cache input and configured to store data input for programming to the memory cells coupled to the second plurality of data lines; and wherein the first primary data cache, the first secondary data cache, and at least two of the dynamic data caches are configured to be selectively coupled through the data cache input to a data line of the first plurality of data lines of the memory device and the second primary data cache, the second secondary data cache, and remaining dynamic data caches are configured to be selectively coupled through the data cache input at a different time to a data line of the second plurality of data lines of the memory device.