Patent ID: 8101436

Claim:
A testing method of a plurality of integrated circuit chips formed on a semiconductor substrate, wherein the testing method comprises: adhering a rear surface of the semiconductor substrate, which opposes a surface on which the plurality of integrated circuit chips are formed, to a plate-shaped jig by at least one adhesive layer formed over at least an entire region in which integrated circuit elements are arranged; cutting the semiconductor substrate by cutting means to separate the plurality of integrated circuit elements into individual separated integrated circuit elements, the cut semiconductor substrate being adhered on the jig by the adhesive layer; aligning the semiconductor substrate adhered on the jig with a probe positioned in a space above the jig; and testing electrical characteristics of the separated integrated circuit elements while the probe is in contact with electrode pads of the separated integrated circuit elements; wherein the plate-shaped jig used in the testing method has a thermal expansion coefficient that is less than or substantially equal to a thermal expansion coefficient of the semiconductor substrate to reduce positional shift between the separated integrated circuit elements caused by heating of the separated integrated circuit elements during testing of the separated integrated circuit elements.