Patent ID: 7739324

Claim:
An integrated circuit (IC) design tool for synthesizing logic for a sum-of-products functional block in response to a description of a sum-of-products function, the IC design tool comprising: instructions stored in a storage device that when executed by a processor provide one or more software modules to synthesize a gate-level netlist of a sum of products functional block including a partial products generator to multiply bits of a first vector and a second vector together to generate partial product terms, a partial product reduction tree coupled to the partial products generator, the partial products reduction tree to reduce bit-vectors of the sum-of-products function down to a pair of final vectors, the synthesis of the partial product reduction tree responsive to a comparison gate delay and expected arrival times of the partial product terms in each bit vector, and an adder coupled to the partial product reduction tree to receive the pair of final vectors, the adder to add the pair of final vectors together to generate a final result for the sum-of-products functional block.