Patent ID: 7590027

Claim:
A nonvolatile semiconductor device comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines; a data program control section which programs a plurality of first multi-bits data each having a first number of bits, or a plurality of second multi-bits data each having a second number of bits twice that of said first multi-bits data, to said plurality of memory cell arrays; a page buffer circuit which stores said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said word lines from said plurality of memory cell arrays; a data transfer section which transfers said plurality of first multi-bits data or said plurality of second multi-bits data which is read for each of said second number of bits from said page buffer circuit synchronized with a second clock signal having a cycle which is twice that of a first clock signal; and a data output section which receives said data from said data transfer section and outputs externally said data in synchronization with said first clock signal.