Patent ID: 8554161

Claim:
A circuit for biasing a gallium arsenide (GaAs) power amplifier, comprising: a reference voltage generator circuit implemented in a gallium arsenide (GaAs) material system and configured to translate an input voltage to thereby provide an output voltage having a greater voltage level than that of the input voltage, the reference voltage regulator circuit further configured to provide temperature and process compensation; and a field effect transistor (FET) bias circuit implemented in the gallium arsenide material system and adapted to receive an output of the reference voltage generator circuit and adapted to provide an output to a radio frequency (RF) amplifier stage, the reference voltage generator circuit including a first bipolar transistor adapted to compensate for temperature variations in a second bipolar transistor located in the FET bias circuit, a first field effect transistor (FET) adapted to compensate for temperature and process variations in a second FET located in the FET bias circuit, and a third FET adapted to compensate for temperature and process variations in a fourth FET located in the reference voltage generator circuit, the fourth FET having a negative turn on voltage.