Patent ID: 8274849

Claim:
A method of reading a memory cell comprising: applying read control signals to a selected memory cell of a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell of the plurality of memory cells comprises an electrically floating body transistor including a body region which is electrically floating and configured to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state representative of a second charge in the body region of the electrically floating body transistor; generating a current on a bit line coupled to the selected memory cell in response to the read control signals, wherein the current is representative of a data state stored in the selected memory cell; controlling the generated current on the bit line by the selected memory cell by sinking or sourcing at least a portion of the current on the bit line generated by the selected memory cell; sensing a first voltage potential on the bit line to determine the data state stored in the selected memory cell based at least in part on a reference signal and the first voltage potential on the bit line, wherein sinking or sourcing at least a portion of the current on the bit line generated by the selected memory cell includes sinking or sourcing a substantial portion of the current on the bit line generated by the selected memory cell after sensing the first voltage potential on the bit line; and outputting a data state signal which is representative of the data state stored in the selected memory cell.