Patent ID: 7462941

Claim:
An integrated circuit comprising: first solder bumps coupled to receive a first power supply voltage; second solder bumps coupled to receive a second power supply voltage; a first conductive layer having first traces electrically connected to the first solder bumps and having second traces electrically connected to the second solder bumps, wherein the first traces are interleaved between the second traces such that at least one of the first traces is located in between two of the second traces, and at least one of the second traces in located in between two of the first traces; and a second conductive layer comprising first conductive pads electrically connected to the first solder bumps and second conductive pads electrically connected to the second solder bumps; the second conductive layer further including first conductive fingers electrically connected to the first conductive pads and extending outwardly from the first conductive pads and second conductive fingers electrically connected to the second conductive pads and extending outwardly from the second conductive pads; first vias extending from the first conductive fingers to the first traces and second vias extending from the second conductive fingers to the second traces; each. of the first conductive fingers and the second conductive fingers including four conductive fingers per conductive pad an the fingers are arranged such that two fingers extend outwardly in opposite directions along a first axis and two other fingers extend outwardly in opposite directions along a second axis; and wherein the second axis is substantially perpendicular to the first axis.