Patent ID: 8158498

Claim:
A method of fabricating a p-channel MOS transistor, comprising the steps of: forming a gate electrode on a silicon substrate in correspondence to a channel region via a gate insulation film; forming sidewall insulation films on respective sidewall surfaces of said gate electrode; and forming a source region and a drain region of p-type in said silicon substrate at respective outer sides of said sidewall insulation films, said step of forming said source region and drain region of p-type comprising the steps of: forming first and second regions in an amorphous state; crystallizing said first and second regions to convert said first and second regions to first and second polycrystalline regions, respectively, accumulating therein a compressive stress; and forming the source region and drain region around first and second polycrystalline regions, respectively, such that the source region and drain region enclose the first and second polycrystalline regions, respectively, wherein the first and second regions are formed on a portion that is lower than an upper surface of the silicon substrate on which the gate insulation film is formed.