Patent ID: 7224736

Claim:
In a digital display device including a clock recovery system for recovering a system time clock reference from a video bit-stream generated at an encoder to produce a decoder system clock frequency, and a decoding system for decoding and decompressing the video bitstream at a frame rate, an adaptive clocking mechanism for said decoding system comprising: means for extracting from said video bit stream attributes of a video format transmitted via said bitstream; selecting means, cooperatively linked with said decoding system, for selecting a modifier from a group of modifiers based on video format attributes derived from said video bit-stream; and modifying means, cooperatively linked with said selecting means and said decoding system, for modifying a synchronization timing parameter of said decoding system with said selected modifier prior to decoding said video bit-stream, wherein the group of modifiers includes the ratios 1/1, 1000/1001, and 1001/1000.