Patent ID: 8842483

Claim:
A semiconductor device comprising: a plurality of memory cells each connected to a bit line or a complementary bit line; a sense amplifier connected between the bit line and the complementary bit line; a first power supply circuit positioned between a power supply voltage and a first node of the sense amplifier, and configured to select between supplying a power supply voltage to the first node and blocking the power supply voltage from the first node in response to a first control signal; a second power supply circuit positioned between a ground voltage and a second node of the sense amplifier, and configured to select between supplying a ground voltage to the second node and blocking the ground voltage from the second node in response to a second control signal; and at least a first boosting circuit configured to, during a precharge operation of the memory cells, boost a voltage at the first node or the second node in response to a third control signal when the power supply voltage is lower than a first predetermined voltage.