Patent ID: 7042033

Claim:
An MOS transistor formed on a semiconductor substrate of a first conductivity type comprising: (a) an interfacial layer formed on the substrate; (b) a high dielectric constant layer formed on the interfacial layer that comprises a material that is selected from the group consisting of Ta 2 O 5 , Ta 2 (O 1−x N x ) 5 wherein x ranges from greater than 0 to 0.6, a solid solution of (Ta 2 O 5 ) r —(TiO 2 ) 1−r wherein r ranges from about 0.9 to less than 1, a solid solution (Ta 2 O 5 ) s —(Al 2 O 3 ) 1−s wherein s ranges from 0.9 to less than 1, a solid solution of (Ta 2 O 5 ) t —(ZrO 2 ) 1−t wherein t ranges from about 0.9 to less than 1, a solid solution of (Ta 2 O 5 ) u —(HfO 2 ) 1−u wherein u ranges from about 0.9 to less than 1, and mixtures thereof wherein the interfacial layer separates the high dielectric constant layer from the substrate; (c) a gate electrode having a width of less than 0.3 micron covering the high dielectric constant layer; (d) first and second lightly doped regions of a second conductivity type disposed on respective areas of the substrate surface; (e) a source and drain regions of a second conductivity type; (f) a pair of first non-conductive spacers formed adjacent to the gate electrode and formed on the high dielectric constant layer; and (g) a pair of second non-conductive spacers that are adjacent to the first spacers and the high dielectric constant layer and are formed on the interfacial layer.