Patent ID: 6956861

Claim:
An interconnect structure comprising a plurality of input ports, a plurality of output ports, a switch S 1 and a plurality of shared buffers SB N−1 so that a payload of a message M entering the interconnect structure through an input port in serial fashion passes through the switch S 1 in serial fashion and enters the shared buffers SB N−1 in serial fashion with the switch S 1 delivering different portions of the payload of message M to different shared buffers SB N−1 of the said plurality of shared buffers SB N−1 ; wherein a portion of the payload of a message M 1 is delivered to a shared buffer SB j at the same time that a portion of a message M 2 is delivered to a shared buffer SB k , where each of J and K is an integer in the range 0 to N−1; and wherein the payload of message M is decomposed into flits with the flits passing through the switch S 1 in such a way that the flits enter the shared buffers SB N−1 in round robin fashion.