Patent ID: 8063686

Claim:
A phase interpolator system comprising: a phase generator to selectively generate one or more pairs of consecutive phase clocks in response to a pair of orthogonal reference clocks; a control signal decoder coupled to the phase generator, the control signal decoder to selectively generate N phase one control signals and (M−N) phase two control signals in response to the one or more pairs of consecutive phase clocks and an advance or retard signal; and at least one sample clock generator including an integrating capacitor, M current sources selectively coupled to the integrating capacitor, wherein N of the M current sources are selectively coupled to the integrating capacitor in response to the N phase one control signals to charge the integrating capacitor over one of a plurality of slopes and (M−N) of the M current sources are further selectively coupled to the integrating capacitor in response to the (M−N) phase two control signals to charge the integrating capacitor over a constant slope, and an inverter coupled to the integrating capacitor, the inverter to detect a voltage level across the integrating capacitor greater than or equal to an inverter switching threshold level and generate a first edge of a sample clock output signal with a selected phase delay in response thereto.