Patent ID: 8261134

Claim:
A multiprocessor computer system, comprising: a memory system; a requesting processor that sends a plurality of memory operation requests in a plurality of outgoing request packets to the memory system, wherein each of the plurality of request packets includes a header and one of the plurality of memory operation requests, wherein each header includes a packet identifier, and wherein the memory system generates a response packet for successful ones of the plurality of memory operation requests; a plurality of watchdog timers each operable to detect failure of a memory operation request of one of the plurality of memory operation requests based on a timeout passage of a certain timing period from the memory operation request being issued without a valid response before the timeout passage of the certain timing period; an outstanding request buffer (ORB) that includes a plurality of outstanding request buffer (ORB) entries, wherein each one of the plurality of ORB entries is associated with one of the plurality of watchdog timers such that the timeout passage of the certain timing period of the associated watchdog timer indicates a failure of the memory operation request of the associated ORB entry; and an error handler operable to take corrective action regarding each failed memory operation request, the error handler operable, after one of the plurality of memory operation requests has timed out, to interrogate the outstanding request buffer to determine which memory operation request has timed out; wherein at least a portion of the watchdog timer and error handler are implemented in hardware or a tangible machine-readable medium.