Patent ID: 7966592

Claim:
A method to analyze timing in a circuit, comprising the steps of: (A) simulating a reception of both an input signal and a clock signal at a first flip-flop, wherein (i) said input signal has a latest transition, (ii) said input signal arrives through a first path of said circuit and (iii) said clock signal has an active edge; (B) calculating, using a processor, a first value of a time difference between said latest transition and said active edge; (C) calculating a first delay between said active edge and said latest transition appearing in an output signal of said first flip-flop, wherein (i) said first delay is based on a model responding to said first value, (ii) said model characterizes a clock-to-output delay of said first flip-flop as a function of said time difference and (iii) said characterization covering a range of values; (D) calculating a first arrival time of said latest transition in said output signal at a second flip-flop, wherein said second flip-flop is connected to said first flip-flop through a second signal path; and (E) storing said first arrival time in a recording medium.