Patent ID: 8566515

Claim:
A memory subsystem comprising: a memory; and a memory controller that provides one or more data-stream interfaces coupled to receive a data-stream input that includes a plurality of data organized according to a predetermined data structure, provides a random-access interface to individual memory cells and to two-dimensional memory regions within the memory, each individual memory cell and each two-dimensional memory region being associated with a (x, y) coordinate pair that describes a corresponding location within the memory, arbitrates among the data-stream interfaces and random-access interface to serialize concurrently requested memory accesses received through the data-stream interfaces and random-access interface, carries out memory accesses requested through the data-stream interfaces by writing the data-stream input to the memory, and carries out single-memory-cell and two-dimensional-memory-cell-region memory accesses requested through the random-access interface by reading values from, or writing values to, the individual memory cells and the two-dimensional memory-cell regions in the memory.