Patent ID: 7310748

Claim:
A memory hub, comprising: a test command interface for coupling to a test bus and through which test command packets are received, the test command interface configured to latch the test command packets in response to a test clock signal having a test clock frequency; a memory device interface for coupling memory device command, address and data signals to a memory device, the memory device interface configured to provide the memory device command, address and data signals to the memory device in response to a memory device clock signal having a memory device clock frequency; a test command latch coupled to the test command interface and the memory device interface to latch a memory device command of a received test command packet and provide memory device command signals to the memory device in accordance with the memory device command to test the memory device; a test address generator coupled to the test command interface and the memory device interface to generate the memory device address signals for the memory device in accordance with the received test command packet; a test data generator coupled to the test command interface and the memory device interface to generate the memory device data signal for the memory device in accordance with the received test command packet; and an error detect circuit coupled to the test bus and configured to compare expected data corresponding to the memory device data signal and data read from the memory device and further configured to provide a signal indicative of the results from the comparison over the test bus.