Patent ID: 7257671

Claim:
A content addressable memory comprising: a plurality of word memories which respectively have assigned addresses, and each outputs a match/mismatch signal representing storage or no storage of a data item matching search data, in a search mode; and a priority circuit for changing the priority of the addresses which are to be output prior to the other addresses, wherein said priority circuit comprises: a priority encoder for outputting the addresses of the word memories from which the match signals are transmitted to the priority encoder in the search mode, in a predetermined fixed priority order; a first prior word-memory setting section for setting a first prior word memory among said plurality of word memories; and a priority changing part for masking the match signals output from upper-positional word memories, which include the word memories having upper positions compared with the first prior word memory in the fixed priority order in said priority encoder, and for transmitting to the priority encoder signals representing that the upper-positional word memories output no match signals, while transmitting to said priority encoder the match signals output from lower-positional word memories which include the first prior word memory and the word memories having lower positions compared with the first prior word memory in the fixed priority order.