Patent ID: 7143206

Claim:
A data transfer control system comprising: a channel control unit configured to be connected to an external device; a cache memory connected to the channel control unit; and a storage device control unit connected to the cache memory, the storage device control unit being configured to be connected to at least one storage device; wherein the channel control unit includes: a communication interface configured to be connected to the external device; a buffer memory; a local memory; a processor connected to the local memory; a DMA processor comprising a register whose access time is longer than access time of the local memory, and the DMA processor is connected with the processor via a bus and connected to the buffer memory; wherein the processor is configured to write data transfer information into the local memory based on a data transfer request from the external device, the data transfer information including a first address of the buffer memory and a second address of the cache memory which are to be set in the register of the DMA processor; and the DMA processor is configured to read the data transfer information from the local memory, to set the first and second addresses included in the data transfer information in the register of the DMA processor, and to transfer directly either data stored in the first address of the buffer memory into the second address of the cache memory or data stored in the second address of the cache memory into the first address of the buffer memory, according to the data transfer information.