Patent ID: 7969197

Claim:
An output buffer circuit comprising: one or more inverters; a delay circuit for delaying an input signal for a specific time; one or more buffers; a function for transmitting a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages; and a means for making a preemphasis amount variable and an ON resistance of the buffer constant, wherein the output buffer circuit further includes switches, and wherein two or more of the buffers are redundantly connected in parallel with one another, and the number of the buffers that concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers; and, by selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selection signal for selector logic, so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.