Patent ID: 7408819

Claim:
A memory device, including: a matrix of memory cells structured to store data and arranged in a plurality of bit lines, the bit lines extending along a first direction; a page buffer structured to interface the matrix with a downstream circuitry, the page buffer comprising a plurality of read/program units, each read/program unit being associated with and operatively couplable to at least one bit line; at least two groups each including at least two respective read/program units, wherein the read/program units of a generic one of said groups are generically aligned along the first direction, said at least two groups being generically aligned along a second direction transversal to the first direction; a plurality of signal tracks respectively associated with said groups, for conveying signals corresponding to data read from the memory cells to the downstream circuitry, each signal track being shared by the at least two read/program units of the associated group; and means for selectively assigning each signal track to one of the associated read/program units at a time among the at least two read/program units of the group associated with said signal track.