Patent ID: 7071068

Claim:
A method for fabricating a transistor, comprising: forming a device isolation oxide film for defining a groove which corresponds to an active region at the upper portion of a semiconductor substrate; forming a gate oxide film in a central portion of the active region of the semiconductor substrate, wherein the gate oxide film is separated from the device isolation film; forming a first gate electrode on the gate oxide film; forming a first oxide film at side walls of the first gate electrode; forming a lightly doped drain (LDD) region in the active region at both sides of the first gate electrode; forming nitride spacers at both sides of the first gate electrode and at side walls of the device isolation film; forming a source/drain junction region in the semiconductor substrate at both sides of the first gate electrode including the nitride spacers; forming a second oxide film and a planarized third oxide film between the first gate electrode and the device isolation film, wherein the third oxide film fills the space over the active region between the first gate electrode and the device isolation film; and forming a gate electrode having a stacked structure of the first gate electrode, a second gate electrode and a hard mask layer, by forming the second gate electrode and the hard mask layer on the first gate electrode.