Patent ID: 7294855

Claim:
A thin film transistor array panel comprising: a gate conductive layer formed on an insulating substrate; a gate insulating layer on the gate conductive layer; a semiconductor layer on the gate insulating layer; a data conductive layer formed at least in part on the semiconductor layer and comprising a source electrode and a drain electrode separated from each other; a passivation layer formed on the data conductive layer; and an IZO conductive layer formed on the passivation layer, wherein at least one of the gate conductive layer and the data conductive layer includes a dry-etchable lower film and an upper film formed on the lower film, the upper film including Al or Al alloy and having edges located on the lower film, the IZO conductive layer contacts the lower film and a top surface of the upper film, and the semiconductor layer has substantially the same planar shape as the data conductive layer except for a portion located between the source electrode and the drain electrode.