Patent ID: 7456661

Claim:
A circuit for a phase/frequency-locked loop comprising: a frequency-generating oscillator; and a phase/frequency comparator having two edge-triggered storage devices including a first edge-triggered storage device set by an edge of a reference-frequency signal and a second edge-triggered storage device set by an edge of an output-frequency signal from the phase/frequency locked loop, the two edge-triggered storage devices are each reset by a resetting signal that is output from a resetting logic unit, the two edge-triggered storage devices have output signals that are connected to the frequency-generating oscillator, said resetting logic unit having inputs that are supplied with the output signals from the two edge-triggered storage devices, wherein the resetting signal from the resetting logic unit is only activated when both the output signals from the two edge-triggered storage devices have been activated, and is only de-activated when both the output signals from the two edge-triggered storage devices have been deactivated, wherein the resetting logic unit includes an asynchronous level-triggered RS storage device of inverse logic, the resetting input of the asynchronous level-triggered RS storage device having an output signal from an OR gate supplied to it, and wherein the two edge-triggered storage devices each have only a single output, the single output of each of the two edge-triggered storage devices being of non-inverted logic.