Patent ID: 7130208

Claim:
A ferroelectric-type nonvolatile semiconductor memory comprising a first memory unit and a second memory unit; said first memory unit having; a first bit line, a first transistor for selection, first sub-memory units which are N in number (N≧2) and each of which is composed of memory cells which are M in number (M≧2), and plate lines which are M×N in number, and said second memory unit having; a second bit line, a second transistor for selection, second sub-memory units which are N in number and each of which is composed of memory cells which are M in number, and the plate lines which are M×N in number from said first memory unit being shared with the second memory unit, wherein the first sub-memory unit of an n-th layer (n=1, 2 . . . , N) and the second sub-memory unit of the n-th layer are formed on a same insulating layer, the first sub-memory unit of an n′-th layer (n′=2 . . . N) and the second sub-memory unit of the n′-th layer are stacked on the first sub-memory unit of the (n′−1)-th layer and the second sub-memory unit of the (n′−1)-th layer with an insulating layer therebetween, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have a same thermal history with regard to their production processes, the memory cells constituting the first sub-memory unit of the n-th layer and the memory cells constituting the second sub-memory unit of the n-th layer have the thermal history different from a thermal history of memory cells constituting the first sub-memory unit of a k-th layer (k≠n) and the memory cells constituting the second sub-memory unit of the k-th layer, the memory cell in the m-th-place constituting the first sub-memory unit of the n-th layer in the first memory unit and memory cell in the m-th-place constituting the second sub-memory unit of the n-th layer in the second memory unit form a pair to store data of 1 bit each, a reference potential having an n-th potential is provided to the second bit line when data stored in the memory cell constituting the first sub-memory unit of the n-th layer in the first memory unit is read out, a reference potential having an k-th potential is provided to the first bit line when data stored in the memory cell constituting the second sub-memory unit of the k-th layer in the second memory unit is read out, and the n-th potential differs from the k-th potential (k≠n).