Patent ID: 6930499

Claim:
A method of manufacturing an integrated circuit ( 404 ) on a die ( 402 ) that is formed as a detachable part of a wafer ( 401 ) comprising a plurality of dies ( 402 ) that are separated from each other by dicing lanes ( 403 ), which method comprises a step of providing a metallization pattern ( 407 ) in at least one of the dicing lanes ( 403 ) so as to form a communication bus comprising at least one communication bus circuit ( 405 ) that forms part of the integrated circuit ( 404 ), which step is followed by a step wherein the integrated circuit ( 404 ) is tested in accordance with a predetermined testing method that utilizes the communication bus circuit ( 405 ) for communication with the integrated circuit ( 404 ), after which a step is carried out wherein the die ( 402 ) is detached from the wafer ( 401 ), characterized in that the communication bus circuit ( 405 ) is embodied so as to be able to communicate in a wafer test mode as well as in a functional mode, and said communication bus circuit communicates in the wafer test mode during the testing of the integrated circuit ( 404 ).