Patent ID: 7870525

Claim:
A system for improving a probability of an integrated circuit (IC) design meeting timing requirements, the system comprising: a) means for determining a reference slack using a reference run, and determining a sensitivity of slack to a variation in at least one parameter for each of a plurality of timing endpoints of the design; b) means for calculating a failure coefficient from the reference slack and the sensitivity of slack for each of the timing endpoints; wherein the failure coefficient calculating means and the threshold test determining means include means for: calculating a worst case slack for each timing endpoint, wherein the worst case slack calculating means calculates the worst case slack by one of: determining a difference between a nominal slack and a multiple (Y) of a sum over all parameters of an absolute value of standard deviation, and determining a difference between a nominal slack and a multiple (Y) of a root sum square over all parameters of an absolute value of standard deviation, and determining whether a parameter distribution is Gaussian or non-Gaussian; c) means for determining whether each timing endpoint fails a threshold test; d) means for prioritizing any timing endpoints that fail the threshold test according to respective failure coefficients; and e) means for modifying the design to improve a slack of at least one of the timing endpoints.