Patent ID: 8058901

Claim:
An electronic latch comprising: a first circuit configured to drive a first output to a first output logic level when a first input is at a first input logic level and a second input is at the first input logic level, drive the first output to a second output logic level different from the first output logic level when the first input is at a second input logic level and the second input is at the second input logic level, and set the first output to a high impedance state when different input logic levels are applied to the first input and to the second input; a second circuit configured to drive a second output to the first output logic level when a third input is at the first input logic level and a fourth input is at the first input logic level, drive the second output to the second output logic level when the third input is at the second input logic level and the fourth input is at the second input logic level, and set the second output to the high impedance state when different input logic levels are applied to the third input and to the fourth input; and a third circuit configured to maintain voltage levels of the first and second outputs when the first circuit drives the first output to the high impedance state, and the second circuit drives the second output to the high impedance state, wherein the third circuit comprises a plurality of P-channel transistors.