Patent ID: 8258576

Claim:
A semiconductor device comprising: a semiconductor substrate including a first active region of a first conductivity type, a second active region of a second conductivity type, and an isolation region; a first MOS transistor including a first gate electrode structure formed on said first active region, first source/drain regions of the second conductivity type formed in said first active region on both sides of said first gate electrode structure, a first channel region under said first gate electrode structure, recesses dug from surfaces of said first source/drain regions, and semiconductor buried regions of the second conductivity type formed in said recesses and applying stress to the first channel region, said semiconductor buried regions having surfaces at a level higher than a surface of said semiconductor substrate; a second MOS transistor including a second gate electrode structure formed on said second active region, second source/drain regions of the first conductivity type formed in said second active region on both sides of said second gate electrode structure, a second channel region under said second gate electrode structure, semiconductor epitaxial layers of the first conductivity type formed on said second source/drain regions without involvement of recesses; first source/drain extension regions formed in said first active region on both sides of said first gate electrode structure and between said first source/drain regions and the first channel region; second source/drain extension regions formed in said second active region on both sides of said second gate electrode structure and between said second source/drain regions and the second channel region; first side wall spacers formed on side walls of said first gate electrode structure and formed above said first source/drain extension regions; second side wall spacers formed on side walls of said second gate electrode structure and formed above said second source/drain extension regions; third side wall spacers formed on said first side wall spacers and partially covering said semiconductor buried regions; fourth side wall spacers formed on said second side wall spacers and partially covering said semiconductor epitaxial layers; and silicide regions formed on said semiconductor buried regions not covered with said third side wall spacers and on said semiconductor epitaxial layers not covered with said fourth side wall spacers, wherein said semiconductor buried regions are formed between said first source/drain extension regions and the isolation region.