Patent ID: 7964458

Claim:
A method, comprising: forming a first implantation mask comprising a specified first intrinsic stress above a semiconductor device, said first implantation mask covering a first region comprising a first gate electrode formed in a semiconductor layer of said semiconductor device and exposing a second region comprising a second gate electrode formed in said semiconductor layer of said semiconductor device; implanting a dopant species of a second conductivity type into said exposed second region adjacent to said second gate electrode while said first region is covered by said first implantation mask; annealing said first and second regions with said first implantation mask in place; forming a second implantation mask comprising a specified second intrinsic stress, said second implantation mask covering said second region and exposing said first region; introducing dopant species of first conductivity type into said exposed first region adjacent to said first gate electrode; and annealing said first region in the presence of at least a stressed portion of said second implantation mask.