Patent ID: 7521957

Claim:
An impedance controller, comprising: an impedance control transistor array that generates, from a code, a generated impedance at a predetermined node; a first determination unit that determines two candidate codes for matching the generated impedance to a reference impedance; and a second determination unit that determines which one of the two candidate codes is a final code that best matches the generated impedance to the reference impedance; wherein the first determination unit includes: a comparator for comparing a generated voltage at the predetermined node to a reference voltage; a code generator that generates the code depending on an output of the comparator; and a first controller that determines the two candidate codes depending on a bit-pattern of the output of the comparator; and wherein the second determination unit includes: a fine tuning unit that is activated by the first controller to adjust a respective effective impedance at the predetermined node for each of the two candidate codes; a second controller for determining the final code depending on a respective output of the comparator for each of the two candidate codes with the fine tuning unit being activated; and a register for storing the final code.