Patent ID: 7777253

Claim:
A field-effect semiconductor device comprising: (a) a main semiconductor region having a first and a second layer of dissimilar semiconducting materials such that a two-dimensional carrier gas layer is generated along a heterojunction therebetween, the main semiconductor region having a major surface defined by the second layer; (b) a source electrode on the major surface of the main semiconductor region; (c) a drain electrode on the major surface of the main semiconductor region spaced from the source electrode; (d) an insulator placed between the source electrode and the drain electrode on the major surface of the main semiconductor region with spacings from both electrodes, the insulator being made from a material capable of developing a stress to reduce carrier concentration in the two-dimensional carrier gas layer in the main semiconductor region; (e) a gate electrode on the insulator for control of conduction between the source electrode and the drain electrode; and (f) a piezoelectric layer intermediate the gate electrode and the insulator, the piezoelectric layer being made from a material such that a strain is developed in response to a voltage applied to the gate electrode for offsetting the stress developed by the insulator.