Patent ID: 7774574

Claim:
An integrated circuit comprising: a processor operable to issue memory access requests, each memory access request identifying an address in memory to which the request is directed; at least one on-chip resource falling within the address space addressable by the processor; an interface for directing packets off-chip and addressable within the address space of the processor; and a request directing unit for receiving said memory access requests and directing them in accordance with a selected one of first and second address maps, wherein said first address map has a first range of addresses allocated to said at least one on-chip resource and a second range of addresses allocated to said interface, and in said second memory address map said first range of addresses are also allocated to the interface, and wherein said interface comprises at least one chip-side port for transmitting memory access requests in parallel across a plurality of pins, and first and second circuit-side ports each with a reduced number of pins for communicating said packets off-chip.