Patent ID: 7523229

Claim:
An information processing apparatus that executes a plurality of processes concurrently, the information processing apparatus comprising: a processor that executes each of the processes in either one of a privileged mode and a user mode; a memory device; an I/O controller that is connected to the memory device via an I/O bus, the I/O controller controlling an I/O device and being provided with a first register that is mapped to address space accessible by a user process operating in the user mode, and a second register that is mapped to address space accessible by a privileged process operating in the privileged mode; a direct memory access controller that is installed in the I/O controller and performs data transfer between the I/O device and the memory device based on data transfer control information that is set in the first register by the user process; and an access control unit that is installed in the I/O controller and is placed between the direct memory access controller and the I/O bus, the access control unit limiting data transfer operation of the direct memory access controller based on an address output from the direct memory access controller and access control information set in the second register by the privileged process and disabling the direct memory access controller from accessing any area other than a predetermined area in the memory device that is accessible by the user process.