Patent ID: 8319519

Claim:
An impedance code generation circuit comprising: an impedance unit configured to drive a calibration node to a first level by using an impedance value determined by an impedance code; a code generation unit configured to generate the impedance code so that a voltage of the calibration node has a voltage level between a first reference voltage and a second reference voltage; and a reference voltage generation unit configured to generate the first reference voltage and the second reference voltage in response to the impedance code, wherein the code generation unit comprises: a first comparator configured to compare the first reference voltage with the voltage of the calibration node and generate a first comparison signal; a second comparator configured to compare the second reference voltage with the voltage of the calibration node and generate a second comparison signal; a hold signal generation unit configured to activate a hold signal when the first comparison signal and the second comparison signal have different logic levels; and a counter configured to generate the impedance code in response to the first comparison signal or the second comparison signal, and fix the value of the impedance code when the hold signal is activated.