Patent ID: 7107412

Claim:
A memory module comprising: a memory interface structured to interface with a processor-based system; a program memory coupled to the memory interface, the program memory being structured to store program instructions received through the memory interface responsive to a first set of addresses received through the memory interface; and a plurality of memory/processing units each of which includes a processor and a respective system memory, the processor in each of the memory/processing units being coupled to the program memory to receive and then execute the program instructions that have been stored in the program memory and being coupled to the respective system memory to cause the processor to access the respective system memory so that the processors in the plurality of memory/processing units can simultaneously perform a processing function on respective sets of data stored in the respective memory, the system memory of each of the plurality of memory/processing units being coupled to the memory interface to allow the system memories to be accessed by the processor-based system responsive to a second set of addresses received through the memory interface, at least some of the addresses in the second set being different from the addresses in the first set.