Patent ID: 7737748

Claim:
A level shifter of a semiconductor device comprising: a voltage controlled delay unit configured to receive an input signal, invert a level of the input signal, and delay the inverted input signal to output a delayed inverted signal, a delay time of the delayed inverted signal being adjusted in a manner that performs a charging operation with the inverted signal in response to a delay control signal, wherein the voltage controlled delay unit comprises: an inverter configured to receive the input signal and to invert a level of the input signal to output the inverted input signal to the gate of the second NMOS transistor; a capacitor having one terminal to which the ground voltage is applied; and a fifth NMOS transistor having a drain to which an output signal of the inverter is applied and a source connected to the other terminal of the capacitor, and configured to deliver the output signal of the inverter to the capacitor to charge the capacitor with the output signal in response to the delay control signal applied to a gate of the fifth NMOS transistor; a level shifting unit configured to amplify a voltage difference between the input signal and the delayed inverted signal to output a pair of level-shifted signals having different phases, wherein the level shifting unit comprises: a voltage difference generating portion configured to sense a voltage difference between the input signal and the delayed inverted signal in response to the input signal and the delayed inverted signal to generate a voltage difference generated between a pair of input nodes; a voltage difference delivering portion configured to deliver the voltage difference generated between the pair of input nodes to a pair of output nodes in response to a power supply voltage; and a level-shifted signal output portion configured to amplify the voltage difference delivered to the pair of output nodes to output the pair of level-shifted signals.