Patent ID: 7648860

Claim:
A method of manufacturing a device usable as a thin-film transistor, comprising: depositing a semiconducting layer over a substrate; depositing a dielectric layer over said semiconducting layer; depositing a gate metal layer over said dielectric layer; patterning said gate metal layer to form a gate metal structure, said gate metal structure having an upper surface and lateral surfaces; patterning said dielectric layer, using said gate metal structure as a mask, to form a dielectric structure, said dielectric structure having lateral surfaces; etching at least said lateral surfaces of said dielectric structure such that said lateral surfaces of said dielectric structure are etched to a greater extent than said lateral surfaces of said gate metal structure, to thereby form an overhang region below said gate metal structure and adjacent said lateral surfaces of said dielectric structure; depositing a conductive layer over said upper surface of said gate metal structure and said semiconducting layer, said conductive layer comprising: a first region, formed over said gate metal structure such that said first region extends beyond the lateral dimension of said gate metal structure and a portion thereof is in physical and electrical contact with said lateral surfaces of said gate metal structure, extending over said first overhang region; a second region, extending laterally from within said overhang region and increasing in thickness from a location proximate a lateral edge of said dielectric structure within said overhang region to a region outside of said overhang region and laterally adjacent said dielectric structure; and a third region extending laterally in a direction opposite to the lateral direction of said second region so as to be disposed laterally adjacent said dielectric structure and on a side opposite from said second region relative to said dielectric structure; whereby said gate metal structure may act as a gate controlling current flow in a channel defined therebelow in said semiconductive layer between said second region and said third region.