Patent ID: 7786572

Claim:
An electronic package that includes a multiplicity of stacked electronic flip chip circuits, said package comprising: a connection surface or substrate defining first electrical traces and second electrical traces thereon, said first electrical traces extending from first wire bond pads to first contact pads, said second electrical traces extending from second wire bond pads to fourth contact pads; a first flip chip having an active side and a back side, said active side comprising first electrical circuits connected to a first multiplicity of bump contacts on said active side, said multiplicity of bump contacts in electrical contact with said first contact pads and fourth contact pads on said connection surface, said back side of the first flip chip defining electrical traces extending from second contact pads and electrically connected to third wire bond pads; a second flip chip having an active side and a back side and having second electrical circuits connected to a second multiplicity of bump contacts on said active side, said second multiplicity of bump contacts positioned to be in electrical contact with said second contact pads on said first flip chip, said back side of the second flip chip comprising third contact pads and fourth wire bond pads, said second flip chip comprising a via connecting an active circuit on said active side of the second flip chip to either the third contact pads or the fourth wire bond pads; a third flip chip including a third multiplicity of bump contacts in electrical contact with said third contact pads; at least one wire bond connected between one of said third wire bond pads on said back side of said first flip chip and one of said second wire bond pads on said connection surface; and at least one second wire bond connected directly between one of said fourth wire bond pads on said back side of said second flip chip and one of said first wire bond pads on said connection surface.