Patent ID: 7042051

Claim:
A semiconductor device having a MISFET, wherein a semiconductor region which has a conductivity type reverse to that of source and drain regions, is located in a semiconductor substrate below a gate electrode of the MISFET, and includes an impurity layer having a function of preventing punch through and a channel region of the MISFET formed between the gate electrode and the impurity layer, wherein the impurity layer has an impurity concentration distribution having a first peak in a region shallower than the depth of the source and drain region and a second peak in a region deeper than the channel region of the MISFET and shallower than the first peak such that the impurity concentration of the first peak is higher than the impurity concentration of the second peak and such that the impurity concentration of the second peak is higher than the impurity concentration of the channel region, wherein the source and drain regions have relatively low concentration source and drain extension regions and relatively high concentration source and drain diffusion regions, wherein the impurity layer includes a first impurity layer having the first peak and a second impurity layer have the second peak, wherein the first impurity layer is contiguous to a pair of the relatively high concentration source and drain diffusion regions for preventing punch through therebetween, and wherein the second impurity layer is contiguous to a pair of the relatively low concentration source and drain extension regions for preventing punch through therebetween.