Patent ID: 8874855

Claim:
A method for directory-based cache coherence in a multi-core processor system that includes a main memory, a plurality of processor cores, and a plurality of caches each associated with a respective one of the plurality of processor cores, the method comprising: providing a directory descriptor cache in the multi-core processor system, wherein the directory descriptor cache is separate from the plurality of caches, the directory descriptor cache being associated with a subset of the plurality of processor cores; storing a directory descriptor in the directory descriptor cache, the directory descriptor including information identifying each of the plurality of caches associated with the respective ones of the subset of the plurality of processor cores that includes data stored at a respective set of memory locations of the main memory; updating the directory descriptor stored in the directory descriptor cache in response to a processor core of the subset of the plurality of processor cores accessing at least one location of the respective set of memory locations of the main memory; and maintaining a directory descriptor metadescriptor in the main memory, the directory descriptor metadescriptor containing a copy of the directory descriptor stored in the directory descriptor cache.