Patent ID: 8735254

Claim:
A semiconductor device manufacture method comprising: preparing a semiconductor substrate having a first region of a first conductivity type; forming a first drain region of a second conductivity type opposite to said first conductivity type in said first region; forming a gate insulating film on said first region and said first drain region; forming a gate electrode on said first gate insulating film, said gate electrode having an overlap with both said first region and said first drain region; forming an opposite conductivity type region of said first conductivity type by implanting impurities to determine said first conductivity type into a surface layer of said first drain region; forming an insulating film above said first drain region, said insulating film covering a side wall of said gate electrode on a side of said first drain region and extending to a partial area above said opposite conductivity type region; forming a second drain region of said second conductivity type having an impurity concentration higher than an impurity concentration of said first drain region, by implanting impurities for determining said second conductivity into said opposite conductivity type region and an underlying region of said first drain region; and forming a source region of said second conductivity type in said first region on a first end of said first drain region opposite to said gate electrode.