Patent ID: 8648464

Claim:
A semiconductor device comprising: a semiconductor substrate; and an interconnection provided above the semiconductor substrate, the interconnection including a co-catalyst layer, a catalyst layer provided on the co-catalyst layer, and a graphene layer provided on the catalyst layer, the co-catalyst layer comprising a portion contacting the catalyst layer, the portion having a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate, or having a hexagonal close-packed structure with a (002) plane oriented parallel to the surface of the semiconductor substrate, or the co-catalyst layer comprising a portion contacting the catalyst layer, the portion having an amorphous structure or a microcrystalline structure, and the catalyst layer having a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate, or having a Hexagonal close-packed structure with a (002) plane oriented parallel to the surface of the semiconductor substrate.