Patent ID: 8466545

Claim:
A stackable semiconductor package comprising: a substrate comprising a first side surface comprising first pads, wherein the first pads are aligned into at least two parallel rows; solder layers coupled to the first pads; a semiconductor die coupled to the first side surface of the substrate, wherein the semiconductor die has a rectangular perimeter formed by four substantially vertical sidewalls, and at least two of the sidewalls are immediately adjacent to, and parallel to, a respective one of the rows of first pads, and wherein a lateral distance “a” between immediately adjacent ones of the first pads, and a lateral distance “b” between each of the first and second sidewalls of the semiconductor die and the first pads of the row immediately adjacent to the respective sidewall are selected so that a>b; and a protective layer covering the first side surface of the substrate and filling spaces between and directly contacting the solder layers, the protective layer comprising hardened epoxy-based material.