Patent ID: 7315059

Claim:
A semiconductor memory device comprising one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein a memory cell of the plurality of memory cells comprises a charge storage layer, a control gate and an impurity diffusion layer of a second conductivity type which is formed in a portion of the one or more protruding semiconductor layers and the plurality of memory cells is aligned to at least a predetermined direction, the control gate is aligned to the predetermined direction and placed so as to be separated from another control gate, wherein the one or more protruding semiconductor layers are of the same first conductivity type as that of the semiconductor substrate, wherein the one or more protruding semiconductor layers has at least two or more surfaces, and the plurality of memory cells is formed on said at least two or more surfaces of the protruding semiconductor layer, the plurality of memory cells aligned to the predetermined direction is further aligned in the direction perpendicular to the predetermined direction, and the memory cells aligned in the direction perpendicular to the predetermined direction are connected to each other in series, the protruding semiconductor layer is formed so as to have step forms having two or more steps in a cross section in the direction perpendicular to the surface of the semiconductor substrate where a charge storage layer and a control gate are placed on a side of each step of the protruding semiconductor layer in the step form, and the impurity diffusion layer of the second conductivity type is formed in a portion or the entirety of corners of the protruding semiconductor layer in the step form and, thereby, the plurality of memory cells formed on sides of the respective steps of the protruding semiconductor layer is connected in series.