Patent ID: 6872622

Claim:
A method of fabricating a capacitor structure, on a semiconductor substrate comprising the steps of: providing a plurality of gate structures with source/drain regions located in portions of said semiconductor not covered by said gate structures; depositing a first insulator layer on said gate structures; forming a plurality of first, second and third storage node contact plugs in said first insulating layer; forming an etch stop layer on said first insulator layer and on said storage node contact plugs; depositing a second insulator layer on said etch stop layer; removing part of said second insulator layer and part of said etch stop layer to expose a plurality of first storage node windows, and a plurality of second storage node windows on said first and second storage node contact plugs; depositing a first conductive layer on said first storage node window and on said second storage node window to form a first and a second bottom electrode; removing said first conductive layer and said second insulator layer, located between said first storage node window and said second storage node window to form a patterned first conductive layer; forming a dielectric layer on said patterned first conductive layer; depositing a second conductive layer to fill said first storage node window and said second storage node window; and planarizing said second conductive layer to form a top electrode connecting said first and said second bottom electrode.