Patent ID: 8665652

Claim:
A method for erasing a memory array, wherein the memory array comprises a plurality of memory cell strings, each of the memory cell strings comprises a plurality of memory cells connected to a plurality of word lines, wherein each of the memory cell strings further comprises a first transistor and a second transistor, the method for erasing the memory array comprising: applying a first voltage to a substrate of the memory array; applying a second voltage to a word line of a selected memory cell, and applying a plurality of passing voltages to the other word lines; respectively applying a third voltage and a fourth voltage to a first source/drain region and a second source/drain region of the selected memory cell, so that a band to band (BTB) hot hole injecting method is induced to erase the specific memory cell, wherein the third voltage is not equal to the fourth voltage; turning on the first transistor connected to the selected memory cell, so as to apply the third voltage to the first source/drain region of the selected memory cell; and turning off the second transistor connected to the selected memory cell, so that a channel of the memory cells connected to the second source/drain region of the selected memory cell self boosts to the fourth voltage.