Patent ID: 8296541

Claim:
A memory subsystem comprising: a memory module comprising: two or more memory devices; and a buffer device comprising a read data buffer for holding read data from the memory devices; a memory controller for generating read commands for reading data from the memory devices, each read command including a starting address of a memory burst read operation and a delay period for the read data to reside in the read data buffer of the buffer device prior to the buffer device sending the read data to the memory controller, the memory controller further comprising: a read buffer counter to track buffer usage at the memory controller for the read data buffer; and an outstanding read latency counter to keep track of remaining latency of a latest outstanding read operation including transfers of read data associated with the memory burst read operation; and one or more memory busses, wherein the memory module and the memory controller are interconnected via the memory busses and wherein the delay period varies and is calculated by the memory controller responsive to a minimum read latency associated with the memory module and to prevent collisions with other data expected on the memory busses from other read operations, the other read operations including at least one previous memory burst read operation, wherein the memory controller is further configured to update the outstanding read latency counter as a function of a read latency for the memory module, a width of the memory burst read operation, and an additional read data latency time period, the additional read data latency time period calculated for each read command as a read data buffer delay for the memory module.