Patent ID: 8549232

Claim:
An information processing device including a plurality of processing units which process an out-of-order memory access, each of the processing units comprising: a cache memory; an instruction port that holds instructions for accessing data in the cache memory in entries; a first validation determiner that validates a first flag when the first determination unit receives an invalidation request for invalidating data stored in the cache memory after a target data of a load instruction is transferred from the cache memory to an arithmetic unit and when it is determined that the load instruction has a cache index identical to a cache index of a target address of the received invalidating instruction and exists in the instruction port; a second validation determiner that validates a second flag when it is determined that the target data of the load instruction held in an entry of the instruction port has been transferred after a cache miss of the target data occurred; and an instruction re-execution determiner that instructs to re-execute an instruction that follows the load instruction when it is determined that the first flag and the second flag are both valid when the load instruction held in the entry of the instruction port has been completed.