Patent ID: 7937563

Claim:
A processor comprising: a cache configured to store instructions; an instruction fetch unit; control logic configured to pick a first plurality of instructions; and a scheduler configured to: maintain an activity level weight table including a plurality of predetermined weight values, wherein each of said weight values represents an estimated amount of node capacitance switching within the processor that would be caused by execution of one or more corresponding instructions, and wherein an activity level of one or more instructions is based upon one or more of the weight values; associate a first activity level based upon one or more weights from the table with the first plurality of instructions; read a previously determined and stored second activity level associated with a second plurality of instructions; determine a first average node switching capacitance based upon the first activity level and the second activity level; issue a first number of said plurality of instructions in response to determining the first average is less than a first threshold; and throttle instruction issue by issuing a second number of said plurality of instructions in response to determining the first average is greater than the first threshold, wherein said second number is less than said first number.