Patent ID: 8884704

Claim:
A phase-locked loop (PLL), comprising: a frequency locked loop (FLL) comprising: a voltage controlled oscillator (VCO) configured to receive a control voltage signal and to generate an output signal; a frequency divider configured to frequency divide the output signal to generate a frequency-divided output signal; a frequency-to-voltage (F/V) converter configured to receive the frequency-divided output signal and to generate a feedback voltage signal; a loop filter configured to filter the feedback voltage signal to generate a filtered feedback voltage signal; and a subtractor configured to receive a tuning voltage and the filtered feedback voltage signal and to generate the control voltage signal; a phase-frequency detector (PFD) configured to receive a reference signal and an input signal proportional to the output signal and to generate a phase error signal; and a filter configured to filter the phase error signal and to generate the tuning voltage.