Patent ID: 8000130

Claim:
A semiconductor memory device, comprising: a word line; a bit line crossing said word line; a memory cell connected to intersection of said word line and said bit line; and a sense circuit connected to sense node coupled to said bit line, said sense circuit including a first transistor of the first conduction type having a gate connected to said sense node, a second transistor of the second conduction type having a source connected to a first power supply, a drain connected to said sense node, and a gate connected to the drain of said first transistor, a third transistor of the second conduction type having a source connected to the first power supply, a drain connected to the drain of said first transistor, and a gate connected to a control signal line, and a fourth transistor of the first conduction type having a source connected to a second power supply, a drain connected to the source of said first transistor, and a gate connected to said control signal line, wherein said sense circuit is activated with a control signal given to said control signal line.