Patent ID: 7915086

Claim:
A manufacturing method of a semiconductor device, comprising the steps of: (a) providing a wiring substrate having a main surface, a plurality of bonding electrodes formed on the main surface, a common wiring formed inside of the plurality of bonding electrodes in a plane view, a plurality of first lead-out wirings arranged between each of the plurality of bonding electrodes and the common wiring in a plane view, a second lead-out wiring arranged between the plurality of bonding electrodes adjacent to each other in a plane view, a back surface opposing to the main surface, a plurality of land portions formed on the back surface, and a plating layer formed on the plurality of bonding electrodes and the plurality of land portions; (b) mounting a semiconductor chip having a plurality of electrodes over the main surface of the wiring substrate; (c) electrically coupling the plurality of electrodes of the semiconductor chip with the plurality of bonding electrodes of the wiring substrate via a plurality of conductive materials, respectively; (d) sealing the main surface of the wiring substrate and the semiconductor chip with resin; and (e) forming a plurality of external terminals on the plurality of land portions, respectively, wherein one end portion of each of the plurality of first lead-out wirings is electrically connected with one of each of the plurality of bonding electrodes, respectively; wherein the other end portion of each of the plurality of first lead-out wirings, opposing to the one end portion, is electrically separated from the common wiring; and wherein the second lead-out wiring is electrically separated from the common wiring.