Patent ID: 8214689

Claim:
A disk array device, comprising: a first interface unit for sending and receiving information to and from a host computer via a network; a memory device for storing data; a second interface connected to the memory device and for performing I/O processing of data with the memory device; a control unit connected to the first interface unit and the second interface unit and for performing I/O processing of data to a plurality of virtual devices allocated to at least a part of the storage area of the memory device; a cache memory for temporarily storing data associated with the processing of the control unit; a shared memory for storing information for managing the cache memory; a nonvolatile memory for saving data stored in the cache memory and data stored in the shared memory; a first battery that is charged by receiving the supply of electric power from a power source that supplies electric power to the control unit, and for feeding power to the cache memory with the charged electric power; a second battery that is charged in less time than the first battery by receiving the supply of electric power from the power source, and for feeding power to the shared memory with the charged electric power; and a memory controller for saving information stored in the shared memory and data stored in the cache memory to the nonvolatile memory during a power failure of the power source, wherein the memory controller monitors the charging capacity of the first battery during the power restoration of the power source, and gradually releases the storage area of the cache memory as an accessible storage area according to the charging capacity of the first battery, and wherein, during the power restoration of the power source, the memory controller returns information saved in the nonvolatile memory to the shared memory on the condition that the initialization time has lapsed and the charging capacity of the second battery has reached full charge capacity, and gradually returns data saved in the nonvolatile memory to the cache memory according to the charging capacity of the first battery.