Patent ID: 8291175

Claim:
A method for processing a read request identifying an address, comprising: receiving, at a module comprising a flash memory and a memory buffer, the read request from a requesting processor node, wherein the requesting processor node comprises a first processor, a first main memory, and a first cache memory, wherein the address identified by the read request corresponds to a cache line stored on the module, and wherein the read request is transmitted along a processor bus connecting the module and the requesting processor node; determining, using a coherence directory controller within the module, that a copy of the cache line is stored in a second cache memory in a remote processor node, wherein the remote processor node comprises the second cache memory and a second main memory, and wherein the remote processor node is external to the module; sending a coherency message from the module to the remote processor node to change a state of the copy of the cache line in the second cache memory; receiving, at the module, the copy of the cache line from the remote processor node; sending, using the processor bus and in response to the read request, the cache line to the requesting processor node; identifying a requested page stored within the flash memory of the module based on the address; storing a copy of the requested page in the memory buffer of the module; and writing the cache line to the copy of the requested page in the memory buffer of the module.