Patent ID: 7898894

Claim:
A Static Random Access Memory (SRAM) cell, comprising: a write word line; a read word line that is decoupled from the write word line; a pair of cross-coupled inverters; first and second complementary pass transistors coupled to the write word line; a first pair of stacked transistors having first and second transistors, wherein the first transistor of the first pair of stacked transistors is coupled to a first common read and write bit line and the read word line, and wherein the first common read and write bit line is coupled to the first complementary pass transistor; and a second pair of stacked transistors having first and second transistors, wherein the first transistor of the second pair of stacked transistors is coupled to a second common read and write bit line and the read word line, and wherein the second common read and write bit line is coupled to the second complementary pass transistor; and wherein the second transistor of the first pair of stacked transistors is further coupled to the first complementary pass transistor, and the second transistor of the second pair of stacked transistors is further coupled to the second complementary pass transistor.