Patent ID: 8402251

Claim:
A semiconductor device comprising: a first circuit that is dynamically reconfigurable, and executes a first calculation; a second circuit that is dynamically reconfigurable, includes a first storage unit therein, and executes a second calculation; a controller that outputs a first address to the first circuit and the second circuit, and controls input of data into the first circuit, the first address being a value for specifying a first execution circuit for the first calculation and a second execution circuit for the second calculation; and a bus that transfers a result of the first calculation executed by the first circuit to the second circuit, wherein the first circuit executes the first calculation with respect to first input data into the first circuit by means of the first execution circuit configured based on the first address, and outputs the result of the first calculation to the bus, and the second circuit selects the first address or the result of the first calculation based on information stored in the first storage unit addressed by the first address, configures the second execution circuit based on the selected one from the first address and the result of the first calculation, executes the second calculation with respect to second input data into the second circuit by means of the second execution circuit, and outputs a result of the second calculation.