Patent ID: 8570203

Claim:
A system for outputting a signal, comprising: one or more memory elements including: a first memory element configured to store values of a first component in a Taylor series expansion, a second memory element configured to store values that when combined with values stored in a third memory element represent a second component in the Taylor series expansion, and a fourth memory element configured to store values of a third component in the Taylor series expansion; a parallel to serial converter configured to: couple to each of the one or more memory elements, and convert outputs of the one or more memory elements to serial bitstreams for transmission; a serial to parallel converter configured to: receive the serial bitstreams, and convert the serial bitstreams into parallel bitstreams; an adder configured to: receive the outputs of the first memory element, the second memory element, the third memory element, and the fourth memory element as parallel bitstreams from the serial to parallel converter, add the outputs to generate the first component, the second component and the third component of the Taylor series expansion, and combine the first component, the second component and the third component to form a signal output; a digital-to-analog converter (DAC) configured to: receive the signal output from the adder, and convert the signal output to an analog output signal; and a low pass filter configured to: receive the analog output signal from the DAC and provide a filtered analog output signal.