Patent ID: 8448050

Claim:
A memory system having a storage apparatus configured to store coded first data resulting from encoding first data composed of a plurality of pieces of second data and a host configured to send and receive the first data to and from the storage apparatus, the storage apparatus comprising: a first ECC decoder configured to perform hard decision code decoding processing with a hard decision code on a second data basis; a second ECC decoder configured to perform LDPC decoding processing with an LDPC code on a first data basis; a second data error flag section configured to set, for each second data, a second data error flag that stores information about presence or absence of error data in the hard decision code decoding processing; and an ECC control section configured to perform, in the LDPC decoding processing, control of increasing an absolute value of a log likelihood ratio indicating a reliability of second data containing no error data based on the information in the second data error flag section.