Patent ID: 7491593

Claim:
A method for fabricating a thin film transistor (TFT) array substrate, the method comprising: providing an insulating substrate; coating a transparent conductive layer and a gate metal layer on the substrate; forming a gate electrode and a pixel electrode using a first photo-mask process; forming a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a source/drain metal layer on the substrate having the gate electrode and the pixel electrode; forming a source electrode and a drain electrode using a second photo-mask process, the source electrode and the drain electrode defining a channel therebetween, the second photo-mask process comprising coating a photo-resist layer on the source/drain metal layer, exposing the photo-resist layer using a photo-mask comprising a slit, and developing the exposed photo-resist layer to form a photo-resist pattern having a groove; forming a metal layer on the substrate and the pixel electrode; forming a passivation material layer on the source electrode, the drain electrode, the channel, and the metal layer; and forming a passivation layer on the source electrode, the drain electrode and the channel and a metal contact layer using a third photo-mask process, the metal contact layer interconnecting the drain electrode and the pixel electrode.