Patent ID: 8339833

Claim:
A nonvolatile semiconductor storage device comprising: a memory core that includes a plurality of banks, the bank including a plurality of memory cells that are provided into a matrix shape and a data write circuit that supplies a bias voltage necessary to write data to the memory cell, the memory core being logically divided into a plurality of pages, the page including a predetermined number of memory cells belonging to a predetermined number of banks; a control circuit that controls the data write circuit to perform page write in each write unit including a predetermined number of memory cells, pieces of data being written in the page in the page write, the control circuit performing the page write by repeating a step including a program operation and a verify operation, and the control circuit performing the program operation and the verify operation in a next step only to the write unit in which the data write is not completed in the verify operation; and a write data inspection circuit that inspects write data for the bank and determines whether the data write to the bank is not required, wherein the control circuit, in a case that the data write is not required in the write unit in the bank, executes data write in another write unit belonging to the same bank.