Patent ID: 8537626

Claim:
A semiconductor device comprising: a memory cell connected to a word line and a bit line; a sense amplifier circuit connected to the bit line; an access control circuit that controls the word line and the sense amplifier circuit; and an internal voltage generating circuit that generates an internal voltage stabilized regardless of fluctuations of an external voltage, wherein the access control circuit comprises: a first signal generator that operates on the internal voltage and generates a first signal that activates and inactivates the word line; a second signal generator that operates on the internal voltage and generates a second signal that activates and inactivates the sense amplifier circuit in synchronization with an activation and an inactivation of the word line; a third signal generator that operates on the external voltage and generates a third signal that starts and stops a supply of an overdrive voltage to the sense amplifier circuit in synchronization with the activation of the word line or an activation of the sense amplifier circuit; and a fourth signal generator that operates on the internal voltage and generates a fourth signal that inactivates the first signal in synchronization with the activation of the word line or the activation of the sense amplifier circuit, the third signal generator determining a period during which the overdrive voltage is to be supplied, in accordance with a level of the external voltage, and the fourth signal generator determining timing to activate the fourth signal in accordance with a level of the internal voltage, regardless of the level of the external voltage.