Patent ID: 7808045

Claim:
A semiconductor device comprising: a first circuit block having a first sub circuit block including a plurality of first transistors and a second sub circuit block including a plurality of second transistors; a second circuit block having a third sub circuit block including the plurality of first transistors and a fourth sub circuit block including the plurality of second transistors; and a first power select switch connected to the first circuit block and the second circuit block, wherein each of the plurality of first transistors includes a first semiconductor layer formed on a semiconductor substrate via a first embedded oxide film; a first source region and a first drain region formed in the first semiconductor layer and having a same thickness as that of the first semiconductor layer; a first channel region formed between the first source region and the first drain region and formed in the first semiconductor region, the first channel region being a full depletion region; a first gate formed on a first main surface of the first channel region via a first gate insulating film; a second gate formed of a conductive layer formed in contact with a bottom surface of the first embedded oxide film and electrically connected with the first gate; and a first insulating separating layer formed on the semiconductor substrate so as to surround the first semiconductor layer, wherein each of the plurality of second transistors includes a second semiconductor layer formed on, the semiconductor substrate via a second embedded oxide film; a second source region and a second drain region formed in the second semiconductor layer and having a same thickness as that of the second semiconductor layer; a second channel region formed between the second source region and the second drain region and formed in the second semiconductor region, the second channel region being a full depletion region; a third gate formed on a first main surface of the second channel region via a second gate insulating film; a fourth gate formed of a conductive layer formed in contact with a bottom surface of the second embedded oxide film; and a second insulating separating layer formed on the semiconductor substrate so as to surround the second semiconductor layer, wherein an output signal of the first sub circuit block is inputted into the fourth gates of the plurality of the second transistors arranged in the second sub circuit block, wherein an output signal of the third sub circuit block is inputted into the fourth gates of the plurality of the second transistors arranged in the fourth sub circuit block, wherein an input signal into the third gate of each second transistor is independent of the input signal into the fourth gate of that second transistor arranged in the second sub circuit block and the fourth sub circuit block, wherein a power voltage is supplied to the first circuit block or the second circuit block via the first power select switch, and wherein the first power select switch comprises the first transistor.