Patent ID: 7482238

Claim:
A method for manufacturing and operating a semiconductor device, comprising: forming a P + buried layer; forming an N drift region formed over the P + buried layer; forming a cathode, a gate, and an anode over the P + buried layer, the cathode, the gate, and the anode being spaced apart from each another; forming a P + cathode below the cathode and over the P + buried layer; forming a P-base area below the gate and over the P + buried layer, the P-base are being spaced apart from the P + cathode; forming a P + anode below the anode and over the P + buried layer; forming a N + cathode over the P + buried layer and between the cathode and gate, wherein the P-base area is not formed below the N + cathode; and injecting a hole current into the N drift region while a constant voltage is applied to the P + anode, such that a majority of the hole current passes through the P + cathode of via the P + buried layer.