Patent ID: 7448395

Claim:
A method of fabricating a semiconductor device comprising: forming a gate oxide layer on a semiconductor substrate; forming a polysilicon layer on the gate oxide layer; patterning the gate oxide layer and the polysilicon layer to form gate structures; forming offset spacers adjacent to gate stacks; performing an shallow region implant to form extension regions; depositing a dielectric layer and patterning the dielectric layer to form sidewall spacers adjacent to the gate stacks and the offset spacers via a dry etch plasma process that leaves dry etch residue; performing a first cleaning operation that removes a portion of the dry etch residue; performing an extended cleaning operation to substantially remove the dry etch residue after the first cleaning operation; performing an active region deep implant to form active regions after performing the first cleaning operation and the extended cleaning operation; performing an anneal operation to form the active regions; performing a wet pre-clean operation to remove a portion of native oxide from a surface portion of the active regions; performing a reduced sputter operation to substantially remove the native oxide that mitigates dislodging of sidewall materials from the sidewall spacers onto surfaces of the active regions; forming a cobalt layer on the device by depositing cobaly; forming a cap layer on the cobalt layer; performing a first silicide anneal to initiate formation of cobalt mono-silicide regions, wherein the cobalt-silicide regions are substantially uniform; removing the cap layer and the un-reacted cobalt; and performing a second silicide anneal to complete formation of the cobalt di-silicide regions.