Patent ID: 8301946

Claim:
An integrated circuit comprising: A. a TDI input lead, TMS input lead, TCK input lead, and TDO output lead; B. a first access port having an input connected to the TDI input lead, an input connected to the TMS input lead, an input connected to the TCK input lead, an enable input, and a data output coupled to the TDO output lead; C. a second access port having an input connected to the TDI input lead, an input connected to the TMS input lead, an input connected to the TCK input lead, an enable input, and a data output coupled to the TDO output lead; D. an inverter having an input connected to the TCK input lead and an output; E. an access port selector having a port select register and a state machine controller, the port select register having an input coupled to the TDI input lead, control inputs, a first enable output connected to the enable input of the first access port, and a second enable output connected to the enable input of the second access port, the state machine controller having an input coupled to the TMS input lead, an input coupled to the output of the inverter, and control outputs connected to the control inputs of the port select register; and F. a flip-flop having a data input connected to the output of the port select register, a data output coupled to the TDO output lead, and a clock input connected to the input of the inverter and the TCK input lead, the flip-flop passing data from its data input to its data output on a rising edge of a TCK clock signal on the TCK clock lead.