Patent ID: 6980448

Claim:
A dynamic random access memory (DRAM) having a boosted voltage supply comprising: a boosting capacitor having first and second terminals; and a switching circuit including a first transistor between a DC voltage supply and the first terminal of the boosting capacitor and a second transistor between the first terminal of the boosting capacitor and a capacitive load, the first transistor and the second transistor being driven by clock signals derived from an oscillator, the switching circuit alternately connecting the first terminal of the boosting capacitor to the DC voltage supply and to the capacitive load, while alternating the voltage level connected to the second terminal of the boosting capacitor with clocked transistors, to pump the voltage on the capacitive load to a boosted supply voltage greater than and of the same polarity as the DC voltage supply, the second transistor being fully switched to substantially eliminate a threshold voltage reduction of boosted voltage, the boosted supply voltage being supplied to a circuit of the DRAM.