Patent ID: 7859234

Claim:
A switch circuit, comprising: a JFET transistor having a first terminal, a second and a third terminal, in which the first terminal is coupled to receive a high voltage source; a first transistor having a drain terminal, a source terminal and a gate terminal, in which the drain terminal and the source terminal of the first transistor are connected to the second terminal of the JFET transistor and an output terminal of the switch circuit respectively; a second transistor having a drain terminal, a source terminal and a gate terminal, in which the drain terminal of the second transistor is coupled to the gate terminal of the first transistor and the third terminal of the JFET transistor, the gate terminal of the second transistor is coupled to receive a control signal, and the source terminal of the second transistor is coupled to a ground; and a resistive device coupled from the third terminal of the JFET transistor to the second terminal of the JFET transistor; wherein the resistive device provides a bias voltage to turn on the first transistor and the JFET transistor when the second transistor is turned off, the control signal is coupled to turn on the second transistor for switching off the first transistor.