Patent ID: 7683492

Claim:
A semiconductor device comprising: a wiring chip having a pair of first connection pad groups that comprise a plurality of wiring lines arranged in parallel and a plurality of pads connected to respective one end side and other end side of the wiring lines and are arranged in a staggered pattern; a first semiconductor chip, having a group of second connection pads that is formed of a plurality of pads arranged along one side thereof in a staggered pattern; and a second semiconductor chip, having a group of third connection pads that is formed of a plurality of pads arranged along one side thereof in a staggered pattern, wherein the first semiconductor chip and the second semiconductor chip are mounted on the wiring chip via bumps by flip chip mounting such that the one side along which the second connection pads of the first semiconductor chip are formed and the one side along which the third connection pads of the second semiconductor chip are formed so as to face each other, the group of first connection pads on one side and the group of second connection pads are connected with each other, the group of first connection pads on another side and the group of third connection pads are connected with each other, and the first semiconductor chip and the second conductor chip are connected with each other by a bus line connection via bus drivers and bus detectors that are provided to the respective chips, a semiconductor substrate that constitutes the wiring chip, a semiconductor substrate that constitutes the first semiconductor chips, and a semiconductor substrate that constitutes second semiconductor chip are formed of a silicon substrate, the first semiconductor chip is a memory device chip having a memory means that inputs and outputs signals in parallel for each predetermined number of bits, and the second semiconductor chip is a logic circuit chip that inputs and outputs signals in parallel for each predetermined number of bits with the memory device chip, and the respective pads of the second group of connection pads of the first semiconductor chip and the respective pads of the third group of connection pads of the second semiconductor chip are connected with each other via the wiring lines such that all of the plurality of wiring lines arranged on the wiring chip have the same wiring length, wherein the pads of the second group of connection pads of the first semiconductor chip positioned closest to opposing sides of the first semiconductor chip and the second semiconductor chip and the pads of the third group of connection pads of the second semiconductor chip positioned remotest from the opposing sides are connected and, at the same time, the pads of the second group of the connection pads of the first semiconductor chip positioned remotest from the opposing sides and the pads of the third group of the connection pads of the second semiconductor chip positioned closest to the opposing sides are connected.