Patent ID: 7099272

Claim:
A synchronous transport module (STM) comprising: a UTOPIA interface chip for transmitting a UTOPIA level 2 data; one pair of STM interface chips for receiving a UTOPIA level 1 data; a UTOPIA memory for converting the UTOPIA level 2 data into the UTOPIA level 1 data, and transferring the UTOPIA level 1 data to one of the pair of the STM interface chips according to a transmission address; and, a UTOPIA interface control part for converting the transmission address depending on states of the STM interface chips, the UTOPIA interface control part including bits which are used for determining whether the STM interface chips are to be in duplex states and/or simplex states, and other bits which are used for determining whether the respective STM interface chips are to be in active states and/or standby states in the duplexing.