Patent ID: 7919800

Claim:
A capacitor-less memory cell, comprising: an active area formed from a bulk semiconductor substrate; a pass transistor formed on the active area, the pass transistor including a source region, a drain region for coupling with a digit line and a gate for coupling with a word line; and a read/write enable transistor including a gate, a source region, and a drain region commonly shared with the source region of the pass transistor, the read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state, the logic state being storable as charge in a floating body area of the active area to cause different determinable threshold voltages for the pass transistor, wherein at least a portion of the active area is at least substantially physically isolated from the bulk semiconductor substrate by at least one material layer and the gate of the read/write enable transistor extending horizontally to be between the at least a portion of the active area and the source region of the read/write enable transistor in a vertical plane.