Patent ID: 7948785

Claim:
A semiconductor device comprising: a main sense amplifier group including main sense amplifier blocks arranged in a row direction on a substrate and spaced apart from each other; main cell array blocks arranged in the row direction on the substrate and spaced apart from each other; main bit line pairs configured to couple 2×(N+1) main cell array blocks to each of the main sense amplifier blocks, each of the main sense amplifier blocks being disposed between the main cell array blocks and N is a positive integer; an edge sense amplifier group spaced apart from the main sense amplifier group, disposed at one side of the main sense amplifier group and arranged on the substrate, the edge sense amplifier group having edge sense amplifier blocks arranged in a row direction and spaced apart from each other and the edge sense amplifier blocks having edge sense amplifiers; at least one dummy cell array block disposed on a side of the edge sense amplifier group, the edge sense amplifier group being interposed between the at least one dummy cell array block and the main sense amplifier group; and an edge bit line pair configured to couple at least one of N+1 main cell array blocks, the at least one dummy cell array block to at least one edge sense amplifier, at least one main cell array block to at least one edge sense amplifier, and the dummy cell array block to at least one edge sense amplifier.