Patent ID: 7743232

Claim:
A processor, comprising: a plurality of processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA), wherein each of said plurality of processor cores includes a respective local microcode unit configured to store microcode entries; and a remote microcode unit accessible by each of said processor cores and including a remote microcode store configured to store microcode entries; wherein said respective local microcode units and said remote microcode unit are configured such that a given microcode entry that is stored within said respective local microcode units is not also stored within said remote microcode unit; wherein any given one of said processor cores is further configured to: generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by said given processor core; determine whether said particular microcode entry is stored within said respective local microcode unit of said given processor core; and in response to determining that said particular microcode entry is not stored within said respective local microcode unit, convey a request for said particular microcode entry to said remote microcode unit.