Patent ID: 8094509

Claim:
A memory device, comprising: a memory including a plurality of arrays, wherein each of the plurality of arrays is arranged to receive a boost voltage; boost converter circuitry that is arranged to provide the boost voltage, wherein the boost converter circuitry includes: a plurality of boost converters including a first boost converter having at least an output and a second boost converter having at least an output; and a switch that is arranged to couple the output of the first boost converter to the output of the second boost converter if the switch is closed, and to de-couple the output of the first boost converter from the output of the second boost converter if the switch is open; and a switch control circuit that is arranged to, for each data access of one of the arrays of the plurality of arrays, control opening and closing of the switch such that the switch is opened or closed based on distance of the array being accessed from the plurality of boost converters.