Patent ID: 8902675

Claim:
A semiconductor memory device comprising: a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells; and a column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches, one of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled, wherein, when a set of the sense amplifiers capable of handling one of the cell columns is set as a sense amplifier set, a set of the data latches capable of handling one of the cell columns is set as a data latch set, and a set of the one of the sense amplifier sets and the one of the data latch sets is set as a column set, each sense amplifier-data latch unit includes a common control circuit that is used in common for controlling a plurality of column sets of the respective sense amplifier-data latch unit, and a common control circuit of the second sense amplifier-data latch unit has a circuit scale equal to that of a common control circuit of the first sense amplifier-data latch unit.