Patent ID: 6910141

Claim:
An apparatus including integrated processor circuitry, said apparatus comprising: a plurality of interface electrodes including one or more control electrodes to convey one or more incoming control signals from at least one signal source having at least a first combination of respective assertion and de-assertion states corresponding to a power management operation mode; control circuitry coupled to said one or more control electrodes and responsive to said one or more incoming control signals by providing at least one lock control signal having respective assertion and de-assertion states related to said one or more incoming control signal assertion and de-assertion states with said respective assertion states following said first incoming control signal states combination; clock circuitry coupled to said control circuitry and responsive o said at least one clock control signal by providing at least a first clock signal having active and inactive states corresponding to said at least one clock control signal de-assertion and assertion states, respectively; and a plurality of subcircuits coupled to at least a portion of said plurality of interface electrodes, said control circuitry and said clock circuitry, and including pipeline subcircuitry responsive to said first clock signal by selectively operating on one or more instructions for data processing, wherein a first portion of said pipeline subcircuitry is responsive to said active first clock signal by performing at least one or more respective portion of one or more decoding operations upon each one of at least one or more respective portions of one or more incoming instructions to provide one or more decoded instructions, and a second portion of said pipeline subcircuitry is couple to said first pipeline subcircuitry portion and responsive to said active first clock signal by executing said one or more decoded instructions.