Patent ID: 7525173

Claim:
A layout structure of a plurality of metal oxide semiconductor (MOS) transistors, comprising: a first group of MOS transistors having first drain regions and first source regions that are individually allocated to one of a plurality of active regions that is isolated from all sides by a trench isolation, a second group of MOS transistors having second drain regions and second source regions allocated to a second active region of the plurality of active regions, each of the second group of MOS transistors being dummy transistors configured to provide electrical isolation, and the second group disposed between the first group and an edge of the active regions, wherein one or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode, and a gate of the first group and second group of MOS transistors formed of three fingers, the gate including, a first and a second gate finger with a same first given length disposed in parallel and connected to each other at both ends, and a third gate finger having a length less than half of the first given length disposed in parallel with the second gate finger, the third gate fingers belonging to mutually adjacent MOS transistors disposed facing each other in a gate length direction.