Patent ID: 8643105

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a buried insulation film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulation film; an element isolation region provided between active areas which are formed in the semiconductor layer; a source layer and a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer and beneath the source layer and the drain layer, and being in an electrically floating state, the body region accumulating or discharging charges to store data; a gate dielectric film provided on the body region; a gate electrode provided on the gate dielectric film; and a plate electrode facing a side surface of the body region via an insulation film, in the element isolation region; wherein the gate electrode faces an upper surface and both side surfaces of the body region via the gate dielectric film, and a bottom surface of the plate electrode is a substantially same level with that of the body region, a thickness of the plate electrode is substantially equal to that of a side part of the body region beneath the source layer and the drain layer.