Patent ID: 8493796

Claim:
A nonvolatile semiconductor memory device, comprising: a plurality of memory cells each having a charge storage layer formed on a channel region of a semiconductor substrate via a first insulating film and a control electrode formed on the charge storage layer via a second insulating film, and each configured capable of being written with multi-value data such that a threshold voltage of the memory cell is included in a threshold voltage distribution indicating an erase state or any of threshold voltage distributions of multiple kinds of write states; a memory cell array having the memory cells arranged therein; and a control unit configured to execute a write cycle multiple times, the write cycle including a write operation and a write verify operation, the write operation being an operation for applying at least one write pulse voltage to the control electrode selected for data write, and the write verify operation being an operation for determining whether data write is completed or not, when a voltage of the threshold voltage distribution to be provided to the memory cell is lower than a certain value, during the write cycles, the control unit controlling the write operation to apply the write pulse voltage multiple times, and make a voltage value of a finally applied write pulse voltage larger than a voltage value of an initially applied write pulse voltage, and when a voltage of the threshold voltage distribution to be provided to the memory cell is a certain value or more, during the write cycles, the control unit controlling the write operation to apply the write pulse voltage one time, and make a voltage value of the write pulse voltage larger on the write cycle basis.