Patent ID: 7227255

Claim:
A semiconductor device having a plurality of interconnect lines arranged in parallel with each other and having adjoining interconnect lines isolated by an insulator, wherein said insulator between the interconnect lines, comprises: a sidewall insulating layer formed at one side surface of two adjoining interconnect lines and having an approximately ¼ circular sectional shape; and an insulating film formed between said sidewall insulating layer and said interconnect line and having a dimension in the direction of separation of said sidewall insulating layer and said interconnect line defined by the film thickness; a plurality of memory transistors arranged in an array; and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, arranged extending in a row direction, and repeating in a column direction, two adjoining word lines being isolated by: a sidewall insulating layer formed at a side surface of one word line and having an approximately ¼ circular sectional shape; and an insulating film formed between said sidewall insulating layer and said word line and having a dimension in the direction of separation of said sidewall insulating layer and said word line defined by the film thickness, wherein said plurality of word lines include: first shape word lines having vertical side surfaces or forward tapered sectional shapes and having sidewall insulating layers formed at the two side surfaces; and second shape word lines adjoining said first shape word lines at the two sides in the width direction and having at least top ends reverse tapered, the reverse tapered shapes of said second shape word lines being formed reflecting the shapes of said sidewall insulating layers, the first shape word lines and second shape word lines being alternately arranged in the column direction, and wherein charge storage films including charge storage means inside are formed between said first shape word lines and said semiconductor, between said second shape word lines and said semiconductor, between said first shape word lines and said sidewall insulating layers, and between said second shape word lines and said sidewall insulating layers.