Patent ID: 7268394

Claim:
A Junction Field Effect Transistor (JFET), comprising: a buried layer that defines a backgate; an epitaxial layer over the buried layer; a doped isolation region in the epitaxial layer and connecting with the buried layer; a gate region interposed between source and drain regions, the doped isolation region surrounding the gate, source and drain regions, the gate region, the buried layer, and the doped isolation region being formed to have one of a n-type and a p-type dopant oxide isolation regions located at least partially in the epitaxial layer and between the gate region and the source and drain regions and a threshold voltage implant region associated with at least one of the gate region, the source region, and the drain region, the threshold voltage implant region comprising one of a NMOS threshold voltage (VTN) implant and a PMOS threshold voltage (VTP) implant selected according to the respective type of dopants used to form the associated at least one of the gate region, the source region and the drain region.