Patent ID: 8253256

Claim:
A stacked semiconductor package comprising: a first semiconductor package comprising: a first semiconductor chip haying a first surface and a second surface facing away from the first surface comprising; a first bonding pad disposed on the first surface of the first semiconductor chip; and a through-electrode electrically connected with the first bonding pad, passing through the first and second surfaces, such that a portion of the through-electrode extends out of the second surface; and a second semiconductor package comprising a second semiconductor chip having a through-hole defined therein, wherein the portion of the through-electrode that extends out of the second surface is inserted into the through-hole and electrically connected with a second bonding pad, wherein the second semiconductor chip comprises at least two stacked second semiconductor chips each having a through-hole defined therein, and wherein centers of each of the through-hole are substantially aligned, and a cross-sectional area of each the through-holes decreases in the direction that through-electrode extends from the first surface of the first semiconductor chip, such that the through-holes defined in the at least two stacked second semiconductor chips have a cross-sectional shape of steps, and a cross-sectional shape of the through-electrode corresponds to the cross-sectional shape of the through-holes defined in the at least two stacked second semiconductor chips.