Patent ID: 8629562

Claim:
A modular chip structure comprising: a substrate; a carrier platform attached to the substrate, the carrier platform comprising: a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and a plurality of pre-designed chip circuits selected from the group consisting of chips, chip macros, chips in combination with at least one chip macro and chip macros in combination with at least one chip assembled on the carrier platform, wherein the carrier platform comprises at least one cavity therein configured to serve as a terminal for one or more of a passive circuit, a decoupling capacitor, a resistor, a voltage regulator module and an additional chip macro, and wherein the plurality of conductive vias provides: i) one or more power and ground inputs and outputs to each of the pre-designed chip circuits through the carrier platform, and ii) one or more signal inputs and outputs to each of the pre-designed chip circuits through the carrier platform, wherein the wiring layer is configured to segment the power and ground inputs and outputs to one or more of the pre-designed chip circuits from the power and ground inputs and outputs to at least one other of the pre-designed chip circuits so as to form the plurality of voltage islands, and wherein the wiring layer is configured to segment the signal inputs and outputs to one or more of the pre-designed chip circuits from the signal inputs and outputs to at least one other of the pre-designed chip circuits.