Patent ID: 8286045

Claim:
A test apparatus testing a device under test comprising: a main pattern generating section that generates a main pattern used for testing the device under test at each test cycle; a plurality of sub-pattern generating sections each of which generates a sub-pattern corresponding to a different one of segment cycles based on a main pattern, the segment cycles formed by dividing a test cycle period, a test signal supplying section that supplies, to the device under test, a multiplexed test pattern formed by switching sub-patterns generated by the plurality of sub-pattern generating sections at each of the segment cycles; and a plurality of delay selecting sections each of which selects one of (i) a main pattern that is from the main pattern generating section and (ii) a delayed main pattern that is formed by delaying the main pattern from the main pattern generating section by a test cycle, and supplies the selected one to a corresponding one of the sub-pattern generating sections.