Patent ID: 7342839

Claim:
A circuit for accessing a memory cell, the circuit comprising: a local bitline; a local sense amplifier having a plurality of transistors, said local bitline connecting the memory cell to said sense amplifier; a first global bitline connected to a first one of said plurality of transistors; a second global bitline connected to a second one of said plurality of transistors; and a secondary sense amplifier connected to said first and second global bitlines, wherein said local sense amplifier includes: a first transistor having a gate connected to said local bitline, a source connected to said first global bitline, and a drain connected to said second global bitline; a second transistor having a gate connected to said first global bitline, a drain connected to said local bitline, and a source connected to a first power supply; and a third transistor having a gate connected to said second global bitline, a source connected to said second power supply, and a drain connected to said local bitline.