Patent ID: 7994587

Claim:
A semiconductor device comprising: a semiconductor substrate; a first gate insulating film and a second gate insulating film, the first gate insulating film being provided in a first transistor region on the semiconductor substrate, the second gate insulating film being provided in a second transistor region on the semiconductor substrate and being smaller in thickness than the first gate insulating film; a plurality of first metal oxide semiconductor (MOS) transistors formed on the first gate insulating film and each of the first MOS transistors has a first gate electrode; a plurality of second MOS transistors formed on the second gate insulating film and each of the second MOS transistors has a second gate electrode; a first element isolation region in the first transistor region, the first element isolation region being provided between the plurality of first MOS transistors, the first element isolation region being formed by embedding an insulating film in the semiconductor substrate; and a second element isolation region in the second transistor region, the second element isolation region being provided between the plurality of second MOS transistors, the second element isolation region being formed by embedding the insulating film in the semiconductor substrate, wherein the first element isolation region has a first region and a second region; a bottom surface of the second region is deeper than that of the first region by the difference of thickness between the first gate insulating film and the second gate insulating film; and a bottom surface of the first region is equal in a bottom surface of the second element isolation region.