Patent ID: 7964950

Claim:
An electronic parts packaging structure comprising: a wiring substrate having a wiring pattern; an insulating film formed on the wiring substrate, the insulating film having an opening portion in a packaging area in which a semiconductor chip is mounted, the opening portion having an area bigger than an area of the semiconductor chip; the semiconductor chip having a connection terminal on an element formation surface thereof and having a protection film on a backside thereof, the connection terminal of the semiconductor chip being flip-chip mounted on the wiring pattern exposed in the opening portion of the insulating film; filling resin formed in a gap of a lower side of the semiconductor chip and a gap between a side surface of the semiconductor chip and a side surface of the opening portion of the insulating film; a via hole penetrating a predetermined portion of the semiconductor chip and the protection film on the connection terminal; and an upper wiring pattern formed on the insulating film and the protection film, and connected to the connection terminal through the via hole of the semiconductor chip, wherein an upper surface of the semiconductor chip and an upper surface of the insulating film having the opening portion are set to an almost same height.