Patent ID: 8804806

Claim:
A symbol timing recovery circuit comprising: an interpolator to generate at least one of an interpolation data of zero-crossing point and data identification point of an input digital signal, using a first finite impulse response filter; a forward equalizer to eliminate a forward interference wave from the input digital signal based on the interpolation data generated by the interpolator, using a second finite impulse response filter, and to output a first resultant signal obtained after the elimination, a first identification signal, and a first error signal; a backward equalizer to eliminate a backward interference wave of the input digital signal based on the interpolation data generated by the interpolator, using a first infinite impulse response filter, and to output a second resultant signal obtained after the elimination, a second identification signal, and a second error signal; a first tap coefficient calculating unit to calculate a tap coefficient of the second finite impulse response filter, based on the interpolation data generated by the interpolator, the first resultant signal and the second resultant signal; a second tap coefficient calculating unit to calculate a tap coefficient of the first infinite impulse response filter, based on the interpolation data generated by the interpolator, the first resultant signal and the second resultant signal; and a timing recovery unit to generate a tap coefficient of the first finite impulse response filter, based on the tap coefficient of the second finite impulse response filter, the tap coefficient of the first infinite impulse response filter, the first identification signal, the first error signal, the second identification signal and the second error signal.