Patent ID: 7829929

Claim:
A non-volatile memory device comprising: an active region; a wordline formed on the active region to cross the active region; a charge trapping layer interposed between the active region and the wordline; a tunneling layer interposed between the charge trapping layer and a semiconductor substrate; a blocking layer interposed between the charge trapping layer and the wordline; and a filling insulation film filling recessed regions of the charge trapping layer, covering the active region, and having a top surface at the same level as the blocking layer; wherein a cross region of the active region and the wordline comprises an overlap region in which the charge trapping layer is disposed and a non-overlap region in which the charge trapping layer is not disposed; and wherein sidewalls of the tunneling layer and sidewalls of the blocking layer are aligned with an outer boundary of the cross region, and at least an end of the charge trapping layer is inwardly recessed from the sidewalls of the tunneling layer and the sidewalls of the blocking layer.