Patent ID: 7298799

Claim:
A combiner processor comprising: a sliding correlator for correlating a serial stream of baseband symbols against a first codeword and forming a correlation peak output; a training decision function coupled to said correlation peak output and generating a window output that is asserted at the start of an interval and unasserted at the end of said interval and also a training decision output; a demultiplexer coupled to said correlation peak output and having a learn control input whereby when said demultiplexer learn control input is asserted: said correlation peak output is coupled to a channel profile memory such that said correlation peak output is added to the contents of said channel profile memory when said training decision output is true and said correlation peak output is inverted and added to the contents of said channel profile memory when said training decision output is false; and when said demultiplexer learn control input is not asserted: said correlation peak output is multiplied with the complex conjugate of the contents of said channel profile memory and coupled to an accumulator which adds said multiplier result when said window output is asserted and generates a decision output when said window output is unasserted.