Patent ID: 8018250

Claim:
A system, comprising: a plurality of input/output blocks, wherein each of the plurality of input/output blocks includes: an output driver having a first control port for receiving a first tri-state signal; an input driver having a second control port; control circuitry coupled to receive the first tri-state signal and coupled to the second control port; wherein the control circuitry provides a second tri-state signal responsive to control signaling; wherein the input driver is coupled to receive the second tri-state signal; and a first input/output node commonly coupled to an output port of the output driver and a first input port of the input driver; wherein responsive to the control signaling, which includes the first tri-state signal and the second tri-state signal, the output driver is de-activated during a receive mode and activated during a send mode, and the input driver is activated during the receive mode and de-activated during the send mode; wherein the control circuitry of each of the plurality of input/output blocks coupled to receive a disable signal.