Patent ID: 8094641

Claim:
An apparatus comprising: a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port; a bit rate processor to perform bit rate processing on input data and to write data resulting from the bit rate processing to the dual-port frame memory through the first access port, in which the bit rate processor does not read data from the dual-port frame memory through the second access port; a chip rate processor to read data from the dual-port frame memory through the second access port and perform chip rate processing on the data read from the dual-port frame memory, in which the chip rate processor does not write data to the dual-port frame memory through the first access port; and a data processor to execute a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port.