Patent ID: 8001330

Claim:
A cache memory comprising: a cache array logically partitioned into at least first and second slices wherein said first slice contains a first plurality of bytes arranged in at least a first row of said cache array and said second slice contains a second plurality of bytes arranged in at least a second row of said cache array, said first plurality of bytes and said second plurality of bytes further being arranged in columns defining common sectors; and a cache controller which receives a load request including an address for a requested memory block and feeds the address to each of first and second rows, said cache controller having a single access/ command port, single output, a first directory associated with said first slice, a second directory associated with said second slice, and a single cache arbiter which manages accesses from said first and second directories and controls said single access/command port, wherein the address is selectively delivered to only one of said first and second directories based on a setting of a designated bit in the address, an enable signal is sent from said selected one of said first and second directories to a corresponding one of said first and second rows when the address matches an entry in said selected one of said first and second directories, and said sectors of said cache array are successively powered to pipeline the requested memory block from either of said first slice of said cache array or said second slice of said cache array to said single output under control of said single cache arbiter.