Patent ID: 7884425

Claim:
A semiconductor memory device, comprising: a device isolation pattern on a substrate defining a first active region and a second active region, wherein the first active region includes a first common source region, a plurality of first source/drain regions and a first drain region and wherein the second active region includes a second common source region, a plurality of second source/drain regions and a second drain region; an insulation layer overlying the first active region and the second active region; a common source line extending through the insulation layer and electrically connected to the first common source region and the second common source region; a first landing plug extending through the insulation layer and electrically connected to the first drain region; a second landing plug extending through the insulation layer and electrically connected to the second drain region; a first bit line located over the insulation layer and electrically connected to the first landing plug; and a second bit line located over the insulation layer and electrically connected to the second landing plug, wherein an upper surface of at least one of the first landing plug and the second landing plug is substantially coplanar with an upper surface of the common source line, wherein the first bit line and the second bit line are located at different heights above the substrate, and wherein the common source line extends along a plane parallel to a top surface of the substrate such that the common source line crosses over the first active region and the second active region.