Patent ID: 8522178

Claim:
A method comprising: modeling a memory array using a first model, wherein modeling the memory array comprises modeling each memory cell of the memory array to include a first uni-directional transistor that controls write operations into the memory cell and a second uni-directional transistor that controls read operations out of the memory cell; storing the first model of the memory array in memory of a computer system; and executing software on the computer system to: perform a transistor-level static timing analysis of the first model of the memory array, wherein performing the transistor-level static timing analysis includes determining a critical path of the memory array; perform a dynamic simulation on a dynamic simulation model of the critical path of the memory array, wherein the dynamic simulation determines timing requirements for the memory array; and perform a gate-level static timing analysis of a circuit that uses the memory array, wherein the gate-level static timing analysis uses the timing requirements for the memory array determined from the dynamic simulation.