Patent ID: 7692309

Claim:
A semiconductor device comprising: a plurality of non-customized layers in which are arranged an array of logic cells, each logic cell including a plurality of logic devices; a first routing grid that includes a first non-customized metal routing layer, a first via layer, and a second non-customized metal routing layer, wherein the first via layer is a customized via layer that is disposed directly on top of the first non-customized metal routing layer and the second non-customized metal routing layer is disposed directly on top of the first via layer; a second routing grid, disposed above the first routing grid, that includes a third non-customized metal routing layer, a second via layer, and a fourth non-customized metal routing layer, wherein the second via layer is a customized via layer that is disposed directly on top of the third non-customized metal routing layer and the fourth non-customized metal routing layer is disposed directly on top of the third via layer; and a third via layer disposed above the first routing grid and beneath the second routing grid, the third via layer being a non-customized via layer.