Patent ID: 8015457

Claim:
A semiconductor device comprising: a first redundancy ROM circuit storing a first redundancy address, receiving an input address, and comparing the input address with the first redundancy address to output a first redundancy selection signal, the first redundancy selection signal takes an active level when the input address is coincident with the first redundancy address and takes an inactive level when the input address is incoincident with the first redundancy address; a second redundancy ROM circuit storing a second redundancy address, receiving the input address, and comparing the input address with the second redundancy address to output a second redundancy selection signal, the second redundancy selection signal takes the active level when the input address is coincident with the second redundancy address and takes the inactive level when the input address is incoincident with the second redundancy address; a third redundancy ROM circuit storing a third redundancy address, receiving the input address, and comparing the input address with the third redundancy address to output a third redundancy selection signal, the third redundancy selection signal takes the active level when the input address is coincident with the third redundancy address and takes an inactive level when the input address is incoincident with the third redundancy address; a first local decision circuit coupled to the first and second redundancy ROM circuits to receive the first and second redundancy selection signals, outputting a first error signal when the first redundancy selection signal takes the inactive level and the second redundancy selection signal takes the active level; a second local decision circuit coupled to the second and third redundancy ROM circuits to receive the second and third redundancy selection signals, outputting a second error signal when the second redundancy selection signal takes the inactive level and the third redundancy selection signal takes the active level; and a main decision circuit coupled to the first and second local decision circuit, outputting a main error signal in response to receive at least one of the first and second error signals.