Patent ID: 7898382

Claim:
A method for remotely determining a status of a door lock comprising: a receiver device receiving a broadcast signal from a broadcast device built into the door, said receiver device located remotely from the door, said broadcast signal comprising a door lock status consisting of the status of the door lock, said broadcast signal temporarily powering a trigger receive circuit in the receiver device; said temporarily powered trigger receive circuit activating a main receiver circuit of the receiver device; said activated main receiver circuit receiving the door lock status that is in the broadcast signal; and said main receiver circuit storing the received door lock status in a memory location in the receiver device, wherein the memory location consists of a first field and a second field, wherein the main receiver circuit comprises a logic circuit for performing said storing the door lock status in the memory device, wherein the logic circuit comprises a first AND gate and a second AND gate, wherein the first AND gate comprises a first input having a fixed value of 1, a second input, and an output coupled to the first field of the memory location, wherein the second AND gate comprises a first input having the fixed value of 1, a second input, and an output coupled to the second field of the memory location, wherein the door lock status in the broadcast signal is encoded in bits consisting of a first input bit of 0 or 1 and a second input bit of 0 or 1, and wherein the method further comprises: said second input of the first AND gate receiving the first input bit received from the broadcast signal; said first AND gate performing an AND of the first input bit and the fixed input of 1 at the first input of the first AND gate to generate a first output bit; transmitting the first output bit from the output of the first AND gate to the first field of the memory location; said second input of the second AND gate receiving the second input bit received from the broadcast signal; said second AND gate performing an AND of the second input bit and the fixed input of 1 at the first input of the second AND gate to generate a second output bit; transmitting the second output bit from the output of the second AND gate to the second field of the memory location.