Patent ID: 8222924

Claim:
A first-in, first-out (FIFO) circuit that operates asynchronously, comprising: a data path comprising data latches sequentially connected through data-wire segments; and a control circuit configured to generate control signals for the data latches, comprising: control components sequentially connected to each other through control-wire segments, wherein the control components are configured to asynchronously generate the control signals for the data latches; and repeaters located within the control-wire segments, wherein the repeaters are configured to repeat asynchronous signals communicated between the asynchronous control components, and wherein each repeater receives on a control-wire for a predecessor stage for the repeater a signal from the predecessor stage to cause the repeater to drive a control-wire for a successive stage for the repeater for a predetermined delay and then stop, and, after stopping, the repeater receives on the control-wire for the successive stage a signal to cause the repeater to drive on the control-wire for the predecessor stage a signal for predecessor stage; wherein the control circuit is configured to generate the control signals so that the data path behaves as a FIFO.