Patent ID: 8156299

Claim:
A method of enabling a memory controller associated with a remapping table to enable access to content in a memory system that includes asymmetric memory, the method comprising: receiving, at the memory controller, a request for an Input/Output (I/O) write to a first memory management unit-specified physical address; accessing a remapping table associated with a memory controller; using the remapping table to identify a first memory controller-specified physical address associated with the first memory management unit-specified physical address, the first memory controller-specified physical address corresponding to a first location within asymmetric memory storage; identifying a first disruption region within the asymmetric memory storage that includes the first location; writing contents from the first disruption region to a second disruption region; configuring the memory controller to process, between a time when the contents from the first disruption region begin to be written to the second disruption region and before a time when writing of the contents to be written to the second disruption region has been completed, read instructions from the memory management unit for requested content associated with a second memory management unit-specified physical address that is associated with the disruption region for the first memory-management unit specified physical address by reading the requested content from the first disruption region; and configuring the remapping table to associate the first memory management unit-specified physical address with a second memory controller-specified physical address corresponding to the second disruption region after determining that the contents have been written to the second disruption region, wherein the first disruption region and the second disruption region include physical addresses that are associated with characteristics that include corrupted content or nondeterministic read latency as a result of attempting to read data from the physical addresses concurrent with an I/O write being performed involving the physical addresses.