Patent ID: 6881989

Claim:
A semiconductor integrated circuit comprising base cells arrayed in first and second directions perpendicular to each other, each base cell comprising: an N-type well; a plurality of P-type regions formed in said N-type well and arrayed in said second direction; a P-type well arranged adjacent to said N-type well in said first direction; a plurality of N-type regions formed in said P-type well and arrayed in said second direction; gate lines each formed in said first direction with passing above a channel between adjacent two of said P-type regions and passing above a channel between adjacent two of said N-type regions, a first one of said gate lines not having gate contact regions at both ends thereof, a second one of said gate lines having gate contact regions at both ends thereof; an N-type well contact region formed in said N-type well on a side of said first directional end of said first one of said gate lines; a P-type well contact region formed in said P-type well on a side of the opposite first directional end of said first one of said gate lines; Intra-cell interconnections formed in a first wiring layer; a first power supply line connected to said N-type well contact region with passing in said second direction, said first power supply line formed in a second wiring layer above said first wiring layer; and a second power supply line connected to said P-type well contact region with passing in said second direction said second power supply line formed in said second wiring layer.