Patent ID: 7297998

Claim:
A semiconductor device, comprising: a bit line interlayer insulating layer over a semiconductor substrate; first and second bit line patterns adjacent to each other on the bit line interlayer insulating layer; a buried contact interlayer insulating layer between the first and second bit line patterns, wherein a portion of the buried contact interlayer insulating layer includes a contact hole defined therein; a contact hole spacer covering a side wall of the contact hole; and a contact hole plug on the contact hole spacer and filling the contact hole, wherein the contact hole extends between the first and second bit line patterns through the buried contact interlayer insulating layer and the bit line interlayer insulating layer and exposes a side wall of the first bit line pattern, wherein the buried contact interlayer insulating layer has an etching selectivity ratio lower than the bit line interlayer insulating layer, wherein a first portion of the first bit line pattern is adjacent to and exposed by the contact hole and has a first width along a direction, and wherein a second portion of the first bit line pattern adjacent to the first portion of the first bit line pattern has a second width along the direction greater than the first width.