Patent ID: 7061321

Claim:
An amplifier system for connection through interconnects to a read head, said amplifier system comprising: a first and second transistors each having a first terminal, a second terminal, and a base terminal, wherein said two base terminals are respectively connected to the interconnects through which an input signal is transmitted from the read head to said transistors, wherein said first terminals are connected to outputs of said amplifier system; a bias voltage control circuit connected to said first and second transistors adapted to provide a bias voltage across the base terminals of the first and second transistors; and a common mode voltage control circuit connected between first terminals of the first and second transistors and the base terminals of the first and second transistors to provide feedbacks from the first terminals to the base terminals of the first and second transistors, wherein said bias voltage control circuit comprises a third and fourth transistors each having a first terminal, a second terminal, and a base terminal, wherein said second terminals of said first and third transistors are connected, and said second terminals of said second and fourth transistors are connected, wherein bias voltages are respectively applied to the base terminals of said third and fourth transistors, and wherein said bias voltage control circuit further comprises a voltage generation circuit for generating a bias voltage, said voltage generation circuit having an output connected to an amplification circuit with an amplification coefficient +K and also connected to another amplification circuit with an amplification coefficient −K, and wherein outputs of the amplification circuits are connected to base terminals of said third and fourth transistors, providing bias voltages +BIAS and −BIAS on said base terminals.