Patent ID: 7260106

Claim:
A system to manage energy usage of a processor, comprising: a data communication network; a transmitter, coupled to the data communication network, to invoke a protocol state machine to send a packet and to wait for an acknowledgment of receipt; a receiver, in communication with the transmitter coupled to the data communication network, to receive, process, and verify the packet and to send the acknowledgment of receipt of the packet; an incoming packet buffer, coupled to the protocol state machine in the transmitter, to store an incoming packet to be transmitted by the transmitter; and a processor, coupled to the protocol state machine in the transmitter, the processor enters a low power, low clock rate mode while waiting for the acknowledgment of receipt of the packet from the receiver, wherein the protocol state machine manages a power level of the processor based on a utilized capacity of the buffer and the transmitter awakens when the incoming packet buffer reaches a low water mark.