Patent ID: 7719854

Claim:
An apparatus comprising: one or more Input/Output (I/O) conductors, wherein the I/O conductors pass through a hermetic seal such that a first end of the I/O conductors resides on a non-hermetic side of the hermetic seal and a second end of the I/O conductors resides on a hermetic side of the hermetic seal within a hermetically sealed interior of a hermetically sealed metal case of the apparatus; a printed circuit interconnect substrate residing on the hermetic side of the hermetic seal, wherein the printed circuit interconnect substrate includes a multi-layer circuit board comprising a buried signal layer between first and second conductive layers, wherein each conductive layer is electrically connected to a constant voltage to form a constant voltage plane, wherein the multi-layer circuit board is arranged substantially parallel to the hermetic seal and normal to the I/O conductors to provide electrical shielding, and wherein one I/O conductor provides an electrical connection to the constant voltage plane; and one or more ceramic chip capacitors mounted on the printed circuit interconnect substrate and mounted within the hermetically sealed interior of the hermetically sealed metal case, wherein a first end of each capacitor is electrically connected via printed circuit interconnect to the second end of an I/O conductor and a second end of each capacitor is electrically connected via the printed circuit interconnect to the metal case.