Patent ID: 7155642

Claim:
An interleaver for a turbo encoder in a Universal Mobile Telecommunications System (UMTS), comprising: a register for updating and registering a plurality of parameters for setting an operating condition of the interleaver; an address calculator for generating a finally interleaved address using an inter-row permutation pattern T(j), an intra-row permutation pattern increment arrangement value incr(j) and an intra-row permutation basic sequence s(i) provided from the register, comprising: an intra-row permutation pattern generator for calculating an intra-row permutation pattern value using the intra-row permutation pattern increment arrangement value incr(j), comprising: a first adder for adding a previous intra-row permutation pattern read from an intra-row permutation pattern memory of the register with the intra-row permutation pattern increment arrangement value incr(j) to thereby output a first add value; a second adder for adding the first add value output from the first adder to a prime number −(p−1) to thereby output a second add value; a first multiplexer for selectively outputting one of the first and second add values from the first and second adders; a sign detector connected to the second adder and the first multiplexer for providing a selection control signal to the first multiplexer so that the first multiplexer outputs the second add value as an address of the intra-row permutation basic sequence s(i) when the second add value has a positive value, and outputs the first add value as an address of the intra-row permutation basic sequence when the second add value has a negative value; and a second multiplexer for outputting a predetermined initial value during an initial operation of the intra-row permutation pattern generator, and then providing the output of the first multiplexer as a read address of the intra-row permutation pattern storage arrangement device for a succeeding intra-row permutation pattern; an intra-row permutation pattern storage arrangement device for storing intermediate data while the intra-row permutation pattern generator calculates the intra-row permutation pattern; and a final address generator for calculating an address of finally interleaved data using the inter-row permutation pattern T(j) from the register and the intra-row permutation basic sequence s(i) corresponding to the intra-row permutation pattern value generated by the intra-row permutation pattern generator; and a data storage device for storing data input to the turbo encoder and outputting data corresponding to the address generated by the address calculator.