Patent ID: 7652740

Claim:
An array substrate for use in a liquid crystal display device, comprising: a gate electrode, a gate line and a gate pad electrode on a substrate, wherein all of the gate electrode, the gate line and the gate pad electrode have a double-layered structure including a first barrier metal layer and a first copper layer, wherein the first barrier metal layer is interposed between the substrate and the first copper layer, wherein sides of the first copper layer are inside of sides of the first barrier metal layer and wherein the first barrier metal layer and the first copper layer have a smooth taper shape without any steps on their sides; a buffer layer between the substrate and the first barrier metal layer, wherein the buffer layer is a double layer; a gate insulation layer on the substrate covering the double-layered gate electrode, gate line and gate pad; an active layer and an ohmic contact layer sequentially formed on the gate insulation layer and over the gate electrode; a data line on the gate insulation layer crossing the gate line, source and drain electrodes contacting the ohmic contact layer, and a data pad electrode on the gate insulation layer, wherein all of the data line, the source and drain electrodes, and the data pad electrode have a double-layered structure including a second barrier metal layer and a second copper layer, wherein the second barrier metal layer is interposed between the substrate and the second copper layer, wherein each of the first and second barrier metal layers includes a metallic material that has a good adhesive characteristic to the substrate and prevents a reaction between the second copper layer and both the active layer and the ohmic contact layer, and wherein the metallic material is one of tantalum (Ta) and titanium (Ti); a passivation layer formed on the gate insulation layer to cover the double-layered data line, source and drain electrodes, and data pad electrode, wherein the passivation layer has a drain contact hole exposing the drain electrode, a gate pad contact hole exposing the gate pad electrode, and a data pad contact hole exposing the data pad; and a pixel electrode, a gate pad terminal and a data pad terminal all of which are formed of a transparent conductive material on the passivation layer.