Patent ID: 7191317

Claim:
An execution unit for use in a computer system for conditionally carrying out an operation defined in a computer instruction, the execution unit comprising: first and second input stores for holding respective first and second source operands on which the operation defined in the instruction is to be carried out, wherein each input store holds a plurality of objects of a predetermined size, each object defining one of a plurality of lanes, a maximum number of lanes being determined by a smallest allowable predetermined object size; a plurality of operators associated respectively with said lanes for carrying out the operation specified in the instruction on objects in corresponding lanes of said first and second input stores; a destination buffer for holding the results of the operation on a lane-by-lane basis; and selecting means for determining independently for each lane, in dependence on stored condition values derived from the results of executing a prior instruction sequence, whether or not the operation is to be executed on objects in that lane; wherein a number of stored condition values corresponds to said maximum number of lanes in each of said first and second input stores, a prior operation being operable to generate said condition values so that, when the source operands have less than the maximum number of lanes, two or more condition values are set to a same value so that each individual condition value is generated regardless of a degree of packing of the first and second source operands.