Patent ID: 6849944

Claim:
An integrated circuit package, comprising: a die associated with an integrated circuit, the die having a bottom surface; a die pad having a top surface opposite the bottom surface of the die; at least two bump pad traces each coupled to the top surface of the die pad; a plurality of traces each coupled to the top surface of the die pad in a corresponding inter-bump pad region between adjacent bump pad traces; and a plurality of solder bumps each coupling the die to the die pad at a corresponding bump pad trace to provide electrical connectivity between circuitry associated with the die and circuitry associated with the die pad; each inter-bump pad region being free from any solder mask material deposited to control collapse of the die towards the die pad during a reflow process for bonding the die to the die pad using the solder bumps, a supporting structure that contacts the die during the reflow process having been used instead to substantially prevent collapse of the die towards the die pad.