Patent ID: 7633785

Claim:
A semiconductor memory device comprising a plurality of memory chips and an interface chip that are stacked, each memory chip comprising a control signal setting unit, which sets input signals applied to first and second input nodes as less significant 2-bit control signals of n-bit control signals, performs a logic AND operation on the less significant 2-bit control signals to generate AND operated signals, performs a logic XOR operation on each of the AND operated signals and each bit signal of more significant n-2-bit input signals applied to third to n-th input nodes to set the n-2-bit control signals, outputs the signal applied to the second input node through a first output node, inverts the signal applied to the first input node to output the inverted signal through a second output node, and outputs the more significant n-2-bit input signals through third through n-th output nodes, respectively, wherein first through n-th output nodes of one of two adjacent memory chips are respectively connected to first through n-th input nodes of the other of the two adjacent memory chips.