Patent ID: 7881290

Claim:
A serial interface circuit comprising: a plurality of serial transmitters for a plurality of channels, respectively; and a plurality of serial receivers provided for said plurality of channels and connected with said plurality of serial transmitters, respectively, wherein each of said plurality of serial transmitters transmits a serial signal, and each of said plurality of serial receivers comprises: a receiver circuit configured to convert the serial signal into a data sequence; n register groups configured to shift the data sequence, wherein n is an integer more than 1; a data processing circuit configured to perform a data process on said data sequence based on n outputs of said n register groups and a detection result; and a header detecting circuit configured to detect a header of the data sequence when b register groups from a first register group to a bth register group among said n register groups shift the data sequence, and to output the detecting result to said data processing circuit, wherein said serial transmitter converts c-bit (c is an integer more than 1) data TD[c−1: 0 ] synchronous with a system clock signal into a serial signal and transmits the serial signal, and said receiver circuit converts the serial signal into the data sequence D[m−1: 0 ] of m (m is a positive integer) data, said header detecting circuit receives the data sequence and the shifted data sequences, D[(b*m−1):((b−1)*m−a+1)] (a is an integer satisfying a<c) to be supplied to said b register groups, compares a header bit sequence indicating a-bit data which specifies a start bit of the data sequence D[m−1: 0 ] and a bit sequence indicating a start bit of the data sequence D[(b*m−1):((b−1)*m−a+1)], and outputs the detecting result to said data processing circuit when the bit sequence indicating the start bits of the data D[(b*m−1)], D[(b*m−2)], . . . D[(b−1)*m] of the data sequence D[(b*m−1):((b−1)*m−a+1)] is equal to the header bit sequence.