Patent ID: 8566516

Claim:
A memory module comprising: 2*N dynamic random access memory (DRAM) devices each having a capacity of M, wherein the 2*N DRAM devices comprising: a first group of N DRAM devices; and a second group of N DRAM devices, wherein each of the N DRAM devices in the first group shares a distinct refresh control signal with a respective DRAM device in the second group; emulation logic configured to emulate an interface protocol of two emulated DRAM devices each having a capacity of N*M, wherein a first of the two emulated DRAM devices includes the N DRAM devices from the first group, and a second of the two emulated DRAM devices includes the N DRAM devices from the second group; an interface circuit configured to receive from a memory controller a refresh command for the two emulated DRAM devices, the interface circuit including: a calculation unit configured to determine offset timings for N independently controlled staggered refresh cycles, wherein exactly one DRAM device from the first group and one DRAM device from the second group are refreshed in each of the independently controlled staggered refresh cycles, the offset timings providing timings of each of the independently controlled staggered refresh cycles; and a scheduler configured to order independently controlled staggered refresh commands directed to the 2*N DRAM devices in the first and the second groups based on the offset timings determined by the calculation unit.