Patent ID: 8203888

Claim:
A non-volatile semiconductor storage device comprising: a memory cell array including an array of NAND cell units, each of the NAND cell units including a memory string having a plurality of memory cells connected in series and selection transistors each connected to an end of the memory string; a plurality of word lines each commonly connected to those of the memory cells aligned along a first direction; a plurality of bit lines each connected to one end of each of the NAND cell units; a source line connected to the other end of each of the NAND cell units; and a plurality of sense amplifier circuits, each of the sense amplifier circuits being configured to determine data retained in the memory cell by supplying a read current to the bit line and detecting a magnitude of the read current flowing through the bit line after a setup time required for the read current to reach a steady state, the sense amplifier circuits being configured to carry out a plurality of read cycles on a plurality of the bit lines each connected to any one of the memory cells that are selected by a selected one of the word lines, during second and subsequent read cycles, the sense amplifier circuits being configured to stop supplying the read current to any one of the bit lines when it is determined in a preceding read cycle that a current not less than a certain determination current level flows therethrough, while keep supplying the read current to remaining bit lines, and the setup time of the bit lines in a first read cycle being set shorter than the setup time of the bit lines in the second and subsequent read cycles.