Patent ID: 8458539

Claim:
An apparatus comprising: a plurality of vector registers, each associated with a state of a state machine, including a first vector register associated with a first state of the state machine, wherein each bit is set in response to a code, a request, or an event associated with a transaction identifier; a first group of registers, associated with the first state, comprising a first mask register and a first arm register, wherein contents of the first mask register are used to inhibit some bit positions in the first arm register, wherein the first mask register and the first arm register are programmed to detect a first request or a first event; a plurality of comparators comprising a first comparator to compare first debug data with contents of the first mask register and the first arm register to determine a comparison result to be stored in one or more bits of the first vector register; and a triggering logic unit to determine whether or not to trigger a fire event based at least on the comparison result stored in the one or more bits of the first vector register and a corresponding comparison result stored in one or more corresponding bits of others of the plurality of vector registers.