Patent ID: 6924664

Claim:
A field programmable gate array (FPGA) comprising: an interconnect structure for routing signals on said FPGA; and a plurality of logic heads that receive a plurality of logic head inputs from said interconnect structure and output a plurality of logic head outputs to said interconnect structure, said logic heads comprising: (1) a plurality of logic blocks that are capable of performing combinatorial logic on said logic head inputs, said plurality of logic blocks formed in a cascaded manner such that the outputs of some logic blocks are provided as inputs to other logic blocks; (2) an input section that receives said plurality of logic head inputs and routes said plurality of logic head inputs to said plurality of logic blocks; and (3) an output section that interfaces to and outputs said logic head outputs to said interconnect structure; wherein a one of said logic head outputs of said logic head are output onto a plurality of lines of said interconnect structure through said output section, said output section comprising: a plurality of output buffers corresponding with each of said plurality of lines, said output buffers receiving said one of said logic head outputs and driving said one of said logic head outputs onto its corresponding line; and a programmable switch that can switch another one of said plurality of output buffers from its corresponding line to a different one of said corresponding line such that the logic head output is double driven onto one of said plurality of lines.