Patent ID: 7474571

Claim:
A level shifter configured to level shift an input signal from a first voltage domain corresponding to a first supply voltage to a second voltage domain corresponding to a second supply voltage, the level shifter comprising: a first P-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to receive the second supply voltage and coupled to receive a signal on a gate terminal of the first PMOS transistor; a second PMOS transistor having a drain coupled to a first node, a gate coupled to receive the input signal, and a source coupled to a drain of the first PMOS transistor; a first N-type metal-oxide-semiconductor (NMOS) transistor having a drain coupled to the first node, a gate coupled to receive the input signal, and a source coupled to ground; and a second NMOS transistor coupled in parallel with the first NMOS transistor and having a gate coupled to an enable signal, wherein, if the enable signal indicates that the input signal is disabled, the second NMOS transistor participates in holding an output of the level shifter steady at a predetermined voltage level.