Patent ID: 8458434

Claim:
A method for managing memory of a computing device including: mapping an address from an address space of a physically-mapped device without a memory management unit (MMU) to a first address of a common address space so as to create a first mapping instance that is a one-to-one mapping between the address from the address space of the physically-mapped device and the address of the common address space, wherein the common address space is composed of a set of addresses that can be read from, and written to, by the physically-mapped device, a processor with a memory management unit, and an MMU device with a memory management unit; encapsulating an existing processor mapping that maps an address from an address space of the processor to a second address of the common address space to create a second mapping instance; creating a third mapping instance between an address from an address space of the memory-management-unit (MMU) device and a third address of the common address space, wherein the first, second, and third addresses of the common address space may be the same address or different addresses; and manipulating the first, second, and third mapping instances using the same function calls.