Patent ID: 8379431

Claim:
A semiconductor memory device, comprising: a memory cell array including memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having a variable resistance value, the memory cell array being configured by a plurality of memory strings each including plural ones of the memory transistors connected in series, the memory strings being disposed with their longer direction extending in a first direction; word lines disposed with their longer direction extending in a second direction orthogonal to the first direction, and each connected commonly to the gate electrodes of plural ones of the memory transistors lined up in the second direction; a plate line disposed to sandwich the variable resistance film between itself and the gate electrode; a plurality of first voltage terminals configured to supply a certain voltage to first ends of the plurality of memory strings, respectively; and a plurality of second voltage terminals configured to supply a certain voltage to second ends of the plurality of memory strings, respectively.