Patent ID: 8781046

Claim:
A device ( 1 ) for reconstructing a clock signal of a baseband serial signal (NRZ-D), including: a pulse generator circuit ( 2 ) designed to generate pulses at each transition, rising or falling, of the baseband serial signal (NRZ-D); a phase-locked loop ( 5 ) including a voltage-controlled oscillator ( 6 ) which generates an oscillator output signal (VCO-S) and a filter ( 7 ) providing a setpoint signal (VCO-E) to the oscillator ( 6 ), the phase-locked loop ( 5 ) also including a switch ( 8 ) inserted between the oscillator ( 6 ) and the filter ( 7 ) whose switching is controlled by the output (Cde-S) of the pulse generator circuit ( 2 ), and in which the filter ( 7 ) is a low-pass filter, such that: in the presence of a pulse generated by the pulse generator circuit ( 2 ), the switch ( 8 ) is closed and the filter ( 7 ) then averages the oscillator output signal (VCO-S) passing through the switch to provide the setpoint signal (VCO-E) to the oscillator; in the absence of a pulse generated by the pulse generator circuit ( 2 ), the switch ( 8 ) is open and the filter ( 7 ) then stores a constant level signal to deliver the setpoint signal (VCO-E) to the oscillator; wherein the filter ( 7 ) comprises a first and a second RC cell respectively having a first cutoff frequency, and a second cutoff frequency, the first RC cell cutoff frequency being lower than the second RC cell cutoff frequency, the first RC cell providing a storage function when there is an absence of transitions in the baseband serial signal, and the second RC cell providing filtering of phase noise in the received message.