Patent ID: 6969660

Claim:
A semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate having a major surface including first and second regions and a boundary area formed between the first and second regions in contact therewith; forming a first lower electrode layer on portions of the first insulating film in the first region and in the boundary area, and removing a portion of the first insulating film in the second region to expose the major surface; forming a second insulating film on the first lower electrode layer in the first region and in the boundary area and on the major surface in the second region, the second insulating film having a film material or a film thickness different from that of the first insulating film; forming a second lower electrode layer on portions of the second insulating film in the second region and in the boundary area, and removing a portion of the second insulating film in the first region to expose the first lower electrode layer; etching the major surface in the first and second regions to be self-aligned with the first and second lower electrode layers, thereby forming trenches for device isolation in the first and second regions; filing the trenches in the first and second regions with an insulating layer to form device isolation regions; forming an upper electrode layer on the first and second lower electrode layers; and patterning the first and second lower electrode layers and the upper electrode layer by etching, thereby forming first and second gate electrodes in the first and second regions, respectively.