Patent ID: 7852305

Claim:
A flat panel display, comprising: a plurality of pixel electrodes; a first multiplexer for receiving a high working voltage and a low working voltage and controlled by an off-controlling signal to output an input low power voltage; a second multiplexer for receiving the high working voltage and a zeroth clock signal and controlled by the off-controlling signal to output a zeroth input clock signal; a third multiplexer for receiving the high working voltage and a first clock signal and controlled by the off-controlling signal to output a first input clock signal; and at least a gate driver having an amorphous silicon gate structure and (N+1) shift registers, wherein N is a positive integer and n is a positive integer ranging from 1 to (N+1), the gate driver is electrically connected to the pixel electrodes, and the n th shift register comprises: a SR flip-flop, which has a set terminal, a reset terminal, an output terminal and an inverting output terminal, and is electrically connected to the high working voltage and the low working voltage, wherein the set terminal is coupled to an (n−1) th output signal of the (n−1) th shift register, the reset terminal is coupled to an (n+1) th output signal of the (n+1) th shift register; a first transistor, which is formed on a glass substrate and has a control terminal coupled to the output terminal and a first terminal for receiving an M th input clock signal, wherein M=1 if n is even and M=0 if n is odd; and a second transistor formed on the glass substrate, wherein the second transistor has a control terminal coupled to the inverting output terminal, a first terminal coupled to a second terminal of the first transistor for outputting an n th output signal, and a second terminal coupled to receive the input low power voltage, wherein: in response to the off-controlling signal being transformed from a high-level voltage to a low-level voltage when the flat panel display is turned off, the input low power voltage outputted from the first multiplexer is transformed to the high working voltage, the zeroth input clock signal outputted from the second multiplexer is transformed to the high working voltage, the first input clock signal outputted from the third multiplexer is transformed to the high working voltage to make the first transistor or the second transistor of the n th shift register turn on and output the n th output signal at the high working voltage to cause discharge of the pixel electrodes connected to the n th shift register.