Patent ID: 7127616

Claim:
A semiconductor integrated circuit configured for connection to a first external ROM and a second external ROM, comprising: a first decryption code block storing a decryption code; a first decoder circuit connected to the first decryption code block and decrypting encrypted data stored in the first external ROM, by utilizing the decryption code in the first decryption code block; a configuration circuit connected to the first decoder circuit; an FPGA circuit connected to the configuration circuit, wherein the circuit structure of the FPGA circuit is determined by the configuration circuit; a second decryption code block connected to the configuration circuit and comprising a circuit structure, determined by the configuration circuit, for storing a decryption code; a second decoder circuit connected to the second decryption code block, wherein the second decoder circuit decrypts encrypted data stored in the second external ROM by using the decryption code in the second decryption code block; a CPU connected to the second decoder circuit, the CPU being operable in response to encrypted data stored in the second external ROM; and an internal circuit connected to the FPGA circuit and the CPU, the circuit operation of which is determined by the FPGA circuit and the CPU.