Patent ID: 6839884

Claim:
A method of validating a hardware design, the method comprising: receiving a representation of the hardware design, the hardware design including a plurality of modules having a hierarchical relationship, the representation including a plurality of variables with which logical signals are associated; receiving information regarding intended flow of the logical signals among the plurality of variables; automatically generating a plurality of checks based upon the representation of the hardware design and the information regarding the intended flow of the logical signals, each of the plurality of checks being symptomatic of one or more errors relating to the flow of one or more of the logical signals among the plurality of variables; validating the hardware design by performing validation processing on the plurality of modules by making use of validation processing previously performed with respect to any of the plurality of modules based upon the hierarchical relationship, said making use of validation processing previously performed including: identifying identical modules within the plurality of modules; obtaining a result of validation processing performed with respect to one of the identical modules; and reusing the result for at least one other identical module of the identical modules.