Patent ID: 7653168

Claim:
A method comprising: applying a clocking signal to each of: a first clocked memory element, a second clocked memory element, a third clocked memory element and a fourth clocked memory element, where the first clocked memory element, the second clocked memory element, the third clocked memory element and the fourth clocked memory element are connected in series in a closed data loop, where an output of the first clocked memory element is directly connected to an input of the second clocked memory element, an output of the second clocked memory element is directly connected to an input of the third clocked memory element, an output of the third clocked memory element is directly connected to an input of the fourth clocked memory element, and an output of the fourth clocked memory element is directly connected to the input of the first clocked memory element; checking a relation between digital values stored in the first clocked memory element, the second clocked memory element, the third clocked memory element and the fourth clocked memory element; and outputting a signal from the loop at a frequency less than the clocking signal; wherein checking the relation between digital values stored in the third clocked memory element and the fourth clocked memory element occurs on one of: a rising clock edge and a falling clock edge, and checking a relation between digital values stored in the first clocked memory element and the second clocked memory element occurs on the other of: the rising clock edge and the falling clock edge.