Patent ID: 8344925

Claim:
A system for adaptive timing control in successive approximation analog-to-digital conversion of a sampled analog signal within a conversion period comprising: a state machine unit operating responsive to a state clocking signal to maintain a set of successive approximation states including at least one sampling state and a plurality of hit conversion states; a reference generating unit operably coupled to said state machine unit, said reference generating unit generating a quantization level reference for each of said bit conversion states; a comparator unit operably coupled to said state machine and reference generating units, said comparator unit executing responsive to a comparator clocking signal to compare the sampled analog signal with said quantization level reference for determining a bit value for each said bit conversion state; and, a clock generator unit operably coupled to said state machine and comparator units, said clock generator unit operating responsive to a triggering signal to adaptively define said state and comparator clocking signals for each of said successive approximation states, said clock generator unit thereby adaptively delaying execution of said comparator unit in each said bit conversion state until said reference generating unit substantially completes generation of said quantization level reference therefor.