Patent ID: 7892942

Claim:
A method of forming a semiconductor construction, comprising: forming a patterned mask over a semiconductor material; the patterned mask comprising tunnel dielectric, and comprising polysilicon over the tunnel dielectric; while using the patterned mask to define a location of an opening, removing semiconductor material from said location to form the opening; forming a silicon dioxide liner within the opening and directly against the semiconductor material; forming polysilazane along the liner within the opening to a level that only partially fills the opening and leaves a remainder of the opening unfilled, the polysilazane being directly against the silicon dioxide liner; converting the polysilazane to a silicon dioxide-containing composition; said converting using a temperature of less than 300° C., and using gaseous ozone; forming high density silicon dioxide over the silicon dioxide-containing composition to fill the remainder of the lined opening; and forming a pair of memory cells on opposing sides of the opening, the memory cells comprising the tunnel dielectric and the polysilicon; the memory cells further comprising intergate dielectric material over the polysilicon, and control gate material over the intergate dielectric material; the tunnel dielectric being laterally adjacent the high density silicon dioxide, and being elevationally above the silicon dioxide-containing composition; an entirety of the intergate dielectric material being elevationally above all of the high density silicon dioxide that is between the pair of the memory cells.