Patent ID: 7007099

Claim:
In a combination including an HDLC formatter and a message processing core, a high speed message exchange interface for transferring messages between said HDLC formatter and said message processing core with minimal utilization of processing resources, comprising: a memory shared by said HDLC formatter and said message processing core; a handshaking system for coordinating message storage and retrieval in said shared memory by said HDLC formatter and said message processing core, said handshaking system implementing an information exchange mechanism whereby said HDLC formatter and said message processing core share memory location information relative to messages said HDLC formatter and said message processing core have respectively stored and retrieved in said shared memory; said information exchange mechanism being periodically initiated by said processor core accessing said HDLC formatter; said handshaking system including a shared storage location in said HDLC formatter containing pointers that provide information about locations in said shared memory where receive messages have been stored and transmit messages have been retrieved by said HDLC formatter, where transmit messages have been stored by said message processing core, and where receive messages can be stored by said HDLC formatter; said pointers including first and second pointers written by said HDLC formatter and respectively indicating where messages have been stored and retrieved in said shared memory by said HDLC formatter, and third and fourth pointers written by said message processing core and respectively indicating where messages have been stored in said shared memory by said message processing core and where messages can be stored by said HDLC formatter; said pointers being index pointers that point to locations in corresponding FIFOs, each FIFO containing pointers to message blocks in said shared memory; said FIFOs including a RCV FIFO for Receive messages placed in said shared memory by said HDLC formatter and a TX FIFO for Transmit messages placed in said shared memory by said message processing core; said shared location containing said pointers being part of said HDLC formatter but accessible by said message processing core via single-beat PCI bus accesses; said first pointer pointing to a location in said RCV FIFO that contains a pointer to a last Receive message stored in said shared memory by said HDLC formatter; said second pointer pointing to a location in said TX FIFO that contains a pointer to a last Transmit message retrieved from said shared memory by said HDLC formatter; said third pointer pointing to a location in said RCV FIFO that contains a pointer to a last Receive message buffer area made available in said shared memory by said message processing core; and said fourth pointer pointing to a location in said TX FIFO that contains a pointer to a last Transmit message stored in said shared memory by said message processing core.