Patent ID: 8654589

Claim:
A memory, comprising: a word line; a charge pump coupled to the word line; and a charge pump control circuit coupled to the charge pump, wherein the charge pump control circuit is configured to turn on the charge pump if a word line voltage on the word line is lower than a first predetermined threshold voltage and turn off the charge pump if the word line voltage is higher than a second predetermined threshold voltage, wherein the charge pump control circuit comprises a current detection circuit, wherein the current detection circuit comprises a current mirror circuit, wherein the current mirror circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, and wherein a drain of the second PMOS transistor is coupled to a drain of the first NMOS transistor, a gate of the first NMOS transistor, and a gate of the second NMOS transistor.