Patent ID: 6934896

Claim:
A time shift circuit for a semiconductor test system for changing a delay timing of a portion of a test pattern for testing a semiconductor device, comprising: a multiplexer for selectively producing delay value data indicating a value of time shift for a specific portion of test pattern in response to a shift command signal; a vernier delay unit for producing timing vernier data based on programmed delay data prepared in the semiconductor test system and the delay value data selected by the multiplexer; and a timing generator for generating a timing edge for the specific portion of the test pattern based on the timing vernier data from the vernier delay unit; wherein the shift command signal sets either a normal mode where predetermined delay value data is selected by the multiplexer or a time shift mode where delay value data for shifting the timing edge in real time is selected by the multiplexer; and wherein the vernier delay unit, comprising: an adder for summing the programmed delay data and the selected delay value data from the multiplexer; a decoder for decoding higher bits of output data of the adder to produce a register select signal; and a series of delay registers for delaying the timing vernier data configured by lower bits of the output data of the adder where one of the delay registers is selected by the register select signal to receive the timing vernier data as a first delay register.