Patent ID: 8520461

Claim:
A method of operating a memory device, comprising: identifying a first plurality of memory blocks each comprising at least one substandard memory cell; identifying a second plurality of memory blocks each comprising no substandard memory cells; generating a plurality of candidate first row address codes by omitting different one or more bits of a row address corresponding to two or more memory blocks, where at least one of the two or more memory blocks is from the first plurality of memory blocks; selecting one of the plurality of candidate first row address codes as a first row address code; generating a second row address code by omitting one or more bits of a row address corresponding to at least two memory blocks from the second plurality of memory blocks; performing a first refresh operation simultaneously on the memory blocks having the first row address code value using a first refresh period; and performing a second refresh operation simultaneously on the memory blocks having the second row address code value with a second refresh period longer than the first refresh period.