Patent ID: 7107511

Claim:
A Low Density Parity Check (LDPC) code Log-Likelihood Ratio (LLR) decoder that is operable to decode a bit within a signal, the decoder comprising: an initialization functional block that computes a Log-Likelihood ratio (LLR) of a channel metric and assigns an initial value of a variable node extrinsic information value to be the LLR of the channel metric, the channel metric corresponding to a communication channel over which the signal is communicated; a check node processing functional block that computes a check node extrinsic information value using the value of the variable node extrinsic information value by employing min* processing, min** processing, max* processing, or max** processing; a variable node processing functional block that computes a variable node extrinsic information value using the value of the variable node extrinsic information value and the check node extrinsic information value; wherein the variable node processing functional block provides the variable node extrinsic information value as feedback to the check node processing functional block to perform a plurality of decoding iterations; and a variable bit estimation functional block that estimates a value of the bit within the signal using the variable node extrinsic information value.