Patent ID: 7738486

Claim:
A SerDes configured to support multiple data rates, the SerDes comprising: a serializer portion including: a first bypass stage configured to receive a plurality of transmit signals, wherein the first bypass stage passes the transmit signals unchanged to a multiplexer stage when the transmit signals are at a first aggregate data rate and decodes the transmit signals when the transmit signals are at a second aggregate data rate; the multiplexer stage coupled with an output of the bypass stage and configured to receive the unchanged transmit signals or the decoded transmit signals and generate a plurality of multiplexed signals; and a dynamic multiplexer configured to: combine two of the multiplexed signals into a single output signal; or pass one of the multiplexed signals through unchanged as one of two or more output signals depending on the aggregate data rate of the transmit signals; and a deserializer portion including: a demultiplexer stage configured to receive and demultiplex a plurality of retimed signals, the number of retimed signals and the number of demultiplexed signals depending on the aggregate data rate of one or more receive signals received by the deserializer portion, the one or more receive signals being at the first aggregate data rate or the second aggregate data rate; and a second bypass stage coupled with the demultiplexer and configured to: pass the demultiplexed signals through unchanged when the one or more receive signals are at the first aggregate data rate or encode the demultiplexed signals when the one or more receive signals are at the second aggregate data rate.