Patent ID: 7835197

Claim:
An integrated semiconductor memory, comprising: a clock connection to apply a clock signal; a memory cell array with memory cells to store data of a first data record that has a first or a second data value; a data generator circuit with a first input connection to apply the data of the first data record, with a first output connection to output data of a second data record that has a first or a second data value, and with a second output connection to generate a first control signal; and an evaluation unit with input to receive the first data record, the second data record and a second control signal, the second control signal being delayed by one clock period of the clock signal with respect to the first control signal; wherein the data generator circuit is adapted to generate the data values of the data of the second data record in dependence on the evaluation of the data values of the first and second data record and the second control signal from the evaluation unit.