Patent ID: 8209139

Claim:
A capacitance evaluation circuit, comprising: a capacitive voltage divider comprising a switch circuit, a first capacitor and a second capacitor, wherein the switch circuit is coupled to the first and second capacitors, the switch circuit is controlled by a first clock signal and a second clock signal, which is an inversion signal of the first clock signal, and a voltage variation of a first terminal of the first capacitor is coupled to a first terminal of the second capacitor based on a conduction state of the switch circuit; an analog-to-digital converter (ADC), coupled to the capacitive voltage divider, converting a voltage of the first terminal of the second capacitor into a first digital signal; and a processing module, coupled to the ADC, detecting a capacitance of the second capacitor and a capacitance variation of the second capacitor according to the first digital signal of the ADC and a parameter of the ADC; wherein the ADC comprises: a switch-sample-capacitor circuit having a first input terminal and an output terminal, wherein the first input terminal of the switch-sample-capacitor circuit is coupled to the first terminal of the second capacitor of the capacitive voltage divider, and the switch-sample-capacitor circuit is controlled by the first clock signal and the second clock signal to sample the voltage of the first terminal of the second capacitor of the capacitive voltage divider; an operation amplifier having a first input terminal coupled to the output terminal of the switch-sample-capacitor circuit, a second input terminal, a first output terminal and a second output terminal; a comparator having a first input terminal coupled to the first output terminal of the operation amplifier, a second input terminal coupled to the second output terminal of the operation amplifier, and an output terminal for outputting a second digital signal; a latch, receiving the second digital signal outputted from the comparator, wherein the latch outputs the second digital signal as a third digital signal under triggering of the first clock signal; an inverter, inverting the third digital signal; a counter, counting the third digital signal to generate the first digital signal; and a switch-capacitor circuit coupled to the second input terminal of the operation amplifier and controlled by the first clock signal, the second clock signal, the third digital signal and the inverted third digital signal.