Patent ID: 8048330

Claim:
A method, comprising: forming a first dielectric layer above a transistor comprising a gate electrode structure; forming a first interlayer dielectric material above said first dielectric layer using a specified precursor material, said first interlayer dielectric material having a first removal rate with respect to a specified chemical mechanical polishing recipe; forming a second interlayer dielectric material above said first interlayer dielectric material using said specified precursor material, said second interlayer dielectric material having a second removal rate with respect to said specified chemical mechanical polishing recipe, said second removal rate differing from said first removal rate; and planarizing a surface of a layer stack comprising said first dielectric layer and said first and second interlayer dielectric materials by performing a planarization process comprising a chemical mechanical polishing process performed on the basis of said specified chemical mechanical polishing recipe wherein at least a portion of said second interlayer dielectric material remains above at least a portion of said first interlayer dielectric material after performing said planarization process.