Patent ID: 8225063

Claim:
A synchronous dynamic random access memory (SDRAM) module coupled to a memory accessing device by way of a memory adapter, said memory adapter comprising a device interface for communicating with said memory accessing device providing a first clock at a first clock rate, said device interface being operable to receive an SDRAM command, a row address and a column address for a data read or write of a burst of data units, and a data unit to be written to said SDRAM module having an expected bit size, wherein said SDRAM module comprises: a memory interface for interconnection with said memory adapter, said memory interface comprising: a memory clock line for receiving from said memory adapter a memory clock at a frequency equal to n times said first clock, and phase-locked with said first clock, wherein n>1; a plurality of control lines for receiving from said memory adapter n SDRAM commands generated from said received SDRAM command; an address line for receiving from said memory adapter n column addresses generated from said received column address and said row address, said row address presented on said address line between two adjacent ones of said n column addresses; and a plurality of data lines for receiving from said memory adapter n data units generated from said received data unit, each of said n data units having one nth said expected bit size.