Patent ID: 8183613

Claim:
A memory device, comprising: an insulation layer on a substrate; an active pattern on the insulation layer, the active pattern including two protrusions and a recess between the protrusions, the active pattern including: a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively; and a base region at other portions of the active pattern, the base region serving as a floating body for storing data; a gate insulation layer on a surface of the active pattern; and a gate electrode on the gate insulation layer, the gate electrode surrounding a lower portion of the active pattern and partially filling the recess, wherein: the base region serves as a base of a single bipolar transistor, the first impurity region serves as an emitter of the single bipolar transistor, the second impurity region serves as a collector of the single bipolar transistor, and the gate electrode surrounding the lower portion of the active pattern and partially filling the recess serves as a gate electrode of the single bipolar transistor.