Patent ID: 7200197

Claim:
In a semiconductor integrated circuit including: a hard macro having a plurality of combinational circuits for performing predetermined logic processing and a plurality of flip flops for performing data transfer, the hard macro being registered as a circuit pattern beforehand; an input flip flop for taking input data in synchronization with a clock signal; an output flip flop for outputting output data in synchronization with the clock signal; a first data path for giving the input data taken in the input flip flop to the hard macro; and a second data path for giving data outputted from the hard macro to the output flip flop, the hard macro comprising: a first flip flop for holding data given from the first data path at timing delayed from the clock signal, a second flip flop for performing data transfer between the plurality of the combinational circuits in synchronization with the clock signal, and a third flip flop for holding data outputted to the second data path at timing advanced from the clock signal for output.