Patent ID: 8125022

Claim:
A semiconductor device formed on a substrate having a principal surface comprising: a semiconductor element area positioned at a central area of the substrate, the semiconductor element area including a first semiconductor region of a first conductive type, a second semiconductor region of the first conductive type disposed apart from the first semiconductor region, and a third semiconductor regions of a second conductive type disposed between the first semiconductor region and the second semiconductor region and exposed on the principal surface, the third semiconductor region having a first junction with the first semiconductor region at a first junction depth receding from the principal surface; a fourth semiconductor region of the second conductive type exposed on the principal surface of the substrate and away from the central area of the substrate, the fourth semiconductor region being electrically connected to the third semiconductor region; having a second junction with the first semiconductor region at a second junction depth common with the first junction depth, and having an impurity concentration common with the third semiconductor region; trenches within the fourth semiconductor region, the trenches having bottoms receding from the principal surface and shallower than the second junction depth; and wherein at least one of the trenches is substantially filled with insulant.