Patent ID: 7028237

Claim:
An internal bus testing device for a semiconductor integrated circuit in which an internal bus control circuit and a plurality of modules are linked by a plurality of internal buses, comprising: an area selector provided to cause the internal bus control circuit to select an address area corresponding to one of the plurality of internal buses; an area address setting unit setting the internal bus control circuit in an internal bus test mode in response to an internal bus test start signal, the area address setting unit storing a state setting signal and a predetermined address value indicating the address area; and a control unit supplying, at a start of an internal bus test, the address value from the area address setting unit to the area selector by transmitting the state setting signal from the area address setting unit to the area selector, wherein the internal bus testing device is provided to access one of the plurality of modules linked to one of the plurality of internal buses, with respect to all address areas assigned to the semiconductor integrated circuit when an arbitrary address area corresponding to one of the plurality of internal buses is selected from among the assigned address areas.