Patent ID: 8058690

Claim:
A system comprising: an SDRAM memory; and a processor coupled to the SDRAM memory, the processor including therein at least one SRAM memory cell comprising: first, second, third and fourth diffusions formed on a substrate, each diffusion having constant width, wherein the first and fourth diffusions have therein a pair of channels, each of which separates a source from a drain, and the second and third diffusions have therein a channel that separates a source from a drain, first and third gate electrodes formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a first pass-gate transistor and the third gate electrode overlaps one of the pair of channels on the fourth diffusion to form a second pass-gate transistor, a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a first pull-down transistor and overlaps the channel of the second diffusion to form a first pull-up transistor, and wherein the first pass-gate, pull-down and pull-up transistors are of at least two different constructions, and a fourth gate electrode formed on the substrate, wherein the fourth gate electrode overlaps one of the pair of channels of the fourth diffusion to form a second pull-down transistor and overlaps the channel of the third diffusion to form a second pull-up transistor, wherein the second pass-gate, pull-down and pull-up transistors include transistors of at least two different constructions.