Patent ID: 7634710

Claim:
A method of decoding signals to generate a received bit stream, comprising: receiving modulated signals; generating bits representing the modulated signals, and beliefs representing an associated reliability of each bit; a bit node computation block receiving the bits and associated beliefs, and generating a plurality of bit node messages; a plurality of M serially-connected pipeline stages receiving the bit node messages and after M decoding cycles, generating a plurality of check node messages once per decoding cycle, comprising; for each iteration cycle, each of the M serially-connected pipeline stages performing check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different than component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.