Patent ID: 8692588

Claim:
A multiplex driving circuit receiving a start signal, a first clock signal, a second clock signal, a gate high voltage, a low voltage signal and n slave signals, the multiplex driving circuit comprising m driving modules for generating m×n gate driving signals, wherein an x-th driving module of the m driving modules comprises: an x-th shift register receiving the first clock signal, the gate high voltage and the low voltage signal, wherein according to a (x−1)-th master signal from a (x−1)-th shift register and a (x+1)-th master signal from a (x+1)-th shift register, the x-th shift register generates an x-th high voltage signal, an x-th master signal and an x-th control signal; and n driving stages for respectively receiving the n slave signals and receiving the x-th high voltage signal, wherein in response to the highest voltage of the x-th high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals, wherein the highest voltage of the x-th high voltage signal is greater than the gate high voltage.