Patent ID: 7149876

Claim:
A massively parallel processing computer, comprising: a main memory; a processing array, said processing array comprising a plurality of processing elements each coupled to a corresponding portion of said main memory, each processing elements comprising: a processing circuit; and a communication circuit, coupled to said processing circuit, said communication circuit comprising: a first bus, said first bus being an N-bit wide bus coupled to said corresponding portion of said main memory, and for transferring data in parallel between said communication circuit and said corresponding portion of main memory, N being an integer greater than one; a plurality of second buses, each of said second buses being a 1-bit wide bus for serially transferring data between said communication circuit and another one of said plurality of processing elements; and a register, said register being a multi-bit register, said register coupled to said processing circuit, said first bus, and said plurality of second buses, and wherein said register buffers data transfers between said first bus and said plurality of second buses.