Patent ID: 8310293

Claim:
A circuit, comprising: a first signal generator adapted to generate a first PWM source signal; a logic circuit adapted to generate a first PWM control signal from the first PWM source signal; a first delay circuit adapted to delay a first edge of the first PWM control signal by a programmable first delay and produce a first delayed PWM control signal; a second delay circuit adapted to delay a second edge of the first PWM control signal by a programmable second delay and produce a second delayed PWM control signal; and a first set/reset circuit having a set input coupled to receive the first delayed PWM control signal and a reset input coupled to receive the second delayed PWM control signal, the first set/reset circuit further having an output generating a first PWM output control signal having a duty cycle controlled by the delayed first edge in the first delayed PWM control signal and the delayed second edge in the second delayed PWM control signal.