Patent ID: 6891216

Claim:
A test structure for use in DRAM comprising: a semiconductor substrate; a transistor formed on said semiconductor substrate, said transistor comprising a first region and a second region, both said first region and said second region being formed in said semiconductor substrate, said first region and said second region for use as source/drain regions of said transistor; a deep trench capacitor formed in said semiconductor substrate, said deep trench capacitor having a first width, said deep trench capacitor having a first side and a second side opposite to said first side, said transistor being on said first side of said deep trench capacitor; a shallow trench insulator (STI) formed in a top portion of said deep trench capacitor, said STI having a second width, wherein said second width is substantially shorter than said first width; a third region formed in said semiconductor substrate, said third region being on said second side of said deep trench capacitor; a first contact formed on said semiconductor substrate and contacting with said first region; and a second contact formed on said semiconductor substrate and contacting with said third region.