Patent ID: 8017987

Claim:
A semiconductor memory device comprising: a semiconductor substrate having: first device regions on which circuit elements having a double-layer gate structure is formed, and second device regions on which circuit elements having a single-layer gate structure is formed; first element isolation insulating films that divide the first device regions with one another; second element isolation insulating films that divide the second device regions with one another; a gate insulating film formed on the semiconductor substrate; a first circuit element including: a first gate electrode layer formed on the gate insulating film in the first device regions, a first inter-electrode insulating film formed on the first gate electrode layer and on the first element isolation insulating films, and a second gate electrode layer formed on the first inter-electrode insulating film; and a second circuit element including: a third gate electrode layer formed on the gate insulating film in the second device regions, a second inter-electrode insulating film formed on the third gate electrode layer, and a fourth gate electrode layer formed on the third gate electrode layer and on the second element isolation insulating films; wherein, in a direction perpendicular to a main surface of the semiconductor substrate, a thickness of the third gate electrode layer from the gate insulating film to the second inter-electrode insulating film is larger than a thickness of the first gate electrode layer from the gate insulating film to the first inter-electrode insulating film, and wherein the gate insulating film is formed completely on a single plane parallel to a surface of the semiconductor substrate between source/drain regions of the second circuit element.