Patent ID: 7783845

Claim:
A non-volatile memory system comprising: a non-volatile flash memory circuit including: a array of non-volatile memory cells formed of a plurality of erase blocks each having one or more sectors, each sector comprising a plurality of individually programmable non-volatile memory cells and including a portion for user data portion and a portion for header data; program circuitry connectable to the memory array to write the memory cells thereof; and erase circuitry connectable to the memory array to erase the erase blocks thereof; and a controller circuit connected to the non-volatile flash memory circuit, where the controller circuit including logic circuitry whereby the memory circuit is managed by organizing the erase blocks into composite logical groups formed of multiple erase blocks according to a control data structure maintained by the controller, and wherein, in response to an erase command specifying one or more sectors of the memory circuit for erase, the logic circuitry determines which of the specified sectors form complete logical groups according to the control data structure and which of the specified sectors do not form complete logical groups according to the control data structure, performs a physical erase operation on those of the specified sectors determined to form complete logical groups, and performs a write operation to logically mark as erased, without performing a physical erase operation on, those of the specified sectors determined not to form complete logical groups.