Patent ID: 6847538

Claim:
A memory IC, comprising: word lines; bit lines that traverse the word lines; a first memory cell and a second memory cell provided at intersections between the word lines and the bit lines, the first memory cell being composed of a first capacitor and an N-type MOS transistor, the second memory cell being composed of a second capacitor and a P-type MOS transistor, a gate of the N-type MOS transistor and a gate of the P-type MOS transistor being commonly connected to each identical one of the word lines, and either sources of the N-type MOS transistor and the P-type MOS transistor or drains of the N-type MOS transistor and the P-type MOS transistor being commonly connected to each identical one of the bit lines, electrodes on one side of the first and second capacitors being commonly connected to a plate electrode of the memory IC, and an electrode on the other side of the first capacitor being connected to the source or the drain, an electrode on the other side of second capacitor being connected to the source or the drain; and an operation circuit that writes and reads data at the plurality of the first memory cell and the second memory cell, the operation circuit being composed of a circuit structure that writes and reads data in and from either one or both of the first memory cell and the second memory cell.