Patent ID: 7030022

Claim:
A method of manufacturing a semiconductor device having a first region, in which a capacitance component is a dominant cause of a RC delay, and a second region, in which a resistance component is a dominant cause of a RC delay, comprising: performing a first etching process to an insulating layer formed on a semiconductor substrate, so that at least one first trench having a first depth and a second trench having the first depth are formed in the first region and the second region, respectively; performing a second etching process to the second trench, so that a third trench having a second depth deeper than the first depth is formed in the second region, wherein the insulating layer has a first thickness under the third trench and a second thickness under the at least one first trench, the first thickness of the insulating layer under the third trench being less than the second thickness of the insulating layer under the at least one first trench; filling the at least one first trench and the third trench with a metal layer; and removing portions of the metal layer, so that a first metal interconnection and a second metal interconnection are formed inside of the at least one first trench and the third trench, respectively.