Patent ID: 6873506

Claim:
An integrated circuit comprising: a. a lateral NPN transistor having an emitter, a base, and a collector, the NPN transistor operable to conduct current between the emitter and the collector upon a positive first avalanche voltage applied between the emitter and collector; b. an input element operable to receive a input voltage; c. a circuitry connected to the input element and to the NPN transistor; d. an NMOS transistor, having a source, a drain, and a gate, coupled to the lateral NPN transistor; e. the gate capacitively coupled to input element and resistively coupled to a ground to maintain a voltage corresponding to the input voltage; f. the NMOS operable to conduct a drain current upon an electrostatic-discharge voltage less positive than the first avalanche voltage applied to the input element, the electrostatic-discharge voltage being more positive than the ordinary operating voltage of the circuitry coupled to the input element; g. a lateral PNP transistor, having an emitter, a base, and a collector, connected to the input element and resistively coupled to the ground; and h. the lateral PNP transistor operable to conduct a collector current upon an electrostatic-discharge voltage less positive than the first avalanche voltage applied to the input element, the electrostatic-discharge voltage being more positive than the ordinary operating voltage of the circuitry coupled to the input element, the collector current setting a base voltage at the base of the lateral NPN transistor.