Patent ID: 8169050

Claim:
A structure comprising: a substrate including an integrated circuit comprised of a plurality of active devices; at least one first metallization level including a first dielectric layer and a plurality of first conductive features in the first dielectric layer; at least one second metallization level including a second dielectric layer and a plurality of second conductive features in the second dielectric layer, the at least one second metallization level disposed vertically between the at least one first metallization level and the substrate; an on-chip inductor included in the first conductive features of the at least one first metallization level; and an on-chip capacitor included in the second conductive features of the at least one second metallization level, the on-chip capacitor positioned laterally within the at least one second metallization level such that the on-chip capacitor is in a substantially vertical alignment with the on-chip inductor in the at least one first metallization level, the first dielectric layer is vertically between the first conductive features of the on-chip inductor and the second conductive features of the on-chip inductor, and the second dielectric layer is vertically between the second conductive features of the on-chip capacitor and the substrate.