Patent ID: 7913022

Claim:
A multi-port memory controller (MPMC) comprising: a plurality of ports for coupling devices to the MPMC, wherein the plurality of ports comprises a variable number of ports implemented using programmable interconnects; port interface modules (PIMs) connected to the ports, the port interface modules including a PIM circuit to translate signals received from one of the ports and provide them to components in the MPMC, wherein the PIM circuit is programmable to interface with one or more devices of one or more types at the plurality of ports; a physical interface coupled between a memory device and the PIMs, wherein the physical interface comprises a changeable physical interface implemented using programmable interconnects coupled to inputs of the memory device and enables data alignment by setting a delay of a delay element associated with an input of the physical interface to enable data coupled to a data path circuit of the MPMC to be correctly aligned; a plurality of transaction encoders, each transaction encoder coupled to a port of the plurality of ports and generating an address based upon a transaction type requested by the port; and a control memory to receive an address from a transaction encoder of the plurality of transaction encoders, the control memory storing data for accessing the memory device based upon a transaction type.