Patent ID: 7027335

Claim:
A semiconductor storage device comprising: a memory cell array including memory cells and bit lines for transfer of data in the memory cells; an amplifier circuit connected to the bit lines to amplify data in the memory cells; a first switching element connected between the bit lines and the amplifier circuit; a first reference voltage source which applies to a gate of the first switching element a voltage for controlling the first switching element; a second switching element and a third switching element connected between the gate of the first switching element and the first reference voltage source, said second switching element and said third switching element being connected in parallel to each other; a second reference voltage source which applies to a gates of the second and third switching elements a voltage for controlling the second and third switching elements; a first timing shift circuit connected between the gate of the third switching element and the gate of the second switching element to delay the operation of the third switching element from the operation of the second switching element; and a feedback circuit to return to the gate voltage at the gate of the first switching element back to the first timing shift circuit, wherein the first timing shift circuit connects the second reference voltage source to the gate of the third switching element when the gate voltage exceeds a given set voltage.