Patent ID: 7012001

Claim:
A method for manufacturing a semiconductor device for use in a memory cell, comprising the steps of: a) preparing an active matrix having at least one transistor, a plurality of conductive plugs electrically connected to the at least one transistor and an insulating layer laterally between adjacent conductive plugs; b) forming a conductive layer over each conductive plug to form a bottom electrode; c) forming a (Ta 2 O 5 ) x (TiO 2 ) y composite layer over the bottom electrodes, x and y representing a respective molar fraction; d) forming a dielectric layer over the (Ta 2 O 5 ) x (TiO 2 ) y composite layer; and e) patterning the dielectric layer and the (Ta 2 O 5 ) x (TiO 2 ) y composite layer into a preset configuration.