Patent ID: 7208791

Claim:
An integrated circuit device comprising: an integrated circuit substrate; a conductive lower electrode layer of a capacitor on the integrated circuit substrate; a dielectric layer on the lower electrode layer; a conductive upper electrode layer of the capacitor on the dielectric layer; a first intermetal dielectric layer on the upper electrode layer, the first intermetal dielectric layer including at least one via hole extending to the upper electrode layer; a first conductive interconnection layer on the at least one via hole of the first intermetal dielectric layer; a second intermetal dielectric layer on the first intermetal dielectric layer, the second intermetal dielectric layer including at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer; and a second conductive interconnection layer on the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.