Patent ID: 8723548

Claim:
A logic apparatus, comprising: a logic block having an input for receiving data and an output for producing data that has been stored in said logic block, said logic block including, a first inverter having an input and an output, said input being coupled to said input of said logic block, said output being coupled to said output of said logic block, and a digital logic component having an input and an output, said input of said digital logic component being coupled to said output of said first inverter, said output of said digital logic component being coupled to said input of said first inverter; a first inverter block, said first inverter block including one or more pairs of inverters, said one or more pairs of inverters being sequentially connected to form a loop, said loop of one or more pairs of inverters being coupled to one of said input and said output of said first inverter, wherein said first inverter block is coupled to said input of said first inverter; and a second inverter block that is coupled to said output of said first inverter, wherein said second inverter block includes one or more pairs of inverters, said one or more pairs of inverters being sequentially connected to form a loop.