Patent ID: 7898900

Claim:
A latency counter that counts a latency of an internal command in synchronism with a clock signal, the latency counter comprising: a counter circuit that updates a count value in synchronism with the clock signal; and a point-shift FIFO circuit that includes a plurality of latch circuits, that fetches the internal command to any one of the latch circuits based on a count value of the counter circuit, and that outputs the internal command fetched to any one of the latch circuits based on the count value of the counter circuit, wherein the point-shift FIFO circuit includes: a first wired-OR circuit that logically operates based on outputs of a plurality of latch circuits belonging to a first group among the latch circuits; a second wired-OR circuit that logically operates based on outputs of a plurality of latch circuits belonging to a second group among the latch circuits; a gate circuit that logically operates based on outputs of at least the first and second wired-OR circuits; and first and second reset circuits that reset the first and second wired-OR circuits, respectively, based on the count value of the counter circuit.