Patent ID: 8344471

Claim:
An integrated circuit, comprising: a substrate having a bonding pad region and a non-bonding pad region; a first via formed over the substrate in the bonding pad region, wherein the first via is disposed between, and electrically coupled to, a first conductive component and a second conductive component, the first via having a first dimension in a top view toward the substrate; and a plurality of second vias formed over the substrate in the non-bonding pad region, wherein at least a subset of the second vias are disposed between, and electrically coupled to, a third conductive component and a fourth conductive component, the plurality of second vias each having a second dimension in the top view and the second dimension being substantially less than the first dimension, wherein the first conductive component and the third conductive component are disposed in a first metal layer, and wherein the second conductive component and the fourth conductive component are disposed in a second metal layer that is different from the first metal layer.