Patent ID: 8773160

Claim:
An integrated circuit having a monitor circuit for monitoring timing in a critical path in the integrated circuit, the critical path having a target timing margin, the monitor circuit comprising: a first flip-flop having an input and an output; a second flip-flop having an input and an output, wherein the inputs of the first and second flip-flops are connected together to form a signal input node capable of receiving an input signal; a delay circuit adapted to apply a delay value to a signal outputted from the first flip-flop; and a logic circuit having an output and at least a first input and a second input, the first input being connected to the delay circuit, and the second input being connected to the output of the second flip-flop, wherein: the output of the logic circuit indicates whether the target timing margin is satisfied or not satisfied, and the delay circuit comprises: a gross-delay element adapted to provide a gross delay value; and a fine-delay detector circuit adapted to generate, based on the gross delay value, an output signal indicating the extent to which the target timing margin is satisfied.