Patent ID: 8420520

Claim:
A method for fabricating a chip package, comprising: providing a first metal pad over a semiconductor substrate, a second metal pad over said semiconductor substrate and a passivation layer over said semiconductor substrate, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first metal pad, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second metal pad, and said second contact point is at a bottom of said second opening; forming a metal layer over said passivation layer and on said first and second contact points; forming a photoresist layer on said metal layer; forming a third opening in said photoresist layer and vertically over said first and second contact points and said passivation layer, wherein said third opening exposes a region, vertically over said passivation layer and said first and second contact points, of said metal layer, wherein said forming said third opening comprises exposing said photoresist layer using a 1X stepper with at least two of G-line, H-line and I-line; after said forming said third opening, electroplating a first gold layer over said region, said first and second contact points and said passivation layer with an electroplating solution comprising gold and sulfite ion; after said electroplating said first gold layer, removing said photoresist layer; and after said removing said photoresist layer, removing said metal layer not under said first gold layer.