Patent ID: 7667491

Claim:
A circuit for buffering a data signal to a low voltage logic device, the circuit comprising: a tri-state output buffer responsive to an enable signal and having at least one driver transistor having a first operating range, a first input configured to receive the data signal, a second input configured to receive the enable signal, a voltage input configured to receive a first supply potential, and an output configured to couple to the low voltage logic device, wherein the at least one driver transistor includes a first driver transistor coupled between the voltage input and the output, wherein the tri-state output buffer is adapted to provide a potential at the output that corresponds to the first supply potential when the first driver transistor is on; and a supply-input protection circuit connected to the voltage input of the tri-state buffer and configured to provide the first supply potential, the supply-input protection circuit comprising a first N-type transistor and at least one diode, wherein a source of the first N-type transistor is coupled to said voltage input, a drain of the first N-type transistor is configured to receive a second potential, and a gate of the first N-type transistor is coupled to a predetermined bias potential that is greater than the first supply potential, and the gate also is coupled to the source of the first N-type transistor via the at least one diode, wherein the at least one diode includes a cathode coupled to the gate and an anode coupled to the source, said first N-type transistor configured to supply the first supply potential to said output buffer when said gate receives the predetermined bias potential, wherein the first supply potential is based on the second potential, and the predetermined bias potential is greater than the second potential, and wherein said first N-type transistor has a second operating range that is greater than the first operating range of the at least one driver transistor, and wherein the first N-type transistor is configured to protect the at least one driver transistor of the output buffer at said voltage input when said second potential increases to a saturation region of the first N-type transistor, and wherein when the second potential increases to the saturation region of the first N-type transistor, the first N-type transistor limits current flowing from the drain to the source, thus providing the first supply potential at a level that is lower than a level that would damage the at least one driver transistor.