Patent ID: 8319526

Claim:
A latched comparator circuit comprising: an input amplification unit including a first and a second input terminal for receiving a first and a second input voltage, respectively, of the latched comparator circuit, a first and a second output terminal for outputting a first and a second output voltage, respectively, of the input amplification unit, and a reset terminal arranged to receive a reset signal for resetting the input amplification unit; a buffer unit operatively connected to the first and the second output terminal of the input amplification unit, the buffer unit including a first and a second output terminal for outputting a first and a second output voltage of the buffer unit, respectively; and a control unit operatively connected to the input amplification unit and the buffer unit, the control unit being adapted to generate the reset signal based on the first and the second output voltage of the buffer unit and a clock signal, and to generate an output signal of the latched comparator circuit based on the first and the second output voltage of the buffer unit; wherein the input amplification unit is adapted to balance the first and the second output voltage of the input amplification unit when the reset signal is in a first state, and to generate the first and the second output voltage of the input amplification unit by amplifying a voltage difference between the first and the second input voltage when the reset signal is in a second state; wherein the buffer unit includes a clock terminal for receiving the clock signal; and wherein the buffer unit is adapted to precharge the first and the second output terminal of the buffer unit to a first voltage level when the clock signal is in a first state, and to selectively provide a conductive path to a node having a second voltage level from one of the first and the second output terminals of the buffer unit at least based on the first and the second output voltage of the input amplification unit when the clock signal is in a second state.