Patent ID: 8817929

Claim:
A transmission circuit comprising: a plurality of lane blocks arranged in parallel to each other configured to convert parallel data supplied from a corresponding lane into serial data and output said serial data; and a clock enabler block including at least one clock enabler for outputting a drive clock phase-locked with a reference clock to said plurality of lane blocks after a plurality of cycles of said reference clock in response to an enable signal; each of said plurality of lane blocks comprising: a divider for dividing said drive clock supplied from said clock enabler block to generate a divide clock and a load signal; and a parallel-to-serial converter for converting said parallel data supplied from said corresponding lane into said serial data in synchronization with said divide clock and said load signal generated by said divider and said drive clock generated by said clock enabler block, wherein said plurality of lane blocks are grouped into a plurality of lane groups; and in said clock enabler block: a plurality of clock enablers are arranged in a tree structure of two stages; an output path of an output drive clock of a clock enabler in a preceding stage of said two stages to which said reference clock is supplied is branched to a number of branches equivalent to a number of groups of said plurality of lane groups; and clock enablers of said plurality of clock enablers of a succeeding stage of said two stages are arranged to a plurality of branches extending from said preceding stage and output drive clocks of said clock enablers of said succeeding stage are supplied to lane blocks of corresponding lane group, wherein, said clock enabler block, for synchronizing said lane blocks on said lane group: controls said output drive clock in accordance with said enable signal of a clock enabler of said plurality of clock enablers corresponding to said lane group subject to synchronization arranged on a branch path to be branched into said number of groups of said lane group; and controls another clock enabler of said plurality of clock enablers into a clock output state.