Patent ID: 7351653

Claim:
A method for carrying out a damascene process in semiconductor fabrication, comprising the sequential steps of: forming an intermetal dielectric film comprising at least a main layer and an upper layer each of a different chemical composition, on a semiconductor substrate; patterning the intermetal dielectric film to form an intermetal dielectric pattern having at least an opening that penetrates the intermetal dielectric pattern; forming a conductive film of a conductive material on the intermetal dielectric pattern so as to fill the opening with the conductive material; etching the conductive film using a chemical/mechanical polishing operation to form a conductive pattern that exposes the top face of the intermetal dielectric pattern and fills the opening; and selectively removing said upper layer of the intermetal dielectric pattern using etching selectivity resulting from the difference in chemical composition of the main layer and the upper layer to remove scratches caused by the chemical/mechanical polishing operation.