Patent ID: 7852691

Claim:
A semiconductor memory device, comprising: a plurality of submacros mutually connected via global data lines, each of said submacros including: a first and a second memory block, and a memory block control circuit arranged between said first and second memory blocks, said first block control circuit including: a DQ buffer block connected to said first memory block via first complementary data lines and connected to said second memory block via second complementary data lines; a dynamic data shift redundancy circuit block connected to said DQ buffer block via local data lines and operative to relieve said first and second memory blocks; an address latch operative to latch an address received from external; and a DQ buffer control circuit operative to receive said address latched at said address latch and generate a DQ buffer control signal to control said DQ buffer block, wherein said dynamic data shift redundancy circuit block selects a relief area at the time of read operation utilizing a DQ buffer control signal generated at said DQ buffer control circuit.