Patent ID: 7269090

Claim:
A memory system comprising: an array of addressable storage elements arranged in a plurality of rows and a plurality of columns, wherein the array of addressable storage elements comprises a plurality of nonvolatile memory cells; and decoding circuitry coupled to the array of addressable storage elements, the decoding circuitry, responsive to decoding a first element address, to access a first storage element of a first row of the plurality of rows, mid the decoding circuitry, responsive to decoding a second element address consecutive to the first element address, to access a second storage element of a second row of the plurality of rows, the second row of the plurality of rows different from the first row of the plurality of rows; wherein the first address comprises a group of bits; wherein the second address comprises a group of bits; wherein the decoding circuitry includes a row decoder and a column decoder; wherein the row decoder is operable responsive to a first portion of the group of bits of the first address and the second address; wherein the column decoder is operable responsive to a second portion of the group of bits of the first address and the second address, wherein a bit of the second portion is more significant than a bit of the first portion.