Patent ID: 7752377

Claim:
A structure compatible with I2C bus and system management (SM) bus, comprising: a first device, having an I2C bus interface; a second device, having a SM bus interface; and a timing buffering apparatus, connected between the I2C bus interface and the SM bus interface, the timing buffering apparatus comprising: a first-direction transmission circuit, wherein when the first device drives a data line of the I2C bus interface to transform from the first state to the second state, the first-direction transmission circuit allows a data line of the SM bus interface to stay in the first state for a holding time and then transform from the first state to the second state, or the first-direction transmission circuit allows the data line of the SM bus interface to transform from the first state to the second state and stay in the second state for the holding time, the first-direction transmission circuit comprising: a first comparison sub-circuit, connected to the I2C bus interface, the first comparison sub-circuit outputting a first control signal according to the voltage level of the I2C bus interface; a first switch, disposed on a data transmission path from the first device to the second device, wherein the first switch receives the first control signal from the first comparison sub-circuit and is turned on/off according to the first control signal; a second switch, disposed on the data transmission path from the first device to the second device, wherein the second switch receives the first control signal from the first comparison sub-circuit and is turned on/off according to the first control signal; and a delay sub-circuit, connected between the first switch and the second switch, wherein when the data transmission path from the first device to the second device is turned on, the delay sub-circuit provides the holding time to allow the data line of the SM bus interface to stay in the first state or the second state for the holding time; a second-direction transmission circuit, for transmitting data from the second device to the first device, the second-direction transmission circuit comprising: a second comparison sub-circuit, connected to the SM bus interface, the second comparison sub-circuit outputting a second control signal according to the voltage level of the SM bus interface; and a third switch, disposed on a data transmission path from the second device to the first device, wherein the third switch receives the second control signal from the second comparison sub-circuit and is turned on/off according to the second control signal.