Patent ID: 8343827

Claim:
A method of manufacturing a semiconductor device having an n-channel field effect transistor formed in a major surface of a semiconductor substrate, the method comprising the steps of: (a) sequentially forming a gate insulating film and a gate electrode in a major surface of the semiconductor substrate having a p-type well formed therein; (b) forming a first n-type impurity diffusion layer by ion-implanting first n-type impurities into the semiconductor substrate on both sides of the gate electrode; (c) forming a sidewall comprising an insulating film in a sidewall of the gate electrode; (d) forming a second n-type impurity diffusion layer by ion-implanting second n-type impurities into the semiconductor substrate on both sides of the sidewall; (e) forming a source/drain comprising the first n-type impurity diffusion layer and the second n-type impurity diffusion layer by applying a first heat treatment to the semiconductor substrate and thereby activating the first n-type impurities and the second n-type impurities; (f), after the step (e), forming an amorphous layer by ion-implanting cluster carbon into the second n-type impurities diffusion layer, and (g), forming a Si:C layer by applying a second heat treatment to the semiconductor substrate and thereby recrystallizing the amorphous layer, wherein a position of a second junction between the second n-type impurity diffusion layer and the p-type well in a thickness direction of the semiconductor substrate is deeper than a position of a first junction between the first n-type impurity diffusion layer and the p-type well in the thickness direction of the semiconductor substrate, and wherein a position, at which a concentration of the carbon contained in the Si:C layer becomes the maximum, is deeper than the position of the first junction between the first n-type impurity diffusion layer and the p-type well in the thickness direction of the semiconductor substrate and is shallower than the position of the second junction between the second n-type impurity diffusion layer and the p-type well in the thickness direction of the semiconductor substrate.