Patent ID: 8823429

Claim:
A device, comprising: a data input configured to receive input data signal from an electronic device; a voltage controlled oscillator configured to generate first, second, third, and fourth clock signals mutually out of phase with each other; a phase detector circuit configured to receive the input data signal and the first, second, third, and fourth clock signals and to generate a first phase difference signal and a second phase difference signal based at least in part on the data signals and one or more of the clock signals, the second phase difference signal configured to transition to a high value if a transition in the input data signal is detected while the first phase difference signal is high; and a charge pump circuit coupled to the phase detector circuit, including: an OR gate configured to receive as input signals the first and the second phase difference signals and to pass a first current when the first and/or second phase difference signals are at the high value; and an output coupled to the voltage controlled oscillator, the output configured to provide an output signal to the voltage controlled oscillator based at least in part on the first current, the voltage controlled oscillator configured to adjust a frequency of the clock signals based on the output signal.