Patent ID: 8378421

Claim:
A thin film transistor substrate comprising: a substrate; an adhesive layer on the substrate; a semiconductor layer comprising a first doped region, a second doped region and a channel region on the adhesive layer; a first dielectric layer on the semiconductor layer; a gate electrode overlapping the channel region on the first dielectric layer; a second dielectric layer on the first dielectric layer and the gate electrode; a source electrode disposed on the second dielectric layer and electrically connected to the first doped region; and a drain electrode spaced apart from the source electrode and electrically connected to the second doped region, wherein: the channel region is disposed between the first doped region and the second doped region, and has a transmittance higher than those of the first doped region and the second doped region; the channel region has a thickness less than that of any one of the first doped region and the second doped region; and the first dielectric layer includes a first region disposed on the channel region and a second region disposed on the first and second doped regions, and a thickness of the first dielectric layer in the first region is greater than a thickness of the first dielectric layer in the second region.