Patent ID: 7005341

Claim:
A method of fabricating a dynamic random access memory cell, comprising the steps of: providing a substrate having a patterned mask layer thereon and a deep trench therein, wherein the patterned mask layer exposes the deep trench, and the substrate has a lower electrode formed at a bottom portion of the deep trench, wherein an interior surface of the deep trench has a capacitor dielectric layer thereon; filling with a first conductive layer at the bottom portion of the deep trench; removing the capacitor dielectric layer uncovered by the first conductive layer; forming a collar oxide layer on a sidewall of the deep trench uncovered by the first conductive layer; filling with a second conductive layer over the first conductive layer in the deep trench; forming a trench in the substrate on one side of the second conductive layer, wherein the trench exposes a portion of the substrate and the second conductive layer; forming a semiconductor strip in the trench to expose a portion of the substrate at the bottom portion of the trench, wherein one end of the semiconductor strip is positioned next to the second conductive layer while the other end of the semiconductor strip is positioned next to the substrate; forming a gate dielectric layer over the substrate to cover an exposed semiconductor strip and the substrate; and forming a gate over the gate dielectric layer, wherein the gate crosses over the semiconductor strip, and the gate-covered portion of the semiconductor strip serves as a channel region.