Patent ID: 8660223

Claim:
A communication device comprising: a phase locked loop (PLL) circuit that comprises: (a) a phase comparing unit that receives a reference clock signal and a feedback clock signal and generates a control voltage in accordance with a phase difference between the reference clock signal and the feedback clock signal; (b) a voltage controlled oscillator that oscillates at an oscillation frequency in accordance with the control voltage and generates a spectrum-modulated output clock signal; (c) a phase interpolator that receives the spectrum-modulated output clock signal and generates a phase-shifted signal obtained by shifting phase of the spectrum-modulated output clock signal; (d) a feedback path that supplies the phase-shifted signal or a signal obtained by dividing frequency of the phase-shifted signal to the phase comparing unit as the feedback clock signal; and (e) a controlling unit that periodically changes a modulation degree of the spectrum-modulated output clock signal by controlling the phase interpolator to change a phase shift amount at timings predetermined in accordance with a spread spectrum clock (SSC) modulation profile; a signal receiving unit that operates upon receiving supply of the spectrum-modulated output clock signal; and a signal transmitting unit that is capable of receiving both of the spectrum-modulated output clock signal and the phase-shifted signal or a shaped clock signal which is obtained by shaping a waveform of the phase-shifted signal, the signal transmitting unit being operated by the spectrum-modulated output clock signal, or the phase-shifted signal or the shaped clock signal that is selectively supplied.