Patent ID: 7495978

Claim:
A semiconductor device comprising: a first bit line; a second bit line; a first redundant bit line; a second redundant bit line; a plurality of first word lines each crossing said first bit line; a plurality of second word lines each crossing said second bit line, each of the second word lines being provided separately from each of the first word lines; a plurality of first memory cells each disposed at a different one of intersections of said first bit line and said first word lines; a plurality of second memory cells each disposed at a different one of intersections of said second bit line and said second word lines; a plurality of first redundant memory cells connected to said first redundant bit line, a plurality of second redundant memory cells connected to said second redundant bit lines; a first amplifier circuit connected to said first bit line and said second bit line to amplify a difference in potential between said first bit line and said second bit line; and a first redundant amplifier circuit connected to said first redundant bit line and said second redundant bit line to amplify a difference in potential between said first redundant bit line and said second redundant bit line, wherein said semiconductor device is configured such that said first bit line is replaced with said first redundant bit line but said second bit line is not replaced with said second redundant bit line.