Patent ID: 8712057

Claim:
An integrated circuit comprising: a first cryptographic block to iteratively descramble received information using one of an internal key and a preprogrammed key to form one of a descrambled key and a descrambled data; a key feedback path for storing of the descrambled key as the internal key and to provide the one of the internal key and the preprogrammed key to a key input of the first cryptographic block; a second cryptographic block to descramble received scrambled digital content using a final descrambling key from the first cryptographic block to form descrambled digital content, wherein the first cryptographic block is separate and different from the second cryptographic block; a data feedback path for storing of the descrambled data within a data register as internal data, wherein the data feedback path for descrambled data is separate and different from the key feedback path for the descrambled key, wherein the key feedback path and the data feedback path to operate according to an off-chip insecure CPU; and data selection logic coupled to the data register and an external information input, the data selection logic to provide one of the internal data from the data register and the received information from the external information input to a data input of the first cryptographic block.