Patent ID: 8537609

Claim:
A memory device, comprising: a memory array, including a first division having a plurality of first cells and a second division having a plurality of second cells, wherein each of the first cells and the second cells includes a first electrode, a second electrode, and a memory material between the first electrode and the second electrode; a first circuit electrically connected to the first division, and causing the first division to be operated in a bipolar operation mode; and a second circuit electrically connected to the second division, and causing the second division to be operated in a unipolar operation mode, wherein each of the first memory cells is operated in the bipolar operation mode, each of the first memory cells is in a high resistance state when an insulating layer is separated from the memory material, and each of the first memory cells is in a low resistance state when at least a part of the insulating layer is recombined with the memory material.