Patent ID: 7257700

Claim:
A method for avoiding register read-after-write (RAW) hazards upon returning from a speculative-execution mode in a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions, the method comprising: issuing instructions for execution in program order during execution of a program in a normal-execution mode; upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, generating a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commencing execution in the speculative-execution mode; and upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, using the checkpoint to resume execution in the normal-execution mode from the launch-point instruction; wherein resuming execution in the normal-execution mode involves ensuring that entries that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for when resuming execution from the launch-point instruction; and wherein generating the checkpoint involves saving a precise architectural state of the processor to facilitate subsequent recovery from exceptions that arise during the speculative-execution mode.