Patent ID: 7906987

Claim:
A semiconductor integrated circuit, comprising: a plurality of reconfigurable cores arranged separately from one another, said plurality of reconfigurable cores each operating synchronously with respect to a clock signal and having a logic reconfiguration function; and a first group of registers formed between a first reconfigurable core and a second reconfigurable core included in said plurality of reconfigurable cores, said first group of registers being configured to temporarily hold an output from said first reconfigurable core and transfer the output from said first reconfigurable core to said second reconfigurable core, wherein said plurality of reconfigurable cores each includes: a plurality of logic elements arranged in a matrix and each configured to implement a predetermined logic; and programmable wiring interconnecting said plurality of logic elements, wherein said first group of registers include a first register and a second register that each receive a same clock signal as a clock signal provided for said second reconfigurable core, said second reconfigurable core receiving data held in said second register.