Patent ID: 7170317

Claim:
A circuit for generating a sum bit representing the sum of three binary input signals; the circuit comprising: first logic arranged to generate a first intermediate signal as the logical XOR of the first and second binary input signals and a second intermediate signal as the inverse of the logical XOR of the first and second binary input signals; and second logic arranged to receive said first and second intermediate signals generated by said first logic, and to generate an output signal as the logical XOR of the first intermediate signal and the third binary input signal, said second logic comprising at least two pass gates, wherein: a first gate terminal of a first of said pass gates is arranged to receive the third binary input signal, a second gate terminal of said first pass gate is arranged to receive the inverse of the third binary input signal, a first gate terminal of a second of said pass gates is arranged to receive the inverse of the third binary input signal, and a second gate terminal of said second pass gate is arranged to receive the third binary input signal; input terminals of the first and second pass gates are connected to receive the first intermediate signal and the second intermediate signal respectively; output terminals of said pass gates are used to generate said output signal, wherein said first logic includes a first pair of pass gates for use in the generation of said first intermediate signal and a second pair of pass gates for use in the generation of said second intermediate signal; and each said pass gate includes a gate terminal and an inverse gate terminal.