Patent ID: 7471556

Claim:
A locally-latched phase-change memory (PCM) comprising: a data input that receives a data word in response to a write request and a write address; a data output that outputs a data word in response to a read request and a read address; a host write buffer, coupled to the data input, for storing the data word; a plurality of PCM cells each having a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase; a plurality of banks, each bank comprising: an array of the plurality of PCM cells; an X decoder, receiving an X portion of the write address or receiving an X portion of the read address, for selecting a row of the PCM cells selected by an activated word line selected from a plurality of word lines in the array; a Y decoder, receiving a Y portion of the write address or receiving a Y portion of the read address, for selecting a column of the PCM cells in the array as selected PCM cells; local sense amplifiers for reading read data stored in the selected PCM cells in response to the read address; local write drivers for driving a set pulse for a set period of time to the selected PCM cells that are being written to the first logical state, and for driving a reset pulse for a reset period of time to the selected PCM cells that are being written to the second logical state; local bank write latches, storing write data that includes set data bits indicating the first logical state and reset data bits indicating the second logical state, the local bank write latches coupled to control the local write drivers to drive the set pulse and the reset pulse to the selected PCM cells; and shared data lines, driven by the host write buffer, for transferring write data from the data word in the host write buffer to the local bank write latches for a selected bank in the plurality of banks, wherein the selected bank is selected by a bank portion of the write address; an array data mux that disconnects the shared data lines from the local bank write latches of a prior selected bank before the set and reset pulses are applied to the selected PCM cells, allowing data transfer to the selected bank while the set and reset pulses are being applied to the prior selected bank, whereby set and reset pulses are driven to the selected PCM cells from data stored in the local bank write latches, freeing the shared data lines when the set and reset pulses are applied.