Patent ID: 8594256

Claim:
A multi-chip antenna diversity architecture that optimizes power consumption based on channel conditions comprising: a first receiver chip that receives a first input signal from a first antenna, said first receiver chip comprising: a first clock phase lock loop (PLL) that generates a first digital clock; a first crystal oscillator operatively connected to said first clock PLL; a first tuner that amplifies said first input signal; a first demodulator operatively connected to said first tuner, wherein said first demodulator demodulates said first input signal received from said first tuner; a first maximum ratio combiner (MRC) operatively connected to said first demodulator; a first power sequencer that controls said first receiver chip; and a first Diversity State Machine (DSM) operatively connected to said first power sequencer; a second receiver chip that receives a second input signal from a second antenna, said second receiver chip comprising: a second clock PLL that generates a second digital clock; a second crystal oscillator operatively connected to said second clock PLL; a second tuner that amplifies said second input signal; a second demodulator operatively connected to said second tuner, wherein said second demodulator demodulates said second input signal received from said second tuner; a second MRC operatively connected to said second demodulator; a second power sequencer; and a second DSM operatively connected to said second power sequencer, wherein said first receiver chip or said second receiver chip transitions a power state based on a value of at least one channel metric, wherein said second MRC and said second crystal oscillator are disabled upon said first receiver chip being powered ON, and wherein any of said first receiver chip and said second receiver chip is powered OFF when said value of said channel metric exceeds a predetermined threshold value.