Patent ID: 7195953

Claim:
A manufacturing method for a semiconductor package comprising the steps of: forming a lead frame by processing a thin metal plate, wherein the lead frame comprises a stage for mounting a semiconductor chip thereon, a plurality of groups of leads arranged in a periphery of the stage, and a plurality of lead interconnection members for interconnecting a plurality of leads in each group of the leads respectively; mounting the semiconductor chip on the stage of the lead frame via bonding, wherein the semiconductor chip is wired with the plurality of leads; forming a molded resin for integrally fixing the semiconductor chip, the stage, and the leads therein, the molded resin having side surfaces around a periphery thereof; plating prescribed surfaces of the leads that are exposed to an exterior of the molded resin; and cutting the plurality of leads at a plurality of cutting lines so that the plurality of leads are made electrically independent of each other, and so that the plurality of leads do not extend beyond the side surfaces of the molded resin, wherein a through hole is formed in each lead in a thickness direction of the lead frame so as to allow the plurality of cutting lines to pass therethrough, and wherein the through holes are formed at a selected timing within a prescribed time period counting from a timing of forming the lead frame to a timing of plating the leads.