Patent ID: 8498167

Claim:
A semiconductor memory device comprising: a command decoder for receiving an external command to generate a self-refresh control signal, wherein the memory device performs self-refresh operations in response to the self-refresh control signal; a plurality of memory banks, each memory bank having a plurality of memory cells arranged in columns and rows; a bank address generator for generating a target bank address to each of the memory banks to perform the self-refresh operation on the target bank; a self-refresh counter for specifying a target refresh row to all memory banks; and a self-refresh timing circuit comprising: a temperature sensor for generating a voltage in response to a sensed temperature; a reference voltage source for generating a constant voltage; a comparison circuit for comparing the voltage from the temperature sensor with the constant voltage to generate a comparison signal; an enable circuit for generating an enable signal to activate the comparison circuit; and an oscillation circuit for generating a self-refresh clock signal in response to the comparison signal and the enable signal, wherein the self-refresh clock signal controls the operating frequency of the bank address generator and the self-refresh counter; wherein the enable signal is generated when self-refresh operations for at least one refresh row are completed in all memory cell banks.