Patent ID: 8804429

Claim:
A non-volatile memory device comprising: a charge pump for providing a programming current; an array of non-volatile memory cells, with each memory cell programmed by the programming current; said array of non-volatile memory cells partitioned into a plurality of units, with each unit comprising a plurality of memory cells; an indicator memory cell associated with each unit of non-volatile memory cells; a counter circuit for counting the number of memory cells of each unit to be programmed, the counter circuit comprising a digital ‘0’ bit detector comprising a clock pulse generator, the ‘0’ bit detector configured to sequentially check the bits to be programmed for ‘0’ bits; and a programming circuit for programming the memory cells of each unit using said programming current, when an output of the counter circuit indicates a certain percentage or less of the memory cells of each unit is to be programmed, and for programming the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using said programming current, when the output of the counter circuit indicates more than said certain percentage of the memory cells of each unit is to be programmed.