Patent ID: 8570090

Claim:
An electronic component protection power supply clamp circuit connected to a positive terminal and a negative terminal of a power supply, the clamp circuit comprising: a feedback latching circuit including a first p-type metal-oxide-semiconductor (PMOS) transistor and a first n-type metal-oxide-semiconductor (NMOS) transistor; a clamp transistor; a capacitor having a first end that is connected to the negative power supply terminal, and a second end that is connected to a drain terminal of the first PMOS transistor and a drain terminal of the first NMOS transistor; a first resistor having a first end that is connected to the positive power supply terminal, and a second end that is connected to the second end of the capacitor; a plurality of inverters connected between the second end of the first resistor and a gate terminal of the clamp transistor; a second resistor having a first end that is connected to the negative power supply terminal, and a second end that is connected to a gate terminal of the first PMOS transistor and a gate terminal of the first NMOS transistor; and a third resistor having a first end that is connected to either the positive or negative power supply terminal, and a second end that is connected to the gate terminal of the clamp transistor.