Patent ID: 8302050

Claim:
A computerized method of characterizing a design under verification (DUV) by a set of computers on a computer farm, the method comprising: executing in a verification environment (VE) a set of verification tests on a DUV to stimulate the DUV to collect test results from the DUV; collecting a set of failure data for the test results; generating sets of common failures by clustering the failure data; generating a set of simplified tests by removing a portion of the set of verification tests executing the set of simplified test; generating a set of hints from the common failures, wherein the hints indicate a potential failure mode or a potential root cause failure of the DUV for the test results for the simplified set of tests; generating a set of debug data from the set of simplified tests, the sets of common failures, wherein the debug data including trace information collected from the set of simplified tests; and transferring the set of hints and the set of debug data to a user computer for storage, display, and use in an interactive debug session of the DUV.