Patent ID: 7989341

Claim:
A method of manufacturing integrated circuit devices comprising: providing a semiconductor substrate with a surface region, the surface region comprising one or more layers overlying the semiconductor substrate; forming a copper layer overlying the surface region; forming a dielectric layer overlying the copper layer; forming a photoresist layer overlying the dielectric layer; aligning a proximity mask to an aligning feature, the proximity mask comprising a first region and a second region, the first region of the proximity mask possessing a first light transmission rate and the second region of the proximity mask possessing a second light transmission rate lower than the first transmission rate; exposing the photoresist layer using the proximity mask, a first portion of the photoresist layer being exposed through the first region of the proximity mask and a second portion of the photoresist layer being exposed through the second region of the proximity mask; developing the photoresist layer, whereby the first portion of the photoresist layer is removed and a thickness of the second portion of the photoresist layer is removed; etching the photoresist layer and the dielectric layer to form a dual-damascene structure by using a single-step etch process, wherein a via opening and a trench opening are formed in the dielectric layer by using the single-step etch process, wherein the ratio of thickness of the photoresist layer and the dielectric layer is 1:1 and the ratio of the etch rate of the photoresist layer to the dielectric layer is 1:1; forming a diffusion barrier layer over the dielectric layer and the copper layer; forming a copper seed layer overlying the diffusion barrier layer; forming a second copper layer from the copper seed layer using an electrochemical plating (ECP) process; and planarizing the second copper layer by using a chemical-mechanical polishing (CMP) process.