Patent ID: 7960759

Claim:
A circuit for use in an integrated circuit, said circuit comprising: a first collinear diffusion region; a second collinear diffusion region spaced opposite and substantially parallel to said first collinear diffusion region; a sequence of N collinear gate layers disposed substantially parallel to each other and perpendicular to said first collinear diffusion region and said second collinear diffusion region and each overlapping one or both of said first collinear diffusion region and said second collinear diffusion region to form gate electrodes; wherein a first gate layer in said sequence overlaps said first collinear diffusion region to form a gate electrode therewith and does not overlap said second collinear diffusion region; a next (N−2) gate layers in said sequence overlap both said first collinear diffusion region and said second collinear diffusion region to form respective gate electrodes; and an Nth gate layer in said sequence overlaps said second collinear diffusion region to form a gate electrode therewith and does not overlap said first collinear diffusion region; and further comprising a bridging conductor electrically connecting said first gate layer and said Nth gate layer passing said (N−2) gate layers without electrically connecting to at least some of said (N−2) gate layers.