Patent ID: 8385128

Claim:
A semiconductor memory, comprising: at least one of nonvolatile memory cells including a real cell transistor including a first control gate and a first floating gate; a word line coupled to the first control gate; a bit line coupled to the real cell transistor and precharged before a read operation; a sense amplifier operating, in the read operation, in response to activation of a sense amplifier enable signal and determining logic held in each of the nonvolatile memory cells according to a voltage of the bit line, the voltage varying with a cell current flowing through the real cell transistor; and a timing generation unit including a replica cell transistor and a switch transistor coupled in series between a first node and a ground line, and activating the sense amplifier enable signal when the first node, which is coupled to the ground line via the replica cell transistor and the switch transistor at the time of the read operation, changes from a high level to a low level, wherein the replica cell transistor includes a second control gate receiving a constant voltage and a second floating gate coupled to the second control gate, and wherein the switch transistor is turned on upon receipt of an operation enable signal at a gate of the switch transistor, the operation enable signal being activated at the time of the read operation.