Patent ID: 7019400

Claim:
A semiconductor device having a multilayer interconnection structure, comprising: a chip semiconductor substrate; a plurality of interlayer insulating layers disposed on the chip semiconductor substrate; a circuit section disposed on the chip semiconductor substrate; a seal ring section comprising a seal ring structure; and a plurality of walls of the seal ring structure that extend through the interlayer insulating layers and are arranged along a peripheral portion of the chip semiconductor substrate such that the walls surround the circuit section, wherein the walls include upper sub-walls and lower sub-walls, the upper sub-walls extending through an interlayer insulating layer for an upper wiring layer, which is one of the interlayer insulating layers, and further extending into another interlayer insulating layer for a lower wiring layer adjacent to the upper wiring layer, and the lower sub-walls extend through the interlayer insulating layer for the lower wiring layer through which the upper sub-walls extending and connecting to the upper wiring layer such that lower portions of the upper wiring layers each extend into corresponding upper portions of the lower sub-walls.