Patent ID: 7644227

Claim:
A buffer with a downstream input, a downstream output, an upstream input, an upstream output, a staging loop with a data storage capacity of X bits, a staging marker loop with the same storage capacity as the staging loop, a primary storage loop that stores a logical list with an end and a begin and has a data storage capacity greater than the storage loop, a storage begin marker loop with a storage capacity equal to the storage capacity of the primary storage loop that stores the begin of the logical list, a storage end marker loop with a storage capacity equal to the storage capacity of the primary storage loop that stores the end of the logical list, a output marker loop with a storage capacity equal to the staging loop, a first set of state storage loops, and a second set of state storage loops comprising: a first state machine connected to the downstream input, the downstream output, the staging loop, the primary storage loop, the storage begin marker loop, the storage end marker loop, and the first set of state storage loops that initializes the logical list, manages the staging loop, manages the transfer of X bits of data from the downstream input to the staging loop, manages the transfer said data from the staging loop to the end of the logic list, and manages the end of the logical list and a second state machine connected to the upstream input, the upstream output, the primary storage loop, the storage begin marker loop, the output marker loop, and the second set of state storage loops that transfers X bits of data from the begin of the logical list to the upstream output and manages the begin of the logical list.