Patent ID: 7572691

Claim:
A method of fabricating a non-volatile memory, comprising the following steps: forming two openings on a substrate; forming a stacked gate structure on the substrate between the two openings, wherein the stacked gate structure comprises a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer; forming a liner on a bottom of each of the two openings and a portion of a sidewall of each of the two openings, wherein a top surface of the liner is lower than that of the substrate; forming a second conductive layer on the liner at the bottom of each of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner; and forming a third conductive layer on the second conductive layer and the liner, wherein a top surface of the third conductive layer is at least co-planar with that of the substrate and lower than that of the first dielectric layer.