Patent ID: 8486803

Claim:
A wafer level chip scale packaging method for encapsulating a bottom and side walls of a semiconductor chip comprising: preparing a plurality of semiconductor chips at a front side of a semiconductor wafer; grinding at a backside to reduce a thickness of the semiconductor wafer; attaching the backside of the semiconductor wafer onto a dicing film; cutting from the front side of the semiconductor wafer to separate the semiconductor chips, each semiconductor chip remaining its position on the dicing film with the relative position and space between adjacent semiconductor chips unchanged; flipping and attaching the semiconductor chips remaining on the dicing film on a top surface of a double-sided tape, removing the dicing film, and attaching a bottom surface of the double-sided tape on a supporting substrate; depositing a molding compound to cover the back side of the semiconductor chips and to fill in the spaces between the adjacent semiconductor chips; flipping the semiconductor chips with the molding compound, removing the supporting substrate and the double-sided tape from the front side of semiconductor chips; depositing and reflow solder balls on the front side of the semiconductor chips at positions corresponding to top electrodes of each semiconductor chip; and cutting through the molding compound in the space between adjacent chips to separate individual chip packages, the bottom and side walls of each semiconductor chip are covered with the molding compound for protection.