Patent ID: 7041540

Claim:
A method for fabricating a thin film transistor, comprising: forming a polysilicon layer over a substrate; forming a gate dielectric layer over said polysilicon layer; forming a patterned photoresist mask having a first portion and a second portion over said gate dielectric layer, wherein said second portion has a thickness smaller than that of said first portion; patterning said gate dielectric layer using an etching process with said patterned photoresist mask acting as an etching mask, said patterned gate dielectric layer having a third portion and a fourth portion, wherein said fourth portion is positioned at two sides of said third portion and has a thickness smaller than that of said third portion; performing an ion implanting process with said patterned photoresist mask and said patterned gate dielectric layer acting as a doping mask to form a source region and a drain region in said polysilicon layer under said fourth portion of said patterned gate dielectric layer and to form a lightly-doped-drain (LDD) region in said polysilicon layer under said third portion of said patterned gate dielectric layer, wherein a channel region is configured in said polysilicon layer under said first portion of said patterned photoresist mask, and said lightly-doped-drain (LDD) region is positioned between said channel region and said source region or between said channel region and said drain region; removing said patterned photoresist mask; and forming a gate layer over said gate dielectric layer and said channel region.