Patent ID: 7910928

Claim:
A TFT array substrate comprising: a gate line, a gate electrode and a common electrode formed on a substrate; a gate insulation layer formed on the gate line, the gate electrode and a common electrode; a data line formed substantially perpendicular to the gate line to define a sub-pixel, and source and drain electrodes formed above the gate electrode; a semiconductor layer formed below the data line and the source and drain electrodes, wherein the semiconductor layer is formed in substantially the same pattern as those of the data line and the source and drain electrodes; a pixel electrode directly connected with the drain electrode without a contact hole on the gate insulation layer; a gate pad electrode formed at the end of the gate line as one body; a data pad electrode formed at the end of the data line; a transparent conductive layer over the gate and data pad electrodes and contacting with the gate and data pad electrodes; a passivation layer over the substrate and having open areas over the pixel electrode, the common electrode and the transparent conductive layer; wherein the gate insulation layer has open areas on the gate and data pad electrodes and the common electrode.