Patent ID: 8140893

Claim:
A fault-tolerant system including a plurality of subsystems each similarly comprising a plurality of CPUs (Central Processing Units), memory, a northbridge, an IO bridge and software, with similar processes executed among said subsystems through a lockstep method, wherein each of said plurality of subsystems comprises: a control unit configured to relay communications between said northbridge and said IO bridge and configured to connect to other subsystems, an error detection data creation unit positioned at least either between said plurality of CPUs, between said CPU and said memory, or between said CPU and said northbridge, said error detection data creation unit creating a single error detection data from a packet of data each time the packet of data is exchanged between the pair between which said unit is positioned, and a signal transmission circuit configured to connect said error detection data creation unit and said control unit; wherein said control unit detects discrepancies in processes among said plurality of subsystems by comparing and detecting mismatches in error detection data created by said error detection data creation unit received via said signal transmission circuit and error detection data received from said other subsystems.