Patent ID: 8289086

Claim:
A digital fractional phase-locked loop (PLL) comprising: a digital-in digital-out voltage controlled oscillator (DDVCO) for generating a PLL output and a feedback signal, the feedback signal including an integer output and a fraction output; a phase/frequency detector for determining phase differences between the feedback signal and a reference clock signal, and generating digital representations based on the integer output and the fraction output; a digital accumulator block for introducing an accumulated phase offset to the digital representations using a fractional component of a division ratio; and a digital loop filter for integrating outputs of the digital accumulator block and providing a resulting voltage to the DDVCO, wherein the DDVCO includes: an integer counter block for generating the integer output; a fractional counter block for generating the fraction output; and a timing de-skew block for ensuring alignment between the integer output and the fraction output, wherein the integer counter block and the timing de-skew block receive a PLL output generated by the fractional counter block, and the fractional counter block receives an output of the digital loop filter.