Patent ID: 8638636

Claim:
An apparatus, comprising: a memory integrated circuit including: a plurality of decoder circuits controlling a plurality of word lines, the plurality of decoder circuits processing word line addresses to identify, with a specificity of individual word lines, a subset of the plurality of word lines to perform an erase operation on the subset of the plurality of word lines, a decoder circuit of the plurality of decoder circuits including: an inverter having an input and an output controlling a word line to perform the erase operation, wherein a voltage range of the input extends between a first voltage reference and a second voltage reference; logic controlled by a word line address to determine a value of the input of the inverter during the erase operation wherein the logic includes: a plurality of electrical paths between an inverter determinative node and the first voltage reference, the plurality of electrical paths controlled by the word line address during the erase operation, the inverter determinative node determining the value of the input of the inverter, including: a first electrical path of the plurality of electrical paths turned on during the erase operation for the decoder circuits controlling word lines unselected for the erase operation; and a second electrical path of the plurality of electrical paths turned on during a program operation for the decoder circuits controlling word lines selected for the program operation and during a read operation for the decoder circuits controlling word lines selected for the read operation.