Patent ID: 8429470

Claim:
A method of testing a memory device, comprising: writing first data to an array of memory cells in the memory device corresponding to each of a plurality of memory addresses in a first write operation; reading first read data from the array of memory cells in the memory device for each of the plurality of memory addresses in a first read operation; determining, based on the first react data, whether the first data were correctly stored in the array of memory cells corresponding to each of the plurality of memory addresses; writing second data, in a second write operation, to the memory cells in the memory device corresponding to each of the plurality of memory addresses that were determined to have correctly stored the first data; masking the second write operations to an address of the plurality of memory addresses in response to determining the address incorrectly stored the first data; reading second read data from the array of memory cells in the memory device corresponding to each of the plurality of memory addresses that were accessed in the second write operation; determining, based on the second read data, whether the second data were correctly stored in memory cells for each of the plurality of memory addresses that were accessed in the second write operation; writing third data, in a third write operation, to the array of memory cells in the memory device for each of the plurality of memory addresses that were determined to have correctly stored the second data; and reading third read data from the array of memory cells in the memory device corresponding to each of the plurality of memory addresses to determine which of the plurality of addresses may include a defect.