Patent ID: 7391244

Claim:
A delay locked loop comprising a line of n delay cells (R 1 , R 2 , . . . , Rn) mounted in series from a delay cell of rank 1 to a delay cell of rank n, n being an integer greater than or equal to 2, each delay cell outputting a delayed signal, the line of delay cells having an input which is an input of the delay cell of rank 1 and which is connected to a first input of a phase/frequency detector, wherein said delay locked loop comprises control means including a sigma delta modulator ( 6 ) and having n inputs and an output, each input of the control means being connected to an output of a different delay cell of the line of delay cells and the output of the control means being connected to a second input of said phase/frequency detector, said control means selecting at each clock signal (H), on the basis of a control information (I), one of the delayed signals for applying to said second input of said phase/frequency detector, the number of delay cells seen by the phase/frequency detector being able to change at each tick of the clock signal (H).