Patent ID: 8261139

Claim:
A test apparatus for testing a memory under test, comprising: a writing section that writes data into at least one of addresses of the memory under test; a comparing section that compares, with an expected value signal, an output signal that is output from the memory under test in response to the data writing by the writing section, to output first fail information indicating whether the output signal matches the expected value signal; a fail memory that is to store the first fail information in association with each of the addresses of the memory under test; a mark memory that stores, in association with each of the addresses of the memory under test, validity information indicating whether second fail information is valid, the second fail information being fail information that is stored in the fail memory; a fail information updating section that, in association with an address associated with the first fail information output from the comparing section, (i) when validity information read from the mark memory indicates second fail information is invalid, stores the first fail information into the fail memory, and (ii) when validity information read from the mark memory indicates second fail information is valid, calculates a logical OR between second fail information read from the fail memory and first fail information output from the comparing section and stores the logical OR into the fail memory; and a register that stores clear instruction information to be stored into the mark memory, the clear instruction information indicating whether the second fail information is valid or invalid.