Patent ID: 7674685

Claim:
A method of fabricating a semiconductor device comprising, in order: forming a hard mask pattern exposing a cell region portion and a peripheral region portion of a semiconductor substrate; removing the exposed portions of the semiconductor substrate to form a cell region trench structure and a peripheral region trench structure; depositing a first insulating layer to a thickness T I1 whereby the trench structures are only partially filled; depositing a spin-on-glass (SOG) layer to a thickness T S sufficient to fill the cell region trench structure; treating the SOG layer to form a silicon oxide layer; removing upper portions of the silicon oxide layer and the first insulating layer to form a planarized surface having exposed surfaces of a silicon oxide layer pattern, a first insulating layer pattern and the hard mask pattern; removing a thickness T r of material from both the cell region trench structure and the peripheral region trench structure to form first recesses that have a bottom surface below a reference plane defined by the primary surface of the semiconductor substrate, wherein the bottom surface includes exposed surfaces of a modified silicon oxide pattern and a modified first insulating layer pattern, depositing a second insulating layer to a depth T I2 sufficient to fill the recessed regions; and removing an upper portion of the second insulating layer to form a planarized surface including a second insulating layer pattern and the hard mask pattern.