Patent ID: 7069362

Claim:
A processing system, comprising: a first ring and a second ring for interconnecting a plurality of nodes, each of said plurality of nodes comprising: at least one processor; memory; an input bus for said first ring; an input bus for said second ring; an output bus for said first ring; an output bus for said second ring; and a device for coupling said input bus of said first ring to said output bus of said second ring or said input bus of said second ring to said output bus of said first ring; wherein said coupling provides interprocessor communication among at least two of said plurality of nodes by allowing data of said first ring to reach said second ring; wherein data in said first ring flows in opposite directions with respect to said second ring; wherein each of said plurality of nodes further comprises hardware for broadcasting snoop addresses on said first ring and said second ring simultaneously; wherein each of said plurality of nodes further comprises hardware for forwarding an incoming snoop addresses on the same ring that said incoming snoop address was received on; wherein each of said plurality of nodes further comprises an address bus availability model to determine when a snoop addresses can be broadcast to one of said plurality of nodes that has not received said snoop address being broadcast.