Patent ID: 7217625

Claim:
A method of fabricating a semiconductor device, the method comprising: forming a gate pattern comprising a gate insulating layer and a gate electrode, on a semiconductor substrate; sequentially forming a buffer insulating layer, a first insulating layer, and a second insulating layer over the entire surface of the gate pattern and the entire surface of the semiconductor substrate; etching the second insulating layer to form a first spacer on the first insulating layer at both sidewalls of the gate pattern, wherein the buffer insulating layer and a least a thickness portion of the first insulating layer remain over the entire surface of the gate pattern and the semiconductor substrate after etching of the second insulating layer to form the first spacer; subsequently forming a deep source/drain region on the semiconductor substrate as aligned by the first spacer by implanting ions in the substrate through first insulating layer and the buffer insulating layer; removing the first spacer; etching the first insulating layer to remove some of the first insulating layer and leave a portion of the first insulating layer over the buffer insulating layer at both sidewalls of the gate pattern, thereby forming an offset spacer comprising said portion of the first insulating layer over the buffer insulating layer at both sidewalls of the gate pattern, wherein the buffer insulating layer located over the deep source/drain region is exposed during the etching of the first insulating layer; and subsequently forming a shallow source/drain region on the semiconductor substrate adjacent to the deep source/drain region as aligned by the offset spacer.