Patent ID: 7964923

Claim:
A semiconductor structure comprising: at least one field effect transistor located on a surface of a semiconductor substrate, said at least one field effect transistor including a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, said gate conductor stack having sidewalls that include at least one spacer; a second metal semiconductor alloy layer located within said semiconductor substrate at a footprint of said at least one spacer; a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to said first metal semiconductor alloy layer; a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to said second metal semiconductor alloy layer; a trench isolation region located within said semiconductor substrate, wherein an outer edge of said trench isolation region is in contact with an edge of said second metal semiconductor alloy layer; and a diffusion barrier located on a surface of said trench isolation region, and a middle-of-the-line (MOL) dielectric located on said diffusion barrier, wherein said MOL dielectric and said diffusion barrier have upper surfaces that are coplanar with upper surfaces of the first and second contacts and said at least one spacer.