Patent ID: 7687847

Claim:
A semiconductor device, comprising: a substrate having a memory cell region and a high-voltage circuit region; a first source/drain region disposed in the substrate within the memory cell region; a second source/drain region disposed in the substrate within the high-voltage circuit region; a first gate insulation layer disposed on the substrate within the memory cell region; a second gate insulation layer disposed on the substrate within the high-voltage circuit region, wherein the second gate insulation layer has a thickness greater than that of the first gate insulation layer; a floating gate disposed on the first insulation layer; a thickened silicon oxide layer covering a sidewall of the floating gate; a control gate disposed above the floating gate, wherein the control gate has a dimension greater than that of the floating gate; a barrier layer disposed between and in direct contact with the floating gate and the control gate, wherein a thickness of the barrier layer is less than a thickness of the thickened silicon oxide layer on the sidewall of the floating gate; and a gate disposed on the second gate insulation layer.