Patent ID: 7376924

Claim:
A method performed for determining placement of circuitry during integrated circuit design, the method comprising: accessing a net list identifying circuitry connections; assigning a plurality of individual net weights to nets in timing paths within said net list, said individual net weights being valid irrespective of physical design parameters; wherein: said individual net weights include a recoverability net weight proportional to an amount of non-optimizable delay in said timing paths, and said recoverability net weight is determined in response to a ratio of non-optimizable delay in said timing path to optimizable delay in said timing paths, and said individual net weights include a negative slack recoverability factor (NSRF) net weight proportional to a ratio of a negative slack path's total path delay adder due to interconnect to that negative slack path's zero wire load model positive slack margin, determining a composite net weight for nets in said timing paths, said composite net weight being in response to said plurality of individual net weights; concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps; and determining placement of said circuitry in response to said composite net weight.