Patent ID: 6972983

Claim:
An integrated circuit (IC) comprising: an array of ferroelectric memory cells interconnected by platelines, bitlines and wordlines, the wordlines coupled to gates of access transistors of the memory cells, bitlines coupled to first terminals of the access transistors and platelines coupled to first plates of capacitors of the memory cells; a sense circuit coupled to the bitlines; and a voltage source coupled to the sense circuit, the voltage source provides a negative voltage for the sense circuit to precharge the bitlines to a negative precharge voltage level for a memory access to access memory cells in the memory array for data retrieval or data storage, wherein at least the bitline associated with a selected memory cell to be accessed is precharged to the negative precharge voltage level to increase an effective magnitude of a plateline voltage on at least a plateline associated with the selected memory cell to increase a read signal from the selected memory cell.