Patent ID: 8526257

Claim:
A processor comprising: a memory comprising an array of memory cells; a control module configured to (i) generate a clock signal at a first rate, (ii) reduce the first rate of the clock signal to a second rate for a predetermined period, and (iii) adjust the clock signal from the second rate back to the first rate at an end of the predetermined period; a precharge circuit configured to (i) based on the clock signal at the first rate, precharge first bit lines connected to memory cells in a first row of the array of memory cells, (ii) based on the clock signal at the second rate, refrain from precharging the first bit lines during the predetermined period, and (iii) precharge the first bit lines subsequent to the end of the predetermined period; and an amplifier module configured to (i) based on the clock signal at the first rate, access first instructions stored in the first row of the array of memory cells, and (ii) based on the clock signal at the second rate, access second instructions stored in the first row of the array of memory cells or in a second row of the array of memory cells.