Patent ID: 7249297

Claim:
A test method for a semiconductor integrated circuit having a multi-cycle path, the semiconductor integrated circuit comprising: a scannable first memory element operating with edges of a clock signal and having a data input and a data output; at least one scannable second memory element for receiving, at a data input, data having propagated from the data output of the first memory element through a path in a logic circuit operable in multiple cycles longer than one cycle of a system clock rate, operating with edges of the clock signal, and outputting data from a data output; at least one scannable third memory element for receiving, at a data input, data having propagated from the data output of the first memory element through a single-cycle path in the logic circuit operable in one cycle of the system clock rate, operating with edges of the clock signal, and outputting data from a data output; a multi-cycle test enable generation section for generating a signal for distinguishing a multi-cycle test mode from a single-cycle test mode; the test method comprising a multi-cycle test step and a single-cycle test step, and the multi-cycle test step comprising: a scan step of connecting the data input of each of the first, second and third memory elements with the data output of another of the scannable memory elements to define a plurality of scan chains and shifting a test pattern serially into all the scannable memory elements in the scan chain at a test clock rate; a multi-cycle hold step of holding data in the first memory element prior to a capture operation or during the scan step for the duration of the number of cycles equal to or greater than the number of multiple cycles required from the data output of the first memory element to the data input of the second memory element; a multi-cycle capture step of connecting the data inputs of the first, second and third memory elements with the logic circuit and capturing a response of the logic circuit to the test pattern via the data inputs of the memory elements; and a shift-out step of connecting the data input of each of the first, second and third memory elements with the data output of another of the scannable memory elements to define the plurality of a scan chains and shifting out data from the memory element, and the single-cycle test step comprising: the scan step; a single-cycle capture step of connecting the data inputs of the first, second and third memory elements with the logic circuit, and holding data for the second memory element while capturing a response of the logic circuit to the test pattern via the data inputs for the memory elements other than the second memory element; and the shift-out step.