Patent ID: 7187739

Claim:
A timing recovery circuit comprising: a converter for sampling an input signal to generate an intermediate signal carrying samples of the input signal; an interpolator, responsive to a control value for inserting an interpolating sample into the intermediate signal to generate an output signal; a phase error detector for outputting a phase error of the output signal; an adjustment circuit for updating an over-sampling ratio in response to the phase error and a counting value which varies as a comparison result of the phase error and a reference value, the adjustment circuit including a first comparator for outputting a first value when the phase error is larger than the reference value, and for outputting a second value when the phase error is smaller than the reference value, a counter for outputting the counting value, wherein the counting value is increased when the first value is delivered from the first comparator, and the counting value is decreased when the second value is delivered from the first comparator, a second comparator for comparing the counting value with a first threshold and a second threshold, and a second calculation circuit for updating the over-sampling ratio by using the phase error when the counting value is between the first threshold and the second threshold, and for updating the over-sampling ratio by using a correction value when the counting value is not between the first threshold and the second threshold; and a first calculation circuit for deriving the control value from the updated over-sampling ratio and phase error, and for transferring the control value to the interpolator.