Patent ID: 7626402

Claim:
A semiconductor device comprising at least a first, a second, a third, and a fourth resistive elements, wherein each of said resistive elements comprises: a lower layer conductive pattern; an insulating layer formed on said lower layer conductive pattern; an upper layer conductive pattern formed on said insulating layer, having a smaller outline than said lower layer conductive pattern, and having a pair of openings to define a rectangular region therebetween; and a plurality of contacts respectively penetrating through said pair of openings from above said upper layer conductive pattern and reaching said lower layer conductive pattern, wherein a rectangular region of said first resistive elements has a first width and a first length, a rectangular region of said second resistive elements has said first width and a second length different from said first length, a rectangular element of said third resistive element has a second width different from said first width and said first length, and a rectangular region of said fourth resistive elements has said second width and said second length, each of said widths having a first side adjacent to one of said openings, and each of said length having a second side in contact with said first side, and wherein each of said resistive elements is an evaluation pattern for measuring the sheet resistance of a portion of said lower layer conductive pattern not covered by said upper layer conductive pattern.