Patent ID: 8347244

Claim:
A tool for designing analog and mixed signal circuits, the tool comprising: a unit enabling a user to identify one or more critical interconnect lines in a chip architecture; and one or more selectable, predefined transmission line topologies selectable as design elements for said critical interconnect lines, wherein the chip architecture is modeled using said critical interconnect lines before a physical layout of the chip architecture is determined; where said critical interconnect lines are defined by a set of geometry parameters for carrying analog and mixed signals, wherein each topology comprises: one or more signal wires; and a current return path, wherein a majority of electric field lines in an interconnect structure are contained within a boundary of said topology; a set of models enabling a user to perform circuit-level simulations of said chip architecture including said transmission line design elements, wherein each said model comprises a parametrized, equivalent RLC ladder network, wherein RLC refers to a resistor, an inductor, and a capacitor included in the circuit.