Patent ID: 6958508

Claim:
A ferroelectric memory, comprising: a connection structure, a first capacitor structure formed next to the connection structure, and a second capacitor structure formed next to the first capacitor structure; the first and second capacitor structure comprising: an interlayer dielectric film; a plug formed in the interlayer insulating film; a lower electrode formed on the plug; a capacitor insulating film formed on the lower electrode; and an upper electrode formed on the capacitor insulating film; the connection structure comprising: a plug formed in the interlayer dielectric film; a connection pad formed on the plug; an upper electrode formed in an opening formed at the capacitor insulating film that is formed on the connection pad, said upper electrode electrically connected to the connection pad in the opening, wherein the capacitor insulating film extends over and spans the space between the first and second capacitor structure, wherein the upper electrode of the first and second capacitor extends over and spans the space between the first and second capacitor structure, such that the capacitor insulating film and the upper electrode are formed over an area between the first and second capacitor structure as well as over the first and second capacitor structure, wherein the connection structure is electrically connected via the plug of the connection structure to a conductive layer, which serves as an impurity layer, of a transistor that is formed in a substrate, wherein another plug is formed so as to electrically connect another conductive layer of the transistor, and wherein a wiring is formed so as to electrically connect the capacitor upper electrode via the second plug, the transistor and the plug.