Patent ID: 8878239

Claim:
A semiconductor device comprising: a semiconductor substrate having a main surface; a dielectric portion formed to contact the main surface of said semiconductor substrate and having a first thickness and a second thickness larger than said first thickness; a semiconductor region of a first conductivity type formed to contact said dielectric portion and having a first impurity concentration; a first impurity region of a second conductivity type having a second impurity concentration and formed from a surface of said semiconductor region to a first depth in a first region of said semiconductor region, said first region being located directly above a portion which is a part of said dielectric portion and has said first thickness; a second impurity region of the second conductivity type having a third impurity concentration lower than said second impurity concentration, formed from the surface of said semiconductor region to a predetermined depth, and extending from said first impurity region toward a second region of said semiconductor region, said second region being located directly above a portion which is a part of said dielectric portion and has said second thickness; a third impurity region of the second conductivity type located at a distance from said second impurity region and formed in said second region from the surface of said semiconductor region to a predetermined depth; a gate electrode portion formed on a surface of a portion of said semiconductor region located between said second impurity region and said third impurity region with a gate insulating film interposed between said gate electrode portion and the surface of the portion of said semiconductor region; and a depletion layer block portion including a conductive region and formed at a predetermined position in said second region to extend from the surface of said semiconductor region and reach said dielectric portion.