Patent ID: 8006153

Claim:
A computer program product for multipurpose use of built-in self test (BIST) test latches in testing arrays of a processor, the computer program product having a tangible computer-readable medium with a computer program embodied thereon, the computer program comprising: computer code for configuring a first plurality of latches to operate as array built-in self test (ABIST) shadow latches to test the arrays; computer code for reconfiguring the first plurality of latches to operate as logic built-in self test (LBIST) observation latches to test the arrays; and wherein the computer code for configuring further comprises: computer code for serially loading a first data set into a plurality of data latches coupled in parallel to the first plurality of latches; wherein the plurality of data latches and the first plurality of latches are further coupled to form a scan chain of alternating latches from the plurality of data latches and the first plurality of latches; computer code for serially loading a second data set into the first plurality of latches operating as ABIST shadow latches; and computer code for performing back-to-back operations corresponding to the first and second data set, wherein the first plurality of latches shadows the plurality of data latches.