Patent ID: 7705763

Claim:
A successive approximation AD conversion apparatus that outputs digital output data corresponding to an analog input signal, comprising: a bit selecting section that sequentially selects conversion target bits of the output data, from an upper bit downward; a data control section that outputs comparison data determining a value of the conversion target bit, each time a conversion target bit is selected; a DA converting section that outputs an analog comparison signal corresponding to the comparison data; a timing generating section that outputs a comparison control signal ordering comparison initiation, after a prescribed delay time has passed since the DA converting section was supplied with the comparison data; a changing section that changes a timing of the comparison control signal according to a bit position of the conversion target bit, such that the timing of the comparison initiation indicated by the comparison control signal is later for higher conversion target bits; a comparing section that begins comparing the input signal to the comparison signal at the comparison initiation timing indicated by the comparison control signal having the timing changed by the changing section; a completion detecting section that outputs a completion signal causing the bit selecting section to select a next conversion target bit, after the comparing section has output the comparison result; and an output section that outputs output data in which a value of each bit is based on the comparison result by the comparing section.