Patent ID: 6948046

Claim:
An access controller that executes in a continuous access mode, the access to columns in the same row of a synchronous semiconductor memory device that has a storage region divided into a plurality of banks, the access controller comprising: a plurality of last column detection circuits wherein one last column detection circuit is provided corresponding to each of the banks, wherein each of the last column detection circuits detects the access to a last column address in the continuous access mode and generates and outputs a last column detection signal; a selecting circuit that selects and outputs one last column detection signal from among the last column detection signal output by each of the last column detection circuits based on an address signal; and an access control section that activates the row of the synchronous semiconductor memory device when the row is accessed in the continuous access mode, outputs a read command or a write command without deactivating the accessed row each time there is a request for access until the last column detection signal output by the selecting circuit is asserted, and deactivates the accessed row when the last column detection signal output by the selecting circuit is asserted.