Patent ID: 7388771

Claim:
A method for operating a resistance random access memory device having a first conductive member overlying a first programmable resistance random access memory member, the first programmable resistance random access memory member overlying a second conductive member, the second conductive member overlying a second programmable resistance random access memory member, a dielectric spacer on sides of the first conductive member and the first programmable resistance random access memory member and on a top surface of the second conductive member, the second programmable resistance random access memory member having an area that is a function of a thickness of the first dielectric spacer, comprising: connecting the first programmable resistance random access memory member in series with the second programmable resistance random access memory member, the first programmable resistance random access memory member having an area representing a first resistance value, the second programmable resistance random access memory member having an area representing a second resistance value R, the second programmable resistance random access member having the area that is larger than the area of the first programmable resistance random access memory member, the resistance random access memory device having a first logic state (“00” state), a second logic state (“01” state), a third logic state (“10” state) and a fourth logic state (“11” state); changing from one logic state to another logic state in the first and second programmable resistance random access memory members as a function of a material character n and a thickness f of the dielectric spacer.