Patent ID: 8830275

Claim:
A pipelined digital circuit that is configured to receive a binary first input signal having a first number of bits, n and to responsively generate a binary result signal having a second number of bits, m, where each of m and n is greater than 1, where the first input signal represents an input value equal to a predetermined forward function of a to be determined output value, the output value being represented by the to-be-generated result signal, whereby the output value therefore equals a corresponding reverse function of the input value, where said forward function has a monotonically changing range in which said input value appears; the pipelined digital circuit comprising: a plurality of m pipeline stages connected in succession one to the next in pipeline fashion, with each respective one of the pipeline stages having: (a) a digital input port for receiving a respective digital answer signal representing a respective guess value corresponding to the value of the to-be-generated result signal; (b) a comparator having first and second input ports and a comparison output port, where the first input port is operatively coupled to receive a respective copy of the first input signal or optionally the first input signal itself if the respective pipeline stage is a first in the succession of the m pipeline stages; (c) a lookup table (LUT) memory having a LUT input port operatively coupled to receive the respective digital answer signal from the respective digital input port and a LUT output port coupled to the second input port of the comparator, the LUT memory being configured to store lookup data representing output values of the predetermined forward function in said monotonically increasing or decreasing range; and (d) a partial result storing latch, operatively coupled to the comparison output port of the comparator and configured to temporarily store a partial result signal that will form part of the digital answer signal of the respective next pipeline stage if any in said succession of the m pipeline stages; and wherein the succession of pipeline stages are connected so that a progressively improving guess at the to-be-generated result signal can be provided by a pipelined downstream flow of the digital answer signal through the succession of the m pipeline stages.