Patent ID: 7863958

Claim:
A method of adjusting the duty cycle of a signal, the method comprising: generating, by a clock signal source circuit, a clock input signal that includes true and complement clock signals; receiving, by a duty cycle correction circuit, the clock input signal; deriving from the clock input signal, by the duty cycle correction circuit, first and second differential clock signals corresponding to the true and complement clock signals, respectively, the first and second differential clock signals exhibiting respective voltage offsets; and shifting, by the duty cycle correction circuit, the voltage offset of one of the first and second differential clock signals in response to a duty cycle exhibited by a clock output signal derived from the first and second differential clock signals, wherein the duty cycle correction circuit shifts the voltage offset of one of the first and second differential clock signals in response to a duty cycle error signal to provide a voltage offset shifted differential clock signal and a voltage offset un-shifted differential clock signal.