Patent ID: 7498253

Claim:
A method of forming a local interconnection wire, comprising: forming, on an insulation film, a first etching mask pattern that exposes a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with the insulation film, said size being equal to or shorter than a length between outer ends of the gate electrodes, and that independently exposes a portion of an active region provided from outer sides of the gate electrodes, and subsequently etching the insulation film exposed in the first etching mask pattern so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a first recess pattern of the gate electrodes and a second recess pattern at the active region; removing the first etching mask pattern; forming a second etching mask pattern for exposing a partial region in the first recess pattern and the second recess pattern, and then, performing an etching to form a first aperture for exposing a partial surface of the gate electrodes and a second aperture for exposing a partial surface of the active region; removing the second etching mask pattern; and filling the first and second recess patterns and the first and second apertures with conductive material to form a local interconnection layer.