Patent ID: 8255780

Claim:
A method of performing a high speed Viterbi and Trellis Coded Modulated (TCM) decoding for a Multi-Standard support in an application specific processor, said application specific processor comprising: a Load-Store, Logical and De-puncturing (LLD) slot that performs at least one of a Load-Store function, a Logical function, a De-puncturing function, and a Traceback Address generation function to generate decode bits; a Branch Metric Compute (BMU) slot that performs at least one of Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations; an Add-Compare-Select (ACS) slot that performs at least one of Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation; and specialized register file components, said specialized register file components comprising an optimized number of at least one of read ports and write ports that enables a faster processing of said Viterbi decoding functions, wherein said specialized register file components comprising at least one of a De-puncturing Register File, a General Purpose Register file, Primary and Secondary State Metric Register files, and Primary and Secondary Branch Metric Register files, wherein said method comprising: loading channel symbols in an input buffer based on instructions received as a fetch packet; de-puncturing said channel symbols based on a puncturing code rate, said puncturing code rate is at least one of a ½, ⅔, ¾, ⅚, and ⅞ rates convolution codes; storing de-punctured channel symbols in said De-puncturing Register File; and extracting bits from said De-puncturing Register File to said General Purpose Register File.