Patent ID: 6867131

Claim:
A method of adding parasitic capacitance to a SRAM cell, the method comprising the acts of: (a) partially etching a first dielectric layer from a first conductive node and a second conductive node to expose a portion of each of the first conductive node and the second conductive node; (b) forming a respective second dielectric layer on each side of each exposed portion of each of the first conductive node and the second conductive node; (c) forming a first conductive element between the respective dielectric layers between the first conductive node and the second conductive node; (d) forming a second conductive element adjacent the respective dielectric layer on the side of the first conductive node opposite the second conductive node; and (e) forming a third conductive element adjacent the respective dielectric layer on the side of the second conductive node opposite the first conductive node.