Patent ID: 8687433

Claim:
A memory control circuit that controls a read and write operation of a memory having a plurality of divided memory cell arrays that each comprises a plurality of memory cells, the memory control circuit comprising: a write circuit that connects to each of the memory cells in a first memory cell array of the plurality of the memory cell arrays via a first bit line and a second bit line, connects to each of memory cells in a second memory cell array of the plurality of the memory cell arrays via the first bit line and a third bit line and writes data to the memory cell in one of the first and second memory cell arrays; and a read circuit that connects to each of the memory cells in the first memory cell array via the second bit line and connects to each of the memory cells in the second memory cell arrays via the third bit line, and wherein the first bit line, which connects to the write circuit, is connected to the first and second memory cell arrays in common, wherein the memory control circuit further comprises: a common initialization circuit that initializes the first bit line; a second initialization circuit that initializes the second bit line; and a third initialization circuit that initializes the third bit line.