Patent ID: 7180960

Claim:
A phase error corrector comprising: an input ( 1 ) for receiving a complex PSK modulated signal (x(k)); a delay means ( 4 ) connected to said input for delaying said complex PSK modulated signal for generating a first delayed signal (x(k−1)); a multiplier ( 6 ) connected to said input ( 1 ) and said delay means ( 4 ) for multiplying said first delayed signal by said complex PSK modulated signal (x(k)) to generate a forward phase correction signal; a mixer ( 3 ) connected to said input for multiplying said complex PSK modulated signal (x(k)) by a phase correction signal which is generated based on said forward phase correction signal for generating a phase corrected signal; a first angle module ( 8 ) connected to said multiplier ( 6 ) for receiving said forward phase correction signal, said first angle module ( 8 ) calculating a forward phase offset which constitutes the phase of said complex forward phase correction signal; and a second angle module ( 12 ) and a subtractor ( 10 ), said second angle module being connected to an output of said mixer ( 3 ) for generating a backward phase offset constituting the phase of said phase corrected signal; said subtractor ( 10 ) being connected to said first angle module ( 8 ) and said second angle module ( 12 ) for subtracting said forward phase offset from said backward offset thereby calculating a difference phase offset; said phase correction signal being connected based on said difference phase offset.