Patent ID: 7732221

Claim:
A method of fabricating a memory device, comprising: providing a substrate; forming an access transistor on said substrate, said access transistor having a first active area and a second active area; providing a bit line in electrical contact with said first active area; providing an interconnect in electrical contact with said second active area; forming a first write only line; forming a first sense line associated with a first plurality of memory bits, said first sense line being formed over said access transistor and in electrical contact with said interconnect, wherein said interconnect is in electrical contact with said first plurality of memory bits via said first sense line; forming said first plurality of memory bits, each of said first plurality of memory bits being formed over, and in electrical contact with, said first sense line; forming a second sense line, said second sense line being formed over said first plurality of memory bits and in electrical contact with said interconnect; forming a second plurality of memory bits, each of said second plurality of memory bits being formed over, and in electrical contact with, said second sense line.