Patent ID: 7526707

Claim:
A pseudo-random bit interleaver that receives incoming bits and interleaves the incoming bits with parity bits, the interleaver comprising: a pseudo-random number (PRN) generation source for generating pseudo-random numbers (PRNs), each PRN comprising a sequence of bits; Transformation circuitry configured to transform each PRN generated by the PRN generation source into a plurality of different PRNs, each of said plurality of different PRNs comprising a respective transformed PRN sequence of bits, wherein each respective transformed PRN bit sequence identifies a respective parity equation to which a respective one of the incoming bits is assigned; selection circuitry configured to select respective ones of the transformed sequences of bits and to cause each respective incoming bit to be assigned to the respective parity equation identified by the respective selected transformed PRN bit sequence; and parity equation circuitry comprising logical operators for computing parity, the parity equation circuitry receiving the incoming bits and the selected transformed PRN bit sequence, wherein the parity equation circuitry is configured to route each incoming bit to the logical operator of the parity equation circuitry identified by the selected transformed PRN bit sequence, the logical operators operating on the bits routed thereto to compute parity bits, the parity equation circuitry outputting the incoming bits interleaved with parity bits.