Patent ID: 8665605

Claim:
A package structure, comprising: a substrate structure, comprising: a plurality of traces; a substrate core having a first surface and a second surface opposite to the first surface; a plurality of first metal tiles for increasing the strength of the substrate structure, wherein the first metal tiles and the traces are disposed on the first surface, the first metal tiles are in the shape of a polygon and arranged in a matrix, each one of the first metal tiles is separated from the other first metal tiles, the minimum gap between adjacent two of the first metal tiles is equal to 25 μm, and the minimum width of the first metal tiles is wider than the minimum gap between adjacent two of the first metal tiles; a plurality of second metal tiles for increasing the strength of the substrate structure, the second metal tiles are disposed on the second surface; a plurality of first electrically-functioning circuits disposed on the first surface; and a plurality of second electrically-functioning circuits disposed on the second surface; wherein, the traces, the first electrically-functioning circuits and the first metal tiles along the first surface add up to a first metal structure proportion, and the second electrically-functioning circuits and the second metal tiles along the second surface add up to a second metal structure proportion, and the difference between the first metal structure proportion and the second metal structure proportion is within 15%; a chip electrically connected to the substrate structure; and a sealant for sealing the chip, wherein the first metal tiles are electrical isolated, the minimum gap between one of the traces and one of the first metal tiles is equal to 25 μm, and one of the traces is adjacent to one of the first metal tiles.