Patent ID: 7563674

Claim:
A method of manufacturing a NAND flash memory device, the method comprising: sequentially laminating a tunnel oxide layer, a first polysilicon layer, a buffer oxide layer, and a nitride layer on a semiconductor substrate, and etching portions of the tunnel oxide layer, the first polysilicon layer, the buffer oxide layer, the nitride layer, and the semiconductor substrate, thus forming trenches, wherein a side of the nitride layer has a slope; forming an insulating layer within the trenches, and forming isolation layers within the trenches; sequentially stripping the exposed nitride layer and buffer oxide layer so that an upper side of each of the isolation layer has a negative profile due to the slope; forming a second polysilicon layer on the entire surface, thereby forming a seam within the second polysilicon layer due to the negative profile; performing a post annealing process, thereby making the seam into a void; performing a polishing process until the top surfaces of the isolation layers are exposed, and stripping a portion of the top surfaces of the isolation layers; and sequentially forming a dielectric layer and a third polysilicon layer on the entire surface.