Patent ID: 6889278

Claim:
A system configured to acknowledge and service an interrupt issued to a processor of an intermediate node, the system comprising: an external device coupled to a high latency path, the external device generating a pulsed interrupt signal for each type of interrupt supported by the processor; an interrupt multiplexing device accessible by the processor over a fast bus; a low latency path coupling the external device to the interrupt multiplexing device and adapted to transport each pulsed interrupt signal generated by the external device to the interrupt multiplexing device; and a status bit stored within the interrupt multiplexing device, the status bit adapted for assertion whenever the pulsed interrupt signal is detected at the interrupt multiplexing device; wherein, in response to the pulsed interrupt signal, the interrupt multiplexing device issues a level sensitive interrupt (LSI) signal to the processor over the fast bus, the LSI signal remaining asserted until the interrupt is acknowledged by the processor by clearing the status bit.