Patent ID: 6936504

Claim:
A method of fabricating a poly-silicon (poly-Si) thin film transistor (TFT) having back bias effects, the poly-Si TFT fabrication method comprising the steps of: (a) forming a conducting underlayer to which a back bias voltage is applied by using a conductive material on the entire surface of one side of a glass substrate; (b) forming a buffer layer by using an insulation material on the upper portion of the conducting underlayer; and (c) forming a poly-Si TFT on the upper portion of the buffer layer, the step of forming the poly-Si TFT includes the steps of: (i) depositing and patterning an amorphous silicon to form an active region: (ii) depositing a gate insulation film and a conducting film on the amorphous silicon and then etching the result to form a gate and a gate insulation film; (iii) depositing a nickel layer to the position where the source region and the drain region of the transistor on the amorphous silicon layer, and injecting impurities in order to define source and drain regions; (iv) thermally treating the result after injecting the impurities and changing the amorphous silicon portion where the nickel layer is deposited into a region crystallized by a metal induced crystallization (MIC) method, and changing the portion where the impurities are injected into a region crystallized by a metal induced lateral crystallization (MILC) method; and (d) forming gate, source and drain electrodes in the gate, source and drain regions, respectively, and connecting the conducting underlayer with a back bias electrode for applying a back bias voltage.