Patent ID: 8422299

Claim:
A non-volatile semiconductor memory device comprising: memory strings disposed in matrix state; and a control circuit for controlling a voltage applied to the memory strings, wherein each memory string comprises: a semiconductor layer comprising a pair of pillar portions, which extend in a vertical direction to a substrate and are disposed in a column direction, and a coupling portion formed to couple lower ends of the pair of pillar portions; control gates which orthogonally intersect one of the pair of pillar portions or the other of the pair of pillar portions, extend in a row direction, and are laminated above the substrate in a vertical direction to the substrate; a first selection gate which orthogonally intersects one of the pair of pillar portions, extends in the row direction, and is formed above the control gates; a second selection gate which orthogonally intersects the other of the pair of pillar portions, extends in the row direction, is formed above the control gates, and is on the same level as the first selection gate as well as integrated with the first selection gate; memory cell transistors which are formed in the respective intersecting portions of the one of the pair of pillar portions or the other of the pair of pillar portions and the control gates and to which current paths are connected in series; a first selection transistor which is formed to the intersecting portion of one of the pair of pillar portions and the first selection gate, one end of the first selection transistor is connected to one end of the memory cell transistors, and the other end of the first selection transistor is connected to a source line; and a second selection transistor which is formed to the intersecting portion of the other of the pair of pillar portions and the second selection gate, one end of the second selection transistor is connected to the other end of the memory cell transistors, and the other end of the second selection transistor is connected to a bit line, the control circuit makes the threshold value voltage of the first selection transistor higher than the threshold value voltage of the second selection transistor by performing write to the first selection transistor before write to a write target memory cell transistor in the memory cell transistors is performed.