Patent ID: 6970921

Claim:
A computer system, comprising: a host processor, and a network interface coupled to the host processor and to a network, the network interface comprising: a first port that receives data from the host processor; a second port that transmits data to the network; a memory that stores data packets received by the first port, the memory being coupled to the first port and to the second port; and a control circuit that manages the memory as a plurality of queues having respective priorities, including logic to place a packet received from the host into one of the plurality of queues according to a quality of service parameter associated with the packet, and logic to serve packets in the plurality of queues according to the respective priorities, wherein the plurality of queues includes a higher priority queue, and a lower priority queue, and including timeout logic coupled with the lower priority queue which is enabled if a packet is stored in the lower priority queue and preempts the higher priority queue in favor of the lower priority queue if the timeout timer expires.