Patent ID: 7954028

Claim:
A design structure embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: an integrated circuit chip having one or more memory macros and an automatic built-in self-test circuit; means for sending a test pattern to said one or more memory macros from said automatic built-in self-test circuit; means for sending an expected test pattern based on said test pattern to a fail register and writing said test pattern into a memory array of a memory macro of said one or more memory macros; means for, in a standard mode, reading out a resultant pattern from said memory array and sending said resultant pattern from said memory array to said fail register, said fail register comparing said resultant pattern with said expected pattern and generating a current fail record based on said comparison in said fail register if said resultant pattern does not match said expected pattern, said current fail record comprising a type of fail field, a wordline address field and a data field as wide as the number of columns in said memory array and indicating which bits of said test pattern failed; means for storing said current fail record in said fail register if another fail record in said fail register does not have a same wordline address as said current fail record and writing said type of fail field of said current fail record as a wordline fail; means for, if all bits in said data field of said current fail record match all bits of a data field of any other fail record in said fail register and the number of failing bits is less than a preset number of bits but at least equal to one, changing said type of fail field of said current fail record to a bitline fail; means for sending a fail record from said fail register to a repair register of said memory macro; means for generating and storing in said repair register a wordline repair record based on said fail record and sending a wordline repair command to said memory array if said fail type field of said fail record indicates wordline fail, or generating and storing a bitline repair record and sending a bitline repair command to said memory array if said fail type field indicates a bitline fail, said bitline repair record based on said data field of said fail record; means for replacing defective wordlines and bitlines of said memory array of said memory macro of said one or more memory macros with redundant wordlines and bitlines of said memory array based on said wordline and bitline repair commands; and wherein the design structure comprises a netlist.