Patent ID: 7570079

Claim:
A programmable interconnect circuit, the circuit including a plurality of input nodes, an output node, and a plurality of select lines, wherein one of the input nodes is coupled to the output node in response to signals placed on the select lines, the circuit comprising: a) a power supply line and a ground line; and b) a common internal node; and c) a plurality of selection nMOS pass transistors, with each of said selection nMOS pass transistors being connected between one of said input nodes and said common internal node, and each said selection nMOS pass transistor having the control electrode connected to one of said select lines; and d) a buffer device composed of an inverter, with said inverter having its input connected to said common internal node, its output connected to said output node, its power terminal connected to said power supply line, and its ground terminal connected to said ground line; and e) a pull-up device coupled between said power supply line and said common internal node, with said pull-up device being comprised of a pMOS transistor that has its control electrode connected to said output node; and f) a plurality of pull-down devices, with each of said pull-down devices being connected between said output node and said ground line, each of said pull-down devices being comprised of a series connection of an activation nMOS pass transistor and a commitment nMOS pass transistor; and g) a plurality of activation connections, such that there is an activation connection between the control electrode of each of said activation nMOS pass transistors and one of said select lines; and h) a plurality of commitment connections, such that there is a commitment connection between the control electrode of each of said commitment nMOS pass transistors and one of said input nodes, such that an individual instance of said input nodes and an individual instance of said selection lines which are both connected to one particular instance of said selection nMOS pass transistors are also both connected to one particular instance of said pull-down devices; whereby each of said pull-down devices augments one of said selection nMOS pass transistors to improve propagation delay and/or power consumption.