Patent ID: 7709965

Claim:
A metal line of a semiconductor device, comprising: a first interlayer dielectric layer pattern formed on a lower interconnection and having a via hole exposing the lower interconnection; a first barrier pattern selectively provided at a portion of the via hole; a second interlayer dielectric layer pattern on the first interlayer dielectric layer pattern and having a trench above the via hole; a second barrier pattern in the trench and via hole, the second barrier pattern covering the first barrier pattern; a seed pattern formed on the second barrier pattern; and a copper line formed on the seed pattern, wherein the first barrier pattern selectively covers a sidewall of the via hole and the exposed lower interconnection, wherein a bottom surface of the first barrier pattern covers the exposed lower interconnection, and a height of a side of the first barrier pattern formed on the sidewall of the via hole is lower than the thickness of the first interlayer dielectric layer.