Patent ID: 8170170

Claim:
A carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means, wherein said phase synchronizing means includes residual frequency error detecting means for detecting a residual frequency error after a frequency synchronizing process by said frequency synchronizing means and supplying said residual frequency error to said frequency synchronizing means, convergence state determining means for determining a convergence state of phase pull-in on a basis of said residual frequency error detected by said residual frequency error detecting means, and wherein said frequency synchronizing means includes: a frequency error detector configured to provide a frequency error after filter processing to an adder, and frequency pull-in control means for obtaining a result of determination of said convergence state determining means, and determining whether to perform frequency pull-in for said residual frequency error, the frequency pull-in control means having three levels based upon the convergence state such that: in a first level the frequency pull-in control means provides a 0 to the adder, in a second level the frequency pull-in control means provides the residual frequency error to the adder, and in a third level the frequency pull-in control means provides weighted value of the residual frequency error to the adder, and wherein said frequency synchronizing means performs frequency pull-in for said residual frequency error supplied from said residual frequency error detecting means after first timing.