Patent ID: 8614701

Claim:
A scan signal line driver circuit cascaded to another scan signal line driver circuit, said scan signal line driver circuit driving scan signal lines of a display screen according to an externally supplied start signal and an externally supplied clock signal, said scan signal line driver circuit comprising: a scan signal output circuit for performing alternately scanning, after a scan sequence setup period concludes, whereby either odd-numbered scan signal lines or even-numbered scan signal lines are sequentially driven first based on a scan sequence and whereby the remaining scan signal lines are sequentially driven thereafter; a clock pulse counter circuit for sensing, during a scan sequence setup period, a number of clock signals that occur during a variable length of the externally supplied start signal; a scan sequence setup circuit for setting whether the odd-numbered scan signal lines or even-numbered scan signal lines are sequentially driven first in the scan sequence according to the number of clock signals that occurred during the scan sequence setup period and instructing the scan signal output circuit which one of the odd-numbered scan signal lines and the even-numbered scan signal lines to drive first when alternately scanning; and a start signal generating circuit for generating, a number of clock cycles before driving a last scan signal line of the scan signal line driver circuit, a start signal to be supplied to a next scan signal line driver circuit, the number of clock signals being one clock signal less than a delay imposed on a first scan signal line of the scan signal line driver circuit during the scan sequence setup period such that a falling edge of a scan signal of the last scan signal line occurs at a same time as a rising edge of a scan signal of a first scan signal line of the next scan signal line driver circuit that is delayed by its associated scan sequence setup period, wherein: the variable length of the externally supplied start signal varies such that a different number of clock signals occur during the scan sequence setup period of the next scan signal line driver circuit; and when the next scan signal line driver circuit takes over driving of scan signal lines, a scan signal line driven immediately before the takeover is not adjacent to a scan signal line driven immediately after the takeover.