Patent ID: 6930927

Claim:
A line selector for a matrix of memory elements, comprising a plurality of matrix line group selection circuits, each one allowing the selection of a respective group of matrix lines according to a first address, each matrix line group including a plurality of matrix lines, associated with each matrix line group selection circuit, a respective plurality of matrix line selection circuits, each one for allowing the selection of at least one respective matrix line within the respective matrix line group according to a second address, the matrix line selection circuits comprising matrix line driver circuits for driving potentials of the matrix lines, flag means associated with each matrix line group, that can be set to declare a pending status of a prescribed operation to be conducted globally on the memory elements of the respective matrix line group, the flag means enabling, when set, the execution of the prescribed operation on the respective matrix line group, and means for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation, in alternative to the respective line group selection circuit.