Patent ID: 8332590

Claim:
A command processing pipeline to be coupled to a shared cache, the command processing pipeline comprising: a first command processing stage configured to sequentially receive a first cache command and a second cache command, and to sequentially process the first cache command and the second cache command, wherein the first command processing stage is configured to process the second cache command independently of an outcome of processing the first cache command by the first command processing stage; a second command processing stage coupled to the first command processing stage such that the first command processing stage and the second command processing stage are two consecutive command processing stages of a plurality of command processing stages of the command processing pipeline, the second command processing stage configured to sequentially receive the first cache command and the second cache command after processing by the first command processing stage, and to process the first cache command substantially simultaneously with the second cache command being processed by the first command processing stage; and a third command processing stage coupled to the second command processing stage, the third command processing stage configured to (i) receive the first cache command subsequent to the first cache command being processed by the second command processing stage, and (ii) process the first cache command by writing data associated with the first cache command to one of a valid memory and a dirty memory included in the cache.