Patent ID: 7162669

Claim:
An embedded memory having compressed redundancy information on an integrated circuit, comprising: a memory cell array; replacement cells; mapping logic coupled to the memory cell array and the replacement cells for electronically substituting the replacement cells for defective cells at at least one location in the memory cell array; programmable links for storing compressed redundancy information; and decoding logic for decompressing the compressed redundancy information stored in the programmable links and for providing decompressed redundancy information for controlling the mapping logic; wherein the embedded memory having compressed redundancy information is a memory of a cache memory subsystem of a processor integrated circuit selected from the group consisting of a tag memory and a data memory; and wherein the compressed redundancy information is encoded according to the formula: −(red0*red0)/2+(2*io 13 bits+3)*red0/2+red1−red0 where: red 0 is a column at which a first replacement cell column is substituted into the array, red 1 is a column at which a second replacement cell column is substituted into the array; and io_bits is the number of columns at which the first replacement cell column can be substituted into the memory.