Patent ID: 7935998

Claim:
An electronic device, comprising: a semiconductor on insulator substrate, said substrate including a buried insulating layer separating said substrate into an upper semiconductor layer between a top surface of said buried insulating layer and said top surface of substrate and a lower semiconductor layer; at least three vertical field effect transistors (FETs), each of said three or more FETs having a body formed in said upper semiconductor layer, a gate extending from said top surface of said substrate, a first source/drain formed around said gate adjacent to said top surface of said upper semiconductor layer and a second source drain formed around said gate adjacent to said buried insulating layer; and a body contact formed in said substrate between said at least three vertical FETs, said body contact self-aligned to all of said gates of said at least three vertical FETs, said body contact extending above and below said buried insulating layer and electrically connecting said upper semiconductor layer to said lower semiconductor layer.