Patent ID: 7642148

Claim:
A method of producing a semiconductor device, the method comprising: forming a first stress film on a first gate electrode and first source/drain areas of a first transistor area of a semiconductor substrate and on at least a portion of a third gate electrode of an interface area between the first transistor area and a second transistor area; forming a second stress film on a second gate electrode and second source/drain areas of the second transistor area of the semiconductor substrate and overlapping at least a portion of the first stress film on the third gate electrode of the interface area; forming a first interlayer insulating film on the first stress film and the second stress film; planarizing the first interlayer insulating film to expose the second stress film overlapping at least a portion of the first stress film on the third gate electrode, using the second stress film as a planarizing stopping layer; selectively etching at least a portion of the exposed second stress film at a faster rate relative to the planarized first interlayer insulating film to thereby thin a portion of the exposed second stress film that overlaps an underlying portion of the first stress film extending opposite the third gate electrode and is recessed relative to an upper surface of the planarized first interlayer insulating layer; and forming a second interlayer insulating film on the first interlayer insulating film and on the thinned portion of the second stress film, so that a height of an interface between the second interlayer insulating layer and the planarized first interlayer insulating layer relative to the semiconductor substrate is greater than a height of an interface between the second interlayer insulating layer and the thinned portion of the second stress film relative to the semiconductor substrate.