Patent ID: 7069378

Claim:
A content addressable memory (CAM) device, comprising: a first plurality of CAM array blocks configured to generate a first plurality of active hit signals in parallel in response to a search operation; a second plurality of CAM array blocks configured to generate a second plurality of active hit signals in parallel in response to the search operation; a first priority resolution circuit configured to resolve a first soft and hard priority competition between the first plurality of active hit signals; and a second priority resolution circuit configured to resolve a second soft and hard priority competition between the second plurality of active hit signals in a manner that relies on an outcome of the first soft and hard priority competition to identify whether any of the second plurality of active hit signals has a higher priority than a highest priority one of the first plurality of active hit signals; wherein said first priority resolution circuit is responsive to a first plurality of soft priority signals and is configured to generate a first plurality of hierarchical control signals in response to the first soft and hard priority competition; wherein said second priority resolution circuit is responsive to a second plurality of soft priority signals; and wherein at least some of the second plurality of soft priority signals are derived from the first plurality of hierarchical control signals.