Patent ID: 8667343

Claim:
A customized bit error rate (BER) tester for use in a receiver, comprising: a pattern generator circuit configured to generate a repetitive sequence of synchronization symbols for rapid pattern synchronization; a high-speed serial transceiver including a linear feedback shift register including taps configured to match received test sequences received over an optical channel; and an error detector coupled to the high-speed serial transceiver and configured to synchronize the high-speed transceiver, the error detector comprising: a histogram tracking module configured to track the error performance of the receiver by collecting bit level statistics including a first plurality of counters for recording a frequency and distribution of fade duration of a user definable block length of P n and a second plurality of counters for recording a frequency of contiguous error free bits of a user definable block length of M n consecutive bits; a bit error rate tracking configured to track the error performance of the receiver by collecting bit level statistics including: a user programmable parameter for defining a bit error rate J, wherein the user defined bit error rate occurs over a second user programmable parameter defining an averaging window of size K bits, wherein said second user programmable parameter triggers a re-synchronization of the receiver; and a third plurality of counters for recording a number of times a bit error rate J i was observed over a user definable block length of K consecutive bits; and a raw statistics tracking module configured to track the error performance of the receiver by collecting bit level statistics including: a first counter for recording the total number of bits transmitted over the optical channel; a second counter for recording the total number of bits dropped due to loss of synchronization; a third counter for recording the total number of bits transmitted while the receiver is in a state of synchronization; a fourth counter for recording the total number of bits in error while the receiver is in said state of synchronization; and a fifth counter for recording the total number of times the receiver entered into a state of synchronization.