Patent ID: 7676652

Claim:
A method of executing a sequence of variable length instructions stored prior to any fetching as part of decoding and execution within a plurality of discrete memory address regions within a memory of a data processing apparatus, said plurality of discrete memory address regions including a current memory address region and a following memory address region, said current memory address region and said following memory address region being non-contiguous with a gap therebetween, said method comprising the steps of: (i) detecting an attempt to execute a variable length instruction spanning two discrete memory address regions, said two discrete memory address regions being said current memory address region and said following memory address region and said attempt triggering a memory abort, said detecting together with said triggering causing further steps (ii)-(iv) to be performed; (ii) copying instruction data from an end portion of said current memory address region and a start portion of said following memory address region into a fix-up memory address region of said memory to form concatenated instruction data containing said variable length instruction, said fix-up memory address region being separate from said current memory address region and said following memory address region within said memory; (iii) diverting program execution flow to execute said current variable length instruction from within said concatenated instruction data in said fix-up memory address region; and (iv) restoring program execution flow to execute instructions following said variable length instruction from within said following memory address region.