Patent ID: 7671653

Claim:
An implicitly pulsed dual edge triggered pulsed latch comprising: a clock input configured to receive a clock signal; an overlapping clock generator operably coupled to the clock input and configured to generate a plurality of overlapping clock signals in response to the clock signal; a transparency circuit operably coupled to the overlapping clock generator and clock input, the transparency circuit having a first output node that transitions from a high resistance state to a low resistance state and back to the high resistance state in response to an edge transition on the clock signal; a transparent latch circuit comprising: an input node, a circuit output node and a transparency node, the transparency node operably coupled to the first output node and, in conjunction with the transparency circuit, is configured to cause the transparent latch to become transparent when the transparency node is at the low resistance state; and wherein the dual edge triggered pulsed latch passes a logic value on the input node to the circuit output node in response to the edge transition on the clock signal.