Patent ID: 7412671

Claim:
An apparatus for verifying an integrated circuit pattern comprising: a first generator section generating tolerance data corresponding to a target pattern set based on design data of a semiconductor device; a second generator section generating image data of a semiconductor device pattern formed based on the target pattern, wherein the second generator section generates the image data by imaging the semiconductor device pattern; an extraction section extracting contour data of the semiconductor device pattern from the image data supplied from the second generator section; and a data synthesizing section supplied with the tolerance data supplied from the first generator section and the contour data supplied from the extraction section, and overlapping the tolerance data with the contour data, wherein the data synthesizing section determines whether or not a crossover between the overlapped tolerance date and contour data exists, and further wherein the data synthesizing section converts the overlapped tolerance data and the contour data into a polar coordinate data, wherein the tolerance data has upper and lower limit values corresponding to one of a distance from at least one side of a contact pattern to one side of a wiring pattern parallel to said one side when the wiring pattern is connected with the contact pattern, and a distance between the wiring pattern and the contact pattern when the contact pattern is formed adjacent to the wiring pattern.