Patent ID: 7224701

Claim:
Apparatus for implementing frame header alterations in a network processor comprising: a frame alteration command decoder and frame alignment input stage receiving incoming packet frame data and frame information and frame alignment commands and providing a sequential output of a predetermined number of bytes of aligned frame data, and frame header alteration commands, first stage alteration engines coupled to said frame alteration command decoder and frame alignment input stage, said first stage alteration engines sequentially receiving said predetermined number of bytes of aligned frame data, said frame header alteration commands including first stage commands, and first stage command data and providing sequential altered frame data outputs; second stage alteration engines coupled to said first stage alteration engines, said second stage alteration engines sequentially receiving said altered frame data outputs of said first stage alteration engines, said frame header alteration commands including second stage commands and second stage command data and providing final sequential altered frame data; and each of said first stage alteration engines and second stage alteration engines including a plurality of byte-wise arithmetic logic units (ALUs) for performing respective first stage received commands and respective second stage received commands, each of said plurality of byte-wise ALU including inputs for receiving frame data, command data, register data, and commands, and including data and register data outputs.