Patent ID: 8527710

Claim:
A storage controller for controlling data inputs and outputs between a host computer and a storage device, comprising: a cache memory for storing data inputs and outputs between the host computer and the storage device; a shared memory for storing common control information that is required for at least one of command processing and control processing performed by the storage controller, the common control information including program setting information; a plurality of microprocessor packages each including a plurality of microprocessors, a package memory to which at least a portion of the common control information stored in the shared memory is copied as local control information items for the plurality of microprocessors of the microprocessor package, a plurality of local memory units which are respectively provided in correspondence with the microprocessors of the microprocessor package, and a plurality of purge message storage units that are respectively included within the local memory units of the microprocessor package for storing purge messages that are each transmitted from the microprocessor corresponding to the respective local memory unit for the purge message storage unit and that are each for reporting that the local control information items stored in the package memories of the other microprocessor packages are invalid; and a control information synchronization management unit for managing whether each of the local control information items is in sync with the common control information, wherein, in cases where the common control information is updated by any of the microprocessors, the updating microprocessor creates a purge message, stores the purge message in the purge message storage unit of the respective local memory unit for the microprocessor, and transmits a consolidated purge message, into which a plurality of purges messages that have identical, contiguous, or overlapping update locations and are stored in the purge message storage unit of the respective local memory unit for the microprocessor are consolidated, asynchronously with the common control information being updated to a specified one or more of the other microprocessor packages.