Patent ID: 8139416

Claim:
An integrated circuit, comprising: a memory array on a substrate, including: a plurality of memory cell strings, adjacent memory cell strings being separated from each other by an isolation region, each memory cell strings including a plurality of memory cells coupled in series, each adjacent pair of memory cells being coupled by a doped region; a plurality of word lines, each of the word lines being coupled to a memory cell from each of the plurality of memory cell strings; a plurality of bit lines, each bit line being coupled to every other doped region in a corresponding memory cell string; a common source line coupled to every other doped regions in each of the plurality of memory strings that are not coupled to any of the bit lines; a first global bit line coupled to a first bit line and a third bit line; a second global bit line coupled to a second bit line and a fourth bit line; a third global bit line coupled to a fifth bit line and a seventh bit line; a fourth global bit line coupled to a sixth bit line and an eighth bit line; a first select line coupled to a first switch electrically connecting the first global bit line to the first bit line, the first select line being coupled to a fifth switch electrically connecting the third global bit line to the fifth bit line; a second select line coupled to a second switch electrically connecting the second global bit line to the second bit line, the second select line being coupled to a sixth switch electrically connecting the fourth global bit line to the sixth bit line; a third select line coupled to a third switch electrically connecting the first global bit line to the third bit line, the third select line being coupled to a seventh switch electrically connecting the third global bit line to the seventh bit line; a fourth select line coupled to a fourth switch electrically connecting the second global bit line to the fourth bit line, the fourth select line being coupled to an eighth switch electrically connecting the fourth global bit line to the eighth bit line; and a fifth select line couples to a ninth switch electrically connecting a global source line to the common source line.