Patent ID: 6862548

Claim:
A method comprising: instantiating a first delay element on a programmable logic device, the device including a signal tree having a source node connected to first, second, and third destination branches, and first, second, and third logic blocks programmably connectable to the respective first, second, and third destination branches, each of the logic blocks having an input terminal and an output terminal, using a first programming sequence that includes: connecting the first destination branch to the input terminal of the first logic block; and connecting the output terminal of the first logic block to the input terminal of the second logic block; instantiating a second delay element on the device using a second programming sequence that includes: connecting the third destination branch to the input terminal of the third logic block; and connecting the output terminal of the third logic block to the input terminal of the second logic block: and measuring signal skew on the programmable logic device through the signal tree based on a difference in delay between the first and second delay elements.