Patent ID: 8502322

Claim:
A nonvolatile memory device comprising: a peripheral circuit that includes a control element that controls a nonvolatile memory cell formed above a substrate; a first wire that is formed above the peripheral circuit via an inter-layer dielectric film and is connected to the control element; a memory layer in which a plurality of memory-cell-array layers is stacked on the inter-layer dielectric film in which the first wire is formed, each of the memory-cell-array layers including a plurality of nonvolatile memory cells each of which includes a nonvolatile memory element arranged at intersection positions of a plurality of second wires that extend in a first direction and a plurality of third wires that are formed at a height different from the second wires and extend in a second direction, the nonvolatile memory element being sandwiched between the second wires and the third wires; contact plugs that connect between the second wires and the first wire and between the third wires and the first wire, and are formed in a peripheral portion of the memory layer; and drawn wire portions that are connect the second wires and the third wires with the contact plugs in the memory layer, wherein the drawn wire portions that are connected to a second wire and a third wire other than a second wire and a third wire of a bottom layer and a top layer of the memory layer are formed of a wire with a critical dimension in the nonvolatile memory device same as the second wires and the third wires and include two straight line portions that extend in a direction vertical to an extending direction of the second wires or the third wires and one of the straight line portions is connected to the contact plug on an upper surface and both side surfaces of the one of the straight line portions.