Patent ID: 7859339

Claim:
A differential amplification circuit comprising: a differential transistor pair which is constituted of a pair of n-channel MOS transistors whose gates are connected to a pair of differential input terminals, and whose sources are connected together; a current source circuit which is connected between the sources of the differential transistor pair and a ground, a gate of the current source circuit connected to a constant current bias voltage terminal; a current-mirror load circuit which is constituted of a pair of p-channel MOS transistors whose gates are connected together, whose sources are connected to a voltage supply, and whose drains are connected to drains of the n-channel MOS transistors forming the differential transistor pair; and a bias generation circuit for generating a gate bias voltage and a drain bias voltage applied to the p-channel MOS transistors forming the current-mirror load circuit in such a way that a same potential is set to both of the drains of the p-channel MOS transistors, wherein the bias generation circuit is constituted of a first resistor which is connected between the gates of the p-channel MOS transistors and the voltage supply, and a second resistor which is connected between the drain and the gate of one of the p-channel MOS transistors.