Patent ID: 7696811

Claim:
A design structure comprising: design data embodied in a machine-readable medium, said design data useable by a computer based system for designing, manufacturing, or testing an integrated circuit, said integrated circuit comprising: a first set of field effect transistors (FETs) having a designed same first threshold voltage and a second set of FETs having a designed same second threshold voltage, said first threshold voltage different from said second threshold voltage; a first monitor circuit containing at least one FET of said first set of FETs and configured to generate a first output signal based on a first switching speed of said at least one FET of said first FETs; a second monitor circuit containing at least one FET of said second set of FETs and configured to generate a second output signal based on a second switching speed of said at least one FET of said second FETs; a compare circuit configured to generate a compare signal based on said first output signal and said second output signal, said compare circuit including a first edge counter connected between said first monitor circuit and a first comparator, a second edge counter connected between a reference clock and said first comparator and third edge counter connected between said second monitor circuit and said comparator; a control unit responsive to said compare signal and configured to generate a control signal based on said compare signal; an adjustable voltage regulator responsive to said control signal and configured to supply a bias voltage to wells of FETs of said second set of FETs, the value of said bias voltage based on said control signal; and a memory device containing a ratio of said first performance specifications of said first monitor circuit to a second performance specification of said second monitor circuit, said memory device coupled to said comparator.