Patent ID: 8441843

Claim:
A semiconductor integrated circuit device comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of the plurality of memory cells including first and second storage nodes, a first inverter, an input of which is connected to the first storage node and an output of which is connected to the second storage node, including a first p-channel transistor and a first n channel transistor, a second inverter, an input of which is connected to the second storage node and an output of which is connected to the first storage node, including a second p-channel transistor and a second n-channel transistor, a third n-channel transistor connected to the first storage node, and a fourth n-channel transistor connected to the second storage node; a plurality of word lines provided correspondingly to the plurality of rows, respectively, each word line being connected to gate electrodes of the third and fourth n-channel transistors of the memory cells arranged along a first direction in the corresponding row; a plurality of bit line pairs provided correspondingly to the plurality of columns, respectively, each bit line pair having a first bit line connected to the third n-channel transistors of the memory cells arranged along a second direction in the corresponding column and a second bit line connected to the second n-channel transistors of the memory cells arranged along the second direction in the corresponding column; a plurality of memory cell power supply lines provided correspondingly to the plurality of columns, respectively, each memory cell power supply line being connected to source electrodes of the first and second p-channel transistors in the memory cells arranged in the corresponding column, a power supply line that supplies a power voltage; and a plurality of power transistors connected to the plurality of memory cell power supply lines, respectively, each power transistor making an electrical pass between the power supply line and the memory cell power supply line connected thereto, wherein, in each of the plurality of memory cells, the first n-channel transistor, the first p-channel transistor and the third n-channel transistor are arranged along the first direction with the first p-channel transistor located between the first and third n-channel transistors, the second n-channel transistor, the second p-channel transistor and the fourth re-channel transistor are arranged along the first direction with the second p-channel transistor located between the second and fourth n-channel transistors, the second and third n-channel transistors are arranged along the second direction, and the first and fourth n-channel transistors are arranged along the second direction.