Patent ID: 7457154

Claim:
A memory array system, comprising: a plurality of word lines; a plurality of first bit lines or first source/drain lines; a plurality of second bit lines or second source/drain lines; and a plurality of memory units, each memory unit comprising: a gate electrode, coupled to one of the word lines; a gate dielectric layer laid below the gate electrode; an active area, comprising: a first source/drain region, coupled to one of the first source/drain lines or the first bit lines, further comprising a first multi-layer dielectric spacer formed between the first source/drain region and the gate electrode to store electrons or electric charge; a second source/drain region, coupled to one of the second source/drain lines or the second bit lines, further comprising a second multi-layer dielectric spacer formed between the second source/drain region and the gate electrode to store electrons or electric charge; and a semiconductor channel formed between said first source/drain region and second source/drain region; a metal-semiconductor compound layer formed over the gate electrode, first source/drain region and second source/drain region; a selecting/driving circuit coupled to the word lines, the first bit lines and the second bit lines to select corresponding memory units based on predetermined address, a sensing circuit coupled to the selecting/driving circuit to amplify output signals of data stored in the corresponding memory units; and a controller coupled to the selecting/driving circuit and the sensing circuit to perform memory operations on the memory units.