Patent ID: 6842728

Claim:
A circuit arrangement for use in communicating multiple signals over a common signal path between first and second clock domains during hardware-based logic emulation, wherein the first clock domain is emulated via a first multi-step evaluation cycle and the second domain is emulated via a second multi-step evaluation cycle, the circuit arrangement comprising: (a) a buffer interposed in a common signal path between first and second clock domains, the buffer including first and second locations, the first location associated with a first evaluation step in the first multi-step evaluation cycle and a first evaluation step in the second multi-step evaluation cycle, and the second location associated with a second evaluation step in the first multi-step evaluation cycle and a second evaluation step in the second multi-step evaluation cycle; and (b) logic circuitry coupled to the buffer, the logic circuitry configured to store in the first location of the buffer a first time-multiplexed signal output over the common signal path by the first clock domain during the first evaluation step in the first multi-step evaluation cycle, and to store in the second location of the buffer a second time-multiplexed signal output over the common signal path by the first clock domain during the second evaluation step in the first multi-step evaluation cycle, the logic circuit further configured to output the first time-multiplexed signal stored in the first location over the common signal path to the second clock domain during the first evaluation step in the second multi-step evaluation cycle, and to output the second time-multiplexed signal stored in the second location over the common signal path to the second clock domain during the second evaluation step in the second multi-step evaluation cycle.