Patent ID: 7473595

Claim:
A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), comprising the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon substrate; etching the insulation oxide layer until the P-type silicon substrate is exposed to form a bit line contact hole on the drain; implanting arsenic ions into the P-type silicon substrate via the bit line contact hole to form an arsenic bit line contact window; implanting phosphorus ions into the P-type silicon substrate via the bit line contact hole to form a phosphorus bit line contact window below the arsenic bit line contact window; and selecting trivalent phosphorus ions via a magnetic field and implanting selected trivalent phosphorus ions into the P-type substrate after ionizing phosphine.