Patent ID: 7898041

Claim:
An apparatus comprising: a plurality of parallel semiconductor bodies, each of the plurality having a top surface and a pair of laterally opposite sidewalls, each of said plurality having a channel region between a source region and a drain region; a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies; a first source contact to a source region of at least a first of the plurality of parallel semiconductor bodies; a second source contact to a source region of at least a second, of the plurality of parallel semiconductor bodies, wherein the second source contact does not contact the first of the plurality of parallel semiconductor bodies and the first source contact does not contact the second of the plurality of parallel semiconductor bodies; and a single drain contact to a drain region of at least both the first and second of the plurality of parallel semiconductor bodies, wherein the drain contact is of a same metallization level as the first and second source contacts.