Patent ID: 6845478

Claim:
A method of testing memory, comprising: providing one or more semiconductor wafers having one or more semiconductor chips thereon, each said chip comprising one or more segments, each said segment comprising one or more memory cells; providing a programmable testing apparatus comprising one or more test pattern generators and a test bed adapted to receive said one or more wafers in communicative contact so as to address individual memory cells, segments, chips, and wafers and transmit information thereto and receive information therefrom; receiving one or more test commands; constructing a test sequence of one or more commanded tests from said test commands; constructing at least one header comprising identification information for at least one of said wafer, chip, segment, and memory cell, wherein said identification information comprises location information for at least one of said wafer, chip, segment, and memory cell, and a test identifier for the test sequence to be applied to at least one of said wafer, chip, segment, and memory cell; testing at least one of said wafer, chip, segment, and memory cell with the test sequence using one or more test patterns generated by said test pattern generator; collecting the results of said testing and passing them to a display device; passing said identification information to said display device; constructing and displaying a graphical representation of said test results using said identification information.