Patent ID: 7613030

Claim:
A semiconductor memory device comprising a memory cell array having a plurality of memory cells, wherein each of the plurality of memory cells comprises: an analog switch; a first inverter; a second inverter; and a clocked inverter, and wherein: a first terminal of the analog switch is electrically connected to a first data line, a second terminal of the analog switch is directly electrically connected to an input terminal of the first inverter, an output terminal of the second inverter, and an input terminal of the clocked inverter, an output terminal of the first inverter is electrically connected to an input terminal of the second inverter, an output terminal of the clocked inverter is electrically connected to a second data line, each of the analog switch and the clocked inverter is electrically connected to at least one word line, the word line electrically connected to the analog switch is different from the word line electrically connected to the clocked inverter, the analog switch includes a first transistor and a second transistor, the first terminal of the analog switch is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, and the second terminal of the analog switch is electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor.