Patent ID: 8296518

Claim:
An arithmetic processing apparatus comprising: a TLB that stores a part of a TSB area included in a memory unit accessed by the arithmetic processing apparatus, the TSB area storing an address translation pair for translating a virtual address into a physical address; a cache memory that temporarily stores the address translation pair; a TSB base-physical-address storing unit that stores a TSB base physical address that is a starting physical address of the address translation pair stored in the memory unit; a TSB pointer calculating unit that calculates, based on the TSB base physical address and a virtual address to be converted, a TSB pointer used in obtaining from the TSB area a corresponding address translation pair corresponding to the virtual address to be converted; and a translation pair obtaining unit that obtains the corresponding address translation pair from the TSB area using the TSB pointer calculated, and stores the corresponding address translation pair in the cache memory, if the corresponding address translation pair is not retrieved from the TLB or the cache memory, wherein if the corresponding address translation pair is not retrieved from the TLB, the translation pair obtaining unit verifies, via a trap handling process of an OS, whether the corresponding address translation pair is stored in the cache memory, and the translation pair obtaining unit stores the corresponding address translation pair obtained from the TSB area using the TSB pointer in the cache memory prior to the verification via the trap handling process.