Patent ID: 7295029

Claim:
A method of chip-level packaging an integrated circuit (IC) die, comprising: providing a plurality of singulated die chips, each comprising a die and at least one electrical contact point associated with the die; providing a cap wafer; forming electrically conductive paths through the cap wafer at positions corresponding to respective ones of the electrical contact points on respective ones of the plurality of singulated die chips, such that at least one of the electrically conductive paths extends from a first surface of the cap wafer to a second surface of the cap wafer; before cutting the cap wafer, bonding each of the plurality of singulated die chips to the cap wafer, such that the ends of the conductive paths on the first surface of the cap wafer are electrically connected to the respective electrical contact points on the respective plurality of singulated die chips; and cutting the cap wafer between pairs of the singulated die chips, wherein forming each electrically conductive path comprises: drilling a hole through the cap wafer; and filling the hole with an electrically conductive material by: pressing a mixture of powdered metal alloy paste containing an organic solvent into the hole; and subsequently burning away the organic solvent and leaving a hardened metal alloy.