Patent ID: 8133774

Claim:
A method of forming a semiconductor structure comprising: forming at least two field effect transistors on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate; forming a shallow trench isolation structure in said top semiconductor layer, wherein said shallow trench isolation structure laterally abuts and surrounds said at least two field effect transistors; forming a middle-of-line (MOL) dielectric layer over said at least two field effect transistors and said shallow trench isolation structure; and forming at least one conductive via extending from a top surface of said MOL dielectric layer through said MOL dielectric layer, said shallow trench isolation structure, a buried insulator layer, and to a top surface of a bottom semiconductor layer of said SOI substrate, wherein said at least one conductive via is interposed between said at least two field effect transistors and separates said at least two field effect transistors, and said at least one conductive via laterally surrounds said at least two field effect transistors and does not contact any semiconductor material in said top semiconductor layer.