Patent ID: 8080457

Claim:
A fabrication method of a trenched power semiconductor structure, comprising the steps of: providing a substrate, which has a drain zone being defined therein; forming a gate trench in the substrate; forming a dielectric layer on inner surfaces of the gate trench; forming a spacer covering the dielectric layer on a sidewall of the gate trench; forming a polysilicon structure in a space at a bottom of the gate trench, and the space being defined by the spacer; removing an unwanted portion of the spacer with the dielectric layer and the polysilicon structure as a mask by using etching back technology; removing an unwanted portion of the dielectric layer with a remained portion of the spacer as an etching mask to expose the inner surface of an upper portion of the gate trench; wherein the remained portion of the spacer being left on the sidewall of the gate trench; forming a gate dielectric layer on the inner surface of the upper portion of the gate trench; and forming a polysilicon gate in the upper portion of the gate trench; wherein the polysilicon structure is used to increase a distance between the polysilicon gate and the drain zone; wherein an upper edge of the spacer is located above an upper edge of the polysilicon structure.