Patent ID: 8264003

Claim:
A merged cascode transistor circuit comprising: an input voltage signal source having an input voltage signal; a constant voltage source having a predetermined constant voltage; a merged cascode transistor comprising: a semiconductor element; a source electrode electrically connected to a top surface of the semiconductor element; a drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the source electrode; a first gate positioned between the source electrode and the drain electrode and coupled to the semiconductor element to form a first portion of the transistor; and a second gate positioned adjacent to the first gate, and between the source electrode and the drain electrode to form a second portion of the transistor, wherein the second gate includes a field plate and is also coupled to the semiconductor element; wherein the first gate is connected to the input voltage signal source such that conduction of the first portion of the transistor is based on a value of the input voltage signal and the second gate is connected to the constant voltage source such that the second portion of the transistor conducts until a voltage difference between the predetermined constant voltage and a voltage at a node in the semiconductor element between the first portion and the second portion of the transistor reaches a predetermined level, wherein the first portion of the transistor is an enhancement mode transistor and the second portion of the transistor is a depletion mode transistor, and wherein a drain region of the enhancement mode transistor is merged with a source region of the depletion mode transistor at the node in the semiconductor element.