Patent ID: 8305306

Claim:
A semiconductor device comprising: a first wiring; a second wiring; a third wiring; a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor; a second capacitor; and a transistor, wherein a first terminal of the first switch is electrically connected to the first wiring; wherein a second terminal of the first switch is electrically connected to a first terminal of the second switch, wherein the first terminal of the second switch is electrically connected to a first terminal of the first capacitor, wherein a second terminal of the second switch is electrically connected to a source of the transistor, wherein a first terminal of the third switch is electrically connected to a second terminal of the first capacitor, wherein a second terminal of the third switch is electrically connected to a first terminal of the fourth switch, wherein the first terminal of the fourth switch is electrically connected to a drain of the transistor, wherein a second terminal of the fourth switch is electrically connected to the second wiring, wherein a first terminal of the fifth switch is electrically connected to the source of the transistor, wherein a second terminal of the fifth switch is electrically connected to the third wiring, wherein a gate of the transistor is electrically connected to a second terminal of the first capacitor, wherein the source of the transistor is electrically connected to a load, wherein a first terminal of the second capacitor is electrically connected to the second terminal of the first switch, wherein a second terminal of the second capacitor is electrically connected to the source of the transistor, wherein each of the first switch, the second switch, the third switch, the fourth switch and the fifth switch is configured to control conductive state and non-conductive state, wherein the first wiring is configured to transmit an image signal voltage, wherein the second wiring is configured to transmit a current flowing in the transistor, wherein the third wiring is configured to transmit a predetermined voltage, and wherein the transistor is configured to control a value of a current flowing in the load.