Patent ID: 8130190

Claim:
A display controller on one large scale integrated circuit (LSI) and capable of adjusting a frame frequency for a display panel to be coupled thereto, the display controller comprising: an interface which receives display data from an external device to be coupled to the display controller; a memory which stores the display data; a register capable of setting from the external device a division ratio of a first clock signal, a number of reference clocks of a second clock signal per a scanning period, and a number of lines of the display panel; a signal generator which divides the first clock signal by the division ratio to generate the second clock signal, and which generates a signal having the frame frequency based on the number of the second clock signal per the scanning period and the number of lines of the display panel stored in the register; a voltage generator which generates a plurality of driving voltage signals; and a data line driver which converts the display data into ones of the plurality of driving voltage signals to be provided to the display panel; wherein the frame frequency is adjustable by changing the division rate and/or the number of reference clocks of the second clock signal per said scanning period in the register from the external device without changing the number of lines of the display panel in the register.