Patent ID: 6960818

Claim:
A shallow trench isolation structure in a substrate, said shallow trench isolation structure comprising: a trench in said substrate; a nitride liner recessed within said trench and the nitride liner forming a partially enclosed volume, said partially enclosed volume being completely filled with a dielectric material which also completely fills the trench; wherein said nitride liner is recessed such that an uppermost surface of said nitride liner is recessed to a first depth that is greater than a transistor channel depth, Dc, of a transistor that is disposed in a well beside said shallow trench isolation structure, the recessed nitride liner being dimensioned and configured to prevent hot carrier effects due to charge trapping for charge which traverses a channel of the transistor; the dielectric material including an oxide disposed above said nitride liner such that said oxide extends above the uppermost surface of said nitride liner to substantially a top surface of said substrate, such that substantially no polysilicon material is disposed within the trench.