Patent ID: 8085817

Claim:
An automatic clock synchronization controller circuit for use with a counter clock flow pipelined circuit that includes a cascade of processing modules in which each processing module receives input data from a previous module in the cascade, processes the received data and then sends output results to a following module in the cascade, the automatic clock synchronization controller circuit being arranged to receive two clock input signals, one a synchronized clock signal and the other a reference clock signal, and to provide a plurality of output signals to control a selectable delay of a plurality of clock synchronization buffer circuits, comprising: a phase comparator with two inputs and two outputs, one input being for a synchronized clock signal and the other input being for a reference clock signal, one output being to indicate when the two clock signals are in phase and when they are out of phase and the other output being used to indicate if the phase of the synchronized clock signal leads or lags the phase of the reference clock signal in the event the two signals are out of phase; and a finite state machine with two inputs and two outputs, one input coming from the phase comparator and being used to indicate when the two clock signals are in phase or out of phase and the other input also coming from the phase comparator and being used to indicate if the phase of the synchronized clock signal leads or lags the phase of the reference clock signal in the event the two clock signals are out of phase, one output going to a phase adjuster circuit and being used to indicate if an increase in delay is needed and the other output also going to the phase adjuster circuit and being used to indicate if a decrease in delay is needed; and a phase adjuster circuit, the phase adjuster circuit comprising: a first input from the finite state machine and being used to indicate if the total amount of delay needs to be increased, a second input from the finite state machine and being used to indicate if the total amount of delay needs to be decreased, and a plurality of delay select signal outputs connecting the phase adjuster circuit to a delay select signal input of each of the clock synchronization buffer circuits, each delay select signal output being used to indicate a delay select signal associated with a corresponding clock synchronization buffer; wherein a clock signal distributed to each of the processing modules in the cascade is shifted in phase from the input clock signal based on a delay select signal; and further wherein the distribution of clock signals to each of the processing modules occurs in the opposite direction to the flow of data through the local processing modules.