Patent ID: 7283083

Claim:
An apparatus including double-sampled pipeline analog-to-digital conversion (ADC) circuitry having a plurality of serially coupled 1.5 bit ADC stages, comprising: at least one electrode to convey an upstream residue signal from an upstream ADC stage; residue signal generation circuitry coupled to said at least one electrode and responsive to said upstream residue signal, an analog quantization signal, a reset control signal and a first portion of a plurality of clock signals by providing a downstream residue signal; sub-ADC circuitry coupled to said at least one electrode and responsive to said upstream residue signal and a latch control signal by providing first and second digital quantization signals; digital-to-analog conversion (DAC) circuitry coupled to said sub-ADC circuitry and said residue signal generation circuitry, and responsive to said first and second digital quantization signals by providing said analog quantization signal; and timing and control circuitry coupled to said residue signal generation circuitry and said sub-ADC circuitry, and responsive to at least a main clock signal by providing said reset control signal, said first portion of said plurality of clock signals and said latch control signal, wherein each one of said first portion of said plurality of clock signals includes respective leading and trailing signal state transitions, said latch control signal includes leading and trailing signal state transitions, and at least one of said leading and trailing latch control signal state transitions occurs approximately midway said leading and trailing clock signal state transitions.