Patent ID: 7466586

Claim:
A random access memory, comprising: capacitor as a storage element, wherein is formed by an insulator(s) between a first plate and a second plate; and diode as an access device, wherein includes four terminals, a first terminal is p-type, a second terminal is n-type, a third terminal is p-type, a fourth terminal is n-type, the first terminal is connected to a word line, the second terminal is connected to the first plate of the capacitor which serves as a storage node, the third terminal is floating, and the fourth terminal is connected to a bit line to write or read data; and plate line is connected to the second plate of the capacitor which couples to the first plate of the capacitor, and the word line is turned off to cut holding current of the diode during standby; and write sequence, wherein the word line is raised to high level first, and then the plate line is lowered to ground level to clear previous data, then the bit line is asserted, after then the plate line is returned to high level, but the storage node is not coupled by returning the plate line because the diode is in on state when write data is logic high, otherwise the storage node is coupled to higher than logic high level because the diode is in off state when the write data is logic low, after then the word line is de-asserted to ground level, and finally the bit line is de-asserted to ground level; and read sequence, wherein the word line is asserted to high level first, which enables the diode to detect the storage node voltage whether it is forward bias or not, thus the diode is turned on when stored data is logic high otherwise it is not turned on when the stored data is logic low, and then the diode transfers charges to a data latch when the stored data is logic high, otherwise it does not when the stored data is logic low; and data latch including pull-down transistor, current mirror and two inverter-type latch, wherein the pull-down transistor is turned on by the diode when the stored data is logic high, at the same time the current mirror repeats the current and changes latch node from a pre-charge state, after then the latch node is sustained by the latch which the latch node becomes input of first inverter, and it is also connected to output of second inverter, and input of second inverter is output of first inverter, otherwise the current mirror does not flow current when the stored data is logic low, when read.