Patent ID: 6979986

Claim:
A switch shunt regulator (S 3 R) having a power input terminal (INS 3 R) connected to a power source (SA) and coupled to a power output terminal (OUTS 3 R) to which a load is connected, said regulator comprising a comparator (OA, R 1 –R 4 ) having a comparator output coupled to an input of a controlled shunt switch (SW, TR, R 6 –R 7 ), said switch being connected between said power input terminal and a mass terminal (VSS), said comparator being adapted to activate said controlled shunt switch upon comparison of a voltage received at a control input (INCTR) of said regulator with a reference voltage applied at a reference input (Vref) of said comparator, and said comparator activating said controlled shunt switch a predetermined delay (d 4 =t 4 −t 1 ) after having performed said comparison, characterized in that said switch shunt regulator (S 3 R) further comprises a phase anticipator circuit (PAC: DP, CP, R 5 ) coupled between the output of said comparator (OA, R 1 –R 4 ) and the input of said controlled shunt switch (SW, TR, R 6 –R 7 ), said phase anticipator circuit being adapted to reduce the first mentioned predetermined delay (d 4 =t 4 −t 1 ) between said comparator having performed said comparison and said switch being activated to a second predetermined delay (d 2 =t 2 −t 1 ) relatively shorter than said first predetermined delay.