Patent ID: 6861680

Claim:
An electrostatic discharge (ESD) protection circuit for protecting a silicon-on-insulator integrated circuit formed over an insulating layer, said ESD protection circuit comprising: an electrically conductive pad fabricated over said insulating layer; a conductor segment fabricated over said insulating layer, said conductor segment connecting said pad directly to a first node; a first voltage supply rail fabricated over said insulating layer; a second voltage supply rail fabricated over said insulating layer; a first primary diode fabricated over said insulating layer and connected between said first node and said first voltage supply rail; a second primary diode fabricated over said insulating layer and connected between said first node and said second voltage supply rail; an ESD clamp circuit fabricated over said insulating layer and connected between said first voltage supply rail and said second voltage supply rail; a resistor fabricated over said insulating layer and coupled between said first node and a second node coupled to a portion of said integrated circuit; and an channel transistor fabricated over said insulating layer, both of the gate and source of said n channel transistor connected to said second voltage supply rail, and the drain of said n channel transistor coupled to said second node.