Patent ID: 7099328

Claim:
An integrated circuit for processing events related to communication packets, said integrated circuit comprising: a core processor configured to execute software to process a series of communication packets, the processing of each packet being an event and having associated data and context information; and a co-processor comprising a plurality of state information buffers for storing state information, a plurality of context buffers for storing context information associated with a plurality of events and a plurality of data buffers for storing data associated with the plurality of events where the state information comprises a data buffer pointer pointing to one of the plurality of data buffers and a context buffer pointer pointing to one of the plurality of context buffers, where the plurality of state information buffers, the plurality of context buffers and the plurality of data buffers are formed as special purpose dedicated hardware buffers in the integrated circuit; the state information is associated with events wherein each of said state information buffers has an in-use counter indicating the number of events associated with the contents of said buffer.