Patent ID: 8019907

Claim:
A memory controller comprising: an input/output (I/O) circuit configured to operate as either a parallel interconnect or a serial interconnect dependent upon a state of a mode selection signal; wherein during operation as the parallel interconnect, the I/O circuit is configured to provide direct connection between an output of the memory controller and one or more memory modules, wherein the parallel interconnect includes: a plurality of bidirectional data signal paths configured to convey data between the memory controller and the one or more memory modules; a plurality of unidirectional address and command signal paths configured to convey address and command information from the memory controller to the one or more memory modules; and one or more clock signal paths each configured to convey a parallel clock signal from the memory controller to each of the one or more memory modules; wherein during operation as the serial interconnect, the I/O circuit is configured to provide direct connection between the output of the memory controller and one or more data buffer units interposed between the memory controller and the one or more memory modules, wherein each data buffer unit is configured to buffer memory data that is being read from or written to the one or more memory modules, and wherein the serial interconnect includes a separate serial interconnect including a plurality of serial data paths for connection to a corresponding one of the one or more data buffer units; and wherein the I/O circuit includes a number of single ended output drivers and a number of differential output drivers, and during a change from the parallel interconnect to the serial interconnect, the I/O circuit is configured to change connections of a portion of I/O pins of the memory controller from the single ended output drivers to the differential output drivers.