Patent ID: 8302042

Claim:
A method of designing an integrated circuit, comprising: receiving a functional description that is in a first format of said integrated circuit; partitioning said functional description that is in said first format into a plurality of entities based on a plurality of rules by using a computer, wherein each entity maintains a respective partition of said functional description in said first format; synthesizing said functional description that is in said first format of each entity into a gate-level implementation to form a plurality of synthesized entities by using said computer; and after said synthesizing said functional description that is in said first format, using said plurality of synthesized entities to create a physical design implementation for said integrated circuit that satisfies a plurality of design constraints by using said computer, wherein each synthesized entity includes a link to said respective partition of said functional description that is in said first format and that is synthesized into a respective gate-level implementation, wherein said respective partition of said functional description that is in said first format is accessible for resynthesis by using said link.