Patent ID: 8412985

Claim:
A system comprising: a processor to process executable instructions to read and/or write data; a main memory portion and a spare memory portion to store signals representative of said data; a register to receive from an error detection component, and to store, signals representative of bit errors detected during a read process; a multiplexer to physically redirect information of a read or write process from/to a data path of a single row of said main memory portion to/from a data path of a single row of said spare memory portion during processing of said executable instructions, wherein said multiplexer performs said data path redirection based, at least in part, on said signals stored in said register; and a memory module comprising said main memory portion, said spare memory portion, and additional memory portions residing on multiple dies, wherein individual die among said multiple dies include additional multiplexers, and wherein said signals stored in said register are used to operate said additional multiplexers.