Patent ID: 8723770

Claim:
A flat panel display apparatus, comprising: a first pixel region on a substrate and defined by an intersection between a first gate line and a data line, the first pixel region including a first transistor and a first capacitor, and the first pixel region being covered by a first pixel electrode; a second pixel region adjacent to the first pixel region and defined by an intersection between a second gate line and the data line, the second pixel region being covered by a second pixel electrode; the first gate line extending in a first direction, the first gate line being positioned between the first pixel electrode and the second pixel electrode; a second capacitor included in the second pixel region, the second capacitor including a first transparent conductive layer and a second transparent conductive layer; a transparent shielding portion extending from the second transparent conductive layer of the second capacitor toward the first pixel region, the transparent shielding portion covering two opposite edges of the first gate line between the first pixel electrode and the second pixel electrode; and a second transistor in the second pixel region and connected to the second pixel electrode, the second transistor including: a semiconductor layer on the substrate, the semiconductor layer including a channel region, a source region, and a drain region, a gate electrode on the channel region with a first insulating layer between the gate electrode and the channel region, the gate electrode protruding from the second gate line, and a source electrode and a drain electrode of the second transistor connected to the source region and the drain region through a second insulating layer and a third insulating layer on the gate electrode, wherein the second capacitor includes a capacitor wiring line formed of a same material and in a same layer as the gate electrode, the capacitor wiring line directly contacting the first transparent conductive layer, and wherein: the first transparent conductive layer is on the capacitor wiring line, the second transparent conductive layer corresponds to the first transparent conductive layer, the second insulating layer being between the second transparent conductive layer and the first transparent conductive layer, and the second transparent conductive layer is connected to one of the source electrode and the drain electrode of the second transistor.