Patent ID: 7944191

Claim:
A switch mode power supply (SMPS) capable of operating in three different operational modes including a buck mode, a boost mode, and a buck-boost mode, comprising: a power stage further including a plurality of switches operatively switched to generate an output signal that has a predetermined relationship with an input signal, depending on which operational mode has been selected; and a controller stage for determining said operational modes, each of said operational modes being set by determining logic values of a first control signal at a first clock signal of fixed frequency and a second control signal at a second clock signal of fixed frequency respectively, said controller stage operable to change said logic values of said first control signal and said second control signal by comparing feedback signal (FB) to a reference signal (V ref ), wherein said controller stage further comprises: (a) a clock-and-ramp generator for generating said first clock signal, said second clock signal, and a ramp signal, wherein said clock-and-ramp generator further comprises: (i) an oscillator circuit operable to generate a fixed frequency clock signal; and (ii) a frequency divider, electrically coupled to said oscillator circuit, operable to receive said fixed frequency clock signal and to generate said first clock signal and said second clock signal; (b) a duty-cycle-generator for generating said first control signal and said second control signal; and (c) a mode detector for selecting one of said operation mode wherein said clock-and-ramp generator further comprises: a current source operable to generate a fixed current; a first NAND gate electrically coupled to receive said first clock signal to drive a first n-channel Metal Oxide Semiconductor transistor; a second NAND gate electrically coupled to receive said second clock signal to drive a second n-channel Metal Oxide Semiconductor transistor; an offset voltage source, electrically coupled to said second nMOS transistor operable to generate a DC offset voltage proportional to said fixed frequency and said phase difference between said first clock signal and said second clock signal; and a capacitor electrically coupled to said current source, said first nMOS transistor and said second nMOS transistor.