Patent ID: 8004088

Claim:
A chip comprising: a silicon substrate; a first internal circuit in or on said silicon substrate; a driver, receiver or I/O circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit; a first via in said dielectric layer and vertically over said first internal circuit, wherein said first via is connected to said first internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride; a second via in said passivation layer, wherein said second via is connected to said first interconnecting structure; a third via in said passivation layer and vertically over said first via, wherein said third via is connected to said first via; and a second interconnecting structure over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.