Patent ID: 7461239

Claim:
A method, in a data processing device having an instruction pipeline and a load/store pipeline, for processing load instructions, comprising: receiving a load instruction; associating the load instruction with a load tag (LTAG); issuing the load instruction and the LTAG to the load/store pipeline; attempting to retrieve data corresponding to the load instruction from a first cache; determining whether the attempt to retrieve the data corresponding to the load instruction results in a cache hit or a cache miss; and generating an entry in a load table data structure of a load target buffer based on the LTAG and results of the attempt to retrieve data corresponding to the load instruction, wherein generating an entry in the load table data structure comprises: generating an entry in the load table that is indexed by the LTAG associated with the load instruction; and marking the entry as a cache hit or a cache miss based on results of determining whether the attempt to retrieve the data corresponding to the load instruction results in a cache hit or a cache miss, and wherein if the results of determining are a cache miss, the method further comprises: recycling the data corresponding to the load instruction from a memory subsystem; and storing the recycled data in the entry in the load table.