Patent ID: 7793085

Claim:
A memory control circuit provided with an instruction pre-fetch function, for controlling the reading of instructions to be fetched by a CPU (Central Processing Unit), from a memory, comprising: a branch-destination buffer for caching a branch-destination instruction and a branch-destination-instruction address when an instruction address output from the CPU becomes inconsecutive to one another due to a branch instruction, and for outputting, when the instruction address output from the CPU matches a cached instruction address, the corresponding branch-destination instruction to the CPU; an address comparison circuit for comparing the branch-destination-instruction address determined by the branch instruction with a branch-source-instruction address; a difference comparison circuit for comparing the difference between a plurality of bits of the branch-source-instruction address and a plurality of bits of the branch-destination-instruction address determined by the branch instruction with a predetermined reference value; and a buffer-update control circuit for updating data of the branch-destination buffer by the branch-destination instruction only when it is determined according to the result of comparison performed by the address comparison circuit that the branch-destination-instruction address is in a negative direction from the branch-source-instruction address and the difference comparison circuit determines that the difference is equal to or smaller than the reference value; wherein, when the address comparison circuit receives a branch signal reporting that the instruction address output from the CPU has become inconsecutive to one another, from the CPU, the address comparison circuit compares the branch-destination-instruction address determined by the branch instruction with the branch-source-instruction address.