Patent ID: 7465634

Claim:
A method of forming an integrated circuit device, comprising: forming an n-FET gate dielectric on a substrate and a p-FET gate dielectric on the substrate; forming an n-FET gate electrode on the n-FET gate dielectric and a p-FET gate electrode on the p-FET gate dielectric, wherein the n-FET gate electrode and the p-FET gate electrode each comprise metal, wherein the n-FET gate dielectric is located between the n-FET gate electrode and the substrate at an n-FET channel region, and the p-FET gate dielectric is located between the p-FET gate electrode and the substrate at a p-FET channel region; forming an n-FET spacer structure adjacent to the n-FET gate electrode; forming a p-FET spacer structure adjacent to the p-FET gate electrode; forming an elevated n-FET source/drain structure adjacent to the n-FET gate electrode, such that the n-FET spacer structure is located at least partially between the elevated n-FET source/drain structure and the n-FET gate; forming an elevated p-FET source/drain structure adjacent to the p-FET gate electrode, such that the p-FET spacer structure is located at least partially between the elevated p-FET source/drain structure and the p-FET gate electrode; and siliciding at least a first portion of the elevated n-FET source/drain structure and at least a first portion of the elevated p-FET source/drain structure in a source/drain-structure silicidation step, wherein at least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the elevated n-FET source/drain structure and for the elevated p-FET source/drain structure, wherein the at least a first portion of the elevated n-FET source/drain structure extends to at least the surface of the substrate.