Patent ID: 8441879

Claim:
A semiconductor device comprising: at least one memory bank divided into a plurality of segments each including a plurality of memory cells; a refresh counter that generates a refresh address, wherein among memory cells designated by the refresh address within the memory bank, memory cells belonging to all of the segments are refreshed in a first operation mode, and among the memory cells designated by the refresh address within the memory bank, memory cells in at least one designated segment are refreshed and memory cells in at least one undesignated segment are not refreshed in a second operation mode, a segment address register that stores a segment address not to be refreshed in the second operation mode; a determining circuit that compares the segment address stored in the segment address register and the refresh address, wherein in the second operation mode, memory cells belonging to a segment corresponding to the refresh address in which a match is detected by the determining circuit is not refreshed, and a refresh control circuit including a latch circuit set at a time of starting a refresh operation and reset at a time of completing the refresh operation and a gate circuit that prohibits setting of the latch circuit when a match is detected by the determining circuit.