Patent ID: 7038956

Claim:
A method for providing defect information from an integrated memory circuit having memory cells arranged on word lines and bit lines, comprising: writing test data to the memory cells of the memory chip; successively reading out the written test data from the memory cells of a word line group along one of the bit lines; comparing the read-out data and the test data to generate a plurality of first defect information items for the memory cells of the word line group along one of the bit lines, wherein each first defect information item indicates a defect for a particular memory cell if the test data and the read-out data are different for the particular memory cell; buffer-storing the plurality of first defect information items; generating a second defect information item, wherein the second defect information item indicates a defect when at least one of the first defect information items indicates a defect; and providing the second defect information item as an output of the integrated memory circuit, wherein the integrated memory circuit comprises a plurality of memory arrays each comprising a plurality of memory cells arranged on word lines and bit lines, and wherein respective second defect information items are generated for each memory array substantially simultaneously, and wherein corresponding memory cells in the plurality of memory arrays are read substantially simultaneously.