Patent ID: 7683373

Claim:
A thin film transistor, comprising: a substrate; a semiconductor layer formed on the substrate, the semiconductor layer comprising a first region and a second region separated by a grain boundary, and a density of a metal catalyst in the first region differs from a density of a metal catalyst in the second region; the semiconductor layer is formed of a polysilicon layer crystallized by a super grain silicon (SGS) crystallization technique; and a gate insulating layer, a gate electrode, an interlayer insulating layer, and source and drain electrodes formed on the semiconductor layer, wherein the grain boundary extends through the entire thickness of the semiconductor layer, and wherein the amount of the metal catalyst remaining on the first region is in a range of 10 9 to 10 13 atoms/cm 2 , the metal catalyst is formed by using a capping layer having a concentration gradient where the density of the metal catalyst varies depending on a distance from an interface between the amorphous silicon layer and the capping layer.