Patent ID: 8219880

Claim:
An apparatus comprising: a check/correct circuit coupled to receive a block of data and corresponding check bits, wherein the block of data and corresponding check bits are received as N transmissions of bits, wherein the bits received in a given transmission comprise M data bits and L check bits, and wherein the M data bits of the given transmission are divided into a plurality of non-overlapping windows of K bits, and wherein the check/correct circuit is configured to detect one or more errors in the plurality of non-overlapping windows responsive to the M data bits and the L check bits; and a control circuit coupled to the check/correct circuit, wherein the control circuit is configured to record which of the plurality of windows have had errors detected by the check/correct circuit, and wherein the control circuit is configured to detect that a given window of the plurality of windows has had errors detected in each of the N transmissions of data bits corresponding to the block, and wherein the control circuit is configured to signal a device failure for a device corresponding to the given window responsive to detecting that the given window has had errors detected in each of the N transmissions; wherein K, L, M, and N are each integers greater than one.