Patent ID: 8612809

Claim:
A memory device comprising: a package substrate having a first side; a hybrid memory buffer chip attached to the first side of the package substrate, the hybrid memory buffer including high speed input/output (HSIO) logic to support a HSIO interface with a processor and packet processing logic to support a packet processing protocol on the HSIO interface; and one or more memory strata vertically stacked on the hybrid memory buffer, each memory stratum including one or more memory tiles, each memory tile including a memory array and tile input/output (IO) logic; wherein the one or more memory strata are coupled with the package substrate, the one or more memory strata receiving power from the package substrate; wherein the memory device provides a first level of memory in a computing system having two or more levels of memory, a memory subsystem being coupled with the memory device, the memory subsystem to provide a second level of memory, wherein the second level of memory includes a plurality of memory blocks; and wherein the hybrid memory buffer chip includes a tag cache to store an address tag for at least a subset of the plurality of memory blocks, and wherein each address tag includes a disable bit to disable a memory block.