Patent ID: 8053832

Claim:
A one-transistor (1T) memory cell, comprising: a semiconductor layer on a substrate; a buried insulating layer underlying said semiconductor layer; a trench in said semiconductor layer; an electrically insulating offset spacer on a sidewall of said trench; a gate electrode in said trench; a gate insulating layer extending between said gate electrode and a bottom of said trench, said gate insulating layer having a thickness less than a thickness of said offset spacer; and source and drain regions in said semiconductor layer, on opposite sides of said trench; wherein a distance between a bottom of said trench and said buried insulating layer is less than about one-third a length of said gate electrode at the bottom of said trench; wherein a length of said gate electrode at a bottom of said trench is less than or equal to a minimum distance between the offset spacer on a source side of said trench and the offset spacer on a drain side of said trench; wherein said gate insulating layer has a higher dielectric constant relative to the offset spacer; and wherein a portion of the semiconductor layer extending between said gate insulating layer and said buried insulating layer is held in an electrically floating state that supports storage of data in the memory cell.