Patent ID: 7989277

Claim:
A process for fabricating an integrated group III nitride structure of transistors and Schottky diodes, the process comprising: providing semiconductor layers, comprising: providing a group III nitride compound first intermediate layer; providing a group III nitride compound second intermediate layer above the first intermediate layer; providing a group III nitride compound etch stop layer above the second intermediate layer; providing a group III nitride compound third intermediate layer above the etch stop layer; providing a group III nitride compound fourth intermediate layer above the third intermediate layer; fabricating at least one transistor in a first area of the semiconductor layers, comprising removing portions of the etch stop layer, the third intermediate layer, and the fourth intermediate layer in said first area; and fabricating at least one Schottky diode in a second area of the semiconductor layers, comprising removing portions of the fourth intermediate layer in said second area and providing an anode contact on a remaining portion of the fourth intermediate layer in said second area.