Patent ID: 7527994

Claim:
A method of making a channel passivated amorphous silicon thin-film transistor for an active matrix liquid crystal display, the method comprising the steps of: forming a transistor body on a substrate, the transistor body comprising a thin-film structure comprising a gate dielectric layer sandwiched between a gate electrode and an amorphous silicon layer; forming a thin-film dielectric layer on the amorphous silicon layer; exposing a first portion of the amorphous silicon layer by selectively removing a first portion of the thin-film dielectric layer to provide a source contact region; providing source contact material at a first location on the first portion of the amorphous silicon layer to form a source contact with the first portion of the amorphous silicon layer; exposing a second portion of the amorphous silicon layer by selectively removing a second portion of the thin-film dielectric layer to provide a drain contact region; providing drain contact material at a second location on the second portion of the amorphous silicon layer to form a drain contact with the second portion of the amorphous silicon layer, the drain contact material provided at a predetermined distance from the first location for defining a channel length of a channel region of the amorphous silicon layer wherein the source contact material and the drain contact material comprise a contact enhancement layer deposited on at least a portion of the first exposed portion of the amorphous silicon layer, at least a portion of the second exposed portion of the amorphous silicon layer, and at least a portion of a photoresist layer and the contact enhancement layer comprises a thin-film ytterbium layer; lifting off the contact enhancement layer that is deposited on the at least a portion of the photoresist layer by removing the photoresist layer; forming a source electrode that is connected to at least a portion of the contact enhancement layer on the at least a portion of the first exposed portion of the amorphous silicon layer; and forming a drain electrode that is connected to at least a portion of the contact enhancement layer on the at least a portion of the second exposed portion of the amorphous silicon layer.