Patent ID: 8601254

Claim:
A system comprising: a programmable input/output (I/O) pin configurable into multiple operational states; and a memory device to store configuration data that, when provided to the programmable I/O pin, causes the programmable I/O pin to reconfigure into one of the operational states, the programmable I/O pin including configuration reset circuitry configured to change a configuration of the programmable I/O pin between an external data I/O pin and an external reset pin in response to the configuration data, wherein the external data I/O pin is configured to pass I/O data between an external pad and internal circuitry and the external reset pin is configured generate a reset signal to reset the internal circuitry in response to an external input received on the external pad, wherein the system is further configured to: detect a first power level; use the configuration data in the memory device to configure drive states for multiple programmable I/O pins including the programmable I/O pin and additional programmable I/O pins in response to detecting the first power level; detect a second power level; and initiate a system boot process in response to detecting the second power level, wherein the system boot process executes firmware that reconfigures the drive states for at least some of the multiple programmable I/O pins.