Patent ID: 7338865

Claim:
A method for manufacturing a semiconductor device, comprising: forming a first gate layer, comprising silicon, over a dielectric layer located over a semiconductor substrate; doping a first region of said first gate layer differently from a second region of said first gate layer, the first region being adjacent to the second region, such that a first work function of the first region of the first gate layer is different from a second work function of the second region of the first gate layer; depositing a metal-containing layer over both the first and second regions of the first gate layer; forming a first metal silicide layer from the first gate layer and the metal-containing layer; placing a second gate layer, comprising silicon, over the metal silicide layer; and patterning said second gate layer and said first metal silicide layer to form at least two gate structures wherein a first of said at least two gate structures comprise metal silicide formed from said first region of said first gate layer and a second of said at least two gate structures comprises metal silicide formed from said second region of said first gate layer.