Patent ID: 8648416

Claim:
An integrated circuit, comprising: a substrate; a high voltage power transistor integrated with a blocking transistor, wherein said high voltage power transistor comprises: a first drain area including a first drain contact region; a first drift region electrically coupled to the first drain contact region, wherein the first drift region surrounds the first drain area except at said blocking transistor; a first channel/source area surrounding the first drift region; and a first body region in the first channel/source area, said first body region electrically connected to said substrate; and wherein the blocking transistor comprises: a second drain area including a second drain contact region electrically coupled to the first drain contact region; a second drift region electrically coupled to the second drain contact region, wherein a boundary between the second drain area and the second drift region is aligned with a boundary between the first drain area and the first drift region; a second channel/source area abutting the second drift region opposite the second drain area; and a second body region in the second channel/source region, wherein the second body region is electrically isolated from the substrate by a body isolation region.