Patent ID: 7688113

Claim:
A transceiver suitable for interfacing a logic device to a shared bus, the transceiver comprising: a transmit node suitable for receiving an input signal from the logic device; a shared bus node suitable for connecting to the shared bus; control logic coupled to the transmit node and operable to assert a current driver enable signal in response to detecting an assertion of the input signal; and a current driver operable to draw a time varying driver current from the shared bus node in response to detecting an assertion of the current driver enable signal, the driver current producing a wave shaped transition of the shared bus voltage, wherein the wave shaped transition approximates at least a portion of a sinusoidal signal; wherein the driver current includes a resistive component approximating a current attributable to a characteristic resistance of the shared bus and a capacitive component approximating a current attributable to a characteristic capacitance of the shared bus; and wherein the current driver includes a resistive block operable to draw the resistive component of the driver current and a capacitive block operable to draw the capacitive component of the driver current.