Patent ID: 8046401

Claim:
A multiplier, for multiplying an input data value by a selected constant value in CSD form, the selected constant value comprising a plurality of pairs of bits, the multiplier comprising: a plurality of multiplexers, wherein each of said multiplexers is controlled by a respective pair of bits of the selected constant value, and wherein each of said multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and being controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value; a plurality of variable shift blocks, each connected to receive an input from a respective one of said multiplexers, and each being adapted to shift its received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1; and combination circuitry, for receiving the outputs from the plurality of variable shift blocks, and for combining the outputs from the plurality of variable shift blocks and applying further bit shifts, to form an output value equal to the result of multiplying the input data value by the selected constant value.