Patent ID: 7555016

Claim:
A data communication system for communicating an input streamed data signal having an associated clock signal, the system comprising: at least two data handling nodes each having a physical layer interface device and a balanced line interface device, a transmitting one of the data handling nodes being arranged to transmit the input data signal to a receiving one of the data handling nodes; and a twisted-pair wired connection linking the data handling nodes, the wired connection comprising a cable providing at least two parallel data transmission paths between the data handling nodes; in which: at the transmitting node, the input data signal is supplied to the physical layer interface device for packeted transmission via one data transmission path of the wired connection to the receiving node; and the clock signal associated with the input data signal is supplied to the balanced line interface device for substantially continuous transmission via another of the data transmission paths to the receiving node; and at the receiving node, the received clock signal is supplied to the balanced line interface device for recovery and the packeted data signal is supplied to the physical layer interface device for conversion back to a streamed data signal.