Patent ID: 8759916

Claim:
A field effect transistor comprising: an insulator layer; a semiconductor body having a bottom surface adjacent to said insulator layer and a top surface opposite said bottom surface and comprising: silicon source/drain regions; and a silicon alloy channel region positioned laterally between said silicon source/drain regions, said silicon alloy channel region comprising edge portions adjacent to said silicon source/drain regions and a center portion positioned laterally between and immediately adjacent to said edge portions, said edge portions and said center portion each comprising a silicon alloy, said edge portions having a same type conductivity and same conductivity level as said silicon source/drain regions from said top surface to said bottom surface, and said edge portions and said center portion having any of different types of conductivity and different levels of conductivity; a gate structure on said top surface of said semiconductor body adjacent to and aligned above said center portion of said silicon alloy channel region; and gate sidewalls spacers positioned laterally immediately adjacent to said gate structure and further being on said top surface of said semiconductor body adjacent to and aligned above said edge portions of said silicon alloy channel region such that outer surfaces of said gate sidewall spacers are aligned with interfaces between said edge portions of said silicon alloy channel region and said silicon source/drain regions.