Patent ID: 6979625

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a plurality of openings in a dielectric layer having an upper surface, at least one of the openings having a width no greater than a first width and at least one of the openings having a width greater than the first width; depositing a layer of substantially pure copper (Cu) or a first Cu alloy completely filling the at least one opening having a width no greater than the first width and partially filling the at least one opening having a width greater than the first width; depositing a layer of a second Cu alloy, containing an element in a sufficient amount such that the electromigration resistance along grain boundaries of the second Cu alloy is greater than that of the first Cu alloy or is greater than that of substantially pure Cu, to completely fill the at least one opening having a width greater than the first width; planarizing the upper surface of the dielectric layer; forming a recess in the filled openings; and depositing a metal capping layer filling the recess.