Patent ID: 8125257

Claim:
A method for determining a number of steps of a fine delay line (FDL) that are substantially equivalent to a step of a coarse delay line (CDL), the method comprising steps of: providing a clock signal; delaying the clock signal by a first delay substantially equivalent to a first predetermined delay plus an adjustable number of steps of the FDL; delaying the clock signal by a second delay substantially equivalent to a second predetermined delay; adjusting the number of adjustable steps of the FDL so that the first delay is substantially equal to the second delay and providing a first number of adjustable steps of the FDL; delaying the clock signal by a third delay substantially equal to the second predetermined delay plus a step of the CDL; adjusting the number of adjustable steps of the FDL so that the first delay is substantially equal to the third delay and providing a second number of adjustable steps of the FDL; and subtracting the first number from the second number of adjustable steps of the FDL to provide the number of steps of the FDL that are substantially equivalent to the step of the CDL.