Patent ID: 8566775

Claim:
A device comprising: a communication interface to receive circuit test information, the circuit test information including information identifying components of a tested circuit and one or more component relationships of the tested circuit; and a processor to: traverse connectivity associated with the components; identify one or more segments of the tested circuit; define one or more logical columns for a graphical display of the circuit test information based on the one or more segments; optimize at least one of the one or more segments in a logical column, of the defined one or more logical columns, according to a rule set that includes a rule that advances a segment, of the one or more segments, from a default column to a preceding column; layout, based on the traversed connectivity, the one or more logical columns, and the optimized at least one of the one or more segments, the one or more segments; and send a graphic rendering of the tested circuit, via the communications interface, to another device.