Patent ID: 7471345

Claim:
A flat display device comprising: a plurality of pixels arranged in a two-dimensional form in a display area, a plurality of scanning lines arranged along respective rows of groups of the pixels, a plurality of signal lines arranged along respective columns of groups of the pixels, a gate drive circuit which sequentially outputs gate signals to the plurality of scanning lines in each scanning period unit, a source drive circuit which outputs image signals to the plurality of signal lines in each scanning period unit, a plurality of pixel switch circuits each of which is configured to respond to a gate signal from a corresponding one of the scanning lines to supply an image signal from a corresponding one the signal lines to a corresponding one of the pixels, an output inhibition circuit which is provided in the gate drive circuit to inhibit the gate signal from being output, vertical synchronization lock means which freely operates in a phase-locked fashion with an external vertical synchronization signal input from an exterior to generate an internal vertical synchronization signal, a window signal generating circuit which generates a window signal corresponding to the position of the external vertical synchronization signal by use of the internal vertical synchronization signal, a detecting circuit which outputs a detection signal when the external vertical synchronization signal is present in a period of the window signal, and a determination circuit which outputs a gate output inhibition signal used to control the output inhibition circuit when a preset condition that a plurality of detection signals are present in a preset period is not satisfied.