Patent ID: 6946376

Claim:
A method for fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming a gate structure, including: forming a gate dielectric on a surface of the semiconductor substrate; forming a conductive gate aligned on the gate dielectric; forming a silicide layer aligned on the conductive gate; and forming an insulative cap aligned on the silicide layer; forming a drain region within the semiconductor substrate; forming a source region within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate dielectric is over the channel region; forming a first insulative spacer on a first sidewall of the gate structure; forming a second insulative spacer on a second sidewall of the gate structure; forming a first conductive stud in contact with the first insulative spacer, and in electrical contact with the drain region, wherein the first conductive stud includes a first conductive material; and forming, a second conductive stud in contact with the second insulative spacer, and in electrical contact with the source region, wherein the second conductive stud includes a second conductive material, and wherein a surface of the first conductive stud, a surface of the second conductive stud, and a surface of the gate structure are coplanar; forming a conductive contact to the conductive gate, wherein the conductive contact passes through the insulative cap, and wherein the conductive contact is in direct mechanical and electrical contact with the silicide layer; and forming an interlevel layer above the insulative cap and in direct mechanical contact with the insulative cap, wherein the interlevel layer comprises an interlevel dielectric, and wherein the conductive contact passes through the interlevel layer, wherein the interlevel layer comprises a first conductive post conductively coupled to the first conductive stud and a second conductive post conductively coupled to the second conductive stud, wherein the entire first conductive post is displaced backwards by a distance D 1 relative to a front cross-sectional plane that perpendicularly cuts through the first and second conductive studs such that D 1 >0 and D 1 is a minimum distance between the first conductive post and the front cross-sectional plane, and wherein the entire second conductive post is displaced backwards by a distance D 2 relative to the front cross-sectional plane such that D 2 >0 and D 2 is a minimum distance between the second conductive post and the front cross-sectional plane.