Patent ID: 7235869

Claim:
An integrated circuit package, comprising: a substrate having an upper surface, a lower surface and a long slot penetrating from the upper surface to the lower surface, wherein the lower surface is formed with a wiring regions arranged at one side of the long slot, the wiring regions is formed with a plurality of connection points, and a length of the wiring regions is smaller than a length of the long slot of the substrate; a resistant layer, which is coated on and in contact with the lower surface of the substrate, and is located between the long slot and the wiring region, wherein the resistant layer separates the long slot from the wiring region, and a length of the resistant layer is substantially equal to the length of the wiring region; a glue layer coated on the upper surface of the substrate and located at a periphery of the long slot; an integrated circuit having a first surface formed with a plurality of bonding pads and a second surface, the first surface being adhered to the glue layer, the bonding pads being exposed from the long slot of the substrate; a plurality of wires, each of which is arranged within the long slot of the substrate and electrically connects the bonding pad of the integrated circuit to the connection point of the substrate; and a first compound layer filled within the long slot of the substrate to protect the wires.