Patent ID: 7788562

Claim:
An apparatus for testing a Device Under Test (DUT), comprising: one or more Signature Registers (SRs), each SR for receiving a serial output from the DUT and generating an output signature for comparison to one or more possible valid output signatures for that serial output; one or more de-serializers coupled to the one or more SRs for converting one or more of the serial outputs from the DUT into parallel data; and control logic coupled to the one or more SRs for generating a control mask signal to control the masking of indeterminate data by the SRs, wherein the one or more SRs are controllable to mask, on the fly, indeterminate data received on the serial output and reduce the number of possible valid output signatures for its corresponding serial output, and wherein the control logic generates the control signal mask according to a repeating mask/unmask pattern after detecting an alignment character.