Patent ID: 7231079

Claim:
A system for inspecting a defect of an electronic circuit pattern formed on a semiconductor wafer, comprising: an inspection area setting unit which divides an area to be inspected into at least two partial inspection areas on the semiconductor wafer, each of which has each of different inspection conditions; an inspection condition setting unit which sets each inspection condition for each partial inspection area that is set by the inspection area setting unit; an image acquiring system which acquires an image signal from the each partial inspection area on the semiconductor wafer; and an inspection executing unit which executes an inspection to detect the defect by image-processing the image signal acquired by the image detection acquiring system under the each inspection condition which have been set by the inspection condition setting unit, for each partial inspection area set by the inspection area setting unit, wherein the inspection area setting unit divides the area to be inspected into at least the two partial inspection areas including a cell area and a non-cell area according to layout data, and the inspection condition setting unit sets conditions for the image acquiring system not to detect a reference image for each partial image in the cell area and to detect a reference image for each partial image in the non-cell area.