Patent ID: 8208596

Claim:
A system for utilizing a dual-mode phase-locked loop to support a data transmission procedure, comprising: a voltage controlled oscillator that generates a receiver clock signal in response to VCO input signals; a binary phase detector that generates a BPD output signal during a BPD mode by comparing input data and said receiver clock signal; a phase frequency detector that generates a PFD output signal during a PFD mode by comparing a reference signal and a divided receiver clock signal; and a loop filter that performs a BPD transfer function to generate a first one of said VCO input signals from said BPD output signal during said BPD mode, said loop filter performing a PFD transfer function to generate a second one of said VCO input signals from said PFD output signal during said PFD mode, said BPD mode summing a proportional path and an integrated path through said loop filter to generate said first one of said VCO input signals, said integrated path passing through a BPD charge pump and a passive component network, said passive component network including a primary capacitor, a damping resistor, and a secondary capacitor, said BPD output signal controlling said BPD charge pump which provides a BPD charge current to a first end of said primary capacitor, a second end of said primary capacitor being coupled to a ground connection, said first end of said primary capacitor also being connected to a first end of said damping resistor, a second end of said damping resistor being connected to a first end of said secondary capacitor, a second end of said secondary capacitor being coupled to said ground connection, transfer function characteristics F(s) of said loop filter during said BPD mode being expressed by a following equation: F BPDmode ⁡ ( s ) = V VCO , IN V BPD , OUT = K P + I CP , BPD ⁢ 1 ( C 1 + C 2 ) ⁢ s · 1 1 + R 1 ⁢ C 1 ⁢ C 2 C 1 + C 2 ⁢ s .