Patent ID: 7787310

Claim:
A system for writing data onto a memory device, the system comprising: an internal data bus; a plurality of data capture latches coupled to receive write data relative to a write strobe signal, the plurality of latches operable to separate the data digits of the write data into rising edge data captured relative to the rising edge of the write strobe signal and falling edge data captured relative to the falling edge of the write strobe signal; a plurality of demultiplexer circuits each coupled to the internal data bus and to a respective data latch of the plurality of data latches, each of the plurality of demultiplexer circuit adapted to receive the write strobe signal and operable to sequentially latch each of the data digits from the plurality of data capture latches relative to the write strobe signal, at least one of the plurality of demultiplexer circuits operable to generate a latch enable signal corresponding to each data digit upon being latched; and a write control circuit coupled to the plurality of demultiplexer circuits, the write control circuit adapted to receive the write strobe signal and a write latency signal, the write control circuit further adapted to receive the latch enable signals from the at least one of the plurality of demultiplexer circuit, the write control circuit operable to arbitrate between the latch enable signals and the write latency signal to synchronize driving the data digits of the write data onto the internal data bus after the last data digit of the write data has been latched.