Patent ID: 8736732

Claim:
A solid-state image pickup device comprising: an image unit, in which a plurality of pixels each including a photoelectric conversion element for converting an optical signal into an electrical signal are arranged in a matrix, for sequentially scanning pixels in each row and outputting pixel signals of a selected row through a plurality of vertical readout lines arranged in respective columns; a plurality of holding units configured to hold pixel signals outputted through the vertical readout lines; a plurality of conversion units, provided corresponding to the respective holding unit, each configured to convert a pixel signal held by corresponding holding unit from an analog signal to a digital value; a first generation unit configured to generate first part bits of the digital value in accordance with the pixel signal held by the holding unit; and a second generation unit configured to generate second part bits of the digital value in accordance with the pixel signal held by the holding unit and the first part bits generated by the first generation unit, wherein each of the conversion units includes: a comparison unit configured to determine a latch timing of the first part bits and the second part bits in accordance with the pixel signal; an addition unit configured to add first part bits generated by the first generation unit and the second part bits generated by the second generation unit and outputting the digital value; a plurality of capacitive elements which are capacitively coupled to a node at which the pixel signal is held by the holding unit; a control unit configured to change a potential of the node in a stepwise manner by sequentially switching voltages of counter electrodes of the plurality of the capacitive elements; and a determination unit configured to determine the latch timing of the first part bits of the digital value in accordance with a comparison result by the comparison unit, the comparison unit compares the potential of the node with a predetermined potential and the second generation unit includes: a capacitive element which is capacitively coupled to the node at which the pixel signal is held by the holding unit; a control unit configured to change a voltage of a counter electrode of the capacitive element in a slope manner; and a counter value holding unit configured to determine the latch timing of the second part bits of the digital value in accordance with the comparison result by the comparison unit.