Patent ID: 8312070

Claim:
A speed-level calculator for dynamic voltage scaling, applicable to a processor with a plurality of speed levels, said speed-level calculator comprising: a deadline counter that computes a residual time D of deadline for accomplishing a series of related tasks; a shifter that shifts said residual time D to the right for e-m bits to obtain a real number D′=(2 −e *D), rounded to m bits after the decimal point of D′, where e and m are both natural numbers; and a fixed-point multiplier, according to a pre-computed ratio parameter α i of each task T i , for multiplying D′ with α i , and simplifying the multiplication result as a k-bit integer to generate a corresponding discrete speed-level with an error within an order of 2 −p for control of voltage and frequency for said processor, where k and p are natural numbers; wherein p is a defined error tolerance parameter with e being pre-computed, k is a number of bits required for representing the plurality of speed levels, and n is a nature number representing a number of bits in a fractional part of said α i with n=k+p+1, and m=p+2.