Patent ID: 6989690

Claim:
A method of implementing a routing matrix for a programmable logic device (PLD), the method comprising: generating a seed matrix comprising N rows and N columns of numerical signal values, wherein N is an integer greater than one, each signal value appearing at most once in each column and at most once in each row of the seed matrix; generating a distribution matrix comprising S rows and T columns of sub-matrices, wherein S and T are integers greater than one and each sub-matrix corresponds to a column of the seed matrix, each column of the distribution matrix differing from each other column of the distribution matrix in at least (S−1) of the sub-matrices in the column; generating a corresponding adjustment value for each column of the distribution matrix, each adjustment value being an integral multiple of N; generating a routing matrix pattern by adding the corresponding adjustment value to each signal value in each sub-matrix in each column of the distribution matrix; and implementing the routing matrix for the PLD by applying the routing matrix pattern to provide programmable interconnections between a plurality of input terminals and a plurality of output terminals of the routing matrix, each signal value in the routing matrix pattern corresponding to one of the input terminals, each row of signal values in the routing matrix pattern corresponding to a set of the input terminals programmably coupled to a different one of the output terminals.