Patent ID: 7940873

Claim:
A data reproduction circuit for receiving data and reproducing data and a clock, comprising: an over-sampling determination circuit for sampling the received data by a first reproduced clock with a frequency higher than a data rate of the received data, so as to convert the received data into digital signals; a data selection circuit having a first circuit for reproducing data from the digital signals based on the first reproduced clock and for outputting the data, and having a phase/frequency error detection circuit for detecting a phase error and a frequency error from a timing difference between the first reproduced clock and the digital signals so as to generate and output an adjustment signal based on the phase error and the frequency error; and a clock generation circuit having a phase/frequency adjustment circuit for adjusting a phase and a frequency of the first reproduced clock using the adjustment signal, wherein the clock generation circuit provides the first reproduced clock having an adjusted phase and adjusted frequency to the over-sampling determination circuit and the data selection circuit, wherein the phase/frequency error detection circuit detects a data change timing of the over-sampled data based on the first reproduced clock, generates a phase signal from the data change timing, converts the phase signal into a pointer signal that indicates movement of the phase signal, and outputs the pointer signal as the adjustment signal in order to adjust a phase of the first reproduced clock.