Patent ID: 8127058

Claim:
An apparatus including a memory in a processing system, the apparatus comprising: a random access memory, wherein the random access memory implements a plurality of first in first out (FIFOs); a first interface, coupled to the random access memory, between the random access memory and a plurality of storage devices, wherein the first interface operates in a first in first out (FIFO) manner to write data from one of the plurality of storage devices in the FIFO manner to a FIFO of the plurality of FIFOs, and read data from the FIFO to one of the plurality of storage devices in the FIFO manner; and a second interface, coupled to the random access memory, between the random access memory and a processor, wherein the second interface operates in a random access manner to read data in the random access manner from the FIFO and provide the data to the processor, and write data from the processor in the random access manner to the FIFO.