Patent ID: 8086934

Claim:
A decoding apparatus for LDPC (Low Density Parity Check) codes definable by a parity check matrix including a combination of at least one component matrix which can be a P×P (where P is a positive integer) unit matrix, a semi unit matrix obtained by setting one or more of matrix elements each having a value of 1 in said unit matrix to 0, a shift matrix obtained by carrying out a cyclic shift operation on said unit matrix or said semi unit matrix, a sum matrix obtained by computing the sum of a plurality of said unit matrixes, said semi unit matrixes or said shift matrixes, or a P×P 0 matrix, said decoding apparatus comprising: a first computation section configured to carry out a check-node computation process in order to decode said LDPC codes; and a second computation section configured to carry out a variable-node computation process in order to decode said LDPC codes; wherein only said first computation section carries out N (where N is a positive integer smaller than said P) said check-node computation processes at the same time, only said second computation section carries out N said variable-node computation processes at the same time, or said first computation section carries out said N check-node computation processes at the same time whereas said second computation section carries out said N variable-node computation processes at the same time.