Patent ID: 7113417

Claim:
A memory circuit integrated on a semiconductor chip, comprising: at least one memory bank having a plurality of memory cells and a plurality of memory bank connections for accessing the memory cells for reading and writing data; a plurality of connection pads connectable to external supply lines for transferring incoming and outgoing signals; and an interface system for transferring signals between the plurality of connection pads and a plurality of internal signal lines connected to the plurality of memory bank connections, wherein the interface system comprises a plurality of interface circuits, each interface circuit corresponding to a different one of a plurality of modes of operation of the memory circuit, wherein each interface circuit is disposed in a plurality of separate sections, and wherein at least one of the plurality of interface circuits associated with a selected mode of operation of the plurality of modes of operation for the memory circuit is operatively connected between the plurality of internal signal lines and the plurality of connection pads by a metallization structure in a topmost metallization plane of the semiconductor chip.