Patent ID: 7606108

Claim:
A multiport memory comprising: at least one array of bit cells having a plurality of bit lines each coupled to a column of bit cells within said array and a plurality of row lines each coupled to a row of bit cells within said array; a plurality of data access ports coupled to said at least one array of bit cells, each data access port having at least one associated bit line providing data access to a respective column of bits cells within said array such that a given bit cell is enabled for access via said at least one associated bit line when a row line coupled to said given bit cell supplies an access enable signal to a row of bit cells including said given bit cell; control circuitry responsive to signal values indicative of concurrent data accesses via respective associated bit lines of a plurality of data access ports to a common row of bit cells when at least one of said data accesses is a write access via a given data access port to generate an override signal; and override circuitry responsive to said override signal to drive one or more bit values being written to respective bit cells via respective associated bit lines of said given data access port on to associated bit lines of other of said plurality of data access ports that are concurrently enabled for access to said respective bit cells.