Patent ID: 8019976

Claim:
A method for performing parallel operations in a computer system when one or more memory hazards may be present, comprising: at runtime, receiving instructions for detecting one or more critical memory hazards between memory addresses if memory operations are performed in parallel on multiple addresses corresponding to at least a partial vector of addresses, wherein the instructions are inserted in program code prior to runtime, wherein the one or more critical memory hazards include memory hazards that lead to different results when the memory addresses are processed in parallel than when the memory addresses are processed sequentially, and wherein the one or more critical memory hazards are data-dependent and therefore cannot be detected until after the memory addresses have been resolved at runtime wherein while executing the program code, executing the instructions for detecting the one or more critical memory hazards causes a processor to detect the one or more critical memory hazards; and receiving instructions for generating predicate values which specify the elements for which operations may safely be performed in parallel for a first set of consecutive elements in at least the partial vector, wherein the operations that may safely be performed in parallel include the memory operations.