Patent ID: 8489823

Claim:
A microprocessor configured to access an external memory, the microprocessor comprising: a first-level cache; a second-level cache; and a bus interface unit (BIU), configured to interface the first-level and second-level caches to a bus used to access the external memory, wherein the BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache; wherein the second-level cache is configured to: generate a first request to the BIU to fetch a cache line from the external memory; detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line; request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request; wherein the request to refrain from performing the transaction includes a request to terminate the transaction on the bus if the BIU has already been granted ownership of the bus and it is not too late for the BIU to terminate the transaction.