Patent ID: 7532146

Claim:
A multi-bit pipeline analog-to-digital converter (ADC) having a merged capacitor switching structure, comprising a multiplying digital-to-analog converter (MDAC) including: first and second differential capacitors for storing an analog input voltage and formed by merging a number of sampling capacitors; an amplifier for amplifying a residual voltage passed through the first and second differential capacitors; an N-bit flash ADC connected to an input terminal; and a decoding circuit for controlling the voltage applied to the first and second differential capacitors through first to third switches according to a digital code output from the N-bit flash ADC, wherein when bits of the digital code do not have the same value, the decoding circuit turns off the first and second switches connected to positive and negative reference voltages ±V REF and turns on the third switch connected between a bottom plate of the first differential capacitor and a bottom plate of the second differential capacitor and controls the total amount of electric charge stored in the first and second differential capacitors to be 0.