Patent ID: 7889573

Claim:
A storage device comprising: latch control terminals to which latch control signals for performing latch control on a series of signals are input; a plurality of signal terminals to which the series of signals is input; a plurality of latch circuits which are provided so as to correspond to the plurality of signal terminals, the plurality of latch circuits being located at such positions that distances from the plurality of signal terminals to their associated latch circuits do not exceed a specified range and distances from the latch control terminals to their associated latch circuits do not exceed a specified range; and a latch control circuit connected to the latch control terminals to which the latch control signals are input, the latch control circuit outputting a latch signal to the latch circuit; wherein the specified ranges from the signal terminals to the latch circuit are not longer than a distance with which delays of transmission by the signal lines from the signal terminals to the latch circuit become the maximum allowable transmission delay; and the specified ranges from the latch control terminals to the latch circuit are not longer than a distance with which delay of transmission after a latch control signal is input to each latch control terminal until it is transmitted as a latch signal to the latch circuit through the latch control circuit becomes the maximum allowable transmission delay.