Patent ID: 7589425

Claim:
A method of manufacturing a semiconductor device having damascene structures with air gaps, the method comprising: providing a substantially planar layer having a first metal layer; depositing a via level dielectric layer on the substantially planar layer; patterning the via level dielectric layer; at least partly etching the via level dielectric layer; depositing a disposable layer on the at least partly etched portion and the remaining non-etched portion of the via level dielectric layer; patterning the disposable layer; depositing a second metal layer on the via level dielectric layer and between the patterned portions of the disposable layer; planarizing the second metal layer; depositing a permeable dielectric layer on the planarized second metal layer and the patterned portions of the disposable layer; and removing the patterned portions of the disposable layer through the permeable dielectric layer so as to form air gaps.