Patent ID: 8907705

Claim:
A circuit, comprising: a first current generator coupled to a first reference voltage node and configured to generate a first output current at a first intermediate node; a first transistor having a source-drain path coupled to receive the first output current at the first intermediate node and configured to apply the first output current to a second intermediate node in response to a periodic signal; a second transistor having a source-drain path coupled to receive the first output current at the first intermediate node and configured to apply the first output current to an output node in response to a complement of the periodic signal; a first capacitance coupled between the second intermediate node and a second reference voltage node and configured to generate a ramping signal at the second intermediate node in response to the first output current applied by the first transistor; a buffer circuit having an input coupled to receive the ramping signal from the second intermediate node and having an output coupled to generate an output ramping signal at the output node; a third transistor having a source-drain path coupled between the second intermediate node the second reference voltage node; and a comparator circuit having a first input coupled to the output node, a second input configured to receive a second threshold and an output configured to generate a signal for application to a gate of the third transistor.