Patent ID: 7936125

Claim:
A flat panel display, comprising: an insulating substrate; a semiconductor layer having source and drain regions of a thin film transistor formed on the insulating substrate; a gate electrode formed above the semiconductor layer; a first insulating layer formed between the semiconductor layer and the gate electrode; a second insulating layer having contact holes for exposing a portion of the source region and a portion of the drain region; source and drain electrodes connected respectively to the source and drain regions through the contact holes; a lower electrode formed on the second insulating layer and connected to one of the source and drain electrodes; a third insulating layer for passivation and having an opening for exposing a portion of the lower electrode; an organic emission layer formed on the lower electrode and the third insulating layer; and an upper electrode formed on the organic emission layer, wherein the contact holes and the lower electrode are tapered with taper angles of 60° or less with respect to a surface of the insulating substrate.