Patent ID: 7662724

Claim:
A method for manufacturing a capacitor, comprising the steps of: forming a lower electrode above a base substrate; forming a dielectric film composed of one of ferroelectric material and piezoelectric material above the lower electrode; forming an upper electrode above the dielectric film; forming a first silicon oxide film that covers at least the dielectric film and the upper electrode; forming a hydrogen barrier film that covers the first silicon oxide film; forming a contact hole penetrating the hydrogen barrier film and the first silicon oxide film; and forming a wiring layer that embeds the contact hole, wherein an etching selection ratio of the first silicon oxide film to the upper electrode is greater than an etching selection ratio of the hydrogen barrier film to the upper electrode, wherein the first silicon oxide film is formed by a dual-frequency excitation plasma chemical vapor deposition (CVD) method with trimethoxysilane to suppress generation of hydrogen during formation of the first silicon oxide film and prevent deterioration of a hysteresis characteristic of the dielectric film.