Patent ID: 7378312

Claim:
A method of forming a recess gate transistor on a substrate having a device isolation film that defines an active region and a non-active region, the method comprising: separating a first active region from a second active region in a portion of the active region by using a recess; isotropically etching within the recess in order to widen side faces of the recess and to round-process a bottom corner of the recess; placing a gate insulation layer within the recess; forming a gate electrode, which is extended from within the recess in which the gate insulation layer was placed, and which has a flute with a predetermined horizontal thickness measured from a portion of the gate insulation layer in contact with the first active region and that has a predetermined depth from an upper surface of the first active region; forming a first gate spacer on a sidewall of the gate electrode in contact with the gate insulation layer on the first active region, so as to fill the flute; forming a second gate spacer on a sidewall of the gate electrode in contact with the gate insulation layer on the second active region; and forming a source region and a drain region formed mutually oppositely on the first and second active regions with the gate electrode therebetween.