Patent ID: 7369132

Claim:
A graphics processing apparatus, comprising: an output pipeline including a plurality of memory clients; a memory controller connected to said output pipeline, said memory controller being configured to retrieve data requested by respective ones of said plurality of memory clients from a memory; and a buffering module connected between said memory controller and said output pipeline, said buffering module including: a buffer including a buffering space shared by said plurality of memory clients; and a buffer controller connected to said buffer, said buffer controller being configured to dynamically assign portions of said buffering space to respective ones of said plurality of memory clients, said buffer controller being configured to coordinate storage of said data in said assigned portions, said buffer controller being configured to coordinate delivery of said data from said assigned portions to respective ones of said plurality of memory clients, wherein said data includes a first set of data items requested by a first memory client of said plurality of memory clients and a second set of data items requested by a second memory client of said plurality of memory clients, said buffer controller is configured to dynamically assign a first set of memory locations within said buffering space to store said first set of data items, and said buffer controller is configured to dynamically assign a second set of memory locations within said buffering space to store said second set of data items.