Patent ID: 8633722

Claim:
A circuit for testing a plurality of delay circuits in an integrated circuit (IC), comprising: a test signal generator circuit configured to generate a plurality of output signals 1 through N, and in response to an input signal, toggle the plurality of output signals in sequential order from 1 to N with a delay period between the toggle of each output signal X and the toggle output signal X+1 of the N output signals, each output signal being coupled to an input of a respective one of the plurality of delay circuits; and a phase detector circuit coupled to outputs of the plurality of delay circuits, the phase detector circuit, for an output signal of each delay circuit X of delay circuits 2 through N−1, configured to: output a first signal indicating delay circuit X is operational in response to the output signals of delay circuits X−1, X, and X+1 being toggled in the order X-1 followed by X followed by X+1; and output a second signal indicating delay circuit X is not operational in response to the output signals of delay circuits X−1, X, and X+1 being toggled in an order other than X−1 followed by X followed by X+1; wherein for each delay circuit X of the plurality of delay circuits, the phase detector includes a flip flop X having a clock input coupled to receive the output signal of delay circuit X, a clock enable input coupled to receive the output signal of delay circuit X−1, a synchronous reset input coupled to receive the output signal of delay circuit X+1, a data input, and a data output that provides a respective output signal of the phase detector circuit.