Patent ID: 7016246

Claim:
A semiconductor device formed on a semiconductor substrate comprising: a memory; and a terminal fed with a clock signal from outside of said semiconductor device; wherein said memory includes: a plurality of DRAM memory cells each having first, second, and third transistors and formed in a memory array; a plurality of first word lines coupled to the gates of said first transistors; a plurality of second word lines coupled to the gates of said second transistors; a plurality of first bit lines coupled to the source/drain paths of said first transistors; a plurality of second bit lines coupled to the source/drain paths of said second transistors; a means for deferring conflicts of refreshing operation and access to said memory; wherein each gate of said third transistor is coupled to the source/drain path of said first transistor, and each source/drain path of said third transistor is coupled to the source/drain path of said second transistor, and means for eliminating rewrite operations to DRAM memory cells which are not selected but which are coupled to a selected first word line, wherein read operation and write operation are pipelined where an operational cycle is related to row access, wherein said memory operates by a first clock cycle having a higher frequency than a second clock cycle of said access to said memory.