Patent ID: 8218052

Claim:
An imaging system adapted for outputting a video data signal having a video pixel clock rate and a video frame rate, comprising: a timing generator simultaneously providing an imager pixel clock signal and a video pixel clock signal, the imager pixel clock signal having an imager pixel clock rate and an imager frame rate, and the video pixel clock signal having the video pixel clock rate that is greater than the imager pixel clock rate and the video frame rate that is equal to the imager frame rate; a standard imager having a nominal clock rate that is lower than the video pixel clock rate of the video data signal, the standard imager having an imager clock input receiving the imager pixel clock signal and a data output which outputs imager data comprising frames of sequential lines of active image data at the imager pixel clock rate; and a pixel clock rate converter comprised of a memory buffer coupled to the data output of the standard imager, and a memory control circuit for controlling the writing and reading of image data to and from the memory buffer which is coupled to the timing generator and receiving the imager pixel clock signal and the video pixel clock signal, the pixel clock rate converter receiving the imager data from the standard imager synchronously with the imager pixel clock signal and at a rate equal to the imager pixel clock rate, and outputting buffered image data at a rate equal to the video pixel clock rate that is greater than the imager pixel clock rate.