Patent ID: 8842459

Claim:
A semiconductor device including a memory cell, the memory cell comprising: a transistor, a gate of the transistor being electrically connected to a word line, and one of a source and a drain of the transistor being electrically connected to a bit line; a capacitor, one terminal of the capacitor being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor being electrically connected to a wiring; a resistor, one terminal of the resistor being electrically connected to the other of the source and the drain of the transistor, and the other terminal of the resistor being electrically connected to the wiring; and a buffer circuit electrically connected to the other of the source and the drain of the transistor, wherein the one terminal of the resistor is between the one terminal of the capacitor and an input of the buffer circuit, and wherein an amount of electric charge which is discharged from the capacitor and flows to the resistor is larger than an amount of electric charge which is discharged from the capacitor and flows to the transistor.