Patent ID: 7973317

Claim:
An array substrate for an LCD, comprising: a substrate having a transistor region and a storage capacitor region; a thin film transistor in the transistor region, comprising: a semiconductor layer disposed on the substrate; a gate dielectric layer disposed on the semiconductor layer; a gate electrode disposed on the gate dielectric layer; and a source/drain electrode electrically connected to the semiconductor layer; a storage capacitor in the storage capacitor region, comprising: a transparent lower electrode disposed on the substrate; a capacitor dielectric layer disposed on the transparent lower electrode; and an upper electrode disposed on the capacitor dielectric layer and comprising a transparent electrode portion and a metal electrode portion; a planarization layer covering the thin film transistor and the storage capacitor; an interlayer dielectric layer between the planarization layer and the gate electrode and between the planarization layer and the upper electrode, wherein the interlayer dielectric layer above the upper electrode has an opening therein, such that the planarization layer contacts the upper electrode through the opening; and a pixel electrode disposed on the planarization layer and electrically connected to the source/drain electrode through the planarization layer; wherein the semiconductor layer and the transparent lower electrode are formed by the same polysilicon layer and the gate dielectric layer and the capacitor dielectric layer are formed by the same dielectric layer.