Patent ID: 8370714

Claim:
A computer-implemented method of reading and correcting data within a memory device, the method comprising: reading each data bit of a data word where each data bit of the data word is associated with a corresponding first reference cell and as second reference cell, the first reference cell is continuously associated with a 0 memory state and the second reference cell is continuously associated with a 1 memory state, by comparing each bit of the data word to the corresponding first reference cell the corresponding second reference cell; performing error detection on the read data bits; correcting a read data bit when an error is detected using error correction code (ECC); writing each corresponding first reference cell associated with each data bit of the data word to a 0 memory state responsive to correcting the read data bit when the error is detected using ECC; and writing each corresponding second reference cell associated with each data bit of the data word to a 1 memory state responsive to correcting the read data bit when the error is detected using ECC.