Patent ID: 7262476

Claim:
A metal-oxide semiconductor (MOS) device, comprising: a semiconductor layer of a first conductivity type; first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another; a drift region of the second conductivity type formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, the drift region having an impurity doping concentration greater than about 2.0e12 atoms per square centimeter; an insulating layer formed on at least a portion of the upper surface of the semiconductor layer; a gate formed on the insulating layer at least partially between the first and second source/drain regions; and a buried layer of the first conductivity type formed in the semiconductor layer in close relative proximity to and beneath at least a portion of the drift region, at least one of (i) a substantially vertical distance between the buried layer and the drift region and (ii) one or more physical dimensions of the buried layer being configured so as to optimize a power density of the device relative to at least one of an on-resistance and a maximum drain current of the device, the buried layer having an impurity doping concentration greater than about 5e16 atoms per square centimeter.