Patent ID: 8603912

Claim:
A method for the production of an integrated power semiconductor component comprising: providing a semiconductor substrate with a surface region; providing at least one semiconductor circuit region in the semiconductor substrate; providing contact location layers for a contact-connection of the at least one semiconductor circuit region; providing a topmost metallization layer for a contact-connection of the semiconductor circuit region in the surface region of the semiconductor substrate via the contact location layers electrically connected by contacts to the topmost metallization layer; providing an embedding material layer for embedding the semiconductor substrate with the contact location layers and the topmost metallization layer; wherein: below the embedding material layer, a protection and sealing material region is provided laterally beyond the contact location layers and the contacts; the topmost metallization layer is formed in a manner extended laterally also beyond the contact location layer and the contacts in such a way that the topmost metallization layer laterally almost completely extends over and covers the directly underlying structures of the integrated power semiconductor component, the protection and sealing material region is formed directly by the topmost metallization layer whilst avoiding customary and additional electrically insulating protection and sealing stack layers, the embedding material layer and the topmost metallization layer are formed above the surface region of the semiconductor substrate, the topmost metallization layer is formed adjacent to the embedding material layer, and a metallization of the topmost metallization layer is formed by one of a group consisting of sputtering, vapour deposition, electroplating, autogenous electroplating or CVD.