Patent ID: 8362536

Claim:
A semiconductor memory device, comprising: a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction; a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction; a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween; a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions; and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.