Patent ID: 8407454

Claim:
A multi-threaded processor, comprising: a plurality of state machines for tracking a current state of each thread of a plurality of threads, each state machine having states comprising hazard, running, and ready; a respective plurality of hazard counters assigned to each thread currently in the running state; an instruction decoder operable to decode a sequence of instructions from. a thread of the plurality of threads that is in the running state, identify each long latency instruction in the sequence of instructions and responsively increment a selected hazard counter of the plurality of hazard counters assigned to that thread, associate the selected hazard counter with the long latency instruction, and dispatch the long latency instruction for execution, responsive to completion of any previously dispatched long latency instruction, decrementing the hazard counter associated with that long latency instruction, identify a hazard instruction in the sequence of instructions and determine if a value of a hazard counter of the plurality of hazard counters assigned to that thread indicates one or more outstanding tong latency instructions that pose a hazard for the hazard instruction, responsively changing state of the thread from running to hazard, and selecting a replacement thread from a pool of threads having a ready state and changing the replacement thread state to running; and a pipelined execution unit for executing operations according to decoded instruction data from the instruction decoder.