Patent ID: 7675333

Claim:
A Delay Locked Loop (DLL) with equally spaced phases over a wide frequency range, the DLL comprising: a delay line for receiving a reference clock signal and outputting a final delay clock signal in response to the reference clock signal, wherein the delay line includes a plurality of delay cells connected in series, the plurality of delay cells generating a plurality of delay clock signals having equally spaced phases; a control module coupled to the delay line, for generating a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal, the control module comprising: a calibration module for generating a co-prime number with respect to the plurality of delay clock signals, wherein the co-prime number is generated based on counting the number of pulses of the reference clock signal, the calibration module comprising: a counter for counting the number of pulses of the reference clock signal; a decoder coupled to the counter, for generating the co-prime number by decoding a count of the number of pulses of the reference clock signal; a masking module for masking edges of the reference clock signal and the final delay clock signal; and a phase control module coupled to the calibration module, for generating the phase control signal based on a value of the co-prime number.