Patent ID: 7260594

Claim:
An arithmetic logic unit over a finite field GF (2 m ), comprising: a control unit for generating control signals required for an RS-block unit, an SR-block unit and a UV-block unit while outputting an externally-applied signal (mult/div) to be used as an input to select multiplication and division operations without change; the RS-block unit for generating an output value (r 0 ) when receiving the control signals from the control logic unit, and transmitting the output value (r 0 ) to the control logic unit, and calculating R and S values of multiplication and division algorithms; the SR-block unit for performing multiplication and division operations when receiving a control signal output from the control logic unit and a value state output from a one-bit register (state) of the control logic unit, and shifting register values in right and left directions; and a UV-block unit for outputting one-bit register values (P m−1 /u 0 and a 0 /v 0 ) to the control logic unit when receiving the control signals from the control logic unit, and calculating U and V values of multiplication and division algorithms.