Patent ID: 7154303

Claim:
A dynamic circuit comprising: a first clock input terminal; a plurality of input terminals; a precharge MOS transistor connecting a source-drain path between a first potential power supply and a precharge node and connecting a gate terminal to the first clock input terminal; and a plurality of logical-operating MOS transistors, wherein gate terminals of the plurality of logical-operating MOS transistors are connected to the plurality of input terminals, respectively, and at least one intermediate node is formed to connect the source-drain pats of the plurality of logical-operating MOS transistors between the precharge node and a second potential power supply, the dynamic circuit further comprising: a second clock input terminal; and a precharge MOS transistor, different from the precharge MOS transistor, connecting the source-drain path between the first potential power supply and the precharge node and connecting the gate terminal to the second clock input terminal, wherein the different precharge MOS transistor turns to be conductive from the time of formation of a conductive path from the intermediate node to the precharge node.