Patent ID: 8054099

Claim:
An integrated circuit comprising: a number of dual interlocked storage cell flip-flops, wherein each of the number of dual interlocked storage cell flip-flops has two inputs and four storage nodes, wherein the four storage nodes include a number of pairs of circuit nodes that form a number of upsettable circuit node pairs, and wherein a first two of the four storage nodes comprise a master dual interlocked storage cell latch and a second two of the four storage nodes comprise a slave dual interlocked storage cell latch; and a number of temporal filters having two outputs, wherein each of the two outputs is connected to two inputs of a dual interlocked storage cell flip-flop in the number of dual interlocked storage cell flip-flops, wherein each input of the two inputs is connected to a corresponding storage node in the first two storage nodes of the master dual interlocked storage cell latch of the dual interlocked storage cell flip-flop, and wherein the number of temporal filters is physically located between a pair of circuit nodes in the number of pairs of circuit nodes forming a number of upsettable circuit node pairs within the dual interlocked storage cell flip-flop to increase critical node spacing.