Patent ID: 7601630

Claim:
A method for fabricating a semiconductor memory device, the method comprising: forming a first insulation layer on a semiconductor substrate having a cell array region, a core region, and a peripheral region, each having at least one transistor formed thereon; forming a first landing pad on the first insulation layer in the core region and a second landing pad in the peripheral region on the first insulation layer; forming a second insulation layer overlying the first and second landing pads; and forming first conductive lines overlying the first landing pad with the second insulation layer interposed therebetween in the core region and a second conductive line overlying the second landing pad in the peripheral region, wherein the first landing pad is overlapped with a portion of one of the first conductive lines when viewed in plan view, is spaced apart from a first contact connecting the other one of the first conductive lines with the at least one transistor and is spaced apart from the first conductive lines with the second insulation layer interposed therebetween, and wherein the second landing pad is connected to the second conductive line through a second contact.