Patent ID: 7750734

Claim:
An apparatus comprising: an integrated circuit (IC) comprising: a first single-ended gain stage configured to receive an input signal, amplify the input signal, and produce a first amplified signal, wherein the first single-ended gain stage comprises a first transistor comprising a first terminal configured to receive the input signal and a second terminal configured to provide the first amplified signal; a second single-ended gain stage in parallel with the first single-ended gain stage and configured to receive the input signal, amplify the input signal, and produce a second amplified signal, wherein the second single-ended gain stage comprises a second transistor comprising a first terminal configured to receive the input signal and a second terminal configured to provide the second amplified signal, wherein the second single-ended gain stage further comprises a first impedance element coupled to the first terminal of the second transistor, and wherein the first terminal of the second transistor receives the input signal via the first impedance element, and wherein the second single-ended gain stage further comprises a third transistor arranged in a cascode configuration with the second transistor; an inverter coupled to the second single-ended gain stage and configured to receive the second amplified signal and produce an inverted signal representing an inversion of the second amplified signal; and an adder configured to add the first amplified signal and the inverted signal to produce an output signal of the IC.