Patent ID: 7727844

Claim:
A method comprising: forming a first oxide layer over a silicon substrate; etching the first oxide layer to form first oxide layer patterns such that a portion of the silicon substrate at a channel area thereof is exposed, thereby forming an opening; forming a gate insulating layer over the portion of the silicon substrate exposed through the opening; depositing a gate conductive layer on and directly contacting the gate insulating layer such that the opening is filled with the gate conductive layer; forming a gate and protective first oxide layer patterns at lower sidewalls of the gate by etching the gate conductive layer and the first oxide layer patterns, wherein the protective first oxide layer patterns directly contact edge portions of the gate insulating layer, the uppermost surface of the silicon substrate and lower edge portions of the gate; forming a second oxide layer on the silicon substrate including the uppermost surface of the gate and sidewalls of the gate and the protective first oxide layer patterns; forming low-density source/drains in the silicon substrate by performing a low-density ion implantation process after forming the second oxide layer; removing the second oxide layer from the uppermost surface and sidewalls of the gate and sidewalls of the first oxide layer patterns after forming the low-density source/drains; forming gate spacers on and directly contacting sidewalls of the gate and the protective first oxide layer patterns after removing the second oxide layer and forming the low-density source/drains, wherein the gate spacers overlap the low-density source/drain areas; and then forming high-density source/drains by performing a high-density ion implantation process using the gate spacers as an ion implantation mask, wherein the gate insulating layer does not overlap the low-density source/drain and the high-density source/drains.