Patent ID: 7480776

Claim:
A semiconductor memory device, comprising: an integrated circuit (IC) memory chip comprising an integrated memory circuit and a plurality of address pins, wherein the integrated memory circuit comprises: a memory cell array; a data buffer for processing data read from or written to the memory cell array; and a data width control circuit for selectively controlling a data width of the data buffer in response to one or more address bits of an external address signal applied to one or more address pins of the IC memory chip, wherein the data width control circuit comprises: a decoder for decoding the one or more address bits of the external address signal in response to a data access command to generate a first control signal; and a data buffer controller, responsive to the first control signal, to generate a second control signal for controlling the data width of the data buffer, wherein the decoder comprises: a switching circuit; and a logic circuit, wherein the switching circuit is responsive to the data access command in the form of a read command and a write command to pass the one or more address bits of the external address signal to the logic circuit and wherein the logic circuit processes the external address signal to generate the first control signal.