Patent ID: 7184478

Claim:
A receiver circuit, comprising: a differential analog feed forward equalizer (FFE) circuit for receiving a dispersion distorted analog signal and processing the received signal to generate an equalized analog data signal (dispersion compensated signal); a differential clock and data recovery (CDR) circuit for receiving the equalized analog data signal and processing the received equalized analog data signal to generate a recovered clock signal, a decision feedback equalizer (DFE) sign control signal, and a retimed digital data signal; a differential analog slicing level control circuit providing a slicing level input signal to the CDR circuit for adding a static offset to the equalized analog data signal from the FFE; a differential analog DFE circuit processing the DFE sign control signal into a DFE feedback signal supplied to the CDR circuit for adding a dynamic offset to the equalized analog data signal; wherein the FEE is a finite impulse response (FIR) filter with adjustable tan weights, the tan weights having been set to substantially or partially provide dispersion compensation of the signal; wherein the differential slicing level control circuit has means for generating the slicing level input signal in the form of a differential current; wherein the DFE circuit has means for generating the DFE feedback signal in the form of a differential current, the polarity of said differential current being controlled by the DFE sign control signal; and, wherein the CDR circuit comprises: a data discriminator and a flip flop; the data discriminator receiving the equalized analog data signal from the FFE, the slicing level input signal and the DFE feedback signal. combining said three analog signals and processing them into a raw data signal which is a digital signal; the flip fan receiving said raw data signal and the recovered clock signal to generate the DFE Sign control signal and the retimed data signal.