Patent ID: 8037384

Claim:
A semiconductor device comprising: a test target circuit to be tested; scan chains that enable scanning of the test target circuit; a first random number generation circuit that generates random numbers to form test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit and generates random numbers; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit, wherein the random number control circuit includes an inversion logic unit that inverts a logic of an output value from the first random number generation circuit; a condition setting circuit that sets an inversion control condition in the inversion control circuit; and an inversion control circuit that uses the random numbers generated by the second random number generation circuit to control the operation of the inversion logic unit, under the condition set by the condition setting circuit, wherein an output signal from the inversion logic unit is supplied to the test target circuit.