Patent ID: 7228325

Claim:
A circuit for adding a signal at a first input (A) and a second input (B) to produce a sum output (S) according to a bypass signal, comprising: a third input (bypass) for accepting the bypass signal; a logic circuit, communicatively coupled to the third input (bypass) and at least one of the first input (A) and the second input (B), the logic circuit configured to hold at least one of a value of the first input (A) and a value of the second input (B) according to the third input (bypass); a bypass path through which at least one of the first input (A) and the second input (B) is routed according to the bypass signal; and a second logic circuit communicatively coupled to the third input (bypass) and an adder output and an output of the bypass path, the second logic circuit configured to pass only one of the adder output and an output of the bypass path to the sum output (S) according to the third input (bypass); wherein the logic circuit further generates a carry output (CARRY) without computing a new adder output according to the bypass signal (bypass).