Patent ID: 7275226

Claim:
A method of performing latch up check on an integrated circuit (IC) design comprising the steps of: computing a rectangular shape that encloses a conductor region shape and contact shapes on the integrated circuit design, said rectangle shape being the smallest rectangular shape that completely encloses the conductor region shape and the contact shapes; rasterizing the conductor region shape and the contact shapes; iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm; generating shapes representing an unreachable area of the conductor region shape; checking the shapes representing the unreachable area of the conductor region shape against junction shapes in the integrated circuit design, and reporting to a designer any junction shapes which intersect the unreachable area as errors; representing the contact shapes as cells in a byte array; exploring the conductor region shape by expanding the conductor region shape into neighboring cells of the byte array; and periodically skipping expanding corner cells of the contact shapes.