Patent ID: 7504328

Claim:
A process to manufacture a MOSFET, having a source, a gate, and a drain, comprising: providing a P-type silicon wafer and depositing thereon a layer of hafnium oxide; heating said oxide coated wafer at between about 500 and 600° C. for between about 10 and 60 minutes; depositing a first layer of hafnium nitride on said layer of hafnium oxide; then depositing a layer of tantalum nitride on said first layer of hafnium nitride; forming an etch mask that defines said gate and then forming said gate by etching all unprotected surfaces until said silicon wafer is exposed; fully removing said etch mask and then immersing said wafer in dilute HF; then, in a chamber maintained at all times at a pressure below about 5×10 −7 torr, depositing, in succession, a silicide forming layer of ytterbium followed by a capping layer of titanium and then a second layer of hafnium nitride; then heating said wafer in forming gas at a temperature between about 400 and 600° C. for about 1 hour, thereby forming opposing source and drain regions of ytterbium silicide immediately adjacent to said gate; and through etching in dilute HF and then in a mixture of sulphuric acid and hydrogen peroxide, removing said layers of titanium and hafnium nitride as well as any unreacted ytterbium.