Patent ID: 7882325

Claim:
An apparatus comprising: an execution unit; and a memory execution unit to perform a load of a 2N-bit dataset from memory to the execution unit in a single cycle using an N-bit load port in response to an instruction to load the 2N-bit dataset encoded in a single micro-operation, the memory execution unit to translate the single micro-operation into two consecutive memory access cycles, a first memory access cycle to retrieve the high-order N-bits of the 2N-bit dataset at Effective Address (EA)+16, a second memory access cycle to retrieve the low-order N-bits of the 2N-bit dataset at EA, and concurrently loading the high-order N-bits of the 2N-bit dataset into a high-order execution stack and the low-order N-bits of the 2N-bit dataset into a low-order execution stack in the execution unit in the single cycle.