Patent ID: 8593860

Claim:
An SRAM memory device comprising: a global bit line; a plurality of sectioned bit lines (SBLs) connected to the global bit line, each of the SBLs comprising: a local bit line; a plurality of memory cells connected to the local bit line; a local complement bit line connected to the memory cell; and a pass gate coupled to the local bit line; the global bit line being provided in a layer above or below the SBLs and configured in a parallel direction to the local bit lines, wherein the global bit line is not a sense line; wherein the SBLs are arranged in a matrices, each matrix comprising 2 or more SBLs arranged along the global bit line, the SBLs including multiple level column decoding to connect the SBLs to the global bit line; wherein an output of the pass gate within each SBL is coupled to the global bit line; and wherein the pass gates are configured, via coupling to at least one selection signal line, to connect the sectioned bit lines to the global bit line such that a selected pass gate of a selected SBL, when turned on, selectively passes data of the plurality of memory cells of the selected SBL to the global bit line, and unselected pass gates of unselected SBLs, when turned off, isolate the unselected SBLs from the global bit line.