Patent ID: 7847529

Claim:
A linear voltage regulator comprising: a first circuit configured to receive a first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primary output node; and a second circuit having first and second inverters electrically coupled to the primary output node of the first circuit, the second circuit configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range, the second frequency range being greater than the first frequency range; wherein the first inverter has a first input terminal and a first output terminal, the first input terminal being electrically coupled to the first output terminal, the first input terminal being further electrically coupled to a capacitor which is further coupled to electrical ground, the first inverter being further electrically coupled to the primary output node such that a second voltage on the first output terminal is less than the output voltage at the primary output node; and the second inverter having a second input terminal and a second output terminal, the second input terminal being electrically coupled to the first output terminal of the first inverter, the second inverter being further electrically coupled to the primary output node; and the second circuit further comprises a P-FET transistor having a gate terminal, a drain terminal and a source terminal, the source terminal being electrically coupled to a voltage source, the drain terminal being electrically coupled to the primary output node, the gate terminal electrically communicating either directly or indirectly with the second output terminal of the second inverter, such that when the output voltage at the primary output node is increased, the second voltage on the first output terminal of the first inverter is less than the output voltage on the primary output node which induces the second inverter to output a high logic voltage on the second output terminal, and the P-FET transistor reduces the output voltage on the primary output node in response to the high logic voltage.