Patent ID: 7132364

Claim:
A method for forming a metal interconnect of a semiconductor device; comprising: forming a first interconnect insulating layer on a substrate; forming a via hole on a predetermined portion of the first interconnect insulating layer; forming a second interconnect insulating layer on the first interconnect insulating, layer and planarizing the second interconnect insulating layer; forming a hard mask layer on the second interconnect insulating layer; patterning the hard mask layer to remove selective portions of the hard mask layer to create at least one exposed region; forming at least one sidewall in the exposed region, wherein the at least one side wall is formed by forming an insulating layer on the hard mask layer and the exposed region, and at least a portion of the insulating layer; forming a trench by etching the second interconnect insulating layer wherein the sidewalls are used as an etching mask; and forming a metal interconnect in the trench.