Patent ID: 8874822

Claim:
A storage system for accessing data on a low-latency random read memory (LLRRM) device, the storage system comprising: the LLRRM device comprising a plurality of memory banks, each memory bank having an associated LLRRM address range; a storage operating system engine configured for: allocating a plurality of request-queuing data structures, each request-queuing data structure being assigned to a memory bank in the plurality of memory banks and being associated with the LLRRM address range of the assigned memory bank; receiving a plurality of access requests at requested LLRRM addresses in the LLRRM device, each access request comprising a read request or write request; for each received access request, storing the access request in a request-queuing data structure, the plurality of request-queuing data structures comprises a plurality of read request-queuing data structures for storing read requests and at least one write request-queuing data structure for storing write requests; sending, to the LLRRM device, a series of access requests comprising an access request from each read request-queuing data structure in successive order from a first read request-queuing data structure to a last read request-queuing data structure and continuing again from the first read request-queuing data structure until no read requests remain; sending to the LLRM device any access requests from the at least one write request-queuing data structure; and a serial connection between the storage operating system engine and the LLRRM device for sending the series of access requests to the LLRRM device.