Patent ID: 7262465

Claim:
A p-channel MOS transistor, comprising: a strained SOI substrate, said strained SOI substrate comprising a SiGe mixed crystal layer and a strained Si layer formed on said SiGe mixed crystal layer via an insulation film, a channel region being included in said strained Si layer; a gate electrode formed on said strained Si layer in correspondence to said channel region via a gate insulation film; and first and second p-type diffusion regions formed in said strained Si layer at respective first and second sides of said channel region, said strained Si layer having first and second sidewall surfaces respectively at said first and second sides thereof, a first SiGe mixed crystal region in contact with said first sidewall surface and in continuation to said SiGe mixed crystal layer through a first opening formed in said insulation film, a second SiGe mixed crystal region in contact with said second sidewall surface and in continuation to said SiGe mixed crystal layer through a second opening formed in said insulation film, said first and second SiGe mixed crystal regions being in lattice matching with said strained silicon layer respectively at said first and second sidewall surfaces.