Patent ID: 7396738

Claim:
A method of forming a semiconductor memory device, the method comprising: providing a semiconductor substrate having a cell region and a peripheral region, the cell region configured to define a plurality of memory cells; forming first and second gate dielectric layers over the semiconductor substrate in the cell region and peripheral region, respectively; forming an insulating layer over at least the second gate dielectric layer; forming an isolation trench in the peripheral region, the isolation trench defining a first trench and a second trench provided below the first trench, the first trench extending below the second gate dielectric layer and exposing the second gate dielectric layer, the second trench having a smaller opening then the first trench, wherein a step is defined at an interface between the first and second trenches; providing a first gap-fill layer over the isolation trench and on the step, the first gap-fill layer having a first portion on a sidewall of the insulating layer, a second portion on a sidewall of the second gate dielectric layer and over the step, and a third portion at least partly filling the second trench of the isolation trench, the second portion being thicker than the first portion; performing a wet etch to remove at least part of the first gap-fill layer; and providing a second gap-fill layer over the first gap-fill layer in the isolation trench to form an isolation structure, wherein the second portion of the first gap-fill layer is configured to protect the second gate dielectric layer during the wet etch step.