Patent ID: 8405224

Claim:
A semiconductor device comprising a multilayer interconnect structure which is formed above a substrate and includes first to Nth interconnect layers, where N is an integer equal to or larger than 4, stacked from the substrate in this order, the semiconductor device comprising: a lower-layer interconnect formed in the first interconnect layer; an intermediate interconnect formed in the second interconnect layer; an upper-layer interconnect formed in the (N−1)th interconnect layer; a first contact via formed to electrically connect the lower-layer interconnect to the intermediate interconnect; and a second contact via formed to electrically connect the intermediate interconnect to the upper-layer interconnect, wherein when viewed from above, the first contact via and the second contact via both have a rectangular shape with their long sides extending in a same first direction parallel to a longitudinal axis of the lower-layer interconnect, and overlap with each other, and wherein a dimension of the intermediate interconnect extending in the first direction is equal to or greater than a length of the long sides of each of the first contact via and the second contact via.