Patent ID: 8445376

Claim:
A process for post-etching treatment of copper interconnecting wires used to electrically couple an upper interconnecting layer with a lower interconnecting layer, the process comprising: forming the lower interconnecting layer, wherein the forming of the lower interconnecting layer comprises: forming a first dielectric layer on a substrate, wherein the first dielectric layer comprises a first top layer formed on a first low-k material layer that is formed on a first etch stop layer; forming a plurality of wire trenches in the first dielectric layer by etching the first top layer and the first low-k material layer of the first dielectric layer using an etching as selected from the group consisting of CO 2 , CF 3 H, CF 2 H 2 , and CFH 3 until the first etch stop layer of the first dielectric layer is exposed; depositing copper in the plurality of wire trenches; and depositing a top barrier layer overlying the first dielectric layer and the plurality of wire trenches, forming the upper interconnecting layer, wherein the forming of the upper interconnecting layer comprises: forming a second dielectric layer on the top barrier layer; forming a plurality of vias extending through the second dielectric layer and the top barrier layer to expose the copper being deposited in the plurality of wire trenches in the first dielectric layer; and treating the exposed copper through the plurality of vias formed through the second dielectric layer and the top barrier layer using a plasma process comprising NH 3 .