Patent ID: 8232122

Claim:
A method for fabricating an LED chip, comprising: providing a substrate with a SiO 2 pattern layer formed on a portion of a top surface of the substrate, the SiO 2 pattern layer dividing another portion of the top surface the substrate without the SiO 2 pattern layer thereon into a plurality of epitaxial regions; growing lighting structures on the epitaxial regions with a gap formed between each two adjacent lighting structures to expose a part of the SiO 2 pattern layer between the each two adjacent lighting structures; permeating a first etching solution into the gap between the each two adjacent lighting structures to etch the SiO 2 pattern layer away, and forming spaces between a bottom surface of each of the each two adjacent lighting structures and the substrate; permeating a second etching solution into the gap and the space to etch a corresponding lighting structure at a bottom surface and side walls of the corresponding lighting structure, thereby forming the corresponding lighting structure with a trapezoid shape with the sidewalls inclined inwardly along a top-to-bottom direction; forming a p-type contact electrode and an n-type contact electrode on the lighting structure; and cutting the substrate along the gap between the each two adjacent lighting structures, and forming a plurality of LED chips.