Patent ID: 7952142

Claim:
MOSFET gate structures comprising: a first gate structure and a second gate structure formed on a semiconductor substrate; a pair of first offset spacers formed adjacent either side of the first gate structure, each of the first offset spacers comprising a first silicon oxide layer and a first dielectric layer overlying the first silicon oxide layer; a pair of second offset spacers formed adjacent either side of the second gate structure, each of the second offset spacers comprising a second silicon oxide layer and a second dielectric layer overlying the second silicon oxide layer; and ion implanted doped regions formed in the semiconductor substrate adjacent the first offset spacers and the second offset spacers respectively to form a first MOSFET device and a second MOSFET device; wherein, a maximum width of each of the first offset spacers is different from a maximum width of each of the second offset spacers, and the first silicon oxide layer is thinner than the second silicon oxide layer, and wherein the first silicon oxide layer and the second silicon oxide layer are formed on the underlying first gate structure and second gate structure respectively, and at least one of the first gate structure and the second gate structure is doped with a dopant selected from the group consisting of nitrogen and fluorine ions.