Patent ID: 8630053

Claim:
A data processing system, the data processing system comprising: a buffer operable to store received digital samples as a buffered output; an equalizer circuit operable to equalize the buffered output using a first equalization target to yield a first equalized output; a data processing circuit operable to decode the first equalized output to yield a first data output; a retry determination circuit operable to select a second equalization target based at least in part on an occurrence of an error in the first data output, wherein the equalizer circuit is further operable to equalize the buffered output using the equalization target to yield a second equalized output, and wherein the data decoding circuit is further operable to decode the second equalized output to yield a second data output; and a target set buffer operable to store at least the first equalization target and the second equalization target, and wherein the first equalization target does not require additional adaptation in the data processing system.