Patent ID: 6919242

Claim:
A method of simultaneously making a pair of closely spaced, side-by-side, non-volatile memory transistors comprising: depositing on a semiconductor substrate side-by-side floating gates with closely spaced laterally inward edges and distal laterally outward edges, each floating gate having laterally outward and adjacent conductive spacers separated from the floating gate only by tunnel oxide; implanting source regions into said substrate beneath the conductive spacers; implanting a shared drain region into said substrate between the side-by-side floating gates; depositing a conductive region peripherally surrounding and contacting portions of both the floating gate and the conductive spacer, creating an equal potential region separated by tunnel oxide; and depositing a control layer insulatively spaced over the floating gate and conductive spacer whereby a programming voltage applied to the control layer can pull charge from a source region through the tunnel oxide into the floating gate and adjacent conductive spacer.