Patent ID: 6974748

Claim:
A method for manufacturing a semiconductor device comprising: forming a split gate electrode structure in a memory cell region of a substrate; forming a silicon oxide layer on the split gate electrode structure and the substrate; forming a polysilicon layer on the silicon oxide layer; forming an oxide spacer on a sidewall of the polysilicon layer that is positioned over the split gate electrode structure; forming a silicon nitride layer on the polysilicon layer and the oxide spacer; polishing the silicon nitride layer and the polysilicon layer to form two polysilicon layers divided by the split gate electrode structure; removing the silicon nitride layer; and selectively etching the divided polysilicon layers to form a word line on sidewalls of the split gate electrode structure and a logic gate electrode pattern in a logic region of the substrate, wherein the word line has an upper width and a lower width, and wherein the lower width is greater than the upper width.