Patent ID: 8022905

Claim:
A display device comprising: a pixel array section and a driving section; the pixel array section including scanning lines arranged in rows, signal lines arranged in columns, and pixels arranged in a matrix, each of the pixels being disposed at the intersection of one of the scanning lines and one of the signal lines; each of the pixels including at least a sampling transistor, a drive transistor, a holding capacitance, and a light-emitting device, wherein the sampling transistor has its control terminal connected to the scanning line and its pair of current terminals connected between the signal line and the control terminal of the drive transistor, the drive transistor has one of its pair of current terminals connected to the light-emitting device and the other of its pair of current terminals connected to a power source, and the holding capacitance is connected between the control and current terminals of the drive transistor; the driving section including at least a write scanner adapted to sequentially supply a control signal to each of the scanning lines for line-sequentially scanning, and a signal selector adapted to supply a video signal to each of the signal lines, wherein the sampling transistor turns on in response to the control signal supplied to the scanning line to sample the video signal from the signal line and write the sampled video signal to the holding capacitance, the sampling transistor negatively feeds the current flowing from the drive transistor back to the holding capacitance during a given correction period lasting until the sampling transistor turns off in response to the control signal so as to apply the correction of the mobility of the drive transistor to the video signal written to the holding capacitance, the drive transistor supplies a current appropriate to the video signal level written to the holding capacitance to the light-emitting device so as to cause the light-emitting device to emit light, wherein the write scanner includes a shift register and output buffers, the shift register sequentially generates an input signal from each of its stages in synchronism with line-sequentially scanning, each of the output buffers is connected between one of the stages of the shift register and one of the scanning lines and outputs a control signal to the scanning line in response to the input signal, and the output buffer varies the trailing edge waveform of the control signal, adapted to define the timing at which the sampling transistor turns off, at least in two steps in response to the input signal so as to variably control the correction period according to the video signal level.