Patent ID: 7482880

Claim:
An apparatus comprising: a counter having an input for receiving a reference clock signal, a first output for providing a sample clock signal, and a second output; a frequency measurement device having a first input coupled to the sample clock, a second input coupled to a feedback signal, and an output for providing a digital error signal indicating a difference between the ratio of the reference and actual feedback clocks; a digital device having a first input coupled to the sample clock signal, a second input coupled to a digital error signal, and an output for providing a filtered digital error signal; a summing device having a first input coupled to the filtered error signal, a second input and an output for providing an oscillator control signal resulting from a combination of the filtered error signal and the second input; and an oscillator having an input coupled the frequency control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal, wherein the second output of the counter having a multi-bit representation of a frequency modulation control signal value is coupled to the second input to the summing device.