Patent ID: 8838945

Claim:
A data processing circuit comprising: an execution circuit comprising a plurality of functional units; an instruction memory; an instruction decoder coupled to the execution circuit for controlling the execution circuit according to successively executed instructions retrieved from the instruction memory, the instruction decoder being operable in at least a first instruction mode and second instruction mode, instructions for execution in the first instruction mode including an instruction with respective fields for controlling each of the respective functional units, instructions for execution in the second instruction mode each containing no more than one or more fields for controlling a subset of the plurality of functional units, instructions in the first instruction and the second instruction mode have mutually different lengths; a mode control circuit coupled to the instruction decoder, the mode control circuit being configured to control a selection between the first and second instruction modes for instructions executed following a jump command in an instruction in response to instruction mode selection information provided by the execution of the jump command; and a sequencer with a program counter register and an instruction mode dependent shift circuit coupled between the program counter register and a memory address port to shift the program counter value by a mode-dependent amount before applying it to the instruction memory, the instruction mode dependent shift circuit having a shift control input coupled to the mode control circuit.