Patent ID: 8762808

Claim:
An apparatus comprising: a decoder circuit configured to generate a single address signal to read a first parity data signal, a second parity data signal and read and/or write systematic information data, a first a-priori-information signal and a second a-priori-information signal, wherein said decoder circuit (i) reads said first parity data signal, said systematic information data and said first a-priori-information during even half-iterations of a decoding operation and (ii) reads said second parity data, said systematic information data and said second a-priori-information during odd half-iterations of said decoding operation; and a memory configured to store (i) said systematic information data in a first single bank memory and (ii) said first and second a-priori-information signals in a second single bank memory, wherein said systematic information data and said first and second a-priori-information signals are accessible by said single address signal pointing to a similar address in said first single bank memory and said second single bank memory.