Patent ID: 7849298

Claim:
A processor, comprising: at least one execution unit; an instruction sequencing unit coupled to the at least one execution unit; a cache coupled to a memory which is external to the processor, wherein the cache stores volatile information forming at least a portion of a soft state of a process, the soft state being state information that is non-critical for executing a process in the processor, wherein the cache stores a hard architected state, wherein the hard architected state is information within the processor that is architecturally required for the processor to execute the process from a present point in the process, wherein the information comprises information that is stored in a Link and Count Register (LCR), wherein the LCR contains a count register, a link register and rename registers that enable a Branch Execution Unit (BEU) to resolve conditional branches to obtain a path address for the process, and wherein a shadow copy of the hard architected state is stored in the cache such that in response to receiving a process interrupt at the processor the shadow copy of the hard architected state is stored in the memory such that the hard architected state is modified without regard to completion of the storing of the shadow copy in the memory; and interface circuitry coupled to the cache that transmits the soft state to the memory in response to the processor receiving a process interrupt.