Patent ID: 7941717

Claim:
A testing circuit for the testing of an integrated circuit core or circuitry external to an integrated circuit core, the testing circuit comprising: a shift register circuit (WBR) comprising a plurality of cells, for passing test signals, the cells being arranged as a plurality of banks of cells in series; a serial input and a serial output for connection to the input and output of the shift register circuit; a plurality of parallel inputs and outputs, wherein the parallel inputs are for passing test signals to the integrated circuit core for testing of the core, wherein a first bank of bypass multiplexers is controllable either to connect integrated circuit core outputs to the multiplexer outputs or to connect the parallel inputs to the multiplexer outputs thereby bypassing the integrated circuit core, wherein each cell comprises a hold input, wherein the hold input is for coupling the output of a storage element of the cell to the input of the storage element of the cell when the testing circuit is operated in a test mode, wherein the testing circuit is operable in a bypass mode in which the integrated circuit core is bypassed and hold signals are applied to the hold inputs, and wherein the testing circuit is further operable in: a core internal test mode, in which the integrated circuit core outputs are connected through the multiplexers to the banks of shift register cells; and a core external test mode, in which the integrated circuit core is bypassed and the serial input is connected to a first bank of shift register cells, with the banks of shift register cells connected in series.