Patent ID: 7349998

Claim:
An integrated circuit device which is a first LSI and issues data to a second LSI to make the second LSI execute a corresponding processing, said first and second LSIs being connected with a bidirectional command bus, comprising: a counter where the number of data stages which said second LSI can simultaneously receive is set at a reset, and which is decremented or incremented when said data is issued and is incremented or decremented when a ready signal indicating completion of processing corresponding to the data is received from said second LSI; and a data issuing control circuit which inhibits issuing of said data when said counter value becomes a predetermined value; wherein said first and second LSIs are connected with a bi-directional data bus, said first LSI further comprising: an arbiter circuit which issues a grant signal for granting access to said data bus to said second LSI responding to a request signal for requesting access to said data bus from said second LSI, wherein said data issuing control circuit inhibits issuing of data when said grant signal is issued.