Patent ID: 7485521

Claim:
A method for forming a self-aligned dual stressed layer for a semiconductor device having an NFET and a PFET, the method comprising the steps of: forming a first stressed silicon nitride layer over a first one of the NFET and the PFET, the first stressed silicon nitride layer including an end over a portion of an intermediate region between the NFET and the PFET; depositing a second stressed silicon nitride layer over the NFET, the PFET and the intermediate region, the second stressed silicon nitride layer forming a first shoulder over the end of the first stressed silicon nitride layer; forming a sacrificial layer over the second stressed silicon nitride layer, the sacrificial layer forming a second shoulder over the first shoulder; forming a mask over the sacrificial layer and a second one of the NFET and the PFET such that a mask edge is between the first shoulder and the second shoulder; removing the sacrificial layer over the first one of the NFET and the PFET using the mask; removing the mask; and removing the second stressed silicon nitride layer over the first one of the NFET and the PFET.