Patent ID: 7509480

Claim:
A computer program product comprising a computer readable storage medium having control logic stored therein for causing a computer to execute instructions corresponding to one of a plurality of instruction set architecture (ISA) decoding modes, comprising: first control logic for associating a plurality of instructions segregated into at least a first category and a second category with at least a first address range and a second address range, wherein the first category and the first address range correspond to a first ISA decoding mode, and the second category and the second address range correspond to a second ISA decoding mode, and wherein the first address range and the second address range allow an arbitrary non-overlapping range of addresses to be associated with the first and second categories without requiring a symmetrical memory partition based on high-order address bits; and second control logic for providing the first address range and the second address range to a central processing unit (CPU), wherein instructions fetched from memory at locations corresponding to the first address range are designated for decoding according to the first ISA decoding mode, and instructions fetched from memory at locations corresponding to the second address range are designated for decoding according to the second ISA decoding mode.