Patent ID: 7943503

Claim:
A method of forming a vertical interconnect structure within a semiconductor device, the method comprising: forming a second metal layer integral with a vertical interconnect structure to a first metal layer, the second metal layer having four conductive layers, each of the four conductive layers being of different material compositions, wherein a coating layer is titanium, and the coating layer forms a direct interface with an aluminum containing layer, the interconnect structure having three conductive layers, the three conductive layers formed of three different material compositions formed concurrently with three of the four layers of the second metal layer, forming the second metal layer integral with the vertical interconnect structure including: forming an opening extending vertically downward through an insulating layer to an underlying portion of the first metal layer, wherein a length of the opening in a horizontal plane is sufficiently greater than a width of the opening in the horizontal plane so that the opening has a trench shape with a width of about 0.35 microns or less; and filling the opening with conductive material to form a conductive trench via, while simultaneously forming a portion of the second metal layer above the insulating layer.