Patent ID: 7863953

Claim:
A current mode logic circuit, comprising first and second differential switching stages, wherein each of the first and second differential switching stages comprises a plurality of switching devices in a parallel arrangement each arranged to receive one of a plurality of clock signals, each of the first and second differential switching stages responds to a combination of the plurality of clock signals applied to the switching devices, wherein the plurality of switching devices of the first differential switching stage includes first and second switching devices each having a control terminal, a first terminal and a second terminal, the plurality of switching devices of the second differential switching stage includes first and second switching devices each having a control terminal, a first terminal and a second terminal, and wherein the second terminal of first switching device of the first differential switching stage is connected to the second terminal of the first switching device of the second differential switching stage and the second terminal of the second switching device of the first differential switching stage is connected to the second terminal of the second switching device of the second differential switching stage.