Patent ID: 8450129

Claim:
A method of fabricating a thin film transistor (TFT) substrate comprising: forming a gate interconnection line on an insulating substrate, the gate interconnection line comprising a gate line and a gate electrode; forming a gate insulating layer on the gate interconnection line; forming a semiconductor layer and a data interconnection line on the semiconductor layer, the data interconnection line comprising a data line, a source electrode, and a drain electrode; sequentially forming a first passivation layer and a second passivation layer on the data interconnection line, the second passivation layer formed of a same material as the first passivation layer and has more porous lattice structure than that of the first passivation layer; etching the second passivation layer and the first passivation layer, and exposing a drain electrode of a drain electrode-pixel electrode contact portion; and forming a pixel electrode connected to the drain electrode, wherein etching the second passivation layer and the first passivation layer comprises forming the outer sidewalls of the second passivation layer inside the outer sidewalls of the first passivation layer.