Patent ID: 8134824

Claim:
A decoupling capacitor comprising: a semiconductor having an n-type portion and a p-type portion; an NFET transistor formed in said semiconductor; and a PFET transistor formed in said semiconductor, said PFET transistor being substantially formed in said n-type portion and said NFET transistor being substantially formed in said p-type portion, a boundary between said n-type portion and said p-type portion being substantially straight, said transistors configured such that a source and drain of said PFET transistor are connected to a high voltage rail and a source and drain of said NFET transistor are connected to a low voltage rail, wherein a gate of said PFET transistor is connected to said low voltage rail and a gate of said NFET transistor is connected to said high voltage rail, and said NFET transistor and said PFET transistor are arranged in parallel between said high voltage rail and said low voltage rail.