Patent ID: 8588228

Claim:
A nonvolatile memory controller comprising: a plurality of processors; a host controller interface comprising: a command fetch module; a command dispatch module; a plurality of command assembly buffers coupled between the command fetch module and the command dispatch module; the command fetch module configured to detect a nonvolatile memory command stored in a host processing unit by monitoring a submission queue head pointer and a submission queue tail pointer stored in the nonvolatile memory controller, select a command assembly buffer of the plurality of command assembly buffers, retrieve the nonvolatile memory command from the host processing unit, write the nonvolatile memory command to the selected command assembly buffer, and update the submission queue head pointer to indicate that the host controller interface retrieved the nonvolatile memory command from the host processing unit; and the command dispatch module configured to determine the selected command assembly buffer contains the nonvolatile memory command without receiving the submission queue head pointer and the submission queue tail pointer from the command fetch module, select a processor of the plurality of processors, and generate a first request message packet identifying the nonvolatile memory command and the selected processor; a data network coupled to the host controller interface; and a message network coupled to the host controller interface and the plurality of processors, the message network configured to route the first request message packet to the selected processor, the selected processor configured to process the nonvolatile memory command for transferring data between the host processing unit and a nonvolatile memory device through the data network.