Patent ID: 7545663

Claim:
A semiconductor storage device, comprising: a first group consisting of a plurality of core chips, each core chip having a memory cell, and a latch circuit unit for temporarily storing at least one of write data to be stored in the memory cell and read data retrieved from said memory cell; and an interface chip having a peripheral circuit for said cells included in said plurality of core chips; wherein said latch circuit units included in said plurality of core chips are connected in a cascade to said interface chip to perform one of a first operation and a second operation; wherein the first operation supplies write data to be stored in the memory cells serially to each of the latch circuit units from the interface chip, and then transfers the write data in parallel from the latch circuit units to their respective memory cells; wherein the second operation transfers read data from the memory cells to their respective latch circuit units, and then supplies the read data serially from the latch circuit units to the interface chip.