Patent ID: 7470961

Claim:
A semiconductor device comprising: a semiconductor silicon substrate; an impurity diffusion layer provided in a surface region of the semiconductor silicon substrate; an element isolation insulating layer provided in the surface region of the semiconductor silicon substrate; and gate wiring provided on the semiconductor silicon substrate via a gate oxide film, wherein the gate wiring has a gate electrode comprised of at least one selected from the group consisting of metal, metal silicide and polysilicon including impurities, a gate wiring upper structure comprised of silicon nitride provided in contact with the gate electrode, and a sidewall spacer provided in contact with both a side surface of the gate electrode and a side surface of the gate wiring upper structure, the side wall spacer is comprised of one kind or two or more kinds of inorganic compound insulating layers, and at least one kind of the inorganic compound insulating layers is comprised of silicon oxy nitride composed of silicon, oxygen and nitrogen in which a nitrogen content is in the range of 30 to 70% on a percentage basis of the number of nitrogen atoms to the sum of the numbers of oxygen atoms and nitrogen atoms.