Patent ID: 7548086

Claim:
An impedance control circuit in a semiconductor device, comprising: an impedance detector for outputting a first output value to a detection pad connected between an external determination resistor and a pull-up transistor array in response to a pull-up control code data, and outputting a second output value to a first resistance divider terminal commonly connected between a pull-up and pull-down transistor array of a first pull-up and pull-down transistor array pair in response to the pull-up control code data and a pull-down control code data; an output driver comprising: a second pull-up and pull-down transistor array pair; and a mismatch compensating unit, wherein the second array pair includes a plurality of pull-up transistors and a plurality of pull-down transistors, wherein each of the pull-up transistors is connected in series to a different one of the pull-down transistors, wherein the pull-up transistors are connected in parallel to one another, wherein the pull-down transistors are connected in parallel to one another, wherein the mismatch compensating unit is connected in parallel to a last one of the pull-up transistors or a last one of the pull-down transistors at a second resistance divider terminal between the second array pair to compensate for quantization error of the pull-up and pull-down control code data: wherein the mismatch compensating unit comprises one of a pull-up or pull-down transistor and a resistor connected between the transistor of the compensating unit and the second resistance divider terminal, the resistor having a resistance value of twice a unit resistance of the second array pair such that a mismatch between the pull-up and pull-down resistances in the second pull-up and pull-down transistor array is reduced by half a digital control resolution; and an impedance controller for performing a comparison on the first and second output values of the impedance detector to generate the pull-up and pull-down code data.