Patent ID: 8473533

Claim:
A computer-implemented method for simulating a circuit, the method comprising: receiving, by a processor, a Jacobian matrix of a non-linear equation representing the circuit under simulation, the Jacobian matrix having n rows of blocks and n columns of blocks, wherein each block A ij comprises a sub-matrix of numerical entries, the Jacobian matrix factorable into a lower triangular component L and an upper triangular component U; generating, by the processor, a test matrix Z having n rows and n columns of representative numerical entries, wherein a representative numerical entry z ij is determined as a function of a corresponding block A ij in the Jacobian matrix; performing, by the processor, a lower-upper factorization on the test matrix Z to derive a lower triangular component L Z and an upper triangular component U Z ; for each non-zero entry in the lower triangular component L Z of the test matrix Z, determining, by the processor, a corresponding block in the lower triangular component L of the Jacobian matrix; for each non-zero entry in the upper triangular component U Z of the test matrix Z, determining, by the processor, a corresponding block in the upper triangular component U of the Jacobian matrix; and outputting the lower triangular component L and the upper triangular component U of the Jacobian matrix.