Patent ID: 7229870

Claim:
A method of fabricating CMOS transistors comprising: forming a first well and a second well in active areas of a semiconductor substrate; forming first and second gate patterns on gate insulating layers on the first and second wells, respectively; forming a sidewall insulating layer; performing NMOS LIDD ion implantation to form first lightly doped regions in the first well; forming a first gate spacer insulating layer over the sidewall insulating layer; performing PMOS LDD ion implantation to form second lightly doped regions in the second well; sequentially stacking a spacer insulating layer and a second gate spacer insulating layer on the first gate spacer insulating layer; patterning the second and first gate spacer insulating layers and the sidewall insulating layer to form first and second spacers on sidewalls of the first and second gate patterns and expose upper surfaces of the semiconductor substrate in areas of the first and second lightly doped regions; performing NMOS source/drain ion implantation to form first heavily doped regions in the first well; and performing PMOS source/drain ion implantation to form second heavily doped regions in the second well.