Patent ID: 8753952

Claim:
A method of fabricating an integrated circuit, comprising the steps of: defining a contiguous active region having first and second portions at the locations of the surface corresponding to a first ferroelectric capacitor and second ferroelectric capacitor; forming a dielectric film overlying the first and second portions of the active region; defining a contiguous polycrystalline silicon structure having first and second portions overlying the first and second portions of the active region and the dielectric film; at locations corresponding to the first and second ferroelectric capacitors: depositing a first conductive material; then depositing a ferroelectric material; then depositing a second conductive material; etching the first and second conductive materials and the ferroelectric material, to define the first and second ferroelectric capacitors, the first ferroelectric capacitor overlying the first portion of the active region and the first portion of the polycrystalline silicon structure, and the second ferroelectric capacitor overlying the second portion of the active region and the second portion of the polycrystalline silicon structure; and forming a plurality of conductors, a first conductor in electrically-conductive contact with an element of the second conductive material at the first ferroelectric capacitor, a second conductor in electrically-conductive contact with an element of the first conductive material at the second ferroelectric capacitor, and one or more other conductors in electrically-conductive contact with and between an element of the first conductive material at the first ferroelectric capacitor and an element of the second conductive material at the second ferroelectric capacitor; wherein the step of defining the contiguous polycrystalline silicon structure simultaneously defines a separate polycrystalline silicon element.