Patent ID: 7889578

Claim:
A memory device comprising: an internal memory device including: a plurality of data bus inputs for receiving a signal on a data bus; a first strobe input for receiving a first strobe signal indicating that said signal on said data bus relates to a first type of packet; and a second strobe input for receiving a second strobe signal indicating that said signal on said data bus relates to a second type of packet; and a packet header decoder including: a data bus input for receiving a portion of said signal on said data bus; a third strobe input for receiving a third strobe signal; a pulse generator for generating a fourth strobe signal based, at least in part, on said third strobe signal; and a strobe generator for generating one of said first strobe signal and said second strobe signal based, at least in part, on: said portion of said signal on said data bus; and said fourth strobe signal.