Patent ID: 8867269

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells which are each capable of storing data of n bits (n is a natural number of 2 or more) and which are arranged in a matrix, a plurality of word lines which are connected to the plurality of memory cells, and a plurality of bit lines which are each connected to one end of corresponding ones of the plurality of memory cells; and a control circuit, wherein a first memory cell of the plurality of memory cells stores first data of n bits, a second memory cell of the plurality of memory cells stores second data used to determine whether data of k bits (k is a natural number from 2 to n inclusive) is stored in the first memory cell, and the control circuit: performs first determination of determining data read from the data of the second memory cell by supplying a first read voltage to a first word line of the plurality of word lines, performs second determination of determining data read from the second memory cell by supplying the first word line with a second read voltage different from the first read voltage, based on a result of the first determination, and outputs either one of a result obtained by reading the data stored in the first memory cell at the first read voltage and a result obtained by reading the data stored in the first memory cell at the second read voltage, based on a result of the second determination.