Patent ID: 7251573

Claim:
Phase Detector for detecting a phase difference between a data clock (DATA-CLK) and a reference clock (REF-CLK) using a data signal (DATA), wherein a transition of the data signal (DATA) is synchronous with a transition of the data clock (DATA-CLK) and the data clock (DATA-CLK) and the reference clock (REF-CLK) have the same frequency, comprising: a first signal generator ( 42 ) for generating a first binary signal (ERRQ), a pulse width of which is equal to a first time difference (ΔT 1 ) between a transition of the data signal (DATA) and a transition of a first reference clock signal (CKQ) adjacent to the transition of the data signal (DATA), wherein the first signal generator comprises an input for receiving the first reference clock signal (CKQ) and an input for receiving the data signal (DATA), wherein the first reference clock (CKQ) has half the frequency of the reference clock (REF-CLK) and is synchronous with the reference clock, a second signal generator ( 40 ) for generating a second binary signal (ERRI), a pulse width of which is equal to a second time difference (ΔT 2 ) between a transition of the data signal (DATA) and a transition of the second reference clock signal (CKI) adjacent to the transition of the data signal (DATA), wherein the second signal generator ( 40 ) comprises an input for receiving the second reference clock (CKI) and an input for receiving the data signal (DATA), output signal generator ( 44 ) for generating an output signal representative of the phase difference between the data clock (DATA-CLK) and the reference clock (REF-CLK), wherein the output signal is equal to ERRQ−2*(ERRQ AND ERRI) and AND represents a logical AND-operation, or the output is equal to (ERRQ XOR ERRI)−ERRI, wherein XOR represents a logical XOR-operation.