Patent ID: 7517726

Claim:
A method of fabricating a chip scale package (CSP), the method comprising the steps of: receiving a wafer having a plurality of semiconductor devices and a plurality of boundaries separating the semiconductor devices, each semiconductor device having at least one bonding pad; sawing the front of the wafer at a first boundary to establish a first kerf wherein the first kerf does not extend through the back of the wafer; coupling a bonding wire from a bonding pad on the front of a first semiconductor device to a bonding pad on the front of a neighboring semiconductor device, wherein a plurality of said first semiconductor devices and corresponding neighboring semiconductor devices form a plurality of semiconductor device groups; molding the front of the wafer with a non-conductive mold compound wherein the mold compound fills the first kerf and protects the bonding wire; sawing the back of the wafer at the first boundary to establish a second kerf opposite to the first kerf wherein the depth of the second kerf; molding the back of the wafer with a non-conductive mold compound wherein the mold compound fills the second kerf; grinding the back of the wafer to expose a plurality of bonding pads; plating the plurality of exposed bonding pads with a conductive material; and sawing the boundary around the semiconductor device groups to form a plurality of packaged devices, wherein a packaged device includes a first semiconductor device and one or more neighboring semiconductor devices coupled by one or more bonding wires.