Patent ID: 8484276

Claim:
A computer-implemented method for generating a single instruction, multiple data (SIMD) data structure tailored for processing fast Fourier transforms (FFTs) on a SIMD multi-core processor architecture, comprising: receiving input data, wherein the input data is a matrix having m rows and n columns; converting the input data into a SIMD format to produce converted data for simultaneous processing of s rows of the input data, wherein s is a power of two, wherein m and n are greater than and divisible by s, wherein the converted data includes a sequence of blocks, wherein each block includes s consecutive rows of the input data that are interleaved such that a set of each first element of the s consecutive rows immediately precedes a set of each second element of the s consecutive rows in terms of sequential memory addresses and such that the set of each second element of the s consecutive rows immediately precedes a set of each third element of the s consecutive rows in terms of sequential memory addresses, to produce s interleaved rows; and storing the converted data in sequential memory addresses, wherein a SIMD operation, comprising an FFT, is performed on the converted data.