Patent ID: 7395469

Claim:
A method for implementing deterministic based broken scan chain diagnostics using a computer test system connected to a Physical Failure Analysis system comprising the steps of: generating a deterministic test pattern using a base deterministic test pattern set generated by an Automatic Test Pattern Generation (ATPG) system; the deterministic test pattern being a predetermined Level Sensitive Scan Design (LSSD) pattern; utilizing all potential system functional paths and all system clocks on a device under test, loading the deterministic test pattern into each scan chain in the device under test in a system mode using lateral insertion of respective deterministic values of the deterministic test pattern into each of a plurality of latches of each said scan chain via system data ports and applying system clocks to capture the respective deterministic values in each of the plurality of latches of each said scan chain; unloading each scan chain and identifying a last switching latch in each said scan chain; repeating the generating, loading, unloading and identifying a last switching latch in each said scan chain testing steps a selected number of times with the deterministic test pattern; checking for consistent results of the identified last switching latch in each scan chain; and responsive to consistent results being identified, sending the identified last switching latch in each scan chain to said Physical Failure Analysis system to localize a physical defect; and responsive to consistent results not being identified, selecting another deterministic test pattern.