Patent ID: 8351496

Claim:
An integrated circuit having a filter apparatus for filtering a first symbol sequence, the first symbol sequence having a predetermined symbol duration, the apparatus comprising: at least one delay device clocked in accordance with a clock and configured to respectively delay a first symbol sequence by a delay time; at least one adapting device configured to receive the delayed first symbol sequence and to adapt the symbol sequence on the basis of filter coefficients, the at least one adapting device comprising a CML buffer for carrying out a voltage-current conversion of the delayed first symbol sequence where a filter coefficient is set using the current of the Current Mode Logic (CML) buffer; and where a relationship between the delay time of the delay device and a clock duration of the clocked delay device has a predetermined value which corresponds to a delay time which is half of the clock period, wherein the symbol duration of the first symbol sequence corresponds to the clock period of the clock signal of the clocked delay device.