Patent ID: 8499124

Claim:
A method of cache management in a victim cache in a cache hierarchy of a processor core, said method comprising: receiving a castout command identifying a victim cache line castout from another cache memory; thereafter, holding the victim cache line in a cache array of the victim cache; if said another cache memory is a higher level cache in the cache hierarchy of the processor core, updating a cache directory of the victim cache so that the victim cache line is less likely to be evicted by a replacement policy of the victim cache, and otherwise, updating the cache directory of the victim cache so that the victim cache line is more likely to be evicted by the replacement policy of the victim cache; and updating the cache directory to indicate a coherence state for the victim cache line based at least in part on a prior coherence state at said another cache memory received with the castout command, wherein said updating includes: updating the cache directory to indicate a first coherence state in response to a combined response of multiple snoopers to the castout command if the prior coherence state is the first coherence state; and updating the cache directory independently of the combined response if the prior coherence state is a second coherence state.