Patent ID: 7028164

Claim:
A data processor comprising: an instruction execution pipeline comprising N processing stages; and an instruction issue unit capable of fetching instructions into the instruction execution pipeline, the instructions fetched from an instruction cache associated with the data processor, each of the fetched instructions comprising from one to S syllables, the instruction issue unit comprising: a first buffer comprising S storage locations capable of receiving and storing the syllables associated with the fetched instructions; a second buffer comprising S storage locations capable of receiving and storing the syllables associated with the fetched instructions; and a controller capable of: determining if a first one of the storage locations in the first buffer is full; in response to a determination that the first one of the storage locations in the first buffer is full, causing a corresponding syllable in an incoming fetched instruction to be stored in a corresponding one of the storage locations in the second buffer; using a stop bit in a highest syllable of one of the instructions to determine whether every syllable of the instruction has been stored in the first buffer; in response to a determination that every syllable of one of the instructions has been stored in the first buffer, causing the syllables of the instruction to be transferred from the first buffer into at least one of a plurality of issue lanes leading into the instruction execution pipeline; determining if the syllable in the first one of the storage locations in the first buffer has been transferred from the first buffer to the instruction pipeline; and in response to a determination that the syllable in the first one of the storage locations has been transferred, causing the corresponding syllable stored in the corresponding one of the storage locations in the second buffer to be transferred to the first one of the storage locations in the first buffer; wherein the instruction issue unit is capable of fetching syllables from multiple cache lines of the instruction cache during a single fetch.