Patent ID: 7112487

Claim:
Method for fabricating a stacked capacitor array, which comprises a regular arrangement of a plurality of stacked capacitors, with a stacked capacitor being at a shorter distance from the respectively adjacent stacked capacitor in certain first directions than in certain second directions, comprising the following method steps: (a) providing of an auxiliary layer stack having first auxiliary layers with a predetermined etching rate and at least one second auxiliary layer with a higher etching rate on a substrate; (b) etching of in each case one hollow cylinder for each stacked capacitor through the auxiliary layer stack in accordance with the regular arrangement, with the auxiliary layer stack being left in place in intermediate regions between the hollow cylinders; (c) etching isotrophically of the second auxiliary layers to form widened portions of the hollow cylinders, without any second auxiliary layer being left in place between in each case two hollow cylinders which adjoin one another in the first direction and with a second residual auxiliary layer being left in place between in each case two hollow cylinders which adjoin one another in the second direction; (d) depositing conformally of an insulator layer in order to completely fill the widened portions; (e) depositing of a first electrode layer in the hollow cylinders in order to form the stacked capacitors; (f) filling of the hollow cylinders with a first filling; (g) removing of the first auxiliary layers, the second residual auxiliary layers and the first filling; and (h) completing of the stacked capacitor array.