Patent ID: 8713347

Claim:
A method comprising: receiving, by a logic element, a clock signal from a clock bus in between a first high impedance state and a second high impedance state entered into by the clock bus, the clock signal cycling over a plurality of clock cycles, and the logic element being in communication with a clock input of an electronic component; and communicating a masking signal from a storage element to the logic element to mask the clock input of the electronic component from the clock bus, the masking signal being communicated in response to: a transition of a control signal received at a first input of the storage element from a first logic state to a second logic state, wherein the control signal is received over the plurality of clock cycles in between the first high impedance state and the second high impedance state, and wherein, over the plurality of clock cycles, the transition of the control signal occurs within one clock cycle of a final transition of the clock signal before the clock bus enters the second high impedance state, and wherein the control signal is maintained in the first logic state until the transition occurs; and the final transition of the clock signal received at a second input of the storage element.