Patent ID: 7254064

Claim:
A NAND flash memory device comprising: a memory cell array having a plurality of memory cells, each memory cell being connected to a word line and a bit line; a word line voltage supply circuit for supplying a word line voltage to the word line; a page buffer for supplying a bit line voltage to the bit line to program a selected memory cell or read data from the selected memory cell; and a page buffer controller for supplying to the page buffer control signals for controlling the page buffer, wherein during a LSB program operation, the page buffer supplies the bit line with a first bit line voltage for programming or a second bit line voltage for program inhibit in response to LSB data and the control signals; wherein during a MSB program operation, the page buffer supplies the bit line with the second bit line voltage for program inhibit or the first and a third bit line voltage for programming in response to MSB data and the control signals; and wherein the third bit line voltage is between the first bit line voltage and the second bit line voltage.