Patent ID: 7384848

Claim:
A method for forming a flash memory with an inlaid floating gate, said method comprising: providing a substrate having a pad dielectric layer and a first dielectric layer on said pad dielectric layer thereon; transferring a buried diffusion region pattern into said first dielectric layer to expose said pad dielectric layer; forming a buried diffusion region in said substrate; forming a second dielectric layer over said substrate; etching back said second dielectric layer and said pad dielectric layer to expose said buried diffusion region and said first dielectric layer; etching said buried diffusion region to form trenches; forming shallow trench isolations in said trenches; transferring a floating gate pattern into said first and said second dielectric layers; removing said first dielectric layer to expose a portion of said pad dielectric layer; removing said exposed pad dielectric layer to expose said substrate; forming a tunnel dielectric layer on said exposed substrate; forming a first conductive layer on said tunnel dielectric layer and said substrate; planarizing said first conductive layer to expose said shallow trench isolations; forming an inter gate dielectric layer on said first conductive layer and said shallow trench isolations; and forming a second conductive layer on said inter gate dielectric layer.