Patent ID: 8467342

Claim:
A shared memory switch, comprising: a plurality of ports configured to receive and transmit frames of data; frame classification circuitry configured to classify the frames into a plurality of traffic classes; frame memory configured to store the frames, the frame memory including a plurality of shared memory partitions, each of the shared memory partitions corresponding to one or more of the traffic classes, each of the shared memory partitions having a plurality of counters associated therewith, the plurality of counters including at least one per port memory usage counter for each of the plurality of ports and at least one aggregate memory usage counter, the counters associated with each of the shared memory partitions being independent of the counters associated with others of the shared memory partitions; and congestion management circuitry configured to implement congestion management policies for each of the partitions independently with reference to the counters associated with each of the partitions, wherein the congestion management circuitry is further configured to generate and transmit class-specific pause frames to selected ones of the ports with reference to at least some of the counters, and wherein the shared memory switch further comprises egress scheduling circuitry configured to facilitate transmission of the frames, the egress circuitry further being configured to pause transmission of selected ones of the frames corresponding to specific ones of the traffic classes in response to downstream congestion corresponding to the specific traffic classes.