Patent ID: 7929352

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells, each of the memory cells being connected to a word line, a bit line and a source line and storing a plurality of bits by setting the word line to one of a first level, a second level, and an nth level (n: natural number more than 3); and first and second select gates, each of the memory cells being connected to the bit line and the source line by the first and second select gates, respectively, wherein when data is read from a memory cell, the bit line is precharged and the word line is set to i level (i: voluntary level of n) and then, the first and/or second select gates are turned on, data of the memory cell is read by i level; then the first and second select gates are turned off, the word line is set to j level (j: voluntary level of n, j≠i) and, then the first and/or second select gates are turned on, data of the memory cell is read by j level.