Patent ID: 8421130

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; at least one isolation layer formed in the semiconductor substrate, the at least one isolation layer separating a first device area and a second device area; a gate dielectric layer formed over the semiconductor substrate and the at least one isolation layer; and a conductive gate layer formed over the gate dielectric layer; and a silicide layer formed over the conductive gate layer, wherein: the first device area comprises a first MOS transistor comprising: N-type or P-type impurity ions implanted in the conductive gate layer; a first dosage of impurity ions other than N-type or P-type implanted in the conductive gate layer; a source having a second dosage of impurity ions other than N-type or P-type implanted therein, the second dosage being less than half the first dosage; and a drain having the second dosage of impurity ions other than N-type or P-type implanted therein; and the second device area comprises a second MOS transistor serially coupled to the first MOS transistor formed in the first device area, comprising: N-type or P-type impurity ions implanted in the conductive gate layer, wherein the type of impurity ions implanted in the conductive gate layer in the first device area is different than the type of impurity ions implanted in the conductive gate layer of the second device area, and wherein the conductive gate layer is free of the impurity ions other than N-type or P-type in the second device area; and a source and a drain, the source and drain of the second MOS transistor being free of the impurity ions other than N-type or P-type.