Patent ID: 7054802

Claim:
A hardware-assisted design verification system for verifying a target logic circuit design, said verification system having a host workstation in communication with a hardware accelerator, the target logic circuit design comprising Boolean logic gates, registers and memories, the host workstation loading data to or unloading data from the registers and memories, comprising: protocol logic synthesized into the target logic circuit design, said protocol logic comprising: an incoming packet register in communication with said host workstation, said incoming packet register storing packets that include data and commands communicated from the host workstation; an outgoing packet register in communication with said host workstation, said outgoing packet register storing packets that include data to be communicated to the host workstation; command decode logic, said command decode logic decoding said commands in said incoming packet register to identify a particular operation, register or memory location in said target logic circuit design, where said particular operation can comprise a write command and where said particular operation can also comprise a read command; write command execution logic to write data stored in said incoming packet register into said register or memory location in said target logic circuit design for a write command decoded at said command decode logic; read command execution logic to read data from said register or memory location in said target logic circuit design and store said data in said outgoing packet register for a read command decoded at said command decode logic; and interface logic interfacing said registers and memories in said target logic circuit design.