Patent ID: 6909636

Claim:
A flash memory system comprising: an array of flash memory cells; a first local bit line coupled to a first column of flash memory cells; a second local bit line coupled to a second column of flash memory cells; a third local bit line coupled to a third column of flash memory cells; a fourth local bit line coupled to a fourth column of flash memory cells, wherein the first, second, third and fourth local bit lines are positioned generally parallel with each other; a first global bit line; a second global bit line; first, second, third and fourth select transistors, the first select transistor is coupled to the first local bit line and the first global bit line, the second select transistor is coupled to the second local bit line and the second global bit line, the third select transistor is coupled to the third local bit line and the first global bit line, the fourth select transistor is coupled to the fourth local bit line and the second global bit line, wherein the first and third select transistors are located at opposite ends of the array from the second and fourth select transistors; a first select line to activate the first and second select transistors; and a second select line to activate the third and fourth select transistors.