Patent ID: 7350056

Claim:
A method of operating a processor comprising: fetching instructions from a memory, by an instruction fetcher, thus providing fetched instructions; decoding the fetched instructions, by a decoder, the decoder providing decoded instructions to an issue queue that includes a main queue array of storage cells arranged in rows and columns and a side queue array of storage cells arranged in rows and columns, the side queue array including an issue row that issues instructions from the main queue array or the side queue array for out-of-order execution by executions units, each row of the side queue array being capable of receiving instructions from a respective row of the main queue array to enable bypassing of instructions in the main issue queue array in the event of a stall in the main issue queue array; storing, by the main queue array, the decoded instructions in the rows and columns of the main queue array for out-of-order issuance to execution units by the issue row of the side queue array; determining, by the issue queue, if the main queue array is stalled by a first instruction that is not ready-to-issue in one of the rows of the main queue array, the issue queue searching other rows of the main queue to locate a second instruction that is ready-to-issue out-of-order with respect to the stalled first instruction bypassing the stalled first instruction in a particular row of the main queue array by the issue queue forwarding the second instruction in another row of the main queue array to a respective corresponding row of the side queue array for later issuance by the issue row of the side queue array to an execution unit for out-of-order execution while the stalled first instruction remains in the main queue array; wherein the storage cell rows of the main queue array are recursively configured red with respect to one another, and wherein the storage cell rows of the side queue array are recursively configured with respect to one another.