Patent ID: 8516412

Claim:
A method for physically synthesizing a design of an integrated circuit, the method comprising: compiling a logical description of the design into a flattened netlist; extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, wherein the extracting comprises: assigning gates in the flattened netlist to one or more logic modules, wherein the assigning comprises: marking those of the gates that carry hierarchical information with an identifier that indicates one of the one or more logic modules corresponding to the hierarchical information; and grouping those of the gates that are marked with a common identifier into a common one of the one or more logic modules; and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy, wherein at least one of: the compiling, the extracting, or the placing is performed using a processor.