Patent ID: 7870449

Claim:
A testing circuit for the testing of an integrated circuit core or circuitry external to an integrated circuit core, the testing circuit comprising: a shift register circuit for storing testing instruction data, the shift register circuit comprising a plurality of stages, each stage comprising: a serial input and a serial output; a first shift register storage element for storing a signal received from the serial input and providing the signal to the serial output in a scan chain mode of operation; and a second parallel register storage element for storing a signal from the first shift register storage element and providing the signal to a parallel output in an update mode of operation, wherein the testing circuit further comprises a multiplexer for routing either a serial test input to the serial input of the shift register circuit or an additional input into the serial input of the shift register circuit, wherein the testing circuit further comprises a first input for controlling a first update mode of operation, and a second update mechanism for use when the additional input is routed to the serial input, and wherein the second update mechanism is provided by a control circuit which responds to a specific value of data stored in at least one stage of the shift register to generate an update signal for setting the other shift register stages into the update mode of operation.