Patent ID: 8612508

Claim:
A system comprising: one or more hardware components, associated with a first compressor in a first layer, to: receive, via a first bus associated with the first compressor, a first input from a second compressor, the second compressor being in a second layer, and the second layer being different from the first layer, receive, via a second bus associated with the first compressor, a second input from the second compressor, receive, via a third bus associated with the first compressor, a third input from a third compressor, the third compressor being in a third layer, the third layer being different from the first layer and the second layer, the second compressor receiving one or more inputs from a fourth compressor, the fourth compressor being in a fourth layer, the fourth layer being different from the first layer, the second layer, and the third layer, and the first input, the second input, and the third input having a predetermined width, compute a one's complement sum of the first input, the second input, and the third input to generate carry bits having the predetermined width and sum bits having the predetermined width, move a most significant bit of the carry bits to a least significant bit position to obtain modified carry bits, output the sum bits via a fourth bus associated with the first compressor, and output the modified carry bits via a fifth bus associated with the first compressor.