Patent ID: 7532701

Claim:
A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of the plurality of stages comprising: a pull-up transistor controlled by a first node to apply a first clock signal to an output line; a first pull-down transistor controlled by a second node to apply a first driving voltage to the output line; a controller for controlling the first and second nodes; and a compensating capacitor connected between the first node and an input line of a second clock signal, the second clock signal being different from the first clock signal, wherein the controller includes: a first transistor for applying the start pulse to the first node in response to the second clock signal; a second transistor for applying a second driving voltage to the second node in response to the second clock signal; a third transistor for applying the first driving voltage to the second node in response to the first clock signal; and a fourth transistor for applying the first driving voltage to the third transistor in response to a voltage at the first node.