Patent ID: 8319347

Claim:
An electronic device package, comprising: a wafer, containing a chip, wherein the chip has a first surface and an opposite second surface; a plurality of conductive electrodes disposed on or over the first surface of the chip a plurality of contact holes formed in the chip to expose the conductive electrodes; at least one recess disposed in the chip and apart from the side of the chip by a distance, wherein the at least one recess extends along a direction from the second surface to the first surface of the chip; the plurality of contact holes disposed at a bottom of the at least one recess to expose contact surfaces of corresponding conductive electrodes, wherein the plurality of contact holes are disposed at the bottom of a single recess; an insulating layer, covering the second surface of the chip and extending to a sidewall and the bottom of the at least one recess, wherein the contact holes are disposed in the insulating layer; and a plurality of conductive trace layers disposed on the insulating layer, wherein each of the conductive trace layers extend from the second surface to the sidewall and the bottom of the at least one recess and extend to the contact surface of the conductive electrode through the corresponding contact hole, and width of the conductive trace layers is smaller than a width of the corresponding conductive electrodes as measured in the same direction.