Patent ID: 7338849

Claim:
A method of fabricating a semiconductor device, the method comprising: forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate; forming a plurality of first conductive layer patterns on the active regions, the first conductive layer patterns being spaced apart from each other in a lengthwise direction of the active regions and respectively including at least four sidewalls substantially perpendicular to the semiconductor substrate and an upper surface therebetween; conformally forming an insulating layer on the semiconductor substrate and on the at least four sidewalls and the upper surface therebetween of ones of the first conductive layer patterns; forming a second conductive layer on the insulating layer; and patterning the second conductive layer until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns, the second conductive layer patterns crossing the active regions and the isolation layer to overlap the first conductive layer patterns.