Patent ID: 7867848

Claim:
A method for fabricating a dual bit memory device, the method comprising: fabricating a charge trapping stack overlying a substrate, wherein the charge trapping stack comprises a tunnel oxide layer, a charge trapping layer overlying the tunnel oxide layer, and an insulating layer overlying the charge trapping layer; forming a plurality of sacrificial members overlying the charge trapping layer; etching isolation openings within the charge trapping layer between adjacent sacrificial members of the plurality of sacrificial members; globally depositing an oxide layer overlying the plurality of sacrificial members, within the isolation openings, and overlying portions of the charge trapping layer; forming a plurality of control gates overlying each of the isolation openings; removing the plurality of sacrificial members; etching portions of the oxide layer and the charge trapping layer that do not underlie the plurality of control gates; and forming a plurality of impurity doped bitline regions within the substrate using the plurality of control gates as a mask.