Patent ID: 7389318

Claim:
A data processing apparatus comprising: receiving means for receiving data; separating means for separating said data received by said receiving means into a first data item and a second data item; first storing means for storing said first data item; second storing means for storing said second data item; first processing means for decoding said first data item; second processing means for decoding said second data item; generating means for generating a first and a second clock for use by said first and said second processing means in processing said first data item and said second data item respectively; first controlling means for raising a frequency of said first clock if a data size of said first data item stored in said first storing means is higher than a first reference value, said first controlling means further lowering the frequency of said first clock if the data size of said first data item is lower than a second reference value; and second controlling means for raising the frequency of said second clock if the data size of said second data item is higher than a third reference value, said second controlling means further lowering the frequency of said second clock if the data size of said second data item is lower than a fourth reference value; wherein, if there occurs a difference in total processing time between a transmission block and a reception block handling said first data item and said second data item, and if Buf 1 is assumed to denote a data size processible by said first processing means and Buf 2 to represent an average value of said first reference value and said second reference value, then said first controlling means causes a center value of a controllable range of data sizes accommodated by said first storing means to correspond to a sum of Buf 1 and Buf 2 .