Patent ID: 8436719

Claim:
A network device, comprising: a network module operable to implement network functions of the network device; a status displaying module operable to receive displaying signals from the network module, to indicate operating status of the network device using a plurality of displaying signal transmission lines connecting the network module and the status displaying module; a processor operable to direct the network module to implement the network functions; a power providing module operable to provide power for the processor, the network module, and the status displaying module; and a power saving circuit coupled to the plurality of displaying signal transmission lines connecting the network module and the status displaying module, and operable to couple the displaying signals transmitted to the status displaying module from the network module to obtain coupled signals and to control modes of the processor and the power providing module according to existence of the coupled signals, wherein the power saving circuit comprises: a signal inputting module operable to input the coupled signals; a transistor, wherein the base of the transistor is connected to the signal inputting module, the emitter of the transistor is connected to the ground, and the transistor is on upon the condition that the coupled signals are present and off upon the condition that no coupled signals are present; and a voltage dividing module operable to receive logic signals from general purpose input output (GPIO) ports of the network device, connected to the emitter of the transistor, operable to output a controlling signal according to the transistor and the logic signals so as to control modes of the processor and the power providing module, wherein the voltage dividing module comprises: a first dividing resistor operable to receive a first logic signal from a first GPIO port of the network device; a second dividing resistor operable to receive a second logic signal from a second GPIO port of the network device; a dividing capacitor, wherein one end of the dividing capacitor is connected to the first dividing resistor and the second dividing resistor, and another end of the dividing capacitor is connected to the ground; and a third dividing resistor, wherein one end of the third dividing resistor is connected to the first dividing resistor and the second dividing resistor, another end of the third dividing resistor is connected to the emitter of the transistor.