Patent ID: 7587579

Claim:
A method comprising: providing a processor core architecture having a register file and predefined first and second computation and bit-manipulation functional units having access to said register file; and providing an arbitrary functional unit external to said processor core architecture and coupled to said first and second functional units, said arbitrary functional unit having access to said register file; receiving an instruction packet that includes an instruction for said arbitrary functional unit; selecting based on data within the instruction packet which of the first and second computation and bit-manipulation functional units is to control the access of the arbitrary functional unit to the register file; executing the instruction by the arbitrary functional unit and controlling, by the first computation and bit-manipulation functional unit, writing a result of the execution in the register file when the first computation and bit-manipulation functional unit is selected; and executing the instruction by the arbitrary functional unit and controlling, by the second computation and bit-manipulation functional unit, writing a result of the execution in the register file when the second computation and bit-manipulation functional unit is selected.