Patent ID: 8111568

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; and a bit test circuit configured to perform a parallel bit test to determine defective memory cells, the bit test circuit including a plurality of data input/output terminals operationally coupled to the plurality of memory cells, wherein the bit test circuit is configured to ignore a first data provided to at least one data input/output terminal and perform the parallel bit test for a second data provided to remaining input/output terminals, and the bit test circuit includes a plurality of comparators coupled to each of the plurality of input/output terminals, each of the comparators includes, a first input configured to receive data from the data input/output terminal, a second input configured to receive expected data from a tester, and a third input coupled to an output of a mode register, the third input is configured to receive a mode register set signal, the comparators are configured to output a non-defective pass signal for ignored data based on at least one of the data, the expected data and the mode register set signal.