Patent ID: 7675308

Claim:
An on-chip test circuit for testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, the on-chip test circuit comprising: a flip-flop, for serially receiving, registering and serially outputting test patterns; a mode selector, coupled to the power switch and the flip-flop, for controlling operation mode of the power switch according to a test indication signal, the test indication signal indicates whether the power switch is in test mode or not; and a voltage level control circuit, coupled to the decoupling capacitance, for controlling voltage level of the decoupling capacitance; wherein under test mode, the mode selector selects the test patterns serially output from the flip-flop into the power switch and the voltage level control circuit pre-charges or discharges the decoupling capacitance, so that the voltage level of the decoupling capacitance is analyzed for determining whether the power switch is passed or failed.