Patent ID: 8817523

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array including one or more first wires, one or more second wires crossing the first wire, and one or more memory cells connected to both the wires at a crossing portion of the first wire and the second wire, the memory cell including a variable resistance element storing data in a non-volatile manner by a resistance value; and a control circuit setting the variable resistance element in a first resistance state by application of first voltage to the memory cell, setting the variable resistance element in a second resistance state by application of second voltage to the memory cell, and reading data from the memory cell by application of third voltage to the memory cell, the control circuit applying to the memory cell at predetermined timing weak write voltage causing the variable resistance element to be held in the first resistance state and the second resistance state, and the weak write voltage being set in a range between a maximum value and a minimum value of two or more read voltages to be used at the time of read operation.