Patent ID: 8731688

Claim:
A processing apparatus, comprising: a memory a first processor that is coupled to the memory and executes a first procedure including: executing a program including a plurality of instructions; issuing a first command, complying with a first command system, by executing the program upon detecting a second command, complying with a second command system different from the first command system, for starting a process to issue the first command; recording an operation log about an operation corresponding to the plurality of instructions in the memory in response to the first command; and a second processor that is coupled to the memory and executes a second procedure including issuing a third command complying with the first command system to instruct recording the operation log about the operation corresponding to the plurality of instructions in the memory, wherein, when both the first command and the third command are issued, the third command is executed on a priority basis, a notification for notifying of non-executing of the first command is issued, and the first processor reissues the first command.