Patent ID: 8448097

Claim:
A method for checking a set of layout design rules on a region of an integrated circuit layout, the layout including a plurality of physical shapes each specific to a layer of the layout and each having layout corners at respective locations in the layout, for use by a computer system having access to a design rule data set indicating a particular derivation operator for deriving derived shape information for a particular derived layer in dependence upon at least two of the layout layers, the design rule data set further indicating constraint values of design rules in the data set including a particular design rule referencing the particular derived layer, the method comprising the steps of: the computer system deriving shape information for the particular derived layer in dependence upon the particular derivation operator, the derived shape information indicating at least one derived corner location in the particular derived layer; the computer system traversing a plurality of shape corners in the region including corners in at least two locations and including the derived corner; for each corner in at least a subset of at least two of the corners traversed, the computer system populating a layout topology database with values in dependence upon the respective corner location, the subset including corners in at least two locations and including the derived corner; after the layout topology database has been populated with values in dependence upon the corner locations of all corners in the subset, the computer system comparing values in the layout topology database to values in the particular design rule to detect any violations; and where a design rule violation is detected, reporting it to a user.