Patent ID: 7911246

Claim:
A DD *Delay Locked loop) circuit for delaying a reference clock according to a level of a control voltage, comprising: a clock selection control unit configured to generate a clock selection signal on the basis of a phase comparison signal and, after the clock selection signal is generated, to generate an initialization signal; a delay control unit configured to, when the initialization signal is enabled, transfer an initial voltage that is generated by dividing an external power supply voltage to a delay unit as the control voltage, and control a delay operation of a delay reference clock to be selected on the basis of the clock selection signal; and an initial voltage generate unit configured to generate the initial voltage from the external power supply voltage according to whether or not the initialization signal is enabled and to transfer the initial voltage to the delay control unit, wherein the initial voltage generate unit comprises: a voltage dividing section configured to divide the external power supply voltage according to a resistance ratio so as to generate one or more divided voltages; a switching section configured to receive the one or more divided voltages and output the initial voltage according to whether or not the initialization signal is enabled; a clock input unit configured to receive an external clock thereby outputting the reference clock; a clock divide unit configured to divide a phase of the reference clock to output a plurality of divided clocks; and a first phase compare unit configured to compare the phase of the reference clock with a phase of the feedback clock thereby generating the phase comparison signal.