Patent ID: 7460062

Claim:
A signal processing apparatus comprising: AD clock generating means for generating an AD clock used for sampling of AD conversion to generate a plurality of AD clocks that are equal in frequency and different in phase; a plurality of AD converting means each of which inputs the AD clocks that are different in phase from each other for AD converting an analog signal into digital signals at a timing of inputted AD clock; a plurality of first storage means for storing data of respective AD conversion results that are converted by the respective AD converting means at a timing of the same clock as any one of the AD clocks that are inputted by the respective AD converting means, separately; a plurality of second recording means for storing respective data that are stored by the respective first recording means at a timing of the same clock as the clock used in one of AD converting means, separately; data reading/writing means that executes writing and reading of data for writing the respective data stored by the respective second recording means as a group of data at a timing of the same clock as the clock used in the plurality of second recording means, and divides the group of written data into the respective data for reading the respective data at a timing of the different clock from the clock used in writing the data in the number of times corresponding to the number of divided data; and signal processing means for executing given signal processing by using the respective data read by the data reading/writing means at a timing of the same clock as the clock used in reading the data by the data reading/writing means.