Patent ID: 7456468

Claim:
A semiconductor memory device comprising: a first dopant area and a second dopant area, the first dopant area and the second dopant areas disposed in a semiconductor substrate; an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including an amorphous material comprising at least one of an Hf silicate, a Zr silicate, a Y silicate, and a Ln silicate; and a gate electrode layer disposed on the insulating layer, wherein the insulating layer comprises: a tunneling oxide layer disposed in contact with the first dopant area and the second dopant area; a data storing layer disposed on the tunneling oxide layer; and a blocking oxide layer disposed on the data storing layer, wherein the tunneling oxide layer consists of the amorphous material having the chemical formula ((Hf, Zr, Y or Ln)O 2 ) x (SiO 2 ) 1−x , where (0.03≦x≦0.26).