Patent ID: 7560340

Claim:
A method of manufacturing a flash memory device, the method comprising: forming a tunnel oxide layer and a conductive layer for a floating gate on a semiconductor substrate; etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form trenches; gap-filling the trenches with an insulating layer to form isolation layers; polishing the isolation layers to expose a top surface of the conductive layer; etching the isolation layers to lower an effective field oxide height (EFH) to a top surface of the tunnel oxide layer; forming sidewalls on sidewall parts of the conductive layer; etching the isolation layers up to a region below the tunnel oxide layer using the sidewall parts as masks; stripping the sidewall parts and performing an etch process in order to widen an opening part of each isolation layer and increase the height of the sidewalls of the exposed conductive layer; and forming a dielectric layer and a second conductive layer for a control gate on the entire surface.