Patent ID: 8913423

Claim:
An apparatus comprising: a memory cell comprising a magnetic tunnel junction (MTJ) structure coupled between a bit line and a source line, the MTJ structure including: a free layer coupled to the bit line; and a pinned layer, wherein a magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state, wherein the pinned layer has a physical dimension to produce an unbalanced offset magnetic field, wherein the physical dimension is associated with a switching current ratio of the MTJ structure, wherein the unbalanced offset magnetic field corresponds to a first switching current through the MTJ structure to enable switching from the first state to the second state when a first voltage is applied to the bit line, and wherein the unbalanced offset magnetic field corresponds to a second switching current through the MTJ structure to enable switching from the second state to the first state when the first voltage is applied to the source line.