Patent ID: 7886090

Claim:
A device having under-run management capabilities, the device comprises: a processor; a memory unit; a direct memory access controller; multiple information frame transmitters; multiple buffers coupled to the multiple information frame transmitters and to multiple under-run logics; wherein each buffer is adapted to store a fraction of a maximal sized information frame; wherein a certain under-run logic out of the multiple under-run logics is coupled to a certain buffer out of the multiple buffers, and to a certain information frame transmitter out of the multiple information frame transmitters; and wherein the certain under-run logic is adapted to: (i) detect an occurrence of a buffer under-run associated with a transmission attempt of a certain information frame from the certain buffer, (ii) instruct the certain frame transmitter to transmit predefined packets until a last packet of the certain information frame is retrieved from the certain buffer and (iii) send to the processor an under-run indication after at least one predefined packet was transmitted; wherein the certain under-run logic is adapted to detect the occurrence of the buffer under-run if the last packet that belongs to the certain information frame was not retrieved from the certain buffer, if the certain frame transmitter expects to receive information from the certain buffer and if a buffer fullness level reaches a predefined minimal level.