Patent ID: 8155256

Claim:
A method for asynchronous retiming using a clock signal (FREF), and an oversampling clock signal (CKV), comprising the steps of: sampling the FREF using both the rising and falling edges of the CKV to produce first and second retimed FREF signals; selecting from either the first or second retimed FREF signals one that provides a predetermined level of metastability; wherein the sampling step comprises sampling by the rising edges of the CKV using a first clocked memory element and sampling by the falling edges of the CKV using a second clocked memory element; wherein the sampling step produces both rising and falling edge retimed signal paths, and choosing from either the rising or falling edge signal paths, the signal path that is furthest away from metastability; and wherein the choosing step is performed by a midedge detector that comprises a time-to-digital converter (TDC) that is clocked by the FREF.