Patent ID: 8809829

Claim:
A method for manufacturing an integrated circuit, comprising: providing an array of phase change memory cells on an integrated circuit substrate, the phase change memory cells having respective first and second electrodes with active regions within bodies of phase change material having a bulk stoichiometry between the first and second electrodes; providing bias circuitry to set and reset the phase change memory cells in the array by applying set and reset pulses to cause the phase change memory cells to transform to a set state resistance or a reset state resistance; and applying forming current after forming the first and second electrodes to the phase change memory cells in the array to form a phase change material in the respective active regions having a modified stoichiometry, the modified stoichiometry in the respective active regions being different than the bulk stoichiometry outside the respective active regions and between the first and second electrodes, the forming current being induced by a forming pulse that is different from the set pulse and different from the reset pulse, and applied before the set and reset pulses are applied, wherein said applying forming current includes applying a pulse having a duration greater than 0.5 milliseconds, or a pulse having a current magnitude sufficient to cause a temperature in the active region greater than a melting temperature for the phase change material for a first duration, with a sloped trailing edge in which the current magnitude drops over a time interval significantly greater than a quench cutoff for the phase change material.