Patent ID: 7299461

Claim:
A method to create an expansion syntax for semiconductor design software that allows a single complex software code expression that represents multiple logic gates to be expanded into one or more simple software code expressions that individually represent a single logic gate, comprising: embedding a list construct within a software code expression wherein said list construct includes an expansion syntax indicator comprising a pair of brackets enclosing a plurality of list parameters wherein said list parameters identify list members and wherein said list members comprise ordered integers within the range of integers identified by a start integer, an end integer, and optionally a count integer, a step integer and or a skip integer to indicate a count of integers to step or skip during expansion, wherein said list construct further comprises one or more iterators used as an operator acting upon a parameter list to expand the list members, and wherein the list is grouped as a default list name or a explicit list name; interpreting said list construct within said software code expression according to one of said iterator and said list member expansion syntax using an expansion function; and expanding using said expansion function said list construct within said software code expression to create a set of expanded expressions, said expanding further comprising: where one of said software code expressions contains only one unique iterator, said one code expression is expanded as the list size associated with said one unique iterator; or where said software code expression contains more than one unique iterator, said one code expression is expanded as the cross product of the list sizes associated with each unique iterator; wherein the cross product is defined according to the relationships between the skip and stride definitions of said iterators, if any, or as a full cross product otherwise.