Patent ID: 8810948

Claim:
An apparatus comprising: read channel circuitry; and signal processing circuitry associated with the read channel circuitry, the signal processing circuitry comprising: an equalizer having an input coupled to an output of an analog-to-digital converter, the equalizer being configured to determine an equalized digital data signal from an oversampled digital data signal; a filter having an input coupled to an output of the equalizer, the filter being configured to filter the equalized digital data signal; a detector having an input coupled to an output of the filter, the detector being configured to determine a hard decision and reliability of the filtered digital data signal; and a decoder having an input coupled to an output of the detector, the decoder being configured to decode the filtered digital data signal based at least in part on the hard decision and reliability; wherein the equalizer is configured: to receive the oversampled digital data signal comprising a first set of sampled digital data and a corresponding second set of sampled digital data, where samples in the first set of sampled digital data are offset from corresponding ones of the samples in the second set of sampled digital data by a phase difference; and to combine one or more samples from the first set of sampled digital data with respective corresponding ones of the samples in the second set of sampled digital data to determine the equalized digital data signal.