Patent ID: 7681153

Claim:
A method for estimating a static power consumption of an integrated circuit, the method comprising: dividing the integrated circuit into at least one cell; characterizing a static power consumption of the at least one cell based on a contribution of at least one input node and a contribution of at least one output node of the cell, each contribution representing a multiplication of a leakage coefficient and a probability of the at least one input node and the at least one output node; determining a value of the leakage coefficient of the at least one input node and the at least one output node; determining a value of the probability of the at least one input and at least one output node; and calculating the static power consumption of the cell to determine the static power consumption of the integrated circuit using a computer; wherein the leakage coefficient of the at least one input node and at least one output node is determined as a coordinate of an orthogonal projection of a vector representing the static power consumption of the cell into a base of vectors representing the at least one input node, the at least one output node and a constant; and replacing a gate netlist of the cell with a logic gate template by adding an internal node besides the input node and the output node of the cell.