Patent ID: 7417319

Claim:
A semiconductor device comprising: a semiconductor substrate; a lower interconnect layer having a height measured orthogonally from said substrate and a width measured parallel to an upper surface of said substrate, said width being greater than said height, said lower interconnect layer comprised of a first barrier metal layer, an interconnect metal layer formed contacting the first barrier metal layer, and a second barrier metal layer formed contacting the interconnect metal layer; an interlayer dielectric formed contacting said second barrier metal layer; a first via opening and a second via opening located within said interlayer dielectric and extending into said second barrier metal layer, the second via opening formed with a larger bottom area than a bottom area of the first via opening; a first via of conductive material filling said first via opening and a second via of the conductive material filling said second via opening, a bottom area of the first via being less than a bottom area of the second via; and an upper interconnect layer including a third barrier metal layer contacting said interlayer dielectric, a second interconnect metal layer contacting said third barrier metal layer, and a fourth barrier metal layer contacting said third barrier metal layer, said upper interconnect layer formed contacting said first via and free of contact with said second via so that said lower interconnect layer and said upper interconnect layer are electrically connected through the first via and not electrically connected through said second via, said first via and said second via being electrically connected by said lower interconnect layer.