Patent ID: 7462904

Claim:
A non-volatile memory device comprising: an upwardly protruding fin disposed on a substrate; a control gate electrode crossing the fin; a floating gate including a first storage gate and a second storage gate interposed between the control gate and the fin, the first storage gate disposed on a sidewall of the fin, and the second storage gate being disposed on a top surface of the fin and connected to the first storage gate; a first insulation layer and a second insulation layer, the first insulation layer interposed between the first storage gate and the sidewall of the fin, and the second insulation layer is thinner than the first insulation layer and interposed between the second storage gate and the top surface of the fin, wherein at a write or erase operation, the second insulation layer has a thickness sufficient to allow tunneling of charges and the first insulation layer has a thickness sufficient to suppress tunneling of charges; and a blocking insulation layer interposed between the control gate electrode and the floating gate.