Patent ID: 7115477

Claim:
A method for fabricating a gate with dual gate dielectric layer, comprising: providing a semiconductor substrate, with a dielectric layer, a hard mask layer, and a patterned photoresist layer with a first opening sequentially formed thereon, wherein the first opening exposes the hard mask layer; etching the hard mask layer to form a second opening using the patterned photoresist layer as a mask; removing the patterned photoresist layer; conformally forming an insulating layer over the hard mask layer and the second opening; anisotropically etching the insulating layer to form a spacer on a sidewall of the second opening; implanting nitrogen ions into the semiconductor substrate using the hard mask layer and the spacer as masks; removing the spacer and the exposed dielectric layer; and thermally oxidizing the semiconductor substrate to form a gate oxide layer over a bottom of the second opening using the hard mask layer as a mask.