Patent ID: 8145902

Claim:
An apparatus, comprising: a plurality of processors capable of being operatively coupled to a main memory that includes a plurality of sandboxes, each processor including an associated local memory and being operable to request at least some data from the main memory for use in the local memory, each processor having at least one of the sandboxes associated therewith; and at least one main processor operable to control access by the processors to data within the main memory, within the processors, and to permit or deny access by the processors to data within the respective sandboxes, wherein: the plurality of processors are each operable to enter a plurality of programmable modes, including: (i) a normal mode of operation in which requests initiated by others of the processors for data transfers into or out of the given processor are serviced, subject to the access controlled by the main processing unit; and (ii) a secure mode of operation in which no requests initiated by others of the processors for data transfers into or out of the given processor that has entered the secure mode are serviced, but such transfers initiated by the given processor are serviced subject to the access controlled by the main processing unit, the main processing unit is operable to establish a special secure relationship between one processor that has entered the secure mode of operation and a further processor that has entered the normal mode of operation, in which the main processing unit excludes access to data in a sandbox of the main memory that is associated with the further processor by others of the processors, even when such other processors are in the secure mode of operation, but permits access to the data in the sandbox of the main memory that is associated with the further processor by the one processor that is in the secure mode, and the main processor is operable to monitor data within all processors except the one processor in the secure mode of operation.