Patent ID: 8543368

Claim:
A method for testing a switch device, comprising: receiving, by a processor, logic constraints for modeling switching circuitry of the switch device, the logic constraints being configured to correlate egress ports of the switch device as logic functions of packets input to the switch device; receiving, by the processor, a predetermined egress port that constrains a desired egress port from which the input packets are output from the switch device; and determining, by the processor, at least one set of parameter values including at least ingress port identifications for inputting packets to satisfy the logic constraints and the egress port constraint, wherein the determining includes using a constraint solving problem (CSP) engine to solve a circuit model having an input interface, a first stage, a first-second interface, a second stage, a second-third interface, and an output interface, each of the stages being configured to receive stage inputs from an interface coupled to a previous stage, and provide stage outputs to an interface coupled to a next stage.