Patent ID: 8300003

Claim:
A driver comprising: a plurality of data output units configured to output data based on a plurality of clock signals, respectively; and a multi-phase clock generator configured to, receive a master clock signal to generate the plurality of clock signals with identifiers, the plurality of clock signals having a same frequency as the master clock signal and different phases in a period of the master clock signal and configured to provide the plurality of clock signals to the respective data output units, the identifiers identifying the plurality of data output units, and provide a second clock signal of the plurality of clock signals to an (i+j)th data output unit if a first clock signal of the plurality of clock signals is provided to an (i)th data output unit, i being a natural number, and j representing a delta value and being a natural number greater than one, wherein a number of the plurality of clock signals corresponds to a number of the plurality of data output units, and the plurality of clock signals including the first clock signal and the second clock signal are immediately adjacent sequentially generated.