Patent ID: 8582361

Claim:
A nonvolatile semiconductor memory comprising: a memory cell array including first and second blocks; a first driver; the first block comprising a first cell unit including a selected memory cell and a first select gate transistor, and a second cell unit including an unselected memory cell and a second select gate transistor; a bit line to which the first and the second cell units are connected; and a word line electrically connected to a memory cell in the first cell unit and connected to a memory cell in the second cell unit, wherein a read operation is performed with a first step and a second step, wherein, in the first step, a ground voltage is applied to the bit line, a first voltage is applied to the first select gate transistor, and a second voltage is applied to the second select gate transistor, the first and second voltages being higher than the ground voltage, wherein, in the second step, the ground voltage is applied to the second select gate transistor, the first voltage is applied to the first select gate transistor, a third voltage is applied to the bit line, and a read voltage or a transfer voltage higher than the read voltage is applied to the word line in the first block, the third voltage being higher than the ground voltage.