Patent ID: 8482316

Claim:
A circuit comprising: a keeper circuit operable to supply current to a leaker circuit to compensate for a first current leakage in first NMOS transistors of the leaker circuit; and a controller operable to provide a control signal to the keeper circuit, wherein the control signal is based on the first current leakage in the leaker circuit, wherein the control signal is a pulse having a first value during a first period, a second value during a second period, and a duration of a clock cycle, wherein the keeper circuit provides a current to the leaker circuit during the first period and the keeper circuit withholds the current to the leaker circuit during the second period, wherein durations of the first period and the second period are based on the first current leakage, wherein the controller further includes a delay chain of inverters, the delay chain of inverters including: second NMOS transistors, wherein an increase of the first current leakage causes an increase in a second current leakage through the second NMOS transistors; and one or more second PMOS transistors operable to compensate for an increase in the second current leakage, wherein the one or more PMOS transistors are operable to determine a duration of the second period based on the second current leakage.