Patent ID: 6970374

Claim:
A static random access memory (SRAM) comprising: at least a first wire; at least a second wire; a plurality of word lines; a plurality of pairs of bit lines; a plurality of SRAM cells for storing data, each of the SRAM cells is connected to the first wire, the second wire, a corresponding word line, and a corresponding pair of the bit lines; a first bias terminal for inputting V DD ; a second bias terminal for inputting V SS ; at least a first capacitor connected to the first wire for maintaining a voltage level of the first wire above a first predetermined voltage level; at least a second capacitor connected to the second wire for maintaining a voltage level of the second wire below a second predetermined voltage level; at least a first switch unit connected between the first bias terminal and the first wire having a first control terminal for inputting a first control signal, wherein the first switch unit is turned on by the first control signal during read/write operations of the SRAM cells; and at least a second switch unit connected between the second bias terminal and the second wire having a second control terminal for inputting a second control signal, wherein the second switch unit is turned on by the second control signal during read/write operations of the SRAM cells.