Patent ID: 7603497

Claim:
A queue circuit for a recovery unit, comprising: a register having N number of entries with N corresponding outputs; a first signal path for a current read value corresponding to a current read entry of said register, said first signal path including a first N-to-1 multiplexer having inputs respectively connected to said outputs of said register, wherein the current read entry is output from said first N-to-1 multiplexer responsive to a first select signal pointing to a current read position; a second signal path for a next read value corresponding to a next read entry of said register, said second signal path including a second N-to-1 multiplexer which is separate from said first N-to-1 multiplexer, having inputs respectively connected to said outputs of said register, wherein the next read entry is output from said second N-to-1 multiplexer responsive to a second select signal pointing to a next read position; a capture latch; and a 2-to-1 output multiplexer separate from said first and second N-to-1 multiplexers which receives inputs from the first signal path and the second signal path in parallel and selectively passes one of the current read value and next read value to said capture latch based on an instruction completion signal.