Patent ID: 7670959

Claim:
A method of manufacturing a memory device, comprising: forming a first dielectric layer over a substrate; forming a charge storage layer over the first dielectric layer; forming a second dielectric layer over the charge storage layer; forming a control gate layer over the second dielectric layer; forming a hard mask layer over the control gate layer; forming a bottom anti-reflective coating (BARC) layer over the hard mask layer; and providing an etch chemistry comprising tetrafluoromethane (CF 4 ), trifluoromethane (CHF 3 ), and oxygen (O 2 ), where the flow rate of CF 4 to CHF 3 ranges from about 70:30 to about 99.99:0.1, to etch at least the first dielectric layer, the charge storage layer, the second dielectric layer, and the control gate layer.