Patent ID: 8600327

Claim:
A phase generation circuit, comprising: a decoder operable to: receive a plurality of input bits of an n-bit value; and generate a plurality of phase signals in response to receiving the input bits; a phase register coupled to the decoder and operable to store the n-bit value and further operable to output the n-bit value to the decoder in response to a triggering signal; a control circuit that is operable to cause one or more selected bits of the n-bit value output to the decoder to be set to zero regardless of the actual-value of the bit output of the phase register; a voltage controlled oscillator operable to generate a voltage signal at a frequency, wherein the triggering signal for the phase register is generated at least in part based on the frequency of the voltage controlled oscillator; and a prescaler operable to divide the frequency of the voltage signal by an integer to control the rate at which the phase register is triggered by the voltage controlled oscillator, wherein the control circuit performs frequency band selection by setting the one or more selected bits of the n-bit value to zero and thereby determining which phase signals are generated by the decoder.