Patent ID: 8589774

Claim:
A signal processing apparatus comprising: a memory device configured to store a group of signals comprising a filtered digital signal and one or more previous signals, the filtered digital signal being based on an analog signal; a detector to interpret the filtered digital signal as first discrete values; a controller configured to determine whether the first discrete values are adequately indicated based on an output of the detector, and initiate a retry mode when the first discrete values are not adequately indicated; and an averager that is communicatively coupled with the memory device to produce a new signal in the retry mode, the new signal being determined based on an average of at least a portion of the group of signals, wherein the detector is configured to interpret the new signal as second discrete values in the retry mode, wherein the controller is configured to determine whether the second discrete values are adequately indicated based on hard decisions indicated by the new signal and hard decisions indicated by the filtered digital signal.