Patent ID: 8027144

Claim:
A capacitor structure over a substrate, comprising: a plurality of conductive line levels parallel to each other and located over the substrate, wherein each conductive line level comprises a plurality of conductive lines including at least two first conductive lines parallel to each other and at least two second conductive lines parallel to each other, each first conductive line is isolated from each second conductive line, the first conductive lines on the conductive line levels neighboring each other are aligned to each other and the second conductive lines on the conductive line levels neighboring each other are aligned to each other so that the conductive lines on the conductive line levels together form a plurality of conductive co-planes comprising at least two first conductive line co-planes having the first conductive lines thereon and at least two second conductive line co-planes having the second conductive lines thereon, each conductive line co-plane comprises at least one of the conductive lines on each conductive line level; a plurality of vias located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels, wherein, on a height level of each of the conductive line co-planes, the vias are arranged only on one of the neighboring conductive line co-planes; a dielectric layer interposed between the conductive line levels; a first conductive end electrically connected to the first lines on each of the conductive line levels; and a second conductive end electrically connected to the second lines on each of the conductive line levels.