Patent ID: 8559587

Claim:
A fractional-N divider circuit, comprising: a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one; a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said second reference signal having a duty cycle that is more nearly uniform relative to the divider output signal; a divider modulation circuit configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal, said divider modulation circuit comprising a segmented accumulator configured to generate a plurality of segments of a count value having at least one period of latency therebetween; and a phase error calculator configured to provide at least one segment of the count value to said phase correction circuit.