Patent ID: 7412475

Claim:
A method of error detection in a computer processor having a plurality of memory elements, comprising: computing a base digital root (DR) for each memory element having a value stored therein to form a corresponding base DR; performing an operation on one or more of said memory elements to form a result; performing said operation on one or more of said corresponding base DRs to form a check value; computing a result DR of said result; comparing said result DR to said check value; and signaling an error based on said comparing, wherein said computing a base DR and said computing a result DR each comprise: operating a set of input adders, each configured to add two 4-bit inputs and each configured to produce a single 4-bit output and a carry bit, and operating a set of cascade adders operably connected to said 4-bit outputs and said carry bits of said set of input adders and configured to add said 4-bit outputs and said carry bits to produce the HDR of all of said 4-bit inputs without a carry bit, wherein said set of input adders and said set of cascade adders operate combinatoricly.