Patent ID: 8131893

Claim:
A memory device accessible by a first CPU and a second CPU, comprising: a first FIFO corresponding to said first CPU; a second FIFO corresponding to said second CPU; a shared storage medium configured to be writable and readable by said first CPU and said second CPU via said first FIFO and said second FIFO, respectively; a first individual storage medium and a second individual storage medium; a first register controller provided between said first individual storage medium and said first FIFO and configured to exclusively write data from said first CPU to said first individual storage medium, said first individual storage medium being connected to said first FIFO and said second FIFO independently of the first register controller, said first medium being independently readable by said first CPU and said second CPU via said first FIFO and said second FIFO respectively; a second register controller provided between said second individual storage medium and said second FIFO and configured to exclusively write data to said second individual storage medium from said second CPU, said second individual storage medium being connected to said first FIFO and said second FIFO independently of the second controller, said second individual storage medium being independently readable by said first CPU and said second CPU via said first FIFO and said second FIFO respectively, wherein data corresponding to different addresses of said first individual storage medium are simultaneously readable by said first CPU and said second CPU.