Patent ID: 7880454

Claim:
A system for controlling timing of switches in power regulator/power amplifiers, the system comprising: at least one pulse generating component to generate a first rising edge and a first falling edge indicative of source switch (high side) output and to generate a second rising edge and a second falling edge indicative of synchronous rectifier (low side) switch body diode conduction; a time measuring component to: receive signals corresponding to the first rising edge, the first failing edge, the second rising edge and the second falling edge and signals corresponding to a control system high side switch drive signal rising edge, a control system high side switch drive signal falling edge, a control system low side switch drive signal rising edge, a control system low side switch drive signal falling edge and a signal indicative of a predetermined time, and provide a plurality of time measurements, wherein the plurality of time measurements are indicative of time differences between edges; a first adjustable time delay circuit to receive a first group of time measurements from the plurality of time measurements and a control system high side switch drive signal and to provide a delayed control system high side switch drive signal; a second adjustable time delay circuit to receive a second group of time measurements from the plurality of time measurements and a control system low side switch drive signal and to provide a delayed control system low side switch drive signal; a timing circuit to receive an output of a control system signal ramp counter, to compare the output of the control system signal ramp counter to a predetermined offset from a rising edge of a control system high side switch drive signal and to a predetermined time and to generate a blanking pulse; and a counter synchronous with a control system signal rate to deliver a signal indicative of a rate at which the blanking pulse is provided as a calibration pulse, wherein the rate is substantially less than a nominal control system signal rate, wherein an output of the counter is provided to the timing circuit, and wherein the timing circuit provides a calibration signal comprising the blanking pulse provided at the rate.