Patent ID: 7875525

Claim:
A method of manufacturing a stack-type capacitor, the method comprising: (a) sequentially stacking an etch stop layer and an interlayer dielectric on a substrate and forming a via hole by patterning the interlayer dielectric and the etch stop layer, the via hole exposing a diffusion barrier layer formed on an underlying conductive plug; (b) sequentially forming a ruthenium first metal layer and a second metal layer in the via hole and on an upper surface of the interlayer dielectric, the first and second metal layers completely filling the via hole; (c) exposing the upper surface of the interlayer dielectric by removing the first and second metal layers formed thereon; (d) forming a lower electrode formed of the first metal layer and the second metal layer by removing the interlayer dielectric; and (e) sequentially depositing a dielectric layer and an upper electrode on the lower electrode, wherein the ruthenium first metal layer is formed by atomic layer deposition, and forming the first metal layer includes: (i) absorbing a halogen-series material to the resultant structure of (a) before absorbing a ruthenium precursor, the halogen-series material covering an entire exposed surface of the diffusion barrier layer; (ii) absorbing the ruthenium precursor on the interlayer dielectric and the diffusion barrier layer of a resultant structure of (a) to form a ruthenium precursor layer; (iii) purging any remaining ruthenium precursor; (iv) decomposing the ruthenium precursor by absorbing an oxygen gas to the ruthenium precursor layer to form a ruthenium oxide layer; (v) purging any remaining oxygen gas; (vi) reducing the ruthenium oxide layer by supplying a hydrogen gas thereto; and repeating steps (ii) to (vi) until the ruthenium first metal layer having a predetermined thickness is formed.