Patent ID: 8470613

Claim:
A method comprising: providing a package for a first integrated circuit, the package including a package substrate that includes a first plurality of conductors and a second plurality of conductors to connect to the first integrated circuit, each of the first plurality of conductors including a first pad proximate a first side of the first integrated circuit and each of the second plurality of conductors including a second pad proximate a second side of the first integrated circuit, wherein the second side is adjacent to the first side, and wherein each of the first plurality of conductors and the second plurality of conductors extends to a third plurality of pads on the package substrate, wherein package pins are connected to the third plurality of pads; connecting two or more integrated circuits with chip-on-chip packaging using the first pads on the first conductors for a second integrated circuit of the two or more integrated circuits and using the second pads on the second conductors for a third integrated circuit of the two or more integrated circuits, wherein the second integrated circuit is oriented orthogonally to the third integrated circuit; determining that the chip-on-chip packaging is reliable; and reducing the package substrate for a subsequent integrated circuit by eliminating the third plurality of pads and the extension of the first plurality of conductors and the second plurality of conductors to the third plurality of pads, wherein the reducing is responsive to the determining.