Patent ID: 6928575

Claim:
An integrated circuit having a multiprocessor architecture, the circuit comprising: a first processor, which operates synchronously with a first internal clock signal; a second processor, which operates synchronously with a second internal clock signal; a memory, which operates synchronously with a third internal clock signal; and a clock supply unit, which respectively adjusts the delays of three clock signal generated from an external clock signal and respectively supplies the three clock signals as the first, the second and the third internal clock signals, such that the first, the second and the third internal clock signals are in phase with each other; wherein the first processor, the second processor, the memory, and the clock supply unit are integrated together on a single chip, wherein the clock supply unit further, receives a first terminating signal and a second terminating signal; stops supplying all of the first, second and third internal clock signals when the first and second terminating signals are asserted at the same time; stops supplying only the first internal clock signal when the first terminating signal is solely asserted; and stops supplying only the second internal clock signal when the second terminating signal is solely asserted.