Patent ID: 7924642

Claim:
A semiconductor memory device, comprising: a memory cell array of memory cells arranged in a matrix; a plurality of word lines arranged in said memory cell array to select said memory cells in a row direction; a pair of read bit lines arranged in a direction orthogonal to said word lines to read data from one of said memory cells, a first read bit line in the pair of read bit lines being provided with a signal from one of the memory cells when a second read bit line in the pair of read bit lines is provided with a reference potential; a single write bit line arranged in a direction orthogonal to said word lines to write data in one of said memory cells; and a sense amp operative to amplify a potential difference caused between said pair of read bit lines, wherein said sense amp includes a differential input circuit having a pair of differential input terminals connected to said pair of read bit lines and operative to produce a pair of first differential output signals, a latch-type amplifier operative to provide a pair of second differential output signals based on the pair of first differential output signals, and a cutoff circuit operative to establish connection between said differential input circuit and said latch-type amplifier and break connection between said differential input circuit and said latch-type amplifier.