Patent ID: 7692966

Claim:
A nonvolatile semiconductor memory device, comprising: a memory array, wherein said memory array comprises a plurality of sub-blocks; each sub-block comprises a plurality of word lines extending in a first direction, a plurality of local bit lines which extend in a second direction crossing said first direction, and a plurality of memory cells each storing information based on a level change of its threshold voltage and each placed so as to correspond to each intersection of a word line and a local bit line; said plurality of sub-blocks are arrayed in said second direction; and said nonvolatile semiconductor memory device further comprising: a plurality of divided global bit lines corresponding to each sub-block and extending in said second direction; a first switching circuit corresponding to each sub-block and being placed between a corresponding plurality of divided global bit lines and said plurality of local bit lines included in a corresponding sub-block, a second switching circuit being provided between each of adjacent sub-blocks, and placed between a plurality of divided global bit lines corresponding to one of the corresponding adjacent sub-blocks and a plurality of divided global bit lines corresponding to the other sub-block, a voltage controlling circuit for independently controlling a voltage on each divided global bit line, a sense latch connected to said plurality of divided global bit lines corresponding to a sub-block at one end of said plurality of sub-blocks, and a decoder controlling a voltage on a word line corresponding to a selected memory cell of said plurality of memory cells belonging to a selected sub-block of said plurality of sub-blocks; wherein said selected memory cell is connected to said sense latch via corresponding first and second switching circuits, and said sense latch carries out write-in/read-out of data into/from said selected memory cell in cooperation with said voltage controlling circuit and said decoder.