Patent ID: 6928571

Claim:
A system, comprising: a data source, having a plurality of different lines; a plurality of programmable delay elements, each coupled to one of said plurality of lines, to control a delay in said one of said lines to produce delayed values; a register, storing values for said programmable delay elements which respectively control an amount of delay caused by said delay elements; an arbitration logic, coupled to said plurality of delayed values, and operating to determine relative timing of said plurality of lines, wherein said arbitration logic includes a first element which produces a set of first values for said register, and a second element which determines relative arrival of signals based on said first values, and wherein said arbitration logic dithers between different sets of values, and determines which of said plurality of values produces a best desired result, and stores said best result in said register, wherein said plurality of programmable delay elements thereafter are programmed with values in said register.