Patent ID: 6872665

Claim:
A method of fabricating an integrated circuit, comprising the following steps performed in order of: forming an interlevel dielectric layer over a semiconductor body; forming an intrametal dielectric layer over said interlevel dielectric layer; forming a hardmask over said intrametal dielectric layer; forming a via pattern over said hardmask; selectively etching a via through said hardmask; partially extending said via by selectively etching said intrametal dielectric layer; depositing a BARC layer over said hardmask and within said via, wherein said BARC layer is significantly thicker within said via than over said hardmask; forming a trench pattern over said BARC layer; and etching a trench in said intrametal dielectric layer, wherein said etching a trench step further removes at least a portion of said BARC layer within said via and removes a portion of said interlevel dielectric layer such that at the conclusion of said etching a trench step said via extends through said interlevel dielectric layer.