Patent ID: 8890602

Claim:
A well-biasing circuit for an integrated circuit (IC), wherein the IC includes a plurality of cells that operate on a core power supply, and each cell includes an n-well region and an n-well bias contact to bias the n-well region, and wherein the well-biasing circuit is connected to an n-well bias contact of each cell, the well-biasing circuit comprising: a well-bias regulator for providing a first n-well bias voltage to the n-well bias contact based on a control signal, when the IC is in a low power mode; a switch, connected between the core power supply and the n-well bias contact, for connecting the core power supply to the n-well bias contact when the IC is in a RUN mode and disconnecting the core power supply from the n-well bias contact when the IC is in the low power mode; a voltage inverter circuit having an input terminal for receiving the control signal, a power supply terminal connected to the core power supply, and an output terminal for generating first and second intermediate voltages when the IC is in the RUN mode and the low power mode, respectively; a level-shifter, connected to the output terminal of the voltage inverter circuit, for level shifting the first intermediate voltage to a pre-defined voltage when the IC is in the RUN mode; a complementary metal-oxide semiconductor (CMOS) inverter circuit having an input terminal connected to the level-shifter for receiving the pre-defined voltage when the IC is in the RUN mode and the second intermediate voltage when the IC is in the low power mode, a power supply terminal for receiving the pre-defined voltage, and an output terminal for generating an output voltage; and a resistive-voltage divider, connected between the output terminal of the CMOS inverter circuit and the switch, for scaling down the output voltage when the IC is in the low power mode, wherein the CMOS inverter circuit enables and disables the switch when the IC is in the RUN and low power modes, respectively.