Patent ID: 6996640

Claim:
A data transfer controller for asynchronously transferring data by way of a buffer device comprising a plurality of data storage locations without performing a read address and write address comparison, the controller comprising: a buffer-segment module configured to define a plurality of buffer segments comprising at least two data storage locations in the buffer device, the data storage locations of respective ones of the buffer segments being filled with data from at least one data source device operating in a respective clock domain, wherein the buffer-segment module is further configured to dynamically adjust the number and/or size of the buffer segments; and a segment-availability gauge configured to generate, upon the data storage locations of any respective buffer segment being filled up with said data, an indication of availability of the filled data storage locations of the data contents of the respective buffer segment for transfer to at least one data destination device operating in a respective clock domain, the segment-availability gauge being further configured to generate, upon the contents of the respective segment being acknowledged as transferred to the destination device, an indication of availability of that buffer segment for further refilling of data from the source device, the clock domain of the at least one source device being distinct than the clock domain of the at least one destination device.