Patent ID: 8043900

Claim:
A method of manufacturing a semiconductor integrated circuit device having an integrated circuit, the method comprising the steps of: (a) preparing a first layout of the integrated circuit including a plurality of active regions, a plurality of gate electrodes, a plurality of signaling wirings, a plurality of power-feeding wirings, a plurality of signaling plugs, and a plurality of power-feeding plugs; and (b) deleting the power-feeding plug that is placed within a first distance from each of the signaling plugs among the power-feeding plugs from the first layout, wherein in the step (a), the power-feeding plugs for electrically connecting the power-feeding wiring to the active region are placed under the power-feeding wiring, wherein a potential higher than that of the signaling wiring and the signaling plug is supplied to the power-feeding wiring and the power-feeding plug, and wherein the power-feeding plug deleted from the first layout in the step (b) is close to the signaling plug, close enough to impair an operation of the integrated circuit.