Patent ID: 7925913

Claim:
A method of operating clock data recovery circuitry in a serial interface of a programmable integrated circuit device, wherein said serial interface operates under a serial communications protocol that includes a signal indicating entry into an idle period, said method comprising: during said idle period, operating said clock data recovery circuitry in a mode in which said clock data recovery circuitry toggles between a lock-to-data state and a lock-to-reference state; asserting a synchronization signal upon receipt of data following said idle period; in each lock-to-data interval during toggling of said clock data recovery circuitry, checking for assertion of said synchronization signal; and in absence of said synchronization signal during said lock-to-data interval, continuing said toggling of said clock data recovery circuitry, and on detection of said synchronization signal discontinuing toggling of said clock data recovery circuitry and maintaining said clock data recovery circuitry in said lock-to-data state.