Patent ID: 7675342

Claim:
A CMOS integrated circuit (IC) including an array of programmable resistive elements, each of said programmable resistive elements comprising: a first field effect transistor (FET), the drain of said first FET connected to a selectable program-supply line; a program select connected to the gate of said first FET; a second FET, the drain of said second FET coupled to a resistive load line; a resistor select connected to the gate of said second FET; and a phase change resistor connected to the source of said first FET and the source of said second FET; wherein four pair of said programmable resistive elements are connected to a common said selectable program-supply line and a common said resistive load line, said four pair forming a dynamically variable resistor, in each pair one resistor select being a resistance adjust for the pair; and wherein a four bit select is connected to said resistor select and said resistance adjust on two of said four pair, a two bit select is connected to said resistor select and said resistance adjust on a third of said four pair and, said resistance adjust is grounded on a fourth of said four pair.