Patent ID: 7105457

Claim:
A method of manufacturing a semiconductor device comprising the steps of: (a) setting, on a main surface of a semiconductor wafer, a semiconductor chip formation region and a peripheral region surrounding said semiconductor chip formation region; (b) forming, within said semiconductor chip formation region, a circuit device and a plurality of electrode pads for connection to said circuit device; (c) forming, on said main surface, an insulating film which exposes a portion of each of said plurality of electrode pads; (d) forming, on said insulating film, a conducting film covering said plurality of electrode pads; (e) forming a wiring layer on said conducting film; (f) forming a negative resist layer over said wiring layer and said peripheral region; (g) optically exposing and patterning said negative resist layer, using a shielding layer to optically shield protruding electrode formation regions defined on said wiring layer and using an optical exposure apparatus having an electrode blind which optically shields a plurality of electrode formation regions in said peripheral region, so as to form aperture portions in said protruding electrode formation regions to expose a portion of said wiring layer and so as to expose said conducting film at a plurality of locations to form a plurality of electrode portions; and (h) executing a plating step, using as a mask said patterned resist layer having said aperture portions, to form protruding electrodes in said protruding electrode formation regions.