Patent ID: 7563692

Claim:
A method, comprising: forming a conducting layer on a first wafer; forming both an insulating layer on a substantially flat side of a second wafer, and a continuous conducting area disposed on or within only a portion of the second wafer, wherein only the insulating layer comprises a plurality of cavities abutting the second wafer continuous conducting area; bonding a side of the conducting layer opposite the first wafer to a side of the insulating layer opposite the second wafer; and removing at least a portion of the first wafer without removing at least a portion of the conducting layer such that the conducting layer forms a plurality of diaphragms that are electrically insulated with respect to one another, each diaphragm corresponding to one of the cavities and substantially parallel to the second wafer, and further such that the continuous conducting area forms a single fixed capacitor plate common to all cavities with corresponding diaphragms.