Patent ID: 8406050

Claim:
A method of sensing a data value in a memory cell of a non-volatile NAND architecture memory string, comprising: applying a read voltage to a selected word line coupled to a selected non-volatile memory cell of the NAND architecture memory string that is selected for reading; applying a pass voltage to one or more unselected word lines and coupled non-volatile memory cells of the non-volatile NAND architecture memory string; coupling the non-volatile NAND architecture memory string to a source line and a bit line; sourcing current from a current source on to the bit line; using the current from the current source while the read voltage is applied to the selected word line coupled to the selected non-volatile memory cell, increasing a voltage of the bit line if the selected non-volatile memory cell is deactivated in response to the read voltage; sensing the voltage of the bit line at a control gate of a transistor to determine the data value stored in the selected non-volatile memory cell of the non-volatile NAND architecture memory string; and using the sensing of the voltage of the bit line to selectively isolate the selected non-volatile memory cell from the current source.