Patent ID: 6912012

Claim:
A method of achieving lock in a phase-locked loop comprising: counting pixels of digital video data, testing for the occurrence of a sync pulse in the digital data and in connection with detecting a sync pulse, performing the following steps: storing the pixel count value in a register; comparing the saved pixel count value with a nominal pixel count value; detecting whether the digital video data represents a video cassette recorder signal or a television signal; detecting whether noise exists in the digital video data signal when the digital video data represents a television signal; adjusting, by a coarse amount, an increment value to a discrete time oscillator in connection with the comparison of the saved pixel count value with the nominal pixel count value when the digital video data represents a video cassette recorder signal and a noise-free television signal; and further adjusting, by a fine amount, the increment value in connection with a phase error, whose computation is based on a demmer window weighting function applied to the sync pixels when the digital video data represents a video cassette recorder signal and a noise-free television signal; adjusting, by a fine amount, the increment value in connection with a phase error, whose computation is based on a flat window weighting function applied to the sync pixels when the digital video data represents a television signal having noise, adjusting by fine amount includes tuning a normalization constant to bring the falling edge of the sync pulse so as to be substantially centered within a flat window of a width corresponding to predetermined number of pixel clock cycles.