Patent ID: 7834653

Claim:
A method comprising controllably utilizing a control signal generated by an Input/Output (IO) core to: isolate, during a failsafe mode of operation and a tolerant mode of operation, a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a plurality of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof; feed back an appropriate voltage to a floating node created by the isolation of the current path; and control a voltage across each transistor of the plurality of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor of the plurality of cascaded transistors derived from one of the supply voltage and the external voltage supplied through the IO pad during modes of operation thereof, the modes of operation including the failsafe mode of operation, the tolerant mode of operation, and a driver mode of operation, wherein the external voltage supplied through the IO pad varies from zero to a value of the supply voltage during the driver mode of operation, wherein the supply voltage is zero during the failsafe mode of operation, and wherein the external voltage supplied through the IO pad increases to a value above the supply voltage during the tolerant mode of operation.