Patent ID: 8482118

Claim:
An integrated circuit package comprising: a substrate; a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable epoxy formed over the substrate, wherein the epoxy layers include at least one patterned epoxy layer; a first integrated circuit having an active surface that is embedded in one of the epoxy layers; at least one interconnect layer that includes at least one conductive via, the at least one interconnect layer being embedded in one of the epoxy layers; and a first antenna that is formed from a conductive material and is electrically coupled with the active face of the first integrated circuit through at least one of the interconnect layers, the first antenna being formed over one of the epoxy layers, wherein at least one of the epoxy layers is positioned between first antenna and the substrate; wherein the plurality of stacked epoxy layers includes at least one epoxy layer that covers the first antenna such that the first antenna is not exposed; the first integrated circuit is positioned in a first layer of the plurality of the epoxy layers; the integrated circuit package further comprises a second integrated circuit that is positioned in a second layer of the plurality of epoxy layers; and the first antenna is positioned between the first and second epoxy layers.