Patent ID: 6882574

Claim:
An erasable programmable read only memory comprising: two serially connected P-type metal-oxide semiconductor (MOS) transistors,wherein a first P-type MOS transistor acts as select transistor, a gate of said first P-type MOS transistor is coupled to select gate voltage, a first node of said first P-type MOS transistor is connected to source line voltage, a second node of said first P-type MOS transistor is connected to a first node of a second P-type MOS transistor, wherein a second node of said second P-type MOS transistor is connected to bit line voltage, wherein a gate of said second P-type MOS transistor serves as a floating gate, wherein said erasable programmable read only memory does not need to bias a certain voltage on a control gate for programming and thereby injecting hot carriers onto said floating gate, and wherein said erasable programmable read only memory is capped by dielectric materials which are transparent to ultraviolet (UV) light.