Patent ID: 7805549

Claim:
A transfer apparatus, comprising: a first interface constructed to interface with a first bus; a second interface constructed to interface with a second bus; a bridge unit connected with said first interface via a first internal bus and with said second interface via a second internal bus and constructed to transfer a transaction between said first bus and said second bus; a data transfer unit connected with said first interface via a third internal bus and with said second interface via a fourth internal bus and constructed to perform a DMA data transfer between said first bus and said second bus; and a sequence control unit constructed to control an order in which the transaction transfer by said bridge unit and the DMA data transfer by said data transfer unit are enabled, such that a read transaction by said bridge unit is enabled when a write transaction and the DMA data transfer do not exist, such that the DMA data transfer is enabled when the DMA data transfer precedes the write transaction and a transfer destination of the DMA data transfer has been acquired, and such that the write transaction is enabled when the write transaction precedes the DMA data transfer or when the transfer destination of DMA data transfer is not acquired.