Patent ID: 8509359

Claim:
A multi-channel sequential Viterbi decoder comprising: an input buffer; a signal driver for reading data from the input buffer; a selector that selects symbols from the data; a decoder channels parameters unit; a processing unit for resetting path metrics; a processing unit for setting a path metric value based on a path number; a processing unit for getting a bit from the path with assigned number; a processing unit for processing the selected symbols and which is connected to the decoder channels parameters unit; a memory for storing decoding paths and path metrics from the processing units; a unit for generating a channel base address; a unit for generating a cell address for addressing the memory based on the channel base address; and a plurality of buffers for decoder output that receive an input from the processing unit for processing the selected symbols, wherein: outputs of the processing units are connected to a bus; the unit for generating a cell address is connected to the bus; the selector is connected to inputs of the processing units for resetting path metrics, for setting a path metric value, and for getting a bit from the path with assigned number; the processing unit for getting a bit from the path and the processing unit for processing the selected symbols provide the bit to the plurality of data buffers; the input buffer provides outputs to the signal driver, the selector, the unit for generating the channel base address and to the processing unit for processing the selected symbols; the signal driver providing an output to the input buffer and to the selector; and the signal driver receiving inputs from the processing units.