Patent ID: 7977218

Claim:
A method of forming at least a portion of a memory core array upon a semiconductor substrate, the method comprising: forming shallow trench isolation structures in the substrate substantially surrounding a memory device region within the memory core array; forming an oxide layer over the substrate in the memory device region and over the shallow trench isolation structures; wherein an inner section of the oxide layer formed over the memory device region is thicker than an outer section of the oxide layer formed over the shallow trench isolation structures substantially surrounding the memory device region; forming a first polysilicon layer over the inner and outer sections of the oxide layer, and patterning the first polysilicon layer, wherein the patterned first polysilicon layer comprises one or more polysilicon dummy tiles formed over the outer section of the oxide layer, and wherein the patterned first polysilicon layer further comprises at least one inner section of the patterned first polysilicon layer formed over the inner section of the oxide layer that is electrically connected to the one or more polysilicon dummy tiles, wherein the one or more polysilicon dummy tiles are connected to the at least one inner section of the patterned first polysilicon layer by one or more polysilicon bridges formed by patterned portions of the first polysilicon layer; and continuously maintaining the presence of the one or more polysilicon bridges until formation and patterning of a second polysilicon layer within the memory device region.