Patent ID: 8737137

Claim:
A memory comprising: a word line driver circuit; a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit; a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit, wherein the write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit, wherein the write bias generator includes: a diode configured transistor including a first current terminal for receiving the write voltage and a second current terminal connected to the output node; a first transistor having a first current terminal connected to the output node, a second current terminal, and a control terminal; a second transistor having a first current terminal for receiving the write voltage, a second current terminal connected to the control terminal of the first transistor, and a control terminal connected to the output node, wherein during a write mode, the conductivity of the second transistor controls the conductivity of the first transistor for regulating the voltage of the output node.