Patent ID: 7745919

Claim:
A semiconductor device comprising: a plurality of semiconductor chips, each of which includes: lower and upper surfaces; a plurality of lower terminals on the lower surface; a plurality of upper terminals on the upper surface, each of the upper terminals being vertically aligned correspondingly with one of the lower terminals; and a plurality of conductive lines, each of the conductive lines being provided to electrically connect an associated one of the lower terminals to an associated one of the upper terminals which is not vertically aligned to the associated one of the lower terminals, wherein the plurality of the semiconductor chips are stacked with each other such that the upper terminals of a lower one of the semiconductor chips are connected respectively to the lower terminals of an upper one of the semiconductor chips, and each of the lower electrodes of the lowermost semiconductor chip is electrically connected through the conductive lines to, and vertically aligned with, a corresponding one of the upper terminals of the uppermost semiconductor chip.