Patent ID: 7463649

Claim:
A system for checking the validity of data transmission, the system comprising a data transmitting computer, a data receiving computer, and a network, wherein: the data transmitting computer is provided for generating a check-code of original data, and sending a data packet, which comprises the original data and the check-code, to the data receiving computer via the network, the data transmitting computer comprising a Central Processing Unit (CPU), a Peripheral Component Interface (PCI) bus, and a memory, the CPU of the data transmitting computer comprising: a shift operation unit for performing a shift operation on data units of the original data; an addition operation unit for adding data in all data units after the shift operation to obtain a checksum 1 ; a complement operation unit for calculating a 2's complement of the last 2 m bytes of the checksum 1 to obtain a check-code; and a control unit for reading the original data from the memory via the PCI bus, and sending a data packet comprising the original data and the check-code to the data receiving computer; and the data receiving computer is provided for receiving the data packet from the data transmitting computer, checking and determining whether the data packet is valid, the data receiving computer comprising a CPU, the CPU of the data receiving computer comprising: a shift operation unit for performing a shift operation on the data units of the original data unpacked from the received data packet; an addition operation unit for adding the data units after the shift operation to obtain a checksum 2 , and adding the last 2 m bytes of the checksum 2 to the check-code from the received data packet to obtain a checksum 3 ; and a control unit for determining whether the data packet from the data transmitting computer is valid by checking whether the last 2 m bytes of the checksum 3 equals “0;” wherein “m” represents the number “0” or any natural number.