Patent ID: 8449675

Claim:
A process for producing an epitaxially coated semiconductor wafer with low resistivity below the epitaxial layer, comprising providing a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type and having a front surface and a back surface, forming a layer on the front surface of the substrate wafer by introducing additional dopant atoms of the n type or p type into the substrate wafer through the whole of the front surface of the substrate wafer, the layer extending from the front surface of the substrate wafer into the substrate wafer and having a thickness of at least 20 μm, the dopant concentration in the layer being increased by the additional dopant atoms introduced from the level n + to the level n ++ when the substrate wafer is an n + doped wafer, or from the level p + to the level p ++ when the substrate wafer is a p + doped wafer; depositing an epitaxial layer on the front surface of the substrate wafer; and removing material from the back surface of the substrate wafer until the thickness of the substrate wafer is less than 120 μm or until the dopant level of the substrate wafer is exclusively n ++ or p ++ .