Patent ID: 8724425

Claim:
A semiconductor storage device, wherein the semiconductor storage device is configured to generate a third signal for latching data based on one of a first signal and a second signal, the first and second signals being output from an address change detection signal terminal which is configured to receive a signal indicating a change in the address signal, to set a first access mode for subsequent cycles based on a first pulse width of the first signal indicating a first address change, to set a second access mode for the subsequent cycles based on a second pulse width of the second signal indicating a second address change and to perform an access operation to a core circuit based on one of the first access mode and the second access mode which are set based on the first address change and the second address change, respectively, wherein the first access mode is a synchronous operating mode, and the second access mode is an asynchronous operating mode, wherein the address change detection signal terminal is provided in addition to an address input terminal to receive an address signal.