Patent ID: 7328361

Claim:
A digital bus comprising: a transmitter unit capable of generating a plurality of clock signals; a receiver unit comprising: one or more first-in-first-out (FIFO) units; and a synchronizer unit coupled to the one or more FIFO units, the synchronizer unit adapted to receive the plurality of clock signals, a sample clock signal, and a reset signal and to generate a plurality of write reset signals and a read reset signal, wherein each of the plurality of write reset signals has a latency with respect to the read reset signal of less than or equal to one clock cycle, the synchronizer unit comprising: a first synchronizer unit to receive the plurality of clock signals and the reset signal and to generate a synchronized reset signal; a second synchronizer unit to receive the plurality of clock signals and the synchronized reset signal and to generate the plurality of write reset signals; and a third synchronizer unit to receive the sample clock signal, the synchronized reset signal, and the plurality of write reset signals and to generate the read reset signal having a latency with respect to each of the write reset signals of less than or equal to one clock cycle; and a transmission medium to couple the plurality of clock signals from the transmitter unit to the receiver unit.