Patent ID: 7734455

Claim:
A method for verifying a design, performed by a computing device, the method comprising: creating, using a processor associated with the computing device, a graphical model of the design with a graphical modeling tool, where the graphical model includes a block diagram model that includes a plurality of model elements, where the plurality of model elements includes blocks interconnected by lines that represent signals; coupling, using the processor, a graphical postcondition element to a selected model element of the plurality of model elements, the graphical postcondition element including an indication of a desired result associated with the selected model element, where the graphical postcondition element corresponds to a block of the block diagram model; generating, using the processor, an executable form of the design from the graphical model; generating, using the processor, a postcondition specification based on the indication, where the postcondition specification is in a form usable by a verification tool; and providing, using the processor, the executable form of the design and the postcondition specification to the verification tool, to instruct the verification tool to implement one or more verification scenarios in which the selected model element produces the desired result.