Patent ID: 7298004

Claim:
A charge-trapping memory cell comprising: a semiconductor substrate comprising a main surface; a plurality of parallel fins provided as bitlines and arranged at a distance from one another on said main surface; said fins comprising a lateral dimension with respect to said main surface of less than about 30 nm and being subdivided into a plurality of disjointed pairs of adjacent first and second fins; a memory layer sequence provided for charge-trapping and arranged on surfaces of said fins; a plurality of parallel wordlines arranged at a distance from one another across said fins; source/drain regions located in said fins between said wordlines and at ends of said fins; contact areas of said source/drain regions at said ends of said fins, each of said contact areas being common to the fins of one of said pairs; a first plurality of select transistors located in said first fins of said pairs of fins between said plurality of wordlines and said contact areas; a second plurality of select transistors located in said second fins of said pairs of fins between said plurality of wordlines and said contact areas; and select lines coupling said first plurality of select transistors and said second plurality of select transistors, respectively.