Patent ID: 8327236

Claim:
An error judging circuit comprising: a first EOR circuit tree that generates a check bit of an error correction code by polynomial remainder calculation of C(x)=x 2 I(x)modP(x) with respect to a polynomial expression I(x) of an original code which is protected from an error with respect to data of m bit block unit by addition in a Galois extension field GF (2 m ) (m is a natural number not less than 8) in S m EC-D m ED using (k, k−3) Reed-Solomon code (k is a natural number not more than 2 m ) when P(x) is a primitive polynomial of m-order in a Galois field GF(2), a primitive element in the Galois extension field GF (2 m ) is α, and a root of P(x)=0 is α i (i=0, . . . , m−1); a second EOR circuit tree that generates syndromes S 0 , S 1 , S 2 from S n =Y(α n ) (n=0, 1, 2) with respect to code C(x) in which the check bit is added to the original code when a polynomial representation of a code which is to be detected an error and has a possibility that an error is mixed is Y(x); and an error detection circuit unit that detects if there is a one block error, a two block error, or no error based on whether or not an equation of syndromes S 1 2 =S 0 S 2 is satisfied and for detecting a position p of a block error from an equation of syndromes S 0 α p =S 1 in the Galois extension field GF (2 m ).