Patent ID: 7268601

Claim:
An apparatus for correcting a duty cycle of a clock signal, comprising: a first clock buffer for receiving an external clock signal through a non-inverting terminal of the first clock buffer and for receiving an external clock bar signal through an inverting terminal of the first clock buffer to thereby output a first internal clock signal; a second clock buffer for receiving the external clock bar signal through the non-inverting terminal of the second clock buffer and for receiving the external clock signal through the inverting terminal of the second clock buffer to thereby output a second internal clock signal; a delay line unit for receiving the first and second internal clock signals from the clock buffers, a first detection signal and a second detection signal to output a first delayed internal clock signal by delaying the first internal clock signal according to the first detection signal, and a second delayed internal clock signal by delaying the second internal clock signal according to the second detection signals; a duty error controller for receiving the first and second delayed internal clock signals and outputting a first duty controlled clock signal and second duty controlled clock signal by shifting each edge of the first and second delayed internal clock signals in order to match; a first delay model unit for receiving the first duty controlled clock signal which travels to a data input/output pin to output a first compensated clock signal by compensating for a difference between the external clock signal and the first duty controlled clock signal; a first direct phase detector for receiving the external clock signal, generating a first detection signal by comparing the external clock signal and the first compensated clock signal and outputting the first detection signal to the delay line unit; a second delay model unit for receiving the second duty controlled clock signal which travels to a data input/output pin to output a second compensated clock signal by compensating for a difference between the external clock signal and the second duty controlled clock signal; and a second direct phase detector for generating a second detection signal by comparing the external clock signal and the second compensated clock signal and outputting the second detection signal to the delay line unit.