Patent ID: 7839669

Claim:
A semiconductor memory device, comprising: a first memory cell array including a plurality of arrayed memory cells each containing a ferroelectric capacitor, a first bit line and a second bit line arranged to read data out of said memory cells, selection lines arranged to selectively connect said memory cell to said first bit line or said second bit line, and a plate line arranged to apply a drive voltage to said ferroelectric capacitor; a second memory cell array including a plurality of arrayed memory cells each containing a ferroelectric capacitor, a third bit line and a fourth bit line arranged to read data out of said memory cells, selection lines arranged to selectively connect said memory cell to said third bit line or said fourth bit line, and a plate line arranged to apply a drive voltage to said ferroelectric capacitor; a sense amp circuit operative to detect and amplify a potential difference caused between any two of said first through fourth bit lines; a decoupling circuit operative to selectively connect any two of said first through fourth bit lines to said sense amp circuit and decouple the remainder from said sense amp circuit; and a bit-line potential control circuit arranged between said decoupling circuit and said first and second memory cell arrays and operative to fix the voltage of said bit lines decoupled from said sense amp circuit by said decoupling circuit to a first potential, the bit lines being among said first through fourth bit lines.