Patent ID: 8824197

Claim:
A static random access memory (RAM) comprising: a plurality of word lines; a plurality of pairs of local bit lines; a plurality of memory cells arranged in correspondence with intersections of the plurality of pairs of local bit lines and the plurality of word lines; a plurality of capacitance shared circuits each arranged for each of the plurality of pairs of local bit lines; a common connection line connecting the plurality of capacitance shared circuits; and a pair of global bit lines connected to the plurality of pairs of local bit lines, wherein: each capacitance shared circuit comprises two N-channel transistors connected between the pair of local bit lines and the common connection line corresponding to each other, a drain of one of the two N-channel transistors is connected to one of the pair of local bit lines, a drain of the other of the two N-channel transistors is connected to the other of the pair of local bit lines, and sources of the two N-channel transistors are connected to the common connection line.