Patent ID: 7566598

Claim:
A method of mask reduction for producing a low-temperature polysilicon thin film transistor array by use of a photo-sensitive low-K dielectric, comprising the steps of: (a) defining a polysilicon-island on a preprocessed glass substrate; (b) forming a gate oxide layer and a first metal layer in sequence; (c) patterning said first metal layer to define a gate; (d) forming a photosensitive low-K dielectric layer; (e) patterning said photosensitive low-K dielectric layer using photolithography so that a lithographic pattern is transferred onto said photosensitive low-K dielectric layer; (f) using said photosensitive low-K dielectric layer as an etch mask to carry out etching on said gate oxide layer to form a plurality of contact holes on said gate oxide layer; (g) forming a second metal layer and patterning the same; and (h) forming a transmissive pixel electrode layer and patterning the same to define a pixel electrode, wherein the photosensitive low-K dielectric layer formed functions as both a passivation layer and an interlayer dielectric.