Patent ID: 8643116

Claim:
A semiconductor device comprising: a first MISFET fabricated over a semiconductor substrate and having a first conductive type; a second MISFET fabricated over the semiconductor substrate and having the same conductive type as the first conductive type, and a third MISFET fabricated over the semiconductor substrate and having a different conductive type from the first conductive type, wherein the first MISFET includes: (a1) a first gate insulating film arranged over the semiconductor substrate; (b1) a first gate electrode arranged over the first gate insulating film; and (c1) a first source region and a first drain region which are formed in a first active region on the semiconductor substrate, wherein the second MISFET includes: (a2) a second gate insulating film arranged over the semiconductor substrate; (b2) a second gate electrode arranged over the second gate insulating film; and (c2) a second source region and a second drain region which are formed in a second active region on the semiconductor substrate, wherein the third MISFET includes: (a3) a third gate insulating film arranged over the semiconductor substrate; (b3) a third gate electrode arranged over the third gate insulating film; and (c3) a third source region and a third drain region which are formed in a third active region on the semiconductor substrate, wherein the first to third active regions are separated from each other by an element isolation region formed on the semiconductor substrate, wherein the first gate electrode and the second gate electrode are coupled electrically, the first source region and the second source region are coupled electrically, and the first to third drain regions are coupled electrically, wherein a threshold voltage of the first MISFET and a threshold voltage of the second MISFET are different from each other, and wherein the first and second MISFETs both are in an off-state when the third MISFET is in an on-state, and the first and second MISFETs both are in an on-state when the third MISFET in an off-state.