Patent ID: 7419905

Claim:
A method of fabricating a gate electrode for a semiconductor comprising the steps of: providing a substrate prepared with a gate stack, the gate stack includes a gate dielectric on the substrate and a gate layer on the gate dielectric, the gate layer comprising a first material of thickness t p , the first material being selected from the group consisting of Si, Si 1-x —Ge x alloy, Ge and mixtures thereof; providing a metal layer on the gate layer, the metal layer having a thickness t m , wherein the thicknesses t p and t m are related by a predetermined ratio of t m /t p ; and annealing the layers, wherein the predetermined ratio results in all of the first material of the gate layer and substantially all of the metal of the metal layer over the gate layer being consumed during reaction with one another to form a resulting layer which serves as a gate electrode in contact with the gate dielectric, wherein the gate electrode comprises a work function close to about a mid-gap of silicon band gap.