Patent ID: 7045429

Claim:
A method of manufacturing a semiconductor device comprising: forming a semiconductor layer structure on a substrate; forming first spacers on both sidewalls of the semiconductor layer structure; forming gate electrodes on sidewalls of the first spacers, respectively; forming lightly doped source regions at first portions of the substrate adjacent to the semiconductor layer structure by implanting first impurities into the first portions of the substrate using the semiconductor layer structure, the first spacers and the gate electrodes as masks; forming halo regions adjacent to the lightly doped source regions beneath the gate electrodes by implanting second impurities into second portions of the substrate beneath the gate electrodes using the semiconductor layer structure, the first spacers and the gate electrodes as masks; forming second spacers on sidewalls of the gate electrodes, respectively; forming heavily doped source regions and a highly doped drain region by implanting third impurities using the first spacers, the gate electrodes and the second spacers as masks, the heavily doped drain region being formed in the semiconductor layer structure and the heavily doped source regions being adjacent to the lightly doped source regions; and forming a lightly doped drain region beneath the semiconductor layer structure by thermally treating the substrate to diffuse the third impurities in the heavily doped drain region into the substrate.