Patent ID: 8716072

Claim:
A method for simultaneously forming a nanowire field effect transistor (FET) device and a double gate FET device, the method comprising: depositing a first semiconductor layer on a substrate wherein a surface of the first semiconductor layer is parallel to {110} crystalline planes of the first semiconductor layer; epitaxially depositing a second semiconductor layer on the first semiconductor layer; etching the first semiconductor layer and the second semiconductor layer to define a nanowire channel portion comprising a plurality of nanowires that connect a first source region pad to a first drain region pad, the nanowire channel portion having sidewalls that are parallel to {100} crystalline planes, and the first source region pad and the first drain region pad having sidewalls that are parallel to {110} crystalline planes; where etching further comprises simultaneously etching the first semiconductor layer and the second semiconductor layer to define a single channel portion that connects a second source region pad to a second drain region pad, the channel portion having sidewalls that are parallel to {100} crystalline planes, and the second source region pad and the second drain region pad having sidewalls that are parallel to {110} crystalline planes; and performing an anisotropic etch that removes primarily material from {100} crystalline planes of the first semiconductor layer such that the nanowire channel portion and the channel portion are suspended by the first and second source region pads and the first and second drain region pads, respectively.