Patent ID: 7768063

Claim:
A semiconductor device comprising a semiconductor substrate; a first conductive layer provided on a surface of the semiconductor substrate and serving as one of a source and a drain; a first interlayer insulating film provided on the first conductive layer; a gate electrode film provided on the first interlayer insulating film; a second interlayer insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second interlayer insulating film, the gate electrode film and the first interlayer insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulating film provided on the side surface of the gate opening and having a projecting shape at a portion between the first interlayer insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulating film, and serving as the one of the source and the drain while being in contact with the first conductive layer; a channel which is buried in the gate opening above the second conductive layer so as to face the gate electrode film with the gate insulating film therebetween, and which has a channel layer generated therein, the channel layer allowing majority carriers to flow between the source and the drain in response to a voltage applied to the gate; a third conductive layer buried in the gate opening above the channel so as to be in contact with the gate insulating film to serve as the other one of the source and the drain; and a fourth conductive layer of the same conductivity type as that of the first conductive layer, the fourth conductive layer provided on the side surface of and near the bottom of the recess so as to be in contact with the first and second conductive layers.