Patent ID: 8786019

Claim:
A CMOS FinFET device comprising: a substrate including a first region and a second region; a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region; an insulation material disposed on the substrate and between the first and second fins; a first portion of the first fin comprising a material that is the same material as the substrate; a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin; a first portion of the second fin comprising a material that is the same material as the substrate; a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin; and a gate structure disposed on a central portion of the first fin including the III-V semiconductor material separating source and drain regions of a N-type metal-oxide-semiconductor (NMOS) fin-like field effect transistor (FinFET) device of the CMOS FinFET device and disposed on a central portion of the second fin including the Ge material separating source and drain regions of a P-type metal-oxide-semiconductor (PMOS) fin-like field effect transistor (FinFET) device of the CMOS FinFET device, wherein the source and drain regions of the NMOS device define a channel region of the NMOS device therebetween, and wherein the source and drain regions of the PMOS device define a channel region of the PMOS device therebetween.