Patent ID: 7445995

Claim:
A method of fabricating a flash memory structure, comprising the steps of: patterning a semiconductor substrate to remove part of the semiconductor substrate to a predetermined depth with a plurality of island blocks formed in the semiconductor substrate and a trench formed between two adjacent island blocks, wherein a top surface of each of the island blocks is a first top surface of the semiconductor substrate and a surface of the trench is a second top surface of the semiconductor substrate; forming a first insulating dielectric layer on the semiconductor substrate to simultaneously cover the island blocks and the trench; forming a charge storage layer pattern on the first insulating dielectric layer such that the trench is filled with the charge storage layer pattern; forming a second insulating dielectric layer on the charge storage layer pattern to cover the charge storage layer pattern; forming a conductive layer on the second insulating dielectric layer to cover the second insulating dielectric layer; forming a nitride covering layer on the conductive layer to cover the conductive layer; patterning the conductive layer, the second insulating dielectric layer and the charge storage layer pattern to form a gate stack unit such that part of the first insulating dielectric layer in the trench and part of the first insulating dielectric layer on the island block are exposed, wherein the gate stack unit covers at least part of the three side surfaces of the island block, and is positioned on part of the trench and part of the island block; and implanting ions into part of the first top surface and the second top surface of the semiconductor substrate to form respectively a drain region and a source region.