Patent ID: 7464345

Claim:
A method for estimating resources during design planning comprising the steps of: (A) receiving design information for an integrated circuit design, wherein a first portion of said integrated circuit design is complete and a second portion of said integrated circuit design is incomplete; (B) receiving user input of estimated design information for said second portion of said integrated circuit design; and (C) automatically generating one or more representative blocks representing said second portion of said integrated circuit design based on said user input, wherein said one or more representative blocks comprise an estimated register transfer level (RTL) representation of said second portion of said integrated circuit design, wherein said estimated RTL representation comprises one or more representative blocks of code that (i) have no real functional purpose and (ii) when synthesized have a size and characteristics substantially equivalent to a final actual RTL description for said second portion of said integrated circuit design, and wherein said estimated RTL representation has a proportion of logic to registers that is configurable in response to said user input.