Patent ID: 8266385

Claim:
A method for caching data, which is to be written back to a main memory, in a cache memory in a memory apparatus, the memory apparatus comprising: a cache memory including a plurality of cache segments, memorizing, for each cache segment, validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component controlling access to the cache memory; and the method of the cache controlling component comprising the steps of: detecting, at a detecting component, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment; and issuing, for each area detected, a read command to the main memory, making each area a valid sector, and writing the data in the cache segment back to the main memory, wherein the validity data is a bit string in which logical values are arrayed, the logical values each indicating whether or not each sector is valid; and wherein detecting comprises steps of: a bit inverting section inputting the validity data read from the cache memory, and inverting or not inverting each of the bits of the validity data, and outputting them; a bit mask section inputting the validity data output from the bit inverting section, wherein when a mask pattern is set, the bit mask section masks the validity data with the mask pattern, and if no mask pattern is set, the bit mask section outputs the validity data unchanged; and a priority encoder detecting the highest-order bit whose logical value is true from the validity data output from the bit mask section, and outputting a bit position of the highest-order bit; and a controller changing the setting of the bit inverting section every time a bit position is input from the priority encoder and setting a mask pattern to the bit mask section, the mask pattern masking the bit string from the highest-order bit to the input bit position; and detecting the bit positions output from the priority encoder in sequence as boundaries between areas having consecutive invalid sectors and valid sectors.