Patent ID: 7087483

Claim:
A method for forming a single transistor planar RAM memory cell with improved charge retention comprising the steps of: providing a silicon substrate comprising an STI structure and an overlying dielectric gate layer; depositing a polysilicon layer; forming a pass transistor structure adjacent a planar storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second P− doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to form an ion implant mask fully covering the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; wherein the predetermined distance is less than twice the predetermined width; and, carrying out a second ion implantation process to form a P+ doped region in a second portion of the second doped region while retaining the P− doped region in the first doped region.