Patent ID: 7023442

Claim:
A system comprising: a clock generator configured to generate a source clock signal; and a plurality of video routers coupled in a linear series, wherein each video router VR(K) receives the source clock signal from the clock generator, and buffers the source clock signal to generate an output clock OC(K), wherein each video router in the linear series is connected to the next video router in the linear series by a set of connecting buses CB(K), and wherein K is a non-negative integer; wherein each video router VR(K), K=0, 1, . . . , N R −1 includes an output interface configured to transmit a stream S K of video data words onto the connecting bus CB(K), wherein the output interface transmits one video data word of the stream S K onto the connecting bus CB(K) in response to each triggering edge of the output clock OC(K), wherein the output interface buffers the output clock OC(K) to generate a synchronous clock SC(K) and transmits the synchronous clock SC(K) onto the connecting bus CB(K), wherein, for K=0, 1, . . . , N R −2, the connecting bus CB(K) conducts the stream S K and the synchronous clock SC(K) to the next video router VR(K+1), and wherein N R is the number of video routers; wherein each video router VR(K), K=1, 2, . . . , N R −1 includes a link interface buffer configured to receive the stream S K−1 of video data, words and the synchronous clock SC(K−1) from the connecting bus CB(K−1), wherein the link interface buffer is configured to receive and internally store one of the video data words of the stream S K−1 in response to each triggering edge of the synchronous clock SC(K−1), and wherein the link interface buffer is configured to generate a local stream LS(K) by accessing one of the internally stored video data words in response to each triggering edge of the output clock OC(K).