Patent ID: 6901070

Claim:
A switch comprising: a plurality of port blocks organized as an array of N number of rows and M number of columns each comprising: a plurality of I/O ports each including K number of P-bit wide output ports; and a plurality of memory cells each including a first pass gate for coupling a selected line of a first port block with a storage element and a second pass gate for coupling a selected line of a second port block with said storage element; read decoder circuitry for selecting one of said plurality of I/O ports of a first selected one of said plurality of port blocks and reading data from a selected memory cell of a second selected one of said plurality of port blocks, said read decoder comprising: for each of said N number of rows, M number of K ×1 multiplexers each for selecting one of K number of P-bit wide output ports from each of said port blocks of said M number of columns; and an N ×1 multiplexer for selecting one of N number of output ports selected by said M number of K ×1 multiplexers; and write decoder circuitry for selecting one of said plurality of I/O ports of a second selected one of said plurality of port blocks and writing data into a selected memory cell of said second selected port block.