Patent ID: 7375555

Claim:
An integrated circuit with a signal pad and circuit coupled thereto having higher voltage tolerance with lower voltage assist, comprising: an integrated circuit signal pad; a first N-channel metal oxide semiconductor (NMOS) transistor ( 142 ) having a drain coupled to the integrated circuit signal pad and a gate coupled to an operating voltage; a second NMOS transistor ( 128 ) having a source coupled to a power common and a drain coupled a source of the first NMOS transistor ( 142 ); a first P-channel metal oxide semiconductor (PMOS) transistor ( 126 ) having a drain coupled to the integrated circuit signal pad and the drain of the first NMOS transistor ( 142 ); a second PMOS transistor ( 124 ) having a drain coupled to a source of the first PMOS transistor ( 126 ), and a source of the second PMOS transistor ( 124 ) coupled to the operating voltage; a third PMOS transistor ( 122 ) having a drain coupled to the integrated circuit signal pad and a source coupled to a gate of the second PMOS transistor ( 124 ); a fourth PMOS transistor ( 114 ) having a drain coupled to the gate of the second PMOS transistor ( 124 ) and the source of the third PMOS transistor ( 122 ), the fourth PMOS transistor ( 114 ) having a source coupled to a five volt control signal; a third NMOS transistor ( 116 ) having a drain coupled to the gate of the second PMOS transistor ( 124 ) and the source of the third PMOS transistor ( 122 ), the third NMOS transistor ( 116 ) has a gate coupled to the operating voltage and a source coupled to the five volt control; a fourth NMOS transistor ( 120 ) having a source coupled to the integrated circuit signal pad and a gate coupled to the operating voltage; a fifth PMOS transistor ( 118 ) having a source coupled to the integrated circuit signal pad and a gate coupled to the operating voltage; drains of the fourth NMOS transistor ( 120 ) and the fifth PMOS transistor ( 118 ) are coupled to a gate of the fourth PMOS transistor ( 114 ); a gate of the first PMOS transistor ( 126 ) is coupled to a data out signal; a gate of the second NMOS transistor ( 128 ) is coupled to a data out enable signal; a first parasitic diode ( 132 ), the first parasitic diode ( 132 ) being formed between the source and the drain of the first PMOS transistor ( 126 ); and a second parasitic diode ( 134 ), the second parasitic diode ( 134 ) being formed between the source and the drain of the second PMOS transistor ( 124 ), wherein current flow through the second parasitic diode ( 134 ) drives the integrated circuit signal pad to substantially the operating voltage when the five volt control signal is at a logic 1 and the second parasitic diode ( 134 ) substantially prevents current flow from the integrated circuit signal pad to the operating voltage when the integrated circuit signal pad is at a voltage more positive than the operating voltage.