Patent ID: 7586358

Claim:
A level shifter comprising: a signal conversion unit which receives a first input signal having a predetermined period and a second input signal which is an inversion of the first input signal, wherein the signal conversion unit comprises: a first conversion unit which outputs a first output signal through a first output terminal and comprises; a first transistor which transfers a first voltage to the first output terminal; a first capacitor which turns the first transistor on and off according to the second input signal; and a second capacitor which increases a voltage of the first output terminal according to the first input signal; and a second conversion unit which outputs a second output signal through a second output terminal and comprises; a second transistor which transfers a second voltage to the second output terminal; a third capacitor which turns the second transistor on and off according to the second input signal; and a fourth capacitor which reduces a voltage of the second output terminal according to the first input signal; and an amplifying unit which receives the first and second output signals and generates a third output signal having an amplitude greater than the first input signal, wherein the first conversion unit further comprises: a third transistor which transfers the first voltage to a third output terminal according to the voltage of the first output terminal; and the second conversion unit further comprises: a fourth transistor which transfers the second voltage to a fourth output terminal according to the voltage of the second output terminal, wherein the first output signal has substantially a same phase as the first input signal and having a voltage higher than the first input signal; and the second output signal has substantially a same phase as the first input signal and having a voltage lower than the first input signal; wherein the amplitudes of the first and second output signals are substantially the same as those of the first and second input signals, respectively; and wherein a minimum voltage level of the first output signal is the first voltage which is higher than a minimum voltage level of the first input signal, and a maximum voltage level of the second output signal is the second voltage which is lower than a maximum voltage level of the first input signal and lower than the first voltage.