Patent ID: 7178115

Claim:
An LSI manufacturing method to avoid prototype-hold, comprising the following steps of: designing an LSI under an EDA (electronic design automation) environment to produce design data of a designed LSI; performing logic simulation on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of event based test vectors as a result of the logic simulation; producing test related data files with use of the design data and event based test vectors; producing an event tester simulator which simulates an operation of an event tester where the event tester simulator is software which runs on a computer system and the event tester is a physical system having tester hardware for testing physical LSIs; verifying the test related data files and the event based test vectors through the event tester simulator where the test related data in the test related data files include data concerning signal parameters and sockets that are unique to the event tester; producing a prototype LSI through a fabrication provider by using the design data; testing the prototype LSI by the event tester by using the event based test vectors and test related data files verified by the event tester simulator and debugging errors by event edits and feedbacking test results to design engineers and the fabrication provider; and wherein simulation test vectors in said test vector file are directly used in the event tester without data conversion or translation to be applied to the prototype LSI.