Patent ID: 8738932

Claim:
A system for providing processor-based security, comprising: a processor chip having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor chip, the processor chip encrypting data written to, and decrypting data read from, the external memory using the at least one encryption key and verifying data read from the external memory using the at least one hash value; and a hypervisor program executed by the processor chip, the hypervisor program and the processor chip creating a secure storage area for at least one trusted software module in response to launching of the at least one trusted software module, the hypervisor program and the processor chip creating a plurality of secure storage areas upon launching of a plurality of trusted software modules, wherein the plurality of secure storage areas comprises a first secure storage area in a non-volatile memory external to the processor chip, and the processor stores in the plurality of registers a second hash value and a second encryption key as trust anchors for the first secure storage area, and wherein the processor chip encrypts data written to, and decrypts data read from, the non-volatile memory using the second encryption key and verifies data read from the non-volatile memory using the second hash value.