Patent ID: 8156252

Claim:
An apparatus comprising: an interface configured to receive data for writing data to a storage system or for reading data from the storage system, the storage system having a plurality of memory modules; a plurality of memory controllers each coupled to the interface, wherein a memory module is coupled to each of the plurality of memory controllers; and a block data striper coupled to the interface and to the plurality of memory controllers wherein the block striper is operable for block striping data to write data to or to read data from a plurality of channels coupled with a plurality of storage devices or memory modules, and the block striper further comprises: an input receiving (i) an input logical block address (LBA) for a block of data, (ii) an input sector count for the block of data, and (iii) a read or write command for the block of data; a first divider unit configured for dividing the received input LBA by a number of channels of the plurality of channels to compute a first quotient result including: (i) an output divided LBA passed to each channel, and (ii) an output divided remainder (modulus); and a first logic unit using the output divided remainder (modulus) to determine a selected starting channel for a block striped read or write operation.