Patent ID: 8649201

Claim:
A memory device comprising: a memory cell array in which memory elements are arranged in matrix; and a writing circuit, wherein the memory element has a semiconductor film including two impurity regions, an insulating film over the semiconductor film, and an electrode over the insulating film; and wherein the writing circuit includes a voltage generating circuit for generating a voltage in order to apply to the memory element at plural times, a first switch, a second switch, a third switch, an output terminal, and a timing controlling circuit for controlling an output of the voltage, wherein a source or drain of each of the first, second and third switch is electrically connected to each other, wherein control signals from the timing controlling circuit are applied to a gate of each of the first, second and third switch, wherein the first switch is electrically connected to the timing controlling circuit and the output terminal, wherein the second switch is electrically connected to the voltage generating circuit and the output terminal, wherein the third switch is electrically connected to the voltage generating circuit and the output terminal, and wherein the source or drain of the first switch is electrically connected to a constant potential source.