Patent ID: 8103922

Claim:
An integrated circuit having at least one processing stage comprising: a speculative node; an output node; precharge circuitry coupled to said speculative node to precharge said speculative node; logic circuitry responsive to one or more input signals to provide a first discharge path in dependence upon values of said one or more input signals; complementary logic circuitry responsive to one or more complement input signals, said one or more complement input signals being complements of said one or more input signals, to provide a second discharge path in dependence upon said one or more complement input signals, such that combinations of said one or more input signals that provide said first discharge path do not provide said second discharge path and combinations of said one or more input signals that do not provide said first discharge path do provide said second discharge path; evaluation control circuitry responsive to at least one evaluation control signal to couple said speculative node to said logic circuitry to be discharged through said first discharge path in dependence upon said one or more input signals; an inverting circuit coupled to said speculative node and configured to charge said output node if said speculative node is discharged; wherein subsequent to coupling of said speculative node to said logic circuit, said evaluation circuit couples said output node to said complementary logic circuitry to be discharged through said second discharge path in dependence upon said one or more complementary input signals; and error detection circuitry coupled to said output node to detect an error when said output node is discharged through said complementary logic circuitry.