Patent ID: 7410855

Claim:
A method of manufacturing a semiconductor device comprising: forming an n-type semiconductor region and a p-type semiconductor region on a semiconductor substrate; forming a first gate dielectric layer above the n-type semiconductor region and the p-type semiconductor region; forming a second gate dielectric layer above the p-type semiconductor region, the second gate dielectric layer being made of an insulating material different from that of a the first gate dielectric layer; and forming a gate electrode layer on the first gate dielectric layer and the second gate dielectric layer, such that a relation: (χ B −χ A )×( d A +d B )≧3.9 is satisfied by electronegativity (χ A ) and an atomic radius (d A , a unit thereof is Å) of a metal element constituting the gate electrode layer and by electronegativity (χ B ) and an atomic radius (d B ) of an element having the highest binding energy to combine with the metal element constituting the gate electrode layer among elements constituting the portion of the first gate dielectric layer facing the gate electrode layer.