Patent ID: 7187597

Claim:
An integrated circuit, comprising: an array of memory cells; a data register coupled to the array of memory cells; an address register coupled to the array of memory cells; a controller coupled to the data register and to the address register; address storage coupled to the controller, the address storage configurable for storing an address associated with at least one defective memory cell of the array of memory cells within a group of memory cells of the array of memory cells; data storage coupled to the controller, the data storage configured to store configuration data associated with the group of memory cells of the array of memory cells, the configuration data being part of configuration information for configuration of the integrated circuit; and the controller configured to cause the address to be loaded into the address register and the configuration data to be loaded into the data register responsive to configuration of at least a portion of the array of memory cells and configured to maintain a write state for continually writing the configuration data to the group of memory cells of the array of memory cells as addressed responsive to the address during operation of the integrated circuit configured with the configuration information.