Patent ID: 7423465

Claim:
A duty cycle correction circuit for generating a correction signal for changing a phase relationship of first and second complementary clock signals to provide duty cycle corrected clock signals, the duty cycle correction circuit comprising: a first circuit operable to generate a first signal indicative of a time period of a high-cycle of the first clock signal; a second circuit operable to generate a second signal indicative of a time period of a low-cycle of the first clock signal; decode logic coupled to the first and second circuits and operable to monitor the first and second signals and generate delay adjustment signals in response to the first and second signals; logic circuitry coupled to the decode logic and operable to generate the correction signal to change the phase relationship of the first and second complementary clock signals by increasing and decreasing the phase by an incremental change in response to delay adjustment signals from the decode logic indicating an increase and decrease, respectively, in a difference between the time periods of the high- and low-cycles of the first clock signal approximately equal to twice the incremental change; and a counter circuit coupled to the decode logic and operable to count occurrences of active delay adjustment signals indicative of increasing and decreasing differences between time periods of the high- and low-cycles of the first clock signal, the counter circuit operable to count in a first direction in response to active adjustment signals indicative of an increasing difference and count in a second opposite direction in response to active adjustment signals indicative of a decreasing difference.