Patent ID: 7550790

Claim:
A semiconductor device comprising: 2 n semiconductor active layers, each of which having: a first connecting portion; a second connecting portion; a third connecting portion; (n+1) p-type impurity regions between the first connecting portion and the third connecting portion; (n+1) n-type impurity regions between the first connecting portion and the third connecting portion; and 2*n channel forming regions, each of which is between corresponding two of any one of the (n+1) p-type impurity regions and the (n+1) n-type impurity regions; 2*n gate electrode wiring lines, each of which is adjacent to corresponding one of the 2*n channel forming regions, with a gate insulating film interposed therebetween; 2 n gradation voltage lines, each of which is electrically connected to corresponding one of the 2 n semiconductor active layers in the first connecting portion and the second connecting portion; and an output line electrically connected to the 2 n semiconductor active layers in the third connecting portion, wherein n is a natural number larger than 1.