Patent ID: 7346161

Claim:
A cipher designing apparatus for designing cipher logic of a cipher device that effects cipher or decryption per block by using an F-function for converting input bits to output bits using a plurality of S-boxes, said cipher designing apparatus comprising: an input unit inputting a memory capacity of a high-speed referable memory provided to said cipher device, an entire inputting and outputting bit number being input to and output from said cipher device, and a minimum input and output bit number of said S-boxes as an initial value; a tentative decision unit dividing the entire input and output bit number by the initial value to acquire an integer quotient and an integer remainder, making a first set composed of the integer quotient pieces of the initial value, subtracting a number of one from the remainder integer number, when the remainder integer number is not zero, and adding the subtracted number of one to the initial value in the first set one by one until the integer value remainder becomes zero, so as to acquire a second set composed of integer numbers, and tentatively deciding the integer numbers in the second set as a tentative inputting and outputting bit number of S-box; a combining unit combining the integer numbers so as to make a third set of integer composed of combining integers; a selecting unit determining how many pieces of the combined integers are in the third set, repeating the tentative deciding, combining and determining until a number of the combined integer numbers become equal to a final number that is calculated based on the memory capacity and the entire inputting and outputting bit number, and selecting, when the number of the combined integer numbers becomes equal to the final number, the combined integers of the third set to be an optimal combination of input and output bit numbers of each of the S-box; a S-box generating unit generating a plurality of S-boxes each having the input and output bit number selected by said selecting unit.