Patent ID: 7177209

Claim:
A semiconductor memory device, comprising: a memory cell array divided into a plurality of row blocks and a plurality of repair blocks toward a row direction, wherein the respective row blocks and the respective repair blocks are divided into a plurality of segments toward a column direction; and a control circuit for storing a repair information of a defective cell and replacing a row segment of the row block including the defective cell with a repair segment of the repair block according to the repair information, by inputting a row address signal and a column address signal, the control circuit comprising: a block selecting circuit for outputting a block select signal to select a predetermined row block according to the row address signal; a fuse circuit for storing information of the repair block and the repair segment, and outputting a column select signal to select the repair segment and a row repair signal to select the repair block according to a result of comparing the row address signal and the column address signal with the information of the repair block and the repair segment; an enable circuit for outputting a block enable signal to enable a normal block and a redundancy block by logically combining the block select signal and the row repair signal; a row decoder circuit for enabling a predetermined word line of the normal block by decoding the block select signal and the row address signal; a redundancy row decoder circuit for enabling a predetermined word line of the repair block according to the row repair signal; a sense amplifier control circuit for controlling a sense amplifier to sense a data of a memory cell of a selected block according to the block enable signal; and a connection circuit for accessing a normal cell or a redundancy cell by connecting a segment input/output line with a local input/output line according to the row repair signal, the block enable signal, the column select signal and a column select summation signal.