Patent ID: 7149879

Claim:
A processor using parity check to switch instruction modes, capable of executing N-bit and 2N-bit mode instructions respectively in N-bit and 2N-bit modes, an N-bit mode instruction consisting of an N-bit word, a 2N-bit mode instruction consisting of two N-bit words, each N-bit word including P-bit parity and (N-P)-bit instruction code, P being an integer greater than or equal to 1, wherein the parity of each N-bit mode instruction is even parity such that corresponding N-bit word has an even number of one bits, and the parities of each N-bit word of each 2N-bit mode instruction are odd parities such that corresponding N-bit words have an odd number of one bits, the processor comprising: an instruction input device, which includes a memory having a width of 2N-bit for storing a plurality of 2N-bit words representing instructions; an instruction fetch device, which fetches a 2N-bit word from the instruction input device; and a mode switch logic, which determines whether the 2N-bit word fetched by the instruction fetch device is two (N-P)-bit instructions or one 2(N-P)-bit instruction, and accordingly switches the processor to be in corresponding N-bit or 2N-bit mode, wherein when the 2N-bit word fetched is on an even parity state, which is determined by first performing an XOR operation on two N-bit words included in the 2N-bit word to thereby obtain two results and then performing an XOR operation on the two results, the 2N-bit word is determined as two (N-P)-bit instructions if the two results indicate that the two N-bit words are on the even parity state, and determined as one 2(N-P)-bit instruction if the two results indicate that the two N-bit words are on the odd parity state.