Patent ID: 7843459

Claim:
A processor comprising: a first data path having a first bit width; a second data path having a second bit width greater than the first bit width; a plurality of third data paths having a combined bit width less than the second bit width; a wide operand storage coupled to the first data path and to the second data path for storing a wide operand received over the first data path, the wide operand having a size with a number of bits greater than the first bit width; a register file including registers having the first bit width, the register file being connected to the third data paths, and including a wide operand register for storage of a wide operand specifier which specifies both an address and the size of the wide operand; a functional unit capable of initiating only one instruction at a time, the functional unit coupled by the second data path to the wide operand storage, and coupled by the third data paths to the register file; and wherein the functional unit executes a single instruction containing instruction fields (i) specifying the wide operand register to cause retrieval of the wide operand for storage in the wide operand storage, (ii) a vector operand register in the register file, (iii) a control register in the register file, and (iv) a results register in the register file, the instruction causing the functional unit to perform a matrix multiply operation between matrix elements contained in the wide operand storage and vector elements contained in the vector register, the matrix elements and vector elements being of a size specified by the control register to thereby produce a plurality of results elements, and in which the functional unit also performs an extraction of the results elements under control of the control register to produce a value which is stored in the results register.