Patent ID: 7339416

Claim:
A low dropout voltage regulator comprising: a supply input terminal for connecting a supply voltage and an output terminal for providing a regulated output voltage; a reference voltage source; an output voltage monitor; an error amplifier having a first input connected to the reference voltage source, a second input connected to the output voltage monitor, and an output supplying an error signal in response to deviations of the regulated output voltage from a desired target output voltage value at the output terminal; a power output FET, having a gate terminal and a drain-source channel connected between the supply input terminal and the output terminal of the voltage regulator; a driver FET of a p-conductivity type, having a gate terminal connected to the control output of the error amplifier, a drain terminal connected to ground and a source terminal connected to the gate of the power output FET; and a current source ( 148 ; 348 ) supplying a drain-source current (I DS ) for the driver FET ( 140 ; 340 ), connected between the supply input terminal ( 102 ; 302 ) and the source terminal ( 144 ; 344 ) of the driver FET ( 140 ; 340 ); the gate terminal of the power output FET being controlled by the error amplifier via the driver FET in such a way that any deviations of the regulated output voltage from a desired target output voltage value are minimized; the regulator further comprising: a bypass FET of an n-conductivity type, having a source terminal connected to the gate terminal of the driver FET, a drain terminal connected to the source terminal of the driver FET, and a gate terminal connected to a bias voltage source, said bias voltage source providing a voltage determined such that the bypass FET begins conducting when the source voltage of the driver FET cannot be further reduced towards the drain potential by application of the error signal to its gate, due to the inherent gate-source voltage drop of the driver FET.