Patent ID: 7008848

Claim:
A method of fabricating a mask read only memory, comprising: forming a gate insulation layer over a semiconductor substrate; forming a first polysilicon layer over the gate insulation layer; forming photoresist patterns over the first polysilicon layer, which entirely cover a peripheral circuit region but are patterned in a cell array region to expose regions that are to become buried impurity diffusion regions; performing ion implantation using the photoresist patterns as a mask to form a plurality of buried impurity diffusion regions near the surface of the semiconductor substrate, wherein the buried impurity diffusion regions are formed in parallel, are separated from each other by a first predetermined interval, and extend in the same direction; removing the photoresist patterns, and sequentially stacking a second polysilicon layer and a metal silicide layer over the first polysilicon layer; and sequentially etching the first and second polysilicon layers and the metal suicide layer so as to form a plurality of word lines, wherein the word lines are formed in parallel, are separated from each other by a second predetermined interval, and extend in a direction perpendicular to that of the buried impurity diffusion regions.