Patent ID: 7551690

Claim:
A receiver comprising: a plurality antennas and tuning units for receiving and demodulating respective modulated signals each corresponding to a transmitted signal comprising a carrier modulated with a coded signal to thereby provide a plurality of corresponding demodulated coded signals, said coded signal comprising a digital signal train comprising a plurality of successive digital signals resulting from A/D conversion of an analog input signal, each of said digital signals comprising a plurality of bits arranged from a most significant bit to a least significant bit and including a higher-order bit and a lower-order bit therein, each of said digital signals being divided into a plurality of blocks arranged from a highest-order block, which includes the most significant bit, to a lowest-order block, which includes the least significant bit, the number of the bits in the highest-order block including the most significant bit being smaller than the number of the bits in the lowest-order block including the least significant bit, the number of the bits in each block of each digital signal being smaller than or equal to an adjacent lower-order block, each of said blocks having a parity bit attached thereto; parity check means to which said demodulated coded signals outputted from said plurality of demodulating means are inputted, said parity check means making a parity check on respective ones of said blocks of said demodulated coded signals; selecting means for selecting, from each set of corresponding blocks in said demodulated coded signals outputted from said plurality of demodulating means, a block judged to be error-free from the result of the parity check made by said parity check means; combining means for combining the blocks selected by said selecting means into one digital signal and outputting the one digital signal, wherein said combining means outputs successive combined digital signals corresponding to successive digital signals from said digital signal train; and memory means for storing therein a last one of said combined digital signals successively outputted from said combining means, said selecting means, when said parity check means judges that all of the corresponding blocks in each set contain error, selecting the corresponding block of said last one of said combined digital signals stored in said memory means.