Patent ID: 7089136

Claim:
A circuit for programming and testing electrical fuse (eFuse) circuits in a device, said circuit comprising: an eFuse circuit that includes a fuse, a blow device, and a control input for said blow device; first logic means for determining when to blow said fuse, wherein said first logic means comprises: a first latch component having multiple inputs and which provides a true output; a second latch component having multiple inputs and which provides both a second true output and a complement output; wherein said second latch component is programmed with a blow value for said fuse such that the blow value dictates when a fuse is to be blown; and an EFUSEPROGRAM signal that together with said true output and said second true output provides the control input to said blow device; second logic means for triggering a bypass of a pre-blow process within said eFuse circuit when said fuse is not to be blown, wherein a shifted 1 propagating through a plurality of eFuse circuits within said device is passed to a next downstream eFuse circuit without delay attributable to said pre-blow process; wherein said second logic means comprises: an AND gate having a first input coupled to said complement output of said second latch, a second input coupled to said program signal, and a result output; a multiplexer (MUX) having a first MUX input coupled to the true output of said first latch component, a second MUX input coupled to a selected output of a previous MUX of a third eFuse circuit sequentially before said eFuse circuit, a select input coupled to said result output of said AND gate, and a select output; and third logic means for maintaining the EFUSEPROGRAM signal in a logic low state during serial readout of fuse latches within a shift path, such that the MUX is forced to choose the input from a fuse latch of the circuit and the fuse latch is forced to be within the shift path regardless of the state of the pattern latch.