Patent ID: 8324064

Claim:
A method for forming a varactor diode having a first terminal and a second terminal, comprising: providing a substrate comprising a semiconductor having a first surface; providing a first mask on the first surface with openings extending to the first surface; forming cavities under the openings extending into the semiconductor a first distance, wherein the cavities have sidewalls and a bottom; creating at least one sub-isolation buried layer (SIBL) region beneath the bottom and part way up the sidewalls of at least one of the cavities; filling the cavities with a dielectric to create isolation regions in the cavities overlying the at least one SIBL region; and forming a varactor junction in the substrate laterally proximate but not intersecting a first isolation region, wherein a first side of the varactor junction is coupled to the first terminal and a second side of the varactor junction is coupled to the second terminal through the at least one SIBL region.