Patent ID: 7383397

Claim:
A snoop filtering method for supporting cache coherency in a computing environment having multiple processing units, each processing unit having one or more cache memories associated therewith and an associated snoop filter device, said method comprising the steps of: for each snoop filter device of a processing unit: providing a first scoreboard data structure having bit locations for tracking data that have been loaded into a cache memory of its associated processor in response to a cache miss; setting said bit locations in said first scoreboard data structure to indicate possibility of data located in said cache memory at a particular address; receiving snoop requests from one or more processing units and decoding an address of the received snoop request; comparing said decoded address against corresponding bits set in said first scoreboard data structure; and, forwarding said received snoop request to said associated processor in response to matching of a bit set in said first scoreboard data structure, or otherwise discarding said snoop request, determining a cache wrap detection condition by tracking whether every cache line has been overwritten with new cache line content in said cache memory since a prior detected cache wrap condition; and, providing a second scoreboard data structure having corresponding bit locations as said first scoreboard data structure; and, copying contents of first scoreboard data structure into said second scoreboard data structure upon detection of a cache wrap detection condition indicating all cache lines have been overwritten with new cache line content.