Patent ID: 7164170

Claim:
A recess gate transistor formed on a substrate having a device isolation film that defines an active region and a non-active region, the active region being sub-defined by a recess as a first active region and a second active region, the transistor comprising: a gate insulation layer formed with a predetermined thickness within the recess; a gate electrode surrounded by the gate insulation layer in a portion that is within the recess, the gate electrode extended from within the recess, the gate electrode having a first sidewall that is partially in contact with the gate insulation layer on the first active region, and having a second sidewall that is partially in contact with the gate insulation layer on the second active region; a first gate spacer having a predetermined horizontal thickness measured from a portion of the gate insulation layer in contact with the first active region, and which is formed on the first sidewall to have a predetermined depth from an upper surface of the first active region; a second gate spacer formed on the second sidewall, wherein the second gate spacer is disposed on an upper surface of the second active region; and a source region and a drain region formed mutually oppositely on the first and second active regions with the gate electrode therebetween.