Patent ID: 7610421

Claim:
A bus request control circuit provided in a signal processing circuit having highest priority of a plurality of processing circuits connected to an arbitration circuit, the bus request control circuit comprising: a request signal transmitting section which transmits a request signal to request a bus right to the arbitration circuit; a request acknowledge signal receiving section which receives a request acknowledge signal transmitted from the arbitration circuit in response to the request signal transmitted to the arbitration circuit; a large-capacity buffer memory to store data read from a memory; and a counting section which performs counting to measure time required for a signal processing circuit having a low priority in the arbitration circuit to request the bus right to the arbitration circuit, wherein when the buffer memory has free space for storing data, transmission of a next request signal from the request signal transmitting section is performed after the counting section ends the counting, and wherein a request for the bus right by the signal processing circuit having a low priority made anytime during the counting by the counting section is ensured priority over a request for the bus right by the signal processing circuit having highest priority.