Patent ID: 7039186

Claim:
An encryption key generation circuit for generating at least one 128-bit round sub key used in at least one sub round for encryption of 128-bit plaintext, from an encryption key having 64×n bits (2≦n≦4; where n is an integer), comprising: an exclusive OR circuit for calculating an exclusive OR of 1-bit information located at identical positions in 8-bit information included in each byte of the encryption key so as to generate 1-byte calculation information; a register for storing (8×n+1)-byte information represented by a sum of the encryption key having 8×n bytes and the 1-byte calculation information; a byte rotation circuit for performing byte rotation of rotating the (8×n+1)-byte information by 1 byte in each sub round of the at least one sub round; a 3-bit rotation circuit for performing 3-bit rotation of rotating bits in each byte of the (8×n+1)-byte information by 3 bits in each sub round; and 16 adders for adding a 128-bit bias value to (8×n)-byte information from the lowest byte of the (8×n+1)-byte information processed with the byte rotation and the 3-bit rotation, so as to generate one of the at least one 128-bit round sub key in each sub round.