Patent ID: 7795666

Claim:
A semiconductor time switch comprising: a semiconductor substrate; a cell portion provided on the semiconductor substrate and including a first input/output terminal, a second input/output terminal and a pseudo control gate terminal, the cell portion including, a plurality of linear semiconductor layers formed on the semiconductor substrate in parallel with each other in a first direction and serving as active areas, one end of each linear semiconductor layer being connected to the first input/output terminal and the other end being connected to the second input/output terminal in the cell portion, a plurality of first gate insulating films formed on the linear semiconductor layers, a plurality of first linear conductor layers formed on the first gate insulating films in parallel with each other, extended in a second direction crossing the first direction, and serving as control gates, a plurality of second linear conductor layers formed on the first gate insulating films in parallel with each other, extended in the second direction, and arranged alternately with the first linear conductor layers, floating gates inserted in intersections of the linear semiconductor layers and the first linear conductor layers, provided on the first gate insulating films, and coupled to the first linear conductor layers through inter-gate insulating films, and first selecting transistors inserted between one end portion of the linear semiconductor layers and the first input/output terminal, and second selecting transistors inserted between an other end portion of the linear semiconductor layers and the second input/output terminal, a source region of each first selecting transistor is connected to the first input/output terminal, and a drain region of each second selecting transistor is connected to the second input/output terminal; and an electron booster provided on the semiconductor substrate and connected to the pseudo control gate terminal, the electron booster including a MOS transistor having a first source region and a first drain region formed on the semiconductor substrate, a second gate insulating film formed on a semiconductor region between the first source region and the first drain region, and a booster gate electrode formed on the second gate insulating film, the booster gate electrode being connected to the second linear conductor layers through the pseudo control gate terminal of the cell portion.