Patent ID: 8090191

Claim:
A method for inspection and fault analysis, comprising: delivering a test pattern as an input to a semiconductor chip; at the time of delivering said test pattern as an input, scanning and illuminating said semiconductor chip with a laser beam, so that said semiconductor chip is heated; generating an image to visualize resistance changes in said semiconductor chip resulting from said scanning and illuminating step; and determining a presence or absence of an abnormal current route, based on said image generated in said generating step, wherein said steps of scanning and illuminating said semiconductor chip and generating an image are carried out under a first condition, wherein, if the presence of said abnormal current route has been determined in said determining step, a second scanning and illuminating step is conducted upon said semiconductor chip under a second condition and a second image is generated for visualizing resistance changes in said semiconductor chip under said second condition, and wherein, after carrying out said step of generating a second image under said second condition, a second determining step is carried out for detecting a presence or absence of an abnormal current route conducting an abnormal IDDQ in said semiconductor chip based on said second image, said first condition being a condition with a higher speed than in said second condition.