Patent ID: 7284138

Claim:
An apparatus, comprising: a system logic unit coupled to receive a clock (CLK) signal and a power save mode acknowledge (PSM_ACK) signal, wherein the PSM_ACK signal is asserted in a power saving mode, and wherein the system logic unit is configured to perform a function dependent upon the CLK signal and to produce a clock enable (CLK_EN) signal in response to the PSM_ACK signal; enable logic coupled to receive the PSM_ACK signal and the CLK_EN signal, and configured to selectively produce one of a MUX enable signal and a MUX disable signal dependent upon a selected combination of the PSM_ACK signal and the CLK_EN signal; a multiplexer (MUX) coupled to the enable logic and configured to receive the MUX enable signal and to select one of a plurality of PLL frequency inputs, and to generate a CLK signal in response to the selected one of a plurality of PLL frequency inputs and the MUX enable signal; and a phased locked loop (PLL) unit coupled to the MUX and a reference clock (REF_CLK) signal, and configured to use the REF_CLK signal to produce the plurality of PLL frequency inputs to the MUX.