Patent ID: 7095265

Claim:
An integrated circuit comprising: a. a clock tree having: i. a clock root node; ii. first and second clock destination nodes; iii. a first plurality of adjustable clock buffers disposed in series between the root node and the first clock destination node, each of the first plurality of adjustable clock buffers including a clock-adjust port; and iv. a second plurality of adjustable clock buffers disposed in series between the root node and the second clock destination node, each of the second plurality of adjustable clock buffers including a clock-adjust port; and b. a control circuit coupled to the clock-adjust ports of the first and second pluralities of clock buffers, the control circuit having: i. an adjustable delay section having an input node coupled to the clock root node, a delay-section output node, and a delay-adjust port; and ii. a phase detector coupled to the clock root node, the delay-section output node, and the delay-adjust port.