Patent ID: 7069363

Claim:
A bus comprising: a master interface connectable to a master device external to said bus and configured to (i) receive an early command signal from said master device with an early timing relationship to a first clock edge of a system clock and (ii) present a bus wait signal to said master device, wherein said early timing relationship comprises validity both a set-up time before and a hold-time after a respective edge of said system clock; a slave interface connectable to a slave device external to said bus and configured to (i) present a command signal to said slave device with a standard timing relationship to said first clock edge, (ii) present said early command signal to said slave device with said early timing relationship to said first clock edge and (iii) receive a slave wait signal from said slave device, wherein said standard timing relationship comprises a delay after said respective clock edge; and a control logic configured to (i) register said early command signal with said first clock edge to generate said command signal, (ii) multiplex said early command signal to said slave interface and (iii) multiplex said slave wait signal into said bus wait signal.