Patent ID: 7224594

Claim:
A glitch protect valid cell for maintaining a desired logic state value in response to a glitch signal and a timing signal, the glitch protect valid cell is electrically coupled to a content addressable memory (CAM) array, differential bit lines for providing a true valid bit and its complement, a logic element for providing the glitch signal, and a clockline for providing the timing signal, the glitch protect valid cell comprising: a memory element, the memory element is electrically coupled to the bit lines and stores an initial state value of the true valid bit and the complement valid bit; a state machine, the state machine is responsive to the memory element and stores the previous logic state value of the true valid bit from the memory element; and a glitch protect circuit electrically coupled to the memory element and the state machine, the glitch protect circuit including a propagation delay assembly and a restore assembly electrically coupled to the propagation delay assembly, the propagation delay assembly includes a glitch and timing signal dependent logic gate and a first pull down network electrically coupled to the glitch and timing signal dependent logic gate and the memory element, the first pull down network is responsive to the glitch signal and the timing signal to selectively engage the glitch and timing signal dependent logic gate, particularly, in a glitch protect condition, the first pull down network resets the initial state value of the true valid bit according to the timing signal and the glitch signal, the state machine and the first pull down network respectively provide to the glitch and timing signal dependent logic gate a previous state value and the reset value, the restore assembly includes a second pull down network electrically coupled to the propagation delay assembly and the memory element, in the glitch protect condition, the second pull down network is responsive to a pull up network selectively enabled within the glitch and timing signal dependent logic gate and resets the complement valid bit in the memory element, via the timing signal and a restore signal provided by the glitch and timing signal dependent logic gate indicating the enabled pull up network, thereby restoring the initial state value of the true valid bit.