Patent ID: 7026209

Claim:
A method for fabricating a DRAM array, comprising: patterning a semiconductor substrate to form rows and columns of pillars thereon; forming a capacitor on a lower portion of a sidewall of each pillar; partially filling spaces between the pillars with a first insulating material to cover the capacitors; forming a gate structure of a transistor on the sidewall of each pillar above the first insulating layer, wherein a method for forming the gate structure comprises steps of: forming a gate insulating layer on the sidewall of each pillar above the first insulating material; forming a conductive layer between the pillars and on the first insulating material, the conductive layer having a top surface lower than the top surface of the pillar; forming a mask spacer an the sidewall of each pillar above the conductive layer; forming a mask layer comprising a plurality of linear patterns over the substrate, wherein each linear pattern runs over the pillars in one column; and etching the conductive layer using the mask spacer and the mask layer as a mask to form a gate electrode on the sidewall of each pillar, wherein the gate electrodes on the pillars in one column are connected via the conductive layer between the pillars of the same column to form a gate line; forming a first doped region of a transistor in the sidewall of each pillar coupling with the capacitor on the sidewall of the same pillar; forming a second doped region of a transistor in a top portion of each pillar; filling the spaces between the pillars with a second insulating material to cover the transistors; forming a plurality of bit lines over the substrate, wherein each bit line is electrically connected to the second doped regions of the transistors in one row; and forming a plurality of word lines over the substrate, wherein each word line is coupled with the gates of the transistors in one column.