Patent ID: 8694572

Claim:
A circuit for performing decimal floating-point fused-multiply-add (FMA) calculation of ±A×B±C, comprising: a formulation unit configured to generate a multiplicand significand, a multiplicand exponent, a multiplier significand, a multiplier exponent, an addend significand, and an addend exponent by decoding a multiplicand, a multiplier, and an addend, respectively, according to a decimal floating-point format comprising a plurality of binary-coded-decimal (BCD) digits, wherein the multiplicand, the multiplier, and the addend are represented by A, B, and C, respectively; a decimal FMA core coupled to the formulation unit and comprising: a shifter configured to shift the addend significand based on the multiplicand exponent, the multiplier exponent, and the addend exponent to generate an aligned addend significand; a partial product generator configured to generate a plurality of partial products from the multiplicand significand and the multiplier significand concurrently with generating the aligned addend significand; and an adder configured to generate an intermediate result significand by: when ±A×B and ±C have a same sign indicating an addition: adding the plurality of partial products and the aligned addend significand; and when ±A×B and ±C have opposite signs indicating a subtraction: adding the plurality of partial products and a nine's complement of the aligned addend significand; and a result generator coupled to the decimal FMA core and configured to: selectively increment the intermediate result significand to convert the nine's complement into a ten's complement when ±A×B and ±C have opposite signs; and generate a result of the FMA calculation based on the intermediate result significand.