Patent ID: 7424660

Claim:
A circuit for testing multiple memories, comprising: a first BIST controller within an integrated circuit, wherein the first BIST controller is coupled with at least a first memory, the first BIST controller comprising a BIST address port for coupling the first BIST controller to the first memory; a second BIST controller within the integrated circuit, wherein the second BIST controller is coupled with at least a second memory; a third BIST controller within the integrated circuit, wherein the second BIST controller is coupled with at least a third memory; a fourth BIST controller within the integrated circuit, wherein the fourth BIST controller is coupled with at least a fourth memory; a first resume input on the integrated circuit for receiving a first resume signal, wherein the first resume input is coupled in parallel to at least the first BIST controller and the second BIST controller, wherein the first BIST controller is responsive to the first resume signal to resume testing of the first memory and the second BIST controller is responsive to the first resume signal to resume testing of the second memory; and a second resume input on the integrated circuit for receiving a second resume signal, wherein the second resume input is coupled in parallel to at least the third BIST controller and the fourth BIST controller, wherein the third BIST controller is responsive to the second resume signal to resume testing of the third memory and the fourth BIST controller is responsive to the second resume signal to resume testing of the fourth memory.