Patent ID: 7634706

Claim:
An error recovery system including: a bit detector that detects bits in a data signal and assigns values of 1 and 0 to the detected bits; accumulators that determine counts of the numbers of times respective bits are assigned values of 1 in re-reads of the data signal; a data reconstruction processor that assigns values of 1 to respective bits with associated counts that are greater than a majority detection threshold and values of 0 to respective bits with associated counts that are less than the majority detection threshold, sets flags for bits with values of 1 and associated counts that are less than a predetermined upper threshold and for bits with values of 0 and associated counts that are greater than a predetermined lower threshold, groups the bits into symbols and sets erasure pointers to identify the locations of a predetermined number, s, of the symbols that are associated with the highest degree of uncertainty in the detected bits; and an error and erasure decoder that corrects the s symbols in the identified locations as erasures and detects and corrects up to 2 ⁢ t - s 2 errors using a distance d error correction code, where the minimum distance d min =2t+1.