Patent ID: 7750723

Claim:
A voltage generation circuits comprising: a reference voltage generation circuit including: a first reference terminal from which a first reference voltage is output, and a second reference terminal from which a second reference voltage lower than the first reference voltage is output; an output circuit including: an output terminal from which an output voltage is output, a first PMOS transistor connected between a first power supply line of a high level and the output terminal, and a first NMOS transistor connected between the output terminal and a second power supply line of a low level; a first operational amplifier including: a first inverting input terminal including a gate of a PMOS transistor to be connected to the second reference terminal, a first non-inverting input terminal including a gate of a PMOS transistor to be connected to the output terminal, and a first output terminal connected to a gate of the first PMOS transistor; a second operational amplifier including: a second inverting input terminal including a gate of an NMOS transistor to be connected to the first reference terminal, a second non-inverting input terminal including a gate of an NMOS transistor to be connected to the output terminal, and a second output terminal connected to a gate of the first NMOS transistor; a first switch that connects one of the first reference terminal and the second reference terminal to the first inverting input terminal; a second switch that connects one of the first reference terminal and the second reference terminal to the second inverting input terminal; a third switch that connects one of the first output terminal and the second output terminal to the gate of the first PMOS transistor; and a fourth switch that connects one of the first output terminal and the second output terminal to the gate of the first NMOS transistor.