Patent ID: 7426253

Claim:
A method for counting events in a computer system comprising: providing a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of said hybrid counter array; setting an overflow bit means associated with each respective counter device in response to an associated counter device reaching an overflow condition; providing a second counter portion comprising a memory device having N addressable memory locations in correspondence with said N counter devices, each said addressable memory location being for storing a second count value for a respective counter device representing higher order bits of said hybrid counter array; monitoring, by a control means, each of said N associated overflow bit means of said first counter portion and initiating incrementing a value of a corresponding said second count value stored at said corresponding addressable memory location in said second counter portion in response to detecting a respective overflow bit being set; resetting said overflow bit means after detecting a respective overflow bit being set; and, comparing a second incremented count value against a pre-determined threshold value, and asserting an interrupt signal in response to said incremented second count value being equal to a pre-determined threshold value.