Patent ID: 8493808

Claim:
A memory device for use in a serial interconnection configuration comprising a plurality of memory devices connected in-series, each of the memory devices being addressable based on device identification (ID), the memory device comprising: a receiver configured to receive an input port enable signal, a serial input signal and an output port enable signal, the receiver comprising: a first input buffer configured to receive the input port enable signal and to provide an internal input enable signal; a second input buffer configured to receive the serial input signal and to provide an internal serial input signal; and a third input buffer configured to receive the output port enable signal and to provide an internal output enable signal; and an output provider configured to output a serial output signal, an echo of the input port enable signal and an echo of the output port enable signal, the output provider comprises: logic circuitry configured to receive the internal serial input signal and the internal input enable signal, and provide an input signal to a first flip-flop; and a selector configured to receive an output signal of the first flip-flop, receive an internal serial output signal, receive an ID match signal, and select the output signal from the first flip-flop when the ID match signal is de-asserted or select the internal serial output signal when the ID match signal is asserted.