Patent ID: 7087442

Claim:
Process for the formation of a spatial chip arrangement including a plurality of rigid chips, each of the plurality of chips having a peripheral connection surface, arranged in several planes and electrically connected to one another, comprising the steps of arranging at least two flexible carrier substrates with their conducting-path structures comprising a plurality of conducting paths located opposite one another, carrying out the arrangement by means of clamping device accommodating ends of the carrier substrates in order to fix the carrier substrates with their conducting paths located opposite one another, connecting the rigid chips via their peripheral connection surfaces to assigned conducting paths of the conducting-path structures of the flexible carrier substrates by the chips being arranged transverse to a longitudinal extent of the carrier substrate, wherein a connecting material is first applied in the form of isolated deposits of soldering material onto the conducting paths and/or the connection surfaces and is then activated by melting in order to connect the conducting-paths and the connection surfaces via the melted soldering material, the spatial chip arrangement being built up by means of a sandwich type layering of the rigid chips and connecting the rigid chips to the flexible substrates subsequently.