Patent ID: 8385119

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array comprising a plurality of bit-lines, a plurality of word-lines intersecting the bit-lines, a source-line, and a plurality of NAND cell units, each NAND cell unit comprising a plurality of memory cells connected in series, each memory cell comprising a control gate connected to one of the word-lines, each NAND cell unit comprising ends connected to one of the bit-lines and the source-line, respectively; a data write portion configured to write data to the memory cell array by repeating a write loop until the data write is complete, the write loop comprising a program operation of applying a selected word-line of the word-lines with a program voltage necessary for program and a verify operation of applying the selected word-line with a verify voltage necessary for verify, the program voltage being changed for each write loop by a predetermined step width, the data write being performed in units of a page comprising a plurality of memory cells selected by the selected word-line; and an endurance determination portion configured to determine the endurance of the memory cells of the page, the data write portion supplying the selected word-line with a program voltage of a step width depending on the endurance.