Patent ID: 8441128

Claim:
A semiconductor arrangement comprising: a circuit carrier comprising a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer; a bonding wire; at least N half bridge circuits wherein N≧1, each half bridge circuit comprising: a first circuit node, a second circuit node and a third circuit node; a controllable first semiconductor switch comprising a first main contact electrically connected to the first circuit node, a second main contact electrically connected to the third circuit node, and a gate contact for controlling an electric current between the first main contact and the second main contact; a controllable second semiconductor switch comprising a first main contact electrically connected to the second circuit node, a second main contact electrically connected to the third circuit node, and a gate contact for controlling an electric current between the first main contact and the second main contact; wherein the first semiconductor switch and the second semiconductor switch of each of the half bridge circuits are arranged on that side of the first metallization layer facing away from the second insulation layer; the bonding wire is directly bonded to the intermediate metallization layer at a first bonding location.