Patent ID: 7996203

Claim:
A system for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies and a cache controller, comprising: a processor for executing instructions from memory; a testcase generator configured to generate a plurality of instruction streams, each instruction stream having an instruction address; wherein the instruction address has a plurality of operand fetch addresses within a prefetch boundary; and wherein instructions in the plurality of instruction streams loop back to corresponding instruction addresses for the instructions; a queue configured to store information relating to the plurality of instruction streams; a simulation application; wherein when the operand address for a particular instruction of the plurality of instruction streams has more than three strides, the simulation application records the strides of the particular instruction in the queue; wherein when the processor issues a fetch command, if the simulation application determines that a fetch command operand address for a line of the processor matches an operand address in the queue, the fetch command being issued by the processor is marked in the queue; the simulation application being configured to search the queue for a first operand address having more than three strides and having the biggest stride when the processor issues a prefetch command, wherein: if the first operand address having more than three strides in the queue does not match a prefetch command operand address of the prefetch command, the simulation application issues an error message; if there is a match, the simulation application marks the prefetch command being sent in the queue; and if, subsequently, the fetch command is issued on the prefetch command operand address, the simulation application issues an error message to indicate that the prefetch command operand address has already been prefetched.