Patent ID: 8053316

Claim:
A method of fabricating a vertical channel transistor, comprising: forming an active pattern having a line type on a substrate so as to extend in a first horizontal direction; patterning the active pattern to form a vertical channel that is spaced apart in the first horizontal direction from other vertical channels; and forming a buried bit line extending in the first horizontal direction on the substrate; wherein the forming of the active pattern includes forming a first trench extending in the first horizontal direction on the substrate, and filling the first trench with a first insulating layer to form an active bar extending in the first horizontal direction; wherein the forming of the buried bit line includes: before forming the vertical channel: forming a buried bit line pattern offset with at least one side surface of the active bar by cutting the first insulating layer in the first horizontal direction, forming a liner on an inner sidewall of the buried bit line pattern, forming a damascene buried bit line pattern in the buried bit line pattern by removing a part of the active bar which is not protected by the liner, and forming a metal buried bit line extending in the first horizontal direction in the damascene buried bit line pattern and connected electrically to at least one side surface of the active bar; and forming a word line extending in a second horizontal direction along at least one side surface of the vertical channel, the second horizontal direction intersecting the first horizontal direction.