Patent ID: 7245530

Claim:
A semiconductor memory device comprising: memory cells each of which includes a first MOS transistor and a second MOS transistor, the first MOS transistor including a source, a drain and a first stacked gate which includes a floating gate formed on a semiconductor substrate with a first gate insulating film interposed therebetween and a control gate formed on the floating gate with a first inter-gate insulating firm interposed therebetween, and the second MOS transistor including the source, the drain connected to the source of the first MOS transistor and a second stacked gate which includes a first gate electrode formed on the semiconductor substrate with a second gate insulating film interposed therebetween and a second gate electrode formed on the first gate electrode with a second inter-gate insulating film interposed therebetween, the second gate electrode being in an electrically floating state; bit lines each of which is connected to the drains of the first MOS transistors; source lines each of which is connected to the sources of the second MOS transistors; a memory cell array in which the memory cells are arranged in a matrix; word lines each of which is formed by connecting commonly the control gates of the first MOS transistors in a same row; select gate lines each of which is formed by connecting commonly the second stacked gates of the second MOS transistors in a same row; and metal wiring layers which are formed so as to correspond to the select gate lines, wherein the memory cell array includes first regions in which the memory cells are formed and second regions each of which is formed between adjacent first regions, at least part of the second gate electrode and second inter-gate insulating film of the second MOS transistor are removed in the second regions, exposing the top surface of each of the first gate electrodes, and the metal wiring layers are each connected electrically to the first gate electrode of the corresponding one of the select gate lines by a contact plug in the second region.