Patent ID: 7116149

Claim:
A duty cycle correction circuit of, comprising: a differential amplifier, which receives and amplifies differential reference clock signals through a first input terminal and a second input terminal, and outputs differential output signals to a first differential output terminal and a second differential output terminal, respectively; a first transmission circuit, which is connected between the first differential output terminal and a first node, and transmits a signal of the first differential output terminal to the first node, in response to transmission control signals; a second transmission circuit, which is connected between the second differential output terminal and a second node, and transmits a signal of the second differential output terminal to the second node, in response to the transmission control signals; a first storage unit, which is connected between the first node and a ground voltage and accumulates electric charges on the first node; a second storage unit, which is connected between the second node and the ground voltage and accumulates electric charges on the second node; and a current control circuit, which controls an amount of electric charges accumulated in the first storage unit and an amount of electric charges accumulated in the second storage unit, in response to a combination of duty cycle switching signals and corresponding current switching control signals.