Patent ID: 8331177

Claim:
A semiconductor memory device, comprising: a memory cell array including memory cells each having a variable resistance element, the memory cells arranged at intersections of a plurality of first lines and a plurality of second lines, respectively; a first control circuit configured to apply a first voltage to a selected first line; and a second control circuit configured to apply a second voltage having a voltage value higher than that of the first voltage to a selected second line, the first control circuit including a detecting circuit configured to detect a leak current to flow from the second line to the first line through a memory cell during a forming operation for bringing the memory cell into a state that allows the memory cell to shift between a high resistance state and a low resistance state, and the second control circuit including: a current supply circuit configured to supply a constant current to the second line during the forming operation; and a compensating circuit configured to supply a compensating current having the same current value as that of the leak current to the second line during the forming operation based on the leak current detected by the detecting circuit.