Patent ID: 7512872

Claim:
A test apparatus that tests a device under test, comprising: a reference clock generator that generates a reference clock for the test apparatus; a first variable delay circuit that delays a data signal output from the device under test by a designated time to output the delayed signal as a delay data signal; a second variable delay circuit that delays a clock signal showing a timing at which the data signal should be acquired, which is output from the device under test, by a designated time to output the delayed clock signal as a first delay clock signal; a first flip-flop that acquires the delay data signal at a timing based on the reference clock; a second flip-flop that acquires the first delay clock signal at a timing based on the reference clock; a first delay adjusting section that adjust a delay amount of at least one of the first variable delay circuit and the second variable delay circuit so that the first flip-flop and the second flip-flop acquire the delay data signal and the first delay clock signal at a timing at which the signals are changed; a third variable delay circuit that delays the clock signal by a designated time to output the delayed clock signal as a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on a result obtained by acquiring the first delay clock signal of which a phase is adjusted by the first delay adjusting section at a timing at which the second delay clock signal is changed, in order to adjust a phase difference between the first delay clock signal and the second delay clock signal to a desired phase difference; and a deciding section that decides the good or bad of the signal output from the device under test based on a result obtained by acquiring the delay data signal at a timing at which the second delay clock signal is changed.