Patent ID: 8410537

Claim:
A nonvolatile semiconductor memory device comprising: a semiconductor layer of a first general conductive type; a first element isolation layer and a second element isolation layer that are formed adjacent to each other in the semiconductor layer so as to elongate in a first direction in plan view of the memory device; a trench disposed between the first and second isolation layers and comprising a first sidewall and a second sidewall opposite from the first sidewall, in the plan view of the memory device the first sidewall being parallel to a second direction that is perpendicular to the first direction and the second sidewall slanting from the second direction; a source layer of a second general conductive type formed in the second sidewall of the trench and a bottom portion of the trench; a first insulation film disposed on the first and the second sidewalls of the trench and on the bottom portion of the trench; a floating gate disposed on the first insulation film in the trench; a control gate disposed on the semiconductor layer so as to overlap the first and second element isolation layers partially in the plan view of the memory device, the control gate overlapping the floating gate partially; and a second insulation film disposed between the control gate and the floating gate.