Patent ID: 7652513

Claim:
A data retention apparatus comprising: a first latch for latching a data input and transmitting a data output; and a second latch coupled to the first latch for retaining the data input while the first latch is inoperative in a standby power mode, wherein the second latch includes: a second latch inverter having an inverter input and an inverter output; a switching circuit coupled to the inverter output, the inverter input, and a retention signal, wherein the switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal, wherein the logic state is in accordance with the data input retained in the standby power mode; a standby power source operable to provide power in the standby power mode, the standby power source being coupled to the second latch inverter and the switching circuit; an output generating circuit having an input coupled to the inverter output and an output coupled to the data output, wherein the output generating circuit is inoperative in the standby power mode.