Patent ID: 8349708

Claim:
A method for manufacturing integrated circuits, comprising the steps of: providing the integrated circuits on the wafer, the integrated circuits on a wafer comprising: a wafer substrate; a plurality of integrated circuits formed lattice-like in rows and columns on the wafer substrate; first and second saw lines separating the integrated circuits, the first saw lines running parallel and equidistant with respect to each other in a first direction defined by the rows, and the second saw lines running parallel and equidistant with respect to each other in a second direction defined by the columns; and a plurality of process control modules formed on the wafer substrate such that a given process control module of the plurality of process modules is bounded by two consecutive first saw lines as well as by two consecutive second saw lines; detecting the process control modules on the wafer substrate utilizing an alignment detecting device of a separating device; aligning the separating device in response to the detected process control modules; and guiding the separating device along the saw lines; wherein detecting the process control modules includes utilizing light shining through a bottom surface of the wafer substrate, the bottom surface of the wafer substrate being opposite to a surface of the wafer substrate on which the integrated circuits are formed, and wherein the separating device is guided on the bottom surface of the wafer substrate along the saw lines.