Patent ID: 8296602

Claim:
A processor comprising: a plurality of processing sections, each of which executes a predetermined process; a plurality of fault detecting circuits respectively provided for said plurality of processing sections, to detect a fault in one of said plurality of processing sections, to identify the one of the plurality of the processing sections as a fault processing section, and to generate a fault detection signal identifying the fault processing section; a fault monitoring and control section configured to select and control a normal processing section among said plurality of the processing sections other than the fault processing section to execute a relieving process in response to said fault detection signal; and a memory section including a plurality of memory regions which are respectively used for the plurality of processing sections and a common memory region which is commonly accessed by the plurality of processing sections, wherein the normal processing section executes the relieving process based on a process program stored in the common memory region when the normal processing section receives a relieving process instruction from the fault monitoring and control section, wherein the processor is a semiconductor integrated circuit in one chip.