Patent ID: 7543291

Claim:
A processor purging system, comprising: a translation lookaside buffer (TLB) resident on a processor and having a plurality of translation pairs; a component resident on the processor; and logic configured to receive a purge signal and to make a determination whether any of the translation pairs in the TLB corresponds to the purge signal, the logic configured to purge, in response to the purge signal, one of the translation pairs in the TLB if any of the translation pairs in the TLB corresponds to the purge signal, the logic further configured to determine, based on whether any of the translation pairs in the TLB corresponds to the purge signal, whether to search the component resident on the processor for information related to an address indicated by the purge signal, the logic further configured to purge the information from the component in response to the purge signal if any of the translation pairs in the TLB corresponds to the purge signal.