Patent ID: 7937633

Claim:
A system-in-package type semiconductor device comprising: a logic chip; and a memory chip connected with external terminal through said logic chip, wherein said logic chip comprises a data holding circuit configured to hold a test data in a test mode, stores the test data supplied through a data input/output terminal in said data holding circuit in response to a test data set command, and writes the test data which has been stored in said data holding circuit in said memory chip in response to a test data write command, wherein the data holding circuit is configured to only hold data to be written in said memory chip, wherein said logic chip reads the test data stored in said memory chip as a read test data in response to a test data read command, and outputs the read test data through said data input/output terminal, wherein said data holding circuit comprises a plurality of registers, which hold a plurality of the test data corresponding to different test patterns, and wherein said data holding circuit comprises a selector which selects one of said plurality of registers in response to a register selection instruction externally supplied from said logic chip.