Patent ID: 8575763

Claim:
A semiconductor device comprising, a first semiconductor chip including a first surface, a second surface opposite to the first surface, a side surface joined to the first and second surfaces to define an edge thereof, and a first electrode formed on the second surface; a first seal that seals the side surface and includes a lower surface which is substantially coplanar with the second surface of the first semiconductor chip; a rewiring layer formed over the second surface of the first semiconductor chip and at least a part of the lower surface of the first seal, and electrically connected to the first electrode of the first semiconductor chip; a second semiconductor chip stacked over the first surface of the first semiconductor chip; and a second seal that seals at least a first gap between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a second electrode formed on the first surface, the second electrode being electrically connected to the first electrode, and the second semiconductor chip includes a third electrode formed on a third surface thereof, the second semiconductor chip is stacked over the first surface of the first semiconductor chip so that the third electrode is electrically connected to the second electrode of the first semiconductor chip.