Patent ID: 7594215

Claim:
A method for improving the routability of one or more nets of an electronic circuit design, comprising: receiving data of a ball grid array (BGA), including pin location information; receiving net data, including net position information; associating net position information with pin location information such that connection paths are identified; determining whether there exists an intersection among the connection paths by traversing one or more rings; determining whether reassignment of a net position relative to a pin location would result in at least one of: an elimination of the intersection among the connection paths, a shorter connection path, and an resolution of an overloaded channel by moving one or more of the connection paths to another channel with available capacity; creating or updating a routing solution for the electronic circuit design by modifying at least one of said net data and said data of the ball grid array based at least in part on the act of determining whether there exists an intersection, wherein the act of creating or updating the routing solution is performed by a computer processor; and storing the routing solution on a computer readable storage medium or a storage device or displaying the routing solution on a display apparatus.