Patent ID: 6949943

Claim:
A method for in-line electrical testing of a flip-chip semiconductor assembly during its manufacture, the method comprising: providing one or more integrated circuit (IC) dice, each with a surface having interconnection bumps thereon; providing a printed circuit board (PCB) with conductive epoxy pads deposited on a surface thereof for flip-chip attachment to the interconnection bumps of the one or more IC dice; providing an in-line electrical test socket for connection to the PCB; inserting the PCB into the in-line electrical test socket; positioning the one or more IC dice on the surface of the PCB with the interconnection bumps of the one or more IC dice in conductive contact with the conductive epoxy pads of the PCB to form the flip-chip semiconductor assembly while the PCB is inserted into the in-line electrical test socket; attaching the one or more IC dice to the PCB; while the PCB is inserted in the in-line electrical test socket and before encapsulation of the one or more IC dice, electrically testing the flip-chip semiconductor assembly using the in-line electrical test socket; repairing the flip-chip semiconductor assembly if it fails the electrical testing; and encapsulating the one or more IC dice of the flip-chip semiconductor assembly.