Patent ID: 7779180

Claim:
A semiconductor device comprising: a plurality of data processing modules; a controller that controls the data processing modules; a memory module that provides a work area for the data processing modules and the controller; and a bus that allows the controller to access to the data processing modules and the memory module, wherein each of the data processing modules comprises: a core module that performs data processing on input data and generates output data; a translate data interface that receives the input data and outputs the output data; a property interface that receives parameter data to be used in the data processing performed by the core module, and outputs information regarding the core module; an open/close interface that initializes an environment and a state for the data processing performed by the core module, and releases the environment; and a query interface that notifies static entries of the translate data interface, the property interface, and the open/close interface, to the controller for enabling the controller to access the translate data interface, the property interface, and the open/close interface, in a common procedure with respect to other ones of the data processing modules, wherein the property interface receives the parameter data defined by a character string or a numerical string, and wherein the core module is configured to represent a functionality selected from various types of processing functionality in accordance with the parameter data received by the property interface.