Patent ID: 8169072

Claim:
A semiconductor device comprising: a reinforcing board having a first face and a second face; an electronic part accommodating portion configured to penetrate the reinforcing board; a through hole configured to penetrate the reinforcing board; an electronic part configured to have a front face on which an electrode pad is formed and a back face, and be accommodated into the electronic part accommodating portion; a through electrode configured to be installed inside the through hole; a first sealing resin configured to fill a gap between the through electrode and an inner wall of the through hole; a second sealing resin configured to be filled into the electronic part accommodating portion while causing a bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside; and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode, the second sealing resin is configured to cover the electronic part inside the electronic part accommodating portion while causing the bonding face of the electrode pad to be exposed to the outside, the through electrode has a first bonding face arranged on the first face of the reinforcing board, and the bonding face of the electrode pad, the first face of the reinforcing board, the first bonding face of the through electrode, and a first face of the second sealing resin and a face of the first sealing resin positioned on the first bonding face of the through electrode are arranged on one plane where the electrode pad and the through electrode are directly connected.