Patent ID: 8239158

Claim:
A system comprising: a host computer including a processor and memory storing program instructions; a measurement device coupled to the host computer, wherein the measurement device includes a programmable hardware element; wherein the program instructions are executable to cause the processor of the host computer to perform a plurality of iterations of a first loop, wherein each respective iteration of the first loop includes: an I/O phase during which the processor reads measurement data from the programmable hardware element, wherein the measurement data is acquired from a physical system coupled to the measurement device; and a control phase during which the processor uses measurement data read from the programmable hardware element to perform an algorithm; wherein the programmable hardware element is configured to perform a plurality of iterations of a second loop, wherein each respective iteration of the second loop includes: an active phase during which the programmable hardware element stores measurement data acquired from the physical system in memory of the programmable hardware element; and a delay phase during which the programmable hardware element does not store measurement data in the memory of the programmable hardware element; wherein the program instructions are further executable to cause the processor of the host computer to synchronize the second loop performed by the programmable hardware element with the first loop performed by the processor by communicating with the programmable hardware element to adjust a length of the delay phase for one or more iterations of the second loop.