Patent ID: 6980021

Claim:
An output buffer for driving a capacitively-terminated transmission line having a characteristic impedance Z 0 and which conveys data bits during respective unit intervals, said output buffer arranged to generate a waveform which varies with said data bits, said waveform comprising: a first portion during which said waveform transitions from a first voltage V 1 to a second voltage V 2 between a time t 1 and a time t 2 ; a second portion during which said waveform remains fixed at said second voltage V 2 until a time t 3 ; a third portion during which said waveform transitions to a voltage V 3 between V 1 and V 2 between time t 3 and a time t 4 ; and a fourth portion during which said waveform remains fixed at said third voltage V 3 until a time t 5 ; said output buffer arranged to generate said waveform within a unit interval whenever successive data bits transition from a first logic state to a second logic state; said output buffer arranged to have an output impedance Z 1 much less than Z 0 when generating said first and second output buffer waveform portions such that voltage V 2 is maximized, and arranged to have a non-zero output impedance Z 2 greater than Z 1 when generating said fourth output buffer waveform portion to absorb transitions reflected back to said buffer by said capacitive termination.