Patent ID: 8354319

Claim:
A method of fabricating a planar field effect transistor (FET) and a multiple gate FET (MUGFET) together in a multiple layer substrate, comprising: etching an upper layer in the substrate to form a first active device region for the MUGFET and a pair of second active device regions for the planar FET; filling etched regions in the upper layer of the substrate with a shallow trench isolation (STI) material to form a plurality of STI filled regions; forming a plurality of trenches in the first active device region; forming a first gate region for the MUGFET over a portion of the first active device region; and forming a second gate region for the planar FET over a portion of the pair of second active device regions, wherein forming a first gate region for the MUGFET over a portion of the first active device region and forming a second gate region for the planar FET over a portion of the pair of second active device regions comprises forming a dielectric layer on top of the upper layer in the substrate, forming a gate layer on top of the dielectric layer, and etching the gate layer and the dielectric layer at selective locations to form the first and second gate regions; and wherein top surfaces of each of the STI filled regions, the first active device region for the MUGFET, the plurality of trenches in the first active device region, and the second active device regions are all co-planar with respect to one another.