Patent ID: 8349669

Claim:
A thin film transistor fabrication method, comprising: depositing a gate dielectric layer over a gate electrode and a substrate; forming an active channel over the gate dielectric layer, the forming comprising: depositing one or more gate control layers comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, indium, tin, cadmium and gallium having a first composition, at least one or the one or more gate control layers is in contact with the gate dielectric layer; depositing one or more bulk layers in contact with at least one of the one or more gate control layers, the one or more bulk layers comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, indium, tin, cadmium and gallium having a second composition different than the first composition; and depositing one or more back channel interface control layers in contact with at least one of the one or more bulk layers, the one or more back channel interface control layers comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, indium, tin, cadmium and gallium having a third composition different than one or more of the first composition and the second composition; depositing a conductive layer on the topmost layer of the one or more back channel interface control layers; and patterning the conductive layer to define source and drain electrodes and expose the topmost layer of the one or more back channel interface control layers.