Patent ID: 7928756

Claim:
A method of reducing I/O noise, comprising reducing the current flowing in an I/O driver after a non-zero time delay following a high-to-low or low-to-high signal change, while maintaining at least some current flow through the I/O driver at all times, wherein the I/O driver includes PMOS and NMOS driver transistors the gates of which are fed by a pre-driver in the form of a NAND gate that includes a first PMOS transistor connected in parallel with a second PMOS transistor and having their outputs connected to the gate of the PMOS driver transistor, and a NOR gate that includes a first NMOS transistor connected in parallel with a second NMOS transistor and having their outputs connected to the gate of the NMOS driver transistor, the NAND and NOR gates each being connected between a power rail and ground, the method comprising controlling current flow through the NAND gate from the power rail to ground by connecting the outputs of the first and second PMOS transistors to ground via a first current control transistor, and controlling current flow through the NOR gate from the power rail to ground in order by connecting the outputs of the first and second NMOS transistors to the power rail via a second current control transistor.