Patent ID: 7873768

Claim:
An apparatus, comprising: a host computer including a plurality of ports and a processor for running an operating system having device drivers enabling communication over the plurality of ports: first and second memory devices, each memory device including data storage, a controller for controlling data transfer to and from the data storage, and a plug with contacts for disconnectably connecting with the power, ground, and data contacts of an independent port of the host computer; and interconnections between the first and second memory devices to provide for communication of data between the controllers of the first and second memory devices and to provide power to the controllers of the first and second memory devices when either or both of the first and second memory devices are plugged into one of the plurality of ports, wherein a rate of data transfer to the first and second memory devices over the first and second ports approaches an effective speed that is about twice the rate of data transfer for a single root hub when both of the first and second memory devices are plugged into the plurality of ports.