Patent ID: 8032688

Claim:
A memory integrated circuit comprising: an address decoder to selectively access memory cells within a memory array through a memory channel; a mode register including bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic coupled to a plurality of address signal lines, the address decoder, and the mode register, the control logic to support independent sub-channel memory access into the memory array through sub-channels of the memory channel by selectively accessing the memory array at different levels of granularity based on the enable bit and the at least one sub-channel select bit, wherein a first level of granularity of the different levels of granularity for a memory array access is an entire memory channel of the memory array when the enable bit is de-asserted, and a second level of granularity of the different levels of granularity for a memory array access is a subset of the entire memory channel of the memory array when the enable bit is asserted, and wherein the at least one sub-channel select bit is to assign the sub-channels of the memory array, and wherein the control logic includes a multiplexer to select one of the address signal lines of the memory channel address bus on which to capture independent address information, and wherein the multiplexer is further to swizzle the independent address information from a first significant address bit to a second significant address bit.