Patent ID: 8271824

Claim:
A memory interface circuit comprising: a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data strobe buffer configured to receive a data strobe signal supplied from said memory; a system clock synchronizing circuit configured to supply a data read from said memory to a logic circuit in synchronization with said system clock signal; and a delay detecting circuit provided at a front stage to said system clock synchronizing circuit and configured to detect a transmission delay from said clock signal supply buffer to said data strobe buffer, wherein said delay detecting circuit generates a phase difference data indicating said transmission delay based on a difference between a phase of said system clock signal and a phase of said data strobe signal outputted from said data strobe buffer, and supplies said phase difference data to said system clock synchronizing circuit, wherein said system clock synchronizing circuit generates a read clock signal by shifting said system clock signal based on said phase difference data, and controls a supply timing at which said data is supplied to said logic circuit, based on said read clock signal, and wherein said delay detecting circuit specifies a rising timing and a falling timing of said data strobe signal based on a mask signal which deactivates said data strobe signal, and generates said phase difference data based on an effective period of said data strobe signal which is determined based on the specified rising timing and the specified falling timing.