Patent ID: 8691703

Claim:
A method of manufacturing a semiconductor device, comprising: forming first gate lines and second gate lines over a semiconductor substrate, wherein the second gate lines are arranged at wider intervals than each of the first gate lines; forming a multi-layered insulating layer over an entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines, and between the first and the second gate lines; forming a mask pattern on the remaining multi-layered insulating layer, wherein the mask pattern covers the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layer not covered by the mask pattern to expose the first gate lines and the second gate lines, wherein the multi-layered insulating layer remains lower between the first gate lines than between the second gate lines.