Patent ID: 8906764

Claim:
A method of forming an NVM cell and a logic transistor using a semiconductor substrate, comprising: in a non-volatile memory (NVM) region, forming over the semiconductor substrate a first high-k gate dielectric, an NVM work function setting metal, a metal select gate, and a first dielectric layer, wherein the work function setting layer is on the first high-k gate dielectric, the metal select gate is on the work function setting layer, a top surface of the first dielectric layer is substantially aligned with a top surface of the metal select gate, and the first dielectric layer has a first opening in which the work function setting layer and the metal select gate are present in the first opening; in a logic region, forming over the semiconductor substrate a second high-k gate dielectric, a logic work function setting metal, a metal logic gate, a source and a drain in the semiconductor substrate, and a second dielectric layer, wherein the logic work function setting metal is on the second high-k gate dielectric, a top surface of the second dielectric layer is substantially aligned with a top surface of the metal logic gate, the second dielectric layer has a second opening in which the logic work function setting metal and the metal logic gate are present in the second opening, and the metal logic gate is on the logic work function setting metal; removing the first dielectric layer in the NVM region while leaving the second dielectric layer in the logic region; forming a charge storage layer comprising nanocrystals over the NVM region including over the metal select gate; forming a metal layer over the charge storage layer; patterning the metal layer to form a control gate; and etching the charge storage layer to leave a remaining portion of the charge storage layer aligned to the control gate.