Patent ID: 7971081

Claim:
An apparatus comprising: processor cores; volatile memory to act as system memory for the processor cores; a smaller non-volatile memory to hold system context information copied from the volatile memory; a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores; power management logic to control at least some aspects of power management; and an embedded processor to control transfer of system context data between the volatile memory and the smaller non-volatile memory, the embedded processor being independent of the processor cores and of a platform state of the apparatus; wherein, in response to a suspend to volatile memory power state change command, the apparatus causes a system context to be saved by the operating system to a contiguous region of the volatile memory and provides a setting to indicate a hibernate state, wherein the setting causes an interrupt resulting in the embedded processor shutting down the processor cores and copying the system context from the volatile memory to the smaller non-volatile memory, followed by the embedded processor powering down the volatile memory and placing the embedded processor in a power down state; and wherein, in response to a resume command, the embedded processor and the processor cores are wakened, the embedded processor initializes the volatile memory and copies at least a portion of the system context from the smaller non-volatile memory to the volatile memory.