Patent ID: 8067269

Claim:
A method for fabricating transistors, each transistor comprising a plurality of epitaxial layers on a common substrate, the method comprising: forming a plurality of source contacts on a first surface of the plurality of epitaxial layers; forming at least one drain contact on the first surface; forming at least one gate contact on the first surface; forming at least one layer of insulating material over and between the at least one gate contact, the plurality of source contacts and the at least one drain contact for insulating the at least one gate contact, the plurality of source contacts and the at least one drain contact; forming a conductive layer over and through at least a part of the at least one insulating layer, the conductive layer connecting the plurality of source contacts; forming at least one seed layer on the conductive layer; and forming at least one heat sink layer over the at least one seed layer; and wherein the at least one seed layer is configured to buffer stresses of thermal expansion caused by the at least one heat sink layer.