Patent ID: 7847316

Claim:
A semiconductor device comprising a lower semiconducting element, a lower electrode layer formed on an upper surface of said lower semiconducting element, an upper electrode layer formed on an upper surface of said lower electrode layer, an upper semiconducting element secured on an upper surface of said upper electrode layer, and an adhesive layer for bonding said upper electrode layer and upper semiconducting element, wherein the upper surfaces of said lower and upper electrode layers are formed of different materials from each other, the upper surface of said lower semiconducting element has a cell-forming region arranged at a central area of the upper surface in said lower semiconducting element and a cell-free region annularly arranged on an outer periphery of said lower semiconducting element to surround the cell-forming region by the cell-free region, said cell-forming region having a plurality of cells functionable as semiconductively active regions, and said cell-free region having no cell, the upper electrode layer has a notch on said cell-free region in said lower semiconducting element to form a bonding region on the upper surface of said lower electrode layer over said cell-free region, said bonding region being exposed to outside of the upper electrode layer through said notch to attach a lead wire on said bonding region, and the upper semiconducting element is secured on the adhesive layer over the cell-forming region of said lower semiconducting element.