Patent ID: 7676768

Claim:
A method of logic design for routing an asynchronous signal, said method of logic design comprising: receiving a specification of a clock signal; receiving a specification of a plurality of destination storage elements clocked by said clock signal; receiving a specification of an asynchronous signal to be routed to said destination storage elements; placing a logic design comprising the clock signal, the plurality of destination storage elements, and the asynchronous signal; and, physically synthesizing by using a computer a routing of the asynchronous signal in the placed logic design to each of the destination storage elements, said routing comprising: selecting a distribution network that routes the output from a distribution buffer to each of said destination storage elements; and inserting at least one pipeline storage element inserted between the source of said asynchronous signal and said distribution buffer that is clocked by said clock signal, whereby said asynchronous signal arrives at each of said destination storage elements within a same clock cycle of said clock signal.