Patent ID: 7821796

Claim:
A substrate for an integrated circuit package, comprising: a core comprising a dielectric layer with a pattern of large-diameter conductive vias extending therethrough from a top side to a bottom side of the core, wherein the large-diameter conductive vias include signal-bearing vias and voltage plane vias; a first top insulating layer disposed on the top side of the core; a top transmission line reference plane metal layer disposed on a top side of the first top insulating layer; a second top insulating layer disposed on a top side of the top transmission line reference plane metal layer; a top signal layer having top conductive paths routed above tops of the large-diameter conductive vias and connected through the first and second top insulating layer and the top transmission line reference plane metal layer to the top side of the signal bearing vias, wherein the top transmission line reference plane metal layer provides a reference plane for transmission lines formed by the top conductive paths, wherein the top transmission line reference plane metal layer defines voids extending above a top area of the signal-bearing vias so that capacitive coupling between top ends of the signal-bearing vias and the top transmission line reference plane metal layer is substantially reduced, wherein at least some of the top conductive paths extend across the top area of the signal-bearing vias, and wherein the top transmission line reference plane metal layer includes conductive stripes extending through the voids underneath the at least some top conductive paths and above the corresponding signal-bearing vias, to isolate the at least some conductive paths from the signal-bearing vias.