Patent ID: 8411494

Claim:
A magnetic random access memory comprising: a transistor comprising a gate width, the transistor is formed on a substrate and is electrically coupled to a word line; a plurality of memory layers sequentially disposed above the substrate, each memory layer comprising a plurality of magnetoresistive elements, each magnetoresistive element comprising an element width, a pinned layer comprising a fixed magnetization direction directed substantially perpendicular to the substrate, a free layer comprising a reversible magnetization direction directed substantially perpendicular to the substrate in its equilibrium state, and a tunnel barrier layer residing between the pinned layer and the free layer; a plurality of conductor layers disposed alternately with the memory layers beginning with a memory layer positioned adjacent to the substrate, each conductor layer comprising a plurality of parallel bit lines overlapping the word line, the plurality of bit lines being disposed adjacent to the free layer and independently electrically coupled to the plurality of magnetoresistive elements at first terminals; wherein the gate width is substantially larger than the element width, and wherein the plurality of magnetoresistive elements are jointly electrically coupled to the transistor at second terminals.