Patent ID: 7566923

Claim:
A platform application specific integrated circuit (ASIC) having a base layer comprising: a predefined input/output (I/O) region comprising a plurality of first pre-diffused regions disposed in said base layer; a predefined core region comprising (i) a plurality of second pre-diffused regions disposed in said base layer and (ii) one or more metal layers defining a plurality of power regions, wherein said plurality of power regions are electrically isolated from each other and said one or more metal layers on said base layer are deposited such that each of said plurality of power regions is connected to a respective one of a plurality of supply voltages; and an R-cell transistor fabric, said R-cell transistor fabric comprising a plurality of R-cells, each R-cell including multiple diffusions, a gate layer and a metal layer forming a five-transistor cell, said five-transistor cell including two n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs), two p-channel metal oxide semiconductor (PMOS) FETs, one small PMOS device, and contact points, wherein said contact points are attached to power, ground, inputs and outputs via upper metal layers.