Patent ID: 7272027

Claim:
A digital signal processor, comprising: a content addressable memory (CAM) array having a plurality of rows of CAM cells; an array of storage elements having a plurality of rows of the storage elements coupled to the CAM array, each row of storage elements to store a number corresponding to a data word stored in one of the rows of the CAM cells; and priority logic coupled to the array of storage elements, the priority logic to provide to a plurality of priority signal lines an indication of a location of a particular number in the array of storage elements, wherein the priority logic comprises: a first plurality of compare circuits, each compare circuit coupled to one of the storage elements in the array of storage elements, and each compare circuit having a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the plurality of priority signal lines; and a delay circuit coupled to each of the first plurality of compare circuits.