Patent ID: 8149882

Claim:
A bus system, comprising: at least one superordinate unit; one or more subordinate units; and an information bus for communication of one or more standard messages between the at least one superordinate unit and the one or more subordinate units, wherein, each standard message is configured as a data block comprising an address field and a data field for communication of address and data information, and a header field, including a plurality of synchronization fields and at least one status field, positioned in front of the address and data fields, wherein one or more initial synchronization frames are constantly exchanged between the units, with each synchronization frame comprising characters ‘X’ and ‘Y’ in alternative fashion, and with the ‘X’ and ‘Y’ characters being assigned bit values of ‘1’ and/or ‘0’, and wherein, for a real-time transmission of a time-critical message from a first unit to a second unit, the first unit generates a new synchronization frame by changing the bit values of one or more of the ‘X’ and ‘Y’ characters in a one of the initial synchronization frames, and transmits the new synchronization frame to a third unit.