Patent ID: 7416956

Claim:
A method of fabricating an integrated circuit, comprising: forming a trench isolation region in a substrate between a first portion of a layer formed above said substrate and a second portion of said layer formed above said substrate, said forming includes forming a first trench portion in said substrate between said first and second potions of said layer and a second trench portion in said substrate between said first and second portions of said layer, said first and second portions of said layer are formed prior to forming said trench isolation region, said second trench portion is formed subsequent to said first trench portion, said first trench portion includes a first sidewall, a second sidewall, and a bottom; forming a first sidewall spacer on said first sidewall and a second sidewall spacer on said second sidewall prior to forming said second trench portion, wherein forming said second trench portion includes etching said substrate between said first sidewall spacer and said second sidewall spacer at said bottom of said first trench portion to form said second trench portion below said first trench portion; growing a first dielectric material to at least partially fill said second trench portion; removing said first sidewall spacer and said second sidewall spacer after growing said first dielectric material; and depositing a second dielectric material to at least partially fill said first trench portion after removing said first sidewall spacer and said second sidewall spacer.