Patent ID: 8445353

Claim:
A method for integrating a metal-insulator-metal (MIM) capacitor and a thin film resistor in an integrated circuit, the method comprising: providing a semiconductor wafer substrate; depositing a first dielectric layer outwardly of the semiconductor wafer substrate; the first dielectric layer having a top surface; depositing a first metal layer outwardly of the first dielectric layer, touching the top surface of the first dielectric layer; patterning the first metal layer with a design corresponding to the structure of the integrated circuit being manufactured, wherein portions of the first metal layer are separated by separator openings etched down to the top surface of the first dielectric layer; also wherein a portion of the first metal layer forms a bottom plate for the MIM capacitor; depositing a second dielectric layer outwardly of the first metal layer wherein the second dielectric layer forms an insulator for the MIM capacitor; depositing a second metal layer outwardly of the second dielectric layer, the second metal layer having a top surface, wherein a first portion of the second metal layer forms a top plate for the MIM capacitor and a first contact pad for the thin film resistor, and wherein a second portion of the second metal layer forms a second contact pad for the thin film resistor, the MIM capacitor and the thin film resistor coupled in parallel; depositing a third dielectric layer outwardly of the second metal layer, and planarizing the third dielectric layer to expose the top surfaces of the top plate of the MIM capacitor and the first and second contact pads for the thin film resistor; forming a thin film resistor layer of the thin film resistor outwardly of and in electrical contact with the first and second contact pads; etching the thin film resistor layer such that a continuous portion of the etched thin film resistor layer physically contacts surfaces of the first and second contact pads; depositing a fourth dielectric layer outwardly of the thin film resistor layer and the top plate of the MIM capacitor, and planarizing the fourth dielectric layer; and forming multiple filled conductive vias outwardly of the second metal layer, each contact pad electrically connected to at least one of the filled conductive vias; wherein, after formation of the filled conductive vias, the thin film resistor layer is located between the filled conductive vias.