Patent ID: 7602599

Claim:
A method of making a metal-metal capacitor, comprising: providing a substrate; forming, in the order of, a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer over the substrate; forming a first mask layer covering the third metal layer, patterning the first mask layer to expose a portion of the third metal layer; etching the portion of the third metal layer exposed and the underlying second dielectric layer using the first mask layer as a mask and allowing the etching to stop at the second dielectric layer while not penetrating therethrough, thereby forming an upper capacitor structure comprising a second metal layer, a second dielectric layer, and a third metal layer; forming a second mask layer covering the third metal layer and the second dielectric layer, patterning the second mask layer to expose a portion of the second dielectric layer; etching the portion of the second dielectric layer exposed, the underlying second metal layer and the underlying first dielectric layer using the second mask layer as a mask and allowing the etching to stop at the first dielectric layer while not penetrating therethrough, thereby forming a lower capacitor structure comprising a second metal layer, a first dielectric layer, and a first metal layer; removing the second mask layer; forming a third mask layer covering the third metal layer, the second dielectric layer, and the first dielectric layer, patterning the third mask layer to expose a portion of the first dielectric layer, wherein the third mask layer is anti-reflective; etching the portion of the first dielectric layer exposed, the underlying first metal layer and the substrate using the third mask layer as a mask and allowing the etching to stop at the substrate, thereby forming the border of the metal-metal capacitor and a metal interconnect conductive wire comprising the first metal layer, wherein the metal-metal capacitor is separated from the metal interconnect conductive wire by a trench; depositing an inter-metal dielectric layer covering the third mask layer and filling the trench, planarizing the inter-metal dielectric layer; and; etching the inter-metal dielectric layer and the third mask layer to form at least one via hole on the first metal layer, the second metal layer, and the third metal layer.