Patent ID: 7541272

Claim:
A method of forming a solder bump connection at a metallic bonding pad surface of a semiconductor chip, said method comprising the steps of: a) forming a patterned passivation layer upon said metal bonding pad surface, said patterned passivation layer including an opening at said metallic bonding pad surface to define a location for said solder bump connection; b) forming a barrier material stack including top and bottom conductive material layers upon said patterned passivation layer, said barrier material stack conforming to a surface of said patterned passivation layer; c) removing top conductive material layer portion of said stack adjacent said solder bump connection location so that a top conductive material layer portion at said solder bump connection location defines a surface that is substantially coplanar with a surface of remaining bottom conductive material layers adjacent said solder bump connection location; d) forming a patterned resist material layer upon said substantially coplanar surface, said patterned resist material layer including an opening at said defined solder bump connection location; e) forming a diffusion barrier layer upon said substantially coplanar surface defined by said patterned resist material layer opening; f) providing solder material upon a surface of said diffusion barrier layer and between patterned walls defining said patterned resist material layer opening; g) removing the patterned resist material layer and removing remaining bottom conductive material layer portions of said barrier material stack under said patterned resist layer; and, h) reflowing the solder material to form said solder bump connection, wherein said bottom conductive material layer adjacent said solder bump connection exhibit decreased amount of undercut under said diffusion barrier layer to enable reduced pitch and increased mechanical stability of said solder bump connection.