Patent ID: 7612422

Claim:
A dual work function semiconductor device, comprising: a semiconductor substrate conductively doped to form a PMOS region and an NMOS region; a first patterned portion of a layer of dielectric material formed over the PMOS region; a first patterned portion of a layer of metal gate electrode material formed on the first patterned portion of the layer of dielectric material; implanted electronegative species at a metal surface of the first patterned portion of the layer of metal gate electrode material at a first interface of the first patterned portion of the layer of metal gate electrode material and the first patterned portion of the layer of dielectric material, wherein a first plurality of interface dipoles is formed at the first interface to provide the first patterned portion of the layer of metal gate electrode material with an increased work function value; a second patterned portion of the layer of dielectric material formed over the NMOS region; a second patterned portion of the layer of metal gate electrode material formed on the second patterned portion of the layer of dielectric material; and implanted electropositive species at a metal surface of the second patterned portion of the layer of metal gate electrode material at a second interface of the second patterned portion of the layer of metal gate electrode material and the second patterned portion of the layer of dielectric material, wherein a second plurality of interface dipoles is formed at the second interface to provide the second patterned portion of the layer of metal gate electrode material with a decreased work function value.