Patent ID: 8886840

Claim:
An integrated circuit (IC) chip, comprising: an attachment unit interface (XAUI) configured to receive 3 Gigabit (3 Gbit) serial data via a plurality of channels; a digital core configured to convert the 3 Gbit serial data received via the plurality of channels to 10 Gigabit (10 Gbit) serial data; and a physical media dependent (PMD) interface configured to provide the 10 Gbit serial data directly to an optical PMD for transmission over an optical network, wherein the IC chip is configured to: switch between at least one internally generated reference clock and at least one externally generated reference clock to support a transmission of the 10 Gbit serial data based upon an asynchronous mode or a synchronous mode; and operate in the synchronous mode by utilizing the at least one internally generated reference clock and operate in the asynchronous mode by utilizing the at least one externally generated reference clock.