Patent ID: 8877523

Claim:
A method of packaging an integrated circuit die, the method comprising: forming a first panel comprising a first plurality of integrated circuit die, wherein the first plurality of integrated circuit die are encapsulated in the first panel; separating the first plurality of integrated circuit die from the first panel if a threshold number of the first plurality of integrated circuit die are not properly placed within the first panel, wherein a determination of whether the threshold number of the first plurality of integrated circuit die are not properly placed is performed prior to formation or provision of an electrically conductive coupling to any of the first plurality of integrated circuit die, and said separating is performed prior to the formation or provision of an electrically conductive coupling to any of the first plurality of integrated circuit die; forming a second panel after said separating, the second panel comprising a second plurality of integrated circuit die, wherein the second plurality of integrated circuit die are encapsulated in the second panel, and the second plurality of integrated circuit die comprises at least one integrated circuit die of the first plurality of integrated circuit die separated from the first panel; and forming a plurality of electrically conductive interconnects over the second panel, wherein the plurality of electrically conductive interconnects are coupled to conductive structures of the second plurality of integrated circuit die of the second panel.