Patent ID: 8116118

Claim:
A random access memory cell comprising: at least a plurality of symmetrical dual-gate transistors coupled to storage nodes and forming a flip-flop, each of the plurality of symmetrical dual-gate transistors having two gates; at least a first asymmetric dual-gate access transistor and at least a second dual-gate access transistor disposed respectively between a first bit line and a first storage node, and between a second bit line and a second storage node, a first gate of the first access transistor and a first gate of the second access transistor being connected to a first word line able to route a biasing signal, a second gate of the first access transistor being connected to the second storage node and a second gate of the second access transistor being connected to the first storage node, wherein each gate of a dual-gate transistor is made of at least a block based on at least one gate material, each dual-gate transistor having its first gate, a semiconductor active zone and its second gate superimposed or juxtaposed on a support, and wherein each asymmetric dual-gate transistor is such that the current delivered between the drain and the source of the transistor is different depending on whether the first gate or the second gate is activated, for an identical biasing, and wherein each symmetrical dual-gate transistor is such that the current delivered between the drain and the source of the transistor is identical depending on whether the first gate or the second gate is activated, for an identical biasing.