Patent ID: 8670269

Claim:
A resistive memory device comprising: a memory cell array including a plurality of memory cells arranged in a memory block defined by a plurality of rows, each row including a word line connecting memory cells; a control circuit configured to control a test operation, a normal write operation, and a weak write operation, as selectively applied to memory cells in the memory cell array; and a current supplying circuit that generates a first write current and a second write current having a higher level than the first write current, wherein the control circuit is further configured to distinguish normal memory cells from weak memory cells among the plurality of memory cells during the test operation, the weak memory cells being relatively poorly magnetized as compared with the normal memory cells, and the control circuit is still further configured to control application of the first write current to the normal memory cells during the normal write operation, and application of the second write current to the weak memory cells during the weak write operation.