Patent ID: 7562107

Claim:
A mixed-type adder wherein when an overall bit width of a mantissa and a summand is n, the overall bit width is divided into I bit groups (where, I is a positive number larger than 1), which are respectively allocated to I sub adders in sequence, the I sub adders having different carry propagation schemes, the respective sub adders including: a carry input unit Cin that linearly receives carry signals transferred from a previous adder; a carry output unit Cout that performs an addition operation of allocated bit values and the carry input signals and then linearly outputs the generated carry signals to a subsequent adder in the different carry propagation schemes; and a sum output unit that outputs a sum added in the respective adders; wherein the mixed-type adder uses an adder intellectual property (IP) having bit width parameters adjusted such that the sum of width of I bits is the overall bit width.