Patent ID: 7989863

Claim:
A semiconductor device, comprising: a lower interlayer dielectric layer disposed on a substrate; a first landing pad formed in the interlayer dielectric layer to contact the substrate; a second landing pad formed in the interlayer dielectric layer to contact the substrate, where the second landing pad includes a metal silicide layer and is spaced apart from the first landing pad; an interconnection pattern disposed on the lower interlayer dielectric layer to cover the second landing pad, the interconnection pattern including an intermediate dielectric layer, wherein the lower interlayer dielectric layer and the intermediate dielectric layer partially surround the metal silicide layer; an etch stop layer formed to cover sidewalls of the interconnection pattern and to cover a portion of the lower interlayer dielectric; an upper interlayer dielectric layer disposed on the etch stop layer to fill a gap region adjacent to the interconnection pattern; and a buried contact plug formed in the upper interlayer dielectric layer and etch stop layer to contact the first landing pad in the gap region.