Patent ID: 8013393

Claim:
A device, comprising: a semiconductor-on-insulator (SOI) structure comprising a carrier wafer, a silicon substrate, and insulating layer is disposed between the carrier wafer and the silicon substrate, comprising: a first conductivity-type diode region disposed within the silicon substrate and that extends to the insulating layer, wherein the first conductivity-type is P + ; a first well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the first well device region is directly in series with and in physical contact with the first conductivity-type diode region, wherein the first well device region is a first P-well device region; a P + -type separation region disposed within the silicon substrate and that extends to the insulating layer, wherein the P + -type separation region is in series with the first well device region and has a single P + conductivity-type; a second well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the second well device region is in series with the P + -type separation region, wherein the second well device region is a second P-well device region; a second conductivity-type diode region disposed within the silicon substrate, wherein the second conductivity-type diode region is disposed within the silicon substrate and extends to the insulating layer, wherein the second conductivity-type diode region is in series with the second well device region, wherein the second conductivity-type is N + ; and a first gate electrode disposed overlying the first well device region of the silicon substrate; a second gate electrode disposed overlying the second well device region of the silicon substrate; a circuit to be protected from an electrostatic discharge event; and a bias circuit coupled to the first gate electrode and the second gate electrode, wherein the bias circuit comprises: means for applying a positive bias voltage to both the first gate electrode and the second gate electrode during normal operation, and stopping application of the positive bias voltage to both the first gate electrode and the second gate electrode in response to an electrostatic discharge event.