Patent ID: 8722472

Claim:
A method of forming a hybrid semiconductor structure comprising: providing a semiconductor on insulator substrate comprising a top semiconductor layer and a buried insulating layer; providing a material stack on top of the top semiconductor layer, the material stack including alternating layers of semiconductor material and sacrificial material, wherein the bottommost layer of the patterned material stack is the top semiconductor layer of the semiconductor on insulator substrate; providing a hard mask over the patterned material stack; blocking the hard mask and material stack in a first portion of the semiconductor structure; removing the hard mask and material stack in a second portion of the semiconductor structure while leaving a layer of the top semiconductor layer; depositing an oxide layer over the top semiconductor layer in the second portion of the semiconductor structure; depositing a hard mask over the oxide layer; patterning the hard masks in the first and second portions of the semiconductor structure to form a plurality of hard mask structures in the first and second portions of the semiconductor structure; forming a dummy gate over a central portion of each of said plurality of hard mask structures in the first and second portions of the semiconductor structure; forming a sacrificial material layer abutting the dummy gates in the first and second portions of the semiconductor structure; removing the dummy gates to form a trench in the sacrificial material layer of each of the first and second portions of the semiconductor structure to expose the central portion of each of said plurality of hard mask structures in the first and second portions of the semiconductor structure; etching a plurality of fins within the trench in the patterned material stack in the first portion of the semiconductor structure using the plurality of patterned hard masks in the first portion as an etch mask and etching a plurality of fins within the trench in the top semiconductor layer in the second portion of the semiconductor structure using the plurality of patterned hard masks in the second portion as an etch mask; removing the plurality of patterned hard masks in the first and second portions of the semiconductor structure; removing each layer of sacrificial material within the trench in the first portion of the semiconductor structure to form a plurality of vertically stacked and vertically spaced apart semiconductor nanowires within the trench in the first portion of the semiconductor structure; and filling the trenches in the first and second portions of the semiconductor structure with a gate region.