Patent ID: 8400847

Claim:
A semiconductor integrated circuit, comprising: a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a read operational mode and a write operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh mode; and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal, wherein the write-read clock control signal generating unit includes: a set-up unit that generates a command control signal activated in response to one of the read operational mode and the write operational mode; a latch unit that generates the read clock control signal and the write clock control signal in response to the command control signal; and a reset unit that resets the latch unit by supplying a reset signal activated in response to one of the idle mode and the refresh mode.