Patent ID: 7586188

Claim:
A chip package, comprising: a coreless package substrate, comprising: an interconnection structure, having a first inner circuit, a carrying surface and a corresponding contact surface, wherein the first inner circuit has a plurality of contact pads disposed on the contact surface; and a ceramic stiffener, disposed on the carrying surface and having a first opening, comprising: a plurality of ceramic dielectric layers; a plurality of conductive vias, wherein each conductive via passes through one of the ceramic dielectric layers; and a plurality of wiring layers, disposed alternately with the ceramic dielectric layers, wherein the wiring layers and the conductive vias together form the second inner circuit and two wiring layers are electrically connected to each other through at least one of the conductive vias; and a chip, disposed on the carrying surface and within the first opening and electrically connected to at least one of the contact pads, wherein the interconnection structure comprises: a plurality of dielectric layers; a plurality of conductive vias, wherein each conductive via passes through one of the dielectric layers; and a plurality of wiring layers, disposed alternately with the dielectric layers, wherein the wiring layers and the conductive vias together form the first inner circuit and two wiring layers are electrically connected to each other through at least one of the conductive vias.