Patent ID: 7023744

Claim:
A memory array comprising: a bitline; and a plurality of memory cells, each of the plurality of memory cells having: a configuration bit terminal; a pair of cross-coupled inverters having first and second bit nodes, wherein one of the first and second bit nodes is connected to the configuration bit terminal; an access transistor having a first current-carrying terminal connected to the bitline, a second current-carrying terminal connected to the first bit node, and an access-transistor control terminal; and a memory transistor having a first current-carrying terminal connected to one of the first and second bit nodes, a second current-carrying terminal connected to a power supply node, and a memory-transistor control terminal; wherein each of the plurality of memory cells further includes a programmable interconnection interposed between the first current-carrying terminal of the memory transistor and the first and second bit nodes; and wherein the programmable interconnection connects the first current-carrying terminal of the memory transistor to the first bit node when programmed in a first state, and connects the first current-carrying terminal of the memory transistor to the second bit node when programmed in a second state.