Patent ID: 7764759

Claim:
A clock and data recovery circuit coupled to an input data signal, comprising: a phase detector, comprising: a linear phase difference generator circuit having a first input coupled to the input data signal and a second input coupled to a recovered clock signal, the linear phase difference generator circuit having a first phase difference output and a second phase different output, the first phase difference output including a first analog signal that is proportional to the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal, the second phase difference output including a second analog signal that is proportional to the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal; and an analog sample and hold circuit coupled to the first and second phase difference outputs of the linear phase difference generator for sampling the analog voltage levels of the first and second phase difference outputs in response to a first transition of the input data signal and for holding the sampled analog voltage levels until a second transition of the input data signal, the sampled analog voltage levels respectively providing linear rising and falling information signals; an averaging circuit that sums the linear rising and falling information signals into a single linear information signal indicative of the relative phase differences between both the rising and falling edges of the input data signal and the recovered clock signal; a gain block that generates a non-linear control signal from the single linear information signal; and a voltage controlled oscillator coupled to the non-linear control signal for generating the recovered clock signal.