Patent ID: 6915394

Claim:
A microprocessor interface disposed between a main memory and a microprocessor, such interface comprising: a semiconductor integrated circuit having formed therein: (i) a data rebuffering section having a main memory bi-directional data port, a microprocessor bi-directional data port coupled to the microprocessor, and a plurality of additional bi-directional data ports, such data rebuffering section being adapted to selectively couple data from any one of the plurality of additional bi-directional data ports to the microprocessor bi-directional data port selectively in accordance with a control signal: and (ii) a main memory interface having a main memory interface bi-directional data port coupled to the main memory and an additional main memory interface bi-directional data port connected to the main memory bi-directional data port of the data rebuffering section, such main memory interface providing control signals to the main memory and for enabling data transfer between the main memory and the microprocessor through the data rebuffering section including a second integrated circuit adapted for controlling the first-mention integrated circuit, such second integrated circuit having thereon a controller adapted for coupling to the main memory interface, such controller being adapted to produce a main memory access control signal, and wherein: the main memory has a two portions of addressable locations, one portion being addressed by the main memory interface in response to a preselected range of memory location addresses provided by the microprocessor and the other portion being addressed by the main memory interface in response to the memory access control signal provided by the controller.