Patent ID: 8659345

Claim:
A switch level circuit with self-adapting dead time control capability comprising: a high-side control transistor ( 10 ) and a low-side synchronous rectifying transistor ( 11 ) having, a source end of the high-side control transistor ( 10 ) connected to an input voltage, and a source end of the low-side synchronous rectifying transistor ( 11 ) being grounded, a drain end of the high-side control transistor ( 10 ) connected to a drain end of the low-side synchronous rectifying transistor ( 11 ) to form a switching node (LX), and a gate end of the high-side control transistor ( 10 ) used as a controlled end of the high-side control transistor ( 10 ), configured for inputting a first external control signal (Pg), and a gate end of the low-side synchronous rectifying transistor ( 11 ) configured as a controlled end of the low-side synchronous rectifying transistor ( 11 ) to control ON/OFF of the high-side control transistor ( 10 ) and the low-side synchronous rectifying transistor ( 11 ), so as to produce a waveform with a controllable duty ratio at the switching node (LX), and produce an output voltage on a load ( 14 ) through an external filtering network ( 13 ); and a control module configured to regulate dead time between the high-side control transistor ( 10 ) and the low-side synchronous rectifying transistor ( 11 ), the control module comprising: a sampling circuit ( 16 ) configured to detect a current dead time by collecting a sampling voltage at the switching node (LX), a regulating circuit ( 17 ) configured to buffer and convert the sampling voltage collected by the sampling circuit ( 16 ), and a controlled delay unit ( 15 ) with an external control input end configured to delay a second external control signal (N g,p ) and takes the delayed second external control signal as a control signal (N g ) for the controlled end of the low-side synchronous rectifying transistor ( 11 ).