Patent ID: 7506015

Claim:
A circuit for generating a remainder from a division of a first polynomial by a second polynomial, comprising: a first sub-circuit adapted to generate a first partial remainder and having an input arranged to receive coefficients of the first polynomial excepting a surplus number of least significant coefficients, wherein the second polynomial has a variable width, the first partial remainder has a fixed width greater than or equal to the variable width, and the surplus number is given by a difference between the fixed width and the variable width; a first adder adapted to generate a sum of data at first and second inputs, the first input arranged to receive the surplus number of the least significant coefficients of the first polynomial, and the second input arranged to receive the surplus number of most significant coefficients of the first partial remainder; a second sub-circuit adapted to generate a second partial remainder from the sum received at an input; and a second adder adapted to generate the remainder from data at first and second inputs, the first input arranged to receive coefficients of the first partial remainder excepting the surplus number of the most significant coefficients, and the second input arranged to receive the second partial remainder.