Patent ID: 7316950

Claim:
A method of fabricating a CMOS device comprising the steps of: (a) forming a gate dielectric on a semiconductor substrate that can be sectioned into a p-well region for forming an NMOSFET and a n-well region for creating PMOSFET; (b) forming an aluminum nitride buffer layer material over the gate dielectric; (c) depositing a first metal on the buffer layer; (d) selectively etching the first metal with a first etchant so that the buffer layer is exposed on one of said p-well and n-well regions; (e) depositing a second metal on both the exposed buffer layer and the remaining first metal; (f) removing said first metal and said second metal and said buffer layer in selected areas so as to form a PMOSFET gate electrode and an NMOSFET gate electrode of said CMOS device; and (g) annealing remaining portions of said first metal and said second metal and said buffer layer to consume said portions of said buffer layer by reacting with said first metal and said second metal to form first and second conductive alloys with first and second work functions respectively.