Patent ID: 8421506

Claim:
An output buffer with process and temperature compensation comprising: an enable terminal means for sending an enable signal; a clock generator electrically connected to the enable terminal and applied to receive the enable signal to provide at least one clock signal; a PMOS threshold voltage detector, for detecting variance of threshold voltage of PMOS transistors, electrically connected to the clock generator and applied to receive the at least one clock signal to provide a first analog signal; an NMOS threshold voltage detector, for detecting variance of threshold voltage of NMOS transistors, electrically connected to the clock generator and applied to receive the at least one clock signal to provide a second analog signal; a first comparator electrically connected to the PMOS threshold voltage detector and applied to receive the first analog signal to provide a first trigger signal; a second comparator electrically connected to the NMOS threshold voltage detector and applied to receive the second analog signal to provide a second trigger signal; a first compensation code generator, for providing a first compensation code while receiving the clock signal and the first trigger signal, electrically connected to the first comparator and the clock generator; a second compensation code generator, for providing a second compensation signal while receiving the clock signal and the second trigger signal, electrically connected to the second comparator and the clock generator; and an output buffer stage, the output buffer stage has an output stage, the output buffer stage is applied to receive the first compensation code and the second compensation code to control a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal.