Patent ID: 7227764

Claim:
A voltage regulating device for a charge pump, the charge pump outputting an output voltage according to a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, the voltage regulating device comprising: a first inverter, for receiving the first clock signal and outputting a first inverse clock signal accordingly; a second inverter, for receiving the second clock signal and outputting a second inverse clock signal accordingly; a third inverter, for receiving the third clock signal and outputting a third inverse clock signal accordingly; a fourth inverter, for receiving the fourth clock signal and outputting a fourth inverse clock signal accordingly; a first voltage regulating capacitor, having one terminal coupled to the output voltage and the other terminal coupled to the first inverter; a second voltage regulating capacitor, having one terminal coupled to the output voltage and the other terminal coupled to the second inverter; a third voltage regulating capacitor, having one terminal coupled to the output voltage and the other terminal coupled to the third inverter; and a fourth voltage regulating capacitor, having one terminal coupled to the output voltage and the other terminal coupled to the fourth inverter; wherein each inverter comprises at least a PMOS transistor and a NMOS transistor, and the width of the PMOS transistor is different from the width of the NMOS transistor in each inverter; wherein the charge pump comprises a first NMOS transistor and a second NMOS transistor, the sources of the first NMOS transistor and the second NMOS transistor are for respectively outputting the output voltage, the gates of the first NMOS transistor and the second NMOS transistor are respectively coupled to the second clock signal and the fourth clock signal, the drains of the first NMOS transistor and the second NMOS transistor are respectively coupled to the first clock signal and the third clock signal, the width of the NMOS transistor is larger than the width of the PMOS transistor in the second inverter and the fourth inverter, and the width of the PMOS transistor is larger than the width of the NMOS transistor in the first inverter and the third inverter.