Patent ID: 7788613

Claim:
A method comprising: accessing by one or more computer systems: a description of a chip comprising a plurality of sequential elements and a clock mesh, the description identifying the sequential elements, indicating locations of the sequential elements on the chip, specifying interconnections among the sequential elements on the chip, and specifying a layout of the chip; information for modeling the sequential elements and interconnections; and a set of parameters of the clock mesh; using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh: determining by the one or more computer systems a plurality of original window locations covering the clock mesh, each original window location comprising one or more of the sequential elements on the chip; and for each original window location: expanding by the one or more computer systems the original window location in one or more directions to generate a larger window location; generating by the one or more computer systems a mesh simulation model comprising a detailed model and an approximate model, the detailed model detailing all components inside the larger window location and the approximate model approximating all components outside the larger window location; simulating by the one or more computer systems the mesh simulation model; and measuring by the one or more computer systems clock timing for the sequential elements in the original window location based on the simulation of the mesh simulation model; and collecting by the one or more computer systems timing information on all the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.