Patent ID: 6940765

Claim:
A repair apparatus in a semiconductor memory device including a main memory cell array with a plurality of main memory cells, a predecoder which performs a first decoding operation on an external address signal, and a decoder which performs a second decoding operation on the address signal undergoing the first decoding operation and selects and activates parts of the plurality of main memory cells, the repair apparatus comprising: a repair control circuit which programs one of an address signal for a first defective cell of the main memory cell array and an address signal for a second defective cell of the main memory cell array and outputs a control signal in response to the address signal undergoing the first decoding operation, the first defective cell being detected during a wafer-level test and the second defective cell being detected during a post package test; a redundancy memory cell array which includes a plurality of redundancy memory cells and is activated to repair one of the first and second defective cells; and a redundancy decoder which is enabled or disabled in response to the control signal and is enabled to activate parts of the redundancy memory cells, wherein the decoder is disabled in response to the control signal when the redundancy decoder is enabled.