Patent ID: 8468410

Claim:
An address generation apparatus for quadratic permutation polynomial (QPP) interleaver, comprising: L QPP units, represented as QPP unit 1 −QPP unit L, L≧2, said apparatus, according to a QPP function Π(i)=(f 1 i+f 2 i 2 )mod k, f 1 and f 2 being QPP coefficients, 0≦i≦k−1, k being information block length of an input sequence, receiving a plurality of configurable parameters and using said L QPP units to compute and output a plurality of interleaver addresses; wherein said Π(i) is an i th interleaver address generated by said apparatus, and each QPP unit j, 1≦j≦L, is a parallel computation unit and outputs in parallel a corresponding group of interleaver addresses.