Patent ID: 7646018

Claim:
A thin film transistor (TFT) array substrate, comprising: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer formed only at a predetermined location corresponding to the channel of the semiconductor layer; a gate pad extending from the gate line a data pad connected to the data line, where a transparent conductive pattern is formed; a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad, and a transparent conductive pattern formed on the drain electrode, wherein the transparent conductive pattern is formed of the same material as the pixel electrode, wherein the gate pad includes, a gate pad lower electrode connected to the gate line; a contact hole penetrating the gate insulating layer and the semiconductor pattern to expose the gate pad lower electrode; and a gate pad upper electrode connected to the gate pad lower electrode, the semiconductor layer and a data metal pattern through the contact hole, wherein the gate pad upper electrode is formed on the data metal pattern, wherein the gate pad upper electrode is formed of the same material as the transparent conductive pattern.