Patent ID: 8037358

Claim:
A semiconductor device for providing an access control for a memory that includes a plurality of storage regions storing the same boot programs comprised of a set of program data, comprising: a memory controller for reading out said program data from said storage regions; and an error detection circuit performing error detection on said read program data, wherein said memory controller is configured to, when said error detection circuit detects an error in one of said read program data read out from one of said storage regions, read out said program data from different one of said storage regions for a current read out and each subsequent read out and read out said one of said read program data as specified by a CPU, said memory controller reads out said one of said read program data from said different one of said storage regions in response to said error being found in said one of said read program data by said error detection circuit, further comprising a readdressing circuit, wherein said one of said read program data is specified with an address by said CPU; said readdressing circuit specifies said address specified by said CPU as a destination address, and indicates one of said storage regions as a destination storage region; said memory controller is configured to read out one of said read program data specified by said destination address; and said readdressing circuit is configured to contain said address specified by said CPU, and to, when an error is found in said one of said read program data by said error detection circuit, specify different one of said storage regions as said destination storage region for the current read out and each subsequent read out, and to specify said address contained therein as said destination address, said readdressing circuit is configured to contain a region number corresponding to said destination storage region, and is responsive to another address being newly specified by said CPU for specifying another one of said storage regions associated with said region number as a next destination storage region, and for specifying said newly specified address as a next destination address, said plurality of storage regions include a first storage region, said readdressing circuit contains a region number corresponding to said first storage region as a main storage region number, and is responsive to said other address being newly specified by said CPU for specifying said first storage region corresponding to said main storage region number as said next destination storage region, and for specifying said newly specified address as said next destination address, said plurality of storage regions include a second storage region, and said readdressing circuit specifies a region number corresponding to said second storage region as a newly-specified main storage region number, when a number of said read program data read out from said first storage region which are determined as including an error is increased up to a threshold.