Patent ID: 7864494

Claim:
An integrated circuit comprising: an input/output (I/O) pad; a power supply (VDD) pad; a diode between the I/O pad and VDD line so that the diode cathode is connected to VDD and the diode anode is connected to the I/O pad; a first precharge elimination circuit between the I/O pad and ground potential, the precharge elimination circuit powered by the same VDD; a second precharge elimination circuit between the VDD pad and ground potential; and an ESD protection circuit between VDD and ground potential, the ESD protection circuit in parallel with the first and the second precharge elimination circuit and powered by the same VDD; wherein the first precharge elimination circuit includes: a first resistor connected to the I/O pad, the first resistor operable as discharge resistor; a first nMOS transistor in series with the first resistor, the first transistor drain connected to the first resistor, and the first transistor source and body connected to ground; and a first RC timer connected to the first nMOS transistor gate, the first RC timer including a second resistor connected to ground and a first capacitor connected to VDD.