Patent ID: 8812774

Claim:
A memory system comprising: a plurality of semiconductor memories each having a plurality of blocks; a first table in which a plurality of memory areas that is associated one-to-one with the blocks in the semiconductor memories is arranged in a matrix, the memory areas associated with the respective blocks in any one of the semiconductor memories are arranged in each column, and defect information indicating presence or absence of a defect in a block associated with each memory area is stored in the memory area; a receiving unit configured to receive a write command requesting writing of data to a semiconductor memory; a generating unit configured to select one of a plurality of index numbers associated one-to-one with a plurality of rows in the first table, and select one block to which data are to be written in each of the semiconductor memories based on the selected index number and the first table to generate a set of the blocks; a second table in which the index number and one of a plurality of channel numbers associated one-to-one with the semiconductor memories are stored in association with each of logical block addresses individually given to a plurality of pieces of the data; and a writing unit configured, when the write command is received by the receiving unit, to select one of the channel numbers, write the data requested to be written to a block associated with the selected channel number among the blocks constituting the set, and write the logical block address given to the data, the index number associated with the set and the selected channel number in association with one another into the second table, wherein when the blocks in each of the semiconductor memories have no defect, the generating unit selects one block associated with the memory area belonging to a row indicated by the index number from each of the semiconductor memories.