Patent ID: 7961503

Claim:
A memory device comprising: a substrate having a source region, a drain region and a channel region, the channel region separates the source region and the drain region, electrons flow through the channel region between the source region and the drain region in a horizontal direction; an electrically insulating layer adjacent to the source region, drain region and channel region; a floating gate element adjacent to the electrically insulating layer, the electrically insulating layer separates the floating gate element from the channel region, the floating gate element is magnetic and comprises a ferromagnetic pinned layer and an anti-ferromagnetic pinning layer, the floating gate element generates the magnetic field and the control gate electrode is non-magnetic; a control gate electrode adjacent to the floating gate element, the floating gate element separates the control gate electrode from the electrically insulating layer, the channel region, electrically insulating layer, floating gate element and control gate electrode being stacked in a vertical direction, the vertical direction being perpendicular to the horizontal direction; and a magnetic field directed through the channel region and perpendicular to the vertical direction and the horizontal direction.