Patent ID: 7496491

Claim:
A delay calculation method for calculating a delay in a logic circuit including at least a MOS transistor, the delay calculation method comprising the steps of: modeling the transistor using: a resistance element whose resistance value is fixed, and a power supply whose voltage varies with time; determining a shape of a voltage waveform of said power supply based on input waveform information associated with a shape of an input waveform of said logic circuit; calculating, by using a machine, a delay in the logic circuit; and displaying or storing or outputting the calculated delay, wherein E(t) represents voltage waveform of said power supply, and wherein determining E(t) includes the steps of: (a) determining whether E(Tslew) is greater than or equal to E, wherein Tslew represents the time when the input waveform has finished its transition to 0 or Vdd and E represents a first constant voltage, (b) upon a determination that E(Tslew) is not greater than or equal to E, calculating a mean gate voltage, (c) using the mean gate voltage to calculate V 1 , wherein V 1 represents a second constant voltage, (d) determining whether E(t 0 +Δt 1 +Δt 2 ) is equal to E, wherein t 0 defines a fixed delay time required for the input waveform to exceed a threshold voltage of the transistor, Δt 1 defines the time required for E(t) to increase from 0 to V 1 , and Δt 2 defines the time required for E(t) to increase from V 1 to E, and (e) upon a determination that E(t 0 +Δt 1 +Δt 2 ) is equal to E, determining the waveform shape of E(t).