Patent ID: 7466724

Claim:
Apparatus for processing packetized data spanning multiple clock cycles, comprising: a counter for counting cycles of a clock signal, said counter being responsive to said clock signal, to a Data Valid signal indicative of the presence of valid data, and to an SOP signal indicative of a start of a packet, said counter incrementing its clock cycle count in response to each of said clock cycles when said Data Valid signal is present, said counter having a range of counts at least equal to a length of said packet; a first comparator, for comparing a present clock cycle count to one of a plurality of reference clock cycle count values and producing a first enable signal in response to a favorable determination, said favorable determination being a determination that said present clock cycle count is equal to said reference clock cycle count value of said first comparator, and wherein each of said reference clock cycle count values can be equal to any count value within said range of counts of said counter; a second comparator, for comparing said clock cycle count to one of a plurality of reference clock cycle count values and producing a second enable signal in response to a favorable determination, said favorable determination being a determination that said present clock cycle count is equal to said reference clock cycle count value of said second comparator, and wherein each of said reference clock cycle count values can be equal to any count value within said range of counts of said counter; a first word recognizer, for comparing a presently received digital word to a reference digital word and producing a determination of equality or non-equality in response to said first enable signal; a second word recognizer, for comparing a presently received digital word to a reference digital word and producing a determination of equality or non-equality in response to said second enable signal; and an output circuit for providing an indication of whether said digital word comparisons produced a determination of equality at each clock cycle corresponding to a reference clock cycle count value.