Patent ID: 7459961

Claim:
A voltage-insensitive bias circuit, comprising: a first resistor connected between a power voltage node and a voltage divider node; a second resistor connected between a ground node and the voltage divider node; a first bipolar transistor having a first base, a first collector and a first emitter; a fourth resistor connected between the first base and the voltage divider node; a fifth resistor connected between the first collector and the power voltage node; a sixth resistor connected between the first emitter and the ground node; a second bipolar transistor having a second base, a second collector and a second emitter, wherein the second collector is connected to the power voltage node; a seventh resistor connected between the first collector and the second base; and a second diode having a second anode and a second cathode, and a third diode having a third anode and a third cathode, wherein the second anode is connected to the second base, the second cathode is connected to the third anode, and the third cathode is connected to the ground node; wherein the second emitter provides a first bias output to a second circuit, the first bias output being appreciably insensitive to voltage fluctuations of the voltage power node.