Patent ID: 8082532

Claim:
A computer-implemented method of implementing a circuit design within an integrated circuit, the method comprising: within an undirected graph representing the circuit design comprising nodes and edges, wherein each node represents a complex function block or a pre-placed component of the circuit design and each edge represents at least one connection linking a pair of complex function blocks of the circuit design forming a complex function block connection, determining an edge weight for each edge; initially placing the complex function blocks on the integrated circuit; calculating a distance between each pair of complex function blocks joined by an edge of the undirected graph; annealing, using a processor, the complex function block placement by minimizing a cost function that calculates, for each edge, a product of the edge weight and the distance between the pair of complex function blocks joined by the edge, and sums the products for each edge, wherein the product for each edge is selectively adjusted according to an over budget term; wherein the over budget term is calculated using delay or length according to whether the complex function block connection consists of a single connection or comprises a plurality of connections; and storing the complex function block placement.