Patent ID: 8304348

Claim:
A semiconductor device manufacturing method comprising: stacking a plurality of electrode layers containing a semiconductor alternately with insulating layers; processing part of a multilayer body of the electrode layers and the insulating layers into a staircase shape and exposing a surface of the staircase-shaped electrode layers; forming a metal film in contact with the exposed electrode layers; reacting the semiconductor of the electrode layers with the metal film to form a metal compound in at least a portion of the electrode layers in contact with the metal film; removing an unreacted portion of the metal film; forming an interlayer insulating layer covering the staircase-shaped electrode layers after removing the unreacted portion of the metal film; forming a plurality of contact holes piercing the interlayer insulating layer, each of the contact holes reaching the metal compound of the electrode layer at a corresponding stage; and providing a plurality of contact electrodes inside the contact holes, wherein the processing part of the multilayer body into the staircase shape is performed by repetition of reducing planar size of a resist film formed above the multilayer body, and etching one of the insulating layers and one of the electrode layers in a portion not covered with the resist film and exposed from the resist film.