Patent ID: 7949820

Claim:
In a system for reading and writing data, including a controller, multiple microprocessor units internally bused to the controller, and multiple memory device configurations, each configuration having a dedicated bus connection to multiples of the microprocessor units, a method for managing access to one or more of the memory device configurations, comprising the steps: (a) receiving a read and write request and data management tasks at the controller requiring access to the memory device configurations; (b) determining at the controller, a microprocessor unit or units to handle the request for read and write and selecting a separate microprocessor unit or units to handle the data management tasks; (c) handing the request for read and write and the data management tasks to the microprocessor unit or units determined at step (b); (d) determining at the microprocessor unit or units, the tasks specified in the request for that microprocessor unit or units; (e) determining a memory address or addresses in one or more of the memory device configurations and accessing the memory device configuration or configurations to satisfy the request.