Patent ID: 7778076

Claim:
A memory unit, comprising: a first metal oxide semiconductor (MOS) transistor, having a first end coupled to a first contact which is coupled to a first voltage, a second end coupled to a second voltage, and a gate coupled to a second contact which is coupled to the first voltage; a second MOS transistor, having a first end coupled to the second contact, a second end coupled to a third voltage, and a gate coupled to the first contact; a first non-volatile device, having a control gate coupled to a first control bias, a first end of the first non-volatile device is coupled to the first contact, and a second end of the first non-volatile device is coupled to a first bit line; and a second non-volatile device, having a control gate coupled to a second control bias, a first end of the second non-volatile device is coupled to the second contact, and a second end of the second non-volatile device is coupled to a second bit line, wherein the first non-volatile device and the second non-volatile device respectively comprise: a substrate, having a source region and a drain region; a charge storage layer, disposed on the substrate, wherein a plurality of assist charges are fixed at only one non-data side of the charge storage layer to accelerate a speed for programming another side of the charge storage layer; and a control gate, disposed on the charge storage layer.