Patent ID: 7403410

Claim:
A device comprising: a bit cell comprising a first storage node; a write line; a first bit line; a first Field Effect Transistor (FET) comprising at least one gate coupled to the memory write line, a first source/drain coupled to the first bit line, and a second source/drain coupled to the first storage node to write a logic state at the first storage node; and a second FET comprising a first gate, a second gate coupled to receive a first control signal from the bit cell, a first channel region substantially controlled by the first gate, a second channel region substantially controlled by the second gate, a first source/drain coupled to the first bit line, and a second source/drain coupled to the second source/drain of the first FET, first FET and the second FET operable to communicate logic state information at the first bit line to the first storage node to write the logic state at bit cell.