Patent ID: 7202500

Claim:
A thin film transistor array substrate, comprising: a gate pattern on a substrate, the gate pattern including a gate electrode of a thin film transistor, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line; a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, and a lower data pad electrode connected to the data line; a semiconductor pattern formed beneath the source/drain pattern; a transparent electrode pattern including a pixel electrode connected to the drain electrode, an upper gate pad electrode connected to the lower gate pad electrode, and an upper data pad electrode connected to the lower data pad electrode; and a gate insulating pattern and a passivation film pattern stacked at remaining areas excluding areas within which the transparent electrode pattern is formed, wherein one end of the drain electrode has a flat surface and an inclined slope surface, an entire surface of the flat surface is covered with the passivation film pattern, and an entire surface of the inclined slope surface is covered with the pixel electrode.