Patent ID: 8473879

Claim:
A method for determining leakage current in a digital circuit integrated on a die, the method comprising: first providing, on the die and separate from the digital circuit, a first leakage monitor comprising at least one N-type transistor connected to a first branch of a first current mirror, the at least one N-type transistor corresponding to an off state for a first plurality of N-type transistors in the digital circuit, wherein the first leakage monitor further comprises a first differential amplifier connected to a second branch of the first current mirror such that current through the second branch of the first current mirror mirrors current through the at least one N-type transistor, the first differential amplifier generates a first leakage current value; second providing, on the die and separate from the digital circuit, a second leakage monitor comprising at least one P-type transistor connected to a first branch of a second current mirror, the at least one P-type transistor corresponding to an off state for a second plurality of P-type transistors in the digital circuit, wherein the second leakage monitor further comprises a second differential amplifier connected to a second branch of the second current mirror such that current through the second branch of the second current mirror mirrors current through the at least one P-type transistor, wherein the second differential amplifier generates a second leakage current value; and measuring the first leakage current value and the second leakage current value to determine a leakage current result based on the first leakage value and the second leakage current value.