Patent ID: 8716081

Claim:
A method of fabrication of a memory device comprising: providing an active region in a substrate; and forming a one transistor random access memory (RAM) for storing digital data in the active region comprising forming a gate structure in the active region, wherein the gate structure is coupled to a word line, forming a source region and an extended drain region adjacent to the gate structure in said substrate, wherein the source region is coupled to a bit line, the extended drain region includes a drain region and a bottom plate of a capacitor, the drain region is adjacent to the gate structure and the bottom plate extends from the drain region to an isolation region, the drain region and the entire bottom plate of the extended drain region are formed simultaneously, wherein the drain region and bottom plate of the extended drain region have about the same dopant concentration, and forming a capacitor dielectric layer and a top plate of the capacitor on the bottom plate, wherein the top plate is on the capacitor dielectric layer, and wherein the top plate is coupled to ground and completely covers the bottom plate, the capacitor dielectric layer is directly on the bottom plate and partially on the isolation region.