Patent ID: 8120400

Claim:
A Phase Locked Loop circuit, comprising: a main path through which an input signal is propagated, and an actual signal is output; a main feedback path through which the actual signal is fed back to an input stage of said main path; and a local feedback path through which feedback is carried out from a path middle of said main path to a path middle of an input stage side; said main path including a phase detector disposed in the input stage configured to detect phases of the input signal and the actual signal, a loop filter disposed on an output side of said phase detector, and a controlled oscillator configured to oscillate at a frequency corresponding to an output signal from said loop filter to generate an oscillation signal, thereby outputting the oscillation signal as the actual signal to said main feedback path, and said local feedback path including a replica portion to which the output signal from said loop filter is input, and which functions as a replica of said controlled oscillator, a delay portion configured to delay an output signal from said replica portion by circuit dead time, a first subtracter configured to obtain a difference between an input signal to the delay portion, and an output signal from said delay portion, and a second subtracter configured to subtract a signal obtained by multiplying an internal signal within said loop filter by a constant value from an output signal from said first subtracter thereby outputting a resulting signal to an input side of said loop filter.