Patent ID: 8089575

Claim:
A display device being configured such that a gate signal line, an insulation film, a semiconductor layer and a conductor layer are sequentially stacked on a substrate, the conductor layer forms at least a drain electrode and a source electrode of a thin film transistor and a drain signal line which are arranged with a channel region of the semiconductor layer sandwiched therebetween, the channel region overlaps the gate signal line, the drain electrode and the source electrode are formed in a pattern in which the drain electrode is formed in an approximately U shape having an open-ended one end side of the U shape and a connecting portion on another end side of the U shape such that the drain electrode surrounds a distal end portion of the source electrode as viewed in plan view and a projecting portion is formed on a side of the connecting portion opposite to the source electrode, and the semiconductor layer and the conductor layer overlap, and the semiconductor layer forms a protruding portion which extends outwardly beyond the conductor layer including at the projecting portion as viewed in plan view.