Patent ID: 8196545

Claim:
A semiconductor wafer manufacturing device, comprising: a storage means which stores a plurality of sets of processing amount data which specify respective processing amounts over substantially the entire area of a wafer under a plurality of sets of processing conditions; a substrate wafer measurement means which obtains substrate wafer flatness profile data by measuring the flatness of a substrate wafer over substantially its entire area; a manufactured wafer prediction means which, by applying each of said plurality of sets of processing amount data to said substrate wafer flatness profile data, calculates a plurality of sets of manufactured wafer flatness profile data, each of which specifies predicted values for flatness profile of a manufactured wafer over substantially its entire area, which would be obtained if said substrate wafer were to be processed under said plurality of sets of processing conditions; a processing conditions selection means which evaluates said plurality of sets of processing conditions on the basis of said plurality of sets of manufactured wafer flatness profile data, and selects one set of processing conditions according to the result of said evaluation; a wafer processing means which manufactures a manufactured wafer by processing said substrate wafer under said selected one set of processing conditions; a flatness measurement device which can measure wafer flatness; an epitaxial layer growth reactor which operates under set processing conditions; and a control device for inputting output data from said flatness measurement device, and controlling said epitaxial layer growth reactor; wherein: said flatness measurement device functions as said substrate wafer measurement means; said epitaxial layer growth reactor functions as said wafer processing means; and said control device functions as said storage means, said manufactured wafer prediction means, and said processing conditions selection means.