Patent ID: 7917701

Claim:
Cache circuitry for use in a data processing apparatus, the cache circuitry comprising: a cache storage comprising a plurality of cache lines for storing data values; control circuitry, responsive to an access request issued by a device of the data processing apparatus identifying a memory address of a data value to be accessed, configured to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage, and if not to initiate a linefill operation to retrieve the data value from memory; and prefetch circuitry configured to determine that the memory address specified by a current access request is the same as a predicted memory address, and, upon said determination, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from said memory at least one further data value in anticipation of that at least one further data value being the subject of a subsequent access request; the first prefetch linefill operation comprising issuing a sequence of selected memory addresses to said memory, and allocating into a corresponding sequence of cache lines of the cache storage the further data values returned from said memory in response to the sequence of selected memory addresses; the second prefetch linefill operation comprising issuing a selected memory address to said memory, and storing in a linefill buffer the at least one further data value returned from said memory in response to that selected memory address, the at least one further data value only being allocated into a cache line of the cache storage when the subsequent access request specifies said selected memory address; and the prefetch circuitry, responsive to an attribute of said current access request, configured to select either said first prefetch linefill operation or said second prefetch linefill operation, wherein the attribute of said current access request comprises an indication as to whether that current access request is being issued by said device to perform a preload operation, if the current access request is being issued to perform said preload operation the prefetch circuitry performs said first prefetch linefill operation, whereas otherwise the prefetch circuitry performs said second prefetch linefill operation.