Patent ID: 7724864

Claim:
A shift register including a plurality of stages to output a plurality of output signals, in sequence, each of the plurality of stages comprising: a driving part outputting an output signal of a selected stage based on one of a start signal and an output signal of a previous stage, and a clock signal, the driving part including; a first transistor connected to a first input terminal that receives one of the output signals of the previous stage and the start signal; a second transistor connected to a clock signal line and an output terminal that outputs the output signal of the selected stage; and a third transistor connected to the output terminal, an off-voltage terminal and a second input terminal that receives an output signal of a next stage to the selected stage; and a discharging part that discharges the output signal of the selected stage, the discharging part including: a discharge transistor having a gate electrode that receives an output signal of a next stage to the selected stage; and an auxiliary transistor having a gate electrode that receives the output signal of the next stage, the auxiliary transistor being electrically connected in series to the discharge transistor, wherein the third transistor receives the output signal of the next stage simultaneously with a receipt of the output signal of the next stage by the discharge transistor.