Patent ID: 7072922

Claim:
Apparatus for identifying a maximum or minimum value among a plurality of values represented by respective a-bit binary signals on a plurality of a-bit wide wires in an integrated circuit module, the apparatus comprising: first means responsive to the a-bit binary signal on each of the plurality of wires to calculate an N-bit vector K based on n most significant bits of all a-bit binary signals and to calculate M N-bit vectors K_ 0 , . . . ,K_(M−1) based on the n most significant bits and m least significant bits of all a-bit binary signals, where n=a−m, N=2 n , M is at least 2 m −1 and m is either a/2 or (a−1)/2; second means responsive to vectors K_ 0 , . . . ,K(M−1) for calculating N table vectors; third means responsive to vector K for selecting one of the table vectors to derive a vector P; fourth means responsive to vector P for selecting a table vector; and an output for calculating the minimum or maximum binary value from the vectors selected by the third and fourth means.