Patent ID: 8076734

Claim:
A semiconductor structure comprising: a semiconductor substrate including an isolation region that surrounds an active region; a gate dielectric comprising other than a thermal processing product of the semiconductor substrate located on a surface of the active region of the semiconductor substrate; a gate electrode located on a surface of said gate dielectric; and a pair of source and drain regions located within the active region and separated by a channel region located beneath the gate electrode, wherein said gate dielectric has a first set of edges in a first direction and a second set of edges in a second direction that intersects said first direction, wherein said first set of edges in said first direction is aligned to, and does not extend beyond, outer edges of said gate electrode, and said second set of edges in said second direction has a first edge that coincides with, and is aligned to, and does not extend beyond, a first edge of said isolation region in a view in a direction perpendicular to said surface of said active region and a second edge that extends beyond a second edge of said isolation region.