Patent ID: 7714353

Claim:
An insulated gate semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on a first major surface of the first semiconductor layer; trenches in a surface portion of the second semiconductor layer, the trenches extending in parallel to each other and forming a planar stripe pattern; third semiconductor regions of the first conductivity type in the surface of the second semiconductor layer arranged between every other of the trenches along a direction perpendicular to a longitudinal direction of the trenches so that the third semiconductor regions are alternately arranged with surface regions of the second semiconductor layer existing between the trenches along the surface of the second semiconductor layer; a fourth semiconductor region of the second conductivity type arranged selectively in a surface portion of the third semiconductor region; a gate electrode in each trench with a gate insulator film interposed between the gate electrode and a wall of the trench; an emitter electrode in electrical contact commonly with the third semiconductor region and the fourth semiconductor region; and a collector electrode in contact with a second major surface of the first semiconductor layer; wherein, in a portion of the third semiconductor region in contact with the gate electrode via the gate insulator film, an impurity concentration in a portion of the third semiconductor region sandwiched between a bottom plane of the fourth semiconductor region and a bottom plane of the third semiconductor region and parallel to the first major surface of the first semiconductor layer is the lowest.