Patent ID: 7885102

Claim:
A semiconductor device comprising: a plurality of word lines; a first bit line intersecting with the word lines; a second bit line intersecting with the word lines; a plurality of memory cells disposed at intersecting points of the word lines and the first and second bit lines; a plurality of pairs of input/output buses including a first common data line and a second common data line; a first data holding circuit and a first programming circuit provided corresponding to the first common data line and the first bit line; a second data holding circuit and a second programming circuit provided corresponding to the second common data line and the second bit line; and a programming controller operable to control the first and the second programming circuit, wherein the first and second data holding circuits fetch in and hold data transferred in parallel along the first and second common data lines, wherein the first and the second programming circuit supply the first and second bit lines with a programming voltage, according to the data held in the first and the second data holding circuit, and wherein the programming controller generates a plurality of control signals corresponding to each of the first programming circuit and the second programming circuit.