Patent ID: 7135999

Claim:
A circuit arrangement for compensating for nonlinearities from analog/digital converters operating with different timing, comprising: at least two analog/digital converters which are each clocked with different timing, each of the at least two analog/digital converters having a predetermined nonlinear converter characteristic with integral nonlinearities, each of the at least two analog/digital converters configured to receive an analog input signal and convert the analog input signal into a digital intermediate signal; and a circuit unit operably coupled to receive the digital intermediate signals from the at least two analog/digital converters, the circuit unit configured to successively provide the digital intermediate signals in order to produce a digital output signal; wherein a first nonlinear converter characteristic of a first analog/digital converter has a predetermined relationship with a first nonlinear converter characteristic of a second analog/digital converter such that after the digital intermediate signals have been successively provided by the circuit unit, at least some integral nonlinearities in the at least two analog/digital converters at least partially compensate for one another.