Patent ID: 7132718

Claim:
A non-volatile semiconductor memory device, comprising: a semiconductor substrate; first and second semiconductor regions of a first conductivity type formed in said semiconductor substrate; a first channel region and a second channel region between said first semiconductor region and said second semiconductor region in said semiconductor substrate, said first channel region being located on the side close to said first semiconductor region and said second channel region being located on the side close to said second semiconductor region; a first gate formed above said first channel region via a first insulator; and a second gate formed above said second channel region via a second insulator, wherein said non-volatile memory is enabled to perform at least a writing operation, an erasing operation and a charge holding operation, and such that in the writing operation electrons are injected into said second insulator, in the erasing operation holes are injected into said second insulator and in the holding operation charges are held in said second insulator, and wherein the charge density of an impurity in said first channel region is different from the charge density of an impurity in said second channel region.