Patent ID: 8878582

Claim:
An apparatus for duty cycle calibration, comprising: an input calibration circuit, calibrating an input clock signal by applying logic operations and delay on the input clock signal so as to generate an input calibration clock signal; a delay chain, comprising a plurality of delay units coupled in series, and delaying the input calibration clock signal so as to generate a first delay clock signal at a first node of the delay chain and generate a second delay clock signal at a second node of the delay chain, wherein at least two of the plurality of delay units each have an adjustable delay time; a first comparator, comparing the input calibration clock signal with the first delay clock signal so as to generate a first control signal; a second comparator, comparing the input calibration clock signal with the second delay clock signal so as to generate a second control signal; and a controller, arranged to control the delay according to the first control signal and to control the adjustable delay time according to the second control signal.