Patent ID: 7127589

Claim:
A data processor for multiprocessing a data-driven program and a control-driven program in the same pipeline, on an instruction-by-instruction basis, wherein a processing element for performing pipeline processing comprises: an instruction fetch unit which fetches a data-driven instruction or a control-driven instruction from an instruction memory based on an input packet or a program counter, and issues the instruction in the form of a packet; an instruction decode unit which decodes the instruction issued from the instruction fetch unit, and outputs the decoded instruction in the form of a packet wherein, in the case of the control-driven instruction, an access is made to a register and, if a data hazard is detected, register renaming is performed, before outputting the decoded instruction; a firing control unit which stores the instruction decoded by the instruction decode unit in a matching memory for waiting therein, and which selects one of ready-to-fire instructions and outputs the selected instruction in the form of a packet, thereby performing control to fire the instruction; an execution unit which performs an operation specified by the instruction fired by the firing control unit and, in the case of the data-driven instruction, transfers an operation result in the form of a packet to the instruction fetch unit, but in the case of the control-driven instruction, forwards the operation result in the form of a packet to the firing control unit; and a write back unit which writes the operation result of the control-driven instruction executed by the execution unit into a register associated therewith.