Patent ID: 7773425

Claim:
An electrically erasable programmable virtual ground nonvolatile semiconductor memory comprising: a memory cell array comprising nonvolatile memory cells respectively connected to row lines and column lines, each nonvolatile memory cell including two storage areas, wherein each single data bit of the memory is stored as a pair of complementary threshold states being set to outer storage areas of two nonvolatile memory cells at symmetrical locations with respect to a first pair of column lines adjacent to each other; a row selection circuit for applying a predetermined read voltage to a row line to which the two nonvolatile memory cells are connected; a column selection circuit for applying a ground voltage to a second pair of column lines just outside the two nonvolatile memory cells to be read simultaneously and applying another predetermined read voltage to the first pair of column lines running in a region between the two nonvolatile memory cells to be read simultaneously; and a read conversion circuit for comparing currents which run through the two nonvolatile memory cells and for converting the currents into data on the basis that the outer storage areas of the two nonvolatile memory cells have complementary threshold states.