Patent ID: 8854055

Claim:
A differential capacitive transducer system for sensing a physical quantity, the differential capacitive transducer system comprising: a first capacitive core including a first variable capacitor and a second variable capacitor, the first variable capacitor extending from a first core input to a first common node, the second variable capacitor extending from a second core input to the first common node; a second capacitive core including a third variable capacitor and a fourth variable capacitor, the third variable capacitor extending from a third core input to a second common node, the fourth variable capacitor extending from a fourth core input to the second common node; an integrator circuit including a first integrator input, a second integrator input and an integrator output; a chopping system for switchably coupling first and second positive signals and first and second negative signals to the first, second, third and fourth core inputs and for switchably coupling the first and second common nodes to the first and second integrator inputs, the chopping system switching back and forth between a high state and a low state; wherein when the chopping system is in the high state, the chopping system couples the first positive signal to the first core input, the first negative signal to the second core input, the second negative signal to the third core input, the second positive signal to the fourth core input, the first common node to the first integrator input and the second common node to the second integrator input; a first differential summing circuit summing the integrator output with a reference voltage and generating the first positive signal and the second positive signal, a first feedback path feeding back the integrator output to the first differential summing circuit; a second differential summing circuit summing the integrator output with an inverted reference voltage and generating the first negative signal and the second negative signal, the reference voltage and the inverted reference voltage having substantially the same magnitude and opposite polarity; and a second feedback path feeding back the integrator output to the second differential summing circuit; and wherein when the chopping system is in the low state, the chopping system couples the second negative signal to the first core input, the second positive signal to the second core input, the first positive signal to the third core input, the first negative signal to the fourth core input, the second common node to the first integrator input and the first common node to the second integrator input.