Patent ID: 8294505

Claim:
A programmable passive device, comprising: a common node; at least two further nodes; a first bank of passive device elements electrically coupled to the common node; a second bank of passive device elements electrically coupled to the common node, wherein the first bank of passive device elements and the second bank of passive device elements comprise on-chip complimentary metal oxide semiconductor (CMOS) device elements; and a plurality of switches associated with each of the passive device elements of the first bank and the second bank, the plurality of switches selectively coupling at least one of the passive device elements of at least one of the first bank to a first one of the at least two further nodes and selectively coupling at least one of the passive device elements of the second bank to a second one of the at least two further nodes, wherein the first one of the at least two further nodes is directly connected to a first pad, the second one of the at least two further nodes is directly connected to a second pad, and the common node is electrically connected to a third pad; the first pad is configured to be grounded while the second pad is biased to create a capacitance configuration of a serial connection; the third pad is configured to be grounded while the first pad and the second pad are biased in order to create the capacitance configuration of a parallel connection; a capacitance value of the device is programmable by biasing and grounding respective ones of the first pad, the second pad and the third pad in order to achieve the capacitance configuration of the serial connection or the parallel connection between the first bank and the second bank of the passive device elements and the plurality of switches include an e-fuse or an anti-fuse, wherein the e-fuse is programmed to open at a first bias and the anti-fuse is programmed to close at a second bias higher than the first bias such that the plurality of switches offers a second time programmability.