Patent ID: 8119481

Claim:
A method for manufacturing a charge trapping memory comprising: defining a semiconductor body including a channel region on a semiconductor body, the channel region having a channel surface, and source and drain terminals adjacent the channel; defining a gate; forming a dielectric stack between the channel surface and the gate, including forming a tunneling dielectric layer on one of the channel surface and the gate; forming a charge trapping dielectric layer on the tunneling dielectric layer; and forming a blocking dielectric layer on the charge trapping dielectric layer, wherein forming the blocking dielectric layer includes forming a first layer of material having a dielectric constant κ 1 in contact with the charge trapping dielectric layer and forming a second layer of material having a dielectric constant κ 2 in contact with the other of the channel surface and the gate, where κ 2 is greater than κ 1 , and the second layer has thickness less than κ 2 /κ 1 times that of the first layer.