Patent ID: 6960500

Claim:
A method of forming a cell area of a flash memory device comprising: forming an active region having a plurality of line shaped sub-regions on a semiconductor substrate, each being defined parallel to each other by an isolation layer; forming a gate insulating layer and a silicon floating gate layer in said active region; forming a floating gate intermediate pattern by patterning said floating gate layer; forming a dielectric layer over said floating gate intermediate pattern; forming a silicon control gate layer over said dielectric layer forming a plurality of gate lines by partially etching said silicon control gate layer, said dielectric layer, and said floating gate intermediate pattern; doping said active region between said gate lines by using a dose of impurity below 1.0×10 15 ions/cm 2 ; forming a lower interlayer insulating layer over the whole surface of said substrate over which said doping is carried out; forming a groove exposing a common source region in said active region by partially etching said lower interlayer insulating layer; depositing a silicon layer to fill said groove; forming a wall shaped silicon common source line and exposing upper portions of said gate lines by planarizing said silicon layer and said lower interlayer insulating layer; and forming a metal silicide layer on exposed upper surfaces of said gate lines and on said silicon common source line.