Patent ID: 8543870

Claim:
A circuit for detecting and recording chip fails, comprising: a common error bus, wherein the common error bus comprises: a bus status line, carrying a bus state signal indicating either an idle state or a busy state of the common error bus; a bus clock line, carrying a bus clock signal; and a bus data line, carrying a fail code from one of the plurality of fail detector modules to the control center; a plurality of fail detector modules, each of which is configured to receive at least a data signal to determine an occurrence of a chip fail and to correspondingly broadcast a fail code on the common error bus when the common error bus is not busy, wherein each of the plurality of fail detector modules comprises: a combinational logic, including a plurality of input ports to receive the at least a data signal, the bus state signal, the bus clock signal and a reset signal and a plurality of output ports to provide a local busy signal and the bus state signal; and a data transmission block, including a plurality of input ports to receive the bus clock signal, the reset signal and the local busy signal and an output port to broadcast a fail code on the bus data line of the common error bus; wherein the combinational logic is configured to provide the bus state signal indicating the busy state of the common error bus and to instruct the data transmission block to broadcast a fail code when the combinational logic determines an occurrence of a chip fail according to the at least a data signal, and to provide the bus state signal indicating the idle state of the common error bus when the combinational logic receives the reset signal; wherein the data transmission block is configured to broadcast a fail code on the bus data line when receiving the local busy signal and to stop broadcasting when receiving the reset signal; and a control center, configured to record a fail code from the common error bus and to report the recorded fail code when required.