Patent ID: 7736944

Claim:
A manufacturing method of semiconductor devices including semiconductor chips comprising steps of: (a) setting a plurality of semiconductor chip disposal regions, on which a plurality of the semiconductor chips is to be disposed at predetermined intervals, on a base comprising a first surface and a second surface which opposes the first surface, and forming a construction for aiding singularization so as to surround the semiconductor chip disposal regions; (b) providing a semiconductor chip having a first main surface on which a plurality of electrode pads is provided, a second main surface which opposes the first main surface, and a plurality of side surfaces positioned between the first main surface and second main surface on the semiconductor chip disposal region such that the second main surface faces the semiconductor chip disposal region; (c) forming an extension portion, having a first face and a second face which opposes the first face, on the base so as to contact the side surfaces of the semiconductor chip and thereby surround the semiconductor chip, such that the level of the first face is substantially equal to the level of the first main surface; (d) forming an insulating film on the first face of the extension portion and the first main surface such that a part of each of the electrode pads is exposed; (e) forming a plurality of wiring patterns on the insulating film so as to be electrically connected to the electrode pads, respectively and extended from the electrode pads to the upper side of the first face of the extension portion; (f) forming a sealing portion on the wiring patterns and insulating film such that a part of each of the wiring patterns positioned on the upper side of the first face is exposed; (g) forming a plurality of external terminals over the wiring patterns in a region including the upper side of the extension portion and connecting the external terminals to the wiring patterns; (h) forming individual semiconductor devices comprising the semiconductor chip by cutting along a cutting line which passes through the construction for aiding singularization; (i) forming position alignment marks on a region of the base other than the semiconductor chip disposal region; and (j) disposing the plurality of semiconductor chips at predetermined intervals while gradually adjusting the disposal positions of the semiconductor chips using the coordinates of the position alignment marks as a reference, whereby the plurality of semiconductor chips is disposed on the plurality of semiconductor chip disposal regions at the predetermined intervals.