Patent ID: 7534655

Claim:
A method for inkless wafer processing, the method comprising: receiving a full wafer, wherein the full wafer includes partial wafers, an orientation marker, and a reference die; selecting a non-circuit die on the full wafer; and cutting the full wafer along an edge of a selected one of the non-circuit die to provide the partial wafers, the cutting being performed in a particular direction relative to the orientation marker, wherein the cutting provides a first one of the partial wafers containing the reference die, and a second one of the partial wafers containing the selected one of the non-circuit die but excluding the reference die; selecting one partial wafer from the partial wafers; singulating the partial wafer to provide singular dies; loading the partial wafer for placement of the singular dies; receiving wafer map data for the full wafer, wherein the wafer map data includes a non-circuit bin; identifying the partial wafer; locating a non-circuit die from the non-circuit bin, wherein the non-circuit die on the partial wafer and the reference die are located in a row; assigning a pseudo reference die corresponding to the partial wafer, wherein the pseudo reference die and the non-circuit die from the non-circuit bin are adjacently disposed in the row; and initiating the placement of the singular dies using the pseudo reference die as a local reference die for the partial wafer.