Patent ID: 6948027

Claim:
An integrated circuit dynamic random access memory (“DRAM”) device having an integrated cache system, comprising: at least one DRAM array divided into a plurality of blocks; an auxiliary memory of the type not required to be refreshed; an address decoder coupled to receive a memory address and being operable to decode the address and generate decoded address signals corresponding thereto; an input/output circuit coupled to the at least one DRAM array, the auxiliary memory, and the address decoder, the input/output circuit being operable to respond to a first control signal by coupling write data from an external data terminal to a location in a block of the at least one DRAM array corresponding to the decoded address signals, or to respond to a second control signal by coupling write data from the external data terminal to a location in the auxiliary memory, or to respond to a third control signal by coupling data from the auxiliary memory to a location in a block of the at least one DRAM array corresponding to the decoded address signals; and a control circuit coupled to the at least one DRAM array, the auxiliary memory, the address decoder, and the input/output circuit, the control circuit being operable to refresh the at least one DRAM array one block at a time, the control circuit further being operable to generate the first control signal when the block of the at least one DRAM array corresponding to the decoded address signals is not being refreshed, to generate the second control signal when the block of the at least one DRAM array corresponding to the decoded address signals is being refreshed, to generate the third control signal when the block of the at least one DRAM array that was being refreshed when the data was stored in one of the auxiliary memory is no longer being refreshed.