Patent ID: 7402855

Claim:
An anti-fuse memory array comprising: a plurality of anti-fuse transistors arranged in rows and columns, each anti-fuse transistor including a polysilicon gate over a channel region in a substrate, the channel having a preset length; a diffusion region proximate to a first end of the channel region; a variable thickness gate oxide between the polysilicon gate and the substrate, the variable thickness gate oxide having a thick gate oxide portion extending from the first end of the channel region to a predetermined distance of the preset length, and a thin gate oxide portion extending from the predetermined distance to a second end of the channel region, an oxide breakdown zone proximate to the second end of the channel region fusible to form a conductive link between the polysilicon gate and the channel region; bitlines coupled to the diffusion regions of a column of anti-fuse transistors; a sense amplifier coupled to a pair of the bitlines through isolation devices, said isolation devices including transistors, each having a gate oxide corresponding to said thick gate oxide portion; and wordlines coupled to the polysilicon gates of a row of anti-fuse transistors.