Patent ID: 7036062

Claim:
An integrated circuit design-for-test focused tester comprising: a printed circuit board; a vector memory carried on the printed circuit board; a tester controller memory carried on the printed circuit board; a communications and control circuitry section carried on the printed circuit board for receiving test sequence data and tester command data for performing at least one design-for-test test of a connected integrated circuit device from a systems controller and loading said test sequence data in the vector memory and loading said tester command data in the tester controller memory; a set of design-for-test test signals derived from the test sequence data; a tester controller carried on the printed circuit board for controlling the design-for-test focused tester according to the tester command data loaded in the tester controller memory; and a vector sequencer circuitry section carried on the printed circuit board and operating under control of the tester controller to drive the connected integrated circuit device with the set of design-for-test test signals so as to run the connected integrated circuit device through the at least one design-for-test test, the vector sequencer circuitry section further operating under control of the tester controller to: 1) receive signals produced during the at least one design-for-test test by the connected integrated circuit device, 2) compare the received signals to expected results and 3) produce test results data noting differences of the received signals from the expected results.