Patent ID: 8753927

Claim:
A method of forming a semiconductor structure, said method comprising: forming at least one opening within an interconnect dielectric material; and forming an anti-fuse structure within the least one opening, wherein said forming the anti-fuse structure comprises: forming a contiguous layer of a diffusion barrier material on an exposed uppermost surface of the interconnect dielectric material and at least within the at least one opening; forming a contiguous layer of a first conductive metal on an exposed surface of the contiguous layer of the diffusion barrier material; performing a reflow anneal which causes portions of the contiguous layer of the first conductive metal to flow into the at least one opening forming a first conductive metal plug within the at least one opening, wherein a remaining portion of the contiguous layer of the first conductive metal which is present inside and outside the at least one opening remains in contact with said first conductive metal plug; forming a contiguous layer of an anti-fuse material on exposed surfaces of the first conductive metal plug and the remaining portion of the contiguous layer of the first conductive metal; forming a contiguous layer of a second conductive metal on an exposed surface of the contiguous layer of the anti-fuse material; and removing a portion of the contiguous layer of the second conductive metal, a portion of the contiguous layer of the anti-fuse material, remaining portions of the contiguous layer of the first conductive metal, and a portion of the contiguous layer of the diffusion barrier material that are located outside of the at least one opening.