Patent ID: 8713285

Claim:
A system comprising: a read and write capable data memory storing a multi-dimensional data structure, and at least one processor; a programmable address generation unit comprising programmable descriptor memory, said programmable address generation unit configured to translate connection identifiers into real addresses in order to access the multi-dimensional data structure in a desired pattern; wherein said programmable descriptor memory further comprises a buffer descriptor memory, and said buffer descriptor memory is selected from the group consisting of point-to-point, broadcast, scatter, and gather buffer types; and wherein said descriptor memory further comprises a port descriptor memory, and said port descriptor memory is selected from the group consisting of FIFO, matrix transform, nested loop, end point, and non-recursive pattern port types; said address generation unit configured to calculate real addresses by executing a series of patterns pre-programmed by said least one processor into the address generation unit's port descriptor memory prior to accessing the multi-dimensional data structure, the address generation unit receiving as inputs a set of parameters defining characteristics of said patterns; wherein said connection identifier comprises a predefined number of bits, and said at least one processor loads said connection identifier into said buffer descriptor memory; said at least one processor further configured to access the multi-dimensional data structure at the real addresses calculated by the address generation unit using said patterns and said connection identifier.