Patent ID: 8084850

Claim:
A semiconductor chip package comprising: a substrate comprising a unitary substrate body having a first main surface, a second main surface, a cavity that defines an opening in the first main surface, and holes extending from the bottom of the cavity to the second main surface, a first interconnection pattern of conductive material integral with the substrate body and extending along the first main surface of the substrate body; a second interconnection pattern of conductive material integral with the substrate body and extending along the second main surface of the substrate body, wherein the holes of the substrate body open at portions of the second interconnection pattern; via conductors extending through the substrate body from the first interconnection pattern to the second interconnection pattern so as to electrically connect the first and second interconnection patterns; electrically conductive vias respectively disposed in the holes at the bottom of the cavity in the substrate body and contacting said portions of the second interconnection pattern; a semiconductor chip disposed within the cavity and mounted to the substrate, the chip having electrical contacts in the form of pads, the pads facing in a direction towards the bottom of the cavity such that the chip has a flip-chip orientation with respect to the substrate, and the pads being electrically conductively bonded to the vias so as to be electrically connected by the vias to said portions of the second interconnection pattern; and conductive bumps respectively bonded to the regions of the second interconnection pattern.