Patent ID: 8214417

Claim:
A floating point unit (FPU) comprising: an adder configured to add a first mantissa and a second mantissa; and an operand adjust unit coupled to provide at least the first mantissa to the adder, wherein the operand adjust unit is further coupled to receive a first operand and a second operand for a floating point add operation, and wherein the operand adjust unit is configured to right shift at least one mantissa corresponding to one of the first and second operands responsive to a shift count generated from exponent portions of the first and second operands, and wherein the operand adjust unit is configured to detect whether neither, one, or both of the first and second operands are subnormal numbers in parallel with at least the shift count generation, and wherein the operand adjust unit is configured to left shift by one bit a shifted mantissa resulting from the right shifting to generate the first mantissa, wherein the left shift is responsive to only one of the first and second operands being a subnormal floating point number, and wherein the operand adjust unit is configured to generate a first guard bit, a second guard bit, a round bit, and a sticky bit responsive to the right shifting, and wherein the first guard bit is a most significant bit right-shifted out of the shifted mantissa, and wherein the second guard bit is a second most significant bit right-shifted out of the shifted mantissa, and wherein the round bit is a third most significant bit right-shifted out of the mantissa, and the sticky bit is a logical OR of remaining bits right shifted out of the mantissa; and wherein the operand adjust unit is configured, responsive to performing the left shift, to generate: the first mantissa including the first guard bit as the least significant bit of the mantissa, a corresponding guard bit equal to the second guard bit, a corresponding round bit equal to the round bit of the shifted mantissa, and a corresponding sticky bit equal to the sticky bit of the shifted mantissa; and wherein the operand adjust unit is configured, responsive to not performing the left-shift, to generate: the corresponding guard bit equal to the first guard bit, the corresponding round bit equal to the second guard bit, and the corresponding sticky bit equal to the logical OR of the round bit corresponding to the shifted mantissa and the sticky bit corresponding to the shifted mantissa.