Patent ID: 8555209

Claim:
A method for forming a circuit layout, comprising: performing first proximity effect modeling based on photolithography proximity effects caused by a first layer by using a computer, wherein the first layer comprises a gate poly and a field poly formed on a substrate; performing second proximity effect modeling based on photolithography proximity effects caused by a second layer, wherein the second layer comprises an active layer positioned under the gate poly, and wherein performing the second proximity effect modeling includes calculating a pattern density of the active layer by using a computer; combining results of the first and second proximity effect modeling using a modeling algorithm by using a computer; performing proximity correction using the combined results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography by using a computer: inputting the circuit layer to a processor; generating a target based on the inputted circuit layout; performing the proximity correction on the generated target; and outputting the manipulated mask layout.