Patent ID: 6864517

Claim:
An integrated circuit comprising selected bipolar transistors from a first set of bipolar transistors and a second set of bipolar transistors formed in a semiconductor substrate; a SiGe layer formed on said semiconductor substrate; said first set of bipolar transistors formed in said substrate having a collector; a base formed in a base layer layer of crystalline silicon material which includes a base dopant and Ge and an emitter disposed above and abutting said base, in which an emitter dopant concentration intersects a Ge concentration at a depth into the base where the ramp rate of said Ge concentration is greater than a threshold value; said second set of bipolar transistors formed in said substrate having a collector; a base formed in said layer of crystalline silicon material which includes said base dopant and Ge; an additional layer of crystalline silicon material on second set of bipolar transistors, disposed above and abutting said base; and an emitter disposed above and abutting said additional layer of crystalline silicon material, in which an emitter dopant concentration intersects the base at a different vertical location relative to said Ge concentration where the ramp rate of said Ge concentration is less than a threshold value.