Patent ID: 8484441

Claim:
A hardware computer processor having control and data processing capabilities, said computer processor comprising: a hardware decode unit for decoding instructions and operable to separate control instructions from data processing instructions thereby to supply all control instructions and no data processing instructions to a dedicated hardware control processing facility; the dedicated hardware control processing facility comprising a control execution path dedicated to processing only said control instructions, said control execution path having its own control register file of a first bit width for handling control instructions of a first bit width and functional units comprising a branch unit, a hardware execution unit, and a load/store unit; and a dedicated hardware data processing facility dedicated to processing said data processing instructions, said dedicated data processing facility separate from said dedicated control processing facility and having its own data register file separate from said control register file, said data register file having a second bit width for handling data processing instructions of a second bit width, said second bit width wider than the first bit width, said dedicated data processing facility comprising a first data execution path including fixed operators and a second data execution path including at least configurable operators and a controller, both of said first and second data execution paths separate from said control execution path and each other, wherein said configurable operators are pre-configured into a plurality of hardwired operator classes; wherein said decode unit is operable to supply one of said control instructions to one of said functional units and operable to detect whether one of said data processing instructions defines a fixed data processing instruction or a configurable data processing instruction, wherein said configurable data processing instruction indicates at least one operand to be processed and includes an opcode portion defining the operation to be carried out on the at least one operand, said decode unit causing the computer processor to supply said one of said data processing instructions to said first data execution path for processing when said fixed data processing instruction is detected and to said second data execution path for processing when said configurable data processing instruction is detected; and wherein said controller is operable to configure the connectivity of said configurable operators in accordance with configuration information provided in the opcode portion of said configurable data processing instruction, and wherein said configurable operators are arranged to receive said at least one operand.