Patent ID: 8754394

Claim:
A variable resistive memory device, comprising: a plurality of active regions configured to be arrayed in rows in a first direction and in zigzags in a second direction so that first landing plugs and second landing plugs are alternately disposed in a second direction; a gate pattern configured to be stretched in the second direction while dividing each active region into a first portion and a second portion by running across the active region; the first landing plugs and the second landing plugs that are formed on the first portions and the second portions, respectively; bit lines configured to be stretched in the first direction and coupled with the first landing plugs through bit line contacts; first electrode contacts and second electrode contacts that are coupled with the second landing plugs of even-numbered rows and the second landing plugs of odd-numbered rows, respectively, among rows of the active regions arrayed in the first direction; first electrodes configured to be stretched in a third direction while being coupled with the first electrode contacts and cut over the second electrode contacts; second electrodes configured to be stretched in a fourth direction crossing the third direction while being coupled with the second electrode contacts and cut over the first electrode contacts; and a variable resistive material layer configured to be interposed between the first electrodes and the second electrodes, wherein the first electrode contacts and the second electrode contacts are alternately arrayed in the third direction and the fourth direction.