Patent ID: 8036034

Claim:
A semiconductor storage device comprising: a memory cell array having a plurality of memory cells, each of the memory cells capable of storing multiple bits of information allocated to a plurality of threshold voltage distributions; a sense amplifier circuit configured to read data stored in the memory cell as well as threshold voltage information indicative of at which position a threshold voltage of the memory cell is positioned in one of the plurality of threshold voltage distributions; a first data retaining circuit configured to retain the data and the threshold voltage information read from the memory cell; a second data retaining circuit configured to retain the data and the threshold voltage information read from the memory cell, and output the data and the threshold voltage information to an outside circuit; and a control circuit configured to control read, write, and erase operations on the memory cell array, the sense amplifier circuit being configured to perform a data-read operation and a threshold-voltage-information read operation at the same time by a series of voltage application operations to a word line connected to the memory cell, the control circuit being configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from the memory cell array and retained in the first data retaining circuit.