Patent ID: 7274546

Claim:
An apparatus for protecting an integrated circuit from an electrostatic discharge (ESD) event, comprising: a multiple stage triggering network configured between a pair of power rails; and a power clamp coupled to said multiple stage triggering network, said power clamp configured to discharge current from the ESD event; said multiple stage triggering network having a first control path and a second control path configured to individually control activation of said power clamp; said first control path further comprising a first inverter coupled to a first RC trigger stage, a second inverter coupled to an output of said first inverter, and PFET switch having a gate thereof coupled to an output of said second inverter, said PFET switch further coupled to a gate of said power clamp; and said second control path further comprising a second RC trigger stage coupled to said output of said first inverter, a third inverter coupled to said second RC trigger stage, a third RC trigger stage coupled to an output of said third inverter, and an NFET switch having a gate thereof coupled to said third RC trigger stage, said NFET switch further coupled to said gate of said power clamp.