Patent ID: 7652937

Claim:
A receiver architecture for a computer processor, the receiver architecture comprising: a first linear receiver stage configured to receive a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and to transform the differential DQS input signal into a first differential output signal that swings between an upper supply voltage and a voltage corresponding to the upper supply voltage minus a first programmable swing voltage; a second linear receiver stage coupled to the first linear receiver stage, the second linear receiver stage being configured to receive the first differential output signal, and to shift the first differential output signal by a programmable shift voltage, resulting in a second differential output signal; a third linear receiver stage coupled to the second linear receiver stage, the third linear receiver stage being configured to receive the second differential output signal, and to transform the second differential output signal into a third differential output signal that swings between a lower supply voltage and a voltage corresponding to the lower supply voltage plus a second programmable swing voltage; and a programming architecture coupled to the first linear receiver stage, the second linear receiver stage, and the third linear receiver stage, the programming architecture being configured to set the first programmable swing voltage, the programmable shift voltage, and the second programmable swing voltage.