Patent ID: 8760925

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of memory blocks, the memory blocks including a first memory string and a second memory string, the first memory string including first memory transistors and a first transistor, the second memory string including second memory transistors and a second transistor; a first select transistor electrically connected to a first end of the first memory string; a second select transistor electrically connected to a first end of the second memory string; word lines electrically connected to gates of the first memory transistors and gates of the second memory transistors; a first select gate line electrically connected to a gate of the first select transistor; a second select gate line electrically connected to a gate of the second select transistor; a first line electrically connected to a gate of the first transistor and a gate of the second transistor; transfer transistors including a third transistor to a sixth transistor, a first end of the third transistor being electrically connected to the first select gate line, a first end of the fourth transistor being electrically connected to the second select gate line, a first end of the fifth transistor being electrically connected to the first line, and a first end of the sixth transistor being electrically connected to the first line; a second line electrically connected to gates of the third transistor and the fourth transistor; a third line electrically connected to a gate of the fifth transistor, the third line being different from the second line; and a fourth line electrically connected to a gate of the sixth transistor, the fourth line being different from the second line and the third line.