Patent ID: 7035755

Claim:
A system for controlling test instruments that are configured to test one or more integrated circuits, the system comprising: a master clock directly connected to each of two or more test instruments, the master clock being configured to provide a master clock signal to the two or more test instruments, the two or more test instruments being connected to form a communication ring, each of the two or more test instruments including an input port and an output port, the output port of a first test instrument being connected only to the input port of a second test instrument, a data word provided to the input port of the first test instrument being provided to the input port of the second test instrument only by the output port of the first test instrument; and a controller connected to the communication ring, the controller being configured to align counters of the two or more test instruments to derive a common clock time value from the master clock signal, the controller being further configured to generate and send data words into the communication ring to carry the data words to each of the two or more test instruments, the data words including at least one data word specifying a test event to be performed, a common clock time value, and at least one of the two or more test instruments, wherein the at least one of the two or more test instruments is configured to perform the test event at the time specified by the common clock time value.