Patent ID: 8304342

Claim:
A method of forming a semiconductor device, comprising: forming a gate stack over a semiconductor substrate, the gate stack having a height and including a layer of gate dielectric material formed over the substrate, a layer of gate electrode material including polysilicon formed over the layer of gate dielectric material, and a layer of silicon-germanium (SiGe) material formed over and in direct contact with the layer of gate electrode material; forming a layer of first dielectric material over the gate stack and over regions of the substrate adjacent to the gate stack; forming a layer of second dielectric material over the layer of first dielectric material, the layers of first and second dielectric materials having a combined thickness greater than the height of the gate stack; performing a chemical mechanical polishing (CMP) process to planarize the layers of first and second dielectric materials down to expose the layer of silicon-germanium material; following the chemical mechanical polishing (CMP) process, selectively chemically etching the layer of silicon-germanium material using an etchant to expose the polysilicon; following the chemically etching, forming a blanket layer of siliciding material over the planarized layers of first and second dielectric materials and over the exposed polysilicon; and reacting the siliciding material with the polysilicon to form a silicide.