Patent ID: 8111553

Claim:
A non-volatile semiconductor memory device, comprising: at least one memory cell block including a plurality of memory cells, each memory cell including a memory transistor and a selection transistor serially connected between a plurality of bit lines and a common source line, the memory transistor and the selection transistor having gates respectively connected to a plurality of selection lines and a plurality of word lines disposed in a direction perpendicular to the bit lines; a bit line selection switch block including a plurality of bit line selection switches configured to electrically connect the bit lines with corresponding global bit lines in response to voltages applied to a plurality of bit line selection switch lines, respectively; and a controller configured to decode an address applied externally at the time of a program operation, control the voltage applied to the bit line selection switch line, and electrically disconnect a bit line that is not selected from the global bit line to float the bit line that is not selected.