Patent ID: 7973575

Claim:
A programmable frequency divider comprising: a divided clock generator dividing a frequency of an input clock signal F in by a first divide ratio (N+1) or a second divide ratio N according to a divide ratio control signal MC to generate a plurality of divided clock signals D out ; a counting unit counting a number CNT of the plurality of divided clock signals D out , by performing swallow mode counting and program mode counting sequentially on the plurality of divided clock signal D out ; a control signal generator generating the divide ratio control signal MC, using the number CNT of the plurality of divided clock signals D out , a count S by the swallow mode counting and a count P by the program mode counting, the count P corresponding to a maximum of the number CNT of the plurality of clock signals D out , feeding the divide ratio control signal MC back to the divided clock generator, and generating a reset control signal RST for resetting the counting unit; and a selector for selecting and outputting a count M out from among the count S and the count P, using the divide ratio control signal MC fed back from the control signal generator as a selection control signal.