Patent ID: 8819510

Claim:
An address and command port comprising: A. a data input and output lead and a clock lead; B. input and output circuitry having a lead connected to the input and output lead, a data in output, a data out input, and an output enable input; C. serial in parallel out circuitry having a data input connected to the data in output, a first data in output, a second data in output, and a clock input coupled to the clock lead; D. register circuitry having a first data in input connected to the first data in output, a second data in input connected to the second data in output, a first register data output, a second register data output, and an update clock input; and E. master controller circuitry having a data input connected to the data in output of the input and output circuitry, an enable output coupled to the output enable input of the input and output circuitry, an input connected to the first register data output, an input connected to the second register data output, a trace output, and a JTAG output.