Patent ID: 7838371

Claim:
A method of manufacturing a field effect transistor (FET), comprising: depositing a gate dielectric over a semiconductor region; depositing a dummy structure over the gate dielectric in a dummy structure region and patterning the dummy structure to have defined edges; depositing a first metallic layer with a first work function conformally over the gate dielectric and dummy structure; etching back the first metallic layer selectively from the top of the dummy structure and the top of the gate dielectric leaving the first metallic layer on the sides of the dummy structure on the gate dielectric; depositing a second metallic layer with a second work function different to the first work function conformally over the gate dielectric and dummy structure and over the first metallic layer on the sides of the dummy structure; etching back the second metallic layer selectively from the top of the dummy structure and the top of the gate dielectric leaving a second metallic layer on the first metallic layer on the sides of the dummy structure on the gate dielectric; removing the dummy structure leaving the first and second metallic layers on the gate dielectric as gate metallic layer having a longitudinally varying work function; and implanting source and drain regions longitudinally adjacent to the first and second metallic layers to form a field effect transistor with a gate having a material that varies longitudinally along its length.