Patent ID: 7521353

Claim:
A method for reducing dielectric overetch, the method comprising: depositing a layer or stack of at least semiconductive material; patterning and etching the layer or stack of at least semiconductive material to form at least semiconductive features; depositing first dielectric fill over and between the at least semiconductive features; planarizing to coexpose the first dielectric fill and the at least semiconductive features, forming a substantially planar surface; depositing a dielectric etch stop layer directly on the planar surface; depositing second dielectric material on the dielectric etch stop layer; etching a void in the second dielectric material, wherein the etch is selective between the second dielectric material and the dielectric etch stop layer, wherein the etch stops on the dielectric etch stop layer; and etching a portion of the dielectric etch stop layer to expose portions of the at least semiconductive features.