Patent ID: 7054897

Claim:
A memory structure comprising: an array of data elements; and access circuitry, wherein the access circuitry is operable in a first mode that provides parallel access to a set of data elements that are horizontally aligned in the array; in a second mode that provides parallel access to a set of data elements that are vertically aligned in the array; in a third mode that provides parallel access to a set of data elements that are horizontally aligned, and in a fourth mode that provides parallel access to a set of data elements that are vertically aligned, the data elements accessed in the third and fourth modes having data widths that differ from data widths of the data elements accessed in the first and second modes respectively, the access circuitry comprising: first enable lines, each first enable line being coupled to enable a set of data elements that are horizontally aligned in the array; and second enable lines, each second enable line being coupled to enable a set of data elements that are vertically aligned in the array, and third enable lines, each third enable line being coupled to enable a first set of data elements that are vertically aligned in the array and to enable a second set of data elements that are vertically aligned in the array, and an address decoder connected to the first, second, and third enable lines, wherein in the first and third modes, the address decoder activates one of the first enable lines corresponding to an address signal; in the second mode, the address decoder activates one of the second enable lines corresponding to the address signal; and in the fourth mode, the address decoder activates one of the third enable lines corresponding to the address signal.