Patent ID: 8219744

Claim:
A semiconductor memory device in which an operation is automatically carried out under a control of a processor, comprising: a first memory block including a plurality of nonvolatile memory cells, data held in the memory cells included in the first memory block being erased at a time; a plurality of second memory blocks including the memory cells, data held in the memory cells included in the second memory blocks being erase at a time, the number of the memory cells included in each of the second memory blocks being smaller than that in the first memory block; a sense amplifier which reads data from the memory cell and amplifies the data, the sense amplifier reading data from selected one of the second memory block and non-selected one of the second memory blocks continuously, when the data is read from one of the second memory block; a verification circuit which verifies whether or not write or erase of data to the memory cell has been carried out properly using the data read by the sense amplifier, the verification circuit, when the data is read from the non-selected one of the second memory cell block, determining that the write or erase of data has been performed properly regardless of the read data; and the processor which provides information concerning selection/non-selection of the second memory block to the verification circuit.