Patent ID: 8922276

Claim:
An operational amplifier circuit comprising: a non-inverting input terminal and an inverting input terminal; an output terminal; a constant current producing transistor; a differential pair of transistors comprising a first transistor and a second transistor the source terminals of which are connected to the drain terminal of the constant current producing transistor and which carry out a differential operation in a pair, the first transistor and the second transistor having the same conduction type as the conduction type of the constant current producing transistor; an input switching circuit carrying out switching between a first connection state and a second connection state, the first connection state being a state in which the non-inverting input terminal is connected to the gate terminal of the first transistor and, along with this, the inverting input terminal is connected to the gate terminal of the second transistor, and the second connection state being a state in which the inverting input terminal is connected to the gate terminal of the first transistor and, along with this, the non-inverting input terminal is connected to the gate terminal of the second transistor; a pair of active load transistors comprising a third transistor and a fourth transistor the gate electrodes of which are connected to each other and one of which is in a diode connection, the third transistor and the fourth transistor having a different conduction type from the conduction type of the constant current producing transistor, the first transistor and the second transistor; a differential switching circuit carrying out switching between a third connection state and a fourth connection state, the third connection state being a state in which the drain terminal of the third transistor is connected to the drain terminal of the first transistor and, along with this, the drain terminal of the fourth transistor is connected to the drain terminal of the second transistor, and the fourth connection state being a state in which the drain terminal of the third transistor is connected to the drain terminal of the second transistor and, along with this, the drain terminal of the fourth transistor is connected to the drain terminal of the first transistor; a buffer circuit connected to the drain terminal of the fourth transistor, outputting a voltage equal to the voltage of the drain terminal of the fourth transistor, and transmitting the outputted voltage to the output terminal at low output impedance; and a switching signal generator generating a signal for switching the connection states in the input switching circuit and the connection states in the differential switching circuit every specified period of time, the connection states in the input switching circuit and the connection states in the differential switching circuit being switched every specified period of time.