Patent ID: 7058120

Claim:
An integrated high-speed parallel-to-serial and serial-to-parallel transceiver, wherein the transceiver comprises: receiver section that includes: receiver clocking circuit operably coupled to produce at least one high frequency receiver clock; serial to parallel module operably coupled to convert inbound serial data into inbound parallel data at a rate corresponding to the at least one high frequency receiver clock; and receiver compensation operable to at least partially compensate for at least one of integrated circuit operational limitations and integrated circuit fabrication limitations of at least one of the receiver clocking circuit and the serial to parallel module, wherein the receiver clocking circuit and the receiver compensation further comprise: fine phase detector operably coupled to produce a fine difference signal based on a phase difference between the inbound serial data and a fine feedback clock that is representative of the at least one high frequency receiver clock; fine charge pump operably coupled to produce a voltage representative of the fine difference signal; coarse phase and frequency detector operably coupled to produce a coarse difference signal based on a difference between a reference clock and a coarse feedback clock that is representative of the at least one high frequency receiver clock; coarse charge pump operably coupled to produce a voltage representative of the coarse difference signal; filter operably coupled to filter the voltage representation of the coarse difference signal and the voltage representation of the fine difference signal to produce a filtered difference representation; voltage controlled oscillator operably coupled to produce an oscillation based on the filtered difference representation; post PLL filter operably coupled to amplify and filter the oscillation to produce the at least one high frequency receiver clock; and coarse divider operably coupled to produce the coarse feedback clock from the at least one high frequency receiver clock; transmitter section that includes: transmitter clocking circuit operably coupled to produce at least one high frequency transmitter clock; parallel to serial module operably coupled to convert outbound parallel data into outbound serial data at a rate corresponding to the at least one high frequency transmitter clock; and transmitter compensation operable to at least partially compensate for at least one of the integrated circuit operational limitations and the integrated circuit fabrication limitations of at least one of the transmitter clocking circuit and the parallel to serial module.