Patent ID: 7061807

Claim:
A semiconductor memory device comprising: a memory cell unit having a plurality of memory cells connected in series; a first select transistor connected to the memory unit at a first end; a second select transistor connected to the memory unit at a second end; and a programming circuit for programming into a selected memory cell among the plurality of memory cells, wherein the programming circuit applies, at a time of programming, a first voltage to a first gate electrode of the selected memory cell, applies a second voltage to a gate electrode of a second memory cell positioned between the selected memory cell and the second end and adjacent to the selected memory cell while applying the first voltage to the first gate electrode, the second voltage being lower than the first voltage, and applies a third voltage to a gate electrode of at least a third memory cell positioned between the memory cell, to which the second voltage is applied, and the second end while applying the first voltage to the first gate electrode, the third voltage being lower than the first voltage but higher than said second voltage, and applies a fourth voltage to a gate electrode of a fourth memory cell positioned between the selected memory cell and the first end and adjacent to the selected memory cell while applying the first voltage to the first gate electrode, the fourth voltage being higher than a fifth voltage which is a lowest voltage in all voltages applied to gate electrodes of all memory cells positioned between the selected memory cell and the second end while applying the first voltage to the first gate electrode.