Patent ID: 7662713

Claim:
A semiconductor device production method comprising the steps of: forming a first interconnection layer on a semiconductor substrate; forming an interlevel insulation film which covers the first interconnection layer; forming an interlevel connection opening in a predetermined interlevel connection opening region in the interlevel insulation film to expose a part of the first interconnection layer; forming a barrier layer on a region of the first interconnection layer after the formation of the first interconnection layer but before the formation of the interlevel insulation film, the region of the first interconnection layer including the interlevel connection opening region, and having a greater area than the interlevel connection opening region; and forming a second interconnection layer of gold as an uppermost interconnection layer on the interlevel insulation film so as to electrically connect the second interconnection layer to the first interconnection layer via the barrier layer in the interlevel connection opening, wherein the interlevel insulation film includes a first layer, a second layer, and a third layer filling a recess in the second layer.