Patent ID: 8462100

Claim:
A semiconductor device comprising: a substrate; a pixel comprising a transistor over the substrate; and a signal line driver circuit over the substrate, the signal line driver circuit comprising: a first transistor; a second transistor; a third transistor; and a fourth transistor, wherein one of a source and a drain of the first transistor is electrically connectable to a first terminal of a driver IC, wherein one of a source and a drain of the second transistor is electrically connectable to the first terminal of the driver IC, wherein one of a source and a drain of the third transistor is electrically connectable to a second terminal of the driver IC, wherein one of a source and a drain of the fourth transistor is electrically connectable to the second terminal of the driver IC, wherein the other of the source and the drain of the first transistor is electrically connected to a first signal line, wherein the other of the source and the drain of the second transistor is electrically connected to a second signal line, wherein the other of the source and the drain of the third transistor is electrically connected to a third signal line, and wherein the other of the source and the drain of the fourth transistor is electrically connected to a fourth signal line, wherein each of the transistor included in the pixel, the first transistor, the second transistor, the third transistor and the fourth transistor comprises: a gate electrode; a gate insulating layer; and an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer including indium, wherein the gate electrode, the gate insulating layer, and the oxide semiconductor layer are overlapped with each other and the gate insulating layer is interposed between the gate electrode and the oxide semiconductor layer.