Patent ID: 7904656

Claim:
A controller for interfacing with a storage medium, the storage medium being partitioned into multiple data wedges and sectors, the controller comprising: a buffer controller to arbitrate access to a buffer memory via a multi-channel bus; a storage medium interface through which data to and from the storage medium is transferred, the storage medium interface including DWFT (Data Wedge Format Table) cache circuitry having a DWFT cache memory to cache DWFT entries, the storage medium interface to access the sectors of the storage medium based on physical locations of the sectors, as defined by the DWFT entries cached within the DWFT cache memory; wherein the multi-channel bus includes a DWFT channel to which the DWFT cache circuitry is connected; and wherein in a DWFT tenure for the DWFT channel, a DWFT process performed by the DWFT cache circuitry reads DWFT entries stored in the buffer memory, and caches the DWFT entries in the DWFT cache memory.