Patent ID: 7120071

Claim:
A testing method for a semiconductor memory, comprising the steps of: storing data in each of a plurality of memory cell blocks; electrically connecting a first memory cell block with a sense amplifier in response to an enabled state of a first block selection signal and simultaneously electrically connecting a second memory cell block with the sense amplifier in response to an enabled state of a second block selection signal, the sense amplifier shared by the first memory cell block and the second memory cell block of the plurality of memory cell blocks; sensing data of the two memory cell blocks through the sense amplifier; and determining whether the sensed data is normal based on a bit line capacitance increase according to the connection of the two memory cell blocks; wherein the first and the second block selection signals are generated by a block selection signal generating circuit, the block selection signal generating circuit comprising: a first transistor inputting a control signal from an input node and outputting the control signal as the first block selection signal in response to a disabled state of a test mode enable signal, a second transistor inputting the control signal from the input node and outputting the control signal in response to an enabled state of the test mode enable signal, a first inverter outputting an inverted signal of the output signal from the second transistor as the first block selection signal, and a second inverter outputting an inverted signal of the control signal from the input node as the second block selection signal.