Patent ID: 7944237

Claim:
An integrated circuit comprising: a process register fabricated on the integrated circuit adapted to store a value indicating a strength of a fabrication process in which the integrated circuit was fabricated, the process adjust value not indicating a current operating temperature of the integrated circuit and not indicating a current operating voltage of the integrated circuit; a logic circuit fabricated on the integrated circuit; an adjustable register fabricated on the integrated circuit and connected to the logic circuit and comprising a data input, a data output, and a clock input; an adjustable buffer coupled between the logic circuit and the data input and comprising a buffer input, a buffer output, and a hold time adjustment input, which is controlled by the value stored in the process register and selects between a plurality of different propagation delays between the buffer input and the buffer output; and a control circuit fabricated on the integrated circuit and comprising a process monitor, which measures characteristics of semiconductor devices on the integrated circuit and loads the process adjust value into the process register that identifies the strength of the process with which the integrated circuit was fabricated.