Patent ID: 8791758

Claim:
An apparatus comprising: a gain circuit comprising a first gain transistor and a second gain transistor, wherein an emitter of the first gain transistor is electrically connected to an emitter of the second gain transistor, and wherein the first and second gain transistors have a first type of device polarity; and a buffer circuit comprising: a first buffer transistor comprising an emitter electrically connected to a base of the first gain transistor and a base configured to receive a first input signal; a second buffer transistor comprising an emitter electrically connected to a base of the second gain transistor and a base configured to receive a second input signal, wherein the first and second buffer transistors have a second type of device polarity opposite the first type of device polarity; a first linearization transistor comprising a collector electrically connected to the base of the first gain transistor and a base electrically connected to a collector of the first buffer transistor; and a second linearization transistor comprising a collector electrically connected to the base of the second gain transistor and a base electrically connected to a collector of the second buffer transistor, wherein the first and second linearization transistors have the first type of device polarity.