Patent ID: 7696041

Claim:
A method for fabricating an integrated circuit having a component, comprising: providing a substrate comprising a first surface; forming a mold on said first surface, said mold comprising at least one depression arranged in such a way that a contact region in a region of said first surface is at least partly uncovered, and wherein the depression comprises a lower section abutting the first surface and an upper section overlying the lower section and remote from the first surface; forming a sacrificial layer on sidewalls of said depression in solely the upper section of said depression, wherein the lower section of the depression is not covered with the sacrificial layer; forming a first electrode by applying a first conductive layer in the lower section of said depression and to said sacrificial layer in the upper section of said depression; removing said sacrificial layer in order to uncover said sidewalls of said mold in said upper section; applying a dielectric layer to said first conductive layer; and forming a second electrode by applying a second conductive layer to said dielectric layer.