Patent ID: 8362575

Claim:
An integrated circuit structure comprising: insulation regions comprising top surfaces; and a fin field-effect transistor (FinFET) comprising: a semiconductor fin over and adjacent to the insulation regions; a gate dielectric on a top surface, and extending on sidewalls, of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region over the insulation regions and adjoining the semiconductor fin, wherein the source/drain region comprises: a first semiconductor region comprising silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region, and wherein the first semiconductor region comprises an up-slant facet and a down-slant facet; and a second semiconductor region comprising silicon and the element, wherein the element has a second atomic percentage in the second semiconductor region with the second atomic percentage being lower than the first atomic percentage, wherein the second semiconductor region comprises a first portion on the up-slant facet and has a first thickness, and wherein a second portion of the second semiconductor region on the down-slant facet has a second thickness smaller than the first thickness.