Patent ID: 7848160

Claim:
A semiconductor storage device, comprising: a plurality of memory cells connected to first and second column trees; and a sensing circuit reading data from the memory cells, wherein the sensing circuit performs a read operation for a selected one of the memory cells, wherein the sensing circuit performs the read operation by electrically connecting the column tree that is connected to the read-selected memory cell to a sensing line and electrically connecting the column tree that is connected to a non-selected memory cell to a reference sensing line, wherein the sensing circuit electrically connects the first and second column trees, respectively, to the sensing line and the reference sensing line in response to a first control signal, wherein the sensing circuit electrically connects the first and second column trees, respectively, to the reference sensing line and the sensing line in response to a second control signal, and wherein the sensing circuit equalizes voltages at internal nodes thereof in response to the first and second control signals.