Patent ID: 8463972

Claim:
A computing platform comprising: at least one processor, wherein each of the at least one processor includes a local advanced programmable interrupt controller (APIC) and an interrupt descriptor table; a plurality of general purpose input/output (GPIO) pins communicatively coupled to the at least one processor via an emulated input/output APIC, the emulated input/output APIC communicatively coupled to the at least one processor via a local APIC associated with the at least one processor, wherein the GPIO pins are to be coupled to at least one peripheral device, each peripheral device to communicate via a data bus; and a kernel to execute on at least one of the at least one processors, the kernel configured to include a common GPIO driver serving as interrupt request routing agent, wherein the kernel is further configured to dynamically define interrupt routing information and interrupt descriptor tables for each of the at least one processor based on results of a call back function of discovered GPIO device drivers, and wherein the common GPIO driver is configured to retrigger interrupts received from a requesting device, at run time, as inter-processor interrupts, based on the interrupt descriptor table and identifier of the requesting device, wherein the computing platform is a mobile device having an architecture without PCI pins for interrupt request signals.