Patent ID: 7073043

Claim:
A multiprocessor data processing system (MP) comprising: a plurality of processors including a first processor and a second processor coupled together by an interconnect, wherein each processor comprises a cache coherency subsystem including a translation look-aside buffer (TLB), at least one execution unit and an associated execution queue, wherein said execution queue holds queue address instructions with real addresses translated from corresponding virtual address by said TLB; a memory coupled to said plurality of processors by said interconnect and which includes a page frame table (PFT) in which is stored a plurality of page table entries (PTEs) of virtual and real address translation pairs; operating logic associated with each processor for implementing a TLB invalidate (TLBI) response protocol that controls a response by each of said plurality of processors to receipt of TLBIs; and wherein, responsive to receipt of a TLBI by said first processor generated in response to a page fault at the PFT associated with a memory access operation of the first processor, said TLBI response protocol triggers said first processor to first drain queued address instructions from the execution queue of each of said at least one execution unit of said first processor before issuing said TLBI out on the interconnect, wherein said TLBI is snooped on the interconnect by the second processor only after draining of the execution queue has completed at said first processor.