Patent ID: 8745293

Claim:
A data processor, comprising: a first input buffer configured to store first input data and including a plurality of data storage areas, each data storage area being configured to store a sectional input data set; a second input buffer configured to store second input data that has been inputted prior to the first input data and including a plurality of data storage areas, each data storage area being configured to store a sectional input data set; an output buffer including a plurality of storage areas and being configured to store output data; a data converter connected between the first and second input buffers and the output buffer; and a register storing plural conversion patterns in conformity with a desired data format conversion, wherein the data converter is configured to generate the output data based on both the first input data that is currently stored in the first input buffer and the second input data that is currently stored in the second input buffer, in accordance with a selected one of the conversion patterns stored in the register, and to copy a sectional input data set from an arbitrary one of the plurality of data storage areas of the first and second input buffers to an arbitrary one of the data storage areas of the output buffer, based on the selected one of the conversion patterns.