Patent ID: 8582369

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; and a control circuit configured to control a voltage applied to the plurality of memory cells, the control circuit being configured to provide to the memory cells a threshold voltage distribution which is at least partly negative thereby erasing retained data of the memory cells, and to provide to the memory cells plural types of positive threshold voltage distributions thereby writing plural types of data to the memory cells, the control circuit being configured to, in a write operation on the memory cells, execute: a first write operation for providing plural types of positive threshold voltage distributions to a write-object first memory cell; a first write verify operation for verifying whether the positive plural types of threshold voltage distributions have been obtained in the first memory cell or not; a second write operation for providing a first threshold voltage distribution to a second memory cell adjacent to the first memory cell; the first threshold voltage distribution being a lowest threshold voltage distribution among the plural types of positive threshold voltage distributions; and a second write verify operation for verifying whether the first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold voltage distribution has been obtained in the second memory cell or not, and output results of the first write verify operation and the second write verify operation.