Patent ID: 6987048

Claim:
A method of fabricating a memory device comprising: providing a semiconductor substrate; forming a stacked gate over the semiconductor substrate, the stacked gate including a bottom dielectric layer, a charge storing dielectric layer formed over the bottom dielectric layer, a top dielectric layer formed over the charge storing dielectric layer, and a gate electrode formed over the top dielectric layer; forming a pair of silicided buried bitlines within the substrate, the silicided buried bitlines functioning as a source and a drain for the memory device; forming a wordline pad over the stacked gate, the step of forming a wordline pad comprising: forming a word line conductor along a first direction perpendicular to the direction along which the silicided buried bitlines extend; and selectively etching portions of the wordline conductor substantial above each silicided buried bitline; and forming at least one local interconnect in electrical contact with the wordline pad, said interconnect electrically connecting the wordline pad to at least one adjacent wordline pad.