Patent ID: 8045546

Claim:
An apparatus, comprising: a plurality of processor tiles, each processor tile comprising a processor core; an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores; and an extension network to connect input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the associated processor tile and receives output data from the associated processor tile, the extension network being configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable, and the extension network connecting a first portion of the input/output ports of one of the peripheral devices to a first portion of input/output ports of the interconnection network that are associated with processor tiles that are physically positioned closer to the peripheral device, and the extension network connecting a second portion of the input/output ports of the peripheral device to input/output ports of the interconnection network that are associated with processor tiles that are physically positioned farther away from the peripheral device.