Patent ID: 7061792

Claim:
An SRAM memory structure, comprising a plurality of 8T memory cells arranged in rows and columns, and defining multiple sectors, each sector comprising multiple rows and the sectors together defining all of the rows of the memory structure, a plurality of word lines for selecting rows of memory cells in the structure by being connected to transistor gates within the 8T memory cells, a plurality of column select lines for selecting columns of memory cells by being connected to transistor gates within the 8T memory cells, a pair of bit lines for each memory cell, and a plurality of sector select lines for defining shortened sections of columns, wherein each column select line is logically ANDed with each sector select line to define a local select line to allow the memory cells in the column corresponding to said column select line but limited to the sector corresponding to the desired sector select line to be selected for discharging, and wherein a column select line together with a word line and sector select line allows an individual memory cell to be selected for discharging.