Patent ID: 8089142

Claim:
A stacked die package comprising: a package substrate having a top side and a bottom side, the top side having a plurality of bond pads, and the bottom side having a ball-grid array pattern; a first semiconductor device mounted on the top side of the package substrate, the first semiconductor device having a plurality of bond pads; a silicon interposer mounted on the first semiconductor device, the interposer having a first interposer bond pad and a second interposer bond pad, wherein the first and second interposer bond pads are formed by a conductive trace, and wherein the interposer includes: an interposer substrate; a dielectric layer formed on the interposer substrate; the conductive trace formed on the dielectric layer; and a passivation layer formed on the conductive trace, the passivation layer having a plurality of windows to expose the conductive trace in areas defining the interposer bond pads; a second semiconductor device mounted on the interposer, the second semiconductor device having a plurality of bond pads; and a plurality of bond wires coupled between the bond pads of the package substrate, the first semiconductor device, the silicon interposer, and the second semiconductor device, wherein each of the plurality of bond wires is coupled between two adjacent layers of the stacked die package.