Patent ID: 8395364

Claim:
A semiconductor device including a DC-DC converter, comprising: a first die pad having a first lead for use as an input for the DC-DC converter; a second die pad having a second lead for use as an output for the DC-DC converter; a third die pad having a third lead; a fourth lead to supply a ground potential to the DC-DC converter; a first semiconductor chip including a high side MOSFET of the DC-DC converter, the first semiconductor chip being disposed over the first die pad, the first semiconductor chip having a top surface and a bottom surface opposite the top surface, the first semiconductor chip having a first gate electrode pad and a first source electrode pad on the top surface, and a first drain electrode on the bottom surface, the first drain electrode being coupled to the first die pad; a second semiconductor chip including a low side MOSFET of the DC-DC converter, the second semiconductor chip being disposed over the second die pad, the second semiconductor chip having a top surface and a bottom surface opposite the top surface, the second semiconductor chip having a second gate electrode pad and a second source electrode pad on the top surface, and a second drain electrode on the bottom surface, the second drain electrode being coupled to the second die pad; a third semiconductor chip including a first driver circuit to drive the high side MOSFET and a second driver circuit to drive the low side MOSFET, the third semiconductor chip being disposed over the third die pad, the third semiconductor chip having a top surface and a bottom surface opposite the top surface, the third semiconductor chip having a first pad and a second pad on the top surface, the first pad being coupled to an output of the first driver circuit, the second pad being coupled to an output of the second driver circuit; a first bonding wire being coupled to the first pad of the third semiconductor chip and the first gate electrode pad of the first semiconductor chip; a second bonding wire being coupled to the second pad of the third semiconductor chip and the second gate electrode pad of the second semiconductor chip; a first metal plate being coupled to the first source electrode pad of the first semiconductor chip and the second die pad; a second metal plate being coupled to the second source electrode pad of the second semiconductor chip and the fourth lead; and a sealing body sealing the first, second, and third semiconductor chips, portions of the first, second, third, and fourth leads and portions of the first, second, and third die pads being exposed from the resin body; wherein the second metal plate has a first, second, and third portions, the first portion is coupled to the second source electrode pad of the second semiconductor chip, the third portion is coupled to the fourth lead, and the second portion is coupled to the first and third portions, and wherein one or a plurality of first openings is formed in the second portion of the second metal plate.