Patent ID: 7998860

Claim:
A method for fabricating a semiconductor component comprising: providing a semiconductor substrate having a circuit side, a back side and a plurality of conductive vias comprising vias extending from the circuit side to the back side, an electrically insulating layer lining the vias and a metal in the vias; forming a plurality of circuit side conductors on the circuit side in electrical contact with the conductive vias; forming an outer dielectric layer on the circuit side having openings aligned with the conductive vias; removing portions of the semiconductor substrate from the back side to expose terminal portions and surfaces of the conductive vias extending from the back side with a height X; depositing a polymer layer on the back side encapsulating the terminal portions and the surfaces of the terminal portions with the polymer layer having a thickness equal to or greater than the height X; planarizing the polymer layer, the terminal portions and the surfaces of the terminal portions to form self aligned conductors comprising the metal embedded in the polymer layer, a planarized polymer surface and planarized contactors on the conductive vias, with the planarizing step controlled to endpoint at the surfaces of the conductive terminal portions; and forming a plurality of terminal contacts on the planarized contactors.