Patent ID: 8095831

Claim:
A data processing system, comprising: a processor; a cache coupled to the processor; and cache control circuitry coupled to the cache, the cache control circuitry performing error detection, the cache control circuitry further comprising a user programmable error action control register for storing a control value for selecting one of a plurality of error actions to be taken when a cache error is detected, wherein a first value of the control value selected by a user implements an automatic invalidation of a cache line containing the cache error without an exception being taken regardless of whether the cache line is dirty or clean, and a second value of the control value selected by the user implements an automatic invalidation of a cache line containing the cache error with an exception being taken regardless of whether the cache line is dirty or clean, wherein the user dynamically programs the control value which determines whether error action to be taken is a transparent operation or a non-transparent operation.