Patent ID: 6937074

Claim:
An apparatus for generating a power-up signal, comprising: a first power-up detecting circuit to which an external power supply voltage is applied, the first power-up detecting circuit configured to activate a first power-up signal when an increase of the external power supply voltage is detected; a second power-up detecting circuit to which an internal power supply voltage is applied, the second power-up detecting circuit configured to activate a second power-up signal when an increase of the internal power supply voltage is detected; and a power-up signal generating circuit configured to activate a final power-up signal in response to a combination of the first and second power-up signals, wherein the power-up signal generating circuit comprises: a first p-type metal oxide semiconductor (PMOS) transistor, a source of the first PMOS transistor being coupled to the external power supply voltage, and the first power-up signal being applied to a gate of the first PMOS transistor; a first n-type metal oxide semiconductor (NMOS) transistor, a source of the first NMOS transistor being coupled to a ground voltage, a drain of the first NMOS transistor being coupled to a drain of the first PMOS transistor, and the second power-up signal being applied to a gate of the first NMOS transistor; a second PMOS transistor, a source of the second PMOS transistor being coupled to the external power supply voltage, a gate of the second PMOS transistor being coupled to the around voltage, and a drain of the second PMOS transistor being coupled to the drain of the first PMOS transistor; a third PMOS transistor, a drain of the third PMOS transistor and a source of the third PMOS transistor being coupled to the external power supply voltage, and a gate of the third PMOS transistor being coupled to the drain of the first PMOS transistor; a first inverter configured to invert a signal from the drain of the first PMOS transistor; a second inverter configured to invert a signal from the first inverter; and a third inverter configured to invert a signal from the second inverter.