Patent ID: 6898142

Claim:
A semiconductor memory device including a memory cell array area divided into a plurality of areas, wherein said semiconductor memory device further includes: at least one programmable circuit for setting a value of at least one output signal through programming; at least one area setting unit being electrically coupled between said memory cell array area and said at least one programmable circuit for deciding an area corresponding to an address signal, which selects said memory cell, in accordance with an output signal from said programmable circuit and for setting at least one area from said plurality of areas based on said address signal; and at least one refresh operation control unit being electrically coupled to said memory cell array area for making said area setting unit to set a specific area in said plurality of areas and refreshing said specific area based on at least one kind of specific refresh control signal having a longer cycle than a basic refresh control signal at least when said semiconductor memory device is in a predetermined state.