Patent ID: 8149150

Claim:
A cyclic analog/digital converter for processing an input signal having a first signal level and a second signal level, the first signal level including a noise component, and the second signal level including a signal component superimposed on the noise component, comprising: a gain stage having first, second and third capacitors and an operational amplifier circuit, the gain stage performing a process for noise cancellation and amplification to generate a difference signal and a process for cyclic A/D conversion of the difference signal, and the difference signal indicating a difference between the first and second signal levels; a sub A/D converter circuit receiving a signal from an output of the operational amplifier circuit; a logic circuit connected to the sub A/D converter circuit; a D/A converter circuit operable in accordance with a control signal from the logic circuit; and a timing circuit for controlling operations of the process for noise cancellation and amplification and the process for cyclic A/D conversion of the gain stage, in the process for noise cancellation, the gain stage sampling either one of the first and second signal levels into each of the first and second capacitors, and, in response to reception of another of the first and second signal levels through the first and second capacitors at an input of the operational amplifier circuit to which the third capacitor is connected as a feedback capacitor, the gain stage generating the difference signal at an output of the operational amplifier circuit and storing the difference signal in each of the first and second capacitors, and in the process for cyclic A/D conversion, the gain stage receiving a signal from the D/A converter circuit through the first capacitor at the input of the operational amplifier circuit to which each of the second and third capacitors are connected as a feedback capacitor, to generate an operation value at the output of the operational amplifier circuit, and sampling the operation value into the first capacitor.