Patent ID: 8367475

Claim:
A method, comprising: forming a substrate panel that includes a plurality of substrates that each include routing; testing the substrates in the substrate panel to determine a set of working substrates; singulating the substrate panel to separate the plurality of substrates; attaching a subset of the separated substrates to a surface of a carrier, the subset of the separated substrates being the set of working substrates; mounting one or more dies to each of the substrates on the carrier; encapsulating the dies and the substrates on the carrier with a molding compound; detaching the carrier from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates; attaching a plurality of interconnects to each of the substrates at a surface of the molded assembly; and singulating the molded assembly to form a plurality of integrated circuit packages, each integrated circuit package including at least one of the dies and a substrate having a peripheral ring of the molding compound around an outer edge of the substrate.