Patent ID: 7016230

Claim:
A non-volatile semiconductor memory device comprising a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a sense amplifier circuit for reading said memory cell array, wherein said sense amplifier circuit comprises: a first transistor disposed between a bit line of said memory cell array and a sense node to serve for sensing bit line data, said first transistor being driven by a voltage generating circuit including a boost circuit to transfer a bit line voltage determined in response to data of a selected memory cell to said sense node; a second transistor coupled to said sense node for precharging said sense node prior to bit line data sensing; a data latch for judging a transferred bit line voltage level to store a sensed data therein; and a capacitor for boosting said sense node, one end thereof being connected to said sense node, the other end thereof being alternatively given a first voltage and a second voltage higher than the first voltage.