Patent ID: 7091079

Claim:
A method of forming transistors having three different operation voltages, comprising: providing a substrate, the substrate being a first conductive type well and comprising a high voltage (HV) region, a medium voltage (MV) region, and a low voltage (LV) region; forming at least a deep well with a second conductive type encompassing the LV region and the MV region in the substrate; forming a plurality of first conductive type wells and second conductive type wells in the HV region, the MV region, and the LV region; forming a gate oxide layer with a first thickness on the substrate, and covering the HV region, the MV region, and the LV region; performing a first implantation process upon the MV region and the LV region, and partially removing the gate oxide layer in the MV region and the LV region so that the gate oxide layer has a second thickness in the MV region and the LV region; performing a second implantation process upon the LV region, and partially removing the gate oxide layer in the LV region so that the gate oxide layer has a third thickness in the LV region; forming a gate over each first conductive type well and each second conductive type well; and forming a source and a drain in each first conductive type well and each second conductive type well to respectively form a plurality of HV transistors in the HV region, a plurality of MV transistors in the MV region, and a plurality of LV transistors in the LV region.