Patent ID: 7965556

Claim:
A semiconductor memory device comprising: a first semiconductor chip; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip; a second nonvolatile memory provided on the second semiconductor chip; a system bus which directly connects the first and second nonvolatile memories; a plurality of data terminals connected to the first and second nonvolatile memories through the system bus; and an enable terminal connected to the first and second nonvolatile memories, wherein: the first nonvolatile memory is configured to receive an enable signal from the enable terminal; the first nonvolatile memory is configured to sequentially output data to the system bus in response to the enable signal, the data including a first piece of data and a second piece of data to be output next to the first piece of data; the first nonvolatile memory is configured to output the first piece of data to the system bus in response to a first edge of the enable signal; the first nonvolatile memory is configured to output the second piece of data to the system bus in response to a second edge of the enable signal; and the second nonvolatile memory is configured to latch the first piece of data output from the first nonvolatile memory, through the system bus, before the first nonvolatile memory outputs the second piece of data.