Patent ID: 8327249

Claim:
An apparatus comprising: a controller configured to monitor a bus and capture operation codes (opcodes) transmitted over the bus, the bus being configured to transmit memory opcodes and non-memory opcodes; an opcode decoder operationally coupled with the controller, the opcode decoder being configured to determine if a captured opcode is a memory write operation or a memory read operation; and a parity module operationally coupled with the opcode decoder, the parity module being configured to: calculate a parity bit for data associated with the memory write operation; calculate a parity bit for data associated with the memory read operation; compare the calculated parity bit for the data associated with the memory read operation with a previously stored parity bit for the data associated with the memory read operation; and in the event the calculated parity bit for the data associated with the memory read operation and the previously stored parity bit for the data associated with the memory read operation do not match, provide at least one of a hardware parity error notification and a software parity error notification.