Patent ID: 7441065

Claim:
A system for bi-directional transmission of data between a source and sink over a Display Data Channel (DDC) compatible two-wire interface, the system comprising: a first translator responsive to and operative to develop a first local I 2 C bus signal for signal current flow in a first direction and responsive to and operative to develop a different protocol signal over the DDC-compatible two-wire interface for signal current flow in a second direction; the first translator including an I 2 C port for converting serial data signal and serial clock signal into internal signal blocks, a translation logic for translating the internal signal blocks to the different protocol signal, and a physical interface for interfacing the translated different protocol signal onto the DDC-compatible two-wire interface; a first buffer responsive to and operative to develop the first local I 2 C bus signal for signal current flow in the first direction and responsive to and operative to develop a buffered signal including a buffered data signal and a buffered clock signal for signal current flow in the second direction; the first buffer including a first data buffer circuit for assisting the current flow of the serial data signal to extend the distance over which the serial data signal may be communicated, and a first clock buffer circuit for assisting the current flow of the serial clock signal to extend the distance over which the serial clock signal may be communicated; the buffered data signal being communicated over a first wire of the DDC-compatible two-wire interface and the buffered clock signal being communicated over a second wire of the DDC-compatible two-wire interface; a logic responsive to the first local I 2 C bus signal and operative to control a first switch coupled to the DDC-compatible two-wire interface wherein the first switch connects the DDC-compatible two-wire interface to one of the first translator, the first buffer, and an isolation firewall in which electrical access to the source via the DDC two-wire interface is cut off; a second translator responsive to and operative to develop the different protocol signal for signal current flow in the first direction and responsive to and operative to develop a second local I 2 C bus signal for signal current flow in the second direction when the first switch is connected to the first translator and a second switch coupled to the DDC-compatible two-wire interface is connected to the second translator; and a second buffer responsive to and operative to develop the buffered signal including the buffered data signal and the buffered clock signal for signal current flow in the second direction; and responsive to and operative to develop the second local I 2 C bus signal for signal current flow in the first direction when the first switch is connected to the first buffer and the second switch coupled to the DDC-compatible two-wire interface is connected to the second buffer.