Patent ID: 7292576

Claim:
An ATM switch comprising: at least one basic switch, said basic switch including output buffer parts, each corresponding to one of output lines and each being connected to input lines of said basic switch, each of said output buffer parts including: output buffers, each corresponding to one of said input lines; a time sorting part which is connected to said output buffers, wherein said time sorting part outputs a head cell stored in one of said output buffers; and address filters, each being provided in front of one of said output buffers and being connected to one of said input lines, wherein each of said address filters stores a cell arriving from an input line connected to said each address filter in a corresponding output buffer as an actual cell if a destination of said cell is an output line corresponding to said address filters, and each of said address filters stores said cell as a dummy cell in said corresponding output buffer if said destination of said cell is not said output line corresponding to said address filters, wherein, when a dummy cell arrives from an input line, said basic switch stores said dummy cell in said output buffers each corresponding to said input line from which said dummy cell arrives, wherein, a time stamp and cell type information of said head cell are sent to said time sorting part from each of said output buffers, so that said time sorting part checks a number of head cells having the earliest time stamp, and outputs a head cell having the earliest time stamp if the number is one, and wherein if the number is larger than one, said time sorting part checks a number of actual head cells having the earliest time stamp, and if there is no actual head cell, said time sorting part selects and outputs a dummy head cell randomly, and if there are a plurality of actual head cells, said time sorting part selects and outputs an actual head cell which is stored in an output buffer having the longest queue length.