Patent ID: 8037214

Claim:
A method of controlling direct memory access, the method comprising: reading and storing data to be transmitted in response to a direct memory access controller (DMAC) operation request; first-transmitting a portion of the data corresponding to an initial burst size to a data destination; after resetting a burst size according to an available storage size of the data destination, second-transmitting another portion of the data corresponding to the reset burst size to the data destination; if all the data are not transmitted through the first-transmitting and the second-transmitting, repeating the second-transmitting until all the data are transmitted; and if all the data are transmitted through the first-transmitting and the second-transmitting, generating an interrupt signal, wherein the reading and storing of the data comprises: obtaining bus mastership in response to the DMAC operation request from the data destination; enabling a channel through which a DMAC operation is requested and checking a data source, the data destination, a total amount of the data to be transmitted, and the initial burst size; and after reading the data by accessing the data source, storing the read data in an internal storage medium, and the second-transmitting comprises: checking the state of the data destination each time a portion of the data is transmitted through the first-transmitting or the second-transmitting; resetting the burst size according to the state of the data destination; and reading another portion of the data corresponding to the reset burst size and transmitting the read portion of the data to the data destination.