Patent ID: 7276433

Claim:
A method of forming memory circuitry comprising: providing a silicon-comprising substrate comprising a memory array area and a peripheral circuitry area, the memory array area comprising a first pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate in at least a first cross-section of the substrate, the peripheral circuitry area comprising a second pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate at least in a second cross-section of the substrate, the conductive structures of the second pair being spaced further from one another in the second cross-section than are those of the first pair in the first cross-section; depositing a masking material between the conductive structures of each of the first and second pairs; removing the masking material effective to expose silicon between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section; after the removing effective to expose silicon, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section; and after the annealing, removing at least some of the masking material from between the conductive structures of the first pair in the first cross-section.