Patent ID: 7864617

Claim:
A memory comprising: a first plurality of memory cells, each of the first plurality of memory cells having a first terminal coupled to a bit line, a second terminal coupled to a word line, and a power supply terminal; a first selection circuit having a first input, a second input coupled to a first power supply voltage terminal, an output coupled to the power supply terminal of each of the first plurality of memory cells, and a control input for receiving a first write assist control signal; and a first write assist circuit coupled to the first input of the first selection circuit, the first write assist circuit for reducing a voltage at the power supply terminal of each of the first plurality of memory cells to a first predetermined magnitude during a write operation and in response to an asserted first write assist enable signal, the first write assist circuit comprising: a first transistor of the first conductivity type having a first current electrode coupled to the first input, a second current electrode selectively coupled to a second power supply voltage terminal, and a control electrode coupled to receive a first variable bias voltage, the first transistor of the first conductivity type for modifying a voltage at the power supply terminal of each memory cell of the plurality of memory cells to the first predetermined magnitude during the write operation; and a first bias voltage generator coupled to the control electrode of the first transistor of the first conductivity type, the first bias voltage generator for providing the first variable bias voltage in response to the asserted first write assist enable signal.