Patent ID: 8190809

Claim:
Apparatus for addressing a memory of a computer system, the memory containing individually and successively addressable memory banks where is an integer, each memory bank having a plurality of individually addressable rows, each row containing a plurality of individually and successively addressable data cells for storing data arranged such that upon addressing and accessing a data cell in a row of a memory bank, all of the other data cells of the row containing the addressed data cell are partially accessed, and all the data cells of the row are available for a quicker next access than for an access to a data cell in any other of the bank's rows not already accessed or partially accessed, the apparatus comprising: a bank select device for choosing bank selects for addressing the memory banks in an offset interleaved pattern, the bank select device comprising a plurality of addressable locations, and a plurality of storage locations, each storage location being correlated to a respective one or more of the plurality of addressable locations and each addressable location being correlated to one of the plurality of storage locations, each storage location storing a respective bank select for addressing a respective one of the memory banks, there being as many storage locations as memory banks and at least as many addressable rows in all of the memory banks as there are addressable locations, the addressable locations and storage locations being grouped into a plurality of interleave patterns such that, for each interleave pattern, there are Q storage locations and there are 2 A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and one remainder loop containing R sequentially addressable locations, where L·Q+R=2 A , 0<R<Q, ≧Q≧3 and Q has at least one odd factor greater than 1, and where A, L, Q and R are integers, a shunt having a value S defining an offset as a difference in bank selects for successive interleave patterns so that each interleave pattern of the plurality of interleave patterns commences with a different bank select and a complete rotation of all of the interleave patterns addresses each of the memory banks an equal number of times, the bank select device being responsive to an input address to an addressable location to choose the bank select from the correlated storage location such that successive input addresses addressing successive addressable locations during execution of an interleave pattern choose successive bank selects, the plurality of interleave patterns being organized so that bank selects are chosen to address a different set of Q successive memory banks as offset by S for successive ones of the plurality of interleave patterns; and address apparatus responsive to memory addresses to address memory banks using the banks selects chosen by the bank select device.