Patent ID: 7804346

Claim:
A level converting flip-flop comprising: a data input circuit configured to generate a pull-up current in response to an input data signal having one of an input supply voltage smaller than an output supply voltage and a ground voltage; a clocking circuit configured to provide the pull-up current to an internal node in response to a clock signal having the input supply voltage and the ground voltage; a current mirror circuit configured to pull-up an output node to the output supply voltage in response to the pull-up current provided to the internal node; a latch circuit configured to latch an output data signal generated at the output node; and a switch transistor configured to block the pull-up current in response to an inverse signal of the output data signal, a source of the switch transistor being connected to the ground voltage, wherein the data input circuit is configured to generate a pull-down current in response to the input data signal, the clocking circuit is configured to provide the pull-down current to the output node in response to the clock signal, the data input circuit includes, a first input transistor including a gate configured to receive the input data signal and a source connected to a drain of the switch transistor, a first inverter configured to invert the input data signal, and a second input transistor including a gate configured to receive an output signal of the first inverter and a source connected to the ground voltage, and the clocking circuit includes, a buffer configured to buffer the clock signal, a second inverter configured to generate a delayed inverse clock signal by inverting an output signal of the buffer, a first clocking transistor configured to provide the pull-up current to the internal node in response to the clock signal, a source of the first clocking transistor connected to a drain of the first input transistor, a second clocking transistor configured to provide the pull-down current to the output node in response to the clock signal, a source of the second clocking transistor connected to a drain of the second input transistor, and a third clocking transistor configured to provide the pull-down current to a source of the second clocking transistor in response to the delayed inverse clock signal.