Patent ID: 8438003

Claim:
A computer-implemented method of improving simulator processing, the method comprising: allocating data used by a simulation scheduler; simulating predication in a non-predicated architecture, wherein the simulated predication comprises: determination of a maximum pseudo-predicated instruction sequence length by considering target machine microarchitecture characteristics; implementation of multi-valued read-operation and multi-valued write-operation vector element access, wherein any of the multi-value read-operation and the multi-valued write-operation can be expressed as 0/1/X/Z bits; and implementation of multi-way branches with assignment statements having a same left-hand-side (lhs); determining a selection path in a multi-sensitive “always” block to reduce taken multi-way branches, and generating code; wherein allocating data used by a simulation scheduler further comprises: probing a line size of a processor cache; providing a software override of a value of the probed line size; and selecting one or more of a core routine algorithm and data structure for the simulation scheduler, wherein a sum of line sizes is not greater than a d1_linesize, wherein the d1_linesize is a line size of a level 1 data cache.