Patent ID: RE41205

Claim:
A method of fabricating a semiconductor device comprising the steps of: forming a field oxide layer defining , which defines an active area and a field area on a semiconductor substrate of a first conductive type; forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate; forming impurity regions of a second conductive type in the semiconductor substrate in use of using the gate as a mask; forming a first insulating interlayer layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate; forming a second insulating interlayer layer on the first insulating interlayer layer by depositing another insulator of which an etch rate is different from that of the first insulating interlayer layer ; forming a third insulating interlayer layer on the second insulating interlayer layer by depositing still another insulator of which an etch rate is different from that of the second insulating interlayer layer ; and forming a first contact hole and second contact holes respectively exposing the gate and heavily doped impurity regions respectively by successively patterning the third to first insulating interlayer successively by layers through photolithography , wherein the second insulating layer is etched by C 2 HF 6 O 2 , and wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer .