Patent ID: 7853737

Claim:
A communication data processing device comprising: a memory storing data; a plurality of buffer memories coupled to the memory via a data bus, each said buffer memory capable of receiving data and providing data independently from the other buffer memories; a selector coupled to the plurality of buffer memories; a data read request queue storing read requests for requesting data to be read from the memory and written into one of the plurality of buffer memories; a bus arbiter coupled to the memory and the data read request queue, the bus arbiter arbitrating a data transfer via the data bus from the memory to one of the plurality of buffer memories in response to the read request; a selection control data queue coupled to the selector, the selection control data queue storing selection control data indicating which one of the plurality of buffer memories is selected by the selector; an alignment logic coupled to the selector, the alignment logic aligning data output from the selector into a sequence corresponding to a packet communication; and a controlling section coupled to the plurality of buffer memories and the selection control data queue, wherein each of the plurality of buffer memories sends a ready signal to the controlling section in response to a completion of data transfer from the memory into the buffer memory, thereby indicating that the buffer memory is ready to transfer data to the alignment logic, wherein the controlling section places the selection control data in the selection control data queue to indicate a buffer memory which sends the ready signal.