Patent ID: 7171529

Claim:
A microcomputer in which a CPU, a plurality of memory macros, and an interleave controller are positioned on a chip, said interleave controller allowing for interleaving in which the plurality of memory macros are operated alternately based on whether memory addresses output by the CPU for memory accesses are odd or even, said microcomputer comprising: a plurality of dedicated read clock generating circuits; wherein each dedicated read clock generating circuit of the plurality of dedicated read clock generating circuits is separate and apart from said interleave controller; wherein each dedicated read clock generating circuit of the plurality of dedicated read clock generating circuits is configured to generate a respective read clock signal by receiving and frequency-dividing a system clock signal; wherein each dedicated read clock generating circuit of the plurality of dedicated read clock generating circuits is connected to receive the system clock signal from a corresponding clock signal path that does not come from said interleave controller; wherein each dedicated read clock generating circuit of the plurality of dedicated read clock generating circuits is configured to supply the respective read clock signal over a corresponding wire to a corresponding memory macro of the plurality of memory macros; and wherein each dedicated read clock generating circuit of the plurality of dedicated read clock generating circuits is disposed on the chip in close proximity to the corresponding memory macro of the plurality of memory macros.