Patent ID: 6987477

Claim:
An apparatus including a pipelined analog-to-digital converter (ADC), comprising: a plurality of pipeline stages coupled in series and including a first pipeline stage, at least one intermediate pipeline stage and a last pipeline stage, each of which provides M bits of resolution for an N-bit digital output signal corresponding to an analog input signal, wherein said first pipeline stage is responsive to said analog input signal by providing a first analog residue signal and a first digital signal with M+1 bits corresponding to M+1 most significant bits (MSBs) of said N-bit digital output signal, each of said at least one intermediate pipeline stage is responsive to a prior analog residue signal from a directly preceding one of said plurality of pipeline stages by providing a subsequent analog residue signal and an intermediate digital signal with M+1 bits corresponding to M+1 less significant intermediate bits of said N-bit digital output signal, and said last pipeline stage is responsive to a last subsequent analog residue signal by providing a final analog residue signal and a last digital signal with M+1 bits corresponding to M+1 lesser significant intermediate bits of said N-bit digital output signal; and a final ADC coupled to said last pipeline stage and responsive to said final analog residue signal by providing a final digital signal with 2M+1 bits corresponding to 2M+1 least significant bits (LSBs) of said N-bit digital output signal.