Patent ID: 8458642

Claim:
A method of modeling contact resistance for a field effect transistor, said field effect transistor comprising: a semiconductor body comprising: multiple diffusion regions comprising: source regions; and drain regions; and multiple channel regions, each channel region being positioned between a source region and a drain region; a gate structure having multiple fingers, each finger traversing said semiconductor body adjacent to a corresponding channel region and between a source region and a drain region associated with said corresponding channel region; and multiple contacts to said multiple diffusion regions; and, said method comprising: analyzing a design of said field effect transistor to determine a number of said fingers, using a computer; and calculating, based on said number of said fingers, a first total contact resistance associated with said source regions and a second total contact resistance associated with said drain regions, using said computer, said calculating comprising using formulas which account for a first amount of current passing through all contacts to an inner diffusion region between two fingers of said gate structure being greater than a second amount of current passing through all contacts to an outer diffusion region adjacent to only one finger of said gate structure.