Patent ID: 7203121

Claim:
A semiconductor integrated circuit device comprising: a memory cell array for which a data write operation is to be performed by an external write enable signal; an address transition detecting circuit which detects transition of a column address signal, the column address signal being used to specify a column address of the memory cell array; a control circuit having a timeout circuit, the control circuit which generates an internal circuit control signal of desired length used to control column access to the memory cell array based on a result of detection by the address transition detecting circuit; and a column selection line whose selection time is controlled by the control circuit, wherein the column address signal used for selection of the column selection line is latched without clock-operating the external write enable signal in a period of time in which the column selection line is selected at a write operation time, and wherein a time for fetching data to be written at the write operation time is determined only by a transition time of the column address signal.