Patent ID: 6922354

Claim:
In a semiconductor memory device comprising a plurality of CMOS SRAM cells, being arranged on a semiconductor substrate in a matrix shape, each comprising a pair of access transistors, a pair of drive transistors, and a pair of load transistors, each region being a cell region with an elongated shape in a row direction, wherein three well regions are formed side by side in a row direction so that a second conductivity type well region may be disposed between two first conductivity type well regions on said semiconductor substrate, and wherein one of said access transistors and one of said drive transistors are formed in each of two said first conductivity type well regions within said cell region, and a pair of said load transistors is formed in said second conductivity type well region; and comprising a plurality of interconnection layers over transistors which configure said CMOS SRAM cell; the semiconductor memory device, comprising: a plurality of paired bit lines, formed of one of said plurality of interconnection layers, each being extended in a column direction to be connected to said CMOS SRAM cell in the same column, and arranged in parallel in a row direction; a plurality of high potential side power supply interconnections, formed of the same interconnection layer as that of said bit line, and each being arranged between said paired bit lines to be connected to said CMOS SRAM cell in the same column; a plurality of word lines, formed of said interconnection layer upper than that of said bit line by one layer, each being extended in a row direction to be connected to said CMOS SRAM cell in the same row, and arranged in parallel in a column direction; and a low potential side power supply interconnection, formed of said interconnection layer upper than that of said word line by one layer, and connected to said CMOS SRAM cell.