Patent ID: 7423926

Claim:
A semiconductor memory comprising: a plurality of memory cells for even addresses arranged in a memory array for even addresses and configured to store even addressed data, the even addressed data being associated with even row addresses; a plurality of write word lines for even addresses arranged parallel to a row direction of the memory array for even addresses and configured to select the plurality of memory cells for even addresses in the row direction of the memory array for even addresses to write the even addressed data; a plurality of write bit lines for even addresses arranged parallel to a column direction of the memory array for even addresses and configured to transfer the even addressed data to the plurality of memory cells for even addresses in the column direction of the memory array for even addresses; a plurality of memory cells for odd addresses arranged in a memory array for odd addresses and configured to store odd addressed data, the odd addressed data being associated with odd row addresses; a plurality of write word lines for odd addresses arranged parallel to a row direction of the memory array for odd addresses and configured to select the plurality of memory cells for odd addresses in the row direction of the memory array for odd addresses to write the odd addressed data; and a plurality of write bit lines for odd addresses arranged parallel to a column direction of the memory array for odd addresses and configured to transfer the odd addressed data to the plurality of memory cells for odd addresses in the column direction of the memory array for odd addresses.