Patent ID: 7989954

Claim:
An integrated circuit chip comprising: a silicon substrate; an I/O circuit in or over said silicon substrate, wherein said I/O circuit comprises a first NMOS transistor with a ratio of a physical channel width of said first NMOS transistor to a physical channel length of said first NMOS transistor ranging from 20 to 20,000; an internal circuit in or over said silicon substrate, wherein said internal circuit comprises a second NMOS transistor with a ratio of a physical channel width of said second NMOS transistor to a physical channel length of said second NMOS transistor ranging from 0.1 to 20; a dielectric structure over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric structure, wherein said first interconnecting structure is connected to a first node of said I/O circuit; a first metal interconnect over said silicon substrate, wherein said first metal interconnect is connected to said first node of said I/O circuit through said first interconnecting structure; a second interconnecting structure over said silicon substrate and in said dielectric structure, wherein said second interconnecting structure is connected to a first node of said internal circuit; a second metal interconnect over said silicon substrate, wherein said second metal interconnect is connected to said first node of said internal circuit through said second interconnecting structure; a passivation layer over said dielectric structure, said I/O circuit and said internal circuit, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening; and a third interconnecting structure over said passivation layer and on said first and second contact points, wherein said first node of said I/O circuit is connected to said first node of said internal circuit through, in sequence, said first interconnecting structure, said first metal interconnect, said third interconnecting structure, said second metal interconnect and said second interconnecting structure, wherein said third interconnecting structure comprises an adhesion layer, a seed layer on said adhesion layer, and an electroplated metal layer on said seed layer, wherein said electroplated metal layer has a thickness between 2 and 30 micrometers.