Patent ID: 6977539

Claim:
An integrated circuit device, comprising: an integrated circuit chip having a clock driver therein that supports generation of a plurality of output clock signals having different frequencies in a range between 1 and 1/N times a frequency of an internal clock signal and full-period programmable skew characteristics, where N is a positive integer greater than one; wherein the clock driver comprises an internal clock signal generator selected from the group consisting of a phase-locked loop (PLL) integrated circuit and a delay-locked loop (DLL) integrated circuit; wherein the clock driver is configured to support generation of a divide-by-N clock signal having a full-period programmable skew characteristics that is stepped in N×M time units having a duration equal to 1/M times a period of the internal clock signal, where M is a positive integer greater than eight; and wherein the clock driver comprises: a divide-by-N clock generator responsive to a first skew signal; and a synchronization unit electrically coupled to an output of said divide-by-N clock generator circuit and responsive to the first skew signal.