Patent ID: 7098472

Claim:
A memory cell comprising: a storage node; a transfer field effect transistor (FET), said transfer FET being configured to connect a data line to the storage node in response to at least one of a write signal and a read signal; and a first negative differential resistance (NDR) field effect transistor (FET), the first NDR FET comprising a first source coupled to the storage node, a first gate coupled to receive a first gate bias voltage, a first drain for receiving a first supply voltage, and a first body coupled to receive a first body bias voltage; and a second NDR FET, the second NDR FET comprising a second source coupled to receive a second supply voltage, a second gate coupled to receive a second gate bias voltage, a second drain coupled to the storage node, and a second body coupled to receive a second body bias voltage, wherein the first body bias voltage causes the first NDR FET to exhibit one of a zero threshold voltage and a negative threshold voltage.