Patent ID: 8832336

Claim:
A method for reducing system latency in a data interface between a physical medium attachment and a physical coding sublayer, wherein the data interface comprises a data transmitter and a data receiver, wherein the physical medium attachment is operable to deserialize incoming serial data from the physical coding sublayer, and the physical coding sublayer is operable to verify that the physical medium attachment correctly aligns the incoming data, the method comprising: (a) generating a bit clock signal in a global macro, (b) providing the bit clock signal to the data transmitter and the data receiver, (c) generating a byte clock signal in the global macro, where the byte clock signal is a divided version of the bit clock signal, (d) providing the byte clock signal to the physical coding sublayer, the data transmitter, and the data receiver, (e) transferring data from the data receiver to the physical coding sublayer in response to the byte clock signal, wherein the bit clock signal is not directly used to transfer data from the data receiver to the physical coding sublayer, (f) transferring data from the physical coding sublayer to the data transmitter in response to the byte clock signal, wherein the bit clock signal is not directly used to transfer data from the physical coding sublayer to the data transmitter, and (g) sequentially registering the incoming serial data as pairs of deserialized bits in a double buffer circuit by: writing bit pairs to an upper half of the double buffer circuit at a first clock speed while reading previously loaded bit pairs from a lower half of the double buffer circuit at a second clock speed that is less than and dependent upon the first clock speed, and writing bit pairs to the lower half of the double buffer circuit at the first clock speed while reading previously loaded bit pairs from the upper half of the double buffer circuit at the second clock speed.