Patent ID: 7761763

Claim:
A self-test method of a system-on-chip (SOC) with a built-in-self-test (BIST) circuit, the method comprising: inputting test pattern data to a first combinational circuit through a BIST logic circuit; storing test result data outputted from a second combinational circuit in storage cells within the BIST logic circuit; reading the test result data stored in the storage cells; and compressing and storing the read test result data; wherein each of the storage cells comprises: first storage cells and second storage cells; wherein the step of inputting test pattern data includes: writing control data with a first set value in a control register within the BIST logic circuit; writing the test pattern data in the first storage cells; writing the control data with a second set value in the control register; writing the test pattern data in the second storage cells; and writing the control data with a third set value in the control register when the test pattern data is written in the last second storage cell among the second storage cells.