Patent ID: 8402181

Claim:
An arbiter for a switch having a plurality of ingress ports and a plurality of egress ports comprising: a first scheduler coupled to receive egress port requests from each of the ingress ports, and in response, grant connections that extend completely between the ingress ports and the egress ports for a first set of clock ticks; a second scheduler coupled to receive egress port requests from each of the ingress ports, and in response, grant connections that extend completely between the ingress ports and the egress ports for a second set of clock ticks, wherein the first set of clock ticks alternate with the second set of clock ticks; and a first set of interconnects that transmit a first set of signals identifying granted connections between the ingress ports and the egress ports from the first scheduler to the second scheduler; and a second set of interconnects that transmit a second set of signals identifying granted connections between the ingress ports and the egress ports from the second scheduler to the first scheduler.