Patent ID: 7989869

Claim:
A nonvolatile memory device comprising: a plurality of parallel active regions defined by a device isolation layer formed on a semiconductor substrate, each of the plurality of parallel active regions extending in a first direction; and a plurality of parallel word lines crossing over the plurality of active regions, each of the plurality of parallel word lines extending in a second direction intersecting the first direction, wherein the plurality of parallel word lines are disposed between a string selection line and a ground selection line and are substantially without non-straight portions in a plan view, wherein the plurality of parallel active regions are periodically arrayed in the second direction to have a first pitch which is a sum of a width of one of the plurality of parallel active regions and a distance between two immediately adjacent ones of the plurality parallel active regions, wherein the width of each of the plurality of parallel active regions is consistent among the plurality of parallel active regions and the distance between immediately adjacent ones of the plurality of parallel active regions is consistent among the plurality of parallel active regions, wherein the plurality of parallel word lines are periodically arrayed in the first direction to have a second pitch which is a sum of a width of one of the plurality of parallel word lines and a distance between two immediately adjacent ones of the plurality of parallel word lines wherein the width of each of the plurality of parallel word lines is consistent among the plurality of parallel word lines and the distance between immediately adjacent ones of the plurality of parallel word lines is consistent among the plurality of parallel word lines, and wherein the second pitch is greater than the first pitch.