Patent ID: 6993551

Claim:
A method for reducing computational steps in a digital processor having multiplication operations that produce a plurality of multiplication products, wherein the multiplication operations are used to carry out a desired signal processing function having predefined characteristics, said method comprising: specifying at least one multiplication operation, wherein the desired signal processing function has an associated set of initial coefficients for implementing the function; determining an initial total number of non zero bits of tile associated set of Initial coefficients; modifying the set of initial coefficients to generate a plurality of sets of modified coefficients by scaling all the coefficients in the set of initial coefficients by a common scale factor, wherein the common scale factor has a value varying between about 0.5 and about 2; choosing a set of modified coefficients such that the resulting number of nonzero bits is reduced and that the predefined characteristics of the function are achieved; and implementing the function in the digital processor using the set of modified coefficients.