Patent ID: 7253105

Claim:
A method of fabricating an interconnect structure comprising: providing a structure comprising a porous ultra low k (ULK) dielectric having a dielectric constant of less than 3.0 on a substrate, said porous ULK dielectric having at least one opening located therein; filling said at least one opening with at least a conductive material; planarizing at least said conductive material utilizing a CMP slurry to provide a planarized structure having an upper surface of said conductive material that is substantially coplanar with an upper surface of said ULK dielectric, said ULK dielectric is exposed to said CMP slurry and said planarizing provides a planarized ULK dielectric with patterned conductors having a leakage current density that is lower than that measured without an UV radiation exposure step, and a breakdown field that is higher than that measured without an UV radiation exposure step; exposing said planarized structure to UV radiation at a temperature from about 200° to about 450° C.; subjecting said planarized structure to a plasma preclean process; and forming a capping layer on at least said conductive material.