Patent ID: 8296598

Claim:
A double data rate output circuit comprising: an edge detector for receiving a first clock signal and providing a second clock signal having twice a frequency of the first clock signal to an edge detector output; a multiplexer for receiving rising edge data having a data rate corresponding to the frequency of the first clock signal at a first input, receiving falling edge data having a data rate corresponding to the frequency of the first clock signal at a second input, and, based on a selection signal received at a selection input, alternately providing the data received at the first input and the second input to a multiplexer output; an edge triggered flip-flop having a data input coupled to the multiplexer output, a clock input coupled to the edge detector output, and a flip-flop output providing data received at the data input and latched on edges of the clock received at the clock input; and a data output buffer having an input coupled to the flip-flop output and an output coupled to a data output terminal, wherein the double data rate output circuit provides rising edge data and falling edge data on the data output terminal at a data rate corresponding to twice the frequency of the first clock signal.