Patent ID: 8585917

Claim:
A method of manufacturing a dynamic random access memory (DRAM), comprising: forming a lower structure, the lower structure including a plurality of transistors, a plurality of interconnections each connected to a respective transistor, an insulating layer disposed between the plurality of interconnections; forming a first sacrificial layer on the lower structure; patterning the first sacrificial layer to form a plurality of openings to expose respective ones of the plurality of interconnections; forming a lower electrode layer on sidewalls of the openings; forming a second sacrificial layer on the lower electrode layer, the second sacrificial layer filling the openings; forming a plurality of lower capacitor electrodes including etching the second sacrificial layer and the lower electrode layer to expose the first sacrificial layer; wet etching to remove the first and second sacrificial layers; cleaning the plurality of lower capacitor electrodes; rinsing the plurality of lower capacitor electrodes; and drying the plurality of lower capacitor electrodes using supercritical carbon dioxide.