Patent ID: 7694249

Claim:
An Intellectual Property (IP) generator, comprising: a partitioning module to generate IP sub components of an electronic system design as an abstract executable representation; a power module to aggregate power consumption estimates of all the IP sub components in the electronic design system prior to performing logic synthesis of the electronic system design, wherein the estimated aggregated power consumption of all the IP sub components are presented to the user during an architectural exploration stage of the design process via the user interface; a timing module to estimate a time frame to travel through each IP sub-component in the electronic design system prior to performing logic synthesis of the electronic system design and aggregate each IP sub-component time estimate to generate an overall timing estimate of the IP design, wherein the estimated time frames of a synthesizable Register Transfer Level design are presented to a user via a user interface during an architectural exploration stage of a design process; and an output module to supply the Register Transfer Level design of the electronic system design for logic synthesis, wherein the user interface solicits an amount and type of circuit level components that make up each IP sub component and the timing module generates parameters that estimate an amount and type of circuit level components that make up each IP sub component based on the user supplied configuration parameters including the amount and type of circuit level components that make up each IP sub component, and the overall timing estimate accounts for the amount and type of circuit level components that make up each IP sub component, the time frame to travel through each IP sub-component individually, and then each IP sub-component time estimate is aggregated to generate the overall timing estimate.