Patent ID: 7118963

Claim:
A method of manufacturing a semiconductor memory intergrated circuit comprising: forming a plurality of gate insulating films each having a thickness required for each of a cell array region and a peripheral circuit region on a semiconductor substrate; forming a first-layer gate electrode material film not doped with impurities on said gate insulating films; etching said semiconductor substrate covered with said first-layer gate electrode material film to make grooves for device isolation, and burying the device isolation grooves with a device isolation insulatin film; forming a second-layer gate electrode material film not doped with impurities on said device isolation insulating film and said first-layer gate electrode material film, said first-layer gate electrode material film being maintained in self alignment with regions surrounded by said device isolation insulating film and; selectively introducing impurities into said first-layer and second-layer gate electrode material films in said cell array region; selectively etching said second-layer gate electrode material film to isolate portions of said second-layer gate electrode material film on said device isolation insulating film in said cell array region; forming an additional gate insulating film on said second-layer gate electrode film to serve as an insulation film between floating gates and control gates of memory cells, said additional gate insulating film being formed over said cell array region and said peripheral circuit region; removing said additional gate insulating film from said peripheral circuit region; forming a third-layer gate electrode material film not doped with impurities on said additional gate insulating film, said third-layer gate electrode material film being formed over said cell array region and said peripheral circuit region; processing the first-layer, second-layer and third-layer gate electrode material films in said cell array region and said peripheral circuit region into a desired pattern to form control gates and floating gates in said cell array region and to form gate electrodes in said peripheral circuit region; and forming source and drain diffusion layers and lowering the resistance of said gate electrode by introducing impurities into said cell array region and said peripheral circuit region under a plurality of different conditions.