Patent ID: 7697365

Claim:
A decoder for flash memory comprising: a voltage supply terminal for coupling to a first voltage source; a plurality of MOS type transistors arranged in a plurality of decoding circuits to generate a plurality of enable signals in response to a plurality of control signals, each of the MOS type transistors including a substrate voltage terminal for selective coupling to a second voltage source, the second voltage source having a voltage different than the first voltage source and having a voltage different than ground, each decoding circuit generating a corresponding one of the plurality of enable signals, the substrate voltage terminals of a selected decoder being coupled to the second power source, the substrate voltage terminals of unselected decoders being coupled to the first power source; the plurality of decoding circuits include a virtual ground voltage terminal, a plurality of bulk voltage generators coupled to the substrate voltage terminals of a corresponding one of the plurality of decoding circuits for providing a first voltage in response to an enable signal corresponding to the plurality of control signals and providing a second voltage in response to an disable signal corresponding to the plurality of control signals; and a selection circuit for selectively coupling the virtual ground voltage terminal of a selected decoding circuit to a voltage source providing a first voltage less than a ground voltage and coupling the virtual ground voltage terminal of unselected decoding circuits to a voltage source providing a second voltage less than a ground voltage.