Patent ID: 8598922

Claim:
A semiconductor device, comprising: a first internal terminal; a first transistor comprising a first conductivity type, the first transistor coupled between a first reference potential and the first internal terminal, the first transistor comprising a first control terminal; a second transistor comprising a second conductivity type, the second transistor coupled between a second reference potential and the first internal terminal, the second transistor comprising a second control terminal; an oscillator comprising an output terminal to output a clock signal; and a comparator coupled to the first internal terminal, and that compares a potential of the first internal terminal when the first internal terminal is coupled to the first reference potential with a potential of the first internal terminal when the first internal terminal is coupled to the second reference potential; an external terminal being connectable to the first internal terminal; and a second internal terminal being coupled to the external terminal, and that receives an input signal through the external terminal, wherein each of the first control terminal and the second control terminal is coupled to the output terminal to commonly receive the clock signal, wherein the first transistor and the second transistor exclusively operate according to the clock signal, wherein the comparator comprises a first comparator, wherein the semiconductor device further comprises: a third internal terminal; a third transistor of the first conductivity type coupled between the first reference potential and the third internal terminal, the third transistor including a third control terminal; a fourth transistor of the second conductivity type coupled between the second reference potential and the third internal terminal, the fourth transistor comprising a fourth control terminal; a second comparator coupled to the third internal terminal, and that compares a potential of the third internal terminal when the third internal terminal is coupled to the first reference potential with a potential of the third internal terminal when the third internal terminal is coupled to the second reference potential; and an internal circuit, wherein each of the third control terminal and the fourth control terminal is coupled to the output terminal to commonly receive the clock signal, wherein the third and fourth transistors exclusively operate according to the clock signal, and wherein the internal circuit determines an operation mode based on an output of the first comparator and an output of the second comparator.