Patent ID: 7415590

Claim:
An integrated circuit to which inputs and outputs (I/Os) are separately provided and to which a write address and a read address are simultaneously input during one period of a clock signal, the integrated circuit comprising: a plurality of memory blocks, each of the memory blocks comprising a plurality of sub-memory blocks; a plurality of data memory blocks corresponding to the memory blocks, wherein each of the data memory blocks has the same size as a sub-memory block; and a tag memory controlling unit, which writes data to the memory blocks or reads data from the memory blocks in response to the write address or the read address, wherein when the write address and the read address are the same as a data memory address, the read operation is performed in the data memory block and the write operation is performed in the sub-memory block, and wherein when the write address and the read address are both not the same as the data memory address, the operation corresponding to the address that is the same as the data memory address is performed in the data memory block and the operation corresponding to the address that is not the same as the data memory address is performed in the sub-memory block.