Patent ID: 8582708

Claim:
A clock and data recovery circuit, comprising: a multiphase clock generator circuit configured to generate a multiphase clock having a plurality of clocks; a sampling circuit configured to sample a received data signal transferring serial data in synchronism with each of the plurality of clocks, and to generate a plurality of data signals respectively representing values sampled in synchronism with the respective plurality of clocks; a data recovery unit configured to generate a selection signal indicating a data signal having an appropriate phase among the plurality of data signals; and a storage unit configured to store the selection signal, wherein the data recovery unit generates the selection signal during at least a part of an initialization period for receiving a data signal and selects one of the plurality of data signals based on the selection signal read from the storage unit, selects from the plurality of clocks a clock corresponding to the selected data signal, and outputs the selected data signal and the selected clock, and the data recovery unit reads the selection signal stored in the storage unit as an initial value, selects one of the plurality of data signals based on the initial value and starts the clock and data recovery operation by reading the initial value, and thereafter the data recovery unit performs data communication.