Patent ID: 7919816

Claim:
A gate controlled fin resistance element for use as ESD protection element in an electrical circuit, comprising: a fin structure having a first connection region, a second connection region and a channel region formed between the first connection region and the second connection region; a gate region formed at least over a part of the surface of the channel region, the gate region being electrically coupled to the second connection region, so that the gate controlled fin resistance element has a low electrical resistance during a first operating state of the electrical circuit, and that the gate controlled fin resistance element has a higher electrical resistance during a second operating state of the electrical circuit, said second operating state being characterized by the occurrence of an ESD event, the connection regions being n doped; the channel region having a plurality of first partial regions and a plurality of second partial regions, which first partial regions and second partial regions form an alternate sequence; the first partial regions having an intrinsic conductivity or being p doped; the second partial regions being n doped; the number of first partial regions being greater than the number of second partial regions.