Patent ID: 8013375

Claim:
A semiconductor memory device comprising: a semiconductor substrate including a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis, wherein the length is greater than the width, wherein the plurality of active regions are provided in a plurality of columns in the direction of the second axis; a field isolation layer on the semiconductor substrate surrounding each of the active regions so that field isolation layer separates and provides electrical isolation between each of the active regions in a same column and so that the field isolation layer separates and provides electrical isolation between active regions in adjacent columns; a plurality of wordline pairs on the substrate, wherein each wordline pair crosses active regions of a respective column of active regions to define a drain portion of each of the active regions between wordlines of the respective wordline pair, and to define source portions at opposite ends of each of the active regions; a plurality of bitlines on the substrate crossing the plurality of wordline pairs, wherein each bitline is electrically coupled to a drain portion of a respective active region of each column, and wherein each bitline crosses drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns; and a plurality of memory storage elements, wherein each memory storage element is electrically coupled with a respective one of the source portions so each end of each of the active regions is electrically coupled to a different one of the memory storage elements.