Patent ID: 7844931

Claim:
A method for optimizing the signal time behavior of an electronic circuit design comprising at least one fixed circuit element, wherein the at least one fixed circuit element is characterized by at least one of the following conditions: it cannot be cloned, it cannot be removed, it cannot be modified, said first tree being divided into a second tree and a third tree, wherein said second tree includes said at least one fixed circuit element, wherein said third tree includes no fixed circuit elements, and wherein said second tree and said third tree are coupled to each other through said at least one fixed circuit element, the method comprising: generating one or more first alternative versions of said third tree, wherein said first alternative versions are Boolean equivalent to said third tree, and wherein a first target arrival time window is satisfied by said first alternative versions of said third tree; generating one or more second alternative versions of said second tree, wherein said second alternative versions of said second tree are Boolean equivalent to said second tree, and wherein the latencies for the fixed circuit elements connecting said second tree and said third tree are taken into account for the generation, and wherein a second target arrival time window is satisfied by said second alternative versions of said second tree; selecting the second alternative version of said one or more second alternative versions having the minimum signal arrival time and selecting the first alternative version of said one or more first alternative versions having the minimum signal arrival time; replacing said second clock tree with said selected second alternative version and replacing said third clock tree with said selected first alternative version; and storing said modified circuit design in a computer.