Patent ID: 7875970

Claim:
An integrated circuit package comprising: a) a leadframe having a first surface and an opposing second surface; b) a semiconductor die having a first surface and an opposing second surface, said first surface of said semiconductor die mounted on said first surface of said leadframe; c) an encapsulation compound having a first side and an opposing second side, said first surface of said leadframe and said second surface of said semiconductor die embedded in said first side of said encapsulation compound; d) a heat sink disposed in proximity to said semiconductor die, said heat sink comprising: i) a base sheet having a first surface facing said semiconductor die and an opposing second surface; ii) at least one castellation extending from said first surface of said base sheet, said castellation having a first surface facing said semiconductor die and at least one second surface adjacent to said first surface of said castellation and said first surface of said base sheet; wherein said first surface of said base sheet, said first surface of said castellation and said at least one second surface of said castellation are embedded in said second side of said encapsulation compound, such that a layer of encapsulation compound separates said heat sink from said semiconductor die and said leadframe, said second surface of said leadframe exposed to the environment on one side and said second surface of said base sheet exposed to the environment on an opposing side; and wherein said at least one castellation further comprises an undercut at said at least one second surface of said castellation, such that a cross sectional area of said first surface of said castellation is larger than a cross sectional area along said second surface of said castellation.