Patent ID: 7821806

Claim:
A memory circuit, comprising: a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node; a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch; and a control circuit configured to control the gate node and the second source/drain node of the MIS transistor in a first operation such that a lingering change is created in the transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes: a highly-doped substrate layer; a lightly-doped substrate layer disposed on the highly-doped substrate layer; diffusion regions formed in the lightly-doped substrate layer; a gate electrode; sidewalls; and an insulating film.