Patent ID: 8683149

Claim:
A memory controller, comprising: signal connectors to electrically couple to a communication path that includes multiple links, the communication path for electrically coupling to a memory device that can be a first memory device or a second memory device; and an interface circuit electrically coupled to the signal connectors and configurable to operate in either a first operating mode or a second operating mode depending on a type of the memory device coupled to the communication path, wherein, in the first operating mode, when the memory device is the first memory device, the interface circuit is to communicate with the first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path; wherein, in the second operating mode, when the memory device is the second memory device instead of the first memory device, the interface circuit is to communicate with the second memory device via the communication path using time multiplexing, in which at least some of the multiple links in the communication path time interleave command/address information and data, the second memory device being of a different type from the first memory device; and control logic to schedule use of at least some of the multiple links based on configuration information specifying a given operation mode.