Patent ID: 7902885

Claim:
An output buffer system comprising: a compensated output driver utilizing a separate compensation codes for at least one PMOS transistors and at least one NMOS transistors, said compensated output driver coupled to a first driving node, a second driving node and an output node, the compensated output driver having a pull-up driver section for driving said output node in response to a signal at the first driving node and a pull down driver section for driving said output node in response to a signal at the second driving node; a compensated pull-up slew rate controller utilizing a separate compensation codes for the PMOS transistors and the NMOS transistors, said compensated pull-up slew rate controller connected between an input node and the compensated output driver through the first driving node for controlling a pull-up slew rate of the compensated output driver during a transition of an output from 0 to 1; and a compensated pull-down slew rate controller utilizing a separate compensation codes for the PMOS transistors and the NMOS transistors, said compensated pull-down slew rate controller connected between the input node and the compensated output driver through the second driving node for controlling a pull-down slew rate of the compensated output driver during a transition of the output from 1 to 0 to minimize the variations in the current slew rate of the output buffer over process, voltage and temperature condition for improving the slew rate control.