Patent ID: 7969402

Claim:
A gate driving circuit for outputting driving signals to a plurality of gate lines, the circuit comprising: p shift registers for driving gate lines divided into p groups, respectively, wherein the plurality of gate lines comprises first to p-th gate lines sequentially deposited and corresponding to first to p-th shift registers, respectively, wherein each of the p shift registers includes a plurality of stages dependently connected to one another, and each of p start signals is sequentially input to an input terminal of a first stage of each of the first to p-th shift registers, respectively, and an output signal from a selected stage is connected to an input terminal of the next stage of each of the p shift registers, whereby the first to p-th gate lines are sequentially driven by means of the output signals of first to p-th stages corresponding to the first to p-th shift registers, respectively, wherein each of the p start signals of a high state are partially overlapped, wherein the p start signals used in the p shift registers are shifted from one another by 1/p, and wherein p is a natural number of four, and the gate lines are divided into four groups in an order of 4n-3, 4n-2, 4n-1 and 4n, wherein n is a natural number of one or more.