Patent ID: 7262075

Claim:
A method of fabricating nano interconnections to connect an integrated circuit to a substrate, the method comprising: providing a polymer material having a stiffness less than approximately 1 GPa; patterning the polymer material to provide a plurality of polymer columns, each defining an outer surface, the polymer material comprising at least one of polymide or polynorbornene; adjusting a portion of the outer surfaces of the polymer columns by at least one of physical or chemical roughening so that the outer surfaces comprise a plurality of anchoring elements formed on the outer surfaces; cleaning the polymer columns by exposing them to ultrasonic energy; coating the polymer columns with metal such that the metal attaches to at least a portion of the anchoring elements formed on the outer surfaces so that a plurality of nano interconnections are formed; and disposing the nano interconnections between an integrated circuit and a substrate so that the nano interconnections connect the integrated circuit and the substrate, wherein cleaning the polymer columns occurs prior to coating the polymer columns.