Patent ID: 8332715

Claim:
A test pattern generating method of generating a test pattern with respect to a semiconductor circuit having first and second common circuits and a non-common circuit other than the first and second common circuits, each of the first and second common circuits having a scan chain for checking an operation of the circuit by applying a test pattern from the outside of the circuit, the test pattern generating method characterized by comprising steps of: reading, by a circuit information reading unit, circuit information of the semiconductor circuit; creating, by a scan chain set creating unit, a set of scan chains and a set of assumed faults for each of the first and second common circuits, wherein the assumed fault is a fault fixed to a terminal of a logic element constituting the common circuit; determining, by a test target circuit determining unit, any of the first and second common circuits as the common circuit of a first test target based on the reading; generating, by a test pattern generating unit, a test pattern for the determined common circuit of the first test target by using the created set of the scan chains and the set of the assumed faults; compressing, by a test pattern compressing unit, the generated test pattern; detecting, by a circuit fault detecting unit, a circuit fault that the common circuit of the first test target has by using the compressed test pattern; and determining, by a common circuit determining unit, the common circuit, which is different from the common circuit of the first test target among the first and second common circuits based on the detecting, as the common circuit of a second test target.