Patent ID: 8857022

Claim:
A method comprising: forming a plurality of plates and a plurality of dielectric layers interleaved with one another, wherein the forming the plurality of plates and the plurality of dielectric layers comprises at least: forming a first metal plate; forming a high-k dielectric layer on the first metal plate; forming a second metal plate on the high-k dielectric layer; forming a low-k dielectric layer on the second metal plate; and forming an upper metal plate on the low-k dielectric layer; patterning the upper metal plate by removing portions thereof; patterning portions of the low-k dielectric layer and the second metal plate; patterning portions of the high-k dielectric layer and first metal plate; etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate, wherein the protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor, wherein: the first metal plate forms a bottom metal plate of the first MIM capacitor and the second MIM capacitor, simultaneously; the second metal plate forms a floating middle metal plate of the first MIM capacitor and the top plate of the second MIM capacitor, simultaneously; and the third metal plate is the uppermost plate that forms the top plate of the first MIM capacitor.