Patent ID: 8392861

Claim:
A design method for automatically placing cells of a semiconductor integrated circuit device by using a computer system, comprising: during a period of a cell layout processing by a layout program on the computer system, a library for estimating timing and area is used to estimate a timing constraint and an area increase after timing optimization and to place cells so that wiring congestion does not occur while meeting the timing constraint, wherein the library for estimating timing and area includes a library for estimating long wires, a library for estimating multi fan-outs, and a library for estimating multi-stage logic, resulting in a path, the timing of which before layout is different, wherein the library for estimating long wires includes a library of estimated delay values and estimated cell areas in accordance with distances by the cell drive capability change or buffering by changing a cell wiring distance, wherein the library of estimated delay values and estimated cell areas includes delay values and cell areas estimated on an assumption that a point where an inverse of speed is minimal for the wiring distance is buffered, and wherein the point where the inverse of speed is minimal for the wiring distance is found for each of two or more different buffer drive capabilities and the library for estimating long wires estimates the delay value and the area, respectively, based on the point where the inverse of speed found for each of the two or more different buffer drive capabilities is minimal.