Patent ID: 8131980

Claim:
A non-transitory machine readable storage medium having embodied therein a design structure for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a processor load queue for issuing load requests; a delay queue, which comprises a delay path including (a) a plurality of initial delay stages including a first stage and associated first staging multiplexer (MUX), (b) a final stage with an associated final staging MUX; a feedback path for returning retried operations as an input to the first staging MUX; at least one bypass path extending from before one of the plurality of initial delay stages to an input of the final staging MUX; a memory subsystem and memory subsystem controller for controlling access to the memory subsystem; a livelock detection mechanism that monitors for the occurrence of a livelock condition within the system, wherein said livelock detection mechanism comprises logic for: sampling instructions that are sent to the memory subsystem controller; and comparing the number of flushes detected against a pre-established threshold value; and a delay queue controller having livelock resolution logic that is activated by the livelock detection mechanism, wherein said delay queue controller responds to the detection of the livelock condition by dynamically changing a selection at said final staging MUX to enable rescheduling of a retried operation ahead of a newer operation at the memory subsystem controller, wherein said livelock resolution logic is automatically activated when the livelock detection mechanism detects a series of flushes corresponding to a load operation that targets a particular cache line but does not complete, and wherein said livelock resolution logic comprises logic for: in response to the number of flushes being less than the pre-established threshold value, said livelock resolution logic activates a first response to resolve the livelock condition, said first response including a disabling of a delay bypass for new operations received at the delay queue such that all new operations are made to pass through each stage of the delay queue before being presented for selection at the final staging MUX; and in response to the number of flushes reaching the pre-established threshold value, said livelock resolution logic activates a second response to resolve the livelock condition, said second response including granularly selecting individual instructions from selected ones of the initial delay stages and the feedback path to forward for selection at the final stage MUX, such that a single step instruction processing is enabled; wherein, when the livelock condition is resolved, said delay queue controller triggers a selection of operations on the bypass path at the final staging MUX.