Patent ID: 7016928

Claim:
A floating point operand testing circuit for identifying a status of a floating point operand, comprising: an analysis circuit configured to determine the status of the floating point operand based upon data within the floating point operand; and a result generator circuit coupled to the analysis circuit and being responsive to at least one control signal, the result generator being configured to assert a result signal if the floating point analysis circuit indicates the floating point status is of a predetermined format specified by the at least one control signal, wherein the data within the floating point operand encodes the status in the predetermined format, the predetermined format being from a group comprising not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, exact, and inexact; and the predetermined format for the NaN comprises a plurality of bits indicative of a predetermined type of operand condition resulting in the NaN status.