Patent ID: 8129849

Claim:
A method of making a semiconductor package comprising: forming solder masks on a substrate which has a plurality of conductive patterns formed on upper and lower surfaces of the substrate, in such a manner that the solder masks are formed on the conductive patterns except for a region of the conductive patterns in which bond fingers and ball lands are formed; attaching a semiconductor die to the upper portion of the substrate using adhesive; bonding the semiconductor die to the conductive patterns electrically by means of conductive wires; attaching an adhering portion, made of thermosetting resin having fluidity in a predetermined temperature range, to a supporting portion for supporting the adhering portion, to form an encapsulant, the supporting portion having: a lower surface with a total area identical with a total area of an upper surface of the adhering portion; an upper surface with a total area identical with the total area of the upper surface of the adhering portion; and sides directly extending between the upper surface of the supporting portion and the lower surface of the supporting portion; performing a first heating process for heating the adhering portion in the fluidity state; pressing the encapsulant vertically downwards so that the adhering portion covers the semiconductor die and the conductive wires placed on the upper surface of the substrate, the supporting portion having enough hardness to maintain flatness of the encapsulant; performing a second heating process for heating the adhering portion at a predetermined temperature so as to cure the adhering portion after the pressing; and fusion-welding solder balls to the ball lands; wherein the supporting portion is selected from the group consisting of polyimide and epoxy.