Patent ID: 8143094

Claim:
A manufacturing method of a silicon carbide semiconductor device comprising: a step of forming inside a first conductive-type silicon carbide layer second conductive-type well regions by ion-implanting a first impurity that is non-diffusible by activation annealing but forms a second conductive-type region in the silicon carbide layer; a step of forming in portions sandwiched between a surface of the silicon carbide layer and their respective well regions first conductive-type source regions by ion-implanting a second impurity that is non-diffusible by the activation annealing but forms a first conductive-type region in the silicon carbide layer, and a third impurity that is diffusible by the activation annealing and forms a second conductive-type region in the silicon carbide layer; a step of forming, in portions sandwiched between the surface of the silicon carbide layer and their respective well regions, and in the silicon carbide layer on inner outsides of the source regions, second conductive-type channel regions by diffusing by the activation annealing the third impurity having been included in the source regions; and a step of forming over a surface of the silicon carbide layer gate electrodes, intervening between the surface and the electrodes a gate insulation film, so as to cover the channel regions, a part of a surface-exposed portion of the silicon carbide layer in inner outsides of the channel regions, and a part of the source regions; and the well regions, the channel regions, and the gate electrodes being formed so that, given that extending lengths, with respect to the inner sides of the source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch<Lg<Lwell is satisfied.