Patent ID: 8723267

Claim:
An integrated circuit having an active semi-conductive layer, separated from a semi-conductive substrate layer by a buried layer of insulator material, including PMOS and NMOS transistors, said integrated circuit comprising: first and second transistors that are both PMOS or both NMOS; and first and second ground planes respectively positioned plumb with the first and second transistors between the buried layer of insulator material and the silicon substrate layer, wherein the first transistor has a type of doping of its ground plane opposite to that of its source, and has a first threshold voltage; wherein the second transistor has a type of doping of its ground plane identical to that of its source, and has a second threshold voltage; wherein the first threshold voltage is a function of a difference in potential applied between the source and the ground plane of the first transistor; wherein the second threshold voltage is a function of a difference in potential applied between the source and the ground plane of the second transistor; wherein the first and second threshold voltages are capable of varying respectively in first and second ranges of voltages should the difference in potential between the ground plane and the source of the first or second transistor vary between a zero value and a value equal to a power supply voltage of the circuit; and wherein the thickness of the buried layer of insulator material is fine enough for the maximum value of the first range to be at least 10% greater than the minimum value of the first range, and the minimum value of the second range to be at least 10% less than the maximum value of the second range.