Patent ID: 7531903

Claim:
An interconnection structure, used in a pad region of a substrate, wherein a semiconductor circuit and a pad corresponding to the pad region are disposed on the pad region of the substrate; the interconnection structure comprising: a patterned conductive layer disposed below the pad, and the patterned conductive layer comprising: an auxiliary layer having a plurality of gaps; and a plurality of first wire lines, disposed between the gaps of the auxiliary layer, passing through the gaps and exiting from the pad region; a first dielectric layer, disposed between the patterned conductive layer and the pad, covering the patterned conductive layer; a plurality of via plugs, disposed in the first dielectric layer, for connecting the auxiliary layer and the pad; a second dielectric layer, disposed between the substrate and the patterned conductive layer, covering the semiconductor circuit; and a plurality of contact plugs, disposed in the second dielectric layer, for electrically coupling the semiconductor circuit and the first wire lines.