Patent ID: 7269742

Claim:
A microprocessor configuration, comprising: a central processing unit; a functional unit; a memory unit; said central processing unit, said memory unit, and said functional unit each having a first encryption unit with: a first means for providing an alterable key being the same in said first encryption unit for each of said central processing unit, said memory unit and said functional unit; and a first combinational logic element; said memory unit having a second encryption unit with: a second means for providing a key; and a second combinational logic element; a bus receiving alterable key encrypted data from said central processing unit, said memory unit, and said functional unit; said first encryption unit of said central processing unit directly connecting said central processing unit to said bus said first encryption unit of said functional unit directly connecting said functional unit to said bus; said first encryption unit of said memory unit directly connecting said memory unit to said bus; said bus connecting said central processing unit, said functional unit, and said memory unit to one another for interchanging the alterable key encrypted data therebetween, the alterable key encrypted data transmitted by said bus and sent to said memory unit being decrypted using the alterable key and encrypted using the key, resulting in key encrypted data, and the key encrypted data transmitted from said memory unit and sent to said bus being decrypted using the key and encrypted using the alterable key resulting in the alterable key encrypted data; and said second combinational logic element connected between said second means and said first combinational logic element of said first encryption unit of said memory unit.