Patent ID: 8111796

Claim:
A clock synchronization device for phase aligning timing signals for a computational system to one of a plurality of reference clock signals, comprising: a clock selector for selecting between at least a first of the plurality of reference clock signals and an alternative of the plurality of reference clock signals for phase aligning the timing signals therewith; a phase locked loop for receiving the first reference clock signals, and the alternative reference clock signals; wherein the phase locked loop includes: (a) one or more phase error registers, wherein: (i) when the first reference clock signals are selected for phase aligning the timing signals, one of the one or more phase error registers repeatedly receives and stores data indicative of phase errors between the timing signals, and the first reference clock signals, and (ii) when the alternative reference clock signals are selected for phase aligning the timing signals, one of the one or more phase error registers repeatedly receives and stores data indicative of phase errors between the timing signals, and the alternative reference clock signals; (b) a first phase offset register corresponding to the first reference clock signals, wherein the first phase offset register repeatedly receives and stores data indicative of a phase error between the timing signals and the first reference clock signals, when the first reference clock signals are not selected by the clock selector for phase aligning the timing signals; (c) a second phase offset register corresponding to the alternative reference clock signals, wherein the second phase offset register repeatedly receives and stores data indicative of a phase error between the timing signals and the alternative reference clock signals, when the alternative reference clock signals are not selected by the clock selector for phase aligning the timing signals; wherein when the clock selector signals a switch from one of the first and alternative reference clock signals to the other of the first and alternative reference clock signals, the data in the one of the first and second phase offset registers corresponding to the other reference clock signals is: (d) combined with one of the phase error registers having data indicative of phase errors between the timing signals and the other reference clock signals for obtaining a phase error for correction, and (e) modified so that a subsequent combining with the one of the phase error registers having data indicative of phase errors between the timing signals and the other reference clock signals brings the timing signals into closer phase alignment with the other reference clock signals.