Patent ID: 7129543

Claim:
A method of designing a semiconductor device including a MOS transistor formed on an SOI substrate including a supporting substrate, a buried oxide film and an SOI layer, said MOS transistor being operated based on a predetermined clock, said MOS transistor comprising: a first semiconductor region of a first conductivity type and selectively formed in said SOI layer; a second semiconductor region of said first conductivity type and selectively formed in said SOI layer independently of said first semiconductor region; a body portion of a second conductivity type and including a body region, said body region being a region of said SOI layer which lies between said first and second semiconductor regions; a gate electrode formed on a gate oxide film formed on said body region; and at least one body contact electrically connected to said body portion and receiving a fixed potential, said method comprising the steps of: (a) providing an operating frequency of said predetermined clock; and (b) determining a layout pattern of said MOS transistor based on the operating frequency of said predetermined clock, wherein the layout pattern of said MOS transistor is determined in said step (b) so as to satisfy the conditional expression R·C·< 1 where C=the gate capacitance (F) of said MOS transistor, R=the resistance of a fixed potential transmission path extending from said at least one body contact to said body region, f=the operating frequency of said predetermined clock, and f≧500 MHz.