Patent ID: 7800159

Claim:
An array of contactless non-volatile memory cells comprising: a substantially single crystalline semiconductor substrate of a first conductivity type, having a planar surface; a plurality of non-volatile memory units arranged in a plurality of rows and columns, each memory unit comprising; a first region of a second conductivity type in said substrate along said planar surface; a second region of the second conductivity type in said substrate along said planar surface, spaced apart from the first region; a channel region between the first region and the second region, said channel region characterized by three portions: a first portion, a second portion and a third portion, with the second portion between the first portion and the third portion, and the first portion adjacent to the first region, and the third portion adjacent to the second region; a first floating gate over the first portion, and insulated therefrom; a first independently controllable control gate over the first floating gate and capacitively coupled thereto; a first independently controllable erase gate over the first region and insulated therefrom; an independently controllable word line over the second portion and insulated therefrom; a second independently controllable erase gate over the second region and insulated therefrom; a second floating gate over the third portion and insulated therefrom; and a second independently controllable control gate over the second floating gate and capacitively coupled thereto; wherein units in the same row share the word line in common; wherein units in the same column share the first region in common to one side, with said first region extended in said substrate from one row to another, the first erase gate in common, the second region in common to the other side, with said second region extended in said substrate from one row to another, and the second erase gate in common; wherein units in the same column share the first control gate in common and the second control gate in common; And wherein electrical contacts to said array are made only along the extremities of said array to said first region and said second region.