Patent ID: 7344931

Claim:
A method of manufacturing a semiconductor device including a semiconductor layer having a heavily doped source region, a heavily doped drain region, a lightly doped source region, a lightly doped drain region, and a channel region, and a gate electrode opposite to the semiconductor layer with an insulating layer interposed therebetween, the method comprising: forming a semiconductor film on a substrate; forming a resist on the semiconductor film such that a first portion of the resist corresponding to the heavily doped source region and the heavily doped drain region is thinner than a second portion of the resist corresponding to the lightly doped source region, the lightly doped drain region, and the channel region; forming the heavily doped source region and the heavily doped drain region by etching the semiconductor film in a predetermined pattern using the resist as a mask and injecting high-density impurities into the semiconductor film through the first portion of the resist; removing the resist from the semiconductor film to form a gate insulating layer on the semiconductor film; forming the gate electrode at a position on the gate insulating layer which corresponds to the channel region; and forming the lightly doped source region and the lightly doped drain region by injecting impurities having a density lower than the density of the high density impurities into the semiconductor film using the gate electrode as a mask.