Patent ID: 7769988

Claim:
An integrated personal computing system comprises: a central processing unit operable to execute operational instructions, wherein the central processing unit includes an arithmetic logic unit interoperably coupled with a data module, an instruction module via a native bus having a native CPU bus rate wherein the central processing unit issues a memory access request when information relating to executing one of the operational instructions is not stored within the data module or the instruction module, and wherein the central processing unit is contained on a substrate; north bridge operably coupled to interface with memory at a memory rate, wherein the north bridge includes a memory access request buffer interoperably coupled with a memory controller, wherein the memory access request buffer receives the memory access request from the central processing unit at the native CPU bus rate, wherein the memory controller retrieves the memory access request from the memory access request buffer at the memory rate, wherein the memory controller processes the memory access request to produce a memory response that includes information stored in memory, and wherein the north bridge is contained on the substrate; and a bus operably coupled to the central processing unit and the north bridge, wherein the bus operates at the native CPU bus rate and provides a transport medium for memory access requests and corresponding memory responses between the central processing unit and the north CHICAGO/#bridge using a native protocol to the central processing unit, and wherein the bus is contained on the substrate.