Patent ID: 7015102

Claim:
A method of forming an electrically erasable and programmable read only memory cell comprising the steps of: forming a first layer of semiconductor material over a bulk material and having a first conductivity type; forming a first region in between said bulk material and said first layer, and having a second conductivity type; forming a trench into a surface of said first layer and having a sidewall and a bottom; forming a second region in said first layer, laterally adjacent to an upper portion of said trench, and having the second conductivity type; forming a channel region in said first layer between said first region and said second region, and extending generally along said sidewall of said trench; forming an electrically conductive floating gate having at least a portion thereof within said trench; forming an electrically conductive control gate having at least a portion thereof disposed over and insulated from said floating gate; and forming an electrically conductive tunneling gate disposed over and insulated from at least a portion of said control gate.