Patent ID: 8111088

Claim:
A level shifter comprising: an input circuit that receives a differential logic signal from two input nodes associated with two complementary logic levels, the two input nodes coupled respectively to symmetric portions of the input circuit, the input circuit including a level transition balancing circuit; a logic element coupled to the input circuit, wherein: the level transition balancing circuit balances the respective rise and fall times of level shifted versions of the two complementary logic levels associated with the differential logic signal during a transition from a first to a second of the two complementary logic levels and an associated level shift; the logic element stores and provides outputs of the level shifted versions of the two complementary logic levels on two output nodes after the transition; and wherein the level transition balancing circuit includes a capacitor in parallel with a transfer element for each of the two input nodes, the capacitor balancing the respective rise and fall times during the transition using a capacitance and a previous level shifted version of the complementary logic level stored in the logic element.