Patent ID: 7886178

Claim:
A semiconductor memory apparatus, comprising: a locked loop circuit adjusting and outputting a phase of a control clock signal which is an internal clock signal in order to synchronize with an external clock signal inputted from outside; a test clock signal input unit inputting two or more test clock signals which have lower frequencies than the external clock signal and which respectively have a difference of phases; an adjusting clock signal generation unit which generates an adjusting clock signal obtained by multiplying a frequency of the test clock signal; a test mode selecting unit selecting the adjusting clock signal as an input to the locked loop circuit instead of the external clock signal in order to test the locked loop circuit; a counting unit which counts the control clock outputted from the locked loop circuit for a predetermined time if the locked loop circuit inputs the adjusting clock signal which is selected by the test mode selecting unit; a comparing unit which compares a counted value obtained by the counting unit to a predetermined expected value; and a phase adjusting unit which adjusts a phase of the control clock signal outputted from the locked loop circuit based on a comparison result between the counted value and the expected value obtained by the comparing unit.