Patent ID: 7408383

Claim:
An interconnect architecture for a programmable logic device comprising: a plurality of interconnect routing lines; a plurality of first-level multiplexers each having data inputs and a data output, the data inputs of the first-level multiplexers connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer; a plurality of second-level multiplexers each having data inputs and a data output, the second-level multiplexers organized into multiplexer groups; a plurality of lookup tables, each lookup table associated with one of the multiplexer groups and having a plurality of lookup table inputs, each lookup table input coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated; wherein the data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.