Patent ID: 8148220

Claim:
A method for manufacturing a tunnel field effect transistor, comprising: providing a substrate lying in a plane; growing an elongate monocrystalline nanostructure on the substrate, the elongate monocrystalline nanostructure having an integrated drain region or source region, the elongate monocrystalline nanostructure further having a channel region comprising a first semiconductor material having a first lattice constant, and a heterosection comprising a second semiconductor material having a different lattice constant from the first semiconductor material, wherein the heterosection acts as an source region or drain region; selectively doping the drain region or source region, channel region, and heterosection to a preselected doping level and a preselected dopant type; forming an integrated drain contact to the drain region of the elongate monocrystalline nanostructure; depositing on side walls of the elongate monocrystalline nanostructure a gate dielectric; depositing on top of the gate dielectric a gate contact; and forming a source contact or drain contact on top of the heterosection of the elongate monocrystalline nanostructure, whereby a tunnel field effect transistor is obtained; wherein at least one of the source region and drain region of the elongate monocrystalline nanostructure is situated in the first section and is highly doped according to a first conductivity type; wherein at least one of the source region and drain region of the elongate monocrystalline nanostructure is situated in the heterosection and is highly doped according to a second conductivity type, wherein an interface between a main part of the elongate monocrystalline nanostructure and the heterosection is substantially defect-free; wherein a channel region adjacent to the heterosection and comprising the first semiconductor material which is lowly doped according to the first conductivity type or lowly doped according to the second conductivity type and is situated between the source region and drain region; and wherein a gate structure is on the channel region of the elongate monocrystalline nanostructure, the gate structure comprising a gate dielectric with a gate contact on top of the gate dielectric.