Patent ID: 7598538

Claim:
An ESD (electro-static discharge) protecting circuit comprising: a device isolation layer in a field region of a semiconductor substrate having a first conductivity type; first and second high-concentration impurity regions in the semiconductor substrate, isolated from each other by the device isolation layer and having a second conductivity type, wherein the first high-concentration impurity region contacts a first sidewall surface of the device isolation layer and the second high-concentration impurity region contacts a second sidewall surface of the device isolation layer opposite to said first sidewall surface; a third high-concentration impurity region in the semiconductor substrate, isolated from the second high-concentration impurity region by the device isolation layer, and having the first conductivity type; a first well in a first portion of the semiconductor substrate in contact with and below the second and third high-concentration impurity regions and below a first portion of the first high-concentration impurity region, and having the first conductivity type a second well in a second portion of the semiconductor substrate in contact with and below a second portion of the first high-concentration impurity region on one side of the first well, and having the second conductivity type; and a fourth impurity region below the first high-concentration impurity region at a boundary between the first and second wells, the fourth impurity region separating the first high-concentration impurity region from the first well, and having the first conductivity type.