Patent ID: 8381157

Claim:
A device comprising: a first semiconductor chip that comprises, a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a plurality of first data signals in response to data stored in selected ones of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a plurality of first data electrodes, and a first data control circuit coupled to the first control logic circuit and the first data electrodes, the first data control circuit receiving the first data signals and responding to change from the inactive level to the active level of the first output timing signal to initiate driving each of the first data electrodes to a logic level related to an associated one of the first data signals; and a second semiconductor chip that comprises, a second memory cell array including a plurality of second memory cells, a second control logic circuit accessing the second memory cell array and producing a plurality of second data signals in response to data stored in selected ones of the second memory cells, the second control logic circuit being configured to store second timing adjustment information and to produce a second output timing signal that is adjustable in timing of change from an inactive level to an active level by the second timing adjustment information, a plurality of second data electrodes, each of the second data electrodes penetrating the second semiconductor chip to include a first end portion on a side of a first main surface of the second semiconductor chip and a second end portion on a side of a second main surface of the second semiconductor chip opposite to the first main surface, and a second data control circuit coupled to the second control logic circuit and the second data electrodes, the second data control circuit receiving the second data signals and responding to change from the inactive level to the active level of the second output timing signal to initiate driving each of the second data electrodes to a logic level related to an associated one of the second data signals, the first semiconductor chip being stacked over the first main surface of the second semiconductor chip such that each of the first data electrodes of the first semiconductor chip is connected to the first end portion of an associated one of the second data electrodes of the second semiconductor chip.