Patent ID: 7514975

Claim:
A circuit for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input configured to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is received at said data input, is clocked into said at least one latch and passes to said data output along said forward data path; wherein at least one of said at least one latch comprises a retention latch for retaining a signal value during said sleep mode, and said circuit further comprises a tristateable device, arranged between said forward data path and said retention latch, for selectively isolating said retention latch from said forward data path in response to receipt of a first sleep signal; wherein said circuit is responsive to receipt of a second sleep signal received after said first sleep signal and configured to enter said sleep mode such that said portion of said circuit is powered down by reducing a voltage difference across said portion of said circuit, and a voltage difference across said retention latch and said tristateable device is maintained, wherein said retention latch is configured to receive said clock signal and comprises a clocked tristate inverter, and transistors arranged in parallel with a portion of said clocked tristate inverter and configured to receive said first sleep signal such said retention latch retains state irrespective of a value of said clock signal during receipt of said first sleep signal.