Patent ID: 8830761

Claim:
A method, comprising: reading a first memory cell of an array of memory cells each having a charge accumulation transistor in series with a selection transistor, the reading including: applying a read biasing voltage to a bitline to which the first memory cell and a second memory cell of the array are electrically coupled; applying, via a first wordline electrically coupled to the first and second memory cells, a positive selection voltage to respective gates of the selection transistors of the first and second memory cells; applying a read voltage to a control gate of the charge accumulation transistor of the first memory cell; and sensing a current flowing in the memory cell; maintaining the charge accumulation transistor of the second memory cell in a blocked state while reading the first memory cell by applying a negative inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell; and applying a null voltage to control gates of the charge accumulation transistors of third and fourth memory cells of the array which are electrically coupled to a second wordline.