Patent ID: 7250885

Claim:
A time interleaved analog-to-digital converter system including an analog input, a clock input, and a digital output, comprising: a non-sequential channel selection circuit, operatively connected to said clock input, to generate channel selection signals; a plurality of analog-to-digital converters, operatively connected to said analog input, to said non-sequential channel selection circuit, and to said clock input, to receive said analog input, a channel selection signal, and a clock signal, each analog-to-digital converter being associated with a channel, each analog-to-digital converter receiving a different channel selection signal; a reference analog-to-digital converter, operatively connected to said non-sequential channel selection circuit, to said analog input, and to said clock input, to receive an analog input signal, a channel selection signal, and a clock signal; a plurality of clock sequence detection circuits, operatively connected to said non-sequential channel selection circuit, to receive a channel selection signal and the channel selection signal received by said reference analog-to-digital converter, each clock sequence detection circuit being associated with one of said plurality of analog-to-digital converters that receives the same channel selection signal; a plurality of timing skew estimation circuits, operatively connected to said reference analog-to-digital converter, to receive an output from said reference analog-to-digital converter and to generate a timing skew estimate, each timing skew estimation circuit being operatively connected to one of said plurality of clock sequence detection circuits and being associated with one of said plurality of analog-to-digital converters, each timing skew estimation circuit receiving an output from the associated analog-to-digital converter; and a selection circuit operatively connected to said plurality of analog-to-digital converters, said reference analog-to-digital converter, and said non-sequential channel selection circuit; said selection circuit selecting one output from said plurality of said analog-to-digital converters and said reference analog-to-digital converter to be provided to said digital output in response to said channel selection signals.