Patent ID: 8373443

Claim:
A logic circuit comprising: a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode; a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; a first terminal electrically connected to the second gate electrode of the second transistor; and a second terminal electrically connected to a portion where the second transistor is connected to the first transistor, wherein a high power supply voltage terminal is electrically connected to one of the first source electrode and the first drain electrode of the first transistor, and the first gate electrode of the first transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor; wherein one of the second source electrode and the second drain electrode of the second transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor, and a low power supply voltage terminal is electrically connected to the other of the second source electrode and the second drain electrode of the second transistor, wherein the first transistor comprises: the first gate electrode; a gate insulating layer provided over the first gate electrode; a first oxide semiconductor layer provided over the gate insulating layer; the first source electrode which is electrically connected to the first oxide semiconductor layer; and the first drain electrode which is electrically connected to the first oxide semiconductor layer, wherein a reduction prevention layer does not overlap the first oxide semiconductor layer, the first source electrode, and the first drain electrode, wherein the second transistor comprises: the second gate electrode; the gate insulating layer provided over the second gate electrode; a second oxide semiconductor layer provided over the gate insulating layer; the second source electrode which is electrically connected to the second oxide semiconductor layer; and the second drain electrode which is electrically connected to the second oxide semiconductor layer, wherein the reduction prevention layer overlaps the second oxide semiconductor layer, the second source electrode, and the second drain electrode.