Patent ID: 8535990

Claim:
A process of forming an integrated circuit, comprising steps: providing a wafer, said wafer further including: a substrate of a semiconductor material with a first crystal orientation; and a top layer of semiconductor material with a second crystal orientation formed over said substrate; removing said top layer of semiconductor material in a logic region to expose said substrate; growing an epitaxial layer of semiconductor material on said substrate in said logic region, wherein said epitaxial layer has said first crystal orientation; forming an array of SRAM cells in said top layer of semiconductor material, in which each said SRAM cell further includes: two SRAM NMOS transistors; and two SRAM PMOS transistors; and; forming a logic circuit in said epitaxial layer in said logic region, said logic circuit further including: a plurality of logic NMOS transistors; and a plurality of logic PMOS transistors.