Patent ID: 8476693

Claim:
A nonvolatile semiconductor memory, comprising: a memory cell array including a plurality of NAND cell units, each of NAND cell units having a plurality of memory cell transistors formed on a semiconductor substrate at a predetermined spacing, each of memory cell transistors having a first gate insulating film, a floating gate electrode, a second gate insulating film and a control gate electrode stacked on the semiconductor substrate in the order, each of NAND cell units having a source-side select gate transistor disposed at one end of the plurality of memory cell transistors and a drain-side select gate transistor disposed at the other end of the plurality of memory cell transistors, the source-side select gate transistors of the NAND cell unit being disposed in such a manner as to face each other and interpose a first contact therebetween, and the drain-side select gate transistors of the NAND cell unit being disposed in such a manner as to face each other and interpose a second contact therebetween; a first silicon nitride film present in a region between the source-side select gate transistors and disposed at a position lowest from the upper surface of the semiconductor substrate; and a second silicon nitride film formed in a region between the drain-side select gate transistors and disposed at a position lowest from the upper surface of the semiconductor substrate, wherein a spacing including the first contact between the source-side select gate transistors is smaller than a spacing including the second contact between the drain-side select gate transistors, and wherein a distance from the upper surface of the semiconductor substrate to the upper surface of the first silicon nitride film is larger than a distance from the upper surface of the semiconductor substrate to the upper surface of the second silicon nitride film.