Patent ID: 7898037

Claim:
A semiconductor structure comprising: a substrate; a first Fin field-effect transistor (FinFET) at a top surface of the substrate, the first FinFET comprising: a first fin; a first gate dielectric on a top surface and sidewalls of the first fin; a first gate electrode on the first gate dielectric; a first source/drain region in a portion of the first fin uncovered by the first gate dielectric; and a first source/drain silicide region on the first source/drain region; a second FinFET at the top surface of the substrate, the second FinFET comprising: a second fin; a second gate dielectric on a top surface and sidewalls of the second fin; a second gate electrode on the second gate dielectric; a second source/drain region in a portion of the second fin uncovered by the second gate dielectric; and a second source/drain silicide region on the second source/drain region; a first inter-layer dielectric (ILD) over the first and the second FinFETs; a second ILD over the first ILD; a contact plug contacting the first and the second source/drain silicide regions, wherein the contact plug comprises a sidewall extending continuously from a top surface of the first ILD to lower than top surfaces of the first and the second source/drain silicide regions, with the sidewall being substantially vertical with substantially no horizontal shift, and wherein the contact plug includes a contiguous structure which extends over the first fin and the second fin and interposes the first fin and the second fin; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the bottom IMD and a via in the second ILD, wherein the via has a bottom surface contacting a top surface of the contact plug.