Patent ID: 7829419

Claim:
A method, comprising: selectively forming an isolation region in a semiconductor substrate to define a memory array region and a peripheral circuit region, the memory array region including a first active region for a memory cell transistor of a first channel type, the peripheral circuit region including second and third active regions respectively for first and second peripheral transistors, the first peripheral transistor being of the first channel type, the second peripheral transistor being of a second channel type that is different from the first channel type, each of the first, second, and third active regions including a channel formation portion and source and drain formation portions; forming a first gate structure on the channel formation portion of the first active region and second and third gate structures respectively on the channel formation portions of the second and third active regions, the first gate structure being for the memory cell transistor, the second gate structure being for the first peripheral transistor, the third gate structure being for the second peripheral transistor, each of the first, second, and third gate structures comprising a gate insulating film and a gate electrode formed on the gate insulating film; removing respective parts of the source and drain formation portions of the first active region to form recesses respectively in the source and drain formation portions of the first active region, the removing the respective parts of the source and drain formation portions of the first active region being carried out while protecting respective parts of the source and drain formation portions of the second and third active regions from being removed; and performing epitaxial growth to form epitaxial layers in the recesses of the source and drain formation portions of the first active regions and on the source and drain formation regions of each of the second and third active regions.