Patent ID: 7778371

Claim:
A method for controlling the duty cycle and frequency of a digitally generated clock, the method comprising: accepting a first clock signal having a fixed first frequency, as follows: dividing the first clock signal by integer n; and, supplying a second signal having a plurality of phases; loading a frequency control word with a first pattern into a first plurality of serially-connected registers; loading a duty cycle control word with a second pattern into a second plurality of serially-connected registers; generating a register clock signal in response to the first clock and the first pattern, as follows: serially supplying the frequency control word to a chain of phase selection registers clocked by the register clock signal; and, serially selecting second signal phases in response to the first pattern, as follows: generating a sequence of phase selection register output pulses in response to the register clock signal and the first pattern; and, using the generated register output pulses to select the phases of the second signal; and, generating the digital clock signal having the frequency and the duty cycle responsive to the register clock signal and the second pattern.