Patent ID: 8068577

Claim:
A pull-down control circuit usable in a shift register, comprises: (a) an input circuit electrically coupled to a first control voltage, V 1 ; (b) a release circuit electrically coupled to the input circuit, a second control voltage, V 2 , and the reference voltage, VSS; (c) a pull-down circuit electrically coupled to the input circuit and the release circuit; (d) an output circuit electrically coupled to the input circuit and the pull-down circuit; (e) a first input terminal for receiving the first control voltage, V 1 ; (f) a second input terminal for receiving the second control voltage, V 2 ; and (g) a third input terminal for receiving the reference voltage, VSS, wherein the release circuit has a first input terminal electrically connected to the second input terminal, a second terminal electrically connected to a node, K, and a third terminal electrically connected to the third input terminal, and comprises three transistors T 12 , T 13 and T 14 , wherein the transistors T 12 has a gate, a drain electrically connected to the second terminal, and a source electrically connected to the third terminal; wherein the transistors T 13 has a gate electrically connected to the first terminal, a drain electrically connected to the gate, and a source electrically connected to the gate of the transistor T 12 ; and wherein the transistors T 14 has a gate electrically connected to the first terminal, a drain electrically connected to the gate of the transistor T 12 , and a source electrically connected to the third terminal; wherein the input circuit has a transistor T 4 having a gate electrically connected to the first terminal, a drain electrically connected to the gate, and a source electrically connected to the second terminal of the release circuit; wherein the pull-down circuit has a transistor T 6 having a gate electrically connected to a node, Q, a drain electrically connected to the node K, and a source electrically connected to the third terminal of the release circuit; and wherein the output circuit has a transistor T 5 having a gate electrically connected to the node K, a drain electrically connected to the drain of the transistor T 4 , and a source electrically connected to a node, P, and a transistor T 7 having a gate electrically connected to the gate of the transistor T 6 , a drain electrically connected to the node P, and a source electrically connected to the source of the transistor T 6 .