Patent ID: 8397112

Claim:
A system for detecting faults on a test chain, the system comprising: a circuit having at least an output wherein the output of the circuit provides a test signal; the test chain having an input, a plurality of buffers connected in series and an output; wherein the input of the test chain is directly connected to the output of the circuit and an input of a first buffer in the plurality of buffers; wherein an output of a last buffer in the plurality of buffers is directly connected to the output of the test chain; a register having at least an input and an output; wherein the input of the register receives a logical value representing the output of the test chain; wherein the logical value may be observed by test circuitry; a plurality of pull-up devices wherein each pull-up device in the plurality of pull-up devices has a control input, an input and an output; wherein the control input of first pull-up device is connected to the input of the test chain; wherein each of the remaining control inputs is connected to an output of a buffer respectively; wherein each output of the plurality of pull-up devices is directly connected to an individual tri-state node respectively; wherein each input of the plurality of pull-up devices is directly connected to a DC voltage; wherein the plurality of pull-up devices are activated only when the tri-state nodes are tested.