Patent ID: 8642470

Claim:
A semiconductor device manufacturing method, comprising: (a) etching a first dielectric layer to form a recess, wherein said first dielectric layer is formed of a first dielectric material; (b) depositing a second dielectric material over said first dielectric layer and said recess to form a second dielectric layer, such that said recess is enclosed by said first dielectric layer and said second dielectric layer to form a space; (c) forming a first trench in said first dielectric layer and said second dielectric layer, adjacent to but separate from any space, while maintaining the space undamaged as an air gap; (d) further etching said first trench to form a first through hole, wherein said first trench and said first through hole that communicate with each other penetrate said first dielectric layer and said second dielectric layer; (e) filling a first conductive material into said first trench and said first through hole to form a conductive material via; (f) performing a chemical mechanical planarization on said first conductive material such that a surface obtained through the planarization is higher than the top end of said air gap; (g) forming a second blocking layer on the surface obtained through said chemical mechanical planarization; (h) forming a third dielectric layer on said second blocking layer; (i) etching said third dielectric layer to form a second trench and a second through hole that communicates with said second trench, wherein said second trench and said second through hole penetrate said third dielectric layer and said second blocking layer, and the lower end of said second through hole is substantially flush with the top end of said first conductive material; and (j) filling a second conductive material into said second trench and said second through hole.