Patent ID: 7829409

Claim:
A method of fabricating a topological capacitor, the method comprising the steps of: providing a silicon substrate having a top surface; depositing an etch mask on the top surface of the substrate, the etch mask further comprising etch lines defining a plurality of capacitive elements of a plurality of capacitive element groups and etch lines defining the plurality of capacitive element groups, wherein the width of the etch lines defining the plurality of capacitive element groups is greater than the width of the etch lines defining the plurality of capacitive elements within the group; anisotropically etching the substrate top surface identified by the etch mask to form a plurality of spaced pillar capacitive elements and a plurality of capacitive element groups; thermally oxidizing the etched substrate top surface; depositing a diffusion barrier adjacent to the oxidized surface; depositing a conductive silicon substrate layer adjacent to the diffusion barrier; and depositing a polysilicon layer adjacent to the conductive layer thereby forming a topological capacitor having a plurality of capacitive elements and a plurality of capacitive element groups.