Patent ID: 7199573

Claim:
An electronic circuit, comprising: a plurality of input/output (I/O) nodes for connecting the electronic circuit to at least a further electronic circuit; a test unit for testing the electronic circuit in a test mode of the electronic circuit, the test unit comprising a combinatorial circuit having a plurality of inputs and an output, the combinatorial circuit implementing an exclusive logic function; the I/O nodes being logically connected to the test unit in the test mode, wherein: a first selection of the I/O nodes is arranged to carry respective input signals and is connected to the plurality of inputs of the combinatorial circuit; and a second selection of the I/O nodes comprises a first I/O node and is arranged to carry respective output signals, the first I/O node being coupled to the output of the combinatorial circuit; and the second selection of I/O nodes further comprises a second I/O node that is coupled to an I/O node from the first selection of I/O nodes in the test mode via a connection that includes at least one of a buffer and an inverter, wherein the inverter facilitates a third I/O node from the second selection of I/O nodes being coupled to a further I/O node from the first selection of I/O nodes via a connection that bypasses the combinatorial circuit, and the buffer facilities at least the second I/O node being coupled to the I/O node from the first selection of I/O nodes.