Patent ID: 7362134

Claim:
A device comprising: a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value; a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value, the latch stage further comprising: a NOR logic stage having a first input to receive the bypass value, a second input to receive a representation of the second data value, and an output; and an inverter logic stage having an input coupled to the output of the NOR logic stage and an output coupled to the second input of the NOR logic stage and the second input of the second combinatorial logic stage; and a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.