Patent ID: 7328117

Claim:
A computer program product for verifying an asynchronous circuit, embodied on a computer-readable medium and comprising code that, when executed, causes a computer to perform the following: (a) carrying out a function simulation of an asynchronous circuit based on circuit information of said asynchronous circuit including a sequential circuit stored in a storage device; and (b) monitoring an output value from an output node of said sequential circuit every unit time, and setting said output value in n time as a value of a metastable state, when said output value in said n time is changed from said output value in (n−1) time; wherein said step (a) includes: (a1) when said asynchronous circuit includes a plurality of sequential circuits which are connected to a same net, separating said net for each of said plurality of sequential circuits, and (a2) carrying out said function simulation of a first asynchronous circuit including a separated sequential circuit, which is included in said plurality of sequential circuits and connected to said separated net, wherein said step (b) includes: (b1) monitoring said output value from said output node of said separated sequential circuit every unit time, and setting said output value of said separated sequential circuit in said n time as said value of the metastable state, when said output value of said separated sequential circuit in said n time is changed from said output value in said (n−1) time.