Patent ID: 7019595

Claim:
A phase control loop circuit for tuning to a reference frequency signal comprising: a phase lock loop (PLL) circuit being responsive to a reference frequency signal having a reference frequency, said PLL circuit including a voltage control oscillator (VCO) for generating a VCO output, said PLL circuit for generating a PLL output, said phase control loop circuit processing said VCO output to generate an output frequency signal having an output frequency; and a coarse tuning circuit being coupled to said PLL circuit, said coarse tuning circuit being responsive to said PLL output for processing the same to generate a counter output, said VCO being responsive to said counter output, said counter output being used for coarse tuning said output frequency signal to said reference frequency signal, said coarse tuning circuit further responsive to a lock detection (LD) signal, said LD signal for controlling said counter output to cause said output frequency to be within a predetermined range of frequencies including said reference frequency, said PLL circuit for fine tuning said output frequency signal to said reference frequency signal, wherein said PLL circuit and said coarse tuning circuit tune the output frequency to the reference frequency included in a wide range of frequencies further wherein said PLL circuit includes a phase-frequency detector (PFD) circuit for comparing said output frequency with said reference frequency to generate a PFD output, said PFD output including a Δf signal for representing the difference between said output frequency and said reference frequency, said PLL circuit further including a charge pump (CP) circuit responsive to said PFD output for generating a current, the value of said current being based on the value of said Δf signal, wherein said PLL circuit further includes a loop filter responsive to said current for converting the same to generate a control voltage (V ctrl ) signal having a voltage value V ctrl , said V ctrl signal being provided to said VCO to control said VCO output, said V ctrl signal controlling said VCO output to enable said PLL circuit to fine tune said output frequency to said reference frequency, further wherein said coarse tuning circuit includes a comparator circuit, said comparator circuit including a first comparator and a second comparator, said V ctrl signal being included in said PLL output, said first and second comparators being responsive to said PLL output, said first comparator being responsive to a first fixed value signal having a first voltage value, said second comparator being responsive to a second fixed value signal having a second voltage value.