Patent ID: 7599223

Claim:
A non-volatile memory comprising: an array of memory cells that is organized into erasable blocks, each erasable block containing a block of word lines for accessing memory cells that are erasable together, and each word line containing at least one page of memory cells that are programmable together; a designated sample of pages representative of the given page within a block; an associated programming voltage for programming each page of the sample, the associated programming voltage having a staircase waveform with an initial value and a predetermined maximum voltage limit; a built-in self testing module for determining a starting programming voltage for a given page, said module providing memory operations including: (a) erasing the sample of pages; (b) for every page in the sample, programming and verifying the page step by step of the staircase waveform until either the maximum voltage limit has been reached or the page has been programmed to a target pattern and in which case a final programming voltage is accumulated as part of a gathered statistics; and (c) providing the gathered statistic for computing an average starting programming voltage for the sample for deriving a starting programming voltage for the given page; and wherein: the sample is part of larger sample taken from a plurality of blocks in the memory array; and the gathered statistics includes accumulated initial values associated with programmable pages from the plurality of blocks.