Patent ID: 7087991

Claim:
An integrated circuit package, comprising: a substrate having a first surface, wherein the substrate comprises an internal circuit; a chip having an active surface with a plurality of bonding pads thereon and a backside surface attached to the first surface of the substrate; and a build-up circuit structure on the substrate, the build-up circuit structure having at least one insulation layer, at least one patterned circuit layer and a plurality of via openings, wherein the insulation layer is located between the active surface and the patterned circuit layer, the via openings corresponding to the bonding pads pass through the insulation layer, wherein the via openings are deposited with a conductive material, the patterned circuit layer electrically connects with the bonding pads through the conductive material and a portion of the patterned circuit layer expands into a region outside the active surface of the chip, wherein the space between the chip and the substrate is filled by the material of the insulation layer.