Patent ID: 7265604

Claim:
A high-frequency switch circuit arrangement, comprising: an input terminal, inputting a high-frequency signal; an output terminal, outputting the input high-frequency signal; a first field effect transistor, being connected between the input terminal and the output terminal; a second field effect transistor, having a drain connected to the input terminal so as to enter a conduction state when the first field effect transistor is in a non-conduction state; and first and second capacitative elements being connected in series between a source of the second field effect transistor and a ground terminal; wherein the first and second capacitative elements are implemented as an MIM (metal insulator metal) capacitor comprising a lower electrode created on a semiconductor substrate and first and second upper electrodes formed apart on a dielectric layer via the dielectric layer formed on the lower electrode, the source of the second field effect transistor is connected to the first upper electrode, the second upper electrode is connected to the ground terminal, and the first capacitative element formed between the first upper electrode and the lower electrode and the second capacitative element formed between the lower electrode and the second upper electrode make up the first and second capacitative elements connected in series.