Patent ID: 8716078

Claim:
A method for fabricating a vertical JFET, the method comprising: providing a III-nitride substrate of a first conductivity type; forming a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate; forming a second III-nitride epitaxial layer of the first conductivity type coupled to the first III-nitride epitaxial layer; removing at least a portion of the second III-nitride epitaxial layer to expose a sidewall of the second III-nitride epitaxial layer; removing at least a portion of the first III-nitride epitaxial layer to form a channel region of the vertical JFET, wherein the channel region has a channel sidewall; forming a III-nitride gate structure of a second conductivity type coupled to the channel sidewall, wherein a top of the III-nitride gate structure is lower than a top of the second III-nitride epitaxial layer; and forming a gate metal electrically coupled to the III-nitride gate structure and laterally self-aligned with respect to the sidewall of the second III-nitride epitaxial layer, wherein forming the gate metal comprises: forming a first masking layer covering the top of the second III-nitride epitaxial layer; depositing a metal layer to form a first metal structure on the first masking layer; forming a second metal structure on the top of the III-nitride gate structure, wherein the first metal structure and the second metal structure are vertically spaced apart by a source spacer; and removing the first masking layer and the source spacer to lift off the first metal structure, preserving the second metal structure to form the laterally self-aligned gate metal.