Patent ID: 8209471

Claim:
A memory system comprising: a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing; a cache memory configured between a host apparatus and the nonvolatile semiconductor memory; a controller driving the parallel operation elements in parallel and executing data transfer between the nonvolatile semiconductor memory and the host apparatus via the cache memory; a first management table having a correspondence relation between the physical blocks driven in parallel and a logical block associated with the plurality of physical blocks; and a second management table having a correspondence relation between a LBA logical address input in sector units from the host apparatus and the logical block, wherein the controller includes: a first control unit that performs, when a first event related to a change in the correspondence relation between the plurality of physical blocks and the logical block occurs, processing corresponding to the first event based on the first management table and updates the first management table; and a second control unit that performs, when a second event related to a change in the correspondence relation between the LBA logical address and the logical block occurs, processing corresponding to the second event based on the second management table and updates the second management table, and the controller causes the first and second control units to operate independently from each other.