Patent ID: 8916975

Claim:
A semiconductor memory device, comprising: a semiconductor circuit substrate having a chip pad region comprising first and second data pads configured to receive a pair of differential data signals, respectively, and a power pad interposed between the first and the second data pads, wherein the first and the second data pads are at equal distances from the power pad; first and second data lines formed on the semiconductor circuit substrate at a first side with reference to the chip pad region, each of the first and second data lines extending on the semiconductor circuit substrate and arranged adjacent to each other, wherein the first and second data lines are electrically connected to the first and second data pads, respectively; and power lines formed on the semiconductor circuit substrate at a second side with reference to the chip pad region, the second side being opposite to the first side with reference to the chip pad region, the power lines extending on the semiconductor circuit substrate, wherein the power lines are electrically connected to the power pad, wherein the chip pad region is interposed between the first side and the second side of the semiconductor circuit substrate.