Patent ID: 7298000

Claim:
A semiconductor die, comprising: an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising: a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising: forming an insulating layer on the substrate; forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer; forming a conductive layer on the insulating layer and the exposed portion of the substrate; forming a fill layer on the conductive layer, wherein the fill layer fills the opening; and removing the conductive layer and the fill layer to a level below a top of the insulating layer; wherein the bottom plate has a cylindrical shape, the bottom plate includes at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon, and the silicon material is conductively doped; a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising: forming a dielectric layer on the insulating layer, the conductive layer and the fill layer; and removing the dielectric layer from the insulating layer and the fill layer, wherein the dielectric cap includes at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides, and wherein the dielectric cap is annealed at approximately 600 degree C. to 1000 degree C. for approximately 10 to 20 seconds; a dielectric layer on the bottom plate and the dielectric cap, wherein the dielectric cap is adapted to form part of the dielectric layer; and a cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate.