Patent ID: 7821049

Claim:
A semiconductor memory device comprising; a first transistor and a second transistor formed on a semiconductor substrate, both the first transistor and the second transistor being MIS transistors; a memory capacitor formed above the first transistor, the memory capacitor being connected to the first transistor, the memory capacitor being stacked with a lower electrode, a dielectric film and an upper electrode in order, the lower electrode being connected to a source or a drain of the first transistor; a pair of dummy memory capacitors formed above the second transistor, each dummy memory capacitor being stacked with a dummy lower electrode, a dummy dielectric film and a dummy upper electrode in order, the dummy lower electrodes in the pair being configured as a common electrode, the memory capacitor and the dummy memory capacitor being formed in a same plane above the semiconductor substrate; a wiring layer formed above the memory capacitor and the dummy memory capacitor, the wiring layer being connected to the source or the drain of the first transistor and the upper electrode; a first plug connecting between a source or a drain of the second transistor and the dummy lower electrode; and a second plug connecting between the dummy lower electrode and the wiring layer, the second plug penetrating into the paired dummy upper electrodes and the paired dummy dielectric films to contact with a surface of the dummy lower electrode.