Patent ID: 7529412

Claim:
An image processing apparatus for converting image data between a raster scan order and a block scan order, comprising: an image data processor for supplying image data of a raster scan order having a given horizontal resolution and a given vertical resolution; a line memory for storing image data of a plurality of lines; an address generating block for converting supplied image data of raster scan order to block scan order by generating a common read/write address for the line memory so that only one line memory is required for performing simultaneous read and write operations, the address generating block including a block address generator for generating an address of a block which image data is read from and written into; a line offset generator for providing a line offset between an earlier common read/write address and a present common read/write address for the line memory; and an address generator including a multiplexer sequentially providing a plurality of input values including at least one output of at least two adders and the address of the block to a next anchor address register; a first adder of the at least two adders outputting a sum of a next anchor address of the next anchor address register and the line offset; a second adder of the at least two adders outputting a difference of the next anchor address of the next anchor address register and a desired value; an anchor address register receiving the next anchor address from the next anchor address register; and a common read/write address operator operating upon the received next anchor address to generate the common read/write address; and an encoder receiving image data of the block scan order from the line memory and encoding the received image data.