Patent ID: 7362632

Claim:
A system for testing a plurality of memory devices, comprising: a) a probe card comprising: a plurality of sets of input ports, each set of input ports comprising: at least two input ports each configured to receive a respective test signal; and a chip select port configured to receive a chip select signal; a plurality of sets of output ports each communicatively coupled to a respective one of the sets of input ports; each set of output ports comprising: at least two output ports communicatively coupled to a respective one of the at least two input ports of the respective set of the input ports; and b) a separate chip selector for each set of input ports and respective set of output ports, wherein each chip selector is configured to: receive the chip select signal from the respective chip select port; receive a command signal via one of the input ports of the respective set of input ports, wherein the command signal is one of the test signals; and in response to the received command signal, issue at least one chip selection signal to select, for testing, at least one of two or more memory devices connected to the set of output ports.