Patent ID: 8187950

Claim:
A method of forming a semiconductor structure comprising: providing a semiconductor substrate with a substrate region, the substrate region having an even surface; forming a pad oxide layer overlying the substrate region; forming a stop layer overlying the pad oxide layer; patterning the stop layer and the pad oxide layer to expose a portion of the substrate region; forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height; depositing an oxide layer to a first height within the trench using an HDP-CVD process; depositing a silicon nitride layer within the trench, the silicon nitride layer overlying the oxide layer and at least filling the trench; performing a planarization process to remove a portion of the silicon nitride and oxide layers to expose a top surface of the trench; and removing the pad oxide and stop layers; wherein the top surface of the trench is coplanar with the even surface of the substrate region, and wherein the planarized silicon nitride layer entirely covers the top surface of the trench.