Patent ID: 6972608

Claim:
A clock generating circuit, comprising: a reference clock oscillating circuit for carrying out an oscillating operation to output a reference clock signal during a period for which an oscillation permitting instruction is given based upon an oscillation control signal, and stopping the oscillating operation to stop the output of the reference clock signal during a period for which an oscillation stop instruction is given based upon the oscillation control signal; an oscillation control unit for outputting the oscillation control signal to give the oscillation permitting instruction for a predetermined time of a predetermined time duration, wherein the oscillation control unit is equipped with a temperature detecting unit for detecting the temperature of a measuring clock output unit, and controls the time interval for giving the oscillation permitting instruction on the basis of the detected temperature; and a frequency multiplying circuit for multiplying and outputting the frequency of the reference clock signal through digital processing, wherein the frequency multiplying circuit comprises: the measuring clock output unit for generating a measuring clock signal having a frequency higher than the frequency of the reference clock signal based upon the oscillating operation based on digital control; a measuring unit for measuring the period of the reference clock signal on the basis of the period of the measuring clock signal during the oscillation permitting instruction period, thereby achieving period data; a period data holding unit for holding the period data; and a multiplying unit for multiplying the frequency of the reference clock signal with the period of the measuring clock signal as a resolution based upon the period data successively measured during the oscillation permitting instruction period or on the basis of the period data held in the period data holding unit during the oscillation stop instruction period, thereby generating a multiplied clock signal.