Patent ID: 7642828

Claim:
A level conversion circuit comprising: an input section, comprising: N-channel MOS transistors for a differential transistor pair; a pair of resistors; and a constant current source, wherein the constant current source is connected to common sources of the N-Channel MOS transistors, and each of the pair of resistors is connected to drains of the N-Channel MOS transistors as loads, and wherein said input section is configured to receive a first signal of a first signal level and a correction signal, and to generate a second signal of a second signal level from said first signal and said correction signal; a level converting section configured to convert said second signal into an output signal of a third signal level; and a duty correcting section configured to generate said correction signal corresponding to a duty ratio of said output signal and to output said correction signal to said input section, said duty correcting section comprising a correcting section differential transistor pair connected in parallel with said differential transistor pair of the input section, wherein said second signal is generated through current addition of a drain current of said differential transistor pair in the input section and a drain current of the differential transistor pair in said duty correction section.