Patent ID: 7352209

Claim:
A voltage-level converter comprising: a static voltage-level converter having an input node and at least three outputs, the static voltage-level converter including no more than four transistors and a first inverter, the no more than four transistors including a first pair of transistor including a first transistor and a second transistor connect in series between a first voltage level and a first pull-up node and a second pair of transistors including a third transistor and a four transistor connected in series between the first voltage level and a second pull-up node; a fifth transistor coupled to the input node and the first pull up node of the static voltage-level converter, the fifth transistor coupling the first pull-up node to a second voltage level; a sixth transistor coupled to the input node though a first inverter, the sixth transistor coupling the second pull-up node of the static voltage-level converter to the second voltage level; and a second inverter having no more than three transistors coupled in series, the no more than three transistors coupled in series coupling the first voltage level to the second voltage level, wherein a gate of each of the no more than three transistors of the second inverter is coupled to one and only one of the at least three outputs of the static voltage-level converter.