Patent ID: 7049196

Claim:
A method for fabricating a gain cell on a semiconductor substrate, the method comprising the steps of: forming a vertical write transistor having multiple sides, the vertical write transistor having a gate, a body region and first and second source/drain regions; forming a vertical read transistor having multiple sides, the vertical read transistor having a body region and first and second source/drain regions, the vertical read transistor further having a gate region that couples to the second source/drain region of the vertical write transistor; forming a charge storage node coupled to the second source/drain region of the vertical write transistor; forming a write bit line that couples to the first source/drain region of the vertical write transistor; forming a write wordline that couples to the gate region of the vertical write transistor; forming a read bit line that couples to the first source/drain region of the vertical read transistor; and forming a read wordline that couples to the second source/drain region of the vertical read transistor.