Patent ID: 8806148

Claim:
A method in a multiprocessor data processing system including a plurality of cache memories including a cache memory, the method comprising: in response to a read-type request of an associated processor core, issuing, by the cache memory, a read-type operation for a target cache line; while servicing the read-type request, monitoring, by the cache memory, to detect receipt of a competing store-type operation for the target cache line; in response to receiving the target cache line of the read-type operation: installing the target cache line in a data array of the cache memory and, in a directory of the cache memory, setting a state field associated with the target cache line to a selected initial coherence state among multiple possible initial coherence states based on whether the competing store-type operation is detected while servicing the read-type request, wherein the setting includes: selecting, as the initial coherence state, a first coherence state that designates the cache memory as a source of copies of the target cache line in response to not detecting a competing store-type operation while servicing the read-type request; and selecting, as the initial coherence state, a different second coherence state that does not designate the cache memory as a source of copies of the target cache line in response to detecting a competing store-type operation while servicing the read-type request.