Patent ID: 6861699

Claim:
A non-volatile memory device comprising: a pair of bit lines; a pair of word lines; and a unit cell having first and second memory cells connected between the pair of bit lines, wherein the first memory cell formed in a first channel area of a first conductive silicon substrate comprises: a first conductive gate connected to one word line of the pair of word lines; a first dielectric layer including an electron trapping layer formed in the bottom and a side wall of the first conductive gate; and a first junction area of a second conductivity type which is connected to one bit line of the pair of bit lines and is overlapped with the first conductive gate, wherein the second memory cell formed in a second channel area, facing the first conductive gate, comprises: a second conductive gate connected to the other word line of the pair of word lines; a second dielectric layer including an electron trapping layer formed in the bottom and a side wall of the second conductive gate; and a second junction area of the second conductivity type which is connected to the other bit line of the pair of bit lines, and overlapped with the second conductive gate.