Patent ID: 7926017

Claim:
A layout method for a chip, adaptable to place cells on the chip, comprising: assigning a chip area for a floor plan; performing a global reservation deployment process to define a plurality of room units to be uniformly distributed on the chip area; placing cells on the chip based on the floor plan; categorizing the chip area into at least a high frequency region and a low frequency region according to operation frequencies of the cells; performing by a computer a frequency based reservation deployment process to move one or more room units distributed in the low frequency region toward the high frequency region; performing a local cell replacement for the placed cells based on a distribution of the room units to decrease possibility of hotspots; performing a routing and timing analysis to determine whether hotspots are induced from the cell placement; and if hotspots are induced, redistributing room units around the hotspots, and returning to the step of local cell replacement, routing and timing analysis.