Patent ID: 8117584

Claim:
A method of implementing low equivalent series inductance (ESL) and controlled equivalent series resistance (ESR) of a multi-layer chip capacitor, the multi-layer chip capacitor comprising a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, external electrodes and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked, the method comprising: setting an average value of the total number of leads that are to be included in two adjacently disposed internal electrodes facing each other within the block to be smaller than the total number of the external electrodes of the multi-layer chip capacitor; determining the number of leads of each of the internal electrodes within the block on the basis of the average value; and determining a lead location of each of the internal electrodes for which the number of leads has been determined, such that leads of adjacently disposed internal electrodes facing each other and respectively having the first polarity and the second polarity are disposed adjacent one another and are connected with external electrodes having first polarity and second polarity respectively.