Patent ID: 8400812

Claim:
A semiconductor memory device comprising: a memory array including: a plurality of memory cells arranged on a substrate in a matrix state; a plurality of word lines, each of the word lines commonly connected to the memory cells in a common row among the plurality of memory cells; and a plurality of bit lines, each of the bit lines commonly connected to the memory cells in a common column among the plurality of memory cells, a first block, a second block, and a third block being set in the order along the bit line and including the plurality of memory cells; and a peripheral circuit including: a transistor group formed on the substrate having: a first transfer transistor, one of a source and a drain of the first transfer transistor being connected to a part of the word lines belonging to the first block; a second transfer transistor, one of a source and a drain of the second transfer transistor being connected to a part of the word lines belonging to the second block; and a third transfer transistor, one of a source and a drain of the third transfer transistor being connected to a part of the word lines belonging to the third block, the first transfer transistor, the second transfer transistor, and the third transfer transistor sharing one other of the source and the drain, and a direction connecting the source to the drain in each of the first transfer transistor, the second transfer transistor, and the third transfer transistor being different from each other by 90° or 180°.