Patent ID: 8732632

Claim:
A method of generating a reduced gate level model for a circuit design, comprising: providing, in a memory of a computer system that hosts a test synthesis or ATPG environment, a circuit design having a plurality of logic cores, a plurality of wrapper cells, and controller logic, wherein the plurality of wrapper cells comprise a plurality of boundary logic, including state elements, and are serially-controllable and arranged in a plurality of wrapper chains having a plurality of scan input and output ports, wherein each wrapper cell of the plurality of wrapper cells has one or more input ports and one or more output ports, wherein each logic core is wrapped with one or more wrapper chains of the plurality of wrapper chains, and wherein the controller logic is designed to transmit a plurality of test control signals to the plurality of wrapper cells and their wrapper chains; identifying, for each of one or more test modes defined for the logic core, the plurality of wrapper cells for each input and output port of the plurality of input and output ports for each wrapper chain; performing, for each of the one or more test modes, a plurality of structural traces on the plurality of wrapper chains, including logic core input ports and logic core output ports, to identify boundary logic and controller logic associated with each logic core; extracting, for each of the one or more test modes, the boundary logic and the controller logic; and building a model for the plurality of logic cores, stored in the memory of the computer system, based on the extracted boundary logic and the extracted controller logic.