Patent ID: 7537959

Claim:
A method for manufacturing chip stack packages, comprising: providing at least two wafers, each wafer having a front side and a back side, a plurality of chips formed on the front side of the wafer, the chips including circuitry and chip pads arranged within a device periphery, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes adjacent to the device periphery of each chip; forming connection vias by filling the via holes with metal; establishing electrical connections between the chip pads and corresponding connection vias; removing a thickness of material from the back sides of the wafers to form thinned wafers, the removed thickness being sufficient to expose lower surfaces of the connection vias on the thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane while leaving intact the peripheral portions of the scribe lanes; attaching a first plurality of individual chips to a test wafer whereby the connection vias of the first plurality of individual chips are electrically connected to corresponding substrate terminals provided on the test wafer; performing first wafer-level tests on the first plurality of individual chips through contacts provided on the test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures, wherein the connection vias of the second plurality of individual chips are electrically connected to corresponding connection vias of the first plurality of individual chips; performing first or second wafer-level tests on the second plurality of individual chips through the contacts provided on the test wafer; encapsulating the plurality of chip stack structures with a protective encapsulant; and separating the plurality of chip stack structures to form individual chip stack packages.