Patent ID: 7541616

Claim:
A semiconductor memory cell array, comprising: a plurality of dynamic random access memory cells arranged in a matrix of rows and columns, each dynamic random access memory cell includes at least one transistor having: a first region; a second region; a body region disposed between the first region and the second region, wherein the body region is electrically floating; and a gate spaced apart from, and capacitively coupled to, the body region; wherein each memory cell stores at least one data state including (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and wherein: the first region of the transistor of each memory cell corresponding to a first row of dynamic random access memory cells is connected to a first source line, the first region of the transistor of each memory cell corresponding to a second row of dynamic random access memory cells is connected to a second source line, and the first region of the transistor of each memory cell corresponding to a third row of dynamic random access memory cells is connected to the first source line; wherein the first row of memory cells is adjacent to both the second and third rows of memory cells; and wherein the second region of the transistor of each memory cell of the first row of dynamic random access memory cells shares the second region with the transistor of an adjacent memory cell of the second row of dynamic random access memory cells.