Patent ID: 7133992

Claim:
A burst mode counter for use with a memory device having an odd memory array designated by an odd column address and an even memory array designated by an even column address, the burst mode counter comprising: a column address counter changing count responsive to a digital signal, the counter further including a counter control input terminal receiving a counter control signal having a first value causing the counter to increment responsive to the digital signal or a second value causing the counter to decrement responsive to the digital signal; and a counter control circuit receiving a mode signal having a first value indicative of a serial mode of operation and a second value indicative of an interleave mode of operation, the counter control circuit further receiving the least significant bit (“LSB”) and the next to least significant bit (“NLSB”) of a starting column address, the counter control circuit being operable to decode a value of “1” for the LSB and the first value of the mode signal and to generate the second value of the counter control signal responsive thereto, to decode a value of “1” for the NLSB and the second value of the mode signal and to generate the second value of the counter control signal responsive thereto.