Patent ID: 7165206

Claim:
An SRAM-compatible memory including a plurality of memory banks each having a plurality of DRAM cells arranged in a matrix form defined by rows and columns, the DRAM cells interfacing with an external system which does not provide a separate timing period for performing a refresh operation for the DRAM cells, comprising: the memory banks for receiving and storing input data externally provided, the memory banks generating bank information signals each indicating whether a corresponding memory bank is subjected to an invalid read-access; a parity generator for receiving the input data to generate input parity, the input parity being determined based on the input data and a preset parity value; a parity bank for storing the input parity and generating a parity bank information signal indicating whether the parity bank is subjected to the invalid read-access; a refresher timer generating a refresh request signal periodically to activate the refresh operation for both the memory banks and the parity bank; and a data corrector receiving the bank information signals and fetched data from the memory banks and generating output data having same value as the input data by correcting data fetched from a memory bank subjected to the invalid read-access if a checked parity value is different from the preset parity value, the checked parity value being obtained using the fetched data provided from the memory banks and parity data fetched from the parity bank, wherein the data corrector comprises: a bank data control unit for receiving the bank information signals and the fetched data to provide bank control data, any of the bank control data corresponding to fetched data provided from any of the memory banks subjected to the invalid read-access has a first logic value; a parity data control unit for receiving the parity information signal and the parity data fetched from the parity bank to provide parity control data; a discriminating unit for receiving the bank control data and the parity control data and providing discrimination data having a second logic value contrary to the first logical value if the fetched parity data is different from the input parity; and a selecting unit for selecting the bank control data or the discrimination data in response to the bank information signals to generate the output data, wherein the refresh operation is independently performed with respect to the respective memory banks, and is prevented from being simultaneously performed with respect to two or more memory banks.