Patent ID: 7531413

Claim:
A method comprising: forming a device isolation layer on a semiconductor substrate to define at least one active region; forming a channel region in a predetermined portion of the at least one active region; forming two channel portion holes that extend downward from a main surface of the semiconductor substrate and that have the channel region between the two channel portion holes and contact the channel region through sidewalls of the two channel portion holes; forming first gate patterns at the active region such that first gate patterns respectively and sufficiently fill the channel portion holes and extend upward and downward from the main surface of the semiconductor substrate, the first gate patterns crossing the at least one active region; forming second gate patterns disposed on the device isolation layer; and forming shallow impurity regions in the at least one active region of the semiconductor substrate between the gate patterns, the shallow impurity regions in contact with the main surface of the semiconductor substrate, with one of the shallow impurity regions in contact with the channel region, wherein a lowermost portion of the channel region is above bottom surfaces of the two channel portion holes, and wherein the channel region is only between the first gate patterns.