Patent ID: 6937523

Claim:
A method for sensing a programmed/erased state of a selected non-volatile memory (NVM) cell within a memory array, the memory array including a first bit line connected to a first terminal of the selected NVM cell, a second bit line connected to a second terminal of the selected NVM cell, a second NVM cell having a first terminal connected to the second bit line, and a third bit line connected to a second terminal of the second NVM cell, the method comprising: during a first phase, coupling the first bit line to a first voltage source having a first non-zero voltage level, and coupling the second and third bit lines to a ground source; during a second phase beginning at an end of the first phase: decoupling the second bit line from the ground source, whereby a sensed cell signal develops on the second bit in response to a cell current passing through the selected NVM cell from the first bit line, and decoupling the third bit line from the ground source, and then coupling the third bit line to a current source such that a forced neighbor signal is generated on the third bit line; and during a third phase subsequent to the second phase and before the sensed cell signal is stabilized, comparing the sensed cell signal generated on the second bit line with a reference signal to determine the programmed/erased state of the selected NVM cell.