Patent ID: 8174478

Claim:
A gate driving circuit comprising n+1 stages connected to each other in series (n is a constant number larger than 2), each stage comprising: a pull-up part to pull up a present gate signal to a first clock during a first period within one frame and to output the present gate signal to an output terminal; a carry part to pull up a present carry signal to the first clock during the first period and to output the present carry signal to a carry terminal; a pull-down part to receive a next gate signal from a next stage to discharge the present gate signal to a source power voltage; a pull-up driving part to receive a previous carry signal from a previous stage to turn on the pull-up part and the carry part, and to turn off the pull-up part and the carry part in response to the next gate signal, the pull-up driving part being connected to a Q-node comprising a control terminal of the carry part and a control terminal of the pull-up part; a holding part to maintain the present gate signal at the source power voltage; a first floating preventing part connected between the output terminal of the pull-up part and the carry terminal of the carry part; and an inverter to turn the holding part and the first floating preventing part on or off in response to the first clock; and wherein the first floating preventing part resets the carry terminal of the carry part in response to an output signal from the inverter during a second period within the one frame to prevent a Q-node of the next stage from being floated, and the second period does not include the first period.