Patent ID: 8354722

Claim:
A circuit for protecting an integrated circuit from an electrostatic discharge (ESD) event, the circuit comprising: a first well of a first conductivity type; a second well of a second conductivity type, the second well defining a p-n junction with the first well; a first field-effect transistor including a drain in the first well, a source in the first well, and a gate; a doped region of the first conductivity type in the second well; a first pad electrically coupled to the doped region; a second pad electrically coupled to the source of the first field-effect transistor; and a trigger circuit having a first output electrically coupled to the second well and a second output electrically coupled to the first well and to the gate of the first field-effect transistor, the trigger circuit configured to respond to the ESD event at the first pad by outputting a first trigger signal from the first output to the second well and outputting a second trigger signal from the second output to the first well and to the gate of the first field-effect transistor, wherein the first trigger signal and the second trigger signal cause the ESD event to be directed from the first pad through the doped region, the second well, the first well, and the source of the first field-effect transistor to the second pad.