Patent ID: 8487862

Claim:
A shift register comprising: a plurality of first shift register units outputting a plurality of first shift signals, two adjacent first shift register units respectively receiving a first clock signal and a second clock signal, the second clock signal being inverse to the first clock signal; and a plurality of second shift register units outputting a plurality of second shift signals, two adjacent second shift register units respectively receiving a third clock signal and a fourth clock signal, the third clock signal being inverse to the fourth clock signal and being different from the first clock signal by half a period; wherein each of the first shift register units and each of the second shift register units includes a cascade data input terminal, a cascade data output terminal, a first output terminal used to output a corresponding first or second shift signal, a feedback terminal, and a reset terminal; the second shift signal of an Mth second shift register unit is fed back to the feedback terminal of an (N+1)th first shift register unit, the first shift signal of an Nth first shift register unit is fed back to the feedback terminal of the Mth second shift register unit, M is a natural number equal to N, and the reset terminal and the cascade data output terminal of the Nth first shift register unit are connected to the first output terminal and the cascade data input terminal of the (N+1)th first shift register unit, respectively; the reset terminal and the cascade data output terminal of the Mth second shift register unit are connected to the first output terminal and the cascade data input terminal of an (M+1)th first shift register unit, respectively; when the cascade data input terminal of the Nth first shift register unit receives an initial voltage signal, the Nth first shift register unit outputs one of the first shift signals synchronous to the first clock signal, and the (N+1)th first shift register unit outputs another one of the first shift signals synchronous to the second clock signal; and meanwhile, the reset terminal of the Nth first shift register unit determines whether to reset the Nth first shift register unit according to the other one of the first shift signals output from the (N+1)th first shift register unit; and when the cascade data input terminal of the Mth second shift register unit receives the initial voltage signal, the Mth second shift register unit outputs one of the second shift signals synchronous to the third clock signal, and the (M+1)th second shift register unit outputs another one of the second shift signals synchronous to the fourth clock signal; and meanwhile, the reset terminal of the Mth second shift register unit determines whether to reset the Mth second shift register unit according to the other one of the second shift signals output from the (M+1)th second shift register unit.