Patent ID: 7487295

Claim:
1 . A memory control device comprising: a secondary cache that stores data stored in a main storage and address information corresponding to the data; a primary cache that stores data of the secondary cache and address information corresponding to the data; a secondary cache buffer that holds address information as a request of the secondary cache for reference to data stored in the main storage; a primary cache buffer that holds address information as a request of the primary cache for reference to data of the secondary cache; and a central processor that controls the cache in referring to data stored in the main storage, wherein the central processor includes a thread identification information obtaining unit that requests for reference to data stored in the main storage for each of a plurality of threads, and obtains thread identification information for each of the threads; a valid buffer detector that detects number of cache buffers in the primary cache buffer that hold reference requests for each thread based on the thread identification information; and a buffer controller that controls to hold the reference requests in the primary cache buffer such that the number of cache buffers detected for each thread does not exceed a predetermined number and an exclusive use of the primary cache buffer by a particular thread is prohibited, wherein the memory control device further comprises a reference request transfer port as a buffer that transfers the reference requests from the primary cache to the secondary cache, wherein when there is no room in the primary cache buffer for a reference request other than reference requests that are controlled to be held in the cache buffer, the buffer controller controls to hold in the primary cache buffer, the reference request that is controlled to be held in the cache buffer, transfers the reference requests other than reference requests that are controlled to be held in the cache buffer from the primary cache to the secondary cache using the reference request transfer port, and makes the reference request transfer port start to store data stored in the main storage in the secondary cache as well as deters the primary cache from storing data from the secondary cache, and when there is room in the primary cache buffer after the reference request transfer port starts to store the data in the secondary cache, the buffer controller requests to store the data stored in the secondary cache in the primary cache via the primary cache buffer.