Patent ID: 7482848

Claim:
A clock generation circuit, comprising: a first delay circuit that is responsive to a first clock signal; a coarse locking circuit that includes at least one analog synchronous mirror delay circuit, the coarse locking circuit responsive to an output from the first delay circuit and to the first clock signal; a voltage controlled delay circuit that is responsive to an output of the coarse locking circuit and to a voltage control signal; a second delay circuit that is responsive to an output of the voltage controlled delay circuit; a fine locking circuit that is responsive to an output of the second delay circuit and the first clock signal that is configured to generate the voltage control signal; a third delay circuit responsive to the output of the voltage controlled delay circuit; and a fourth delay circuit that is configured to generate the first clock signal from an external clock signal, wherein the first delay circuit is configured to delay the first clock signal by a first mirror delay time that is equal to the sum of a first transmission delay time, a second transmission delay time and a third transmission delay time, wherein the voltage controlled delay circuit is configured to delay the output of the coarse locking circuit by the second transmission delay time, wherein the second delay circuit is configured to delay the output of the voltage controlled delay circuit by a second mirror delay time that is equal to the sum of the first transmission delay time and the third transmission delay time, wherein the third delay circuit is configured to delay the output of the voltage controlled delay circuit by the third transmission delay time, and wherein the fourth delay circuit is configured to delay the external clock signal by the first transmission delay time to generate the first clock signal.