Patent ID: 8830152

Claim:
A liquid crystal display device comprising: a plurality of pixels that are arranged in columns and rows to form a matrix pattern, each of the plurality of pixels including first and second subpixels, the first subpixel exhibiting a higher luminance than the second subpixel at least at a particular grayscale; a plurality of source bus lines, each of which is associated with one of the columns of pixels; a plurality of gate bus lines, each of which is associated with one of the rows of pixels; a plurality of TFTs, each of which is associated with one of the first and second subpixels that each said pixel has; and a plurality of first storage capacitor bus lines, each of which is associated with the first subpixel of one of the pixels, wherein the first subpixel includes: a liquid crystal capacitor which is formed by a first subpixel electrode, a liquid crystal layer, and a counter electrode that faces the first subpixel electrode via the liquid crystal layer; and a first storage capacitor which is formed by a first storage capacitor electrode that is electrically connected to the first subpixel electrode, an insulating layer, and a first storage capacitor counter electrode that faces the first storage capacitor electrode via the insulating layer, the second subpixel includes a liquid crystal capacitor that is formed by a second subpixel electrode and a counter electrode that faces the second subpixel electrode via the liquid crystal layer, a first storage capacitor signal voltage that is applied to the first storage capacitor counter electrode through its associated first storage capacitor bus line is an oscillation voltage, of which one period is shorter than one vertical scanning period, and has at least three potentials including first and second potentials that define a maximum amplitude and a third potential between the first and second potentials, and the first storage capacitor signal voltage supplied to a respective first storage capacitor bus line associated with a respective one of the rows of pixels is at the third potential when a gate signal voltage that is supplied to the gate bus line associated with the respective one of the rows of pixels, and that has been high, goes low.