Patent ID: 8294196

Claim:
A non-volatile memory comprising: source and drain regions located in a transistor body region, the source and drain regions are laterally spaced apart to form a channel region therebetween; a control gate isolated from and located vertically above the channel region; a multilayer charge trapping dielectric between the control gate and the channel region to trap positively charged holes, wherein the multilayer charge trapping dielectric comprises at least one layer of high-K dielectric having a dielectric constant (K) greater than dielectric constants of silicon nitride; a discrete bi-polar junction substantially underlying the channel region, the discrete bi-polar junction coupled to a terminal and configured to operatively inject holes across the discrete bi-polar junction such that hole injection occurs into the multilayer charge trapping dielectric; and program circuitry to program the multilayer charge trapping dielectric, the program circuitry arranged to provide a voltage difference across the discrete bi-polar junction to uniformly inject holes across the discrete bi-polar junction such that the hole injection occurs into the at least one layer of high-K dielectric by applying a positive voltage to the terminal and a negative voltage to the control gate.