Patent ID: 8669613

Claim:
A semiconductor device die with integrated metal oxide semiconductor field effect transistor (MOSFET) and diode-connected enhancement mode JFET, the semiconductor device die comprising: a lower common semiconductor substrate region (CSSR) of type-1 conductivity; a MOSFET device region, located at the top of the CSSR, having: the CSSR as its MOSFET drain region; at least a MOSFET body region of type-2 conductivity, a MOSFET gate region and a MOSFET source region of type-1 conductivity located at the top of the MOSFET drain region; and a diode-connected enhancement mode JFET (DCE-JFET) device region, located at the top of the CSSR, having: the CSSR as its DCE-JFET drain region; at least two DCE-JFET gate regions of type-2 conductivity located at the top of the DCE-JFET drain region and laterally separated from each other along the major CSSR plane with a DCE-JFET gate spacing; at least a DCE-JFET source region of type-1 conductivity located at the top of the CSSR and between the DCE-JFET gate regions, wherein the DCE-JFET source region is shorted to the DCE-JFET gate regions; and whereby the CSSR serially connects the MOSFET device drain region to the DCE-JFET device drain region.