Patent ID: 8841648

Claim:
A memory array comprising: a first memory cell having: a first conductive line; a first bipolar storage element formed above the first conductive line; a second conductive line formed above the first bipolar storage element; and a first steering element disposed above or below the first bipolar storage element; and a second memory cell formed above the first memory cell and having: a second bipolar storage element formed above the second conductive line; a third conductive line formed above the second bipolar storage element; and a second steering element disposed above or below the second bipolar storage element; wherein the first and second memory cells share the second conductive line; wherein the first bipolar storage element has a first storage element polarity orientation within the first memory cell; wherein the second bipolar storage element has a second storage element polarity orientation within the second memory cell; wherein the second storage element polarity orientation is opposite the first storage element polarity orientation; wherein the first bipolar storage element comprises a first semiconductor material layer, and the first steering element comprises the first semiconductor material layer; and wherein the second bipolar storage element comprises a second semiconductor material layer, and the second steering element comprises the second semiconductor material layer.