Patent ID: 7158920

Claim:
A noise checking method for performing, after carrying out cell arrangement and inter cell wiring in an integrated circuit, static noise checking on a result of the cell arrangement and the inter-cell wiring, said method comprising: a timing analyzing step, in which a timing chart of signal transfer on each wire is obtained by performing delay simulation with timing analysis based on the result of the cell arrangement and the inter-cell wiring; a noise value calculating step, in which a noise value is calculated, said noise value representing a degree at which at least one affecting wire (hereinafter will be called the “aggressor”), running in parallel with an object wire (hereinafter will be called the “victim”) to be checked, induces noise onto the victim; a noise value evaluating step, in which it is evaluated whether or not the noise value calculated at said noise value calculating step exceeds a limit value; and an error evaluating step, in which, if it is evaluated at said noise value evaluating step that the noise value is greater than the limit value, comparison is performed, based on the timing chart obtained at said timing analyzing step, between a last edge appearance timing in a signal waveform transmitted on the victim and a last edge appearance timing in a signal waveform transmitted on the aggressor, and then a decision is made on a noise value error in the victim based on the comparison result.