Patent ID: 6953715

Claim:
A method of controlling a capacitance of a TFT-LCD storage capacitor, comprising: forming a gate and a bottom electrode on a transparent substrate; sequentially forming a dielectric layer and a silicon nitride layer on the transparent substrate; forming an undoped amorphous silicon layer on the silicon nitride layer; forming an etching mask on the undoped amorphous silicon layer; sequentially forming a doped amorphous silicon layers and a conductive layer on a the undoped amorphous silicon layer and the etching mask, wherein an etching selectivity ratio of the undoped and doped amorphous silicon layers over the dielectric layer is not less than about 5.0; sequentially patterning the conductive layer and the doped amorphous silicon layer to form a source and a drain on either side of the gate, the undoped amorphous silicon layer serving as a channel between the source and the drain; forming a passivation layer over the transparent substrate, the passivation layer comprising a contact window to expose the source or the drain; and forming a pixel electrode on the passivation layer, the pixel electrode connecting the exposed source or drain electrically through the contact window, and an overlap between the pixel electrode and the bottom electrode forming a storage capacitor.