Patent ID: 8713549

Claim:
A computer implemented method for vectorization of a program loop, the method comprising: receiving a program loop as input, wherein the program loop accesses one or more sets of memory addresses and each set of memory addresses is associated with a potential independent misalignment; and converting the program loop into at least a selective loop and a vector loop, wherein the selective loop is comprised of a prologue loop and an epilogue loop in the program loop, wherein the selective loop performs a conditional leaping address incrementation for each set of memory addresses so that memory addresses accessed by the vector loop are aligned, wherein the vector loop simultaneously accesses a certain number of memory addresses in each set of memory addresses per iteration, and wherein the conditional leaping address incrementation comprises: incrementing a memory address in a first subset of memory addresses; determining whether the memory address is aligned; and incrementing the memory address by a number of memory addresses in a second subset of memory addresses, in response to determining that the memory address is aligned, wherein for the selective loop a number of iterations during execution of the selective loop is known at compile-time, such that a number of loops whose number of iterations will remain a compile time known constant is maximized, and wherein the number of iterations during execution of the prologue loop and the epilogue loop is unknown.