Patent ID: 7636003

Claim:
A limiting amplifier, comprising: an input stage with dc offset cancellation, receiving a differential input signal and outputting a first intermediate differential signal; gain stages, cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal; an output buffer, amplifying the second intermediate differential signal to produce an output signal; and a feedback filter providing a dc offset voltage of the output signal to the input stage for the dc offset cancellation; wherein the input stage comprises a resistor network connected between a pair of input nodes and a power line, the resistor network comprises: a common resistor connected to the power line; a pair of load resistors sharing a common terminal connected to the common resistor; and a shunt resistor with two terminals respectively connected to the load resistors, wherein the input stage further comprises a pair of center-tapped inductors, each connected between a corresponding input node and a corresponding load resistor and providing a center tap for outputting the first intermediate differential signal.