Patent ID: 8383950

Claim:
A method of fabricating a substrate comprising: forming a first etch stop metal protected circuit pattern on a first carrier comprising: patterning a photoresist layer on the first carrier to form a patterned photoresist layer, the patterned photoresist layer comprising circuit pattern artifacts; plating a first patterned etch stop layer on the first carrier and within the circuit pattern artifacts using the first carrier as an electroplating electrode; and plating a first patterned conductor layer on the first patterned etch stop layer and within the circuit pattern artifacts using the first carrier as an electroplating electrode, wherein the first patterned etch stop layer and the first patterned conductor layer form the first etch stop metal protected circuit pattern; forming a second etch stop metal protected circuit pattern on a second carrier; simultaneously laminating the first etch stop metal protected circuit pattern to a first surface of a dielectric layer and the second etch stop metal protected circuit pattern to a second surface of the dielectric layer; forming via apertures between the first etch stop metal protected circuit pattern and the second etch stop metal protected circuit pattern; and forming electrically conductive vias in the via apertures.