Patent ID: 8904046

Claim:
An apparatus for processing a serial input (SI) including command, address and data in accordance with at least one pre-defined sequence and grouped as input bit streams representing the command, address and data and for accessing a memory for data processing, the apparatus comprising: a temporary holding circuit for temporarily storing the address bit streams of the SI, wherein the temporary holding circuit comprises J temporary registers that are serially connected, so that one register forwards its stored bit stream to the next register; an address register circuit for storing the address bit streams temporarily stored in the temporary holding circuit to access the memory, wherein the address register circuit comprises J address registers for storing the address transferred from the J temporary registers, J being an integer greater than one; an interpreting circuit for interpreting the command of the SI, independently of the address bit streams being temporarily held by the temporary holding circuit; and a determination circuit for determining which of the temporarily stored address bit streams corresponds to row address information or column address information, in response to the interpreted command.