Patent ID: 8645450

Claim:
Multiplier-accumulator circuitry implemented in an integrated circuit device that includes a plurality of instances of general-purpose programmable logic elements and at least one instance of special-purpose circuitry, the multiplier-accumulator circuitry comprising: circuitry for forming a plurality of partial products of multiplier and multiplicand inputs; carry-save adder circuitry for adding together the partial products and another input to produce intermediate sum and carry outputs; final adder circuitry for adding together the intermediate sum and carry outputs to produce a final output having no more bits than the maximum number of bits required for one multiplier-multiplicand product; and feedback circuitry for applying the final output to the carry-save adder circuitry as said another input for accumulating the final output; and accumulator-overflow circuitry for accumulating overflow from the final adder circuitry beyond the maximum number of bits from the adding of the intermediate sum and carry outputs; wherein: said multiplier-accumulator circuitry, other than said accumulator-overflow circuitry, is implemented in the special-purpose circuitry; and said accumulator-overflow circuitry is implemented in the general-purpose logic elements.