Patent ID: 8667225

Claim:
A computing system comprising: a cache; and a prefetch unit, wherein the prefetch unit is configured to: maintain a count of a number of cache misses for both read and write operations corresponding to a given data stream, wherein a data stream corresponds to a plurality of contiguous blocks of data in lower-level memory; detect an access to the given data stream; compare said count to a predetermined threshold; responsive to detecting said access and determining said count has reached the predetermined threshold: prefetch a portion of the given data stream from lower-level memory without write permission, responsive to there having not been an access to the given data stream that requests write permission subsequent to said number of cache misses reaching the predetermined threshold; and prefetch said portion of the given data stream from lower-level memory with write permission, responsive to there having been an access to the given data stream that requests write permission subsequent to said number of cache misses reaching the predetermined threshold.