Patent ID: 7388403

Claim:
A two-stage voltage level shifting module for a plurality of I/O devices having different bias voltages, comprising: a first stage voltage level shifting circuit; a first voltage source coupled to a first voltage input terminal of the first stage voltage level shifting circuit; a second voltage source having an voltage level higher than the voltage level of the first voltage source and being coupled to a second voltage input terminal of the first stage voltage level shifting circuit; a third voltage source having an voltage level higher than the voltage levels of both the first voltage source and the second voltage source; a first P-type MOSFET (metal-oxide-semiconductor field-effect transistor) having a source coupled to the third voltage source; a second P-type MOSFET having a source coupled to the third voltage source, a drain coupled to a gate of the first P-type MOSFET, and a gate coupled to a drain of the first P-type MOSFET; and a second stage voltage level shifting circuit comprising: a third P-type MOSFET having a source coupled to the drain of the first P-type MOSFET; a fourth P-type MOSFET having a source coupled to the drain of the second P-type MOSFET; a fifth P-type MOSFET having a gate coupled to the drain of the third P-type MOSFET, a source coupled to the gate of the second P-type MOSFET, and a drain coupled to the first voltage source; a sixth P-type MOSFET having a gate coupled to the drain of the fourth P-type MOSFET, a source coupled to the gate of the first P-type MOSFET, and a drain coupled to the first voltage source; a first N-type MOSFET having a source coupled to the drain of the fifth P-type MOSFET, a gate coupled to a first signal output terminal of the first stage voltage level shifting circuit, and a drain coupled to the gate of the third P-type MOSFET; a second N-type MOSFET having a source coupled to the drain of the sixth P-type MOSFET, a gate coupled to a second signal output terminal of the first stage voltage shifting circuit, and a drain coupled to the gate of the fourth P-type MOSFET; a seventh P-type MOSFET having a gate coupled to the gate of the first N-type MOSFET, a drain coupled to the drain of the first N-type MOSFET, and a source coupled to the second voltage source; and an eighth P-type MOSFET having a gate coupled to the second N-type MOSFET, a drain coupled to the drain of the second N-type MOSFET, and a source coupled to the second voltage source.