Patent ID: 7910990

Claim:
A semiconductor device comprising: (a) a gate trench formed in a main surface of a semiconductor substrate of a first conductivity type; (b) a gate insulating film formed over an inner wall and a bottom portion of the gate trench; (c) a gate electrode formed so as to fill the gate trench and a portion of which protrudes from the semiconductor substrate, the portion of the gate electrode having a width that is not less than a width of the gate electrode in the gate trench; (d) a side wall formed over a side wall portion of the gate electrode protruding from the semiconductor substrate such that the height of an uppermost portion of the side wall is higher than the height of an uppermost portion of the gate electrode; (e) a first semiconductor region of the first conductivity type serving as a source region and formed in the semiconductor substrate; (f) a second semiconductor region of a second conductivity type opposite to the first conductivity type serving as a channel region and formed in the semiconductor substrate below the first semiconductor region; (g) a body trench formed between said side wall and another said side wall formed over a side wall portion of an adjacent gate electrode by self-alignment with the gate electrodes, so as to be deeper than a depth of the first semiconductor region; (h) a third semiconductor region of the second conductivity type having an impurity concentration greater than an impurity concentration of the second semiconductor region and formed at a bottom portion of the body trench and within the second semiconductor region; and (i) a fourth semiconductor region of the first conductivity type serving as a drain region and formed in a portion opposite to the main surface of the semiconductor substrate.