Patent ID: 7176573

Claim:
A semiconductor device comprising: a semiconductor die having a pad-mounting surface defining a horizontal plane, and a plurality of spaced apart first bonding pads formed on said pad-mounting surface; and a multi-level interconnect structure formed on said pad-mounting surface, and including a first insulating layer formed on said pad-mounting surface and formed with a plurality of first holes, each of which exposes a respective one of said first bonding pads from said pad-mounting surface, a plurality of first level conductive horizontal bodies, each of which has an end section that fills a respective one of said first holes to electrically connect with a respective one of said first bonding pads, and an extension that extends from said end section, that is formed on said first insulating layer, and that has a connecting end horizontally offset from the respective one of said first holes, a second insulating layer formed on said first insulating layer and formed with a plurality of first holes, each of which exposes said connecting end of said extension of a respective one of said first level conductive horizontal bodies from said second insulating layer, and a plurality of second level conductive vertical bodies, each of which fills a respective one of said first holes in said second insulating layer to electrically connect with said connecting end of said extension of a respective one of said first level conductive horizontal bodies, and each of which has a connecting end that extends through the respective one of said first holes in said second insulating layer.