Patent ID: 7504688

Claim:
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a non-volatile memory area including a non-volatile memory cell having a gate electrode including a floating gate, an inter-electrode insulating film and a control gate stacked above said semiconductor substrate and having first insulating side walls formed on side walls of said gate electrode; wherein said control gate comprises a first material and said first insulating side walls comprises a second material; a peripheral circuit area including a transistor having a single-layer gate electrode formed above said semiconductor substrate, said single-layer gate electrode being comprised of said first material; a first border area including: a first isolation region formed in said semiconductor substrate for isolating said non-volatile memory area and said peripheral circuit area; a first residual pattern including an insulating film directly formed on said first isolation region in entire direct contact thereto, and made of a same layer as said inter-electrode insulating film and a single conductive layer formed on said insulating film in direct contact thereto, and a first redundant insulating side wall comprised of a same layer as said first insulating side walls and formed on a side wall of said first residual pattern on a side of said non-volatile memory area; and wherein said floating gate is comprised of a first polysilicon and wherein said first residual pattern is free of said first polysilicon.