Patent ID: 6914292

Claim:
A floating gate field-effect transistor comprising: a source region, a drain region and a channel region; a first electrical insulation layer arranged above the channel region; a floating gate region arranged above the first electrical insulation layer; a second electrical insulation layer arranged above the floating gate region; a gate region arranged above the second electrical insulation layer, wherein the first electrical insulation layer or the second electrical insulation layer having an electrically insulating layer sequence comprising three layers as a triple tunnel barrier adapted such that, for storing charge carriers in the floating gate region or for removing charge carriers from the floating gate region, charge carriers tunnel through the triple tunnel barrier, the electrically insulating layer sequence having a lower layer made of a material having a first relative permittivity, a middle layer made of a material having a second relative permittivity and an upper layer made of a material having a third relative permittivity; and the second relative permittivity being greater than the first relative permittivity and greater than the third relative permittivity; the electrically insulating layer sequence being provided in such a way that a stepped potential profile forms in the funnel barrier, the middle layer having a lower potential barrier than the lower layer and than the upper layer.