Patent ID: 8295309

Claim:
A method, implemented by a processor, for time weighted combining of a plurality of binary phase shift key (BPSK) code sequences, the method comprising: providing a first sequence of chips of a BPSK code having a first code power; providing a second sequence of chips of a BPSK code having a second code power; providing a third sequence of chips of a BPSK code having a third code power; determining a majority vote (MV) sequence of chips from said first, second and third sequences of chips; selecting a specific number of samples from each of said MV sequence of chips, and the two sequences of chips of said first, second and third sequences of chips that have the highest code powers, to form samples in a first unit duration, where the unit duration is able to form a time period that is of a time duration that includes a fraction of one chip if needed, and with the specific numbers of samples selected from each of said MV sequence and said two sequences of chips having the highest code powers being representative of the probabilities of each of said sequences being randomly selected based on their respective gains; and further taking into account a number of the samples used for each of the MV sequence of chips and the two highest code power sequences of chips when numbers of samples of each of the MV sequence of chips and the two highest code power sequences of chips are being determined, to form a second unit duration.