Patent ID: 7023049

Claim:
A semiconductor device, comprising: a semiconductor substrate; a nonvolatile memory cell including a first MOS transistor having a first gate formed on the semiconductor substrate, the first gate being a layered gate structure having a first gate insulating film, a first gate electrode film, a second gate insulating film, a second gate electrode film, an ultra-thin insulating film having a thickness of less than approximately 3 nm, and a third gate electrode film, and a source and a drain formed in the substrate to interpose a surface region of the semiconductor substrate beneath the first gate; and a logic circuit including a plurality of second MOS transistors having a second gate formed on the semiconductor substrate, the second gate being a gate structure having a third gate insulating film, the second gate electrode film, the ultra-thin insulating film having a thickness of less than approximately 3 nm, and the third gate electrode film, and the source and the drain formed in the semiconductor substrate to interpose the surface region of the semiconductor substrate beneath the second gate.