Patent ID: 8653604

Claim:
An integrated circuit die supporting a plurality of transistor device types formed by a process comprising the steps of: doping selected portions of a wafer to form a first plurality of wells of a first conductivity type; doping selected portions of the first plurality of wells to form a first plurality of screen layers of the first conductivity type, the screen layers being disposed closer to a surface of the wafer than the wells, the screen layers being formed using one or more screen layer doses; growing a substantially undoped epitaxial layer over the screen layer to a defined thickness and uniformity; forming source and drain structures for the plurality of transistor device types within the undoped epitaxial layer; doping selected portions of the first plurality of screen layers to introduce diffusion-inhibiting dopant species; outdiffusing dopants from the screen layer into the epitaxial layer using a thermal cycling process, wherein the threshold voltages of each transistor device type of the plurality of transistor device types are differentiated by distance of dopant migration towards the gate; and performing halo implants into predetermined portions of the epitaxial layer in alignment with at least one selected source and drain structure, one or more halo implant doses being used to perform the halo implants; wherein the screen layer has a doping concentration that is greater than a doping concentration of the first plurality of wells; wherein at least some of the transistor devices of the plurality of transistor device types are formed using a discrete and individualized predetermined combination of the one or more screen layer dose and the one or more halo implant dose.