Patent ID: 7385430

Claim:
A data output clock generating circuit for a semiconductor memory apparatus, comprising: a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock to generate a rising data output clock wherein the rising data output clock generating unit includes: a rising clock extraction signal generating section receiving the rising output enable signal and the falling clock and generating the rising clock extraction signal, the rising clock extraction signal being enabled at a time of a first rising edge of the falling clock after the rising output enable signal is enabled and being disabled at a time of a first rising edge of the falling clock after the rising output enable signal is disabled; and a rising data output clock generating section receiving the rising clock extraction signal and the rising clock and extracting the rising clock during a period when the rising clock extraction signal is enabled to generate and output the rising data output clock; and a falling data output clock generating unit configured to combine the falling clock with a falling clock extraction signal generated in response to a falling output enable signal and the rising clock to generate a falling data output clock wherein the rising data output clock generating unit and the falling data output clock generating unit are independently driven in parallel.