Patent ID: 8604949

Claim:
A serial-to-parallel converter, comprising: n input latching elements, INL 1 , INL 2 , . . . INL n , configured to sample n successive data of a serial input data stream, respectively; k intermediate latching elements, IL 1 , IL 2 , . . . IL k , configured to sample outputs of a first k input latching elements, INL 1 , INL 2 , . . . INL k , of the n input latching elements, respectively, after a first k data of the n successive data have been sampled by the first k input latching elements, and before a final data of the n successive data has been sampled by the nth input latching element, INL n , and n output latching elements, OL 1 , OL 2 , . . . , OL n , configured to sample outputs of the k intermediate latching elements and a remaining (n−k) input latching elements, INL k+1 , . . . INL n−1 , INL n , of the n input latching elements, respectively, after the nth data of the n successive data has been sampled by the nth input latching element, INL n , and before the kth data of a next n successive data in the serial input data stream has been sampled by the kth input latching element, IN k , wherein the n input latching elements and the k intermediate latching elements are transparent for one state of their clock input, and n and k are positive integers, where n>k.