Patent ID: 8139615

Claim:
A data processing apparatus which performs demultiplexing of multi-channel data into a first channel data group and a second channel data group and outputs them into a bus, the apparatus comprising: a channel demultiplexing circuit; a memory which stores multi-channel data containing a pair of first channel data and second channel data for a predetermined cycle; and a memory controller which sequentially reads out the multi-channel data from the memory for the predetermined cycle and transfers the read multi-channel data to the channel demultiplexing circuit through the bus, wherein the channel demultiplexing circuit includes: a first delay circuit which delays the first channel data only of the multi-channel data transferred from the memory controller for the predetermined cycle and outputs the first delayed channel data; a second delay circuit which delays the second channel data only of the multi-channel data transferred from the memory controller by the predetermined cycle and outputs the second delayed channel data; a channel data holding circuit which stores first coupled data obtained by coupling the first channel data and the first delayed channel data for the multiple predetermined cycles and stores second coupled data obtained by coupling the second channel data and output of the second delayed circuit for the multiple predetermined cycles; and a selective output circuit which selectively reads out the first channel data group and the second channel data group from the channel data holding circuit to output to the bus.