Patent ID: 8589654

Claim:
A memory system comprising: a memory device; a memory interface configured to access the memory device; and a plurality of data signal lines configured to connect the memory device and the memory interface, wherein the memory device includes: a memory device controller configured to control an inner portion of the memory device based on an access from the memory interface; a memory cell configured to store data; a delay adjustment storage unit configured to store timing adjustment data which is used to adjust timing of data and a strobe signal; and a selector configured to select either a path to or from the delay adjustment storage unit or a path to or from the memory cell, as a path from or to the memory interface. the memory interface reads out data 0 at a rise of a strobe signal output from the memory device at a first timing, data 1 at a rise of the strobe signal at a second timing before or after the first timing, data 0 at a fall of the strobe signal at a third timing and data 1 at a fall of the strobe signal at a fourth timing before or after the third timing, as the timing adjustment data, via each of the plurality of data signal lines, and the memory interface searches for a timing range within which the data can be read out while changing timing of reading of the timing adjustment data from the delay adjustment storage unit, and selects and sets timing of reading of the data from the timing range.