Patent ID: 8405450

Claim:
A circuit, comprising: a charge pump having an input terminal, an output terminal, a first enable terminal, and a second enable terminal, the charge pump further including: at least a first charge-pump stage and a second charge-pump stage electrically coupled together at an intermediate node, the first charge-pump stage coupled to the input terminal and the first and second enable terminals, the second charge-pump stage coupled to the output terminal and the first and second enable terminals, the first charge-pump stage having: a first pump capacitor electrically coupled between the first enable terminal and a first internal node; a second pump capacitor electrically coupled between the second enable terminal and a second internal node; a first pump transistor electrically coupled between the first internal node and the intermediate node, and having a first control terminal; and a second pump transistor electrically coupled between the second internal node and the intermediate node, and having a second control terminal; the second charge-pump stage having: a third pump capacitor electrically coupled between the second enable terminal and a third internal node; a fourth pump capacitor electrically coupled between the first enable terminal and a fourth internal node; a third pump transistor electrically coupled between the first internal node and the intermediate node and having a third control terminal; and a fourth pump transistor electrically coupled between the second internal node and the intermediate node and having a fourth control terminal; a first stabilizing stage electrically coupled to the first charge-pump stage and including: a first biasing capacitor electrically coupled between the first control terminal of the first pump transistor and the second enable terminal; a second biasing capacitor electrically coupled between the second control terminal of the second pump transistor and the first enable terminal; and a first equalization circuit electrically coupled between the first and the second control terminals of the first and second pump transistors, respectively, and configured to limit a first voltage between the first and the second control terminals within a first range of values, the first equalization circuit including a first series circuit and a second series circuit, the first series circuit including a first number N t1 of first voltage-controlled switches coupled in series to one another, the second series circuit including a second number of second voltage-controlled switches coupled in series to one another, the first series circuit and the second series circuit being coupled in parallel with reverse polarities.