Patent ID: 8804427

Claim:
A nonvolatile semiconductor memory device, comprising: a plurality of memory units including a plurality of memory cells, the plurality of memory cells being stacked above a substrate; the plurality of memory units including a first memory unit and a second memory unit, the first memory unit including a first memory cell, a second memory cell and a first transistor; a first line electrically connected to a first end of the first memory unit and a first end of the second memory unit, the first line being electrically connected to a first end of the first transistor; a second line electrically connected to a second end of the first memory unit; a third line electrically connected to a second end of the second memory unit; and a controller configured to perform a read operation for the first memory cell on the condition that a first voltage is applied to the second line, a second voltage is applied to the third line, the first voltage is higher than the second voltage, and a third voltage is applied to a gate of the first memory cell, the controller configured to perform an erase operation on the condition that a fourth voltage is applied to the second line, a fifth voltage is applied to the third line, and the fourth voltage is different from the fifth voltage.