Patent ID: 7676661

Claim:
A method of accelerating software functions on a processor, comprising the steps of: feeding a plurality of inputs into a processor implemented on a field programmable gate array (FPGA) from an accelerator module via a first configurable uni-directional serial link (first link) formed from a first-in-first-out streaming communication network; wherein the accelerator module implements a function in hardware on the FPGA; wherein the first link is a communication channel dedicated to serial communication from the accelerator module to the processor; wherein a data value put by the accelerator module on the first link in one clock cycle is available for the processor to read in the immediate next clock cycle; executing by the processor a single first instruction that reads input data from the first link; executing by the processor a single second instruction that writes output data to a second configurable uni-directional serial link (second link) formed from a first-in-first-out streaming communication network; wherein the second link is a communication channel dedicated to serial communication from the processor to the accelerator module; wherein the first and second links are implemented on the FPGA; wherein a data value written by the processor to the second link in one clock cycle is available for the accelerator module to read in the immediate next clock cycle; extracting a plurality of outputs from the processor via the accelerator module via the second link; wherein the step of feeding comprises a step of feeding at least two or more parallel sequences of input values and the step of extracting comprises computing two or more parallel sequences of outputs; and wherein the feeding and extracting occur within a single clock cycle of the processor.