Patent ID: 8169262

Claim:
A method for reducing an offset voltage of an operational amplifier, comprising: receiving a positive input voltage and a negative input voltage via a positive differential input terminal and a negative differential input terminal of an input stage circuit; amplifying the positive input voltage and the negative input voltage to output a first positive output voltage and a first negative output voltage at a first node and a second node of the input stage circuit; generating a reference positive output voltage equal to the first positive output voltage at a third node according to the positive input voltage and the negative input voltage with a feedback circuit; equally amplifying the first negative output voltage and the reference positive output voltage to generate a second positive output voltage at a fourth node and a second negative output voltage at a fifth node with a fixed stage circuit; and generating an output voltage at an output terminal according to a difference voltage between the second positive output voltage and a second negative voltage with an output stage circuit, wherein the fixed stage circuit has a symmetrical circuit structure to clamp offset voltages of the second node and the third node at the same level.