Patent ID: 7003647

Claim:
A method for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory comprising the steps of: providing a page table with page table entries (PTEs) for mapping multiple sized pages from a virtual address space to a physical address space, each of said multiple sized pages being a multiple of a base page size; for a region of contiguous memory having a virtual address and length, dividing said memory region into a minimum number of largest natural blocks based upon alignment and size for said memory region including truncating said virtual address to a base page size boundary for identifying a buffer beginning virtual address for said memory region; and identifying a base PTE for the identified buffer beginning virtual address; assigning PTEs to map said natural blocks; multiple identical PTEs being assigned for each of said natural blocks greater than said base page size; and using one TLB entry to map each of said largest natural blocks.