Patent ID: 7259426

Claim:
A semiconductor device comprising: a first semiconductor layer including: a semiconductor pillar region having a first semiconductor pillar region of a first conductivity type and a second semiconductor pillar region of a second conductivity type, the first semiconductor pillar region and the second semiconductor pillar region being formed alternately according to a predetermined successive pattern; a semiconductor base region of a second conductivity type, each of the first and second semiconductor pillar regions being electrically connected with the semiconductor base region; a first major electrode region of a first conductivity type selectively provided on the semiconductor base region; and a second major electrode region connected with at least the first semiconductor pillar region; a control electrode configured to control a current between the first major electrode region and the second major electrode region; and an electrode pad provided on a pad formation part of the first semiconductor layer via an insulator and connected with the control electrode, the pad formation part including a successive pattern nonformation part where the predetermined successive pattern of the semiconductor pillar region is not formed.