Patent ID: 6910121

Claim:
A method comprising: providing a reorder buffer comprising a plurality of entries associated respectively with a plurality of instructions; executing a first instruction of said plurality of instructions which generates a first register value for a first real register, said first register value being stored in a first alias register identified in a first entry of said reorder buffer associate with said first instruction; determining whether said first register value should be copied from said first alias register to said first real register approximately at a time when first entry of said reorder buffer is needed for a second instruction that is younger in order than said first instruction; providing a data commitment table comprising a plurality of entries associated respectively with a plurality of real registers including a first entry associated with said first real register, said first entry of said data commitment table comprising a committed data location field to indicate if a second register value generated by a third instruction is stored in a second alias register or in said first real register, and a reorder buffer index field to identify a second entry of said reorder buffer containing said, second alias register if said second register value is stored in said second alias register; determining whether said second register value is in said second alias register or in said first real register by reading said committed data location field of said data commitment table; deasserting a second valid data field of said second entry of said reorder buffer if it is determined that said second register value is in said second alias register to indicate that said second register value is not valid for copying from said second alias register to said first real register; and writing an identifier for said first entry of said reorder buffer in said reorder buffer index field of said first entry of said data commitment table.