Patent ID: 7009277

Claim:
A semiconductor device comprising: a semiconductor substrate having a principal plane in which an insulation film is selectively formed; an insulating layer formed on said principal plane; a heat generating layer embedded in said insulation layer and opposing to said principal plane with a part of said insulation layer interposed between said heat generating layer and said principal plane; a first wiring layer disposed on said insulation layer; a second wiring layer disposed on said insulation layer; a first plug embedded in said insulation layer, a lower end of said first plug being connected to one end of said heat generating layer and an upper end of said first plug being connected to said first wiring layer; a second plug embedded in said insulation layer, a lower end of said second plug being connected to other end of said heat generating layer and an upper end of said second plug being connected to said second wiring layer; and a third plug embedded in said insulation layer, an upper end of said third plug being connected to said first wiring layer or said first plug and a lower end of said third plug reaching said insulation film of said principal plane.