Patent ID: 8841897

Claim:
A voltage regulator having current and voltage foldback based upon load impedance, comprising: a power transistor having a gate, a source and a drain, wherein the power transistor is coupled between a power source and a load; a voltage divider coupled in parallel with the load and providing a feedback voltage that represents an output voltage from the power transistor to the load; an error amplifier having a first input coupled to a reference voltage, a second input coupled to the feedback voltage, and an output coupled to the gate of and controlling the power transistor, wherein the error amplifier causes the power transistor to maintain the feedback voltage at substantially the same voltage as the reference voltage; a current sensing circuit for measuring current to the load and providing a sense current representative of the measured load current; a current limit and foldback circuit having a first input coupled to the feedback voltage, a second input coupled to the reference voltage, a third input coupled to the sense current from the current sensing circuit, and an output providing a current foldback bias; and a current-to-voltage offset bias source having a current input and a voltage output, the current input thereof is coupled to the output of the current limiting and foldback circuit providing the current foldback bias, and the voltage output thereof is coupled between the first and second inputs of the error amplifier and provides a voltage offset bias proportional to the current foldback bias from the current limiting and foldback circuit; wherein the current limit and foldback circuit is in a current limit mode when the load current is less than or equal to a current limit value, and in a foldback mode when an output load impedance is less than a foldback load impedance value; whereby the voltage offset bias is substantially zero volts when the load current is less than the current limit value and the output load impedance is greater than the foldback load impedance value, and increases when the output load impedance is less than or equal to the foldback load impedance value, thereby reducing the output voltage and the output current proportionally until the output voltage is at substantially zero volts and the output current is at a foldback current value.