Patent ID: 7702860

Claim:
A memory access apparatus for accessing a first memory and a second memory, comprising: an address outputting unit configured to output a read address to at least one of the first and the second memories based on a data size and an address in an address space of a read data; an access request outputting unit configured to output a read request to at least one of the first and the second memories based on the data size and the address in the address space of the read data; a data information outputting unit configured to output an information on the data size, and an information on the address, of the read data; and a read data outputting unit configured to generate the read data to be output, from the data output from at least one of the first and the second memories in response to the read address output from the address outputting unit and the read request output from the access request outputting unit, based on the information on the data size and the information on the address that are output from the data information outputting unit.