Patent ID: 8253193

Claim:
An integrated circuit containing an MOS transistor, said integrated circuit comprising: a semiconductor substrate; a drift region formed in said substrate, said drift region having a first conductivity type and extending to a top surface of said substrate; an isolation dielectric layer formed at said top surface of said substrate over said drift region; a first gate trench formed in said substrate, such that said first gate trench abuts said isolation dielectric layer; a second gate trench formed in said substrate proximate to said first gate trench opposite from said isolation dielectric layer, such that said second gate trench is separate from said first gate trench; a body well formed in said substrate adjacent to said drift region, such that said body well abuts said first gate trench and said second gate trench, and such that said body well has an opposite conductivity type from said drift region; a buried layer formed in said substrate under said drift region, and under said first gate trench and said second gate trench, such that said buried layer has a same conductivity type as said drift region, and such that a doping density of said buried layer is more than 10 times a doping density of said drift region; a gate dielectric layer formed on exposed surfaces of said substrate in said first gate trench and in said second gate trench; a gate formed on said gate dielectric layer in said first gate trench and in said second gate trench; and a source diffused region formed in said body well, such that said source diffused region abuts said gate dielectric layer in said first gate trench and in said second gate trench, and such that said source diffused region has a same conductivity type as said drift region.