Patent ID: 8194086

Claim:
A computer system, comprising: a system processor; a system bus coupled to the system processor; a system memory coupled to the system bus; and a graphics processing system coupled to the system bus, the graphics processing system, comprising: a plurality of memory banks configured to store data; a pipeline processing system coupled to the plurality of memory banks and configured to process graphics data provided from the memory banks and provide processed graphics data to the memory banks the pipeline processing system comprising: a pre-processed data buffer coupled to the read data bus and configured to temporarily store the graphics data read from a bank of memory; a pixel processing pipeline coupled to the pre-processed data buffer and configured to receive and process the graphics data from the pre-processed data buffer and generate processed graphics data; and a post-processed data buffer coupled to the pixel processing pipeline and configured to receive processed graphics data from the pixel processing pipeline and temporarily store the same before being provided to the write data bus the post-processed data buffer comprising: a first-in first-out (“FIFO”) buffer having an input coupled to the pixel processing pipeline and further having an output at which the processed data is provided after being temporarily stored; and a write buffer circuit having an input coupled to the FIFO buffer and having an output coupled to the write data bus, the write buffer configured to temporarily store the processed data received from the FIFO prior to being written to a memory bank; and a memory controller coupled to the plurality of memory banks and configured to coordinate memory access to the plurality of memory banks to provide graphics data retrieved from a first one of the plurality of memory banks to the pipeline processing system for processing, to provide graphics data retrieved from a second one of the plurality of memory banks to the pipeline processing system for processing concurrently with processing graphics data retrieved from a first one of the plurality of memory banks and concurrently with writing processed graphics data from the first one of the plurality of memory banks back to the first one of the plurality of memory banks.