Patent ID: 6927114

Claim:
A method for fabricating a high voltage dual gate device comprising: forming high voltage n-type and p-type well regions in a high voltage device forming region of a semiconductor substrate, the substrate also having a low voltage device forming region; forming the source/drain of a high voltage NMOS transistor and the source/drain of a high voltage PMOS transistor in the well regions; forming a trench by a STI process and forming a device isolation layer in the trench and forming a buffer nitride film on the resulting structure; forming a high voltage gate oxide film on the buffer nitride film and etching portions of the high voltage gate oxide and buffer nitride films disposed over the low voltage device forming region leaving the said high voltage gate oxide and buffer nitride films intact on top of the high voltage device forming region; and forming low voltage p-type and n-type well regions in the low voltage device forming region and forming a low voltage gate oxide film on top of the low voltage device forming region.