Patent ID: 8887117

Claim:
A method performed by at least one processor, comprising: receiving, by the at least one processor, a physical netlist of a placed integrated circuit (IC) chip design, the physical netlist comprising a plurality of registers; obtaining, by the at least one processor, timing criticalities of register pairs in the registers; assigning weights to the register pairs based on the timing criticalities of the register pairs; and forming, by the at least one processor, clusters of the registers comprising: identifying candidate registers that are in physical vicinity of a first cluster; and selecting from the candidate registers a first register to be added to the first cluster by giving priority to a candidate register in a register pair across a boundary of the first cluster and with a higher timing criticality over a candidate register located closer to the first cluster, the registers in the same cluster having shorter non-common clock paths than the registers in different clusters, and the selecting comprising: if a first candidate register in the candidate registers of the first cluster is unclustered, selecting the first candidate register as the first register to be added to the first cluster if sum of weights of other candidate registers in register pairs across the boundary of the first cluster is optimized.