Patent ID: 8330207

Claim:
A flash memory device, comprising: a lower tunnel insulation layer on a substrate; an upper tunnel insulation layer on the lower tunnel insulation layer; a P-type floating gate on the upper tunnel insulation layer; an intergate insulation layer on the floating gate; and a control gate on the intergate insulation layer, wherein: the upper tunnel insulation layer includes an amorphous oxide layer, the lower tunnel insulation layer and the upper tunnel insulation layer extend between isolations protruding from an upper surface of the substrate, the P-type floating gate and the intergate insulation layer both contact an upper surface of the isolations, a distance that the isolations protrude from the upper surface of the substrate is larger than a distance between an upper surface of the upper tunnel insulation layer and the upper surface of the substrate, the P-type floating gate contacts the upper tunnel insulation layer, the upper tunnel insulation layer contacts the lower tunnel insulation layer, and the lower tunnel insulation layer includes an oxide.