Patent ID: 8242016

Claim:
A method for fabricating an integrated circuit structure, the method comprising: forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer comprising sidewall portions and horizontal portions in the opening, wherein the sidewall portions cover sidewalls of the low-k dielectric layer in the opening; before performing any removal step to remove any horizontal portion of the barrier layer, performing a treatment to the barrier layer in an environment comprising a treatment gas selected from the group consisting essentially of hydrogen, ammonia, and combinations thereof, with the barrier layer being at an elevated temperature during the treatment, wherein after the step of performing the treatment, the sidewall portions of the barrier layer comprises an inner portion and an outer portion, wherein the outer portion separates the inner portion from a low-k dielectric material of the low-k dielectric layer, and wherein the inner portion and the outer portion of the barrier layer have different compositions; forming a seed layer on the barrier layer, wherein there is no vacuum break occurring between the treatment and the step of forming the seed layer; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.