Patent ID: 8219788

Claim:
A system adapted for use with a computer processor having a bus unit and a plurality of physical cores, the system comprising: a memory component adapted to store one or more virtual cores; and a virtual core management component adapted to map the one or more virtual cores to at least one of the plurality of physical cores to enable an execution of a plurality of programs, thereby directing a plurality of transaction signals to the physical cores to an intended destination based on the mapping of the one or more virtual cores; a virtual core to physical core mapping table for storing mappings between the one or more virtual cores and the plurality of physical cores, wherein at least one single virtual core of the one or more virtual cores comprises a collection of logical states for the execution of the plurality of programs, and wherein the at least one single virtual core is configured to execute the plurality of programs, wherein the mapping comprises transferring the collection of logical states of the at least one single virtual core from the memory component to the at least one physical core, wherein the virtual core management component is adapted further to rearrange the mapping of the virtual cores to the physical cores based on utilization of the physical cores, thereby redirecting transaction signals to the physical cores to an intended destination based on the rearrangement of the mapping of the virtual cores, and wherein the virtual core management component saves information about mapping between the virtual core and the physical core such that the physical core executes a program designated to the virtual core that is mapped to the physical core.