Patent ID: 7315939

Claim:
A microcomputer comprising: a non-volatile memory which stores a program and initialized data including clock stabilizing time data and switch data of a setting-variable functional macro; initialized data reading control means which starts the preparation for reading the initialized data in response to a first internal reset signal and controls the reading operation of the initialized data from said non-volatile memory synchronously with a system clock signal; a CPU which executes the program in response to the system clock signal; a main clock generating circuit which generates and outputs a main clock signal; an oscillating circuit which is arranged independently of said main clock generating circuit and which generates a sub-clock signal; a set data register which holds the initialized data read from said non-volatile memory; a setting control unit which sets the first internal reset signal to an inactive level in response to a control signal, selects and outputs the sub-clock signal as the system clock signal, starts the counting operation of pulses of the system clock signal, sets a second internal reset signal to the inactive level when the clock stabilizing time data held in the set data register matches a counted value of the pulse, and selects and outputs the main clock signal as the system clock signal; and a setting-variable functional macro including a switching circuit which is initialized by the output from said set data register, wherein said initialized data reading control means is a dedicated memory control circuit which is arranged independently of said CPU, said memory control circuit starts the reading control of the initialized data when the first internal reset signal is at the inactive level, and a resetting state of said CPU is canceled when the second internal reset signal is at the inactive level.