Patent ID: 7818508

Claim:
A computer system comprising: memory devices having first and second memory segments; a first socket having a first processing core and a first memory controller, wherein the first memory controller is configured to manage access of the first memory segment; a second socket having a second processing core and a second memory controller, wherein the second memory controller is configured to manage access of the second memory segment; a fabric; and a first processor agent associated with the first socket, wherein the first processor agent includes a first coherency controller, wherein the first coherency controller includes a first memory translation cam (MTC), wherein the first MTC is configured to convert a fabric address into a local physical address that is in turn provided to the first memory controller, and wherein the first memory controller is configured to access a particular memory location within the first memory segment based upon the local physical address; and a second processor agent associated with the second socket, wherein the first processor agent is configured to: convert an address of a first memory request, issued by the first processing core for accessing the second memory segment, to a first fabric address, send the first memory request, as modified to include the first fabric address, over the fabric to the second processor agent to cause the second processor agent to convert the first fabric address to a first physical address specifying a memory location of the second memory segment, convert an address of a second memory request, issued by the first processing core for accessing the first memory segment, to a second fabric address, send the second memory request, as modified to include the second fabric address, over the fabric, wherein the modified second memory request is destined to the first processor agent, and convert the second fabric address to a physical address specifying a memory location of the first memory segment.