Patent ID: 7344997

Claim:
A method for manufacturing a semiconductor substrate comprising: a step of forming, on a semiconductor base, a first laminated layered structure composed of a second semiconductor layer having a smaller selection ratio at etching than a first semiconductor layer, laminated on the first semiconductor layer; a step of forming, in a part of an area on the first laminated layered structure, a second laminated layered structure composed of a fourth semiconductor layer having a smaller selection ratio at etching than a third semiconductor layer, laminated on the third semiconductor layer; a step of forming a first groove that penetrates the first semiconductor layer through the fourth semiconductor layer and exposes the semiconductor base; a step of forming a supporting body for supporting the second and fourth semiconductor layers on the semiconductor base on side walls of the first semiconductor layer through the fourth semiconductor layer in the first groove; a step of forming, in a first area divided by the first groove, a second groove that exposes at least a part of the first semiconductor layer through the second semiconductor layer; a step of forming, in a second area divided by the first groove, a third groove that exposes at least a part of the third semiconductor layer through the fourth semiconductor layer; a step of forming void sections under the second and fourth semiconductor layers by selectively etching the first and third semiconductor layers through the second groove and the third groove; and a step of forming dielectric layers disposed below the second and fourth semiconductor layers by thermally oxidizing the second and fourth semiconductor layers through the void sections.