Patent ID: 6986090

Claim:
A method for reducing switching activity during a test scan operation of at least one scan chain in an integrated circuit (IC) comprising the steps of: a) determining stimulus and result value probabilities for a plurality of memory elements in said IC; and b) connecting said memory elements to from at least one scan chain based on said stimulus and result value probabilities to reduce the switching activity as determined by said stimulus and result value probabilities and by ordering said memory elements within said at least one scan chain, wherein connecting said memory elements includes sequentially connecting at least one pair of said memory elements, said at least one pair of memory elements being determined by computing a value extracted from the equation: D ( A,B ){ 1+K[ pm ( A )(1 −pm ( B ))+ pm ( B )(1 −pm ( A ))]}, wherein D(A,B) is a distance between said pair of memory elements, pm(A) is a probability that said stimulus and result values of a first memory element of said pair are the same, pm(B) is a probability that said stimulus and result values of a second memory element of said pair are the same, and K is a constant value.