Patent ID: 6954206

Claim:
A memory controller comprising: a CPU interface arranged to interface with a CPU; a memory interface arranged to interface with a memory storing programs to be processed in the CPU and display data to be displayed on a display; a rendering process circuit to access the memory; and a memory control circuit to control access to the memory from one of the CPU, the display controller and the rendering processor, wherein, when an access to the memory from the CPU is requested at the time when the rendering process circuit accesses the memory, the memory control circuit stops the access to the memory from the rendering process circuit until the access to the memory form the CPU ends, and when the access to the memory from the CPU ends, resumes the access to the memory from the rendering process circuit from the beginning, and wherein the memory control circuit is connected to the CPU, via a CPU bus, and to the memory, via a memory bus, for providing priority to the access from the CPU to the memory, and wherein the memory control circuit comprises: a first decoder to generate a CPU bus access request signal, when an access request is issued from the CPU; a second decoder to generate an internal bus access start signal when an access request is issued from an internal bus; a CPU access buffer to receive the CPU bus access request signal, and to produce a CPU bus access valid signal which exhibits a high logic state during execution of the memory access from the CPU, and returns to a low logic state after the memory access from the CPU ends; a CPU bus access length calculation circuit to calculate the number of cycles required for the memory access from the CPU, and to produce a CPU access length; an internal bus access counter, reset upon receipt of the internal bus access start signal, to count the number of cycles during execution of an internal bus access and to produce an internal access cycle; a stop decision circuit to generate a switching start cycle indicating the timing for setting a switching signal, and a stop start cycle indicting the timing for setting a stop signal; a switching signal generation circuit to generate the switching signal for controlling the memory access from one of the CPU and the rendering process circuit, on the basis of the CPU access length, the internal access cycle, and the switching start cycle; and a stop processing circuit to generate the stop signal for stopping the memory access from the rendering process circuit until the end of the memory access from the CPU, on the basis of a command outputted from the second decoder, the CPU access length output from the CPU bus access length calculation circuit, and the internal bus access outputted from the internal bus access counter, and the stop start cycle.