Patent ID: 8268696

Claim:
A process of forming an integrated circuit, comprising the steps of: providing a substrate; forming a dielectric layer on said substrate; forming an alignment mark segment in said dielectric layer, by a process further including the steps of: forming a contact photoresist pattern on a top surface of said dielectric layer which defines a contact metal field to be etched and an array of pillars of said dielectric layer in said contact metal field to be unetched; etching said dielectric layer through said contact photoresist pattern to remove dielectric layer material from said contact metal field and form an array of pillars of said dielectric layer in said contact metal field, whereby every location in said contact metal field is within a desired maximum horizontal distance from a boundary of said contact metal field, said boundary including edges of said contact metal field and perimeters of said pillars; depositing a conformal layer of contact metal on said top surface of said dielectric layer, on a top surface of said pillars and in said contact metal field; removing said contact metal from said top surface of said dielectric layer and said top surface of said pillars; and removing contact metal from a top surface of said contact metal such that the top surface of said contact metal in said contact metal field is at least 15 nanometers below a top surface of said dielectric layer surrounding said contact metal field; and forming an opaque layer on said top surface of said contact metal and a top surface of said pillars, such that a first top surface of said opaque layer over said contact metal field is at least 15 nanometers below a second top surface of said opaque layer outside said alignment mark segment.