Patent ID: 7724593

Claim:
An apparatus, comprising: a plurality of memory cells arranged in a plurality of columns and a plurality of rows, wherein each memory cell in a column is coupled to each other by a corresponding bit line of a plurality of bit lines; a precharge select circuit operatively coupled to the plurality of bit lines; access circuitry coupled to the plurality of bit lines; and control circuitry coupled to the plurality of memory cells, the precharge select circuit, and the access circuitry, wherein the control circuitry is configured to: receive a first access command to perform a first access operation on a first subset of the plurality of memory cells; initiate a selective precharge operation, by the selective precharge circuit, on a subset of the plurality of bit lines, wherein the subset of the plurality of bit lines is coupled to the first subset of the plurality of memory cells, wherein the subset of the plurality of bit lines includes fewer bit lines than the plurality of bit lines, and wherein the selective precharge operation results in a precharged state of the subset of the plurality of bit lines; check for receipt of a second access command to perform a second access operation on a second subset of the plurality of memory cells, wherein the subset of the plurality of bit lines is coupled to the second subset of the plurality of memory cells; and facilitate performance, by the access circuitry, of the second access operation on the second subset of memory cells, wherein the second access operation is different from the first access operation, and wherein the control circuitry is further configured to facilitate the performance of the second access operation while the subset of the plurality of bit lines remain in the precharged state that results from the selective precharge operation initiated in response to receipt of the first access command.