Patent ID: 7675768

Claim:
A memory device, comprising: a memory cell including a pass transistor, a capacitor, and a carbon nanotube storage element connecting to the pass transistor and the capacitor through a storage node, wherein the carbon nanotube storage element is composed of carbon nanotube(s) disposing in between a bottom electrode and a top electrode; and a first dynamic circuit as a local sense amp connecting to the memory cell through a local bit line, wherein the first dynamic circuit includes a pre-charge transistor for pre-charging the local bit line, a local amplify transistor for reading the local bit line where the local amplify transistor is serially connected to a local select transistor, and a write transistor connecting to the local bit line; and a second dynamic circuit as a segment sense amp connecting to the local select transistor through a segment bit line, wherein the segment sense amp is composed of a pre-set transistor for pre-setting the segment bit line, a segment amplify transistor for reading the segment bit line where the segment amplify transistor is serially connected to a segment select transistor; and a first tri-state inverter as an inverting amplifier of a global sense amp connecting to the segment select transistor through a global bit line, wherein the global sense amp includes a write circuit, a read circuit, a bypass circuit and a returning buffer, the write circuit is composed of a receiving gate for receiving a write data through a forwarding write line and driving a write bit line which is connected to the write transistor of the local sense amp; the read circuit is composed of the first tri-state inverter for reading the global bit line and a reset transistor for resetting the global bit line; the bypass circuit is composed of a second tri-state inverter for bypassing a voltage of the forwarding write line, and a read inverter for receiving an output from the first tri-state inverter or the second tri-state inverter through a common node, and the returning buffer for buffering a returning read line which receives a read output from the read inverter; and in order to reduce turn-off current, the local amplify transistor is composed of longer channel length transistor than that of the pre-set transistor of the segment sense amp, and the segment amplify transistor is composed of longer channel length transistor than that of the reset transistor of the global sense amp; and an output latch circuit receiving and storing an output from the returning buffer; and a latch control circuit generating a locking signal which is generated by a reference signal based on at least a reference memory cell, in order to lock the output latch circuit.