Patent ID: 8250509

Claim:
A method of apportioning timing budgets in an integrated circuit design, the method comprising: using at least one processor, calculating slack for each of a plurality of ports of a plurality of units in an integrated circuit design to generating a plurality of slack offers and slack requests, including, for a first port in a first unit among the plurality of units determined to have a positive slack: performing timing analysis on the first unit to determine a magnitude of the positive slack; determining that at least a portion of logic in the first unit is capable of being replaced with faster logic by tracing a critical path in the first unit coupled to the first port, and detecting at least one logic gate in the critical path capable of being replaced with a faster logic gate during tracing of the critical path; and increasing the magnitude of the positive slack in a slack offer for the first unit in response to the determination; and after calculating slack for the plurality of units, performing negotiation using the generated slack offers and slack requests to reapportion timing budgets for the plurality of units.