Patent ID: 8599604

Claim:
A semiconductor memory device comprising: one or more bit lines; one or more write word lines; one or more read word lines; one or more memory cells; and a first inverter, wherein each of the memory cells comprises a write transistor, a read transistor, and a second inverter, wherein a maximum resistance of the write transistor is 1×10 18 Ω or more, wherein one of a source and a drain of the write transistor is connected to one of the bit lines, wherein one of a source and a drain of the read transistor is connected to another of the bit lines, wherein the other of the source and the drain of the write transistor is connected to an input of the second inverter, wherein the other of the source and the drain of the read transistor is connected to an output of the second inverter, wherein a gate of the write transistor is connected to the write word line, wherein a gate of the read transistor is connected to the read word line, wherein the one of the bit lines is configured to connected to an input of the first inverter, and wherein an output of the first inverter is connected to the another of the bit lines.