Patent ID: 6906387

Claim:
A semiconductor structure having electrostatic discharge (ESD) protection, comprising: an insulating layer; a silicon layer on at least one side of the insulating layer; a first transistor device formed in the silicon layer, the first transistor device having a source region and a drain region; and a second transistor device formed in the silicon layer, the second transistor device having a source region and a drain region; wherein the first transistor device and the second transistor device are connected in series such that the drain region of the first transistor device and the source region of the second transistor device are in a shared region of the silicon layer; the shared region has a depth that does not extend through the silicon layer to the insulating layer; and the first and second transistor devices form a single parasitic bipolar device in the silicon layer such that the first and second transistor devices exhibit simultaneous snapback during an ESD event.