Patent ID: 7632750

Claim:
A process for the manufacture of a wafer substrate for use in the semiconductor industry, comprising: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween, said pattern plate having a plurality of aligned through-holes arranged thereon, wherein said first compressive member and said second compressive member have correspondingly curved facing surfaces to effect an excess solder removal operation during compression of said pattern plate therebetween, and wherein said curved facing surfaces of said compressive members are of slightly cylindrical shape; filling said through-holes with a molten solder; compressing said solder and pattern plate between said first and second opposed compressive members to compact said solder therein and cleans said pattern plate of excess solder; chilling said pattern plate to solidify said molten solder in said through-holes; and removing said pattern plate from said spaced-apart compressive members.