Patent ID: 7979848

Claim:
A non-transitory computer-accessible medium having executable instructions to validate a system, the computer-accessible medium executable instructions capable of directing a processor to perform: receiving scenarios of the system; pattern-matching the scenarios of the system to at least one process-based specification segment; and analyze the formal specification, wherein the computer executable instructions comprise pattern-matching the scenarios of the system to a formal specification, in reference to an inference engine, applying mathematical logic to the formal specification in order to identify a presence or absence of mathematical properties of the scenario, and correcting the absence of the mathematical properties if the mathematical properties are identified as absent in the scenario, and wherein the mathematical properties of the formal specification comprise whether the formal specification implies a system execution trace that includes a deadlock condition, whether the formal specification implies a system execution trace that includes a livelock condition, and whether the formal specification implies a system execution trace that exhibits or does not exhibit a plurality of other desirable or undesirable behaviors including, but not limited to safety properties, security properties, unreachable states, inconsistencies, naming conflicts, unused variables, unexecuted code.