Patent ID: 8786067

Claim:
A semiconductor package, comprising: a plurality of semiconductor chips arranged in a stack structure, the plurality of semiconductor chips including an upper-most semiconductor chip of the semiconductor package; a plurality of substrates having the semiconductor chips respectively attached thereto, each substrate having one or more vias, the plurality of substrates including an upper-most substrate of the semiconductor package; a plurality of solder balls arranged to provide voltages and signals to the plurality of semiconductor chips; a heat sink positioned to spread heat produced in the interior of the package to the outside, the heat sink connected to at least a first solder ball of the plurality of solder balls and positioned above the upper-most semiconductor chip of the semiconductor package, wherein the heat sink is the only heat sink in the semiconductor package; and an insulating layer positioned between the upper-most substrate and the heat sink, wherein a first via in the upper-most substrate is vertically aligned with the first solder ball, at least a second via in a second, lower substrate, and at least a second solder ball disposed between and connecting the first via and second via, and is connected with the first solder ball and the second solder ball, and wherein the insulating layer includes a first hole or a first conductive layer which is vertically aligned with the first solder ball, the first via, second solder ball, and second via, whereby vertical alignment corresponds to a location of the first solder ball with respect to the first via, and the first solder ball, the first via, the second solder ball, and the second via are electrically connected to the heat sink through the first hole or the first conductive layer such that the first solder ball is disposed to pass heat from a second chip corresponding to the second substrate to the heat sink.