Patent ID: 8887013

Claim:
A method of mapping defects in a memory device with memory cells arranged in rows and columns, the method comprising: receiving an incoming address identifying a memory location of a memory cell in the memory device, the incoming address including an incoming row address and an incoming column address, the incoming row address belonging to a group of row addresses, the group of row addresses having no more than one defective memory cell per column, each group of row addresses being assigned an alternate row address or an index and a defective row address; determining whether or not the incoming column address identifies a defective column; if it is determined that the incoming column address identifies a defective column, replacing the incoming column address with an alternate column address that identifies an alternate memory location in the memory device for accessing the memory cell; determining whether or not the incoming row address identifies a defective row; if the incoming row address identifies a defective row, replacing the incoming row address with an alternate row address that identifies the alternate memory location in the memory device for accessing the memory cell; else determining if the incoming address identifies a defective memory cell; if it is determined that the incoming address identifies a defective memory cell, replacing the incoming row address with the alternate row address to be used for identifying an alternate memory location in the memory device for accessing the memory cell; and searching a defective row address table for a match between the incoming column address and a first field of the entries of the defective row address table, the first field of the entries of the defective row address table being the address of columns having defective cells, and if a match occurs, using a second field of the entries of the defective row address table as the defective row address else using a predefined value as the defective row address.