Patent ID: 7601552

Claim:
A method of manufacturing a semiconductor structure of a liquid crystal display (LCD) panel, comprising the steps of: providing a substrate defined with an active device region and a capacitor region; forming and patterning a polysilicon layer in the active device region and the capacitor region of the substrate; forming a first dielectric layer to cover the polysilicon layer and the substrate; forming and patterning a first metal layer on the first dielectric layer, wherein the first metal layer covers part of the polysilicon layer in the active device region to compose a gate electrode and covers the polysilicon layer in the capacitor region to compose a first capacitor electrode; forming a heavily implanted region in the polysilicon layer not covered by the first metal layer in the active device region as a first source/drain and a second source/drain; forming a second dielectric layer to cover the first metal layer and the substrate; forming and patterning a second metal layer to form a data line around the active device region and a second capacitor electrode in the capacitor region; forming a third dielectric layer to cover the second metal layer and the substrate; forming a patterned photoresist layer; etching the third dielectric layer, the second dielectric layer, and the first dielectric layer to form a plurality of via openings exposing the data line, the first source/drain, the second source/drain, and the second capacitor electrode by using the patterned photoresist layer as a mask; forming a third metal layer to cover the patterned photoresist layer and the substrate and to fill the via openings; stripping off the patterned photoresist layer and part of the third metal layer on the patterned photoresist layer; and forming and patterning a transparent conductive layer to form a transparent wire and a pixel electrode, wherein the transparent wire electrically connects the data line and the first source/drain and the pixel electrode electrically connects the second source/drain and the second capacitor electrode.