Patent ID: 8791521

Claim:
A semiconductor device comprising: a semiconductor substrate; an element isolation region defined in the semiconductor substrate and having an element isolation insulating film formed therein; an active region defined in the semiconductor substrate delineated by the element isolation region; a gate insulating film formed in the active region; a charge storage layer formed above the gate insulating film; a multilayered interelectrode insulating film formed in a first region above an upper surface portion of the element isolation insulating film, a second region along a sidewall portion of the charge storage layer, and a third region above an upper surface portion of the charge storage layer; and a control electrode layer formed above the interelectrode insulating film; wherein the interelectrode insulating film comprises a first stack including a first silicon nitride film or a first high dielectric constant film interposed between a first silicon oxide film and a second silicon oxide film formed above the first silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film formed above the second high dielectric constant film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack and, wherein the second silicon nitride film is absent in the third region.