Patent ID: 8432194

Claim:
A bias potential generating circuit comprising: a clock signal generating section that generates a clock signal having a predetermined frequency; a rising wave form signal generating section that generates, synchronous to the clock signal, a rising wave form signal having a wave form of a rising portion of a sine wave; a pulse width modulation signal generating section that generates, synchronous to the clock signal, a pulse width modulation signal by pulse width modulating the rising wave form signal; a first resistor having a first end connected to a reference potential input terminal of an operational amplifier; a second resistor having a first end connected to the first end of the first resistor and to the reference potential input terminal of the operational amplifier, and a second end connected to a ground; and a switch, having a first end connected to a power supply and a second end connected to a second end of the first resistor, that turns ON and OFF based on the pulse width modulation signal.