Patent ID: 7022600

Claim:
A method of forming a damascene interconnection, comprising: (a) sequentially forming an interlayer dielectric and a hard mask layer on a semiconductor substrate; (b) successively patterning the hard mask layer and the interlayer dielectric to form a hole exposing a predetermined portion of the semiconductor substrate; (c) forming a planarization layer in the hole and on the hard mask layer, the planarization layer having a planar top surface extending across the hole; (d) patterning the planarization layer and the hard mask layer to form a groove opening, wherein the groove opening is wider than the hole and exposes a top surface of the interlayer dielectric adjacent to the hole; and (e) etching the exposed interlayer dielectric to form a groove in the interlayer dielectric, wherein the patterned planarization layer is removed before etching the exposed interlayer dielectric and wherein the groove is wider than the hole and a depth of the groove is smaller than a thickness of the interlayer dielectric.