Patent ID: 7881030

Claim:
An electrostatic discharge (ESD) clamp circuit comprising: a first terminal; a second terminal having a first voltage with respect to a voltage at the first terminal, such that the first terminal and the second terminal are coupled between an ESD protected circuit and a direct current (DC) reference; a first enhancement-mode field effect transistor (FET) element formed using a compound semiconductor material and comprising: a first drain coupled to the first terminal; a first source coupled to the second terminal; and a first gate; a first resistive element coupled between the first gate and the second terminal, wherein when the first voltage exceeds a first threshold, the ESD clamp circuit is in a clamping state; and a plurality of resistive elements comprising the first resistive element, wherein the first enhancement-mode FET element further comprises a multiple gate enhancement-mode FET element having a plurality of gates comprising the first gate, such that each of the plurality of resistive elements is coupled between a corresponding each of the plurality of gates and the second terminal.