Patent ID: 7269051

Claim:
An inspection method of an array board which includes a plurality of gate lines arrayed in rows, a plurality of signal lines arrayed in columns and a plurality of pixels each of which is arranged at the intersections of the gate lines with the signal lines, the pixels including switching transistors having control terminals connected to the gate lines and terminals of one side connected to the signal lines, and retention capacitors connected to the terminals of the other side of the switching transistors, the inspection method of the array board comprising the steps of: selecting a signal line out of a plurality of the signal lines; applying a writing electric potential to the selected signal line; selecting a gate line out of a plurality of the gate lines; turning on the switching transistor arranged at the intersection of the selected signal line with the selected gate line, by applying a first electric potential to the one end of the selected gate line and applying a second electric potential being lower than the first electric potential to the other end of the selected gate line; measuring the electric charge quantity stored in the retention capacitor through the selected signal line, and determining a disconnection failure of the selected gate line on the basis of the measured electric charge quantity.