Patent ID: 8358526

Claim:
An electronic memory array comprising: a first plurality of generally parallel conductors each having a non-negligible resistance; a second plurality of generally parallel conductors, each having a non-negligible resistance, overlapping the first plurality of generally parallel conductors; a plurality of storage elements each disposed proximate a point of overlap between the first and second pluralities of generally parallel conductors; one or more first power busses (i) generally parallel to the second plurality of generally parallel conductors and (ii) each having a non-negligible resistance; and one or more second power busses (i) generally parallel to the first plurality of generally parallel conductors and (ii) each having a non-negligible resistance wherein an address path for each storage element (i) is unique and (ii) traverses at least a portion of one of the first plurality of generally parallel conductors, at least a portion of one of the second plurality of generally parallel conductors, at least a portion of one of the first power busses, and at least a portion of one of the second power busses, and all storage element address paths have substantially equivalent voltage drops across the corresponding storage elements.