Patent ID: 7096292

Claim:
A data transfer block for use in an integrated circuit (IC) to interface an on-chip subsystem to an on-chip bus, the data transfer block comprising: a first and a second outbound queue to facilitate selective staging of a first and a second plurality of outbound bus transactions for the on-chip subsystem, at the choosing of the on-chip subsystem, each of said outbound bus transactions including a bus arbitration priority; and a first state machine coupled to the first and second outbound queues to service the first and second outbound queues by according the first queue a first outbound priority and the second queue a second outbound priority, and serially requesting for access to the on chip bus for the staged outbound bus transactions based at least in part on accorded outbound priorities, where access to the on-chip bus is granted to requesting bus transactions based at least in part on the included bus arbitration priorities of the contending bus transactions.