Patent ID: 7935589

Claim:
A method of forming a semiconductor device comprising: providing a substrate having a transistor formed thereon, the transistor comprises a gate and first spacers on gate sidewalls, the first spacers having a first width W 1 ; performing a first etch to form stressor recesses in the substrate adjacent to the first spacers, the first etch is an anisotropic etch, wherein first edges of the stressor recesses are self-aligned to outer edges of the first spacers; forming stressors in the stressor recesses, the stressors having first stressor edges at the first edges of the stressor recesses; forming sacrificial spacers on the gate sidewalls over the first spacers, the sacrificial spacers having a second width W 2 , wherein a total width of the first and sacrificial spacers is W 1 +W 2 ; performing a second etch to form contact openings in the stressors, wherein the second etch is an anisotropic etch which is self-aligned to outer edges of the sacrificial spacers; depositing a conductive layer on the substrate; forming silicide contacts adjacent to the gate by causing a reaction with the conductive layer, wherein the silicide contacts are self-aligned to the outer edges of the sacrificial spacers; and removing the sacrificial spacers after forming the silicide contacts to expose the substrate to provide a gap between the silicide contacts and first stressor edges, the gap having a distance G equal to the width of the sacrificial spacers W 2 to reduce relaxation of stress in the stressors.