Patent ID: 8829644

Claim:
A non-volatile memory device, comprising: a semiconductor substrate having a field region on which a device isolation pattern is arranged, and an active region defined by the device isolation pattern and extending in a first direction; a first dielectric pattern on the active region of the semiconductor substrate; a plurality of conductive stack structures arranged on the first dielectric pattern and having a recess between a pair of the conductive stack structures adjacent to each other in a second direction substantially perpendicular to the first direction, wherein each of the plurality of conductive stack structures includes a floating gate electrode, a second dielectric pattern covering a surface of the floating gate electrode and the device isolation pattern in the recess and extending in the second direction, and a control gate line covering the second dielectric pattern and extending in the second direction; and a protection layer on a sidewall of the plurality of conductive stack structures to protect the sidewall of the plurality of conductive stack structures from over-etching along the first direction, wherein the protection layer includes an etch-proof layer having an oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line, and a spacer layer covering the sidewall of the plurality of conductive stack structures.