Patent ID: 8546880

Claim:
An anti punch-through leakage current MOS transistor, comprising: a second type substrate having a grounding region; a high voltage deep first type well region formed in the second type substrate; a first type light doping region formed in the high voltage deep first type well region so as to form a drain structure; a second type body formed in the high voltage deep first type well region and separately located at a side of the first type light doping region so as to form a source structure and a body structure; a gate structure on the second type substrate, the gate structure connecting between the second type body and the first type light doping region; and an anti punch-through leakage current structure formed in the high voltage deep first type well region and between the second type body and the grounding region, a location of the anti punch-through leakage current structure being deeper than a location of the second type body.