Patent ID: 7613849

Claim:
An integrated circuit comprising: a plurality of processing modules including a first module and a second module; an interconnect device for coupling said plurality of processing modules and for enabling a device-level communication based on transactions between said plurality of processing modules, wherein the first processing module issues at least one transaction for reception by the second processing module through the interconnect device; at least one transaction abortion unit connected at least one of between the first module and the interconnect device and between the second module and the interconnect device for aborting at least one transaction issued from said first module in response to receiving an abort request issued by said first module, by initiating a discard of said at least one transaction to be aborted, and by issuing a response indicating a success/failure of the abort request; and at least one network interface associated to one of said plurality of processing modules for controlling the communication between said one of said plurality of processing modules and said interconnect, wherein said at least one transaction abortion unit is arranged in one of said network interfaces; wherein said at least one network interface further comprise a request buffer for buffering received data; and wherein said transaction abortion unit is adapted to issue a discard for said at least one transaction to be aborted as stored in said request buffer.