Patent ID: 8873607

Claim:
A communication interface device for a processor, comprising: a sampler that samples a receive signal received via a communication line; a data transfer rate acquirer that acquires a data transfer rate; a bit determiner that makes a bit determination regarding the receive signal at the acquired data transfer rate acquired by the data transfer rate acquirer, to thereby acquire serial data contained in the receive signal; a transmitter that sends, via a communication line at the acquired data transfer rate acquired by the data transfer rate acquirer, a transmit signal containing serial data sent by the processor; a processor communicator that outputs to the transmitter the serial data sent by the processor, and outputs to the processor the serial data acquired by the bit determiner; and an adjuster that, when the transmitter sends the transmit signal multiple times at different data transfer rates, adjusts the data transfer rate based on the receive status of respective response signals thereto.