Patent ID: 8537258

Claim:
A solid-state imaging device comprising: a plurality of pixel sections including, respectively, photoelectric converting circuits which include photodiodes for generating charges corresponding to intensities of incident lights and output voltages corresponding to the amounts of the generated charges, and holding circuits which hold voltages output from the photoelectric converting circuits and successively output the charges to a common wire, the amounts of the charges output to the common wire corresponding to the held voltages; a transimpedance circuit including a first amplifier, a first capacitor, and a resistor, where the first capacitor and the resistor are connected in parallel to each other and provided between an input terminal and an output terminal of the first amplifier, and the input terminal of the first amplifier is connected to the common wire; and an integrating circuit which includes a second amplifier, a second capacitor, and a switch, where the second capacitor and the switch are connected in parallel to each other and provided between an input terminal and an output terminal of the second amplifier, and the input terminal of the second amplifier is connected to the output terminal of the first amplifier of the transimpedance circuit, wherein the transimpedance circuit is connected to the integrating circuit so as to transmit a pulse current from the transimpedance circuit to the integrating circuit, wherein each of the plurality of pixel sections includes a first holding circuit and a second holding circuit as a holding circuit, and the solid-state imaging device further comprises: a first common wire connected to the first holding circuit and a second common wire connected to the second holding circuit as the common wire; a first transimpedance circuit connected to the first common wire and a second transimpedance circuit connected to the second common wire as the transimpedance circuit; a first integrating circuit connected to the first transimpedance circuit and a second integrating circuit connected to the second transimpedance circuit as the integrating circuit; and a difference arithmetic circuit which inputs voltages output from the first integrating circuit and the second integrating circuit, respectively, and outputs a voltage corresponding to a difference between the input two voltages, and wherein the capacity of a capacitor for holding a voltage in the holding circuit is in the range of 1 pF to 2 pF.