Patent ID: 8717824

Claim:
A system comprising: a calibration module configured to generate a plurality of calibration codes respectively for a first plurality of transistors located along (i) a plurality of bit lines and (ii) a first word line of a memory array, wherein each of the calibration codes is based on a distance of a corresponding one of the plurality of bit lines from an input of the first word line; a voltage generator configured to generate a first voltage based on a first plurality of codewords, and output the first voltage to an input of a second word line of the memory array; and a control module configured to determine values of threshold voltages of a second plurality of transistors located along (i) the plurality of bit lines and (ii) the second word line based on (a) the first plurality of codewords and (b) currents sensed through the second plurality of transistors in response to the first voltage being output to the input of the second word line, and adjust the values of the threshold voltages of the second plurality of transistors based on the calibration codes.