Patent ID: 8730703

Claim:
The semiconductor integrated circuit device comprising: a first circuit block to be put under a first low-power-consumption control operation; a second circuit block to be put under the first low-power-consumption control operation and a second low-power-consumption control operation; a power supply switch control section for outputting control signals when each low-power-consumption control operation is judged to be allowed in the first and second circuit blocks; a first power supply switch section for performing the first low-power-consumption control operation by cutting off a reference potential fed to the first circuit block in accordance with a control signal output from the power supply switch control section; a second power supply switch section for performing the second low-power-consumption control operation by cutting off a reference potential fed to the second circuit block in accordance with a control signal output from the power supply switch control section; and a frequency/power supply control section for performing the second low-power-consumption control operation by dynamically varying an operating frequency and a core voltage fed to the second circuit block; wherein a first sending-side level shifter sends an output signal from the first circuit block, wherein a first receiving-side level shifter receives a signal sent from a second sending-side level shifter, providing the first circuit block with a signal converted to a voltage level of a power supply amplitude used for the first circuit block, wherein the second sending-side level shifter sends an output signal from the second circuit block, and a second receiving-side level shifter receives a signal sent from the first sending-side level shifter, converts the thus received signal into a signal having a voltage level of a power supply amplitude used for the second circuit block, and provides the thus converted signal to the second circuit block, wherein the first circuit block and the first power supply switch section are formed in a first WELL isolation region formed over a semiconductor substrate, wherein the second circuit block and the second power supply switch section are formed in a second WELL isolation region formed over the semiconductor substrate separately from the first WELL isolation region, and wherein the first receiving-side level shifter, the first sending-side level shifter, the second receiving-side level shifter, and the second sending-side level shifter are formed in a third WELL isolation region other than the first and second WELL isolation regions formed over the semiconductor substrate.