Patent ID: 7482695

Claim:
A semiconductor device comprising: a plurality of semiconductor chips stacked and packaged, at least one of the plurality of semiconductor chips including: an adhesive layer formed on an entire surface of an element-forming surface of the semiconductor chip; a bump formed on a pad on the semiconductor chip and in the adhesive layer, the bump projecting from the adhesive layer; and a bonding wire which is bonded to a projecting portion of the bump, the bonding wire electrically connecting the bump to a wiring layer formed on a printed circuit board, wherein a semiconductor chip of the plurality of semiconductor chips which is arranged in an upper stage is smaller than a semiconductor chip of the plurality of semiconductor chip which is arranged in a lower stage, and wherein said at least one semiconductor chip includes a semiconductor chip having substantially a same size as the semiconductor chip of the lower stage, said device further comprising: a spacer smaller than the plurality of semiconductor chips and interposed between the semiconductor chips having substantially the same size; and a fillet provided between the spacer and the semiconductor chips and covering a connection between the bump and the bonding wire.