Patent ID: 7015106

Claim:
A method of manufacturing a double gate field effect transistor, comprising: forming a pad insulating layer on a semiconductor substrate; forming a first hard mask layer pattern on the pad insulating layer; forming a pad insulating layer pattern and fins by sequentially etching the pad insulating layer and the substrate using the first hard mask layer pattern as a etch mask; forming an non-channel gate oxide film on the substrate in areas where no fins are formed; forming a second hard mask layer pattern that covers the fins and a portion of the non-channel gate oxide film on the substrate; forming trenches on the substrate by etching the non-channel gate oxide film and the substrate using the second hard mask layer pattern as an etch mask; forming device isolation insulating film patterns in the trenches; forming channel gate oxide films on the first side face and the second side face of the fins; and forming a gate line that surrounds the channel gate oxide film and the pad insulating layer pattern.