Patent ID: 7450043

Claim:
A system for compensation of deterministic jitter in measurements made when utilizing a plurality of time interleaved analog-to-digital converters (ADCs) comprising: edge timing measurement error information for each of the plurality of time interleaved ADCs, the edge timing error information being defined, in a calibration phase, as a relationship for compensation of deterministic jitter in measurements made when utilizing a plurality of time interleaved analog-to-digital converters (ADCs), by: detecting a multitude of edges of a waveform; determining measured edge times corresponding to the multitude of edges; determining edge timing measurement errors based upon the comparison of ideal edge times and the measured edge times by associating a value of each measured edge time in relation to the associated one or more time interleaved ADCs to form a scatter relationship, and determining deterministic errors in accordance with the scatter relationship; and associating each edge timing measurement error with one or more of the time interleaved ADCs; and a processing element for converting a measured edge time of one or more edges of a waveform into a corrected edge time; wherein the processing element determines the corrected edge time by subtracting the edge timing measurement error corresponding to one or more of the time interleaved ADCs.