Patent ID: 8502394

Claim:
A multi-stack semiconductor dice assembly, comprising: a first semiconductor die having at least one integrated circuit therein, the first semiconductor die having an upper and a bottom surface, the bottom surface having a first plurality of contact pads thereon; a second semiconductor die having a bottom surface and an upper surface, the upper surface including a first semiconductor region and a second semiconductor region, the second semiconductor region being raised with respect to the first semiconductor region, the first semiconductor region having a first plurality of attachment structures, the second semiconductor die having at least one integrated circuit therein; a first plurality of electrically conductive balls, each electrically conductive ball of the first plurality of electrically conductive balls extending between and adhered to a respective contact pad of the bottom surface of the first semiconductor die and a respective attachment structure of the first semiconductor region of the second semiconductor die; a first plurality of contact pads on the bottom surface of the second semiconductor die; and a second plurality of contact pads on the bottom surface of the second semiconductor die at least partially circumscribing the first plurality of contact pads on the bottom surface of the second semiconductor die, wherein each contact pad of the second plurality of contact pads on the bottom surface of the second semiconductor die is electrically isolated from the at least one integrated circuit of the second semiconductor die.