Patent ID: 8048753

Claim:
A method of fabricating shallow trench isolation silicon-on-insulator (SOI) devices, the method comprising: forming an insulating layer on a bulk silicon substrate; forming an active silicon layer on the insulating layer; forming a transistor on the active silicon layer, the transistor including source/drain regions formed in the active silicon layer; forming a diode on the active silicon layer, the diode including two active regions; forming an interlayer dielectric on the transistor and the diode; forming first, second, third, and fourth contact holes through the interlayer dielectric; filling the first, second, third, fourth contact holes with a conductive material to form first, second, third, and fourth conductive contacts; and forming first and second metal lines on the interlayer dielectric; wherein the first conductive contact connects the drain region of the transistor with the first metal line, the second conductive contact connects one active region of the diode with the first metal line, the third conductive contact connects the second active region of the diode with the second metal line, and the fourth conductive contact connects the second metal line to the bulk silicon layer to form a charging protection device.