Patent ID: 8233321

Claim:
A semiconductor memory device comprising: a plurality of memory cell transistors arranged in a matrix; a plurality of bit lines coupled to a bit line drive circuit controlling a first potential of the plurality of bit lines, the plurality of bit lines include: (i) a bit line coupling to drains of a first set of the plurality of memory cell transistors arranged in a first column and (ii) a second bit line coupling to drains of a second set of the plurality of memory cell transistors arranged in a second column; a plurality of word lines coupled to a word line driver circuit controlling a second potential of the plurality of word lines, the plurality of word lines include: (i) a first word line coupling to gate electrodes of a first set of the plurality of memory cell transistors arranged in a first row and (ii) a second word line coupling to gate electrodes of a second set of the plurality of memory cell transistors arranged in a second row; a plurality of source lines include: a source line coupling to sources of the plurality of memory cell transistors arranged in the first and second rows; a first transistor having a drain coupled to at least one of the plurality of source lines; a second transistor having a drain coupled to a source of the first transistor, and a source coupled to a third potential.