Patent ID: 8095742

Claim:
A microcomputer comprising: a first CPU capable of processing a predetermined task; a first bus coupled with the first CPU; a first memory accessed by the first CPU through the first bus and used as a local memory of the first CPU; a second CPU capable of processing a predetermined task; a second bus coupled with the second CPU; and a second memory accessed by the second CPU through the second bus and used as a local memory of the second CPU, wherein the first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding thereto, wherein the microprocessor further comprises an address translation circuit configured to translate an address output from the second CPU so that access to the first memory by the task becomes access to the second memory when a task so programmed that the task has a data area in the first memory is transferred to the second memory and executed by the second CPU, and wherein the address translation circuit includes a first register capable of holding the initial address of each task in the first memory; a second register capable of holding information on the size of the task; a third register capable of holding the initial address of each task in the second memory; a determination unit configured to determine whether or not an address output from the second CPU falls within an address range determined by information held in the first register and information held in the second register; and a translation unit configured to carry out address translation by adding information held in the third register to the address output from the second CPU when an address output from the second CPU is within the address range.