Patent ID: 8878156

Claim:
A memory device comprising: a semiconductor substrate having a plurality of parallel trenches therein, each of said trenches having a respective one of a plurality of trench bottoms and a respective pair of a plurality of paired trench sidewalls; a memory region formed in said semiconductor substrate, said memory region including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in said trench sidewalls; a plurality of buried source electrodes formed in said trench bottoms, said buried source electrodes coupled to said memory cells along a first direction substantially parallel to said trenches; a plurality of parallel bit lines coupled to said memory cells along a second direction substantially orthogonal to said first direction; a plurality of paired gate electrodes formed on said paired trench sidewalls, said gate electrodes coupled to said memory cells along said first direction; a first and a second stitch region disposed adjacent said memory region along said first direction including a first and a second row of gate contacts formed in said trenches along said second direction, respectively; and a row of source contacts disposed in said trenches along said second direction in said first or said second stitch region, each of said source contacts coupled to a respective one of said buried source electrodes, wherein one of each pair of said gate electrodes formed on a respective pair of said trench sidewalls is coupled to a respective one of said first row of gate contacts disposed in a respective one of said trenches and the other one of each pair of said gate electrodes is coupled to a respective one of said second row of gate contacts disposed in said respective one of said trenches.