Patent ID: 7139195

Claim:
An electrically erasable and programmable memory comprising: a substrate; a memory array comprising a plurality of normal memory cells arranged in rows and columns on said substrate; a plurality of normal bit lines coupled to the columns of said plurality of normal memory cells, and a plurality of word lines coupled to the rows of said plurality of normal memory cells; a row decoder on said substrate and coupled to said plurality of normal bit lines, and a column decoder on said substrate coupled to said plurality of word lines; a read circuit on said substrate and coupled to said memory array; and a non-volatile register on said substrate and integrated with said memory array, and comprising at least one memory point comprising at least one normal memory cell coupled to one of said plurality of normal bit lines and being erase and program accessible through said row and column decoders, said at least one normal memory cell comprising a floating-gate transistor comprising a floating gate and a tunnel window associated with said floating gate, and a selection transistor coupled to said floating-gate transistor, at least one special memory cell comprising a floating-gate transistor comprising a floating gate coupled to the floating gate of said at least one normal memory cell, said floating gate transistor being devoid of a tunnel window, and a special bit line coupled to said at least one special memory cell so that said at least one memory point can be read.