Patent ID: 7705648

Claim:
A circuit for detecting a condition of a monitored signal, comprising: a mode monitor circuit that is arranged to detect a first condition associated with the monitored signal and to assert a first condition signal if the first condition occurs and persists for a first duration; a PWM stoppage circuit that is arranged to detect a second condition associated with the monitored signal and to assert a second condition signal if the second condition occurs and persists for a second duration; and a latch circuit that is arranged to provide a status signal, wherein the status signal is based, in part, on the first condition signal and the second condition signal, wherein the mode monitor circuit includes: a first counter, wherein the first counter is arranged to count clock cycles during which PWM switching is present on the monitored signal, wherein the first counter is arranged to assert the first condition signal if the first counter reaches a first predetermined value, and wherein the PWM stoppage circuit includes: a second counter, wherein the second counter is arranged to count clock cycles during which PWM switching is absent on the monitored signal, and wherein the second counter is arranged to assert the second condition signal if the second counter reaches a second predetermined value.