Patent ID: 8743651

Claim:
A memory comprising: a memory array having a plurality of word lines; a plurality of latching predecoders, wherein each of the latching predecoders comprises: a latch; a first transistor of a first conductivity type having a first current electrode coupled to a power supply voltage, a second current electrode coupled to the latch, and a control electrode coupled to a clock signal; a second transistor of a second conductivity type, opposite the first conductivity type, having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode coupled to a first address bit signal; a third transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the second transistor, a second current electrode, and a control electrode coupled to a second address bit signal; a fourth transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to a delayed and inverted version of the clock signal, and a second current electrode; a fifth transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode coupled to the clock signal, and a second current electrode coupled to ground; and an output, wherein the output provides a predecode value corresponding to a latched value in the latch during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle of the clock signal, wherein the predecode value represents a logic function of the first and second address bit signals; and word line driver logic coupled between the plurality of latching predecoders and the memory array, wherein the word line driver logic activates a selected word line of the plurality of word lines based on the predecode values provided by the plurality of latching predecoders during the first portion of the clock cycle.