Patent ID: 7448025

Claim:
An apparatus, comprising: a processor to execute a plurality of threads simultaneously, each thread including a series of instructions and resulting in an event; an event selection control register (ESCR) coupled to the processor; a first multiplexer coupled to the ESCR to select a class of events, based on a first set of control signals from the ESCR, from a group of event signals issued from the processor; second multiplexer coupled to the ESCR and the first multiplexer to mask, based on a second set of control signals from the ESCR, subclasses of the class of events in order to select an event that belongs to a subclass that is not masked; a logic circuit coupled to the ESCR and the second multiplexer to qualify the event based on a thread ID and a thread current privilege level (CPL), the thread ID indicating a source of the event including a thread of the plurality of threads where the event occurred; and an event counter to count the event qualified by the logic circuit.