Patent ID: 7507625

Claim:
A method for manufacturing a flash memory device, comprising: forming a tunneling oxide layer in an active region of a semiconductor substrate further including a device isolation region having an isolation layer therein; forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer; forming insulation sidewall spacers on sides of the floating gate and the control gate, wherein a first insulation sidewall spacer is over the active region and a second insulation sidewall spacer is over the device isolation region in a cross-section of the floating gate, the gate insulation layer, the control gate, and the insulation sidewall spacers; forming a photoresist pattern over the first insulation sidewall spacer and part of the floating gate, the gate insulation layer, and the control gate exposing the second insulation sidewall spacer and the device isolation layer; exposing a source region by selectively removing portions of the device isolation layer using the photoresist pattern and the second insulation sidewall spacer as an etching mask, wherein a portion of the device isolation layer remains below the second insulation sidewall in the device isolation region; and implanting impurity ions into the source region.