Patent ID: 8609496

Claim:
A method of fabricating a semiconductor device, comprising: forming a first gate insulating layer having a first thickness on a substrate; forming a mask pattern on the first gate insulating layer, the mask pattern comprising an opening exposing the first gate insulating layer; partially removing the first gate insulating layer through the opening to form a second gate insulating layer having a second thickness less than the first thickness; implanting first ions having a first conductive type into the substrate through the opening to a first depth to form a first well; implanting second ions having a second conductive type into the substrate through the opening to a second depth, shallower than the first depth, to form a second well, wherein the second conductive type is opposite to the first conductive type; removing the mask pattern after forming the first well and the second well; forming an implanting mask pattern on the first gate insulating layer and the second gate insulating layer, the implanting mask pattern exposing a portion of the first gate insulating layer and a portion of the second gate insulating layer directly under that the first well and the second well are formed; implanting third ions having the first conductive type into the substrate to a third depth less than the first depth to form a third well, directly under the first gate insulating layer, and to form a fourth well within the first well; forming a first transistor on the first gate insulating layer; and forming a second transistor on the second gate insulating layer.