Patent ID: 7358827

Claim:
A phase locked loop comprising: a phase frequency detector comparing an input clock signal to a feedback clock signal to generate an up signal and a down signal; a main charge pump circuit providing charge to a loop filter capacitor connected to an output terminal thereof in response to the up signal and the down signal; a first amplifier amplifying the voltage of the loop filter capacitor; an auxiliary charge pump circuit providing charge to an output terminal of the first amplifier in response to the up signal and the down signal; a second amplifier amplifying an output voltage of the first amplifier; a voltage-controlled oscillator generating an oscillating clock signal in response to an output voltage of the second amplifier; a divider frequency-dividing the oscillating clock signal to generate the feedback clock signal; and a bias circuit generating a first bias current using an NMOS transistor, generating a second bias current using a PMOS transistor, and summing the first and second bias currents to generate a third bias current in response to the output voltage of the second amplifier, wherein the first bias current is provided as bias currents to the main charge pump circuit and the auxiliary charge pump circuit and wherein the third bias current is provided as a bias current to the first amplifier.