Patent ID: 7605434

Claim:
A semiconductor memory device comprising: a first bank including a first block in which a plurality of first memory cells are arranged in a matrix; a plurality of first bit lines connected to said plurality of first memory cells; a first data line connected to even-numbered bit lines of said plurality of first bit lines via a column selection transistor, and a second data line connected to odd-numbered bit lines of said plurality of first bit lines via a column selection transistor; and a first write load circuit which applies a first write voltage corresponding to write data to the first data line and the second data line at the time of data write, a second bank including a second block in which a plurality of second memory cells are arranged in a matrix; a plurality of second bit lines connected to said plurality of second memory cells; a third data line connected to even-numbered bit lines of said plurality of second bit lines via a column selection transistor, and a fourth data line connected to odd-numbered bit lines of said plurality of second bit lines via a column selection transistor; and a second write load circuit which applies a second write voltage corresponding to write data to the third data line and the fourth data line at the time of data write, and a bank decoder which selects a bank to be activated from the first bank and the second bank, wherein when testing operations of said plurality of first memory cells and said plurality of second memory cells, the bank decoder simultaneously selects the first bank and the second bank, and the first write load circuit and the second write load circuit simultaneously write data in memory cells in the first block and memory cells in the second block.