Patent ID: 7558909

Claim:
A content addressable memory comprising: an array of content addressable memory cells, the array comprising a matchline row comprising data bit cells and control cells, wherein the matchline row is coupled to a matchline, and wherein the matchline is configured to provide a search result corresponding to a match state of the matchline; a match processing circuit associated with the matchline row, wherein the match processing circuit is configured to perform a deletion operation, the deletion operation comprising marking the contents of the matchline row for deletion if (i) the contents of the matchline row correspond to a last word segment of a first wide word or (ii) the contents of the matchline row do not correspond to a last word segment of a second wide word and the match processing circuit receives a match flag from an adjacent match processing circuit indicating that the contents of a lower adjacent matchline row have been marked for deletion; an address decoder for addressing the data bit cells and the control cells; write data circuitry for writing data to the data bit cells and the control cells; and, search data circuitry for writing search data onto searchlines.