Patent ID: 8051230

Claim:
A method of transmitting data between a master device and a slave device via a clock line and at least one data line, the clock line being maintained by default on a first logic value, and each master and slave device being able to tie the clock line to a potential representing a second logic value opposite the first logic value, the method comprising: when the master device sending data to the slave device and the slave device is receiving the data from the master device, then the master device applies data to the data line, then ties the clock line to the second logic value, the slave device detects the second logic value on the clock line, then ties the clock line to the second logic value and reads the data, the slave device maintains the tie to the clock line at the second logic value while the slave device has not read the data, the slave releases the tie to the clock line at the second logic value when the slave device has read the data, and the master device maintains the data on the data line at least until an instant when the clock line is released by the slave device, the master device releases the data on the data line after the clock line is released by the slave device and by the master device; and when the slave device is sending data to the master device and the master device is receiving the data from the slave device, then the master device ties the clock line to the second logic value, the slave device detects the second logic value on the clock line, then ties the clock line to the second logic value, and then or simultaneously applies the data to the data line, the master device maintains the tie to the clock line at the second logic value while the master device has not read the data, the master device releases the tie to the clock line at the second logic value when the master device has read the data, the slave device maintains the data on the data line at least until an instant when the clock line is released by the master device, and the slave device releases the data on the data line after the clock line is released by the master device and the slave device, and with the slave device tying the clock line to the second logic value every time the master device has tied the clock line to the second logic value, regardless of the direction in which the data is transmitted.