Patent ID: 7067391

Claim:
A method to form metal silicide gates in the fabrication of an integrated circuit device, said method comprising: forming polysilicon lines overlying a substrate wherein said polysilicon lines have dielectric sidewalls; forming a first isolation layer overlying said substrate and said dielectric sidewalls wherein said first isolation layer does not overlie the top surface of said polysilicon lines; partially etching down said polysilicon lines such that said top surfaces of said polysilicon lines are below the top surface of said dielectric sidewalls; thereafter depositing a metal layer overlying said polysilicon lines; thermally annealing to completely convert said polysilicon lines to metal silicide gates; and removing unreacted said metal layer to complete said device; wherein said polysilicon lines are covered by a hard mask layer prior to said step of partially etching down said polysilicon lines and further comprising: depositing a second metal layer overlying said substrate, said spacers, and said hard mask layer prior to said step of partially etching down said polysilicon lines; thermally annealing to convert a part of said substrate in said second doped regions to metal silicide; and removing unreacted said second metal layer.