Patent ID: 8140936

Claim:
A memory system comprising: a memory hub device integrated in a memory module; and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external memory controller, wherein the link interface comprises: first error checking and correcting (ECC) logic integrated in the link interface and first cyclic redundancy check (CRC) logic integrated in the link interface, wherein: the external memory controller sends first data to the link interface using ECC code bits thereby setting the memory hub device into an ECC mode when a plurality of memory bits lanes in a first memory channel are not experiencing failures above a predetermined level, the external memory controller sends the first data to the link interface using CRC code bits thereby setting the memory hub device into a CRC mode when at least one of the memory bit lanes in the plurality of memory bits lanes in the first memory channel is experiencing failures above the predetermined level, responsive to receiving the first data with the ECC code bits, the first ECC logic performs error correction operations on the first data that is received from the external memory controller via the first memory channel to be transmitted to a set of memory devices, the first ECC logic generates a first error signal to the external memory controller in response to the first ECC logic detecting a first error in the first data, responsive to receiving the first data with the CRC code bits, the first CRC logic performs error detection operations on the first data that is received from the external memory controller via the first memory channel to be transmitted to the set of memory devices, and the first CRC logic generates the first error signal to the external memory controller in response to the first CRC logic detecting the first error in the first data; and link interface control logic integrated in the link interface, wherein the link interface control logic controls the transmission of the first data to the set of memory devices.