Patent ID: 7618860

Claim:
A method for fabricating a semiconductor device, comprising: forming a first insulating layer over a substrate where a landing contact plug is formed; forming an etch barrier pattern having a line type open region over the first insulating layer; forming a second insulating layer for planarization over the etch barrier pattern; forming a contact mask having a hole type open region over the second insulating layer; performing a self-aligned contact etching process using the etch barrier pattern to etch the second insulating layer disposed under the hole type open region and the first insulating layer disposed under the line type open region to form a contact hole a bottom of which is opened above the landing contact plug; forming a storage node contact plug in the contact hole; and forming a storage node over the storage node contact plug, wherein the hole type open region has a rectangular hole structure with a major axis and a minor axis, and in the major axis direction, one side of the hole type open region is aligned along one side of the etch barrier pattern and another side of the hole type open region is partially overlapped with the etch barrier pattern.