Patent ID: 7538706

Claim:
A MASH modulator, comprising: first, second, and third cascaded accumulators; first and second adders respectively coupled to the first and second accumulators; a first delay unit coupled between the first and second adders; a second delay unit coupled between the second adder and the third accumulator; first and second multipliers, each coupled between a corresponding adder and a corresponding accumulator, multiplying an output value of the corresponding accumulator by a first predetermined number; a third multiplier, coupled between the second delay unit and the third accumulator, multiplying an output value of the third accumulator by the first predetermined number; a third adder, coupled between the first adder and an output of the MASH modulator, adding a second predetermined number to an output value from the first adder; a fourth adder, coupled to an input of the MASH modulator, adding a third predetermined number to an input value thereof; a fourth multiplier, coupled between the fourth adder and an input of the first accumulator, multiplying an output value of the fourth adder by a fourth predetermined number; wherein the third predetermined number is a negative of the second predetermined number, the fourth predetermined number is an inverse of the first predetermined number, and the predetermined numbers are determined according to the input value.