Patent ID: 7193450

Claim:
An apparatus including a load sensing buffer circuit for providing a buffered clock signal with controlled switching current noise (di/dt), comprising: an input electrode to convey an input clock signal; an output electrode to convey, to a load capacitance, a buffered clock signal corresponding to said input clock signal; and buffer amplifier circuitry coupled between said input and output electrodes, and including input amplifier circuitry coupled to said input and output electrodes, and responsive to said input clock signal by providing first and second components of said buffered clock signal and a first intermediate signal corresponding to said input clock signal, and output amplifier circuitry coupled to said input electrode, said output electrode and said input amplifier circuitry, and responsive to said input clock signal and said first intermediate signal by providing at least a third component of said buffered clock signal and at least a second intermediate signal corresponding to said input clock signal.