Patent ID: 7446573

Claim:
A comparator system comprising: a plurality of multiplexers adapted to multiplex a number of differential input signals and a number of differential reference signals; a differencing circuit adapted to receive a differential input signal and a differential reference signal from the multiplexers and provide a differential output signal; a comparator adapted to receive the differential output signal and provide a differential comparator output signal; and a latch adapted to perform differential-to-single ended conversion on the differential comparator output signal to provide a latch output signal, and an output circuit adapted to receive the latch output signal and process the latch output signal to provide a registered digital output signal, wherein: the latch and the output circuit are controlled by at least a first timing control signal; the output circuit and the multiplexers are controlled by at least a second timing control signal; and the output circuit processes the latch output signal with a window function and at least one filter.