Patent ID: 8742805

Claim:
A power on reset (POR) device comprising: a power supply unit providing a power supply voltage; a delay signal generating unit delaying and outputting the power supply voltage provided from the power supply unit by a predetermined time; and a reset signal generating unit comparing a signal output from the delay signal generating unit with a predetermined reference voltage to generate a reset signal, wherein the delay signal generating unit includes: a first capacitor having the power supply voltage applied to one end thereof, a first no connected to the other end of the first capacitor, a first transistor having a first terminal connected to the first node and a second terminal connected to a ground, a second transistor having a first terminal connected to one end of the first capacitor and a control terminal connected to the first node, a second node connected to a control terminal of the first transistor and a second terminal of the second transistor, and a second capacitor having one end connected to the second node and the other end connected to the ground, and the delay signal generating unit outputs a voltage value of the second capacitor.