Patent ID: 6916711

Claim:
A method of forming an EEPROM memory cell, comprising: forming a trench in a predetermined region of a substrate; forming a gate insulation layer on an entire surface of the substrate where the trench is formed; implanting impurity ions into the trench bottom; removing the gate insulation layer of at least one of the trench bottom and the predetermined region adjacent to the trench to expose the substrate; forming a tunneling insulation layer on the exposed substrate; implanting impurity ions into one sidewall of the trench using an oblique ion implantation process; sequentially conformally forming a first conductive layer and a dielectric layer on an entire surface of the substrate; successively patterning the dielectric layer and the first conductive layer to form a floating gate and a dielectric layer pattern, wherein the floating gate covers the bottom and sidewalls of the trench and the dielectric layer pattern is formed on the floating gate; forming a sidewall oxide layer on sidewalls of the floating gate; forming a second conductive layer on an entire surface of the substrate having the floating gate; patterning the second conductive layer to form a sensing line and a word line that are parallel with each other, wherein the sensing line crosses the floating gate, and the word line is disposed in the vicinity of the trench sidewalls into which the impurity ions are implanted, perpendicularly to a normal line of the trench sidewalls; and implanting impurity ions into the substrate of both sides of the sensing line and the word line.