Patent ID: 8482129

Claim:
A method of forming a semiconductor package, comprising: providing a first semiconductor device and a second semiconductor device, each of the first and second semiconductor devices comprising: an integrated circuit region formed on a semiconductor substrate; a first conductive layer pattern overlying the integrated circuit region, wherein a via hole extends through the first conductive layer pattern and the integrated circuit region and into a portion of the semiconductor substrate; an inter-metal dielectric (IMD) layer overlying the first conductive layer pattern, the IMD layer disposed on a bottom and sidewalls of the via hole; an uppermost conductive layer pattern overlying the IMD layer and within the via hole; a plug formed in the via hole; and an uppermost dielectric layer overlying the uppermost conductive layer pattern; and disposing the first semiconductor device below the bottom surface of the semiconductor substrate of the second semiconductor device, wherein an upper surface of the plug in the first semiconductor device is electrically connected to the portion of the uppermost conductive layer pattern of the second semiconductor device.