Patent ID: 8099655

Claim:
A multiplier circuit for multiplying a first polynomial B(x) by a second polynomial C(x), B(x) and C(x) being part of a Galois field GF(2 m ) and being representable in binary format as B[m−1:0] and C[m−1:0] respectively, the multiplier circuit comprising: a first sub-circuit having: a first logic gate unit having a first group of inputs, each input of the first group of inputs for receiving bit B[m−1], the first logic gate unit further having a second group of inputs, each input of the second group of inputs for receiving the bits of a primitive polynomial P(x) of GF(2 m ), P(x) being representable in binary format as P[m−1:0], the first logic gate unit for multiplying the first group of inputs and the second group of inputs to obtain (B[m−1]*P[m−1:0])[m−1:0]; a shifting device for receiving B[m−1:0] and for shifting by 1 bit to the left the bits of B[m−1:0] to obtain LS_B[m−1:0]; and a second logic gate unit for receiving, and for adding, (B[m−1]*P[m−1:0])[m−1:0] and LS_B[m−1:0] to obtain (B(x)*x)[m−1:0]; and, a second sub-circuit having: an input for receiving (B(x)*x)[m−1:0] from the first sub-circuit; inputs for receiving B[m−1:0], C[m−1:0] and P[m−1:0]; and a logic unit for calculating, in accordance with (B(x)*x)[m−1:0], B[m−1:0], C[m−1:0] and P[m−1:0], (C[k]*B(x)*x k )[m−1:0] for each value of k ranging from 0 to m−1, k being an integer, and for summing together (C[k]*B(x)*x k )[m−1:0] for k ranging from 0 to m−1, to obtain (B(x)*C(x))[m−1:0].