Patent ID: 8395434

Claim:
A level shifter circuit connectable to receive an input voltage at a first node, to receive an enable signal, and to supply an output voltage at a second node, the level shifting circuit comprising: a first depletion type NMOS transistor connected between the first node and a first internal node and having a gate connected to the second node; a first PMOS transistor connected between the first internal node and the second node and having a gate connectable to receive the enable signal; an inverter connectable to receive the enable signal and provide as output an inverted enable signal; and a negative voltage section connectable to receive a negative voltage level at a third node, including: a second PMOS transistor connected between the enable signal and a second internal node; a first NMOS transistor connected between the second internal node and third node; a third PMOS transistor connected between the inverted enable signal and a third internal node; and a second NMOS transistor connected between the third internal node and third node, wherein the control gates of the second and third PMOS transistors are connected to ground, the second internal node is connected to the gate of the second NMOS transistor, and the third internal node is connected to the gate of the first NMOS transistor and the second node.