Patent ID: 7746141

Claim:
A delay circuit comprising: a delay time setting circuit to delay a signal input to an input terminal and output the signal as an output signal to an output terminal, wherein an output of a single first transistor is connected to an input of the delay time setting circuit to set a first voltage of said delay time setting circuit or to set an open state of said delay time setting circuit, according to a conduction state of said single first transistor, and an output of the delay time setting circuit is set to a second voltage or an open state according to a conduction state of another transistor of an opposite conductivity type to the first transistor, wherein a control terminal of a first transistor of a delay circuit in a second and subsequent stages among a plurality of delay circuits connected in series is connected to an input terminal of the delay time setting circuit in a previous stage, and a control terminal of a second transistor of the delay circuit in the second and subsequent stages is connected to an output terminal of the delay time setting circuit in a previous stage.