Patent ID: 8043967

Claim:
A method of plating a through silicon via for connecting at least two integrated circuits, wherein the through silicon via has a diameter of at least about 3 micrometers and a depth of at least about 20 micrometers, the method comprising: contacting a structure having a through silicon via hole with a plating solution having copper ions at a concentration of at least about 40 grams per liter and chloride ions at a concentration of no greater than about 2 ppm; and while contacting the structure, plating copper into the through silicon via hole to completely fill the through silicon via hole in a substantially void free manner, wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole, wherein there is substantially no net deposition of copper onto field regions of the structure between a plurality of through silicon via holes while plating copper.