Patent ID: 8624362

Claim:
An IC wafer fabrication method for fabricating the IC wafer defining a plurality of die zones, each of which is adapted to be embedded with an electronic device and provided with a border area adapted to be arranged with a plurality of conductive bumps electrically connected to the electronic device for being used in a further packaging process, the IC wafer fabrication method comprising the steps of: a) forming an integrated circuit layer carrying said electronic device therein and having a top surface on which a plurality of solder pads are arranged and respectively electrically connected to said electronic device; b) applying an insulated layer covering said solder pads on the top surface of said integrated circuit layer; c) forming a seed layer covering said insulated layer and said solder pads; d) forming a photoresist layer on a top surface of said seed layer, and then patterning said photoresist layer to form an opening in each of said die zones, and then filling a shielding block in each said opening such that said shielding block and a part of said seed layer which is combined beneath said shielding block form an electromagnetic shielding layer; and e) removing a residual of said photoresist layer from said seed layer and making the part of said seed layer, which is combined with said shielding block, be spaced laterally from each of said solder pads.