Patent ID: 7432903

Claim:
A common inversion type liquid crystal display apparatus comprising: a plurality of signal lines; a plurality of scan lines; a common electrode; a plurality of pixel units located at intersections between said signal lines and said scan lines and connected to said common electrode; a common voltage generating circuit, connected to said common electrode, for inverting a common voltage applied to said common electrode for every frame and every scan line; a scan line driver, connected to said scan lines, for sequentially selecting said scan lines; a signal line driver, connected to said signal lines, for time-divisionally receiving digital video signals each including a plurality of digital color signals and changing a sequence of said digital video signals including said digital color signals for every two consecutive frames to time-divisionally generate an output sequence of analog video signals including analog color signals, so that each of said analog color signals is placed exclusively at predetermined time slots of said output sequence; and a selector circuit, connected between said signal line driver and said signal lines, for time-divisionally supplying the output sequence of said analog video signals including said analog color signals to said signal lines so that said analog color signals are supplied to their corresponding signal lines, wherein said signal line driver comprises: a horizontal shift register circuit for shifting a horizontal start pulse signal in synchronization with a horizontal clock signal to generate latch signals; a plurality of data registers connected to said horizontal shift register circuit, each of said data registers latching said digital video signals in synchronization with a plurality of consecutive ones of said latch signals; a plurality of multiplexers, each connected to one of said data registers for time-divisionally selecting digital output signals of each of said data registers; and a plurality of digtal/analog converters, each connected to one of said multiplexers, for performing digital/analog conversions upon digital output signals of said multiplexers, wherein each of said data registers comprises: a plurality of groups of latch circuits, each group receiving said digital color signals of one of said digital video signals in synchronization with one of said latch signals, wherein said multiplexers comprises: a first multiplexer, connected to said groups of latch circuits, for selecting said digital color signals of one of said groups of latch circuits in synchronization with a first selection signal; a plurality of additional latch circuits, connected to said first multiplexer, for latching said digital color signals selected by said first multiplexer; and a second multiplexer, connected to said additional latch circuits, for selecting one of said digital color signals latched by said additional latch circuits in synchronization with a second selection signal.