Patent ID: 7371618

Claim:
A method of manufacturing a wafer-level chip-size package comprising: preparing a semiconductor wafer having an upper surface and a lower surface, the upper surface including an array of semiconductor devices and a plurality of conductive bumps extending from the semiconductor devices; encapsulating the upper surface and the conductive bumps in a first encapsulant layer and encapsulating the lower surface in a second encapsulant layer, the encapsulation of the upper and lower surfaces occurring substantially simultaneously, wherein encapsulating the upper and lower surfaces of the semiconductor wafer is achieved by injection molding and includes providing a releasing film on an upper surface of a lower mold, providing a releasing film on a lower surface of an upper mold, positioning the semiconductor wafer between the lower mold and the upper mold, closing the lower mold and the upper mold to form a mold cavity containing the semiconductor wafer, injecting the encapsulant into the mold cavity, curing the injected encapsulant to form an encapsulated semiconductor wafer, opening the mold, and removing the encapsulated semiconductor wafer from the mold; and removing an upper portion of the first encapsulant layer to form a substantially planar surface exposing upper surfaces of the conductive bumps.