Patent ID: 8625347

Claim:
A memory device comprising: a plurality of memory cells, each memory cell storing data of N bits (N is a natural number no less than 2); a control unit configured to perform control of applying voltages of a read voltage set including (2 N −1) hard bit read voltages and a plurality of soft bit read voltages to each of the memory cells; and an error correction unit configured to acquire a log likelihood ratio from a log likelihood ratio table on the basis of soft bit data read out by the soft bit read voltages, the error correction unit configured to perform soft decision decoding based on the acquired log likelihood ratio, wherein the control unit performs first tracking for measuring a first threshold voltage distribution of a first tracking range including a predetermined first hard bit read voltage among the plurality of hard bit read voltages, and the error correction unit performs the soft decision decoding based on log likelihood ratios acquired from different log likelihood ratio tables depending on whether a first least frequent voltage acquired from the first threshold voltage distribution is higher or lower than a predetermined reference voltage on the basis of the first hard bit read voltage.