Patent ID: 7518435

Claim:
In an integrated circuit, a biasing circuit configured to rapidly power up an external circuit from a power-down condition, comprising: a first transistor; a first switch coupled to the first transistor, wherein the first switch is open during the power-down condition, and is closed during a subsequent powering up of the external circuit; a current source coupled to a drain terminal of the first transistor through the first switch; a link that connects a gate of the first transistor with the current source bypassing the first switch; a precharge capacitor, wherein a first terminal of the precharge capacitor is connected to the current source bypassing the first switch, such that the precharge capacitor gets charged to a voltage close to a supply voltage via the link to the current source during the power-down condition; a current multiplier, comprising a second transistor, wherein a gate of the second transistor is connected to the gate of the first transistor; and a second switch coupled to the current multiplier, wherein the current multiplier is configured to deliver biasing current to power up the external circuit when the second switch is closed following the power-down condition; and a third switch coupled in parallel with the current source.