Patent ID: 7413996

Claim:
A method of forming a high k gate insulation layer in an integrated circuit on a substrate, the method comprising the sequential steps of: depositing a base layer onto the substrate, depositing a high k layer onto the base layer, depositing a gate electrode layer onto the high k layer, depositing a hard mask layer onto the gate electrode layer, depositing a photoresist layer onto the hard mask layer, removing portions of the photoresist layer to expose portions of the hard mask layer, etching the exposed portions of the hard mask layer and underlying portions of the gate electrode layer to expose portions of the high k layer, removing all remaining portions of the photoresist layer, subjecting the exposed portions of the high k layer to an ion implanted species that causes lattice damage to the exposed portions of the high k layer, while the exposed portions of the hard mask layer remain on the gate electrode layer, etching both the lattice damaged exposed portions of the high k layer to leave the high k gate insulation layer and the base layer with a single etching step.