Patent ID: 8129830

Claim:
An electronic component package, comprising: a package substrate portion constructed by a first silicon substrate in which a through hole is provided, an insulating layer formed on upper and lower surfaces of the first silicon substrate and inner surface of the through hole, and a through electrode filled in the through hole; and a frame portion formed from a second silicon substrate, and stacked on top of a peripheral portion of the package substrate portion to constitute a cavity on the first silicon substrate, the frame portion whose center part is an opening, the opening which penetrates an upper surface to a lower surface of the frame portion; wherein, the through electrode is positioned in the opening, and an upper surface of the through electrode in the cavity is planarized such that a height of the through electrode is set equal to a height of the insulating layer, and the insulating layer formed on the upper surface of the first silicon substrate is directly in contact with the upper surface of the first silicon substrate and is disposed directly below the entire frame portion.