Patent ID: 8148193

Claim:
A method for fabricating a semiconductor device, comprising: forming an active region in a semiconductor substrate; forming a conductive pattern on a predetermined region of the active region; forming an interlayer dielectric pattern on the conductive pattern, the interlayer dielectric pattern including an opening that exposes the predetermined region of the active region; forming a semiconductor pattern in the opening; forming a heater electrode pattern on the semiconductor pattern in the opening; forming a contact hole spaced apart from the opening, wherein the contact hole exposes the conductive pattern; forming a contact plug to substantially fill the contact hole; and forming a phase change material layer on the heater electrode pattern, wherein forming the conductive pattern and the interlayer dielectric pattern comprises: forming a silicide blocking layer over the predetermined region of the active region, the silicide blocking layer exposing a portion of the semiconductor substrate; forming a metal silicide pattern on the exposed portion of the semiconductor substrate; forming the interlayer dielectric pattern including the opening, wherein the opening exposes the silicide blocking pattern; and removing the silicide blocking pattern exposed by the opening.