Patent ID: 7002871

Claim:
A semiconductor integrated circuit device comprising: a memory cell array; an address buffer which receives an address signal that indicates an address of the memory cell array; a latch circuit which latches the address signal output from the address buffer; an address transition detection circuit which detects transition of the address signal latched by the latch circuit upon receiving an address different from that latched by the latch circuit; and a control circuit which comprises a timeout circuit that controls a cycle operation of the memory cell array, controls operations of the address buffer and the latch circuit, causes the latch circuit to latch an address at operation start time, which is output from the address buffer, during the operation of the memory cell array, when the address transition detection circuit detects the transition of the address during the cycle operation, causes the latch circuit to latch, after an end of the operation of the memory cell array, an address that is currently input to the address buffer, and controls to execute the next cycle operation of the memory cell array in accordance with the address latched by the latch circuit.