Patent ID: 8612911

Claim:
A method comprising: estimating power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with a plurality of gates, at least one gate of the plurality of gates having a single output, wherein the estimating comprises, assigning, by a processor, a first gate of plurality of gates into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation; assigning a second gate of the plurality of gates into the priority queue wherein an output of the second gate is directly connected to an input of a resized gate based on performing an incremental circuit calculation; for each gate from the priority queue, performing the following: removing the gate from the priority queue; determining latest and earliest signal arrival times at an output net of the gate under consideration by static timing analysis and calculating a glitch window as difference; calculating a transition metric for the output net based on the glitch window; in response to the gate not being the end of the logic cone being evaluated, adding its fan-out gates to the priority queue; determining an upper bound of signal transitions from the calculated transition metric; and estimating the power consumption based on the upper bound.