Patent ID: 7569895

Claim:
An integrated circuit device having a plurality of bipolar transistors connected in parallel, comprising: a substrate having an insulating layer at a major surface of the substrate; a semiconductor layer formed at the major surface of said substrate; an isolation trench traversing through the semiconductor layer to said insulating layer so that an area of the semiconductor layer is entirely surrounded by the isolation trench at said major surface and electrically isolated from the substrate and the remaining portions of the semiconductor layer; a plurality of device forming regions located in said semiconductor layer so as to be closely spaced from each other through portions of said semiconductor layer without forming device isolation trenches between the device forming regions; a buried collector region buried in each of said device forming regions between said insulating layer and said semiconductor layer, and a base region formed in said semiconductor layer over the corresponding buried collector region and an emitter region formed in said base region within each of said device forming regions, so as to configure the bipolar transistor in each of said device forming regions including the corresponding buried collector region.