Patent ID: 7807999

Claim:
An array substrate comprising: a first gate line; a second gate line that is electrically insulated from the first gate line; a data line crossing the first and second gate lines to define a pixel region that includes first and second regions; a first switching device that is electrically connected to the first gate line and the data line; a second switching device that is electrically connected to the second gate line; a transmissive electrode that is electrically connected to the second switching device, the transmissive electrode being formed in the first region; a reflective electrode that is electrically insulated from the transmissive electrode, the reflective electrode being formed in the second region that is adjacent to the first region; and a compensating wiring that is electrically connected to the first switching device, the same compensating wiring facing the reflective electrode and the transmissive electrode with an insulation layer interposed between the compensating wiring and the reflective electrode and between the compensating wiring and the transmissive electrode.