Patent ID: 7180139

Claim:
A pixel structure controlled by a scan line and a data line disposed on a substrate, comprising: a thin film transistor disposed on the substrate and electrically connected to the scan line and the data line; a resistance wire disposed on the substrate and electrically connected to the thin film transistor; a first pixel electrode disposed on the substrate and electrically connected to the thin film transistor; a second pixel electrode disposed on the substrate and electrically connected to the thin film transistor through the resistance wire, wherein the thin film transistor comprises: a gate electrode connected to the scan line; a first dielectric layer covering the gate electrode; a first semiconductor layer disposed on the first dielectric layer; a source/drain disposed on the first semiconductor layer, wherein one of the source/drain is electrically coupled to the data line while the other of the source/drain is electrically coupled to the resistance wire and the first pixel electrode; a second dielectric layer disposed on the first dielectric layer and covering the source/drain, wherein the resistance wire comprises: a second semiconductor layer; and a patterned conductor layer electrically coupled to the other of the source/drain and the second pixel electrode, wherein the patterned conductor layer electrically connects to the second semiconductor layer, so that the other of the source/drain and the second pixel electrode are electrically connected.