Patent ID: 8685770

Claim:
A method for manufacturing a thin film transistor array panel, the method comprising: forming a gate line on a substrate; forming a storage electrode line on the substrate in the forming of a gate line; forming a gate insulating layer on the gate line; forming a semiconductor on the gate insulating layer; forming a first data line and a first drain electrode on the semiconductor; forming a lower passivation layer on the first data line and the first drain electrode; forming an upper passivation layer including protrusions and depressions, to define a preliminary contact hole and an opening separate from the preliminary contact hole in the upper passivation layer, wherein each of the preliminary contact hole and the opening exposes the lower passivation layer and overlaps the storage electrode line; forming a metal layer on the upper passivation layer; forming a photosensitive film on the metal layer; etching only the metal layer by using the photosensitive film as an etching mask to form a reflecting electrode, wherein the exposed lower passivation layer remains in the preliminary contact hole by the etching only the metal layer and the remaining exposed lower passivation layer is exposed through the preliminary contact hole by the etching only the metal layer; etching the exposed lower passivation layer remaining in the preliminary contact hole, after the etching only the metal layer, to form a first contact hole exposing the first drain electrode; and forming a connection assistance member connecting the first drain electrode and the reflecting electrode to each other through the first contact hole after removing the photosensitive film, wherein the reflecting electrode contacts the exposed lower passivation layer through the opening.