Patent ID: 8503595

Claim:
A data judgment/phase comparison circuit to which a data and a single clock signal are inputted and which can perform data judgment and phase comparison, the data judgment/phase comparison circuit comprising: a first data judging circuit which performs data judgment for the inputted data in synchronization with the clock signal; a second data judging circuit which performs data judgment for the inputted data in synchronization with the clock signal using a same clock phase as the first data judging circuit; and a phase comparison logic circuit to which an output of the first data judging circuit and an output of the second data judging circuit are inputted, and which outputs a phase comparison output Early indicating that a clock phase is too early or a phase comparison output Late indicating that the clock phase is too late, a data input determination period required for correctly judging a data by the second data judging circuit being longer than the data input determination period required for correctly judging a data by the first data judging circuit, said data input determination period being a sum of the required setup time and required hold time, an output result of the first data judging circuit or a result obtained by delaying the output result being outputted as a data judgment result of the entire data judgment/phase comparison circuit, and the phase comparison logic circuit having a possibility of outputting the phase comparison output Early or Late only when the output of the first data judging circuit and an output of the second data judging circuit are different from each other.