Patent ID: 6990005

Claim:
A semiconductor device comprising: a plurality of ferroelectric capacitors for memory in which each one end thereof is connected to each of a plurality of first bit lines via switching transistor; first plate lines connected to the other ends of said ferroelectric capacitors for memory; first ferroelectric capacitors for reference in which each one end thereof is connected to a second bit line via first n-channel MOS transistor; a second plate line connected to the other ends of said first ferroelectric capacitors for reference; and a p-channel MOS transistor connected to said second plate line, wherein said p-channel MOS transistor is formed in a plate driver circuit to which said first plate lines and said second plate line are connected; wherein said plate driver circuit has a structure that the circuit applies voltage lower than that of said second bit line to said second plate line via said p-channel MOS transistor in an ON state of said p-channel MOS transistor.