Patent ID: 8617949

Claim:
A method for forming a system-on-chip (SOC) device comprising: forming in a common process a first bottom electrode for a first capacitor in a first region, a second bottom electrode for a second capacitor in a second region, and a third bottom electrode for a third capacitor in a third region, wherein the first bottom electrode, the second bottom electrode, and the third bottom electrode are substantially at a same level; forming a first capacitor insulator with a first thickness adjoining the first bottom electrode, a second capacitor insulator with a second thickness adjoining the second bottom electrode, and a third capacitor insulator with a third thickness adjoining the third bottom electrode; and forming in a common process a first top electrode for the first capacitor on the first capacitor insulator, a second top electrode for the second capacitor on the second capacitor insulator, and a third top electrode for the third capacitor on the third capacitor insulator, wherein the first top electrode, the second top electrode, and the third top electrode are substantially at a same level.