Patent ID: 7039793

Claim:
An apparatus within a pipeline microprocessor for expediting the execution of a repeat string operation, the apparatus comprising: an architectural count register, configured to store a number of iterations for the repeat string operation; translation logic, configured to generate a micro instruction having an initialization field, wherein said initialization field indicates said micro instruction is a first micro instruction of a sequence of micro instructions configured to direct the pipeline microprocessor to execute the repeat string operation, and wherein said initialization field indicates a first iteration of the repeat string operation; and execution logic, configured to receive and execute said micro instruction, wherein said execution logic comprises: a shadow count register, coupled said architectural count register, configured to store said number of iterations as provided within said architectural count register; and count update logic, coupled to said shadow count register, configured to detect said initialization field and configured to transfer contents of said shadow count register to a temporary internal count register for use in executing the repeat string operation, whereby generation and execution of a load counter initialization instruction, configured to load said temporary internal count register with said number of iterations, is precluded.