Patent ID: 7797683

Claim:
A method of supporting a plurality of logical threads with a plurality of simultaneous physical threads, comprising: mapping macro-instructions associated with a first logical thread to a next instruction pointer of a simultaneous physical thread; monitoring a processor for a triggering event at a first time; holding the first logical thread in an active state until the triggering event is present; halting the mapping and switching the first logical thread to a drain state if the triggering event is present; monitoring the first logical thread for an interruptible point, wherein the interruptible point corresponds to either an end of a macro-instruction in the first logical thread, or a retirement of a final micro-operation associated with a first logical thread; holding the first logical thread in the drain state until the interruptible point is encountered; switching the first logical thread to a stall state if the interruptible point is encountered; monitoring the processor for the triggering event at a second time; holding the first logical thread in the stall state until the triggering event is not present; switching the first logical thread to a wait state if the triggering event is not present; monitoring the plurality of simultaneous physical threads for an available physical thread; holding the first logical thread in the wait state until the available physical thread is encountered; and switching the first logical thread to the active state if the available physical thread is encountered.