Patent ID: 7991962

Claim:
A system, comprising: processing logic; and a memory management module configured to: allocate a plurality of thread stack units in a portion of memory space, wherein when the plurality of thread stack units have a particular alignment requirement the memory management module adds a first alignment space to a top of a first thread stack unit of the plurality of thread stack units and adds a second alignment space to a bottom of a last thread stack unit of the plurality of thread stack units; partition a particular thread stack unit of the plurality of thread stack units to include a stack and a thread-local storage region, the thread-local storage region located adjacent to an alternate stack that is located at a bottom of the particular thread stack unit, wherein the alternate stack is used when an error condition occurs, and wherein the error condition comprises at least one of a stack corruption error and a guard page error; and associate the stack with a thread that is executable by the processing logic, the thread-local storage region adapted to store data associated with the thread, wherein the portion of memory space allocated for the particular thread stack unit is based on a size of the thread-local storage region that is determined when the thread is generated and based on a size of the stack.