Patent ID: 7872602

Claim:
A time to digital converting (TDC) circuit, comprising: a first delay circuit, comprising at least a first delay stage, for generating a first output signal by delaying a first input signal; a second delay circuit, comprising at least a second delay stage, for generating a second output signal by delaying a second input signal; a first counter, coupled to the first delay circuit, for generating a first counter value by counting the first output signal; a second counter, coupled to the second delay circuit, for generating a second counter value by counting the second output signal; and a comparator, coupled to the first counter and the second counter, for generating a comparing result signal by comparing the first counter value with the second counter value; wherein the first delay stage has a larger delay amount than the second delay stage, the first counter starts counting earlier than the second counter, and the comparator outputs the comparing result signal when the second counter value falls within a predetermined range of values including the first counter value; wherein the first delay circuit comprises a plurality of first delay stages, and the first output signal corresponds to a portion of the first delay stages.