Patent ID: 7721244

Claim:
A large-scale integrated circuit designing system for carrying out layout design by inputting information about configurations of circuits internally formed in each large-scale integrated circuit comprising metal insulator semiconductor transistors, comprising: a gate size correcting unit to detect a wiring segment expected to cause a damage to a gate insulating film of each of said metal insulator semiconductor transistors due to an antenna effect that said wiring segment absorbs electric charges generated during plasma etching processes and to correct, based on a result from specified simulation or from specified experiment, an area of a gate electrode of each of said metal insulator semiconductor transistors connected to the detected wiring segment so as to become a value that enables the prevention of said damage, said gate size correcting unit comprising: a sizing candidate table creating unit to store correction candidate values to be used for correction of an area of said gate electrode in ascending order for every type of a cell corresponding to said circuit configurations to create a sizing candidate cell table; an antenna error net detecting unit to detect a net having said wiring segment expected to cause said damage; a gate pin/cell recognizing unit to recognize a gate pin connected to said net and a type of a cell corresponding to said gate pin; and a cell sizing unit to judge whether or not said damage is able to be prevented by using said correction candidate values in ascending order stored in said sizing candidate cell table based on a specified judgment standard and to correct an area of said gate electrode by using a minimum value that enables the prevention of said damage.