Patent ID: 8792267

Claim:
A memory circuit, comprising: a static random access memory (SRAM) including N banks of memory cells, each bank having M columns of the SRAM, where M and N are positive integers; rows of M sense amplifiers, each row of the M sense amplifiers placed between two banks of the memory cells and having a sense amplifier control circuit and a local input/output circuit wherein each sense amplifier control circuit includes a dummy sense amplifier that imitates the behavior of the M sense amplifiers; a controlled feedback latch storing a previous state of input data in a read cycle; a pull down select block coupled to the controlled feedback latch and the dummy sense amplifier, wherein the pull down select block pulls dummy global read lines of the dummy sense amplifier to LOW, outputs read data depending on the state of outputs of the controlled feedback latch; a dummy output latch coupled to the pull-down select block to store the read data; and a SRAM reset generation circuit coupled to the sense amplifier control circuits and the controlled feedback latch, the SRAM reset generation circuit selecting the input data that is HIGH for the controlled feedback latch and generating a sense amplifier reset signal to reset the sense amplifier control circuits, wherein the dummy output latch is a latch that is the same as a sense amplifier latch used in the local input/output circuit, thereby, no margin is involved between a reset of the sense amplifiers and the read data latched at the dummy output latch in the read cycle.