Patent ID: 7580282

Claim:
A floating-gate non-volatile memory, comprising: a plurality of banks; and a negative bias power line providing a negative bias voltage for said plurality of banks, wherein each of said plurality of banks comprises: a plurality of columns each connected to a plurality of sectors, wherein each sector comprises a plurality of floating-gate memory cells, a plurality of negative biasing column decoders each associated with one column of said plurality of columns, and a bank decoder connected to said plurality of column decoders through an in-bank power line, wherein the bank decoder within a selected one of said banks provides said negative bias voltage received from said negative bias power line for said in-bank power line, and wherein each of said column decoders is responsive to selection of an associated one of said columns for generating a negative voltage signal from said negative bias voltage received from said in-bank power line, and providing said negative voltage signal for said associated one of said columns, wherein said sectors are arranged in a plurality of rows, wherein said each of said plurality of banks further includes a plurality of row decoders associated with said rows of said sectors, wherein one of said row decoders associated with a selected one of said rows of said sectors provides said negative bias voltage received from said negative bias power line for said selected one of said rows of said sectors, and wherein each of said plurality of banks further comprises a plurality of row direction in-bank power lines associated with said rows of said sectors, said plurality of row direction in-bank power lines providing said negative bias voltage received from said row decoders for said associated rows of said sectors, wherein each of said sectors comprises: a decoder which selects said floating gate memory cells, a negative bias feed line connected to said decoder, and a negative bias switch connected between said row direction in-bank power line and said negative bias feed line, wherein said negative bias switch includes: a first N-channel MISFET comprising a gate which receives said negative voltage signal from an associated one of said column decoders, a source connected to an associated one of said row direction in-bank power lines, and a drain connected to said negative bias feed line, a second MISFET comprising a gate which receives a control signal from an associated one of said row decoders, a source connected to said negative bias feed line, and a drain connected to a power supply, a third MISFET comprising a gate which receives a control signal from an associated one of said column decoders, a source connected to said negative bias feed line, and a drain connected to said power supply.