Patent ID: 7054970

Claim:
A bus arbiter for an integrated circuit system including a plurality of bus masters, comprising: a program file comprising a plurality of program registers, wherein each program register is associated with one of the bus masters and stores a predetermined value of a bus occupation rate assigned to the bus master; a temporary file comprising a plurality of temporary registers, wherein each temporary register is associated with one of the bus masters and stores a current value of the bus occupation rate of the bus master; and a point register that designates the bus master having the highest priority among the bus masters at a given time, wherein the bus arbiter grants bus ownership to a current-requesting bus master, wherein the bus arbiter decreases a current value of the bus occupation rate associated with the designated bus master, if the designated bus master is the current-requesting bus master, and wherein the bus arbiter decreases a current value of the bus occupation rate associated with the designated bus master and the current-requesting bus master, if the current-requesting bus master is not the designated bus master.