Patent ID: 7843760

Claim:
Interface circuitry for coupling between a memory device and processing circuitry, the processing circuitry being arranged to issue a plurality of access signals relating to accesses to be performed in the memory device, the interface circuitry comprising: write address latch circuitry for storing a write address signal; write address decoder circuitry responsive to a set first enable signal to decode the write address signal provided from the write address latch circuitry; read address latch circuitry for storing a read address signal issued by the processing circuitry; read address decoder circuitry responsive to a set second enable signal for decoding the read address signal provided from the read address latch circuitry; and decoder select latch circuitry, responsive to an access type indication signal from the processing circuitry, to generate the first and second enable signals in dependence on said access type indication signal, in the event of metastability occurring in the decoder select latch circuitry, the decoder select latch circuitry being arranged to not set at least the second enable signal, thereby disabling at least the read address decoder circuitry in the presence of said metastability.