Patent ID: 8051325

Claim:
A multiprocessor system comprising a plurality of nodes, wherein each of said plurality of nodes comprises a plurality of processors, a plurality of memories respectively connected to said plurality of processors, and first and second node controllers provided for a redundant configuration and connected with said plurality of processors, wherein unique identifiers are assigned to said plurality of processors, said first node controller and said second node controller in each node, and wherein each of said first node controller and said second node controller comprises: a first request control section configured to determine the identifier of a transmission destination of a request based on a memory address of an access destination of said request; a second request control section configured to determine the identifier of the transmission destination of said request based on the memory address of the access destination of said request; a first register configured to hold the identifier of the transmission destination of said request such that said request is outputted to said first request control section; a second register configured to hold the identifier of the transmission destination of said request such that said request is outputted to said second request control section; a first routing table configured to specify one of said first request control section and said second request control section as an output destination of said request based on the identifier held by said first register, the identifier held by said second register, the identifier of the transmission destination of said request, when receiving said request; and a second routing table configured to specify a signal line for the identifier of the transmission destination of said request based on the identifier of the transmission destination which is determined by said first request control section or said second request control section, to transmit said request.