Patent ID: 7087473

Claim:
A method of fabricating a semiconductor integrated circuit in which a normal complementary MOS transistor and a heterojunction complementary MOS transistor are formed on a same substrate, the normal complementary MOS transistor comprising ordinary MOS transistors each having a basic structure including a metal, an oxide and a semiconductor, the semiconductor consisting of a single semiconductor, the heterojunction complementary MOS transistor comprising heterojunction MOS transistors each having said basic structure, the semiconductor of said basic structure consisting of different semiconductors from each other forming a heterojunction, the method comprising: a step A of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation and then forming a pair of p-well and n-well in each of the pair of first device forming regions and the pair of second device forming regions; a step B of oxidizing an entire surface of the semiconductor substrate to form a first oxide film covering the entire surface after the step A; a step C of removing a portion of the first oxide film which overlies the pair of second device forming regions to expose the pair of second device forming regions; a step D of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step E of oxidizing the entire surface of the semiconductor substrate to form a second oxide film covering the surface of the substrate including a surface of the pair of heterojunction structures after the step D; and a step F of forming a pair of gate electrodes above each of the pair of first device regions and the pair of second device regions after the step E, whereby the normal complementary MOS transistor and the heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.