Patent ID: 7545006

Claim:
A semiconductor device comprising: a semiconductor substrate; a gate stack overlying the semiconductor substrate; a lightly doped source/drain (LDD) region adjacent the gate stack; a deep source/drain region adjoining the LDD region; a graded silicide region on the deep source/drain region and the LDD region, wherein the graded silicide region comprises a first portion having a first thickness, a second portion adjoining the first portion and having a second thickness substantially less than the first thickness, and wherein the second portion is closer to a channel region than the first portion; a spacer on a sidewall of the gate stack, wherein the spacer is a slim spacer having a thickness of less than about 200 Å, wherein the spacer is free from portions directly over the second portion of the graded silicide region, and wherein an inner edge of the second portion adjoins an outer edge of the spacer; and a contact etch stop layer (CESL) over the gate stack, the spacer, and the graded silicide region, wherein the CESL is in physical contact with the outer edge of the spacer.