Patent ID: 7509608

Claim:
A method for obtaining an estimate of jitter of an integrated circuit design prior to implementation thereof, the method comprising: obtaining a description of logic blocks of the integrated circuit design; obtaining a description of input/output blocks of the integrated circuit design; first determining of a first type of a first jitter induced by anticipated operation of a logic block onto one or more first clock signals external to the logic block; second determining of a first type of a second jitter induced by anticipated operation of an input/output block on one or more second clock signals external to the input/output block; the first jitter being core logic jitter; the second jitter being output jitter; repeating the first determining for a second type of the first jitter; repeating the second determining for a second type of the second jitter; and estimating the core logic jitter and the output jitter from at least the first type and the second type of each of the first jitter and the second jitter, the core logic jitter being caused by noise generated by internal switching of the logic block, and the output jitter being caused by noise generated by internal switching of the input/output block.