Patent ID: 8716101

Claim:
A method of reducing electromigration cracking and extrusion effects in semiconductor devices, the method comprising: forming a first metal line in a first dielectric layer; forming a cap layer over the first metal line and the first dielectric layer; forming a second dielectric layer over the cap layer; and forming a void in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer, and wherein the void is localized around an anode end of the first metal line so as to prevent extrusions from the anode end from shorting to an adjacent second metal line formed in the first dielectric layer.