Patent ID: 8582338

Claim:
A ternary content addressable memory (CAM) cell for comparing a comparand bit with a data value having one of three possible states represented by a data bit and a mask bit, the CAM cell comprising: a data cell to store the data bit; a mask cell to store the mask bit; and a compare circuit coupled to the data cell and the mask cell, and including a discharge path between a match line and ground potential, wherein the discharge path consists essentially of a single transistor, wherein: the single transistor is a first match line pull-down transistor connected between the match line and ground potential, and having a gate responsive to a logical combination of the data bit, the mask bit, and the comparand bit; and the compare circuit further comprises a second match line pull-down transistor connected between the match line and ground potential, and having a gate responsive to a logical combination of a complemented data bit, the mask bit, and a complemented comparand bit.