Patent ID: 8258586

Claim:
A non-volatile anti-fuse memory cell comprising: a programmable n-channel diode-connectable transistor comprising: a poly-silicon gate over a channel region, the poly-silicon gate having a first portion and a second portion wherein the first portion of the gate is electrically connected to a word line of the memory cell; wherein the channel region has a length and is located in a Pwell; an n-type source region formed in the Pwell region, the n-type source region having a first portion and a second portion wherein the first portion of the source region is proximate to a first end of the channel region and the second portion of the source region is electrically connected to a bit line of the memory cell; a field oxide region formed in the Pwell region, the field oxide proximate to a second end of the channel region; an insulator having a substantially constant thickness located between the poly-silicon gate and the channel region; wherein the poly-silicon gate is doped n-type, the first portion of the poly-silicon gate having a higher n-type doping concentration than the second portion of the poly-silicon gate, the second portion of the poly-silicon gate proximate to the first portion of the source; wherein when the non-volatile anti-fuse memory cell is programmed, a rupture occurs between the first portion of the poly-silicon gate and the channel region proximate to the field oxide region.