Patent ID: 8601415

Claim:
A method, comprising: receiving, by a computer system, a description of architecture of a hardware accelerator for accelerating functional verification of a circuit design, the architecture including a plurality of logical processors; receiving, by the computer system, a description of the circuit design having a plurality of gates; representing, by the computer system, each gate of the plurality of gates, each stage of a plurality of stages of the functional verification, and each logical processor of the plurality of logical processors as a separate object based on the received description of the architecture and the received description of the circuit design; representing, by the computer system, relationships between gates of the plurality of gates as pairwise edges; defining, by the computer system, a goal state that requires each gate of the plurality of gates to be scheduled for execution by a logical processor of the plurality of logical processors during a stage of the plurality of stages of the functional verification; constructing, by the computer system and based on the represented objects and the represented pairwise edges, a plurality of partial gate schedules with each partial gate schedule of the plurality of partial gate schedules dictating execution of one or more gates of the plurality of gates by one or more logical processors of the plurality of logical processors during one or more stages of the plurality of stages; constructing, by the computer system and based on the represented objects and the represented pairwise edges, a plurality of partial routing schedules with each partial routing schedule of the plurality of partial routing schedules dictating routing of one or more values of one or more gates of the plurality of gates to one or more other gates that depend on those values; and combining, by the computer system, two or more partial gate schedules of the plurality of partial gate schedules and two or more partial routing schedules of the plurality of partial routing schedules to form a functional verification schedule that meets the goal state, wherein the combined two or more partial routing schedules minimizes routing of one or more values from one or more logical processors of the plurality of logical processors to one or more other logical processors of the plurality of logical processors.