Patent ID: 7613886

Claim:
An apparatus, comprising: a plurality of parallel processors capable of operative communication with a shared memory; a local memory operatively coupled to a first of the processors such that data may be transferred between the shared memory and the local memory for execution of one or more programs therein; a memory interface circuit, including a Direct Memory Access Controller (DMAC) operable to facilitate data transfers into and out of the local memory of the first processor over a first data transfer path; a channel interface circuit operable to facilitate data transfers into and out of the local memory of the first processor from and to others of the processors over a second data transfer path; a synchronization queue having a respective synchronization flag for each initiated data transfer into the local memory; and a storage circuit, wherein the memory interface circuit is operable to: copy a first value of the respective synchronization flag associated with a first data transfer into the storage circuit in response to a first recover synchronization request, the first data transfer being facilitated by the DMAC circuit over the first data transfer path into at least a first location in the local memory of the first processor, change the first value within the storage circuit in response to completion of the first data transfer into the local memory, and produce a first synchronization signal when the first value indicates that the first data transfer into the local memory has been completed, the first synchronization signal indicating that a data transfer from the at least first location in the local memory of the first processor over the second data transfer path using the channel interface circuit would result in valid data being read.