Patent ID: 6914333

Claim:
A wafer level package incorporating dual compliant layers comprising: a wafer having a multiplicity of IC dies formed on an active surface; each of said multiplicity of IC dies further comprises: a plurality of first I/O pads formed on a top surface insulated by a first dielectric layer deposited therein-between; a plurality of metal cap layers with one formed on each of said plurality of first I/O pads providing electrical communication with said pads; said plurality of metal cap layers each having a thickness sufficiently small so as to allow an adjacent tapered shoulder of a first compliant layer to be later formed; a first compliant layer of a first elastic material having tapered shoulder formed on top of said first dielectric layer; a second compliant layer of a second elastic material on top of said first compliant layer; a plurality of metal traces formed on top of said first and second compliant layers each in electrical communication with one of said plurality of metal cap layer at a first end and extends toward a center of said IC die at a second end; a second dielectric layer formed on top of said plurality of metal traces insulating the latter from each other while exposing a plurality of second I/O pads with one on each of said second end of said plurality of metal traces; and a plurality of solder balls formed on said plurality of second I/O pads.