Patent ID: 7440352

Claim:
A semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines arranged in a matrix, wherein the word lines are divided into a plurality of word line sets, wherein each word line set comprises at least one word line, wherein the word line sets are divided into a first group of word line sets and a second group of word line sets, and wherein the first and second groups of word line sets each comprise more than one of the word line sets; and, a refresh control unit comprising: a first word line enable signal generation unit corresponding to a first word line set of the plurality of word line sets, wherein the first word line enable signal generation unit comprises a latch unit storing either a first or a second data value, and prevents the first word line set from being refreshed only when the latch unit stores the first data value; and, a reset signal generation unit receiving a mode register set (MRS) signal, a word line set address signal, and a power-up signal, wherein, when the received word line address signal corresponds to the first word line set, the reset signal generation unit selectively provides an activated reset signal to the latch unit in accordance with the received MRS signal, the received word line address signal, and the received power-up signal, wherein the latch unit either begins or continues to store the first data value in response to receiving the activated reset signal, and wherein, when the MRS signal indicates an MRS mode, the refresh control unit allows selected word line sets in the first group of word line sets to be refreshed, while preventing every word line set in the second group of word line sets from being refreshed.