Patent ID: 8363441

Claim:
A power conversion apparatus comprising: a plurality of switches including (2m−2) switches constituting a multilevel power converter with m conversion levels; an individual gate drive unit that includes (i) a plurality of gate drivers connected to the plurality of switches and (ii) a plurality of interface circuits, the individual gate drive unit requiring no dedicated power supply; and a signal source for transmitting a signal to the individual gate drive unit so that the signal is transmitted in isolation to each of the plurality of gate drivers from the signal source, wherein power is supplied to the individual gate drive unit from a single common power supply, wherein the plurality of interface circuits include (2m−2) interface circuits connected to the (2m−2) switches, respectively, wherein the first to (2m−3)th interface circuits include power supply terminals 1 - a to (2m−3)-a and 1 - b to (2m−3)-b, respectively, wherein the (2m−2)th interface circuit includes a power supply terminal (2m−2)-a, wherein the single common power supply includes a high voltage side terminal 1 - a ′ and a ground side terminal 1 - b ′, wherein the power supply terminal 1 - b of the first interface circuit is connected to the ground side terminal 1 - b ′ of the single common power supply, wherein the power supply terminal 1 - a of the first interface circuit and the power supply terminal 2 - b of the second interface circuit are connected to the high voltage side terminal 1 - a ′ of the single common power supply, wherein the power supply terminals 2 - a to (2m−4)-a of the second to (2m−4)th interface circuits are connected to the power supply terminals 3 - b to (2m−3)-b of the third to (2m−3)th interface circuits, respectively, wherein the power supply terminal (2m−3)-a of the (2m−3)th interface circuit is connected to the power supply terminal (2m−2)-a of the (2m−2)th interface circuit, and wherein the individual gate drive unit supplies power from the single common power supply to each of the plurality of gate drivers through the plurality of interface circuits.