Patent ID: 7830186

Claim:
A delay locked loop (DLL) apparatus, comprising: a delay means generating respective rising and falling clocks by delaying a reference clock, synchronizing a rising clock replica-delayed with the reference clock, and synchronizing the falling clock with the rising clock synchronized by the reference clock; only one replica delay unit delaying the rising clock to provide the replica-delayed rising clock; a control means controlling the synchronization of the rising clock by comparing the phases of the reference clock and the replica-delayed rising clock, and controlling the synchronization of the falling clock by comparing the phases of the rising clock synchronized by the reference clock and the falling clock, wherein the control means comprises: a first phase detector detecting the phase difference between the reference clock and the replica-delayed rising clock to provide a first detecting signal to an update mode generator; a second phase detector detecting the phase difference between the rising and falling clocks to provide a second detecting signal to the update mode generator; an update enhancer phase detector detecting the phase difference between the reference clock and the replica-delayed rising clock to provide an enhanced detection signal to the update mode generator; the update mode generator providing an update mode signal as the first detection signal, the second detection signal and the enhanced detection signal; and a DCC output unit outputting an output pulse by transmitting the rising clock of the delay means to the replica delay unit and adjusting the pulse width of the rising and falling clocks synchronized with each other in the delay means.