Patent ID: 8922267

Claim:
An electronic device comprising: a first stage (ST 1 ) having an input capacitance (C 1 ); a switch (SW 1 ); a buffer stage (BUF) coupled between the first stage and a second stage (ST 2 ) having an input sensitive to charge injection or voltage glitches, an input of the buffer and the input of the second stage being coupled together at a first node (N 1 ) which is configured to be coupled to a voltage source for supplying a reference voltage (VREF) to the input of the first stage, wherein, in a first configuration of the switch, the switch (SW 1 ) is arranged to connect the input (ST 1 IN) of the first stage to the first node (N 1 ) and to disconnect the input (ST 1 IN) of the first stage from an output (BUFOUT) of the buffer or, in a second configuration of the switch, to connect the input (ST 1 IN) of the first stage to the output (BUFOUT) of the buffer and to disconnect the input (ST 1 IN) of the first stage from the first node (N 1 ), wherein an area of input transistors of the buffer stage is determined by: ABUFOPT = ( C ⁢ ⁢ 1 ⁢ ⁢ σ ⁢ ⁢ VT ∫ 0 VGS ⁢ COX ⁡ ( V ) ⁢ ⅆ V ) 2 / 3 ( 6 ) Where ABUFOPT is the area of the input transistors, COX is the oxide capacitance, VGS is the gate to source voltage, σVT is the standard deviation of an assumed Gaussian distribution of the error due to production spread, and C 1 is the input capacitance of the first stage ST 1 , wherein charge injection or voltage glitches into the second stage are minimized.