Patent ID: 8836025

Claim:
A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other; a third semiconductor layer provided on part of the second semiconductor layer, having the second conductivity type, and having a higher effective impurity concentration than that of the second semiconductor layer; a fourth semiconductor layer of the first conductivity type provided on part of the third semiconductor layer; a fifth semiconductor layer provided on another part of the second semiconductor layer, separated from the third semiconductor layer, and having the first conductivity type; a sixth semiconductor layer provided on part of the fifth semiconductor layer, separated from the second semiconductor layer, having the first conductivity type, and having a higher effective impurity concentration than that of the fifth semiconductor layer; a first insulating film provided on part of the fifth semiconductor layer between the fourth semiconductor layer and the sixth semiconductor layer; a second insulating film provided from above an end portion of the third semiconductor layer on an outer peripheral side of the second semiconductor layer to above a portion of the first semiconductor layer outside the second semiconductor layer; a gate insulating film provided on part of the second semiconductor layer and the third semiconductor layer between the fourth semiconductor layer and the fifth semiconductor layer; and a gate electrode provided on the gate insulating film, a first distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer in the first region being longer than the first distance in the second region, and a second distance between an edge of the second insulating film on an inner peripheral side of the second semiconductor layer and an edge of the third semiconductor layer on an outer peripheral side of the second semiconductor layer in the first region being shorter than the second distance in the second region.