Patent ID: 7237090

Claim:
An interface for transferring data between a central processing unit (CPU) and a plurality of coprocessors, the interface comprising: an instruction bus, configured to transfer instructions to the plurality of coprocessors in an instruction transfer order, wherein particular instructions designate and direct one of the plurality of coprocessors to transfer the data to/from the CPU; and a data bus, coupled to said instruction bus, configured to transfer the data, wherein data order signals within said data bus specify a data transfer order that differs from said instruction transfer order, and wherein said data order signals specify transfer of a data element, said data element corresponding to a specific outstanding instruction, wherein said data order is relative to outstanding instructions, said outstanding instructions being those of said particular instructions transferred to said one of the plurality of coprocessors that have not completed a data transfer; wherein the interface keeps track of said data order, and wherein said data order signals indicate said data order, and wherein said data order signals are provided with said data element as said data element is transferred.