Patent ID: 7184342

Claim:
A semiconductor memory device incorporating a plurality of memory cells therein, comprising: a bit line sense amplifier (BLSA) array provided with a plurality of bit line sense amplifiers for sensing and amplifying data of the memory cells; and a BLSA driving control means for overdriving a bit line connected to the bit line sense amplifier in response to an active command, and for overdriving the bit line in response to a precharge command, wherein the BLSA driving control means includes: an internal signal generator for generating a first enable signal with an activation period corresponding to a row active time and a second enable signal with an activation period which is shorter than the row active time, in response to the active command and the precharge command; a BLSA power line driver for driving BLSA power lines with a normal voltage or overdriving the BLSA power lines; and a driving control signal generator for generating a driving control signal for controlling the BLSA power line driver in response to the first and the second enable signals.