Patent ID: 8564602

Claim:
A method of manufacturing a multiple memory controller computer comprising: providing a first memory controller and a second memory controller for controlling a main memory, wherein each memory controller comprises a configuration register that defines a range of addresses for accelerated graphic transactions, the first memory controller being connected to the second memory controller and a central processing unit via a bus, wherein the bus is separate from a chipset of each of the memory controllers, and each memory controller is independent of the central processing unit; connecting the first memory controller to an accelerated graphics processor via a point-to-point connection that bypasses the bus; providing an address remapping table of entries in the main memory, wherein the address remapping table is located in the range of addresses for the accelerated graphic transactions; and when a memory transaction is associated with graphics data, translating a virtual address of the memory transaction to a physical address based on the address remapping table and routing the memory transaction from the main memory to the accelerated graphics processor via the point-to-point connection based on the physical address, wherein the second memory controller handles requests that are not meant for the accelerated graphics processor, and wherein the first memory controller is configured to reroute requests that are not meant for the accelerated graphics processor to the second memory controller via the bus.