Patent ID: 8843540

Claim:
A circuit for implementing Fast Fourier Transform/Inverse Fast Fourier Transform (FFT/IFFT), comprising: a first multiplexer, a second multiplexer, a first Random Access Memory (RAM), a second RAM, a Read Only Memory (ROM), a third multiplexer, a fourth multiplexer, a complex multiplier, a first complex adder and a second complex adder; the circuit further comprising two data output ends and two data input ends, wherein the two data output ends are output ends of the third and fourth multiplexers respectively or output ends of the first and second RAMs respectively; two input ends of the first multiplexer are connected with one of the data input ends of the circuit and an output end of the first complex adder respectively; two input ends of the second multiplexer are connected with the other data input end of the circuit and an output end of the second complex adder respectively; an output end of the first multiplexer is connected with a data input end of the first RAM; an output end of the second multiplexer is connected with a data input end of the second RAM; input signals of two input ends of the third multiplexer are the output signal of the output end of the first RAM and 0.5 times the output signal of the output end of the first RAM respectively; input signals of two input ends of the fourth multiplexer are the output signal of the output end of the second RAM and 0.5 times of the output signal of the output end of the second RAM respectively; two input ends of the complex multiplier are connected with the output end of the third multiplexer and an output end of ROM respectively; input signals of the two input ends of the first complex adder are the output signal of the output end of the fourth multiplexer and −1 times the output signal of an output end of the complex multiplier respectively; two input ends of the second complex adder are connected with the output end of the fourth multiplexer and the output end of the complex multiplier respectively.