Patent ID: 8356219

Claim:
Integrated circuitry comprising: A. a test data input lead, a test clock lead, a test mode select lead, and a test data out lead; B. a boundary scan register having a test data input coupled to the test data input lead and a test data output coupled to the test data output lead; C. a first test access port having a test data input coupled to the test data input lead, a test clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, and a test data output coupled to the test data out lead, the first test access port being connected to the boundary scan register, and the first test access port having a first select output lead, a second select output lead, and a first enable input lead; D. first megamodule circuitry; E. a second test access port having a test data input coupled to the test data input lead, a test clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, and a test data output coupled to the test data out lead, the second test access port being connected to the first megamodule circuitry and having a third select output lead and a second enable input lead; and F. a test linking module having shift register circuitry, the shift register circuitry having an input coupled to the test data input lead, an output coupled to the test data output lead, control inputs, and first and second enable outputs, the second enable output being coupled to the second enable input lead, the test linking module having state machine circuitry, the state machine circuitry having inputs connected to the test clock lead and the test mode select lead, having inputs coupled to the second and third select output leads, and having outputs connected to the control inputs of the shift register circuitry; and G. gating circuitry having a first input coupled to the first enable output of the shift register circuitry, a second input connected to an external enable input lead, and an output coupled to the first enable input lead.