Patent ID: 7282947

Claim:
A processor-based system, comprising: a processor having a processor bus; a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port; at least one input device coupled to the peripheral device port of the system controller; at least one output device coupled to the peripheral device port of the system controller; at least one data storage device coupled to the peripheral device port of the system controller; and a memory module coupled to the system memory port of the system controller, the memory module comprising: a plurality of memory devices; an active memory component having a plurality of terminals, the active memory component being coupled to the system memory port of the system controller; and a respective conductor tree coupling each of the terminals of the active memory component to a terminal of each of the plurality of memory devices, each of the conductor trees comprising at least one branch, each branch including a pair of transmission lines each of which is connected at only its ends to either one of the memory devices, the respective terminal of the active memory component, or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy have the same length.