Patent ID: 8161312

Claim:
Apparatus for processing data comprising: one or more clock adjustment circuits to adjust one or more clock signals; one or more voltage level adjustment circuits to adjust one or more voltage levels; a plurality of data processing blocks to process data responsive to the one or more clock signals and the one or more voltage levels; and one or more performance feedback signals operate according to one or more performance measurements of the plurality of data processing blocks in real time; wherein the one or more clock adjustment circuits to adjust the one or more clock signals, and the one or more voltage level adjustment circuits to adjust the one or more voltage levels, responsive to the one or more performance feedback signals in real time, and wherein a dominant data processing block is determined according to a system performance algorithm to minimize power consumption, the power consumption is reduced by lowering one or more frequencies of the one or more clock signals and lowering the one or more voltage levels of the plurality of data processing blocks without reducing system performance except for the clock signals and the voltage levels of the dominant data processing block.