Patent ID: 8564034

Claim:
A solid-state imaging device comprising pixels arranged in a two-dimensional array and a drive output circuit that drives the pixels and reads out signals from the pixels, the pixels including a first island-shaped semiconductor formed on a substrate, the drive output circuit including at least one second island-shaped semiconductor formed on the substrate so as to be at the same height as the first island-shaped semiconductor, the first island-shaped semiconductor including a first semiconductor region formed in a bottom portion of the first island-shaped semiconductor, a second semiconductor region formed on the first semiconductor region and composed of a semiconductor having a conductivity type opposite to that of the first semiconductor region or an intrinsic semiconductor, a first gate insulating layer formed on an outer periphery of and on a lower portion of the second semiconductor region, a first gate conductor layer formed so as to surround the first gate insulating layer, a third semiconductor region formed in an outer peripheral portion of the second semiconductor region adjacent to the first gate conductor layer, the third semiconductor region being formed of a semiconductor having the same conductivity type as the first semiconductor region, and a fourth semiconductor region formed on the third semiconductor region and the second semiconductor region and composed of a semiconductor having a conductivity type opposite to that of the first semiconductor region, the second island-shaped semiconductor including a fifth semiconductor region formed in a lower portion of the second island-shaped semiconductor, a sixth semiconductor region formed on the fifth semiconductor region and composed of a semiconductor having a conductivity type opposite to that of the fifth semiconductor region or an intrinsic semiconductor, a second gate conductor layer formed so as to surround a second gate insulating layer formed on an outer periphery of the sixth semiconductor region, and a seventh semiconductor region formed on the sixth semiconductor region so as to be adjacent to the second gate conductor layer and be positioned above the second semiconductor region, wherein the first gate conductor layer and the second gate conductor layer have bottom portions located on the same plane.