Patent ID: 8217673

Claim:
A test circuit for testing an integrated circuit including a plurality of output stages, the test circuit comprising: a test controller that switches operation of the plurality of output stages between a normal operation mode and a test mode; a plurality of switch elements respectively connected to the plurality of output stages; and a level shifter that generates a switch signal for controlling activation and deactivation of the plurality of switch elements in accordance with the normal operation mode and the test mode wherein: the plurality of output stages includes first and second output stages; the plurality of switch elements include first and second switch elements, each formed by a P-channel MOS transistor having a source, drain, and gate, with the gates of the first and second switch elements being connected to each other and having a common gate node, the sources of the first and second switch elements being connected to each other and having a common source node, the drain of the first switch element being connected to the first output stage, and the drain of the second switch element being connected to the second output stage; and the level shifter receives voltage from the common source node to generate the switch signal at the common gate node.