Patent ID: 7920018

Claim:
A booster circuit comprising: a first boosting cell row including N stages (N≧1) of boosting cells; a second boosting cell row including M stages (M≧1) of boosting cells; and at least one analog comparison circuit for outputting a well bias potential generated by an input potential of the boosting cell on the i-th stage (1≦i≦N) of the first boosting cell row and an input potential of the boosting cell on the i-th stage (1≦i≦M) of the second boosting cell row, wherein: each boosting cell includes a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one switching element in either or both of the first well region and the second well region, the at least one switching element is configured to transfer charges from a first terminal to a second terminal, and the well bias potential of the at least one analog comparison circuit is applied to the first well region of the switching element included in the at least one boosting cell of the first and second boosting cell rows.