Patent ID: 8635620

Claim:
A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, the device comprising: a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units; a task interconnection logic means interconnecting the task units for communicating actions from a source task unit to a destination task unit; and each of the task units including: a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action; a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units; and a plurality of control/data registers each corresponding, for a task associated with a task unit of the plurality of task units, to an instance of the algorithm, each one of the control/data registers comprising a control field composed of a completion bit set to 1 when the task associated with the task unit is completed, a validation bit set to 1 when the task associated with the task unit is validated and a L/R bit indicating that an output in an algorithm flow is left or right when the task associated with the task unit includes a decision.