Patent ID: 7161516

Claim:
An N-bit digital to analog converter (DAC) with a binary-weighted capacitor ladder in an integrated circuit, the N-bit DAC comprising: N- 1 sampling switches each having a control gate, a first pole, and a second pole coupled to a voltage reference; a switch controller to receive an N-bit digital data input signal and generate N- 1 control signals, the N- 1 control signals respectfully coupled to each control gate of the N- 1 sampling switches to switch the N- 1 sampling switches open and closed in response to the N-bit digital data input signal; N capacitors formed out of a plurality of active unit capacitor cells in a capacitor array, each of the N capacitors having a top capacitor plate coupled together and to an output of the binary-weighted capacitor ladder, one of the N capacitors having a bottom capacitor plate coupled to a ground while the remaining N- 1 capacitors have a bottom capacitor plate respectively coupled to each first pole of the N- 1 sampling switches; and wherein the plurality of active unit capacitor cells to form the N capacitors being arranged with a plurality of dummy unit capacitor cells in the capacitor array to provide visual symmetry and electrical symmetry.