Patent ID: 8264907

Claim:
A method for writing data to a memory array operating in synchronization with a clock signal having a first transition edge, comprising steps of: (a) providing a data strobe signal having a second transition edge corresponding to the first transition edge of the clock signal; (b) providing a first signal and a second signal; (c) latching the data into the first signal in response to the second transition edge of the data strobe signal; and (d) using the first transition edge of the clock signal to relay the data corresponding to the second transition edge of the data strobe signal if the second transition edge of the data strobe signal is coming in earlier than the first transition edge of the clock signal, wherein: the clock signal has a rising edge and a falling edge, and the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal; the first transition edge of the clock signal is one of the rising and the falling edges of the clock signal; and the step (d) comprises a sub-step of latching the data of the first signal into the second signal at a first time point lagged behind the first transition edge of the clock signal by a first time interval until a second time point in response to the first transition edge of the clock signal when the second transition edge of the data strobe signal is coming in earlier than the first transition edge of the clock signal.