Patent ID: 7526700

Claim:
A semiconductor integrated circuit device comprising: a plurality of external input/output signal terminals; a plurality of unit input/output circuits accompanying the respective external input/output signal terminals; one or more memory macros; a self-testing block for performing a self test of the one or more memory macros within a chip; a plurality of circuit blocks for generating various control signals; and means into which a first mode setting control signal output from a specific one of the unit input/output circuits is input as a control signal for controlling other two or more of the unit input/output circuits and which generates a main operation mode setting signal in accordance with OR logic of the first mode setting control signal and a second mode setting control signal output from a different specific one of the unit input/output circuits into which the first mode setting control signal has been input, wherein the unit input/output circuits are individually controlled by the various control signals and the main operation mode setting signal is an internal setting signal for setting whether or not the semiconductor integrated circuit device is in an operation mode in which self-test function is used.