Patent ID: 8198651

Claim:
A semiconductor device comprising: a first doped region disposed in a substrate; a first source/drain region disposed in the first doped region, the first source/drain region comprising a first conductivity type, and the first doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first source/drain region being coupled to a node to be protected; a second source/drain region coupled to a first power supply potential node, the second source/drain region being coupled to the first doped region; a gate electrode coupled to the first power supply potential node via a trigger circuit, wherein the first and the second source/drain regions, the first doped region, and the gate electrode form a transistor; a second doped region disposed adjacent the first doped region, the second doped region comprising the first conductivity type; and a terminal region disposed in the second doped region, the terminal region comprising the second conductivity type and being coupled to a second power supply potential node, wherein the first source/drain region, the first doped region, the second doped region and the terminal region form a thyristor, wherein the transistor provides a first discharge path for an electro static discharge pulse on an input/output pad of a semiconductor chip, wherein the thyristor provides a second discharge path for an electro static discharge pulse on an input/output pad of a semiconductor chip, and wherein the first discharge path is formed before the second discharge path.