Patent ID: 8051237

Claim:
An integrated circuit comprising: a plurality of units on a semiconductor substrate, at least some of the units being for a first purpose and others being for a second purpose; and an interconnect connecting together the units, the interconnect comprising a number of nodes, wherein a configurable one of the nodes is configurable such that requests made from initiator units on one side of the configurable node to target units on the other side of the configurable node are not sent to the target units, the units for the first purpose being on the opposite side of the configurable node from those of the second purpose, wherein the integrated circuit is effectively configurable into two or more separate logical partitions, and wherein the interconnect has a power management system, and wherein the configurable node, under control of the power management system, is configurable such that requests made from the initiator units on the one side of the configurable node to the target units on the other side of the configurable node are handled as if the units on the other side of the configurable node were in a powered down mode by blocking requests made from the initiator units to the target units when the requests are handled as if the units on the other side of the configurable node were in a powered down mode.