Patent ID: 8467231

Claim:
A semiconductor device comprising: a write word line; a read word line; a bit line; a signal line; a memory cell array comprising a first memory cell and a second memory cell; a first driver circuit; and a second driver circuit, wherein the first memory cell and the second memory cell each comprises: a first transistor including a first channel formation region, the first channel formation region including a first semiconductor material; a second transistor including a second channel formation region, the second channel formation region including a second semiconductor material, wherein the first semiconductor material is different from the second semiconductor material; and a capacitor, wherein a gate of the first transistor, a second terminal of the second transistor, and one electrode of the capacitor are electrically connected to one another, wherein a first terminal of the first transistor of the first memory cell and a second terminal of the first transistor of the second memory cell are electrically connected to each other, wherein the first driver circuit is electrically connected to a second terminal of the first transistor of the first memory cell through the bit line and electrically connected to a first terminal of the second transistor of the first memory cell through the signal line, and wherein the second driver circuit is electrically connected to the other electrode of the capacitor of the first memory cell through the read word line and electrically connected to a gate of the second transistor of the first memory cell through the write word line.