Patent ID: 8907737

Claim:
An apparatus comprising: a finite impulse response (FIR) module including: first latch circuitry to output first signals representing a first bit sequence; second latch circuitry to output second signals representing a second bit sequence, wherein a third bit sequence includes the first bit sequence and the second bit sequence; first selection circuitry including first input groups, the first selection circuitry to concurrently receive the first signals and, based on the first signals, to select one of the first input groups and to output a first voltage identifier; second selection circuitry including second input groups, the second selection circuitry to concurrently receive the second signals and, based on the second signals, to select one of the second input groups and to output a second voltage identifier; and configuration circuitry to receive an input signal and, in response, to transition the FIR module between a first operational mode wherein selection of the first input group and selection of the second input group are each enabled, and a second operational mode wherein selection of the first input group and selection of the second input group are each disabled, wherein the configuration circuitry to transition the FIR module between the first operational mode and the second operational mode includes the configuration circuitry to enable a pulse amplitude modulation with the FIR module in the second operational mode.