Patent ID: 8900961

Claim:
A method of selectively forming a transistor structure, said method comprising: forming a first insulator surface on a substrate, said first insulator surface comprising first insulator material; patterning a gate conductor structure on said first insulator surface; implanting source/drain extension implants into regions of said substrate adjacent said gate conductor structure; forming second insulator spacers adjacent said gate conductor structure, said second insulator spacers comprising a second insulator material different from said first insulator material; removing native oxide from said second insulator spacers; after said removing of said native oxide from said second insulator spacers, forming sacrificial spacers on said second insulator spacers, said forming of said sacrificial spacers comprising: heating said transistor structure; and exposing said transistor structure that is heated to a semiconductor-containing gas to selectively form said sacrificial spacers on said second insulator spacers, said sacrificial spacers comprising semiconductor structures comprising a semiconductor that selectively deposits on said second insulator material and not said first insulator material; implanting source and drain implants into said substrate and said gate conductor structure, said sacrificial spacers masking a portion of said substrate adjacent to said gate conductor structure during said implanting; and removing said sacrificial spacers.