Patent ID: 7398387

Claim:
A device for scrambling data by means of address lines, the processor having a CPU core to execute instructions of the processor and to access data through an address bus and a data bus, the device comprising: a seed generator, connected to an address bus, for generating a seed in accordance with a specific address on the address bus; a first parameter generator, connected to the seed generator, for generating a first parameter based on the seed; a data scrambler, connected to a data bus, for scrambling data based on the first parameter when a CPU core is to write the data to the specific address; a de-scrambler, connected to the data bus, for de-scrambling the data based on the first parameter when the CPU core is to read the data from the specific; and a second parameter generator to generate a second parameter, wherein the data scrambler performs scrambling based on the first parameter and the second parameter, and the de-scrambler performs de-scrambling based on the first parameter and the second parameter.