Patent ID: 7256778

Claim:
A circuit for a liquid crystal display device, comprising: a timing controller including at least one input terminal; a filtering circuit, comprising: a transistor including an emitter connected to a first node, a base connected to a second node and a collector connected to a third node, and a digital input voltage (DVCC) being applied to the first node; a first resistor connected between the first and second nodes; a second resistor connected between the second node and a fourth node, the fourth node being grounded; a third resistor connected between the third and fourth nodes; a reset circuit connected to the timing controller, comprising: a fourth resistor connected between the third node and a fifth node, the fifth node being connected to the at least one input terminal; and a capacitor including a first electrode connected to the fifth node and a second electrode grounded; the filtering circuit permitting a gate operation enable (GOE) mask time of a GOE signal applied to a gate driver of the liquid crystal display device to be longer than about 16 msec and reducing an impulse of a clock signal applied to a source driver of the liquid crystal display device.