Patent ID: 7741673

Claim:
A floating body memory, comprising: a semiconductor substrate comprising a cell region and a peripheral circuit region; a floating body cell located in the cell region of the semiconductor substrate; a first floating body located in the peripheral circuit region of the semiconductor substrate; a peripheral gate pattern positioned on the first floating body; first source and drain regions positioned at both sides of the peripheral gate pattern; and first leakage shielding patterns positioned between the first floating body and the first source and drain regions, the first source and drain regions contacting the first floating body, wherein the first leakage shielding patterns contact bottom surfaces of the first source and drain regions, wherein the first floating body is interposed between the first source and drain regions, and extends under the first leakage shielding patterns, wherein the first floating body extends beyond the first source and drain regions and the first leakage shielding patterns, and wherein the floating body memory further comprises a back bias line positioned on the semiconductor substrate, and a back bias plug positioned between the extended first floating body and the back bias line and in contact with the extended first floating body and the back bias line.