Patent ID: 8692327

Claim:
An LDMOS device comprising: a second conduction type buried layer formed inside a first conduction type epitaxial layer; a first conduction type drain extension region formed over at least a portion of said second conduction type buried layer; a second conduction type drain extension region formed in a portion of said first conduction type drain extension region, wherein said second conduction type drain extension region comprises a gate pattern and a drain region; a first conduction type body in surface contact with said second conduction type drain extension region, wherein said first conduction type body comprises a source region; a first guard ring formed around said second conduction type drain extension region, wherein said first guard ring comprises a first conduction type impurity layer and a second conduction type impurity layer, wherein said second conduction type impurity layer is formed on both sides of said first conduction type impurity layer; and a second guard ring formed around the first guard ring, wherein said second guard ring is connected to a different region of the second conduction type buried layer than said first conduction type drain extension region.