Patent ID: 8299564

Claim:
A method for forming a device of an integrated circuit, comprising: obtaining a substrate formed at least in part of silicon; forming shallow-trench isolation structures in the substrate; forming a dielectric gate layer above the substrate; forming a conductive gate layer above the dielectric gate layer; forming a first hard mask layer above the conductive gate layer; depositing a second hard mask layer above the first hard mask layer, wherein: the dielectric gate layer and the conductive gate layer for transistor devices have at least substantially equivalent channel widths and lengths, a first transistor of the transistor devices has a first source side spacing and a first drain side spacing, a second transistor of the transistor devices has a second source side spacing and a second drain side spacing, the first source side spacing is substantially greater than the second source side spacing, and the first drain side spacing is substantially greater than the second drain side spacing; depositing and patterning a masking layer, wherein the masking layer after patterning leaves exposed the first source region, the first drain region, the second source region, and the second drain region; performing at least one etch, wherein the at least one etch includes: etching the second hard mask layer leaving spacers formed of the second hard mask layer associated with the first transistor and the second transistor, wherein the spacers are disposed along sidewalls of the first hard mask layer conforming to sidewalls of a gate of the first transistor and to sidewalls of a gate of the second transistor, wherein the etching forms first recesses and second recesses and the second recesses are deeper than the first recesses; and forming a silicon germanium film in the first recesses and the second recesses, wherein the silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses.