Patent ID: 7015531

Claim:
A memory device, comprising: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; impurity regions formed in the semiconductor substrate adjacent to each side of the gate electrode; an insulating layer formed on the semiconductor substrate, the gate electrode and the impurity regions; a contact hole formed in the insulating layer for exposing one of the impurity region; a bottom electrode, which is connected to one of the impurity regions, formed in the contact hole and on a portion of the insulating layer; an oxygen diffusion barrier layer formed on the bottom electrode, wherein a portion of the oxygen diffusion barrier layer is buried within the contact hole to fill a remaining portion of the contact hole, wherein oxygen diffusion barrier layer is overlapped with the bottom electrode and the bottom electrode is also overlapped with the impurity region; a ferroelectric layer formed on and in direct contact with the oxygen diffusion barrier layer and the bottom electrode; and a top electrode formed on the ferroelectric layer.