Patent ID: 6850305

Claim:
A layout structure for a liquid crystal display that includes a plurality of units, each of the units comprising: a first data line and a second data line, which are arranged substantially in parallel and adjacent one another; a first scan line, a second scan line adjacent the first scan line, and a third scan line adjacent the second scan line, the first, second, and third scan lines being arranged substantially in parallel and arranged in a matrix pattern together with the first data line and the second data line; a first pixel that includes: a first sub-pixel coupled to the first data line and the first scan line, a second sub-pixel adjacent the first sub-pixel and coupled to the second data line and the first scan line, and a third sub-pixel adjacent the second sub-nixel and coupled to the second data line and the second scan line; and a second pixel that includes; a fourth sub-pixel coupled to the first data line and the second scan line, a fifth sub-pixel adjacent the fourth sub-pixel and coupled to the first data line and the third scan line, and a sixth sub-pixel adjacent the fifth sub-pixel and coupled to the second data line and the third scan line, wherein, when the first scan line is enabled, data on the first data line is input to the first sub-pixel and data on the second data line is input to the second sub-pixel, wherein, when the second scan line is enabled, data on the second data line is input to the third sub-pixel and data on the first data line is input to the fourth sub-pixel, and wherein, when the third scan line is enabled, data on the first data line is input to the fifth sub-pixel and data on the second data line is input to the sixth sub-pixel.