Patent ID: 8063708

Claim:
A phase locked loop, comprising: a phase detector configured to detect a phase difference between a reference clock and a feedback clock to generate a detection signal corresponding to the detected phase difference; a control voltage generator configured to generate a control voltage having a voltage level corresponding to the detection signal; a voltage controlled oscillator configured to generate an internal clock having a frequency corresponding to a voltage level of the control voltage; and a start-up driver coupled to said phase detector and said control voltage generator, said start-up driver configured to receive a start-up signal from an external source, and at least one start-up level multiplex signal having said reference clock information, and, in response to the start-up signal, to drive a control voltage terminal to a predefined start-up level corresponding to the start-up level multiplex signal prior to providing an enable signal to said phase detector, wherein the start-up driver comprises: a voltage generating unit configured to divide a source voltage into a plurality of divided voltages; a voltage selecting unit configured to select one of the plurality of divided voltages in response to the at least one start-up level multiplex signal; a voltage comparing unit configured to compare a voltage level of the control voltage terminal with a voltage level of the selected divided voltage to generate a comparison signal; and a driving unit configured to drive the control voltage terminal by pulling up the control voltage terminal in response to the comparison signal and the start-up signal.