Patent ID: 8055818

Claim:
A method comprising: providing low-latency queue pairs for an input/output (I/O) adapter, each queue pair having an associated queue pair message context for controlling a corresponding queue pair, the queue pair message context comprising a plurality of entries in a queue pair table within the I/O adapter, with each queue pair consisting of a consumer process accessible send queue and a consumer process accessible receive queue, wherein a consumer process is executed on a processor that is in communication with a main memory and the I/O adapter, wherein the providing the low-latency queue pairs further comprises: directly placing one or more messages received over a link in the consumer process accessible receive queue held in the main memory, according to a queue pair context, the queue pair context having entries that control the receive queue, wherein the directly placing one or more messages is performed without placing a work request in the consumer process accessible receive queue that describes a physical address of the one or more messages in main memory; transmitting, over the link, a number of messages held in the consumer process accessible send queue, responsive to receiving notification from the consumer process that the number of messages have been placed directly in the send queue by the consumer process, the send queue being held in the main memory; and determining a queue pair dependent single message length for any messages actually present in the send queue, and determining a queue pair dependent single message length for any messages actually present in the receive queue, independent of message content.