Patent ID: 8572465

Claim:
A nonvolatile semiconductor memory system, comprising: a semiconductor memory to store a data frame encoded with LDPC codes and soft-decision values, each corresponding to each of bits included in the data frame; at least one first error correction unit configured to perform a first error correction for the data frame according to a first iterative decoding algorithm; at least one second error correction unit configured to perform a second error correction for the data frame which is failed to correct error by the at least one first error correction unit, the second error correction being performed according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm, wherein the number of the at least one second error correction units is equal to or smaller than that of the at least one first error correction units; at least one third error correction unit configured to perform a third error correction for the data frame which is failed to correct error by the at least one second error correction unit, the third error correction being performed using the soft-decision value according to a third iterative decoding algorithm, the third iterative decoding algorithm using a message having a larger number of quantization bits than that of the second iterative decoding algorithm; and a memory interface configured to read the data frame and the soft-decision values of the data frame failed to correct error by the at least one second error correction unit from the semiconductor memory.