Patent ID: 8762607

Claim:
A method comprising: maintaining a plurality of memory modes via a universal pin matrix residing on a single memory package at a motherboard of a computing system, wherein the plurality of memory modes are associated with a plurality of physical organizations of memory devices, wherein the universal pin matrix is compatible with the plurality of memory modes, wherein each memory mode is independent of or incompatible with other memory modes of the plurality of memory modes; receiving a request to switch from a first memory mode to a second memory mode of the plurality of memory modes, wherein the first memory mode comprises an interleaved mode and the second memory mode comprises a non-interleaved mode; and dynamically switching, via changing of a control bit, from the first memory mode to the second memory mode, in response to the request, wherein dynamic switching includes dynamically routing data from a first output buffer associated with the first memory mode to a second output buffer associated with the second memory mode, wherein the data includes types of data corresponding to types of the plurality of memory modes, wherein the data relates to data signals, channel control signals, memory-mapped input/output (I/O) registers or addresses, sideband control signals, and design test controls.