Patent ID: 7872657

Claim:
A method of addressing a memory to avoid memory aliasing in an addressing scheme for the memory, wherein the memory is constructed of multiple partitions, the method comprising: allocating a first virtual memory page having a first partition stride and a second virtual memory page having a second partition stride to access graphics surfaces stored in the memory, wherein the first partition stride specifies a first portion size of contiguous memory into which each partition of the memory mapped to the first virtual memory page is interleaved across dynamic random access memory (DRAM) banks of the memory and the second partition stride differs from the first partition stride and specifies a second portion size of contiguous memory into which each partition of the memory mapped to the second virtual memory page is interleaved across the DRAM banks of the memory; determining a physical address for a virtual address; determining that the physical address lies within a page crossing region of a partition of the memory, wherein the page crossing region is a DRAM bank that is intersected by a boundary between the first virtual memory page and the second virtual memory page; computing a partition number corresponding to the partition of the page crossing region using a minimum partition stride supported by the memory addressing scheme; and outputting the physical address to a partition controller to access data in the partition, wherein the partition controller is coupled to the partition and identified by the partition number.