Patent ID: 7485913

Claim:
A semiconductor memory device comprising: a memory cell including a first capacitor and a memory cell transistor, the first capacitor being composed of a first lower electrode, a first capacitive insulating film and a first upper electrode, and the memory cell transistor including a first gate electrode and a first doped layer; and a dummy cell including a second capacitor and a dummy cell transistor, the second capacitor being composed of a second lower electrode, a second capacitive insulating film and a second upper electrode, and the dummy cell transistor including a second gate electrode and a second doped layer, wherein the first upper electrode and the second upper electrode are formed from a same conductive film, the first lower electrode is electrically connected to the first doped layer via a first contact plug directly connected to the first lower electrode, the second lower electrode is electrically connected to the second doped layer via a second contact plug directly connected to the second lower electrode, and the transverse dimension of the bottom of the second lower electrode being rectangular in planer shape is shorter than the transverse dimension of the bottom of the first lower electrode being rectangular in planer shape.