Patent ID: 7457392

Claim:
A delay locked loop, comprising: an input terminal for obtaining a clock signal that will be delayed; an output terminal for providing a delayed output clock signal; a first delay device with a first digitally controllable delay time having a step size, said first delay device having an output; a second delay device with a second digitally controllable delay time having a step size that is larger than the step size of the first delay time, said first delay device and said second delay device being connected in series between said input terminal and said output terminal, said second delay device being connected downstream of said first delay device; a control device for providing a first control signal to said first delay device and a second control signal to said second delay device in a manner dependent on a phase difference between the clock signal that will be delayed and the delayed output clock signal; a first clock-controllable storage element connected between said control device and said first delay device for feeding the first control signal to said first delay device; a second clock-controllable storage element connected between said control device and said second delay device for feeding the second control signal to said second delay device; said first storage element and said second storage element each having a clock input coupled to said output of said first delay device; said output of said first delay device being designed to provide a delayed signal that has been delayed by said first delay device; said second delay device having an input that receives the delayed signal from said output of said first delay device; said second delay device including a plurality of multiplexers each having a first input and a second input and an output; said outputs of said plurality of multiplexers in each case being connected to said first input of another of said plurality of multiplexers; and the second inputs of said plurality of multiplexers in each case being connected to said input of said second delay device.