Patent ID: 7542023

Claim:
A shift register, comprising: M (M is an integer larger than two) stages of transfer elements that transfer N (M>N, N is an integer larger than one) data signals sequentially input within one cycle; and a control circuit to which N clock signals and a control signal are input within the one cycle and that supplies a shift clock signal to N stages of the transfer elements among the M stages of the transfer elements and supplies a skip fixed logic signal to (M−N) stages of the transfer elements among the M stages of the transfer elements based on the control signal, each of the N stages of the transfer elements holding an input data signal instead of a data signal that has been held by the each of the N stages of the transfer elements based on the shift clock signal, and each of the (M−N) stages of the transfer elements allowing a data signal that has been held by one of the transfer elements in a preceding stage to pass therethrough to one of the transfer elements in a subsequent stage based on the skip fixed logic signal.