Patent ID: 7920028

Claim:
A bias circuit for applying a bias voltage to a nonlinear amplification circuit, comprising: a constant-current source; and a first, second, third, and fourth transistors, wherein a current mirror circuit is configured by the first transistor and the second transistor, a drain and gate of the third transistor and a gate of the fourth transistor are connected, the first transistor and the third transistor are cascade connected, the second transistor and the fourth transistor are cascade connected, and the bias voltage is outputted from the drain of the second transistor, gate lengths and gate widths of the first and second transistor are the same, gate lengths of the first to fourth transistor are the same, and gate lengths and gate widths of the first, second, third, and fourth transistor are configured so that k 4 −0.5 −k 3 −0.5 is approximately 1, where k 3 stands for a ratio of a gate width of the third transistor to the gate width of the first transistor and k 4 stands for a ratio of a gate width of the fourth transistor to the gate width of the first transistor.