Patent ID: 7631244

Claim:
A soft error correction method for a memory system having n memory access controllers and a system controller, said soft error correction method comprising: accessing, by any one of the n memory access controllers, a corresponding one of n memories for storing byte-sliced data in cycle synchronism; receiving, by the system controller, a memory access from an arbitrary one of m MPUs and issuing memory address with respect to the n memory access controllers, where m and n are integers greater than or equal to two; when any one of the n memory access controllers detects a correctable error in data read from a corresponding one of the memories, holding, in the memory access control that detected the correctable error, an error address of the corresponding one of the memories where the error was detected, and making an error notification to the system controller with the error address from the memory access controller that detected the correctable error; sending an error correction request from the system controller to the n memory access controllers with the error address in response to the error notification without intervention from the m MPUs; and responsive to the error notification, reading the data from the error address of the corresponding one of the memories, correcting the error and rewriting corrected data to the error address, by the memory access controller holding the error address.