Patent ID: 8058891

Claim:
A delay lock loop circuit comprising: a delay circuit in which a plurality of delay elements each having an equal delay amount are connected in tandem series and which supplies a predetermined delay amount to an input signal to output the delayed signal as an output signal; a phase comparator which outputs a phase signal based on a phase difference between the input signal and the output signal; a counter which receives the phase signal from the phase comparator to output a control signal; a delay time acquiring section which receives the control signal from the counter to output a delay time signal; a cycle slip detection circuit which detects whether or not the output signal causes cycle slip, the cycle slip detection circuit comprising a logical circuit which receives the input signal and the output signal to output a phase difference detection signal indicating whether or not a phase of the input signal matches that of the output signal; and a sequence circuit which outputs a cycle slip detection signal indicating whether or not the output signal causes the cycle slip on the basis of the phase difference detection signal from the logical circuit; and count control means for controlling a count value of the counter in a case where it is detected that the cycle slip is caused.