Patent ID: 8058100

Claim:
A method for fabricating a chip scale package structure, the method comprising: providing a carrier and forming a plurality of metal pads on a predetermined part of a surface of the carrier; mounting a plurality of chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the surface of the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the exposed predetermined part of the first conductive traces; and cutting the encapsulant to form a plurality of chip scale package structures.