Patent ID: 8041758

Claim:
A multiplier comprising: a multiplication array in which partial products are generated by performing multiplication between an n-bit multiplier (n: a natural number) and an n-bit multiplicand; an adder which adds the generated partial products together; and a partial product control circuit which generates an enable signal for activating an effective region in the multiplication array corresponding to effective figures of the multiplier and the multiplicand, wherein the effective figures depend on a format of the multiplier and the multiplicand, and the partial product control circuit controls a status of the enable signal according to a multiplication command designating the format, wherein the multiplication array is constituted by a dynamic circuit; the dynamic circuit in an initial stage of the multiplication array has a switch which is turned on/off by the enable signal; and, when the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.