Patent ID: 7221551

Claim:
An ESD protection circuit connected between a first terminal and a second terminal of an integrated circuit, the ESD protection circuit comprising: a charge dissipation circuit, having more than one bias inputs, that is operable to direct ESD current from one terminal to the other with a relatively low resistance according to signals received in the charge dissipation circuit by the more than one bias inputs to the charge dissipation circuit; an ESD detection circuit connected to the first and second terminals and operable to detect an ESD event comprising detecting when a large voltage has been induced between the first and second terminals and to provide, upon that event, a control signal that is indicative of the detected large voltage; a bias control circuit connected to the ESD detection circuit and operable upon receipt of the ESD detection circuit's control signal to assert the more than one bias inputs; and a timing circuit within the ESD detection circuit that is operable in conjunction with the bias control circuit to generate a first timing signal that is operable to maintain a first of the bias inputs as positively asserted for a first substantially certain time and a second timing signal that is operable to maintain a second of the bias inputs as positively asserted for a second substantially certain time.