Patent ID: 7876142

Claim:
A latch inverter, comprising: a first transistor, the gate of the first transistor receiving a data signal and the source of the first transistor connected to a voltage source; a second transistor, the gate of the second transistor receiving a first trigger clock and the source of the second transistor connected to the drain of the first transistor; a third transistor, the gate of the third transistor receiving a second trigger clock and the drain of the third transistor directly connected to the drain of the second transistor to generate an output signal; a fourth transistor, the gate of the fourth transistor receiving the data signal, the drain of the fourth transistor directly connected to the source of the third transistor, and the source of the fourth transistor being grounded; a fifth transistor, the gate of the fifth transistor receiving the data signal, the drain of the fifth transistor connected to the source of the second transistor, and the source of the fifth transistor being grounded; wherein the fifth transistor is used for providing the source of the second transistor with a first logic level; a sixth transistor, the gate of the sixth transistor receiving the data signal, the source of the sixth transistor connected to a voltage source, and the drain of the sixth transistor connected to the drain of the fourth transistor; wherein the sixth transistor is used for providing the drain of the fourth transistor with a second logic level; wherein the drain of the fifth transistor and the drain of the sixth transistor are separated, and wherein the first and second trigger clocks are independent of the output signal.