Patent ID: 7196370

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array region including a plurality of NAND cells arranged in a matrix manner, each NANID cell having a plurality of memory cell transistors each of which has a stacked gate structure in which a floating gate and control gate are stacked on a semiconductor substrate, a source region, a drain region, and a channel region, and which are arranged in series to share the source and drain regions; a plurality of select transistors formed on the semiconductor substrate, said plurality of select transistors being arranged one at each of two ends of each NAND cell, having a source region, drain region, and channel region, and forming a NAND column together with the NAND cell by sharing the source region or drain region between two memory cell transistors at the two ends of the NAND cell; a first trench-type isolation region formed between columns in an array of the NAND columns, formed in self-alignment with end portions of the channel region and floating gate of the memory cell transistor, and having a recess formed in an upper surface between the floating gates of the memory cell transistors; a second trench-type isolation region having a flat upper surface and formed in self-alignment with an end portion of the channel region of the select transistor between columns in an array of the NAND) columns; a plurality of control gate lines each connected to the control gates of the memory cell transistors in the same row of the memory cell array region, and running in a row direction; a plurality of select gate lines connected to gates of the select transistors in the same row, and running in the row direction; a bit line connected, via a bit line contact, to the drain regions of the select transistors at opposing ends of two NAND columns adjacent to each other in a column direction in the array of the NAN) columns; and a source line connected to the source regions of the select transistors at the other ends of the two NAND columns adjacent to each other in the column direction in the array of the NAND columns.