Patent ID: 7939857

Claim:
A composite device comprising a depletion mode FET including gate, drain and source terminals, and an array of n bipolar transistors including (n−1) bipolar transistors connected in parallel having respective first collector terminals tied together, and respective first emitter terminals tied together, and one (1) sense bipolar transistor connected in parallel with the (n−1) bipolar transistors having a second collector terminal tied to the respective first collector terminals, and a second emitter terminal electrically isolated from the first emitter terminals, wherein a voltage V CE between the first and second collector terminals and the first and second emitter terminals is configured to bias the depletion mode FET, and a current I SENSE flowing through the second emitter terminal provides a value that is approximately equal to a current I D flowing through the drain terminal divided by (C*n), where C is a constant value and n is the size of the array.