Patent ID: 7495287

Claim:
A method of manufacturing a semiconductor device on a semiconductor substrate that has a first element region having a silicon-on-insulator structure (SOI) structure, a second element region having a bulk structure and an element isolation region separating each region, the first region and the second region being provided in a plural number, the method comprising: etching a part of a first area situated next to the first element region in the first element region and/or the element isolation region on the semiconductor substrate to a predetermined depth; forming a mask layer in an unetched second area other than the etched first area; forming a first semiconductor layer made of a material that has a larger etching rate than an etching rate of the semiconductor substrate selectively in an unmasked area; forming a second semiconductor layer made of a material that has a smaller etching rate than the etching rate of the first semiconductor layer on the first semiconductor layer; forming a first groove in a third area where the first semiconductor layer and the second semiconductor layer are formed in the element isolation region, the first groove penetrating the first semiconductor layer and the second semiconductor layer and exposing the semiconductor substrate; forming a supporting layer in the first groove and in at least a part of the first element region, the supporting layer supporting the second semiconductor layer on the semiconductor substrate; forming a second groove in the element isolation region except an area where the first groove is formed, the second groove exposing the first semiconductor layer; forming a cavity under the second semiconductor layer by removing the first semiconductor layer by etching the first semiconductor layer through the second groove; and forming a buried insulating layer embedded in the cavity through the second groove.