Patent ID: 8637957

Claim:
A semiconductor structure comprising: an interconnect dielectric material having at least one opening located therein; an anti-fuse structure located within the least one opening, wherein the anti-fuse structure comprises: a diffusion barrier liner located within the at least one opening and in direct contact with at least sidewall surfaces of the interconnect dielectric material, a first conductive metal plug located within the at least one opening and located on an exposed surface of the diffusion barrier liner, wherein said first conductive metal plug includes vertical sidewall portions that extend upward from an uppermost surface of the first conductive metal plug, an anti-fuse material liner located on an exposed surface of the first conductive metal plug and an exposed surface of the vertical sidewall portions, a second conductive metal plug located on an exposed surface of the anti-fuse material liner, wherein each of the diffusion barrier liner, the vertical sidewall portions, the anti-fuse material liner, and the second conductive metal plug have an uppermost surface that is co-planar with an uppermost surface of the interconnect dielectric material; and an interconnect structure located within a portion of the interconnect dielectric material that lies laterally adjacent the interconnect dielectric material including the anti-fuse structure, wherein said interconnect structure is present within at least one other opening, said at least one other opening is filled with another portion of the diffusion barrier liner, another portion of the first conductive metal plug and other vertical sidewall portions that extend upward from an uppermost surface of the another portion of first conductive metal plug, and another portion of the second conductive metal plug.