Patent ID: 7669090

Claim:
An apparatus for verifying a test IC, comprising: a computer configured to generate a verification test start command; a test pattern generating unit connected to receive said verification test start command for generating a test pattern for verifying a function of said test IC, said test pattern being output to a master IC and the test IC; a comparing unit connected to receive operation signals output from said master IC and said test IC for comparing said operation signals to see if said operation signals are agreed with each other and for generating a comparison signal based on a comparison result; and a judging unit connected to receive said comparison signal for judging if there is any abnormality in said test IC and for outputting a judged signal based on a judged result, said computer being connected to receive said judged signal for displaying said judged result of said test IC and being configured to judge and display whether or not there is an abnormality in said apparatus for verifying said test IC, wherein said test pattern is further input to said judging unit from said test pattern generating unit without being input to said master IC or said test IC, and said computer stores an expected test pattern which is expected to be generated in said test pattern generating unit, said judging unit outputs said test pattern to said computer and said computer compares said test pattern to said expected test pattern, and said computer displays whether or not there is an abnormality in said test pattern generating unit based on a comparison result so as to verify said apparatus itself, and wherein said operation signal from said master IC is input to said judging unit, and said computer stores an expected operation signal which is expected to be generated from said master IC, said computer is connected to receive said operation signal from said master IC output from said judging unit and compares said operation signal to said expected operation signal, and said computer displays whether or not there is an abnormality in said master IC based on a comparison result so as to verify said apparatus itself.