Patent ID: 7924184

Claim:
An integrated circuit comprising: programmable circuitry; and a channel of high-speed serial data signal receiver circuitry that is hard-wired to always output in parallel a predetermined number of data bits that were received by the channel serially; wherein a portion of the programmable circuitry is programmed to receive the predetermined number of data bits from the channel and to output bits thus received in groups of parallel bits, each of which groups can include a number of bits having any of a plurality of programmably selectable ratios to the predetermined number; wherein the channel receives the data bits serially at a serial bit rate and produces a first reference clock signal having a first frequency that is the serial bit rate divided by the predetermined number; wherein said portion of the programmable circuitry is responsive to the first reference clock signal to clock the predetermined number of data bits received from the channel into said portion; and wherein the programmable circuitry further comprises: phase-locked loop circuitry that receives the first reference clock signal and that is programmable to produce a second clock signal having a second frequency that has any one of the programmably selectable ratios to the first frequency.