Patent ID: 7876584

Claim:
A circuit for controlling the secondary FET of a transformer coupled synchronous rectified flyback converter (TCSC) having a primary circuit and a secondary circuit with transformer coupling there between, the primary circuit having a primary transformer coil (PTC) coupled with a primary switching network (PSN) being switched by its built-in primary switching FET (FET pm ), the secondary circuit having a serial connection of a secondary transformer coil (STC) with a secondary coil voltage (Vsec) there across, an output capacitor (Cout) and a secondary switching FET (FET sc ) having a built-in parasitic body diode BD sc with a forward voltage V SD there across, each of the synchronous switching cycles of the TCSC is characterized by a sequence of time marks t PCR , t PSX and t SIC wherein t PCR marks the start of primary coil current (Ipri) ramp up followed by a negative 0-crossing of Vsec, t PSX marks the instant of primary coil current (Ipri)-to-secondary coil current (Isec) transfer followed by a positive 0-crossing of V SD with Vsec ringing and t SIC marks the start of FET sc first-quadrant conduction followed by a positive 0-crossing of I DS also with Vsec ringing, the secondary FET control circuit comprises: a) a V SD sense trigger with a digital trigger output signal V SD -trigger and its analog inputs coupled to the FET sc terminals for sensing the V SD and, upon sensing a positive 0-crossing of V SD , for activating said V SD -trigger; b) an I DS sense trigger with a digital trigger output signal I DS -trigger and its analog inputs coupled to the FET sc terminals for sensing a drain-to-source current I DS of the FET sc and, upon sensing a positive 0-crossing of I DS , for activating said I DS -trigger; c) a Vsec sense trigger with a digital trigger output signal Vsec-trigger and its analog inputs coupled to the STC terminals for sensing the Vsec and, upon sensing a negative Vsec, for activating said Vsec-trigger; and d) a multiple-trigger gate driver (MTGD) having digital trigger inputs V SD -input, I DS -input and Vsec-input respectively coupled to said V SD -trigger, I DS -trigger and Vsec-trigger, a drive output signal V GATE coupled to the gate of FET sc and a set of logic states of: state-I where the FET sc is turned off and latched thus can not be triggered on; state-II where the FET sc is turned off but unlatched thus can be triggered on; and state-III where the FET sc is turned on but unlatched thus can be triggered off; and said MTGD is configured to enter state-III upon activation of said V SD -trigger, enter state-I upon activation of said I DS -trigger and enter state-II upon activation of said Vsec-trigger whereby avoid false triggering of the FETs sc caused by the numerous undesirable Vsec ringings, into incorrect states around the time marks t PSX and t SIC that would otherwise result in an increased secondary power loss of the TCSC.