Patent ID: 7462533

Claim:
A method for fabricating a memory cell, comprising: forming a stacked insulating layer, and a lower conductive layer on a semiconductor substrate; patterning the lower conductive layer and the insulating layer to form a gap region; forming a gate insulating layer on exposed surfaces of the semiconductor substrate and the lower conductive layer in the gap region; forming a gate pattern on the gate insulating layer for filling the gap region, the gate pattern protruded upward to have sidewall portions exposed above the lower conductive layer; forming an upper sidewall pattern on each exposed sidewall portion of the gate pattern; patterning the lower conductive layer and the insulating layer to form a lower sidewall pattern and a charge storage layer under each upper sidewall pattern, wherein the gate pattern and each upper sidewall pattern are used as an etching mask; and forming a source region and a drain region in the semiconductor substrate.