Patent ID: 8088679

Claim:
A method for fabricating an integrated circuit, comprising: fabricating a gate electrode level region above and over a substrate region, wherein the gate electrode level region forms part of an overall gate electrode level of the integrated circuit, and wherein the substrate region forms part of an overall substrate of the integrated circuit, wherein fabricating the gate electrode level region includes fabricating a plurality of linear conductive segments each formed to have a respective length and a respective width as measured parallel to the substrate region, wherein a size of the length of a given linear conductive segment is greater than a size of the width of the given linear conductive segment, wherein the plurality of linear conductive segments are fabricated to have their lengths extend in a first direction in a parallel manner, and wherein the plurality of linear conductive segments are positioned in a side-by-side and spaced apart manner according to a substantially equal centerline-to-centerline spacing as measured in a second direction perpendicular to the first direction, and wherein the plurality of linear conductive segments include a first linear conductive segment defined to form both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, and wherein the plurality of linear conductive segments include a second linear conductive segment that does not form a gate electrode of a transistor device, and wherein the plurality of linear conductive segments include a third linear conductive segment defined to form both a gate electrode of a second transistor of the first transistor type and a gate electrode of a second transistor of the second transistor type.