Patent ID: 8176215

Claim:
A semiconductor memory device capable of connecting to a host device, comprising: a semiconductor memory unit; a host interface unit configured to perform data transfer with the host device and compatible with a plurality of transfer modes obtained by combining one of a plurality of drive voltage modes and one of a plurality of transfer clock modes; a transfer mode control unit configured to output an error code to the host device if the host device inputs a transfer mode change command instructing the semiconductor memory device to change a current transfer mode in a first transfer clock mode and a first drive voltage mode to a second transfer clock mode not supported by the host interface unit in the first drive voltage mode; wherein each transfer mode is a combination of one of the plurality of drive voltage modes, one of the plurality of transfer clock modes, and one of a plurality of transfer bus width modes, and the transfer mode control unit changes a current transfer mode to a combination of a second transfer bus width mode and a second transfer clock mode supported by the host interface unit upon inputting from the host device of a transfer mode change command instructing the semiconductor memory device to change to the second transfer clock mode, which is not supported by the host interface unit in a first transfer bus width mode, when the host interface unit is in the first transfer bus width mode and the first transfer clock mode.