Patent ID: 7117321

Claim:
A method for interleaving SDRAM device access requests, comprising the steps of: establishing at least one master scoreboard register having a number of bits corresponding to a number of available request cycles and wherein a value of each bit in the at least one master scoreboard register is indicative of whether an access command has been accepted for delivery to the SDRAM; receiving an SDRAM access request from at least one device, wherein the SDRAM access requests includes at least one requested cycle for accessing the SDRAM; identifying the bits in the at least one master scoreboard register associated with the at least one requested cycle; determining whether at least one of the identified bits have been previously set; accepting the SDRAM access request if it is determined that none of the identified bits have been previously set; and performing the following steps if it is determined that at least one of the identified bits has been previously set: incrementing the at least one master scoreboard register by one bit; and returning, at a subsequent clock tick, to the step of identifying the bits in the at least one scoreboard register associated with the at least one requested cycle.