Patent ID: 7181563

Claim:
A FIFO memory with single port memory modules for allowing simultaneous read and write operations, comprising: a first single port memory module for an even address of an operation; a second single port memory module for an odd address of said operation, wherein said even address and said odd address alternate; a memory control module, communicatively coupled to said first single port memory module and said second single port memory module, for controlling distribution of reading and writing requests between said even address and said odd address and performance of postponed writing; a data output selection module, communicatively coupled to said first single port memory module and said second single port memory module, for selecting a value between a first output value from said first single port memory module and a second output value from said second single port memory module and holding said value until a next read request comes; a read and write request update module, communicatively coupled to said memory control module and said data output selection module, for updating RE (read enable) and WE (write enable) input flags to avoid reading from empty said first single port memory module and said second single port memory module and writing into full said first single port memory module and said second single port memory module; and an address and status update module, communicatively coupled to said read and write request update module, said memory control module and said data output selection module, for updating values of address registers R_ADR (read address) and W_ADR (write address) used for access to said first single port memory module and said second single port memory module.