Patent ID: 7423461

Claim:
A phase synchronous circuit; comprising: a first delay array; a first selector that selectively inputs either one of a first reference clock and the outputs of the first delay array to the first delay array; a plurality of phase comparators that perform a phase comparison with each delay stage included in the first delay array and a second reference clock; a second delay array; a second selector that selectively inputs either one of the outputs of an external clock and the second delay array to the second delay array; and an output control circuit that selectively outputs an output outputted from each delay stage of the second delay array as an internal clock, wherein the output control circuit grasps a number of round-trips and a number of stages of the first delay array required to make a delay signal of the first reference clock generated by the first delay array synchronize with the second reference clock, and outputs the delay signal by the second delay array of the external clock corresponding to the grasped number of round-trips and number of delay stages as the internal clock.