Patent ID: 8642385

Claim:
A wafer level chip scale package method of forming a semiconductor device comprises the following steps: providing a wafer comprising a plurality of semiconductor chips; forming a plurality of solder bumps on a front side of the wafer electrically connected to a plurality of bonding pads of the semiconductor chips; casting a first molding material on the front side of the wafer such that the front side of the wafer and the solder bumps are covered by a first molding layer; grinding a backside opposite to the front side of the wafer; cutting through the wafer from its backside after grinding to form cutting grooves separating each of the semiconductor chips, and the cutting grooves extending to a depth in the first molding layer; casting a second molding material on the backside of the wafer to form a second molding layer covering the backside of the thinned wafer and at the same time filling in the cutting grooves; grinding the first molding layer to expose a top surface of the solder bumps; cutting along the cutting grooves to separate the semiconductor chips, the first and second molding layers covering the front side, the backside and sidewalls of the separated chips.