Patent ID: 8829672

Claim:
A semiconductor package, comprising: a dielectric layer having opposite first and second surfaces; at least a semiconductor chip embedded in the dielectric layer and having an active surface with a plurality of electrode pads, and a non-active surface opposite to the active surface and exposed from the second surface of the dielectric layer; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface of the dielectric layer; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces of the dielectric layer, respectively; a first circuit layer formed on the first surface of the dielectric layer for electrically connecting the first and second metal posts; and a second circuit layer formed on and projected from the second surface of the dielectric layer for electrically connecting the second circuit layer to the second metal post.