Patent ID: 6956423

Claim:
An interleaved clock generator for generating N interleaved clock signals in response to an input clock signal, where N is a non-prime integer, the interleaved clock generator comprising: interleaved clock generator means of a first type for receiving the input clock signal and for generating in response thereto M interleaved intermediate clock signals, where M is a factor of N and is an integer greater than unity, the interleaved clock generator means of the first type including one of (a) a multi-stage serial-delay circuit and (b) a ring counter circuit; and M interleaved clock generator means of a second type, each for receiving a respective one of the intermediate clock signals from the clock generator means of the first type and for generating in response thereto N/M of the N interleaved clock signals, each of the interleaved clock generator means of the second type including the other of (a) the multi-stage serial-delay circuit and (b) the ring counter circuit, wherein: corresponding edges of temporally adjacent ones of the interleaved clock signals differ in time by a time delay Td; the interleaved clock signals have a frequency of 1/(N*Td); the input clock signal has a frequency of 1/(M*Td) when the interleaved clock generator means of the first type includes the multi-stage serial delay circuit; and the input clock signal has a frequency of M/(N*Td) when the interleaved clock generator means of the first type includes the ring counter circuit.