Patent ID: 7778092

Claim:
A system, comprising: a memory controller; a module including a memory buffer of a first type coupled to a memory device of a first type, the memory buffer being coupled to the memory controller through a memory bus; and a memory module including a memory buffer of a second type coupled to the memory bus and a memory device of a second type coupled to the memory buffer of the second type, the memory buffer of the second type comprising: a downstream link interface coupled to receive a memory request of a first type from the memory controller through the memory bus; an upstream link interface coupled to transmit read data to the memory controller through the memory bus; a memory interface coupled to the memory device of the second type; a converter configured to generate a signal according to a protocol for accessing the memory device of the second type responsive to a memory request of the first type received by the downstream link interface and pass the signal to the memory interface; and a memory transfer state machine coupled to at least one of the converter and the memory interface, the memory transfer state machine being configured to generate timed signals that implement a memory access of the memory device of the second type corresponding to a memory request of the first type received by the downstream link interface.