Patent ID: 8384189

Claim:
An integrated circuit chip comprising: a silicon substrate; a transistor in or on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure, and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride layer; a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers; a patterned circuit layer on said first polymer layer and over said passivation layer, wherein said patterned circuit layer is connected to said first contact point through said first opening, wherein said patterned circuit layer comprises a coil connected to said first contact point through said first opening and connected to said second contact point through said second opening, wherein said coil comprises an electroplated metal; and a second polymer layer over said patterned circuit layer.