Patent ID: 6914835

Claim:
A semiconductor memory device, comprising: a plurality of memory cells; paired bit lines connected to the plurality of memory cells; a plurality of precharge circuits for precharging the paired bit lines to a predetermined precharge voltage in accordance with a first control signal; and a bit line precharge voltage generation unit for supplying a voltage for precharging to the plurality of precharge circuits, an equalizing voltage of the paired bit lines being different from the precharge voltage, the bit line precharge voltage generation unit comprising: a precharge voltage generation circuit for generating the precharge voltage and supplying the precharge voltage to the plurality of precharge circuits; and a precharge voltage pumping circuit including a pumping capacitor, a first switch for connecting a first electrode of the pumping capacitor to a first power source, a second switch for connecting the first electrode to an output node of the precharge voltage generation circuit, a third switch for connecting a second electrode of the pumping capacitor to the first power source, a fourth switch for connecting the second electrode to a second power source, and a control circuit for controlling on/off of the first, second, third, and fourth switches.