Patent ID: 7039576

Claim:
A system verification method to be applied by an intellectual property user for verifying operation of an integrated system design constructed with modules designed in-house and at least one module protected as intellectual property of an outside entity, said verification method comprising: providing design data or a verification model of each of the modules; simulating the operation of the integrated system with one of the input vector sequences so as to obtain a respective output vector sequence, which includes the steps of: dividing a simulation time period into a finite number of time steps in sequence from time 0 to time n; supplying an input vector for said each of the modules at one time step, while observing an internal state of said each module at the respective time step; computing an output vector from said each in-house designed module and the internal state at a starting time of a time step subsequent to the time step, based on the design data or the verification model; transmitting an input vector for said each module of the outside entity to the outside entity at said one time step through a communication line such that the outside entity simulates operation of said each module with the input vector at said one time step so as to compute an output vector; receiving the output vector from the outside entity through a communication line at a beginning of the subsequent time step; integrating the output vectors from all modules at the subsequent time step to obtain an output of the whole system at the subsequent time step; and repeating the supplying, computing, transmitting, receiving and integrating steps from time 0 to time n sequentially to obtain an output sequence of the whole system.