Patent ID: 8547760

Claim:
An apparatus for memory access alignment in a double data rate (DDR) system, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the processor, cause the apparatus to carry out the steps of: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including signaling the DDR memory module of the one or more write operations and sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including signaling the DDR memory module of the read operations and capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations, wherein the read adjust value comprises a number of cycles between signaling the read operations and capturing the data, and wherein the write adjust value comprises a number of cycles between signaling the DDR memory module of the one or more write operations and sending to the DDR memory module the predetermined amount of data of the predetermined pattern along with the data strobe signal.