Patent ID: 7652512

Claim:
A clock synchronizing circuit, applied in a synchronous mirror delay (SMD) block for receiving an input clock, the clock synchronizing circuit comprising: a plurality of stages of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, each clock synchronizing unit comprising: a forward delay unit, for outputting a first delayed clock; a mirror control unit, coupled to the forward delay unit, for outputting a mirror clock according to the input clock and the first delayed clock, the mirror control unit comprising: a first mirror-control device, for outputting a first mirror-controlled clock according to the input clock; a second mirror-control device, for outputting a second mirror-controlled clock according to the first delayed clock; and a third mirror-control device, coupled to the first mirror-control device and the second mirror-control device for outputting the mirror clock according to the input clock, the first mirror-controlled clock and the second mirror-controlled clock; and a backward delay unit, coupled to the mirror control unit for delaying the mirror clock to the corresponding output clock; wherein in a first timing period when the input clock has a first level and the first delayed clock has a second level, the first mirror-controlled clock has the second level, the second mirror-controlled clock has the first level and the mirror clock has the second level.