Patent ID: 7300831

Claim:
A method of fabricating an array substrate structure for a liquid crystal display device, comprising: sequentially forming a transparent conductive material layer and a metallic material layer on a substrate defining a display area and a non-display area, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and a p-type driving TFT portion; forming a first gate electrode in the p-type driving TFT portion, a second gate electrode in the n-type driving TFT portion, a third gate electrode in the pixel TFT portion, a gate line in the display area, a pixel electrode in the pixel electrode area, and a first capacitor electrode connected to the pixel electrode through a first mask process; sequentially forming a gate insulating layer and a silicon layer on the first gate electrode, the second gate electrode, the third gate electrode, the gate line, the pixel electrode and the first capacitor electrode; doping the silicon layer in the p-type driving TFT portion with high concentration p-type impurities (p+) through a second mask process to define a first active region and a first ohmic contact region; doping the silicon layer in the pixel TFT portion and the n-type driving TFT portion with high concentration n-type impurities (n+) and low concentration n-type impurities (n−) through a third mask process to define second and third active regions, second and third ohmic contact regions, first and second lightly doped drain (LDD) regions and a storage capacitor area; forming a first semiconductor layer in the p-type driving TFT portion, a second semiconductor layer in the n-type driving TFT portion, a third semiconductor layer in the pixel TFT portion, and a second capacitor electrode in the storage capacitor area through a fourth mask process; forming a passivation pattern on the first, second and third semiconductor layers through a fifth mask process, wherein the passivation pattern covers the first, second and third active regions, and wherein the first, second and third ohmic contact regions are exposed through the passivation pattern; and forming first source and drain electrodes, second source and drain electrodes, third source and drain electrodes and a data line through a sixth mask process, the first source and drain electrodes contacting the first ohmic contact region, the second source and drain electrodes contacting the second ohmic contact region, the third source and drain electrodes contacting the third ohmic contact region, and the data line connected to the third source electrode.