Patent ID: 8576865

Claim:
A system comprising: a first integrated circuit (IC) including a first set of (N+1) serializer/deserializer (SERDES) modules configured to communicate with a first set of (N+1) SERDES modules of a switch IC of a switch, respectively, where N is an integer greater than 1; a first set of N SERDES modules configured to communicate with a first set of N ports of the switch, respectively; and a first set of N multiplexer modules configured to communicate with (i) the N SERDES modules in the first set of N SERDES modules, respectively, and (ii) the (N+1) SERDES modules in the first set of (N+1) SERDES modules of the first IC, wherein each of the N multiplexer modules is configured to communicate with a pair of SERDES modules in the first set of (N+1) SERDES modules of the first IC; and a second IC including a second set of (N+1) SERDES modules configured to communicate with a second set of (N+1) SERDES modules of the switch IC, respectively; a second set of N SERDES modules configured to communicate with a second set of N ports of the switch, respectively; and a second set of N multiplexer modules configured to communicate with (i) the N SERDES modules in the second set of N SERDES modules, respectively, and (ii) the (N+1) SERDES modules in the second set of (N+1) SERDES modules of the second IC, wherein each multiplexer module in the second set of N multiplexer modules is configured to communicate with a pair of SERDES modules in the second set of (N+1) SERDES modules of the second IC.