Patent ID: 7827327

Claim:
A circuit enabling the transfer of data, said circuit comprising: an input multiplexer receiving a first plurality of input data bytes at a first plurality of input ports at a first time and receiving a second plurality of input data bytes at said first plurality of input ports at a second time; a switching controller coupled to said input multiplexer and controlling the output of said first plurality of input data bytes and said second plurality of input data bytes from said input multiplexer; delay register circuitry coupled to said input multiplexer and receiving predetermined bytes of said first plurality of input data bytes; and an output multiplexer coupled to said input multiplexer and said delay register circuitry, said output multiplexer receiving said predetermined bytes of said first plurality of input data bytes and predetermined bytes of said second plurality of input data bytes, and generating output data bytes at a second plurality of output ports of said output multiplexer, wherein a number of output ports of said second plurality of output ports is equal to a number of input ports of said first plurality of input ports.