Patent ID: 7638263

Claim:
A method of forming an overlay accuracy measurement vernier, the method comprising: forming a first vernier pattern in a predetermined region on a semiconductor substrate, said first vernier pattern having a width; etching the semiconductor substrate using the first vernier pattern as a mask, forming first trenches of a first depth; forming a second vernier pattern having a width wider than the width of the first vernier pattern, the second vernier pattern including the first vernier pattern; etching the semiconductor substrate using the second vernier pattern as a mask to form second trenches of a second depth in the first trenches, thereby forming dual depth trenches comprising the first trenches and the second trenches and having a step of a predetermined width; stripping the first and second vernier patterns and then forming an insulating film to bury the first and second trenches; and etching the insulating film so that at least a portion of the semiconductor substrate of the predetermined region is exposed.