Patent ID: 8754685

Claim:
A circuit comprising: a delay line; and a delay locked loop, wherein the circuit is configured to receive a delay parameter and a clock signal; the delay locked loop is configured to generate a pair of control codes based on a frequency of the clock signal and a frequency of an oscillator of the delay locked loop; the delay locked loop is configured to determine a difference in a phase of a divided signal of the clock signal and a phase of a divided output of the oscillator after the divided output of the oscillator and the divided clock signal are aligned; the delay line is configured to receive an input signal and generate an output signal delayed from the input signal by a time delay that corresponds to a delay line control code calculated from the pair of control codes and the delay parameter; and the delay locked loop is configured to change a frequency of the oscillator corresponding to a first control code of the pair of control codes and to change a frequency of the oscillator corresponding to a second control code of the pair of control codes.