Patent ID: 6887760

Claim:
A process for forming a trench gate power MOS transistor comprising: forming an epitaxial layer having a first type of conductivity on a semiconductor substrate; forming a body region having a second type of conductivity on the epitaxial layer; defining an edge structure and an active area of the transistor in the body region and in the epitaxial layer; forming a gate trench in the active area so that the body region is adjacent opposite sides of the gate trench; countersinking upper portions of the gate trench; forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof; forming a gate conducting layer on surfaces of the gate dielectric layer for defining a gate electrode, the gate conducting layer having a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein; filling the residual cavity of the gate trench with a filler layer, the filler layer having a thickness that is at least double a depth of the residual cavity; planarizing the filler layer and the gate conducting layer; removing the gate conducting layer on an upper surface of the body region while using the filler layer as a self-aligned mask; oxidizing edge surfaces of the gate conducting layer; and forming source regions by implanting dopants in the body region while using the oxidized edge surfaces as a self-aligned mask, and diffusing the implanted dopants in the body region, the body and source regions having an electrical short-circuit therebetween.