Patent ID: 7505325

Claim:
A one time programmable memory array comprising: a read bit line; a programming bit line; a plurality of memory cells, each memory cell containing a control transistor and a floating gate transistor formed in a substrate, the control transistor and the floating gate transistor each having a first region and a second region of conductivity type opposite to the conductivity type of the substrate, said first region of the control transistor being connected to said read bit line and said second region of the control transistor being connected to said first region of the floating gate transistor, said second region of the floating gate transistor being connected to said programming bit line; a first source for providing a first voltage to said programming bit line during the programming of a floating gate transistor connected to said programming bit line and for providing a second voltage to said programming bit line during the reading of the memory cell containing said floating gate transistor; and a second source connected to said read bit line for supplying a third voltage to said first region of the control transistor in said memory cell during the programming of the floating gate transistor in said memory cell and for providing a fourth voltage to said first region of said control transistor during the reading of said floating gate transistor.