Patent ID: 8347249

Claim:
A computer implemented method for placing components for an integrated circuit, the computer implemented method comprising: receiving a plurality of nets, wherein each net is comprised of at least one pin, wherein each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net, wherein the second pin is a member of a second net, and wherein the path is associated with a slack; determining whether the path is a critical path based on the slack; responsive to a determination that the path is a critical path, reducing at least one wire length of the path; moving a non-critical component in order to reduce at least one wire length of the nets that include pins of the non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path; legalizing the components on the plurality of nets having a pin selected from the first pin and the second pin; determining whether a component is a non-critical component; responsive to a determination that component is a non-critical component, legalizing the non-critical component; and responsive to legalizing the non-critical component, incrementally optimizing a time delay of the plurality of paths.