Patent ID: 7941684

Claim:
An apparatus comprising: one or more processors, wherein each processor comprises at least one processor time stamp counter (TSC) and a first control unit coupled to the processor TSC and configured to maintain the processor TSC; and a controller coupled to the one or more processors and comprising at least one controller TSC and a second control unit coupled to the controller TSC and configured to maintain the controller TSC, wherein the controller is configured to signal a first processor of the one or more processors responsive to determining that the processor TSC is out of synchronization with the controller TSC; wherein the first processor is configured to execute a read TSC instruction, and wherein the first processor, in response to having been signalled that the processor TSC is out of synchronization, is configured to resynchronize the processor TSC to the controller TSC before generating a result for the read TSC instruction, and wherein the first processor, in response to having not been signalled that the processor TSC is out of synchronization since a most recent resynchronization of the processor TSC, is configured to generate the result responsive to the processor TSC without resynchronizing.