Patent ID: 8054931

Claim:
A timing recovery circuit, wherein the timing recovery circuit comprises: a digital phase lock loop circuit operable to: receive an error signal that indicates a difference between a predicted sample time and an ideal sample time, and apply an adjustment value such that a subsequent sample time is moved toward the ideal sample time; wherein the digital phase lock loop circuit includes: a phase gain circuit operable to modify the error signal by a phase gain to provide a phase gain output, a phase summation circuit, wherein the phase summation circuit maintains a phase offset value, and wherein the phase summation circuit includes: a phase offset register; and a first adder circuit, wherein the first adder circuit is operable to add a value maintained in the phase offset register to the phase gain output, and to write the product of the addition to the phase offset register subject to a limit imposed by an adjustment limit circuit; wherein the adjustment limit circuit is operable to detect a change in the phase offset value and to impose a limit on the phase offset value based at least in part on an offset value used to achieve a lock condition, and wherein the adjustment value is based at least in part on the phase offset value, a combination summation circuit, wherein the combination summation circuit maintains a combined adjustment value, and wherein the combination adjustment circuit includes: a combination offset register; and a second adder circuit, wherein the second adder circuit is operable to add a value maintained in the combination offset register to a frequency gain output and to the value maintained in the phase offset register, and to write the product of the addition to the combination offset register.