Patent ID: 7941776

Claim:
A method for optimizing an integrated circuit design comprising: creating a cache of post-layout patterns; optimizing said integrated circuit design using said cache of post-layout patterns to create design-specific and context-specific standard cells, wherein said optimizing said integrated circuit design comprises: a. selecting a connected, multi-input, multi-output sub-set of said standard cells from said integrated circuit design, thereby creating a sub-network; b. defining constraints to be imposed on the sub-network from said integrated circuit design, and from the sub-network's local context within said integrated circuit design; c. creating one or more implementations of the sub-network using post-layout patterns from the cache of post-layout patterns; d. building a design-specific and context-specific standard cell for each implementation determined in the previous step; e. substituting a newly built design-specific and context-specific standard cell for the sub-network, thereby forming a modified network; and f. evaluating the characteristics of said modified network with the design-specific and context-specific standard cell, and determining whether to accept or reject the design-specific and context-specific standard cell substitution; and manufacturing an integrated circuit that uses said design-specific and context-specific standard cells.