Patent ID: 7352648

Claim:
A semiconductor memory comprising: a plurality of cell arrays arranged in one direction and each having memory cells and, bit lines and word lines connected to the memory cells; a read/write control unit disposed between a pair of the cell arrays and shared by the pair of the cell arrays to control data reading and writing; a plurality of memory units each including the pair of the cell arrays and said read/write control unit; a global line extending from one end of a row of said cell arrays toward a direction where said cell arrays are arranged, and connected to said read/write control unit to be commonly used for said cell arrays; and a signal control unit disposed on one-end side of the row of said cell arrays and receiving/outputting a signal from/to said global line, wherein: said cell arrays are composed of at least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than said predetermined memory capacity and being shorter in length in the direction of the cell array arrangement than said complete cell array; and said incomplete cell array is disposed closer to said signal control unit than said complete cell array, and said incomplete cell array is included in one of said memory units, and is disposed on the signal control unit side of the corresponding read/write control unit.