Patent ID: 8327308

Claim:
A designing apparatus for designing a semiconductor integrated circuit, the designing apparatus comprising: a memory configured to store design data; and a processor configured to execute a procedure of verifying a timing of the circuit based on delay information included in the design data stored in the memory, the delay information is extracted from results of placing and wiring of the semiconductor integrated circuit, determining whether each value of hold-time errors generated as a result of the timing verification is smaller than a criteria value, extracting, when the value of a hold-time error is smaller than the criteria value, a wiring line in which the hold-time error is improved by performing a wiring line extension process, the wiring line is included in a path having the hold-time error, calculating, for the extracted wiring line, a wiring line extension distance corresponding to an insertion delay value that improves the hold-time error of the path including the extracted wiring line, performing the wiring line extension process to extend the extracted wiring line by the calculated wiring line extension distance, and setting a virtual wiring prohibitive area that causes the extracted wiring line to route via a bypass wiring line corresponding to the calculated wiring line extension distance, and extends the extracted wiring line.