Patent ID: 6990596

Claim:
A memory device comprising: a memory core; an input buffer receiving an external clock signal and generating an internal clock signal; an output path for data read from the memory core and comprising a first internal data bus, a state machine receiving the internal clock signal for controlling a data stream, the state machine being connected to an output of the memory core via the first internal data bus, and the state machine generating a control signal, a second internal bus, an output buffer connected to an output of the state machine via the second internal bus and comprising an output bus, an output stage controlled by said state machine for producing read data on the output bus, an array of master and slave pairs of flip-flops controlled by respective timing signals derived from the internal clock signal, and receiving data from said state machine on said second internal bus and providing, the data to the output stage for producing the data on said output bus, and a logic circuit generating the respective timing signals as the logic NAND and the logic AND of the internal clock signal and of the control signal of the output stage generated by said state machine, and a delay circuit, synchronized by the internal clock signal, and providing, to a control signal input of the output stage, a duplicate of the control signal delayed by a period of the internal clock signal.