Patent ID: 6949784

Claim:
A semiconductor structure of a memory device, comprising: a substrate of a first conductivity type; a first dopant region of a second conductivity type in the substrate; a second dopant region of the first conductivity type in the first dopant region, the second dopant region being more heavily doped than the first dopant region; a gate dielectric atop the second dopant region; a first gate conductor atop the gate dielectric; a self-aligned field-effect transistor comprising a second gate conductor coupled to the first gate conductor; a first contact region of the second conductivity type in the first dopant region, the first contact region being more heavily doped than the first dopant region; a second contact region of the first conductivity in the second dopant region, the second contact region being more heavily doped than the second dopant region; wherein the second dopant region, the gate dielectric, and the first gate conductor form a capacitor.