Patent ID: 7676012

Claim:
A method for generating a spread spectrum clock signal, including the steps of: providing a phase lock loop; inputting a constant clock input signal to said phase lock loop; injecting a spread spectrum modulating signal into said phase lock loop; controlling said phase lock loop so that there is a net zero cycle slip between said spread spectrum clock signal and said constant clock input signal; wherein: Cycle ⁢ ⁢ slip ⁢ ⁢ occurs ⁢ ⁢ i ⁢ f ⁢ ⁢  T wander T clk  > 1 and + _ ⁢ T wander T clk = + _ ⁢ ∂ [ F clk 4 · F mr ] wherein ±∂ is the peak percentage frequency deviation, F CLK is the clock frequency=1/T CLK , where T CLK is the clock period, Twander is the varying displacement between corresponding rising edges of said spread spectrum clock signal and said constant clock input signal, and F MR is the modulation rate.