Patent ID: 8161354

Claim:
A flash memory controller for adaptively configuring an error correction code (ECC) capability of a flash memory, the flash memory controller comprising: a control unit, generating a reading command for reading data content in the flash memory, wherein the flash memory has a data area for storing the data content and a first spare area for storing a first ECC value corresponding to the data content; a buffer for storing the data content which is read from the data area in the flash memory; an ECC module coupled to the control unit and the buffer, utilizing the data content for generating a second ECC value and comparing the second ECC value with the first ECC value to determine whether the data content comprises a plurality of errors based on the compared result of the first ECC value and the second ECC value; and a configuring unit coupled to the ECC module and the control unit, computing an amount of the errors if the data content has the errors to determine whether the amount of the errors exceeds a predetermined threshold; wherein if the amount of the errors exceeds the predetermined threshold, the configuring unit configures the data area of the flash memory via the control unit for assigning a portion of the data area to be a second spare area, and a storage capacity of the first spare area and the second spare area is associated with the ECC capability to allow the ECC module to correct the errors, and wherein the ECC module corrects the errors based on the compared result of the first ECC value and the second ECC value if the amount of the errors is less than the predetermined threshold.