Patent ID: 6921672

Claim:
A method for forming a semiconductor die, the method comprising: providing a plurality of electrically non-isolated test structures that each have a first portion and a second portion and are alternating with a plurality of electrically isolated test structures that each have a first portion and a second portion, wherein a width of each first portion of the electrically non-isolated test structures is equal to or less than a width of each second portion of the electrically non-isolated test structures; scanning a charged particle beam over the first portions of the electrically non-isolated test structures and the first portions of the electrically isolated test structures to thereby perform a voltage contrast inspection on the electrically non-isolated test structures and the electrically isolated test structures without scanning the second portions of the electrically non-isolated test structures and the second portions of the electrically isolated test structures; determining whether there is an open type defect within the second portions of the electrically non-isolated test structures based on the voltage contrast inspection of the first portions of the electrically non-isolated test structures.