Patent ID: 7398347

Claim:
A reconfigurable register apparatus comprising: a plurality of register files having a first subset of the plurality of resister files and a second subset of the plurality of register files, each register file is operable to hold a plurality of addressable entries and each addressable entry having a plurality of bits, each register file having write and read ports for accessing an addressable entry; a write multiplexer complex connecting to the write ports of each of the register files; a read multiplexer complex connecting to the read ports of each of the register files, the read multiplexer complex separate from the write multiplexer complex; and a decode and control unit connected to the write multiplexer complex and the read multiplexer complex, in response to the decode and control unit receiving a first instruction formatted to identify a first entry in the first subset, the decode and control unit configures the addressability of the plurality of register files to access the first entry, in response to the decode and control unit receiving a second instruction formatted to identify a second entry in the second subset, the decode and control unit configures the addressability of the plurality of register files to access the second entry which spans across the first subset and the second subset.