Patent ID: 8032329

Claim:
A performance monitoring apparatus, comprising: an event measurement module that includes an event generator sub-module to generate monitoring events and event measurements associated with transactions between initiator IP cores and target IP cores implemented in an system on a chip design implemented in a fabric integrated circuit, a first software visible register block to provide software access for controlling the event measurement module regarding one or more transactions to monitor and to configure one or more parameters associated with that transaction to track, as well as a filtering sub-module to select transactions to be monitored based on information received from the software, where the event measurement module includes the event generator sub-module, the first software visible register block, as well as the filtering sub-module; and a performance counter module communicatively coupled to the event measurement module to form the performance monitoring apparatus that is located on the system on a chip design implemented in the fabricated integrated circuit, wherein the performance counter module to aggregate events and event measurements received from the event measurement module into quantities of performance metrics associated with transactions between initiator IP cores and target IP cores over the interconnect.