Patent ID: 7361958

Claim:
A CMOS integrated circuit comprising: a PMOS device having a gate dielectric layer formed in an n channel region with a first dopant concentration and a pair of p-type source/drain regions and a gate electrode having a first material composition, said first material composition comprising a metal, said pair of p-type source/drain regions comprising a p-type source/drain extension region and a p-type source/drain contact region, said p-type source/drain extension regions having a second dopant concentration; and an NMOS device having a gate dielectric layer formed on a p-type channel region with a third dopant concentration and a pair of n-type source/drain regions and a gate electrode comprising said first composition, said pair of n-type source/drain regions comprising an n-type source/drain extension region and an n-type source/drain contact region, said n-type source/drain extension regions having a fourth dopant concentration, wherein said first dopant concentration and second dopant concentration and said third dopant concentration and said fourth dopant concentration are such that said gate electrode for said PMOS device exhibits a work function between 0.9-1.1 eV different than the work function exhibited by said gate electrode for said NMOS device.