Patent ID: 7929355

Claim:
A memory device, comprising: a multiplexing unit for outputting data input from global input/output lines in response to a data selection signal received in a normal mode and outputting write leveling data in response to a write leveling signal received in a write leveling mode, wherein the multiplexing unit includes a first multiplexer and a plurality of second multiplexers; a pipe latch unit for latching the data outputted from the multiplexing unit and outputting the latched data; and an output driver for receiving and outputting the latched data, wherein the first multiplexer includes a first pass gate configured to be turned on or off in response to the data selection signal and output the data input from the global input/output lines, and a second pass gate configured to be turned on or off in response to the write leveling signal and output the write leveling data, and wherein each of the second multiplexers includes a first pass gate configured to be turned or off in response to the data selection signal and output the data input from the global input/output lines.