Patent ID: 7054975

Claim:
A bus system comprising a first and second station coupled via a bus for transferring data and control signals, the bus operating according to a protocol in which the first station repeatedly sends requests for data to the second station, the second station responding to each request by sending a message with a data item or sending a negative acknowledge signal, wherein the second station comprises: an interruptable processor for generating data items; a first in first out buffer coupled between the processor and the bus, for buffering data items for successive messages in a first in first out order, the processor being programmed to start writing the data items to the buffer in response to an interrupt; a bus interface arranged to handle the protocol, sending data items from the buffer in the messages, the bus interface determining to send an interrupt to the processor in response to selected ones of the requests, as a function of whether the buffer is empty and whether interrupts have yet been generated since the processor has written into the buffer.