Patent ID: 8462038

Claim:
A successive-approximation A/D converter, comprising: a binary weighted capacitive D/A converter configured to generate a residual signal for each of cycles assigned to each bit of N bits on the basis of an analog input signal and a reference voltage; a first comparator configured to compare a residual signal at a first time point within a cycle with a predetermined voltage to acquire a first comparison result representative of a logical value; a register configured to store the first comparison result therein; a second comparator configured to compare a residual signal at a second time point later than the first time point within the cycle with the predetermined voltage to acquire a second comparison result representative of a logical value; an error determining circuit configured to generate an error detection signal when the first comparison result differs from the second comparison result; and an error-correcting circuit configured to invert, in a case that the error detection signal has been generated, the first comparison result from the register to output an inverted first comparison result, and output, in a case that the error detection signal has not been generated, the first comparison result from the register, without inverting the first comparison result.