Patent ID: 7280370

Claim:
An electronic package comprising: a circuit board comprising a substrate and one or more integrated circuits formed on the substrate; for each of the one or more integrated circuits, first and second contacts formed on the circuit board for electrically coupling the integrate circuit to a surface mount bypass capacitor, wherein (1) the first contact comprises first and second pads such that the first pad is electrically isolated from the second pad, (2) the first pad is electrically coupled to an electrical power supply, (3) the second pad is electrically coupled to the integrated circuit, and (4) no separate test contacts for continuity testing of the first and second pads are present on the substrate adjacent the pads; and for each of the one or more integrated circuits, a surface mount bypass capacitor comprising first and second terminals, wherein the first terminal is connected to both the first and second pads of the first contact and the second terminal is connected to the second contact, whereby the presence of the surface mount capacitor is indicated by a functional test of the integrated circuit.