Patent ID: 7123303

Claim:
A focal plane array comprising a row and column array of pixel forming elements, a vertical shift register for each column with means connecting the stages of each vertical shift register to receive the information from an associated pixel forming element and timing means connected to each vertical shift register for shifting the vertical shift registers in synchronism, a horizontal shift register for producing serially at an output the information from one row of the array which is held in a last stage of each of the vertical shift register and timing signal means for shifting the horizontal shift register, and means for transferring the information in the last stage of each vertical shift register to a corresponding stage of the horizontal shift register, comprising, a storage means for each vertical shift register for holding the information from the last stage of the vertical shift register, and a gate for connecting each storage means to the associated stage of the horizontal shift register, means providing a timing signal separate from the column shift register timing means for opening each gate during a time for transferring the information from the storage means to the corresponding stage of the horizontal shift register and for closing the gate at other times and thereby isolating the operation and timing of the vertical shift registers from the operation and timing of the horizontal shift register.