Patent ID: 8842061

Claim:
A shifting register, comprising: a first thin film transistor, having the gate and the drain connected together to a signal input terminal, and the source connected to a first node which is a pull-up node; a second thin film transistor, having the gate connected to a reset signal terminal, the drain connected to the first node, and the source connected to a low level signal terminal; a third thin film transistor, having the gate connected to the first node, the drain directly connected to a clock signal port, and the source connected to a signal output terminal; a fourth thin film transistor, having the gate connected to the reset signal terminal, the drain connected to the signal output terminal, and the source connected to the low level signal terminal; a capacitor, being connected between the first node and the signal output terminal; a pull-down module, being connected among the clock signal port, the first node and the signal output terminal, and further connected to the low level signal terminal, for maintaining the first node and the signal output terminal to be at low level during a nonworking period of the shifting register; wherein the pull-down module comprises: a fifth thin film transistor, having a gate and a drain connected together to the clock signal port, and a source connected to a second node which is a pull-down node; a sixth thin film transistor, having a gate connected to the first node, a drain connected to the second node, and a source connected to the low level signal terminal; a seventh thin film transistor, having a gate connected to the second node, a drain connected to the first node, and a source connected to the low level signal terminal; and an eighth thin film transistor, having a gate connected to the second node, a drain connected to the signal output terminal, and a source connected to the low level signal terminal; and wherein the shifting register further comprises: a ninth thin film transistor, having a gate directly connected to the drain of the third thin film transistor, a drain connected to the second node, and a source connected to the low level signal terminal.