Patent ID: 7833903

Claim:
A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising the steps of: forming a first interlayer insulating film on a semiconductor substrate; stacking on the first interlayer insulating film a refractory metal film on a first wiring metal film having a barrier metal; depositing an antireflection film on the refractory metal film; forming a wiring including the first wiring metal film having the barrier metal, the refractory metal film, and the antireflection film; forming a second interlayer insulating film on the wiring; etching the second interlayer insulating film to form a contact hole that exposes a surface of the antireflection film so that the surface of the antireflection film corresponds to an uppermost layer of the wiring and an etching by-product is produced on a sidewall of the contact hole; removing the etching by-product produced on the sidewall of the contact hole; thereafter removing a portion of the antireflection film located in a bottom portion of the contact hole to expose a surface of the refractory metal film; and depositing a second wiring metal film through the contact hole.