Patent ID: 7629825

Claim:
An integrated circuit having a programmable delay element, wherein the programmable delay element comprises: a plurality of delay components arranged in series, each including: a single delay stage that has only one delay sub-element for which the amount of delay is variable; a first delay tap before the single delay stage and a final delay tap after the single delay stage; and a signal selection circuit having a plurality of inputs, the signal selection circuit having an output selectively coupled with one of the inputs in response to data select inputs, wherein a first input of the signal selection circuit is coupled with the first delay tap and a second input of the signal selection circuit is coupled with the final delay tap; and wherein the output of the signal selection circuit of a component is coupled with the first delay tap of a successive component, wherein a total delay of the programmable delay element is collectively defined by the data select inputs of the signal selection circuits, and wherein an amount of delay for the delay stage of one component is different from an amount of delay for the delay stage of a second component.