Patent ID: 8921975

Claim:
A semiconductor device comprising: a metal interconnect layer including at least two discrete metal conductors; an inter-level dielectric layer positioned adjacent said metal interconnect layer, said inter-level dielectric layer comprising a first layer having a first thickness and at least one other layer having a second thickness; a conductive fuse positioned within said inter-level dielectric layer, said conductive fuse having a first end and a second end, said conductive fuse being directly connected on said first end and said second end to said metal conductors, said conductive fuse further comprising: a first U-shaped vertical via on said first end and a second U-shaped vertical via on said second end, and a thin linear fuse portion extending between said first U-shaped vertical via on said first end and said second U-shaped vertical via on said second end, said thin linear fuse portion being a sacrificial portion of said fuse, each of said first U-shaped vertical via and said second U-shaped vertical via extending from the end directly connected to said metal conductor through said first layer and at least partially into said at least one other layer, and said linear fuse portion being positioned completely within said first layer, and said linear fuse portion directly contacting a lowest portion of said first layer; and a fuse recess formed partially through said inter-level dielectric layer, said fuse recess extending completely through said at least one other layer and into said first layer, said fuse recess being positioned adjacent said linear fuse portion, a thickness of said inter-level dielectric layer between said linear fuse portion and said fuse recess being less than said first thickness.