Patent ID: 8639945

Claim:
A microprocessor, comprising: a storage element, configured to store decryption key data; an instruction set that includes a branch and switch key instruction; and a fetch unit, configured to fetch and decrypt program instructions using a set of values of the decryption key data stored in the storage element; wherein the fetch unit is configured to fetch an instance of the branch and switch key instruction and decrypt it using a first set of values of the decryption key data stored in the storage element; wherein if the instance of the branch and switch key instruction is resolved as taken, the microprocessor is configured to load the storage element with a second set of values of the decryption key data for subsequent use by the fetch unit to decrypt an instruction fetched at a target address specified by the branch and switch key instruction, wherein the second set of values of the decryption key data is different from the first set of values of the decryption key data; wherein if the instance of the branch and switch key instruction is resolved as not taken, the microprocessor is configured to retain the first set of values of the decryption key data in the storage element for subsequent use by the fetch unit to decrypt an instruction sequentially following the branch and switch key instruction; wherein the fetch unit is further configured to generate a decryption key based on the first set of values of the decryption key data stored in the storage element and a portion of a fetch address used to fetch the branch and switch key instruction, prior to decrypting the branch and switch key instruction; Wherein to decrypt the branch and switch key instruction using the first set of values of the decryption key data the fetch unit is configured to decrypt the branch and switch key instruction with the generated decryption key; Wherein the decryption key data stored in the storage element comprises a plurality of master keys; and Wherein to generate the decryption key based on the decryption key data stored in the storage element and a portion of a fetch address, the fetch unit is configured to select at least two of the plurality of master keys based on a first portion of the fetch address and perform an arithmetic and/or logical operation on the selected at least two of the plurality of master keys to generate the decryption key.