Patent ID: 8609998

Claim:
A wiring board comprising: a wiring formation region in which a plurality of wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, the wiring layers are connected to one another through a via formed in each of the insulating layers; and a peripheral region around the wiring formation region, in which a first reinforcing pattern and a second reinforcing pattern are respectively provided on the same levels as the outermost wiring layer and the wiring layer positioned at an inner layer side among the wiring layers and in an intermittent ring-like shape when viewed in a planar view, wherein one exterior surface on a front surface of the wiring board and another exterior surface on a back surface of the wiring board are provided, wherein a semiconductor chip mounting area is provided on the one exterior surface of the wiring formation region, a plurality of first pad portions are provided on the semiconductor chip mounting area, and the another exterior surface is electrically connectible, wherein one of the plurality of first pad portions is defined at a required position of the outermost wiring layer, wherein the plurality of first pad portions and the first reinforcing pattern are buried in the insulating layer positioned outermost on the one exterior surface side, a front surface of each of the plurality of first pad portions and a front surface of the first reinforcing pattern are exposed and flush with a surface of the insulating layer positioned outermost on the one exterior surface side, side and back surfaces of each of the plurality of first pad portions are covered with the insulating layer, and the back surface of each of the plurality of first pad portions is connected to the via of the wiring layer positioned at an inner layer side, wherein side and back surfaces of the first reinforcing pattern and front, side and back surfaces of the second reinforcing pattern are entirely covered with the insulating layer, and wherein an existence portion of the first reinforcing pattern overlaps with a non-existence portion of the second reinforcing pattern and the non-existence portion of the first reinforcing pattern overlaps with the existence portion of the second reinforcing pattern while an end portion of the existence portion of the first reinforcing pattern overlaps with an end portion of the existence portion of the second reinforcing pattern.