Patent ID: 7277340

Claim:
A circuit, realizing a Sense Electronics Endowed (SEE) memory device with Smart Memory Read (SMR) technique, comprising: a Sense Electronics Endowed (SEE) memory device using an SMR-mode read cycle operation for main data storage with internal “Mem Address”, “Mem Read/enable” signals, and internal “Mem Data out” data needed within a memory read cycle, controlled by a “System Clock” signal and having external Address bus and Data I/O bus systems; a Shadow Memory device for intermediate data storage with an internal “Shadow mem Write” signal and internal “Shadow mem Data” data as necessitated during said SMR-mode read cycle operation, also controlled by said “System Clock” signal; and a control logic module for realizing a timing schedule implementing an SMR-mode read cycle operation for said SEE-memory device as an operation with a modified read cycle compared to normal memory read cycles characterized by a ‘to a fraction of a normal read/enable impulse duration shortened’ SMR-mode memory read/enable impulse duration for said “Mem Read/enable” signal of said SEE-memory device, and by its equally important “Mem Read/enable” signal position as ‘suitable location for proper read timing’.