Patent ID: 8797820

Claim:
A non-volatile memory (NVM) cell, comprising: an antifuse element configured in series between a word control line WP, the source-drain of a bit-select transistor, and a column bit line BL, wherein the bit select transistor is connected by its gate to a word select control line WS, and wherein the antifuse element will open in its unprogrammed state and present less than 10M ohms in its programmed state; a sensing node at a junction between the antifuse element and the bit select transistor; a sensing transistor connected by its gate to the sensing node and by its source and drain between the column bit line BL and a column bit read line BR; wherein, any current passing through the antifuse element will appear as a voltage drop at the sensing node, and such voltage at the sensing node can act to control the sensing transistor; wherein, the antifuse and sensing transistor are configured such that less than 5-μA of current is needing for permanent programming; and wherein the following voltage table is representative of the operation in a 0.13 μm process technology, and “SW/SB” notation indicates a circuit A located at an intersection of selected word (SW) lines and selected bit (SB) lines: Cell V (WP) V (WS) V (BL) V (BR) Programming A SW/SB 5.5 V 2.5 V 0 V 0 V B SW/UB 5.5 V 2.5 V 2.5 V 2.5 V C UW/SB 2.5 V 0 V 0 V 0 V D UW/UB 2.5 V 0 V 2.5 V 2.5 V Read A SW/SB 1.0 V 0 V 0 V V sensing + B SW/UB 1.0 V 0 V 0 V 0 V C UW/SB 0 V 0 V 0 V V sensing + D UW/UB 0 V 0 V 0 V 0 V sensing line.