Patent ID: 7991947

Claim:
A multi-priority encoder comprising: a plurality of interconnected, single-priority encoders arranged in descending priority order, wherein only one of the plurality of single-priority encoders is a highest-priority single-priority encoder having circuitry for receiving match line input signals, each single-priority encoder further comprising: multiple single-priority indicators arranged in descending priority order; circuitry for detecting multiple simultaneous active match line input signals received by single-priority indicators within the highest-priority single-priority encoder; circuitry for blocking lower priority level single-priority encoders from outputting a first match output signal corresponding to a first match line input signal, if a higher level single-priority encoder outputs the first match output signal corresponding to the same first match line input signal; and circuitry for allowing a lower priority level single-priority encoder to output a second match output signal corresponding to a second match line input simultaneously with the first match output signal corresponding to the first match line input such that the multi-priority encoder outputs both first and second match output signals, wherein each match output signal indicates a corresponding match line input signal having a determined priority.