Patent ID: 8243100

Claim:
A method comprising: executing a single instruction at a processor, wherein executing the single instruction includes: receiving first data and second data, wherein the first data comprises a first coordinate and a second coordinate, and wherein the second data comprises a third coordinate and a fourth coordinate; receiving a first control value and a second control value, wherein the first control value indicates a first rotation value selected from a set of ninety degree multiples and the second control value indicates a second rotation value selected from the set of ninety degree multiples; and determining first output data and second output data during a single execution cycle at a single execution unit of the processor, wherein the single execution unit includes vector adder circuitry configurable to perform an add operation, wherein determining the first output data and the second output data includes the vector adder circuitry performing a negation operation, and wherein the first output data corresponds to the first data rotated by the first control value and the second output data corresponds to the second data rotated by the second control value.