Patent ID: 7833860

Claim:
A method of forming and programming an antifuse structure, comprising: forming a recess extending into semiconductor material of a semiconductor substrate, the recess having a curvilinear bottom periphery; the semiconductor substrate having an uppermost surface, and after the recess is formed a first region of the uppermost surface being within the recess, and a second region of the uppermost surface being outside of the recess and elevationally above the first region of the uppermost surface; the recess having a width, and having opposing lateral edges on either side of said width; forming a first dielectric layer within the recess along the curvilinear bottom periphery, the first dielectric layer extending across an entirety of the first region of the uppermost surface of the semiconductor substrate, and across a portion of the second region of the uppermost surface of the semiconductor substrate; the first dielectric layer having outer peripheral edges over the second region of the uppermost surface of the semiconductor substrate; forming a second dielectric layer over the first dielectric layer, the second dielectric layer extending across an entirety of the first region of the uppermost surface of the semiconductor substrate, and across more of the second region of the uppermost surface of the semiconductor substrate than the first dielectric layer so that the second dielectric layer extends laterally outward of the first dielectric layer; forming electrically conductive gate material over the first and second dielectric layers and within the recess to fill the recess; the electrically conductive gate material being patterned to form a gate having a pair of opposing sidewalls; said sidewalls being over the second region of said uppermost surface; forming sidewall spacers along the gate sidewalls, the sidewall spacers covering the outer peripheral edges of the first dielectric layer; forming heavily doped source/drain regions extending into the semiconductor material of the semiconductor substrate; said heavily doped source/drain regions being laterally outward of the sidewall spacers; forming lightly doped source/drain regions under the sidewall spacers; and generating a voltage differential between the gate and one of the source/drain regions; the voltage differential creating snap-back breakdown to form a rupture through the dielectric layer, and the voltage differential being sufficient to form an electrically conductive filament within the rupture, the filament ohmically connecting the gate to one of the lightly doped source/drain regions.