Patent ID: 7778088

Claim:
An erase method for a nonvolatile memory device having an array of memory cells configured to store information corresponding to at least one bit, the method comprising: initiating an erase operation for a group of bits in the array of memory cells, the erase operation comprising a preliminary erase operation for a first portion of the group of bits utilizing a default gate bias voltage; obtaining a count corresponding to a number of erase pulses utilized to erase the first portion of the group of bits during the erase operation, wherein obtaining the count is associated with the preliminary erase operation; determining an adjusted gate bias voltage in response to the count; and erasing a second portion of the group of bits utilizing the adjusted gate bias voltage during the erase operation, wherein determining the adjusted gate bias voltage comprises increasing the absolute value of a baseline negative gate bias voltage proportionately to the count to obtain the adjusted gate bias voltage.