Patent ID: 7155646

Claim:
A system comprising: A. a mode select input; B. a clock input; C. a data input; D. a data output; E. a first enable input; F. a second enable input; G. a test access port including: i. a tap controller state machine connected to the mode select input, the clock input and the first enable input, and providing tap control outputs; ii. data registers, a first multiplexer and a second multiplexer connected in series between the data input and the data output and connected to the tap control outputs; and iii. an instruction register and the second multiplexer connected in series between the data input and the data output, and connected to the tap control outputs; and H. a test controller including: i. a test control state machine connected to the mode select input, the clock input, and the second enable input, and having control inputs and first control outputs; and ii. an instruction register and a multiplexer connected in series between the data input and the data output, and connected to the first control outputs, the instruction register having second control outputs connected to the control inputs.