Patent ID: 8331227

Claim:
A computer-implemented method for determining link failure in a network, comprising: providing a plurality of possible paths between each pair of multi-path load balancing (MPLB) components of a plurality of MPLB components within a Layer 2 network by establishing a plurality of overlapping loop-free topologies within the Layer 2 network in which each of the plurality of MPLB components is reachable by any other of the plurality of MPLB components via each of the plurality of overlapping loop-free topologies; sending, by a first MPLB component of the plurality of MPLB components, a plurality of latency request packets to a second MPLB component of the plurality of MPLB components via a particular path in the network; receiving, by the first MPLB component, a plurality of latency response packets sent by the second MPLB component in response to the plurality of latency request packets; determining, based at least partially upon timestamp information contained in the plurality of latency response packets, an estimated latency between the first MPLB component and the second MPLB component; deriving a link failure timeout period based upon the estimated latency; sending an additional latency request packet from the first MPLB component to the second MPLB component via the particular path; determining that an additional latency response packet, which should be sent by the second MPLB component in response to the additional latency request packet, has not been received by the first MPLB component prior to expiration of the link failure timeout period; in response to such a determination, concluding that a link failure has occurred; and wherein the first MPLB component and the second MPLB component are realized using one or more of hardware logic components, one or more Application Specific Integrated Circuit (ASIC) and one or more processors executing a set of instructions.