Patent ID: 8281081

Claim:
An apparatus comprising: a plurality of processing nodes, each node including: one or more central processing units (CPUs); a random access memory device including: a local memory address space, accessible to the one or more CPUs of only the node that includes the random access memory; and a global memory address space, accessible to CPUs of all the nodes; a parallel link input/output port configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of other nodes; and a protocol engine coupled to the parallel link input/output port, wherein the protocol engine is configured to instruct the parallel link input/output port to prepend a routing header onto a medium access control (MAC) frame, the routing header including a destination address and a command type, the command type including an operation on the global memory address space of either a node which sent the frame or a node which received the frame.