Patent ID: 7906776

Claim:
A voltage controlled oscillator circuit, comprising: an output terminal for outputting an oscillating signal of a radio frequency proportional to a bias voltage; a tuned inductor capacitor (LC) circuit coupled to the output terminal; a first FET having a drain coupled to the tuned LC circuit, a gate coupled to a positive supply voltage, and a source coupled to a common source node; a second FET having a gate coupled to the drain of the first FET and the tuned LC circuit, a drain coupled to a positive supply voltage and a source coupled to the common source node; and a third FET and a fourth FET coupled to provide a bias voltage at the common source node, responsive to the bias voltage; wherein at least one of the first, second, third and fourth FETs comprises: a semiconductor substrate including at least one planarized layer; a channel region including at least one strained channel layer disposed on the at least one planarized layer thereby defining an interface therebetween, the at least one strained channel layer having a distal zone away from the interface wherein the substrate, the interface and the at least one strained channel layer are characterized at least in part by an impurity gradient having a value substantially equal to zero in the distal zone; and a gate electrode overlying a portion of the channel region.