Patent ID: 8193844

Claim:
A semiconductor device comprising: an internal source clock generation unit configured to divide a frequency of an external source clock by a certain ratio, and to output first and second internal source clocks corresponding to first and second edges of the external source clock; a clock phase correction unit configured to detect a duration in which the first and second internal source clocks have a same logic level, to correct a phase difference between the first and second internal source clocks according to a detection result, and to output first and second phase-corrected internal source clocks; a clock delay unit configured to delay the first and second phase-corrected internal source clocks by a delay amount corresponding to a phase difference between the first and second phase-corrected internal source clocks and a feedback clock, and to generate first and second delay locked loop (DLL) clocks; and a clock output unit configured to mix phases of the first and second DLL clocks to output a final DLL clock, and to output the feedback clock to reflect an actual delay condition of an external source clock path in the first or second DLL clock.