Patent ID: 7469312

Claim:
A method for bridging between a Giga-Processor Ultralite (GPUL) bus and an interface bus in a computer processor system, the method comprising the steps of: translating GPUL to interface bus read commands initiated on the GPUL bus to the interface bus; translating GPUL to interface bus write commands initiated on the GPUL bus to the interface bus; translating GPUL to interface bus read commands with modified intervention initiated on the interface bus to the GPUL bus; and translating interface bus to GPUL bus commands only transactions from the interface bus to the GPUL bus; wherein the step of translating GPUL to interface bus read commands initiated on the GPUL bus comprises the steps of: receiving from the GPUL bus a command and tag; performing a retry by sending a retry request on the GPUL bus with a command handshake signal if credit or space is not available; translating the command to an interface bus command and passing the interface bus command to the interface bus and performing the following steps if credit and space is available; placing the command in a FIFO in a flow control unit so the command information can be passed to data buffers upon completion of the transaction; waiting for a reflected command on the interface bus; converting the reflected command to an interface reflected command; passing the interface bus reflected command to the interface bus; processing a snoop phase; and processing a data phase.