Patent ID: 8338952

Claim:
An interconnect structure comprising distinct structural elements with different patterns for interconnecting a semiconductor substrate, wherein the structural elements comprise: an interlevel layer; conducting metal features comprised of conducting metal lines and conducting metal vias, wherein the conducting metal lines are present in the interlevel layer that traverse parallel to the substrate, and conducting metal vias are present through the interlevel layer that traverse orthogonal to the substrate, wherein the conducting metal features have a stepped width within a single dielectric material layer of the interlevel layer; and mechanical supports having a greater elastic modulus than the interlevel layer are present through the interlevel layer, wherein the mechanical supports are separated from the conducting metal lines and the conducting metal vias features by a continuous portion of the interlevel layer, wherein the mechanical supports and the conducting metal vias are formed using a same photoresist mask to substantially eliminate misalignment between the mechanical supports and the conducting metal vias.