Patent ID: 7199634

Claim:
An integrated circuit device, comprising: a duty cycle correction circuit configured to generate a complementary pair of output clock signals having substantially uniform duty cycles in response to a complementary pair of input clock signals having non-uniform duty cycles and a standby control signal that synchronizes timing of power-saving duty cycle update operations within said duty cycle correction circuit, said duty cycle correction circuit comprising: a duty cycle correction amplifier configured to generate the complementary pair of output clock signals in response to the complementary pair of input clock signals; a duty cycle detector configured to generate a complementary pair of pump output signals in response to the complementary pair of output clock signals; a comparator configured to generate a comparator output signal in response to the complementary pair of pump output signals; a counter configured to generate a digital output signal in response to the comparator output signal and the standby control signal; and a digital-to-analog converter configured to generate a complementary pair of analog output signals in response to the digital output signal.