Patent ID: 7320063

Claim:
A processor, comprising: a plurality of functional units, each configured to retrieve operations for processing from an operation storage, wherein each of said plurality of functional units is configured to process retrieved operations independently of each other one of said plurality of functional units; and instruction fetch logic configured to issue instructions for execution by the processor, wherein a subset of said instructions are executable to store operations for processing by said functional units into said operation storage, and wherein a given one of said subset of said instructions is executable on different occasions to store different types of said operations into said operation storage; wherein said instructions are defined within a programmer-visible instruction set architecture (ISA), and wherein said operations are not defined within said ISA; wherein said functional units are configured to retrieve and process said operations from said operation storage autonomously with respect to said instruction fetch logic and said subset of instructions; and wherein said operations stored by said subset of said instructions include synchronization operations configured to coordinate processing of other ones of said operations by said plurality of functional units.