Patent ID: 7979757

Claim:
A memory device system, comprising: a plurality of stacked memory device die connected to each other through a plurality of conductors, each of the memory device die containing a plurality of memory cells having locations corresponding to respective memory addresses, the memory cells of the memory device die configured for access according to a plurality of vaults; a logic circuit die on which the memory device die are stacked, the logic circuit die being coupled to the memory device die through a plurality of conductors, the logic circuit die configured to write data to and read data from the memory device die, the logic circuit die including: a plurality of link interfaces configured to receive serial data and deserialize the data to obtain parallel data; a plurality of downstream targets, each coupled to a respective one of the plurality of link interfaces and configured to receive the parallel data from the respective link interface, decode command and address portions of the received parallel data; a switch coupled to the plurality of downstream targets, the switch configured to receive the decoded command and address portions of the received parallel data and couple the decoded command and address portions of the received parallel data to at least one of the plurality of vertical vaults corresponding to the received decoded address portion; and a packet builder and broadcaster coupled to the plurality of link interfaces, the packet builder and broadcaster including a first input port coupled to receive command signals from a tester on a first interface, and a second input port coupled to receive address signals from the tester on a second interface, the packet builder and broadcaster configured to reformat the command and address signals and to sequentially couple the reformatted command and address signals to at least one of the plurality of link interfaces.