Patent ID: 7958439

Claim:
An address signal comparison system for a non-volatile memory device having memory cells arranged in blocks each of which is associated with a respective block address, the system comprising: a storage device containing a record of the block address and a block size value for each block of memory cells that is non-functional, each block address contained in the storage device being associated with a respective index value, the index values being assigned to the block addresses in order from a lowest index value associated with a lowest block address to a highest index value associated with a highest block address; a counter coupled to the storage device and being configured to provide the index values to the storage device responsive to being incremented; a first comparator coupled to the counter and operable to receive the index values, the first comparator further operable to generate a first comparison signal responsive to determining that a first index value is an initial index value; a first multiplexer having a first input coupled to receive an input block address and a second input coupled to receive an output block address, the first multiplexer being configured to output the input block address responsive to the first comparison signal and to otherwise output the output block address; an adder coupled to the storage device and the output of the first multiplexer, the adder being configured to generate a sum address corresponding to the sum of the block address at the output of the first multiplexer and a block size value received from the storage device; a second comparator coupled to receive the block address at the output of the first multiplexer and the block address from the storage device and being operable to generate a second comparison signal responsive to determining that the block address at the output of the first multiplexer is less than a block address received from the storage device; and a second multiplexer having a first input coupled to receive the sum address from the adder and a second input coupled to the output of the first multiplexer, the second multiplexer being configured to output as the output block address the block address at the output of the first multiplexer responsive to the second comparison signal and to otherwise output the sum address.