Patent ID: 7867843

Claim:
A process comprising: forming a spacer first mask above a substrate; etching through an antireflective coating (ARC) layer and a carbon layer using the spacer first mask to form a spacer second mask that includes a portion of the ARC layer disposed upon a portion of the carbon layer; etching through a nitride layer using the spacer second mask to form a first pillar that includes a portion of the carbon layer disposed upon the nitride layer; forming a spacer third mask that includes the first pillar disposed upon a polycrystalline silicon layer; forming a second pillar using the spacer third mask, wherein the second pillar includes a portion of the nitride layer disposed upon a portion of a polycrystalline silicon layer, a portion of the polycrystalline silicon being disposed upon a gate oxide layer, the gate oxide layer disposed upon a semiconductive substrate, and wherein the semiconductive substrate includes a trench; and forming a floating gate by removing the portion of the nitride layer and filling a pinnacle polysilicon to contact a portion of the polycrystalline silicon layer.