Patent ID: 7312487

Claim:
An integrated circuit (IC) chip comprising: a substrate layer; a first insulating layer on said substrate layer; a first semiconductor layer on said first insulating layer, transistors being formed from said first semiconductor layer and connected together into circuit elements in a circuit layer; a second insulating layer attached to said first semiconductor layer; a second semiconductor layer on said second insulating layer, transistors being formed from said second semiconductor layer, and connected together into an array of circuit elements in a circuit layer, wherein a majority of IC chip elements are located on said first semiconductor layer; and a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on and extending from one of said circuit elements on said first semiconductor layer and said second semiconductor layer, ones of said circuit elements on said first semiconductor layer being connected through said plurality of interlayer connection channels to corresponding ones of said circuit elements on said second semiconductor layer, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said IC; wherein said circuit elements on said SOI CMOS circuit layer include combinational logic and said array of circuit elements is a CMOS driver grid, selected drivers of said CMOS driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer.