Patent ID: 8677037

Claim:
A memory apparatus comprising: a base printed circuit board (PCB) having an edge connector for plugging into a host server system to receive host power; a card level power source mounted to the base PCB to provide card level power during a power failure; one or more memory controllers coupled to the card level power source, each of the one or more memory controllers having a plurality of memory channels; a plurality of non-volatile memory devices (NVMDs) coupled to the card level power source and organized to couple to the plurality of memory channels of the one or more memory controllers; wherein each of the one or more memory controllers to provide queuing and scheduling of memory operations on a channel for each NVMD in the channel, wherein each of the one or more memory controllers includes one or more channel controllers each having a scheduler to control the queuing and scheduling of memory operations to the NVMDs in the channel; wherein in response to a power failure to the host server system or the host power to the edge connector, the one or more memory controllers to receive card level power and change the scheduling of memory operations to the plurality of NVMDs in the plurality of memory channels.