Patent ID: 7420860

Claim:
A semiconductor memory comprising: a plurality of real memory cells arranged in a matrix; a plurality of real signal lines connected respectively to a plurality of real memory cell rows each of which is formed of the real memory cells arranged in one direction; a first dummy signal line wired along said real signal lines on an outside of a region in which said real memory cells are arranged; first dummy memory cells connected to said first dummy signal line, being adjacent to said real memory cells, and to which a predetermined logical level is writable during a test mode; and a voltage setting circuit setting said first dummy signal line to a first voltage to keep said first dummy memory cells in a non-written state during a normal operation mode, and setting said first dummy signal line to a second voltage to write test data onto said first dummy memory cells during the test mode, wherein: said real memory cells and said first dummy memory cells each include a memory element and a transfer switch connected to the memory element; said real signal lines are real bit lines connected to the transfer switches of said real memory cells; said first dummy signal line is a dummy bit line connected to the transfer switches of said first dummy memory cells; said first voltage is a precharge voltage that is a reset voltage for said real bit lines and said dummy bit line; and said second voltage is a voltage for writing a high logical level onto said real memory cells and said first dummy memory cells.