Patent ID: 6934811

Claim:
A microprocessor comprising: an execution engine for generating a memory request signal and a sequential fetch signal, wherein: (i) the memory request signal requests data fetch from a main memory and includes information related to position in the main memory of data requested according to the memory request signal; and (ii) the sequential fetch signal is generated when the requested data is stored at a position of the main memory adjacent to data used immediately previously by the execution engine; and a cache including a cache controller having a state indication section for indicating the state of the cache controller, a data memory for storing data of the main memory by a cache line unit including plural words, a tag memory for storing a tag corresponding to position information related to the main memory of data stored in the data memory, a register for temporarily storing data transferred from the main memory in a cache miss processing cycle, and a data path for interconnecting the data memory and the execution engine, wherein when the execution engine generates the sequential fetch signal and the requested data is stored in the same cache line of the data memory as the data used immediately previously by the execution engine, the data and tag memories enter a low-power stand-by mode, and the requested data is transferred from the register to the execution engine, and wherein the cache controller generates a first signal and a second signal, the first signal generated in response to the state indication section and a chip selection signal, and the second signal generated in response to the state indication section and a clock signal, and the data and tag memories each have a chip selection input and a clock input, wherein the data and tag memories enter the low-power stand-by mode in response to the first signal and second signal output to the chip selection input and clock input, respectively.