Patent ID: 7192820

Claim:
A method for reducing non-uniformity or topography variation between a cell array area and a peripheral circuitry area in a process for manufacturing semiconductor integrated non-volatile memory devices comprises: providing an intermediate stack of multiple layers during manufacturing of gates structures in both the array and circuitry areas; defining the active areas of the memory cells array and of the circuitry on a semiconductor substrate; depositing a thin oxide layer over said active areas; defining the floating gate structures of the memory cells in the array area using a first conductive layer on which dielectric films have been deposited; providing one or more oxide layers, specifically active gate oxide layers, over the active areas of the circuitry; depositing a second conductive layer over said dielectric films and said oxide layers; and providing a thin stack comprising at least a thin dielectric layer and a third conductive layer over said second conductive layer before the step of defining the control gate structures in the array and the single gates in the circuitry, wherein the thickness of the third conductive layer is predetermined so that the sum of the thicknesses of the second polysilicon layer and the third polysilicon layer equals the thickness required for the gate structures of the transistors in the circuitry.