Patent ID: 8200946

Claim:
A data processing system, comprising: a processor; and a memory coupled to the processor, wherein the processor comprises an issue unit, and wherein the issue unit comprises: livelock detection control logic; slow mode control logic coupled to the livelock detection logic; and an issue and dispatch pipeline coupled to the livelock detection control logic and slow mode control logic, wherein: the livelock detection control logic comprises logic configured to detect a livelock condition in the issue and dispatch pipeline, the slow mode control logic comprises logic configured to gradually stall movement of instructions through the issue and dispatch pipeline by an increasing number of processing cycles while the livelock condition continues to be detected by the livelock detection control logic, the slow mode control logic comprises logic configured to return the issue unit to a full speed mode of operation in response to detecting that the livelock condition has been broken, the slow mode control logic comprises a first counter for counting a number of sequential times the livelock condition is detected by the livelock detection logic, and wherein, in response to the first counter having a value equal to a predetermined serious livelock condition threshold value, the slow mode control logic causes the issue and dispatch pipeline to be placed into a serial single step mode of operation that allows only one instruction to issue from the issue and dispatch pipeline with no other instructions being allowed to issue from the issue and dispatch pipeline until execution of an instruction is successfully completed.