Patent ID: 7800136

Claim:
A semiconductor integrated circuit comprising: a semiconductor substrate formed with a plurality of transistors; a first wiring layer formed on said semiconductor substrate; a second wiring layer formed on said first wiring layer; a third wiring layer formed on said second wiring layer; first M 0 wires formed in said first wiring layer for connecting a number of said plurality of transistors to have a specific logic function; a power supplying wire formed in a different wiring layer to said first wiring layer for supplying power to said transistors; a plurality of function areas in which at least one of said first M 0 wire, said power supplying wire, and a number of said plurality of transistors connected via said first M 0 wire as an internal wire are arranged; a second M 0 wire formed in said first wiring layer for connecting a plurality of said function areas; a basic cell having a predetermined height and one of a plurality of said function areas; and, a macro cell including a plurality of function areas which are connected by said second M 0 wire, the height of said macro cell being an integral multiplication of the height of said basic cell.