Patent ID: 7185177

Claim:
A processor system comprising: a code splitting tool for transforming a program by generating an instruction addressing control program as a sequence of instruction fetch (IF) instructions and at least one set of non-control instructions; an instruction fetch (IF) memory storing the sequence of IF instructions; a programmable instruction fetch mechanism that is programmed by the IF instructions to fetch and execute IF instructions in a sequencing order, wherein the sequencing order is controlled by information contained in each of the IF instructions; at least one non-control instruction memory (IMemory) storing the at least one set of non-control instructions, whereby an IF instruction is formatted as a first IF instruction type to identify at least one address of the at least one IMemory and said programmable instruction fetch mechanism operates to fetch IF instructions from said IF memory and execute each fetched first IF instruction type to generate at least one IMemory instruction address to select at least one non-control instruction to be fetched from the at least one IMemory for execution; a second IF instruction type for parallel multiple-issue instructions; and an additional non-control instruction memory (IMemory) comprising a second set of non-control instructions, said programmable instruction fetch mechanism operating to fetch IF instructions from said IF memory and when executing the second IF instruction type generating at least two IMemory instruction addresses to select non-control instructions to be fetched from the at least two IMemories for execution in parallel.