Patent ID: 7936185

Claim:
A clockless return to state domino logic gate which is responsive to a plurality of input logic signals in which each input logic signal switches between first and second logic states, wherein said clockless return to state domino logic gate comprises: a domino circuit, comprising: a plurality of nodes which switch between the first and second logic states, said plurality of nodes including a preset node, an output node, an enable node, and a first reset node; a first inverter having an input coupled to said preset node and an output coupled to said output node; a first device of a first conductivity type having a control terminal coupled to said output node, having a first current terminal coupled to a first source voltage node associated with the first logic state, and having a second current terminal coupled to said preset node; a second inverter having an input coupled to said output node and an output coupled to said enable node; a first device of a second conductivity type having a first current terminal coupled to a second source voltage node associated with the second logic state, having a control terminal coupled to said enable node, and having a second current terminal coupled to said first reset node; a third inverter having an input coupled to said first reset node and having an output; and a second device of said first conductivity type having a first current terminal coupled to said first source voltage node, having a control terminal coupled to said output of said third inverter, and having a second current terminal coupled to said preset node; and an input circuit coupled said preset node, said reset node and said enable node and is configured to be responsive to the plurality of input logic signals, wherein said input circuit pulls said preset node to the second logic state when the plurality of input logic signals are in any one of at least one evaluation state, and wherein said input circuit temporarily pulls said first reset node to the first logic state when the plurality of input logic signals transitions out of any one of said at least one evaluation state.