Patent ID: 7509606

Claim:
A computer-implemented method of optimizing power consumption in a Very Large Scale Integration (VLSI) design, the method comprising: performing a power analysis on a set of components within the design, the performing comprising: generating a first power output signal during a first clock cycle of a simulation of the set of components, the first power output signal representing a first power output value; generating a second power output signal during a second clock cycle of the simulation of the set of components, the second power output signal representing a second power output value; and comparing the first power output signal to the second power output signal; determining, based on the power analysis, whether the set of components is a candidate for clock gating, wherein the determining comprises evaluating the comparison of the first power output signal and the second power output signal, wherein a result of the evaluation consists of one of a difference, an equality, and a substantial equality; and responsive to the result of the evaluation being an equality, marking the set of components as a candidate for clock gating; responsive to determining that the set of components is a candidate for clock gating, obtaining clock gating data from a simulation of the set of components, the clock gating data including statistics on at least one of a percentage of clock cycles that the set of components is potentially clock gated, a percentage of clock cycles that the set of components is clock gated, a percentage of clock cycles that a register in the set of components is clock gated, a percentage of clock cycles that a percentage of bits of a register is clock gated, and a percentage of clock cycles that a latch in a set of components is clock gated; and optimizing the VLSI design based on the clock gating data, wherein the optimizing comprises modifying the VLSI design.