Patent ID: 8669154

Claim:
A method of forming a complementary metal oxide semiconductor (CMOS) device, the method comprising: forming a hard mask over first and second regions of a workpiece, wherein the first region is n-type and the second region is p-type; removing the hard mask from over the second region but not from over the first region, thereby exposing the second region of the workpiece; depositing a first gate dielectric material on the hard mask over the first region, and on the second region of the workpiece; depositing a first gate material on the first gate dielectric material; removing, in a single step, the hard mask, the first gate dielectric material and the first gate material from over the first region but not from over the second region, thereby exposing the first region of the workpiece; depositing a second gate dielectric material on the first region of the workpiece, and on the gate material over the second region; depositing a second gate material on the second gate dielectric material; removing the second gate dielectric material and the second gate material from over the second region but not from over the first region; patterning the first gate material and the first gate dielectric material to form a negative channel metal oxide semiconductor (NMOS) gate/gate dielectric stack over the second region; and patterning the second gate material and the second gate dielectric material to form a positive channel metal oxide semiconductor (PMOS) gate/gate dielectric stack over the first region.