Patent ID: 6938061

Claim:
A parallel counter comprising: at least five inputs for receiving a plurality of binary inputs, wherein m represents the number of high binary inputs; at least three outputs for outputting binary outputs indicating the number of binary ones in the plurality of binary inputs; and a logic circuit connected between the plurality of inputs and the plurality of outputs and for generating at least three of the binary outputs as elementary OR or EXOR symmetric functions of the binary inputs, wherein said elementary OR symmetric function is generated by elementary OR symmetric function logic comprising at least one of: (i) the OR logic combination of the binary inputs and is high if and only if m≧1, (ii) the AND logic combination of sets of the binary inputs and the OR logic combination of the AND logic combinations and is high if and only if m≧k, where k is the size of the sets of binary inputs, each set being unique and the sets covering all possible combinations of binary inputs, or (iii) the AND logic combination of the binary inputs and is high if and only if all said binary inputs are high; and said elementary EXOR symmetric function is generated by elementary EXOR symmetric function logic comprising at least one of: (i) the EXOR logic combination of the binary inputs and is high if and only if m≧1, (ii) the AND logic combination of sets of the binary inputs and the EXOR logic combination of the AND logic combinations and is high if and only if m≧ k and the number of sets of high inputs is an odd number, where k is the size of the sets of binary inputs, each set being unique and the sets covering all possible combinations of binary inputs, or (iii) the AND logic combination of the binary inputs and is high if and only if all said binary inputs are high.