Patent ID: 8349656

Claim:
A manufacturing method of leadframes used for manufacturing semiconductor devices by mounting a plurality of semiconductor elements individually on a plurality of unit leadframes which are arranged in plural rows or a single row in a leadframe material and encapsulating resin thereto, the manufacturing method comprising: providing, with resist films, a first circuit pattern on a front surface of the unit leadframes for forming upper side terminal portions, upper faces of which serve wire bonding portions, and a second circuit pattern on a rear surface of the unit leadframes, forming lower side terminal portions corresponding to the upper side terminal portions; forming a first plating layer and a second plating layer on the front surface and the rear surface of the leadframe material, respectively, after the circuit pattern providing is performed to the leadframe material, and removing the resist films; forming the upper side terminal portions by performing a half-etching treatment onto the front surface of the leadframe, using the first plating layer directly as a resist film without further providing another resist film, wherein a first plating burr removal that excludes ultrasonic wave plating burr removal is conducted at least at an etched area to remove plating burrs generated in an etched area on which the half-etching treatment to form the upper side terminal portions is performed by using the first plating layer directly as the resist film, and a second plating burr removal that includes ultrasonic wave plating burr removal is conducted only at an outer frame area to remove plating burrs generated in the outer frame area on which pilot holes are provided so as to surround the unit leadframes in the leadframe material, to thereby remove plating burrs generated in the upper side terminal portions forming.