Patent ID: 8399315

Claim:
A method for manufacturing a semiconductor structure, comprising: a) forming an epitaxial semiconductor layer on a semiconductor substrate; b) forming a sacrificial gate on the epitaxial semiconductor layer; c) forming a sidewall spacer surrounding the sacrificial gate; d) implanting ions into the epitaxial semiconductor layer using the sacrificial gate as a hard mask, so as to form source/drain regions; e) removing the sacrificial gate to form a gate gap, so as to expose a surface of the epitaxial semiconductor layer, while remaining the sidewall spacer; f) removing the portion of the epitaxial semiconductor layer that is exposed from the gate gap to expose a surface of the semiconductor substrate; g) forming a conformal gate dielectric layer in the gate gap; and h) forming a gate conductor layer in the gate gap, wherein the gate conductor is surrounded by the sidewall spacer, and wherein the sidewall spacer is used with the sacrificial gate for aligning the source/drain regions, is used for removing the sacrificial gate, is used for defining the gate gap, and is used for forming the gate conductor layer.