Patent ID: 7282391

Claim:
A method of fabricating an electronic device, comprising: placing a placement guide over a top surface of a module substrate, a bottom surface of said placement guide facing a top surface of said module substrate, said placement guide having one or more guide openings, said guide openings extending from a top surface of said placement guide to said bottom surface of said placement guide; aligning said placement guide to at least one integrated circuit chip position of one or more integrated circuit chip positions on said module substrate; fixing said aligned placement guide to said module substrate; placing one or more integrated circuit chips in corresponding guide openings of said one or more guide openings, bottom surfaces of said one or more integrated circuit chips facing said top surface of said module substrate, for each of said placed integrated circuit chips, sidewalls of said corresponding placement guide openings constraining electrically conductive bonding structures on bottom surfaces of said placed one or more integrated circuit chips to self-align to corresponding electrically conductive module substrate contact pads on said top surface of said module substrate at corresponding integrated circuit chip positions of said one or more integrated circuit chip positions; bonding said bonding structures to said module substrate contact pads, said bonding structures and said module substrate contact pads in direct physical and electrical contact after said bonding; and after said bonding, removing said placement guide from said module substrate.