Patent ID: 8238160

Claim:
A non-volatile memory device comprising: a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band write operations are sequentially executed during a write operation, wherein the control circuit is further configured to select, during each write operation, a write condition of a next band write operation, wherein each band of the plurality of band write operations is executed according to stored trim information for controlling a write condition, wherein the control circuit comprises: a trim block including a plurality of band registers each band register storing trim information; and a selector configured to select, the band write operation, one of the plurality of band registers of the trim block that store the trim information.