Patent ID: 6977843

Claim:
A semiconductor memory device, comprising: a malfunction prevention device and a nonvolatile memory, the malfunction prevention device comprising: a power source for receiving first and second external voltages and outputting a voltage when the first or second external voltage exceeds a predetermined threshold value; a first divider for receiving the first external voltage to divide it by a first predetermined value and outputting the resultant value; a second divider for receiving the second external voltage to divide it by a second predetermined value and outputting the resultant value; a reference voltage generator for receiving the output of the power source and outputting a reference voltage; a first comparator for comparing the output of the first divider with the reference voltage and setting the semiconductor memory device in a reset state or a read state until the output of the first divider exceeds the reference voltage; and a second comparator for comparing the output of the second divider with the reference voltage and setting the semiconductor memory device in a reset state or a read state until the output of the second divider exceeds the reference voltage, wherein the nonvolatile memory is a memory cell including: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed below the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having a function of retaining charges.