Patent ID: 8741754

Claim:
A method of fabricating a non-volatile memory, comprising: providing a substrate; sequentially forming a tunneling dielectric layer and a first conductive layer on the substrate; forming a plurality of isolation structures in the first conductive layer, the tunneling dielectric layer and the substrate; patterning the first conductive layer to form a plurality of protruding portions; removing a portion of the isolation structures, so that a top surface of each of the isolation structures is disposed between a top surface of the first conductive layer and a surface of the substrate; forming an inter-gate dielectric layer on the substrate; forming a second conductive layer on the inter-gate dielectric layer; and patterning the second conductive layer, the inter-gate dielectric layer and the first conductive layer, so that the second conductive layer forms a plurality of control gates, and the first conductive layer forms a plurality of floating gates respectively having the protruding portions, wherein the control gates cover and surround the protruding portions of the floating gates in all directions respectively, and each of the protruding portions of the floating gates is shaped as a hillock.