Patent ID: 7295623

Claim:
A serializer/deserializer communications system, comprising: a transmitter, the transmitter coupled to receive N parallel bits of data and transmit the N parallel bits of data into K frequency separated channels on a single conducting differential transmission medium, where N and K are integers each greater than one, the N parallel bits being transmitted into the K frequency separated channels of the sterializer/deserializer system synchronously; and a receiver coupled to receive a sum signal that includes signals from each of the K frequency separated channels from the single conducting differential transmission medium and recover the N parallel bits of data, wherein the receiver includes K demodulators, each of the K demodulators receiving signals on one of the K frequency separated channels, at least one of the K demodulators including an analog down converter that converts the signal corresponding to that channel associated with the at least one of the demodulators to a base-band signal in a single step; an analog-to-digital converter coupled to receive the base-band signal from the analog down converter and generate a digitized base-band signal; an equalizer circuit coupled to receive the digitized base-band signal and create an equalized symbol; and a decoder that synchronously retrieves the equalized symbol and retrieves a decoder that receives the equalized symbol and retrieves bits associated with the at least one of the K demodulators associated with the at least one of the K demodulators.