Patent ID: 7295052

Claim:
A power-on control circuit for generating a power-on control signal, comprising: a coupling device coupled to a first voltage supply; a first inverter, coupled between the coupling device and a complementary voltage, having an input node coupled to a second voltage supply with a supply voltage level lower than that of the first voltage supply; and a level shifter, coupled between the first voltage supply and the complementary voltage, having a first input node connected to an output node of the first inverter and a second input node coupled to the second voltage supply, for generating the power-on control signal when the first voltage supply is powered up and the second voltage supply is turned off and for disabling the power-on control signal when the second voltage supply is subsequently powered up, wherein the coupling device eliminates a leakage current path from the first voltage supply to the complementary voltage through the first inverter, wherein the coupling device comprises a PMOS capacitor and an NMOS capacitor serially coupled between the first voltage supply and the complementary voltage.