Patent ID: 8115532

Claim:
A delay chain circuit, comprising: one or more delay cells coupled serially; and a load cell coupled in series with the one or more delay cells, wherein: an input signal to the delay chain circuit passes through a number of the one or more delay cells according to a first control signal of each of the one or more delay cells; a signal delay time in each of the determined number of the one or more delay cells depends on a second control signal input to each of the one or more delay cells; and each of the one or more delay cells and the load cell includes a programmable capacitor, the programmable capacitor engaging a number of unit capacitors determined by the second control signal, wherein the programmable capacitor is coupled between an output pin of the inverter and a ground, wherein the second control signal is a serial control line, wherein each of the one or more delay cells and the load cell comprises an inverter coupled to receive a first input signal and generate a first output signal and a nor-multiplexer coupled to receive the first output signal from the inverter and a second input signal, and to generate a second output signal equal to either the first output signal or the second input signal according to the first control signal.