Patent ID: 6944794

Claim:
A microcontroller comprising: a CPU; a bus controller; an instruction address bus and an instruction code bus, of a first bit number, which connect said CPU and bus controller; and a debug support unit, which is connected to said instruction address bus and instruction code bus, wherein said debug support unit is connected to an external in-circuit emulator via a tool bus whose bit number is smaller than said first bit number and via a bus status signal line which reports on the status of the tool bus; and wherein said debug support unit comprises: a parallel to serial conversion circuit, which performs parallel to serial conversion of an instruction address; a status information generation circuit, which generates a status information signal, which contains branch information and an instruction fetch request, in response to a branch signal and instruction fetch request signal received from said CPU; a status output circuit, which outputs an instruction address output signal to said bus status signal line in response to the status information signal; and a data output circuit, which, in response to said status information signal, when said branch information contains a branch, outputs said converted instruction address in series to said tool bus, and when the branch information contains no branch, outputs a branchless signal in place of said instruction address to said tool bus.