Patent ID: 8059249

Claim:
A flat panel display, comprising: a display panel comprising a display region, a peripheral circuit region, and a plurality of first wires and second wires disposed within the peripheral circuit region; a flexible printed circuit (FPC) board electrically connected to the first wires and the second wires, the first wires and the second wires respectively extending from the underneath of the FPC board to two opposite sides of the display panel; a plurality of first source driving chips disposed in the peripheral circuit region and electrically connected to the FPC board through a part of the first wires, respectively; a plurality of second source driving chips disposed in the peripheral circuit region and electrically connected to the FPC board through the second wires, respectively; a control circuit board electrically connected to the FPC board; and a chip bonding pad disposed under the first source driving chips or the second source driving chips, wherein the chip bonding pad comprises: a first conductive layer; a first dielectric layer covering the first conductive layer and having a plurality of first through holes; a second conductive layer disposed on the first dielectric layer; a second dielectric layer covering the second conductive layer and the first dielectric layer, and having a plurality of second through holes and third through holes arranged alternately, the second through holes corresponding to the first through holes; and a third conductive layer covering the second dielectric layer, the second conductive layer exposed by the third through holes, and the first conductive layer exposed by the first through holes, wherein the first conductive layer is electrically connected to the second conductive layer through the third conductive layer.