Patent ID: 7923363

Claim:
Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area said non-volatile memory device comprising a cell stack including a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first oxide layer; the method comprising: providing the substrate having the first semiconductor layer; depositing the charge trapping layer; depositing the electrically conductive layer; creating a protective layer on sidewalls of at least the charge trapping layer comprising at least the first oxide layer; patterning the cell stack to form at least two non-volatile memory cells; and after at least deposition of the charge trapping layer and creation of the protective layer, creating a shallow trench isolation in between said at least two nonvolatile memory cells; wherein the protective layer is arranged for preventing a local change of a thickness of the first insulating layer at or near the sidewalls during a further processing step.