Patent ID: 8493154

Claim:
Apparatus including a cascode amplifier having a lower and a upper transistor, said lower transistor having a gate coupled to an input signal, said input signal capable of being amplified, said upper transistor having a source coupled directly to a drain of said lower transistor, and said upper transistor having a drain coupled to an amplification power node and to an amplified output signal; said upper transistor having a gate coupled to a bias node, said bias node coupled to a feedback circuit including a plurality of capacitors in series, said bias node also coupled to a voltage divider including a plurality of resistors in series, said feedback circuit and said voltage divider coupled between said amplification power node and a grounding voltage; said lower transistor gate coupled to a bias circuit, said bias circuit being responsive to said input signal, said lower transistor gate being biased in response to said input signal, said bias circuit disposed to rectify a peak voltage of said input signal; wherein said feedback circuit couples signals from the drain of said upper transistor to the gate of said upper transistor; said voltage divider decreases a bias voltage for said upper transistor gate in response to an increase in said input signal; and said bias circuit decreases a bias voltage for said lower transistor gate in response to a decrease in said input signal.