Patent ID: 7033877

Claim:
A process for fabricating an integrated circuit structure comprising: forming a first device region selected from the group consisting of a source region and a drain region of a semiconductor device in a semiconductor substrate; forming a multilayer stack comprising at least three layers of material over the first device region in the semiconductor substrate, wherein the second layer is interposed between the first and the third layers, and wherein the first layer is adjacent the first device region; forming a first and a second window in the at least three layers of material, wherein said first and second windows terminate at the first device region formed in the semiconductor substrate; forming a semiconductor material within the first and the second windows, thereby forming a first and a second semiconductor plug in the at least three layers of material, wherein each of the first and the second semiconductor plugs has a first end and a second end, and wherein the first end of each semiconductor plug is in contact with the first device region, and wherein the first semiconductor plug is of a first conductivity type; forming a second device region selected from the group consisting of a source region and a drain region at the second end of the first semiconductor plug, wherein one of the first and second device regions is a source region and the other is a drain region; forming a third device region selected from the group consisting of a source region and a drain region at the second end of the second semiconductor plug, wherein one of the first and the third device regions is a source region and the other is a drain region; removing the second layer, thereby exposing a portion of the first and the second semiconductor plugs; forming a layer of dielectric material on the exposed portion of the first semiconductor plug; forming a region of a second conductivity type surrounding the first conductivity type region of the second semiconductor plug; and forming a gate electrode having a first region in contact with the layer of dielectric material and having a second region in contact with the second conductivity type region of the second semiconductor plug.