Patent ID: 7596033

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a plurality of word lines, arranged corresponding to the memory cell rows, each connected to the memory cells on a corresponding row; subdecode circuitry including subdecode elements arranged corresponding to the respective word lines, for setting voltages of the word lines in accordance with a set of source signals and a set of gate signals; block decode circuitry for producing the source signals in accordance with an address signal; and gate decode circuitry for producing the gate signals in accordance with an address signal, and each subdecode element including first and second transistor of a common conductivity type each having a source and a gate, the gates of the first and second transistors being supplied with first and second gate signals, respectively, from said gate decode circuitry, the sources of said first and second transistors being supplied with first and second source signal, respectively, from the block decode circuitry, and drains of said first and second transistors being coupled commonly to a corresponding word line, and the subdecode elements being arranged such that contacts to the gates are aligned on a line, contacts to the sources are arranged linearly and adjacent subdecode elements are arranged so as for their second transistors to share a region of the respective sources.