Patent ID: 8111756

Claim:
A method using a chip for reducing computational complexity of video compression standard, at least comprising: providing an intra 4×4 macroblock search algorithm with a luma prediction mode by the chip, and the intra 4×4 macroblock search algorithm includes a condition-correlation search mode having a first upper block, a first left block, a half-full search mode, and a context-correlation search mode, and the intra 4×4 macroblock search algorithm has multiple prediction modes including a mode 0 , a mode 1 , a mode 2 , a mode 3 , a mode 4 , a mode 5 , a mode 6 , a mode 7 and a mode 8 ; using the intra 4×4 macroblock search algorithm to determine a pre-determined prediction mode for computation based on the first upper block and the first left block by the chip; providing an intra 16×16 macroblock search algorithm with a luma prediction mode, and using the intra 16×16 macroblock search algorithm and the intra 4×4 macroblock search algorithm to accelerate the luma prediction modes of the intra 4×4 macroblock and the intra 16×16 macroblock by the chip; providing a chroma macroblock, including a U macroblock and a V macroblock by the chip; and using a chroma search algorithm to accelerate a plurality of chroma prediction modes of the U macroblock and the V macroblock by the chip; wherein the condition-correlation search mode includes a plurality of search conditions and comprises: performing only the mode 2 (DC) when the first upper block and the first left block are both non-available by the chip; performing the mode 1 , the mode 2 and the mode 8 when the first upper block is non-available and the first left block is available by the chip; performing the mode 0 , the mode 2 , the mode 3 and the mode 7 when only the first upper block is available and the first left block is non-available by the chip; and using the half-full search mode and the context-correlation search mode when the first upper block and the first left block are both available by the chip.