Patent ID: 6936909

Claim:
An antifuse circuit comprising: an antifuse comprising a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal in an antifuse circuit; a high-voltage transistor comprising a first terminal coupled to the second terminal of the antifuse and a gate terminal to control the high-voltage transistor; and a gate bias circuit coupled between the gate terminal of the high-voltage transistor, the first terminal of the antifuse, and a supply voltage to couple the gate terminal of the high-voltage transistor to an intermediate voltage between the supply voltage and the elevated voltage on the first terminal of the antifuse to protect the high-voltage transistor, wherein the gate bias circuit further comprises: a first adjustable resistor and a diode-connected transistor coupled in series between a common bus line and the gate terminal of the high-voltage transistor; and a second adjustable resistor coupled between the gate terminal of the high-voltage transistor and the supply voltage.