Patent ID: 7534696

Claim:
A method for forming a multilayer interconnect structure including interconnected conductive wiring and vias spaced apart by a combination of solid and gaseous dielectrics, said method comprising: (a) providing an initial structure comprising a patterned via-level dielectric including one or more permanent dielectric layers, said patterned via-level dielectric disposed on a first planar “line level” having conductive features embedded in a sacrificial place holder dielectric, and patterned through its entire thickness with cavities for vias and perforations for subsequent transport of said sacrificial place holder dielectric, wherein patterning of the vias and perforations comprises a single masking step; (b) forming a patterned next planar line-level layer of sacrificial place holder dielectric on said patterned via level dielectric, said next line-level dielectric is patterned through its entire thickness with cavities for lines; (c) lining said via and line cavities with one or more layers of conductive adhesion/barrier materials and filling said via and line cavities with a low resistivity conductive material to form a planar structure; (d) forming a dielectric bridge layer having perforations therethrough over said planar structure; and (e) forming air gaps by at least partially extracting said sacrificial place holder dielectric through said perforations, wherein the patterned via level dielectric including the one or more permanent dielectric layers having at least a portion present underlying the line cavities adjacent the vias, and sealing said perforations in said bridge layer with a pinch off dielectric material after said extracting said sacrificial place holder dielectric through said perforations.