Patent ID: 8099544

Claim:
An information processing apparatus comprising: an information processing apparatus main body; and a nonvolatile semiconductor memory drive which is accommodated in the information processing apparatus main body, the nonvolatile semiconductor memory drive including a nonvolatile semiconductor memory having a memory area including a plurality of blocks, and a control module, the control module having a first erase mode in which an address management table, which is indicative of a correspondency between logical block addresses and physical addresses of the nonvolatile semiconductor memory, is initialized to indicate that the memory area has no user data, a second erase mode in which the address management table is initialized to indicate that the memory area has no user data, and the blocks, other than a defective block, which are included in the memory area, are erased, and a third erase mode in which the address management table is initialized to indicate that the memory area has no user data, and the blocks, including the defective block, which are included in the memory area, are erased, and the control module selectively using the first erase mode, the second erase mode and third erase mode, thereby executing an erase operation on the memory area, wherein the control module selects the first erase mode when a command for designating the first erase mode is received from the information processing apparatus main body, selects the second erase mode when a command for designating the second erase mode is received from the information processing apparatus main body, and selects the third erase mode when a command for designating the third erase mode is received from the information processing apparatus main body.