Patent ID: 7859245

Claim:
An apparatus for outputting a vital output for a processor including an output state, said apparatus comprising: a first input structured to receive the output state from said processor; two independent circuits, each of said two independent circuits comprising a second input electrically interconnected with said first input, a third input, a fourth input and an output including the output state from said processor, each of said two independent circuits being structured to repetitively monitor the output and the third and fourth inputs of a corresponding one of said two independent circuits to confirm agreement therebetween; two switches, each of said two switches being controlled by the output of the corresponding one of said two independent circuits, said two switches cooperating to form said vital output; and two feedback circuits, each of said two feedback circuits being between the output and the third input of the corresponding one of said two independent circuits, and also being between the output of the corresponding one of said two independent circuits and the fourth input of the other one of said two independent circuits.