Patent ID: 7917879

Claim:
A semiconductor chip configured to include one or more distinct but functionally interfaced dynamic array sections, comprising: a dynamic array section on the semiconductor chip, the dynamic array section following a dynamic array architecture, the dynamic array architecture requiring conductive features to be linearly defined along a virtual grate in one or more levels of the dynamic array section, the dynamic array architecture further defined, (i) wherein a given virtual grate is defined by a framework of parallel lines spaced at about a constant pitch, (ii) wherein some of the parallel lines in the given virtual grate are occupied by multiple conductive features and a substantially uniform gap is maintained between proximate ends of adjacent conductive features that occupy a common line in the given virtual grate; and (iii) wherein the substantially uniform gap between the proximate ends of adjacent conductive features is maintained within each line that is occupied by multiple conductive features within the given virtual grate.