Patent ID: 7865809

Claim:
A system for performing data error correction in a non-volatile memory device comprising: a plurality of data error detectors each containing an odd-syndrome calculator, wherein the odd-syndrome calculator is configured for calculating odd terms of syndrome polynomial of a codeword; at least one data encoder configured for encoding a chunk of data based on a predetermined coding scheme of (Bose, Ray-Chaudhuri, Hocquenghem) BCH (4200, 4096, 8) code including a 4200-bit codeword with 4096-bit information data and up to eight (8) random correctible data errors; a multiplexer coupling to the plurality of data error detectors; and a data error corrector, coupling to the multiplexer, comprising an even-syndrome calculator, a key-solver and an error locator, wherein the even-syndrome calculator is configured for calculating even terms of the syndrome polynomial, wherein the key solver is configured for determining coefficients of error polynomial based on the odd and even terms of the syndrome polynomial, and wherein the error locator is configured for finding one or more locations of random data error using the coefficients of error location polynomial.