Patent ID: 7906399

Claim:
A method of making a MOS transistor, comprising: forming a gate insulating layer on a semiconductor substrate; forming a gate conductor on the gate insulating layer over a channel in the substrate, the channel having a width W 0 and a length L 0 , and the gate conductor having a contact region not intersecting an active area of the MOS transistor; and implanting dopant ions using a photo mask in an active area of the substrate to form (i) a source and a drain on opposite sides of the channel, each of the source and the drain having a width equal to W 0 , a length L s/d , and a contact region, and (ii) at least one of an additional source area and an additional drain area, the additional source area and/or additional drain area extending between the contact region of the source and/or the drain to the contact region of the gate conductor, and having a width W 1 larger than W 0 and a length L 1 less than L s/d .