Patent ID: 7211482

Claim:
A method for forming a memory cell of a semiconductor memory device, comprising: forming a field region and an active region on a substrate; forming a source/drain region in the substrate; forming a recess gate hole by etching the substrate in the active region; forming a gate oxide layer on the active region of the substrate; forming a gate layer and a gate mask layer on the gate oxide layer; and patterning the gate layer, the gate mask layer and the gate oxide layer to form a plurality of access gates on the active region of the substrate and a plurality of pass gates on the field region of the substrate and to form a notch in each of the plurality of access gates by decreasing a width of each of the plurality of access gates on at least one side thereof so that a width of each of the plurality of access gates is narrower than a width of each of the pass gates, to thereby form a first self-aligned contact region between adjacent pass gates and access gates and a second self-aligned contact region between adjacent access gates, wherein a width, of the first self-aligned contact region is larger than a width of the second self-aligned contact region.