Patent ID: 8427205

Claim:
A method for fast locking of a wide-range frequency synthesizer comprising: receiving, by a first processing unit, a digital information signal relating to a required final frequency signal; determining, by the first processing unit, a primary frequency value and a corresponding frequency multiplication mode based upon the digital information signal; receiving, by a primary synthesizer, the primary frequency value and an external reference frequency signal; generating, by the primary synthesizer, a signal of the primary frequency value based upon the received primary frequency value and the external reference frequency signal; receiving, by a second processing unit, the primary frequency value; determining, by the second processing unit, a pre-charge voltage value corresponding to the primary frequency value, wherein the pre-charge voltage value is voltage value across a loop filter of a delay locked loop measured by the second processing unit during a training mode; receiving, by the delay locked loop, the signal of the primary frequency value; transmitting, by the second processing unit, in response to a change in the primary frequency value, a signal to open the delay locked loop and the pre-charge voltage value measured during the training mode corresponding to a new value of the primary frequency signal; pre-charging the delay locked loop to the pre-charge voltage value for a predetermined time in response to opening the delay locked loop; and closing the delay locked loop in response to pre-charging the delay locked loop to obtain fast locking of the wide-range frequency synthesizer.