Patent ID: 7236385

Claim:
An integrated circuit memory device comprising: a substrate assembly comprising first and second memory arrays separated by a throat region, the throat region comprising a data path; first, second and third metal layers, each layer being disposed in substantially parallel spaced relation over said substrate assembly, each layer including a plurality of traces; a plurality of IO lines connected between said memory arrays and said throat region, wherein a first portion of said IO lines are routed through said second metal layer and a second different portion of said IO lines are routed through said third metal layer; a first row logic circuit respectively connected to and associated with said first memory array and located on a side of said first memory array opposite a side of said first memory array that is adjacent said throat region; and a second row logic circuit respectively connected to and associated with said second memory array and located on a side of said second memory array opposite a side of said second memory array that is adjacent said throat region.