Patent ID: 7397685

Claim:
A semiconductor memory device comprising: a memory cell including a ferroelectric capacitor and a cell transistor and storing binary data at a first potential level and a second potential level which is higher than the first potential level; a bit line which reads the binary data out of the memory cell; a correction circuit which corrects an error of the binary data read out of the memory cell via the bit line; a setting circuit which sets to the first potential a potential of the bit line connected to the memory cell from which the binary data is once read, after the binary data is transferred to the correction circuit; and a control circuit which controls the potential of the bit line connected to the memory cell from which the binary data is read, in accordance with a result of error correction of the binary data in the correction circuits, wherein the control circuit sets the potential of the bit line connected to the memory cell from which the binary data is read at the second potential level when the result of error correction corresponds to the second potential level.