Patent ID: 7868668

Claim:
A power-on detector, comprising: a voltage-detecting unit, configured for receiving an input voltage, and detecting the input voltage to output a first output voltage, the voltage-detecting unit comprising: a first transistor, wherein a source of the first transistor is coupled to the input voltage, and a gate and a drain of the first transistor are coupled to each other; a second transistor, wherein a source of the second transistor is coupled to the input voltage, and a gate and a drain of the second transistor are coupled to each other; a third transistor, wherein a source of the third transistor is coupled to a ground, and a gate and a drain of the third transistor are coupled to each other; a fourth transistor, wherein a source of the fourth transistor is coupled to the ground, and a gate and a drain of the fourth transistor are coupled to each other; a first resistor, having a first terminal coupled to the drain of the first transistor, and a second terminal coupled to the drain of the third transistor; a second resistor, having a first terminal coupled to the drain of the second transistor, and a second terminal coupled to the drain of the fourth transistor; and a comparator, having an output terminal outputting the first output voltage, a negative input terminal coupled to the second terminal of the first resistor, and a positive input terminal coupled to the first terminal of the second resistor, wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.