Patent ID: 7254201

Claim:
A clock and data recovery circuit comprising: a clock signal generator that generates N clock signals, each clock signal having a phase difference of 360/N degrees from each other, wherein N denotes an integer, and wherein phases of the N clock signals are 360/N×K, wherein K denotes an integer from K=0 to N−1; a phase selector that selects an (I+2) th clock signal of the N clock signals as a recovered clock signal if an clock signal of the N clock signals is in a first state and if an (I+1) th clock signal of the N clock signals is in a second state when a logic level transition of a received data is detected, wherein I denotes an integer from 1 to N; and a recovered data generator that receives the received data and the recovered clock signal to generate a recovered data that is synchronized with the recovered clock signal output from the phase selector.