Patent ID: 8759169

Claim:
A method for producing a semiconductor wafer having an active silicon layer and at least one III-V layer ( 30 , 31 , 32 ) configured to integrate components formed from III-V semiconductor material and silicon by using a silicon process technology comprising: providing an SOI silicon wafer ( 1 ) with a buried insulation layer ( 22 ) and an active silicon layer ( 24 , 42 ) formed thereon, wherein at least a first ( 39 ) and at least a second ( 38 ) area of the active silicon layer ( 24 , 42 ) being electrically insulated from each other are formed by the buried insulation layer ( 22 ) and a trench isolation ( 26 ; 26 ′, 26 ″); covering the first insulated area ( 39 ) of the active silicon layer ( 24 , 42 ) with a mask ( 29 , 59 ); forming a cavity ( 28 , 43 , 70 ) in the second area ( 38 ) of the active silicon layer ( 24 , 42 ) by using the mask ( 29 , 59 ) as an etch mask, wherein the cavity is formed to extend through the buried insulation layer ( 22 ) and terminate in or on a crystalline semiconductor material whereon the buried insulation layer is formed; and forming at least one single-crystalline III-V layer ( 30 , 31 , 32 ) in the cavity ( 28 , 43 , 70 ) by a selective epitaxy process in the presence of the mask ( 29 , 59 ).