Patent ID: 7817756

Claim:
A processor circuit for suppressing interference in a received signal represented as digital signal samples, the processor circuit comprising: an adaptive filter which is configured to process a first quantity of digital signal samples per unit time when the adaptive filter is operating in a first mode, and a second quantity of digital signal samples per unit time when the adaptive filter is operating in a second mode, wherein the first quantity is less than the second quantity; wherein the first mode is an adaptive mode in which the adaptive filter adapts to changes in the received signal, and the second mode is a non-adaptive mode having a reduced adaptability compared to the adaptive mode; wherein the adaptive filter is configured to perform a first computation load per sample when the adaptive filter is operating in the adaptive mode, and a second computation load per sample when the adaptive filter is operating in the non-adaptive mode, the second computation load per sample being less than the first computation load per sample; wherein a ratio of the first quantity of digital signal samples per unit time to the second quantity of digital samples per unit time is approximately equal to a ratio of the second computation load to the first computation load.