Patent ID: 7864621

Claim:
A compiled memory formed on a chip with a functional block and accessed by the functional block comprising: a pair of memory blocks each including word groups each having at least one of word lines, memory cells coupled to the word lines, and bit lines coupled to each of the memory cells; a data control unit inputting/outputting a data signal to/from the memory cells via the bit lines; couple control units each provided with correspond to the memory blocks to selectively couple the bit lines of each of the memory blocks to the data control unit; and a decoder unit selecting one of the couple control units corresponding to one of the memory blocks to be accessed, and decoding an address signal to select any of the word groups, wherein a logic of the decoder unit is formed by assigning a bit of the address signal to identify one of the memory blocks and one of the couple control units lower than a bit of the address signal to identify one of the word groups.