Patent ID: 7851329

Claim:
A method comprising: forming a trench in a specific region of a semiconductor substrate using a hard mask pattern formed on the semiconductor substrate as an etch mask, wherein the trench is formed from a top surface of the semiconductor substrate to a maximum depth of about 2000 Å to about 8000 Å; forming a first gate insulating layer which fills the trench; forming a doped drift region in the semiconductor substrate under the first gate insulating layer; forming a source region and a drain region in the semiconductor substrate at both sides of the first gate insulating layer, the source region being separated from the first gate insulating layer and the drain region being in contact with the doped drift region; forming a second gate insulating layer over the semiconductor substrate between the first gate insulating layer and the source region, wherein the doped drift region is separate from the second gate insulating layer; and forming a gate electrode over the first and second gate insulating layers, wherein said forming a first gate insulating layer comprises: forming an insulating layer formed over the semiconductor substrate to fill the trench; planarizing the insulating layer until the hard mask pattern is exposed; and etching an upper portion of the first gate insulating layer when removing the hard mask pattern.