Patent ID: 7659786

Claim:
A ring oscillator comprising: a first logic block having a first input connected to a specific point along a delay path, a first output and a second output; and a second logic block having a first input connected to the first output of the first logic block, a second input connected to the second output of the first logic block, a third input connected to an end of the delay path and a first output connected to a beginning of the delay path, wherein: the first logic block is arranged to, in use, alternately switch its first output and second output from logical HIGH to logical LOW, and vice versa, every time a rising edge is input into its first input; and the second logic block is arranged to, in use, alternately select its first input and its second input every time a rising edge is input into its third input, such that: a pulse width of a signal output from the first output of the second logic block is indicative of the time necessary for one of a rising edge or a falling edge to propagate from the beginning of the delay path to the specific point along the delay path and an inverse pulse width of the signal output from the first output of the second logic block is indicative of the time necessary for the one of the rising edge or the falling edge respectively to propagate from the specific point along the delay path to the end of the delay path.