Patent ID: 8775911

Claim:
A processor comprising: a plurality of cores, wherein at least one of the cores comprises: a cache; a plurality of general purpose registers; and a plurality of execution units comprising a store data unit, an integer execution unit, a floating point execution unit, and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises logic to: perform a cyclic redundancy check (CRC) operation in response to one or more CRC32 instructions executed in a 32-bit mode of operation or a 64-bit mode of operation, wherein the logic is to perform the CRC operation on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, and 32-bits, and wherein the one or more CRC32 instructions are to indicate the data size on which to perform the CRC operation.