Patent ID: 8161439

Claim:
A method of processing an assertion during verification of a logic design, comprising: generating an evaluation engine that encodes, using a non-deterministic finite automata (NFA) model, temporal behavior of the logic design required by the assertion for a single attempt to evaluate the assertion; implementing the evaluation engine in first reconfigurable hardware associated with a hardware accelerator, wherein the hardware accelerator includes an assertion evaluation machine having a hardware implemented first-in-first out (FIFO) configured to receive and transmit data from the evaluation engine; simulating the logic design over a plurality of clock events; and performing attempts to evaluate the assertion by the evaluation engine sequentially based on input stimuli obtained from the logic design during simulation thereof, each of the attempts resulting in one of the assertion passing, the assertion failing, or the assertion requiring further evaluation, wherein each attempt is stored in the hardware implemented FIFO as a token; wherein performing includes initiating at least one new attempt to evaluate the assertion by the evaluation engine for at least one of the plurality of clock events; wherein at each clock event, the at least one new attempt that initiated to evaluate the assertion and all the tokens from previous clock events are processed sequentially by the evaluation engine.