Patent ID: 8372712

Claim:
A method of manufacturing a memory device, the method comprising: forming a first P-typed impurity region and a second P-typed impurity region that have a first P-typed impurity concentration by implanting P-typed impurities into an upper portion of a semiconductor substrate; selectively implanting the P-typed impurities into a surface portion of the second P-typed impurity region to selectively form a third P-typed impurity region having a second concentration substantially larger than the first P-typed impurity concentration at the surface portion of the second P-typed impurity region; subsequently forming a floating gate, an ONO layer pattern and a control gate on the first P-typed impurity region and the third P-typed impurity region; and implanting N-typed impurities into the first P-typed impurity region and the third P-typed impurity region to form a first source region, a first drain region, a second source region and a second drain region, the first source region and the first drain region being formed at the second P-typed impurity region below both sides of the floating gate, the second source region and the second drain region being formed at the first P-typed impurity region below both sides of the floating gate; forming a drain contact on the first drain region; and forming a source contact on the second drain region.