Patent ID: 7543114

Claim:
A memory controller comprising: a main controller configured to store a control data signal received from a processor through a first bus, and control a memory by generating a request data signal based on the stored control data signal; a data reading unit separate from the main controller, configured to store read address signals received from at least one of the processor and IP blocks through a second bus separate from the first bus, and read data from the memory by generating command data signals based on the read address signals; an interface configured to interface at least one of the main controller and the data reading unit with the memory; a controller configured to output a register control signal and a transmission request signal to the interface in response to a transmission control signal received through the second bus, and output first selection control signals when a transmission granting signal is received from the interface; an address register configured to store the read address signals received through the second bus and output the read address signals in response to the register control signal; a first multiplexer configured to select at least one of a plurality of command signals and output the at least one selected command signal as a read command signal in response to an external command selection signal, and a second multiplexer configured to select the read command signal and the read address signals sequentially, and output the read command signal and the read address signal as the command data signal in response to the first selection control signals.