Patent ID: 8222671

Claim:
A thyristor comprising: a plurality of power thyristor devices connected in parallel, each said thyristor device configured to provide a device current at which the device has an on-resistance with a positive temperature coefficient; and wherein each power thyristor device of the plurality of thyristor devices connected in parallel comprises a semiconductor body comprising: a first region of a first conductivity type provided with a first main electrode; a second region of a second conductivity type that is opposite the first conductivity type, the second region forming a first PN junction with the first region; a third region of the first conductivity type forming a second PN junction with the second region and provided with a gate electrode; and a fourth region of the second conductivity type forming a third PN junction with the third region and having an electrical connection to a second main electrode; wherein the gate electrode of the third region comprises an insulated gate overlaying a channel area of the third region; wherein the fourth region has a structure which contacts the second main electrode; wherein the third region is beneath the fourth region; wherein the thyristor has a cell spacing of greater than 300 um, wherein the thyristor has a carrier lifetime of between 0.1 microseconds and 100 microseconds; wherein a depth of an emitter of said thyristor is between 0.5 μm and 3 μm; wherein a structure under the gate comprises a diode with a positive on-state resistance temperature coefficient; and wherein each said device has a MOS gate having a width equal to or greater than said cell spacing and said width being a structural dimension of said MOS gate.