Patent ID: 7883949

Claim:
A method of forming a p-channel MOS device in silicon carbide, comprising: forming an n-type well in a silicon carbide layer; implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer, the p-type region at least partially defining a channel region in the n-type well adjacent the p-type region; forming a p-type threshold adjustment region in the channel region by implanting p-type dopants into the channel region; annealing the implanted ions in an inert atmosphere at a temperature greater than 1650° C.; forming a gate oxide layer on the channel region; and forming a gate on the gate oxide layer; wherein the silicon carbide layer comprises a p-type silicon carbide layer including a JFET region adjacent to the n-type well, and wherein the p-type region comprises a p-type emitter region spaced apart from the JFET region and defining the channel region between the p-type emitter region and the JFET region.