Patent ID: 7073088

Claim:
An apparatus, comprising: a data bus comprising: a plurality of primary signal lines exclusively used to transmit data between modules connected to said bus in the absence of an inoperable signal line; an extra supplemental signal line that remains idle in the absence of an inoperable primary signal line; and a maintenance signal line used to communicate the presence or absence of an inoperable primary signal line and the implementation of the substitute signal line to carry data to each of said plurality of modules, one of said plurality of modules comprises: a bus signal monitor testing for inoperable primary signal lines on said bus; and a microprocessor communicating results of said test and whether said supplemental signal line has been implemented to carry data to each of said plurality of modules via said maintenance signal line, each module comprises a bus signal selector connecting a bus signal transmitter to the appropriate operable, activated signal lines that carry data based on signals received from said maintenance signal line enabling normal data transfer over said bus between ones of said plurality of modules despite a presence of an inoperable primary signal line.