Patent ID: 8447581

Claim:
A method of generating executable simulation code from a circuit design, the method comprising: generating a parse tree of the circuit design wherein multiple instances of a module of the circuit design are represented by a single representative parse node in the parse tree; for each instance of the module represented in the parse tree: creating an instance-specific data structure for the instance; allocating a respective memory area for the instance; storing an address of the respective memory area allocated to the instance in the instance-specific data structure; storing data in the instance-specific data structure of the instance indicating connectivity between the instance and other instances; and configuring the representative parse node of the instance to refer to the respective instance specific data structure of the instance; and generating executable simulation code by a processor, by: traversing the parse tree; and for each instance of the module represented in the parse tree: determining the respective instance specific data structure from the reference in the representative parse node; retrieving the connectivity data and the address memory area allocated to the instance from the respective instance specific data structure; and generating and storing simulation code of the instance using the retrieved memory addresses and connectivity data.