Patent ID: 7795945

Claim:
A signal process circuit, comprising: a first input terminal via which an input signal is supplied; a second input terminal via which a predetermined signal is supplied; a cross-coupled inverter circuit, including first and second CMOS inverter circuits, in which (i) an input of the first CMOS inverter circuit and an output of the second CMOS inverter circuit are interconnected to each other and (ii) an output of the first CMOS inverter circuit and an input of the second CMOS inverter circuit are interconnected to each other; an output terminal connected to one of the output of the first CMOS inverter circuit and the output of the second CMOS inverter circuit; a current control circuit configured to apply current to the first and second CMOS inverter circuits in accordance with a timing signal, the input signal, and the predetermined signal; and a reset circuit configured to connect the output terminal to the first input terminal in response to the timing signal.