Patent ID: 8222106

Claim:
A method of fabricating a nonvolatile semiconductor memory device, comprising: forming a gate insulating film on portions of a semiconductor substrate corresponding to first and second cell array regions respectively; forming a charge storage layer on the gate insulating film of the first and second cell array regions; forming a plurality of element isolation trenches so as to extend through the charge storage layer and the gate insulating film and into the semiconductor substrate; forming an element isolation insulating film in the element isolation trenches of each of the first and second cell array regions; etching an upper part of the element isolation insulating film so that the heights of upper surfaces of first and second element isolation insulating films are lower than the height of the charge storage layer and so that the first element isolation insulating film in the first cell array region has an upper surface located higher than an upper surface of the second element isolation insulating film in the second cell array region; forming an interelectrode insulating film on the charge storage layer and the element isolation insulating film; and forming a control electrode on the interelectrode insulating film.