Patent ID: 8582389

Claim:
A semiconductor memory storage device for storing data comprising: a plurality of storage cells, each storage cell comprising at least two access control devices, each of said access control devices providing said storage cell with access to or isolation from a respective one of two data lines in response to an access control signal, said two data lines being connected to at least one data port; access control circuitry for applying said access control signal via at least one of two access control lines to control a plurality of said access control devices; wherein at least one of said at least two access control devices of each storage cell is controlled by said access control signal received from a first of said two access control lines to provide said storage cell with access to or isolation from a first of said two data lines, and at least one further of said at least two access control devices is controlled by said access control signal received from a second of said two access control lines to provide said storage cell with access to or isolation from a second of said two data lines; said access control circuitry is responsive to at least one data access request, said at least one data access request is a write request, to apply a data value to be written to both of said first and second data lines and to apply said access control signal to both of said first and second access control lines, said access control circuitry is responsive to said write request to apply said access control signal to said first of said two access control lines and after a predetermined time delay to apply said access control signal to said second of said two access control lines.