Patent ID: 8233310

Claim:
A resistance-change memory comprising: bit lines in a first direction; word lines in a second direction intersecting with the first direction; and a memory cell array comprising memory cells each comprising a selection transistor and a variable resistance element configured to store data “0” and data “1” by a change in resistance value, the variable resistance element comprising a first terminal connected to a first bit line and a second terminal connected to a drain of the selection transistor, the selection transistor comprising a source connected to a second bit line and a gate connected to a word line, wherein a first word line is between the first variable resistance element and the second variable resistance element, a second word line is between the third variable resistance element and the fourth variable resistance element, two word lines are between a first pair comprising the first and second variable resistance elements and a second pair comprising the third and fourth variable resistance elements, in a layout of first to fourth variable resistance elements in order in the first direction, and a column is constructed by repeating the layout in the first direction.