Patent ID: 7013443

Claim:
A delay diagnosis method for a semiconductor integrated circuit including a plurality of blocks, comprising the steps of: inputting register transfer level logic information including connection information of said blocks, and floor plan information including positional information of each block on said semiconductor integrated circuit; finding the number of registers or edges as the start point of a path connected to a register or an edge as the end point of said path; computing the logic stage number of said path from the number of registers or edges as the start point of said path; finding block-to-block distances from said floor plan information when said path extends over a plurality of blocks; computing intra-block delays from said logic stage number and gate unit-value delays; computing inter-block delays from said block-to-block distances and routing unit-value delays; and diagnosing if the delay of said path can be converged within a target path delay from the relation among said computed intra-block delays, said computed inter-block delays and said target path delay.