Patent ID: 7245158

Claim:
A circuit wiring layout in a semiconductor memory device, the layout comprising: first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources are connected in parallel to a drain of the second p-type MOS transistor, the first and second p-type MOS transistors and the first and second n-type MOS transistors forming a NOR gating portion for a decoder, wherein the first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line, the first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively, and the first and second p-type MOS transistors sharing an active junction with each other in a first area, and wherein the first and second n-type MOS transistors are spaced from the first area substantially in a direction of the section line and have individual active junctions.