Patent ID: 8484444

Claim:
An apparatus comprising: a plurality of data memories, wherein each data memory of the plurality of data memories comprises a plurality of memory blocks; a processing element (PE) directly coupled to read and write multiplexors for the plurality of data memories by a first bus for load and store accessibility of data in the plurality of memory blocks and directly coupled to an instruction bus; and a hardware assist (HA) unit directly coupled to the read and write multiplexors for the plurality of data memories by a second bus for read and write operations on the data from the plurality of memory blocks and directly coupled to the PE by a third bus, wherein, in response to an instruction received in the PE from the instruction bus, a memory address and control information are transferred in parallel from the PE to the HA unit over the third bus to initiate a HA compute function on memory data transferred from the plurality of memory blocks over the second bus.