Patent ID: 8010334

Claim:
A method of testing an integrated circuit (IC) design, comprising: executing, by a simulator test system, a first workload program on an IC design model, the first workload program including instructions; generating, by the simulator test system, basic block vectors (BBVs) while executing the first workload program, each BBV corresponding to a respective BBV instruction interval of the first workload program, thus defining a number of N instruction intervals; clustering, by the simulator test system, the BBVs by program phase of the first workload program to form BBV clusters; determining, by the simulator test system, a cycles per instruction (CPI) error rate on a per instruction interval basis to provide a base error rate; storing, by the simulator test system, fine grain microarchitecture dependent error rate information that indicates microarchitecture dependent errors of different types that the simulator test system produces during the BBV instruction intervals of the first workload program, thus storing fine grain microarchitecture dependent error rate information for each of the N instruction intervals; storing, by the simulator test system, coarse grain microarchitecture dependent error rate information that indicates microarchitecture dependent errors of different types that the simulator test system produces during execution of the entire first workload program, and generating, by the simulator test system, a weighted error rate including the cycles per instruction (CPI) error rate as the base error rate, the weighted error rate further including weighted fine grain microarchitecture dependent error rate information and weighted coarse grain microarchitecture dependent error rate information.