Patent ID: 8468477

Claim:
A method, comprising: accepting an original hardware description language (HDL) file prescribing an original logic; accepting an original netlist incorporating said original logic, wherein said original netlist has nets; accepting a new HDL file prescribing a new logic, wherein said new logic comprises a logic change relative to said original logic, wherein said original HDL file and said new HDL file both comprise signals; adding a user hint to both said original HDL file and said new HDL file when one of said signals is different between said new HDL file and said original HDL file; creating a current netlist from said original HDL file by using logic synthesis; creating a new netlist from said new HDL file by using logic synthesis, and transferring said user hint into both said current netlist and said new netlist; wherein said current netlist and said new netlist both comprise nets, substituting hint nets in said current netlist with hint nets from said new netlist, wherein hint nets are those of said nets that pertain to said user hint, whereby said current netlist is turned into a specification (SPEC) netlist incorporating said new logic; using said original netlist for executing an equivalence based reduction on said SPEC netlist to generate a delta netlist by: finding a functional correspondence between said original netlist and said current netlist; and recording said functional correspondence on said current netlist; by making use of said recorded functional correspondence on said SPEC netlist, substituting a portion of said nets in said original netlist with a corresponding portion of said nets of said SPEC netlist; and synthesizing said delta netlist using a computer, and inserting said delta netlist into said original netlist, whereupon said original netlist is incorporating said new logic.