Patent ID: 7940574

Claim:
A nonvolatile semiconductor memory including a plurality of memory cells each comprising: a source area, a channel area, and a drain area thereon in this order extending from a surface of a substrate and in a direction perpendicular to the surface of the substrate, and further having a charge-storage layer on an outside surface of the channel area via a gate insulating film, and a control gate on an outside surface of the charge-storage layer so as to cover the charge-storage layer via an insulating layer, the memory cells arranged in a matrix of n rows and m columns on the substrate and further comprising: a plurality of first source lines arranged in a column direction and connecting the source areas of the memory cells with respect to each other; a plurality of parallel bit lines arranged in the column direction and connecting the drain areas with respect to each other on a layer different from the first source line; a plurality of gate lines arranged in a row direction substantially orthogonal to the column direction and connecting the control gates with respect to each other; and second source lines arranged one each at every p rows (p<n) of the matrix and comprising a metal and connecting the first source lines with respect to each other.