Patent ID: 8275941

Claim:
An information processing apparatus, comprising: a cache memory; and a controller configured to write data to the same address of a first storage device and a second storage device which are configured to write and read data per page and to erase data per block unit comprising pages, wherein the controller is configured to: write first data to the first storage device from a first write address to a second write address according to a size of the first data when the controller receives a writing instruction comprising the first write address and the first data; write second data having first data to the second storage device from a head of the first data, a size of the second data is equal to n times a page size, where n is an integer greater than or equal to 1; write, to the cache memory, third data having a size equal to a difference between the size of the first data and the size of the second data, the size of the third data is smaller than the page size; and write fifth data to the second storage device when the controller receives a writing instruction comprising from a third write address is adjacent to the second write address, the fifth data comprising the third data and at least part of fourth data, and a size of the fifth data is equal to the page size.