Patent ID: 7721010

Claim:
A system, comprising: a memory controller configured to output commands, addresses, and data; a first memory device configured to: decode the commands, thereby providing the decoded commands, latch the addresses and the data from the memory controller via a first port of the first memory device, thereby providing latched addresses and latched data, and output the decoded commands, the latched addresses, and the latched data via a second port of the first memory device; and a second memory device comprising a first port and a second port, wherein the second memory device is configured to receive the decoded commands, the latched addresses, and the latched data via the second port of the second memory device, wherein the first memory device and the second memory device are fabricated using substantially the same fabrication procedures and contain identical components, and wherein the second memory device includes logic for decoding the commands and the logic is bypassed when the decoded commands, the latched addresses, and the latched data are received via the second port of the second memory device.