Patent ID: 7009442

Claim:
A linear multiplier circuit, receiving a first input signal and a second input signal, generating a current proportional to a product of the first and second input signals on an output terminal of the linear multiplier circuit, the linear multiplier circuit comprising: a first transistor; a second transistor; a third transistor; and a fourth transistor; wherein each of the first transistor, the second transistor, the third transistor and the fourth transistor has a drain, a source, a gate, and substantially an identity threshold voltage, and operates in a saturation mode with a substantially fixed drain-to-source voltage applied between the drain and source, a gate-to-source voltage applied between the gate and source; wherein the sources of the first and second transistors, and the drains of the third and fourth transistors are coupled together, and the gate-to-source voltages of the first, second, third and fourth transistors are respectively a sum of the first input signal, the second input signal, an additional input signal and the threshold voltage, a sum of the additional input signal and the threshold voltage, a sum of the first input signal, the additional input signal and the threshold voltage, and a sum of the second input signal, the additional input signal and the threshold voltage.