Patent ID: 7365661

Claim:
A digital signal to pulse converter ( 1201 ) comprising: a content addressable memory ( 2494 . 4 ) having at least a write port ( 2428 . 4 ) and a read port ( 2498 . 4 ), wherein the write port ( 2428 . 4 ) is operable to write a first set of data into the content addressable memory ( 2494 . 4 ) as stored data, and the read port ( 2498 . 4 ) is operable to receive a second set of data, wherein the write port ( 2428 . 4 ) is further operable to write said first set of data as stored data to two or more address locations in the content addressable memory ( 2494 . 4 ), wherein each of said two or more address locations is associated with a respective one of a plurality of pulses, and the content addressable memory ( 2494 . 4 ) is operable to compare the stored data with the second set of data and, if a match occurs, to provide an output signal to simultaneously determine a beginning or an end of each of the two or more pulses which are respectively associated with said two or more address locations.