Patent ID: 8914801

Claim:
A system for performing mathematical function evaluation, comprising: a plurality of tables providing values for processing a plurality of mathematical functions; a processing unit comprising logic interfacing with the plurality of tables, the logic further comprising: a first hardware instruction configured to lookup a first value for use in a first stage of evaluation for a mathematical function, the first value retrieved from one of the plurality of the tables; a second hardware instruction configured to retrieve a second value for use in a second stage of evaluation for the mathematical function, the second value used retrieved from the table to be used in conjunction with the first value retrieved by the first instruction; said retrieving of the second value being performed by using the same input as the first hardware instruction, using a value saved by a lookup from a FIFO queue, or using a value saved in a slot according to an immediate tag provided to the second hardware instruction; and a third hardware instruction configured to perform an extended-range fused multiply-add operation, the extended-range fused multiply-add operation performing a range reduction on the mathematical function using the first value.