Patent ID: 8828820

Claim:
A method for forming a transistor, comprising: forming a mask layer on a semiconductor substrate on which a gate has been formed so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer so that at least a portion of at least one of a source region and a drain region is exposed; performing a first ion implantation in the exposed portion of the source region and/or the drain region; and annealing the semiconductor substrate so as to form a dislocation in the exposed portion of the source region and/or the drain region; forming a semiconductor layer containing silicon on the source and drain regions; and forming a metal layer on the semiconductor layer and performing annealing so as to form a metal silicide, wherein the bottom of the metal silicide is higher than the channel between the source region and the drain region; wherein at least one further ion implantation with an implantation depth smaller than that of the first ion implantation is performed after the step of annealing, and the implantation depth of a later ion implantation is smaller than that of a former one in the case that more than one further ion implantations are performed; and an annealing is performed after each of the at least one further ion implantation so that a dislocation is formed; and wherein before one or more of the at least one further ion implantation, a mask layer is selectively formed on the source region and/or the drain region to cover one or more portions of the source region and/or the drain region, wherein no mask layer exists between adjacent ones of the more portions so that ion implantation is only performed to the portions of the source region that are not covered by the mask layer.