Patent ID: 8853027

Claim:
A method of fabricating a split gate memory device, the method comprising: forming an electrically conductive select gate overlying a channel region of a semiconductor substrate; forming a counter doping region in an upper region of the substrate outside of the channel region, wherein a proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate, wherein a conductivity type of the channel region and a first conductivity type of the counter doping region are opposite and wherein an impurity concentration of the counter doping region exceeds an impurity concentration of the channel region; forming an extension region aligned to a distal boundary of the select gate; forming a heavily doped source/drain region adjacent to the extension region; forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region; and forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer; wherein the extension region and the source/drain region have a conductivity type of the counter doping region and wherein an impurity concentration of the extension region is greater than an impurity concentration of the counter doping region and an impurity concentration of the source/drain region is greater than an impurity concentration of the extension region.