Patent ID: 7969780

Claim:
A nonvolatile semiconductor memory device comprising: a flip-flop having a first node (node T) and a second node (node B), the flip-flop having a first inverter to control the first node and a second inverter to control the second node, the first inverter and the second inverter being cross coupled, the first inverter including a first load transistor (MP 1 ) and a first cell transistor (MCN 1 ) connected in series, the second inverter including a second load transistor (MP 2 ) and a second cell transistor (MCN 2 ) connected in series, each of the first cell transistor and the second cell transistor being a threshold controllable transistor; a first bit line (BLT) and a second bit line (BLB); a voltage source line (SL) commonly and directly connected to a source of the first cell transistor and a source of the second cell transistor; a word line; a first gate transistor (MN 1 ) connected between the first bit line and the first node, the first gate transistor being controlled by the word line; a second gate transistor (MN 2 ) connected between the second bit line and the second node, the second gate transistor being controlled by the word line; a first precharge transistor (MP 3 ) connected in parallel to the first load transistor; and a second precharge transistor (MP 4 ) connected in parallel to the second load transistor, wherein the voltage source line (SL) is configured so as to provide a positive voltage to the source of the first cell transistor (MCN 1 ) and the source of second cell transistor (MCN 2 ) in a write mode.