Patent ID: 7571277

Claim:
A semiconductor memory system, comprising: a first memory chip including a plurality of non-volatile memory blocks capable of being erased at once; a second memory chip including a plurality of non-volatile memory blocks capable of being erased at once; and a controller for controlling the first memory chip and the second memory chip, wherein the controller includes: an in-use memory block assigning unit for assigning a part of the memory blocks in the first memory chip as a memory block in use to/from which read/write is performed; a reserved memory block assigning unit for assigning a part of the memory blocks in the first memory chip as a reserved memory block; a degradation detecting unit for detecting degradation of the memory block in use in the first memory chip; an intra-chip block switching unit for switching the memory block in use in the first memory chip whose degradation has been detected to the reserved memory block in the first memory chip as the memory block in use; a remaining reserved memory block count judging unit for detecting a number of the reserved memory blocks unused in the first memory chip and judging whether or not the number of the reserved memory blocks unused has reached a first predetermined value; a memory block initializing unit for starting initialization for the memory block in the second memory chip when the number of the reserved memory blocks unused in the first memory chip reaches the first predetermined value; a memory chip switch judging unit for judging whether or not the number of the reserved memory blocks unused in the first memory chip has reached a second predetermined value; and a memory chip switching unit for assigning the memory block in the second memory chip which has been initialized as the memory block in use in place of the first memory chip when the number of the reserved memory blocks unused in the first memory chip reaches the second predetermined value, and wherein the first predetermined value is set, based on progression speed of the degradation of the first memory chip and speed at which the memory block initializing unit performs the initialization, to such a value that the initialization for the memory block in the second memory chip is completed during a time period between when the memory block initializing unit starts the initialization and when the number of the reserved memory blocks unused in the first memory chip reaches the second predetermined value.