Patent ID: 7861066

Claim:
A processor comprising: one or more execution units configured to execute instruction operations; a scheduler coupled to the one or more execution units and configured to issue the instruction operations for execution by the one or more execution units, and to cause instruction operations that are determined to be incorrectly executed to be replayed; a prediction unit configured to predict, prior to execution, whether a given instruction operation will replay based on an execution history of the given instruction operation, and to provide an indication that the given instruction operation will replay; a decode unit coupled to the scheduler and configured to decode instructions, wherein in response to detecting the indication, the decode unit is further configured to flag the given instruction operation by asserting one or more instruction opcode bits of the given instruction operation; wherein the scheduler is configured to store within a buffer, a prediction bit along with the flagged instruction operation; and wherein the scheduler is further configured to inhibit issue of the given instruction operation that has been flagged until a status associated with the given instruction operation that has been flagged is good.