Patent ID: 7528995

Claim:
A synchronization signal generator comprising: a phase locked loop unit that generates a high-frequency clock signal based on a reference clock signal and a synchronization detection signal; and a plurality of pixel clock generators each of which generates a pixel clock signal based on the high-frequency clock signal and the synchronization detection signal, wherein each of the pixel clock generators includes: a pixel clock generation unit that divides a frequency of said high-frequency clock signal so as to generate one or more first pulses of a reference period, one or more second pulses of a long period longer than the reference period and one or more third pulses of a short period shorter than the reference period, and said pixel clock generation unit outputting, as the pixel clock signal, one of the first, second and third pulses that is designated by an output selection signal; a first data generation unit that outputs a first selection signal selectively designating one of the first, second and third pulses, in synchronization with said pixel clock signal, in accordance with a time-series distribution of the first second and third pulses of each period defined by a first set of data; a second data generation unit that outputs a second selection signal selectively designating one of the first, second and third pulses, in synchronization with said pixel clock signal, in accordance with a time-series distribution of the first, second and third pulses of each period defined by a second set of data; and a synthesizing unit that synthesizes the first selection signal and the second selection signal so as to generate said output selection signal and outputs said output selection signal to said pixel clock generation unit.