Patent ID: 7683415

Claim:
A method of fabricating a semiconductor device, comprising: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a nitride-based layer, a lower electrode layer, a dielectric layer, an upper electrode layer and a hard mask layer on the inter-layer insulation layer; etching the hard mask layer and the upper electrode layer with a first photoresist pattern as an etch mask and the dielectric layer as an etch stop layer; removing the first photoresist pattern; etching the dielectric layer and the lower electrode layer with a second photoresist pattern as an etch mask and the nitride-based layer as an etch stop layer, thereby obtaining a capacitor including an upper electrode, a patterned dielectric layer, a lower electrode and the etched hard mask layer; removing the second photoresist pattern; forming a diffusion barrier layer on the capacitor and the nitride-based layer over the inter-layer insulation layer, wherein a stack of the nitride-based layer and the diffusion barrier layer is formed over the contact plug; and sequentially forming a first metal interconnection line connected with the contact plug by using both of the diffusion barrier layer and the nitride-based layer and the nitride-based layer as an etch top, and second metal interconnection lines connected with the capacitor.