Patent ID: 8751210

Claim:
A method of simulating a circuit design comprising: loading a specification of the circuit design into a first runtime stack; simulating the circuit design specification on a simulator in the first runtime stack; in response to each call during simulation to each first process contained in the specification and having no call to a procedure that contains a wait statement: loading the first process into the first runtime stack; and executing statements of the first process; in response to a call during simulation to a second process contained in the specification and having a call to a procedure containing a wait statement: saving a first state corresponding to the current state of simulation; loading the second process into a second runtime stack; and setting the current state of simulation to a state for continuing simulating with the second process in the second runtime stack; and in response to a wait statement encountered in the procedure called by the second process during simulation of the second process in the second runtime stack: saving a second state corresponding to the current state of simulation; and setting the current state of simulation to the first state for continuing simulating of the specification in the first runtime stack; in response to the simulator determining the wait statement has expired, performing the steps of: saving a third state corresponding to the current state of the simulation; and setting the current state of the simulation to the second state for continuing simulating of the second process in the second runtime stack; in response to completing the simulation of the second process in the second runtime stack, setting the current state of the simulation to the third state for continuing simulating of the specification in the first runtime stack.