Patent ID: 8563363

Claim:
A fabricating method of semiconductor package structure, comprising: providing a dielectric layer, having a first surface and a second surface opposite to each other, wherein a patterned metal layer has been formed on the first surface of the dielectric layer; forming an opening going through the first surface and the second surface of the dielectric layer; forming a first adhesive layer on the second surface of the dielectric layer prior to forming the opening of the dielectric layer; forming a carrier at the second surface of the dielectric layer, wherein the carrier has a third surface and a fourth surface opposite to each other and a portion of the third surface is exposed by the opening of the dielectric layer, and the first adhesive layer is located between the dielectric layer and the carrier for stably fixing the dielectric layer on the carrier; joining a semiconductor die in the opening of the dielectric layer, wherein the semiconductor die has a joining surface and a side-surface; forming a second adhesive layer on the third surface of the carrier exposed by the opening of the dielectric layer prior to joining the semiconductor die, wherein the second adhesive layer is located on the joining surface of the semiconductor die; forming at least a through hole going through the third surface and the fourth surface of the carrier, wherein the joining surface and a portion of the side-surface of the semiconductor die are exposed by the through hole; and forming a metal layer on the fourth surface of the carrier, wherein the metal layer has at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity, an end of the heat conductive post protrudes away from the third surface of the carrier, the containing cavity is located on the end of the heat conductive post and the semiconductor die is located in the containing cavity; forming a stress buffer layer on the joining surface and a portion of the side-surface of the semiconductor die prior to forming the metal layer.