Patent ID: 7801249

Claim:
A carrier phase and symbol timing recovery circuit for recovering a carrier phase and a symbol timing in received digital signal data, the circuit comprising: a pilot-based error detector detecting a first phase error based on a pilot signal included in the received digital signal data; a lower error detector detecting a second phase error based on data in a lower overlapped region, where a lower portion of an information-containing signal included in the received digital signal data overlaps a replica of the information-containing signal; an upper detector detecting a third phase error based on data in an upper overlapped region, where an upper portion of the information-containing signal overlaps a replica of the information-containing signal; a first calculation unit determining a carrier phase offset value from the detected first, second, and third phase errors; and a second calculation unit determining a symbol timing offset value from the detected first, second, and third phase errors; wherein a desired sampling time instant and carrier phase offset are detected at a point where an output of the first calculation unit and an output of the second calculation unit are both zero, so as to simultaneously recover the carrier phase and the symbol timing in the received digital signal data, wherein the first and second calculation units detect a point where mean values of the first, second, and third phase errors are simultaneously zero by using feedback, wherein the first calculation unit multiplies at least one of the first, second, and third phase errors with a respective constant before adding the first, second, and third phase errors, and wherein the second calculation unit multiplies at least one of the first, second, and third phase errors with the respective constant before adding the first phase error to the second phase error to obtain an addition result and subtracting the third phase error from the addition result.