Patent ID: 7523248

Claim:
A memory system, comprising: an integrated circuit master device; a first memory module, the first memory module including: a first integrated circuit buffer device, and a first plurality of integrated circuit memory devices to store data received from the first integrated circuit buffer device; a first plurality of signal lines between the first integrated circuit buffer device and the first plurality of integrated circuit memory devices, wherein the first plurality of signal lines includes a signal line to carry a source synchronous signal that has a predetermined temporal relationship with the data as the data is transferred between the first integrated circuit buffer device and the first plurality of integrated circuit memory devices; a first point-to-point link between the integrated circuit master device and the first integrated circuit buffer device, wherein the first point-to-point link transfers data, address, and control information between the integrated circuit master device and the first integrated circuit buffer device; and a second memory module, the second memory module including: a second integrated circuit buffer device, and a second plurality of integrated circuit memory devices to store data received from the second integrated circuit buffer device; and a second point-to-point link between the integrated circuit master device and the second integrated circuit buffer device, wherein the second point-to-point link transfers data, address, and control information between the integrated circuit master device and the second integrated circuit buffer device.