Patent ID: 7195958

Claim:
A method of fabricating an ESD protection structure on a semiconductor substrate, said ESD protection structure protecting an integrated circuit also fabricated on said semiconductor substrate, comprising: applying a first mask on said semiconductor substrate, said first mask exposing a first area on a surface of said semiconductor substrate to a well implant process for forming N-wells or P-wells in said integrated circuit; applying a second mask on said semiconductor substrate, said second mask exposing a second area adjacent said first area on said surface to a lightly doped drain implant process for forming lightly doped drain regions in said integrated circuit; applying a third mask on said semiconductor substrate, said third mask exposing a third area to a first source/drain implant process for forming a first set of source/drain regions in said integrated circuit, wherein a first part of said third area overlaps with said first area and a second part of said third area overlaps with said second area, and wherein a diffusion region formed in said third area and a diffusion region formed in said second area form a triggering diode for triggering the ESD protection structure to discharge an ESD pulse on said integrated circuit; applying a fourth mask on said semiconductor substrate, said fourth mask exposing a fourth area within said first area to a second source/drain implant process for forming a second set of source/drain regions in said integrated circuit; and forming non-rectifying electrical connections between the second source/drain regions and the first source/drain regions.