Patent ID: 7401242

Claim:
A computer-implemented method comprising: detecting a stall condition within a pipeline stage from a plurality of pipeline stages, wherein the pipeline stage includes a first register, a second register, a first fill detector, and a second fill detector, the first fill detector controlling the first register and the second fill detector controlling the second register; activating a stall signal to the first fill detector in response to detecting the stall condition; in response to receiving the activated stall signal, waiting until the first register includes a first instruction and gating off a first clock to the first register using the first fill detector once the first register includes the first instruction; after gating off the first clock, sending a first register loaded signal from the first fill detector to the second fill detector; and in response to receiving the first register loaded signal, waiting until the second register includes a second instruction and gating off a second clock to the second register using the second fill detector once the second register includes the second instruction.