Patent ID: 7366271

Claim:
A clock and data recovery (CDR) device capable of recovering a clock from data transmitted at a variable data rate, the CDR device comprising: a reference clock generating section arranged to generate a reference clock corresponding to the variable data rate in accordance with a control signal; a clock and data recovery section arranged to receive the transmitted data, recover a clock and data from the received data and output the recovered clock and data; and a control section arranged to generate the control signal according to the variable data rate and send the control signal to the reference clock generating section, wherein said clock and data recovery section comprises: a NRZ (No Return to Zero)-PRZ(Pseudo Return to Zero) converter arranged to convert an NRZ signal having no clock component into a PRZ signal including a clock component and outputting the PRZ signal; a phase/frequency detector arranged to compare the reference clock output from the reference clock generating section with a clock component of the signal outputted from the NRZ-PRZ converter to detect a phase error there between, compare a clock of a signal outputted from a second divider, which has been produced by dividing an output clock of a second voltage-controlled oscillator by a third value M set by the control section, with the clock component of the signal outputted from the NRZ-PRZ converter to detect a frequency error there between, and output the frequency error; a filter arranged to filter the frequency error and compensate for a feedback loop; a second voltage-controlled oscillator arranged to output a phase-synchronized clock according to the control of the filter; a second divider arranged to divide the synchronized clock outputted from the second voltage-controlled oscillator by a third value M which is set by the control section and output the divided clock; and an output section arranged to receive NRZ data and the synchronized clock output from the second voltage-controlled oscillator and output a combined a clock and data signal.