Patent ID: 7615445

Claim:
A method of forming an array of non-volatile memory cells on a semiconductor substrate having a surface, comprising: forming a dielectric layer on the surface of a substrate; forming a first conductive layer over the dielectric layer; forming trenches in the substrate, the trenches separate the first conductive layer into a plurality of first conductive portions, the trenches separate the dielectric layer into a plurality of gate dielectric regions that are self-aligned to the plurality of first conductive portions; forming a plurality of shallow trench isolation structures in the trenches, the shallow trench isolation structures extend in a first direction and are spaced apart in a second direction that is perpendicular to the first direction; subsequently forming a plurality of sidewall spacers that extend in the first direction along exposed sidewalls of ones of the plurality of shallow trench isolation structures, the plurality of sidewall spacers overlying first conductive portions; subsequently forming a plurality of second conductive portions defined by the plurality of sidewall spacers and contacting the first conductive portions; and subsequently removing the plurality of sidewall spacers thereby exposing surfaces of the plurality of first conductive portions and the plurality of second conductive portions.