Patent ID: 7439100

Claim:
A method for forming chip scale packages having flip-chip on lead frame interconnect structures comprising the steps of: providing a main lead frame having first and second sub lead frames, wherein the first and second sub lead frames have a plurality of conductive leads; providing first and second electronic devices, each having a plurality of solderable patterned pads formed on first major surfaces of the first and second electronic devices; solder attaching the solderable patterned pads on the first electronic device to the first sub lead frame in a flip-chip on lead frame configuration without using an intervening solder ball, solder bump, or stud bump, wherein the plurality of solderable patterned pads are configured to physically separate the first electronic device from the first sub lead frame when attached thereto; solder attaching the solderable patterned pads on the second electronic device to the second sub lead frame in a flip-chip on lead frame configuration without using an intervening solder ball, solder bump, or stud bump, wherein the plurality of solderable patterned pads are configured to physically separate the second electronic device from the second sub lead frame when attached thereto; encapsulating the first and second sub lead frames and the first and second electronic devices with an encapsulating material to form an encapsulated assembly; and separating the encapsulated assembly to provide the chip scale packages.