Patent ID: 8391065

Claim:
A semiconductor memory device, comprising: a first memory cell block; a second memory cell block adjacent to the first memory cell block in a first direction; and an interconnect rerouting unit provided between the first memory cell block and the second memory cell block, the first memory cell block including: a plurality of first cell units, each of the plurality of first cell units including a plurality of memory cells; a plurality of second cell units, each of the plurality of second cell units including a plurality of memory cells; a plurality of first interconnects; and a plurality of second interconnects, each of the plurality of first interconnects being aligned in the first direction and connected to one end of each of the first cell units respectively, each of the plurality of second interconnects being aligned in the first direction in each space between the first interconnects and connected to one end of each of the second cell units respectively, the each of the plurality of second interconnects having at least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction being smaller than a width of each of the plurality of first interconnects along the second direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction being smaller than a thickness of each of the plurality of first interconnects along the third direction, the second memory cell block including: a plurality of third cell units, each of the plurality of third cell units including a plurality of memory cells; a plurality of fourth cell units, each of plurality of fourth cell units including a plurality of memory cells; a plurality of third interconnects; and a plurality of fourth interconnects, each of the plurality of third interconnects being aligned in the first direction on a line extending from the first interconnect in the first direction and connected to one end of each of the third cell units respectively, each of the plurality of fourth interconnects being aligned in the first direction on a line extending from the second interconnect in the first direction and connected to one end of each of the fourth cell units respectively, each of the plurality of fourth interconnects having at least one of a width of each of the plurality of fourth interconnects along the second direction being smaller than a width of each of the plurality of third interconnects along the second direction and a thickness of each of the plurality of fourth interconnects along the third direction being smaller than a thickness of each of the plurality of third interconnects along the third direction, the interconnect rerouting unit electrically connecting one of the plurality of fourth interconnects to one of the plurality of first interconnects and electrically connecting one of the plurality of third interconnects to one of the plurality of second interconnects.