Patent ID: 7280426

Claim:
A memory module comprising: a plurality of first terminals for inputting a plurality of command signals from outside of the memory module; a plurality of second terminals for inputting an address from outside of the memory module; a plurality of third terminals for inputting a plurality of data from outside of the memory module; a non-volatile memory; a random access memory for reading data out to outside of the memory module via the plurality of third terminals; a command register into which is written load instruction code, the load instruction code being inputted from outside of the memory module via the plurality of third terminals; and an error correction circuit for checking whether or not data read from the non-volatile memory contains any error and correcting the error when detected, further wherein when the load instruction code is written into the command register, the data stored in the non-volatile memory is transferred from the non-volatile memory to the random access memory via the error correction circuit, and further wherein the random access memory outputs the data after correcting the error by the error correction circuit from the plurality of third terminals when the memory module is accessed to read out data.