Patent ID: 7495290

Claim:
An intermediate state of a semiconductor device comprising: a gate dielectric disposed over a workpiece; a layer of conductive material comprising a thickness of about 30A° or less disposed over and in contact with the gate dielectric, the layer of conductive material comprising metal nitride; a layer of semiconductive material disposed over and in contact with the 30A° thick layer of conductive material, the layer of semiconductive material and the layer of conductive material patterned to define a plurality of gate electrodes; a p-type dopant implanted in the layer of semiconductor material of a portion of said plurality of gate electrodes to form p-channel semiconductor devices; an n-type dopant implanted in the layer of semiconductor material of another portion of said plurality of gate electrodes to form n-channel semiconductor devices; and a source region and a drain region formed in the workpiece proximate the gate dielectric.