Patent ID: 7280407

Claim:
A semiconductor memory device comprising: memory cells each of which has a first MOS transistor with a stacked gate including a floating gate formed on a gate insulating film on a well region formed in the surface of a semiconductor substrate and a control gate formed on an inter-gate insulating film on the floating gate; a memory cell array in which the memory cells are arranged in a matrix; word lines each of which connects commonly the control gates of the first MOS transistors in a same row; a first charge pump circuit which is activated and generates a first voltage in a write operation and erase operation and which supplies the first voltage to either the well region or the word lines; a discharge circuit which, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage; a second charge pump circuit which is activated and generates a second voltage in the write operation and erase operation and which supplies the second voltage to either the well region or the word lines, wherein the first and second voltages are a negative voltage and a positive voltage, respectively, the second charge pump circuit is deactivated after the charge generated by the first charge pump circuit is discharged by the discharge circuit, and the discharge circuit, when the second charge pump circuit is deactivated, discharges the charge generated by the second charge pump circuit to ground or to the power-supply potential, while causing the current to flow to an output node of the second voltage; wherein each of the memory cells includes a second MOS transistor which has a drain connected to the source of the first MOS transistor, the device further includes a select gate line which connects commonly the gates of the second MOS transistors in a same row, the first charge pump circuit supplies the negative voltage to the select gate lines and the well region in the write operation and to the word lines in the erase operation, and the second charge pump circuit supplies the positive voltage to the word line in the write operation and to the well region in the erase operation.