Patent ID: 7393703

Claim:
A method, comprising: on a first wafer having a first arrangement of integrated circuit chips, each integrated circuit chip divided into a second arrangement of regions, measuring a same test device parameter of test devices distributed in different regions of said second arrangement of regions, one or more same regions of all integrated circuit chips of said first wafer including identically designed field effect transistors; and on a second wafer having said first arrangement of integrated circuit chips, each integrated circuit chip divided into said second arrangement of regions, adjusting a same functional device parameter of identically designed field effect transistors within one or more same regions of all integrated circuit chips of said second wafer based on values of said same test device parameter measured on test devices in regions of said integrated circuit chip of said first wafer corresponding to said one or more same regions of said integrated circuit chips of said second wafer by a non-uniform adjustment of physical polysilicon gate widths of said identically designed field effect transistors from region to region within each integrated circuit chip.