Patent ID: 7477043

Claim:
A circuit of an output stage of an LDO voltage regulator implemented with low-voltage devices and still allowing higher voltage levels is comprising: a first low-voltage NMOS pass device having its source connected to its bulk and to an output port of said LDO regulator, its gate controlled by said LDO regulator, and its drain is connected to a means of controllable resistance; and said means of controllable resistance, protecting actively a voltage level at the drain of said NMOS pass device, is implemented between the drain of said first NMOS pass device on one side and on the other side connected to V DD voltage wherein said resistance controlling means comprises a differential amplifier and a second NMOS device, wherein inputs of said amplifier comprise a reference voltage and V DD voltage, the output of said amplifier is connected to the gate of said second NMOS device, the source of said second NMOS device is connected to its bulk and to the drain of said first NMOS pass device and its drain is connected to V DD voltage.