Patent ID: 7484153

Claim:
A method for isolating logic built-in self-test (LBIST) circuitry in a device comprising: providing a plurality of scan chains interposed with functional logic of the device, wherein each of a plurality of functional blocks in the device has a corresponding set of scan chains interposed therewith, and wherein the set of scan chains corresponding to each functional block includes one or more boundary scan chain that is selectively coupled to one or more boundary scan chains of other functional blocks; and selectively coupling or decoupling the boundary scan chains of each functional block with the boundary scan chains of other functional blocks; wherein the boundary scan chains in the processor cores and supporting functional blocks are selectively coupled to the boundary scan chains in other processor cores and supporting functional blocks through AND gates, wherein the coupling the boundary scan chains comprises asserting a control input to the AND gates, wherein the decoupling the boundary scan chains comprises deasserting the control input to the AND gates, and wherein the asserting or the deasserting the control input to each AND gate comprises loading a corresponding value in a control latch, wherein an output of the control latch is coupled to an input of the AND gate.