Patent ID: 8258063

Claim:
A method of manufacturing a polysilicon gate/metal gate electrode/high K dielectric gate stack, comprising the steps of: Step 1) forming an interfacial layer of SiON or SiO 2 on a silicon substrate; Step 2) depositing a high K dielectric film on the interfacial layer; Step 3) performing a rapid thermal anneal of the high K dielectric film; Step 4) depositing a TaN metal gate electrode film on the high K dielectric film; Step 5) depositing a polysilicon gate layer on the TaN metal gate electrode film, and then depositing a hard mask layer; Step 6) patterning a photoresist mask, and performing an anisotropic etching of the hard mask layer by reactive ion etching so as to transfer the pattern of the photoresist mask into the hard mask layer; Step 7) removing the photoresist mask, and etching the polysilicon gate by reactive ion etching with the hard mask as masking layer using a mixed gas of Cl 2 /HBr; and Step 8) etching the TaN metal gate electrode/high K dielectric gate stack by reactive ion etching with the hard mask as masking layer using BCl 3 -based etchant gas, which is anisotropic etching with high selectivity; wherein in Step 8), the BCl 3 etchant is a mixed gas of BCl 3 /Cl 2 /Ar/O 2 , with a flow rate of BCl 3 of about 20-120 sccm, a flow rate of Cl 2 of about 5-30 sccm, a flow rate of O 2 of about 2-15 sccm, and a flow rate of Ar of about 10-60 sccm; an etching power of an upper electrode is about 120-450 W and an etching power of a lower electrode is about 30-200 W; the reaction chamber is maintained at an operating pressure of about 4-15 mTorr; and the temperatures of the reaction chamber and the electrodes are about 50-150° C.