Patent ID: 8275087

Claim:
An apparatus comprising: a communication device comprising a clock recovery module; the communication device being operative as a slave device relative to another communication device that is operative as a master device; the clock recovery module comprising a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device; the clock recovery loop comprising: a primary loop comprising a loop filter and a first frequency error estimator configured to generate a first estimate of error between the master clock frequency and the slave clock frequency; a second frequency error estimator arranged outside of the primary loop and configured to generate a second estimate of error between the master clock frequency and the slave clock frequency; and an accumulator coupled between the second frequency error estimator and the primary loop; wherein the second estimate is controllably injected into the primary loop via the accumulator by combining an output of the accumulator with an output of the loop filter; and wherein the first and second frequency error estimators independently generate the respective first and second estimates by processing arrival timestamps generated in the slave device for respective timing messages received from the master device.