Patent ID: 7110310

Claim:
A RAM store having a shared sense amplifier (SA) structure, in which sense amplifiers (SA) arranged in SA strips between two respective adjacent cell blocks are used by a plurality of bit line pairs from the adjacent cell blocks, and the bit line pairs have respective charge equalization circuits individually associated with them and perform, upon applying a respective precharge control signal, charge equalization between the bit line halves of the respective bit line pairs in a precharge phase. wherein a shorting transistor is arranged in or on a respective sense amplifier (SA) jointly for all bit line pairs that can be connected to the respective sense amplifier, said shorting transistor being provided to connect, at the sense amplifier, the bit line halves of the bit line pairs that are in the precharge phase to one another when the shorting transistor is switched by a separate shorting control signal via a dedicated control line that is separate from the precharge control signal performing the charge equalization between the bitline halves of the respective bitline pairs.