Patent ID: 8656083

Claim:
A system for memory allocation in a computing system, comprising: a volatile memory device; a non-volatile memory device including blocks, each block having addressable physical pages; a memory allocation module stored in the volatile memory device and operable to allocate a physical page address to a system address, wherein the memory allocation module includes: system address rate logic operable to determine a frequency rate for a provided system address, wherein the frequency rate for the provided system address is determined based at least in part on a total number of write operations multiplied by a constant associated with a period for a write operation, plus a total number of read operations multiplied by a period for read operations, plus a total number of erase operations multiplied by an erase operation period in the non-volatile memory device; erase cycle state logic operable to determine an erase cycle state for each block in the non-volatile memory device; address assignment logic that assigns a physical page address to the system address such that the frequency for the provided system address is inversely proportional to the erase cycle state of the block from which the physical page resides, wherein the address assignment logic parses the system address into separate fields to determine whether a cache-line associated with the system address to physical address assignment is included in the non-volatile memory device; and block pooling logic that groups the blocks in two or more allocation pools, wherein each of the two or more allocation pools reflect blocks having different predetermined thresholds of erase cycle states.