Patent ID: 8285944

Claim:
A circuit arrangement for communicating packets of data, comprising: a memory; a write controller coupled to the memory, wherein the write controller is configured to write words of data packets to the memory addressed by a write pointer from a write pointer register, maintain in a write start address register as each data packet is written to the memory a first address that is an address at which a first word of each data packet is stored in the memory, and generate a first signal in response to a first discard signal; wherein for data packets having one word and for data packets having more than one word, the first address of each packet is maintained in the write start address register while writing words of the packet in the memory and updating the write pointer in the write pointer register; a read controller coupled to the write controller and to the memory, wherein the read controller is configured to read words of the data packets from the memory addressed by a read pointer from a read pointer register and temporarily maintain in a read start address register as each data packet is read from the memory a second address that is an address from which the first word of each data packet is read from the memory; wherein for data packets having one word and for data packets having more than one word, the second address of each packet is maintained in the read start address register while reading words of the packet from the memory and updating the read pointer in the read pointer register; wherein the read controller is further configured to compare, in response to the first signal, the first address to the second address, reset the read pointer to the second address in response to the first address being equal to the second address, and not reset the read pointer to the second address in response to the first address being not equal to the second address, and generate a second signal after reset of the read pointer; and wherein the write controller is further configured to reset the write pointer to the first address in response to the second signal from the read controller.