Patent ID: 7590968

Claim:
A method for generating a chip layout based on fabrication process capability, comprising: selecting a minimum required value for a fabrication process capability factor associated with a fabrication process to be performed on a layer sub-region within a chip based on a balance between yield loss of the chip and size of the chip, wherein the fabrication process is characterized by a measurable parameter, the measurable parameter having an associated distribution representing a frequency of occurrence of values of the parameter, the distribution being defined by a mean and a standard deviation, and wherein the fabrication process capability factor represents a minimum fraction of a number of standard deviations that is between the mean of the parameter distribution and either a lower specification limit or an upper specification limit for the fabrication process; determining design rules for the layer sub-region within the chip that will enable the selected minimum required value for the fabrication process capability factor associated with the layer sub-region to be satisfied; generating a layout for the layer sub-region within the chip using the determined design rules associated with the layer sub-region; and recording the generated layout on a computer readable storage medium.