Patent ID: 7035144

Claim:
A flash memory device, in which lower and upper data bits are programmed into memory cells at first and second programming periods, the flash memory device comprising: word lines and bit lines connected to the memory cells; a word line voltage supply circuit connected to the word lines and structured to supply a first word line voltage to the word lines during the first programming period and a second word line voltage to the word lines during the second programming period, the second word line voltage being higher than the first word voltage; and a bit line voltage supply circuit connected to the bit lines and structured to supply, in the first programming period, a first bit line voltage to the bit lines according to a lower data bit to be programmed, structured to read out the programmed lower data bit prior to the second programming period, and structured to supply, in the second programming period, a second bit line voltage to the bit lines according to an upper data bit to be programmed and according to the read lower data bit.