Patent ID: 8557658

Claim:
A method of forming a first and second multi-transistor element comprising: providing a substrate having a first active region and a second active region disposed in the substrate; forming a shallow trench isolation feature in the substrate; forming a floating gate stack adjacent to the isolation feature, the floating gate stack including a first region associated with the first multi-transistor element, a second region associated with the second multi-transistor element, and a notch interposing the first and second regions; forming a control gate stack adjacent to the floating gate stack; forming a common source region associated with the first and second multi-transistor elements, wherein the first multi-transistor element is coupled to the first active region and the second multi-transistor element is coupled to the second active region; forming a first bitline coupled to the first region of the floating gate stack; forming a second bitline coupled to the second region of the floating gate stack; using the first bitline as a read bitline and the second bitline as a program bitline; and forming a wordline adjacent to the floating gate stack and the control gate stack.