Patent ID: 7915734

Claim:
A chip comprising: a silicon substrate; a transistor in or on said silicon substrate; a first copper layer over said silicon substrate; a second copper layer over said first copper layer and said silicon substrate; a dielectric layer between said first and second copper layers; a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers; a first conductive pad over said silicon substrate; a second conductive pad over said silicon substrate; a passivation layer over said first and second copper layers and said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first conductive pad, and said first contact point is at a bottom of said opening, and wherein a second opening in said passivation layer is over a second contact point said second conductive pad, and said second contact point is at a bottom of said opening, wherein said first opening has a width between 0.5 and 20 micrometers; a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first contact point, and a fourth opening in said first polymer layer is over said second contact point, and wherein said first polymer layer has a thickness between 1 and 100 micrometers; and an interconnecting structure on a top surface of said first polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said interconnecting structure, wherein said interconnecting structure comprises a conductive layer on top surface of said first polymer layer and an electroplated copper layer on said conductive layer.