Patent ID: 7453086

Claim:
A thin film transistor panel comprising: a substrate; gate lines formed on the substrate; data lines insulated from the gate lines and intersecting the gate lines; a plurality of thin film transistors connected to the gate lines and the data lines, the thin film transistors each having a drain electrode; a plurality of capacitive coupling electrodes each capacitive coupling electrode being associated with and connected to the drain electrode of the associated thin film transistor; and a plurality of pixel electrodes arranged in a matrix each of the pixel electrodes comprising a first sub-pixel electrode and a second sub-pixel electrode, and each of the pixel electrodes being associated with a pixel area defined by the gate lines and the data lines, wherein the first and second sub-pixel electrodes of each pixel are connected to the drain electrode of the associated thin film transistor, and the second sub-pixel electrode is spaced apart from the first sub-pixel electrode and further wherein the first and second sub-pixel electrodes overlap the capacitive coupling electrodes, wherein the second sub-pixel electrodes have a truncated triangular shape and the truncated shorter end in ones of the second sub-pixel electrodes face in a different direction than the truncated shorter ends of other of the second sub-pixel electrodes.