Patent ID: 7071748

Claim:
In a charge pump clock generating a pump clock signal, a logic circuit executing an algorithm with the following steps: if said pump clock signal is in a first pump clock state for at least a predetermined period of time, switching said pump clock signal from said first pump clock state to a second pump clock state; and if said pump clock signal is in said second pump clock state for at least said predetermined period of time, switching said pump clock signal from said second pump clock state to said first pump clock state; and if at a rising edge of a positive logic pulse a read clock signal changes its state from a first read clock state to a second read clock state, or from said second read clock state to said first read clock state, causing said pump clock signal to change said pump clock signal state at a falling edge of said positive logic pulse unless: {(i) said pump clock signal changed said pump clock signal state at said rising edge of said positive logic pulse; and (ii) said read clock state change at said rising edge of said positive logic pulse is the first one since said most recent pump clock signal state change}.