Patent ID: 7095810

Claim:
A demodulator for demodulating a set of S possible orthogonal modulation codes received serially as binary data, wherein each of said orthogonal modulation codes comprises M binary bits representing an N-bit data symbol and wherein M=2 N , said demodulator comprising: a Logic 00 input detector capable of comparing sequential non-overlapping pairs of said M binary bits of said serially received orthogonal modulation codes to a Logic 00 value and outputting a [+1,+1] signal if a match occurs and outputting a [−1,−1] signal if a match does not occur; a summation circuit comprising S accumulators; a Logic 00 switch array comprising S switches, wherein a Kth one of said S switches in said Logic 00 switch array is capable of coupling an output of said Logic 00 input detector to a first input of a Kth one of said S accumulators; a storage array capable of storing S code masks associated with said S orthogonal modulation codes, wherein each of said S code masks comprises M/2 code mask bits and each of said M/2 code mask bits is associated with a corresponding one of said sequential non-overlapping pairs of said M binary bits in one of said orthogonal modulation codes; and control circuitry capable of synchronously applying the M/2 code mask bits in a Kth one of said S code masks in said storage array as a switch control signal to said Kth switch in said Logic 00 switch array such that a Logic 1 code mask bit in said Kth code mask closes said Kth switch in said Logic 00 switch array whenever said Logic 00 input detector is comparing a sequential non-overlapping pair of said M binary bits equal to 00, thereby connecting the [+1,+1] output signals of said Logic 00 input detector to said first input of said Kth accumulator.