Patent ID: 8266367

Claim:
A two-level flash device comprising: a smart storage switch which comprises: an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping; a high-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity, which is the size of data that is accessible in parallel, and a scattered capacity, which is the size of data that cannot be accessed in parallel, for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels; a virtual storage bridge between the smart storage transaction manager and a NVM controller through a LBA bus; a plurality of NVM controllers, each NVM controller coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped; a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises: NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the low-level mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data.