Patent ID: 7081389

Claim:
A method of manufacturing a semiconductor device, comprising: preparing a semiconductor device having a cell array region and a peripheral circuit region; sequentially forming a gate insulating layer and a gate conductive layer on the semiconductor substrate; forming a word line capping layer on the gate conductive layer; etching the word line capping layer in the peripheral circuit region to expose the gate conductive layer; forming a gate capping layer on the gate conductive layer, the gate capping layer having an etching selectivity ratio different from the word line capping layer; planarizing the gate capping layer to expose the word line capping layer in the cell array region while retaining the gate capping layer in the peripheral circuit region; patterning the word line capping layer, the gate capping layer, and the gate conductive layer to form a plurality of word line patterns in the cell array region and at least one gate pattern in the peripheral circuit region, the word line pattern including a word line and a word line capping layer pattern, the gate pattern including a gate electrode and a gate capping layer pattern; forming gate spacers on side walls of the word line pattern and the gate pattern; sequentially forming a pad interlayer insulating layer and a bit line interlayer insulating layer over a surface of the semiconductor substrate having the gate spacers; and patterning the bit line interlayer insulating layer, the pad interlayer insulating layer, and the gate capping layer pattern to form a cell contact hole penetrating a region between the word line patterns and a peripheral circuit contact hole exposing the gate electrode.