Patent ID: 8369434

Claim:
A data processing apparatus configured to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising: an interleaver configured to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and an address generator configured to generate the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the address generator comprising: a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers, and a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately sixteen thousand, the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of R i ′[ 12 ]=R i-1 ′[ 0 ]⊕ R i-1 ′[ 1 ]⊕ R i-1 ′[ 4 ]⊕ R i-1 ′[ 5 ]⊕ R i-1 ′[ 9 ]⊕ R i-1 ′[ 11 ], and the permutation order forms, with an additional bit, a fourteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R i ′[n] in accordance with a code defined by the table: R′ i bit positions 12 11 10 9 8 7 6 5 4 3 2 1 0 R i bit 8 4 3 2 0 11 1 5 12 10 6 7 9 positions.