Patent ID: 8542538

Claim:
A semiconductor memory device comprising: a memory cell array configured to have a plurality of memory cells arranged in a matrix, each of said plurality of memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3); and a control circuit which controls the potentials of the word line and bit line according to input data and writes data into a memory cell, wherein the control circuit writes data into the memory cell to an a1-valued (a1≦n) threshold voltage in a first write operation, to an a2-valued (a2≦n) threshold voltage in a second write operation, and to an ak-valued (ak≦n) threshold voltage in a k-th write operation (k is a natural number equal to or larger than 2: k≦n), in the first to k-th write operations, raises a program voltage in increments of ΔVpgm, and carries out write operations by repeating a program and verify operation, ΔVpgm in the first to k-th write operations fulfilling the following expression: ΔVpgm in the first write operation>ΔVpgm in the second write operation> . . . >ΔVpgm in the kth write operation.