Patent ID: 8130581

Claim:
A semiconductor memory device comprising: a plurality of pairs of bit lines; a plurality of word lines; a plurality of static memory cells coupled to the plurality of pairs of bit lines and the plurality of word lines so that one memory cell is coupled to one of the plurality of pairs of the bit lines and one word line; a pair of first common lines; a writing amplifier coupled to the pair of first common lines; a plurality of pairs of first selection switches coupled between the plurality of pairs of bit lines and the pair of first common lines so that one of the plurality of pairs of first selection switches is coupled between one of the plurality of pairs of bit lines and the pair of first common lines, respectively; a plurality of pairs of second common lines; a plurality of pairs of second selection switches coupled between the plurality of pairs of bit lines and the plurality of pairs of second common lines so that one of the plurality of pairs of second selection switches is coupled between one of the plurality of pairs of bit lines and the corresponding one of the plurality of pairs of second common lines; and a plurality of sense amplifiers coupled to the plurality of pairs of second common lines, respectively, wherein a quantity of the pairs of bit lines that are coupled to one of the plurality of pairs of second common lines via the pairs of second selection switches is less than a quantity of the pairs of bit lines that are coupled to the pair of first common lines via the pairs of first selection switches.