Patent ID: 7489148

Claim:
A method of providing access to a plurality of unsingulated integrated circuits on a wafer, comprising: providing a first support structure, the first support structure having a first major surface and a second major surface; the first major surface thereof adapted to receive a wafer, and the second major surface thereof adapted to electrically couple to tester pin electronics external to the integrated circuits; disposing a wafer, the wafer having a plurality of unsingulated integrated circuits thereon, on the first major surface of the first support structure; disposing a central portion of a removably attachable, single-sided edge-extended wafer translator over the wafer, and a peripheral portion of the removably attachable, single-sided edge-extended wafer translator on the first surface of the first support structure; and evacuating one or more gases from between the central portion of the removably attachable, single-sided edge-extended wafer translator and the wafer wherein the step of evacuating results in the wafer and the central portion of the removably attachable single-sided edge-extended wafer translator being removably attached to each other.