Patent ID: 8553482

Claim:
An apparatus, comprising: a sense amplifier coupled to receive a differentially-encoded pair of bit line signals from a column of storage cells of an array and further coupled to receive a sense amplifier enable signal that is distinct from a clock signal, wherein a valid value of the pair of bit line signals is encoded with a voltage differential across the pair of bit line signals that is smaller than a voltage difference between a true logic zero and a true logic one; a sense amplifier latch including a latch input, a latch output, and a latch enable signal, wherein the latch input is coupled to receive one or more data output signals from the sense amplifier, wherein during operation, in response to assertion of the latch enable signal, the sense amplifier latch opens to pass a value of the latch input to the latch output, and in response to deassertion of the latch enable signal, the sense amplifier latch closes to store the value of the latch input; a plurality of logic gates that, during operation, detects assertion of one or more input signals and responsively asserts the sense amplifier enable signal; and a self-timed loop circuit coupled to the plurality of logic gates and further coupled to receive the sense amplifier enable signal; wherein during operation, in response to assertion of the sense amplifier enable signal, the sense amplifier is activated to convert the voltage differential across the pair of bit line signals into the one or more data output signals encoded using voltage values corresponding to the true logic zero or the true logic one; wherein the latch enable signal is controlled by the sense amplifier enable signal, such that the sense amplifier latch opens in response to activation of the sense amplifier and closes in response to deactivation of the sense amplifier; and wherein during operation, the self-timed loop circuit detects assertion of the sense amplifier enable signal and, in response, causes the sense amplifier enable signal to deassert, such that assertion of the sense amplifier enable signal is frequency dependent and deassertion of the sense amplifier enable signal is self-timed.