Patent ID: 7245687

Claim:
A phase-locked loop (PLL) device comprising: an interpolator receiving and processing an input signal by an interpolation operation in response to an interpolation timing value to obtain an output signal; a timing error detector in communication with said interpolator for detecting a timing error value of said output signal; a loop filter in communication with said timing error detector for outputting said interpolation timing value to said interpolator in response to said timing error value; and a lock controller for receiving and adjusting said interpolation timing value from said loop filter according to a timing quality of said output signal, and providing said adjusted interpolation timing value for said loop filter to be outputted to said interpolator, said lock controller comprising: a register for storing a backup copy of said interpolation timing value; and a multiplexer set electrically coupled between said register and said loop filter for allowing said backup copy of said interpolation timing value in said register to be updated when said timing quality is in a good condition, and allowing said backup copy of said interpolation timing value to be read by said loop filter when said timing quality is in a bad condition.