Patent ID: 7971118

Claim:
A conversion method for converting a test vector set with respect to a scan circuit, comprising: setting one or more candidate bits which can be a don't care bit and one or more fixed bits which cannot be a don't care bit to identify a don't care bit identifiable as don't care from only the candidate bits of the test vector set, the don't care bit being a logic bit which can be either a logic value 0 or a logic value 1 for achieving a predetermined object; and deciding a logic value for a don't care bit in a test cube to reduce differences in logic values before and after a scan capture when outputting scan cells included in the scan circuit; wherein setting the candidate bits and fixed bits includes: discriminating a bit in which a logic value difference is generated before and after scan capture and a bit in which the logic value difference is not generated before and after scan capture from each other in outputs of scan cells included in the scan circuit in relation to each test vector of the test vector set; setting the bit in which the logic value difference is not generated as the fixed bit; and identifying the candidate bit satisfying predetermined conditions among the bits in which the logic value difference is generated and setting the remaining bits in which the logic value difference is generated failing to be identified as the candidate bit as the fixed bit, and wherein the don't care bit is identified from the candidate bits, while the don't care bit is not identified from the fixed bits.