Patent ID: 8762096

Claim:
A signal analyzer for analyzing a digital modulation signal under test having a digital modulation error detection circuit comprising: a plurality of non-transitory detection blocks configured to provide measured values of symbol data of the digital modulation signal under test; a non-transitory trigger detection block configured to evaluate available shifts between symbol data of the digital modulation signal under test according to the modulation format and the symbol rate of the digital modulation signal under test; a non-transitory symbol timing signal generation block configured to generate first symbol timing signals according to the symbol rate of the digital modulation signal under test; a non-transitory predicted value generation block configured to generate predicted values of the symbol data using the measured values and the available shifts; and a non-transitory comparison block configured to compare the predicted values and corresponding measured values according to the first symbol timing signals to determine whether the comparison result is within or out of an acceptable range, wherein the comparison block is further configured to provide a trigger signal if the comparison result is out of the acceptable range.