Patent ID: 7678680

Claim:
A method for fabricating a semiconductor device, comprising: providing a wafer having a plurality of power semiconductor die, each die including at least one metallic power electrode on a surface thereof each electrode having an outer boundary; forming a blanket barrier layer over said wafer covering at least the entire surfaces of said electrodes of said die; forming a blanket copper seed layer over said blanket barrier layer; forming a photoresist layer over said copper seed layer; removing selected portions of said photoresist layer to create a plurality of openings, each opening exposing at least a portion of said blanket copper seed layer that is disposed over a respective electrode; forming a copper body in each opening over each exposed portion of said blanket copper seed layer, wherein each copper body spreads over and includes an outer boundary contained in an outer boundary of a respective electrode; forming a solderable body over each copper body; removing the remainder of said photoresist layer; removing portions of said copper seed layer and said barrier layer not under said copper body; and applying and patterning a passivation body to include an opening over said solderable body, wherein said metallic power electrode is comprised of a metal different from said copper body.