Patent ID: 7943508

Claim:
A method of manufacturing a semiconductor device, comprising: sequentially forming a first interlayer dielectric layer and a second interlayer dielectric layer on a base interlayer dielectric layer having a metal interconnection; forming a first photoresist pattern for forming a trench on the second interlayer dielectric layer; forming a dummy trench by etching the second interlayer dielectric layer using the first photoresist pattern as an etching mask; filling the dummy trench with an insulating layer similar to the material of the first interlayer dielectric layer; forming a second photoresist pattern for forming a contact hole on the insulating layer; forming the contact hole by etching the insulating layer and the first interlayer dielectric layer using the second photoresist pattern as an etching mask; removing the second photoresist pattern; and etching the insulating layer to form a trench without using a third photoresist pattern.