Patent ID: 6940752

Claim:
A non-volatile semiconductor memory device comprising: an electrically erasable and programmable non-volatile semiconductor memory cell having a control gate; a bit line connected to a first terminal of the memory cell; a source line connected to a second terminal of the memory cell; a sense amplifier connected to the bit line; an erase circuit configured to erase data of the memory cell; an erase verify circuit configured to read a status of the memory cell by the sense amplifier through the bit line after the erase circuit erases the data of the memory cell; and a soft-programming circuit configured to perform soft-programming with respect to the erased memory cell by controlling a voltage of the bit line in accordance with the read status of the memory cell, wherein the semiconductor memory cell forms a NAND type memory cell by being connected to other semiconductor memory cells in series, a first terminal of the NAND type memory cell is connected to the bit line and a second terminal of the NAND type memory cell is connected to the source line, the erase verify circuit repeatedly applies a selection voltage to the control gate of one of the semiconductor memory cells of the NAND type memory cell and reads out the status of the selected semiconductor memory cell by the sense amplifier through the bit line, and the soft-programming circuit performs the soft-programming by applying a predetermined soft-programming voltage to the control gates of the semiconductor memory cells of the NAND type memory cell.