Patent ID: 7616040

Claim:
A flip-flop comprising: a clock supply circuit configured to output a clock signal alternating between a first state and a second state when a sleep signal is inactive, and to fix said clock signal in said first state when said sleep signal is active; a first holding circuit configured to fetch an input signal while said clock signal is indicating said first state, and to hold said input signal while said clock signal is indicating said second state; a second holding circuit configured to fetch a first signal output by said first holding circuit while said clock signal is indicating said second state, and to hold said first signal while said clock signal is indicating said first state; an input switching circuit configured to supply as said input signal a second signal output by said second holding circuit when a hold signal is active, and to supply an external signal as said input signal when said hold signal is inactive; and a power supply control circuit configured to supply power to said first holding circuit and said input switching circuit when a power supply control signal is active, and not to supply power to said first holding circuit and said input switching circuit when said power supply control signal is inactive.