Patent ID: 8503238

Claim:
A system for error recovery for flash memory, comprising: a receiver configured to: receive an indication associated with an error-correcting code (ECC) decoding failure related to data stored on a page of flash memory; identify a logical type of the page, including by determining a bit type associated with the page; adjust a threshold based at least in part on the logical type, including by: in the event it is determined the bit type associated with the page is a most significant bit (MSB), adjusting one or more MSB read thresholds; and in the event it is determined the bit type associated with the page is a least significant bit (LSB), adjusting one or more LSB read thresholds; and read the page using the adjusted threshold, including by: in the event it is determined the bit type associated with the page is a MSB, reading the page using the one or more adjusted MSB read thresholds; and in the event it is determined the bit type associated with the page is a LSB, reading the page using the one or more adjusted LSB read thresholds; and an interface coupled to the receiver.