Patent ID: 8637915

Claim:
A nonvolatile semiconductor memory comprising: first and second memory cells each having a stack gate structure provided with a floating gate, a control gate, and an insulator sandwiched between the floating gate and the control gate, and being adjacent to each other in an extending direction of the control gate, wherein each of the floating gates of the first and second memory cells comprises a first film, and a second film arranged on the first film, the second film having a width narrower than that of the first film in the extending direction of the control gate; the first film is arranged between element isolation insulating layers, each of the element isolation insulating layers having an upper surface lower than that of the first film; the insulator has a first layer arranged on the floating gate and a second layer arranged above the first layer, the second layer having a dielectric constant higher than dielectric constants of the first layer and the element isolation insulating layers; a first space between the first films of the first and second memory cells is filled with one of the element isolation insulating layers and only the first layer of the insulator arranged on the one of the element isolation insulating layers; and a second space between the second films of the first and second memory cells includes the first layer and the second layer.