Patent ID: 8023612

Claim:
An apparatus, comprising: m dynamic entry shift registers, with each of said m dynamic entry shift registers configured to receive a different signal applied as an input signal and to generate a different output signal corresponding to its input signal; wherein m is an integer greater than one; wherein said m dynamic entry shift registers are configured to generate an aligned m said output signals of said m dynamic entry shift registers, with at least a first dynamic shift register of said m dynamic entry shift registers in a configuration to cause a different delay through the first dynamic shift register than at least one other of said m dynamic entry shift registers; and control circuitry configured to align said different signals based on detected one or more delimiters included in each of said different signals said applied to said m dynamic entry shift registers; wherein said aligning includes adjusting the delay through a particular one or more of said m dynamic entry shift registers for which said one or more delimiters are received in a particular one or more of said different signals corresponding to the particular one or more of said m dynamic entry shift registers at a different bit time than in a different particular one or more of said different signals corresponding to a different particular one or more of said m dynamic entry shift registers; wherein each particular dynamic shift register of said m dynamic entry shift registers is configured to receive a particular input signal of said m different signals and to produce a particular output signal of the aligned m said output signals; wherein the particular output signal is a same serial sequence of bits delayed by one or more bit times.