Patent ID: 7538591

Claim:
A phase frequency detector comprising: an up-signal generating unit including a first stage and a second stage, the first stage generating a first control signal in accordance with an internal clock signal and a reset signal, the second stage generating a first output signal synchronized with a front edge of the internal clock signal in accordance with the internal clock signal, an inverted signal of the reset signal, and the first control signal; a down-signal generating unit including a third stage and a fourth stage, the third stage generating a second control signal in accordance with an external clock signal and the reset signal, the fourth stage generating a second output signal synchronized with a front edge of the external clock signal in accordance with the external clock signal, the inverted signal of the reset signal, and the second control signal; a first buffer receiving and inverting the first output signal to output an up-signal; a second buffer receiving and inverting the second output signal to output a down-signal; and a reset signal generator receiving the first and second output signals to output the reset signal that deactivates the up-signal and the down-signal, the reset signal being activated when the up-signal and the down-signal are simultaneously activated, wherein the first control signal is activated when the internal clock signal is in a deactivation state, and is deactivated when the reset signal and the internal clock signal are simultaneously activated, and wherein the first output signal is activated when the first control signal is in a deactivation state, and is deactivated when the internal clock signal is activated.