Patent ID: 7391250

Claim:
A data retention cell for preserving an output data signal in a power-saving mode comprising: an input control circuit having a first input port for receiving an input data signal, a second input port for receiving a retention signal, a third input port for receiving a clock, a fourth input port for receiving a feedback signal, a first output port for outputting an internal input data signal, and a second output port for outputting an internal clock, the input control circuit comprising a delay unit, the delay unit having an input port coupled to the second input port of the input control circuit for receiving the retention signal and an output port; and a master-slave flip-flop having a first input port coupled to the first output port of the input control circuit for receiving the internal input data signal, a second input port coupled to the second output port of the input control circuit for receiving the internal clock, a first output port for outputting the output data signal, and a second output port for outputting the feedback signal, the master-slave flip-flop comprising a master latch unit having an input port and an output port, and a slave latch unit having an input port and an output port, wherein the slave latch unit is coupled to be powered between a real supply voltage and a real ground voltage and the master latch unit is coupled to be powered by a virtual power.