Patent ID: 7924605

Claim:
A semiconductor memory device, comprising: a memory cell array comprising a plurality of sub arrays, each sub array comprising a plurality of memory cells, the memory cell comprising a pair of storage nodes that are complementary to each other; a first bit-line connected to one storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays; a second bit-line connected to the other storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays; a first read circuit provided in each of the sub arrays, the first read circuit having an input end connected to the second bit-line and an output end connected to the first bit-line, and a second read circuit having an input end connected to the first bit-line and an output, end for outputting data read from the memory cell, wherein the first bit-line is a bit-line connected in common to the plurality of the sub arrays, the second bit-line is provided for each of the sub arrays, the first read circuit transfers data to the first bit-line, the data being read from the memory cell through the second bit-line, and the second read circuit outputs data, the data being read from the memory cell through the first bit-line.