Patent ID: 6985001

Claim:
A process of testing functional combinational logic in an integrated circuit having distributor circuits, collector circuits, a certain number of scan paths connected between the distributor circuits and the collector circuits, each scan path including functional registers that can be configured into scan registers, and a controller controlling operation of the distributor circuits, the collector circuits, and the scan paths, comprising: A. receiving a start test signal; B. configuring the functional circuitry into a test mode; C. capturing response data outputs from all parallel scan paths into the collector circuits; D. shifting data in the distributor circuits and collector circuits the certain number of times to load stimulus data into the distributor circuits and unload response data from the collector circuits; E. shifting data in the scan paths one time to load the scan paths with one bit of test stimulus data from the distributor circuits; F. testing if the scan paths have filled with the test stimulus pattern, including: i. repeating the process from step C if they have not filled with the test stimulus pattern; or ii. proceeding with the next step if they have filled with the test stimulus pattern; and G. testing for receipt of an end of test signal, including: i. if the end of test signal has not been received, then capturing response pattern data from the combinational logic into the scan paths and repeating the process from step C; or ii. if the end of test signal has been received, then configuring the functional circuitry into a normal mode.