Patent ID: 8391046

Claim:
A memory cell array in which a plurality of memory cells are arranged in an array, the memory cell array comprising: a plurality of word lines respectively connected to the plurality of memory cells; a plurality of first bit lines respectively connected to the plurality of memory cells; and a plurality of second bit lines respectively connected to the plurality of memory cells, wherein each of the memory cells includes: a metal-oxide semiconductor (MOS) transistor; and a switching element which is formed inside a contact hole including a first electrode connected to a first diffusion layer of the MOS transistor, wherein the switching element includes: a first conductive layer; a second conductive layer provided above the first conductive layer; and a gap having a size of nanometer order which is formed between the first conductive layer and the second conductive layer, and in which gap a phenomenon that a resistance value is changed by application of a predetermined voltage between the first conductive layer and the second conductive layer occurs, wherein each of the word lines is connected to a gate electrode of the MOS transistor, wherein each of the first bit lines is connected to a second electrode connected to a second diffusion layer of the MOS transistor, wherein each of the second bit lines is connected to the second conductive layer, and wherein data is written in one or more selected memory cells among the memory cells by supplying a write voltage to one or more of the first bit lines connected to the one or more selected memory cells and specifying one or more of the word lines connected to the one or more selected memory cells, and data is read from one or more selected memory cells among the memory cells by supplying a read voltage to one or more of the first bit lines connected to the one or more selected memory cells and specifying one or more of the word lines connected to the one or more selected memory cells.