Patent ID: 7054986

Claim:
A programmable buffer circuit for interfacing a CPU to a plurality of channel interfaces, comprising: a single dual port memory having a first port coupled to a CPU data bus and a second port coupled to a channel data bus that serves said plurality of channel interfaces; an arbitrator for arbitrating access to said dual port memory by individual ones of said channel interfaces over said channel data bus for selectively storing data in and reading data from said single dual port memory; an address generator for generating dual port memory addresses for selectively reading data from and writing data to said single dual port memory using said CPU data bus and said channel data bus; and an allocator and control unit programmable by said CPU for specifying individual ones of buffer locations and buffer sizes within said single dual port memory for individual ones of said channel interfaces, and for enabling individual ones of said buffers, said allocator having outputs coupled to said address generator for controlling the generation of addresses thereby depending on which channel interface is currently selected for access to said single dual port memory, wherein in a first case said control unit operates individual ones of channel buffers in a block access mode of operation using a set of channel registers and in a second case said control unit operates said individual ones of channel buffers in a first in/first out (FIFO) access mode of operation using said same set of channel registers.