Patent ID: 7631281

Claim:
A method comprising: using a processor to perform steps of: providing MOS varactor including a gate, a source, and a drain formed over a p-type semiconductor substrate, calculating a first port gate impedance Z A , a second port bulk impedance Z B and a substrate impedance Z C in a measured s-parameter using a first model equation Re ( Z A )= Re ( Z 11 −Z 12 )= R gate and a second model equation Im ⁡ ( Z A ) = Im ⁡ ( Z 11 - Z 12 ) = ω ⁢ ⁢ L gate - 1 ω ⁢ ⁢ C var , where L gate represents the overall inductance of the first port via and the gate, R gate represents a unit cell via/contact resistance of the first port and the gate, and C var is formed of Cgate and C par , where C gate represents a variable capacity of a MOS-type variable capacitance and C par represents a parasitic capacitance of the varactor, parameters Z 11 and Z 12 are values obtained by transforming the measured s-parameter, and ω is a constant.