Patent ID: 7500171

Claim:
A memory circuit comprising: a data storage section for storing a plurality of data sets and a plurality of redundant data sets, which are used for error correction for the data sets; and an error correction section for performing at least error detection for the data sets in the data storage section by using the redundant data sets, when the memory circuit is not accessed from outside for data input or output, and outputting at least result of the error detection as an error detection signal, wherein when the memory circuit is accessed so as to output a designated one of the stored data sets, the designated data set is outputted without being subjected to the error detection by the error correction section, wherein the error correction section includes: an output data error check and correct circuit for performing error correction for the data set read from the data storage section by using a corresponding one of the redundant data sets and outputting the obtained error-corrected data and the error detection signal; a data selection circuit for selecting the error-corrected data when the error detection signal indicates detection of an error, and, in other situations, selecting data input from outside, and outputting the selected data to the data storage section; and a coding circuit for generating, based on the data output from the data selection circuit, a redundant data set to be used for error correction for that data and outputting the generated redundant data set to the data storage section, wherein the data storage section includes: a data memory cell array for storing the data sets; a redundant data memory cell array for storing the redundant data sets; a control circuit for outputting an internal address signal, which is used to access the data memory cell array and the redundant data memory cell array; and an address decoder for decoding the internal address signal and supplying the decoded signal to the data memory cell array and the redundant data memory cell array, wherein the control circuit includes an address selector for selecting an error correction internal address signal, generated cyclically for access to the data memory cell array and the redundant data memory cell array, or an external address signal input from outside, latching and then outputting the selected signal as the internal address signal.