Patent ID: 6883071

Claim:
A system for evaluating scalable symmetric multiple processor cache coherency protocols and algorithms, the system comprising: a scalable symmetric multiple processor computer system, wherein the scalable symmetric multiple processor computer system comprises: a central electronics complex (CEC), one or more first buses connected to the CEC, one or more first processor slots connected to the one or more first buses, and a memory; an application specific integrated circuit (ASIC) replacing a processor in each of the one or more first processor slots of the scalable symmetric multiple processor computer system; a first memory cache unit associated with each ASIC; one or more second buses connected to each ASIC; one or more second processors connected to each second bus; and a second memory cache unit associated with each second processor, wherein the memory, the first memory cache unit, and the second memory cache unit each comprise one or more multiple-byte cache lines; and wherein one byte of each of the multiple-byte cache lines is reserved for access by one of the one or more second processors.