Patent ID: 8923473

Claim:
A driver circuit, comprising: a signal processing circuit, including: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, the third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal; and a shift register; wherein the first node becomes active in a case where the first input terminal becomes active; the second node becomes active in a case where the second input terminal becomes active; the output terminal is connected to the first power supply via the resistor; the first input terminal of the signal processing circuit receives a signal which is supplied to all stages of the shift register in common; the second input terminal of the signal processing circuit receives a signal which is supplied to a predetermined stage(s) of the shift register; a signal obtained from the output terminal of the signal processing circuit is supplied to all of the stages of the shift register; the shift register includes a flip-flop in each of the stages of the shift register; the flip-flop includes (i) a first output section which (a) includes a bootstrap capacitor and (b) is connected to a first clock signal terminal, (ii) a second output section which is connected to the first power supply, (iii) a first input section which charges the bootstrap capacitor, (iv) a discharge section which discharges the bootstrap capacitor, (v) a second input section which is connected to the second output section, and (vi) a reset section which (a) is connected to a second clock signal terminal and (b) controls the discharge section and the second output section; and the first output section is controlled by use of a first initialization signal; the first input section is controlled by use of a second initialization signal; the discharge section and the second output section are controlled by use of a third initialization signal; and the third initialization signal is obtained from the output terminal of the signal processing circuit in such a manner that (A) the first initialization signal is supplied to the first input terminal of the signal processing circuit and (B) a start pulse, which defines timing that the shift register starts carrying out shifting, is supplied to the second input terminal of the signal processing circuit.