Patent ID: 8207580

Claim:
A power integrated circuit (IC) device comprising: a substrate of a first conductivity type; a lateral high-voltage field-effect transistor (HVFET), which comprises: a first well region disposed in the substrate, the first well region being of a second conductivity type opposite to the first conductivity, the first well region comprising an extended drain of the lateral HVFET; a first drain region of the second conductivity type disposed in the first well region; a first body region of the first conductivity type disposed in the substrate, the first body region having first and second lateral edges, the second lateral edge adjoining the first well region; a first source region of the second conductivity type disposed within the first body region near the second lateral edge; a first insulated gate disposed over the substrate, the first insulated gate extending laterally from the second lateral edge to the first source region; a first source electrode electrically connected to the first source region; a drain electrode electrically connected to the first drain region; a sense FET disposed adjacent the lateral HVFET, the sense FET comprising: a second well region of the second conductivity type disposed in the substrate, the second well region comprising an extended drain of the sense FET; a second drain region of the second conductivity type disposed in the second well region, the drain electrode being electrically connected to the second drain region; a second body region of the first conductivity type disposed in the substrate, the first body region having third and fourth lateral edges, the third lateral edge adjoining the second well region; a second source region of the second conductivity type disposed within the second body region near the third lateral edge; a second insulated gate disposed over the substrate, the second insulated gate extending laterally from the third lateral edge to the second source region; a second source electrode electrically connected to the second source region; a third well region of the second conductivity type laterally disposed in an area of the substrate between the first and second body regions, a sense resistor being formed between first and second spaced-apart contact regions in the third well region, the first source electrode being electrically connected to the first contact region and the second source electrode being electrically connected to the second contact region, wherein when the lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.