Patent ID: 6851079

Claim:
A circuit comprising: a first pad circuit configured to transfer a first data signal in response to a pad control signal; a second pad circuit configured to generate a second data signal from an input signal in response to said pad control signal; a core logic configured to (i) exchange said first data signal with said first pad circuit, (ii) receive said second data signal and (iii) generate a control signal; a first cell configured to (i) transfer said first data signal between said first pad circuit and said core logic and (ii) swap said first data signal and a test signal; a second cell configured to (i) transfer said second data signal from said second pad circuit to said core logic and (ii) swap said second data signal and said test signal; and a test circuit configured to (i) exchange said test data signal with said first cell and said second cell, (ii) store a test control signal and (iii) multiplex said test control signal and said control signal to generate said pad control signal.