Patent ID: 8842688

Claim:
An apparatus comprising: a midplane circuit board comprising an uplink card connector receiver disposed on a first side and a line card connector receiver disposed on a second side that is opposite the first side; an uplink card comprising a first uplink card connector and a second uplink card connector, the first uplink card connector disposed at least adjacently to a first uplink card edge and the second uplink card connector disposed at least adjacently to a second uplink card edge that is disposed oppositely to the first uplink card edge, the uplink card connecting to the midplane circuit board such that the first uplink card connector interfaces with the uplink card connector receiver with the uplink card disposed orthogonally to the midplane circuit board; a line card comprising a first line card connector disposed at least adjacently to a first line card edge and a second line card connector disposed at least adjacently to a second line card edge that is disposed oppositely to the first line card edge, the line card connecting to the midplane circuit board such that the first line card connector interfaces with the line card connector receiver with the line card disposed orthogonally to both of the midplane circuit board and the uplink card; and a central processing unit disposed on the midplane circuit board; and at least one memory storing instructions that, when executed by the central processing unit, cause the central processing unit to perform operations comprising: encapsulating each segment in a sequence of 64 byte segments into a separate Ethernet extension protocol frame, the sequence of 64 byte segments resulting from breaking up a Ethernet frame received from a switch port on the line card or the uplink card; assigning a same virtual link identification to all Ethernet extension protocol frames originating from the switch port; and passing the Ethernet extension protocol frames from the central processing unit to a destination switch port.