Patent ID: 6924683

Claim:
An integrated flip-flop device, comprising: an output stage having a pull-up path and pull-down path therein that are rendered conductive in response to leading edges of pull-up and pull-down control pulses, respectively; a sense amplifier configured to generate first and second data output signals in response to at least one data input signal and a clock signal; and an edge acceleration stage configured to generate the pull-up and pull-down control pulses in response to the first and second data output signals, respectively, said edge acceleration stage comprising: a pull-up buffer having an even number of inverters therein that are connected in series and alternatingly skewed to accelerate the leading edge of the pull-up control pulse relative to a trailing edge of the pull-up control pulse, wherein a first of the even number of inverters is skewed in favor of its pull-up strength and a last of the even number of inverters is skewed in favor of its pull-down strength; and a pull-down buffer having an odd number of inverters therein that are skewed to accelerate the leading edge of the pull-down control pulse relative to a trailing edge of the pull-down control pulse.