Patent ID: 7352064

Claim:
A method of forming a metal line critical dimension in a single damascene process on a semiconductor substrate, the method comprising the steps of: providing the semiconductor substrate including at least one metal level and at least one substrate dielectric layer thereover, wherein the at least one substrate dielectric layer includes a hardmask layer over a hydrogenated silicon oxy-carbide (SiCOH) layer; forming a multiple layer resist scheme including a first layer of a first type material over the substrate, a second layer of a second type material over the first layer, and a third layer of a third type material over the second layer, wherein the first layer includes a planarizing layer, the second layer includes a dielectric layer, and the third layer includes a photoresist, and the first, second, and third types of materials alternate between organic and inorganic material; patterning the third layer for the metal line critical dimension; and sequentially etching to form the metal line critical dimension using a different tailored etch recipe for each of the first, second and third layer, and employing different process conditions for each etching.