Patent ID: 8560881

Claim:
A controller for use in a solid state storage system including a plurality of FLASH memory devices, the controller comprising: (a) a buffer adapted to store information reflecting blocks of memory within the FLASH memory devices that were previously used to store data and that are available for storage of different data; (b) block stripe assembly circuitry for assembling block stripes using the information contained in the buffer, each block stripe comprising three or more blocks, each block corresponding to a group of memory locations within a given FLASH memory device, each block within a given block stripe being located within a FLASH memory device different from the FLASH memory devices in which the other blocks in the block stripe are located, wherein the block stripe assembly circuitry determines the number of blocks to be included in each assembled block stripe based on the information in the buffer such that the number of blocks in a first block stripe is different from the number of blocks in a second block stripe; (c) data protection circuitry for generating data protection information using a first group of data items; (d) circuitry for associating each data item in the first group of data items with a memory location in a block of a first block stripe, each data item being associated with a memory location in a different block of the first block stripe from other data items, and for associating the data protection information generated using the first group of data items with a memory location in a block within the first block stripe that is different from the blocks used in storing the first group of data items; and (e) auxiliary data protection circuitry for generating auxiliary data protection information using data items associated with memory locations in the same block for each block within the first block stripe.