Patent ID: 8604532

Claim:
A computing apparatus, comprising: a memory; an input output device; and at least one processor, coupled to said memory and said input output device and operative to process information, at least some of said information being stored in said memory; wherein at least a portion of said memory in turn comprises: a plurality of bit line structures; a plurality of word line structures; one or more dynamic random access memory cells, wherein each of said one or more dynamic random access memory cells is operatively coupled to one of said plurality of bit line structures and one of said plurality of word line structures and wherein each of said one or more dynamic random access memory cells comprises: a capacitive storage device, said capacitive storage device comprising a gated diode having a first gate stack, said first gate stack comprising a first high-K dielectric, wherein said first high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide; and a write access transistor, said write access transistor being operatively coupled to said capacitive storage device and having a second gate stack, said second gate stack comprising a second high-K dielectric, wherein said second high-K dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide.