Patent ID: 7925945

Claim:
A scan circuit comprising: A. a functional circuit formed on the semiconductor substrate of an integrated circuit, the functional circuit including logic circuits to be tested; B. scan path circuitry having plural scan paths, each scan path being formed of serially connected scan cells, each scan path having leads connected to the logic circuits to carry stimulus signals to the logic circuits and to receive response signals from the logic circuits, each scan path having a serial data input lead and a serial data output lead, each scan path being organized in at least first and second selectable and separate scan path parts, each scan path part having a serial input connected to the serial data input lead of that scan path, a serial output lead selectively coupled to the serial data output lead of that scan path, and a separate set of scan path part control input leads; C. test data generator circuitry having control inputs and a serial data output connected to the serial data input lead of each scan path; D. test data compactor circuitry having control inputs and a serial data input connected to the serial data output lead of each scan path; E. controller circuitry having control outputs; and F. adaptor circuitry having control inputs connected with the control output leads of the controller circuitry, the adaptor circuitry having first control outputs connected with the control input leads of the first scan path parts and second control outputs connected with the control input leads of the second scan path parts.