Patent ID: 7618886

Claim:
A semiconductor device manufacturing method comprising: arranging on a base plate a plurality of semiconductor construction assemblies in which a plurality of conductors having pads are formed on a semiconductor substrate, so as to space apart the semiconductor construction assemblies from each other; forming an insulating layer on an entire upper surface of the base plate including the plurality of semiconductor construction assemblies; forming, on an upper surface of the insulating layer, upper conductors which have connection pads and are connected to corresponding pads of the conductors of the semiconductor construction assemblies, so as to arrange at least one of the upper conductors on the insulating layer formed between the semiconductor construction assemblies; and cutting the insulating layer between the semiconductor construction assemblies to obtain a plurality of semiconductor devices each having at least one semiconductor construction assembly in which the connection pad of at least one of the upper conductors is formed on the insulating layer in a region outside the semiconductor construction assembly; wherein arranging the semiconductor construction assemblies on the base plate so as to space apart the semiconductor construction assemblies from each other includes arranging a buried member between the semiconductor construction assemblies.