Patent ID: 7685331

Claim:
A direct memory access (DMA) controller for transmitting data between a first device and a second device, the DMA controller comprising: a central unit; a logic address buffer caching a link-list of cluster addresses obtained from a file allocated table (FAT) in a nonvolatile memory; a divide unit dividing the link-list of cluster addresses into a plurality of sub-link-lists of cluster addresses according two requirements each of the sub-link-lists of cluster addresses being continuous and a length of the sub-link-lists of the cluster addresses being less than a maximum allowed cluster number in length for a corresponding DMA transmission; and an interrupt controller to receive an interrupt request with priority level information from the first device to have the DMA transmission with the second device and to decide which DMA channel is going to be served depending on the priority level of the interrupt request; wherein the central unit is caused to configure the DMA transmission between the first and second devices into a number of batches of sub-DMA transmissions, each of the batches corresponding to one of the sub-link-lists of cluster addresses, as a result, the batches of sub DMA transmissions according to the continuous sub-link-lists of cluster addresses proceed without causing impact on a CPU in the source device.