Patent ID: 6933610

Claim:
A method of bonding a semiconductor die without an ESD circuit and a separate ESD circuit to an external lead, said method comprising: bonding said external lead to said separate ESD circuit; then bonding said separate ESD circuit to said semiconductor die; packaging said die and said circuit in a single package, wherein said external lead is bonded to said ESD circuit and to said semiconductor die coupling the package to a chip carrier, said carrier having a first surface having said external lead, and a second surface opposite said first surface and an aperture between said first surface and said second surface said semiconductor die having a mounting surface with a mounting pad thereon; said mounting surface facing said second surface with said mounting pad in said aperture; said ESD circuit on said mounting surface in said aperture; wherein said external lead is bonded to said ESD circuit in said aperture and to said mounting pad in said aperture; and wherein said semiconductor die is a memory die, said die being substantially rectilinear in share with a plurality of rows having a plurality of mounting pads thereon substantially in the middle of said rectilinear shape.