Patent ID: 7955897

Claim:
A method for manufacturing chip structures, comprising the steps of: providing a wafer, the wafer having an active surface and a back surface opposing to the active surface, a plurality of longitudinal saw streets and a plurality of traverse saw streets defined on the back surface of the wafer, a plurality of first longitudinal areas and a plurality of first traverse areas defined on the back surface of the wafer and respectively along the longitudinal saw streets and traverse saw streets, the widths of the first longitudinal areas and first traverse areas are respectively greater than the widths of the longitudinal saw streets and traverse saw streets, a second area defined between each two adjacent first longitudinal areas and each two adjacent first traverse areas, a plurality of third areas defined on the each second area and separated from each other; forming a plurality of first recesses on the first longitudinal areas and first traverse areas; forming a plurality of second recesses on the second areas except for the third areas, the second recesses in connection with the first recesses; and singulating the wafer along the longitudinal and traverse saw streets.