Patent ID: 7118955

Claim:
A method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate, which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor having the steps of: a) providing the gate stacks next to one another on the semiconductor substrate provided with a gate dielectric, the gate stacks having a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, in particular a tungsten silicide, and an upper third layer made of silicon nitride; b) forming a sidewall oxide on uncovered sidewalls of the first and second layers of the gate stacks; c) removing at least partly the sidewall oxide on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor; and e) forming silicon nitride sidewall spacers on the gate stacks.