Patent ID: 8516496

Claim:
An electronic device, comprising: a processor configured to execute a first thread and a second thread; a memory coupled to the processor and configured to store a first stack used by the first thread, wherein the processor is further configured to switch from execution of the first thread to execution of the second thread by halting the first thread at a switch point; and executing a minimum context push instruction comprised in a first instruction set of the processor, wherein execution of the minimum context push instruction pushes a minimum context of the first thread onto the first stack, wherein the minimum context comprises at least a program counter and a status register; and wherein the memory is further configured to store a second stack used by the second thread, and the processor is further configured to switch by executing a minimum context POP instruction comprised in the first instruction set of the processor, wherein execution of the minimum context pop instruction pop a minimum context of the second thread from the second stack.