Patent ID: 8823419

Claim:
A ping pong comparator voltage monitoring circuit, comprising: a first comparator having a first input connected to a voltage Vin to be monitored, a second input connected to a first node, and an output which toggles from a first state to a second state when Vin increases above the voltage applied to said first comparator's second input and toggles from said second state to said first state when Vin falls below the voltage applied to said first comparator's second input; a second comparator having a first input connected to said voltage Vin, a second input connected to a second node, and an output which toggles from a first state to a second state when Vin increases above the voltage applied to said second comparator's second input and toggles from said second state to said first state when Vin falls below the voltage applied to said second comparator's second input; a multiplexer connected to receive the outputs of said first and second comparators at first and second inputs, respectively, and to receive a periodic control signal at a ‘select’ input, said multiplexer arranged to alternately couple the voltage applied to said first and second inputs to an output in response to said periodic control signal, said multiplexer output being the output of said voltage monitoring circuit; a first reference voltage source which produces a voltage V ref1 at a third node which is referenced to a circuit common point; a second reference voltage source which produces a voltage V ref2 at a fourth node which is referenced to said voltage V ref1 such that the voltage at said fourth node is given by V ref1 +V ref2 ; a first hysteresis voltage source which produces a voltage hyst 1 and is arranged to be switchably connected between said third node and said first node; and a second hysteresis voltage source which produces a voltage hyst 2 and is arranged to be switchably connected between said fourth node and said second node; said voltage monitoring circuit arranged such that said first and second hysteresis voltage sources are switched in such that the voltage at said first node is V ref1 +hyst 1 and the voltage at said second node is V ref1 +V ref2 +hyst 2 when said multiplexer output has toggled from said first state to said second state due to a rising value of Vin, and such that the voltage at said first node is V ref1 and the voltage at said second node is V ref1 +V ref2 when said multiplexer output has toggled from said second state to said first state due to a falling value of Vin.