Patent ID: 7369423

Claim:
A nonvolatile memory device using a hybrid switch cell, comprising: a plurality of hybrid switch cell arrays each having a hierarchical bit line structure including a plurality of sub bit lines connected to one of a plurality of main bit lines, each hybrid switch cell array including a sub cell array having a plurality of unit hybrid switch cells arranged in row and column directions between a word line and a sub bit line, wherein a voltage of the sub bit line induced by cell data is converted into current so that a sensing voltage of a main bit line is induced; a plurality of word line driving units for selectively driving the word lines of the plurality of hybrid switch cell arrays; and a plurality of sense amplifiers for sensing and amplifying data applied from the plurality of hybrid switch cell arrays, wherein each of the unit hybrid switch cells comprises a nonvolatile ferroelectric capacitor whose one terminal is connected to the word line, and a hybrid switch which is connected between the other terminal of the nonvolatile ferroelectric capacitor and the sub bit line and is selectively switched depending on a voltage applied to the word line and the sub bit lines, wherein the hybrid switch comprises: a PN diode switch connected in a forward direction between the other terminal of the nonvolatile ferroelectric capacitor and the sub bit line, and a PNPN diode switch connected in a backward direction between the other terminal of the nonvolatile ferroelectric capacitor and the sub bit line.