Patent ID: 7764110

Claim:
An internal voltage generating circuit of a semiconductor device, comprising: a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level; and a second voltage driver including: a frequency detecting unit configured to receive and detect a frequency of an external clock and generate a periodic driving control signal having a predefined active pulse width in each period of periods of the periodic driving control signal, wherein the periods of the periodic driving control signal vary in response to the frequency of the external clock and the predefined activation pulse width remains the same in response to variations in the frequency of the external clock, the frequency detecting unit including a buffer configured to buffer the external clock in response to an operation control signal, a frequency divider configured to divide an output clock of the buffer by a predefined multiple, and a detection pulse generator configured to generate the periodic driving control signal having the predefined activation pulse width at each edge of a clock output from the frequency divider; and a driving unit connected to the internal voltage terminal and configured to pull up the internal voltage terminal to the target level in response to the periodic driving control signal.