Patent ID: 7254068

Claim:
A memory device formed on a semiconductor substrate, comprising: a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells coupled with the plurality of word lines and the plurality of pairs of bit lines; a plurality of amplifiers coupled with the plurality of pairs of bit lines and amplifying signals on the plurality of pairs of bit lines; a plurality of first signal transmission lines coupled with the plurality of amplifiers and transmitting the amplified signals; a plurality of buffer circuits coupled with the plurality of first signal transmission lines; and a plurality of second signal transmission lines coupled with the plurality of buffer circuits and transmitting signals via the buffer circuits, wherein the plurality of pairs of bit lines is formed in a first layer on a main surface of the semiconductor substrate and is arranged to extend in a first direction of the main face, wherein the plurality of first signal transmission lines is formed in a second layer positioned above the first layer and is arranged to extend in the first direction, wherein the plurality of second signal transmission lines is formed in a third layer positioned above the first layer and the second layer and is arranged to extend in a second direction different from the first direction, and wherein a part of the plurality of second signal transmission lines which is not arranged over the first signal transmission lines is not arranged in parallel with the first signal transmission lines, and wherein a part of the second signal transmission lines which is not arranged over the first signal transmission lines does not cross at right angles with the first signal transmission lines.