Patent ID: 7739557

Claim:
An autonomous error recovery method for a cache of a computing system, said method comprising: testing addressed data and associated control information of a cache of a computing system for a permanent error within a selected storage compartment of the cache, wherein the addressed data is to be provided responsive to a request therefor by a requester, and wherein the permanent error prevents cache update processing from storing a correct value of the addressed data in the selected storage compartment of the cache; and responsive to detecting the permanent error, automatically bypassing the cache by retrieving contents of an addressed storage compartment of a main memory of the computing system, and providing the contents of the addressed storage compartment of the main memory to the requester responsive to the request, wherein the cache and the main memory comprise separate memory devices of the computing system, wherein the addressed data comprises a first quad-word of an addressed data value and a second quad-word of the addressed data value, and wherein the automatically bypassing the cache and retrieving further comprises handling the request as a miss if the permanent error is detected in a code word corresponding to the first quad-word of the addressed data, and if the permanent error is detected in the second quad-word of the addressed data, but not the first quad-word of the addressed data, sending the first quad-word of the addressed data from the cache to the requester, and sending the second quad-word of the addressed data from the main memory responsive to the request, thereby bypassing the cache with the second quad-word.