Patent ID: 7469016

Claim:
A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal from an output terminal, the circuit for generating a ternary signal comprising: a first transistor being on-off controlled by a first control signal, wherein a source is connected to a high-potential-side power supply and a drain is connected to the output terminal; a second transistor being on-off controlled by a second control signal, wherein a source is connected to a first low-potential-side power supply and a drain is connected to the output terminal; a third transistor being on-off controlled by a third control signal, wherein a source is connected to a second low-potential-side power supply that is lower than the first low-potential-side power supply and a drain is connected to the output terminal; and a sequential circuit receiving the input-control signal and the reset signal, being set to an initial state when the reset signal is a first signal level, outputting the first control signal and the third control signal that make the first transistor and the third transistor be switched in a complementary manner in compliance with a level of the input-control signal in the initial state, being released from the initial state when the reset signal is switched from the first signal level to a second signal level, and outputting the second control signal and the third control signal that make the second transistor and the third transistor be switched in a complementary manner in compliance with a level of the input-control signal after a falling edge of the input-control signal is detected in a state that the sequential circuit is released from the initial state.