Patent ID: 7772893

Claim:
A digital frequency synthesizer, comprising: an accumulator, for receiving an input signal and an accumulated value and outputting a phase information accordingly, the phase information being sent back to the accumulator, wherein the phase information comprises a most significant bit (MSB) and a remainder; a transition value generator, for generating a set of a plurality of transition reference values; a phase selection control generator, coupled to the accumulator and the transition value generator, for receiving the phase information and the set of the transition reference values, the phase selection control generator outputting a reference pulse signal according to the MSB and comparing the remainder and the transition reference values for outputting a phase selection control signal; a phase delay locked loop array, for receiving the input signal and generating a set of a plurality of multiphase signals (MPSs); and a phase selection circuit, coupled to the phase selection control generator and the phase delay locked loop array, the phase selection circuit for receiving the reference pulse signal, the phase selection control signal, and the set of the MPSs and outputting a frequency synthetic signal accordingly.