Patent ID: 7298657

Claim:
A ferroelectric random access memory comprising: a memory cell block which includes a plurality of unit cells connected in series and each composed of a memory cell transistor having a source and a drain and a ferroelectric storage element connected in parallel between the source and drain of the memory cell transistor, the memory cell block being connected between a bit line and a plate line via a block selecting transistor; and a redundancy memory cell block which includes a plurality of unit cells the number of which is smaller than that of the unit cells in the memory cell block, the unit cells being connected in series and each composed of a redundancy cell transistor having a source and a drain and a ferroelectric storage element connected in parallel between the source and drain of the redundancy cell transistor, the redundancy memory cell block being connected between the bit line and a spare plate line via a spare block selecting transistor, the redundancy memory cell block being used in place of the memory cell block when any of the unit cells in the memory cell block is defected.