Patent ID: 7356718

Claim:
A semiconductor memory circuit, comprising: a controller for switching the semiconductor memory circuit into a standby mode with a reduced power requirement; an analog subcircuit having a power input and a signal output; a switching device, for supplying electrical power, connected to the power input; a low-pass filter connected to the signal output of the analog subcircuit; a further subcircuit having a further power input and a signal input connected to the output of the low-pass filter; and a further switching device connected to the power input of the further subcircuit, wherein the controller is connected to drive the switching device such that the switching device, in the standby mode, supplies the analog subcircuit with electrical power during a first periodically repeated time duration and does not supply the electrical power during a second periodically repeated time duration, and wherein the controller is configured and connected to drive the further switching device such that the further switching device, in the standby mode, supplies the further subcircuit with electrical power during a third periodically repeated time duration and does not supply electrical power during a fourth periodically repeated time duration.