Patent ID: 8503253

Claim:
A semiconductor device, comprising: a nonvolatile memory cell which has a changeable resistance based on a data to be written; a word line coupled to the memory cell; a bit line coupled to the memory cell; a first transistor coupled between the bit line and a first node; a second transistor coupled between the bit line and a second node; a first charge pump circuit configured to generate a first internal supply voltage for applying the first internal supply voltage to the first node; a second charge pump circuit configured to generate a second internal supply voltage for applying the second internal supply voltage to the second node; a first control circuit configured to be responsive to a level on the first node to operate the first charge pump circuit; and a second control circuit configured to be responsive to a level on the second node to operate the second charge pump circuit, wherein the first charge pump circuit comprises: a first capacitor including first and second electrodes driven by the first control circuit to produce the first internal supply voltage; and a third transistor coupled between a first power source line and a node between the second electrode of the first capacitor and the first node, wherein the second charge pump circuit comprises: a second capacitor including first and second electrodes driven by the second control circuit to produce the second internal supply voltage; and a fourth transistor coupled between the first node and a node between the second electrode of the second capacitor and the second node.