Patent ID: 8476749

Claim:
A chip package, comprising: a set of semiconductor dies arranged in a stack in a vertical direction, which is substantially perpendicular to a plane that is parallel to a first semiconductor die in the vertical stack, wherein a given semiconductor die, after the first semiconductor die, is offset in a horizontal direction in the plane by an offset value from an immediately preceding semiconductor die in the vertical stack, thereby defining a stepped terrace at one side of the vertical stack; and a ramp component, electrically and mechanically coupled to the semiconductor dies, wherein the ramp component is positioned on the one side of the vertical stack, and wherein the ramp component is approximately parallel to a direction along the stepped terrace, which is between the horizontal direction and the vertical direction, wherein one or more of the semiconductor dies include at least one mechanical stop that protrudes in the vertical direction from a surface of the at one or more semiconductor dies that is parallel to the plane, wherein a side of the ramp component that is approximately parallel to the direction along the stepped terrace rests on the at least one mechanical stop, and wherein the mechanical stops facilitate assembly of the chip package.