Patent ID: 8458241

Claim:
A twiddle factor generator for generating a final twiddle factor value for an nth twiddle factor in a fast Fourier transform (FFT) system, the twiddle factor generator comprising: a hardware memory address calculator for generating a temporary address value for the nth twiddle factor, generating a twiddle factor memory address value for the nth twiddle factor based on the temporary address value, and outputting a control signal based on the temporary address value; a twiddle factor storage unit for storing a twiddle factor value corresponding to the twiddle factor memory address value for the nth twiddle factor, the twiddle factor value generated based on a previously generated twiddle factor value, and outputting the twiddle factor value as a real part and an imaginary part; and a controller for outputting the final twiddle factor value to the FFT system based on the control signal output from the memory address calculator and the twiddle factor value output from the twiddle factor storage unit, wherein the memory address calculator generates the temporary address value for the nth twiddle factor by: calculating a multiplied value by multiplying a sign value of the nth twiddle factor and a parameter value indicating a twiddle factor case; and adding the multiplied value to a twiddle factor memory address value for an (n-1)th twiddle factor.