Patent ID: 7429511

Claim:
A method of forming a tunneling insulating layer of an electrically erasable and programmable memory device, the method comprising: forming a first insulating layer on a substrate; forming a re-flowable material layer pattern having an aperture of a first width on the first insulating layer; implanting impurity ions into the substrate through the aperture of the first width; re-flowing the re-flowable material layer pattern to form a re-flown material layer pattern having an aperture of a second width that is smaller than the first width; removing the first insulating layer that has been exposed by the re-flown material layer pattern having the aperture of the second width to expose the substrate; and forming a tunneling insulating layer on the exposed substrate and, wherein, when the re-flowable material layer pattern having the aperture of the first width is re-flown, the impurity ions implanted into the substrate are diffused to form an impurity diffusion region.