Patent ID: 7799617

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a first conductive structure comprising a first metal layer and a metal fuse on a semiconductor substrate having a bonding pad area and a fuse area, wherein the metal fuse is formed in the fuse area; forming a first inter-metal dielectric (IMD) layer covering the first conductive structure and the metal fuse; partially removing the first IMD layer to form a via hole through which the first conductive structure is partially exposed; forming a second conductive structure on the first IMD layer to fill the via hole, wherein the second conductive structure comprises a second metal layer and an etching prevention layer formed on the second metal layer; forming a second IMD layer on the first IMD layer, wherein the second IMD layer covers the second conductive structure; partially removing the second IMD layer and the first IMD layer to form an opening exposing the fuse area and the bonding pad area; and partially etching the metal fuse to reduce a thickness of the metal fuse while protecting the second metal layer with etching prevention layer.