Patent ID: 7353471

Claim:
A method for analyzing the thermal conductance of a semiconductor chip design comprising a plurality of physical layers, the method comprising: performing full-chip thermal analysis of said semiconductor chip design, the full-chip thermal analysis producing full-chip temperature data; defining at least one thermal layer within said plurality of physical layers, in accordance with said full-chip temperature data, said at least one thermal layer representing a variance in thermal conductance relative to a remainder of said semiconductor chip design; computing a thermal conductance of said at least one thermal layer; and iterating said performing, said defining, and said computing such that said iterating refines said full-chip temperature data, wherein said at least one thermal layer is defined in accordance with at least one thermal property of at least one corresponding physical layer, said at least one thermal property comprising at least one of: a thermal conductivity of a material forming said at least one corresponding physical layer, a density of a material forming said at least one corresponding physical layer, a specific heat of a material forming said at least one corresponding physical layer, a thickness of a material forming said at least one corresponding physical layer, a cross-sectional area of a material forming said at least one corresponding physical layer and physical boundaries of a package incorporating said semiconductor chip design.