Patent ID: 7932773

Claim:
A charge domain circuit, comprising: a first signal output portion that includes a first sampling capacitor that performs sampling of a first input signal to the first sampling capacitor at a specified time interval, and outputs a first signal; a second signal output portion including a second sampling capacitor that performs sampling of a second input signal to the second sampling capacitor after a delay of n times the specified time interval after the first input signal is sampled, and outputting a second signal, n being a positive integer; a third signal output portion that includes a third sampling capacitor that performs sampling of a third input signal to the third sampling capacitor after a delay of n times the specified time interval after the second input signal is sampled, and outputs a third signal; and an adder portion that adds the first signal, the second signal, and the third signal together and outputs a resulting signal, wherein a capacitance ratio of the first sampling capacitor to the second sampling capacitor continuously or discretely varied.