Patent ID: 7838366

Claim:
A method of fabricating a metal gate structure, comprising: providing a semiconductor substrate, the semiconductor substrate defining at least an isolation region and at least an active region; forming a dielectric material on the semiconductor substrate; forming a polysilicon material on the semiconductor substrate; planarizing the polysilicon material using chemical mechanical polishing to form a planarized polysilicon material on the isolation region and the active region; patterning the planarized polysilicon material and the dielectric material to form at least a first gate and a second gate on the semiconductor substrate, wherein the first gate is on the active region and the second gate is partially set across on the isolation region; forming an inter-layer dielectric material covering the first gate and the second gate on the semiconductor substrate; removing a portion of the inter-layer dielectric material until exposing the first gate and the second gate; performing an etching process to remove the first gate and the second gate to form a first recess and a second recess corresponding respectively to the first gate and the second gate within the inter-layer dielectric layer; forming at least a metal material within the first recess and the second recess.