Patent ID: 7996200

Claim:
A method for computer-generation of a test plan of a hardware design using transaction-based abstraction, the method comprising: selecting one or more transaction-processing finite state machines (FSMs), wherein the one or more transaction-processing FSMs determine one or more transaction boundaries, a transaction boundary being a starting and ending time step of a transaction, wherein the step of selecting includes: recognizing signals of the hardware design that indicate FSM candidates; and identifying the one or more transaction-processing FSMs from the FSM candidates; extracting the one or more transaction-processing FSMs; obtaining an abstracted FSM based upon the one or more extracted transaction-processing FSMs; and abstracting signals in the hardware design based on the abstracted FSM, wherein abstracting signals includes steps of: creating one or more abstracted signal functions associated with composite states of a composed FSM; creating abstracted expressions by combining abstracted signal functions from different composite states that are associated with an abstracted state of the abstracted FSM; and combining the abstracted expressions to form a single expression per signal over abstracted states of the abstracted FSM.