Patent ID: 7492292

Claim:
An apparatus comprising: an analog front end to receive a signal from a communication channel physical medium; an analog-to-digital converter (ADC) coupled to an output of the analog front end to digitize the received signal, wherein the ADC is a time-interleaved pipelined ADC having a digital compensator to receive an error signal and to adaptively update a first value and a second value based on the error signal; a digital signal processor (DSP) coupled to receive an output signal of the ADC to process the digitized signal and to generate a decision output and the error signal, wherein the error signal from the DSP is fed back to the analog front end for use in calibration of an analog circuit, and the output signal corresponds to ∑ k = 1 N ⁢ ⁢ h ^ k ⁢ d k + off ⁢ s ^ ⁢ et , wherein ĥ k corresponds to the first value corresponding to a vector of N values, offŝet corresponds to the second value, N corresponds to the number of stages of the ADC, and d k is a decision output of the k th stage of the ADC that is weighted by the corresponding ĥ k , wherein ĥ k and offŝet are adapted based on the error signal.