Patent ID: 7652511

Claim:
A slew-rate control circuitry, comprising: an input controlled logic unit, receives signal from at least one input and provides at least one output; and an output buffer circuitry, receives signal from at least one input and provides at least one output, including: a first P-channel MOS transistor switch having a source connected to a supply voltage and its gate receives an output signal from said input controlled logic unit; a second P-channel MOS transistor switch having a source connected to drain of said first PMOS switch, a gate connected to a circuit and a drain connected to an output; a first N-channel MOS transistor switch having a drain connected to a reference voltage and a gate receives another output signal from said input controlled logic unit; and a second N-channel MOS transistor switch having a drain connected to source of said first N-channel MOS transistor switch, a gate connected to the circuit and a source connected to the output; and at least one feedback MOS circuitry, provides control over feedback for said slew-rate control circuitry, including; a capacitive element connected to output in one end; a third P-channel MOS transistor switch having a source connected to gate of said first P-channel MOS transistor, a gate connected to said input controlled logic unit and a drain connected to other end of said capacitive element; and a third N-channel MOS transistor switch having a drain connected to gate of said first N-channel MOS transistor, a gate connected to said input controlled logic unit and a source connected to said capacitive element.