Patent ID: 7902026

Claim:
A method of fabricating a semiconductor device having a vertical channel transistor, the method comprising: forming a hard mask pattern on a substrate; forming a preliminary active pillar by etching the substrate using the hard mask pattern as an etch mask; reducing a width of the preliminary active pillar to form an active pillar having a width less than that of the hard mask pattern; forming a lower source/drain region by implanting impurity ions into the substrate adjacent to an exposed outer periphery on the active pillar and exposed sidewalls of the hard mask pattern using the hard mask pattern as an ion implantation mask, the exposed outer periphery being separated from an imaginary extension line that extends from the exposed sidewalls of the hard mask pattern normal to the substrate, and the exposed outer periphery being separated from the imaginary extension line by a shadow region surrounding the active pillar; and forming an upper source/drain region on the active pillar and vertically separated from the lower source/drain region.