Patent ID: 8502320

Claim:
An integrated circuit, comprising: a substrate of a first conductivity type; a well of a second conductivity type disposed in the substrate; a first gate electrode structure disposed over the well; a second gate electrode structure disposed over the substrate outside the area of the well; a first set of source/drain (S/D) terminals disposed in corresponding recesses in the well, the first set of S/D terminals adjacent to the first gate electrode structure; a first planar diode junction layer of the first conductivity type disposed in a recess in the substrate, the recess located in a region of the substrate outside of the well; a second set of S/D terminals disposed on a surface of the substrate, the second set of S/D terminals adjacent to the second gate electrode structure; and a second planar diode junction layer of the second conductivity type disposed over at least a portion of the first planar diode junction layer.