Patent ID: 8084830

Claim:
A semiconductor memory device, comprising: a plurality of first wirings and a plurality of second wirings formed to intersect with each other; and a memory cell array including memory cells arranged therein, each of the memory cells being located at respective intersections between the first wirings and the second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series, the rectifier element including: a p type first semiconductor region; a n type second semiconductor region; and a third semiconductor region formed to be sandwiched between the first and second semiconductor regions, and having an impurity concentration that is smaller than those of the first and second semiconductor regions, the first to third semiconductor regions being laminated in the rectifier element, the first semiconductor region being formed of, at least in part, silicon-germanium mixture (Si 1-x Ge x (0<x<=1)), and the second and third semiconductor regions being formed of silicon (Si).