Patent ID: 8592296

Claim:
A method of gate-last fabrication for a field effect transistor (FET), the method comprising: forming a gate stack on a silicon substrate, the gate stack comprising: a high-k dielectric layer located on the silicon substrate; a first gate metal layer located over the high-k dielectric layer, the first gate metal layer consisting of titanium nitride and having a thickness, wherein the thickness determines a work function of the FET; a threshold voltage tuning layer located between the high-k dielectric layer and the first gate metal layer, wherein a thickness of the threshold voltage tuning layer is based on the thickness of the first gate metal layer; an oxygen barrier layer located over the first gate metal layer, the oxygen barrier layer comprising tantalum nitride (TaN) formed by atomic layer deposition (ALD); and a second gate metal layer located over the oxygen barrier layer; forming a polysilicon layer over the gate stack; annealing the gate stack and the silicon substrate; removing the polysilicon layer; and forming a metal contact over the gate stack.