Patent ID: 8804409

Claim:
A semiconductor storage device comprising: a plurality of bit lines; a plurality of word lines; a plurality of memory cells corresponding to intersections between the bit lines and the word lines, and including magnetic tunnel junction elements capable of storing data; a plurality of sense amplifiers each corresponding to plurality of the bit lines and configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines; a plurality of read latch parts corresponding to the sense amplifiers, respectively, and configured to latch data detected by the corresponding sense amplifiers; and a plurality of read global data buses connected to the read latch parts, respectively, and configured to consecutively transmit data latched by the read latch parts at a time of a data read operation, wherein the memory cells constitute a cell array unit, a plurality of the cell array units sharing the word lines constitute a memory cell macro, a plurality of the memory cell macros sharing the read global data buses constitute a macro block, the sense amplifiers in one of the memory cell macros are connected to the different global data buses, respectively, the read latch parts in one of the memory cell macros are connected to the different global data buses, respectively, and at the time of the data read operation, the memory cell macros in the macro block consecutively transmit data to the corresponding read global data buses.