Patent ID: 7800408

Claim:
An apparatus for rapidly charging I 2 C bus lines, comprising: a first time delay circuit; a second time delay circuit; an SDA line driver coupled to an SDA line of an I 2 C bus; an SCL line driver coupled to an SCL line of the I 2 C bus; wherein: the first time delay circuit generates a first pulse upon detection of an internal SCL signal at a first logic level, the first pulse having a first pulse time duration, the second time delay circuit generates a second pulse upon detection of completion of the first pulse, the second pulse having a second pulse time duration, the first pulse time duration is shorter than a time duration of an internal SDA signal; the second pulse time duration is shorter than a time duration of an internal SCL signal; and whereby: when the internal SDA signal is at the first logic level the SDA line driver charges the SDA line capacitance through a low impedance circuit during the first pulse time duration, and the SCL line driver charges the SCL line capacitance through a low impedance circuit during the second pulse time duration.