Patent ID: 7508705

Claim:
A method for programming multi-level non-volatile memory comprising a flag cell and a plurality of multi-bit storage cells, each of the plurality of multi-bit storage cells for storing data represented by a least significant bit (LSB) and a most significant bit (MSB), the method comprising: programming the storage cells with LSB data such that programmed storage cells have a threshold voltage greater than VR 1 ; modifying the threshold voltage of the programmed storage cells such that each of the programmed storage cells has a threshold voltage greater than VR 2 when it is desired that the storage cell store the third or fourth value; programming the storage cells with MSB data such that each of the storage cells: has a threshold voltage lower than a voltage VR 1 when it is desired that the storage cell store a first value; has a threshold voltage greater than the voltage VR 1 and lower than a voltage VR 2 when it is desired that the storage cell store a second value; has a threshold voltage greater than the voltage VR 2 and lower than a voltage VR 3 when it is desired that the storage cell store a third value; and has a threshold voltage greater than a voltage VR 3 when it is desired that the storage cell store a fourth value, wherein VR 1 <VR 2 <VR 3 , wherein the flag cell is programmed to signal whether MSB data has been programmed.