Patent ID: 7763931

Claim:
A nonvolatile semiconductor memory device, comprising: a semiconductor substrate having an upper surface; a plurality of memory cell transistors formed in the semiconductor substrate, each memory cell transistor including a gate electrode having a gate insulating layer formed on the upper surface of the semiconductor substrate, a floating gate electrode layer formed on the gate insulating layer, an inter-gate insulating layer formed on the floating gate electrode layer, and a control gate electrode layer formed on the inter-gate insulating layer; a first oxide-based insulating film formed above the upper surface of the semiconductor substrate between the gate electrodes, the first oxide-based insulating film including an upper surface being at level with or higher than an upper surface of the floating gate electrode layer but lower than an upper surface of the control gate electrode layer; a nitride-based insulating film formed on the first oxide-based insulating film, the nitride-based insulating film containing boron (B) and located level with or higher than the upper surface of the floating gate electrode layer but lower than the upper surface of the control gate electrode layer; and a second oxide-based insulating film formed on the nitride-based insulating film.