Patent ID: 8234782

Claim:
A method of fabricating a component for a microelectronic device on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas, comprising: forming a first pattern in a resist layer on the dielectric layer, the first pattern having an arrangement of apertures corresponding to a desired arrangement of contact openings over first portions of the active areas and conductor openings over second portions of the active areas; etching the dielectric layer to form contact openings over the first portions of the active areas and conductor openings over the second portions of the active areas; depositing a first conductive material into the contact openings to construct contacts and into the conductor openings to construct conductors; forming a second pattern in another resist layer on the workpiece, the second pattern having an elongated slot extending over a plurality of the contacts and portions of the dielectric layer; etching an elongated trench in upper portions of the contacts under the elongated slot; filling the elongated trench with a second conductive material; and planarizing the workpiece to form a conductive line in the elongated trench, contacts in the dielectric layer, and conductors in the dielectric layer.