Patent ID: 8207882

Claim:
An analog to digital converter (ADC), comprising: a folding stage, configured to: determine one of a first plurality of sub-ranges of the input voltage range in which an input analog voltage falls based on a comparison of the input analog voltage to one or more first reference voltages, and offset the input analog voltage by a folding voltage offset corresponding to the determined one of the sub-ranges to produce a residue voltage, the folding voltage offset selected from a first set of voltage offsets, and each voltage offset in the first set corresponding to a respective one of the plurality of sub-ranges; and a plurality of ADC stages, wherein a first one of the plurality of ADC stages is configured to receive the residue voltage produced by the folding stage, and each other ADC stage of the plurality of ADC stages is configured to receive a residue voltage from a previous one of the plurality of ADC stages; and wherein each of the plurality of ADC stages is configured to: determine one of a second plurality of sub-ranges of the input voltage range in which the received residue voltage falls based on a comparison of the received residue voltage to one or more second reference voltages, multiply the received residue voltage by a factor of N to produce an intermediate voltage, select a cyclic voltage offset corresponding to the determined one of the second plurality of sub-ranges from a second set of voltage offsets, each voltage offset of the second set corresponding to a respective one of the second plurality of sub-ranges, and adjust the intermediate voltage by the cyclic voltage offset.