Patent ID: 7236035

Claim:
A semiconductor device comprising: a first logic circuit which has its supply voltage controlled; a second logic circuit which operates in response to an external clock signal; an adjustment circuit including a detection circuit and a first delay circuit supplied with the external clock signal, the detection circuit detecting a skew between timings of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit and adjusting the delay time of the first delay circuit according to the result of the detection, and the first delay circuit applying an output signal to the first logic circuit as a third clock signal, wherein the detection circuit includes a second delay circuit adapted to delay the second clock signal in time to output a fourth clock signal, and a measurement circuit connected to receive the fourth clock signal output from the second delay circuit and the first clock signal to measure a time difference between the first and fourth clock signals and output a control signal which is a function of the time difference, and the delay time of the first and second delay circuits are controlled in accordance with the control signal from the measurement circuit.