Patent ID: 8683448

Claim:
An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a program residing in the memory; a debugger residing in the memory and executed by the at least one processor, the debugger debugging the program, the debugger performing the steps of: (A) allowing a user to define a plurality of breakpoints in the program; (B) creating an entry in a breakpoint table for each of the plurality of breakpoints defined by the user in step (A); (C) writing an original instruction in the program corresponding to each breakpoint defined by the user in step (A) to a corresponding entry in the breakpoint table; (D) replacing a plurality of instructions in the program with a plurality of corresponding trap instructions that give control to the debugger at locations defined by the breakpoints defined by the user in step (A); (E) each time the debugger halts execution of the program, performing the steps of: (E1) reading the plurality of instructions in the program corresponding to the plurality of breakpoints defined in the breakpoint table; (E2) determining whether any of the plurality of instructions in the program corresponding to the plurality of breakpoints changed; (E3) for each of the plurality of instructions in the program that changed, removing the corresponding breakpoint by removing the entry in the breakpoint table corresponding to the breakpoint; and (E4) for each breakpoint removed in step (E3), providing notification to the user that the breakpoint was removed.