Patent ID: 7824987

Claim:
A semiconductor device manufacturing method, comprising the steps of: (a) forming a first gate insulating film on a first element formation region of a semiconductor substrate in a SRAM section while forming a second gate insulating film on a second element formation region of the semiconductor substrate in a logic circuit section; (b) forming gate electrode formation films on the first gate insulating film and the second gate insulating film; (c) forming a first n-type gate electrode formation film by introducing a first n-type impurity at a first impurity concentration to the gate electrode formation film on the first element formation region; (d) forming a second n-type gate electrode formation film by introducing a second n-type impurity at a second impurity concentration higher than the first impurity concentration to the gate electrode formation film on the second element formation region; (e) forming, after the step (c) and the step (d), a first n-type gate electrode and a second n-type gate electrode by patterning the first n-type gate electrode formation film and the second n-type gate electrode formation film; and (f) performing, after the step (e), thermal treatment to diffuse the first n-type impurity contained in the first n-type gate electrode and the second n-type impurity contained in the second n-type gate electrode.