Patent ID: 8612687

Claim:
A method, in a data processing system, for latency-tolerant memory access in a three-dimensional stacked memory, the method comprising: receiving, by a memory controller, a memory access command from a processing core; sending, by the memory controller, a memory access command to each of a plurality of memory layers in the three-dimensional stacked memory, wherein sending the memory access command to each of the plurality of memory layers in the three-dimensional stacked memory comprises sending by the memory controller a first command to a first memo layer in a first cycle, relaying the first command by the first memory layer to a second memory layer in a second cycle, relaying the first command by the second memory layer to a third memory layer in a third cycle, and relaying the first command by the third memory layer to a fourth memory layer in a fourth cycle; receiving, by the memory controller, a portion of a cache line from each memory layer within the plurality of memory layers to form a cache line; and returning, by the memory controller, the cache line to the requesting processor core.