Patent ID: 7380110

Claim:
A processor comprising: a bus for carrying at least a portion of an instruction instance identifier; a branch prediction storage, connected to said bus, including: branch direction storage, connected to said bus and having a first output for providing a branch direction indication, for storing entries for branch direction indications, wherein each branch direction indication stored in said branch direction storage indicates a direction of a branch instruction instance with respect to branch prediction; and in response to said at least a portion of said instruction instance identifier, a branch direction indication associated with that instruction instance identifier is provided on said first output; and branch prediction qualifier indications storage connected to at least a portion of said bus and having a second output for providing a branch predication qualifier indication, for storing entries for branch prediction qualifier indications, wherein in response a signal on said at least a portion of said bus, a branch prediction qualifier indication associated with said at least a portion of said instruction instance identifier is provided on said second output; wherein said entries in said branch direction indications storage are more numerous than said entries in said branch prediction qualifier indications storage; and an outcome of said branch instruction instance is predicted based at least in part on said branch direction indication on said first output and said branch prediction qualifier indication on said second output.