Patent ID: 8730758

Claim:
A method for adjusting a write timing in a memory device, comprising: receiving, by the memory device, a data signal, a write clock signal, and a reference signal from a processing unit; buffering, by the memory device, the reference signal; sampling, by the memory device, the buffered reference signal; computing phase measurements of the sampled reference signal over a period of time; comparing the computed phase measurements of the sampled reference signal over the period of time; generating, by the memory device, a phase shift based on the compared phase measurements over the period of time; generating, by the memory device, a phase error signal based on the phase shift; and adjusting, by the memory device, a phase difference between the data signal and the write clock signal based on the phase error signal, wherein the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.