Patent ID: 7587532

Claim:
Control circuitry comprising: A. flag generation circuitry having a reset input lead, a write input lead, an enable input lead, and plural count output leads, in which the flag generation circuitry includes: a. a series connection of D-type flip-flops and multiplexers, b. each flip-flop having a D input, a reset input, an enable input, and a Q output, c. each multiplexer having first and second inputs, a control input connected to the write input lead, and an output connected to the D input of a flip-flop, and d. the reset input of all the flip-flops being connected to the reset input lead, the enable input of all the flip-flops being connected to the enable input lead, the Q outputs being connected to the plural count output leads; B. switch circuitry having plural inputs connected to the plural count output leads, a queue full output, and a Full/Selector input, the switch circuitry coupling one of the plural inputs to the queue full output in response to a control input; and C. comparator circuitry having a Full/Selector output connected to the Full/Selector input of the switch circuitry.