Patent ID: 7287200

Claim:
A jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, comprising: a PLL circuit for generating an oscillating signal corresponding to a given reference signal; a variable delay circuit for outputting said clock signal of said delayed oscillating signal; a low-frequency application section for applying a low-frequency component of said phase jitter component to said oscillating signal by controlling oscillation frequency of said PLL circuit based on the low-frequency component of said jitter data; and a high-frequency application section for applying a high-frequency component of said phase jitter component to said clock signal by controlling a delay in said variable delay circuit based on the high-frequency component of said jitter data, wherein said PLL circuit has a voltage controlled oscillator for generating said oscillating signal having frequency corresponding to given control voltage; a phase comparator for generating said control voltage based on a result of comparison of the phase of the given reference signal and the phase of said oscillating signal; and a low-pass filter for removing the high-frequency component of said control voltage to give to said voltage controlled oscillator, and said low-frequency application section superimposes voltage corresponding to said jitter data to said control voltage generated by said phase comparator and inputs it to said low-pass filter, and wherein an oscillating signal generated by a voltage controlled oscillator is fed back to the phase comparator via a frequency divider, said feed back is performed inside of a PLL circuit.