Patent ID: 7123516

Claim:
A non-volatile memory comprising: an array of non-volatile memory cells arranged in columns using bit lines; first and second comparators for comparing a bit line voltage with first and second reference voltages respectively to respectively produce first and second output signals; a bit line current-to-voltage converter coupled between a selected one of the bit lines and the first and second comparators to generate the bit line voltage in response to a bit line current; and first and second reference current-to-voltage converters, for respectively generating the first and second reference voltages, respectively coupled between the first and second comparators and first and second reference currents, each reference current-to-voltage converter comprising: a resistor; an activation circuit coupled to the resistor; and a floating gate transistor, coupled to the activation circuit, for creating a voltage drop across the resistor that provides one of the first or second reference voltages in response to the first or second reference currents respectively.