Patent ID: 7788422

Claim:
Data circuitry comprising: A. host circuitry including a digital signal processor central processing unit connected with processor memory circuitry, and direct memory access circuitry; B. front end interface circuitry; and C. receive circuitry including plural modules receiving data signals from the front end circuitry and outputting processed data signals for the memory circuitry, the receive circuitry further including: i. transfer memory circuitry containing channel allocation data; ii. host interrupt interface circuitry having data event inputs receiving the processed data signals, channel allocation inputs connected with the transfer memory circuitry, an initiate transfer output, and control outputs carrying first block ID signals, transfer configuration information signals, and post-transfer information signals; and iii. host transfer interface circuitry having an initiate transfer input connected to the initiate transfer output, control inputs connected to the control outputs, data inputs coupled with the processed data signals, a request transfer output coupled with the direct memory access circuitry, and data outputs, the transfer module including buffer circuitry connected between the data inputs and data outputs and controller circuitry connected to the buffer circuitry, the initiate transfer input, and the control inputs.