Patent ID: 7174631

Claim:
A method for fabricating an electrical connection terminal of an embedded chip, which comprises the steps of: providing a circuit board embedded with a chip having a plurality of conductive pads on a surface thereof; forming an insulating layer on the circuit board, wherein the insulating layer is formed with a plurality of first openings, and at least one of the first openings corresponds to a position of the conductive pads of the chip; forming a zincified treatment layer on the conductive pad of the chip by pre-depositing the zincified treatment layer; forming a nickel layer on the zincified treatment layer by an electroplating process, for effectively adhering the nickel layer on the conductive pad with the zincified treatment layer; forming a conductive layer on a surface of the nickel layer, the insulating layer and the first opening thereof; forming a patterned resist layer on the conductive layer, wherein the resist layer having a plurality of second openings to expose a part of the conductive layer to be subsequently deposited with a metal layer, and at least one of the second openings corresponds to the position of the conductive pad of the chip; and forming a second metal layer on the exposed part of the conductive layer by an electroplating process.