Patent ID: 7332924

Claim:
An apparatus for testing a semiconductor device for breakdown, wearout or failure, the test circuitry being embedded in the semiconductor device, the test circuitry comprising: at least two testers, each tester comprising: a device under test (DUT) embedded in the semiconductor device; a supply voltage connection for enabling a power supply that is external to the semiconductor device to be connected to the tester for supplying voltage to the DUT; a current monitoring connection for enabling a current monitoring device to be electrically coupled to the current monitoring connection for monitoring a current passing through the DUT; and a voltage regulator circuit comprising an operational amplifier (op-amp) having a non-inverting input that receives a reference voltage, the reference voltage being supplied to the op-amp from a global reference voltage supply that simultaneously supplies a reference voltage to all of the op-amps of all of the testers, each op-amp of each tester having an output that is electrically coupled to the DUT of the corresponding tester; and wherein the supply voltage connections of the testers are electrically coupled such that the supply voltages are simultaneously supplied to the supply voltage connections of the testers.