Patent ID: 7557809

Claim:
A data processor formed on a LSI, comprising: a central processing unit; a first internal bus coupled to said central processing unit; a second internal bus; a memory controller couples to said central processing unit, said first internal bus, and said second internal bus, wherein said memory controller interfaces to an external synchronous DRAM, receives address information from said central processing unit via said first internal bus, and provides an address based on said address information to said external synchronous DRAM; a display control unit providing display signals to outside of the data processor; a bus controller coupled to said central processing unit via said first internal bus, and coupled to external flash memory and/or static RAM via an external system bus, wherein said display control unit is operable to be coupled to said second internal bus, and to be coupled to said memory controller accessing said external synchronous DRAM, and wherein said central processing unit said display control unit are operable to be shared with a memory area of said external synchronous DRAM.