Patent ID: 8314726

Claim:
A time-to-digital conversion circuit for providing a digital output indicative of a time at which an event occurred, the conversion circuit comprising: a clock configured to generate a first clock signal having a clock period; a coarse timing circuit configured to count the number of elapsed clock periods from a reference point in time to detection of the event to be measured, wherein the coarse timing circuit generates a coarse count corresponding to the most significant bits of the digital output; a time division circuit configured to divide the clock period into smaller sub-intervals by generating a plurality of second clock signals, each second clock signal being a copy of the first clock signal and each copy being phase delayed with respect to the first clock signal, the number of copies being equal to the number of sub-intervals; a fine timing circuit configured to determine in which sub-interval of the clock period the event occurred, wherein the fine timing circuit generates the least significant bits of the digital output; and a correction circuit configured to correct an erroneous offset between the first and second clock signals in the fine timing circuit, wherein the correction circuit further comprises a synch circuit configured to determine in which half of the clock period the event occurred to correct for the erroneous offset in the fine timing circuit.