Patent ID: 7902886

Claim:
A multi reference phase locked loop (MPLL) for generating a high speed clock having a high speed clock frequency and phase locking it to a lowest common reference frequency derived from a selected one of at least two reference clocks, the MPLL comprising: (a) a prescaler for reducing frequency of at least one of said at least two reference clocks, comprising a first multiplexer for multiplexing the high speed clock and the at least two reference clocks into a multiplexed clock; and a divider circuit for reducing frequency of the multiplexed clock; (b) a reference selector for selecting the selected one of said at least two reference clocks after its frequency has been reduced in the reference selector to the lowest common reference frequency; (c) a phase detector for comparing the selected one of the at least two reference clocks with a feedback clock, and generating a frequency control voltage indicative of a phase error between the compared clocks; (d) a voltage controlled oscillator (VCO) for generating the high speed clock having the high speed clock frequency based on the frequency control voltage until phase locking is indicated by a convergence of the phase error to a substantially constant value; and (e) a feedback divider for processing the high speed clock into the feedback clock with the same lowest common reference frequency.