Patent ID: 8378719

Claim:
A frequency divider circuit adapted to receive an input clock signal having a first period and adapted to provide an output clock signal having a second period that is a programmable multiple, A, of the first period, the frequency divider circuit comprising: a shift register circuit adapted to receive the input clock signal, the shift register circuit provides a first output signal; and a duty cycle compensation circuit configured to receive the first output signal, the duty cycle compensation circuit comprises: a first delay circuit configured to provide a second output signal, the second output signal having a substantially constant amplitude when multiple A is even, the second output signal corresponding to the first output signal delayed by a first delay when multiple A is odd; a second delay circuit configured to provide a third output signal, the third output signal corresponding to the first output signal delayed by a second delay that is substantially one-half an input clock signal cycle less than the first delay; and an OR circuit having a first input adapted to receive the second output signal and a second input adapted to receive the third output signal, the OR circuit provides the output clock signal as a result performing an OR function on the second and third output signals.