Patent ID: 8756555

Claim:
A method for generating a biased layout for making an integrated circuit using a standard cell library containing cell layouts, comprising: (a) identifying a nominal layout defined by one or more cell layouts, each cell layout having one or more transistors having transistor gate features with a nominal gate length; (b) identifying an annotated layout, the annotated layout itself provides information for identifying gate-length biasing of one or more of the transistor gate features in one or more cell layouts of the nominal layout; and (c) producing a biased layout by modifying the nominal layout using the information provided by the annotated layout, such that the biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout, the information defining an amount of the biasing which is a design-specific directive that must be implemented when producing the biased layout, the annotated layout making the amount of biasing layout-transparent to avoid violation of a design rule, the method implemented by a processor executing a program.