Patent ID: 7149072

Claim:
A multilayered chip capacitor array, comprising: a capacitor body having a plurality of dielectric layers stacked together; a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween; at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body; and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively, wherein the at least one first conductive via is connected to the first inner electrodes and is electrically insulated from the second inner electrodes, wherein the plurality of the second conductive vias are divided into k (k≧2) groups each having at least one second conductive via, and the second inner electrodes are divided into k groups each having at least one second inner electrode, and each group of second conductive vias is connected to each group of second inner electrodes and is electrically insulated from the other group of second inner electrodes and first inner electrodes, wherein the first and second conductive vias are disposed so that magnetic fields induced by current flowing into the inner electrodes connected thereto are offset.