Patent ID: 7948013

Claim:
A layout of an integrated circuit device, comprising: a gate electrode level layout portion including five or more adjacently positioned linear shaped layout features each formed to have a respective length and a respective width when viewed from above, wherein a size of the length of a given linear shaped layout feature is greater than or equal to a size of the width of the given linear shaped layout feature, wherein the five or more adjacently positioned linear shaped layout features are formed to have their lengths extend in a first direction in a parallel manner, wherein the five or more adjacently positioned linear shaped layout features are formed to have a substantially equal centerline-to-centerline spacing between each pair of adjacently positioned linear shaped layout features as measured perpendicular to the first direction, and wherein the region of the gate electrode level includes six linear shaped layout features each formed to have their lengths extend in the first direction in the parallel manner, wherein the six linear shaped layout features include, a first linear shaped layout feature defined to form both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, a second linear shaped layout feature defined to form a gate electrode of a second transistor of the first transistor type, a third linear shaped layout feature defined to form a gate electrode of a second transistor of the second transistor type, a fourth linear shaped layout feature defined to form a gate electrode of a third transistor of the first transistor type, a fifth linear shaped layout feature defined to form a gate electrode of a third transistor of the second transistor type, a sixth linear shaped layout feature defined to form a gate electrode of both a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type.