Patent ID: 6963231

Claim:
An insulating device for system on chip (SOC), wherein the SOC has a first circuit region powered by a main power source and a second circuit region powered by a real-time power source, comprising: a selector designating the main power source or a battery source as the real-time power source; a level detector powered by operating power source to detect a voltage level of the main power source and output a resulting signal; a NAND gate coupled to the first circuit and the level detector to produce a logic output according to the resulting signal and an output signal of the first circuit, wherein the NAND gate comprises: a first NMOS transistor having a gate coupled to the output signal of the first circuit, and a source coupled to ground and a drain; a second NMOS transistor having a gate coupled to the result signal, a source coupled to the drain of the first NMOS transistor and a drain as an output terminal; a first PMOS transistor having a gate coupled to the gate of the first NMOS transistor, a source coupled the real-time power source and a drain coupled to the drain of the second NMOS transistor; and a second PMOS transistor having a gate coupled to the gate of the second NMOS transistor, a source coupled to the real-time power source and a drain coupled to the drain of the second NMOS transistor.