Patent ID: 7521762

Claim:
A semiconductor device having a standby cycle and an active cycle, comprising: a plurality of stages of inverter circuits including a first type of inverter circuit including a first P-channel MIS transistor and a first N-channel MIS transistor connected between a first power source node and a second power source node, a second type of inverter circuit including a second P-channel MIS transistor and a second N-channel MIS transistor connected between said first power source node and said second power source node, and said first type of inverter circuit and said second type of inverter circuit being successively and alternately connected in series in said plurality of stages, wherein said first P-channel MIS transistor is turned on in said standby cycle and turned off in said active cycle in accordance with an input signal, and is of a buried channel type having an N+ polycrystalline silicon gate formed at the surface of an N-type semiconductor substrate region, said second P-channel MIS transistor is turned off in said standby cycle and turned on in said active cycle in accordance with said input signal, and is of a surface channel type having a P+ polycrystalline silicon gate formed at the surface of an N-type semiconductor substrate region, said first N-channel MIS transistor is turned off in said standby cycle and turned on in said active cycle in accordance with said input signal, and is of a surface channel type having an N+ polycrystalline silicon gate formed at the surface of a P-type semiconductor substrate region, and said second N-channel MIS transistor is turned on in said standby cycle and turned off in said active cycle in accordance with said input signal, and is of a buried channel type having a P+ polycrystalline silicon gate formed at the surface of a P-type semiconductor substrate region.