Patent ID: 7511529

Claim:
A noise suppression circuit comprising: a first transistor having a gate connected to a signal source, a first source/drain connected to a detect node, and a second source/drain connected to a first power supply voltage; a second transistor having a gate connected to the first power supply voltage, a first source/drain connected to a second power supply voltage, and a second source/drain connected to the detect node; a first inverter having an input connected to the detect node and an output; a third transistor having a gate connected to the output of the first inverter, a first source/drain connected to the first power supply voltage, and a second source/drain; a fourth transistor having a gate, a first source/drain connected to the signal source, and a second source/drain connected to the second source/drain of the third transistor; and a second inverter having an input connected to the signal source and an output connected to the gate of the fourth transistor.