Patent ID: 8000954

Claim:
An FPGA emulation system comprising: a physical FPGA device under test having a plurality of pins; a controller circuit; and a bus functional model hardware circuit having a plurality of pins coupled to the plurality of pins of the FPGA device under test, the bus function model hardware circuit responsive to signals representing predetermined input characteristics of said FPGA device under test and configured to apply one or more signals to said physical FPGA device under test corresponding to said predetermined input characteristics and configured to receive one or more signals representing output characteristics of said FPGA device under test in order to emulate the operation of said FPGA device under test in a predefined selectable and flexible electrical operating environment associated with the physical FPGA device under test such that when a design change in the FPGA device under test results in a change in the pin-out configuration of the FPGA device under test, the controller circuit is configured to program the selectable and flexible electrical operating environment, the FPGA device under test, and the bus functional model hardware circuit so that the FPGA emulation system can emulate and verify the design change without the need to rebuild a prototype board.