Patent ID: 7450429

Claim:
An integrated circuit including: a supply-voltage input node driven by an external supply-voltage; a voltage regulator having an input coupled to the supply-voltage input node and a voltage-regulator output supplying a regulated voltage; a charge pump having an input coupled to the supply-voltage input node and a charge-pump output supplying a high voltage having a value higher than the external supply-voltage; a memory array having a plurality of memory cells coupled to word lines and bit lines; a word-line driver coupled to the memory array to provide the external supply-voltage and high voltage to the word lines; a decoder coupled to the word-line driver; a bit line selector coupled to the memory array to select the bit lines; a bit line driver coupled to the bit line selector to drive the bit line selector: a memory control circuit coupled to the supply-voltage input, the charge-pump output, to the voltage-regulator output, to the word-line driver, and to the bit-line selector, the memory control circuit configured to receive a read/write signal and to selectively couple one of the charge-pump output and the supply-voltage input node to the word line driver and the bit-line selector.