Patent ID: 6972996

Claim:
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, the memory cell array having a plurality of blocks wherein within each block memory cells are arranged; and a word-line select circuit including transfer transistors arranged in row and column directions, and configured so as to transfer a plurality of different voltages to word lines through a current path of the transfer transistors and select memory cells in at least one row of said plurality of blocks, the transfer transistors including a first transistor which transfers the lowest voltage of voltages applied to the word lines in a writing operation, a second transistor which transfers the highest voltage of the voltages applied to the word lines in a writing operation, and a third transistor, which is arranged between the first transistor and the second transistor, and which is applied with an intermediate voltage between the highest voltage and the lowest voltage during a writing operation.