Patent ID: 7929359

Claim:
A dynamic random access memory (DRAM) circuit for storing a logic high state or a logic low state comprising: a p-type semiconductor region; an n-well located in the p-type semiconductor region; a p-channel access transistor having a first p-type source/drain region and a second p-type source/drain region located in the n-well; a capacitor coupled to the second p-type source/drain region of the access transistor, the capacitor including a conductor overlying a portion of the n-well, wherein a p-type oxidation enhancing implant is located below a gate dielectric of the capacitor; and a wordline driver connected to a gate terminal of the access transistor, the wordline driver being configured to apply a first voltage to the gate terminal of the access transistor when the DRAM circuit is not being accessed, the first voltage being a positive power supply voltage.