Patent ID: 8917567

Claim:
A semiconductor device comprising a memory cell array having a hierarchical bit line structure, the device comprising: a first global bit line; a first local bit line corresponding to the first global bit line; a first hierarchical switch controlling an electrical connection between the first global bit line and the first local bit line; a sense amplifier amplifying a signal voltage of the first global bit line; a precharge voltage generating circuit generating a precharge voltage; a first precharge circuit supplying the precharge voltage to the first global bit line, the precharge voltage being supplied from the precharge voltage generating circuit through a first line; a second precharge circuit supplying the precharge voltage to the first local bit line, the precharge voltage being supplied from the precharge voltage generating circuit through a second line; and a control circuit controlling the first hierarchical switch, and the first and second precharge circuits; wherein, in a precharge operation of the first local bit line and the first global bit line that are in a state of being electrically connected to each other through the first hierarchical switch, the control circuit is configured to activate the first precharge circuit so that while the first precharge circuit is activated, the precharge voltage is supplied to the first global bit line through the first line and is supplied to the first local bit line through the first global bit line and the first hierarchical switch, and after a lapse of a predetermined time from when the precharge voltage is supplied to the first local bit line through the first global bit line and the first hierarchical switch, the control circuit is configured to activate the second precharge circuit so that the precharge voltage is supplied to the first local bit line through the second line, and the predetermined time is set to a time necessary from activation of the first precharge circuit until a potential of the first local bit line converges to the precharge voltage, wherein the control circuit is configured to electrically disconnect between the first global bit line and the first local bit line h inactivating the first hierarchical switch prior to activating the second precharge circuit after the lapse of the predetermined time.