Patent ID: 7692230

Claim:
A memory cell structure, comprising: a memory stack having a bottom electrode and a top electrode; a conductive extender electrically connected to the bottom electrode and having an extending portion laterally extending from the memory stack, the memory stack formed on a main portion of the extender; a data control line for controlling a memory state of the memory stack and formed directly vertically beneath the memory stack and the main portion of the extender, but not in electrical contact with the memory stack or the main portion of the extender; an under-metal layer formed directly vertically beneath at least a portion of the extending portion and directly vertically beneath at least a portion of the data control line, the under-metal layer electrically coupled to a switching device for reading the memory state of the memory stack; and a via structure directly connecting the extending portion to the under-metal layer, and formed directly and laterally adjacent to the data control line.