Patent ID: 7489754

Claim:
An integrated circuit, comprising: a counter circuit adapted to register counts based on a target signal to generate a count value; and a control circuit adapted to control the generation of the count value in the counter circuit based on a reference signal, wherein: the counter circuit is adapted to register more than one count per period of the target signal and generate the count value based on two or more phases of the target signal; the generated count value is related to a frequency difference between the target and reference signals; the counter circuit comprises: a first target counter adapted to register counts based on occurrences of a first phase of the target signal to generate a first count number; a second target counter adapted to register counts based on occurrences of a second phase of the target signal to generate a second count number; and a multiplexer adapted to select a value from the first and second count numbers to generate the count value; and the control circuit comprises a reference counter adapted to, based on the reference signal, generate a control signal applied to the first and second target counters and to a pointer circuit, wherein the pointer circuit is adapted to control the value selection in the multiplexer based on said control signal.