Patent ID: 8351290

Claim:
A memory device comprising: a memory including a plurality of nonvolatile memory cells; and a memory controller comprising an encoder configured to (i) receive user write data and (ii) encode the user write data to generate encoded data, wherein the encoder includes an inserter to insert an indicator in the user write data prior to encoding the user write data, wherein the inserted indicator indicates whether or not the encoded data is in an erased state, wherein data stored in the memory is in the erased state if the data is intended to erase a section of the memory in which the data is stored, and wherein the encoded data is stored in the memory, and a decoder configured to (i) read the encoded data from the memory, (ii) generate user read data from the encoded data read from the memory, wherein the decoder includes a count detector configured to (i) count a number of 1's in the encoded data read from the memory, (ii) determine that the encoded data is in the erased state if the counted number of 1's is less than a threshold, wherein the user write data has N number of data bits, wherein N is an integer, and wherein the threshold is equal to N/2.