Patent ID: 7617435

Claim:
A decoding system, configured to decode forward error correction (FEC) encoded data that has been encoded using a concatenated Reed-Solomon code and trellis code scheme, comprising: trellis decoder circuitry configured to process the encoded data according to path portions of at least one trellis graph; order restoring circuitry coupled to an output of the trellis decoder circuitry configured to restore ordering of symbols in the encoded data; Reed-Solomon error detection and correction circuitry coupled to an output of the order restoring circuitry, configured to process block-based error correcting codes in data from the trellis decoder circuitry to detect and correct errors in the FEC encoded data, and further configured to provide a hard-decision output as an output of the decoding system; and reordering circuitry coupled to an output of the Reed-Solomon error detection and correction circuitry and configured to reorder the hard-decision output and to provide the reordered hard-decision output to the trellis decoder circuitry; wherein the trellis decoder circuitry is configured to choose one or more path portions of the at least one trellis graph indicated by the hard-decision output from the Reed-Solomon error detection and correction circuitry, and wherein an output of the trellis decoder circuitry depends, at least in part, on the chosen one or more path portions.