Patent ID: 7515461

Claim:
A memory device, comprising: a memory cell coupled to a bit line and a word line and including phase change material having a data state associated therewith; a sense amplifier defining a sensing node; circuitry to selectively place the bit line in signal communication with the sensing node, defining a selected bit line; a current source to produce a read current; a switch coupled to selectively apply the read current to the sensing node; and circuitry coupled to the switch and responsive to a signal from the selected bit line to control a quantity of energy to which the phase change material in the memory cell associated with the selected bit line is subjected to in the presence of the read current so that the data state remains consistent, wherein the sense amplifier includes a reference input, and circuitry to supply a reference voltage having a plurality of values to the reference input, and the sense amplifier is adapted to sense a voltage on the sensing node relative to said plurality of values in a sensing sequence to detect multiple bits of data from a selected memory cell.