Patent ID: 8116121

Claim:
A static random access memory cell, comprising: two non-planar pass-gate transistors on a semiconductor substrate, each of the two non-planar pass-gate transistors comprising one or more non-planar pass-gate fins; two non-planar pull-up transistors on the semiconductor substrate, each of the two non-planar pull-up transistors comprising one or more non-planar pull-up transistor fins; two non-planar pull-down transistors on the semiconductor substrate, each of the two non-planar pull-down transistors comprising one or more non-planar pull-down transistor fins; and two assist-bars on the semiconductor substrate, each of the two assist bars comprising one or more assist-bar fins extending parallel to the one or more non-planar pass gate fins of at least one of the two non-planar pass-gate transistors, the one or more non-planar pull-up transistor fins of at least one of the two non-planar pull-up transistors and the one or more non-planar pull down transistor fins of at least one of the two non-planar pull-down transistors and the two assist-bars electrically connecting a portion of the one or more fins of at least one of the two non-planar pull-up transistors and a portion of the one or more fins of at least one of the two non-planar pull-down transistors, wherein the two assist-bars are provided in a same layer level as the one or more non-planar pull-up transistor fins and the one or more non-planar pull-down transistor fins.