Patent ID: 8692350

Claim:
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first principal surface and a second principal surface; a diffusion layer of the second conductivity type in a planar lattice pattern on the first principal surface; a V-groove formed on a side of the second principal surface in a planar lattice pattern with the same pitch as that of the planar lattice pattern of the diffusion layer and including a bottom surface parallel to the second principal surface and exposing the diffusion layer, and a tapered side surface rising from the bottom surface; a semiconductor layer of the second conductivity type on the second principal surface surrounded by the tapered side surface; and an isolation layer of the second conductivity type formed on the side surface of the V-groove, the isolation layer electrically connecting the diffusion layer of the second conductivity type on the side of the first principal surface and the semiconductor layer of the second conductivity type on the second principal surface, wherein the V-groove has a chamfered configuration around an intersection between a corner part of the side surface of the V-groove and the bottom surface of the V-groove.