Patent ID: 7166898

Claim:
A semiconductor device comprising: a substrate; a plurality of doped silicon regions disposed on the substrate; a plurality of metal layers disposed above the substrate, including a first metal layer and a second metal layer; a plurality of discrete conductive pad areas formed in the first metal layer and arranged in a first pattern that repeats in two dimensions and has a first pitch, the first metal layer being disposed on the doped silicon regions and being the one metal layer of the plurality of metal layers closest to the doped silicon regions, each conductive pad area directly electrically connected to a plurality of doped silicon regions; and a plurality of discrete translation traces formed in the second metal layer, each translation trace having a solder element attached thereto and being electrically connected to a plurality of conductive pad areas, the solder elements arranged in a second pattern that repeats in two dimensions and has a second pitch; wherein the plurality of metal layers further contains zero, one, or two additional metal layers disposed between the first metal layer and the second metal layer.