Patent ID: 7552318

Claim:
A microprocessor which commits results of non-speculative instructions to at least one architected facility, comprising: multiple execution units; architected registers which store operand data used by said execution units; dispatch logic which detects the occurrence of a stall condition during execution of program instructions by said execution units, speculatively executes one or more pending instructions which include at least one branch instruction during the stall condition, determines the validity of data utilized by the speculative execution, and maintains a vector of dirty bits to track the validity of the pending instructions, wherein dirty bits in the vector are initially set to “0” and a given one of the dirty bits is set to “1” when a corresponding instruction passes a writeback stage where a result calculated by one of said execution units is provided to one of said architected registers; an instruction queue; and a branch prediction unit which predicts a path of the branch instruction prior to said detecting of the occurrence of the stall condition, and fetches predicted instructions from the predicted path into said instruction queue, wherein said dispatch logic speculatively flushes the predicted instructions from the instruction queue in response to said executing of the branch instruction when the dirty bit for the branch instruction is set to “0”.