Patent ID: 7225372

Claim:
A testing board comprising: a plurality of sockets in which a plurality of semiconductor memories to be tested are adapted to be mounted respectively; a testing circuit for generating first data and first addresses used for a first test in accordance with a first predetermined algorithm to the plurality of semiconductor memories; a buffer circuit having a buffer memory for holding the first data generated by the testing circuit and a comparison and judgment circuit for comparing the first data stored in the buffer memory with second data read from the semiconductor memory being adapted to be mounted in the socket to detect whether the first and second data are coincident with each other or not, terminals for connecting the testing circuit to an external control apparatus, and wiring for electrically connecting the plurality of sockets, the buffer circuit, the testing circuit and the terminals, wherein the testing circuit comprises: a volatile memory for storing third data forming a basis for generating fourth data used in a second test using a test pattern having no regularity to the plurality of semiconductor memories, and data generating means for reading out the third data from the volatile memory to generate the fourth data for the second test.