Patent ID: 7953782

Claim:
A digital frequency generator that produces an output frequency relative to a reference clock, a device including: a reference clock signal having cycles, a numerator accessible in memory, a denominator accessible in memory, an accumulator stage coupled to the reference clock, the numerator and the denominator, that iteratively signals a terminal condition signal and a remainder signal after a number of cycles that it would take to reach an overflow condition by repeatedly accumulating the numerator and overflowing an accumulator that has a range from zero to the denominator minus one; a selector, coupled to the terminal condition signal and the remainder signal of the accumulator stage, including a state machine and an output section, wherein the state machine transitions, responsive to the terminal condition signal, through (a) a low value state, (b) a rising intermediate value state, (c) a high value state, (d) a falling intermediate value state, and circularly to (a) the low value state; wherein the output section outputs a value signal responsive to the state machine, (a) outputting a low value responsive to the low value state, (b) outputting a rising intermediate value, during the rising intermediate value state and responsive to the remainder signal, (c) outputting a high value responsive to the high value state, and (d) outputting a falling intermediate value, during the falling intermediate value state and responsive to the remainder signal, wherein the output section further outputs a binary rising-or-falling signal responsive to the state machine, a digital to analog converter (abbreviated DAC) coupled to the value signal and the rising-or-falling signal of the selector, wherein the DAC outputs an analog signal responsive the value signal with an offset responsive to the rising-or-falling signal; a filter coupled to the analog signal, outputting a filtered analog signal; and a comparator coupled to the filtered analog signal and outputting a stream of pulses.