Patent ID: 7984406

Claim:
A computer-implemented timing verification method for obtaining a delay time for a signal propagated through a signal path and performing timing verification, the method comprising: storing, in a storage unit, a table including a wiring resistance variation amount and a wiring capacitance variation amount that are in accordance with a geometry deviation of a wire from a reference geometry; extracting, by a processing circuit, a wiring structure of the signal path from the storage unit; extracting, by the processing circuit, a wiring resistance variation amount and a wiring capacitance variation amount that correspond to the extracted wiring structure from the table; generating, by the processing circuit, an on-chip-variation coefficient from the extracted wiring resistance variation amount and the wiring capacitance variation amount; calculating, by the processing circuit, the delay time for the signal propagated through the signal path based on the generated on-chip-variation coefficient; dividing, by the processing circuit, a wire that forms the signal path into segments having the reference geometry; and setting, by the processing circuit, for each segment, the number of segments in a local zone that includes said segment as a wiring density of the location at which the segment is formed; wherein the table includes a first table containing wiring resistance variation amounts respectively corresponding to wiring densities at locations where the segments are formed and a second table containing wiring capacitance variation amounts respectively corresponding to wiring densities at locations where the segments are formed, with the wiring resistance variation amount and the wiring capacitance variation amount being extracted from the first and second tables.