Patent ID: 7191311

Claim:
A method of interconnecting L processors of a parallel computer to facilitate torus partitioning, where each of the processors comprises a processing unit and a switch, where the switch comprises a first external port, a second external port, a third external port, a fourth external port, a first internal port, and a second internal port, where the L processors comprise R non-overlapping partitions, where each of the partitions comprises the processing unit of at least one of the processors, and where L is an integer ≧2 and R is an integer ≧1, the method comprising: connecting the L switches of the L processors among the external ports of the L switches in an extended torus architecture; and setting the connected L switches thereby interconnecting each of the partitions as a torus, wherein the setting comprises computing the span of the partition, wherein the computing comprises finding the minimum coordinate, MIN, in the partition, determining the maximum coordinate, MAX, in the partition, setting the span of the partition to be equal to the set of coordinates i, where MIN≦i≦MAX, where i is an integer, if the span of the partition contains exactly two coordinates, where i and i+1 are the two coordinates that belong to the span, if the span of the partition contains exactly two coordinates, where i and i+1 are the two coordinates that belong to the span, if i=1, connecting the third external port and the second internal port (E 3 ,I 2 ) of the first switch, connecting the first external port and the first internal port (E 1 ,I 1 ) of the first switch, connecting the second external port and the second internal port (E 2 ,I 2 ) of the second switch, and connecting the first external port and the first internal port (E 1 ,I 1 ) of the second switch; if i=L−1, connecting the third external port and the first internal port (E 3 ,I 1 ) of the (L−1)th switch, connecting the fourth external port and the second internal port (E 4 ,I 2 ) of the (L−1)th switch, connecting the second external port and the first internal port (E 2 ,I 1 ) of the Lth switch, and connecting the fourth external port and the second internal port (E 4 ,I 2 ) of the Lth switch; and otherwise, where 2≦i≦L−2, connecting the third external port and the fourth external port (E 3 ,E 4 ) of the (i−1)th switch, connecting the second external port and the first internal port (E 2 ,I 1 ) of the ith switch, connecting the third external port and the second internal port (E 3 ,I 2 ) of the ith switch, connecting the first external port and the first internal port (E 1 ,I 1 ) of the (i+1)th switch, and connecting the second external port and the second internal port (E 2 ,I 2 ) of the (i+1)th switch.