Patent ID: 7294545

Claim:
A method of manufacturing a memory cell defined along first, second, and third orthogonal dimensions, said method comprising the steps of: forming, along said first dimension, one-half of a bit line contact feature, one word line feature, one word line space feature, and one-half of a field poly line feature; forming, along said second dimension, two one-half field oxide features and one active area feature such that said first and second dimensions define a 6F 2 memory cell; forming said bit line contact feature such that it is characterized by a bit line contact hole bounded by insulating side walls; filling said bit line contact hole with a conductively doped polysilicon plug such that said bit line contact hole plug defines an upper plug surface profile, wherein said bit line contact hole is filled with said doped polysilicon plug by partially filling said bit line contact hole through an initial deposition technique and subsequently topping off said partial fill through selective doped polysilicon growth; forming a storage node such that it is characterized by a storage node contact hole bounded by insulating side walls; and filling said storage node contact hole with a conductively doped polysilicon plug such that said storage node plug defines an upper plug surface profile.