Patent ID: 8073668

Claim:
An integrated circuit (IC) test system, comprising: a test manager information handling system (IHS) that includes a system memory that stores a full system model for a device under test integrated circuit (DUT IC), the full system model including a support memory; a hardware accelerator simulator, coupled to the test manager IHS via an interface bus, the hardware accelerator simulator including a hardware accelerator memory; the test manager IHS being configured to transmit the full system model to the hardware accelerator simulator; the hardware accelerator simulator being configured to map the full system model to the hardware accelerator memory so that the hardware accelerator simulator emulates the full system model, thus providing a mapped hardware accelerator simulator that emulates the DUT IC as an emulated DUT IC and emulates the support memory as an emulated memory, the full system model including a plurality of fault injection points; the test manager IHS being configured to load an architecture verification program (AVP) into the emulated memory, the AVP testing the full system model for results of injected faults, and to select a subset of the plurality of fault injection points for fault injection, thus providing a plurality of selected fault injection points, wherein the test manager IHS selects the subset of the plurality of fault injection points for fault injection at the same time that the hardware accelerator simulator maps the full system model into the hardware accelerator; and the mapped hardware accelerator simulator being further configured to inject a fault into a selected fault injection point of the plurality of selected fault injection points in the full system model when commanded by the test manager IHS, and to transmit to the test manager IHS for storage a result of injecting the fault into the selected injection point, the mapped hardware accelerator simulator being further configured to inject faults at other selected fault injection points to provide respective results.