Patent ID: 7149954

Claim:
An apparatus for conducting bench testing of data fields, comprising: a memory configured to store a number representative of the number of data fields to be analyzed; a hardware module coupled, at least indirectly, to the memory and configured to (i) receive an input data stream, (ii) perform a cyclic redundancy checksum (CRC) processing on the received data stream, and (iii) produce an output representative of an actual number of received data fields analyzed, wherein the input data stream includes synchronization markers defining boundaries of each of the received data fields; a comparator configured to (i) compare the number stored in memory and the actual number of received data fields for which CRC has been processed and (ii) produce a disabling signal when the actual number matches the number stored in the memory; and a detector coupled to the comparator and configured to (i) receive the input data stream and sense the synchronization markers, (ii) receive the disabling signal, and (iii) disable the module when the disabling signal is received.