Patent ID: 7591067

Claim:
A method for manufacturing a thermally enhanced coreless thin substrate with an embedded chip, comprising: providing a carrier metal layer; attaching at least one chip to the carrier metal layer, wherein the chip has a plurality of electrodes; forming a first dielectric layer on the carrier metal layer and covering the chip, wherein the first dielectric layer has a plurality of through holes, the through holes are linked to the carrier metal layer, and the first dielectric layer exposes the electrodes; forming a first wiring layer on the first dielectric layer, wherein the first wiring layer comprises a plurality of first trace lines and a plurality of second trace lines, the first trace lines is electrically connected to the carrier metal layer via the through holes and the second trace lines are electrically connected to the electrodes; and patterning the carrier metal layer so that the carrier metal layer comprises a heat sink portion attached to the chip.