Patent ID: 7173874

Claim:
A multi-port memory having a common memory interface and a plurality of memory ports through with the memory is accessed, the multi-port memory including first and second memory cell arrays, the multi-port memory comprising: a first address decoder circuit coupled to the first memory cell array and configured to decode first address signals for accessing memory cells of the first memory cell array; a first input/output (I/O) circuit coupled to the first memory cell array, the first address decoder circuit, and a first one of the plurality of memory ports, the first I/O circuit configured to couple data between the first memory cell array and the first one of the plurality of memory ports in response to accessing memory cells of the first memory cell array through the first one of the plurality of memory ports; a second address decoder circuit coupled to the second memory cell array and configured to decode second address signals for accessing memory cells of the second memory cell array; a second I/O circuit coupled to the second memory cell array, the second address decoder circuit, and the a second one of the plurality of memory ports, the second I/O circuit configured to couple data between the second memory cell array and the second one of the plurality of memory ports in response to accessing memory cells of the second memory cell array through the second one of the plurality of memory ports; a third address decoder circuit coupled to the first and second memory cell arrays and configured to decode third address signals for accessing memory cells of the first or second memory cell array, the third address decoder circuit decoding the same number of address signals for accessing memory cells of the first memory cell array as for accessing the memory cells of the second memory cell array; and a third I/O circuit coupled to the first and second memory cell arrays, the third address decoder, and the common memory interface, the third I/O circuit configured to couple data between memory cells of either the first or second memory cell array and the common memory interface in response to accessing memory cells of the first or second memory cell array through the common memory interface.