Patent ID: 7805477

Claim:
Computing circuits for running an audio decoding algorithm on programmable processors comprising: a program control device ( 110 ) for generating an operation start signal of the MPEG-2 or MPEG-4 AAC algorithm and controlling the programmable processor; a program memory ( 150 ) for storing application programs of the programmable processor; an inverse address ( 130 ) calculating unit for generating inverse addresses of the input data in MDCT or IMDCT operations of the MPEG-2 or MPEG-4 AAC algorithm; a data memory ( 160 , 170 ) for storing operations data; an address generator ( 120 ) for calculating the addresses of the data memory ( 160 , 170 ) by use of inverse addresses generated by the inverse address calculating unit ( 130 ); a data ROM ( 180 , 190 ) for storing cosine and sine data; a data processing device ( 140 ) for performing arithmetic and logic operations using the data memory ( 160 , 170 ) and the data ROM ( 180 , 190 ); and a state register for running the MPEG-2 or MPEG-4 decoding operations.