Patent ID: 7053495

Claim:
A semiconductor integrated circuit device comprising: a substrate; an interlevel dielectric film formed over the substrate; an external-component-connecting wire made of a first metal film and formed in a first groove provided in the interlevel dielectric film; a fuse wire made of the first metal film and formed on a second groove provided in the interlevel dielectric film; a target mark made of the first metal film and formed in a third groove provided in the interlevel dielectric film; a dielectric film formed over the interlevel dielectric film to cover the target mark; a pad electrode made of a second metal film, formed directly on the dielectric film and connected to the external-component-connecting wire, and a pad-electrode alignment mark for use in alignment relative to the pad electrode, the pad-electrode alignment mark being formed on the dielectric film and made of the second metal film, wherein the target mark and the pad-electrode alignment mark are substantially L-shaped in plan view, and the substantially L-shaped target mark and pad-electrode alignment mark overlap at their elbows in plan view, and the target mark is formed in a same layer as the fuse wire provided below the pad electrode, and is used as an alignment mark during laser machining for blowing the fuse wire.