Patent ID: 6967147

Claim:
A process for forming dual gate oxides for use in high performance DRAM systems or logic circuits, the process comprising using a shadow area to control gate oxide thickness at active area (AA) corners adjacent a shallow trench isolation (STI) region, the process comprising: providing a substrate having formed thereon an active area and the shallow trench isolation, the shallow trench isolation being filled with an oxide material having an exposed surface protruding above adjacent areas of the substrate; affecting a first low dose angled nitrogen implant into the substrate at an angle such that a shadow area is formed adjacent to the oxide material, the nitrogen dose in the shadow area of the active area being less than the amount of the nitrogen dose implanted in the remaining non-shadowed area; affecting a first mask so that nitrogen ions (N 2 + ) to be implanted do not penetrate a masked region; and affecting a second nitrogen ion implantation by employing a second shadow area inducing means at a temperature sufficient to provide a lesser amount of nitrogen ion dosage in the second shadow area of the active area is less than the amount of nitrogen dose implanted in the remaining non-shadowed area.