Patent ID: 8555097

Claim:
A reconfigurable processor, comprising: a plurality of processing units, each of which includes: a functional unit; a distributed configuration memory which stores a plurality of configuration information of the functional unit; a no-operation (NOP) register which stores information which represents whether or not a NOP operation is performed at a respective clock cycle; and a controller configured to manage a first pointer which points to an entry of the NOP register, to activate or deactivate the distributed configuration memory based on an entry of the NOP register to which the first pointer points at the respective clock cycle, and to manage a second pointer which points to a configuration information from among the plurality of configuration information stored in the distributed configuration memory, wherein the functional unit performs an operation based on the configuration information from the distributed configuration memory which is pointed to by the second pointer, at the respective clock cycle, while the distributed configuration memory is activated, and performs a NOP operation when the distributed memory is deactivated such that the functional unit does not read configuration information when the functional unit performs the NOP operation.