Patent ID: 8742967

Claim:
An analog to digital converter generating a plurality of corresponding voltages in response to a plurality of values of a grey level, wherein the grey level includes k bits with k being a natural number larger than 1, and the analog to digital converter comprises: a decoding device, comprising: a first decoding circuit, for providing a first output voltage, a second output voltage and a third output voltage substantially having the same level when w most significant bits (MSBs) of the grey level all correspond to the same logic value; a second decoding circuit, for providing a first intermediate voltage in response to x MSBs next to the w MSBs when the w MSBs correspond to different logic values; a logic operation circuit, for generating a first logic control signal, a second logic control signal and a third logic control signal according to the x MSBs and y MSBs next to the x MSB; a third decoding circuit, for providing a second intermediate voltage in response to the x MSBs and the first to the third logic control signals when the w MSBs correspond to different logic values; and a fourth decoding circuit, for selectively having the first output voltage equal to one of the first and the second intermediate voltages, selectively having the second output voltage equal to one of the first and the second intermediate voltages, and selectively having the third output voltage equal to one of the first and the second intermediate voltages according to the y MSBs and z MSBs next to the y MSBs when the w MSBs correspond to different logic values; and an operational amplifier, for generating a pixel voltage according to the first to the third output voltages; wherein, the level of the pixel voltage ranges between the first and the second intermediate voltages when the w MSBs correspond to different logic values; wherein, w, x, y and z are natural numbers satisfying the condition: w+x+y+z≦k.