Patent ID: 7411850

Claim:
A semiconductor storage device comprising: information memory cells; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell provided in the memory cell array; a reference bit line connected to the reference memory cell which stores one of digital data “0” or “1” and not connected to a reference memory cell storing the other digital data “0” or “1”; and sense amplifiers connected to the information bit lines and the reference bit line, one of the sense amplifiers using a reference voltage generated by using only the single kind of digital data among digital data “0” and “1”, the reference voltage having a middle potential between a potential of a bit line transmitting data “0” and a potential of a bit line transmitting data “1”; first select transistors connected between the information bit lines and the sense amplifiers; a second select transistor connected between the reference bit line and the sense amplifiers; first load current transistors connecting a power source to the information bit lines; and a second load current transistor connecting the power source to the reference bit line, wherein the memory cell array includes a single reference memory cell and a single reference word line, to which only the single reference memory cell is connected in the memory cell array, and wherein the information word lines and single reference word line are selected during data readout from one of the information memory cells, the data of the single reference memory cell being used to generate a reference potential.