Patent ID: 7888214

Claim:
A method of fabrication of a semiconductor device comprising: providing a substrate having a PMOS region and a NMOS region; providing a PMOS transistor in the PMOS region and a NMOS transistor in the NMOS region, wherein the PMOS transistor comprises a PMOS gate, PMOS gate dielectric, PMOS channel and PMOS S/D regions, and the NMOS transistor comprises a NMOS gate, NMOS gate dielectric, NMOS channel, and NMOS S/D regions; forming a stress layer having a first stress over the substrate, the stress layer covering the PMOS region and the NMOS region; forming a dielectric layer over the stress layer; forming PMOS S/D contact holes having a PMOS S/D contact layout design through the stress layer in the PMOS region to expose portions of the PMOS S/D regions and NMOS S/D contact holes having a NMOS S/D contact layout design through the stress layer in the NMOS region to expose portions of the NMOS S/D regions, wherein the PMOS S/D contact hole layout design is based on PMOS stress considerations and has a PMOS S/D contact hole area, the PMOS S/D contact layout design comprises adapting size, shape, number or location or a combination thereof of the PMOS S/D contact holes to cause the stress layer with the first stress to induce a first desired stress on the PMOS channel based on the PMOS stress considerations, the NMOS S/D contact hole layout design is based on NMOS stress considerations and has a NMOS S/D contact hole area, and the NMOS S/D contact layout design comprises adapting size, shape, number or location or a combination thereof of the NMOS S/D contact holes to cause the stress layer with the first stress to induce a second desired stress on the NMOS channel based on the NMOS stress considerations, wherein the PMOS S/D contact hole area is larger than the NMOS S/D contact hole area or the PMOS S/D contact holes are closer to the PMOS gate than the NMOS S/D contact holes are to the NMOS gate or a combination thereof, and the first desired stress is different from the second desired stress; and forming contact plugs in the PMOS contact holes and the NMOS contact holes.