Patent ID: 6943396

Claim:
An integrated circuit including a plurality of electro-static discharge (ESD) protection circuits comprising: a semiconductor substrate; a plurality of trenches formed in the semiconductor substrate; a node electrode filling the lower portion of each trench of said plurality of trenches; a plurality of doped buried source regions, one each adjacent each of said plurality of trenches at an intermediate level; a plurality of drain regions formed on the surface of said semiconductor substrate and between adjacent ones of said plurality of trenches; at least one vertical transistor formed partially in an upper portion of each of said plurality of trenches, each of said vertical transistors further comprising one of said plurality of drain regions and one of said doped buried source region; a plurality of doped buried plate regions, one each located adjacent the lower portion of each one of said plurality of trenches; a group of electronic circuits other than ESD protection circuits formed in a first group of said plurality of trenches, said group of electronic circuits comprising a first group of said vertical transistors connected to said node electrode and said doped buried plate region of said trench, said node electrode and said doped buried plate region connected to form a capacitor; and a group of ESD protection circuits formed in a second group of said plurality of trenches, said group of ESD protection circuits comprising a second group of said vertical transistors and said doped buried plate region adjacent said trenches, said doped buried source region of said second group of transistors extended so as to be in electrical contact with said doped buried plate region.