Patent ID: 7562272

Claim:
A circuit, comprising: a phase-locked loop (PLL) circuit; an electrical fuse (eFuse) array coupled to the PLL circuit; a control unit coupled to the eFuse array, wherein the control unit comprises: an eFuse controller; a power-on reset (POR) engine coupled to the eFuse controller, wherein the POR engine includes logic that, in response to receiving a reset signal, sends a control signal to the eFuse controller to sense data values from eFuses in the eFuse array to thereby generate sensed data; and logic that provides control signals to the eFuse array to cause the eFuse array to provide configuration data to the PLL circuit to thereby configure the PLL circuit to operate with a particular set of characteristics; a latch coupled to the control unit, wherein the sensed data from the eFuses in the eFuse array are provided to the latch, and wherein the latch provides the sensed data to the PLL circuit; a decoder coupled to the PLL circuit and the latch, and wherein a portion of the sensed data from the eFuses is provided to the decoder which decodes the portion of the sensed data to thereby generate decoded data, and wherein the decoder provides the decoded data to the PLL circuit; a scan latch coupled to the latch and the eFuse array, wherein the scan latch scans- in the sensed data from the eFuse array and provides the sensed data to the latch in response to the latch receiving a control signal from the POR engine; and a clock select multiplexer having a first input for receiving a reference clock and a second input for receiving an output from the PLL circuit, wherein: the control unit has logic that sends a clock select signal to the clock select multiplexer to select either the reference clock or the output from the PLL circuit, the control unit has logic that sends a first clock select signal to the clock select multiplexer to select the reference clock prior to the PLL circuit being configured by the configuration data from the eFuse array, and the control unit has logic that sends a second clock signal to the clock select multiplexer to select the output of the PLL circuit after the PLL circuit has been configured by the configuration data from the eFuse array.