Patent ID: 7616491

Claim:
A semiconductor memory device comprising: first and second NAND units in which a plurality of memory cells are arranged in a row and a column, and the plurality of memory cells arranged in the column is connected in series; a first bit line shared by the first and second NAND units; first and second selection transistors connected in series between the first bit line and the first NAND unit, wherein the first selection transistor has a first threshold voltage and a first signal is supplied to its gate, and the second selection transistor has a second threshold voltage higher than the first threshold voltage and a second signal is supplied to its gate; third and fourth selection transistors connected in series between the first bit line and the second NAND unit, wherein the third selection transistor has the second threshold voltage, and the first signal is supplied to its gate, and the fourth selection transistor has the first threshold voltage, and the second signal is supplied to its gate; and a control unit which changes a voltage potential of the first and the second signals and a voltage potential of the first bit line from a first level to a second level higher than the first level in writing data into a memory cell of the first NAND unit, and changes the voltage potential of the first bit line from the second level to the first level after changing the voltage potential of the first signal from the second level to the first level, the control unit applying a negative voltage to a substrate in writing the data into a memory cell of the second NAND unit after discharging of the first bit line, and the control unit which applies a write voltage to a selected word line, and applies a voltage potential of a third level higher than the second level and lower than the write voltage to an unselected word line after supplying the negative voltage to a substrate.