Patent ID: 8879333

Claim:
A three-dimensional non-volatile memory device, comprising: a plurality of word lines comprising conductive material, the conductive material alternates with dielectric material in a stack; a plurality of memory cells arranged in a plurality of NAND strings, each NAND string comprising a select gate drain (SGD) transistor at a drain-side end of the NAND string; a set of bit lines in communication with the drain-side ends of the NAND strings; a set of SGD lines in communication with the SGD transistors of the NAND strings; and a control circuit, the control circuit: performs one erase iteration of an erase operation for the plurality of memory cells in which the plurality of memory cells is not inhibited from being erased, and after the one erase iteration, performs a verify test using a first verify condition, the verify test using the first verify condition is passed by a first subset of memory cells in the plurality of memory cells and is not passed by second and third subsets of memory cells in the plurality of memory cells; performs another erase iteration of the erase operation in which the first subset of memory cells is inhibited from being erased while the second and third subsets of memory cells are not inhibited from being erased, and after the another erase iteration, performs a verify test using a second verify condition, the verify test using the second verify condition is passed by the second subset of memory cells but not by the third subset of memory cells; and performs an additional erase iteration of the erase operation in which the first and second subsets of memory cells are inhibited from being erased while the third subset of memory cells is not inhibited from being erased, and after the additional erase iteration, performs a verify test using a third verify condition, the verify test using the third verify condition is passed by the third subset of memory cells.