Patent ID: 6847542

Claim:
An SRAM cell comprising: a first inverter comprising a first load element and a first driver NMOSFET; a second inverter comprising a second load element and a second driver NMOSFET and having input and output terminals cross-coupled to output and input terminals of the first inverter, respectively; a first transfer gate NMOSFET having a drain-to-source path inserted between the output terminal of the first inverter and a first bit line and a gate connected to a word line; and a second transfer gate NMOSFET having a drain-to-source path inserted between the output terminal of the second inverter and a second bit line and a gate connected to the word line, wherein a current drivability of the first inverter and the first transfer gate NMOSFET for the first bit line is set to be larger than a current drivability of the second inverter and the second transfer gate NMOSFET for the second bit line.