Patent ID: 7629821

Claim:
A semiconductor memory device comprising: a phase comparator for comparing a phase of a reference clock with that of a feedback clock; a delay chain for delaying the reference clock to output a delayed version of the reference clock; a delay controller for controlling a delay value of the delay chain in response to a comparison result of the phase comparator; a fine delay chain for finely adjusting the delayed version of the reference clock and outputting a finely delayed version of the reference clock; a delay model for delaying the finely delayed version of the reference clock outputted from the fine delay chain by a modeled delay value to provide a delayed clock as the feedback clock; a locking state detector for generating a locking variation signal corresponding to a phase difference between the reference clock and the feedback clock; and a fine delay controller for controlling a fine adjustment value of the fine delay chain in response to an output of the delay controller and the comparison result of the phase comparator, wherein a fine adjustment period of the fine delay chain is adjusted in response to the locking variation signal.