Patent ID: 8283728

Claim:
A semiconductor device comprising: a power supply line supplied with a power supply voltage; a power supply node connected with said power supply line; a ground line; a ground pad connected with said ground line; a signal input pad; a main protection circuit section configured to discharge an ESD surge applied to a first pad as one of said power supply node, said signal input pad and said ground pad to a second pad as another thereof; a protection object circuit; a connection node connected with said protection object circuit; a first resistance element connected between said signal input pad and said connection node; and a sub protection circuit section, wherein said sub protection circuit section comprises: a least one of a first PMOS transistor having a source connected with said connection node, a drain connected with said ground line and a gate and a back gate connected with said power supply line, and a first NMOS transistor having a source connected with said connection node, a drain connected with said power supply line and a gate and a back gate connected with said ground line.