Patent ID: 7344947

Claim:
A method of fabricating drain extended semiconductor devices comprising: designating a first region of a semiconductor body for devices having a first channel length and a second region of the semiconductor body for devices having a second channel length; selecting a common threshold voltage for the first and second regions; forming first well regions within the first region; forming second well regions within the second region; forming back gate well regions in the first and second regions according to the common threshold voltage, wherein the back gate well regions in the first and second regions are formed with an equal back gate length and dopant concentration; forming first drain extension within the first region; forming second drain extension regions within the second region; forming first gate structures within the first region according to the first channel length; forming second gate structures within the second region according to the second channel length; forming first drain regions within the first drain extension regions; forming second drain regions within the second drain extension regions; forming first source regions within the back gate well regions within the first region; and forming second source regions within the back gate well regions within the second region.