Patent ID: 7969190

Claim:
A buffer circuit comprising: a first node configured to be connected to a first circuit, wherein the first circuit is configured to operate at a first power supply voltage; a second node configured to be connected to a second circuit, wherein the second circuit is configured to operate at a second power supply voltage; an input stage circuit coupled between the first node and the second node, wherein the input stage circuit is configured to receive at least one signal from the first circuit at the first node and to provide at least one signal to the second circuit at the second node, and wherein the input stage circuit includes: a first NMOS transistor coupled to the first node; a first inverter coupled to the first NMOS transistor; a second inverter coupled between the first inverter and the second node; and a first PMOS transistor coupled to the first inverter, wherein the first PMOS transistor is configured to be connected to the second power supply voltage, wherein the first PMOS transistor includes a gate coupled to the second node; and a diode having a positive terminal and a negative terminal, wherein the negative terminal is coupled to the first node and the positive terminal is coupled to the second node; wherein the first circuit, the second circuit, and the buffer circuit are configured to be connected to a third power supply voltage.