Patent ID: 8450622

Claim:
A multilayer wiring substrate, comprising: a stacked configuration that is multilayered by alternately stacking a plurality of resin insulating layers formed with a same material as a main element and a plurality of conductor layers; a plurality of first principal surface side connection terminals that are arranged on a first principal surface of the stacked configuration; and, a plurality of second principal surface side connection terminals that are arranged on a second principal surface of the stacked configuration, wherein the plurality of conductor layers are arranged in the plurality of resin insulating layers and connected by a via conductor which expands in diameter as either the first principal surface or the second principal surface is approached, wherein, the plurality of first principal surface side connection terminals include an IC chip connection terminal, which has an IC chip as a connection target, and a passive element connection terminal, which has a passive element as a connection target and is greater in area than the IC chip connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer that is exposed at the first principal surface of the stacked configuration; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer of the uppermost outer layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer of the uppermost outer layer; wherein a surface of the resin insulating layer of the uppermost outer layer defines a reference surface; and wherein an upper face of the upper terminal part is higher than the reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.