Patent ID: 7545664

Claim:
A memory system comprising: a memory controller; and a daisy chain of memory chips further comprising at least a first memory chip and a second memory chip, each memory chip in the daisy chain of memory chips further comprising: an array capable of storing data; and a self time block configured to dynamically determine at least one access time of the array and drive at least one timing signal to the array responsive to the determination; wherein the memory controller is configured to create an address/command word and further configured to transmit the address/command word on a first point to point interconnection to the first memory chip; if the address/command word is not directed to the first memory chip, the first memory chip is configured to transmit the address/command word to the second memory chip on a second point to point interconnection; the self time block further comprising a ring oscillator having a frequency that tracks the at least one access time of the array.