Patent ID: 7663960

Claim:
A semiconductor memory, comprising: memory cells; and a voltage supply circuit that switches and outputs multiple set voltages from an output terminal and supplies a voltage to the memory cells, the voltage supply circuit comprising: a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first flag signal when detecting that the voltage outputted from the boosting circuit is not lower than the set voltage, outputs a second flag when detecting that the voltage outputted from the boosting circuit is not lower than a frequency adjusting voltage set lower than the set voltage; and a control circuit that controls an operation of the boosting circuit in response to the set voltage and the output signal of the voltage detecting circuit, wherein the control circuit controls boosting capability of the activated boosting circuit so as to reduce the boosting capability by changing a frequency of a clock signal for causing the boosting circuit to perform a boosting operation, from a first frequency to a second frequency lower than the first frequency in response to the second flag signal, controls the activated boosting circuit so as to deactivate the boosting circuit in response to the first flag signal, increases at least the second frequency when the set voltage is changed to a higher voltage, and reduces at least the second frequency when the set voltage is changed to a lower voltage.