Patent ID: 7161823

Claim:
A semiconductor dynamic random access memory (DRAM) device comprising: a memory cell array comprising a repeated row/column pattern of cell blocks, each cell block comprising a sub-memory-cell array, and a sense amplifier section and a sub-wordline driver section associated with the sub-memory-cell array; first, second, and third patterned metal layers disposed over the memory cell array, each patterned metal layer comprising a plurality of traces; and insulating layers deposited around the patterned metal layers to substantially insulate the traces except where holes in one of the insulating layers are provided to establish electrical contact to a trace; wherein the first patterned metal layer traces include a plurality of substantially parallel local Input/Output (I/O) lines, each coupled to a plurality of sense amplifier sections in cell blocks arranged in a row, a plurality of first power lines to provide memory cell array power, running substantially parallel to the local I/O lines, and a plurality of main word lines running substantially parallel to the local I/O lines, each connecting to a plurality of the sub-wordline driver sections in cell blocks arranged in a row; wherein the second patterned metal layer traces include a plurality of substantially parallel column select lines, each connecting to an input/output gate in a cell block; wherein the third patterned metal layer traces include a plurality of third power lines to provide memory cell array power; and wherein the traces in at least one of the second and third patterned metal layers further include a plurality of global I/O lines, running substantially parallel to the column select lines, each global I/O line connected to a plurality of the cell blocks to selectively multiplex a plurality of the local I/O lines onto that global I/O line.