Patent ID: 7580316

Claim:
A semiconductor memory device comprising: a memory cell array which includes a plurality of subarrays arranged in the form of a matrix, and a plurality of word lines and a plurality of bit lines connected to the subarrays, the subarray comprising a bit line driving transistor which drives the bit line, a sub-bit line connected to the gate of the bit line driving transistor, and a plurality of memory cell transistors which are connected to the sub-bit line and drive the sub-bit line according to signals from the word lines, wherein: the bit line driving transistor has a drain connected to the bit line and a source connected to a first power potential supply line; and the subarray further includes a transmission transistor, which has a gate connected to the bit line and a drain connected to the sub-bit line, and a loading transistor section which includes a loading transistor or a series circuit comprised of plural loading transistors whose gates are connected each other, and the loading transistor section, which has the series circuit, having a configuration where the gates is connected to the second power potential supply line, the outermost source is connected to the first power potential supply line, and the outermost drain is connected to the source of the transmission transistor.