Patent ID: 8582706

Claim:
A method for training a data path, comprising: instructing a first device to send a plurality of first training signals to a second device via a corresponding plurality of data lines between the first device and the second device, wherein each first training signal of the plurality of first training signals comprises a specified bit pattern that is equal to a corresponding clock signal of a system clock during transmission of that bit pattern by the first device; instructing the second device to perform: for each first training signal: for each delay setting of a plurality of delay settings: delaying reception of the first training signal by the delay setting, thereby generating a delayed first training signal; capturing signal state of the delayed first training signal via first and second flip-flops over a specified period of time, comprising: the first flip-flop capturing the signal state of the delayed first training signal on each rising edge of the system clock; and the second flip-flop capturing the signal state of the delayed first training signal on each falling edge of the system clock; wherein said capturing signal state accumulates in memory a characterization of the delayed first training signal indicating: whether a 1 was received at the first flip-flop over the specified period of time; whether a 0 was received at the first flip-flop over the specified period of time; whether a 1 was received at the second flip-flop over the specified period of time; and whether a 0 was received at the second flip-flop over the specified period of time; wherein the characterization indicates whether the delayed first training signal was received accurately over the specified period of time; analyzing the respective characterizations of the delayed first training signals; and selecting a delay setting of the plurality of delay settings for the data line of the first training signal based on the respective characterizations, wherein said selecting selects the delay setting that most substantially aligns the specified bit pattern with the clock signals of the system clock thereby removing metastability on the data line, wherein a subsequent signal transmitted on the at least one data line and received by the second device at the selected delay setting will be substantially aligned with the system clock either in phase or in an opposite phase of a clock cycle of the system clock.