Patent ID: 7241668

Claim:
A method for forming an alignment mark structure ( 148 ) for a semiconductor device, the method comprising: forming a via passage ( 128 ) having a first depth at a selected level of a substrate of the semiconductor device; forming an alignment recess ( 130 ) having a second depth greater than the first depth at the selected level of the semiconductor device substrate; forming a first metal layer ( 140 ) over said selected substrate level, within said via passage and within said alignment recess ( 130 ), wherein said via passage ( 128 ) is at least substantially filled with the first metal layer ( 140 ), and wherein said alignment recess ( 130 ) is only partially filled by said first metal layer ( 140 ); forming a second metal layer ( 142 ) over said first metal layer ( 140 ) such that said alignment recess ( 130 ) is completely filled; planarizing said second metal layer ( 142 ) and said first metal layer ( 140 ) down to said selected substrate level, thereby creating a sacrificial plug ( 144 ) of said second layer material within said alignment recess; and removing said sacrificial plug ( 144 ) in a manner so as not to substantially roughen the planarized surface at said selected substrate level.