Patent ID: 7999571

Claim:
An integrated circuit including a non-Flash non-volatile state machine, comprising: a silicon semiconductor substrate including circuitry fabricated in a logic plane of the silicon semiconductor substrate, the circuitry including a configuration device operative to provide a configuration for a state machine, and a select array electrically coupled with the configuration device and operative to receive inputs and provide outputs; and at least one memory plane in direct contact with and fabricated directly above the silicon semiconductor substrate, the at least one memory plane including a non-volatile re-writeable memory comprising a two-terminal resistivity-sensitive memory element electrically coupled with the select array and operative to receive the inputs and the configuration from the select array, the non-volatile re-writeable memory is configured to implement the state machine, wherein the non-volatile re-writable memory Includes at least one two-terminal cross-point array, each two-terminal cross-point array Including a plurality of first conductive array lines, a plurality of second conductive array lines arranged orthogonally to the plurality of first conductive array lines, and a plurality of the two-terminal resistivity-sensitive memory elements, each two-terminal resistivity-sensitive memory element is positioned between a cross-point of a unique pair of first and second conductive array lines and is electrically in series with Its respective pair of first and second conductive array lines, and wherein each two-terminal resistivity-sensitive memory element is electrically coupled with the select array through Its respective pair of first and second conductive array lines.