Patent ID: 7272671

Claim:
A data processing system with programmable addressing, comprising: at least one multifunctional input/output device operating in a logical partition environment, wherein the logical partition environment comprises a first operating system and a second operating system distinct from the first operating system; a memory coupled to the at least one multifunctional input/output device, wherein the memory contains a first set of control bits, wherein the first set of control bits allocate a first function of the multifunctional input/output devices into a first memory location of the memory, and wherein the first function is assigned to the first operating system; an address bus coupled to the at least one muitifunctional input/output device, wherein the address bus allows transmission of the control bits between the at least one multifunctional input/output device and the memory; and a programmable address control coupled to the address bus, wherein the programmable address control relocates the first set of control bits from the first memory location to a second memory location in the memory, and wherein the second memory location is inaccessible to the first operating system.