Patent ID: 7791951

Claim:
A method for operating a non-volatile memory device including a source region and a drain region defining a channel region, a gate insulation layer on the channel region, a floating gate on the gate insulation layer, a select gate electrode on the gate insulation layer and the floating gate, a control gate electrode on a sidewall of the floating gate and the gate insulation layer to be opposite to the select gate electrode, wherein the select gate electrode comprises a top select gate electrode disposed on the floating gate and a sidewall select gate electrode disposed on a sidewall of the floating gate and the gate insulation layer opposite to the control gate electrode, an intergate dielectric interposed between the select gate electrode and the floating gate, a tunnel insulation layer interposed between the control gate electrode and the floating gate, and a spacer insulation pattern interposed between the top select gate electrode and the sidewall select gate electrode and between the top select gate electrode and the control gate electrode, the method comprising: a write step in which charges are injected to the floating gate through the gate insulation layer; a read step in which fluctuation of a threshold voltage of the channel region below the floating gate, caused by charges stored in the floating gate is sensed; and an erase step in which tunneling of the charges stored in the floating gate is induced through the tunnel insulation layer.