Patent ID: 8575672

Claim:
A nonvolatile semiconductor memory device comprising: a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and respective sidewalls and arranged in a matrix of rows and columns extending in respective row and column directions; a bit line on the top surfaces of the pillars in one of the rows and connecting the pillars in the row; a word line on the sidewalls of one of the pillars in the row; and a memory layer interposed between the word line and the one of the pillars in the row; drain regions in upper portions of the plurality of pillars; and source regions beneath the plurality of pillars; wherein all the source regions are connected together in both the row and column directions; wherein a topmost surface of the word line is lower than a topmost surface of the memory layer and lower than a topmost surface of the plurality of pillars; and wherein a bottommost surface of the word line is higher than a bottommost surface of the memory layer.