Patent ID: 8503136

Claim:
A protecting circuit for reducing leakage currents, comprising: a first PMOS transistor (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor), coupled between a first voltage node and a node, and having a first gate coupled to an input node; a second PMOS transistor, coupled between the node and an output node, and having a second gate; a first NMOS transistor (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor), coupled between the output node and a ground node, and having a third gate coupled to the input node; and a second NMOS transistor, coupled between the input node and the second gate, and having a fourth gate coupled to a second voltage node, wherein the ground node provides a ground voltage, the first voltage node provides a first voltage, the second voltage node provides a second voltage, and the first and second voltages are both higher than the ground voltage.