Patent ID: 8341360

Claim:
A system comprising: a memory; a processor; a controller coupled between the processor and the memory that determines ordering of writes to the memory; and DMA engine circuitry between the controller and a plurality of peripheral devices to control writing of data from the plurality of peripheral devices into the memory; wherein a protocol as performed by the DMA engine circuitry in order to write data into the memory comprises: re-ordering a plurality of requests into a first order transmitting the plurality of requests in the first order to the controller; receiving from the controller a plurality of responses to the requests in a second order, wherein each response from the plurality of responses corresponds to one of the requests from the plurality of requests, the second order corresponding to a different order than the first order; and writing data to the memory in the second order, wherein data is written to the memory for each of the protocol requests in response to receipt of the request's corresponding protocol response.