Patent ID: 7985636

Claim:
A method for fabricating a low temperature poly-silicon (p-Si) thin film transistor (LTPS-TFT) substrate, the method comprising: providing a substrate and forming a p-Si layer over the substrate; forming a p-Si pattern, the p-Si pattern comprising a source electrode contact region and a drain electrode contact region of a first type TFT, and a source electrode contact region and a drain electrode contact region of a second type TFT; heavily doping the source electrode contact region and the drain electrode contact region of the first type TFT with a first dopant; forming a gate insulator on the p-Si pattern, and forming a gate electrode of the first type TFT and a gate electrode of the second type TFT on the gate insulator; heavily doping the source electrode contact regions and drain electrode contact regions of the first and second type TFTs with a second dopant; forming a passivation layer on the gate insulator and the gate electrodes of the first and second type TFTs; forming a plurality of contact holes corresponding to the p-Si pattern; and forming a source electrode connected to the source electrode contact region having been doped with the first dopant and the second dopant of the first type TFT, and a drain electrode connected to the drain electrode contact region having been doped with the first dopant and the second dopant of the first type TFT, and a source electrode connected to the source electrode contact region having been doped with the second dopant of the second type TFT, and a drain electrode connected to the drain electrode contact region having been doped with the second dopant of the second type TFT, via the contact holes; wherein the p-Si pattern further comprises a storage capacitor contact region, during heavy doping of the source electrode contact region and the drain electrode contact region of the first type TFT with a first dopant, the storage capacitor contact region is heavily doped with the first dopant synchronously; during formation of a gate electrode of the first type TFT and a gate electrode of the second type TFT on the gate insulator, a first electrode is formed on the gate insulator synchronously, during formation of a source electrode connected to the source electrode contact region of the first type TFT and a drain electrode connected to the drain electrode contact region of the first type TFT, and a source electrode connected to the source electrode contact region of the second type TFT and a drain electrode connected to the drain electrode contact region of the second type TFT via the contact holes, a second electrode is formed on the passivation layer synchronously; and the storage capacitor contact region, the gate insulator, the first electrode, the passivation layer, and the second electrode define a storage capacitor; wherein the first dopant and the second dopant are compensative, and the molar ratio of the first dopant to the second dopant is approximately 2 to 1.