Patent ID: 7190842

Claim:
Elementary cell of a linear filter for image processing, comprising: an input, intended to sequentially receive data relating to pixels of an image to be processed, a circulation output, intended to sequentially transmit the said data with a delay, a calculation output intended to sequentially transmit results obtained by a processing of the said data in said elementary cell, a main delay line having an input capable of being linked to the input of said elementary cell and an output capable of being linked to the circulation output and to the calculation output of said elementary cell, a coefficients memory, provided so as to contain at least one multiplier coefficient, and a multiplier connected to the coefficients memory, having an input and an output which are capable of being linked respectively to the output of the main delay line and to the calculation output of said elementary cell, the said multiplier being intended to perform multiplications on the said data received at the input of the said multiplier by at least one of the said multiplier coefficients of the coefficients memory and to transmit via the output of the said multiplier the result obtained, wherein the main delay line is capable of producing a maximum shift corresponding to at least two pixels of the image to be processed and in that said elementary cell also comprises: an auxiliary delay line having an input and an output which are capable of being linked respectively to the input of said elementary cell and to the circulation output of said elementary cell, an adder having a first and a second input which are capable of being linked respectively to the input of said elementary cell and to the output of the main delay line, and an output capable of being linked to the multiplier, delay line selection means having a first and a second state, the said means being intended to link the input of said elementary cell to the circulation output of said elementary cell by way of the main delay line in the first state and by way of the auxiliary delay line in the second state, and calculation selection means having at least two states, the said means being intended to link the input of said elementary cell and/or the output of the said main delay line to the corresponding inputs of the adder, in the said states respectively.