Patent ID: 6914468

Claim:
A controllable delay circuit ( 2 ) for delaying an electric input signal ( 4 ), which delay circuit ( 2 ) is designed for receiving the input signal ( 4 ) and at least one independent external control signal ( 6 ), wherein during operation the delay circuit ( 2 ) delays the input signal ( 4 ) by a delay for generating an output signal ( 8 ), which delay is a function of the at least one control signal ( 6 ), characterized in that the delay circuit ( 2 ) comprises a first module ( 10 ) for generating a base signal ( 11 ) and at least one support signal ( 12 ) on the basis of the input signal ( 4 ) and the at least one control signal ( 6 ), wherein during operation the phase and/or the amplitude of the at least one support signal ( 12 ) is controllable with respect to the phase and/or the amplitude of the base signal ( 11 ) by means of the at least one control signal ( 6 ), and wherein the delay circuit ( 2 ) furthermore comprises a second module ( 14 ) which is connected to the first module ( 10 ) and which comprises a signal conductor ( 16 ) and at least one support conductor ( 18 ), which signal conductor ( 16 ) and which at least one support conductor ( 18 ) extend mutually substantially parallel over at least a portion of the conductors in one another's vicinity, and wherein during operation the first module ( 10 ) supplies the base signal ( 11 ) to a first end of the signal conductor ( 16 ) for generating the output signal ( 8 ) at a second end of the signal conductor ( 16 ), and wherein during operation the first module ( 10 ) supplies at least the at least one support signal ( 12 ) to the at least one support conductor ( 18 ).