Patent ID: 7179713

Claim:
A method of fabricating a fin transistor, comprising: forming a silicon layer, a mask oxide layer and a nitride layer on a substrate; forming a fin by etching the nitride and mask oxide layers and silicon layer; forming a first insulating oxide layer; etching the first insulating oxide layer corresponding to a gate forming area using a gate mask to expose the fin; forming a gate oxide layer on a sidewall of the silicon layer exposed by the etch; filling the etched portion of the first insulating oxide layer with a first metal to form a gate electrode; removing the remaining first insulating oxide layer; forming a gate spacer; forming source/drain regions in the silicon layer aligned with the gate electrode; forming a second insulating oxide layer over the substrate; etching the second insulating oxide layer using a metal mask to form a trench exposing the gate electrode and to form trenches over the source/drain regions; forming contact holes on the source/drain regions; and filling the contact holes and the trenches with a second metal.