Patent ID: 7992042

Claim:
A debug support device for debugging a multiprocessor configured by a first, a second, and a third unit processors, comprising: a debug unit processor selecting section for detecting the second unit processor being in a HALT state by periodically checking a status register of the first, the second, and the third unit processors; a unit processor stop section activated by the second unit processor being in the HALT state detected by the debug unit processor selecting section when execution of a thread reaches a breakpoint which is set in the thread executed on the first unit processor and invokes exception handling, for issuing an instruction of stopping execution threads executed on the first and the third unit processors to stop the execution of the first and the third unit processors substantially simultaneously; and a debugging execution section for detecting information about the first, the second, and the third unit processors of which execution is stopped by the unit processor stop section, and for performing debug handling on the second unit processor being in the HALT state after the execution of the first and the third unit processors are stopped.