Patent ID: 7883959

Claim:
A semiconductor processing method, comprising: providing a semiconductor substrate having a memory array region, a peripheral region proximate the memory array region, and a pitch region between the memory array region and the peripheral region; the substrate having an uppermost surface, a horizontal direction being defined to extend along the uppermost surface of the substrate; providing a plurality of horizontally-elongated elements extending over one or both of the peripheral region and the pitch region, the horizontally-elongated elements containing electrically conductive lengths within electrically insulative liners; wherein the horizontally-elongated elements have uppermost surfaces; forming an electrically insulative material between the horizontally-elongated elements; removing at least some of the electrically insulative material from between the horizontally-elongated elements to leave trenches between the horizontally-elongated elements; forming an electrically conductive material over the uppermost surfaces of the horizontally-elongated conductive elements and within the trenches; planarizing the electrically conductive material to remove the electrically conductive material from over the uppermost surfaces of the horizontally-elongated conductive elements while leaving some of the electrically conductive material remaining between the horizontally-elongated conductive elements; wherein the electrically conductive material remaining between the horizontally-elongated elements has one or more electrically isolated segments, wherein the electrically conductive material remaining between the horizontally-elongated elements is at a first elevational level over the semiconductor substrate, wherein circuitry is over the semiconductor substrate at a second elevational level different from the first elevational level; forming interconnects between the circuitry and at least one of the one or more segments of the electrically conductive material; and utilizing the at least one segment as an electrical jumper to electrically couple regions of the circuitry with one another.