Patent ID: 8380964

Claim:
A processor, comprising; an issue queue to receive a set of dispatched instructions, the issue queue including: an instruction data store (IDS) having a plurality of queue positions that store the set of dispatched instructions; and an age matrix for managing a relative age of each dispatched instruction in the set of dispatched instructions stored in the IDS with respect to other dispatched instructions in the set of dispatched instructions stored in the IDS, wherein: the age matrix includes a plurality of memory cells configured in a number of rows and a number of columns, and during the dispatching of at least one dispatched instruction in the set of dispatched instructions, the issue queue: stores the at least one dispatched instruction in the IDS, updates the age matrix to reflect the age of the at least one instruction relative to other dispatched instructions in the IDS, modifies the age matrix row memory cells to a first state and column memory cells to a second state corresponding to the at least one dispatched instruction's queue position to reflect the relative age of the at least one dispatched instruction with respect to other dispatched instructions in the IDS, and for each row in the matrix, modifies a relative age storage element with an age value corresponding to a sum of the memory elements having the second state, wherein the age value indicates the age of each dispatched instruction in the set of dispatched instructions in the IDS.