Patent ID: 8299530

Claim:
A semiconductor structure comprising: a semiconductor substrate including at least one patterned gate stack located within a pFET device region of said semiconductor substrate, said at least one patterned gate stack comprises a high k gate dielectric located on an upper surface of said semiconductor substrate, and a metal gate electrode located atop the high k gate dielectric; a spacer located on said upper surface of said semiconductor substrate, said spacer having an inner edge in contact with a vertical sidewall of said at least one patterned gate stack and an opposing outer edge; extension regions located within said semiconductor substrate at a footprint of said at least one patterned gate stack; a channel region located within said semiconductor substrate beneath said at least one patterned gate stack; and a localized workfunction tuning area located within a portion of at least one of said extension regions that is positioned adjacent said channel region, but not extending beyond said outer edge of said spacer, and within at least one sidewall portion of the at least one gate stack including a sidewall portion of the high k gate dielectric and the metal gate electrode, wherein other portions of said at least one of said extension regions that extend beyond the outer edge of said spacer, and other portions of said at least one patterned gate stack adjacent said at least one sidewall portion of said patterned gate stack are void of said localized workfunction tuning area.