Patent ID: 6947343

Claim:
A semiconductor memory device including a plurality of memory blocks, each of the memory blocks comprising: a memory cell array block having a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells connected between the plurality of word lines and the plurality of bit line pairs; a write bit line pair; a sense bit line pair; a column selecting circuit having a plurality of first transmission transistors for transmitting data between a selected bit line pair among the plurality of the bit line pairs and the write bit line pair in response to a plurality of write control signals, and a plurality of second transmission transistors for transmitting data between the selected bit line pair and the sense bit line pair in response to a plurality of read control signals; and a pre-charge and write control circuit for pre-charging and equalizing the sense bit line pair in response to a pre-charge enable signal during a pre-charge operation, generating the plurality of the read control signals in response to a write enable signal and a plurality of column selecting signals during a read operation, and generating the plurality of write control signals in response to a block selecting signal, the write enable signal, the pre-charge enable signal, and the plurality of the column selecting signals during a write operation.