Patent ID: 7227860

Claim:
A packet switch comprising: (a) at least one input into which a packet is input; (b) a switch which receives said packet from said input and switches an output through which said packet is transmitted; and (c) a scheduler which controls said switch, said scheduler comprising: (c1) a shuffler which shuffles an order of precedence in a first request transmitted from said input to transfer said packet; (c2) a schedule algorithm which determines said output, based on said first request having said order of precedence having been shuffled by said shuffler, and produces a second request to transfer a packet which second request is associated with said first request having said order of precedence having been shuffled by said shuffler; (c3) a re-shuffler which turns an order of precedence of said second request to be identical with said order of precedence in said first request as found before having been shuffled by said shuffler, and returns the thus turned order of precedence back to said input, and wherein said packet is a non-segmented packet, wherein said input has N input port(s) wherein N is an integer equal to or greater than 1, and wherein said shuffler shuffles an order of precedence in N request(s) to transfer a packet, transmitted through said N input port(s), so as to define N! patterns of an order of precedence, wherein said shuffler includes a plurality of cyclic circuits in which a request to transfer a packet, transmitted through said N input ports, is initially set, and wherein a cyclic circuit or cyclic circuits other than a final stage cyclic circuit cycles both (a) said initially set request, and (b) a request to transfer a packet, set by the previous stage cyclic circuit, in synchronization with a carry signal transmitted from the next stage cyclic circuit, and transmits said requests to said next stage cyclic circuit, and a final stage cyclic circuit cycles both (a) said initially set request and (b) a request to transfer a packet, set by the previous stage cyclic circuit, in synchronization with a slot pulse generated in a predetermined cycle.