Patent ID: 7817468

Claim:
A semiconductor memory device comprising: a plurality of memory cell transistors which have a stacked gate including a charge accumulation layer and a control gate, and are configured to retain 2 n levels from “0” data to “2 n −1” data (n is a natural number more than 1) according to a threshold voltage, the threshold voltages of the memory cell transistors being increased in ascending order of the “0” data to the “2 n −1” data; word lines which are connected to the control gate of the memory cell transistors; and a control circuit which controls a data write operation to the memory cell transistors, the control circuit writing the data into the memory cell transistors connected commonly to one of the word lines, the control circuit writing the data into the memory cell transistors by a first write operation and a second write operation subsequent to the first write operation, the “2 n −1” data being written into one of the memory cell transistors in the first write operation, the data having the threshold voltage lower than that of the “2 n −1” data being written in the second write operation.