Patent ID: 7038506

Claim:
A digital logic system comprising: a reset input for receiving a reset signal; a clock input for receiving an externally generated main clock signal; an ancillary clock generator for generating an ancillary clock signal independent of the externally generated main clock signal and having short term frequency stability in relation to an expected duration of a system reset phase; at least one functional circuits; a clock selection multiplexer having a first input for receiving the externally generated main clock signal, a second input for receiving the ancillary clock signal, and an output for providing the externally generated main clock signal or the ancillary clock signal to said at least one functional circuit; and a resettable edge-triggered shift register having a first input for receiving the externally generated main clock signal, a second input for receiving the reset signal, and an output connected to said clock selection multiplexer for deselecting the ancillary clock signal and selecting the externally generated main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.