Patent ID: 7222271

Claim:
A method for repairing bit errors in memory chips having a multiplicity of memory cells, the method comprising: (a) detecting bit errors using an error identification algorithm; (b) determining the addresses of faulty memory cells; (c) in response to detecting a bit error, setting a data bit initiating a repair mode; (d) in the repair mode, interpreting a signal present on one of a plurality of data lines to the memory chips as repair command to perform a repair; (e) repairing the bit errors by activating redundant memory cells, with the repair being effected in an installed state of the memory chip; and (f) in a system having a plurality of memory chips, deactivating the data lines to the memory chips which are not faulty in the repair mode, wherein only the data line to the faulty memory chip, on which line an error has been indicated, is active.