Patent ID: 8159882

Claim:
A memory system, comprising: a nonvolatile semiconductor memory device including a memory cell array containing a plurality of memory cells connected to word lines extending in a selection row direction and bit lines extending in a selection column direction, each memory cell having a threshold adjusted to belong to any one of 2 x pieces of threshold distributions (x is an integer of 3 or more) to store x-bit data corresponding to said threshold distribution, said memory cells arranged in matrix, a word line control circuit connected to said word lines and operative to apply a write voltage, a write-verify voltage or a read voltage to a word line connected to a data write or read target memory cell, a sense amplifier circuit connected to said bit lines and operative to read data stored in said memory cell and hold said read data and data to be written in said memory cell, and a control circuit operative to generate said write voltage, said write-verify voltage and said read voltage and also generate control signals for control of various parts to control writing and reading data to/from said memory cell; and a controller operative to control reading and writing data from/to said nonvolatile semiconductor memory device, wherein a writing operation and a verifying operation are repeated at the time of writing to write x-bit data in said memory cell, said writing operation including converting input data provided based on a first bit assignment pattern into a second bit assignment pattern, and applying a write voltage to said word line to shift the threshold of said memory cell based on said second bit assignment pattern, said first bit assignment pattern created such that pieces of x-bit data assigned to adjacent threhold distributions have only a one-bit difference therebetween and an alignment of data on the same digit of 2 x pieces of x-bit data corresponding to an alignment of 2 x pieces of threshold distributions contains at least two transition points of “0” and “1”, said second bit assignment pattern having a suppressed shift of the threshold distribution at the time of writing smaller than said first bit assignment pattern, said verifying operation including applying a write-verify voltage to said word line to verify said threshold, wherein a read voltage corresponding to said transition points of “0” and “1” is applied at the time of reading to said word line on a page basis to determine x-bit data stored in said memory cell one-bit by one-bit based on said first assignment pattern, said page containing a set of data on the same digit bit in pieces of x-bit data stored in said memory cells connected to the word line.