Patent ID: 7057970

Claim:
A nonvolatile ferroelectric memory control device comprising: a page address buffer for latching a page address having a block page address region and a column page address region in response to a chip enable signal, and for decoding the latched page address; a row address latch unit for latching a row address in response to the chip enable signal, and for outputting the latched row address; an address transition detector for detecting transition of the latched row address, and for outputting an address transition detecting signal; a reset signal transition detector for detecting transition of a reset signal in response to the chip enable signal, and for outputting a reset transition detecting signal; a write enable signal transition detector for detecting transition of a write enable signal in response to the chip enable signal, and for outputting a write enable transition detecting signal; a synthesizer for outputting a transition synthesizing signal in response to the address transition detecting signal, the reset transition detecting signal and the write enable transition detecting signal; and a chip control signal generator for selectively generating a control signal to control a chip operation in response to the transition synthesizing signal.