Patent ID: 7420869

Claim:
A memory device, comprising: a first clock input configured to receive a first clock signal; a second clock input configured to receive a second clock signal; a data input configured to receive a serial data word; a state input configured to receive a state signal; a register device comprising a data input and a clock signal input, and configured to accept a data word on its data input based on a clock signal on the clock signal input thereof; a multiplexer device comprising a control input, a first and a second data input, and a data output which is coupled to the data input of the register device, wherein the multiplexer device is configured to couple one of its data inputs to its data output based on a signal on the control input thereof; a buffer store comprising a first and a second data output coupled to a respective data input of the multiplexer device, wherein the buffer store is configured to accept the serial data word on the data input based on signals on the first clock input and on the state input, and configured to output a parallel data word to one of the two data outputs; a synchronization circuit comprising a control output coupled to the control input of the multiplexer device, a clock signal output coupled to the clock signal input of the register device, and inputs coupled to the second clock input and to the state input, respectively, wherein the synchronization circuit is configured to generate and output the clock signal to the clock signal output thereof, wherein the clock signal is derived from a time profile of the signal on the state input and the signal on the second clock input.