Patent ID: 7348277

Claim:
A method of fabricating a semiconductor device comprising: forming a pad layer, a pad interlayer insulating layer, an etch stop layer, a planarized interlayer insulating layer, and a sacrificial layer sequentially on a semiconductor substrate; forming at least one trench in the sacrificial layer and the planarized interlayer insulating layer, and forming at least one via contact hole in the etch stop layer, the pad interlayer insulating layer, and the pad layer, the via contact hole being formed under the trench; forming a diffusion barrier layer and a conductive layer sequentially on the sacrificial layer to fill the trench and the via contact hole; and performing a first chemical mechanical polishing (CMP) process at least one time to expose the conductive layer, the diffusion barrier layer, and to remove a portion of the sacrificial layer to expose a remaining portion of the sacrificial layer; and performing a second CMP process until the remaining portion of the sacrificial layer is removed and the planarized interlayer insulating layer is exposed and at least partially removed.