Patent ID: 7903496

Claim:
A semiconductor memory device having four banks, comprising: only one address input unit configured to input an address signal from an external device, and to transfer the address signal as a transferred address signal; an internal column address generating unit, connected to the address input unit, configured to receive the transferred address signal, and generate the transferred address signal as an internal column address; an internal row address generating unit, connected to the address input unit, configured to receive the transferred address signal and a row address control signal, logically combine the transferred address signal and the row address control signal after the transferred address signal is received by both the internal column address generating unit and the internal row address generating unit, and generate the combined signal as an internal row address; and an internal address control unit, connected to the internal row address generating unit, configured to generate the row address control signal for controlling the internal row address generating unit to be inactivated when all four bank active signals for respectively activating the four banks are activated.