Patent ID: 8237187

Claim:
A package structure for chip, comprising: a semiconductor carrier substrate having an upper surface and an opposite lower surface; a chip overlying the semiconductor carrier substrate and having a first surface and an opposite second surface facing the upper surface, wherein the chip comprises at least a first electrode and a second electrode; a first conducting structure overlying the semiconductor carrier substrate and electrically connecting the first electrode; a second conducting structure overlying the semiconductor carrier substrate and electrically connecting the second electrode; a first through-hole comprising a stacked hole in the semiconductor carrier substrate and penetrating the upper surface at an upper opening of the semiconductor carrier substrate and the lower surface at a lower opening of the semiconductor carrier substrate and disposed next to the chip, wherein the stacked hole comprises a first lower hole and a first upper hole stacked thereon; a first conducting layer overlying a sidewall of the first through-hole and electrically connecting the first conducting structure, wherein there remains an upper space within the first through-hole which is not filled to the upper opening by any electrically conductive material and a lower space within the first through-hole which is not filled to the lower opening by any electrically conductive material; a first middle conducting layer located at an interface between the first upper hole and the first lower hole and electrically connected to the first conducting layer overlying the sidewall of the first through-hole, wherein the first middle conducting layer completely separates the first upper hole and the first lower hole; and a third conducting structure comprising a second through-hole and overlying the semiconductor carrier substrate and electrically connecting the second conducting structure.