Patent ID: 8914615

Claim:
Apparatus for processing data comprising: processing circuitry configured to perform processing operations; an architectural register file having a plurality of architectural registers for storing operand values; first decoder circuitry configured to decode program instructions of a first instruction set to generate control signals for controlling said processing circuitry to perform processing operations; and second decoder circuitry configured to decode program instructions of a second instruction set to generate control signals for controlling said processing circuitry to perform processing operations; wherein program instructions of said first instruction set include first logical register specifiers specifying first logical registers holding operand values, said first logical registers corresponding to architectural registers within said architectural register file and having a plurality of different sizes corresponding to different numbers of words of data up to a maximum number of words of data; program instructions of said second instruction set include second logical register specifiers specifying second logical registers holding operand values, said second logical registers corresponding to architectural registers within said architectural register file and having a plurality of different sizes corresponding to different numbers of words of data up to said maximum number of words of data; said first decoder circuitry is configured to map said first logical specifiers using a first mapping to a common address format; said second decoder circuitry is configured to map said second logical specifiers using a second mapping to said common address format; and said second mapping is divergent from said first mapping wherein at least some values used as both a first logical register specifier and a second logical register specifier map to different architectural registers.