Patent ID: 7867884

Claim:
A wafer fabrication method, comprising: a first step of forming a plurality of first channel regions with a first conductivity type in a first region on a surface of a wafer by making a plurality of exposure shots and performing development on a resist formed in the first region to form a resist pattern and implanting an impurity ion with the first conductivity type into the wafer using the resist pattern in the first region as a mask; a second step of forming a plurality of second channel regions with the first conductivity type having an impurity concentration different from an impurity concentration of the first channel regions in a second region different from the first region on the surface of the wafer by making a plurality of exposure shots and performing development on a resist formed in the second region to form a resist pattern and implanting an impurity ion with the first conductivity type into the wafer using the resist pattern in the second region as a mask; a third step of forming a plurality of third channel regions with a second conductivity type different from the first conductivity type in a third region on the surface of the wafer by making a plurality of exposure shots and performing development on a resist formed in the third region to form a resist pattern and implanting an impurity ion with the second conductivity type into the wafer using the resist pattern in the third region as a mask; and a fourth step of forming a plurality of fourth channel regions with the second conductivity type having an impurity concentration different from an impurity concentration of the third channel regions in a fourth region different from the third region on the surface of the wafer by making a plurality of exposure shots and performing development on a resist formed in the fourth region to form a resist pattern and implanting an impurity ion with the second conductivity type into the wafer using the resist pattern in the fourth region as a mask, wherein the first region and the second region are two regions divided by a first line segment on the wafer, and the third region and the fourth region are two regions divided by a second line segment intersecting with the first line segment on the wafer.