Patent ID: 8810491

Claim:
A liquid crystal display (LCD) panel, comprising: a plurality of pixels, {P(n,m)}, spatially arranged in the form of a matrix, n= 1 , 2 , . . ., N, and m= 1 , 2 , . . ., M, each pixel P(n,m) defined between a respective pair of scanning lines (G n , G n — CS ) and two neighboring data lines D m and D m+1 crossing the pair of scanning lines (G n , G n — CS ), and comprising a pixel electrode, a first transistor, T 1 , electrically coupled to the scanning lines G n , the data line D m and the pixel electrode, and a second transistor, T 2 , electrically coupled to the scanning lines G n — CS and the pixel electrode, wherein the pixel electrode comprises a main pixel electrode and a sub-pixel electrode, wherein in operation, a pair of scanning signals (g n , g n — CS ) is applied to the pair of scanning lines (G n, G n — CS ) to sequentially turn on the first and second transistors T 1 and T 2 , a data signal is applied to the data line D m to charge the pixel electrode, wherein the scanning signal g n — CS is delayed from the scanning signal g n by time T D , so that the pixel electrode of the pixel P(n,m) has a first voltage V 1 (n,m) at the time t when the first transistor T 1 is turned on and a second voltage V 2 (n,m) at the time (t+T D ) when the second transistor T 2 is turned on, respectively, wherein each pixel P(n,m) further comprises: a first liquid crystal (LC) capacitor, Clc 1 , and a first storage capacitor, Cst 1 , both electrically connected between the main pixel electrode and a common electrode in parallel; a second LC capacitor, C 1 c 2 , and a second storage capacitor, Cst 2 , both electrically connected between the sub-pixel electrode and the common electrode in parallel; a third transistor T 3 having a gate electrically connected to the scanning line G n , a source electrically connected to the data lines D m and a drain; and a first coupling capacitor Cx 1 electrically connected between the sub-pixel electrode and the drain of the third transistor T 3 , wherein the first transistor T 1 has a gate electrically connected to the scanning line G n , a source electrically connected to the data lines D m and a drain electrically connected to the main pixel electrode, and wherein the second transistor T 2 has a gate electrically connected to the scanning line G n — CS , a source electrically connected to the drain of the third transistor T 3 and a drain electrically connected to the sub-pixel electrode.