Patent ID: 8259507

Claim:
A nonvolatile memory device comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; a plurality of word lines and a plurality of bit lines associated with the memory cells; and a word line booster circuit coupled to the word lines for supplying a selected word line with a word line voltage during an operation of the memory device, wherein the word line booster circuit comprises: first and second boosting capacitors that are connected in parallel, a first precharge circuit for precharging the first boosting capacitor and the second boosting capacitor, a third boosting capacitor operatively coupled to the first and second boosting capacitors via a charge-sharing transistor, the third boosting capacitor being coupled to one end of a load resistor to generate an output signal at the other end of the load resistor to be used as the word line voltage when the charge sharing transistor is enabled, a second precharge circuit for precharging the third boosting capacitor, a voltage detector circuit adapted to generate a detecting signal when the word line voltage reaches a target voltage during a read mode operation of the nonvolatile memory device, and a clock control circuit adapted to enable the charge sharing transistor and to disable one of the first and second boosting capacitors upon receiving a control signal from an address transition detector and the detecting signal from the voltage detector.