Patent ID: 7446026

Claim:
A method for forming a semiconductor device comprising: providing a semiconductor substrate having a first doped region and a second doped region; providing a first gate dielectric over the first doped region and providing a second gate dielectric over the second doped region, both the first doped region and the second doped region being electrically isolated by an isolation region that also separates the first gate dielectric and the second gate dielectric; forming a first gate stack for an N-channel transistor over the first gate dielectric over the first doped region, the first gate stack having a metal portion over and in contact with the first gate dielectric, a first in situ doped semiconductor portion over and in contact with the metal portion, and a first blocking cap comprising a material for preventing counter doping and over the first in situ doped semiconductor portion; forming a second gate stack for a P-channel transistor over the second gate dielectric over the second doped region, the second gate stack having a second in situ doped semiconductor portion over and in contact with the second gate dielectric, and a second blocking cap over and in contact with the second in situ doped semiconductor portion and comprising the material for preventing counter doping; separately performing implants to form source/drain regions adjacent the first gate stack to form the N-channel transistor and to form source/drain regions adjacent the second gate stack as the P-channel transistor, wherein the first and second blocking caps each have a thickness sufficient to substantially block dopants from the implant from entering the first and second in situ doped semiconductor portions, respectively; forming first stressor source/drain regions adjacent the first gate stack and having an upper surface that is below a lower surface of the first gate dielectric; and forming second stressor source/drain regions adjacent the second gate stack and in direct contact with a portion of a sidewall of the second gate dielectric.