Patent ID: 7117296

Claim:
A method of programming a non-volatile semiconductor memory device having a memory cell array in which electrically erasable and programmable memory cells are arrayed comprising: applying a program voltage to a selected memory cell of said memory cell array to shift a data of the cell from a first logic state to a second logic state; reading a data programmed in said memory cell array and verifying that the programmed data of said selected memory cell shifted to said second logic state; reading a data programmed in said memory cell array and erratic program checking whether the threshold voltage of a memory cell to be held in said first logic state exceeds a third value set as an upper limit value of said first logic state; and reading the data programmed in said memory cell array and over-program checking whether the threshold voltage of said selected memory cell shifted to said second logic state exceeds a fourth value set as an upper limit of said second logic state.