Patent ID: 7154983

Claim:
A method of operating a first-in first-out (FIFO) circuit supplying data to an integrated circuit employing an internal clock from an integrated circuit employing an external clock not synchronized with the internal clock, comprising: providing a plurality of registers operable to be written in response to write pointer signals controlled by the external clock and to be read in response to read pointer signals controlled by the internal clock, each of the registers having an input coupled to a common write signal node to receive data input in response to the write pointer signals and having an output coupled to a common read signal node to provide data output in response to the read pointer signals; and when the read pointer signals and the write pointer signals simultaneously attempt to read and write the same FIFO register, recording the read pointer signals into state machine registers that are clocked by their corresponding write pointer signals to provide overflow detection signals and logically combining the overflow detection signals to generate an overflow condition signal for resetting the FIFO.