Patent ID: 7493441

Claim:
A write-caching mass storage controller, comprising: a plurality of volatile memory banks, each having separate power inputs; a battery, coupled to provide power to said plurality of volatile memory banks via said separate power inputs during a main power loss; switches, coupled to said battery and the main power, each having a control input, said switches configured to selectively provide power to said plurality of volatile memory banks from the main power or from said battery in response to said control input; a processor, coupled to said plurality of volatile memory banks, configured to control storage of critical data to a first subset of said plurality of volatile memory banks and to refrain from controlling storage of said critical data to a second subset of said plurality of volatile memory banks, wherein said first and second subset are mutually exclusive, wherein said critical data comprises data which must be retained during said main power loss to avoid loss of write-cached user data, wherein said processor is configured to execute programs; and control logic, coupled to said control input of said switches, configured to receive information from said processor specifying which of said plurality of volatile memory banks is included in each of said first and second subsets, and configured to control said switches to: provide main power to said plurality of volatile memory banks under normal conditions; and provide battery power to said first subset of volatile memory banks and disable said second subset of said plurality of volatile memory banks from receiving power from said battery in response to detecting said loss of main power.