Patent ID: 7194088

Claim:
A system of cryptography processor comprising: an exponentiator operable to perform modulo exponentiation comprising reducing the size of an intermediate result at least once during modulo exponentiation computations; a modulo processor, operable to perform modulo reduction, comprising an adder, wherein the modulo processor is coupled to receive operands from the exponentiator corresponding to the modulo exponentiation, is operable to add the operands using the adder to provide a sum, and is operable to return the sum to the exponentiator, wherein the modulo processor is operable to perform modulo reduction independent of the exponentiator to speed up cryptography processor; wherein said adder is a full adder; and the operands from the exponentiator comprise carry data and sum data corresponding to a partial product; and wherein said modulo processor is operable to calculate a Montgomery constant in hardware and provide the Montgomery constant to the exponentiator for converting an operand into Montgomery form in preparation for the modulo exponentiation.