Patent ID: 7519932

Claim:
A system for analyzing crosstalk occurring in a semiconductor integrated circuit, comprising: a calculator configured to calculate timing windows of first and second wires, which are routed in the semiconductor integrated circuit, under a first analysis condition and calculate timing windows of the first and second wires under a second analysis condition; a sequence determination module configured to determine whether a sequence of the timing windows of the first and second wires under the first analysis condition interchanges with a sequence of the timing windows of the first and second wires under the second analysis condition when there is no overlapping of the timing windows under any of the first and second analysis conditions; and an analysis module configured to analyze crosstalk occurring between the first and second wires when there is no overlapping of the timing windows under any of the first and second analysis conditions, the interchange of the sequence of the timing windows of the first and second wires occurs and when there is an overlapping of the timing windows of the first and second wires under at least one of the first and second analysis conditions, wherein the analysis module does not analyze the crosstalk when there is no overlapping of the timing windows under any of the first and second analysis conditions and the interchange of the sequence of the timing windows does not occur.