Patent ID: 6987421

Claim:
A common mode voltage generating circuit for supplying a common mode voltage (Vcm) to a first and a second output terminal (O 1 , O 2 ) forming differential outputs of an amplifier stage (AMP), the common mode voltage generating circuit comprises: a first transistor (T 1 ) and a second transistor (T 2 ) having interconnected first main electrodes, and both having a second main electrode coupled to a supply terminal (Vss), a third transistor (T 3 ) with a second main electrode coupled to a first main electrode of the first transistor (T 1 ), and a first main electrode coupled to the first output terminal (O 1 ) and to a control electrode of the first transistor (T 1 ), a fourth transistor (T 4 ) with a second main electrode coupled to a first main electrode of the second transistor (T 2 ), and a first main electrode coupled to the second output terminal (O 2 ) and to a control electrode of the second transistor (T 2 ), a fifth transistor (T 5 ) with a control electrode for receiving a first reference voltage (Vr; Vl), and a sixth transistor (T 6 ) having a second main electrode coupled to the first main electrode of the fifth transistor (T 5 ), and a first main electrode for receiving a current (2I) from a current source (CS 4 ), the first main electrode and the control electrode of the sixth transistor (T 6 ) being interconnected, the third, the fourth and the sixth transistors (T 3 , T 4 , T 6 ) having interconnected control electrodes and being biased to operate in their saturation region, the first, second and fifth transistors (T 1 , T 2 , T 5 ) being biased to operate in their linear region, wherein the common mode voltage generating circuit further comprises a seventh transistor (T 7 ) with a second main electrode coupled to the supply terminal (Vss), a first main electrode coupled to the first main electrode of the fifth transistor (T 5 ), and a control electrode for receiving a second reference voltage (Vh), the seventh transistor (T 7 ) being biased to operate in its linear region, and wherein the first main electrode is a collector and the second main electrode is an emitter for bipolar transistors, and the first main electrode and the second main electrode are a drain and a source, respectively, or the other way around, for field effect transistors.