Patent ID: 8154935

Claim:
A device comprising: an interface circuit operable to communicate with a system and with a plurality of physical memory circuits, and to present to the system an emulated memory circuit, the interface circuit including a first component of a first type and a second component of a second different type, wherein the first component is operable to: receive, from the system, a first signal, wherein the first signal is associated with a first operation to be performed by the emulated memory circuit, the first operation including at least one of a first mode register write operation or a first mode register read operation; and forward the first signal to the second component after a first delay, wherein the first delay is a function of the first operation associated with the first signal; and wherein the interface circuit is operable to: identify at least one physical memory circuit, of the plurality of physical memory circuits, that is not being accessed; and perform a power-saving operation on the identified at least one physical memory circuit that is not being accessed.