Patent ID: 8354338

Claim:
A fabrication method of a circuit board structure with an embedded semiconductor chip, comprising the steps of: providing a semiconductor wafer having an active surface, the active surface having a plurality of electrode pads; forming a passivation layer on the active surface of the semiconductor chip and surfaces of the electrode pads and the passivation layer formed with openings to expose the electrode pads, followed by forming a plurality of connection metal pads on the electrode pads; forming a protection layer on the connection metal pads and the passivation layer formed on the active surface of the semiconductor wafer and a surface of the connection metal pads, wherein the protection layer completely covers the surface of the connection metal pads; cutting the semiconductor wafer and the protection layer to cut the semiconductor wafer into a plurality of semiconductor dies having the protection layer disposed thereon; providing a carrier board having at least one cavity, and receiving in the cavity at least one semiconductor chip having the protection layer, wherein a gap is formed between the semiconductor chip and the cavity; forming a dielectric layer on the carrier board and the protection layer, wherein a part of the dielectric layer fills the gap between the semiconductor chip and the cavity; simultaneously forming through the dielectric layer and the protection layer vias corresponding in position to the connection metal pads of the semiconductor chip by laser so as to expose the connection metal pads; and forming on the dielectric layer a circuit layer, that has conductive portions disposed in the vias of the dielectric layer and the protection layer, such that the circuit layer is electrically connected to the connection metal pads of the semiconductor chip via the conductive portions.