Patent ID: 7009261

Claim:
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on said semiconductor substrate; a field insulating film formed selectively on a surface of said semiconductor layer; an element isolating region of the first conductivity type extending from the surface of said semiconductor layer to said semiconductor substrate, and isolating each of elements; a gate electrode of a DMOS (Double-Diffused Metal Oxide Semiconductor) transistor formed on said semiconductor layer with a gate insulating film therebetween; a well region of the first conductivity type formed at the surface of said semiconductor layer, and extending from a source side of said DMOS transistor to a position under said gate electrode; a first impurity diffusion layer of the first conductivity type formed at the surface of said semiconductor layer, and functioning as a base of a first bipolar transistor; a second impurity diffusion layer of the first conductivity type formed at the surface of said semiconductor layer, and functioning as a resistance; third and fourth impurity diffusion layers of the first conductivity type formed at the surface of said semiconductor layer, and functioning as an emitter and a collector of a second bipolar transistor; a fifth impurity diffusion layer of the first conductivity type formed at a surface of said well region, and functioning as a back gate region of said DMOS transistor; a sixth impurity diffusion layer formed at the surface of said semiconductor layer, functioning as a drain of said DMOS transistor, and having a lightly doped region containing impurities of the second conductivity type at a relatively low concentration and a first heavily doped region containing impurities of the second conductivity type at a relatively high concentration; seventh and eighth impurity diffusion layers of the second conductivity type formed at the surface of said semiconductor layer, and functioning as emitter- and collector-leading layers of said first bipolar transistor; a ninth impurity diffusion layer of the second conductivity type formed at the surface of said semiconductor layer, and functioning as a base-leading layer of the second bipolar transistor; and a tenth impurity diffusion layer formed at the surface of said well region, functioning as a source of said DMOS transistor, and formed of a second heavily doped region containing impurities of the second conductivity type at a concentration similar to the concentration of said first heavily doped region.