Patent ID: 7974408

Claim:
A method for scrambling an RSA-CRT algorithm calculation by an electronic circuit, wherein a result is obtained from two modular exponentiation calculations, each providing a partial result, and from a recombination step, the method comprising acts of: adding a digital quantity to at least one first partial result used in the RSA-CRT algorithm before said recombination step; and cancelling the effects of the digital quantity after the recombination step, wherein each partial result is modulo one of two relatively prime numbers, the product of which represents the modulo of the modular exponentiation, said digital quantity being such that the modular addition, modulo the number from which the second partial result is obtained, of this quantity to the first partial result, is not zero; said digital quantity is less than the difference between the second of the two relatively prime numbers and the first partial result; and the recombination step comprises calculating a value X m according to the following relation: X m =[( X ″−( X′+R ))*( q −1 mod p )]* q +( X′+R ), where X′ and X″ designate the first and second partial results, q and p designate respectively the first and second of the two relatively prime numbers, and R designates said digital quantity.