Patent ID: 7436699

Claim:
A nonvolatile semiconductor memory device comprising: a plurality of memory cells, arranged in rows and columns, each having a storing portion having a resistance value set according to storage data; a plurality of bit lines, arranged corresponding to the respective memory cell columns, each connected to the memory cells in a corresponding column; a plurality of source lines, arranged corresponding to the memory cell rows, each connected to the memory cells in a corresponding row; write circuitry for transmitting a voltage corresponding to write data to a bit line on a selected column in data writing; and source line drive circuitry for driving a source line on a selected row to first and second voltage levels in a predetermined sequence in said data writing, according to a current flowing between the bit line in said selected column and the source line in said selected row via a corresponding memory cell, the storing portion of the corresponding memory cell having the resistance value set, wherein said write circuitry writes multiple bits of data in parallel; said nonvolatile semiconductor memory device further comprises: a column select circuit for selecting in parallel a plurality of columns equal in number to a bit width of the data to be written; and said source line drive circuitry drives the source line common to the memory cells on the plurality of selected columns in said predetermined sequence.