Patent ID: 7525189

Claim:
A semiconductor device characterized by comprising: a wiring board comprising a plurality of connecting terminals arranged on one surface in a direction of thickness and a plurality of external connecting bumps arranged on the other surface in the direction of thickness; and at least one semiconductor chip connected to said connecting terminals, wherein said wiring board comprises: a first wiring portion comprising a plurality of wiring layers and said external connecting bumps; and a second wiring portion electrically connected to said first wiring portion and integrated with said first wiring portion in the direction of thickness, said connecting terminals are made of contact plugs formed in through holes extending through the second wiring portion in the direction of thickness, sizes of opposing surfaces of said first wiring portion and said second wiring portion are equal, a thermal expansion coefficient of said second wiring portion is smaller than a thermal expansion coefficient of said first wiring portion and equal to a thermal expansion coefficient of said semiconductor chip, said semiconductor chip is a silicon chip, said second wiring portion comprises a base made of silicon, and said contact plugs are formed in said base.