Patent ID: 7020730

Claim:
A method for operating a microprocessor configuration, which comprises: connecting a first unit through a bus to a second unit, the bus having: a state signal line for conveying a state signal specifying an operating state of the bus; and lines for conveying bus signals specifying at least one data value; connecting a bus control unit to the state signal line; assigning at least one address to the second unit, the second unit being activated by the at least one address; controlling access of the first unit to the second unit through the bus with the bus control unit; and when the bus control unit communicates through the state signal line that no access is being carried out by the first unit to the second unit, generating a data value under random control and applying the data value to the lines as the bus signals, the data value generated not corresponding to any valid second unit address and no memory address being accessed as a result of the random control.