Patent ID: 7000122

Claim:
A managing system for managing a plurality of VRMs associated with a plurality of microprocessors and connected in parallel together between first and second supply voltage references, said VRMs having output terminals connected together and arranged to communicate over a common bus receiving an output current signal from said plurality of VRMs, wherein said managing system comprises: an equivalent droop resistor; an error amplifier receiving input signals, said input signals including an output voltage signal from said plurality of VRMs, a reference voltage (Vref), and a droop voltage produced through the equivalent droop resistor, said error amplifier effecting a comparison of said input signals to generate a control voltage signal to said plurality of VRMs; first and second control resistors connected, in series with each other, to said common bus to receive said output current signal; a third summing node, being input a first local control voltage from said first control resistor as a positive addend and a second local control voltage from said second control resistor as a negative addend; and a controller connected to an output of said third summing node and said equivalent droop resistor for supplying an internal control current to said equivalent droop resistor.