Patent ID: 8258562

Claim:
A semiconductor device comprising: a memory cell which does not have a Tri-gate structure; and a select gate transistor provided for the memory cell; wherein a gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor, wherein the select gate transistor includes: a semiconductor region; the gate insulating film that covers an upper surface of the semiconductor region; the element isolation region formed to sandwich the semiconductor region in a lateral direction in a cross section in a direction perpendicular to a substrate, and having a projecting portion whose upper surface is set higher than an upper surface of the gate insulating film and that contacts a side surface of the semiconductor region and a portion whose upper surface is set lower than the upper surface of the gate insulating film and that does not contact the side surface of the semiconductor region; and a gate electrode layer formed to cover the element isolation regions and gate insulating film.