Patent ID: 7413958

Claim:
A method for fabricating an etched grooved GaN-based permeable-base transistor device, comprising: opening a window for helium implantation on a hydride vapor phase epitaxy (HVPE) grown n + GaN quasi-substrate layer, using optical lithography; implanting helium on the n+ GaN quasi-substrate layer over the window for helium implantation, so as to provide an insulating layer for contact pads of the device; opening a window for collector fingers using E-beam lithography; depositing an ohmic metallization layer over the window for the collector fingers; lifting-off ohmic metallization, thereby forming the collector fingers; opening a window for a self-aligned base recess using optical lithography; etching to recess a base layer to an n − GaN quasi-substrate layer grown on the n + GaN quasi-substrate layer, wherein the etching is performed with a ramp down in chuck bias voltage wherein said ramp down is from a high chuck bias voltage to a low chuck bias voltage; opening a window for a collector contact pad, using optical lithography; depositing a high quality silicon nitride layer over the window for a collector contact pad; and lifting-off or wet chemical etching the high quality silicon nitride layer, thereby forming a silicon nitride collector contact pad.