Patent ID: 6915396

Claim:
A method of providing ordered access to a memory, comprising the steps of: comparing an address of an incoming transaction with the address of each pending transaction to create an original match vector indicating sequencing requirements between said incoming transaction and said pending transactions, said original match vector including a bit corresponding to a result of each comparison; forming an image of said original match vector and concatenating said image of said original match vector with said original match vector to form an extended match vector; receiving a value which indicates the relative age of said pending transaction; generating a counter mask from said value; generating masked match bits with a logic operation on said extended match vector and said counter mask; identifying one of said masked match bits based on a predetermined criteria; setting remaining ones of said match bits to a first predetermined logic value to provide an applied mask; and logically combining a first segment of said applied mask with a second segment of said applied mask to identify at most one of said pending transactions required to be completed prior to allowing said incoming transaction to be processed.