Patent ID: 7916567

Claim:
An integrated circuit device including a memory array comprising: at least one sense amplifier; at least one complementary bitline pair, a first bitline of said pair extending distally from said at least one sense amplifier in a first direction and a second bitline of said pair extending distally from said at least one sense amplifier in a second opposite direction; a plurality of associated wordline pairs disposed orthogonally to said first and second bitlines, a first wordline of said wordline pairs intersecting said first bitline and a second wordline of said wordline pairs intersecting said second bitline; a memory cell coupled to each of said first and second wordlines of said wordline pairs at an intersection with each of said first and second bitlines respectively, wherein said first and second wordlines of said wordline pairs are coupled together, wherein said memory cells comprise 1T/1C memory cells and wherein predetermined partial logic level ones and zeroes are stored in said capacitors of said 1T/1C memory cells to increase the tRC speed of said device.