Patent ID: 8875002

Claim:
A device, comprising: a controller configured to provide a data word and check bits for the data word to decoding logic; the decoding logic configured to generate a decoding of the data word and check bits for the data word in conformance with an H-matrix having the following properties: (a) no all 0 columns; (b) all columns are distinct; (c) no linear dependency involving three or less columns; (d) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, where j=i+1 and m=k+1; and (e) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, where (j=i+1 and m−k=q) or (k=j+1 and m−i=q) or (m=k+1 and j−i=q) for all integer values of q such that q>1 and q<=d, where d>=2 and d<=n−1 where n−k is a number of the check bits.