Patent ID: 7237218

Claim:
A method for optimizing dynamic power characteristics of an integrated circuit (IC) chip, wherein the IC chip includes a plurality of layers and at least one of the layers is a power mesh layer, the method comprising: providing at least one dummy metal mesh layer in the plurality of layers, wherein a dummy metal grid is provided on each of the at least one dummy metal mesh layers, the dummy metal grid comprising a plurality of interconnected metal lines that provide no logical functionality; coupling the at least one dummy metal mesh layer to a ground (Vss) net on the at least one power mesh layer, wherein the coupling further comprises: providing at least one ground tap on each of the at least one dummy metal mesh layers, wherein the at least one ground tap is a short jog; and connecting the dummy metal grid to the at least one ground tap, wherein by connecting the at least one dummy metal mesh layer to the ground (Vss) net, the capacitance on the ground (Vss) net is increased.