Patent ID: 7981787

Claim:
A semiconductor device manufacturing method, comprising: providing a laminated member in which at least an AlGaAs electron donating layer or an AlGaAs Schottky layer, a GaAs gate-buried layer, an InAlGaAs etching stopper layer, and a GaAs contact layer are laminated on or above a substrate in this order; etching the GaAs contact layer to form a first through hole; etching the InAlGaAs etching stopper layer to form a second through hole having approximately the same size as the first through hole; etching the GaAs gate-buried layer to form a third through hole in the first and second through holes, the third through hole being smaller than the first through hole; and forming an electrode in the first and second through holes, wherein a ratio of In:Al of the InAlGaAs etching stopper layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs etching stopper layer is in a range of approximately 1.5:8.5 to approximately 5:5.