Patent ID: 6998297

Claim:
A method comprising the steps of: a. providing a semiconductor wafer comprising a plurality of integrated circuit chips, each chip having a surface and a plurality of bonding pads associated with the integrated circuit and a periphery defined by saw lines; b. providing a plurality of metallic lead frames interconnected by a plurality of metallic leads having ends and a middle to form a sheet of lead frames; a first group of the leads having a lowered portion at the ends and a raised portion at the middle; c. applying a securing agent to the lowered portion of the leads and attaching the sheet of lead frames to the wafer; each lead frame opposing an integrated circuit chip and the raised portion of the first group of leads overhanging the saw lines; d. wire-bonding the bonding pads in the chips to the lowered portion of the leads; e. applying a encapsulating material to form a encapsulating layer and to encapsulate the plurality of chips and the plurality of lead frames, the encapsulating layer having a surface substantially parallel to the chip surface and substantially level with the raised portion of the leads; and f. partitioning the chips by severing the leads and wafer along the saw lines.