Patent ID: 8094653

Claim:
A shared memory arbitrator (SMA) for coordinating data transfers in a plurality of software parameterizable control blocks and a shared memory for use in wireless communications, comprising: an address register containing memory addresses of the parameterizable control blocks and configured to allocate the memory addresses by sending a write grant in response to a request signal; a data bus for loading parameters and transferring data in the plurality of software parameterizable control blocks in a physical layer transport composite processing system; sequencing logic configured to send a plurality of channel requests for requesting parameters and data transference amongst the shared memory and the plurality of software parameterizable control blocks, wherein the sequencing logic is further configured to send a read grant to the address register to allocate the memory addresses; a plurality of grants from the SMA to allow the parameters and data transference amongst the plurality of software parameterizable control blocks; and a data strobe to increment and decrement the address register.