Patent ID: 8164097

Claim:
A thin film transistor array panel comprising: an insulating substrate; a thin film transistor including a gate electrode, a drain electrode, a source electrode and a semiconductor and formed on the insulating substrate; a first passivation layer on the drain and the source electrodes, and including a first contact hole and an upper surface; and a pixel electrode formed on the first portion of the first passivation layer and connected to the drain electrode through the first contact hole, wherein a first portion of the upper surface is under the pixel electrode, a second portion of the upper surface is lower than the first portion and overlaps the gate electrode, a third portion of the upper surface is inclined with respect to the first and second portions, and connects the first portion to the second portion, such that the first and second portions are spaced apart from each other in a direction parallel to the insulating substrate, and the pixel electrode does not overlap the third portion.