Patent ID: 7262646

Claim:
A power-on reset circuit comprising: a first p-channel MOS transistor having a gate, a drain, a source and a substrate, the gate and drain of said first p-channel MOS transistor being grounded, and the substrate of said first p-channel MOS transistor being connected to a power supply; a first resistor which is inserted and connected between said power supply and the source of said first p-channel MOS transistor; a first inverter having an input terminal and an output terminal, said input terminal of said first inverter being connected to the source of said first p-channel MOS transistor; a second p-channel MOS transistor having a gate, a drain, a source and a substrate, the gate of said second p-channel MOS transistor being connected to said power supply, the drain of said second p-channel MOS transistor being grounded, and the source and substrate of said second p-channel MOS transistor being connected to said input terminal of said first inverter; and a power-on reset signal output terminal for outputting a power-on reset signal, said power-on reset signal output terminal being connected to said output terminal of said first inverter.