Patent ID: 8058924

Claim:
A method of providing process, voltage, and temperature variation tolerance within a semiconductor device, the method comprising: establishing a variation tolerant voltage signal at a selected node within a first device; conducting a first variation tolerant current signal through the selected node; mirroring the first variation tolerant current signal to conduct a second variation tolerant current signal; generating a first bias voltage from the second variation tolerant current signal; programmably applying the first bias voltage to control a slew rate of a second device; generating a third variation tolerant current signal; mirroring the third variation tolerant current signal to generate a fourth variation tolerant current signal through a common mode voltage node, wherein a voltage generated across a termination impedance of outputs of a differential amplifier in a common mode is substantially equal to a common mode voltage generated at the common mode voltage node; and utilizing the common mode voltage at the common mode voltage node to detect changes in the output of the differential amplifier.