Patent ID: 7786813

Claim:
A data processing system comprising a central processing unit (CPU), operable to generate a clock signal, the CPU having an interleaved voltage-controlled oscillator (VCO) comprising: a ring circuit comprising a series connection of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises: a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistor, the field effect transistors responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; a DC offset generator configured to adjust the amplified voltage signal, thereby providing the compensating voltage input; a random access memory (RAM) configured to store operating commands; a read only memory (ROM) configured to store BIOS and recovery code; and an I/O adapter, and a bus system coupling the CPU to the ROM, the I/O adapter, and the RAM.