Patent ID: 7474126

Claim:
A method for implementing logic, the method comprising: providing a first differential input pair; providing a second differential input pair; providing a first emitter follower transistor: providing a second emitter follower transistor: wherein the collector of a first transistor of the first differential pair is electrically coupled to the collector of a first transistor of the second differential pair, and to an upper voltage via a first resistor, and to a base of the first emitter follower transistor; wherein the collector of a second transistor of the first differential pair is electrically coupled to the collector of a second transistor of the second differential pair, and to the upper voltage via a second resistor, and to a base of the second emitter follower transistor; and selecting a first resistive value associated with the first resistor to be different from a second resistive value associated with the second resistor, wherein the difference between the first resistive value and the second resistive value yields a particular type of logic gate having a differential output at an emitter of the first emitter follower transistor and an emitter of the second emitter follower transistor.