Patent ID: 8456925

Claim:
A non-volatile memory device, comprising: a plurality of input pads; a buffer configured to buffer data inputted through the plurality of the input pads in synchronization with a write enable signal; an even latch configured to store a first buffered data outputted from the buffer in response to an even write enable signal; an odd latch configured to store a second buffered data outputted from the buffer in response to an odd write enable signal; a transfer unit configured to transfer stored data in the even latch and the odd latch to a selected bank of a plane in response to a bank selection signal, wherein the transfer unit comprises: a first demultiplexer configured to output the stored data in the even latch and the odd latch as a first bank data or a second bank data in response to the bank selection signal; a second demultiplexer configured to output the first bank data to a first bank of a first plane and a first bank of a second plane; and a third demultiplexer configured to output the second bank data to a second bank of the first plane and a second bank of the second plane.