Patent ID: 7589370

Claim:
An integrated metal-insulator-semiconductor (MIS) shunt capacitor comprising: a bottom electrode; a capacitor dielectric overlying the bottom electrode; a plurality of capacitor top plates overlying the capacitor dielectric, each capacitor top plate having a principal dimension and a lesser dimension, wherein individual capacitor top plates of the plurality are arranged proximate and adjacent to one another in an array along respective principal dimensions thereof, and further wherein the bottom electrode is shared among the plurality of capacitor top plates; a plurality of conductive stripes, wherein at least one conductive stripe is positioned on opposite sides of each capacitor top plate along the principal dimension of a respective capacitor top plate; a grounded top metal layer overlying a portion of the plurality of capacitor top plates, wherein each of the plurality of conductive stripes is coupled between the bottom electrode and the grounded top metal layer; an inter-level dielectric, wherein the inter-level dielectric is configured to (i) isolate the plurality of capacitor top plates from the grounded top metal layer, and (ii) isolate the plurality of conductive stripes from adjacent ones of the plurality of capacitor top plates; and an external ground via disposed proximate to and adjacent at least one side edge of the plurality of capacitor top plates, wherein the grounded top metal layer is electrically coupled to the external ground via.