Patent ID: 7473590

Claim:
A method of fabricating a semiconductor device comprising: forming a lower gate electrode on a semiconductor substrate; forming a lower interlayer dielectric layer to cover the surface of the semiconductor substrate along with the lower gate electrode; forming a body pattern having a portion overlapping the lower gate electrode, on the lower interlayer dielectric layer; forming an upper gate electrode across the body pattern, and having a portion overlapping the lower gate electrode with an intervening insulating layer between the upper and the lower gate electrodes; forming a source/drain region in the body pattern so that the body pattern is provided between the upper gate electrode and the lower interlayer dielectric layer; forming an upper interlayer dielectric layer to cover the surface of the semiconductor substrate along with the upper gate electrode; forming at least one body contact hole penetrating the upper interlayer dielectric layer, the upper gate electrode, the body pattern, and the lower interlayer dielectric layer, thereby exposing the lower gate electrode; and forming a body contact plug filling the body contact hole, wherein the body contact plug is not in contact with the source/drain region.