Patent ID: 7358179

Claim:
A method of manufacturing a semiconductor device, comprising: (a) forming a transistor having a structure including a first source electrode, a gate electrode, a drain electrode, and a second source electrode, arranged in the order named in a first direction, on an upper surface of a semiconductor substrate; (b) forming a first side wall and a second side wall on said upper surface of said semiconductor substrate, said first side wall and said second side wall extending in the first direction, being located on opposite sides and spaced, along a second direction, that is perpendicular to the first direction and parallel to said upper surface of said semiconductor substrate, from each of said first source electrode, said gate electrode, said drain electrode, and said second source electrode, said first and second side walls having a height, perpendicular to said upper surface of said semiconductor substrate, that is higher than the height of said gate electrode with respect to said upper surface of said semiconductor substrate; (c) forming a sacrificial layer on said upper surface of said semiconductor substrate covering said transistor, said sacrificial layer having a height with respect to said upper surface of said semiconductor substrate substantially the same as the height of said first and second side walls; (d) partially removing said sacrificial layer to expose said first source electrode and said second source electrode; (e) forming an interconnect line extending in the first direction on an upper surface of said sacrificial layer, said interconnect line being in contact with said first side wall and said second side wall, said interconnect line being connected to said first source electrode and said second source electrode, said step (e) being performed after said step (d); and (f) removing said sacrificial layer, said step (f) being performed after said step (e).