Patent ID: 7951669

Claim:
A method of making a memory cell array on a semiconductor substrate having a surface area doped with a first conductivity type, comprising: forming a first set of strips of conductive material elongated in a first direction across a surface area of the substrate with a first layer of dielectric material therebetween wherein said first set of strips are separated in a second direction thereacross with spaces therebetween, the first and second directions being substantially perpendicular to each other, forming a second set of strips of conductive material elongated in the first direction and at least partially occupying the spaces between the first set of strips in the second direction, the second set of strips being separated from the first set of strips by a second layer of dielectric material and the second set of strips being spaced apart from the substrate surface by a third layer of dielectric material, and separating the first and second sets of strips of conductive material along their lengths, thereby forming a rectangular array of individual conductive elements, wherein separating the first and second sets of strips comprises: etching trenches into the substrate surface by etching through strips of the first set, strips of the second set, the first layer of dielectric, the second dielectric and the third layer of dielectric, and forming a fourth dielectric material to substantially occupy the trenches.