Patent ID: 7733714

Claim:
A memory circuit, comprising: a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node; a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch; and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch, the upward lingering change being a shift of the threshold voltage from an initial threshold in a first direction and the downward lingering change being a shift of the threshold voltage from the initial threshold in a second direction opposite the first direction.