Patent ID: 6930935

Claim:
A redundancy control circuit comprising: a redundancy decoder comprising a plurality of fuse circuits corresponding to a plurality of determination signals which are previously activated, wherein each of said plurality of fuse circuits contains a plurality of fuse sections, and each of said fuse sections contains a fuse; and a decoder killer circuit which generates a killer signal when at least one of said plurality of determination signals is active, said killer signal is outputted to an external unit in a first check mode, wherein one of said plurality of fuse circuits is selected based on a first control signal and first address bits of a first address in said first check mode, and said determination signals corresponding to the non-selected fuse circuits are inactivated, and a specific one of said plurality of fuse sections of said selected fuse circuit inactivates said determination signal corresponding to said selected fuse circuit based on whether said fuse of said specific fuse section is cut in said first check mode, and each of said plurality of fuse sections of said selected fuse circuit other than said specific fuse section does not inactivate said determination signal.