Patent ID: 6985999

Claim:
A microprocessor, coupled to a bus for transferring data from a memory to the microprocessor, the bus operating at a first clock frequency, and the microprocessor operating at a second clock frequency, wherein the second clock frequency is N times the first clock frequency, the microprocessor comprising: a cache memory, for generating requests to read data from the memory on the bus, said requests comprising a plurality of access types; control logic, coupled to said cache memory, for receiving and accumulating said requests from said cache memory for approximately N cycles of the second clock frequency, and prioritizing said accumulated requests according to said plurality of access types; and a bus interface unit, coupled to said control logic, for receiving from said control logic after said approximately N cycles of the second clock frequency a highest priority one of said prioritized requests, wherein said plurality of access types includes a blocking access type request, wherein said control logic prioritizes blocking access type requests as highest priority of said access types.