Patent ID: 7969213

Claim:
A delay locked loop (DLL) circuit comprising: a clock input buffer configured to generate a reference clock signal by buffering an external clock signal and to output the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal; a timing compensation unit configured to generate a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during a duty cycle correction operation in response to a timing control signal; a duty cycle control unit configured to generate the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal; and a delay line configured to generate a delay clock signal by delaying the compensation reference clock signal in response to a delay control signal; a delay modeling unit configured to generate a feedback clock signal by delaying the delay clock signal with a delay value acquired by modeling a delay amount of an output path of the delay clock signal; a phase detection unit configured to generate a phase detection signal by comparing a phase of the feedback clock signal with the phase of the compensation reference clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.