Patent ID: 8555229

Claim:
A computer-implemented method for optimizing an integrated circuit layout for implementation in an integrated circuit performed using at least one computing device, the method comprising: obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout; partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules, using the at least one computing device; identifying a boundary condition between two of the groups, and distributing a slack or a gap between the two of the groups in response to identifying the boundary condition; creating a plurality of integer linear programming problems associated with each of the plurality of hierarchical constraint groups; determining a solution for each of the plurality of integer linear programming problems according to specific rules associated with each of the plurality of integer linear programming problems; redistributing the slack or the gap based on the determined solution for each of the plurality of integer linear programming problems; and integrating each solution for each of the plurality of integer linear programming problems together to form a second integrated circuit layout, using the at least one computing device, wherein the integrating is performed only after the redistributing of the slack or the gap.