Patent ID: 7590882

Claim:
A method for providing bus recalibration, the method comprising: receiving input data at a transmit side, the transmit side including a memory controller or a memory module within a cascaded interconnect memory system; scrambling values of the input data at the transmit side resulting in scrambled data, the scrambling including mixing values of data bits in the input data with a known pattern designed to reduce the likelihood that the data values will not switch within a selected number of bits and provides transitions to determine an optimum phase for data sampling at a receive side; transmitting the scrambled data to the receive side via a memory bus, the receive side including an other memory controller or memory module within the memory system, and the receive side directly connected to the transmit side by a packetized multi-transfer interface via the memory bus; periodically synchronizing a sampling clock and a data phase of the scrambled data at the receive side for the data sampling on the memory bus; and de-scrambling the scrambled data at the receive side resulting in the input data.