Patent ID: 7082559

Claim:
A semiconductor integrated circuit device comprising: a test target circuit including a plurality of nodes and terminals; a control circuit configured to generate an internal reset signal, and an internal operation mode signal, in response to an external clock signal or an internal clock signal generated from the external clock signal, an external reset signal, and an external operation mode signal inputted therein; and an observation circuit configured to receive input data from observation points of the test target circuit through branches to the observation circuit, in order to observe a test that causes the test target circuit to perform a substantially normal functional operation, the observation points having been selected from the nodes and terminals corresponding to faults not detected by a fault simulation that causes the test target circuit to perform a substantially normal functional operation, the observation circuit comprising a plurality of flip-flops, wherein the observation circuit is controlled by the internal clock signal, the internal reset signal, and the internal operation mode signal, and is configured to reset the flip-flops in response to the internal reset signal, and to selectively perform, using the flip-flops, (a) a first operation of compressing input data from the observation points to generate a signature during substantially normal operation of the test target circuit, the input data being generated in the test target circuit in accordance with test patterns that cause the test target circuit to perform a substantially normal functional operation, and (b) a second operation of serially transferring data, to cause the flip-flops to be connected in series and to read the signature out of the observation circuit, in response to the internal operation mode signal.