Patent ID: 6928013

Claim:
A timing control method for operating a synchronous memory, wherein the synchronous memory has a local data bus, a signal amplification bus, and a global data bus, the timing control method comprising the steps of: providing a synchronous timing such that following operations are carried out in a (n+1) th clock cycle of the synchronous timing; reading and decoding the (a+1) th address; pre-charging the local data bus that stores the a th bath of local data into an initial value in a local data bus pre-charging period; amplifying and transferring the a th batch of global data from the signal amplification bus to the global data bus in a global data transmission period; transferring the (a+1) th batch of local data to the local data bus in a non-local data bus pre-charging period; pre-charging the signal amplification bus and the global data bus that stores the a th batch of global data into an initial value in a signal amplification bus pre-charging period after temporarily storing the a th batch of global data to a register; and transferring the (a+1) th batch of local data from the local data bus to the signal amplification bus.