Patent ID: 7443215

Claim:
A frequency synthesis circuit comprising: pulse density modulator for mapping an “X” bit value to a “Y” bit value, wherein Y<X; interpolator control circuit, coupled to said pulse density modulator, for generating a Y bit control word, updated at a first interval rate, to emulate an X bit value updated at a second interval rate, wherein said first interval rate is faster than said second interval rate; phase locked loop circuit for receiving a reference clock signal and a feedback clock signal and for generating an output clock signal by locking said reference clock signal and a feedback clock signal based on a low pass frequency characteristic of said phase lock loop; interpolator circuit, coupled to said phase locked loop in a feedback path, for receiving said Y bit control word and said output clock signal and for generating said feedback clock signal by introducing a time delay, that varies with time, in said output clock signal; and wherein, said pulse density modulator for dithering said first interval rate of said Y bit control word at a frequency higher than said low pass frequency characteristic of said phase lock loop.