Patent ID: 7433224

Claim:
A static random access memory (SRAM) device capable of storing a program that is accessible when said SRAM device is powered up, said SRAM device comprising a plurality of storage cells, each of said storage cells comprising: a data latch having a first input/output (I/O) line and a second I/O line, said data latch comprising: a first inverter having an input coupled to said first I/O line and an output coupled to said second I/O line; a second inverter having an input coupled to said second I/O line and an output coupled to said first I/O line; and a biasing circuit capable of forcing at least one of said first and second I/O lines to a known logic state when power is applied to said SRAM device, wherein said known logic state comprises a portion of said program, said biasing circuit comprising a grounding circuit selectively connected by a programmable connect to one of said first inverter output and said second inverter output, wherein said grounding circuit is temporarily enabled after power is applied to said SRAM device, thereby grounding one of said first inverter output and said second inverter output and forcing said second I/O line to said known logic state.