Patent ID: 7084456

Claim:
A semiconductor device comprising: a substrate of a first conductivity type; a gate structure in a plurality of trenches in the substrate, wherein in each of the trenches, the gate structure comprises a conductive gate surrounded by an insulating material that has a first thickness at a sidewall of the trench and a second thickness at a bottom of the trench, the second thickness being greater than the first thickness; a first region of a second conductivity type adjacent to at least one of the trenches, the first region extending to a first depth in the substrate and including a channel region adjacent to the trenches; a second region of the second conductivity type, wherein the second region is in electrical contact with the first region, and the second region extends to a second depth that is deeper than the first depth and shallower than the trenches; and a third region of the first conductivity type atop the first region, wherein a voltage on the conductive gate controls a current flow from the third region through the first region to an underlying portion of the substrate, wherein the substrate comprises a layer in which the trenches reside, the layer having a graded dopant profile such that a concentration of dopants of the first conductivity increases with depth in the layer.