Patent ID: 7098073

Claim:
A method of stacking semiconductor packages comprising: providing a first semiconductor package comprising a first surface having a first plurality of conductive bumps attached thereto for making electrical connection to the first semiconductor package, and comprising an opposite and nonplanar second surface comprising a mold cap and a plurality of adjoining solder lans; placing a second semiconductor package overlying the first semiconductor package, the second semiconductor package comprising a first surface and an opposite second surface, the second surface comprising a second plurality of conductive bumps positioned outside of a central portion of the second surface and in contact with the plurality of adjoining solder lans of the first semiconductor package; positioning an intervening element between and in direct contact with the first semiconductor package and the second semiconductor package, the intervening element being sufficiently tacky to adhere to each of the first semiconductor package and the second semiconductor package and providing rigidity to adjoining surfaces of the first semiconductor package and the second semiconductor package that are in contact with the intervening element; extending the intervening element laterally outside a perimeter of at least one of the first semiconductor package and the second semiconductor package and bending the intervening element a predetermined amount; making direct electrical contact between the first semiconductor package and the second semiconductor package via the second plurality of conductive bumps and the solder lans; and connecting an underlying substrate to the first semiconductor package, the underlying substrate having a plurality of contacts, each being in contact with at least one of the first plurality of conductive bumps of the first semiconductor package.