Patent ID: 6952118

Claim:
An integrated circuit die comprising a domino stage having an evaluation phase, a pre-charge phase, and an inactive state, the domino stage comprising: a first supply rail; a second supply rail; a node; a nMOS pull-down logic comprising a set of input ports, each input port having an input voltage; a first pull-down nMOSFET connected to the nMOS pull-down logic so that during an evaluation phase a conditional low impedance path is provided between the node and the second supply rail depending upon the set of input port voltages; a first pull-up pMOSFET connected to the node so that a low impedance path is provided between the node and the first supply rail when the domino stage is in a pre-charge phase; and a discharge logic to discharge the node when in an inactive state and to force the input port voltages HIGH when the domino stage is in an inactive state.