Patent ID: 8045355

Claim:
A semiconductor memory device, comprising: a plurality of cell arrays, each cell array including a plurality of word lines, a plurality of bit lines disposed to overlap the word lines, and a plurality of cells electrically connected between the word lines and bit lines, respectively, one portion of the cell arrays forming a memory cell array that has said cells as memory cells, and another portion of the cell arrays forming a reference cell array that has said cells as reference cells; a cell selection circuit operative to select from said memory cell array a memory cell whose data is to be read, and to select from said reference cell array a reference cell at a position corresponding to a position of the memory cell selected in said memory cell array; and a sense amplifier circuit operative to detect and compare a current or a voltage of said selected memory cell with a current or a voltage of said selected reference cell, and thereby read data of said memory cell, wherein said memory cell array and reference cell array have an identical structure.