Patent ID: 8261221

Claim:
A computer-implemented method for comparing circuit configurations, the method comprising: receiving, by a computer, a first circuit configuration and a second circuit configuration; the first circuit configuration comprising a first set of timing nodes, first edges connecting the first set of timing nodes, and first timing constraints applicable to said first circuit configuration; the second circuit configuration comprising a second set of timing nodes, second edges connecting the second set of timing nodes, and second timing constraints applicable to said second circuit configuration; wherein timing nodes from the first circuit configuration are mapped to timing nodes from the second circuit configuration; identifying, by the computer, a first source set of at least one timing node in the first circuit configuration and a first sink set of at least one timing node in the first circuit configuration; identifying, by the computer, a second source set of at least one timing node in the second circuit configuration and a second sink set of at least one timing node in the second circuit configuration, the second source set corresponding to the first source set and the second sink set corresponding to the first sink set, the correspondence based on the mapping of timing nodes between the first circuit configuration and the second circuit configuration; determining, by the computer, a first set of timing constraints, comprising aggregating first timing constraints encountered in a traversal of timing paths from the first source set to the first sink set; determining, by the computer, a second set of timing constraints, comprising aggregating second timing constraints encountered in a traversal of timing paths from the second source set to the second sink set; determining, by the computer, whether the first set of timing constraints is equivalent to the second set of timing constraints; and responsive to determining that the first and second sets of timing constraints are not equivalent, indicating, by the computer, a mismatch between the first circuit configuration and the second circuit configuration.