Patent ID: 7750690

Claim:
An output stage for an electronic circuit between a supply terminal receiving a first reference voltage and a reference terminal being maintained at a second reference voltage, the output stage comprising: at least one input terminal configured to receive an input signal; an output terminal to be coupled to an external load; a pre-buffer coupled to said at least one input terminal and comprising an enable terminal configured to receive a general enable signal, at least one first output terminal configured to supply a first control signal, a first inverter, and at least one second inverter coupled in series with said first inverter between said at least one input terminal and said at least one first output terminal; said at least one second inverter comprising a first transistor, and a second transistor, said first transistor being coupled in series to said second transistor and being between the supply terminal and the reference terminal; an output buffer comprising at least one first transistor between the supply terminal and said output terminal, and a control terminal coupled to said at least one first output terminal of said pre-buffer and configured to receive the first control signal; at least one first tracking circuit between the supply terminal and said at least one first output terminal of said pre-buffer, said at least one first tracking circuit comprising a first intermediate node, a switch configured to be activated by a first activation signal during at least one transient of said at least one first transistor, and a first capacitor between the supply terminal and said first intermediate node, said first intermediate node to be coupled to said at least one first output terminal of said pre-buffer by way of said switch; and a first enable circuit between said second transistor and the reference terminal and configured to bring said at least one first output terminal of said pre-buffer to a tri-state condition.