Patent ID: 7290254

Claim:
A method for optimizing profiling and compilation of a target program using a compiler coupled to a processor unit, the method comprising: (a) transferring uncompiled instructions of the target program from a flash memory to an instruction cache; (b) translating the transferred uncompiled instructions from a set of instructions to a pre-compiled set of instructions using a translating software while simultaneously using a profiling software to profile the set of instructions to determine a plurality of profile values; (c) transferring the previously determined plurality of profiles values from step (b) to at least one hardware profile counter and storing the previously determined plurality of profile values in the at least one hardware profile counter, wherein the processor unit is coupled to the at least one hardware profile counter and the at least one hardware profile counter is coupled to a hardware switch; (d) using a compiler support software to perform a determination that the pre-compiled set of instructions resulting from step (b) are ready for compilation by the compiler based on the compiler support software reading of one or more of the previously stored plurality of profile values; (e) disabling of further translating and profiling of the set of instructions as performed in (b) based on comparing one or more of the profile values transferred in (c) to one or more predetermined values; the disabling further including disabling the at least one hardware profile counter using the compiler support software to act upon the hardware switch after the pre-compiled set of instructions are determined ready for compilation; and (f) to accomplish optimization of profiling and compiling of the target program, repeating steps (a), (b), and (c) for the remaining set of instructions until steps (b) and (c) are disabled based on steps (d) and (e).