Patent ID: 7359248

Claim:
A method for programming a NAND flash memory device having zero state memory cells, first state memory cells, second state memory cells and third state memory cells, each memory cell being associated with a first latch circuit and a second latch circuit, the method comprising the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state; (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells; (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells; and verifying the second state memory cells between steps (b) and (c) by applying a first verify signal to the first latch circuit and applying a second program voltage to a selected word line associated with the second state memory cells.