Patent ID: 8460970

Claim:
A method of making a packaged semiconductor device comprising: a. etching a pattern of interlocking features on a top surface of a monolithic substrate; b. plating a first pattern on the top surface of the monolithic substrate thereby forming a plurality of routing traces each having a first contact point and at least one additional contact point, wherein at least some of the first contact points or additional contact points coincide with at least one interlocking feature; c. plating a second pattern on a bottom surface of a monolithic substrate; d. mounting a semiconductor die on the top surface of the monolithic substrate with an adhesive; e. attaching wirebonds from the semiconductor die to the first contact points of the routing traces; f. encapsulating the die in a mold compound; g. Etching away the portions of the monolithic substrate not plated by the second pattern thereby forming standoffs disposed at least some of the additional contact points; and h. singulating the semiconductor device.