Patent ID: 8432747

Claim:
A method of testing a static random access memory (SRAM), the SRAM comprising a SRAM cell, a first bit line connected to a first node of the SRAM cell via a first transfer gate of the SRAM cell, a second bit line connected to a second node of the SRAM cell via a second transfer gate of the SRAM cell, a precharge circuit including a first transistor connected between a power supply terminal and the first bit line, and a second transistor connected between the power supply terminal and the second bit line, the method comprising: writing a data into the SRAM cell to store a first potential level at the first node and a second potential level greater than the first potential level at the second node; supplying the power supply voltage from the power supply terminal to the first and second bit lines by activating the first and second transistors and deactivating the first and second transfer gates; and supplying the power supply voltage to the first bit line by activating the first transistor and activating the first and second transfer gates.