Patent ID: 7184662

Claim:
A switching network comprising: a first memory comprising 2x rows and y columns; a second memory comprising 2x rows and y columns; an x-to-2x demultiplexer configured to receive a first array of signals that comprises x rows of signals and y columns of signals and to switch, during a first stage, the signals only within each column of said first array to form a second array of signals in one of the first and second memories; and a 2x-to-x multiplexer configured to switch, during a second stage, the signals in said second array within both rows and columns to generate a third array of signals; wherein x and y are both positive integers greater than 1; and wherein to accomplish the switching; the x-to-2x demultiplexer writes into the first memory while the 2x-to-x multiplexer reads from the second memory, and the x-to-2x demultiplexer writes into the second memory while the 2x-to-x multiplexer reads from the first memory.