Patent ID: 7483320

Claim:
A method of inputting/outputting data in a semiconductor memory device, comprising: buffering, in a normal mode, first data and second data that are read from a memory cell array to generate buffered first data and buffered second data and to output the buffered first data and the buffered second data to a first output node of the memory device and a second output node of the memory device, respectively; and buffering, in a test mode, one of the first data and the second data through a first transmission line and a second transmission line in response to at least one control signal to generate one of buffered first data and buffered second data and to output the one of buffered first data and buffered second data to the first output node of the memory device and the second output node of the memory device, wherein the at least one control signal is provided from an external device, and wherein the semiconductor memory device is a double-data rate DRAM (DDR DRAM) and the at least one control signal is applied through a Data Input Output Mask (DQM) pin from the external device.