Patent ID: 7846806

Claim:
A method of manufacturing a self aligned silicon germanium heterojunction bipolar transistor, the method comprising the steps of: forming a non-selective epitaxial growth (NSEG) collector; forming an NSEG base over the NSEG collector; forming an NSEG monocrystalline silicon emitter over the NSEG base; and performing a first etch process to remove non-central portions of the NSEG monocrystalline silicon emitter and non-central portions of the NSEG base; wherein the step of forming the NSEG base comprises the steps of: forming a first layer of the NSEG base over the NSEG collector, wherein the first layer of the NSEG base comprises a first layer of silicon; forming a second layer of the NSEG base over the first layer of the NSEG base, wherein the second layer of the NSEG base comprises a layer of silicon germanium; and forming a third layer of the NSEG base over the second lager of the NSEG base, wherein the third layer of the NSEG base comprises a second layer of silicon; and wherein performing the first etch process comprises removing the non-central portions of the NSEG monocrystalline silicon emitter and non-central portions of the third layer of the NSEG base down to the second layer of the NSEG base.