Patent ID: 7598630

Claim:
A computer comprising an off-die memory device; a processor die, comprising: a plurality of die connection elements, wherein a first subset of the plurality of die connection elements receive power; a processor circuit; and a power-gating circuit electrically connected between the first subset of die connection elements and the processor circuit, wherein a second subset that is at least a portion of the first subset of die connection elements are not over the power-gating circuit, and wherein the power-gating circuit controls the application of power to the processor circuit by switchably interconnecting the first subset of the die connection elements to the processor circuit; and a substrate having an ungated conductive area to electrically connect a power supply input to an input of the power-gating circuit via the first subset of the die connection elements; and a gated conductive area electrically connected to an output of the power-gating circuit via a third subset of die connection elements and to the functional circuit via a fourth subset of die connection elements that are above the functional circuit, wherein a fifth subset that is at least a portion of the third subset of die connection elements are not over the power-gating circuit.