Patent ID: 8243219

Claim:
A liquid crystal display comprising: (m+2) gate signal lines utilized for transmitting (m+2) gate signals; n data lines utilized for transmitting n data signals; and a pixel array comprising m*n pixels, an (i,j) th pixel of the m*n pixels comprising: a main pixel comprising: a first switch element having: a gate electrode electrically connected to an i th gate signal line; and a source electrode electrically connected to a j th data signal line; a main pixel storage capacitor having a first electrode electrically connected to a drain electrode of the first switch element; and a main pixel liquid crystal capacitor having a first electrode electrically connected to the drain electrode of the first switch element; a sub-pixel comprising: a second switch element having a source electrode electrically connected to the j th data signal line; a sub-pixel storage capacitor having a first electrode electrically connected to a drain electrode of the second switch element; and a sub-pixel liquid crystal capacitor having a first electrode electrically connected to the drain electrode of the second switch element; a resistor having: a first electrode electrically connected to a gate electrode of the second switch element; and a second electrode electrically connected to the i th gate signal line; and a third switch element having: a gate electrode electrically connected to an (i+1) th gate signal line; a source electrode electrically connected to an (i−1) th gate signal line; and a drain electrode electrically connected to a gate electrode of the second switch element; wherein m, n, i, and j are positive integers.