Patent ID: 8284888

Claim:
A clock and data recovery device, comprising: an oscillator configured to produce a first clock signal in response to a frequency control signal; clock circuitry configured to receive the first clock signal and produce an output clock signal based on a phase control signal; a phase detector configured to receive a data input signal and the output clock signal and produce a data output signal and a phase detection signal; a loop filter configured to produce the phase control signal by filtering the phase detection signal; a controller configured to control the frequency of the oscillator using the frequency control signal based on measurements of the first clock signal, the output clock signal, and the data input signal; wherein the clock circuitry comprises: a phase interpolator configured to receive the first clock signal and produce a second clock signal based on the phase control signal, where the second clock signal is interpolated from two phases of a plurality of phases of the first clock signal; a prescaler configured to receive the second clock signal and produce the output clock signal by dividing the second clock signal by a value of a prescaler control signal produced by the controller.