Patent ID: 7974053

Claim:
An ESD protection circuit for a differential I/O pair in an IC comprising a first I/O pin and a second I/O pin, the ESD protection circuit comprising: a discharge device having a first end, a second end, and a triggering end; a first diode coupled between the first I/O pin and the first end of the discharge device in a forward direction toward the discharge device; a second diode coupled between the second I/O pin and the second end of the discharge device in a forward direction toward the second I/O pin; an ESD detection circuit having a positive power end, a negative power end, and an output end; the positive power end being coupled to a positive power line of the IC, the negative power end being coupled to a negative power line of the IC, the output end being coupled to the triggering end of the discharge device; and a third diode coupled between the first end of the discharge device and the positive power line of the IC in a forward direction toward the positive power line; wherein via the output end, the ESD detection circuit turns the discharge device off during normal power operations and triggers the discharge device during an ESD event.