Patent ID: 7276753

Claim:
A dynamic random access memory (DRAM) cell, comprising: a deep trench capacitor disposed inside a deep trench in a substrate, wherein the deep trench capacitor further comprises: a lower electrode disposed in the substrate at a bottom portion of the deep trench; an upper electrode disposed within the deep trench; a capacitor dielectric layer disposed between the bottom portion of the deep trench and the upper electrode; and a collar oxide layer disposed on a sidewall of the deep trench exposed by the capacitor dielectric layer and disposed between the upper electrode and the substrate; and an active device disposed inside a trench in the substrate, wherein the active device is positioned next to the deep trench capacitor, wherein the active device further comprises: a semiconductor strip disposed inside the trench to expose a portion of the substrate at the bottom portion of the trench, wherein one end of the semiconductor strip is positioned next to the substrate while the other end of the semiconductor strip is positioned next to the upper electrode; a gate dielectric layer disposed on the semiconductor strip; a gate disposed on the gate dielectric layer, wherein the gate crosses over the semiconductor strip, and the semiconductor strip covered by the gate serves as a channel region; and a doped region disposed in a portion of the semiconductor strip adjacent to the substrate and in the substrate adjacent to the semiconductor strip.