Patent ID: 7605663

Claim:
A Phase Lock Loop (PLL), comprising: a phase frequency detector, used for receiving a feedback signal and a reference signal and outputting a pull-up signal and a pull-down signal after comparing the feedback signal to the reference signal; a device for stabilizing the output of the PLL, used for receiving the reference signal and for outputting a frequency control signal in response to the reference signal with a frequency lower than or equal to a default value, wherein the device for stabilizing the output of the PLL comprises: a third current source, comprising a first end, a second end, and a control end. wherein the first end of the third current source is coupled to a first level; a fourth current source, comprising a first end, a second end, and a control end, wherein the first end of the fourth current source is coupled to the second end of the third current source, and the second end of the fourth current source is coupled to a second level; a charge storing component, wherein an end thereof is coupled to the second end of the third current source, and the other end is coupled to the second level; an edge detector, comprising an input end and an output end, wherein the input end of the edge detector receives the reference signal, and the output end of the edge detector is coupled to the control end of the third current source and the control end of the fourth current source, wherein when the reference signal transits to a second status from a first status, the fourth current source is turned on; otherwise, the third current source is turned on; and a comparator, comprising an input end and an output end, wherein the input end of the comparator is coupled to the second end of the third current source, and the output end of the comparator outputs the frequency control signal; a charge pump, having an output end for outputting a voltage signal, used for receiving the pull-up signal and the pull-down signal and the frequency control signal and to output the voltage signal according to the pull-up signal, the pull-down signal and the frequency control signal, comprising: a pull-up circuit, receiving the pull-up signal and the frequency control signal, coupled to the output end of the charge pump and used for increasing the voltage signal; and a pull-down circuit, receiving the pull-down signal and the frequency control signal, coupled to the output end of the charge pump and used for decreasing the voltage signal, wherein the pull-up circuit and the pull-down circuit are turned off by the frequency control signal to stabilize the voltage signal when the frequency of the reference signal is lower than or equal to the default value; a voltage control oscillator VCO, receiving the voltage signal and used for outputting an oscillating signal according to the voltage signal; and a frequency divider, used for dividing frequency of the oscillating signal and then for outputting the frequency-divided oscillating signal as the feedback signal.