Patent ID: 7572713

Claim:
A method of fabricating a semiconductor device including an upper surface having a memory cell region and a peripheral circuit region, comprising: patterning a mask on the upper surface to form a first trench having a first opening width in the memory cell region and a second trench having a second opening width which is larger than the first opening width; and etching the upper surface in the memory cell and the peripheral circuit regions simultaneously, with the mask by an reactive ion etching (RIE) process using reactive plasma including an HBr gas, a Cl 2 gas, a fluorocarbon gas and an O 2 gas so that the first trench includes a first bottom portion having a first depth and the second trench includes a pair of bottom end portions having a second depth deeper than the first depth and a bottom middle portion formed between the bottom end portions, wherein the bottom middle portion includes a third depth that is shallower than the second depth, and the third depth of the bottom middle portion is the same as the first depth of the first trench.