Patent ID: 8214705

Claim:
An integrated circuit comprising: A. a semiconductor substrate; B. functional IP core circuits formed on the substrate, the IP core circuits forming a periphery on the substrate and having core functional input leads and core functional output leads that extend beyond that periphery; and C. test circuits formed on the substrate within the periphery of the functional IP core circuits, the test circuits including: i. a test data input lead extending beyond the periphery of the functional IP core circuits; ii. a test data output lead extending beyond the periphery of the functional IP core circuits; iii. a test clock lead extending beyond the periphery of the functional IP core circuits; iv. a test mode select lead extending beyond the periphery of the functional IP core circuits; v. a test access port coupled to the test data input lead, the test data output lead, the test clock lead, and the test mode select lead; vi. test data registers coupled to the test data input lead, and the test data output lead; vii. an instruction register coupled to the test data input lead and the test data output lead; viii. a first external register present lead separate from the test data input lead and the test data output lead, connected to the instruction register and extending beyond the periphery of the functional IP core circuits; and ix. a second external register present lead separate from the test data input lead and the test data output lead, connected to the instruction register and extending beyond the periphery of the functional IP core circuits.