Patent ID: 8476718

Claim:
A semiconductor device, comprising a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having trap levels so that a ratio of minority carriers to majority carries in a current flowing via the trap levels can be made higher, the trap levels capturing or releasing charges formed by inclusion of the at least one element, density of the at least one element in the metal oxide layer being in the range of 1 ×10 15 cm −3 to 2.96 ×10 20 cm −3 , the trap levels being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film, wherein when the MISFET is an n-MISFET, the majority carriers are electrons and the minority carriers are holes, and when the MISFET is a p-MISFET, the majority carriers are holes and the minority carriers are electrons.