Patent ID: 8352672

Claim:
A memory system comprising: a nonvolatile memory including a plurality of data blocks, each of which includes a plurality of pages ordered in a respective sequential order, the nonvolatile memory being configured to erase data by erasing one or more entire data blocks of the plurality of data blocks; and a controller configured to write data to the plurality of data blocks; wherein for each block of the plurality of data blocks, the controller is configured to sequentially write data to the data block by writing data to pages in the data block according to the respective sequential order; wherein for each block of the plurality of blocks, a respective last page is a page in the data block that has been written last in the respective sequential order, and wherein for each block of the plurality of blocks, a respective first page is the page directly after the respective last page in the respective sequential order; wherein the controller is configured to check whether the nonvolatile memory has been affected by power interruption; wherein if a first data block does not include a page that has been incorrectly written by power interruption, the controller is configured to resume sequentially writing data to the first data block at the respective first page; wherein if a first data block includes a page that has been incorrectly written by power interruption, the controller is configured to resume sequentially writing data to the first data block at a second page, the second page being a page that is at least two pages after the respective first page in the respective sequential order.