Patent ID: 7646060

Claim:
Field effect transistor comprising a source region ( 9 ), a drain region laterally spaced from said source region ( 9 ) and of highly doped n-type, a base layer ( 5 ) of highly doped p-type, an n-type channel layer ( 11 ) of lower doping concentration extending laterally and overlying both said source region ( 9 ) and base layer ( 5 ) and interconnecting the source region ( 9 ) and the drain region for conducting a current between these layers in the on-state of the transistor, said source region ( 9 ) having a portion overlapping said base layer ( 5 ), interposed between said base layer ( 5 ) and channel layer ( 11 ) and defining a vertical edge along said base layer ( 5 ), and a gate ( 16 ) formed upon the n-type channel layer ( 11 ) which is self-aligned both laterally and perpendicularly with respect to the underlying source region ( 9 ) and base layer ( 5 ), with said gate ( 16 ) not overlapping said source region ( 9 ) and entirely overlapping said base layer ( 5 ), and additionally comprising a dielectric layer ( 14 ) situated upon said channel layer ( 11 ) and above both said source ( 9 ) and drain regions and comprising an opening for receiving metal forming the gate ( 16 ) self-aligned both laterally and perpendicularly.