Patent ID: 8288260

Claim:
A process for fabricating a semiconductor device, the process comprising: growing an n-channel layer of gallium arsenide (GaAs) on a buffer layer; growing a barrier layer on said channel layer; epitaxially growing a first etch-stop layer on said barrier layer; growing a first contact layer comprising a wide band-gap material on said first etch-stop layer; epitaxially growing a second etch-stop layer on said first contact layer; growing a second contact layer on said second etch-stop layer, said second contact layer comprising a highly doped material; and selectively etching portions of said first contact layer, said second etch-stop layer, and said second contact layer to form a gate region, wherein (i) said first and said second contact layers have a first etch rate and said first and said second etch-stop layers have a second etch rate in a chosen first etch chemistry, (ii) said first and said second contact layers have a third etch rate and said first and said second etch-stop layers have a fourth etch rate in a chosen second etch chemistry, (iii) said first etch rate is larger than said second etch rate, and (iv) said fourth etch rate is larger than said third etch rate.