Patent ID: RE39518

Claim:
A method of fabricating an integrated circuit comprising: pattern, exposure, and develop a photoresist layer on a wafer in a photolithography process that forms a plurality of structures on the integrated circuit including a gate; measuring a DICD critical dimension of the gate following developing of the photoresist layer in a Develop Inspection Critical Dimensions (DICD) operation; etching the wafer including etching of the gate; measuring a FICD critical dimension of the gate following etching of the wafer in a Final Inspection Critical Dimensions (FICD) operation; feeding forward the DICD critical dimension to a process model; feeding back the FICD critical dimension to the process model; and controlling a photoresist deposit and etch process recipe parameter in the process model according to the DICD critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity.