Patent ID: 8129242

Claim:
A method of manufacturing a memory device, comprising: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming a first semiconductor layer including a plurality of separate parts, comprising: forming an unpatterned semiconductor layer on the dielectric layer; forming an insulating layer on the unpatterned semiconductor layer; and patterning the insulating layer and the unpatterned semiconductor layer to form the separate parts of the first semiconductor layer; forming a buried drains in the substrate; forming a buried drain oxide mesas between the separate parts of the first semiconductor layer, each buried drain oxide mesa positioned over one of the buried drains, and each buried drain oxide mesa having an upper surface extending above upper surfaces of the separate parts of the first semiconductor layer; removing the patterned insulating layer to expose the upper surfaces of the plurality of the separate parts of the first semiconductor layer; and forming a plurality of U-shaped semiconductor structures, each being right above and in electrical connection with one of the plurality of separate parts of the first semiconductor layer to form a floating gate, comprising: forming a second semiconductor layer covering the plurality of the separate parts of the first semiconductor layer, wherein the second semiconductor layer has a plurality of recesses therein, each recess in the plurality of recesses being right above one of the plurality of the separate parts of the first semiconductor layer, and the second semiconductor layer covers the upper surfaces of the buried drain oxide mesas; forming an oxide layer on top of the second semiconductor layer, wherein the oxide layer has a sufficient thickness such that each of the plurality of recesses is filled up; removing a plurality of portions of the oxide layer and a plurality of non-recess portions of the second semiconductor layer, comprising: removing the plurality of portions of the oxide layer to expose the plurality of the non-recess portions of the second semiconductor layer; and removing the plurality of the non-recess portions of the second semiconductor layer to expose the upper surfaces of the buried drain oxide mesas and form a second plurality of separate parts of the second semiconductor layer, and removing all remaining portions of the oxide layer to expose an interior surface of each of the plurality of the U-shaped semiconductor structures, wherein a portion of each of the buried drain oxide mesas is also removed to expose a portion of each of the separate parts of the first semiconductor layer.