Patent ID: 8006171

Claim:
An apparatus for random parity check and correction with BCH code, comprising: a Bose-Chaudhuri-Hocquenghem (BCH) parity check code encoder, for using BCH encoding to encode parity check code and outputting parity check code bits; a channel, connected to the BCH parity check code encoder, for computing a message of data writing to a flash memory and the parity check code bits from the BCH parity check code encoder into a receiving data, and outputting the receiving data; a BCH parity check code decoder, connected to the channel, for receiving the receiving data and the parity check code bits from the channel, using BCH decoding to compute parity check code minimum polynomial, eigen values, error address polynomial and error address, outputting the error address; and a static random access memory (SRAM), connected to the BCH parity check code decoder, and storing error data of the flash memory, for correcting the error data based on the error address from the BCH parity check code decoder.