Patent ID: 8008643

Claim:
A memory device comprising: a bottom electrode; a dielectric fill layer having a top surface; a top electrode, on the top surface of the dielectric fill layer; a sub-lithographic pillar of memory material disposed between the bottom electrode and the top electrode within the dielectric fill layer, the memory material being programmable to a plurality of resistive states by heating; a heater consisting of a heater material having a resistivity greater than that of the top electrode and greater than that of the memory material in its most highly resistive state disposed on the sub-lithographic pillar of memory material within the dielectric fill layer between the top electrode and the sub-lithographic pillar of memory material, the heater having a top surface in direct contact with the top electrode; and a programmable resistive change region in the sub-lithographic pillar of memory material selectively programmable by resistively heating the heater so as to convert the programmable resistive change region from a first resistive state to a second resistive state, the programmable resistive change region being confined to a part of the sub-lithographic pillar adjacent to the heater, wherein the sub-lithographic pillar of memory material has a diameter, and the heater has a diameter, wherein the diameter of the heater is the same as the diameter of the sub-lithographic pillar of memory material.