Patent ID: 8423851

Claim:
A measured device coupled to test equipment providing at least two test factors and receiving a test result, comprising: a combinatorial logic circuit comprising: a first storage module storing the test factors according to a first operation clock; a second storage module storing and outputting at least two output factors according to a second operation clock, wherein the frequency of the second operation clock is higher than the frequency of the first operation clock; wherein when the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module; and a main circuit generating the test result according to the output factors output by the second storage module, wherein the test equipment obtains information as to whether the main circuit is normal according to the test result, wherein the first storage module comprises at least two flip-flops, during a first period, a first flip-flop of the first storage module stores a first test factor among the test factors; and during a second period following the first period, the first test factor stored in the first flip-flop is output to a second flip-flop of the first storage module and the first flip-flop stores a second test factor among the test factors, wherein the second storage module comprises at least two flip-flops, and during a third period following the second period, the first test factor stored in the second flip-flop is served as a first output factor among the output factors and the first output factor is output and stored in a third flip-flop of the second storage module, and the second test factor stored in the first flip-flop is served as a second output factor among the output factors and the second output factor is output and stored in a fourth flip-flop of the second storage module.