Patent ID: 7692467

Claim:
An apparatus, comprising: a semiconductor die; a first power rail on the semiconductor die and having a first no-load bias voltage from a first voltage source; a ground rail on the semiconductor die; a first voltage divider on the semiconductor die electrically coupled between the first power rail and the ground rail and having a midpoint node; a first pair of capacitors on the semiconductor die, the first of which is electrically coupled between the first power rail and the midpoint node and the second of which is electrically coupled between the midpoint node and the ground rail to provide capacitive decoupling for power delivered to the first power rail; a second power rail on the semiconductor die having a second no-load bias voltage from a second voltage source less than the first no-load bias voltage; and a second pair of capacitors on the semiconductor die, the first of which is electrically coupled between the ground rail and the second power rail and the second of which is electrically coupled between the second power rail and the ground rail to provide capacitive decoupling for power delivered to the second power rail.