Patent ID: 7923760

Claim:
An electronic structure with a plurality of interconnects, comprising: a first dielectric layer; a first interconnect; a second interconnect, wherein said second interconnect is spaced apart from said first interconnect, and wherein said first and said second interconnects are recessed into said first dielectric layer; a first dielectric spacer, wherein said first dielectric spacer is adjacent to a sidewall of said first interconnect, wherein said first dielectric spacer is in between said first and said second interconnects, and wherein said first dielectric spacer tapers outward, away from said sidewall of said first interconnect, from the top of said first interconnect to the bottom of said first interconnect; a second dielectric spacer, wherein said second dielectric spacer is adjacent to a sidewall of said second interconnect, wherein said second dielectric spacer is in between said first and said second interconnects, wherein said second dielectric spacer tapers outward, away from said sidewall of said second interconnect, from the top of said second interconnect to the bottom of said second interconnect, and wherein said first and said second dielectric spacers are discontiguous from one another with a gap in between said first and said second dielectric spacers; and a second dielectric layer, wherein said second dielectric layer is above said first and said second interconnects, wherein said second dielectric layer is above said first and said second dielectric spacers, and wherein said second dielectric layer is above said gap in between said first and said dielectric spacers, wherein the dielectric constant of said first and said second dielectric spacers is greater than the dielectric constant of said first and said second dielectric layers, and wherein the dielectric constant of said first and said second dielectric layers is greater than the dielectric constant of said gap.