Patent ID: 7994010

Claim:
A process for fabricating a semiconductor device, the process comprising: forming a gate electrode on a principal surface of a semiconductor substrate; forming first sidewall spacers in contact with sidewalls of the gate electrode; forming a predefined doped portion in the semiconductor substrate using the first sidewall spacers as a doping mask; forming masking sidewall spacers on the predefined doped portion and adjacent to the first sidewall spacers; selectively etching away the predefined doped portion of the substrate to form a cavity beneath the masking sidewall spacers that extends across the width of a base of the masking sidewall spacers and leaving a channel region of the substrate beneath the first sidewall spacers; forming an epitaxial region in the cavity, such that a surface profile of the epitaxial region is defined by the masking sidewall spacers and includes a step region above the principal surface at a perimeter of the masking sidewall spacers and spaced away from the gate electrode by the first sidewall spacers and the masking sidewall spacers; removing the first sidewall spacers and the masking sidewall spacers and forming implant spacers adjacent to the gate electrode; implanting the channel region underlying the gate electrode using the implant spacers as a doping mask to form one or both of a halo region or an extension region in the channel region.