Patent ID: 8453033

Claim:
A semiconductor memory device comprising: a plurality of semiconductor memory chips having writable storage regions in which data requested to be written by an information processing apparatus is written, the data having one or more pieces of first data in a predetermined unit, and one or more pieces of the first data including second data; a determining unit configured to determine, by referring to use state information, a prescribed number or fewer of semiconductor memory chips to which the pieces of the first data are to be written, from the semiconductor memory chips except for semiconductor memory chips having no writable storage regions, the use state information indicating, for each of the storage regions in each of the semiconductor memory chips, whether the storage region is writable or not; a write controller configured to write the pieces of the first data and redundant information that is calculated from the second data and is used for correcting an error in the second data into the writable storage regions in the semiconductor memory chips determined by the determining unit; and a storage unit configured to store therein identification information and region specifying information so as to be associated with each other, the identification information associating the second data and the redundant information, and the region specifying information specifying the storage regions in the semiconductor memory chips to which the pieces of the first data included in the second data and the redundant information are to be written.