Patent ID: 7167386

Claim:
A ferroelectric memory comprising: a bit line; a word line arranged to intersect with said bit line; and a memory cell including: a switching element arranged between said bit line and said word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions, and a ferroelectric capacitor arranged between said bit line and said word line and serially connected to said switching element, pulse application means for applying a pulse having a prescribed pulse width causing polarization inversion when a high voltage is applied to said ferroelectric capacitor while causing substantially no polarization inversion when a low voltage is applied to said ferroelectric capacitor of said memory cell, and for applying a high voltage pulse having said prescribed pulse width to selected said memory cell while applying a low voltage pulse having said prescribed pulse width to non-selected said memory cell at least either in data writing or in data reading.