Patent ID: 8288238

Claim:
A method for self-alignedly fabricating a tunneling field-effect transistor based on a planar process, comprising steps of: 1) defining an active region on a substrate by shallow trench isolation, and then sequentially growing a gate dielectric, depositing polysilicon, and carrying out a gate implantation with respect to the polysilicon; 2) depositing a first hard dielectric on the polysilicon and then etching the first hard dielectric to define a channel region, and then depositing a second hard dielectric and then a chemical mechanical polishing process is carried out on the second hard dielectric by using the upper surface of the first hard dielectric as the stop layer, wherein the first hard dielectric and the second hard dielectric comprise different materials and are selectively etchable by different chemical agents; 3) applying photoresist on a mask comprising both the first and second hard dielectric, carrying out photolithography to define a through hole over a region where a drain region is to be formed, carrying out wet etching on the second hard dielectric over the region through the through hole to remove the second hard dielectric over the region, removing the photoresist, removing the polysilicon over the region by etching, and carrying out a n-type ion implantation process to form the drain region of the device; 4) depositing the second hard dielectric to cover the drain region, and carrying out a chemical mechanical polishing process on the second hard dielectric by using the upper surface of the first hard dielectric as the stop layer, thereby forming a hard mask for protecting the drain region; 5) applying a photoresist on a mask comprising both the first and second hard dielectrics, carrying out photolithography to define a through hole over a region where a source region is to be formed, carrying out a wet etching on the second hard dielectric over the region through the through hole to remove the second hard dielectric over the region, removing the photoresist, removing the polysilicon over the region by etching, and carrying out a p-type ion implantation process to form the source region of the device; 6) depositing the second hard dielectric to cover the source region, and carrying out a chemical mechanical polishing process on the second hard dielectric by using the upper surface of the first hard dielectric as the stop layer, thereby forming a hard mask to protect the source region; 7) carrying out an anneal process to activate the impurities, and carrying out subsequent procedures for manufacturing the transistor.