Patent ID: 6891410

Claim:
An apparatus for determining a processing speed of an integrated circuit, the apparatus comprising: a first flip flop having an input port operative to receive an input signal, an output port operative to provide a flip flop output signal and a timing port operative to receive an incoming clock signal; a delay circuit operably coupled to the output port of the first flip flop such that the delay circuit is operative to receive the flip flop output signal and generating a delay timing signal; at least one clock speed adjusting circuit operably coupled to the delay circuit; a multiplexer operably coupled to the at least one clock speed adjusting circuit and the delay circuit, wherein the multiplexer has a select delay input port operative to receive a select delay signal such that the multiplexer generates a multiplexer output signal corresponding to at least one of: an output signal generated by the at least one clock speed adjusting circuit and the delay timing signal; and a second flip flop having input port operative to receive the multiplexer output signal, an output port operative to provide a timing output signal and a timing port capable of receiving the incoming clock signal.