Patent ID: 8392476

Claim:
A semiconductor memory device comprising: a semiconductor memory chip having a plurality of storage areas; a first write control unit configured to receive a request for writing first data associated with a logical block address from an information processing device, and perform a first writing of writing the first data in an unwritten location in an erased storage area from which data has been erased among the storage areas of the semiconductor memory chip; a first storage unit configured to store therein association information representing association between a physical address indicating the location in which the first data is written and the logical block address associated with the first data; a second write control unit configured to receive a request for writing third data associated with a same logical block address as that associated with second data, which is already written, and write the third data in an unwritten location in an erased storage area among the storage areas of the semiconductor memory chip; a first updating unit configured to update the association information to association information indicating association between the logical block address and a physical address for the third data when the third data is written by the second write control unit; a third write control unit configured to perform garbage collection by performing a second writing of writing fourth data, which is not invalid and which is in the storage area of the semiconductor memory chip in which the second data was previously written, in another storage area that is erased; and a frequency adjusting unit configured to adjust, according to a ratio set in advance, a frequency of the first writing in response to a request from the information processing device and a frequency of the second writing for the garbage collection.