Patent ID: 7549033

Claim:
A method of operating a non-volatile memory device, comprising: receiving an F-bit word, wherein F is a positive integer, wherein the F-bit word comprises a set of command and address signals, wherein the set of command and address signals consists of an Active command signal, Bank Address signals BA 0 -BA 2 , and Row Address signals A 0 -A 11 , and wherein the receiving the F-bit word comprises: receiving a first portion of the F-bit word substantially simultaneous with receiving a first event, wherein the first portion of the F-bit word comprises G-bits, wherein G is less than F, wherein the first portion of the F-bit word comprises the Active command signal, the Bank Address signals BA 0 -BA 2 , and a first subset of Row Address signals, wherein the receiving the Active command signal includes using a set of Command Pins, and wherein the receiving the Bank Address signals and the first subset of Row Address signals includes using a set of Address Pins; and receiving a second portion of the F-bit word substantially simultaneous with receiving a second event, wherein the second portion of the F-bit word comprises H-bits, wherein H is F-G, wherein the second portion of the F-bit word comprises a second subset of Row Address signals, and wherein the receiving the second subset of Row Address signals includes using the set of Command Pins and the set of Address Pins; performing a memory command, in a non-volatile memory, in response to the received F-bit word; sending the first portion of the F-bit word substantially simultaneous with sending the first event by an external controller; and sending the second portion of the F-bit word substantially simultaneous with sending the second event by the external controller.