Patent ID: 8416795

Claim:
A scheduler for scheduling and queuing received unicast packets within an Ethernet switch, the Ethernet switch having two or more interfacing ports, each interfacing port being provided with an output buffer logically divided into different priority buffers, and having a processor coupled to a non-transitory memory device for storing computer program instructions, wherein when the processor executes the computer program instructions the scheduler is caused to: determine a destination address and a traffic priority of a received unicast packet; search for a stored association between the destination address and an interfacing port of the Ethernet switch; when a stored association is found, schedule and queue the received unicast packet in one of the priority buffers of the output buffer in an associated interfacing port according to the received unicast packet's traffic priority; and when no association is found, flood the received unicast packet in a flooding buffer in every interfacing outgoing port of the Ethernet switch, and schedule the flooded unicast packet for transmission through each of the interfacing outgoing ports according to the flooded unicast packet's traffic priority after packets for which an association was found are transmitted.