Patent ID: 7750715

Claim:
A method for generating a first clock signal in a first signal path in response to a first input signal and a second clock signal in a second signal path in response to a second input signal, each of the first and second input signals comprises a first signal state and a second signal state, each of the first and second clock signals comprises a first clock level and a second clock level said method comprising: performing a first electrical charge transfer from the first signal path to a charge storage component when the first input signal is in the first signal state and the second input signal is in the second signal state, causing the first clock signal to change from the first clock level to a first intermediate level; causing the first clock signal to operate in the second clock level while the first input level remains in the second signal state; when the first input signal is in the second signal state and the second input signal is in the first signal state: causing the second clock signal to change from the second clock level to a second intermediate level; causing the first clock signal to operate in the second clock level and the second clock signal to operate in the first clock level; performing a second electrical charge transfer from the second signal path to the charge storage component, causing the second clock signal to change from the first clock level to a third intermediate level; causing the second clock signal to operate in the second clock state while the second input signal remains in the first signal state; when the first input signal is in the second signal state and the second input signal is in the first signal state, causing the first clock signal to change from the second clock level to a fourth intermediate level; and then when the first input signal is in the first signal state and the second input signal is in the second signal state, causing the first clock signal to change form the fourth intermediate level to the first clock level.