Patent ID: 8139332

Claim:
A semiconductor integrated circuit device comprising: a plurality of input/output circuits arranged along by a chip end side of a chip on which the input/output circuits are formed; wherein each input/output circuit includes: a logic circuit; a level conversion circuit coupled to the logic circuit; a pre-buffer coupled to the level conversion circuit; an NMOS output buffer and a PMOS output buffer coupled to an I/O pad and arranged to be driven by the pre-buffer; a first electrostatic breakdown protective circuit coupled between the pre-buffer and the PMOS output buffer; a second electrostatic breakdown protective circuit coupled between the pre-buffer and the NMOS output buffer; a third electrostatic breakdown protective circuit coupled between the logic circuit and the level conversion circuit; the PMOS output buffer is placed nearer than the first electrostatic breakdown protective circuit to the I/O pad; and the NMOS output buffer is placed nearer than the second electrostatic breakdown protective circuit to the I/O pad.