Patent ID: 8884687

Claim:
A power gating circuit comprising: a first current switch connected between a power rail and a circuit block operated by an operating supply voltage, the first current switch providing a first current when the first current switch is turned on; and a second current switch connected between the power rail and the circuit block, the second current switch providing a second current larger than the first current when the second current switch is turned on; and a switching controller that turns on the first current switch when transitioned from a sleep mode to an active mode in response to an operating mode signal to change the operating supply voltage using the first current, generates a reference voltage based on the operating supply voltage that changes more slowly than the operating supply voltage, and turns on the second current switch based on the reference voltage to provide the second current to the circuit block, wherein each of the first and second current switches is connected between a high-voltage power line of the power rail and a virtual high-voltage power line that supplies the operating supply voltage to the circuit block, and the switching controller comprises: a delay buffer that buffers a voltage of a first node to supply the buffered voltage to the second current switch; and a voltage detection control buffer that generates the reference voltage maintained lower than the operating supply voltage supplied through the virtual high-voltage power line, and outputs the operating mode signal through the first node after delaying a falling transition of the operating mode signal until the reference voltage reaches a predetermined voltage level, and disables a pull-down path between the reference voltage and a low-voltage power line of the power rail in response to an output signal of the delay buffer.