Patent ID: 7554304

Claim:
Voltage regulator for providing an output voltage (Vout) to a load (Zload), comprising an output transistor (T 1 ), an operational amplifier (OA), a floating voltage source (FVS; C 1 ) and a first reference voltage source (VS); the output transistor (T 1 ) being connected via a drain terminal (D) to a voltage supply (Vsup), and via a source terminal (S) being connectable to a supply terminal (X 1 ) of the load (Zload); a first input (IN 1 ) of the operational amplifier (OA) being connected to a feedback line (FL) to receive an input voltage derived from said source terminal (S); the first reference voltage source (VS) being arranged for providing a reference voltage (Vref) to a second input (IN 2 ) of the operational amplifier (OA); an output (O 1 ) of the operational amplifier (OA) being connected to a first terminal (F 1 ) of the floating voltage source (FVS; C 1 ), the output of the operational amplifier being arranged for providing an output voltage to the first terminal, and the floating voltage source having a second terminal (F 2 ) connected to a gate terminal (G) of the output transistor (T 1 ); the floating voltage source (FVS) being arranged for providing a voltage level (Vg) at the gate terminal of the output transistor (T 1 ) higher than said output voltage of said operational amplifier (OA).