Patent ID: 7863110

Claim:
A method for fabricating a semiconductor device, comprising: forming a device isolation layer in a semiconductor substrate to define an active region therein; forming a low voltage well of a first conductivity type within the active region of the semiconductor substrate; forming a high voltage impurity region of a second conductivity type within the active region in an upper portion of the low voltage well; forming a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer; and forming a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, such that the floating impurity region is a first portion of an upper surface of the active region and is spaced apart from the high concentration impurity region, wherein a portion of the high voltage impurity region is between the floating impurity region and the high concentration impurity region and is a second portion of the upper surface of the active region.