Patent ID: 8021943

Claim:
A semiconductor fabrication method comprising: providing a structure which includes a semiconductor substrate comprising a top substrate surface and a plurality of subsurface layers comprising a silicon-oxide layer and silicon-on-insulator (SOI) layer, said plurality of subsurface layers including a top surface; patterning a protective material on said top surface; performing a material removal process to simultaneously form a contact trench and an isolation trench, said material removal process removing at least a portion of said top surface and a portion of said subsurface layers such that said contact trench and said isolation trench are formed on said top substrate surface of said semiconductor substrate; forming an insulator within said isolation trench; lining said contact trench with said insulator; boring a channel in said contact trench by removing a portion of said insulator to expose said top surface of said semiconductor substrate; and filling said contact trench with a conductive material such that said conductive material is deposited over said insulator and said conductive material is in contact with said semiconductor substrate via said channel, wherein said conductive material consists of only polysilicon.