Patent ID: 7642136

Claim:
A method for reducing stresses applied to one or more bonded interconnects of a substrate and a PCB (Printed Circuit Board), comprising the steps of: coupling a compound on a top surface of the substrate, wherein the compound has a property of expanding when a heat profile is applied thereto; coupling a cover on the PCB so that it overhangs at least a portion of the compound; applying a double-sided adhesive between the compound and a top surface of the substrate at respective perimeter portions, before coupling the cover, leaving voids (i) below the compound and above the top surface of the substrate interior to the perimeter portions and (ii) above the compound and below the cover; and applying the heat profile to at least the compound and the double-sided adhesive thereby causing the compound to expand such that the compound removes the voids (1) below the compound and above the top surface of the substrate and (2) above the compound and below the cover.