Patent ID: 7372338

Claim:
A self-adjusting clock generator for producing a stable frequency output, comprising: a voltage control oscillator for generating a frequency output; a frequency to voltage converter for converting the frequency output to a voltage output, the frequency to voltage converter including: a current supply circuit for supplying current; a current control transistor for controllably passing the current from the current supply circuit according to the frequency output; a first capacitor and a second capacitor; a first transistor coupled to the first capacitor in parallel; a second transistor coupled between the first capacitor and the second capacitor; a clock cycle divider circuit for dividing the frequency output into three intervals defined by interval one, interval two, and interval three; wherein the first capacitor is charged during the interval one; the second capacitor is charged by the first capacitor through the second transistor during the interval two; the first capacitor is completely discharged to ground through the first transistor while the current control transistor is off during the interval three, wherein the voltage output is compared with a reference voltage to produce a comparison voltage denoting drifted frequency of the frequency output, the comparison voltage is provided as feedback to a voltage input of the voltage control oscillator such that frequency of the frequency output generated by the voltage control oscillator is adjusted in accordance with the comparison voltage to converge into the stable frequency output.