Patent ID: 7509513

Claim:
A method of synchronizing local real-time clocks of a plurality of computer components via synchronization units of each of said plurality of computer components communicating together comprising: receiving a configuration signal from a local processor of a first computer component separate from a data transfer bus; generating on differential lines one or more outbound synchronization pulses with dominant and recessive states for transmission over a synchronization bus common to the synchronization units; receiving from said synchronization bus one or more inbound synchronization pulses; performing quadruplex majority voting by eliminating synchronization pairs originating from a same synchronization unit; synchronizing the local real-time clocks based upon any one of minor and major cycles; implementing a multiple operation state control of a synchronization unit, wherein a transition from an Out of sync operating state to an In sync operating state is triggered by a sending of a first code Start_miF or of a second code Start_MAF, and a transition from the In sync operating state to the Out of sync operating state is triggered by a fault vote on three codes comprising Init_sync, Start_miF, and Start_MAF; and resynchronizing a real-time clock synchronization signal for transmission to a second computer component based upon processing of said configuration signal and said one or more inbound synchronization signals.