Patent ID: 8644064

Claim:
A method of operating a semiconductor device, comprising: configuring the semiconductor device to include at least one string of serially connected memory cells connected between first and second impurity regions, wherein each of the memory cells has a gate, the serially connected memory cells comprise a target cell that is selected as a target cell in a selecting step, a first cell that is a nearest neighbor cell of the target cell on a first side of the target cell, and a second cell that is a nearest neighbor cell of the target cell on a second side, opposite the first side, of the target cell, and a source/drain region of at least one of the serially connected memory cells is different from at least one of the first and second impurity regions in at least one of a conductivity type and an impurity concentration; applying to the gate of the first cell a first voltage that is a minimum voltage among voltages applied to the gates of all of the serially connected memory cells other than the target cell; applying to the gate of the second cell a second voltage that is a maximum voltage among voltages applied to the gates of all of the serially connected memory cells; and applying to the gate of a third cell, which is a cell among the serially connected cells that is different from the target cell, the first cell, and the second cell, a third voltage during the cell selecting step, wherein the third voltage has a voltage level between the first and second voltages.