Patent ID: 6912619

Claim:
A memory apparatus comprising: a first storage region from which data can be read and into which data can be written, in accordance with instructions made by a user; a second storage region from which data can be read and into which data can be written, when a data-processing apparatus to which the memory apparatus is connected performs prescribed procedures; a third storage region being a read-only region in which data has been already written; and a conversion table which includes logic addresses assigned only to blocks in said first storage region and not to (i) defective blocks and (ii) non-defective blocks in said second storage region and/or said third storage region; wherein said third storage region stores a user-use prohibition table which contains address data of the second storage region and another address data of one or more defective locations in said memory apparatus; and wherein said user or said data-processing apparatus is prohibited from accessing said one-or more defective locations contained in said user-use prohibition table.