Patent ID: 8409950

Claim:
A method for integrating a silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a standard sub-90 nm complementary metal oxide semiconductor (CMOS) foundry process flow, comprising: performing standard CMOS foundry process flow, including: forming an alignment layer on a silicon substrate; forming twin-wells in the silicon substrate to form a plurality of devices on the silicon substrate; and isolating neighboring devices on the silicon substrate; patterning, on the silicon substrate, a memory window implant layer using a memory window implant photoresist and a memory window implant mask, forming a patterned SONOS memory cell region of an embedded SONOS NVM; patterning, on the silicon substrate, a stack removal photoresist layer defined by a stack removal photoresist mask, wherein the memory window implant mask is smaller than the stack removal photoresist mask; and depositing, on the silicon substrate, a high permittivity (high-k) gate oxide layer as a capping oxide layer.