Patent ID: 7888246

Claim:
A method of fabricating a semiconductor integrated circuit device, comprising: forming a first dielectric layer on a semiconductor substrate; patterning the first dielectric layer to form a first patterned dielectric layer; forming a non-single crystal seed layer on the first patterned dielectric layer; removing a portion of the seed layer to form a patterned seed layer; forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer; removing portions of the second dielectric layer to form a second patterned dielectric layer; irradiating the patterned seed layer to single-crystallize the patterned seed layer; removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer; and forming a gate electrode in contact with the single-crystallized seed layer.