Patent ID: 7564877

Claim:
A field programmable gate array (FPGA) for multiplexing data and enable signals input from a plurality of input ports and outputting the multiplexed signal to one output port, the FPGA comprising: a plurality of memories, which are connected to the input ports, that store the input data and enable signals, respectively, and output one-shot signals from one or more memories of said plurality of memories, respectively, at trailing edges of the enable signals; and a finite state machine (FSM) that sequentially reads the data signals stored in the memories in an input order of the one-shot signals input from the memories by outputting read enable signals to the memories according to the input order of the one-shot signals, wherein the memories output the stored data signals in an input order of the read enable signals input from the FSM, and wherein a corresponding pair of the data and enable signals is input to each of said plurality of memories at the same time.