Patent ID: 7681016

Claim:
A method of operating a microprocessor-based computer system, comprising: dividing a sequence of operations from a single execution thread and across multiple basic blocks into strands by assigning operations from different ones of said basic blocks to different ones of said strands; numbering all of said strands at compile time to provide an implicit logical time ordering; explicitly labelling said operations within each of said strands with strand numbering and executing them sequentially according to an original sequential order; executing certain operations from said strands out of order with respect to their said original sequential order; providing each of said strands with a predication status that determines whether certain operations from each of said strands should be completed; composing a plurality of said strands into an executable code region; making a predication status of each of said strands resettable at the start of the execution of the executable code region; giving certain of said strands a predication status indicating that certain operations in the executable code region should not be completed; making the predication status usable to support recovery from data speculative operations between said strands; repeating execution of the executable code region when a failed data speculation occurs; and setting the predication status of said strands upon a repeat execution such that any of said strands that have already been completely executed are not re-executed.