Patent ID: 7750467

Claim:
A chip scale package structure comprising: a chip having an active surface and an inactive surface opposing to the active surface, a plurality of conductive bumps being formed on the active surface, a metal pad being formed on an end of each of the conductive bumps, wherein the end of each of the conductive bumps completely covers a surface of the metal pad; an encapsulant encapsulating the chip and the conductive bumps, the metal pads formed on the ends of the conductive bumps being exposed outside from the encapsulant and being on the same level as a surface of the encapsulant; a plurality of first conductive traces formed on the encapsulant and electrically connected to the metal pads; a solder mask applied on the first conductive traces and having a plurality of openings, predetermined parts of the first conductive traces being exposed through the openings; and a plurality of conductive elements formed on the exposed predetermined parts of the first conductive traces.