Patent ID: 8169758

Claim:
An integrated circuit comprising n different voltage rails, with n being an integer number greater than two, thus defining n different power domains, further comprising an on-chip ESD protection circuit, wherein: said ESD protection circuit comprises at least one group of ESD clamp devices, each such group comprising n−1 ESD clamp devices, said n−1 ESD clamp devices being arranged in a ladder-configuration, said ladder-configuration being characterized in that there is one of said n−1 ESD clamp devices interposed between each of said n voltage rails and the respective voltage rail having a next lower voltage, thus defining an ESD current path between each one of said n voltage rails and the voltage rail having the next respective lower voltage, and wherein each of said ESD clamp devices is off under normal power operation of said integrated circuit, wherein at least one NMOS transistor, situated in a p-well, serves as a bottom most ESD clamp device of one group of the at least one group of ESD clamp devices, the bottom most ESD clamp device being connected to two adjacent voltage rails having two lowest voltages of said n voltage rails, and wherein PMOS transistors situated in an n-well serve as the other ESD clamp devices of the one group of the at least one group of ESD clamp devices, and wherein none of terminals of the ESD clamp devices is connected to a substrate of the integrated circuit.