Patent ID: 8063685

Claim:
A flip-flop circuit, comprising: a data input; a clock input for receiving a clock signal having a plurality of active edges and inactive edges; a data output; an input circuit for setting a first node and a second node to different initial logic states in response to an inactive edge of the clock signal, and selectively changing the logic state of either the first node or the second node in response to a pulse input signal to control the state of a third node, said selection depending on the logic state of the data input, wherein the input circuit includes, a first precharge circuit comprising a first transistor coupled between the first node and a first supply voltage for setting the initial logic state of the first node, a second precharge circuit comprising a second transistor coupled between the second node and a second supply voltage for setting the initial logic state of the second node to the logic state opposite the initial logic state of the first node, a first circuit path comprising a first pair of transistors coupled in series between the first node and the second supply voltage, and a second circuit path comprising a second pair of transistors coupled in series between the second node and the first supply voltage; a pulse generator circuit for enabling the pulse input signal in response to an active edge of the clock signal, and disabling the pulse input signal in response to detecting the change in the initial logic state of either the first node or the second node; and a latch for storing a data output signal for output at the data output, the data output signal depending on the logic state of the third node.