Patent ID: 7755406

Claim:
A duty cycle correction circuit with wide-frequency working range, the duty cycle correction circuit receiving a reference clock signal from a clock generator and correcting duty cycle of the received reference clock signal for outputting an output clock signal, the duty cycle correction circuit comprising: a modulation circuit, comprising: a pulse generator, comprising: a NAND gate, comprising: a first input end, coupled to the clock generator; a second input end; and an output end for outputting a periodic low-level pulse signal; and a first modulator, coupled between the clock generator and the second input end of the NAND gate, for modulating low-level status of the reference clock signal according to a reference voltage and accordingly outputting the modulated reference clock signal to the second input end of the NAND gate; and a modulation device, comprising at least one second modulator coupled to the output end of the NAND gate for modulating low-level status of the periodic low-level pulse signal according to the reference voltage and accordingly outputting the modulated periodic low-level pulse signal as the output clock signal; a delay circuit coupled to one output end of the modulation device for delaying the output clock signal by a predetermined period and accordingly outputting a first corrected clock signal and a second corrected clock signal; wherein the first corrected clock signal and the second corrected clock signal are inverted to each other; and a Phase Lock Loop (PLL) circuit, coupled to the delay circuit, for estimating high-level status and low-level status of the first corrected clock signal and the second corrected clock signal and accordingly generating the reference voltage.