Patent ID: 8583973

Claim:
An apparatus comprising an integrated circuit (IC) chip (e.g., 110 ) comprising: a logic core (e.g., 130 ); a built-in self-test (BIST) module (e.g., 122 ); and an interface (e.g., 140 ) that enables external test equipment (e.g., 150 ) to communicate with the chip, wherein, for BIST testing: the test equipment is external to a circuit board on which the chip is configured; the test equipment transmits test input data to the BIST module via the interface; the BIST module applies the test input data to the logic core; the logic core processes the test input data to generate test output data; the BIST module receives the test output data from the logic core; the BIST module transmits the test output data to the test equipment via the interface; the BIST module is not configured to compare the test output data to golden signature test data; the test equipment is configured to compare the test output data to the golden signature test data to determine whether or not the BIST testing was successful; and the BIST module is configured to (i) generate a cyclic redundancy check (CRC) value for the BIST testing and (ii) compare the CRC value to a golden CRC value stored in the BIST module.