Patent ID: 7164605

Claim:
A semiconductor memory device comprising: a plurality of cell array banks each including a plurality of pages, the same page addresses being assigned to the cell array banks, each bank including a plurality of electrically rewritable and non-volatile memory cells arranged therein; address decode circuits disposed for the respective cell array banks to select pages in the cell array banks; and sense amplifier circuits disposed for the respective cell array banks to read cell data of selected pages in the cell array banks, wherein in a first read cycle selecting a first page in a first cell array bank, a second page in a second cell array bank with the same page address as the first page is read simultaneously with the first page, and then the read data of the first page in the first cell array bank is output, and in a second read cycle successive to the first read cycle, the read data of the second page in the second cell array bank, which has been read in the first read cycle, is output.