Patent ID: 8572628

Claim:
A method of inter-thread data communications in a computer processor with multiple hardware threads of execution, each hardware thread operatively coupled for data communications through an inter-thread communications controller, the method comprising: registering, by the inter-thread communications controller responsive to one or more RECEIVE opcodes, one or more receiving threads executing the RECEIVE opcodes; receiving, from a SEND opcode of a sending thread by the inter-thread communications controller, specifications of a number of derived messages to be sent to receiving threads and a base value; generating, by the inter-thread communications controller, the derived messages, incrementing the base value once for each registered receiving thread so that each derived message comprises a single integer as a separate increment of the base value; sending, by the inter-thread communications controller to each registered receiving thread, a derived message; and returning, from the inter-thread communications controller to the sending thread, an actual number of derived messages received by receiving threads.