Patent ID: 7073106

Claim:
A method for testing stuck-at-faults in circuitry configured to determine matching of memory cell contents comprising the steps of: loading a first register with a first value, wherein said first register is configured to store contents for a row of a memory array; writing said first value into an entry in said memory array; loading a second register with a second value; loading a third register with one of said second value and a third value, wherein said second and said third values are pre-selected to test selector circuits for stuck-at-faults with a pattern, wherein said selector circuits are configured to determine matching of memory cell contents in said memory array, wherein said pattern comprises a first set of bits to be inputted to said selector circuits, wherein said pattern further comprises a second set of bits to be stored in memory cells embedded with said selector circuits; predecoding a value stored in n-most significant bits of said second register and a value stored in n-most significant bits of said third register to produce a predecode value; comparing said predecode value with a value stored in n-most significant bits of said entry in said memory array; and determining if a stuck-at-fault occurred based on said comparison.