Patent ID: 7586352

Claim:
A converter, comprising: a time-delay circuit having an input configured to receive a PWM signal, the time delay circuit configured to delay rising edges of the PWM signal by an ON delay and to delay falling edges of the PWM signal by an OFF delay to form a drive signal available at an output of the time-delay circuit for a semiconductor switch element; wherein the input is connected, via a series connection of a first resistor and a second resistor, to a first terminal of a first capacitor, a second terminal of the first capacitor constantly at a low level; wherein the first terminal of the first capacitor is connected to an input of a comparator, an output of the comparator configured to form the output of the time-delay circuit, the output configured to change between a high level and a low level as a function of a voltage level at the input of the comparator, the voltage level at the input of the comparator being a function of a state of charge of the first capacitor; and wherein a diode is connected in parallel to the second resistor, the first resistor and the second resistor configured to limit a charging current for the first capacitor in response to a change from a low level to a high level at the input of the time-delay circuit, only the first resistor configured to limit a discharging current for the first capacitor upon a change from a high level to a low level at the input of the time-delay circuit.