Patent ID: 8773421

Claim:
A multiplexer configured to receive a plurality of differential signals, to select one that corresponds to a control signal, and to output, via an output port, the differential signal thus selected, the multiplexer comprising: a plurality of differential input ports each configured to receive a corresponding signal from among the plurality of differential signals; and a plurality of buffers respectively provided to the plurality of differential input ports, each comprising a differential input terminal connected to the corresponding differential input port and a differential output terminal connected to the output port, and each configured such that the states thereof are switchable according to the control signal between an enable state in which a differential signal that corresponds to the differential signal input to the differential input terminal is output, and a disable state in which current consumed by the buffer becomes substantially zero and the differential output terminal thereof is set to a high-impedance state, wherein each of the plurality of buffers comprises: the aforementioned differential input terminal; the aforementioned differential output terminal; a first fixed voltage terminal; a second fixed voltage terminal; a first transistor and a second transistor each configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a third transistor and a fourth transistor each configured as an N-channel MOSFET, which are arranged in series between the first fixed voltage terminal and the second fixed voltage terminal; and a fifth transistor configured as a P-channel MOSFET and a sixth transistor configured as an N-channel MOSFET, which are sequentially arranged in series so as to form a path in parallel with a path comprising the second and third transistors, wherein the gates of the second and third transistors are connected to one side of the differential input terminal, and wherein the gates of the fifth and sixth transistors are connected to the other side of the differential input terminal, and wherein the drains of the second and third transistors are connected to one side of the differential output terminal, and wherein the drains of the fifth and sixth transistors are connected to the other side of the differential output terminal, and wherein an inversion signal that is the inversion of the control signal is input to the gate of the first transistor, and wherein the control signal is input to the gate of the fourth transistor.