Patent ID: 7218553

Claim:
A method for programming a memory cell comprising a floating-gate transistor, in a series of programming cycles each comprising: a step of verifying the state of the memory cell followed by applying a pulse of a programming voltage to the memory cell if the verify step shows that the cell is not in the programmed state; the verify step comprising a first read of the memory cell by applying a first read voltage greater than a reference threshold voltage to a control gate of the memory cell, the memory cell being considered not to be in the programmed state with reference to the first read if a first-read current flowing through the memory cell is above a first threshold; wherein the step of verifying the memory cell comprises a second read of the memory cell by applying a second read voltage lower than or equal to the reference threshold voltage to its control gate, the memory cell being considered not to be in the programmed state with reference to the second read if a second-read current flowing through the memory cell is above a second threshold; and wherein programming voltage pulses are applied to the memory cell while the latter is considered not to be in the programmed state with reference to at least one of the two reads, without exceeding a number of programming pulses representative of a failure of the memory cell.