Patent ID: 7537980

Claim:
A method of manufacturing a stacked semiconductor device, comprising: preparing a seed layer that includes impurity regions doped with impurities; forming a first insulation interlayer pattern on the seed layer, the first insulation interlayer pattern having at least one first opening that exposes a surface of the seed layer in the impurity regions; performing a first selective epitaxial growth (SEG) process on exposed surfaces of the seed layer to form at least one first plug including single crystalline silicon germanium that partially fills the at least one first opening; performing a second SEG process on the at least one first plug to form a second plug including single crystalline silicon that fills a remainder of the at least one first opening; performing a third SEG process on the first insulation interlayer pattern to form a first channel layer including single crystalline silicon on the first insulation interlayer pattern; forming a second insulation interlayer on the first channel layer; sequentially removing a portion of the second insulation interlayer, the first channel layer and the at least one second plug over the at least one first plug to form a thru-hole exposing an upper surface of the at least one first plug; completely removing the at least one first plug until the surface of the seed layer in the impurity regions is exposed to form at least one serial opening; and filling the at least one serial opening with at least one metal wiring.