Patent ID: 7509564

Claim:
An encoder comprising: a plurality of N-parallel encoders, each of the N-parallel encoders adapted to accept N symbol inputs, in parallel, during a cycle and produce, in parallel, N symbol outputs during a cycle, and wherein each N-parallel encoder is adapted to produce a plurality of redundancy symbols after a predetermined number of input symbols have been input to the encoder, wherein said N symbol inputs comprise a plurality of input bits, wherein said plurality of redundancy symbols comprise a plurality of output bits, wherein each N-parallel encoder comprises an input delay unit and an output delay unit, wherein each input delay unit delays only a subset of said plurality of input bits, and wherein each output delay unit delays only a subset of said plurality of output bits; and a first device coupled to the N-parallel encoders and adapted to create an M-parallel frame, the M-parallel frame adapted to hold a plurality of codewords, each codeword comprising a plurality of symbols; and a second device coupled to the M-parallel frame and adapted to create a serial data stream from a plurality of symbols in the M-parallel frame.