Patent ID: 8410493

Claim:
A semiconductor device comprising: a first substrate; a second substrate; a multi-level interconnect structure provided over the first substrate; a first inductor provided in the multi-level interconnect structure so as to surround all transistors provided over the first substrate in a plan view; and a second inductor provided in the multi-level interconnect structure so as to surround all the transistors provided over the first substrate in the plan view, wherein the second inductor is provided over the first inductor, wherein the first substrate is provided with a first circuit region containing a first circuit, wherein the second substrate is provided with a second circuit region containing a second circuit, wherein the first inductor is provided in the multi-level interconnect structure so as to include the first circuit region, wherein the second inductor is provided in the multi-level interconnect structure so as to include the first circuit region, and wherein one of the first inductor and the second inductor is connected to the first circuit, and the other of the first inductor and the second inductor is connected to the second circuit.