Patent ID: 7436206

Claim:
A semiconductor integrated circuit comprising: a data non-holding circuit corresponding to a logic circuit which unholds data therein in a standby mode; a data holding circuit corresponding to a logic circuit which needs to hold data therein in the standby mode; a virtual high potential source line connected to source electrodes of respective p-type field effect transistors provided within the data non-holding circuit; a first high potential source line connected to source electrodes of respective p-type field effect transistors provided within the data holding circuit; a second high potential source line supplied with a potential higher than a potential of the first high potential source line; a first high potential switch which connects the first high potential source line and the virtual high potential source line in an operation mode and allows the virtual high potential source line to float in the standby mode; a second high potential switch which connects substrate terminals of the respective p-type field effect transistors provided within the data holding circuit and the first high potential source line in the operation mode and connects the substrate terminals and the second high potential source line in the standby mode; and a gate circuit which inputs an output signal of the data non-holding circuit to the data holding circuit in the operation mode and fixes an input signal value of the data holding circuit in the standby mode.