Patent ID: 8819615

Claim:
A method, comprising: identifying a first assembly of critical logic cells that are series-connected according to a path to be monitored between an input node and an output node; identifying output logic cells which are not in the first assembly but are directly connected to an output of a critical logic cell in the first assembly; determining an equivalent capacitance of said output logic cells connected at the outputs of the critical logic cells for said path; for each critical logic cell, determining a logic level for each input which is not connected to another critical logic cell of said path that will force a signal present at the input node to follow said path; arranging the first assembly on an integrated circuit chip; arranging on said integrated circuit chip a control circuit formed of a second assembly of control logic cells that is an exact copy of the first assembly in terms of number and type of cells and in terms of connection diagram, wherein each of the control logic cells is a homolog of a corresponding one of the critical logic cells; and connecting at least one charge cell at the output of each of the control logic cells so that a total equivalent capacitance at the output of said each control logic cell is equal to the determined total equivalent capacitance for the corresponding critical logic cell.