Patent ID: 7396724

Claim:
A method of fabricating a semiconductor device including a dual-hybrid liner over a PFET and an NFET, the method comprising: depositing a tensile silicon nitride layer over the PFET and the NFET; depositing a hard mask over the tensile silicon nitride layer, the hard mask including one of tetraethyl orthosilicate (TEOS), plasma-enhanced chemical vapor deposited (PECVD) silicon dioxide, carbon doped silicon dioxide and silicon carbide (SiC); removing the hard mask over the PFET to the tensile silicon nitride layer using a first photoresist mask; removing the first photoresist mask; etching to remove the tensile silicon nitride layer over the PFET to a silicide layer adjacent the PFET using the hard mask as a pattern; performing an annealing operation to remove damage to the silicide layer and reduce silicide resistance after etching to remove the tensile silicon nitride layer: depositing a compressive silicon nitride layer over the PFET and the NFET; removing the compressive silicon nitride layer over the NFET using a second photoresist mask; removing the second photoresist mask; and depositing an interlayer dielectric over the PFET and the NFET.