Patent ID: 7307000

Claim:
A method for fabricating a capacitor for a semiconductor device, comprising the steps of: forming a first inter metal dielectric layer on a substrate; forming a first metal layer to fill a trench on the first inter metal dielectric layer; polishing the first metal layer using a chemical mechanical polishing to form a first electrode; forming a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer on the first electrode; patterning the third metal layer using a selective etching to form a third electrode; patterning the second metal layer using a selective etching to form a second electrode that overlaps the first electrode and the third electrode; forming an etch stop layer to cover the first, second, and third electrodes, said etch stop layer being in direct contact with at least the third electrode; forming a second inter metal dielectric layer over the etch stop layer; etching the second inter metal dielectric layer using a selective photolithography process to form via holes to expose the etch stop layer; removing the etch stop layer to expose the first, second, and third electrodes; filling the via holes to form plugs, the plugs electrically connecting the first, second, and third electrodes; and forming metal wirings on the second inter metal dielectric layer to conduct electricity to the first to third electrodes through the plugs.