Patent ID: 8694818

Claim:
A control circuit comprising; a plurality of clock synchronization units configured to shift an input signal in response to sampling clock signals which are inputted thereto; a selection output block configured to select an output signal from output signals of the plurality of clock synchronization units, and output the selected output signal; and a plurality of clock sampling units configured to sample clock signals for sampling periods defined by signals, which are activated before the signals inputted to the plurality of clock synchronization units are activated, thereby generating the sampling clock signals, wherein the plurality of clock sampling units supplies the sampling clock signals to the plurality of clock synchronization units in response to a plurality of sampling control signals to control output periods of the sampling clock signals, wherein the plurality of clock sampling units correspond to the plurality of clock synchronization units in a one-to-one manner and comprise: a first clock sampling unit configured to sample the clock signal for a sampling period defined by a source in signal and an output signal of a first clock synchronization unit corresponding to the first clock sampling unit, thereby generating a first sampling clock signal; and at least one clock sampling unit configured to sample the clock signal for a sampling period defined by an output signal of a previous clock synchronization, unit and an output signal of a corresponding clock synchronization unit corresponding to the at least one clock sampling unit, thereby generating a corresponding sampling clock signal.