Patent ID: 7764132

Claim:
A digital frequency locked-loop (DFLL) circuit residing on a local core of a multi-core microprocessor system for generating a local core clock with a frequency value for driving the local core, comprising: a micro-controller configured to receive a plurality of digital data for characterizing the local core; a digitally-controlled ring oscillator configured to generate the local core clock for the local core, the digitally-controlled ring oscillator having a delay chain disposed between an output of the digitally-controlled ring oscillator and a feedback input of the digitally-controlled ring oscillator, the delay chain having a plurality of delay taps each receiving the local core clock from the output through the feedback input of the digitally-controlled ring oscillator for enabling single or multi-step quantum changes in the frequency value of the local core clock; and a counter device configured to continually validate the frequency value of the local core clock by generating a digital signal representative of the frequency value to the micro-controller, the micro-controller compares the frequency value of the local core clock to a desired clock frequency when the micro-controller receives the digital signal from the counter device, and the micro-controller selects one of the plurality of delay taps based on the comparison to adjust the frequency value of the local core clock towards alignment with the desired clock frequency.