Patent ID: 7451370

Claim:
An integrated circuit providing test pads in addition to scan circuitry comprising: A. core circuitry having a core output lead; B. boundary scan circuitry having a boundary input lead connected to the core output lead and a boundary output lead; C. a bond pad; D. an output buffer having an input lead coupled to the boundary output lead and having an output lead connected to the bond pad; E. a first test signal lead connected to a first test pad; F. a second test signal lead connected to a second test pad; G. a third test signal lead connected to a third test pad; and H. peripheral scan circuitry having a peripheral scan path including scannable cells controlling switches: i. a first switch selectively connecting the first test signal lead to the input lead of the output buffer; ii. a second switch selectively connecting the second test signal lead to the output lead of the output buffer; and iii. a third switch selectively connecting the third signal lead to the output of the output buffer.