Patent ID: 7550992

Claim:
A logic cell for an integrated circuit, the logic circuit comprising: redundant outputs, including a first output equipped with an output transistor of type P and a second output equipped with an output transistor of type N; and an isolation element connecting said first and second outputs and forming an isolation resistance, wherein said isolation element includes: a first isolation transistor of type P mounted in series with a second isolation transistor of type N, with the drains of the first and second isolation transistors being connected respectively to the drains of the first and second output transistors, wherein the gate of the first isolation transistor is connected to a first reference voltage and the gate of the second isolation transistor is connected to a second reference voltage; and a first bypass transistor of type P, of which the gate is connected to the gate of the output transistor of type P, the source is connected to the second reference voltage and the drain is connected to the sources of the isolation transistors, and a second bypass transistor of type N of which the gate is connected to the gate of the output transistor of type N, the source is connected to the first reference voltage and the drain is connected to the sources of the isolation transistors.