Patent ID: 7787277

Claim:
A semiconductor memory device comprising: a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells and a first selection gate transistor; a word line unit comprising a plurality of word lines connected to the plurality of memory cells and included in the memory cell unit, the plurality of word lines each formed by continuously extending control gates of the memory cells; a first word line arranged on one end portion of the word line unit, the first word line being included in the plurality of word lines; and a first selection gate line formed by continuously extending gates of the first selection gate transistors, the first selection gate line located adjacent to the first word line in the memory cell unit; wherein the plurality of word lines are formed by using a mask having a data pattern in which line width of the first word line is larger than line width of a word line located adjacent to the first word line.