Patent ID: 7855456

Claim:
A metal line structure of a semiconductor device, comprising: a lower metal line formed on a semiconductor substrate; an insulation layer formed on the resultant semiconductor substrate, the insulation layer having a metal line forming region exposing at least a portion of the lower metal line; a diffusion barrier formed on a surface of the metal line forming region of the insulation layer, the diffusion barrier comprising: a WN x layer; a W—N—B ternary layer; and a Ti—N—B ternary layer, wherein the W—N—B ternary layer has a thickness in the range of 10 to 100% of the thickness of the WN x layer; a wetting layer formed on the diffusion barrier and made of any one of a Ti layer and a TiN layer; and an upper metal line formed on the wetting layer to fill the metal line forming region of the insulation layer, wherein the WN x layer, the W—N—B ternary layer, the Ti—N—B layer and the wetting layer are formed on the surface of the metal line forming region in sequence.