Patent ID: 8060356

Claim:
A method for emulating a target system having a main target processor, a secondary target processor element and an instruction memory associated with the secondary target processor element with a host system having one or more host processors, a host memory coupled to the host processors, and a presentation device coupled to the one or more host processors, the method comprising: a) emulating the instruction memory, wherein a) includes grouping two or more target system code instructions for the secondary target processor into one or more fragments, each fragment having a known start and a known end, and includes maintaining a data structure that maps the host memory locations of the starts and ends of the fragments; b) implementing a main translation function; wherein b) includes translating each fragment into a corresponding set of position-independent instructions executable by the host system, and storing the one or more fragments at locations in the host memory; c) emulating the secondary target processor, wherein c) includes, loading one or more fragments into one or more of the host processors, determining if a memory layout for target system code corresponding to the one or more fragments has changed, dynamically re-linking the one or more fragments without retranslating the one or more fragments based on changes to the memory layout to produce one or more re-linked fragments, and executing the re-linked fragments on the one or more of the processors; and d) presenting a result based on execution of the re-linked fragments with the presentation device.