Patent ID: 6967897

Claim:
A nonvolatile ferroelectric memory device having a wide page buffering function, comprising: a single cell array block including all cell arrays having a hierarchical bit line architecture for inducing a sensing voltage of a main bit line depending on a sensing voltage of cell data transmitted to a sub bit line; a word line driving unit located at a first side of the single cell array block and for selectively activating a word line of the single cell array block; a plate line driving unit located at a second side of the single cell array block and for selectively activating a plate line of the single cell array block; a wide page buffer unit for simultaneously sensing voltages of all main bit lines in the single cell array block, buffering the sensed data and transmitting the buffered data to a data buffer unit by a predetermined data width in response to a column selecting signal; and a column selecting unit for selectively activating the column selecting signal in response to a column address.