Patent ID: 7668989

Claim:
A semiconductor device comprising: a first semiconductor chip; and a second semiconductor chip that includes a serial interface circuit that transfers serial data between the serial interface circuit and an external device through a serial bus, the second semiconductor chip being stackable above the first semiconductor chip, the second semiconductor chip having a first plurality of electrodes that electrically connect the external device and the serial interface circuit, the first plurality of electrodes being disposed along a first side of the second semiconductor chip, the second semiconductor chip having a second plurality of electrodes that electrically connect an internal circuit included in the first semiconductor chip and the serial interface circuit, the second plurality of electrodes being disposed along a second side of the second semiconductor chip, the second side being a longer side than the first side, a first distance from the second side of the second semiconductor chip to a fifth side of the first semiconductor chip being shorter than a second distance from a fourth side of the second semiconductor chip to the fifth side of the first semiconductor chip, the fifth side of the first semiconductor chip being parallel to the second side of the second semiconductor chip, and the fourth side of the second semiconductor chip being opposite to the second side of the second semiconductor chip, the serial interface circuit including: a first data transfer circuit; a clock transfer circuit; and a second data transfer circuit; the first data transfer circuit, the clock transfer circuit and the second data transfer circuit being disposed along the first side of the second semiconductor chip, the clock transfer circuit being disposed between the first data transfer circuit and the second data transfer circuit, in a single-channel mode, data being transferred by the first data transfer circuit, a clock signal being transferred by the clock transfer circuit, and in a two-channel mode, the data being transferred by the first data transfer circuit and the second data transfer circuit, the clock signal being transferred by the clock transfer circuit.