Patent ID: 8295287

Claim:
A method for controlling access to a bus, the method being implemented by a Network Interface (NI), wherein the NI is coupled to a first memory via the bus, the method comprising: receiving, by a Direct Memory Access (DMA) controller on the NI, a schedule, wherein the schedule indicates one or more timeslots reserved for transmission of deterministic data, wherein the schedule also indicates one or more available timeslots which are not reserved for transmission of deterministic data, wherein the bus receives deterministic data during the one or more timeslots reserved for transmission of deterministic data according to the schedule; receiving, by the NI, first data for transmission onto the bus during a first timeslot of the one or more reserved timeslots, wherein the first timeslot is not an available timeslot, and wherein the first data are received in a non-deterministic manner; determining that the first timeslot is one of the one or more reserved timeslots based on the schedule; buffering the first data in a buffer memory during the first timeslot; and transferring the first data to the first memory via the bus during a second timeslot, wherein the second timeslot is one of the one or more available timeslots, wherein said transferring is performed after said buffering.