Patent ID: 8406059

Claim:
An integrated circuit memory device, comprising: at least a first block of non-volatile memory cells; a volatile memory device having a data storage capacity equivalent to at least a capacity of said at least a first block of non-volatile memory cells; and a memory controller electrically coupled to said at least a first block of non-volatile memory cells and said volatile memory device, said memory controller configured to update a block of data in the first block of non-volatile memory cells by: applying program stresses to erased memory cells in the first block of non-volatile memory cells to thereby increase their threshold voltages concurrently with copying the block of data from the first block of non-volatile memory cells to said volatile memory device; then erasing the entire first block of non-volatile memory cells; and then adjusting threshold voltages of a first plurality of erased memory cells at a first address in the first block of memory cells to thereby narrow a distribution of threshold voltages between the first plurality of erased memory cells concurrently with programming a second plurality of memory cells at the first address with data read from said volatile memory device.