Patent ID: 7400537

Claim:
A non-volatile memory system, comprising: a set of non-volatile storage elements, said set includes a first subset and a second subset of non-volatile storage elements; and managing circuitry in communication with said set of non-volatile storage elements, said managing circuitry erases said set by: enabling erasing of said first and said second subset of non-volatile storage elements, applying one or more erase voltage pulses to said set while said first and second subset are enabled for erasing until said first subset is verified as erased, said managing circuitry excludes said second subset of non-volatile storage elements from verification when verifying whether said first subset is erased, after said first subset is verified as erased, inhibiting said first subset from further erasing while enabling erasing of said second subset, and applying one or more additional erase voltage pulses to said set while said first subset is inhibited and said second subset in enabled until said second subset is verified as erased.