Patent ID: 7123300

Claim:
An image processor arranged in operation to generate an interpolated video signal from a received video signal representative of an image, said image processor comprising: a register store comprising a plurality of register elements and being coupled to a control processor, said register store being arranged in operation to receive said video signal and to provide pixels of said received video signal, under control of said control processor to an interpolator, selected register elements being connected to said interpolator to provide said pixels of said received video signal for interpolation, each of said plurality of register elements being arranged to store a pixel of said received video signal, two or more of said plurality of register elements having an input connected to a first plurality of the register elements and an output connected to a second plurality of the register elements, the first plurality of the register elements not including any of the second plurality of the register elements, and each of said two or more of said plurality of register elements is configurable under control of said control processor to feed the pixel stored in said register element to one of said second plurality of said register elements to which said register element is connected in accordance with a temporal reference, said interpolator being coupled to said register store and arranged in operation to generate said interpolated video signal by interpolating said pixels provided by said register store, wherein said control processor is operable to detect a feature of said image having both vertical and horizontal components, to control the configuration of said register elements to provide the input pixels associated with said feature to said interpolator to interpolate the feature of said image having both the vertical and the horizontal components.