Patent ID: 8108658

Claim:
A data processing circuit, the data processing circuit comprising a register file having read ports and write ports; a plurality of functional units, each functional unit corresponding to one issue-slot, each functional unit being coupled to a respective one of the read ports, and each functional unit being coupled to a respective one of the write ports for writing a respective result; at least one instruction issue slot having outputs for supplying register selection information to the respective ones of the read ports and to the respective ones of the write ports, and an output for an operation code, the functional units of the plurality being coupled to the output for the operation code; wherein the operation code includes either a primary operation codes that cause only one of the functional units to perform an operation at a time or a secondary operation codes that cause a plurality of functional units to perform an operation simultaneously, wherein the functional units are arranged in groups of functional units such that different values of the operation code select respective groups of functional units to enable execution of complicated operations in response to a single operation code and said groups correspond to specific types of command codes, and to receive operand data containing at least one shared operand from at least one read port shared by the functional units; and, the functional units associated with a same instruction issue slot are arranged to simultaneously respond to a value of the operation code by each executing a respective operation using the at least one shared operand, each functional unit of the plurality producing a respective result, obtained by processing the at least one shared operand, at a respective one of the write ports.