Patent ID: 7265012

Claim:
A method of forming a CMOS device comprising: forming a plurality of isolation regions in a substrate; forming at least two first type wells in said substrate; forming at least two second type wells in said substrate; providing a first mask over said substrate overlying at least one of said first type wells; doping said substrate with a first voltage threshold implant; removing said first mask; providing a second mask over said substrate overlying at least one of said second type wells; doping said substrate with a second voltage threshold implant; removing said second mask; forming a gate oxide over said first and second type wells; depositing a gate conductor over said substrate; providing a third mask overlying each of said first type wells; doping said gate conductor with a first gate conductor dopant; removing said third mask; providing a fourth mask overlying each of said second well types; doping said gate conductor with a second gate conductor dopant; removing said fourth mask; forming a plurality of gate stacks over said substrate, at least one gate stack formed over each of said first and second type well; and forming source/drain regions in said substrate about said gate stacks.