Patent ID: 7379382

Claim:
A memory device, comprising: a memory array operable to store write data responsive to a write command at a location corresponding to an address applied to the memory device, the memory array being operable to output read data responsive to a read command from a location corresponding to an address applied to the memory device; and a read data output circuit coupled to receive the read data from the memory array, the read data output circuit comprising: a plurality of data latches, each of the data latches having a clock input, a data input, and an output on which a respective read data signal is transmitted from the memory device, each of the data latches being operable to receive at its data input a respective bit of the read data from the memory array; a signal distribution tree having an input node coupled to receive a first digital signal and a plurality of output nodes each of which is coupled to the clock input of a respective one of the data latches; a phase interpolator in a signal path of the signal distribution tree between the input node and each of the output nodes; and a delay line in at least one signal path of the signal distribution tree between the input node and at least one of the output nodes.