Patent ID: 7143268

Claim:
A data processor comprising: a plurality of execution clusters, each of said execution clusters comprising an instruction execution pipeline having a plurality of processing stages capable of executing instruction bundles each comprising one or more syllables, wherein each of said instruction execution pipelines is a plurality of lanes wide, each of said lanes capable of receiving one or more of said syllables of said instruction bundles; an instruction cache capable of storing a plurality of cache lines, each of said cache lines comprising a plurality of the syllables; an instruction issue unit capable of receiving fetched ones of said plurality of cache lines and issuing complete instruction bundles toward said execution clusters, wherein at least one complete instruction bundle is issued having an out-of-order alignment; and alignment and dispersal circuitry capable of receiving said complete instruction bundles from said instruction issue unit and routing each of said received complete instruction bundles to a correct one of said execution clusters as a function of at least one address bit associated with each of said complete instruction bundles, the alignment and dispersal circuitry also capable of reordering each of the at least one complete instruction bundle having the out-of-order alignment so as to align the syllables in the complete instruction bundle with correct ones of the lanes.