Patent ID: 8365031

Claim:
A memory control apparatus for a memory system having a plurality of memories configured to store byte-sliced data, a plurality of memory access controllers provided in correspondence with the plurality of memories and respectively configured to make an access in cycle synchronism with respect to a corresponding one of the plurality of memories, and a system controller configured to issue a read request with respect to the plurality of memory access controllers, comprising: a first circuit configured to hold an error address where a correctable error is detected when the correctable error is detected in data read from one of the plurality of memories; a second circuit configured to make an error notification with respect to the system controller; a third circuit configured to receive an error correction request and a dummy read address from the system controller; and a fourth circuit configured to read the data from the error address and perform a soft error correction when the first circuit holds error address and the error correction request is received by the third circuit, and to read the data from the dummy read address received by the third circuit and write back the read data when the first circuit does not hold the error address.