Patent ID: 8281279

Claim:
A method, executed by a data processing system, for creating a shift register definition from high-level model using high-level model simulation, the method comprising: initializing, by the data processing system, all potential scan chain latches in a high-level integrated circuit model; for each scan chain, identifying, by the data processing system, latches in the scan chain; separating, by the data processing system, each scan chain into groups of latches, wherein each group of latches is a sub-portion of its respective scan chain; for each group of latches in a given scan chain, identifying, by the data processing system, latches that change after each shift until all groups of latches in the given scan chain are defined and ordered; and responsive to the data processing system determining that a divergence occurs for the given scan chain, isolating, by the data processing system, a scan path latch for each shift with a divergence in the given scan chain.