Patent ID: 8829945

Claim:
A circuit comprising: a delay circuit including an input for receiving a signal and an output for providing a delayed version of the signal; a transition detector coupled to the input of the delay circuit and including a detector output, the transition detector to detect a transition within the signal and to provide a look ahead signal to the detector output in response to detecting the transition; a pre-driver circuit including an input coupled to the output of the delay circuit to receive the delayed version of the signal, a control input, at least one signal output, and a plurality of bias outputs; a controller coupled to the detector output to receive the look ahead signal and to the control input of the pre-driver circuit to provide a control signal, the controller to control bias signals on the plurality of bias outputs to selectively increase a driving strength of signals and biases applied to an output stage in response to the look ahead signal; and the output stage including a first transistor having a control terminal coupled to the at least one signal output of the pre-driver circuit to receive the delayed version of the signal and including a second transistor coupled between the first transistor and an output node and having a control terminal coupled to one of the plurality of bias outputs of the pre-driver circuit; and a timer configured to start in response to a delayed transition within the delayed version of the signal.