Patent ID: 7394273

Claim:
A packaged semiconductor chip, comprising: a semiconductor chip including a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of said semiconductor chip; and a package element having a plurality of external features conductively connected to said plurality of conductive features of said semiconductor chip, said semiconductor chip further including a monitored element including a conductive interconnect conductively interconnecting a first node of said semiconductor chip to a second node of said semiconductor chip, a detection circuit operable to compare a variable voltage drop across said monitored element with a reference voltage drop across a reference element on said chip at a plurality of different times during a lifetime of said packaged semiconductor chip to detect when a resistance of said monitored element is over threshold; a redundancy conductive interconnect, and a redundancy control circuit, said redundancy control circuit being operable in response to said resistance of said monitored element being detected over said threshold value to disconnect said monitored element and connect said redundancy conductive interconnect in place of said monitored element.