Patent ID: 7172939

Claim:
A method for forming a memory device, the method comprising a sequence of steps: providing a substrate comprising a surface region; forming well structure within the substrate, the well structure including a cell well region for a plurality of cell regions and a peripheral well region for a peripheral region; forming a gate dielectric layer overlying the surface region, the surface region extending over the cell well region and the peripheral well region; forming polysilicon film overlying the gate dielectric layer overlying the well structure; forming cap layer overlying the polysilicon film; selectively removing a portion of the cap layer overlying the cell regions to expose the polysilicon film overlying the cell regions while maintaining the cap layer on the peripheral region; forming a blanket nitride layer overlying the cap layer and exposed cell region; forming a plurality of word gates by patterning the polysilicon film in the cell region while using a portion of the nitride layer as a hard mask while exposing a portion of the surface of the substrate between each of the word gates; forming control gate channel implant; forming an oxide-on-nitride-on oxide layer overlying the word gates and exposed portion of the surface of the substrate between each of the word gates; forming a pair of polysilicon sidewall spacers on each word gate to form a pair of control gates while each pair of control gates is being isolated electrically from the word gate by a portion of the oxide-on-nitride-on-oxide layer, each of the control gates also being overlying a portion of the oxide-on-nitride-on oxide; forming cell LDD structures for each of the control gates; forming a buried bit line structure within a portion of the substrate for each of the LDD structures; forming an interlayer dielectric overlying regions within each of the word gate structures; protecting the cell regions; and processing the peripheral region while maintaining the protection on the cell region.