Patent ID: 8921173

Claim:
A method for fabricating an integrated circuit (IC) on a semiconductor substrate, the method comprising: forming a conductively doped buried layer below an upper surface of a semiconductor substrate, wherein the conductively doped buried layer has a first conductivity type; forming a first well region that extends from the upper surface of the semiconductor substrate to the conductively doped buried layer, wherein the first well region has the first conductivity type; forming a field dielectric region at the upper surface of the semiconductor substrate, wherein the field dielectric region defines a first active region; and fabricating a vertical double-diffused metal-oxide-semiconductor (DMOS) structure within the first active region by: forming a gate dielectric layer over the first active region; forming a polysilicon layer over the gate dielectric layer; forming a mask over the polysilicon layer; etching the polysilicon layer through the mask, thereby forming one or more gate electrodes over the first active region; performing a first implant through the mask, thereby forming a plurality of body regions in the first well region, wherein the body regions have a second conductivity type, opposite the first conductivity type, and wherein the body regions are aligned with the gate electrodes; forming a pre-metal dielectric layer over the field dielectric region; and forming a deep metal plug that extends through the pre-metal dielectric layer, the field dielectric region and the first well region, and into the conductively doped buried layer.