Patent ID: 7129578

Claim:
A substrate for a semiconductor device comprising: an insulating substrate body having a plurality of cut-away portions cut away from at least one side edge surface thereof at a distance from each other, and defining an elongated surface of each of said cut-away portions for receiving gathered ends of wiring for surface treatment, and defining between an adjacent pair of said cut-away portions a protrusion serving as a chucking portion for allowing said substrate body to be chucked; a die pad for securing a semiconductor chip, said die pad being positioned on said insulating substrate body; a plurality of bonding electrodes surrounding said die pad; a plurality of external electrodes for allowing said substrate for a semiconductor device to be mounted, each external electrode being electrically connected to a corresponding one of said plurality of bonding electrodes and being positioned under said insulating substrate body; a plurality of wiring segments being divided into a plurality of wiring segment groups for surface treatment, gathered ends of which terminate at said elongated surface of said cut-away portions, wherein each wiring segment of a wiring segment group extends on said insulating substrate body such that each wiring segment connects each external electrode to the corresponding one of said plurality of bonding electrodes through a common one of the plurality of cut-away portions; and wiring for supplying power to said semiconductor chip and for grounding, wherein the wiring for supplying power to said semiconductor chip and for grounding is located at least at one of the side edges of said insulating substrate body except for said cut-away portion wherein the wiring for supplying power to said semiconductor chip and for grounding is located on both sides of said wiring for surface treatment, said wiring for surface treatment being located at said portion of said side surface of said insulating substrate body, and said portion being opposed to said cut-away portion, and wherein said wiring for surface treatment is positioned between one wiring for supplying power to said semiconductor chip and for grounding and the other wiring for supplying power to said semiconductor chip and for grounding, and wherein said wiring for supplying power to said semiconductor chip and for grounding has a width wider than that for said wiring for surface treatment for enhancing resistance to electrostatic damage.