Patent ID: 8039310

Claim:
A manufacturing method for a semiconductor device comprising: (a) setting a plurality of semiconductor chip disposal regions, each for one of a plurality of semiconductor chips to be disposed thereon, at a predetermined pitch on a base, each of the plurality of semiconductor chips having a first main surface with a plurality of electrode pads provided thereon, a surface protecting film formed on the first main surface and exposing the electrode pads, a second main surface opposite to the first main surface, and a plurality of side surfaces between a surface of the surface protecting film and the second main surface; (b) forming an extension portion from an insulating material such that a plurality of concave portions are formed on the base, each of the concave portions being defined by inside walls, with a bottom surface portion of each concave portion defined by a lowermost portion of the inside walls matching a profile of the second main surface of one of the plurality of semiconductor chips, the inside walls being gradually thinner towards a center of the concave portion; (c) providing the plurality of semiconductor chips each in a corresponding one of the plurality of concave portions, the second main surface thereof facing the bottom surface of the corresponding one concave portion, and the side surfaces thereof being in contact with the lowermost portion of the inside walls of the corresponding one concave portion; (d) forming wiring patterns extending from the electrode pads to a region including an upper side of the extension portion; (e) forming a plurality of external terminals over the wiring patterns in the region including the upper side of the extension portion; and (f) severing the plurality of semiconductor chips to form individual semiconductor devices each having one of the plurality of semiconductor chips.