Patent ID: 8462841

Claim:
A video processing device comprising; a bitstream accelerator module having an input configured to receive a stream of encoded video data in a first video format or a second video format, and an output configured to access a memory, in which the memory is configured to store intermediate video data, wherein the bitstream accelerator module is configured to decode the stream of encoded video data from multiple formats and is configured to decode the stream of encoded video data in the first or second video formats to provide the intermediate video data in a common output video format; and a video processing engine configured to access the memory to read the intermediate video data, in which the video processing engine is configured to decode the intermediate video data that is in the common output video format to generate video data in the first or second video formats, wherein the bitstream accelerator is configured to: detect a neighbor macro block of a first macro block location; read a portion of the neighbor macro block from the memory; use the portion of the neighbor macro block to generate a first macro block corresponding to the first macro block location; and write the first macro block to the memory.