Patent ID: 8316188

Claim:
A processor comprising: a data cache configured to store a plurality of cache tags and a corresponding plurality of cache blocks; a duplicate cache tags configured to store a duplicate copy of the plurality of cache tags, and wherein the processor is further configured to detect snoop hits for snooped memory operations by checking the duplicate cache tags; and a prefetch unit configured to generate prefetch requests to prefetch data into the data cache, wherein the prefetch unit is coupled to the duplicate cache tags and is configured to check the duplicate cache tags to detect whether or not the prefetch request misses in the data cache, wherein the prefetch request proceeds to fetch a cache block into the data cache responsive to detecting that the prefetch request misses in the data cache by checking the duplicate cache tags, and wherein the processor is configured to check the prefetch request for the data cache miss during a clock cycle that the duplicate cache tags are idle for snooped memory operations.