Patent ID: 7498632

Claim:
A flash memory device comprising: a silicon substrate having formed thereon a wall-type silicon body connected with the substrate; a first insulating film formed on the surface of the silicon substrate and the surface of the silicon body; a nitride film formed on the first insulating film; a second insulating film for element isolation formed on the nitride film so as to reach the surface level of the silicon body; a charge storage node, a control electrode, an inter-electrode insulating film and a control electrode, sequentially formed on the resulting structure; a region to be used as a channel, which is recessed from the surface of the silicon body to a reasonable depth; the second insulating film being, if necessary, recessed from the surface to a reasonable depth; the first insulating film and the nitride film being etched more than the recess width or depth of the silicon body; a tunneling insulating film formed on the surface and sides of the recessed region of the silicon body; a charge storage node, an inter-electrode insulating film and a control electrode sequentially formed on the resulting structure; and source/drain regions formed to a depth in the silicon body on both sides of the gate stack wherein the gate stack consisting of a charge storage node, an inter-electrode insulating film, and a control electrode, and an insulating film spacer formed on both sides of the gate stack.