Patent ID: 7315540

Claim:
A data switching circuit, comprising: at least one input for receiving during a same time period a plurality of data streams, wherein each of the data streams comprises a plurality of like-sized data quantities; a plurality of addressable memories, wherein each of the plurality of addressable memories comprises a plurality of memory cells; circuitry for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time; and reading circuitry, coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities alternately to respective multiple output channels; wherein M is an integer greater than one; wherein each of the data streams consists of an integer number N TS of time slots; wherein each of the plurality of addressable memories consists of a number of rows equal to N TS times M; wherein the plurality of data streams consists of an integer number N in of data streams; wherein each of the plurality of addressable memories consists of a number of columns equal to a rounded up integer of a quotient equal to N in divided by M; wherein each of the plurality of addressable memories consists of an integer number N c of columns, the columns comprising the memory cells; wherein the circuitry for writing writes data to each of the integer number N c of columns at a same time; and wherein the reading circuitry comprises: sense amplifier circuitry; and switching circuitry coupled between groups of the integer number N c of columns and the sense amplifier circuitry, wherein the switching circuitry is operable to select a subset of columns from each of the groups to which it is coupled and to provide signals from the selected subset to the sense amplifier circuitry.