Patent ID: 7876592

Claim:
A system comprising: a system board including: a setup module configured to output an optimized signal if each of a plurality of dual in-line memory modules connected to a system board are voltage optimized dual in-line memory modules, and configured to output a standard signal if each of the plurality of dual in-line memory modules connected to the system board are standard dual in-line memory modules; a first voltage regulator in communication with a first plurality of dual in-line memory module voltage pins, the first voltage regulator configured to output a first voltage to the first plurality of dual in-line memory module voltage pins in response to receiving the optimized signal, and further configured to output the first voltage to the first plurality of dual in-line memory module voltage pins in response to receiving the standard signal; and an isolation switch in communication with a second plurality of dual in-line memory module voltage pins, the isolation switch configured to output a second voltage to the second plurality of dual in-line memory module voltage pins in response to receiving the optimized signal; and a dual in-line memory module connected to the system board, the dual in-line memory module including: a dynamic random access memory having a first input terminal connected to the first plurality of dual in-line memory module voltage pins, and a second input terminal, the dynamic random access memory configured to receive the first voltage on the first input terminal; and a second voltage regulator having an input terminal connected to the second plurality of dual in-line memory module voltage pins, and an output terminal connected to the second input terminal of the dynamic random access memory, the second voltage regulator adapted to receive the second voltage, and configured to provide a third voltage to the second input terminal of the dynamic random access memory.