Patent ID: 7675522

Claim:
A video signal processing circuit, comprising: a GRAM which stores pixel data, which is data corresponding to pixels of a display screen, at least in the amount equivalent to said display screen, said pixel data being written in said GRAM in synchronization to a memory clock signal; a latch circuit which reads and stores pixel data corresponding to pixels representing a scanning line of said display screen from said GRAM; and a control unit, wherein said pixel data corresponding to said pixels representing said scanning line stored in said latch circuit is displayed on said display screen, in the case of contention between writing of said pixel data in said GRAM and reading of said pixel data corresponding to said pixels representing said scanning line to said latch circuit from said GRAM, said control unit delays for a predetermined delay time reading of said pixel data corresponding to said pixels representing said scanning line and controls so as to perform reading of said pixel data corresponding to said pixels representing said scanning line to said latch circuit from said GRAM once again, and said control unit comprises a delay unit which delays and inputs a display read control signal and a data latch signal for said predetermined delay time during a period which is after a point at which said memory clock signal corresponding to writing of said pixel data in said GRAM is supplied, said writing accompanying said contention, but which is before supplying of the next memory clock signal following said memory clock signal so that said latch circuit reads pixel data corresponding to pixels representing said scanning line.