Patent ID: 7166889

Claim:
A non-volatile semiconductor memory device, comprising: a memory cell having a tunnel oxide layer formed on a semiconductor substrate, a floating gate formed on the tunnel oxide layer, a control gate to which voltage is supplied, a source diffusion layer and a drain diffusion layer, the source and drain diffusion layers formed in the semiconductor substrate adjacent to the tunnel oxide layer; a contact layer connected to the drain diffusion layer; and a layer formed above the memory cell, the layer comprising at least one of: 1) a silicon oxide layer to which aluminum are doped, 2) an aluminum oxide layer, 3) a silicon oxide layer to which titanium are doped, 4) a silicon oxide layer to which two of nitrogen, aluminum, and titanium are doped, 5) a silicon oxide layer to which nitrogen, aluminum, and titanium are doped, 6) a titanium oxide layer, 7) a titanium and aluminum oxide layer, 8) a simple metal layer comprising one of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, 9) an alloy layer comprising at least two of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, and the at least two of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc being included 50% or more, 10) a nitrogenous layer of the alloy layer, and 11) a hydrogenated layer of the alloy layer.