Patent ID: 7872922

Claim:
A memory system comprising: a nonvolatile semiconductor memory including a first physical original block and a second physical original block both comprising n (n being natural number) write unit areas, and a first physical subblock and second physical subblock both comprising a plurality of write unit areas; and a controller which: writes data having one of first to p-th (p being natural number smaller than n) logical addresses into the first physical original block and data having one of (p+1)-th to m-th (m being natural number not smaller than p+2 and not larger than n) logical addresses into the second physical original block, writes, when the controller receives a request to write data which has one of the first to p-th logical addresses and exists in the first physical original block, the write-request-target data into a write unit area of the first physical subblock having a physical address which follows a physical address of a write unit area of the first physical subblock which stores the data written lastly in the first physical subblock and which is followed by a physical address of a write unit area which stores no data, writes, when the controller receives a request to write data which has one of the (p+1)-th to m-th logical addresses and exists in the second physical original block, the write-request-target data into a write unit area of the second physical subblock having a physical address which follows a physical address of a write unit area of the second physical subblock which stores the data written lastly in the second physical subblock and which is followed by a physical address of a write unit area which stores no data.