Patent ID: 7110297

Claim:
A semiconductor storage device, comprising: a memory array comprising a plurality of memory elements, each of the plurality of memory elements comprising a gate electrode provided via a gate insulating film on a semiconductor layer, a channel region provided under the gate electrode, a first diffusion region and a second diffusion region provided on opposite sides of the channel region and having a conductivity type opposite to that of the channel region, and a first memory function section and a second memory function section provided on opposite sides of the gate electrode and having a function of retaining charges, the gate electrode of each memory element being connected to one of a plurality of word lines, the first diffusion region and the second diffusion region of each memory element each being connected to one of a plurality of bit lines; a row decoder for selecting one of the plurality of word lines in accordance with a row address; and a write control circuit for applying a write pulse to a bit line, which is connected to one of the first diffusion region and the second diffusion region of the memory element connected to the selected word line, in accordance with a column address, wherein the write control circuit controls the application of the write pulse so that a quantity of charges retained in one of the first memory function section and the second memory function section of the memory element corresponds to a value of multibit data.