Patent ID: 7485530

Claim:
A method for manufacturing an integrated circuit memory device, comprising: providing a semiconductor body having a first conductivity type; forming a continuous charge storage structure on the semiconductor body; depositing a first gate conductor layer over the charge storage structure; patterning the first gate conductor layer to define a first plurality of wordlines over the continuous charge storage structure, the first plurality of wordlines arranged in parallel with spaces between them over a plurality of continuous, multiple-gate channel regions; forming an isolation layer of material on sidewalls of the first plurality of wordlines; depositing a second gate conductor layer over the isolation layer on the sidewalls and over the continuous charge storage structure in the spaces between the first plurality of wordlines, and isolated from the first plurality of wordlines by the isolation layer; to define a second plurality of wordlines over the continuous charge storage structure on the semiconductor body, the first plurality of wordlines and the second plurality of wordlines arranged in parallel over the plurality of continuous, multiple-gate channel regions, the first and second pluralities of wordlines including a first word line and a last wordline, and providing a plurality of gates in series over respective continuous, multiple-gate channel regions to provide a plurality of multiple-gate memory cells; and defining a first contact line in the semiconductor body parallel to and adjacent to the first wordline in the series and a second contact line in the semiconductor body parallel to and adjacent to the last wordline in the series to provide source and drain terminals for the plurality of multiple-gate memory cells.