Patent ID: 7405972

Claim:
A non-volatile memory, comprising: a plurality of memory units arranged in a row/column array, neighboring memory units in the same row being disposed in a mirror symmetry manner, each memory unit comprising: a first conductive type well disposed within a substrate; a second conductive type drain region, a second conductive type doped region and a second conductive type source region disposed within a first conductive type well; a select gate disposed on the substrate between the second conductive type source region and the second conductive type doped region; a control gate disposed on the substrate between the second conductive type doped region and the second conductive type drain region; and a charge storage structure comprising at least a charge storage layer disposed between the control gate and the substrate; the non-volatile memory further comprising: a plurality of drain lines arranged in parallel in the column direction and connected with the second conductive type drain regions of the memory units in one column; a plurality of bit lines arranged in parallel in the row direction and connected with the second conductive type source region of the memory units in one row; a plurality of word lines arranged in parallel in the column direction and connected with the select gate of the memory units in one column; and a plurality of control lines arranged in parallel in the column direction and connected with the control gates of the memory units in one column, wherein every two control lines are electrically connected together; the two columns of memory units with the electrically connected control lines compose a page; and the two neighboring memory units in the same page in the row direction commonly share the second conductive type drain region.