Patent ID: 7463538

Claim:
A semiconductor memory device, comprising: an input and output line to transfer data to be written to a plurality of memory cells; a precharge control circuit to generate a precharge control signal, the precharge control circuit including: a precharge blocking unit to generate a precharge blocking signal, the precharge blocking signal to maintain disabled the input and output line precharge even after the second write command when other commands are not being applied after the first write command; and a precharging unit to generate a precharge control signal, the precharge control signal to control precharging the input and output line responsive to the precharge blocking signal, where the precharge control signal is adapted to disable the input and output line precharge responsive to a continuous write operation within a same memory bank, the precharging unit including: a logic circuit to logically manipulate an inverted version of the precharge blocking signal and a column select line disable signal; and a latch circuit to generate the precharge control signal by latching an output of the logic circuit and a column select line enable signal; and a plurality of memory banks each including a plurality of memory cells, where the continuous write operation occurs within the same memory bank according to a same memory bank address.