Patent ID: 8635426

Claim:
A memory device comprising: one or more memory arrays each comprising a plurality of memory storage locations; an address input for receiving a memory address to be transformed into a physical address within the one or more memory arrays; a row address decoder/selector configured to select one or more physical-address locations within the one or more memory arrays along a first dimension; a column address decoder/selector configured to select one or more physical-address locations within the one or more memory arrays along a second dimension different from the first dimension; and transforming logic configured to (i) transform a first portion of the address received at the address input, thereby forming a transformed address portion, and (ii) direct the transformed address portion to the row address decoder/selector, wherein (i) the row address decoder/selector selects physical-address locations based on the transformed address portion and a second portion of the address different from the first portion, (ii) the column address decoder/selector selects physical-address locations based on the first portion of the address, and (iii) the physical-address locations selected by the row address decoder/selector and the column address decoder/selector fall along a generally diagonal path within the one or more memory arrays.