Patent ID: 8012842

Claim:
A method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer, the method comprising: using a first patterned photomask to form in the bulk semiconductor wafer a first doped buried region of a first dopant type underneath a collector of a first bipolar transistor structure plus a first doped tank region of a second dopant type underneath the first doped buried region; using a second patterned photomask to form a second doped buried region of the second dopant type underneath a collector of a second bipolar transistor structure plus a second doped tank region of the second dopant type underneath the second doped buried region; using the second patterned photomask to also form a third doped buried region of the second dopant type underneath a contacting sinker adjacent to the first bipolar transistor structure plus a third doped tank region of the second dopant type underneath the third doped buried region, the third doped tank region being in contact with the first doped tank region; forming a base of the first bipolar transistor coupled to the collector of the first bipolar transistor and a base of the second bipolar transistor coupled to the collector of the second bipolar transistor; and forming an emitter of the first bipolar transistor coupled to the base of the first bipolar transistor and an emitter of the second bipolar transistor coupled to the base of the second bipolar transistor.