Patent ID: 7315905

Claim:
A system-on-chip integrated circuit comprising: at least one digital module having a reset input permitting said digital module to be placed in either a normal mode or in a reset mode; a peripheral initialization register having a bit corresponding to each of said at least one digital module, each bit storing either a first digital state indicating a normal mode for the corresponding digital module or a second opposite digital state indicating a reset mode for the corresponding digital module, each bit connected to said reset input of said corresponding digital module; a direct memory access unit connected to each of said at least one digital module and to said peripheral initialization register, said direct memory access unit operable to receive, prioritize and queue date movement transactions between said digital modules, generate a pending transaction signal for each digital module indicating whether said direct memory access unit controls an uncompleted data movement transaction involving said digital module, and read from and write to said peripheral initialization register; and a peripheral interface unit disposed between said direct memory access unit and said peripheral initialization register, said peripheral interface unit operable to prevents a write to said peripheral initialization register changing a digital module from said reset mode to said normal mode while said direct memory access unit indicates an uncompleted data movement transaction involving said digital module.