Patent ID: 7529875

Claim:
A method comprising: assigning interrupts for a plurality of input/output (I/O) devices among a plurality of nodes of a system based on at least one of the nodes to which the I/O devices are connected; the nodes at which interrupt service routines for the I/O devices reside; and, processors of the nodes for the nodes having processors, where one or more of the nodes are processorless and/or memoryless and one or more other of the nodes have processors and memory, wherein assigning the interrupts for the I/O devices among the nodes of the system comprises, for a given interrupt for a given I/O device, the given I/O device connected to a first node of the nodes of the system, the given I/O device having an interrupt service routine to handle the given interrupt, the interrupt service routine residing at a second node of the nodes of the system, the first node being different than the second node, in order from (a)-(c): (a) where the first node to which the given I/O device is connected has a cache, memory, and at least one processor, and the second node at which the interrupt service routine of the given I/O device resides does have a cache, memory, and at least one processor, assigning the given interrupt for the given I/O device to the first node; (b) where the first node does not have a cache, memory, and at least one processor, the second node at which the interrupt service routine of the given I/O device resides does have a cache, memory, and at least one processor, and a third node of the nodes of the nodes of the system has memory and at least one processor, assigning the given interrupt for the given I/O device to the second node; (c) where both the first node and the second node do not each have a cache, memory, and at least one processor, assigning the given interrupt for the given I/O device to the third node, the third node being different than the first node and the second node; for each node having processors, assigning the interrupts for the devices that are performance critical and that have been assigned to the node among the processors of the node in a round-robin manner; dynamically modifying assignments of the interrupts among the nodes of the system based on actual performance characteristics of the assignments; and, for each node having processors, dynamically modifying assignments of the interrupts that are performance critical and that have been assigned to the node among the processors of the node based on actual performance characteristics of the assignments.