Patent ID: 7211460

Claim:
A method for exposing at least a portion of a device feature on a semiconductor device, the method comprising: forming a plurality of alignment marks on the semiconductor device; and grinding away portions of the semiconductor device to expose the device feature, wherein the rate of grinding is varied based on exposure of at least some of the alignment marks, wherein: forming a plurality of alignment marks on the semiconductor device comprises: forming a pair of first alignment marks on the semiconductor device that are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature; forming a pair of second alignment marks on the semiconductor device that are aligned along a second direction with the device feature, which is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature, wherein one of the second alignment marks is on the device feature; and forming a pair of third alignment marks on the semiconductor device that are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks; and grinding away portions of the semiconductor device comprises grinding a side face of the semiconductor device in the second direction to substantially simultaneously expose the first alignment marks, the second alignment mark on the device feature, and the third alignment marks.