Patent ID: 8737161

Claim:
A system for use with a DRAM, said system comprising: a DQS signal generating portion operable to provide a DQS signal to the DRAM at a first time; a clock signal generating portion operable to provide a clock signal to the DRAM; a delay determining portion operable to receive a delay signal from the DRAM and to generate a delay value based on the received signal; an adjustment portion operable to generate an adjustment value based on the delay value; and a controlling portion, wherein said DQS signal generating portion is operable to provide a second DQS signal to the DRAM, wherein said controlling portion is operable to instruct said DQS signal generating portion to provide the second DQS signal at a second time based on the adjustment value, and wherein the delay signal corresponds to the DRAM having received the DQS signal prior to receiving the clock signal.