Patent ID: 8187941

Claim:
A method of manufacturing a semiconductor device having a power MISFET, comprising steps of: (a) forming a first layer of a first conductivity type over a semiconductor substrate of the first conductivity type; (b) forming a first insulating film over the first layer; (c) patterning the first insulating film such that the first layer is exposed from the first insulating film; (d) forming a first trench in the first layer and the semiconductor substrate using the first insulating film as a mask; (e) filling a second layer of a second conductivity type opposite to the first conductivity type into the first trench; (f) removing the first insulating film, an upper surface of the second layer being higher than an upper surface of the first layer; (g) forming a second insulating film over the first layer and the second layer; (h) etching the second insulating film to form a side wall spacer over a side wall of the second layer; (i) forming a second trench in the first layer by using the side wall spacer as a mask; (j) removing the second insulating film; (k) forming a gate insulating film in the second trench; (l) forming a gate electrode over the gate insulating film such that the second trench is filled by the gate insulating film and the gate electrode; (m) forming a third layer of the second conductivity type in the first layer and the second layer by an ion introducing method; (n) forming a fourth layer of the first conductivity type in the third layer by an ion introducing method; (o) forming a fourth insulating film over the gate electrode; (p) forming a third trench in the fourth layer and the third layer using the fourth insulating film as a mask, whereby a side surface of the fourth layer is exposed; and (q) depositing a metal film in the third trench such that the metal film contacts the third layer and the side surface of the fourth layer.