Patent ID: 7224597

Claim:
A ferroelectric memory device for storing data by using a plurality of memory cells composed of combinations of ferroelectric capacitors and transistors, the ferroelectric memory device comprising: a main bit line disposed intersecting word lines; a plurality of local bit lines associated with the main bit line and disposed intersecting the word lines; a plurality of first switching elements provided between the local bit lines and the main bit line, respectively, for selectively connecting one of the plurality of local bit lines to the main bit line; a plurality of memory cells provided at intersecting positions between the word lines and the plurality of local bit lines, respectively; and a plurality of redundant memory cells provided at intersecting positions between the main bit line and the word lines, wherein, when the memory cells include a malfunctioning memory cell, the malfunctioning memory cell is prohibited from operating, and the redundant memory cell performs a substitute operation, and conduction states of the plurality of first switching elements are set such that the local bit line connected with the malfunctioning memory cell is connected to the main bit line.