Patent ID: 8310316

Claim:
An on-chip oscillator circuit mounted on a semiconductor substrate, wherein a first wiring layer and a plurality of second wiring layers having a thickness smaller than the first wiring layer are stacked on the semiconductor substrate; wherein the oscillator circuit comprises: an inductor formed by the plurality of second wiring layers, and an inverter circuit including an n-type MISFET and a p-type MISFET; wherein the inductor is connected to the inverter circuit so as to operate as a load on the inverter circuit; wherein the inductor is operable to oscillate at a frequency at which the inductor and a parasitic capacitance of the inverter circuit resonate; wherein a drain of the n-type MISFET and a drain of the p-type MISFET are connected to each other, and an output of the inductor is connected to a connection point of those drains; wherein the plurality of second wiring layers forming the inductor includes a first layer to an nth layer stacked on each other where n is an integer not less than 2, each of the first layer to the nth layer extends substantially concentrically with respect to a common center from an outermost turn as a first turn to an innermost turn as an mth turn where m is an integer not less than 2 and has a discontinuous end in each turn, wiring layers of the plurality of second wiring layers that are located vertically adjacent to each other are connected to each other through a via at a location at which each of the wiring layers has the discontinuous end such that currents flow in the same direction through the wiring layers, turns located radially adjacent to each other in a wiring layer of the uppermost layer or the lowermost layer of the plurality of second wiring layers are connected to each other at a location at which each of the turns has the discontinuous end such that currents flow in the same direction through the turns, the inductor is connected continuously from an end of the first turn of the first layer that is not connected to another turn to an end of the mth turn of the first layer or the nth layer that is not connected to another turn, and currents flow in the same direction through turns stacked vertically adjacent to each other, and currents flow in the same direction through turns arranged adjacent to each other in each of the plurality of second wiring layers.