Patent ID: 7822070

Claim:
A bus station circuit comprising: a bus interface configured to receive command messages and data from a bus; a detector configured to detect transmission of synchronisation patterns on the bus; and a message processing circuit configured to process the messages and the data, and to switch from a synchronisation disabled state to a synchronisation enabled state in response to detection of a synchronisation pattern, define at least a first time-slot and a second time-slot that follows on the first time slot, both time-slots between a pair of successive synchronisation patterns, during the first time-slot: identify starting points of successive messages head to tail from the end points of immediately preceding messages when operating in a synchronization enabled state, test content of the messages for validity, and switch to a synchronization disabled state wherein the identification of starting points is disabled subsequent to a message with invalid content, in response to detection of the message with invalid content, detect the start of the second time slot in which synchronisation is maintained in a different way before the next synchronisation pattern is received, and upon the detected start of the second time-slot, switch to a mode wherein the second one of the bus station circuits receives data from the second time-slot as a whole.