Patent ID: 8164870

Claim:
An ESD protection arrangement for a high-voltage I/O pad, comprising: a high-voltage NMOS transistor coupled between said high-voltage I/O pad and a low-voltage terminal, said high-voltage NMOS transistor having a parasitic component between a source and a drain thereof; and a trigger coupled to said high-voltage I/O pad and said parasitic component, to monitor the voltage on said high-voltage I/O pad in order to trigger said parasitic component when the voltage on said high-voltage I/O pad raises above a threshold value during an ESD event, so as to release an ESD current therethrough from said high-voltage I/O pad to said low-voltage terminal; wherein said trigger comprises: two diodes face-to-face coupled by a node between a voltage input and said high-voltage I/O pad; a first transistor coupled between said node and said parasitic component; and a second transistor between said parasitic component and said low-voltage terminal; wherein said first and second transistors are switched by a voltage, so as to couple said high-voltage I/O pad or said low-voltage terminal to said parasitic component.