Patent ID: 8085068

Claim:
A frequency divider circuit, comprising: a) a dynamic section configured to receive an input signal having a first frequency, and to output an intermediate signal having a second frequency lower than the first frequency, wherein the dynamic section comprises a plurality of dynamic frequency divider stages, a first dynamic frequency divider stage receiving the input signal having the first frequency, a last dynamic frequency divider stage providing the intermediate signal having the second frequency, each dynamic frequency divider stage comprises a plurality of thin film transistors and a loop of 2p+1 segments, where p is an integer greater than or equal to 1, and each dynamic frequency divider stage after the first dynamic frequency divider stage, if present, receiving as an input an output from a preceding dynamic frequency divider stage; and b) a static section configured to receive the intermediate signal, and to output a signal having a third frequency lower than the second frequency, wherein the dynamic and static sections comprise a plurality of thin film transistors.