Patent ID: 8773174

Claim:
A rail to rail differential buffer input stage, comprising: a high voltage power supply rail and a low voltage power supply rail, a pair of input terminals and a plurality of output paths; n-type and p-type input differential pairs of transistors for receiving a differential input signal from said pair of input terminals and supplying respective differential output current signals on the plurality of output paths when activated, and connected in voltage follower configuration to said low voltage power supply rail and to said high voltage power supply rail respectively; a reference voltage generator including a reference differential pair of transistors for receiving the differential input signal from said pair of input terminals and generating a dynamic reference voltage that is greater or less than a common mode voltage of the differential input signal when said common mode voltage is respectively less or greater than an intermediate value, wherein the intermediate value is a voltage value of said common mode voltage that makes the n-type and p-type input differential pairs of transistors conduct; and n-type and p-type dummy pairs of transistors having current conducting paths connected in parallel with current conducting paths of said n-type and p-type input differential pairs of transistors respectively, said dummy pairs of transistors being controlled by said dynamic reference voltage; wherein said n-type or said p-type dummy pair of transistors conducts to divert supply rail current away from and deactivate the associated transistors of respective n-type or p-type input differential pairs when said common mode voltage of said input signal is further from said dynamic reference voltage than a threshold value, both said dummy pairs conducting and both said input differential pairs being activated when said common mode voltage of said input signal is closer to said dynamic reference voltage than said threshold value.