Patent ID: 7504872

Claim:
A pin-programmable delay cell, comprising: an input channel through which an input signal is transmitted; a first control input channel through which a first control signal is transmitted for controlling a first transmission gate; a second control input channel through which a second control signal is transmitted for controlling a second transmission gate and a third transmission gate, wherein, when the first transmission gate and the second transmission gate are closed and the third transmission gate is opened, the input signal is transmitted through the first transmission gate and the second transmission gate in parallel; a first set of delay elements disposed between the input channel and the third transmission gate, wherein each delay element may be reconfigured with a single interconnect layer change; a second set of delay elements, wherein: each delay element may be reconfigured with a single interconnect layer change, the first transmission gate, the second transmission gate and the third transmission gate are disposed between the first set of delay elements and the second set of delay elements, the input channel is coupled to an input of the first transmission gate and to an input of the second transmission gate, and an output of the first transmission gate and an output of the second transmission gate are coupled to the second set of delay elements; and a first output channel through which a first output signal is transmitted.