Patent ID: 7839714

Claim:
A non-volatile semiconductor storage device, comprising: a memory array including memory cells; a plurality of word lines installed in the memory array, for controlling gates of said memory cells; a sub-decoder including a pull-up power line, a pull-down power line, and a plurality of drivers, said drivers permitting said sub-decoder to selectively drive word lines in accordance with a pre-decode signal and a main decode signal; a pre-decoder, coupled to the sub-decoder, and generating said pre-decode signal in accordance with a first group of address bits; and a main decoder, coupled to the sub-decoder, and generating said main decode signal in accordance with a second group of address bits, a potential of the pull-up power line and a potential of the pull-down power line being controlled in response to the main decode signal, wherein the pre-decoder provides a first voltage as the pre-decode signal when the first group of address bits is selected and a second voltage as the pre-decode signal when the first group of address bits is unselected, said first voltage and said second voltage being predetermined so that word lines are positively provided a voltage regardless of whether a word line is selected or unselected, wherein one of said first voltage and said second voltage comprises a negative potential lower than a ground potential.