Patent ID: 7202535

Claim:
A manufacturing method for an integrated semiconductor structure comprising the steps of: (a) providing a semiconductor substrate having an upper surface and having first and second transistor regions; wherein said first transistor region is a n-MOSFET region and second transistor region is a p-MOSFET region; and (b) forming a gate structure on said first and second transistor region including at least one gate dielectric layer and one gate layer in each of said first and second transistor regions; wherein said gate layer in said second transistor region is made of negatively doped polysilicon; wherein said at least one gate dielectric layer in said first transistor region comprises a first dielectric layer; wherein said at least one gate dielectric layer in said second transistor region comprises an interfacial dielectric layer located adjacent to said gate layer in said second transistor region, which interfacial dielectric layer forms an Al 2 O 3 containing interface on said gate layer in said second transistor region causing a Fermi-pinning effect; and wherein said first transistor region does not include said interfacial dielectric layer.