Patent ID: 7479694

Claim:
Circuitry comprising: a first integrated circuit having first active devices; a second integrated circuit having second active devices, a plurality of metal interconnect layers, and at least one elastic dielectric layer at least in part between two of the plurality of metal interconnect layers, wherein at least one of the plurality of metal interconnect layers interconnects a plurality of the second active devices underneath the at least one elastic dielectric layer; and a plurality of bonds formed between the first integrated circuit and second integrated circuit wherein the bonds provide a primary means of adhesion between the first integrated circuit and the second integrated circuit, wherein the at least one elastic dielectric layer is substantially flexible, and wherein the at least one elastic dielectric layer has a stress of at least one of less than about 8×10 8 dynes/cm 2 and 2 to 100 times less than the fracture strength of the at least one elastic dielectric layer.