Patent ID: 8653609

Claim:
An integrated circuit structure comprising: a substrate; insulation regions over the substrate; and a fin field-effect transistor (FinFET) comprising: a plurality of fins over the substrate, wherein each of the plurality of fins comprises a first fin portion and a second fin portion; a gate stack on a top surface and sidewalls of the first fin portion of each of the plurality of fins; an epitaxial semiconductor layer comprising a portion directly over the second fin portion of each of the plurality of fins, and sidewall portions directly over the insulation regions; a silicide layer on, and having an interface with, the epitaxial layer, wherein a peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of peripherals of the plurality of fins is greater than 1; and a dummy fin, wherein the epitaxial semiconductor layer extends on a top surface and sidewalls of the dummy fin, and wherein the effective silicide peripheral does not comprise any sidewall portion on outer sides of the dummy fin.