Patent ID: 8234543

Claim:
A microprocessor, comprising: control hardware, configured to receive and store control values and to provide the control values to circuits of the microprocessor for controlling operation of the microprocessor; a first plurality of fuses, selectively blown collectively with a predetermined value; and a second plurality of fuses, selectively blown collectively with an error correction value computed from the predetermined value collectively blown into the first plurality of fuses; wherein, in response to being reset, the microprocessor is configured to: read the first and second plurality of fuses; detect an error in the value read from the first plurality of fuses using the value read from the second plurality of fuses; correct the value read from the first plurality of fuses back to the predetermined value using the value read from the second plurality of fuses; and use the corrected predetermined value to write the control values into the control hardware; wherein at least a portion of the circuits of the microprocessor include a clock generation circuit, wherein at least a portion of the control values provided by the control hardware controls a frequency of a clock signal within the microprocessor generated by the clock generation circuit.