Patent ID: 6920078

Claim:
A row decoder of a CMOS image sensor, the row decoder addressing to a plurality of pixels arranged in rows and columns in a CMOS image sensor, the row decoder including a plurality of unit arrays, wherein a unit array comprises: a first NAND gate for generating a reset gate signal in response to an address signal and a reset signal; a second NAND gate for generating a selection gate signal in response to the address signal and a selection signal; a first latch for resetting an output thereof in response to an address latch signal and latching the address signal as the output in response to the address latch signal and the address signal; a third NAND gate for receiving the address signal and a transmitted signal; a fourth NAND gate for receiving the output of the latch and a shutter transmitted signal; and an OR gate for receiving the outputs of the third and fourth NAND gates and generating a transmitted gate signal.