Patent ID: 7842542

Claim:
A method of making an embedded semiconductor die package, comprising: providing a temporary carrier with a wafer-form factor; depositing an adhesive layer over the temporary carrier; providing a prefabricated frame carrier having a similar wafer-form factor as the wafer-form factor of the temporary carrier, the prefabricated frame carrier including a plurality of leadframe interconnect structures and corresponding die mounting sites disposed across the wafer-form factor of the prefabricated frame carrier, each leadframe interconnect structure being formed around the corresponding die mounting site; mounting the prefabricated frame carrier to the adhesive layer; disposing semiconductor die within the corresponding die mounting sites; depositing an encapsulant over the semiconductor die; forming a first conductive layer over a first surface of the lead frame interconnect structure and the encapsulant, the first conductive layer and the lead frame interconnect structure being electrically connected to the semiconductor die; forming a first insulating layer over the first conductive layer; removing the temporary carrier; forming a second conductive layer over a second surface of the lead frame interconnect structure and the encapsulant opposite the first surface of the lead frame interconnect structure and the encapsulant, the second conductive layer being electrically connected to the lead frame interconnect structure; forming a second insulating layer over the second conductive layer; and singulating the prefabricated frame carrier to separate the leadframe interconnect structures and semiconductor die.