Patent ID: 7213090

Claim:
A serial data transfer apparatus comprising: a plurality of selectors, the plurality of selectors each having two inputs and an output; and a transfer gate, the transfer gate gating a transfer of data, wherein one inputs of the plurality of selectors are connected to respective bits of a data bus in an order that transfer bits are arranged, and the other inputs thereof are connected to the outputs of the other selectors in the order, the transfer gate is connected to the output of the selector in a final stage of the plurality of selectors, the respective corresponding bit data of the data bus are set in the plurality of selectors when a transmission enable signal is in a negated state, and the plurality of selectors and the transfer gate are connected so as to serially transfer the data when the transmission enable signal is in an asserted state, and the set data is serially transferred in the connecting state by means of a delayed action resulting from an inter-selector delay time, and is not controlled by a clock signal.