Patent ID: 7818528

Claim:
A method of asynchronous clock regeneration, comprising: synchronizing a first write pointer and a second write pointer, including allowing the first write pointer to sample data from the second write pointer for synchronizing the write pointers, the first write pointer being communicatively coupled with the second write pointer, the first write pointer being an offline write pointer of an offline FIFO connected to an offline data path for voltage and temperature compensation, the second write pointer being an online write pointer of an online FIFO connected to an online data path; swapping at least one bit from the first write pointer with at least one bit of the second write pointer when the bits are static; and regenerating a DQS (Data Strobe Signal) clock from a signal received from the swapped write pointers within the system clock domain, including creating a falling edge of the regenerated DQS (Data Strobe Signal) clock and, when burst DQS (Data Strobe Signal) clocking, generates a pulse during asynchronous reset, removing the pulse and holding the regenerated DQS clock in a low state to suppress additional pulses, wherein the sampled data is sampled directly from within a DQS domain.