Patent ID: 7592661

Claim:
A circuit formed in a semiconductor substrate, the circuit including at least one high voltage, drain-extended (DE) n-channel metal-oxide-semiconductor (NMOS) transistor, the DE NMOS transistor comprising: a source and a drain formed in the semiconductor substrate, the source separated from the drain by a channel region; a number of diffused deep n-wells (DNWs), at least one of the number of DNWs forming the drain-extension region for the DE NMOS transistor, the drain extension region surrounding the drain and extending a predetermined distance into the channel region, the drain extension region having a doping concentration lower than the source and the drain to achieve depletion during reverse biasing of the transistor, thereby raising a breakdown voltage thereof; a p-well region substantially surrounding the source and extending in to the channel region, the p-well region including a first p-well section (PW 1 ) with doping concentration lighter than the doping of the source and a second p-well section (Pw 2 ) in between the PW 1 and the source, the PW 2 having doping concentration heavier than the PW 1 doping concentration and having doping concentration lighter than the doping concentration of the source an isolation structure to isolate the drain from the channel region, and wherein the drain extension regions of the DE NMOS transistor extend underneath the isolation structure; and wherein the channel region of the DE-NMOS further comprises a substantially undoped gap between the DNW and a p-well surrounding the source, the gap substantially undoped by doping of the DNW and the p-well.