Patent ID: 7844933

Claim:
A method of optimizing timing of signals within an integrated circuit design using proxy slack values, said method comprising: propagating signals through said integrated circuit design to output timing signals, wherein said timing signals comprise at least one late slack value associated with a longest path through said integrated circuit design and at least one early slack value associated with a shortest path through said integrated circuit design; for early mode timing analysis, setting an early proxy slack value to zero if said late slack value is less than zero, and if said late slack value is not less than zero, restricting said early proxy slack value to a maximum of the early slack value and the negative of the late slack value; for late mode timing analysis, setting a late proxy slack value to zero, if said early slack value is less than zero, and if said early proxy slack value is not less than zero, restricting said late proxy slack value to a maximum of the late slack value and the negative of the early slack value; performing timing optimization with said early proxy slack value and said late proxy slack value to produce optimized timing values; and outputting said optimized timing values for said integrated circuit design.