Patent ID: 7103748

Claim:
A method for improving memory management in a computer system having a processing logic and a first and second memory, the method comprising the steps of: storing address translation information between virtual addresses and real addresses in the first memory; caching at least part of the address translation information in the second memory for faster access from the processing logic, the part of the address translation information including a subset of address translation information, wherein the second memory is more proximal to the processing logic than is the first memory; and preventing the subset of address translation information from being replaced with other address translation information stored in the first memory; wherein the step of preventing the subset of address translation information from being replaced with other address translation information stored in the first memory further comprises the steps of: generating one or more Class IDs for a range register, each Class ID representing a given address range of an effective address; accessing a replacement management table (RMT) using the one or more Class IDs as indices; mapping the one or more Class IDs to one or more sets of the at least part of the address translation information; determining which set of the address translation information is eligible for replacement based on the RMT; and performing a replacement algorithm on only the set of the address translation determined to be eligible for replacement.