Patent ID: 7867899

Claim:
A method for wordline formation in an integrated circuit memory device, comprising: forming a plurality of columns of a polycrystalline silicon for respective number of wordlines; forming respective recesses in the plurality of columns by selectively etching top surfaces of the plurality of columns, wherein the selective etching comprises: depositing an etch stop layer on top of the plurality of columns and depositing a thick oxide layer on top of the etch stop layer; performing a chemical-mechanical planarization process to remove the thick oxide layer; and performing a dry etching process with a high selectivity of a material forming the etch stop layer over another material forming the thick oxide layer; forming core transistor junctions associated with the wordlines; and performing a salicidation process for the plurality of columns of the polycrystalline silicon to form the wordlines with low resistance, wherein the salicidation process reduces the resistance of the wordlines, wherein other regions except the plurality of columns of the polycrystalline silicon are shielded from the salicidation process.