Patent ID: 8312361

Claim:
An arithmetic circuit comprising: a register; a preprocessing circuit that stores in the register an objective numerical value; a solution prediction circuit that predicts a partial solution on the basis of the numerical value every time the numerical value is stored in the register, where the partial solution is a value represented by a part of digits constituting a solution to be obtained from the objective numerical value and prediction is made in descending order of digit significance; an intermediate-value calculation circuit that generates an intermediate value by a predetermined calculation using one or more partial solutions predicted by the solution prediction circuit, appends one or more extended sign bits to the intermediate value by sign extension, and stores the intermediate value to which the one or more extended sign bits are appended in the register; a solution generation circuit that sequentially acquires the one or more partial solutions predicted by the solution prediction circuit, and generates a solution on the basis of the one or more partial solutions; and an error detection circuit that compares a value of a sign bit constituting the intermediate value stored in the register with a value of one of the one or more extended sign bits stored in the register, and detects an error when the value of the sign bit is different from the value of the one of the one or more extended sign bits.