Patent ID: 7444440

Claim:
A method for increasing a processor data communication rate through a serial peripheral interface (SPI) module comprising the steps of: storing a first value from a Central Processing Unit (CPU) using a virtual special function register (VSFR), the VSFR comprising a virtual transmitter register and a virtual receiver register, wherein the first value is stored in memory addresses within a FIFO memory device external to the SPI module, the memory addresses within the FIFO memory device identified by hardware pointers in the SPI module, wherein the first value is written to the memory addresses within the FIFO memory device by the virtual transmitter register, wherein the step of storing the first value further comprises the steps of: writing the first value from the CPU to the VSFR by providing a write signal, a special function register (SFR) address signal, and a data signal from the CPU to the SPI module; sending, to a bus interface from the SPI module, a data register chip select (DRCS) signal, and a CPU transmitter pointer address signal in response to hardware in the SPI module recognizing the SFR address signal as the signal that causes the first value to be stored in the FIFO memory device starting at an address indicated by the CPU transmitter pointer address signal; writing the first value from the bus interface to the FIFO memory device starting at the address indicated by the CPU transmitter pointer address signal; and retrieving the first value and transmitting the first value through the SPI module, wherein the first value is retrieved from the FIFO memory device and transmitted through the SPI module.