Patent ID: 7904869

Claim:
A method of area compaction for integrated circuit layout design comprising: determining physical extent boundaries for each layer of a first circuit building block; establishing a first packing key with respect to the determined physical extent boundaries of each layer of the first circuit building block, wherein the packing key defines an interlocking characteristic for packing compaction with another circuit building block; determining physical extent boundaries for each layer of a second circuit building block; and establishing a second packing key with respect to the determined physical extent boundaries of each layer of the second circuit building block, wherein the second packing key defines an interlocking characteristic for packing compaction with the first circuit building block or another circuit building block; determining packing compatibilities of one or more pairs of circuit building blocks of a library of circuit building blocks, wherein the packing compatibility for a given pair of circuit building blocks is determined according to respective packing keys of each circuit building block of the given pair of circuit building blocks; defining using a computer, a packing optimization variable for the at least one pair of interlocked circuit building blocks of one or more clusters, wherein the packing optimization variable includes (i) a value of unity in response to the at least one pair of interlocked circuit building blocks of a given cluster having a packing compaction of one hundred percent (100%) at the interlocking boundary or (ii) a value less than unity in response to the at least one pair of interlocked circuit building blocks having a packing compaction of less than one hundred percent (100%) at the interlocking boundary; and forming clusters between two or more of the first circuit building block, the second circuit building block, and another circuit building block of the library of circuit building blocks based upon respective packing compatibilities, wherein a cluster includes at least one pair of circuit building blocks interlocked with one another at an interlocking boundary.