Patent ID: 7303645

Claim:
A method for hermetically sealing devices, the method comprising: providing a substrate, the substrate including a plurality of individual chips, each of the chips including a plurality of devices, each of the chips being arranged in a spatial manner as a first array, the array configuration including a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips, the second street regions intersecting the first street regions to form the array configuration; providing a transparent member of a predetermined thickness, the transparent member including a plurality of recessed regions within the predetermined thickness and arranged in a spatial manner as a second array, each of the recessed regions being bordered by a standoff region, each of the recessed regions having a depth defined by a portion of the predetermined thickness, wherein the depth ranges from about 0.1 mm to about 1.0 mm; aligning the transparent member in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips whereupon the standoff region being coupled to each of the plurality of first street regions and being coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions; and hermetically sealing each of the chips within one of the respective recessed regions by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.