Patent ID: 6933209

Claim:
A process for stacking chips comprising: forming insertion pins connected to an insertion-pin frame by necks, the insertion pins having a pitch matching a pitch of pins on a first chip; wherein the insertion pins and the insertion-pin frame are flat and co-planar; applying a first solder paste to a first surface of the insertion pins; aligning the first chip to the insertion-pin frame and placing first pins of the first chip onto the first solder paste on the first surface of the insertion pins; re-flowing the first solder paste by heating the insertion pins and the first pins to generate a first intermediate assembly; applying a second solder paste to a second surface of the insertion pins, the second surface opposite the first surface; aligning a second chip to the insertion-pin frame and placing second pins of the second chip onto the second solder paste on the second surface of the insertion pins; re-flowing the second solder paste by heating the insertion pins and the second pins to generate a second intermediate assembly; and detaching the insertion pins from the insertion-pin frame by breaking the necks between the insertion pins and the insertion-pin frame to form a final assembly of the first chip, the second chip, and the insertion pins, whereby the first chip is stacked with the second chip using the insertion pins that are flat and co-planar.