Patent ID: 7259418

Claim:
A semiconductor device comprising a MISFET including a first gate electrode formed on a first active region which is a first impurity diffusion region of a first conductivity type and surrounded by isolation trenches and a MIS capacitor including a second gate electrode formed on a second active region which is a second impurity diffusion region of a second conductivity type and surrounded by the isolation trenches, wherein the MISFET comprises: a first gate dielectric interposed between the first gate electrode and the first active region; a first sidewall covering the sides of the first gate electrode; a first offset spacer interposed between the first gate electrode and the first sidewall; source and drain regions of a second conductivity type formed in parts of the first active region located to both sides of the first gate electrode; a third impurity diffusion region of a second conductivity type interposed between each of the source and drain regions and a part of the first active region located immediately below the first gate electrode, and containing an impurity at a lower concentration than the source and drain regions; a first silicide layer formed in an upper portion of the first gate electrode; and a second silicide layer formed in each upper portion of the source and drain regions, the MIS capacitor comprises: a second gate dielectric interposed between the second gate electrode and the second active region; a second sidewall covering the sides of the second gate electrode; a second offset spacer interposed between the second gate electrode and the second sidewall; at least one substrate contact region of a second conductivity type provided in a part of the second active region located to at least one side of the second gate electrode; a third silicide layer formed in an upper portion of the second gate electrode; and a fourth suicide layer formed in an upper portion of the substrate contact region, the second sidewall is formed so as to be in contact with on the second active region, said at least one substrate contact region is in contact with the isolation trench located along the gate length, the second active region has no impurity diffusion region substantially equal in impurity concentration to the third impurity diffusion region, and said at least one substrate contact region overlaps with the second offset spacer in a plan view.