Patent ID: 7539954

Claim:
A computer-implemented method for correcting microdevice layout data for processing effects, comprising: receiving, at a computer, at least a portion of a device layout data file that defines features to be created on a wafer; dividing, by the computer, the device layout data into a number of windows that include one or more features or portions thereof; determining, by the computer, an image intensity on a wafer due to the area of the features or portions thereof in each window by: applying a decomposition algorithm to the features or portions thereof included in a window to define a number of primitives representative of the areas occupied by features or portions thereof in the window; for each primitive, accessing a number of area look up tables each storing pre-calculated data for a convolution of a sum of coherent systems (SOCS) kernel and the primitive; and using the data from each of the area look up tables to determine the image intensity due to the area of the features or portions thereof in the window; determining, by the computer, an image intensity on a wafer due to the edges of the features or portions thereof in each window by: applying a decomposition algorithm to the features or portions thereof in each window to define a number of edge segments that are combined to define the edges of the features or portions thereof in the window; for each edge segment accessing a number of edge look up tables storing pre-calculated data for a convolution of a sum of coherent systems (SOCS) kernel and the edge segment; and using the data from each edge look up table to determine the image intensity on the wafer due to the edges of the features or portions thereof in the window.