Patent ID: 6934295

Claim:
A multi-mode scheduler including a N×kM scheduler for adjusting data transmission between N-pieces of input interface sections, where N is a positive integer, and kM-pieces of output interface sections, where said M is a positive integer and said k is an integer not less than two, said multi-mode scheduler comprising: k-pieces of N×M schedulers to be said N×kM scheduler; and (k−1)-pieces of selection circuits for switching allocated output port information input from an outside of said N×kM scheduler and information from one of said N×M schedulers at a front step so as to be input to another one of said N×M schedulers as allocated output port information; wherein an operation of said N×kM scheduler or an operation of said N×M schedulers having k-pieces of priority classes is set freely with switching operation of said (k-1)-pieces of selection circuits.