Patent ID: 8559222

Claim:
A nonvolatile semiconductor memory comprising: a first transistor; a second transistor; memory cell unit including memory cells electrically connected in series between the first transistor and the second transistor; a source line electrically connected to the first transistor; a bit line electrically connected to the second transistor; word lines electrically connected to gates of the memory cells; a sense amplifier including a first node, a third transistor, a fourth transistor and a first capacitor, one end of the third transistor being electrically connected to the bit line, the other end of the third transistor being electrically connected to the first node, one end of the fourth transistor being electrically connected to both the first node and the other end of the third transistor, and one end of the first capacitor being electrically connected to the first node; and a controller configured to perform a verify operation on a condition that a verify voltage is applied to a first word line selected from the word lines and a first voltage is applied to a gate of the fourth transistor, and a second voltage is applied to a gate of the third transistor twice during applying the first voltage to the gate of the fourth transistor, the second voltage being higher than the first voltage.