Patent ID: 7144772

Claim:
A method for fabricating a semiconductor device, comprising: forming an oxidation barrier pattern and a capping layer pattern which are sequentially stacked on a semiconductor substrate; encasing exposed surfaces of the capping layer pattern with a mold insulating layer so that the mold insulating layer extends a distance above the capping layer pattern and between adjacent capping layer patterns, the mold insulating layer material having an etch selectivity with respect to the capping layer pattern material; planarizing the mold insulating layer until a top portion of the capping Layer pattern is exposed; removing the capping layer pattern to form a lower electrode recess exposing substantially an entire top surface of the corresponding underlying oxidation barrier pattern; and forming a lower electrode about inner surfaces of the lower electrode recess, wherein the capping layer pattern is made of a material having an etch selectivity with respect to the oxidation barrier pattern material.