Patent ID: 7903485

Claim:
An electrical system including embedded non-volatile memory configured to emulate NOR-Flash memory using non-Flash-based memory elements and including circuitry configured to reclaim defective memory in the embedded non-volatile memory, comprising: an integrated circuit including a first portion comprised of a semiconductor substrate including circuitry fabricated on a logic plane, and a second portion comprised of a single memory plane in contact with the semiconductor substrate, the second portion is vertically disposed above and is fabricated directly on top of the logic plane; at least one two-terminal cross-point memory array embedded in the single memory plane and including a plurality of first and second conductive array lines that are electrically coupled with at least a portion of the circuitry and a including a plurality of non-volatile two-terminal memory elements operative to store non-volatile data as a plurality of conductivity profiles, each two-terminal memory element is positioned at a cross-point of one of the plurality of first conductive array lines with one of the plurality of second conductive array lines and includes a first terminal electrically coupled with its respective first conductive array line and a second terminal electrically coupled with its respective second conductive array line, each two-terminal memory element including an electrolytic tunnel barrier having a thickness that is less than 50 Å and electrically coupled with the first terminal, the electrolytic tunnel barrier in contact with and electrically in series with a mixed valence conductive oxide having mobile oxygen ions and electrically coupled with the second terminal, the circuitry including a NOR-type Flash memory interface (NOR I/F) electrically coupled with a plurality of signals including control signals, address signals, and data signals for performing data operations on one or more of the plurality of two-terminal memory elements in the at least one two-terminal cross-point memory array, and the circuitry including a memory reclamation circuit configured to operate in a programming mode and a functional mode, wherein the programming mode is operative to receive defective memory location data indicative of address data for one or more defective two-terminal memory elements in the at least one two-terminal cross-point memory array and to write the defective memory location data to a defective memory list positioned in a first group of the at least one two-terminal cross-point memory array, and wherein the functional mode is operative to receive a memory address for a data operation on the at least one two-terminal cross-point memory array and to activate an address error signal if the memory address matches the defective memory location data in the defective memory list and operative to substitute a subset of the two-terminal memory elements positioned in a second group of the at least one two-terminal cross-point memory array for the one or more defective two-terminal memory elements.