Patent ID: 7916760

Claim:
A packet sending apparatus for performing packet sending, the apparatus comprising: a clock frequency deviation correction calculation section to calculate a valid packet sending period and a number of the valid packets included in the valid packet sending period, wherein the valid packets have packet information; and a packet sending section to exercise priority control by determining whether a packet to be sent is a priority packet or a non-priority packet and by sending a priority packet in preference to a non-priority packet, and to perform a packet sending process on a timing of a packet to be corrected other than the valid packets completely included in the valid packet sending period at the time of correcting the clock frequency deviation by inserting a packet gap corresponding to a sending stop period for which packet sending is stopped to prevent loss of packet information, wherein: when a transmission clock frequency of the packet sending apparatus and the packet receiving apparatus is k Hz, clock frequency deviation of the packet sending apparatus is f parts per million, and clock frequency deviation of the packet receiving apparatus is g p.p.m., the clock frequency deviation correction calculation section calculates an interval L clk in which loss of s-bit data occurs due to clock frequency deviation by using L=k/[(f-g)×10 −6 ]; when a number of bits included in one packet is m and a receiving buffer for changing a clock to be used is not located on a receiving side, the clock frequency deviation correction calculation section calculates a quotient of (L-s)/m as the number of the valid packets included in the valid packet sending period; and the packet sending section performs the packet sending process on the timing of the packet to be corrected at the time of correcting the clock frequency deviation by inserting the packet gap corresponding to an s-bit sending stop period.