Patent ID: 7444570

Claim:
An integrated circuit (IC), comprising: input/output (I/O) interface logic which receives an external bus clock signal having a first frequency, which receives and operates according to a pad clock signal, and which is configured to detect a test mode and to internally provide a test signal if said test mode is detected; and a clock circuit, coupled to said I/O interface logic, comprising: a core clock circuit which generates a core clock signal at a second frequency based on said bus clock signal and a first clock ratio value; a pad clock circuit which generates a preliminary clock signal at a third frequency based on said bus clock signal and a second clock ratio value; a test clock circuit which generates a test clock signal at a fourth frequency based on said first frequency, said second clock ratio value and a third clock ratio value in which said fourth frequency is suitable for operating said I/O interface logic during said test mode; and a select circuit which selects, based on said test signal, between said test clock signal and said preliminary clock signal as said pad clock signal.