Patent ID: 7883963

Claim:
A method of making a memory cell comprising two split sub-lithographic charge storage nodes, comprising sequentially performing the acts of: forming first openings in a first poly layer and a charge storage layer on a semiconductor substrate using only a patterned first mask layer as a mask, thereby forming a patterned first poly layer ( 300 ); forming a center oxide layer and a second poly in the first opening; removing the patterned first mask layer; forming spacers adjacent side surfaces of the center oxide layer and on portions of the upper surface of the patterned first poly layer, wherein the surfaces of the spacers which are not adjacent to the side surfaces of the center oxide layer or on portions of the upper surface of the patterned first poly layer, are sloping; and forming two split sub-lithographic first poly gates, two split sub-lithographic charge storage nodes, and bit line openings by removing exposed portions of the patterned first poly layer and at least portion of the exposed portions of the charge storage layer that are not covered with the spacer.