Patent ID: 6907497

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array in which electrically erasable and programmable memory cells are arrayed, each of said memory cells storing therein a first logic state with a threshold voltage lower than or equal to a first value or a second logic state with a threshold voltage higher than or equal to a second value that is higher than said first value; a data hold circuit for holding program data to be programmed into said memory cell array, said data hold circuit also functioning as a sense amplifier circuit for sensing data as read out of said memory cell array; and a controller configured to control a program sequence for said memory cell array, wherein said controller has the control functions of: a program control function for applying, based on said program data loaded into said data hold circuit, a program voltage to a selected memory cell of said memory cell array to let the data shift from said first logic state to said second logic state; a program verify control function for reading the data programmed into said memory cell array and for verifying that the programmed data of said selected memory cell shifted to said second logic state; an erratic program verify control function for reading the data programmed into said memory cell array and for checking that the threshold voltage of a memory cell to be held in said first logic state does not exceed a third value set as an upper limit value of a variation of said first logic state; and an over-program verify control function for reading the data programmed into said memory cell array and for checking that the threshold voltage of said selected memory cell shifted to said second logic state does not exceed a fourth value set as an upper limit thereof.