Patent ID: 8526232

Claim:
A nonvolatile memory device, comprising: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at at a first side of the memory cell array and which is configured to perform a first operation on the memory cells; a second circuit block that is disposed at a second side of the memory cell array and which is configured to perform second operation on the memory cells, wherein the second operation is different from the first operation, and wherein the first side is opposite the second side such that the memory cell array is located between the first and second circuit blocks; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which is configured to compare a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal and to supply the redundancy control signal to the first circuit block and to the second circuit block.