Patent ID: 7749823

Claim:
A method of fabricating a thin film transistor substrate of horizontal electric field type, comprising the steps of: depositing a first conductive layer on a substrate; forming a gate line, a gate electrode connected to the gate line, a lower gate pad electrode, a first common line in parallel to the gate line and a lower common pad electrode connected to the first common line from said first conductive layer; coating a gate insulating film on the gate line, the gate electrode, the lower gate pad electrode, the first common line and the common pad electrode; sequentially depositing a semiconductor layer and a second conductive layer on the gate insulating film; forming a semiconductor pattern from the semiconductor layer so that the semiconductor pattern is formed on a predetermined region of the gate insulating film; forming a data line crossing the gate line and the common line, a source electrode and a lower data pad electrode connected to the data line, a drain electrode opposed to the source electrode and a pixel electrode connected to the drain electrode from the second conductive layer on said semiconductor pattern; forming a second common line in parallel to the data line and a common electrode extending from the second common line to make an horizontal electric field along with the pixel electrode from said second conductive layer on the semiconductor pattern; coating a protective film over the substrate; patterning the protective film and the gate insulating film to provide first to third contact holes for exposing the lower gate pad electrode, the lower common pad electrode and the lower data pad electrode; and patterning a third conductive layer to provide an upper gate pad electrode, an upper common pad electrode and an upper data pad electrode within said first to third contact holes, respectively.