Patent ID: 7502990

Claim:
A method for processing data to be interleaved and stored in N target memories, the method comprising: producing within a current cycle of a clock signal, from N producers clocked by the clock signal, N data including i groups GR i of m i output data to be stored sequentially into i target memories in accordance with interleaving information, with 1≦i≦N and 0≦m i ≦N; and for each group GR i comprising determining a number S i less than or equal to m i and less than or equal to a number M less than N, and selecting S i data among the m i data of the group within the current cycle, storing the S i selected data in a register bank connected to the target memory associated to the group within the current cycle, reading data stored in the register bank, and writing the data into the associated target memory within the current cycle, and delaying during a next cycle of the clock signal the m i -S i producers having respectively produced the m i -S i non-selected data.