Patent ID: 8043922

Claim:
A method of fabricating a semiconductor device, the method comprising: forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region; forming an offset spacer comprising a first material on the gate structures; performing first ion implantation for source/drain region formation using the gate structures and the offset spacer as an ion implantation mask; forming a material layer comprising a second material on the semiconductor substrate and the gate structures; forming a material layer comprising a third material, which has an etch selectivity with respect to the second material, on the material layer comprising the second material; etching-back the material layer comprising the third material using the material layer comprising the second material as an etch stop layer to form a multi-layered spacer comprising the second material and the third material; performing second ion implantation using the gate structures and the multi-layered spacer as an ion implantation mask; and removing the material layer comprising the third material.