Patent ID: 8043895

Claim:
A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising: a) providing first and second microelectronic substrates each including a plurality of microelectronic elements attached together at dicing lanes, each of said plurality of microelectronic elements including a first edge and a second edge remote from said first edge, each of said plurality of microelectronic elements further including contacts and traces extending from said contacts to identical locations proximate said first and second edges; b) stacking and joining said first and second microelectronic substrates in first and second different orientations to form a stacked assembly such that said first edges of said microelectronic elements of said first microelectronic substrate are aligned with said second edges of said microelectronic elements of said second microelectronic substrate; c) exposing said traces at said first and second edges of said microelectronic elements of said first and second microelectronic substrates, respectively; and d) forming first and second leads, said first leads connected to said exposed traces of said microelectronic elements of said first microelectronic substrate, said second leads connected to said exposed traces of said microelectronic elements of said second microelectronic substrate, said second leads being electrically isolated from said first leads.