Patent ID: 7836263

Claim:
A nonvolatile-memory controlling method for continuously accessing a plurality of memory banks structured so as to have each memory bank accessible independently, said nonvolatile-memory controlling method comprising: controlling a chip enable signal for respective ones of said plurality of memory banks in order to provide an enabled state and a disabled state; in a busy cycle of a first memory bank of said plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing said second memory bank into the enabled state while said access information is issued for said second memory bank using the chip enable signal for said second memory bank; bringing said first memory bank while in said busy cycle into the disabled state using the chip enable signal for said first memory bank, while said access information is issued for said second memory bank; in a busy cycle of said second memory bank, issuing access information to said first memory bank; bringing said first memory bank into the enabled state while said access information is issued for said first memory bank using the chip enable signal for said first memory bank; bringing said second memory bank while in said busy cycle into the disabled state using the chip enable signal for said second memory bank, while said access information is issued for said first memory bank, such that said plurality of memory banks are respectively accessed continuously but are respectively disabled during busy cycles to reduce a power consumption of said non-volatile memory.