Patent ID: 7482246

Claim:
A method for fabricating a trench isolation structure in a semiconductor device comprising: forming a mask film pattern on a semiconductor substrate having cell regions and peripheral circuit regions; forming trenches in the semiconductor substrate via an etching process using the mask film pattern as an etching mask, the trenches further defining mesa regions adjacent to the trenches; forming a sidewall oxide film on exposed portions of the semiconductor substrate in the trenches; forming a first liner nitride film overlying the trenches and mesa regions; performing a first preheating process on the semiconductor substrate having the first liner nitride film formed thereon; forming a first oxide film overlying the first liner nitride film and mesa regions; forming a second liner nitride film overlying the first oxide film; performing a second preheating process on the semiconductor substrate having the second liner nitride film formed thereon; forming a second oxide film to fill the trenches and cover the mesa regions; performing a planarization process on the second oxide film so that a surface of the mask film pattern is exposed; and removing the mask film pattern.