Patent ID: 8143693

Claim:
A semiconductor device comprising: a semiconductor chip including an active surface on which pads are disposed; a passivation layer pattern covering the active surface of the semiconductor chip and exposing the pads; a first insulation layer pattern on the passivation layer pattern; a fuse in the semiconductor chip, wherein the first insulation layer pattern defines a fuse cutting opening above the fuse exposing the passivation layer pattern; a second insulation layer pattern on only a portion of the first insulation layer pattern, wherein the second insulation layer pattern fills the fuse cutting opening and exposes a portion of an upper surface of the first insulation layer pattern outside of the fuse cutting opening, and wherein the second insulation layer pattern includes a protruding portion at the fuse cutting opening; and redistribution line patterns electrically connected to the pads and extending across the second insulation layer pattern and the first insulation layer pattern, wherein the redistribution line patterns are on sides of the protruding portion of the second insulation layer pattern.