Patent ID: 7920024

Claim:
An amplifier comprising: a pair of power supply terminals for receiving a supply voltage; an output stage having a pair of n-channel and p-channel output transistors, and a pair of cascode n-channel and p-channel transistors, said n-channel transistors being connected in series and said p-channel transistors being connected in series, and said serially connected n-channel transistors being serially connected to said serially connected p-channel transistors; an output node in said output stage at an interconnection between said n-channel and p-channel output transistors; a first differential amplifier stage and associated first current path stage, both connected across said power supply terminals, for biasing said n-channel output transistor; a second differential amplifier stage and associated second current path stage, both connected across said power supply terminals for biasing said p-channel output transistor; a first dynamic bias circuit coupled across said power supply terminals for biasing said n-channel cascode transistor; and a second dynamic bias circuit coupled across said power supply terminals for biasing said p-channel cascode transistor, wherein said first dynamic bias stage comprises a pair of p-channel transistors having sources and drains connected in parallel and a diode connected n-channel transistor connected in series with said pair of p-channel transistors, a gate connection of said n-channel transistor providing bias to a gate of said output stage n-channel cascode transistor.