Patent ID: 8447904

Claim:
A data processing system comprising: a memory addressable by a range of physical memory addresses; at least one first software domain having a first privilege level and supporting a trusted I/O management entity; a plurality of second software domains each having a privilege level which is below the first privilege level and each having a virtual memory address space; a memory management unit configured to perform virtual address translation of a virtual memory address into a physical memory address; and an input and/or output device supporting a plurality of virtualised interfaces, each virtualised interface being associated with a respective one of the non-privileged software domains, the input and/or output device further comprising an address translation data store maintained up-to-date by the trusted I/O management entity and at least one operation management unit having access to the address translation data store and being configured to perform virtual address translation in one or more of the virtual memory address spaces; wherein, for I/O operations requested by a virtualised interface of the input and/or output device, the input and/or output device is configured to invoke the operation management unit to perform virtual address translation for those I/O operations meeting one or more predefined first criteria and to invoke the memory management unit to perform virtual address translation for those I/O operations which do not meet the one or more predefined first criteria.