Patent ID: 7782696

Claim:
A semiconductor storage device comprising: at least one bit line; a plurality of memory cells connected to said bit line and each supplying a holding potential of the memory cells to the bit line; and a sense amplifier connected to said bit line, for amplifying said holding potential and feeding the amplified holding potential to said bit line; said semiconductor storage device further comprising: a switch provided to said bit line between said memory cells and said sense amplifier and capable of continuously varying a degree of conduction; and a switch control circuit for varying the degree of conduction of said switch in accordance with an access request signal; wherein said switch control circuit causes the holding potential of said memory cells to be transmitted to said sense amplifier via said bit line by increasing said degree of conduction, then decreases said degree of conduction and gradually increases said degree of conduction as time elapses while said sense amplifier amplifies the transmitted holding voltage and feeds the amplified holding voltage to said bit line.