Patent ID: 8692566

Claim:
A test apparatus that tests a device under test, comprising: a plurality of testing sections that sequentially execute commands included in programs supplied respectively thereto so as to output data patterns to be provided to pins of the device under test; and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections, wherein each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more designated testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to the at least two testing sections, the one or more designated testing sections being a different combination of testing sections than the at least two testing sections.