Patent ID: 7687332

Claim:
A method of manufacturing an integrated circuit including a sensitive portion and a noisy portion, the method comprising: forming at least one trench on a substrate at least as deep as a first predefined thickness, wherein the substrate includes: an upper layer of a semiconductive material with the first predefined thickness, wherein the upper layer of semiconductive material is thicker than 50 nm and the sensitive and noisy portions are both provided on the upper layer; and a layer of a dielectric material with a second predefined thickness, wherein the layer of dielectric material is disposed below the upper layer of semiconductive material, and wherein the at least one trench is formed to isolate the sensitive portion from the noisy portion; after said forming the at least one trench, physically separating the substrate into a plurality of chips, wherein one of the plurality of chips includes both the sensitive and noisy portions; and after said physically separating the substrate, electrically interconnecting the sensitive portion to the noisy portion.