Patent ID: 8637359

Claim:
A method of fabricating a field effect transistor device, comprising the steps of: providing a wafer having an active layer on an insulator; defining at least one active area in the active layer by removing portions of the active layer outside of the active area; patterning a plurality of fin hardmasks on the active layer; placing a dummy gate over a central portion of the fin hardmasks, wherein portions of the active layer outside of the dummy gate will serve as source and drain regions of the device; implanting one or more doping agents into the source and drain regions; depositing a dielectric filler layer around the dummy gate; removing the dummy gate to form a trench in the dielectric filler layer, wherein the fin hardmasks are present on the active layer in the trench; using the fin hardmasks to etch a plurality of fins in the active layer within the trench, wherein the fins will serve as a channel region of the device; activating the doping agents implanted into the source and drain regions using rapid thermal annealing; and forming a replacement gate in the trench, wherein the step of activating the doping agents implanted into the source and drain regions is performed before the step of forming the replacement gate in the trench.