Patent ID: 7317244

Claim:
A semiconductor device, comprising: a printed circuit board having a plurality of conductive patterns; at least one semiconductor chip having a main surface at which a circuitry is formed, the semiconductor chip being mounted on the printed circuit board; a plurality of raised electrodes being formed on a periphery of the main surface of the semiconductor chip; metallic plated layers being formed on the electrodes of the semiconductor chip, said metallic plated layers comprising first and second metallic plated layers, wherein the first metallic plated layer is formed on the electrode of the semiconductor chip so as to cover a side surface and a top surface of the electrode, and the second metallic plated layer is formed on the first metallic plated layer so as to cover a side surface and a top surface of the first metallic plated layer, and wherein the first and second metallic plated layer is different from each other in material; and metallic wires which are directly connected to the second metallic plated layer on the respective electrodes, without the use of additional conductive bumps, to electrically connect the conductive patterns with the metallic plated layers on the electrodes respectively.