Patent ID: 7480201

Claim:
A design structure, for a memory chip, the design structure for the memory chip memory chip comprising: a first input configured to receive an address/command word; a first output configured to re-drive an address/command word; circuitry configured to determine from contents of the address/command word if the address/command word is directed to the memory chip; and an array capable of storing data; wherein the memory chip is configured to make a read from or write to the array when the address/command word is determined to be directed to the memory chip; if the address/command word is determined to not be directed to the memory chip, the memory chip is configured to re-drive the address/command word onto the first output; wherein the design structure includes at least one of a netlist which describes circuitry on the memory chip, test data files, characterization data, verification data, or design specifications; and wherein the design structure resides on a tangible storage medium as a data format used for the exchange of layout data of integrated circuits.