Patent ID: 7964418

Claim:
A method of manufacturing a semiconductor layer comprising: i) depositing, during a first period of time, at least one Group IIIA element and at least one Group VIA element on a substrate or on an optional layer that is optionally disposed on the substrate; ii) depositing, during a second period of time, at least one Group IB element and said at least one group VIA element on the substrate or on the optional layer that is optionally disposed on the substrate, wherein at least a portion of said at least one Group IB element combines with said at least one Group VIA element to form a IB 2 VIA composition; iii) monitoring a first deposition state, during said depositing step ii), by making a first plurality of measurements of an indicia of said first deposition state; and iv) terminating or attenuating said depositing step ii) at a first critical control point based on a function of said first plurality of measurements of said indicia of said first deposition state.