Patent ID: 7881132

Claim:
A semiconductor memory device, comprising: a delay locked loop configured to generate a delay control signal corresponding to a detected phase difference between a reference clock signal and a feedback clock signal by detecting the phase difference, and to generate a delay locked loop (DLL) clock signal by delaying the reference clock signal an amount corresponding to the delay control signal, and to delay the feedback clock signal by a DLL delay time by which the DLL clock signal would be delayed by a practical clock/data path; a delay time measurement device configured to measure a first degree of delay between the reference clock signal and the feedback clock signal in response to locking finishing information synchronized with an external clock signal and to output the first degree of delay as a delay measurement value; and an output enable signal generation device configured to delay read command information synchronized with the external clock signal by a second degree of delay between the reference clock signal and the DLL clock signal and generate the read command information as a final output enable signal by synchronizing the read command information with the DLL clock signal in response to both the delay measurement value and Column Address Strobe (CAS) latency information.