Patent ID: 7338895

Claim:
A method of forming a dual damascene interconnect structure, comprising the steps of: (a) forming a multilayer of dielectrics on a surface of a substrate, comprising: a cap layer; a first non-porous low-k dielectric layer; an etch stop or etch smoothing layer; a porous low-k dielectric layer; and a CMP polish stop layer; (b) producing a multilayer of dielectrics having thereon line and via profiles having a bottom portion and sidewalls; (c) applying a second thin, non-porous low-k dielectric layer on said bottom portion and sidewalls of said line and via profiles; (d) selectively removing said thin, non-porous dielectric layer from said bottom portion of said vias and lines; (e) depositing a conductive liner conformally in said line and via profiles so as to cover on said bottom portion and sidewalls of said vias and lines; and (f) depositing a conductive metal in said line and via profiles to produce said interconnect structure; wherein said second thin non-porous low-k dielectric layer has a composition that will covalently bond with said first non-porous low-k dielectric layer and said first porous low-k dielectric layer to produce said dual damascene interconnect structure with enhanced adhesion wherein said second thin non-porous low-k dielectric layer is covalently bound with said first non-porous low-k dielectric layer and said first porous low-k dielectric layer; and wherein said second thin non-porous low-k dielectric layer is selected from the group consisting of: organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, silicon carbides, silicon oxides, and a combination thereof.