Patent ID: 8520796

Claim:
A signal transfer circuit comprising: first to n th switches that are respectively connected to bits of an n-bit (n is a natural number larger than 1) digital signal output from a digital signal generating circuit and controlled by a transfer control circuit; a first memory circuit including first to n th memories that respectively hold bits of the n-bit digital signal input through the first to n th switches and are serially connected to each other; a second memory circuit including (n+1) th to m th (m is a natural number larger than 2) memories that hold a digital signal and are serially connected to each other, an output signal of the n th memory of the first memory circuit being input to the (n+1) th memory of a first stage; and (n+1) th to m th switches that are connected to output signals of the (n+1) th to m th memories of the second memory circuit and controlled by a read control circuit, wherein each of the first memory circuit and the second memory circuit is controlled by the transfer control circuit such that a digital signal held in an i th (i is a natural number which is larger than 1 and equal to or less than n or m) memory is transferred to an (i+1) th memory of a next stage, and the n-bit digital signal output from the digital signal generating circuit is transferred from the first memory circuit to the second memory circuit, and then output through the (n+1) th to m th switches.