Patent ID: 8344984

Claim:
A liquid crystal display, comprising: a liquid crystal display panel including a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of liquid crystal cells, the liquid crystal display panel including a quad type pixel structure in which red, green, blue, and white subpixels constitute one pixel; a logic circuit that sequentially outputs a plurality of polarity control signals, a logic level of each of the polarity control signals being inverted every three horizontal periods, phases of the polarity control signals being different from one another; a data drive circuit that inverts a polarity of a data voltage in response to the polarity control signals received from the logic circuit to supply the data voltage with the inverted polarity to the data lines; and a gate drive circuit that sequentially supplies gate pulses to the gate lines, wherein the logic circuit supplies a first polarity control signal, including a logic level inverted every three horizontal periods, to the data drive circuit during an N-th frame period (where N is a positive integer), supplies a second polarity control signal subsequent to the first polarity control signal, including a logic level inverted every three horizontal periods and including a phase more delayed than a phase of the first polarity control signal by 1 horizontal period, to the data drive circuit during an (N+1)th frame period, including a first inversion polarity control signal subsequent to the second polarity control signal, including a logic level is inverted every three horizontal periods and including a phase is more delayed than a phase of the second polarity control signal by 2 horizontal periods, to the data drive circuit during an (N+2)th frame period, and supplies a second inversion polarity control signal subsequent to the first inversion polarity control signal, including a logic level is inverted every three horizontal periods and including a phase is more delayed than a phase of the first inversion polarity control signal by 1 horizontal period, to the data drive circuit during an (N+3)th frame period.