Patent ID: 8314502

Claim:
A semiconductor device comprising: an alignment mark formation region; and an integrated circuit formation region; the semiconductor device including: (a) a semiconductor substrate; (b) a first wiring layer formed over the semiconductor substrate, the first wiring layer formed in the integrated circuit formation region; (c) a plurality of first patterns formed over the semiconductor substrate and in the same layer as the first wiring layer, the plurality of first patterns being formed in the alignment mark formation region; (d) a first interlayer insulating film formed over the semiconductor substrate to cover the first wiring layer and the plurality of first patterns; (e) a second wiring layer formed over the first interlayer insulating film, the second wiring layer being formed in the integrated circuit formation region; (f) a plurality of second patterns formed over the first interlayer insulating film and in the same layer as the second wiring layer, the plurality of second patterns being formed in the alignment mark formation region; (g) a second interlayer insulating film formed over the semiconductor substrate to cover the second wiring layer and the plurality of second patterns; and (h) an alignment mark formed over the second interlayer insulating film, the alignment mark being formed in the alignment mark formation region, wherein the plurality of second patterns are arranged so as not to overlap the plurality of first patterns in a plan view.