Patent ID: 6960501

Claim:
A method of manufacturing a semiconductor memory device including a memory cell comprised of a single transistor of a first MISFET, and a second MISFET for a peripheral circuit, comprising steps of: (a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with (i) a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode and a control gate electrode of said first MISFET formed on said second gate insulating film, and with (ii) a third gate insulating film of said second MISFET formed on said peripheral circuit forming region and a gate electrode of said second MISFET formed on said third insulating film, wherein said third gate insulating film has thickness greater than that of said first gate insulating film; (b) introducing an impurity into said memory cell forming region for forming a first semiconductor region in said substrate; (c) introducing an impurity into said memory cell forming region for forming a second semiconductor region in said substrate; (d) after said steps (b) and (c), performing a heat treatment to form said first semiconductor region and said second semiconductor region; (e) after said step (d), introducing an impurity into said memory cell forming region for forming a third semiconductor region in said substrate, wherein said first semiconductor region is formed to surround said third semiconductor region, wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region, wherein a junction depth of said third semiconductor region into said substrate is greater than that of a junction depth of said second semiconductor region, and wherein a dose introduced in said step (e) is higher than the dose in step (c); (f) introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region in said substrate, wherein a dose introduced in said step (e) is higher than the dose in said step (f); and (g) after said steps (e) and (f), forming first side wall spacers on both side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both side surfaces of said gate electrode of said second MISFET, wherein said fourth semiconductor region serves as a drain region of said second MISFET, and wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said third semiconductor region by tunneling through said first gate insulating film.