Patent ID: 8183911

Claim:
A circuit, comprising: a cascode MOS transistor having an open drain output configured to be coupled through a first integrated circuit output pad and terminating resistance to a terminating voltage supply and having a source node; a current switching device connected in series with the source node of the cascode MOS transistor; a bias generator circuit configured to generate a bias voltage for application to a gate of the cascode MOS transistor, the bias generator having a first supply voltage input configured to be coupled through a second integrated circuit pad to an integrated circuit voltage supply different from the terminating voltage supply and having a second supply voltage input different from the first supply voltage input coupled to receive a voltage present at the open drain output of the cascode MOS transistor; wherein the voltage at the open drain of the cascode MOS transistor is supplied from the terminating voltage supply; and wherein the bias generator circuit is configured, in the absence of the integrated circuit voltage supply, to derive the bias voltage for application to the gate of the cascode MOS transistor from the voltage present at the open drain output obtained at the second supply voltage input from the terminating voltage supply.