Patent ID: 6917113

Claim:
A solder interconnect structure for electronic package interconnections comprising: at least one electronic circuit chip attached to a top surface of a chip carrier with a first array of solder connections, said first array of solder connections having a first lead free off-eutectic solder composition; a second array of solder connections attached to a bottom surface of said chip carrier, said second array of solder connections having a second lead free off-eutectic solder composition, said second lead free off-eutectic solder composition having a lower liquidus temperature than said first lead free off-eutectic solder composition; an organic interposer having a top surface attached to said second array of solder connections; a third array of solder connections attached to a bottom surface of said organic interposer, said third array of solder connections having a third lead free off-eutectic solder composition, said third lead free off-eutectic solder composition having a lower liquidus temperature than said second lead free off-eutectic solder composition; and a circuit board having a top side attached to said third array of solder connections to create a solder interconnect structure.