Patent ID: 6859862

Claim:
A microprocessor, comprising a control unit and a cache connected with the control unit for storing data to be used by the control unit, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion, the normal cache portion being controlled by a hardware implemented automatic replacement process, and further wherein the locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache portion, an instruction that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, and a direct memory access engine that controls transfer of data between the locked cache portion and the external memory, wherein the direct memory access engine includes first and second special purpose registers, wherein the first special purpose register controls transfer of data from the external memory into the locked cache potion and the second special purpose register controls transfer of data from the locked cache portion to the external memory.