Patent ID: 8237213

Claim:
A memory array, comprising: first and second substantially vertical, adjacent semiconductor structures; a plurality of first and second charge storage structures, wherein the first charge storage structures are each adjacent to the first semiconductor structure, and wherein the second charge storage structures are each adjacent to the second semiconductor structure; a plurality of first and second control gates, wherein the first control gates are each adjacent to a respective one of the first charge storage structures, and wherein the second control gates are each adjacent to a respective one of the second charge storage structures; wherein each memory cell of a first serially-coupled string of memory cells comprises a respective one of the first control gates and a respective one of the first charge storage structures; wherein each memory cell of a second serially-coupled string of memory cells comprises a respective one of the second control gates and a respective one of the second charge storage structures; and wherein no control gates are interposed between the adjacent semiconductor structures.