Patent ID: 8836359

Claim:
A method of evaluating linearity of a capacitive-to-digital converter of a capacitive sensor integrated circuit chip, the method comprising: providing multiple test capacitors; measuring capacitance values of the multiple test capacitors and parasitic capacitance of a first input A and a second input B to the capacitive-to-digital converter; applying the multiple test capacitors in multiple permutations to the first input A and the second input B of the capacitive-to-digital converter, and for each of at least some permutations, determining an error between an expected output of the capacitive-to-digital converter using the capacitance values and an actual measured output of the capacitive-to-digital converter, the error comprising a difference between the expected output and the actual measured output; and determining linearity error for the capacitive-to-digital converter using the determined errors for the at least some permutations of applying the multiple test capacitors to the first input A and the second input B of the capacitive-to-digital converter.