Patent ID: 7983111

Claim:
A memory controller for controlling a memory that operates in synchronization with a clock signal, wherein the memory sequentially outputs data of addresses starting from a target address in synchronization with the clock signal after receiving a read command and the target address, the memory controller comprising a supply control module that performs a supply process for supplying data inside the memory corresponding to a request address to an external device, in response to a read request designating the request address which is transmitted from the external device, wherein the supply process includes a supply process using a sequential mode, and wherein the supply process using the sequential mode includes: a process for acquiring data to be supplied to the external device from the memory in response to read requests by repeatedly stopping and restarting supply of the clock signal without supplying the read command and the target address to the memory, in a case where a plurality of consecutive request addresses are sequentially designated one after another by a plurality of the consecutive read requests; and a process for supplying requested data from among data acquired in response to the plurality of the read requests to the external device.