Patent ID: 7126185

Claim:
A charge trap insulator memory device comprising: a bottom word line; a first insulating layer formed on the bottom word line; a P-type float channel formed on the first insulating layer and kept at a floating state; a second insulating layer formed on the P-type float channel; a charge trap insulator, formed on the second insulating layer, where charges are stored; a third insulating layer formed on the charge trap insulator; a top word line formed on the third insulating layer; and a P-type drain region and a P-type source region formed at both sides of the P-type float channel, wherein data are written in the charge trap insulator by a voltage difference of the top word line and the float channel, and data are read according to different channel resistance induced to the float channel depending on polarity states of charges stored in the charge trap insulator while a positive read voltage is applied to the bottom word line.