Patent ID: 7009884

Claim:
A semiconductor storage device comprising a memory cell array having a plurality of memory elements, and a program verify circuit for controlling application of programming voltages into the plurality of memory elements, wherein each of the memory elements comprises: a gate electrode formed on a semiconductor layer via a gate insulator; a channel region arranged below the gate electrode via the gate insulator; diffusion regions which are arranged on opposite sides of the channel region and which have a conductive type opposite to that of the channel region; and memory function bodies which are formed on opposite sides of the gate electrode and which have a function of retaining electric charge or polarization, and wherein the program verify circuit comprises: a comparator for comparing a current state of each memory element being programmed with a state to which the memory element is to be programmed; and a program load circuit which is connected to the comparator and which stores, for each memory element, a value outputted from the comparator and indicating whether or not the memory element should be further programmed, the program load circuit including a circuit for, once the memory element has initially been verified by the comparator as having been programmed, precluding storing for each memory element a value indicating that the memory element needs to be further programmed.