Patent ID: 6937679

Claim:
A system comprising: an interconnect; a transmitting chip including a transmitter to produce a spread spectrum data signal to the interconnect in response to a spread spectrum clocking transmitting clock signal; and a receiving chip coupled to the transmitting chip through the interconnect, the receiving chip including: clock recovery circuitry to receive the spread spectrum data signal and a reference clock signal and in response thereto to produce an in phase clock signal which is in phase with the spread spectrum data signal and mirrors frequency changes in the spread spectrum data signal, wherein the spread spectrum data signal has embedded clock information and a varying frequency; and a receiving gate to receive the spread spectrum data signal and the in phase clock signal and to gate the spread spectrum data signal to produce a gated data signal in response to the in phase clock signal; and wherein the clock recovery circuitry includes mirroring circuitry to receive the spread spectrum data signal and the reference clock signal and in response thereto to produce a frequency mirrored clock signal that mirrors frequency changes in the spread spectrum data signal, a phase detector to receive the spread spectrum data signal and in response thereto to produce a phase information signal, and a phase interpolator to receive the phase information signal and the frequency mirrored clock signal and in response thereto to produce the in phase clock signal.