Patent ID: 7516436

Claim:
A method for manufacturing power slits in a power bus located on a chip, comprising: (a) receiving a computer program product that defines locations for the power slits in the power bus, the computer program product comprising a computer usable medium having computer readable program code embodied in the computer usable medium for causing an application program to execute on an operating system of a computer, the computer readable program code comprising, a computer readable first program code to locate the power bus in a defined region of the chip, a computer readable second program code to determine a first number of power slits to be generated in a horizontal direction of the power bus, a computer readable third program code to determine a second number of power slits to be generated in a vertical direction of the power bus, and a computer readable fourth program code to define the power slits in the horizontal and vertical directions of the power bus according to the first and second numbers of power slits calculated by the computer readable second and third program codes, respectively; and (b) forming the power slits in the power bus in accordance with the locations defined by the received computer program product.