Patent ID: 7781822

Claim:
A nonvolatile semiconductor memory comprising: a cell array region configured to include a memory cell transistor that comprises first source and drain regions, a gate insulating film on a semiconductor region between the first source and drain regions, a first floating gate electrode on the gate insulating film, and a first control gate electrode stacked on the first floating gate electrode via a first inter-gate insulating film; a low voltage circuit region configured to include a low voltage transistor that comprises a first element isolating region, second source and drain regions, which contact with the first element isolating region, a low voltage gate insulating film on a semiconductor region between the second source and drain regions, a second floating gate electrode on the low voltage gate insulating film, a second inter-gate insulating film, provided with an opening, on the second floating gate electrode, a second control gate electrode on the second inter-gate insulating film, a first metallic salicide film on the second control gate electrode, and a first gate contact electrically in contact with the metallic salicide film; and a high voltage circuit region configured to include a high voltage transistor that comprises a second element isolating region, third source and drain regions, which contact with the second element isolating region, a high voltage gate insulating film on a semiconductor region between the third source and drain regions, a third floating gate electrode on the high voltage gate insulating film, a third inter-gate insulating film, provided with an opening, on the third floating gate electrode, a third control gate electrode on the third inter-gate insulating film, a second metallic salicide film on the third control gate electrode, and a second gate contact electrically in contact with the second metallic salicide film, wherein the first metallic salicide film is formed only directly beneath the gate contact, and the second metallic salicide film is formed only directly beneath the second gate contact.