Patent ID: 7328229

Claim:
A programmable divide-by clock generator comprising: a writeable register storing a divide-by factor; a divide factor register having a data input connected to said writeable register and an enable input receiving a load divide factor signal for storing said divide-by factor stored in said writeable register upon receipt of a load divide factor signal; a counter receiving and counting an input clock a number of cycles corresponding to said divide-by factor stored in said divide factor register thereby generating a divided clock signal; a first synchronizer having an input receiving a load divide register signal upon writing to said writeable register and a clock input receiving said input clock for delaying said load divide register signal to synchronize with said input clock at an output; an OR gate having a first input connected to said output of said first synchronizer, a second input and an output; a flip-flop having a data input connected to said output of said OR gate, a clock input receiving said input clock and an output, said flip-flop storing and outputting a signal received at said data input upon each receipt of a clock signal at said clock input; a first AND gate having a first input connected to said output of said flip-flop, a second inverting input and an output connected to said second input of said OR gate; a second synchronizer having an input connected to said output of said flip-flop and a clock input receiving said divided clock signal for delaying said output of said flip-flop to synchronize with an inverse of said divided clock signal at an output, said output connected to said second inverting input of said first AND gate; a second AND gate having a first input connected to said output of said flip-flop, a second input connected to said output of said second synchronizer and an output connected to said load enable input of said divide factor register generating said load divide factor signal; and a third AND gate having a first input receiving said divided clock signal of said counter, a second inverting input connected to said output of said second synchronizer and an output generating a divided clock output signal, said divided clock output signal corresponding to said input clock divided by said divide-by factor.