Patent ID: 7516307

Claim:
A processor comprising: a decode unit to decode a plurality of packed data instructions including a packed sum of absolute differences (PSAD) instruction having a first format to identify a first set of packed data, and a packed multiply-add (PMAD) instruction having a second format to identify a second set of packed data, said decode unit to initiate a first set of operations on the first set of packed data responsive to decoding the PSAD instruction and to initiate a second set of operations on the second set of parked data responsive to decoding the PMAD instruction, said second set of operations including at least multiplying corresponding packed data elements of the second set of packed data to produce products and summing said products by pairs; and an execution unit to perform a first operation of the first set of operations initiated by the decode unit and to perform a second operation of the second set of operations initiated by the decode unit.