Patent ID: 8593179

Claim:
A delay circuit of a semiconductor integrated device comprising: a plurality of inverters connected in cascade, each said inverter including: a pair of first FETs that each have a channel of a first conductivity type, a drain of one of the first FETs and a source of the other being connected to each other at a first connection node, gates of both the first FETs being connected to each other at an input node, a first potential being always applied to a source of the one of the first FETs as long as the semiconductor integrated device is in operation, and a drain of the other being connected to an output node; a pair of second FETs that each have a channel of a second conductivity type, a drain of one of the second FETs and a source of the other being connected to each other at a second connection node, gates of both the second FETs being connected to each other at the input node, a second potential being always applied to a source of the one of the second FETs as long as the semiconductor integrated device is in operation, and a drain of the other being connected to the output node; a first additional FET that applies the second potential to the first connection node when a potential at the output node becomes the second potential; a second additional FET that always supplies the second potential to the first additional FET as long as the semiconductor integrated device is in operation; a third additional FET whose source receives the first potential and whose drain is connected to a gate of the second additional FET; a fourth additional FET whose source receives the second potential and whose gate and drain are both connected to a gate of the third additional FET; a fifth additional FET that applies the first potential to the second connection node when a potential at the output node becomes the first potential; a sixth additional FET that always supplies the first potential to the fifth additional FET as long as the semiconductor integrated device is in operation; a seventh additional FET whose source receives the second potential and whose drain is connected to a gate of the sixth additional FET; and an eighth additional FET whose source receives the first potential and whose gate and drain are both connected to a gate of the seventh additional FET.