Patent ID: 7064598

Claim:
A buffer comprising: a capacitor having a first terminal for receiving an input signal, and a second terminal; a first transistor having a first current electrode coupled to a first power supply voltage terminal for receiving a first power supply voltage, a control electrode coupled to said second terminal of said capacitor, and a second current electrode for providing an output signal of the buffer; a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode coupled to said second terminal of said capacitor, and a second current electrode coupled to a second power supply voltage terminal for receiving a second power supply voltage; wherein said input signal has a peak-to-peak voltage swing equal to a first voltage; wherein a voltage difference between said first power supply voltage and said second power supply voltage is equal to a second voltage that is lower than said first voltage; and wherein a capacitance of said capacitor is chosen such that a peak-to-peak voltage swing at said control electrodes of said first and second transistors is less than or equal to said second voltage, and wherein the capacitance of said capacitor is greater than a combined parasitic capacitance of the first transistor and the second transistor.