Patent ID: 8525167

Claim:
A laminated chip package in which a plurality of semiconductor plates are laminated, each of the semiconductor plates having a semiconductor device and a wiring electrode connected to the semiconductor device, wherein an inner electrode for examination is provided, the inner electrode for examination having two end faces, an end face of the inner electrode for examination is formed on at least one side surface for wiring of a plurality of side surfaces of the plurality of semiconductor plates, the inner electrode for examination is formed inside of the at least one side surface for wiring, the inner electrode for examination has a turn structure, the two end faces of the inner electrode are both formed on and are both on a same plane with the same at least one side surface for wiring, and an outer electrode for examination is provided, which is configured to connect the end faces of the inner electrode for examination along a lamination direction of the plurality of semiconductor plates, only for two adjacent semiconductor plates of the plurality of semiconductor plates.