Patent ID: 7962813

Claim:
An integrated circuit comprising: A. a test clock input lead; B. a test data in input lead; C. a test data out output lead; D. a test mode select input lead; and E. TAP linking module circuitry having a test data input coupled with the test data in input lead, a test data out output coupled with the test data output lead, a test clock input connected to the test clock input lead, and a test mode select input connected to the test mode select input lead, the module circuitry including: i. instruction register circuitry having an input coupled with the test data in input lead, a test data output, a control input, and link control outputs; ii. module multiplexer circuitry having one input coupled with the test data in input lead, another input coupled with the test data output of the instruction register circuitry, a test data output coupled with the test data out output lead, and a control input; iii. TAP control circuitry having inputs coupled with the test clock input lead and the test mode select lead, and control outputs connected with the control input of the instruction register circuitry and the control input of the module multiplexer circuitry; iv. gating circuitry having one input coupled with the test mode select input lead, enable inputs connected with the link control outputs of the instruction register, and one gated test mode select output for each enable input; v. input multiplexing circuitry having one input coupled with the test data in input lead, select inputs connected with the link control outputs of the instruction register, and one selected test data out output for each select input; and vi. output multiplexing circuitry having test data out inputs, a select input connected with the link control outputs of the instruction register, and a test data output coupled with the test data out output.