Patent ID: 7809085

Claim:
A data recovery system for processing a high speed differential data signal and a clock signal into a digital signal, comprising: analog front end (AFE) circuitry having adjustable parameters for processing the differential data signal into a preprocessed data signal having reduced distortion; an oversampling circuit providing a digital representation of the preprocessed data signal; a training function circuit for estimating a quality of the digital representation of the preprocessed data signal, and adjusting the parameters of the AFE circuitry to improve the quality of the digital representation of the preprocessed data signal; and a bit extractor circuit for generating the digital signal from the digital representation of the preprocessed data signal; wherein the training function circuit further comprises: a digital circuit for estimating the quality of the preprocessed data signal and generating a Quality Number indicating said quality; an evaluation run control circuit for adjusting the parameters of AFE circuitry to a number of predetermined settings, and for monitoring a predetermined large number of the oversampled bits for each setting; a memory for retaining the best setting corresponding to the highest Quality Number; and a means for updating the parameters of the AFE circuitry to the best setting.