Patent ID: 7781285

Claim:
A method of fabricating a semiconductor device comprising: preparing a semiconductor substrate comprising a cell region and a peripheral circuit region; forming island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction on the substrate of the cell region, each of the vertical gate structures comprising a semiconductor pillar having a concave portion formed in a sidewall of the semiconductor pillar and a cell gate electrode surrounding a center portion of the semiconductor pillar in the concave portion of the semiconductor pillar; simultaneously forming a bit line separation trench inside the semiconductor substrate below a gap region between the vertical gate structures and a peripheral circuit trench confining a peripheral circuit active region inside the semiconductor substrate of the peripheral circuit region, in which the bit line separation trench is formed in parallel with the column direction of the vertical gate structures; forming a bit line separation insulating layer and a peripheral circuit isolation layer inside the bit line separation trench and the peripheral circuit trench, respectively; and forming a word line on the bit line separation insulating layer along the row direction of the vertical gate structures, the word line being formed to contact a portion of a sidewall of the cell gate electrode and expose a remaining portion of the sidewall of the cell gate electrode in the column direction of the vertical gate structures and to electrically connect two neighboring vertical gate structures.