Patent ID: 7183149

Claim:
A method of manufacturing a field effect transistor, comprising steps of: (a) forming an ohmic metal layer on a substrate in source and drain regions; (b) sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein the insulating layer is exposed in the first region, and a lowermost resist pattern is exposed in the second region; (c) exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; (d) performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and (e) forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns.