Patent ID: 7060540

Claim:
A method of fabricating a thin film transistor array on a substrate having at least one designated display region, the method comprising the steps of: forming a first patterned conductive layer over the substrate, wherein the first patterned conductive layer distributes over an area range that exceeds the designated display region; forming a first dielectric layer over the substrate such that a portion of the first patterned conductive layer outside the designated display region is exposed; forming a second patterned conductive layer over the first dielectric layer, wherein the second patterned conductive layer and the portion of the first patterned conductive layer exposed by the first dielectric layer are electrically connected; forming a second dielectric layer over the substrate, wherein the second dielectric layer has a plurality of contact openings; forming a plurality of pixel electrode over the second dielectric layer such that the pixel electrode and the second patterned conductive layer are electrically connected through the contact openings; and removing the second dielectric layer, the second patterned conductive layer, the first dielectric layer and the first patterned conductive layer outside the designated display region.