Patent ID: 7109547

Claim:
A non-volatile semiconductor memory device, comprising: a semiconductor substrate including a memory cell region and a peripheral region, the memory cell region including a plurality of first element regions and a plurality of first element separate regions which insulate between the first element regions, each first element separate region extending toward a first direction, the peripheral region including a second element region and a second element separate region which insulates the second element region; a plurality of control gates, each control gate being formed over the first element region and the first element separate region and extending toward a second direction crossing to the first direction; a plurality of charge storage portions, each charge storage portion being formed between the control gate and the first element region; a first insulating film formed between the semiconductor substrate and the charge storage portions; a second insulating film formed between the charge storage portions and the control gates; a third insulating film formed on the second element region; and a peripheral gate formed on the third insulating film, the peripheral gate including a first electrode portion, a second electrode portion and a fourth insulating film located between the first and the second electrode portions; wherein a first upper surface of the first element separate regions facing to the control gate protrudes from a second upper surface of the semiconductor substrate, a height of the first upper surface is lower than a height of a third upper surface of the charge storage portion, a fourth upper surface of the first element separate regions between the control gates is lower than the height of the first upper surface, and a fifth upper surface of the second element separate region protrudes from the second upper surface and is lower than a height of the fourth insulating film relative to the second upper surface.