Patent ID: 7723833

Claim:
A semiconductor package comprising: a substrate having a top surface, a bottom surface and a cavity through the top and bottom surfaces of the substrate, the top surface comprising a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions, wherein a bottom of the at least one gap is defined by the top surface of the substrate; a first semiconductor chip having an active surface and a non-active surface, the non-active surface of the first semiconductor chip being in contact with the adhesive portions, and the active surface of the first semiconductor chip being electrically connected to the substrate; a second semiconductor chip having an active surface and a non-active surface, the non-active surface of the second semiconductor chip being attached to the non-active surface of the first semiconductor chip by a layer of adhesive therebetween, and the active surface of the second semiconductor chip being electrically connected to the substrate, wherein the cavity accommodates the second semiconductor chip; and an encapsulant material covering the first and second semiconductor chips, their associated electrical connections, and filling the at least one gap between the adhesive portions between the first semiconductor chip and substrate in one step.