Patent ID: 8377722

Claim:
A method for preparing a structure for atomic force probing of a conductive feature embedded in a dielectric layer, the method comprising: removing an interlayer dielectric and wiring of at least one metallization level of a back-end-of-line wiring structure to expose the dielectric layer and the conductive feature; after the dielectric layer and the conductive feature are exposed, forming an insulator layer on the dielectric layer so as to cover the conductive feature; forming a contact hole in the insulator layer that penetrates from a top surface of the insulator layer through the insulator layer to the conductive feature; at least partially filling the contact hole with a conductive stud that is electrically connected with the conductive feature and exposed at the top surface of the insulator layer so as to define a probe pad; and recessing the top surface of the insulator layer relative to a top surface of the conductive stud with a wet chemical etch or a reactive ion etching process so that the top surface of the conductive stud projects above the top surface of the insulator layer by 5 nanometers or less.