Patent ID: 7650484

Claim:
An array-type computer processor comprising: A) a data path unit, said data path unit including i) a plurality of processor elements arranged in a matrix, said processor elements performing data processes including generation and communication of event data, and ii) a plurality of switch elements, said plurality of switch elements controlling connections between said plurality of processor elements for respective operation states of said data path unit; B) a state control unit for receiving said event data from said processing elements and sequentially transferring i) a cooperative partial instruction code representing a context for each said operation state of said data path unit, and ii) an event data which has been input to said state control unit according to an instruction code to said data path unit for each said operation state according to an instruction code; and C) a code-obtaining means for i) obtaining data of a predetermined number of said instruction codes of a program from an external program memory, respective instruction codes of said instruction codes of said program comprising cooperative partial instruction codes wherein a cooperative partial instruction code of an instruction code represents an operation state and another cooperative partial instruction code of said instruction code represents a context corresponding to said connections between said plurality of processor elements, and ii) transferring said partial instruction codes representing operation states to said data path unit and transferring said partial instruction codes representing contexts to said data-path unit whereby a) said state control unit temporarily holds only a predetermined number of partial instructions representing operation states for operation and b) said data path unit temporarily holds only a predetermined number of said partial instruction codes representing contexts for operation, said code-obtaining means being responsive to said data path unit and said state control unit such that every time said data path unit and said state control unit complete operations with cooperative partial instruction codes respectively held therein, said code-obtaining means obtains data of said respective cooperative partial instruction codes of said instruction codes of subsequent operation states and contexts, respectively.