Patent ID: 7809141

Claim:
A method for ciphering with an integrated processor data to be stored in a memory, the method comprising: combining each data block to be ciphered with a result of a first function of a storage address of the data block in memory and a digital quantity to provide combined data; and applying to the combined data a ciphering algorithm which is a second function of at least one key specific to the integrated processor, to obtain a ciphered data block, the digital quantity being different from the at least one key, wherein: the storage address of the ciphered data block in the memory is an address A that comprises bits A 1 , . . . A n ; the digital quantity different from the at least one key comprises bit vectors R 1 , . . . , R n ; said first function is a function IVGEN that is a linear combination according to the following formula: I ⁢ ⁢ V ⁢ ⁢ G ⁢ ⁢ E ⁢ ⁢ N ⁡ ( A ) = ∑ i = 1 n ⁢ ( A i ⋆ R i ) .