Patent ID: 8344776

Claim:
A memory interface circuit connected to a memory device that outputs a first data signal and has a variable drive capability for driving the first data signal, said memory interface circuit comprising: a first delay unit configured to delay a first strobe signal outputted from the memory device by a first delay amount to generate a first delayed strobe signal; a first data latch unit configured to latch the first data signal as a first latched data signal in synchronization with the first delayed strobe signal; a second data latch unit configured to latch the first data signal as a second latched data signal; a first delay control unit configured to sequentially change a value of the first delay amount; a first range calculating unit configured to calculate a first delay range width that is a width of a range of values of the first delay amount which allow said first data latch unit to correctly latch the first data signal as the first latched data signal; and a drive capability setting unit configured to adjust the drive capability of the memory device so as to widen the first delay range width.