Patent ID: 8656233

Claim:
A scan cell, comprising: first, second, and third data inputs configured to receive respective data in, test data in, and serial in data bits; a control input configured to receive a control signal; latching logic configured to latch data bits received at first and second latch inputs to a scan cell output, said first latch input being configured to receive said data in data bit received from a functional block configured to output a parallel data word including said data in data bit; and selection logic configured to select between said test data in and serial in data bits depending on a state of said control signal, and to provide said selected bit to said second latch input, wherein: an immediately preceding scan cell of a scan chain provides said serial in data bit; and said latching logic comprises a two-phase clocked flip-flop configured to latch said data in data bit to said scan cell output upon operation of a first clock signal, said first clock signal not controlled by said control signal.