Patent ID: 8143926

Claim:
A data signal generating apparatus, comprising: a data output unit ( 11 ) for outputting m-bit parallel data and a data synchronization clock signal synchronized with said m-bit parallel data in response to a data request signal produced by dividing the frequency of a reference clock signal by a plural number “m”; a m:1 multiplexer ( 13 ) for receiving said m-bit parallel data from said data output unit in response to a latch signal produced by dividing said frequency of said reference clock signal by said plural number “m”, and outputting, at a rate of said reference clock signal, a data synchronization serial data produced from said m-bit parallel data; and synchronization means ( 25 ) having a phase comparator ( 16 ) for comparing the phase of said data synchronization clock signal with the phase of said latch signal, said synchronization means being operative to synchronize said m-bit parallel data outputted from the data outputting unit with said latch signal, wherein said synchronization means includes: a control unit ( 26 ) for producing a control signal based on a comparing result obtained by said phase comparator; and a variable delay device ( 30 ) for delaying, on the basis of said control signal, said reference clock signal or a divided clock signal produced by dividing said frequency of said reference clock signal by a number equal to or smaller than said plural number “m”, at least one systematically-expanded data conversion unit having a m:1 multiplexer ( 13 ) and a synchronization means ( 40 ), wherein said data output unit is operative to output said data synchronization clock signal to said synchronization means of said systematically-expanded data conversion unit, and to output said m-bit parallel data synchronized with said data synchronization clock signal to said m: 1 multiplexer of said systematically-expanded data conversion unit, and said synchronization means of said systematically-expanded data conversion unit is operative to synchronize said data synchronization clock signal with said latch signal produced in said m:1 multiplexer.