Patent ID: 7989302

Claim:
A method of fabricating a device structure using a device layer of an SOI substrate, the method comprising: forming a gate structure carried on a top surface of the device layer; applying a first mask with a window that exposes a portion of the top surface adjacent to at least one sidewall of the gate structure; implanting ions of a first conductivity type through the window in the first mask and into the device layer using at least one sidewall of the gate structure as a second mask to define a first doped region adjacent to the gate structure; and implanting ions of a second conductivity type through the window in the first mask and into the device layer to form a p-n junction in the first doped region such that a first segment of the p-n junction is aligned substantially parallel to the top surface of the device layer and a second segment of the p-n junction extends from the first segment toward the top surface of the device layer, wherein the ions of the first conductivity type are implanted at a first incident angle relative to a surface normal of the top surface and the ions of the second conductivity type are implanted at a second incident angle relative to the surface normal of the top surface.