Patent ID: 8896130

Claim:
A multi-chip stack structure, comprising: a chip carrier having a first surface and an opposite second surface; a first chip group comprising a plurality of first chips disposed on the first surface of the chip carrier in a step-like manner, wherein the plurality of first chips are electrically connected to the first surface of the chip carrier through bonding wires, and the bonding wires are free from connecting to the second surface of the chip carrier; a second chip disposed on a topmost one of the plurality of first chips of the first chip group, wherein the second chip is electrically connected to the first surface of the chip carrier through bonding wires, and the bonding wires are free from connecting to the second surface of the chip carrier; an insulative film on the topmost one of the plurality of first chips of the first chip group to cover parts of ends of the bonding wires of the topmost one of the plurality of first chips of the first chip group and at least a part of the second chip; a third chip having a third surface and an opposite fourth surface, and being stacked on the insulative film, wherein the third chip is free from contacting the first chip group and the second chip, the third surface of the third chip contacts the insulative film, the insulative film is free from covering the fourth surface of the third chip, the third chip is electrically connected to the first surface of the chip carrier through bonding wires, and the bonding wires are free from connecting to the second surface of the chip carrier; and an encapsulant formed on the chip carrier to encapsulate the first chip group, the second chip, and the third chip.