Patent ID: 7656416

Claim:
A graphics processing circuit, comprising: a triangle stipple circuit operative to generate polygon stippling data in response to vertex data; a line anti-aliasing circuit, operative to generate anti-aliased line data in response to the vertex data, the line anti-aliasing data generation performed in parallel with the polygon stippling data generation; a line stipple circuit, operative to generate stippled line data in parallel with the polygon stippling data generation and the line anti-aliasing data generation; a point anti-aliasing circuit operative to generate anti-aliased point data in response to the vertex data in parallel with the polygon stippling data generation, the anti-aliased line data generation and the stippled line data generation, one of the polygon stippling data, anti-aliased line data, stippled line data and anti-aliased point data providing a primitive texture coordinate set; a rasterizer operative to generate a pixel texture coordinate set in response to the primitive texture coordinate set, and operative to apply an appearance value to a pixel defined by the pixel texture coordinate set; and a texture circuit, coupled to the rasterizer, operative to retrieve the appearance value from a corresponding one of a plurality of textures in a multi-texture map, the multi-texture map including data representing point, line and polygon texture data.