Patent ID: 7643601

Claim:
A discrimination circuit for a data signal having duty cycle deviation for use in an optical receiver, comprising: a phase locked loop (PLL) circuit containing a phase comparator circuit for performing a phase comparison between a data signal of bit rate B (bits/s) and a clock signal of B/2 (Hz) at intervals of 2/B (sec); a duty cycle evaluation circuit for evaluating a duty cycle between input data before and after a point at which said PLL circuit is locked; and a control circuit for controlling, based on a result of said evaluation, a data discrimination phase before and after the point at which said PLL circuit is locked, wherein: said control circuit includes an initial phase setting circuit in which duty cycle information representing an initial phase adjustment is set; and said initial phase setting circuit compares said duty cycle information representing said initial phase adjustment with an output of said duty cycle evaluation circuit and, when locked in phase in the same condition as said duty cycle information representing said initial phase adjustment, said locked condition is maintained, but when locked in phase in a condition different from said duty cycle information representing said initial phase adjustment, a clock output of a voltage-controlled oscillator in said PLL circuit is inverted.