Patent ID: 7889540

Claim:
A semiconductor device, comprising: a memory cell which includes a first inverter and a second inverter, said first inverter comprising a first drive transistor and a first load transistor, said second inverter including a second drive transistor and a second load transistor, and an input terminal and an output terminal thereof, respectively, connected to an input terminal and an output terminal of the first inverter; a first transmission transistor provided between the output terminal of the first inverter and a line of a first bit line pair; a second transmission transistor provided between the output terminal of the second inverter and an other line of the first bit line pair; a third transmission transistor provided between the output terminal of the first inverter and a line of a second bit line pair; a fourth transmission transistor provided between the output terminal of the second inverter and an other line of the second bit line pair; a first isolation transistor which isolates the second drive transistor and the second transmission transistor; and a second isolation transistor having a gate formed commonly to a gate of the first isolation transistor, the second isolation transistor isolating the first transmission transistor and the second drive transistor, wherein a first active region in which the first transmission transistor, the second transmission transistor, the second drive transistor, and the first isolation transistor are formed, is formed in a continuous region, and wherein the first isolation transistor is provided between the second drive transistor and the second transmission transistor.