Patent ID: 7281152

Claim:
A processor, comprising: a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data per each execution unit, the execution unit being executed by the operational processing part as a unit; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part, the clock frequency determining part including a table indicating the relation between the amounts of the data detected by the data amount detector and the variation of the clock frequency, a clock frequency holder holding a practical current clock frequency supplied to the operational processing part, and an adder adding to the current clock frequency the variation obtained from the table, the clock frequency determining part determining newly the output value of the adder as the clock frequency of the clock signals; an execution status detector detecting whether a certain execution unit becomes the predetermined state or not; a timer newly starting the clocking when the execution status detector detects that the execution unit has become the predetermined state; and a clock frequency changing part changing the clock frequency, the clock frequency changing part decreasing the absolute value of the variation according to the value of the timer, wherein the adder adds to the current clock frequency the variation which is changed by the clock frequency changing part.