Patent ID: 6958272

Claim:
A method of forming at least a portion of a SONOS dual bit memory core array upon a semiconductor substrate, the method comprising: forming a portion of a charge trapping dielectric layer over the substrate; forming a resist over the portion of the charge trapping dielectric layer; patterning the resist to form a plurality of resist features having respective first spacings therebetween; performing a pocket implant through the first spacings and the portion of the charge trapping dielectric layer, the pocket implant performed at an angle relative to the semiconductor substrate so as to establish pocket implants within the substrate that extend at least partially under the resist features; performing a bitline implant through the first spacings and the portion of the charge trapping dielectric layer to establish buried bitlines within the substrate having a width corresponding generally to the first spacing, the bitlines not covering the portions of the pocket implants that extend under the resist features, wherein the bitline implant is performed before the pocket implant; removing the patterned resist; forming the remainder of the charge trapping dielectric layer over the portion of the charge trapping dielectric layer; forming a wordline material over the remainder of the charge trapping dielectric layer; and patterning the wordline material to form wordlines that overlie the bitlines.