Patent ID: 7886256

Claim:
A processor-implemented method for determining a static timing analysis of a logic design, comprising: on at least one processor, executing instructions that cause the processor to perform operations including: inputting physical delay arcs of a plurality of physical elements of an integrated circuit, each physical element including one or more physical components and each physical delay arc of the physical element specifying a propagation delay from an input of the physical element to an output of the physical element; respectively mapping a plurality of logic components of the logic design to selected ones of the physical components of the physical elements; for each of the logic components, determining logic delay arcs from the physical delay arcs of the physical element that includes the physical component to which the logic component is mapped, wherein each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component; performing a static timing analysis of the logic components of the logic design using the logic delay arcs; and outputting a description of the static timing analysis of the logic components of the logic design.