Patent ID: 7725657

Claim:
A method comprising: associating a first priority indicator with first data stored in a first entry of a shared cache memory by a first core of a processor executing a first thread to indicate a priority level of the first thread and updating a first counter indicative of a number of entries in the shared cache memory associated with the first thread; associating a second priority indicator with second data stored in a second entry of the shared cache memory by a graphics engine of the processor executing a second thread to indicate a priority level of the second thread and updating a second counter indicative of a number of entries in the shared cache memory associated with the second thread; allocating the shared cache memory between the first thread and the second thread using a gradient partition algorithm in which weighted hit rate derivatives as a function of cache allocation by the first thread and the second thread are substantially equal; and dynamically allocating additional space in the shared cache memory to the first thread, wherein the first and second threads are of an equal priority level, and the first thread is accessing the shared cache memory more than the second thread.