Patent ID: 7038898

Claim:
An ESD protection circuit comprising: a first MOS transistor having: a first semiconductor region of a first conductivity type, the first semiconductor region being connected to a supply voltage; a first terminal region of a second conductivity type formed in the first semiconductor region; a spaced-apart second terminal region of the second conductivity type formed in the first semiconductor region; a first channel region of the first semiconductor region formed between the first and second terminal regions; a first gate oxide region formed on the first semiconductor region over the first channel region; and a first gate formed on the first gate oxide region over the first channel region, the first gate being connected to the first terminal region; and a second MOS transistor having: a second semiconductor region of the first conductivity type, the second semiconductor region being connected to the supply voltage; a third terminal region of a second conductivity type formed in the second semiconductor region; a spaced-apart fourth terminal region of the second conductivity type formed in the second semiconductor region, the fourth terminal region being electrically connected to the first terminal region; a second channel region of the second semiconductor region formed between the third and fourth terminal regions; a second gate oxide region formed on the second semiconductor region over the second channel region; and a second gate formed on the second gate oxide region over the second channel region, the second gate being connected to the third terminal region.