Patent ID: 7519889

Claim:
A method to reduce logic built in self test (LBIST) manufacturing test time of integrated circuits, the method comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array locally disposed on an integrated circuit, each of the plurality of test seeds is associated with a set of LBIST control information, the set of LBIST control information for each of the plurality of test seeds is loaded into the locally accessible on-chip memory array, wherein the loading is provided at a same input; sending the plurality of test seeds from the locally accessible on-chip memory array repetitively into a pseudo-random pattern generator one at a time during an LBIST operation being under the control from the set of LBIST control information; generating random bit streams serially into a plurality of parallel shift registers of the integrated circuit through the use of the plurality of test seeds; and performing a logic built-in self test on a plurality of logic blocks in the integrated circuit to detect defects within the integrated circuit.