Patent ID: 7707393

Claim:
A computer system comprising: a first execution channel comprising: a first load/store unit, including a shared load/store memory configured to store instant and subsidiary data values associated with scatter and gather operations and directly coupled to a data cache by an address bus and a data bus; and a first execution unit coupled to the first load/store unit via a common register file having a plurality of registers; and a second execution channel comprising: a second load/store unit including the shared load/store memory; and a second execution unit coupled to the second load/store unit via the common register file; and a decode unit configured to decode a dualled scatter instruction or a dualled gather instruction, forward a first portion of the dualled scatter instruction to the first execution channel and a second portion of the dualled scatter instruction to the second execution channel, and forward a first portion of the dualled gather instruction to the first execution channel and a second portion of the dualled gather instruction to the second execution channel.