Patent ID: 8078804

Claim:
A method for managing a data cache memory associated with a processor comprising a plurality of processor clusters that operate simultaneously on scalar and vectorial data, the plurality of processor clusters comprising a low cluster and a high cluster coupled to the data cache memory via an intercluster data path, with the low cluster being selectably activated to only operate on the scalar data and with both the low and high clusters being selectably activated to operate on the vectorial data, the method comprising: providing in the data cache memory data locations for storing therein data for processing by the plurality of processor clusters; and accessing the data locations in the data cache memory via the intercluster data path either in a scalar mode or in a vectorial mode, each processor cluster comprising a plurality of processing elements, with the plurality of processing elements in each processor cluster being symmetrical with the plurality of processing elements in other processor clusters so that activating the low cluster only supports the scalar mode and activating both the the low cluster along with the high cluster supports the vectorial mode, with the accessing based on the following if accessing the data locations is in the scalar mode, then an address to be accessed is computed by the processor cluster that needs the data, and if accessing the data locations is in the vectorial mode, then the address to be accessed is computed by one of the processor clusters and is identical for all of them.