Patent ID: 8901746

Claim:
A semiconductor memory device comprising: a substrate; a plurality of parallel first conducive lines on the substrate, wherein the plurality of parallel first conductive lines extends in a first direction on a memory cell region and on a contact region of the substrate; and a plurality of parallel second conductive lines on the contact region of the substrate, wherein each of the plurality of parallel second conductive lines extends in a second direction different than the first direction, wherein each of the second conductive lines is connected to a respective one of the first conductive lines, wherein a first one of the second conductive lines is between a second one of the second conductive lines and the memory cell region, wherein the second one of the second conductive lines is between a third one of the second conductive lines and the first one of the second conductive lines, wherein a length of the first one of the second conductive lines is less than a length of the second one of the second conductive lines, wherein the first and second ones of the second conductive lines are adjacent, wherein the second and third ones of the second conductive lines are adjacent, wherein the first one of the second conductive lines includes a protruding portion that protrudes toward the second one of the second conductive lines, wherein the second one of the second conductive lines includes a protruding portion that protrudes toward the first one of the second conductive lines, and wherein a distance between the first and second ones of the second conductive lines is equal to a distance between the second and third ones of the second conductive lines.