Patent ID: 7282786

Claim:
A semiconductor package comprising: a leadframe having a die pad and a plurality of first and second leads arranged about the periphery of the die pad; a first semiconductor chip securely attached to a lower surface of the die pad, the first semiconductor chip being electrically coupled to the first and second leads; a first package body individually encapsulating the first semiconductor chip, the die pad and at least a portion of each of the first and second leads, the first package body having a cavity exposing an upper surface of an inner lead portion of each of the second leads; a second semiconductor chip disposed in the cavity of the first package body and above an upper surface of the die pad, the second semiconductor chip being electrically coupled to the inner lead portions of the second leads; and a cover disposed over the cavity of the first package body, wherein at least a portion of the first package body is interposed between the second semiconductor chip and the die pad.