Patent ID: 8796668

Claim:
A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, the method comprising: forming a graphene layer on a substrate; doping a portion of the graphene layer, resulting in a region of doped graphene adjacent a region of undoped graphene; forming a dielectric layer on top of the graphene layer; a via formed through the dielectric layer; forming a carbon nanotube film in the via and over the region of undoped graphene; etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene, the gate comprising a first portion of the etched carbon nanotube film that is isolated from the undoped graphene channel by the dielectric layer; and wherein etching the carbon nanotube film also forms a top level interconnect on top of the dielectric layer and in contact with the via, the top level interconnect comprising a second portion of the etched carbon nanotube film that is separated from the first portion of the etched carbon nanotube film.