Patent ID: 8386977

Claim:
A method for checking integrity of a circuit design for an integrated circuit passing through a first and second semiconductor chip, the first semiconductor chip having larger surface dimensions than the second semiconductor chip, the method comprising: determining a design cell to be mirrored from either a design cell of the first semiconductor chip or a corresponding design cell from the second semiconductor chip; setting a bounding shape parameter around elements of the determined design cell corresponding to the integrated circuit; defining an axis around which coordinates of the determined design cell can be reversed; rotating the elements within the bounding shape parameter around the axis to produce reverse coordinates of the elements corresponding to the integrated circuit; merging the design cell and the corresponding design cell such that the merged design cells represent the integrated circuit passing through the first and second semiconductor chips when stacked; creating a virtual metal abstract layer having dimensions of a terminal metal abstract layer of the first semiconductor chip and images from a terminal metal abstract layer of the second semiconductor chip; and merging the virtual metal abstract layer and the terminal metal abstract layer of the first semiconductor chip wherein the merged metal abstract layers depict connecting contacts of the first and second semiconductor chips when stacked performing one or more verification processes on the merged design cells.