Patent ID: 6970962

Claim:
A pipelined bus system for use in interconnecting devices within a computer system comprising a sending device connected to a receiving device through a processor local bus interface; wherein the receiving device asserts a request pipeline depth signal, the request pipeline depth signal indicating a number N of discrete transfer requests that may be sent by the sending device prior to acknowledgment of receipt of a transfer request by the receiving device; wherein the sending device is configured to sample the request pipeline depth signal and responsively assert a first request signal comprising no more than N transfer requests without waiting for a first request reception acknowledgment; and wherein the receiving device is configured to modify the request pipeline depth signal to either increase or decrease the number N to a number Y prior or subsequent to a first request reception acknowledgement received by the sending device, and the sending device is configured to sample the modified request pipeline depth signal after a first request reception acknowledgment and responsively assert a second request signal comprising no more that Y transfer requests without waiting for a second request reception acknowledgment.