Patent ID: 7519140

Claim:
An automatic frequency correction phase-locked loop (PLL) circuit comprising: an analog control circuit which generates an analog control voltage; and a digital control circuit which generates a digital control signal and which comprises a High-side comparator which receives the analog control voltage and compares the analog control voltage with a High-side threshold voltage, a Low-side comparator which receives the analog control voltage and compares the analog control voltage with a Low-side threshold voltage, a state monitor circuit which receives outputs of the High-side comparator and the Low-side comparator and monitors state of offset frequencies, and a counter and decoder which generates the digital control signal under control of the state monitor circuit, wherein at least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides one of a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes, and, when the analog control voltage is stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit has provided the first threshold voltage, the state monitor circuit switches the threshold switching circuit from providing the first threshold voltage to providing the second threshold voltage, thereby expanding an interval between the High-side threshold voltage and the Low-side threshold voltage.