Patent ID: 8149621

Claim:
A flash memory device comprising: a memory cell array including a plurality of bit lines; a control unit configured to output estimated data; and an input/output buffer unit including a plurality of page buffers, each of the plurality of page buffers corresponding to one of the plurality of bit lines in the memory cell array and configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal, wherein a voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state wherein each of the plurality of page buffers is configured to output the test result signal if every page in the memory cell array to be tested is tested, and each of the plurality of page buffers includes, an output node to output the test result signal, the test result signal indicating whether the bit line corresponding to the page buffer is in a pass state or the failure state, a precharge transistor located between the bit line corresponding to the page buffer from and the output node, the precharge transistor configured to precharge the bit line corresponding to the page buffer with a voltage of the output node based on a precharge control signal, a sensing node connected to the bit line and configured to receive a voltage corresponding to a bit value of the test data read from the precharged bit line, and a latch configured to be active or inactive based on the voltage of the sensing node and output a voltage based on whether the read-out test data and the estimated data are identical.