Patent ID: 7750677

Claim:
A complementary pass-gate logical (CPL) XOR/XNOR circuit, comprising: first and second PMOS devices, sources of which are connected to Vdd; first and second NMOS devices, drains of which are connected to respective drains of the first and second PMOS devices to form respective circuit XNOR and XOR outputs, wherein gates of the first PMOS and first NMOS devices are connected together forming a first node, and wherein the gates of the second PMOS and NMOS devices are connected together forming a second node; third and fourth NMOS devices, drains of which are connected respectively to the first node; fifth and sixth NMOS devices, drains of which are connected respectively to the second node; and A, B circuit inputs, wherein the A circuit input is provide to a source of the third and fifth NMOS devices, the B input is provided to gates of the fourth and sixth NMOS devices, an inverted form of the A input is provided to gates of the fourth and sixth NMOS devices, and an inverted form of the B input is provided to the gates of the third and fifth NMOS devices, wherein the XOR and XNOR outputs are connected respectively to back-gates of the first and second PMOS devices to dynamically modulate the threshold voltages of the PMOS devices during normal circuit operation.