Patent ID: 7523359

Claim:
An apparatus for facilitating, monitoring, and responding to error events, comprising: a set of counters associated with a processing system resource, each counter associated with a Cyclic Redundancy Check (CRC) error event and having attributes defining a count value, one or more counter thresholds directly related to time, and empirical status information for the error event in relation to time, wherein each counter is a sliding counter configured to count error events up to a predefined number of error events within a window of time measured backwards in time from a current time; an update module comprising software stored on a memory device, executed by a processor complex, and configured to update one or more counters within the set in response to an error event for the processing system resource; and a management module comprising software stored on the memory device, executed by the processor complex, and configured to persist and maintain a life cycle for one or more counters based on the attributes the management module further comprising a storage module comprising software stored on the memory device, executed by the processor complex, and configured to selectively store a persistent copy of the counters in the set on a storage device of a redundant processing system in response to one of an error recovery action and a processing system shutdown.