Patent ID: 7940585

Claim:
A multi-column decoder stress test circuit comprising: a control unit configured to receive a plurality of column test signals and generate a multi-column enable signal; and a multi-enable decoding unit coupled to the control unit, the multi-enable decoding unit configured to receive the multi-column enable signal and the plurality of column test signals and to generate a plurality of enabled column selection signals, wherein the multi-enable decoding unit comprises: a multi-enable predecoding unit configured to receive column addresses according to the multi-column enable signal and the column test signals and to output coding signals; and a main decoding unit coupled to the multi-enable predecoding unit, the main decoding unit configured to receive and decode the coding signals and to output the column selection signal, and wherein the coding signals include a plurality of control coding signals and a plurality of main coding signals, and wherein the multi-enable predecoding unit comprises: a control coding unit configured to receive the first column addresses, which are a portion of the column addresses, according to the column test signals and the multi-column enable signal, and to output the control coding signals; and a main coding unit coupled to the control coding unit, the main coding unit configured to receive second column addresses, which are remaining column addresses excluding the first column addresses, according to the multi-column enable signal, and to output the main coding signals.