Patent ID: 7434126

Claim:
A computer-aided design (CAD) method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test and self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode, said CAD method comprising the computer-implemented steps of: (a) compiling the HDL code or netlist that represents said integrated circuit or circuit assembly in physical form into a design database; (b) performing test rule check for checking whether said design database contains any multiple-capture rule violations in said scan-test or said self-test mode; (c) performing test rule repair until all said multiple-capture rule violations have been fixed; (d) performing multiple-capture test synthesis for generating a testable HDL code or netlist; and (e) generating HDL test benches and automatic test equipment (ATE) test programs for verifying the correctness of said testable HDL netlist in said scan-test or said self-test mode.