Patent ID: 7474084

Claim:
A circuit arrangement for driving a gate of a transistor, in particular a MOSFET, which is arranged in an electronic device, said circuit arrangement ( 2 ) being designed for variably driving the gate ( 221 ) as a function of an operating state of the electronic device, in which the transistor ( 23 ) is arranged, the circuit arrangement including: a control unit ( 21 ), which is designed for variably driving the gate ( 221 ); and a gate driver circuit ( 22 ), which is connected to the control unit ( 21 ) and can be parameterized by the control unit ( 21 ), the gate driver circuit ( 22 ) being electrically connected to the gate ( 221 ) of the transistor ( 23 ), wherein the gate driver circuit ( 22 ) has a circuit which is graduated in binary fashion and has pull-up resistors ( 226 a to 226 d ) and pull-down resistors ( 223 a to 223 d ), and a NAND element ( 224 a to 224 d ) is connected to each pull-up resistor ( 226 a to 226 d ) via a corresponding pull-up switching transistor ( 225 a to 225 d ), an AND element ( 221 a to 221 d ) is connected to each pull-down resistor ( 223 a to 223 d ), via a corresponding pull-down switching transistor ( 222 a to 222 d ), and the gate driving signal and the parameterization signal are input to the NAND elements ( 224 a to 224 d ) and AND elements ( 221 a to 221 d ).