Patent ID: 7922920

Claim:
A method to fabricate at least one micro-leak structure, the method comprising: fabricating channels in the at least one micro-leak structure by a plurality of semiconductor processing tools; mounting the at least one micro-leak structure in an inlet of a tube of a gaseous sampling device; patterning two double-sided polished silicon wafers with alignment marks from standard photolithography techniques; transferring a contact aligner and alignment marks to the silicon in a plasma etch: aligning inlet holes on one of the double-sided polished silicon wafers micro-channels on the other double-sided polished silicon wafer; removing photoresist from the two double-sided polished silicon wafers; removing patterned oxide layers from the first of the two double-sided polished silicon wafers in a dilute hydrofluoric acid solution to leave a smoother silicon surface that can interfere with the bonding surface of the wafer; bonding the two double-sided polished silicon wafers in a wafer bonder; annealing the two double-sided polished silicon wafers into a thermal oxidation tube; patterning into one side of the bonded wafer pair inlet holes and circular dicing lanes to define the final device diameter; etching holes and dicing lanes through to the center of the wafer pair; and etching matching dicing lanes and a single outlet hole on the opposite side of the wafer pair.