Patent ID: 6962848

Claim:
A method for fabricating a semiconductor integrated circuit comprising a memory, the method comprising: forming one or more pairs of first structures over a semiconductor substrate, wherein each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells, the control gates in each first structure overlying the floating gates of the first structure, each first structure having a top surface; forming first doped regions in the semiconductor substrate, wherein each pair (S 1 , S 2 ) of the first structures corresponds to a plurality of the first doped regions each of which provides (i) a first source/drain region to a memory cell having floating and control gates in the structure S 1 and (ii) a first source/drain region to a memory cell having floating and control gates in the structure S 2 ; wherein for each pair of structures (S 1 ,S 2 ), the structure S 1 has a first sidewall facing the structure S 2 and has a second sidewall opposite from the first sidewall, and the structure S 2 has a first sidewall facing the structure S 1 and a second sidewall opposite from the first sidewall: and the method further comprises: for each pair (S 1 , S 2 ), forming at least one second conductive line over the semiconductor substrate, wherein a bottom surface of the second conductive line extends between the first structures S 1 and S 2 below the top surfaces of the structures S 1 and S 2 and physically contacts each of the first doped regions which provide the first source/drain regions to the memory cells having floating and control gates in the structures S 1 , S 2 ; and forming a third conductive line adjacent to the second sidewall of each first structure, the third conductive line providing conductive gates to the memory cells having the floating and control gates in the first structure, the conductive gates being insulated from the floating and control gates.