Patent ID: 7206870

Claim:
A hardware register structure in an integrated circuit, comprising: a first plurality of storage elements for storing a set of data, an indicator for signifying a validity of the stored set of data, and an indicator for signifying membership in a group of the stored set of data relative to a previous set of data and a subsequent set of data, and an update input indicator for signifying that values in the storage elements can be replaced by the subsequent set of data; a second plurality of storage elements for storing a copy set of data, an indicator signifying a validity of the stored copy set of data, and an indicator signifying membership in a group of the copy set of data relative to other sets of data; an additional storage element structured to store the update input indicator and to generate an update output indicator that is delayed from the update input indicator by one cycle; a first set of one or more logic elements structured to cause, when the update output indicator is asserted, a new set of copy data, a new indicator-signifying membership in the group, and a new indicator signifying a validity of the new set of copy data to be loaded into the second plurality of storage elements; and a second set of one or more logic elements structured to cause, when the update input indicator is asserted and the update output indicator is de-asserted, the copy set of data presently stored in the second plurality of storage elements to be loaded into the first plurality of storage elements.