Patent ID: 6970527

Claim:
A transmitting circuit comprising: a clock signal transmitting circuit for transmitting a clock signal through a first signal line; a synchronization data generating circuit for generating synchronization data which represents a delimiter of serial data being transmitted of a predetermined unit length, and whose value changes two or more times in a predetermined time interval associated with the clock signal; and a data transmitting circuit for superposing the generated synchronization data on each serial data of the unit length and for synchronizing the serial data with the clock signal and transmitting the serial data through a second signal line; wherein, as said synchronization data, said synchronization data generating circuit generates a set of data including inverted data of the last data of said unit-length serial data, and the last data after the inverted data; wherein said synchronization data generating circuit generates data whose value changes two or more times within a period in which a level of the clock signal is constant, that is, from a rising edge to a next falling edge, or from a falling edge to a next rising edge of said clock signal; and wherein the predetermined time interval from a rising edge to a next rising edge of the clock signal, a frame synchronization data is transmitted and a next frame transmission is started.