Patent ID: 7271638

Claim:
A delay circuit comprising: a delay line circuit including a plurality of stages of delay units; a first switch controlled to be turned on and off based on an input control signal, and a second switch, said second switch being connected to an output of the delay unit of the stage number corresponding to said input control signal, and being turned on at a time point when the transition edge of the rise or fall of the input signal supplied to said delay circuit and propagated has traversed a number of stages corresponding to said input control signal, said second switch causing transition of a common node from one logic value to the other logic value through said first switch in the on-state; a signal generating circuit connected to said common node to generate a rising signal or a falling signal responsive to said transition of said common node; and a control circuit responsive to an input signal supplied to said delay circuit to set said common node to said one logic value by the other transition, that is, the falling or rising, of said input signal.