Patent ID: 8274339

Claim:
A phase lock loop (PLL) voltage-controlled oscillator device, comprising: a tank circuit having a capacitor and an inductor and for providing an oscillating frequency in response to a control voltage; a control block responsive to a frequency control signal and for adjusting oscillation frequency, wherein the device is associated with a frequency verse control voltage curve having a first region for determining if a PLL lock condition is satisfied and defined by V reflo and V refhi , where V reflo is a lower limit of the first region and V refhi is an upper limit of the first region; a post-lock temperature compensation block configured with a switchable multi-leg capacitor bank that is responsive to a digital temperature compensation control signal and for adjusting post-lock oscillation frequency; and an automatic frequency control circuit for generating the frequency control signal and configured with: a reset circuit for resetting the control voltage to a mid-range value between V reflo and V refhi in response to the PLL lock condition not being satisfied and the control voltage being either greater than V refhi for a specified waiting time period or less than V reflo for a specified waiting time period; and an AFC freeze control circuit for causing the automatic frequency control circuit to enter a freeze mode in response to lock being acquired and the control voltage being between V reflo and V refhi for a specified waiting time period; wherein the frequency verse control voltage curve has a second region defined by V bot and V top , where V bot is less than V reflo and V top is greater than V refhi , such that the first region is within the second region; wherein in response to lock being acquired and the control voltage being greater than V top , capacitor legs of the multi-leg capacitor bank are sequentially disengaged until the control voltage is at an acceptable level; and wherein in response to lock being acquired and the control voltage being less than V bot , capacitor legs of the multi-leg capacitor bank are sequentially engaged until the control voltage is at an acceptable level.