Patent ID: 8084784

Claim:
A semiconductor heterostructure comprising: a substrate having a first in-plane lattice parameter; a relaxed buffer layer formed upon the substrate and having a graded second in-plane lattice parameter, wherein the second in-plane lattice parameter is graded so as to increase upward from a minimum at the substrate to a maximum at the top of the buffer layer; a strained additional layer formed upon the buffer layer and having a third in-plane lattice parameter, wherein the third in-plane lattice parameter has a value less than the maximum of the second in-plane lattice parameter at the top of the buffer layer and wherein the thickness of the additional layer is less than a first critical value above which defects occur; and a strained top layer formed upon the additional layer and having a fourth in-plane lattice parameter, wherein the fourth in-plane parameter is constant and wherein the thickness of the top layer is less than a second critical value above which defects occur.