Patent ID: 7349283

Claim:
An integrated semiconductor memory, comprising: a first voltage generator for generating a first operating voltage; at least one circuit component to which the first operating voltage is supplied via a first interconnect; a second voltage generator for generating a second operating voltage, wherein the second operating voltage is supplied to the at least one circuit component via a second interconnect; first comparator circuits, wherein one of the first comparator circuits compares a level of the first operating voltage received from a first location of the first interconnect with a first reference voltage, and another of the first comparator circuits compares a level of the first operating voltage received from a second location of the first interconnect with the first reference voltage, each of the first comparator circuits generating a respective first comparison signal in response to comparison of the level of the first operating voltage with the first reference voltage; second comparator circuits, wherein one of the second comparator circuits compares a level of the second operating voltage received from a first location of the second interconnect with a second reference voltage, and another of the second comparator circuits compares a level of the second operating voltage received from a second location of the second interconnect with the second reference voltage, each of the second comparator circuits generating a respective second comparison signal in response to comparison of the level of the second operating voltage with the second reference voltage; evaluation logic configured to generate evaluations signals each having a first or second state, wherein the evaluation logic controls states of the evaluation signals as a function of the respective first comparison signals in response to receiving the first comparison signals from the first comparator circuits and wherein, in response to receiving the respective second comparison signals, the evaluation logic generates the evaluation signals such that the states of the evaluation signals are a function the respective second comparison signals; and contact terminals configured to receive the evaluation signals.