Patent ID: 7329918

Claim:
A semiconductor memory device comprising: a semiconductor substrate that includes a memory cell array area and a core/perimeter area; an interlayer insulation layer formed on the semiconductor substrate; a first etch stop layer formed on the interlayer insulation layer; a plurality of contact plugs arranged non-linearly in at least one direction and formed on the memory cell array area, the plurality of contact plugs passing through the first etch stop layer and the interlayer insulation layer to contact the semiconductor substrate; a plurality of landing pads arranged non-linearly in at least one direction and formed on the plurality of contact plugs, each of the plurality of landing pads electrically connected with one of the plurality of contact plugs; a plurality of resistors that are formed on the core/perimeter area to the same height as the landing pads; and a plurality of storage nodes, the entire outer lateral surfaces of which are exposed, each of the plurality of storage nodes formed on one of the plurality of landing pads.