Patent ID: 7312495

Claim:
A memory cell comprising: a source and a drain diffused into a substrate, the source and the drain having a channel region therebetween with a midpoint of the channel region being located equidistant from the source and the drain; a first charge storing layer and a second charge storing layer formed on the substrate over the channel region, the first charge storing layer composed of a first material and the second charge storing layer composed of a second material; a gate formed over the source, the drain, the first charge storing layer and the second charge storing layer; a control gate formed over the midpoint of the channel region for controlling a middle portion of the channel region, said control gate located equidistant between the first charge storing layer and the second charge storing layer and underneath the gate; and a plurality of dielectric layers, wherein a first of the plurality of dielectric layers separating the source from the gate, a second of the plurality of dielectric layers separating the drain from the gate, and a third, a fourth and a fifth of the plurality of dielectric layers separating the control gate from the first charge storing layer, the second charge storing layer and the gate, respectively, and wherein at least the third and the fourth of the plurality of dielectric layers is composed of a third material, the third material providing an isolation dielectric thickness of greater than seventy Angstroms in order to separate the first material of the first charge storing layer and the second material of the second charge storing layer from the control gate, and wherein at least one of the first and second materials is an ONO material composed of a bottom dielectric layer of oxide, a middle nitride charge trapping layer and a top dielectric layer of oxide, wherein the middle nitride charge trapping layer has a nitride charge trapping layer length between 150 angstroms and 300 angstroms.