Patent ID: 8701064

Claim:
A timing error removing method comprising: selecting a logic-level correction location corresponding to a connection between cells in a semiconductor integrated circuit to be designed and a first buffer to be inserted at the logic-level correction location, wherein the logic-level correction location and the first buffer are able to remove a timing error in the semiconductor integrated circuit to be designed, and the selecting being executed by a central processing unit; and searching for a vacant area in the semiconductor integrated circuit where the first buffer can be placed for the logic-level correction location, and if the vacant area is not found, further searching for a combination of a plurality of buffers whose respective physical sizes are smaller than a physical size of the first buffer, the combination of the plurality of buffers being able to be placed in the semiconductor integrated circuit and being able to replace the first buffer in terms of a delay obtained as if the first buffer is inserted, and the searching being executed by the central processing unit.