Patent ID: 7692252

Claim:
A semiconductor integrated circuit device comprising: a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell well contact area, wherein a layout pattern of the first wiring bodies is the same as a layout pattern of the second wiring bodies, wherein the first wiring bodies include bit lines, word lines and block selection lines, the second wiring bodies include cell well bias lines, word lines and block selection lines, the bit lines and cell well bias lines are formed by use of the same conductive layer and width of the bit line in a row direction is the same as width of the cell well bias line in the row direction, wherein transistors each having a source/drain portion of the same conductivity type as the conductivity type of the cell well are formed below the cell well bias line and the cell well bias line is connected to the cell well via the source/drain portion of the above same conductivity type.