Patent ID: 8283731

Claim:
A programmable memory array comprising a plurality of memory cells, at least one memory cell of the plurality of memory cells comprising: an isolation layer formed of a dielectric material; a field effect transistor comprising: a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type, wherein the first semiconductor region and the second semiconductor region are formed over the isolation layer; a channel region of a second conductivity type formed between the first semiconductor region and the second semiconductor region; a first gate insulator overlying the channel region; and a first conductive gate overlying the first gate insulator; a programmable element comprising: a third semiconductor region of the first conductivity type; the second semiconductor region of the first conductivity type; a semiconductor body present between the second semiconductor region and the third semiconductor region, wherein the third semiconductor region and the semiconductor body are formed over the isolation layer, and, wherein the semiconductor body of the programmable element is undoped; a second gate insulator overlying the semiconductor body; and a second conductive gate present over the second gate insulator; a bit line in contact with the first semiconductor region; a select word line coupled to the first conductive gate; and a program word line coupled to the second conductive gate.