Patent ID: 8054280

Claim:
A data driver comprising: an input circuit structured to receive at least one external digital image data signal; a converter electrically coupled to the input circuit and structured to receive the at least one image data signal from the input circuit, and to convert the at least one image data signal into at least one analog data voltage; an output buffer circuit electrically coupled to the converter and structured to receive the analog data voltage from the converter, and to buffer the analog data voltage responsive to at least one bias voltage; a bias voltage control circuit electrically coupled to the output buffer; and a feedback path between the output buffer circuit and the bias voltage control circuit, wherein the bias voltage control circuit is structured to receive the analog data voltage from the output buffer circuit, to compare the analog data voltage with a predefined reference voltage so as to count a slew rate of the analog data voltage, and to vary a voltage level of the at least one bias voltage based on the counted result of the slew rate, and wherein the bias voltage control circuit comprises: a comparator structured to compare the analog data voltage and the reference voltage responsive to a first clock and a first enabling signal, and to output a comparison voltage corresponding to the compared result; a first level shifter structured to level down the comparison voltage; a counter structured to receive the leveled down comparison voltage, to count a number of a high period of the comparison voltage responsive to a second clock and a second enabling signal, and to output first to k th voltages corresponding to the count number; a latch structured to latch the first to k th voltages output from the counter responsive to an output start signal and the first enabling signal; a second level shifter structured to level up the first to k th voltages output from the latch to output first to k th switching voltages; and a bias circuit structured to control a voltage level of the at least one bias voltage responsive to the first to k th switching voltages, and to feedback the at least one bias voltage to the output buffer circuit.