Patent ID: 7749841

Claim:
A method of fabricating a nonvolatile semiconductor memory device having a memory array configuration including a plurality of bit lines each formed of a diffusion layer and a plurality of word lines formed over a surface region of a semiconductor substrate, the plurality of bit lines being arranged side by side in a column direction, and the plurality of word lines being arranged side by side in a row direction crossing the bit lines, the method comprising the steps of: (a) forming a layered dielectric film on the semiconductor substrate; (b) forming a first conductive film including silicon as a main component on the layered dielectric film; (c) forming a first dielectric film on the first conductive film; (d) patterning the first dielectric film and the first conductive film such that the first dielectric films and first conductive films are left side by side in the column direction to form a layered pattern composed of the first dielectric films and the first conductive films; and (e) performing first impurity implantation to form a first impurity diffusion layer being the same in conductivity type as the semiconductor substrate, the first impurity implantation being performed along a direction having an inclination angle to a normal direction to a principal plane of the semiconductor substrate by using the layered pattern as a mask, wherein: step (d) includes: (da1) patterning the first dielectric film by selective etching such that the first dielectric films having a shape with a width narrower in an upper surface than in a lower surface are left side by side in the column direction; and (da2) after step (da1), patterning the first conductive film to form the first conductive films having a substantially vertical shape by using the patterned first dielectric films as a mask, and in step (c), the first dielectric film is formed to have a thickness larger than a total thickness of the layered dielectric film and the first conductive film.