Patent ID: 7663415

Claim:
A phase locked loop (PLL), comprising: a phase frequency detector having a first input connected to the input of the PLL and having a second input, controlled charge pump with an associated loop filter, having its input connected to the output of the phase frequency detector, and having a control input, an output, and having a gain, a controlled oscillator having a control input an output, a frequency divider having its input connected to the output of the controlled oscillator and its output connected to the second input of said phase frequency detector, and a compensation block having a first input connected to the output of said controlled charge pump, a second input connected to the output of said controlled oscillator, a first output connected to the control input of said controlled charge pump and a second output connected to the control input of said controlled oscillator, the compensation block operable to generated signals on the first and seconds outputs to set the value of the gain of the controlled charge pump that causes the controlled charge pump to supply control signals on the control input of the controlled oscillator that causes an output signal on the output of the controlled oscillator to have minimum and maximum frequencies having expected minimum and maximum values, respectively.