Patent ID: 8324070

Claim:
A method for manufacturing a semiconductor device, the method comprising: forming an active region in a semiconductor substrate; forming a first silicon layer over the active region, wherein the first silicon layer is coupled to the active region; forming a relaxed silicon germanium layer in a trench formed in an NMOS region of the first silicon layer; forming a second silicon layer over the relaxed silicon germanium layer; forming a third silicon layer over a PMOS region except the NMOS region of the first silicon layer; and forming a gate on the second silicon layer and the third silicon layer; wherein forming the third silicon layer includes: forming a third hard mask pattern exposing the PMOS region on the second silicon layer; growing a silicon layer using by the third hard mask pattern as a growth barrier on the first silicon layer; and exposing the second silicon layer by planarizing the third hard mask pattern and the third silicon layer.