Patent ID: 7945740

Claim:
A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising: a memory switching data processing system comprising: one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing one or more communications paths for data among the one or more CPUs and the at least two banks of memory modules; and a flexibly configurable memory bus switch implemented separately from the at least two banks of memory modules, wherein the switch comprises a first configuration adapting a first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules, and wherein one or more segments of the switch are implemented by a plurality of dual in-line memory module (‘DIMM’) cards, the plurality comprising a first DIMM card including a first edge connector configured to adapt the first CPU only to the first bank of memory modules and a second DIMM card including a second edge connector configured to adapt the first CPU to both the first bank of memory modules and the second bank of memory modules.