Patent ID: 8560816

Claim:
A method, comprising: a processor initiating execution of a sequence of instructions comprising an atomic transaction; during execution of the sequence of instructions, the processor encountering an instruction within the atomic transaction that modifies a value of a processor register; in response to said encountering: the processor determining whether the processor register should be checkpointed; and in response to determining that the processor register should be checkpointed, the processor checkpointing the processor register, where said checkpointing comprises: saving the value of the processor register; and setting a value of an indicator associated with the processor register to a value that indicates that the processor register has been checkpointed; and in response to the atomic transaction failing to commit its results: the processor determining whether the value of the processor register will be modified prior to being read by another instruction; and the processor restoring the saved value of the processor register to the processor register unless it is determined that the processor register will be modified prior to being read by another instruction; wherein no processor registers are checkpointed in response to said encountering other than those whose values are modified by the encountered instruction; and wherein at least some of said determining, said saving, or said setting are performed by hardware mechanisms within the processor.