Patent ID: 7675444

Claim:
An isolation circuit comprising: a first line circuit comprising: a plurality of data converters, coupled to receive input signals, the plurality of data converters samples and converts the inputs signals to a plurality of input digital signals; a multiplexer, coupled to receive the plurality of input digital signals and a synchronization signal, the multiplexer combines the plurality of input digital signals and the synchronization signal into an unencoded composite bit stream; a data encoder, coupled to receive the unencoded composite bit stream, the data encoder removes a DC bias from the unencoded bit stream and outputs a composite bit stream that is coupled to an isolation capacitor, the composite bit stream having a frequency above a threshold that allows the composite bit stream to be communicated across the isolation capacitor; a neutral potential circuit comprising: a data decoder, coupled to the isolation capacitor and to receive the composite bit stream, the data decoder decodes the composite bit stream, and generates a recovered data stream and a recovered clock; a control logic, synchronization and de-multiplex module, coupled to receive the recovered data stream and the recovered clock, the control logic, synchronization and de-multiplex module synchronizes the recovered data stream relative to the recovered clock and generates a plurality of output digital signals corresponding to the plurality of input signals; and wherein the first line circuit is in close proximity to a second line circuit, and a potential difference between the first and second line circuit is greater than 1500 volts.