Patent ID: 7176513

Claim:
A memory device having an address bus and a data terminal, comprising: an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line; a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus; a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell comprises: an active region formed in a substrate; an epitaxial post formed over the active region, the epitaxial post defined by at least one surface facing away from a surface of the substrate and at least two peripheral surfaces; a transfer gate formed adjacent to the at least two peripheral surfaces of the epitaxial post; and a memory cell capacitor formed over the at least one surface facing away from the surface of the substrate.