Patent ID: 7082581

Claim:
A memory device comprising: an address interface coupled to a first I/O buffer circuit; a first interconnect circuit coupled to the first I/O buffer circuit and to an address register, wherein the first interconnect circuit comprises, a first set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, a subset of generally longer than average conductors of the first set of conductors, and a subset of generally shorter than average conductors of the first set of conductors, wherein each member of the subset of shorter conductors is routed beside a member of the subset of longer conductors such that a space occupied by each of the shorter conductors is not filled by another conductor or component when each of the shorter conductors reaches the end of its generally parallel run length; a data interface coupled to a second I/O buffer circuit; a second interconnect circuit coupled to the second I/O buffer circuit and to a data buffer, wherein the second interconnect circuit comprises, a second set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, a subset of generally longer than average conductors of the second set of conductors, and a subset of generally shorter than average conductors of the second set of conductors, wherein each member of the subset of shorter conductors is routed beside a member of the subset of longer conductors such that a space occupied by each of the shorter conductors is not filled by another conductor or component when each of the shorter conductors reaches the end of its generally parallel run length; a control interface coupled to a third I/O buffer circuit; and a third interconnect circuit coupled to the third I/O buffer circuit and to a control circuit, wherein the third interconnect circuit comprises, a third set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, a subset of generally longer than average conductors of the third set of conductors, and a subset of generally shorter than average conductors of the third set of conductors, wherein each member of the subset of shorter conductors is routed beside a member of the subset of longer conductors such that a space occupied each of the shorter conductors is not filled by another conductor or component when each of the shorter conductors reaches the end of its generally parallel run length.