Patent ID: 8610260

Claim:
A microelectronic package, comprising: first and second microelectronic elements each embodying a greater number of active devices to provide memory storage array function than any other function, and each microelectronic element having one or more columns of element contacts each column of element contacts extending in a first direction along a face of such microelectronic element; a substrate having first and second opposed surfaces and first and second opposed edges extending between the first and second surfaces, the first surface having first substrate contacts and second substrate contacts thereon, the first substrate contacts facing the element contacts of the first microelectronic element and joined thereto, and the second substrate contacts facing the element contacts of the second microelectronic element and joined thereto; and a plurality of terminals exposed at the second surface of the substrate and electrically connected with the first and second substrate contacts, the terminals being disposed at positions within a plurality of parallel columns extending in the first direction along the second surface of the substrate and being configured to connect the microelectronic package to at least one component external to the microelectronic package, the terminals including first terminals disposed within at least one of the columns of terminals in a central region of the second surface of the substrate, the first terminals being configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within a microelectronic element of the first and second microelectronic elements, wherein the central region has a width in a second direction along the second surface of the substrate transverse to the first direction, the width of the central region not more than three and one-half times a minimum pitch between any two adjacent columns of the parallel columns of the terminals, wherein an axial plane extending in the first direction and centered relative to the columns of element contacts of the first and second microelectronic elements extends in a third direction normal to the second surface of the substrate and intersects the central region of the second surface, and wherein the first terminals are configured to carry all of the address information usable by the circuitry within the package to determine the addressable memory location.