Patent ID: 7581128

Claim:
A microcomputer, comprising: a central processing unit; a program memory for storing a control program executed by the central processing unit; a plurality of peripheral circuits for implementing a predetermined function; a clock control circuit for controlling a clock signal provided to the central processing unit and the peripheral circuits; a voltage drop detection circuit for detecting a drop in a voltage of a power source below a predetermined level, the voltage drop detection circuit being disposed at an end portion of a power line, and an interrupt control circuit for outputting an interrupt request to the central processing unit when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, wherein the program memory further stores a subroutine program for causing the central processing unit to execute a clock control process, when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, a frequency of the clock signal provided through the clock control circuit to the central processing unit is divided down, a supply of the clock signal provided to the peripheral circuits is stopped, and the subroutine program is executed by the central processing unit, the central processing unit, operating in accordance with the subroutine program, selectively resumes the supply of the clock signal provided to the peripheral circuits, the central processing unit, operating in accordance with the subroutine program, selectively divides down a frequency of the clock signal provided to the peripheral circuits while resuming the supply, the clock control circuit includes a divider circuit and a multiplexer circuit for selecting between a first path for outputting the clock signal provided to the central processing unit without frequency division and a second path for outputting the clock signal provided to the central processing unit through the divider circuit, when the voltage drop detection circuit detects the drop in the voltage below the predetermined level, the multiplexer circuit switches to the second path, and when the central processing unit enables the interrupt request, the interrupt control circuit outputs a interrupt vector pointing to a starting address of the subroutine program to the central processing unit.