Patent ID: 7663936

Claim:
A semiconductor device comprising: a plurality of word lines; a plurality of bit lines each intersecting each of the word lines; a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines; a plurality of sense amplifiers each operatively connected to an associated one of the bit lines to amplify a data signal on the associated one of the bit lines; a plurality of data holding circuits each temporally storing data from an associated one of the sense amplifiers, the data holding circuits being divided into a plurality of groups each including plural data holding circuits; a plurality of selectors each provided for an associated one of the groups and each including a plurality of input nodes and an output node, the input nodes of each of the selectors being connected respectively to the data holding circuits of an associated one of the groups, each of the selectors selecting one of the input nodes in response to logic input data supplied thereto and connecting a selected one of the input nodes to the output node; and a set of data terminals each connected to the output node of an associated one of the selectors.