Patent ID: 8161091

Claim:
A method for performing a decimal floating point operation, the method comprising: receiving a first operand including a first coefficient and a first exponent into a first register; receiving a second operand including a second coefficient and a second exponent into a second register; receiving an operation associated with the first operand and the second operand, wherein the operation is an addition or a subtraction; performing three concurrent calculations on the first operand and the second operand, the three concurrent calculations including: applying the operation to the first operand and the second operand based on a first assumption that the first exponent is equal to the second exponent, wherein the applying the operation based on the first assumption results in a first result and includes utilizing a two cycle adder; applying the operation to the first operand and the second operand based on a second assumption that an absolute difference between the first exponent and the second exponent is less than or equal to a number of leading zeros in the coefficient of the operand with the larger exponent, wherein the applying the operation based on the second assumption results in a second result and includes utilizing exponent difference circuitry, rotator circuitry, and the two cycle adder; and applying the operation to the first operand and the second operand based on a third assumption that the absolute difference between the first exponent and the second exponent is greater than the number of leading zeros in the coefficient of the operand with the larger exponent, wherein the applying the operation based on the third assumption results in a third result and includes utilizing the exponent difference circuitry, leading zero detect circuitry, the rotator circuitry, and the two cycle adder; and selecting a final result using result selector circuitry, the selecting from the first result, the second result and the third result.