Patent ID: 7360062

Claim:
A method for controlling cycle-by-cycle interleaving of instructions between a number of instruction threads in a simultaneous multithreading processor, the method including the steps of: (a) generating a base thread selection signal based at least partially on an interleaving rule which specifies a relative frequency at which instructions are to be taken from each of the number of instruction threads, the base thread selection signal indicating a first instruction thread for processing from among the number of instruction threads; (b) applying a feedback signal associated with one of the instruction threads included in the number of instruction threads as a first input and applying the base thread selection signal as a second input in generating a final thread selection signal, the final thread selection signal indicating a particular instruction thread included in the number of instruction threads; (c) generating an additional base thread selection signal based at least partially on the interleaving rule, the additional base thread selection signal indicating an additional instruction thread for processing from among the number of instruction threads; (d) applying an additional feedback signal associated with one of the instruction threads included in the number of instruction threads as an additional first input and applying the additional base thread selection signal as a second additional input in generating an additional final thread selection signal, the additional final thread selection signal indicating a respective instruction thread included in the number of instruction threads; and (e) combining the final thread selection signal and the additional final thread selection signal to produce a thread selection MUX control signal, and applying the thread selection MUX control signal to effect a selection of one of the number of instruction threads for interleaving an instruction into an interleaved stream of instructions.