Patent ID: 7903722

Claim:
An apparatus comprising: a receiver for receiving a multipath signal; and a searcher that stores delayed samples of the received multipath signal; wherein the searcher is operative on the delayed samples of the received multipath signal for identifying one or more paths of the received multipath signal; wherein the searcher comprises: a shift register for storing J sub-chip delayed samples of the received multipath signal; a number of descramblers for correlating at least some of the stored J sub-chip delayed samples of the received multipath signal with a portion of a scrambling code over a chip interval, such that (a) N of the J sub-chip delayed samples are correlated at a time with the portion of the scrambling code, where J>N>1, and (b) J output values are provided over the chip interval, wherein each descrambler uses the same portion of the scrambling code; and an integrator for accumulating each of the J output values from the number of descramblers over a dwell period, wherein the dwell period comprises more than one chip interval.