Patent ID: 7508698

Claim:
A method of writing to an SRAM memory cell of an array using an SRAM bitline enhancement circuit for enhancing a differential voltage produced by the memory cell on associated first and second bitlines of the array without the use of a sense amplifier circuit, the SRAM memory cell comprising first and second cross-coupled inverters connected to first and second latch nodes, respectively, and first and second pass transistors connected between the first and second latch nodes and the respective first and second bitlines of the array, the SRAM bitline enhancement circuit comprising first and second cross-coupled pull-ups connected between a supply node and the first and second bitlines, respectively, wherein an output of the first pull-up is connected to the first bitline, and an output of the second pull-up is connected to the second bitline, and wherein an input of the first pull-up is connected to the second bitline and an input of the second pull-up is connected to the first bitline, the method comprising: accessing a wordline associated with the SRAM memory cell by asserting a read wordline voltage to the accessed wordline, thereby generating the differential voltage between the first and second bitlines; enhancing the differential voltage on the first and second bitlines of the array without the use of a sense amplifier circuit using the SRAM bitline enhancement circuit; and asserting a write wordline voltage after generation of the differential voltage between the first and second bitlines to the accessed wordline of the memory cell during a write operation after enhancing the differential voltage on the first and second bitlines.