Patent ID: 8198700

Claim:
A semiconductor device structure, comprising: a p-type metal oxide semiconductor (PMOS) region and an n-type metal oxide semiconductor (NMOS) region defined in a substrate, the PMOS region and NMOS region separated by one or more inter-well shallow trench isolation (STI) structures; the PMOS region having a first set of intra-well STI structures formed therein for isolating semiconductor devices formed within an n-type well and the NMOS region having a second set of intra-well STI structures formed therein for isolating semiconductor devices formed within a p-type well, wherein the one or more inter-well STI structures are formed at a substantially same depth with respect to the first and second sets of intra-well STI structures; the PMOS region further having a main n-well region formed therein, and the NMOS region further having a main p-well region formed therein, wherein a bottom of the main n-well region and the main p-well region is disposed above a bottom of the one or more inter-well and first and second sets of intra-well STI features; the PMOS region further having one or more deep n-well regions formed therein that couple main n-well and regions otherwise isolated by the first set of intra-well STI structures; and the NMOS region further having one or more deep p-well regions formed therein that couple main p-well and regions otherwise isolated by the second set of intra-well STI structures; wherein the one or more deep n-well and deep p-well regions are spaced away from the one or more inter-well STI structures.