Patent ID: 7420394

Claim:
A buffer circuit, comprising: a first buffer stage, the first buffer stage comprising: a signal input; a first node responsive to the signal input; a second node responsive to the signal input; a variable resistive device having a first terminal coupled to the first node and a second terminal coupled to the second node, the variable resistive device for providing a variable resistance between the first and second nodes; a second buffer stage, the second buffer stage comprising: a signal output; a first transistor including a control electrode coupled to the first node; a second transistor including a control electrode coupled to the second node; a third transistor including a control electrode coupled to the first node; a fourth transistor including a control electrode coupled to the second node; wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are series coupled transistors coupled between a first voltage terminal and a second voltage terminal.