Patent ID: 7609090

Claim:
A level shifter circuit comprising MOS input devices and cross-coupled MOS pull-up devices, each MOS pull-up device being coupled in series with a respective one of the MOS input devices, and each of the MOS input devices including an input node adapted to receive an input signal and including a signal node coupled to a corresponding output node of the level shifter circuit, the level shifter circuit further comprising a dynamic charge injection device coupled to each output node, each dynamic charge injection device operable responsive to the input signal applied to a corresponding one of the MOS input devices to inject current into the corresponding output node to reduce a capacitive coupling between the input node and the corresponding output node; wherein the level shifter circuit comprises: a first PMOS transistor having a source terminal connected to a high voltage supply, a drain terminal connected to a first output node, and a gate terminal connected to a second output node; a second PMOS transistor having a source connected to the high voltage supply, a drain terminal connected to the second output node, and a gate terminal connected to the first output node; a first NMOS transistor having a drain terminal connected to the drain terminal of the first PMOS transistor through the first output node, a source terminal connected to a ground voltage and a gate terminal connected to a first input node for receiving a first input signal; a second NMOS transistor having a drain terminal connected to the drain terminal of the second PMOS transistor through the second output node, a source terminal connected to the ground voltage and a gate terminal connected to a second input node for receiving a second input signal, the second signal being an inverted signal of the first input signal; an inverter circuit operatively coupled between the gate terminal of first NMOS transistor and the gate terminal of the second NMOS transistor for inverting the first input signal to the second input signal; a first NMOS diode connected to the first output node for providing the second input signal; and a second NMOS diode connected to the second output node for providing the first input signal.