Patent ID: 7724031

Claim:
An integrated circuit (IC) device comprising: a first group of logic array blocks (LABS) substantially aligned with each other parallel to a line; and a second group of LABs substantially aligned with each other paralled to said line and spaced from the first group of LABs perpendicular to said line, the second group of LABs being coupled to the first group of LABs by a plurality of horizontal and vertical conductors, wherein: each LAB in the first and second groups comprises (1) a same plural number of logic elements (LEs), each of which LEs can provide a look-up table combinational logic function, and (2) a secondary signal region for providing clock signals to the LEs in the LAB; and the first group of LABs is substantially offset from the second group of LABs parallel to said line by half the number of LEs in each LAB.