Patent ID: 8468488

Claim:
A method placing and routing a signal path in an integrated circuit layout, said integrated circuit layout comprising a plurality of rows of cells, and said signal path comprising a plurality of said cells and combinational paths having at least one net between said cells in said signal path, said method comprising: determining whether an adjacent cell is swappable with a selected cell, wherein said selected cell is one of said cells of said signal path, and said adjacent cell is swappable when said adjacent cell (i) is adjacent to said selected cell in a same row as said selected cell or (ii) is in an adjacent row in said integrated circuit layout and has a same width or a same available area as said selected cell; using a computer or data processing system, determining a difference in a delay of said signal path by swapping positions of said swappable cell and said selected cell; determining whether swapping said positions of said swappable cell and said selected cell (i) improves timing of the signal path and (ii) causes a timing violation in one or more other signal paths of said layout; and when swapping said positions of said swappable cell and said selected cell (i) does not cause a timing violation in the one or more other signal paths and (ii) improves timing of the signal path, re-placing said swappable cell and said selected cell in the swapped positions, and re-routing wires in affected nets in the combinational paths.