Patent ID: 8503601

Claim:
A gate-on array shift register, comprising: a signal input unit, receiving and providing a input signal; a control transistor, comprising two terminals and a control terminal, the control terminal of the control transistor being electrically coupled to the signal input unit to receive the previous-stage output signal, one terminal of the control transistor being for receiving a first clock signal and another terminal of the control transistor being coupled to the output terminal of the gate-on array shift register, the control transistor being conducted at a first pulse period of the first clock pulse signal; and at least three stable modules, each of the at least three stable module being electrically coupled to the control terminal of the control transistor and the output terminal of the gate-on array shift register, and stabilizing the control terminal of the control transistor and the output terminal of the gate-on array shift register at a specific potential when a corresponding clock pulse signal and the previous-stage pulse signal are enabled, each of the stable modules having a work clock with a frequency different from the frequency of the first clock signal, and enable periods of the work clocks of the stable modules being different from each other and work cycles of the work clocks being respectively less than 50%.