Patent ID: 8738167

Claim:
A non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, the program comprising instructions for performing the steps of: providing a first active circuitry layer wafer comprising a P+ portion covered by a P− layer, the P− layer of the first active circuitry layer wafer including active circuitry; fabricating a first wiring layer at a top surface of the first active circuitry layer wafer; bonding the first wiring layer of the first active circuitry layer wafer directly to a second wiring layer of an interface wafer; after bonding the first active circuitry layer wafer to the interface wafer, selectively removing the P+ portion of the first active circuitry layer wafer with respect to the P− layer of the first active circuitry layer wafer; and after selectively removing the P+ portion of the first active circuitry layer wafer, fabricating a third wiring layer directly on the backside of the P− layer, wherein the program further comprises instructions for performing the steps of: providing a base wafer, the base wafer including a fourth wiring layer; performing a high-precision face-to-face alignment of the P− layer of the first active circuitry layer wafer face down to the base wafer; and bonding the third wiring layer on the backside of the P− layer of the first active circuitry layer wafer directly to the fourth wiring layer of the base wafer.