Patent ID: 7177185

Claim:
A non-volatile memory device having a unit cell, the unit cell comprising: a transistor including: a gate oxide layer on a substrate; a polysilicon gate having lateral faces; sidewall floating gates having lateral faces; block oxide layers formed between the polysilicon gate and sidewall floating gates, the block oxide layers comprising a first block oxide layer and a second block oxide layer on the first block oxide layer; sidewall spacers formed on the lateral faces of the polysilicon gate and the lateral faces of the sidewall floating gates; a polysilicon oxide layer formed between polysilicon gate and the sidewall floating gates and the sidewall spacers, and over a top surface of the polysilicon gate; and source and drain regions; a plurality of word lines vertically placed on the substrate and connected to the polysilicon gate; a first bit line orthogonally placed to the word lines and connected to the source region; and a second bit line orthogonally placed to the word lines and connected to the drain region.