Patent ID: 8811054

Claim:
A system, comprising: a semiconductor memory device and a controller, the semiconductor memory device comprising: a first external terminal provided to receive a system clock; a second external terminal provided to receive a read command; a third external terminal configured to output a data strobe signal in response to the read command, the data strobe signal including a read preamble and a toggle transition following to the read preamble; a fourth external terminal provided to output a read data in synchronization with the toggle transition of the data strobe signal; and control circuitry configured to control a length of the read preamble of the data strobe signal based on a preamble length information, the length of the read preamble being either a first length corresponding to the preamble length information or a second length, and the control circuitry being further configured to control a dynamic change of the length of the read preamble between the first and second lengths based on a change of operation within the semiconductor device, and wherein one of the first length and the second length is at least substantially longer than the other length, the controller comprising: a fifth external terminal provided to correspond to the system clock; a sixth external terminal provided to output the read command; a seventh external terminal provided to receive the read data; an eighth external terminal provided to receive the data strobe signal related to the read data; and a ninth external terminal provided to output the preamble length information.