Patent ID: 8910233

Claim:
A signal processing apparatus, comprising: a first signal processing block, for processing an input signal to generate a first target processing result, including a plurality of packets that are in a packet format recognizable to a second signal processing block the first time after the input signal is received by the first signal processing block, to an output port of the first signal processing circuit, wherein each of the packets contains a corresponding packet identifier (PID), wherein the input signal is not in the packet format recognizable to the second signal processing block, and the first signal processing block derives the packets from processing the input signal; and the second signal processing block, having an input port coupled to the output port of the first signal processing circuit, for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result; wherein there is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit.