Patent ID: 7724569

Claim:
A 1-transistor type DRAM driving method performing a data write of a bit corresponding to a level applied to a bit line, the method including: holding data in a first hold period by deactivating a word line of an NMOS transistor component and precharging a source line and a bit line thereof; operating both the NMOS transistor component and a bipolar transistor component in a complex operation period by activating the word line of the NMOS transistor component, shifting a source line voltage from the precharge to a ground voltage, and shifting a bit line voltage from the precharge to a corresponding multi level bit voltage level after the first hold period; operating only the bipolar transistor component in a bipolar transistor operation period by deactivating the word line of the NMOS transistor component after the complex operation period; and holding the data in a second hold period by precharging the source line and the bit line of the NMOS transistor component, whereby the data write of the corresponding multi level bit applied to the bit line is performed after the bipolar transistor operation period.