Patent ID: 7496695

Claim:
An apparatus comprising: a first interface circuit configured to communicate on an interface according to a protocol; a direct memory access (DMA) controller coupled to the first interface circuit; and a host coupled to the DMA controller, wherein the host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host; wherein the DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and wherein the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations; and wherein the DMA controller comprises a transmit control circuit, a receive control circuit, and a loopback circuit coupled to the transmit control circuit and the receive control circuit, wherein the transmit control circuit is configured to read data from the first plurality of the plurality of memory locations and provide the data to the loopback circuit, and wherein the loopback circuit is configured to provide the data to the receive control circuit, and wherein the receive control circuit is configured to write the data to the second plurality of the plurality of memory locations; and wherein the receive control circuit is further configured to write data from the first interface circuit to the address space, and wherein the DMA controller comprises an arbiter configured to arbitrate between the loopback circuit and the first interface circuit to provide data to the receive control circuit in the case that data is available to be written concurrently from both the first interface circuit and the loopback circuit; and wherein the transmit control circuit is configured to read the data from the first plurality of the plurality of memory locations in response to a DMA descriptor, and wherein the DMA descriptor further includes an address of the second plurality of the plurality of memory locations, and wherein the loopback circuit is coupled to receive the address and to provide the address to the receive control circuit to write the data to the second plurality of the plurality of memory locations.