Patent ID: 8537094

Claim:
A shift register, comprising a plurality of stages, {S n }, connected in serial, n=1, 2, . . . , N, N being a positive integer, wherein each stage S n comprises: (a) a first output for outputting a gate signal, G(n), and a second output for outputting a stage carry signal, ST(n); (b) a pull-up circuit electrically coupled between a node, Q(n), and the second output; (c) a pull-up control circuit electrically coupled to the node Q(n); (d) a pull-down circuit electrically coupled between the node Q(n) and the first output, wherein the pull-down circuit comprises a first pull-down circuit and a second pull-down circuit; (e) a pull-down control circuit electrically coupled between the node Q(n) and the pull-down circuit, wherein the pull-down control circuit comprises a first pull-down control circuit and a second pull-down control circuit; and (f) a control circuit electrically coupled between the node Q(n) and the first output; wherein each of the first and second pull-down control circuits comprises: a first transistor T 51 /T 61 having a gate configured to receive a first clock signal, LC 1 or a second clock signal, LC 2 , a source electrically coupled to the gate and a drain; a second transistor T 52 /T 62 having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the first transistor T 51 /T 61 and a drain configured to receive a supply voltage VSS; a third transistor T 53 /T 63 having a gate electrically coupled to the drain of the first transistor T 51 /T 61 , a source electrically coupled to the source of the first transistor T 51 /T 61 and a drain electrically coupled to a node P(n)/K(n); and a fourth transistor T 54 /T 64 having a gate electrically coupled to the node Q(n), a source electrically coupled to the drain of the third transistor T 53 /T 63 and a drain configured to receive the supply voltage VSS; and wherein the pull-up control circuit of the stage S n is further electrically coupled to the node Q(n−1) and the second output of the stage S n−1 , and comprises: a first transistor T 11 having a gate, a source electrically coupled to the second output of the stage S n−1 for receiving the stage carry signal ST(n−1) therefrom and a drain electrically coupled to the input node Q(n); and a second transistor T 12 having gate electrically coupled to the node Q(n−1) of the stage S n−1 , a source configured to receive one of a plurality of control signals {HCj}, and a drain electrically coupled to the gate of the first transistor T 11 .