Patent ID: 7352645

Claim:
A semiconductor memory device, comprising: a memory matrix comprising a plurality of memory cells, arranged according to a plurality of rows and a plurality of columns; a plurality of bit lines, each bit line being associated with at least one respective column of said plurality; a bit line selection structure structured to select at least one of said bit lines; and a voltage clamping circuit structure structured to cause clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to the selected at least one of said bit lines during a read operation, wherein said voltage clamping circuit structure includes: a plurality of controlled clamping devices, each one univocally connected to a respective bit line; a control circuit structured to selectively activate the controlled clamping devices, wherein said plurality of controlled clamping devices is arranged according to at least two arrays, the bit lines connected to the controlled clamping devices of one of the at least two arrays being alternated with the bit lines connected to the controlled clamping devices of another one of the at least two arrays; and a hierarchic column selection structure comprising: a first hierarchic level comprising first-level bit lines, each one associated with a respective column of said plurality; a levels hierarchy of levels higher than the first hierarchic level, said levels hierarchy comprising at least one higher hierarchic level higher than the first hierarchic level, said higher hierarchic level comprising respective higher-level bit lines, each one associated with a respective packet of lower-level bit lines belonging to a lower hierarchic level lower than said higher hierarchic level; and a bit line selection structure for selecting at least one of the bit lines of the at least one higher hierarchic level.