Patent ID: 7292176

Claim:
A delay line, comprising: a delay-control terminal; a reset terminal; and n stages of delay cells DCELL x connected in series, wherein each of the delay cells DCELL x is coupled to the delay-control terminal and the reset terminal for transmitting a first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period, and resetting the outputs of the delay cells to a second level when the sensing period is finished, wherein the DCELL x is the x th delay cell, where 0<x≦n, and the sensing period is decided by a signal from the reset terminal; wherein at least an output terminal t y of a delay cell DCELL y , among the delay cells DCELL 1 ˜DCELL n used as output terminal of the delay line, where 0<y≦n; and wherein the delay cell DCELL x comprises: a first current source for deciding the supplied current value according to a signal of the delay-control terminal; a second current source for deciding the supplied current value according to a signal of the delay-control terminal; a third current source for deciding the supplied current value according to a signal of the delay-control terminal; a fourth current source for deciding the supplied current value according to a signal of the delay-control terminal; a first inverter coupled between the first current source and the second current source to obtain power, for inverting and output the signal of input terminal of the first inverter in the sensing period and resetting the output of the first inverter to the second level after the sensing period is finished according to the signal from the reset terminal, wherein an input terminal of the first inverter is coupled to an output of a delay cell DCELL x-1 of the preceding stage; and a second inverter coupled between the third current source and the fourth current source to obtain power, wherein an input terminal of the second inverter is coupled to the output terminal of the first inverter, and an output terminal of the second inverter serves as the output of the delay cell DCELL x of the current stage.