Patent ID: 7125747

Claim:
A process for manufacturing a plurality of leadless semiconductor packages, comprising: providing a leadless leadframe having a packaging matrix, the packaging matrix having a plurality of units and a plurality of connecting bars, wherein each unit has a plurality of leads connected to the connecting bars, a plated metal layer is formed on the upper surfaces of the leads and the upper surfaces of the connecting bars; disposing a plurality of chips in the units; wire-bonding the chips and the leads of the leadless leadframe; forming an encapsulant on the packaging matrix of the leadless leadframe to cover the chips and the plated metal layer on the upper surfaces of the leads and the connecting bars; removing portions of the connecting bars to form a plurality of grooves corresponding to the connecting bars; performing a first sawing step to cut out the plated metal layer in the grooves; probing the lower surfaces of the leads after performing the first sawing step for electrically testing the packaged chips; and performing a second sawing step after the electrical testing, the encapsulant being cut along the grooves to form a plurality of individual package bodies of the leadless semiconductor packages.