Patent ID: 7554373

Claim:
A pulse width modulation circuit, comprising: a multiphase clock generation section generating a multiphase clock signal according to a reference clock; and a pulse width modulation signal generation section generating a pulse width modulation signal according to input data and the multiphase clock signal generated by the multiphase clock generation section, by selecting an arbitrary clock signal from the multiphase clock signal in accordance with said input data, wherein the multiphase clock generation section comprises a phase lock loop circuit and generates the multiphase clock signal by phase-interpolating an intermediate clock signal generated by the phase lock loop circuit, wherein the pulse width modulation signal generation section comprises: a clock selection circuit selecting the arbitrary clock signal from the multiphase clock signal generated by the multiphase clock generation section according to the input data; and a pulse width modulation signal generation circuit generating a pulse width modulation signal according to the clock signal selected by the clock selection circuit, wherein the clock selection circuit includes a first decoder decoding part of input data, a second decoder decoding another part of the input data, a first selector selecting a plurality of clock signals from the multiphase clock signal according to the data decoded by the first decoder, and a second selector selecting an arbitrary clock signal from the plurality of clock signals selected by the first selector according to the data decoded by the second decoder.