Patent ID: 8461886

Claim:
A phase locked loop comprises: a phase frequency detector (PFD) configured to: receive a reference clock signal and a feedback clock signal, output a first signal, which includes first phase information for a rising edge of the reference clock signal, and a second signal, which includes second phase information for a rising edge of the feedback clock signal; a logic gate including an AND gate with an inverted input and a non-inverted input, wherein one of the first signal or the second signal from the PFD is coupled to the inverted input and the other signal is coupled to the non-inverted input, wherein the AND gate is configured to logically combine the first signal and the second signal to produce a pulse signal having a rising edge, which includes the first phase information, and a falling edge, which includes the second phase information; a time to digital converter (TDC) coupled the logic gate wherein the pulse signal output from the AND gate is input to the TDC, and wherein the TDC is configured to generate a digital timing signal, which includes timing information for a phase difference of the first and the second phase information; and a controlled oscillator coupled to the TDC and configured to vary or maintain a frequency of the feedback clock signal from the digital timing signal.