Patent ID: 6944737

Claim:
A memory module, comprising: at least one memory device responsive to a memory clock signal having a memory clock frequency; and a data buffer responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation, wherein the data buffer comprises: a write circuit, comprising: a plurality of write registers responsive to a rising and/or falling edge of the first buffer clock signal; a plurality of write control buffers that transmit a plurality of write signals from the plurality of write registers; a write switch that couples and/or decouples the plurality of write control buffers responsive to a test enable signal; a plurality of write delay units that delay the plurality of write signals; and a plurality of write selectors that select a first of the plurality of write delay units during the normal mode of operation and select a second of the plurality of write delay units during the test mode of operation; and a read circuit, comprising: a plurality of read delay units that receive a plurality of read signals from the plurality of memory devices; a plurality of read selectors that select a first of the plurality of read delay units during normal mode of operation and select a second of the plurality of read delays units during test mode of operation; a plurality of read control buffers that transmit the plurality of read signals from the plurality of read selectors; a read switch that couples and/or decouples the plurality of read control buffers in response to the test enable signal; and a plurality of read registers that receives the plurality of read signals from the plurality of read control buffers responsive to the rising edge and/or the falling edge of the first buffer clock signal.