Patent ID: 7436221

Claim:
A differential leakage canceling analog storage cell circuit having a sample phase and a hold phase, comprising: a signal receiving terminal; a reference voltage source; a first switch having a first terminal coupled to the signal receiving terminal and a second terminal; a second switch having a first terminal coupled to the second terminal of the first switch and a second terminal; a first sampling capacitor having a first end coupled to the second terminal of the first switch and a second end; a second sampling capacitor having a first end coupled to a voltage source and a second end; a leakage canceling transistor having gate, source, drain and bulk terminals and a residual leakage between the source and bulk terminals and having the drain and bulk terminals connected to the reference voltage source and having the source terminal connected to the second end of the second sampling capacitor; an amplifier having first and second input terminals and an output terminal, the first input terminal coupled to the second end of the second sampling capacitor and the source terminal of the leakage canceling transistor, the second input terminal coupled to the second end of the first sampling capacitor, and the output terminal being coupled to the second end of the second switch and the second end of the first sampling capacitor via a switch structure; wherein the switch structure includes: a core transistor having gate, source, drain and bulk terminals and a residual leakage between the source and bulk terminals and having the bulk terminal connected to the reference voltage source and having the source terminal connected to the second end of the first sampling capacitor and the second input terminal of the amplifier; a disconnect switch coupled to the drain of the core transistor and to the amplifier output terminal to selectively disconnect the core transistor drain from the amplifier output terminal during the hold phase; and a connect switch coupled to the drain of the core transistor and to the reference voltage source to connect the drain of the core transistor to the reference voltage source during the hold phase, wherein the residual leakage of the leakage canceling transistor into the second sampling capacitor substantially cancels the residual leakage of the core transistor into the first sampling capacitor.