Patent ID: 7746701

Claim:
A memory device, comprising: a first memory cell array comprising a plurality of memory cells arranged in rows and columns, each of the columns including respective bit lines to which the memory cells in the column are selectively coupled; a second memory cell array comprising a plurality of memory cells arranged in rows and columns, each of the columns including respective bit lines to which the memory cells in the column are selectively coupled; a row decoder operable to receive a row address and to select a corresponding row of the memory cells in one of the first and second memory cell arrays in response thereto; a column decoder operable to receive a column address and to select a corresponding column of the memory cells in one of the first and second memory cell arrays in response thereto; a pre-charge unit positioned between the first and second memory cell arrays, the pre-charge unit being operable to pre-charge at least some of the bit lines in at least one of the first and second memory cell arrays; and a data register selectively coupled to the bit lines in the first and second memory cell arrays, the data register being positioned at a location other than between the first and second memory cell arrays and being operable to route read data from the bit lines to external data terminals and to route write data from the external data terminals to the bit lines.