Patent ID: 6927994

Claim:
A ferroelectric memory device comprising: a plurality of word lines disposed in parallel; a plurality of bit lines disposed in parallel so as to intersect the word lines; a plurality of ferroelectric memory cells disposed at respective intersecting points of the word lines and the bit lines; a word line driver section which drives the word lines; a bit line driver section which drives the bit lines; a first voltage supply line and a second voltage supply line which are connected with the word line driver section, the first voltage supply line being used for a selected word line among the word lines, and the second voltage supply line being used for an unselected word line among the word lines; a third voltage supply line and a fourth voltage supply line which are connected with the bit line driver section, the third voltage supply line being used for a selected bit line among the bit lines, and the fourth voltage supply line being used for an unselected bit line among the bit lines; a power supply circuit which generates a plurality of types of voltages; and a voltage select circuit which selectively outputs the plurality of types of voltages generated by the power supply circuit to the first voltage supply line, the second voltage supply line, the third voltage supply line, and the fourth voltage supply line, wherein the word line driver section and the bit line driver section apply a select voltage to a selected memory cell among the ferroelectric memory cells, and apply an unselect voltage to a remaining unselected memory cell among the memory cells, and wherein the voltage select circuit fixes a potential of one of the second voltage supply line and the fourth voltage supply line when the select voltage is applied to the selected memory cell.