Patent ID: 7948012

Claim:
A layout of an integrated circuit device, comprising: a diffusion level layout portion including a number of diffusion region layout shapes to be formed within a portion of a substrate; a gate electrode level layout portion defined to pattern conductive features within a gate electrode level over the portion of the substrate corresponding to the diffusion level layout portion, wherein the gate electrode level layout portion corresponds to a circular area on the integrated circuit having a radius of up to about 1965 nanometers and oriented substantially parallel to the substrate, the gate electrode level layout portion including a plurality of linear-shaped layout features placed to extend lengthwise in a first direction so as to extend parallel to each other, wherein at least four of the plurality of linear-shaped layout features within the gate electrode level layout portion are defined to include one or more gate electrode portions which extend over one or more of the number of diffusion region layout shapes to form respective transistor devices, and wherein at least one of the plurality of linear-shaped layout features does not include a gate electrode portion that forms a gate electrode of a transistor device.