Patent ID: 8283955

Claim:
An electronic circuit for a double data rate interface arranged between a processor and random access memory, the electronic circuit comprising: an element that creates a first delay in a first data strobe signal from the random access memory and a second delay in a second data strobe signal from the random access memory, wherein the first and the second data strobe signal are each others complement, the electronic circuit being arranged such that the respective delays in the respective data strobe signals are equal to a sum of a set-up time and a data bus rise time, wherein the electronic circuit further comprises: a controller, a first slave delay line for delaying the first data strobe signal with the first delay, a second slave delay line for delaying the second data strobe signal with the second delay, wherein the first slave delay line and the second slave delay line comprise variable delay line elements that are also controlled by the controller, and a delay-locked loop, wherein the delay-locked loop comprises a terminal for receiving a clock signal, a delay line coupled to the terminal for delaying the clock signal to obtain a delayed clock, wherein the delay line comprises a plurality of variable delay line elements, the delay-locked loop further comprising: i) a phase comparator for comparing the delayed clock with the clock signal, and ii) the controller for controlling respective delays of the plurality of variable delay line elements to obtain a phase difference between of clock signal and the delayed clock of one clock period of the reference clock, and wherein the first and second delays of the plurality of delay line elements of the respective slave delay lines is matched with the sum of the set-up time and data bus rise time.