Patent ID: 6959426

Claim:
A method for scan design architecture with non-scan testing cost, said method comprising: transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; connecting said plurality of sequential cells with at least one shifter registers; obtaining at least one scan chains; substituting an auto test pattern generation (ATPG) step for said sequential circuit with an ATPG for said combinational circuit; providing a scan forest architecture wherein each sequential cell (scan flip-flop) is a node; using primary inputs (SI 1 . . . SI k ) of said sequential circuit as root nodes of scan trees in the scan forest thus said root nodes work as scan-in signals to load test vectors when the sequential circuit is under test mode; connecting one group of the scan flip-flops to each primary input according to the principle that every two scan flip-flops in the same group do not converge in a circuit structure; forming a first level of the scan forest by the groups of the scan flip-flops; selecting a certain scan flip-flop for each group of the first level to be a predecessor of one group of the next level; and repeating the above steps until all scan flip-flops are connected with the scan forest.