Patent ID: 8102884

Claim:
A Network On a Chip (NOC), the NOC comprising: a first processing node in the NOC, wherein the NOC comprises multiple processing nodes, multiple routers, multiple communication controllers, and multiple network interface controllers, wherein each of the multiple processing nodes is coupled to one of the multiple routers through a dedicated memory communications controller from the multiple communication controllers, wherein each of the multiple communication controllers controls communications between the multiple processing nodes and an off-chip memory, and wherein each of the multiple network interface controllers controls inter-processing node communications through the multiple routers; at least one execution unit within the first processing node; a Compressed Direct Inter-thread Communications Buffer (CDICB) coupled to the processing node, wherein the CDICB is populated with operands from an Uncompressed Direct Inter-thread Communication Buffer (UDICB) that comprises at least one empty buffer cell between at least two operands that are stored in the UDICB, and wherein the UDICB and the CDICB contain multiple different operand aggregates; a multiplexer (MUX) Special Purpose Register (SPR) coupled to the CDICB and the first processing node, wherein the MUX SPR stores MUX control data; and a MUX controller coupled to the MUX SPR and a first set of MUXs within the first processing node, wherein the MUX controller utilizes the MUX control data from the MUX SPR and the first set of MUXs to realign original operands retrieved from the CDICB by the first processing node, wherein the realigned original operands are organized by data rows in an organization format that is required by an execution unit architecture for supplying operands to said at least one execution unit.