Patent ID: 8111538

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells which are set into low-resistance states/high-resistance states according to “0” data/“1” data; a timer circuit configured to generate a pulse at each preset time, a plurality of flag cells provided for a plurality of memory cell strings each of which comprises a preset number of memory cells among the plurality of memory cells; and a write circuit, wherein an allocation of the “0” data/“1” data and the low-resistance state/high-resistance state is switched each time the pulse is generated, the flag cells are configured to store allocation information of the “0” data/“1” data and the low-resistance state/high-resistance state, and the write circuit is configured to rewrite data of a memory cell string to inverted data obtained by inverting the data of the memory cell string based on the allocation information stored in the flag cells when the memory cell string is first accessed after the allocation is switched.