Patent ID: 7515002

Claim:
In a portable dual mode receiver circuit, a clock system comprising: a baseband clock circuit; a multiplier circuit coupled to the baseband clock circuit for multiplying a baseband clock by a multiplier value to a master clock frequency which has as factors a first integer divider value of a first channel spacing clock signal of a first band, and a second integer divider value of a second channel spacing clock signal of a second band; a programmable reference divider coupled to receive a clock signal of said master clock frequency, said programmable divider selectively dividing said master clock frequency by said first integer divider value of said first band or by said second integer divider value of said second band to produce respectively said first channel spacing clock signal and said second channel spacing clock signal; a voltage controlled oscillator (VCO) coupled to receive a phase error signal for generating a frequency controlled analog radio frequency (RF) signal at a desired frequency for system output; a programmable VCO divider circuit coupled to receive said analog RF signal, said programmable VCO divider circuit dividing a frequency of said analog RF signal by a first channel integer when said programmable reference divider produces said first channel spacing clock signal, and dividing the frequency of said analog RF signal by a second channel integer when said programmable reference divider produces said second channel spacing clock signal, and producing a digital feedback signal; and, a digital phase detector coupled to receive an output of said programmable reference divider to detect phases of said first channel spacing clock signal and said second channel spacing clock signal, said digital phase detector also having as a reference input the digital feedback signal, said digital phase detector producing as an output an analog phase error signal in a form of a steering voltage.