Patent ID: 8081534

Claim:
A semiconductor memory device, comprising: a local line driving block configured to differentially drive a positive local line and a negative local line by selectively inverting data on a global line according to row addresses; a global line driving block configured to drive the global line by selectively inverting data on the positive local line and data on the negative local line according to the row addresses; a first cell region configured to allow a first internal data to be equalized with the data on the positive local line in response to column addresses and the row addresses; and a second cell region configured to allow a second internal data to be equalized with the data on the negative local line in response to the row addresses and the column addresses, wherein the local line driving block includes: a global data inversion control unit configured to selectively invert the data on the global line in response to the row addresses: and a global data driving unit configured to differentially drive output data of the global data inversion control unit to the positive local line and the negative local line.