Patent ID: 7677931

Claim:
A method of reducing port to port crosstalk on a multiport assembly comprising: placing at least one BEMI in at least one compensation region, disposed on a PCB, said BEMI being adapted to reduce port to port crosstalk noise by generating an opposite polarity signal to an unwanted noise signal generated through port to port adjacency; wherein said PCB includes a plurality of ports, said plurality of ports at least including a first port and a second port, said first port and said second port being disposed adjacent to each other; wherein each port of said plurality of ports includes a plurality of modular insert pins, and is associated with an IDC pin group; wherein said at least one compensation region includes one selected from the group consisting of: (a) a first region generating noise compensation with respect to crosstalk noise that results from coupling between at least one modular insert pin of said first port and at least one IDC pin associated with said second port, (b) a second region generating noise compensation with respect to crosstalk noise that results from coupling between at least one modular insert pin of said first port and at least one modular insert pin of said second port, (c) a third region generating noise compensation with respect to crosstalk noise that results from coupling between at least one IDC pin associated with said first port and at least one modular insert pin of said second port, and (d) a combination thereof; and wherein each of said first port and said second port is an RJ45 jack port, and each of said plurality of modular insert pins of said first port and said plurality of modular insert pins of said second port comprises respective first, second, third, fourth, fifth, sixth, seventh, and eighth modular insert pins mounted to said PCB such that the corresponding pluralities of modular insert pins form similar respective two-row arrays, an upper row of which including, in sequence, said second, fourth, sixth, and eighth modular insert pins, a lower row of which including, in sequence, said first, third, fifth, and seventh modular insert pins, a leftmost column of which including said first modular insert pin and said second modular insert pin, and a rightmost column of which including said seventh modular insert pin and said eighth modular insert pin.