Patent ID: 8881233

Claim:
A system comprising: a processor; and a memory coupled to the processor, the memory having stored thereon executable instructions that when executed by the processor cause the processor to effectuate operations comprising: maintaining by a federated clock service at least a first time domain using a first representation of time relative to real time and a second time domain using a second representation of time relative to real time, wherein the first time domain is used to manage one or more resources utilized by one or more of a first plurality of devices assigned to the first time domain, and the second time domain is used to manage one or more resources utilized by one or more of a second plurality of devices assigned to the second time domain; interacting by a resource utilization coordinator with the federated clock service to alter at least one time base in at least one of the first time domain or the second time domain in order to alter a rate at which at least one resource is utilized; sequencing, using a sequencer interacting with the first time domain, timing events for the first time domain; and sequencing, using the sequencer interacting with the second time domain, timing events for the second time domain; wherein the federated clock service includes a timekeeper service that is used to place at least one of the first or the second time domain in a paused state relative to real time.