Patent ID: 7324561

Claim:
A circuit for generating an output oscillation signal with low jitter, the circuit comprising: an oscillator configured to generate an initial oscillation signal at an initial frequency, the oscillator having a control input to vary an amplitude of the initial oscillation signal; a first frequency multiplier configured to multiply the initial frequency of the initial oscillation signal to result in a first signal with first frequency and first undesired frequency components; a filter configured to minimize the first undesired frequency components of the first signal; a second frequency multiplier configured to multiply the first signal to result in the output oscillation signal with second frequency and second undesired frequency components; a second feedback circuit configured to compare a predetermined range and at least one of the first signal and the output oscillation signal to result in a reference value; and a first feedback circuit configured to vary the control input based upon a comparison between the reference value and the amplitude of the initial oscillation signal to minimize the second undesired frequency components.