Patent ID: 7541640

Claim:
A method of forming a semiconductor device, comprising: forming a vertical field-effect transistor, including: forming a heavily doped substrate, forming a channel layer above said heavily doped substrate, forming a heavily doped source/drain layer above said channel layer, forming a source/drain contact above said heavily doped source/drain layer, patterning and etching pillar regions through said source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell, forming non-conductive regions in said portions of said channel layer within said pillar regions, and forming a gate above said non-conductive regions in said pillar regions; and forming a Schottky diode, including: forming a trench through said heavily doped substrate to said channel layer outside of said vertical cell and said pillar regions, and forming a contact below said heavily doped substrate within said vertical cell and pillar regions and within said trench, said contact within said vertical cell and pillar regions providing another source/drain contact for said vertical field-effect transistor, said contact within said trench providing an anode configured to cooperate with said channel layer that provides a cathode for said Schottky diode.