Patent ID: 8488699

Claim:
A physical layer device comprising: a plurality of ports, wherein each port of the plurality of ports is programmable to receive a waveform of a grandmaster clock; and a clock synchronization module configured to i) receive the waveform of the grandmaster clock from a first port of the plurality of ports, the first port having been programmed to receive the waveform of the grandmaster clock, and ii) clean up the waveform of the grandmaster clock, wherein cleaning up the waveform of the grandmaster clock includes one or more of removing jitter from the waveform of the grandmaster clock, controlling a voltage swing of the waveform of the grandmaster clock, or establishing fixed edge rates of the waveform of the grandmaster clock, and wherein, in response to the first port being programmed to receive the waveform of the grandmaster clock, other ones of the plurality of ports are programmed to receive the waveform of the grandmaster clock, as cleaned up by the clock synchronization module, for use when transmitting data.