Patent ID: 7452756

Claim:
A process for manufacturing a semiconductor device, comprising: providing a semiconductor substrate of a first conductivity type, having upper and lower surfaces; forming a collector region of a second conductivity type on the lower surface of said semiconductor substrate; forming at least one pair of isolation regions of the second conductivity type extending from the upper surface of said semiconductor substrate to said collector layer for defining a drift region of the first conductivity type, in conjunction with said collector region; forming a base region of the second conductivity type adjacent the upper surface of said semiconductor substrate and within the drift region; forming an emitter region of the first conductivity type adjacent the upper surface of said semiconductor substrate and within said base region; forming a gate electrode opposing to said base region via an insulating layer; and forming an emitter electrode on said emitter region; polishing said collector region to have thickness in the range between 17 μm to 50 μm, after forming said gate electrode and said emitter electrode; and forming a collector electrode on said polished collector region.