Patent ID: 8253583

Claim:
An indicator system operable in an alarm state, the system comprising: at least one sensor configured to detect a condition; a signal processing circuit in communication with the at least one sensor, the signal processing circuit being configured to generate a signal in the alarm state, wherein the signal processing circuit generates a voltage at a signal processing circuit output (PIN); a control circuit comprising: semiconductor switch (T 1 ) including a control input connected to the processing circuit output (PIN), a load circuit in electrical communication with the processing circuit output (PIN), the load circuit comprising: a freewheeling diode (D 1 ) connected in parallel with a series circuit including an inductor (L 1 ) and a light emitting diode (LED), and a first, current measuring resistor (R 1 ) configured to generate a current-proportional voltage applied to an input of the control circuit to generate a clocked control signal for the semiconductor switch (T 1 ); a transistor (T 2 ) including a base and a collector connected to the signal processing circuit output (PIN) via a second resistor (R 2 ), the transistor (T 2 ) delivering the clocked control signal for the semiconductor switch (T 1 ) as a function of the current-proportional voltage applied to the transistor base; and a further transistor (T 3 ) including: a collector connected to the control input of the semiconductor switch (T 1 ), and a base connected to the collector of the transistor (T 2 ) configured to deliver the clocked control signal, wherein: the semiconductor switch (T 1 ) is connected between a supply voltage and an input to the load circuit, the supply voltage is supplied via a two-core line or from an installed battery, a clamp diode (D 2 ) connects a load-side terminal of the semiconductor switch (T 1 ) to an output of the control circuit, the indicator system is configured to communicate with a control center via the two-core line or wirelessly, the semiconductor switch (T 1 ) comprises a switching transistor including a base connected as a control input to the collector of the further transistor (T 3 ) via a third resistor (R 5 ) and an emitter connected via a fourth resistor (R 6 ) to the base, and wherein the ratio of the resistances of the third and fourth resistors is selected such that the switching transistor remains blocked at a supply voltage which is less than a predefined lower limiting value to deactivate the control circuit.