Patent ID: 7543096

Claim:
A fault-tolerant mass storage system, comprising: first and second RAID controllers, coupled for communication via a PCI-Express link, each comprising: a bus bridge, coupled to said link and to first and second buses; a cache memory, coupled to said first bus, configured to cache user data for storage on disk drives controlled by said controllers; and a CPU, and a CPU memory coupled to said CPU, each coupled to said second bus, wherein said CPU is configured to fetch and execute program instructions from said CPU memory, wherein said CPU is configured to program said bus bridge with window information defining a window of locations within said CPU memory, wherein said window comprises less than an entirety of said CPU memory; wherein said bus bridge is configured to receive data on said link from the other of said first and second RAID controllers, to write said data to said CPU memory if destined for said CPU memory, but only within said window and nowhere else within said CPU memory, and to write said data to said cache memory if destined for said cache memory, wherein said bus bridge is configured to refrain from writing said data to said CPU memory outside of said window even if said bus bridge determines that a portion of said data is destined for said CPU memory within said window.