Patent ID: 7302505

Claim:
A multi-protocol interface comprises: a wide bandwidth amplifier operable to amplify a first formatted input signal or a second formatted input signal to produce an amplified input signal; a data sampling module, coupled to the wide bandwidth amplifier, that converts the amplified input signal into a first parallel data stream having a first word size in accordance with at least one first sampling clock signal when the multi-protocol interface is in a first operational mode and to convert the amplified input signal into a second parallel data stream having a second word size in accordance with at least one second sampling clock signal when the multi-protocol interface is in a second operational mode, wherein the data sampling module includes: a latch module, coupled to the wide bandwidth amplifier, that samples the amplified input signal in accordance with the at least one first sampling clock signal when the multi-protocol interface is in the first operational mode or in accordance with the at least one second sampling clock signal when the multi-protocol interface is in the second operational mode to produce signal samples; a double data rate to single data rate module, coupled to the latch module, that converts the signal samples into a first series of signal samples and a second series of signal samples; and a buffer, coupled to the double data rate module, wherein the first and second series of signal samples are written into the buffer and wherein the first and second series of signal samples are retrieved from the buffet as the first data stream when the multi-protocol interface is in the first operational mode and retrieved from the buffer as the second data stream when the multi-protocol interface is in the second operational mode; and a clocking module, coupled to the data sampling module and a reference clock, that generates the at least one first sampling clock signal from the reference clock when the multi protocol interface is in the first operational mode and to generate the at least one second sampling clock signal based on the reference clock when the multi-protocol interface is in the second operational mode.