Patent ID: 7710300

Claim:
A digital to analog converter (DAC) module configured to convert a digital input signal to an analog output signal, comprising: a primary sigma-delta modulator configured to reduce a resolution of the digital input signal from a first number of bits to a second number of bits to produce a primary digital segment and a primary quantization error, the second number of bits being less than the first number of bits; a primary scrambler configured to scramble the primary digital segment to provide a primary scrambled digital signal using a first number of butterfly circuits; a primary DAC configured to convert the primary scrambled digital signal from a digital representation to an analog representation to provide a primary analog segment; a secondary scrambler configured to scramble the primary quantization error to provide a secondary scrambled digital signal using a second number of butterfly circuits, the second number of butterfly circuits being equal to the first number of butterfly circuits; and a secondary DAC configured to convert the secondary scrambled digital signal from a digital representation to an analog representation to provide a secondary analog segment; an adder configured to combine the primary scrambled digital signal and the secondary scrambled digital signal to produce the analog output signal.