Patent ID: 7088792

Claim:
A device for decoding and error-checking data that have been encoded with a convolutional code, said device comprising: (a) a receiver which is configured to receive: (i) data having been used to generate a cyclic redundancy code (CRC) and then encoded with a convolutional code, and (ii) the CRC for the data; (b) a decoder which is configured to decode the data in order to remove the convolutional code and output the data in time-reversed order; (c) a cyclic redundancy check circuit which includes a plurality of serially connected linear feedback shift registers, collectively having a state; and (d) a plurality of feedback paths, each leading to an input of one of the linear feedback shift registers, wherein the cyclic redundancy check circuit is configured: (i) to initialize the state of the linear feedback shift registers to the CRC; (ii) upon completion of said initialization, to receive and process the data from the decoder in time-reversed order; and (iii) such that upon completion of said processing of said data, if no errors are present in the data, the state of the plurality of linear feedback shift registers is equal to a fixed initial state, and wherein a set of multipliers corresponding to a set of coefficients is interposed in the feedback oaths such that when data are shifted through the feedback shift registers, the device performs division by x for an input bit equal to 0, and, for an input bit equal to 1, performs division by x and then adds x k+m−1 , where x is a variable of a generating polynomial g(x)=g k x k +g k−1 x k−1 + . . . +g 1 x+g 0 , k is the highest order of the generating polynomial, and m is the total number of input bits to be decoded.