Patent ID: 7444529

Claim:
A microcomputer comprising: a rewritable nonvolatile memory, which has a power source circuit forming a power source for own operation thereof based on a power source fed from an external unit, and stores a control program; a clock control circuit, which is so constructed as to selectively produce first clock signals that start relatively quickly from an oscillation halt state and have a relatively low oscillating precision and second clock signals that start relatively delayed from the oscillation halt state and have a relatively high oscillating precision, at least the second clock signals being produced using an oscillation output of an external oscillator as reference clock signals; and a CPU, which receives the clock signals produced by the clock control circuit and operates upon reading out the control program from the nonvolatile memory; wherein the CPU discontinues an oscillating operation of at least the second clock signals in the clock control circuit when the CPU is shifted to a low power consumption mode; the power source circuit of the nonvolatile memory is so constructed to interrupt the external power source when the CPU is shifted to the low power consumption mode and resume supply of the external power source when the low power consumption mode is reset; the control program read by the CPU when the low power consumption mode is reset is partly pre-arranged in a start memory which is capable of reading data at a time point when the low power consumption mode is reset; the clock control circuit resumes, when the low power consumption mode is reset, the oscillating operation for oscillating at least the second clock signals, feeds to the CPU the first clock signals of which the oscillation is in a stable state for only a predetermined period of time and, thereafter, feeds the second signals instead thereto; and the CPU reads the control program arranged in the start memory when started as a result of resetting the low power consumption mode.