Patent ID: 8687799

Claim:
A data processing circuit for performing processing related to encryption on data, comprising: processing means for performing processing related to encryption on the data; timing means for supplying a master clock; delaying means for supplying a delay clock; noise generating means for generating noise; superimposing means for superimposing the noise generated by the noise generating means on a current consumed by the processing means; and timing signal generating means for generating a timing signal indicating a timing at which the noise generated by the noise generating means is superimposed on the current consumed, wherein the processing means performs the processing in synchronization with the supplied master clock; wherein the delaying means supplies the delay clock by delaying the master clock by a delay period of time corresponding to a processing period of time for which the data is encrypted by the processing means; wherein the timing signal generating means generates the timing signal according to the delay clock supplied by the delaying means; and wherein the delay period of time is set such that the timing signal is set to a first logical level in the vicinity of a beginning of the processing period of time and a second logical level otherwise.