Patent ID: 7631138

Claim:
In a memory system having non-volatile memory cells arranged in blocks as a unit of erase, pages therein as a unit of data programming and reading, and planes of a plurality of blocks that are independently accessible, a method of operation of the memory system, comprising: logically forming metablocks that individually include blocks from a plurality of the planes, sequentially receiving write commands with a varying number of units of data and logical addresses of the individual units of data, determining from the write commands whether (1) a given one or more units of data having consecutive logical addresses are being received or (2) more than said given number of one or more units of data having consecutive logical addresses are being received, and writing all the data received with individual write commands by (1), in response to determining that the given one or more units of data having consecutive logical addresses are being received, writing the given one or more units of data into at least one page within at least one of the blocks of only one of the planes, and (2), in response to determining that more than said given number of one or more units of data having consecutive logical addresses are being received, writing the more than said given number of units of data in parallel into pages within two or more blocks of one of the metablocks in two or more planes.