Patent ID: 8030761

Claim:
A chip package comprising: a carrier having a first and a second major surface, wherein the first major surface comprises an active region surrounded by an inactive region; contact pads in the active region for mating with chip contacts of a chip; a support structure disposed on the inactive region of the first major surface, wherein the support structure forms a dam surrounding the active region; a chip stack comprising n number of chips disposed in the active region, wherein a n th chip is stacked on top of a n th −1 chip, and contacts of the n th chip are coupled to contact pads on a top surface of the n th −1 chip; spacing around the chip stack between the dam and the chip stack, wherein the spacing creates convection paths to dissipate heat; and chip stabilizers in the spacing, wherein the chip stabilizers contact the chip stack and dam to stabilize the chip stack without completely filling the spacing to maintain the convection paths to dissipate heat.