Patent ID: 8324043

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a first active region for a P-channel field-effect transistor in a substrate; forming a second active region for an N-channel field-effect transistor in the substrate; forming a first gate stack on the first active region; forming a second gate stack on the second active region; forming a first layer on the first active region in a region where the first gate stack is not formed, forming a second layer on the second active region in a region where the second gate stack is not formed, the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer; forming an interlayer insulating film to cover upper regions of the first and second gate stacks and the first and second layers; forming a first contact hole in the interlayer insulating film, the first contact hole including a first lower region exposing the SiGe epitaxial layer of the first layer; forming a second contact hole in the interlayer insulating film, the second contact hole including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer; forming a first metal silicide film including germanium (Ge) in the first lower region; forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film; and forming contact plugs on the first and second metal silicide films in the first and second contact holes.