Patent ID: 8115727

Claim:
A system for displaying image, comprising: a digital data sampling circuit with N stage data inputs; wherein N is an integer number greater than 2, comprising: a first stage flip-flop outputting a first output signal; a second stage flip-flop outputting a second output signal; a (K−1)th stage flip-flop outputting a (K−1)th output signal; a Kth stage flip-flop outputting a Kth output signal; a first stage sample latch circuit receiving digital data according to a first control signal; a second stage sample latch circuit receiving the digital data according to a second control signal; a K stage sample latch circuit receiving the digital data according to a Kth control a first stage logic circuit comprising a first inverter inverting one of the first output signal and the second output signal to generate a first inverse logic signal, and generating the first control signal according to another one of the first and the second output signal and the first inverse logic signal; and a second stage logic circuit generating the second control signal according to the first output signal and the second output signal; and a Kth stage logic circuit generating the Kth control signal according to the (K−1)th output signal and the Kth output signal without via any inverter when K is not equal to 1 nor N; only the first and the last AND logic gate in the stage logic circuit are directly connected to the respective inverters.