Patent ID: 7532189

Claim:
A display comprising: a plurality of drain and gate lines which are arranged so as to intersect each other; first and second pixel portions, each of which includes subsidiary capacitances having a first electrode which is connected to a pixel electrode and a second electrode, arranged adjacent to each other along the same gate line; a first subsidiary capacitance line which is connected to said second electrode of said subsidiary capacitance of said first pixel portion and a second subsidiary capacitance line which is connected to said second electrode of said subsidiary capacitance of said second pixel portion, the first and second subsidiary capacitance lines being provided corresponding to one of the plurality of gate lines; and a signal providing circuit including a plurality of signal providing circuit portions which provide a first signal with a first voltage supply source and a second signal with a second voltage supply source to the first subsidiary capacitance line of said first pixel portion and the second subsidiary capacitance line of said second pixel portion, respectively, wherein one of said signal providing circuit portions is provided to every one of said plurality of gate lines or every two or more of said plurality of gate lines, and respective said signal providing circuit portions provide said first and second signals to said first and second subsidiary capacitance lines of said gate lines corresponding thereto, respectively, and said first signal is provided to said first subsidiary capacitance line and said second signal is provided to said second subsidiary capacitance line in one frame period, and said second signal is provided to said first subsidiary capacitance line and said first signal is provided to said second subsidiary capacitance line in the next one frame period.