Patent ID: 8692623

Claim:
A relaxation oscillator circuit comprising: first and second clock generator subcircuits; and a control circuit configured to control the first and second clock generator subcircuits, wherein each of the first and second clock generator subcircuits comprises: a comparator having a non-inverted input terminal and an inverted input terminal; a first current-voltage converter circuit including a first capacitor having a grounded first electrode and a second electrode, the first current-voltage converter circuit outputting, as a first output voltage, a voltage of the second electrode of the first capacitor upon charging the first capacitor with a first constant current; a multiplexer configured to output one of the first output voltage and a predetermined reference voltage, to the non-inverted input terminal of the comparator; and a second current-voltage converter circuit including a second capacitor having first and second electrodes, the first electrode being connected to a power source that outputs a predetermined power voltage and a second electrode, wherein the second current-voltage converter circuit outputs, as a second output voltage, a voltage of the second electrode of the second capacitor upon discharging the second capacitor with a second constant current, to the inverted input terminal of the comparator, wherein, for an interval of generating a comparison voltage, the control circuit grounds the second electrode of the first capacitor, controls the multiplexer to output the reference voltage to the non-inverted input terminal of the comparator, discharges the second capacitor with the second constant current after resetting the second electrode of the second capacitor to a predetermined reset voltage that is higher than the reference voltage and equal to or lower than the power voltage, and holds the second output voltage when a level of an output signal from the comparator is inverted as a comparison voltage of the comparator, and wherein, for a clock generating interval, the control circuit controls the multiplexer to output the first output voltage to the non-inverted input terminal of the comparator, and charges the first capacitor with the first constant current until the level of the output signal from the comparator is inverted, wherein the control circuit controls the first and second clock generator subcircuits, so that one subcircuit of the first and second clock generator subcircuits operates for the interval of generating the comparison voltage, then another subcircuit operates for the clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the interval of generating the comparison voltage and the clock generating interval, and wherein the control circuit generates a clock based on output signals from the comparators of the first and second clock generator subcircuits.