Patent ID: 6949455

Claim:
A method for forming a semiconductor device structure in a semiconductor layer, comprising: forming a first region and a second region of opposite conductivity type in the semiconductor layer, the first region and the second region being electrically isolated by an isolation region; forming a control electrode dielectric overlying the first region and the second region; forming a silicon-containing layer overlying and in contact with the control electrode dielectric; doping a first portion of the silicon-containing layer with a first predetermined dopant material; doping a second portion of the silicon-containing layer with a second predetermined dopant material; depositing a metal layer overlying the silicon-containing layer; annealing the semiconductor device to form a first control electrode silicide in the first portion of the silicon-containing layer and to form a second control electrode silicide in the second portion of the silicon-containing layer; forming a first control electrode from the first control electrode silicide and forming a second control electrode from the second control electrode silicide; and completing formation of a first transistor using the first control electrode and completing formation of a second transistor using the second control electrode.