Patent ID: 8300457

Claim:
A non-volatile memory comprising: a plurality of non-volatile memory cells organized into a page of contiguous memory cells linked by a word line and each memory cell of the page is accessible by a bit line; a page of sensing circuit coupled to sense corresponding memory cells of said page of contiguous memory cells; a programming circuit for programming said page of contiguous memory cells in parallel to respective target states; a controller for controlling the programming circuit and the page of sensing circuits, said controller performing programming operations that comprises: sensing said page of contiguous memory cells in parallel to verify said page of memory cells relative to respective target states by sensing currents flowing through each memory cell of the page, wherein each memory cell is coupled to a bit line and wherein the bit line voltage of each said bit line is controlled to be constant during sensing; inhibiting said each memory cell that has been verified among said page; applying a programming pulse to said page of contiguous memory cells; and repeating the programming operations until all memory cells of said page have been verified.