Patent ID: 8017494

Claim:
A method of fabricating a power semiconductor device, comprising: covering a surface of a semiconductor body with a mask body wherein said mask body is not separated from said semiconductor body by an oxide layer; removing portions of said mask body to define openings extending to said semiconductor body; creating a plurality of gate trenches and a plurality of laterally spaced termination trenches disposed around said gate trenches, said trenches being spaced from one another by mesas; oxidizing the bottom and sidewalls of said gate trenches and said termination trenches; depositing gate electrode materials inside said gate trenches and said termination trenches wherein said gate electrode materials are not deposited on a backside of said semiconductor body; etching back said gate electrode material to leave gate electrodes in said trenches and conductive spacers along sidewalls of said termination trenches; depositing a low density oxide over said gate electrodes and spacers; patterning said low density oxide to obtain a low density oxide body over each gate electrode over said spacers in said termination trenches; and depositing a metal layer atop said semiconductor body; and etching said metal layer to form at least a source contact which extends over at least one of said termination trenches.