Patent ID: 6878579

Claim:
A method of manufacturing a semiconductor device comprising: forming a first conductive type first diffusion layer in a second conductive type silicon substrate; forming sequentially a first oxide layer containing a first conductive type impurity, a second oxide layer, and a third oxide layer containing the first conductive type impurity on the first diffusion layer; patterning the first to third oxide layer to expose a part of the first diffusion layer; performing a selective crystal growth of silicon by using the exposed silicon portion as the seed to form a silicon layer on the exposed silicon portion; flattening the silicon layer by using chemical mechanical polishing; performing ion-implantation of a second conductive type impurity into the silicon layer; forming sequentially a first conductive second diffusion layer and a first insulating layer on the silicon layer and the third oxide layer; patterning the first insulating layer, the second diffusion layer, and the third oxide layer; forming a first conductive type third diffusion layer in the silicon layer to perform thermal treatment to execute solid phase diffusion of the first conductive type impurity into the silicon layer; forming a sidewall of an insulating material at a side portion of the third oxide layer, the second diffusion layer, and the first insulting layer; removing the second oxide layer to expose the silicon layer; depositing a polycrystalline silicon-germanium layer containing a first conductive type impurity on the entire surface in such manner that a germanium concentration is continuously increased from the lower portion of the silicon layer to the upper portion of the silicon layer; and patterning the polycrystalline silicon-germanium layer to form a gate electrode.