Patent ID: 7401316

Claim:
A method of designing a processor of an integrated circuit, comprising: identifying reusable portions of a custom design to be created for a processor; custom designing said processor to meet specific performance criteria, including: custom designing macros for said reusable portions including a first macro having an instruction pipeline function and a second macro having an instruction stream buffer function; specifying a number of instances of each macro including a number of instances of said first and second macros; and assembling said macros and providing interconnections for said macros including said first macro and a plurality of said second macros to form an instruction pipeline unit and a plurality of instruction stream buffers interconnected with said instruction pipeline unit, each of said instruction stream buffers being operable to buffer an instruction stream different from the instruction stream buffered in at least one other said instruction stream buffer, such that said instruction pipeline unit is operable to provide cycle-by-cycle multiple-threading.