Patent ID: 7392273

Claim:
A circuit in a floating point processor having fused multiply/add circuitry comprising: registers for receiving binary numbers B, A and C; a multiplier connected to receive binary numbers A and C to generate a product A*C; an aligner connected to receive said binary number B as an addend, said addend B having a fractional part and an exponent part, and said aligner aligning the addend fraction to the fraction of the product by shifting the fractional part of B by a predetermined amount of bits as given by a shift amount calculated separately; an adder connected to outputs of said multiplier and said aligner, said adder outputting a calculated sum; a pre-normalizer multiplexer for receiving a binary number output from said adder and for shifting said output for normalizing; a shift control input of said pre-normalizer multiplexer being connected to receive a control-signal reflecting Leading Zero Anticipation (LZA) information associated with said addend; a pre-normalizer control signal generation unit (PCSGU) connected to one of said registers for receiving said addend B, said pre-normalizer control signal generation unit determining the leading zero-count of the addend B and adding the leading zero-count to said shift amount, and controlling said pre-normalizer multiplexer, whereby said control:signal indicates that the sum is larger than a predetermined value.