Patent ID: 7467286

Claim:
A processor-implemented method comprising: receiving a single scalar packed data instruction, the scalar packed data instruction specifying locations in a 128-bit logical register file of a first 128-bit packed data operand and a second 128-bit packed data operand, each of the 128-bit packed data operands including a low-order segment and a high-order segment, and each of the segments including two 32-bit single precision floating point data elements; and storing, as a result of executing the single scalar packed data instruction within the processor, in a storage area specified by the scalar packed data instruction, a 128-bit packed data result operand, the 128-bit packed data result operand including a single data element that is a result of an operation selected from an add operation and a multiply operation performed on a single pair of corresponding data elements of the first and second 128-bit packed data operands, and the 128-bit packed data result operand including a plurality of other data elements having values that are not results of either add operations or multiply operations performed on pairs of corresponding data elements of the first and second 128-bit packed data operands.