Patent ID: 7054987

Claim:
An integrated circuit performing a bridge function, comprising: a front side bus interface unit disposed in said integrated circuit operative to act as an interface for a hyper-threaded central processing unit (CPU), said front side bus interface operative to initiate transactions with at least two units bridged to said integrated circuit, said front side bus interface unit executing a front side bus interface protocol having a request phase to receive a transaction request from said hyper-threaded CPU, a response phase for said integrated circuit to respond to said transaction request, and a data phase for a data transfer associated with an accepted transaction, said front side bus interface protocol being a pipelined protocol with an in-order transaction queue in which only one data phase of one transaction may proceed at any one time; and a posted write buffer for posting writes for at least one of said units, said posted write buffer having a maximum data capacity for queued posted writes beyond which a transaction request generating another posted write may be accepted but for which an associated data transfer phase is held up until said posted write buffer at least partially drains to accommodate said another posted write; said front side bus interface unit configured to monitor said posted write buffer and respond to a transaction request that would generate a new posted write exceeding a current remaining capacity of said posted write buffer with a retry response; wherein said integrated circuit has a mode of operation for said hyper-threaded CPU in which transaction requests of a thread that would schedule posted writes to a non-system memory which would stall completion of other transaction requests are retried at a later time by said integrated circuit to facilitate servicing another thread comprising a transaction request for reading a system memory.