Patent ID: 8006172

Claim:
An iterative error correcting decoding system interposed between a network interface and a block matrix memory, the system comprising: a First-In-First-Out (“FIFO”) memory block for storing said data coupled to said network interface for receiving data; at least one timing recovery module communicatively coupled to said network interface for receiving data, wherein each timing recovery module detects cycle slip; an auxiliary timing recovery module communicatively coupled to each FIFO memory block; a unique iterative error correction code decoder communicatively coupled to and interposed between each of said at least one timing recovery module and said block matrix memory wherein said unique iterative error correction code decoder performs a first number of error correcting iterations to achieve convergence and wherein, responsive to either said at least one timing recovery module detecting cycle slip or said unique iterative error correction code decoder failing to achieve convergence in said first number of iterations, communicating data in said FIFO memory block to said auxiliary timing recovery module; and an auxiliary iterative error correction code decoder communicatively coupled to and interposed between said auxiliary timing recovery module and said block matrix memory, wherein said auxiliary iterative error correction code decoder is configured to receive data from said auxiliary timing recovery module and perform a second number of error correcting iterations, said second number being greater than said first number.