Patent ID: 7155699

Claim:
A method for performing Optical and Process Correction (OPC) on an IC mask layout comprising: determining OPC corrections for the IC mask layout on an area-by-area basis, each area being an aerial subset of the IC mask layout wherein the OPC corrections are determined by: selectively tagging geometries of each area with at least one tag identifier to characterize the geometries in order to facilitate performance of an equivalency determination, the at least one tag identifier characterizing an edge fragment as a vertical edge fragment, a horizontal edge fragment, an edge fragment adjacent to a line-end edge fragment, or a concave corner edge fragment; determining if the geometries of a current area are equivalent, for OPC purposes, to the geometries in any previously corrected area, prior to the application of the corrections by analyzing if the tag identifiers indicate that the number, size, and relative locations of the geometric features in a windowed area, that includes and encircles the current area, are identical to the geometric features of a previously corrected windowed area or have the same number of geometric features and the sizes and relative locations of the geometric features are within a predetermined tolerance level as the geometric features in a previously corrected windowed area; and reusing the determined OPC corrections for the previously corrected windowed area if the current area is considered to be equivalent, wherein said OPC corrections for each area are determined iteratively employing model-based simulations, and each of said model-based simulations includes geometries of an adjacent neighboring area that are within an enlargement distance from the area for which the model-based simulation is being performed.