Patent ID: 7196954

Claim:
A method for bit line sensing in a semiconductor memory device, comprising: a. during a first time interval connecting a first capacitor to a core voltage and a second capacitor to ground; b. for a second time interval beginning after the first time interval, connecting the first and second capacitors to first and second source nodes, respectively, of a block of a plurality of bit line sensing amplifiers to transfer charge from the first and second capacitors to a bit line associated with the block of bit line sensing amplifiers; c. for a third time interval beginning after completion of the second time interval, connecting the first and second source nodes to the core voltage and ground, respectively, to complete bit line sensing; and d. after completion of said third time interval, connecting the first and second capacitors to the first and second source nodes, respectively, to transfer charge on the bit line associated with the block of bit line sensing amplifiers to the first and second capacitors.