Patent ID: 8134387

Claim:
A method for synchronizing data from a source clock domain operating according to a source clock, to a target clock domain operating according to a target clock, the method comprising: clocking an input data value originating from the source clock domain into a first latch using the target clock, during a present cycle of the target clock, to obtain a clocked input data value; clocking an output data value into a second latch using the target clock, during the present cycle of the target clock, to obtain a clocked output data value; comparing the clocked input data value with the clocked output data value during the present cycle of the target clock; when the comparing indicates that the clocked input data value is the same as the clocked output data, leaving the output data value unchanged; and when the comparing indicates that the clocked input data value is different from the clocked output data: if the clocked input data value does not exhibit metastable behavior, clocking the clocked input data into a third latch using the target clock, during a next cycle of the target clock, to update the output data value; and if the clocked input data value exhibits metastable behavior, clocking a defined logical state into the third latch using the target clock, during the next cycle of the target clock, to update the output data value.