Patent ID: 8024673

Claim:
A layout evaluation apparatus that evaluates a circuit layout of a semiconductor integrated circuit to be manufactured by estimating a result of planarization in manufacturing the semiconductor integrated circuit, the layout evaluation apparatus comprising: a dividing unit that divides the circuit layout into partial areas; a partial area data calculating unit that calculates, for each partial area, at least one of a wiring density in the partial area, a total perimeter length of wirings in the partial area, and a maximum value of differences of wiring densities in adjacent partial areas adjacent to the partial area from the wiring density in the partial area as partial area data; a critical region setting unit that sets a range of the wiring density, a range of the total perimeter length, and a range of the maximum value from which a height variation larger than an upper limit value is expected as critical regions based on a flatness estimation equation corresponding to a type of the circuit layout; and a map generating unit that plots the critical regions and the partial area data on a same map.