Patent ID: 8117575

Claim:
Apparatus for performing timing analysis on a circuit, comprising: a first storage device portion storing a state dependent stage weight for each of a rising time arc and a falling time arc of each of a plurality of cells in a cell library; an adder for calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path, the circuit path having up to N number of stages; a second storage device portion that stores a table containing on chip variation (OCV) derating factors, the table being indexed by values of the sum; and means for calculating a total path delay for the circuit path, based on the OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path, wherein each of the OCV derating factor in the table also corresponds to an individual circuit path in a cell having up to N number of stages, a 3-sigma delay and a mean delay at each respective stage of the reference cell calculated by performing a statistical simulation at the reference cell's transistor level having determined a mean delay and variation at each of the N stages of the reference cell, taking into account process variation parameters, and the OCV derating factors being determined as the ratio of the 3-sigma delay to the mean delay at each respective stage up to N of a reference cell.