Patent ID: 7826251

Claim:
A memory cell comprising: an eight transistor SRAM cell comprising: bit lines each comprising a read bit line and a write bit line; word lines each comprising a read word line and a write word line; a write circuit comprising: a poly-SiON gate stack, the poly-SiON gate stack comprising a static storage element comprising a plurality of poly-SiON inverters, wherein the gate stack is electrically isolated from the bit lines and the word lines; and at least one write access circuit coupled with the static storage element; a read circuit decoupled from the write circuit, said read circuit coupled with a corresponding read bit line and read word line for selectively activating the read circuit, the read circuit comprising: a metal Hi-k gate stack, coupled with the poly-SiON gate stack, the metal Hi-k gate stack comprising first and second metal Hi-k dielectric transistors connected in a stacked arrangement; wherein a drain terminal of the first transistor is connected to the corresponding read bit line, and a source terminal of the first transistor is connected to a drain terminal of the second transistor; wherein a source terminal of the second transistor is connected to a reference source; wherein a gate terminal of the first transistor is connected to the read word line and forms a first input of the read circuit; wherein a gate terminal of the second transistor is connected to an internal node of the static storage element and forms a second input of the read circuit; and wherein the read circuit is configured such that a substantially low resistance electrical path is formed between the drain terminal of the first transistor and the source terminal of the second transistor when both the first and second inputs of the read circuit are enabled.