Patent ID: 7358613

Claim:
A semiconductor device comprising: a plurality of wirings disposed in parallel to each other, each wiring including: a metal wiring layer including a first side surface, a first upper surface having a first width and a first bottom surface having a second width larger than the first width; a first barrier metal layer disposed on the metal wiring layer and including a second side surface, a second upper surface and a second bottom surface contacting with the first upper surface of the metal wiring layer, the second bottom surface including a third width larger than the first width of the first upper surface; and a second barrier metal layer disposed below the metal wiring layer and including a third side surface, a third upper surface contacting with the first bottom surface of the metal wiring layer, a third bottom surface, the third upper surface including a fourth width larger than the second width of the first bottom surface; a first insulating layer disposed below the second barrier metal layer and including a fourth upper surface contacting with the third bottom surface of the second barrier metal layer; and a second insulating layer covering the wirings so that a void is defined between the wirings, wherein the void has a larger sectional area than the metal wiring layer, the void includes an upper portion located between the second upper surface and the second bottom surface of the first barrier metal layer between the wirings, and the void includes a bottom portion located between the third upper surface and the third bottom surface of the second barrier metal layer between the wirings.