Patent ID: 7846794

Claim:
A method of forming a flash memory cell comprising: providing a silicon substrate having a main surface; forming a first dielectric layer on the main surface of the substrate; forming a floating gate above the dielectric layer; forming an inter-gate dielectric layer above the floating gate; forming a control gate above the inter-gate dielectric layer; removing portions of the control gate, the inter-gate dielectric layer, the floating gate and the first dielectric layer; forming a source region in a portion of the silicon substrate proximate the main surface; forming a drain region in a portion of the silicon substrate proximate the main surface, the drain being spaced apart from the source region; forming a second dielectric layer surrounding outer portions of the dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate; forming a low-k dielectric spacer layer on the second dielectric layer; and forming a fourth dielectric layer on the low-k dielectric spacer layer, wherein the fourth dielectric layer directly contacts with the control gate.