Patent ID: 7376027

Claim:
A write-sensing circuit for semiconductor memories comprising: a first and a second local bit-lines (BLs) forming a complementary BL pair; a first and a second global bit-lines (GBLs) forming a complementary GBL pair; and at least one switching circuit controlled by the first and second GBLs and controllably coupling a predetermined power supply source to the first and second BLs, separately, wherein when the first and second GBLs are asserted during a write operation, the switching circuit couples only one of the first and second BLs to the predetermined voltage supply source, wherein the predetermined voltage supply source is a lower voltage power supply source (Vss), wherein the switching circuit comprises a first and a second N-type metal-oxide-semiconductor (NMOS) transistors, wherein sources of both the first and second NMOS transistors are coupled to the Vss, a drain of the first NMOS transistor is coupled to the second BL, a drain of the second NMOS transistor is coupled to the first BL, a gate of the first NMOS transistor is coupled to the first GBL and a gate of the second NMOS transistor is coupled to the second GBL, wherein the first and second GBLs remains the same polarity during both read and write operations.