Patent ID: 7663929

Claim:
A semiconductor memory device, comprising: a memory cell array having plural memory cells connected between a bit line and a cell source line; a sense amplifier of the current sense type operative to initially charge said bit line with a charging voltage controlled by a bit-line control signal and detect the value of current flowing in said bit line when a certain gate voltage is given to a data read-targeted memory cell to decide data read out of said memory cell; and a bit-line control signal generator circuit operative to receive the voltage on said cell source line, generate said bit-line control signal in accordance with the received voltage on said cell source line and provide it to said sense amplifier, wherein said memory cell array forms a plurality of control areas in a direction orthogonal to the direction of extension of said bit line, wherein said sense amplifier initially charges a bit line in each control area in said memory cell array with a charging voltage controlled by a respective individual bit-line control signal, wherein said bit-line control signal generator circuit is one of plural bit-line control signal generator circuits provided in accordance with said control areas in said memory cell array, wherein each bit-line control signal generator circuit receives the potential on said cell source line in a corresponding control area, individually generates and provides said bit-line control signal in said each control area in accordance with the received voltage on said cell source line in each control area.