Patent ID: 8208312

Claim:
A non-volatile memory cell formed in a semiconductor substrate comprising: an antifuse element having a programming node, the antifuse element being configured to have changed resistivity after the programming node is subjected to one or more voltage pulses, the change in resistivity representing a change in logic state; and a capacitor element coupled to the antifuse element and configured to provide the one or more voltage pulses to the programming node; wherein the antifuse element comprises a MOS transistor having a gate, a source, and a drain, the gate being coupled to one of the programming node and a control node and the source and drain being coupled to the other one of the programming node and the control node; wherein the MOS transistor antifuse element is formed in a well having a first type of conductivity that is opposite to a second type of conductivity from which the substrate is formed and the source and drain of the MOS transistor antifuse element have the first type of conductivity, and wherein the source, drain and well of the MOS transistor antifuse element are configured to be coupled to the same voltage level.