Patent ID: 7057432

Claim:
A phase detector generating first and second control signals in response to a phase difference between a first clock and a second clock comprising: a latch having a set input, a reset input, a first latch output generating the first control signal, and a second latch output generating the second control signal; a first modified logic gate (MLG) having first, second, and third logic inputs, and a first logic output generating a logic one in response to a first logic combination of logic zero states of the first, second and third logic inputs and generating a logic zero in response to a second logic combination of the logic one states of the first, second, and third logic inputs, wherein the first logic input of the first MLG is coupled to the second clock, the second logic input of the first MLG is coupled to the first clock, and the first logic output is coupled to the set input; and a second MLG having first, second, and third logic inputs and a second logic output generating a logic one in response to the first logic combination of logic zero states of the first, second and third logic inputs and generating a logic zero in response to the second logic combination of the logic one states of the first, second, and third logic inputs, wherein the first logic input of the second MLG is coupled to the first clock, the second logic input of the second MLG is coupled to the second clock, the third logic input of the second MLG is coupled to the first logic output, and the second logic output is coupled to the reset input and the third logic input of the first MLG.