Patent ID: 6842884

Claim:
A method of equivalence checking, comprising: providing a first logic function and a second logic function; inserting don't care gates in the first and second logic functions in response to don't care conditions in the first and second logic functions to create a first intermediate circuit and a second intermediate circuit; propagating and merging all 3 value don't care 3DC gates of the first intermediate circuit into a single 3 value don't care gate when 3 value don't care gates and symbolic don't care SDC gates coexist in either of the first and second intermediate circuits; propagating and merging all 3 value don't care gates of the second intermediate circuit into a single 3 value don't care gate when 3 value don't care gates and symbolic don't care gates coexist in either of the first and second intermediate circuits; producing a first circuit and a second circuit in response to propagating and merging the 3 value don't care gates; and in response to the first and second circuits, performing a combinational equivalence check of the first circuit to the second circuit under different equivalence relations.