Patent ID: 7619463

Claim:
An electronic circuit, comprising: a load circuit that includes a first transistor and a second transistor coupled together in a current mirror configuration whereby a first current flowing through the first transistor is mirrored by a second current flowing through the second transistor, and wherein the first transistor has a drain terminal of the first transistor directly coupled to a gate terminal of the first transistor; and a power down circuit comprising: a third transistor configured as a switch located between a supply voltage and the first transistor, the switch configuration comprising a source terminal of the third transistor directly coupled to the drain terminal of the first transistor, and a gate terminal of the third transistor directly coupled to a first end of a first resistor for operating exclusively in a switching mode consisting of a) an on-state of the third transistor whereby the first transistor is connected to the supply voltage or b) an off-state of the third transistor whereby the first transistor is disconnected from the supply voltage thereby powering down the load circuit; and a fourth transistor that is coupled to the third transistor through the first resistor, the fourth transistor configured as a source follower for driving the third transistor into one of the on state or the off state.