Patent ID: 8001507

Claim:
An electric circuit comprising: a clock output circuit for delivering a clock signal; a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal; and a data output circuit for receiving the clock signal from the clock output circuit and transmitting, in synchronization with the clock signal, data to the processing circuits via wirings different from the wirings of the clock transmission, wherein the processing circuits are DDR2 SDRAMs to which the data transmitted from the data output circuit is written in synchronization with the clock signal, the wirings for clock transmission is connected by a single wire between the clock output circuit and a certain point referred as a first point on the electric circuit, and is further connected between the first point and the individual processing circuits by a plurality of wirings branching from the first point so that the wirings have the same length, the single wire includes a wiring length adjustment portion which has a meandering pattern and which is used for adjustment of length of the wirings for clock transmission, and the adjustment of the length of the wirings for clock transmission by use of the wiring length adjustment portion is so performed as to make substantially equal time periods, both from output of the clock signal by the clock signal output circuit, to arrival of the data corresponding to the clock signal at the processing circuits and to arrival of the clock signal to the processing circuits via the wirings for clock transmission.