Patent ID: 7356741

Claim:
A semiconductor device, comprising: an embedded dynamic random access memory (eDRAM) for storing data, the eDRAM including a plurality of memory cells; and a test controller for testing the plurality of memory cells to determine if the cells are defective, the test controller including: a built-in self-test (BIST) core for performing tests on the eDRAM using one or more , proven testing algorithms for testing a plurality of different eDRAM products and eDRAM product generations, the BIST core employing fixed input/output interface definitions; selectable tester interface for interfacing the BIST core with an external tester, wherein the selectable tester interface interfaces with said BIST core according to said fixed input/output interface definitions of the BIST core and interfaces with an external tester using one of a plurality of tester interface options depending on a type of external tester to be used for testing the semiconductor device; and a selectable eDRAM interface for interfacing the BIST core with the eDRAM using one of a plurality of eDRAM interfaces depending on the type of eDRAM embedded in the semiconductor device.