Patent ID: 7382158

Claim:
A level shifter circuit, including: a first output control element formed by a p-channel MOS transistor arranged between an output terminal and a high potential power supply voltage line; a second output control element formed by an n-channel MOS transistor arranged between the output terminal and a reference voltage line; a first switch element for controlling connection between a gate terminal of the first output control element and the high potential power supply voltage line in accordance with an output enable signal for performing an output corresponding to an input signal; and a second switch element for controlling connection between a gate terminal of the second output control element and the reference voltage line in accordance with an output disable signal for realizing a high impedance state; wherein when the output enable signal has a high level and the input signal has a high level, a voltage higher than a voltage of the input signal is output from the output terminal, the level shifter circuit being characterized by: a high impedance holding means including: a set means for applying high potential power supply voltage to the gate terminal of the first output control element when the high potential power supply voltage exceeds a threshold voltage of the first output control element; and a reset means for stopping the application of the high potential power supply voltage to the gate terminal of the first output control element when the first switch element starts control.