Patent ID: 7173868

Claim:
A sense amplifier of a ferroelectric memory device comprising: a MBL sensing unit for sensing and amplifying a voltage of a main bit line when a sensing signal is activated, inverting and amplifying the voltage of the main bit line, and regulating a level of an output voltage depending on the level of the inverted and amplified voltage; a voltage dropping unit for dropping the level of the inverted and amplified voltage in the MBL sensing unit to a predetermined level; a coupling regulation unit, connected in parallel to the voltage dropping unit, for transmitting a signal inverted and amplified in the MBL sensing unit to an output terminal of the voltage dropping unit; a pull-down regulation unit for pulling down output voltages from the voltage dropping unit and the coupling regulation unit when the sensing signal is inactivated; a sensing load unit for applying sensing load variably to the MBL sensing unit in response to output signals from the voltage dropping unit and the coupling regulation unit and regulating an output voltage level from the MBL sensing unit; and an amplification unit for amplifying the output voltage of the MBL sensing unit level-regulated by the MBL sensing unit and the sensing load unit.