Patent ID: 8856261

Claim:
A system for checkpointing data in a parallel computing system having a plurality of computing nodes, each node having one or more processors and network interface devices for communicating system and user application messages over a network, said checkpointing system comprising: one or more network elements interconnecting said network interface devices of computing nodes via links to form a network; a system control device to communicate control signals to each said computing node of said network for stopping receiving and sending message packets at a node, and to communicate further control signals to each said one or more network interface elements for stopping flow of message packets within said formed network; a control unit, at each computing node and at one or more said network elements, responsive to control signals to stop each of said network elements and stop each said network interface device involved with processing of packets in said formed network including stopping (direct memory access) DMA packet injection and packet reception sub-units at each node to prevent new packets from being injected into or received from the network, and, to stop a flow of packets communicated on links between nodes of said network; and, said control unit at each node and said one or more network elements, responsive to said further control signals to obtain and save network packet data and network control state information in both said network interface devices and network elements, and, said control unit further restoring all network packet data to both said network interface devices and network elements, prior to enabling network traffic and computations to resume, a memory storage device being adapted to temporarily store said obtained network packet data and said network control state information, and said system including a separate control network, and said separate control network including a host control device, which is configured to communicate with each said nodes and said separate network permitting communication between said nodes, said separate control network implementing a barrier wherein each compute node signals a “barrier entered” message to the separate control network, and waits until receiving a “barrier completed” message from the host control device of said separate control network, wherein each said computing node further comprises: state machine registers for temporarily storing said network state information, said host control device reading said state machine registers for determining when all units have stopped and all packet flows are no longer in transit along links in the network; each node including a read/write mechanism for respectively reading and writing to all internal network elements including network register and buffers.