Patent ID: 8086975

Claim:
A computer-executable program product for designing asynchronous circuits, the program product comprising a non-transitory computer-readable storage medium with resident computer-readable instructions, which when loaded in a computer system causes the computer system to: (A) receive as an input a synchronous netlist corresponding to a synchronous circuit; (B) create a logic cluster configured and arranged to receive and process one or more tokens, the logic cluster comprising: combinational logic; completion sensing logic; a plurality of memory elements; and an asynchronous controller, wherein the asynchronous controller has a combined functionality of (a) a token filter (TF) module configured and arranged to (i) receive a token in input channels L and EN, and (ii) send a token on an output channel R based on the value received on EN, (b) a token latch (TL) module configured and arranged to (i) receive a token on an EN channel, (ii) receive a value on an L channel, (iii) based on a value of UPDATE on the L channel, update a value of an internal state variable d with a new value and send a value of d to an output channel R, and (iv) based on a value of NOUPDATE on the L channel send a previously stored value of d to the output channel; and (c) wherein when no new tokens are provided to the cluster, the controller does not re-evaluate a combinational logic datapath and generates and sends information about new tokens to one or more clusters in a fanout of the cluster; (C) cause the logic cluster to process one or more tokens; and (D) produce as an output an asynchronous netlist of an asynchronous circuit corresponding to the synchronous circuit.