Patent ID: 6946349

Claim:
A method for integrating the fabrication of a SONOS memory cell with gate oxides of different thicknesses comprising the steps of: providing a semiconductor substrate having implanted regions for wells and drains for core regions, input/output (I/O) regions, and SONOS cell regions surrounded by isolation areas; forming sequentially a blanket silicon oxide layer, a storage silicon nitride layer, and a top silicon oxide layer (ONO layer) on said substrate; forming a sacrificial silicon nitride layer on said top silicon oxide layer; patterning said sacrificial silicon nitride layer and said ONO layer leaving portions of said ONO layer with said sacrificial silicon nitride layer over said SONOS cell regions while exposing surface of said substrate over said core regions and said I/O regions; forming a first gate oxide (ISSG) on said exposed surface, while partially oxidizing said sacrificial silicon nitride layer to form a sacrificial silicon oxide layer while protecting said top silicon oxide layer; patterning said first gate oxide to leave portions over said I/O regions while concurrently removing said first gate oxide over said core regions and removing said sacrificial silicon oxide layer; forming a second gate oxide over said core regions while concurrently oxidizing remaining said sacrificial silicon nitride layer to complete said SONOS memory cell and said first gate oxide and said second gate oxide each of a different thickness.