Patent ID: 8756466

Claim:
An apparatus integrated into a design of a system-on-chip (SOC) circuit, the apparatus connected to a plurality of scan groups having one or more clock domains therein, the scan groups further having peripheral isolation and a defined activity factor (AF) for each of the plurality of scan groups, wherein the apparatus is configured to divide the SOC circuit respective of an estimation of power dissipation of each of the plurality of scan groups, wherein for the estimation of power dissipation, the apparatus comprises: a first circuit which generates one or more scan groups using at least a register-transfer-level (RTL) design description of the SOC circuit and a circuit library corresponding the SOC circuit; a second circuit which establishes a peripheral interaction factor (PIF) for each of the plurality of scan groups; a third circuit which performs a power simulation for each of the plurality of scan groups; a fourth circuit which generates a report for each of the plurality of scan groups containing at least power consumption data of the plurality of scan groups obtained in response to the power simulation for the plurality of scan groups; and a fifth circuit which optimizes the testing of the SOC by grouping the plurality of scan groups into a plurality of test groups based on the power consumption of the plurality of scan groups as provided in the report and at least one of a tester's power capability, desired test time, and test cost on the tester.