Patent ID: 7284175

Claim:
An apparatus for inserting a DFD (design-for-debug) circuitry in an integrated circuit to debug or diagnose functional cores each having a selected fault type and a system clock; said apparatus comprising: (a) a DFD selector for indicating which said functional cores and said selected fault types will be debugged or diagnosed simultaneously; (b) a plurality of break registers in each said functional core which are stitched together for storing predetermined break conditions during diagnosis; (c) a step counter in each said functional core for storing a predetermined number of clock cycles during diagnosis; (d) a scan connector for connecting multiple scan chains in said functional cores to a boundary-scan chain in said integrated circuit; (e) a RESET control circuitry that resets the contents of said functional cores when a reset control signal is set to logic value 1; (f) a BREAK control circuitry in a functional clock controller that accepts a break condition signal from a said functional core to stop said system clock immediately when a break control signal is set to logic value 1 and a said predetermined break condition is met; (g) a RUN control circuitry in said functional clock controller that allows said system clocks to run forever when a run control signal is set to logic value 1; (h) a STEP control circuitry in said functional clock controller that accepts a step limit signal from a said functional core to stop said system clock immediately when a step control signal is set to logic value 1 and said system clock has run for an additional, said predetermined number of clock cycles. (i) a STOP control circuitry in said functional clock controller that stops said system clocks when a stop control signal is set to logic value 1; and (j) a multiplexer for connecting said DFD selector and said scan connector to a TAP (test access port) controller in said integrated circuit.