Patent ID: 8395931

Claim:
A semiconductor memory device comprising: a first line; a second line; a third line; a fourth line; a fifth line; and a memory cell comprising: a first transistor; a second transistor; and a capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one of electrodes of the capacitor, wherein a gate of the first transistor is electrically connected to the first line, wherein the other of the source and the drain of the first transistor is electrically connected to the fifth line, wherein one of a source and a drain of the second transistor is electrically connected to the third line, wherein the other of the source and the drain of the second transistor is electrically connected to the fourth line, wherein the other of electrodes of the capacitor is electrically connected to the second line, wherein the first transistor comprises a semiconductor layer including an oxide semiconductor, and wherein an area of the capacitor is less than 2 times an area of a channel region of the second transistor.