Patent ID: 7290191

Claim:
An integrated circuit, comprising: a test pin, a first test clock pin, a second test clock pin, a third test clock pin, a functional clock pin, a scan-in pin, a scan-out pin and an enable pin; a test controller having a test input connected to said test pin, a first test clock input connected to said first test clock pin, a functional clock input connected to said functional clock pin, a first control output and a second control output; a clock splitter having a first clock input connected to said second test clock pin, a second clock input connected to said functional clock pin, a first control input connected to said first control output of said test controller, a second control input connected to said second control output and of said controller, an enable input connected to said enable pin, a ZB clock output and a ZC clock output; and an LSSD scan chain comprised of serially connected latches, a first stage of each latch having a first data input, a second data input and a C clock input connected to said ZC clock output of said clock splitter, an A CLK input connected to said third test clock pin, a second stage of each latch having a data output and a B clock input connected to said ZB clock output of said clock splitter, a data output of a previous latch connected to a first input pin of an immediately subsequent latch, a first data input of a first latch of said LSSD scan chain connected to said scan-in pin and a data output pin of a last scan chain latch of said scan chain connected to said scan-out pin.