Patent ID: 8854902

Claim:
A circuit, comprising: a memory cell array including: a first section having a plurality of memory cells and at least one data bit line for each column of memory cells in said first section; and a second section having a plurality of write timer cells arranged in a column, each write timer cell including an internal true node, an internal complement node and a pullup transistor having a gate terminal coupled to said internal true node, said second section including at least one reference bit line coupled to the column of write timer cells and having a true reference internal line coupled to the internal true nodes of the column of write timer cells; column circuitry coupled to the first and second sections of the memory cell array, said column circuitry including a reference write driver circuit having an output coupled to drive said at least one reference bit line; and means for lowering a gate to source voltage of the write timer cell pullup transistor by raising a lower voltage level to which said internal true node is pulled down during a write operation to a voltage level above logic low level.