Patent ID: 7660971

Claim:
In a processor, a method comprising: in response to receipt of an instruction sequence including instructions, said instructions including a first instruction indicating an update to a particular logical register among a plurality of logical registers and a previous second instruction also indicating an update to the particular logical register: in a register mapper, mapping said particular logical register to a physical register among a plurality of physical registers within a register file of the processor and recording the mapping between the particular logical register and the physical register; in a last definition (DEF) data structure, recording an identifier of the first instruction as a most recent instruction in the instruction sequence that defines contents of the particular logical register; in a next DEF data structure, recording the identifier of the first instruction in association with an identifier of the previous second instruction; in a recovery data array having in a first dimension multiple columns each corresponding to respective one of the plurality of logical registers and having in a second dimension multiple rows each corresponding to a respective one of a plurality of possible instruction identifiers including the identifier of the first instruction, indicating which of the instructions in the instruction sequence updates said plurality of logical registers; executing instructions in the instruction sequence, wherein the executing includes executing at least some of the instructions speculatively; and in response to misspeculation during execution of the instruction sequence, performing a recovery operation to place the identifier of the previous second instruction in the last DEF data structure by reference to said next DEF data structure and said recovery data array.