Patent ID: 7277357

Claim:
A delay-locked loop, comprising: a delay line having first and second inputs and an output, the first input configured to receive an external clock signal via a clock input path and the output configured to couple with an output driver of a memory device; an I/O model having an output and an input, the input of the I/O model configured to couple with the output of the delay line via a clock distribution network of the memory device, the I/O model configured to model delay of the output driver; a phase detector having forward and feedback path inputs and an output, the forward path input coupled to the first input of the delay line and the feedback path input coupled to the output of the I/O model; and a filter circuit having an input coupled to the output of the phase detector and an output coupled to the second input of the delay line, the filter circuit including a first oscillation filter and a majority filter for filtering oscillations from input signals received on the input and generating oscillation filtered control signals on the output.