Patent ID: 8711073

Claim:
A display system, comprising: a display panel including a plurality of pixel units, where the pixel units are arranged as a matrix having respective rows of the pixel units, each of the pixel units having at least a main subpixel and one or more subsidiary subpixels, wherein the main and subsidiary subpixels of each pixel unit are coupled to receive respective charges from a same data line associated with the given pixel unit; a first driver for applying, by way of corresponding first gate lines, first gate signals to respective first thin film transistors used to charge and discharge the respective main subpixels; and a second driver for applying, by way of corresponding second gate lines, second gate signals to respective second thin film transistors used to charge and discharge the respective subsidiary subpixels, wherein the first and second drivers generate the respective first and second gate signals thereof independently such that the first and second gate signals can have partially time-overlapped turn-on levels, wherein each of the first and second drivers includes a respective plurality of sequentially connected shift register stages, the first driver having more shift register stages than the second driver, wherein the first driver comprises a first gate clocks generator for generating first and second main gate clock signals, said plurality of sequentially connected shift register stages of the first driver includes a plurality of first application timing circuits for timing application of turn-on levels of the first gate signals to the main subpixels in response to the first and second main gate clock signals, and the second driver comprises a second gate clocks generator for generating first and second subsidiary gate clock signals, said plurality of sequentially connected shift register stages of the second driver includes a plurality of second application timing circuits for timing application of turn-on levels of the second gate signals to the subsidiary subpixels in response to the first and second subsidiary gate clock signals, and wherein said plurality of sequentially connected shift register stages of the first driver further includes a plurality of reset timing circuits interposed between the first application timing circuits for defining a duration of turn-on drive time provided by the first application timing circuits relative to total time consumed by combination of the reset timing circuits and the first application timing circuits.