Patent ID: 7419850

Claim:
A method to manufacture a coreless packaging substrate, comprising the following steps: (A) providing a carrier board, and forming a first solder mask on a top surface of the carrier board, wherein a plurality of first openings are formed in the first solder mask to expose parts of the carrier board; (B) forming a first metal layer in each of the first openings, and forming a first dielectric layer on a surface of the first solder mask and on the first metal layers; (C) forming a first resistive layer on a surface of the first dielectric layer, and forming a plurality of second openings in the first resistive layer at positions corresponding to the first metal layer, followed by forming a second metal layer in each of the second openings and then removing the first resistive layer; (D) forming a built-up structure on surfaces of the first dielectric layer and the second metal layers, wherein the built-up structure includes at least a dielectric layer, at least a third metal layer of patterned circuit, a plurality of conductive vias, as well as a plurality of conductive pads; (E) forming a second solder mask on the built-up structure, wherein a plurality of third openings are formed in the second solder mask to expose the conductive pads of the built-up structure; (F) removing the carrier board and the first metal layers to thereby expose parts of bottom surfaces of the first dielectric layer, and forming a plurality of fourth openings in the first dielectric layer to expose parts of bottom surfaces of the second metal layers; and (G) forming a solder bump in each of the third openings in the second solder mask, and forming a solder layer in each of the first openings in the first solder mask.