Patent ID: 8086980

Claim:
An improved method for validating a physical implementation of voltage region power distribution networks in a semiconductor chip design comprising the steps of: performing a plurality of early chip design steps resulting in an early semiconductor chip design including an initial chip floor plan and a chip power grid layout; performing a series of early power grid validity checks on the power distribution networks after the early chip design steps by: using routing properties coded on region shapes for quick identification of voltage regions and their expected power metallurgy characteristics, analyzing region power distribution networks against the chip floor plan, which contains circuit abstracts rather than real circuit layouts, and using coded connectivity attributes already existing in the chip power grid layout and the chip floor plan, eliminating a need to build a full logical representation of a complete power metallurgy and via structure as required by conventional chip physical design checking methods; performing a series of post early power grid validity checks on aspects of the chip design other than power distribution networks, including chip signal routing steps; and performing full-chip formal and physical design verification and analysis procedures after completion of all mentioned steps and checks; wherein one or more of the method steps are performed by a computer.