Patent ID: 7176088

Claim:
A method for fabricating a bit line structure, comprising the steps of: a) forming a trench (T) in a substrate ( 1 , 2 , 3 ); b) forming a trench insulation layer ( 6 ) at a trench surface of the trench (T); c) forming an electrically conducting filling layer ( 7 ) on the trench insulation layer ( 6 ) of the trench (T) in order to realize a buried bit line (SLx); d) forming a covering insulation layer ( 8 , 9 , 8 A) in an upper region of the trench (T); e) forming first and second doping regions ( 10 ) at the surface of the substrate ( 3 ); f) forming a multiplicity of covering connecting layers ( 12 ) on the filling layer ( 7 )in partial regions of the covering insulation layer ( 8 , 9 , 8 A); g) forming a multiplicity of self-aligning terminal layers ( 13 ) for electrically connecting the multiplicity of covering connecting layers ( 12 )to the second doping regions ( 10 , S); h) forming an intermediate insulation layer ( 14 ) at the surface of the substrate; i) forming an electrically conducting layer ( 15 ) as surface bit line (DLx); and j) forming a multiplicity of contacts (DC) for electrically connecting the surface bit line (DLx) to the first doping regions (D).