Patent ID: 8501579

Claim:
A process of fabricating a chip, the process comprising: providing a wafer having a first surface and a second surface opposite to each other; forming a plurality of holes on the first surface of the wafer; forming an electroplating seed layer on the first surface and on walls of the holes; forming a first patterned mask on the electroplating seed layer located above the first surface; forming a conductive material in the holes by performing an electroplating process so as to form a plurality of conductive holes; removing the first patterned mask and a portion of the electroplating seed layer located below the first patterned mask; forming a second patterned mask on the first surface of the wafer; etching the first surface with use of the second patterned mask as an etching mask so as to form a plurality of insulating ring areas and a plurality of stress buffer ring areas, wherein the insulating ring areas respectively expose side walls of the conductive holes, and the insulating ring areas are respectively located in the stress buffer ring areas; and disposing an insulating material in the insulating ring areas and the stress buffer ring areas to form a plurality of insulating rings and a plurality of stress buffer rings.