Patent ID: 7706209

Claim:
A semiconductor device including: a plurality of word lines disposed in parallel; a plurality of bit lines extending in a direction perpendicular to the extending direction of said word lines; a memory cell array having a plurality of memory cells disposed in an array form, and connected to corresponding ones of said word lines and said bit lines; a word line reset level generating circuit for generating a negative potential; wherein non-selected ones of said word lines are set to said negative potential by applying the output of said word line reset level generating circuit to non-selected ones of said word lines; and wherein said word line reset level generating circuit is controlled to change the amount of said negative potential supplied to the non-selected ones of said word lines in accordance with a bank access operation of said memory cell array; a word line reset level detecting circuit for detecting the output state of said word line reset level generating circuit; a word line reset level control circuit for controlling the operation of said word line reset level generating circuit on the basis of the detection result of said reset level detecting circuit; and a plurality of banks; wherein said word line reset level generating circuit comprises a plurality of circuit units corresponding to said plurality of banks, and capable of operating independently; and wherein said plurality of circuit units are selected and operated in accordance with the bank access operation of said memory cell array.