Patent ID: 7546445

Claim:
An information processor having a delayed branch function, the processor comprising: an instruction cache; and an instruction read circuit configured to read Very Long Instruction Word (VLIW) instruction codes from the instruction cache by addressing the instruction cache, wherein the instruction read circuit comprises: a branch prediction circuit, including a storage in which a branch target address, branch history information, and delay slot information indicating a last position of delay slot instructions are stored in correspondence with an address of a branch instruction, outputting hit information as to whether or not an input address is coincident with the branch instruction address, when the coincidence is true, accessing the storage to output the delay slot information and prediction information on a presence of a branch based on the branch history information, obtaining a number of steps included in the VLIW instruction code based on the delay slot information, and when the prediction information indicates that there is a branch, further outputting the branch target address; an incrementer configured to output a sequential address; and an address selection circuit selectively outputting the branch target address or an output of the incrementer, based on the hit information, the delay slot information, and the prediction information, the address selection circuit outputting the output of the incrementer a predetermined number of times based on the delay slot information when the hit information indicates that the coincidence is true.