Patent ID: 8341562

Claim:
A method comprising: pre-determining a threshold enclosure; retrieving first layouts of a semiconductor chip from a non-transitory computer-readable medium, wherein the first layouts comprise via patterns and metal line patterns; finding enclosures of the via patterns based on the via patterns and the metal line patterns; comparing the enclosures of the via patterns to the threshold enclosure; and modifying the metal line patterns to generate second layouts of the semiconductor chip, wherein the step of modifying the metal line patterns comprises: increasing a first portion of the enclosures of the via patterns to not smaller than the threshold enclosure when the first portion of the enclosures of the via patterns is smaller than the threshold enclosure; and maintaining a second portion of the enclosures not changed and copying the second portion of enclosures to the second layouts when the second portion of the enclosures of the via patterns is not smaller than the threshold enclosure.