Patent ID: 8423864

Claim:
A receiving apparatus comprising: a deinterleaving device configured to perform a deinterleaving process on an LDPC-coded data signal having undergone an interleaving process, said LDPC representing low Density Parity Check, by use of a memory which has columns capable of storing as many as “a” data, said “a” being an integer of at least 1; and a control device configured such that if said data signal is supplied in units of N data, said N being an integer smaller than said “a;” then said control device controls said deinterleaving device to write said data signal to a predetermined address of said memory while reading previously written data from said predetermined address in a write period, said control device further controlling said deinterleaving device to stop writing said data signal to said predetermined address of said memory while reading said previously written data from said predetermined address in a write inhibit period.