Patent ID: 7560774

Claim:
An integrated circuit chip comprising: a plurality of LDMOS (laterally double-diffused metal oxide semiconductor) devices having different voltage ratings, wherein the LDMOS devices are configured on a substrate having a first conductive type, and each LDMOS device is constructed with components comprises: two gate conductive layers, respectively disposed on two first active regions of the substrate; a common drain contact region having a second conductive type, wherein the common drain contact region is configured in a second active region, and the second active region is configured between the first active regions; an isolation structure, isolating the second active region and the first active regions; wherein the isolation structure between each of the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each of the two gate conductive layers, and each of the two gate conductive layers on each of the two first active regions has a length “L” extending along the longitudinal direction of the above channel, the LDMOS devices having different voltage ratings comprise different A/L values.