Patent ID: 7289364

Claim:
An electrically programmable memory device, comprising: a matrix of memory cells arranged in a plurality of memory arrays and at least one redundancy array, the memory arrays being grouped into at least one set; and means, for each memory array, for substituting the use of the memory array with the use of one of the at least one redundancy array in response to a failure of the memory array, the means for substituting including: means for associating each set with a predetermined one of the at least one redundancy array; a plurality of flags including a respective flag for each memory array indicative of the failure or not of the memory array; and selecting means for enabling each memory array or the associated redundancy array according to the corresponding flag, wherein the memory cells are arranged in a plurality of rows and a plurality of columns, each memory array including at least one column, wherein the matrix includes a further row memory cells for storing the flags, and wherein each memory array includes a plurality of columns, and wherein the memory device further includes a selector for selecting a column in each array, the selector being interposed between the plurality of rows and the further row.