Patent ID: 8264393

Claim:
A cyclic redundant signed digit (RSD) analog-to-digital converter (ADC) comprising: a gain circuit, comprising: a first switch coupled between an input terminal and a first node, the first switch for applying an input signal to the first node; a second switch coupled between the first node and a second node, the second switch for applying a residual voltage feedback signal to the first node; a first amplifier having a first input terminal, a second input terminal, and an output terminal selectively coupled to the second node; a second amplifier having a first input terminal, a second input terminal, and an output terminal selectively coupled to the second node; and at least first, second, third, and fourth capacitors, each of the first, second, third, and fourth capacitors capable of being selectively coupled between the first node and the first input terminals of both of the first and second amplifiers during an analog-to-digital conversion comprising a plurality of clock cycles; wherein the gain circuit uses the first amplifier to generate a gain factor of at least four and the gain circuit uses the second amplifier to generate a gain factor of two, wherein the first amplifier operates to amplify the residual voltage feedback signal during the first clock cycle of the plurality of clock cycles while the second amplifier is disconnected from the first node, and wherein during a second clock cycle subsequent to the first clock cycle, the second amplifier operates to amplify the residual voltage feedback signal while the first amplifier is disconnected from the first node.