Patent ID: 8126045

Claim:
A decision feedback equalizer (DFE), comprising: a first circuit portion, including: summer circuits configured to add at least one dynamic feedback tap to a received input to provide a sum and to add at least one speculative static tap to the sum; sense amplifiers configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal; a passgate multiplexer configured to receive outputs from at least two sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of at least two sense amplifiers during a precharge period of the sense amplifiers; a gating circuit configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period; and a regenerative buffer coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the at least one dynamic feedback tap to a summer circuit on the first circuit portion of the DFE.