Patent ID: 8544024

Claim:
A multi-processor system comprising: a sending processor adapted to send a data message; a receiving processor adapted to receive the data message; and a memory unit associated with the receiving processor; a size-index table associated with the sending processor; a direct memory access controller associated with the receiving processor, and adapted to execute scatter chains comprising at least one peripheral-to-memory transfer and at least one memory-to-memory transfer; a data link associated with the sending processor and the receiving processor; the sending processor comprising an output buffer associated with the data link, and being adapted to map a size of a payload portion of the data message to an index of the size-index table, and to send the data message containing the size, the index and the payload portion to the receiving processor; mapping circuitry associated with the receiving processor, the mapping circuitry comprising: a pointer array for storing pointers; an index register; and a pointer register; and being adapted to map the index contained in the data message received from the sending processor to a pointer, wherein the pointer is associated with a buffer of the memory unit; and the receiving processor comprising an input buffer associated with the data link, and being adapted to: receive the data message containing the size, the index, and the payload portion; and wherein the direct memory access controller is further adapted to: read the size from the input buffer; read the index from the input buffer; write the index to the index register; write the pointer to the pointer register; read the pointer, associated with the buffer of the memory unit, from the pointer register; read the payload portion from the input buffer; and write the payload portion to the buffer of the memory unit as indicated by the pointer.