Patent ID: 7260760

Claim:
A method for built-in self-testing for high-performance circuits, configured to generate and apply a test pattern to a circuit under test, comprising the steps of: providing a memory device comprising a quantity value s of original test seeds; providing a logic structure in communication with the circuit-under-test and the memory device through a first communication link, the logic structure comprising a log 2 s bit seed counter, a log 2 2n bit twist counter and a log 2 n bit shift counter, wherein the twist counter and the shift counter are in communication with a first communication link input scan register having a length n; the logic structure seed counter and twist counter using a seed generation algorithm to produce generated test seeds from the original test seeds by applying test patterns; the input scan register loading a total test seed plurality comprising the generated test seeds and the original test seeds into the circuit-under-test; the circuit-under-test generating a totality test seed response plurality in response to an input of the total test seed plurality, one test seed response for each test seed; a response suppression circuit in communication with the circuit-under-test and the logic structure through the first communication link and comprising a logic component having a number of inputs x=log 2 s+log 2 2n+log 2 n+1 and a test mode bit input using the logic structure twist counter and shift counter to perform the steps of: generating a deterministic test pattern subset of the generated test seeds by looping the original test seeds through the input scan register; identifying each totality test seed response plurality response generated in response to a deterministic test pattern subset test seed; and disabling each totality test seed response plurality response not identified in the identifying step; and a second communication link compactor in communication with the response suppression circuit compacting the identified test seed responses to generate compacted test responses to a response monitor.