Patent ID: 7598796

Claim:
A semiconductor device comprising: a voltage generator receiving a first voltage and generating a second voltage on an output node, the second voltage being different from the first voltage, wherein the voltage generator includes a first charge pump circuit that has a first capacitor receiving a first clock to a first node of the first capacitor, a first PMOS transistor of which source and drain are connected between a second node of the first capacitor and the output node of the voltage generator, and a first NMOS transistor of which source and drain are connected between the second node of the first capacitor and the output node of the voltage generator, wherein the voltage generator further includes a second charge pump circuit that has a second capacitor receiving a second clock to a first node to the second capacitor, a third PMOS transistor of which source and drain are connected between a second node of the second capacitor and the output node of the voltage generator, a third NMOS transistor of which source and drain are connected between the second node of the second capacitor and the output node of the voltage generator, wherein the second clock is an inversion clock of the first clock, wherein a gate of the first PMOS transistor is connected to the second node of the first capacitor, wherein a gate of the third PMOS transistor is connected to the second node of the second capacitor, wherein a gate of the first NMOS transistor is connected to the second node of the second capacitor, wherein a gate of the third NMOS transistor is connected to the second node of the first capacitor.