Patent ID: 7816756

Claim:
A power semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer of the first conductivity type and alternately arranged along at least one direction parallel to an upper face of the first semiconductor layer of the first conductivity type; a first main electrode electrically connected to the first semiconductor layer of the first conductivity type; a fourth semiconductor layer of the second conductivity type selectively formed in an upper face of the second semiconductor layer of the first conductivity type and an upper face of the third semiconductor layer of the second conductivity type; a fifth semiconductor layer of the first conductivity type selectively formed in an upper face of the fourth semiconductor layer of the second conductivity type; a second main electrode electrically connected to the fourth semiconductor layer of the second conductivity type and the fifth semiconductor layer of the first conductivity type; and a control electrode formed above the second semiconductor layer of the first conductivity type, the third semiconductor layer of the second conductivity type, the fourth semiconductor layer of the second conductivity type, and the fifth semiconductor layer of the first conductivity type via a gate insulating film, the control electrode including: first portions periodically arranged along a first direction selected from arranging directions of the third semiconductor layer of the second conductivity type, the third semiconductor layer of the second conductivity type having a shortest arrangement period in the first direction, and second portions periodically arranged along a second direction, the second direction being parallel to the upper face of the first semiconductor layer of the first conductivity type and crossing the first direction, and the arrangement period of the first portions being m times the arrangement period of the third semiconductor layer of the second conductivity type, where m is an integer not less than 2.