Patent ID: 8913196

Claim:
A video processing device that takes as input any of a plurality of serial digital interface signals that each contain signals in which parallel data that contain at least video data have been converted to serial data and information of a clock for synchronizing said parallel data and in which the video format of said video data and a frequency of said clock each mutually differ, said device comprising: a deserializer that both converts serial digital interface signals that are received as input to said parallel data and extracts said clock; a format detection unit that both detects said video format of said video data that are contained in said parallel data that have been converted by said deserializer and supplies as output clock ratio information that indicates a ratio between a clock frequency and a pixel clock frequency stipulated by the video format that was detected; a pixel clock generation unit that, based on said clock that was extracted by said deserializer, generates a pixel clock having the frequency stipulated by the video format that was detected by said format detection unit and supplies the generated pixel clock; a saving unit that saves said video data that are contained in said parallel data that were converted by said deserializer and that supplies as output the saved video data in synchronization with said pixel clock that was supplied from said pixel clock generation unit; a write control unit that, based on said clock ratio information that was supplied from said format detection unit, divides into two or four portions said video data that are contained in said parallel data that were converted by said deserializer and saves the divided video data in said saving unit; and a processor that, synchronized with said pixel clock that was supplied from said pixel clock generation unit, subjects data that were supplied from said saving unit to processing according to the video format that was detected by said format detection unit.