Patent ID: 8437213

Claim:
An integrated circuit including a functional memory, the functional memory comprising: row and column periphery units having periphery sourcing and sinking voltage supply ports; an array of memory cells connected to the row and column periphery units that are organized in corresponding rows and columns; a word line connected between the row periphery unit and a memory cell of the array, the word line being controlled by a word line driver to provide row access to the memory cell, the word line being coupled to a word line driver sourcing voltage supply, the row periphery unit being coupled to a periphery sourcing voltage supply and a periphery sinking voltage supply; a bit line connected between the column periphery unit and the memory cell, the bit line being controlled by direct bit line access circuitry to provide direct bit line access to the memory cell through a bit line analog access port, the bit line analog access port being coupled to one of a bond pad, a probe pad, a bump, and an on-chip test controller, the column periphery unit being coupled to the periphery sourcing voltage supply and the periphery sinking voltage supply; and an independent voltage supply port connected to the memory cell, the independent voltage supply port being coupled to an independent array voltage supply, the independent array voltage supply having a voltage that is not constrained by a voltage of another voltage supply including the word line driver sourcing voltage supply, the periphery sourcing voltage supply, and the periphery sinking voltage supply; wherein the word line driver sourcing voltage supply has a voltage that is not constrained by a voltage of another voltage supply, the periphery sourcing voltage supply has a voltage that is not constrained by a voltage of another voltage supply, and the periphery sinking voltage supply has a voltage that is not constrained by a voltage of another voltage supply.