Patent ID: 6874046

Claim:
A method for enabling a processor that directs I/O requests over a first communications channel to a first plurality of logical devices during normal operations to switch and direct I/O requests over a second channel to a second plurality of logical devices normally operating as a mirror of the first plurality of logical devices and each of the plurality of logical devices has an identifying control block, I/O requests normally being processed using control blocks for the first plurality of logical devices, said method being responsive to a swap command to direct I/O requests to an identified logical device over the second channel and comprising the steps of: A) determining, during normal operations, an operating validity of both the first and second pluralities of logical devices, and B) performing an address switch by: i) verifying the operating validity of the logical devices in the first and second pluralities of logical devices corresponding to the identified logical device based upon the step of determining operating validity during normal operations, and ii) in response to a successful verification, blocking I/O requests to the identified logical device to enable the exchange of the information in each control block associated with the logical devices corresponding to the identified logical device in the first and second pluralities of logical devices, said blocking being terminated after the exchange whereby subsequent processor I/O requests to the identified logical device are directed to the corresponding logical device in the second plurality of logical devices.