Patent ID: 8652929

Claim:
A fabrication method of a CMOS device for reducing a charge sharing effect in a radiation environment, wherein, comprising: 1) providing a silicon wafer as a substrate ( 1 ), and polishing a front surface of the substrate into a mirror surface, and after a typical cleaning process, evaporating aluminum on a back surface of the substrate to form an aluminum film as an ohmic contact, and coating an acid-proofing protection layer over the aluminum film; 2) putting the silicon wafer into a mixed solution of hydrofluoric acid and ethanol, and using the aluminum film on the back surface of the substrate as an anode and using a platinum slice as a cathode, etching the silicon wafer with a constant current, picking out the silicon wafer after etching and performing a cleaning process, etching the aluminum on the back surface of the silicon wafer, and forming a layer of porous silicon to form an additional isolation region ( 3 ); 3) growing a silicon oxide layer over the additional isolation through a thermal oxidation process and performing an etching process after a photolithography process to form an isolation region ( 4 ) of a device; 4) epitaxially growing a semiconductor material layer, and planarizing the semiconductor material layer to form an active region ( 5 ) of the device; 5) thermally oxidizing a thin gate dielectric material layer and forming a gate dielectric of the device after a photolithography process; 6) growing a mask oxide layer and depositing a material of a gate, forming a gate pattern after a photolithography process, etching the material of the gate to form a gate region ( 6 ) of the device; 7) forming a LDD region ( 7 ) by performing an implantation process; 8) depositing a material of a gate sidewall, and performing an anisotropic etching to form a gate sidewall ( 8 ); 9) forming a source and drain region ( 9 ) by performing a source and drain implantation, and performing an annealing process to activate impurities.