Patent ID: 7072206

Claim:
A semiconductor integrated device comprising: a first bit line; a second bit line; a first word line; a second word line; a memory cell group having a first memory cell and a second memory cell, wherein each memory cell is connected to the first and second bit lines and the first and second word lines, wherein each of the memory cells comprise a first inverter having a first input node and a first output node, a second inverter having a second input node and a second output node, wherein the first input node of the first inverter is connected to the second output node of the second inverter, and the first output node of the first inverter is connected to the second input node of the second inverter, a first switch connected to the first input node of the first inverter, the first bit line and the first word line, wherein the first switch electrically connects the first input node to the first bit line during a first operation, and a second switch connected to the second input node of the second inverter, the second bit line and the second word line, wherein the second switch electrically connects the second input node and the second bit line during the first operation and during a second operation; and an output circuit connected to the first and second bit lines, wherein the output circuit outputs a bit information when a signal from either of the bit lines is latched.