Patent ID: 6977226

Claim:
A method for fabricating a semiconductor memory device including a cell region and a peripheral circuit region, the method comprising: forming a plurality of line patterns in the cell region and the peripheral circuit region, each being formed by stacking a conductive layer, an insulating hard mask, and a spacer allocated at sidewalls of each of the line patterns; removing the entire insulating hard mask and the entire spacer formed in the peripheral circuit region; forming a conductive spacer at sidewalls of each line pattern in the peripheral circuit region, wherein a spacing distance between the line patterns is at least onefold greater than a width of the line pattern; forming an insulation layer on an entire surface of the resulting structure; forming a photoresist pattern for forming a contact hole exposing the conductive layer on the insulation layer; and forming a deep contact hole exposing the conductive layer by etching the insulation layer with use of the photoresist pattern as an etch mask.