Patent ID: 7662669

Claim:
A method for fabricating wafer-level packages comprising: providing a cover wafer including a first surface and a second surface; depositing a plurality of cover wafer rings on the first surface of the cover wafer; precutting the cover wafer through the first surface and partially through the cover wafer so as to provide precuts at a plurality of predetermined locations; providing a substrate wafer; fabricating a plurality of integrated circuits on the substrate wafer; depositing a substrate wafer ring around one or more integrated circuits on the substrate wafer; providing a lateral interconnect from one or more integrated circuits through its associated substrate wafer ring; bonding the substrate wafer rings to the cover wafer rings to provide bonding rings that define cavities between the cover wafer and the substrate wafer in which the integrated circuits are provided; cutting the cover wafer through the second surface of the cover wafer at the locations where the precuts are provided so as to remove portions of the cover wafer between adjacent precuts and between the bonding rings and exposing the lateral interconnects where the lateral interconnects are laterally spaced from the cuts; and cutting the substrate wafer between the bonding rings and laterally adjacent to the lateral interconnects so as to separate wafer-level packages.