Patent ID: 7888219

Claim:
A method of forming a non-volatile memory device, the method comprising: forming a tunnel insulating layer on a semiconductor substrate, wherein the semiconductor substrate comprises a cell array region and a peripheral circuit region; forming a charge-trap layer on the tunnel insulating layer; forming a trench extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layer remain on opposite sides of the trench; forming a device isolation layer in the trench; removing portions of the charge-trap layer on the peripheral circuit region of the semiconductor substrate while maintaining portions of the charge-trap layer on the cell array region of the semiconductor substrate; after removing portions of the charge-trap layer, forming a blocking insulating layer on the device isolation layer and on remaining portions of the charge-trap layer; forming a gate electrode on the blocking insulating layer; and patterning the blocking insulating layer and remaining portions of the charge-trap layer to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.