Patent ID: 7125808

Claim:
A method for manufacturing non-volatile memory cells on a semiconductive substrate, comprising at least the following steps: forming active areas in said semiconductive substrate, bounded by portions of an insulating layer; forming a first thin layer of tunnel oxide and depositing a first layer of conductive material on said active areas; defining a plurality of floating gate regions, wherein the definition of the floating gate regions comprises the steps of: forming a plurality of alternated stripes of a first material above active areas alternated by active areas lacking stripes; forming spacers of a second material in the shelter of the side walls of said stripes, said second material being selectively etchable with respect to said first material, depositing a layer of a third material in order to fill in the space between said spacers, polishing said layer of a third material together with said alternated stripes and said spacers to the same planar level, selectively removing said spacers in order to expose portions of said first layer of semiconductive material, etching said first layer of semiconductive material in order to form grooves in correspondence with its exposed portions, selectively removing said alternated stripes and said layer of a third material.