Patent ID: 8284377

Claim:
A display device comprising: a first gate line; and two gate-on-array circuits arranged at two opposite sides of the first gate line, each of the gate-on-array circuits comprising a first stage electrically coupled to the first gate line; wherein each of the first stages comprises: a first transistor, the first source/drain electrode of the first transistor being electrically coupled to the first gate line and acts as an output terminal of the first stage, and the second source/drain electrode of the first transistor being electrically coupled to receive a clock pulse signal; and a repair circuit including a first terminal, a second terminal and at least one control terminal, the first terminal of the repair circuit being electrically coupled to the gate electrode of the first transistor, the second terminal of the repair circuit being electrically coupled to a predetermined potential, and the at least one control terminal of the repair circuit being adapted to receive at least one repair signal to pull a potential on the gate electrode of the first transistor to the predetermined potential and thereby the first transistor is maintained at off-state when the at least one repair signal is supplied to the repair circuit, the at least one control terminal being preset to be electrically disconnected with the at least one repair signal.