Patent ID: 7485533

Claim:
A method for fabricating a non-volatile memory, the method comprising: forming sequentially a tunneling layer, a charge-trapping layer, a barrier layer and a control gate layer on a substrate; forming a first mask layer on the control gate layer, wherein the first mask layer comprises a first opening that exposes a region predetermined for forming the memory; forming a second mask layer on a sidewall of the first opening; removing portions of the control gate layer, the barrier layer, the charge-trapping layer and the tunneling layer to form a second opening through the control gate layer, the barrier layer, the charge-trapping layer and the tunneling layer, using the first and the second mask layers as a mask; removing the first and the second mask layers; forming an insulation layer on a surface of the second opening; forming a conductive layer to fill the second opening; forming a third mask on the control gate layer, the insulation layer and the conductive layer; defining a gate stacked structure using the third mask layer; and removing the third mask layer.