Patent ID: 8344496

Claim:
An integrated circuit chip, comprising: a plurality of conducting pads on a first surface of the integrated circuit for providing power and ground, the plurality of conducting pads located in a periphery region of the integrated circuit chip; a first plurality of through-silicon-vias within the periphery region of the integrated circuit chip; a second plurality of through-silicon-vias within a non-periphery region of the integrated circuit chip; and a first conducting line providing electrical communication between one of the first plurality of through-silicon-vias and one of the second plurality of through-silicon-vias, the first conducting line extending along a second surface of the integrated circuit chip from the one of the first plurality of through-silicon-vias to the one of the second plurality of through-silicon-vias, the second surface opposing the first surface, wherein each via of the first plurality of through-silicon-vias and the second plurality of the through silicon vias extend from the first surface to the second surface and wherein one of power and ground is supplied to a plurality of circuits located within the non-periphery region of the integrated circuit chip through a path defined by the one of the first plurality of through-silicon-vias, the first conducting line, and the one of the second plurality of through-silicon-vias.