Patent ID: 7348790

Claim:
An apparatus comprising: a number of Boundary Scan terminals to receive Boundary Scan instruction; a number of functional terminals including a first functional terminal and a second functional terminal; a first driver coupled to a first supply node and the first functional terminal, the first driver including an output node coupled to the first functional terminal and responsive to the Boundary Scan instruction to couple the first functional terminal to the first supply node via a transistor of the first driver during a test; a first control node coupled to the first driver to enable the first driver to decouple the first functional terminal from the first supply node during the test to allow the first functional terminal to float for a time interval; a second driver coupled to a second supply node and the second functional terminal, the second driver including an output node coupled to the second functional terminal and responsive to the Boundary Scan instruction to couple the second functional terminal to the second supply node via a transistor of the second driver during the test; a second control node coupled to the second driver to enable the second driver to decouple the second functional terminal from the second supply node during the test to allow the second functional terminal to float for the time interval; an internal circuitry coupled to the first and second functional terminals to measure a voltage of at least one of the first and second functional terminals after the time interval.