Patent ID: 6963507

Claim:
A semiconductor device comprising a nonvolatile memory array and a central processing unit, wherein said nonvolatile memory array comprises a plurality of memory cells, a plurality of word lines, a plurality of data lines, and a control circuit, wherein each of said memory cells comprises a gate terminal, a first terminal and a second terminal, wherein each of said word lines is coupled to the gate terminals of corresponding ones of said memory cells, wherein each of said data lines is coupled to the first terminals of corresponding ones of said memory cells, wherein said central processing unit is capable of instructing a program operation to said nonvolatile memory array, and wherein in said program operation, said control circuit of said nonvolatile memory array selects one word line, supplies a program voltage to the selected word line, and supplies a first voltage for a first duration of time to a first data line coupled to a first memory cell to be subjected to programming, and supplies the first voltage for a second duration of time to a second data line coupled to a second memory cell to be subjected to programming after the start of supplying the first voltage to the first data line and before the completion of the first duration of time, regardless of whether one or more memory cells not to be subjected to programming are coupled to the selected word line between the first memory cell and the second memory cell.