Patent ID: 7888257

Claim:
A process for fabricating an integrated circuit package, said package comprising: 1) an integrated circuit die including a bonding pad array, 2) a substrate comprising electrical contact pads, and 3) electrical communication structures with pitch of 65 μm or less, said structures comprising an electrically conducting wire compression bonded to a bonding pad of said array and bonded to at least one of said contact pads; said process comprising: contacting said wire to said bonding pad, then applying a force such that said wire is compression bonded to said bonding pad, and then covering said die with a passivating material wherein: said bonding pad comprises aluminum deposited at least partially over a passivation structure, said bonding pad is surrounded by a partially overlaying passivation region, and the configuration of said bonding pad before applying said force is such that, after applying said force, crevice formation between said bonding pad and said wire is substantially avoided.