Patent ID: 8559220

Claim:
A semiconductor device comprising: a source line; a bit line; a first signal line; a plurality of second signal lines; a plurality of word lines; a plurality of memory cells connected in series between the source line and the bit line; a driver circuit configured to drive the plurality of second signal lines and the plurality of word lines so as to select a memory cell specified by an address signal; a writing circuit configured to output a writing potential to the first signal line; a reading circuit configured to compare a plurality of reading potentials and a bit line potential input from the bit line connected to the specified memory cell; a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the bit line potential and the plurality of reading potentials; and a potential generation circuit configured to generate the writing potential and the plurality of reading potentials to be supplied to the writing circuit and the reading circuit, wherein one of the plurality of memory cells comprises: a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and a capacitor, wherein a substrate including a semiconductor material is provided with the first transistor, wherein the second transistor includes an oxide semiconductor layer, and wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other, wherein the source line and the first source electrode are electrically connected to each other, wherein the bit line and the first drain electrode are electrically connected to each other, wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other, wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other, wherein one of the plurality of word lines and the other of the electrodes of the capacitor are electrically connected to each other, and wherein the oxide semiconductor layer is formed using an In—Ga—Zn—O-based oxide semiconductor material.