Patent ID: 7620046

Claim:
A network interface controller, comprising: an interface to a media access controller to receive ingress packets from a network connection; at least one interface to multiple processors commonly served by the network interface controller; and circuitry to: receive ingress packets from the media access controller and process respective ingress packets by: determining a first identifier for a respective ingress packet based at least in part on data fields within a header of the respective ingress packet; performing a lookup of a table based on the first identifier, the table associating identifiers with respective ones of the multiple processors commonly served by the network interface controller; and enqueuing the respective ingress packet for receipt by a one of the multiple processors associated with the identifier by the table; and receive egress packets from the multiple processors commonly served by the network interface controller and process respective egress packets by: determining a second identifier based at least in part on data fields within a header of a respective egress packet received from a one of the multiple processors; and modifying the table to associate the second identifier with the one of the multiple processors from which the egress packet was received, wherein subsequently received ingress packets belonging to a same flow as the egress packet are enqueued for receipt by the one of the multiple processors from which the egress packet was received; wherein each of the multiple processors is associated with a different receive queue and transmit queue pair; wherein the table associating respective identifiers with respective ones of the multiple processors commonly served by the network interface controller comprises a table associating respective identifiers with respective receive queue and transmit queue pairs associated with the respective multiple processors; wherein enqueueing the respective ingress packet for receipt by a one of the multiple processors comprises enqueuing the respective ingress packet to a receive queue of the receive queue and transmit queue pair associated with the one of the multiple processors; and wherein egress packets from the multiple processors are in enqueued in a transmit queue of the receive queue and transmit queue pair associated with the one of the multiple processor.