Patent ID: 8519432

Claim:
A semiconductor switch, comprising: a substrate; a first PNPN structure on said substrate; electrical contacts which provide anode, gate and cathode connections to said first PNPN structure; an external node; and a MOSFET on said substrate arranged to conduct a current between said external node and said electrical contact which provides said anode connection when on and to inhibit the current conducted between said external node and said electrical contact which provides said anode connection and thereby turn off said semiconductor switch when off, said first PNPN structure arranged to conduct a current between said electrical contact which provides said anode connection and said electrical contact which provides said cathode connection when a voltage lower than a threshold voltage is applied to said electrical contact which provides said gate connection to said first PNPN structure, and to maintain said current conduction via regenerative feedback when the voltage applied to said electrical contact which provides said gate connection to said first PNPN structure rises above said threshold voltage as long as said current conducted between said electrical contact which provides said anode connection and said electrical contact which provides said cathode connection is greater than a threshold current; wherein said first PNPN structure comprises parallel and adjacent stripe-shaped n-type and p-type planar regions formed in the top surface of said substrate, and wherein said MOSFET is a planar structure formed in the top surface of said substrate adjacent to said first PNPN structure and comprising parallel and adjacent stripe-shaped source, gate and drain planar regions, with the gate regions spaced apart from each other, such that, when the top surface of said substrate is viewed from above in a plan view, said first PNPN structure's parallel and adjacent stripe-shaped planar regions are oriented such that they are extended parallel to a first axis and said MOSFET is oriented such that said MOSFET's parallel and adjacent stripe-shaped source, gate and drain planar regions are extended perpendicular to said first axis, such that said first PNPN structure and said MOSFET structure can be sized independently.