Patent ID: 7501680

Claim:
A memory device, comprising: a source region and a drain region in a substrate, wherein the source and drain region are spaced apart from each other; a memory cell on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; and a control gate on the memory cell; wherein the memory cell includes a first tunneling oxide layer on the substrate, a second tunneling oxide layer on the first tunneling oxide layer, and a control oxide layer on the second tunneling oxide layer over the nanocrystals, further comprising an amino organic silane layer on the second tunneling oxide layer, wherein the amino organic silane layer is formed of an amino organic silane represented by Formula (1): wherein R 1 , R 2 and R 3 are each independently a hydrogen atom, a halogen atom, a C 1-5 alkyl group or a C 1-5 alkoxy group, and at least one of R 1 , R 2 , and R 3 is a halogen atom or a C 1-5 alkoxy group; R 4 and R 5 are each independently a hydrogen atom, NH 2 CH 2 CH 2 —(NHCH 2 CH 2 ) x —, an aliphatic alkyl group including at least one nitrogen atom, or a cyclo alkyl including at least one nitrogen atom, wherein x is an integer from 0 to 10; and n is an integer from 3 to 20.