Patent ID: 7626225

Claim:
A semiconductor device including a nonvolatile memory element, the nonvolatile memory element, comprising: a first region, a second region formed adjacent to the first region, and a third region formed adjacent to the second region; the nonvolatile memory element further including a semiconductor layer, a separating insulation layer which is formed in the semiconductor layer and which demarcates a forming region of the nonvolatile memory element, a first well which is formed in the semiconductor layer of the first region, a first source region and a first drain region formed within the first well, a second well which is separated from the first well, which surrounds the first well, and which is formed on a periphery of the first well and in the semiconductor layer of the second region, a second source region and a second drain region formed within the second well, a third well formed in the semiconductor layer of the third region, a first insulation layer formed above the semiconductor layer of the forming region of the nonvolatile memory element that continuously crosses the first, second, and third regions, and a first conductive layer formed above the first insulation layer functioning as a floating gate electrode that continuously crosses the first, second, and third regions, a first area where the first conductive layer overlaps the third well being greater than a second area where the first conductive layer overlaps the semiconductor layer of the second region, the third well and the second well being made continuous with each other.