Patent ID: 8232161

Claim:
A method for manufacturing a semiconductor device including a trench gate type MISFET having a p-type channel and a resistive element provided between a gate pad and a gate electrode of the trench gate type MISFET, comprising the steps of: (a) forming a p-type semiconductor region over a semiconductor substrate; (b) forming a trench in the p-type semiconductor region; (c) forming a gate insulating film over an inner wall of the trench; (d) forming a gate electrode so as to bury the trench; (e) forming an n-type channel forming area in an area shallower than the trench of the p-type semiconductor region; (f) forming a p-type source region in a surface region shallower than the bottom of the n-type channel forming area; (g) forming a first n-type semiconductor region in the n-type channel forming area; and (h) forming a second n-type semiconductor region in an area deeper than the first n-type semiconductor region and shallower than the bottom of the trench, wherein an impurity concentration of the second n-type semiconductor region is lower than that of the first n-type and higher than that of the n-type channel forming area.