Patent ID: 7176583

Claim:
A solder bump connection at a surface of a metallic bonding pad of a semiconductor chip comprising: a patterned passivation layer formed upon said metal bonding pad surface, said patterned passivation layer including an opening at said metal bonding pad surface defining a location for said solder bump connection; a barrier material stack formed above said patterned passivation layer and including top and bottom conductive material layers, portions of said top conductive material layer portion adjacent said solder bump connection being removed such that a top conductive material layer at said solder bump connection location includes a surface that is substantially coplanar with a surface of remaining bottom conductive material layer portions adjacent said solder bump connection location; a diffusion barrier layer formed upon said substantially coplanar surface at said solder bump connection location; and, a solder bump formed upon a surface of said diffusion barrier layer, wherein portions of said bottom conductive material layer adjacent said solder bump connection exhibit decreased amount of undercut under said diffusion barrier layer to enable reduced pitch and increased mechanical stability of said solder bump connection.