Patent ID: 7521741

Claim:
A semiconductor structure comprising: a substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the substrate; a second HVW region of the first conductivity type overlying the substrate; a third HVW region overlying the substrate, wherein the third HVW region is of a second conductivity type opposite the first conductivity type, and wherein the third HVW region has at least a portion between the first HVW region and the second HVW region; an insulation region in the first HVW region, the second HVW region, and the third HVW region; a gate dielectric over and extending from the first HVW region to the second HVW region; a gate electrode on the gate dielectric; a shielding pattern over the insulation region, wherein the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm; a source region and a drain region adjacent the gate electrode; a source contact plug over, and electrically connected to, the source region; and a drain contact plus over, and electrically connected to, the drain region, wherein the shielding pattern is electrically disconnected from the gate electrode, the source region, and the drain region.