Patent ID: 7663192

Claim:
A CMOS device comprising: an NMOS transistor comprising: a first gate electrode; a first gate insulator under the first gate electrode, the first gate insulator defining a first gate insulator plane; a first source region and a first drain region, both of which have a first portion below the first gate insulator plane and a second portion above the first gate insulator plane; a first electrically insulating material above the first gate insulator plane; a first source contact extending through the first electrically insulating material and terminating in the second portion of the first source region and a first drain contact extending through the first electrically insulating material and terminating in the second portion of the first drain region; and a first blocking layer having a first portion between the first gate electrode and the first source contact and a second portion between the first gate electrode and the first drain contact; and a PMOS transistor comprising: a second gate electrode; a second gate insulator under the second gate electrode, the second gate insulator defining a second gate insulator plane; a second source region and a second drain region, both of which have a first portion below the second gate insulator plane and a second portion above the second gate insulator plane; a second electrically insulating material above the second gate insulator plane; a second source contact extending through the second electrically insulating material and terminating in the second portion of the second source region and a second drain contact extending through the second electrically insulating material and terminating in the second portion of the second drain region; and a second blocking layer having a first portion between the second source region and the second electrically insulating material and a second portion between the second drain region and the second electrically insulating material.