Patent ID: 8754671

Claim:
A field programmable gate array (FPGA), comprising: a switching block routing array comprised of a set of signal inputs and a set of signal outputs; a transistor element having a first terminal connected to one of the set of signal inputs and a second terminal connected to one of the set of signal outputs; a plurality of resistive elements comprising a first resistive element and a second resistive element configured to be dynamically programmed to activate or deactivate the transistor element; a shared node connected to a second terminal of the first resistive element, connected to a first terminal of the second resistive element, and connected to a gate of the transistor element; and a programming circuit having an output contact exclusive to the shared node of the first resistive element and the second resistive element and electrically connected to the shared node via a path that is independent of the first resistive element and the second resistive element, wherein a voltage applied by the output contact at the shared node facilitates dynamic programming of the first resistive element or the second resistive element.