Patent ID: 8273623

Claim:
A method of forming an integrated circuit including a transistor and a capacitor, comprising: forming a first doped well region in a transistor region and a second doped well region in a capacitor region of a semiconductor substrate using first shared processing steps, the second doped well region defining a first capacitor plate; forming a field oxide layer over the second doped well region; forming a gate structure for the transistor over the first doped well region; forming a first interlevel dielectric layer over the field oxide layer and over the gate structure; forming a conductive lead above the first interlevel dielectric layer to provide an electrical connection for the transistor; forming a second interlevel dielectric layer over the first interlevel dielectric layer including over the conductive lead; forming a protective overcoat layer over the second interlevel dielectric; forming an opening through the protective overcoat and the second interlevel layer down to the conductive lead, using at least two photomask patterning and etching steps; and forming a second capacitor plate over the protective overcoat layer over the second doped well region, and forming a conductive feature over the protective overcoat layer and within the opening in the transistor region using second shared processing steps.