Patent ID: 7250347

Claim:
A semiconductor structure fabrication method, comprising the steps of: (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) a semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film, and wherein an intersecting plane intersects both the gate electrode region and the semiconductor region such that in the intersection plane, a first common interfacing surface of the intersecting plane and the gate electrode region forms a closed loop around a second common interfacing surface of the intersecting plane and the semiconductor region; and then (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically discounected from each other.