Patent ID: 8513738

Claim:
A device structure for protecting an integrated circuit from an electrostatic discharge (ESD) event, the device structure comprising: a plurality of dielectric regions comprised of a dielectric material and defining an inner perimeter surrounding a device region comprised of a semiconductor material having a first conductivity type; a first field-effect transistor including a drain comprised of a first portion of a first doped region in the device region, the first doped region having a second conductivity type opposite to the first conductivity type; a first isolation region comprised of the dielectric material and projecting from the inner perimeter of one of the dielectric regions into the first doped region; and a diffusion resistor comprised of a second portion of the first doped region that defines a body having a higher electrical resistance than the first portion of the first doped region, the drain of the first field-effect transistor directly coupled with the body of the diffusion resistor, wherein the first isolation region narrows a cross-sectional area of the second portion of the first doped region relative to the first portion of the first doped region to form the body of the diffusion resistor.