Patent ID: 7501884

Claim:
A capacitive circuit for use in a semiconductor device, the circuit comprising: a first plurality of low voltage MOSFETs each having their respective source and drain electrically coupled together, the first plurality of MOSFETs series-coupled to each other by electrically coupling a gate of one of the plurality to the coupled source/drain of another of the first plurality; a high voltage power supply electrically coupled to the first plurality of low voltage MOSFETs to provide a voltage higher than a maximum operating voltage of any one of the first plurality of low voltage MOSFETs, wherein a coupled source/drain of one of the first plurality of MOSFETs at a first end of the series electrically coupled to a first terminal of the the power supply, and a gate of another of the first plurality of MOSFETs at a second end of the series is electrically coupled to a second terminal of the power supply; and a plurality of resistive elements each electrically parallel-coupled across corresponding ones of the plurality of MOSFETs, the plurality of resistive elements comprising a second plurality of low voltage MOSFETs each having a gate and one of a source and drain electrically coupled together, the gate and the one of the source and drain of each of the second plurality electrically coupled to the gate of a corresponding one of the first plurality of low voltage MOSFETs, and the other of the source and drain of each of the second plurality electrically coupled to the coupled source/drain of the corresponding one of the first plurality of low voltage MOSFETs, wherein an equivalent capacitance of the coupled first plurality of low voltage MOSFETs is sufficient to operate under the voltage provided by the power supply.