Patent ID: 7851305

Claim:
A method of manufacturing a NAND nonvolatile semiconductor memory which involves forming a bit line contact between adjacent select transistors of the NAND nonvolatile semiconductor memory, the method comprising: patterning memory cells and said select transistors of said NAND nonvolatile semiconductor memory; forming a first insulating film between adjacent two of said memory cells, between said memory cells and said select transistors, and between adjacent two of said select transistors; selectively etching the first insulating film between said select transistors to form a side wall spacer on each of said select transistors; forming a second insulating film on said memory cells, said first insulating film between said memory cells, said select transistors and said side wall spacers; forming a resist pattern on said second insulating film; simultaneously forming a first opening in an insulating film and a control gate on a floating gate of each of said select transistors using said resist pattern and a second opening between said adjacent select transistors using said resist pattern; and simultaneously embedding a conductive film in said first and second openings to form a connection layer that electrically connects the floating gate and the control gate of each of said select transistors to each other and to form said bit line contact between said adjacent select transistors.