Patent ID: 7087472

Claim:
A method of making a semiconductor device comprising the steps of: providing a body of semiconductor material comprising a first conductivity type, wherein the body of semiconductor material has an upper surface and a lower surface opposing the upper surface, wherein a portion of the body of semiconductor material forms a drain region, and wherein the lower surface provides a drain contact; forming a first trench in the body of semiconductor material and extending from the upper surface, wherein the first trench has a first width, a first depth from the upper surface, first sidewalls, and a first bottom surface; forming a second trench within the first trench, wherein the second trench has a second width, a second depth from the first surface, second sidewalls and a second bottom surface; forming a first source region in the body of semiconductor material extending from the upper surface and spaced apart from the first trench by a portion of the body of semiconductor material; introducing a dopant of a second conductivity type into at least a portion of the second sidewalls and the second bottom surface to form a doped trench gate region, wherein the doped trench gate region extends into the body of semiconductor material for controlling conduction in the device and wherein the drain region, the first source region, and the doped trench gate region form a vertical juntion FET device; forming a first passivation layer over the doped trench gate region; and forming a second passivation layer over the first passivation layer thereby filling at least the second trench.