Patent ID: 7354854

Claim:
A method of making an integrated circuit including nickel silicide contact regions, comprising: (a) providing an integrated circuit structure including a silicon layer having a surface, a source region and a drain region of a transistor disposed in the silicon layer at its surface, a gate dielectric layer disposed on the surface of the silicon layer on an area located between the source region and the drain region, a polycrystalline silicon gate electrode disposed on the gate dielectric layer, a first dielectric spacer disposed on the surface of the silicon layer along an edge of the polycrystalline silicon gate electrode, and a second dielectric spacer disposed on the surface of the silicon layer along another edge of the polycrystalline silicon gate electrode, and a layer of a oxide and an opening in the layer of oxide exposing the source and a drain regions and also exposing at least a portion of the polycrystalline silicon gate electrode and also exposing surfaces of the first and second dielectric spacers; (b) forming a nickel layer on an exposed surface of the integrated circuit structure; (c) performing a first anneal to cause formation of first and second nickel silicide regions in surface portions of the source and drain regions, respectively, in contact with the nickel layer and to cause formation of a third nickel silicide region in the portion of the polycrystalline silicon gate electrode in contact with the nickel layer; (d) using a chrome etchant to perform an etch back operation to remove un-reacted nickel from the integrated circuit structure and to remove all nickel and/or nickel remnants from the exposed surfaces of the first and second dielectric spacers wherein the chrome etchant includes cerric ammonium nitrate, nitric acid, and acetic acid, the etch back operation including using the chrome etchant to remove all un-reacted nickel and any nickel precipitates from the integrated circuit structure.