Patent ID: 7911909

Claim:
A jitter counter which is connected to a PLL circuit for generating a clock signal, which is necessary for signal processing, from a binary signal, and counts jitters of the binary signal, the jitter counter comprising: a determination signal generation circuit which generates a determination signal that has a given pulse width having the phase center at the position of a pulse edge of the clock signal by using an output signal from a voltage controlled oscillator constituting the PLL circuit, or using a frequency divided signal obtained by dividing the frequency of the output signal from the voltage controlled oscillator, or using output signals from the respective stages of a ring oscillator constituting the voltage controlled oscillator; a phase determination circuit which at every time when logic inversion of the binary signal occurs, determines whether or not the inversion position is present in a determination section given by the pulse width of the determination signal based on an output signal from a phase comparator constituting the PLL circuit and on the determination signal; a phase counter which based on an output signal from the phase determination circuit, counts the number of times that inversion positions of the binary signal are not present in the determination section or times that inversion positions of the binary signal are present in the determination section, wherein the jitter counter outputs a count value of the phase counter as a jitter count value.