Patent ID: 7876602

Claim:
A memory cell adapted to be coupled to first and second reference voltages, the memory cell comprising: a first inverter having a first switching element of a first conductivity type and second and third switching elements of a second conductivity type, each of said switching elements having a respective control node; a second inverter having a first switching element of said first conductivity type and second and third switching elements of said second conductivity type, each of said switching elements having a respective control node; a first output node of the first inverter connected to the respective control nodes of the first, second, and third switching elements of the second inverter; a second output node of the second inverter connected to the respective control nodes of the first, second, and third switching elements of the first inverter; a first access transistor having a control node and a first conduction node connected to said first output node; a second access transistor having a control node and a first conduction node connected to said second output node; a first capacitive element coupled between said second reference voltage and the control nodes of the first, second and third switching elements of said first inverter; and a second capacitive element coupled between said second reference voltage and the control nodes of the first, second and third switching elements of said second inverter.