Patent ID: 7711933

Claim:
A programmable device comprising: a processing core; an internal configuration access port coupled to the processing core; a plurality of configuration memory cells coupled to the internal configuration access port; and a memory management unit coupled between the processing core and the internal configuration access port; wherein the processing core is configured to access a first subset of the plurality of configuration memory cells as read/write memory, the first subset comprising configuration memory cells that can be set or reset without changing the function of the configured circuits of the programmable device, and wherein the memory management unit maps the first subset of the plurality of configuration memory cells into a memory space of the processing core; wherein the memory management unit translates memory accesses from the processor core to a protocol used in programmable elements for accessing the plurality of configuration memory cells through the internal configuration access port; wherein, when using the memory management unit, the processing core uses memory calls to access the plurality of configuration memory cells without being specially modified to use the protocol of the programmable elements for accessing the plurality of configuration memory cells; wherein the first subset of the plurality of configuration memory cells is configured with predetermined user data and wherein the processing core is configured to access the first subset of the plurality of configuration memory cells as read-only memory.