Patent ID: 8704810

Claim:
A semiconductor device comprising: a first region including first, second, third, and fourth transistors, arranged in a 2×2 matrix, wherein, relating to a row and a column of the 2×2 matrix in which the first transistor is arranged, the second transistor is arranged in the same row and the other column, the third transistor is arranged in the other row and the same column, and the fourth transistor is arranged in the other row and the other column; first and second signal lines arranged on a first interconnect layer, the first and second signal lines being separated to each other and extended in the row direction over the 2×2 matrix; and third and fourth signal lines arranged on a second interconnect layer which is different from the first interconnect layer, the third and fourth signal lines being separated to each other and extended in the row direction over the 2×2 matrix, the first and second signal lines and the third and fourth signal lines being provided in association with the first region; the first transistor having a first impurity diffusion layer connected to the first signal line on the first interconnect layer, the second transistor having a first impurity diffusion layer connected to the third signal line on the second interconnect layer, the third transistor having a first impurity diffusion layer connected to the fourth signal line on the second interconnect layer, and the fourth transistor having a first impurity diffusion layer connected to the second signal line on the first interconnect layer, wherein the first and third transistors have respective gate electrodes connected in common to a first binary input signal, the second and fourth transistors have respective gate electrodes connected in common to a second binary input signal, the first and second input signals are complementary to each other, the first and second transistors have second impurity diffusion layers coupled together at a first node, a signal on the first signal line or the third signal line being transmitted to the first node via the first or second transistor which is made conductive responsive to the first and second binary input signals, and the third and fourth transistors have second impurity diffusion layers coupled together at a second node, a signal on the second signal line or the fourth signal line being transmitted to the second node via the third or fourth transistor which is made conductive responsive to the first and second binary input signals.