Patent ID: 8225045

Claim:
A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches, said method comprising: installing each of a plurality of cache lines in a congruence class of the first lower level cache and recording, in the first lower level cache, an access chronology for the plurality of cache lines and a respective membership of each of the plurality of cache lines in one of a plurality of classes including at least a first class and a second class, wherein recording a respective membership includes recording membership in the first class for one or more cache lines of the congruence class installed in response to a first access by the first processing unit that missed in the first lower level cache and recording a respective membership in the second class for one or more cache lines of the congruence class for which a subsequent second access by the first processing unit resulted in a hit in the first lower level cache; thereafter, in response to a data request, selecting a victim cache line to be castout from the congruence class in the first lower level cache, wherein the selecting includes selecting the victim cache line from among one or more cache lines in the second class while excluding one or more cache lines in the first class from the selection; the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination of the victim cache line; and in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the first lower level cache and holding the victim cache line in the second lower level cache.