Patent ID: 7660963

Claim:
An interface device for a computer system comprising at least one master working with at least one slave configured to be readable and writable at chosen addresses, each master being configured to execute tasks and to deliver slave addresses for reading and/or writing purposes, wherein the interface device comprises: a group of first FIFO memories, wherein each first FIFO memory is assigned to one of said masters for storing data representative of executed tasks of the master; a group of dynamically allocatable second FIFO memories linkable to one another and to said first FIFO memories; and processing means configured to compute dynamically a FIFO memory size required by each of said masters at a given time, considering the importance of the tasks that the master is executing, and to allocate dynamically a number of second FIFO memories to each of said masters chosen according to the corresponding computed FIFO memory size, wherein said second FIFO memories have identical sizes, and said processing means is configured to determine the second FIFO memories to be allocated dynamically as a function of a working parameter representative of a processing speed, wherein said processing means is configured, in case of second FIFO memory allocation needs for at least two masters greater than the number of remaining second FIFO memories not yet allocated, to allocate said remaining second FIFO memories to a master for which exceeding of a threshold is detected earliest among the at least one masters during a bus observation window of the computer system.