Patent ID: 7647452

Claim:
A method for reducing power consumption of a cache, the cache adapted for use with a processor, the method comprising: requesting at least a portion of the cache to enter a low-power mode, the cache comprising a plurality of data entries and a plurality of tag entries, the tag entries in a one-to-one correspondence with the data entries, each of the data entries enabled to store a line of data, and each of the tag entries enabled to store a tag usable, at least in part, to identify any line of data stored in the corresponding data entry; archiving in a tag archive area, in response to the requesting, particular tags stored in at least some of the tag entries; reducing, in response to the requesting, power provided to at least some of the data entries; repopulating, after the act of reducing power, a subset of the tag entries from the tag archive area; and wherein the cache and the processor are implemented within one or more integrated circuits.