Patent ID: 7078936

Claim:
In an integrated circuit chip including a plurality of metal layers, first and second supply potentials and at least two adjacent logic blocks, a modifiable circuit for coupling the at least two adjacent logic blocks, comprising: a plurality of modifiable cycles formed between the at least two adjacent logic blocks, each modifiable cycle having a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein said first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks, and a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein said second metal interconnect structure is located at said boundary of the at least two adjacent logic blocks; wherein said first metal interconnect structure and said second metal interconnect structure are coupled together; and wherein a state of any modifiable cycle is repeatedly programmable by altering any one of the metal layers and/or any one of the vias.