Patent ID: 7768325

Claim:
A signal synchronization circuit comprising: a first signal path; a second signal path, wherein said first signal path and said second signal path each comprise: an input node; a first element that receives an input signal applied to said input node; a second element that receives an output signal from said first element; a multiplexor that receives said output signal from said first element and that further receives an output signal from said second element; a third element that receives an output signal from said multiplexor; and an output node that receives an output signal from said third element; a first XOR gate that receives said output signal from said second element of said first signal path and that receives said output signal from said third element of said first signal path, wherein an output signal from said first XOR gate controls said output signal from said multiplexor of said second signal path; and a second XOR gate that receives said output signal from said second element of said second signal path and that receives said output signal from said third element of said second signal path, wherein an output signal from said second XOR gate controls said output signal from said multiplexor of said first signal path.