Patent ID: 8482073

Claim:
An integrated circuit including a plurality of Fin field effect transistors (FINFETs), the integrated circuit comprising: a substrate; a plurality of fin-channel bodies over the substrate, the fin-channel bodies including a first fin-channel body and a second fin-channel body; a gate structure disposed over the fin-channel bodies; at least one first source/drain (S/D) region of a first FINFET adjacent the first fin-channel body; and at least one second S/D region of a second FINFET adjacent the second fin-channel body, wherein the at least one first S/D region is electrically coupled with the at least one second S/D region, and the at least one first and second S/D regions are substantially free from including the first fin-channel body and the second fin-channel body, wherein the at least one first and second S/D regions each includes a first epitaxial region over a second epitaxial region, the first epitaxial region and the second epitaxial region are disposed in at least one trench opening defined substantially parallel with the gate structure, and an entire lower interface between the first epitaxial region and the second epitaxial region is substantially flat.