Patent ID: 7505752

Claim:
A receiver (e.g., 100 ) comprising: a first receiver circuit (e.g., 108 ) adapted to receive a first input signal (e.g., I) and a second input signal (e.g., IN) and generate in response thereto a first intermediate signal (e.g., OUTA) and a second, intermediate signal (e.g., OUTAN); a second receiver circuit (e.g., 106 ) adapted to receive the first input signal and the second input signal and generate in response thereto a third intermediate signal (e.g., OUTB) and a fourth intermediate signal (e.g., OUTBN); and a mixer circuit (e.g., 110 ) adapted to combine (i) the first and third intermediate signals to generate a first output signal (e.g., OUT) and (ii) the second and fourth intermediate signals to generate a second output signal (e.g., OUTN), wherein: the first and second receiver circuits effectively operate over different ranges of common-mode voltages.