Patent ID: 8637864

Claim:
A semiconductor device comprising: a first electrode layer and a second electrode layer; an oxide semiconductor layer over the first electrode layer and the second electrode layer, wherein the oxide semiconductor layer includes a first region electrically connected to the first electrode layer, a second region electrically connected to the second electrode layer, and a channel formation region between the first region and the second region; a gate insulating layer over the oxide semiconductor layer; a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the channel formation region; a first insulating layer over the gate electrode layer; sidewall insulating layers covering side surfaces of the gate electrode layer and side surfaces of the first insulating layer; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor layer, side surfaces of the gate insulating layer, and side surfaces of the sidewall insulating layer; a second insulating layer over the source electrode layer and the drain electrode layer; a third insulating layer over the first insulating layer, the sidewall insulating layers, the source electrode layer, the drain electrode layer, and the second insulating layer; and a first wiring layer electrically connected to the first region through a first opening and a second wiring layer electrically connected to the second region through a second opening, wherein the first opening and the second opening are formed in the second insulating layer and the third insulating layer, and wherein heights of top surfaces of the source electrode layer and the drain electrode layer are lower than heights of top surfaces of the first insulating layer, the sidewall insulating layer, and the second insulating layer, and are higher than a height of a top surface of the gate electrode layer.