Patent ID: 7527188

Claim:
A process for fabricating an interconnect structure on an electronic device which comprises: forming an insulating material on a substrate, wherein said insulating material comprises at least one member selected from the group consisting of silicon dioxide, phosphosilicate glass, boron doped PSG, tetraethylorthosilicate and a low-k dielectric material and said low-k dielectric material comprises at least one member selected from the group consisting of CVD porous carbon-doped oxide, non-porous carbon-doped oxide, porous spin-on organo silicates, non-porous spin-on organo silicates, porous spin-on organic polymers and non-porous spin-on organic polymers; lithographically defining and forming recesses for lines and/or via in said insulating material in which interconnection conductor material will be deposited; depositing an interconnection conductor material comprising an alloy of silver and beryllium, wherein the amount of beryllium is about 0.2 to about 5% by weight; wherein the beryllium is deposited in recesses and the silver is deposited above the beryllium; and providing a silver seed layer between said beryllium and silver; selectively oxidizing the beryllium by annealing at temperatures of about 250° C. to about 500° C. in an oxidizing atmosphere containing an oxidizing agent having a partial pressure of about 10 −8 to about 1 Torr wherein the oxidizing agent comprises oxygen or water vapor thereby forming a layer of beryllium oxide on the alloy; and planarizing the resulting structure to provide electrical isolation of individual lines and/or vias.