Patent ID: 7812400

Claim:
A SRAM structure comprising: a semiconductor substrate comprising at least one SRAM cell; a first n-well region in the semiconductor substrate; a first p-well region in the semiconductor substrate; an insulating region between and adjoining the first n-well and the first p-well regions and having a top surface coplanar with a surface of the semiconductor substrate; a gate dielectric layer on the first n-well and the first p-well regions; and a first gate electrode strip on the gate dielectric layer and extending from over the first p-well region to over the first n-well region, wherein the first gate electrode strip comprises a first portion over the first n-well region, a second portion over the first p-well region, and a third portion over the insulating region, wherein a thickness of the third portion is substantially less than thicknesses of the first and the second portions, the first gate electrode strip having a silicide layer, the silicide layer having a uniform thickness in the first portion, the second portion, and the third portion of the first gate electrode strip and directly contacting the first gate electrode strip.