Patent ID: 7423912

Claim:
A non-volatile memory array comprising: a plurality of PMOS SONOS non-volatile memory transistors arranged in an array of memory cells with a single SONOS transistor in each memory cell, each transistor having an upper programming threshold characteristic line with respect to charge retention time and a lower erase threshold characteristic line with respect to charge retention time that is a charge neutral flat characteristic line, the lines being separated by at least 0.5 volts at a retention time of 10 years and mutually convergent over the retention time, thereby defining a window, the programming and erase threshold characteristic line being negative over the retention time; and sense amplifier means for generating a read voltage represented by a characteristic line that is linear in said window with respect to retention time and is located at least 0.1 volts above the lower characteristic line at the retention time of 10 years.