Patent ID: 7148735

Claim:
A level shifter comprising: a first P-type transistor for receiving a first power supply voltage, a drain of the first P-type transistor electrically connected to a first node, wherein a gate terminal of the first P-type transistor receives an input signal; first and second N-type transistors serially connected to the first node, wherein a gate terminal of the first N-type transistor receives the input signal; a source of the second N-type transistor receives a reference voltage; and a gate terminal of the second N-type transistor receives a second power supply voltage; a first inverter receiving a signal supplied via the first node and outputting an inverted signal of the signal supplied via the first node in response to a voltage difference between the first power supply voltage and the reference voltage; a second P-type transistor for receiving the second power supply voltage, a drain of the second P-type transistor electrically connected to a second node and a third N-type transistor for receiving the reference voltage, a drain of the third N-type transistor electrically connected to the second node, wherein a gate terminal of the second P-type transistor is electrically connected to a third node and a gate terminal of the third N-type transistor is electrically connected to the first node; a third P-type transistor for receiving the second power supply voltage, a drain of the third P-type transistor electrically connected to the third node and a fourth N-type transistor for receiving the reference voltage, a drain of the fourth N-type transistor electrically connected to the third node, wherein a gate terminal of the third P-type transistor is electrically connected to the second node and a gate terminal of the fourth N-type transistor receives the inverted signal output by the first inverter; and a second inverter receiving a signal supplied via the third node and outputting an inverted signal of the signal supplied via the third node in response to a voltage difference between the second power supply voltage and the reference voltage as an output signal.