Patent ID: 7294890

Claim:
A fully salicided MOSFET structure, comprising: (a) a substrate having a channel bounded by doped source/drain (S/D) regions that are formed in an active area defined by isolation regions; (b) a patterned gate stack with two sides formed on said substrate wherein each side is abutted by a spacer having a top surface and a side, said gate stack is comprised of a gate dielectric layer formed on the substrate above the channel and an overlying and fully silicided gate electrode which is recessed below the top surface of the spacers by a certain distance; (c) an insulator block mask having two sides and a top surface which is formed on the substrate above the isolation regions; (d) a silicidation stop layer with a first thickness that is formed adjacent to one side of the insulator block mask, on the S/D region of the substrate between the insulator block mask and a spacer, and along the side of the spacer; and (e) a raised and fully silicided S/D element formed on the silicidation stop layer on either side of the fully silicided gate electrode and having a top surface that is essentially coplanar with the top surface of the spacers.