Patent ID: 7203816

Claim:
A multi-processor system apparatus having a plurality of processors connected to each other by a network arrangement, comprising: a multiplicity of processor elements, each processor element including a processor, a memory, and an interface for connection with said network arrangement; and an array of multi-stage interconnection networks having a multiple stage connection arrangement where multiple stages of switching elements are provided for interconnection between said processor elements, wherein said processor elements and said multi-stage interconnection networks are grouped to clusters based on a specific number and arranged in multiple levels and the transfer of data packets between said processor elements is conducted according to a schedule statically determined with the use of switching state tables which are generated at different timings and indicate the status of the switching elements in said multi-stage interconnection networks, wherein said multi-stage interconnection networks of a multiple stage connection arrangement, comprise two paths, respectively, of an upstream linking network for upward transfer of data packets from the lower stage to the upper stage and of a downstream linking network for downward transfer of data packets from the upper stage to the lower stage.