Patent ID: 6861317

Claim:
A method of forming a gate contact in a MOSFET device, the steps comprising: forming a first dielectric layer on a substrate, having oxide-filled isolation trenches, gate structure, sidewall passivation around gate, source and drain with lightly and heavily doped regions; planarizing said first dielectric layer and recessing said first dielectric layer below the level of said gate structure; forming a second dielectric etch stop layer over said first dielectric layer; planarizing said second dielectric layer in level with the gate structure; pattern said second dielectric layer, using oversize gate mask to leave said second dielectric layer around said gate structure; and forming electrical gate contact steps comprising: forming an inter-level dielectric layer over partially formed MOSFET device; patterning contact holes to source drain regions, patterning contact hole to gate stopping on said second dielectric layer; forming planarized metal patterns in and over said contact holes.