Patent ID: 7910485

Claim:
A method for forming a contact hole in a semiconductor device, the method comprising: forming a plurality of gate patterns over a substrate; forming a plurality of landing plugs between the gate patterns; forming an insulation layer over the substrate including the landing plugs; forming a hard mask layer over the insulation layer; forming a bit line contact mask over the hard mask layer; forming a hard mask pattern by etching the hard mask layer using the bit line contact mask; forming a first contact hole by partially etching the insulation layer using the hard mask pattern; forming a spacer on sidewalls of the first contact hole; forming a second contact hole to expose a surface of the landing plugs by etching the remaining insulation layer within the first contact hole; forming a third contact hole by horizontally etching the second contact hole, wherein a line width of the third contact hole is wider than that of the first contact hole; and removing the hard mask pattern and the spacer to form a bit line contact hole including the first and third contact holes, wherein the bit line contact mask is formed to have a small-sized develop inspection critical dimension (DICD) so as to prevent an overlap between the gate patterns and the second contact hole.