Patent ID: 8078791

Claim:
A data processing device, comprising: a memory that includes a plurality of banks; and a control block to: generate a refresh signal, determine an availability of the plurality of banks, determine an order for sending refresh requests to the plurality of banks based on the availability of the plurality of banks, where: the order is determined before sending the refresh requests to the plurality of banks, a first one of the plurality of banks is associated with a bank access delay that is greater than zero, and one or more second banks, of the plurality of banks, are placed, in the order, before the first one of the plurality of banks, where a number of the one or more second banks placed before the first one of the plurality of banks equals the bank access delay associated with the first one of the plurality of banks, and send a refresh request to each of the one or more second banks before sending a refresh request to the first one of the plurality of banks.