Patent ID: 7719449

Claim:
A system comprising: a serializer/deserializer (SERDES) block comprising a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block comprising a layout select tag, a first PCS lane operatively connected to the fourth SERDES lane, a second PCS lane operatively connected to the third SERDES lane, a third PCS lane operatively connected to the second SERDES lane, and a fourth PCS lane operatively connected to the first SERDES lane; a media access control (MAC) layer block comprising a first plurality of pins operatively connected to the first PCS lane, a second plurality of pins operatively connected to the second PCS lane, a third plurality of pins operatively connected to the third PCS lane, and a fourth plurality of pins operatively connected to the fourth PCS lane; a first differential lane operatively connected to the first SERDES lane; a second differential lane operatively connected to the second SERDES lane; a third differential lane operatively connected to the third SERDES lane; a fourth differential lane operatively connected to the fourth SERDES lane; and a device operatively connected to the first differential lane, the second differential lane, the third differential lane, and the fourth differential lane, wherein the device transmits a start of frame (SOF) delimiter on the first differential lane, wherein the value of the layout select tag is true, wherein the first SERDES lane is configured to serialize a plurality of data streams associated with the first PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on a value of the layout select tag.