Patent ID: 7692234

Claim:
A semiconductor device comprising: first MISFETs constituting memory cells arranged in a first direction and in a second direction crossing to the first direction; and selective MISFETs, wherein each of the first MISFETs includes a floating gate formed on a main surface of a semiconductor substrate through a first gate insulating film, a control gate electrode formed over an upper portion of the floating gate electrode through a first interlayer insulating film, a first semiconductor region and a second semiconductor region formed in the substrate and serving as source/drain regions, and a channel-forming region formed between the first semiconductor region and the second semiconductor region, wherein the first MISFETs adjoining in the second direction are isolated by a first insulating film filled in a groove formed in the semiconductor substrate, wherein a selective MISFET, of the selective MISFETs, includes a first gate electrode formed with the same level layer as the floating gate electrode, a second interlayer insulating film formed with the same level layer as the first interlayer insulating film, a second gate electrode formed with the same level layer as the control gate electrode, and a pair of third semiconductor regions formed in the substrate and serving as source/drain regions, wherein the selective MISFET is arranged in the first direction adjacent to a first MISFET, of the first MISFETs, such that the first semiconductor region of the first MISFET is electrically connected to one of the pair of the third semiconductor regions of the selective MISFET, wherein the selective MISFET includes a first region and a second region such that the first region and the second region are arranged in the first direction and such that, at the first region, the second gate electrode is formed over an upper portion of the first gate electrode through the second interlayer insulating film, and wherein, at the second region of the selective MISFET, the second interlayer insulating film is removed such that a bottom surface of the second gate electrode at the second region is lower than a bottom surface of the second gate electrode at the first region and such that a channel-forming region at the second region of the selective MISFET is in contact with the second semiconductor region.