Patent ID: 7659877

Claim:
A shift register comprising a plurality of stages each including: a flip-flop which is driven by a drive voltage higher than an amplitude of a clock signal, in order to serially transfer an input signal in sync with the clock signal; a level shifter which level-shifts the clock signal or an inversion signal which is an inversion of the clock signal, and supplies the level-shifted signal to the flip-flop; and a control circuits for controlling an operation time of the level shifter, at least an output signal or a signal which is an inversion of the output signal being supplied from the flip-flop of one stage to the control circuit of another stage, so that the input signal is serially transferred, in each of the stages, the control circuit controls the operation time of the level shifter to be shorter than a cycle of the clock signal, and wherein each control circuit respectively controls the operation time of the respective level shifters to be shorter than the cycle of the clock signal, and the control circuit for controlling the operation time of a given stage has an input directly connected to an output of the flip-flop of the previous stage.