Patent ID: 7420870

Claim:
A phase locked loop circuit, comprising: a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal; a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal; and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≧4) internal clock signals, wherein the voltage controlled oscillator circuit includes a hyper-ring oscillator, a frequency of the n internal clock signals is a multiple of a frequency of the external clock signal without using a divider and the n internal clock signals have different phases from one another and have the same phase difference and at least one of the n internal clock signals is used to generate the feedback clock signal and the feedback clock signal is locked with the external clock signal, and wherein the hyper-ring oscillator comprises at least two loops connecting inverting circuits as a ring-type, at least one of the inverting circuits is commonly connected to the at least two loops, and at least one of the n internal clock signals is generated by combining phases of output signals of at least two of the inverting circuits.