Patent ID: 8681560

Claim:
A non volatile memory device comprising: a plurality of memory cells; programming circuitry configured to select a group of memory cells, receive a first data word and program memory cells of the selected group based on the data word, said programming circuitry including a program circuit configured to receive at least one second data word, and, for each second data word, select a corresponding portion of memory cells of the group and send a program current in parallel to discriminated memory cells of the portion based on the corresponding second data word during a corresponding program phase, and an optimization circuit configured to generate said at least one second data word from the first data word, each of said at least one second data word causing during each program phase, the number of discriminated memory cells to be maximized compatibly with a maximum predetermined limit of the total program current provided by the program circuit, wherein the optimization circuit comprises a measure and filter circuit configured to determine a number of bits of the second data word to be programmed and to output the second data word to the program circuit, and a comparator circuit configured to compare the number of bits of the second data word to be programmed with the maximum predetermined limit and to provide a control signal to enable the measure and filter circuit to output the second data word to the program circuit when the number of bits to be programmed does not exceed the maximum predetermined limit.