Patent ID: 7305650

Claim:
A method for a behavioral synthesis process for realizing a digital logic circuit, the method comprising: identifying at least one subset from a behavioral algorithm that describes functions of the digital logic circuit, the subset including at least one of these functions; extracting the identified subset from a data structure representation of logical content of the behavioral algorithm; creating at least one customized building block component corresponding to the extracted subset, the customized building block component having an equal or greater number of functions at a lower level of abstraction relative to the extracted subset; and using the created customized building block component in the behavioral synthesis process in place of the extracted subset, including: providing a reference in the data structure representation, where the subset was extracted therefrom, that corresponds to the created customized building block component; providing the customized building block component and the data structure representation having the reference to the customized building block component to a scheduling and allocation process; and providing an output of the scheduling and allocation process to a subsequent level of abstraction in the behavioral synthesis process.