Patent ID: 7808856

Claim:
A method to reduce leakage of a Static Random Access Memory (SRAM) array comprising: subdividing the SRAM array into a plurality of sub-arrays; independently controlling the supply voltages of the subarrays; coupling the plurality of sub-arrays to a regulated virtual ground level having an electric potential higher than a system ground level; switching one or more of the plurality of subarrays from a power saving mode to a high performance mode by individually disconnecting them from the regulated virtual ground level and connecting them to system ground level, while maintaining other sub-arrays in the power saving mode; integrating an on-chip voltage regulator with the SRAM array capable of supplying a regulated virtual ground level higher than a system ground level to each of the plurality of sub arrays; employing a local read/write circuit as a level shifter between the virtual ground level and the system ground level; and decoupling one of the plurality of sub-arrays from a feedback network regulating the virtual ground level when switching from the power save mode to the high performance mode.