Patent ID: 8772095

Claim:
A method of manufacturing a semiconductor device, the method comprising: providing a structure that includes a substrate, and a gate electrode at an upper part of the substrate, the gate electrode having opposite sides; forming doped amorphous source/drain regions to the sides of the gate electrode, respectively, such that the amorphous source/drain regions are spaced from each other across a channel region of the substrate; subsequently annealing the substrate to recrystalize the doped amorphous source/drain regions; and before the substrate is annealed, forming over the doped amorphous source/drain regions of the substrate a stress inducing layer that stresses the doped amorphous source/drain regions during the recrystallizating of the doped amorphous source/drain regions, and wherein the forming of the doped amorphous source/drain regions comprises a pre-amorphization implantation (PAI) process that amorphizes the source/drain regions to the sides of the gate electrode, and implanting, into the amorphized source/drain regions, impurities that will minimize differences between crystal growth rates in different crystallographic directions during the annealing of the substrate.