Patent ID: 8627047

Claim:
A method for loading data in a pipelined microprocessor, the method comprising: issuing a load request that comprises a load address requiring at least one block of data, the at least one block of data the same size as a largest contiguous granularity of data returned from a cache; determining that the load address matches at least one block address in a store address queue, wherein determining that there is a match comprises using a cache index address for a comparison between the load address and an address in the store address queue; based on determining that there is an address match, performing a) through c): a) reading a data block from a buffer register designated by the matching address in the store address queue and sending the data block along with data from the cache to satisfy the load request for a most recent entry in the store address queue that matches the load address; b) comparing a unique set id of the data block to the set id of the matching address in the store address queue after sending the data block; c) based on determining that there is a set id match, continuing the load request, or, based on determining that there is not a set id match, setting a store-forwarding state of the matching address in the store address queue to no store-forwarding and rejecting the load request; and reading a data block from a cache based on the load address and sending the data block to satisfy the load request, based on determining that there is no address match.