Patent ID: 8433023

Claim:
A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory coupled to the processor bus adapted to allow data to be stored, the memory comprising: a command data latch circuit for storing a command data packet at a time determined from a command clock signal, the command data latch comprising: a latch circuit having a data input and a clock input, the data input being adapted to receive the command data packet and store the command data packet responsive to a clock signal applied to the clock input; and a clock generator circuit for generating a latch signal from a master clock signal, the clock generator circuit comprising: a first delay-lock loop having a first voltage controlled delay circuit receiving a reference clock signal and generating a sequence of clock signals which are increasingly delayed from the reference clock signal to a last clock signal by delaying the reference clock signal by respective delays that are a function of a first control signal, and a phase detector comparing the phase of first and second clock signals in the sequence and generating the first control signal as a function of the phase difference therebetween, the phase detector comprising: a first input configured to receive the first clock signal; a second input configured to receive the second clock signal; and a charge pump comprising an output terminal, a first current source, and a second current source, and wherein the charge pump is configured to cause the first and second current sources to bypass the output terminal responsive to the first and second clock signals being substantially in phase, wherein the charge pump comprises a first switching device and a second switching device coupled in series between the first current source and the output terminal, and wherein one of the first and second switching devices is configured to substantially prevent current flow between the first current source and the output terminal responsive to the first and second clock signals being in phase, and; wherein the charge pump comprises a third switching device and a fourth switching device coupled in series between the second current source and the output terminal, and wherein one of the third and fourth switching devices is configured to substantially prevent current flow between the second current source and the output terminal responsive to the first and second clock signals being in phase.