Patent ID: 7471568

Claim:
A method for operating a multi-level-cell (MLC) memory device, comprising a substrate; a gate electrode; and a charge trapping structure disposed between the substrate and the gate electrode and having a second bit operation window, the charge trapping structure having a first storage side space apart from a second storage side, the first storage side having m bits for 2 m multiple voltage threshold Vt distributions and a plurality of sensing windows, each sensing window in the first storage side defining a voltage margin between two voltage threshold Vt distributions; the method comprising: enlarging the second bit operation window by a hole injection that move holes to the charge trapping layer; and wherein the hole injection comprises one of applying a positive gate voltage to erase the memory device to a negative voltage level by moving holes from the gate electrode to the charge trapping structure, and of applying a negative gate voltage to erase the memory device to a negative voltage level by moving holes from the substrate to the charge trapping structure.