Patent ID: 7447876

Claim:
A microprocessor system, comprising: (A) an instruction fetch unit adapted to fetch instructions from an instruction store and to provide a predetermined plurality of the instructions to an instruction buffer; (B) an execution unit, coupled to the instruction fetch unit, adapted to execute a selected one or more of the plurality of instructions stored in the instruction buffer in an out-of-order fashion with respect to a predefined program order, the execution unit including a load store unit adapted to identify load requests to a memory system capable of being made out-of-order with respect to the predefined program order and to make identified load requests out-of-order, the load store unit further adapted to make store requests to the memory system, the load store unit comprising: (1) an address path adapted to manage a plurality of addresses associated with the plurality of instructions and to provide addresses to the memory system, the address path comprising: (a) a plurality of address buffers, each of the plurality of address buffers adapted to store an address of a first byte of an access associated with one of the load requests or one of the store requests, and an address of a last byte of the access associated with one of the load requests or one of the store requests, and (b) a pointer that indicates the relative age of a load request or a store request corresponding to an address stored in one of the plurality of address buffers, and (2) a data path adapted to transfer load data from the memory system to the execution unit and to transfer store data from the execution unit to said memory system.