Patent ID: 8593197

Claim:
A delay line circuit, comprising: a delay line section, receiving an input clock signal and a feedback clock signal and delaying one of the input clock signal and the feedback clock signal to generate an output clock signal, wherein the delay line section comprises a plurality of delay units coupled in series; and a feedback selection section, coupled to the delay line section and feedbacking the output clock signal to one of the delay units to serve as the feedback clock signal based on a selection signal, wherein one of the input clock signal and the feedback clock signal is delayed by a specific number of the delay units based on the selection signal to change the frequency of the output clock signal, wherein the selection signal comprises a plurality of multiplexing control signals, and the feedback selection section comprises: a plurality of multiplexer units, each of the multiplexer units comprising a first input terminal, a second input terminal, and an output terminal, and each of the multiplexer units controlled by the corresponding multiplexing control signals, wherein the first input terminal of a m-th multiplexer unit of the plurality of multiplexer units is coupled to a first one of the delay units, the output terminal of the m-th multiplexer unit is coupled to a second one of the delay units, and the second input terminal of the m-th multiplexer unit directly receives the output clock signal to serve as the feedback clock signal based on a m-th multiplexing control signal; and the first input terminal of a m+1-th multiplexer unit is coupled to a third one of the delay units, the output terminal of the m+1-th multiplexer unit is coupled to a fourth one of the delay units, and the second input terminal of the m+1-th multiplexer unit directly receives the output clock signal to serve as the feedback clock signal based on a m+1-th multiplexing control signal.