Patent ID: 7893718

Claim:
A multiplexer, comprising: a first N-to-1 selection circuit configured to route a true or complementary version of a selected first input signal to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one; a second N-to-1 selection circuit configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal; and an output driver comprising a pull-up circuit responsive to a signal generated at the output of said first N-to-1 selection circuit and a pull-down circuit responsive to a signal generated at the output of said second N-to-1 selection circuit; wherein said pull-down circuit comprises a first NMOS pull-down transistor having a gate terminal responsive to the signal generated at the output of said second N-to-1 selection circuit; and wherein said pull-up circuit comprises: a first PMOS pull-up transistor having a gate terminal responsive to the signal generated at the output of said first N-to-1 selection circuit; a second PMOS pull-up transistor having a source terminal electrically coupled to a drain terminal of the first PMOS pull-up transistor; and an NMOS node discharge transistor having a drain terminal electrically coupled to the source terminal of the second PMOS pull-up transistor and a gate terminal electrically connected to gate terminals of the first and second PMOS pull-up transistors.