Patent ID: 8110447

Claim:
A process for fabricating electronic packages containing a chip, the process comprising the steps of: patterning the bottom surface of a lead frame, the bottom surface being the opposite side of the lead frame from where the chip is mounted; etching the bottom surface in accordance with the bottom pattern, wherein a cavity in the bottom surface of the lead frame is formed by the etching; filling the bottom surface cavity with a pre-mold material; etching the top surface of the lead frame in accordance with a top pattern forming electrical conductive runs; etching the top surface between the runs, wherein the etching creates a top cavity that extends through the thickness of the lead frame to the pre-mold material, wherein the runs on the top surface are isolated and located to accommodate electrical connections to the chip; and thereafter: mounting the chip to the top surface of the lead frame; making electrical connections between the chip and the lead frame; and encapsulating the chip and lead frame.