Patent ID: 7305604

Claim:
A clock test circuit in an integrated circuit, comprising: a first clock network coupled to receive a first clock signal; a second clock network coupled to receive a second clock signal; a first double-data rate flip-flop having first data ports, first clock ports, a first reset port, and a first output port, the first double-data rate flip-flop coupled to receive the first clock signal from the first clock network to one of the first clock ports and coupled to receive the second clock signal from the second clock network to another one of the first clock ports, the one of the first clock ports associated with a logic low input to one of the first data ports, the other one of the first clock ports associated with a logic high input to another one of the first data ports; a second double-data rate flip-flop having second data ports, second clock ports, a second reset port, and a second output port, the second double-data rate flip-flop coupled to receive the first clock signal from the first clock network to one of the second clock ports and coupled to receive the second clock signal from the second clock network to another one of the second clock ports, the one of the second clock ports associated with a logic high input to one of the second data ports, the other one of the second clock ports associated with a logic low input to another one of the second data ports; a first flip-flop coupled to receive a first output from the first double-data rate flip-flop; and a second flip-flop coupled to receive a second output from the second double-data rate flip-flop.