Patent ID: 7733764

Claim:
A method of reducing data path latency in digitally processing a sequence of data samples, the data path latency being associated with a transient processing operation on the data samples, comprising: at the transition into the transient processing operation on the data samples reading the sequence of data samples into a tapped clocked delay chain, wherein each data storing element of the chain has an associated enabling signal for controlling, on any given clock cycle, whether to update or not its respective stored data sample; during the transient processing operation on the data samples, processing data samples from taps on the clocked delay chain; in response to receiving a signal of completion of the transient processing operation on the data samples, controlling the enabling signal of each data storing element in the chain to allow shifting data samples through an end portion of the clocked delay chain on a selected first set of clock cycles determining a first shifting rate and shifting data samples in an initial portion of the delay chain on a selected second set of clock cycles determining a second shifting rate, wherein the initial portion is complementary to the end portion and wherein the first shifting rate is higher than the second shifting rate; and dynamically reducing the length of the clocked delay chain by moving the output of the delay chain to the last data storing element of the initial portion, after a number of clock cycles.