Patent ID: 7936331

Claim:
A shift register having a plurality of stages which sequentially generate output signals in synchronization with a plurality of clock signals, wherein each of the stages comprises: a set terminal, a reset terminal, a gate voltage terminal, an output terminal and first and second clock terminals; an input unit for receiving a scan start signal or an output signal from a previous stage and outputting the scan start signal or the output signal as a first voltage; a first unit for passing at least two clock signals; a second unit for outputting at least one of the at least two clock signals or a second voltage in response to an output signal from a next stage; and an output unit for generating an output signal synchronized with at least one of the at least two clock signals in response to the outputs of the input unit and the second unit, wherein the input unit is connected between the set terminal and a first contact point and includes a first switching element having a control terminal connected to the set terminal, wherein the first unit comprises: a second switching element connected between the first clock terminal and a second contact point; and a third switching element connected between the second clock terminal and a third contact point, wherein a control terminal of the second switching element is connected to the first clock terminal, and a control terminal and an input terminal of the third switching element are directly connected to the second clock terminal.