Patent ID: 7355909

Claim:
A memory device, comprising: a memory array including a plurality of first array columns and a plurality of second array columns, wherein each of the first and second array columns are coupled to a plurality of memory cells, and wherein each of the first and second array columns are independently addressable; one or more column redundancy structures coupled to the memory array, each of the one or more column redundancy structures including a first redundancy column and a second redundancy column, wherein each of the first and second redundancy columns are independently addressable; and an array controller coupled to the memory array and the one or more column redundancy structures, the array controller operable to map the address of a first array column found to be defective to the address of the first redundancy column, and to map the address of a second array column found to be defective to the address of the second redundancy column, wherein the memory array further comprises a first reference column which substantially matches loading characteristics of one or more of the first array columns, the array controller further operable to map the address of the first reference column to the second redundancy column.