Patent ID: 7317343

Claim:
An integrated circuit having a pulse-generation circuit for generating at least two control signals, the pulse-generation circuit comprising: clock-delay circuitry connected to receive an input clock signal and generate a plurality of differently delayed clock signals; a plurality of pulse generators, each connected to receive a different clock signal from the clock-delay circuitry and generate a set signal or a reset signal having a pulse based on a transition in the received clock signal; and a plurality of set-reset latches, each connected to receive one of the set signals at its set input and one of the reset signals at its reset input and generate one of the control signals, wherein the clock-delay circuitry comprises: a delay block having a full set of inverters partitioned to form at least three cascaded delay sub-blocks, each delay sub-block comprising one or more series-connected inverters corresponding to a different subset of the inverters in the full set, the at least three delay sub-blocks comprising: a first delay sub-block that generates one or more delayed clock signals, each delayed clock signal corresponding to a different inverter output in the first delay sub-block; a second delay sub-block that is connected to the first delay sub-block and functions as an individually controllable semi-global delay element; and a third delay sub-block that is connected to the second delay sub-block and generates one or more other delayed clock signals, each other delayed clock signal corresponding to a different inverter output in the third delay sub-block; and at least one individually controllable mux that receives at least two delayed clock signals directly from the partitioned delay block and selects one of the at least two directly-received delayed clock signals as a clock signal for one of the pulse generators.