Patent ID: 6909135

Claim:
A semiconductor memory device comprising: a first transistor memory circuit including a first well region having a first conductivity type; a first impurity diffusion region on said first well region, wherein said first impurity diffusion region has a second conductivity type, different from the first conductivity type, as a first storage node of said first transistor memory circuit; a second well region adjacent to said first well region, said second well region having the second conductivity type; and a second impurity diffusion region on said second well region, said second impurity diffusion region having the first conductivity type, as a second storage node of said first transistor memory circuit, a third impurity diffusion region on said first well region, wherein said third impurity diffusion region has the second conductivity type, said third impurity diffusion region is not electrically connected to said first and second storage nodes, and no transistor element is located in said third impurity diffusion region; and a fourth impurity diffusion region on said second well region, wherein said fourth impurity diffusion region has the first conductivity type, said fourth impurity diffusion region is not electrically connected to said first and second storage nodes, and no transistor element is located in said fourth impurity diffusion region.