Patent ID: 7139208

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; an internal data bus for transferring data with a selected memory cell of said memory cell array; row select circuitry, activated in response to activation of an array activation instructing signal, for selecting a row in said memory cell array when activated, said row select circuitry selecting a first row of said memory cell array according to a first address and selecting a second row of said memory cell array according to a second address; a plurality of sense amplifiers, provided corresponding to said columns, activated in response to activation of said array activation instructing signal, for sensing, amplifying and latching data of corresponding columns; first column select circuitry, activated when a data rearrangement write instructing signal is deactivated, for selecting a column of said memory cell array on which a memory cell on said first row is located according to a column address signal to couple a selected column with said internal data bus when activated; rearrangement column select circuitry, activated when said data rearrangement write instructing signal is activated, for selecting a column of said memory cell array on which a memory cell on said second row is located according to said column address signal to couple a selected column with said internal data bus when activated; rearrangement control circuitry, activated when said data rearrangement write instructing signal is activated, for counting a number of times of column select operations of said rearrangement column select circuitry, and deferring ceasing a driving operation on the second row to a select state by said row select circuitry till said count value reaches a prescribed value; a preamplifier for amplifying the data on said internal data bus, said preamplifier latching output data thereof when a rearrangement operating mode instructing signal is activated; and a data buffer, activated when said data rearrangement write instructing signal is activated, for transferring the data outputted by said preamplifier onto said internal data bus.