Patent ID: 8295099

Claim:
A method of operating an integrated circuit (IC) comprising: providing the IC with a dual-port memory cell in a first state having a high voltage value at a first internal node of the dual port memory cell and a low voltage value at a second internal node of the dual port memory cell, a first bitline and a second bitline being selectively coupled to the first internal node and a first complementary bitline and a second complementary bitline being selectively coupled to the second internal node; reading a data value from the dual port memory cell during a clock cycle; generating an end-of-read signal; generating a WRITE assist pulse having a delay from the end-of-read signal and a duration; coupling a high voltage to each of the first bitline and the first complementary bitline of the dual port memory cell during the WRITE assist pulse; and writing a low voltage value to the first internal node and a high voltage value to the second internal node during the clock cycle.