Patent ID: 8379459

Claim:
A memory system comprising: a memory device configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock, the memory device comprising: a delay locked loop (DLL) in a power-off state for outputting the DLL clock in an unlocked state; a command interface for receiving a DLL power-on command, the DLL power-on command including instructions for performing a DLL initialization process to generate a DLL clock in a locked state and for configuring the memory device in a DLL on-mode to utilize the DLL clock as input to generating the read clock; and latency circuitry for delaying the configuring the memory device in a DLL on-mode until after a specified period of time has elapsed, the specified period of time relative to receiving the DLL power-on command, thereby allowing the memory device to service memory read commands in the DLL off-mode while the DLL initialization process is being performed.