Patent ID: 8242566

Claim:
An ESD clamp, comprising: a first bipolar transistor having a first emitter region, a first collector region, a first base region and a first base region to collector region spacing dimension D Z1 ; and further is adapted to have a first trigger voltage Vt 1 Z1 at D=D Z1 ; a second bipolar transistor series coupled to the first bipolar transistor and having a second emitter region, a second collector region, a second base region and a second base region to collector region spacing D Z2 or D Z3 ; and further is adapted to have a second trigger voltage Vt 1 Z2 or Vt 1 Z3 different than the first trigger voltage Vt 1 Z1 ; and wherein the first transistor is adapted to have a slope (ΔVt 1 /ΔD) Z1 at D=D Z1 and the second transistor is adapted to have a slope (ΔVt 1 /ΔD) Z2 at D=D Z2 or (ΔVt 1 /ΔD) Z3 at D=D Z3 , and wherein (ΔVt 1 /ΔD) Z1 is greater than (ΔVt 1 /ΔD) Z2 or (ΔVt 1 /ΔD) Z3 .