Patent ID: 7099182

Claim:
A static random access memory comprising a memory cell which comprises: a first inverter having a first load element and a first transistor, a first input terminal and a first output terminal, the first load element and the first transistor being connected between a first terminal and a second terminal in series, a first potential being applied to the second terminal at a time when data are read from the memory cell; a second inverter having a second load element and a second transistor, a second input terminal connected to the first output terminal and a second output terminal connected to the first input terminal, the second load element and the second transistor being connected between a third terminal and a fourth terminal in series, a second potential different from the first potential being applied to the fourth terminal at a time when data are read from the memory cell; a first transfer transistor which selectively and electrically connects the first output terminal and a first bit line; and a second transfer transistor which selectively and electrically connects the second output terminal and a second bit line.