Patent ID: 8028154

Claim:
A method for reducing storage space for instructions, the method comprising: storing new instructions in a nonvolatile random access memory; generating, within a network adapter chip, native processor machine language instructions from corresponding new instructions stored in the nonvolatile random access memory that is external to the network adapter chip, the new instructions comprising fewer bits than said native processor machine language instructions, the native processor machine language instructions being configured in a native processor machine language instruction format, the new instructions being configured into a patch code instruction format in which the new instructions do not comprise a native processor machine language, the patch code instruction format comprising a memory map format for use with the nonvolatile random access memory, the memory map format comprising a signature field, a format field, a flag field and a data block, the flag field comprising a first flag, a second flag and other flags, the first flag indicating that a service code patch is present in the data block, the second flag indicating that an initialization code patch is present in the data block, one or more of the other flags relating to power supplied to the network adapter chip, the new instructions being configured into the patch code instruction format to save memory space in the nonvolatile random access memory and being configured to modify boot functionality of a self boot code, said network adapter chip comprising a physical layer, a media access controller layer, a processor, a random access memory and a read only memory, the physical layer being connected to a gigabit Ethernet and handling voice and data traffic, the native processor machine language instructions resulting from decoding of the new instructions by the processor, the new instructions that are not able to be decoded by the processor being ignored without causing an interrupt or an exception, the read only memory providing the self boot code that generates said native processor machine language instructions from the corresponding new instructions stored in the nonvolatile memory during a boot phase of the network adapter chip, the read only memory providing the self boot code that generates said native processor machine language instructions from the corresponding new instructions stored in the nonvolatile memory that execute in a loop after the boot phase of the network adapter chip; and executing said generated native processor machine language instructions within said network adapter chip.