Patent ID: 8609473

Claim:
A method for fabricating a stackable integrated circuit layer comprising the steps of: providing a prepackaged integrated circuit package comprising an integrated circuit die, removing a predetermined portion of the package in a first operation to define a partially-depackaged integrated circuit die, affixing the partially-depackaged integrated circuit die and a spacer element having a predetermined thickness and a predetermined set of surface dimensions to a substrate whereby at least a portion of the spacer element is disposed between the partially-depackaged integrated circuit die and the substrate to define a convex, partially-depackaged integrated circuit die surface, removing a predetermined portion of the convex, partially-depackaged integrated circuit die surface in a second operation, defining a stud bump on a contact pad of the integrated circuit die, encapsulating the die in a potting material to define a potted assembly having an active surface and an inactive surface, removing a portion of the potting material from the active surface to a predetermined first depth whereby a predetermined portion of the stud bump is exposed on the active surface, and defining one or more electrically conductive traces on the active surface in electrical connection with the stud bump.