Patent ID: 7457168

Claim:
A non-volatile memory device comprising: a memory core comprising a plurality of sectors, each one of the plurality of sectors being accessed via a word line connected to a corresponding row decoder, and comprising a plurality of non-volatile memory cells, each one of the plurality of non-volatile memory cells being connected to the word line, a bit line selected from a plurality of bit lines, and a bulk terminal; wherein each row decoder comprises a storage device configured to store an erase verification result for a corresponding sector; an erase voltage supplying circuit comprising; a wordline voltage generator receiving an internal word line voltage from a high voltage generating circuit and an external word line voltage from a source external to the erase voltage supplying circuit and providing a word line voltage to each one of the row decoders, a bitline generator receiving an internal bit line voltage from a high voltage generating circuit and an external bit line voltage from a source external to the erase voltage supplying circuit and providing a bit line voltage to at least one of the plurality of bit lines, and a bulk voltage generator receiving an internal bulk voltage from a high voltage generating circuit and an external bulk voltage from a source external to the erase voltage supplying circuit and providing a bulk voltage to the bulk terminal, and a state control circuit configured to control operation of the memory core and erase voltage supplying circuit, such that an erase voltage is simultaneously supplied to the plurality of sectors during a pre-program operation and sequentially supplied to the plurality of sectors in accordance with the stored erase verification results during a post-program operation.