Patent ID: 6856009

Claim:
A stacked package comprising: a multi-chip package comprising: a carrier; a first integrated circuit die coupled to the carrier; a second integrated circuit die coupled to the carrier; an encapsulant disposed about each of the first integrated circuit die and the second integrated circuit die; and a plurality of conductive elements coupled between an outer surface of the encapsulant and each of the first integrated circuit die and the second integrated circuit die; and a first integrated circuit module comprising: an interposer having a first side and a second side and a plurality of conductive vias therethrough, and comprising a conductive trace layer electrically coupled to the conductive vias, wherein the first side of the interposer is coupled to the multi-chip package such that each of the plurality of conductive vias is aligned with a respective one of the plurality of conductive elements; a third integrated circuit die coupled to the second side of the interposer, wherein the third integrated circuit die is electrically coupled to the conductive trace layer; and a fourth integrated circuit die coupled to the second side of the interposer; wherein the fourth integrated circuit die is electrically coupled to the conductive trace layer.