Patent ID: 7335930

Claim:
A static random access memory (SRAM) cell; comprising: a first P-channel field effect transistor (PFET), a second PFET, a first N-channel field effect transistor (NFET), a second NFET, a third NFET and a fourth NFET, each PFET and NFET having a source and a drain; a first gate segment common to said first PFET and said first NFET, a second gate segment common to said second PFET and said second NFET, said first and second gate segments having top surfaces, sidewalls and ends; a first silicide layer contacting a first end of said ends of said first gate segment and a drain of said second PFET; a second silicide layer contacting a contact region of at least one of said sidewalls of said second gate segment and a drain of said first PFET; a third silicide layer contacting a contact region of at least one of said sidewalls of said first gate segment and a drain of said second NFET; a fourth silicide layer contacting a first end of said ends of said second gate segment, a drain of said first PFET and a drain of said fourth NFET; and a fifth silicide layer contacting a second end of said ends of said first gate segment and a drain of said third NFET.