Patent ID: 7895506

Claim:
An iterative decoder and early-exit condition detector comprising: a first codeword generator to generate a first codeword from decoded bits generated from a first sub-decoder after one or more half-iterations of the iterative decoder; a second codeword generator to generate a second codeword from decoded bits generated from a second sub-decoder after an additional half-iteration of the iterative decoder; and circuitry to buffer and compare the first and second codewords to determine whether the decoded bits generated from the second sub-decoder are valid; and a controller to set a codeword matching level to configure the iterative decoder to perform one of double or triple codeword matching based on an estimated signal-to-noise ratio (SNR), wherein when the first and second codewords match and when the codeword matching level is set to double codeword matching: the circuitry to buffer and compare indicates that the decoded bits comprise valid decoded bits; and the iterative decoder refrains from performing further iterations for current input bits, and wherein when the codeword matching level is set to triple codeword matching: the first codeword generator generates a third codeword from an output of the first sub-decoder after another additional half-iteration of the iterative decoder; the circuitry to buffer and compare compares the third codeword to both the first and second codewords; and the iterative decoder refrains from performing further iterations for the current input bits and indicates that the decoded bits comprise valid decoded bits when the third codeword matches both the first and second codewords.