Patent ID: 7190620

Claim:
A method for operating bits of memory cells in a memory array, the method comprising: applying operating pulses to at least one of Type-I bits and Type-II bits of a sample of memory cells, a Type-I bit being defined as a bit in a dual bit cell whose other bit is erased and a Type-II bit being defined as a bit in a dual bit cell whose other bit is programmed; determining a response of at least one of an electrical, physical and mechanical property of said at least one of Type-I bits and Type-II bits to said operating pulses; applying at least one operating pulse as a function of said response to at least some other Type-I bits of said array; applying at least one further operating pulse as a function of said response to at least some other Type-II bits of said array; wherein applying the at least one operating pulse as a function of said response comprises adjusting the at least one operating pulse with a first adjustment and with a second adjustment as a function of said response, and applying at least one further operating pulse to Type-I bits with the first adjustment and to Type-II bits with the second adjustment; and wherein the at least one further operating pulse is applied to the Type-I bits with the first adjustment and only afterwards to Type-II bits with the second adjustment.