Patent ID: 7006582

Claim:
A receiving circuit, comprising: (a) a demodulator which pulls in a phase of a burst signal and outputs a demodulated data obtained by demodulating the burst signal, wherein the burst signal has a preamble part for storing phase information or data therein, a synchronous pattern part for storing synchronous information therein, and a data part for storing the data therein; (b) a controller which performs counting based on the demodulated data to output a first timing signal and a second timing signal, said controller including a synchronous pattern detector which detects synchronous information of the demodulated data to output a detection signal, a counting unit which performs counting based on the detection signal to output a count therefrom, and a timing generator having a plurality of set values, which compares the count and the set values and generates the first and second timing signals based on the result of comparison; and (c) a storage unit which stores the demodulated data or outputs the stored demodulated data, based on the first and second timing signals, said storage unit storing the demodulated data when the first timing signal is inputted thereto and outputs the stored demodulated data when the second timing signal is inputted thereto.