Patent ID: 8189388

Claim:
A flash memory device comprising: a main cell array configured to have main memory cells for storing data; a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array; a page buffer circuit configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array; a repair circuit including fuse circuits having fuse memory cells each of which is programmed in response to address information; wherein the repair circuit is operated in response to a program state of the fuse memory cells and outputs a repair signal; each of the fuse circuits including a cell controller and a switch circuit; the cell controller being configured to output a program voltage which is applied to a gate of the fuse memory cells during a program operation of the fuse memory cells, a verify voltage which is applied to the gate of the fuse memory cells during a verification operation of the fuse memory cells, a control signal, and a verifying signal; the switch circuit being configured to transmit the verifying signal to the fuse memory cells in response to the control signal during the verification operation of the fuse memory cells; and a data input/output controller configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit.