Patent ID: 7600203

Claim:
A circuit design system comprising: a storage unit in which a netlist is stored; a fault-candidate extracting module configured to extract equivalent fault class G 1 to G I (I is an integer equal to or greater than 1) from said netlist and to generate a fault-candidate data indicating said equivalent fault class G i (i is an integer not less than 1 and not greater than I), wherein said equivalent fault class G i is a portion of a design target circuit in which a fault position can not be specified by an external measurement and includes a plurality of nodes N i1 to N iji (J i is a number of nodes included in said equivalent fault class G i ); a judgment module configured to select a target node out of said plurality of nodes N i1 to N iji included in said equivalent fault class G i indicated by said fault-candidate data, wherein at least one observation point used for failure analysis is inserted into said target node; and an observation-point inserting module configured to update said netlist by inserting said at least one observation point into said target node, wherein said judgment module decides said target node based on said number J i , a probability that a fault is included in said equivalent fault class G i is represented by P i , a parameter D i with respect to said equivalent fault class G i is given by the following equation: D i =J i ×P i , and a sum of said parameter D i with respect to all equivalent fault class is represented by M, said judgment module decides said target node such that said sum M is reduced due to said insertion of said observation point, a reduction rate of said sum M due to said insertion of said observation point takes a maximum value.