Patent ID: 6903441

Claim:
A semiconductor package with enhanced chip groundability, comprising: a substrate having a front surface and a back surface, wherein the front surface is formed with at least one ground plane, the back surface is formed with a plurality of ground-ball pads, and a plurality of conductive vias are formed through the substrate for electrically connecting the ground around plane to the ground-ball pads; at least one semiconductor chip having an active surface and an inactive surface, wherein the active surface is formed with a plurality of conductive traces and a plurality of ground pads electrically connected to the conductive traces, allowing the ground pads to be connected via the conductive traces to an electrically-conductive wall formed on a side surface of the chip, and wherein the inactive surface is adhered by means of an electrically-conductive adhesive to the front surface of the substrate, allowing the electrically-conductive adhesive to come in contact with both the electrically-conductive wall and the ground plane of the substrate to thereby electrically interconnect the electrically-conductive wall with the ground plane; an encapsulation body formed over the front surface for encapsulating the chip; and a plurality of solder balls implanted on the ground-ball pads over the back surface of the substrate and electrically connected to an external device, so as to allow the ground pads of the chip to be electrically connected to an external device successively via the conductive traces, electrically-conductive wall, electrically-conductive adhesive, ground plane, conductive vias, ground-ball pads, and the solder balls.