Patent ID: 7288958

Claim:
A slew rate calibrating circuit comprising: a signal processing unit to output an input signal in a manner in which restrictions are put on a change rate of a voltage of the input signal and to be able to adjust a slew rate as a maximum change rate of a voltage of the output signal; a variable signal delaying unit being connected to an input side of said signal processing unit and to be able to adjust a delay time of a signal to be input to said signal processing unit; a clock selecting unit to select either of a first clock or a second clock having a period extended by a predetermined unit time than that of the first clock and to supply the selected clock to said variable signal delaying unit; a first rectangular signal outputting unit to receive a signal to be output from said signal processing unit and to invert logic of the signal every time a high-low relationship between a voltage of said signal to be output from said signal processing unit and a first predetermined reference voltage is reversed and to output a first rectangular signal having a rectangular waveform; a delay time setting unit to compare, in a time section during which said clock selecting unit selects the first clock, a first time lag, one by one, between a rising edge or falling edge of a waveform of the first clock and a rising edge or falling edge of the first rectangular signal to be output from said first rectangular signal outputting unit in a manner to respond to a corresponding rising edge or falling edge of another first clock existing one period before the rising edge or falling edge of the waveform of the first clock and to set a specified delay time to said variable signal delaying unit, the specified delay time being capable of canceling out the first time lag; a second rectangular signal outputting unit to receive a signal to be output from said signal processing unit and to invert logic of the signal every time a high-low relationship between a voltage of the signal to be output from said signal processing unit and a second predetermined reference voltage being different from that of said first reference voltage is reversed and to output a second rectangular signal; and a slew rate setting unit to compare, in a time section during which said clock selecting unit selects the second clock, a second time lag, one by one, between a rising edge or falling edge of the second clock and a rising edge or falling edge of the second rectangular signal to be output from said second rectangular signal outputting unit in a manner to respond to a corresponding rising edge or falling edge of another second clock existing one period before rising edge or falling edge of the second clock and to set a specified slew rate to said signal processing unit, such that the second time lag disappears.