Patent ID: 8064260

Claim:
A flash memory device comprising: a first section including flash memory for storing data; and a second section including: i) at least first and second pumping circuits having outputs, the second section being a peripheral circuit section, the first pumping circuit being configured to increase voltage produced therefrom under control of at least a first oscillation signal, and the second pumping circuit being configured to increase voltage produced therefrom under control of at least a second oscillation signal, different from the first oscillation signal; ii) first and second regulator circuits; and iii) first and second oscillators for providing the first and second oscillation signals respectively, the first regulator circuit coupled to the first pumping circuit output, the first oscillator configured to receive an outputted voltage of the first regulator circuit, the second regulator circuit coupled to the second pumping circuit output, and the second oscillator configured to receive an outputted voltage of the second regulator circuit, and iv) wherein the first pumping circuit is configured to produce, at the first pumping circuit output, a first voltage required for carrying out a first type of memory operation, and the second pumping circuit being configured to produce, at the second pumping circuit output, a second voltage required for carrying out a second type of memory operation different than the first type of memory operation, and wherein the second pumping circuit pumps up from one transistor threshold voltage (Vtn) less than a voltage level of the first voltage.