Patent ID: 7071053

Claim:
A method of manufacturing a semiconductor device having a dielectric capacitor including a bottom electrode, a dielectric layer and a top electrode on an underlying substrate having a three-dimensional structure, comprising: providing a silicon substrate having a first insulation layer comprising SiO 2 thereon, and a second insulation layer comprising SiO 2 formed on said first insulation layer, said second insulation layer having a hole formed therein; forming a bottom electrode on side wall of said hole and a surface of said first insulation layer in a bottom of the hole; forming a third insulation layer on the top surface of said second insulation layer; forming a dielectric layer covering said bottom electrode and said third insulation layer, wherein the said third insulation layer is a MgO layer or a Al 2 O 3 layer; forming a top electrode on said dielectric layer; wherein the bottom electrode and the top electrode are formed by a metalorganic chemical vapor deposition process at 300° C. or higher and 500° C. or lower using a β-diketone ruthenium complex as the precursor, one of O 2 , H 2 , N 2 O, O 3 , CO and CO 2 is used as a reaction gas, and the volume ratio of the reaction gas to a carrier gas is 1% or more.