Patent ID: 7651939

Claim:
A process of forming an electronic device comprising: forming a first conductive region within a substrate corresponding to a first component; forming a second conductive region within the substrate and adjacent to the first conductive region, wherein the second conductive region corresponds to a second component; depositing a stressor layer including an insulating material over the first conductive region and the second conductive region; forming a first insulating layer over the stressor layer, wherein forming the first insulating layer includes forming a void within the first insulating layer and wherein, from a top view, the void lies between the first conductive region and the second conductive region; forming a first opening through a first portion of the first insulating layer and a second opening through a second portion of the first insulating layer, wherein: the first portion overlies the first conductive region; the second portion overlies the second conductive region; the void connects the first opening and the second opening; and the stressor layer lies between the first conductive region and a bottom of the first opening, and between the second conductive region and a bottom of the second opening; forming a second insulating layer over the stressor layer within the first opening, the second opening, or any combination thereof, wherein forming the second insulating layer includes substantially blocking the void.