Patent ID: 8859299

Claim:
A method for developing a STT-RAM stack in a combinatorial manner, the method comprising: providing a substrate, wherein the substrate comprises a plurality of site-isolated regions defined thereon; and wherein each site-isolated region comprises one or more test structures; depositing a first layer on each of the site-isolated regions, wherein the first layer is operable as a tunnel barrier layer; depositing a second layer above the first layer on each of the site-isolated regions, wherein the second layer is operable as a fixed magnetic layer; depositing a third layer above the second layer on each of the site-isolated regions, wherein the third layer is operable as an antiferromagnetic layer; wherein at least one process parameter for the depositing of at least one of the first layer, the second layer, or the third layer is varied in a combinatorial manner between each of the site-isolated regions; and wherein at least one of the first layer, the second layer, or the third layer is deposited using a high productivity combinatorial atomic layer deposition (ALD) technique or a high productivity combinatorial physical vapor deposition (PVD) technique.