Patent ID: 8766324

Claim:
An integrated circuit (IC) chip having a plurality of memory cell array blocks, the IC chip comprising: a first memory cell array block having a first set of power lines including at least one positive high supply voltage (Vdd) line and at least one complementary low supply voltage (Vss) line; a second memory cell array block having a second set of power lines including at least one Vdd line and at least one Vss line, the second memory cell array block being disposed adjacent to the first memory cell array block, wherein each power line of the second set of power lines have at least one horizontal section and at least one vertical section on a same power line; a cell partition area disposed between the first and the second memory cell array blocks; and at least one signal line formed on a same metal layer as the first set of power lines routed across the cell partition area, wherein the first set of power lines are physically separated from the second memory cell array block and the second set of power lines are physically separated from the first memory cell array block.