Patent ID: 6912150

Claim:
A semiconductor dynamic random access memory device comprising: a plurality of bit lines, including a first bit line and a second bit line; a sense amplifier, having a first input coupled to the first bit line and a second input coupled to the second bit line; a first digitally controlled reference current generator, selectively coupled to the first bit line, to generate a first reference current in response to a first reference current control word; a plurality of memory cells, including a first memory cell coupled to the first bit line and a second memory cell coupled to the second bit line, to store a first data state and a second data state, each memory cell includes: at least one transistor including a source region, a drain region, a body region disposed between and adjacent to the source region and the drain region, wherein the body region is electrically floating, and a gate spaced apart from, and capacitively coupled to, the body region; wherein the transistor includes a first state which is representative of a first charge in the body region and a second state which is representative of a second charge in the body region, and wherein the memory cell is in: (1) the first data state when the transistor is in the first state and (2) the second data state when the transistor is in the second state; and wherein the sense amplifier uses the first reference current to sense whether the second memory cell is in the first data state or the second data state.