Patent ID: 8369142

Claim:
A nonvolatile semiconductor memory device, comprising: a cell unit including a first and a second selection gate transistor and a memory string provided between said first and second selection gate transistors and including a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into said memory cell, wherein the number of program stages for at least one of memory cells on both ends of said memory string is lower than the number of program stages for other memory cells, said data write circuit executes the first stage program to said memory cell having the number of program stages lower than the number of program stages for said other memory cells after the first stage program to said other memory cells, the number of program stages for a first memory cell counted from said first selection gate transistor is N (N=an integer of 1 or more), and the number of program stages for other memory cells is M (M=an integer layer than N), said data write circuit executes the i 1 -th stage (i 1 =an integer of 1-N) program to said first memory cell after execution of the i 1 -th stage program to a second memory cell counted from said first selection gate transistor, and said data write circuit executes the i 2 -th stage (i 2 =an integer of 1-M) program to the k-th (k=an integer of 3 or more) memory cell counted from said first selection gate transistor after execution of the i 2 -th stage program to the (k−1)-the memory cell.