Patent ID: 8387071

Claim:
An apparatus, comprising: a finite state machine (FSM) of an integrated circuit (IC), the FSM having a plurality of states including a first state, a second state, and a replicated variant of the second state; a control logic of the IC, coupled with the FSM; an event generator of the IC coupled to the FSM; and a robust physically unclonable function (PUF) circuit of the IC, coupled with the control logic and the event generator, wherein the robust PUF circuit is configured to receive an input from the event generator and in response, provide an output to the FSM and the control logic to control, respectively, transition of the FSM from the first state to the second state or to the replicated variant of the second state in lieu of the second state, and transition of the FSM out of the replicated variant of the second state when the output to the FSM caused the FSM to transition from the first state to the replicated variant of the second state in lieu of the second state, and wherein the event generator is configured to generate the input for the robust PUF circuit based at least in part on a first signal from the FSM, representative of a current state of the FSM, and a signal from a source external to the IC.