Patent ID: 7467245

Claim:
A method for a bus arbiter to control access to a bus, comprising: determining by a first device a first priority level of first data to be transferred by the first device, wherein the first priority is based on a latency requirement of a first type of data corresponding to the first data; determining by a second device a second priority level of second data to be transferred by the second device, wherein the second priority level is based on a latency requirement of a second type of data corresponding to the second data; receiving a first bus access request from a first device requesting access to the bus for transferring the first data; receiving data representative of the first priority for the first data corresponding to the first bus access request separately from the first bus access request; asserting a first bus grant corresponding to the first bus access request to the first device until an entire packet transfer completion is imminent unless a bus access request is received with a higher priority level; receiving a second bus access request from the second device for transferring the second data;, receiving data representative of the second priority level for the second data separately from the first bus access request, the data representative of the priority of the first data, and the second bus access request, wherein the second priority level is a higher priority than the first priority level; immediately de-asserting the first bus grant associated with the first bus access request responsive to the second bus access request having a higher priority than the bus access request; and asserting a second bus grant associated with the second bus access request signal to the second device responsive to the second bus access request having a higher priority than the bus access request; wherein the first device is responsive to the de-asserting of the first bus grant to immediately relinquish the bus.