Patent ID: 8265134

Claim:
An apparatus comprising: an interleaved analog to digital converter (ADC) having M interleaved ADC channels, the interleaved ADC comprising: an input port for receiving an analog input signal; a programmable gain amplifier coupled to the input port; M ADC channels, each coupled to an output of the programmable gain amplifier, each ADC channel including a track-and-hold unit coupled to ADC conversion circuitry; retimer circuitry coupled to the ADC channels to combine digital output signals from the ADC channels into a digital output signal for the interleaved ADC; an output port coupled to the retimer circuitry; automatic gain control coupled between the retimer circuitry and the programmable gain amplifier, for adjusting a gain of the programmable gain amplifier; and a timing recovery circuit and analog phase interpolator, coupled to an output of the retimer circuitry for adjusting a phase of a clock input to the track-and-hold units; and a multi-channel equalizer coupled to an output of the interleaved ADC, the multi-channel equalizer capable of applying a different equalization to different interleaved ADC channels.