Patent ID: 8077068

Claim:
An N-bit asynchronous quantizer including: 2 N −1 signal amplifier stages (G 1 2 -G 2 N −1 2 ; I 1 , Cs, M 1 ) arranged in series, the input of the first stage being capable of receiving a signal to be quantized; 2 N −1 comparators (C 1 2 -C 2 N −1 2 ; I 2 , H), one comparator being connected to the output of each amplifier stage (G 1 2 -G 2 N −1 2 ; I 1 , Cs, M 1 ), and capable of comparing the value of this output with a predetermined threshold value; and at least 2 N −2 delay lines (D 1 2 -D 2 N −1 2 ) placed at the output of the 2 N −2 first comparators, the signals supplied at the output of the delay lines (D 1 2 -D 2 N −1 2 ) and of the last comparator constituting at any instant the quantized binary values of the input signal with a time shift, wherein the quantizer further comprises, at the start or at the end of the amplifier stage sequence, an additional amplifier stage, and an additional comparator connected to the output of the additional amplifier stage and capable of comparing the output thereof with the zero value in order to determine the sign of the signal to be quantized.