Patent ID: 7197093

Claim:
A digital signal processing apparatus for processing an input digital signal that has been segmented as blocks each having a predetermined data amount and highly efficiently encoded along with adjacent blocks in a predetermined format, comprising: decoding means for decoding the highly efficiently encoded digital signal along with adjacent blocks encoded in the predetermined format; modifying process means for modifying the decoded digital signal; delay compensating means for compensating a delay of the decoded signal decoded by said decoding means and modified by said modifying process means; and encoding means for highly efficiently encoding the modified and delay compensated digital signal along with adjacent blocks into the predetermined format, wherein the input digital signal that has been highly efficiently encoded is read from a record medium, and wherein a delay of the digital signal that has been highly efficiently encoded by said encoding means is compensated by said delay compensating means and then the delay compensated signal is written to the record medium so that the phase of the compensated digital signal matches the phase of the digital signal that has been read from the record medium.