Patent ID: 8227339

Claim:
A method comprising: depositing a plurality of dielectric layers on top of a semiconductor structure, said plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of said plurality of dielectric layers down into said plurality of dielectric layers by a non-selective etching process, wherein at least one of said multiple openings has a depth below said etch-step layer; and continuing etching said multiple openings by a selective etching process until one or more openings of said multiple openings that are above said etch-stop layer reach and expose said etch-stop layer, wherein said etch-stop layer is a first etch-stop layer; said plurality of dielectric layers are further separated by a second etch-stop layer that is separated from and underneath said first etch-stop layer; and said at least one of said multiple openings is a first opening; further comprising creating a second opening of said multiple openings that has a depth below said second etch-stop layer.