Patent ID: 7084055

Claim:
A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first insulating film over a semiconductor substrate; (b) forming a plurality of wirings on the first insulating film; (c) forming a second insulating film at a first temperature, so as to cover the wirings; (d) heat-treating the second insulating film at a second temperature; (e) etching the second insulating film so that a surface of a wiring, of the plurality of wirings, is exposed to form an aperture in the second insulating film; (f) forming a first conductive layer inside the aperture at a third temperature by means of chemical vapor deposition technique; (g) forming a second conductive layer on the first conductive layer; and (h) polishing the first and second conductive layers so that the first and second conductive layers remain selectively inside the aperture, wherein the second temperature is higher than the first temperature and the third temperature, and wherein in the step (d), a speed of increase in temperature from the first temperature to the second temperature is 60° C./second or less.