Patent ID: 7911027

Claim:
A semiconductor device comprising: a bypass capacitor including an MOS structure formed to be extended from a power wiring region of the semiconductor device to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and having a gate electrode formed through a capacitive insulating film on a diffusion region having a first conductivity type; and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein: the bypass capacitor has a contact to come in contact with a power wiring which is formed on a surface of the gate electrode and includes the diffusion region having the first conductivity type and a diffusion region of the substrate contact connected to each other, the bypass capacitor has an opening portion for forming a contact region, and the diffusion region is connected to have a different electric potential from that of the gate electrode through a diffusion contact to come in contact with the diffusion region through the opening portion.