Patent ID: 8738840

Claim:
A system, comprising: a memory that has stored thereon computer-executable components; a processor that executes the following computer-executable components stored in the memory: a kernel component that detects when pages are fetched from a permanent storage device, wherein the pages are stored on one or more FLASH memory devices employed for random access memory applications; a buffer component that temporarily holds a plurality of the pages while the pages are being stored on the FLASH memory device; an address match component that compares a plurality of incoming addresses and determines if a data return is directed to the page buffer or the FLASH memory device based on a Program and Erase cycle of the FLASH memory device; and an allocation component that allocates pages to at least one of the FLASH memory device or the page buffer based on a type of page fault, wherein in response to a read major page fault, the allocation component allocates a page in marked with copy on write protection from a main storage device to the FLASH memory device, and wherein in response to a write major page fault, the allocation component allocates a page in from the main storage device to the page buffer and allocates a buffer page for a write reference that hits on a FLASH page, and wherein in response to a minor page fault the allocation component is configured to determine whether an existing page is already in the page buffer, and in response to there being an existing page on an existing physical page buffer page, the virtual management component maps to the existing physical page buffer page, and in response to there not being an existing page on an existing physical page buffer page, a page is allocated on the buffer component and a FLASH page is demapped.