Patent ID: 8679921

Claim:
A method of forming a non-planar field effect transistor (FET), comprising: providing a substrate having a first surface; forming a cavity extending into the substrate a first distance to a bottom thereof, wherein the cavity is bounded by a first sidewall and a second sidewall, with each sidewall extending between the bottom and the first surface; forming first doped regions in the substrate proximate the first surface and laterally adjacent to each sidewall; forming a second doped region in the substrate proximate the bottom of the cavity and extending laterally within each sidewall; forming a gate insulator on each sidewall; forming a first gate conductor in contact with the gate insulator adjacent the first sidewall and overlying the second doped region; forming a second gate conductor in contact with the gate insulator adjacent the second sidewall and overlying the second doped region; forming a dielectric material between the first gate conductor and the second gate conductor; and forming first, second and third electrical connections, respectively, to the first doped region, the second doped region and the first gate conductor.