Patent ID: 7344930

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming first, second, and fourth islands-shaped polycrystalline silicon layers having relatively large grain sizes and a third islands-shaped polycrystalline silicon layer having relatively small grain sizes above an insulating substrate; (b) forming a first gate insulating film having a first thickness on the first islands-shaped polycrystalline silicon layer; (c) forming second, third, and fourth gate insulating films having second, third, and fourth thicknesses which are all not less than the first thickness on the second, third, and fourth islands-shaped polycrystalline silicon layers; (d) forming first to fourth gate electrodes on the first to fourth gate insulating films to define first to fourth channel regions; (e) adding an n-type impurity to a low concentration to the first to fourth islands-shaped polycrystalline silicon layers by using the gate electrodes as a mask; (f) patterning the first gate insulating film to the shape of the first gate electrodes and patterning the second and third gate insulating films so that the second and third gate insulating films project from the second and third gate electrodes; (g) masking a gate insulating film on the fourth islands-shaped polycrystalline silicon layer and the second islands-shaped polycrystalline silicon layer and adding an n-type impurity at a different acceleration voltage; and (h) masking the first, second, and third polycrystalline silicon layers and adding a p-type impurity to the fourth polycrystalline silicon layer at a different acceleration voltage.