Patent ID: 7851259

Claim:
A method of forming a semiconductor package, the method comprising: preparing a lower printed circuit board including a plurality of first interconnections and a plurality of ball lands on an upper surface of the lower printed circuit board and a plurality of first lower pads on a lower surface of the lower printed circuit board; mounting a semiconductor chip on the upper surface of the lower printed circuit board, such that the semiconductor chip is electrically connected to the lower printed circuit board in a flip-chip structure; forming a lower molded resin compound on the upper surface of the lower printed circuit board and the semiconductor chip, the lower molded resin compound having a plurality of via holes exposing the ball lands; preparing an upper printed circuit board including a plurality of solder balls formed on a lower surface of the upper printed circuit board and a plurality of second interconnections on an upper surface of the upper printed circuit board; aligning the solder balls into the via holes; and reflowing the solder balls to connect ball lands and the solder balls, wherein each of the via holes has a top portion adjacent to the upper printed circuit board and a bottom portion adjacent to the lower printed circuit board, and a size of the top portion of each respective via hole is larger than a size of the bottom portion of the respective via hole.