Patent ID: 6849873

Claim:
A thin film transistor array panel for a liquid crystal display, comprising: an insulating transparent substrate; a gate wire including a gate line and a gate electrode connected to the gate line and having a single-layered structure on the insulating transparent substrate; a redundant data line formed by the same layer as the gate wire on the insulating transparent substrate; a gate insulating layer covering the gate wire and the redundant data line, and having a first contact hole exposing the redundant contact hole; a semiconductor layer formed on the gate insulating layer on the gate electrode; a data wire including a data line intersecting the gate line and connected to the redundant data pad through the first contact hole, a source electrode formed on a portion of the semiconductor layer and connected to the data line, and a drain electrode formed on a portion of the semiconductor layer and opposite to the source electrode with respect to the gate electrode; a pixel electrode connected to the drain electrode and formed on the gate insulating layer in a pixel enclosed by the gate line and the data line; and a passivation layer covering the pixel electrode at least in part and the data wire, and having an opening exposing the pixel electrode.