Patent ID: 7118987

Claim:
A method of forming a stress relaxed shallow trench isolation (STI) structure to improve charge mobility of a MOSFET device comprising the steps of: providing a semiconductor substrate; forming a trench in the semiconductor substrate; forming a plurality of liner layers comprising an uppermost plurality of nitride liners selected from the group consisting of silicon nitride (SiN) and silicon oxynitride (SiON) to line the trench; then forming a plurality of trench filling oxide layers, said plurality of trench filing oxide layers is a spin-on glass (SOG) that comprises a precursor selected from the group consisting of organic and inorganic mixtures for forming cross-linked silicon oxide containing structures; wherein at least one stress relaxing thermal annealing step is carried out during and following formation of said plurality of trench filling oxide layers to form a trench filling substantially free of stress; and, removing excess trench filling oxide layers above the trench level.