Patent ID: 8809144

Claim:
A method of fabricating an on-chip capacitor having a variable capacitance, the method comprising: forming first and second ports in a dielectric layer that are configured to be powered with opposite polarities and that have a parallel arrangement; forming a first and second electrodes in the dielectric layer with a parallel arrangement in a space between the first and second ports and aligned transverse to the first and second ports, wherein the first electrode has an end separated from the first port by a first gap so that the first port and the end of the first electrode lack direct physical connection, and the second electrode has an end separated from the second port by a second gap so that the second port and the end of the second electrode lack direct physical connection; forming a first voltage-controlled unit configured to selectively open and close a first current path coupling the first electrode with the first port; and forming a second voltage-controlled unit configured to selectively open and close a second current path coupling with the second port; wherein the on-chip capacitor has a larger capacitance value when the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port than when the first and second electrodes are electrically isolated from the first and second ports.