Patent ID: 7609571

Claim:
A semiconductor memory device comprising: a memory cell array block comprising a plurality of first memory cells connected to a plurality of first bit lines and a plurality of second memory cells connected to a plurality of second bit lines; a first sensing block disposed on a first side of the memory cell array block, wherein, when enabled, the first sensing block performs a first sensing operation to amplify a voltage difference between a pair of the first bit lines and between a pair of second bit lines corresponding to the pair of the first bit lines; a second sensing block disposed on a second side of the memory cell array block, wherein, when enabled, the second sensing block performs a second sensing operation to amplify a voltage difference between a pair of the second bit lines and between a pair of second sense bit lines corresponding to the pair of second bit lines; and, a control unit receiving a sensing block selection address signal, wherein, when the sensing block selection address signal specifies the first sensing block, the control unit enables the first sensing block and disables the second sensing block.