Patent ID: 8165188

Claim:
A transceiver, comprising: a first digital to analog converter (DAC), for receiving a first digital signal to generate an analog signal; an operation circuit, coupled to the first DAC, for receiving the analog signal and a feedback signal to generate an operated analog signal; an analog to digital converter (ADC), for generating a second digital signal according to the operated analog signal; a digital signal processing circuit, for processing the second digital signal to generate a processed digital signal; a second DAC, for generating the feedback signal according to the processed digital signal; an adjustable delay circuit, for delaying a clock signal according to a control signal to adjust at least one sampling point of at least one of the first DAC, the second DAC and the ADC; a control circuit, for generating the control signal according to the processed digital signal; and an analog front end circuit, coupled between the ADC and the operating circuit, and comprising at least one delay circuit; wherein the control circuit is further coupled to the analog front end circuit for controlling a delay amount of the analog front end circuit according to the processed digital signal.