Patent ID: 7932541

Claim:
A hetero-junction bipolar transistor structure comprising: a single crystalline semiconductor substrate having a top surface; an emitter region within said single crystalline semiconductor substrate below said top surface, said emitter region comprising a first type dopant; a single crystalline semiconductor extrinsic base layer on said single crystalline semiconductor substrate, said single crystalline semiconductor extrinsic base layer comprising a second type dopant; a first trench extending through said single crystalline semiconductor extrinsic base layer to said single crystalline semiconductor substrate and having a first sidewall and a bottom surface; a single crystalline semiconductor intrinsic base layer above said single crystalline semiconductor extrinsic base layer and further lining said first trench such that, within said first trench, a first portion of said single crystalline semiconductor intrinsic base layer is adjacent to said first sidewall and a second portion of said single crystalline semiconductor intrinsic base layer is adjacent to said bottom surface; a dielectric layer on said single crystalline semiconductor intrinsic base layer; a second trench extending through said dielectric layer to said single crystalline semiconductor intrinsic base layer, said second trench having a second sidewall approximately aligned above said first sidewall; a sidewall spacer within said second trench positioned laterally adjacent to said second sidewall and within said first trench positioned laterally adjacent to said first portion of said single crystalline semiconductor intrinsic base layer; and a collector layer comprising said first type dopant and having a single crystalline semiconductor lower portion, a mid-portion and a polycrystalline semiconductor upper portion, said single crystalline semiconductor lower portion of said collector layer being within said first trench on said second portion of said single crystalline semiconductor intrinsic base layer and positioned laterally adjacent to said sidewall spacer, said mid-portion of said collector layer being within said second trench above said lower portion and positioned laterally adjacent to said sidewall spacer, and said polycrystalline semiconductor upper portion being above said mid-portion and extending horizontally onto said dielectric layer.