Patent ID: 7443890

Claim:
A multistage bit stream multiplexer having a switchable forward/reverse clock relationship comprising: a first multiplexing integrated circuit that receives a first plurality of bit streams at a first bit rate and that produces a second plurality of bit streams at a second bit rate, wherein the first plurality of bit streams are greater in number than the second plurality of bit streams are in number, and wherein the first bit rate is less than the second bit rate, the first multiplexing integrated circuit including: a phase locked loop (PLL) that receives a reference clock signal and produces a PLL Data Clock having a frequency equal to the second bit rate, and wherein a plurality of latches receive the PLL Data Clock, latch data multiplexed from the first plurality of bits streams, and produce the second plurality of bit streams; a second multiplexing integrated circuit that receives the second plurality of bit streams and that outputs at least one high-speed bit stream at a line bit rate that exceeds the second bit rate; and a clock circuit, wherein the clock circuit generates a forward transmit clock for use by the first multiplexing integrated circuit in producing the second plurality of bit streams based upon a reference clock signal that is selectable from a plurality of inputs based upon a clock selector input, wherein the plurality of inputs include a reverse transmit clock generated by the second multiplexing integrated circuit.