Patent ID: 8325240

Claim:
A data transfer device transferring a digital data signal in synchronization with a clock signal, comprising: a data transfer line serially transferring the data signal; a clock transfer line transferring the clock signal; a decision unit deciding an adjustment amount by which a phase of the clock signal accompanying the data signal is shifted, the adjustment amount being used when transferring the data signal in synchronization with the clock signal; and a phase adjusting unit shifting the phase of the clock signal in accordance with the adjustment amount decided by the decision unit while keeping a frequency of the clock signal fixed, wherein the decision unit repeatedly transfers a test signal in synchronization with the clock signal while shifting the phase of the clock signal and decides the adjustment amount based on the transferred test signal and the clock signal, the test signal being a digital data signal for test, and the test signal is a binary signal whose signal values alternately change in the same cycle as that of the clock signal.