Patent ID: 6909657

Claim:
A memory circuit, comprising: memory areas selected by a memory selection signal; and a control circuit connected to and refreshing said memory areas in accordance with a refresh request signal, said control circuit: in a first operating mode, carrying out the refreshing of one of said memory areas at a refresh address after receiving the refresh request signal and generating a refresh signal if an addressed memory area has been deselected or if, in an event of selection of said addressed memory area by the memory selection signal, access to said addressed memory area has ended before generation of a further refresh request signal; in a second operating mode, interrupting the access to said addressed memory area for writing and reading-out of data and carrying out the refreshing of said address memory area by generating the refresh signal if said addressed memory area has been selected and the further refresh request signal has been received before an ending of the access to said addressed memory area after receiving the refresh request signal.