Patent ID: 7286625

Claim:
A clock and data recovery circuit, comprising: (a) a multi-phase voltage-controlled oscillator (VCO) for accepting a control signal and for changing a frequency of a 10 GHz clock signal output from the voltage-controlled oscillator in response thereto, wherein the voltage-controlled oscillator outputs a plurality of phases of the 10 GHz clock signal; (b) a phase detector (PD) for sampling a 40 Gb/s input data signal using the 10 GHz clock signal received from the voltage-controlled oscillator and generating four 10 Gb/s output data signals in response thereto, wherein the 40 Gb/s input data signal is re-timed and de-multiplexed into the 10 Gb/s output data signals by the phase detector using half-quadrature phase offsets of the 10 GHz clock signal, such that each of the 10 Gb/s output data signals detects an edge or transition in the 40 Gb/s input data signal and whether the edge or transition is early or late with respect to its corresponding half-quadrature phase offset of the 10 GHz clock signal; (c) a voltage-to-current (V/I) converter for converting the 10 Gb/s output data signals from the phase detector to a control current; and (d) a loop filter (LPF) for integrating the control current from the Voltage-to-Current Converter and for outputting the control signal to the voltage-controlled oscillator in response thereto; (e) wherein the multi-phase voltage-controlled oscillator, phase detector, voltage-to-current converter and loop biter are implemented in complementary metal-oxide semiconductor (CMOS).