Patent ID: 7696008

Claim:
A wafer-level chip packaging process, comprising: providing a wafer having a plurality of chip units, wherein the wafer has an active surface and an opposite back surface, and a plurality of pads are disposed on the active surface; forming a plurality of through holes under the pads; filling the through holes with a conductive material such that the conductive material within each through hole is electrically connected to corresponding one of the pads and a portion of the conductive material is exposed and protrudes from the back surface of the wafer; after filling the through holes, forming a transparent adhesive layer covering the active surface and encapsulating the pads on the active surface; disposing a transparent cover panel on the transparent adhesive layer such that the transparent cover panel is attached to the wafer through the transparent adhesive layer; and performing a singulation process such that the chip units with a corresponding part of the transparent cover panel is separated form others to form a plurality of independent chip package structures.