Patent ID: 8140743

Claim:
A semiconductor memory device comprising: a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and said memory array section, said memory array section and said interface section being sealed in a package; wherein said interface section includes a plurality of interface modules configured to correspond to a plurality of memory types on a selectable one-to-one basis, a clock generation section configured to generate a plurality of clock signals based on a system clock signal supplied by said external memory controller, the generated clock signals being used by said plurality of interface modules, a mode interpretation section configured to interpret an input mode designation signal as indicative of one of said memory types in order to output a mode signal denoting the interpreted memory type, and one of said plurality of interface modules accesses said memory array section for either a write or a read operation in response to said mode signal output by said mode interpretation section.