Patent ID: 8872749

Claim:
A display device comprising: a plurality of pixels; a plurality of scanning lines; and a plurality of common lines; a scanning line drive circuit; and a common line drive circuit; wherein the scanning line drive circuit has a shift register circuit and a scanning voltage generation circuit for generating a scanning voltage; the shift register circuit has a plurality of shift pulse generation circuits for generating a first shift pulse and second shift pulse; the scanning voltage generation circuit has a plurality of base circuits; each one of the shift pulse generation circuits corresponds to n of the base circuits and provides shift pulse inputs to drive n gate lines, where n is an integral number of 2 or greater; the first shift pulse and the second shift pulse generated by the shift pulse generation circuit and corresponding to each of the plurality of base circuits are input into the each of the plurality of base circuits in the scanning voltage generation circuit; first through nth scanning line clocks are input into the plurality of base circuits, wherein a first scanning line clock is input to a respective first base circuit of the scanning voltage generation circuit and an nth scanning line clock is input to a respective nth base circuit of the scanning voltage generation circuit; each of the plurality of base circuits in the scanning voltage generation circuit respectively has: a first transistor including a first electrode to which the first shift pulse generated by the shift pulse generation circuit provided in the shift register circuit is input, a control electrode to which a fixed first power supply voltage is input and a second electrode, and a second transistor including a control electrode connected to the second electrode in the first transistor, a first electrode to which one of the first through nth scanning line clocks is input, and a second electrode connected to a scanning voltage output terminal; each of the plurality of base circuits outputs a selected scanning voltage synchronized with inputting one of the first through nth scanning line clocks from the scanning voltage output terminal when the first shift pulse that has been input is at a first voltage level, wherein the first through nth scanning line clocks are inputted having at least one of mutually different phases relative to each other and identical phases relative to each other in response to a selection of at least one of a gate line sequential drive method and a multiple gate line drive method of the plurality of pixels, and the common line drive circuit determines an AC drive method of the plurality of pixels, wherein the first through nth scanning line clocks have mutually different phases relative to each other in response to a selection of the gate line sequential drive method and the first through nth scanning line clocks have identical phases relative to each other in response to a selection of the multiple gate line drive method.