Patent ID: 7391656

Claim:
A memory read control apparatus in communications with a memory for transferring selected data read from said memory comprising: a data output latch control circuit receiving an external timing signal to provide a timing signal to data output latch within said memory for synchronization of the transferring of the selected data from said memory; a sense amplifier latch control circuit in communication with said data output latch control circuit to receive a sense amplifier latch clear signal which is combined with a data line sense amplifier enable signal to generate a sense amplifier latch control signal that is communicated to a sense amplifier latch of said memory to gate the selected data read from said memory; and a sense amplifier control circuit in communication with said sense amplifier latch control circuit to provide said data line sense amplifier enable signal to said sense amplifier latch control circuit and to receive said sense amplifier latch control signal from said sense amplifier latch control circuit and in communication with a data line sense amplifier within said memory to provide said data line sense amplifier enabling signal to said data line sense amplifier and to said sense amplifier latch control circuit and receive the sense amplifier latch signal from said sense amplifier latch control circuit to indicate that said data line sense amplifier of said memory is to be disabled.