Patent ID: 8482956

Claim:
A semiconductor memory device comprising: a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor; word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column; bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells arranged in the same row; a common line extending in the column or the row direction, and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells; a word line voltage applying circuit that applies a voltage to a word line connected to the memory cell selected as a writing target in the writing of the information stored in the memory element; a first voltage applying circuit that applies a write voltage to the bit line connected to the selected memory cell; and a second voltage applying circuit that previously applies an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to applying the write voltage, and that applies the precharge voltage to the common line connected to the selected memory cell while the write voltage is applied to the bit line connected to the selected memory cell.