Patent ID: 7665051

Claim:
A method for checking a layout of an electronic circuit of a semiconductor component, the method comprising: using a computer processing apparatus, reading in the layout and a corresponding cell list, the layout comprising a plurality of cells; using the computer processing apparatus, enlarging a boundary for each cell in the plurality of cells by an offset distance to form a halo region disposed between the boundary and the enlarged boundary; using the computer processing apparatus, determining an environment for each cell in the plurality of cells, wherein the environment includes all the interfaces from the cell to adjacent cells in the layout within the halo region around each cell; using the computer processing apparatus, automatically identifying classes of cells in the layout, wherein cells with a same environment are assigned to a same class; using the computer processing apparatus, storing the classes in a cell database; and using the computer processing apparatus, making a comparison in a pre-design rule check (preDRC) step between a layout to be checked and the cell database, where matches and mismatches are identified automatically.