Patent ID: 7392497

Claim:
A method of routing a metal interconnect layer in an integrated circuit, the method comprising: defining a single-width wire having a width corresponding to a design ground rule minimum-width; defining a wide wire having a width greater than the design ground rule minimum-width; generating a net list from a logical design file; performing a first interconnect routing of the metal interconnect layer based on an initial physical placement of a plurality of logic elements within the integrated circuit; replicating a first single-width wire such that multiple instances of the first single-width wire are routed in parallel and terminated in accordance with a source and a sink as defined in the net list; decomposing a first wide wire into a plurality of single-width wires such that a resistance through the plurality of single-width wires is substantially equal to a resistance through the first wide wire; and iteratively routing the metal interconnect layer until a plurality of predefined design specifications are satisfied.