Patent ID: 7479802

Claim:
An integrated circuit comprising: an integrated circuit programmable to operate on input data in accordance with one or more predetermined digital algorithms comprising: a first memory portion comprising at least one instruction defining a digital algorithm; a second memory portion comprising configuration data in conjunction with said digital algorithm; a third memory portion operable to selectively provide data inputs and to receive and store data outputs; a logic computation unit comprising a programmable array of a plurality of execution units, each of said execution units being programmable to provide Boolean functionality as determined by a corresponding first portion of said at least one instruction, each of said execution units being programmably interconnected with others of said execution units in accordance with at least a portion of said configuration data, and each of said execution units programmably operating on said data inputs from said third memory portion to provide said data outputs for storage in said third memory portion; and a circuit operable to provide execution clock cycles to said first, second and third memory portions such that said logic computation unit computes said digital algorithm, said execution clock cycles being selected such that the time to compute said digital algorithm is a predetermined time.