Patent ID: 7952415

Claim:
A level shift circuit, comprising: a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, wherein the level shifter includes a diode-connected transistor; an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power; a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, wherein the first buffer includes a second sourcing circuit and a second sinking circuit connected in series between the firstpower and the second power; a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit, wherein the second buffer includes a third sourcing circuit and a third sinking circuit connected in series between the first power and the second power; operation of the second sourcing circuit is controlled in response to a first level-shifted signal, wherein the sourcing operation of the second sourcing circuit is controlled in response to the first level-shifted signal, the first level-shifted signal being output from a source terminal of the diode-connected transistor, and operation of the third sinking circuit is controlled in response to a second level-shifted signal, wherein the sinking operation of the third sinking circuit is controlled in response to the second level-shifted signal, the second level-shifted signal being output from a drain terminal of the diode-connected transistor.