Patent ID: 7049668

Claim:
A semiconductor structure comprising: a substrate having a major surface; a plurality of low-resistance trenches formed in said substrate extending from said major surface, some of said low-resistance trenches being orientated in a first direction and others of said low-resistance trenches being orientated in a second direction, each of said low-resistance trenches being filled with conductive material which is electrically separated from said substrate by insulating material, said conductive material comprises polycrystalline silicon; a first insulating layer disposed on said major surface above said low-resistance trenches, said first insulating layer having a plurality of first contact openings above said low-resistance trenches along said first and second directions, said first insulating layer comprises silicon dioxide; a first conductive layer having crisscrossing segments disposed above said major surface of said substrate, some of said segments being orientated in said first direction and others of said segments being orientated in said second direction, each of said segments being disposed in substantial alignment and in contact with one of said low-resistance trenches through one of said first openings; a plurality of low-capacitance trenches disposed in said substrate, each of said low-capacitance trenches being disposed without said first conductive layer disposed thereabove and having a trench width substantially narrower than the corresponding trench width of each of said low-resistance trenches, said low-resistance trenches and said low-capacitance trenches being disposed interposing with each other in said substrates; a second insulating layer disclosed above said first conductive layer, said second insulating layer having a plurality of second contact openings, said second insulating layer comprises borophosphorous silicon glass; a second conductive layer disposed above said second insulating layer and in contact with said substrate through said second contact openings, said second conductive layer being substantially rectangular in shape disposed on said major surface of said substrate, wherein said rectangular shape of said second conductive layer having no elongated voids extended therein, thereby allowing bonding wires to be substantially unrestrictively attached onto said second conductive layer, said second conductive layer is plated with copper; and a source layer disposed in said substrate extending from said major surface, wherein said structure is a MOSFET structure having a source, a drain and a gate, said source includes said source layer, said drain includes said substrate, and said gate includes said low-resistance and low-capacitance trenches.