Patent ID: 7208356

Claim:
A method of manufacturing a multiple-gate metal oxide semiconductor (MOS) transistor, the method comprising: forming a single-crystal silicon pattern on an insulating layer the single-crystal silicon pattern providing source and drain regions, a channel region formed between the source and drain regions, and expansion regions interconnecting the source and drain regions, respectively, with the channel region; forming a silicon oxide layer and a nitride layer on the single-crystal silicon pattern; patterning the nitride layer to expose a top surface of the silicon oxide layer that exists in parts of the channel region and the expansion regions; forming an oxide layer taking a form of a field oxide layer having a beak in the channel region and the expansion regions by subjecting the exposed portion of the top surface of the silicon oxide layer to oxidation; using the patterned nitride layer as a mask removing the formed oxide layer of the channel region and the expansion regions to expose the single-crystal silicon pattern of the channel region and expansion regions; forming a gate insulating layer on an exposed single-crystal silicon pattern of the channel region; forming a gate electrode on the gate insulating layer; and implanting impurity ions into the single-crystal silicon pattern of the source and drain regions.