Patent ID: 7047371

Claim:
An integrated memory, comprising: a memory cell array containing a plurality of memory banks each with respective memory cells; at least a first and a second independently operated connection panel for external communication with the memory each connected to a respective command and address bus and to a respective data bus; a plurality of switches each assigned to a respective one of said memory banks for selectively connecting each one of said memory banks with a respective said data bus; a control circuit for external access to said memory banks, said control circuit being configured to: produce a number of first control signals, a respective one of said memory banks being assigned one of the first control signals and upon occurrence of an access to said memory bank assigned thereto, said first control signal indicating the access; and produce a first one and a second one of second control signals, the first one of the second control signals being assigned to the first connection panel and the second one of the second control signals being assigned to the second connection panel; produce the first one of the second control signals upon detecting an access collision to one of said memory banks such that when access to one of the memory banks via the second connection panel is already present, access to the same said memory bank is requested via the first connection panel; and produce the second one of the second control signals upon detecting an access collision to one of said memory banks such that when access to one of the memory banks via the first connection panel is already present, access to the same said memory bank is requested via the second connection panel; produce the first one of the second control signals upon an access collision occurring between a refresh mode on one of said memory banks and an access requested to the same memory banks via the first connection panel; and produce the second one of the second control signals upon an access collision occurring between a refresh mode on one of said memory banks and an access requested to the same memory banks via the second connection panel; external contacts, the first and second control signals being supplied to said external contacts for providing the first and second control signals externally of the integrated memory.