Patent ID: 7532072

Claim:
A differential amplifier comprising: an input stage, said input stage comprising: a first differential amplification stage biased by a first current source and adapted to generate a first pair of intermediate differential signals in response to a pair of differential input signals; and a second differential amplification stage biased by a second current source and adapted to generate a second pair of intermediate differential signals in response to the pair of differential input signals; a second stage adapted to generate a third pair of intermediate differential signals between first and second nodes responsive to the first and second pairs of intermediate differential signals; an output stage adapted to supply a pair of differential output signal responsive to the third pair of intermediate differential signals; and a feedback circuit adapted to supply a feedback signal to define a common mode voltage of the pair of differential output signals in accordance with an external value, wherein said second stage comprises: first and second transistors responsive to the first pair of intermediate differential signals; and third and fourth transistors responsive to the second pair of intermediate differential signals; said first and third transistors being coupled to the first node and adapted to pass a substantially same first current; said second and fourth transistors being coupled to the second node and adapted to pass a substantially same second current, each of said first and second transistors forms a cascode amplifier with a different one of the transistors disposed in the first differential amplification stage, and each of said third and fourth transistors forms a cascode amplifier with a different one of the transistors disposed in the second differential amplification stage, the differential amplifier further comprising a first resistive load disposed between a first supply voltage and the first transistor, and a second resistive load disposed between the first supply voltage and the second transistor.