Patent ID: 8391087

Claim:
A semiconductor device comprising: a memory cell array made up of a plurality of basic units, each of said plurality of basic units including a plurality of memory cells, data being able to be written and read to and from each of said plurality of memory cells; a first bus that is arranged in common for said plurality of basic units of said memory cell array and that transfers write data and read data; a second bus that is arranged in common for said plurality of basic units of said memory cell array and that transfers an address/command; a plurality of first buffer circuits, each of which is arranged in correspondence with each of said plurality of basic units of said memory cell array and receives an address/command transferred on said second bus to supply said address/command received to said each of said plurality of basic units, an address/command control unit that generates an address/command responsive to each of a write command and a read command to send the generated address/command to said second bus; and a data input/output control unit that sends write data to said first bus and receives read data from said first bus, each of said plurality of basic units of said memory cell array including: a first amplifier that receives write data to be written to a memory cell, transferred on said first bus and amplifies said write data; and a second amplifier that amplifies read data read from a memory cell and outputs said amplified read data to said first bus, wherein there are provided first to third time periods each constituting a unit period for pipeline control, said first time period including a control delay in which an address/command to be transferred to said second bus is generated by said address/command control unit in response to each of write and read commands, and in which write data to said first bus is prepared by said data input/output control unit in response to said write command, said second time period including a selection time in which in said basic unit of said memory cell array, writing to a selected memory cell for said write command or reading from a selected memory cell for said read command is performed, and said third time period including an output delay in which said data input/output control unit receives read data transferred on said first bus and outputs said read data to a data terminal, said read data being output to said first bus by said second amplifier in said selection time associated with said read command, said first time period having a length greater than or equal to said second time period.