Patent ID: 7280412

Claim:
A data bus inversion circuit for a semiconductor memory device, comprising: a data bus inversion block configured to selectively invert an input data signal comprising a plurality of serial bit signals based on a logic state of the plurality of serial bit signals, wherein the data bus inversion block comprises: a comparison deciding unit configured, in a first mode, to compare a first comparison signal that is generated based on a number of changed logic bits and a number of unchanged logic bits obtained by comparing respective bit signals of the input data signal and a previous input data signal, with inversion information of the previous input data signal, and to generate a first inversion control signal based on the comparison, the first inversion control signal indicative of whether the input data signal is to be inverted or not, and further configured, in a second mode, to generate a second inversion control signal based on a predominant logic state of the bit signals of the input data signal; and a data converting unit configured to invert, or not invert, the input data signal in response to the first inversion control signal and/or the second inversion control signal.