Patent ID: 8896773

Claim:
An array substrate for FPR 3D liquid crystal display, characterized in that comprises: a plurality of pixel units, some of the plurality of pixel units for forming left-eye signal being referred as left-eye pixel units, and another some of the plurality of pixel units for forming right-eye signal being referred as right-eye pixel units, the left-eye pixel units and the right-eye pixel units being alternately arranged, and each of the left-eye and right-eye pixel units comprising a main pixel area and a sub pixel area; circuit for affecting the left-eye and right-eye pixel units and being laid out at boundary areas of the left-eye pixel units and the right-eye pixel units, the circuit comprising: a charge gate, a share gate and a share capacitor, wherein the charge gate of one left-eye pixel unit and the share gate and share capacitor of the one left-eye pixel unit are laid out at two opposite sides of the one left-eye pixel unit, the charge gate, share gate and share capacitor of the one left-eye pixel unit are respectively adjacent to share gate and share capacitor of an adjacent right-eye pixel unit and charge gate of another adjacent right-eye pixel unit; and the array substrate further comprises first TFT, second TFT and third TFT; first TFT and second TFT for respectively controlling displaying and close of main pixel area and sub pixel area, third TFT being connected to share capacitor for controlling voltage difference existing between main pixel area and sub pixel area.