Patent ID: 8553193

Claim:
A pixel structure located on a substrate, comprising: a first scan line and a second scan line; a scan signal transmission line, electrically connected to the first scan line, wherein the scan signal transmission line is not parallel to the first scan line and the second scan line; a data line which is not parallel to the first scan line and the second scan line, wherein a portion of the data line, the first scan line, and the second scan line are formed by a same layer; a first insulating layer covering the portion of the data line, the first scan line, and the second scan line, the first insulating layer having a first recess located at respective sides of the portion of the data line; a second insulating layer covering the first insulating layer; a capacitor electrode line located on the second insulating layer and covering the data line, the capacitor electrode line further covering the first recess of the first insulating layer; a third insulating layer located on the capacitor electrode line; a first active device electrically connected to the second scan line and the data line; a first pixel electrode located on the third insulating layer and electrically connected to the first active device; a second active device electrically connected to the first scan line and the first active device; and a second pixel electrode located on the third insulating layer and electrically connected to the second active device.