Patent ID: 7697367

Claim:
A semiconductor memory device comprising: a plurality of memory blocks each including main word lines and sub-word lines; a main word decoder configured to set a selected main word line to a first potential and to set an unselected main word line to one of a second potential and a third potential; a cyclic signal generating circuit configured to generate a cyclic signal that indicates timing at predetermined intervals; a block selecting circuit configured to select a memory block to be accessed; a successive-selection circuit configured to successively select the memory blocks one after another; and a word decoder control circuit configured to control the main word decoder such that at least unselected one of the main word lines of a memory block selected by the block selecting circuit is set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after an access operation, and such that the main word lines of a memory block being selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal.