Patent ID: 7232719

Claim:
A method for manufacturing an integrated circuit which comprises a memory having a conductive charge storage node at least partially located in a first trench in a semiconductor substrate, the memory comprising a transistor which comprises a first source/drain region in the semiconductor substrate, the first source/drain region being electrically coupled to the charge storage node, the first source/drain region being present at a first side of the first trench but not at a second side of the first trench, or being connected by a conductive path to the first side of the first trench but not to the second side of the first trench, the memory comprising an isolation region present at the second side of the first trench, the method comprising: (a) forming the first trench in the semiconductor substrate; (b) forming first material in the first trench in the isolation region and adjacent to a location of the first source/drain region or the conductive path; (c) forming a mask over the isolation region; (d) removing a first portion of the first material adjacent to the location of the first source/drain region or the conductive path while the mask protects the first material in the isolation region; and (e) forming conductive material in a region from which the first portion of the first material was removed, the conductive material providing at least a portion of the charge storage node adjacent to the location of the first source/drain region or the conductive path; (f) etching the semiconductor substrate adjacent to a third side of the first trench to form a second trench; (g) after operation (e), removing a second portion of the first material from the isolation region; (h) forming first dielectric in the isolation region at a former location of the second portion of the first material, and forming second dielectric in the second trench; and (i) forming said transistor; wherein the first dielectric reaches deeper into the semiconductor substrate than a top of said at least a portion of the charge storage node adjacent to the location of the first source/drain region or the conductive path; wherein the second trench reaches deeper into the semiconductor substrate than the first dielectric; and wherein the first dielectric and the second dielectric are formed at the same time.