Patent ID: 8614922

Claim:
A semiconductor storage apparatus comprising: a first memory region; and a second memory region, wherein the first memory region includes: a first and a second memory plane, each memory plane including a plurality of memory cells arranged in a matrix; a first and a second block of pairs of sense-latch and write drivers to read and to write information in the first and the second memory planes; and a first memory region control circuit to respectively generate: a first write enable signal output to the first block of pairs of sense-latch and write driver, a second write enable signal output to the second block of pairs of sense-latch and write driver, and a first readout start signal output to the first and second blocks of pairs of sense-latch and write driver, according to an input internal address and a read/write control signal, wherein the second memory region includes: a third and a fourth memory plane, each memory plane including a plurality of memory cells arranged in a matrix; a third and a fourth block of pairs of sense-latch and write driver to read and to write information in the third and the fourth memory planes; and a second memory region control circuit to respectively generate: a third write enable signal output to the third block of pairs of sense-latch and write driver, a fourth write enable signal output to the fourth block of pairs of sense-latch and write driver, and a second readout start signal output to the third and fourth blocks of pairs of sense-latch and write driver, according to the input internal address, and the read/write control signal, and wherein the first readout start signal in the first memory region control circuit is activated, the third and fourth write enable signals in the second memory region control circuit are activated, and the third and fourth blocks of pairs of sense-latch and write driver perform first and second rewrite operations in the second memory region in a first period in which the first and second blocks of pairs of sense-latch and write driver are performing a first verify read in the first memory region.