Patent ID: 7616510

Claim:
A dynamic semiconductor storage device comprising: a first bit line; a second bit line arrayed in pairs with the first bit line; a word line intersecting the first and second bit lines; a memory cell connected to the first bit line and the word line; a reference word line intersecting the first and second bit lines; a reference memory cell connected to the second bit line and the reference word line; means for activating the word line; bit line precharging means for precharging the first and second bit lines to a ground voltage or a power voltage before the word line is activated; means for activating the reference word line when the word line is activated; reference voltage precharging means for precharging the reference memory cell to a reference voltage before the reference word line is activated; level shift means for shifting voltage levels of the first and second bit lines when the word line is activated; a first sharing line; a second sharing line arrayed in pairs with the first sharing line; a first isolator connected between the first and second bit lines and the first and second sharing lines; a sense amplifier of first conductivity type connected between the first and second sharing lines; and a first sense amplifier of second conductivity type; wherein the first sense amplifier of second conductivity type includes: a first field-effect transistor of a second conductivity type having a gate connected to the second bit and a drain connected to the first sharing line or the first bit line, and a second field-effect transistor of second conductivity type having a gate connected to the first bit line and a drain connected to the second sharing line or the second bit line.