Patent ID: 7456469

Claim:
A semiconductor device comprising: a semiconductor silicon substrate; device separation portions provided at predetermined positions on said semiconductor silicon substrate; a cell transistor having a recess channel structure being provided at a first region at said semiconductor silicon substrate defined by said device separation portions; a peripheral transistor having an nMOSFET structure being provided at a second region at said semiconductor silicon substrate defined by said device separation portions; and a peripheral transistor having an pMOSFET structure being provided at a third region at said semiconductor silicon substrate defined by said device separation portions, (A) said cell transistor having the recess channel structure comprising: (1) a recess provided at a predetermined position on said semiconductor silicon substrate; (2) a gate insulating film provided in contact with an inside of the recess; (3) a gate electrode having an N-type polysilicon layer provided in contact with the gate insulating film and a conducting layer provided in contact with the N-type polysilicon layer; and (4) a pair of source/drain regions including N-type diffusion layers provided at both sides of the gate electrode on a surface region of said semiconductor silicon substrate, (B) said peripheral transistor having the nMOSFET structure provided at the second region, having: (5) a gate insulating film provided at a predetermined position on said semiconductor silicon substrate; (6) a gate electrode having an N-type polysilicon layer provided in contact with the gate insulating film and a conducting layer provided in contact with the N-type polysilicon layer; and (7) a pair of source/drain regions including N-type diffusion layers provided at both sides of the gate electrode on a surface region of said semiconductor silicon substrate, (C) said peripheral transistor having the pMOSFET structure provided at the third region, having: (8) a gate insulating film provided at a predetermined position on said semiconductor silicon substrate; (9) a gate electrode having a P-type polysilicon layer provided in contact with the gate insulating film and a conducting layer provided in contact with the P-type polysilicon layer; and (10) a pair of source/drain regions including P-type diffusion layers provided at both sides of the gate electrode on a surface region of said semiconductor silicon substrate, the N-type polysilicon layer in said cell transistor containing an N-type impurity at an approximately constant concentration.