Patent ID: 8006041

Claim:
A prefetch processing apparatus for performing prefetch processing for preloading data from a main memory to a cache memory, the data being used when a central processing unit executes a program, the prefetch processing apparatus comprising: a central-processing-unit monitor unit that monitors, during the execution of the program, processing states of the central processing unit at a plurality of predefined time periods, each of the time periods being measured relative to time elapsed from start time of executing the program; a cache-miss-data address obtaining unit that obtains, during the execution of the program, cache-miss-data addresses within the predefined time periods, the cache-miss-data addresses being addresses of data resulting from accessing the main memory due to a cache miss; a cycle determining unit that determines a cycle of time required for executing the program between at least two select predefined time periods, based on the central-processing -unit processing states monitored by the central-processing-unit monitor unit; and an identifying unit that identifies a prefetch position in a cycle in which a prefetch-target address is to be prefetched by associating the cycle determined by the cycle determining unit with the cache-miss-data addresses obtained by the cache-miss-data address obtaining unit, the prefetch-target address being an address of data on which prefetch processing is to be performed.