Patent ID: 8134182

Claim:
A junction pseudomorphic high-electron-mobility transistor comprising: a semi-insulating substrate; a doping layer located on the substrate; a n-type barrier layer over said doping layer; a source electrode, a drain electrode, and a gate electrode on said barrier layer, the electrodes being provided at approximately the same distance from the semi-insulating substrate; a buried gate region under the gate electrode and in which an impurity is doped, the buried gate region being formed in the barrier layer; and a slit in the barrier layer, the slit located between the buried gate region and the drain electrode and filled with an insulating material, wherein, the slit extends from the surface of the barrier layer towards the doping layer to a depth of between 30% to 70% of the thickness of the barrier layer, the depth of the slit extending at approximately the same amount or more than a depth of the buried gate region, and a width of the buried gate region relative to a direction between the source and drain electrodes is less than a width of the gate electrode.