Patent ID: 7036017

Claim:
A microprocessor configuration, comprising: a central processing unit; at least one peripheral unit; a bus connecting said central processing unit to said peripheral unit; a first cryptographic unit configured in said peripheral unit, said first cryptographic unit being connected to said bus; a second cryptographic unit configured in said central processing unit, said second cryptographic unit being connected to said bus; a connection for supplying a regular clock signal clock-synchronously controlling said first cryptographic unit and said second cryptographic unit; a random number generator for producing a succession of random values, said random number generator being coupled to said first cryptographic unit for supplying the random values thereto, said random number generator being coupled to said second cryptographic unit for supplying the random values thereto; the random values being supplied to said first cryptographic unit and to said second cryptographic unit clock-synchronously under the control of said clock signal; said first cryptographic unit performing a cryptographic operation being controlled based on the random values produced by said random number generator; said second cryptographic unit performing a cryptographic operation being controlled based on the random values produced by said random number generator; and said peripheral unit and said central processing unit both functioning as transmitting units and receiving units, and data is transmitted via said bus in an encoded manner by a respective transmitting unit and the data is decoded by a respective receiving unit.