Patent ID: 8563370

Claim:
A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls, wherein the transistor is fabricated over a SOI substrate, comprising the following steps: 1) performing an isolation process; 2) depositing a SiO 2 layer and a SiN layer; 3) performing a photolithography process to define a channel region and a large source/drain region; 4) performing an etching process to transfer a pattern of a photoresist to SiN and SiO 2 hard masks; 5) depositing a layer of material A having a high etching selection ratio with respect to Si; 6) performing a photolithography process to define a Fin bar; 7) performing an etching process to transfer the pattern of the photoresist to the layer of material A, so as to form a hard mask for the Fin bar and the large source/drain region; 8) performing an etching process on the Si layer using the layer of material A and the SiN layer as the hard mask, so as to form the Fin bar of Si and the large source/drain region; 9) depositing a SiN layer; 10) etching the SiN layer to form SiN sidewalls; 11) performing an oxidization process to form a nanowire; 12) removing an oxide layer by using a wet etch process, so as to form a suspended nanowire; 13) forming a gate oxide layer; 14) depositing a polysilicon layer; 15) performing a photolithography process to define a gate line; 16) performing an etching process to transfer the pattern of the photoresist to the polysilicon layer; 17) performing an implantation process on the polysilicon layer and the source/drain region; 18) performing a wet etch process on the SiN layer; 19) depositing a SiO 2 layer to form an air sidewall; 20) performing an annealing process to activate impurities; 21) performing subsequent processes by using conventional processes, so as to complete the fabrication.