Patent ID: 7557610

Claim:
An integrated circuit disposed on a semiconductor die, wherein the integrated circuit comprises a plurality of columns extending from a first column on a first side of the semiconductor die to a second column on a second side of the semiconductor die opposite the first side, each of the columns is substantially completely occupied by a plurality of tiles, wherein substantially all of the tiles of each of the columns have an identical width, wherein a width of one of the columns differs from a width of another of the columns, and wherein there are input/output interconnect tiles in a third column enabling connections between columns, and input/output block tiles disposed in at least two of the columns, the input/output block tiles enabling internal connections to circuits in an adjacent column by way of the third column of input/output interconnect tiles and enabling external connections to first associated bond bumps of the semiconductor die, and the input/output block tiles in at least one of the columns of input/output block tiles being in a column other than the first column or the second column and an input/output block tile of the at least one column being disposed in a central location to receive a clock signal by way of a bond bump of the input/output block tile, wherein the first column on the first side of the semiconductor die comprises a plurality of multi-gigabit transceivers enabling external connections to second associated bond bumps of the semiconductor die, the plurality of multi-gigabit transceivers being coupled to a fourth column of input/output interconnect tiles.