Patent ID: 7673201

Claim:
A method of restoring a selected operational state of a circuit design implemented within a programmable integrated circuit (IC), the method comprising: pipelining a clock gating signal that selectively pauses a clock of the circuit design; storing configuration data specifying an operational state of the circuit design at a first simulation clock cycle in non-configuration memory; at a second simulation clock cycle, gating the clock of the circuit design; loading the stored configuration data into configuration memory of the programmable IC that controls configuration of the circuit design, wherein loading the configuration data reconfigures the circuit design and restores the operational state of the circuit design in existence at the first simulation clock cycle; and advancing the clock of the circuit design a number of clock cycles corresponding to a difference between the second simulation clock cycle and the first simulation clock cycle, wherein a state of the circuit design in existence at the second simulation clock cycle is implemented within the circuit design.