Patent ID: 8203861

Claim:
In a field programmable gate array (FPGA) or programmable logic device (PLD) coupled to a programmable non-volatile configuration storage bit circuit the improvement comprising: a first floating gate associated with a first non-volatile device; a second floating gate associated with a second non-volatile device; a first drain region associated with said first non-volatile memory device; and a second drain region associated with said second non-volatile memory device; and wherein the first drain region and the second drain region overlap respective sufficient portions of said first floating gate and said second floating gate respectively such that a programming voltage applied to said drain regions can be imparted to said floating gates through capacitive coupling; an output coupled to said first non-volatile device and said second non-volatile device; wherein a value of said output of said programmable non-volatile circuit is based on a programmed state of said first non-volatile device and said second non-volatile memory device and can be used to configure a function to be performed by the FPGA or PLD; and wherein said first non-volatile device is a pull-up device coupled to a first voltage source, and said second non-volatile device is a pull-down device coupled to a second voltage source which has less potential than said first voltage source.