Patent ID: 6854042

Claim:
A high speed data rate converting and switching circuit for use in computer memory systems comprising n memory banks, and further comprising a first external clock having a first frequency and a second external clock having a second frequency equal to n times the first frequency, the circuit comprising: (a)a data MUX and latch subsystem which transfers each of a multiplicity of system bus data signals having the second frequency to a memory bank data signal having the first frequency during a write operation, and which transfers each of a multiplicity of memory bank data signals having the first frequency to a system data bus data signal having the second frequency during a read operation; (b)A strobe MUX and latch subsystem which generates a memory bank strobe signal having the first frequency, and which is synchronized to the memory bank data signals with a 90 degree phase shift during the write operation, and which generates a system bus strobe signal having the second frequency which is synchronized to, and in phase with, the system bus data signals during the read operation; (c)a mask MUX and latch subsystem which generates a memory bank mask signal having the first frequency, and is synchronized to the memory bank data signals during the write operation.