Patent ID: 8189376

Claim:
A method of manufacture of an integrated circuit device including (i) a memory section including a plurality of memory cells, wherein each memory cell thereof includes at least one n-channel transistor having a gate, gate dielectric and first, second and body regions, and (ii) a logic section including a plurality of n-channel transistors having a gate, gate dielectric and first, second and body regions, the method comprising: depositing a gate dielectric material on or above a semiconductor substrate; depositing a gate semiconductor material on or over the gate dielectric material; implanting or introducing one or more acceptor-type doping species into at least portions of the gate semiconductor material within the memory section; forming the gates of the n-channel transistors of the plurality of memory cells of the memory section from at least the gate semiconductor material having one or more acceptor-type doping species implanted or introduced therein, wherein the gates of the n-channel transistors of the plurality of memory cells include work functions based at least partially on a work function of one or more materials comprising the gates of the n-channel transistors of the plurality of memory cells of the memory section; forming the gates of the n-channel transistors of the logic section from at least the gate semiconductor material within the logic section; and introducing one or more donor-type doping species into at least portions of the gate semiconductor material in the logic section, wherein the gates of the n-channel transistors of the logic section include work functions based at least partially on a work function of one or more materials comprising the gates of the n-channel transistors of the logic section, and wherein the work functions of the gates of the n-channel transistors of the plurality of memory cells of the memory section are greater than the work functions of the gates of the plurality of n-channel transistors of the logic section such that a threshold voltage of the n-channel transistors of the plurality of memory cells of the memory section is less than a threshold voltage of the plurality of n-channel transistors of the logic section resulting in a reduction in applied voltages and power consumption for operations on the n-channel transistors of the plurality of memory cells of the memory section as compared to the plurality of n-channel transistors of the logic section.