Patent ID: 7958465

Claim:
A method of forming an integrated circuit structure on a chip, the method comprising: extracting an active layer from a design of the integrated circuit structure, wherein the active layer comprises an active pattern, and wherein the active pattern comprises a diffusion region having a first length and a first width; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; adding by using a computer stress-blocking dummy diffusion regions throughout the chip comprising: adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region, wherein the first stress-blocking dummy diffusion region has a second length no less than about the first length of the active pattern; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region, wherein the second stress-blocking dummy diffusion region has a third length no less than about the first width of the active pattern; and after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.