Patent ID: 8003480

Claim:
A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM, comprising: forming a stacked structure on a semiconductor substrate, wherein the semiconductor substrate has a plurality of conductor plugs, the stacked structure includes an upper oxide layer, a lower oxide layer, a dielectric layer, and a nitride layer, the dielectric layer and the nitride layer are between the upper oxide layer and the lower oxide layer, the nitride layer is on the dielectric layer; forming a photoresist layer on the upper oxide layer, partially etching the photoresist layer and the upper oxide layer; depositing a polysilicon layer on the upper oxide layer and the nitride layer; depositing a nitrogen oxide layer on the polysilicon layer and the upper oxide layer; partially etching the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias; oxidizing the polysilicon layer converting the polysilicon layer to silicon dioxide surrounding the vias; etching the nitride layer, the dielectric layer and the lower oxide layer beneath the vias; forming a metal plate and a capacitor lower electrode in each of the vias; and etching the nitrogen oxide layer, the polysilicon layer, certain portions of the nitride layer and the dielectric layer under the nitride layer in turn, wherein each of capacitor lower electrodes is surrounded and adhered with the silicon dioxide and the nitride layer to increase the supporting force, reduce the difficulty of disposing a capacitor dielectric layer and a capacitor upper electrode onto the capacitor lower electrode, and prevent toppling of the capacitor lower electrode.