Patent ID: 6918050

Claim:
A clock generating circuit comprising: (1) a delay adjustment circuit comprising: a) a first gate array that has each gate serially connected for carrying out fine adjustment of a delay time interval of an input signal; b) a capacitance connected to an output side of a specified gate in the first gate array via a first switching device; c) a second gate array that is connected to an output side of said first gate array via a second switching device and carries out rough adjustment of the delay time interval of said input signal; and d) a control device that controls said first switching device and said second switching device so as to adjust the delay time interval of said input signal by adjusting the capacitance connected to the output side of the specified gate in the first gate array and the number of gate stages in the second gate array; (2) a duty ratio detecting device that detects a duty ratio of a clock output of the clock generating circuit; and (3) a control device that automatically updates on output value set in a register in said delay adjustment circuit so as to become a pre-set duty ratio based on a detected output of said duty ratio detecting device.