Patent ID: 8539120

Claim:
A pixel processor comprising: a pixel processing engine configured to perform pixel-level operations on reference pixels to generate reconstructed video frames, wherein the pixel-level operations include transform, interpolation, compensation, deblocking and filtering; a controller that includes a hybrid buffer operation (HBO) module that is configured to operate in both a first-in-first-out (FIFO) manner and a random access manner, and wherein the HBO module is configured to read messages from a video processor HBO module in a FIFO manner to generate commands from the messages, and an F-Block configured to access the commands from the HBO module in a random access manner and to execute the commands; a read agent circuit configured to read input video data via a direct memory access (DMA) circuit; a write agent circuit configured to write output data via the DMA circuit; a data receiver configured to read reference blocks from a video cache; a register file configured to provide operands for the pixel processing engine; an instruction memory that is interfaced to the controller and that is preloaded with opcodes to direct the pixel processing engine on how to perform tasks; an opcode lookup circuit configured to look up the opcodes that control a current operation of the pixel processing engine; and a data memory configured for use by the pixel processing engine.