Patent ID: 7400534

Claim:
A semiconductor integrated circuit device comprising: even-numbered bit lines; odd-numbered bit lines; cell source lines; first memory elements electrically connected between the even-numbered bit lines and the cell source lines; and second memory elements electrically connected between the odd-numbered bit lines and the cell source lines and belonging to the same rows as the first memory elements; wherein a potential corresponding to data to be programmed is applied to the first memory element via the even-numbered bit line and a potential which suppresses programming is applied to the second memory element via the cell source line while the odd-numbered bit lines are kept in an electrically floating state when data is programmed into the first memory element, and a potential corresponding to data to be programmed is applied to the second memory element via the odd-numbered bit line and a potential which suppresses programming is applied to the first memory element via the cell source line while the even-numbered bit lines are kept in an electrically floating state when data is programmed into the second memory element.