Patent ID: 8542744

Claim:
An apparatus for scalable block pixel filtering comprising: a first processing element (PE) of a plurality of PEs separate from a controller configured to dispatch instructions to the plurality of PEs; a first PE local memory unit of a plurality of PE local memory units, the first PE local memory unit directly coupled by a first memory interface to the first PE for load and store operations with the first PE, wherein the first PE local memory unit stores pixel data from a first macroblock; and a first hardware assist unit (HAU) of a plurality of HAUs, the first HAU directly coupled by a first PE interface to the first PE for command and data transfers and directly coupled by a second memory interface to the first PE local memory unit for separate load and store operations with the first HAU and the first HAU having state machine functions configured to perform deblocking filtering on the first macroblock loaded from the first PE local memory unit in parallel with operations in the first PE, wherein the first HAU utilizes a boundary strength (Bs) value for a block boundary between two neighboring pixel blocks to select a computation data path to perform edge filtering.