Patent ID: 7733984

Claim:
A polyphase filter network used with a phase rotator circuit comprising: said polyphase filter network creating a quadrature phase version of an input signal, said polyphase filter network being partitioned into a first part and a second part; said first part of said polyphase filter network being coupled to inputs of a first buffer stage of the phase rotator circuit; said first buffer stage including an equalizing buffer stage increasing amplitude of each respective input signal at a predefined frequency relative to DC; said second part of said polyphase filter network being coupled to outputs of said first equalizing buffer stage and being embedded in the phase rotator circuit; said second part of said polyphase filter network having a selected frequency response and being coupled to a pair of phase rotator multipliers of the phase rotator circuit by a second buffer stage; said second buffer stage including a lowpass buffer stage having a predefined lowpass frequency response and providing in-phase clock signals and quadrature clock signals to said pair of phase rotator multipliers; and said pair of phase rotator multipliers of the phase rotator circuit receiving mixing weights controlled by a plurality of binary control signals applied by a pair of digital-to-analog converters (DACs).