Patent ID: 7977247

Claim:
A method of forming a semiconductor structure comprising: forming at least one opening in a semiconductor substrate, said at least one opening defining a channel region for a semiconductor device; forming a block copolymer within said at least one opening and extending on an upper surface of said semiconductor substrate that is adjacent said at least one opening, said block copolymer having the formula A-B or A-B-A, where block A comprises a polymer of a mono alkenyl arene and block B is a polymer of acrylic acid, methacrylic acid or an ester thereof, selectively removing block B from within the at least one opening, leaving block A as a patterned mask; etching exposed portions of the semiconductor substrate within the at least one opening to provide an array of more than one electrically isolated channel within the channel region and having a space there between, said space between each neighboring channel is located within a distance that is less than or equal to twice the width of each channel of said array; forming a gate dielectric layer on sidewall surfaces and an upper surface of each of said electrically isolated channels; forming a gate conductor layer on said gate dielectric layer and on exposed surfaces of the semiconductor substrate not including said array of more than one electrically isolated channel; and forming a source diffusion region laterally abutting one end of each of said array of more than one electrical isolated channel and forming a drain diffusion region laterally abutting another end of each of said array of more than one electrical isolated channel.