Patent ID: 6977443

Claim:
A semiconductor device, comprising: a substrate, comprising: plural conductor patterns arranged around a chip-carrying region on a principal surface of said substrate, each of said plural conductor patterns having a nearly rectangular land, said land having a constricted portion that is formed in the central area of the land with a width smaller than that of the remaining portions of said land, said remaining portions of said land comprising a capillary tool contact portion and a wire contact portion arranged on opposing side of said constricted portion; adjacent lands of said plural conductor patterns are arranged substantially in parallel such that said capillary tool contact portion of one land is adjacent to said constricted portion of an adjacent land; a semiconductor chip that has plural electrode pads on its principal surface and is mounted on the semiconductor chip-carrying region of said substrate, plural conductor wires that connect said electrode pads and the lands on said substrate; and a sealant that seals said conductor wires and said semiconductor chip.