Patent ID: 8664728

Claim:
A transistor comprising: a p-type substrate having a p-type body; an n-well formed in the substrate; a source formed in the n-well including a p-doped p-body, a p-doped p+ region within the p-body, and a first n-doped n+ region within the p-body; a drain formed in the n-well and spaced apart from the source, the drain including a second n-doped n+ region; a channel region for current flow from the drain to the source, the channel region having an intrinsic breakdown voltage; a gate to control channel formation in the channel region between the source and the drain; and a breakdown region in the n-well between the p-body and the p-type body of the substrate outside the channel region, wherein doping and dimensions of the breakdown region and channel region are such that an extrinsic breakdown voltage of the breakdown region is lower than the intrinsic breakdown voltage.