Patent ID: 7956450

Claim:
A multi-chip package comprising: a substrate including: electrode terminals on an upper surface of the substrate, and ball lands on a lower surface of the substrate; a lower semiconductor chip placed face-down on the substrate, the lower semiconductor chip including: first bonding pads on a front surface, and first connectors electrically and mechanically connecting together the first bonding pads of the lower semiconductor chip to the electrode terminals of the substrate; and metal patterns on a back surface of the lower semiconductor chip; an upper semiconductor chip placed face-down type on the back surface of the lower semiconductor chip, the upper semiconductor including: second bonding pads on a frontal surface of the upper semiconductor, and second connectors electrically and mechanically connecting the second bonding pads of the upper semiconductor chip and the metal patterns; metal wires electrically connecting together the metal patterns of the lower semiconductor chip and the electrode terminals of the substrate; an encapsulant sealing the upper surface of the substrate, the lower semiconductor chip, the upper semiconductor chip and the metal wires; and mounting units on the ball lands which are on the lower surface of the substrate wherein the first and second bonding pads each comprise an adhesive layer, a diffusion barrier layer and a wetting layer.