Patent ID: 7394678

Claim:
An access method applied in a ferroelectric memory comprising: providing the ferroelectric memory comprising a memory unit, a first current source, and a second current source, wherein the memory unit comprising: a positive bit line and a negative bit line which are parallel to each other, the first current source and the second current source coupled to the positive bit line and the negative bit line respectively; a word line which is virtually perpendicular to the positive and the negative bit lines; a positive memory cell coupled to the word line and the positive bit line, and configured to be connected to the positive bit line when the word line is enabled; a negative memory cell coupled to the word line and the negative bit line, and configured to be connected to the negative bit line when the word line is enabled; a plate line coupled to the positive and the negative memory cells; and a sense amplifier having a latch coupled to the positive bit line and the negative bit line, wherein the sense amplifier further including a first transistor for coupling the latch to ground and a second transistor for coupling the latch to a supply voltage; enabling the word line; enabling the plate line to generate a voltage difference between the positive bit line and the negative bit line after the word line is enabled; activating the first current source and the second current source to enlarge the voltage difference after the plate line is enabled; enabling the sense amplifier to further enlarge the voltage difference by raising the higher voltage among the voltage in the positive bit line and the voltage in the negative bit line to high level and reducing the lower voltage to low level after the first current source and the second current source are activated, wherein the sense amplifier is enabled by first activating the first transistor in the sense amplifier via a first enable controlling signal (SAN) and thereafter activating the second transistor in the sense amplifier via a second enable controlling signal (SAP); and sensing the voltage difference between the positive bit line and the negative bit line and outputting the content stored at the ferroelectric memory accordingly after the sense amplifier is enabled.