Patent ID: 8017459

Claim:
A method of fabricating a thin film transistor (TFT) array substrate, the method comprising: forming a gate interconnection line on an insulating substrate, the gate interconnection line comprising a gate line and a gate electrode; forming a gate insulating layer on the gate interconnection line; forming a semiconductor layer and a data interconnection line on the semiconductor layer, the data interconnection line comprising a data line, a source electrode, and a drain electrode; sequentially forming a first passivation layer, a second passivation layer and a third passivation layer; etching the third passivation layer, the second passivation layer and the first passivation layer, and exposing a drain electrode of a drain electrode-pixel electrode contact portion; and forming a pixel electrode connected to the drain electrode, wherein a composition of the second passivation layer and third passivation layer is the same, and a process temperature for the third passivation layer is higher than that of the second passivation layer and wherein the first passivation layer comprises silicon oxide or silicon oxy-nitride and the second passivation layer, and the third passivation layer comprises silicon nitride.