Patent ID: 7565593

Claim:
An information-processing apparatus comprising: a first memory having a plurality of addressed locations, each location holding a plurality of bits; and a first control circuit, wherein the first control circuit includes: a first memory controller coupled to the first memory, the memory controller including: a read-bit-swap circuit coupled to receive data from the first memory, the read-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each read bit is coupled to one input on each of two non-adjacent multiplexers; a write-data bit-swap circuit coupled to transmit data to the first memory, the write-bit-swap circuit including a plurality of two-input one-output multiplexers, wherein each bit to be written is coupled to one input on each of two non-adjacent multiplexers; and a swap-controller circuit operatively coupled to the read-bit-swap circuit and to the write-data bit-swap circuit to selectively choose one or more spare bits in place of a corresponding number of other bits.