Patent ID: 7504693

Claim:
A strained bulk silicon or SOI (silicon on insulator) MOS (metal oxide semiconductor) transistor device having gate stress engineering with SiGe and/or Si:C, comprising: a substrate of either bulk silicon (Si) or silicon on insulator (SOI), and a gate dielectric layer over directly on a surface of the substrate; a stacked gate structure of SiGe and/or Si:C to produce stresses in a channel region of said transistor device beneath said stacked gate structure and within the substrate by the structures of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure and having a first stressed film layer of large grain size Si or SiGe formed on top the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C formed on top the first stressed film layer, and a semiconductor or conductor layer formed on top the second stressed film layer.