Patent ID: 7046565

Claim:
An electronic memory system including a memory array which includes a number of pairs of bitlines comprising: a true bitline and a complementary bitline; a first normal cell connected to the true bitline and a second normal cell connected to the complementary bitline; a first reference cell connected to the true bitline and a second reference cell connected to the complementary bitline, a clock for generating timing pulses including short circuiting-equalization pulses and for selectively providing reference potential pulses in a reference potential mode of operation; a sense amplifier having a true terminal connected to the true bitline and a complementary terminal connected to the complementary bitline; equalization short circuiting means connected to the clock and to the true bitline and the complementary bitline for short circuiting the true bitline and the complementary bitline together in response to the short circuiting pulses to equalize the electric potential thereon as a function of short circuiting-equalization; and precharge circuit means for connecting at least one of the true bitline and the complementary bitline to a electrical potential selected from a higher voltage or low voltage reference potential in response to a precharge equalization clock pulse from the clock.