Patent ID: 7948767

Claim:
A chip-level packaging integrated circuit packaging structure, comprising: a substrate having a first surface, an inner circuit formed on the first surface, a second surface opposite to the first surface, and an outer circuit with a plurality of connecting pins formed on the second surface and electrically connected to the inner circuit; a bare semiconductor die without lead frame having an active surface and a back surface opposite to the active surface, a plurality of bond pads formed on the active surface, the bare semiconductor die being mounted on the first surface of the substrate such that the plurality of bond pads contact the inner circuit; a heat-dissipating module comprising a heat pipe and a plurality of heat dissipating fins punched through by the heat pipe, the heat pipe having a flat end surface and a cylindrical surface and comprising a capillary structure and a working fluid sealed therein, the capillary structure formed on both an inner wall of the cylindrical surface and an inner wall of the flat end surface, wherein the flat end surface of the heat pipe directly bonding to the back surface of the bare semiconductor die; a protection encapsulation accommodating the bare semiconductor die, the flat end surface and a portion of the cylindrical surface of the heat pipe, wherein the cylindrical surface of the heat pipe passes through a upper surface of the protection encapsulation and the upper surface of the protection encapsulation not directly contacting with the flat end surface of the heat pipe; and a casing including a top cap, a lower cap opposite to the top cap and a side frame connected to the top cap and the lower cap, the casing enclosing the heat-dissipating module, the protection encapsulation and the substrate, wherein the lower cap has a hole and the plurality of connecting pins of the outer circuit of the substrate extends out of the hole.