Patent ID: 7993958

Claim:
A method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a data line and a drain electrode on the gate insulating layer; forming an organic semiconductor layer on the data line, the drain electrode, and an exposed portion of the gate insulating layer between the data line and the drain electrode; forming a protective member fully covering the organic semiconductor layer; forming a passivation layer on the protective member, the data line, and the drain electrode; forming a contact hole in the passivation layer to expose a portion of the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the contact hole, wherein the forming the protective member comprises: depositing an insulating layer at a temperature equal to or lower than a room temperature; and patterning the insulating layer in a dry manner to form the protective member.