Patent ID: 8723328

Claim:
A multilayer wiring substrate comprising: an interlayer insulation layer isolating a lower conductor layer from an upper conductor layer; via holes formed in the interlayer insulation layer; and via conductors formed in the respective via holes for connecting the lower conductor layer and the upper conductor layer; wherein: a surface of the interlayer insulation layer is a rough surface; the via holes open at the rough surface of the interlayer insulation layer; stepped portions are formed in opening verge regions of the surface around the via holes such that the stepped portions are recessed from peripheral regions of the interlayer insulation layer around the opening verge regions; the stepped portions are higher in surface roughness than the peripheral regions; the upper conductor layer comprises lands connected to upper ends of the corresponding via conductors continuously; and the via conductors and the upper conductor layers cover a top surface of the stepped portion and a top surface of the peripheral region.