Patent ID: 7649521

Claim:
An image display apparatus, comprising: a plurality of scanning signal lines and a plurality of data signal lines which are arranged in a matrix form; a plurality of pixels provided correspondingly to respective intersections between said plurality of scanning signal lines and said plurality of data signal lines, wherein said plurality of pixels are divided into pixel blocks, each pixel block being made up of pixels arranged along mutually different scanning lines and along a common data line, corresponding to a set of video signals to be supplied thereto by time-division; and a scanning signal line driving circuit to sequentially output a scanning signal for selecting a pixel, to each of said plurality of scanning signal lines, the pixels constituting one pixel block being sequentially selected via mutually different scanning signal lines, wherein: said scanning signal line driving circuit includes shift register groups provided in a number of k, k indicating a number of time segments in a transmission time for transmitting video signals by time division, wherein, of all the shift registers provided for respective scanning signal lines, those which correspond to the scanning signal lines connected to pixels to which the video signals are supplied in the i-th order (1·i≦k) are mutually connected in series, the video signals to be supplied to the pixels in each pixel block; and a scanning signal to be outputted to each of the scanning signal lines connected to the pixels in the first shift register group is generated by performing a logical operation to obtain a logical AND of a) an output signal from one of the shift registers in the i-th shift register group, b) an inversed signal of the output signal from the shift register in said i+1-th shift register group (the first shift register group in the case of i =k), and c) a scanning signal generation control signal supplied by a separately provided signal supply line.