Patent ID: 7057418

Claim:
A method for phase detection by an exclusive-OR gate in a half-rate phase detector using a clock signal synthesized from an incoming data signal, comprising: producing delayed versions of the clock signal; producing delayed versions of the incoming data signal; combining a first delayed version of the incoming data signal with alternate transitions of a first delayed version of the clock signal to produce first precursor signals; multiplexing the first precursor signals in response to a second delayed version of the clock signal to produce a multiplexed signal; providing the multiplexed signal only to an input of the exclusive-OR gate; combining the multiplexed signal with a second delayed version of the incoming data signal in the exclusive-OR gate to produce a phase signal indicative of a phase difference between the incoming data signal and the clock signal; combining the first precursor signals with alternate transitions of the second delayed version of the clock signal to produce second precursor signals; and combining the second precursor signals to produce a reference signal indicative of a degree of synchronization between an interval in the incoming data signal and a corresponding integration interval.