Patent ID: 8500983

Claim:
A method of controlling plating of copper interconnects on a semiconductor wafer, the method comprising: (a) immersing a plating surface of the wafer in plating bath comprising a copper salt and a suppressor while applying a cathodic current to the wafer in the range of about 1.5 to 20 mA/cm 2 during substantially the entire immersion of the plating surface; (b) within less than about 1000 ms of completing the immersion in (a), applying a high cathodic current pulse to the wafer, the pulse having a magnitude that is greater than any of the current densities applied in (a) and that is at least about 20 mA/cm 2 for a duration of about 20 to 1000 ms; and (c) within less than about 1000 ms of completing the current pulse in (b), conducting bottom up copper fill using lower current densities than the current densities of the high cathodic current pulse with a baseline current density of about 1 to 20 mA/cm 2 and a plurality of micropulses having a magnitude of about 10 to 40 mA/cm 2 above the baseline current density, the micropulses having a duration of about 1 to 495 ms, a time interval between micropulses being about 50 to 500 ms, wherein the magnitude of each micropulse, the duration of each micropulse, or the time interval between any two micropulses is random, and wherein the suppressor is distributed across the face of the wafer at different concentrations prior to (c).