Patent ID: 7301205

Claim:
A semiconductor device provided with a CMOS-FET circuit, comprising: a first element isolating film filling a trench provided around an NMOS forming region; a second element isolating film filling a trench provided around a PMOS forming region; a first insulating film provided on the first and second element isolating films; a second insulating film provided on the first insulating film; a tensile stress film provided on the second insulating film, penetrating the first and second insulating films, extending into the first element isolating film, and having a tensile stress, the tensile stress film having an end; and a compressive stress film provided on the second insulating film, penetrating the first and second insulating film, extending into the second element isolating film, and having a compressive stress, the compressive stress film having an end; wherein the end of the tensile stress film contacts the end of the compressive stress film above a region between the NMOS forming region and the PMOS forming region.