Patent ID: 8080886

Claim:
An integrated circuit semiconductor device comprising: a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern; an overlay key region formed in a second portion of the silicon substrate, the overlay key region including a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern by correcting overlay and alignment errors using the second insulating pattern; and an alignment key region formed in a third portion of the silicon substrate, the alignment key region including a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.