Patent ID: 7566901

Claim:
A thin film transistor array panel comprising: an insulating substrate; a plurality of first signal lines formed on the insulating substrate; a plurality of second signal lines formed on the insulating substrate and intersecting the first signal lines in an insulating manner; a pixel electrode formed in a pixel area defined by the intersections of the first signal lines and the second signal lines and including a plurality of subareas partitioned by cutouts and a plurality of bridges connecting the subareas; a first thin film transistor connected to the pixel electrode; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts, and a second thin film transistor connected to the direction control electrode, wherein two long edges of each subarea are parallel to each other and the at least one of the cutouts overlapping the portion of the direction control electrode defines one of two longest edges of the subarea.