Patent ID: 6937683

Claim:
A digital phase-locked tracking loop timing recovery circuit comprising: an edge detector for detecting an edge transition in an input bit stream; a digitally implemented loop counter including a plurality of registers indicative of a transition state of said loop counter, wherein said loop counter can be in one of a plurality of progressively advancing early phase transition states, a plurality of progressively advancing late phase transition states and a neutral state; and, a digitally implemented phase counter including a plurality of registers indicative of a transition state of said phase counter, said transition state of said phase counter responsive to detection of said edge transition in said input bit stream, said transition state of said loop counter, and a prior transition state of said phase counter; said transition state of said loop counter responsive to said detection of said edge transition in said input bit stream, a prior transition state of said loop counter and a transition state of said phase counter at said detection of said edge transition, wherein said circuit generates clock pulses recovered from a stream of input bits, and wherein said transition states of said phase counter are non-linear and include a first set of states indicative of an early phase, and a second set of states indicative of a late phase.