Patent ID: 7629814

Claim:
A latch circuit comprising: an input amplifying circuit that amplifies input signals; a memory logic circuit that stores data included in the input signals using signals that are amplified by the input amplifying circuit; a precharging circuit that preliminarily sets voltages of two latch output nodes to “high”, the two latch output nodes being employed for an output of data stored in the memory logic circuit; a clock synchronization switch that controls a current flowing through the input amplifying circuit; a current supply circuit that controls the current flowing through the memory logic circuit; and a reverse clock synchronization switch that preliminarily sets a voltage of a node connecting the memory logic circuit and the current supply circuit to “high”, wherein the precharging circuit and the reverse clock synchronization switch are arranged in a first transistor level at a power supply side, the input amplifying circuit and the memory logic circuit are arranged in a second transistor level, the clock synchronization switch and the current supply circuit are arranged in a third transistor level at a ground side, and the memory logic circuit is connected to the current supply circuit.