Patent ID: 7724852

Claim:
A circuit, comprising: N phase mixers to receive a primary clock signal, wherein a respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase; and a plurality of M receivers, wherein M is smaller than N, and wherein the M receivers are to receive data in accordance with respective secondary clock signals from respective ones of a first group of M phase mixers in the N phase mixers in a first time period, and to receive data in accordance with respective secondary clock signals from respective ones of a second group of M phase mixers in the N phase mixers in a second time period, the second group of M phase mixers having at least one first phase mixer that is not in the first group of M phase mixers, the first group of M phase mixers having at least one second phase mixer that is not in the second group of phase mixers; and wherein at least one receiver of the M receivers receives data in accordance with distinct secondary clock signals, output by distinct phase mixers of the N phase mixers, during the first and second time periods; a calibration circuit to calibrate a secondary clock signal output by the at least one first phase mixer in the first time period and to calibrate the secondary clock signal output by the at least one second phase mixer in the second time period; and control logic to select a coupling configuration for coupling the secondary clock signals output by the N phase mixers to the plurality of M receivers and the calibration circuit.