Patent ID: 7449392

Claim:
A method of manufacturing a semiconductor device having gates and junction regions, the method comprising the steps of: forming a pad oxide film and a pad nitride film on a silicon substrate having a device isolation region and an active region; etching the pad oxide film, the pad nitride film, and the silicon substrate to form a trench in the device isolation region; forming an insulating film spacer on a trench sidewall including the etched pad oxide and nitride films; laterally etching a portion of the active region in the silicon substrate to form a vacant space using the pad oxide film, the pad nitride film, and the insulating film spacer as etch barriers; removing the insulating film spacer; forming a conductive electrode on the surface adjoining the laterally etched portion in the active region and on the surface of the trench in the isolation region; and filling up the trench and the laterally etched portion with an oxide film to form a device isolation film, wherein a vacant cavity is present between the device isolation film and the conductive electrode.