Patent ID: 6936879

Claim:
A dynamic random access memory cell, comprising: a FET comprising: a first and second source/drain region formed in a silicon substrate; a channel region between said first and second source/drain regions; a gate dielectric formed over said channel region; a wordline formed over said gate dielectric; and a bitline electrically connected to said first source/drain; a trench capacitor comprising: a trench in said silicon substrate, said trench having a sidewall and a bottom portion; pits etched into said sidewall and said bottom portion, said pits formed in a pattern; a node insulator layer on said pits, said sidewall and said bottom portion; and a trench conductor filling said trench, and said second source/drain electrically connected to said trench conductor by a conductive strap having a bottom surface, said bottom surface of the conductive strap being in direct mechanical and electrical contact with a top surface of the trench conductor and being coplanar with a top surface of said second source/drain.