Patent ID: 7392339

Claim:
A method of operating a memory device having multiple memory bank arrays utilizing a memory controller and being responsive to command signals, address signals, and a plurality of bank address signals, the method comprising: specifying, via a precharge scheduler in the memory controller, a plurality of the multiple memory bank arrays to be precharged using an address signal and a plurality of bank address signals, wherein the precharge scheduler operates using a credit model and the precharge scheduler is utilized to schedule precharges for only the specified plurality of memory banks; and initiating in response to first command signals a precharge command controlling a precharge operation to the specified plurality of memory banks, but not all of the multiple memory bank arrays, wherein the memory controller includes a counter for each of the specified plurality of memory banks, updates the counter each time a precharge occurs for the specified plurality of memory banks, and decrements the counter each time a refresh period has elapsed.