Patent ID: 7246252

Claim:
A delay compensation system, comprising: a first integrated circuit, the first integrated circuit including output drivers, one of the output drivers configured to provide a transmit clock signal and another of the output drivers configured to provide a read command signal; and a second integrated circuit coupled to the first integrated circuit to receive the transmit clock signal and the read command signal, the second integrated circuit configured to provide a read clock signal responsive to the transmit clock signal and to provide a data signal responsive to the read command signal, wherein the first integrated circuit includes a delay compensation circuit, the delay compensation circuit being configured to operate synchronously with the transmit clock signal for a send portion and to operate synchronously with the read clock signal on a receive portion and wherein the delay compensation circuit includes a counter configured to count responsive to clock pulses to track latency of the second integrated circuit and wherein the counter is configured to reset a count responsive to a latency parameter of the second integrated circuit, the count being enabled to wait for a period of data validity for the data signal.