Patent ID: 8089316

Claim:
A broadband active circuit with a feedback structure, the active circuit comprising: an active load unit providing a load varied according to control voltages; an active circuit unit connected between the active load unit and a ground and outputting a signal corresponding to a pre-set bandwidth, among input signals; and a feedback circuit unit formed between output terminals of the active circuit unit and the active load unit and providing signals from the output terminals of the active circuit unit to the active load unit, wherein the active load unit comprises: a first PMOS transistor having a source connected to a power voltage terminal, a gate receiving a first control voltage among the control voltages, and a drain connected to a first output terminal among the output terminals; and a second PMOS transistor having a source connected to the power voltage terminal, a gate receiving a second control voltage among the control voltages, and a drain connected to a second output terminal among the output terminals, wherein the active circuit unit comprises: a first NMOS transistor having a drain connected to the first output terminal, a source, and a gate connected to a first input terminal; a second NMOS transistor having a drain connected to the second output terminal, a source, and a gate connected to a second input terminal; and a third NMOS transistor having a drain connected to a connection node between the sources of the first and second NMOS transistors, a gate connected to a first bias voltage terminal, and a source connected to the ground, wherein the feedback circuit unit comprises: a first inductor having one end connected to the power voltage terminal; a second inductor having one end connected to the power voltage terminal; a fourth NMOS transistor having a drain connected to the other end of the first inductor, a source, and a gate connected to the first output terminal; a fifth NMOS transistor having a drain connected to the other end of the second inductor, a source, and a gate connected to the second output terminal; and a sixth NMOS transistor having a drain connected to a connection node between the sources of the fourth and fifth NMOS transistors, a gate connected to a second bias voltage terminal, and a source connected to the ground.