Patent ID: 7975195

Claim:
A scan latch comprising: a logic data output storage circuit comprising: a first transistor that controls a connection between a first data latch node of the logic data output storage circuit and a LOW logic signal source based on a slave phase clock signal of a two-phase clock; and a second transistor that controls a connection between a second data latch node of the logic data output storage circuit and the LOW logic signal source based on a scan clock signal; a logic data pass-through switch that controls entry of a logic data from a combinational logic circuit to the first data latch node based on the slave phase clock signal; a scan data output storage circuit comprising: a first transistor that controls a connection between a first scan latch node of the scan data output storage circuit and a LOW logic signal source based on the scan clock signal; a first scan data pass-through switch that controls entry of a scan data from a scan data source to the first scan latch node based on the scan clock signal; and a second scan data pass-through switch that controls passage of the scan data from a second scan latch node to the second data latch node based on the scan clock signal.