Patent ID: 7196369

Claim:
An integrated circuit device, comprising: a device substrate; integrated circuitry on the device substrate to be protected from plasma damage during manufacture, the integrated circuitry conductively coupled to a node, and the node having operating voltages applied thereto during operation; a MOS transistor on the device substrate, having a gate, a semiconductor bulk conductively coupled to its gate, and a source and a drain in the semiconductor bulk; one of the source and drain of the MOS transistor being conductively coupled to said node, the other of the source and drain of the MOS transistor being conductively coupled to a ground reference; the gate of the MOS transistor floating during manufacture, and being conductively coupled to at least one of a positive voltage and a negative voltage, said at least one of the positive voltage and the negative voltage biasing the MOS transistor in a normally off condition during operation at said operating voltages.