Patent ID: 7932544

Claim:
A layout of an integrated circuit device, comprising: a diffusion level layout portion including a plurality of diffusion region layout shapes to be formed within a portion of a substrate, wherein the plurality of diffusion region layout shapes respectively correspond to active areas of the portion of the substrate within which one or more processes are applied to modify one or more electrical characteristics of the active areas of the portion of the substrate, wherein the plurality of diffusion region layout shapes are separated from each other by one or more non-active regions of the portion of the substrate; and a gate electrode level layout portion defined to pattern conductive features within a gate electrode level over the portion of the substrate corresponding to the diffusion level layout portion, the gate electrode level layout portion including six linear-shaped layout features placed to extend lengthwise in a first parallel direction, wherein each of the six linear-shaped layout features is defined to include one or more gate electrode portions which extend over one or more of the plurality of diffusion region layout shapes, wherein each gate electrode portion and a corresponding diffusion region layout shape over which it extends together define a respective transistor device, wherein the six linear-shaped layout features include, a first linear-shaped layout feature defined to form both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, a second linear-shaped layout feature defined to form a gate electrode of a second transistor of the first transistor type, a third linear-shaped layout feature defined to form a gate electrode of a second transistor of the second transistor type, a fourth linear-shaped layout feature defined to form a gate electrode of a third transistor of the first transistor type, a fifth linear-shaped layout feature defined to form a gate electrode of a third transistor of the second transistor type, a sixth linear-shaped layout feature defined to form a gate electrode of both a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type, wherein the fourth linear-shaped layout feature includes a first portion that forms the gate electrode of the third transistor of the first transistor type and a second portion that extends away from the third transistor of the first transistor type, wherein a length of the second portion that extends away from the third transistor of the first transistor type is greater than a length of the first portion that forms the gate electrode of the third transistor of the first transistor type.