Patent ID: 8799438

Claim:
One or more computer-readable storage devices storing computer-executable instructions, that when executed by a processor, configure the processor to perform acts comprising: receiving a first graph of nodes, the nodes of the first graph being arranged in a first topology; receiving a second graph of nodes, the nodes of the second graph being arranged in a second topology, the first topology and the second topology both being representations of an entity; selecting a first node from the first graph and a first node from the second graph, the first node from the first graph and the first node from the second graph being a first anchor pair; determining that the first node from the first graph and the first node from the second graph are symmetrical to each other; generating a one-hop subgraph of the first graph and a one-hop subgraph of the second graph, the one-hop subgraph of the first graph comprising at least nodes that are a single connection link from the first node of the first graph, and the one-hop subgraph of the second graph comprising at least nodes that are a single connection link from the first node of the second graph; determining if the one-hop subgraph from the first graph and the one-hop subgraph from the second graph are isomorphic; and if the one-hop subgraph of the first graph and the one-hop subgraph of the second graph are not isomorphic, incrementing counters that are associated with the nodes of the one-hop subgraph of the first graph and incrementing counters associated with the nodes of the one-hop subgraph of the second graph.