Patent ID: 8612910

Claim:
A computer-implemented method for analyzing an integrated circuit design, the method comprising the steps of: providing at least one processor; providing a memory coupled to the at least one processor, the memory including logic blocks in the integrated circuit design and a plurality of user assertions for the integrated circuit design that are separate from the logic blocks; the at least one processor performing the steps of: (A) reading the plurality of user assertions for the integrated circuit design from the memory, each of the plurality of user assertions defining a performance target for the integrated circuit design, the plurality of user assertions including a first user assertion that references a first clock and a second user assertion that references a second clock, wherein the first clock is a real clock in the integrated circuit design and the second clock does not correspond to a real clock in the integrated circuit design; (B) reading at least one clock alias that correlates the second clock to the first clock; and (C) using the clock alias to generate a new user assertion that references the first clock from an existing user assertion that references the second clock, the timing analysis mechanism performing timing analysis of the integrated circuit design using the new user assertion.