Patent ID: 8108607

Claim:
A system comprising: a master device to provide control information for memory access; an integrated circuit buffer device including: a first interface to receive the control information; a second interface to output the control information; and a register to store a value that indicates a number of ranks of integrated circuit memory devices to perform the memory access in response to the control information; a first signal path extending from the second interface; a second signal path, separate from the first signal path, extending from the second interface; a first plurality of integrated circuit memory devices forming a first rank to output a first predetermined amount of data onto the first signal path, the first signal path to convey the first predetermined amount of data from the first rank to the second interface in response to the control information; and a second plurality of integrated circuit memory devices forming a second rank to output a second predetermined amount of data onto the second signal path, the second signal path to convey the second predetermined amount of data from the second rank to the second interface in response to the control information.