Patent ID: 6904538

Claim:
A data detector, comprising: a delay logic, receiving an unfiltered input signal in quadrature and in-phase components, and applying a delay to each of the in-phase and quadrature phase components of the unfiltered input signal; a first multiplication logic, the first multiplication logic multiplying the delayed in-phase component of the unfiltered input signal by the quadrature phase component of the unfiltered input signal to obtain a first multiplication result; a second multiplication logic, the second multiplication logic multiplying the delayed quadrature phase component of the unfiltered input signal by the in-phase component of the unfiltered input signal to obtain a second multiplication result; an adder, the adder adding the first multiplication result with the second multiplication result and generating a decision signal; and a post-detection correction logic, the post-detection correction logic being applied to the decision signal to reduce inter-symbol interference.