Patent ID: 7671626

Claim:
A device, comprising: a plurality of logic array blocks arranged in an array, one of the logic array blocks in the array including: a first logic element (LE) including a first input pin, a second input pin, a third input pin and a fourth input pin; a second logic element (LE) including a fifth input pin, a sixth input pin, a seventh input pin and an eighth input pin; a secondary signal generation unit configured to send signals to the first logic element and the second logic element, the signals including an add-or-subtract control signal, a synchronous clear signal, and a synchronous load signal; a first group of routing lines, each of the first group of routing lines coupled with the first input pin, the third input pin, the fifth input pin and the seventh input pin; and a second group of routing lines, each of the second group of routing lines coupled with the second input pin, the fourth input pin, the sixth input pin and the eighth input pin.