Patent ID: 7206956

Claim:
A memory device comprising: a memory array configured to store data; an output circuit operatively coupled to the memory array and configured to hold data accessed from the memory array in response to a read request and to generate a data output signal comprising the data accessed from the memory array; and a delay lock loop operatively coupled to the output circuit and configured to receive a reference clock signal and to generate an output clock signal based on the reference clock signal, the delay lock loop comprising: a synchronization circuit configured to generate the output clock signal by shifting a phase of the reference clock signal and adjusting a clock duty cycle of the reference clock signal to introduce a first distortion in a duty cycle of the output clock signal with respect to the reference clock signal, wherein the first distortion is phase-inverted with respect to a second distortion introduced by at least one component of the output circuit during operation such that, when the output clock signal is applied to the output circuit, the output clock signal compensates for output data duty cycle distortion.