Patent ID: 8564340

Claim:
A dual phase locked loop (PLL) circuit with an output signal, comprising: a phase/frequency detector, for generating an error signal; a charge pump, coupled to the phase/frequency detector, for generating a charge pump signal according to the error signal; a coarse-tuning circuit, coupled to the charge pump, for coarse-tuning a frequency of the output signal of the dual PLL circuit to approximate a target frequency, the course-tuning circuit comprising: a first filter unit, coupled to the charge pump, for removing high frequency components of the charge pump signal to generate a first control voltage; and a first voltage-to-current converting unit, coupled to the first filter unit, for converting the first control voltage to a first control current; a fine-tuning circuit, coupled to the charge pump, for fine-tuning the frequency of the output signal of the dual PLL circuit to the target frequency, the fine-tuning circuit comprising: a second filter unit, coupled to the charge pump, for removing high frequency components of the charge pump signal to generate a second control voltage; and a second voltage-to-current converting unit, coupled to the second filter unit, for converting the second control voltage to a second control current; a current control oscillator (CCO), coupled to the coarse-tuning circuit and the fine-tuning circuit, for generating the output signal having the target frequency, the current control oscillator being a loop oscillator comprising a plurality of inverters; an N divider, coupled to the CCO and the phase/frequency detector, for frequency-dividing by N the frequency of the output signal of the dual PLL circuit, wherein the first filter unit comprises a resistor having a predetermined resistance and a capacitor connected in series as a first RC circuit, the second filter unit comprises a second RC circuit, and as a result of the predetermined resistance the first RC circuit has a greater time constant than that of the second RC circuit; and wherein the first voltage-to-current converting unit comprises a first N-path metal oxide semiconductor (NMOS) transistor, the second voltage-to-current converting unit comprises a second NMOS transistor, the first transistor has its gate coupled to a first output end of the first filter unit and the second transistor has its gate coupled to a second output end of the second filter unit, a source of the first transistor is coupled to a source of the second transistor, so that the first transistor and the second transistor form a parallel source follower to provide a total current to the CCO to control the CCO to generate the output signal of the dual PLL circuit having the target frequency.