Patent ID: 8065651

Claim:
An method for testing a circuit, the method comprising: configuring, by computer, a first design-for-test (DFT) core to perform a test on a first module of the circuit, by: configuring a set of test inputs of the DFT core to receive a compressed test vector; configuring a combinational decompression logic of the first DFT core to generate an uncompressed test vector by decompressing the compressed test vector, wherein the uncompressed test vector is scanned into a set of scan chains; configuring a combinational compression logic to generate a compressed response vector by compressing a response vector, wherein the response vector is scanned out of the set of scan chains; and configuring a set of response outputs of the first DFT core to receive the compressed response vector; configuring a first series of flip-flops to receive an input bit stream associated with the compressed test vector, wherein an output of a first flip-flop in the first series of flip-flops is coupled to a first test input in the set of test inputs; configuring a second series of flip-flops to generate a first output bit stream associated with the compressed response vector, wherein a first response output in the set of response outputs is coupled to an input of a first flip flop in the second series of flip flops; and configuring a first set of multiplexers to interface the outputs of the first series of flip-flops with the set of test inputs of the first DFT core, wherein the first set of multiplexers are used to input the compressed test vector into the test inputs of the first DFT core in a forward direction or in a backward direction.