Patent ID: 7665207

Claim:
A method of making a multi-chip electronic package comprising: providing an organic, laminate chip carrier having first and second surfaces and including a plurality of electrically conductive planes spacedly positioned therein and separated by respective layers of dielectric material, at least one of said layers of dielectric material being comprised of polytetrafluoroethylene (PTFE); providing a plurality of electrical contacts on said first surface of said organic, laminate chip carrier; providing a plurality of electrical conductors on said second surface of said organic, laminate chip carrier, selected ones of said electrical contacts being electrically coupled to selected ones of said electrical conductors; positioning an application specific integrated circuit (ASIC) semiconductor chip on said first surface of said organic, laminate chip carrier and electrically coupling said ASIC semiconductor chip to said selected ones of said electrical contacts using a first plurality of solder balls; positioning a memory semiconductor chip on said ASIC semiconductor chip using an adhesive such that said ASIC and memory semiconductor chips form a stacked orientation, said positioning of said memory semiconductor chip including positioning of a second plurality of solder balls between said memory semiconductor chip and said ASIC semiconductor chip to provide a thermal path between said ASIC semiconductor chip and said memory semiconductor chip; electrically coupling said memory semiconductor chip to others of said selected ones of said electrical contacts using a wirebond operation while said memory semiconductor chip is positioned on said ASIC semiconductor chip and said second plurality of solder balls are positioned between said ASIC semiconductor chip and said memory semiconductor chip; and positioning a metal heat-sinking member substantially over said ASIC semiconductor chip and said memory semiconductor chip.