Patent ID: 7020749

Claim:
A signal processor comprising: a processor having a cache memory and a process execution unit executing a process by use of information temporarily stored in the cache memory; and an external memory provided external to the processor, wherein the process execution unit automatically returns to a start point of loop-type data at an end of the loop-type data and sequentially reads out the loop-type data from the external memory to the cache memory and the process execution unit comprises: an instruction decoding/issuing unit configured to receive an execution instruction; a register file configured to receive a register number specifying a signal from the instruction decoding/issuing unit; a prefetch execution control unit configured to receive a prefetch instruction execution signal from the instruction decoding/issuing unit and register content output data from the register file; an external memory control unit configured to receive an external memory control instruction signal from the prefetch execution control unit; a cache memory control unit configured to receive a cache memory control instruction signal from the prefetch execution control unit; and a data process unit coupled to the external memory control unit and to the cache memory control unit, and the prefetch execution control unit comprises: a temporary memory configured to receive the register content output data from the register file; a prefetch address operational generator/comparator unit which receives data from the temporary memory; a prefetch block number operation unit configured to receive prefetch block number data different from the data from the temporary memory and transmits/receives a first control signal to/from the prefetch address operational generator/comparator unit; and an external memory access number status decision unit configured to receive an external memory control instruction response signal from the external memory control unit receiving external memory access address information transmitted from the prefetch address operational generator/comparator unit, and transmits a second control signal to the prefetch address operational generator/comparator unit.