Patent ID: 7045397

Claim:
A process of making a JFET structure comprising the steps of: (a) etching a trench in a substrate, wherein the substrate comprises a layered structure including an n+ type layer forming a source, an n type layer, and an n+ type layer forming a drain; (b) forming a bottom oxide layer within a well of said trench; (c) depositing a first spacer layer on walls of said trench; (d) partially etching back said bottom oxide layer to form windows between said bottom oxide layer and said first spacer layer, wherein said windows expose portions of said n type layer; (e) forming a doped polysilicon layer on said etched bottom oxide layer, and within said windows; (f) annealing said doped polysilicon layer to form a gate silicide layer on said etched bottom oxide layer, so that portions of said doped polysilicon layer remain within said windows; wherein said annealing further forms p-type regions by laterally diffusing impurities from said doped polysilicon into said n type layer, creating a p-n junction; and (g) filling said trench with another oxide layer deposited on said silicide layer.