Patent ID: 8123969

Claim:
A method of forming vertical conductors for multilayer conductor structures on a workpiece, comprising: forming an underlying conductor layer on said workpiece; depositing a dielectric layer over said underlying conductor layer; forming an opening of diameter of 65 nm or less through said dielectric layer to expose a corresponding surface portion of said underlying conductor layer at the bottom of said opening while leaving dielectric material on said surface portion of said underlying layer; treating a metal lid to produce a reentrant surface profile and a surface roughness in excess of RA 2000 on an interior surface of the lid, and installing the metal lid as the ceiling of a plasma reactor chamber having a workpiece support pedestal facing the interior surface of the ceiling; placing said workpiece on said workpiece support pedestal; removing said dielectric material from said surface portion of said underlying conductor layer by generating a plasma in said chamber, so as to generate residue of said dielectric material in said chamber, while capturing at least a portion of said residue on said interior surface of said lid; and wherein said generating a plasma comprises: (1) introducing an inert gas into said reactor chamber; (2) coupling VHF plasma source power of 60 MHz or greater to the wafer pedestal of a sufficient power level to establish an etch rate on the order of 200-500 Å/min at a surface of said workpiece; (3) coupling LF or HF plasma bias power of 13.56 MHz or less of a sufficient power level to realize an etch rate on the order of 200-500 Å/min of said dielectric residue at said bottom said opening; (4) evacuating said reactor chamber to maintain a desired chamber pressure.