Patent ID: 7129143

Claim:
A method of fabricating a semiconductor device having a dual spacer, the method comprising: depositing first and second insulation films on a semiconductor substrate sequentially and patterning the second insulation film to form an opening; forming an inner sparer on an inner wall of the opening such that the inner spacer has a height less than a height of the inner wall of the opening; depositing conductive material in the opening and forming a gate poly by planarizing the conductive material such that the gate poly has a wide upper portion defined by a width of the opening and a narrow lower portion defined by the inner spacer; removing the second insulation film and forming a lightly doped drain (LDD) using the gate poly and the inner spacer as a mask; forming an outer spacer on side walls of the gate poly and the inner spacer; forming source/drain regions using the gate poly and the outer sparer as a mask; and forming a suicide film on the gate poly and the source/drain regions.