Patent ID: 8477539

Claim:
A non-volatile memory cell, which is used to store a single bit data, comprising: a substrate having a first conductive type; a first store transistor and a second store transistor disposed in the substrate, wherein a first gate of the first transistor and a second gate of the second transistor are coupled to each other, wherein the first transistor and the second transistor both have a second conductive type opposite to the first conductive type; and a select transistor having a second conductive type disposed in the substrate, wherein a first source region of the first transistor is coupled to a bit line, wherein a second drain region of the second transistor and a select gate of the select transistor are coupled to a select gate line, wherein a first drain region of the first transistor is coupled to a source region of the select transistor, and wherein a third drain region of the select transistor is coupled to a select line, so that a bit is stored in the first and second gates by controlling the bit line and the select gate line, or the bit stored in the first and second gates is erased by controlling the bit line and the select gate line.