Patent ID: 7564317

Claim:
A high/low voltage tolerant interface circuit, comprising: a first transistor, having a gate, a first source/drain, a second source/drain and a bulk, wherein the first source/drain is coupled to an input node; a bulk-voltage generator module, coupled to the first source/drain of the first transistor for determining whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to a voltage of the input node, wherein the predetermined voltage is greater than the first voltage; and a bias module, coupled to the gate of the first transistor for providing a bias to the gate of the first transistor so as to make the first transistor conduct and control a voltage of the second source/drain of the first transistor, wherein the bias module comprises: a first circuit, coupled between the second source/drain and the gate of the first transistor for sensing a voltage of the second source/drain of the first transistor so as to provide the bias to the gate of the first transistor; and a second circuit, coupled between the first source/drain and the gate of the first transistor for sensing a voltage of the first source/drain of the first transistor and determining whether or not to adjust the bias.