Patent ID: 7211851

Claim:
A ferroelectric memory comprising: a first N channel MOS transistor connected between N 1 and N 2 nodes; a second N channel MOS transistor connected between the N 2 node and an N 3 node; a first P channel MOS transistor connected between P 1 and P 2 nodes; a second P channel MOS transistor connected between the P 2 node and a P 3 node; a first wiring formed in a first wiring layer to interconnect the N 1 node and the P 1 node; a second wiring formed in the first wiring layer to interconnect the N 3 node and the P 3 node; a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N 2 node and the P 2 node; a first ferroelectric capacitor whose first electrode is connected to the first wiring; and a second ferroelectric capacitor whose first electrode is connected to the second wiring, wherein second electrodes of the first and second ferroelectric capacitors are both connected to the N 2 node or the P 2 node.