Patent ID: 6883045

Claim:
A computer system comprising: one or more processors; an input/output node connected to said one or more processors through a point-to-point packet bus; and a graphics bus coupled to convey address, data and control signals between said input/output node and one or more graphics adapters; wherein said input/output node includes a peripheral interface circuit including an apparatus for reordering graphics transactions, said apparatus comprising: a data buffer including a first plurality of storage locations each corresponding to one of a plurality of tag values, wherein said data buffer is configured to receive a plurality of data packets associated with said graphics transactions each having one of said plurality of tag values, and wherein said data buffer is configured to store said plurality of data packets in said first plurality of storage locations according to said tag values; and a control unit coupled to said data buffer and including a storage unit having a second plurality of locations each corresponding to one of said plurality of tag values, wherein each of said second plurality of locations is configured to provide an indication of whether a given data packet has been stored in said data buffer; wherein said control unit is further configured to determine an order in which said plurality of data packets is read from said data buffer.