Patent ID: 7691698

Claim:
A method of fabricating a semiconductor device, comprising: forming stress inducing layers under a first gate structure, wherein the stress inducing layers comprise: (i) a SiGe layer formed on a first Si layer formed on a substrate and (ii) a second Si layer formed on the SiGe layer; protecting portions of the stress inducing layers under the first gate structure; protecting a second gate structure having a stress component associated therewith; etching unprotected areas of the stress inducing layers at sides of the first gate structure to form openings and a resulting stress under the first gate structure, wherein the etching exposes an upper surface of the first Si layer formed on the substrate; forming a second SiGe layer on etched portions of a silicon layer of the second gate structure; forming a third Si layer on the second SiGe layer; filling the openings with a material by forming a fourth Si layer on the exposed upper surface of the first Si layer; and forming a shallow trench isolation (STI) on the substrate, wherein the stress inducing layers are formed adjacent to the STI, and a bottom surface of the STI and a bottom surface of the first Si layer are formed on an upper surface of the substrate.