Patent ID: 7733151

Claim:
A clock signal generating system for generating an output clock signal comprising: a phase locked loop (PLL) circuit which requires a reference clock signal of at least a predetermined first frequency, an output of the PLL circuit being coupled to generate the output clock signal; and a clock signal multiplication circuit having: an oscillator; a counter circuit that is clocked by an oscillator clock signal produced by the oscillator and that is coupled to receive a first clock signal of a second frequency that is substantially lower than the first frequency, wherein the counter circuit samples its contents in response to the first clock signal; a clock filter and clock period estimator circuit that is coupled to receive the sampled contents of the counter circuit; a first delta-sigma modulator that is coupled to receive an estimate which is representative of the period of the first clock signal multiplied by a ratio of the first frequency to the second frequency, and which is produced by the clock filter and clock period estimator circuit for producing an integer representation of the estimate; a memory for receiving a predetermined number of the integer representations; and a first divider circuit coupled to divide the oscillator clock signal by the predetermined number of the integer representations to generate a second clock signal which has a frequency at least as high as the first frequency, wherein the output clock signal is phase-locked with respect to the first clock signal, and wherein a reference clock input of the PLL circuit is coupled to receive the second clock signal.