Patent ID: 7763935

Claim:
A semiconductor structure, at least comprising: a semiconductor substrate; a plurality of buried diffusion (BD) regions formed in the semiconductor substrate, including pairs of adjacent BD regions that are spaced a channel region apart; an ONO dielectric formed on the semiconductor substrate, the ONO dielectric comprising a first ONO dielectric group having a first thickness formed above the BD regions and a second ONO dielectric group having a second thickness formed above the channel regions; and a gate structure formed on the ONO dielectric, wherein the first thickness of the first ONO dielectric group is less than the second thickness of the second ONO dielectric group, and the thickness of a first bottom dielectric layer of the first ONO dielectric group is less than the thickness of a second bottom dielectric layer of the second ONO dielectric group, the first and second bottom dielectric layers respectively being the lowest layers of the first and second ONO dielectric groups, and wherein a bottom surface of the first bottom dielectric layer of the first ONO dielectric group and a bottom surface of the second bottom dielectric layer of the second ONO dielectric group contact a surface of the semiconductor substrate.