Patent ID: 7646185

Claim:
A synchronous switching regulator controller comprising a first switch driver coupled to a first terminal to provide a first driving signal, a second switch driver coupled to a second terminal to provide a second driving signal, a PWM ramp clock generator providing a PWM ramp clock signal to a PWM comparator and a control logic circuit generating control signals for the first and second switch drivers based at least in part on the output signal of the PWM comparator, the synchronous switching regulator controller comprising: a switch detection circuit receiving a power cycle signal indicating that the synchronous switching regulator controller is to be turned on and the PWM ramp clock signal, the switch detection circuit measuring a voltage at an output node of the second switch driver, the switch detection circuit providing a driver enable signal to the control logic circuit in response to the assertion of the power cycle signal, the driver enable signal having a first logical state when the voltage at the output node of the second switch driver is greater than a reference voltage and a second logical state when the voltage at the output node of the second switch driver is less than the reference voltage, wherein the control logic circuit disables the second switch driver when the drive enable signal has the first logical state and enables the second switch driver when the drive enable signal has the second logical state.