Patent ID: 7343589

Claim:
A computer-implemented method, comprising: reading computer code comprising at least one variable and a code transaction; detecting a statement within the code, the statement specifying the code transaction and a manner in which the specified code transaction is to be analyzed, and indicating that in a first logic path following from the statement an exception occurred in connection with the code transaction and in a second logic path following from the statement an exception did not occur in connection with the code transaction; analyzing the specified code transaction in the manner specified in the corresponding statement and according to each logic path and determining an assignment state of the at least one variable in each of the first and second logic paths following from the statement; merging the assignment state of the at least one variable as determined in the first logic path with the assignment state of the at least one variable as determined in the second logic path; and determining that a function is invalid if the function is performed within the code with respect to the at least one variable while the at least one variable has a merged assignment state being an incorrect assignment state, otherwise determining that the function is valid; and processing the computer code according to the determination.