Patent ID: 7608480

Claim:
A semiconductor device fabrication method comprising: preparing a base member having at least one conductive surface formed at least at predetermined portions of a given surface of the base member, and separately arranging, on the at least one conductive surface at the predetermined portions of said given surface of the base member, a plurality of semiconductor constructing bodies each including a semiconductor substrate and a plurality of external connection bump electrodes formed on the semiconductor substrate; forming an insulating layer on the base member around the semiconductor constructing bodies; forming at least one upper interconnecting layer on one of the semiconductor constructing bodies and the insulating layer, such that the upper interconnecting layer is electrically connected to one of the external connection bump electrodes of the semiconductor constructing body; forming a vertical conducting portion which electrically connects said given surface of the base member and the upper interconnecting layer through at least the insulating layer; and cutting the insulating layer and base member between the semiconductor-constructing bodies, thereby obtaining a plurality of semiconductor devices each including at least one semiconductor constructing body.