Patent ID: 7180765

Claim:
A ferroelectric memory comprising: a ferroelectric capacitor to store data; a bit line inputting and outputting data with respect to said ferroelectric capacitor; a first switching element selectively connecting said ferroelectric capacitor and said bit line; a control circuit including a first field effect transistor to be connected to said bit line and a reference potential, and to lower potential of said bit line when said bit line is connected to said ferroelectric capacitor; a reference ferroelectric capacitor to store fixed data; a reference bit line to input and output data with respect to said reference ferroelectric capacitor; a reference switching element selectively connecting said reference ferroelectric capacitor and said reference bit line; and a second field effect transistor to be connected to said reference bit line and the reference potential, wherein said first field effect transistor and said second field effect transistor configure a current mirror circuit.