Patent ID: 8112691

Claim:
A computer-based method comprising: using a single SIMD pipeline in a processor to perform a process for generating a Fletcher/Alder checksum for a data string, said process comprising: accumulating a plurality of first sub-partial checksums S 1 [ 0 ], S 1 [ 1 ], . . . , S 1 [N−1], where N is an integer; N is a degree of SIMD processing; and said plurality of first sub-partial checksums S 1 [ 0 ], S 1 [ 1 ], . . . , S 1 [N−1] are stored in integer registers of said processor; accumulating a plurality of second sub-partial checksums S 2 [ 0 ], S 2 [ 1 ], . . . , S 2 [N−1] wherein said plurality of second sub-partial checksums S 2 [ 0 ], S 2 [ 1 ], . . . , S 2 [N−1] are stored in integer registers of said processor; accumulating said plurality of second sub-partial checksums S 2 [ 0 ], S 2 [ 1 ], . . . , S 2 [N−1] to generate a SIMD second partial checksum; scaling said SIMD second partial checksum, using a shift operation, by N to obtain a scaled SIMD second partial checksum; correcting said scaled SIMD second partial checksum to generate a second partial checksum S 2 ; accumulating said plurality of first sub-partial checksums S 1 [ 0 ], S 1 [ 1 ], . . . , S 1 [N−1] to generate a first partial checksum S 1 ; combining said first and second partial checksums S 1 , S 2 to generate a Fletcher/Alder checksum for said data string; and storing said Fletcher/Alder checksum in a memory wherein said Fletcher/Alder checksum is for use in determining integrity of said data string.