Patent ID: 8222693

Claim:
A transistor circuit comprising: a semiconductor body; a plurality of transistor cells in the body, each cell having a channel region in the body and, underlying the channel region, a drain drift region; an array of trenches extending from an upper surface of the semiconductor body, each trench extending through one of the channel regions and into an underlying drain drift region; and in each trench, a gate dielectric insulating layer extending from an upper surface of the semiconductor body, over a top corner of the trench and along a sidewall of the trench adjacent to both the channel region and the drain drift region; a layer of silicon nitride laterally adjacent a portion of the gate dielectric insulating layer that is adjacent the drain drift region; a layer of silicon dioxide laterally adjacent a portion of the gate dielectric insulating layer that is adjacent the drain drift region; a gate immediately laterally adjacent a portion of the gate dielectric insulating layer that is adjacent the channel region; and a field plate below the gate and separated from a portion of the gate dielectric insulating layer that is adjacent the drain drift region by the respective layers of silicon nitride and silicon dioxide.