Patent ID: 8084317

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming a gate electrode on a semiconductor substrate having a device isolation region, wherein forming the gate electrode comprises forming an insulation layer on the semiconductor substrate, forming a polysilicon layer on the insulation layer, forming a hard mask layer on the polysilicon layer, and patterning the insulation layer, the polysilicon layer, and the hard mask layer to form a gate insulation layer, the gate electrode, and a hard mask, respectively; forming a first drain spacer on sidewalls of the gate insulation layer, the gate electrode, and the hard mask on one side of the gate electrode and forming a first spacer layer on an opposite side of the gate electrode and on the semiconductor substrate where a source region is to be formed; forming an asymmetric Lightly Doped Drain (LDD) region by implanting ions into the exposed semiconductor substrate next to the first drain spacer and implanting ions through the first spacer layer; and forming a second drain spacer next to the first drain spacer, partially removing the first spacer layer on the semiconductor substrate where the source region is to be formed to form a first source spacer on sidewalls of the gate insulation layer, the gate electrode, and the hard mask, and forming a second source spacer on side and top surfaces of the first source spacer.