Patent ID: 8203976

Claim:
An interface device comprising a package on which a function block is mounted, the function block including: a parallel-to-serial converting unit configured to convert parallel signals, which are input in parallel thereto, to a single-end signal; a low voltage differential signaling (LVDS) driver configured to convert the single-end signal from the parallel-to-serial converting unit to an LVDS signal; an LVDS receiver configured to convert an LVDS signal, which is input thereto, to a single-end signal; and a serial-to-parallel converting unit configured to convert the single-end signal from the LVDS receiver to parallel signals, wherein the parallel-to-serial converting unit and the LVDS driver are utilized to transmit data, the LVDS receiver and the serial-to-parallel converting unit are utilized to receive data, the function block utilizes a CPU bus, each component in the package switches a transmission direction so as to transmit data when a binary input signal is at a low level, and so as to receive data when the binary input signal is at a high level, and a read signal, which is issued by a CPU to the CPU bus, which is at the low level when the CPU issues an instruction for a reading operation, and which is at the high level when the CPU issues no instruction for a reading operation, is input as an AND signal with a signal at the high level via an AND circuit to each component in the package.