Patent ID: 7180124

Claim:
A memory device having nonvolatile cells, comprising: a device isolation layer formed at a predetermined region of a semiconductor substrate, the device isolation layer defining an active region; a cell trench region formed at a portion of the active region, the cell trench region including a first sidewall, a second sidewall and a bottom surface; a first insulated floating gate and a second insulated floating gate formed on the first and second sidewalls, respectively, the first and second insulated floating gates being spaced apart from each other; a source region formed at the bottom surface of the cell trench region; a common source line interposed between and in contact with the first and second insulated floating gates, the common source line being electrically connected to the source region; a first insulated word line and a second insulated word line overlapping the active region in areas of the active region adjacent to the first and second insulated floating gates, respectively; and a first drain region and a second drain region formed in the active region and adjacent to the first and second insulated word lines, respectively.