Patent ID: 7588984

Claim:
A method to determine the predetermined location of a transistor gate of a dynamic random access memory (DRAM), wherein two trench capacitors are provided in a substrate at two sides of the gate, respectively along the direction of a bit line, said method comprising: forming a patterned first mask layer over the substrate so that at a location where the two trench capacitors are to be built, said substrate is exposed; building said two trench capacitors at the location of said exposed substrate; forming a first dielectric layer to cover said two trench capacitors and make said first dielectric layer and said first mask layer at the same level; removing said first mask layer; conformably forming a second mask layer on the substrate; performing an ion implantation twice at tilt angles on said second mask layer to define an undoped area between said two trench capacitors, wherein said ion implantation is performed twice at different tilt angles relative to the substrate, thereby the distances to said two trench capacitors from the undoped area are different; and removing said undoped area of said second mask layer so that part of the substrate is exposed to serve as the predetermined location of the transistor gate.