Patent ID: 7742350

Claim:
A semiconductor device comprising: a RAM macro including a memory block having a plurality of memory cells accessible from a plurality of ports, a first word line control circuit for activating a word line of a first port in the plurality of ports in accordance with a first word line control signal, a first precharge control circuit for precharging a bit line of the first port, a second word line control circuit for activating a word line of a second port in the plurality of ports in accordance with a second word line control signal, and a second precharge control circuit for precharging a bit line of the second port; and a test circuit including a test setting circuit generating first and second port setting signals in response to a test mode signal, each of the first and second port setting signals being indicative of a selected state of an associated one of the first and second port, and first and second selecting circuits each supplying one of a clock signal to an associated one of the first and second word line control circuits in response to an associated one of first and second port setting signals, wherein each of the first and second word line control circuits activates an associated one of the first and second word lines in response to the clock signal when an associated one of the first and second ports is the selected state based on the associated one of the first and second port setting signals, and activates the associated one of the first and second word lines irrespective of the clock signal when the associated one of the first and second port is not the selected state based on the associated one of the first and second port setting signals, each of the first and second precharge control circuit precharges the bit line of the associated one of first and second ports when the associated one of the first and second port is not the selected state.