Patent ID: 8625350

Claim:
A non-volatile memory cell comprising: a floating gate; a coupling device formed in a first conductivity region; a first select transistor serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region of a second conductivity type, wherein the second conductivity region is a well and the first floating gate transistor is located between the first select transistor and the second select transistor; a second floating gate transistor device formed in a third conductivity region of a first conductivity type; a control line electrically connected to the coupling device; a word line electrically connected to a gate of the first select transistor; a select gate electrically connected to a gate of the second select transistor; an erase line electrically connected to diffusion regions of the second floating gate transistor device; a bit line electrically connected to a drain region of the second select transistor; and a source line electrically connected to a source region of the first select transistor; wherein the floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor device.