Patent ID: 7719311

Claim:
An integrated circuit having a plurality of logic cells, each of said plurality of logic cells comprising: a first input terminal (wlutin), a second input terminal (tsel), a third input terminal (lutin), a plurality of fourth input terminals (ta 0 , ta 1 , ta 2 , ta 3 ), a first output terminal (wlutout) and a second output terminal (lutout); a LUT ( 1702 ) having a plurality of LUT input terminals, which are connected respectively to the plurality of fourth input terminals; and, a LUT output terminal; a first multiplexer ( 1707 ) having a first multiplexer input terminal, a second multiplexer input terminal, a multiplexer select terminal and an multiplexer output terminal; wherein, the first multiplexer input terminal of the first multiplexer is connected to the first input terminal, the second multiplexer input terminal of the first multiplexer is connected to the third input terminal, and the multiplexer select terminal may be programmed to let the first multiplexer pass on either of two signals appearing at the first multiplexer input terminal and the second multiplexer input terminal of the first multiplexer; a second multiplexer ( 1704 ) having a first multiplexer input terminal, a second multiplexer input terminal, a multiplexer select terminal and an multiplexer output terminal; wherein, the first multiplexer input terminal of the second multiplexer is connected to the multiplexer output terminal of the first multiplexer, the second multiplexer input terminal of the second multiplexer is connected to the LUT output terminal, the multiplexer select terminal of the second multiplexer is connected to the second input terminal and the multiplexer output terminal of the second multiplexer is connected to the first output terminal (wlutout); a circuit ( 1703 ) having a first circuit input terminal, a second circuit input terminal, and a circuit output terminal; wherein, the first circuit input terminal is connected to the LUT output terminal, the second circuit input terminal is connected to the third input terminal; a third multiplexer ( 1706 ) having a first multiplexer input terminal, a second multiplexer input terminal, a third multiplexer input terminal, a multiplexer select terminal, and a multiplexer output terminal; wherein, the first multiplexer input terminal of the third multiplexer is connected to the LUT output terminal, the second multiplexer input terminal of the third multiplexer is connected to the multiplexer output terminal of the second multiplexer, the third multiplexer input terminal of the third multiplexer is connected to the circuit output terminal of the circuit, and the multiplexer select terminal may be programmed to pass on any one of the signals appearing at the first, second and third multiplexer input terminals of the third multiplexer.