Patent ID: 8020956

Claim:
An element substrate comprising: a plurality of printing elements; a print signal input terminal inputting a print signal; a clock signal input terminal inputting a clock signal for transferring the print signal; a drive signal input terminal inputting a drive signal for controlling driving of the printing elements; a latch signal input terminal inputting a latch signal for latching the print signal in a latch circuit; a logic circuit controlling driving of the printing elements in accordance with the drive signal; a logic power source input terminal allowing inputting a voltage to be applied to the logic circuit; an NMOS transistor having a drain connected to the logic power source input terminal via a resistor, a source connected to a ground, and a gate receiving a signal based on voltages supplied from the print signal input terminal, the clock signal input terminal, the latch signal input terminal, and the drive signal input terminals; a connection status output circuit configured to output a signal in accordance with a connection status of the logic power source input terminal, or a connection status of each of the print signal input terminal, the clock signal input terminal, the latch signal input terminal, and the drive signal input terminals, based on the output of the NMOS transistor; and a connection status output terminal configured to supply the signal output by the connection status output circuit to outside of the substrate, wherein the signal output via the connection status output terminal is outputted by undergoing voltage division between the logic power source input terminal and the drain and between the drain and the source, and wherein the signal is outputted in accordance with a level of the signal supplied to the gate, and is either a signal having a first level based on a voltage applied to the logic power source input terminal, or a signal having a second level based on the voltages inputted to the signal input terminals.