Patent ID: 7379361

Claim:
A repairable fully-buffered memory module comprising: a substrate having wiring traces formed thereon for conducting signals; contact pads along a lower edge of the substrate, the contact pads for mating with a memory module socket on a motherboard; a buffer chip mounted to the substrate; a packet interface, in the buffer chip, for receiving serial packets from the motherboard through the contact pads, and for generating serial packets for transmission through the contact pads to the motherboard; a memory controller, in the buffer chip, for generating address, data, and control signals to the memory chips in response to the serial packets received from the motherboard; memory chips mounted to the substrate, the memory chips having address, data, and control inputs that are isolated from the contact pads by the buffer chip; a repair address buffer for storing repair addresses of faulty memory locations in the memory chips; a spare repair memory for storing data, the spare repair memory being unused when the memory chips contain no defects; and a repair controller, coupled to the memory controller, for comparing addresses to the repair addresses in the repair address buffer and for accessing the spare repair memory rather than the memory chips for addresses that match the repair addresses; whereby the spare repair memory is accessed for repair addresses on the repairable fully-buffered memory module.