Patent ID: 6876025

Claim:
A memory cell, comprising: a substrate formed with a substantially rectangular trench hole defining a lower region and an upper region, and a horizontal bit line extending in a bit line direction; a trench capacitor formed at said lower region of said trench hole, said trench capacitor having: an inner capacitor electrode formed within said trench hole, an outer capacitor electrode formed outside said trench hole; and a dielectric layer between said inner capacitor electrode and said outer capacitor electrode; a vertical selection transistor formed at said upper region of said trench hole, said selection transistor having: a first source/drain electrode connected to said inner capacitor electrode of said trench capacitor; a second source/drain electrode connected to said horizontal bit line; and a vertically running channel region between said first source/drain electrode and said second source/drain electrode; a horizontally running word line with gate region laterally adjoining said channel region, partially or completely enclosing said channel region, and being electrically insulated therefrom, said horizontally running word line with gate region being formed perpendicular to said bit line running horizontally thereabove, and an extent of said trench hole in a word line direction being at least 1.5 times as large as an extent of the trench hole in the bit line direction; said vertically running channel region of said selection transistor extending through said horizontally running word line with gate region to said bit line above said channel region.