Patent ID: 8051277

Claim:
A data processor, comprising: an input register file; an internal register bus coupled to the input register file; a plurality of programmable logic blocks (PLBs) coupled to the internal register bus; and an output register file blocks coupled to the internal register bus, wherein the internal register bus includes an instruction thread portion and a carry history portion, a plurality of PLBs, wherein each PLB includes: an accumulator, selectively coupled to the internal register bus; a secondary source, selectively coupled to the internal register bus; a carry history register selectively coupled to the carry history portion; an instruction selector coupled to the instruction thread portion; an instruction storage selectively coupled to the instruction selector; an arithmetic logic unit, a selected instruction bus coupled to the accumulator, the secondary source, the carry history register, and the arithmetic logic unit, one of a plurality of two-to-one multiplexers or a data distributor, coupled to the internal register bus, the selected instruction bus, and the accumulator, and a carry output coupled to the arithmetic logic unit, the one of a plurality of two-to-one multiplexers or a data distributor, and a carry history register.