Patent ID: 7733628

Claim:
A multilayer chip capacitor comprising: a capacitor body having a plurality of dielectric layers deposited therein and having a parallelepiped shape; at least three pairs of first and second external electrodes formed on two longer sides, the first and second external electrodes in each of the pairs having different polarities and opposing each other, and the first and second external electrodes on each of the longer sides arranged alternately with each other; and a plurality of first and second internal electrodes arranged alternately to interpose each of the dielectric layers, the first and second internal electrodes connected to the first and second external electrodes by leads, respectively, wherein the capacitor body has a length that is at least 1.1 mm and up to 1.6 mm and the capacitor body has a width that is at least 0.2 mm and up to 0.5 mm, so that the capacitor body has a length that is at least 3 times and up to 7 times a width thereof.