Patent ID: 8723580

Claim:
A signal processing circuit, comprising: a signal selection module, configured to select one from a plurality of input signals for outputting at least one first output signal; a voltage offset module, configured to output an offset voltage; and an amplifier module, coupled to the signal selection module and the voltage offset module, configured to sample the first output signal from the signal selection module, and offset the first output signal according to the offset voltage output from the offset voltage module, and perform an amplification gain control and data buffering processes on the offset signal; wherein the amplifier module comprises: an amplifier, comprising a first input port, a second input port, and an output port for output; an input voltage sampling capacitor, coupled between the signal selection module and the first input port of the amplifier, wherein the input voltage sampling capacitor is a variable capacitor; and a feedback amplification capacitor, coupled between the first input port and the output port of the amplifier, wherein the signal processing circuit is configured to operate in a sampling stage and a holding stage, and when the signal processing circuit is in the sampling stage, the input voltage sampling capacitor and the feedback amplification capacitor are configured to amplify the first output signal, and when the signal processing circuit is in the holding stage, the input voltage sampling capacitor is configured to sample the first output signal, and the feedback amplification capacitor is in a reset status.