Patent ID: 8354717

Claim:
An LDMOS transistor, comprising: a p-type substrate having a surface; an n-well implanted in the substrate, the n-well having a first surface area on the surface; a gate; a source including a p-doped p-body implanted in the n-well, the p-body having a second surface area on the surface, the p-body extending below the gate, a p-doped p+ region implanted in the p-body, a first n-doped n+ region implanted in the p-body and abutting the p+ region, the n+ region being on a side of the p+ region closer to the gate; and a drain including an n-doped shallow drain region implanted in the n-well, the shallow drain region having a third surface area on the surface, the shallow drain region being spaced a first predetermined non-zero distance from the p-body as measured along the surface of the substrate, and a second n-doped n+ region implanted in the shallow drain region.