Patent ID: 7424078

Claim:
A synchronous compensator comprising: a detector for detecting a specific word to output a detection signal; a first counter loaded with data supplied for incrementing in response to the detection signal and outputting a carry signal; a second counter for incrementing according to the carry signal; a sync timing generator for generating a sync timing signal according to outputs supplied from said first and second counters; a sync compensation circuit for generating an enable signal associated with a compensation range on a basis of the output from said first counter and a value of a range to enable; and a load generator for generating a loading signal for loading said first counter with the data on the basis of the enable signal and the detection signal, said sync compensation circuit comprising: a storage for storing a value indicating the compensation range to enable; an enable generator for setting the compensation range on the basis of the value supplied, predicting a timing, when the detection signal is supplied next, to generate the enable signal, and generating the enable signal for a sync compensation associated with the compensation range having a central position thereof set to a predicted position for the output from said first counter; and a data generator for defining an amount of correction performed at a time, said data generator comprising: an inverter for inverting output signals from said enable generator; an enable counter for counting inverted output signals to output a count value; a corrected value generator for generating a relative correction value associated with the compensation range on the basis of the count value from said enable counter; and an adder for adding a fixed value to the generated relative correction value.