Patent ID: 7388255

Claim:
A semiconductor device comprising: a semiconductor substrate; a separation region disposed in the semiconductor substrate, wherein the separation region is separated from other parts of the semiconductor substrate; an embedded layer having a first conductive type, wherein the embedded layer is disposed on a bottom portion of the separation region, and wherein the embedded layer has an electric potential in a floating state; a channel forming region having a second conductive type, wherein the channel forming region is disposed on a surface portion of the separation region on a principal surface of the semiconductor substrate; a source region having the first conductive type, wherein the source region is disposed on a surface portion of the channel forming region; a drain region having the first conductive type, wherein the drain region is disposed on another surface portion of the separation region on the principal surface of the semiconductor substrate, and wherein the drain region is separated from the channel forming region; a first electrode for applying a source voltage to the source region; a second electrode for applying the source voltage to the channel forming region; a third electrode for applying a drain voltage to the drain region; a trench disposed on the principal surface of the semiconductor substrate, wherein the trench penetrates the channel forming region between the source region and the drain region, and wherein the trench is deeper than the channel forming region; a trench gate electrode disposed on an inner surface of the trench through a gate insulation film; an offset layer having the first conductive type, wherein the offset layer is disposed on a portion of the separation region to be a current path provided by the trench gate electrode between the channel forming region and the drain region, and wherein the portion is further another surface portion of the separation region on the principal surface of the semiconductor substrate; and an electric field relaxation layer having the second conductive type, wherein the electric field relaxation layer is disposed under the channel forming region and the offset layer in the separation region, and wherein the electric field relaxation layer is deeper than the trench, is connected to the channel forming region, and covers a bottom of the trench.