Patent ID: 8489787

Claim:
A method comprising: assigning each of a plurality of sampled instruction address registers to a particular thread running for an application on the plurality of processor cores; configuring each of the plurality of sampled instruction address registers by storing, in each of the plurality of sampled instruction address registers, a thread identification of the particular thread in a thread identification field and a processor identification of the particular thread in a processer identification field; setting, by a counter, a bit in a trigger status register corresponding to a particular thread identification and to a particular processor identification of the particular thread in response to the counter identifying an event requiring an interruption of the particular thread on a particular processor core; interrupting, by an interrupt signal, the particular thread in response to the counter setting the bit in the trigger status register; freezing, by a first signal on an interrupt channel, a sampled instruction address register having the particular thread identification field and the particular processor identification field in response to the counter setting the bit in the trigger status register; recording, by an interrupt handler, a sampled instruction corresponding to the particular thread that was interrupted in response to an interrupt handler executing on the particular thread; clearing the bit in the trigger status register by the interrupt handler in response to the interrupt handler recording the sample instruction; and unfreezing, via a second signal on the interrupt channel, the sampled instruction address register having the particular thread identification field and the particular processor identification field corresponding to the particular thread on the particular processor core that the cleared trigger status register bit represents in response to the interrupt handler clearing the bit in the trigger status register.