Patent ID: 6873932

Claim:
A method of predicting the lifetime of a semiconductor device at a predetermined operating condition, said method comprising: (a) performing a hot carrier injection (HCI) accelerated stress test on a plurality of MOS transistors; (b) for each HCI test, determining (i) a HCI lifetime τ and (ii) at least one of a maximum substrate current I submax and a maximum gate current I gmax at which the transistor is stressed; (c) fitting data from the HCI tests with a hot carrier lifetime model of the form of at least one of: τ =A /( I submax ) m , and τ= A /( I gmax ) m , where A and m are fitting parameters; (d) obtaining A and m from the fitting step; (e) performing a wafer level test on at least 10 N MOS transistors, where N is an integer greater than 2, in which at least one of (i) I submax and (ii) I gmax is determined for each of the at least 10 N MOS transistors, yielding a statistical distribution of one of (i) I submax values and (ii) I gmax values; (f) determining a median lifetime to failure τ 50% for the statistical distribution of at least one of (i)) I submax values and (ii) I gmax values at the predetermined operating condition, yielding a statistical distribution of τ 50% values; and (g) from the determined median lifetime to failure τ 50% , calculating a projected lifetime at (10 −(N−2) )% cumulative failure τ (10 −(N−2) )% corresponding to the predetermined operating condition.