Patent ID: 8164504

Claim:
A successive approximation register analog digital converter (SAR ADC), comprising: a first conversion unit including a correction capacitor array and a bit capacitor array 2 N-1 less than the number of bits; a second conversion unit configured to differentially operate with the first conversion unit; a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units; a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal; and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal, wherein after an input analog signal is sampled, outputs of the first and second conversion units are connected to input terminals of the comparator to determine a digital value corresponding to the most significant bit (MSB) according to the output voltage of the comparator.