Patent ID: 8722500

Claim:
A method for fabricating an integrated circuit comprising: processing of the integrated circuit in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts; depositing an etch resistant layer and a fill layer overlying the dummy gates and the metal silicide contacts; planarizing the fill layer and exposing a top portion of the dummy gates; removing the dummy gates overlying channel regions; depositing and patterning a mask layer to provide a mask opening overlying a portion of a channel region and a portion of an adjacent metal silicide contact; etching the fill layer, etch resistant layer and a portion of the sidewall spacers exposed through the mask opening to expose a portion overlying the adjacent metal silicide contact; depositing a gate electrode material overlying the channel region and the exposed portion overlying the adjacent metal silicide contact; and planarizing the gate electrode material to form a gate electrode and a gate-to-metal silicide contact interconnect.