Patent ID: 8261173

Claim:
An apparatus comprising: a first circuit to compute a first metric at a second cycle (M 0 (k+1)) by taking a first minimum of (1) a sum of a first metric at a first cycle (M 0 (k)), a multiple of an incoming signal (y(k)) and a multiple of an amplitude of the incoming signal, and (2) a sum of a second metric at a first cycle (M 1 (k)), the incoming signal and the amplitude of the incoming signal; a second circuit to compute the second metric at a second cycle (M 1 (k+1)) by taking a second minimum of (1) a sum of a third metric at the first cycle (M 3 (k)), and (2) a sum of a fourth metric at a first cycle (M 3 (k)) and the amplitude of the incoming signal subtracting the incoming signal; a third circuit to compute the third metric at a second cycle (M 2 (k+1)) by taking a third minimum of (1) a sum of the first metric at the first cycle (M 0 (k)), the incoming signal and the amplitude, and (2) the second metric at the first cycle (M 1 (k)); a fourth circuit to compute a fourth metric at a second cycle (M 3 (k+1)) by taking a fourth minimum of (1) a sum of the first metric at the first cycle (M 0 (k)), the incoming signal (y(k)) and the amplitude of the incoming signal, and (2) a sum of a fourth metric at a first cycle (M 3 (k)) and a multiple of the amplitude of the incoming signal subtracting a multiple of the incoming signal; and a substractor to substract an average of the first metric, the second metric, the third metric and the fourth metric at the first cycle.