Patent ID: 7937558

Claim:
A system, comprising: i. a plurality of processors, each comprising at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports; and ii. a plurality of dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine; iii. wherein said plurality of processors and said plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement, wherein said plurality of dynamically configurable communication elements are distinct from said plurality of processors; iv. wherein, for each of said processors, said plurality of processor ports are configured for coupling to a first subset of said plurality of dynamically configurable communication elements; v. wherein, for each of said dynamically configurable communication elements, said plurality of communication ports comprise a first subset of communication ports configured for coupling to a subset of said plurality of said processors and a second subset of communication ports configured for coupling to a second subset of said plurality of dynamically configurable communication elements; vi. wherein at least one of said processors is configured to obtain data from two or more of said dynamically configurable communication elements simultaneously.