Patent ID: 8022485

Claim:
A semiconductor device comprising: a pedestal comprising: a first dielectric stack comprising at least three dielectric layers, the first dielectric stack having a sidewall and a major surface; a conductive shield layer between two of the at least three dielectric layers of the first dielectric stack; a second dielectric stack comprising at least two dielectric layers, the second dielectric stack overlying a sidewall of the first dielectric stack where the second dielectric stack has a major surface; and a polysilicon layer overlying the major surface of the second dielectric stack and the major surface of the first dielectric stack; wherein the pedestal further comprises a lower k dielectric region having a dielectric constant less than about 2 wherein the lower k dielectric region is between the polysilicon layer overlying the major surface of the pedestal and the conductive shield layer to reduce input capacitance of the device.