Patent ID: 7031192

Claim:
A non-volatile semiconductor memory, comprising: a) an array of non-volatile MONOS (metal-oxide-nitride-oxide-semiconductor) memory cells, b) a control gate decoder coupled to control gates of said memory cells, c) a word line decoder coupled to word lines of said memory array, d) a bit line decoder coupled to bit lines of said memory array, e) a data control unit coupled to said bit line decoder, f) an input/output (I/O) interface unit coupled to a plurality of I/O data lines from the data control unit, g) a chip control unit controlling said control gate decoder, the word line decoder, the bit line decoder, the data control unit and the I/O interface unit, h) said data control unit containing a plurality of sub-units serially coupled together and coupling a verify signal, starting with a first sub-unit coupled to a second sub-unit and ending with said chip control unit coupled to a last sub-unit whereby a program and erase verify signal is coupled to said chip control unit indicating program and erase operations completed, i) each said sub-unit providing an inhibit voltage to the bit line coupled to said each sub-unit to prevent further current from flowing to said memory cell connected to the bit line upon completion of program and erase operation on said memory cell.