Patent ID: 8086889

Claim:
A semiconductor integrated circuit device comprising: a first flip-flop on a first scan chain path disposed in a first region; a second flip-flop disposed on a second scan chain path disposed in a second region which does not overlap with the first region; a first clock tree for distributing a clock to the first flip-flop; a second clock tree for distributing a clock to the second flip-flop; a gate circuit; and a test clock generator for distributing generated test clocks to the first clock tree and the second clock tree via the gate circuit, wherein the gate circuit independently shuts off inputs of the test clocks to the first clock tree and the second clock tree; the semiconductor integrated circuit device further comprising: a first test pattern generator; a second test pattern generator; a first multiple input signature register; and a second multiple input signature register, wherein the first test pattern generator generates first test data and inputs the first test data to the first flip-flop through the first scan chain path in scan-in, the second test pattern generator generates second test data and inputs the second test data to the second flip-flop through the second scan chain path in the scan-in, the first multiple input signature register reads data from the first flip-flop through the first scan chain path in scan-out, and the second multiple input signature register reads data from the second flip-flop through the second scan chain path in the scan-out.