Patent ID: 7705410

Claim:
A logical inverter circuit comprising: a first resistance means, a second resistance means and a third resistance means connected in series with each other, each comprising a first contact portion and a second contact portion, wherein said second resistance means is arranged between said first resistance means and said third resistance means, said first contact portion of said first resistance means is arranged to receive a first potential, and said second contact portion of said first resistance means is arranged electrically between said first resistance means and said second resistance means, and said first contact portion of said third resistance means is arranged electrically between said third resistance means and said second resistance means and said second contact portion of said third resistance means is arranged to receive a second potential, which is lower than said first potential; a depletion mode transistor having JFET characteristics, comprising a source, a drain and a gate, wherein said drain is connected to a contact portion arranged electrically between said second and third resistance means; output means comprising a first and a second terminal; wherein said source of said transistor and said second terminal of said output means are electrically connected to each other and arranged to receive a third potential, which is higher than said second potential and lower than said first potential, said source and said gate are arranged to receive a potential difference corresponding to a logical input, and said second terminal of said output means is connected to a contact portion arranged electrically between said first resistance means and said second resistance means, such that a potential difference between said first and second terminals of said output means, equaling an inverting-operation of said logical input, is provided.