Patent ID: 8347176

Claim:
An information-processing apparatus comprising: a first memory controller comprising: a memory-chip interface that outputs a stream of processor memory requests to a plurality of memory chips, wherein the stream of processor memory requests includes a plurality of read requests and a plurality of write requests, wherein each of the stream of processor requests specifies a memory address that is sent in a plurality of portions to at least one of the plurality of memory chips, including a row-address portion that specifies a selected row and a column-address portion that specifies one or more selected column locations within the selected row; and a refresh controller, coupled to the memory-chip interface, and configured to insert read-refresh requests into the stream of processor requests, wherein the read-refresh requests use refresh addresses that cycle through address-bit combinations for the row-address portion to access all rows of the at least one of the plurality of memory chips within a refresh-rate requirement of the plurality of memory chips, and to also cycle through the address-bit combinations for the column-address portion to access all columns in each row, and wherein read-refresh result data is fetched to the memory-chip interface as a result of each of the read-refresh requests such that read-refresh result data is fetched from every data location in the plurality of memory chips at intervals using the read-refresh requests.