Patent ID: 7493479

Claim:
A data processing device for a multiple instruction-set processor, the data processing device comprising: an instruction execution device configured to execute a first instruction set as specific instructions and perform pipeline processing with a first pipeline comprising first plural stages; and an instruction conversion circuit configured to convert second instructions of a second instruction set into a first instruction string of the first instruction set, and to supply the first instruction string to the instruction execution device, the first instruction string including one or more first instructions, wherein the instruction execution device comprises a pipeline control device configured to control a stall of the first pipeline and a cancellation of remaining instructions on the first pipeline at branch time using signals, wherein the instruction conversion circuit comprises a counter device and a second pipeline comprising second plural stages and each of the second plural stages corresponds each of the first plural stages, wherein the second pipeline is configured to be controlled by the pipeline control device using signals used to control the first pipeline and to perform the same pipeline processing as the pipeline processing of the first pipeline, and wherein the counter device decrements a count value when a flag synchronous with one instruction of the first instruction string is inputted into the second pipeline and arrives in one stage of the second plural stages, wherein the first plural stages have an instruction decode stage, an instruction execution stage, a memory access stage, and a writeback stage, wherein the second plural stages have a simulated instruction decode stage corresponding to the instruction decode stage, a simulated instruction execution stage corresponding to the instruction execution stage, a simulated memory access stage corresponding to the memory access stage, and a simulated writeback stage corresponding to the writeback stage, and wherein first hardware includes the first pipeline, second hardware includes the second pipeline, and the first hardware and the second hardware separate from each other.