Patent ID: 8248284

Claim:
An analog-digital converter (ADC) comprising: a correlated double sampling (CDS) circuit configured to perform CDS on each of a reset signal and an image signal output from a pixel to generate a correlated double sampled reset signal and a correlated double sampled image signal, respectively; and a delta sigma (ΔΣ) ADC configured to output a difference between a first digital code generated by performing ΔΣ analog-digital conversion on the correlated double sampled reset signal and a second digital code generated by performing ΔΣ analog-digital conversion on the correlated double sampled image signal, wherein the ΔΣ ADC is configured to generate the first digital code such that the first digital code sequentially increases from an initial value during a reset phase, to generate the second digital code such that the second digital code sequentially increases from the initial value during a signal phase, and to output a difference between the first digital code and the second digital code.