Patent ID: 8786092

Claim:
A semiconductor integrated circuit device, comprising: a rectangular shaped semiconductor substrate including an active region in which one or more circuits are formed; a metal wiring layer formed on or over the semiconductor substrate, wherein the semiconductor substrate is a silicon substrate; and a passivation layer covering the metal wiring layer, four corner non-wiring regions provided, respectively, at each of four corners of the semiconductor integrated circuit device, where no portion of the metal wiring layer is formed on the four corner non-wiring regions; wherein the passivation layer has a step in its upper surface at a seam between a portion thereof under which the metal wiring layer is present and a portion thereof under which the metal wiring layer is absent, and each of the corner non-wiring regions is a triangular region enclosed by a first line connecting the corner of the semiconductor integrated circuit device and a first point located on an edge extending from the corner, a second line connecting the corner and a second point located on another edge extending from the corner, and a third line connecting the first point and the second point, with no portion of the metal wiring layer inside the triangular region.