Patent ID: 8810292

Claim:
A PLL circuit, comprising: a phase comparator to detect a phase difference between a reference signal and a feedback signal; first and second charge pumps each to output a current according to a detection result of the phase comparator; a filter to output a first current obtained by removing a high frequency component of the output current of the first charge pump; an integrator to integrate the output current of the second charge pump; a voltage-current conversion circuit to output a second current according to an integrated result of the integrator; an oscillator to generate an oscillating signal of a frequency according to a third current generated by adding the first and the second currents, and to feed it back to the phase comparator, and an adder that adds the first and the second currents to output the third current, wherein the adder includes: a first transistor whose source is coupled to a first power supply, and whose drain and gate are coupled to a first node to which the first and the second currents are supplied; a second transistor whose source is coupled to the first power supply, whose gate is coupled to the first node, and whose drain is coupled to the oscillator; a third transistor that is provided between a drain of the first transistor and the first node, and whose gate is supplied with a bias voltage; and a fourth transistor that is provided between a drain of the second transistor and the oscillator, and whose gate is supplied with the bias voltage.