Patent ID: 8855961

Claim:
A computer implemented system for conducting testing of electronic devices, including: a nontransitory computer readable storage medium storing a plurality of machine readable processing sequences, said plurality of processing sequences comprising: a first processing sequence that receives a first data structure, the first data structure being the result of execution of a first test protocol configured to test any species of electronic device within a genus of electronic devices; the first data structure being generic with respect to species within the genus of electronic devices; a second processing sequence that extracts data from the first data structure; a third processing sequence that generates a second data structure specific to a first electronic device species using data extracted from the first data structure; a fourth processing sequence that outputs the second data structure to a first device of the first electronic device species; a fifth processing sequence that receives a third data structure from the first device of the first electronic device species; the third data structure being specific to the first electronic device species; a sixth processing sequence that extracts data from the third data structure; and a seventh processing sequence that generates a fourth data structure that is based off the third data structure, the fourth data structure being generic with respect to species of electronic devices within the genus of electronic devices.