Patent ID: 7262444

Claim:
A power semiconductor chip packaging structure, comprising at least one power semiconductor chip having an active surface and an opposing back surface in which the back surface is electrically coupled to a power module substrate to form a power module and in which the power module substrate comprises an insulating substrate having at least one electrically conductive contact to which the power semiconductor chip is electrically coupled, the chip having one or more contact pads on the active surface; a dielectric film adjacent to the power semiconductor chip, the dielectric film having one or more through holes aligned with the one or more contact pads; a patterned electrically conductive layer adjacent to the dielectric film, the conductive layer having one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads; and one or more air gaps between the dielectric film and the active surface of the at least one power semiconductor chip.