Patent ID: 7954023

Claim:
A semiconductor integrated circuit comprising: a first power domain including a first functional block having a first flip-flop, a second flip-flop, and a first combination logic; a second functional block having a third flip-flop, a fourth flip-flop, and a second combination logic; a first scan chain including the first flip-flop and the second flip-flop; and a second scan chain including the third flip-flop and the fourth flip-flop, wherein the semiconductor integrated circuit is configured to be set to one of a first mode, a second mode, and a third mode, and wherein the first mode cuts off power to be supplied to the first power domain, wherein the second mode inputs a first vector, which is independent of a previous-stage circuit of the first flip-flop and a previous-stage circuit of the second flip-flop, to the first combination logic via the first scan chain, and subsequently cuts off a first clock signal to be supplied to the first functional block, and wherein the third mode only cuts off the first clock signal.