Patent ID: 8117508

Claim:
A non-volatile memory device comprising: a memory cell array with memory cells arranged therein, each memory cell storing an electrically rewritable resistance value as data in a non-volatile manner; a first cache circuit configured to hold program data to be programmed in the memory cell array; a second cache circuit configured to hold preprogrammed data read from an area of the memory cell array, where the program data is to be programmed; and a judging circuit configured to compare and check data state bits of a first logic state in the program data loaded in the first cache circuit with corresponding bits in the preprogrammed data read in the second cache circuit, compare and check data state bits of a second logic state in the program data loaded in the first cache circuit with corresponding bits in the preprogrammed data read in the second cache circuit, and judge whether there are one or more disagreement bits therebetween or not with respect to the first logic state bits and the second logic state bits in the program data respectively; a fail bit counting circuit configured to count the disagreement bits detected in the judging circuit, and compare the disagreement bit number with a permissible value to output the compared result with respect to the first logic state bits and the second logic state bits in the program data respectively.