Patent ID: 8533430

Claim:
A computer system comprising: a processor; a memory control coupled to the processor; a memory coupled to the memory control, the memory further comprising one or more groups, each group further comprising one or more banks; a first memory portion resident in the memory; and an application executing in the processor; wherein the application provides the memory control with information, prior to writing a first data element in the first memory portion, about the first memory portion in the memory, including an intended stride for data elements in the first memory portion, the memory control using the intended stride when writing the data elements at a first stride, the first stride not the same as the intended stride, to distribute the data elements among the one or more groups and the one or more banks in the one or more groups in the first memory portion in such a way that a subsequent strided access at the intended stride does not consecutively access a particular bank in a particular group; and wherein the first memory portion comprises more than one data element; and wherein a subsequent access, at the first stride, of the data elements written to the first memory portion does not consecutively access a particular bank in a particular group; and wherein reordering of accesses is not performed.