Patent ID: 7216249

Claim:
A clock generation system for generating at least a first frequency clock having a first frequency, a second frequency clock having second frequency, and a third-frequency clock having a third frequency, said clock generation system comprising: a first PLL circuit supplied with said first-frequency clock as a reference clock and adapted to generate an intermediate-frequency clock having an intermediate frequency having a predetermined first ratio to said reference frequency; a second PLL circuit supplied with said intermediate-frequency clock and adapted to generate said second-frequency clock, with said second frequency having a predetermined second ratio to said intermediate frequency; and a third PLL circuit supplied with said intermediate-frequency clock and adapted to generate said third-frequency clock, with said third frequency having a predetermined third ratio to said intermediate frequency, wherein said second-frequency clock is obtained by frequency dividing the clock outputted from said second PLL circuit; and said third-frequency clock is obtained by frequency dividing the clock outputted from said third PLL circuit, and wherein the frequencies of said first-, second-, and third-frequency clocks are 27 MHz, 33.8688 MHz, and 36.864 MHz, respectively.