Patent ID: 7180935

Claim:
An electronic system for compensating for delay time fluctuations, comprising: a first module comprising a memory device in which at least some bits of the data transmitted from the first module to a further module are stored; a connecting line, wherein the data is transmitted from the first module to the further module via the connecting line; and a reference signal line via which a reference signal is transmitted from the further module to the first module, wherein the reference signal is selected as a function of a timing of the data received by the further module via the connecting line from the first module, with respect to a clock signal received by the further module, and wherein the reference signal has a bit sequence corresponding to a bit sequence received by the further module via the connecting line from the first module wherein the transmission of the data by the first module is altered as a function of the reference signal received by the first module, the alteration being one of delaying and speeding up of the data transmission, and wherein an extent of the alteration of the transmission of data is determined based on a comparison of the bits stored in the memory device in the first module with the bit sequence of the reference signal transmitted by the further module to the first module.