Patent ID: 7743355

Claim:
A method of achieving timing convergence in an overall design of one of a digital integrated circuit and a functional unit of a digital integrated circuit comprising the steps of: automatically partitioning the overall design of one of the digital integrated circuit and the functional unit of a digital integrated circuit into macros; apportioning a timing and area budget to each of said macros; creating a reformulated objective function for optimization of timing characteristics of one or more of said macros, the objective function for each of said one or more of said macros having contributions from a plurality of primary output signals in said macro and being dependent on both sub-critical paths and critical paths within said macro, wherein the objective function is formulated as follows: Σ i=1 n f (−slack i )=Σ i=1 n f (−( RAT i −AT i −desired_slack)); wherein f is a penalty function, slack i is an effective slack of an i th output of the macro, with slack defined as the algebraic difference between a required arrival time (RAT) and an actual arrival time (AT), and wherein desired_slack represents a user defined additional slack; improving the timing characteristics of each of said one or more of said macros by attempting to minimize said objective function timing the overall design; and re-apportioning the timing and area budgets and repeating the improving and timing steps until timing closure is achieved.