Patent ID: 8890958

Claim:
A supervisor circuit for verifying portions of information to be displayed, comprising: a synchronizer that is arranged to receive timing information from one or more video signals that include frame data generated by a display controller for driving a display and to generate synchronization signals in response to the received timing information; a region indicator that is arranged to, in response to the generated synchronization signals, indicate when the one or more video signals is transmitting a portion of the frame data of a test region of a frame; a frame data capture unit that is arranged to, in response to one or more indications from the region indicator, capture the portion of the frame data of the test region of the frame; and a diagnostic unit that is arranged to compare a representation of the captured portion of the frame data of the test region of the frame with a representation of a commanded portion of the frame data of the test region of the frame, wherein the synchronizer includes: a pixel clock generator to generate a pixel clock from the received timing information.