Patent ID: 8921942

Claim:
A method for producing a stacked electrostatic discharge (ESD) clamp, comprising: providing a semiconductor substrate of a first conductivity type and having an upper surface; forming at least a first transistor having a first conductivity type first well region extending a first distance into the substrate from the first surface, the first well region having a first lateral edge forming a portion of a base of the first transistor; forming at least a second transistor having a first conductivity type second well region extending a first distance into the substrate from the first surface, the second well region having a second lateral edge forming a portion of a base of the second transistor; forming in the first transistor a third well region of a second opposite conductivity type extending a third distance into the substrate from the first surface, the third well region having a third lateral edge separated from the first lateral edge by a first spacing dimension D 1 ; forming in the second transistor a fourth well region of a second opposite conductivity type extending a third distance into the substrate from the first surface, the fourth well region having a fourth lateral edge separated from the second lateral edge by a second spacing dimension D 2 ; and wherein the first transistor is serially coupled to the second transistor and D 1 is different than D 2 ; wherein the first spacing dimension D 1 is chosen from a first zone Z 1 of spacing dimensions D, the first transistor adapted to have a trigger voltage Vt 1 Z1 and a trigger voltage slope (ΔVt 1 /ΔD) Z1 at D=D 1 ; wherein the second spacing dimension D 2 is chosen from a second zone Z 2 of spacing dimensions D, the second transistor adapted to have a trigger voltage Vt 1 Z2 and a trigger voltage slope (ΔVt 1 /ΔD) Z2 D=D 2 ; and wherein (ΔVt 1 /ΔD) Z1 is at least twice (ΔVt 1 /ΔD) Z2 .