Patent ID: 7412637

Claim:
An apparatus that accepts a virtual scan pattern stored in an ATE (automatic test equipment) for generating broadcast scan pattern in a broadcaster having n broadcast scan inputs and m outputs to test a random access scan based (RAS-based) integrated circuit, where n<m, the RAS-based integrated circuit containing an m-input and m-output a RAS core organized in an array of RAS cells so that each row is randomly and uniquely addressable, the inputs to the RAS core connected to the outputs of the broadcaster, the outputs from the RAS core connected to the inputs of a compactor having m inputs and k outputs for compacting selected outputs of aid RAS core for comparison in said ATE, where k<m, said apparatus comprising: a) said broadcaster having said broadcast scan inputs that accepts virtual scan patterns via its said broadcast scan inputs for generating broadcast scan patterns as inputs to said RAS core; wherein said broadcaster comprises a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.