Patent ID: 8411705

Claim:
An adaptive clock recovery (ACR) system for a receiver, the ACR system comprising: a first closed-loop control processor that generates a reference phase signal from an input phase signal representing packet delay values corresponding to arrival times of packets at the receiver; a delay-offset estimation component, that compares the input phase signal to the reference phase signal to generate a delay-offset estimate signal representative of a phase offset for the packet arrival times relative to the reference phase signal, wherein the phase offset is one of (i) a delay-floor phase offset and (ii) an established phase offset; a delay-offset compensation component that generates a delay-offset-compensated phase signal based on the reference phase signal and the delay-offset estimate signal; and a second closed-loop control processor that generates, from the delay-offset-compensated phase signal, an output phase signal, that can be used to generate a recovered clock signal.