Patent ID: 8423940

Claim:
A computer-implemented method for noise aware routing in an integrated circuit chip design, the computer-implemented method comprising: a logic system performing an uplift timing analysis using a route-based extractor for a given routed placement of nets connecting electric circuits of an integrated circuit chip design; the logic system locating one or more affected shapes in a halfbay between a ground stripe and a power stripe based on a list of aggressor and victim nets and a proximity parameter; the logic system prioritizing the one or more affected shapes into different priorities based on one or more coupling uplift values associated with the one or more affected shapes from the uplift timing analysis and correlating, for the one or more affected shapes, timing uplift with cycle time due to noise; the logic system giving a higher priority to shapes having a higher coupling uplift value; and the logic system rearranging the affected shapes within the integrated circuit chip design according to the respective priority to create an optimized integrated circuit chip design.