Patent ID: 8570076

Claim:
A frequency divider comprising: a first local oscillating input node; a low power frequency divider coupled to the first local oscillating input node, wherein the low power frequency divider generates a first enable signal in response to a local oscillating input signal present on the first local oscillating input node; and a high speed latch coupled to the first local oscillating input node and the low power frequency divider, wherein the high speed latch generates an output signal in response to the local oscillating input signal and the first enable signal, wherein the output signal is divided in frequency from the local oscillating input signal; wherein the low power frequency divider comprises a plurality of divider transistors and the high speed latch comprises a plurality of latch transistors larger relative to the plurality of divider transistors; and further wherein approximately half of a current at the first local oscillating input node is directed to the low power frequency divider and remaining current is directed to the high speed latch.