Patent ID: 7102904

Claim:
A circuit for comparing a first match line and a second match line in a CAM circuit comprising: a first keeper circuit having a first input coupled to the second match line; a second keeper circuit having a second input coupled to the first match line; a third keeper circuit; a fourth keeper circuit; and a first NAND gate having a first NAND input coupled to the first match line and a second NAND input coupled to the second match line, wherein the first keeper circuit includes: a first PMOS device; a second PMOS device coupled in series with the first PMOS device, wherein the first input is coupled to a gate of the second PMOS device; and a second NAND gate having a third NAND input coupled to the first match line and a fourth NAND input coupled to an output of the first NAND gate, wherein the first and third keeper circuits are coupled to the first match line so as to be capable of maintaining a first voltage level on the first match line, and wherein the second and fourth keeper circuits are coupled to the second match line so as to be capable of maintaining a second voltage level on the second match line.