Patent ID: 7558147

Claim:
A semiconductor memory device, comprising: a predecoding circuit for predecoding address signals; a first main decoding circuit for decoding output signals of the predecoding circuit, thereby outputting first decoding signals to a first bank; and a second main decoding circuit for decoding output signals of the predecoding circuit, thereby outputting second decoding signals to a second bank, wherein the predecoding circuit includes: a first predecoder for decoding first address signals which correspond to a predetermined number of bits starting from a most significant bit of the address signals and for outputting the decoded signals to the first and the second main decoding circuit; and a second predecoder for decoding second address signals which are selected from rest address signals except for the first address signal of the address signals and for outputting the decoded signals to the first or the second main decoding circuit in response to a bank select signal.