Patent ID: 7417476

Claim:
A power-on reset circuit, comprising: a first circuit arranged between a high voltage supply terminal (VDD) and a low voltage supply terminal (VSS), wherein the first circuit is configured to output a low-voltage reset signal at an output node when VDD is powered up and to output a high voltage signal at the output node after the VDD reaches a predetermined voltage during power up, wherein the first circuit comprises a transistor connected between VDD and a node S 3 , an R-C circuit connected between the node S 3 and VSS, and a Schmitt trigger circuit configured to change the voltage at the output node in response to the voltage at the node S 3 ; a second circuit configured to set the output node to a low voltage after VDD is powered off; and a third circuit configured to provide a supply voltage at a node DV to the second circuit, wherein the supply voltage is lower than the voltage of VDD by approximately one diode voltage.