Patent ID: 7417330

Claim:
A semiconductor device comprising: a semiconductor substrate having an upper surface, a lower surface and a peripheral side surface intervened between the upper surface and the lower surface, and having an integrated circuit and a plurality of connection pads formed on the upper surface; a protection film which has opening portions through which the respective connection pads are exposed and is provided on the upper surface of the semiconductor substrate; a plurality of wirings which are connected with one of the connection pads and have connection pad portions each of which is formed on the protection film; a plurality of external connection electrodes provided on the connection pad portions of the wirings each of the external connection electrodes having a height of 80 to 150 μm; a first sealing film having a thermal expansion coefficient less than 20 ppm/° C. and provided on the protection film and the wirings formed on the upper surface of the semiconductor substrate around the external connection electrodes and having substantially the same height of each of the external connection electrodes, each impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the first sealing film being not greater than 10 ppm; and a second sealing film having a thermal expansion coefficient greater than 20 ppm/° C. and directly provided on at least one of the lower surface and the peripheral side surface of the semiconductor substrate with the exception of an upper surface side of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing film being not smaller than 100 ppm.