Patent ID: 8552556

Claim:
A wafer level fan out package comprising: a semiconductor die comprising: a first surface; a second surface opposed to the first surface, the second surface comprising a bond pad; and a third surface coupling the first and second surfaces to each other; a stiffener extending outward from the third surface of the semiconductor die; a conductive via passing through the stiffener, wherein the conductive via comprises a through hole; a first electrically conductive pattern coupled to the first surface of the semiconductor die and to the conductive via; a second electrically conductive pattern coupled to the second surface of the semiconductor die, the second electrically conductive pattern coupling the bond pad to the conductive via; a first passivation layer coupled to the first electrically conductive pattern and filling the through hole of the conductive via; and a second passivation layer coupled to the second electrically conductive pattern and to the first passivation layer, the second passivation layer being a different passivation layer than the first passivation layer.