Patent ID: 7193912

Claim:
A semiconductor integrated circuit device comprising: a sense amplifier provided with a CMOS latch circuit for amplifying and retaining signals of a pair of input/output nodes in response to an operation timing signal; a pair of precharge MOSFETs provided on said pair of input/output nodes, becoming in an on state during a precharge period, and supplying a precharge voltage to each of said input/output nodes; a selection switch MOSFET for connecting said pair of input/output nodes and a complementary bit-line pair in accordance with a selection signal; a first equalize MOSFET provided between said complementary bit-line pair and short-circuited during said precharge period; and a dynamic memory cell provided between one of said complementary bit-line pair and a word line intersecting therewith and including an address selection MOSFET and a storage capacitor, wherein gate insulators of said selection switch MOSFET and a first equalize MOSFET are made of first film-thickness gate insulators, a gate insulator of said precharge MOSFET is made from a second film-thickness gate insulator thinner than said first film-thickness gate insulator, a precharge signal corresponding to a power supply voltage is supplied to said precharge MOSFET, and an equalize signal and the selection signal corresponding to a boost voltage equal to or higher than said power supply voltage are supplied to said first equalize MOSFET and selection switch MOSFET, respectively.