Patent ID: 8007914

Claim:
A wafer having a two layer backside seal, comprising: a silicon wafer substrate having a first major side and second major side and a two layer backside seal comprising; a low stress LPPECVD- low temperature oxide (LTO) layer having a first major side and a second major side, the first major side of the low stress LPPECVD-LTO layer in direct contact with the first major side of the wafer substrate; and a high stress LPPECVD-LTO layer having a first major side and a second major side, the first major side of the high stress LPPECVD-LTO layer being adjacent to the second major side of the low stress LPPECVD-LTO layer; and wherein the stress in the low stress LPPECVD-LTO layer is less than 100 MPa and the stress in the high stress LPPECVD-LTO layer is less than 300 MPa and the stress in the high stress LPPECVD-LTO layer is higher than the stress in the low stress LPPECVD-LTO layer.