Patent ID: 7411256

Claim:
A semiconductor integrated circuit device, comprising: a semiconductor substrate; and a capacitor forming at least part of a memory cell and including a multi-layer structure comprising: a lower capacitance electrode; a capacitance insulating film; an upper capacitance electrode, all of which are deposited in this order, said capacitor being disposed on said semiconductor; and a well contact cell coupled to said memory cell, wherein said lower capacitance electrode comprises a node interconnect of said memory cell embedded in a trench formed in an interlayer dielectric layer provided on said semiconductor substrate, and an upper surface thereof is formed to be substantially coplanar to an upper surface of said interlayer dielectric layer, wherein said capacitance insulating film is substantially flatly formed so as to contact the upper surface of said interlayer dielectric layer containing said lower capacitance electrode, wherein said upper capacitance electrode is substantially flatly formed so as to contact an upper surface of said capacitance insulating film and across an entire region of said memory cell except a region thereof for providing an electric coupling to an upper layer interconnect, and wherein said upper capacitance electrode is extended into a partial region of said well contact cell.