Patent ID: 7046687

Claim:
A port processor configured to receive data packets from a line card, each data packet comprising a destination port address and data, the port processor comprising: a random access memory (RAM) configured to store packets from the line card; a content addressable memory (CAM) configured to store a plurality of entries, each CAM entry configured to comprise (a) a destination port address field and (b) a pointer field, wherein each CAM entry has a memory address corresponding to a memory location of the RAM; a storage unit configured to store a plurality of queue entries, each queue entry configured to comprise (a) a destination port address of a set of one or more CAM entries, (b) a header pointer field equal to a pointer field of a first CAM entry in the set, and (c) a tail pointer field equal to a pointer field of a last CAM entry in the set; and a controller configured to control the RAM, CAM and storage unit.