Patent ID: 8803561

Claim:
A semiconductor circuit comprising: an output circuit for outputting an ON driving signal as a first positive pulse during a first time period and an OFF driving signal as a second positive pulse during a second time period; a first capacitor for charging ON driven electric charges in response to said ON driving signal; a second capacitor for charging OFF driven electric charges in response to said OFF driving signal; a first signal generating circuit for generating a first trigger signal in response to said ON driving signal; a second signal generating circuit for generating a second trigger signal in response to said OFF driving signal; an ON driven electric charge discharging circuit for discharging said ON driven electric charges capacitor in response to said second trigger signal; an OFF driven electric charge discharging circuit for discharging said OFF driven electric charges of in response to said first trigger signal; a Set-Reset Flip-Flop which operates in response to said ON driven electric charges and said OFF driven electric charges which are charged thereto; and a Delay-type Flip-Flop to which an output of said Set-Reset Flip-Flop and an NOR output of said first trigger signal and said second trigger signal are inputted.