Patent ID: 8023603

Claim:
An interface circuit comprising: a shift clock generator to generate a shift clock having different cycles according to a data sequence of a data string; a data holding circuit to hold the data string and serially output the data string in response to the shift clock; a transistor to drive a bus line upon receiving an output of the data holding circuit; and a detector to detect the data sequence of the data string, wherein the shift clock generator changes a cycle of the shift clock based on a detection result of the detector, and wherein: the data string comprises a first data string of a bits (n>I) the shift clock comprises a first shift clock, the data string further comprises a second data string of n bits, the second data string being different from the first data string, the shift clock generator generates a second shift clock according to a data sequence of the second data string, a cycle of the first shift clock is different from a cycle of the second shift clock the first data string includes a specific data sequence of 2 bits, and the second data string does not include the specific data sequence.