Patent ID: 8659956

Claim:
A method of generating a reference voltage on an integrated circuit device having a memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line is associated with a plurality of memory cells, wherein each memory cell comprises an electrically floating body transistor including a body region which is electrically floating, and wherein each memory cell is programmable to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the transistor, and (ii) a second data state representative of a second charge in the body region of the transistor, the method comprising: applying a first voltage to a first group of associated bit lines; applying a second voltage to a second group of associated bit lines; and generating a reference voltage based upon the first voltage and the second voltage by electrically coupling the first group of associated bit lines and the second group of associated bit lines.