Patent ID: 7505339

Claim:
A static semiconductor memory device having a test mode, comprising: a plurality of memory cells arranged in rows and columns, each having a storage node pair statically holding complementary potentials while a power supply potential is being supplied, and each having two load MOS transistors, two driver MOS transistors, and two access MOS transistors; a plurality of word lines arranged for the respective rows of said plurality of memory cells; a row select circuit selecting a plurality of target word lines as a unit from among said plurality of word lines according to a provided row select signal; a plurality of bit line pairs arranged corresponding to the columns of said plurality of memory cells, respectively, and each having first and second bit lines connected to said two access MOS transistors, respectively; a column select circuit selectively activating said plurality of bit line pairs in accordance with a provided column select signal; a power supply circuit selectively supplying a power supply potential to each of said plurality of memory cells; a write circuit writing data into memory cells connected to said plurality of target word lines among said plurality of memory cells and setting potential states of said first and second bit lines according to a supply instruction signal; and a control circuit receiving a signal selecting said plurality of target word lines, and providing said row select signal and said column select signal, wherein in said test mode in which data are written into said plurality of memory cells, said power supply circuit stops supply of said power supply potential to each of said plurality of memory cells by setting both potential states of said first and second bit lines to an inactive level in response to inactivation of said supply instruction signal at a first step, said write circuit sets the potential state of one of said first and second bit lines according to said data to an active level and the potential state of the other bit line to the inactive level in response to activation of said instruction signal at a second step, and said power supply circuit supplies said power supply potential to each of said plurality of memory cells in response to activation of said supply instruction signal, after said second step.