Patent ID: 8625371

Claim:
A memory component comprising: a signaling interface having an on-die terminated data input/output (I/O), an unterminated input to receive command/address (CA) signals, a strobe input and a clock input, each to be coupled to a respective external signaling link; data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write date bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O; CA circuitry to sample the CA signals at the CA input, the sampling of the CA signals being timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively; and closed-loop clock generation circuitry coupled to receive the second clock signal via the clock input and to generate the first clock signal with a phase that establishes, at the signaling interface, an alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal.