Patent ID: 8804403

Claim:
A semiconductor memory device comprising a memory cell including: a first driving transistor connected to a first storage node; a first load transistor connected to the first storage node; a first read transfer transistor connected between the first storage node and a first read bit line; a first variable resistance element which has one terminal connected to the first storage node and has another terminal, a resistance of which changes depending on a voltage applied to both terminals; a first write transfer transistor arranged between a first write bit line and the first variable resistance element; a second driving transistor connected to a second storage node; a second load transistor connected to the second storage node; a second read transfer transistor arranged between the second storage node and a second read bit line; a second write transfer transistor arranged between the second storage node and a second write bit line, wherein a source of the first driving transistor and a source of the second driving transistor are connected to a first supply voltage and data written to the first storage node is saved to the first variable resistance element in response to the first supply voltage changing between a plurality of different voltage levels.