Patent ID: 7535278

Claim:
A clock circuit, comprising: a plurality of clock output blocks, each clock output block being coupled to receive a common clock signal, and each clock output block having an output providing a respective clock signal with a selectable phase delay relative to the common clock signal and other ones of the delay blocks, each clock output block comprising: a plurality of counter controlled delay devices (CCDs), each CCD having an input coupled to receive the common clock signal, and further having an output; and a latch having a first set input coupled to the output of a first one of the CCDs, and a first reset input coupled to the output of a second one of the CCDs, the latch having an output providing the output of the clock output block, wherein each of the CCDs comprises: a starter circuit having an input providing the input of the CCD, a reset input, and an output; an oscillator having a start input coupled to the output of the starter circuit, a reset input, and an output; a counter having a clock input coupled to the output of the oscillator, a reset input, and a count output; a sampler register having an input coupled to the count output of the counter, and further having an output providing the output of the CCD and further coupled to the reset inputs of the starter circuit, the oscillator and the counter; and a delay element coupling the output of the sampler register to a reset input of the sampler register.