Patent ID: 8867273

Claim:
A non-volatile semiconductor memory device comprising: a plurality of cell units including first and second select gate transistors and a memory string that is provided between the first and second select gate transistors and includes a plurality of memory cells which store electrically-rewritable data and are connected in series to each other; and a data writing unit that sequentially writes lower page data and upper page data corresponding to the lower page data to a selected memory cell selected in order from one close to the first select gate transistor to one close to the second select gate transistor, and performs a first writing operation of writing the lower page data to the selected memory cell and a second writing operation of writing the upper page data to the selected memory cell after the first writing operation for n (n is an integer equal to or greater than 2) non-selected memory cells which are adjacent to a side of the selected memory cell close to the second select gate transistor.