Patent ID: 7171535

Claim:
A serial operation pipeline, comprising: a plurality of arithmetic-logic circuits connected in a cascade fashion, each of the arithmetic-logic circuits capable of being controlled independently and being operable together with other of the arithmetic-logic circuits, at least one of the plurality of arithmetic-logic circuits including a first line for outputting data from an upstream stage to a downstream stage, a second line for feeding back reverse data from the downstream stage to the upstream stage, and a latch circuit that latches the data on the first and second lines; wherein each of the plurality of arithmetic-logic circuits includes a decoder for executing a process including an operation corresponding to contents of an externally supplied instruction to produce an execution result, and for outputting data representative of the execution result to a selected one of the first and second lines; wherein the first line includes a pair of lines for outputting first output data and second output data to the downstream stage, and the latch circuit includes a first data latch circuit that latches the first output data, a second data latch circuit that latches the second output data, a carry latch circuit that latches a carry resulting from an operation executed by the decoder for the operation of a succeeding figure, and a shift latch circuit that delays one of the first output data and the second output data for a given period of time.