Patent ID: 8639886

Claim:
A method of performing a store-to-load forwarding operation in a processor of a computer system having a memory, the method comprising: executing a first load instruction that results in a first load cache miss condition; in response to occurrence of the first load cache miss condition, the processor: copying a current state of the processor to a restore point in the memory; entering a runahead mode of operation, wherein during the runahead mode of operation the processor: continually executing a plurality of subsequent instructions that are more recent than the first load instruction, wherein the plurality of subsequent instructions include a second load instruction; forwarding speculative values produced by the plurality of subsequent instructions to new store entries within the store queue, wherein the store queue is disposed within an execution core of the processor; in response to encountering a second load cache miss condition of the second load instruction during the runahead mode and prior to a time that the first load instruction completes processing the first load cache miss condition, stalling for a period of time; and providing at least one subsequent load instruction included in the plurality of subsequent instructions being executed during the runahead mode access all store entries of the store queue, wherein each store entry includes an address and data associated with a store instruction; and in response to the first load instruction completing: retrieving the restore point; and executing a first subsequent instruction of the plurality of subsequent instructions from the restore point while continuing concurrent processing the second load instruction from the memory.