Patent ID: 8364736

Claim:
A memory-based FFT/IFFT processor comprises: a main memory to store data; a processing element for decomposed FFT computation; a control unit to control: (1) the memory for I/O data and to control butterflies computation (2) computation order of the decomposed FFT (3) the memory addressing of the main memory for data access with in-place policy, wherein the function (3) of the control unit controls the data access with in-place policy for both the butterflies computation and the I/O data for each memory blocks; and wherein the address of accessed data is determined by the index vector (n 1 , n 2 . . . , n k ) and equation (a 2 ): address = ∑ i = 1 k - 2 ⁢ ( ∏ j = i + 1 k - 1 ⁢ ⁢ U j ) ⁢ u i + u k - 1 ⁢ ⁢ mod ( N ⁢ / ⁢ M ) ( a 2 ) Here, N=N 1 N 2 . . . N k and we take M=N t is one of {N 1 , N 2 , . . . , N k }. And, (U 1 , U 2 , . . . , U k−1 )=(N 1 , N 2 , N t−1 , N t+1 , . . . , N k ), (u 1 , u 2 , . . . , u k−1 )=(n 1 , n 2 , . . . , n t−1 , n t+1 , . . . , n k ).