Patent ID: 8687440

Claim:
A semiconductor memory device comprising: a memory cell array from which a data signal or signals of a first bit number including a payload data signal and an error checking and correcting code data signal are simultaneously read; a sense amplifier configured to amplify the read data signal or signals; a sense amplifier data selector configured to select a data signal or signals of a second bit number which are a portion of the data signals amplified by the sense amplifier; an error checking and correcting unit configured to perform error checking and correcting based on at least a portion of the selected data signals of the second bit number; a first holding unit configured to hold an input data signal externally input to the semiconductor memory device; a second holding unit connected to the first holding unit via a first switch; an amplifier configured to amplify the data signal or signals of the second bit number selected by the sense amplifier data selector; a third holding unit configured to hold a data signal which is obtained before or after amplification by the amplifier; and an error checking and correcting code data signal generator configured to generate the error checking and correcting code data signal based on a data signal held in the second holding unit.