Patent ID: 8631183

Claim:
An integrated circuit system comprising: a first integrated circuit that is connected with a first data bus having first bus width and requires first time to perform data transmission and reception once; a second integrated circuit that is connected with a second data bus having second bus width larger than the first bus width in bit width and requires second time longer than the first time to perform data transmission and reception once; and a relay circuit that is connected with the first data bus and the second data bus and transmits and receives data to and from the first integrated circuit and the second integrated circuit respectively via the buses, the relay circuit including a first-data-bus control unit, a second-data-bus control unit, a first temporary storage unit for high-speed read, and a second temporary storage unit for high-speed read, wherein the first integrated circuit outputs a first readout signal and a readout source address for reading out continuous readout data to be received and excess data which is equivalent to both m times (m is an integer larger than 1) of access of the first data bus and one access of the second data bus and stores, when all data including the excess data added to the readout data to be received is received from the relay circuit, the readout data to be received excluding the excess data, the relay circuit outputs, every time the first readout signal for predetermined m times is received from the first integrated circuit, a second readout signal to the second integrated circuit only when the first readout signal in the first time is received, acquires data which is equivalent to both m times of access of the first data bus and one access of the second data bus from the second integrated circuit and stores the data, and outputs the data to the first integrated circuit, the data output to the first integrated circuit comprising the readout data to be received and the excess data, the second readout signal being generated by modifying the readout source address of the first readout signal, the second integrated circuit outputs, according to the second readout signal output from the relay circuit, data from the readout source address designated first by the first integrated circuit to the relay circuit, the data from the readout source address comprising the data acquired by the relay circuit, and the first-data-bus control unit and the second-data-bus control unit alternately operate such that, while data is stored in the first temporary storage unit for high-speed read, data is output from the second temporary storage unit for high-speed read and, while data is stored in the second temporary storage unit for high-speed read, data is output from the first temporary storage unit for high-speed read.