Patent ID: 7787499

Claim:
A receiver block comprising: a synchronization generator generating a sequence of synchronization signals with a short interval between successive ones of said sequence of synchronization signals; a plurality of converter blocks receiving each of a plurality of sequences of serial data elements on a corresponding one of a plurality of serial data channels, said plurality of converter blocks converting each of said plurality of sequences of serial data elements to a corresponding one of a plurality of sequences of parallel data elements, said plurality of converter blocks sending each of said plurality of sequences of parallel data elements on a corresponding one of a plurality of parallel data channels, wherein each of said parallel data elements comprises a byte containing 8 bits, such that said sequence of synchronization signals are generated periodically with a period of eight times the period of said second common clock signal, and wherein each of said sequence of synchronization signals comprises a pulse; and said plurality of converter blocks receiving said sequence of synchronization signals and ensuring that said plurality of parallel data channels are synchronized with a first common clock signal in response to each of said sequence of synchronization signals such that all of said sequences of parallel data elements are sent on said plurality of parallel data channels using said first common clock signal, wherein said plurality of converter blocks receive a second common clock signal associated with said plurality of serial data channels and wherein said second common clock signal provides a common reference for said plurality of serial data channels.