Patent ID: 6927450

Claim:
A semiconductor device comprising: a plurality of parallel extending conductive regions comprising an impurity provided on a substrate surface that constitutes a region of a memory cell array; a pair of said conductive regions being interconnected by a wiring constituting an upper layer of the substrate or by a conductive region of the substrate surface, said pair of said conductive regions composing a set of sub-bit lines; a plurality of gate electrodes formed in a direction that perpendicularly intersects the longitudinal direction of the sub-bit lines, said gate electrodes composing word lines; a set of the sub-bit lines being connected to a main bit line via a selection transistor; a plurality of the selection transistors being disposed in opposition on both sides of the memory cell array; plural sets of the sub-bit lines connected to respective ones of a plurality of selection transistors on one side of the memory cell array and plural sets of the sub-bit lines connected to respective ones of a plurality of selection transistors on the other side of the memory cell array being arranged in interdigital fashion; and a memory-cell transistor having an insulating film including first and second oxide films, and a nitride film sandwiched between said first and second oxide films, provided on the substrate surface, and a Salicide-structure gate electrode provided on the insulating film; wherein said insulating film is provided even in a region besides a channel region immediately underlying the gate electrode of the memory-cell transistor.