Patent ID: 6885580

Claim:
A memory device, comprising: a memory array comprising a plurality of resistive memory cells, each one of said memory cells being coupled to one of a plurality of row lines and one of a plurality of column lines; addressing circuitry, for selecting a selected row line and a selected column line; a read voltage source, for supplying, via said addressing circuitry, a read voltage to said selected row and column lines during a read/sense period; a plurality of sample and hold circuits, each associated with a respective one of said column lines; a plurality of sense circuits, each associated with a respective one of said sample and hold circuits; a switching circuit, said switching circuit operable in a first state to couple said read voltage source with said selected row line while simultaneously coupling said selected column line with an associated one of said sample and hold circuits, and said switching circuit operable in a second state to decouple said read voltage source from said selected row line while simultaneously decoupling said selected column line from said associated one of said sample and hold circuits; and a control circuit for operating said switching circuit in a said first state after a start of said read/sense period of a memory cell associated with said selected row and column lines, and for operating said switching circuit in said second state before an end of said read/sense period.