Patent ID: 7724060

Claim:
An interface circuit comprising a clock output circuit configured to: detect whether a logic level of an input clock signal is at a first logic level or a second logic level, when detecting a logic level change of an input control signal from a third logic level to a fourth logic level; when the detected logic level of the input clock signal is at the first logic level: change a logic level of an output clock enable signal from a fifth logic level to a sixth logic level at the same time as the logic level change of the input control signal from the third logic level to the fourth logic level, and output the input clock signal, as an output clock signal, to a data register that is configured to serially read in data synchronously with the output clock signal, the output clock enable signal being a signal for outputting the input clock signal, as the output clock signal, to the data register; and when the detected logic level of the input clock signal is at the second logic level: detect when the logic level of the input clock signal changes from the second logic level to the first logic level, and change the logic level of the output clock enable signal from the fifth logic level to the sixth logic level at the same time as the logic level change of the input clock signal from the second logic level to the first logic level, and output the input clock signal, as the output clock signal, to the data register, when detecting that the logic level of the input clock signal changes from the second logic level to the first logic level, wherein outputting the input clock signal, as the output clock signal, is based on the logic level of the input clock signal, the logic level of the input control signal, and the logic level of the output clock enable signal.