Patent ID: 7408230

Claim:
An EEPROM device comprising: a first gate stack of a memory transistor formed on a semiconductor substrate; a second gate stack of a selection transistor adjacent the first gate stack with a spacer therebetween on the semiconductor substrate; a source region formed on a portion of the semiconductor substrate adjacent the first gate stack at a side opposite the second gate stack; a drain region formed on a portion of the semiconductor substrate adjacent the second gate stack at a side opposite the first gate stack; a floating junction region formed on an active region of the substrate and forming a channel of the memory transistor and/or the selection transistor, wherein the floating junction region is formed of: a first doped region, one end of which is extended facing the drain region and the other end of which is extended facing the source region and located under the first gate stack and formed on the semiconductor substrate so as to be completely beneath the first gate stack, the spacer, and the second gate stack; and a second doped region formed on the semiconductor substrate to surround the first doped region and being doped with an opposite conductivity type dopant than the first doped region and being located so as to be completely beneath the first gate stack, the spacer, and the second gate stack, whereby a length of the effective channel of the memory transistor and/or the selection transistor is increased, wherein the first doped region is an n + dopant region, and wherein the second doped region is a p − dopant region that surrounds the n + dopant region.