Patent ID: 8922012

Claim:
An integrated circuit (IC) chip comprising: an integrated circuit (IC) device including a plurality of conductive structures stacked on a substrate and a plurality of wiring lines electrically connected to the plurality of the conductive structures; an electrode pad arranged on the IC device and electrically communicating with the conductive structures through at least one of the plurality of wiring lines, the electrode pad including a first pad to which at least one of the wiring lines is extended and a second pad making direct contact with the at least one of the wiring lines that is partially positioned under the second pad; a passivation pattern covering the electrode pad and including a first passivation opening through which the first pad is partially exposed and at least a second passivation opening through which the second pad is partially exposed, the second passivation opening being horizontally apart from the wiring line positioned under the second pad; and a bump structure arranged on the passivation pattern and including a first bump structure making contact with the first pad through the first passivation opening and a second bump structure making contact with the second pad through the second passivation opening such that the second bump structure is horizontally apart from the underlying wiring line, wherein the second passivation opening includes a first split passivation opening apart from at least one of the plurality of wiring lines by a first distance in a first direction and a second split passivation opening apart from the at least one of the plurality of wiring lines by a second distance in a second direction opposite to the first direction, so that the first and the second split passivation openings are arranged on the second pad symmetrical to each other with respect to the at least one of the plurality of wiring lines, and wherein the first pad has no wiring line directly under it.