Patent ID: 7477553

Claim:
A control device for controlling a buffer memory that can store n data words and is capable of being used for data transfer between a first system and a second system, the control device comprising: a write pointer comprising a first n-bit shift register, wherein: the first n-bit shift register comprises a data input and a data output that are connected together, a control input, and a clock input, a write-enable signal, which is active when the memory is not full and the first system commands a write operation, is supplied to the control input of the first n-bit shift register, a first clock signal associated with the first system is supplied to the clock input of the first n-bit shift register, and the first n-bit shift register contains at least two successive bits in a first logic state, with the other bits being in a second logic state; a read pointer comprising a second n-bit shift register, wherein: the second n-bit shift register comprises a data input and a data output that are connected together, a control input, and a clock input, a read-enable signal, which is active when the memory is not empty and the second system commands a read operation, is supplied to the control input of the second n-bit shift register, a second clock signal associated with the second system is supplied to the clock input of the second n-bit shift register, and the second n-bit shift register contains at least two successive bits in the first logic state, with the other bits being in the second logic state; a write management circuit for comparing content of the write pointer and content of the read pointer, and authorizing or not authorizing a write operation in the memory; and a read management circuit for comparing the content of the write pointer and the content of the read pointer, and authorizing or not authorizing a read operation in the memory.