Patent ID: 7308537

Claim:
A method of operating a cache memory comprising: logically partitioning a cache array into at least first and second slices with a first plurality of cache lines in the first cache slice and a second plurality of cache lines in the second cache slice; arranging the cache array in rows and columns of cache sectors, the rows corresponding to cache ways, wherein a given cache line is spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency; detecting that one of the cache ways is defective, the defective cache way being in a first set of cache ways assigned to the first cache slice and the second cache slice; and disabling the first set of cache ways while continuing to use at least one other set of cache ways assigned to the first cache slice and the second cache slice.