Patent ID: 7978499

Claim:
A semiconductor storage device comprising: a memory cell array having memory cells positioned at intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells including a rectifier element and a variable resistance element connected in series; and a control circuit configured to apply a first voltage to a selected one of the first wirings as well as a second voltage to a selected one of the second wirings, so that a first potential difference is applied to a selected memory cell positioned at an intersection between the selected one of the first wirings and the selected one of the second wirings, the control circuit comprising: a signal output circuit configured to output a first signal based on a first current flowing through the selected memory cell via the selected one of the first wirings and the selected one of the second wirings and a reference current; and a current retaining circuit configured to retain a second current flowing through the first wirings or a wiring electrically connected to the first wirings during a certain period of time, the signal output circuit being configured to determine the first current based on the second current retained by the current retaining circuit; and the control circuit being configured to stop application of the first voltage to the first wirings based on the first signal.