Patent ID: 8766705

Claim:
A semiconductor integrated circuit having a semiconductor chip, comprising: a logic circuit; a plurality of series-coupled buffers that are distributively disposed in a region containing the logic circuit and are arranged to have a constant logical value of primary-stage input; a plurality of parallel-coupled detection diodes that are in a reverse-biased state with respect to a signal path between an input of each of the buffers and an output of a buffer located at a stage anterior thereto; a detection circuit for detecting an input logical value inversion due to a change to a forward-biased state in the detection diode at the time of light irradiation; and a limiter circuit for imposing limitation on operation of the logic circuit in response to the input logical value inversion detected by the detection circuit, the logic circuit, the series-coupled buffers, the parallel-coupled detection diodes, the detection circuit, and the limiter circuit being formed in the single semiconductor chip.