Patent ID: 7502247

Claim:
An integrated circuit comprising: an array of SRAM memory cells arranged in rows and columns, the SRAM cell comprising cross-coupled amplifiers having internal pull-up transistors connected to a supply line; a plurality of wordlines associated with the rows of cells of the array; a plurality of bit lines associated with the columns of cells of the array; a word line driver operable to drive a selected word line of the array, wherein the wordline driver is further operable to: during a write operation, access the selected wordline associated with the SRAM memory cell by asserting a read wordline voltage to the selected wordline; generate a bit line difference voltage on the bit lines; and assert a write wordline voltage after generation of the bit line difference voltage to the selected wordline of the memory cell during the write operation; wherein the bit line difference voltage imposed on the bit line by an accessed cell increases the stability of the cell prior to the word line being driven to a full access voltage.