Patent ID: 7470612

Claim:
A method of forming a metal wiring layer of a semiconductor device, the method comprising: forming an insulating layer pattern defining a recess on a substrate; forming a first barrier metal layer which extends over an upper surface of the insulating layer pattern, over a side wall of the insulating layer pattern that defines the sides of the recess, and along the bottom of the recess; forming a second barrier metal layer on the first barrier metal layer comprising including over that portion of the first barrier metal layer that overlies the upper surface of the insulating layer pattern and over that portion of the first barrier metal layer that extends within the recess, the second barrier metal layer comprising a nitride layer, and wherein the forming of the second barrier metal layer is terminated at a time when the nitrogen content of that portion of the second barrier metal layer extending within the recess is lower than the nitrogen content of that portion of the second barrier metal layer which lies over the upper surface of the insulating layer pattern; filling only a portion of the recess with electrically conductive material to thereby form a damascene wiring; and forming an etch stop layer pattern in an upper portion of the recess which is not occupied by the damascene wiring.