Patent ID: 7206928

Claim:
A method comprising: powering up a system on a chip (SoC) with a system control circuitry (SCC) that contains a central processing unit (CPU); holding the CPU in a reset condition; using a serial boot hardware, with no CPU and firmware involvement, to configure the system to interface with various system memory architectures including random memory types and organizations; retrieving, over a serial data bus using the serial boot hardware and a serial communications protocol, information about a system memory configuration and a boot program from a first section of a first serial programmable read only memory (PROM); retrieving, over a serial data bus using the serial boot hardware and the serial communications protocol, a boot program from a second section of the first serial PROM using the information about the system memory configuration and the boot program; writing the boot program into a system memory that is external to the SoC; releasing the CPU from the reset condition; and booting the SoC using the boot program.