Patent ID: 7307024

Claim:
A method for fabricating a flash memory, comprising the steps of: forming a tunneling oxide layer on a semiconductor substrate; forming a floating gate by depositing a first polycrystalline silicon layer on the tunneling oxide layer; selectively etching the floating gate and the tunneling oxide layer to form two regions, wherein the two regions have a predetermined width on an active area of the semiconductor substrate, are separated from each other by a predetermined interval, and are connected to each other in a field area of the semiconductor substrate; forming a gate insulation film on the entire surface of the semiconductor substrate including the floating gate; forming a control gate by depositing a second polycrystalline silicon layer on the gate insulation film; exposing an outside wall of the floating gate by etching the gate insulation film formed on the outside wall of the floating gate while selectively etching the control gate and the gate insulation film such that the control gate and the gate insulation film to have a predetermined width; forming a nitride film on the entire top surface of the semiconductor substrate and then forming a side wall on outside walls of the control gate, the gate insulation film, the floating gate, and the tunneling oxide by blanket-etching the nitride film, wherein the side wall is formed to have a height which is not greater than a height of the control gate; and forming a source and drain region by injecting impurities into the semiconductor to the outside of the floating gate.