Patent ID: 8812934

Claim:
A data storage system comprising: a memory circuit comprising memory cells; and a control circuit to generate a first set of redundant bits indicating bit positions of the memory cells having stuck-at faults in response to a first write operation if a first rate of the stuck-at faults in the memory cells is greater than a first threshold, wherein first data bits are stored in the memory cells during the first write operation, wherein the control circuit encodes second data bits to generate first encoded data bits and a second set of redundant bits that indicate a transformation performed on the second data bits to generate the first encoded data bits in response to a second write operation if a second rate of stuck-at faults in the memory cells is greater than a second threshold, wherein the first encoded data bits are stored in the memory cells during the second write operation, and wherein the first encoded data bits stored in the memory cells having the stuck-at faults match digital values of corresponding ones of the stuck-at faults.