Patent ID: 8378389

Claim:
A semiconductor device comprising: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer, wherein the n-channel field-effect transistor region is a region that includes the p-type second channel layer; an n-type gate layer formed simultaneously with the n-type gate region; the first channel layer; and the n-type first barrier layer laminated in this order above the compound semiconductor substrate.