Patent ID: 7394124

Claim:
A dynamic random access memory, comprising: a deep trench capacitor disposed in a first trench of a substrate, wherein the substrate further has a second trench, wherein a depth of the second trench is smaller than a depth of the first trench, and a part of the second trench overlaps with the first trench and the remained part of the second trench does not overlap with the first trench, the deep trench capacitor comprising: a bottom electrode disposed in the substrate at a bottom of the first trench; a capacitor dielectric layer disposed on a lower sidewall of the first trench; a first collar oxide layer disposed on an upper sidewall of the first trench and above the capacitor dielectric layer; and a first conductive layer disposed in the first trench; a second conductive layer disposed in the second trench and directly and electrically connected with the first conductive layer; a gate structure disposed on the substrate; and a third conductive layer disposed on the surface of the substrate on both sides of the gate structure, wherein the third conductive layer at one side of the gate structure is directly and electrically connected with the second conductive layer.