Patent ID: 8884304

Claim:
A thin film transistor array substrate, comprising: a substrate comprising a display region, a gate driver region, and a source driver region; a plurality of poly-silicon islands disposed on the substrate, wherein each of the poly-silicon islands comprises a source region, a drain region, and a channel region disposed between the source region and the drain region, the poly-silicon islands comprising: a plurality of first poly-silicon islands disposed in the display region and the gate driver region, the first poly-silicon islands having a main grain boundary with grains protrude from the surface of the first poly-silicon islands and a sub grain boundary, wherein the main grain boundary of the first poly-silicon islands is only disposed within the source regions and/or the drain regions; a plurality of second poly-silicon islands disposed in the source driver region, wherein grain sizes of the first poly-silicon islands are different from grain sizes of the second poly-silicon islands, such that the grain sizes of the first poly-silicon islands disposed in gate driver region are different from grain sizes of the second poly-silicon islands disposed in the source driver region, the second poly-silicon islands comprise a main grain boundary and a sub grain boundary, and the main grain boundary of the second poly-silicon islands is only disposed within the source regions or the drain regions, the grain sizes of the second poly-silicon islands are substantailly smaller than the grain sizes of the first poly-silicon islands; and a plurality of gates, disposed on the substrate and being corresponds to the channel regions.