Patent ID: 8885388

Claim:
A memory comprising: an array of memory cells; a first module configured to compare a first state of a memory cell with a reference, wherein the memory cell is in the array of memory cells; and a second module configured to, subsequent to a first read cycle or a first write cycle of the memory cell and based on the comparison, reform the memory cell to reset and increase a current difference in resistance between the first state and a second state of the memory cell, wherein the current difference is increased to be (i) greater than or equal to a predetermined difference, or (ii) equal to an initial difference obtained during an initial forming of the memory cell, the initial forming of the memory cell is performed subsequent to manufacturing of the memory and prior to the first read cycle or the first write cycle of the memory cell, the second module is configured to, during the reforming, apply a first voltage to the memory cell, and the first voltage is greater than a voltage applied to the memory cell during the first read cycle or the first write cycle.