Patent ID: 7388243

Claim:
A self-aligned buried contact pair, comprising: a substrate having a plurality of diffusion regions; a lower layer on the substrate, the lower layer exposing a pair of the plurality of diffusion regions in the substrate; a plurality of bit lines on the lower layer, each of the plurality of bit lines being formed between adjacent diffusion regions in the substrate and each of the plurality of bit lines having bit line sidewall spacers formed on sidewalls thereof; an upper interlayer dielectric (ILD) layer on the plurality of bit lines and the lower layer; a pair of buried contact pads between adjacent bit lines and within the upper ILD layer, each of the pair of buried contact pads being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of buried contact pads having one of the pair of capacitors thereon, wherein a pair of the plurality of the bit line sidewall spacers is adjacent to each of the buried contact pads and respective bit line sidewall spacers of each of the pairs of the plurality of the bit line sidewall spacers have an asymmetrical shape relative to each other.