Patent ID: 8817516

Claim:
A memory circuit comprising: a first transistor; a second transistor; a first inverter comprising an input terminal connected to one of a source electrode and a drain electrode of the first transistor, and an output terminal; a second inverter comprising an input terminal connected to one of a source electrode and a drain electrode of the second transistor, and an output terminal; a third transistor comprising one of a source electrode and a drain electrode connected to the input terminal of the first inverter and the one of the source electrode and the drain electrode of the first transistor, and the other of the source electrode and the drain electrode connected to the output terminal of the second inverter; a fourth transistor comprising one of a source electrode and a drain electrode connected to the input terminal of the second inverter and the one of the source electrode and the drain electrode of the second transistor, and the other of the source electrode and the drain electrode connected to the output terminal of the first inverter; a fifth transistor comprising one of a source electrode and a drain electrode connected to the one of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the third transistor; a first capacitor comprising a first electrode connected to the other of the source electrode and the drain electrode of the fifth transistor; a sixth transistor comprising one of a source electrode and a drain electrode connected to the one of the source electrode and the drain electrode of the second transistor and the one of the source electrode and the drain electrode of the fourth transistor; and a second capacitor comprising a first electrode connected to the other of the source electrode and the drain electrode of the sixth transistor, wherein each of the fifth transistor and the sixth transistor has an off-state current per channel width of 1 μm is 100 zA or lower.