Patent ID: 7269709

Claim:
A memory controller comprising: a plurality of channel control circuits, wherein each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels, and wherein the plurality of channels, during use, are coupled to a memory system; a decode circuit coupled to receive an indication of whether or not the plurality of channels are ganged or not ganged, the decode circuit also coupled to receive a transaction on an interconnect and decode a command from the transaction to be sent to the channel control circuits to perform a memory access to the memory system based on the indication, and the decode circuit to determine which of the plurality of channels is to be used based on the indication; a channel configuration register coupled to the decode circuit and the plurality of channel control circuits, wherein the channel configuration register is programmable to store the indication and data is transferred to or from the memory system based on the command and responsive to the indication; and a data normalizer circuit coupled to the plurality of channel control circuits and to a data portion of the plurality of channels, wherein the data normalizer circuit is configured to route read data from the plurality of channels to a first channel control circuit responsive to the indication indicating that the plurality of channels are ganged, and wherein the data normalizer is configured to route read data from the plurality of channels to a respective one of the plurality of channel control circuits responsive to the indication indicating that the channels are not ganged.