Patent ID: 7355876

Claim:
A memory array circuit comprising: a common power supply line; a plurality of mutually parallel word lines; at least 2mn+1 mutually parallel sub-bit lines crossing the word lines, m and n being integers greater than one; at least 2n mutually parallel main bit lines; at least 2mn first switching elements switchably connecting each of the at least 2n main bit lines to a consecutive group of m of the sub-bit lines; at least 2mn+1 second switching elements switchably connecting each of the 2mn+1 sub-bit lines to the common power supply line; a plurality of memory cells, each memory cell having a pair of main electrodes connected to a mutually adjacent pair of the sub-bit lines and a control electrode connected to one of the word lines, each memory cell storing two bits of information readable from different ones of the main electrodes when the word line to which the control electrode is connected is activated; m first signal lines connected to and controlling different sets of the first switching elements, each set including one first switching element and all other first switching elements disposed at intervals equal to integer multiples of m sub-bit lines from that one second switching element; and 2m second signal lines connected to and controlling different sets of the second switching elements, each set including one second switching element and all other second switching elements disposed at intervals equal to integer multiples of 2m sub-bit lines from that one second switching element.