Patent ID: 6936922

Claim:
A semiconductor package comprising: a substrate including a core insulative layer with a central through hole, and a plurality of circuit patterns on a first surface of the core insulative layer, with each of the plurality of circuit patterns of the first surface including a ball land; wherein a first subset of ball lands protrude further from the first surface than a second subset of the ball lands; a plurality of same size solder balls, wherein a respective one of the solder balls is fused to each of the respective ball lands of the first and second subsets of the ball lands, whereby the solder balls fused to the ball lands of the first subset protrude further from the first surface than the solder balls fused to the ball lands of the second subset; a semiconductor die disposed in the through hole and electrically coupled to the circuit patterns; and a hardened encapsulant in the through hole covering the semiconductor die.