Patent ID: 8448118

Claim:
A computer-implemented method of determining intra-die wirebond pad placement locations in an integrated circuit (IC) die, the method comprising: generating a dividing band in the IC die, the dividing band dividing the IC die into a first region and a second region; determining a voltage drop across the first region and a voltage drop across the second region; comparing the voltage drop across the first region with the voltage drop across the second region; and in response to the voltage drop across the first region not being equal to the voltage drop across the second region, iteratively performing the following: moving the dividing band to a new location within the IC die to form a new first region and a new second region; determining a voltage drop across the new first region and a voltage drop across the new second region; and comparing the voltage drop across the new first region and the new second region until the voltage drop across the new first region is approximately equal to the voltage drop across the new second region.