Patent ID: 7476969

Claim:
A semiconductor package for surface mounting, said semiconductor package comprising; a substrate having a mounting surface and a back surface facing opposite to each other, wire-bonding electrode patterns for wire-bonding being formed exclusively and directly on said mounting surface and connector electrode patterns and lead-in patterns for electrolytic plating being formed exclusively and directly on said back surface, said lead-in patterns being connected to said connector electrode patterns and reaching an edge part of said substrate; semiconductor chips that are wire-bonded on said mounting surface; and a resin layer that seals said mounting surface so as to seal in said wire-bonding electrode patterns; wherein said mounting surface has no lead-in pattern formed thereon to reach an edge part of said substrate; wherein said substrate is provided with passages through which the wire-bonding and connector electrode patterns placed correspondingly opposite to each other with respect to said substrate on said mounting surface and said back surface are electrically connected; and wherein said wire-bonding and connector electrode patterns each have a metal film that is formed by an electrolytic plating process.