Patent ID: 8302297

Claim:
A method for fabricating a circuit board structure, comprising the steps of: providing a carrier board; forming a first circuit layer on the surface of the carrier board; forming a first dielectric layer on the carrier board and the first circuit layer in a manner that the first circuit layer is exposed from a surface of the first dielectric layer; forming a second dielectric layer on the first circuit layer and the first dielectric layer; forming a metallic layer on the second dielectric layer; forming a plurality of vias to penetrate the second dielectric layer and the metallic layer, so as for portions of the first circuit layer to be exposed from the vias, respectively; forming a conductive layer on the metallic layer, walls of the vias, and the exposed portions of the first circuit layer; forming a resist layer on the conductive layer, followed by forming a plurality of opening regions to penetrate the resist layer so as to expose correspondingly a portion of the conductive layer, wherein a portion of the opening regions corresponds in position to the vias; forming a second circuit layer on the conductive layer of the opening regions, and forming a first conductive via in the via so as for the second circuit layer to be electrically connected to the first circuit layer; removing the conductive layer, the metallic layer, and the resist layer on the conductive layer; and removing the carrier board so as to expose the first dielectric layer and the first circuit layer.