Patent ID: 8008776

Claim:
A chip comprising: a silicon substrate; a transistor in or on said silicon substrate; a first metal layer over said silicon substrate; a second metal layer over said first metal layer and over said silicon substrate; a dielectric layer between said first and second metal layers; a contact pad over said silicon substrate; a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a silicon nitride, wherein a first opening in said passivation layer is over a first contact point of said contact pad, and said first contact point is at a bottom of said first opening; a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 1 and 100 micrometers, wherein a second opening in said first polymer layer is over said first contact point; a metallization structure on said first contact point, in said second opening and on said first polymer layer, wherein said metallization structure comprises electroplated gold in said second opening and over said first polymer layer; and a second polymer layer on said metallization structure, wherein a third opening in said second polymer layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said third opening, wherein said second contact point is connected to said first contact point through said second opening, wherein said second contact point is not vertically over said first contact point.