Patent ID: 8793560

Claim:
An apparatus comprising: a processor configured to obtain real and imaginary components of received symbols for a transmission sent via a communication channel, and derive log-likelihood ratios (LLRs) for a first pair of code bits based on the real component of each of the received symbols and a second pair of code bits based on the imaginary component of each of the received symbols, the LLRs comprising: a first LLR function for sign bits that determine a sign of the real and imaginary components of the symbols; and a second LLR function for magnitude bits that determine a magnitude of the real and imaginary components of the symbols; and a memory coupled to the processor; wherein the LLRs comprise a piecewise linear approximation comprising a plurality of linear functions determined from an estimated signal amplitude of the received symbols, an estimated noise variance of the received symbols, a scale factor, and a scaled threshold.