Patent ID: 7563682

Claim:
A method in the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, including an LDMOS transistor, comprising the steps of: providing a semiconductor substrate, forming LDMOS source and drain regions of a first doping type in said substrate wherein the LDMOS drain region comprises a lighter and a heavier doped region, forming a channel region of a second doping type opposite of the first doping type in said substrate between said LDMOS source and drain regions and with a laterally graded net doping concentration, and forming an LDMOS gate region on said substrate, said LDMOS gate region including a gate semiconductor layer region on top of a gate insulation layer region, wherein the gate semiconductor layer region of said LDMOS gate region is formed with a laterally graded net doping concentration in a portion of the gate semiconductor layer region arranged directly over the channel region.