Patent ID: 7844754

Claim:
A data transfer apparatus, comprising: a processor; a memory as a main memory connected to the processor; a data transfer unit that is a direct memory access controller connected to the memory through a plurality of buses and is configured to perform data transfer processing to transfer data to be transferred from a device having the data to be transferred to a first storage area of the memory by bypassing the processor, and when the data transfer processing finishes, write status data indicating completion of the data transfer processing in a second storage area of the memory, and output a predetermined interrupt signal to the processor after writing the status data; and a transfer data readout processing unit that is an interrupt processing program provided in the processor, the transfer data readout processing unit being configured to refer to the second storage area in response to the predetermined interrupt signal sent to the processor and perform determination processing that determines whether or not the status data is written, repeat the reference to the second storage area when a result of the determination processing indicates that the status data is not written, and read out the data to be transferred in the first storage area and erase the status data in the second storage area when the status data is written.