Patent ID: 7839174

Claim:
An output buffer circuit, comprising: a high voltage detecting circuit for detecting a power supply with at least three selectable voltage levels and generating a first and a second determining signals and a first and a second bias voltages according to the power supply; a dynamic gate bias generating circuit biased by the first and the second bias voltages and receiving the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals; an output stage circuit comprising three P-type transistors stacked one by one and three N-type transistors stacked one by one, at least one of the P-type transistors and at least one of the N-type transistors being biased by the gate bias voltages, for outputting an output signal with the selectable voltage levels to an I/O pad; and a pad voltage detector for detecting a voltage of the I/O pad and providing a pad voltage detecting signal for the output stage circuit to modify the output signal outputted to the I/O pad.