Patent ID: 7208386

Claim:
A method of fabricating a drain-extended transistor, comprising: forming a first lightly-doped region of a first conductivity type at a selected location of a semiconductor surface of a body; forming a second lightly-doped region of a second conductivity type at a selected location of the semiconductor surface; implanting dopant of the first conductivity type into selected locations of the first lightly-doped region; forming isolation structures at the selected locations of the first lightly-doped region at which dopant of the first conductivity type is implanted in the implanting step, and an isolation structure at a selected location of the second lightly-doped region; forming a gate electrode over the surface, the gate electrode overlapping portions of the isolation structures at selected locations of the first lightly-doped region, and overlapping a plurality of channel regions of the first lightly-doped region disposed between the isolation structures; forming a source region at a selected location of the first lightly-doped region; and forming at least one drain region at a selected location of the second lightly-doped region, the at least one drain region spaced apart from the plurality of channel regions by the isolation structure at the selected location of the second lightly-doped region.