Patent ID: 6928632

Claim:
A method of designing a semiconductor device in which plural clocks having different frequencies are applied to a logic region, comprising the steps of: (a) dividing said logic region by the region of a logic operating with a specific clock, to obtain plural domains; (b) disposing-plural power supply bumps in a matrix manner in said logic region and, based on a predetermined first rule, uniquely assigning plural power supply voltages of different types that correspond to said clocks respectively, to said power supply bumps; (c) disposing plural first power supply lines in parallel in a first layer and, based on a predetermined second rule, uniquely assigning said power supply voltages to said first power supply lines; (d) disposing plural second power supply lines in parallel in a second layer different from said first layer, such that said second power supply lines are orthogonal to said first power supply lines when viewed from above and, based on a predetermined third rule, uniquely assigning said power supply voltages to said second power supply lines; and (e) classifying said power supply voltages into a power supply voltage used in each of said plural domains and changing, based on said classification, said power supply voltages uniquely assigned to said power supply bumps and said first and second power supply lines, one by one of said plural domains.