Patent ID: 7960274

Claim:
A method of forming a semiconductor structure comprising: providing a multilevel interconnect structure comprising a lower interconnect level and an upper interconnect level, wherein said lower interconnect level comprises a first dielectric material having at least one conductive feature embedded therein and said upper interconnect level comprises a second dielectric material having at least one opening that is in direct contact with said at least one conductive feature of the lower interconnect level; selectively depositing a Co-containing buffer layer in said at least one opening on exposed surfaces of said at least one conductive feature of the lower interconnect level; forming a first liner and a second liner within said at least one opening, wherein said first liner is continuously present on sidewalls of said second dielectric material within said at least one opening and on an entirety of an upper surface of the Co-containing buffer layer, and wherein said second liner is continuously present on an upper surface of said first liner; and forming a conductive material on said second liner in said at least one opening.