Patent ID: 7193330

Claim:
A semiconductor device comprising: a semiconductor chip having a first main surface on which a plurality of electrode pads are provided, a second main surface which opposes said first main surface, and a plurality of side surfaces between said first main surface and said second main surface; an extension portion which has a first surface and a second surface opposing said first surface, and which is formed in contact with said side surfaces of said semiconductor chip to surround said semiconductor chip and such that said first surface is at a substantially equal level to the level of said first main surface; an insulating film which is formed on said first surface and said first main surface such that a part of each of said plurality of electrode pads is exposed; a plurality of wiring patterns electrically connected to each of said electrode pads, respectively and extended from said electrode pads to the upper side of the first surface of said extension portion; a sealing portion which is formed on said wiring patterns and said insulating film such that a part of each of said wiring patterns is exposed; and a plurality of external terminals provided over said wiring patterns in a region including the upper side of said extension portion; and wherein a portions of said wiring patterns on a boundary and vicinity thereof between said semiconductor chip and the extension portion are formed wider or more thickly than other portions of said wiring patterns.