Patent ID: 6878995

Claim:
A CMOS-compatible lateral DMOS transistor, comprising: a gate insulator having a unitary thickness under a control gate in an entire active region through which current flows; a doped well region near a surface of the transistor, the well region determining the transistor threshold voltage, the well region being so arranged under the control gate that the well region occupies the entire area under the control gate on an active region and ends within a drift space between the control gate and a highly doped drain region, a highly doped zone of the same conductivity type as the highly doped drain region, said highly doped zone directly adjoining the control gate; wherein at least a semiconductor region immediately beside and under the highly doped drain region has a markedly lower doping concentration in comparison with the doping concentration of the well region, wherein the drift space between time control gate and the highly doped drain region has a surface that is totally covered by a VLDD region of the same conductivity type as the drain region, wherein the VLDD region is lowly doped in comparison with the highly doped drain region, the area-related net doping concentration in the VLDD region not exceeding a value of 5×10 12 At/cm 2 , such that upon application of a drain voltage which is below the breakdown voltage of the gate insulator the VLDD region is totally depleted of free charge carriers up to the semiconductor surface, at least in the part of the drift space, which adjoins the control gate and which is in the well region or in the part of the drift space adjoining said a highly doped zone, and wherein the VLDD region doping is also present outside the drift space of the DMOS transistor on all surface portions of active regions, which are not covered by the control gate.