Patent ID: 6883011

Claim:
A parallel counter comprising: a plurality of inputs for receiving a binary number as a plurality of binary inputs; a plurality of outputs for outputting binary outputs indicating the number of binary ones in the plurality of binary inputs, said plurality of outputs including a first output adapted to output a least significant bit of the binary outputs and at least one other output adapted to output at least one higher significant bit of the binary outputs; and a logic circuit connected between the plurality of inputs and the plurality of outputs and for generating at least one of said at least one higher significant bit of the binary outputs as an elementary EXOR symmetric function of the binary inputs; wherein the logic circuit comprises elementary EXOR symmetric function logic for generating said elementary EXOR symmetric function of the binary inputs, the elementary EXOR symmetric function logic equating to at least one of: (i) the EXOR logic combination of the binary inputs and is high if and only if m≧1 and the number of high inputs is an odd number, (ii) the AND logic combination of sets of the binary inputs and the EXOR logic combination of the AND logic combinations and is high if and only if m≧k and the number of sets of high inputs is an odd number, where k is the size of the sets of binary inputs, each set being unique and the sets covering all possible combinations of binary inputs, or (iii) the AND logic combination of the binary inputs and is high if and only if all said binary inputs are high; wherein said elementary EXOR symmetric function logic is divided into a plurality of EXOR logic units, each EXOR logic unit is arranged to generate logic unit binary outputs as an elementary EXOR symmetric function of the binary inputs to the EXOR logic unit, the binary inputs of said plurality of inputs are divided into inputs to a plurality of said EXOR logic units, and at least one said higher significant bit of the binary outputs is generated using said logic unit binary outputs of a plurality of said EXOR logic units.