Patent ID: 8019039

Claim:
A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising: a pull-up unit, electrically connected to an Nth gate line of the gate lines, for pulling up an Nth gate signal of the gate signals according to a driving control voltage and a first clock; an input unit for inputting an (N−1)th gate signal generated by an (N−1)th shift register stage of the shift register stages to become the driving control voltage, wherein the input unit comprises a transistor having a first end electrically connected to the (N−1)th shift register stage for receiving the (N−1)th gate signal, a gate end for receiving a fourth clock, and a second end electrically connected to the pull-up unit; an energy-store unit, electrically connected to the pull-up unit and the second end of the transistor, for storing the driving control voltage; a discharging unit, electrically connected to the energy-store unit, for performing an alternate pull-down operation on the driving control voltage according to a second clock and a third clock; and a pull-down unit, electrically connected to the Nth gate line, for performing an alternate pull-down operation on the Nth gate signal according to the second clock and the third clock; wherein a high-level pulse of the first clock, a high-level pulse of the second clock, a high-level pulse of the third clock and a high-level pulse of the fourth clock are not overlapped to each other.