Patent ID: 7209192

Claim:
A thin film transistor array panel comprising: an insulating substrate; a gate line assembly formed on the insulating substrate with gate lines, and gate electrodes; a gate insulating layer covering the gate line assembly; a semiconductor pattern formed on the gate insulating layer; a data line assembly formed on the gate insulating layer overlaid with the semiconductor pattern, the data line assembly having data lines crossing over the gate lines, source electrodes connected to the data lines, and drain electrodes facing the source electrodes; storage capacitor electrode lines formed between the neighboring data lines while crossing over the gate lines; a passivation layer covering the data line assembly, the storage capacitor electrode lines and the semiconductor pattern while bearing contact holes exposing the drain electrodes; and pixel electrodes formed on the passivation layer while being connected to the drain electrodes through the contact holes, the pixel electrodes being overlapped with the storage capacitor electrode lines, wherein the storage capacitor electrode lines receive common electrode voltages and wherein the storage capacitor electrode lines are parallel with the data lines and are formed in the same layer as the data lines.