Patent ID: 8291257

Claim:
In a data processing system having a plurality of phase-locked loops coupled to a master clock, each of the plurality of phase-locked loops providing a respective clock signal to respective clocked circuitry, a method to compensate for injection locking comprising: (a) turning on at least two of the plurality of phase-locked loops; (b) setting a dynamically variable delay circuit that is between the master clock and one of the at least two of the plurality of phase-locked loops to have a predetermined value of delay, the dynamically variable delay circuit having a plurality of delay values; (c) measuring performance of at least one of the plurality of phase-locked loops by using the plurality of delay values to provide a plurality of performance values; (e) determining a center of a quiet zone of phase difference between clocks of the at least two of the plurality of phase-locked loops; (f) adjusting, if necessary, a currently selected temporary delay value for the one of the at least two of the plurality of phase-locked loops to an adjusted new temporary delay value that corresponds to substantially the center of the quiet zone; and (g) during operation of the data processing system, turning off the at least two of the plurality of phase-locked loops and repeating (a) through (f).