Patent ID: 7886207

Claim:
An integrated circuit comprising: a plurality of logic circuits comprising: a first logic circuit having a first logic depth, number of gates, number of gate inputs and number of gate outputs; a second logic circuit having a second logic depth, number of gates, number of gate inputs and number of gate outputs; and a scan chain configured to test the plurality of logic circuits, the scan chain comprising: a first scan chain portion configured to test the first logic circuit based on a scan input test pattern applied thereto and output a first output test pattern; a second scan chain portion configured to test the second logic circuit based on the first output test pattern and output a second output test pattern; and a switching unit configured to select and output one of the first output test pattern and the second output test pattern as a scan output test pattern based on at least one of differences between the first and second logic depths, first and second numbers of gates, first and second numbers of gate inputs and first and second numbers of gate outputs.