Patent ID: 8659944

Claim:
A memory device, comprising: an integrated circuit substrate; a plurality of stacks of semiconductor material strips on the integrated circuit substrate, the plurality of stacks being ridge-shaped and including at least two semiconductor material strips separated by insulating material into different plane positions of a plurality of plane positions; a plurality of word lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the plurality of stacks and the plurality of word lines; memory elements in the interface regions, which establish a 3D array of memory cells accessible via the plurality of semiconductor material strips and the plurality of word lines, the memory cells arranged in strings between bit line structures and source lines, wherein the strings are NAND strings; and diodes coupled to the strings, between ends of the strings of memory cells and one of the bit line structures and the source lines.