Patent ID: 7890684

Claim:
A system comprising: a bus; a plurality of slave devices coupled to the bus; and a master device coupled to the plurality of slave devices via the bus and configured to generate a global clock; wherein the master device is configured to initiate a bus transaction comprising an outbound phase and an inbound phase; wherein the master device is configured to transmit and receive data clocked on the global clock and wherein the master device is further configured to transmit data over the bus to one or more of the plurality of slave devices, during the outbound phase of the bus transaction, at a rate of one bit per clock cycle of the global clock; wherein one or more of the plurality of slave devices is configured to receive and transmit data clocked on the global clock and wherein one or more of the plurality of slave devices is further configured to transmit data over the bus to the master device, during the inbound phase of the bus transaction, at a rate of one bit per N consecutive clock cycles of the global clock, where N is an integer greater than or equal to 2.