Patent ID: 8130570

Claim:
A data transfer circuit which transfers data from a first clock domain operating with a first clock to a second clock domain operating with a second clock different from the first clock, the circuit comprising: an asynchronous memory to which transfer data is written from the first clock domain with the first clock and from which the written transfer data is read to the second clock domain with the second clock; a scan flip-flop whose input terminal is connected to a first position located on a data path, of the transfer data, from the asynchronous memory to the second clock domain, and whose output terminal is connected to a second position located on a data path, of the transfer data, from the asynchronous memory to the first position; and a clock selector which selects a clock to drive the scan flip-flop from the first clock and the second clock, wherein a memory BIST is performed with the first clock on a data path from the asynchronous memory through the first position to the scan flip-flop by causing the clock selector to select the first clock, and a scan test is performed with the second clock on a data path from the scan flip-flop through the second position and the first position to the second clock domain by causing the clock selector to select the second clock.