Patent ID: 7952902

Claim:
A content addressable memory for receiving an input data, a pattern data and a data clock signal and outputting a hit signal and an address signal, the content addressable memory comprising: a plurality of content addressable memory units connected in series, each said content addressable memory unit being adapted to receive said input data and said data clock signal and to output a comparison result signal; and an encoder coupled to the comparison result signal of each of said content addressable memory units and adapted for outputting a hit signal and a memory address signal subject to the comparison result signal received; wherein each said content addressable memory unit comprises a first register for storing a set data of the respective content addressable memory; a plurality of storage and compare modules, a first one of said storage and compare module being coupled to the output end of said first register, each said storage and compare module being adapted for storing a pattern data and comparing the pattern word to the input data and then outputting a comparison result; a first multiplexer, said first multiplexer comprising a first input end coupled to the data output end of said first register, a second input end coupled to a carry input signal, and a selection input end coupled to a cascade control input signal; a plurality of AND gates, each said AND gate comprising a first input end coupled to the comparison result output end of one said storage and compare module, a first one of said AND gate comprising a second input end coupled to the output end of said first multiplexer; a plurality of flip-flops connected in series by means of said AND gates, each said flip-flop comprising a data input end coupled to the output end of one said AND gate and a data output end coupled to the second input end of one said AND gate; and a second multiplexer, said second multiplexer comprising a selection input end coupled to the cascade output signal, and a plurality of input ends respectively coupled to the data output ends of said flip-flops.