Patent ID: 7930608

Claim:
An integrated circuit for testing electronic components, comprising: a plurality of clock buffers and a plurality of latches synchronously operated in accordance with operating clock signals distributed via the clock buffers; a testing mechanism for performing an At Speed Test to shift data that are initially set for the latches in accordance with the operating clock signals to succeeding latches, respectively; a timing designation circuit for generating a first output signal pulse that remains active for a predetermined period and enabling a clock signal pulse generated after said first output signal has been generated but during said period when said first output signal pulse is still active; and a current consumption circuit including a ring-type oscillator including a plurality of components, each component having an output connected to an input of the next component in the ring and each component being arranged to produce an output which is inverted in relation to the input thereto, the oscillator being provided in correspondence with each of at least a part of the plurality of clock buffers, the oscillator being operable to consume a certain amount of current in the period during which the first output signal is active, the ring-type oscillator including a delay control input terminal, the oscillation cycle of the ring-type oscillator being selectively adjusted by adjusting an input of the delay control input terminal.