Patent ID: 7154784

Claim:
A flash memory device comprising: a memory cell array including memory cells connected to pluralities of bitlines; page buffer circuits correspondingly connected to bitline pairs with a predetermined number among the plural bitlines, sequentially storing sensing data bits corresponding to read data bits received through at least a portion of the bitline pairs with the predetermined number in response to one of transfer control signals and a latch control signal during a read operation, and sequentially outputting the stored data bits to one of internal input/output lines in response to one of the transfer control signals; Y-gate circuits correspondingly connected to the page buffers through the internal input/output lines, each connecting or disconnecting one of the internal input/output lines with a data input/output line in response to one of input/output control signals; and a Y-decoder generating the transfer control signals and the input/output control signals in response to column address signals, a read command or a program command.