Patent ID: 7834437

Claim:
A semiconductor package comprising: a plate having first via patterns formed on a center portion and second via patterns formed on edge portions; a connection wiring formed on a top surface of the plate to connect directly at least one first via pattern to at least one second via pattern; a plurality of passive elements formed on the top surface of the plate having the connection wiring formed thereon; a semiconductor chip having a plurality of bonding pads, the semiconductor chip being attached to a bottom surface of the plate opposite the top surface of the plate and electrically connected to the first via patterns; and a plurality of external connection terminals, each of which is attached to each of the second via pattern on the bottom surface of the plate, wherein the passive element comprises a plurality of first metal patterns formed with the connection wiring, an insulating film covering all of the first metal patterns and the connection wiring, and a plurality of second metal patterns formed on the top surface of the insulating film and spaced apart from the first metal patterns in a position corresponding to the first metal patterns, and wherein the plate is composed of a wafer having a thickness greater than that of the semiconductor chip.