Patent ID: 7526056

Claim:
In a delay locked loop circuit that includes a delay line configured to receive a clock signal and pass the clock signal through an adjustable number of delay elements, a phase detector circuit configured to sample a phase of a clock signal at an output terminal of the delay line and received at a feedback clock input of the phase detector and the clock signal received at a reference input of the phase detector, the phase detector configured to generate a first signal when the phase of the clock signal at the feedback clock input of the phase detector is not approximately equal to the phase of the reference clock signal at a reference input of the phase detector and the variance is in a first direction, wherein the phase detector is further configured to generate a second signal when the phase of the clock signal at the feedback clock input of the phase detector is not approximately equal to the phase of the reference clock signal at the reference input of the phase detector and the variance is in a second direction that is opposite the first direction, a method for adjusting the number of delay elements through which the clock signal passes in the delay line, the method comprising the following: when operating in an operational mode after pseudo-lock, an act of a filter receiving a first signal from the phase detector; an act of determining whether the reception of the first signal results in a predetermined number of multiple consecutive first signals being received from the phase detector; and an act of adjusting the adjustable number of delay elements through which the clock signal passes in the delay line if there has been the predetermined number of multiple consecutive first signals received from the phase detector without any intervening second signals being received from the phase detector; and an act of preventing adjustment of the adjustable number of elements through which the clock signal passes in the delay line if there has not been the predetermined number of multiple consecutive first signals received from the phase detector; and when operating in a reset mode before pseudo-lock, an act of allowing signals from the phase detector to adjust the number of delay elements through which the clock signal passes in the delay line without waiting for the predetermined number of multiple consecutive first signals or for the predetermined number of multiple consecutive second signals.