Patent ID: 7593282

Claim:
A memory core employing an open bit line architecture, comprising: a plurality of first bit lines; a plurality of second bit lines, the second bit lines having a complementary relationship with the first bit lines; a first sub-memory array having a plurality of first memory cells configured to output first data into the first bit lines in response to a first word line control signal; a second sub-memory array having a plurality of second memory cells configured to output second data into the second bit lines in response to a second word line control signal, the second data having a complementary relationship with the first data; a bit line amplification circuit configured to amplify the first data on the first bit lines and the second data on the second bit lines; and a column selection circuit including a first column selection transistor configured to electrically couple the first bit lines to a first input/output line in response to a column selection signal and a second column selection transistor configured to electrically couple the second bit lines to a second input/output line having a complementary relationship with the first input/output line, the first and second column selection transistors being arranged between the bit line amplification circuit and the first sub-memory array, each of the first and second column selection transistors including a first single contact formed on a source area of the first and second column selection transistors and a second single contact on a drain area of the first and second column selection transistors, the first single contact being connected to one of the first and second bit lines, the second single contact being connected to one of the first and second input/output lines.