Patent ID: 7863653

Claim:
A semiconductor device, comprising: an oxide layer over a first silicon layer; a second silicon layer over said oxide layer, wherein said oxide layer is between said first silicon layer and said second silicon layer; a spacer on said first silicon layer, wherein said spacer contacts said oxide layer, said first silicon layer, and said second silicon layer; a graded germanium layer on said first silicon layer, wherein said graded germanium layer contacts said spacer and said first silicon layer, and wherein a lower portion of said graded germanium layer comprises a higher concentration of germanium than an upper portion of said graded germanium layer; an n-type field effect transistor over said second silicon layer; a p-type field effect transistor over said graded germanium layer; and a third silicon layer over said graded germanium layer, wherein said third silicon layer is between said graded germanium layer and said p-type field effect transistor, wherein said oxide layer is only below said n-type field effect transistor and is not below said p-type field effect transistor, wherein said third silicon layer comprises strained pseudomorphic silicon, wherein said strained pseudomorphic silicon comprises a layer of single-crystal silicon, and wherein said third silicon layer is a lattice-mismatched heterostructure.