Patent ID: 6970977

Claim:
A multiprocessor write-into-cache data processing system comprising: A) a memory; B) at least first and second shared caches; C) a system bus coupling said memory and said first and second shared caches; D) at least first, second, third and fourth processors having, respectively first, second, third and fourth private caches; E) said first and second private caches being coupled to said first shared cache by a first internal bus, and said third and fourth private caches being coupled to said second shared cache by a second internal bus; F) a gateword stored in said memory, the gateword governing access to common code/data shared by processes running in a plurality of said processors; G) means for each given processor to read and test the gateword by performing successive swap operations between said memory and said given processor's shared cache and between said given processor's shared cache and private cache; H) means for a first given processor finding the gateword stored in memory OPEN to write the gateword CLOSEd in its private cache, and, thereafter, successive swap operations are carried out between: 1) the first given processor's private cache and the first given processor's shared cache; and 2) the first given processor's shared cache and memory to flush the first given processor's shared cache of a block containing the gateword and thereby write the gateword CLOSEd in memory; I) means, when said first given processor completes use of the common code/data governed by the gateword, writing said gateword OPEN in its private cache, and, thereafter, successive swap operations are carried out between: 1) the first given processor's private cache and the first given processor's shared cache; and 2) the first given processor's shared cache and memory to flush the first given processor's shared cache of the block containing the gateword and thereby write the gateword OPEN in memory.