Patent ID: 8014212

Claim:
A semiconductor device comprising: a plurality of columns of bit line pairs, each bit line pair including True and Bar bit lines, between which at least a memory cell is connected; a sense amplifier that includes True and Bar terminals and that performs differential amplification; a switching circuit that selects one out of: a straight connection in which the True and Bar bit lines of a selected column bit line pair are connected to the True and Bar terminals of the sense amplifier, respectively, and a cross connection in which the True and Bar bit lines of a selected column bit line pair are connected to the Bar and True terminals of the sense amplifier, respectively; and an IO (input/output) line pair for the plurality of columns of bit line pairs, the IO line pair including True and Bar IO lines, the True and Bar terminals of the sense amplifier being connected to True and Bar IO lines, respectively, wherein: a bit line pair of a selected column among the plurality of columns of bit line pairs is connected to the IO line pair via a column selection circuit that is in an on state, and the switching circuit is arranged on the IO line pair between connection portions of the IO line pair and column selection circuits provided for the plurality of columns and connection nodes of the IO line pair and the True and Bar terminals of the sense amplifier.