Patent ID: 7068546

Claim:
An integrated memory, comprising: a memory cell array, the memory cell array having word lines for selecting memory cells and bit lines for reading out or writing data signals; a read/write amplifier, the read/write amplifier being connected to the bit lines for assessing and amplifying data signals; and a voltage generator circuit, including a first capacitor, a first transistor with a first terminal connected to an electrode of the first capacitor and a second terminal connected to a first supply potential, a second transistor with a first terminal connected to the electrode of the first capacitor and a second terminal connected to a first terminal of the read/write amplifier, and a pulse shaper connected to a control terminal of the first transistor and a control terminal of the second transistor, the pulse shaper controlling the first and second transistors such that the first transistor operates as an open switch and the second transistor operates as a closed switch for a predetermined period of time during an assessment and amplification operation of the read/write amplifier.