Patent ID: 7288442

Claim:
A method for manufacturing a thin film transistor (TFT) array panel, comprising steps of: depositing a first conductive layer formed of aluminum or aluminum alloy material on a substrate; patterning the first conductive layer to form a gate line and a gate pad connected to the gate line; depositing an insulating layer on the gate line and the gate pad; forming a semiconductor layer on the insulating layer; depositing a second conductive layer on the semiconductor layer; patterning the second conductive layer to form a data line; forming a contact hole extending through the insulating layer and exposing the aluminum or aluminum alloy material of the gate pad; performing an annealing process; depositing using a sputtering process a third conductive layer formed of an indium zinc oxide (IZO) layer; and patterning the third conductive layer to form a conductive pattern directly contacting the aluminum or aluminum alloy material of the gate pad in the contact hole, wherein the sputtering process is performed at a temperature below 200° C., wherein the annealing process is performed immediately before depositing the third conductive layer.