Patent ID: 7268386

Claim:
A nonvolatile semiconductor memory comprising: a plurality of stripe-shaped active regions extending in a bit line direction; device isolation regions having tops thereof arranged at a location higher than the active regions; a plurality of word lines and select gate lines intersecting with the bit line direction; and memory cell transistors arranged at the intersections of the active regions and the word lines via gate insulator films, comprising floating gate electrodes formed on the device isolation regions and gate insulator films on the active regions, and isolated on the device isolation regions, control gate electrodes arranged on the floating gate electrodes, and inter-gate insulator films arranged between the control gate electrodes and the floating gate electrodes; wherein the thickness of the floating gate electrodes on the active regions and a maximum thickness of the floating gate electrodes on the device isolation regions are substantially the same, and steps are provided at the edges of the floating gate electrodes isolated on the device isolation regions, the floating gate electrodes have steps half the maximum thickness of the floating gate electrodes, and the steps at the edges of the floating gate electrodes isolated on the device isolation regions have a length in a direction parallel to the word lines for the floating gate electrodes which is greater than the thickness of the inter-gate insulator films.