Patent ID: 7633803

Claim:
A method of operating a memory device including a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor wherein the string selection transistor is coupled between the string and a bitline and wherein the ground selection transistor is coupled between the string and a common source line, the method comprising: selecting one of the plurality of memory cell transistors in the string as a selected memory cell transistor for a program operation so that other memory cell transistors in the string are unselected; during the program operation, applying a plurality of negative voltage pulses to a channel region of the selected memory cell transistor; while applying the plurality of negative voltage pulses to the channel region, applying a positive pass voltage to control gate electrodes of the unselected memory cell transistors; and while applying the plurality of negative voltage pulses to the channel region, applying a positive program voltage to a control gate electrode of the selected memory cell.