Patent ID: 8856426

Claim:
A memory device comprising: a first circuit configured to perform data recording for storing; and a second circuit configured to perform data transfer control to allow the first circuit to perform data recording and data reproduction, wherein the first circuit and the second circuit are separately implementable, and wherein the first circuit includes: a data recording circuit configured to read recorded data from an address appointed by an address signal when a read/write signal stays at a first level, and configured to write data to the address appointed by the address signal when the read/write signal stays at a second level; a write/read control circuit configured to perform data write/read control on the data recording circuit according to the address signal in response to a read or write instruction from the second circuit; and a read control circuit configured to transfer data read from the data recording circuit to the second circuit through a first path different from a second path through which the write/read control circuit is configured to transfer data.