Patent ID: 8564323

Claim:
A circuit arrangement for testing a reset circuit, the circuit arrangement comprising: a reset circuit, comprising, a voltage input for feeding an input voltage, and an output for providing a reset signal as a function of the input voltage; a changeover switch, comprising, a first input for feeding a test voltage, a second input for feeding a supply voltage, a control input for changing over between the first and the second input as a function of a test adjustment signal, and an output that is coupled to the voltage input of the reset circuit; an output logic circuit, comprising, a first input, coupled to the output of the reset circuit, a second input for feeding the test adjustment signal, a first output for providing a system reset signal as a function of the reset signal and the test adjustment signal, and a second output for providing a result signal as a function of the reset signal and the test adjustment signal; and an input logic circuit, comprising, a first input, coupled to the first output of the output logic circuit, a second input for feeding a data signal, and an output for providing the test adjustment signal and coupled to the control input of the changeover switch and the second input of the output logic circuit.