Patent ID: 8755466

Claim:
A receiver comprising: a mixer configured to mix a received signal in a receive path with an oscillation signal; an oscillator configured to output the oscillation signal as a base signal, which oscillates at a base frequency B; a clock generation device configured to generate at least one clock signal from the base signal, whose input is connected to the output of the oscillator, the clock generation device comprising a frequency divider, which is formed to divide the base frequency by a factor F=x+A to generate a clock signal, where x is a positive whole number and A is approximately 1/2 and wherein the clock signal has a frequency of approximately B/(x+½); and at least one signal processing device configured to process the output of the mixer in the receive path based on the clock signal generated by the frequency divider; wherein the base signal comprises an in-phase signal and a quadrature-phase signal, the in-phase signal and the quadrature-phase signal having the same base frequency, wherein the frequency divider is configured to count alternately edges of the in-phase signal and of the quadrature-phase signal, to increase or decrease a counter state M for each counted edge, and wherein the frequency divider is further configured to generate a rising or falling edge at the counter state of M=2m+1, where m is a predefined positive whole number.