Patent ID: 7969806

Claim:
An integrated circuit, comprising: a plurality of memory segments each comprising at least one memory cell that is configurable in at least first and second states to store data, wherein an erased memory segment includes no memory cells in the first state and a programmed memory segment includes at least one memory cell in the first state; and a controller configured to control programming and erasing of memory segments, wherein the controller is configured to: map an external memory address of write data to an internal memory address of an erased memory segment such that the erased memory segment is programmed with the write data; remap the external memory address to a second internal memory address of an erased memory segment in response to a write access for an external memory address previously mapped to a first internal memory address of a programmed memory segment; and identify for erasure the programmed memory segment associated with the first internal memory address and control selective erasure of the identified programmed memory segment.