Patent ID: 8530903

Claim:
A FET, comprising: a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer; first and second finger arrays, each of the finger arrays including a source, gate and drain electrode located over the barrier layer and extending in a longitudinal direction thereon, wherein a portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source electrode of the first finger array extends beyond a first edge of the mesa and the source electrode of the second finger array extends beyond a second edge of the mesa and wherein the gate electrode of the first finger array extends along a first edge sidewall of the mesa and the gate electrode of the second finger array extends along a second edge sidewall of the mesa; first and second conductive source interconnects disposed over the buffer layer, each conductive source interconnect having a first end electrically connected to the source electrode of one of the finger arrays; a first dielectric layer disposed over the buffer layer and under the first and second conductive source interconnects; first and second sets of conductive gate nodes extending along the buffer layer, each set being electrically connected to the portion of one of the gate electrodes extending along one of the sidewalls of the mesa; first and second gate pads disposed on the second dielectric layer and adjacent to opposing sides of the mesa; first and second conductive gate connect strips each located over a conductive gate node and in contact therewith, each of said conductive gate connect strips being in electrical contact with the a respective one of the gate pads; first and second source pad vias formed in the first dielectric layer; and first and second source pads each formed in a respective one of the source pad vias, the first and second conductive source interconnects each having a second end, the second ends of the first and second conductive source interconnects being in electrical contact with the first and second source pads, respectively.