Patent ID: 7693700

Claim:
A method of simulating an integrated circuit comprising: receiving a first model of a first circuit portion; converting the first model of the first circuit portion to a second model of the first circuit portion, the second model comprising a plurality of electrical components having a first set of values, the second model having a circuit topology; receiving a first input waveform having by a second set of values; defining a first multidimensional data point that includes the first set of values and the second set of values; determining a first output waveform corresponding to the first multidimensional data point by interpolating a plurality of multidimensional data points including a second multidimensional data point and a third multidimensional data point, thereby obtaining the first output waveform corresponding to the second model and the first input waveform; determining a delay using the first output waveform; annotating a netlist with the delay; and providing the annotated netlist, wherein the second multidimensional data point comprises a second set of input parameters representing: a third model of a second circuit portion comprising a plurality of electrical components having the circuit topology, a second input waveform, and a second output waveform, and wherein the third multidimensional data point comprises a third set of input parameters representing: a fourth model of a third circuit portion comprising a plurality of electrical components having the circuit topology, a third input waveform, and a third output waveform.