Patent ID: 7042094

Claim:
A structure for connecting stacked conductive components of an integrated chip, comprising: a first conductive layer; a second conductive layer in a substantially parallel plane with said first conductive layer; a first dielectric layer formed between said first and second conductive layers; a third conductive layer in a substantially parallel plane with said second conductive layer; a second dielectric layer formed between said second and third conductive layers; a first via structure formed in said first dielectric layer and substantially perpendicular to said first and second conductive layers for providing a conductive path therebetween, the first via structure including a plurality of vias defining a first group of vias and arranged in a first area; and a second via structure formed in said second dielectric layer and substantially perpendicular to said second and third conductive layers for providing a conductive path therebetween and arranged such that portions of said second via structure lie outside an area defining said first via structure, the second via structure including a plurality of vias defining a second group of vias and arranged in a second via area, the first via area and the second via area having a substantially similar oblong shape with a major dimension, the centers of the oblong shapes being substantially aligned and the major axis of the first via area being offset by approximately 90 degrees to the major axis of the second via area such that only portions are overlapping and forming a crisscross pattern.