Patent ID: 7299447

Claim:
A method of testing a mapping, present on a computer system, of an electrical circuit that is actuatable with instruction sets, wherein: the electrical circuit has a closed instruction space and a plurality of memory cells, and the circuit is described by a reference model having a plurality of states and a plurality of state transitions; at least one of an acceptable instruction set for each state and an unacceptable instruction set for each state is predefined, an instruction set having an input vector and an output data item, whereby for each input vector of an instruction set there is reached, starting from a respectively present state, a subsequent state and an output data item is generated; the mapping of the electrical circuit is configured, upon receiving an acceptable instruction set as a data input, to allow a state transition into a subsequent state of the mapping and to output the generated output data item, and, upon receiving an unacceptable instruction set as a data input, to issue a fault message; the states and the state transitions of the mapping corresponding to the states and the state transitions of the reference model; and instruction sets are generated with specific probabilities and applied to the mapping of the electrical circuit, the instruction sets being either acceptable instruction sets or unacceptable instruction sets, an unacceptable instruction set having a combination of input signals, being not related to an instruction, or having commands being applied at a time, at which the commands are not allowed; the method which comprises the following steps: a) initializing the mapping of the electrical circuit to be tested; b) selecting a region of the mapping of the electrical circuit to be tested; c) writing initial data into the mappings of the memory cells of the region selected in step b); d) generating a sequence of acceptable instruction sets using the reference model; e) applying the instruction sets generated in step d) as an input vector for the mapping to test the region of the mapping selected in step b); f) generating an unacceptable instruction set using the reference model; g) applying the unacceptable instruction set as an input vector for the mapping to test the region of the mapping selected in step b); h) checking whether the mapping of the electrical circuit supplies a fault message; i) repeating steps f) to h) for further unacceptable instruction sets; j) repeating steps c) to i) until sufficient precision of the testing is achieved; and k) repeating steps b) to j) for further regions of the mapping of the electrical circuit to be tested.