Patent ID: 6847098

Claim:
A semicondutor device on a semiconductor substrate, comprising: a silicon alloy on said semiconductor substrate; insulator filled openings in a top portion of said silicon alloy layer, with portions of said insulator filled openings recessed at edge of said insulator filled openings; a strained silicon shape comprised with a first segment of strained silicon shape overlying a portion of said silicon alloy layer located between said insulator filled openings, and comprised of attached second segments of said strained silicon shape located on top surface of recessed portions of said insulator filled openings, with the top surface of said strained silicon shape level with the top surface of non-recessed portions of said insulator filled openings; first insulator spacers on the sides of said strained silicon shape, embedded in said insulator filled openings; a gate insulator layer on a top surface of said strained silicon shape; a conductive gate structure on said gate insulator layer in an area in which said gate insulator layer overlays a portion of said first segment of strained silicon shape; second insulator spacers on the sides of said conductive gate structure; a lightly doped source/drain region in a portion of said strained silicon shape not covered by said conductive gate structure, with said lightly doped source/drain region equal in depth to the thickness of said strained silicon shape; and a heavily doped source/drain region in a portion of said strained silicon shape not covered by said conductive gate structure or by said second insulator spacers with said heavily doped source/drain region equal in depth to the thickness of said strained silicon shape.