Patent ID: 7528757

Claim:
A circuit for generating a set of intermediate voltages between two reference voltages, said circuit comprising two input ports for feeding two reference voltages, wherein the intermediate voltages are generated by a number of self calibration units that correspond to the number of intermediate voltages to be generated, wherein each self calibration unit receives the voltages of the neighboring calibration units or the voltage of one neighboring calibration unit and one of the reference voltages, and wherein each self calibration unit comprises: an error amplifier for providing an error voltage, a comparator for providing an up/down signal when the error voltage exceeds a positive or a negative voltage level, an up/down counter working as an integrator and counting an internal count one up or one down depending on the up/down signal received from the comparator, a digital-analog-converter for converting the digital signal received from the up/down counter into an analog signal, and a clock signal generator for providing clock signals for the error amplifier and the up/down counter.