Patent ID: 7855417

Claim:
A non-volatile memory, comprising: a silicon on insulation (SOI) substrate, comprising a first conductive type silicon body layer; a memory cell, disposed on the SOI substrate, the memory cell comprising: a gate, longitudinally disposed on the SOI substrate; a charge storage structure, disposed between the gate and the SOI substrate; a bottom dielectric layer, disposed between the charge storage structure and the SOI substrate; a top dielectric layer, disposed between the charge storage structure and the gate; a second conductive type drain region disposed in the first conductive type silicon body layer at one lateral side of the gate; and a second conductive type source region disposed in the first conductive type silicon body layer at another lateral side of the gate; and a first conductive type doped region, disposed in the first conductive type silicon body layer, and electrically connected to the first conductive type silicon body layer beneath the gate, wherein the first conductive type doped region and the second conductive type source region are disposed at the same lateral side of the gate and are juxtaposedly arranged along a longitudinal direction of the gate.