Patent ID: 7977662

Claim:
An integrated circuit memory device, comprising: a non-volatile memory array having an array of phase-changeable memory elements therein that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements, said first electrically insulating region comprising: a silicon nitride layer covering the array of phase-changeable memory elements and directly contacting sidewalls thereof, said silicon nitride layer having an undulating surface profile with peaks and valleys thereon; and a silicon oxide layer on the silicon nitride layer, said silicon oxide layer extending into the valleys in the undulating surface profile and including an array of voids therein that are separated from sidewalls of the phase-changeable memory elements by said silicon oxide layer; and wherein each of the voids in said array of voids is located within a valley in the undulating surface profile at a position about equidistant between a corresponding pair of the phase-changeable memory elements.