Patent ID: 7751247

Claim:
An apparatus comprising: a circuit for trimming a reference voltage including a resistor dividing a drain voltage, a flash memory resistor including a flash memory, an NMOS transistor turning on/off a drain of the flash memory, and an amplifier comparing the reference voltage and a node voltage, wherein the resistor includes one end connected to a V node, the NMOS transistor has a drain connected to the V node and a source connected to the drain of the flash memory, the flash memory includes the drain connected to the source of the NMOS transistor, a source connected to a system voltage, and a gate connected to a drain voltage, and the amplifier is connected to the V node to receive the node voltage; an NMOS gate switch turning on/off the NMOS transistor; a flash cell gate switch switching the gate voltage of the flash memory when the flash memory is in at least one of program, erase, and resistance states; a flash cell source switch switching a source voltage of the flash memory for the erase operation of the flash memory; and a flash cell drain switch switching the drain voltage of the flash memory for the program operation of the flash memory.