Patent ID: 6936866

Claim:
A vertical semiconductor component, comprising: a substrate of a first conductivity type having a first and a second side; an insulating layer covering said first side and having a side remote from said substrate; a more highly doped layer of the first conductivity type applied on said second side; a metallic drain contact applied on said more highly doped layer; a metallic gate contact; a multiplicity of MOS cells on said first side of said substrate for forming a first semiconductor switch, each MOS cell having: a first well of the second conductivity type, said first well being introduced into said substrate and reaching said first side; a first metallic source contact extended through said insulating layer; a first source region of the first conductivity type being incorporated into said well and having a potential, reaching to said first side of said substrate, and connecting to said first metallic source contact; a first gate on said side of said insulating layer remote from said substrate, said first gate partly covering said well and connecting to said metallic gate contact; a plurality of further MOS cells identical to said multiplicity of MOS cells, said further MOS cells having a second well, a second source region having a potential, a second gate on said first side of said substrate for forming a second semiconductor switch; and a second source contact electrically insulated from said first source contact and extending through said insulating layer; said second source regions of said further MOS cells connected to said second source contact on said first side; and a region of the second conductivity type being incorporated into said substrate, reaching to said first side, and electrically connecting to said second gate of said further MOS cells, said region having a potential floating relative to the potential of the first and second source regions of said MOS cells and further MOS cells.