Patent ID: 7463541

Claim:
A semiconductor storage device comprising: information memory cells; a plurality of memory cell arrays including the information memory cells arranged in a matrix; information word lines connected to the information memory cells; bit lines connected to the information memory cells; reference memory cells, each of which is provided for a pair of bit lines and is connected to one bit line of the pair, all reference memory cells storing a same digital data; average transistors connected between the pair of the bit lines, the average transistors connecting the pair of the bit lines with each other when a reference data is generated, the reference data having a middle potential between a potential of a bit line transmitting a first data and a potential of a bit line transmitting a second data; and sense amplifiers respectively connected to two bit lines included respectively in two memory cell arrays, one of the sense amplifiers being connected to one of the information memory cells included in one of the two memory cell arrays via one of the two bit lines and being connected to the reference memory cell included in the other memory cell array via the other bit line when a data is read out from one of the information memory cells, the sense amplifiers using the reference data.