Patent ID: 7087997

Claim:
An integrated circuit including a patterned copper layer, a patterned aluminum layer, an opening in a layer of material, said opening extending between a location on said patterned copper layer and a location on said patterned aluminum layer, a multi-layer barrier liner in said opening and having a thickness, said barrier liner extending between said patterned aluminum layer and said patterned copper layer at said location on said patterned copper layer and across said copper layer to cover a bottom of said opening, said multi-layer barrier layer including at least a first layer being of a material which is conductive and having adhesion to copper and tungsten comparable to that of tantalum or tantalum nitride or titanium nitride and resisting interdiffusion of copper and tungsten and a second layer formed on said first layer and being of a material which assists in the formation of a stud during deposition of tungsten on which tungsten can be deposited, one or both of said first and second layers forming a conductive barrier to process materials which are reactive with copper, and a stud connection formed of tungsten and located within said barrier liner wherein said barrier liner comprises a layer of tantalum nitride, and a layer of PVD tungsten.