Patent ID: 7052954

Claim:
A method of fabricating a semiconductor device comprising steps of: (a) forming a gate electrode presenting a MOS structure on a semiconductor substrate; (b) after step (a), forming a first conductive layer on said gate electrode with a single element material or only a metal material; (c) after step (b), patterning said first conductive layer; and (d) after step (c), forming a second conductive layer on said first conductive layer, wherein said step (c) includes a step of: (c-1) patterning said first conductive layer in a manner to provide for dividing the first conductive layer into a first part connected to said gate electrode and a second part to be connected by contacting said second conductive layer, said method further comprising a step of: (e) forming an interlayer insulating film configured to intervene between said first part and said second conductive layer between said steps (c) and (d).