Patent ID: 7206950

Claim:
A processor system including a plurality of processors characterized by comprising: assignment controlling means for reading instructions to be executed by the respective processors and for controlling assignments of the instructions to the processors; and clock controlling means for controlling the frequencies of clock signals to be supplied to the respective processors, in accordance with the instructions to be executed by the processors according to the assignments, wherein the assignment controlling means includes: instruction analyzing means for analyzing whether the instructions are executable by the respective processors and for analyzing constraints on the timings of executing the respective instructions; execution period estimating means for estimating execution periods reciuired of the respective processors to execute the instructions; and assignment determining means for determining assignments of the instructions to the processors based on a result of the analysis and the estimated execution periods such that if one of the instructions is executable by two or more of the processors, said one of the instructions is assigned to one of the processors which exhibits the shortest execution period for executing the instruction, wherein the assignments of the instructions to the processors are controlled in accordance with the determination by the assignment determining means.