Patent ID: 7701248

Claim:
A storage element for controlling a logic circuit, said storage element comprising: a first floating gate flash memory transistor of a first conductivity type, said first floating gate flash memory transistor having a first region and a spaced apart second region, each region being of a second conductivity type with a channel region of the first conductivity type therebetween; a floating gate is spaced apart from a first portion of the channel region and is adjacent to the first region; a coupling gate is over the floating gate and is capacitively coupled thereto; a control gate is adjacent to and spaced apart from the floating gate and the coupling gate, said control gate is spaced apart from another portion of the channel region and has a portion adjacent to the second region; an erase gate is over the first region and is spaced apart therefrom and spaced apart from the floating gate and the coupling gate; a second floating gate flash memory transistor of the first conductivity type, said second floating gate flash memory transistor has a first region and a spaced apart second region, each region being of the second conductivity type with a channel region of the first conductivity type therebetween; a floating gate is spaced apart from a first portion of the channel region and adjacent to the first region; a coupling gate is over the floating gate and is capacitively coupled thereto; a control gate is adjacent to and spaced apart from the floating gate and the coupling gate, said control gate is spaced apart from another portion of the channel region and has a portion adjacent to the second region; an erase gate is over the first region and is spaced apart therefrom and spaced apart from the floating gate and the coupling gate; wherein the second region of the first floating gate flash memory transistor is electrically connected to the second region of the second floating gate flash memory transistor, and provides a storage output; and a switch having an input, two outputs, and a switch input for receiving the storage output at the input, and for supplying a signal to one of the two outputs in response to the switch input, wherein said one output being coupled to the logic circuit.