Patent ID: 6867085

Claim:
A method of manufacturing an insulated gate semiconductor device, said method comprising: forming a resist over a crystal semiconductor comprising a part to become a channel forming region; forming a dotted hole in said resist by patterning said resist using electron drawing method or FIB method; forming an intrinsic or substantially intrinsic region and impurity regions in said part to become the channel forming region by introducing a first impurity into said channel forming region through said resist having said dotted hole, said first impurity being selected from the group consisting of carbon, nitrogen and oxygen; and introducing into said crystal semiconductor a second impurity that gives one conductivity to form a source region and a drain region in said crystal semiconductor with said channel forming region therebetween, wherein said impurity regions have total width of Wpi in a direction of a channel width W, and a total width of said intrinsic or substantially intrinsic region is Wpa in said direction of said channel width W, where Wpi/W=0.1 to 0.9 and Wpa/W=0.1 to 0.9, and wherein said source region and said drain region and said channel forming region are provided in a transistor of at least one selected from the group consisting of an arithmetic operating section, a memory section, a DRAM circuit and an SRAM circuit.