Patent ID: 6992926

Claim:
A driver circuit for a semiconductor storage device, the driver circuit driving a memory array which includes a plurality of memory elements, wherein: each memory element includes: a gate electrode; a semiconductor layer; a gate insulating film sandwiched between the gate electrode and the semiconductor layer; a channel region provided under the gate electrode; diffusion regions respectively provided on two sides of the channel region, the diffusion regions being of the other conductivity type than the channel region; and memory functioning members respectively provided on two sides of the gate electrode, the memory functioning members having a function of holding charges therein, and the driver circuit includes: an output driver, connected to a node, for driving a word line of the memory array, wherein the node is set to a potential for controlling operation of the driver circuit; a first transistor connected between the node and a power source, and a second transistor connected between the node and a wire returned to the power source, one of the first transistor and the second transistor being activated, during reading operation, in accordance with a read control signal supplied to its gate; a plurality of writing/erasing transistors connected in series between the node and the wire returned to the power source, the plurality of writing/erasing transistors being activated in accordance with a writing/erasing control signal, the first transistor being activated during writing/erasing period so as to operate together with the writing/erasing transistors, in order to control output supplied from the output driver.