Patent ID: 7043574

Claim:
A computer system comprising: at least one pair comprising a first processor connected to a first input/output unit, and a second processor connected to a second input/output unit, wherein the first processor is connected to the first input/output unit via two data transmitting routes and the second processor is connected to the second input/output unit via said two transmitting routes, wherein said first or second processor sends a frame, which is included in data, to said first or second input/output unit, respectively via one of said two data transmitting routes and simultaneously sends the frame via another of said two data transmitting routes; and wherein said first or second input/output unit sends a frame, which is included in data, to said first or second, processor, respectively via one of said two data transmitting routes and simultaneously sends the frame via another of said two data transmitting routes; and said first or second input/output unit or said first or second processor receives the same frames via one of said two data transmitting routes and via the other of said data transmitting routes, and accepts either of the same frames based on the order in which said frames were received.