Patent ID: 7405439

Claim:
A memory cell structure, comprising: a first memory capacitor arranged in a local area and comprised of a first lower electrode, a first upper electrode, and a first dielectric oxide film interposed between the first lower electrode and the first upper electrode; a second memory capacitor arranged in the local area, spaced apart from the first memory capacitor, and comprised of a second lower electrode, a second upper electrode, and a second dielectric oxide film interposed between the second lower electrode and the second upper electrode; a local interconnection layer that is electrically conductive and impermeable to hydrogen, extends within the local area, and is comprised of a first contact portion that is in contact with the first upper electrode and spaced apart from the first dielectric oxide film by the first upper electrode, a second contact portion that is in contact with the second upper electrode and spaced apart from the second dielectric oxide film by the second upper electrode, and a non-contact portion that connects the first contact portion to the second contact portion and is spaced apart from the first and second memory capacitors; and a hydrogen barrier layer that is electrically conductive and impermeable to hydrogen, and covers at least the first and second contact portions of the local interconnection layer.