Patent ID: 8441847

Claim:
A method for programming a multi-level phase change memory cell, comprising: applying a sequence of write pulses as a programming signal to said multi-level phase change memory cell; and adjusting in real time at least one parameter of said write pulse as a function of a resistance error; wherein said resistance error is determined as the difference between the resistance of the multi-level phase change memory cell and a reference resistance level; wherein said reference resistance level is a desired resistance of said multi-level phase change memory cell; and wherein said parameter of said write pulse of said programming signal is determined on the basis of said resistance error by calculating said write pulse parameter using either step A, step B, or step C as follows: wherein step A comprises calculating said write pulse parameter in the analog domain by summing a write offset signal and a feedback signal to generate a write signal applied to said multi-level phase change memory cell, subtracting a reference current I ref ) from a current sample of said multi-level phase change memory cell taken during a read period of said write signal to generate a current error signal corresponding to said resistance error of said multi-level phase change memory cell, and integrating said generated current error signal to provide said feedback signal, wherein step B comprises calculating iteratively said write pulse parameter in the discrete domain as follows: P(k+1)=f(P(k), R Ref -R(k)), wherein P is said write pulse parameter, k is a sequential number of said respective write pulse, R Ref is said reference resistance level of said multi-level phase change memory cell, and R(k) is a measured resistance level of the multi-level phase change memory cell, and wherein step C comprises calculating iteratively said write pulse parameter in the discrete domain, wherein said write pulse parameter is a write pulse amplitude, as follows: P(k+1)=P(k)+k i [R Ref -R(k)], wherein P is said write pulse amplitude, k is a sequential number of said write pulse amplitude, k i is an adjustable weighting factor, R Ref is said reference resistance level of said multi-level phase change memory cell, and R(k) is said measured resistance level of said multi-level phase change memory cell.