Patent ID: 8483263

Claim:
A receiver circuit comprising: an equalizer circuit that adjusts reception intensity of an input signal based on an intensity adjustment value to generate a correction input signal; a first holding unit that holds a plurality of data items sampled based on a sampling clock for sampling values of the data items transmitted by the correction input signal in a receiving order; a second holding unit that holds a plurality of values of the correction input signal sampled based on a complementary sampling clock for sampling a boundary value of the data items in a receiving order; and an equalizer control circuit that judges the strength of reception intensity of the correction input signal based on a plurality of output signals of the first holding unit and a plurality of output signals of the second holding unit to update the intensity adjustment value based on the judgment result, wherein the equalizer control circuit judges the strength of the reception intensity based on the plurality of values held in the second holding unit when first data that is held at the earliest timing by the first holding unit and second data held subsequent to the first data have the same polarity.