Patent ID: 7868445

Claim:
An electronic module comprising: a chip layer including: at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, at least one contact pad at the upper surface, and a pad mask over the upper surface with at least one opening therein exposing the at least one contact pad at the upper surface; a structural material surrounding and physically contacting the at least one side surface of each chip of the at least one chip of the chip layer, the structural material having an upper surface substantially co-planar with or parallel to an upper surface of the at least one chip and defining at least a portion of a front surface of the chip layer, and a lower surface substantially co-planar with or parallel to a lower surface of the at least one chip and defining at least a portion of a back surface of the chip layer, and wherein the structural material comprises a dielectric material; and a metallization layer disposed over the front surface of the chip layer, the metallization layer residing at least partially on and in physical contact with the structural material and at least partially on and in physical contact with the pad mask of the at least one chip, and extending over at least one edge of the at least one chip, and wherein the pad mask of the at least one chip of the chip layer and the structural material of the chip layer electrically isolate the metallization layer from the at least one edge of the at least one chip and from one or more electrical structures of the at least one chip.