Patent ID: 8060693

Claim:
A data processing apparatus comprising: a storage that has first to m th memory blocks, each memory block having first to n th sectors and stores data in the first to n th sectors; a specific area erasion section that erases all of the data stored in the first sector of each memory block in the first to m th memory blocks, the first sector in each memory block in the first to m th memory blocks being erased, and the second to n th sectors of each memory block being sequentially erased after all of the first sectors in each memory block in the first to m th memory blocks are erased; an area erasion section that erases the data stored in at least one of the second to n th sectors; and an erasion control section that controls the specific area erasion section and the area erasion section so that erasion of the specific area erasion section takes precedence over erasion of the area erasion section, wherein n and m are natural numbers and n is greater than 1 and m is greater than 1.