Patent ID: 7910922

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of circuit elements formed on the semiconductor substrate; a plurality of bonding pads formed on the semiconductor substrate and electrically connected to the circuit elements; a protective layer formed over the semiconductor substrate and having first openings formed therein such that at least parts of surfaces of the bonding pads are not covered by the protective layer; a plurality of relocation wiring lines formed over the protective layer and each including a first conductor and a first external terminal connection portion integrally formed with the first conductor such that the first conductor electrically coupled to a first one of the bonding pads through the first opening; a first insulating layer over the relocation wiring lines and having second openings formed therein; and a plurality of external terminals formed over the first external terminal connection portions and electrically coupled to the first external terminal connection portions, wherein the number of the bonding pads is greater than the number of the first external terminal connection portions.