Patent ID: 7949907

Claim:
A programmable logic device comprising: a plurality of logic elements and a plurality of I/O pins; at least one of a multiplexer unit and a de-multiplexer unit coupled between said plurality of logic elements and plurality of I/O pins, wherein a phase shift-value along with polarity to apply on a first clock signal or a second clock is determined, and wherein said first clock signal or second clock signal is shifted with the determined phase shift-value; and a control unit for generating control signals for selecting at least one input of the multiplexer unit and at least one output of the de-multiplexer unit, said control unit includes inputs for receiving said first clock signal, said second clock signal, and indicators, said indicators being indicative of a phase skew amongst the first clock signal and the second clock signal and the control unit being configured for generating adaptively adjusted control signals according to the first clock signal and the second clock signal and indicators, said adaptively adjusted control signals are adaptively adjusted for eliminating impact of the phase skew amongst the first clock signal and the second clock signal, wherein the adaptively adjusted control signals are used to select at least one input of the multiplexer unit and at least one output of the de-multiplexer unit, and wherein the indicators are decoupled from functional pins and coupled to a plurality of logic states, said plurality of logic states together being indicative of a phase skew amongst the first clock signal and the second clock signal.