Patent ID: 7553748

Claim:
A method of manufacturing a semiconductor device, the method comprising: providing a substrate including impurity regions and a channel region between the impurity regions; forming a gate structure on the channel region of the substrate, the gate structure including a gate insulation layer pattern, a gate pattern and a mask pattern sequentially stacked on the channel region of the substrate; forming a spacer layer covering the gate structure; forming an insulating interlayer pattern on a resultant structure including the gate structure, the insulating interlayer pattern including a contact hole through which at least one of the impurity regions is exposed, wherein forming the insulating interlayer pattern includes: forming a dummy layer overlying the gate structure; forming a dummy pattern by patterning the dummy layer in such a way that the dummy layer remains on the impurity regions, the dummy pattern extending substantially perpendicularly to the substrate in the impurity region of the substrate; forming an insulating interlayer on the substrate including the dummy pattern to a sufficient thickness to cover the dummy pattern; and partially removing the insulating interlayer from the substrate until a top surface of the insulating interlayer is lower than a top surface of the dummy pattern, thereby forming the insulating interlayer pattern, an upper portion of the dummy pattern being protruded from the insulating interlayer pattern; forming a capping layer pattern on the insulating interlayer pattern, the capping layer pattern including an opening connected to the contact hole; and forming a conductive pattern to fill up the opening and the contact hole.