Patent ID: 7490186

Claim:
A memory system comprising: a memory controller; and a daisy chain of memory chips, the daisy chain of memory chips further comprising a first memory chip and a second memory chip; an address/command bus chain serially coupling the memory controller to the first memory chip and the second memory chip; a data bus chain having a number of data bus bits, serially coupling the memory controller to the first memory chip and the second memory chip, the data bus chain further comprising: a first portion of data bus bits in the data bus chain is dedicated to transferring data from the memory controller to the daisy chain of memory chips; and a second portion of data bus bits in the data bus chain is dedicated to transferring data from a memory chip in the daisy chain of memory chips to the memory controller; wherein an apportionment of data bus bits to the first portion and to the second portion is programmable a first write queue on the first memory chip configured to receive a first write data word transmitted over the first portion of data bus bits in a first link from the memory controller to the first memory chip; a second write queue on the second memory chip configured to receive a second write data word transmitted over the first portion of data bits in a second link from the first memory chip to the second memory chip, wherein at least a portion of the first write data word and at least a portion of the second write data word are transmitted simultaneously; a first read queue on the first memory chip configured to receive a first read data word transmitted over the second portion of data bus bits in the second link from the second memory chip to the first memory chip; and a second read queue on the second memory chip configured to hold a second read data word read from an array in the second memory chip, or received from a third data chip coupled to the second memory chip on a second portion of data bits in a third link from the third memory chip to the second memory chip, wherein at least a portion of the first read data word and at least a portion of the second read data word are transmitted simultaneously.