Patent ID: 8300126

Claim:
A system that staggers resets of rows of pixels in a complementary metal-oxide-semiconductor (CMOS) imaging system-on-chip (iSoC) sensor, comprising: a reset component that sends reset signals to reset transistors of pixels included in a pixel array to reset the pixels; a select component that transfers select signals to select transistors of the pixels included in the pixel array to readout values from the pixels; and a signal timing component that controls timing of the reset component and the select component to coordinate transferring reset signals and select signals to the pixels, wherein when employing sub-frame integration, a first select signal is transferred at a first time period, a first reset signal is transferred at a second time period, a second select signal is transferred at a third time period, and a second reset signal is sent at a fourth time period, such that disparate rows of pixels in the pixel array are reset at different, non-intersecting time periods during a unique readout time interval, wherein the unique readout time is not longer than a time needed to integrate one frame and the first time period, the second time period, the third time period and the fourth time period are non-overlapping.