Patent ID: 7810054

Claim:
A method of optimizing power usage in an integrated circuit design, said method comprising: analyzing multiple operating speed cut points that are expected to be produced by said integrated circuit design, wherein said integrated circuit design produces integrated circuit devices that are identically designed and perform at different operating speeds caused by manufacturing process variations, wherein said operating speed cut points are used to divide said integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices, and wherein said relatively fast integrated circuit devices consume more power than said relatively slow integrated circuit devices; selecting at least one initial operating speed cut point to minimize a maximum power consumption level of said relatively slow integrated circuit devices and said relatively fast integrated circuit devices; manufacturing said integrated circuit devices using said integrated circuit design using manufacturing equipment; testing operating speeds of said integrated circuit devices using a tester; and adjusting said initial operating speed cut point to a final operating speed cut point based on said testing to minimize said maximum power consumption level of said relatively slow integrated circuit devices and said relatively fast integrated circuit devices.