Patent ID: 7142042

Claim:
An apparatus, comprising: a first stage circuit that includes an array of amplifier circuits, wherein each of the amplifier circuits includes: an offset adjustment circuit, an output that is coupled to a common node, an input that is arranged to receive a feedback signal, and a null control input that is arranged to receive a respective null control signal such that each respective offset adjustment circuit is arranged to remove a respective input referred offset for a respective one of the amplifier circuits in response to each respective null control signal, wherein each respective null control signal is independent of one another; a second stage circuit that is arranged to provide a reference signal to an output node in response to an intermediate signal that is associated with the common node; a feedback circuit that is arranged to provide the feedback signal in response to the reference signal, wherein the feedback circuit includes a band-gap core circuit, wherein the band-gap core circuit comprises: a first bipolar junction transistor that is arranged in a common-base configuration with a second bipolar junction transistor, and a resistor that is coupled to the second bipolar junction transistor, wherein the first bipolar junction transistor has a first base-emitter voltage given as VBE1, the second bipolar junction transistor has a second base-emitter voltage given as VBE2, and a voltage across the resistor is given as delta VBE, wherein the first stage circuit, the second stage circuit, and the feedback circuit are arranged for closed-loop operation with the band-gap core circuit such that VBE1=VBE2+delta VBE; and a null control logic circuit that is arranged to provide a set of null control signals, where each null control signal is associated with a respective one of the amplifier circuits such that the amplifier circuits are selectively zeroed to minimize the effects of offset in each of the amplifier circuits.