Patent ID: 8229288

Claim:
A stream data reproducing system comprising: an input buffer configured to accumulate stream data input from a stream source; a decoder core circuit configured to decode the stream data accumulated in the input buffer to generate decoded data; an output buffer configured to output the decoded data after accumulation thereof; a transfer memory cell configured to store the stream data accumulated in the input buffer and the decoded data generated in the decoder core circuit; and a data transfer control circuit configured to control transfer of the stream data from the input buffer to the transfer memory cell, and transfer of the decoded data from the transfer memory cell to the output buffer, the data transfer control circuit further comprising: a buffer read circuit configured to read out the stream data from the input buffer; a transfer region write circuit configured to write the stream data read out from the buffer read circuit into the transfer memory cell; a transfer region read circuit configured to read out the decoded data from the transfer memory cell; a buffer write circuit configured to write the decoded data read out by the transfer region read circuit into the output buffer; and a main control circuit configured to control the buffer read circuit, the transfer region write circuit, the transfer region read circuit, and the buffer write circuit, wherein the main control circuit receives a command for transferring of the stream data from the decoder core circuit and outputs a first transfer mode flag for providing notification of transfer start of the stream data for the buffer read circuit and the transfer region write circuit, and wherein the transfer region write circuit writes the stream data read out by the buffer read circuit in a predetermined transfer size into the transfer memory cell according to the first transfer mode flag, and thereafter outputs a first transfer completion flag for resetting the first transfer mode flag.