Patent ID: 7107374

Claim:
A system, comprising: a processor; a configurable system interconnect (CSI) bus coupled to the processor; a configurable system logic (CSL) device, comprising programmable functions and programmable interconnections, coupled to the CSI bus; dedicated signal lines separate from the CSI bus and coupled to the configurable system logic device, the dedicated signal lines comprising a first set of dedicated signal lines used to transmit commands from the CSL device and a second set of dedicated signal lines to receive commands at the CSL device; a direct memory access (DMA) controller coupled to the first set of dedicated signal lines and the second set of dedicated signal lines; and a bus master unit (BMU) coupled to the CSI bus, and coupled to the CSL device via the first set of dedicated signal lines used to receive commands at the BMU from the CSL device and the second set of dedicated signal lines to transmit grant commands from the BMU to the CSL device, wherein the BMU arbitrates to take control of the CSI bus on behalf of the CSL device enabling the CSL device to perform data transfers to or from the CSI bus when the BMU is selected for bus mastering and wherein the CSL device selectively receives the grant signal only the BMU or from the DMA controller.