Patent ID: 6928588

Claim:
A network device comprising: a buffer memory having a plurality of memory locations including redundant memory locations, said memory locations having addresses; a plurality of network ports; a memory controller coupled to said buffer memory and configured to read and write data from and to said buffer memory; a first plurality of fuses coupled to said redundant memory locations of said buffer memory; a second plurality of fuses coupled to said memory controller and configured to store an address of a failed memory location of said plurality of memory locations; and a built-in self test unit coupled to said buffer memory and to said second plurality of fuses, and configured to perform a test of said buffer memory to determine an address of a failed memory location of said plurality of memory locations, and to store said address of said failed memory location in a fuse of said second plurality of fuses; and wherein said memory controller is configured to prevent a use of said failed memory location based on said address stored in said fuse.