Patent ID: 7908100

Claim:
A power consumption analyzing apparatus comprising: a clock gating cell detector configured to detect a clock gating cell which is not present in RTL data indicative of Register Transfer Level data but present in a gate-level netlist based on the RTL data of a target circuit and the netlist corresponding to the RTL data; a test bench description generation unit configured to add a description concerning the clock gating cell detected by the clock gating cell detector to the RTL data; a monitor signal generation unit configured to specify a monitor signal used for power consumption analysis from the RTL data obtained by adding the description concerning the clock gating cell; an RTL simulation unit configured to execute operational simulation of the target circuit by using the RTL data obtained by adding the description concerning the clock gating cell; a monitor unit configured to detect a logic of the monitor signal during the execution of the operational simulation; and a power consumption analysis unit configured to analyze power consumption due to a toggle at a clock terminal of a clock synchronizing cell included in the target circuit.