Patent ID: 7821131

Claim:
A microelectronic substrate including: a substrate having a die-side surface including a die-attach region; a system of interconnects extending through the substrate and adapted to allow a connection of the substrate to external circuitry; a plurality of solder bumps including: a plurality of die-attach solder bumps electrically coupled to the system of interconnects and disposed in the die-attach region; and a plurality of barrier solder bumps isolated from the system of interconnects, the barrier solder bumps being disposed outside of the die-attach region and being adapted to substantially limit a flow of underfill away from the die-attach region; and a plurality of metal pads on the substrate, wherein the plurality of metal pads include barrier pads isolated from the system of interconnects, the barrier pads being disposed outside of the die-attach region, and the barrier solder bumps being disposed on respective ones of the barrier pads.