Patent ID: 6853063

Claim:
A semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, a primary side circuit being provided on said first semiconductor substrate, a secondary side circuit provided on said second semiconductor substrate, first capacitive insulation means provided on said first semiconductor substrate for electrically insulating and isolating between said primary side circuit and said secondary side circuit while permitting signal transmission between said primary side circuit and said secondary side circuit, second capacitive insulation means provided on said second semiconductor substrate for electrically isolating between said primary side circuit and said secondary side circuit while permitting signal transmission therebetween, a first lead frame for input and output of a signal to and from said primary side circuit, a second lead frame for signal input and output to and from said secondary side circuits, a third lead frame supporting thereover said first semiconductor substrate, and a fourth lead frame supporting said second semiconductor substrate, wherein an external electrode of said first capacitive insulation means and an external electrode of said second capacitive insulation means are connected together by a bonding wire while letting said first semiconductor substrate and said second semiconductor substrate plus the first to fourth lead frames be sealed by a dielectric resin, and wherein said primary side circuit is on an analog input/output side, wherein said secondary side circuit has an analog front end being on a digital input/output side, wherein said capacitive insulation means permits signal transmission between the analog input/output side circuit and the digital input/output side circuit, and wherein said analog input/output side circuit and said digital input/output side circuit are electrically insulated and isolated from each other.