Patent ID: 7657589

Claim:
A method of generating a fixed point approximation, comprising: determining a value, denoted N, of the most significant bit in x to serve as an index into a table that contains fixed-point representations of x (N-fractional — bits)y , wherein the retrieved value is denoted as v 1 , and storing the value in a computer readable medium; forming another index, denoted M, from the k o bits immediately following the most significant bit, wherein M is used as an index to address a second table that contains two output values per table entry: v 2 =(1 +a 1 2 −1 +a 2 2 −2 + . . . +a k o 2 −k o ) y ; and v 3 =y/( 1 +a 1 2 −1 + . . . +a k o 2 −k o ); and storing the two values; creating a fixed-point number from remaining bits of x if any exist that directly follow the index M; inserting these remaining bits into the created number starting at the k o +1 fractional-bit to get a result, wherein both the integer-bits and the first k o fractional-bits of the result are all zero, and wherein the remaining bits of the result are the remaining bits of x to generate a second result v 4 , and storing the second result; computing the final result: x y ≈v 1 ×v 2 ×[1+(v 3 ×v 4 )] using fixed-point arithmetic to generate said fixed point approximation used by an electronic device.