Patent ID: 7613989

Claim:
A Viterbi decoder, comprising: a computing device configured to generate control signals dependent on a plurality of decisions associated with a plurality of paths and operable to decide data values, the computing device includes a data value input configured to receive sets of data values; a distance metric to calculate distances for the received sets of data values; and an accumulate-and-compare module operable to calculate distances for the received sets of data values; a unidirectional bus having a width of 1×2 ((degree of parallelization)+1) bits and configured to convey control signals; a path memory in communication with the computing device through the unidirectional bus, the path memory configured to store the decided data values; and an output in communication with the path memory to provide at least one output value; where one of the computing device and the path memory shifts data strings in the path memory according to conditions of Viterbi decoding with the control signals associated with the plurality of paths.