Patent ID: 6871328

Claim:
A method for implementing a user logic design including at least one logic design memory in a programmable logic device comprising physical memory devices of one or more types, the method comprising: dividing the logic design memory into a plurality of memory slices; performing an analysis of the programmable logic device including the physical memory devices; mapping the plurality of memory slices to the physical memory devices based at least in part on the analysis; and wherein the mapping the plurality of memory slices to the physical memory devices based at least in part on the analysis comprises: grouping the plurality of memory slices into one or more compatible logic groups, wherein memory slices of a particular compatible logic group have substantially the same control signals; grouping memory slices within each of the one or more compatible logic group into one or more sub-groups, wherein memory slices grouped into a particular sub-group share substantially the same constraints; and mapping the plurality of memory slices onto the physical memory devices in an order determined by to which compatible logic group and sub-group each of the plurality of memory slices belongs.