Patent ID: 8438511

Claim:
A computer-implemented method of logic synthesis for preserving a reset behavior of a circuit, the method comprising: providing the circuit; identifying a memory element at a first location within the circuit, wherein the memory element is reset with a first reset value; relocating the memory element across at least a first portion of the circuit resulting in at least one relocated memory element; duplicating the at least one relocated memory element; connecting the at least one relocated memory element and the at least one duplicated memory element with the circuit; determining, by using a computer, a plurality of reset values for the at least one relocated memory element and the at least one duplicated memory element, wherein the first reset value is produced at the first location when the plurality of reset values are propagated through the circuit from the at least one relocated memory element and the at least one duplicated memory element to the first location; duplicating a second portion of the circuit, wherein the first portion of the circuit includes the second portion of the circuit; and connecting the duplicated second portion of the circuit with the circuit and the at least one relocated memory element and the at least one duplicated memory element.