Patent ID: 8354330

Claim:
A method of fabricating a SOI SJ LDMOS structure that can completely eliminate substrate-assisted depletion effects, the method comprising the following steps: (1) a conductive layer is prepared below a buried oxide layer of a SOI structure using a bonding technique, the conductive layer being prepared by; a1) acquiring a first intermediate structure by depositing a barrier layer on a first bulk silicon wafer, then depositing a charge conducting layer on the barrier layer; a2) acquiring a second intermediate structure by forming a silicon dioxide layer on a second bulk silicon wafer by thermal oxidation, depositing a barrier layer on the silicon dioxide layer and depositing a charge conducting layer on the barrier layer; a3) bonding the first intermediate structure and the second intermediate structure by a metallic bonding technique to obtain the conductive layer below the buried oxide layer of the SOI structure; a4) decreasing a size of the second bulk silicon wafer at its back by hydrogen ion-implantation smart-cut technology to be as thin as a top silicon film of the SOI structure; and a5) leading out the conductive layer; and (2) a SJ LDMOS structure is fabricated on the SOI structure having the conductive layer.