Patent ID: 8110495

Claim:
A method of producing a wiring structure of a semiconductor device, comprising: a step (a) of forming a first opening in a first insulating layer formed above a substrate and forming a lower plug in the first opening; a step (b) of forming a wiring layer above the first insulating layer and the lower plug; a step (c) of forming a second insulating layer above the wiring layer, and forming, in the second insulating layer, a second opening opposite to the first opening, and forming an upper plug in the second opening; wherein by heat treatment at the step (b), in a case that there is a single grain in a first region of the wiring layer between the upper plug and the lower plug, a size of the grain in the first region becomes substantially equal to a size of a single grain or an average size of grains in a second region of the wiring layer not between the upper plug and the lower plug and, in case that there are a number of grains in the first region, average size of the grains in the first region becomes substantially equal to the size of the single grain or the average size of the grains in the second region.