Patent ID: 7272691

Claim:
A data processor apparatus, comprising: a plurality of processor elements including a first processor element, a second processor element, and a third processor element; a memory having a plurality of parts, each memory part being associated with said respective processor element; and a first switching element associated with said first processor element for switchably coupling said first processor element to its associated memory part for at least one of read and write access, and wherein said first switching element has an input port for access to at least one of said associated memory part and said first processor element, an output port for access to at least one of said associated memory part and said first processor element, a first port being coupled to an input/output port of a second switching element, the second switching element being associated with said second processor element for switchably coupling said second processor element to its associated memory part, a second port being coupled to an input/output port of a third switching element, the third switching element being associated with said third processor element for switchably coupling said third processor element to its associated memory part, a first switch means for selectively coupling said first port to one of said input port and said output port, and a second switch means for selectively coupling said second port to one of said input port and said output port.