Patent ID: 8385340

Claim:
A packet processor, comprising: a memory storing microcode that specifies respective sets for a plurality of types of a plurality of packets, each of the packets having a type of the plurality of types, and the respective set for each type specifies a plurality of elementary operations for each of a plurality of stages other than an initial stage of the plurality of stages; and a programmable compute pipeline coupled to the memory for sequentially processing the plurality of packets, wherein: the programmable compute pipeline includes a sequence of the plurality of stages, and the sequence begins with the initial stage; the initial stage includes an operation selector that selects the respective set for the type of each of the plurality of packets; and each stage of the plurality of stages other than the initial stage includes a plurality of elementary components that are programmable to concurrently perform each of a plurality of combinations of the plurality of elementary operations, and the plurality of elementary components concurrently perform a selected one of the plurality of combinations for each of the plurality of packets, the selected combination including the plurality of elementary operations specified for the stage in the respective set that the operation selector selects for the type of the packet; wherein the programmable compute pipeline is one of a plurality of programmable compute pipelines arranged in a programmable protocol pipeline for a plurality of protocol layers, and for each first and successive second one of the programmable compute pipelines in the programmable protocol pipeline, the first programmable compute pipeline is programmable to determine a second offset from a first offset and provide the second offset to the second programmable compute pipeline.