Patent ID: 7624254

Claim:
A processor, comprising: control logic; and a segmented instruction execution pipeline comprising an upper pipeline prior to the point at which instructions may be out of program order and one or more lower pipelines beyond the point at which instructions may be out of program order; a General Purpose Register (GPR) file operative to dynamically associate GPR logical identifiers to physical registers, comprising: a plurality of physical registers; a Speculative Renaming Table (SRT) containing mappings of all current GPR logical identifiers to physical registers; and a Committed Renaming Table (CRT) containing mappings of GPR logical identifiers to physical registers only for instructions that have committed; wherein the control logic is operative to immediately flush all instructions from the upper pipeline upon detecting a mispredicted branch, to fetch instructions from a correct branch target address in the cycle following flushing the upper pipeline, to flush all uncommitted instructions from the lower pipelines upon committing the mispredicted branch instruction for execution, to copy the contents of the CRT to the SRT upon flushing all uncommitted instructions from the lower pipelines, to place a hold at the end of the upper pipeline following the upper pipeline flush, and to remove the hold upon flushing all uncommitted instructions from the lower pipelines; wherein the control logic includes an instruction ordering mechanism operative to track the confirmed and committed status of instructions, and further operative to flush all uncommitted instructions from the lower pipelines when the mispredicted branch instruction is the newest confirmed instruction; and wherein each lower pipeline that executes branch instructions includes a confirmation state operative to set a mispredicted branch indication in the instruction ordering mechanism when a branch instruction is determined to have been mispredicted.