Patent ID: 7599980

Claim:
A method for using the Newton-Raphson technique to compute a square-root within an arithmetic-logic unit (ALU) of a computer system, comprising: receiving a radicand b; and calculating √{square root over (b)} by first using the Newton-Raphson technique to find 1/√{square root over (b)}, and then multiplying 1/√{square root over (b)} by b to produce √{square root over (b)}; wherein using the Newton-Raphson technique to find 1/√{square root over (b)} involves obtaining an initial estimate x 0 for 1/√{square root over (b)} and iteratively solving the equation x i + 1 = x i ⁢ ⁢ ( 3 - bx i 2 2 ) by, using a multiplier circuit twice to compute bx i 2 , performing a bit-wise complement operation on bx i 2 , shifting the result, and modifying the first two bits of the result to compute 3 - bx i 2 2 , whereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation, and using the multiplier circuit to multiply x i by 3 - bx i 2 2 to compute x i ⁢ ⁢ ( 3 - bx i 2 2 ) , wherein a separate inverter and a separate multiplexer are attached to each bit position of the multiplier circuit to selectively perform a bit-wise complement or a shift operation during specific passes through the multiplier circuit.