Patent ID: 8884798

Claim:
An apparatus comprising: a plurality of voltage range adjusters, one for each bit of a digital sequence, arranged in series such that the plurality of voltage range adjusters is configured to convert the digital sequence to an analog representation, each of the voltage range adjusters being configured to receive a respective bit of the digital sequence, the voltage range adjusters comprising a first voltage range adjuster, zero or more intermediate voltage range adjusters, and a last voltage range adjuster, wherein the first voltage range adjuster is configured to produce first high and low output voltages based on first high and low input voltages, respectively, and a most significant bit value of the digital sequence, wherein the last voltage range adjuster is configured to produce last high and low output voltages based on last high and low input voltages, respectively, and a least significant bit value of the digital sequence, wherein the last high and low input voltages are responsive to the first high and low output voltages, respectively, as modified by any of the zero or more intermediate voltage range adjusters; and a combiner configured to produce an analog output signal based on the last high and low output voltages.