Patent ID: 8487382

Claim:
An integrated circuit having metal gate stacks, comprising: a semiconductor substrate; a first gate stack of an n-type field-effect transistor, the first gate stack including: a high k dielectric layer on the semiconductor substrate; a titanium nitride layer on the high k dielectric material layer; a first metal layer on the titanium nitride layer, the first metal layer comprised of one of titanium nitride and tantalum nitride; and a second metal layer on the first metal layer such that the second metal layer physically contacts the first metal layer; and a second gate stack of a p-type FET, the second gate stack including: the high k dielectric layer on the semiconductor substrate; the titanium nitride layer on the high k dielectric material layer; a third metal layer on the titanium nitride layer, wherein the third metal layer is different from the first and second metal layers; and a fourth metal layer on the third metal layer, wherein the second metal layer comprises at least one of titanium aluminum and titanium aluminum nitride in physical contact with the first metal layer.