Patent ID: 7783877

Claim:
A boot-switching apparatus, disposed in a system having a plurality of processors and a plurality of memories, comprising: a plurality of processor enabling pins, respectively coupled to the processors, each of the processor enabling pins being suitable for setting an enabling signal to enable or disable one of the processors, which corresponds to the processor enabling pin; a plurality of processor detection pins, respectively coupled to the processors, each of the processor detection pins being suitable for detecting working status of one of the processors, which corresponds to the processor detection pin, and obtaining a detection signal; a plurality of memory selection pins, coupled to the memories, suitable for setting a selection signal to switch the memories; and a timer, set with a time-out, suitable for counting down the time-out when the system is booting, wherein when the countdown of the time-out is completed, whether or not each of the enabling signals of the processor enabling pins matches the detection signal of one of the processor detection pins is determined, wherein the processor enabling pin and the processor detection pin correspond to the same processor, the processor is disabled through one of the processor enabling pins, which corresponds to the processor, if the enabling signal does not match the detection signal, the memories are switched through the memory selection pins one by one until a memory that works normally is located if all the enabling signals and detection signals match each other.