Patent ID: 7208353

Claim:
A method of manufacturing a semiconductor device forming a MISFET, comprising: preparing an SOI substrate in which a support substrate made of a semiconductor, a buried insulating film, and a semiconductor layer are stacked one after another; implanting impurities into a surface layer of the support substrate, which contacts the buried insulating film, to form a diffusion layer; selectively etching the semiconductor layer except for regions including source and drain regions and a channel region of the MISFET, to form an upper structure in which the source and drain regions and the channel region are formed inside; forming a sidewall insulating film on side surfaces of the upper structure; selectively etching the semiconductor layer exposed from side portions of the sidewall insulating film, to expose the buried insulating film, and to form a lower structure under the upper structure, the lower structure having a larger cross-sectional area than that of the upper structure, the lower structure being parallel to a main surface of the support substrate; forming an insulating layer on the buried insulating film around the lower structure, upper structure, and sidewall insulating film; forming a dummy gate in a region on the upper structure, in which a gate electrode of the MISFET is to be formed; selectively implanting impurities into portions of the upper structure that are not covered with the dummy gate, to form the source and drain regions; forming an interlayer insulating film around the dummy gate; selectively removing the dummy gate, to form a gate groove having sidewalls made of the interlayer insulating film and exposing the channel region; forming a gate insulating film on the channel region exposed from a bottom of the gate groove; partially etching the gate insulating film and insulating layer at the bottom of the gate groove to form a hole which partially exposes side surfaces of the lower structure; forming gate electrodes in the gate groove and the hole; partially etching the interlayer insulating film, insulating layer, and buried insulating film to form a contact hole connected to the diffusion layer; and forming an upper wire in the contact hole.