Patent ID: 7185174

Claim:
A switching element for switchably coupling a two-dimensional array of circuit elements each having an input and an output, the switching element comprising: an input for coupling to at least one associated local circuit element; an output for coupling to at least one associated local circuit element; means for switchably coupling said input to said output; a first input/output port, a second input/output port, a third input/output port, and a fourth input/output port, each input/output port being swichably coupled to said input, said output, and each other; a first switch means having a first state in which said first input/output port is coupled to said second input/output port, a second state in which said first input/output port is coupled to said third input/output port, and third state in which said first input/output port is coupled to said fourth input/output port; a second switch means having a first state in which said second input/output port is coupled to said first input/output port, a second state in which said second input/output port is coupled to said fourth input/output port, and a third state in which said second input/output port is coupled to said third input/output port; a third switch means having a first state in which said third input/output port is coupled to said second input/output port, a second state in which said third input/output port is coupled to said first input/output port, and a third state in which said third input/output port is coupled to said fourth input/output port; and a fourth switch means having a first state in which said fourth input/output port is coupled to said third input/output port, a second state in which said fourth input/output port is coupled to said second input/output port, and a third state in which said fourth input/output port is coupled to said first input/output port; and wherein said first and third input/output ports are spaced apart along a first axis, and said second and fourth input/output ports are spaced apart along a second axis, wherein said second axis traverses said first axis between said first and third input/output ports.