Patent ID: 6889240

Claim:
A data processing device comprising: a first processing unit having an integer calculation function; a second processing unit controlled by the first processing unit having a fixed-point data calculation function; wherein the second processing unit includes a register and a multiplier which is to perform an integer data calculation and a fixed-point data calculation; wherein the first processing unit performs a first type instruction, and the second processing unit performs a second type instruction, the second type instruction having a first instruction for calculating an integer data and a second instruction for calculating a fixed-point data; wherein the first processing unit decodes the first type instruction and the second type instruction, wherein the first processing unit outputs a control signal corresponding to a decoded result to the second processing unit when the first processing unit decodes the second instruction, wherein when the first processing unit decodes the first type instruction, the first processing unit operates, wherein when the first processing unit decodes the first instruction of the second type instruction, the multiplier in the second processing unit calculates an integer data, wherein when the first processing unit decodes the second instruction of the second type instruction, the multiplier in the second processing unit calculates a fix-point data, wherein when a second instruction is executed to transfer data, whose bit length is shorter than the bit length of the register, from the register to the outside of the second processing unit, the second processing unit outputs a required bit length of the data from the higher-order side of the register to the outside.