Patent ID: 7613990

Claim:
An add-compare-select circuit, comprising: an adder circuit to receive first and second sets of cost signals and configured to provide first and second summations of the first and second sets of cost signals; a first synchronization circuit, coupled to the adder circuit, the first synchronization circuit configured to store and provide the first and second summations in synchrony with a clock signal; a compare circuit to receive the first and second summations in response to the clock signal and configured to provide a comparison signal indicative of a relative difference between a magnitude of the first summation and a magnitude of the second summation; a second synchronization circuit, coupled to the first synchronization circuit and the compare circuit, the second synchronization circuit configured to store and provide the first and second summations in synchrony with the clock signal and to store and provide the comparison signal in synchrony with the clock signal; and a selection circuit, coupled to the second synchronization circuit, the selection circuit configured to provide a selected signal that is equal to one of the first or second summations in response to a value of the comparison signal.