Patent ID: 7573139

Claim:
A semiconductor system comprising: a first subsystem including: a first semiconductor interposer having a first dimension and a first and a second surface; conductive lines on the first and second surfaces; conductive vias extending from the first to the second surface, contacting the lines; terminals with attached non-reflow metal studs connected to the vias; a first semiconductor chip having a dimension narrower than the first interposer dimension, and an active surface; terminals with non-reflow metal studs on the active surface; the first chip flip-attached to the second surface of the first interposer so that the first interposer dimension projects over the chip dimension; a second subsystem including: a second semiconductor interposer having a second dimension and a third and a fourth surface; conductive lines on the third and fourth surfaces; conductive vias extending from the third to the fourth surface, contacting the lines; terminals with attached non-reflow metal studs connected to the vias; a second semiconductor chip having a dimension narrower than the second interposer dimension, and an active surface; terminals with non-reflow metal studs on the active surface; the second chip flip-attached to the fourth surface of the second interposer so that the second interposer dimension projects over the chip dimension; reflow bodies on the terminals of the first interposer surface connecting to studs on the fourth surface of the projecting second interposer; an insulating substrate having a fifth and a sixth surface with terminals; conductive lines between the fifth and the sixth surface; conductive vias extending from the fifth to the sixth surface, contacting the lines; and reflow bodies on the terminals of the fifth substrate surface connecting to the studs on the second surface of the projecting first interposer.