Patent ID: 8539170

Claim:
A decoding circuit for decompressing lossless-encoded compressed data, comprising: a separator constructed to separate the lossless-encoded compressed data into a first command that requires memory access and a second command that requires no memory access, by referring to a command table; a first cache memory which stores a predetermined number of first commands separated by the separator; a second cache memory which stores a predetermined number of second commands separated by the separator; a decoder constructed to request memory reading of decompressed data necessary for decompression of the first command, to decode the first command based on the decompressed data, and to request memory writing of decompressed data obtained by decoding; and a memory controller constructed to control reading and writing of a third cache memory and a line memory, wherein the line memory is a semiconductor memory other than a static random access memory, and to execute memory reading and memory writing corresponding to a request from the decoder, wherein, in response to a memory read request from the decoder, when corresponding data exists in the third cache memory, the memory controller supplies, to the decoder, at least part of data read out from the third cache memory, and when no corresponding data exists in the third cache memory, the memory controller supplies, to the decoder, at least part of data burst-read from actual addresses of the line memory based on reading of the first command stored in the first cache memory.