Patent ID: 7577797

Claim:
A method of data processing in a cache coherent data processing system including at least first and second coherency domains, wherein said first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory, and wherein said second coherency domain includes a second processing unit having a second cache memory, said method comprising: in the first cache memory, setting a coherency state field associated with a storage location and an address tag to a first coherency state; in response to snooping an exclusive access request specifying a target address matching said address tag, said first cache memory providing a first partial response to said exclusive access request based at least in part upon said first coherency state; in response to snooping the exclusive access request, said memory controller determining whether it is responsible for said target address and providing a second partial response to said exclusive access request based at least in part upon an outcome of said determination; accumulating at least said first and second partial responses to obtain a combined response for said exclusive access request, said combined response including an indication of whether or not a highest point of coherency and a memory controller of a home system memory for said target address reside within a same coherency domain; said first cache memory updating said coherency state field from said first coherency state to a second coherency state in response to said indication in said combined response, wherein said second coherency state indicates: that said address tag is valid, that said storage location does not contain valid data, whether a target memory block associated with said address tag is likely cached within said first coherency domain, and that the home system memory that is responsible for the target address is not located within the first coherency domain; wherein said updating comprises updating said coherency state field from said first coherency state to said second coherency state in response to said indication indicating that the highest point of coherency and the memory controller of the home system memory for said target address do not reside within a same coherency domain; and said first cache memory predicting, by reference to said coherency state field, a scope of broadcast transmission of a data access request targeting said memory block.