Patent ID: 7644256

Claim:
A method in a processor, in which data is processed in a pipelined manner, the data being included in a plurality of contexts, comprising a first context ( 3 ), each context passing a plurality of consecutive stages ( 2 a - 2 f ), in addition to which a plurality of operations is adapted to be executed on the contexts, each operation comprising a plurality of consecutive operation steps and the consecutive operation steps of one operation being executed on a context at least two different consecutive stages ( 2 a - 2 f ), the method comprising: at a first stage ( 2 a ), executing an initial operation step ( 6 a ) of a first operation on the first context ( 3 ), and at a second stage ( 2 b ) that consecutively follows the first stage ( 2 a ), subsequently commencing an execution on the first context of an initial operation step ( 7 a ) of a second operation before an execution on the first context ( 3 ) of a following operation step ( 6 b ) of the first operation is completed, wherein, at each clock cycle of the processor, the first context ( 3 ) is received at one of the stages from the preceding stage, the first context is unconditionally moved to a next stage and a subsequent context of a subsequent operation is received at the first stage ( 2 a ).