Patent ID: 8008758

Claim:
A semiconductor package comprising: a generally planar die pad defining multiple peripheral edge segments; a plurality of first leads which each include first and second downsets formed therein in spaced relation to each other, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad; a plurality of second leads, at least some of which include a downset formed therein, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad; a semiconductor die attached to the die pad and portions of the first leads, the semiconductor die being electrically connected to at least one of each of the first and second leads; and a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the first and second downsets of the first leads and the downsets of the second leads are covered by the package body, at least portions of the die pad and the first leads are exposed in and substantially flush with the bottom surface of the package body, and portions of at least some of the second leads protrude from at least one of the side surfaces of the package body.