Patent ID: 7269078

Claim:
A memory system for writing data to a memory array in response to a clock signal or reading out the data from the memory array, the memory system comprising: a buffer circuit which receives and outputs a first signal and a second signal in response to a control signal and an inverted control signal when the written or read data are n bits, and outputs the first signal in response to the control signal and the inverted control signal when the data are k bits; and a latch unit which latches the data in response to at least one of the first signal and the second signal and outputs the latched data to the memory array; wherein the buffer circuit includes: a first buffer unit which amplifies and outputs the first signal; a second buffer unit which amplifies and outputs the second signal or outputs the first signal according to the logic level of the control signal; and a third buffer unit which amplifies the first signal and either sends or does not send the amplified first signal to the second buffer unit depending on the logic level of the inverted control signal, wherein the logic levels of the control signal and the inverted control signal are determined by the number of data bits.