Patent ID: 8184080

Claim:
A liquid crystal display comprising: a liquid crystal panel assembly including a first, a second and a third scanning area, each of the scanning areas including a plurality of gate lines connected to a plurality of pixels which include switching elements connected to the gate lines and data lines; a gate driver applying a voltage to the gate lines for turning on the switching elements; a data driver selecting gray voltages corresponding to gray signals and applying the selected gray voltages to the pixels via the data lines as data signals, each of the data signals including normal data signals and a black data signal; and a signal controller providing the gray signals and control signals for controlling the gate driver and the data driver, wherein, in one frame period, the signal controller controls the gate driver and the data driver such that the black data signal is applied to pixels connected to gate lines of the second scanning area while gate-on voltages are applied to the gate lines of the second scanning area and then, the normal data signals are applied to pixels connected to gate lines of the first scanning area while gate-on voltages are sequentially applied to the gate lines of the first scanning area in an arranging direction in which the gate lines are arranged; the signal controller controls the gate driver and the data driver such that, in said one frame period, gate-on voltages are applied to gate lines of the third scanning area after the gate-on voltage is applied to the last gate line of the first scanning area and then the black data signal is applied to pixels connected to the gate lines of the third scanning area, wherein, in a frame period next to said one frame period, the signal controller controls the gate driver and the data driver such that the black data signal is applied to pixels connected to gate lines of the second scanning area while gate-on voltages are applied to the gate lines of the second scanning area and then, the normal data signals are applied to the pixels connected to gate lines of the first scanning area while gate-on voltages are sequentially applied to the gate lines of the first scanning area in a direction opposite to the arranging direction of the gate lines.