Patent ID: 7738281

Claim:
A semiconductor storage device comprising: a plurality of memory cells each provided with an access transistor in which a source is connected to a bit line and a gate is connected to a word line and a capacitor in which a storage electrode is connected to a drain of the access transistor, the plurality of memory cells being placed in a matrix shape in column and row directions; a sense amplifier circuit connected to the source of the access transistor via the bit line; a reference voltage generating circuit for generating a first reference voltage and a second reference voltage in which the second reference voltage is generated by depressing voltage of the first reference voltage; a bit-line precharge voltage generating circuit for controlling potential of a bit-line precharge voltage to be equivalent to the first reference voltage, the bit-line precharge voltage generating circuit, the bit-line precharge voltage generating circuit comprising a first differential amplifier having the first reference voltage and the bit-line precharge voltage as inputs and a first pull-up element for pulling up the bit-line precharge voltage based on output of the first differential amplifier; a cell plate voltage generating circuit for controlling potential of a cell plate voltage to be equivalent to the second reference voltage, the cell plate voltage generating circuit comprising a second differential amplifier having the second reference voltage and the cell plate voltage as inputs and a second pull-up element for pulling up the cell plate voltage based on output of the second differential amplifier.