Patent ID: 7724058

Claim:
A system comprising: a first latch; and a pulse generator coupled to provide a timing signal to the first latch, wherein the pulse generator includes a second latch that has characteristics matching the first latch, the pulse generator further comprising: the second latch responsive to a clock input; and a logic circuit coupled to the clock input and coupled to an output of the second latch, the logic circuit to provide a pulse output including at least one pulse having a pulse width that varies in response to a data propagation time of the second latch, wherein the pulse width is associated with a delay time that includes an inverter delay time and the data propagation time of the second latch, wherein the logic circuit includes circuitry that performs a logical AND function with respect to an output of the second latch as a first input to the AND and the clock input as a second input to the AND, wherein the circuitry includes multiple transistors and an output inverter, wherein the output inverter provides the pulse output, and wherein the logic circuit further includes an enable input to selectively enable generation of the pulse output.