Patent ID: 6911690

Claim:
A flash memory cell, comprising: a substrate; a stack gate structure formed on said substrate, said stack gate structure including a select gate dielectric layer, a select gate, and a gate cap layer, said select gate dielectric layer being formed between said substrate and said select gate, said gate cap layer being formed on said select gate; a spacer formed along a sidewall of said select gate; a control gate formed on one side of said stack gate structure and connected to said stack gate structure; a floating gate formed between said control gate and said substrate and including a recess, wherein a top surface of said floating gate layer is positioned between a top surface of said spacer and a top surface of said gate cap layer; an inter-gate dielectric layer formed between said control gate and said floating gate; a tunneling dielectric layer formed between said floating gate and said substrate; and a drain region and a source region formed in said substrate, wherein said drain region and said source region formed on the one side and the other side of said control gate and said stack gate structure respectively.