Patent ID: 8508303

Claim:
A digital frequency/phase locked loop for controlling an outputted oscillation frequency on the basis of a signal error that is a difference between an inputted channel signal and the oscillation frequency, the digital frequency/phase locked loop comprising: a comparator for comparing the channel signal to a loopback signal having the oscillation frequency to generate the signal error; a digital loop filter for generating a control voltage that determines the oscillation frequency, on the basis of the signal error; a VCO for controlling an oscillation frequency on the basis of the control voltage; a loopback path through which the oscillation frequency generated by the VCO is outputted as the loopback signal to the comparator; and a control section for monitoring the signal error generated by the comparator, and controlling the digital loop filter such that the oscillation frequency of the VCO comes into a stationary state, when detecting that the signal error is within a predetermined range based on 0 after the channel signal is switched, wherein the digital loop filter includes an FIR filter and an IIR filter, and the control section (i) obtains the control voltage outputted by the digital loop filter, (ii) sets 0 to a delay block of the FIR filter, and (iii) sets the control voltage obtained from the digital loop filter to a delay block of the IIR filter.