Patent ID: 7675811

Claim:
Circuitry for reading from a double data rate type memory, said circuitry comprising: control logic; a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by said control logic; a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of said double data rate type memory; a gate coupled to said second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along said data strobe line in response to a data strobe masking gating signal; and a data strobe masking gating signal modifier receiving from said control logic an expected data receipt duration indicating signal and an extent of delay indicating signal and applying to said expected data receipt duration indicating signal a variable time delay based at least in part on said extent of delay indicating signal such as to center said expected data receipt duration indicating signal about the midpoint of said duration of said data transmission.