Patent ID: 7843222

Claim:
A buffer-driving circuit capable of increasing a responding speed of a buffer circuit and a lifespan of the buffer circuit, the buffer circuit having a transmitting transistor and a voltage-sharing transistor, the transmitting transistor coupled between a first voltage source and the voltage-sharing transistor, the voltage-sharing transistor coupled between the transmitting transistor and an output end of the buffer circuit, the first voltage source providing a first voltage, the buffer circuit utilized for buffering an input signal and accordingly generating an output signal from the output end of the buffer circuit, the buffer-driving circuit comprising: a level-shifting circuit, for shifting a voltage level of the input signal so as to generate a level-shifting signal; wherein when the voltage level of the input signal is equal to a first predetermined voltage level, the level-shifting signal is equal to the first voltage; when the voltage level of the input signal is equal to a second predetermined voltage level, the level-shifting signal is equal to a second voltage; a pulse generator, for generating a pulse signal with a predetermined period when the input signal is in a transition state; and a bias circuit, comprising: a first inverter, comprising: an input end, coupled to the level-shifting circuit, for receiving the level-shifting signal; an output end, coupled to a control end of the transmitting transistor, for outputting a transmitting gate-driving signal so as to control the transmitting transistor; a first power end, coupled to the first voltage source, for receiving the first voltage; and a second power end; and a second inverter, comprising: an input end, coupled to the pulse generator, for receiving the pulse signal; an output end, coupled to a control end of the voltage-sharing transistor and the second power end of the first inverter, for outputting a voltage-sharing gate-driving signal; a first power end, coupled to a second voltage source, for receiving the second voltage; and a second power end, coupled to a third voltage source, for receiving a third voltage; wherein an amplitude of the transmitting gate-driving signal is between the first voltage and the voltage-sharing gate-driving signal; wherein an amplitude of the voltage-sharing gate-driving signal is between the second voltage and the third voltage.