Patent ID: 8289060

Claim:
A flip-flop, comprising: a functional latch configured to maintain a logic state of the flip-flop in a power-up mode; a retention latch configured to maintain the logic state of the flip-flop in a power-down mode, wherein true and complementary data values are transferred concurrently from the functional latch to the retention latch to minimize a required transfer time, and wherein the flip-flop is a pulsed state retention power gating flip-flop; first and second switches configured to selectively couple the functional latch to the retention latch responsive to a first control signal, wherein the first control signal is asserted to connect the functional latch and the retention latch for data transfer, and wherein the first control signal is deasserted to disconnect the functional latch and the retention latch; and a read circuit coupled to the functional latch, wherein the read circuit is configured to transfer data from the retention latch to the functional latch when a read signal is asserted, a power-down signal is deasserted, and the first control signal is asserted.