Patent ID: 8564351

Claim:
A circuit for latching logic states, comprising: a primary latch arranged to latch a primary input signal in response to a primary latch clock signal, and to generate a primary output signal in response to the latched primary input signal; a secondary latch arranged to latch the primary output signal in response to a secondary latch clock signal, and to generate a secondary output signal in response to the latched primary output signal; and a composite clock generator that is arranged to generate a composite clock signal in response to a first input clock signal and a second input clock signal, wherein the primary latch clock signal is generated in response to the composite clock signal and the secondary latch clock signal is coupled to or generated in response to the second input clock signal, or the primary latch clock signal is coupled to or generated in response to the first input clock signal and the secondary latch signal is generated in response to the composite clock signal; wherein the first input clock is received at a first clock input that is coupled to a first clock tree, and the second input clock is received at a second clock input that is coupled to a second clock tree, the first clock tree including buffers exclusive of the second clock tree, and the second clock tree including buffers exclusive of the first clock tree.