Patent ID: 7402463

Claim:
A method of fabricating a semiconductor structure comprising: providing a structure including an insulator having lithography defined via and line openings, said structure further comprising an underlying insulator including an underlying interconnect, said insulator is separated from said underlying insulator by a dielectric film, said dielectric film having an opening which exposes portions of said underlying interconnect; forming an organic planarizing material on said structure to fill said via and line openings with said organic planarizing material; forming an oxide layer having at least one opened area for forming an anti-fuse structure, said at least one opened area is located above a pair of adjacent line openings, wherein said at least one opened area is formed by lithography and etching through said oxide layer stopping on said organic planarizing material; removing at least a portion of said organic planarizing material within said at least one opened area to expose a portion of each pair of said adjacent line openings; embedding an electrically conductive layer selected from one of Ta, TaN, W, Cu, Al, Pt, Pd, Ru, Rh, Ag, and Au in said insulator between said pair of adjacent line openings utilizing atomic layer deposition; removing said oxide layer and remaining organic planarizing material by a combination of chemical etching and stripping; filling said vias and line openings with at least an electrically conductive interconnect material selected from Cu, Al, Al(Cu) and W; planarizing said electrically conductive interconnect material to an upper surface of said insulator, wherein said planarizing removes said embedded electrically conductive layer from an upper horizontal surface of said insulator forming at least a pair of adjacent interconnects comprising a buried electrically conductive layer surrounding a portion of each respective interconnect, each buried first electrically conductive layer is separated by a dielectric region which permits current flow when a bias is applied to one of said interconnects of said pair; and forming a dielectric capping layer atop said insulator including said pair of adjacent interconnects.