Patent ID: 8649233

Claim:
A semiconductor device comprising: a plurality of memory cells that are arranged in a matrix manner and identified by an X-address signal and a Y-address signal; a first data amplifier that connects to a first memory cell identified among the plurality of memory cells by an X-address signal and a selection signal obtained by predecoding a Y-address signal, amplifies data read from the first memory cell during a read operation, and amplifies data to be written into the first memory cell during a write operation; a second data amplifier that connects to a second memory cell identified among the plurality of memory cells by the X-address signal and a delayed selection signal obtained by delaying the selection signal, amplifies data read from the second memory cell during a read operation, and amplifies data to be written into the second memory cell during a write operation; a generator that generates a delayed operation clock signal by delaying an operation clock signal that defines an operation timing of said first data amplifier; and a timing controller that receives a first control signal that controls operation of said first data amplifier and a second control signal that controls operation of said second data amplifier, outputs the first control signal to said first data amplifier at timing according to the operation clock signal, and outputs the second control signal to said second data amplifier at a timing according to the delayed operation clock signal.