Patent ID: 8193840

Claim:
A system timer, comprising: a divider unit configured to fractionally divide a first clock signal and output a second clock signal having an asymmetric duty ratio; and an interrupt generation unit configured to count a cycle of the second clock signal and output an interrupt signal according to the count, wherein the divider unit comprises: a fractional divider configured to count a cycle of the first clock signal according to a first control value and output a fractionally divided first clock signal in response to fractionally dividing the first clock signal according to a count value resulting from counting the cycle of the first clock signal; and a duty ratio adjuster configured to accumulate a second control value according to the fractionally divided first clock signal compare the accumulated second control value with a first reference value, and output a control signal for adjusting a duty ratio of the fractionally divided first clock signal according to a result of comparing the accumulated second control value with the first reference value, wherein the duty ratio adjuster comprises: an accumulating comparator configured to accumulate the second control value according to the fractionally divided first clock signal, compare the accumulated second control value with the first reference value, and output a comparative signal according to the result of comparing the accumulated second control value with the first reference value, and an accumulator configured to output the control signal to increase the first control value according to the comparative signal output from the accumulating comparator, wherein the fractional divider increases a cycle of the first clock signal according to the increased first control value, fractionally divides the first clock signal with the increased cycle, and outputs the second clock signal having the asymmetric duty ratio.