Patent ID: 7642586

Claim:
An integrated circuit comprising a memory cell array, comprising: a semiconductor body; a plurality of cell transistor devices formed along a plurality of parallel active area stripes of said body, said active area stripes running in a first direction and being laterally insulated from each other by intervening insulation trenches; each of said cell transistor devices comprising: a pillar formed in said semiconductor body; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on a bottom of said gate trench and surrounding a lower region of said pillar; a gate formed on said gate dielectric in said gate trench and surrounding a lower region of said pillar; and 1 a second source/drain region formed in an upper region of said semiconductor body adjoining said gate trench; a plurality of parallel bitlines running in a second direction and being connected to respective second source/drain regions of said cell transistor devices; a plurality of wordlines running in a third direction and connecting the respective gates of said cell transistor devices associated with different bitlines; and a plurality of cell capacitor devices being connected to respective first source/drain regions of said cell transistor devices.