Patent ID: 7308065

Claim:
A delay locked loop circuit, comprising: a first loop circuit including a first adjustable delay section to provide a first clock signal having a controlled phase relationship with respect to an external clock signal; and a second loop circuit, coupled to the first loop circuit, the second loop circuit comprising: a first phase detector to receive an input clock signal and a first feedback clock signal, the first phase detector to provide a signal that is representative of a phase difference between the first feedback clock signal and the input clock signal; a first control circuit coupled to the first phase detector, the first control circuit to provide a plurality of control signals based on the signal that is representative of the phase difference between the first feedback clock signal and the input clock signal; and a selection block coupled to the first adjustable delay section, the selection block to adjust a phase of a second clock signal based on the plurality of control signals and the first clock signal, wherein the second clock signal is distinct from the first clock signal and is used to generate the first feedback clock signal.