Patent ID: 8768678

Claim:
A method of simulating a circuit design using a compiled hardware description language (HDL) specification of the circuit design, the method comprising, for each simulation cycle: determining a set of HDL processes to be executed in the simulation cycle, each HDL process of the set of HDL processes including one or more compiled HDL statements of the compiled HDL specification to be executed in the simulation cycle; scheduling the set of HDL processes for execution on two or more process threads as a function of a respective simulation cost associated with each HDL process of the set and a respective runtime state of each HDL process in the simulation cycle, wherein the scheduling includes determining associated simulation costs of HDL statements in each HDL process of the set; determining a resulting simulation cost of a conditional statement in an HDL process of the set, the conditional statement conditioning execution during simulation between a first set of one or more statements and a second set of one or more statements based on whether a condition of the conditional statement evaluates to true or false, and said resulting simulation cost of the conditional statement being determined as a sum of a first term and a second term, wherein: the first term is a sum, scaled by a probability of the condition evaluating to true, of a simulation cost for the conditional statement plus a simulation cost of the first set of one or more statements; and the second term is a sum, scaled by a probability of the condition evaluating to false, of the simulation cost for the conditional statement plus a simulation cost of the second set of one or more statements; and executing, on a processor, an HDL process of the set in the simulation cycle using one of the two or more process threads in response to scheduling the HDL process of the set for execution by the one of the two or more process threads.