Patent ID: 8351541

Claim:
A data processing apparatus for communicating data bits via a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising: a parity interleaver configured to perform parity interleaving on a Low Density Parity Check (LDPC) encoded data bits obtained by LDPC encoding the data bits according to a parity check matrix of an LDPC code, which includes a parity matrix corresponding to parity bits of an LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position, a mapping unit configured to map the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals, a symbol interleaver configured to read-into a symbol interleaver memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the symbol interleaver memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals of the OFDM symbol, and an address generator configured to generate the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the address generator comprising: a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation code to form an address of one of the OFDM sub-carriers, and a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately thirty two thousand, the linear feedback shift register has fourteen register stages with a generator polynomial for the linear feedback shift register of R′ i [13]=R′ i-1 [0]⊕R′ i-1 [1]⊕R′ i-1 [2]⊕R′ i-1 [12], and the permutation code forms, with an additional bit, a fifteen bit address R i [n] for the i-th data symbol from the bit present in the n-th register stage R′ i [n] in accordance with the table: R′ i bit positions 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R i bit positions 6 5 0 10 8 1 11 12 2 9 4 3 13 7.