Patent ID: 8420487

Claim:
A method for realizing a power electronic MOS device comprising: making a thick oxide layer grown from a semiconductor layer; providing a first mask on said thick layer to define a plurality of areas to be realized as gate oxides; anisotropically etching the thick layer and realizing a plurality of central parts with high thickness; removing the first mask; realizing a thinner gate oxide layer with respect to said thick oxide layer to form portions lateral to said central parts and a plurality of insulating interconnection portions transversal with respect to said thinner gate layer and thick oxide layer; such that said thinner gate layer and thick oxide layer includes a thick central part and lateral portions with reduced thickness, and a plurality of insulating interconnection portions coupling said lateral portions; depositing, on top of said semiconductor layer, a conductive layer; providing a providing a second mask of the conductive layer to define a gate structure comprising a conductive mesh that includes a plurality of first conductive portions overlapped onto said central part of said gate oxide and a plurality of conductive bridges overlapped onto said interconnection portions; anisotropically etching said central part of said gate oxide to define areas corresponding to a plurality of second conductive portions to be realized and overlapped onto said lateral portions; removing the second mask; said gate structure comprising said plurality of first conductive portions overlapped onto said lateral portions of said gate oxide and said conductive mesh comprising said plurality of second conductive portions overlapped onto said thick central part of said gate oxide interconnected to each other and onto said first gate conductive portions from said plurality of conductive bridges overlapped onto said interconnection portions.