Patent ID: 8343781

Claim:
A method for testing an integrated circuit, comprising the steps of: forming a plurality of scan chains, each scan chain formed by the steps of: forming a first endpoint; forming a second endpoint; forming a first metal layer, comprising a plurality of segments; forming a second metal layer, comprising a plurality of segments; forming a via layer, comprising a plurality of vias wherein each via is configured and disposed to connect a segment of the first metal layer to a segment of the second metal layer; wherein the step of forming the first metal layer comprises forming a segment connected to said first endpoint and also comprises forming a segment connected to said second endpoint; and wherein one of the layers formed is a functional layer, and wherein two of the layers formed are test layers; performing a resistance measurement between the first endpoint and second endpoint of each of the plurality of scan chains; indicating a failure if the resistance measurement exceeds a predetermined threshold; and wherein the step of forming a plurality of scan chains comprises the steps of: computing the number of scan chains as the number of endpoints divided by two; and computing the number of vias per scan chain as the total number of vias for a given level divided by the number of chains.