Patent ID: 7924960

Claim:
A system comprising: a first buffer configured to receive data at a first rate, and output the data at a second rate; a processing module configured to receive the data from the first buffer at the second rate, convert the data into processed data, and output the processed data at a third rate; and a second buffer configured to receive the processed data from the processing module at the third rate, and output the processed data at a fourth rate, the third rate being initially faster than the fourth rate to avoid a buffer underflow condition in the second buffer, wherein in response to the second buffer reaching a predetermined capacity, the processing module is further configured to temporarily stop (i) receiving data from the first buffer and (ii) outputting the processed data to the second buffer, and wherein in response to the second buffer reaching the predetermined capacity, the processing module is further configured to adjust the second rate to avoid a buffer overrun condition in the first buffer.