Patent ID: 8140830

Claim:
A circuit arrangement, comprising: a high power/high performance execution unit configured to execute instructions from an instruction set; a reduced power/reduced performance execution unit configured to execute instructions from the instruction set, wherein the reduced power/reduced performance execution unit has a lower power consumption and lower performance relative to the high power/high performance execution unit and is functionally equivalent to the high power/high performance execution unit such that instructions from the instruction set are interchangeably executable by either of the reduced power/reduced performance and high power/high performance execution units; a first instruction buffer associated with a first hardware thread, the first instruction buffer configured to receive instructions associated with a first task having a higher performance requirement; a second instruction buffer associated with a second hardware thread, the second instruction buffer configured to receive instructions associated with a second task having a lower performance requirement; at least one issue queue; multithreaded routing logic coupled to the reduced power/reduced performance and high power/high performance execution units and configured to route instructions stored in the first and second instruction buffers to the reduced power/reduced performance and high power/high performance execution units for execution thereby, the multithreaded routing logic configured to route instructions associated with the first task to the high power/high performance execution unit via the at least one issue queue based upon the higher performance requirement for the first task, and to route instructions associated with the second task to the reduced power/reduced performance execution unit via the at least one issue queue based upon the lower performance requirement for the second task.