Patent ID: 7805578

Claim:
An apparatus, comprising: a plurality of memories; a plurality of processing units respectively coupled to said plurality of memories; an interface coupled to said plurality of memories by a plurality of buses, at least one of the plurality of buses being at least one data bus for transferring data from said interface to said plurality of memories, said interface configured to control access to said plurality of memories using an identifier to identify a memory location in one of said plurality of memories and another memory location in another of said plurality of memories; and an array controller coupled to said plurality of processing units by a control bus for sending at least one of instructions and commands to each of the plurality of processing units, and coupled to said interface by a broadcast bus, said array controller configured to provide broadcast data to at least said memory location via said interface and said at least one data bus by first providing said broadcast data to said interface via said broadcast bus, and control, via said at least one of instructions and commands sent via said control bus, at least one of said plurality of processing units that corresponds to said memory location to receive said broadcast data from said memory location, wherein said at least one data bus is thereby used to provide both said data and said broadcast data from said interface to said memory location, and said interface is further configured to identify said memory locations substantially simultaneously.