Patent ID: 8541830

Claim:
A nonvolatile semiconductor memory device comprising a plurality of memory cell array layers being stacked, each memory cell array layer including: a plurality of semiconductor layers, each extending in a first direction and being in parallel to each other; gate insulating layers formed on the semiconductor layers; a plurality of floating gates formed on the gate insulating layers and arranged in the first direction; inter-gate insulating layers adjacent to the floating gates; and a plurality of control gates that face the floating gates via the inter-gate insulating layers at both sides of the floating gates in the first direction and that extend in a second direction intersecting the first direction, in the cell array layers adjacent to each other in a stacking direction, the control gates of the cell array layer in a lower cell array layer and the control gates of the cell array layer in an upper cell array layer intersecting each other, the floating gates in the lower cell array layer and the semiconductor layers on the floating gates being aligned in position with each other.