Patent ID: 8598589

Claim:
An array substrate comprising: a transistor area in which a transistor is formed; a capacitor area in which a capacitor is formed, wherein the capacitor is electrically connected to the transistor; a light transmittance area adjacent to at least one of the transistor area and the capacitor area; a first insulating layer formed in at least one of the transistor area and the capacitor area, wherein the first insulating layer is not formed in the light transmittance area, and wherein the first insulating layer is formed at least in the capacitor area, and is used as a dielectric layer of the capacitor; and a second insulating layer having i) a first portion arranged to substantially overlap with the first insulating layer in the at least one area, and ii) a second portion formed in the light transmittance area, wherein the first insulating layer has substantially the same etched surface as at least one electrode of the capacitor.