Patent ID: 7990753

Claim:
A nonvolatile semiconductor memory device having a plurality of unit cell arrays having memory cells each containing a first wiring and a second wiring intersecting each other, and a variable resistive element arranged at each intersection of said first wiring and said second wiring and electrically rewritable to nonvolatilely store a resistance value as data, characterized by comprising: a control circuit for applying a predetermined voltage to a memory cell in selectively accessing said memory cell; wherein said control circuit accumulates a predetermined electric charge in a parasitic capacitance of said memory cell included in a first unit cell array that is a specific unit cell array and not accessed at a first time, while on the other hand, accumulates a predetermined electric charge in a parasitic capacitance of said memory cell included in a second unit cell array that is said specific unit cell array other than said first unit cell array and not accessed at a second time after the passage of a predetermined time from said first time.