Patent ID: 7778283

Claim:
A system comprising: at least two network devices electrically connected, each device connected to a timing bridge device having an inbound path and an outbound path, each path including, a shift register interposing a physical layer and a media access control layer, a packet recognizer receiving the output of the shift register, the shift register loading a message, the inbound path further including an adder, having a positive input connected to its packet recognizer and a negative input, having an output connected to its shift register for adjusting timing in the message, and the outbound path further including an adder, receiving a first and a second input from its packet recognizer and an output connected to its media access control layer; a timer connecting to the packet recognizer of the inbound and the outbound path, generating timer readings; and a controller connecting to the timer and the packet recognizer of the outbound path, receiving external control signals; wherein the packet recognizers have time calibrated access paths to the timer so that when a timing packet is detected by one of the packet recognizers an appropriate timestamp can be generated.