Patent ID: 8723712

Claim:
A digital to analog converter, comprising: at least one current steering source, each comprising: a data current source providing a source current to a source node; a first switch having a first terminal coupled to said source node and having a second terminal coupled to a first control node, and a second switch having a first terminal coupled to said source node and having a second terminal coupled to a second control node, wherein said first and second switches are controlled by a data bit and an inverted data bit, respectively, which are collectively configured to activate one of said first and second switches at a time to steer said source current to a selected one of said first and second control nodes; a first buffer device having a first terminal coupled to said first control node and having a second terminal coupled to a first current output node and a second buffer device having a first terminal coupled to said second control node and having a second terminal coupled to a second current output node; and a first activation current source which is configured to provide a first activation current to said first buffer device via said first control node, and a second activation current source which is configured to provide a second activation current to said second buffer device via said second control node; and a master replica bias network, comprising: a replica buffer device coupled to a replica control node and which is configured to replicate biasing of at least one of said first and second buffer devices; and a master buffer amplifier having an output configured to drive said first and second buffer devices and said replica buffer device in parallel to maintain said first, second and replica control nodes at a common master control voltage.