Patent ID: 8530290

Claim:
A method of fabricating a thin film transistor, comprising: preparing a substrate; forming an amorphous silicon layer on the substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization inducing metal; forming a semiconductor layer by patterning the polycrystalline silicon layer; forming a gate insulating layer on the semiconductor layer; forming a photoresist pattern exposing an edge region of the semiconductor layer on the substrate having the gate insulating layer, and doping a first impurity into the edge region, the edge region being formed along a length and in an outer region of the semiconductor layer; forming a gate electrode after removing the photoresist pattern; forming source and drain regions and a channel region by doping a second impurity into the semiconductor layer using the gate electrode as a mask; annealing the substrate so as to remove the crystallization inducing metal from the semiconductor layer; forming an interlayer insulating layer on the gate electrode; etching the interlayer insulating layer and the gate insulating layer to form a first contact hole exposing the source region and a portion of the edge region adjoining the source region and a second contact hole exposing the drain region and a portion of the edge region adjoining the drain region; and forming a source electrode in the interlayer insulating layer and first contact hole electrically connected to the source region and the portion of the edge region adjoining the source region and forming a drain electrode in the interlayer insulating layer and second contact hole electrically connected to the drain region and the portion of the edge region adjoining the drain region.