Patent ID: 7657233

Claim:
A device for calculating feedback signaling message (FSM) bits, comprising: a circuit configured to calculate feedback signaling message (FSM) bits by means of which the signals sent from two antennas of a base station are influenced with reference to their phase difference and/or their amplitudes with the aid of the two estimated channel impulse responses, wherein the circuit is in hard-wired form, wherein the circuit is configured to generate a first complex phasor from first components of the two channel impulse responses and a second complex phasor from second components of the two channel impulse responses, and further configured to produce a first FSM bit by a rotation and projection of the first phasor and a comparison of the rotated and projected first phasor with a constant threshold value and configured to produce a second FSM bit by a rotation and projection of the second phasor and a comparison of the rotated and projected second phasor with the constant threshold value, and wherein the first and the second components of the two channel impulse responses comprise different components.