Patent ID: 8742851

Claim:
A two-stage dual-output g m cell having an input, a first output and a second output, the dual-output g m cell comprising: a first transistor having a source, a drain, and a gate, the gate coupled to the input, the drain coupled to a first end of a first inductor; a second transistor having a source, a drain, and a gate, the drain of the second transistor coupled to the second output, the gate of the second transistor coupled to a second end of the first inductor and a first end of a second inductor; a third transistor having a source, a drain, and a gate, the drain of the third transistor coupled to the first output, and a parallel R-L circuit, one end of the parallel R-L circuit coupled to a second end of the second inductor, the other end of the parallel R-L circuit coupled to the source of the third transistor, wherein the parallel R-L circuit having a resistor and a third inductor connected in parallel to form a compensation network.