Patent ID: 7932735

Claim:
A system for testing chip I/O (input/output) circuits, comprising: a) an integrated circuit chip; b) a first driver transistor and a second driver transistor to form an output driver circuit connected to an I/O pad of said chip; c) a test transistor formed from said first driver transistor; d) a test logic connected to a selector circuit to control selection of said test transistor to produce a test current; e) a switch circuit controlled by said test logic to couple said test current from said I/O pad to a current comparator circuit on said chip, wherein said switch circuit couples test current from said I/O pad to a test bus to which is coupled a plurality of said I/O pads, whereby said test bus connects test current from said plurality of said I/O pads to the current comparator circuit; and f) an output of said current comparator circuit to produce a test result by comparing the test current to a reference current.