Patent ID: 7673118

Claim:
A multiprocessor system comprising: a network having a network topology; and a plurality of processors, each of said plurality of processors internally comprising: a central processing unit (CPU) including integer, scalar, floating point, and Boolean units; a local memory; a first and a second multi-ported network switch; an addressable C-register adapted for holding both transient and resident data items, said C-register connected to other C-registers located in neighboring processors for providing parallel communication between said C-register and said other C-registers via said first and second multi-ported network switches, said C-register is available for use by said central processing unit during vector computations upon completion of communication tasks and wherein communications between said C-registers occurs without accessing said local memory or said central processing unit; and a programmable communication unit; said network switches having log 2 P ports to the network; said plurality of processors interconnected in the network for collaborative task execution; said communication unit providing one or more dynamic switch configuration settings to said first and second multi-ported switches on each communication cycle of a communication task thereby providing vector-like communications among said plurality of processors, wherein on average one data item is communicated to its destination processor in every communication cycle; said CPU, local memory, and said communication unit coupled and configured to provide computations and vector-like communication tasks, utilizing said addressable C-register located within each of said plurality of processors.