Patent ID: 8813005

Claim:
A method of testing a module of a circuit design, comprising: tagging a plurality of flip-flops in a netlist of the module with respective path names of the flip-flops from a hardware description language (HDL) specification of the module; simulating with the netlist on a programmed processor; capturing event data to a first file during the simulating, for each event the event data describing a signal identifier, an associated signal value, and an associated timestamp; determining whether or not event data in the first file matches event data in a second file of event data; in response to a difference determined between the first file and the second file, determining an earliest occurrence of an event in the first file having an associated signal value of a first signal that does not match an associated signal value of a corresponding event in the second file; determining one of the plurality of flip-flops that output the first signal; and outputting the respective path name of the one flip-flop.