Patent ID: 7042930

Claim:
A system for indicating bit synchronization of a received signal spectrum spread by a spreading code modulating data bits having a bit duration between bit boundaries extending over and synchronized to an integer number of code periods of the spreading code, the system comprising, an integrate and dump clock generator for generating a reference integrate and dump clock having a reference integration period having a duration equal to the bit duration, and for generating staggered integrate and dump clocks from the reference integrate and dump clock, the staggered integrate and dump clocks respectively indicating offsets in code period increments between the reference integrate and dump clock and the bit boundaries, one of the staggered integrate and dump clocks is synchronously aligned with the bit duration, a hypothesis correlator for correlating the received signal with a replica code of the spreading code synchronized to the reference integrate and dump clock, the hypothesis correlator receiving the staggered integrate and dump clocks for respective integration and dumping over respective integration periods respectively staggered by the offsets for respectively generating hypotheses over the respective integration periods, and a selector for selecting one of the respective hypotheses for a respective one of the offsets as a synchronized offset for one of the respective integration periods as a synchronized integration period coherently synchronized to the bit boundaries for indicating bit synchronization.