Patent ID: 8250305

Claim:
In a processor, a method for providing data buffers partitioned from a cache array in a memory cache and configured to be read and written by an owning data flow controller, the method comprising: clearing cache directories associated with the processor to an initial state; initializing pre-selected cache lines to be reserved individual cache lines; determining a selected directory state that includes an ownership tag indicating a reserved state for the owning data flow controller to read and write from and to the reserved individual cache lines, the ownership tag indicating that data held in the reserved directory state is ineligible for data caching, wherein an absolute address field of an associated directory is not specified in response to the ownership tag being in reserved state, and the reserved individual cache lines are not used as part of the memory cache, and are read and written only by the owning data flow controller; in response to the desired cache state, sending load commands with an address and data; loading cache lines and cache line directory entries into the cache; storing the specified data in the corresponding cache line, and setting the directory state to the value specified.