Patent ID: 8817521

Claim:
A control method for at least one memory cell comprising a transistor and a resistor connected to the transistor in series between a first node and a second node, comprising: programming the memory cell in a programming mode, wherein the step of programming the memory cell comprises: providing a first controlling voltage to a gate of the transistor; providing a first setting voltage to the first node; and providing a second setting voltage to the second node; determining whether the memory cell has been successfully programmed; when the memory cell has been successfully programmed, impedance of the memory cell is in a first state, and when the memory cell has not been successfully programmed, a specific action is executed, wherein the specific action is to reset the memory cell, and the step of resetting the memory cell comprises: providing a second controlling voltage to the gate of the transistor, wherein the first controlling voltage is less than the second controlling voltage; providing a first reset voltage to the first node; and providing a second reset voltage to the second node, wherein the impedance of the memory cell is in a second state when the memory cell is successfully reset, and wherein the impedance of the memory cell in the second state is higher than the impedance of the memory cell in the first state; wherein the step of resetting the memory cell further comprises: determining whether the memory cell has been successfully reset; when the memory cell has been successfully reset, the impedance of the memory is in the first state; when the memory has not been successfully reset, at least one of the second controlling voltage, the first reset voltage and the second reset voltage is increased and the increased voltage is provided to the transistor.