Patent ID: 7825522

Claim:
A device comprising: a first pattern and a second pattern both created in an intermediate conductive layer of a chip, wherein said first pattern establishes a first of a plurality of plates of a first capacitor; at least one via created in an insulating layer above said intermediate conductive layer, wherein said via is aligned with said second pattern; and a first bump created in a top conductive layer above said insulating layer, wherein said first bump (i) is located directly above said first plate, (ii) establishes a second of said plates of said first capacitor, (iii) is suitable for flip-chip bonding and (iv) connects to said second pattern through said via such that both of said plates of said first capacitor are accessible in said intermediate conductive layer; and a third pattern and a fourth pattern both created in a lower conductive layer below said intermediate conductive layer, wherein (i) said third pattern is located under said first bump and establishes part of said first plate and (ii) said fourth pattern is connected to said second plate such that both of said plates of said first capacitor are accessible in said lower conductive layer.