Patent ID: 8762902

Claim:
A method for a computer system for detecting an invalid winding path in a layout design for the manufacture of electronic devices, the invalid winding path including one or more overlapping polygons, the computer system having one or more processors, a computer-readable storage device, and a user interface device, the method comprising: providing a layout design file having at least one pattern layer, the at least one pattern layer having a winding path; generating a first reticle pattern from the winding path using a first calculation scheme by means of the one or more processors; generating a second reticle pattern from the winding path using a second calculation scheme by means of the one or more processors; comparing the first reticle pattern with the second reticle pattern; and in the event that there is no match: outputting a text message indicating a presence of one or more overlapping polygons; and in the event that there is a match: generating a reticle pattern file.