Patent ID: 7167937

Claim:
A bus system comprising: a system bus serving, at the least, as a control bus and a data bus; and master I/F (Interface) circuits and slave I/F circuits, being connected through said system bus, so that at the least, commands and data are exchanged by master core circuits, connected to said master I/F circuits, and by slave core circuits, connected to said slave I/F circuits; wherein said slave I/F circuits include: enable/disable notification holding units for respectively holding enable/disable notifications, obtained from said slave core circuits, that indicate whether various process requests, issued by said master core circuits, are capable of being coped with, and enable/disable notification transmitters for, upon receiving said commands from said master I/F circuits, returning said enable/disable notifications without transmitting said commands to said slave core circuits; and wherein said master I/F circuits include: command transmitters for respectively receiving, from said master core circuits, commands for said process requests issued to said slave core circuits and for transmitting said commands to said slave I/F circuits; size detectors for employing a transmission command, which instructs said slave core circuits to receive master data transmitted by said master core circuits, to detect the amount of said master data; data holding units for temporarily holding said master data for which the detected amount is smaller than a predetermined amount; enable notification transfer units for, when said enable notifications are returned from said slave I/F circuits while said master data are not temporarily stored, transmitting said enable notifications to said master core circuits; data transfer units for, upon receiving said enable notifications, transferring to said slave core circuits said master data received from said master core circuits; and data transmitters for, when said enable notifications are received from said slave I/F circuits while said master data are temporarily stored, transmitting said master data to said slave I/F circuits without transmitting said enable notifications to said master core circuits.