Patent ID: 8034714

Claim:
A method of fabricating a semiconductor device, the method comprising: providing a underlying layer including active regions and device isolation layers, each active region having first and second conductive regions; forming conductive line patterns over the underlying layer, each conductive line pattern passing between the first and the second conductive regions; forming an interlayer insulating layer over the underlying layer so as to fill between the conductive line patterns; etching the interlayer insulating layer to form a trench extending across the conductive line patterns and passing over the device isolation layer between the active regions; forming an insulating pattern within the trench, the insulating pattern being different material from the interlayer insulating layer; wet etching the interlayer insulating layer using the insulating pattern and the conductive line pattern as an etch mask to form a contact hole for any of the first and the second conductive regions; and forming a contact plug within the contact hole to electrically couple the contact plug and any of the first and the second conductive regions.