Patent ID: 7932135

Claim:
A method of manufacturing a thin film transistor array substrate, comprising: sequentially depositing a first conductive material, a gate insulating layer, a semiconductor layer, and a second conductive material on a substrate; forming a first resist pattern having three height levels on the second conductive material; forming a gate line, a data line that crosses the gate line and has first and second slit units, a source electrode connected to the data line and having a third slit unit, and a drain electrode positioned opposite the source electrode with a channel interposed between the source electrode and the drain electrode and having a fourth slit unit, through a plurality of etching processes using the first resist pattern; depositing a passivation layer on an entire surface of the substrate, including a portion in which the first resist pattern is removed, and then forming a second resist pattern on the passivation layer; removing the second resist pattern and the passivation layer in a pixel region through an etching process; depositing a third conductive material on an entire surface of the substrate including the pixel region; removing the second resist pattern and the third conductive material deposited on the remaining passivation layer through a lift-off process; and forming a pixel electrode connected to the drain electrode in the pixel region.