Patent ID: 7049230

Claim:
In a semiconductor device having a silicon substrate having a gate electrode, a junction area, and an insulating interlayer, wherein a contact hole exposing the junction area is formed in a portion of the insulating interlayer, a method of forming a contact plug in the contact hole comprising the steps of: i) performing a plasma process removing natural oxides on the exposed surface of the junction area; ii) depositing a first silicon layer in the contact hole without completely filling the contact hole and on the insulating interlayer, wherein the first silicon layer includes epitaxial silicon in the lower portion of the contact hole, amorphous silicon in the portion above the lower portion of the contact hole, and polycrystalline silicon on the insulating interlayer; iii) applying heat to the first silicon layer transforming the amorphous silicon into epitaxial silicon in the portion above the lower portion of the contact hole; iv) depositing a second silicon layer on the first silicon layer; and v) performing a CMP process with respect to the first and second silicon layers so as to expose the insulating interlayer.