Patent ID: 8711162

Claim:
An arbitration circuit usable with an electronic apparatus, comprising: a latch unit comprising a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation; a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate a first internal signal to activate a scanning operation and a second internal signal to activate a reading/writing operation, to maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation, an information signal generating unit to generate an information signal indicating a section of a scanning operation or a reading/writing operation of the memory in response to any one of the first internal signal and the second internal signal; a control signal generating unit to generate a control signal in which a clock is activated in correspondence to the activation of each of the first internal signal and the second internal signal and to control the scanning operation or the reading/writing operation of the memory to be performed; and a multiplexer to receive a scan address and a read/write address and to selectively output any one address in response to the information signal wherein during a conflict of the first internal signal and the second internal signal, either signal, once activated, is maintained without interruption until completion of its respective operation.