Patent ID: 8008200

Claim:
A method of forming a dual damascene structure in the manufacture of an integrated circuit, comprising: providing a conductor in a dielectric layer; forming a barrier layer as a via etch-stop layer over the conductor and the dielectric layer; forming an interlevel dielectric layer over the barrier layer; forming a lower dielectric hardmask layer over the interlevel dielectric layer; forming an upper dielectric hardmask layer directly on the lower dielectric hardmask layer; forming and patterning a first resist layer over the upper dielectric hardmask layer to define a via opening etch profile; selectively etching the upper dielectric hardmask layer using the via opening etch profile to form a via opening through the upper dielectric hardmask layer but not through the lower dielectric hardmask layer; removing the patterned first resist layer with the via opening formed through the upper dielectric hardmask layer but not through the lower dielelectric hardmask layer; after removing the patterned first resist layer and with the via opening formed though the upper dielectric hardmask layer but not though the lower dielectric hardmask layer, forming a multi-layer resist stack, including: forming an underlayer directly on the upper dielectric hardmask layer including within the via opening; forming an intermediate hardmask layer over the underlayer; and forming a second resist layer over the intermediate hardmask layer; patterning the second resist layer to define a trench opening etch profile over the via opening; selectively etching the intermediate hardmask layer and underlayer using the trench opening etch profile of the patterned second resist layer to form a trench opening pattern in the underlayer down to the upper dielectric hardmask layer; simultaneously etching through the upper dielectric hardmask layer and the lower dielectric hardmask layer using the trench opening pattern to form a partial trench opening in the interlevel dielectric layer; the etching operating on the via opening in the upper hardmask layer to extend the via opening below the trench opening to form a partial via opening in the interlevel dielectric layer; further simultaneously etching the interlevel dielectric layer to extend the partial trench opening down within the interlevel dielectric layer and to extend the partial via opening down to the barrier layer; and etching the barrier layer through the further extended via opening, to further extend the partial via opening down to the conductor.