Patent ID: 7179709

Claim:
A method of fabricating a non-volatile memory device having a local silicon-oxide-nitride-oxide-silicon (SONOS) gate structure, comprising: providing a semiconductor substrate having a cell transistor area, a high voltage transistor area, and a low voltage transistor area; forming at least one memory storage pattern defining a cell gate insulating area on the semiconductor substrate within the cell transistor area; forming an oxidation barrier layer on the semiconductor substrate within the cell gate insulating area; forming a lower gate insulating layer on the semiconductor substrate within the high voltage transistor area; forming a conformal upper insulating layer on the memory storage pattern, the oxidation barrier layer, and the lower gate insulating layer; and forming a low voltage gate insulating layer to a thickness less than a combined thickness of the upper insulating layer and the lower gate insulating layer on the semiconductor substrate within the low voltage transistor area.