Patent ID: 7361973

Claim:
A semiconducting device comprising: a semiconductor substrate having a mesa portion and recessed surfaces, wherein said mesa portion contains a mesa top surface and mesa sidewalls located above and adjoined to said recessed surfaces, and wherein said mesa top surface is vertically offset from said recessed surfaces; a singled gated transistor comprising a gate region including a gate dielectric and a gate electrode, wherein said gate dielectric abuts said mesa top surface and is disjoined from said recessed surfaces and said mesa sidewalls; silicide regions abutting said mesa top surface, said mesa sidewalls, and said recessed surfaces, wherein a portion of said silicide region is located below said recessed surfaces and another portion of said silicide region is located above said mesa top surface; source and drain regions located under and aligned to said recessed surfaces; and a nitride liner abutting said silicide regions not abutting said mesa top surface, wherein said nitride liner provides a longitudinal stress to a device channel underlying said gate region in said mesa portion of said semiconductor substrate.