Patent ID: 7534679

Claim:
A method for producing a semiconductor circuit arrangement, the method comprising the steps of: a) preparing a semiconductor substrate with a bipolar transistor region and a field effect transistor region; b) forming a first electrically conductive layer at a surface of the semiconductor substrate for the purpose of realizing a base connection layer in the bipolar transistor region and a first split gate layer in the field effect transistor region; c) forming an implantation mask over less than an entire surface of the first electrically conductive layer; d) carrying out a first collector implantation for the purpose of forming a collector connection zone in the bipolar transistor region of the semiconductor substrate, the collector connection zone being formed in areas of the substrate not covered by the implantation mask; e) forming a hard mask layer at a surface of the first electrically conductive layer; f) forming a first etching mask at a surface of the hard mask layer for the purpose of patterning the hard mask layer and for the purpose of uncovering at least one emitter window in the bipolar transistor region; g) patterning a base connection layer using the patterned hard mask layer; h) carrying out a second collector implantation using the patterned hard mask layer and the base connection layer for the purpose of forming a collector zone in the surface of the semiconductor substrate; i) forming a base layer in the region of the emitter window at the surface of the collector zone and at the sidewalls of the base connection layer; j) forming a second etching mask at a surface of the patterned hard mask layer for the purpose of uncovering a field effect transistor region; k) patterning the patterned hard mask layer anew using a second etching mask for the purpose of uncovering a first electrically conductive layer in the field effect transistor region; l) forming a second electrically conductive layer at a surface of the uncovered first electrically conductive layer, the patterned hard mask and the base layer; m) forming a third etching mask at a surface of the second electrically conductive layer; n) patterning a second electrically conductive layer using a third etching mask for the purpose of realizing an emitter layer in the region of the emitter window and a second split gate layer in the field effect transistor region; and o) completing a bipolar transistor in the bipolar transistor region and a field effect transistor in the field effect transistor region.