Patent ID: 7315472

Claim:
A non-volatile memory device comprising: a plurality of memory blocks each of the memory blocks including memory cells, the memory cells being connected in series to bit lines, respectively, wherein each of the plurality of memory blocks comprises: a first sub-memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines associated with the first group of memory cells, respectively, and second select transistors connected to a common source line; and a second sub-memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines associated with the second group of memory cells, respectively, and fourth select transistors connected to the common source line; wherein memory cells within each memory block are connected to N word lines, the first sub-memory block is connected to 1/2N word lines of the N word lines, and the second sub-memory block is connected to the remaining 1/2N word lines of the N word lines, and wherein 1/2N word lines of the first sub-memory block and first and second select lines of the first and second select transistors are connected to 1/2N global word lines and first and second global select lines, respectively, through a first sub block select switch unit, and 1/2N word lines of the second sub-memory block and third and fourth select lines of the third and fourth select transistors are connected to the remaining 1/2N global word lines and the first and second global select lines, respectively, through a second sub block select switch unit.