Patent ID: 7324395

Claim:
A semiconductor memory device having an open bitline architecture comprising: a first memory cell array; a second memory cell array; a pair of bitlines comprising a first bitline of the first memory cell array and a second bitline of the second memory cell array; a sense amplifier connected between the pair of bitlines; a first circuit that is configured to control the connection of the first bitline to the sense amplifier in response to a first control signal; a second circuit that is configured to control the connection of the second bitline to the sense amplifier in response to a second control signal; a third circuit that is configured to precharge the first bitline to a predetermined voltage in response to a first precharge signal; and a fourth circuit that is configured to precharge the second bitline to the predetermined voltage in response to a second precharge signal, wherein the second circuit is configured to disconnect the second bitline from the sense amplifier after termination of a sensing operation that is performed on the first memory cell array, which is activated, and wherein the fourth circuit precharges the second bitline after the second bitline is disconnected from the sense amplifier.