Patent ID: 7985651

Claim:
A method of fabricating a semiconductor device, comprising: forming a gate trench in a semiconductor substrate to define source/drain regions separated from each other by the gate trench, wherein the semiconductor substrate is exposed through the gate trench and includes impurities of a first conductivity type, the source/drain regions include impurities of a second conductivity type different from the first conductivity type, and the concentration of the second conductivity type impurities increases as the impurities approach the surfaces of the source/drain regions; forming a differential gate dielectric layer along the surfaces of the source/drain regions and the semiconductor substrate exposed through the gate trench; and forming a gate electrode filling the gate trench, wherein the differential gate dielectric layer has a first thickness between the gate electrode and the semiconductor substrate and has a second thickness greater than the first thickness between the gate electrode and the source/drain regions, and wherein forming the gate trench to define source/drain regions includes, implanting Arsenic (As) into the semiconductor substrate to form a first impurity region, implanting Phosphorous (P) into the semiconductor substrate to form a second impurity region under the first impurity region, implanting the first conductivity type impurities into a lower part of the second impurity region to form a third impurity region, and implanting the first conductivity type impurities into a lower part of the third impurity region to form a fourth impurity region.