Patent ID: 8274834

Claim:
A semiconductor memory device comprising: a memory cell array having a block including a plurality of memory cell units formed in a well, each memory cell unit including a plurality of electrically rewritable nonvolatile memory cells connected in series, and a first select gate transistor coupled to a memory cell at an end of the memory cell unit between the memory cell unit and a bit line; plural word lines each coupled to a corresponding one of the memory cells in the memory cell units; a first selection gate line coupled to the first select gate transistor; and a control circuit configured to control a write operation that writes data in one selected memory cell in the memory cell unit, the write operation includes determining an initial write pulse data voltage, applying the initial write pulse data voltage to a word line of the one selected memory cell in the memory cell unit, and incrementing the write pulse data voltage if the data is not successfully written, and the control circuit is configured to control the determining the initial write pulse data voltage to be a first voltage in a case that the selected memory cell is the memory cell at the end of the memory cell unit, and to be a second voltage in the case that the selected memory cell is a memory cell other than the memory cell at the end of the memory cell unit.