Patent ID: 8803191

Claim:
A lateral thyristor device, comprising: a semiconductor layer which is positioned atop a layer of insulator, and is completely isolated by trenches on all sides thereof; a heavily-doped n+ emitter region at one end of a length of said semiconductor layer, and a lightly doped p-type base region adjacent said n+ emitter region, and a lightly doped n-type base region adjacent to said p-type base region but not to said n+ emitter region, and a heavily doped p+ emitter region which abuts said lightly doped n-type base region but not said lightly doped p-type base region nor said heavily doped n+ emitter; a first current carrying terminal contacting the n+ emitter region; a second current carrying terminal contacting the p+ emitter region, wherein the first current carrying terminal and the second current carrying terminal are located over a top surface of the semiconductor layer to form a lateral current-conduction device; a plurality of embedded gate electrodes spaced along the boundary between said p-type base region and said n-type emitter region, each said gate electrode being capacitively coupled to a portion of said p-type base region which is nearest said n+ emitter region; all of said gate electrodes which are adjacent said n+ emitter region being electrically connected together; wherein, when said gate inverts an adjacent portion of said p-type base region, a population of electrons, at a surface of said gate nearest said n-type base region provides a virtual emitter and thereby sustains latchup once conduction has been initiated; and wherein the combination of said n+ emitter and said p-type base, and the combination of said p+ emitter and said n-type base, are not jointly able to sustain latching if said gate has not inverted adjacent portions of said p-type base region.