Patent ID: 7389404

Claim:
A matrix data processor comprising: an arithmetic logic unit; a register set coupled to said arithmetic logic unit, said register set comprising: a physical register set; at least a first configuration register, said at least a first configuration register comprising a first plurality of matrix configuration parameters; and at least a second configuration register, said at least a second configuration register comprising a second plurality of matrix configuration parameters; a memory coupled to said arithmetic logic unit and to said register set; and a control program residing in said memory, said control program being configured to receive an instruction and, based on said instruction, select one of said at least a first configuration register and said at least a second configuration register, along with the corresponding plurality of matrix configuration parameters, said control program being configured to construct a first logical two-dimensional source matrix and a second logical two-dimensional source matrix using said instruction and said first or second plurality of matrix configuration parameters, said control program being configured to instruct said arithmetic logic unit to perform at least one matrix operation using said first and second logical two-dimensional source matrices as operands.