Patent ID: 8484488

Claim:
An apparatus comprising: a first core of a plurality of cores having a first instruction set to execute a program at a first performance level, the first core stopping executing the program when a triggering event occurs; a second core of the plurality of cores having a second instruction set compatible with the first instruction set and having a second performance level different than the first performance level, the second core being in a power down state when the first core is executing the program; and a circuit coupled to the first and second cores, the circuit upon receiving the triggering event to provide a signal to the first core to commence a power down sequence, the circuit to power up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level, wherein the circuit provides that only one of the plurality of cores is to execute the program at any time, the other cores of the plurality of cores being powered down.