Patent ID: 7462899

Claim:
A semiconductor memory device, comprising: a semiconductor substrate in which a cell region and a core and peripheral region are defined; isolation layers formed in the semiconductor substrate to define active regions therein; a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region, wherein each one of the first and second gate electrode structures comprises a conductive layer and a gate spacer formed on sidewalls of the conductive layer; source/drain regions formed in the active regions on respective sides of each of the first and second gate electrode structures; self-aligned contact pads formed though an insulating interlayer formed on the semiconductor substrate to contact a source/drain region in the cell region; etch stoppers formed on the insulating interlayer and interposed between the self-aligned contact pads in the cell region; and top spacers formed on at least sidewalls of the gate spacers of the second gate electrode structure, wherein respective bottom surfaces of the etch stoppers and the to spacers are coplanar.