Patent ID: 7360069

Claim:
A multi-processor system that conforms to a cache coherency protocol, the system comprising: a processor that transmits a source request for a data fill associated with a cache line in response to a cache miss, the processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills received from one or more other processors of the multi-processor system in response to one or more source requests, a speculative data fill being a copy of a requested data fill that has an undetermined coherency state, wherein the processor pipeline receives a coherent data fill from the multi-processor system after a speculative data fill is received in response to the one or more source requests; and a log that retains executed load instruction entries associated with executed program instructions, the executed load instruction entries being retired if a cache line associated with data of a speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.