Patent ID: 8012796

Claim:
A method for fabricating a semiconductor package structure, comprising: providing a silicon substrate having a thickness t 1 between first and second opposing planar surfaces; forming a pattern of conductive vias to a depth d below the first surface of silicon substrate, which is less than the thickness t 1 of the silicon substrate; forming a wiring layer on the first surface of the silicon substrate, wherein the wiring layer comprises a first pattern of electrical contacts and redistribution wiring that provides electrical connections between the first pattern of electrical contacts and the conductive vias; bonding a glass handler substrate to the wiring layer on the first surface of the silicon substrate; recessing the second surface of the silicon substrate to expose bottom portions of the blind conductive vias and reduce the thickness t 1 of the silicon substrate to a thickness t 1 ′, where t 1 ′ is less than about 150 microns to about 1-10 um; forming an insulating layer on the recessed second surface of the silicon substrate with the bottom portions of the conductive vias exposed; forming electrical contacts on the exposed bottom portions of the conductive vias to provide a second pattern of electrical contacts; bonding the second pattern of electrical contacts to a third pattern of electrical contacts on a second package substrate layer; and removing the mechanical glass handler substrate, wherein forming a pattern of conductive vias in the first surface of the first silicon substrate comprises: etching a pattern of annular trenches in the first surface of the first silicon substrate to the depth dl below the first surface of the substrate, each annular trench surrounding an inner core of silicon substrate material; forming a liner layer on the exposed sidewall surfaces of the annular trenches; and filling the annular trenches with a metallic material.