Patent ID: 8145958

Claim:
An integrated circuit, comprising: processing logic configured to perform data processing operations on data; a plurality of memory units configured to store data for access by the processing logic; and memory test logic configured to perform a sequence of tests in order to seek to detect memory defects in the plurality of memory units, the memory test logic comprising: a plurality of test wrapper units, each test wrapper unit associated with one of said memory units, and configured to perform tests on its associated memory unit; a test controller configured to control performance of the sequence of tests by communicating with each of the test wrapper units to provide test data defining each test to be executed by that test wrapper unit and to provide control signals to control execution of each test by that test wrapper unit; a first communication link configured to provide said test data to each of the test wrapper units directly from the test controller; and a second communication link configured to provide said test data to each test wrapper unit in an ordered sequence from the test controller, when controlling performance of the sequence of tests in a first mode of operation, the test controller providing said test data as first test data via the first communication link and in a second mode of operation the test controller providing said test data as second test data via the second communication link, and said test controller providing said control signals via the first communications link.