Patent ID: 7139898

Claim:
A pipelined multistreaming processor, comprising: an instruction cache for concurrently providing a plurality of instructions for a plurality of instruction streams; fetch logic coupled to said instruction cache enabled to concurrently fetch said plurality of instructions for said plurality of instruction streams from said instruction cache; a plurality of instruction queues coupled to said fetch logic where each one of said plurality of instruction queues is associated with at least one of said plurality of instruction streams, wherein the number of said plurality of instruction queues is greater than said plurality of instruction streams that are provided by said instruction cache; a dispatch stage coupled to said plurality of instruction queues for selecting and dispatching instructions for said plurality of instruction streams to a set of execution units; and select logic coupled to said instruction cache, and to said plurality of instruction queues, said select logic monitoring each of the plurality of instruction queues, said select logic selecting ones of said plurality of instruction streams to fetch instructions from said instruction cache, the selecting based on the monitoring.