Patent ID: 7535753

Claim:
A semiconductor memory device comprising: a first inverter circuit and a second inverter circuit formed by transistors; a first storage node connected to an output terminal of the first inverter circuit and an input terminal of the second inverter circuit; a second storage node connected to an input terminal of the first inverter circuit and an output terminal of the second inverter circuit; a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, and formed by a P-type transistor; a second transfer gate which is connected between a second power node of the second inverter circuit and a second bit line, and formed by a P-type transistor; a first word line connected to gate terminals of the first transfer gate and the second transfer gate; a first read transistor which is connected between the first power node and a second word line, and formed by an N-type transistor having a gate terminal connected to the second storage node; a second read transistor which is connected between the second power node and the second word line, and formed by an N-type transistor having a gate terminal connected to the first storage node; and an application circuit which is connected to the second word line, and applies a read voltage within a range of a ground voltage (inclusive) to a power supply voltage (exclusive) to the second word line in reading data.