Patent ID: 7330991

Claim:
An apparatus comprising: a processor (i) configured to operate at a first data rate in response to a first clock signal and (ii) having a first bus interface unit to communicate on a system bus; an interface circuit having (A) a state machine, (B) a second bus interface unit to communicate on said system bus and (C) a control status register having a completion bit that indicates in alternate states that (a) said processor is finished with a current transfer to said interface circuit and (b) said interface circuit is ready to begin a new read/write operation, said interface circuit being configured to (i) operate at a second data rate in response to a second clock signal and (ii) convert data received from said processor over said system bus from said first data rate to said second data rate; and a first memory (i) having a plurality of banks, (ii) coupled to said interface circuit and (iii) configured to present/receive said data to/from said interface circuit at said second data rate, wherein said state machine is configured to precharge and close all of said banks prior to a refresh cycle being performed.