Patent ID: 8836680

Claim:
A pixel circuit having a video mode, a memory mode and an inversion mode of operation, comprising: a pixel storage node for storing data to be output by a display element; a pixel write circuit configured to receive display data and provide the display data to the pixel storage node for storage thereon; a hold circuit operatively coupled to the pixel write circuit and configured to minimize leakage of charge from the pixel storage node through the pixel write circuit; and an internal inversion circuit operatively coupled to the hold circuit and the pixel storage node and configured to invert a voltage of the data stored on the pixel storage node and a voltage applied to a display element that receives data stored on the pixel storage node, wherein the pixel write circuit comprises an input node, an output node, and an intermediate node electrically connected between the input node and the output node, wherein the output node is electrically connected to the pixel storage node, and the hold circuit comprises a switching device configured to selectively couple the intermediate node to a second power source terminal, wherein when the pixel circuit is operating in memory mode, the switching device is configured to maintain a voltage on the intermediate node at the same level as a voltage on the pixel storage node, wherein the switching device comprises a supply transistor having a source and drain, the drain of the supply transistor electrically connected to the second power source terminal, and the source of the supply transistor electrically connected to the intermediate node, and wherein the supply transistor comprises a first supply transistor and a second supply transistor, the first supply transistor comprising an n-channel transistor and the second supply transistor comprising a p-channel transistor, and wherein a drain of the first supply transistor is electrically connected to the second power source terminal, a source of the first supply transistor is electrically connected to a source of the second supply transistor, and a drain of the second supply transistor is electrically connected to a fifth power source terminal.