Patent ID: 7719315

Claim:
A programmable clock generator comprising: an input logic circuit receiving a global clock signal and generating a local clock signal in response to a feedback clock signal from a feedback path and a feedback gate signal, wherein the input logic circuit forms a first part of the feedback path and a pulse width of the local clock signal is determined by a first delay of a feed-forward path and a second delay of the feedback path; a feed-forward circuit receiving the local clock signal and generating a data clock in response to a clock delay signal, wherein the feed-forward circuit forms the feed-forward path and delays transitions of the local clock signal the first delay time when the clock delay signal is a first logic state and delays a positive transition of the local clock signal an additional third delay time when the clock delay signal is a second logic state; and a feedback circuit forming a second part of the feedback path and receiving the data clock signal and the local clock signal and generating the feedback clock signal in response to a feedback delay control signal, wherein the data clock signal is a pulse signal with a pulse width equal to the first delay plus the second delay, independent of the clock delay signal, and delayed the first delay time relative to the local clock signal when the clock delay signal has the first logic state and further, the data clock signal is delayed relative to the local clock signal the sum of the first and third delay times when the clock delay signal has the second logic state.