Patent ID: 7071770

Claim:
A bias generator, comprising: a reference transistor connected in a diode configuration; a current sink transistor in a path of the reference transistor configured to generate a reference current; a first current mirror configured to generate a mirrored current as a function of the reference current; an impedance element in a path of the first current mirror configured to generate a first voltage in proportion to the mirrored current; a cascade feedback buffer with an input operably coupled to the first voltage and an output operably coupled to a gate of the current sink transistor, the cascade feedback buffer comprising: a buffer current source comprising a p-channel transistor having a source coupled to a supply voltage, a gate coupled to a gate of the reference transistor, and a drain coupled to the output of the cascade feedback buffer; and a buffer current sink comprising an n-channel transistor having a source coupled to a ground voltage, a gate coupled to the input of the cascade feedback buffer, and a drain coupled to the output of the cascade feedback buffer; and a second current mirror configured to generate an output current as a function of the reference current.