Patent ID: 7495484

Claim:
A programmable frequency multiplier device, comprising: a frequency doubler section configured to receive an input signal having a frequency f, and to output a plurality of doubled signals, each of the plurality of doubled signals having a frequency 2 n ×f (n=0, 1, 2, . . . ); a selector section configured to select a plurality of the doubled signals output from the frequency doubler section, and to output the plurality of the selected doubled signals as selected signals; and a frequency summation section configured to multiply the selected signals, and to output a multiplied signal having a frequency f out =f×(m 0 2 0 +m 1 2 1 + . . . +m k 2 k + . . . +m n 2 n ), wherein m k =0 or 1, and k=0, 1, . . . , n.