Patent ID: 8572524

Claim:
A method for forming an IC comprising: providing a substrate with a photoresist layer; providing a mask with a mask pattern, wherein providing the mask comprises deriving the mask pattern from an input mask design layout which is provided prior to forming a physical mask, obtaining a mask bias from an optical proximity correction (OPC) model of an OPC system with an OPC simulator, wherein the OPC system estimates critical dimension (CD) variation of one or more feature types on the input mask from measured inline process variation data of an actual wafer process line to obtain the mask bias, wherein inline process variation data includes variations in develop inspection CD and resist sidewall angle measurements profile, and adjusting the input mask with the mask bias to produce an adjusted input mask, and forming the physical mask having a physical mask pattern using the adjusted input mask; exposing the photoresist layer by passing radiation from an exposure source through the physical mask formed using the adjusted input mask; and developing the photoresist to transfer the physical mask pattern of the physical mask to the photoresist layer.