Patent ID: 7713807

Claim:
A method of forming CMOS devices on a hybrid crystal oriented substrate comprising: providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second crystallographic orientation separated by an insulating layer, said first crystallographic orientation is different from said second crystallographic orientation and said first semiconductor layer lies above said second semiconductor layer; protecting a portion of the bonded substrate to define a first device area, while leaving another portion of the bonded substrate unprotected, said unprotected portion of the bonded substrate defining a second device area; etching said unprotected portion of the bonded substrate to expose a surface of the second semiconductor layer; forming a spacer on exposed sidewalls of the first semiconductor layer after said etching; regrowing a semiconductor material on said exposed surface of the second semiconductor layer, said semiconductor material having a crystallographic orientation that is the same as the second crystallographic orientation; planarizing the bonded substrate containing the semiconductor material so that an upper surface of the first semiconductor layer is substantially planar with an upper surface of the semiconductor material; forming a material stack over planarized bonded substrate and forming trench openings in the material stack in the first semiconductor layer, wherein an upper portion of the spacer is removed, and the trench openings extend to a top surface of said insulating layer; forming at least one trench dielectric portion by filling the trench openings with a dielectric material, wherein the at least one trench dielectric portion vertically contacts a top surface of a lower portion of the spacer, whereby at least one trench dielectric portion laterally separates the first device region from the second device region; and forming at least one first semiconductor device in said first device region, while forming at least one second semiconductor device on said semiconductor material in said second device area.