Patent ID: 8296551

Claim:
In a system in which a hardware target computer system, which has a target instruction set architecture (ISA), executes target instruction sequences corresponding to source instruction sequences of a source system, which has a source ISA and is running on the target computer system, each target instruction sequence of one or more target instructions corresponding to a source instruction sequence of one or more source instructions, a method for handling exceptions comprising the following steps: converting source instruction sequences into target instruction sequences by binary translation; executing the translated target instructions; sensing the presence of an exception and determining whether the sensed exception is synchronous or asynchronous, a synchronous exception being defined as an exception resulting from attempted execution of a target instruction, where synchronous exceptions are of either of two types, namely, transparent and non-transparent, a transparent exception being defined as an exception requiring processing action wholly within the target computer system, and a non-transparent exception being defined as an exception requiring processing that alters a visible state of the source system, an asynchronous exception being defined as an exception resulting from an event unrelated to the execution of a target instruction; if the sensed exception is asynchronous, delaying application of the sensed exception until after the completion of the target instruction sequence corresponding to the current source instruction when the asynchronous exception is sensed; and if the sensed exception is synchronous, determining whether the sensed synchronous exception is transparent or non-transparent, and: if the sensed synchronous exception is transparent, handling the exception externally from the source system, the visible state of the source system thereby being unaffected by the handling of the exception; or if the sensed synchronous exception is non-transparent, forwarding the exception to the source system for processing.