Patent ID: 8306047

Claim:
A packet switch for switching packets comprising: a plurality of input ports, each configured to receive one or more of the packets; a plurality of output ports, each configured to deliver one or more of the packets; for each input port, a demultiplexer having an output corresponding to each output port and being configured to receive each packet from the input port and to direct it to one of the outputs based at least in part on information in a header for the packet; for each output of each demultiplexer, a programmable delay line configured to receive each packet from the output of the demultiplexer and to delay the output of each packet from the programmable delay line for a programmable amount of time which may be re-programmed while the packet is being delayed by the programmable delay line; for each set of programmable delay lines that are configured to receive packets from the outputs of the demultiplexers that correspond to the same output port: a programmable delay line controller configured to repeatedly: program the set of programmable delay lines to delay packets received during a look-ahead period; at the end of the look-ahead period, determine for the packets which have been received by the set of programmable delay lines during the look-ahead period: an output sequence for the packets; and for each of the packets, the amount of remaining delay needed within its programmable delay line to cause the packet to arrive at the output of its programmable delay line in conformance with the determined output sequence; and after the determining, re-program each of the set of programmable delay lines, as needed, to provide the determined remaining delay for that programmable delay line; and a multiplexer configured to receive the packets from the outputs of the set of programmable delay lines and to multiplex them together onto the output port that corresponds to the set of programmable delay lines.