Patent ID: 7474552

Claim:
An integrated circuit comprising a memory device, the memory device comprising: a programmable storage unit for storing a storage state; and a receiver circuit comprising a first terminal for applying a power supply voltage, a second terminal for applying a reference voltage, a third terminal, a first current path, a second current path and a controllable resistor, wherein: the first current path of the receiver circuit includes a first transistor having a control terminal and the second current path of the receiver circuit includes a second transistor having a control terminal and the first and second current paths are connected in parallel between the first terminal and the third terminal of the receiver circuit; the controllable resistor of the receiver circuit is connected between the third terminal and the second terminal of the receiver circuit; a resistance value of the controllable resistor of the receiver circuit is dependent on the storage state, wherein the storage state indicates one of a high power dissipation or a low power dissipation and the resistance value of the controllable resistor is selected to have a first resistance value or a second resistance value that is lower than the first resistance value in response to the storage state; and the first and second transistors respectively are connected to the second terminal for applying the reference voltage via the controllable resistor, wherein the control terminal of the first transistor is actuated by a first signal, the control terminal of the second transistor is actuated by a second signal that is different from the first signal, and the control terminal of the first transistor and the control terminal of the second transistor are separated from each other.