Patent ID: 7913221

Claim:
A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device, the method comprising steps of: (a) inputting, from a storage device, layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based on interconnects in the layout data; and (c) outputting, to a storage device, layout data including the air gap exclusion area determined in the step (b), wherein: the step (b) comprises steps of: (b1) performing timing calculation for the layout data; (b2) specifying a timing error position in the layout data based on results obtained in the step (b1); (b3) specifying an amount and a position of an air gap exclusion area to be inserted for the timing error position; and (b4) forming or deleting an air gap exclusion area for the timing error position, and the steps (a) through (c) are performed by a device for designing an interconnect structure.