Patent ID: 7725641

Claim:
A single-instruction multiple-data processor comprising: a plurality of operation units configured to execute parallel operations with input data; a memory configured to rearrange and store data enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel; and a data interconnection unit configured to shift the plurality of data output from the memory in a data access operation, and correspondingly provide the shifted data to the plurality of operation units as the input data, wherein the memory is configured with M internal address numbers and each of the internal address numbers corresponds to M bank numbers, where M is an integer greater than 0, a start bank number of a data stream stored in each of the internal address numbers is shifted by N bank numbers if the corresponding internal address number increases by one, where N is an integer greater than 0, and a number of bits the plurality of data is shifted is determined based on the start bank number of the corresponding internal address number of the memory; and wherein a first internal address y of the memory is (x %16)×16 if first data of a data stream is x, and a start bank number corresponding to the first internal address y is y/4+4(y %4).