Patent ID: 8368573

Claim:
An analog-to-digital converter comprising: a ΣΔ modulator; an adjusting circuit, coupled to the ΣΔ modulator, and configured to output dummy data and adjust a total of an amount of change of ΣΔ modulated data output from the ΣΔ modulator and an amount of change of the dummy data to be constant; and a level converting part, coupled to the ΣΔ modulator, and configured to receive the ΣΔ modulated data, wherein the adjusting circuit outputs an inverted value of the dummy data of one clock before as present output data when the ΣΔ modulated data does not change, and outputs the dummy data of one clock before as the present output data when the ΣΔ modulated data changes, wherein the level converting part includes a first level converter configured to output the ΣΔ modulated data by converting a level of the ΣΔ modulated data, and a second level converter configured to receive the dummy data from the adjusting circuit, and wherein the second level converter is configured to cancel a frequency dependence of noise with respect to the ΣΔ modulated data.