Patent ID: 8921947

Claim:
A semiconductor device, comprising: a substrate with a gate layer formed thereon and silicides formed therein, and the gate layer comprising plural metal gates separated by an insulation, said silicides positioned between the metal gates; at least a conductive contact formed in the insulation between adjacent metal gates for electrically connecting the silicide; and a patterned dielectric layer formed on the metal gates, the insulation and the conductive contact, and the patterned dielectric layer at least having a first metal-0 (M0) opening exposing the conductive contact; wherein the conductive contact has a bottom area with a first diameter (CD1) for electrically connecting the silicide, and has a top area with a second diameter (CD2) for opening the insulation, wherein the first M0 opening has a bottom area with a third diameter (CD3) for exposing the conductive contact, and the third diameter (CD3) is smaller than the second diameter (CD2).