Patent ID: 8492808

Claim:
A semiconductor device comprising: (a) a semiconductor substrate having a first main surface and a second main surface; (b) an MISFET provided over the first main surface of the semiconductor substrate; (c) a first interlayer insulating film covering therewith the first main surface of the semiconductor substrate and the MISFET; (d) a first wiring layer provided over the first interlayer insulating film; (e) a second wiring layer provided over the first wiring layer; and (f) a third wiring layer provided over the second wiring layer, wherein the first wiring layer comprises: (d1) a second interlayer insulating film; (d2) a first wiring trench formed in the second interlayer insulating film; (d3) a first barrier metal film formed over the side surface and the bottom surface of the first wiring trench and containing at least one of tantalum, titanium, ruthenium, manganese, and tungsten as one of the main metal components of the first barrier metal film; and (d4) a first copper wiring film formed over the first barrier metal film to embed the first wiring trench, configuring a first wiring together with the first barrier metal film, and containing an additive element, wherein the second wiring layer comprises: (e1) a third interlayer insulating film; (e2) a second wiring trench formed in the third interlayer insulating film; (e3) a second barrier metal film formed over the side surface and the bottom surface of the second wiring trench and containing at least one of tantalum, titanium, ruthenium, manganese, and tungsten as one of the main metal components of the second barrier metal film; (e4) a third barrier metal film formed over the second barrier metal film and containing at least one of cobalt, nickel, and iron as one of the main components of the third barrier metal film; and (e5) a second copper wiring film formed over the third barrier metal film to embed the second wiring trench, configuring a second wiring together with the second and third barrier metal films, and comprised of pure copper, and wherein the third wiring layer comprises: (f1) a magnetic memory element.