Patent ID: 6958919

Claim:
A zero voltage switching power conversion circuit comprising: a zero voltage switching (ZVS) circuit ( 10 ) coupled to a full bridge ( 20 ) composing of a first pair of transistors (Tr 1 ,Tr 2 ) and a second pair of transistors (Tr 3 , Tr 4 ), each pair of transistors including a PMOS transistor (Tr 1 , Tr 4 ) connected to an NMOS transistor (Tr 2 , Tr 3 ); and a transformer ( 30 ) having a primary side coupled to the full bridge ( 20 ) and a secondary side coupled to a load through an output capacitor (C 2 ); wherein the ZVS switching circuit ( 10 ) further comprises: a high frequency oscillation circuit ( 11 ), which generates a high frequency signal T 1 ; a first divider ( 12 ) with an input terminal connected to the high frequency oscillation circuit ( 11 ) to receive the high frequency signal T 1 , wherein the frequency of the high frequency signal T 1 is divided by the first divider ( 12 ) to obtain a first driving signal P 1 ; a first controllable non-overlap circuit ( 13 ), which receives the first driving signal P 1 from the first divider ( 12 ) and generates two non-overlapped signals based on the first driving signal P 1 ; a first voltage level booting circuit ( 14 ), which boots voltage levels of the two non-overlapped signals output from the first controllable non-overlap circuit ( 13 ) so as to derive a first driving signal (Q 1 ) and a second driving signal (Q 2 ) respectively applied to a corresponding one of the first pair of transistors (Tr 1 , Tr 2 ); a voltage-controlled PWM circuit ( 15 ) to receive the high frequency signal T 1 from the high frequency oscillation circuit ( 11 ) and then shifts its phase thus obtaining a phase-shifted high frequency signal T 2 ; a second divider ( 16 ), which receives the phase-shifted high frequency signal T 2 , divides the frequency of the phase-shifted high frequency signal T 2 to derive a second driving signal P 2 ; a second controllable non-overlap circuit ( 17 ), which receives the second driving signal P 2 from the second divider ( 16 ) and generates two non-overlapped signals based on the second driving signal P 2 ; and a second voltage level booting circuit ( 18 ), which boots voltage levels of the two non-overlapped signals output from the second controllable non-overlap circuit ( 17 ) to derive a third driving signal (Q 3 ) and a fourth driving signal (Q 4 ) that are respectively applied to a corresponding one of the second pair of transistors (Tr 3 Tr 4 ); said four driving signals (Q 1 –Q 4 ) respectively applied to control the four transistors to determine conducting and non-conducting periods of each transistor.