Patent ID: 7569468

Claim:
A method of forming a floating gate memory, comprising: forming a plurality of floating gate memory cell gate stacks; forming a spacer dielectric layer overlying the plurality of floating gate memory cell gate stacks having at least one trench that exposes a source region of at least one of the floating gate memory cell gate stacks; depositing a layer of polysilicon overlying the spacer dielectric layer such that a portion of the layer of polysilicon substantially fills the at least one trench and contacts the source region; selectively implanting ions in the portion of the layer of polysilicon that substantially fills the at least one trench; and wet etching the layer of polysilicon to remove non-implanted regions of the layer of polysilicon to form a polysilicon local interconnect line in the at least one trench; wherein forming a spacer dielectric layer comprises patterning a first mask layer to expose at least one portion of the spacer dielectric layer corresponding to the at least one trench and removing the at least one portion of the spacer dielectric layer corresponding to the at least one trench using the first mask layer as a mask to expose the source region; wherein selectively implanting the ions in the portion of the layer of polysilicon that substantially fills the at least one trench comprises patterning a second mask layer to expose the portion of the layer of polysilicon that substantially fills the at least one trench; and wherein patterning the first and second mask layers comprises patterning the first and second mask layers with the same pattern.