Patent ID: 7705394

Claim:
A nonvolatile semiconductor memory comprising: a cell array region including a memory cell transistor, which comprises; first source and drain regions, a first tunneling insulating film formed on a semiconductor region between the first source and drain regions, a first floating gate electrode layer formed on the first tunneling insulating film, a first inter-gate insulating film formed on the first floating gate electrode layer, a first control gate electrode layer formed on the first inter-gate insulating film, a second control gate electrode layer formed on the first control gate electrode layer, and a first metallic silicide film electrically connected to the second control gate electrode layer; a high voltage circuit region that is disposed around the cell array region and comprises; a high voltage transistor, which comprises second source and drain regions, a high voltage gate insulating film formed on a semiconductor region between the second source and drain regions, a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture formed on the high voltage gate electrode layer, a third control gate electrode layer formed on the second inter-gate insulating film, a fourth control gate electrode layer formed on the third control gate electrode layer, and a second metallic silicide film electrically connected to the fourth control gate electrode layer; a low voltage circuit region that is disposed in a different area from the high voltage circuit region, which is around the cell array region, and comprises; a low voltage transistor that comprises third source and drain regions, a second tunneling insulating film formed on a semiconductor region between the third source and drain regions, a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture formed on the second floating gate electrode layer, a fifth control gate electrode layer formed on the third inter-gate insulating film, a sixth control gate electrode layer formed on the fifth control gate electrode layer, and a third metallic silicide film electrically connected to the sixth control gate electrode layer; and a liner insulating film directly disposed on the first source and drain regions, the second source and drain regions, and the third source and drain regions.