Patent ID: 7247571

Claim:
A method for planarizing a semiconductor structure, comprising: providing a semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density; forming a first dielectric layer and a second dielectric layer, the second dielectric layer covering the trenches in the first and second areas and the first dielectric layer; performing a first chemical mechanical polishing on the second dielectric layer using a predetermined type of slurry for reducing a thickness thereof; rinsing the polished second dielectric layer by using deionized water; and performing a second chemical mechanical polishing on the second dielectric layer using the predetermined type of slurry for removing the second dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas, and wherein the predetermined type of slurry provides a higher polish rate for the second dielectric layer than the first dielectric layer.