Patent ID: 7358790

Claim:
A level shift circuit, comprising: a first power supply terminal to which a first potential is supplied; a second power supply terminal to which a second potential is supplied, wherein the second potential is lower than the first potential; a first PMOS transistor having a source connected to the first power supply terminal, a gate connected to a first input terminal, and a drain connected to a first output terminal; a second PMOS transistor having a source connected to the first power supply terminal, a gate connected to a second input terminal, and a drain connected to a second output terminal; a third PMOS transistor having a source connected to the first power supply terminal, a gate connected to the second output terminal, and a drain connected to a third output terminal; a first NMOS transistor having a drain and a gate connected to the first output terminal; a second NMOS transistor having a drain and a gate connected to the second output terminal; a third NMOS transistor having a drain connected to a source of the first NMOS transistor, a gate connected to the second output terminal, and a source connected to the second power supply terminal; a fourth NMOS transistor having a drain connected to a source of the second NMOS transistor, a gate connected to the first output terminal, and a source connected to the second power supply terminal; and a fifth NMOS transistor having a source connected to the second power supply terminal, a gate connected to the second output terminal, and a drain connected to the third output terminal, wherein a threshold voltage of the fifth NMOS transistor is less than a threshold voltage of the second NMOS transistor in an enhancement mode.