Patent ID: 7875540

Claim:
A method for manufacturing a recess gate in a semiconductor device, the method comprising: forming a field oxide layer on a substrate to define a plurality of active regions; forming a hard mask pattern over the substrate to selectively expose at least a portion of at least one of the active regions; forming a neck pattern in the at least one active region through an etching process using the hard mask pattern as an etch barrier; forming a sacrificial sidewall on sidewalls of the neck pattern and the hard mask pattern; forming a bulb pattern under the neck pattern through an etching process using the hard mask pattern; removing the sacrificial sidewall and the hard mask pattern; forming a gate insulating layer over the substrate; and forming a gate electrode over the gate insulating layer to fill at least the neck pattern and the bulb pattern, wherein forming the hard mask pattern includes forming the hard mask pattern to cover facing ends of neighboring active regions adjacent to the gate electrode and the field oxide layer between the neighboring active regions.