Patent ID: 8053307

Claim:
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a cell active region and a peripheral active region; forming a cell gate electrode in the cell active region; forming a cell gate capping layer on the cell gate electrode; forming impurity regions in the cell active region at opposite sides of the cell gate electrode; forming at least two cell epitaxial layers on the cell active region, forming a peripheral gate pattern on the peripheral active region; forming gate spacers on sidewalls of the peripheral gate pattern; forming impurity regions in the peripheral active region; and forming at least two peripheral epitaxial layers on the peripheral active regions, wherein forming of the cell gate electrode and the peripheral gate pattern includes: forming conductive mask patterns covering the cell active region and the peripheral active region, the conductive mask pattern covering the cell active region having an opening exposing a portion of the cell active region; etching the cell active region using the conductive mask patterns as a mask to form a recess; forming a first conductive layer on the conductive mask patterns and in the recess; forming a second conductive layer and a capping insulating layer on the first conductive layer; and patterning the capping insulating layer, the second conductive layer, the first conductive layer and a gate insulating layer so that the first conductive layer remains in the recess and the peripheral gate pattern is formed on a portion of the peripheral active region.