Patent ID: 8653577

Claim:
A nonvolatile semiconductor memory device comprising: a stacked body in which a plurality of insulating films and a plurality of electrode films are alternately stacked; a plurality of selection gate electrodes provided on the stacked body; a plurality of bit lines provided on the selection gate electrodes; a plurality of semiconductor pillars passing through the stacked body and the selection gate electrodes, whose upper ends are connected to the bit lines; a plurality of connective members separated from one another, one of the connective members connected between a lower part of a first of the semiconductor pillars and a lower part of a second of the semiconductor pillars; and a charge storage layer provided between each of the electrode films and each of the semiconductor pillars, each of the electrode films being divided for each of the selection gate electrodes, the first of the semiconductor pillars passing through a first of the selection gate electrodes and connected to a first of the bit lines, and the second of the semiconductor pillars passing through a second of the selection gate electrodes and connected to a second of the bit lines, wherein the selection gate electrode extends in a first direction orthogonal to a stacking direction of the insulating films and the electrode films, the bit line extends in a second direction orthogonal to the stacking direction and intersecting the first direction, and the one of the connective members extends in a direction orthogonal to the stacking direction and inclined to both the first direction and the second direction, and the first of the bit lines and the second of the bit lines are adjacent.