Patent ID: 7050282

Claim:
A power supply clamp circuit for preventing damage to integrated circuits when electrostatic discharge occurs at a first voltage source of the integrated circuits, the integrated circuits further comprising a second voltage source that is independent from the first voltage source and having the same voltage as the first voltage source, the power supply clamp circuit comprising: a first voltage generator electrically connected to a first node for generating a voltage; a first PMOS transistor having a source electrically connected to the first voltage source, a gate electrically connected to the first node, and a drain electrically connected to a second node; a first NMOS transistor having a drain electrically connected to the second node, a gate electrically connected to the first node, and a source connected to ground; a second NMOS transistor having a drain electrically connected to the first voltage source, a gate electrically connected to the second node, and a source connected to ground; and a second PMOS transistor having a source electrically connected to the second node, a gate and a drain both electrically connected to the first node.