Patent ID: 7596650

Claim:
An apparatus comprising: a passive interposer including at least a first direct passive interconnect and a second direct passive interconnect, wherein the passive interposer is to be coupled to an unpopulated socket of a system, wherein the passive interposer is to route signals from a first processor of the system through the first direct passive interconnect to a device coupled to the unpopulated socket via a first interconnect separate from the first direct passive interconnect and from the first processor through the second direct passive interconnect to a main memory locally coupled to the unpopulated socket via a second interconnect separate from the second direct passive interconnect, wherein the first processor is to determine a change in configuration of the system, and responsive to the determination to reconfigure a first interface therein from a first protocol to enable communication of the signals to the device to a second protocol to enable communication of second signals to a second processor when the system is reconfigured to include the second processor in place of the passive interposer, the first interface including a first protocol engine to communicate according to the first protocol and a second protocol engine to communicate according to the second protocol.