Patent ID: 7345345

Claim:
A CMOS semiconductor device comprising: a semiconductor substrate of a first conductivity type; a first well of a second conductivity type formed in a surface portion of the semiconductor substrate; a second well of the second conductivity type formed in the surface portion of the semiconductor substrate, the second well being separated from the first well; a third well of the first conductivity type formed in a surface portion of the first well; a fourth well of the second conductivity type formed in a surface portion of the second well; a MOS transistor comprising a channel of the second conductivity type formed in a surface portion of the third well; and a MOS transistor comprising a channel of the first conductivity type formed in a surface portion of the fourth well, wherein the first well and the second well are biased at the same electric potential, and a source of the MOS transistor in the third well and a source of the MOS transistor in the fourth well are biased at different electric potentials.