Patent ID: 8509006

Claim:
A semiconductor device comprising: a plurality of word lines configured to be connected to gates of a plurality of memory cell transistors, respectively; a word line driver configured to supply one of a selection voltage and a non-selection voltage to each of said plurality of word lines; a first detection circuit configured to detect a first current flowing into said word line driver through a wiring supplying said selection voltage when said selection voltage is supplied to one of said plurality of word lines through said word line driver; a control circuit configured to detect abnormality of said plurality of word lines and said word line driver based on said first current; and a second detection circuit configured to detect a second voltage of said plurality of word lines when said word line driver supplies said non-selection voltage to said plurality of word lines, wherein said control circuit detects abnormality of said plurality of word lines and said word line driver based on the first current and said second voltage.