Patent ID: 7015742

Claim:
A switched capacitor circuit capable of eliminating clock feedthrough for use in an oscillator having an output frequency, the switched capacitor circuit comprising: a control signal generator for generating a first control signal and a second control signal, wherein the second control signal is complementary to the first control signal; a positive side primary switch element selectively connecting a positive side first node to a positive side second node depending upon the first control signal, wherein the positive side first node is connected to a positive side capacitance; and a positive side additional switch element selectively connecting the positive side first node to a positive side third node depending upon the second control signal; wherein during a time that the positive side primary switch element is connecting the positive side first node to the positive side second node such that the switched capacitor circuit is connected to a resonator of the oscillator, the output frequency of the oscillator is a first frequency value, and during a time that the positive side primary switch element is not connecting the positive side first node to the positive side second node such that the switched capacitor circuit is not connected to the resonator of the oscillator, the output frequency of the oscillator is a second frequency value being different than the first frequency value.