Patent ID: 7906381

Claim:
A method for fabricating transistors of first and second types in a single substrate, the method comprising: delimiting at least one first active zone and at least one second active zone of the substrate by lateral isolation trench regions; removing an upper portion of the second active zone so that an upper surface of the second active zone is below an upper surface of the first active zone; after removing the upper portion of the second active zone, forming first and second layers of semiconductor material on the second active zone, so that an upper surface of the second layer is substantially in the same plane as the upper surface of the first active zone, the first layer being constituted by a first material that is selectively removable with respect to a second material constituting the second active zone and with respect to a third material constituting the second layer; producing a first insulated gate on the first active zone and a second insulated gate on the second layer; selectively removing at least one of the isolation trench regions so as to allow access to the first layer; selectively removing the first layer so as to form a tunnel under the second layer; and filling the tunnel with a dielectric material so as to insulate the second layer from the second active zone of the substrate.