Patent ID: 7053444

Claim:
A semiconductor device, comprising: a semiconductor wafer substrate assembly comprising at least a region of a semiconductor wafer; at least first and second transistor columns overlying the semiconductor wafer region within a single sector of the semiconductor device, wherein the first transistor column comprises at least a first transistor and the second transistor column comprises at least a second transistor and each of the at least first and second transistors comprises: a transistor control gate; a dielectric capping layer having a horizontally oriented upper surface; first and second vertically oriented sidewalls at least partially formed by a portion of the dielectric capping layer and the transistor control gate; and a spacer formed along and contacting the first vertically oriented sidewall and a spacer formed along and contacting the second vertically oriented sidewall; an etch stop layer overlying the horizontally oriented upper surface of the dielectric capping layer of each of the first and second transistors and which contacts the spacer formed along the first vertically oriented sidewall; a planarized dielectric layer having a first vertically oriented sidewall which overlies the first transistor and a second vertically oriented sidewall which overlies the second transistor; a spacer formed along and contacting the first vertically oriented sidewall of the dielectric layer and a spacer formed along and contacting the second vertically oriented sidewall of the dielectric layer; and a source local interconnect interposed between the first and second transistors which contacts each spacer formed along the second vertically oriented sidewall of each of the first and second transistors and the spacers formed along the first and second vertically oriented sidewalls of the dielectric layer.