Patent ID: 7865692

Claim:
A translation memory (TM) system comprising: a byte addressable X-TM portion; a byte addressable Y-TM portion; an X-TM K-by-K byte-wide switch, wherein the X-TM K-by-K byte wide switch selects an X entry that is overlapped within K bytes of an accessed X-TM entry; a Y-TM K-by-K byte-wide switch, wherein the Y-TM K-by-K byte wide switch selects a Y entry that is overlapped within K bytes of an accessed Y-TM entry; an X-TM switch output latch holding the X entry as a latched X entry; and a Y-TM switch output latch holding the Y entry as a latched Y entry, wherein overlapping X entries are stored in the X-TM to minimize the X-TM size, overlapping Y entries are stored in the Y-TM to minimize the Y-TM size, and the latched X entry and the latched Y entry are combined to create an instruction in a form suitable for execution on a core processor.