Patent ID: 8892816

Claim:
A system comprising: a selection module configured to select a plurality of memory blocks of a first memory, wherein the plurality of memory blocks are partially written with first data, wherein the plurality of memory blocks are selected in response to receiving a write command to write second data to the plurality of memory blocks, and wherein prewritten locations of the first memory cannot be overwritten without first erasing the prewritten locations; a control module configured to write the first data in a portion of a second memory instead of writing the first data in the first memory and to write the first data in the portion of the second memory prior to erasing the first data from the plurality of memory blocks, wherein prewritten locations of the second memory can be overwritten without first erasing the prewritten locations of the second memory; and a location description module configured to generate a description table indicating whether data in memory locations in the portion of the second memory are valid or invalid, wherein data initially written to a first memory location corresponding to a logical address are indicated as valid, and in response to new data being written to a second memory location corresponding to the logical address, the data in the first memory location are indicated as invalid, and wherein in response to the control module writing additional data to the portion of the second memory, a rate of adding data to the portion becomes equal to a rate at which data in memory locations in the portion becomes invalid so that the first data is written in the portion without first merging the first data.