Patent ID: 7610534

Claim:
A processor-implemented method for determining a total length of one or more instruction registers of one or more unidentified devices in a scan chain of a plurality of devices having respective instruction registers, the processor-implemented method comprising: determining from a first data shift of the scan chain whether each of the plurality of devices is an identified device that has a respective identification register with a recognized value; determining an overall length of the instruction registers of the plurality of devices in the scan chain from a first instruction shift of the scan chain; for each pair of sub-sequences of unidentified ones of the plurality of devices in the scan chain, wherein a first and second sub-sequence of the pair are separated in the scan chain by a third sub-sequence of at least one identified device, determining an actual position within the overall length for the respective instruction register of an identified device of the third sub-sequence in response to, for each of at least one trial position within the overall length, a second data shift of the scan chain obtaining the recognized value of the respective identification register of the identified device following a second instruction shift of the scan chain that attempts to set the respective instruction register of the identified device at the trial position; and determining the total length of the instruction register of every unidentified device in each of the sub-sequences of the unidentified devices as a function of the overall length of the instruction registers of the plurality of devices, the actual position of the identified device for each pair of the sub-sequences of the unidentified devices, and a length of the respective instruction register of each identified device.