Patent ID: 8304768

Claim:
A thin film transistor array substrate comprising: a plurality of gate lines and a plurality of data lines on a substrate, to define pixel regions crossing each other; thin film transistors, each formed at the intersection of the gate lines and the data lines, and including a gate electrode, a source electrode and a drain electrode; common lines, each including a first pattern formed across the data lines, a second pattern formed adjacent to the data lines on both sides in the pixel region and parallel to the data lines, and a third pattern formed adjacent to the gate lines to connect the second pattern disposed on both the sides in the associated one of the pixel regions, and passing below the drain electrode of the thin film transistors, wherein the first pattern, the second pattern and the third pattern are integrated; and a pixel electrode formed in each pixel region, wherein a contact portion is formed between the drain electrode and the pixel electrodes to connect each other, wherein the third pattern is fully overlapped with the contact portion, and wherein the second pattern formed on the both sides in the pixel region and the third pattern are connected to each other, and have a “U”-shape with respect to an edge of the pixel electrode in each pixel region.