Patent ID: 7074659

Claim:
A method of fabricating a transistor having a source, drain, and a gate on a substrate, the method comprising: implanting, into a surface of the substrate, a first impurity region ( 500 A) with a first volume and a first surface area, the first impurity region being of a first type; forming a gate oxide ( 508 ) between a source region and a drain region of the transistor; covering the gate oxide with a conductive material ( 708 A); implanting, into the source region of the transistor, a second impurity region ( 518 ) with a second volume and a second surface area in the first surface area of the first impurity region, the second impurity region being of an opposite second type relative to the first type, wherein implanting the second impurity region includes, a first implant ( 802 ) to limit a vertical depth of the second impurity region; and a second implant ( 804 ) separate from the first implant to control a lateral channel length of the transistor; implanting, into the source region of the transistor, a third impurity region ( 514 ) with a third volume and a third surface area and a fourth impurity region ( 516 ) with a fourth volume and a fourth surface area, in the second surface area of the second impurity region, the third impurity region being of the first type, the fourth impurity region being of the opposite second type; and implanting, into the drain region of the transistor, a fifth impurity region ( 510 ) with a fifth volume and a fifth surface area, the fifth impurity region being of the first type.