Patent ID: 7962871

Claim:
A method comprising: using a computer to conduct a static timing analysis on an integrated circuit design, wherein conducting the static timing analysis includes: deteimining a first point and a second point of a plurality of points in the integrated circuit design; generating a plurality of signals having different delays, wherein a first signal of the plurality of signals has a first delay, and wherein a second signal of the plurality of signals has a second delay that is different from the first delay; creating a plurality of logical paths between the first point and the second point of the integrated circuit design; associating the first signal with a first logical path of the plurality of logical paths; associating the second signal with a second logical path of the plurality of logical paths; and within a single static timing run, concurrently propagating the first signal that has the first delay from the first point to the second point via the first logical path and the second signal that has the second delay from the first point to the second point via the second logical path.