Patent ID: 7733717

Claim:
A system comprising: a plurality of memory cells organized in a plurality of rows and columns; wherein each column includes an upper set of memory cells connected to a common upper bit line, a lower set of memory cells connected to a common lower bit line, and an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on the upper and lower bit lines and to produce an output signal therefrom; wherein for each column the upper bit line has an upper bit line delay associated therewith, the lower bit line has a lower bit line delay associated therewith, wherein the upper bit line delay is different from the lower bit line delay, and the evaluation circuit has a first input and a second input, wherein the first input has an associated first evaluation delay and the second input has an associated second evaluation delay which is greater than the first evaluation delay; wherein for each column in which the upper bit line delay is greater than the lower bit line delay, the upper bit line is connected to the first input of the evaluation circuit and the lower bit line is connected to the second input of the evaluation circuit; and wherein for each column in which the upper bit line delay is less than the lower bit line delay, the upper bit line is connected to the second input of the evaluation circuit and the lower bit line is connected to the first input of the evaluation circuit.