Patent ID: 8019950

Claim:
A memory controller interface, comprising: a processor block core embedded in a host integrated circuit having programmable resources for communication with a memory controller; the memory controller being instantiated in the programmable resources; the memory controller interface including: an output path including a first processor block interface, an address queue, a write data queue, and a first translation circuit; the first processor block interface coupled to receive address input and data input; the address input being provided from the processor block interface to the address queue; the data input being provided from the processor block interface to the write data queue; the first translation circuit coupled to receive the address input from the address queue and coupled to receive the write data input from the write data queue, wherein the first translation circuit is configured to translate the write data from an internal data width to a width of a write bus coupled thereto; an input path including a second processor block interface, a read data queue and a second translation circuit; the input path coupled to receive read data via the memory controller for the second translation circuit; the second translation circuit coupled to provide the read data to the read data queue, wherein the second translation circuit is configured to translate the read data from an external data width of a read bus to the internal data width; and the read data queue coupled to provide the read data to the second processor block interface for output therefrom.