Patent ID: 7889535

Claim:
A process of testing an integrated circuit, comprising steps: providing a first programmable data storage component in said integrated circuit, said first programmable data storage component including: a first state node; a second state node coupled to said first state node by a state circuit, said second state node being complementary to said first state node; a first data ferroelectric capacitor coupled to said first state node; and a second data ferroelectric capacitor coupled to one of said first state node and said second state node; programming said first programmable data storage component with a first screening data value, such that said first data ferroelectric capacitor and said second data ferroelectric capacitor are polarized so as to provide data retention when power is removed from said first programmable data storage component; powering down said first programmable data storage component, so as to preserve polarizations in said first data ferroelectric capacitor and said second ferroelectric capacitor from said programming step; applying a disturb voltage to at least one of said first state node and said second state node; performing a recall and power up process on said first programmable data storage component; reading a first read data value from said first programmable data storage component; and comparing said first read data value to said first screening data value.