Patent ID: 8555221

Claim:
A computer-implemented method of partitioning a circuit design for hardware-accelerated functional verification, comprising: receiving a description of the circuit design which includes a plurality of nodes interconnected to form a plurality of nets, by executing first program instructions in a computer system; constructing a directed hypergraph with vertices representing the nodes and edges representing the nets, one of the vertices in each edge being a source, by executing second program instructions in the computer system; computing a slack for each edge based on the edge's source, by executing third program instructions in the computer system; assigning each edge a weight which is a function of the edge's slack, by executing fourth program instructions in the computer system; partitioning the hypergraph to create a vertex partitionment which optimizes a total weighted cut of the edges using the edge weights, by executing fifth program instructions in the computer system; and mapping the vertex partitionment to a partitionment of the nodes, by executing sixth program instructions in the computer system.