Patent ID: 7984396

Claim:
A dummy pattern arrangement apparatus comprising: a recognition layer insertion section configured to insert a plurality of recognition layers, each of the plurality of recognition layers covers a specific area on a chip area layout; a dummy pattern arrangement section configured to designate a corner positioned at a same direction on the chip area layout for each of the plurality of recognition layers as a dummy pattern creation starting point, and create a dummy pattern on the specific area from the dummy pattern creation starting point in EB data (Electron Beam Exposure Data), wherein the dummy pattern is determined to satisfy a condition that a positional relation between the dummy pattern and a circuit formed on the chip area layout in each of the plurality of recognition layers is determined to be same, and wherein the dummy pattern consists of a plurality of dummy pattern elements which are periodically arranged in X-direction and Y-direction, the X-direction size and the Y-direction size of each of the plurality of dummy pattern elements are same value represented by DP, the X-direction gap and the Y-direction gap of adjacent elements of the plurality of dummy pattern elements are same value represented by GAP, and X-direction size X R and Y-direction size Y R of the recognition layer are determined by following: X R =a ( DP +GAP)+ DP Y R =b ( DP +GAP)+ DP, wherein a and b are positive integers, respectively.