Patent ID: 8806316

Claim:
An interleaved parity computation circuit, comprising: a first parity circuit configured to receive a first set of bits including a first parity bit during a first clock cycle and generate a first asynchronous signal indicative of the parity of the first set of bits, the first parity circuit including a first input latch coupled to a first parity generator, the first parity generator coupled to a first asynchronous latch configured to provide the first asynchronous signal, the first parity generator configured to check the parity of the first set of bits and provide a first result to the first asynchronous latch; a second parity circuit distinct from the first parity circuit and configured to receive a second set of bits including a second parity bit during a second clock cycle and generate a second asynchronous signal indicative of the parity of the second set of bits, the second parity circuit including a second input latch coupled to a second parity generator, the second parity generator coupled to a second asynchronous latch configured to provide the second asynchronous signal, the second parity generator configured to check the parity of the second set of bits and provide a second result to the second asynchronous latch; and a combining circuit coupled to the first and second parity circuits and configured to provide a signal, based at least in part on the first and second asynchronous signals, indicative of whether the parity of at least one of the first and second set of bits was incorrect.