Patent ID: 7453733

Claim:
A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of blocks each including a plurality of electrically reprogrammable nonvolatile memory cells; a first circuit for selecting one from said plurality of blocks, said first circuit having a plurality of transistors connected to word lines connected to some of said nonvolatile memory cells; and a second circuit for generating a first voltage V 1 , a second voltage V 2 and a third voltage V 3 , a fourth voltage V 4 and a fifth voltage of V 5 satisfying following expressions: V3<V2<V1; V3<V4; and V3<=V5, said first voltage V 1 being applied to a source or drain of one of said transistors connected to a selected word line at a time of programming, said second voltage V 2 being applied to sources or drains of a plurality of said transistors connected to non-selected word lines at the time of programming, said third voltage V 3 being applied to a source or a drain of one of said transistors connected to at least one of said non-selected word lines at the time of programming, said third voltage V 3 being higher than a well or substrate voltage of said plurality of transistors, said fourth voltage V 4 being applied to said source or said drain of one of said transistors connected to said selected word line in the period from the time when said second voltage V 2 is applied to corresponding said transistors connected to said non-selected word lines until the time of programming, said fifth voltage V 5 being applied to said source or said drain of one of said transistors connected to said selected word line following the time of programming and said second voltage V 2 continuing to be applied to corresponding said transistors connected to said non-selected word lines.