Patent ID: 8804420

Claim:
A semiconductor memory device, comprising: a memory unit including a plurality of memory cores divided into a plurality of columns, each of the memory cores including bit lines, word lines, and a plurality of memory cells, each of the memory cells capable of storing multiple bits of data; a row decoder configured to select the word lines in the memory core according to an address signal; column control circuits configured to control input/output of data to/from the plurality of memory cells via the bit lines; and a control circuit configured to control the row decoder and the column control circuits, at least one of the plurality of columns being an LM column for storing LM flag data indicating a progression state of a write operation of the multiple bits of data, and each of the column control circuits being configured to execute an LM address scan operation for confirming whether the LM column exists in a corresponding one of the memory cores or not, and then stores a result of the LM address scan operation in a register, in various kinds of operations after the LM address scan operation, each of the column control circuits being operative to execute an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data stored in the register is first data, and omit executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data stored in the register is second data.