Patent ID: 8466503

Claim:
A semiconductor structure, comprising: (a) a semiconductor region including a channel region, a first source/drain region, and a second source/drain region, wherein the channel region is disposed between the first source/drain region and the second source/drain region, and wherein a first direction from the semiconductor region to the channel region is perpendicular to a top surface of the semiconductor region; (b) a gate dielectric region in direct physical contact with the channel region; and (c) a gate electrode region including a top portion and a bottom portion, wherein the bottom portion is in direct physical contact with the gate dielectric region, wherein the gate electrode region is electrically insulated from the channel region by the gate dielectric region, and wherein a first upper portion and a second upper portion of the first and second source/drain regions are wider in a second direction perpendicular to the first direction than are a first lower portion and a second lower portion of the first and second source/drain regions, respectively; wherein the first upper portion of the first source/drain region consists of a first upper layer and a first lower layer; wherein the first upper layer comprises a first silicide and an implanted material; wherein the first lower layer comprises silicon and the implanted material and does not comprise the first silicide; wherein the second upper portion of the second source/drain region consists of a second upper layer and a second lower layer; wherein the second upper layer comprises a second silicide and the implanted material; wherein the second lower layer comprises silicon and the implanted material and does not comprise the second silicide, wherein the first upper layer is above the gate dielectric region in the first direction such that the gate dielectric region is disposed in the first direction between the channel region and the first upper layer, and wherein the second upper layer is above the gate dielectric region in the first direction such that the gate dielectric region is disposed in the first direction between the channel region and the second upper layer.