Patent ID: 7221188

Claim:
A logic circuit comprising: an evaluate circuit having a plurality of inputs, the evaluate circuit including a dynamic node, the evaluate circuit including an evaluate device having an input coupled to a clock line, the evaluate circuit including a full keeper coupled to the dynamic node; a static output circuit including a first input coupled to the dynamic node, the static output circuit including a sample device, the sample device including an input coupled to the clock line, the static output circuit including an output; a second evaluate circuit having a second plurality of inputs, the second evaluate circuit including a second dynamic node, the second evaluate circuit including a second evaluate device having an input coupled to a clock line, the second evaluate circuit including a second full keeper coupled to the second dynamic node; wherein the static output circuit includes a second input coupled the second dynamic node; wherein the full keeper includes: a first transistor having a first current terminal coupled to a first voltage supply, the first transistor having a second terminal coupled to the dynamic node; a second transistor having a third current terminal coupled to the dynamic node; wherein the first transistor, the second transistor, and the evaluate device are coupled in series.