Patent ID: 8653602

Claim:
A semiconductor transistor device comprising: a substrate; a p-doped region within and exposed through the substrate; an n-doped region within and exposed through the substrate, each of the p-doped region and the n-doped region having a first top surface and a center thereof, and a second top surface at sides thereof, the second top surface lower than the first top surface to define notches within each of the p-doped region and the n-doped region between the first top surface and the second top surface; vertical spacers over each of the p-doped region and the n-doped region; silicide within the notches defined within each of the p-doped region and the n-doped region, the silicide having a top surface flush with the first top surface of each of the p-doped region and the n-doped region, the silicide lowering contact resistance between a source and a drain of the semiconductor transistor device and a corresponding contact of the semiconductor transistor device; a mask layer over the substrate; a first replacement metal gate within the mask layer and over the p-doped region, comprising a first interfacial layer adjacent to side surfaces of the mask layer and to the top surface of the p-doped region, and a first layer at least partially diffused into the first interfacial layer, to one or more of: reduce a threshold voltage of the transistor and reduce a thickness of an inversion layer of the semiconductor transistor device; and a second replacement metal gate within the mask layer and over the n-doped region, comprising a second interfacial layer adjacent to side surfaces of the mask layer and to the top surface of the n-doped region, and a second layer at least partially diffused into the second interfacial layer, to one or more of: reduce the threshold voltage of the transistor and reduce the thickness of an inversion layer of the semiconductor transistor device, wherein the second layer is different than the first layer.