Patent ID: 7495949

Claim:
An asymmetrical random access memory cell ( 1 ) comprising: a first cross coupled inverter ( 2 ) having a first node ( 22 ); a second cross coupled inverter ( 3 ) having a second node ( 32 ); a pair of complementary bit-lines comprising a first bit-line blc), the first bit-line coupled to the first node; and a second bit line (blt), the second bit-line coupled to the second node; the first bit-line being coupled to a first pass-transistor ( 21 ); the second bit-line being coupled to a second pass-transistor ( 31 ); wherein, the first cross coupled inverter ( 2 ) comprises a different switching threshold than the second cross coupled inverter such that the first and second cross coupled inverters provide asymmetrical physical behaviours; and wherein the third pass-transistor ( 4 ) is coupled in series to the first pass-transistor ( 21 ) between the first node and the first bit-line (blc).