Patent ID: 8385394

Claim:
A method of measuring clock signal jitter, said method comprising: receiving, by a built in self test circuit, an initial clock signal from an on-chip phase locked loop; dividing a frequency of said initial clock signal by two in order to produce a feedback clock signal; performing a coarse tuning process using a delay locked loop of a built in self test (BIST) circuit, said coarse tuning processing comprising delaying said initial clock signal from said on-chip phase locked loop until a delayed clock signal with a predetermined phase shift from said initial clock signal is achieved and locking in said delayed clock signal such that said initial clock signal and said delayed clock signal are out of phase; performing a fine tuning process using a Vernier delay line of said BIST circuit, said fine tuning process comprising receiving and simultaneously propagating said initial clock signal and said delayed clock signal to acquire data indicating phase differences between said initial clock signal and said delayed clock signal; processing said data to measure cycle-to-cycle jitter of said initial clock signal; using said Vernier delay line to acquire additional data indicating phase differences between said feedback clock signal and a reference clock signal; and processing said additional data to measure phase jitter between said reference clock signal and said feedback clock signal.