Patent ID: 8917550

Claim:
A memory module comprising: at least two non-volatile memory devices, each device comprising: a memory array having a plurality of non-volatile memory cells coupled to word lines and bit lines; a plurality of cache registers for inhibiting programming of a column of memory cells, each cache register coupled to a pair of bit lines; a plurality of data caches for storing data to be programmed, each data cache coupled to the pair of bit lines; and a memory controller circuit coupled to the memory array, the controller circuit configured to execute a method for programming the plurality of memory cells such that the controller circuit generates a series of program and verify pulses to program original data into a row of memory cells, sets each respective cache register in response to a successful verification, performs a subsequent verification operation to determine verified data, and performs a post-programming program operation on the row of memory cells if the verified data is different from the original data; and a plurality of contacts configured to provide selective contact between the memory devices and a host system.