Patent ID: 8822290

Claim:
A method comprising: recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin; forming a dummy gate to cover a middle portion of the semiconductor fin; forming an Inter-Layer Dielectric (ILD) to cover end portions of the semiconductor fin, wherein the end portions of the semiconductor fin are on opposite sides of the middle portion; removing the dummy gate to form a first recess, wherein the middle portion is exposed to the first recess; removing the middle portion of the semiconductor fin from the first recess to form a second recess; performing an epitaxy to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions; and forming a gate dielectric and a gate electrode in the first recess, wherein the gate dielectric and the gate electrode are over the semiconductor material.