Patent ID: 7180165

Claim:
A chip-scale package comprising: a substrate having a first surface and an opposite second surface, the substrate composed of a controlled thermal expansion material; a memory die having a first surface and an opposite second surface, the first surface of the memory die mounted facing the first surface of the substrate, the memory die is electrically coupled to the substrate using a plurality of rigid underside coupling members, the substrate having a coefficient of expansion that matches a coefficient of expansion of the memory die to within six parts per million per degree Celsius or less, wherein the second surface of the memory die remains completely exposed; a plurality of solder balls mounted on the first surface of the substrate in a ball grid away configuration adjacent to the memory die, at least one of the solder balls electrically coupled to at least one of the underside coupling members; a plurality of pads coupled to the second surface of the substrate, each pad electrically coupled to one or more of the plurality of solder balls in a staggered routing scheme; and one or more electronic components mounted on the second surface of the substrate in an area opposite of the memory die, wherein the combined distance that an electronic component and the memory die protrude from the substrate is less than the distance that a solder ball and pad protrude from the substrate.