Patent ID: 7034628

Claim:
An oscillator circuit comprising: a first node; a second node; a logic device that includes a number of serially-connected logic blocks, the serially-connected logic blocks having a first logic block that is connected to the first node, and a last logic block that is connected to the second node; and a start-up time reduction circuit connected to the first and second nodes, the start-up time reduction circuit having: a gain stage that has two serially-connected logic blocks that lie in parallel with the last two logic blocks of the logic device such that an input of a first logic block of the last two logic blocks of the logic device and an input of a first logic block of the gain stage are connected together; a plurality of control transistors connected to the gain stage; and a control circuit connected to the first node and the control transistors, the control circuit outputting a plurality of enable signals to the control transistors to enable the gain stage only when a magnitude of a voltage on the first node is within a predetermined range.