Patent ID: 8368425

Claim:
A level shifter, comprising: a first N-type transistor and a second N-type transistor, forming a differential input pair, wherein a gate of the first N-type transistor and a gate of the second N-type transistor receive an input signal and an inverted input signal, respectively, and a source of the first N-type transistor and a source of the second N-type transistor are coupled to ground, and wherein the input signal and the inverted input signal are operated within a first voltage range associated with a first power; a first P-type transistor and a second P-type transistor, configured between a second power and the differential input pair and cross-coupled to each other to make a gate of the first P-type transistor and a gate of the second P-type transistor operate within a second voltage range associated with the second power, wherein a source of the first P-type transistor and a source of the second P-type transistor are both coupled to the second power, a drain of the first P-type transistor and a drain of the second P-type transistor are coupled to a drain of the first N-type transistor and a drain of the second N-type transistor, respectively, the gate of the first P-type transistor is coupled to the drain of the second P-type transistor, and the gate of the second P-type transistor is coupled to the drain of the first P-type transistor; a first voltage rising circuit, coupling the second power to the gate of the first P-type transistor when the input signal changes from a first low voltage level of the first voltage range to a first high voltage level of the first voltage range; and a second voltage rising circuit, coupling the second power to the gate of the second P-type transistor when the input signal changes from the first high voltage level to the first low voltage level, wherein, the first voltage rising circuit comprises: a third P-type transistor, having a source coupled to the second power, a drain coupled to the gate of the first P-type transistor, and a gate; and a first NAND gate, receiving the input signal and a first signal, and generating an output to control the gate of the third P-type transistor, wherein: the first signal is a voltage level at the gate of the second P-type transistor, or is generated by inverting the voltage level at the gate of the second P-type transistor by an even number of inverters, or is generated by inverting a voltage level at the gate of the first P-type transistor by an odd number of inverters; and the first NAND gate comprises a third N-type transistor and a fourth N-type transistor, wherein the third and fourth N-type transistors are coupled in series between the gate of the third P-type transistor and the ground, a gate of the third N-type transistor is operative to receive the input signal while a gate of the fourth N-type transistor is operative to receive the first signal.