Patent ID: 8516426

Claim:
A method for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components, at least two stack components of the multiple stack components being on different ones of the two or more strata, the method comprising: storing a plurality of operating modes that respectively have different power dissipations; determining, by a controller, a respective effective power budget for each of the at least two stack components based on respective ones of the plurality of operating modes targeted for the at least two stack components, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components; and selectively accepting or re-allocating the respective ones of the plurality of operating modes targeted for the at least two stack components based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints, wherein the power constraints comprise vertical structure electrical constraints.