Patent ID: 7791679

Claim:
A device comprising a plurality of first thin film transistors and a plurality of second thin film transistors, each of said first and said second thin film transistors comprising a source electrode, a gate electrode, and a drain electrode; wherein at least one of said first thin film transistors comprises the source electrode, the gate electrode and the drain electrode being sequentially arranged along a normal orientation away from its corresponding data line, at least one of said second thin film transistors comprises the drain electrode, the gate electrode and the source electrode being sequentially arranged along a reverse orientation away from its corresponding data line; and wherein, in the second thin film transistor, (i) a crossover is formed by the data line corresponding to the second thin film transistor and the gate electrode of the second thin film transistor when the data line is connected to the source electrode of the second thin film transistor; or (ii) a first crossover is formed by the data line corresponding to the second thin film transistor and the gate line connected to the second thin film transistor when the data line is connected to the source electrode of the second thin film transistor, the first crossover being spaced apart from a second crossover where the gate line connected to the second thin film transistor crosses the data line corresponding to the second thin film transistor; wherein said crossover in (i) or said first crossover in (ii) serve to effect substantially the same source electrode and drain electrode orientation as in said first thin film transistor; wherein said first thin film transistors comprise a crossover to substantially balance any parasitic capacitance affected by said crossover in said second thin film transistor.