Patent ID: 7741645

Claim:
A semiconductor structure comprising: a first semiconductor substrate comprising a first semiconductor material having a first melting point; a first set of semiconductor devices located on said first semiconductor substrate; a via-level dielectric layer located on said first set of semiconductor devices and containing first contact vias contacting said first set of semiconductor devices; a planar dielectric layer locating on a top surface of said via-level dielectric layer; a second semiconductor substrate located over said first semiconductor substrate, said first set of semiconductor devices, and said planar dielectric layer, wherein said second semiconductor substrate comprises a second semiconductor material having a second melting point, wherein said second melting point is lower than said first melting point; a second set of semiconductor devices abutting said second semiconductor substrate; and at least one inter-substrate via vertically extending through said second semiconductor substrate and said planar dielectric layer, said at least one inter-substrate via comprising a metal, wherein no semiconductor material is embedded between a planar top surface of said planar dielectric layer and a bottom surface of said planar dielectric layer.