Patent ID: 7940876

Claim:
A frequency synchronizing apparatus for synchronizing a slave device with a start of frame (SOF) signal to mark a reference interval, comprising: a frequency divider, used to receive a high-frequency signal and divide the high-frequency signal by a variable frequency factor to obtain a lock frequency signal; a counter unit, having a default pulse number, for obtaining a currently detected deviation by calculating a difference between the default pulse number and a pulse number of the lock frequency signal during a current reference interval; an operating unit, used to generate an error adjusting value based on the currently detected deviation, wherein the operating unit includes: a register, used to receive the currently detected deviation, and generate the error adjusting value after a content of the resister is updated by adding up the currently detected deviation and a previously detected deviation which has been already stored in the resister; and an error accumulator, used to accumulate all the detected deviations, and perform a value tuning process when a sum of all the detected deviations exceeds a threshold value; and an adjusting unit, used to receive the error adjusting value and generate a proportional adjusting value, so that the frequency divider adjusts the variable frequency factor based on the error adjusting value at every proportional adjusting value of a next reference interval; wherein by adjusting the variable frequency factor, the slave device receives the lock frequency signal and synchronizes a frequency with a master device to which the slave device connects.