Patent ID: 7316954

Claim:
A method of fabricating an integrated circuit device, comprising: forming an impurity region of a first conductivity type in a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a first contact hole exposing the impurity region, in the first insulating layer; forming a first poly Si 1-x Ge x conductive plug of the first conductivity type directly contacting the exposed impurity region, in the first contact hole; forming a second insulating layer on the first poly Si 1-x Ge x conductive plug and the first insulating layer; forming a second contact hole exposing the first poly S 1-x Ge x conductive plug, in the second insulating layer; and forming a second poly Si 1-x Ge x conductive plug of the first conductivity type on the first poly Si 1-x Ge x conductive plug, in the second contact hole.