Patent ID: 7692950

Claim:
A semiconductor memory device comprising: first and second active areas extending in a first direction on a semiconductor substrate; first and second split word lines extending in a second direction on the semiconductor substrate; a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas; a first variable resistance element formed on the first active area between the first and second split word lines; a second variable resistance element formed on the second active area between the first and second split word lines; first and second bit lines extending in the first direction, and respectively coupled to the first and second variable resistance elements, a first contact coupling the first active area to the first variable resistance element; a second contact formed on the opposite side of the first contact with respect to the first split word line and coupling the first active area to the common source line; a third contact formed on the opposite side of the second contact with respect to the second split word line and coupling the first active area to the common source line; a fourth contact coupling the second active area to the second variable resistance element; a fifth contact formed on the opposite side of the fourth contact relative with respect to the first split word line and coupling the second active area to the common source line; and a sixth contact formed on the opposite side of the fourth contact with respect to the second split word line and coupling the second active area to the common source line.