Patent ID: 6903016

Claim:
A method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the method comprising: depositing a barrier layer over the field and inside surfaces of the at least one opening; depositing a non-conformal seed layer and a conformal seed layer over the barrier layer, wherein the non-conformal seed layer is deposited by a PVD technique and the conformal seed layer is deposited by a CVD technique prior to depositing the non-conformal seed layer, and wherein a thickness of the non-conformal seed layer is in a range of about 100 Å to about 3,000 Å over the field and a thickness of the conformal seed layer is in a range of about 50 Å to about 500 Å over the field, the non-conformal and the conformal seed layers do not seal the at least one opening, thereby leaving enough room for electroplating inside the at least one opening; and electroplating a metallic layer over the non-conformal and the conformal seed layers, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.