Patent ID: 7315969

Claim:
A memory module, comprising: an electronic printed circuit board; a plurality of integrated memory chips arranged on the printed circuit board; a test device arranged on the printed circuit board separately from the memory chips and configured to test the memory chips; a control line for receiving control commands from the test device, the control line branching at a node into a plurality of control lines that respectively supply the control commands to the memory chips; an address line for receiving address commands from the test device, the address line branching at a node into a plurality of address lines that respectively supply the address commands to the memory chips; and a plurality of selections lines, each of the selection lines connecting an individual one of the memory chips to the test device, wherein the test device is configured to individually activate and deactivate memory chips for testing by supplying a selection signal to an individual memory chip on a respective selection line, such that the memory chips are individually selectable for testing via the selection lines; wherein the test device, for testing the memory chips, autonomously generates the control commands, the address commands, and data values, without receiving any control command, address command, or data value from outside, in response to an external clock signal being supplied to the memory module, the test device supplying the control commands to the memory chips via the control lines and supplying the address commands to the memory chips via the address lines, the test device supplying the data values to the memory chips for storage in the memory chips during testing.