Patent ID: 7495929

Claim:
A system, comprising: a processor; a memory; a disk drive; and a circuit board including a semiconductor device interface bus to couple the processor, the memory, and the disk drive to each other, the circuit board including a dielectric layer, the semiconductor device interface bus including a plurality of traces disposed in the dielectric layer, and the circuit board further including: a first reference layer disposed on a first side of the dielectric layer, the first reference layer including a plurality of openings having a first opening in a breakout region of the first reference layer and a second opening in another region of the first reference layer, a diameter of the first opening being smaller than a diameter of the second opening; and a second reference layer disposed on a second side of the dielectric layer, the second reference layer including a second plurality of openings, the first plurality of openings being arranged in a substantially alternating manner with respect to the second plurality of openings, and the first and second plurality of openings being complementarily disposed to contribute to achieving a differential impedance for at least a pair of traces of the plurality of traces.