Patent ID: 7711873

Claim:
A first processor that executes an application, the first processor comprising: a first interface module that interfaces said first processor to a second processor, said first interface module including N interfaces, where N is an integer greater than 1; and a first communication control module (CCM) that is coupled to said first interface module and that selects M interfaces from said N interfaces based on bandwidth requested by said application to transmit data generated by said application to said second processor, where M is an integer and 1≦M≦N, wherein said first CCM comprises: a first transmit buffer that buffers first data generated by said application; and a first splitter module that receives said first data from said transmit buffer and outputs said first data to said M interfaces, wherein when M>1, said first splitter module splits said first data into first portions and outputs said first portions to said M interfaces based on data rates of said M interfaces.