Patent ID: 7564713

Claim:
A semiconductor integrated circuit device comprising: nonvolatile semiconductor memory cells, each memory cell being able to store at least a first bit and a second bit based on threshold voltage state; bit lines each connected to one end of the nonvolatile semiconductor memory cells; a data circuit connected to the bit lines to temporarily store program data for the nonvolatile semiconductor memory cells; the data circuit supplying, during a data program operation, a first program potential, a second program potential, or a third program potential to each bit line; the first program potential, which is lower than the second program potential, being supplied until the threshold voltage of the nonvolatile memory cell surpasses a first-pass level less than a second-pass level; the second program potential, which is lower than the third program potential, being supplied when the threshold voltage of the nonvolatile memory cell is between the first-pass level and the second-pass level; the third program potential being supplied after the threshold voltage of the nonvolatile memory cell surpasses the second-pass level; and the second program potential for the first bit being different from the second program potential for the second bit.