Patent ID: 7666732

Claim:
A method of fabricating a semiconductor structure comprising: providing a structure comprising a semiconductor substrate including at least one nFET device region and at least one pFET device region, said device regions are separated by an isolation region and said at least one nFET device region includes a first gate dielectric stack having a net dielectric constant greater than silicon dioxide located on a surface of said substrate and said at least one pFET device region has a second gate dielectric stack having a net dielectric constant greater than silicon dioxide located on a surface of said substrate, said first gate dielectric stack is different from said second gate dielectric stack and said first gate dielectric stack contains no net negative charge and said second gate dielectric stack contains no net positive charge; and forming a single metal layer on said first and second gate dielectric stacks, wherein said singe metal layer atop the first gate stack provides an nFET gate stack having a band edge workfunction and wherein said single metal layer atop the second gate dielectric stack provides a pFET having a ¼ gap workfunction.