Patent ID: 7065738

Claim:
A method of verifying an optical proximity correction (OPC) model for use with an OPC simulation tool that manipulates an integrated circuit layout corresponding to a layer to be embodied in a wafer by a photolithographic technique, the method comprising: a) correcting a test pattern having a plurality of structures with the OPC simulation tool using the OPC model to generate a corrected output file for the test pattern; b) extracting critical dimension (CD) values from the corrected output file for layout locations corresponding to a plurality of selected structures of the test pattern; c) developing a data set from the extracted CD values, the data set indicative of corrected test pattern CD versus pitch for at least one target CD and the data set from the extracted CD values includes a plot of corrected test pattern CD versus pitch; d) comparing the data set for the extracted CD values with an experimentally derived data set, the experimentally derived data set indicative of reticle opening CD versus pitch that when imaged using the photolithographic technique produce wafer structures having the at least one target CD and the experimentally derived data set includes a plot of actual reticle opening CD that can be used to print the at least one target CD versus pitch, and wherein the comparing is carried out by establishing a difference between the plots; and wherein a), b), c) and d) are carried out for each of a plurality of OPC models and the method further comprises selecting one of the plurality of OPC models that has the closest correlation between compared data sets.