Patent ID: 8872271

Claim:
A pass gate provided between a data holding unit of an SRAM cell and a bit line, comprising: a first tunnel transistor and a first diode connected in series between the data holding unit and the bit line; and a second tunnel transistor and a second diode connected in series between the data holding unit and the bit line and connected in parallel to the first tunnel transistor and the first diode, wherein: gate electrodes of the first tunnel transistor and the second tunnel transistor are connected to a word line; the first diode and the second diode have rectification in mutually opposite directions between the data holding unit and the bit line; the first tunnel transistor and the second tunnel transistor are n-type tunnel transistors having an n-type drain region and a p-type source region; the first diode has rectification in a same direction as an operation direction of the first tunnel transistor; and the second diode has rectification in a same direction as an operation direction of the second tunnel transistor.