Patent ID: 8601204

Claim:
A memory apparatus for use with a host system, the memory apparatus comprising: a plurality of memory circuits; and an interface circuit including: one or more first components of a first type, each of the one or more first components being electrically couplable to the host system; and one or more second components of a second type different from the first type, each of the one or more second components being electrically couplable to the host system, the interface circuit being operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits, the at least one aspect comprising a timing that relates to a refresh operation latency, wherein each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component of the one or more first components and to at least one second component of the one or more second components.