Patent ID: 8604863

Claim:
A switch control circuit, comprising: a first terminal, a second terminal, and a third terminal; a serial-parallel converter configured to convert a serial switching control signal inputted from the third terminal into first parallel switching control signals in synchronization with a clock signal inputted from the second terminal when the first terminal is at a first power-supply potential, and to stop this operation when the first terminal is at a second power-supply potential; a selector configured to select either the first parallel switching control signals converted by the serial-parallel converter or second parallel switching control signals inputted into the second and third terminals, depending on the potential of the first terminal; a driver circuit configured to convert potential levels of the first parallel switching control signals or the second parallel switching control signals selected by the selector, and to generate parallel switching control signals with potential levels capable of switching a switch circuit; and a tri-state buffer configured to comprise an input terminal connected to the serial-parallel converter and an output terminal connected to the third terminal, the tri-state buffer capable of setting the output terminal to high impedance.