Patent ID: 7042799

Claim:
A write circuit of a DDR SDRAM, comprising: a multiplexer for outputting, in response to a data strobe rising signal and a data strobe falling signal, a data on the rising edge and the falling edge; an input data strobe generator for outputting, according to a start address flag, a data input strobe even signal and a data input strobe odd signal by using the data strobe falling signal; a skew detector for detecting a skew between an internal clock and an internal data strobe signal and outputting a skew detection signal; a skew compensation circuit for controlling, in response to the skew detection signal, the internal clock and outputting a prewrite strobe signal with the skew compensated; a write strobe generator for outputting, in response to the prewrite strobe signal, a write strobe signal; a data register for classifying, in response to the data input strobe even signal and the data input strobe odd signal, a output data from the multiplexer into an even data and an odd data, and outputting the data through first and second gio bus lines; and first and second write driver for synchronizing the output data with the write strobe signal and inputting the data to a DRAM core through first and second local input/output bus lines.