Patent ID: 7388292

Claim:
An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, a second opening in said passivation layer exposing a second pad of said first metallization structure, and a third opening in said passivation layer exposing a third pad of said first metallization structure, wherein said first, second and third pads are separate from one another, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; a second metallization structure over said passivation layer and over said first, second and third pads, wherein said second metallization structure comprises electroplated copper, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, said third metal layer having a thickness greater than those of said first and second metal layers, and said fourth metal layer having a thickness greater than those of said first and second metal layers, and wherein said first pad is connected to said second and third pads through a clock distribution network of said second metallization structure, and said second pad is connected to said third pad through said clock distribution network; and a first polymer layer between said third and fourth metal layers, wherein said first polymer layer has a thickness greater than those of said passivation layer, said first dielectric layer and said second dielectric layer.