Patent ID: 7313778

Claim:
A method of designing a programmable logic device comprising the steps of: defining modules of a circuit design comprising components of a same type; prior to annealing the circuit design, determining a set of static shapes for each module, wherein each shape of the set of static shapes for each module is sized so that utilization of sites within the shape by components of the module associated with the shape is less than a threshold utilization; annealing the circuit design to determine a floorplan by, at least in part, for each module during a first iteration of annealing, selecting a shape from the set of static shapes associated with the module and applying the selected shape to the module; and for at least one module during at least one further iteration of annealing, selecting a different shape from the set of static shapes associated with the at least one module and applying the different shape to the at least one module, wherein each iteration of annealing the circuit design is evaluated according to evaluation of a cost function.