Patent ID: 7751517

Claim:
A system for synchronized data communication comprising: a first communication interface for receiving data and a first clock signal, the first clock signal being associated with a transmitting source; a second communication interface for sending data; a processing component for separating a single data stream into multiple data streams; a clock being configured to provide a second clock signal; a plurality of buffer components for providing data lanes for data streams, each of the buffer components being characterized by a predetermined buffer size, the plurality of buffering component including a first buffer component and a second buffer component, the first buffer component being configured to received a first clock signal and a second data signal, the first buffer component further comprising a write pointer and a read pointer, the write pointer being adaptably synchronized to the first clock signal, the read pointer being adaptably synchronized to the second clock signal; a first half-full state calculator configured for determining at least a first half-full state status at least for the first buffer component; and a controller component being configured to determining an offset value for each of the buffer component, the offset value being associated with the first half-status and a relative position of indicators of the plurality of buffers; wherein: the first buffer component inserts or removes one or more offset indicators if the difference between the first clock signal and a second clock signal is greater than a clock threshold value; the first buffer component updates the read pointer based on an offset value determined by the controller component; the first buffer component increments the read pointer if an amount of data stored in the first buffer is greater than a first buffer threshold value; the first buffer component decrements the read pointer if an amount of data stored in the first buffer is less than a second buffer threshold value.