Patent ID: 8400820

Claim:
A memory cell, comprising: a first data node; a pull-up branch coupled to the first a data node; a pull-down branch coupled to the first data node; and a impedance adjuster coupled to the first data node; the memory cell further comprising: first, second, third, and fourth supply nodes; a first stage, wherein the first stage comprises: the pull-up branch comprising a first transistor having a first path node coupled to the first supply node, a second path node coupled to the data node, and a control node; and the pull-down branch comprising a second transistor having a first path node coupled to the second supply node, a second path node coupled to the data node, and a control node coupled to the control node of the first transistor; and wherein the impedance adjuster comprises: a third transistor having a first path node coupled to the third supply node, a second path node coupled to the data node, and a control node coupled to the control nodes of the first and second transistors; and a fourth transistor having a first path node coupled to the fourth supply node, a second path node coupled to the data node, and a control node coupled to the control nodes of the first and second transistors.