Patent ID: 7996660

Claim:
A computer system comprising a central processing unit (CPU), the CPU comprising: an instruction execution pipeline having a plurality of pipeline stages; detection circuitry for detecting a pipeline stage conflict; stall circuitry connected to receive a detection signal from the detection circuitry and operable to stall a portion of the instruction execution pipeline until the pipeline stage conflict is resolved; mode circuitry connected to the stall circuitry having a protected mode enabling the stall circuitry and a non-protected mode disabling the stall circuitry; and interrupt circuitry connected to the mode circuitry and responsive to receipt of an interrupt signal to store an indication of a current mode of the mode circuitry, cause the mode circuitry to enter the protected mode, perform an interrupt service routine corresponding to the received interrupt signal in the protected mode, and upon completion of the interrupt service routine restore the mode circuitry to a mode corresponding to the stored indication of current mode.