Patent ID: 8169228

Claim:
A chip testing circuit, comprising: a first compressing circuit, for generating a first compressing signal according to a first group of feedback signals outputted by the chip wherein the first group of feedback signals comprises a first feedback signal; a second compressing circuit, for generating a second compressing signal according to a second group of feedback signals outputted by the chip wherein the second group of feedback signals comprises a second feedback signal; a judging circuit, coupled to the first and the second compressing circuits, for generating a judging signal selectively according to one of the following signals or combination thereof: the first compressing signal, the second compressing signal, the first feedback signal, and the second feedback signal; and an interface circuit, coupled to the judging circuit and receiving the first feedback signal or the second feedback signal, for generating a test result according to a comparison between the judging signal and the first feedback signal or the second feedback signal to determine whether the chip has a defect or not.