Patent ID: 8400742

Claim:
An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad, the ESD protection circuit comprising: a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage; an inverter having an input end and an output end, the output end of the inverter being coupled with a gate of the clamp FET; a resistance-capacitance (RC) time constant circuit coupled between the first supply voltage and the second supply voltage; a current mirror including a first transistor, the current mirror being coupled between the input end of the inverter and the second supply voltage; and a circuit coupled with the input end of the inverter, the circuit being capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.