Patent ID: 8457269

Claim:
A clock and data recovery (CDR) architecture, comprising: a frequency detector configured to receive a data signal and a plurality of clock signals with different phases to generate a plurality of intermediate signals and generate a frequency control signal, wherein the plurality of intermediate signals indicate relation between the data signal and the plurality of clock signals; a phase detector configured to generate a phase control signal according to the intermediate signals; a phase charge pump circuit configured to output a first current signal according to the phase control signal; a frequency charge pump circuit configured to output a second current signal according to the frequency control signal; a voltage controlled oscillator configured to output an adjusted clock signal according to the first current signal and the second current signal; an up/down counter configured to receive the phase control signal to accordingly adjust a counter value; and an adaptive phase interpolator configured to interpolate the plurality of clock signals with different phases according to the counter value and the adjusted clock signal, and select at least one of the plurality of clock signals with different phases for sampling the data signal.