Patent ID: 7642601

Claim:
A semiconductor integrated circuit device comprising: memory cells of a random access memory arranged in at least a first direction and each memory cell including a first n channel MISFET, a second n channel MISFET, a first p channel MISFET and a second p channel MISFET, the first n channel MISFET separately arranged, in a second direction crossing the first direction, from the first p channel MISFET in the memory cell, the second p channel MISFET separately arranged, in the second direction, from the second n channel MISFET in the memory cell, a drain region of the first n channel MISFET electrically connected to a drain region of the first p channel MISFET by a first interconnection in the memory cell, a drain region of the second n channel MISFET electrically connected to a drain region of the second p channel MISFET by a second interconnection in the memory cell, the first interconnection comprised of a same level metal layer as the second interconnection; a first wiring line electrically connected to a source region of the first n channel MISFET and a source region of the second n channel MISFET in the memory cell, the first wiring line extending in the first direction and comprised of a higher level metal layer than first interconnections and second interconnections of the memory cells; a second wiring line electrically coupled to the first wiring line and comprised of a different level metal layer from the first wiring line, the second wiring line extending in the second direction; a third wiring line extending in the second direction and comprised of the same level metal layer as the second wiring line, the second wiring line and the third wiring line being spaced apart, in the first direction, from each other through the memory cells and electrically coupled to the first wiring line; a first switch circuit including a first MISFET, and in which the second wiring line is electrically connected to one of a source region and a drain region of the first MISFET of the first switch circuit; and a second switch circuit including a second MISFET and separately arranged in the first direction from the second wiring line, and in which the third wiring line is electrically connected to one of a source region and a drain region of the second MISFET of the second switch circuit, wherein the first MISFET of the first switch circuit and the second MISFET of the second switch circuit turn off at a standby mode, and wherein the first MISFET of the first switch circuit (SW 2 ) and the second MISFET of the second switch circuit (SW 2 ) turn on at an active mode in which a reference voltage is applied to the first wiring line through the second wiring line and the third wiring line.