Patent ID: 7007132

Claim:
Digital processing apparatus comprising: a processor including a microcontroller for executing microcontroller instructions, the instructions including memory access instructions, said processor generating a next access signal that indicates if a next memory access by said processor is in sequence with a current memory access, wherein the next access signal is asserted when memory accesses are sequential and is deasserted when memory accesses are non-sequential; a flash memory having a continued burst mode of operation, said memory having a memory bus for communication with said processor; and a bus interface unit for controlling access to said memory in response to the memory access instructions, said bus interface unit enabling the continued burst mode of the memory while the next access signal is asserted and inhibiting the continued burst mode of the memory when the next access signal is deasserted to provide a continued burst mode of variable length in response to the next access signal and to avoid reading of unused words, wherein the variable length of the continued burst mode is dynamically controlled in response to the next access signal.