Patent ID: 7984281

Claim:
An apparatus comprising: a hardware multi-threaded processor comprising: a plurality of threads, wherein each of the plurality of threads is enabled to service an interrupt; a first configuration register indicating an interrupt logic level; a second configuration register indicating an interrupt trigger; and an automatic disable interrupt register including a plurality of bits, each bit of the plurality of bits associated with a corresponding interrupt of a plurality of interrupts; and processing logic comprising: a first multiplexer including an interrupt input, an output, and an interrupt logic level select input responsive to the first configuration register to selectively output the first interrupt at the output, wherein the first interrupt is received at the interrupt input; an edge detection circuit coupled to the output and configured to detect a rising or falling edge of the first interrupt; and a level detection circuit coupled to the output and adapted to detect a logic level associate with the first interrupt; wherein the processing logic is configured to: receive a first interrupt; select a first thread of the plurality of threads, wherein the first thread is selected based on the interrupt logic level, the interrupt trigger, and a first bit of the plurality of bits of the automatic disable interrupt register, wherein the first bit of the plurality of bits corresponds to the first interrupt; provide access by the first thread to the first interrupt of the plurality of interrupts; set the first bit of the plurality of bits of the automatic disable interrupt register while the first interrupt is being serviced by the first thread; and prevent access to the first interrupt by a second thread of the plurality of threads while the first interrupt is being serviced by the first thread of the plurality of threads.