Patent ID: 7786802

Claim:
An output stage circuit adapted for enhancing a driving capability of an output signal outputted by an amplifying circuit, the output stage circuit comprising: a first transistor, a first source/drain terminal thereof coupled to a first common voltage; a second transistor, a first source/drain terminal thereof coupled to a second source/drain terminal of the first transistor, a second source/drain terminal thereof coupled to a second common voltage, a gate terminal thereof coupled to an output terminal of the amplifying circuit; an level shifter, comprising a first terminal, a second terminal and a third terminal, wherein the first terminal thereof is coupled to the output terminal of the amplifying circuit and receives the output signal, the second terminal is coupled to the second common voltage, the level shifter is used for shifting the DC voltage of the output terminal of the amplifying circuit a preset voltage, and responding the output signal to the third terminal thereof; a frequency compensating circuit, a first terminal thereof coupled to the first source/drain terminal of the second transistor, a second terminal thereof coupled to the gate terminal of the second transistor; a third transistor, a first source/drain terminal thereof coupled to the third terminal of the level shifter, a second source/drain terminal thereof coupled to the first common voltage; and a voltage generator, for outputting a control voltage to a gate terminal of the third transistor to control a voltage of the first source/drain terminal of the third transistor in order to control a current flowing through the first and the second transistors; wherein the voltage generator comprises: a fifth transistor, a first source/drain terminal thereof coupled to the first common voltage, a gate terminal thereof coupled to the gate terminal of the third transistor; a first current source, a first terminal thereof coupled to a second source/drain terminal of the fifth transistor, a second terminal coupled to the second common voltage; and a bias amplifier, a positive terminal thereof receiving a specific gate bias, a negative terminal thereof coupled to the second source/drain terminal of the fifth transistor, an output terminal coupled to the gate terminal of the fifth transistor.