Patent ID: 8513727

Claim:
A nonvolatile memory device having a surrounding stacked gate fin FET, the device comprising: a silicon-on-insulator (SOI) substrate being characterized by a first conductivity type, the substrate including an upper surface; a fin active region projecting from the upper surface of the substrate; a tunnel oxide layer overlying the fin active region; a first gate electrode disposed on the tunnel oxide layer and upper surface of the substrate; a dielectric composite layer formed on the surface of the first gate electrode; a second gate electrode formed on a top surface and side surfaces of the dielectric composite layer and patterned so as to define a stacked gate structure including the second gate electrode, the dielectric composite layer, the first gate electrode, and the tunnel oxide layer; a dielectric spacer formed on sidewalls of the stacked gate electrodes structure; source/drain regions formed in the fin active region on both sides of the second gate electrode; and elevated source/drain regions overlying the respective source/drain regions, wherein the elevated source/drain regions have a top surface that is substantially coplanar with a top surface of the second gate electrode.