Patent ID: 8487662

Claim:
A multiplexer, comprising: an output that provides an output signal; and a plurality of switch circuits that receive a plurality of input signals, each switch circuit comprising: a channel unit, coupled to the output, being conducted during a channel conduction period; a plurality of switches coupled to the channel unit, each switch corresponding and coupled to one of the input signals, the switches respectively being conducted in a plurality of switch conduction periods; a differential output that outputs a differential output signal according to the input signals; a plurality of differential switch circuits, each differential switch circuit comprising: a channel unit, comprising a first channel end being coupled to the differential output and a second channel end, that conducts the first channel end to the second channel end during a channel conduction period; and a predetermined number of switches, each switch corresponding to a respective one of the input signals, each switch comprising two transmission ends respectively coupled to the second channel end and an invert signal associated with the respective input signal, each switch having a switch conduction period during which the switch conducts the two transmission ends; a first complementary driving unit, comprising a controlled end and a channel end respectively coupled to the output and the differential output; and a second complementary driving unit, comprising a controlled end and a channel end respectively coupled to the differential output and the output, wherein, the switch conduction periods and the channel conduction period in each switch circuit are partly overlapped, and the switch conduction periods in each switch circuit are non-overlapped.