Patent ID: 8559462

Claim:
A synchronization signal detection apparatus for a bus signal varying between a first level and a second level, the bus signal including a header field and a synchronization signal field following the header field, the header field having at least M successive bits of the first level, where M is an integer more than the Nth power of 2, where N is a positive integer, the synchronization signal field having alternating bits starting with the second level, the synchronization signal detector comprising: a temporary synchronization signal detector configured to detect the Nth power of 2 successive bits of the first level as a temporary synchronization signal when receiving the Nth power of 2 successive bits of the first level before receiving the alternating bits; and a final synchronization signal detector configured to determine that the detected temporary synchronization signal is the header field when receiving the at least M successive bits of the first level and when detecting that the integer M exceeds the Nth power of 2.