Patent ID: 7678689

Claim:
A method of fabricating a memory device, the method comprising: forming landing plugs between gates on a semiconductor substrate; forming an etch stop layer, a first conductive layer, and a first hard mask layer over the semiconductor substrate; etching the first hard mask layer to form first hard mask patterns; performing a first etch process to form bit lines by etching the first conductive layer and the etch stop layer using the first hard mask patterns as an etch mask; forming a first spacer on sidewalls of the bit line; gap-filling a second conductive layer between the bit lines; forming a first storage node contact (SNC) plug between the bit lines by polishing the second conductive layer until the first hard mask patterns are exposed; performing a second etch process to reduce a height of the first hard mask patterns and the first SNC plug; forming the second hard mask layer over the first hard mask patterns and the first SNC plug; etching the second hard mask layer to form second hard mask patterns on the first hard mask patterns; and forming a second SNC plug between the second hard mask patterns.