Patent ID: 7696963

Claim:
A buffer, comprising: a first capacitor for receiving a gradation voltage through a first terminal; a first inverter having an input terminal connected to a second terminal of the first capacitor; a second capacitor having a first terminal connected to an output terminal of the first inverter; a second inverter having an input terminal connected to a second terminal of the second capacitor; a third capacitor having a first terminal connected to an output terminal of the second inverter and supplying a voltage; a first transistor connected to a second terminal of the third capacitor, and controlling current flowing from a first power source to a data line so as to supply the gradation voltage to the data line in correspondence to the voltage supplied by the third capacitor; a second transistor connected to the first terminal of the first capacitor, and supplying the gradation voltage to the first capacitor in response to a first control signal; a third transistor connected between the first terminal of the first capacitor and a second power source, and controlled by a second control signal; a fourth transistor connected between the second terminal of the third capacitor and the first power source, and controlled by the first control signal; and a fifth transistor connected between the data line and the second power source, and controlled by the first control signal.