Patent ID: 7875561

Claim:
A method, comprising: conformally forming a first stress-inducing layer above a first plurality of transistors formed above a substrate, said first stress-inducing layer generating a first type of stress in a first channel region of at least one of said first plurality of transistors; conformally forming a second stress-inducing dielectric layer above a second plurality of transistors, wherein said second stress-inducing dielectric layer has a greater thickness than said first stress-inducing dielectric layer and induces a different type of stress than said first stress-inducing layer in a second channel region of at least one of said second plurality of transistors; forming a first dielectric layer above said first and second stress-inducing layers, said first dielectric layer having an internal stress level less than a stress level of said first stress-inducing layer; forming a third stress-inducing layer above said first dielectric layer, said third stress-inducing layer inducing said first type of stress in said first channel region; and forming a second dielectric layer above said second stress-inducing layer.