Patent ID: 7183815

Claim:
A driver comprising: a plurality of functional circuits including a first functional circuit having a relatively high frequency of operations and a second functional circuit having a relatively low frequency of operations and connected to the first functional circuit, the first functional circuit including a first buffer circuit having a first CMOS inverter circuit having a first P channel MOS transistor and a first N channel MOS transistor, which are connected in series, and a first timing adjusting circuit, connected to the first CMOS inverter circuit, for supplying first and second switching signals to gates of the first P channel MOS transistor and the first N channel MOS transistor such that in a period during which one of the first P channel and first N channel MOS transistors is turned off, the other one of the first P channel and first N channel MOS transistors is turned on, the second functional circuit including a second buffer circuit having a second CMOS inverter circuit having a second P channel MOS transistor and a second N channel MOS transistor, which are connected in series, and a second timing adjusting circuit, connected to the second CMOS inverter circuit, for receiving an input signal and supplying a third switching signal to the gate of the second P channel MOS transistor such that an ON timing of the second P channel MOS transistor is delayed and an ON duration of the second P channel MOS transistor is shorter than an OFF duration of the second N channel MOS transistor, wherein second timing adjusting circuit supplies a fourth switching signal to the gate of the second N channel MOS transistor such that an ON timing of the second N channel MOS transistor is delayed and an ON duration of the second N channel MOS transistor is shorter than an OFF duration of the second P channel MOS transistor.