Patent ID: 8321636

Claim:
An electronic system comprising: a first memory area coupled for access by a first processor via a first bus, the first bus having a plurality of bus sections separately branching from the first processor, wherein each bus section has a first end connected to the first processor and a second end opposite the first end, wherein the second end of one bus section is connected to the first memory area, and the second end of at least one other bus section bypasses and so is not connected to the first memory area; a second memory area coupled for access by a second processor; a second bus, the second bus having a first portion connected to the second processor for providing access to the second memory area via the second processor and a second portion connected to the second end of the at least one other bus section of the first bus that bypasses the first memory area; at least one memory configuration that supports shared access of the second memory area by the first and second processors, wherein the at least one configuration includes access by the first processor to a first set of memory locations of the second memory area via the second processor and the at least one other bus section of the first bus that bypasses the first memory area, and access by the second processor to a second separate set of memory locations of the second memory area; and at least one other memory configuration that supports direct access of the second memory area by the first processor and not via the second processor.