Patent ID: 8181136

Claim:
A computer-readable, non-transitory storage medium storing a circuit operation verification program for causing a computer to execute a process, comprising: based on logic simulation results for an operation verification target circuit including a control circuit instructing a switching restraining mode to a specific circuit, identifying, from a control signal data storage device storing an ID of a control signal net through which a control signal to instruct said switching restraining mode is transmitted, a signal value of said control signal, by which said switching restraining mode is enabled, and an ID of a switching restrained net, through which a signal directly influenced by enabling said switching restraining mode is transmitted, in association each other, a switching restrained net, for which said signal value of said control signal of said control signal net at a specific time is a signal value by which said switching restraining mode is enabled, and which corresponds to the pertinent control signal net, and setting a switching probability restraint information list including said ID of the identified switching restrained net and said specific time to said identified switching restrained net; identifying, from a propagation condition data storage device storing, for each type of the circuit, a propagation condition by which said switching probability restraint information list set for an input side net of the circuit is propagated to an output side net of the circuit, a propagation condition for a type of a specific circuit whose input side net is a net for which said switching probability restraint information list is set, and judging whether or not said results of logic simulation satisfy the identified propagation condition, and propagating said switching probability restraint information list set for said input side net to said output side net of said specific circuit, upon detecting that said results of said logic simulation satisfy said identified propagation condition; and judging whether or not said specific time included in said switching probability restraint information list propagated to said output side net of said specific circuit is a time prior to a predetermined time or more from a present time, and upon detecting that said specific time is a time prior to said predetermined time or more from said present time, outputting an error.