Patent ID: 7352611

Claim:
A semiconductor integrated circuit comprising: a pair of power source wires; a plurality of static memory cells; a voltage control circuit for controlling an operation voltage applied from said power source wires to said static memory cells; a monitor circuit for monitoring a voltage of said power source wires; and a mode control circuit for controlling a plurality of operation modes, wherein: said mode control circuit controls a low power consumption mode of said semiconductor integrated circuit; said monitor circuit detects a change of decrease of a potential difference between said pair of power source wires; and said voltage control circuit executes control in such a manner as to increase a lower potential among potentials of a pair of power source nodes of said static memory cell in response to indication of the low power consumption mode by said mode control circuit and executes control in such a manner as to decrease the lower potential among potentials of said pair of power source nodes of said static memory cell in response to detection of the rise of the potential of said lower power source wires by said monitor circuit.