Patent ID: 8014211

Claim:
A register file comprising: a plurality of cells each configured to store a bit, wherein the plurality of cells are divided into a plurality of non-overlapping sets of two or more cells; a plurality of local bit lines including a first local bit line, wherein each of the plurality of non-overlapping sets of cells are associated with respective local bit lines of the plurality of local bit lines including a first set of cells associated with the first local bit line; bit line generation circuitry coupled to the first local bit line and to the first set of cells, wherein the bit line generation circuitry is configured to drive the first local bit line responsive to a selected cell for a read of the register file being one of the first set; a first pull-up circuit coupled between the first local bit line and a source voltage line, wherein a gate terminal of the first pull-up circuit is coupled to receive a first group select signal that corresponds to the first local bit line and indicates whether or not the selected cell is in the first set, wherein the first pull-up circuit is configured to pull up the first local bit line toward a source voltage present on the source voltage line during the read of the register file responsive to the first group select signal being de-asserted, indicating that the selected cell is not in the first set; and global bit line generation circuitry coupled to a global bit line and further coupled to receive the first group select signal and the first local bit line, wherein the global bit line generation circuitry is configured to selectively drive a global bit line responsive to the first group select signal and the first local bit line.