Patent ID: 7042771

Claim:
A Random Access Memory (RAM), comprising: (a) at least one memory array comprising plurality of bit line pairs, plurality of word lines and plurality of memory cells for storing and retrieving binary data; (b) a set of bit line sense amplifiers for sensing and enhancing differential signals between bit lines of said bit line pairs; (c) a set of column access devices for coupling said bit line pairs to data lines; (d) a bit line sense amplifier power supply circuit for powering said bit line sense amplifiers; (e) first and second delay circuits for delaying a word line timing pulse by predetermined periods of time, the first and second delay circuits being coupled in series so that the first delay circuit delays the word line timing pulse by a first period of time and the second delay circuit adds to the first delay, thus providing a further delayed version of the word line timing pulse; (f) a first logic circuit for logically combining said word line timing pulse and the delayed version of the word line timing pulse to produce a bit line sense amplifier enable signal, for enabling the bit line sense amplifier power supply circuit; and (g) a second logic circuit far logically combining said word line timing pulse and the further delayed version of the word line timing pulse to produce a column select enable signal.