Patent ID: 7495590

Claim:
A column driver for Liquid Crystal Display (LCD) panel, which drives data lines for pixels of the panel, the column driver comprising: n number of Digital-to-Analog Converters (DAC) which receives digital data for n channels, and converts the digital data into analog signals for n channels; n number of amplifiers which receives the analog signals from the output of the n DAC and amplifies the analog signals for driving the data lines of the pixels; a switch array for switching the output of the n amplifiers either to n data lines or to the an input of the comparator wherein said switch array delivers the output voltages of the amplifiers for each of n channels to each data line of the pixel through switch points T 0 , T 1 , T 2 , . . . , T 15 during the normal operation mode while said switch array delivers the output voltages of the amplifiers for each of n channels to an input terminal of a comparator through selecting switch points S 0 , S 1 , S 2 , . . . , Sn in a successive manner according to a timing clock sequence controlled by a controller during the test mode; the comparator which compares the output voltage of the amplifier via the switch points S 0 , S 1 , S 2 , . . . , Sn with a reference voltage level and outputs a train of either high or low digital level in accordance with the timing clock sequence controlled by the controller during the test mode for the extraction of offset voltage data; a memory which receives a digital signal train from the comparator during the test mode for extracting the offset voltage under the control of the controller, stores the offset voltage data for each of n channels, and provides a subtracting unit with the offset voltage data under the control of the controller during the normal operation mode; the subtracting unit which reads out the offset voltage data for each of n channels stored in the memory, subtracts the read-out offset voltage data from a digital input signal input during the normal operation mode, and feeds the subtraction result to the n DACs; and the controller which scans a reference voltage for the comparator as a plurality of levels for application during the test mode, generates the timing clock sequence for selecting outputs of the n amplifiers, connects the outputs to the comparator, stores the offset voltage data for each of the n channels in the memory, and controls the access to the stored offset voltage data.