Patent ID: 8362818

Claim:
A clock adjustment circuit comprising: a first switching element which is in a conductive state when an in-phase clock signal in a high level is applied to an input terminal; a second switching element whose input terminal is connected to an output terminal of the first switching element, and which becomes in the conductive state when the in-phase clock signal in a low level is applied to an output terminal; a third switching element which is in a conductive state when a reverse-phase clock signal in a high level is applied to an input terminal; a fourth switching element whose input terminal is connected to an output terminal of the third switching element, and which becomes in the conductive state when the reverse-phase clock signal in a low level is applied to an output terminal; a first capacitor element with one terminal connected to an output terminal of the first switching element; a second capacitor element with one terminal connected to an output terminal of the third switching element; and a shift detection unit that detects a potential difference between the output terminal of the first switching element and the output terminal of the third switching element and outputs the detection signal as a signal for adjusting a duty ratio of the clock signal.