Patent ID: 8536029

Claim:
A method of fabricating a complementary metal-oxide semiconductor (CMOS) circuit having a nanowire field-effect transistor (FET) and a finFET, the method comprising: providing a wafer having an active layer over a buried oxide (BOX), wherein the active layer includes at least a first region and a second region; thinning the first region of the active layer, for forming a stepped surface in the active layer defined by the first region and the second region of the active layer; depositing an organic planarizing layer on the active layer that defines a planar surface disposed on the active layer; forming a first lithography hardmask on the organic planarizing layer over portions of the first region of the active layer and a second lithography hardmask on the organic planarizing layer over portions of the second region of the active layer; etching to define nanowires and pads in the first region of the active layer; suspending the nanowires over the BOX layer; etching fins in the second region of the active layer using the second lithography hardmask; forming a first gate stack that surrounds at least a portion of each of the nanowires, wherein the portions of each of the nanowires surrounded by the first gate stack define a channel region of a nanowire FET; forming a second gate stack covering at least a portion of each of the fins, wherein the portions of the fins covered by the second gate stack define a channel region of the finFET; and simultaneously growing an epitaxial material on exposed portions of the nanowires, the pads and the fins, wherein the epitaxial material grown on the exposed portions of the nanowires and the pads define source and drain regions of the nanowire FET and wherein the epitaxial material grown on the exposed portions of the fins defines source and drain regions of the finFET.