Patent ID: 8412889

Claim:
A synchronization method utilizing a lock bit in a computing system which also has a cache, the cache having cache lines, operation of the cache in the computing system being subject to a cache protocol which has at least a shared state and an exclusive state, the method comprising the steps of: acquiring a cache line in the shared state outside an atomic region; comparing a condition to a state specification outside the atomic region, the state specification occupying a different location in the computing system than the lock bit occupies in the computing system, and the state specification capable of identifying at least three states; if match requirements are met in the shared state then entering the atomic region and acquiring the cache line in the exclusive state, comparing the condition to the state specification within the atomic region and if the match requirements are met then setting the lock bit within the atomic region and returning a success indicator, and if the match requirements are not met within the atomic region then exiting the atomic region without setting the lock bit, the match requirements being met when the condition matches the state specification and the lock bit is clear; and if the match requirements are not met in the shared state then returning a failure indicator.