Patent ID: 8319289

Claim:
A power MISFET comprising a semiconductor substrate having at least one main surface, wherein, the main surface of the semiconductor substrate has a source region, a channel region, a drift region, and a drain region arranged thereon in sequence along the main surface of the semiconductor substrate, the drift region includes a trench region which is shallower than the drift region formed therein in a direction from the main surface of the semiconductor substrate to the inside of the semiconductor substrate, an inside of the trench region is filled with a first insulating film, the main surface of the semiconductor substrate has: a gate electrode layer arranged on the channel region interposing a second insulating film; and a dummy gate electrode layer arranged on the drift region and the first insulating film interposing a third insulating film thereon, a plane arrangement of the main surface of the semiconductor substrate is such that: the source region and the drain region are arranged at opposite sides to each other across the gate electrode layer, and the gate electrode layer does not overlap the first insulating film, and the dummy gate electrode layer is arranged separately from the gate electrode layer between the gate electrode layer and the drain region, an edge portion of the dummy gate electrode layer at the drain region side overlaps the first insulating film and an edge portion of the dummy gate electrode layer at the source region side overlaps the drift region, and the dummy gate electrode layer is electrically connected with the source region.