Patent ID: 6937495

Claim:
An integrated circuit comprising: a memory array having memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased; a selection circuit for selecting one of a group of bit lines; a bit line sensing circuit for determining the data state of a selected memory cell on the selected bit line, said sensing circuit comprising: a bias isolation circuit for biasing the selected bit line coupled thereto at a selected bit line bias voltage and for conveying a current on the selected bit line onto a sense node while keeping the selected bit line substantially at the selected bit line bias voltage; a reference current circuit for coupling to the sense node a reference current; and a voltage amplifier circuit responsive to a voltage developed on the sense node by a net difference in current between the selected bit line current and the reference current.