Patent ID: 7474563

Claim:
A flash memory comprising: a plurity of memory elements, each having a control terminal, a program terminal and a threshold voltage; a program unit having an output node, wherein the program unit outputs a program current through the output node, and wherein the node has a node voltage; and a detecting unit, coupled to the program unit and the memory element for detecting the node voltage, and blocking the program current once the node voltage exceeds a reference voltage, wherein the detecting unit comprises: a first NMOS transistor and a second NMOS transistor, the first NMOS transistor and the second NMOS transistor coupled between the second PMOS transistor and the memory element, and the gate of the first NMOS transistor connected to a clamp voltage; and a comparator, a positive input terminal of the comparator coupled to the common node of the first PMOS transistor and the current source, and a negative input terminal of the comparator connected to the common node of the first NMOS transistor and the second PMOS transistor and outputting a control voltage to the gate of the second NMOS transistor.