Patent ID: 7252909

Claim:
A method for reducing Critical Dimension (CD) non-uniformity in creating a patterned layer of semiconductor material, comprising: providing a substrate, said substrate having been provided with one or more layers of semiconductor material; depositing a first masking layer over one or more layers of semiconductor material; creating, while applying methods for compensation of optical proximity effects and micro-loading, a first pattern in said first masking layer, said first pattern being a pattern of high-density semiconductor device features and isolated semiconductor device features and dummy features, said creating while applying methods for compensation of optical proximity effects and micro-loading a first pattern in said first masking layer comprising: first exposing said first masking layer with a first mask, said first mask comprising a first and a second pattern, said first pattern being a pattern of high-density semiconductor device features having a first cross-section, said second pattern being full-size assist features having a second cross-section, said full-size assist features being designed to maximize contribution to spatial frequency and to achieve unification of an exposure level of the high-density device features; second exposing said first masking layer with a second mask, said second mask comprising a third pattern, said third pattern aligning with said second pattern on said first mask; and etching said first masking layer in accordance with said first and second exposure of said masking layers; patterning at least one of said one or more layers of semiconductor material in accordance with said first pattern; removing said first masking layer; depositing a second masking layer over said at least one layer of semiconductor material, including said patterned at least one of said one or more layers of semiconductor material; creating a second pattern in said second masking layer, said second pattern exposing dummy features of said patterned at least one of said one or more layers of semiconductor material; patterning said at least one layer of semiconductor material in accordance with said second pattern; and removing said second masking layer.