Patent ID: 7608511

Claim:
A fabrication method of a trenched power MOSFET comprising steps of: providing a substrate and forming an epitaxial layer thereon; forming a plurality of gate trenches in the epitaxial layer; forming a gate oxide layer on an exposed surface of the epitaxial layer; forming a plurality of polysilicon gates in the gate trenches respectively; implanting dopants with a first conductivity type into the epitaxial layer below the gate oxide layer; driving-in the dopants with the first conductivity type in an oxygen-free environment to form a body below the gate oxide layer; implanting dopants with a second conductivity type into the body below the gate oxide layer; driving-in the dopants with the second conductivity type in an oxygen-free environment to form a plurality of source regions in the body; forming self alignment silicide (salicide) on exposed surfaces of the polysilicon gates by using the gate oxide layer as a mask; depositing a dielectric layer covering the epitaxial layer and the polysilicon gates and forming a contact window to expose the source region and part of the body; and forming a heavily-doped region with the first conductivity type into the body beneath the contact window.