Patent ID: 7335543

Claim:
A method for fabricating a high voltage semiconductor device, the method comprising: providing a substrate having a surface region; forming a well region within the substrate; forming a double diffused drain region within the well region; forming a gate dielectric layer overlying the surface region; forming a gate polysilicon layer overlying the gate dielectric layer; forming a mask layer overlying the gate polysilicon layer; patterning the gate polysilicon layer to form a gate electrode having a first predetermined width and a predetermined thickness, the gate electrode having a first side and a second side formed between the first predetermined width, the gate electrode being coupled to the double diffused drain region within the well region, the first side having a lower corner overlying the gate dielectric layer and an upper corner underlying the mask layer, the second side having a lower corner overlying the gate dielectric layer and an upper corner underlying the mask layer; causing an oxidation of the gate electrode such that the lower corner on the first side and the lower corner on the second side convert from polysilicon material into silicon dioxide while the upper corner on the first side and the upper corner on the second side are substantially free from oxidation; and continuing to convert the lower corner of the first side and the lower corner of the second side to reduce the first predetermined with of the gate electrode comprising polysilicon material to a second predetermined width comprising polysilicon material to increase a breakdown voltage of the high voltage semiconductor device to greater than 20 volts.