Patent ID: 8362803

Claim:
A voltage translator circuit, comprising: an input stage adapted for receiving an input signal referenced to a first voltage supply; a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal; a voltage clamp coupled between the input stage and the first latch circuit, the voltage clamp being operative to set a maximum voltage across the input stage to a prescribed level, the voltage translator circuit generating a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp; and a second latch circuit connected to the first output in a feedback configuration, the second latch circuit being operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply; wherein the voltage clamp is adapted to receive a first bias signal for setting the maximum voltage across the input stage, the first bias signal varying as a function of the first control signal.