Patent ID: 7664213

Claim:
A data communications system comprising: a source clock signal; a first clock domain comprising a first clock signal which is derived from the source clock signal, wherein the first clock signal has a first frequency; and a second clock domain comprising a second clock signal which is derived from the source clock signal, wherein the second clock signal has a second frequency which is different from the first frequency, and wherein both the first frequency and the second frequency are an integer multiple of a frequency of the reference clock signal, and the first frequency is not an integer multiple of the second frequency; wherein the first clock domain includes circuitry which is configured to: generate a reference clock signal derived from the source clock signal; generate the first clock signal; utilize the first clock signal to sample the reference clock signal; assert an aligned signal responsive to detecting an edge of the reference clock signal, wherein the aligned signal indicates an edge of the first clock signal is aligned with an edge of the second clock signal; sample said reference clock signal on each falling edge of the first clock signal; detect a sequence wherein said reference clock signal is low on a first cycle of the first clock signal, and said reference clock signal is high on a cycle of the first clock signal immediately following the first cycle; and assert a pre-aligned signal which indicates a rising edge of the reference clock signal has been detected, responsive to detecting said sequence.