Patent ID: 8514306

Claim:
A correlated double sampling (CDS) circuit comprising: a sampling circuit configured to perform a CDS on a reset signal and an image signal respectively during a CDS phase and configured to output a difference between a correlated double sampled reset signal and a correlated double sampled image signal; a feedback unit configured to feed back the difference output from the sampling circuit to an input of the sampling circuit during a programmable gain amplifier (PGA) phase; and an offset correction circuit configured to correct an offset voltage in the difference between the correlated double sampled reset signal and the correlated double sampled image signal, and cancel an offset voltage of the CDS circuit during the CDS phase using the corrected offset voltage, wherein the sampling circuit is configured to amplify the difference fed back during the PGA phase by N times (N is a natural number) and output a first amplified signal, and the sampling circuit includes, an amplifier including a first input terminal and a second input terminal, and configured to output the difference between the correlated double sampled reset signal and the correlated double sampled image signal as an output signal, a first capacitor connected to the first input terminal of the amplifier through a first node, and a second capacitor connected between an output terminal of the amplifier and a second node, the feedback unit is connected between the output terminal of the amplifier and the first node and is configured to feedback the output signal to the first node, at least one of the first capacitor and the second capacitor are configured to vary the capacitance ratio there between to M (M is a natural number):1 during the CDS phase, and to vary the capacitance ratio of the first capacitor to the second capacitor to M′ (M′ is a natural number):1 during the PGA phase, and the amplifier is configured to amplify the fed-back output signal by (M*M′) times and output a second amplified signal.