Patent ID: 8572153

Claim:
A circuit, having inputs A, B, C, and, D, for multiplying a multiplicand by a multiplier, the circuit comprising: a first circuit portion, comprising: a first multiplexer having a first data input, a second data input, a third data input, a fourth data input, a first select input, a second select input, and a first multiplexer output, wherein A is present on the first data input, A plus a one's complement of B is present on the second data input, the one's complement of B is present on the third data input, and a value zero is present on the fourth data input; and a first adder tree having a first input, a second input, and an output, the first multiplexer output of the first circuit portion being coupled to the first input of the first adder tree, a difference of a product of A times C minus a product of B times D being output onto the output of the first adder tree; and a second circuit portion, comprising: a first multiplexer having a first data input, a second data input, a third data input, a fourth data input, a first select input, a second select input, and a first multiplexer output, wherein B is present on the first data input, B plus A is present on the second data input, A is present on the third data input, and the value zero is present on the fourth data input; and a second adder tree having a first input, a second input, and an output, the first multiplexer output of the second circuit portion being coupled to the first input of the second adder tree, a sum of a product of A times D plus a product of B times C being output onto the output of the second adder tree.