Patent ID: 8223909

Claim:
A polyphase sampling apparatus, comprising: a plurality of sampling circuits configured to sample a periodic digital signal according to a polyphase clock system having multiple phases; and a plurality of logic level change circuits coupled to said plurality of sampling circuits operable to detect logic level changes of the periodic digital signal that occur between phases of said polyphase clock system, wherein a periodic phase difference between a first pair of consecutive phases of the polyphase clock system is different from a periodic phase difference between a second pair of consecutive phases and wherein the time for which a test signal is a ‘1’ or a ‘0’ is greater than the maximum phase delay ΔΦMax among the polyphase clocks, wherein the periodic digital signal is sampled at a rate equal to the inverse of the phase difference between the consecutive sampling clock signals and successively sampling the periodic digital signal is performed using logic circuitry that is clocked at a rate that is less than the rate at which the periodic digital signal is sampled.