Patent ID: 8772051

Claim:
A method of fabricating an embedded memory device comprising: providing a wafer having a memory area and a logic area; providing a topmost metal contact layer on a surface of said wafer and covering said topmost metal contact layer with dielectric and etch stop layers; in said memory area, opening vias through said dielectric and etch stop layers to said topmost metal contact layer and, in said logic area, opening evenly distributed dummy fill patterns through a portion of said dielectric and etch stop layers; filling said vias and dummy fill patterns with a metal layer and planarizing said metal layer thereby forming a flat wafer surface; forming MTJ elements on said flat wafer surface in said memory area and forming dummy MTJ elements on said flat wafer surface in said logic area; thereafter etching away all said dummy MTJ elements, said dummy fill patterns, and surrounding layers in said logic area; and thereafter forming metal connections to said topmost metal contact layer in said logic area and forming top lead connections to said MTJ elements in said memory area.