Patent ID: 7886253

Claim:
A design structure embodied in a computer readable storage medium, which when executed by a computer system, performs an iterative synthesis of an integrated circuit design to attain power closure while maintaining other design criteria, the design structure comprising: program code for performing an initial synthesis of the integrated circuit design to generate a netlist containing a listing of circuits and interconnections that form the integrated circuit design; program code for generating a tag list that specifies a tag for each node in the netlist; program code for identifying a predetermined number of nodes from the netlist that are representative of worst case power consuming nodes; program code for performing a power reduction algorithm on each of the predetermined number of nodes; program code for calculating power of the netlist after each instance that a power reduction algorithm is run on a node selected from the predetermined number of nodes; program code for determining after each instance that a power reduction algorithm is run on a node selected from the predetermined number of nodes whether the netlist satisfies design constraints specified for the integrated circuit design; program code for using the tag list to iterate through the performing of a power reduction algorithm, calculating of power and determining of whether the netlist satisfies specified design constraints for each of the predetermined number of nodes; and program code for generating a final netlist after all of the predetermined number of nodes have been iterated through the performing of a power reduction algorithm, calculating of power and determining of whether the netlist satisfies specified constraints.