Patent ID: 7215315

Claim:
A shift register comprising a plurality of stages, each of the stages comprising one of cascaded shift circuits, each of the shift circuits comprising: an output terminal which sequentially outputs an output signal and which applies the output signal to the shift circuit in a succeeding stage; an input terminal to which the output signal from the shift circuit in a preceding stage is applied; a reset terminal to which the output signal from the shift circuit in the succeeding stage is applied; a first wiring; a second wiring; a section for applying a predetermined voltage to the first wiring in response to the input of the output signal from the shift circuit in the preceding stage to the input terminal and in accordance with the application of the predetermined voltage to the first wiring, outputting an externally applied signal of a predetermined level to the output terminal as the output signal; a section for reducing a voltage level of the first wiring in response to the application of the output signal to the reset terminal by the shift circuit in the succeeding stage; a section for applying the predetermined voltage to the second wiring in response to a change in the level of the voltage applied to the first wiring; a section for applying the predetermined voltage to the second wiring in response to the application of the output signal to the reset terminal by the shift circuit in the succeeding stage; and a section for reducing a voltage level of the output signal in response to the application of the predetermined voltage to the second wiring, wherein the section for outputting the signal of the predetermined level as the output signal has a first transistor which applies the predetermined voltage to the first wiring in response to the input of the output signal to the input terminal, and a second transistor which outputs the signal of the predetermined level to the output terminal wire in response to the application of the predetermined voltage to the first wiring, the section for reducing the voltage level of the first wiring in response to the application of the output signal to the reset terminal has a third transistor, the section for applying the predetermined voltage to the second wiring in accordance with the change in the voltage level of the first wiring has a fourth transistor, the section for applying the predetermined voltage to the second wiring in response to the application of the output signal to the reset terminal has a fifth transistor, and the section for reducing the voltage level of the output signal in response to the application of the predetermined voltage to the second wiring has a sixth transistor.