Patent ID: 7673294

Claim:
A method of operating a very long instruction word data processor by transforming a compiler scheduled irregular software pipelined loop conditioned upon data in a condition register into a modified irregular software pipelined loop to prevent over-execution upon loop exit consisting of the steps of: for each instruction within the irregular software pipelined loop determining all modified registers; determining if an instruction modifying a register can be conditionally executed based upon the condition register; if an instruction modifying a register can be conditionally executed based upon the condition register, replacing the instruction with a instruction performing the same function conditional upon the inverse of the condition register; determining if a register move instruction conditional upon the inverse of the condition register can be inserted into the scheduled software pipelined loop without disturbing the schedule; if a register move instruction conditional upon the inverse of the condition register can be inserted into the scheduled software pipelined loop without disturbing the schedule, inserting a conditional register move instruction from a register modified by a register modifying instruction to an additional previously unused register within the loop into the scheduled software pipelined loop without disturbing the schedule; and controlling operation of the very long instruction word processor using the modified irregular software pipelined loop; and said steps of determining all modified registers, determining if an instruction modifying a register can be conditionally executed based upon the condition register, replacing the instruction, determining if a register move instruction conditional upon the inverse of the condition register can be inserted into the scheduled software pipelined loop without disturbing the schedule and inserting a conditional register move instruction are performed automatically by the compiler.