Patent ID: 7683480

Claim:
An apparatus that includes a wirebond array, the apparatus comprising: a ground plane having a top surface; a semiconductor device over a first portion of the top surface of the ground plane, wherein the semiconductor device includes a series of bond pads; an isolator over a second portion of the top surface of the ground plane, wherein the isolator has a top surface, a face extending perpendicular from the ground plane to the top surface of the isolator, and an edge between the top surface of the isolator and the face; a package lead on the top surface of the isolator; a ground connection region on the top surface of the isolator and extending along the edge, wherein the ground connection region is substantially coplanar with the package lead; a connector that electrically connects the ground connection region and the top surface of the ground plane, wherein the connector includes wrap-around metallization formed on the face of the isolator; a plurality of signal wires; and a plurality of ground wires interdigitated with and substantially parallel to the plurality of signal wires, wherein the plurality of signal wires and the plurality of ground wires have substantially the same loop heights so that the wirebond array operates as an impedance matching element, and wherein signal wires are attached at first ends of the signal wires to the package lead and at second ends of the signal wires to first bond pads of the series of bond pads, and the ground wires are attached at first ends of the ground wires to the ground connection region and at second ends to second bond pads of the series of bond pads, wherein the first bond pads and the second bond pads are different from each other.