Patent ID: 8386905

Claim:
An error correcting method, for a memory chip, wherein the memory chip has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the physical pages belonging to the same physical block are individually written and simultaneously erased, the error correcting method comprising: generating a plurality of error checking and correcting (ECC) codes corresponding to a plurality of data, and sequentially writing the plurality of data and the ECC codes corresponding to the plurality of data into the physical pages of a first physical block among the physical blocks; generating a first parity information according to the plurality of data; writing the first parity information into one of the physical pages of the first physical block following the plurality of data; correcting the plurality of data by using the ECC codes corresponding to the plurality of data; and correcting one of the plurality of data in the first physical block according to the first parity information when the one of the plurality of data cannot be corrected by using the ECC codes corresponding to the one of the plurality of data.