Patent ID: 8325127

Claim:
A shift register, comprising a plurality of shift register stages, {S n }, n=1, 2, . . . , N, N being a positive integer, electrically coupled to each other in series, each stage S n comprising: (a) a stage shift circuit having a first input for receiving a first control signal, HC n , and an output for outputting an output signal responsively; and (b) a de-multiplexing circuit comprising a first switch circuit and a second switch circuit, wherein the first switch circuit has a first input for receiving a first clock signal CK 1 , a second input electrically coupled to the output of the stage shift circuit, and an output for outputting a first scanning signal, G( 2 n −1), responsively, and wherein the second switch circuit has a first input for receiving a second clock signal CK 2 , a second input electrically coupled to the output of the stage shift circuit, and an output for outputting a second scanning signal, G( 2 n ), responsively, wherein each of the first control signal HC n , the first clock signal CK 1 and the second clock signal CK 2 is characterized with a waveform alternating between a high voltage level and a low voltage level, wherein the high voltage levels of the first control signal HC n , the first clock signal CK 1 and the second clock signal CK 2 have widths, W H , W 1 and W 2 , respectively, satisfying the following relationship of: W H ≧W 1 +W 2 .