Patent ID: 7849235

Claim:
A direct memory access controller in a first node in an information processing system, comprising a data transfer control unit configured to judge whether or not a first message is in need of a completion response from a second node in the information processing system using a response timing flag indicating end interrupt timing in a descriptor, when receiving a request to transmit the first message to the second node from firmware of the first node, to transmit the first message to another direct memory access controller that is included in the second node by way of a bus, to notify the firmware of a completion of transmission of the first message before the direct memory access controller receives the completion response from the second node if the data transfer control unit judges that the first message is not in need of the completion response, and to notify the firmware of the completion of transmission of the first message after the direct memory access controller receives the completion response from the second node if the data transfer control unit judges that the first message is in need of the completion response.