Patent ID: 7730117

Claim:
A system configured to perform floating point arithmetic operations in a pipelined floating-point unit comprising multiple stages, the system comprising: an input register configured to receive an operand; arithmetic operation circuitry configured to perform an arithmetic operation upon the operand; a normalizer configured to provide feedback of an intermediate result of the arithmetic operation circuitry to the input register as a modified operand prior to completion of rounding and normalization in a final stage of the pipelined floating-point unit, and further configured to provide a normalizing indicator to a rounding correction block; the rounding correction block of the pipelined floating-point unit configured to perform a method comprising: performing a masking or shift operation on the modified operand in response to determining that the modified operand is in an un-normalized format to make the modified operand equivalent to a normalized truncated operand; and determining a rounding correction value as a function of a target precision and the normalizing indicator; and the pipelined floating-point unit configured to perform a method comprising: performing single precision incrementing of the modified operand in response to the rounding correction value indicating single precision and the rounding circuitry indicating the incrementing based on a result of a previous arithmetic operation; and performing double precision incrementing of the modified operand in response to the rounding correction value indicating double precision and the rounding circuitry indicating the incrementing based on the result of the previous arithmetic operation, thereby enabling the arithmetic operation to start at least one cycle before the previous arithmetic operation completes a final stage of the pipelined floating-point unit.