Patent ID: 7561653

Claim:
A method for synchronizing signals generated and used in different clock domains in a system comprising a Phase-Locked Loop (PLL) clock signal supplied to a Voltage Controlled Delay Loop (VCDL), the VCDL employing a multiphase clock, the Phase-Locked Loop (PLL) clock signal having a rising edge and a falling edge, said method comprising the steps of: adjusting the phases of the multiphase clock, said adjusting comprising controlling a current phase delay by determining an injection point location; determining a recovered clock from one of said adjusted phases of the multiphase clock; providing a phase control signal to the VCDL, the phase control signal being transmitted in phase with the recovered clock and comprising phase control data; and, determining, as a function of the injection point location, which of said rising and falling edges of the PLL clock signal to use to synchronize the phase control signal relative to the PLL clock.