Patent ID: 7215146

Claim:
An apparatus comprising: a comparator having a pair of cross coupled PFETs with sources coupled to an I/O power supply, and a differential pair of (NFETs) with sources coupled to ground and gates respectively coupled to a data input and an inverted data input, wherein the cross coupled PFETs and the differential pair of NFETs to level translate low swing logic levels at the data input to high swing logic levels on a node between the pair of cross coupled PFETs and the differential pair of NFETs; first and second pull-up PFETs with sources coupled to a pull-up voltage supply and drains respectively coupled between the differential pair of NFETs and the pair of cross coupled PFETs, the first and second pull-up PFETs to speed the level translation on the node in response to the data input and the inverted data input; and a buffer having an input coupled to the drain of one of the pair of cross coupled PFETs and a buffered output, the buffer to buffer a load on the buffered output from the input, wherein the buffer includes: a first PFET with a source coupled to the I/O power supply and a gate coupled to the drain of one of the pair of cross coupled PFETs; a first cascode PFET with a source coupled to the drain of the first PFET and a gate coupled to the first bias voltage; a first cascode NFET with a drain coupled to the drain of the first cascode PFET and a gate coupled to the second bias voltage; a first pull-down NFET with a drain coupled to the source of the first cascode NFET, a source coupled to ground, and a gate coupled to the drain of one of the differential pair of NFETs; and a third pull-up PFET with a drain coupled to the drain of the first pull-down NFET, a source coupled to the pull-up voltage supply, and a gate coupled to the drain of the one of the differential pair of NFETs.