Patent ID: 6879527

Claim:
A semiconductor memory device in which a plurality of memory cells are arranged in the form of a matrix in row and column directions, the semiconductor memory device comprising: a plurality of memory array blocks each including set numbers of memory cells, the memory array blocks being arranged in the row direction; a Row Address Strobe (RAS) chain aligned at a first side of the plurality of memory array blocks in the row direction, the RAS chain selecting and activating a particular word line; a Column Address Strobe (CAS) chain aligned at a second side of the plurality of memory array blocks in the column direction, the CAS chain amplifying N bits of data from each of the plurality of memory array blocks and outputting the amplified N bits from each of the memory array blocks to a corresponding input/output (IO) line, wherein N is a natural number more than 2; and a data converter for which sequentially outputs the amplified N bits of data from each of the memory array blocks, beginning with the amplified N bits of data from a memory array block nearest to the RAS chain and subsequently outputting the amplified N bits of data from a memory array block farthest from the RAS chain.