Patent ID: 8183600

Claim:
A semiconductor integrated circuit device comprising: a first tap for the supply of a first potential, the first tap being formed in a first direction; a second tap for the supply of a second potential, the second tap being formed in the first direction and positioned so as to confront the first tap in a second direction intersecting the first direction; a cell array comprising a plurality of standard cells each formed between the center of the first tap in the second direction and the center of the second tap in the second direction; and a plurality of layers of wiring lines formed over the first tap, the second tap and the cell array, wherein a cell height between the first and second taps is set to a value equal to the product of an integer representing a number of wiring lines in the first direction and increased by 0.5, and a wiring pitch of second-layer wiring lines of the plurality of layers of wiring lines.