Patent ID: 8716781

Claim:
A non-volatile memory (NVM) cell, comprising: a substrate ( 16 ); a select gate over the substrate ( 16 ) having a planarized to surface; a control gate ( 32 ) over the substrate and laterally adjacent the select gate, wherein the control gate has a planarized to surface; a nanocrystal stack ( 20 ) between the control gate and the substrate, wherein the nanocrystal stack comprises a bottom dielectric, a plurality of nanocrystals on the bottom dielectric, and a top dielectric on and around the plurality of nanocrystals; a high-k gate dielectric ( 34 ) between the select gate and the substrate and along a first sidewall of the select gate, between the first sidewall of the select gate and a first sidewall of the control gate, wherein: the select gate comprises a barrier metal layer ( 35 ) which is in physical contact with the high-k gate dielectric between the select gate and the substrate and between the first sidewall of the select gate and the first sidewall of the control gate; a first source/drain region ( 44 ) in the substrate, laterally adjacent a second sidewall of the select gate, opposite the first sidewall of the select gate; a second source/drain region ( 46 ) in the substrate, laterally adjacent a second sidewall of the control gate, opposite the first sidewall of the control gate, wherein the select gate and the control gate are between the first and second source/drain regions; and a logic gate over the substrate having a planarized to surface that is coplanar with the planarized top surface of the control gate and the planarized top surface of the select gate.