Patent ID: 7459749

Claim:
A semiconductor device, comprising: a channel region formed in a surface of a semiconductor substrate in a first depth range, a trench being formed in the surface as penetrating the channel region in a depthwise direction; a drain region, formed in the semiconductor substrate in a third depth range, at a greater depth than the channel region; a source region formed in the semiconductor substrate in a second depth range, on a side of the channel region opposed to the drain region in the depthwise direction; a gate insulating film formed on an inside wall of the trench, the gate insulating film being in contact with the channel region; a gate electrode including: a polysilicon layer opposing the channel region with the gate insulating film interposed therebetween, the polysilicon layer being embedded in an internal space of the trench at least in the first depth range; a low-resistance layer essentially formed from a metal element and disposed in the trench, above the polysilicon layer that opposes the channel region, and entirely located above the first depth range; a barrier metal layer entirely located above the first depth range and interposed between the polysilicon layer and the low-resistance layer such that the metal atoms diffusion from the low-resistance layer into the polysilicon layer is retarded; and an insulating layer disposed on the low-resistance layer and having a top surface positioned within the trench, wherein: in a surface of the low-resistance layer, a region opposing the polysilicon layer is entirely located at a smaller depth with respect to the depthwise direction of the trench than the first depth range.