Patent ID: 7050781

Claim:
An apparatus, comprising: a filter comprising a first stage and a second stage, the first stage having a differential output and the second stage having a differential input; an adjustable value capacitor coupled in parallel between the differential output of the first stage of the filter and the differential input of the second stage of the filter; and a calibration circuit coupled to the adjustable value capacitor, the calibration circuit being driven by a calibration clock signal and including a comparator and a state machine, wherein the state machine is configured to cause a capacitance value of the adjustable value capacitor to decrease from a higher capacitance value to a lower capacitance based on an input value represented by a number of input binary bits, wherein the calibration circuit is configured to terminate a calibration operation after a number of clock cycles, wherein the number of clock cycles is at most equal to two to the power of the number of the input binary bits, and wherein the calibration circuit adjusts a cutoff frequency of the filter when the filter is powered on by adjusting the capacitance value of the adjustable value capacitor until the cutoff frequency of the filter is within a predetermined range of a target cutoff frequency.