Patent ID: 6982585

Claim:
A pulse shaping system, comprising: a read only memory that stores a set of parallel data; a register that loads the set of parallel data; a clock generator that outputs a clock signal; a clock signal delaying unit comprising a plurality of cascaded delay circuit units, each including an input terminal connected to a plurality of cascaded signal delay devices to obtain delayed pulses at a plurality of delayed times by delaying leading and trailing edges of an input signal to the input terminal; a delayed pulse gate that passes the delayed pulse selected by the set of parallel data which indicates a specific delayed pulse used during operation of the pulse shaping system from among said delayed pulses at said plurality of delayed times, and the delayed pulse gate outputs the delayed pulse from an output terminal, wherein said plurality of the cascaded delay circuit units are cascaded by connecting the output terminal of the delayed pulse gate of one of the cascaded delay circuit units with the input terminal of the clock signal delaying unit of the other of the cascaded delay circuit unit, and the clock signal is input to the input terminal of the clock signal delaying unit of the cascaded delay unit which lies firstly in the cascade comprising of the plurality of the cascaded delay circuits.