Patent ID: 8006016

Claim:
A method for addressing system latency within a network system, comprising: providing a same network interface unit, the same network interface unit including a plurality of direct memory access (DMA) channels, wherein each of the DMA channels is configured to transfer data between the same network interface unit and a main system memory through a same interconnect that is coupled to the main system memory and a plurality of processing entities, wherein the same network interface unit is distinct from the main system memory, the same interconnect and the plurality of processing entities; and moving data within each of the plurality of direct memory access channels independently and in parallel to and from the main system memory though the same interconnect such that one or more of the plurality of direct memory access channels operate efficiently in the presence of memory latencies across multiple requests, wherein the data is moved within each of the plurality of DMA channels independent and parallel with respect to each of the other ones of the plurality of DMA channels.