Patent ID: 7328416

Claim:
A method for modeling timing characteristics of a circuit block of a design for an integrated circuit, the circuit block having a main circuit and a timing circuit, the method comprising: determining an output delay, the output delay being an interval of time from a clock signal reaching a clock reference point (CRP) to an output signal arriving at an output pin of the main circuit, the CRP being positioned between the timing circuit and the main circuit; determining a timing circuit delay, the timing circuit delay being an interval of time from a clock signal arriving at a clock input pin to a clock signal arriving at the CRP, the clock input pin being an input pin to the timing circuit, and the determining of the timing circuit delay being based on a computer simulation of a netlist of circuit elements in the timing circuit; and identifying whether there are any critical paths by separately modeling the timing circuit and the main circuit, and improving the design when the critical paths are identified.