Patent ID: 7173293

Claim:
A transistor device comprising: a series of layers formed on a substrate, said layers including a first plurality of layers comprising n-type dopant material, a second plurality of layers formed above said first plurality of layers and including a p-type modulation doped quantum well structure that defines a channel region, and a third plurality of layers formed above said second plurality of layers and comprising n-type dopant material, wherein said first plurality of layers includes an n-type ohmic contact layer; a collector terminal metal layer that is formed above said third plurality layers, said collector terminal metal layer having a first side opposite a second side; a plurality of p-type ion implant regions that are disposed on said first and second sides of said collector terminal metal layer, said p-type ion implant regions operably coupled to said channel region defined by said p-type modulation doped quantum well structure; a patterned base terminal metal layer that is formed on said said p-type ion implant regions for contact to said channel region defined by said p-type modulation doped quantum well structure; and a patterned emitter terminal metal layer that is formed on said n-type ohmic contact layer on said first and second sides of said collector terminal metal layer; wherein said patterned base terminal metal layer is interdigitated with respect to said patterned emitter terminal layer on both said first and second sides of said collector terminal metal layer.