Patent ID: 7243212

Claim:
A processor-controller interface for non-lock-step operation, comprising: a processor, the processor configured to provide an instruction; and a controller coupled to the processor to receive the instruction, the controller configured to provide a busy signal to indicate to the processor that the controller is not ready to process the instruction, the controller configured to initiate processing of the instruction while maintaining the busy signal at a first logic state indicating that the controller is not ready to processing the instruction; the controller configured to hold the busy signal at the first logic state until a sufficient amount of the instruction has been executed by the controller for an appearance of lock-step operation between the processor and the controller though the controller operates at a lower frequency than the processor; the controller configured to transition the busy signal to a second logic state for time remaining to complete execution of the instruction by the controller; wherein the processor does not have to be slowed or stalled for operation of circuitry instantiated in programmable logic which is capable of performing at least one function responsive to the instruction, the circuitry being coupled to the processor via the controller.