Patent ID: 8420524

Claim:
A method of forming a void boundary structure, comprising: forming a molding layer including a pair of holes on a semiconductor substrate, wherein the pair of holes includes plug and line molding parts which are sequentially stacked and have different diameters; forming interconnections filling the holes; removing the molding layer between the interconnections by, forming a mask layer on the interconnections and the molding layer, the mask layer having an alignment hole exposing the molding layer between the interconnections, etching the molding layer through the alignment hole using the mask layer as an etch mask, and removing the mask layer from the interconnections and the molding layer, the mask layer being formed of an insulating layer having a different etch rate from the molding layer; and forming a void boundary layer which covers the molding layer and the interconnections, and defines a void between the interconnections including, forming a sealed layer on the molding layer and the interconnections, the sealed layer covering a sidewall of one interconnection, extending to a neighboring interconnection facing the one interconnection and covering a sidewall of the neighboring interconnection in order to open a space between the interconnections, and forming a buried layer on the sealed layer to close the space between the interconnections.