Patent ID: 8191035

Claim:
A method for providing a digital circuit design of a programmable chip system, comprising: generating a connection panel by using a processor, the connection panel including a plurality of looped interconnects displayed in a plurality of columns, wherein each column of the plurality of columns is allocated to a particular master component, wherein the plurality of looped interconnects includes a first looped interconnect and a second looped interconnect, wherein the plurality of looped interconnects includes adjustable information identifying relationship states between a first master component, a first slave component, and a second slave component, wherein the relationship states include a connected state, a connectable state, and an open state, wherein the connected state indicates that the first master component is coupled to the first slave component, the connectable state indicates a possibility of coupling the first master component to the first slave component, and the open state indicates a decoupling between the first master and first slave component; displaying a first subset of the plurality of looped interconnects, wherein the first subset of the plurality of looped interconnects includes a plurality of lines coupling a port of the first master component to a port of the first slave component, wherein a vertical portion of the first looped interconnect is located in a first column of the plurality of columns of the connection panel allocated to the first master component, wherein the vertical portion of the first looped interconnect in the first column of the plurality of columns allocated to the first master component overlaps with a vertical portion of the second looped interconnect, wherein the second looped interconnect is configurable to couple the first master component to the second slave component, and displaying a second subset of the plurality of looped interconnects, wherein the second subset of the plurality of looped interconnects includes a plurality of lines coupling a port of a second master component to a port of at least one of the first, the second, or a third slave component, wherein a vertical portion of the first looped interconnect is located in a second column of the plurality of columns of the connection panel allocated to the second master component.