Patent ID: 8531963

Claim:
A semiconductor integrated circuit comprising: a plurality of cores; and an interconnecting network including adaptors connected to each of said cores and a plurality of routers connecting said adaptors to communicate therebetween; wherein said adaptors include: a transmission side adaptor connected to a first core of said plurality of cores, storing first delivery information in which information of a reception side adaptor, which permits said transmission side adaptor to transfer a request signal from said first core, is registered, and transferring said request signal to be received from said first core to said reception side adaptor, which is registered in said first delivery information, through said interconnecting network in accordance with said first delivery information; and the reception side adaptor connected to a second core of said plurality of cores, storing second delivery information in which information of the transmission side adaptor, which is permitted to transfer said request signal to said reception side adaptor, and information of address range in said second core, that an access is permitted, is registered, and said reception side adaptor determining whether or not to receive said request signal to be received through said interconnecting network and whether or not to access to said second core, in accordance with said second delivery information, and wherein information for filter control with respect to address range in said second core that said first core is permitted to access, is divided into said first delivery information and said second delivery information hierarchically set up in accordance with said first delivery information, information of the reception side adaptor, which permits said transmission side adaptor to transfer said request signal from said first core, is registered in said first delivery, and information of the transmission side adaptor, which is permitted to transfer said request signal to said reception side adaptor, and information of address range in said second core, that the access is permitted, is registered in said second delivery information.