Patent ID: 7915108

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a device isolation structure filled with oxide-based material in a substrate to form active regions; forming a hard mask layer patterned over the substrate having the device isolation structure to expose a first region defining an active region pattern in the active region and a second region in the device isolation structure to be adjacent to the active region pattern and to cover portions of the device isolation structure disposed between the neighboring active regions and between the second region, where in the first region, the second region and the portions of the device isolation structure are aligned in a line shape, and the hard mask layer covers the substrate except for the first region, the second region and the portions of devices isolation structure; the hard mask layer further comprising: forming a first mask layer patterned over the substrate having the device isolation structure to expose the first region; forming a second mask layer over the first mask layer; forming a third mask pattern, having straight lines with a space separating each of the straight lines, over the second mask layer; forming a fourth mask pattern, covering an area over the device isolation structure and between neighboring active regions, over the third mask pattern; and recessing exposed portions of the first and second mask layers using the fourth mask pattern and third mask pattern as etching barriers to expose portions of the oxide-based material; recessing the exposed portions of the oxide based material using the first mask layer as etch barrier to form an active region pattern in the active region; removing the first mask layer; forming a gate insulation layer over the substrate to cover at least the active region pattern; and forming a gate electrode over the gate insulation layer to cover at least the active region pattern.