Patent ID: 7422951

Claim:
A method of fabricating a self-aligned bipolar transistor, comprising the steps of: forming at least one trench in a portion of a first conductive type substrate; filling the at least one trench with an isolating material to form a device isolation layer; forming a second conductive type well in the substrate isolated by the device isolation layer, the second conductive type being different from the first conductive type; forming a polysilicon gate on the substrate; forming an insulating layer on the substrate; forming a sidewall spacer on lateral sides of the polysilicon gate by etching the insulating layer; forming a P + ion implanted region in a first portion of the second conductive type well; forming an N + ion implanted region in a second portion of the second conductive type well, the second portion being separated from the first portion; and forming a silicide layer in contact with the P + and N + ion implanted regions.