Patent ID: 7307469

Claim:
A step-down power supply for lowering an external power supply voltage with respect to a ground voltage to generate an internal power supply voltage equal to a referenced voltage and providing the internal power supply voltage to a load, then step-down power supply receiving a load activation signal indicating activation of the load, the step-down power supply comprising: an internal power supply node through which the internal power supply voltage is provided to the load; a control mode a differential amplifier having an output terminal connected to the control node, for comparing the internal power supply voltage with the reference voltage and adjusting a voltage of the control node with the internal power supply voltage differs from the reference voltage; a driving having an input terminal receiving the external power supply voltage, a control terminal connected to the control node, and an output terminal connected to the internal power supply node, for supplying power to the internal power supply node at a voltage lower than the external power supply voltage by an amount responsive to the voltage of the control node; a pull-down circuit for supplying the ground voltage to the control node for a first predetermined time in response to the load activation signal; and a pull-up circuit for supplying the external power supply voltage to the control node for a second predetermined time following the first predetermined time wherein the pull-up circuit comprises: a pulse signal generator receiving the load activation signal and generating a pulse signal when the load activation signal is asserted; a logic gate having an output terminal, an input terminal receiving the load activation signal, and another input terminal receiving the pulse signal output by the pulse signal generator; and a transistor having a current-conducting terminal receiving the external power supply voltage, another current-conducting terminal connected to the control node, and a control terminal connected to the output terminal of the logic gate.