Patent ID: 7467285

Claim:
A method, comprising: invoking, by a first processor executing a first operating system and an application, a second processor, executing a second operating system, to create a shadow page table used for address translation for the application, wherein the shadow page table is implemented in a sequestered memory region non-alterable by processes controlled by the first operating system and accessible to processes executed by the second operating system, wherein the shadow page table provides address translation from virtual to physical addresses in memory pages accessible to the first operating system used by the application; validating, by the second processor, the application to determine whether the application is acceptable in response to being invoked to create the shadow page table; and creating, by the second processor, the requested shadow page table in the sequestered memory region for address translation for the memory pages accessible to the application and the first operating system in response to determining that the application is acceptable, wherein the first processor accesses the shadow page table in the sequestered memory region to perform address translation.