Patent ID: 8124971

Claim:
A memory cell, comprising: a first conductor in a trench in a first dielectric, the first dielectric over and interfacing with a semiconductor substrate, the trench in the first dielectric not formed all the way through to the semiconductor substrate such that a portion of the first dielectric remains between the first conductor and the substrate; a second conductor in a trench in a second dielectric; and a non-silicided pillar coupling the first and second conductors, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell, the pillar comprising: a non-silicided semiconductor over the first conductor; and a non-silicided antifuse over the semiconductor, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell, a top surface of the antifuse that faces the second conductor not extending above a bottom surface of the second dielectric such that a bottom surface of the second conductor that faces the pillar is substantially uniform in the trench in the second dielectric, at least one of a portion of the trench in the first dielectric layer and a portion of the trench in the second dielectric layer not occupied by the first conductor and the second conductor, respectively, filled with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier but not the first conductor or the second conductor.