Patent ID: 8873275

Claim:
A semiconductor storage device, comprising: a plurality of memory cells that each comprise a variable resistance element; a plurality of first wires and a plurality of second wires, wherein each memory cell is disposed between and electrically coupled to one of the plurality of first wires and one of the plurality of second wires; and a control circuit that is configured to: apply a set voltage (V s ) having a first polarity for a set voltage application time (T s ) to a first memory cell during a set operation in which the variable resistance element is changed to a set state having a first threshold voltage in the first polarity; apply a reset voltage having a second polarity being opposite to the first polarity to the first memory cell during a reset operation in which the variable resistance element is changed to a reset state having a second threshold voltage larger than the first threshold voltage in the first polarity; and apply a cancel voltage (V cancel ) having the first polarity for a cancel voltage application time (T cancel ) to a second memory cell in the reset operation, wherein the second memory cell is applied a certain voltage when the reset voltage is applied to the first memory cell, the absolute value of the certain voltage is less than the absolute value of the reset voltage, wherein the relationship between the set voltage (V s ), the set voltage application time (T s ), the cancel voltage (V cancel ) and the cancel voltage application time (T cancel ) satisfies, - Vs ln ⁡ ( Ts A ) > - 2 ⁢ Vcancel ln ⁡ ( Tcancel A ) , wherein A is a constant.