Patent ID: 7574642

Claim:
A method for efficient multipurpose use of built-in self test (BIST) test latches in testing arrays of a processor, comprising: configuring a first plurality of latches to operate as array built-in self test (ABIST) shadow latches to test the arrays; reconfiguring the first plurality of latches to operate as logic built-in self test (LBIST) observation latches to test the arrays; and wherein the step of configuring further comprises: serially loading a first data set into a plurality of data latches coupled in parallel to the first plurality of latches; wherein the plurality of data latches and the first plurality of latches are further coupled to form a scan chain of altemating latches from the plurality of data latches and the first plurality of latches; serially loading a second data set into the first plurality of latches operating as ABIST shadow latches; and performing back-to-back operations corresponding to the first and second data set, wherein the first plurality of latches shadows the plurality of data latches.