Patent ID: 8643817

Claim:
A display panel comprising: a first substrate comprising a plurality of pixels each including a single liquid crystal capacitor all electrodes of which are disposed entirely within the first substrate; a second substrate facing the first substrate; a liquid crystal layer disposed between the first and second substrates; a plurality of first switching devices configured to connect two first signal lines adjacent to each other, respectively, in a direction in which a data line is extended; and a plurality of second switching devices configured to connect two second signal lines adjacent to each other, respectively, in the direction in which the data line is extended, wherein each of the plurality of pixels comprises: the data line; a gate line insulated from the data line over a region in which the gate line crosses the data line; a first signal line crossing the data line at a first side of the pixel, the first signal line insulated from the data line over a region in which the first signal line crosses the data line, the first signal line spaced apart from the gate line; a second signal line crossing the data line at a second side of the pixel, opposite to the first side of the pixel, the second signal line insulated from the data line over a region in which the second signal line crosses the data line, the second signal line spaced apart from the gate line and the first signal line; a switching device connected to the data line and the gate line; a first pixel electrode connected to the switching device; and a second pixel electrode connected to either the first signal line or the second signal line but not to both, wherein an image is displayed by the liquid crystal layer according to an electric field generated between the first and second pixel electrodes, wherein pixels of the plurality of pixels having the first pixel electrode connected to the first signal line are alternately arranged with pixels of the plurality of pixels having the second pixel electrode connected to the second signal line, wherein the pixels having the first pixel electrode and the pixels having the second pixel electrode are disposed in a same row, and wherein each of the first and second switching devices receives a gate-off voltage which turns off the first switching device from a period of time beginning before a gate-on voltage is input to two gate lines corresponding to the two first signal lines and ending after a gate-off voltage is input to the two gate lines corresponding to the two first signal lines.