Patent ID: 6967875

Claim:
A static random access memory system, the static random access memory system comprising: a memory cell region, said memory cell region is individually coupled with a first bitline and a second bitline; a first sub-circuit, said first sub-circuit is individually coupled with said first bitline and said second bitline; and a second sub-circuit, said second sub-circuit is individually coupled with said first bitline and said second bitline between said memory cell region and said first sub-circuit, wherein said first sub-circuit and said second sub-circuit individually and simultaneously communicate a first complemental signal and a second complemental signal to perform an interaction so as to attain and maintain a voltage for operating said memory cell region, and said second sub-circuit comprises a first symmetric sub-circuit and a second symmetric sub-circuit; wherein said first symmetric sub-circuit is coupled with said first bitline between said memory cell region and said first sub-circuit; and said second symmetric sub-circuit is coupled with said second bitline between said memory cell region and said first sub-circuit, wherein said second symmetric sub-circuit and said first symmetric sub-circuit are cross-coupled from each other, whereby said second sub-circuit can detect the differential voltage level between said first bitline and said second bitline by itself so as to compensate to said voltage immediately.