Patent ID: 8169012

Claim:
A semiconductor device comprising: a substrate on which a cell region and a peripheral circuit region are demarcated; a plurality of capacitors disposed in the cell region, the capacitors including lower electrodes, a dielectric layer on the lower electrodes, and an upper electrode on the dielectric layer; and a plurality of supports each engaged with and supporting a respective group of the lower electrodes, wherein the supports comprise at least one first stripe-shaped support disposed at a level spaced a first distance from the substrate, each first stripe-shaped support extending longitudinally in a first direction, and at least one second stripe-shaped support disposed at a level spaced a second distance, different from the first distance, from the substrate, each second stripe-shaped support extending longitudinally in the first direction, whereby each stripe-shaped support disposed at one of the levels in the device is spaced from the respective group of lower electrodes which are engaged and supported by each stripe-shaped support disposed at another of the levels in the device, wherein the lower electrodes are arrayed in a plurality of rows each extending in the first direction, and each of the stripe-shaped supports engages and supports a plurality of adjacent ones of the rows of the lower electrodes, and wherein the lower electrodes in each of the rows are not aligned, in the second direction, from the lower electrodes in the row adjacent thereto, whereby the lower electrodes of the plurality of adjacent rows supported by each respective one of the supports are arrayed in a zigzag pattern along the first direction.