Patent ID: 7142024

Claim:
A power on reset circuit, comprising: a first pulse generation circuit including a first input node, a first static current control feedback node and a first output node from which a first pulse signal is generated; a second pulse generation circuit including a second input node, a second static current control feedback node and a second output node from which a second pulse signal is generated; a static current control transistor switch including a source-drain circuit and a gate, the gate connected to only one of the first or second static current control feedback nodes of the first/second pulse generation circuits; and a resistive divider circuit including a plurality of resistors connected in series with each other at a plurality of taps, the resistive divider circuit connected in series with the source-drain circuit of the static current control transistor, and a first one of the taps connected to the first input node of the first pulse generation circuit and a second one of the taps connected to the second input node of the second pulse generation circuit.