Patent ID: 6927460

Claim:
An isolated NMOS transistor made on a die containing conventional bipolar transistors wherein the conventional bipolar transistors define an N+ type buried layer, the isolated NMOS transistor comprising: a P-type well, means for making an electrical contact to the P-type well, the contact defining a gate of the isolated NMOS transistor, two separate N-type areas formed in the P-type well, one N-type area forming the source and the other forming the drain of the isolated NMOS transistor, the N+ type buried layer, common to the conventional bipolar transistors, underlying the P-type well, a P+ buried layer on top of the N+ type buried layer, and N-type areas connecting the N+ type buried layer wherein the combination of the N-type areas and the N+ type buried layer completely surround the P-type well from the substrate of the die.