Patent ID: 7696779

Claim:
A system LSI, comprising an input/output section and a logic circuit section, wherein the input/output section includes: an I/O power source cell having a power supply voltage higher than a power source for the logic circuit section; and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell, and the logic circuit section includes: a first I/O power consuming circuit which uses the I/O power source cell as a power source, the first I/O power consuming circuit being connected to a first line leading from the I/O power source line in at least one of the plurality of I/O cells, wherein the plurality of I/O cells includes first and second I/O cells each of which has a pad connected to an external terminal, said system LSI further comprising: a filler cell which is provided between the first I/O cell and the second I/O cell and in which the I/O power source line is provided, wherein the first I/O power consuming circuit is provided in a layer below the filler cell, and the first I/O power consuming circuit is connected to the I/O power source line in the filler cell.