Patent ID: 8390341

Claim:
A bridge output circuit configured to output, via an output terminal, an output signal having a voltage level that corresponds to a control signal, the bridge output circuit comprising: a high-side transistor arranged between a first fixed voltage terminal and the output terminal; a low-side transistor arranged between the output terminal and a second fixed voltage terminal; a low-side off-detection circuit configured to compare a gate signal of the low-side transistor with a predetermined first level so as to detect whether or not the low-side transistor is off, and to generate a low-side off-detection signal which is asserted when it is detected that the low-side transistor is off; a high-side off-detection circuit configured to compare a gate signal of the high-side transistor with a predetermined second level so as to detect whether or not the high-side transistor is off, and to generate a high-side off-detection signal which is asserted when it is detected that the high-side transistor is off; a high-side driver configured to generate the gate signal for the high-side transistor according to the control signal and the low-side off-detection signal; a low-side driver configured to generate the gate signal for the low-side transistor according to the control signal and the high-side off-detection signal, and wherein the low-side off-detection circuit comprises a low-side detection transistor that is of the same type as the low-side transistor, a first terminal of which is connected to the second fixed voltage terminal, and which is configured to receive, via a gate thereof, the gate signal of the low-side transistor, a first resistor arranged between a second terminal of the low-side detection transistor and a third fixed voltage terminal, and a first bypass circuit arranged in parallel with the first resistor, and configured to be switched on when the control signal is set to a level which instructs the low-side transistor to switch off, and to be switched off when the control signal is set to a level which instructs the low-side transistor to switch on, and wherein a signal output via the second terminal of the low-side detection transistor is output as the low-side off-detection signal.