Patent ID: 7661099

Claim:
A method for optimizing a transaction comprising an initial sequence of computer operations by constructing a computer implemented graph representative of the computer operations, the method comprising: identifying one or more idempotent operations comprised within the initial sequence; and reordering the initial sequence to form a reordered sequence comprising a first sub-sequence of the computer operations followed by a second sub-sequence of the computer operations, the second sub-sequence comprising only the one or more idempotent operations, wherein each of the computer operations of the initial sequence has a respective sequence number (sn) and comprises a variable (v) equated to a function (k), and wherein identifying the one or more idempotent operations comprises: defining for the initial sequence graph vertices comprising variable vertices as ordered pairs (sn,v) and function vertices as ordered pairs (sn,k); constructing directed line segments between the graph vertices in response to predefined rules; and determining that a given directed line segment representative of a given computer operation is not contained in a loop of the directed line segments, so as to identify the given computer operation as idempotent, wherein the predefined rules comprise: constructing, for each computer operation sn, a directed line segment from each function vertex (sn,k) to its variable vertex (sn,v); for i<j, constructing a directed line segment from a variable vertex (sn,v) of a sequence number i to a function vertex (sn,k) of a sequence number j, if: v appears as an argument in function k, and there is no computer operation between sequence i and sequence j for which v is a variable; for i=j, constructing a directed line segment from the variable vertex (sn,v) to the function vertex (sn,k) if v appears as an argument of k; and constructing, for each pair of computer operations sn, sp, sp>sn, a directed line segment from the variable vertex (sn,v) to the variable vertex (sp,v) if a same variable v is in both operations and variable v does not appear in a computer operation between computer operations sn, sp; wherein the reordered sequence is an optimized representation of the initial sequence thereby optimizing the transaction in the event of failure.