Patent ID: 8527935

Claim:
An electronic design automation (EDA) tool for reducing power consumption of an electronic circuit design, wherein the circuit design includes a plurality of digital logic elements, the EDA tool comprising: a memory used to store the electronic circuit design; and a processor, in communication with the memory, and configured to: generate a look-up table (LUT) for storing a mapping between a type, a predetermined optimum power input transition time and at least one characteristic of each digital logic element in a cell library, wherein the predetermined optimum power input transition time of a digital logic element corresponds to a lowest sum of a switching power and a short circuit power of the digital logic element, wherein at the predetermined optimum power input transition time, the switching power and short circuit power of the digital logic element are equal; identify an input transition time of a first digital logic element; and replace the first digital logic element with a second digital logic element when the input transition time of the first digital logic element is not equal to the predetermined optimum power input transition time of the first digital logic element, wherein the second digital logic element has a predetermined optimum power input transition time equal to the input transition time of the first digital logic element.