Patent ID: 6874064

Claim:
A first-in first-out (FIFO) memory device, comprising: an embedded memory device; and a multi-port cache memory device having a data input port, a data output port, a first memory port configured to pass write data to said embedded memory device during memory write operations and a second memory port configured to receive read data from said embedded memory device during memory read operations, said multi-port cache memory device comprising: a data input register configured to receive write data from the data input port when the data input register is enabled during FIFO write operations; a retransmit register configured to receive write data from the data input port when the retransmit register is enabled during FIFO write operations; and a multiplexer configured to enable a first memory path that routes first data from the second memory port to the data output port during first FIFO read operations, block the first memory path and enable a direct path that routes second data from said data input register to the data output port during second FIFO read operations, and block the first memory and direct paths and enable a retransmit path that routes third data from said retransmit register to the data output port during retransmit operations, in response to at least one path signal.