Patent ID: 7248504

Claim:
A data processing device comprising: a nonvolatile memory provided with a memory array; and a controller, wherein the memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor, the first MOS transistor, which is used for data storing, having a charge retention layer and a memory gate, and the second MOS transistor having a control gate to selectively connect the first MOS transistor to a bit line, and wherein the controller enables emission of electrons held in a charge retention layer using hot carriers generated in a nonvolatile memory cell channel region by application of negative voltage to the memory gate, enables injection of electrons into the charge retention layer using hot carriers generated in the nonvolatile memory cell channel region by application of positive voltage to the memory gate, and controls the generation and suppression of hot carriers by a bit line voltage on each bit line.