Patent ID: 8046399

Claim:
A computer system comprising: a memory; and a processor coupled to said memory, said processor comprising: a fused-unfused floating point multiply-add (FMA) module, said fused-unfused FMA module for receiving a first multiply term, a second multiply term, and an addition term, wherein in response to said processor receiving a single unfused multiply-add opcode, said fused-unfused FMA module generates an unfused multiply-add rounding result, wherein in response to said processor receiving a single fused multiply-add opcode, said fused-unfused FMA module generates a fused multiply-add rounding result, wherein said unfused multiply-add rounding result is a rounded sum of said addition term with a rounded value of the product of said first multiply term and said second multiply term without obtaining the product of said first multiply term and said second multiply term, wherein in generating said unfused multiply-add rounding result, instead of generating said product of said first multiply term and said second multiply term, a first terminal partial product and a second terminal partial product are generated from said first multiply term and said second multiply term, and further wherein each said first terminal partial product and said second terminal partial product are truncated to produce, respectively, a truncated first terminal partial product and a truncated second terminal partial product, before being combined with said addition term.