Patent ID: 8629528

Claim:
A semiconductor memory device comprising: a semiconductor substrate; a plurality of word lines formed on the semiconductor substrate at predetermined intervals, each of the word lines having a first word line insulating film, a charge accumulating layer, a second word line insulating film, and a controlling gate electrode stacked in sequence; selecting transistors arranged on at least one side of the plurality of word lines; an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors; a first air gap located between a pair of adjacent word lines, the first air gap being separated from the pair of adjacent word lines by a first spacer insulating film and covered by the interlayer insulating film; a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors, the first side wall portion facing the selecting transistors, and the second air gap being separated from the first side wall portion by a second spacer insulating film and covered by the interlayer insulating film; and a third air gap located at a second side wall portion of one of the selecting transistors, the second side wall portion being opposite to one of the word lines, and the third air gap being separated from the second side wall portion by a third spacer insulating film and covered by the interlayer insulating film, wherein a distance between the word lines is smaller than a distance between the selecting transistors, the first, second, and third air gaps are filled with air, and a size of the first air gap is larger than a size of the third air gap.