Patent ID: 8170168

Claim:
A clock data recovery circuit comprising: a detection circuit that detects whether a first logical value D 1 is not equal to a second logical value D 2 , and whether the first logical value D 1 is not equal to a third logical value D 3 , provided that an input data signal sampled at edges of a clock signal at timings t 1 , t 2 , and t 3 are the logical values D 1 , D 2 and D 3 , respectively; and a clock generation circuit that changes a phase of the clock signal based on detection results from the detection circuit, so that the timings at which the logical values of the input data signal change correspond to the timings t 2 and t 3 , wherein timing t 2 <timing t 1 <timing t 3 , wherein the clock signal comprises first and second clock signals having opposite phases to one another, and wherein, when the detection circuit is set in a first operation mode, a timing of an edge of the first clock signal is a timing t 1 , timings of edges of the second clock signal sandwiching the timing t 1 are timings t 2 and t 3 , and when the detection circuit is set in a second operation mode, timings of three temporally consecutive edges of the first clock signal are timings t 2 , t 1 , and t 3 .