Patent ID: 8060844

Claim:
A method for generating timing constraints for a digital circuit using a computer-driven system having at least a digital data storage and a digital data processor, comprising the steps of: a step for describing said digital circuit using a hardware description language (HDL); a step for constructing said digital circuit from said HDL description, using the computer-driven system; and a step for constructing, using the computer-driven system, a system of clocks and artificial flip-flops by the following steps: a step for assigning inputs to an input stage of the digital circuit; a step for computing a length of a longest path from any input to each output; a step for assigning outputs to stages as denoted by the longest path length; a step for adding skips (1T delays) where alternative paths are shorter than the longest path; a step for establishing a series of clocks (C 0 , C 1 , C 2 , . . . , wherein subscripts 0, 1, 2, etc, are integers that denote the sequence in the series of clocks) with a long clock period and a phase delay of T between successive members of said series; for each output and input, a step for constructing a dummy flip-flop inserted in a path connecting said output and input; and a step for clocking said dummy flip-flop with a clock whose subscript is a stage to which the input or output has been assigned; whereby slack equivalence is created, in which timing slacks are equivalent to those in an optimized circuit.