Patent ID: 8352531

Claim:
A floating point processor, comprising: a normalizer result bus that contains an intermediate calculated result; and a rounder that has an increment data path and a non-increment data path, wherein the intermediate calculated result is provided to an input of each of the increment data path and the non-increment data path, wherein upon an occurrence of a corner case, the non-increment data path forces a fraction portion of the intermediate calculated result to all ones or all zeros and the increment data path does not force a fraction portion of the intermediate calculated result to all ones or all zeros; the non-increment data path comprises a leading zero correction multiplexer that selects between bits 1 - 52 or bits 0 - 51 of the intermediate calculated result of the normalizer result bus, output of the leading zero correction multiplexer connecting to a first input of a logic OR gate while a second input of the logic OR gate connects to a signal to force the fraction portion to all ones, where output of the logic OR gate connects to a non-inverting logic of a logic AND gate while an inverting input of the logic AND gate connects to a signal to force the fraction portion to all zeros, and wherein output of the logic AND gate if a first rounder input to a rounded fraction multiplexer; the increment data path comprises a fraction incrementer that adds 1 to a least significant bit position, the fraction incrementer outputting a second rounder input of a first set of bits 1 - 52 to the rounded fraction multiplexer and outputting a third rounder input of a second set of bits 0 - 51 to the rounded fraction multiplexer.