Patent ID: 8850448

Claim:
A dynamic reconfigurable heterogeneous processor architecture with load balancing, comprising: a plurality of microprocessors; at least one dynamic reconfigurable heterogeneous processor coupled to said plurality of microprocessors and assisting said plurality of microprocessors in executing operations; and a work control logic unit coupled to said plurality of microprocessors and said at least one dynamic reconfigurable heterogeneous processor, analyzing work proportion of each of said plurality of microprocessors, dynamically allocating said at least one dynamic reconfigurable heterogeneous processor to support said plurality of microprocessors to execute said operations, and balancing workload of each of said plurality of microprocessors; wherein a method of designing a circuit of said at least one dynamic reconfigurable heterogeneous processor comprising steps of: performing a plurality of hardware requirement analyses using operation requirement trees for basic operations of said plurality of microprocessors, wherein each of said operation requirement trees comprises a plurality of operation nodes showing an operation required; choosing common said plurality of operation nodes of said operation requirement trees to establish a plurality of block-selection trees; choosing sharable said plurality of operation nodes of said plurality of block-selection trees and adding a multiplexer operation node at each sharable said plurality of operation nodes, respectively; and searching all said plurality of block-selection trees and choosing said plurality of operation nodes and associated said multiplexer operation node of said plurality of block-selection trees that fulfill all necessary reconfiguration requirements of said at least one dynamic reconfigurable heterogeneous processor.