Patent ID: 8904156

Claim:
A multithreaded microprocessor comprising: an instruction fetch unit configured to fetch and maintain a plurality of instructions belonging to one or more threads; and one or more execution units configured to concurrently execute the one or more threads; wherein the instruction fetch unit includes a conditional branch prediction unit configured to provide, for each of the one or more threads, a direction branch prediction in response to receiving an instruction fetch address of a current conditional branch instruction, wherein the conditional branch prediction unit includes: a plurality of storages each including a plurality of entries, wherein each entry is configured to store one or more prediction values, and each prediction value of a given storage corresponds to at least one conditional branch instruction in a cache line; and a control unit coupled to the plurality of storages and configured to generate a separate index value for accessing each storage, wherein the control unit is configured to generate a first index value for accessing a first storage by hashing a plurality of different portions of the instruction fetch address, and to generate each other index value for accessing each other respective storage by hashing the first index value with a different portion of direction branch history information for each storage.