Patent ID: 7366267

Claim:
Circuitry for using a reference clock signal to extract data from a data signal, the data signal having a data rate that is twice the reference clock signal frequency, comprising: first circuitry configured to derive from the reference clock signal first and second phase-shifted versions of the reference clock signal that are respectively synchronized with oppositely polarized transitions in level of the data signal; second circuitry configured to sample the data signal in a predetermined phase relationship to the first phase-shifted version of the reference clock signal in order to produce a first partial stream of data extracted from the data signal; and third circuitry configured to sample the data signal in a predetermined phase relationship to the second phase-shifted version of the reference clock signal, while the second circuitry samples the data signal in a predetermined phase relationship to the first phase-shifted version of the reference clock signal, in order to produce a second partial stream of data extracted from the data signal.