Patent ID: 7054205

Claim:
A circuit for determining the propagation delay of an integrated circuit, comprising: a first rank of logic memory elements, each logic memory element having a data input, a data output, and a clock input, the clock inputs being coupled together and configured to be driven by a clock signal; a plurality of delay units coupled in series, each delay unit having an input and an output, the output of each delay unit configured to drive the data input of one of the logic memory elements; a plurality of AND gates, each AND gate being associated with one of the series of delay units, each AND gate having an output configured to drive the data input of the logic memory element of the first rank associated with the delay unit associated with the AND gate, each AND gate having a first input configured to be driven by the output of its associated delay unit and a second input configured to be driven by the output of the AND gate associated with the delay unit immediately preceding the delay unit associated with the AND gate, the second input of the AND pate associated with a first delay unit of the series of delay units being configured to be driven by a logic HIGH; and a logic inverter having an input configured to be driven by the clock signal, the inverter having an output configured to drive the input of the first delay unit of the plurality of delay units.