Patent ID: 8642403

Claim:
A method of forming contacts to source and drain regions in a field-effect transistor (FET) device wherein the source and drain regions of the device are displaced from an underlying substrate, the method comprising the steps of: depositing a patternable dielectric onto the device so as to surround each of the source and drain regions of the device; exposing the patternable dielectric to cross-link the portions of the patternable dielectric that surround the source and drain regions of the device, resulting in cross-linked portions of the patternable dielectric and uncross-linked portions of the patternable dielectric; selectively removing the uncross-linked portions of the patternable dielectric relative to the cross-linked portions of the patternable dielectric, wherein the cross-linked portions of the patternable dielectric form dummy contacts that surround the source and drain regions of the device; depositing a planarizing dielectric onto the device around the dummy contacts; selectively removing the dummy contacts relative to the planarizing dielectric to form vias in the planarizing dielectric that surround the source and drain regions of the device; and filling the vias with at least one metal so as to form replacement contacts that surround the source and drain regions of the device.