Patent ID: 7830386

Claim:
A computer system configured to perform register transfer level (RTL) simulations, comprising: a central processing unit (CPU); a host memory coupled to the CPU and including: an RTL model compiler configured for execution by the CPU to translate a first portion of an RTL model of an electronic circuit device under test and a testbench, each designed for execution by a cycle based simulator, into a graphics program that includes shader or vertex program instructions for execution by the programmable graphics processor, and a graphics device driver configured to provide the graphics program and simulation inputs to a programmable graphics processor; a local memory coupled to the programmable graphics processor and including: state information related to a current state of memory elements in the RTL model, and state information related to a next state of the memory elements in the RTL model, wherein the state information related the next state is stored in the local memory as state variables representing the state of each memory element of the electronic circuit device under test in a graphics surface, and wherein a second portion of the RTL model that is not designed for execution by the cycle based simulator is not translated into the graphics program and is executed by the CPU; and the programmable graphics processor that is configured by the graphics program to: read the state information related to the current state of memory elements in the RTL model as texels of a first texture map from the local memory, combine the texels with the simulation inputs for a current simulation timestep to produce filtered texture data that is next state values for each memory element of the electronic circuit device under test represented in the graphics program as the next state variables, and store the next state variables in the local memory as a second texture map corresponding to a particular texture identifier.