Patent ID: 7416949

Claim:
A method of manufacturing a semiconductor device, comprising: forming first and second gates including patterning a silicon-containing layer on a semiconductor substrate; etching simultaneously said patterned silicon-containing layer of said first gate and first substrate portions adjacent to said first gate, to form a first gate electrode opening and source and drain openings, respectively, wherein said second gate and second substrate portions adjacent to said second gate are masked; forming SiGe simultaneously in said first gate electrode openings and in said source and drain openings, wherein said second gate electrode and said second substrate portions are masked; removing said SiGe from an upper surface of said first gate to form a second opening therein; depositing a metal simultaneously on said first and second gates to form a metal layer thereon; and annealing said first and second gates to form fully silicided first and second gate electrodes, wherein an amount of said metal at an interface of said fully silicided gate electrode layer and an underlying gate dielectric layer is greater than an amount of said metal an second interface of said second fully silicided gate electrode layer and an underlying second gate dielectric layer.