Patent ID: 7265409

Claim:
A non-volatile semiconductor memory comprising: a memory transistor including: a stacked-layer film formed between a semiconductor substrate and a gate electrode and having a charge storage ability, a first conductivity type region formed in the semiconductor substrate in which a channel is formed under the control of the gate electrode via the stacked-layer film, and two second conductivity type regions formed in the semiconductor substrate sandwiching the first conductivity type region therebetween, wherein a thickness of the first conductivity type region in a stacking direction of the stacked-layer film is not greater than a thickness of either one of the two second conductivity type regions, and a channel length L is between channel lengths L 1 and L 2 , with L 1 being estimated for determining the boundary of occurrence of short channel effects at the time of a write operation and L 2 at the time of a read operation, and L 1 is different from L 2 .