Patent ID: 6927480

Claim:
A multi-chip package with electrical interconnection comprising: a leadframe having a plurality of leads, the leads including a common lead; a dielectric carrier attached to the leadframe; a relay conductor having a top surface and a bottom surface, the bottom surface of the relay conductor being attached to the dielectric carrier to make the relay conductor be electrically isolated from the leadframe, the top surface of the relay conductor being formed for wire-bonding connection; a first chip disposed on the dielectric carrier, wherein the first chip has a back surface, an active surface, and a first pad disposed on the active surface of the first chip; a second chip disposed on the dielectric carrier, wherein the second chip has a back surface, an active surface and a second pad disposed on the active surface of the second chip; a first bonding wire connecting the first pad of the first chip to the top surface of the relay conductor; a second bonding wire connecting the second pad of the second chip to the top surface of the relay conductor; a third bonding wire connecting the top surface of the relay conductor to the common lead; and a molding compound sealing the first chip, the second chip, the relay conductor, the first bonding wire, the second bonding wire and the third bonding wire.