Patent ID: 7216319

Claim:
An integrated circuit comprising: a global clock buffer having a global clock buffer input; a first regional clock buffer having a first regional clock buffer input and a first regional clock buffer output; a global clock tree having a global clock tree trunk portion connected to the global clock buffer and a first global clock tree spine connected to and extending from the global clock tree trunk portion, the first global clock tree spine coupling a clock signal from the global clock buffer to the first regional clock buffer input; a first regional clock tree having a first regional clock tree trunk portion electrically connected to the first regional clock buffer output and a first regional clock tree spine connected to and extending from the first regional clock tree trunk portion, the first regional clock tree spine having a first end and a second end; a first flip-flop proximate and electrically connected to the first end of the first regional clock tree spine; a circuit block; a first routing portion connecting the circuit block to the global clock buffer input; and a second routing portion connecting the first flip-flop to the circuit block so as to form a first clock ring allowing measurement of a first clock ring delay of the first clock ring.