Patent ID: 8437165

Claim:
A semiconductor memory device comprising: a first memory cell including a first transistor, a second transistor, and a capacitor; a second memory cell including a third transistor; a first line; a second line; a third line; a fourth line; and a fifth line, wherein a gate of the first transistor is electrically connected to the first line, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a first electrode of the capacitor, wherein a second electrode of the capacitor and a gate of the third transistor are electrically connected to the second line, wherein the other of the source and the drain of the first transistor is electrically connected to the third line, wherein one of a source and a drain of the second transistor is electrically connected to the fourth line, and wherein the other of the source and the drain of the second transistor is electrically connected to the fifth line.