Patent ID: 7836269

Claim:
A system that secures information in a memory, comprising: a host processor that generates at least one command, the at least one command is at least one of a read, a write, a program, or an erase command; and at least one other processor associated with the host processor that receives and analyzes the at least one command, and determines if the at least one command is valid and if the at least one command has access rights to a partition in the memory, the at least one other processor comprises an authentication component that solicits authentication data from an entity and determines access rights to the memory based in part on the authentication data received from the entity, and the at least one other processor controls access to the memory based in part on a level of authentication associated with the authentication data; the at least one other processor further comprises a host memory interface that monitors information communicated via a bus situated between the host processor and the memory, the host memory interface analyzes the information and determines if the at least one command is valid and if the at least one command has access rights to a partition in the memory, the bus positioned in part in the at least one other processor, the host memory interface aborts the at least one command if it is invalid, and the host memory interface prevents the at least one command from executing an operation in the memory if the at least one command does not have access rights to the partition regardless of the validity of the at least one command.