Patent ID: 8219847

Claim:
An arithmetic unit supplied with a clock for performing an operation in arbitrary one of a high clock mode in which a specified clock frequency is supplied and a low clock mode in which a specified clock frequency lower than that of the high clock mode is supplied, the arithmetic unit comprising: an execution section, which performs one of a plurality of different basic operations included in a targeted operation at one cycle of the clock frequency when in the high clock mode, and sequentially performs at least two basic operations of the targeted operation at one cycle of the clock frequency when in the low clock mode; a clock mode storage section which receives and stores, in accordance with a supplied clock frequency, one of high clock mode information and low clock mode information from an external circuit, and the external circuit outputting the high clock mode information indicative of the high clock mode when a clock frequency in the high clock mode is supplied, and outputting the low clock mode information indicative of the low clock mode when a clock frequency in the low clock mode is supplied, wherein the execution section performs one of the basic operations in the targeted operation at one cycle of the clock frequency when the clock mode storage section stores the high clock mode information, and wherein the execution section sequentially performs at least the two basic operations in the targeted operation at one cycle of the clock frequency when the clock mode storage section stores the low clock mode information.