Patent ID: 7005349

Claim:
A method of manufacturing a SONOS memory, the method comprising: forming a silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layer on a substrate; forming a buffer layer on the ONO dielectric layer, the buffer layer having a trench exposing a portion of the surface of the ONO dielectric layer; forming first conductive spacers on inner walls of the trench; separating the ONO dielectric layer into two portions by selectively removing the exposed portion of the ONO dielectric layer using the first conductive spacers as an etch mask; forming a gate dielectric layer on the exposed substrate resulting from the separation of the ONO dielectric layer, the gate dielectric layer extended onto exposed sidewalls of the separated ONO dielectric layer and the first conductive spacers inside the trench and also onto top surface of the buffer layer; forming a second conductive layer on the gate dielectric layer to fill a gap between the inner walls of the trench; removing the gate dielectric layer exposed by the second conductive layer; removing the buffer layer using the first conductive spacers as an etch mask; and patterning the two-separated ONO dielectric layers by selectively removing a portion of each of the separated ONO dielectric layer, which is exposed by the removal of the buffer layer, using the first conductive spacers as an etch mask.