Patent ID: 8824616

Claim:
A integrated transceiver circuit device comprising: a plurality of receivers coupled to a plurality of channels, each of the channels being configured for transmitting asynchronous data to one of the receivers, each of the receivers comprising: a pre-amplifier device having an input and an output, the input being coupled to a channel associated with the receiver; a comparator device comprising an input coupled to the pre-amplifier, and configured to identify one or more binary states; a phase interpolator device coupled to a receiver of the comparator device, the phase interpolator device being configured to perform a digital to phase conversion using information from the one or more binary states; and a clock data recovery (CDR) device coupled to an output of the comparator device and configured to drive the phase interpolator device to synthesize a frequency and phase of a signal from the output; and a phase locked loop (PLL) device, the PLL device being common to and being coupled to each of the phase interpolator devices.