Patent ID: 8130549

Claim:
A memory system, comprising: a nonvolatile memory device, including a plurality of multi-bit nonvolatile memory cells, each multi-bit nonvolatile memory cell storing at least two bits; a memory storing a program when the system powers up; and a controller implementing the program to control operations of the non-volatile memory device including providing instructions used to program and erase the at least two bits from each of at least some of the multi-bit nonvolatile memory cells and to manage the at least two bits from each of at least some of the multi-bit nonvolatile memory cells that are over-programmed, wherein the controller comprises an error signal generator configured to, for each of at least some of the memory cells: receive the at least two bits stored in the memory cell and at least two bits to be programmed in the memory cell, and assert an error signal when the memory cell is over-programmed relative to the at least two bits to be programmed in the memory cell.