Patent ID: 7042073

Claim:
A semiconductor device comprising: a wiring substrate having a main surface, a plurality of wiring lines and a plurality of electrode pads; a first semiconductor chip having a main surface, a plurality of semiconductor elements and a plurality of electrodes, the first semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of first bump electrodes in such a manner that the main surface of the first semiconductor chip is opposed to the main surface of the wiring substrate; a second semiconductor chip having a main surface, a plurality of semiconductor elements and a plurality of electrodes, the second semiconductor chip being mounted over the main surface of the wiring substrate through a plurality of second bump electrodes in such a manner that the main surface of the second semiconductor chip is opposed to the main surface of the wiring substrate and that a side face of the second semiconductor chip is adjacent to a side face of the first semiconductor chip; a third semiconductor chip having a main surface, a plurality of semiconductor elements and a plurality of electrodes, the third semiconductor chip being mounted over the first and second semiconductor chips in such a manner that a rear surface of the third semiconductor chip is opposed to rear surfaces of the first and second semiconductor chips; a plurality of bonding wires electrically connecting the plurality of electrodes of the third semiconductor chip and the plurality of electrode pads respectively; a first resin member sealing between the main surface of the first semiconductor chip and the main surface of the wiring substrate, between the main surface of the second semiconductor chip and the main surface of the wiring substrate, and between the side face of the first semiconductor chip and the side face of the second semiconductor chip; and a second resin member sealing the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, part of the main surface of the wiring substrate, and part of the first resin member, wherein the first resin member contains a first silica filler, the first silica filler having a first particle diameter, the second resin member contains a second silica filler, the second silica filler having a second particle diameter, and wherein the first particle diameter is smaller than the second particle diameter.