Patent ID: 7750702

Claim:
A pulse generation circuit for outputting a pulse with a predetermined waveform to an output terminal in response to a start signal, comprising: an inverter delay circuit including a plurality of inverters connected in series and each executing logic inversion on the start signal with a predetermined amount of delay; a first switching circuit adapted to connect the output terminal to a first voltage V 1 when a logical product of an output Di (i denotes an even number in a predetermined range) of an ith inverter of the inverter delay circuit and an output XDi−1 of an i−1th inverter of the inverter delay circuit is true, and to connect the output terminal to a second voltage V 2 when a logical sum of the output Di of the ith inverter of the inverter delay circuit and an output XDi+1 of an i+1th inverter of the inverter delay circuit is false; a second switching circuit adapted to connect the output terminal to the first voltage V 1 when a logical product of the output Di of an ith inverter of the inverter delay circuit and the output XDi+1 of the i+1th inverter of the inverter delay circuit is true, and to connect the output terminal to the second voltage V 2 when a logical sum of the output XDi+1 of the i+1th inverter of the inverter delay circuit and an output Di+2 of an i+2th inverter of the inverter delay circuit is false; and a start signal control circuit adapted to input the start signal to the inverter delay circuit with a delay equal to an amount of delay of every inverter of the inverter delay circuit when the first switching circuit is activated, and to input the start signal to the inverter delay circuit without the delay when the second switching circuit is activated.