Patent ID: 8619469

Claim:
A non-volatile memory device integrated in a chip of semiconductor material, the memory device comprising: a plurality of memory cells, each one including a first well and a second well of a first type of conductivity being formed in an insulating region of a second type of conductivity; a first, a second, a third and a fourth region of the second type of conductivity being formed in the first well for defining a sequence of a first selection transistor of MOS type; a storage transistor of floating gate MOS type; and a second selection transistor of MOS type being coupled in series, the first region being short-circuited to the first well, a first gate of the first selection transistor, a second gate of the second selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well, the control gate being capacitively coupled with the floating gate.