Patent ID: 8627003

Claim:
An apparatus comprising: a requirements module that receives one or more of a capacity upgrade goal for an overall capacity of an array of members that are memory devices in a computer memory and a speed-related performance upgrade goal for an overall performance of the array, each member of the array having an individual performance capability wherein the overall performance has a substantially inverse relationship with a highest quantity of members of a subset of the array and a substantially direct relationship with the individual performance capability of the members; an analysis module that identifies a first potential capacity change that can be achieved at a lower overall performance and a second potential capacity change that can be achieved at a higher overall performance; and a reconfiguration module that generates one or more of a first physical reconfiguration recommendation calculated to yield an overall capacity improvement that takes into consideration the capacity upgrade goal and the first potential capacity change and a second physical reconfiguration recommendation calculated to yield an overall performance improvement that takes into consideration the performance upgrade goal and the second potential capacity change, wherein the requirements module, the analysis module, and the reconfiguration module comprise one or more of logic hardware and executable code, the executable code stored on one or more non-transitory computer-readable storage media.