Patent ID: 7397702

Claim:
A read/verify circuit for multilevel memory cells, the circuit comprising: a read terminal selectively connectable to an array cell of a plurality of array cells, the array cell having an array cell threshold voltage; a plurality of reference cells having respective reference threshold voltages; a plurality of threshold-detection circuits including a first threshold-detection circuit for detecting said array cell threshold voltage and a set of reference threshold-detection circuits for detecting said reference threshold; voltages, each threshold-detection circuit comprising a resistor as a detector element, arranged so as to be traversed by a current in response to a turning-on of either the array cell or one of the reference cells connected thereto; a ramp-voltage generator for providing a ramp read voltage, the ramp voltage generator connected to respective control terminals of said reference cells and the array cell of the plurality of array cells; and a read register coupled to said set of reference threshold-detection circuits, the turning on of each reference cell triggering modification of the read register until the array cell turns on.