Patent ID: 7087951

Claim:
A process of fabricating a non-volatile memory cell array, comprising: forming strips of polysilicon across a semiconductor substrate with a layer of dielectric therebetween, the polysilicon strips being elongated in a first direction across the substrate and being spaced apart in a second direction, wherein the first and second directions are orthogonal with each other, etching trenches into the substrate between at least every other one of the polysilicon strips, said trenches being defined by positions of the polysilicon strips and having lengths extending in the first direction, thereafter implanting ions along the lengths of the trenches to form elongated sources and drains in said trenches, thereafter separating the strips of polysilicon into individual floating gates, thereby forming a two-dimensional array of floating gates, forming a first plurality of elongated gates extending across the array of floating gates in the second direction that extend into the trenches crossed by them, and forming a second plurality of elongated gates.