Patent ID: 6995055

Claim:
A method of manufacturing a semiconductor integrated circuit having first and second conductivity type CMOS transistors, comprising the steps of: providing an SOI substrate having a semiconductor film of a first conductivity type provided on a support substrate of a first conductivity type via a buried insulating film; simultaneously forming at least one alignment mark and a contact hole for each CMOS transistor in the SOI substrate, the at least one alignment mark and the corresponding contact hole extending through the semiconductor film and the buried insulating film and into the support substrate, the contact holes being formed in a source-body-tie region of the CMOS transistors and being formed adjacent to regions where a source region and a body region of the CMOS transistors are to be formed; forming a thermal oxide film on the semiconductor film to cover an inside of the contact holes; forming second conductivity type impurity regions in the support substrate in regions where the first and second conductivity type CMOS transistors are to be formed; performing a thermal process to diffuse impurities in the second conductivity type impurity regions; forming a first conductivity type impurity region in the semiconductor film so as to reach the buried insulating film in a region where the second conductivity type CMOS transistor is to be formed; forming a first conductivity type impurity region in a region of the support substrate surrounded by one of the second conductivity type impurity regions and disposed opposite to the first conductivity type impurity region formed in the semiconductor film; forming a second conductivity type impurity region in the semiconductor film so as to reach the buried insulating film in a region where the first conductivity type CMOS transistor is to be formed; forming gate oxide films, gate electrodes, source regions, drain regions, and body regions of the CMOS transistors; forming an interlayer insulating film over the CMOS transistors; etching the interlayer insulating film so as to form source region contacts, drain region contacts, and body contacts for each of the CMOS transistors; and forming wiring on the interlayer insulating film.