Patent ID: 7145203

Claim:
A high-voltage n-channel MOSFET, comprising: a p− doped substrate; a p− well disposed in said substrate; a first n+ doped region disposed in said p− well; a source terminal coupled to said first n+ doped region; an n− well disposed in said substrate; a second n+ doped region disposed in said n− well; a drain terminal coupled to said second n+ doped region; a p+ doped region disposed in said substrate; a body terminal coupled to said p+ doped region; a graded-junction region of said substrate separating said p− well and said n− well; a dielectric layer disposed over said p− well, said graded junction region and a portion of said n− well; a first isolator disposed in said n− well, said isolator including a dielectric material that is in contact with said dielectric layer; a second isolator disposed at least partially in said n− well, said second isolator including a dielectric material and isolating said second n+ region from said p+ region; and a gate disposed over said dielectric layer and a portion of said first isolator.