Patent ID: 7639737

Claim:
A receiver comprising: a. a receive port to receive an input data signal; b. an equalizer coupled to the receive port to equalize the input data signal, the equalizer including an equalizer control port and an equalizer output port, wherein the equalizer issues an equalized data signal on the equalizer output port; c. a data sampler coupled to the equalizer output port to receive the equalized data signal, the data sampler to sample the equalized data signal and issue a series of data samples on a data-sampler output port; d. an edge sampler coupled to the equalizer output port to receive the equalized data signal, the edge sampler to sample the equalized data signal and issue a series of edge samples on an edge-sampler output port; and e. equalizer control circuitry coupled to the equalizer control port of the equalizer, the equalizer control circuitry including: i. a bit correlator having a correlator input port, coupled to the data-sampler output port, and a match port, the bit correlator to issue a match signal on the match port when the series of data samples matches a specified bit pattern; ii. a phase detector coupled to the data-sampler output port and the edge-sampler output port, the phase detector to issue a relative-timing signal on a relative-timing port, the relative-timing signal based upon a comparison of ones of the edge and data samples; and iii. equalization logic coupled to the relative-timing port, the match port, and the equalizer control port, the equalization logic to adjust the equalizer in response to the relative-timing signal and the match signal.