Patent ID: 8176460

Claim:
An electrostatic discharge (ESD) protection optimizer for an integrated circuit (IC) comprising: a series of operating instructions stored on a computer readable storage medium that directs an operation of a processor when executed thereby, the instructions including: a circuit analyzer configured to identify ESD cells and circuitry of said IC by comparing component information of said IC with predefined ESD protection elements and predefined circuit topologies; and an ESD resistance determiner configured to calculate a resistance value to couple in series with said circuitry, said resistance value based on protection cell physical attributes associated with said identified ESD cells and circuitry physical attributes associated with said identified circuitry, wherein said ESD resistance determiner is further configured to identify ESD protection paths between the at least one terminal pair of said identified circuitry; and wherein said ESD resistance determiner is further configured to collapse each of said ESD protection paths into a single ESD component having combined physical attributes based on said protection cell physical attributes associated with said identified ESD cells of said each of said ESD protection paths.