Patent ID: 7577779

Claim:
A method for handling operation of circuitry, the method comprising: configuring an on-chip programmable device that functions as a master on a first bus, wherein the first bus comprises a second bus and a third bus coupled via a bridge, wherein the second bus is a high speed bus and the third bus is a low speed bus, wherein the on-chip programmable device comprises a high-speed second bus interface that directly interfaces the second bus and a low-speed third bus interface that directly interfaces the third bus, wherein at least one interface to another device is coupled to said third bus, the at least one interface comprising a general purpose input/output interface, a three-wire interface and a digital-to-analog converter control interface, wherein said another device comprises a front-end transmitter, a front-end receiver and a baseband processor, wherein said another device is off an integrated circuit (IC) chip that comprises the on-chip programmable device, wherein the on-chip programmable device is programmed by a processor via the high-speed second bus interface, the processor directly accessing the second bus, the on-chip programmable device directly accessing the second bus and directly accessing the third bus; and controlling said another device coupled to said at least one interface via at least one signal generated by said on-chip programmable device, wherein said at least one generated signal is communicated via said third bus to said at least one interface when said on-chip programmable device receives an input timer signal.