Patent ID: 8629515

Claim:
A semiconductor device, comprising: a semiconductor substrate; a source and a drain region formed on the semiconductor substrate; and a gate structure disposed on the substrate between the source and drain regions, the gate structure including: an interfacial layer formed over the substrate; a high-k dielectric formed over the interfacial layer; and a metal gate element formed over the high-k dielectric wherein the metal gate element includes a first linear sidewall substantially perpendicular a top surface of the semiconductor substrate and an opposing second linear sidewall substantially perpendicular the top surface of the semiconductor substrate, wherein the first linear sidewall and the second linear sidewall extend to a top surface that is co-planar with a top surface of a spacer element abutting the gate structure and wherein the metal gate element includes: a first metal layer and a second metal layer, wherein the first metal layer provides a work function for the metal gate element and defines a first portion of the first linear sidewall and a first portion of the second linear sidewall and wherein the second metal layer defines a second portion of the first linear sidewall and a second portion of the second linear sidewall, wherein the second metal layer is a non-silicide fill metal including copper, wherein a liner layer of the spacer element directly interfaces with the first metal layer and the second metal layer; and wherein the metal gate element has a length at a top surface that is greater than a length at the bottom surface, the bottom surface being closer to the substrate than the top surface, wherein the lengths are measured along a channel length.