Patent ID: 7053658

Claim:
A logic circuit comprising: a first transistor; a second transistor that is arranged to operate as a cascode transistor in cooperation with the first transistor, wherein the second transistor includes: a gate that is coupled to a bias node, a drain that is coupled to a first output node, and a source that is coupled to a second output node; a third transistor; a fourth transistor that is arranged to operate as a cascode transistor in cooperation with the third transistor, wherein the fourth transistor includes: a gate that is coupled to the bias node, a drain that is coupled to a first complement output node, and a source that is coupled to a second complement output node, a first keeper switch circuit that is coupled to the bias node, the second complement output node, and the second output node, and a second keeper switch circuit that is coupled to the bias node, second output node, and the second complement output node.