Patent ID: 7800968

Claim:
A differential sense amplifier assembly, comprising: a first transconductance circuit configured to conduct a memory cell current based on a bitline voltage, wherein the memory cell current is indicative of a data state of the memory cell being read; a first integration circuit configured to integrate the memory cell current or a first current associated therewith, and generate a first voltage at a first differential output terminal in response thereto; a second transconductance circuit configured to conduct a reference cell current based on a reference bitline voltage, wherein the reference cell current is indicative of an intermediate data state of a reference memory cell being read; a second integrator circuit configured to integrate the reference cell current or a second current associated therewith, and generate a second voltage at a second differential output terminal in response thereto; an equalizer circuit configured to equalize voltages at the first and second differential output terminals prior to integration by the first and second integrator circuits, wherein a differential voltage measured across the first and second differential output terminals is indicative of the data state of the memory cell being read.