Patent ID: 7958321

Claim:
An apparatus for reducing memory access conflict when a plurality of data processing elements perform simultaneous access to a memory including a plurality of pages, each of which includes a plurality of subpages, the apparatus comprising: an access arbiter configured to map a subpage division address corresponding to least significant bits of a memory access address received from each of the data processing elements to another address having the same number of bits as that of the subpage division address in order for data to be output from each of the subpages in a corresponding page at a time of the simultaneous access; and a selector, prepared for each of the pages, configured to select one of the data output from the subpages using the mapped results, wherein the access arbiter classifies the pages using most significant bits of the memory access address and concatenates middle bits of the memory access address and most significant bits of the mapped address to use as a subpage address.