Patent ID: 7183646

Claim:
A semiconductor die carrier comprising: a carrier housing having a cavity; a semiconductor die disposed in the cavity; a plurality of leads extending through a side wall of the carrier housing, the leads having first end portions located within the carrier housing and second end portions located outside of the carrier housing, wherein the first end portions are electrically connected to the semiconductor die via a conductive medium and the second end portions are adapted for forming surface mount connections to a printed circuit board; and an electrical interconnect component of an electrical interconnect component mating pair having two types, the electrical interconnect component coupled to the carrier housing and having a plurality of conductive pins electrically connected to the semiconductor die via a conductive medium, wherein the electrical interconnect component corresponds to the first type that mates with electrical interconnect components of the second type to form electrical connections, the pins being accessible from the outside of the carrier housing to mate with corresponding pins of the second type interconnect components, wherein the conductive pins of the electrical interconnect component are located above the printed circuit board when the leads form surface mount connections to the printed circuit board.