Patent ID: 7102610

Claim:
An apparatus for an LCD that is organized as rows and columns, wherein data for the LCD is organized according to lines within a frame, the apparatus comprising: a memory circuit that is configured to store display image data and further configured to couple the display image data to the LCD such that the LCD is capable of processing the display image data, wherein a sequence that the image data is sent to the memory circuit is different from a sequence that the image data is coupled to the LCD; and a display control circuit that is coupled to the memory circuit, wherein the display control circuit is configured to: receive the display image data, transfer the display image data to the memory circuit, select a first set of line addresses for a first subframe, wherein the first subframe includes at least two lines that are non-adjacent to one another, select a second set of line addresses for a second subframe, select a first scan sequence order for the first subframe of a first frame, select a second scan sequence order for the second subframe of the first frame, select a third scan sequence order for the first subframe of a second frame; select a fourth scan sequence order for the second subframe of the second frame; control column driver polarities of a plurality of column drivers such that the column driver polarities correspond to: a first set of polarities during a first time interval while the first subframne of the first frame is processed, a second set of polarities during a second time interval while the second subframe of the first frame is processed, a third set of polarities during the third time interval while the first subframe of the second frame is processed, and a fourth set of polarities during the fourth time interval while the second subframe of the second frame is processed, wherein each pixel in the LCD has an associated drive voltage that corresponds to an average voltage of zero over time, and wherein the second subframe is processed after the first subframe for each frame, control the transfer of the display image data such that the display image data is transferred from the memory circuit to the LCD according to: the first scan sequence order during the first time interval, the second scan sequence order during the second time interval, the third scan sequence order during the third time interval, and the fourth scan sequence order during the fourth time interval; and control a scanning of the rows such that the rows are scanned according to: the first scan sequence order during the first time interval, the second scan sequence order during the second time interval, the third scan sequence order during the third time interval, and the fourth scan sequence order during the fourth time interval.