Patent ID: 7372340

Claim:
A clock generation circuit, comprising: a phase-locked loop for generating a plurality of clock phases, comprising a phase detector having a first input receiving a reference signal and a second input receiving a feedback signal, for producing an error signal at an output corresponding to a phase difference between the reference and feedback signals, a filter for low-pass filtering the error signal, a voltage-controlled oscillator for generating the plurality of clock phases at a frequency selected by the filtered error signal, wherein one of the plurality of clock phases is coupled to the phase detector as the feedback signal; and a flying-adder frequency synthesis circuit, comprising: a plurality of phase selection circuits, each phase selection circuit receiving the plurality of clock phases from the phase-locked loop and receiving a frequency select signal, and for selecting one of the plurality of clock phases responsive to the frequency select signal, an output multiplexer, having inputs coupled to the outputs of the plurality of phase selection circuits, for selecting each of its inputs for application to an output in sequence, a first toggle multivibrator, having a clock input coupled to an output of the output multiplexer, the first toggle multivibrator arranged to invert its state responsive to a transition at its clock input, and a second toggle multivibrator, having a clock input coupled to an output of the first toggle multivibrator, and having an output, the second toggle multivibrator arranged to invert its state responsive to a transition at its clock input; wherein the voltage-controlled oscillator comprises: an even-numbered plurality of differential stages, each differential stage having positive and negative inputs and positive and negative outputs; wherein the positive and negative outputs of all but a selected one of the plurality of differential stages are connected to the negative and positive inputs, respectively, of the next adjacent one of the plurality of differential stages; and wherein the positive and negative outputs of the selected one of the plurality of differential stages are connected to the positive and negative inputs, respectively, of the next adjacent one of the plurality of differential stages.