Patent ID: 8525259

Claim:
A semiconductor device comprising: a semiconductor layer of a first general conductive type; an element isolation insulation layer formed on the semiconductor layer and having an opening in plan view of the semiconductor layer, an inner edge of the opening in the element isolation insulation layer defining an active region in the plan view, and the active region being wider in a gate width end portion than in a gate width center portion in the plan view; a body layer of a second general conductive type formed in the active region and comprising a channel region; a source layer of the first general conductive type formed in the body layer; a gate insulation film formed in the active region so as to cover the channel region; a gate electrode formed on the gate insulating film; a drift layer of the first general conductive type formed in the semiconductor layer; and a drain layer of the first general conductive type formed in the drift layer, wherein the inner edge of the opening in the element isolation insulation layer includes a corner portion in the plan view.