Patent ID: 7315539

Claim:
A method for handling data between a Clock and Data Recovery (CDR) circuit and a data processing unit of a telecommunications network node of an asynchronous network, using a bit rate adaptation system comprising a memory unit and Pointer Synchronization Controller, said memory unit having a memory stack and a write process circuit and a read process circuit, said method comprising the steps of: the CDR passing recovered data and recovered clock signals to the bit rate adaptation system and the bit rate adaptation system handling the data to the processing unit at a rate indicated by a local node clock; the write process circuit, controlled by the recovered clock, incrementing a write pointer and writing the recovered data into the memory address indicated by said write pointer, and the read process circuit controlled by the local clock incrementing a read pointer and reading the recovered data from the memory address indicated by said read pointer, both pointers running free until the end of a data frame; and the pointer synchronization controller monitoring the recovered data signal to detect guard bands between data frames and bit synchronization fields and, depending on this information, acting on the pointers of the memory unit wherein upon detecting the guard band between data frames, the write pointer is set to a predetermined fixed initial address; and upon detecting the bit synchronization field of the input data frame, the read pointer is set to said write pointer fixed initial address.