Patent ID: 8434086

Claim:
A system comprising: a processor; one or more memory storage units; software code stored in the one or more memory storage units, where the software code is executable by the processor and comprises: a plurality of adaptive partitions each having an associated guaranteed processor time budget and one or more associated process threads from a plurality of process threads; the plurality of process threads each having a priority and each dynamically associable with any one of the plurality of adaptive partitions; and a process scheduler executable by the processor configured to: when the system is under a normal load, allocate the processor to a process thread, of the plurality of process threads, that is in a ready state and having the highest priority amongst process threads, of the plurality of process threads, that are in the ready state; and when the system is in overload, allocate the processor to a process thread, of the plurality of process threads, that is in the ready state, having the highest priority amongst process threads, of the plurality of process threads, that are in the ready state and for which the adaptive partition that the process thread is associated with has available guaranteed processor time budget; where the guaranteed processor time budget is allocated and billed over successive averaging windows; and where a portion of the guaranteed processor time budget associated with each adaptive partition is billed whenever the processor is allocated to a process thread associated with the adaptive partition.