Patent ID: 7964918

Claim:
A semiconductor device, comprising an n-channel field effect transistor and a p-channel field effect transistor formed on a semiconductor substrate, wherein: a gate electrode of one of the n-channel field effect transistor and the p-channel field effect transistor includes a metal-containing layer in contact with a gate insulating film, and a first silicon-containing layer formed on the metal-containing layer; a gate electrode of the other one of the n-channel field effect transistor and the p-channel field effect transistor includes a second silicon-containing layer in contact with a gate insulating film, a conductive oxide layer formed on the second silicon-containing layer, another metal-containing layer formed on the conductive oxide layer, and a third silicon-containing layer formed on the other metal-containing layer; the metal-containing layer and the other metal-containing layer are formed by a same metal-containing film; the first silicon-containing layer and the third silicon-containing layer are formed by a same silicon-containing material film, an offset spacer is formed on a side surface of the gate electrode of the other one of the n-channel field effect transistor and the p-channel field effect transistor, and a width of a lower portion of the offset spacer in the gate length direction is smaller than that of an upper portion of the offset spacer in the gate length direction.