Patent ID: 8332552

Claim:
A method for configuring multiple high bandwidth input/output controllers for a plurality of processing cores on a processor chip, the method comprising: connecting a plurality of physical interface macros and a plurality of input/output interface controllers to a switch on the processor chip, wherein the switch and the plurality of input/output interface controllers are implemented in hardware in the processor chip; selecting an input/output interface controller, from the plurality of input/output interface controllers on the processor chip, for each physical interface macro within the plurality of physical interface macros on the processor chip, wherein each of the plurality of physical interface macros supports heterogeneous electrical properties to provide the selected one of a plurality of input/output interface controllers; setting a mode selector for each physical interface macro to configure each physical interface macro to provide an input/output interface for the respective selected input/output interface controller; disabling power permanently to non-selected input/output interface controllers, wherein the plurality of input/output interface controllers consist of the selected input/output interface controllers and the non-selected input/output interface controllers; configuring the switch to connect each physical, interface macro to its respective selected input/output interface controller such that the plurality of physical interface macros and their respective input/output interface controllers provide a plurality of input/output interfaces for the plurality of processing cores on the processor chip.