Patent ID: 7809924

Claim:
A system for generating an effective address, comprising: a dispatch unit for dispatching an instruction; an adder for generating a first portion of the effective address for the instruction by calculating a first plurality of effective address bits of the effective address; a multiplexer for generating a second portion of the effective address for the instruction by guessing a second plurality of effective address bits of the effective address to form a guessed generated effective address for the instruction; a mechanism for sending the guessed generated effective address to a translation unit; a mechanism for determining whether the guessed generated effective address is correct; responsive to determining that the guessed generated effective address is not correct; a mechanism for invoking a reject for all load and store instructions; a mechanism for instructing the translation unit to ignore the guessed generated effective address; a mechanism for redispatching the instruction for which the guessed generated effective address was not correct; a mechanism for generating a calculated effective address for the instruction by calculating all effective address bits of the effective address to form a calculated generated effective address; scratch registers for storing the calculated generated effective address; and a mechanism for sending the generated calculated effective address from the scratch registers to the translation unit.