Patent ID: 7839653

Claim:
A storage controller comprising: a plurality of logical boards and a backplane for connecting signal lines between the logical boards and supplying power to the logical boards, wherein the backplane comprises a first signal connector for connecting signals of logical boards that are connected to an upper level of the backplane, a second signal connector for connecting signals of logical boards that are connected to a lower level of the backplane, a first power source connector for supplying power to the logical boards connected to the upper level of the backplane, and a second power source connector for supplying power to the logical boards connected to the lower level of the backplane; wherein the first power source connector is formed at one end of the backplane and the second power source connector is formed at another end of the backplane, wherein at least one of the signal lines of the backplane which connects at least one of the signals from the first signal connector to the signals from the second connector is located at the center of the backplane, wherein each of the logical boards comprises a third power source connector connected to either the first power source connector or the second power source connector thereof and a third signal connector connected to either the first signal connector or the second signal connector thereof, the third power source connector being located at one end of said each logical board, wherein a logical board that is connected to the upper level of the backplane receives power via the third power source connector thereof which in turn is connected to the first power source connector thereof, wherein a logical board that is connected to the lower level of the backplane receives power via the third power source connector thereof which in turn is connected to the second power source connector thereof, wherein each of the logical boards further comprises a plurality of ports to be connected to host interfaces, said each logical board receives from the backplane a position signal indicating whether said each logical board is connected to the upper level of the backplane or the lower level of the backplane, wherein logical port numbers of the ports thereof are changed in such a manner that alignment of logical port numbers of the ports of logical boards connected to the upper level of the backplane and alignment of logical port numbers of the ports of logical boards connected to the lower level of the backplane match.