Patent ID: 7499310

Claim:
A bit line voltage supply circuit in a semiconductor memory device, comprising: a bit line voltage switch for applying a first supply voltage to a bit line pair in response to a first switch control signal, and for applying a second supply voltage having a lower voltage than the first supply voltage to the bit line pair in response to a second switch control signal; and a bit line voltage controller for controlling the first and second switch control signals so that the second supply voltage is supplied to the bit line pair in a standby mode, and the first supply voltage is supplied to the bit line pair for a predetermined time period when the semiconductor memory device changes from the standby mode to an operational mode; wherein the bit line voltage controller includes: a Y-main decoder for generating the first switch control signal as an equalization and precharge control signal using a block select signal, a bit line select signal, and a chip select association signal; and a bit line level controller for generating the chip select association signal and the second switch control signal in response to the block select signal and a chip select signal.