Patent ID: 8390026

Claim:
An electronic device comprising a first transistor, the first transistor comprising: a first source/drain region having a first uppermost surface at a first elevation and a first lowermost surface at a second elevation; a second source/drain region having a second uppermost surface substantially at the first elevation and a second lowermost surface substantially at the second elevation; a first gate electrode; and a first channel region, wherein the first channel region includes a heterojunction region overlying a semiconductor substrate, and the heterojunction region is at most approximately 5 nm thick, wherein: the heterojunction region is a portion of the first channel region lying between the first gate electrode and a heterojunction, the heterojunction being the interface of a first layer underlying the first channel region and a second layer underlying the first channel region, the second layer having a different semiconductor composition than the first layer; and the heterojunction lies at a third elevation that is between the first and second elevations.