Patent ID: 7176517

Claim:
A flash memory comprising: a common source line having a first predetermined width, on a semiconductor substrate; a common source in the semiconductor substrate below the common source line; first and second floating gates having a second predetermined width and a height substantially equal to that of the common source line, on outer side walls of the common source line; first tunneling oxide layers between the first floating gate and the semiconductor substrate; a second tunneling oxide layer between to second floating gate and the semiconductor substrate; first and second dielectric layers, each comprising a first oxide layer, a nitride layer, and a second oxide layer, respectively on top and side surfaces of the first and second floating gates and over the semiconductor substrate outside the first and second floating gates; first and second control gates respectively on the first and second dielectric layers, including over the semiconductor substrate outside the first and second floating gates such that the first and second control gates each have a step; and first and second drains in the semiconductor substrate outside the control gate and the common source line.