Patent ID: 7880305

Claim:
An electrical apparatus consisting of first and second different types of circuitry which are interconnected into a functional electrical apparatus unit, an interface supporting rigid insulating relatively high resistivity silicon semiconductor wafer element; having first and second essentially parallel planar surfaces and having a thickness V, said first type of circuitry being positioned on said first planar surface of said rigid relatively high resistivity silicon semiconductor insulating wafer element said second type of circuitry positioned on said second planar surface of said rigid relatively high resistivity silicon semiconductor insulating wafer element, said rigid relatively high resistivity silicon semiconductor insulating wafer further having an array of sub 100 micrometer size electrical blind via opening pathways, each said blind via opening pathway having a wall and a bottom, said blind via opening pathway extending from a contact point on said first type of circuitry on said first planar surface of said rigid relatively high resistivity silicon semiconductor insulating wafer element to said bottom of said blind via pathway opening adjacent said second planar surface of said rigid relatively high resistivity silicon semiconductor insulating wafer element, said blind via pathway extending substantially through said rigid relatively high resistivity silicon semiconductor insulating wafer element said electrical blind via pathways having a diameter X; and, said walls and said bottoms forming said electrical via pathways through said rigid relatively high resistivity silicon semiconductor insulating wafer element being solely filled respectively with an adhesion promoting layer consisting of Cu and TaN/Ta having integrated therein nanoparticles of a Pd active catalyst metal and an electrolessly deposited conducting Ni material situated in contact with said adhesion promoting layer containing said Pd active catalyst metal, each said electrical via pathway terminating at said bottom of said electrical via pathway located adjacent a top of said second planar surface of said rigid relatively high resistivity silicon semiconductor insulating wafer element said electrical via pathway having an aspect ratio V:X in the range of between about 1:1 to 10:1.