Patent ID: 6837731

Claim:
A high density vertical surface mount package having a semiconductor die for use in a computer comprising: a substrate having a plurality of circuits located on at least one surface thereof and having at least two apertures therethrough for use in a computer; two J-shaped locking pins for attaching and removing at least one packaged semiconductor die to the substrate, each J-shaped locking pin of the two J-shaped locking pins including a stem portion and a hooking portion, the hooking portion having a curved portion formed on a first end of the stem portion and having a thickness, each J-shaped locking pin of the two J-shaped locking pins attached to the substrate using an aperture therein for engaging the substrate, the curved portion of the hooking portion of each of the two J-shaped locking pins facing each other and aligned having the curved portion of the hooking portion of one J-shaped locking pin of the two J-shaped locking pins facing the other J-shaped locking pin of the two J-shaped locking pins; and the at least one packaged semiconductor die for use in the computer, the at least one packaged semiconductor die having a first edge for vertically supporting the at least one packaged semiconductor die on the substrate, and having at least one J-shaped locking edge located on each side adjacent the first edge of the at least one packaged semiconductor die for receiving the curved portion of the hooking portion of each J-shaped locking pin of the two J-shaped locking pins attached to the substrate, the at least one packaged semiconductor die having a thickness no wider than the thickness of the hooking portion of each J-shaped locking pin of the two J-shaped locking pins for connecting the at least one packaged semiconductor die to the substrate while allowing removal therefrom and having a plurality of in-line package leads extending along a length of the first edge of the at least one packaged semiconductor die, each lead of the plurality of leads extending downwardly from the at least one packaged semiconductor die, a portion of each of the plurality of leads extending below the at least one packaged semiconductor die and resiliently biasing a portion of each of the plurality of leads against at least one circuit of the plurality of circuits located on the at least one surface of the substrate.