Patent ID: 6897702

Claim:
An integrated circuit comprising: a power supply node; a ground node; a common node; a first p-channel FET comprising a source, gate, and drain, wherein the source and drain of the first p-channel FET are coupled to the power supply node, and wherein the gate of the first p-channel FET is coupled to the common node; a first n-channel FET comprising a source, gate, and drain, wherein the source and drain of the first n-channel FET are coupled to the ground node, and wherein the gate of the first n-channel FET is coupled to the common node; a common node biasing circuit coupled between the power supply and ground nodes, wherein the common node biasing circuit comprises: a pull-up clamp circuit coupled between the power supply node and the common node, wherein the pull-up clamp circuit comprises a diode-connected n-channel FET and three diode-connected p-channel FETs, wherein one of the three diode-connected p-channel FETs is coupled in series between the other two of the three diode-connected p-channel FETs, wherein the three diode-connected p-channel FETs are coupled in series between the power supply node and the diode-connected n-channel FET, and wherein the diode-connected n-channel FET is coupled in series between the three diode-connected p-channel FETs and the common node; a pull-down circuit coupled between the common node and the ground node, wherein the pull-down clamp circuit comprises a pair of diode-connected n-channel FETs and a pair of diode-connected p-channel FETs, wherein the pair of diode-connected p-channel FETs are coupled in series between the common node and the two diode-connected n-channel FETs, and wherein the two diode-connected n-channel FETs are coupled in series between the two diode-connected p-channel FETs and the ground node.