Patent ID: 7791989

Claim:
An arithmetic processing circuit unit to receive a plurality of signals and performing an addition/subtraction operation on the plurality of signals, the arithmetic processing circuit unit comprising: differential signal generating circuits to convert the plurality of signals into a plurality of differential signals; and an operational circuit comprising: a plurality of first transistors each to receive at a respective control electrode thereof a corresponding one of positive signals of the plurality of differential signals from the differential signal generating circuits; a plurality of second transistors each to receive at a respective control electrode thereof a corresponding one of negative signals of the plurality of differential signals, the plurality of second transistors arranged in parallel with the plurality of first transistors; and a filter circuit connected between the first and second transistors to receive, respectively, a positive signal and a negative signal of one differential signal, wherein, the arithmetic processing circuit unit is configured so that, when a subtraction operation is performed on two signals, a first electrode of the first transistor receiving one of the two signals is connected to a first electrode of the second transistor receiving the other of the two signals, and a first electrode of the second transistor receiving the one of the two signals is connected to a first electrode of the first transistor receiving the other of the two signals, and wherein, the arithmetic processing circuit unit is configured so that, when an addition operation is performed on two signals, a first electrode of the first transistor receiving one of the two signals is connected to a first electrode of the first transistor receiving the other of the two signals, and a first electrode of the second transistor receiving the one of the two signals is connected to a first electrode of the second transistor receiving the other of the two signals.