Patent ID: 8375158

Claim:
A memory system comprising: a flash memory device comprising a plurality of memory blocks implementing a plurality of data blocks, a plurality of log blocks, and a plurality of free blocks; and a flash translation layer (FTL) configured to maintain a number of free blocks at least equal to a reference number by converting selected memory blocks among the data and log blocks into free blocks using at least one merge operation during a background period, and further configured to convert selected ones of the free blocks into data and log blocks, respectively, wherein the FTL selects data and log blocks for conversion into free blocks based upon a use frequency of the log blocks, wherein the FTL selects for conversion a first data and log block group before a second data and log block group, the first data and log block group comprises first log blocks of the plurality of log blocks and the second data and log block group comprises second log blocks of the plurality of log blocks, and the first log blocks have a lower use frequency than the second log blocks.