Patent ID: 8194481

Claim:
A semiconductor device, comprising: a main memory unit including a plurality of main cells; an auxiliary memory unit including a plurality of auxiliary cells arranged into rows and columns, each of the auxiliary cells corresponding to a respective set of the main cells; a plurality of wordlines each connected to a respective row of the auxiliary cells; a plurality of bitlines each connected to a respective column of the auxiliary cells; row decoder circuitry for selecting, in a first mode of operation, an individual wordline among the plurality of wordlines and, in a second mode of operation, a group of wordlines within the plurality of wordlines; bitline control circuitry for driving the bitlines to enable writing of auxiliary cells connected to a wordline that has been selected; control logic circuitry for (i) controlling the bitline control circuitry while the row decoder circuitry operates in the second mode of operation so as to set each of the auxiliary cells to a first logic state; (ii) causing input data to be written to selected ones of the main cells; and (iii) controlling the bitline control circuitry while the row decoder circuitry operates in the first mode of operation so as to set those auxiliary cells corresponding to the selected ones of the main cells to a second logic state different from the first logic state.