Patent ID: 7366803

Claim:
A circuit for buffering data received in a first clock domain and output in a second clock domain, said circuit comprising: a first circuit coupled to receive a stream of data blocks using a first clock signal, said first circuit removing idle data blocks from said stream of data blocks to create a first modified data stream, wherein said first circuit removes an ordered set of a pair of consecutive ordered sets of said stream of data; a memory device coupled to receive said first modified data stream and to selectively output data blocks of said first modified data stream; a second circuit coupled to said memory device to generate a second modified data stream using a second clock signal, said second modified data stream comprising said data blocks of said first modified data stream and idle data blocks inserted among said data blocks of said first modified data stream; and wherein said first circuit removes said idle signal blocks and said ordered set of said pair of consecutive ordered sets when said memory device is not near empty, wherein said pair of consecutive ordered comprises a Sequence ordered-set.