Patent ID: 7781290

Claim:
A method of manufacturing a complementary metal-oxide semiconductor (CMOS) device, comprising: forming a preliminary layer for forming a channel on a semiconductor substrate in which an NMOS region and a PMOS region are defined, the preliminary layer including a sacrificial layer and a thin body channel layer; patterning the preliminary layer for forming the channel to form a preliminary pattern for forming an NMOS channel in the NMOS region and a preliminary pattern for forming a PMOS channel in the PMOS region; anisotropically etching the ends of the preliminary patterns for forming the NMOS and PMOS channels until a surface of the semiconductor substrate is exposed to form a groove, thereby forming a pattern for forming the NMOS channel in the NMOS region and a pattern for forming the PMOS channel in the PMOS region; trimming the patterns for forming the NMOS and PMOS channels; forming an NMOS source/drain region and a PMOS source/drain region by filling the groove with a material layer after trimming the patterns for forming the NMOS and PMOS channels; forming an NMOS thin body channel and a PMOS thin body channel by removing a residual sacrificial layer of the patterns for forming the NMOS and PMOS thin body channels; forming an NMOS insulating layer surrounding the NMOS thin body channel on a surface of the NMOS thin body channel when the PMOS region is masked; forming an NMOS metal gate pattern on a surface of and surrounding the NMOS insulating layer; forming a PMOS insulating layer surrounding the PMOS thin body channel on a surface of the PMOS thin body channel when the NMOS region is masked; and forming a PMOS metal gate pattern on a surface of and surrounding the PMOS insulating layer; wherein the NMOS insulating layer comprises a silicon oxide layer and the PMOS insulating layer comprises an electron-trapping layer, the NMOS insulating layer comprises a hole trapping dielectric layer and the PMOS insulating layer comprises a silicon oxide layer, or the NMOS insulating layer comprises a hole-trapping dielectric layer and the PMOS insulating layer comprises an electron-trapping dielectric layer; and wherein, in trimming the patterns for forming the NMOS and PMOS channels, the sacrificial layer and the thin body channel layer of the patterns for forming the NMOS and PMOS channels are simultaneously etched.