Patent ID: 8436635

Claim:
A semiconductor wafer comprising: a plurality of die areas having active circuitry comprising a plurality of circuit elements; a plurality of scribe line areas between said plurality of die areas; at least one test module (TM) formed in or on said plurality of scribe line areas, each TM including a plurality of test transistors arranged in a plurality of rows and a plurality of columns, each of said plurality of test transistors including at least four terminals comprising a source (S), a drain (D), a gate (G) and a body (B), said TM comprising a plurality of pads, said plurality of pads comprising: a source pad coupled to the source terminal of each of said plurality of test transistors; a global body pad coupled to the body terminal of each of said plurality of test transistors; a plurality of locally shared gate pads, wherein each gate pad is coupled to the gate terminal of all of said plurality of test transistors in a respective one of said plurality of columns; a plurality of locally shared drain pads, wherein each drain pad is coupled to a drain terminal of all of said plurality of test transistors in a respective one of said plurality of rows.