Patent ID: 8139704

Claim:
A variable bandwidth phase lock loop (PLL), comprising: a phase offset accumulator configured to: provide a phase compensation signal that is subtracted from a phase error, the phase error being derived from an input clock reference (ICR) value and a recovered clock reference (RCR) value; and add a loop filter output to the phase offset accumulator in response to a renormalization signal; a loop filter configured to: receive a signal corresponding to the difference in the phase error and the phase compensation signal; and provide the loop filter output to (i) the phase offset accumulator, (ii) a programmable user gain, and (iii) a phase error summing component; a voltage controlled oscillator (VCO) offset accumulator configured to: provide a voltage offset signal that is added to a voltage output by the user gain; and add the voltage output by the user gain to the VCO offset accumulator in response to the renormalization signal; wherein the phase error summing component is configured to add the phase compensation signal and the loop filter output to provide a filtered phase error signal; wherein the RCR value is generated based on a sum of the voltage offset signal and voltage output by the user gain.