Patent ID: 7087493

Claim:
A method of forming a memory circuit comprising a plurality of six transistor memory cells, comprising the steps for each of the six transistor memory cells of: forming a first inverter having an input and an output, and comprising: a first transistor forming a first drive transistor comprising first and second source/drain regions and a gate; a second transistor forming a first pull-up transistor comprising first and second source/drain regions and a gate; wherein the output of the first inverter is coupled to the first source/drain region of the first drive transistor and to the first source/drain region of the first pull up transistor; forming a second inverter having an input and an output, and comprising: a third transistor forming a second drive transistor comprising first and second source/drain regions and a gate; a fourth transistor forming a second pull-up transistor comprising first and second source/drain regions and a gate; wherein the output of the second inverter is coupled to the second source/drain region of the second drive transistor and to the first source/drain region of the second pull up transistor; forming a fifth transistor forming a first access transistor having a gate and having a first source/drain region coupled to the output of the first inverter and a second source/drain region for communicating to a first bit line; forming a sixth transistor forming a second access transistor having a gate and having a first source/drain region coupled to the output of the second inverter and a second source/drain region for communicating to a second bit line; forming at least one insulating layer in a position relative to the first through sixth transistors; applying a first mask to the at least one insulating layer to form a plurality of vias through the at least one insulating layer; forming a first conducting layer comprising a plurality of conducting plugs in the plurality of vias, wherein the plurality of conducting plugs comprise: a first conducting plug coupled to the first source/drain region of the first drive transistor; a second conducting plug coupled to the first source/drain region of the first pull-up transistor and to the gate of the second drive transistor and to the gate of the second pull-up transistor; a third conducting plug coupled to the first source/drain region of the second drive transistor; and a fourth conducting plug coupled to the first source/drain region of the second pull-up transistor and to the gate of the first drive transistor and to the gate of the first pull-up transistor; forming a second conducting layer comprising a plurality of conducting elements, wherein the plurality of conducting elements comprise: a first conducting element coupled to and physically contacting the first conducting plug and coupled to and physically contacting the second conducting plug; and a second conducting element coupled to and physically contacting the third conducting plug and coupled to and physically contacting the fourth conducting plug.