Patent ID: 7181564

Claim:
A data processing apparatus comprising: a CPU for executing a program for performing data processing; a rewritable non-volatile memory for storing data that are to be referred to at the time of the data processing; a RAM for storing data in a rewrite target region when rewriting the data stored in the non-volatile memory while the CPU is in operation; an external interface circuit for interfacing transfer of a control signal and data when the non-volatile memory is accessed from outside the data processing apparatus while the CPU is in operation; and a fetch bus interface circuit that is connected between the CPU, the non-volatile memory, and the external interface circuit, the fetch bus interface circuit having a data holding circuit therein, the data holding circuit being separate from the CPU and capable of temporarily holding data which are read out from the non-volatile memory when operation of the CPU is suspended prior to the non-volatile memory access being completed, and the holding circuit providing the data temporarily held therein to the CPU in response to resumption of the operation of the CPU and, thereafter, providing data read out from the memory to the CPU without temporarily holding the data therein, and controls, according to the control signal, a switching of a fetch bus between the non-volatile memory and the RAM when the non-volatile memory is accessed from outside the data processing apparatus while the CPU is in operation.