Patent ID: 8411487

Claim:
A semiconductor memory device comprising: a memory cell array formed of memory cells, a plurality of which is arranged respectively in a row direction and a column direction, each memory cell including a variable resistance element in which an electrode is supported at each of two terminals of a variable resistor, a resistance state is defined by a resistance property between the two terminals and transitions between two or more different resistance states by applying electric stress between the two terminals, and one resistance state after the transition is used for storing information, wherein the memory cell array is divided into a plurality of subbanks, each of the subbanks comprises: common word lines each connecting the memory cells in the same row, and common bit lines each connecting the memory cells in the same column; a row decoder that applies a voltage to the word lines of the subbank; and a column decoder that applies a voltage to the bit lines of the subbank, in a writing of selected memory cells in the memory cell array, one of an erasing action and a programming action is performed on each of the selected memory cells, in the erasing action, an erasing voltage pulse for transitioning the resistance state of the variable resistance element of the memory cell to an erased state having a lowest resistance value is applied to the selected memory cell, regardless of the resistance state of the variable resistance element of the selected memory cell, and in the programming action, the erasing voltage pulse is applied to the selected memory cell, and a first programming voltage pulse for transitioning the resistance state of the variable resistance element of the memory cell from the erased state to a predetermined resistance state is applied to the selected memory cell, regardless of the resistance state of the variable resistance element of the selected memory cell, and the semiconductor memory device further comprises a control circuit that controls an application of the first programming voltage pulse in the programming action to one of two memory cells, and an application of the erasing voltage pulse in the erasing action or the programming action to the other of the two memory cells so that the applications are performed in an identical action cycle with respect to the two memory cells, which belong to the different subbanks, of the selected memory cells.