Patent ID: 8330206

Claim:
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of memory elements formed on the semiconductor substrate in rows and columns; a plurality of bit lines selectively connected with the plurality of memory elements in the respective columns; and a plurality of word lines connected with the plurality of memory elements in the respective rows, each of the plurality of memory elements including: a first gate insulating film formed on the semiconductor substrate, a charge accumulation layer formed on the first gate insulating film, a second gate insulating film formed on the charge accumulation layer, and a control electrode formed on the second gate insulating film; the second gate insulating film and the control electrode extending across the plurality of memory elements in a direction transverse to the bit lines in a cross section along the direction transverse to the bit lines, wherein an upper corner portion of the charge accumulation layer in the cross section along the direction transverse to the bit lines has a curved surface, and the upper corner portion is situated above the first gate insulating film.