Patent ID: 8164120

Claim:
A semiconductor device comprising: a semiconductor substrate having an element isolation insulating film and a gate insulating film for MOS field effect transistors, respectively formed on one surface of the semiconductor substrate; a capacitor formed on the element isolation insulating film, the capacitor having a lamination structure stacking a lower electrode, a capacitor insulating film and an upper electrode in this order on the element isolation insulating film, and the upper electrode including a first upper electrode formed on the capacitor insulating film and made of a same material as a material of the lower electrode and a second upper electrode formed on the first upper electrode and made of a material different from the material of the first upper electrode; a MOS field effect transistor having a gate electrode formed on the gate insulating film, the gate electrode including a first gate electrode made of the same material as the material of the lower electrode and a second gate electrode formed on the first gate electrode and made of a same material as a material of the second upper electrode, a thickness of the first gate electrode being approximately equal to a thickness of the lower electrode, and a thickness of the second gate electrode being approximately equal to a thickness of the second upper electrode; and a first fuse formed on the element isolation insulating film, the first fuse including a first soluble layer made of the same material as the material of the lower electrode and a second soluble layer formed on the first soluble layer and made of the same material as the material of the second upper electrode, a thickness of the first soluble layer being approximately equal to the thickness of the lower electrode, and a thickness of the second soluble layer being approximately equal to the thickness of the second upper electrode.