Patent ID: 8289062

Claim:
An analog delay line system comprising: an analog delay line comprising a plurality of analog delay elements, individual ones of the plurality of analog delay elements configured to receive a bias signal and a respective periodic input signal and delay the respective periodic input signal to provide a periodic output signal to generate a respective delayed periodic output signal, wherein the respective periodic input signal of each one of the delay elements coupled to an output of another one of the delay elements comprises a respective one of the delayed periodic output signals, and wherein an amount of delay is based, at least in part, on the bias signal; frequency measurement circuitry coupled to at least a portion of the analog delay line and configured to measure a frequency of at least one of said respective periodic input signals, the frequency measurement circuitry configured to provide a control signal based, at least in part, on the frequency of the at least one of said respective periodic input signals, wherein the frequency measurement circuitry comprises a counter configured to generate a signal corresponding to a number of periods elapsed between an input and an output of the analog delay line; and bias control circuitry configured to receive the control signal and further configured to generate the bias signal based, at least in part, on the frequency of the at least one of said respective periodic input signals.