Patent ID: 7739529

Claim:
A device comprising: a receiver for receiving a repeated transmission that comprises a forward link packet (FLP), the FLP including a FLP data and a postamble, and the postamble including a series of high-low transitions; and a microprocessor coupled to the receiver, the microprocessor periodically partially awakening to determine whether the transmission is likely a FLP based at least in part on the receiver having received a predetermined number of transitions of the repeated transmission, with the received transitions including transitions within the postamble; and a transmitter through which the microprocessor is configured to transmit a reverse link packet (RLP) in response to the FLP; wherein the postamble achieves at least one of the following: shortens the amount of time that the transmitter is on by enabling the microprocessor to turn on the transmitter only after the microprocesser has read the FLP data to determine whether a RLP is called for; increases the amount of time between the FLP data and the RLP, thereby allowing the microprocessor enough time to stabilize the transmitter on an appropriate return link channel; shortens the amount of the time that the receiver needs to be on to sense the existence of the transmission; increases the amount of time that a phase locked loop (PLL) of the transmitter has to lock onto an appropriate return link channel; or shortens the amount of time that a PLL of the transmitter is on by enabling a PLL of the transmitter to be turned on after the microprocesser has read the FLP data to determine whether a RLP is called for.