Patent ID: 7427551

Claim:
A method of forming a semiconductor resistor structure comprising the steps of: a) providing an interlevel dielectric material structure; b) etching a trough structure in said dielectric structure; c) depositing a layer of conductive material having lateral and vertical portions in said trough structure; d) depositing a layer of insulator material having lateral and vertical portions above said layer of conductive material in said trough structure; e) alternating deposition of conductive and insulator material layers according to steps c) and d) to form said resistor structure having properties tailored according to types and thicknesses of said conductive and insulator materials; f) planarizing a surface of said resistor structure; and, g) forming a via structure above said planarized surface to connect a top surface of each said vertical portions of said conductive film layers of said resistor structure to an adjacent wire level.