Patent ID: 7769095

Claim:
An apparatus for timing recovery in an OFDM system comprising: a third order phase lock loop (PLL) comprising: a Fast Fourier Transform (FFT) stage for receiving a number of input signals in the time domain and transforming one or more of the number of input signals to the frequency domain; one or more of the number of input signals having an associated sampling frequency and phase and comprising a number of symbols, the Fast Fourier Transform stage being arranged to apply a Fast Fourier Transform process to one or more of the number of input signals, the Fast Fourier transform process having an associated window of operation; a phase rotation stage couplable to an output of the Fast Fourier Transform stage for adjusting the phase of one or more of the one or more transformed signals; a frequency offset estimation stage couplable to an output of the phase rotation stage for estimating frequency offset between sampled signals to provide one or more frequency offset estimates; a first accumulator couplable to an output of the frequency offset estimation stage for accumulating the one or more frequency offset estimates; a low pass filter couplable to an output of the first accumulator for stabilizing the phase lock loop; a second accumulator couplable to an output of the low pass filter for accumulating outputs of the low pass filter; the second accumulator being arranged to control phase rotation in the phase rotation stage; and a controller stage for controlling timing associated with the window of operation of the Fast Fourier Transform process applied by the Fast Fourier Transform stage, the second accumulator being arranged to control the controller stage; the phase rotation being arranged to generate a time recovered output signal.