Patent ID: 8487452

Claim:
A semiconductor package, comprising: a substrate; a first semiconductor chip stacked on the substrate and having a plurality of chip pads disposed on an upper surface of the first semiconductor chip; and a second semiconductor chip stacked on the first surface of the first semiconductor chip, having a lower surface to face the upper surface of the second semiconductor chip and having a plurality of chip pads disposed on an upper surface of the second semiconductor chip; and an overlap area and a non-overlap area formed between the first semiconductor chip and the second semiconductor chip; and wherein the chip pads of the second semiconductor chip are disposed on the overlap area and the non-overlap areas, wherein the chip pads of the second semiconductor chip that disposed on the overlap area are electrically connected to the chip pads of the first semiconductor chip, and wherein the chip pads of the second semiconductor chip that disposed on the non-overlap areas are not electrically connected to the chip pads of the first semiconductor chip.