Patent ID: 7405985

Claim:
A method of operating an integrated circuit comprising: providing a plurality of memory cells arranged into a plurality of columns; providing a plurality of latches to hold data associated with a corresponding one of said columns; providing a shift register having a plurality of stages with an output coupled to an enable input of a corresponding latch; determining that one or more of said columns each includes a defective memory cell; fusing out the shift register stages corresponding to the columns determined to include a defective memory cell; loading a strobe bit into a first stage of the shift register to enable coupling of the corresponding first latch to an input line; and clocking the shift register to advance the strobe bit from the first stage of the shift register to the subsequent stages to enable coupling of the corresponding subsequent latches to the input line, wherein when a stage is fused out the strobe bit is advanced through the fused out stage without being clocked and without the fused out stage enabling the corresponding latch to an input line.