Patent ID: 8769211

Claim:
An apparatus comprising: a first and second processing core, wherein the first and second processing cores to each process a first and second thread respectively; a first and second distributed cache slice to store data for either or both of the first and second processing cores; and a first and second core interface co-located with the first and second processing cores respectively, each core interface to maintain a finite state machine (FSM) to be executed in response to receiving a request from a thread of its co-located processing core to monitor a cache line in the distributed cache, wherein the FSM comprises: a wait state to record a request from a co-located core's thread to monitor a specific cache line, a monitor state to monitor for a pseudo-snoop of the cache line being monitored, wherein the pseudo-snoop activates the FSM, but is not sent to the core that requested the monitoring of the cache line, and an information state to send a wakeup event to the thread that requested the monitoring of the cache line.