Patent ID: 7303964

Claim:
A method of fabricating shallow isolation trench structures in a wafer, comprising: forming a multi-layer dielectric-charge trapping-dielectric stack over a substrate of the wafer; removing the multi-layer dielectric-charge trapping-dielectric stack in a periphery region of the wafer, thereby defining a multi-layer dielectric-charge trapping-dielectric stack in a core region of the wafer; forming a gate dielectric layer over the periphery region of the substrate; forming a first polysilicon layer over the multi-layer dielectric-charge trapping-dielectric stack in the core region and the gate dielectric in the periphery region; concurrently forming an isolation trench in the substrate, through the first polysilicon layer and the multi-layer dielectric-charge trapping-dielectric stack in the core region and through the first polysilicon layer and the gate dielectric layer in the periphery region, thereby defining isolation trenches; filling the isolation trenches with a dielectric material; and forming a second polysilicon layer over the first polysilicon layer and the filled trenches.