Patent ID: 8166331

Claim:
A computer system, comprising: a power supply to output necessary voltages and a first power good signal to the computer system, the necessary voltages comprising a first system voltage, the first power good signal being delayed for a first time to be effective after voltages of the first system voltage being risen to a rated value; a south bridge chip; and a timing control circuit comprising a delay module to receive and delay the first power good signal; wherein the timing control circuit is operable to generate a second power good signal to the south bridge chip according to the first power good signal, the second power good signal is generated after the first power good signal being delayed for a second time by the delay module, the first power good signal indicating that the necessary voltages provided to the computer system are ready in response to being effective, the second power good signal indicating that necessary input powers of the south bridge chip are ready in response to being effective; the timing control circuit further comprises a processing module and a two-stage voltage level switching module, the processing module is connected to the delay module to output a transistor-transistor logic (TTL) level signal according to the first power good signal delayed by the delay module, the two-stage voltage level switching module receives the TTL level signal and outputs the second power good signal, the second power good signal is at a same TTL level as the TTL level signal in response to the computer system not being triggered off.