Patent ID: 7433262

Claim:
A method for delaying an input control signal, comprising: receiving an input clock signal; determining a number of cascaded delay elements required to generate a first delay equal to a target amount of the period of the input clock signal; receiving an input data signal having an edge that was generated at the same time as an edge of the input control signal; determining a fraction number equal to the number of cascaded delay elements needed to generate a second delay for one of the input data signal and the input control signal equal to an amount of time necessary to align the edge of the input data signal with the edge of the input control signal, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the input clock signal; delaying the input control signal by an amount of time realized by the number of cascaded delay elements to realize the first delay altered by the fraction number of delay elements.