Patent ID: 7920019

Claim:
A microprocessor, comprising: a first substrate bias rail which provides a first bias voltage during a first operating mode and a second substrate bias rail providing a second bias voltage during said first operating mode; a first supply node providing a core voltage and a second supply node providing reference voltage; wherein said first bias voltage is provided at a positive voltage offset relative to said core voltage and wherein said second bias voltage is provided at a negative voltage offset relative to said reference voltage during said first operating mode; a plurality of clamp devices comprising a plurality of P-channel devices coupled between said first substrate bias rail and said first supply node and a plurality of N-channel devices coupled between said second substrate bias rail and said second supply node; a P-type level shift circuit having an input coupled to a first output of a control logic and an output coupled to a gate of at least one of said plurality of P-channel devices; an N-type level shift circuit having an input coupled to a second output of said control logic and an output coupled to a gate of at least one of said plurality of N-channel devices; a P-type buffer having an input coupled to said output of said P-type level shift circuit and an output coupled to at least one of said plurality of P-channel devices, wherein said P-type buffer switches its output between said reference voltage and said first bias voltage; an N-type buffer having an input coupled to said output of said N-type level shift circuit and an output coupled to at least one of said plurality of N-channel devices, wherein said N-type buffer switches its output between said core voltage and said second bias voltage; said control logic comprising said first output providing a first control signal for controlling said plurality of P-channel devices and said second output for providing a second control signal for controlling said plurality of N-channel devices, wherein said control logic turns on said plurality of clamp devices to clamp said first substrate bias rail to said first supply node and to clamp said second substrate bias rail to said second supply node during a second operating mode and which turns off said plurality of clamp devices during said first operating mode; and wherein said control logic switches said first control signal and said second control signal between said reference voltage and said core voltage, wherein said P-type level shift circuit switches its output between said reference voltage and said first bias voltage in response to said first control signal, and wherein said N-type level shift circuit switches its output between said core voltage and said second bias voltage in response to said second control signal.