Patent ID: 7502970

Claim:
A memory device comprising: a data storage section; a comparison section which compares in write processing, for data being target of the write processing, a state before the data is stored in the data storage section with a state of the data which is stored in the data storage section and read out from the data storage section, and compares in erase processing, for a data block being target of erase processing of the data storage section, an actual state of the data block after the erase processing is executed with a theoretical data state after the erase processing is executed; a section which obtains a first number of errors which is the number of bits which do not coincide or the number of error byte units in which incoincidence occurs for the write processing, and obtains a second number of errors which is the number of bits which do not coincide or the number of error byte units in which incoincidence occurs for the erase processing on the basis of a comparison result from the comparison section; and a section which returns the first number of errors to a host device for the write processing, and returns the second number of errors to the host device for the erase processing.