Patent ID: 7682918

Claim:
A process for forming a device with an MOS ESD protection transistor, said process comprising: forming spaced apart surface isolation regions in a substrate of a first polarity type; forming an insulated gate between the spaced apart surface isolation regions; heterodoping dopants of the first polarity type into the entirety of a surface region that is inside a closed figure and only inside said closed figure, and dopants of a second polarity type opposite to the first polarity type into the entirety of said surface region inside said closed figure and only inside said closed figure, said surface region being between, and spaced apart from, the gate and the surface isolation region closest to the gate to form p-n junctions having retrograde doping profiles beneath the substrate surface for lowering the breakdown voltage within the heterodoped portions in order to direct a substantial portion of the breakdown current below the surface of the substrate and into the body of the substrate between the heterodoped regions; and forming source and drain regions in the substrate surface on opposite sides of the gate such that said closed figure extends vertically through the source and drain regions and into the substrate of the formed device.