Patent ID: 8756394

Claim:
A memory control system, comprising: a memory device controller configured to interface with one or more memory devices, wherein the memory device controller is coupled to one or more of the memory devices and configured for data communication with the one or more memory devices via a memory bus; control registers configured to maintain control register values that are adjustable to tune memory bus timing margins in multi-dimensions, wherein the memory bus timing margins are tunable for implementation with the one or more memory devices; and a memory timing tuner configured to adjust the control register values to tune the memory bus timing margins in the multi-dimensions, the adjust at least comprising: adjust, for a first dimension of the multi-dimensions, the memory bus timing margin in a positive direction of the first dimension from an initial starting point until a first timing fail is determined, the initial starting point corresponding to a passing memory bus timing; adjust, for the first dimension of the multi-dimensions, the memory bus timing margin in a negative direction of the first dimension from the initial starting point until a second timing fail is determined; and determine, for the first dimension of the multi-dimensions, a center point between the first and second timing fails as an optimal memory bus timing of the first dimension.