Patent ID: 8039336

Claim:
A method of fabricating a semiconductor device, comprising the steps of: forming a first insulation film on a semiconductor substrate; forming a first silicon layer on said first insulation film; forming a mask film over said first silicon layer; etching said first silicon layer, said first insulation film and said semiconductor substrate using said mask film as a mask to provide a trench; filling said trench with a second insulation film to provide an isolating insulation film; removing said mask film; forming a second silicon layer on said first silicon layer and said isolating insulation film; and patterning said second silicon layer, first silicon layer and first insulation film; wherein in the step of forming said first silicon layer, an undoped silicon layer is formed as said first silicon layer, and in the step of forming said second silicon layer, a doped silicon layer is formed by depositing a silicon layer having a predetermined impurity concentration as said second silicon layer, and an impurity included in said second silicon layer is thermally diffused into said first silicon layer through a subsequent thermal process corresponding to annealing at 900° C. or more, so that a distribution of said impurity's concentration throughout the first and second polysilicon layers has an absolute maximum value located in said first polysilicon layer, and said distribution substantially monotonously increases from said second polysilicon layer to said absolute maximum value and decreases from said absolute maximum value toward said first insulation film and said first silicon layer is smaller in crystal grain size than said second silicon layer.