Patent ID: 7118995

Claim:
A method for determining a fabrication condition for a semiconductor structure design, the method comprising the steps of: (a) providing a relationship between a yield of the semiconductor structure design, a deposition temperature, and a precursor flow rate, wherein the yield of the semiconductor structure design is a function of a percentage of satisfactory structures of a plurality of semiconductor structures formed according to the semiconductor structure design in all the plurality of semiconductor structures, and wherein the semiconductor structure design comprises: (i) a first region and a second region, wherein the first region and the second region are in direct physical contact with each other via a first common interface surface, and (ii) a third region and a fourth region being on top of the first and second regions, respectively, wherein the third and fourth regions are grown by a step of depositing a growth material simultaneously on top of the first and second regions such that a second common interface surface between the third and fourth region grows from the first common interface surface, wherein the first and third regions comprise a same material and have single-crystal atoms arrangement, wherein the first region has a different atoms arrangement than the fourth region, and wherein the step of depositing the growth material is performed under the deposition temperature and the precursor flow rate; (b) selecting a target yield of the yield for the semiconductor structure design; and (c) determining a desired deposition temperature and a desired precursor flow rate based on the target yield and the relationship.