Patent ID: 7849242

Claim:
A flash memory device comprising: a flash memory mappable to an address space of a host that is separate from the flash memory device; a device connector for facilitating communication between the host and the flash memory device, the device connector configured to connect to at least one pair of differential, serial buses, wherein the device connector comprises: R+ and R− pins connected to one differential, serial bus; and T+ and T− pins connected to another differential, serial bus; and a flash memory controller coupled between the flash memory and the device connector, wherein the flash memory controller is configured to extract transaction packets from signals sent by the host, wherein the controller is further configured to respond to each transaction packet, which includes a header field and a data payload field, wherein the data payload field of a first transaction packet of an operation to be performed on the flash memory includes a command word setting relating to the operation, and wherein the command word setting includes a command word signature that indicates the data payload field provides the command word setting instead of a data payload.