Patent ID: 7332743

Claim:
A thin film transistor array panel, comprising: an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer covering the gate line; a data line formed on the gate insulating layer; a lower passivation layer covering the data line; an upper passivation layer formed on the lower passivation layer and comprising an organic insulating material; and a pixel electrode formed on the upper passivation layer, wherein the gate insulating layer, the lower passivation layer, and the pixel electrode satisfy the following condition equations: 4( d G n G +d P n P )=which is an even multiple of a wavelength of light; and 4 d I n I =which is an even multiple of the wavelength, and, wherein the thicknesses of the gate insulating layer, the lower passivation layer, and the pixel electrode are represented as d G , d P , and d I , respectively, and the refraction index of the gate insulating layer, the passivation layer, and the pixel electrode are represented as n G , n p , and n I , respectively.