Patent ID: 7022574

Claim:
A method of manufacturing a semiconductor device comprising at least first and second MOS transistors, said method comprising: (a) providing a semiconductor substrate having at least first and second active regions of a first conductivity type and at least third and fourth active regions of a second conductivity type opposite to said first conductivity type; (b) forming a gate oxide layer having a first thickness onto at least said first, second, third and fourth active regions; (c) forming an electrode layer of non-doped polysilicon onto said gate oxide layer; (d) patterning said electrode layer to form first, second, third and fourth gate electrodes onto said first, second, third and fourth active regions, respectively; (e) doping said first active region and said first gate electrode with an impurity of said second conductivity type to form a first transistor driven at a first voltage level, said first gate electrode being doped at a first concentration; (f) doping said second active region and said second gate electrode with an impurity of said second conductivity type to form a second transistor to be driven at a second voltage level lower than said first voltage level, said second gate electrode being doped at a second concentration higher than said first concentration; (g) doping said third active region and said third gate electrode with an impurity of said first conductivity type to form a third transistor to be driven at said first voltage level, said third gate electrode being doped at a third concentration; and (h) doping said fourth active region and said fourth gate electrode with an impurity of said first conductivity type to form a fourth transistor to be driven at said second voltage level, said fourth gate electrode being doped at a fourth concentration higher than said third concentration.