Patent ID: 8906775

Claim:
A method for fabricating a semiconductor device, comprising: forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate; forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein; bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer; and separating the second semiconductor substrate from the bonded second semiconductor wafer, wherein, in the forming of the second semiconductor wafer, forming of the structures including the pillar and the bit lines stacked therein comprises: stacking a first silicon layer and a second silicon layer on the second semiconductor substrate; stacking a conductive layer and a hard mask layer on the second silicon layer; forming the bit lines by etching the hard mask layer and the conductive layer; etching the second silicon layer and the first silicon layer below the bit lines; forming a spacer at sidewalls of the etched second silicon layer, the etched first silicon layer and the bit lines; etching the second semiconductor substrate by a predetermined depth using the spacer as an etch barrier; and forming a third silicon layer by implanting ions into the etched second semiconductor substrate.