Patent ID: 7495507

Claim:
A circuit for generating bias voltages comprising: an input transistor configured to receive a reference current; at least one bias branch, configured to generate the bias voltages, including: a first load; a second load that is coupled in serial with the first load; and a mirroring transistor configured to form a current mirror with the input transistor and configured to provide the first and second loads with a mirror current that is dependent on the reference current, wherein the bias voltages are respectively output from one or more of a junction of the first load and the mirroring transistor and a junction of the first load and the second load; and a reference current generating circuit for generating the reference current, including: a first current mirror configured to current-mirror based on a second current, so as to generate a first current that is substantially in inverse proportion to variation of a power supply voltage; a current compensation unit configured to compensate the first current by removing a variation of the first current corresponding to the variation of the power supply voltage; a second current mirror configured to generate the second current based on the compensated first current, and configured to provide the second current to the first current mirror; and a current output unit configured to output the second current as the reference current.