Patent ID: 7187015

Claim:
An electronic structure comprising: a first conductive layer covering a rectangular area in a first conductive pattern; a first etch-stop layer formed over the first conductive layer; a first via layer formed over the first etch-stop layer in a first via pattern, a second conductive layer formed over the first via layer in a second conductive pattern; a second etch-stop layer formed over the second conductive layer; a second via layer formed over the second etch-stop layer in a second via pattern; a third conductive layer formed over the second via layer in a third conductive pattern; a third etch-stop layer formed over the third conductive layer; a third via layer formed over the third etch-stop layer in a third via pattern; a fourth conductive layer formed over the third via layer in a fourth conductive pattern; a fourth etch-stop layer formed over the fourth conductive layer; a fourth via layer formed over the fourth etch-stop layer in a fourth via pattern; a fifth conductive layer formed over the fourth via layer in a fifth conductive pattern; an interlayer dielectric separating segments of the via patterns from one another and, the interlayer dielectric also separating segments of the conductive patterns from one another; a first electrode connected to the fifth conductive layer; and a second electrode connected to the fourth conductive layer, wherein the via layers are formed from conductive material, wherein the via layers cover parts of their underlying conductive layer and leave other parts covered by the etch-stop layer, wherein the via layers are connected to underlying and overlying conductive layers where the via pattern and the underlying and overlying conductive patterns intersect, wherein the conductive layers are coupled to one another through via layers, and wherein the conductive layers are capacitively coupled to one another through underlying and overlying etch-stop layers.