Patent ID: 8271729

Claim:
A method, in a data processing system, for read- and write-aware cache, the method comprising: receiving a cache access request in a cache controller from a processing unit; if the cache access request is a load resulting in a cache miss, the cache controller loads a cache line of data into a read-often region of a cache, wherein the cache comprises an array of banks and wherein the read-often region comprises banks that are close in proximity to the processing unit; if the cache access request is a store resulting in a cache miss, the cache controller places the cache line of data into a write-often region of the cache, wherein the write-often region comprises banks that are far in proximity to the processing unit; initializing a saturation counter associated with the cache line; receiving a subsequent cache access request in the cache controller for accessing the cache line; responsive to the cache access request being a store at the read-often region or a load at the write-often region, decrementing the saturation counter; responsive to the saturation counter being less than a threshold, determining that the cache line is not in the correct region; and responsive to the cache line not being in the correct region, swapping the cache line with a cache line in the opposite region.