Patent ID: 8627018

Claim:
At a computer system which includes system memory and one or more processors, a method for automatically optimizing a function for execution on one or more parallel accelerator processors, the method comprising: an act of the computer system accessing a function, the function configured to operate over a multi-dimensional matrix of memory cells, the function configured to be invoked as a plurality of threads on at least one parallel accelerator processor, each thread in the plurality of threads configured to operate on a corresponding memory cell; an act of the computer system identifying a layout of the plurality of memory cells of the multi-dimensional matrix of memory cells, including identifying how the memory cells map to global memory at the at least one parallel accelerator processor; an act of the computer system analyzing the function to identify how each of the plurality of threads access the global memory to operate on corresponding memory cells when invoked over the multi-dimensional matrix of memory cells; and an act of the computer system altering the function to utilize a more efficient memory access scheme when accessing the global memory based on the layout of the multi-dimensional matrix and based on analyzing the function, the more efficient memory access scheme increasing coalesced memory access invoked over the multi-dimensional matrix of memory cells, coalesced memory accesses comprising two or more threads accessing the global memory in a single memory transaction.