Patent ID: 7729160

Claim:
A phase-change random access memory (PRAM) comprising: a memory block including a plurality of memory columns corresponding to a same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; a plurality of column address fuse boxes corresponding to the plurality of redundancy memory columns, each of the plurality of column address fuse boxes receiving a column address, for determining whether the plurality of memory columns include at least one repaired memory column, and providing a designation signal for designating the at least one repaired memory column among the plurality of memory columns; a control fuse box providing an input/output repair mode control signal for designating input/output repair modes; an input/output decoder receiving and decoding the designation signal and the input/output repair mode control signal and providing a plurality of path selection signals; and a plurality of path selection circuits receiving the plurality of path selection signals and disabling input/output paths of the at least one repaired memory column and enabling redundancy input/output paths of the at least one redundancy memory column to replace the at least one repaired memory column, wherein the memory columns comprise at least one PRAM cell.