Patent ID: 8804018

Claim:
An apparatus comprising: a pixel region including a plurality of pixel columns; a line memory including a plurality of storage units each configured to store a signal output from corresponding one of the plurality of pixel columns; a first common signal line to which a signal is output from the line memory; a second common signal line to which a signal is output from the line memory; a first block line that is disposed on a first signal path between the line memory and the first common signal line and is configured to receive a signal that has been output from one of an odd-numbered pixel column and an even-numbered pixel column and has been stored in one of the plurality of storage units; a second block line that is disposed on a second signal path between the line memory and the second common signal line and is configured to receive a signal that has been output from the other one of the odd-numbered pixel column and the even-numbered pixel column and has been stored in one of the plurality of storage units; a plurality of first switches that are disposed on a third signal path between the line memory and the first block line and are each configured to control an electric connection between one of the plurality of storage units and the first block line; a plurality of second switches that are disposed on a fourth signal path between the line memory and the second block line and are each configured to control an electric connection between one of the plurality of storage units and the second block line; a plurality of first control lines each configured to supply a first driving pulse for controlling a conductive state of one of the plurality of first switches; a plurality of second control lines each configured to supply a second driving pulse for controlling a conductive state of one of the plurality of second switches; at least one first lead line configured to transmit a signal output from the first block line to the first common signal line; at least one second lead line configured to transmit a signal output from the second block line to the second common signal line; and a scanning unit configured to individually supply driving pulses to the plurality of first control lines and the plurality of second control lines, wherein one of the first or second control lines and one of the first or second lead lines is alternately disposed along a direction parallel to the scanning circuit so that one of the plurality of second control lines, the first lead line, one of the plurality of first control lines, the second lead line, and a different one of the plurality of second control lines are disposed in this order along the direction parallel to the scanning direction of the scanning unit.