Patent ID: 7812438

Claim:
A silicon die comprising: a back-end-of-line (BEOL) layer covered by a stress buffer layer and a plurality of vias formed in the stress buffer layer, said vias extending through said stress buffer layer to said BEOL layer, and a plurality of bond pads for connection with electrical contacts, wherein each bond pad has a geometric center and a perimeter, said bond pads are formed over said vias in one to one correspondence such that a geometric center of each said via is within said perimeter of such corresponding bond pad, and each bond pad is aligned with one of a plurality of horizontal rows, each horizontal row having a centerline on said silicon die, and wherein within a first said horizontal row having a first centerline, said geometric center of at least one bond pad in said first horizontal row is aligned with said first centerline, while said via corresponding with said at least one bond pad is offset from said centerline and said offset is in a direction towards a geometric center of said silicon die.