Patent ID: 8918612

Claim:
An apparatus, comprising: a microprocessor; a non-volatile reprogrammable memory communicatively coupled to the microprocessor via a first communication path, the non-volatile reprogrammable memory for storing data including microprocessor program instructions; and a logical module, communicatively coupled to the non-volatile reprogrammable memory via a second communication path independent from the first communication path, the logical module for securely reading at least a portion of the data stored in the non-volatile reprogrammable memory, for reading a stored integrity value from a source independent from the non-volatile reprogrammable memory and the second communication path, and for verifying the at least a portion of the data stored in the non-volatile reprogrammable memory according to the read at least a portion of the data stored in the non-volatile reprogrammable memory and the read integrity value; wherein the stored integrity value is read from an internal memory of the microprocessor.