Patent ID: 7996650

Claim:
A microprocessor configured to perform a speculative tablewalk, comprising: a translation lookaside buffer (TLB), configured to indicate that a physical page address of a page of memory that a memory access instruction is attempting to access is missing in the TLB; and a tablewalk engine, configured to: determine whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory; perform operations of the tablewalk in an out-of-order manner with respect to the execution of unretired program instructions older than the memory access instruction, while none of the predetermined set of conditions exists; and wait to perform the operations of the tablewalk until the microprocessor has retired all program instructions older than the memory access instruction, when at least one of the predetermined set of conditions exists; wherein to determine whether at least one of the predetermined set of conditions exists, the tablewalk engine is configured to at least determine whether the memory page whose physical page address is missing in the TLB is a global page; wherein to determine whether the memory page whose physical page address is missing in the TLB is a global page, the tablewalk engine is configured to at least determine whether the memory page whose physical page address is missing in the TLB is of a type for which the microprocessor will not invalidate an entry in the TLB for the memory page when the microprocessor performs a task switch.