Patent ID: 7266587

Claim:
A node comprising: an interconnect internal within the node; one or more coherent agents internal within the node coupled to the interconnect, wherein the interconnect supports intranode coherency for transactions on the interconnect with the one or more coherent agents coupled to the interconnect; a plurality of interface circuits, wherein each of the plurality of interface circuits is coupled to receive coherency commands from a respective remote node of a plurality of remote nodes; a memory bridge coupled to the interconnect and configured to maintain internode coherency for transactions between one or more coherent agents coupled to the interconnect and the remote nodes, and to generate additional coherency commands responsive to coherent transactions on the interconnect, the memory bridge including a map circuit to map a node number identifying one of the other nodes as to which of the plurality of interface circuits is used to transmit a respective coherency command to that one other node; and a switch coupled to the plurality of interface circuits and the memory bridge, wherein the switch is configured to selectively couple a selected interface circuit to the memory bridge to transmit the coherency commands to the memory bridge.