Patent ID: 8835997

Claim:
A static random access memory (SRAM) array, comprising: at least one p-type field effect transistor, including: a first gate stack having a first gate dielectric layer having a width, and isolating spacers forming a first gate having a gate length, Lgate and an effective gate length, Leff; and a first source region and first drain region adjacent the first gate stack, wherein the first source and first drain regions are formed from a low extension dose implant performed at a dose between 1×10 10 atoms/cm 2 to 1×10 13 atoms/cm 2 that decreases a difference between Lgate and Leff, such that the first source and first drain regions underlap only the isolating spacers, and that Leff is greater than the width of the first gate dielectric layer, as a result of the low extension dose implant; and at least one n-type field effect transistor, including: a second gate stack having a second gate dielectric layer having the width, and isolating spacers forming a second gate having the gate length, L gate and an second effective gate length; and a second source region and second drain region adjacent the second gate stack, wherein the second source and second drain regions are formed from a high extension dose implant performed at a dose between 1×10 15 and 5×10 15 atoms/cm 2 , such that the second source and second drain regions underlap the isolating spacers and the second gate stack, and that the second effective gate length is less than the width of the second gate dielectric layer, as a result of the high extension dose implant, wherein the p-type field effect transistor has a higher resistance than the n-type field effect transistor.