Patent ID: 8502568

Claim:
An integrated circuit having an input for receiving an input signal to said integrated circuit and a receiver circuit coupled to said input and configured to convert a voltage level of said input signal to an output signal for use within said integrated circuit, said receiver circuit comprising: conduction path circuitry coupled between said input and a first node and configured to provide a conduction path between said input and said first node; and buffer circuitry coupled between said first node and an output for outputting said output signal; wherein said conduction path circuitry comprises a first PMOS transistor and a second transistor connected in series between said input and said first node and a first NMOS transistor connected in parallel with said first PMOS transistor and said second transistor between said input and said first node; and said second transistor has a gate input coupled to said output of said buffer circuitry to receive said output signal such that, as said input signal switches from a low potential to a high potential, said output signal driven by said buffer circuitry switches to a control potential that switches said second transistor to a low conductance state thereby blocking a conduction path from said input to said first node via said first PMOS transistor and said second transistor.