Patent ID: 8643422

Claim:
A slicer comprising: a first latch, the first latch comprising: an evaluating transistor configured to receive a first clock signal, the evaluating transistor connectable to a first voltage source; a developing transistor configured to receive a second clock signal, the developing transistor connectable to the first voltage source, wherein the first clock signal is different from the second clock signal; a first input transistor configured to receive a first input; a second input transistor configured to receive a second input, wherein the first and second inputs are complementary signals and the first and second input transistors are connected with the developing transistor; at least one pre-charging transistor configured to receive a third clock signal, the at least one pre-charging transistor connectable to a second voltage source having a voltage level greater than the first voltage source, wherein the at least one pre-charging transistor is connected to a first output node and a second output node; and at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes; a second latch connected to the first and second output nodes and to a third output node; and a buffer connected to the third output node and configured to generate an evaluation output signal.