Patent ID: 7202519

Claim:
A memory device, comprising: a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device; a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line; wherein the first memory cell further includes a first cell capacitor coupled to the first source/drain region of the first access transistor through an extension; wherein the second memory cell further includes a second cell capacitor having a storage node, the storage node and the extension of the first memory cell located side by side; and wherein the second source/drain region of the second access transistor is interposed between the first bit line and the storage node of the second cell capacitor.