Patent ID: 7551495

Claim:
A semiconductor memory device, comprising: a memory cell configured to store data; a storage unit configured to store at least one data pattern; a data output circuit configured to output the stored data during a first type of read operation and configured to output the at least one data pattern during a second type of read operation; and an output control circuit for controlling the data output circuit such that the memory cell is not accessed during read operations of the second type, wherein the output control circuit includes a first logic gate for generating an enable signal in response to an active signal and a read leveling signal; a column command decoder for operating responsive to the enable signal and generating a read signal in response to a read command; a second logic gate for disabling a column selection line in response to the read leveling signal; a delay locked loop circuit for generating a clock signal in response to the enable signal; and a latency circuit for controlling data synchronization with the clock signal so such the output of the data output circuit is synchronized with the clock signal.