Patent ID: 7683688

Claim:
An integrated circuit comprising: at least one clocked latch circuit, said clocked latch circuit comprising: a first stage comprising a latch node positioned between a first pull up device and a first and at least a second pull down device, said first stage operative to receive inputs comprising a data signal, a clock signal and a clocked complement of said data signal, a second stage comprising a second pull up device and a third pull down device having said latch node therebetween, wherein at least one gate of said first pull up device and said first and second pull down device is directly coupled to at least one gate of said second pull up device and said third pull down device, and an output inverter coupled to said latch node, wherein said clocked latch circuit is operable to pull said latch node low under at least one logical combination of said inputs, and pull said latch node high under at least one other logical combination of said inputs, and wherein said first pull down device comprises a first NMOS input transistor operative to receive said data signal, said second pull down device comprises a second NMOS input transistor operative to receive said clock signal, and said first pull up device comprises a first PMOS input transistor operative to receive said clocked complement of said data signal, wherein said latch node is between said second NMOS input transistor and said first PMOS input transistor.