Patent ID: 6999338

Claim:
A semiconductor storage device comprising: a memory cell array including a plurality of SRAM memory cells (SRAM: Static Random Access Memory) arrayed therein; a plurality of word lines configured to select the memory cells; a plurality of complementary pairs of data lines configured to transmit data into and from the memory cells; a first potential line configured to supply a first drive potential to each of the memory cells; a second potential line configured to supply a second drive potential lower than the first drive potential to each of the memory cells; a first additional FET (FET: Field-Effect Transistor) disposed on one potential line of the first and second potential lines, to selectively bring the one potential line into conduction; a selection signal supply line configured to supply a selection signal to a gate terminal of the first additional FET, so as to set the first additional FET in an ON-state, when each of the memory cells is selected; a second additional FET disposed on the one potential line, in parallel with the first additional FET, to selectively bring the one potential line into conduction; and a bias generation circuit configured to generate a bias potential and supply the bias potential to a gate terminal of the second additional FET, wherein the bias potential is generated to reflect one or both of fluctuations in a potential difference between the first and second drive potentials, and variations in threshold voltage of FETs included in a cross-feedback circuit of each of the memory cells.