Patent ID: 8667368

Claim:
A method for outputting a plurality of pages of data from a NAND memory array to a data bus through a data register and a cache register associated with the NAND memory array, comprising: storing NAND memory array data in the data register, the data register being organized in a plurality of portions, and the cache register being organized in a plurality of portions corresponding to the portions of the data register; outputting data from the cache register portions, seamlessly and in alternation; while outputting data from a first one of the cache register portions, providing data to one of the cache register portions other than the first portion from the corresponding portion of the data register and performing an ECC computation thereon; and while outputting data from a second one of the cache register portions, providing data to one of the cache register portions other than the second portion from the corresponding portion of the data register and performing an ECC computation thereon.