Patent ID: 7223624

Claim:
A process of fabricating a micromechanical device comprising: providing a first semiconductor wafer having generally planar horizontal dimensions; forming a recess region in the semiconductor wafer; securing a semiconductor layer to a surface of the wafer opposite the recess region, wherein the semiconductor layer includes a vertical dimension generally perpendicular to the generally planar horizontal dimensions of the first semiconductor wafer and includes a horizontal dimension generally parallel to the generally planar horizontal dimension of the first semiconductor wafer, and wherein the act of securing includes: providing a second wafer with the semiconductor layer formed thereon, forming a recess in the semiconductor layer, securing the semiconductor layer to the first surface of the wafer, and removing the second wafer; forming a suspended structure in the semiconductor layer disposed opposite the recess region, wherein the suspended structure includes a vertical dimension generally parallel to a vertical dimension of the semiconductor layer and includes a horizontal dimension generally parallel to a horizontal dimension of the semiconductor layer; wherein the suspended structure includes a boundary region that is released from other portions of the semiconductor layer except in a flexure region of the boundary region; wherein the suspended structure includes a seismic mass region within the boundary region; wherein the flexure region of the boundary region and released portion of the boundary region are disposed to permit generally rotational movement of the seismic mass about an axis through the flexure region and in a direction generally parallel to the vertical dimension of the semiconductor layer; and wherein a vertical dimension of the flexure region is thin relative to a vertical dimension of the seismic mass region so as to promote such rotational movement in response to an acceleration force applied in a direction generally perpendicular to the horizontal dimension of the semiconductor layer.