Patent ID: 7324362

Claim:
A content addressable memory (CAM) cell circuit, comprising: a stack section that includes a compare circuit that controls at least one impedance path coupled to at least one match line in response to a first compare input and a second compare input, and a configuration circuit that includes a first switching device that couples a first data value line to the first compare input in response to a stored first data value, and a second switching device that couples a second data value line to the first compare input in response to a stored complementary first data value, a third switching device that couples a third data value line to the second compare input in response to a stored second data value, and a fourth switching device that couples a fourth data value line to the second compare input in response to a stored complementary second data value; and pairs of data value lines being driven according to different complementary compare data values in a binary mode of operation, and one pair of data value lines being driven to complementary compare data values and the other pair of value lines being driven to at least one predetermined potential, unrelated to a compare data value, in a ternary mode of operation.