Patent ID: 7366889

Claim:
A cluster processing system, comprising: a first network defined as a hardwired bus including a number of slots into each of which an individual circuit board can be positioned; a plurality of circuit boards each positioned in one of the number of slots of the first network, each of the circuit boards defined to include a plurality of processing nodes, wherein each processing node includes a processor and associated local memory, wherein the first network is defined to extend through each of the plurality of circuit boards so as to connect together each of the plurality of processing nodes within the plurality of circuit boards, wherein the first network is defined to handle communication of control data between the plurality of processing nodes within the plurality of circuit boards; and a second network defined separate from the first network, the second network defined to enable non-control data communication among the plurality of processing nodes within the plurality of circuit boards, the second network defined to include a non-configurable switch on each of the plurality of circuit boards, wherein each non-configurable switch on a given circuit board is hardwired to network connector circuitry at each processing node on the given circuit board.