Patent ID: 7656736

Claim:
A semiconductor device comprising: a plurality of negative voltage supply lines connected in common, a plurality of negative voltage detection circuits provided corresponding to said plurality of negative voltage supply lines, respectively, each providing a first activation signal when a voltage of a corresponding negative voltage supply line is higher than a predetermined negative voltage, a plurality of negative charge supply circuits provided corresponding to said plurality of negative voltage supply lines, respectively, each supplying negative charge to a corresponding negative voltage supply line when said first activation signal is output from a corresponding negative voltage detection circuit, a plurality of memory circuits provided corresponding to said plurality of negative voltage supply lines, respectively, each receiving said negative voltage from a corresponding negative voltage supply line, allowing a data write/read operation independently, and a control circuit rendering a first number of negative voltage detection circuits active among said plurality of negative voltage detection circuits in an active mode, and rendering a second number of negative voltage detection circuits active in a standby mode, said second number lower than said first number.