Patent ID: 7211480

Claim:
A semiconductor device manufacturing method comprising the steps of: (a) forming a stopper layer for chemical mechanical polishing over a surface of a semiconductor substrate; (b) forming an element isolation trench in said stopper layer and said semiconductor substrate; (c) depositing a nitride film covering an inner surface of said trench; (d) depositing a first oxide film through high density plasma CVD, said first oxide film burying at least a lower portion of said trench deposited with said nitride film; (e) washing out said first oxide film and control-etching some of the exposed nitride film over a side wall of said trench by hydrofluoric acid to leave the thinned nitride film having a controlled thickness; (f) depositing a second oxide film by CVD, said second oxide film burying said trench after said washing-out; and (g) removing said oxide films over said stopper layer by chemical mechanical polishing; wherein said step (e) leaves said nitride film having a thickness of 7 nm or thinner in an upper area of said trench.