Patent ID: 8290107

Claim:
A clock data recovery circuit, comprising: a data sampling block that samples a burst data signal with a reference clock having the same frequency as that of the burst data signal; a reference clock generation block that generates the reference clock at a fixed phase difference; a phase comparator that determines a phase difference between the burst data signal and the reference clock according to a result of sampling by the data sampling block; and a phase adjustment control circuit that collects the result of the comparison from the phase comparator and notifies the reference clock generation block of how much the reference clock phase is moved in each fixed phase determination period, wherein the phase adjustment control circuit, upon detecting a phase difference between a burst data signal and a first reference clock in the first phase determination period after beginning receiving of burst data signals, instructs the reference clock generation block to generate a second reference clock of which phase is moved by a first phase moving distance that is N times of the fixed phase difference from the initial phase of the first reference clock, then instructs the reference clock generation block to generate a third reference clock of which phase is further moved by a distance under the first phase moving distance and over the fixed phase difference from the second reference clock in the next and subsequent phase determination periods, and instructs the reference clock generation block to generate a fourth reference clock of which phase is moved by the fixed phase difference from the first reference clock upon detecting a phase difference between the burst data signal and a previous reference clock after the phase moving distance matches with the fixed phase difference.