Patent ID: 7830280

Claim:
A semiconductor device comprising: a scrambler configured to scramble a first parallel data group including at least two N-bit parallel data to generate a second parallel data group including at least two N-bit scrambled parallel data, where N is 2 or an integer greater than 2; and a balance coding block configured to receive the second parallel data group and perform DC balance encoding on each N-bit scrambled parallel data of the second parallel data group to generate M-bit balance codes, where M is an integer greater than N, wherein the balance coding block selectively inverts corresponding N-bit scrambled parallel data based on the number of bits of a first logic level or the number of bits of a second logic level in each N-bit scrambled parallel data and adds a flag bit, the flag bit informs whether the corresponding N-bit scrambled parallel data is inverted or not, to selectively inverted N-bit scrambled parallel data.