Patent ID: 8365025

Claim:
A flash memory comprising: a memory sector with a plurality of flash memory cells; a busy signal output circuit, which is configured to output a busy signal to an external device; a data input buffer, which receives from outside write data to be written into one or more of the plurality of flash memory cells; a plurality of data memory circuits which is configured to memorize n bits to temporarily memorize the write data; and an error correction circuit, which takes m1-bits write data (m1<n) to generate m2-bits check data, and takes m3 bits write data (m1+m2+m3<n) to generate m4 bits check data (m1+m2+m3+m4≦n) after generating m2-bits check data (m1+m2<n), wherein the m2-bits check data is input to said plurality of data memory circuits after the m1-bits write data is input to said plurality of data memory circuits to be memorized temporarily, the m4 bits check data is input to said plurality of data memory circuits after the m3 bits write data is input to said plurality of data memory circuits to be memorized temporarily, and the m1 and m3 bits write data and m2 and the m4 bits check data, which are temporarily memorized in said plurality of data memory circuits, are written in said memory sector after the m4 bits check data is temporarily memorized in said plurality of data memory circuits, and wherein, when said error correction circuit generates the m2-bits check data, the busy signal is output from said busy signal output circuit to the external device.