Patent ID: 7388244

Claim:
A semiconductor device, comprising: at least one trench capacitor that comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in said trench over the first metallic electrode layer, and a second metallic electrode layer located in said trench over the dielectric layer; and at least one field effect transistor (FET) located on said substrate, said at least one FET comprising a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region, wherein the second metallic electrode layer of the trench capacitor is electrically connected to at least one of the source and drain regions of the at least one FET by a metallic region including a metal silicide strap and a non-silicided metal, said non-silicided metal forms a direct contact between the second metallic electrode layer and the metal silicide strap.