Patent ID: 7839170

Claim:
A voltage level shifter circuit for shifting an input signal from a low voltage domain to a high voltage domain, comprising: a NOR gate configured to receive a first intermediate signal at a first input and a second intermediate signal that is a delayed version of the first input at a second input and produce an output for the high voltage domain that is a voltage shifted version of the input signal; a first NMOS transistor that is coupled between the first input of the NOR gate and a ground voltage and configured to disable a direct current leakage path between a high voltage supply of the high voltage domain and the ground voltage when the input signal is at the ground voltage; and a first PMOS transistor that is coupled to the high voltage supply of the high voltage domain and configured to disable the direct current leakage path between the high voltage supply of the high voltage domain and the ground voltage when the input signal is at a low voltage supply of the low voltage domain.