Patent ID: 8530328

Claim:
A method for manufacturing a semiconductor device, comprising: forming a first shallow trench in a substrate; filing the first shallow trench with a material with high stress to form a first trench isolation in the substrate; forming a semiconductor device structure in an active region surrounded by the first shallow trench isolation; depositing an interlayer dielectric layer to cover the substrate, the first shallow trench isolation and the semiconductor device structure; etching the interlayer dielectric layer to form an opening exposing the first shallow trench isolation; completely removing the first shallow trench isolation by etching the first shallow trench isolation through the opening in the interlayer dielectric layer, so as to expose the substrate to form a shallow trench in the substrate; only filling the shallow trench in the substrate and the opening in the interlayer dielectric layer with an insulating material of high stress to form a second shallow trench isolation; and planarizing the insulating material of high stress in the second shallow trench isolation to make the second shallow trench isolation flush with the interlayer dielectric layer.