Patent ID: 7212051

Claim:
A sample-reset loop filter, comprising: a control signal generator including: a phase detector configured to compare the phases of a reference signal and a feedback signal and to generate an up signal and a down signal responsive to the phase comparison; a programmable delay circuit configurable to delay the up and the down signals; a divider circuit configured to respond to the up and down signals to provide a divided clock signal; and a clock generator configured to respond to the divided clock signal to provide hold even and hold odd signals; a first charge pump configured to charge a first pair of input nodes in a complementary fashion responsive to the pulse widths of the up signal and the down signal; a second charge pump configured to charge a second pair of input nodes in a complementary fashion responsive to the pulse widths of the up and down signals; a loop filter having an integration path configured to filter the potentials of the first pair of input nodes to provide an integration current and having a feed-forward path configured to filter the potential of the second pair of input nodes to provide a feed-forward current; and a current-controlled oscillator configured to adjust the frequency of an output signal responsive to the summation of the integration current and the feed-forward current; wherein the feed-forward path includes a switched-capacitor ripple-smoothing filter.