Patent ID: 8652886

Claim:
A method for manufacturing a thin film transistor array substrate for a display panel comprises: forming a gate pattern on a substrate, wherein the gate pattern includes a gate electrode, a plurality of gate lines and a plurality of storage electrode lines; forming a gate insulating film on the gate pattern including the gate electrode, the plurality of gate lines and the plurality of storage electrode lines; forming a source/drain pattern and a semiconductor pattern on the substrate, wherein the source/drain patterns includes a plurality of data lines, a source electrode and a drain electrode; forming a first passivation film, a second passivation film, and a third passivation film successively on the substrate; forming a first photoresist pattern which includes a first portion formed on part of the drain electrode and on a pixel region and a second portion formed on the semiconductor pattern which includes a channel region between the source electrode and the drain electrode, and wherein the second portion of the photoresist pattern has a relatively higher height than the first portion; patterning an exposed portion of the first passivation film, the second passivation film and the third passivation film using the first photoresist pattern; forming a second photoresist pattern by removing the first portion of the first photoresist pattern using an etch-back process; patterning an exposed portion of the third passivation layer around the pixel region using the second photoresist pattern, wherein the patterning of the third passivation film includes over-etching the third passivation film; forming a transparent electrode film on the substrate; and removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern to form a transparent electrode pattern on the second passivation layer.