Patent ID: 6964912

Claim:
A method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate; providing a plurality of trenches in the semiconductor substrate using a first hard mask, which trenches are arranged offset with respect to one another in rows and columns; causing the hard mask to recede by a predetermined distance with respect to a trench wall at a top side of the semiconductor substrate for forming a first hard mask that has been caused to recede; providing an isolation trench structure in the semiconductor substrate using a second hard mask, the isolation trench structure subdividing the first hard mask that has been caused to recede along the rows into strip sections and the strip sections of adjacent rows being arranged offset with respect to one another; the receding process resulting in a reduction of an overlap region between two strip sections of adjacent rows in comparison with an overlap region which would be present without the receding process; removing the second hard mask; and filling and planarizing the isolation trench structure with a filling material using the first hard mask subdivided into the strip sections.