Patent ID: 8020040

Claim:
An information processing apparatus comprising: a plurality of processors comprising a first processor and a second processor; a plurality of memories comprising a first memory and a second memory; and a plurality of devices, at least two error handler program retaining sections which are provided at least to said first memory and said second memory and which retain an error handler program, if an error occurs in one of said memories, said first processor executing the error handler program stored in said first memory, if said first processor has failed to normally complete the error handler program, said second processor executing the error handler program stored in said second memory, if a second error occurs at one of said devices, said first processor sequentially accessing one or more non-extracted devices from which information has not been extracted among said devices in a first scanning order to extract information from each of the non-extracted devices, and the second processor sequentially accessing the non-extracted devices in a second scanning order reverse to the first scanning order to extract information from the non-extracted devices.