Patent ID: 7939914

Claim:
A semiconductor structure, comprising: a substrate comprising an upper silicon layer on a top surface of a buried oxide layer; a pre-metal dielectric layer on a top surface of said upper silicon layer; one or more field effect transistors, each field effect transistor of said one or more field effect transistors comprising first and second source/drains formed in said upper silicon layer, said first and second source/drains extending from a top surface of said upper silicon layer to said top surface of said buried oxide layer, a gate electrode isolated from said upper silicon layer by a gate dielectric layer and metal silicide layers on respective top surfaces of said first and second source/drains and on a top surface of said gate electrode; a first set of two or more wiring levels, each wiring level of said first set of two or more wiring levels comprising electrically conductive wires in a corresponding dielectric layer, a lowermost wiring level of said first set of two or more wiring levels on a top surface of said pre-metal dielectric layer; electrically conductive first contacts, a first contact of said first contacts extending from said top surface of said pre-metal dielectric layer to said metal silicide layer on a first source/drain of a first field effect transistor of said one or more field effect transistors, one or more wires of said lowermost wiring level of said first set of wiring levels in electrical contact with said first contact; electrically conductive second contacts, a second contact of said second contacts extending from a bottom surface of said buried oxide layer through said first source/drain of said first field effect transistor to a bottom surface of said metal silicide layer of said first source/drain of said first field effect transistor; and a second set of two or more wiring levels, each wiring level of said second set of said two or more wiring levels comprising electrically conductive wires in a corresponding dielectric layer, a lowermost wiring level of said second set of two or more wiring levels on said bottom surface of said buried oxide layer, one or more wires of said lowermost wiring level of said second set of wiring levels in electrical contact with said second contact.