Patent ID: 7817464

Claim:
A phase change memory cell, comprising: an interlayer insulating layer formed on a semiconductor substrate; a first electrode and a second electrode disposed on the interlayer insulating layer; a phase change material layer disposed between the first and second electrodes, the phase change material layer being one of an undoped GeBiTe layer having a composition ratio within a range surrounded by four points (A 1 (Ge 21.43 , Bi 16.67 , Te 61.9 ), A 2 (Ge 44.51 , Bi 0.35 , Te 55.14 ), A 3 (Ge 59.33 , Bi 0.5 , Te 40.17 ) and A 4 (Ge 38.71 , Bi 16.13 , Te 45.16 )) represented by coordinates on a triangular composition diagram having vertices of germanium (Ge), bismuth (Bi) and tellurium (Te), a doped GeBiTe layer containing an impurity and having a composition ratio within a range surrounded by four points (D 1 (Ge 10 , Bi 20 , Te 70 ), D 2 (Ge 30 , Bi 0 , Te 70 ), D 3 (Ge 70 , Bi 0 , Te 30 ) and D 4 (Ge 50 , Bi 20 , Te 30 )) represented by coordinates on the triangular composition diagram, and a doped GeTe layer containing an impurity and having a composition ratio corresponding to coordinates on a straight line between the points D 2 and D 3 ; and a bit line disposed on the interlayer insulating layer and electrically connected to the second electrode.