Patent ID: 7685480

Claim:
A content addressable memory (CAM) system, the system comprising: a plurality of CAM arrays having a plurality of rows of CAM cells to store data coupled to wordlines, searchlines, bitlines and matchlines for reading from, writing to, and searching data in the CAM cells; a hit circuit coupled to the matchlines of each of the plurality of CAM arrays, the hit circuit to compare the data stored in the CAM cells against data presented on the wordlines of the CAM array; a fuse circuit to identify a CAM array as being a defective CAM array or a non-defective CAM array; a shift circuit coupled to the each of the plurality of CAM arrays, the shift circuit to shift the wordlines and the matchlines to bypass an identified defective CAM array; and a hit off circuit coupled to the hit circuit, the hit off circuit to turn off the hit circuit for an identified defective CAM array, the hit off circuit further comprising an XNOR circuit utilizing tristate inverters to reduce capacitive coupling noise at the output of the XNOR circuit.