Patent ID: 8543989

Claim:
An apparatus comprising: a storage configured to store a program embedded with a plurality of trace statements, each of the trace statements including an instruction for outputting trace records which identify time when and portions where the trace statements are executed in the program; and a processor configured to: execute the program iteratively while selecting one or two of the trace statements at random for each cycle of executing the program wherein the instruction in the trace statements is activated so as to output a trace record and the instruction in the rest of the trace statements is deactivated so as not to output another trace record, calculate each time intervals required by the program to run through the section between adjacent two trace statements by statistically analyzing the outputted trace records, evaluate a performance of the program on the basis of the time intervals; and generate a set of learning data on the basis of the set of the outputted trace records and identify pairs of learning data of the programs, each of the pairs having the same position or two different positions of the trace statements designated as a start and an end trace statements for one of the each of the pairs and designated as an end and a start trace statements for the other of the each of the pairs of execution cycles, respectively.