Patent ID: 8051122

Claim:
An arithmetic device comprising: a plurality of general-purpose registers which store parallel arithmetic data; a plurality of pattern registers which store a plurality of items of pattern data indicating the rearrangement of the data, wherein the pattern registers store a plurality of items of pattern data using at least one of a smallest bit width, a bit width twice the smallest bit width, and a bit width n times the smallest unit (where n is a power-of-two number) as a unit; a select circuit which selects one of said plurality of items of pattern data stored in said plurality of pattern registers according to specifying data included in an instruction, wherein the select circuit selects an overall pattern register when the parallel arithmetic data is rearranged using the smallest bit width as a unit, selects one of the areas obtained by dividing the pattern register in two when the parallel arithmetic data is rearranged using a rearrangement bit width twice the smallest unit as a unit, and selects any one of the areas obtained by dividing the pattern register into n parts or more than n parts when the parallel arithmetic data is rearranged using a bit width n times the smallest unit (where n is a power-of-two number) as a unit; and a rearranging circuit which rearranges the parallel arithmetic data according to the item of the pattern data selected by the select circuit.