Patent ID: 7143247

Claim:
A computer system having a memory, a data unit comprising a first parallel execution pipeline in a first slot of the data unit and a second parallel execution pipeline in a second slot of the data unit, said pipelines being arranged to output data for storing in said memory, and at least one other execution pipeline being arranged to output access addresses for the data, and a data memory controller arranged to receive data from each of said at least two parallel execution pipelines and form at least one data queue of data awaiting store operations in said memory, said data memory controller having a first input for receiving data from the first parallel execution pipeline, a second input for receiving data from the second parallel execution pipeline, reordering circuitry to enable reordering of data prior to entry on said at least one data queue and to insert data from said first and second inputs onto said at least one data queue in an order different from the order of arrival of data from said parallel execution pipelines at said first and second inputs such that data from the first slot is inserted onto the queue before data from the second slot and at least one address queue, separate from said at least one data queue, holding store addresses for use in storing data in said memory.