Patent ID: 7135379

Claim:
A method of forming isolation trenches in a semiconductor fabrication process, comprising: forming a patterned masking structure overlying a substrate to expose a first area of the substrate; forming spacers on sidewalls of the patterned masking structure, wherein the spacers cover a perimeter region of the first area thereby leaving a second area, smaller than the first area, exposed; etching the second exposed area to form an isolation trench and filling the trench with a trench dielectric; removing the spacers to expose the perimeter region; using the masking structure and the trench dielectric as a mask, implanting an impurity into a portion of the substrate underlying the exposed perimeter region wherein the implanted impurity surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate; prior to depositing the first and second masking layers, depositing a pad layer overlying the substrate, wherein the first pad layer comprises an oxide; and following deposition of the pad layer and prior to forming the patterned masking structure, depositing a polish stop layer overlying the pad layer.