Patent ID: 8686760

Claim:
A buffer comprising: a first transistor for transmitting a first power source voltage to an output terminal according to an input voltage applied to a gate of the first transistor; a second transistor for transmitting an inverted voltage of the input voltage to the output terminal; a capacitor comprising a first terminal coupled to a gate of the second transistor and a second terminal configured to be input with a first level voltage or a second level voltage according to the input voltage; a third transistor for transmitting a second power source voltage to the gate of the second transistor according to the input voltage applied to a gate of the third transistor, the input voltage also being applied to the gate of the first transistor; a fourth transistor for transmitting the first level voltage to the second terminal of the capacitor according to the input voltage; and a fifth transistor for transmitting the second level voltage to the second terminal of the capacitor according to the inverted voltage.