Patent ID: 7284215

Claim:
A method for use in connection with an integrated circuit design, the method comprising: identifying distinct timing paths of the integrated circuit design, the distinct timing paths having timing violations; identifying a first subset of the distinct timing paths including a plurality of timing paths wherein each of the plurality of timing paths includes at least one first common characteristic; within the plurality of timing paths forming the first subset, grouping the timing paths into one or more groups, each timing path within a group having at least one second common characteristic, correcting a first timing path violation for one of the timing paths within the group; repeating the first timing path violation correction for at least one of the other timing paths within the group; and identifying a second subset of the distinct timing paths including a second plurality of timing paths, wherein each of the second plurality of timing paths includes at least one third common characteristic, wherein a particular timing path including the at least one first characteristic and the at least one third characteristic is identified with a subset based on a prioritization of the first subset and the second subset, wherein the prioritization is based at least in part on the number of groups within each subset.