Patent ID: 7348632

Claim:
An NMOS device comprising: a first insulating layer; a channel layer which is a p-type semiconductor, and in contact with a top surface of the first insulating layer; a source and a drain which are n-type semiconductors, and in contact with both sides of the channel layer respectively and a top surface of the first insulating layer; a gate insulating layer located on the channel layer; a gate located on the gate insulating layer; a source metal connecting layer which is a conductor, and in contact with a top surface of the first insulating layer and a source silicide located between the source and the source metal connecting layer; a drain metal connecting layer which is a conductor, and in contact with a top surface of the first insulating layer and a drain silicide located between the drain and the drain metal connecting layer; a source metal line which is a conductor, and in contact with the source metal connecting layer; a drain metal line which is a conductor, and in contact with the drain metal connecting layer; and a gate metal line which is a conductor, and in contact with a gate silicide located between the gate and the gate metal line.