Patent ID: 7602017

Claim:
An N channel MOSFET (NMOS) comprising: a) a P − epitaxial layer on a substrate; b) a source and a drain formed in said epitaxial layer and located on opposite sides of a gate lying on a gate which lies on said epitaxial layer; c) a first N type upper buffer layer extending from under said source laterally to a position between a first edge of said gate closest to said source at a top surface of said epitaxial layer and a middle of said gate; d) a second N type upper buffer layer extending from under said drain laterally to a position between a second edge of said gate closest to said drain at said top surface of said epitaxial layer and said middle of said gate; e) a first P type lower bulk layer extending from under said first N type buffer layer laterally to a position under said gate at said top surface of said epitaxial layer which is closer to said drain than to said source; and f) a second P type lower bulk layer extending from under said second N type buffer layer laterally to a position under said gate at said top surface of said epitaxial layer which is closer to said source than to said drain, said first and second P type bulk layers overlying each other in a region under said gate.