Patent ID: 7305499

Claim:
A DMA transfer controller comprising: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for a plurality of logical processors performed by a main processor; a data transfer performing unit for performing the DMA transfer on the basis of the transfer parameters; a control unit for controlling the receive and transmit of the transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors, wherein, when the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence, and wherein, when all DMA transfers related to a certain logical processor are completed before the bus occupation elapse time reaches the bus occupation time value, the control unit starts the DMA transfers based on the transfer parameters related to the logical processors of the prescribed sequence.