Patent ID: 7216198

Claim:
A semiconductor integrated circuit device having a dynamic RAM, said dynamic RAM comprising a memory array, a RAM control section, an ECC-codec circuit, and an ECC controller, said RAM control section comprising a command decoding section responsive to an external command from the outside of said dynamic RAM for decoding the external command and a super self-refresh control circuit, said super self-refresh control circuit being contained within said RAM control section, wherein: said command decoding section is also adapted to receive an internal command generated inside said dynamic RAM and to decode the internal command; said ECC controller comprises a command generating section and an address generating section, said address generating section being contained within said ECC controller; said command decoding section delivers a start instruction signal representative of encoding to said ECC controller when an entry command is decoded as the external command; said command generating section of said ECC controller delivers, upon reception of the start instruction signal, a first operation mode signal representative of the encoding and simultaneously makes said address generating section of said ECC controller sequentially generate addresses corresponding to operation timings of the first operation mode signal and supplies the addresses to said memory array; said ECC-codec circuit carries out, upon reception of the first operation mode signal, an encoding operation of producing a check bit for error detection/correction with reference to information data stored in said memory array and writes the check bit into a predetermined region of said memory array; said command generating section of said ECC controller delivers, upon completion of the encoding operation by said ECC-codec circuit, a first end signal as the internal command to said command decoding section; said super self-refresh control circuit of said RAM control section starts, when said command decoding section receives and decodes the first end signal as the internal command, a super self-refresh operation which has a refresh cycle lengthened within an allowable range of error occurrence by an error correcting operation using the check bit.