Patent ID: 8618627

Claim:
An integrated circuit comprising: a level-shift transistor including: a source region near a working top surface of a semiconductor substrate, the semiconductor substrate having a first conductivity type; a drain region near the working top surface and laterally offset from the source region; a drift region extending from the drain region toward the source region, the drift region having a second conductivity type, the drift region including a first resurf region within the drift region near the working top surface and having the first conductivity type; and a gate located above the working top surface and laterally between the source and drain regions; a high voltage region including: a first well region laterally offset from the drift region, the first well region having the second conductivity type; a high voltage interconnect coupling the level-shift transistor to the high voltage region; and an isolation region located laterally between the level-shift transistor and the high voltage region, the isolation region comprising a portion of the semiconductor substrate extending to the top working surface.