Patent ID: 7902889

Claim:
A delay locked loop comprising: a buffer for outputting an internal clock by buffering an external clock; a delay block for delaying the internal clock for a delay time determined in response to a plurality of selection signals and a plurality of control signals, thereby outputting a delayed clock; a control signal generation block for generating at least one control signal according to a phase difference between the internal clock and a feedback clock generated by delaying the delayed clock by a delay time taken for the internal clock to be outputted; a selection block for outputting the plurality of selection signals in response to a signal instructing an off mode of the delay locked loop, wherein the selection signals are configured to select the delay time in the delay block during the off mode and are used to delay the internal clock with the selected delay time in the delay block; and an output driver for driving the delayed clock, wherein the delay locked loop is turned off during the off mode so that the feedback clock is not used by the delay locked loop in controlling the delayed clock during the off mode.