Patent ID: 7015094

Claim:
A method of fabricating a ferroelectric memory device having a cell array region with at least one cell transistor and a peripheral circuit region with at least one peripheral circuit transistor, the method comprising: forming a bit line pad and a storage node contact pad on the cell array region; forming a first interlayer dielectric layer overlying the bit line pad and the storage node contact pad; forming a bit line, a gate contact pad, and a source/drain contact pad which respectively connect with the bit line pad, a gate electrode, and a source/drain of the peripheral circuit transistor through the first interlayer dielectric layer; forming a second interlayer dielectric layer overlying the bit line, the gate contact pad, and the source/drain contact pad; forming a storage node contact plug connected to the storage node contact pad through the first and second interlayer dielectric layers and, concurrently, forming a gate contact plug and a source/drain contact plug connected to the gate contact pad and the source/drain contact pad, through the second interlayer dielectric layer, respectively; forming a ferroelectric capacitor connected to the storage node contact plug on the second interlayer dielectric layer; forming a third interlayer dielectric layer over the ferroelectric capacitor; patterning the third interlayer dielectric layer to form first via holes exposing the gate contact plug and the source contact plug; and forming a first interconnection that extends over a region of the third interlayer dielectric layer, conformally covers the sidewalls of the first via holes, and is connected to at least one of the gate contact plug and the source/drain contact plug.