Patent ID: 7550833

Claim:
A semiconductor device, comprising: a base plate; a first semiconductor construction which is arranged on the base plate and which has a first surface that includes a plurality of external connection electrodes formed around an upper surface periphery; a second semiconductor construction which is of a smaller size than the first semiconductor construction, and which is provided in an inner area of an external connection electrodes arrangement area of the first semiconductor construction, on the first surface of the first semiconductor construction; an insulating layer formed around a periphery of the first semiconductor construction and the second semiconductor construction; an upper layer insulating film formed on the first semiconductor construction, the second semiconductor construction and the insulating layer; and an upper layer wiring which is: (i) provided at least on the upper layer insulating film, (ii) electrically connected to the external connection electrodes of the first semiconductor construction, (iii) electrically connected to plural external connection electrodes of the second semiconductor construction, and (iv) extends to at least an area corresponding to the insulating layer formed around the periphery of the first semiconductor construction.