Patent ID: 8769508

Claim:
A method for a central processing unit (CPU), comprising: selectively operating decode logic to decode Reduced Instruction Set Computer (RISC) instructions and virtual machine instructions wherein register indications are produced for the virtual machine instructions without translating to RISC instructions; a mechanism to store operands for the RISC instructions in the register file; processing the decoded instructions in a single execution unit within the CPU; said processing comprising selectively operating the single execution unit and a register file to process outputs from the decode logic corresponding to the RISC instructions or the virtual machine instructions; operating a common program counter for the RISC instructions and the virtual-machine instructions; maintaining a virtual machine operand stack in the register file with at least one of an underlow and overflow mechanism for the operand stack when selectively decoding virtual machine instructions; and configuring the CPU to process RISC instructions after at least one of a reset and power-on.