Patent ID: 8856199

Claim:
A random number generator circuit comprising: a physical random number generating element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers and outputting a random number sequence; a testing circuit testing the random number sequence; a first memory storing information about error-correcting-code; and an error correcting code circuit including: a first XOR gate including an input terminal to receive digital random numbers that are sent as input signals; a shift register including a plurality of flip-flops connected in series, one in a first stage of the flip-flops receiving an output of the first XOR gate; a plurality of pass transistors corresponding to the respective flip-flops, one terminal of each of the pass transistors being connected to an output terminal of each corresponding one of the flip-flops, a gate of each of the pass transistors receiving a signal in accordance with the information stored in the first memory; a plurality of second XOR gates corresponding to the respective pass transistors except one of the pass transistors corresponding to one in a first stage of the flip-flops and connected in series, one in a first stage of the second XOR gates performing an exclusive-OR operation on signals that are sent from another terminal of corresponding one of the pass transistors and another terminal of the one of the pass transistors corresponding to the one in the first stage of the flip-flops, each of the second XOR gates except the one in the first stage of the second XOR gates performing an exclusive-OR operation on signals that are sent from another terminal of each corresponding one of the pass transistors and an output terminal of each one in a precedent stage of the second XOR gates; a switch being switched on and off in accordance with the result of a test conducted by the testing circuit, and sending an output of one in the last stage of the second XOR gates to the other input terminal of the first XOR gate; and a selector switch selecting and outputting one of an output of the flip-flop in the last stage of the shift register and the output of the one in the last stage of the second XOR gates, in accordance with the result of the test conducted by the testing circuit, the error correcting code circuit outputting the output of the one in the last stage of the second XOR gates as a corrected random number sequence from the selector switch when the result of the test conducted by the testing circuit indicates a rejection, and the testing circuit testing the corrected random number sequence when the result of the test indicates the rejection.