Patent ID: 6919249

Claim:
A method of manufacturing a semiconductor device comprising: forming a multi-layered structure including a semiconductor layer of a first conductivity type, a semiconductor region of a second conductivity type, a semiconductor region of a first conductivity type one over another in this order; forming a trench which extends from the semiconductor region of the first conductivity type through the semiconductor region of the second conductivity type to the semiconductor layer of the first conductivity type; forming an insulating layer over an inner wall of the trench; embedding a conductor in a space defined by the insulating layer in the trench; introducing impurity of the first conductivity type into part of a surface of the semiconductor region of the first conductivity, the part being apart from the trench, so as to from a region higher in concentration of which deepest level does not reach the underlying semiconductor region of the second conductivity type, partially etching away the region higher in concentration to expose the semiconductor region of the second conductivity type; and connecting an electrode to the region higher in concentration and to the exposed portion of the semiconductor region of the second conductivity type.