Patent ID: 7109761

Claim:
A comparator circuit constructed with MOSFETs of a LOCOS-drain structure formed on a P-type silicon substrate, the comparator circuit comprising: a first P-channel MOSFET of the LOCOS-drain structure having a source connected to a first power supply, which supplies a first supply voltage, through a first resistance element and a gate to which a reference voltage is applied; a second P-channel MOSFET of the LOCOS-drain structure having a source connected to the first power supply through a second resistance element and a gate to which an input signal voltage is applied; a current mirror circuit connected between drains of the first and the second P-channel MOSFETs and a ground; a comparison operation unit having a reference voltage input terminal and a comparison voltage input terminal, which are connected to the drains of the first and the second P-channel MOSFETs, respectively, and comparing the input signal voltage and the reference voltage, with power being provided from a second power supply, which supplies a second supply voltage lower than the first supply voltage of the first power supply; and voltage clamping means, disposed on a reference voltage input terminal side of the comparison operation unit, for performing a clamp operation when a potential of the terminal tends to rise above a predetermined level.