Patent ID: 6844772

Claim:
A threshold voltage extraction circuit, comprising: a first current mirror comprising a first transistor and a second transistor; a holding circuit, having a first terminal, a second terminal, and an output, the holding circuit adapted to control a current through the first current mirror by operating to maintain substantially equal the voltages at a first terminal and at a second terminal; a first resistor circuit coupled to the second transistor and the first terminal of the holding circuit, wherein the first resistor circuit comprises, a first resistor coupled between the source and gate of the third transistor, and a second resistor having a first terminal coupled to the gate of the third transistor, and having a second terminal coupled to the drain of the third transistor; a third MOS transistor, having a drain, a source and a gate, the drain and the gate coupled to the first resistor circuit adapted to generate a voltage which is a multiple of a source-gate threshold voltage of the third transistor, the source coupled to ground; a second resistor circuit coupled to the first transistor and to the second terminal of the holding circuit; a fourth MOS transistor, having a drain, a source and a gate, the drain and the gate coupled to the second resistor circuit, the fourth MOS transistor adapted to generate a threshold voltage across the second resistor circuit, by the operation of the holding circuit; a second current mirror coupled to the first current mirror, adapted to cause a current to flow through a third resistor circuit that corresponds to the current through the first current mirror to thereby provide and output voltage corresponding to the threshold voltage.