Patent ID: 7143384

Claim:
A method of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) technique, the method comprising: analyzing logic placement in the design; generating a list of placement patterns as a result of analyzing the logic placement, the list of placement patterns including a list of nets associated with each placement pattern; sorting the list of placement patterns in an order determined by a number of nets associated with each placement pattern; routing the nets associated with each placement pattern, in order from a placement pattern having a largest number of nets to a placement pattern having a smaller number of nets; and wherein routing the nets associated with each placement pattern comprises, for each placement pattern: selecting a plurality of sample nets from the list of nets associated with the placement pattern; generating a plurality of routing templates for each sample net and adding the routing templates to a cache of routing templates; selecting from the cache of routing templates a best template for unrouted nets associated with the placement pattern; and routing each unrouted net that can be routed using the best template.