Patent ID: 7313646

Claim:
An electronic system comprising: an initiator module complying with specifications of a first communication protocol; a target module addressable by the initiator module and complying with specifications of a second communication protocol, different from the first communication protocol; an interface and control module for interfacing between the first communication protocol and the second communication protocol; wherein: the interface and control module is coupled to the initiator module by a communication bus; the interface and control module is constructed so as to set a composite instruction detection signal in response to detecting a composite instruction executed by the initiator module, said composite instruction detection signal being used for the interfacing; the interface and control module is constructed to detect a composite instruction executed by the initiator module by monitoring, at each determined clock cycle of the initiator module, evolution of nondedicated information which is collected on the communication bus, with respect to a previous cycle of the initiator module; the nondedicated information which is collected at a determined clock cycle of the initiator module includes information identifying an elementary operation undergoing execution by the initiator module at the determined clock cycle, and a current logic value of a signal for selecting the target module; and a composite instruction is detected when, at a determined clock cycle of the initiator module, a change of the elementary operation executed by the initiator module is detected with respect to the previous clock cycle of the initiator module, while, at the same time, the signal for selecting the target module which was active is kept active.