Patent ID: 7690031

Claim:
An electronic data flash card adapted to be accessed by a host computer that is capable of establishing a communication link, said electronic data flash card comprising: a card body; one or more flash memory devices mounted on the card body, the flash memory device including a plurality of non volatile memory cells for storing a data file, said memory cells being arranged in at least one of a plurality of memory blocks, a plurality of pages, and a plurality of sectors; an input/output interface circuit mounted on the card body for establishing communication with the host computer, wherein the input/output interface circuit includes a Universal Serial Bus (USB) interface circuit including means for transmitting said data file using a Bulk Only Transport (BOT) protocol; and a flash memory controller mounted on the card body and electrically connected to said flash memory device and said input/output interface circuit, wherein the flash memory controller comprises: (a) means for determining whether the flash memory device is supported by a processing unit of the flash memory controller in accordance with a flash detection algorithm code, (b) arbitration means for identifying non-functional memory cells of the flash memory device, and for assigning physical addresses to an associated logical address, where each said physical address corresponds to an associated plurality of memory cells of the flash memory device; (c) means for operating in one of: a programming mode in which said flash memory controller activates said input/output interface circuit to receive the data file from the host computer, and to store the data file in a first physical address of said flash memory device that is assigned by said arbitration means to a first logical address, said programming mode being initiated in response to an associated standard USB BOT write command issued from the host computer to the flash memory controller; a data retrieving mode in which said flash memory controller receives a standard USB BOT read command issued from host computer including the first logical address, and activates said input/output interface circuit to transmit the data file read from the first physical address to the host computer; and a data resetting mode in which obsolete data previously written into one or more memory blocks is erased from the flash memory device, wherein said data resetting mode is initiated and performed automatically by said flash memory controller.