Patent ID: 6991993

Claim:
A method of fabricating a trench isolation structure of a semiconductor device, comprising: forming an etch mask pattern on a semiconductor substrate to expose respective areas of the substrate; forming a first trench having a first width and a second trench having a second width by etching the semiconductor substrate exposed by the etch mask pattern, the second width being greater than the first width; forming a trench filler insulation layer that fills the trenches and wherein the portion of the trench filler insulation layer filling the second trench has an upper surface disposed at a level no higher than that of the etch mask pattern, and the portion of the trench filler insulation filling the first trench has an upper surface disposed at a level higher than that of the etch mask pattern; subsequently forming a trench protection layer pattern on the portion of the trench filler insulation layer filling the second trench; subsequently removing material of the trench filler insulation layer by planarizing the structure using the etch mask pattern and the trench protection layer pattern as a planarization stopper, whereby the planarizing of the trench filler insulation layer terminates at the planarization stopper.