Patent ID: 7640527

Claim:
A method of circuit design for a programmable device, comprising: importing a logical description of a circuit design having static logic and reconfigurable logic into a graphical environment; and processing, by using a processor, the circuit design in a graphical user interface (GUI) of the graphical environment by: displaying a representation of the logical description in a netlist view of the GUI, a floorplan of the programmable device in a floorplan view of the GUI, and area constraints within the floorplan in a physical hierarchy view of the GUI; floorplanning the logical description to locate the static logic and the reconfigurable logic in the floorplan of the programmable device via interaction with at least one of the netlist view, the floorplan view, or the physical hierarchy view; performing at least one design rule check (DRC) via interaction with the netlist view, the floorplan view, and the physical hierarchy view; and managing a partial reconfiguration implementation of the circuit design for the programmable device by: implementing the static logic; implementing at least one partial reconfiguration module (PRM) of the reconfigurable logic; and assembling the static logic and the at least one PRM as implemented to generate a plurality of bitstreams including at least one full bitstream and at least one partial bitstream.