Patent ID: 7196951

Claim:
A semiconductor memory comprising: a plurality of memory blocks each of which includes a real cell array having a plurality of real memory cells arranged in matrix form, a row redundancy cell array having a plurality of row redundancy memory cells arranged in a row direction and a redundancy word line connected to said row redundancy memory cells, and a column redundancy cell array having a plurality of column redundancy memory cells arranged in a column direction and a redundancy bit line connected to said column redundancy memory cells; a plurality of redundancy column switches connecting redundancy bit lines to a data bus line; a redundancy column selection line connected to said redundancy column switches to allow said redundancy column switches to operate, and wired in common to said memory blocks; a plurality of row redundancy circuits each of which is formed so as to correspond to said redundancy word line, receiving an external row address signal, and activating a row hit signal to select a corresponding redundancy word line when a received external row address signal coincides with a defective row address programmed in advance; a plurality of column redundancy circuits formed so as to correspond to respective memory groups each having a prescribed number of said memory blocks, each of the column redundancy circuits operating when activated in response to a corresponding enable signal, receiving an external column address signal, and activating a column hit signal to select said redundancy column selection line when a received external column address signal coincides with a defective column address programmed in advance; and a column redundancy selection circuit receiving row hit signals and a block address signal to select said memory groups, activating the enable signal corresponding to a column redundancy circuit of one of said memory groups indicated by said block address signal when all of said row hit signals are deactivated, and activating the enable signal to activate the column redundancy circuit of one of said memory groups corresponding to an activated row hit signal when any one of said row hit signals is activated.