Patent ID: 7962821

Claim:
A semiconductor integrated circuit comprising: a built-in self test (to be referred to as a BIST hereinafter) circuit including: a data generator that is configured to generate write data to be written in a memory cell and output the write data to the memory cell; an address generator that is configured to generate an address data including address to be assigned to the memory cell and output the address data to the memory cell; a memory control signal generator that is configured to generate a memory control signal for controlling the memory cell and output the memory control signal to the memory cell; a result analyzer that is configured to receive a failure detecting signal indicating a failure of the memory cell and analyze a result of the BIST to output the analyzed result of the BIST; a diagnostic data transferring unit that is configured to: receive the failure detecting signal, a first clock signal, and a second clock signal having a lower frequency than the first clock signal; output a shift enable signal in response to receiving the failure detecting signal, store failure information of the memory cell in synchronization with the first clock signal; transfer the failure information in synchronization with the second clock signal in response to receiving the failure detecting signal; and a BIST control unit that is configured to control the data generator, the address generator, the memory control signal generator and the result analyzer and output a BIST status signal indicating a status of the BIST to the diagnostic data transferring unit; and a memory collar including: the memory cell that is configured to receive the first clock signal, the write data, the address data signal, and the memory control signal, and write the write data; a fetch register that is configured to fetch data written in the memory cell when the shift enable signal is not given and transfer fetched data to the diagnostic data transferring unit when the shift enable signal is given; a comparing unit that is configured to compare the data fetched in the fetch register with an expected value output from the BIST circuit; a first logical unit that is configured to: receive the compared result output from the comparing unit and a control signal output from the diagnostic data transferring unit; perform a first logical operation on the compared result and the control signal; and output a result of the first logical operation; a flag register that is configured to fetch the output of the first logical unit when the output of the first logical unit indicate that the failure of the memory cell is not happened and output the fetched data; and a second logical unit that is configured to: receive the output of the first logical unit and the output of the flag register; perform a second logical operation on the output of the first logical unit and the output of the flag register; and output a result of a second logical operation as the failure detecting signal.