Patent ID: 8421497

Claim:
A semiconductor chip, comprising: a plurality of memory cells; at least one first center pad disposed on a center region of the semiconductor chip and connected to the plurality of memory cells; at least one first edge pad disposed on an edge region of the semiconductor chip and connected to a first transmission line of a semiconductor module; at least one second edge pad disposed on the edge region of the semiconductor chip and connected to a chipset voltage application unit of the semiconductor module; at least one first redistribution pattern connected between the at least one first center pads and the at least one first edge pads; at least one second redistribution pattern connected between the at least one first edge pads and the at least one second edge pads; at least one second center pad disposed on the center region of the semiconductor chip and connected to the plurality of memory cells; at least one third edge pad disposed on the edge region of the semiconductor chip and connected to a second transmission line; and at least one third redistribution pattern connected between the at least one second center pad and the at least one third edge pad, wherein an impedance of the at least one second redistribution pattern is impedance matched to an impedance of the first transmission line, and an impedance of the at least one third redistribution pattern is impedance matched to a difference between an impedance of the second transmission line and impedances from the at least one second center pad to the plurality of memory cells.