Patent ID: 8148224

Claim:
A method of manufacturing a semiconductor device including a MISFET, comprising the steps of: (a) providing a semiconductor substrate of a first conductivity type; (b) forming a first trench in the semiconductor substrate; (c) forming a first conductive film in the first trench, wherein the first conductive film has a protruding portion which protrudes from a surface of the semiconductor substrate; (d) forming a first impurity region of a second conductivity type opposite the first conductivity type in the semiconductor substrate, wherein a depth of the first impurity region is shallower than a depth of the first trench; (e) forming a second impurity region of the first conductivity type in the semiconductor substrate, wherein a depth of the second impurity region is shallower than the depth of the first impurity region; (f) forming a side wall spacer over the second impurity region and over a side surface of the protruding portion; (g) forming a second trench by using the side wall spacer as a mask in the semiconductor substrate, wherein the second trench penetrates the second impurity region and reaches the first semiconductor impurity region; (h) forming a third impurity region of the second conductivity type in the first impurity region located at a bottom of the second trench, wherein an impurity concentration of the third impurity region is higher than an impurity concentration of the first impurity region; (i) after the step (h), recessing the side wall spacer, thereby a part of a surface of the second impurity region is exposed; and (j) after the step (i), forming a second conductive film in the second trench, wherein the conductive film is electrically connected with the exposed surface of the second impurity region outside of the second trench and is electrically connected with the first, second and third impurity regions inside of the second trench.