Patent ID: 8803533

Claim:
A method of determining an interface trap density at an interface between a semiconductor and a dielectric or oxide layer disposed on a surface of the semiconductor, comprising: placing an initial electric charge on at least a portion of a surface of a dielectric or oxide layer disposed on a semiconductor, wherein placing the initial electric charge on the surface of the dielectric or oxide layer creates an accumulation state in the semiconductor, wherein placing the initial charge on the surface of the dielectric or oxide layer results in an electric charge, Q C , on the surface of the dielectric or oxide layer, placing at least two increments of additional electric charge on the at least a portion of the surface of the dielectric or oxide layer, wherein each of the at least two increments of additional electric charge have an opposite sign as the initial electric charge, wherein after placement of the at least two increments of additional electric charge on the at least a portion of the surface of the dielectric layer the semiconductor is in depletion, wherein the electric charge, Q C , changes with the placement of each of the at least two increments of additional electric charge, measuring a corresponding value of a contact potential difference voltage, V CPD , after placement of each of the at least two increments of additional electric charge on the at least a portion of the surface of the dielectric layer, wherein each measured value of the contact potential difference, V CPD , corresponds to a value of electric charge, Q C , on the surface of the dielectric layer, determining a dielectric capacitance, C OX , value of the dielectric layer while the semiconductor is in accumulation from the measured contact potential difference voltage, V CPD , values and corresponding electric charge, Q C , values, and values of the at least two increments of additional electric charge, determining a flat band voltage, V FB , of the contact potential difference voltage, V CPD , from a doping level in the semiconductor and the dielectric capacitance value, C OX , determining one or more surface barrier voltage values, V SB , wherein the surface barrier voltage value, V SB , is a difference between the contact potential difference voltage, V CPD , on a V CPD -Q C curve at the corresponding electric charge, Q C , and a voltage value, V OX , on a straight line at the corresponding electric charge, Q C , wherein the line has a slope that is an inverse of the dielectric capacitance value, C OX , and the line intersects the V CPD -Q C curve based on the measured contact potential difference voltage values, V CPD , and corresponding electric charge values, Q C , at the flatband voltage, V FB , and determining one or more interface trap densities, D it , for a corresponding one or more electric charge values, Q C , from the corresponding one or more electric charge values, Q C , the corresponding surface barrier voltage values, V SB , the doping level in the semiconductor, and an extrinsic Debye length, L D , for the semiconductor.