Patent ID: 8767483

Claim:
An apparatus comprising: a first evaluation unit, the first evaluation unit including: a plurality of input nodes, each input node to receive a different one of a plurality of data values; and a number of legs, each leg having a number of access devices such that a control terminal of each access device is coupled to a different one of the input nodes, the legs arranged in parallel with each other, the number of access devices in each leg being greater than or equal to two; a second evaluation unit, the second evaluation unit including: a plurality of input nodes to receive the plurality of data values inverted, each input node coupled to receive a different one of the inverted data values; and a number of legs, each leg having a number of access devices such that a control terminal of each access device is coupled to a different one of the input nodes, the legs arranged in parallel with each other, the number of access devices in each leg being greater than or equal to two; and a comparison unit coupled to both an output of the first evaluation unit and an output of the second evaluation unit, the comparison unit having an output node to provide a signal indicative of a majority of one value in the data values, wherein the output of the first evaluation unit is coupled to a first reference voltage through a first enable transistor having a gate configured to receive a first enable signal for the first evaluation unit, and wherein the output of the second evaluation unit is coupled to the first reference voltage through a second enable transistor having a gate configured to receive a first enable signal for the second evaluation unit.