Patent ID: 8069314

Claim:
A processor in a GPS signal receiver having a first mode of operation and a second mode of operation, comprising: a plurality of correlators, wherein the number of correlators that are active during the first mode of operation is greater than the number of correlators that are active during the second mode of operation, and wherein each correlator (1) receives a predetermined code and an input data stream representing digitized signals received from OPS satellites, and (2) provides an output data stream representing a product of the input data stream and the predetermined code, offset by a code phase selected for that correlator; an accumulator which receives the output data streams of the correlators and which provides, for each data stream, a corresponding integration sum over a predetermined time period; and a memory circuit which receives and stores the integration sums from the accumulator wherein, during the second mode, memory space allocated for storing the integration sums corresponding to data streams from correlators that are active during the first mode, but not active during the second mode, are reallocated for use other than storing integration sums.