Patent ID: 7461236

Claim:
An integrated circuit comprising: a plurality of tiles, each tile comprising a processor; a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled; a switch instruction fetch unit configured to fetch switch instructions for the switch in a first mode in which input data arriving at the switch in successive cycles are forwarded according to different switch instructions fetched by the switch instruction fetch unit during the successive cycles; and a multiplexer configured to select a coupling between an input port and output port for forwarding data from the input port to the output port in a given cycle, wherein, in a first mode, the multiplexer is configured to select respective couplings for forwarding input data arriving at the switch in successive cycles according to switch instructions fetched by the switch instruction fetch unit in the successive cycles, and, in a second mode, the multiplexer is configured to select a single coupling for forwarding input data arriving at the switch in successive cycles according to circuitry that establishes the single coupling with power to the switch instruction fetch unit turned off during the successive cycles; wherein switch is configured to synchronize forwarding of data at multiple input ports to respective output ports in the first mode, and to forward data at multiple input ports to respective output ports independently without requiring synchronization in the second mode.