Patent ID: 7884641

Claim:
An integrated circuit comprising: at least one data pin connecting the integrated circuit to circuits external to the integrated circuit; a plurality of operational units, each including at least one data input/output for data transfer, an enable input and inputs connected to operating circuits of the integrated circuit, a predetermined enable signal on said enable input placing said operational unit in a normal mode to exchange data via said at least one data input/output and a predetermined not-enable signal on said enable input placing said operational unit in a stall mode not capable of exchanging data via said at least one data input/output, each operational unit transmitting signals corresponding to said inputs connected to said operating circuits on said at least one data line when in a normal mode; and a selection logic including a plurality of enable lines each connected to an enable input of a corresponding operational unit, a plurality of data lines, a data line connected to each of said at least one data input/output of each operational unit and connected to said data pin, said selection logic selectively enabling an operation unit and connecting said data input/output of said enabled operation unit to said at least one data pin.