Patent ID: 7920012

Claim:
A semiconductor device to which a first power supply potential and a second power supply potential higher than said first power supply potential are supplied, the semiconductor device comprising: an internal circuit operated by being supplied with said first power supply potential to output a first internal signal; an inverter circuit operated by being supplied with said first power supply potential and having a P-channel MOS transistor and an N-channel MOS transistor within which a parasitic diode is formed to output a second internal signal obtained by inverting said first internal signal; a level shifter circuit operated by being supplied with said second power supply potential and having a level shifter for outputting a level shift signal depending on said first and second internal signals, which are complementary to each other, inputted to first and second input terminals, respectively; a current generating circuit including a current mirror circuit for supplying a current to a current path to a power supply node for supplying said first power supply potential to said inverter circuit through said parasitic diode, when said second power supply is inputted before said first power supply; and a bias circuit connected between said current generating circuit and said inverter circuit.