Patent ID: 7054221

Claim:
A data pass control device for masking a write ringing in a write operation after generating a predetermined length of data strobe signal in a DDR SDRAM, the data pass control device comprising: a data input buffer for receiving data inputted from the outside of the device; a data strobe buffer for receiving a predetermined length of data strobe signal inputted from the outside of the device and outputting first and second control signals; a data latch for storing the data outputted from the data input buffer, in response to the first and second control signals; a data strobe buffer controller for outputting a third control signal to control an operation of the data strobe buffer; and a write operation period detector for detecting a write operation period during a write operation and outputting a fourth control signal to control the data strobe buffer controller, wherein the fourth control signal is outputted when the predetermined length of data strobe signal is present, and wherein the third control signal enables the data strobe buffer in the write operation period and disables the data strobe buffer when the write operation is completed in response to the fourth signal.