Patent ID: 8637363

Claim:
A method of manufacturing a semiconductor device, the method comprising: forming an etch target layer on a semiconductor substrate; forming a preliminary mask pattern on the etch target layer, the preliminary mask pattern being formed to have a planar shape corresponding to a design layout that includes wave line type patterns which are arrayed in parallel and each of the wave line type patterns being formed to include a plurality of main pattern portions serially arrayed in each column and a plurality of connection bar pattern portions for connecting the plurality of main pattern portions in each column; forming node separation walls on sidewalls of the preliminary mask patterns to provide an array of main space portions which are located at both sides of each of the connection bar pattern portions; removing the main pattern portions to provide an array of additional space portions which are separated from the main space portions by the node separation walls; etching the etch target layer using the node separation walls as etch masks to form an array of through holes penetrating the etch target layer; and forming an array of nodes which are disposed in respective ones of the through holes.