Patent ID: 8222082

Claim:
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming an integrated circuit in each of a plurality of chip areas over a semiconductor substrate partitioned into the chip areas by a scribe area; (b) forming, in an upper layer of said integrated circuit, a first wiring extending from a first circuit region to a second circuit region; (c) defining part of said first wiring of said first circuit region as a first pad and defining part of said first wiring of said second circuit region as a second pad; (d) forming a protective film over said semiconductor substrate under the presence of said first wiring; (e) forming a first opening in said protective film over said first pad or forming a second opening in said protective film over said second pad; (f) cutting said semiconductor substrate along said scribe area and dividing said semiconductor substrate into individual semiconductor chips; and (g) mounting each said semiconductor chip over a corresponding mounting substrate and, through a first bonding wire or a first bump electrode thereof, electrically coupling each semiconductor chip with said corresponding mounting substrate, wherein, in said step (g), if electrically coupling a semiconductor chip with said mounting substrate through said first bonding wire, said first opening is formed in said protective film over said first pad in said step (e) and said first bonding wire is coupled to said first pad in said step (g), wherein, if electrically coupling a semiconductor chip with said mounting substrate in said step (g) through said first bump electrode, said second opening is formed in said protective film over said second pad in said step (e), said first bump electrode being coupled to said second pad, and wherein said first wiring is electrically coupled to a power supply potential or a reference potential.