Patent ID: 8200734

Claim:
An arithmetic unit comprising: M interfaces, each containing n leads, where K=M−L of the interfaces pertain to data strips, and remaining L>1 of the interfaces pertain to error detection-and-correction strips; and a read only memory (ROM) structure having K inputs that contain n leads each, said K inputs being coupled to said K interfaces, said structure developing L n-bit signature strips in response to data strips D i , i=1, 2, . . . K, that are applied to said K interfaces, where said ROM structure includes a ROM module that in response to an input that is applied to an address port of the module and which includes data strip D i , outputs an n-bit word that is related to g i ·D i , g is a preselected polynomial generator of said finite field, g i is a coefficient polynomial that corresponds to said polynomial generator raised to power i, and “·” is multiplication over the field; where in response to data strips D i , i=1, 2, . . . K applied to said K interfaces said ROM structure outputs a first of said L n-bit signature strips corresponding to P=D 0 +D 1 + . . . +D K-1 and a second of said L n-bit signature strips corresponding to Q=g 0 ·D 0 +g 1 ·D 1 + . . . +g M-1 ˜D M-1 .