Patent ID: 8885413

Claim:
An apparatus comprising: a memory structure comprising non-volatile memory cells that are arranged on word lines and bit lines; and a microcontroller that is communicatively coupled with the memory structure, the microcontroller configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period; wherein the failure is based on two or more mismatches between the data and two or more read back versions of the data corresponding to two or more attempts to write the data to the memory structure; and wherein the microcontroller is configured to apply a first voltage to the selected word lines for the two or more attempts and apply a second voltage to the one or more unselected word lines for the two or more attempts, wherein the second voltage is less than the first voltage, and wherein the negative bias voltage is less than the second voltage.