Patent ID: 7369600

Claim:
Apparatus for receiving a serial data stream comprised of a plurality of multiple symbol data words and converting said data stream into a parallel data stream, said apparatus comprising: a first delay line, said first delay line being a tapped analog delay line including a serial input for receiving said serial data stream, a serial output, a plurality of stages between said serial input and said serial output, and a plurality of parallel output taps, one for each of said stages; a ring oscillator including a loop having said first delay line inserted therein for monitoring a transmission frequency of said multiple symbol data words; a frequency tracking loop for calibrating said ring oscillator, said tracking loop generating a control signal that is connected to said control input of said first delay line to control the delay characteristics of said first delay line, and thereby control the oscillation frequency of said ring oscillator; a multiple bit output latch having a plurality of parallel inputs for simultaneously receiving each symbol of one of said multiple symbol data words in said data stream, a corresponding plurality of parallel outputs and a control input for selectively latching symbol values that are present at said latch inputs onto said latch outputs, said parallel inputs each being connected to a corresponding one of said parallel output taps of said first delay line; and means for detecting when the symbols of any serial data word are aligned in said stages of said first delay line, and in response thereto, supplying a latch control signal to said latch control input, said means for detecting comprising a sliding window correlator for correlating signal values on each of said delay line parallel output taps with reference signal values and generating a correlator output signal having a magnitude that is increased when the symbols of any serial data word are aligned in said stages of said first delay line; and a resonator loop for adding a present value of said correlator output signal with one or more previous values of said correlator output signal and thereby generating a latch control signal that includes a spike which occurs when the symbols of any serial data word are aligned in said stages of said first delay line and is of sufficient magnitude to cause said output latch to latch the symbols in said stages of said first delay line onto said outputs of said output latch; whereby, when the symbols of any serial data word are aligned in said stages of said first delay line, the symbols will be output as a multiple bit parallel data word on said latch outputs.