Patent ID: 8018937

Claim:
An apparatus comprising: a pipelined switch, wherein the pipelined switch is configured to control processing of a plurality of packets, wherein each packet of the packets comprises a header portion, a class of service indicator, and a corresponding tail portion, comprising a plurality of packet header buffers (PHBs); a plurality of PHB pointers, each of the PHB pointers configured to point to a PHB of the PHBs; a plurality of pipeline stage circuits wherein the pipeline stage circuits are connected in a sequence, and the pipeline stage circuits comprise at least a first stage circuit and a last stage circuit, the first stage circuit is configured to read a header portion of a packet of the packets, and store the header portion in at least one of the PHBs using at least one of the PHB pointers, except for the last stage circuit, each of the pipeline stage circuits is configured to pass data to a next one of the pipeline stage circuits, at least one of the pipeline stage circuits is configured to generate a modified header portion by modifying the header portion stored in the at least one of the PHBs, wherein the modifying comprises replacing at least a portion of the header portion, and the at least the portion of the header portion comprises label information, and the last stage circuit is configured to be coupled to a switching matrix by virtue of being configured to output the modified header portion; and a tail portion transmission path for transmitting the tail portion through the pipelined switch.