Patent ID: 7880693

Claim:
A display comprising: a plurality of pixel circuits configured to be arranged in a matrix and each include at least one transistor of which the conduction state is controlled through reception of a drive signal to a control terminal; a scanner configured to output a drive signal to the control terminals of the transistors included in the pixel circuits; and a drive interconnect configured to be connected to the control terminals of the transistors in the pixel circuits in common and allow transmission of a drive signal output by the scanner, wherein the drive interconnect includes a configuration that averages signal delay due to interconnect resistance differences dependent upon a distance from a drive signal output terminal of the scanner, wherein: a line width of the drive interconnect is increased in linkage with increase in a distance from the drive signal output terminal of the scanner, the drive interconnect is formed as interconnects on two layers, and a line width of a whole of the interconnect on one layer is uniform, and a line width of the interconnect on the other layer is increased in linkage with increase in a distance from the drive signal output terminal of the scanner.