Patent ID: 8760902

Claim:
A system comprising: an interposer having a first surface that includes first, second and third portions: a first semiconductor chip mounted on the first portion of the first surface of the interposer, the first semiconductor chip that comprises: first and second terminals supplied with first and second voltages, respectively, the first voltage being greater than the second voltage; a third terminal supplied with first control information; a first circuit coupled to the third terminal, the first circuit being configured to output a first control signal in response to the first control information; a second circuit coupled to the first and second terminals and the first circuit, the second circuit being configured to generate a third voltage based on the first and second voltages in response to the first control signal, the third voltage being different from each of the first and second voltages; and a third circuit coupled to the second circuit, the third circuit being configured to operate on the third voltage; a second semiconductor chip mounted on the second portion of the first surface of the interposer, the second semiconductor chip that comprises: fourth and fifth terminals supplied with the first and second voltages, respectively; a sixth terminal supplied with second control information; a fourth circuit coupled to the sixth terminal, the fourth circuit being configured to output a second control signal in response to the second control information; a fifth circuit coupled to the fourth and fifth terminals and the fourth circuit, the fifth circuit being configured to generate a fourth voltage based on the first and second voltages in response to the second control signal, the fourth voltage being different from each of the first and second voltages; and a sixth circuit coupled to the fifth circuit, the sixth circuit being configured to operate on the fourth voltage; and a third semiconductor chip mounted on the third portion of the first surface of the interposer, the third semiconductor chip that comprises seventh and eighth terminals supplied with the first and second control information, respectively, the seventh and eighth terminals being electrically coupled to the third and sixth terminals through the interposer, respectively.