Patent ID: 8158466

Claim:
A method of fabricating an array substrate, the method comprising: forming a gate line and a gate electrode on a substrate having a pixel region, the gate electrode being connected to the gate line; forming a gate insulating layer on the gate line and the gate electrode; forming an oxide semiconductor layer and an auxiliary pattern on the gate insulating layer, the auxiliary pattern including a conducting material; forming source and drain electrodes on the auxiliary pattern and a data line over the gate insulating layer, the source and drain electrodes being disposed over a first portion of the auxiliary pattern and spaced apart from each other to expose a second portion of the auxiliary pattern, the second portion of the auxiliary pattern covering the entire channel region of the oxide semiconductor layer, and the data line crossing the gate line to define the pixel region; oxidizing the second portion of the auxiliary pattern of the conducting material into an insulating material; forming a passivation layer on the source and drain electrodes and the data line, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the drain contact hole.