Patent ID: 8203177

Claim:
A flash memory device, comprising: a substrate; a cell stack comprising a plurality of cell stack layers, each cell stack layer comprising: a semiconductor layer for providing junction areas and channel areas, and an interlayer isolation layer for insulating the semiconductor layer, wherein: the semiconductor layer and the interlayer isolation layer are repeatedly stacked to form the plurality of cell stack layers, the semiconductor layer includes a silicon layer doped with p-type impurities, each junction area includes an impurity-doped area in a shape of a stripe formed by doping n-type impurities on some area of the silicon layer, and each junction area extends in a direction along which a NAND cell string extends; an array of gate columns, each gate column penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack disposed at an interface between each gate column and the cell stack to store charge.