Patent ID: 7971162

Claim:
A method to assess spare latch placement in a macro, the method comprising steps of: using a processor for determining a location for each spare latch in the macro; examining local clock buffers associated with the macro to locate any local clock buffers without a spare latch directly attached to clock nets driven by said local clock buffer; measuring a distance between each of the local clock buffers without spare latches and a closest spare latch; running statistics for the local clock buffers from the measuring step, wherein the statistics relate to a measured distance between the local clock buffers and the spare latches; locating macros with inadequate spare latch placement using the statistics, by: surpassing a bound on chip frequency performance and surpassing a maximum number of allowed latches in a clock domain; setting a criterion for a maximum distance between each local clock buffer, without spare latches and a closest spare latch, wherein setting the criterion for maximum distance comprises: setting a local clock to be routed to meet overall chip frequencies; calculating an overall distribution of distances; and looking for distances that fall beyond normal statistical bounds; and loading the spare latches that meet the criterion to the macro.