Patent ID: 8213253

Claim:
A semiconductor memory comprising: a regular memory cell having a cell capacitor storing an electric charge corresponding to one of a high logic level and a low logic level; a regular pre-sense amplifier having a regular capacitor which is saturated by the electric charge read from the regular memory cell holding the high logic level and from which a saturation voltage is read, and which is not saturated by the electric charge held in the regular memory cell holding the low logic level and from which a read voltage lower than the saturation voltage is read, and generating a regular read voltage corresponding to the electric charge being stored; a reference memory cell having a cell capacitor storing the electric charge corresponding to the high logic level; a reference pre-sense amplifier having a reference capacitor which is saturated by the electric charge read from the reference memory cell holding the high logic level and from which the saturation voltage is read, and generating the saturation voltage as a reference read voltage; a differential sense amplifier differentially amplifying a difference between the regular read voltage and a reference voltage which is lower than the reference read voltage by a first voltage to generate logic of data held in the regular memory cell; and a voltage conversion circuit being arranged between an output of the reference pre-sense amplifier and an input of the differential sense amplifier and generating the reference voltage.