Patent ID: 8278166

Claim:
A method of manufacturing a complementary metal oxide semiconductor (CMOS) device comprising steps of: providing a substrate having a first region and a second region defined thereon; forming a first gate structure and a second gate structure respectively in the first region and the second region, each of the gate structures comprising a gate dielectric layer, a sacrificial layer, and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate at two sides of the second gate structure; performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer to cover the entire second region and expose the entire first region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer in the first region to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure, and the first spacer in the second region and the hard mask layer on the second gate structure being protected from the dry etching process by the second patterned protecting layer.