Patent ID: 7135743

Claim:
An ESD protection device with complementary dual drain implant comprising: a) an N-well implanted in a P-substrate; b) an N+ diffusion implanted over said N-well, such that said N+ diffusion extends into said P-substrate on both sides of said N-well; c) where said N+ diffusion is shared by the drains of two adjacent NMOS transistors; d) a pad coupled conductively to said N+ diffusion between said drains; and e) a P-ESD implant interposed between said N+ diffusion and said N-well such that said P-ESD implant is embedded within said N+ diffusion and said N-well, where said P-ESD implant lowers the avalanche voltage of a transistor by reducing the breakdown voltage of the drain/P-substrate junction, and where sections of said embedded P-ESD implant extend at either end of said P-ESD implant beyond said N-well and said N+ diffusion, said P-ESD implant thus coupling electrically to said P-substrate.