Patent ID: 8530324

Claim:
A method of fabricating a memory device comprising: forming in a cell array region of a microelectronic substrate, a cell signal transfer conductor layer and a lower layer on the cell signal transfer conductor layer, the lower layer including a flat outer surface that extends onto a peripheral region of the substrate; forming a dielectric layer on the flat outer surface of the lower layer in the cell array region and in the peripheral region; forming a peripheral signal transfer conductor layer on the dielectric layer in the peripheral region; etching the dielectric layer in the cell array region and in the peripheral region using the peripheral signal transfer conductor layer as an etch mask; forming an insulating layer on the flat outer surface of the lower layer in the cell array region and extending on the flat outer surface of the lower layer in the peripheral region and on the peripheral signal transfer conductor layer, the insulating layer having a flat outer surface from the cell array region to the peripheral region; forming a flat stopper layer on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region; and forming an array of memory cell capacitor storage nodes in the cell array region that extend beyond the insulating layer and that penetrate through the flat stopper layer and the insulating layer.