Patent ID: 7587019

Claim:
A fractional frequency divider (FFD), comprising: an input terminal receiving an input signal; an output terminal outputting an output signal; a modulus controlling unit (MCU) having a first dual-edge trigger (FDET), receiving said input signal and generating a modulus selection signal (MSS) in response to said FDET; and a frequency dividing unit (FDU) having: a first NOT gate having an input and an output terminal; a first AND gate having a first terminal, a second terminal coupled to said output terminal of said first NOT gate and an output terminal; a second NOT gate having an input terminal coupled to said output terminal of said FFD and receiving a first feedback signal and an output terminal coupled to said first terminal of said first AND gate; a second dual-edge trigger (SDET) having: a first latch having a first terminal coupled to said output terminal of said first AND gate, a second terminal being an enable terminal, coupled to said input terminal of said FFD and receiving said input signal, and an output terminal; and a second latch having a first terminal coupled to said output terminal of said first AND gate, a second terminal coupled to said input terminal of said FFD and receiving said input signal and an output terminal; and a first multiplexer having a first terminal coupled to said output terminal of said first latch, a second terminal coupled to said output terminal of said second latch, a third terminal coupled to said input terminal of said FFD and receiving said input signal, and an output terminal coupled to said output terminal of said FFD, coupled to said MCU and dividing a frequency of said input signal by one of an integer and a fractional moduli in response to said SDET and said MSS to generate said output signal via said first multiplexer.