Patent ID: 7061284

Claim:
A state circuit, comprising: a first flip flop coupled to receive a first feedback signal and a clock signal, and configured to produce a first output signal and an inverted version of the first output signal dependent upon the first feedback signal and the clock signal; a second flip flop coupled to receive the first output signal and the clock signal, and configured to produce a second output signal and an inverted version of the second output signal dependent upon the first output signal and the clock signal; a state correction circuit coupled to receive the inverted versions of the first and second output signals and a second feedback signal, and configured to produce a third output signal dependent upon the inverted versions of the first and second output signals and the second feedback signal; a third flip flop coupled to receive the third output signal and the clock signal, and configured to produce a fourth output signal, and an inverted version of the fourth output signal as the second feedback signal, dependent upon the third output signal and the clock signal; a fourth flip flop coupled to receive the fourth output signal and the clock signal, and configured to produce a fifth output signal dependent upon the fourth output signal and the clock signal; and wherein the state circuit is configured to produce an output signal having a frequency that is less than a frequency of the clock signal.