Patent ID: 7007262

Claim:
A high level synthesis method for automatically generating a register transfer level circuit description from a behavioral circuit description, wherein clock timings for registers are synthesized simultaneously during the synthesis of the register transfer level circuit description from the behavioral circuit description, wherein the method comprises the steps of: generating a control data flow graph (CDFG) by converting the behavioral circuit description to the CDFG; scheduling the CDFG in such a way that the number of registers is minimized with a given number of clock cycles; allocating hardware to the CDFG scheduled in the step of scheduling the CDFG; scheduling a clock by adjusting clock timings for registers allocated in the step of allocating hardware in such a way that a clock period is reduced; and performing retiming by changing the allocation of the registers to the CDFG in the step of allocating hardware when the clock period obtained in the step of scheduling a clock is greater than a desired clock period, wherein the synthesis method is terminated when the clock period obtained in the step of scheduling a clock is smaller than the desired clock period, and wherein the synthesis method returns to the step of scheduling a clock when the clock period is improved as a result of the step of performing retiming.