Patent ID: 7269704

Claim:
A system for reducing inactive periods in an integrated circuit coupled to an external peripheral by an external data bus, the integrated circuit having a processor, an address decoder coupled to the processor by an internal data bus, the system comprising: an external bus circuit coupled to the internal data bus and the external data bus, the external bus circuit configured to receive a read signal requesting data from the processor and in response generate a wait signal until data from the external peripheral is available on the internal data bus, the wait signal indicating that the external and internal data bus are not available for other purposes, and after the processor has received data from the internal data bus the external bus circuit stops generating the wait signal and generates a busy signal, the busy signal indicating that the internal data bus is available and the external data bus is not available for other purpose; and a logic gate coupled to the address decoder and the external bus circuit, the logic gate configured to receive the wait signal from the external bus circuit, the address decoder further configured to transmit a hold signal to the logic gate if the processor requests an address located in the external peripheral, the hold signal indicating that the external data bus is not available, the logic gate configured to transmit to the processor either the wait or hold signals.