Patent ID: 8661389

Claim:
A method of designing an integrated circuit, the method comprising: providing a cell library including a first cell structure and a second cell structure, the first cell structure including a first dummy gate electrode disposed on a first boundary of the first cell structure, a first edge gate electrode disposed adjacent to the first dummy gate electrode, a first oxide definition (OD) region having a first edge disposed between the first edge gate electrode and the first dummy gate electrode, the second cell structure including a second dummy gate electrode disposed on a second boundary of the second cell structure, a second edge gate electrode disposed adjacent to the second dummy gate electrode, a second OD region having a second edge disposed between the second edge gate electrode and the second dummy gate electrode; and determining, using a computer, if the first cell structure is to be abutted with the second cell structure, wherein if the first cell structure is to be abutted with the second cell structure, the method includes abutting the first cell structure with the second cell structure, and if the first cell structure is not to be abutted with the second cell structure, the method includes increasing an area of a first portion of the first OD region between the first edge gate electrode and the first dummy gate electrode; wherein said increasing the area of a first portion of the first OD region comprises: determining if a space between the first and second boundaries is larger than a pitch of the first gate electrode, wherein if the space is not larger than the pitch of the first gate electrode, the method includes increasing the area of the first portion by extending the first edge of the first OD region, and if the space is larger than the pitch of the first gate electrode, the method further includes: determining if the first portion of the first OD region is to be electrically coupled with a signal net, wherein if the first portion of the first OD region is to be electrically coupled with a signal net, the method includes increasing the area of the first portion by extending the first edge of the first OD region, and if the first portion of the first OD region is not to be electrically coupled with a signal net, the method includes increasing the area of the first portion by replacing the first dummy gate electrode with a first dummy transistor.