Patent ID: 8200949

Claim:
An apparatus, comprising: a processor capable of simultaneously processing a plurality of threads, the processor including: a register file, and a register file cache in communication with the register file; wherein the processor is operable to: store first data in the register file cache or bypass the register file cache and write to the register file, copy the first data from the register file cache to the register file, retrieve the first data from the register file, store second data in the register file cache, retrieve the second data from the register file cache, and delete the second data from the register file cache before the second data is copied from the register file cache to the register file; wherein the register file cache is simultaneously utilized by each of the plurality of threads; wherein the register file cache is allocated amongst each of the plurality of threads based on a policy that dictates a number of registers of the register file cache that are allocated to each of the plurality of threads.