Patent ID: 7428197

Claim:
A PLL circuit comprising: an analog-to-digital converter that quantizes a signal read from a recording medium using a sampling clock; a phase error detecting circuit that detects a phase error between a desired clock and the sampling clock on the basis of a data stream signal resulting from the quantization by the analog-to-digital converter, to output a phase error detection signal; and an oscillator that varies an oscillating frequency thereof in accordance with the phase error detection signal outputted from the phase error detecting circuit, and gives the oscillating clock as the sampling clock, wherein the phase error detecting circuit includes: phase error detecting means that detects the phase error from the data stream signal and a data stream signal that is 1 clock cycle earlier; absolute value comparing means that detects an absolute value of the phase error detected by the phase error detecting means exceeding a predetermined threshold; holding means that holds a polarity of the phase error detected by the phase error detecting means for a period of the detection by the absolute value comparing means, wherein the polarity is as of a timing of the detection by the absolute value comparing means; anticoincidence detecting means that detects anticoincidence between the polarity held by the holding means and a polarity of the phase error detected by the phase error detecting means; and polarity inverting means that provides the phase error detection signal by inverting the polarity of the phase error detected by the phase error detecting means when the anticoincidence detecting means detects the anticoincidence, and provides the phase error detection signal without inverting the polarity of the phase error detected by the phase error detecting means when the anticoincidence detecting means does not detect the anticoincidence.