Patent ID: 8799556

Claim:
An apparatus, comprising: a plurality of multi-level memory cells configured to store data, wherein one or more of the multi-level memory cells are designated as pilot memory cells, and wherein each pilot memory cell is configured to store known, pre-determined data; an estimation block configured to, based on the known, pre-determined data stored in the one or more pilot memory cells, determine (i) estimated mean values of level distributions of the multi-level memory cells and (ii) estimated standard deviation values of level distributions of the multi-level memory cells; and a computation block operatively coupled to the estimation block, wherein the computation block is configured to, based at least in part on (i) the estimated mean values of level distributions of the multi-level memory cells and (ii) the estimated standard deviation values of level distributions of the multi-level memory cells, compute (i) detection threshold values associated with crossing points of level distributions of the multi-level memory cells and (ii) mean values of level distributions of the multi-level memory cells, wherein the detection threshold values associated with the crossing points are to be used in order to facilitate reading of the data stored in the multi-level memory cells, and wherein the mean values of level distributions of the multi-level memory cells are to be used to minimize write error probabilities for writes to the multi-level memory cells.