Patent ID: 7178114

Claim:
A method for use by a computer-aided design tool for generating a final layout for an electronic device implemented within an integrated circuit (IC), the method comprising the steps of: a. storing a device template including a master layout specifying dimensions and relative positions of objects within the IC to form the electronic device, wherein some of the object dimensions and relative positions are specified as functions of values of input parameters, and wherein at the device template also includes a script containing instructions for modifying a preliminary layout for the electronic device to produce the final layout, b. receiving the values of the input parameters from a user, c. evaluating the functions relative to the values of the input parameters supplied by the user at step b to determine values of object dimensions and relative positions the device template specifies as functions of the input parameters, d. generating the preliminary layout for the electronic device wherein object dimensions and relative positions specified by the preliminary layout are consistent with those specified in the master layout and with the values of object dimensions and relative positions determined at step c, and e. modifying the preliminary layout in accordance with the script to generate the final layout for the electronic device.