Patent ID: 8693149

Claim:
A TSD device comprising: a semiconductor substrate; a vertical MOS transistor formed on the semiconductor substrate and having a drain coupled to a first terminal of the TSD device, a source coupled to a second terminal of the TSD device, and also having a gate, and a gate-to-source enabling threshold voltage; a voltage reference circuit formed on the semiconductor substrate and coupled between the first and second terminals of the TSD device to receive an input voltage, the voltage reference circuit having an output configured to form a reference voltage in response to the input voltage increasing to a first value that is greater than a threshold voltage of the voltage reference circuit wherein the reference voltage has a value that is less than the gate-to-source enabling threshold voltage of the vertical MOS transistor; a first transistor formed on the semiconductor substrate, the first transistor coupled to receive the reference voltage and form a signal to enable the vertical MOS transistor responsively to the voltage reference circuit forming the reference voltage wherein the vertical MOS transistor clamps the first terminal of the TSD device to a second value that is greater than the first value as a current through the vertical MOS transistor increases from a first value to a second value; the voltage reference circuit including a second transistor having a control electrode coupled to a first current carrying electrode of the second transistor, a second current carrying electrode, and a body of the second transistor coupled to the second terminal of the TSD device, the voltage reference circuit including a resistor coupled between the second current carrying electrode of the second transistor and the second terminal of the TSD device.