Patent ID: 8575968

Claim:
A circuit comprising: a differential comparator having a positive output and a negative output; an output stage connected to the differential comparator, the output stage configured to (i) receive the positive output and the negative output at control electrodes of transistors of the output stage and, (ii) provide a single output in response to the positive output and the negative output; a first current source connected to the differential comparator and the output stage; a second current source selectively connected to the differential comparator and the output stage; a third current source connected to the differential comparator and the output stage; and a fourth current source selectively connected to the differential comparator and the output stage, wherein the first current source and the third current source are configured to supply power to (i) the differential comparator while the differential comparator is in a low-power state, and (ii) the output stage while the output stage is in a low-power state, and the second current source and the fourth current source are configured to periodically supply power (i) to transition the differential comparator from the low-power state of the differential comparator to a power-on state, and (ii) to transition the output stage from the low-power state of the output stage to a power-on state.