Patent ID: 8507992

Claim:
A semiconductor device comprising: a substrate comprising a first device region and a second device region; an n-type conductivity digital device present in the first device region comprising a first digital gate structure having at least a first digital device high-k dielectric present atop a first silicon surface of the substrate and at least one rare earth metal present atop the first digital device high-k dielectric, wherein an edge of the first digital device high-k dielectric is aligned with an edge of the at least one rare earth metal, and an n-type analog conductivity device having a first analog gate structure with at least a first analog device high-k dielectric present atop a second silicon surface, wherein a thickness of an first analog gate dielectric structure including the first analog device high-k dielectric of the n-type analog conductivity device is greater than a thickness of first digital gate dielectric structure including the first digital device high-k dielectric of the n-type conductivity digital device, wherein an edge of the first analog gate dielectric structure is horizontally offset from an edge of an overlying gate conductor of the first analog gate structure; and a p-type conductivity digital device present in the second device region comprising a second digital gate structure having a second digital device high-k dielectric, the second digital gate structure atop a first device channel including a Ge-containing layer, wherein the first high-k dielectric digital device has a greater charge than the second digital device high-k dielectric, wherein an edge of the second digital device high-k dielectric is aligned with an edge of an overlying gate conductor of the second digital gate structure, and a p-type analog conductivity device having a second analog gate structure with at least a second analog device high-k dielectric present atop a second device channel of a Ge-containing layer, wherein a thickness of a second analog gate dielectric structure including the second analog device high-k dielectric of the p-type analog conductivity device is greater than a thickness of second digital gate dielectric structure including the second digital device high-k dielectric of the p-type conductivity digital device, wherein an edge of the second analog gate dielectric structure is horizontally offset from an edge of an overlying gate conductor of the second analog gate structure.