Patent ID: 8921166

Claim:
A method for use in fabricating a chip, the method comprising: providing a first functional area and a second functional area of a layer; and adding at least one dummy structure, wherein the adding comprises: determining a size and placement of the at least one dummy structure as a function of a width of at least one of the first functional area and the second functional area and a density and location of the first functional area and the second functional area within a predetermined distance of a location; and adding a first plurality of dummy structures having a first size at a first location and a second plurality of dummy structures having a second size less than the first size at a second location adjacent the first location, wherein the first plurality of dummy structures is closer to the first functional area than the second plurality of dummy structures, wherein, in a region surrounding the first functional area, the number of first plurality of dummy structures is less than the number of second plurality of dummy structures.