Patent ID: 7323379

Claim:
A method of forming an embedded DRAM system including DRAM cells and logic transistors on the same semiconductor substrate, each of the DRAM cells having an access transistor and a capacitor structure, the method comprising of: forming a first cavity having a first depth in a first region of the semiconductor substrate; forming a second cavity having a second depth in a second region of the semiconductor substrate, wherein the second cavity is deeper than the first cavity; forming a first dielectric region in the first cavity and a second dielectric region in the second cavity; etching a portion of the second dielectric region to create a third cavity that exposes a sidewall of the second cavity; forming a first dielectric layer over the upper surface of the semiconductor substrate and the exposed sidewall of the second cavity; forming a second dielectric layer over the upper surface of the semiconductor substrate; forming an electrode layer over the first dielectric layer and the second dielectric layer; and patterning the electrode layer to form a capacitor electrode of the capacitor structure and a gate electrode of the access transistor, wherein the capacitor electrode is located over the first dielectric layer, and extends over the upper surface of the semiconductor substrate and the sidewall of the second cavity, the capacitor electrode being at least partially located in the third cavity, and wherein the gate electrode is located over the second dielectric layer.