Patent ID: 7720139

Claim:
An equaliser circuit for equalising first samples of an asynchronously over-sampled signal, the equalising circuit comprising: a first input for inputting the first samples into an FIR filter, the FIR filter having a set of filter coefficients; an output for outputting the equalised first samples; a second input for inputting an error signal, the error signal being indicative of a deviation of a second sample of an equalised synchronous signal from one of a set of predefined signal levels, the error signal having a delay with respect to a current first sample at the first input, the sequence of the first samples used for the adaptation having substantially the same delay, the equalised synchronous signal being reconstructed from the equalised first samples; a circuit component for adaptation of the filter coefficients based on the error signal and a sequence of the first samples, and operable for adaptation of at least one of the filter coefficients by determining the sign of the error signal in accordance with the sign of one of the first samples of the sequence and updating the one of the filter coefficients on the basis of the absolute value of the error signal and its sign.