Patent ID: 7167534

Claim:
An oversampling clock recovery circuit comprising: first through 2N-th phase comparators (PD 1 to PD 2 N) with a one-to-two correspondence with one bit of an input data, where N represents a predetermined positive integer, each of said first through said 2N-th phase comparators having an UP signal output terminal for producing an UP signal and a DOWN signal output terminal for producing a DOWN signal, each of N odd numbered phase comparators (PD(2n+1)) corresponding to a transition point of said input data, where n represents an integer between 0 to (N−1), both inclusive; and a majority circuit ( 10 ) for deciding by majority on UP signals and DOWN signals supplied from said first through said 2N-th phase comparators, said majority circuit having 2N UP signal input terminals and 2N DOWN signal input terminals, said N odd numbered phase comparators (PD(2n+1)) having N DOWN signal output terminals connected to N DOWN signal input terminals of said majority circuit and N UP signal output terminals connected to N UP signal input terminals of said majority circuit, N even numbered phase comparators (PD(2n+2)) having N DOWN signal output terminals connected to N UP signal input terminals of said majority circuit and N UP signal output terminals connected to N DOWN signal input terminal of said majority circuit.