Patent ID: 7480199

Claim:
A method of operating a DRAM device in either a high power, full density mode or a low power, reduced density mode, comprising: reordering each row address applied to the DRAM device by making the N most significant bits of the row address the N least significant bits of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address, where N is a positive integer; when operating in the full density mode, accessing rows of memory cells in an array according to the reordered row address; when operating in the full density mode, refreshing the memory cells in the array at a first rate; when operating in the reduced density mode, accessing rows of memory cells in the array according to the reordered row address, and, when accessing each row of memory cells, also accessing 2 N −1 adjacent rows of memory cells; when operating in the reduced density mode, refreshing memory cells in the memory array at a second rate that is slower than the first rate; and when switching from operation in the full density mode to operation in the reduced density mode, transferring data from each row of the array in which data are stored to the 2 N −1 adjacent rows of memory cells.