Patent ID: 7888218

Claim:
A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising: forming a charge trapping dielectric layer over the substrate; forming a first polysilicon layer over the charge trapping dielectric layer; forming a hardmask over the first polysilicon layer; patterning the hardmask to form hardmask features having first spacings having a first width therebetween; forming first sidewall spacers adjacent to the hardmask features, with respective pairs of sidewall spacers defining second spacings having a second width less than the first width therebetween; patterning the first polysilicon layer to form first polysilicon features defining third spacings having the second width therebetween; patterning the charge trapping dielectric layer to define fourth spacings having the second width therebetween; forming second sidewall spacers adjacent to the patterned charge trapping dielectric layer and the first polysilicon layer features to define fifth spacings having a third width therebetween that is less than the second width; performing bitline implants through the fifth spacings, to establish buried bitlines within the substrate having respective bitline widths corresponding to the third width; performing a pocket implant through the fifth spacings into the semiconductor substrate; removing the second sidewall spacers; performing a dielectric deposition to fill in spacings between the patterned charge trapping dielectric layer and first polysilicon features with one or more dielectric materials; performing a chemical mechanical polishing to remove excess dielectric based materials after performing the dielectric deposition; forming a second polysilicon layer over the first polysilicon features and the dielectric material disposed therebetween; and patterning the second polysilicon layer to form wordlines.