Patent ID: 7088617

Claim:
A nonvolatile semiconductor storage device comprising: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a charge storage layer and a control gate, a first selection transistor disposed at one end of the memory cell and having a first selection gate, and a second selection transistor disposed at the other end of the memory cell and having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate of the memory cell of each of the memory cell units, a first selection gate line connected to the first selection gate of the first selection transistor of each of the memory cell units, and a second selection gate line connected to the second selection gate of the second selection transistor of each of the memory cell units; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the common control gate line is connected commonly to the control gate lines of at least two of the memory cell unit groups selected in a first combination, wherein the first common selection gate line is connected commonly to the first selection gate lines of at least two of the memory cell unit groups selected in a second combination different from the first combination, wherein the second common selection gate line is connected commonly to the second selection gate lines of at least two of the memory cell unit groups selected in a third combination different from the first and second combinations; and wherein the memory cells in the respective memory cell unit groups are each uniquely selected on the basis of a combination of the common control gate line and the first and second common selection gate lines.