Patent ID: 7336550

Claim:
A semiconductor memory device comprising a plurality of memory cell blocks, each comprising a plurality of memory cells and a set of word lines configured to access cells from the plurality of memory cells, the semiconductor memory device comprising: a redundancy signal generator configured to output a redundancy signal indicating whether any of the plurality of memory cell blocks includes one or more defective cells and, if there are one or more defective cells in at least one cell block, configured to output address signals of repair word lines corresponding to the one or more defective cells; a redundancy signal decoder configured to decode the redundancy signal and the address signals of the repair word lines and based thereon to output word line enable signals associated with normal word lines that do not relate to the one or more defective cells; and a set of normal word line drivers configured to selectively enable the normal word lines and not to enable the repair word lines in response to the word line enable signals.