Patent ID: 7529126

Claim:
A data processing apparatus comprising: a memory array including a plurality of memory cells, a plurality of bit lines, a plurality of voltage supply circuits, and a plurality of current control circuits; and a power circuit to supply a voltage to each of the voltage supply circuits, wherein for each said bit line, a corresponding voltage supply circuit is used for determining a voltage level applied to the bit line in accordance with data to be programmed to a memory cell coupled to the bit line, and wherein each said current control circuit comprises a first circuit coupled between one of the bit lines and the power circuit and maintains a first current flowing into the bit line at a first current level, and a second circuit coupled between one of said bit lines and one of said voltage supply circuits and maintains a current flowing at the memory cell by flowing out the current from the bit line to the voltage supply circuit at a second current level during a programming period of the memory cell.