Patent ID: 8670276

Claim:
A mass storage device coupled to a host and comprising a storage media comprising a plurality of first memory devices including a first memory, and further having a first interface circuit, the storage media further comprising a plurality of NAND flash memory devices including NAND flash memory, the plurality of first memory devices being distinct from the plurality of NAND flash memory devices and the first memory being distinct from the NAND flash memory, the storage device partitioned into a plurality of Logical Units (LUNs) based on the capabilities and resources of the mass storage device, the LUNs being made of a combination of at least a portion of the first memory and at least a portion of the NAND flash memory, each LUN being mapped to a particular type of media or collection of different types of media in accordance with its utilization; and a controller having a second interface circuit coupled to the first memory device and the NAND flash memory device, wherein the plurality of LUNs is employed by the host to optimize its performance based on the attributes of the LUNs.