Patent ID: 7404050

Claim:
A method of operating a memory device, the memory device including at least one memory module, the method comprising: a) receiving a command and write data signal in a first memory module; b) transmitting a read data signal from the first memory module; c) receiving an input clock signal in the first memory module; d) regenerating the input clock signal in a clock synthesizer unit of the memory module to produce a regenerated input clock signal of the first memory module, wherein the clock synthesizer unit comprises a digitally implemented phase-locked loop, e) synchronizing the read data signal transmitted from the first memory module to the regenerated input clock signal of the first memory module; and wherein said regenerating of the input clock signal further comprises, generating a digital phase difference signal on the basis of an input clock signal of the phase-locked loop and a feedback clock signal, receiving the phase difference signal, and controlling a digitally controlled oscillator in response to the filtered phase difference signal.