Patent ID: 7256652

Claim:
A differential receiver circuit: a first input transistor, wherein a first terminal of the first input transistor is coupled to a first bias node a second input transistor, wherein a first terminal of the second input transistor is coupled to a second bias node; a first bias transistor, wherein a first terminal of the first bias transistor is coupled to the first bias node; a second bias transistor, wherein a first terminal of the second bias transistor is coupled to the second bias node; a first current source coupled to provide current to the first bias node; and a second current source coupled to provide current to the second bias node; wherein the differential receiver circuit is coupled to a first voltage node and a second voltage node, wherein the first and second current sources are coupled to provide current to the first and second bias nodes, respectively, such that the voltage present on the first and second bias nodes remains within approximately a threshold voltage of a midpoint between a voltage present on the first voltage node and a voltage present on the second voltage node.