Patent ID: 8238138

Claim:
A semiconductor memory device comprising: a bit line and a sense line; a data storage element having a data storage state changing in accordance with a voltage applied to said bit line; a first switch for controlling connection of said sense line to said bit line; a data latch circuit having a second data holding node and a first data holding node connected to said sense line; and a second switch for controlling connection of said second data holding node of said data latch circuit to said bit line; wherein at a data update time, said second switch is put in a turned-on state in order to apply a data update pulse to said data storage element on the basis of information appearing on said second data holding node; afterwards, said first switch is put in a turned-on state; and then, said data latch circuit carries out a read-to-verify operation to detect an electric potential appearing on said bit line by taking a reference electric potential supplied to said second data holding node as a comparison reference and then makes use of data latched after said read-to-verify operation as information for determining whether or not it is necessary to apply a next data update pulse to said data storage element.