Patent ID: 8482071

Claim:
An electrostatic discharge (ESD) protection device comprising: an MOS transistor comprising a gate, a drain and a source disposed in a first semiconductor region; a node designated for ESD protection electrically connected to the drain; and a diode coupled between the gate and the source, the diode comprising a second semiconductor region disposed within the first semiconductor region, wherein the second semiconductor region of the diode is directly connected only to the gate of the MOS transistor via a connection, and is isolated from other components in the ESD protection device besides the gate of the MOS transistor, the connection, and the first semiconductor region, the diode would be reverse biased if the MOS transistor were in an active operating region, the ESD protection device is configured to be triggered via an internal parasitic drain to gate capacitance of the MOS transistor and without a capacitor external to the MOS transistor, and the gate of the MOS transistor is biased only by a reverse diode current of the diode after an ESD event.