Patent ID: 7876623

Claim:
A memory device, comprising: an array of non-volatile memory cells; one or more sense amplifier circuits, wherein each of the one or more sense amplifier circuits comprises: a plurality of data latches each coupled to the array of non-volatile memory cells and configured to latch a programmed state of one or more of the non-volatile memory cells in response to a read operation performed on the one or more non-volatile memory cells; and a plurality of cache latches, wherein each cache latch is configured to store data to be stored in the memory array during a program operation; a first summation circuit coupled to the plurality of data latches and configured to generate a first summation of data stored in the plurality of data latches; a second summation circuit coupled to the plurality of cache latches and configured to generate a second summation of data stored in the plurality of cache latches; and a program voltage adjustment circuit, wherein the program voltage adjustment circuit is configured to compare the first summation and the second summation and generate a program voltage change in response to a comparison of the first summation and the second summation.