Patent ID: 8004879

Claim:
A semiconductor memory device comprising: a plurality of word lines; a plurality of digit line pairs each comprising first and second digit lines; a plurality of memory cells provided in a matrix fashion corresponding to each node of said plurality of word lines and said plurality of digit line pairs; and a plurality of column selection lines provided corresponding to each of said plurality of digit line pairs; wherein each of said plurality of memory cells comprises: a first inverter having an input terminal coupled with a first node and an output terminal coupled with a second node; a second inverter having an input terminal coupled with said second node and output terminal coupled with said first node; a first access transistor coupled between said first digit line and said first node; a second access transistor coupled between said second digit line and said second node; a first conductivity type first transistor coupled between gates of said first and said second access transistors and said column selection line, and having a gate coupled with said word line; and a second conductivity type first transistor coupled between gates of said first and said second access transistors and a fixed potential, and having a gate coupled with said word line.