Patent ID: 7180768

Claim:
A semiconductor memory device comprising a plurality of word lines placed along a first direction, a plurality of bit line pairs placed along a second direction intersecting said first direction, and a plurality of memory cells placed at intersections of said plurality of word lines and plurality of bit line pairs, each of said plurality of memory cells including: first and second nodes; a first PMOS transistor having a source-drain path between said first node and one of said bit line pairs, in which the gate is connected to said word line; a second PMOS transistor having a source-drain path between said second node and another said bit line pair, in which the gate is connected to said word line; a first NMOS transistor, in which the drain is connected to said first node and the gate is connected to said second node; and a second NMOS transistor, in which the drain is connected to said second node and the gate is connected to said first node, wherein a first voltage is applied to a word line of at least one of said plurality of memory cells selected in read mode, and wherein a second voltage less than said first voltage is applied to said word line of at least one of said plurality of memory cells selected in write mode.