Patent ID: 7558996

Claim:
A method implemented in a device under test having multiple scan chains interposed with functional logic of the device, the method comprising: (a) scanning input bit patterns into the scan chains; (b) performing a first set of M−1 LBIST test cycles, where M is a positive integer greater than 1, and wherein each of the test cycles in the first set comprises a functional phase in which the input bit patterns are propagated through the functional logic, followed by a scan shift phase in which resulting bit patterns captured in the scan chains are shifted out of the scan chains and accumulated in a MISR; (c) in an Mth LBIST test cycle, inhibiting shifting of the captured bit patterns from the scan chains into the MISR; (d) exporting the captured bit patterns of the Mth test cycle from the scan chains to a memory external to the device.