Patent ID: 8838901

Claim:
A data processing system, comprising: a processor core; a cache memory hierarchy coupled to the processor core, the cache memory hierarchy including at least one upper level cache and a lowest level cache, wherein the lowest level cache includes a cache array, a cache directory, and a cache controller that controls read and write access to the cache array and updates the cache directory to maintain coherence, wherein the lowest level cache includes a virtual write queue formed of only a subset of the cache array; and a memory controller coupled to the lowest level cache and to a system memory forming a lowest level of storage addressable by a real address space of the processor core, wherein: the memory controller controls read and write access to the system memory; the memory controller includes a cache cleaner component and a physical write queue from which the memory controller writes data received from the lowest level cache to the system memory; the memory controller has visibility into the virtual write queue; the memory controller coordinates writeback to the system memory by: the cache cleaner component initiating cleaning accesses to the lowest level cache to place into the physical write queue copies of selected cachelines from the virtual write queue having spatial locality with data present in the physical write queue without removing the selected cachelines from the lowest level cache; and writing at least some of the copies of the selected cachelines and the data present in the physical write queue to the system memory in a write burst operation.