Patent ID: 7610471

Claim:
A data processor comprising a plurality of data processing circuits executing different instruction flows respectively, wherein each of the data processing circuits has a plurality of registers to which the instruction flows refer, and a flag bit showing a validity with respect to data kept in the plurality of registers on an individual register basis, when executing a first instruction for directing an operation for writing data in the register of the other data processing circuit, the data processing circuit confirms whether or not the register targeted for the direction of the writing operation according to the first instruction is invalid, waits for the register to be made invalid if the register is not invalid, and performs the writing operation after the register is made invalid, when executing a second instruction for providing a direction for invalidating data of the register referred to by use of the corresponding flag bit concurrently with the reference to the register, the data processing circuit suspends execution of the reference until the register is made valid if the register targeted for the direction of data invalidation by the second instruction is invalid, the data processing circuit performs control for invalidating the register to which a reference has been made after the second instruction has been executed, and the first and second instructions constitute an instruction set including a load instruction, an address generation instruction, a store instruction, and a memory access instruction.