Patent ID: 7292953

Claim:
A semiconductor memory device for performing an off chip driver (OCD) calibration control operation to adjust a data output impedance comprising: a decoder configured to generate an OCD default control signal, an OCD operation signal, and plural data in response to a column address strobe (CAS) signal, and a result of decoding an address signal; a code generator for receiving plural-bit data to generate an OCD control code; a first circuit for receiving the OCD control code and the OCD operation signal to generate a plurality of impedance adjustment control signals; and a second circuit for receiving the plural-bit data and adjusting the data output impedance in response to the plurality of impedance adjustment control signals, wherein the decoder includes an extended mode register set (EMRS) decoder for decoding the address signal to generate an OCD period signal and a CAS signal generator for outputting the OCD operation signal to the first circuit for receiving the OCD control code in response to the OCD period signal.