Patent ID: 7461212

Claim:
A cache system, comprising: a processing device operative to access a main memory device; a primary cache coupled to said processing device, said primary cache being accessible from said processing device at faster speed than the main memory device; and a secondary cache coupled to said processing device via said primary cache, said secondary cache being accessible from said processing device at faster speed than the main memory device, wherein said primary cache and said secondary cache are configured such that first data is stored as a data entry in each of said primary cache and said secondary cache when the first data is read from the main memory device in response to access from said processing device, and such that second data in the secondary cache is invalidated without invalidating the second data in the primary cache when a need arises to replace a cache line corresponding to the second data in the secondary cache upon a miss in the secondary cache in response to access from said processing device, thereby breaking an inclusion condition between the primary cache and the secondary cache at a time of data replacement in the secondary cache.