Patent ID: 8745557

Claim:
A computer-implemented method comprising: receiving by a first processor an executable, source graphical model configured to execute over one or more model steps, the model having a target block configured to: receive parallel input data, and perform a function on the parallel input data, locating the target block in the source graphical model; and generating by the first or a second processor a hardware description for at least a portion of the source graphical model that includes the target block, the generated hardware description including: a hardware description of a serializer, the hardware description of the serializer configured to receive the parallel input data and convert the parallel input data into a serial input data stream, a hardware description of the function performed by the target block, the hardware description of the function performed by the target block configured to: receive the serial input data stream from the serializer, generate a serial data output stream, and operate, at least in part, at a higher clock rate relative to a first clock rate that corresponds to the one or more model steps.