Patent ID: 7123001

Claim:
A delay-locked loop (DLL) circuit comprising: a first DLL; and a second DLL, wherein the first DLL comprises: a first phase comparator configured to compare a phase of a first feedback clock with a phase of a second reference clock of the second DLL to determine a first phase difference; and a first variable delay element configured to receive input relating to the first phase difference determined by the first phase comparator and to delay a first reference clock by an amount that depends on the determined first phase difference; and wherein the second DLL comprises: a second phase comparator configured to compare a phase of a second feedback clock with a phase of the first reference clock of the first DLL to determine a second phase difference; and a second variable delay element configured to receive input relating to the second phase difference determined by the second phase comparator and to delay said second reference clock by an amount that depends on the determined second phase difference.