Patent ID: 7233530

Claim:
A system for reducing over-erased memory cells, comprising: N sense amplifiers, N being an integer; at least one memory sector segmented by the N sense amplifiers into N erase retry units with one erase retry unit of the memory sector corresponding with one sense amplifier, the memory sector having a starting address and an ending address; and a data input buffer system, including, (a) at least N sticky buffers for showing whether any of the N erase retry units of the memory sector are erased after the erase process of the erase operation, the N sticky buffers corresponding with the N erase retry units and the N sense amplifiers with at least one sticky buffer corresponding with one erase retry unit of the memory sector and one sense amplifier, the erase process of the erase operation being followed by a verification process of the erase operation, the erase operation including at least one erase process and at least one verification process; and (b) a mask register for accessing the N sticky buffers to identify which erase retry units fail to be erased after the erase process of the erase operation.