Patent ID: 7356648

Claim:
A memory device, comprising: a buffer memory having a plurality of addressable memory registers; the buffer memory capable of being partitioned into a plurality of buffer regions; a counter having a plurality of storage registers, each storage register being associated with a respective buffer region of the buffer memory; a logic network for writing and reading data into and out of the buffer memory, the logic network for partitioning the buffer memory into the plurality of buffer regions, wherein the logic network writes/reads data from a plurality of unique data classes into/from the plurality of buffer regions such that each data class is uniquely written into and uniquely read from a different buffer region, and wherein the logic network increments a value in a respective storage register associated with a respective buffer region each time that buffer region reaches a predetermined usage level; and a timer for periodically sending a timing signal to the logic network, the period of the timing signal defining a timing window; wherein in response to the timing signal, the logic network: recalls the respective values from the storage registers; whereby the respective value stored in each storage register indicates a number of times that the respective buffer region reaches the predetermined usage level within the timing window; and re-partitions the buffer memory according to the respective value having a highest value such that a more utilized buffer region is assigned more of the addressable memory registers.