Patent ID: 8539312

Claim:
A logic die configured to couple to memory device dice through a plurality of through silicon vias, the logic die comprising: an error checking system configured to generate a plurality of error checking bits from write data received at the logic die for storage in the memory device dice, the error checking system configured to transfer the error checking bits from the logic die to the memory device dice in a serial burst of parallel error checking bits using respective through silicon vias, the error checking system further being structured to receive read data from the memory device dice and corresponding error checking bits from the memory device dice in a serial burst of parallel error checking bits using the respective through silicon vias, the error checking system further being configured to use the received error checking bits to determine if the corresponding read data contains at least one erroneous read data bit; and a data encoding system configured to receive the write data and configured to use an encoding algorithm to encode the write data before the write data are transferred and to transfer to the memory device dice at least one data encoding bit indicative of the encoding of the write data, the at least one data encoding bit being transferred to the memory device dice using at least one of the respective through silicon vias through which the error checking system is configured to transfer the error checking bits.