Patent ID: 8726491

Claim:
A method of forming a STT-RAM device on a substrate wherein said substrate has a via stud formed in a first dielectric layer and an overlying bottom electrode layer that contacts said via stud and has a planar top surface, comprising: (a) forming a dual-spin-filter (DSF) stack of layers on said planar top surface and above said via stud, said DSF stack of layers has a top surface and is comprised of: (1) a seed layer; (2) a first anti-ferromagnetic (AFM) layer. (3) a first pinned layer comprised of CoFeB; (4) a MgO tunnel barrier layer; (5) a free layer having a FM1/NCC/FM2 configuration wherein said FM1 and FM2 layers are made of Fe, Co, Ni, FeB, or crystalline CoFeB and said NCC layer is a nanocurrent channel layer comprised of M(Si) grains in an oxide, nitride, or oxynitride matrix where M is a metal; (6) a non-magnetic spacer; (7) a second pinned layer; (8) a second AFM layer; and (9) a capping layer wherein the seed layer, first AFM layer, first pinned layer, MgO tunnel barrier, free layer, non-magnetic spacer, second pinned layer, second AFM layer, and capping layer are sequentially formed on the bottom electrode; (b) annealing at a sufficient temperature to form a crystalline MgO layer and crystalline CoFeB layers; (c) patterning said DSF stack of layers and the bottom electrode layer to form a DSF structure and a bottom electrode above said via stud, said DSF structure has a top surface and sidewalls and an elliptical shape or another rounded shape in a plane parallel to the top surface of the bottom electrode; (d) depositing a second dielectric layer on the first dielectric layer and on the DSF structure; (e) planarizing the second dielectric layer such that the second dielectric layer becomes coplanar with the capping layer; and (f) forming a bit line on the second dielectric layer and on the capping layer.