Patent ID: 7638401

Claim:
A method of forming a memory device, the method comprising the steps of: forming an n-well and a p-well in a semiconductor substrate; forming a gate insulating layer over the semiconductor substrate; forming a layer of undoped polysilicon over the gate insulating layer; forming an insulating film over the undoped polysilicon layer; patterning the undoped polysilicon layer and the insulating film to form a first, second, and third plurality of undoped polysilicon gates each having an overlying insulating region; forming a side wall insulating region along the sidewalls of each of the first, second, and third plurality of undoped polysilicon gates; etching the overlying insulating regions to form a thinner insulating film over each of the first, second, and third plurality of undoped polysilicon gates; forming n-doped source/drain regions adjacent the first plurality of undoped polysilicon gates and simultaneously doping each of the first plurality of undoped polysilicon gates and the second plurality of undoped polysilicon gates through the thinner insulating films to form a first and a second plurality of doped polysilicon gates, and forming p-doped source/drain regions adjacent the third plurality of undoped polysilicon gates and simultaneously doping each of the third plurality of undoped polysilicon gates through the thinner insulating films to form a third plurality of doped polysilicon gates.