Patent ID: 7496866

Claim:
A method for optimizing pipeline structure placement in a circuit design according to a method for optimizing pipeline structure placement in a circuit design, comprising the steps of: initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design, further comprising the steps of: in identifying poor placements through a process of identifying circuits involved in a class of degenerate cases, and removing circuits having poor placements of said class of degenerate cases by unplacing them from the global placement solution and correcting other non-degenerate poor quality placements wherein correcting poor quality placements is accomplished using a further process step where said unplaced circuits are virtually replaced according to said placement algorithms which are executed against said global placement solution as an existing fixed global placement background for the remainder of the design, said virtual replacement generating an equilibrium point solution for said unplaced circuits “in-situ” within said existing Global placement solution for the remainder of the design.