Patent ID: 8779835

Claim:
A signal processing arrangement comprising: a signal processing stage that divides an input signal (Vin) applied to a signal input (In) of the signal processing stage into at least two subsignals (Vin_a, Vin_b) as a function of a signal amplitude (A) of the input signal (Vin), wherein the signal processing stage is a pre-amplifier (Pre_Amp) at which at least two amplifier outputs (Va, Vb) of which the at least two subsignals (Vin_a, Vin_b) are made available and is designed for parallel signal processing of the subsignals (Vin_a, Vin_b), and a reconstruction stage comprising an analog to digital converter (ADC) that weights and combines the at least two subsignals (Vin_a, Vin_b), is connected to the signal processing stage, and provides an output signal (Vout) which is a linear combination of the at least two processed subsignals (Vin_a, Vin_b) to reconstruct the input signal (Vin), wherein the output signal (Vout) is described by a linear function of the input signal (Vin).