Patent ID: 7760537

Claim:
A programmable ROM comprising: a SRAM cell which stores ROM data; and a control circuit which controls an operation of programming and reading the ROM data, the SRAM cell including, a first field effect transistor of a first conductivity type as a load having a source connected to a first power source terminal; a second field effect transistor of a second conductivity type having a source connected to a second power source terminal and a drain connected to a drain of the first field effect transistor; a third field effect transistor of the second conductivity type having a gate connected to a word line and used for data transfer between a first bit line and the drains of the first and second field effect transistors; a fourth field effect transistor of the first conductivity type as a load having a source connected to the first power source terminal; a fifth field effect transistor of the second conductivity type having a source connected to the second power source terminal and a drain connected to a drain of the fourth field effect transistor; and a sixth field effect transistor of the second conductivity type having a gate connected to the word line and used for data transfer between a second bit line and the drains of the fourth and fifth field effect transistors, wherein the gates of the first and second field effect transistors are connected to the drains of the fourth and fifth field effect transistors, the gates of the fourth and fifth field effect transistors are connected to the drains of the first and second field effect transistors, and the control circuit writes reverse data which is reverse to the ROM data into the SRAM cell, turns off the third and sixth field effect transistors after writing the reverse data, and applies stress to the first and fourth field effect transistors, when the control circuit programs the ROM data to the SRAM cell.