Patent ID: 7570611

Claim:
A data transfer arrangement comprising: a plurality of logic elements, the plurality of logic elements including a plurality of macro cells; a plurality of processing elements; a transfer element to transfer data in parallel between each logic element of the plurality of logic elements and each processing element of the plurality of processing elements, the transfer element including a circular shift register including a plurality of shift registers coupled in parallel in a circular arrangement, each shift register of the plurality of shift registers including a shift register of N bits, each shift register of the plurality of shift registers having a corresponding bit associated with such shift register, the corresponding bit to indicate that loading of data into such shift register has been completed, the plurality of shift registers including a first portion coupled to the plurality of macro cells, and a second portion coupled to the plurality of processing elements, the first and the second portions of the plurality of shift registers including a plurality of shift registers of N bits; and a clock to produce clock cycles, the clock coupled to the first portion and to the second portion of the plurality of shift registers, each shift register to transmit N bits of data to a next shift register in the circular shift register during a clock cycle, the clock operating to clear the corresponding bit for each of the corresponding shift registers of the plurality of shift registers, after M clock cycles, where M is a number of processing elements plus macro cells being coupled to the transfer element.