Patent ID: 7978559

Claim:
A semiconductor memory device comprising: a plurality of word lines; a plurality of pairs of bit lines and complementary bit lines; a plurality of memory cells, each memory cell being disposed at a region where a respective word line and a pair of a bit line and a complementary bit line cross each other; and a voltage control unit comprising a plurality of elements that are connected in series between a power voltage source and the memory cells and are switched on/off in response to a control signal that controls an operation of the memory cells, wherein the voltage control unit controls the voltage of the power voltage source to supply a controlled voltage to the memory cells, wherein the control signal comprises a power gating control signal and a write enable signal, wherein the voltage control unit further comprises: a logic gate that performs a logic operation on the power gating control signal and the write enable signal; and a plurality of second switches that are switched on/off in response to an output of the logic gate, and wherein the elements connected in series are each switched on/off in response to an output of a respective one of the plurality of second switches.