Patent ID: 8045382

Claim:
An erasing method for a flash memory device, comprising: erasing a plurality of memory cells of a selected memory block; and post-programming the erased plurality of memory cells to have a threshold voltage distribution with a lowest level that is in a voltage range that is near 0V, wherein the lowest level is a negative voltage that is near 0V, wherein post-programming the plurality of erased memory cells comprises: first post-programming the plurality of memory cells in the memory block in one operation wherein the memory block is first programmed as a unit by verify reading a result of the first post-programming with a predetermined verifying voltage; and second post-programming the plurality of memory cells in the memory block in groups according to word lines by verify reading a result of the second post-programming with a predetermined verifying voltage, wherein the memory block is second programmed in the unit of word line, wherein if there is an increase of voltage gap between a level of a control signal for controlling a precharging level of a selected bit line during a precharging period of the verify reading and a level of the control signal applied during a sensing period of the verify reading, recognizing the verifying voltage as a negative voltage, and wherein, during the sensing period, the verifying voltage is decreased and the level of the control signal applied is decreased.