Patent ID: 7210074

Claim:
An automated test equipment (ATE) that tests digital devices, said ATE comprising: a plurality of drive channels, each drive channel provides a bit of a data vector to a device under test (DUT) at a first predetermined time period; a plurality of receive channels, each receive channel latches in a receive bit of data from said DUT at a second predetermined time period, said second predetermined time period starting at a zero receive point; each one of said plurality of drive channels further comprises a first drive channel calibration circuit that adjusts a first drive channel programmable delay, in each drive channel, to deskew the plurality of drive channels with respect to a parasitic delay associated with each drive channel, so that each drive channel provides said bit of said data vector to said DUT during said first predetermined time period; and each one of said plurality of receive channels further comprises a first receive channel calibration circuit that adjusts a first receive channel programmable delay, in each receive channel, to deskew the plurality of receive channels with respect to a parasitic delay associated with each receive channel, so that each receive channel is calibrated to latch in said receive bit just after said zero receive point and within said second predetermined time period.