Patent ID: 6934349

Claim:
A phase detector configured to output an up signal when a first clock signal is ahead of a second clock signal in phase, and outputting a down signal when said first clock signal is behind said second clock signal in phase, said phase detector comprising: first, second, and third flip-flops; a flip-flop (F/F) control circuit which brings said first flip-flop to a reset state when at least one of said first and second clock signals has a first logic, brings said first flip-flop to a set state when both said second and third flip-flops are in the set state, brings said second flip-flop to the se state when said first clock signal has a second logic and said first flip-flop is in the reset state, brings said second flip-flop to the reset state when both said second and third flip-flop are in set state, brings said third flip-flop to the set state when said second clock signal has a second logic ad said first flip-flop is in reset state, and brings said third flip-flop to the reset state when both said second and third flip-flops are in the set state; and an up-down signal output circuit configured to output said up signal and down signal based on the outputs of said second and third flip-flops.