Patent ID: 7960238

Claim:
A method for manufacturing an integrated circuit including an NMOS transistor, comprising: providing a substrate having a semiconductor surface; forming a gate stack comprising forming a gate dielectric then a gate electrode on said gate dielectric, wherein a channel region is located in said semiconductor surface below said gate stack; implanting a first In implant at a first energy; after said first In implant, implanting a second In implant at a second energy, wherein said first In implant together with said second In implant form an In region having a retrograde profile under at least a portion of said channel region, and further wherein said second energy is at least 5 keV more than said first energy; and forming source and drain regions; wherein said method is exclusive of any annealing at 800° C. or more between said first In implant and said second In implant; wherein said first In implant and said second In implant are both performed before forming said gate stack; and further wherein said In region covers an entire length of said channel region.