Patent ID: 7707521

Claim:
A layout architecture of a standard cell, suitable for an integrated circuit, comprising: a substrate; a first conductor, arranged on the substrate for transmitting a first voltage; a second conductor, arranged on the substrate for transmitting a second voltage; a third conductor, arranged on the substrate for transmitting a third voltage; a fourth conductor, arranged on the substrate for transmitting a fourth voltage; a first device region, arranged on the substrate and adjacent to the first conductor; a second device region, arranged on the substrate, adjacent to the first device region, and beneath the second conductor; a third device region, arranged on the substrate, adjacent to the second device region, and beneath the third conductor; and a fourth device region, arranged on the substrate and between the third device region and the fourth conductor, wherein each of the first, the second, the third, and the fourth conductors is parallel to each other, the first device region is arranged between the first conductor and the second device region, the second device region is arranged between the first and the third device regions, and the third device region is arranged between the second and the fourth device regions.