Patent ID: 7439777

Claim:
A sampling circuit comprising: a buffer having an input for receiving an input signal to be sampled, the buffer driving at its output a buffered version of the input signal; a holding capacitor for holding a voltage representative of a sampled, buffered input signal, the holding capacitor having first and second nodes; first, second and third switches, the first switch being connected between the buffer output and the first node of the holding capacitor, the first node of the holding capacitor for providing the sampled output voltage, and the second switch being connected between the second node of the holding capacitor and a first reference voltage, and the third switch being connected between the second node of the holding capacitor and a second reference voltage; a multi-phase oscillator for providing one or more clock signals, one of which operates the second switch; a control circuit that receives the one or more rotary clock signals and provides timing pulses for opening and closing the first switch and third switches, wherein the first switch and second switch are closed during sampling of the input signal and the second switch is opened to end the sampling, and wherein, after the second switch is opened, the control circuit closes the third switch to bias the voltage on the charging capacitor with the second reference voltage; and a fourth switch connected between the second node of the holding capacitor and the first reference voltage; wherein, while the second switch is open and before the second switch is closed, the control circuit closes the fourth switch during an interval to cause the voltage on the second node of the holding capacitor to be substantially the same as the first reference voltage.