Patent ID: 7442415

Claim:
A method of forming a layer of high-k dielectric gate oxide in an integrated circuit comprising: preparing a silicon substrate, including forming an H-terminated surface on the silicon substrate; forming a high-k dielectric layer by a sequence of ALD cycles and elevated temperature annealing including: depositing a first layer of metal ligand by an ALD cycle with a metal nitrate precursor to form a metal oxide layer; and depositing a second layer of metal ligand by ALD cycle with a non-oxygen containing metal chloride precursor to form a metal oxide layer; repeating said depositing a first layer of metal ligand and said depositing a second layer of metal ligand N times to form a layer of metal oxide having a near-critical thickness; annealing the substrate and the metal oxide layers in an elevated temperature annealing process every N ALD cycles; repeating the sequence of ALD cycles and elevated temperature annealing until a high-k dielectric metal oxide layer of desired thickness is formed; annealing the structure in a final annealing step; and completing the integrated circuit.