Patent ID: 8587023

Claim:
A guard ring system in a semiconductor substrate for protecting an integrated circuit comprising: a first PMOS device formed within an N-well in the substrate, wherein the substrate is coupled to a first voltage; a first guard ring including a first NMOS device with its gate coupled to the first voltage and its source and drain coupled to a second voltage which is higher than the first voltage to form a first N+ guard ring and a second N+ guard ring, respectively, wherein the first NMOS device is formed within said N-well and is disposed adjacent to the first PMOS device; a second NMOS device formed outside the N-well; and a second guard ring formed between the first PMOS device and the second NMOS device, wherein the second guard ring is disposed outside the N-well and comprises a second PMOS device with its gate coupled to the second voltage and its source and drain coupled to the first voltage to form a first P+ guard ring and a second P+ guard ring, respectively.