Patent ID: 8386545

Claim:
A system which uses common adder circuitry to perform either one of a horizontal minimum instruction and a sum of absolute differences instruction, comprising: a plurality of digital values which comprises a first set of digital values and a second set of digital values for the sum of absolute differences instruction, and which otherwise comprises a plurality of digital value pairs each comprising an upper digital value and a lower digital value for the horizontal minimum instruction; a plurality of adders, each comparing a first digital value with a second digital value and providing a corresponding one of a plurality of absolute difference values and a corresponding one of a plurality of carry outputs; a sum circuit which sums corresponding groups of said plurality of absolute difference values to provide a plurality of sum of absolute differences values; said plurality of adders comprising a plurality of adder pairs, each adder pair comprising an upper adder and a lower adder in which said upper adder provides a corresponding one of a plurality of propagate outputs; a compare circuit which combines said plurality of carry outputs and said plurality of propagate outputs to determine a minimum one of said plurality of digital value pairs; and a routing circuit which routes each of said plurality of digital value pairs to at least one of said plurality of adder pairs in order to compare each digital value pair with every other digital value pair when the horizontal minimum instruction is indicated, and which otherwise routes said first and second sets of digital values to said plurality of adders to determine an absolute difference between each digital value of said first set of digital values with a corresponding digital value of each of sequential groups of digital values of said second set of digital values when the sum of absolute differences instruction is indicated.