Patent ID: 7391653

Claim:
An operation method for a twin MONOS memory comprising: providing an array of memory cells comprising: polysilicon control gates on a substrate having an oxide-nitride-oxide (ONO) layer underlying said control gates wherein said nitride portion of said ONO layer underlying said control gates provides memory storage and having a channel in said substrate underlying each of said control gates; memory diffusions within said substrate between each two of said control gates wherein said memory diffusions are connected to adjacent diffusions alternately by a local wiring overlying said substrate; and metal bit lines crossing said control gates and isolated by shallow trench isolation (STI) lines; selecting a memory cell from said array of memory cells by a bit line, a control gate line, and a pair of selected control gates at a bit side and at a source side of said selected memory cell; and programming said selected memory cell by multi-level programming comprising: applying a high voltage to one of said pair of selected control gates and a low voltage on a channel of said selected control gate to eject electrons stored in nitride portion of said ONO layer underlying said selected control gate through said top oxide portion of said ONO layer; and controlling a threshold voltage of said selected memory cell by adjusting a difference of provided voltages of one of said pair of selected control gates of said selected memory cell and a channel of said selected memory cell wherein said difference is adjusted by adjusting the channel voltage provided by said control gate of said selected memory cell or by said bit line of said selected memory cell.