Patent ID: 8572469

Claim:
An apparatus comprising: a plurality of memories; a plurality of turbo decoders configured to decode a turbo coded signal having an information block length, L, such that the plurality of turbo decoders including at most L turbo decoders; and a processing module, coupled to the plurality of memories and the plurality of turbo decoders, configured to perform contention-free mapping between the plurality of memories and the plurality of turbo decoders during a plurality of decoding cycles; and wherein: during at least one of the plurality of decoding cycles: a first subset of the plurality of turbo decoders is configured to process information from a subset of the plurality of memories, such that each turbo decoder of the first subset of a plurality of turbo decoders processing respective information from a respective, corresponding one memory of the subset of the plurality of memories, to generate updated information; and a second subset of the plurality of turbo decoders is configured to perform dummy decoding; and the apparatus is configured to employ the updated information to generate estimates of information bits encoded within the turbo coded signal.