Patent ID: 7352225

Claim:
An apparatus including DC offset reduction circuitry, comprising: switching circuitry responsive to a control signal by alternately allowing and interrupting conveyance of at least one of first and second AC input signals having mutually lower and higher magnitudes, respectively; signal mixing circuitry coupled to said switching circuitry and responsive to reception of said first and second AC input signals by providing a product signal having a magnitude with a first DC component and a first plurality of signal components related to said first and second AC input signals, wherein said signal mixing circuitry comprises Gilbert multiplier circuitry; signal summing circuitry coupled to said signal mixing circuitry and responsive to said product signal and a DC compensation signal by providing a sum signal having a magnitude with a second DC component and said first plurality of signal components related to said first and second AC input signals; and signal filter circuitry coupled to said signal summing circuitry and responsive to said sum signal by providing an output signal having a magnitude with a third DC component and a second plurality of signal components related to said first and second AC input signals; wherein said DC compensation signal has a magnitude related to a sum of said first DC component and at least one of said second plurality of signal components related to said second AC input signal, and said third DC component is approximately zero.