Patent ID: 8829587

Claim:
A flash memory device, comprising: a semiconductor substrate, a gate stack formed on the semiconductor substrate; a channel region below the gate stack; spacers outside the gate stack; and source/drain regions outside the channel region and in the semiconductor substrate, wherein the gate stack comprises: a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer and inner walls of the spacers; a second gate dielectric layer covering a surface of the first conductive layer; and a second conductive layer covering a surface of the second conductive gate dielectric layer, wherein the first conductive layer, the second gate dielectric layer, and the second conductive layer are patterned to form a top part of the gate stack above said spacers such that a cross section of the second conductive layer has a T-shaped profile, wherein a length of the top portion of the T-shaped profile is smaller than a distance between outer walls of the spacers.