Patent ID: 6871152

Claim:
An eye diagram analyzer comprising: a clock signal waveform delay circuit having an input for receiving a clock signal and an output producing a delayed clock signal that is delayed by a selected first amount and whose transitions in a selected direction serve as a time reference; a threshold detector having a variable threshold, an input for receiving a data signal to be measured as an eye diagram and having an output producing a logical data signal; a variable data signal waveform delay circuit having an input coupled to receive the logical data signal and an output producing a delayed logical data signal whose amount of delay is a swept second amount that can range from less than to more than first amount of delay; a transition detection circuit coupled to the delayed clock signal and to the delayed logical data signal, and having an output producing a transition signal indicative of a transition in the delayed logical data signal occurring during a selected length of time subsequent to a transition in the selected direction within the delayed clock signal; a counter coupled to the transition signal and that counts occurrences thereof; and a memory whose content is organized as an eye diagram data structure indexed by the signed difference in the first and second amounts of delay, by the variable threshold, and that stores in an indexed location the number of counted occurrences that the data signal occupied the indexed location with an eye diagram.