Patent ID: 7724756

Claim:
A data packet input/output (I/O) buffer for a data packet communications system, comprising: a first-in first-out (FIFO) buffer for storing data packets; and a FIFO buffer controller, the FIFO buffer controller comprising: an ingress monitor and an egress monitor that monitor contents of the FIFO buffer; a state table updated by the ingress monitor with a number of bytes received by the FIFO buffer and updated by the egress monitor with a number of bytes transmitted by the FIFO buffer; and a scheduler that responds to an end-of-packet indication being stored in the FIFO buffer by transmitting a data packet that corresponds to the end-of-packet indication and, in the absence of an end-of-packet indication transmits a partial data packet from the FIFO buffer when an ingress FIFO data rate is less than an egress I/O data rate and a current fill level of the FIFO buffer exceeds a threshold.