Patent ID: 8349723

Claim:
A method comprising: forming a conductive stud inside a first dielectric layer; forming one or more conductive paths inside a second dielectric layer, said second dielectric layer being on top of said first dielectric layer, wherein said one or more conductive paths being substantially close to a region of said second dielectric layer remaining on top of a top surface of said conductive stud; forming a via hole on top of and exposing said top surface of said conductive stud, said via hole exposing at least a portion of sidewalls of said one or more conductive paths; depositing a conductive liner at a bottom and sidewalls of said via hole; and depositing a conductive material in said via hole forming a via, said via being in contact with said one or more conductive paths via said conductive liner, wherein forming said conductive stud comprises forming said conductive stud on top of and being in contact with a contact location of a semiconductor device that is created in a semiconductor substrate with said semiconductor substrate being underneath said first dielectric layer.