Patent ID: 7532052

Claim:
A clock duty changing apparatus changing a duty ratio of an input clock signal with nearly 50% duty ratio to a target value being externally supplied and outputting the input clock signal thereinafter as an output signal, comprising: a duty regulation circuit including a delay selection circuit and an operation circuit, the delay selection circuit being configured to generate a delay signal generated by delaying the input clock signal by delay time determined based on a first control signal and a second control signal, the first control signal being externally supplied to the apparatus in order to designate the target value, the second control signal being generated in the apparatus, the operation circuit being configured to generate the output clock signal by a logic operation using the delay signal and the input clock signal; a duty comparison circuit determining whether or not the duty ratio of the output clock signal matches the target value; and a duty correction circuit generating the second control signal depending on the determination result made by the duty comparison circuit, the second control signal indicating a correction amount of the delay time given to the delay signal so that mismatch between the duty ratio of the output clock signal and the target value is reduced.