Patent ID: 7185176

Claim:
A SIMD (Single Instruction Multiple Data) processor for performing a SIMD operation on a plurality of data pairs, wherein each data pair of the plurality of data pairs is made up of one piece of data belonging to a first data group and one piece of data belonging to a second data group, and at least one data pair among the plurality of data pairs is made up of pieces of data in different positions of the first data group and the second data group, said SIMD processor comprising: a decoding unit operable to decode an instruction; and an execution unit operable to execute the instruction according to a result of the decoding performed by said decoding unit, wherein: when a SIMD instruction including (i) an operation code specifying an operation type, (ii) a first operand specifying the first data group containing a data array comprised of n pieces of data, n being ≧2, and (iii) a second operand specifying the second data group containing a data array comprised of n pieces of data, is decoded by said decoding unit, said execution unit is operable to perform an operation specified by the operation code on n data pairs, each of the n data pairs being made up of one piece of data belonging to the first data group and one piece of data belonging to the second data group; at least one data pair among the n data pairs is made up of an i-th data in the data array of the first data group and a j-th data in the data array of the second data group, j being not equal to i; the operation code specifies the operation type without including any fields specifying data in the n data pairs; and said execution unit is operable to execute the operation specified by the operation code simultaneously on the n data pairs, based on the result of the decoding performed by said decoding unit.