Patent ID: 7689808

Claim:
A data processor comprising: a first array changer that changes an array sequence of bits in reverse sequence for each bit block for a bit stream, the bit stream having a plurality of the bit blocks; a buffer to temporarily store bit blocks with bit array sequence changed by the first array changer; a first processor to read bits included in bit blocks to be processed by the first processor by each number of bits, a predetermined processing unit, in an array sequence of the buffer; a second processor to process bit blocks different from bit blocks processed by the first processor; a second array changer to read bits included in bit blocks to be processed by the second processor in the array sequence of the buffer and change an array sequence of bits included therein in reverse sequence to supply to the second processor; and a controller to control whether to change an array sequence of bits by the first and the second array changers according to a type of a bit stream, the array sequence of bits in a bit block being different depending on the type, wherein the first processor is to process a bit block including a variable length data part in the bit stream, the second processor is to process a bit block including a fixed length data part in the bit stream, and between two types of bit streams having a same array sequence of bits in a bit block including the fixed length data part but with different array sequences of bits in a bit block including the variable length data part, for one type of the bit stream, the controller controls the first and the second array changers not to change the array sequence, but for another type of the bit stream, the controller controls the first and the second array changers to change the array sequence.