Patent ID: 7860123

Claim:
A wireless communication apparatus, comprising: a packet memory; a first interface coupled to the packet memory, for receiving a packet and storing the packet in the packet memory; a shift register set coupled to the first interface, for recording an address of the packet stored in the packet memory, the shift register set comprising a plurality of shift registers connected in series, the plurality of shift registers comprising a first shift register coupled to the first interface and a last shift register, each shift register having a valid bit for configuring the state of the shift register so as to transmit the address of the packet to the next shift register according to the valid bit of the next shift register; and a second interface coupled to the packet memory and the last shift register of the shift register set, for configuring the valid bits of the shift register set according to an acknowledge (ACK) signal of sending the packet, and accessing the shift register set so as to read and send the packet stored in the packet memory according to the address of the packet recorded in the shift register set.