Patent ID: 7200024

Claim:
A memory device, comprising: a semiconductor substrate; an address converter fabricated in the substrate, the address converter being operable to receive and convert optical address signals into corresponding electrical address signals; an address decoder fabricated in the semiconductor substrate, the address decoder being coupled to the address converter to receive the electrical address signals from the address converter; a data converter fabricated in the substrate, the data converter being operable to receive and convert optical write data signals into corresponding electrical write data signals and to receive and convert electrical read data signals into corresponding optical read data signals; a read/write circuit fabricated in the semiconductor substrate, the read/write circuit being coupled to the data converter to receive the electrical read data signals from the data converter and to couple the electrical write data signals to the data converter; a control signal converter fabricated in the substrate, the control signal converter being operable to receive and convert optical control signals into corresponding electrical control signals; a control logic unit fabricated in the semiconductor substrate, the control logic unit being coupled to the control signal converter; and a memory-cell array fabricated in the semiconductor substrate, the memory-cell array being coupled to the address decoder, control logic unit, and read/write circuit.