Patent ID: 8361335

Claim:
A method of fabricating a semiconductor device comprising the steps of: providing a first pattern design having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality; forming a second pattern design by reversing the tonality of the first pattern design, and wherein the first polygon is converted from the first tonality to the second tonality, and wherein the second and third polygons are both converted to the first tonality; forming a third pattern design from the second pattern design by converting the second polygon from the first tonality to the second tonality; forming a fourth pattern design from the second pattern design by converting the third polygon from the first tonality to the second tonality; forming a fifth pattern design by reversing the tonality of the third pattern design; and forming a sixth pattern design by reversing the tonality of the fourth pattern design.