Patent ID: 7274589

Claim:
A semiconductor storage device comprising an SRAM cell having a first inverter, a second inverter with an input terminal and output terminal connected to an output terminal and input terminal of said first inverter respectively, a first pass transistor provided in a path between said output terminal of said first inverter and a first bit line, a second pass transistor provided in a path between said output terminal of said second inverter and a second bit line, and a word line connected to gates of said first and second pass transistors; wherein said SRAM cell comprising: a third pass transistor provided in a path between said first pass transistor and said first bit line; a fourth pass transistor provided in a path between said second pass transistor and said second bit line; and a voltage applying unit applying a first voltage to said word line at the time of a read operation of said SRAM cell, and applying a second voltage larger than said first voltage to said word line at the time of a write operation of said SRAM cell.