Patent ID: 7825459

Claim:
A method of operating a silicon-oxide-nitride-oxide-silicon (SONOS) memory device including a memory type transistor in which a gate is formed with a SONOS structure on a semiconductor substrate, the method comprising: applying a predetermined operation voltage to the gate, wherein the gate includes: a tunneling oxide layer; a memory node structure formed on the tunneling oxide layer and having a trap site in which charges passing through the tunneling oxide layer are trapped, the memory node structure including crystal layers having nanocrystals that are separated from one another to trap the charges; and a gate electrode formed on the memory node structure, wherein the memory node structure includes: a first memory node layer, a second memory node layer and a third memory node layer, at least one of the first through third memory node layers including the crystal layer, the crystal layer being isolated from adjacent memory node layers; and establishing a state of the memory node structure in response to the predetermined operation voltage, the memory node structure having at least four states.