Patent ID: 7460400

Claim:
A nonvolatile semiconductor memory device, comprising: a data input buffer to receive input data; a plurality of control lines; a control circuit configured to assert selected ones of the control lines; and a plurality of memory cell units arranged in rows and columns and including respective latch circuits and respective nonvolatile memory cells, each nonvolatile memory cell being coupled to a corresponding latch circuit in a corresponding memory cell unit, the memory cell units on a common row being coupled to the respective control lines, wherein the memory cell units are configured to perform a write operation in which the latch circuits of the memory cell units on a selected row store respective bits of the input data, and are further configured to perform a store operation in which the respective bits of the input data are transferred from the latch circuits to the nonvolatile memory cells for storage therein in response to assertion of respective control lines by the control circuit, so that only one or more selective bits of the input data selected by the control circuit are stored in the nonvolatile memory cells.