Patent ID: 8743645

Claim:
A semiconductor memory device comprising: a plurality of static memory cells arranged in rows and columns; a plurality of word lines, arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row; a plurality of word line drivers arranged corresponding to the respective word lines, for driving corresponding word lines to a selected state according to a word line select signal; a plurality of cell power supply lines, arranged corresponding to the respective memory cell columns, each coupled to cell power supply nodes of the memory cells in a corresponding column; a plurality of down power supply lines arranged corresponding to the respective memory cell columns, maintained at a ground voltage level in data reading and rendered electrically floating in data writing; and a plurality of write assist elements arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.