Patent ID: 7875492

Claim:
A method for fabricating an integrated circuit including a memory, the method comprising: providing a preprocessed wafer including first contacts; depositing a first electrode material layer over the preprocessed wafer; depositing a first phase change material layer over the first electrode material layer; etching the first phase change material layer and the first electrode material layer self-aligned to the first phase change material layer to form lines of first phase change material and first electrode material contacting the first contacts; depositing a dielectric material layer over exposed portions of the first phase change material, the first electrode material, and the preprocessed wafer; planarizing the dielectric material layer to expose the first phase change material; depositing a second phase change material layer over the first phase change material and the dielectric material layer; depositing a second electrode material layer over the second phase change material layer; and etching the second electrode material layer, the second phase change material layer, the first phase change material, and the first electrode material to form conductive lines, phase change material self-aligned to the conductive lines providing storage locations, and bottom electrodes self-aligned to the conductive lines and contacting the first contacts.