Patent ID: 7482675

Claim:
A semiconductor structure, comprising: (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a first bond pad electrically connected to a first transistor of the integrated circuit; (c) a first protection ring on the top substrate surface and on a perimeter of the integrated circuit; (d) a dicing region on the top substrate surface, wherein the first protection ring is sandwiched between and physically isolates the integrated circuit and the dicing region, and wherein the dicing region includes a first probe pad electrically connected to the first bond pad through a first electrically conductive region, wherein the first electrically conductive region comprises polysilicon, wherein the first protection ring comprises a first portion, a second portion, and a third portion, wherein the first portion of the first protection ring comprises copper (Cu), wherein the second and third portions of the first protection ring comprise tungsten (W), wherein the first electrically conductive region is disposed between but not electrically coupled to the second and third portions of the first protection ring, wherein the first electrically conductive region is on and in direct physical contact with a first shallow trench isolation (STI) region of the substrate, wherein the first electrically conductive region is surrounded by the first STI region and a first dielectric cap region, wherein the first dielectric cap region comprises BPSG (boro-phospho-silicate glass), and wherein the first dielectric cap region is sandwiched between and in direct physical contact with both the first protection ring and the first electrically conductive region.