Patent ID: 7515484

Claim:
A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines, the page buffer circuit comprising: a Most Significant Bit (MSB) latch configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, the MSB latch configured to output an inverted upper sensing data, or store an input data and output an inverted input data; a Least Significant Bit (LSB) latch configured to sense a voltage of the sensing node in response to the control signal, the LSB latch configured to store and output a lower sensing data, or store and output an input data received through the MSB latch; a data I/O circuit coupled to the MSB latch and a data I/O line, the data I/O circuit configured to perform the input and output of a sensing data or the input and output of a program data; an inverted output circuit configured to invert data stored in the LSB latch, the inverted output circuit configured to output an inverted data to the MSB latch; a MSB verification circuit configured to output a verification signal in response to the data stored in the MSB latch; and a LSB verification circuit configured to output a verification signal in response to the data stored in the LSB latch.