Patent ID: 8148770

Claim:
A memory device, comprising: a substrate; a conductive layer formed over the substrate, where the conductive layer comprises a plurality of conductive regions, each of the conductive regions having a width ranging from about 500 Å to about 2,000 Å; a semiconducting layer formed over the conductive layer; a source region; a drain region; a bit line formed over the conductive layer and adjacent the semiconducting layer, the bit line to electrically couple at least one of the source region or drain region to the conductive layer, where a width of the bit line ranges from about 100 Å to about 500 Å; a first dielectric layer formed over the conductive layer; a charge storage element formed over the first dielectric layer; a second dielectric layer formed over the charge storage element; a control gate formed over the second dielectric layer; and a plurality of dielectric regions, and where each of the plurality of conductive regions is separated from an immediately adjacent conductive region by one of the dielectric regions, and where a first one of the plurality of conductive regions is coupled to the bit line and forms part of a bit line structure.