Patent ID: 7503028

Claim:
A method of designing a mask layout for an integrated circuit, the method comprising the steps of: providing a plurality of mask shapes corresponding to a plurality of layers; providing lithographic models for said plurality of layers, said models describing processes according to which wafer images are transferred from said mask shapes to a wafer; determining simulated wafer images resulting from transferring said plurality of mask shapes in accordance with said models; providing constraints comprising functional constraints that ensure proper functional interaction among said simulated wafer images; evaluating said simulated wafer images relative to other of said simulated wafer images and if said constraints are violated, modifying said mask layout to correct said violations; providing target images representing desired wafer images on said wafer; and providing edge placement error constraints for said simulated wafer images relative to said target images; and wherein the step of evaluating said simulated wafer images relative other of said simulated wafer images further comprises evaluating said simulated wafer images relative to said target images, wherein said functional constraints have higher priority than said edge placement error constraints.