Patent ID: 8139395

Claim:
A semiconductor memory device, comprising: a memory cell array formed of a number of memory cells aligned in a matrix shape in a row direction and a column direction, each memory cell comprising a memory element and a cell transistor, wherein the memory element has two input/output terminals so that information is stored using a difference in electrical properties between the two terminals and the stored information is written by applying a writing voltage across the two terminals, the cell transistor has two input/output terminals and one control terminal, and a first end of the input/output terminal of the memory element and a first end of the input/output terminal of the cell transistor are connected; word lines extending in the row direction for connecting control terminals of the cell transistors in the memory cells aligned in same rows to each other; first bit lines extending in the column direction for connecting second ends of the input/output terminals of the cell transistors in the memory cells aligned in same columns to each other, the second end being not connected to the memory elements; second bit lines extending in the row or column direction for connecting second ends of the input/output terminals of the memory elements in the memory cells to each other, the second ends being not connected to the cell transistors; a word line voltage applying circuit for applying a voltage to a word line connected to the memory cell selected to be written; a first voltage applying circuit for applying the writing voltage to the first bit line connected to the selected memory cell; and a second voltage applying circuit for applying a pre-charge voltage to both the first bit line and the second bit line connected to the selected memory cell before application of the writing voltage.