Patent ID: 8049545

Claim:
A delay locked loop (DLL) circuit comprising: a delay line which includes a plurality of series connected unit delay circuits and which delays an external clock signal in response to a control signal; a phase detector which detects a phase difference between a signal output by the delay line and the external clock signal; a control unit which generates the control signal in response to signals output by the phase detector; and a control circuit which controls bias currents and delay times of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, wherein the control circuit generates a delay control signal and a bias control signal according to the CWL signal, and each of the unit delay circuits comprises: a first pair of differential transistors which are respectively controlled by an input signal and a complementary input signal; a first pair of variable resistors interconnected between a power voltage and respective first terminals of the first pair of differential transistors, wherein respective resistances of the first pair of variable resistors are set according to the delay control signal generated by the control circuit; a first bias transistor including a first terminal is connected to second terminals of the first pair of differential transistors and a second terminal is connected to a ground voltage, wherein the first bias transistor is controlled by the bias current control signal generated by the control circuit; a second pair of variable transistors which are respectively controlled by an internal output signal and a complementary internal output signal that are respectively output by the first terminals of the first pair of differential transistors; a second bias transistor including a first terminal connected to second terminals of the second pair of differential transistors and a second terminal connected to the ground voltage, wherein the second bias transistor is controlled by the bias current control signal generated by the control circuit; a third pair of differential transistors which are respectively controlled by the internal output signal and the complementary internal output signal; a second pair of variable resistors interconnected between the power voltage and respective first terminals of the third pair of differential transistors, wherein respective resistances of the second pair of variable resistors are set according to the delay control signal generated by the control circuit; and a third bias transistor including a first terminal connected to second terminals of the third pair of differential transistors and a second terminal connected to the ground voltage, wherein the third bias transistor is controlled by the bias current control signal generated by the control circuit.