Patent ID: 8572419

Claim:
A system-on-chip comprising: a system bus; a plurality of devices configured to generate request signals to access the system bus; a plurality of pulse modules, each configured to (i) receive a respective one of the request signals, (ii) receive a summation signal, and (iii) lengthen a pulse of the respective one of the request signals based on the summation signal to generate an output signal, wherein the summation signal indicates a remaining number of requests by the plurality of devices for the system bus, wherein the pulse of the respective one of the request signals indicates a request for the system bus by one of the plurality of devices, and wherein each of the output signals has a respective one of the lengthened pulses; a summer configured to (i) receive the output signals from the plurality of pulse modules, and (ii) generate the summation signal based on the output signals; a frequency module configured to select a frequency based on the summation signal; and a clock generator configured to generate a clock signal having the frequency, wherein communication between the plurality of devices via the system bus is implemented based on the clock signal.