Patent ID: 8592884

Claim:
A semiconductor device comprising: a first wiring layer formed above a semiconductor substrate; an insulating film formed above the first wiring layer; a first hole formed in the insulating film; a first metal layer covering an internal surface of the first hole and formed on an upper surface of the insulating film, and connected to the first wiring layer; a second metal layer formed on the first metal layer in the first hole; a third metal layer formed on the first metal layer located on the upper surface of the insulating film and connected to the first metal layer and the second metal layer; a dielectric insulating film formed above the third metal layer; a second wiring layer formed on the dielectric insulating film; and a capacitor comprising a lower electrode including the third metal layer, the dielectric insulating film, and an upper electrode including the second wiring layer, wherein the first hole is located in a first area outside of a second area where the upper electrode and lower electrode face each other; and the first metal layer located in the second area is flat.