Patent ID: 8759918

Claim:
A semiconductor device, comprising: a semiconductor substrate including a device region and a device isolation region; a first dynamic threshold MOS transistor formed in the device region; and a second dynamic threshold MOS transistor formed in the device region, the device region including a well having a first conductivity type, the first dynamic threshold MOS transistor having a first gate electrode formed on a surface of the semiconductor substrate via a first gate insulation film, a first diffusion region formed in the well at a first side of the first gate electrode, and a second diffusion region formed in the well at a second side of the first gate electrode opposite to the first diffusion region, the second dynamic threshold MOS transistor having a second gate electrode formed on the surface of the semiconductor substrate via a second gate insulation film at the second side of the gate electrode, a third diffusion region formed in the well at a side of the second gate electrode closer to the first gate electrode, and a fourth diffusion region formed in the well at a side of the second gate electrode opposite to the third diffusion region, the first and second gate electrodes and the first through fourth diffusion regions having a second conductivity type opposite to the first conductivity type, the second diffusion region and the third diffusion region being formed by a common diffusion region formed in the well, first through fourth insulation regions being formed respectively underneath the first through fourth diffusion regions in contact with respective bottom edges of the first through fourth diffusion regions, the second insulation region and the third insulation region being formed by a common insulation region, there extending a first body region of the first conductivity type and constituting a body of the first dynamic threshold MOS transistor along the first gate electrode between the first insulation region and the second insulation region as a part of the device region, there extending a second body region of the first conductivity type and constituting a body of the second dynamic threshold MOS transistor along the second gate electrode between the third insulation region and the fourth insulation region as a part of the device region, the first gate electrode being connected to the first body region electrically, the second gate electrode being connected to the second body region electrically, the first through fourth insulation regions having respective bottom edges located lower than bottom edges of the first and second body regions, the first and second body regions having respective bottom edges located lower than the bottom edges of the first through fourth diffusion regions.