Patent ID: 7673140

Claim:
A multimedia data processing system, comprising: a first integrated circuit, the first integrated circuit comprising: a first logic block receiving an encoded multimedia data stream; a hardware encryption circuit coupled to the first logic block, the hardware encryption circuit encrypting the received data stream to generate an encrypted data stream with access control; and a first Peripheral Component Interconnect Express (PCI-Express)-compatible interface circuit supporting data communication over a plurality of PCI-Express virtual channels, wherein the plurality of PCI-Express virtual channels comprises at least an unencrypted default virtual channel and a dedicated encrypted virtual channel, wherein the first PCI-Express-compatible interface circuit includes a first plurality of channel interconnects, each channel interconnect associated with a virtual channel among the plurality of virtual channels, wherein a first channel interconnect among the plurality of virtual channels is coupled to the hardware encryption circuit to receive the encrypted data stream, and wherein the first PCI-Express-compatible interface circuit communicates the encrypted data stream from the hardware encryption circuit over the dedicated encrypted virtual channel; a second integrated circuit coupled to the first integrated circuit by a PCI-Express-compatible interconnect, the second integrated circuit comprising: a second PCI-Express-compatible interface circuit coupled to the PCI-Express-compatible interconnect to receive the encrypted data stream over the dedicated encrypted virtual channel, the second PCI-Express-compatible interface circuit comprising: a second plurality of channel interconnects, each channel interconnect associated with a virtual channel among the plurality of virtual channels; a hardware decryption circuit coupled to a first channel interconnect among the second plurality of channel interconnects for the second PCI-Express-compatible interface circuit and configured to decrypt the encrypted data stream; and a second logic block coupled to the hardware decryption circuit decoding the decrypted data stream, the decoding providing the multimedia stream to a subscriber authorized by the access control; and control logic coupled to at least one of the first and second PCI-Express-compatible interface circuits and configured to communicate authorization data over the default virtual channel to authorize secure communication between the first and second integrated circuits over the dedicated encrypted virtual channel, wherein all data sent over the dedicated encrypted virtual channel are encrypted.