Patent ID: 7844952

Claim:
An apparatus comprising: at least one processor; a memory coupled to the at least one processor; a multi-threaded computer program residing in the memory, the multi-threaded computer program comprising a plurality of threads; and a debugger residing in the memory and executed by the at least one processor, the debugger executing the multi-threaded computer program, providing an interface from which a user specifies a criterion from one or more selectable criteria for grouping at least two of the plurality of threads into a plurality of groups, and displaying the plurality of groups in a manner that visually distinguishes between threads in each of the plurality of groups in a display, wherein the one or more selectable criteria comprises at least a first criterion which specifies to group the at least two threads according to current and historical breakpoints which defines the plurality of groups as a first group of threads that have current breakpoints set, a second group of threads that have historical breakpoints, and a third group of threads that have no current breakpoints set and no historical breakpoints, wherein a thread having historical breakpoints comprises a thread which has had breakpoints set in the past.