Patent ID: 7454730

Claim:
A method for inserting repeaters into an integrated circuit synthesis comprising method operations of: identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design; organizing the possible repeater insertion locations in a tree enabling bottom-up traversal; generating a set of solutions for each of the insertion locations while traversing the tree in a first direction, considering both set up time and hold time concurrently when generating the set of solutions, identifying solutions that are non sub-optimal in a late mode and solution that are non sub-optimal in an early mode, identifying combinations of solutions that are non sub-optimal in the late mode and combinations of solutions that are non sub-optimal in the early mode, identifying combinations common to both combinations of solutions and eliminating the combinations common to both combinations of solutions; and organizing the set of solutions in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load.