Patent ID: 7085940

Claim:
A system for reducing the power consumption in a floating point unit of a processor that includes an instruction buffer and a floating point multiply adder unit, the processor capable of selectively executing iterative loops of a program the system comprising: a branch unit, responsive to the instruction buffer, that includes a counter register, wherein the branch unit detects execution of an instruction that causes the floating point multiply adder unit to enter a tight loop and wherein the counter register counts each iteration of the tight loop; a last iteration detector that receives an iteration signal from the counter register in the branch unit indicating whether a last iteration of the tight loop has been executed; a write inhibitor, responsive to the instruction buffer and to the last iteration detector, that asserts a write inhibit signal when an initial execution in an iterative loop is detected from the instruction buffer and when the last iteration detector has not detected the last iteration of the tight loop, and that does not assert the write inhibit signal when the last iteration detector has detected the last iteration of the tight loop; and a float register that stores a value from the floating point multiply adder unit when the write inhibit signal is not asserted and the does not store the value from the floating point multiply adder unit when the write inhibit signal is asserted, so that the value from the floating point multiply adder unit is stored by the float register only after execution of the last iteration of the tight loop.