Patent ID: 7562191

Claim:
A processor core having a multi-cycle processing pipeline, comprising: a multi-way set associative cache, each way of the cache having an associated tagram; a predictor coupled to the multi-way set associative cache; and a policy counter coupled to the predictor and configured to provide a policy signal indicative of a power-saving mode to the predictor, wherein the predictor operates in one of a first power-saving mode and a second power-saving mode in response to the policy signal, and when operating in the first power-saving mode, the predictor enables during a first processing cycle a first tagram associated with a first way predicted by the predictor as containing an instruction to be fetched from the multiway set associative cache, and when operating in the second power-saving mode, the predictor enables during the first processing cycle all tagrams associated with the multi-way set associative cache.