Patent ID: 7444472

Claim:
A microprocessor, comprising: processor logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction, wherein said cache line memory write transaction comprises sending an entire cache line to memory, and wherein individual data elements within said cache line are enabled to be written to said memory with doubleword granularity; and sparse write logic, coupled to said processor logic, which causes said processor logic to specify a sparse write-combined memory write transaction on said request signals and to provide a corresponding plurality of doubleword enable bits on said address signals, wherein said corresponding plurality of doubleword enable bits determines which doublewords of said cache line are to be written to said memory; wherein said processor logic asserts a first part on said address signals and said request signals to provide said address and said request for said cache line memory write transaction, and which asserts a second part on said address signals and said request signals to specify said sparse write-combined memory write transaction and to provide said plurality of doubleword enable bits; and wherein said sparse write logic causes said processor logic to replace an attribute value and byte enable bits on said address signals of said second part with said plurality of doubleword enable bits.