Patent ID: 8195921

Claim:
A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads, comprising: a first array comprising a first plurality of microcode operations associated with an instruction from the plurality of instructions, the first array capable of delivering a first predetermined number of microcode operations from the first plurality of microcode operations; a second array comprising a second plurality of microcode operations, the second array capable of providing one or more of the second plurality of microcode operations in the event that the instruction decodes into more than the first predetermined number of microcode operations and an arbiter coupled between the first and second arrays, wherein the arbiter determines which thread from the plurality of threads accesses the second array; wherein the first array provides an address within the second array in the event that the instruction decodes into more than the first predetermined number of microcode operations wherein the second array provides a second predetermined number of microcode operations, and in the event that the instruction decodes into more than the second predetermined number of microcode operations, then the second array provides a subsequent address within the second array to the arbiter.