Patent ID: 7587551

Claim:
A storage system, comprising: a plurality of disk drives; and a storage controller coupled to the plurality of disk drives for reading/writing data from/to the plurality of disk drives, the storage controller comprising: a plurality of interfaces connected to a plurality of host computers through an external storage area network (SAN); a cache memory storing data read from the plurality of disk drives and storing data to be written to the plurality of disk drives; and a plurality of processors connected to the plurality of interfaces and the cache memory through an internal network, and each of a plurality of processor groups, including two or more of the plurality of processors, causing at least one of the plurality of interfaces to transfer data, received from at least one of the plurality of host computers, from the at least one of the plurality of interfaces to the cache memory, and each of the plurality of processor groups causing the at least one of the plurality of interfaces to transfer data, to be transferred to the at least one of the plurality of host computers, from the cache memory to the at least one of the plurality of interfaces, wherein: each of the plurality of interfaces stores a routing information, including identifications of the plurality of processor groups and a plurality of logical unit numbers (LUNs) each identifying a logical volume storing data to be controlled to transfer by at least one of the plurality of processor groups, extracts a network address and a logical unit number from a received access request upon reception of the access request from the at least one of the plurality of host computers, specifies one of the plurality of processor groups which processes the received access request based on the routing information, and transfers the received access request to the specified processor group so that the specified processor group causes one of the plurality of interfaces to transfer data of the received access request between the one of the plurality of interfaces and the cache memory.