Patent ID: 7363402

Claim:
A data communications architecture for use by a computing environment to reduce latency in data communications comprising: a first data interface cooperating with a first computer processor to accept computer processor data and to format the computer processor data, wherein the data interface comprises any of data drivers, overlay management information, routing logic and information, and channel training information; a plurality of SERDES communications channels comprising: a serializer cooperating with the first data interface to obtain the computer processor data for encoding; a deserializer cooperating with the serializer to receive the encoded data and to decode the encoded data for communication to a second data interface for use by a second computer processor; and a physical link therebetween; and a control channel comprising an existing SERDES communications channel operable to provide error detection information for at least a second existing SERDES communications channel; wherein the data communications architecture is configured to orchestrate parallel operation of the SERDES communications channels.