Patent ID: 6992003

Claim:
A semiconductor fabrication process, comprising: forming an ILD overlying a substrate of a semiconductor wafer wherein forming the ILD comprises: forming a low K dielectric overlying a semiconductor substrate of the wafer, wherein a dielectric constant of the low K dielectric is less than or equal to 3.0; forming an organic, silicon-oxide, glue layer dielectric overlying the low K dielectric including forming a plasma within a CVD reactor chamber using a specified set of precursors including a carbon bearing precursor and maintaining the plasma during formation of the glue layer dielectric; and forming a CMP stop layer dielectric overlying the glue layer dielectric including reducing a flaw rate of the carbon bearing precursor following formation of the glue layer dielectric while continuing to maintain the plasma to form the CMP stop layer dielectric wherein the CMP stop layer dielectric is substantially free of carbon; forming a void in the ILD; depositing a conductive material over the wafer to fill the void; and removing portions of the conductive material exterior to the void by polishing the wafer with a CMP process and terminating the CMP process on the CMP stop layer dielectric.