Patent ID: 8400202

Claim:
A control system, comprising: a counter unit receiving a reference clock signal to generate a timing signal based on the reference clock signal; a plurality of intermittent clock generating units each coupled to a storage unit storing bit string data, each of the intermittent clock generating units receiving the reference clock signal and the timing signal, wherein each of the intermittent clock generating units masks a clock pulse of the reference clock signal based on the bit string data stored in the storage unit to output an intermittent clock signal in response to the timing signal; a plurality of logic circuits receiving the intermittent clock signals generated by the intermittent clock generating units; a control unit configured to set each of the bit string data to reduce a peak electric current of the logic circuits; and a memory storing a combination of the bit string data, wherein the combination of the bit string data is predetermined for reducing a peak electric current of the logic circuits, and the control unit sets each of the bit string data based on the combination of the bit string data stored in the memory.