Patent ID: 7765509

Claim:
A method for generating simulated wiring connections between a semiconductor device and a carrier, said method adapted to be performed by execution of a connection assignment algorithm on a processor of a computer system, said method comprising: identifying a plurality of first factors and instances of each first factor, said plurality of first factors relating to the semiconductor device, wherein said semiconductor device is located parallel to and over said carrier such that said semiconductor device and said carrier comprise a common center point in a plane of a top side of the carrier onto which the semiconductor device has been projected; identifying a plurality of second factors and instances of each second factor, said plurality of second factors relating to the carrier, said plurality of first factors and said plurality of second factors being associated with each other on a one-to-one basis, the instances of each first factor being correlated to the instances of each associated second factor on a one-to-one basis, first I/O terminals on said semiconductor device comprising an identified instance of each first factor, second I/O terminals on said carrier comprising an identified instance of each second factor; forming a simulated sector initiating from an I/O terminal from said first I/O terminals and extending outward in said plane through a perimeter of said semiconductor device and a perimeter of said carrier, wherein said simulated sector comprises a first angle; automatically generating a simulated wiring connection between each first I/O terminal and a matching second I/O terminal, subject to the identified instance of each first factor of each first I/O terminal being correlated to the identified instance of the associated second factor of the matching second I/O terminal, wherein said automatically generating comprises locating a first said simulated wiring connection from said I/O terminal from said first I/O terminals to said matching second I/O terminal within said simulated sector comprising said first angle; identifying a first region on said semiconductor device, said first region comprising third I/O terminals on said semiconductor device; identifying a second region on said carrier, said second region comprising fourth I/O terminals on said carrier; and automatically generating a simulated wiring connection between each I/O terminal of said third I/O terminals located in said first region and an associated I/O terminal of said fourth I/O terminals located in said second region.