Patent ID: 8279652

Claim:
A package for a memory device, comprising a set of external conductor elements for connecting to a memory circuit within the package, the memory circuit including a transmitting port and a receiving port, the transmitting port and the receiving port having a combined first predetermined number of conductors for providing connections to the transmitting port and the receiving port to connect command/address and data signals of the transmitting and receiving ports to the exterior of the package, the set of external conductor elements comprising a second predetermined number of external conductor elements for providing connections between the transmitting and receiving ports and the exterior of the package for the command/address and data signals, the second predetermined number being less than the first predetermined number, wherein the set of external conductor elements comprises a subset of external conductor elements allocated to the transmitting port and the receiving port and wherein the transmitting port and the receiving port are connected to control circuits between the transmitting port and receiving port and the subset of external conductor elements that control whether data signals can be transmitted between the subset of external conductor elements and either of the transmitting port and receiving port, such that, when the control circuits do not permit signal transmission between one of the transmitting port and the receiving port and the subset of the external conductor elements, data signals can be transmitted between the subset of the external conductor elements and the other of the transmitting port and the receiving port.