Patent ID: 7300888

Claim:
A method of manufacturing an integrated circuit device, comprising: forming a pattern comprising a pair of mesa regions on a substrate; forming a first insulating layer on the pair of mesa regions; forming a second insulating layer on the pair of mesa regions and the substrate; forming a capping layer on the second insulating layer; patterning the capping layer and the second insulating layer together, such that parts of the first insulating layer that were covered by the second insulating layer are exposed without exposing the mesa regions under the first insulating layer; forming insulating spacers on sidewalls of the second insulating layer such that the second insulating layer is enclosed by the insulating spacers, the capping layer, the first insulating layer, and the substrate; forming a conductive layer on the pair of mesa regions and the substrate so as to fill a contact region between the pair of mesa regions and to cover the mesa regions; and removing a portion of the conductive layer such that an upper surface of the first insulating layer, opposite the substrate, is exposed.