Patent ID: 7889553

Claim:
A non-volatile memory cell, comprising: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a polysilicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate, wherein the substrate is p− doped such that the read-out transistor is an NMOS transistor, the substrate including an n-well adjacent the interdigitation of the finger extensions, the n-well having an active region with a first portion doped n+ and a second portion doped p+, the floating gate including an additional extension that overlays both portions in the active region so as to create an n+ doped channel and a p+ doped channel in the active region.