Patent ID: 7733689

Claim:
A method for operating a memory circuit, comprising: providing a memory circuit comprising: a plurality of word line structures comprising READ and WRITE word lines; a plurality of bit line structures comprising READ and WRITE bit lines and intersecting said word line structures at a plurality of cell locations; a voltage supply configured to supply a first supply voltage VDD, and a second supply voltage; a plurality of cells formed at said cell locations, each of said cells comprising: a logical storage element having first and second terminals and a storage element supply voltage terminal; a WRITE access device configured to selectively interconnect said first terminal to a corresponding one of said WRITE bit lines under control of a corresponding one of said WRITE word lines; and a pair of series READ access devices configured to ground a corresponding one of said READ bit lines when a corresponding one of said READ word lines is active and said second terminal is at a logical level; and writing a logical “one” to said logical storage element of a given one of said cells by applying said second supply voltage to said corresponding one of said WRITE word lines and applying said first supply voltage VDD to said storage element supply voltage terminal, said second supply voltage being greater than said first supply voltage, substantially without the use of a complementary WRITE bit line.