Patent ID: 8012827

Claim:
A method of manufacturing a dual work function semiconductor device comprising: manufacturing a first transistor in a first region of a semiconductor substrate, the first transistor comprising a first gate stack having a first effective workfunction (WF1 eff ), the first gate stack comprising a first gate dielectric capping layer and a first metal gate electrode layer on and in contact with the first gate dielectric capping layer, the first gate dielectric capping layer determining the first effective workfunction (WF1 eff ); manufacturing a second transistor in a second region of the substrate, the second transistor comprising a second gate stack having a second effective workfunction (WF2 eff ), the second gate stack comprising a second gate dielectric capping layer and a second metal gate electrode layer on and in contact with the second gate dielectric capping layer, the second metal gate electrode layer being formed from the same metal composition as the first metal gate electrode layer, the second gate dielectric capping layer being formed from the same dielectric material as the first dielectric capping layer, the second gate dielectric capping layer determining the second effective work function (WF2 eff ) being the same as the first effective workfunction (WF1 eff ); and applying a first thermal budget to at least the first gate dielectric capping layer and a second thermal budget to at least the second gate dielectric capping material, the first thermal budget being smaller than the second thermal budget such that the first effective workfunction (WF1 eff ) is modified into a final first effective workfunction (WF1 eff-final ) and such that the second effective workfunction (WF2 eff ) is modified into a final second effective workfunction (WF2 eff-final ), wherein the final first effective workfunction (WF1 eff-final ) is different from the final second effective work function (WF2 eff-final ).