Patent ID: 7949986

Claim:
A method of having a computer program embodied on a computer readable medium evaluate the feasibility for proposed SoC architecture comprising the steps of: having a user enter input variables relating to a proposed SoC architecture for generating and capturing trace information; assigning values to the input variables; generating trace information; determining whether it is an appropriate time to place said trace information into a trace source FIFO; if the time is appropriate, placing said trace information into said trace source FIFO; determining whether it is an appropriate time to remove said trace information from said trace source FIFO; if the time is appropriate, removing said trace information from said trace source FIFO; capturing the level of data present in said trace source FIFO at various clock cycles; analyzing the level of data present in said trace source FIFO at various clock cycles to determine the percentage of said trace source FIFO's maximum level occupied by said trace information; and analyzing the percentages calculated to determine if the proposed architecture will accommodate said trace information.