Patent ID: 7379356

Claim:
A memory comprising: at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair, wherein the at least one memory segment includes a test column; an address decoder, coupled to the at least one memory segment, the address decoder including a row decoder and a column decoder that addresses a selected one of the array of memory cells in a selected one of the plurality of columns in response to a memory address; a sense amplifier, coupled to the at least one memory segment, the sense amplifier, in response to a sense amp enable signal, that generates a data output by sensing a differential voltage from the corresponding bitline pair of the selected one of the plurality of columns; and a sense amp enable signal generator, coupled to the sense amplifier, that generates the sense amp enable signal with adjustable timing, based on sense amp feedback signals, wherein the sense amp enable signal generator is coupled to the address decoder, and wherein the sense amp enable signal generator includes a test generation module that generates a test column address corresponding to the test column.