Patent ID: 8188542

Claim:
A field effect transistor comprising: a substrate; a field insulation layer disposed in the substrate, the field insulation layer defining a first substrate region and a second substrate region spaced apart from each other; a gate on the first substrate region; a channel region defined in the first substrate region under the gate, the channel region comprising a first portion having a first width under the gate and a second portion having a second width under the gate, along a channel width direction that is transverse to a direction from the first substrate region to the second substrate region; a heavily doped region in the second substrate region; and a lightly doped region in the substrate surrounding a sidewall and a bottom surface of the heavily doped region, wherein the first portion is interposed between the second substrate region and the second portion, the first portion is adjacent to the field insulation layer between the first and the second substrate regions, and the first width under the gate is smaller than the second width under the gate; and wherein the first width under the gate is defined by a first distance between opposite ends of the channel region under the gate, and the second width under the gate is defined by a second distance between opposite ends of the channel region under the gate.