Patent ID: 8478920

Claim:
A computer implemented method for controlling data stream interruptions on a shared bus, the method comprising: receiving a first request to transfer data, determining high priority data components and low priority data components for the first request, the high priority data components comprising a first portion of a cache line, and the low priority data components comprising a second portion of the cache line; transferring the high priority data components without interruptions; based on receiving further requests while transferring the high priority data components, rejecting the further requests; based on the transferring of the high priority data components being complete for the first request, transferring the low priority data components of the first request; and based on receiving other requests while transferring the low priority data components, allowing the other requests to interrupt the transferring of the low priority data up to a maximum allowed number of interruptions, the maximum allowed number of interruptions being based on a number of chip-to-chip interfaces for the first request.