Patent ID: 8183152

Claim:
A method of fabricating a semiconductor device, comprising: forming a conductive layer on a substrate; forming a mask layer on the conductive layer; forming first patterns spaced apart from each other and a second pattern on the mask layer, wherein the second pattern includes first and second linear portions parallel to each other; forming first auxiliary masks over ends of the first patterns, respectively, and forming a second auxiliary mask over and spanning the first and second portions of the second pattern, wherein sidewalls of the second auxiliary mask are disposed on the first and second portions of the second pattern, respectively; etching the mask layer using the first and second patterns and the first and second auxiliary masks as an etch mask to thereby form a first upper mask of first upper mask pattern features below the first patterns, respectively, and a second upper mask of a second upper mask pattern feature below the second pattern; and removing the first and second patterns and the first and second auxiliary masks, and etching the conductive layer using the first and second mask patterns as an etch mask to thereby form first conductive patterns below the first upper mask pattern features, respectively, and a second conductive pattern below the second upper mask pattern feature.