Patent ID: 7913065

Claim:
A method of providing a circuit having a custom processor, the method comprising: providing the custom processor on the circuit, the custom processor including one or more or more functional units; providing a program memory coupled with the custom processor through a decoder; and storing a compressed instruction sequence in the program memory, the compressed instruction sequence corresponding to a predetermined instruction sequence, wherein said predetermined instruction sequence includes a plurality of instructions, each instruction of said predetermined instruction sequence comprising a first number of bits in respective bit positions and being executed by at least one of the functional units of the custom processor during a different clock cycle; wherein the compressed instruction sequence is determined by: performing at least one identification process on said instructions, in order to identify relationships between the bits in said bit positions among said instructions of said predetermined instruction sequence; generating a compressed instruction sequence, comprising one compressed instruction corresponding to each instruction of the predetermined instruction sequence, and each compressed instruction comprising a second number of bits, based on the identified relationships between the bits in said bit positions in said instructions of said predetermined instruction sequence.