Patent ID: 8755309

Claim:
A method for facilitating communication between a first microprocessor and a second microprocessor in a multi-processor device using a serial bus, the serial bus comprising at least a serial clock signal line, a first serial data line and a second serial data line, comprising: transmitting a continuous serial clock signal from the first microprocessor to the second microprocessor over the serial clock signal line; transmitting a first plurality of words from the first microprocessor to the second microprocessor over the first serial data line during the transmission of the continuous serial clock signal, wherein the first plurality of words are transmitted in a first plurality of frames, the first plurality of frames including at least one data frame; and transmitting a second plurality of frames from the second microprocessor to the first microprocessor over the second serial data line during the transmission of the continuous clock signal, wherein the transmission of each of the second plurality of frames is synchronized with the transmission of each of a respective one of the first plurality of frames, wherein a marker word in a header of at least one frame transmitted from the first microprocessor to the second microprocessor is detected and the transmission of the second plurality of frames is synchronized based on the detected marker word, and wherein the first microprocessor transmits a word select signal to the second microprocessor and transmits each of the first plurality of frames in synchronization with the continuous serial clock signal and the word select signal, and wherein the second plurality of frames is transmitted in synchronization with the continuous serial clock signal and the word select signal.