Patent ID: 8163623

Claim:
A method of manufacturing a semiconductor device, comprising: forming a mesh pattern defining a storage node region over a semiconductor substrate; forming a lower electrode over the semiconductor substrate and sidewalls of the mesh pattern; forming a dielectric layer over the lower electrode; and forming an upper electrode over the dielectric layer, wherein the forming the mesh pattern includes: forming a first line pattern; and forming a second line pattern passing across the first line pattern to obtain the mesh pattern, wherein the forming the first line pattern includes: forming a first sacrificial line pattern over the semiconductor substrate; forming a first silicon nitride layer over a sidewall of the first sacrificial line pattern; and removing the first sacrificial line pattern, and wherein the forming the second line pattern includes: forming a second sacrificial line pattern passing across the first line pattern; forming a second silicon nitride layer over a sidewall of the second sacrificial line pattern; and removing the second sacrificial line pattern.