Patent ID: 6853587

Claim:
A vertical multiple bit cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; a first transmission line coupled to the first source/drain region; and a second transmission line coupled to the second source/drain region; wherein the MOSFET is a programmed MOSFET having a charge programmed in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region such that the programmed MOSFET operates at reduced drain source current; and wherein both the first and second source/drain regions of the MOSFET share a source/drain region with a second MOSFET.