Patent ID: 8086765

Claim:
A computer implemented method comprising: identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address and directly by an Input/Output (I/O) device, and the physical address used as part of a Direct Memory Address (DMA) operation generated by the I/O device that is programmed by a Virtual Machine (VM), wherein the concurrent accessing grant the hypervisor access to the common physical address while buffering access from the I/O device; transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written; and updating a physical address to machine address (P2M) translation table associated with the hypervisor, and an I/O Memory Management Unit (IOMMU) translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.