Patent ID: 7808105

Claim:
A semiconductor package comprising: a first semiconductor die including a first surface, an opposing second surface, and a bonding pad formed on the second surface; a first redistribution layer coupled to the bonding pad of the first semiconductor die, the first redistribution layer being disposed on the second surface of the first semiconductor die; a first solder bump coupled to the first redistribution layer; a second semiconductor die including a first surface, an opposing second surface, and a bonding pad formed on the first surface of the second semiconductor die, wherein the second surface of the second semiconductor die is longer than the first surface of the second semiconductor die, further wherein a third surface of the second semiconductor die connects the first surface of the second semiconductor die and the second surface of the second semiconductor die, and the third surface is slanted to be non-perpendicular to the first surface of the second semiconductor die and the second surface of the second semiconductor die; a second redistribution layer coupled to the bonding pad of the second semiconductor die, the second redistribution layer being disposed on the first surface of the second semiconductor die; a second solder bump coupled to the second redistribution layer and coupled to the first solder bump; a third redistribution layer coupled to the second redistribution layer, the third redistribution layer being disposed on the second surface of the second semiconductor die; and a solder ball coupled to the third redistribution layer.