Patent ID: 8581326

Claim:
A nonvolatile semiconductor memory device comprising: first laminated bodies each having a plurality of first gate electrodes laminated with insulating films disposed therebetween to form a plurality of first memory cells on a substrate, second laminated bodies located separately from the first laminated bodies on the substrate and each having a plurality of second gate electrodes laminated with insulating films disposed therebetween to form a plurality of second memory cells, gate insulating film portions located on side surfaces of the first laminated bodies and the second laminated bodies and each containing a charge storage layer, first semiconductor layers that are each located between the first laminated bodies and the second laminated bodies on which the gate insulating film portion is formed and act as active regions of the first memory cells and the second memory cells, first select transistors located above the first semiconductor layers and each serially connected to an uppermost one of the first memory cells, second select transistors located above the first semiconductor layers and each serially connected to an uppermost one of the second memory cells, isolation insulating films located on the first semiconductor layers to separate the first select transistors and the second select transistors into portions on the first laminated body sides and the second laminated body sides, and a substrate potential applying electrode located to penetrate the isolation insulating films from a front surface side to a back surface side and connected to the first semiconductor layers.