Patent ID: 7485516

Claim:
A method of forming an integrated circuit device by the following steps: forming a doped region in a silicon semiconductor substrate which has a top substrate surface; forming a gate electrode stack over a portion of said semiconductor substrate with said gate electrode stack with vertically extending sidewalls including a gate dielectric layer and a gate electrode overlying said gate dielectric layer; vertically implanting of nitrogen molecules or nitrogen atoms into said doped region of said semi-conductor substrate aside from said gate electrode stack at a low energy level of about between about 2 keV and a maximum energy of about 10 keV forming a nitrogen implanted layer in said doped region of said semiconductor substrate without amorphizing said silicon semiconductor substrate; forming silicon oxide offset spacers preferentially on said vertically extending sidewalls of said gate electrode stack and in contact with a portion of said nitrogen implanted layer of said semiconductor substrate by a step of oxidation of said gate electrode stacks to form with said nitrogen implanted layer in said doped region acting to suppress formation of silicon oxide on said top substrate surface of said doped region in said semiconductor substrate; and then etching to remove silicon oxide completely from said top substrate surface without completely removing silicon oxide from said vertically extending sidewalls of said gate electrode stack; whereby said doped region implanted with nitrogen molecules or nitrogen atoms acts to suppress the formation of silicon oxide on the top surface of said doped region of said semiconductor substrate without distortion of bonds in said silicon semiconductor substrate and said silicon oxide offset spacers remain on said vertically extending sidewalls.