Patent ID: 7554382

Claim:
A switch comprising: a first field effect transistor, FET, having a gate, source, drain, and well, wherein an input signal A is received on the drain or the source and an output signal is presented to the source or drain, respectively, when the first FET is on; a first internal power rail; a second FET arranges so that, when the first FET is turned off, the second FET is turned on coupling the well of the first FET to the first internal power rail; a third FET that couples the first internal power rail to a positive power supply when the input signal goes low; and a fourth FET that couples the first internal power rail to the input signal A when the positive power supply goes low, wherein, when the second FET is on, the well of the first FET will be maintained at the higher of the positive power supply or the A input signal.