Patent ID: 7202133

Claim:
A method of forming a semiconductor device comprising: a) forming a gate structure over a substrate being doped with a first conductivity type impurity; b) performing a doped depletion region implantation by implanting ions being a second conductivity type into the substrate to form doped depletion regions; and c) performing a S/D implantation by implanting ions being the second conductivity type into the substrate to form source and drain regions adjacent to said gate structure; at least a portion of the doped depletion regions is directly beneath and separated from said source and drain regions; (1) said doped depletion regions having an impurity concentration and thickness so that said doped depletion regions are depleted due to a built-in potential created between said doped depletion regions and said substrate; said doped depletion regions having an impurity concentration so that a built-in junction potential between said doped depletion regions and said substrate forms depletion regions in the substrate between said source and drain regions and the doped depletion regions; said depletion regions have a net impurity concentration of the first conductivity type, a channel region in said substrate under said gate structure; wherein said doped depletion regions are not directly beneath said channel region.