Patent ID: 7310787

Claim:
A method of reorganizing an array layout in a behavioral synthesis tool used to design an integrated circuit, comprising: reading a source code description associated with the integrated circuit into the behavioral synthesis tool, the source code description having at least one array in a first layout format; storing the source code description in an intermediate data structure within the behavioral synthesis tool; and transforming the array layout from the first layout format to a second layout format, the first layout format and the second layout format being associated with the manner of implementing the at least one array in the integrated circuit, wherein transforming includes packing the array into a memory resource or a second array, and wherein packing further comprises at least one of the following: packing more than one word of the array into each word of the memory or the second array, packing the array to the memory or the second array in a little endian format, packing the array to the memory or the second array in a big endian format, packing the array into the memory or the second array in an interlacing format, packing a single word of the array into multiple words of the memory or the second array, packing the array into a customized location in the memory or the second array, or packing the array to a specified bit location within a specified word of the memory or the second array.