Patent ID: 7653167

Claim:
A circuit comprising: a phase interpolator-based data recovery circuit comprising: a first clock signal; a second clock signal; a third clock signal; a fourth clock signal; a first input clock controlled phase interpolator conditioner, wherein the first input clock controlled interpolator conditioner comprises a first set of digital 2-to-1 MUXs, wherein the first set of MUXs receive the first and third clock signal and, wherein the first set of MUXs are coupled to a first flip-flop, wherein said first flip-flop is configured to receive the second input clock signal and a first control signal as input; a second input clock controlled phase interpolator conditioner, wherein the second input clock controlled interpolator conditioner comprises a second set of digital 2-to-1 MUXs, wherein the second set of MUXs receive the second and fourth clock signal and, wherein the second set of MUXs are coupled to a second flip-flop, wherein said second flip-flop is configured to receive the third input clock signal and a second control signal as input, wherein the first control signal and the second control signal are independent of each other; and a phase interpolator mixer coupled to the first and second input clock controlled phase interpolator conditioners.