Patent ID: 8644107

Claim:
A system comprising: a controller comprising first, second and third terminals provided independently of each other; and a memory comprising fourth, fifth, sixth, seventh and eighth terminals provided independently of each other and the fourth, fifth and sixth terminals being provided correspondingly to the first, second and third terminals of the controller; the controller being configured to output a write data signal to the third terminal while the controller is clocking the first terminal, and the memory being configured to receive the write data signal from the sixth terminal while the fourth terminal is being clocked in response to the clocking the first terminal; the memory being configured to output a read data signal to the sixth terminal while the memory is clocking the fifth terminal and the controller being configured to receive the read data signal from the third terminal while the second terminal is being clocked in response to the clocking the fifth terminal, the memory being configured to clock the fifth terminal while the fourth terminal is being clocked, the fourth terminal is being clocked while the controller is clocking the first terminal, the fourth and seventh terminals being clocked in a differential transmission system, and the fifth and eighth terminals being clocked in the differential transmission system.