Patent ID: 8597991

Claim:
A method for fabricating a semiconductor device, the method comprising: forming a gate stack on an active region in a p-type field effect transistor (pFET) portion of a silicon-on-insulator (SOI) substrate, wherein the silicon-on-insulator substrate comprises a n-type field effect transistor (nFET) portion; forming a gate spacer over the gate stack; forming, while maintaining exposed a first region reserved for a source region and a second region reserved for a drain region in each of the pFET portion and the nFET portion of the SOI substrate, a first trench having dimension d″ in the first region reserved for the source region and a second trench having dimension d″ in the second region of the pFET portion, and a third trench having dimension d′″ in the first region and a fourth trench having dimension d′″ in the second region of the nFET portion, wherein each of the dimensions d″ and d′″ are different from each other; and epitaxially growing, while maintaining exposed the first and second regions of at least the pFET portion of the SOI substrate, silicon germanium within at least the first trench and the second trench.