Patent ID: 7035133

Claim:
A method of driving an SRAM-compatible memory including memory blocks and sense asnplifiers, the memory blocks each having DRAM cells arranged in a matrix form defined by rows and columns, the SRAM-compatible memory externally interfacing with an external system in which no timing period for performing a refresh operation is provided and first and second external access periods are provided for externally accessing the SRAM-compatible memory, the first external access period including a first refresh period and a first internal access period and the second external access period including a second refresh period, the method comprising the steps of: a) fetching data to be refreshed from a DRAM cell in a first row of a first memory block and storing the fetched data in a first sense amplifier during the first refresh period; b) storing the data fetched from the DRAM cell in the first row of the first memory block and stored in the first sense amplifier in a second sense amplifier; c) storing data accessed from a DRAM cell in a second row of the first memory block in the first sense amplifier during the first internal access period; and d) rewriting the data stored in the second sense amplifier in the DRAM cell in the first row of the first memory block during the second refresh period.