Patent ID: 7840629

Claim:
An apparatus, comprising: at least one encoder circuit including a plurality of logic gates operable to convert from radix 2 to radix 4 by receiving a group of bits of a multiplier and producing a set of encoded bits representing numbers of the group consisting of −2, −1, 0, 1, 2, wherein the set of encoded bits includes: a first bit that is true when the associated number is 2, a second bit that is true when the associated number is −2, a third bit that is true when the associated number is either negative or zero, and a fourth bit that is true when the associated number has an absolute value of 1; and a plurality of selector circuits, each operable to: (i) receive the encoded bits from the at least one encoder and a respective group of bits of the multiplicand, and (ii) produce a respective bit of a partial product wherein: each selector circuit is operable to receive a respective group of two bits of the multiplicand, Ai, Aj to produce the respective bit of a partial product, and each selector circuit includes a plurality of logic gates that are operable to produce an output bit, Si, in accordance with the following Boolean expression: Si=(B 1 !AND Aj) !AND (B 2 !AND Aj) !AND (B 4 !AND (B 3 XOR Ai)).