Patent ID: 8422306

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array comprising a set of NAND cell units, each NAND cell unit comprising a memory string and first and second select gate transistors connected to the respective ends of the memory string, the memory string comprising a plurality of non-volatile memory cells connected in series; a word line commonly connected to the control gates of the memory cells arranged in a direction intersecting the memory string; a bit line connected to a first end portion of each NAND cell unit; a source line connected to a second end portion of each NAND cell unit; a sense amplifier circuit configured to sense a potential or a current of the bit line to determine data held in the memory cell; and a control circuit configured to apply a write pulse voltage to a selected word line to perform a write operation to 1-page memory cells along the selected word line, and then perform a verify read operation to confirm whether data write to the 1-page memory cells is completed or not, and according to the result of the verify read operation, perform a step-up operation to raise the write pulse voltage by a step-up voltage, and perform the write operation again, the amount of the step-up voltage being changed according to a distribution width of a first threshold voltage distribution generated during a process of the write operation to the memory cells.