Patent ID: 8659112

Claim:
An integrated circuit (IC), comprising: a substrate having a semiconductor surface; at least a core PMOS transistor and a non-core PMOS transistor formed in said substrate, wherein said core and said non-core PMOS transistor each comprise: a gate structure including a gate electrode on a gate dielectric formed over said semiconductor surface, wherein said gate dielectric for said core PMOS transistor is at least 2 Å of equivalent oxide thickness (EOT) thinner as compared to said gate dielectric for said non-core PMOS transistor; source/drain regions formed in said semiconductor surface on both sides of said gate structure, and source/drain extension regions formed on both sides of said gate structure, wherein said source/drain regions are distanced from said gate structure further than said source/drain extension regions, wherein said non-core PMOS transistor includes co-doping in its source/drain extension region comprising carbon and nitrogen each having minimum peak concentrations of 1×10 16 /cm 3 , and said core PMOS transistor excludes at least one of said carbon and said nitrogen.