Patent ID: 7283603

Claim:
A shift register, comprising: a. a start pulse input line for providing a start pulse; b. a first signal line for providing a first clock signal; c. a second signal line for providing a second clock signal; d. a third signal line for providing a third clock signal; e. a fourth signal line for providing a fourth clock signal; and f. a plurality of stages, {S j }, j=1, 2, . . . , N, N being a positive integer, wherein the j-th stage S j comprises: (i). a first to fourth inputs, wherein when j is an odd number, the first to fourth inputs are electrically coupled to the first, second, third and fourth signal lines for receiving the first, second, third and fourth clock signals, respectively, and when j is an even number, the first to fourth inputs are electrically coupled to the third, fourth, first and second signal lines for receiving the third, fourth, first and second clock signal, respectively; (ii). a fifth input for receiving an input signal; (iii). a first output electrically coupled to a corresponding gate for providing a gate driving signal to the gate responsive to the input signal and the first to fourth clock signals, wherein the gate driving signal is shifted from the input signal; and (iv). a second output for providing an output signal having a frequency and a phase that are substantially same as those of the gate driving signal, respectively, wherein the plurality of stages {S j } are electrically coupled in serial such that the fifth input of the first stage S 1 is electrically coupled to the start pulse input line for receiving the start pulse, and the fifth input of the i-th stage S i , i=2, 3, . . . N, is electrically coupled to the second output of the (i−1)-th stage S i−1 , for receiving a corresponding output signal therefrom, wherein each of the first to fourth clock signals is characterized with a frequency and a phase, wherein the frequency of the first clock signal and the frequency of the third clock signal are substantially identical and the phase of the first clock signal and the phase of the third clock signal are substantially reversed, and wherein the frequency of the second clock signal and the frequency of the fourth clock signal are substantially identical and the phase of the second clock signal and the phase of the fourth clock signal are substantially reversed, respectively, and wherein the frequency of the first clock signal is higher than the frequency of the second clock signal.