Patent ID: 7291923

Claim:
In an integrated circuit, a layer including a plurality of conductive wires, the layer comprising: a horizontal surface of a first wire of the plurality of conductive wires having a proximal end and a distal end, the proximal end having a first width, the distal end having a second width, the second width being less than the first width, the first wire tapered from the proximal end to the distal end, the first wire further having a first substantially vertical surface; a second wire of the plurality of conductive wires spaced apart from the first wire, the second wire having a second substantially vertical surface, the first wire and the second wire each horizontally disposed along side each other, wherein capacitors are created between the first substantially vertical surface and the second substantially vertical surface, the capacitors respectively associated with capacitances, the capacitors being associated with a plurality of loads, the plurality of loads being progressively reduced responsive to a progressive reduction of the capacitances as associated with the first wire taper; and a plurality of taps, a tap of the plurality of taps located between a pair of loads of the plurality of loads.