Patent ID: 8264905

Claim:
A nonvolatile memory device comprising: multiple memory cell blocks; multiple section word line driver blocks; a main word line traversing the multiple memory cell blocks and being coupled to each of the multiple section word line driver blocks; a floating prevention circuit which includes elements each directly connected to a corresponding sub-word line and the main word line, wherein wherein each of the multiple memory cell blocks includes the multiple sub-word lines connected to corresponding nonvolatile memory cells located in the each of the multiple memory cell blocks; and each of the multiple section word line driver blocks includes a section word line driver including multiple pull-down transistors and a selection transistor, wherein each of the multiple pull-down transistors has one node connected to a corresponding sub-word line and another node connected to a common node, and the selection transistor has a gate connected to the main word line, one node connected to the common node and another node connected to a ground.