Patent ID: 8018756

Claim:
A semiconductor memory device comprising: a plurality of word lines each of which includes a writing word line and a reading word line; a plurality of bit lines each of which includes first and second writing bit lines and a reading bit line, the first and second writing bit lines and the reading bit line intersecting with the plurality of word lines; a plurality of memory cells that are provided at portions in which the plurality of word lines and the plurality of bit lines intersect with each other, wherein the memory cell includes: a flip-flop circuit in which inputs and outputs of a first inverter and a second inverter are mutually connected, the first inverter including a first transistor of the first conduction type and a second transistor of the second conduction type, the first inverter being connected between a power supply line and a ground line, the second inverter including a third transistor of the first conduction type and a fourth transistor of the second conduction type, the second inverter being connected between the power supply line and the ground line; a fifth transistor of the second conduction type that is connected between the output of the first inverter and the first writing bit line, a gate of the fifth transistor being connected to the writing word line; a sixth transistor of the second conduction type that is connected between the output of the second inverter and the second writing bit line, a gate of the sixth transistor being connected to the writing word line; a seventh transistor of the second conduction type, in which a drain is connected to the reading bit line and a gate is connected to the reading word line; and an eighth transistor, in which a source is connected to the ground line, a drain is connected to the source of the seventh transistor, and a source is connected to the input of the first inverter and the output of the second inverter, wherein the writing word line is divided into a plurality of unit writing word lines, and data is written in the predetermined memory cell connected to the selected unit writing word line during data write, wherein thresholds of the seventh and eighth transistors are equal thresholds of the fifth and sixth transistors, and are lower than the thresholds of the second and forth transistors, wherein the reading bit line is precharged to the power supply potential during a normal operation, and is not precharged to the power supply potential during standby, and whenever data is not being written to the memory cell, the first and second writing bit lines are in a floating state and are not precharged to a predetermined potential.