Patent ID: 8542226

Claim:
A gate pulse modulating circuit, comprising: a timing controller, generating an output enable signal and multiple time control signals; a high gate voltage generating unit, electrically connected to timing controller and for receiving the time control signals, and generating a high gate voltage with a waveform including a plurality of cutting edges in response to the time control signals; a low gate voltage generating unit, generating a low gate voltage; and a gate driver, electrically connected to the timing controller for receiving the output enable signal, the high gate voltage generating unit for receiving the high gate voltage and the low gate voltage generating unit for receiving the low gate voltage, and generating a plurality of gate pulses in response to a plurality of enable periods of the output enable signal; wherein a waveform of the gate pulses includes a plurality of cutting edges; wherein the time control signals comprise a first time control signal and a second time control signal, and the high gate voltage generating unit comprises: a first inverter, having an input to receive the first time control signal; a first transistor, having a gate electrically connected to an output of the first inverter, a source to receive a maximum voltage, and a drain connected to a high gate voltage output; a second transistor, having a gate electrically connected to the output of the first inverter, and a drain connected to the high gate voltage output; a first resistor, connected between a source of the second transistor of and a first voltage; a second inverter, having an input to receive the second time control signal; a third transistor, having a gate electrically connected to an output of the second inverter output and a drain connected to the output of the first inverter; a fourth transistor, having a gate electrically connected to a source of the third transistor, and a drain connected to the high gate voltage output; and a second resistor, connected between a source of the fourth transistor and a second voltage; and wherein the maximum voltage is greater than the first voltage, and the first voltage is greater than the second voltage.