Patent ID: 7238602

Claim:
A process of chip-size package, comprising the steps of: separating dice having pads on a wafer; forming a first contact conductive layer on said dice to cover said pads; forming a first dielectric layer on said first contact conductive layer and said dice to form first openings exposing said first contact conductive layer; placing said dice including said pads, said first contact conductive layer and said first dielectric layer formed on a base; filling a first material layer on said base into a space among said dice on said base; patterning a second dielectric layer to form second openings exposing said first contact conductive layer; filling and patterning a second conductive material layer into said second openings and on said second dielectric layer; patterning a second material layer to form third openings exposing said conductive second material; and welding solder balls on said third openings.