Patent ID: 7317656

Claim:
A process for operating a semi-conductor memory component, comprising: activating memory cells of a memory cell array, included in a first set of memory cells in a same row or column of the memory cell array, when at least one of the memory cells included in the first set requires access; accessing a corresponding memory cell or memory cells; deactivating the memory cells included in the first set of memory cells, when access to at least one further memory cell, not included in the first set of memory cells, occurs; and prematurely deactivating the memory cells included in the first set of memory cells when a pre-determined time or number of pulses after the at least one of the memory cells included in the first set of memory cells have last been accessed, and no further accessing of the at least one of the memory cells included in the first set of memory cells occurs within the predetermined time or number of pulses.