Patent ID: 8111760

Claim:
A deblock filter unit comprising: a first pixel data buffer for temporarily storing a block of contiguous pixels of a predetermined size; a second pixel data buffer for temporarily storing a block of contiguous pixels of said predetermined size; a deblock hardware module operable to perform a deblock filter operation on pixel data; a first memory access switch operable to connect to a frame buffer and alternately connected to said first and second data buffers; a second memory access switch operable to connect to said deblock hardware module and alternately connected to said first and second data buffers; wherein said first and second memory access switches operate cooperatively in a first mode during which pixel data may be transferred between the frame memory and said first pixel buffer via said first memory access switch and pixel data may be transferred between said second pixel buffer and said deblock filter module via said second memory access switch, and a second mode during which pixel data may be transferred between the frame memory and said second pixel buffer via said first memory access switch and pixel data may be transferred between said first pixel buffer and said deblock filter module via said second memory access switch; wherein said deblock filter module is operable to deblock filter along 8 by 8 pixel horizontal boundaries, deblock filter along 8 by 4 pixel horizontal boundaries, deblock filter along 8 by 8 pixel vertical boundaries, and deblock filter along 4 by 8 pixel vertical boundaries; and wherein said deblock filter module is further operable to deblock filter along 8×8 pixel horizontal boundaries and said deblock filter along 8×4 pixel horizontal boundaries occur in a single 16 pixel horizontal stripe filtering operation including filtering horizontal stripes i from i=0 to an end of a frame by recalling rows 16 i to 16 i +19 from the first or second pixel data buffer according to a current mode of said first and second memory access switches, updating 8 rows 16 i +7, 16 i+ 8, 16 i+ 3, 16 i+ 4, 16 i+ 15, 16 i+ 16, 16 i+ 11, 16 i+ 12, and storing said updated rows in the first or second pixel data buffer according to said current mode of said first and second memory access switches.