Patent ID: 7045410

Claim:
A method of reducing a difference in threshold voltages between PMOS transistors and NMOS transistors in a CMOS device, comprising: forming an isolation hard mask layer over an NMOS region and a PMOS region of a semiconductor body; patterning the isolation hard mask layer, thereby defining isolation regions in both the NMOS region and the PMOS region of the semiconductor body, the isolation regions having a width associated therewith; implanting an n-type dopant solely into the isolation regions of the semiconductor body using the patterned isolation hard mask, thereby forming threshold voltage compensation regions in both the NMOS and PMOS regions having a depth associated therewith, and the compensation regions having a width greater than the width of the isolation regions; patterning the semiconductor body using the patterned isolation hard mask after performing the implant, thereby forming isolation trenches in the semiconductor body having a depth greater than the depth of the compensation regions and separating the compensation regions into compensation sub-regions on sides of the isolation trenches; filling the isolation trenches with a dielectric material; forming a p-type region in the NMOS region and an n-type region in the PMOS region either before or after implanting the n-type dopant in the isolation regions, wherein the n-type dopant within the compensation sub-regions causes an increase in p-type dopant loss to the isolation region in the NMOS region, and causes a decrease in n-type dopant loss to the isolation region in the PMOS region, thereby causing an increase in threshold voltage for NMOS transistors in the NMOS region and a decrease in threshold voltage for PMOS transistors in the PMOS region.