Patent ID: 7600176

Claim:
An apparatus, comprising: a plurality of adders; a plurality of multipliers; a memory that is operable to: output a first plurality of symbol elements, in parallel format, to the plurality of adders and to the plurality of multipliers such that each element of the first plurality of symbol elements is provided to one adder within the plurality of adders and to one multiplier within the plurality of multipliers; output a second plurality of symbol elements, in parallel format, to the plurality of adders and to the plurality of multipliers such that each element of the second plurality of symbol elements is provided to one adder within the plurality of adders and to one multiplier within the plurality of multipliers; and a processor that is operable to control alternative writing of a first resultant and a second resultant to the memory; and wherein: the first resultant is generated by the multiplication of the first plurality of symbol elements and the second plurality of symbol elements using the plurality of multipliers; and the second resultant is generated by the adding of the first plurality of symbol elements and the second plurality of symbol elements using the plurality of adders.