Patent ID: 8890579

Claim:
An integrated circuit, comprising: a high-voltage n-channel metal oxide semiconductor (MOS) power transistor, having: a drain node; a source node, said power transistor source node being directly electrically connected to an instance of a ground node of said integrated circuit; and a gate node, said power transistor gate node being connected to a power switching signal source capable of providing an off state bias which puts said power transistor into an off state and capable of providing an on state bias which puts said power transistor into an on state; such that said power transistor is capable of operating with at least 300 volts on said power transistor drain node; a high-voltage n-channel MOS blocking transistor, having: a drain node, said blocking transistor drain node being electrically connected to said power transistor drain node; a source node, said blocking transistor source node being electrically isolated from said ground node of said integrated circuit; and a gate node coupled to a bias current source clamped with respect to the source node; such that said is him as blocking transistor is capable of operating with at least 300 volts on said power transistor drain node; a high-voltage n-channel MOS reference transistor, having: a drain node, said reference transistor drain node being connected in series with a reference current source; and a gate node, said reference transistor gate node being coupled to said power transistor gate node, wherein said reference transistor gate node is directly electrically connected to said power transistor gate node; a voltage comparator, having: an inverting input, said comparator inverting input being connected to said reference transistor drain node; a non-inverting input, said comparator non-inverting input being coupled to said blocking transistor source node, a buffer and a voltage divider coupled between said blocking transistor source node and said comparator non-inverting input; and an output, said comparator being configured to provide an overcurrent signal at said comparator output when a potential at said comparator non-inverting input is higher than a potential at said comparator inverting input.