Patent ID: 7199469

Claim:
A semiconductor device comprising: a first semiconductor chip having on one main surface thereof a control circuit, a first bonding pad, and a plurality of second bonding pads; a second semiconductor chip having on one main surface thereof a memory circuit and a third bonding pad and disposed on the one main surface of the first semiconductor chip, the memory circuit being controlled in accordance with a control signal generated in the control circuit on the first semiconductor chip; a first lead having an inner lead portion and an outer lead portion integral with the inner lead portion, the inner lead portion being disposed at a position around the first semiconductor chip; a plurality of second leads each having an inner lead portion and an outer lead portion integral with the inner lead portion, the inner lead portion being disposed at a position around the first semiconductor chip; a first bonding wire for connecting the first bonding pad on the first semiconductor chip with the inner lead portion of the first lead; a plurality of second bonding wires for connecting the plural second bonding pads on the first semiconductor chip with the inner lead portions of the plural second leads; a third bonding wire for connecting the third bonding pad on the second semiconductor chip with the inner lead portion of the first lead; and a resin seal member for sealing the first and second semiconductor chips, the first, second and third bonding wires, and the inner lead portions of the first and second leads, wherein the control signal generated in the control circuit is outputted from the first bonding pad on the first semiconductor chip and is inputted to the third bonding pad on the second semiconductor chip through the first bonding wire, the first lead and the third bonding wire.