Patent ID: 8400754

Claim:
A plurality of ceramic electronic components in which a plated layer is formed on a surface of a portion of each of a plurality of ceramic element bodies, comprising: a plurality of ceramic element bodies having upper and lower surfaces and left and right side surfaces connecting the upper and lower surfaces; and a plurality of plated layers in which each of the plated layers is arranged to extend from one end of the upper surface of each of said plurality of ceramic element bodies to one end of the lower surface by passing through at least one of the left side surface and the right side surface; wherein each of the plurality of plated layers includes a first portion that is disposed on the one end of the upper surface of each of said plurality of ceramic element bodies and a second portion that is disposed on the one end of the lower surface of each of said plurality of ceramic element bodies; a ratio of a standard deviation relative to an average value of lengths of the first and second portions of said plurality of plated layers disposed on the one end of the upper surface and the lower surface of each of said plurality of ceramic element bodies is about 3% or less.