Patent ID: 7586123

Claim:
A thin film transistor array substrate, comprising: a gate electrode connected to a gate line; a source electrode connected to a data line, which crosses the gate line to define a pixel area; a drain electrode opposed to the source electrode with a channel therebetween; a active layer in the channel; a first and second ohmic contact layers disposed on the active layer and being spaced apart from each other, wherein the first ohmic contact layer is beneath the source electrode and the second ohmic contact layer is beneath the drain electrode; a pixel electrode contacting with the drain electrode; and a channel protective film provided on the active layer corresponding to the channel to protect the active layer in the channel, wherein all of the channel protective film is disposed only between the first and second ohmic contact layers, wherein a bottom surface of the channel protective film is lower than a uppermost surface of the first and second ohmic contact layers and a top surface of the channel protective film is higher than the uppermost surface of the first and second ohmic contact layers.