Patent ID: 6913975

Claim:
A method of manufacturing a non-volatile memory cell in a substantially single crystalline semiconductive material of a first conductivity type, wherein said method comprising: forming a first region and a second region in said material, with said first region and said second region being of a second conductivity type, different from said first conductivity type, with a channel region for the conduction of charges connecting said first region and said second region; said channel region, having a first portion and a second portion, with said first portion of said channel region adjacent to said first region and said second portion of said channel between said first portion and said second region; forming a dielectric on said channel region; forming a sacrificial layer on said dielectric; forming a first cavity in said sacrificial layer, said first cavity being spaced apart from said first portion of said channel region; forming a first floating gate in said first cavity; and forming a gate electrode, capacitively coupled to said first floating gate, and spaced apart from said second portion of said channel region.