Patent ID: 7274062

Claim:
A non-volatile memory, comprising: a substrate; a plurality of trench isolation structures, disposed in the substrate to define a active region; a first conducting type well region, disposed in the substrate; a second conducting type shallow doped region, disposed in the first conducting type well region and contiguous to a surface of the substrate; a pair of stacked gate structures, disposed in the active region of the substrate and at each side of the trench isolation structures, wherein each stacked gate structure further comprises at least a floating gate layer and a control gate layer on the floating gate layer; two second conducting type pocket doped regions, respectively disposed at peripheries of the pair of stacked gate structures in the substrate, wherein each pocket doped region extends to an underneath of each stacked gate structure; two first conducting type drain regions, respectively disposed in the pocket doped regions which is at the outer side of the stacked gate structure; an auxiliary gate layer, disposed between the two stacked gate structures on the substrate, and wherein a bottom of the auxiliary gate layer is lower than a bottom of the second conducting type shallow doped layer; a gate dielectric layer, at least disposed between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structures; and at least two conducting plugs, disposed on the substrate, and the conducting plug further extended downward to connect with the pocket doped regions and the drain regions in the pocket doped regions.