Patent ID: 7041594

Claim:
A method for fabricating a semiconductor device, comprising: forming a well of a first conduction type in a substrate; forming an impurity region of a second conduction type in the first conduction type well; forming a lower interlayer dielectric on the substrate including the well and the impurity region; selectively etching the lower interlayer dielectric to form an opening exposing the impurity region; filling the opening with a first conductive layer to form a contact plug, wherein a void is formed in the contact plug; forming an upper interlayer dielectric on the lower interlayer dielectric including the contact plug; selectively etching the upper interlayer dielectric to form an interconnection groove exposing the contact plug; overetching the contact plug and a substrate including the exposed void to expose the void to the well; and filling the interconnection groove with a second conductive layer to form an interconnection, wherein: a seam connecting the contact plug to the well is formed at the void extended to the well.