Patent ID: 7548447

Claim:
A semiconductor memory device, comprising: a semiconductor substrate; first lines oriented in one direction and separately arranged on the semiconductor substrate in another direction; floating bodies separately arranged on the first lines at a predetermined interval at locations on which memory cells are arranged; gates arranged adjacently to the floating bodies and respectively insulated from the floating bodies; word lines separately arranged above the first lines in a perpendicular direction to the first lines and electrically connected to the gates arranged in a perpendicular direction to the first lines; drains respectively arranged on the floating bodies; and second lines separately arranged on the drains to overlap the first lines and electrically connected to the drains oriented in the same direction as the first lines, wherein lines of one group among a group of the first lines and a group of the second lines are bit lines and lines of the other group among the group of the first lines and the group of the second lines are source lines, and a voltage applied to the source lines during a write operation is different from a voltage applied to the source lines during a read operation.