Patent ID: 7611952

Claim:
A semiconductor device manufacture method comprising the steps of: (a) forming an isolation region surrounding and defining each of a plurality of active regions and each of a plurality of dummy regions of a semiconductor substrate, said active regions being regions for forming transistors, said dummy regions being regions in which no transistors are formed; (b) forming thin insulating films on said active regions and dummy regions; (c) forming a gate electrode on the thin insulating films in said active regions; (d) implanting impurity ions in said active regions by using said gate electrodes as a mask to form shallow source/drain regions; (e) depositing a spacer insulating film on said semiconductor substrate, said spacer insulating film covering said gate electrodes; (f) anisotropically etching said spacer insulating film, detecting as an etching end point a time when surfaces of said semiconductor substrate are exposed in said active regions and dummy regions, wherein an area of thin insulating film is increased by forming a thinnest insulating film in the dummy region, and leaving side wall spacers on side walls of each of said gate electrodes; and (g) implanting impurity ions into said active regions by using said gate electrodes and side wall spacers as a mask to form low resistivity and deep source/drain regions in said active regions.