Patent ID: 7510943

Claim:
A method of manufacturing a semiconductor device, the method comprising: providing a workpiece; forming a first gate dielectric material over the workpiece in a first region of the workpiece; forming a second gate dielectric material over the workpiece in a second region of the workpiece, the second gate dielectric material comprising a different material than the first gate dielectric material; patterning the first gate dielectric material and the second gate dielectric material to form a first gate dielectric of a first transistor and a second gate dielectric of a second transistor; forming recesses in the workpiece proximate the first gate dielectric and the second gate dielectric; filling the recesses in the workpiece proximate the first gate dielectric with a first dopant-bearing metal, the first dopant-bearing metal comprising a first dopant; filling the recesses in the workpiece proximate the second gate dielectric with a second dopant-bearing metal, the second dopant-bearing metal comprising a second dopant, the second dopant being different than the first dopant; and annealing the workpiece, causing diffusion of the first dopant and second dopant into the workpiece, forming first doped regions within the workpiece adjacent the first dopant-bearing metal and second doped regions within the workpiece adjacent the second dopant-bearing metal, wherein the first dopant-bearing metal and the first doped regions comprise a source region and a drain region of the first transistor, and wherein the second dopant-bearing metal and the second doped regions comprise a source region and a drain region of the second transistor.