Patent ID: 8116132

Claim:
A flash memory device including a multi-level cell, comprising: a wordline voltage generating unit generating a plurality of wordline voltages having different corresponding voltage levels for read operations of the multi-level cell, the plurality of wordline voltages comprising a first wordline voltage having a first voltage level, a second wordline voltage having a second voltage level higher than the first voltage level, and a third wordline voltage having a third voltage level higher than the second voltage level; a switch unit receiving the plurality of wordline voltages from the wordline voltage generating unit and an initialization voltage, and selectively outputting each of the plurality of wordline voltages and the initialization voltage through sequential switching operations to read the multi-level cell during a current read cycle, the switch unit comprising a plurality of first switches, respectively connected between the plurality of wordline voltages and an output node, and a second switch, connected between the initialization voltage and the output node; and a row decoder for operating the wordline of the multi-level cell based on an output of the switch unit, wherein the initialization voltage is provided to the output node immediately after each of the second wordline voltage and the third wordline voltage is provided to the output node during the current read cycle.