Patent ID: 8386755

Claim:
A microprocessor configured to execute an instruction, the instruction specifying a floating-point input operand having a predetermined size, wherein the instruction instructs the microprocessor to round the floating-point input operand to an integer value using a rounding mode and return the integer value as a floating-point result having the same predetermined size as the input operand, the microprocessor comprising: an instruction translator, configured to translate the instruction into first and second microinstructions; and an execution unit, configured to execute the first and second microinstructions; wherein the first microinstruction receives as an input operand the instruction floating-point input operand and generates an intermediate result from the instruction input operand; wherein the second microinstruction receives as an input operand the intermediate result of the first microinstruction and generates the floating-point result of the instruction from the intermediate result; wherein the intermediate result is the same predetermined size as the instruction floating-point input operand.