Patent ID: 8826090

Claim:
An integrated circuit comprising: A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead; B. test access port circuitry coupled to the test data in lead, the test data out lead, the test clock lead, and the test mode select lead, the test access port circuitry including a data register coupled to the test data in lead and the test data out lead and having parallel connections with other circuitry, and including state machine circuitry coupled with the test clock lead, the test mode select lead, and the data register; and C. TMS communication circuitry having a bi-directional data connection with the test mode select lead and connections with data source circuitry and data destination circuitry that are separate from the other circuitry, the TMS communication circuitry including state machine circuitry, separate from the state machine in the test access port circuitry, coupled with the data source circuitry and the data destination circuitry.