Patent ID: 8707009

Claim:
An integrated circuit comprising: a variable-width data port operable to communicate first data of a first data width or second data of a second data width; a fixed-width data port operable to convey third data of a third data width to a memory die; and a data-width translator coupled between the variable-width and fixed-width data ports, the data-width translator supporting data-width configurations, including: a first data-width configuration in which the data-width translator translates the first data of the first data width and a first data rate on the variable-width data port to the third data of the third data width and the first data rate on the fixed-width data port; and a second data-width configuration in which the data-width translator translates the second data of the second data width and a second data rate on the variable-width data port to the third data of the third data width and the second data rate on the fixed-width data port; wherein the data-width translator includes an address translator operable to translate at least one bit of an external address into a data-mask signal to the memory die.