Patent ID: 7383453

Claim:
An instruction-processing system with minimal static power leakage, the instruction-processing system comprising: a core with instruction-processing circuitry; an area coupled to the core; a core voltage provided to the core; and an area voltage provided to the area; wherein in a normal operation mode: a clock signal to the core is active; the core voltage is a first value; the core is active; the area voltage is a second value; and the area is active; wherein in a first power-saving mode that is exited upon receipt of an interrupt signal: the clock signal to the core is inactive; the core voltage is equal to or greater than the first value; and the area voltage is equal to or greater than the second value; wherein in a second power-saving mode that can be exited upon receipt of a signal that is not an interrupt signal: the clock signal to the core is inactive; the core voltage is less than the first value; and the area voltage is equal to or greater than the second value.