Patent ID: 8625384

Claim:
A synchronous type semiconductor storage device comprising: an array unit which includes a cell array and sense amplifiers, the cell array comprising a plurality of memory cells disposed in a lattice shape, and the sense amplifiers connected to the memory cells through bit lines; a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one cycle time of a read operation and a write operation with respect to the array unit as one cycle; a secondary amplifier which is connected to the sense amplifiers through a read/write line and which is activated according to the read pulse signal to read out data stored in the sense amplifiers through the read/write line; and a write driver which is connected to the sense amplifiers through the read/write line and which is activated according to the write pulse signal to write data in the sense amplifiers through the read/write line, wherein the read/write pulse generator includes: a ½ frequency divider which is input with the clock signal and outputs a first frequency-divided signal formed by ½-dividing a frequency of the clock signal; a first inverter which is input with the first frequency-divided signal and outputs a second frequency-divided signal formed by inverting the first frequency-divided signal; a first pulse generation circuit which is input with the first frequency-divided signal, and which generates and outputs a first pulse signal based on the first frequency-divided signal; a second pulse generation circuit which has the same configuration as that of the first pulse generation circuit, which is input with the second frequency-divided signal, and which generates and outputs a second pulse signal based on the second frequency-divided signal; and a first OR circuit which is input with the first pulse signal and the second pulse signal, and which outputs the read pulse signal and the write pulse signal.