Patent ID: 7599361

Claim:
A network processor for maintaining processing order of data packets in a process flow, the network processor comprising: a packet input queue, each packet in said queue having a unique flow-identification; a plurality of pipeline units having respective inputs and outputs disposed within the network processor, each pipeline unit (PU) capable of accepting a received packet from the packet input queue and comprising a predetermined number of pipeline stages for processing the received packet by the network processor, wherein the number of pipeline stages is at least two; multiple flow-identification content addressable memories (FICAM), each said FICAM associated with a respective PU and comprising a number of locations, equal to the number of pipeline stages in said respective PU, for accepting respective flow-identifications of packets being processed by the pipeline stages of said respective PU; each said FICAM including: a row of content addressable memory (CAM) cells operative to store a first flow-identification, the first flow-identification corresponding to a first packet dispatched for processing by a PU; and a comparison unit operative: to compare a second flow-identification corresponding to a second packet with contents of said row of CAM cells; to make a determination if the second flow-identification is same as the first flow-identification; to generate a hit message if said second flow-identification is the same as the first flow-identification; and to generate a miss message when none of said multiple FICAM comparison units generate a hit message; and a controller, responsive to said hit message, operative to reschedule said second packet such that said second packet is not placed in a PU until said miss message is generated, to maintain processing order of said first and said second packets.