Patent ID: 7880519

Claim:
A delay synchronization loop type clock signal generating circuit, comprising: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring type shift register for setting time length of said digital delay line by flip-flop output of each stage thereof; and a delay amount control unit for controlling supply of shift clocks to said ring-type shift register, based on a phase relation between said first clock signal and said second clock signal, wherein, said digital delay line is a configuration of a serial connection of (a) a first delay line for coarse adjustment of delay time and (b) a second delay line for fine adjustment of delay time, said ring-type shift register is a configuration of (a) a first ring-type shift register corresponding to said first delay line and (b) a second ring-type shift register corresponding to said second delay line, said delay amount control unit is a configuration of (a) a first delay amount control unit corresponding to said first delay line and (b) a second delay amount control unit corresponding to said second delay line, and said shift clock which drives said first and second ring-type shift registers has a frequency lower than said first clock signal or said second clock signal.