Patent ID: 7076601

Claim:
A semiconductor device comprising: a memory controller receiving commands from a CPU, and controlling a memory including a plurality of memory banks, wherein said memory controller has a first mode and a second mode, wherein each of said plurality of memory banks comprises a plurality of word lines, data lines, and memory cells, wherein said memory is controlled to precharge after a read access in said first mode, wherein said memory is controlled to receive next access command without precharge operation after a read access in said second mode, wherein when a refresh command is received by said memory controller, said memory controller precharges said plurality of memory cells of said plurality of memory banks before refreshing said plurality of memory cells, wherein a successive read access after refresh command is operated without a precharge operation, wherein said memory controller comprises a page access decision circuit, a mode changing circuit, and an address generating circuit, wherein said page decision circuit compares a row address inputted to said memory controller and the previous address, wherein said mode changing circuit receives signals from said page decision circuit and holds information of a number of consecutive access to each of said plurality of said memory banks, and wherein said address generating circuit receives signals from said page decision circuit and from said mode changing circuit and outputs bank active commands, bank addresses, row addresses, and column addresses to said memory.