Patent ID: 8921945

Claim:
A combined DMOS/IGBT power transistor for integration in SOI-technology and configured for high voltages, the power transistor comprising: a low doped active layer ( 3 ) with a thickness of about 50 μm; a plurality of individual source cells ( 11 ), each comprising: a well area ( 7 ) comprising a doping that is opposite to the active layer ( 3 ) to form a pn-transition between the well area ( 7 ) and the active layer ( 3 ), a highly doped source area ( 9 ), and a gate area ( 10 ); a highly doped vertical layer ( 5 ), one side thereof being adjacent to an isolation trench ( 4 ) and another side thereof being adjacent to the active layer ( 3 ); a highly doped embedded lateral layer ( 6 ) arranged above and adjacent to an embedded oxide layer and below the low doped active layer ( 3 ), wherein the highly doped embedded lateral layer ( 6 ) is connected to the highly doped vertical layer ( 5 ) and the active layer ( 3 ), the highly doped vertical layer ( 5 ), the highly doped embedded lateral layer ( 6 ) and the source area ( 9 ) having the same charge carrier type; a drain area ( 8 ) forming a DMOS-drain area connected to the highly doped vertical layer ( 5 ), said drain area and the connection forming a vertical DMOS structure that further comprises the low doped active layer ( 3 ), the plurality of individual source cells ( 11 ), the highly doped vertical layer ( 5 ), and the highly doped embedded lateral layer ( 6 ); a highly doped IGBT collector ( 21 ) with an opposite charge carrier type as the low doped active layer ( 3 ), proximal to a surface of the highly doped vertical layer ( 5 ), the IGBT collector reaching into the highly doped vertical layer ( 5 ) to form a pn-transition between the highly doped vertical layer ( 5 ) and the highly doped IGBT collector ( 21 ) forming a part of a lateral IGBT structure that further comprises the low doped active layer ( 3 ) and the plurality of individual source cells ( 11 ); a contact ( 14 ) connected to at least a portion of the DMOS-drain area ( 8 ) and at least a portion of the highly doped IGBT collector ( 21 ), the contact thereby forming a common connection for the DMOS-drain area ( 8 ) and the IGBT collector ( 2 ) and wherein the DMOS-drain area ( 8 ) and the highly doped IGBT collector ( 21 ) are arranged proximal to the surface of the highly doped vertical layer ( 5 ) and the DMOS-drain area ( 8 ) has a smaller top surface extension than the highly doped IGBT collector ( 21 ).