Patent ID: 7161390

Claim:
A latching dynamic logic structure comprising: a dynamic logic gate coupled to a static logic input interface and a static set-reset output latch; said dynamic logic gate receiving a clock signal, a data signal, and a select signal output of the static logic input interface; said dynamic logic gate including a dynamic node and a pulldown network coupled to the dynamic node; said dynamic logic gate including a precharge transistor for precharging said dynamic node prior to the clock signal transition; said pulldown network selectively discharging said dynamic node following a clock signal transition dependent on the data signal and the received select signal output of the static logic input interface being active; said pulldown network coupled in series with an evaluation transistor for discharging said dynamic node following the clock signal transition dependent upon the data signal and the received select signal output of the static logic input interface being active; said pulldown network including a pair of series connected transistors connected between said dynamic node and an evaluation transistor; and said set-reset output latch being coupled to said dynamic node of the dynamic logic gate for providing an output signal.