Patent ID: 7825456

Claim:
An apparatus comprising: isolation patterns formed in a semiconductor substrate; a bit line comprising a high-density first-type ion implantation region formed in an upper portion of an active region of the semiconductor substrate between the isolation patterns; a well tap region comprising a first high-density second-type ion implantation region formed in an upper portion of the semiconductor substrate and spaced apart from the high-density first-type ion implantation region; second high-density second-type ion implantation regions formed below the high-density first-type ion implantation region and the first high-density second-type ion implantation region such that the uppermost surface thereof is below the uppermost surface of the high-density first-type ion implantation region and the first high-density second-type ion implantation region, respectively; an insulating layer pattern formed on and contacting the high-density first-type ion implantation region, the high-density second-type ion implantation regions and the uppermost surface of the isolation patterns; and an word line interconnection formed on the insulating layer pattern and crossing over the high-density first-type ion implantation region.