Patent ID: 8751694

Claim:
A device that can perform a data transfer operation in response to each of data transfer commands and can accept a new data transfer command while a data transfer operation responsive to a previous data transfer command is in progress, comprising: a plurality of first latch circuits each including a clock terminal, an input terminal and an output terminal, the first latch circuits being connected such that the output terminal of a preceding one of the first latch circuits is connected to the input terminal of a succeeding one of the first latch circuits and the output terminal of an ending one of the first latch circuits is connected to the input terminal of a starting one of the first latch circuits, a plurality of second latch circuits each including a clock terminal, an input terminal and an output terminal, the second latch circuits being connected such that the output terminal of a preceding one of the second latch circuits is connected to the input terminal of a succeeding one of the second latch circuits and the output terminal of an ending one of the second latch circuits is connected to the input terminal of a starting one of the second latch circuits, a first node supplied with a transfer initiation signal that takes an active level each time the data transfer operation responsive to each data transfer command is initiated, the first node being connected in common to the clock terminals of the first latch circuits, a second node supplied with a transfer completion signal that takes an active level each time the data transfer operation responsive to each data transfer command is completed, the second node being connected in common to the clock terminals of the second latch circuits, a plurality of first logic circuits each connected to the output terminal of an associated one of the first latch circuits and the output terminal of an associated one of the second latch circuits, each of the first logic circuits being configured to produce a first signal when both of the associated one of the first latch circuits and the associated one of the second latch circuits produce a first logic level at the output terminals thereof and a second signal when at least one of the associated one of the first latch circuits and the associated one of the second latch circuits produces the output terminal thereof a second logic level, and a second logic circuit coupled to the first logic circuits, the second logic circuit being configured to produce an active level when at least one of the first logic circuits produces the first signal.