Patent ID: 7723799

Claim:
A semiconductor device, comprising: a P-substrate; an N-well disposed in the P-substrate; an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage; a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage; a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage; an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage; and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a conductive state brought by a gate substantially connected to the ground voltage to maintain the low voltage to be substantially at the ground voltage until a possibility that the low voltage rises higher than the ground voltage is eliminated.