Patent ID: 7145792

Claim:
A semiconductor integrated circuit device having a memory circuit comprising: a memory array including: a plurality of word lines, a first dummy word line, a second dummy word line, a plurality of bit lines across the plurality of word lines, the first dummy word line, and the second dummy word line, a plurality of memory cells each having a first capacitor and a first MOSFET, a source and a drain of the first MOSFET being coupled between one of the plurality of bit lines and a storage node of the first capacitor, and a gate of the first MOSFET being coupled to one of the plurality of word lines, and a plurality of dummy memory cells each having a second capacitor, a second MOSFET, and a third MOSFET, a source and a drain of the second MOSFET being coupled between one of the plurality of bit lines and a storage node of the second capacitor, a gate of the second MOSFET being coupled to the first dummy word line, a source and a drain of the third MOSFET being coupled between the storage node of the second capacitor and a reference voltage, and a gate of the third MOSFET being coupled to the second dummy word line; a plurality of sense amplifiers each provided corresponding to one of the plurality of bit lines, sensing a difference between a signal read out from a selected memory cell and a signal read out from one of the plurality of dummy memory cells, and amplifying the signal read out from the selected memory cells to a first voltage or a second voltage; and a precharge circuit supplying the first voltage to the plurality of bit lines, wherein the reference voltage is between the first voltage and the second voltage.