Patent ID: 8040118

Claim:
A low-dropout (LDO) voltage regulator comprising: an error amplifier which compares a reference voltage with a feedback voltage of an output voltage and outputs an error signal based on the result of the comparison, the error amplifier being biased by an input voltage; a first MOS transistor having a gate electrically connected to the error signal, a source electrically connected to the input voltage and a drain electrically connected to the output voltage; a voltage divider which transmits a predetermined part of the output voltage to the error amplifier as feedback voltage; and a level limiter which limits a level of the output voltage from changing beyond and below an offset voltage when a level of a load current changes, wherein the level limiter comprises: a decrease limiter which limits the output voltage from decreasing below a low point of the offset voltage when the load current increases; and an increase limiter which limits the output voltage from increasing beyond a high point of the offset voltage when the load current decreases.