Patent ID: 6878580

Claim:
A method for manufacturing a semiconductor device comprising: (a) forming a gate dielectric layer on a semiconductor substrate; (b) forming a silicon seed layer on the gate dielectric layer; (c) forming a poly-SiGe layer having a Ge density gradient, wherein the Ge density gradient is created by initially flowing Si source gas and Ge source gas on the seed layer at substantially the same time and then decreasing the amount of the Ge source gas; (d) forming a gate whose bottom is narrower than its top, wherein the gate includes sides negatively sloping from the bottom of the gate to the top of the gate; (e) performing a thermal process on a resultant structure on which the rate is formed to make the germanium density uniform throughout the entire gate; and (f) forming a source/drain region on the semiconductor device at both sides of the gate by implanting impurities on the resultant structure on which the gate is formed after performing the thermal process.