Patent ID: 7209066

Claim:
A circuit, comprising: a multiplexer adapted to receive a plurality of analog signals and an input select signal, the multiplexer operable, in response to the input select signal, to output one of the received analog signals; an analog signal processing circuit coupled to receive the analog signal output from the multiplexer and further coupled to receive a process command signal representative of one or more analog signal processing parameters, the analog signal processing circuit operable, in response to the process command signal, to process the analog signal using the one or more analog signal processing parameters and supply a processed analog signal; a queued analog to digital converter (QADC) coupled to receive the processed analog signal and a conversion trigger signal, the QADC operable, upon receipt of the conversion trigger signal, to convert the processed analog signal to digital data representative thereof; and a sequence control circuit operable to supply the input select signal, and the process command signal, and is further operable to supply the conversion trigger signal a predetermined settling time period after supplying the process command signal.