Patent ID: 8549258

Claim:
A configurable processing apparatus, comprising: a plurality of single data single instruction processing units, each processing unit having at least a stall-output signal generating circuit to output at least a stall-output signal, wherein the stall-output signal indicates that an unexpected stall occurred in the processing unit, the processing unit further receives at least a stall-in signal, and the stall-in signal is used to control whether the processing unit is to be stalled for at least one instruction until an unexpected stall has ended; and at least an instruction synchronization control circuit, and at least a configuration memory, the instruction synchronization control circuit receiving the stall-output signals, and generating the stall-in signals in response to a first content comprising a group tag which records a group number to indicate simultaneous stalling for all processing units in a same group and a shared instruction flag which records whether a processing unit shares an instruction with the same group, stored in the configuration memory and the stall-output signals of the processing units.