Patent ID: 8508268

Claim:
A PLL circuit comprising: a voltage controlled oscillator configured to output a high frequency signal; an injection locked frequency divider configured to frequency-divide the output high frequency signal; a frequency divider configured to frequency-divide the frequency-divided signal into a frequency of a reference signal; a phase frequency detector configured to compare the frequency-divided signal from the frequency divider with the reference signal and configured to output a phase difference and a frequency difference; a charge pump configured to convert the output phase difference and the frequency difference into an electric current; a loop filter configured to generate a control voltage for the voltage controlled oscillator in accordance with the thus-converted electric current and configured to apply the generated control voltage to the voltage controlled oscillator; and a calibration circuit configured to control an oscillation band which determines an oscillation frequency of the voltage controlled oscillator and configured to control a control parameter for activating the injection locked frequency divider in a determined operating range, wherein the calibration circuit is configured to adjust the oscillation band of the voltage controlled oscillator in accordance with a frequency-divided signal of the adjusted injection locked frequency divider after adjustment of the control parameter of the injection locked frequency divider.