Patent ID: 7129101

Claim:
A method of testing a manufacturing process of an integrated circuit test vehicle comprising the steps of: designing said integrated circuit test vehicle, said integrated circuit test vehicle comprising: a plurality of unit delay cells wherein each said unit delay cell comprises a unit cell input, a unit cell output, a library driving cell, and an interconnect module wherein said unit cell input is connected to said library driving cell, said library driving cell is further connected to said interconnect module, said interconnect module is further connected to said unit cell output, said plurality of unit delay cells are connected in series to each other from said unit delay cell output to said unit delay cell input creating a chain of said unit delay cells; an input signal trace that is connected to the lead unit delay cell unit cell input of said chain of said unit delay cells; and an output signal trace that is connected to the last unit delay cell unit cell output of said chain of said unit delay cells; manufacturing said integrated circuit test vehicle using said manufacturing process; applying a test signal to said input signal trace of said integrated circuit test vehicle; reading a result signal from said output signal trace of said integrated circuit test vehicle; comparing said result signal to a predetermined reference signal; and concluding that said manufacturing process is defective if said result signal does not match said predetermined reference signal.