Patent ID: 6918049

Claim:
A clock synthesizer operable to produce a non-aligned clock output signal and a realigned output clock signal based on an non-aligned output clock, wherein the realigned output clock signal is a phase shifted version of the non-aligned output clock, comprising: an accumulator associated with a selected accumulator overflow value and coupled to the input clock, comprising: an accumulator bus operable to carry an accumulator bus value, wherein the non-aligned clock output signal is derived from the accumulator bus value; an accumulator adder operable to produce an accumulator adder modulo sum of a value on a first adder input port and a value on a second adder input port, wherein the value on the first adder input is a selected frequency control value and the value on the second adder input port is the accumulator bus value; and an accumulator register coupled to the accumulator adder, wherein the accumulator register is operable to store a register value based on the modulo sum and place a selected portion of the register value on the accumulator bus to store as the accumulator bus value; an offset adder bus coupled to the accumulator bus, wherein the offset adder bus is operable to carry an offset adder bus value derived from the accumulator bus value; and an offset adder operable to produce an offset adder modulo sum of a value on a first offset adder input port and a value on a second offset adder input port, wherein the value on the first adder input is a selected phase offset value and the value on the second adder input port is the offset adder bus value, wherein the realigned output clock signal is derived from the offset adder modulo sum and wherein a phase offset between the realigned output clock signal and the input clock is derived from the selected phase offset value.