Patent ID: 7166250

Claim:
A method of forming a metal interconnect comprising: (a) providing a substrate in which a conductive layer has been formed; (b) forming sequentially a stack of layers on said substrate including a passivation layer at the bottom of said stack followed by a dielectric layer and a etch stop or cap layer in which one or more layers in said stack is comprised of a poly(arylene ether) comprising the structure: wherein n=5 to 10000 and monovalent Ar 1 and divalent Ar 2 are heteroaromatic groups that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements and the ether linkage is attached directly to a heteroaromatic ring or to an aromatic ring that is fused to a heteroaromatic ring; (c) forming an opening in said stack of layers, said opening is aligned above said conductive layer; and (d) depositing a barrier metal layer and a metal layer within said opening followed by planarizing said metal to be coplanar with the top of said stack.