Patent ID: 7290128

Claim:
A method for fault resilient boot of complex multi-rail processors in an information handling system, said method comprising the steps of: clearing processor DC-to-DC regulator failure status for all processors of an information handling system upon initial power-up; setting FRB_ENABLE when asserting PS_ON#, wherein FRB_ENABLE remains set until PS_ON# is de-asserted; setting a processor DC-to-DC regulator status as failed when an associated processor DC-to-DC regulator has failed; checking all processor DC-to-DC regulator status to determine if no processor DC-to-DC regulator has failed, then coupling all processor Powergood signals directly to SYSTEM_POWERGOOD generation logic; otherwise if at least one processor DC-to-DC regulator status is set as a failure, then masking the associated processor Powergood signal by forcing it indicate good status before coupling to the SYSTEM_POWERGOOD generation logic; and rebooting the information handling system with the remaining processors having good DC-to-DC regulators and disabling the processor having the failed DC-to-DC regulator.