Patent ID: 7001786

Claim:
A wafer-level burn-in method for performing a burn-in with respect to a semiconductor wafer provided with a plurality of semiconductor integrated circuit chips each having a transistor, an electrode for product connected electrically to the transistor and having a metal bump provided on a surface thereof, and an electrode pad for test connected electrically to the transistor to be used specifically for a wafer-level burn-in, the method comprising the steps of: performing a probe test on the plurality of semiconductor integrated circuit chips by using the electrode pad for product; performing an insulating treatment with respect to the electrode pad for test of the faulty one of the plurality of semiconductor integrated circuit chips determined to be faulty in the step of performing the probe test; and after the step of performing the insulating treatment, performing a wafer-level burn-in using the electrode pad for test with respect to the good one of the plurality of semiconductor integrated circuit chips determined to be good in the step of performing the probe test.