Patent ID: 6980242

Claim:
A solid-state image sensing device comprising: a) a photoelectric converter portion having a plurality of photoelectric converters arranged in two dimensions on a semiconductor substrate; b) a pixel portion comprising a vertical transfer portion for vertically transferring signal charges of said photoelectric converter portion at separate timing of first transfer and second transfer; and a solid-state image sensor provided by one of c) a solid-state image sensor comprising: c1) a dummy portion located adjacent to said pixel portion in a photo-shielded state and having photoelectric converters that are similar to those in said photoelectric converter portion; c2) a first charge memory portion for storing charges of odd-numbered pixels vertically transferred from said pixel portion at the time of first transfer; and c3) a second charge memory portion for storing charges of even-numbered pixels vertically transferred from said pixel portion at the time of second transfer, and c′) another solid-state image sensor comprising: c′1) a dummy portion located adjacent to said pixel portion in a photo-shielded state and having photoelectric converters that are similar to those in said photoelectric converter portion; c′2) a first charge memory portion for storing charges of even-numbered pixels vertically transferred from said pixel portion at the time of first transfer; and c′3) a second charge memory portion for storing charges of odd-numbered pixels vertically transferred from said pixel portion at the time of second transfer; and d) controlling means for supplying vertical transfer pulses for vertically transferring charges to each of said dummy portion, said pixel portion, said first charge memory portion, and said second charge memory portion of said solid-state image sensing device, wherein said controlling means, after charges in said first charge memory portion and second charge memory portion have been transferred, temporarily stops generation of vertical transfer pulses supplied to said first and second charge memory portions, whereupon said controlling means generates vertical transfer pulses additionally to allow undesired charges corresponding to the pixels of said dummy portion to be time-compressed and transferred at high speed to gates at the starting end of said first charge memory portion generates an instructing control signal to allow the undesired charges stored in the gates at the starting end to be abandoned when the charges are delivered.