Patent ID: 7330914

Claim:
A DMA controller that accesses a transfer source and a transfer destination of a DMA transfer via a bus, chaining a plurality of data segments in the transfer source according to an instruction by an external initiator, and performing burst-transfer to the transfer destination, comprising: a bus read section that reads the data segments of the transfer source as a first data; a buffer for burst-transfer that stores the data in the bus width units; a boundary data buffer that stores the boundary data and the transfer destination address offset of the next data segment when a boundary data, that is a remaining data after dividing in the bus width units and is data less than the bus width, is generated; an accumulator that calculates a shift amount of said first data based on a transfer source address offset acquired by an instruction of said initiator and a transfer destination address offset stored in said boundary data buffer; a data shift section that shifts said first data according to said shift amount, merges the boundary data generated in the previous data segment and said shifted first data to generate a second data, and outputs said boundary data and the transfer destination address offset of the next data segment to said boundary data buffer and outputs the data before said boundary data out of said second data to said buffer for burst-transfer when the boundary data is generated in said second data and the next data segment is chained; and a bus write section that burst-transfers the data stored in said buffer for burst-transfer to the transfer destination.