Patent ID: 7593430

Claim:
In a communication system conveying data frames of differing signal hierarchies, an apparatus for generating virtual clock signals for said differing signal hierarchies, comprising: an elastic storage unit comprising: a buffer for receiving data frames of a first signal hierarchy, receiving an input clock signal associated with said data frames of said first signal hierarchy, receiving a clock enable signal, and converting said data frames of said first signal hierarchy to data frames of a second signal hierarchy using a virtual clock signal, wherein said virtual clock signal is generated using a combination of said input clock signal and said clock enable signal; a write counter coupled to said buffer for determining a write count indicative of a number of data frames entering said buffer; and a read counter coupled to said buffer for determining a read count indicative of a number of data frames leaving said buffer; and a phase-locked loop coupled to said elastic storage unit, said phase-locked loop for: generating said clock enable signal; and providing said clock enable signal to said elastic storage unit.