Patent ID: 8518723

Claim:
A method of fabricating a semiconductor integrated circuit device, comprising: providing a semiconductor substrate; sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate; forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction; forming first hard mask patterns by etching the hard mask layer using the first etch masks; forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction; forming second hard mask patterns by etching the first hard mask patterns using the second etch masks; forming spacers on sidewalls of the second hard mask patterns; and patterning the etching target layer using the second hard mask patterns having the spacers.