Patent ID: 7724225

Claim:
A display panel for a liquid crystal display, comprising: a timing controller, receiving a LVDS/TMDS/DVI differential signal, to generate a plurality of TTL signals and a sync signal; and a plurality of source drivers, each comprising at least one bus directly connected to the timing controller to receive the corresponding TTL signal; wherein: the timing controller comprises a clock line, coupled to the source drivers for a transmission of the sync signal; and the TTL signals, sequentially transmitted in the bus, conform to the transistor-to-transistor logic standard; wherein each bus comprises three transmission lines which transmit a first TTL signal, a second TTL signal or a third TTL signal respectively; wherein the frequency of the first, second and third TTL signals is determined by the equation: frequency=(the clock of the timing controller×the number of bits of a gray level)/(a number of the source driver×2).