Patent ID: 8239697

Claim:
A performance state control system comprising: a processor including a plurality of pre-defined power states and a plurality of performance states, wherein the processor is operable to switch between the plurality of performance states in response to a determination made by a performance state determination algorithm; a voltage regulator that is coupled to the processor by a bus, wherein the voltage regulator is operable to provides a regulated voltage to the processor in response to a signal from the processor; and a performance state control circuit that is coupled to the bus and operable to: receive the signal from the processor; determine that the processor is in a first power state of the plurality of pre-defined power states using the signal; determines a time that the processor is in the first power state; and instructs the processor to execute the performance state determination algorithm in response to the time exceeds a pre-determined threshold value, wherein the performance state determination algorithm is not executed if the time does not exceed the pre-determined threshold value.