Patent ID: 7251761

Claim:
An assembly for an LSI test which supplies a test signal output from an LSI tester to a target LSI to be tested and outputs, to the LSI tester, a test result signal generated by processing of the target LSI performed in accordance with the test signal, the assembly comprising: a peripheral circuit coupled to the target LSI and allowing the target LSI to operate in the same manner as in actual operation; a first clock generator for generating a first clock as a reference clock for the actual operation in the target LSI; a second clock generator for generating a second clock to allow the target LSI to obtain the test signal from the LSI tester; a third clock generator for generating a third clock to allow the target LSI to output a test result signal, wherein the first clock, the second clock, and the third clock are asynchronous with each other; and a printed circuit board on which the peripheral circuit and the first, second, and third clock generators are mounted.