Patent ID: 7795671

Claim:
A semiconductor device comprising: a semiconductor substrate; a source region and a drain region provided in said substrate; wherein said source region and said drain region are laterally spaced from each other; a drift region in said substrate between said source region and said drain region; wherein said drift region includes a structure having at least first and second trench MOS capacitors extending from proximate said source region to proximate said drain region; and further includes a vertical stack having at least three regions, one on top of the other, including at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of said first conductivity type, wherein each of said first, second, and third regions extend from proximate said source region to proximate said drain region and extends between said first and second trench MOS capacitors; wherein, when said device is in an on state, current flows between said source and drain regions through said second region of said second conductivity type; and, when said device is in an off/blocking state, said second conductivity region is depleted by four separate electric fields from said first and third regions of said stack and from said first and second trench MOS capacitors.