Patent ID: 7763523

Claim:
A method for forming a device isolation structure of a semiconductor device, comprising the steps of: forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill the trench, wherein the flowable insulation layer is formed as a PSZ (polysilazane) layer, first annealing the PSZ layer in an atmosphere containing H 2 O (water vapor) at least three times increasing the annealing temperature each time, so that the PSZ layer is converted into a SiO 2 layer; second annealing the SiO 2 layer as dry annealing, so that the SiO 2 layer is densified; removing the second annealed SiO 2 layer until the hard mask pattern is exposed; removing the exposed hard mask pattern; and densifying the flowable insulation layer.