Patent ID: 7577231

Claim:
A clock multiplier structure, comprising: a clock signal generator for generating an output clock signal having a plurality of first oscillation cycles, said clock signal generator including: a ring oscillator for generating an oscillator signal having a first frequency and a plurality of second oscillation cycles; a rollover counter in electrical communication with said ring oscillator for counting ones of said plurality of second oscillation cycles of said ring oscillator from a seed value to a terminal value and outputting a pulse each time said rollover counter reaches said first terminal value; a saturation counter in electrical communication with said clock signal generator for counting ones of said plurality of second oscillation cycles from a multiplier start value to a saturation value and outputting a binary signal indicating whether or not said saturation counter has reached said saturation value, said saturation counter for receiving an input clock signal and configured to reset as a function of said input clock signal; and a seed value generator in electrical communication with said saturation counter, said seed value generator for generating said seed value when said binary signal indicates that said saturation has not reached said saturation value, said seed value generator in electrical communication with said rollover counter for providing said seed value to said rollover generator.