Patent ID: 8188534

Claim:
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix; and a gate line, a word line, a bit line to be selected based on an address signal and to supply a writing voltage to the memory cell to be written, and a source line to which a power supply potential is supplied, wherein each of said plurality of memory cells includes: a storage transistor having a first impurity region and a second impurity diffusion region opposed to each other through a first channel formation region, a first gate electrode formed above said first channel formation region, and a charge accumulation node formed below said first channel formation region; and an access transistor connected to said storage transistor in series, having said first impurity diffusion region, a third impurity diffusion region opposed to said first impurity diffusion region through a second channel formation region, and a second gate electrode formed above said second channel formation region, said second impurity diffusion region is connected to said source line, said third impurity diffusion region is connected to said bit line, said first gate electrode is connected to said gate line, and said second gate electrode is connected to said word line.