Patent ID: 8797082

Claim:
An integrated circuit comprising: a plurality of physical regions comprising circuitry; and one or more characterizers within one or more of the physical regions, wherein respective circuitry within a characterizer of the one or more characterizers is configured to: receive a first clock signal; generate a second clock signal with a frequency less than a frequency of the first clock signal; and generate a plurality of other clock signals by combining each of the first clock signal and the second clock signal in sequential logic; wherein the sequential logic comprises a divide-by-N counter and a plurality of flip-flops including a first flip-flop and a second flip-flop, each configured to receive the first clock signal as a clock input; wherein in response to detecting an error measurement mode for determining skew in the sequential logic, the respective circuitry is further configured to: select a same polarity of the first clock signal as the clock input of each of the divide-by-N counter, the first flip-flop, and the second flip-flop; and select a test clock signal to be received as the first clock signal, wherein the test clock signal is generated by external test equipment wherein in response to detecting a mode different from the error measurement mode, the respective circuitry is configured to select an opposite polarity of the first clock signal as the clock input of the first flip-flop.