Patent ID: 7734985

Claim:
A memory device comprising: a split bank pair of memory banks including a first memory bank and a second memory bank, wherein the first memory bank and the second memory bank can be configured as either a single logical memory bank or as two separate memory banks; column address generation logic coupled to the split bank pair of memory banks; and a register bit to indicate whether the memory device is in an error check mode or a non-error check mode, wherein when the memory device is in the error check mode, a first row of the first memory bank to store data, a second row of the second memory bank to store error check bits corresponding to the data, and in response to a first column address and a row address being sent from the memory controller to the memory device: the memory device to access the data with the row address and the first column address, the column address generation logic to generate a different column address based on the first column address, and the memory device to activate a fraction of the second row with the row address and the different column address, the activating the fraction of the second row to access the error check bits.