Patent ID: 7501670

Claim:
A circuit, comprising: input drain, source and gate nodes; a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state; an enhancement mode FET having a source, drain and gate, wherein the source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET; and wherein the drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node, and wherein the group III nitride depletion mode FET comprises: a substrate; a first active layer disposed over the substrate; a second active layer disposed on the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer; a flash layer disposed on the second active layer; and a source, gate and drain contact disposed on the flash layer.