Patent ID: 7962814

Claim:
A process of operating an integrated circuit comprising: A. placing target system test circuitry, which can operate in one of a test mode of passing test signals through the target system test circuitry and an advanced mode of preventing the passing of test signals through the target system test circuitry, and which target system test circuitry includes state machine circuitry, in the test mode of operation, in the test mode of operation the state machine circuitry can be stepped through at least states of Capture-DR, Shift-DR, and Update-DR; B. stepping the state machine circuitry, in the test mode, through a special sequence of the states that includes the Capture-DR state and Update-DR state and does not include the Shift-DR state; C. detecting the special sequence of the states in the target system test circuitry; and D. moving the target system test circuitry out of the test mode of operation and into the advanced mode of operation in response to the detecting.