Patent ID: 8151059

Claim:
A semiconductor chip, comprising: a first core cache cluster having a first plurality of processor cores, a first portion of a shared cache associated with said first plurality of processor cores, and, a first scalability agent associated with said first portion of said shared cache; a second core cache cluster having a second plurality of different processor cores, a second portion of said shared cache associated with said second plurality of processor cores, and, a second scalability agent associated with said second portion of said shared cache; interconnect circuitry interconnecting said first and second core cache clusters; said first and second portions of said shared cache assigned different respective address spaces of said shared cache and where no portion of said shared cache on said semiconductor chip has overlapping address space with another portion of said shared cache on said semiconductor chip; and, said first and second scalability agents each having respective conflict detection, analysis and resolution logic to detect, analyze and resolve respective conflicts of caching transactions directed to its respective address space.