Patent ID: 7924066

Claim:
An output buffer, comprising: an inverter connected to provide an output in response to receiving a buffer input; a pull up output transistor having a drain connected to provide a buffer output; a first resistor connected between the inverter output and the gate of the pull up transistor; a first feedback capacitor connected between the gate of the pull up transistor and the buffer output; a pull down output transistor having a drain connected to the buffer output; a second resistor connected between the inverter output and the gate of the pull up transistor; a second feedback capacitor connected between the gate of the pull down transistor and the buffer output; a third transistor having a source connectable to a power supply, a gate connected to the input signal, and a drain connected to the gate of the pull up transistor, and a fourth transistor having a source connectable to a ground, a gate connected to the input signal, and a drain connected to the gate of the pull down transistor, wherein current is driven through the first capacitor to slow the rise of the output voltage in response to the buffer input going high and current is driven through the second capacitor to slow the fall of the output voltage in response to the buffer input going low.