Patent ID: 8760577

Claim:
A clock data recovery circuit comprising: a receiver circuit configured to receive a serial data including a predetermined pattern and to sample said serial data in synchronization with a clock signal to generate a sampled data; a PLL circuit configured to perform clock data recovery based on said sampled data to generate said clock signal; and a false lock detection circuit configured to detect false lock of said PLL circuit by detecting that a false lock pattern is included in said sampled data, wherein said false lock pattern is a pattern obtained by said receiver circuit sampling said predetermined pattern when said false lock of said PLL circuit occurs, wherein said serial data is a video data signal supplied to a display driver for a display device, wherein said video data signal comprises: a video data corresponding to a video image displayed on said display device; and a control data for controlling processing of said video data in said display driver, and wherein said predetermined pattern is contained in said control data.