Patent ID: 8038864

Claim:
A method of fabricating a semiconductor device having a plating process of filling a plurality of recesses provided to an insulating film formed on a substrate with an electro-conductive material, comprising the steps of: determining a first surface area S 1 of over an entire surface of said substrate which includes the area of side walls of said plurality of recesses over the entire surface of said substrate; determining a second surface area S 2 of over an entire surface of said substrate which excludes said area of side walls of said plurality of recesses; determining a ratio of surface area Sr=S 1 /S 2 ; and performing the plating with a first current density when fine recesses not larger than a predetermined width, out of all of said plurality of recesses, are filled with said electro-conductive material, said first current density being obtained by correcting a predetermined first reference current density based on the determined ratio of surface area Sr=S 1 /S 2 .