Patent ID: 7216326

Claim:
A method of determining an optimized resource interconnection pattern within an essentially semiconductor digital device, said essentially semiconductor digital device comprising resources and being represented by a representation describing the functionality of said digital device, said representation comprising transfers, said transfers being defined by their source resource and their destination resource, said interconnection pattern includes at least one segmented bus temporarily facilitating at least two transfers with partially overlapping scheduling intervals, said at least one segmented bus comprising a switch, said switch defining segments within said at least one segmented bus, said method comprising: inputting a representation of the functionality of said essentially digital device, including the number and type of said resources and at least partial scheduling of said transfers; performing a first determination of the minimal number of parallel communicating resources and adding virtual switches to essentially all bus segments, said first determination defining a default segmentation; and performing a second determination of abstract or relative positions of said resources within said essentially digital device, and at least fixing the amount of switches and the place of said switches, by selectively removing virtual switches, said second determination resulting in a refinement of said default segmentation.