Patent ID: 7671575

Claim:
A circuit for regulating an output voltage provided to a load, comprising: an error amplifier for outputting an error signal based on a comparison of an error in a predetermined equivalence between a reference voltage and the output voltage provided to the load; a summing point for generating a summed error signal, wherein the summed error signal includes a summing of the error signal with an information signal regarding a current flowing through the load, wherein the summed error signal is a representation of both the error in the output voltage and an amount of current that is flowing through the load; a latch that enables the routing of a current to drive the load, wherein the operation of the latch is controlled by the summed error signal in response to both the amount of current that is flowing through the load and an error in the output voltage; a current source that is arranged to provide the information signal; and an analog multiplier, wherein the analog multiplier is arranged to modify the magnitude of the summed error signal.