Patent ID: 8850133

Claim:
A system, comprising: a processor configured to: cause a first portion of data to be read using a first read block size; determine a first throughput associated with the first read block size; cause a second portion of data that is different from the first portion of data to be read using a second read block size that is different from the first read block size, wherein the second portion of data is read using the second read block size beginning at a first offset that is aligned to a power of 2 from a starting position of the data; and select, based at least in part on a comparison of the first throughput and a second throughput associated with the second read block size, one of the first and second read block sizes to use to complete the data transfer operation; and a memory coupled to the processor and configured to provide the processor with instructions; wherein determining a first throughput includes reading a third portion of data using the first read block size and calculating an average; and wherein the processor is further configured to read a sufficient number of blocks using the first read block size such that an amount of data read using the first read block size is aligned to a power of 2.