Patent ID: 7193657

Claim:
A video signal processing apparatus comprising: a plurality of line memories to which in sequence video signal data inputted is written on a line-by-line basis; a timing controller for controlling a timing to write the video signal data to the plurality of line memories and a timing to read the video signal data from the plurality of line memories; a computation output portion for computing the video signal data read from the plurality of line memories and outputting video signal data differing in resolution which is determined by a pixel count in the horizontal direction and a line count in the vertical direction; a reference pixel count decision unit which decides a reference pixel count in the horizontal direction of the video signal data obtained from the computation output portion, by letting a difference be a specified period of time which is determined depending on a conversion rate of the resolution of the video signal data, wherein the difference is a difference between an elapsed period of time for a specified number of lines of the video signal data inputted and an elapsed period of time for a line count corresponding to the specified number of lines of the video signal data obtained from the computation output portion; a counting unit which counts the specified period of time; and a pixel count variation unit which varies from the reference pixel count the pixel count in the horizontal direction of the video signal data obtained from the computation output portion if the count of the counting unit is equal to or smaller than the specified period of time.