Patent ID: 8692133

Claim:
A semiconductor package, comprising: an insulation substrate having a top surface and a bottom surface; a circuit pattern on the top surface of the insulation substrate, the circuit pattern including: a first signal conductive pattern; and first and second ground conductive patterns spaced apart from each other; a first insulation film partially covering the first signal conductive pattern and the first and second ground conductive patterns, and exposing a portion of the first signal conductive pattern, a first portion of the first ground conductive pattern, and a portion of the second ground conductive pattern; a first conductive member on the first signal conductive pattern and the first and second ground conductive patterns; and a semiconductor chip on the first conductive member; wherein the first conductive member covers a portion of the first insulation film between the first portion of the first ground conductive pattern and the portion of the second ground conductive pattern, wherein the first conductive member contacts the first portion of the first ground conductive pattern and the portion of the second ground conductive pattern to electrically connect the first and second ground conductive patterns, and wherein the semiconductor chip is electrically connected to the first signal conductive pattern and the first ground conductive pattern.