Patent ID: 8519880

Claim:
An AD converter comprising: a VT converter circuit part configured to input an analog input voltage and a sampling clock (CK), convert the analog input voltage to a corresponding delay time, and output time domain data; a ring oscillator circuit part of a plurality of N stages configured to input the time domain data; an error propagation circuit part being inserted between a ring oscillator circuit part of a previous stage and a ring oscillator circuit part of a next stage, the error propagation circuit part taking out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagating the delay information to the ring oscillator circuit part of a subsequent stage; a counter circuit part configured to measure a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage; an output signal generator part configured to generate an output signal from an output counted value of each counter circuit part; and a reset part configured to reset each error propagation circuit part and each counter circuit part with a sampling clock (CK).