Patent ID: 8102001

Claim:
A semiconductor device for electrostatic discharge (ESD) protection, comprising: a semiconductor substrate; an n-type well formed in the substrate; a p-type metal-oxide-semiconductor (PMOS) transistor formed in the n-type well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region; an n-type region formed in the n-type well electrically connected to the first diffused region of the PMOS transistor, wherein the n-type region includes a plurality of sub-regions formed in the n-type well, the plurality of sub-regions being separated apart from each other by the first diffused region of the PMOS transistor; and a p-type region formed in the substrate outside of the n-type well, and electrically connected to the second diffused region of the PMOS transistor, wherein the gate of the PMOS transistor is kept at a reference voltage level to keep the PMOS transistor at an on state before an ESD event occurs.