Patent ID: 7277339

Claim:
A semiconductor storage device comprising: a precharge circuit configured to precharge a bit line connected to a selected memory cell for a read operation, the precharge circuit including a first MOS transistor of a first conductivity type which has a gate connected to the bit line, a second MOS transistor of a second conductivity type which has a gate connected to the bit line, the second MOS transistor having a current path one end of which is connected to one end of a current path in the first MOS transistor, a third MOS transistor of the first conductivity type which has a current path one end of which is connected to the other end of the current path in the first MOS transistor, the other end of the current path in the third MOS transistor being connected to a power supply, and a fourth MOS transistor of the second conductivity type which has a gate connected to a junction between the current paths in the first and second MOS transistors and which controls a charge level of the bit line; a discharge circuit configured to discharge the bit line using a current flowing through the selected memory cell; and a sense amplifier configured to sense a voltage across the bit line.