Patent ID: 6987322

Claim:
A semiconductor device fabricated using a multilayer hard mask, comprising: a substrate with a device region and an alignment region having a first opening therein to serve as an alignment mark; a dielectric layer overlying the substrate and filled in the first opening, wherein the dielectric layer on the device region has a plurality of contact holes therein; a first polysilicon layer, a silicon oxide layer, and a second polysilicon layer successively disposed on the dielectric layer to serve as the multi-layer hard mask, wherein the multi-layer hard mask on the device region has a plurality of holes therein to expose the contact holes and the multi-layer hard mask over the first opening on the alignment region has a second opening therein to expose the first polysilicon layer; a barrier layer conformably disposed on the multi-layer hard mask and the inner surfaces of the contact holes and the second opening; and a metal layer disposed on the barrier layer and filling the contact holes and the second opening.