Patent ID: 7383527

Claim:
A semiconductor integrated circuit manufacturing method, including a netlist, said method comprising: setting a permissible range of values relating to an element, the setting being based on categorizing previously extracted floor plan data and searching the categorized data; creating a floor plan in accordance with the netlist, the floor plan satisfying the permissible range of values; placing a plurality of elements in a configuration on a basis of the floor plan; extracting routing constraints for the configuration to realize a permissible range of values for a plurality of parasitic elements; and routing a pattern in accordance with the extracted routing constraints, wherein setting the permissible range of values comprises: executing a provisional floor plan from circuit connection information; inserting only parasitic elements extracted from said provisional floor plan into relevant nodes of a circuit; deriving a range of parasitic element values satisfying characteristics from results of a circuit simulation in which parasitic element values are increased or decreased; and providing a derived range of parasitic element values as said permissible range of values for the plurality of parasitic elements.