Patent ID: 8364735

Claim:
A test method of an integrated circuit with a random-number generation circuit, comprising: optimizing including testing random numbers output from a random-number generation circuit incorporated in an integrated circuit, while adjusting a control parameter for the random-number generation circuit, and optimizing the control parameter; wherein the optimizing further includes: adjusting the control parameter for the random-number generation circuit until a result of a first test based on NIST SP800-22 becomes OK; and optimizing the control parameter by obtaining a predetermined number of random numbers generated immediately after the power-on reset after each power-on reset from the random-number generation circuit, for which the adjusted control parameter is set, by repeating the power-on reset with respect to the integrated circuit for a preset number of times, executing at least one of a second test based on matched number of bits in the obtained predetermined number of random numbers and a third test based on number of 0 or 1 appearing at a same bit position in the predetermined number of random numbers, and adjusting the control parameter for the random-number generation circuit until at least one executed test result becomes OK.