Patent ID: 8493260

Claim:
A successive approximation register (SAR) analog-to-digital converter (ADC) for converting an analog input into an N-bit digital output in a conversion phase composed of a plurality of conversion sub-phases, comprising: three comparators; three capacitor arrays, each having two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators, wherein the SAR logic is further used for controlling the three capacitor arrays to sample the analog input before the conversion phase, wherein the analog input includes a differential positive input and a differential negative input, the SAR logic controls the two capacitor sub-arrays of each capacitor array to sample the differential positive input and the differential negative input respectively, wherein, in each conversion sub-phase, the set of adjusted reference levels coupled to the two capacitors of the three capacitor sub-arrays for sampling the differential positive input is: (−1,−1), (−1,−1), and (−1,−1) if the set of data outputted from the three comparators in a preceding conversion sub-phase is (0,0,0); (0,−1), (0,−1), and (0,−1) if the set of data outputted from the three comparators in a preceding conversion sub-phase is (0,0,1)/(1,0,0); (0,1), (0,1), and (0,1) if the set of data outputted from the three comparators in a preceding conversion sub-phase is (0,1,1)/(1,1,0); and (1,1), (1,1), and (1,1) if the set of data outputted from the three comparators in a preceding conversion sub-phase is (1,1,1), wherein, the “1” represents positive reference level, the “−1” represents negative reference level, and the “0” represents a common mode voltage related to the positive and negative reference level.