Patent ID: 6922716

Claim:
An apparatus ( 302 ) for performing dynamically scalable single instruction multiple data (SIMD) operations comprising: a first vector arithmetic logic unit ( 402 ) operably coupled to a first data vector (VRA) from a first input data bus, a second data vector (VRB) from a second vector data bus, and a third data vector (VRC) from a third vector data bus to produce a first vector result (VRD) wherein the first vector functional arithmetic logic unit ( 402 ) performs individual conditional operations on fields of VRA and VRB to produce VRD, and wherein the conditional operations are based on VRC; a second vector arithmetic logic unit ( 401 ) operably coupled to the first data vector (VRA) from the first input data bus, the second data vector (VRB) from the second input data bus, and to the first vector arithmetic logic unit, wherein the individual conditional vector operations in the first vector arithmetic logic unit are conditionally controlled by a vector result from the second vector arithmetic logic unit.