Patent ID: 7486119

Claim:
A delay-locked loop circuit comprising: a variable voltage generator configured to generate a variable bias voltage signal in response to a standby signal, wherein the variable bias voltage signal has differing voltage levels according to operation modes, wherein the operation modes include a standby mode and an active mode; and a delay-locked loop configured to generate an internal clock signal in response to the standby signal and the variable bias voltage signal, wherein the internal clock signal is synchronized with an external clock signal and the variable voltage generator comprises: a reference voltage generating unit configured to generate a reference voltage; and a driving unit configured to generate the variable bias voltage signal in response to the reference voltage and the standby signal, wherein the driving unit comprises: a first current driving transistor that operates in response to the standby signal; and a second current driving transistor that is activated in response to a complementary standby signal, wherein one of the first and the second current driving transistors is smaller than the other, the smaller sized current driving transistor being activated in the standby mode, and the larger sized current driving transistor being activated in the active mode.