Patent ID: 7208991

Claim:
A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed, wherein one or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the plurality of transistors form a first sub-circuit and a second sub-circuit, the first sub-circuit comprising a plurality of P-type transistors connected in parallel with each other, some of the P-type transistors having different effective widths, and the second sub-circuit comprising a corresponding plurality of N-type transistors connected in parallel with each other, some of the N-type transistors having different effective widths, and further comprising an N-type transistor connected in parallel with the plurality of P-type transistors in the first sub-circuit, the N-type transistor discharging voltage across the plurality of P-type transistors in the first sub-circuit during a low portion of the signal, and a P-type transistor connected in parallel with the plurality of N-type transistors in the second sub-circuit, the P-type transistor discharging voltage across the plurality of N-type transistors in the second sub-circuit during a high portion of the signal, and wherein the first sub-circuit and the second sub-circuit are connected in series with each other so that one of the first and second sub-circuits delays the edge followed by the other of the first and second sub-circuits further delaying the edge, and wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented.