Patent ID: 8533649

Claim:
A computer implemented method of reducing leakage power in integrated circuit designs, comprising: receiving a cell-based integrated circuit design having at least a plurality of signal paths with first slack values that comply with timing requirements specified for the circuit design; replacing, by a computer, a plurality of cell instances in the circuit design with pivot variants of the cell instances, a pivot variant of a cell instance being a footprint equivalent variant of the cell instance with highest power efficiency relative to signal delay amongst footprint equivalent variants of the cell instance, the first slack values being converted into second slack values that violate the timing requirements as a result of replacing the plurality of cell instances; for each of the signal paths having the second slack values, replacing one or more cell instances in the signal path with lower signal delay variants of the one or more cell instances until the second slack values are converted into third slack values that comply with the timing requirements; and outputting a revised version of the circuit design having the third slack values.