Patent ID: 7535399

Claim:
An apparatus comprising: a first circuit configured to generate a plurality of digital intermediate signals in response to an analog input signal, said first circuit comprising a plurality of analog-to-digital converter (ADC) stages, each ADC stage configured to generate a respective residual output signal and a respective one of said plurality of digital intermediate signals in response to a respective input signal, a respective set of threshold voltages and a respective set of reference voltages, wherein a first ADC stage receives said analog input signal as the respective input signal, a first set of threshold voltages and a first set of reference voltages and each remaining ADC stage receives the residual output signal from another ADC stage as the respective input signal, a second set of threshold voltages and a second set of reference voltages, wherein the first set of threshold voltages and the first set of reference voltages are shifted with respect to the second set of threshold voltages and the second set of reference voltages by a first predetermined voltage level and a second predetermined voltage level, respectively; and a second circuit configured to generate a digital output signal in response to the plurality of digital intermediate signals.