Patent ID: 7420400

Claim:
A method of calibrating a duty cycle measurement (DCM) circuit for determining the duty cycle of a digital signal, the method comprising: supplying the digital signal to the duty cycle measurement (DCM) circuit, the DCM circuit being situated on an integrated circuit (IC) that includes a capacitor; charging, by charger circuitry in the DCM circuit, the capacitor to a voltage value that depends on the duty cycle of the digital signal; varying the duty cycle of the digital signal to a plurality of different duty cycle values, the digital signal charging the capacitor to a different voltage value for each of the duty cycle values thereof; and storing, in a data store, each voltage value and the corresponding duty cycle value wherein the digital signal includes a plurality of pulses, each pulse including first and second logic states, the charging circuit charging the capacitor up during the first logic states of the pulses, the charging circuit discharging the capacitor during the second logic state of the pulses, the first and second logic states exhibiting respective durations that define the duty cycle of a particular digital signal, thus leaving a voltage value on the capacitor related to the duty cycle of the plurality of pulses.