Patent ID: 7705398

Claim:
A semiconductor device, comprising: a semiconductor substrate having first and second main surfaces and including a first impurity region of a first conductivity type; a second impurity region of a second conductivity type formed in said first main surface of said semiconductor substrate and surrounded by said first impurity region at said first main surface; a third impurity region of the first conductivity type formed in said first main surface and sandwiching said second impurity region with said first impurity region; a fourth impurity region of the second conductivity type selectively formed in said second main surface of said semiconductor substrate and sandwiching said first impurity region with said second impurity region; a fifth impurity region of the first conductivity type having higher impurity concentration than said first impurity region, selectively formed in said second main surface of said semiconductor substrate and sandwiching said first impurity region with said second impurity region; and a control electrode layer formed to be opposite to said second impurity region, sandwiched between said first impurity region and said third impurity region, with an insulating layer interposed; wherein that portion of said second main surface, which is opposite to a portion of said first main surface where said first impurity region is formed, is in the peripheral regions of the semiconductor device, surrounds regions for forming said fourth and fifth impurity regions, formed alternatively on said second main surface, and is a region of a second conductivity type.