Patent ID: 7900204

Claim:
An apparatus comprising: a hardware processor associated with a computer system for processing virtual interrupts in a layered virtualization architecture with one or more intervening virtual machine monitors; recognition logic that recognizes an interrupt request during execution of a virtual machine; window logic that determines whether an interrupt window is open based on an interrupt blocking control bit, an interrupt blocking instruction, and an activity state that blocks interrupts; evaluation logic that determines whether to transfer control of the apparatus to said one or more intervening virtual machine monitors in response to the interrupt request if the interrupt window is open, wherein determining which of said one or more intervening virtual machine monitors to transfer control occurs by following at least one pointer in a chain of pointers from a controlling virtual machine control structure to a child virtual machine control structure until an interrupt control bit is found to be set; and exit logic that transfers control to the intervening virtual machine monitor if said window logic determines that the interrupt window is open and said evaluation logic determines to transfer control.