Patent ID: 8143723

Claim:
A dynamic random access memory device comprising: a semiconductor substrate: a plurality of laminated bit line structures, including a first laminated bit line structure and a second laminated bit line structure, each of the plurality of laminated bit line structures including a conductive pattern and an insulating pattern, plurality of the conductive patterns being formed above the semiconductor substrate, and plurality of the insulating patterns being formed separately and over the conductive patterns respectively; a first insulating film formed between the plurality of the laminated bit line structures; a first contact hole formed in the first insulating film between the first laminated bit line structure and the second laminated bit line structure; a second insulating film formed in contact with the first insulating film and in contact with the upper surface of the first laminated structures; a storage electrode formed between the first laminated bit line structure and the second laminated bit line structure, the storage electrode being connected to the semiconductor substrate; wherein the first contact hole reaches the insulating pattern of the first laminated bit line structure.