Patent ID: 8867293

Claim:
A semiconductor memory device which changes a refresh timing when refreshing a memory core having memory cells, comprising: a temperature detecting unit configured to supply a temperature-dependent signal that assumes a first state when temperature is higher than a threshold and that assumes a second state when the temperature is lower than the threshold; a refresh address generating circuit configured to generate a refresh address in response to a refresh request; and a control circuit configured to elongate the refresh timing upon a passage of a certain time following the supply of the temperature-dependent signal by the temperature detecting unit, wherein the control circuit includes: a counter circuit that starts counting at a point in time at which the temperature-dependent signal changes from the first state to the second state; and a refresh request generating circuit configured to generate the refresh request at a first certain interval before the supply of the temperature-dependent signal, to continue to generate the refresh request at the first certain interval during a period following the supply of the temperature-dependent signal before the counter circuit reaches a certain count value, and to generate the refresh request at a second certain interval different from the first certain interval after the counter circuit reaches the certain count value.