Patent ID: 8580628

Claim:
A method for forming an integrated circuit ( 40 ) with a mis-alignment tolerant electrical contact ( 44 ), comprising: providing a substrate ( 21 ) with a first upper surface ( 211 ), a semiconductor region ( 22 - 1 ) with a contact area ( 221 ) on the first upper surface ( 211 ), a first electrically conductive region ( 26 ) laterally proximate the semiconductor region ( 22 - 1 ) over the first upper surface ( 211 ), and a first dielectric region ( 34 , 34 ′) over the first upper surface ( 211 ) substantially laterally enclosing the first electrical conductor ( 26 ); converting an upper portion ( 264 ) of the first electrical conductor ( 26 ) to a second dielectric region ( 29 ); applying a mask ( 40 ) over the first ( 34 , 34 ′) and second ( 29 ) dielectric regions, the mask ( 40 ) having an opening ( 401 ) extending partly over the contact area ( 221 ) and partly over the second dielectric region ( 29 ); forming under the mask opening ( 401 ) a passage ( 41 ) extending through the first dielectric region ( 34 , 34 ′) to the contact area ( 221 ) and to a part ( 292 ) of the second dielectric region ( 29 ); filling the passage ( 41 ) with a conductor ( 44 ) thereby making electrical connection to the contact area ( 221 ), but wherein the conductor ( 44 ) is electrically insulated from the first electrical conductor ( 26 ) by the second dielectric region ( 29 ); forming dielectric sidewall spacers ( 261 ) on the first conductive region ( 26 ) located between the dielectric region ( 34 ) and the first electrical conductor ( 26 ); and forming a barrier layer ( 27 ) laterally surrounding the first electrical conductor ( 26 ) between the first electrical conductor ( 26 ) and the dielectric sidewall spacers ( 261 ); wherein the barrier layer is an electrical conductor, the method further comprising prior to the step of applying the mask ( 40 ), replacing an upper part ( 271 ) of the barrier layer ( 27 ) with another material ( 382 ), and wherein replacing an upper part ( 271 ) of the barrier layer ( 27 ) with another material ( 382 ) occurs prior to converting an upper portion ( 264 ) of the first electrical conductor ( 26 ), and when the another material ( 382 ) is an electrical conductor, the method further comprises, converting at least some of the another material ( 382 ) to a third dielectric at substantially the same time as converting the upper portion ( 264 ) of the first electrical conductor ( 26 ) to the second dielectric, thereby forming the dielectric region ( 29 ) from a combination of the second and third dielectrics.