Patent ID: 7592215

Claim:
A method of fabricating a semiconductor device comprising: forming a plurality of word line patterns on a semiconductor substrate in a cell array region; forming at least one gate pattern on the semiconductor substrate in a peripheral circuit region; forming word line spacers on the side walls of the word line patterns and gate spacers on the side walls of the at least one gate pattern; forming an interlayer insulating layer on an upper surface of the semiconductor substrate having the word line spacers and the gate spacers; etching the interlayer insulating layer and the word line spacers to form a self-aligned contact hole penetrating a predetermined region between the word line patterns; after forming the self-aligned contact hole, forming a self-aligned insulating layer on the interlayer insulating layer and within the self-aligned contact hole; and etching the self-aligned insulating layer thereby forming a self-aligned contact spacer having a width different from that of the gate spacers on a side wall of the self-aligned contact hole.