Patent ID: 8233330

Claim:
An integrated circuit structure comprising: a static random access memory (SRAM) circuit comprising: a pair of global bit-lines being complementary to each other; a pair of local bit-lines being complementary to each other; a global read/write circuit coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation; a first multiplexer and a second multiplexer, each comprising a first input and a second input, wherein the first input of the first multiplexer and the first input of the second multiplexer are coupled to different ones of the pair of global bit-lines; and a sense amplifier comprising a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer, wherein the sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation.