Patent ID: 6847124

Claim:
A semiconductor device comprising: a substrate; a first conducting layer having an interconnection region that provides for an external electrical contact; an insulating layer interposed between the substrate and the first conducting layer; and a second conducting layer embedded in the insulating layer and made of a softer material than that of the insulating layer, the first conducting layer, the insulating layer, and the second conducting layer being stacked on the substrate, the second conducting layer having an area that at least partially overlaps with the interconnection region in a stacked direction of the first conducting layer, die insulating layer, and the second conducting layer, the area of the second conducting layer overlapping with the interconnection region having at least one notch that extends through die second conducting layer in the stacked direction and separates the second conducting layer in a layer direction of the second conducting layer, a portion of the insulating layer being embedded in the notch.