Patent ID: 7800202

Claim:
A semiconductor device comprising a pair of an n-channel transistor and a p-channel transistor, said n-channel transistor being formed using a first semiconductor layer provided on an SOI substrate and a first gate insulating layer covering at least part of a surface of said first semiconductor layer, said p-channel transistor being formed using a second semiconductor layer provided on said SOI substrate and a second gate insulating layer covering at least part of a surface of said second semiconductor layer; wherein said first semiconductor layer has a first region and a second region for forming a channel of said n-channel transistor and said second semiconductor layer has a third region for forming a channel of said p-channel transistor, a surface of said first region having a (110) plane or a plane within ±10° from the (110) plane, and a surface of said second region having one or a plurality of planes different from the plane within ±10° from the (110) plane and adapted to provide a greater mobility of electrons than the plane within ±10° from the (110) plane, with a surface of said third region having a (110) plane or a plane within ±10° from the (110) plane; and wherein a width and a length of the surface of said first region, a height and a length of the surface of said second region, and a width and a length of the surface of said third region are determined so that the sum of an area of the surface of said first region and an area of the surface of said second region is substantially equal or equivalent to an area of the surface of said third region and, further, operating speeds of said n-channel transistor and said p-channel transistor are substantially equal or equivalent to each other.