Patent ID: 6981083

Claim:
A method of operating a processor, said method comprising: storing in a first set of storage locations in the processor a first hard architected state of a first process currently undergoing execution by the processor, wherein said first hard architected state represents one of multiple states encountered during execution of said first process; storing in a second set of storage locations in the processor a second hard architected state of a second process that is idle, wherein said second hard architected state represents one of multiple states encountered during execution of said second process; storing a shadow copy of the first hard architected state within the processor to a set of shadow resisters, wherein the shadow copy is non-executable by the processor; in response to receiving a process interrupt at the processor, storing the shadow copy of the first hard architected state in a system memory through the use of an Integrated Memory Controller (ICM), thereby bypassing a load/store unit (LSU) in the processor, and loading the second hard architected state from the second set of storage locations into the first set of storage locations; and executing the second process.