Patent ID: 6968489

Claim:
An integrated circuit, comprising logic circuits connected to a plurality of shift register latch scan chains and self-test circuits for testing said logic circuits, said self-test circuits in said integrated circuit comprising: a pseudo-random pattern generator for generating at least one flat pseudo-random patterns to provide to each of the scan chains; A plurality of weighting circuits for receipt of the pseudo-random patterns from the pattern geneator, a different one of the weighting circuits associated with each of the scan chains, each weighting circuit having a selectable weight set to provide flat or weighted pseudo-random patterns to the scan chains independently of one another; a different storage element associated with each of the weighting circuits for receipt and storage of flat and weighted pesudo-random patterns each from its different associated weighting circuit; and a selection circuit for individually addressing each of the storage elements for selective entry of either a flat or weighted pseudo-random pattern into different shift register latches of said scan chains independently of one another for scanning said weighted pattern to said logic circuits to enable provision of pseudo-random patterns of different weights to different shift register latches in the same scan chain.