Patent ID: 8200883

Claim:
An apparatus comprising: an address bus having a plurality of address signals lines to carry shared address signals and independent address signals; an address decoder to selectively access memory cells within a memory array using memory cell address lines, the address decoder accessing memory cells to fill an entire memory channel and accessing memory cells to fill at least one sub-channel of the memory channel, each memory sub-channel comprising a portion of a memory channel and carrying a smaller number of bits than the entire memory channel; a mode register to store a plurality of sub-channel select bits, each sub-channel select bit indicating the selection of one of the plurality of memory sub-channels; and control logic coupled to the address bus, the address decoder, and the mode register, the control logic, in response to each sub-channel select bit, to select a corresponding portion of the address signal lines to support access through the corresponding memory sub-channel and to couple the independent address lines into the address decoder.