Patent ID: 8140797

Claim:
An integrated circuit comprising: an on-chip memory data bus having a plurality of conductive wires to communicate data stored in a memory to at least one of peripheral devices, an on-chip memory connected to the memory data bus, the on-chip memory being controllable to set either a logical one or a logical zero on each of the wires of the memory data bus according to data stored in a memory segment, so that the data stored in the memory segment can be communicated to at least one peripheral device in response to a read instruction, the operation of setting either a logical one or a logical zero on each of the wires of the memory data bus corresponding to a memory access time interval an on-chip access right manager to grant or deny access to the memory segment to the peripheral device according to predetermined access rights upon reception of a read instruction from the peripheral device, the operation of determining whether to grant or refuse access to the memory segment to the peripheral device corresponding to an assess time interval, an on-chip lock connected to the memory data bus, the lock being controllable by the access right manager to block access to logical one or zero set on each memory data bus wire as long as the access to the memory segment is not granted, wherein the integrated circuit is configured to start both the process of setting, by the on chip memory, of either a logical one or a logical zero on each of the wires of the memory data bus, as well as the process of deciding whether to grant or refuse the access to the memory segment by the on-chip access right manager to the peripheral device, upon reception of the read instruction from the peripheral device, wherein the process of setting either a logical one or a logical zero and the process of deciding whether to grant or refuse the access to the memory segment are performed at least partially at the same time, wherein the process of setting either a logical one o a logical zero is configured to begin before the process of deciding whether to grant or refuse the access to the memory segment, wherein the assess time interval is configured to end before the memory access time interval.