Patent ID: 7345919

Claim:
A semiconductor device comprising: a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase, each of said memory cells being an electrically rewritable nonvolatile memory cell; a core selecting portion which selects an optional number of cores from said plurality of cores for writing or erasing data; a data writing portion which writes data in a selected memory cell in a core selected by said core selecting portion; a data erasing portion which erases data from a selected block in a core selected by said core selecting portion; a data reading portion which reads data out from a memory cell in a core which is not selected by said core selecting portion; a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential for a data read operation in a data read mode; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supply potential for a data write or erase operation in a data write or erase mode; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in the data read mode or the data write or erase mode.