Patent ID: 7821509

Claim:
A shift register comprising: a clock signal supply line for supplying a clock signal; a plurality of selectors coupled to the clock signal supply line to generate driving signals in response to sampling signals, each of the selectors comprising a first NOR gate; and a plurality of stages respectively coupled to the selectors to generate the sampling signals in response to the driving signals, wherein at least one of the selectors is adapted to generate at least one of the driving signals in response to a previous one of the sampling signals supplied from a previous one of the stages and a next one of the sampling signals supplied from a next one of the stages, and the first NOR gate is configured to generate a low level signal when at least one of a previous one of the sampling signals from a previous one of the stages and a next one of the sampling signals from a next one of the stages are supplied to the first NOR gate and to output a high level signal in other cases.