Patent ID: 7170802

Claim:
A non-volatile memory comprising: an array of non-volatile storage units arranged into a plurality of bit lines and forming one or more rows; a data transfer line; a plurality of data transfer circuits each connectable to a respective set of one or more of the bit lines and the data transfer line to transfer data between the respective set of bit lines and the data transfer line, wherein data is transferred between each of the data transfer circuits and the data transfer line in response to a respective column select signal; and a plurality of column select circuits connected to form a clocked shift register, having a clock input, each connected to a respective data transfer circuit to provide the respective column select signal, and each having a fuse input, wherein when a fuse signal is asserted on the fuse input, the column select circuit passes the shift register pulse to next stage in the shift register without waiting for the clock and without asserting its respective column select signal.