Patent ID: 8195732

Claim:
An apparatus for computing a GF (2 m ) multiplication, where m is a positive integer, the apparatus comprising: means to calculate a portion of the GF (2 m ) multiplication in a GF multiplication circuit cell; means to interconnect an m-by-m array of GF multiplication circuit cells; means to connect a plurality of inputs to the m-by-m array, wherein the m-by-m array of GF multiplication circuit cells is constructed by replicating the GF multiplication circuit cell in a regular m-by-m organization and interconnecting the m-by-m array of GF multiplication circuit cells according to the equation Y(i)=Y(i−1)+(q m-1 *p+Y(−1) m-1 *g)*x m-i , i=1, 2, . . . , m for m bits in input operands q m-i , and p, set g is coefficients of a generator polynomial g[x], Y(0)=0, and Y(i=m) is an m bit result of the GF(2 m ) multiplication; and means for storing the m bit result of the GF (2 m ) multiplication.