Patent ID: 7978524

Claim:
A semiconductor device comprising: a plurality of first data lines coupled to a plurality of first memory cells, each of which stores one of first information and second information, a plurality of first dummy cells, each of which stores the first information, and a plurality of second dummy cells, each of which stores the second information; a plurality of second data lines coupled to a plurality of second memory cells, each of which stores one of the first information and the second information, a plurality of third dummy cells, each of which stores the first information, and a plurality of fourth dummy cells, each of which stores the second information; a first common data line coupled to the plurality of first data lines through a plurality of first switches; a second common data line coupled to the plurality of second data lines through a plurality of second switches; and a read circuit coupled to the first and second common data lines, and arranged to amplify a potential difference between the first and second common data lines, wherein when one of the plurality of first memory cells is selected, the following are selected to read out the information stored in the selected first memory cell: (1) one of the plurality of third dummy cells; (2) one of the plurality of fourth dummy cells; (3) one of the plurality of first switches that is coupled to the selected first memory cell; and (4) two of the plurality of second switches that are coupled to the selected third dummy cell and the selected fourth dummy cell; and wherein when one of the plurality of second memory cells is selected, the following are selected: (5) one of the plurality of first dummy cells; (6) one of the plurality of second dummy cells; (7) one of the plurality of second switches that is coupled to the selected second memory cell; and (8) two of the plurality of first switches that are coupled to the selected first dummy cell and the selected second dummy cell.