Patent ID: 7659878

Claim:
A display control device comprising: a shift register configured to generate n shift pulses (n is a natural number) in series in synchronization with a clock signal; a data hold block configured to hold n gradation data that are digital data corresponding to an image displayed on a display panel; and a DA converter configured to convert said n gradation data into corresponding gradation voltages respectively, wherein said data hold block has: n first latch circuits configured to respectively latch said n gradation data in series in synchronization with said n shift pulses; and n second latch circuits provided between said DA converter and said n first latch circuits respectively, wherein an electrical connection between said n first latch circuits and said n second latch circuits is cut off while said n first latch circuits receive said n gradation data respectively, and said n gradation data are simultaneously supplied to said DA converter from said n first latch circuits through said n second latch circuits after said n first latch circuits finish latching all of said n gradation data.