Patent ID: 7710167

Claim:
A circuit, comprising: a first circuit portion configured to receive a pulse-width modulated first signal and a second signal, and configured to generate third and fourth signals each responsive to the first and second signals, wherein the first circuit portion is configured to cause the third signal to pulse responsive to a rising edge of the first signal, and to cause the fourth signal to pulse responsive to a falling edge of the first signal; a second circuit portion configured to receive the third and fourth signals and to generate a fifth signal responsive to both the third and fourth signals; a third circuit portion configured to control an on/off state of a first switch in response to the fifth signal, wherein the second signal is present at a load path terminal of the first switch; a capacitor coupled in series with a voltage supply and the load path terminal of the first switch; and a second switch coupled to the capacitor and configured to selectively connect and disconnect the capacitor to the voltage supply, wherein the second circuit portion is configured to control an on/off state of the second switch in response to at least one of the third and fourth signals.