Patent ID: 8028186

Claim:
A node, comprising: a switch; and an input port and an output port, each port having first, second, third and fourth lines, the input port receiving a data word on at least a pair of lines of the first, second third and fourth lines, data bits of the data word having a differential time delay therebetween, wherein the switch is configurable to communicate between the input port and the output port so that the data bits of the data word received on the pair of lines of the input port are routed to a pair of lines of the output port and the pair of output lines is selected based on at least the differential time delay of the data bits of the data word; the node further comprising: a second output port, having first, second, third and fourth lines, and to select between the first output port and the second output port so that the data bits of received on the pair of lines of the input port are routed to a pair of output lines of the second output port, the pair of output lines being selected based on at least the differential time delay of the received data word.