Patent ID: 8361868

Claim:
A method of manufacturing a semiconductor device, comprising: providing a substrate having a semiconductor surface layer, the substrate having a stressor layer positioned at a depth within the substrate so that the stressor layer has an interface with the semiconductor surface layer, a stressed region of the stressor layer adjacent the interface provided in a stressed state in comparison to the semiconductor surface layer; forming a gate structure above the semiconductor surface layer; relaxing a first portion of the stressor layer under the gate structure so as to strain a first portion of the semiconductor surface layer under the gate structure, the relaxing accomplished by implanting into second and third portions of the stressor layer aligned with second and third portions of the semiconductor surface layer; and forming respective source and a drain regions in at least a part of the second and third portions of the semiconductor surface layer, wherein the substrate comprises silicon, the stressor layer comprises silicon germanium and the semiconductor surface layer comprises silicon.