Patent ID: 8492251

Claim:
A method of forming a thin layer structure for a semiconductor device, comprising: forming at an upper portion of a substrate a pattern that exposes part of an upper surface of the substrate; loading the substrate having the pattern thereon onto a susceptor in a process chamber; and forming a layer on the exposed part of the surface of the substrate such that all outer surfaces of the layer have <100> crystallographic orientations, respectively, wherein the forming of the layer comprises a selective epitaxial growth (SEG) process performed on the substrate in the process chamber, and which SEG process includes: supplying reaction source gas into the process chamber, and effecting a temperature control over at least one cycle of a first time period and a second time period that follows the first time period chronologically, and wherein the duration of the second time period is shorter than that of the first time period, the temperature of the substrate is maintained at one temperature throughout the entire duration of the first time period, and the temperature of the substrate is raised from said one temperature to a second temperature during the course of the second time period.