Patent ID: 8879331

Claim:
A method for operating a shared bit line string architecture, comprising: setting a selection even/odd string transistor into a conducting state, the selection even/odd string transistor is connected between a first string and a second string, the first string includes a first select transistor with a first threshold voltage, the second string includes a second select transistor with a second threshold voltage greater than the first threshold voltage, the first select transistor and the second select transistor are controlled by a drain-side select line, the first string includes a memory cell, the second select transistor includes a drain that is directly connected to a shared bit line, the selection even/odd string transistor is connected to the shared bit line and the first select transistor; setting the drain-side select line to a voltage that is greater than the first threshold voltage and less than the second threshold voltage; and performing an operation on the memory cell subsequent to the setting a selection even/odd string transistor into a conducting state.