Patent ID: 7492817

Claim:
An adaptive digital filter comprising: a filtering circuit including a delay circuit having a coefficient a defined by a fundamental formula: a[n+1]=a[n]+β·e[n]·q[n]/p[n], where β is a factor having a number greater than 0 and smaller than 2, e[n] is a difference between a filter input and a filter output, q[n]=u[n−1], and p[n]=u[n] 2 +u[n−1] 2 , the u[n] being an input to the delay circuit, the u[n−1] being an output from the delay circuit; a coefficient renewal circuit that calculates a renewal value of the coefficient a upon input of sampling data to the filtering circuit and that renews the coefficient a by utilizing the calculated renewal value; wherein the coefficient renewal circuit calculates 2 m (m is an integer) greater than p[n] in the fundamental formula, and also calculates the renewal value of the coefficient a in accordance with an execution formula: a[n+1]=a[n]+β·e[n]·q[n]/2 m in place of the fundamental formula, wherein 2 m in the execution formula is a minimum value greater than the p[n], wherein the coefficient renewal circuit calculates the renewal value of the coefficient a by a fixed-point system, the coefficient renewal circuit comprising: a first calculator that detects an uppermost digit with a 1 set therein among digits of binary data representing the p[n], and calculates 2 m whose binary representation includes only a single 1 placed in a digit one higher than said uppermost digit; a bit shifting circuit for shifting respective bits of binary data representing a dividend divided by the p[n] in the fundamental formula, the shifting being performed toward a lower digit side by m bits to produce new binary data; and a second calculator that calculates the renewal value of the coefficient a by using said new binary data.