Patent ID: 7697318

Claim:
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells arranged at intersections of bit line pairs and word lines, wherein each of said memory cells includes a first transistor having one main electrode connected to a first bit line, said first transistor being formed on a substrate, a second transistor having one main electrode connected to a second bit line, said second transistor being formed on said substrate, a first node electrode for data-storage connected to the other main electrode of said first transistor, said first node electrode being formed above the first and second transistors via an interlayer insulator, said interlayer insulator formed between multilayered wirings, a second node electrode for data-storage connected to the other main electrode of said second transistor, said second node electrode being formed above the first and second transistors via said interlayer insulator, a shield electrode with a closed-loop shape surrounding said first and second node electrodes via said interlayer insulator, and a first capacitor including said interlayer insulator between said first and second node electrodes, said first capacitor being configured to store data in said first and second node electrodes, wherein said first transistor and said second transistor have respective gates both connected to an identical word line, wherein said first bit line and said second bit line are connected to an identical sense amp, wherein said first node electrode, said second node electrode, said first bit line, said second bit line, said word line and said shield electrode are electrically isolated from one another with the interlayer insulator interposed therebetween.