Patent ID: 8380933

Claim:
A multiprocessor system comprising: a plurality of processor cores to be debugged; a plurality of cache memories each of which is provided in correspondence with one of the processor cores and includes a tag storage unit configured to store a validity bit representing whether a cache line as a unit to store data is valid, a dirty bit representing whether data in the cache line has been rewritten, and address information of the data in the cache line; a shared memory shared by the processor cores; an arbitration circuit configured to arbitrate a plurality of access requests from the processor cores to the shared memory and send the arbitrated access request to the cache memories, each of the access requests including a first identification signal for identifying an access in which the dirty bit has been rewritten; and an interrupt circuit configured to generate an interrupt for a processor core upon detecting a violation access, wherein each cache memory includes a violation detection circuit configured to detect a violation access by comparing the information in the tag storage unit with the access request from the arbitration circuit, and the violation detection circuit determines the violation access when (a) another processor core makes a read access to the cache line having valid bit =1 and dirty bit =1, (b) another processor core makes a write access to the cache line having valid bit =1, (c) the processor core which is holding data in the cache line having valid bit =1 and dirty bit =1 makes a read access to the cache line by itself, or (d) the processor core which is holding data in the cache line having valid bit =1 makes a write access to the cache line by itself; the violation detection circuit generates violation information about the detected violation access, the interrupt circuit receives the violation information, specifies a processor core of an interrupt target using the violation information, and changes a condition of the processor core of the interrupt target on the basis of interrupt information, and the interrupt information is set for each violation access pattern, contains the number of processor cores of the interrupt target, and is rewritable from the outside.