Patent ID: 8559212

Claim:
A memory circuit, comprising: a first PMOS transistor, coupled between a first voltage terminal and a first node; a second PMOS transistor, coupled between the first voltage terminal and a second node; a first NMOS transistor, coupled between a third node and a second voltage terminal; a second NMOS transistor, coupled between a fourth node and the second voltage terminal; a memory cell array, comprising a plurality of memory cells, wherein at least one of the memory cells comprises a first inverter and a second inverter, wherein a positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node; a control circuit capable of controlling gate voltages of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor, and when the memory circuit operates in a power down mode, the control circuit is capable of controlling the gate voltages to turn on the first PMOS transistor, turn off the second PMOS transistor, turn off the first NMOS transistor, and turn on the second NMOS transistor, to pull an output voltage of the first inverter of the memory cell to a logic high voltage and pull an output voltage of the second inverter of the memory cell to a logic low voltage.