Patent ID: 7849277

Claim:
A bank controller that controls communication to banks of a synchronous dynamic random access memory (DRAM), comprising: (a) a plurality of processing blocks each having at least one first-in first-out (FIFO) memory that is associated with one of the banks of said synchronous DRAM and capable of performing data communication with the associated bank, said plurality of processing blocks performing predetermined operations with data stored in said FIFO memories; and (b) a memory interface that controls said data communication, said memory interface comprising: (b-1) a priority order determining block that determines an order of priorities in said data communication between said FIFO memories and the associated banks; and (b-2) a memory controller that implements the data communication between one of said FIFO memories that is assigned a high priority in said data communication and the associated bank, wherein said priority order determining block determines said order of priorities in said data communication at least on the basis of states of precharge of said banks, said precharge of said banks is an operation performed on said banks after stored data is read from said banks to prevent a loss of said stored data said priority order determining block determines said order of priorities among said FIFO memories on the basis of, in an order of precedence, (1) information about communication request signals sent from said processing blocks to said memory interface, and (2) information about the states of precharge of said banks, where these information (1) and (2) are referred to in this order of precedence, and when said information (1) and (2) are in same conditions, said priority order determining block determines said order of priorities on the basis of channel numbers assigned to said FIFO memories.