Patent ID: 7808538

Claim:
A CMOS image sensor, comprising: a plurality of pixels arranged in rows; a timing and control circuit in electrical communication with the plurality of pixels, wherein the timing and control circuit includes: a monitoring module for determining whether at least one of a first and a second row of pixels are overexposed; an exposure control module configured for exposing a third row of pixels after reading out the first and second rows of pixels, wherein the exposure control module is configured for exposing the third row of pixels in response to determining that the at least one of the first and second rows are overexposed, the third row of pixels being disposed between the first and second rows of pixels; and a readout module configured for: outputting the first row of pixels exposed for a first exposure period; outputting the second row of pixels exposed for the first exposure period after outputting the first row of pixels; and thereafter, outputting the third row of pixels exposed for a second exposure period different than the first exposure period.