Patent ID: 7037775

Claim:
A process for forming active transistors for a semiconductor memory device, said process comprising the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of said transistor gates; forming temporary oxide spacers on said generally vertical sidewalls of said transistor gates by depositing an oxide spacers on said semicondutor memory device that has a thickness that is more than half the spacing between said transistor gates in said memory array section and by etching said oxide layer to form said temporary oxide spacers; after said step of forming temporary spacers, growing epitaxial silicon over exposed silicon regions; after said step of growing an epitaxial silicon, implanting a second type of conductive dopants into said exposed silicon regions to form source/drain regions of said active transistors; removing said temporary oxide spacers; and forming permanent nitride spacers on said generally vertical sidewalls of said transistor gates.