Patent ID: 8748272

Claim:
A method of introducing strain into the channel of a MOS device, comprising: providing a semiconductor substrate; forming a channel in the semiconductor substrate; forming a first gate dielectric layer on the channel; forming a polysilicon gate layer on the first gate dielectric layer; doping or implanting a first element into the polysilicon gate layer; removing a part of the first gate dielectric layer and polysilicon gate layer to thereby form a first gate structure; forming a source/drain extension region in the channel; forming spacers on both sides of the first gate structure; forming a source/drain in the channel; performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing the strain including a horizontal strain component in a direction along the channel and a vertical strain component in a direction perpendicular to the channel in the polysilicon gate layer, and introducing the strain to the channel through the gate dielectric layer to cause a change in the size of the semiconductor lattice in the surface layer of the channel region such that the strain is maintained in the channel; removing the polysilicon gate layer to form an opening by using a wet or dry etching process; and filling the opening with a metal gate layer, thereby forming the MOS device by a gate-last process.