Patent ID: 7906816

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate; an element isolation region which is formed in the semiconductor substrate to isolate an element region of the semiconductor substrate; memory cells having floating gates and formed on the element region, the floating gate having a laminated structure with a plurality of conductive films; resistor elements formed on the element region, each resistor element having a contact portion for connection with a wiring and a resistor portion acting as a resistor, the resistor portion having a laminated structure having at least one of the plurality of conductive films and an insulating layer formed on the plurality of conductive films, and a bottom surface of the insulating layer contacting to an upper surface of the resistor portion; and wherein the contact portion includes a first structure and a second structure, the second structure is directly connected to the first structure via an opening formed in the insulating layer and a gate-gate insulating film, the gate-gate insulating film contacts to an upper surface of the insulating layer, and the insulating layer is flush with the element isolation region a top of the contact portion being at the same height with a top of the insulating layer, and the gate-gate insulating film is formed on the insulating layer.