Patent ID: 7723194

Claim:
A method of fabricating semiconductor devices comprising: forming a isolation layer in a semiconductor substrate to define an active region; forming a gate pattern on the active region; implanting impurities into the active region at both sides of the gate pattern; forming a spacer insulation layer on a surface of the semiconductor substrate with the gate pattern, the spacer insulation layer having a first region between the isolation layer and the gate pattern, wherein the closer the first region lies to the gate pattern, the thinner it becomes; anisotropically etching the spacer insulation layer to form a sidewall spacer on a sidewall of the gate pattern, and to leave a blocking insulation layer on the isolation layer and on a portion of the active region neighboring the isolation layer; and applying a silicidation process to the semiconductor substrate to form a silicide layer on a source/drain region between the blocking insulation layer and the sidewall spacer, the silicide layer having a boundary aligned to the edge of the blocking insulation layer and a boundary aligned to the edge of the sidewall spacer.