Patent ID: 8473719

Claim:
An apparatus comprising: a result register; a first source register; a second source register; an instruction control device to receive a single instruction multiple data add instruction, the single instruction multiple data add instruction to specify the result register, to specify the first source register which is to store a first operand, and to specify the second source register which is to store a second operand, the single instruction multiple data add instruction having a number of source operands parameter to specify a number of source operands including the first and second operands, wherein the number of source operands parameter is capable of specifying any one of two, three, and four source operands, wherein the number of source operands parameter is to have a value selected from 0, 1, 2, and 3, in which the value of 0 is to specify the two source operands, the values of 1 and 2 are to specify the three source operands, and the value of 3 is to specify the four source operands, wherein when the number of source operands parameter specifies four source operands a third source register is to be a register one greater than the first source register and a fourth source register is to be a register one greater than the second source register, the single instruction multiple data add instruction having a data length field to indicate a data length of at least one operand within each of the first and second operands as being one of a plurality of different data lengths, and the single instruction multiple data add instruction having a parameter to indicate that a modulo addition, of two to a power of the indicated data length, minus one, is to be performed; and a single instruction multiple data add logic device coupled with the instruction control device, the single instruction multiple data add logic device to perform the indicated modulo addition of at least the first and second operands to generate a result and to store the result in the result register.