Patent ID: 8705292

Claim:
A memory circuit comprising: a first memory circuit; a second memory circuit; a first switch; a second switch; and a phase inverter circuit, wherein the first memory circuit comprises a first transistor, a second transistor, a third transistor, and a capacitor, wherein the first transistor comprises an oxide semiconductor film, wherein one of a source and a drain of the first transistor is connected to a first signal line, and the other of the source and the drain of the first transistor is connected to one electrode of the capacitor and a gate of the second transistor, wherein the other electrode of the capacitor is grounded, wherein a gate of the first transistor is connected to a second signal line, wherein an input terminal of the phase inverter circuit is connected to the second signal line, and an output terminal of the phase inverter circuit is connected to an input terminal of the first switch, wherein a first terminal of the phase inverter circuit is connected to a power supply line, and a second terminal of the phase inverter circuit is grounded, wherein a first terminal of the first switch is connected to the power supply line, a second terminal of the first switch is connected to one of a source and a drain of the second transistor, and the other of the source and the drain of the second transistor is grounded, wherein a gate of the third transistor is connected to a gate of the second transistor, one of a source and a drain of the third transistor is connected to the power supply line, and the other of the source and the drain of the third transistor is connected to an output terminal of the first switch, wherein a first terminal of the second switch is connected to the output terminal of the phase inverter circuit, and a second terminal of the second switch is connected to the second signal line, and wherein the output terminal of the first switch is connected to the second memory circuit through the second switch.