Patent ID: 6911851

Claim:
A data latch timing adjustment apparatus for adjusting latch timing of output data, the apparatus comprising: a delay selecting section for delaying the output data with a plurality of delay amounts, generating a plurality of delayed output data pieces, and selecting and outputting one of the delayed output data pieces; a latch circuit for receiving the delayed output data piece selected by the delay selecting section and a latch pulse signal, and latching the delayed output data piece at a time of receiving the latch pulse signal; a delay control section for controlling the delay selecting section such that one of the delayed output data pieces with a delay amount different from that of the preceding delayed output data piece is selected by the delay selecting section and the current delayed output data piece is input to the latch circuit every time the latch pulse signal is input to the latch circuit; a comparison circuit for comparing the data piece latched by the latch circuit with an associated checking data piece to determine whether or not the latched data piece and the checking data piece match each other; and a determination section for receiving a plurality of comparison results from the comparison circuit, and determining, based on the comparison results, a delay amount in the delay selecting section with which the latch circuit latches the data piece appropriately.