Patent ID: 7183798

Claim:
A programmable logic device comprising: a first logic slice adapted to receive a first clock signal, wherein the first logic slice comprises: a first write port clock multiplexer; a first write port control circuit coupled to the first write port clock multiplexer; a first and a second lookup table coupled to the first write port control circuit; a first and a second register couplable to the first and second lookup table; and a first read port clock multiplexer coupled to at least one of the first and second registers; a second logic slice adapted to receive a second clock signal, wherein the second logic slice comprises: a second write port clock multiplexer; a second write port control circuit coupled to the second write port clock multiplexer; a third and a fourth lookup table coupled to the second write port control circuit; a third and a fourth register couplable to the third and fourth lookup table; and a second read port clock multiplexer coupled to at least one of the third and fourth registers; and wherein the first logic slice is also adapted to receive the second clock signal and the second logic slice is also adapted to receive the first clock signal.