Patent ID: 8367533

Claim:
A method of forming a semiconductor device, the method comprising: providing a semiconductor substrate having a PMOS region; forming a gate pattern on the PMOS region of the semiconductor substrate, the gate pattern including a first metal silicide pattern; forming a first source/drain region in the PMOS region of the semiconductor substrate; forming a spacer on a sidewall of the gate pattern, the spacer covering a portion of the first source/drain region; forming an interlayer dielectric that covers the gate pattern and the first source/drain region; forming a contact hole in the interlayer dielectric that exposes a portion of the semiconductor substrate; selectively forming a metal pattern that includes a dopant in the contact hole on the exposed portion of the semiconductor substrate; and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern while diffusing some of the dopant into the semiconductor substrate.