Patent ID: 6933665

Claim:
An emitter tip array, comprising: a number of vertical geometries on a silicon substrate, wherein the number of vertical geometries are formed by a method comprising: implanting a P-type dopant in a patterned manner into a silicon substrate, wherein implanting a P-type dopant in a patterned manner includes using a mask structure to define a more heavily P-type doped region in the silicon substrate surrounding a number of less heavily doped emitter tip regions; anodizing the silicon substrate, wherein anodizing the silicon substrate causes the more heavily doped region to form a porous silicon region, oxidizing the porous silicon region to form an oxidized porous silicon region; removing a portion of the oxidized porous silicon region; and a number of gate structures adjacent to the number of vertical geometries, wherein the mask structure self aligns the gate structures with the number of vertical geometries.