Patent ID: 8836014

Claim:
An electronic memory cell comprising: a substrate on which there is formed an active channel zone produced in a semiconductor material and comprising a channel disposed between a drain extension region and a source extension region; a first gate structure surmounting a first part of said channel; a lateral spacer disposed against at least one lateral flank of said first gate structure, said lateral spacer comprising a second gate structure surmounting a second part of said channel, said second gate structure comprising: a stack of layers, wherein one of said layers is arranged to store electrical charges, said stack including a first stack zone in contact with said second part of said channel and a second stack zone in contact with said lateral flank of said first gate structure; a conductive zone of the second gate structure including a first lateral face in contact with said second stack zone in such a way that the latter separates said lateral flank of the first gate structure and said first lateral face; a lower face essentially plane and parallel to the plane of the substrate, said lower face being in contact with said first stack zone in such a way that said first stack zone separates said second part of said channel and said lower face; an upper face essentially plane and parallel to the plane of the substrate; a second lateral face, said first and second lateral faces connecting said lower face to said upper face, said second lateral face being inclined at an angle α strictly between 0 and 90° with respect to the plane of the substrate, in such a way that the length of said upper face is strictly greater than the length of said lower face, said lengths being measured as the distance between said first and second lateral faces over the length of said channel.