Patent ID: 7913110

Claim:
An apparatus comprising: a memory comprising a matrix with rows and columns of memory cells; a read access circuit configured to execute a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix and to output data from the retrieval unit, the data in the retrieval unit comprising payload data and addressable extra data outside an address space for the payload data; a processing circuit coupled to the read access circuit and configured to execute an extra read process comprising issuing the read command, receiving the extra data, to perform error detection on only the extra data, making use of an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data using data from the retrieval unit including the payload data, according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data, the processing circuit being configured to perform further processing using the data from the extra data or the corrected extra data, dependent on whether the error detection indicates an error in the extra data; wherein the read access circuit is configured to read the retrieval unit and to serially output data from the retrieval unit in response to the read command, the processing circuit being configured to obtain the extra data from a part of the retrieval unit that is output in response to the read command at least partly before the payload data, and causing the output to cease if the error detection indicates absence of an error in the extra data.