Patent ID: 6907555

Claim:
A self-test circuit that detects defects of a memory device, incorporated in the memory device having a memory control circuit that controls write and read operations with respect to a memory core in response to a command, comprising: a test operation command generating circuit that, in self-test activated condition, generates a test operation command that designates said writing or reading, and that supplies the test operation command to said memory control circuit; a test address generating circuit that, in said self-test activated condition, generates a test address and supplies the test address to said memory core; a test data generating circuit that, in said self-test activated condition, generates test data and supplies the test data to said memory core; a test output circuit that compares read data from said memory core with said test data and stores information as to the result of this comparison, and outputs the information to the outside; and a test operation mode selector circuit that, in said self-test activated condition, generates a test operation mode signal that designates any of a plurality of test operation modes including said write or read in response to a test operation mode input signal from outside, wherein, in response to said test operation mode signal, said test operation command generating circuit generates said test operation command for executing said test operation mode, wherein said self-test circuit goes into the self-test activated condition in response to a self-test activation signal from outside.