Patent ID: 7937634

Claim:
A circuit providing dynamic scan chain partitioning, comprising: a partitioning block circuit adapted for insertion into a scan chain architecture, the scan chain architecture having a plurality of scan chains, each of the scan chains having a scan chain clock; the partitioning block circuit being configured for manipulating the scan chain clocks feeding the scan chains and being configured for dynamically partitioning the scan chains into groups to minimize peak power, wherein the partitioning block circuit comprises: a partition register containing a plurality of flip-flops for each of the scan chains; a clock generator block circuit for generating a clock signal feeding the partition register; a plurality of AND gates connected to the flip-flops; and a plurality of multiplexers connected to the plurality of AND gates, the plurality of multiplexers selecting one of the clock signals as the clock signal for the corresponding scan chain, each of the clock signals having a delay adjusted to stagger clock edges within a shift cycle.