Patent ID: 7939408

Claim:
A method of fabricating a non-volatile memory for 2-bit operation comprising: sequentially forming a tunnel dielectric layer, a charge storage layer, and a charge blocking layer on a-semiconductor substrate; forming a hard mask for an isolation region defining active regions extending in a word line direction on the charge blocking layer; sequentially patterning the tunnel dielectric layer, the charge storage layer, and the charge blocking layer, using the hard mask as an etch mask; forming the isolation region in the semiconductor substrate exposed to the hard mask; selectively removing the hard mask; forming gates extending in the word line direction on the patterned charge blocking layer, and partially crossing with the active regions repeatedly; selectively removing the underneath exposed and remaining charge blocking layer, the charge storage layer and the tunnel dielectric layer using the gate as an etch mask, thereby patterning such that the charge storage layer is confined to the portions where the gate and the active cross; forming first and second source/drain regions in the active region at a region exposed out of both sides of the gate; forming an insulating layer to cover the first and second source/drain regions and the gate; forming a connecting contact penetrating the insulating layer and exposing the first and second source/drain regions; and forming first and second bit lines on the insulating layer to be connected to the first and second source/drain regions respectively through the connecting contact and extend in a bit line direction crossing the word line direction, wherein at least one of the gates and the active regions are formed in a zigzag pattern.