Patent ID: 7292082

Claim:
A digital duty cycle corrector for a multi-phase clock application comprising: a flip-flop receiving a signal having a first clock cycle as an input and generating a reference signal having a cycle twice the first clock cycle; a duty corrector generating a signal having a second clock cycle that is half the cycle of the reference signal, from the reference signal; a duty detector measuring an amount of a duty error of the second clock cycle signal and generating a digital code value to control a duty cycle of the second clock cycle signal becomes 50%, wherein the digital code value comprises a plurality of binary bits; and a phase inverter inverting a phase of the second clock cycle signal by 180° such that a rising edge of the second clock cycle signal is always fixed constantly regardless of a duty cycle correction operation, wherein the duty cycle is determined by a thermometer code having a plurality of binary bits so that, when a thermometer code value increases, the duty cycle of the second clock cycle signal decreases and, when a thermometer code value decreases, the duty cycle of the second clock cycle signal increases.