Patent ID: 7765446

Claim:
A method for verifying design rules which are applied when a semiconductor integrated circuit having a scan path circuit is laid out, comprising: (a) selecting scan chains which are the closest to those of design rules of the semiconductor integrated circuit based on layout information; (b) laying out interconnections between flip-flops of the selected scan chains so as to bring the interconnections close to each other while providing the minimum spacing specified in the design rules in any given direction; (c) generating signals to be inputted to the selected scan chains to test for the effect of crosstalk; (d) bringing the selected scan chains to a shift resistor state in which shift resistor operation can be effected; and (e) determining whether crosstalk occurs or not by inputting the signals to the scan chains being in the shift resistor state and by comparing an expected value and values of signals outputted from scan-out terminals via the shift resistors of the scan chains.