Patent ID: 7456033

Claim:
A method of evaluating a semiconductor device, said method comprising the steps of: forming a plurality of MOS transistors, each MOS transistor having an active layer and a gate that are the same as those of the semiconductor device, the active layer being provided with a first portion and a second portion arranged substantially at right angles with each other and connected by an arcuate curved portion therebetween, the gate being formed over the first portion of the active layer, the gate being separated from the second portion by a pattern interval, the MOS transistors being identical to each other except that the pattern interval of each MOS transistor is different from each other; measuring characteristics of the plurality of MOS transistors respectively; plotting the characteristics relative to the pattern interval, and finding a minimum pattern interval from which the characteristics of MOS transistors become substantially constant irrespective to an increase of the pattern interval, wherein the MOS transistors include a number of MOS transistors enough to provide the minimum pattern; and setting a pattern interval of the semiconductor device to be the same as or greater than said minimum pattern interval.