Patent ID: 8468422

Claim:
A method for predicting uncorrectable errors in a memory system comprising: detecting a plurality of correctable errors from a memory device; analyzing the plurality of correctable errors to identify a pattern of the plurality of correctable errors, the pattern indicative of a future occurrence of an uncorrectable error from the memory device wherein the analyzing operation comprises: identifying a plurality of first correctable errors from a first bit position of a memory device, the plurality of first correctable errors generated while accessing a first address and a second address in the memory device, wherein the first address and the second addresses are distinct; identifying a plurality of second correctable errors from a second bit position of the memory device, the plurality of second correctable errors generated while accessing a third address and a fourth address in the memory device, wherein the third address and the fourth addresses are distinct; identifying a first checkword position associated with the first bit position; identifying a second checkword position associated with the second bit position; and identifying whether the first checkword position and the second checkword position occur in a same checkword construct comprising a plurality of checkword positions populated by a plurality of bit positions of the memory device; and determining that the plurality of first correctable errors occurs at the first bit position and the plurality of second correctable errors occurs at the second bit position; and providing an indicator of the future occurrence of the uncorrectable error from the memory device.