Patent ID: 7586137

Claim:
A non-volatile memory device comprising: a semiconductor substrate; a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities; a trapping structure which includes a tunneling layer, which is disposed on a predetermined region of the semiconductor substrate and through which charge carriers are tunneled, and a charge trapping layer, which is formed on the tunneling layer and traps the tunneled charge carriers; a gate insulating layer which is conformably formed on the trapping structure and the semiconductor substrate; a gate electrode which is formed on the gate insulating layer; and a channel region which is formed between the source region and the drain region and includes a first channel region formed on a lower part of the trapping structure and a second channel region formed on a lower part of the gate insulating layer, the threshold voltage of the first channel region being lower than that of the second channel region, wherein the gate insulating layer and the gate electrode are formed on the first channel region and the second channel region.