Patent ID: 7019406

Claim:
A thermally enhanced semiconductor package, comprising: at least one chip having an active surface and an opposite inactive surface, the active surface formed with a plurality of bond pads thereon; a conductive bump formed on each of the bond pads of the chip; a heat sink attached to the inactive surface of the chip and having a surface area larger than that of the chip; an encapsulation body for encapsulating the heat sink, the chip, and the conductive bumps, wherein a plurality of surfaces, other than that for attaching the chip, of the heat sink and ends of the conductive bumps are exposed to outside of the encapsulation body; a plurality of first conductive traces formed on the encapsulation body and electrically connected to the exposed ends of the conductive bumps; and a solder mask layer applied over the first conductive traces and formed with a plurality of openings for exposing predetermined portions of the first conductive traces.