Patent ID: 8258868

Claim:
An apparatus comprising: a first voltage rail; a second voltage rail; a first current mirror including: a first current mirror transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first current mirror transistor is coupled to the first voltage rail; and a second current mirror transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the second current mirror transistor is coupled to the first voltage rail, and wherein the second passive electrode and control electrode of the second current mirror transistor are each coupled to the control electrode of the first current mirror transistor; a differential input pair including: a first ambipolar transistor that is coupled to the second passive electrode of the first current mirror transistor at its drain; and a second ambipolar transistor that is coupled to the second passive electrode of the second current mirror transistor at its drain and the source of the first ambipolar transistor at its source; a correction circuit including: a first resistor that is coupled to the gate of the first ambipolar transistor and that receives a first portion of an input signal; a second resistor that is coupled to the gate of the second ambipolar transistor and that receives a second portion of the input signal; a first diode that is coupled to the gate of the first ambipolar transistor at its anode and to the gate of the second ambipolar transistor at its cathode; and a second diode that is coupled to the gate of the second ambipolar transistor at its anode and the gate of the first ambipolar transistor at its cathode; and a second current mirror having: a third current mirror transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the bias transistor is coupled to the sources of the first and second ambipolar transistors, and wherein the second passive electrode of the bias transistor is coupled to the second voltage rail; a fourth current mirror transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode and the control electrode of the fourth transistor receive a bias voltage, and wherein the control electrode of the fourth current mirror transistor is coupled to the control electrode of the third current mirror electrode, and wherein the second passive electrode of the fourth current mirror transistor is coupled to the second voltage rail.