Patent ID: 7956448

Claim:
A stacked structure, comprising: a first substrate including a first pad structure; and a second substrate including: a transistor gate formed over the second substrate, a first conductive structure extending through the second substrate and having a top surface that is substantially planar with a top surface of the second substrate, the first conductive structure including at least one of a dielectric liner and a barrier layer surrounding a conductive material, an interlayer dielectric (ILD) layer disposed over the transistor gate, the ILD layer including at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate, a second conductive structure disposed in the ILD layer and being at least partially disposed over a surface of the first conductive structure, and a passivation layer disposed over the ILD layer and including a second pad structure that makes electrical contact with the second conductive structure, wherein the first substrate is coupled to the second substrate by bonding the first substrate with the second substrate such that the first pad structure contacts the second pad structure.