Patent ID: 8184660

Claim:
An system comprising: a first circuit configured to generate a multiplexed signal in response to a video input signal, said video input signal comprising a plurality of video frames, wherein (i) a first sequence of said video input signal operates at a first frame rate, and (ii) a second sequence of said video input signal operates at a second frame rate; said multiplexed signal comprises (a) a pre-defined packet which specifies a new frame rate corresponding to either (i) said first frame rate or (ii) said second frame rate, and (b) repeated video frames encoded as a digital duplicate of a previous frame; wherein the first circuit comprises a digital detector configured to detect digitally repeated frames and augments said digitally repeated frames into augmented digitally repeated frames; if the digital detector detects the digitally repeated frames, said multiplexed signal comprises (c) the pre-defined packet which specifies said new frame rate corresponding to either (i) said first frame rate or (ii) said second frame rate, and (d) said augmented digitally repeated frames arranged in a field repeat pattern scheme if said video input signal comprises (i) only said first frame rate or (ii) only said second frame rate; and a second circuit configured to generate a video output signal in response to decoding said multiplexed signal.