Patent ID: 6987825

Claim:
A digital synchronous circuit, comprising: a clock generating circuit for outputting a plurality of clock signals having same frequency and different phases; a plurality of first latch circuits for taking in an input data signal according to corresponding ones of said plurality of clock signals; a control circuit for outputting a control signal after a prescribed period of time according to a change in said input data signal; and a plurality of second latch circuits for taking in and holding outputs of said plurality of first latch circuits, respectively, according to said control signal, wherein said control circuit includes a pulse generating circuit for generating a pulse signal according to a change in said input data signal, and a delay circuit for receiving said pulse signal and entering a meta-stable state for at least part of, but not more than, said prescribed period time to cause delay for said prescribed period of time, wherein the delay circuit comprises a third latch circuit for receiving said pulse signal at a data input node and a clock input node, and said third latch circuit has a first output node for outputting a signal of an equal polarity to said data input signal and a second output node for outputting an inverted output of said signal output from said first output node.