Patent ID: 7268591

Claim:
A memory subsystem system comprising: a memory array having 2 n locations; an address decoder coupled to receive n address bits indicating a first address of the memory array corresponding to one of the 2 n locations, wherein the address decoder is configured to provide a first plurality of output based on the n address bits; rotation logic coupled to receive at least a subset of the n address bits and m rotation bits, and wherein the m rotation bits indicate a number of locations the first address is to be shifted if the first address falls within a specified range of addresses, wherein the rotation logic is configured to provide a second plurality of outputs based on one or more of n address bits and the m rotation bits, and wherein the rotation logic is configured to operate in parallel with the address decoder; and address selection logic, wherein the address selection logic is coupled to receive the first plurality of outputs from the address decoder and the second plurality of outputs from the rotation logic, wherein the address selection circuit is configured to select a second address in the memory array based on the first and second pluralities of outputs.