Patent ID: 7099192

Claim:
A nonvolatile memory structure comprising: a semiconductor substrate, said semiconductor substrate being p-type or n-type; a transistor located on a surface of said semiconductor substrate, said transistor comprising a first dielectric on the surface of said semiconductor substrate, a conducting gate stacked above said first dielectric, and several first doped regions in said semiconductor substrate as a source and a drain thereof, respectively; and a capacitor located on the surface of said semiconductor substrate and electrically separated from said transistor by an isolator region, said capacitor comprising a second doped well region formed in said semiconductor substrate, a single contact region formed in said well region, a second dielectric on a surface of said second doped well region, and a second conducting gate stacked above said second dielectric, wherein a control gate voltage V control is applied exclusively to said single contact region, and wherein said first and second conducting gates being are electrically connected together to form a single floating gate; wherein if said semiconductor substrate is p-type, then said first doped region and said second doped region are n-type, wherein during an erase mode of operation of said memory structure, a source voltage coupled to said source and a drain voltage coupled to said drain, respectively, are higher than a substrate voltage coupled to said semiconductor substrate, and wherein said control gate voltage is much higher than said substrate voltage.