Patent ID: 7725844

Claim:
A circuit for implementing sense amplifier verification comprising: a sense amplifier; a first pull-up resistor connected between a positive voltage supply rail and a first sensing node of the sense amplifier; a second pull-up resistor connected between a positive voltage supply rail and a second sensing node of the sense amplifier; a first predefined resistor and a second predefined resistor coupled to the first sensing node; said first predefined resistor having a first resistance to impersonate a blown fuse and said second predefined resistor having a second resistance to impersonate an unblown fuse; a reference resistor coupled to the second sensing node; a first control transistor connected between said first predefined resistor and the first sensing node; a second control transistor connected between said second predefined resistor and the first sensing node; a reference control transistor connected between said reference resistor and the second sensing node; a first control signal applied to said first control transistor to connect said first predefined resistor to the first sensing node, and a reference control signal applied to said reference control transistor to connect said reference resistor to the second sensing node for sensing said first predefined resistor relative to said reference resistor; a second control signal applied to said second control transistor to connect said second predefined resistor to the first sensing node, and said reference control signal applied to said reference control transistor to connect said reference resistor to the second sensing node for sensing said second predefined resistor relative to said reference resistor; and the sense amplifier responsive to identifying a respective sense amplifier output of an unblown eFuse and a blown eFuse, identifying valid sense amplifier operation.