Patent ID: 8227301

Claim:
A method of fabricating a semiconductor device structure using a semiconductor-on-insulator substrate having a semiconductor layer, a bulk semiconductor region underlying the semiconductor layer, and a dielectric layer between the semiconductor layer and the bulk semiconductor region, the method comprising: patterning the semiconductor layer to define a semiconductor body with first and second sidewalls extending to the dielectric layer, the semiconductor body having a first section with a first constant width between the first and second sidewalls, a second section with second constant width between the first and second sidewalls, and a third section between the first and second sections; forming a gate electrode having an arrangement relative to semiconductor body such that each of the first, second, and third sections of the semiconductor body is at least partially overlapped by the gate electrode; and introducing a first impurity of a first conductivity type into the first, second, and third sections of the semiconductor body with a first concentration selected in conjunction with the first width and the second width such that, when the first section is biased by a bias potential, the first and third sections are partially depleted and the second section of the semiconductor body is fully depleted to define a floating charge-neutral region in the first and third sections, wherein the first, second, and third sections are disposed along the length of the semiconductor body, the first constant width of the first section is wider than the second constant width of the second section, and the third section tapers from the first constant width of the first section to the second constant width of the second section.