Patent ID: 8656256

Claim:
A method for operating a multi-level cell (MLC) flash memory circuit, the method comprising the steps of: reading data from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, wherein the memory block is initially operating in the MLC mode, and wherein the MLC flash memory circuit stores an MLC table for tracking memory blocks in the MLC mode, an SLC table for tracking memory blocks in the SLC mode and a defective blocks table for tracking memory blocks in the defective mode; performing error correction on the read data to correct read errors in the read data; determining if a number of bits corrected by the error correction exceeds a predetermined threshold value; if the number of bits corrected by the error correction exceeds the predetermined threshold value, switching the operating mode of the memory block from the MLC mode to the SLC mode; and updating at least one of the MLC table, the SLC table or the defective blocks table based on the switching of the operating mode.