Patent ID: 8324951

Claim:
A dual data rate flip-flop circuit comprising: a plurality of latch circuits connected in parallel, each latch circuit including a clock input, a data input, and a latch circuit output; a plurality of C-elements, each C-element including a plurality of C-element inputs and a C-element output, at least one of said plurality of C-element inputs being connected to said latch circuit output of at least one said latch circuit; an extended C-element having a plurality of extended C-element inputs and an extended C-element output, at least one of said plurality of extended C-element inputs being connected to at least one of said C-element output; an output buffer inverter connected to said extended C-element output, said output buffer inverter having a flip-flop circuit output; at least one internal keeper circuit connected to said plurality of C-elements; and a C-element keeper circuit connected to said extended C-element output.