Patent ID: 7491657

Claim:
A method of manufacturing a semiconductor device comprising: forming a gate insulating film on a one time programmable (OTP) cell region on a substrate; forming a floating gate on the gate insulating film; forming first insulating spacers that cover sidewalls of the floating gate; forming source/drain regions on sides of the floating gate on the substrate; forming a plasma enhanced oxide (PEOX) film that covers the floating gate and the first insulating spacers; forming an interlayer insulating film on the PEOX film; forming a gate to form a transistor in a main chip region near the OTP cell region on the substrate and forming second insulating spacers that cover sidewalls of the gate after forming the first insulating spacers in the OTP cell region; and forming a silicon oxy nitride (SiON) film pattern that covers the gate and the second insulating spacers except the floating gate and an area surrounding the floating gate after forming the source/drain regions and before forming the PEOX film.