Patent ID: 8514652

Claim:
A multiple-port memory device having at least first and second ports each configured to support read and write operations, the multiple-port memory device further comprising: a single-port memory device comprising a memory array; and control circuitry coupled between the first and second ports and the single-port memory device; wherein the control circuitry is configured to multiplex input signals received over the first and second ports of the multiple-port memory device into respective input time slots of the single port of the single-port memory device, and to demultiplex output time slots of the single port of the single-port memory device into respective output signals that are supplied over the first and second ports of the multiple-port memory device; wherein the single-port memory device receives the input signals in accordance with a first clock signal and processes those input signals using a second clock signal having a higher clock rate than the first clock signal; and wherein the input and output time slots are defined with respect to the second clock signal.