Patent ID: 7638774

Claim:
An array panel comprising: a substrate including a gate driver region, a data pad region, and a storage capacitor region; a first conductive line formed in the data pad region; a second conductive line formed in the storage capacitor region, a portion of the second conductive line functioning as a capacitor electrode of a storage capacitor; a first switching element formed in a pixel region; a first transparent layer including first and second transparent electrodes formed on the first and second conductive lines, respectively; an insulating layer having a first contact hole extending to the first transparent electrode on the first conductive line in the data pad region and a second contact hole extending to a drain electrode of the first switching element in the pixel region; an organic layer formed on the insulating layer, the organic layer having a first removed portion exposing the first transparent electrode in the data pad region and a second removed portion exposing the drain electrode of the first switching element in the pixel region; and a second transparent layer formed on the organic layer, the second transparent layer including a third transparent electrode directly connected to the first transparent electrode through the first contact hole in the data pad region and a fourth transparent electrode directly connected to the drain electrode through the second contact hole in the pixel region, wherein a portion of the organic layer in the storage capacitor region is removed, and the fourth transparent electrode extends to the storage capacitor region to be disposed directly on the insulating layer in the storage capacitor region, thereby forming the storage capacitor comprising the capacitor electrode, the second transparent electrode, a portion of the insulating layer in the storage capacitor region, and the fourth transparent electrode extending to the storage capacitor region.