Patent ID: 8521996

Claim:
A pipelined microprocessor, comprising: a pipeline of stages for processing instructions; and an instruction set, comprising first and second distinct types of conditional branch instructions includable by a program; wherein the microprocessor is configured to make a prediction of conditional branch instructions of the first type and to flush the pipeline of instructions if the prediction is subsequently determined to be incorrect, wherein the microprocessor incurs a branch misprediction penalty related to processing of conditional branch instructions of the first type when the prediction is subsequently determined to be incorrect; wherein the microprocessor is configured to always correctly resolve conditional branch instructions of the second type without making a prediction of conditional branch instructions of the second type, wherein the microprocessor avoids ever incurring a branch misprediction penalty related to processing of conditional branch instructions of the second type; wherein for each instance of the conditional branch instructions of the second type, the microprocessor is configured to wait to correctly resolve the instance until a branch condition state has been updated by a newest instruction that updates the branch condition state that is older in ram order than the instance and then to use the updated condition state to resolve the instance; and wherein the microprocessor further comprises: an execution unit, configured to execute the newest instruction that updates the branch condition state that is older in program order than the instance; and an instruction fetch unit, preceding the execution unit in the microprocessor pipeline; and wherein the instruction fetch unit, rather than sending the instance to the execution unit to be resolved and rather than making a prediction of the instance, is configured to wait to correctly resolve the instance until the branch condition state has been updated by the newest instruction that updates the branch condition state that is older in program order than the instance and then to use the updated condition state to resolve the instance.