Patent ID: 8860433

Claim:
An apparatus comprising: a first clock signal generator to provide a first clock signal to a transmitter of a transceiver, wherein the first clock signal is to operate at a first frequency; a second clock signal generator to provide a second clock signal to a receiver of the transceiver, wherein the second clock signal is to operate at a second frequency, wherein the receiver is to sample an output of the transmitter at a sampling rate determined by the second frequency, and wherein the second clock signal generator is to receive the first clock signal and generate the second clock signal; and a logic circuit operative to receive an output signal from the receiver and further to determine an indication of jitter based on the received output signal, wherein the logic circuit is further to determine the indication of jitter by counting the number of consecutive clock cycles in a transition period, wherein the transition period is a period of time in which the output signal transitions from a first state to a second state.