Patent ID: 7355466

Claim:
A mixer circuit comprising: a first differential transistor pair; a second differential transistor pair; first and second local oscillator signal terminals coupled with the first and second differential transistor pairs; first and second mixed signal terminals, the first mixed signal terminal being coupled with the first differential pair and the second mixed signal terminal being coupled with the second differential pair; first and second baseband signal terminals, each baseband signal terminal being coupled with the first differential pair and the second differential pair; a first current source coupled with the first differential pair and the first mixed signal terminal, the first current source, in operation, providing a first direct-current bias to the first differential pair; a second current source coupled with the second differential pair and the second mixed signal terminal, the second current source, in operation, providing a second direct-current bias to the second differential pair; and a gate-bias circuit coupled with the first and second differential transistor pairs, the gate-bias circuit, in operation, providing a direct-current voltage bias to gate terminals of the first and second differential transistor pairs, wherein the gate-bias circuit comprises: a power supply terminal that, in operation, delivers a power supply voltage to the gate-bias circuit; an electrical ground supply terminal that, in operation, provides an electrical ground reference to the gate-bias circuit; a resistor divider coupled between the power supply terminal and the ground supply terminal, the resistor divider, in operation, establishing a direct-current voltage potential based on the power supply voltage, wherein the established voltage is applied to gate terminals of transistors of the first and second differential pairs; a first series resistor coupled with the resistor divider and respective gate terminals of a first transistor of the first differential pair and a first transistor of the second differential pair, so as to deliver the established voltage potential; and a second series resistor coupled with the resistor divider and respective gate terminals of a second transistor of the first differential pair and a second transistor of the second differential pair, so as to deliver the established voltage potential.