Patent ID: 8097913

Claim:
An electrically erasable and programmable read only memory (EEPROM) device comprising: a substrate; and a pair of transistors including first and second transistors formed on the substrate, the first and second transistors having substantially the same structure and configured to alternately serve as a memory transistor and a selection transistor within the same memory cell according to an applied signal, wherein a common source region is formed between the first and second transistors, as a source region for both of the first and second transistors, a first drain region is formed adjacent to the first transistor opposite the common source region, and a second drain region is formed adjacent to the second transistor opposite the common source region, wherein the common source region, the first drain region, and the second drain region have a first impurity concentration, a second impurity concentration, and a third impurity concentration, respectively, the second and third impurity concentrations being substantially larger than the first impurity concentration, and wherein the first transistor includes a first floating gate that is not shorted with a second floating gate of the second transistor.