Patent ID: 8829944

Claim:
An integrated circuit comprising: positive and negative input nodes configured to receive positive and negative input signals (e.g., Vplus, Vminus); input circuitry (e.g., 210 ) powered by a local power supply signal (e.g., VDD); a set of one or more clocked input switches (e.g., 208 ) connected between the input nodes and the input circuitry and configured to control application of the input signals to the input circuitry based on a switch clock signal (e.g., CLK_SW); clock circuitry (e.g., 204 , 206 ) configured to selectively generate the switch clock signal based on either the local power supply signal or the positive input signal; and an over-voltage detector (e.g., 202 ) configured to detect whether the positive input signal is greater than or less than the local power supply signal and generate and apply a corresponding control signal (e.g., VSEL) to the clock circuitry, such that: when the control signal indicates that the positive input signal is greater than the local power supply signal, the clock circuitry uses the positive input signal to power the switch clock signal; and when the control signal indicates that the positive input signal is less than the local power supply signal, the clock circuitry uses the local power supply signal to power the switch clock signal.