Patent ID: 7023445

Claim:
An apparatus comprising: a processor; a graphics unit comprising a graphics unit cache configured to store graphics data; a memory coupled to the processor and the graphics unit, wherein the memory is configured to store processor data and graphics unit data; and a shared cache coupled to the processor, the graphics unit, and the memory, wherein the shared cache is configured to store processor data and graphics unit data; wherein the graphics unit is configured to: partition images to be rendered into a plurality of subset areas; track the number of times data corresponding to each of the subset areas is considered during the rendering of a first image; and determine for each of the subset areas whether data corresponding to a subset area is cacheable; wherein the graphics unit includes a plurality of entries, each entry corresponding to one of the subset areas and including an indicator which indicates whether the corresponding subset area is cacheable in the shared cache; wherein during the rendering of a second image, the graphics unit is further configured to store data evicted from the graphics unit cache in the shared cache only if an indicator in an entry which corresponds to the data evicted from the graphics unit cache indicates the data evicted from the graphics unit cache is cacheable in the shared cache, said indicator being set prior to initiating the rendering of the second image.