Patent ID: 7606695

Claim:
A system for evaluating simulators using a circuit design comprising: a processor; a reference simulator configured to generate golden data by executing a first simulation image using the processor, wherein the first simulation image is compiled from a first implementation of the circuit design; a test simulator configured to generate test data by executing a second simulation image, wherein the second simulation image is compiled from a second implementation of the circuit design; and a comparator configured to select a portion of the test data, use a mapping rule of a plurality of mapping rules to identify a portion of the golden data associated with the portion of the test data, and generate a comparison result by comparing the portion of the golden data to the portion of the test data before the execution of the second simulation image on the test simulator has completed, wherein the plurality of mapping rules map an internal hierarchy of the first implementation to an internal hierarchy of the second implementation, wherein the comparison result is used to debug the test simulator by correcting and displaying an error detected in the comparison result, and wherein the reference simulator executes the first simulation image in lockstep with execution of the second simulation image.