Patent ID: 8258496

Claim:
A semiconductor integrated circuit device comprising: a semiconductor substrate on which a circuit is formed; a plurality of cell arrays stacked on the semiconductor substrate in such a manner that first metal lines and second metal lines crossing each other are repeatedly stacked with memory cells disposed at the respective cross-points of the first and second metal lines; interlayer insulating films buried between the first and second metal lines and between memory cells arranged laterally; and vertical wirings so disposed outside of the cell arrays as to couple the first and second metal lines of the cell arrays to the circuit, the vertical wirings being formed of multi-layered metal pieces buried in the interlayer insulating films, wherein the multi-layered metal pieces are patterned from the same metal layers as the first and second metal lines, each layer of the multi-layered metal pieces has multiple metal pieces disposed at multiple contact portions in a stripe-shaped contact trench formed to be extended over the multiple contact portions on the interlayer insulating film, and the multiple metal pieces are formed by dividing a metal layer formed along a bottom and side walls of the stripe-shaped contact trench in a longitudinal direction.