Patent ID: 7919991

Claim:
A comparator circuit for comparing first and second binary numbers A and B each having a number N of bits, comprising: a single-bit comparison stage having a plurality of input pairs each for receiving a corresponding bit A n of the first binary number and a corresponding bit B n of the second binary number, having a plurality of first outputs each for generating a corresponding single-bit equality signal EQ n , and having a plurality of second outputs each for generating a corresponding single-bit greater than signal GT n ; and a resolution stage having a plurality of first inputs to receive the single-bit equality signals, a plurality of second inputs to receive the single-bit greater than signals, having a first output to generate an output equality signal EQ OUT indicating whether the first binary number is equal to the second binary number, and having a second output to generate an output greater than signal GT OUT indicating whether the first binary number is greater than the second binary number, wherein the single bit comparison stage comprises: a first PMOS transistor coupled between a voltage supply and a first output node and having a gate to receive a clock signal; a second PMOS transistor coupled between the voltage supply and a second output node and having a gate to receive the clock signal; first and second NMOS transistors coupled in series between the first output node and a discharge node and having gates to receive the corresponding bits A n and B n ; third and fourth NMOS transistors coupled in series between the first output node and the discharge node and having gates to receive the corresponding bits !A n and !B n ; and a fifth NMOS transistor coupled between the second output node and an intermediate node between the first and second NMOS transistors having a gate to receive !B n .