Patent ID: 8501543

Claim:
A method for packaging an electronic component comprising: providing a silicon wafer, the silicon wafer having a silicon wafer first surface and a silicon wafer second surface, opposite the silicon wafer first surface; applying a first dielectric layer, the first dielectric layer having a first dielectric layer first surface and a first dielectric layer second surface, opposite the first dielectric layer first surface, the first dielectric layer first surface being applied to the silicon wafer second surface; ablating patterns in the first dielectric layer to create vias extending vertically in the first dielectric layer and trenches extending horizontally in the first dielectric layer; applying a first conductive layer, the first conductive layer having a first conductive layer first surface and a first conductive layer second surface, opposite the first conductive layer first surface, the first conductive layer being applied directly to the first dielectric layer second surface, the first conductive layer completely filling the patterns ablated in the first dielectric layer such that the first conductive layer second surface is at least substantially co-planar with the first dielectric layer second surface to create conductive vias extending vertically in the first dielectric layer and traces extending horizontally in the first dielectric layer; and singulating the silicon wafer with the applied first dielectric layer and the applied first conductive layer into individual packaged electronic components.