Patent ID: 8860218

Claim:
A semiconductor die, comprising a metal stack including a top level metal having a plurality of die pads therein; a passivation layer formed over said top level metal; a first contact stack including: a first die pad from said plurality of die pads, said first die pad having a first pad perimeter; a first via through said passivation layer to said first die pad, said first via having a first via perimeter, and a first under bump metallization (UBM) pad contacting said first die pad through said first via having a first UBM pad perimeter and a first solder bump on said first UBM pad, said first solder bump having a bump diameter and a bump height sized to contact a first level of a multiple bonding level substrate, and a second contact stack, including: a second die pad from said plurality of die pads, said second die pad having a second pad perimeter shorter than said first pad perimeter; a second via through said passivation layer to said second die pad, said second via having a second via perimeter smaller than said first via perimeter, and a second UBM pad contacting said second die pad through said second via having a second UBM pad perimeter that is smaller than said first UBM pad perimeter and a second solder bump on said second UBM pad, said second solder bump having bump diameter and a bump height sized to contact a second level of said multiple bonding level substrate, wherein said semiconductor die is configured to pass a first current through a combination of said first die pad, said first via and said first UBM with a current density below a predetermined threshold current density per perimeter length at said first pad perimeter, at said first via perimeter and at said first UBM pad perimeter, wherein when said first current is passed through a combination of said second die pad, said second via and said second UBM said first current would have exceeded said predetermined threshold current density per perimeter length at said second pad perimeter, at said second via perimeter, and at said second UBM pad perimeter.