Patent ID: 8223107

Claim:
A data driver circuit comprising: a shift register section comprising flip-flops in cascade-connection and configured to shift a pulse signal through said flip-flops in synchronization with a clock signal, the shift register section including said flip-flops grouped in units of N (N is an integer of at least 2) flip-flops into M (M is an integer of 2 ) partial shift registers, and said M partial shift registers are reset in units of partial shift registers in synchronization with the clock signal, the M partial shift registers are connected in cascade; and a control circuit configured to receive a display data in response to the shifted pulse signal from said shift register section and to drive data lines of a display section based on display data to display the display data on the display section, wherein a first one of said M partial shift registers is reset in response to a reset signal, and each of said M partial shift registers other than said first partial shift register is reset in response to supply of the pulse signal or the shifted pulse signal input to one of said M partial shift registers which is directly previous to said partial shift register.