Patent ID: 7179702

Claim:
A method of manufacturing a semiconductor device, comprising: forming an isolation region in a semiconductor substrate to provide an N- and a P-channel MISFET regions each surrounded by the isolation region; forming an insulating film on the semiconductor substrate; forming a conductive film on the insulating film; patterning selectively the conductive film to provide a gate region in each of the MISFET regions; forming source and drain regions in each of the MISFET regions for the patterned conductive film by a self-alignment way; forming a sidewall insulating film around the patterned conductive film; removing the conductive film and the insulating film of the gate region to provide a space region surrounded by the sidewall insulating film; forming a gate insulating film on the N- and P-channel MISFET regions each surrounded by the space region, respectively; forming a first metal silicide film on the gate insulating film within the space region to provide a first gate electrode film; forming a metal film different from metal composing the first metal silicide film on the P-channel MISFET region; and heat-treating the semiconductor substrate to form a second gate electrode film formed by a solid phase reaction between the first metal silicide film and the metal film, the second gate electrode film being composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide.