Patent ID: 7392170

Claim:
A method of simulating a circuit having a hierarchical data structure, comprising: representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph; the hierarchically arranged set of branches including a first branch that includes one or more leaf circuits and a second branch that includes one or more leaf circuits; wherein the first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches; selecting a group of leaf circuits from the first and second branches for simulation; representing the two or more leaf circuits as a merged leaf circuit in response to two or more leaf circuits of the circuit having a substantially same isomorphic behavior; creating a first port connectivity interface dynamically for the group of leaf circuits in response to the merged leaf circuit; wherein the first port connectivity interface communicates changes in signal conditions among the group of leaf circuits; simulating the group of leaf circuits in accordance with the first port connectivity interface; and storing simulation results of the group of leaf circuits in a memory device.