Patent ID: 6906951

Claim:
A memory comprising: a bit line connected to a column of memory cells, each of the memory cells having a threshold voltage in one of a plurality of states that represent data values, the plurality of states including a first state representing a first data value and a second state representing a second data value; a main pull-up device that is connected to the bit line during a read operation; a first reference bit line connected to a first column of reference cells, wherein each of the reference cells in the first column has a threshold voltage that is betweon the first state and the second state; a first pull-up device that is connected to the first reference bit line during the read operation; a second reference bit line connected to a second column of reference cells, each reference cell in the second column having a threshold voltage that is in the first state; a second pull-up device that is connected to the second reference bit line during the read operation, wherein a gate of the second pull-up device is coupled to a source of the second pull-up device and to the gates of the main and first pull-up devices; a plurality of word lines, wherein each word line is coupled to control one of the memory cells and one of the reference cells; and a first sense amplifier coupled to sense a difference between the bit line and the first reference bit line.