Patent ID: 7364969

Claim:
A semiconductor fabrication process, comprising: forming a tunnel dielectric over first and second regions of a semiconductor substrate; forming a charge storage element overlying the tunnel dielectric; removing portions of the tunnel dielectric and the charge storage element overlying the second region; forming a second dielectric overlying the first and second regions; forming a conductive gate electrode layer overlying the second dielectric; patterning the conductive gate electrode layer to form a first gate electrode overlying the first region and a second gate electrode overlying the second region; forming first source/drain regions aligned to the first gate electrode in the first region and second source/drain regions aligned to the second gate electrode in the second region to form a thin film storage device in the first region and a high voltage transistor in the second region, wherein the second dielectric serves as a gate dielectric for the high voltage device and a control oxide for the thin film storage device.