Patent ID: 8640075

Claim:
A computer-implemented method for designing an integrated circuit, the computer-implemented method comprising: receiving, by a processor, a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together; detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises: a source driver having an input source slew that is greater than a source slew limit threshold, wherein the detecting comprises: adding a test buffer at a boundary of the source driver; and determining that the input source slew at the test buffer is greater than the source slew limit threshold; replacing the component with a different component that is independent of the problem, wherein the replacing comprises: asserting a new buffer at an output of the source driver; asserting a slew that is less than the source slew limit threshold for the source driver; and asserting a new arrival time for data at the new buffer that is approximately equal to an arrival time at a driver in the component plus a length of a wire connecting the test buffer and the driver multiplied by a time of flight along the wire for the data between the driver and the test buffer; and testing others components of the number of components based on the different component.