Patent ID: 6999368

Claim:
A semiconductor memory device so configured that by a memory cell array in which a plurality of memory cells each including a capacitor and a transistor are arranged in a matrix, a plurality of word lines connected to ones of the plurality of memory cells arranged in the row direction of the memory cell array, a plurality of bit lines connected to ones of the plurality of memory cells arranged in the column direction of the memory cell array, and a signal from the outside, a read/write can be performed to the plurality of memory cells, the device comprising: a clock oscillator for generating an oscillation clock; a first signal generation circuit for generating, based on the oscillation clock, a refresh request signal; a second signal generation circuit for generating, in response to an access request signal from the outside, a start time detection signal indicating a refresh start possible zone; and a third signal generation circuit for generating, based on the refresh request signal and the start time detection signal, a refresh internal row control signal for performing an internal refresh operation.