Patent ID: 7339279

Claim:
A chip-size package structure, comprising: a base; a die with pads adhered to said base; first conductive lines formed on said die to cover said pads; a first dielectric layer formed on said die and said first conductive lines, and said first dielectric layer having first openings on said first conductive lines; a first material layer formed on said base and filled in a space between said dice on said base; a second dielectric layer formed on said first dielectric layer and said first material layer, and said second dielectric layer having second openings on said first conductive lines; second conductive lines formed on said first openings and said second openings to electrically couple with said first conductive lines, respectively; a second material layer formed on said second conductive lines and said second dielectric layer, and said second material layer having third openings on said second conductive lines; and solder balls welded on said third openings and electrically coupling with said second conductive lines, respectively.