Patent ID: 8737140

Claim:
A semiconductor memory device, comprising: a plurality of strings each configured to comprise a drain select transistor, memory cells, and a source select transistor coupled in series between a bit line and a common source line; and peripheral circuits configured to perform an operation of precharging a bit line so that a precharge level of the bit line varies depending on whether an adjacent unselected memory cell, which is adjacent to a selected memory cell, is in the program state or the erase state, by supplying a first voltage to the adjacent unselected memory cell arranged toward the drain select transistor, a second voltage to remaining memory cells in order to turn on the remaining memory cells, and a third voltage higher than a bit line precharge voltage to the common source line and perform a read operation of supplying a read voltage lower than the second voltage to the selected memory cell, the second voltage to the remaining memory cells including the adjacent unselected memory cell, and a ground voltage to the common source line.