Patent ID: 7154138

Claim:
A transistor arrangement, comprising: a substrate, and a vertical transistor comprising: a first electrode region, a second electrode region arranged generally above the first electrode region, a channel region between the first electrode region and the second electrode region, a gate region beside the channel region, an electrically insulating region at least partly surrounding the gate region such that the gate region is electrically decoupled from adjacent vertical transistors, and an electrically insulating layer sequence between the gate region and the channel region, wherein two mutually spatially separate and electrically decoupled sections of the electrically insulating layer sequence are adapted for storage of charge carriers, and wherein an electrically insulating region at least partly surrounding one or both of the first electrode region and the second electrode region electrically decouples said one or both of the first electrode region and the second electrode region from their surroundings with the exception of the channel region and the electrically insulating layer sequence.