Patent ID: 7906441

Claim:
A method of fabricating a MOS transistor, the method comprising: forming a gate dielectric layer over a substrate in a first chamber coupled to a transfer chamber; transferring said gate dielectric layer to said transfer chamber following said forming of said gate dielectric layer, said transfer chamber being maintained at pressures of about 3 Torr to about 200 Torr while being actively purged with an inert gas; transferring said gate dielectric layer to a second chamber from said transfer chamber, said second chamber being coupled to said transfer chamber, and introducing nitrogen atoms into said gate dielectric layer by subjecting said gate dielectric layer to a plasma process using a plasma formed with power levels between about 2 watts and 3000 watts and at pressures between about 5 mTorr and about 50 Torr; transferring said gate dielectric layer to said transfer chamber following said introducing of nitrogen atoms into said gate dielectric layer, said transfer chamber being maintained at pressures of about 3 Torr to about 200 Torr while being actively purged with an inert gas; transferring said gate dielectric layer to a third chamber from said transfer chamber, said third chamber being coupled to said transfer chamber, and subjecting said gate dielectric layer to a rapid-thermal process; and transferring said gate dielectric layer to said transfer chamber following said rapid-thermal process, said transfer chamber being maintained at pressures of about 3 Torr to about 200 Torr while being actively purged with an inert gas.