Patent ID: 7746694

Claim:
A nonvolatile memory cell integrated circuit, comprising: a nonvolatile memory array including a plurality of columns, each column of the plurality of columns including a plurality of nonvolatile memory cells arranged in a series, such that a subset of nonvolatile memory cells in the series are electrically connected to a bit line via other nonvolatile memory cells in the series, each nonvolatile memory cell of the array including: a charge storage structure storing charge to control a logical state stored by the nonvolatile memory cell integrated circuit; source and drain regions separated by a channel region; one or more dielectric structures at least partly between the charge storage structure and the channel region and at least partly between the charge storage structure and a source of gate voltage, wherein, for each nonvolatile memory cell of the array, an interface separates part of the one or more dielectric structures from the channel region, and a first end of the interface ends at an intermediate part of the source region and a second end of the interface ends at an intermediate part of the drain region.