Patent ID: 6940150

Claim:
A semiconductor wafer device comprising: a semiconductor wafer comprising a circuit area disposed in a central area of said semiconductor wafer and a peripheral area disposed around said circuit area of said semiconductor wafer; a number of semiconductor elements formed in said circuit area; a circuit multi-layer wiring structure formed on said circuit area and comprising multi-layer wirings connected to said semiconductor elements and interlevel insulating films, at least some of said multi-layer wirings being damascene wirings including wiring patterns and via conductors embedded in respective ones of said interlevel insulating films; and a peripheral multi-layer structure formed on said peripheral area, comprising insulating films made of the same layers as said interlevel insulating films and having one or more trenches formed in respective one or ones of said insulating films, each of said trenches having opposing sidewalls and a bottom surface in an associated one of said insulating films, and a conductor pattern filling each of said trenches and made of a same material as said wiring patterns in an associated one of said interlevel insulating films and not having conductor patterns corresponding to said via conductors.