Patent ID: 7526054

Claim:
A method of communicating between an emulator and an evaluation board including a digital circuit comprising: applying a reference clock signal at a predetermined frequency to the digital circuit and a delayed clock circuit; sampling a delayed return data signal from the digital circuit by a delayed reference clock generator; comparing the sampled delayed return data signal to an expected return data signal by the delayed reference clock generator; if the delayed return data signal is equal to the expected return data signal, then using the applied reference clock signal in the digital circuit to communicate between the digital circuit and the emulator; and if the delayed return data signal is not equal to the expected return data signal, then adjusting a delay in the delayed return data signal by varying a delay of the reference clock signal until the delayed return data signal is equal to the expected return data signal, wherein adjusting the delay in the delayed return data signal by varying the delay of the reference clock signal until the delayed return data signal is equal to the expected return data signal comprises: adjusting the reference clock signal using a predetermined amount of time; applying the adjusted reference clock signal to the digital circuit and the delayed clock circuit; sampling the delayed return data signal from the digital circuit by the delayed reference clock generator; comparing the sampled delayed return data signal to the expected return data signal generated by the delayed reference clock generator; if the delayed return data signal is equal to the expected return data signal, then using the applied adjusted reference clock signal in the digital circuit to communicate between the digital circuit and the emulator; if the delayed return data signal is not equal to the expected return data signal, then computing a delay between the reference clock signal and the adjusted reference clock signal; determining that the computed phase delay exceeds a threshold phase delay; if so, then adjusting the reference clock signal by decrementing the reference clock signal using the predetermined amount of time and using the adjusted reference clock signal to communicate between the emulator and the digital circuit; and if not, then repeating the above adjusting, applying, sampling, comparing and determining steps until the delayed return data signal is equal to the expected return data signal and using the adjusted reference clock signal to communicate between the emulator and the digital circuit.