Patent ID: 7106638

Claim:
A memory device, comprising: a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals; at least one memory array, the at least one memory array writing data to and reading data from locations corresponding the address signals responsive to the memory control signals; a data path extending between a plurality of externally accessible data bus terminals and the memory array for coupling data signals to and from the memory array; and an active termination circuit for setting the input impedance of plurality of the externally accessible terminals to a predetermined value, the active termination circuit comprising: a respective first controllable impedance device coupled between a first supply voltage and each of the externally accessible terminals, the impedance of the first controllable impedance device being controlled by an impedance control signal; a second controllable impedance device coupled between a second supply voltage and a feedback node, the second controllable impedance device being a different controllable impedance device from the first controllable impedance devices, and the feedback node being different from one of the externally accessible terminals, the impendace of the second controllable impedance device being controlled by the impedance control signal; a predetermined resistance coupled between the feedback node and a third supply voltage, the second controllable impedance device and the predetermined resistance forming a voltage divider between the second and third supply voltages to produce a feedback voltage at the feedback node; and a circuit generating the impedance control signal as a function of the feedback voltage so that magnitude of the feedback voltage is substantially constant.