Patent ID: 7836221

Claim:
A direct memory access (DMA) system, comprising: at least one read bus having at least a first read port for reading data from a first peripheral device; at least one write bus having at least a first write port for writing data into a second peripheral device; at least one buffer memory bus having at least a second read port and at least a second write port for accessing a buffer memory; and a direct memory access controller, comprising: a plurality of channels electrically connected between the read bus and the memory bus, connected between the write bus and the memory bus, and connected between the read bus and the write bus, wherein a source address and a destination address of data for each channel are assigned by a control table; and a bus arbiter for performing bus arbitration and prioritizing data access among the read bus, the write bus, and the buffer memory bus; wherein reading and writing operations for one DMA transaction are executed by different buses.