Patent ID: 7970980

Claim:
A memory controller for a digital device, comprising: an interface for communicating with a plurality of memory modules embodying an addressable memory; logic receiving memory addresses for processing by said digital device; memory access logic which accesses memory locations in said addressable memory responsive to receiving said memory addresses, said memory access logic supporting a plurality of different configurations of said memory modules embodying said addressable memory and, for each said configuration of said memory modules, decoding a memory address to a plurality of physical parameter selections representing physical parameters of said addressable memory according to a respective corresponding decoding map of a plurality of decoding maps, said plurality of physical parameter selections including a row select and a column select representing a row and column respectively of memory cell arrays in said memory modules embodying said addressable memory; wherein, for a first subset of said plurality of different configurations of said memory modules, said first subset being fewer than all of said plurality of different configurations of said memory modules, said memory access logic produces a decoded selection of a first subset of said plurality of physical parameter selections according to the decoding map corresponding to the configuration, said first subset of physical parameter selections not including said column select, said first subset of physical parameter selections being decoded from at least a portion of said memory address, before said memory access logic produces said column select from at least a portion of said memory address; and wherein, for a second subset of said plurality of different configurations of said memory modules, said second subset being fewer than all of said plurality of different configurations of said memory modules, said first and second subsets of said plurality of different configurations of said memory modules being disjoint, said memory access logic produces a decoded selection of said first subset of said plurality of physical parameter selections according to the decoding map corresponding to the configuration at substantially the same time that said memory access logic produces said column select from at least a portion of said memory address.