Patent ID: 8411804

Claim:
A receiver comprising: a first plurality of delay cells coupled in a series arrangement, wherein each delay cell in the first plurality of delay cells is designed to provide a corresponding delay to a corresponding input signal, the first plurality of delay cells operable to propagate a pulse-width modulated (PWM) signal in a forward direction for a duration of a first interval to generate, at the end of the first interval, a first plurality of delayed signals, wherein the first plurality of delay cells is operable to propagate the first plurality of delayed signals and a logic zero signal in a reverse direction for a duration of a second interval to generate, at the end of the second interval, a second plurality of delayed signals including a feedback signal, wherein the feedback signal is an output of a last delay cell when the first plurality of delay cells is configured in the reverse direction, wherein the logic zero signal is an input to a first delay cell in the series arrangement when the first plurality of delay cells is configured in the reverse direction; and a first flip-flop coupled to receive the feedback signal on a reset terminal, the first flip-flop being coupled to receive the PWM signal on a clock terminal, wherein an output of the first flip-flop at the end of the second interval specifies a value of a data modulated on the PWM signal for an interval from the start of the first interval to the end of the second interval.