Patent ID: 8531246

Claim:
An apparatus comprising: a phase-locked loop (PLL) to generate a PLL output signal; a plurality of interpolative dividers coupled to the PLL output signal and configured to provide respective independent output signals from the plurality of interpolative dividers; wherein each of the interpolative dividers includes, a delta sigma modulator coupled to receive a respective one of a plurality of divide ratios and generate an integer portion and a digital quantization error; a fractional-N divider coupled to the PLL output signal and configured to supply a divided signal based on the PLL output signal and a divide control signal, wherein the divide control signal is determined in accordance with the integer portion; and a phase interpolator coupled to the fractional-N divider and to the delta sigma modulator to adjust a phase of the divided signal according to the digital quantization error to reduce error in the divided signal and supply a respective one of the independent output signals.