Patent ID: 8526567

Claim:
A shift register comprising: a first line; a second line; a third line; a fourth line; a first stage; a second stage; a third stage; and a fourth stage, wherein the first line is configured to supply a first clock signal during a first period and a first constant potential during a second period, wherein the second line is configured to supply a second clock signal that is an inverted clock signal of the first clock signal during the first period and a second constant potential during the second period, wherein the third line is configured to supply a third clock signal during the second period and a third constant potential during the first period, wherein the fourth line is configured to supply a fourth clock signal that is an inverted clock signal of the third clock signal during the second period and a fourth constant potential during the first period, wherein the first stage is electrically connected to the first line such that the first clock signal and the first constant potential are input to the first stage, wherein the second clock signal and the second constant potential are not input to the first stage, wherein an output terminal of the first stage is electrically connected to an input terminal of the second stage, wherein the second stage is electrically connected to the second line such that the second clock signal and the second constant potential are input to the second stage, wherein the first clock signal and the first constant potential are not input to the second stage, wherein an output terminal of the second stage is operationally connected to an input terminal of the third stage, wherein the third stage is electrically connected to the third line such that the third clock signal and the third constant potential are input to the third stage, wherein the fourth clock signal and the fourth constant potential are not input to the third stage, wherein an output terminal of the third stage is electrically connected to an input terminal of the fourth stage, wherein the fourth stage is electrically connected to the fourth line such that the fourth clock signal and the fourth constant potential are input to the fourth stage, and wherein the third clock signal and the third constant potential are not input to the fourth stage.