Patent ID: 7353356

Claim:
A FIFO circuit comprising: a write counter circuit for counting a write clock signal during a valid period of input data, and for outputting a write counter value; a memory circuit for storing the input data in response to the write counter value output from said write counter circuit; an empty address management circuit for deciding whether said memory circuit includes data which has not yet been read out of said memory circuit, in response to the write counter value output from said write counter circuit and in response to a read counter value; a read counter circuit for counting a read clock signal and for outputting the read counter value when said empty address management circuit makes a decision that said memory circuit includes the data which has not yet been read; a selector circuit for selecting and reading data from said memory circuit in response to the read counter value output from said read counter circuit; a write pulse generating circuit for converting the write counter value output from said write counter circuit into write pulses, wherein said memory circuit stores the input data in response to the write pulses output from said write pulse generating circuit; and a delay circuit for delaying the input data to synchronize the input data with the write pulses, and for supplying the delayed input data to said memory circuit.