Patent ID: 7484078

Claim:
A data processing circuit with a pipelined asynchronous instruction processor, the data processing circuit comprising a register file with a write port; a pipeline of instruction processing stages a first and a second one of the stages that are in series in the pipeline each having a result output for writing a result to the write port, if instruction dependent information in the stage concerned requires writing; a timing circuit arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective stages partially overlaps; a write sequencing circuit arranged to perform write tests alternately for instruction dependent information in the first and second one of the stages the write sequencing circuit when performing the write test for a particular one of the stages testing whether the instruction dependent information in the particular one of the stages requires writing of a result, and, if so, delaying transfer of new instruction dependent information through the pipeline to the particular one of the stages until the write port has been committed to writing the result before results that the write port may subsequently be committed to write.