Patent ID: 7073111

Claim:
A test access port comprising: a test clock input; a test mode select input; a test data in input; a test data out output; a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, and a Shift-DR signal, and having a control bus input; an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output; a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the Update-DR signal and the Shift-DR signal, the boundary scan register having a modified Clock-DR input; a delay circuit connected to the test clock input and having a delayed clock output; and propagation test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, and the modified Clock-DR input to test the propagation of functional signals received by the boundary scan register.