Patent ID: 7808754

Claim:
A hybrid protection circuit, comprising: a stress detection circuit between a power supply voltage and a ground voltage, the stress detection circuit configured to output a detection signal that is activated when a positive electrostatic discharge (ESD) event or a positive electrical over-stress (EOS) event occurs; a clamp device between the power supply voltage and the ground voltage, the clamp device configured to discharge first charges generated by a negative ESD event or a negative EOS event when the negative ESD event or the negative EOS event occurs and configured to discharge second charges generated by the positive ESD event or the positive EOS event in response to a clamping signal activated when the positive ESD event or the positive EOS event occurs; and an on-time adjustment circuit between the power supply voltage and the ground voltage, the on-time adjustment circuit configured to receive the detection signal, configured to output the clamping signal, and configured to maintain the clamping signal in an active state until the second charges generated by the positive ESD event or the positive EOS event are discharged, wherein the on-time adjustment circuit includes a first feedback circuit and a second feedback circuit connected in series with respect to each other, an output of the second feedback circuit is connected to a control input of the clamp device, the first feedback circuit includes: a first inverter configured to invert the detection signal; a second inverter configured to invert a first output signal of the first inverter; and a first feedback transistor configured to bias a second output signal of the second inverter to the first inverter, and the second feedback circuit includes: a third inverter configured to invert the second output signal; a fourth inverter configured to invert a third output signal of the third inverter to generate the output of the second feedback circuit, as the clamping signal; and a second feedback transistor configured to bias the clamping signal to the third inverter.