Patent ID: 8895387

Claim:
A method of manufacturing a nonvolatile semiconductor memory device, the method comprising: forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer; implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask; forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns; forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern; forming a metal layer on the second insulating layer in the first concave portion and on the first insulating layer in the second concave portion; and executing a heat treatment to activate the impurities, before forming the metal layer and after the ion implantation.