Patent ID: 8043974

Claim:
A method of forming an interconnection structure, comprising: providing a semiconductor substrate having opposite main and back surfaces, and a side surface extending between the main surface to the back surface; forming a first insulating layer on the semiconductor substrate, wherein the first insulating layer is located over the main, back and side surfaces of the semiconductor substrate; forming a second insulating over the first insulating layer, wherein the second insulating layer is located over the main and side surfaces of the semiconductor substrate; sequentially forming first and second metal layers over second insulating layer, wherein the first metal layer is located over the main and side surfaces of the semiconductor substrate, and the second metal layer is located over the main surface of the semiconductor substrate; and performing a semiconductor wet etching process onto the first metal layer and the first and second insulating layers, wherein the semiconductor wet etching process is performed using a semiconductor wet etchant comprising a mixture of deionized water, a fluorine-based compound, an oxidizer and an inorganic salt, wherein a concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant, and wherein the inorganic salt comprises at least one of an ammonium ion (NH 4 + ) and a chlorine ion (Cl − ).