Patent ID: 8822252

Claim:
A method of fabricating electrical connections in an integrated MEMS device comprising: forming a MEMS wafer comprising: forming one or more cavities in a first semiconductor layer; bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer; etching at least one via through the second semiconductor layer and the dielectric layer; depositing a conductive material on the second semiconductor layer and filling the at least one via; patterning and etching the conductive material to form at least one standoff; depositing a germanium layer on the conductive material; patterning and etching the germanium layer; patterning and etching the second semiconductor layer to define one or more MEMS structures; and bonding the MEMS wafer to a base substrate using a eutectic bond between the germanium layer on the one or more standoffs and aluminum pads of the base substrate.