Patent ID: 7970979

Claim:
A field programmable gate array (FPGA) integrated circuit, comprising: a logic and routing block having a plurality of dedicated logic cells, each dedicated logic cell having a first logic and routing cell and a second logic and routing cell; a plurality of configurable dedicated connection circuits, the plurality of configurable dedicated connection circuits being interconnected with one another through bus-based connections to form a bus architecture, each configurable dedicated connection circuit having a plurality of bus-based inputs, a plurality of bus-based outputs, and a multiplexer, the multiplexer having configuration bits for routing a first bus-based input in the plurality of bus-based inputs via a first bus to a first bus-based output in the plurality of bus-based outputs, each configurable dedicated connection circuit being directly connected to only one signal processing unit; one or more first dedicated lines connecting from the first logic and routing cell in a dedicated logic cell of the logic and routing block to the first bus-based input in a first configurable dedicated connection circuit; and one or more second dedicated lines connecting from the first bus-based output in the first configurable dedicated connection circuit to the first logic and routing cell in the dedicated logic cell of the logic and routing block.