Patent ID: 7786586

Claim:
An apparatus comprising: a semiconductor substrate formed with a sub-structure; at least one metal line layer formed over the semiconductor substrate, the at least one metal layer including a lower metal line layer formed over the semiconductor layer and an upper metal line layer formed over the lower metal line layer; at least one inductor line layer formed over the metal line layer; and a space layer formed between the inductor line layer and the semiconductor substrate, wherein the lower metal line layer includes a lower insulating film formed over an entire upper surface of the semiconductor substrate, a lower hole formed on a first side of the lower insulating film, a lower photoresist layer formed in the lower hole, a lower silylation film formed over the lower photoresist layer, a lower via hole formed on a second side of the lower insulating film, and a lower metal line buried in the lower via hole, wherein the upper metal line layer includes an upper insulating film formed over an entire upper surface of the lower insulating film including the lower silylation film and the lower metal line, an upper hole formed in a first side of the upper insulating film to expose the lower photoresist layer, an upper photoresist layer formed in the upper hole, an upper silylation film formed over the upper photoresist layer, an upper via hole formed in a second side of the upper insulating film, and an upper metal line buried in the upper via hole.