Patent ID: 7954040

Claim:
An encoding apparatus for encoding a codeword to obtain a corresponding parity code, the parity code being embedded in the codeword and dividing the codeword to have intermediate symbol locations between a first and a second set of data symbols, each data symbol forming a coefficient, the first set of data symbols, the second set of data symbols, and the parity code respectively forming a first polynomial (M 1 (x)), a second polynomial (M 2 ( x )), and a parity code polynomial (R(x)), the encoding apparatus comprising: a timing controller for issuing a timing controlling signal to control operations of the encoding apparatus; a plurality of multipliers, each multiplier being used for multiplying an input with a predetermined stored coefficient to obtain a corresponding output, multiple stages of serially-cascaded registers, each stage of registers being used for temporarily storing a registered data in the register of said stage and updating the registered data according to the timing controlling signal; and a plurality of adders, each adder being used for adding an output of the multiplier with the registered data in the register of the previous stage, each stage of registers being used for temporarily storing an output of a corresponding adder to generate the registered data in the register of said stage; wherein, the adders store a plurality of coefficients of a first code generator polynomial (G 1 ( x )) in advance, and sequentially accepting the plural coefficients of the first polynomial (M 1 ( x )) from high order terms to low order terms as the inputs of the adders according to the timing controlling signal, so as to obtain a plurality of coefficients of a first remainder polynomial (R 1 ( x )); and wherein the multipliers store a plurality of coefficients of a second code generator polynomial (G 2 ( x )), the second code generator polynomial (G 2 ( x )) being generated from the first code generator polynomial (G 1 ( x )) via a predetermined reciprocal substitution procedure; and wherein the multipliers sequentially accept the plurality of coefficients of the second polynomial (M 2 ( x )) from low order terms to high order terms as the inputs of the multipliers according to the timing controlling signal, so as to obtain a plurality of coefficients of a second remainder polynomial (R 2 ( x )); and wherein finally, the coefficient of each term of the parity code polynomial (R(x)), therefore the parity code, is obtained by performing an adding procedure on the first remainder polynomial (R 1 ( x )) and the second remainder polynomial (R 2 ( x )).