Patent ID: 7618492

Claim:
A method of manufacturing a flash memory cell, the method comprising: providing a workpiece, the workpiece comprising a first region and a second region; disposing a tunnel dielectric material over the workpiece; forming a masking material over the tunnel dielectric material over the second region of the workpiece, leaving the tunnel dielectric material over the first region of the workpiece exposed; exposing the tunnel dielectric material over the first region of the workpiece to a first substance, forming a plurality of nanocrystal formation locations on the tunnel dielectric material over the first region; exposing the tunnel dielectric material over the first region of the workpiece to at least one second substance, selectively forming a nanocrystal at each of the plurality of nanocrystal formation locations on the tunnel dielectric material, while at a same time not forming nanocrystals on or over the masking material; removing the masking material; forming a dielectric material over the nanocrystals in the first region of the workpiece; and forming a gate material over the dielectric material in the first region of the workpiece.