Patent ID: 7508895

Claim:
An oversampling apparatus for oversampling decoded data on a frame by frame basis at an oversampling ratio of α, and outputting the oversampled data on a frame by frame basis, the oversampling apparatus comprising: an output buffer that has a memory capacity α+1 times as much as one frame of the decoded data, such that the output buffer is divided into memory areas 1 , 2 , . . . , α and α+1 in ascending order of addresses for use; a first portion that operates during a first time slot sharing (α−1)/α of a time length of a current frame N for writing decoded data of the current frame N into the memory area α+1, and for allowing the output buffer to output a first part of oversampled data of a preceding frame N−1 which has been previously written in the memory areas 1 to α−1 so that the memory areas 1 to α−1 are made free; a second portion that operates during a second time slot sharing 1/α of the time length of the current frame N for reading the decoded data of the current frame N written in the memory area α+1 of the output buffer so that the memory area α+1 is made free and the read data of the current frame N is oversampled, and writing the oversampled data of the current frame N into the free memory area α+1 and the free memory areas 1 to α−1, and further allowing the output buffer to output a second part of the oversampled data of the preceding frame N−1 which has been previously written in the memory area α, so that the memory area α is made free for writing of decoded data of a succeeding frame N+1; and a third portion that controls the output buffer to shift the addresses of the memory areas 1 to α+1 in cyclic manner while the first and second portions sequentially repeat writing and reading of the decoded data, writing of the oversampled data, and outputting of the oversampled data from the output buffer with respect to the succeeding frames N+1, N+2, and so on.