Patent ID: 7687860

Claim:
A semiconductor device comprising: a first gate formed on an active region of a substrate, wherein the active region is defined by device isolation layer patterns; a first insulating layer formed between the first gate and the active region; and first and second impurity regions formed on the active region on both sides of the first gate, wherein a first portion of the first gate adjacent to the first impurity region is different in cross-sectional shape from a second portion of the first gate adjacent to the second impurity region, wherein respective cross-sectional shapes of the first and second portions are defined by cross-sectional lines running between the first and second impurity regions and immediately adjacent thereto in a word line direction in the device; wherein the first portion of the first gate has substantially an inverted T-shaped section and the second portion of the first gate has a box-shaped section when taken along a direction crossing the active region and the device isolation layer patterns; wherein the first impurity region is lower in concentration than the second impurity region.