Patent ID: 8318543

Claim:
A method of manufacturing a semiconductor device, comprising the following steps in order: (a) bonding a first terminal surface of a first terminal of a first chip and a second terminal surface of a second terminal of a second chip onto a surface of a first bonding layer provided on a flat face of a first support so that the first terminal surface and the second terminal surface are aligned with each other; (b) preparing a second support having a second bonding layer formed thereon and then bonding the second support onto a first back face of the first chip and a second back face of the second chip through the second bonding layer, the second bonding layer covering the first and second back faces of the first and second chips so as to absorb a difference in height between the first and second chips; (c) peeling the first support from the first and second chips to expose the first and second terminal surfaces of the first and second chips in a same plane in alignment with each other; (d) forming, on the second support, an insulating layer so as to cover the first and second terminal surfaces and at least part of side surfaces of the first and second chips; (e) forming an opening in the insulating layer from which at least one of the first and second terminal surfaces of the first and second chips is exposed; and (f) forming a wiring which is connected to at least one of the first and second terminal surfaces through the opening in the insulating layer.