Patent ID: 8015336

Claim:
A semiconductor device comprising: a plurality of slave blocks; a master block controlling the slave blocks; a bidirectional bus connected between the master block and each of the slave blocks to transmit data therebetween; a unidirectional bus connected between the master block and each of the slave blocks, said unidirectional bus accommodating the transmission of control signals generated in the master block to the slave blocks wherein the master block detects a propagation delay time between the master block and the slave blocks, wherein a selected slave block of the plurality of slave blocks transmits an allocated symbol to the master block via the bidirectional bus, the master block counts a number of clocks between a time when the selected slave block transmits the allocated symbol and a time when the allocated symbol reaches the master block, such that the propagation delay time between the master block and the selected slave block is detected, and stores the detected propagation delay time, and wherein the master block transmits data to the selected slave block via the bidirectional bus, and thereafter generates an enable signal and transmits the enable signal to the selected slave block via the unidirectional bus, wherein a delay time between transmission of the data and transmission of the enable signal is equivalent to the detected propagation delay time for the selected slave block.