Patent ID: 7550324

Claim:
A method for manufacturing a programmable logic device (PLD), comprising: creating circuitry of at least one wafer, the circuitry arranged in a plurality of integrated circuits in the at least one wafer, one of the integrated circuits having a portion of the circuitry that includes an array of programmable tiles, a set of electrically programmable fuses, and a plurality of programming pads for the set of electrically programmable fuses, wherein the programmable tiles include a plurality of programmable logic resources and a plurality of programmable interconnect resources, and a subset of the programmable tiles is coupled to the set of electrically programmable fuses by an interface port that includes a control port and a serial input and serial output signals; programming the set of electrically programmable fuses with an identifier of the integrated circuit using the programming pads, the identifier including a specification of a lot including the at least one wafer, a specification of a wafer for the integrated circuit in the lot, and a specification of a location of the integrated circuit in the wafer, wherein the integrated circuit supplies the identifier from the set of electrically programmable fuses via the serial output signal of the interface port in response to a sequence of shift commands being provided to the control port of the interface port; and mounting the integrated circuit in a package that does not have external pins for at least one of the programming pads.