Patent ID: 6982902

Claim:
An array of magnetoresistive random access memory (MRAM) cells disposed on a substrate at intersections of local bit lines and global word lines, comprising: a plurality of local bit lines, each local bit line electrically coupled to at least one MRAM cell; a plurality of switches, each switch selectively connecting a global bit line to at least one local bit line; and a plurality of select lines, each select line having a first terminal coupled to a control input of one of the switches and a second terminal coupled to a controller of read and write operations of an MRAM device comprising at least one said arrays wherein the local bit lines comprise stacked local bit lines electrically cooled to each other and to the switch selectively connecting the stacked local bit lines to the global bit line, one stacked bit line is magnetically coupled to the global bit line, and the remaining stacked local bit lines are each magnetically coupled to a separate global bit line of the MRAM device.