Patent ID: 6972248

Claim:
A method of fabricating a semiconductor device, comprising the steps of: providing a substrate having a first region and a second region; forming a plurality of stack gate structures on the first region and the second region of the substrate, wherein each stack gate structure comprises a gate dielectric layer a gate dielectric layer next to the substrate, a gate conductive layer in the middle and a cap layer on top; forming a spacer on each side of the stack gate structure; forming a plurality of conductive regions in the substrate between the stack gate structures; forming a first dielectric layer over the substrate, wherein the top surface of the first dielectric layer exposes the cap layers; forming a buffer layer over the substrate within the first region to cover the first dielectric layer and the cap layers; removing a portion of the cap layers of the stack gate structure within the second region so that the cap layers within the second region have a thickness smaller than or equal to the buffer layer; forming a second dielectric layer over the first region and the second region of the substrate; forming a first mask layer over the second dielectric layer, wherein the first mask layer having: a plurality of first openings within the first region formed above various conductive regions; and a plurality of second openings with the second region formed above various cap layers of the stack gate structures; removing the second dielectric layer and its underlying buffer layer as well as cap layers within the first opening and the first dielectric layer within the second openings to form a plurality of first contact openings and a plurality of second contact openings respectively, wherein the first contact openings expose various conductive regions within the first region and the second contact openings expose various gate conductive layers of the stack gate structures within the second region; and removing the first mask layer.