Patent ID: 7588973

Claim:
A method of manufacturing a semiconductor device comprising: forming a laminated film structure on a semiconductor substrate, by laminating a buried insulating film, a single crystalline semiconductor layer, a first insulating film subsequently in this order on the semiconductor substrate; etching the first insulating film and the single crystalline semiconductor layer to form a plurality of separated film-laminates formed of the single crystalline semiconductor layer and the first insulating film on the buried insulating film; forming a second insulating film on the laminated film structure to cover the film-laminates; flattening the second insulating film until a height of the second insulating film from the semiconductor substrate becomes the same as that of the first insulating film to form an element isolation region; etching the first insulating film of at least a first one of the film-laminates to expose the single crystalline semiconductor layer under the first insulating film of said at least a first one of the film-laminates; forming a MOS transistor on the exposed single crystalline semiconductor layer of said at least first one of the film-laminates; etching the first insulating film of at least a second one of the film-laminates to expose the single crystalline semiconductor layer under the first insulating film of said at least a second one of the film-laminates; depositing single crystalline semiconductor layers of a predetermined thickness on the single crystalline semiconductor layers having the MOS transistor formed thereon of said at least a first one of the film-laminates and on the exposed single crystal semiconductor layer of said at least a second one of the film-laminates; and forming a bipolar transistor on the deposited single crystalline semiconductor layer on the exposed single crystal semiconductor layer of said at least a second one of the film-laminates.