Patent ID: 7045423

Claim:
A method for fabricating a semiconductor device, comprising: implanting impurities of a first conductivity in a surface of a semiconductor substrate at a first concentration; forming a gate insulating film on the surface of the semiconductor substrate; forming a charge storage layer on the gate insulating film; forming a element isolation region in the semiconductor substrate and the gate insulating film; forming an inter-gate insulating film on the element isolation region and the charge storage layer; forming on the inter-gate insulating film a mask material having an opening portion which exposes at least a part of a surface of the inter-gate insulating film; implanting impurities of the first conductivity type in the semiconductor substrate via the opening portion in the mask material at a second concentration higher than the first concentration; removing the inter-gate insulating film that is exposed to the opening portion in the mask material; forming a control gate electrode on the inter-gate insulating film, the control gate electrode being connected to the charge storage layer via a region where the inter-gate insulating film has been removed; forming a stacked gate electrode by patterning the charge storage layer, the inter-gate insulating film and the control gate electrode; and forming source and drain regions by implanting impurities of a second conductivity type in the semiconductor substrate around the gate electrode.