Patent ID: 7352602

Claim:
A memory device comprising: a first die comprising: a first circuit configured to be enabled by a first control signal; a first input pin configured to receive the first control signal; and a first path selector arranged between the first input pin and the first circuit and configured to select a first signal path to the first circuit from the first input pin; and a second die comprising: a second circuit configured to be enabled by a second control signal; a second input pin configured to receive the second control signal; and a second path selector arranged between the second input pin and the second circuit and configured to select a second signal path to the second circuit from the second input pin, wherein the first die and the second die form a stack such that a signal may be routed though each of the first signal path and the second signal path in a direction perpendicular to a surface of the first die and a surface of the second die, wherein the surface of the second die is disposed parallel to the surface of the first die.