Patent ID: 7173877

Claim:
A memory system, comprising: at least one memory device; a memory controller configured to control operation of the at least one memory device; a first clock line extending from a write clock output of the memory controller to a clock port of the at least one memory device to provide a clock signal to the at least one memory device; a second clock line extending from the clock port of the at least one memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to the read clock input of the memory controller; and a synchronization circuit, disposed in the at least one memory device, configured to receive the clock signal from the memory controller and to synchronize output data to the clock signal being forwarded back to the memory controller; wherein the synchronization circuit is configured to synchronize the output data to the received clock signal such that the output data is output from a data output of the memory device synchronized to the received clock signal.