Patent ID: 7023088

Claim:
A semiconductor package, comprising: an insulating layer formed on a wafer that is provided with an electrode; an opening portion made in a region conformable to said electrode in said insulating layer; a rerouting layer connected to said electrode through said opening portion; a sealing resin layer which seals said wafer, said insulating layer, and said rerouting layer; and posts penetrating through said sealing resin layer, a solder bump being formed on each of upper surfaces of said posts; wherein each of said posts comprises: a resin projection portion formed on said insulating layer separated from other resin projections of other posts; and a conductive layer that coats at least an upper surface of said resin projection portion and connected to said rerouting layer and said solder bump; and wherein a boundary between each of said posts and said sealing resin layer is present outside said upper surface of said posts as is viewed in plan.