Patent ID: 8031001

Claim:
A differential amplifier comprising: a main differential amplifier circuit that receives a pair of input signals and supplies a pair of output signals based on a difference between the input signals; and a bias control differential amplifier circuit that receives the pair of output signals and controls a control terminal of the current-limiting transistor based on an offset voltage included in the output signals so as to reduce the offset voltage, wherein the main differential amplifier circuit includes: a current-limiting transistor; a first input transistor that is connected between a common node point and the first output terminal, a control terminal of the first input transistor being connected to the first input terminal; a second input transistor that is connected between the common node point and the second output terminal, a control terminal of the second input transistor being connected to the second input terminal; and the current-limiting transistor that is connected between the common node point and a first power supply line, a control terminal of the current-limiting transistor receiving output of the bias control differential amplifier circuit, and wherein the bias control differential amplifier circuit includes: a third transistor that is connected between a second power supply line and a first node point, a control terminal of the third transistor being connected to the first output terminal; a fourth transistor that is connected between the first node point and a first power supply line, a control terminal of the fourth transistor being connected to the first node point; a fifth transistor that is connected between the second power supply line and the control terminal of the current-limiting transistor, a control terminal of the fifth transistor being connected to the second output terminal; and a sixth transistor that is connected between the control terminal of the current-limiting transistor and the first power supply line, a control terminal of the sixth transistor being connected to the first node point.