Patent ID: 6940743

Claim:
A semiconductor memory device, comprising: a memory cell array having at least first and second memory cells and at least one word line, the first memory cell having an associated first bit line and an associated first complementary bit line and the second memory cell having an associated second bit line and an associated second complementary bit line; a reference cell array having an associated reference word line and a reference cell, wherein the reference cell includes a first capacitor that is coupled to a first supply voltage, a first transistor having a control terminal that is coupled to the reference word line and a second transistor having a control terminal that is coupled to the reference word line, wherein the first capacitor is coupled to the first complementary bit line through the first transistor and that is coupled to the second complimentary bit line through the second transistor; and at least one sense amplifier that is associated with the first memory cell and that is configured to sense and amplify the voltage difference between a signal on the first bit line and a signal on the first complementary bit line.