Patent ID: 7906849

Claim:
A chip comprising: a silicon substrate; a transistor in or on said silicon substrate; a first copper layer over said silicon substrate; a second copper layer over said first copper layer and over said silicon substrate; a dielectric layer between said first and second copper layers; a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers; a first conductive pad over said silicon substrate; a second conductive pad over said silicon substrate; a passivation layer over said first and second copper layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first conductive pad, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers, and wherein a second opening in said passivation layer is over a second contact point of said second conductive pad, and said second contact point is at a bottom of said second opening; a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first contact point, and a fourth opening in said first polymer layer is over said second contact point, wherein said first polymer layer has a thickness between 1 and 100 micrometers; and a metallization structure on said first polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said metallization structure, wherein said metallization structure comprises a titanium-containing layer on said first polymer layer and an electroplated copper layer over said titanium-containing layer, wherein said electroplated copper layer has a sidewall not covered by said titanium-containing layer.