Patent ID: 8232941

Claim:
A liquid crystal display (LCD) device having a plurality of display rows, a plurality of display columns, and a plurality of pixels, where said pixels are defined by the display rows and the display columns, the LCD device further comprising: a timing controller configured to generate a gate driving circuit output enabling signal and a gate driving circuit clocking signal, the timing controller being further configured to variably adjust a timing of a data load signal output thereby, where the data load signal determines a timing point when display data signals will be output for the display columns of a correspondingly activated display row; a level shifter, operatively coupled to the timing controller and configured to generate gate driving circuit clock pulses in response to the output enabling signal and the gate driving circuit clocking signal generated by the timing controller; a gate driving circuit, responsive to the gate driving circuit clock pulses of the level shifter and configured to sequentially activate the display rows one after the next by sequentially activating a plurality of gate lines one after the next, by generating a first gate driving signal in response to the gate driving circuit clock pulses generated by the level shifter, said gate driving circuit including a shift register having a plurality of stages which are dependently connected to each other; and a clipping unit, operatively interposed between the gate driving circuit and the timing controller, the clipping unit being configured to provide the timing controller with a second gate driving signal generated by clipping the first gate driving signal in response to the to-be-clipped first gate driving signal being output from a last stage of the gate driving circuit, wherein the timing controller is configured to variably adjust the timing of the data load signal by measuring and calculating a delay time associated with the first gate driving signal that is output from the last stage of the gate driving circuit by comparing a timing of the second gate driving signal with a timing of the output enabling signal, wherein the gate driving circuit is configured to operate in accordance with a first digital signaling range having a predetermined gate-on voltage level and a predetermined gate-off voltage level, wherein the level shifter is configured to generate the gate driving circuit clock pulses also in accordance with the first digital signaling range having the gate-on voltage level and the gate-off voltage level, wherein the level shifter is further configured to generate gate driving circuit clock bar pulses in accordance with the first digital signaling range, where the clock bar pulses have an inverted phase with respect to a phase of the gate driving circuit clock pulses, and wherein the first gate driving signal comprises a reset signal for resetting the gate driving circuit.