Patent ID: 6890830

Claim:
A method for fabricating a semiconductor device comprising: a first step of forming a first interconnect pattern forming layer from a conducting film on a semiconductor substrate and a first insulating film on said first interconnect pattern forming layer; a second step of forming a plug electrically connected to said first interconnect pattern forming layer by forming an opening in said first insulating film by selective etching and filling said opening with a conducting film; a third step of forming a resist pattern corresponding to a first interconnect pattern including a dummy pattern from a resist film applied over said semiconductor substrate including said plug; a fourth step of patterning said first insulating film by etching said first insulating film with said resist pattern and said plug used as a mask; a fifth step of forming, from said first interconnect pattern forming layer, said first interconnect pattern and said dummy pattern that is electrically insulated from said first interconnect pattern and includes a plurality of fine patterns adjacent to each other by etching said first interconnect pattern forming layer with said resist pattern and said plug used as a mask; a sixth step of forming, on said semiconductor substrate, a second insulating film covering said plug, said first interconnect pattern and said dummy pattern so as to form air gaps between patterns of said first interconnect pattern and between said line patterns of said dummy pattern; and a seventh step of planarizing a top face of said second insulating film until said plug is exposed and forming, on said second insulating film, a second interconnect pattern electrically connected to said plug after planarization.