Patent ID: 7479701

Claim:
A semiconductor structure, comprising: a first rigid dielectric layer; a second rigid dielectric layer; a first non-rigid low-k dielectric layer formed between the first and second rigid dielectric layer; a plurality of dummy fill shapes formed in the first non-rigid layer which replace portions of the first non-rigid low-k dielectric layer with lower coefficient of thermal expansion (CTE) metal such that an overall CTE of the first non-rigid low-k dielectric layer and the plurality of dummy fill shapes matches a CTE of the first and second rigid dielectric layers more closely than that of the first non-rigid low-k dielectric layer alone; and an interconnect arranged on the first non-rigid low-k dielectric layer, wherein the dummy fill shapes surround the interconnect and are aligned with one another in rows and columns, wherein the dummy fill shapes physically connect together the first and second rigid dielectric layers and have a density of approximately between 45% and 50% of a density of the first non-rigid low-k dielectric layer.