Patent ID: 8139051

Claim:
A driving circuit, comprising: odd-numbered and even-numbered pixel cells arranged in a matrix of rows and columns; odd-numbered data lines and even-numbered data lines alternately disposed in parallel with each other and the columns; odd-number gate lines and even-numbered gate lines disposed in parallel with each other and at right angles to the data lines so as to be electrically insulated from said data lines, the gate lines disposed in pairs of one odd-numbered gate line and one even-numbered gate line; a gate line driving circuit for driving the odd-numbered gate lines and the even-numbered gate lines independently of each other; a data line driving circuit coupled to first ends of the data lines for driving the odd-number data lines and the even-numbered gate line independently of each other; and a detection circuit coupled to second ends of the data lines to receive signals from the data lines, the detection circuit including (1) inputting means for applying a signal having a predetermined potential to each of the odd-numbered gate lines and the even-numbered gate lines, the inputting means comprising a switch coupled between the odd-numbered and even-numbered data lines (2) a control circuit coupled to the inputting means to control same, and (3) comparing means for comparing potentials of each adjacent odd-numbered data line and even-numbered data line with each other, and outputting a comparison result, wherein, (a) each odd-numbered pixel cell is connected to an odd-numbered data line and an odd-numbered gate line, and each even-numbered pixel cell is connected to an even-numbered data line and an even-numbered gate line, the odd-numbered pixel cells of a given row being connected to the same odd-numbered gate line and respective odd-numbered data lines, the even-numbered pixel cells of a given row being connected to the same even-numbered gate line and respective data lines, the pixel cells of a given column being connected to the same data line; (b) each of the pixel cells includes (i) accumulating means for accumulating therein charges based on a potential of a signal corresponding to pixel data input through corresponding one of the data lines connected thereto, and (ii) connecting means for connecting the corresponding one of the data lines connected thereto and the accumulating section to each other based on a potential of the corresponding one of the data lines connected thereto; and (c) said data lines, said gate lines, said pixel cells, said gate line driving circuit, said data line driving circuit, said inputting means, and said comparing means are disposed either on one semiconductor substrate or on one insulating substrate.