Patent ID: 7253088

Claim:
A process comprising: mating a microelectronic die substrate to a board, wherein the substrate includes an upper surface, a lower surface, and a solder first bump disposed on the lower surface, wherein the solder first bump is selected from: 36%≦indium≦63%; 28%≦tin≦48%; and 2%≦bismuth 26%; 42%≦bismuth≦62%; 19%≦tin≦42%; and 7%≦indium 28%; 33%≦indium≦67%; 32%≦bismuth≦67%; and 0.1%≦tin≦20%; 52%≦indium≦54% indium; 0.01%≦zinc≦2%; and 46%≦tin≦48%; or 33%≦indium≦67%; 32%≦bismuth≦67%; and 0.1%≦zinc≦1%; and forming a stress-compensation collar (SCC) on the board during mating the die and the board, wherein the SCC abuts the solder first bump.