Patent ID: 6859070

Claim:
A semiconductor integrated circuit device comprising: a plurality of flip-flops cascade-connected by having data output terminals respectively connected to data input terminals of the next-stage flip-flops and each having a data input terminal for scan test and a data output terminal for scan test, each of the plurality of flip-flops including a first clocked inverter having an input terminal connected to the data input terminal and operated in response to a first clock signal, a second clocked inverter having an input terminal connected to the data input terminal for scan test and an output terminal connected to an output terminal of the first clocked inverter and operated in response to a second clock signal, a latch circuit connected to the output terminals of the first and second clocked inverters, a first inverter having an input terminal connected to the output terminals of the first and second clocked inverters and an output terminal connected to the data output terminal, and a second inverter having an input terminal connected to the output terminals of the first and second clocked inverters and an output terminal connected to the data output terminal for scan test, wherein a reset signal is input via the data input terminal for scan test of the first stage flip-flop among the plurality of flip-flops and sequentially transferred from the data output terminal for scan test to the succeeding-stage flip-flops via a transmission path different from a data transmission path.