Patent ID: 7400391

Claim:
A system for identifying systematic yield losses, the system comprising: a device configured to test produced products using a test sequence, said test producing yield data related to a wafer, said wafer being divided into multiple zones, each said zone containing a number of individual chips, each individual chip being in multiple zones; a device configured to calculate and store for each zone of said wafer a first data series R 1 , wherein each element of said first series is the yield of a said zone of said wafer for each tested wafer of the same size; a device configured to calculate and store for each element of data series R 1 a second data series R 2 , wherein each element of said second series is a p consecutive element moving average of data series R 1 ; a device configured to calculate and store for each element of data series R 1 a third data series R 3 , wherein each element of said third data series is a p consecutive element moving standard deviation of data series R 1 ; a device configured to calculate for each element of data series R 1 a trigger point, wherein said trigger point is calculated as the respective data series R 2 element less an adjusted respective data series R 3 value; and a device configured to trigger a notification when the trigger point calculated for each element of data series R 1 is greater than the respective element of data series R 1 , wherein the yield of a zone is the number of acceptable individual chips divided by the total number of chips in said zone.