Patent ID: 7227086

Claim:
A semiconductor chip package comprising: a first semiconductor chip having a first surface and an active surface opposite the first surface with chip pads arrayed within a perimeter of the active surface; a second semiconductor chip having a first surface and an active surface opposite the first surface with chip pads arrayed within a perimeter of the active surface; a mounting means having a mounting region to which the first surface of the first semiconductor chip is affixed and mount pads arrayed on the mounting means; bonding wires providing electrical connections between chip pads and mount pads, an upper portion of the bonding wires extending from the chip pads and above and across peripheral regions of the active surfaces; a first adhesive tape attached to the active surface of the first semiconductor chip and to the upper portion of the bonding wires attached to the chip pads arrayed on the active surface of the first semiconductor chip, the first adhesive tape being also attached to the first surface of the second semiconductor chip; and a second adhesive tape attached to the active surface of the second semiconductor chip and substantially encapsulating the upper portion of the bonding wires attached to the chip pads arrayed on the active surface of the second semiconductor chip; wherein at least one of the first adhesive tape and the second adhesive tape is larger than at least one of the active surface of the first semiconductor chip and the active surface of the second semiconductor chip.