Patent ID: 7493505

Claim:
A processing system with a suspend mode of operation to allow low power operation, the processing system operable to receive power across positive and negative terminals, comprising: an instruction based digital processing block; a clock section for generating a system clock for clocking said digital processing block; an internal voltage generator for decreasing the voltage across the digital processing block in a suspend mode of operation; and a mode controller for controlling said internal voltage generator to operate in a full power mode of operation wherein the power across said digital processing block is substantially equal to the voltage across the positive and negative terminals, and in the suspend mode of operation to reduce the voltage across said digital processing block to less than the voltage across the positive and negative terminals; wherein said digital processing block is disposed between internal positive and negative terminals associated with the positive and negative terminals, respectively, and at least one of said internal positive and negative terminals is isolated from the associated one of the positive and negative terminals, and wherein said internal voltage generator is disposed between said at least one of said internal positive and negative terminals for increasing the voltage difference therebetween.