Patent ID: 7315934

Claim:
A data processor comprising: n processing elements which respectively include n register files and n operation units, n being an integer no less than 2, the n register files storing a data matrix having x rows and y columns, x and y being integers that satisfy 1≦x≦n and 1≦y≦n; a block decoder operable to decode a command and output a read instruction and a write instruction to the register file in each processing element; and a network unit including a first selector and a second selector which are each operable to simultaneously perform n transfers, each of the n transfers being a transfer of data from a register file in one processing element to an operation unit in another processing element, wherein when the read instruction is output from the block decoder, the register file in each processing element reads two pieces of data belonging to a same column in the data matrix and outputs the two pieces of data respectively to the first selector and the second selector, the first selector and the second selector each simultaneously perform the n transfers, to change a horizontal position of a piece of data output from the register file in each processing element, the operation unit in each processing element receives a piece of data output from the first selector and a piece of data output from the second selector, and when the write instruction is output from the block decoder, the register file in each processing element writes two pieces of data output from the operation unit in the same processing element into any two of a plurality of registers included in the register file.