Patent ID: 7505353

Claim:
A semiconductor memory device comprising: a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to establish variable access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports, wherein the select control unit establishes the variable access paths directly in response to command signals external to the memory device, wherein the memory array is divided into at least four memory areas; and the select control unit is structured to establish a first data path and a first address path between a first input/output port and a first of the at least four memory areas, to establish a second data path and a second address path between a second input/output port and a second of the at least four memory areas, to establish a third data path and a third address path between the first input/output port and a third of the at least four memory areas, and to establish a fourth data path and a fourth address path between the second input/output port and a fourth of the at least four memory areas, in response to the command signals external to the memory device, wherein when the memory device is operating, the command signals external to the memory device are transmitted via: at least four first signal terminals, the external command signals transmitted via at least one of the first signal terminals being structured to establish a data path and an address path between one of the four memory areas and the first input/output port; and at least four second signal terminals, the external command signals transmitted via at least one of the second signal terminals being structured to disable a data path and an address path between one of the four memory areas and the second input/output port.