Patent ID: 7764091

Claim:
A square wave to pseudo-sinusoidal clock conversion circuit comprising: a first stage, wherein the first stage comprises a cross-coupled differential pair input gain stage and includes a positive input side and a negative input side, the first stage being configured to receive a differential square wave clock input that is a weak clock input across the positive input side and the negative input side, wherein responsive to the differential square wave clock input, the first stage is configured to provide a first pass attempt to create a balanced differential clock with pull-up and pull-down symmetry, the first stage being configured to saturate the weak clock input to a large swing, the first stage further comprising a first transistor of a first conductivity type configured on an output positive side of the first stage as an active load for the cross-coupled differential pair input gain stage, the first transistor of first conductivity type being controlled via a gate bias voltage for the active load which comes from a first diode-connected transistor having the first conductivity type doing current mirroring and acting as an active load for an outer differential pair of first and second transistors of a second conductivity type, the first transistor of the second conductivity type configured as a negative input side second conductivity type transistor of the outer differential pair of first and second transistors of second conductivity type, which is cross-coupled with an inner differential pair of third and fourth transistors of second conductivity type; a second stage, wherein the second stage comprises a positive output side push-pull with low pass filter circuit and a negative output side push-pull with low pass filter circuit, wherein the positive and negative output side push-pull with low pass filter circuits are responsive to the first pass attempt balanced differential clock from the first stage for producing an output pseudo-sinusoidal clock that comprises a nearly sinusoidal output with slew rate and clock waveform pull-up and pull-down symmetry for each of a respective one of the positive and negative output sides; a positive output side floating bias circuit, wherein the positive output side floating bias circuit is configured to provide a floating bias to the negative output side push-pull with low pass filter circuit of the second stage; and a negative output side floating bias circuit, wherein the negative output side floating bias circuit is configured to provide a floating bias to the positive output side push-pull with low pass filter circuit of the second stage; wherein the first and second stages together include resistors configured to provide for active inductive peaking to boost an amplification and buffering of the square wave to pseudo-sinusoidal clock conversion circuit for multi-GHz bandwidth performance.