Patent ID: 7676537

Claim:
A method in an integrated circuit for generating an address value having a contiguous address range from a plurality of selection results, each selection result being an one-of-k selection result, the method comprising: (a) selecting a plurality of multiplication factors, the multiplication factors being power-of-two multiplication factors and the sum of the multiplication factors being equal to k; (b) selecting a first selection result as a first input value; (c) selecting a second selection result as a second input value; (d) shifting using an ALU (arithmetic-logic unit) shifter implemented in the integrated circuit the first input value towards the most significant bit by each of the plurality of multiplication factors to generate a plurality of shifted input values, each shifted input value being shifted towards the most significant bit by one of the plurality of multiplication factors; (e) adding using an ALU adder implemented in the integrated circuit the plurality of shifted input values and the second input value; (f) generating an address output value; (g) selecting the next selection result as the first input value; (h) selecting the address output value as the second input value; and (i) repeating the steps of (d) to (h) until all selection results have been selected, wherein the address output value generated by the addition of the last selection result and the address output value generated by shifting using the ALU shifter and adding using the ALU adder of all previous selection results is the address value having a contiguous address range.