Patent ID: 7064090

Claim:
A method of manufacturing a semiconductor integrated circuit device comprising: (a) forming a semiconductor region of a first conductivity type in a first region at a primary face of a semiconductor substrate of said first conductivity type, and then forming, on said semiconductor substrate above said semiconductor region of the first conductivity type, a semiconductor region of a second conductivity type having a greater area of a planar pattern than said semiconductor region of the first conductivity type such that there is formed a zener diode comprised of said semiconductor region of the first a conductivity type and said semiconductor region of the second conductivity type, wherein said semiconductor region of the second conductivity type, constituting a part of said zener diode, is formed simultaneously to the forming of another semiconductor region of the second conductivity type for producing a source and a drain of a MISFET formed in a second region at the primary face of said semiconductor substrate; (b) forming an insulation film on the primary face of said semiconductor substrate, and then forming a plurality of connection holes in said insulation film which are extended to an upper part of a region located outside a junction formed between the semiconductor regions of said first and second conductivity types; and (c) forming a wire at the upper part of said insulation film, wherein said wire and said semiconductor region of said second conductivity type effect an electrical connection through said plurality of connection holes.