Patent ID: 7298808

Claim:
A signal synchronization mapper, for mapping an input data stream characterized by a first frequency into an output data stream characterized by a second frequency, said mapper comprising: (a) a frequency offset measurement block for producing a frequency offset output signal representative of frequency offset between: (i) a recovered clock signal representative of the frequency of said input data stream; (ii) a reference clock signal; (b) a frequency-locked loop coupled to receive and reduce jitter in said frequency offset output signal, and for producing a jitter-reduced output signal; and, (c) a Δ-Σ modulator external to and series-connected to said frequency-locked loop to receive and quantize said jitter-reduced output signal and for producing one of a preselected number of bit stuffing signals; (d) a FIFO buffer coupled between said input and output data streams; and (e) a FIFO adjuster coupled between said FIFO buffer and said frequency-locked loop, said FIFO adjuster for synchronizing said frequency-locked loop with said FIFO buffer; wherein: (f) said frequency offset measurement block operates at a measurement frequency; (g) said Δ-Σ modulator operates at a stuffing frequency; and, (h) said measurement frequency is not equal to said stuffing frequency.