Patent ID: 7557427

Claim:
A semiconductor device, comprising: a semiconductor substrate including a main surface; a plurality of first interconnections formed in a predetermined region on said main surface and extending in a predetermined direction; a plurality of second interconnections formed in a region adjacent to said predetermined region and extending in said predetermined direction, a first fixed potential applied to said plurality of second interconnections; an insulating layer formed on said main surface and filling in between each of said plurality of first interconnections and between said first interconnection and said second interconnection adjacent to each other; a first well region of a first conductive type formed below said plurality of first interconnections and said plurality of second interconnections, said first well region to which said first fixed potential is applied, each of said plurality of said second interconnections connected to said first well region; and two second well regions of a second conductive type, said first well region formed between one of said two second well regions and the other of two said second well regions, said two second well regions to which a second fixed potential is applied, wherein said plurality of first interconnections are located at substantially equal intervals in a first plane parallel to said main surface, and said plurality of first interconnections and said plurality of second interconnections are located to align in a direction substantially perpendicular to said predetermined direction, said plurality of first interconnections are formed between said plurality of second interconnections, and a capacitance is formed by said plurality of first interconnections and said insulating layer formed between each of said plurality of first interconnections.