Patent ID: 8213232

Claim:
A nonvolatile semiconductor memory comprising: a memory cell unit in which a plurality of electrically connected memory cells, each memory cell of said plurality of memory cells having an electric charge accumulation layer and a control electrode stacked thereon; a source side selection transistor electrically connected to said memory cell of one end of said plurality of memory cells; and a drain side selection transistor electrically connected to the other end of said plurality of memory cells; a plurality of word lines each of which is electrically connected to a control electrode of said plurality of memory cells; a source line which is electrically connected to said source side selection transistor; a bit line which is electrically connected to said drain side selection transistor; and a gate line control circuit which, on a data readout operation, applies a first voltage to a non-selected word line connected to a non-selected memory cell of said memory cell unit and applies a second voltage, which is lower than said first voltage, to a selected word line connected to a selected memory cell, wherein said gate line control circuit applies a voltage to said non-selected word line before said gate line control circuit applies a voltage to said selected word line, said voltage applied to said non-selected word line being lower than said first voltage after the gate line control circuit applies said voltage to said selected word line and before said voltage applied to said selected word line reaches said second voltage, and said gate line control circuit operates either said drain side selection transistor or said source side selection transistor before said gate line control circuit applies said voltage to said non-selected word line.