Patent ID: 7960791

Claim:
An integrated circuit structure comprising: a bulk wafer; a silicon germanium conductor layer above and contacting said bulk wafer; an insulator layer above and contacting said silicon germanium conductor layer; a pair of silicon fins above and contacting said insulator layer, wherein said pair of silicon fins have inner sidewalls separated by a space and wherein a width of said space is 0.5-3 times a width of one of said silicon fins; a first dielectric layer adjacent to said inner sidewalls; and a gate conductor adjacent to said first dielectric layer and filling said space between said pair of silicon fins, wherein said pair of silicon fins further has outer sidewalls opposite said inner sidewalls, wherein said first dielectric layer has a first thickness, and wherein said structure further comprises: a second dielectric layer, having a second thickness, on said outer sidewalls, wherein said first thickness is different from said second thickness.