Patent ID: 7868795

Claim:
A method, comprising: providing a J-bit analog to digital converter which receives an analog input signal and produces a corresponding uncalibrated digital result, the uncalibrated digital result having bit 0 as a least significant bit, having bit J−1 as a most significant bit, and having bit K between bit 0 and bit J−1, the analog to digital converter having a plurality of capacitive elements wherein the plurality of capacitive elements are sufficient to perform a J-bit analog to digital conversion, and wherein J and K are integers; providing an extra capacitive element in addition to the plurality of capacitive elements; providing an extra result bit, wherein the extra result bit is generated by performing an operation using the plurality of capacitive elements and the extra capacitive element; providing an analog input voltage at a first input of a comparator; using a first portion of the plurality of capacitive elements and the extra capacitive element to produce a voltage step at a second input of the comparator; if a resulting output of the comparator is a first voltage, asserting the extra result bit and negating bit K through the most significant bit of the uncalibrated digital result, and performing successive approximations to determine bits K−1 to 0 of the uncalibrated digital result; and if the resulting output of the comparator is a second voltage, negating the extra result bit and performing successive approximations to determine bits J−1 to 0 of the uncalibrated digital result.