Patent ID: 7199402

Claim:
A semiconductor device comprising: a first semiconductor region of a first conductivity type, defined by an upper end surface, a lower end surface opposing to the upper end surface, and first and second side boundary surfaces connecting the upper and lower end surfaces when viewed in section; a second semiconductor region of the first conductivity type having top and bottom surfaces, disposed under the first semiconductor region, a portion of the surface being in contact with the lower end surface of said first semiconductor region so as to share a common boundary surface by the first and second semiconductor regions, wherein a first concavity is cut into the bottom surface of the second semiconductor region; a third semiconductor region of a second conductivity type disposed on the first semiconductor region and being in contact with the upper end surface of said first semiconductor region; a fourth semiconductor region having first and second inner surfaces in contact with the first and second side boundary surfaces respectively when viewed in section and an impurity concentration lower than said first semiconductor region, configured such that the fourth semiconductor region is disposed between the second and third semiconductor regions; and a first main electrode layer being in contact with the bottom surface of the second semiconductor region, a part of the first main electrode layer being buried in the first concavity.