Patent ID: 7585718

Claim:
A method of manufacturing a transistor, the method comprising: forming a multilayer insulating structure on a first conductive structure, the multilayer insulating structure including a first etch-stop layer, a first insulating layer and a second etch-stop layer sequentially stacked on the first conductive structure; forming a second conductive structure on the multilayer insulating structure; forming a second insulating layer on the second conductive structure and the multilayer insulating structure; etching the second insulating layer and the second conductive structure to form a second insulating layer pattern and a second conductive structure pattern, respectively, the second insulating layer pattern defining a first hole having a first radius, the second conductive structure pattern defining a second hole having the first radius; forming a spacer on sidewalls of the first and second holes to partially cover the multilayer insulating structure; etching the second etch-stop layer and the first insulating layer using the spacer as an etch mask to form a second etch-stop layer pattern and a first insulating layer pattern, respectively, the second etch-stop layer pattern together with the first insulating layer pattern defining a third hole communicating with the second hole, the third hole having a second radius substantially smaller than the first radius; forming a sacrificial filler on the first etch-stop layer to fill up the third hole; removing the spacer; removing the sacrificial filler; etching the first etch-stop layer to form a first etch-stop layer pattern defining a fourth hole communicating with the third hole, the fourth hole having the second radius; and growing a carbon nano-tube from a portion of the first conductive structure exposed through the fourth hole.