Patent ID: 8644098

Claim:
A method for testing at least one address connection of a memory having multiplexed banks, rows, and columns, comprising: (a) obtaining a first memory address from a plurality of memory addresses, the plurality of memory addresses being selected from the group consisting of bank, row, and column addresses, by setting all ones or all zeros to one of a bank, row, and column address; (b) writing a first data pattern to the plurality of memory addresses beginning at a second memory address, the second memory address being different from the first memory address, with one of the plurality of memory addresses having a value stuck at a fixed logic state; (c) writing a second data pattern to the plurality of memory addresses beginning at the first memory address, the second data pattern being different from the first data pattern; (d) reading a resulting data pattern from the plurality of memory addresses beginning at the second memory address; and (e) comparing the second data pattern to the resulting data pattern to determine whether a match exists between any portion of the second data pattern and a corresponding portion of the resulting data pattern.