Patent ID: 8498321

Claim:
A method for digital signal processing, the method comprising: generating, using a subtractor hardware module, a residual chip-level signal by subtracting an estimate of an interference suppressed version of a received signal from said received signal; interpolating, using a combiner hardware module comprising a first hardware module and a memory, said residual signal; generating, using a transform hardware module comprising said first hardware module and said memory, a residual symbol-level signal based on said interpolated residual signal; and generating, using a weighting hardware module comprising said first hardware module and said memory, an addback symbol-level signal based on said estimate of said interference suppressed version of said received signal and said residual symbol-level signal, wherein said addback symbol-level signal is used to generate an updated estimate of said interference suppressed version of said received signal, and wherein said updated estimate of said interference suppressed version of said received signal is used for iterative interference cancellation of said received signal.