Patent ID: 8179174

Claim:
A phase lock loop (PLL), comprising: a frequency divider generating a divided frequency with a dividing value; a phase frequency detector (PFD), coupled to said frequency divider, receiving said divided frequency and a reference frequency and generating a PFD output signal by comparing said divided frequency and said reference frequency; a charge pump (CP), coupled to said PFD, receiving said PFD output signal and generating a CP output signal; a loop filter (LPF), coupled to said CP, receiving said CP output signal and generating a LPF output signal; a voltage control oscillator (VCO), coupled to said LPF and said frequency divider, outputting a VCO signal; a controlling circuit, coupled to the VCO and the frequency divider, receiving said VCO signal, said divided frequency and said reference frequency, and generating a compensating voltage output signal; and a comparator, coupled to said controlling circuit and said LPF, generating a comparison result by comparing said compensating voltage output signal and said LPF output signal; wherein said controlling circuit modulates said dividing value according to said comparison result.