Patent ID: 8381003

Claim:
A computer system comprising: a computer that includes a plurality of CPU sockets connected to each other and their respective memories, each of the plurality of CPU sockets including one or more CPU cores, a crossbar switch, and a memory controller, the memory controller of each of the plurality of CPU sockets being connected to the one or more CPU cores through the crossbar switch and connected to a memory controlled by the respective ones of the plurality of CPU sockets, the memory being accessible from another one of the plurality of CPU sockets through the crossbar switch, wherein the computer determines whether all the CPU cores in at least one of the plurality of CPU sockets are in a power saving state; wherein when all the CPU cores are in a power saving state, the computer further determines whether a total usage of the memory controlled by the memory controller in the at least one of the plurality of CPU sockets falls below a predetermined threshold; and when the total usage falls below the predetermined threshold, the computer relocates contents of the memory to a memory controlled by a memory controller in another one of the plurality of CPU sockets, thereby eliminating any access from other ones of the plurality of CPU sockets to the memory connected under the at least one of the plurality of CPU sockets and bringing a whole of the at least one of the plurality of CPU sockets into the power saving state.