Patent ID: 7274613

Claim:
A dynamic RAM, comprising: a plurality of dynamic memory cells, each of the dynamic memory cells comprising a MOSFET and a capacitor, said MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor; a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells; a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, the plurality of complementary bit line pairs being placed so as to extend in directions opposite to one another, and the end of each of the plurality of complementary bit line pairs being located at the center between each of the plurality of complementary bit line pairs; a sense amplifier array comprising a plurality of latch circuits, the plurality of latch circuits being connected with the one end of each of the plurality of complementary bit line pairs and respectively amplifying differences in voltage between the complementary bit line pairs; a plurality of word drivers connected with the plurality of word lines and placed in a plurality of division areas which are divided by the sense amplifier array; and a plurality of power supply lines formed in mesh form, the plurality of power supply lines supplying power to the plurality of word drivers, wherein the plurality of power supply lines are formed over an area which includes the plurality of division areas.