Patent ID: 7505327

Claim:
A method of controlling a semiconductor memory device which includes a first and a second memory cell array each of which has memory cells each including a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a drain connected to a source of the first MOS transistor, and word lines each of which connects commonly the control gates of the first MOS transistors in a same row, the method comprising: erasing all of the memory cells included in the first and second memory cell arrays; injecting electrons into the floating gates of the memory cells connected to m (m is an integer) of the word lines included in the second memory cell array and making the threshold voltages of the memory cells positive; comparing the time required to discharge first bit lines each of which connects commonly the drains of the first MOS transistors in a same column in the first memory cell array with the time required to discharge second bit lines each of which connects commonly the drains of the first MOS transistors in a same column in the second memory cell array; and decreasing the value of m and returning to the erasing of all of the memory cells, if the result of the comparison shows that the second bit lines took a shorter time to discharge than the first bit lines.