Patent ID: 6966017

Claim:
A built-in self-test unit for testing a cache memory block on an integrated circuit, the built-in self-test unit comprising: a controller; an address generator associated with the controller for supplying predetermined address information to the cache memory block; and a data generator for supplying a predetermined pattern of test data to the cache memory block in response to signals from the controller, wherein: (i) the controller activates the generators to sequentially execute a series of steps in accord with a test algorithm, including write operations and read operations, (ii) the write operations comprise writing the test data pattern to storage in lines of random access memory within the cache memory block and writing tag bits to tag storage for each line, as though each cache location were addressed absolutely, and (iii) the read operations comprise supplying a series of partial addresses and known tag settings from the address generator to cause the cache memory block to output data from storage in specific locations of the cache memory block in sequence.