Patent ID: 7415597

Claim:
A processor, comprising: a scheduler configured to issue operations; and a load store unit coupled to receive memory operations issued by the scheduler and configured to execute the memory operations; and a predictor comprising a plurality of entries, wherein each of said entries includes a dependence prediction value and a counter indicative of a strength of a corresponding dependence prediction value, wherein said dependence prediction value comprises a bit which predicts whether a given load is dependent upon an older store; wherein said load store unit is further configured to: predict whether a given load operation is dependent upon an older store operation by accessing a given predictor entry of said entries corresponding to said given load operation, and evaluating a given dependence prediction value included in said given predictor entry; execute said given load operation before an address of said older store operation is computed in response to predicting that said given load operation is independent of said older store operation; detect whether said given load operation has been mispredicted subsequent to predicting that said given load operation is independent of said older store operation, the misprediction relating to whether the given load operation is dependent upon the older store operation; and provide a replay indication to said scheduler indicating that said load operation should be reissued in response to detecting that said given load operation has been mispredicted.