Patent ID: 7707370

Claim:
An information processing apparatus comprising: a plurality of memory channels each including a unit memory; a circuit for performing interleave control such that an interleave number can be constantly a multiplier of 2 when the unit memory connected to a particular memory channel is accessed; a circuit for interleaving by a WAY number Z 1 the unit memory of the way number Z 1 as a maximum multiplier of 2 not exceeding a maximum WAY number X as a multiplier of 2 when a total number of the unit memory is Y, interleaving by a WAY number Z 2 remaining unit memory of the WAY number Z 2 as a maximum multiplier of 2 not exceeding the maximum WAY number X in remaining unit memories of Y−Z 1 , . . . , and interleaving, by a WAY number Zi, remaining unit memory of the WAY number Zi as a maximum multiplier of 2 not exceeding the maximum WAY number X; a segment information holding circuit for holding segment information as a pair of any of the WAY number Z 1 , Z 2 , . . . , and Zi, and a number of lower limit address increment segments as an increment from an address of the unit memory for which interleave is determined in advance in a same memory channel; and a lower limit address circuit for holding a lower limit address obtained by adding an upper limit address of the unit memory for which interleave is determined in advance in the same memory channel to the number of the lower limit address increment segments of the unit memory of the segment information; an upper limit address circuit for holding an upper limit address obtained by adding the lower limit address of the unit memory to a WAY number of the unit memory of the segment information; and an address conversion circuit for outputting a hit signal when the lower limit address≦an access address<the upper limit address holds true, and performing interleave of a WAY number of a number of hit signals on the access address.