Patent ID: 8683164

Claim:
A memory system comprising: a memory vault comprising a plurality of memory arrays, the memory arrays located on a plurality of stacked memory dies, the dies arranged in a first dimension, the memory dies including a first memory die and a second memory die, the plurality of memory arrays including a first memory array located on the first memory die and a second memory array located on the second memory die, the first memory die including a third memory array, the second memory die including a fourth memory array, the first and third memory arrays arranged in a second dimension perpendicular to the first dimension, the second and fourth memory arrays arranged in the second dimension, wherein first and second memory arrays are included in the memory vault, and wherein the third and fourth memory arrays are included in an additional memory vault; and a memory vault controller (MVC) located on a logic die stacked with the memory dies and communicatively coupled to the memory vault to provide at least one of control, switching or communication logic associated with the memory vault, wherein the MVC is associated with a vault timing module to provide control of a delay associated with a data clock to clock a data digit into a storage cell associated with the MVC, a delay associated with a data strobe to transfer the data digit to a storage cell associated with the memory vault and/or a subsection of the memory vault, and/or a memory array timing parameter associated with memory array access, and wherein the vault timing module includes a write strobe delay control module and the MVC further includes a write strobe delay element and a write strobe driver, the write strobe delay element to receive a clock signal and a delay control command from the write strobe delay control module.