Patent ID: 7617378

Claim:
A multiprocessor data processing system (MP) that enables tracking of multiple, concurrent translation look-aside buffer invalidates (TLBIs) issued by different processors, said MP comprising: a plurality of processors including a first processor and a second processor coupled together by an interconnect, wherein each processor comprises a cache coherency subsystem that includes a translation look-aside buffer (TLB), a TLB controller, at least one execution unit and an associated execution unit queue, a snooper, and a TLBI register; wherein said TLBI register comprises a plurality of entries, each specifically assigned to a particular processor among the plurality of processors and each entry being utilized to specifically track a completion status of TLBIs of the particular processor to which the entry is assigned; a memory coupled to said plurality of processors by said interconnect and which includes a page frame table in which is stored a plurality of page table entries (PTEs) of virtual and real address translation pairs; and operating logic associated with each processor for implementing a TLBI protocol that controls a response by each of said plurality of processors to a receipt of one or more TLBIs wherein said TLBI protocol includes: when a TLBI is received at said first processor, logic for recording within a first TLBI register of said first processor a TLBI state of each processor of said MP, wherein said recording of a state includes assigning a value to an entry of the TLBI register that is specially assigned to the particular processor, said value indicating whether that the particular processor has issued a TLBI operation on the interconnect that has not yet completed at said first processor; logic for tracking a completion status of each outstanding TLBI operation utilizing said first TLBI register at said first processor.