Patent ID: 7129762

Claim:
A flip-flop circuit having an input to receive an input signal and having an output to provide an output signal, comprising: a flip-flop having a data input, a clock input, and a data output; a first pass gate having an input to receive the input signal, an output coupled to the data input of the flip-flop, and a control terminal to receive a first control signal; a second pass gate having a first data terminal coupled to the data input of the flip-flop, a second data terminal coupled to the output of the flip-flop circuit, and a control terminal to receive a second control signal; and a third pass gate having an input coupled to the data output of the flip-flop, an output coupled to the output of the flip-flop circuit, and a control terminal to receive a third control signal, wherein the first, second, and third control signals are unique signals that are generated in response to a clock enable signal and a bypass signal.