Patent ID: 7067902

Claim:
An integrated circuit (IC) chip comprising: the chip comprising a base substrate, a plurality of stacked levels of conductive metallurgy and low-k dielectric material fabricated over the substrate, the conductive metallurgy including active electrical lines, with the conductive metallurgy in different levels being connected by conductive metallurgy vias, and being capped by a top oxide cap covering the plurality of stacked levels; a plurality of stacked via pillars positioned at a plurality of spaced locations in the chip, wherein the plurality of stacked via pillars extend completely from the base substrate of the chip to the top oxide cap of the chip, and at least a portion of the plurality of stacked via pillars are not electrically connected to any of the active electrical lines or vias, wherein the plurality of stacked via pillars support the structural stability of the chip design to accommodate deformations during any thermal and/or mechanical stresses.