Patent ID: 7776672

Claim:
A method of manufacturing a semiconductor device having: a second conductivity type base region selectively provided in a surface region on a first principal surface of a first conductivity type semiconductor substrate; a first conductivity type emitter region selectively provided in a surface region of the base region; a MOS gate structure including: a gate insulator film provided on a surface of a section of the base region, the section being positioned between the semiconductor substrate and the emitter region; and a gate electrode provided on the gate insulator film; an emitter electrode in contact with the emitter region and the base region; a second conductivity type collector layer provided on a surface of a second principal surface of the semiconductor substrate; a collector electrode in contact with the collector layer; and a second conductivity type isolation layer surrounding the MOS gate structure, reaching the first principal surface from the second principal surface while being inclined to the first principal surface, and coupled to the collector layer, wherein each of the first principal surface and the second principal surface is a {100} plane, and a surface of the isolation layer is a {111} plane, the method comprising the steps of: forming the MOS gate structure on the first principal surface of the first conductivity type semiconductor substrate; covering the second principal surface of the first conductivity type semiconductor substrate with a mask having openings of a desired pattern along the <110> direction; forming a trench having a V-shaped or trapezoidal-shape cross section in the semiconductor substrate from the second principal surface side, by wet anisotropic etching with an alkaline solution, sections of the second principal surface of the semiconductor substrate not covered by the mask; and forming the second conductivity type isolation layer and a diffused layer on the second principal surface by introducing a second conductivity type impurity into a side wall of the trench and the second principal surface.