Patent ID: 7755084

Claim:
A semiconductor wafer comprising a substrate having a semiconductor element formation layer, a lowermost metal layer formed on or above the semiconductor element formation layer, and an uppermost metal layer formed on or above the lowermost metal layer, the semiconductor wafer further comprising: a plurality of chip regions; an evaluation element region that is defined as a region between the plurality of chip regions and that has a cutaway region that is subjected to dicing when separating an individual chip and a remnant region that is not subjected to dicing when separating the chip; an evaluation element formed at the evaluation element region; a lowermost layer electrode pad that is formed at a pad region defined as extending from the remnant region over the cutaway region within the evaluation element region, and that is formed at the lowermost metal layer so as to be electrically connected to the evaluation element; and an uppermost layer electrode pad that is formed at the pad region and that is electrically connected to the lowermost layer electrode pad, wherein the lowermost layer electrode pad and the uppermost layer electrode pad that are formed at the remnant region and the pad region are configured by a combination of metals having a line width of less than or equal to a predetermined value.