Patent ID: 8281110

Claim:
An out-of-order execution in-order retire microprocessor, comprising: a branch predictor, configured to predict the presence of branch instructions fetched from an instruction cache and to generate information associated with the branch instructions; an instruction decoder, configured to decode the fetched branch instructions; a branch information table, comprising a circular queue N entries allocated in program order in response to the instruction decoder decoding the branch instructions, each of the N entries configured to store the information generated by the branch predictor associated with one of the branch instructions, wherein the allocated entry is de-allocated after execution of the branch instruction; and a reorder buffer, coupled to the branch information table, comprising M entries, each of the M entries configured to store information associated with an unretired instruction within the microprocessor, wherein each of the M entries includes a field that indicates whether the unretired instruction is a branch instruction and, if so, a tag identifying one of the N entries in the branch information table storing the information associated with the branch instruction; wherein N is less than M.