Patent ID: 7961126

Claim:
An apparatus for reduction of unwanted idle tones by dithering a variable resolution nlev (nlev>2) quantizer of a multi-bit (M-bit, M>1, M=Floor(log 2(nlev))) sigma-delta analog-to-digital converter (ADC), comprising: a multi-bit (M-bit, M>1) sigma-delta modulator comprising a multi-level digital-to-analog converter (DAC), an analog voltage summation circuit coupled to the multi-level DAC, an analog loop filter coupled to an output of the analog voltage summation circuit, a variable resolution quantizer having nlev (nlev>2) levels coupled to the analog loop filter, an encoder coupled to the variable resolution quantizer, wherein the encoder converts outputs from the variable resolution quantizer into binary representations thereof and the binary representations are applied to the multi-level DAC, and a random sequence generator coupled to the variable resolution quantizer, wherein the random sequence generator generates a plurality of random numbers N(n) in a sequence, where N(n) are random integer numbers between 2 and nlev, whereby resolutions of the variable resolution quantizer are determined by respective ones of the plurality of random numbers N(n) for each analog voltage sample taken by the sigma-delta modulator; a voltage reference coupled to the multi-level DAC; and a digital filter coupled to the encoder and receiving the binary representations therefrom.