Patent ID: 8189368

Claim:
A memory device, comprising: a multi-port static random access memory (SRAM) cell; a first bit line conductor, a first complementary bit line conductor, a second bit line conductor and a second complementary bit line conductor coupled to access ports of the SRAM cell; a first word line and a second word line coupled to the access ports of the SRAM cell; and a Vdd power supply conductor and four Vss power supply conductors coupled to the SRAM cell, wherein the bit line conductors and power supply conductors are disposed in parallel in a first common metallization layer, with the Vdd power supply conductor centered among the conductors in the first common metallization layer, a first pair of the bit line conductors on a first side of the Vdd power supply conductor, a second pair of the bit line conductors on a second side of the Vdd power supply conductor, first and second ones of the four Vss power supply conductors disposed adjacent the Vdd power supply conductor on the first and second sides of the Vdd power supply conductor, respectively, a third Vss power supply conductor disposed between the bit line conductors of the first pair of the bit line conductors and a fourth Vss power supply conductor disposed between the bit line conductors of the second pair of the bit line conductors.