Patent ID: 7380111

Claim:
A method, comprising: providing a prediction for a predicate in an instruction in an instruction pipeline of an out-of-order processor; setting a first set of values for selected predicate registers in a predicate register file according to the prediction, wherein the first set of values includes predicted values for the predicate; obtaining a second set of values which represents architecturally determined values for the predicate, the second set of values being computed by a read-modify-write operation, wherein the second set of values includes architecturally correct values for the predicate, and wherein performing the read-modify-write operation comprises: substantially simultaneously reading all values from all the predicate registers in the predicate register file, including the first set of values for the selected predicate registers; modifying the first set of values in the selected predicate registers; and substantially simultaneously writing the values to a set of new predicate registers in the predicate register file, including the second set of values; comparing the first set of values with the second set of values; and flushing the instruction with incorrectly predicted predicate and any dependent instructions from the instruction pipeline if the first set of values is different from the second set of values.