Patent ID: 8670265

Claim:
A method of reducing power used in a static random access memory (SRAM), comprising: providing an array of memory cells in the SRAM, the array of memory cells arranged in rows and columns, each row of the memory cells connected to a word line, and each column of the memory cells connected to a bit line, a latch sourcing supply line, and a latch sinking supply line; applying a first voltage between latch sourcing and latch sinking supply lines for a column of memory cells that are in the array and are column addressed during a read cycle of the array; and applying a second voltage between latch sourcing and latch sinking supply lines for a column of memory cells that are in the array and are not column addressed during the read cycle of the array; wherein the first voltage is greater than the second voltage; and wherein each memory cell in the array comprises: a latch connected between a latch sourcing supply line and a latch sinking supply line; and at least one read buffer.