Patent ID: 6941496

Claim:
An error detecting circuit comprising: an error data storing unit for dividing a circuit implemented in a chip into predetermined areas, and outputting a plurality of error signals in response to a plurality of state error signals, a serial chain signal, a lock-enable signal, and a chip error signal, each of the plurality of state error signals being enabled when an error occurs in a corresponding predetermined area, the serial chain signal for reading the plurality of state error signals stored in the chip if the chip goes out of order when the error occurs in the circuit, and the lock-enable signal for determining whether or not to preserve the plurality of state error signals; and an error data collecting unit for outputting the chip error signal in response to the plurality of error signals output from the error data storing unit, wherein the error data storing unit stores and outputs at least one of the plurality of state error signals and, in response to the serial chain signal, enables confirmation of at least one of the plurality of state error signals stored in the error data storing unit by observing the chip error signal.