Patent ID: 8766402

Claim:
A semiconductor device structure, comprising: a semiconductor substrate having a first conductivity type and a top surface; a plurality of first doped regions at a first depth below the top surface arranged in a checkerboard fashion, wherein the plurality of first doped regions are of a second conductivity type, and wherein the plurality of first doped regions define a plurality of first regions in the substrate at the first depth, whereby the plurality of first regions in the substrate are in a checkerboard pattern in which each first region of the plurality of first regions is between adjacent first doped regions of the plurality of first doped regions; a plurality of second doped regions arranged in a checkerboard fashion, wherein the plurality of second doped regions are of the second conductivity type and are above and directly on the plurality of first regions in the substrate; a dielectric layer over the top surface; and an inductive element over the dielectric layer, wherein the inductive element is over the plurality of first doped regions.