Patent ID: 8854905

Claim:
A semiconductor device, comprising: an internal circuit configured to perform write operations in response to each of a plurality of write commands, wherein the plurality of write commands are sequentially input to the internal circuit; a first pulse generation unit configured to generate a first pulse activated during a first delay amount in response to a write command, which is input during an inactivation period of the first pulse, out of the plurality of write commands; a second pulse generation unit configured to generate a second pulse activated during the first delay amount in response to a delayed write command, which is input during an inactivation period of the second pulse, out of the plurality of write commands after a second delay amount from the activation time of the first pulse; and a transfer control unit configured to prevent commands other than the plurality of write commands from being transferred to the internal circuit during a sum of the activation period of the first pulse and the activation period of the second pulse.