Patent ID: 8135105

Claim:
A circuit for correcting a frequency of an output clock in a receiving device, the receiving device receiving data and a time stamp component, the time stamp component being based at least partially on a desired frequency of the output clock, the circuit comprising: an output clock feedback loop that adjusts at least one of a phase of the output clock and a frequency of the output clock, the adjustment being based at least partially on the time stamp component; a FIFO buffer that temporarily stores the data, the FIFO buffer having an actual data level, a target data level ranqe including an upper threshold and a lower threshold, and a desired data level within the target data level range; and a time stamp adjuster that selectively adjusts the time stamp component based on a status of the FIFO buffer, the status of the FIFO buffer being based at least in part on the actual data level; wherein when the actual data level in the FIFO buffer is above the upper threshold, the time stamp adjuster increases the time stamp component by a percentage that is based at least in part upon an offset equal to the difference between the actual data level in the FIFO buffer and the desired data level.