Patent ID: 7534680

Claim:
A method for manufacturing a BiCMOS device, comprising the steps of: forming a collector plug, a P-well doped with P-type impurities, and an N-well doped with N-type impurities, in an SOI substrate having a first insulating film and a first semiconductor that is made of any one of N-type and P-type semiconductors and disposed on the first insulating film, the collector plug being made of the same type as the first semiconductor and more highly doped than the first semiconductor on a portion of the first semiconductor; forming a buffer oxide film and a nitride film; forming any one of a single open slit and a plurality of open slits by patterning the nitride film, and removing the nitride film disposed on a portion where a field oxide film is to be formed; forming a field oxide film, a collector made of the first semiconductor surrounded with the field oxide film and the collector plug, and an oxide film disposed on a portion where the collector and the collector plug are contacted to each other and having a thickness thinner than that of the field oxide film, by performing a thermal oxidation process; removing the nitride film; forming a gate oxide film of a CMOS; depositing a SiGe gate layer on the gate oxide film of the CMOS and a base epitaxial layer of a HBT simultaneously, wherein the SiGe gate layer made of same type of the first semiconductor; depositing a second insulating film on the SiGe layer and removing a portion of the deposited second insulating film by patterning, wherein the portion of the second insulating film is deposited on a contact hole of the HBT and a gate of CMOS; depositing a polysilicon layer on the gate of the CMOS and the contact hole of the HBT simultaneously, wherein the polysilicon layer made of the same type as the first semiconductor; forming a gate of CMOS and an emitter of the HBT by patterning the polysilicon layer; performing N-type doping with a low concentration into a source / drain region of the P-well, and P-type doping with a low concentration into a source/drain region of the N-well; forming a spacer in a sidewall of the emitter and a sidewall of the gate of the CMOS device; and performing N-type doping with a high concentration into a source/drain region of the NMOS device, and P-type doping with a high concentration into a source/drain region of the PMOS device; forming a base protective layer on an edge of a portion where the base and the collector are contacted to each other, the base protective layer being made of the same type of semiconductor as the base, and more highly doped than the base, after forming the emitter and the gate of the CMOS device; patterning the base of HBT; forming a silicide layer of a compound of a silicon and a metal; forming a third insulating film; and forming an emitter wiring; a base wiring; a collector plug wiring of the HBT device; a source wiring, a drain wiring and a gate wiring of the CMOS device; by depositing and patterning a conductor metal.