Patent ID: 7366043

Claim:
A current reduction circuit of a semiconductor device comprising: an enabling signal generator which outputs a predetermined enabling signal in association with a cell block in which a bridge has been formed between a word line and a bit line; and an isolation controller which is enabled in response to the enabling signal, and outputs a first control signal to periodically isolate the bridge-formed cell block from a sense amplifier array for a predetermined period in a standby mode in response to a periodic signal enabled at intervals of a predetermined time, wherein the isolation controller includes: a first buffer which buffers the periodic signal; a delay which delays an output signal from the first buffer for a predetermined period; a first logic unit which logically operates the output signal from the first buffer and an output signal from the delay; a second buffer which is enabled in response to the enabling signal, and buffers an output signal from the first logic unit; a latch which latches an output signal from the second buffer; and a second logic unit which logically operates a first block select signal and an output signal from the latch.