Patent ID: 7257172

Claim:
A signal processing device utilizing partial response maximum likelihood detection, comprising: an iterative decoder which detects a signal from a partial response equalized sample value sequence, utilizing iterative decoding, the iterative decoder having a plurality of cascade-connected decoder units, each of the decoder units including a soft-decision Viterbi detector which outputs soft-decision values from a sample value sequence input to each of the decoder units; a partial response waveform generator which generates a digital value sequence of an expected partial response waveform based on an output of the soft-decision Viterbi detector included in a predetermined one of the decoder units, the predetermined decoder unit being other than a final-stage decoder unit; a flag generator which generates flag information indicative of whether reliability of the digital value sequence generated by the partial response waveform generator is low or high, based on the output of the soft-decision Viterbi detector included in the predetermined decoder unit; an error detector which detects error values in the partial response equalized sample value sequence, the error detector utilizing the digital value sequence generated by the partial response waveform generator, as a digital value sequence of a reference waveform for feedback control of a predetermined control target, the reference waveform being referred to for error value detection; and an error output controller which controls output of the error values detected by the error detector in accordance with a state of the flag information generated by the flag generator.