Patent ID: 7900179

Claim:
A computer implemented method comprising: identifying a plurality of nodes in a design file, wherein the design file represents an electronic device design, where each of the plurality of nodes represents a conductor between device components of the electronic device design, the plurality of nodes including a first node; determining if the first node is a first re-routable node based upon a comparison of a simulated signal propagation delay of an existing route of the first node to a simulated signal propagation delay of a defined route of the first node; in response to determining that the first node is a first re-routable node, determining a priority of the first re-routable node with respect to a second re-routable node based upon a simulated signal propagation delay of a first path encompassing the first re-routable node and a simulated signal propagation delay of a second path encompassing the second re-routable node to provide a prioritized set of re-routable nodes; and storing the prioritized set of re-routable nodes.