Patent ID: 7984222

Claim:
A memory system for storing and retrieving data for a processing system, the memory system comprising: a memory controller for receiving and responding to memory access requests; a plurality of memory devices; a memory bus in communication with the memory controller; and a memory hub device in communication with the memory bus, the memory hub device comprising: a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus; a memory device interface for communicating with the memory devices; and a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation, the performance monitor comprising: a bin counter for logging an elapsed time between related events, the performance monitor configured to transfer one or more entries in the bin counter into an event frequency array after a defined period of time has elapsed; and a trace array for recording one or more of the address, control and data information over time, the performance monitor further configured for setting thresholds on event counters and bin counters, and the trace array is stopped when one or more of the thresholds is exceeded, thereby stopping the trace array upon indication of an unexpected event occurring.