Patent ID: 8474034

Claim:
An apparatus comprising: a hardware processor configured to implement an anti-replay check for a plurality of received packets and a plurality of corresponding sequence numbers; and a circular buffer coupled to the hardware processor and comprising a bitmap used in the anti-replay check, wherein the bitmap is slided in a circular manner by updating a low index that points to a first sequence number for a first received packet and a high index that points to a last sequence number for a last received packet without bit-shifting, wherein the bitmap comprises a plurality of bit blocks that comprise a quantity of bits that determine a configured window size, wherein the bitmap further comprises an additional bit block that comprises a plurality of redundant bits, wherein the plurality of bit blocks combined with the plurality of redundant bits determine an actual window size, and wherein, when an update results in a new value of one of the low index and the high index exceeding the end of the circular buffer, the redundant bits are used so that the new value of one of the low index and the high index wraps around from the beginning of the circular buffer and the bitmap is slided without bit-shifting.