Patent ID: 8547726

Claim:
A semiconductor memory device comprising: a memory cell array in which memory cells each including at least a rectification element and a variable resistance element, which are connected in series, are disposed; a peripheral circuit including a first even bit line and a first odd bit line of a first side, and a second even bit line and a second odd bit line of a second side, which are electrically connected to the memory cells; a sense amplifier configured to sense the memory cells via the peripheral circuit; and a control circuit configured to control operations of the memory cell array and the sense amplifier, wherein a potential of a selected bit line, which is one of the first even bit line and the first odd bit line of the first side, is boosted by charge sharing of the second even bit line and the second odd bit line which are nonselected bit lines and physically neighbor the first even bit line or the first odd bit line of the first side, which is connected to a selected one of the memory cells, and the control circuit is configured to independently control the two nonselected bit lines by providing an offset between timings of discharging the nonselected bit lines.