Patent ID: 7541217

Claim:
A fabrication method of a stacked chip structure, comprising: providing a wafer having a first surface, a second surface opposite to the first surface, a plurality of first bonding pads disposed on the first surface, a plurality of second bonding pads disposed on the second surface, and a plurality of conductive structures penetrating the first surface and the second surface and electrically connected to the first bonding pads and the second bonding pads; forming a first conductive layer on the first surface of the wafer and covering the first bonding pads with the first conductive layer; forming a first patterned polymer layer on the first conductive layer, wherein the first patterned polymer layer has a plurality of first openings for exposing the first conductive layer; forming a second patterned polymer layer on the second surface, wherein the second patterned polymer layer has a plurality of second openings for exposing the second bonding pads; electroplating a second conductive layer on the first conductive layer, wherein the second conductive layer is located within the first openings; heating the second conductive layer for forming a plurality of solder bumps on the first bonding pads and forming a patterned first conductive layer, wherein the patterned firsts conductive layer has a first portion and a second portion separated from the first portion, the first portion is disposed between the solder bump and the first bonding pad, and the second portion is disposed between the first patterned polymer layer and the wafer; and stacking a plurality of the wafers on a substrate structure, wherein a first wafer of the wafers is electrically connected to the second bonding pads of a second wafer through the solder bumps, and the first wafer is correspondingly connected to the second patterned polymer layer on the second wafer through the first patterned polymer layer disposed on the first wafer.