Patent ID: 7015537

Claim:
An array of non-volatile memory cells comprising: a semiconductor substrate; a plurality of non-volatile memory cells formed in said substrate, arranged in a plurality of rows and columns; each memory cell comprising; a first terminal and a second terminal with a channel therebetween in said substrate, said channel having a first portion and a second portion; a transistor gate insulated from said substrate and positioned to control the conduction of current in said first portion of said channel; a floating gate insulated from said substrate and positioned to control the conduction of current in said second portion of said channel; a control gate capacitively coupled to the floating gate; a plurality of buried bit lines in said substrate arranged substantially parallel to one another; each buried bit line electrically connected to the first terminal of memory cells arranged in the same column; wherein adjacent memory cells in the same row share a common buried bit line; a plurality of buried source lines in said substrate arranged substantially parallel to one another; each buried source line electrically connected to the second terminal of memory cells arranged in the same column; wherein adjacent memory cells in the same row share a common buried source line; a plurality of gate lines arranged substantially parallel to one another, each gate line electrically connected to the transistor gate of memory cells arranged in the same column; and a plurality of word lines ranged substantively parallel to one another, each word line electrically connected to the control gate of memory cells arranged in the same row.