Patent ID: 8117513

Claim:
A test generation method of a semiconductor logic circuit device comprising: a combinational portion including external input lines, pseudo external input lines, external output lines and pseudo external output lines; and a plurality of scan flip-flops connected between said pseudo external output lines and said pseudo external input lines, such that said plurality of scan flip-flops are connected in series to each other as a shift register, thus realizing at least one scan chain, said test generation method comprising: converting a test cube including one or more unspecified bits in said external input lines and said pseudo external input lines into a test vector including no unspecified bits to reduce a number of discrepancies between bits of said pseudo external input lines and respective bits of said pseudo external output lines, wherein said converting comprises determining a case type by determining a bit state of said pseudo external input lines and a bit state of said pseudo external output lines, wherein the determining of a case type comprises: a case type 1 defined by a state where there are no unspecified bits in said pseudo external input lines and said pseudo external output lines; a case type 2 defined by a state where there is at least one unspecified bit in said pseudo external input lines and there is no unspecified bit in said pseudo external output lines; a case type 3 defined by a state where there is no unspecified bit in said pseudo external input lines and there is at least one unspecified bit in said pseudo external output lines; and a case type 4 defined by a state where there is at least one unspecified bit in said pseudo external input lines and there is at least one unspecified bit in said pseudo external output lines.