Patent ID: 8811499

Claim:
A video multiviewer system comprising: a plurality of video inputs configured to receive a plurality of router outputs from a router that correspond to a plurality of router input video streams; a video input/Out (I/O) controller configured to assign addresses for a selected subset of the router input video streams; a multiviewer video processor coupled to said plurality of video inputs, the multiviewer video processor comprising memory that includes a texture buffer, wherein the multiviewer video processor is configured to: lock an assigned address of the texture buffer in response to the video I/O controller assigning an address to the texture buffer for each of the selected subset of the router input video streams; and store the selected subset of the router input video streams in respective locked address texture buffers via direct memory access (DMA) and a display coupled to said multiviewer video processor and configured to receive and simultaneously display in respective video windows of the display the selected subset of the router input video streams that are stored at respective locked address texture buffers in response to a user input at a user input device; wherein the multiviewer processor is configured to provide a control signal to the router, wherein the control signal identifies the selected subset of the router input video streams to be provided by the router to the plurality of router outputs for display in the respective video windows of the display in response to the user input at the user input device wherein the router is configured to have a greater number of router inputs than the number of video inputs of the multiviewer system.