Patent ID: 6949429

Claim:
A method for manufacturing a semiconductor memory device, the method comprising: a) separating a cell area from a peripheral circuit area on a semiconductor substrate and forming device active areas; b) forming a plurality of MOS transistors in the device active areas of the cell area and the peripheral circuit area; c) forming a first interlayer dielectric (ILD) film on the semiconductor substrate and forming a first electrode pattern and a guard-ring pattern surrounding the cell area on the first ILD film; d) sequentially forming a conductive layer for a first electrode and an insulating layer for patterning on the first electrode pattern and the guard-ring pattern; e) opening the entire cell area and a part of the guard-ring pattern, removing the conductive layer for the first electrode and the insulating layer for patterning to the first ILD film, and forming a first electrode node in the cell area; f) removing the insulating layer for patterning that is filled in the first electrode node; g) forming a dielectric layer and a conductive layer for a second electrode on the semiconductor substrate; h) forming a pattern for a second electrode on the conductive layer for the second electrode; and i) forming a contact fill for a plate electrode while being in contact with the second electrode that is formed on the sidewall and the bottom of the guard-ring pattern.