Patent ID: 7952130

Claim:
An eDRAM-type semiconductor device comprising: a semiconductor substrate; a dynamic random access memory (DRAM) section formed on said semiconductor substrate; a logic circuit section formed on said semiconductor substrate; an insulating layer formed on said semiconductor substrate; a first capacitor formed in said insulating layer at said DRAM section, said first capacitor defining a part of a memory cell of said DRAM section; and a second capacitor formed in said insulating layer at said logic circuit section, wherein said first capacitor comprises a lower electrode layer formed on an inner wall face of a hole formed in said insulating layer, when viewed from above the device the hole having a generally circular shape, said second capacitor comprises a first lower electrode layer portion formed on an inner wall face of at least one groove formed in said insulating layer, when viewed from above the device the groove having a generally rectangular shape, and a second lower electrode layer portion formed directly above a topmost surface of said insulating layer so as to be integrated with said first lower electrode portion, a depth of said hole and a depth of said groove are substantially equivalent to each other, said first and second capacitors are placed at a same level, and said first capacitor has a smaller capacitance than said second capacitor.