Patent ID: 8614597

Claim:
An apparatus comprising: two or more series transistor elements configured to generate an output signal in response to (i) an input signal, (ii) a first bias signal, and (iii) a plurality of variable impedances; a plurality of shunt circuits each configured to generate a respective one of said variable impedances in response to a second bias signal, wherein (i) said output signal is attenuated compared with said input signal by an attenuation value, (ii) said output signal has an output power equal to or less than an input power of said input signal, (iii) an amount of said attenuation value is controlled by said first bias signal and said second bias signal, and (iv) one or more of said series transistor elements and each of said plurality of shunt circuits are configured as two or more transistors each having two or more gates; and a plurality of resistors driven by a third bias signal and configured to generate a respective DC voltage at each drain and each source of said transistors.