Patent ID: 8578308

Claim:
A verification apparatus, which verifies, at respective times on a discrete time series, a circuit description that describes a communication between circuit components, in which a signal value changes on a continuous time series, by a design description language that describes the communication as a function call, the apparatus comprising: an allocation device configured to allocate a new variable to an extended statement that designates an event associated with the function call in an extended assertion described using a property description language; a conversion device configured to convert the extended statement into a formula that expresses a condition using the new variable; a value assignment device configured to detect generation of the event at an arbitrary time on the continuous time series, and to assign a value corresponding to a meaning of the extended statement to the new variable so that a description of variable assignment is inserted in the circuit description; a simulation device configured to simulate the circuit description in which the description of variable assignment is inserted; and a determination device configured to determine based on the value of the new variable at each time on the discrete time series if the condition corresponding to the meaning of the extended statement is satisfied.