Patent ID: 8263459

Claim:
A method of manufacturing a non-volatile memory, the method comprising: providing a semiconductor substrate; forming in the semiconductor substrate at least one Shallow Trench Isolation (STI) structure that extends into and above the semiconductor substrate in a height direction; forming on the semiconductor substrate an array of memory cells, each memory cell comprising a tunnel oxide layer formed on the semiconductor substrate, and a floating gate layer formed on the tunnel oxide layer, wherein adjacent memory cells in the array of memory cells are separated from one another by the at least one STI structure; partially etching back the at least one STI structure to expose an upper portion of the floating gate layer of each memory cell, wherein the exposed upper portion of each floating gate layer forms a fin with an exposed top and exposed sidewalls; oxidizing the exposed sidewalls of each fin; removing a first oxidized layer, thereby reducing the width of each fin, and forming an inverted-T floating gate from each floating gate layer; and oxidizing the exposed top of each fin, wherein removing the first oxidized layer additionally reduces the height of each fin.