Patent ID: 8144501

Claim:
An integrated circuit structure comprising: a static random access memory (SRAM) cell comprising: a first pull-up transistor, wherein the first pull-up transistor is a single-gate transistor; a first pull-down transistor forming a first inverter with the first pull-up transistor, wherein the first pull-down transistor comprises a front gate connected to a gate of the first pull-up transistor, and a back-gate decoupled from the front gate; and a back-gate controller coupled to the back-gate of the first pull-down transistor, wherein the back-gate controller is configured to apply a first voltage to the back-gate of the first pull-down transistor in a write operation of the SRAM cell, and apply a second voltage different from the first voltage to the back-gate of the first pull-down transistor in a read operation of the SRAM cell.