Patent ID: 8024388

Claim:
A parallel pseudo-random binary sequence generator comprising: twenty three clocked D-type flip flops each identified by an integer X between 0 and 22, each flip flop comprising a D input D<X> and a Q output Q<X>, and wherein each D-type flip flop has an input coupled to receive a divided clock signal and an input coupled to receive initialization and reset signals; and ten exclusive-NOR gates N<Y>each identified by an integer Y between 0 and 9, each exclusive-NOR gate comprising a first input, a second input, and an output, wherein: the ten Q outputs Q<0> to Q<9> are coupled in parallel to the respective ten D inputs D<10> to D<19>; the three Q outputs Q<10> to Q<12> are coupled in parallel to the respective three D inputs D<20> to D<22>; the ten D inputs D<0> to D<9> are coupled in parallel to the respective outputs of the exclusive-NOR gates N<0> to N<9>; the first inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<8> to Q<17>; the second inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<13> to Q<22>; and the ten Q outputs Q<0> to Q<9> comprise parallel lines on which test data comprising the parallel pseudo-random binary sequence data is generated.