Patent ID: 8732553

Claim:
A memory system comprising: a non-volatile semiconductor memory; an encoder that performs a first encoding process using unit data to generate first parity, and a second encoding process using the unit data to generate second parity; a memory interface that writes, into the non-volatile semiconductor memory, the unit data, the first parity, and the second parity; an error correction processing unit that performs a first error correction process based on the unit data read from the non-volatile semiconductor memory and the first parity corresponding to the unit data, and a second error correction process based on the unit data read from the non-volatile semiconductor memory and the second parity corresponding to the unit data; an error correction history recording unit which records error correction history indicating whether the first error correction process is not successful by the error correction processing unit, in association with each unit data; and an error correction processing control unit that controls the error correction processing unit to perform the first error correction process for the unit data read from the non-volatile semiconductor memory when the error correction history corresponding to the unit data is not recorded or indicates that the first error correction process was successful, controls the error correction processing unit to perform the second error correction process for the unit data when the first error correction process is not successful, and controls the error correction processing unit to perform the second error correction process for the unit data read from the non-volatile semiconductor memory without performing the first error correction process for the unit data when the error correction history corresponding to the unit data indicates that the first error correction process was not successful.