Patent ID: 8705266

Claim:
A semiconductor memory device comprising: a plurality of first interconnects which extend in a first direction and are arranged in a second direction perpendicular to the first direction; a plurality of second interconnects which extend in the second direction and are arranged in the first direction; memory cells formed in regions where the first and the second interconnects cross; a plurality of first drivers which apply voltages to the first interconnects, respectively; a plurality of second drivers which apply voltages to the first drivers and which apply a first voltage to the first driver connected to one selected from the first interconnects, apply a second voltage not lower than the first voltage to the first drivers connected to the first interconnects adjacent to the selected first interconnect, and apply a fourth voltage lower than the first voltage and higher than a third voltage, the third voltage is lower than the first voltage, to the first drivers connected to the first interconnects adjacent to the selected first interconnect when applying the third voltage to the first driver connected to the selected first interconnect.