Patent ID: 7269049

Claim:
A ferroelectric random access memory device comprising: a memory cell array having a plurality of ferroelectric memory cells in a matrix, each including a transistor for charge transfer gate; a first bit line connected to one terminals of the plurality of ferroelectric memory cells; a word line connected to gates of the transistors of the plurality of ferroelectric memory cells; a cell plate line connected to the other terminals of the plurality of ferroelectric memory cells; a second bit line paring with the first bit line; a reference voltage supply circuit connected to the second bit line, and supplying a reference voltage to the second bit line; and a data read circuit connected to the first and second bit lines, the data read circuit including: a sense amplifier having a pair of sense nodes connected to the first and second bit lines, and comparing and amplifying each voltage of the first and second bit lines; and a current mirror circuit having a pair of current input nodes or a pair of current output nodes connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit lines to the other bit line.