Patent ID: 7646070

Claim:
A structure, comprising: (a) a substrate; (b) a semiconductor fin region on top of the substrate; (c) a gate dielectric region on side walls of the semiconductor fin region; (d) a gate electrode region on top walls and on said side walls of the semiconductor fin region, wherein the gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region; and (e) a spacer layer on top of the substrate, the semiconductor fin region, and the gate electrode region, wherein the spacer layer comprises (i) a damaged region on side walls of the semiconductor fin region and (ii) an undamaged region on side walls of the gate electrode region, and wherein the damaged region comprises a material which is not present in (i) the undamaged region, (ii) the semiconductor fin region, and (iii) the gate electrode region.