Patent ID: 8364926

Claim:
An apparatus that exchanges data with a memory controller over a data path having a width, the apparatus comprising: a first rank of memory; a second rank of memory; the first and second ranks of memory each operable to communicate data with the memory controller over the data path; where each of the first rank of memory and the second rank of memory are operable in a selective one of a rank-wide access mode, in which the first rank of memory and the second rank of memory exchange first and second data respectively at mutually exclusive times with the memory controller, where the first and second data each occupy more than half the width of the data path, and a sub-rank access mode, in which a first subrank of the first rank of memory and a first subrank of the second rank of memory exchange third and fourth data, respectively, at mutually exclusive times with the memory controller over a first subset of the width of the data path, and in which a second subrank of the first rank of memory and second subrank of the second rank of memory exchange fifth and sixth data, respectively, at mutually exclusive times with the memory controller over a second subset of the width of the data path, the third, fourth, fifth and sixth data each occupying no more than half of the data path width, the third data associated with an independent memory command from the fifth data and the fourth data associated with an independent memory command from the sixth data.