Patent ID: 8110466

Claim:
A method of forming an integrated circuit structure, the method comprising: providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to form first trenches in the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer over the semiconductor substrate and over the active region, wherein a pattern of the second mask layer is defined using the second lithography mask, and wherein the second mask layer comprises a plurality of mask strips parallel to each other; forming a third mask layer over the second mask layer, wherein a pattern of the third mask layer is defined using the third lithography mask, and wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to form second trenches in the semiconductor substrate through the opening in the third mask layer.