Patent ID: 7640413

Claim:
An interface circuit for a mixed-mode memory device, comprising: an asynchronous operation command detection circuit operable to receive a command signal and generate an asynchronous memory operation activation signal in response to receipt of the command signal corresponding to a request for a memory operation; a synchronous operation command detection circuit operable to receive a command signal and generate a synchronous memory operation activation signal in response to receiving the command signal; a delay circuit coupled to the asynchronous operation command detection circuit and the synchronous operation command detection circuit, the delay circuit operable to receive the asynchronous memory operation activation signal and to generate an output signal after a time delay from receiving the asynchronous memory operation activation signal, the delay circuit further operable to prevent the output signal from being generated in response to receiving the synchronous memory operation activation signal before the time delay ends; and a logic circuit coupled to the synchronous operation command detection circuit and the delay circuit, the logic circuit operable to generate a memory access signal in response to receiving the output signal and the memory access signal in response to receiving the synchronous memory operation activation signal.