Patent ID: 7397279

Claim:
A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the circuit comprising: an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith; a latch circuit coupled to the input stage and operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage; and a voltage clamp circuit connected between the input stage and the latch circuit, the voltage clamp circuit being operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies; wherein the voltage clamp circuit comprises a reference selection circuit operative to receive at least first and second reference signals having first and second amplitudes, respectively, associated therewith, and to select one of the at least first and second reference signals as an output signal of the reference selection circuit based at least in part on the voltage difference between the first and second voltage supplies, the voltage across the input stage being a function of the output signal of the reference selection circuit.