Patent ID: 7425741

Claim:
A non-volatile memory (NVM) cell structure formed in a semiconductor substrate and adapted for performing NVM cell operations including program and erase operations, the NVM cell structure comprising: an MOS storage transistor that includes a conductive floating gate formed over an upper surface of the semiconductor substrate and separated therefrom by intervening gate dielectric material; a second layer of dielectric formed over the conductive floating gate, the second layer of dielectric material comprising a layer of silicon oxide formed on an upper surface of the conductive floating gate, a layer of silicon nitride formed on the layer of silicon oxide, a first layer of PETEOS formed on the layer of silicon nitride, a layer of SAPSG formed on the first layer of PETEOS, and a second layer of PETEOS formed on the layer of SAPSG; and a conductive shield plate formed over the second layer of dielectric material and over the conductive floating gate, the conductive shield plate adapted to receive a biasing signal during the performance of the NVM cell operations.