Patent ID: 8344443

Claim:
A single-poly non-volatile memory device formed over a substrate, comprising: a PMOS select transistor comprising a select gate formed over a select gate dielectric layer, and P+ source and drain regions formed in a shared n-well region of the substrate; a PMOS floating gate transistor serially connected to the PMOS select transistor, where the PMOS floating gate transistor comprises a first part of a p-type floating gate layer formed over a floating gate dielectric layer, and P+ source and drain regions formed in the shared n-well region of the substrate; and a coupling capacitor formed over a p-well region of the substrate and connected to the PMOS floating gate transistor, comprising a first capacitor plate formed with a second part of the p-type floating gate layer, a capacitor dielectric layer, and a second capacitor plate formed with an underlying portion of the p-well region.