Patent ID: 8518772

Claim:
A fabricating method of a semiconductor device, comprising: forming an interlayer insulation layer on a substrate, the interlayer insulation layer including a storage node contact plug; forming an etch stop layer on the interlayer insulation layer, the etch stop layer including a silicon layer or a silicon germanium layer; forming a molding insulation layer on the etch stop layer; forming a hole in the molding insulation layer by selectively etching the molding insulation layer until a portion of the etch stop layer is exposed; forming a first conductive layer conformally on an inner surface of the hole and on a top surface of the molding insulation layer; forming a metal silicide pattern in a predetermined area of the etch stop layer exposed by the molding insulation layer by annealing the first conductive layer and the etch stop layer; after forming the metal silicide pattern, forming a second conductive layer on the first conductive layer; and after forming the metal silicide pattern and before forming the second conductive layer, removing the first conductive layer.