Patent ID: 8214415

Claim:
An interpolator in a system where a stream of respective values of at least a first command signal is communicated across a communications medium according to a predefined update rate, the interpolator comprising: a processing device comprising circuitry configured to implement a first interpolator stage, the first interpolator stage comprising: a first subtractor configured to subtract a predicted value of the first command signal from a corresponding value of the first command signal communicated across the communications medium; a first zero-order hold coupled to receive an output signal from the first subtractor, the first zero-order hold responsive to a sample signal indicative of when fresh values of the first command signal and a second command signal have been received from the communications medium, wherein the second command signal is a time derivative of the first command signal; a first corrector coupled to receive an output signal from the zero-order hold to generate a correction signal; a first adder configured to add the correction signal to a second signal received by the first adder to generate a corrected signal; and a first integrator coupled to receive the corrected signal, the integrator configured to calculate at a higher rate relative to the update rate to generate at least one interpolated prediction of the first command signal.