Patent ID: 7811893

Claim:
A method of manufacturing a MOS transistor, comprising: forming a trench isolation structure of insulating material defining and surrounding an active area within a semiconductor substrate; forming a stress adjuster adjacent the active area within the trench isolation structure at a location between adjacent trench regions of the trench isolation structure; forming a gate structure over the active area; and forming source/drain regions on opposite sides of the gate structure within the active area; whereby a channel region is defined between the source/drain regions under the gate structure; and the stress adjuster acts to increase or decrease compressive stress imparted from the isolation structure to the channel region; and wherein the stress adjuster is formed by covering a part of the substrate between adjacent trench region portions of the trench isolation structure, with the adjacent trench region portions left uncovered; etching the uncovered adjacent trench region portions; and filling the etched adjacent trench region portions with insulating material; the covered part of the substrate being left unetched between the etched and filled adjacent trench region portions.