Patent ID: 7376777

Claim:
A computer system, comprising: an N-bit Digital Signal Processor (DSP) that generates an N-bit write transaction for modifying an N-bit word at an 2×N-bit data location of an N-bit peripheral; a first bus including an N-bit wide data bus, coupled to the N-bit DSP; at least one peripheral including a 2×N-bit-only peripheral, the 2×N-bit-only peripheral having data locations, each data location having a width of 2×N bits, the 2×N-bit-only peripheral being incapable of accepting any N-bit write transactions; a second bus including a 2×N bit wide data bus, coupled to the 2×N-bit-only peripheral; and a bridge coupled between the first bus and the second bus, the bridge including a write merge system, the write merge system including: first logic circuits for receiving new N-bit wide data and for receiving an N-bit write transaction from the N-bit DSP, the N-bit write transaction being for modifying an N-bit word of a 2×N-bit word at a 2×N-bit data location of the 2×N-bit-only peripheral, and second logic circuits for writing a 2×N-bit word to said 2×N-bit data location of the 2×N-bit-only peripheral, the 2×N-bit word including said N-bit word modified by the new N-bit wide data, in which the second logic circuits perform a single write of 2×N bits that changes only said N-bit word that was being modified by the N-bit write transaction.