Patent ID: 8492286

Claim:
A method of forming an electronic fuse comprising: forming a polysilicon structure on top of a semiconductor substrate; implanting at least one dopant into said polysilicon structure to create a doped polysilicon layer in at least a top portion of said polysilicon structure; subjecting said doped polysilicon layer to a reactive-ion-etching (RIE) process, said doped polysilicon layer being substantially unaffected by said RIE process; and converting said polysilicon structure including said doped polysilicon layer into a silicide to form said electronic fuse, wherein subjecting said doped polysilicon layer to said RIE process further comprises removing a cap layer on top of a sacrificial gate electrode of a transistor, wherein said transistor is formed on said semiconductor substrate thereupon said polysilicon structure is formed and wherein said removing removes, at most, a fraction of said doped polysilicon layer with rest of said doped polysilicon layer covering rest of said polysilicon structure, and subsequently applying said RIE process in removing selectively said sacrificial gate electrode of said transistor.