Patent ID: 8473728

Claim:
A method for handling interrupts of multiple instruction threads within a multi-thread processing environment, the method comprising: interleavingly fetching and issuing instructions of a plurality of instruction execution threads for execution by an execution block of the multi-thread processing environment, wherein the plurality of instruction execution threads comprises (i) a subset of the plurality of instruction execution threads and (ii) a first instruction execution thread that is not included in the subset of the plurality of instruction execution threads; for each of the plurality of instruction execution threads, providing a corresponding interrupt signal via a corresponding interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the corresponding instruction execution thread, such that a plurality of interrupt signals via a corresponding plurality of interrupt signal lines are provided for the corresponding plurality of instruction execution threads; masking the subset of the plurality of instruction execution threads, such that each of the subset of the plurality of instruction threads ignores the corresponding interrupt signal; and in response to masking the subset of the plurality of instruction execution threads, processing, by the first instruction execution thread, one or more interrupt signals corresponding to one or more instruction execution threads of the subset of the plurality of instruction execution threads, wherein the plurality of interrupt signal lines are physically separate and distinct signal lines.