Patent ID: 7282969

Claim:
A low divide ratio programmable frequency divider comprising: a divide ratio assigner for assigning divide data as a main divide ratio and a pulse swallow value according to a first divide operation mode or a second divide operation mode in response to a mode selection signal, wherein 2 bits of the divide data are assigned as the pulse swallow value; a prescaler for operating on the first divide operation mode or the second divide operation mode in response to the mode selection signal, dividing an oscillation frequency by N or N+1 in response to a pulse swallow signal in the first divide operation mode, and dividing the oscillation frequency by P, P+1 or P+2 in response to a lowest bit, a divide oscillation frequency, an output signal thereof and the pulse swallow signal in the second operation mode; a main counter for dividing a frequency from the prescaler by the main divide ratio; and a pulse swallow counter for counting a clock of the main counter while outputting the pulse swallow signal to the prescaler, the pulse swallow signal having a swallow level if a counting value corresponds to the pulse swallow value, and having a non-swallow level if the counting value does not correspond to the pulse swallow value.