Patent ID: 7473960

Claim:
A non-volatile memory cell including: a semiconductor body; a memory-transistor well disposed within the semiconductor body; a first switch-transistor well disposed within the semiconductor body to a first side of the memory transistor well and electrically isolated from the memory transistor well; a second switch-transistor well disposed within the semiconductor body to a second side of the memory transistor well opposite the first side and electrically isolated from the memory transistor well; a memory transistor formed within the memory-transistor well and including spaced-apart source and drain regions; a first switch transistor formed within the first switch-transistor well region and including spaced-apart source and drain regions; a second switch transistor formed within the second switch-transistor well region and including spaced-apart source and drain regions; a floating gate insulated from and self aligned with the source and drain regions of the memory transistor and the first and second switch transistors; and a control gate disposed above and self aligned with respect to the floating gate and with the source and drain regions of the memory transistor and the first and second switch transistor.