Patent ID: 7956439

Claim:
A void boundary structure, comprising: a pair of interconnections on a semiconductor substrate, wherein each of the pair of interconnections includes a plug and a line with different widths that are sequentially stacked; a void boundary layer defining a void between the pair of interconnections, covering top surfaces of the pair of interconnections, connecting the pair of interconnections on the top surfaces of the pair of interconnections, and extending downwardly from the top surfaces of the pair of interconnections into an adjacent region of the void between the pair of interconnections; and a molding layer contacting a portion of the void boundary layer in substantially the same level as the top surfaces of the pair of interconnections, and encompassing the pair of interconnections and the remaining portion of the void boundary layer between the pair of interconnections under the top surface of the pair of interconnections, wherein the void boundary layer includes a buried layer and a sealed layer, the sealed layer covering a sidewall of one of the pair of interconnections, extending to a neighboring interconnection of the pair of interconnections facing the one interconnection of the pair of interconnections and covering a sidewall of the neighboring interconnection of the pair of interconnections in order to open a space between the pair of interconnections, and the buried layer is on the sealed layer to close the space between the pair of interconnections.