Patent ID: 8502711

Claim:
A coding circuit for generating a swap tolerant code comprising: a first input configured to receive a first stream of serial data comprising a single bit in each timeslot of a plurality of timeslots; a second input configured to receive a second stream of serial data comprising a single bit in each timeslot of said plurality of timeslots; an odd parity pair detector having a third and a fourth input, said third input being connected to said first input, said fourth input being connected to said second input, said odd parity pair detector configured to output an odd parity pair signal if the bits received at said first and second inputs have different logical values; a memory being connected to said first and second inputs, said memory information on a previous odd parity pair; and an output circuit being connected to said memory and said first and second inputs, said output circuit comprising a first and second output configured to output said previous odd parity pair, if said first input provides a logical 1 and said second input provides a logical 0 and said output circuit outputting the inverted previous odd parity pair, if said first input provides a logical 0 and said second input provides a logical 1.