Patent ID: 7078805

Claim:
A semiconductor wafer comprising: a plurality of chip areas in which a number of semiconductor elements are formed; a dicing area provided at the outside of each chip area; a characteristic evaluating element formed in the dicing area; and a probe-contactable monitoring pad formed in the dicing area and electrically connected to the characteristic evaluating element; wherein the monitoring pad includes two or more exposed surfaces divided via a space that is approximately parallel to the longitudinal direction of the dicing area, the two or more exposed surfaces are electrically connected with each other via a metal wiring of an inner layer; one of the exposed surfaces is arranged in an area for cut away by a dicing blade, another of the exposed surfaces is arranged outside of the area for cut away by the dicing blade, and a space between the one and the another of the exposed surfaces includes an area for positioning a cutting line by dicing blade.