Patent ID: 7379362

Claim:
A semiconductor memory device with a hierarchical bit line structure, comprising: a plurality of subarrays arranged in a row direction and a column direction; a plurality of word lines connected to the subarrays placed on the respective same rows; a plurality of main bit lines connected to the subarrays placed on the respective same columns; a row decoder for selecting one of the word lines, based on a given row address; a column decoder for selecting one of the main bit lines, based on a given column address; and a main bit line control circuit for controlling the main bit line selected by the column decoder, wherein the subarray includes: a sub-bit line; a first switch section for switching whether or not the sub-bit line is connected to a power source voltage; a second switch section for switching whether or not the sub-bit line is connected to a ground voltage; a third switch section for switching whether or not the main bit line is connected to a predetermined power source, based on a voltage of the sub-bit line; and a plurality of memory cells for applying an influence depending on data stored therein, onto the sub-bit line, when a corresponding one of the word lines is selected.