Patent ID: 7358610

Claim:
An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and a second metallization structure over said passivation layer, wherein said second metallization structure comprises a ground plane and a signal line at a same horizontal level, wherein said signal line is separate from and enclosed by said ground plane.