Patent ID: 8327302

Claim:
A method for performing an analysis of a logic design, comprising: detecting, using one or more processors of a data processing system, an initial transient behavior in a logic design embodied in a netlist; determining, using at least one of the one or more processors, a duration of the initial transient behavior; gathering, using at least one of the one or more processors, reduction information on the logic design based on the initial transient behavior; modifying, using at least one of the one or more processors, the netlist based on the reduction information; decomposing, using at least one of the one or more processors, a verification problem for the logic design into a first phase and a second phase, wherein the first phase corresponds to a start-up phase and the second phase corresponds to a phase that occurs after the start-up phase; and minimizing, using at least one of the one or more processors, the second phase of the verification problem based on knowledge that the logic design does not exhibit transient initial behavior in the second phase.