Patent ID: 7599218

Claim:
An integrated circuit having a non-volatile memory, the integrated circuit comprising: memory cells; a memory cell selection circuit having memory cell selection blocks each including selection transistors; a first device to supply a first voltage applicable to said memory cells; a second device to supply a second voltage applicable to said memory cells; wherein: each selection block to select a memory cell includes in parallel a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device; the first sub-block only includes transistors of a first type of conductivity; the second sub-block only includes transistors of a second type of conductivity; each memory cell is linked to the first device by a path having the transistors of the first sub-block of the memory cell selection block and one or more additional transistors in series with the transistors of the first sub-block, and is linked to the second device by a path having the transistors of the second sub-block of the memory cell selection block and one or more additional transistors in series with the transistors of the second sub-block; and the additional one or more transistors in series with the first sub-block is or are of same type of conductivity as the transistors of the first sub-block, and the additional one or more transistors in series with the second sub-block of the selection block is or are of same type of conductivity as the transistors of the second sub-block.