Patent ID: 7393721

Claim:
A method of providing a selected one of two different electrical circuits from a single semiconductor chip comprising: providing a semiconductor chip having formed therein a first one of said two different electrical circuits, said provided semiconductor chip comprising at least an upper metallization layer and a lower metallization layer supported by an insulating layer, said upper metallization layer defining an aperture there through and said lower metallization layer defining an interconnect structure including at least one of a conductive line for providing an electrical connection, or a pair of adjacent conductive lines electrically isolated from each other directly below said aperture in said upper metallization layer, said semiconductor top further comprising a passivation layer formed over said upper metallization layer and defining an opening therein, said opening above a portion of said upper metallization layer defining said aperture; and directing a FIB at said at least one of said conductive lines or said pair of adjacent conductive lines; selectively melting a portion of said at least one of said conductive line to interrupt said electrical connection or melting portions of said pair of adjacent conductive lines to form an electrical connection therebetween.