Patent ID: 7940097

Claim:
An all digital phase locked loop circuit, comprising: a reference frequency indicator, for receiving a reference signal and for generating a frequency indicating value in response to the reference signal, wherein the reference signal has a reference frequency; a phase frequency detector, comparing the reference signal with a frequency divided signal, and generating a phase difference pulse; a time-to-digital circuit, receiving the phase difference pulse and a plurality of output signals, and generating a phase difference value; a digital controller, receiving the phase difference value and the frequency indicating value, and generating a control value; a delta-sigma modulator, modulating the control value and generating a modulated control value in response to the control value; a digital controlled oscillator (DCO), receiving the modulated control value and outputting an output oscillating signal in response to the modulated control value, wherein the output oscillating signal has a digital controlled frequency; a frequency divider, receiving the output oscillating signal and dividing the digital controlled frequency of the output oscillating signal by a divisor to generate the frequency divided signal; and a multi-phase generator, receiving the output oscillating signal and generating the plurality of output signals in response to the output oscillating signal, wherein there is a fixed phase difference existed between the plurality of output signals.