Patent ID: 7405117

Claim:
A method of fabricating a transistor having a source region, a drain region and a gate region on a substrate, the method comprising: implanting, into a surface of the substrate, a high voltage (HV) n-doped n-well with a first volume and a first surface area; forming a gate oxide between a source region and a drain region of the transistor; implanting, into the source region of the transistor, a p-doped p-body with a second volume and a second surface area after forming the gate oxide; covering the gate oxide with a conductive material; forming a source-side oxide spacer and a drain-side oxide spacer on sidewalls of the gate oxide; implanting, into the source region of the transistor, a n-doped n+ region with a third volume and a third surface area and a p-doped p+ region with a fourth volume and a fourth surface area; implanting, into the drain region of the transistor, a n-doped n+ region with a fifth volume and a fifth surface area; and implanting, into the drain region of the transistor, a n-doped lightly doped drain that is shallower than the n-doped n+ region and having a portion which extends beneath the drain-side oxide spacer, the n-doped lightly doped drain having a sixth volume and a sixth surface area.