Patent ID: 7523428

Claim:
A method of generating a block model for a signal integrity (SI) analysis, the method comprising: generating an interface logic model (ILM) for a block, wherein the generating the ILM includes: determining cells in a timing path that starts at an input port and ends at an output port; determining cells in a timing path that starts at an input port and ends at an edge-triggered register; determining cells in a timing path that starts at an edge-triggered register and ends at an output port; and determining any clock tree driving an edge-triggered register forming part of the ILM; and adding identified internal nets of the block to the ILM, the identified internal nets being affected by cross-coupling, thereby providing an improved SI analysis at chip level, wherein the adding identified internal nets includes: determining a cross-coupling effect of an internal net in the block on an interface net of the block; and determining a cross-coupling effect of an internal net of the block on an external net to the block.