Patent ID: 8005880

Claim:
A logic circuit comprising: a latch having N bits of a data word, each bit having a unique bit position; a data correction circuit connected to each of the N bit positions of the latch and adjusting the latch data word to remove any single bit variance within a consecutive equal value bit sequence and providing the adjusted data, said adjusted data having N bit positions; a consecutive equal value sequence count circuit connected to data of every other bit position of said adjusted data and providing output data having a word width of less than N bits, wherein said consecutive equal value sequence count circuit output data is a number of counted consecutive equal value sequence bits of every other bit of said adjusted data; a single bit correction circuit connected to each bit of the data correction latch circuit and logically combining every bit of said adjusted data and providing having a single bit output; and a bit assembly concatenating the single bit output to the consecutive equal value sequence count circuit output, wherein said assembly provides an output data word representing a number of consecutive equal value sequence bits of the latch data word.