Patent ID: 7292430

Claim:
A multi-layer chip capacitor comprising: a capacitor body formed by stacking a plurality of dielectric layers; a plurality of first and second internal electrodes respectively formed on the dielectric layers, the first and second internal electrodes being separated by the dielectric layers and alternately arranged inside the capacitor body, wherein each of the internal electrodes has at least one opening formed at one or more sides thereof; first and second conductive vias, vertically extended to pass through the openings of the second and first internal electrodes, respectively, so as not to contact peripheral edges of the openings, the first and second conductive vias being electrically connected to the first and second internal electrodes, respectively; first and second terminal electrodes formed on one or more side faces of the capacitor body, the first and second terminal electrodes having a first polarity and a second polarity opposite to the first polarity, respectively; and first and second lowermost electrode patterns being coplanar on a dielectric layer inside the capacitor body, each of the patterns including a via contact portion and a lead portion extending therefrom, the first and second lowermost electrode patterns being electrically connected to the first and second terminal electrodes of the opposite polarities, respectively, through the respective lead portions of the lowermost electrode patterns, wherein the first and second conductive vias are in contact with the via contact portions of the first and second lowermost electrode patterns, respectively, and electrically connected to the first and second terminal electrodes through the first and second lowermost electrode patterns, respectively.