Patent ID: 7478030

Claim:
An apparatus for clock stabilization detection for hardware simulation, comprising: a digital clock module for receiving an input clock signal and a feedback clock signal and for providing an output clock signal, the digital clock module configured to lock the feedback clock signal relative to the input clock signal and configured to produce a least common multiple (LCM) clock signal and a lock signal; a state machine for receiving the lock signal and the LCM clock signal and configured to change state of a control signal at least partially responsive to the LCM clock signal and the lock signal; and a select circuit for receiving the control signal and the output clock signal and configured to mask application of the output clock signal responsive to a first state of the control signal and to unmask the application of the output clock signal after the output clock signal is sufficiently stabilized as indicated by a second state of the control signal by the state machine for the hardware simulation to commence.