Patent ID: 8552500

Claim:
A structure, comprising: a semiconductor substrate having a first type of conductivity and a top surface; an insulating layer disposed over the top surface; a semiconductor layer disposed over the insulating layer; a plurality of transistor devices disposed upon the semiconductor layer, each transistor device comprising a source, a drain and a gate stack defining a channel between the source and the drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity; a well region formed adjacent to the top surface of the substrate and underlying the plurality of transistor devices, the well region having a second type of conductivity and extending to a first depth within the substrate; first isolation regions between adjacent transistor devices and extending through the semiconductor layer to a depth sufficient for electrically isolating the adjacent transistor devices from one another; and second isolation regions between selected adjacent transistor devices, the second isolation regions extending through the semiconductor layer, through the insulating layer and into the substrate to a second depth that is greater than the first depth to electrically separate the well region into a first well region and a second well region; further comprising a first contact connected to the first well region for electrically connecting the first well region to a first bias potential and a second contact connected to the second well region for electrically connecting the second well region to a second bias potential.