Patent ID: 8391054

Claim:
A method of making a multi-state current-switching magnetic memory element comprising: depositing a first pinning layer on top of a bottom electrode; depositing a first magnetic tunneling junction (MTJ) of a stack of MTJs on top of the first pinning layer; forming a non-magnetic layer on top of the first MTJ wherein the non-magnetic layer is formed of a material selected from a group comprising: Nickel niobium (NiNb), Nickel phosphorous (NiP), Nickel vanadium (NiV), Nickel bororn (NiB) and copper-zirconium (CuZr); forming a second MTJ on top of the non-magnetic layer, each of the first and second MTJs of the stack having a unique resistance associated therewith, the stack capable of storing more than one bit of information, each of the first and second MTJs of the stack including a barrier layer having a thickness associated therewith, each of the at least two MTJs further including a free layer and a fixed layer, the barrier layer of the first MTJ of the stack directly contacting and formed on top of the fixed layer of the first MTJ of the stack and the free layer of the first MTJ of the stack directly contacting and formed on top of the barrier layer of the first MTJ of the stack, the non-magnetic layer directly contacting and formed on top of the free layer of the first MTJ of the stack, the free layer of the second MTJ of the stack directly contacting and formed on top of the non-magnetic layer and the barrier layer of the second MTJ of the stack formed on top of the free layer of the second MTJ of the stack and the fixed layer of the second MTJ of the stack directly contacting and formed on top of the barrier layer of the second MTJ of the stack, the barrier layer of each of the first and second MTJ of the stack having a thickness that is different from the thickness of the barrier layers of all of the other MTJs of the stack, the thickness of the barrier layer of each of the first and second MTJs of the stack being at least in part indicative of the resistance of each of the MTJs of the stack, the stack being capable of storing one bit in each of the MTJs of the stack; depositing a second pinning layer on top of the second MTJ of the stack; and depositing a top electrode on top of the second pinning layer.