Patent ID: 6953699

Claim:
A method for in situ electrical testing of a flip-chip semiconductor assembly during its manufacture, the method comprising: providing one or more integrated circuit (IC) dice, each with a surface having interconnection bumps thereon; providing a substrate with conductive pads deposited on a surface thereof for flip-chip attachment to the interconnection bumps of the one or more IC dice; providing an in situ electrical test socket for connection to the substrate; inserting the substrate into the in situ electrical test socket; positioning the one or more IC dice on the surface of the substrate with the interconnection bumps of the one or more IC dice in conductive contact with the conductive pads of the substrate to form the flip-chip semiconductor assembly while the subtrate remains inserted into the un situ electrical test socket; electrically testing the flip-chip semiconductor assembly using the in situ electrical test socket while the subtrate is inserted into the in situ electrical test socket and the one or more IC dice are positioned on the surface of the subtrate, and before sealing of the one or more IC dice; repairing the flip-chip semiconductor assembly if it fails the electrical testing; and sealing the one or more IC dice of the flip-chip semiconductor assembly.