Patent ID: 7511985

Claim:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in rows and columns, each memory cell including a variable resistor element of a two-port structure capable of storing a data by shifting an electric resistance from a first state to a second state when a first writing voltage is applied to both ends of the variable resistor element and shifting the electric resistance from the second state to the first state when a second writing voltage is applied to both ends of the variable resistor element, and a selecting transistor connected at either its source or drain to one end of the variable resistor element, wherein the memory cell has such a writing time characteristic that a second writing time required for shifting the electric resistance from the second state to the first state by applying the second writing voltage is longer than a first writing time required for shifting the electric resistance from the first state to the second state by applying the first writing voltage, a second number of the memory cells subjected at once to a second writing action of shifting the electric resistance from the second state to the first state is greater than a first number of the memory cells subjected at once to a first writing action of shifting the electric resistance from the first state to the second state when some or entire of the memory cells in the memory cell array are selected, and at least the second number of the memory cells is two or more between the first number and the second number of the memory cells.