Patent ID: 7596706

Claim:
A disk array system, comprising: a channel adapter board being adapted to be coupled to a plurality of host computers and comprising a channel adapter large scale integrated circuit (LSI) for controlling to transfer data received from each of the plurality of host computers; a cache board comprising a cache LSI for controlling to store data temporarily; a disk adapter board comprising a disk adapter LSI for controlling to store data in a plurality of disk drives; a switch board being coupled to the channel adapter board, the cache board and the disk adapter board, and comprising a switch LSI for controlling to transfer data among the channel adapter board, the cache board and the disk adapter board; and the plurality of disk drives storing data received from the disk adapter board, wherein each of the channel adapter LSI, the cache LSI, the disk adapter LSI and switch LSI is configured from a single LSI package having a single LSI chip and a plurality of voltage conversion circuits, wherein the single LSI chip comprises an internal logic circuit, a power supply control circuit and a plurality of module control circuits, wherein each of the plurality of voltage conversion circuits converts voltage applied from an external power supply to internal voltage for driving the internal logic circuit in the single LSI chip, wherein each of the plurality of module control circuits controls to supply the voltage converted by one of the plurality of voltage conversion circuits to the internal logic circuit, monitors status of the one of the plurality of voltage conversion circuits, and outputs error information to the power supply control circuit, when an abnormality of the one of the plurality of voltage conversion circuits occurs, wherein the. power supply control circuit outputs signals to the plurality of module control circuits to turn on/off the plurality of voltage conversion circuits, monitors status of each of the plurality of voltage conversion circuits by using the plurality of module control circuits, and outputs information of operational status of each of the plurality of voltage conversion circuits to the internal logic circuit, and wherein the internal logic circuit is configured to operate in a LSI high-load mode, in which the internal logic circuit performs high load of data transfer, when the internal logic circuit is powered on and does not perform any load of data transfer, so as to check whether power is supplied from each of the plurality of voltage conversion circuits to the internal logic circuit.