Patent ID: 6845335

Claim:
A semiconductor chip manufacturing method, comprising: analyzing specifications of an ISA of a processor; preparing data required for generating test vectors by use of a result of the analyzing; generating test vectors by use of the data; testing operations of the processor as simulated by a simulator program with the test vectors; synthesizing a logic of the processor having been tested; generating a layout by use of a result of the synthesizing; generating a mask by use of a result of the layout; and generating a wafer by use of the mask, wherein the generating of the test vectors comprises: determining an exception avoiding condition which a set of source error avoiding operands must satisfy in order to avoid invoking an exception of a processor under test by use of operand information, an operation description, and mnemonics; determining an exception avoiding region comprising the set of the source error avoiding operands; and obtaining from the exception avoiding region a plurality of source error avoiding operand values close to an exception invoking region comprising a set of source error.