Patent ID: 7439124

Claim:
A method of manufacturing a semiconductor device, comprising: forming a substrate protection film so as to cover an n-type FET forming region having a first gate electrode formed on a semiconductor substrate and a p-type FET forming region having a second gate electrode formed on said semiconductor substrate; opening said p-type FET forming region by patterning a resist film after the resist film is formed so as to cover said n-type FET forming region and said p-type FET forming region; exposing a surface of said semiconductor substrate by selectively removing said substrate protection film in said p-type FET forming region, so as to leave said substrate protection film on side walls of said second gate electrode; forming a pair of p-type extension regions in the vicinity of a surface of said semiconductor substrate at both sides of said second gate electrode by doping impurities to said semiconductor substrate, with said resist film, said second gate electrode, and said substrate protection film formed on the side walls of said second electrode serving as masks; and removing said resist film formed on said n-type FET forming region, wherein a portion of the substrate protection film over the n-type FET forming region remains over an n-type diffusion layer away from side walls of the first gate electrode.