Patent ID: 7148760

Claim:
A method comprising: providing a VCO output signal of a voltage controlled oscillator to a phase detector module of a phase locked loop PLL, wherein a frequency of said VCO output signal is divided by an adjustable number determined by a divider control signal thus generating a divided VCO output signal, said adjustable number being equal to or larger than one; providing a reference frequency signal comprising a stable reference frequency corresponding to said frequency divided by said adjustable number to said phase detector module; generating a PD error signal by a phase detector module in response to said divided VCO output signal, further in response to said reference frequency signal and in response to said divider control signal, wherein a VCO tuning voltage signal is one of: a) said PD error signal, and b) said PD error signal filtered by a low-pass filter; generating a calibration signal and said divider control signal by a calibration control module in response to said VCO tuning voltage signal according to a predetermined criterion; and providing said VCO tuning voltage signal and said calibration signal to said voltage controlled oscillator for implementing gain tuning of said VCO output signal of said voltage controlled oscillator according to said predetermined criterion.