Patent ID: 8299823

Claim:
An integrated circuit comprising: a reset input and one or more mux select inputs; a combinatorial reset logic comprising one or more inputs and one or more outputs, wherein the one or more inputs of the combinatorial reset logic are operatively coupled with the reset input and with the one or more mux select inputs; a tri-state clock mux with a first pair of inputs, a second pair of inputs, a first output, and a second output, wherein the tri-state clock mux is operatively coupled with the one or more outputs of the combinatorial reset logic; a divide-by-two quadrature divider comprising one or more outputs, a first clock input pair, a second clock input pair, a first latch with outputs and data inputs, and a second latch with outputs and data inputs, wherein the divide-by-two quadrature divider first and second clock input pairs are operatively coupled with the tri-state clock mux first and second outputs, respectively; and a pull-up device and a pull-down device, wherein the pull-up and pull-down devices are operatively coupled with the tri-state clock mux first and second outputs respectively, and wherein the pull-up and pull-down devices are operatively coupled with the first and second clock input pairs of the divide-by-two quadrature divider.