Patent ID: 7897501

Claim:
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers, each spacer comprising a first inner spacer and an second outer spacer on sidewalls of the gate stack, wherein the first inner spacer is formed directly on the sidewall of the gate stack and adjacent the semiconductor substrate and the second outer spacer covers a sidewall of the first inner spacer and adjacent a bottom portion thereof; conformably and sequentially forming a third insulating liner layer and a fourth insulating layer covering the gate stack and the spacers, wherein the third insulating liner layer comprises substantially the same material as the first inner spacer and the fourth insulating layer comprises substantially the same material was the second outer spacer; removing a part of the fourth insulating layer covering the gate stack and upper surfaces of the spacers to form fourth outer spacers over sidewalls of the spacers, wherein the semiconductor substrate is covered by the third insulating layer to avoid lattice crystal destruction; and removing the third insulating layer not covered by the fourth outer spacers to form the third inner spacers after forming the fourth outer spacers, thereby forming a protective layer on a part of the sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.