Patent ID: 8339206

Claim:
A Phase Lock Loop (PLL) comprising: A phase comparator which compares phases of a reference clock and a feedback clock and outputs phase-difference signal; a charge-pump equalizer, which includes a plurality of charge pumps, the plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds the charge currents generated by the plurality of charge pumps, and outputs the added charge current; a loop filter which generates a control voltage according to the charge current; a voltage controlled oscillator which generates an output clock having a frequency corresponding to the control voltage; a divider which divides the output clock to generate the feedback clock; a replica circuit, which includes a digital filter, the digital filter having ideal characteristics of the loop filter and the voltage controlled oscillator, inputting in a phase-difference digital value having phase difference of the phase-difference signal, and generating a replica output according to the ideal characteristics, and outputs a difference signal based on the replica output and an ideal value; and a coefficient generating circuit which smoothes correlation values of the difference signal and the phase-difference signal to generate charge pump coefficients, and negatively feeds back the charge pump coefficients to the plurality of charge pumps respectively, wherein the plurality of charge pumps generate the charge currents each having current value corresponding to each of the charge pump coefficients.