Patent ID: 8253455

Claim:
A delay locked loop circuit, comprising: a first Delay Locked Loop (DLL) core receiving an input clock signal of a first frequency; and a second DLL core receiving the input clock signal of a second frequency equal to or lower than the first frequency, wherein the first DLL core is an analog DLL core, the second DLL core is a digital DLL core and one of the first and second DLL cores operates selectively, wherein the analog DLL core includes, an analog delay circuit having at least one analog delay cell, the analog delay circuit delaying the input clock signal having the first frequency by a first delay time, an analog phase circuit configured to delay an output of the analog delay circuit by a second delay time to generate a first output signal, and a bias circuit configured to provide a bias voltage to the analog delay circuit and the analog phase circuit in response to a detection signal from a frequency detector which detects the frequency of the input clock signal, and the digital DLL core includes, a digital delay circuit having at least one digital delay cell, the digital delay circuit configured to delay the input clock signal having the second frequency by a third delay time, a digital phase circuit configured to delay an output of the digital delay circuit by a fourth delay time to generate a second output signal, and an internal power source voltage generator configured to supply a stable internal power source voltage to the digital delay circuit, the digital phase circuit, and a digital level shifter; and a selection circuit configured to select one of the first and second DLL cores, wherein the selection circuit is configured to select the first DLL core when the detection signal from the frequency detector is a first level, and the selection circuit is configured to select the second DLL core when the detection signal from the frequency detector is a second level, the second level being opposite to the first level.