Patent ID: 8319285

Claim:
A silicon-on-insulator chip comprising: a substrate layer; an insulating layer disposed on the substrate layer; a first compressively strained silicon region having a first crystal orientation and having an underlying first strained layer disposed directly on the insulating layer and which causes the strain of the first strained silicon region; and a second tensile strained silicon region substantially coplanar with but horizontally offset and isolated from the first strained silicon region with a second crystal orientation different from the first crystal orientation and having an underlying strained filloxide layer disposed directly on the insulating layer which causes the strain of the second strained silicon region; an n-channel transistor disposed on the first compressively strained silicon region, the n-channel transistor defining a gate dielectric in contact with the first compressively strained silicon region and a gate in contact with the gate dielectric; and a p-channel transistor disposed on the second tensile strained silicon region, the p-channel transistor defining a separate gate dielectric in contact with the second tensile strained silicon region and a separate gate in contact with the separate gate dielectric.