Patent ID: 8072003

Claim:
A layout of an integrated circuit device, comprising: a gate electrode level region layout that forms part of a gate electrode level of the integrated circuit device, the gate electrode level region layout including a first pair of linear shaped layout features each defined to extend lengthwise along a same first line of extent in a first direction, the first pair of linear shaped layout features separated from each other by a first end-to-end spacing, the first pair of linear shaped layout features having a first linear shaped layout feature that forms a gate electrode of a first transistor of a first transistor type, the first pair of linear shaped layout features having a second linear shaped layout feature that forms a gate electrode of a first transistor of a second transistor type, and the gate electrode level region layout including a second pair of linear shaped layout features each defined to extend lengthwise along a same second line of extent in the first direction, the second pair of linear shaped layout features separated from each other by a second end-to-end spacing, the second pair of linear shaped layout features having a third linear shaped layout feature that forms a gate electrode of a second transistor of the first transistor type, the second pair of linear shaped layout features having a fourth linear shaped layout feature that forms a gate electrode of a second transistor of the second transistor type, a first layout shape of a first conductive structure defined to electrically connect to the gate electrode of the first transistor of the first transistor type; a second layout shape of a second conductive structure defined to electrically connect to the gate electrode of the first transistor of the second transistor type; a third layout shape of a third conductive structure defined to electrically connect to the gate electrode of the second transistor of the first transistor type; and a fourth layout shape of a fourth conductive structure defined to electrically connect to the gate electrode of the second transistor of the second transistor type, wherein each of the first, second, third, and fourth conductive structures electrically connect to at least one other conductive structure formed within a level of the integrated circuit device other than the gate electrode level, wherein the first and third layout shapes respectively of the first and third conductive structures are offset from each other in the first direction.