Patent ID: 8432231

Claim:
A clock system, comprising: a first phase/frequency detector (PFD) having a first input for a reference clock and a second input for a feedback clock, and outputting a difference signal representing a phase and/or frequency difference between the reference clock and the feedback clock; a buffer coupled to the first PFD to store the difference signal over time; a digitally-controlled oscillator (DCO) comprising: a sigma-delta modulator (SDM) having a control input coupled to the buffer, an adder having inputs coupled to the (SDM) and a source of an integer control word, and a first frequency divider having a clock input for a source clock signal and a control input coupled to the adder, the first frequency divider generating an output clock as an output clock of the DCO having an average frequency representing a frequency of the source clock signal divided by (N+F/M), wherein M is a modulus of the SDM; a phase-locked loop (PLL) including a second PFD that has a first input to receive the output clock of the DCO and a second input that is phase-locked to the first input; and a second frequency divider coupled from the second input of the second PFD of the PLL to the second input of the first PFD.