Patent ID: 8423929

Claim:
A method to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code, the IC having at least one or more timing and hardware constraints, comprising: a. extracting parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; b. iteratively optimizing the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met and a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration to arrive at a customized architecture with an application specific instruction set wherein the processor architecture optimization comprises changing an instruction set, including reducing the number of instructions required and encoding the instructions to improve instruction access and decode speed, and to improve instruction memory size requirement; and c. synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication; and d. fabricating the custom integrated circuit.