Patent ID: 8792511

Claim:
A buffer memory system, comprising: a buffer memory residing in a fast pattern processor of a network device, the buffer memory including a plurality of memory locations for storage; and a controller configured to control the storage and retrieval of data from the plurality of memory locations, allocate a first portion of the plurality of memory locations of the buffer memory to a first buffer, wherein the remaining portion of the plurality of memory locations define a second portion; allocate a portion of the second portion to a second buffer and the remaining portion of the second portion defines a third portion, wherein the first buffer and the second buffer are arranged as a ring buffer; reserve a portion of the third portion for assignment to the second butler, with the second buffer assigned a higher priority over the first buffer; and selectively allocate remaining one or more memory locations of the third portion to the first buffer or to the second buffer by retaining ring buffer structure of the first buffer and the second buffer where an allocated first memory location follows an allocated last memory location in each of the first buffer and the second buffer.