Patent ID: 7940078

Claim:
A memory device, comprising: an output circuit; a calibration connector configured to receive a first voltage when an external load is connected thereto; a first calibration circuit operably coupled between the output circuit and the calibration connector, wherein the first calibration circuit includes: a first comparator operably coupled with the calibration connector, wherein the first calibration circuit is configured to generate a first averaged count signal by averaging a first plurality of count signals generated by a first counter in response to a corresponding plurality of input and output configurations of the first comparator; and a first variable impedance circuit operably coupled to the calibration connector and the counter, wherein the first voltage is responsive to the first plurality of count signals; and a second calibration circuit operably coupled with the first calibration circuit and the output circuit, wherein the second calibration circuit includes a second comparator that is configured to receive an input of a second voltage responsive to the averaged count signal.