Patent ID: 6838905

Claim:
A level shifter comprising: an input stage that outputs a first signal, and outputs a second signal in response to the first signal, the first and second signals having opposite logic states, the second signal having a maximum voltage; a pull down stage connected to a first intermediate node, a second intermediate node, and the input stage, the pull down stage pulling down a voltage on the first intermediate node when the first signal has a first logic state, and pulling down a voltage on the second intermediate node when the first signal has a second logic state, the pull down stage including: a first transistor connected to the first intermediate node, the input stage, and ground, a second transistor connected to the first intermediate node, the second intermediate node, and ground, a third transistor connected to the input stage, the second intermediate node, and ground, and a fourth transistor connected to the first intermediate node, the second intermediate node, and ground; a pull-up stage that pulls up the voltage on the first intermediate node to a level shifted voltage greater than the maximum voltage when the first signal has the second logic state, and pulls up the voltage on the second intermediate node to the level shifted voltage when the first signal has the first logic state; a first inversion circuit that outputs a voltage with a logic state, the logic state of the voltage output by the first inversion circuit being opposite to a logic state of the voltage on the second intermediate node; and a blocking circuit that has a fifth transistor connected to the first intermediate node and the pull up stage, and a sixth transistor connected to the second intermediate node and the pull up stage, the blocking circuit further includes a seventh transistor connected to the fifth and sixth transistors.