Patent ID: 8314806

Claim:
A method, comprising: recognizing that a state of a FIFO that holds data to be used to display content on a display has reached a first threshold; operating logic circuitry of said memory controller responsive to said state to cause at least a portion of a memory controller's core logic circuitry and central processing unit interface circuitry of said memory controller to receive their respective clocks by turning on one or more signals provided by a phase locked loop (PLL) circuit, and, operating logic circuitry of said memory controller responsive to said state to cause a memory that is controlled by said memory controller to use a second clock that is generated by a delay locked loop (DLL) within said memory controller; reading additional data to be used to display content on said display from said memory and putting said additional data into said FIFO; and, causing said at least a portion of said memory controller's core logic circuitry and said central processing unit interface circuitry of said memory controller to fail to receive said respective clocks by turning off said one or more signals provided by said PLL circuit and causing said memory to fail to receive said second clock.