Patent ID: 7434120

Claim:
A test mode control circuit comprising: an MRS (mode register set) controller for logically combining an MRS signal, a bank address, an MRS address and a test mode control signal to output a latch control signal wherein the latch control signal is inactivated when the test mode control signal is activated; a test mode control unit for detecting a test mode entry and a test mode exit and outputting the test mode control signal in response to the detecting result wherein the test mode control signal is activated during a test mode; and an address latch for latching and outputting an input address as the MRS address in response to the latch control signal, wherein the MRS address is outputted when the latch control signal is activated; wherein the test mode control unit includes: a test mode detecting unit for detecting the test mode entry and the test mode exit according to the MRS signal and the MRS address; a test mode selecting unit for outputting the test mode control signal of a ground voltage level when a test mode set signal is activated, and outputting the test mode control signal of a peripheral voltage level when a test mode exit signal is activated, wherein the test mode set signal is activated when the test mode detecting unit detects the test mode entry, and the test mode exit signal is activated when the test mode detecting unit detects the test mode exit; and a test mode delaying unit for latching and delaying the test mode control signal for a predetermined time.