Patent ID: 6934899

Claim:
A method of performing high-speed memory testing using a low speed tester, comprising: forming a test circuit on a memory chip on a wafer, said test circuit performing a pulse-width generator function by modifying a sync pulse on the memory chip to produce a column select signal with controlled time-on period; forming a pulse turn-off generator on a memory chip of said wafer, said pulse turn-off generator modifying a write line signal with controlled turn-off delay; enabling said test circuit by connecting a clock signal and a sync signal from said tester to said test circuit; connecting said column select signal from said tester to said pulse turn-off generator of said test circuit of said memory chip, forming a column select signal with controlled time-on period; connecting said write line from said tester to said pulse turn-off generator on a memory chip, forming a modified write line signal with controlled turn-off delay; combining said column select signal with controlled time-on period with said modified write line signal with controlled turn-off delay, creating a write recovery period of the memory chip; and testing said memory chip in said write recovery period.