Patent ID: 8270464

Claim:
A system comprising: a data decision latch (DL) comprising a decision feedback equalizer (DFE) and a data slicer and being operable to: receive an input signal from a receiver, the input signal comprising intersymbol interference (ISI) when communicated from the receiver; receive a data clock (DCLK) signal; and based on the input signal and the DCLK signal, recover data from the input signal to produce a first output signal; a boundary DL comprising a boundary slicer and excluding a DFE and being operable to: receive the input signal from the receiver; receive a boundary clock (BCLK) signal; and based on the input signal and the BCLK signal, recover boundaries between bits in the input signal to produce a second output signal; and a clock and data recovery (CDR) circuit operable to: receive the first and second output signals; and based on the first and second output signals, produce the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than 0.5 unit intervals (UIs) and greater than or equal to zero UIs.