Patent ID: 8331150

Claim:
An integrated nonvolatile static random access memory circuit formed on a substrate, the integrated nonvolatile static random access memory circuit comprising: a static random access memory cell connected to receive and retain a digital signal indicative of a data bit at a first bit line and a complementary digital signal indicative of a complementary data bit a second bit line and in communication with an SRAM word line for controlling access to the first and second bit lines; and a first EEPROM element in communication with the static random access memory cell to receive and permanently retain the digital signal from the static random access memory cell; wherein the first EEPROM element comprises: a first floating gate tunnel oxide transistor comprising an EEPROM control gate connected to an EEPROM word line for controlling activation of the first floating gate tunnel oxide transistor and a floating gate placed over a channel region between a drain and source of the first floating gate tunnel oxide transistor for permanently retaining the digital signal and placed over an insulating layer wherein the insulating layer has a first tunnel window placed in proximity to the source of the first floating gate tunnel oxide transistor for providing a path for transfer of charge between the floating gate and the source during erasing to set an erased threshold voltage level of the first floating gate tunnel oxide transistor and providing a path for transfer of charge between the floating gate and the channel for programming to set a programmed threshold voltage level of the first floating gate tunnel oxide transistor, a first select gating transistor having a drain connected to the static random access memory cell, a source connected to the drain of the floating gate tunnel oxide transistor, and a gate connected to a first select gating signal for controlling access between the floating gate tunnel oxide transistor and the static random access memory cell, and a second select gating transistor having a drain connected to the source of the floating gate tunnel oxide transistor, a source connected to a source line, and a control gate connected to a second select gating signal for controlling access between the floating gate tunnel oxide transistor and the source line.