Patent ID: 7818529

Claim:
An integrated memory control apparatus, for controlling signals transmitted between a memory and a control chip, and between the memory and a micro-processor unit, the integrated memory control apparatus comprising: a first interface decoder, coupled to the control chip through a first serial peripheral interface, configured to decode received signals; a second interface decoder, coupled to the micro-processor unit through a general transmission interface, configured to decode the received signals; and an interface controller, coupled to the first interface decoder and the second interface decoder, and coupled to the memory through a second serial peripheral interface, wherein when the first interface decoder and the second interface decoder respectively receive request signals from the control chip and the micro-processor unit, the second serial peripheral interface bridges a signal sent from the first interface decoder under control of the interface controller, then, a frequency of a first clock signal sent from the first serial peripheral interface is smaller than a frequency of a second clock signal sent from the second serial peripheral interface and the second interface decoder sends a waiting signal output from the interface controller through the general transmission interface, such that the micro-processor unit stops sending signals to the second interface decoder, wherein, the frequency of the second clock signal sent from the second serial peripheral interface is varied with time.