Patent ID: 8799623

Claim:
A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels comprise: a first level comprising a first computation block comprising a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting means, each computing node comprising: an input port; a functional unit; and an output port; the first connecting means configured to interconnect the plurality of computing nodes, wherein each computing node of the plurality of computing nodes further comprises an instruction memory configured to dynamically control the first connecting means during execution of instructions; and a second level comprising a second computation block comprising: a second data input; a second data output; and a plurality of said first computation blocks interconnected by a second connecting means for connecting a selected one of said first data output of each of said first computation blocks and said second data input to each of said first data inputs and for connecting a selected one of said first data outputs to said second data output.