Patent ID: 8222954

Claim:
A method of providing process, voltage, and temperature variation tolerance within a semiconductor device, the method comprising: generating a reference voltage by a pressure, voltage and temperature invariant voltage generator; generating a reference current in a first current path using a first operational amplifier coupled to receive the reference voltage and a voltage at a node of the first current path, the first current path extending from a reference voltage to a ground potential; conducting at least one variation tolerant current signal through a replica of a path of a differential amplifier of the semiconductor device, wherein the at least one variation tolerant current signal is generated by mirroring the reference current in the replica and the replica extends from the reference voltage to the ground potential; mirroring the at least one variation tolerant current signal to conduct a second and a third variation tolerant current signal in the semiconductor device; detecting variation within the replica using a second operational amplifier coupled to receive a voltage at a node of the replica; adjusting a magnitude of the second and third variation tolerant current signals to compensate for the detected variation; and providing an output signal from the semiconductor device in response to the adjusted magnitude of the second and third variation tolerant current signals.