Patent ID: 7592649

Claim:
A memory device with one or more cell array region and peripheral region on a semiconductor substrate, comprising: a plurality of polysilicon strips substantially parallel to each other forming a plurality of word lines on the cell array region, the plurality of polysilicon strips arranged in a plurality of interleaved groups having a first group and a second group; a first layer of conductive strips substantially parallel to each other forming a plurality of bit lines; a second layer of conductive strips substantially parallel to each other, the second layer of conductive strips overlying and coupled to the first group of polysilicon strips; a third layer of conductive strips substantially parallel to each other, the third layer of conductive strips overlying the second layer of conductive strips and being disposed in the peripheral region of the memory device; and a fourth layer of conductive strips substantially parallel to each other, the fourth layer of conductive strips overlying and coupled to the second group of polysilicon strips.