Patent ID: 8324102

Claim:
A method of forming a logic gate, the method comprising the steps of: fabricating at least one metal oxide semiconductor device on a substrate; depositing at least one first insulating layer over the device; forming a first metal layer over the first insulating layer, the first metal layer being interconnected with the device by way of one or more contacts present through the first insulating layer; depositing at least one second insulating layer over the first metal layer; forming a plurality of vias in the second insulating layer in contact with the first metal layer; depositing at least one third insulating layer over the second insulating layer, so as to cover the vias; and forming a second metal layer in the third insulating layer, by the steps of: selectively implanting ions in the third insulating layer so as to form at least one implant region over one or more of the vias, the implanted ions being configured to alter an etch rate through the third insulating layer within the implant region; etching the third insulating layer to, at the same time, form a pattern for the second metal layer both within the implant region and outside of the implant region, wherein the etch rate through the third insulating layer within the implant region is different from an etch rate through the third insulating layer outside of the implant region, and wherein the etch is performed for an amount of time needed to either etch completely through the third insulating layer within the implant region or etch completely through the third insulating layer outside of the implant region; and filling the pattern with a conductor material to form the second metal layer, wherein the second metal layer is in a non-contact position with one or more of the vias.