Patent ID: 7190017

Claim:
A semiconductor device comprising a semiconductor substrate having a memory region and a peripheral circuit region; a plurality of nonvolatile memory cells disposed in said memory region; a plurality of transistors disposed in said peripheral circuit region; a first wiring layer extending in a first direction; and a second wiring layer, insulated from said first wiring layer, extending in said first direction, wherein each said transistor is a transistor to select said memory cell, wherein each said transistor is disposed along said first direction through each isolation region, wherein a pair of diffusion layers for use as a source and a drain of said transistor are disposed in a second direction crossing said first direction, wherein said first wiring layer is electrically connected to the electrode corresponding to the odd-number-th one of a plurality of the electrodes of said transistors, and wherein said second wiring layer is electrically connected to the electrode corresponding to the even-number-th one of a plurality of the electrodes of said transistors.