Patent ID: 8233553

Claim:
A digital broadcast demodulator, which receives a tuner signal output from a tuner and carries out demodulation processing on said tuner signal by using an internal clock signal that is synchronized with a reference signal, comprising: an internal clock-signal generator to generate said internal clock signal; a clock division circuit to divide the internal clock signal from the internal clock-signal generator; an internal clock frequency controller controlling a frequency of said internal clock signal in accordance with a reception channel; a memory storing data on a channel at which a spurious signal is generated by a first internal clock signal of a first frequency, and data on a combination of said channel and a second internal clock signal of a second frequency which does not generate a spurious signal; a clock-signal switching controller configured to cause said internal clock generator to generate said first internal clock signal in the case where said first internal clock signal does not generate a spurious signal at said reception channel, and cause said internal clock generator to generate said second internal clock signal in the case where said first internal clock signal generates a spurious signal at said reception channel, in accordance with data output from said memory; and an OFDM demodulator unit of a one-segment broadcast reception module, wherein said OFDM demodulator unit includes an A/D converter circuit which receives IF signals from said tuner and performs analog/digital conversion, a demodulation processing circuit which carries out demodulation processing on a signal output from said A/D converter circuit, and an error correction circuit which carries out error correction on a signal output from said demodulation processing circuit and outputs a digital signal, and said internal clock-signal generator includes a Phase-Locked Loop (PLL) circuit which receives said reference signal and outputs said synchronized signal, and the clock division circuit which frequency-divides said synchronized signal and supplies one of said first internal clock signal and said second internal clock signal to said A/D converter circuit, said demodulation processing circuit and said error correction circuit, and wherein said internal clock frequency controller controls a dividing ratio of the clock division circuit in accordance with data output from said memory so that the clock division circuit outputs one of said first internal clock signal and said second internal clock signal based on the signal from the internal clock frequency controller.