Patent ID: 8125820

Claim:
A semiconductor memory device comprising: a memory array block including a plurality of memory cells arranged in a matrix, a plurality of bit lines including a first bit line provided with respect to a column of the memory cells, and a plurality of word lines including a first word line provided with respect to a row of the memory cells; an IO block connected to the first bit line; a decoder block connected to the first word line; and a control block provided adjacent to both the IO block and the decoder block, wherein: the IO block includes a first transistor configured to control a potential of the first bit line, and a first logic gate configured to control the first transistor, a drain or a source of the first transistor is connected to an input of the first logic gate, and a gate of the first transistor is connected to an output of the first logic gate, the semiconductor memory device further comprises a second logic gate, an output of the second logic gate is connected to the input of the first logic gate, and the second logic gate is provided inside the IO block.