Patent ID: 7805619

Claim:
A chip, comprising: a circuit comprising a pull-up section, a pull-down logic section, and an output node between said pull-up and pull-down sections; at least one sleep mode pull-up transistor comprising a PFET coupled across the pull-up section to substantially limit a voltage drop across the pull-up section during a sleep mode; and at least one footer transistor comprising an NFET coupled between the pull-down logic section and a Vss to substantially reduce sub-threshold leakage in the pull-down stack during the sleep mode, wherein the at least one footer NFET is shared by additional logic circuits, in which the circuit is part of segmentation logic in a read port circuit, wherein the circuit comprises a NAND circuit to combine the evaluated results of at least two local bit lines that are coupled to data cells through isolation drivers that provide Low data outputs during the sleep mode, the isolation drivers comprising NOR circuits with a first input coupled to a sleep mode signal and a second input coupled to a data cell.