Patent ID: 8873294

Claim:
A memory device, comprising: a memory cell array that includes a plurality of cell strings arranged in rows and columns on a substrate, one of the plurality of cell strings including at least one ground selection transistor, a plurality of cell transistors and at least one string selection transistor sequentially stacked on the substrate along a direction perpendicular to the substrate; an address decoder that is connected to the plurality of cell strings; at least one ground selection line, word lines and string selection lines that are configured provide a connection between the address decoder and the plurality of cell strings, the at least one ground selection line connected to ground selection transistors of the plurality of cell strings, the word lines connected to the plurality of cell transistors of the plurality of cell strings, the at least one string selection lines connected to string selection lines of the plurality of cell strings; a read/write circuit that is connected to the plurality of cell strings and that is configured to exchange data with an external device; and a voltage generating circuit that is configured to provide an erase voltage to the substrate and a word line erase voltage to the word lines and a ground selection line voltage to the at least one ground selection line respectively via the address decoder in an erase operation, wherein after the erase voltage and the ground selection line voltage are applied, a first rising slope of a first voltage of the at least one ground selection line is smaller than a second rising slope of a second voltage of the substrate.