Patent ID: 7332375

Claim:
A method of making an integrated circuit chip package, comprising the steps of: a) providing a leadframe which includes: a frame; a die pad connected to the frame and defining opposed first and second die pad surfaces, and at least one die pad side surface extending between the first and second die pad surfaces; a plurality of tabs connected to the frame and extending toward the die pad in spaced relation thereto, each of the tabs defining opposed first and second tab surfaces and at one tab side surface extending between the first and second tab surfaces; and a reentrant portion disposed within at least a portion of the die pad and within each of the tabs; b) placing an integrated circuit die upon the first die pad surface of the die pad; c) electrically connecting the integrated circuit die to the first tab surface of at least some of the tabs; d) applying an encapsulant material to the integrated circuit die, the first die pad surface of the die pad, the first tab surface of each of the tabs, and into the reentrant portions of the die pad and tab side surfaces, without covering the second surface of each of the tabs; e) hardening the encapsulant material; and f) plating the second tab surface of each of the tabs.