Patent ID: 7761822

Claim:
A method of generating file information in which a circuit structure including an interface block, a speed conversion circuit block and a functional circuit block is described in RTL, the method comprising: setting clock information regarding a clock condition and a clock speed to be used by the speed conversion circuit block for insertion between the interface block to be connected to an external device block and a clock circuit block; reconstructing the clock circuit block including a new clock for accommodating the insertion of the speed conversion circuit block based on the clock information set; associating connection terminal information indicating a connection relationship of connection terminals in the circuit structure with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion in response to the insertion of the speed conversion circuit block, and storing the speed conversion object information in a storage unit; extracting, based on the speed conversion object information stored, the connection terminal information of the connection terminal set as the speed conversion object from the storage unit; generating speed conversion circuit information indicating a connection relationship of the connection terminals in the speed conversion circuit block using the connection terminal information extracted; generating connection terminal information having the connection relationship of the connection terminals in the circuit structure reconstructed based on the speed conversion circuit information generated; and generating file information in which the speed conversion circuit block is inserted between the clock circuit block and the interface block based on said reconstructing of the clock circuit block and the connection terminal information generated.