Patent ID: 8640061

Claim:
A method implemented on a data processing system for circuit synthesis, the method comprising: determining a Read Only Memory (ROM) of a design of a circuit, the ROM having predefined data when the circuit is initialized; automatically generating an initialization circuit and a Random Access Memory (RAM); and automatically inserting a first register at an input side of the ROM responsive to a determination that the ROM is between second and third registers, no register existing on a path between the second and third registers before the first register is inserted, the second and third registers latching data on a same edge of a clock signal, the first and second registers latching data on different edges of the clock signal, wherein the initialization circuit and the RAM are configured to implement the ROM, wherein the initialization circuit is configured to load the predefined data into the RAM when the circuit is initialized, and wherein at least one of the determining and automatically generating is performed by a processor.