Patent ID: 8359420

Claim:
An external memory based first-in-first-out (xFIFO) apparatus, coupled to an external memory and a register bus respectively, the xFIFO apparatus comprising: an xFIFO engine, coupled to the register bus, for receiving a FIFO command from the register bus and generating a writing direct memory access (DMA) command and a reading DMA command; a writing DMA (wDMA) engine, coupled to the xFIFO engine and the external memory, for receiving the writing DMA command from the xFIFO engine and forwarding an incoming data to the external memory; a reading DMA (rDMA) engine, coupled to the xFIFO engine and the external memory, for receiving the reading DMA command from the xFIFO engine and pre-fetching a FIFO data from the external memory; a first virtual FIFO; and a second virtual FIFO; wherein the first virtual FIFO and the second virtual FIFO are coupled between the wDMA engine and the rDMA engine in parallel, the wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.