Patent ID: 8725488

Claim:
A method for adaptive voltage scaling within a processor, the method comprising: selecting a second class critical path associated with a second class of instructions of a program of the processor from a plurality of critical paths for analysis on an emulation circuit set up to emulate the selected second class critical path, wherein a first class of instructions previously executed by the processor at a first voltage and a first frequency before the program changed instruction usage on the processor to the second class instructions; starting a measurement period to measure a delay of a start signal through the emulation circuit and a measurement circuit having a tapped delay line with stored tap outputs during on-chip functional operations of the processor, wherein the selected second class critical path is representative of a worst case critical path through a second class instruction pipeline stage within the processor to be in operation during execution of the program and wherein the measured delay of the emulated selected second class critical path is less than a first class critical path delay associated with the first class instructions; and lowering the first voltage to a second voltage by a control circuit in response to the stored tap outputs during on-chip functional operations, wherein the second voltage powers the selected second class critical path and the second class instructions are executed by the processor at the second voltage and the first frequency.