Patent ID: 7491606

Claim:
A method for fabricating a semiconductor device, comprising: forming a first insulation layer including a plurality of first contact layers over a substrate; forming a second insulation layer over the first insulation layer; forming a plurality of second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer; forming an etch stop layer over the second insulation layer and the second contact layers; forming a third insulation layer over the etch stop layer; forming a hard mask over the third insulation layer, wherein the hard mask includes a material having a physical property substantially identical to that of the second contact layers; etching the third insulation layer and the etch stop layer using the hard mask as an etch mask to form a plurality of first contact holes exposing the second contact layers; etching the exposed second contact layers to form a plurality of second contact holes exposing the first contact holes; and forming bottom electrodes over the inner surface of the second contact holes.