Patent ID: 8895428

Claim:
A manufacture method of a thin film transistor array substrate, comprising steps of: A. depositing a first transparent conductive layer and a first metal layer sequentially to perform patterning for forming a common electrode, a gate electrode and a transparent electrode array; B. depositing an insulating layer, an active layer, an ohmic contact layer and a second metal layer sequentially to perform patterning for forming a source and a drain at two sides of the active layer; C. depositing a second transparent conductive layer to perform patterning for forming a source contact layer, a drain contact layer and a pixel electrode array connected to the drain contact layer; D. forming a protective layer on a trench surface of the active layer; the first transparent conductive layer and the first metal layer are sequentially deposited by sputtering in step A; a half tone mask is employed to perform patterning for forming the common electrode, the gate electrode and the transparent electrode array in step A; the insulating layer, the active layer, the ohmic contact layer and the second metal layer are sequentially deposited by chemical vapor deposition in step B; the second transparent conductive layer is deposited by sputtering in step C.