Patent ID: 7479702

Claim:
A semiconductor package comprising: a first polymer conductive film and a second polymer conductive film, each of the polymer conductive films having at least two layers of parallel and separated wires, and a polymer material between the wires; and a first chip, a second chip and a third chip, each of the chips including an electric pattern connected to a plurality of pads, wherein the pads of the first chip contact a layer of the wires of the first polymer conductive film, a layer of the wires on one side of the first polymer conductive film that is opposite to the first chip contact the pads on a top side of the second chip, the pads on a bottom side of the second chip that is on the other side of the top side of the second chip contact a layer of the wires of the second polymer conductive film, and a layer of the wires on a side of the second polymer conductive film which is opposite to the second chip contact the pads of the third chip for electrically connecting the first chip, the second chip and the third chip to each other through the first and the second polymer conductive films.