Patent ID: 8418156

Claim:
A method, comprising: loading source binary code for execution by a computer system, the computer system comprising memory and a processing unit comprising a plurality of registers and at least one store buffer; identifying, during runtime of said source binary code, a plurality of frequently executed memory instructions within said source binary code, the frequently executed memory instructions include a plurality of store instructions and a plurality of load instructions; defining a two stage commit (TSC) region that includes the frequently executed memory instructions and performing binary optimization operations on the plurality of memory instructions within the TSC region; generating entry marker code and inserting the entry marker code at the beginning of the TSC region, the entry maker code causing said processing unit to begin processing in a TSC mode; generating end marker code and inserting the end marker code at the end of the TSC region, said end maker code causing said processing unit to stop processing in a TSC mode; defining a first stage of the two stage commit (TSC) region wherein, when executed by the processing unit, the plurality of load instructions commit atomically in the first stage, and the plurality of store instructions retire in the first stage; defining a second stage of the TSC region for the frequently executed block of code, wherein the plurality of store instructions commit atomically in the second stage; and allowing at least one additional load or store memory instruction from outside of the TSC region to retire in the second stage of the TSC region.