Patent ID: 7935590

Claim:
A method of manufacturing a complementary metal oxide semiconductor transistor, comprising: providing a substrate; forming a first gate and a second gate on the substrate and forming a first gate insulating layer disposed only between the substrate and the first gate, and a second gate insulating layer disposed only between the substrate and the second gate; forming a first offset spacer around the first gate; forming a second offset spacer around the second gate; forming a disposable spacer around the second offset spacer; forming two epitaxial layers on two sides of the second gate outside the disposable spacer, wherein the step of forming the epitaxial layers comprises: forming a pattern hard mask on the first gate and part of the substrate; and performing an etching process, and the pattern mask, the second gate and the disposable spacer being used as a mask to form two recesses on two sides of the second gate; removing the pattern hard mask; and performing a SEG process to form the epitaxial layers in the recesses; removing the first offset spacer and the disposable spacer; forming two first source/drain extension areas on two sides of the first gate; and forming two second source/drain extension areas in the substrate and in the epitaxial layers outside the second offset spacer of the second gate.