Patent ID: 7294518

Claim:
A method for manufacturing a thin film transistor array panel, comprising: forming a gate line having a gate electrode on a substrate; depositing a gate insulating layer, a semiconductor layer, and a ohmic contact layer on the gate line; patterning the semiconductor layer and the ohmic contact layer; forming a drain electrode and a data line having a source electrode on the gate insulating layer and the ohmic contact layer, the drain electrode facing the source electrode with a gap therebetween; forming a passivation layer having a contact hole exposing the drain electrode; and forming a pixel electrode coupled with the drain electrode through the contact hole on the passivation layer, wherein at least one step of forming the gate line and forming the drain electrode and the data line includes stripping a photoresist layer with a photoresist stripper comprising about 5 wt % to about 20 wt % alcohol amine, about 40 wt % to about 70 wt % glycol ether, about 20 wt % to about 40 wt % N-methyl pyrrolidone, and about 0.2 wt % to about 6 wt % chelating agent.