Patent ID: 8717804

Claim:
A programmable resistance memory device comprising: a semiconductor substrate; at least one cell array, formed above the semiconductor substrate, which comprises a plurality of bit lines arranged in parallel with each other, a plurality of word lines arranged in parallel with each other in such a direction as to cross the bit lines, and memory cells connected between the bit lines and the word lines at cross points of the bit lines and the word lines, each memory cell comprising a programmable resistance element which stores a high resistance state or a low resistance state in a non-volatile manner; and a read/write circuit formed on the semiconductor substrate as underlying the cell array and connected to the bit lines and word lines, the read/write circuit being configured to apply a first write voltage to a selected one of the memory cells to set the programmable resistance element thereof at the low resistance state, the first write voltage shifted in a first direction of increasing or decreasing voltage value from a voltage applied to a non-selected memory cell, and to apply a second write voltage having a value shifted in a second direction of increasing or decreasing voltage value from the voltage applied to a non-selected memory cell that opposes that first direction of the first write voltage to the selected one of the memory cells to set the programmable resistance element thereof at the high resistance state.