Patent ID: 8799902

Claim:
An apparatus comprising: a processor including: a first processing element of a plurality of processing elements adapted to be associated with a first software entity of a plurality of software entities; monitor logic adapted to determine a utilization of a shared resource by the first processing element, the shared resource adapted to be shared by the plurality of processing elements; and priority aware management logic adapted to receive a priority level of the first software entity and to determine an operating point of the first processing element within the priority level based on the priority level of the first software entity and the utilization of the shared resource by the first processing element, wherein the operating point is to include a combination of a rate level of the first processing element and an allocation of a shared resource to the first processing element, wherein priority aware management logic further includes allocation control logic adapted to modify an allocation of a shared resource to the first processing element independent from allocation of the shared resource to the plurality of processing elements other than the first processing element, and wherein the allocation control logic includes resource control logic adapted to modify an amount of cache memory in size that the first processing element is allowed to access.