Patent ID: 8078837

Claim:
A hardware engine control apparatus comprising: a plurality of hardware engines (HWEs) connected by a control bus, each of the hardware engines executing a series of different kinds of processing; a host control device that outputs control commands for controlling operation of the HWEs to a subordinate control device; and the subordinate control device that has a register, in which the control commands from the host control device are sequentially set, and outputs the control commands set in the register to the control bus at timing based on a clock signal, wherein the HWEs operate according to the control commands output from the subordinate control device; the subordinate control device includes: a counter that is controlled to operate by the host control device and counts the clock signal; a control command register in which the control commands including a command code, IDS for identifying the HWEs that should be caused to execute the command code, and timing information in which timing for causing the HWEs to execute the command code is specified by a count value of the clock signal are rewritably set by the host control device; and a comparator that compares the timing information of the control command register with the count value of the counter and, when the timing information and the count value coincide with each other, attaches an ID to the command code and outputs the command code to the control bus.