Patent ID: 6970385

Claim:
A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of floating gate memory cell transistors arranged in a matrix, wherein each of said memory cell transistors includes: first and second diffusion regions of a second conductivity type opposite each other, with a channel region of a first conductivity type interposed therebetween, in a surface layer section of a semiconductor substrate including the non-volatile semiconductor memory device, a two-layer gate electrode having a floating gate and a control gate opposite said channel region of said first conductivity type, with a gate insulating film interposed therebetween, and an electric field buffer layer of said second conductivity type between said first diffusion region and said channel region of said first conductivity type and between said second diffusion region and said channel region of said first conductivity type, not overlapping said two-layer electrode; a control circuit controlling an erase operation of said memory cell transistors on a single unit basis, and a write-back operation after the erase operation; a voltage generating circuit receiving an external power supply voltage to generate an internal power supply voltage and supplying the internal power supply voltage to memory cell transistors on the single unit basis, to be written back in the write-back operation; and a resistance circuit connected to a source line of said plurality of memory cell transistors and causing a voltage drop due to a current flowing in said source line.