Patent ID: 7900164

Claim:
An on-chip interconnect resistance and capacitance measurement structure, comprising: a plurality of spatially adjacent interconnects; a first circuit electrically connected to a first reference capacitor and a first interconnect of the plurality of interconnects; a second circuit electrically connected to a second reference capacitor and the first circuit, the first and second circuits having a similar physical structure and an input, an output and two control terminals; a first signal generator for driving the two circuits simultaneously through their input terminals; a second signal generator for driving the two circuits through their two control terminals; and a third signal generator for driving a second interconnect of the plurality of interconnects; wherein the capacitance of the first interconnect is determined by measuring a current difference between the two circuits and the resistance of the second interconnect is determined by measuring a voltage drop between two positions having a known distance on the second interconnect when the third signal generator feeds a known current into the second interconnect.