Patent ID: 6873019

Claim:
A method for fabricating a semiconductor device, comprising: preparing a semiconductor substrate; forming a first memory cell on the semiconductor substrate, wherein the first memory cell includes a first capacitor and a first MOS transistor having a gate electrode, a source region and a drain region; forming a second memory cell on the semiconductor substrate, wherein the second memory cell includes a second capacitor and a second MOS transistor, wherein the second MOS transistor is formed in a vicinity of the first MOS transistor and has a gate electrode, a source region and a drain region, and wherein one of the source and drain regions of the first MOS transistor and one of the source and drain regions of the second MOS transistor is a shared region; forming a peripheral circuit on the semiconductor substrate, wherein the peripheral circuit includes a third MOS transistor having a gate electrode, a source region and a drain region; forming a nitride layer so as to cover the first, second and third MOS transistors; forming a side wall on the gate electrode of the third MOS transistor by etching the nitride layer on the third MOS transistor; depositing a refractory metal layer on the semiconductor substrate; and exposing the refractory metal layer to a heat treatment so as to form a refractory metallic silicide from the refractory metal and silicon on the source region and the drain region of the third MOS transistor, wherein the gate electrodes of the first, second and third MOS transistors are formed of a polycrystalline silicon, a second refractory metal and a compound made up of the second refractory metal and nitrogen, and wherein a compound layer containing the compound is sandwiched between a polycrystalline silicon layer containing the polycrystalline silicon and a second refractory metallic layer containing the second refractory metal.