Patent ID: 8558231

Claim:
An array substrate, comprising: a substrate having a thin film transistor (TFT) formed thereupon, the TFT having a gate electrode, a source electrode, and a drain electrode; a first metal layer formed on the substrate and comprising a gate line and the gate electrode of the TFT; a first insulating layer covering the first metal layer and the substrate; a semiconductor layer, an ohmic contact layer, and a second metal layer, which are sequentially formed on the first insulating layer, wherein the second metal layer comprises a data line and the source electrode and the drain electrode of the TFT, a lamination of the semiconductor layer and the ohmic contact layer constitutes an active layer, and the data line is connected to the source electrode of the TFT; a second insulating layer covering the semiconductor layer, the ohmic contact layer, and the second metal layer; and a pixel electrode provided on the second insulating layer and connected to the drain electrode, wherein the second metal layer further comprises an etch-blocking pattern in a peripheral area of the pixel electrode within an overlapping region between the pixel electrode and the first metal layer, and the etch-blocking pattern is interposed between the active layer and the pixel electrode.