Patent ID: 7960774

Claim:
A memory device comprising: a bottom electrode; one or more dielectric thin films disposed on the bottom electrode, each dielectric thin film comprising a plurality of dielectric layers with different charge trap densities from each other, wherein each of the plurality of dielectric layers is composed of: a dielectric formed of TiO 2 , ZrO 2 , HfO 2 , V 2 O 5 , Nb 2 O 5 , Ta 2 O 5 , NiO, PdO, or a material in which at least one of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Zr, Hf, Nb, Ta, Pd, and La group elements is added to TiO 2 , ZrO 2 , HfO 2 , V 2 O 5 , Nb 2 O 5 , Ta 2 O 5 , NiO, or PdO, as an impurity; a dielectric of ABO 3 type; or a dielectric consisting of a material having a perovskite structure, except the ABO 3 type, and impurities added to the material; and a top electrode disposed on the one or more dielectric thin films, the top and bottom electrodes configured to receive a voltage applied to the memory device, wherein a resistance of the one or more dielectric thin films is varied according to a voltage applied to the memory device, such that an ohmic current is generated when the applied voltage is a low voltage and a space-charge limit current is generated when the applied voltage is a high voltage, the high voltage being greater than the low voltage.