Patent ID: 7829404

Claim:
A method of forming an electrically programmable and erasable memory device in a substrate of semiconductor material of first conductivity type, comprising: forming first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region therebetween; forming an electrically conductive floating gate having a first portion disposed over and insulated from the channel region, and a second portion disposed over and insulated from the first region and including a sharpened edge; forming an electrically conductive P/E gate having a first portion disposed over and insulated from the first region, and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material; and forming an electrically conductive select gate disposed laterally adjacent to and insulated from the floating gate and disposed over and insulated from the channel region; wherein the formations of the P/E gate and select gate include: forming a layer of conductive material over the channel region, the floating gate, and the first region; and selectively etching away a portion of the conductive material to result in a pair of blocks of the conductive material that are electrically isolated from each other and that constitute the P/E gate and the select gate respectively.