Patent ID: 7304596

Claim:
A digital-to-analog converter adapted for converting an n-bit digital signal into a corresponding analog signal, the n-bit digital signal including higher-order and lower-order signal portions, said digital-to-analog converter having an output node, and comprising: a resistor string including a plurality of first resistors connected in series, said resistor string having first and second endmost nodes disposed respectively at two ends thereof, and a plurality of intermediate nodes, each disposed between a respective adjacent pair of said first resistors; a plurality of first switches, each connected between said output node and a corresponding one of said first endmost, second endmost and intermediate nodes of said resistor string; a decoding unit adapted for converting the higher-order signal portion of the n-bit digital signal into a decoder signal, the decoder signal being used to control said plurality of first switches such that one of said first switches is selected in accordance with the higher-order signal portion of the n-bit digital signal to connect the corresponding one of said first endmost, second endmost and intermediate nodes to said output node; a first voltage-setting unit adapted to be connected between a first reference voltage source and said first endmost node of said resistor string; a second voltage-setting unit adapted to be connected between a second reference voltage source and said second endmost node of said resistor string; said first voltage-setting unit includes a second switch adapted to connect the first reference voltage source to said first endmost node of said resistor string, a third switch adapted to be connected to the first reference voltage source, and a second resistor connected directly to said first endmost node of said resistor string and adapted to be connected to the first reference voltage source via said third switch; said second voltage-setting unit includes third and fourth resistors connected in series, said third resistor being further connected directly to said second endmost node of said resistor string, said second voltage-setting unit further including a fourth switch adapted to connect the second reference voltage source to one node of said fourth resistor opposite to said third resistor, and a fifth switch adapted to connect the second reference voltage source to a junction of said third and fourth resistors; and wherein said first and second voltage-setting units are operable in response to the lower-order signal portion of the n-bit digital signal to adjust voltages at said first endmost, second endmost and intermediate nodes of said resistor string according to the lower-order signal portion of the n-bit digital signal, and wherein the lower-order signal portion is a least significant bit of the n-bit digital signal.