Patent ID: 7984312

Claim:
A system, comprising: a first motherboard configured for generating a first power-on signal; a second motherboard configured for generating a second power-on signal; an electrical power supply configured for electrical communication with the first and second motherboards, the power supply having a plurality of bulk voltage outputs, each bulk voltage output configured for providing one or more output voltages to the first motherboard in response to receiving the first power-on signal and for providing one or more output voltages to the second motherboard in response to receiving the second power-on signal; first and second FET controllers configured for generating, respectively, a first gate signal in response to the first power-on signal and a second gate signal in response to the second power-on signal; a first set of FETs in communication with the first FET controller for selectively switching the output voltages from each bulk voltage output to the first motherboard in response to the first gate signal; and a second set of FETs in communication with the second FET controller for selectively switching the output voltages from each bulk voltage output to the second motherboard in response to the second gate signal.