Patent ID: 7003274

Claim:
A phase locked loop (PLL) frequency synthesizer comprising: a voltage controlled oscillator (VCO) to provide a VCO frequency signal; a switchable non-integer frequency multiplier circuit having a control input, the non-integer frequency multiplier accepting the VCO frequency signal and producing a frequency-multiplied signal at a non-integer multiple of the VCO output frequency or at the VCO output frequency under control of the control input; a programmable divider accepting the frequency-multiplied signal and dividing the frequency of the shifted-frequency signal by a settable amount; a phase detector to compare the phase of the output of the programmable divider to that of a reference oscillator and produce a phase difference signal; and a loop filter to filter a function of the phase difference to produce a control input to the VCO, the frequency synthesizer being to produce a local oscillator signal for a superheterodyne transmitter for operation at a first and a second RF frequency band, the RF bands disparate and each having a bandwidth, the superheterodyne transmitter having a fixed intermediate frequency that is a sizable fraction of the bandwidth of one or more of the RF bands, the superheterodyne transmitter including a first and a second RF upconverter, each having a local oscillator input coupled to the frequency synthesizer, wherein the non-integer multiple is selected such that the frequency synthesizer can supply the local oscillator signal for both the first and second RF bands, such that the tuning range of the VCO is a relatively low fraction of the VCO frequency, and such that spurious mixer products do not fall in the frequency bands of operation.