Patent ID: 8738841

Claim:
A flash memory controller configured to be coupled to external flash memory devices, the flash memory controller comprising: one or more ports for coupling to one or more host devices; a set of flash stage buffers, each configured for holding a page of data read from one of the external flash memory devices pursuant to a respective host command, each flash stage buffer coupled to a respective external flash memory device by a first transmission path; and a set of host port buffers configured for holding data read from a second set of buffers, the set of host port buffers coupled to the second set of buffers by a third transmission path and to the one or more host ports; wherein the flash memory controller is further configured to be coupled to and control operation of an external data path RAM memory, the external data path RAM memory including the second set of buffers, the flash memory controller further configured to hold in the second set of buffers data read from any of the buffers in the set of flash stage buffers, the data stored in the second set of buffers related to a plurality of host commands, the flash memory controller further configured to couple the second set of buffers to the set of flash stage buffers by a second transmission path that includes a path through the external data path RAM memory.