Patent ID: 7994627

Claim:
A stacked package comprising: a substrate; a number of stacked pad redistribution chips, each pad distribution chip comprising: a wafer, wherein a middle vertical line is referred to a line located substantially in the middle of the wafer, wherein a (+) direction is referred to as the direction perpendicular to and on the right side of the middle vertical line, wherein a (−) direction is referred to as the direction perpendicular to and on the left side of the middle vertical line, wherein four quadrants are present in the wafer such that two quadrants are present in each of the left (+) and right (−) side of the middle vertical line and such that all four quadrants meet at a middle point of the wafer; at lest one row of center pads formed on the wafer substantially along the middle vertical line; a row of (+) edge pads formed in one quadrant in the left (+) direction; a row of (−) edge pads formed in one quadrant in the right (−) direction such that the row of (−) edge pads and the row of (+) edge pads are diagonally symmetrical with respect to the middle point of the wafer; and a number of traces in each quadrant for electrically connecting each center pad to the corresponding one of the edge pads; wherein each pad distribution chip stacked on another pad distribution chip is rotated by 90 degrees with respect to the middle point of the wafer such that no two quadrants having the edge pads are stacked; a flexible PCB for electrically connecting the substrate to the pad redistribution chips; and an anisotropic dielectric film for electrically connecting the pad redistribution chips to the flexible PCB and the substrate to the flexible PCB.