Patent ID: 7315066

Claim:
A semiconductor structure, comprising: (a) a semiconductor block comprising a first semiconductor material having a first lattice orientation; (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region comprises a second semiconductor material having a second lattice orientation different from the first lattice orientation; (c) a first semiconductor transistor formed on the semiconductor region, wherein the first semiconductor transistor comprises (i) first and second source/drain (S/D) regions, (ii) a channel region disposed between the first and second S/D regions, (iii) a gate dielectric region on the channel region, and (iv) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; and (d) a discharge prevention structure in direct physical contact with the semiconductor block and electrically coupled to a first electric node of the first semiconductor transistor; wherein a second electric node of the first semiconductor transistor is electrically coupled to the semiconductor block, and wherein the first and second electric nodes are electrically insulated from each other within the first semiconductor transistor by the gate dielectric region.