Patent ID: 8706965

Claim:
A data processing apparatus comprising: processing circuitry comprising a plurality of processing units for performing data processing operations requiring access to data in shared memory, said processing circuitry configured to execute software consisting of a plurality of hierarchical levels of software; each processing unit having a local cache structure associated therewith for storing a subset of said data for access by that processing unit, and access control circuitry for handling access operations issued to the local cache structure, at least one type of access operation to the local cache structure being issued as a local access operation or a shared access operation; a configuration storage for storing an access operation extension value, wherein the access operation extension value is set and unset by software executing at a predetermined hierarchical level; shared access coordination circuitry for coordinating the handling of said shared access operation by said plurality of processing units; on receipt of said shared access operation, the access control circuitry issuing a shared access signal to the shared access coordination circuitry in addition to performing the local access operation to the associated local cache structure; on receipt of said local access operation, if said local access operation has been issued by software at a lower hieratrchical level than said predetermined hierarchical level, the access control circuitry is configured, if the access operation extension value is not set, to perform the local access operation to the associated local cache structure without issuing the shared access signal to the shared access coordination circuitry, and, if the access operation extension value is set, to treat the local access operation as said shared access operation.