Patent ID: 8018464

Claim:
A data processing system comprising: a programmable processor on a single integrated circuit; a main memory external to the single integrated circuit; a bus coupled to the main memory; the programmable processor including: a bus interface coupling the programmable processor to the bus; a first data path having a first bit width coupled to the bus interface; a second data path having a second bit width greater than the first bit width; a plurality of third data paths having a combined bit width less than the second bit width; a wide operand storage, coupled to the first data path and to the second data path, for storing a wide operand received over the first data path, the wide operand having a size with a number of bits greater than the first bit width; a register file including registers, the register file being connected to the third data paths, and including at least one wide operand specifier register storing a wide operand specifier which specifies an address of the wide operand; a functional unit capable of performing operations in response to instructions, the functional unit coupled by the second data path to the wide operand storage, and coupled by the third data paths to the register file; and wherein the functional unit executes a single wide switch instruction containing instruction fields specifying (i) the wide operand specifier register to cause retrieval of the wide operand for storage in the wide operand storage, (ii) a source register in the register file, and (iii) a results register in the register file, the single wide switch instruction causing bits from the source register to be copied into the results register at locations specified on a bit-by-bit basis by the wide operand.