Patent ID: 7664219

Claim:
A flip-flop for a shift register of a data driver, the flip-flop for receiving a first clock signal, an input signal and outputting an output signal, the output signal being fed back to the flip-flop, the flip-flop comprising: a flop core for receiving the input signal and outputting the output signal, wherein the flop core is in power-saving when the input signal and the output signal are both disabled, the flop core outputs the output signal when one of the input signal and the output signal is enabled, and the flop core outputs the output signal when both of the input signal and the output signal are enabled; and a flop header for receiving the first clock signal, the input signal, and the fed-back output signal, and outputting a second clock signal according to the output signal and the input signal, wherein when the input signal and the output signal are both disabled, the second clock signal is in a first state, when one of the input signal and the output signal is enabled, the second clock signal is in a second state, and when both of the input signal and the output signal are enabled, the second clock signal is in the second state, wherein the flop core receives the second clock signal and the input signal and outputs the output signal, when the second clock signal is in the first state, the flop core does not work, and when the second clock signal is in the second state, the flop core works and generates the output signal which is fed back to the flop header.