Patent ID: 8018957

Claim:
A gateway system with automatic dispatch mechanism, comprising: a first transceiver module connected to a first network system; a second transceiver module connected to a second network system; a first automatic dispatch module configured to automatically dispatch first frames from the first transceiver module to the second transceiver module, wherein at least a portion of the bits of the first frames match one of a plurality of predetermined values, wherein the first automatic dispatch module comprises: a plurality of first filters, each of the first filters corresponding to one of a plurality of predetermined values and outputting frames received from the first transceiver module; a plurality of first dispatch registers configured to store outputs of the plurality of the first filters; a first dispatch requesting processor configured to schedule dispatch requests from the first dispatch registers; and a first multiplexer configured to receive frames from the first dispatch register and to output frames to the second transceiver module in accordance with the first dispatch requesting processor; a second automatic dispatch module configured to automatically dispatch second frames from the second transceiver module to the first transceiver module, wherein at least a portion of the bits of the second frames match one of a plurality of predetermined values, wherein the second automatic dispatch module comprises: a plurality of second filters, each of the second filters corresponding to one of a plurality of predetermined values and outputting frames from the second transceiver module; a plurality of second dispatch registers configured to store outputs of the plurality of the second filters; a second dispatch requesting processor configured to schedule dispatch requests from the second dispatch registers; and a second multiplexer configured to receive frames from the second dispatch registers and to output frames to the first transceiver module in accordance with the second dispatch requesting processor; and a main processor configured to control the first transceiver module, the second transceiver module, the first automatic dispatch module and the second automatic dispatch module.