Patent ID: 7464248

Claim:
A microprocessor system, comprising: a microprocessor, issuing a first address to a first address bus; a trap controller, coupled to the first address bus, comprising a trap table, a region table and a patch table, fetching the first address from the first address bus, translating the first address to a second address according to the trap and patch tables, and issuing the second address to a second address bus, and the controller comprising: a comparator, coupled to the trap and region tables, comparing a trap address recorded in the trap table with the first address based on a corresponding region recorded in the region table to acquire a comparison result, wherein a number of bits of the trap address and the first address to be compared is determined based on the corresponding region; and a translator, coupled to the region table, the patch table, and the comparator, fetching a second address from the patch table according to the comparison result and issuing the second address to the second address bus.