Patent ID: 7285798

Claim:
A CMOS inverter construction comprising: a substrate; a first layer over the substrate; the first layer comprising p-type doped Si/Ge and having a relaxed crystalline lattice; a second layer over the first layer; the second layer comprising p-type doped Si/Ge and having a strained crystalline lattice; an NFET device over the second layer and having a transistor gate, the NFET device including n-type doped source/drain regions extending downwardly from adjacent the gate and into the first and second layers; a third layer over the transistor gate; the third layer comprising n-type doped Si/Ge; a fourth layer over the third layer; the fourth layer comprising n-type doped silicon; a PFET device over the NFET device and sharing the transistor gate with the NFET device; the PFET device including p-type doped source/drain regions extending upwardly from adjacent the gate and into the third layer; an electrical interconnect which electrically connects the third layer to one of the NFET device source/drain regions; wherein the substrate comprises p-type doped monocrystalline silicon; and wherein the first layer extends into and physically contacts the p-type doped monocrystalline silicon of the substrate.