Patent ID: 6881635

Claim:
A method of forming an NFET having a strained silicon transistor body in a layer of strained silicon, having a strained silicon layer thickness, disposed on a support layer of SiGe alloy, comprising the steps of: forming a gate dielectric over said strained silicon transistor body; forming a gate electrode over said gate dielectric; forming a pair of temporary dielectric spacers on opposite sides of said gate electrode; removing said strained silicon outside said transistor body and below said pair of temporary spacers by a substantially non-directional process, leaving a buffer portion of strained silicon in said strained silicon layer and a first S/D aperture outside said buffer portion; forming an electrode layer of silicon in said first S/D aperture, making mechanical and electrical contact with said transistor body and with a portion of said support layer of SiGe below said first S/D aperture; forming transition doped areas between said transistor body and electrode areas in said electrode layer on opposite sides of said transistor body; and forming transistor electrodes in said electrode areas.