Patent ID: 8451022

Claim:
An integrated circuit, comprising: a dynamic reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, the dynamic reconfigurable circuit being capable of dynamically changing a circuit configuration thereof by changing over interconnections interconnecting the plurality of computing units, while the dynamic reconfigurable circuit operates, from a first circuit configuration to implement a first function to a second circuit configuration to implement a second function different from the first function; a plurality of circuit blocks; and an input data controlling section configured to control at least one of a configuration and an input timing of input data supplied from each of the plurality of circuit blocks in response to the first circuit configuration or the second circuit configuration of the dynamic reconfigurable circuit, and to input the controlled input data to the dynamic reconfigurable circuit; wherein the integrated circuit is an application specific integrated circuit (ASIC), and the plurality of circuit blocks include a hardware intellectual property (IP) block, a random logic block and a reduced instruction set computer (RISC) processor block.