Patent ID: 8530347

Claim:
A process of forming an electronic device comprising: providing a first interconnect over a substrate having a primary surface; depositing a first insulating layer over the first interconnect; depositing an second insulating layer over the first interconnect layer; forming a second interconnect that is inlaid within the second insulating layer; patterning the first insulating layer and the second insulating layer to define a plurality of openings extending through the first and second insulating layers towards the first interconnect, the plurality of openings spaced vertically apart from the first interconnect, the second interconnect spaced horizontally apart from the plurality of openings; depositing a third insulating layer over the first insulating layer and the second insulating layer to seal the plurality of openings and form a pattern of cavities within the plurality of openings, the pattern of cavities including more than one vertically extending cavities; and forming a third interconnect over the first, second, and third insulating layers, wherein, along a direction substantially perpendicular to the primary surface, the pattern of cavities is disposed between the first interconnect and the third interconnect, the pattern of cavities extending beyond a width of the first interconnect, the second interconnect, or both.