Patent ID: 7400538

Claim:
A method for operating a nitride read only memory (NROM) non-volatile memory (NVM) cell having a source region and a drain region formed in a substrate, and an oxide-nitride-oxide (ONO) structure formed on the substrate and having a first charge trapping region located over the source region, a second charge trapping region located over the drain region, and a central region extending between the first and second charge trapping regions, and a polycrystalline silicon control gate disposed over the ONO structure, the method comprising: (a) applying an erase pulse across the second charge trapping region by generating a positive drain voltage in the drain region and a first negative voltage in the control gate; (b) determining if the second charge trapping region has achieved a predetermined erased state in response to the applied erase pulse; (c) when the second charge trapping region has not achieved the predetermined erased state in (b), determining if the positive drain voltage applied to the drain region during (a) is greater than a predetermined voltage level; and (d) when the positive drain voltage is greater than the predetermined voltage level in (c), applying a second negative refresh voltage to the control gate such that holes enter the ONO structure from the substrate, and then repeating (a) and (b).