Patent ID: 7099202

Claim:
An electronic circuit, comprising: a memory circuit, the memory circuit having an array of memory cells organized into rows and columns, the memory circuit further comprising a sense amplifier having a sense amplifier input and a sense amplifier output, a first bit select multiplexer and a second bit select multiplexer, the first bit select multiplexer and the second bit select multiplexer configured to couple one of either a plurality of first-page global bitlines and a plurality of second-page global bitlines to the sense amplifier input; a plurality of first-page bit address lines, the plurality of first-page bit lines organized so as to be able to access a plurality of first-page data byte locations, each of the plurality of first-page data byte locations having a number of unique first-page bit address lines equal in number to the plurality of first-page global bit lines; a plurality of second-page bit address lines, the plurality of second-page bit lines organized so as to be able to access a plurality of second-page data byte locations, each of the plurality of second-page data byte locations having a number of unique second-page bit address lines equal in number to the plurality of second-page global bit lines; a first-page column multiplexer configured to couple one of the plurality of first-page data byte locations to one of the plurality of first-page global bitlines such that each of the plurality of first-page bit address lines comprising the coupled first-page data byte location is coupled to one of the plurality of first-page global bitlines; and a second-page column multiplexer configured to couple one of the plurality of second-page data byte locations to one of the plurality of second-page global bitlines such that each of the plurality of second-page bit address lines comprising the coupled second-page data byte location is coupled to one of the plurality of second-page global bitlines.