Patent ID: 7774748

Claim:
A system comprising: means for identifying a partially explicit set of instructions used to design a processor; means for automatically generating an explicit instruction set from a partially explicit instruction set, wherein the explicit instruction set forms part of an overall set of instructions to be executed by the processor, the means for automatically generating the explicit instruction set including: means for receiving a description of a partially explicit instruction in the partially explicit set of instructions, the partially explicit instruction description including at least a format and an operation performed by the partially explicit instruction, the operation comprising one or more operands; means for receiving a description of the overall set of instructions, wherein the overall set of instructions description includes parameters that must be explicitly defined for instructions in the overall set of instructions, the parameters including at least one or more fields and consisting of one or more slots, the fields and the slots both comprising one or more bits; means for converting the partially explicit instruction to an explicit instruction for inclusion in the explicit instruction set based on the received description of the partially explicit instruction and the received description of the overall set of instructions, the converting means including: means for assigning encoding/decoding logic to the format of the partially explicit instruction; means for determining a number of the one or more fields that are needed for the conversion and assigning bits for each field in the explicit instruction based on a determination of what is required by each operand in a corresponding operation of the partially explicit instruction; means for determining a number of the one or more slots needed in the explicit instruction based on the determined one or more fields and the corresponding operation, and assigning fields and the corresponding operation to each slot; means for determining a size for each slot of the one or more slots of the explicit instruction and the field bits needed for the operation from the partially explicit instruction assigned to the each slot in order to generate an explicit instruction, the determined slots defining the assigned encoding/decoding logic; and means for generating a hardware description of the processor based on explicit descriptions of the overall set of instructions, wherein the means for identifying, means for automatically generating the explicit instruction set, and the means for generating the hardware description are implemented by one or more computers.