Patent ID: 8352795

Claim:
A method of monitoring a high-integrity processor in a monitored central processing unit of a high integrity processor monitor system, the method comprising: executing a set of sequential instructions a plurality of times, each of the plurality of executions being based on a unique initial value that is obtained from a set of unique initial values stored in the monitored central processing unit or determined by a previous execution of the set of sequential instructions, and wherein executions of the set of sequential instructions a plurality of times test pertinent addressing modes, operand sizes, and instruction side-effects for each instruction tested in the monitored central processing unit; generating a computed final value responsive to each of the plurality of executions of the set of sequential instructions; and sending a computed final value to a monitoring portion of the high integrity processor monitor system responsive to the generating the computed final value for each of the plurality of executions of the set of sequential instructions, wherein the monitored central processing unit is independent of input from the monitoring portion between obtaining the unique initial value and sending the computed final value.