Patent ID: 8138547

Claim:
A method for fabricating a semiconductor device, the method comprising: providing a silicon-on-insulator (SOI) substrate including a buried insulator layer; forming a semiconductor layer overlying the SOI substrate, the semiconductor layer being doped with a dopant of a first conductivity type; forming a gate located on the semiconductor layer, the gate including a gate dielectric layer located on the semiconductor layer and a gate conductor layer located on the gate dielectric layer; forming a source extension region and a drain extension region in the semiconductor layer, the source extension region and the drain extension region contacting the gate dielectric layer, the source extension region and the drain extension region being doped with a dopant of a second conductivity type, which is opposite the first conductivity type; forming a deep drain region in the semiconductor layer, the deep drain region contacting the drain extension region and abutting the buried insulator layer; forming a deep source region in the semiconductor layer, the deep source region contacting the source extension region and abutting the buried insulator layer, the deep drain region and the deep source region being doped with a dopant of the second conductivity type; forming a first metal-semiconductor alloy contact layer using tilted metal formation at an angle tilted towards the source extension region such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate with the first conductive type from the source extension region as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region, wherein the forming the first metal-semiconductor alloy contact layer using tilted metal formation is formed is at the angle θ tilted towards the source extension region such that a size of the angle θ is: 7 ⁢ ° < θ < arctan ⁡ ( L - 2 × L 1 - L g h ) where L is a length between gates, L 1 is a width of a first spacer surrounding each side of the gates, L g is a length of the gates; and h is a height of the gates; and forming a second metal-semiconductor alloy contact located on the first metal-semiconductor layer on each of the source extension region and drain extension region.