Patent ID: 6898694

Claim:
A processor comprising: first and second instruction pointer (IP) sources to provide IPs for first and second instruction threads, respectively; an instruction cache to provide a cache line responsive to an IP; a source arbiter to provide an IP from the first or second IP source to the instruction cache; an instruction buffer (IB) to receive a first block of the cache line from the instruction cache; and a temporary instruction cache (TIC) to receive a second block of the cache line in the same clock cycle, the IB and the TIC receive the first and second blocks of the cache line on a first clock interval, wherein the second block of the cache line is transferred to the IB on a subsequent clock interval, the source arbiter provides IPs from the first and second sources on alternate clock intervals, wherein the IB includes first and second IBs to store instructions from the first and second threads, respectively, and wherein the first IB receives an instruction block from the TIC and the second IB receives an instruction block from the cache on a second clock interval.