Patent ID: 7817766

Claim:
A digital control loop for clock generation, comprising: at least one phase detector which has at least one reference clock signal input for receiving a reference clock signal, a feedback input for receiving a feedback signal and a correction signal output, the phase detector being configured to detect a phase shift of the feedback signal relative to the reference clock signal and output at the correction signal output a correction signal on the basis of the phase shift detected; at least one control loop filter having a signal connection to the correction signal output of the phase detector via a correction signal input for receiving the correction signal, the control loop filter being configured to output, on the basis of the correction signal, a first control signal via a first control output and a second control signal via a second control output, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal; at least one first phase generator which has at least one control input for receiving the first control signal and at least one first phase reference input for receiving a first phase reference signal, wherein the first phase generator is configured to output a first clock signal via a first clock signal output on the basis of the first control signal and the first phase reference signal, wherein the first clock signal output has a signal connection to the feedback input of the phase detector and the first clock signal is transmitted at least partially as feedback signal to the phase detector; and at least one second phase generator which has at least one control input for receiving the second control signal and at least one first phase reference input for receiving the first phase reference signal, wherein the second phase generator is functionally substantially the same as the first phase generator and is configured to output a second clock signal via a second clock signal output on the basis of the second control signal and the first phase reference signal.