Patent ID: 7484118

Claim:
In a multi nodal computer system comprising a plurality of nodes each of which includes chips of different types, wherein one of said chips on each node is a clock chip which is connected to the other chips included on that node via a local communication path and is central to the other chips on that node, the clock chip is capable of providing a clock signal for synchronizing the other chips on the node, a system communication path connects the clock chips on each node, and wherein the other chips on each node are capable of sending a check stop request to the clock chip on their node in case of a malfunction, and the clock chip is capable of selectively disabling one or more chips that caused a malfunction on the node, a method for handling check stops comprising: initiating a check stop by a clock chip depending on a source of a check stop request, wherein said check stop is selected from a group including: a system check stop, a node check stop, and a chip check stop; in case of a system check stop the system communication path drops and the local communication path drops, wherein the local communication path drops after a delay following the system communication path drop; in case of a node check stop all processor unit chips of the node are stopped while all cache chips remain active; and in case of a chip check stop, communicating to other nodes over the system communication path, which continue running, about the chip check stop, and in case the chip check stop is received from a processor unit chip or a Memory Bus Adapt (MBA) chip of a first node, shifting out data from the MBS chip and the processor unit chip into main memory of the first node, processing the shifted out data by a processor unit chip of a second node, and escalating the chip check stop condition to a system check stop condition.