Patent ID: 7755076

Claim:
An array of memory cells on a semiconductor substrate, comprising: first and second word lines on the semiconductor substrate extending in parallel in a first direction, the first word line having a word line width and a principal sidewall surface, the second word line having a word line width and a principal sidewall surface; first and second sidewall dielectric members, the first sidewall dielectric member formed on the principal sidewall surface of the first word line, the second sidewall dielectric member formed on the principal sidewall surface of the second word line; first and second doped regions in the substrate between the first and second word lines; first and second memory members comprising a programmable resistive material with an active region on the first and second sidewall dielectric members, first and second memory members positioned between the first and second word lines, the first memory member having a bottom surface in electrical contact with the first doped region, the second memory member having a bottom surface in electrical contact with the second doped region; a top electrode structure having sides extending in parallel in a second direction perpendicular to the first direction, the top electrode structure positioned over and in electrical contact with the first and second memory members, the first and second memory members having sides aligned with the sides of the top electrode structure; and a dielectric isolation structure isolating the first and second doped regions.