Patent ID: 7884486

Claim:
A chip-stacked package structure, comprising: a main substrate comprising: a substrate having a first surface and a second surface opposite to the first surface; and a first chip disposed on the first surface, the first chip having a first active surface, a first rear surface, wherein the first active surface faces towards the first surface of the substrate, and the first chip is electrically connected to the substrate; a baseboard substrate having a third surface and a fourth surface, the fourth surface faces towards the substrate, the baseboard substrate comprising: a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received; at least one first via plug and at least one second via plug disposed in the first through holes; at least one patterned circuit layer disposed onto the core layer and electrically connected to the at least one first via plug and the at least one second via plug, wherein a portion of the at least one patterned circuit layer is exposed by the first accommodation space; a solder mask disposed on the at least one patterned circuit layer and having an opening to expose another portion of the at least one patterned circuit layer and a plurality of second through holes thereon; and a second chip disposed on the third surface of the baseboard substrate, the second chip having a second active surface, a second rear surface, wherein the second active surface faces towards the third surface of the baseboard substrate, and the second chip is mounted within the opening of the solder mask and electrically connected to the at least one patterned circuit layer; and a molding compound encapsulating the main substrate, and the baseboard substrate.