Patent ID: 8741721

Claim:
A method for manufacturing a semiconductor device having a MOS field-effect transistor, comprising: forming a gate on a semiconductor substrate, forming a source and a drain in the semiconductor substrate, forming a sidewall insulating layer that has a first insulating portion formed in a first direction on the source and the drain and a second insulating portion formed in a second direction on a side wall of the gate, forming a stress film on the source, the drain, the sidewall insulating layer and the gate; and forming in the stress film a slit extending from a surface of the stress film toward the sidewall insulating layer and exposing a bend section of the sidewall insulating layer formed by the first insulating portion and the second insulating portion, wherein the stress film includes a first part and a second part separated by the slit from each other, the first part is located on the gate, and the second part is located on the source and the drain.