Patent ID: 7039819

Claim:
For use in a data processing system that comprises a system-on-a-chip (SOC) device that comprises a central processing unit and a plurality of system-on-a-chip (SOC) modules, an apparatus for initiating a sleep state in said system-on-a-chip (SOC) device in said data processing system, said apparatus comprising; a power management controller coupled to said central processing unit and to said plurality of SOC modules, said power management controller capable of: initiating a sleep state in said system-on-a-chip (SOC) device by sending a sleep request signal to said central processing unit to cause said central processing unit to enter a sleep state and by sending to each of said plurality of SOC modules a clock disable request signal to cause each of said plurality of SOC modules to enter a sleep state; receiving a suspension request acknowledgement signal from said central processing unit acknowledging that said central processing unit had entered a sleep state; and in response to receiving said suspension request acknowledgement signal from said central processing unit, sending a clock disable request signal to each of said plurality of SOC modules.