Patent ID: 8325452

Claim:
A semiconductor device, comprising: a semiconductor chip on which a switching element is formed; a mounting substrate on which the semiconductor chip is mounted with an intervening solder layer; a heat dissipation mechanism that dissipates heat generated by the semiconductor chip; a current detection circuit that detects current flowing in the switching element; a voltage detection circuit that detects a voltage applied to the switching element; a loss calculation circuit that calculates a loss occurring in the switching element based on the current detected by the current detection circuit and the voltage detected by the voltage detection circuit; a temperature detection mechanism that detects a temperature of the semiconductor chip; and a thermal resistance calculation circuit that calculates a thermal resistance in a dissipation path from the semiconductor chip based on the switching element loss calculated by the loss calculation circuit and the semiconductor chip temperature detected by the temperature detection mechanism; wherein the thermal resistance calculation circuit comprises: a temperature difference calculation portion that calculates the temperature difference before and after the occurrence of the loss calculated by the loss calculation circuit by referencing the temperature detected by the temperature detection mechanism; and a thermal resistance calculation portion that calculates the thermal resistance in the heat dissipation path from the semiconductor chip based on the loss calculated by the loss calculation circuit and the temperature difference calculated by the temperature difference calculation portion; wherein the thermal resistance calculation circuit calculates an integrated value of losses occurring in the switching element and the temperature difference of the semiconductor chip based on time elapsed until saturation of temperature in the heat dissipation path from the semiconductor chip and a semiconductor chip temperature difference, and calculates the thermal resistance at a specific location on the heat dissipation path from the semiconductor chip; and wherein by setting a time interval, over which the integrated value of losses occurring in the switching element and the semiconductor chip temperature difference are calculated, to 200 ms or less, the thermal resistance calculation circuit monitors anomalies in the solder layer fixing the semiconductor chip to the mounting substrate, and by setting the time interval, over which the integrated value of losses occurring in the switching element and the semiconductor chip temperature difference are calculated, to two seconds or less, the thermal resistance calculation circuit monitors anomalies in a contact face of the heat dissipation means, and by setting the time interval, over which the integrated value of losses occurring in the switching element and the semiconductor chip temperature difference are calculated, to two seconds or more, the thermal resistance calculation circuit monitors anomalies in the heat dissipation mechanism.