Patent ID: 7161943

Claim:
A method for scheduling a switch for connecting a number of input ports to selected ones of a number of output ports, the method comprising: storing packet forwarding request information for each of a plurality of input port/output port combinations; performing a first scheduling operation at a first scheduler, where the first scheduler is configured to schedule switching of a first set of input port/output port combinations included in the plurality of input port/output port combinations during a first future time slot based on the packet forwarding request information associated with respective input port/output port combinations, wherein the first set of input port/output port combinations is selected such that the respective input ports and output ports included within the first set of input port/output port combinations do not conflict with each other; performing a second scheduling operation at a second scheduler in parallel to the first scheduling operation, where the second scheduler is configured to schedule switching of a second set of input port/output port combinations included in the plurality of input port/output port combinations during a second future time slot based on the packet forwarding request information associated with respective input port/output port combinations, wherein the second set of input port/output port combinations is selected such that the respective input ports and output ports included within the second set of input port/output port combinations do not conflict with each other; and forwarding reservation information associated with the scheduled first set of input port/output port combinations to each of a third scheduler and a fourth scheduler, wherein the third scheduler is associated with a third set of input port/output port combinations sharing at least one common input port with the first set of input port/output port combinations and the fourth scheduler is associated with a fourth set of input port/output port combinations sharing at least one common output port with the first set of input port/output port combinations.