Patent ID: 7292480

Claim:
A nonvolatile memory apparatus comprising: a plurality of terminals including a first terminal for receiving a clock signal, a second terminal for receiving a command, and a third terminal for receiving and for outputting data in response to the clock signal received from the first terminal; a control circuit having a central processing unit; a program memory storing first operation steps for performing an operation of the nonvolatile memory apparatus therein by executing the central processing unit; a volatile memory; and a nonvolatile memory, wherein the program memory and the volatile memory are assigned in a part of an address space of the central processing unit, wherein the nonvolatile memory is capable of storing a first data and a second data, wherein the central processing unit controls to storing the first data to the volatile memory for arbitrary one of storing into the nonvolatile memory and outputting to outside of the nonvolatile memory apparatus thereof via the third terminal by performing the first operation steps stored in the program memory in response to receiving a first command via the second terminal, and is capable of executing the second data as second operation steps storing in the volatile memory in response to receiving a second command via the second terminal, and wherein the control circuit is adapted to setting arbitrary one of a first mode and a second mode, is adapted to make an internal clock signal stop supplying during the second mode.