Patent ID: 7745876

Claim:
A semiconductor integrated circuit (IC) device comprising: a semiconductor substrate having a peripheral circuit region and a cell array region, the cell array region comprising a cell edge region and a cell central region, the cell central region substantially surrounded by the cell edge region, and the cell edge region substantially surrounded by the peripheral circuit region; a device isolation layer disposed in the peripheral circuit region, the cell edge region, and the cell central region, the device isolation layer defining cell active regions in the cell central region and the cell edge region and a peripheral active region in the peripheral circuit region; a peripheral gate pattern disposed on the peripheral active region of the peripheral circuit region and extending upward from a top surface of the peripheral active region; cell gate patterns disposed in the cell active regions of the cell central region and the cell edge region, and protruding into the cell active regions; and a connection line contacting the cell active region and the cell gate pattern of the cell edge region, wherein each of the cell gate patterns comprises a cell gate and a cell gate capping pattern which are sequentially stacked, the cell gate patterns are in contact with each other through the device isolation layer, and the connection line is in contact with the cell gate and the cell active region, and wherein the connection line has a first width on the cell gate and a second width on the cell active region.