Patent ID: 6862670

Claim:
An apparatus for reducing the number of address latches and address comparators needed to maintain data coherency in a microprocessor pipeline, the apparatus comprising: a tagged address stack (TAS), having N latches for storing up to N unique addresses associated with data buffers in the pipeline, each of said N latches having an associated unique TAS tag; N address comparators, coupled to said TAS, for indicating which if any of said N unique addresses matches a new address associated with a new data transaction in the pipeline; and control logic, coupled to said N address comparators, wherein if said N address comparators indicate said new address does not match any of said N unique addresses, then said control logic allocates a free one of said N latches to store said new address into, and causes said new data transaction to latch said unique TAS tag associated with said free one of said N latches allocated.