Patent ID: 8806095

Claim:
An electronic measuring device, comprising: a detection channel module including a plurality of detection channels to receive serial data from an external signal terminal; a sampling module connected to the detection channel module, wherein the sampling module receives the serial data from the detection channel module, and the sampling module includes a plurality of serial-to-parallel converters and a plurality of first-in-first-out (FIFO) registers corresponding to the serial-to-parallel converter, respectively, and each serial-to-parallel converter receives the serial data from a corresponding detection channel to convert the serial data into parallel data bytes and output the parallel data bytes to a corresponding FIFO register, and the corresponding FIFO register stores the parallel data bytes temporarily; a control unit connected to the sampling module, wherein the control unit includes a channel enabler connected to the serial-to-parallel converters, and the channel enabler is capable of outputting a channel enabling signal to the detection channel module to enable a predetermined number of the detection channels needed for data sampling, which is for the sampling module to recognize the serial data received from each detection channel so as to enable a corresponding serial-to-parallel converter to receive the serial data; a data path selector connected to the FIFO registers of the sampling module and the control unit for receiving the parallel data bytes from the sampling module and outputting the parallel data bytes in a sequential arrangement according to a data path signal sent by the control unit; and a memory device connected to both the control unit and the data path selector, wherein the memory device includes a memory controller and a storage unit, the memory controller receives the parallel data bytes from the data path selector and stores the parallel data bytes into the storage unit, and the storage unit has a plurality of storage sectors, a first indicator, and a second indicator, wherein each storage sector has the same number of bits as each of the parallel data bytes transferred from the data path selector, the first indicator is pointed to the storage sector where a first parallel data byte from the data path selector is predetermined to be stored in, and the second indicator is pointed to another storage sector where the memory controller causes a next parallel data byte to be stored in, wherein all the parallel data bytes stored in the FIFO registers are transferred and stored in the storage unit in sequential order; as the parallel data bytes continue to be input into the storage unit, the second indicator continues to point to the next storage sector until the storage unit reaches the full capacity; when the storage unit reaches full capacity, the second indicator is pointed to the same storage sector at which the first indicator is pointed to, and the first indicator is then moved to be pointed to another storage sector based on the predetermined number of the enabled detection channels.