Patent ID: 6906572

Claim:
A semiconductor integrated circuit device comprising: a first circuit including first latches; a second circuit including second latches; a phase locked loop to output a first clock signal; a phase adjusting circuit to output a second clock signal; first clock distribution lines to distribute the first clock signal to said first latches and to said phase adjusting circuit; and second clock distribution lines to distribute the second clock signal to said second latches; wherein the phase locked loop receives a reference clock signal and the first clock signal distributed via the first clock distribution lines and controls a phase of the first clock signal outputted to synchronize the reference clock signal and the first clock signal distributed via the first clock distribution lines, and wherein the phase adjusting circuit receives the first clock signal distributed via the first clock distribution lines and the second clock signal distributed via the second clock distribution lines and controls a phase of the second clock signal outputted to synchronize the first clock signal distributed via the first clock distribution lines and the second clock signal distributed via the second clock distribution lines.