Patent ID: 8843785

Claim:
A method, in a processor chip, for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation, comprising: placing the processor chip into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on an interface of the processor chip; detecting, by health monitoring logic of the processor chip, a triggering condition of the processor chip that is a trigger for initiating debug data collection from the on-chip logic; performing, by an on-chip programmable debug data collection engine of the processor chip, debug data collection from the on-chip logic to generate debug data; and outputting, by the on-chip programmable debug data collection engine of the processor chip, to an external mechanism via the interface, data generated by the on-chip programmable debug data collection engine based on the debug data.