Patent ID: 7420403

Claim:
A latch circuit comprising: a low threshold forward clock inverter inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when an execution clock having a low value in a sleep mode section and corresponding to a system clock in a section other than the sleep mode is in a first logic state; a low threshold input terminal clock inverter inverting an input-terminal logic state, applying the inverted logic state to an output-terminal logic state, and transferring the output-terminal logic state to the input terminal of the low threshold forward clock inverter when the execution clock is in the first logic state; a low threshold pass gate connecting an output terminal of the input terminal clock inverter with the input terminal of the low threshold forward clock inverter in a normal mode, and blocking the connection in the sleep mode; and a high threshold backward clock inverter forming a circular latch structure together with the low threshold forward clock inverter, and inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when the execution clock is in a second logic state.