Patent ID: 7033896

Claim:
A method of manufacturing a transistor with a high breakdown voltage, comprising: defining an active region on a semiconductor substrate by an isolation layer formed in a trench with an insulation material; selectively etching a surface portion of the active region, thereby forming at least one recessed portion in the active region of the substrate; depositing an oxide material on a surface of the substrate, thereby forming an oxide layer with which the recessed portion is filled; lightly implanting ions into the recessed portion of the substrate including the oxide layer, thereby forming lightly doped source/drain regions at surface portions of the recessed portion; removing the oxide layer except for a portion of the oxide layer corresponding to the recessed portion, thereby forming a protective oxide layer on the recessed portion; forming a gate structure between the protective oxide layers; and heavily implanting ions into the substrate between the protective oxide layer and the insulation layer, thereby forming heavily doped source/drain regions on the semiconductor substrate.