Patent ID: 7124213

Claim:
A computer system, comprising: a processor having at least W I/O lines; a bus for transferring at least W I/O bits to and from said processor; a memory module attached to said bus, said memory module for storing and saving a W-bit wide word, wherein said W-bit wide word is applied to said bus, wherein said memory module is comprised of a plurality of memory devices having more than W I/O lines, wherein at least one memory device has a spare I/O line that is not connected to said bus, and wherein said at least one memory device includes; said spare I/O line; N–1 I/O lines, wherein N is an integer; N addressable arrays, at least one of which is associated with said spare I/O line; N multiplexers for routing signals from said N–1 I/O lines and from said spare I/O line to said addressable arrays in response to control signals; and a multiplex controller for producing said control signals; wherein data on at least one of said N–1 I/O lines can be stored in and/or read from said array associated with said spare I/O line.