Patent ID: 7248596

Claim:
A system for memory interleaving in a high-speed switching environment, the system comprising: a plurality of memory units that each comprise one or more memory devices; a plurality of port modules that are each operable to: receive a packet communicated from a component of a communications network and write the received packet to one or more of the plurality of memory units; and read a packet from one or more of the plurality of memory units for communication to the component of the communications network; and an interconnection network comprising a hierarchical structure that comprises one or more switching stages, the interconnection network coupling the plurality of memory units to the plurality of port modules such that: each of the port modules is operable to write to each of the memory units according to a first schedule and each of the port modules is operable to read from each of the memory units according to a second schedule, the first schedule allowing a first number of write operations over a period of time, the second schedule allowing a second number of read operations over the period of time, the second number being twice or more the first number; and a first port module is operable to read a first portion of a packet from one or more memory units for communication to a first component of the communications network before a second port module has received a second portion of the packet communicated from a second component of the communications network.