Patent ID: 8304317

Claim:
A method of patterning a plurality of polysilicon structures, comprising: forming a polysilicon layer over a semiconductor body; performing a first patterning of the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER), wherein the first patterning of the polysilicon layer reduces LER by performing a post-pattern high temperature bake of a developed first photoresist layer overlying the polysilicon layer, and wherein the post-pattern baked photoresist is used as an etch mask to pattern the polysilicon layer wherein the first patterning utilizes a thermal flow assist layer configured to improve temperature sensitivity of the post-pattern high temperature bake, and wherein the post-pattern high temperature bake of the developed photoresist is performed at a temperature below a melting point of the photoresist; and performing a second patterning of the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.