Patent ID: 6855565

Claim:
A semiconductor device manufacturing method comprising: forming a gate electrode over a semiconductor substrate with a gate insulating film interposed between said semiconductor substrate and said gate electrode; forming source and drain diffusion layers on a surface of said semiconductor substrate on both sides of said gate electrode; forming a first interlayer insulating film on said semiconductor substrate to cover said gate electrode, source and drain diffusion layers; forming a buried interconnection and a first contact plug which extends from a portion of said buried interconnection to one of said source diffusion layer and said drain diffusion layer in said first interlayer insulating film which lies on one of said source diffusion layer and said drain diffusion layer; forming a second interlayer insulating film on said first interlayer insulating film and on said buried interconnection containing said first contact plug; forming a pair of second and third contact plugs which extend from a surface of said second interlayer insulating film to said buried interconnection in said second interlayer insulating film formed on said buried interconnection; and forming a first ferroelectric capacitor by sequentially laminating a first lower electrode, first ferroelectric film and first upper electrode in this order on said second contact plug and forming a second ferroelectric capacitor by sequentially laminating a second lower electrode, second ferroelectric film and second upper electrode in this order on said third contact plug.