Patent ID: 7045855

Claim:
A semiconductor device, comprising: a first doping region, which has a first conduction type; a second doping region, which has the first conduction type and is spaced apart from the first doping region; a channel region, which lies between the first and second doping regions and has a second conduction type; and a gate structure provided above the channel region, wherein the gate structure having a first gate dielectric made of a first material with a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material with a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant, the first thickness of the first gate dielectric and the second thickness of the second gate dielectric configured such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain a same threshold voltage, is at least of a same magnitude as a thickness equal to a sum of the first thickness and the second thickness, the gate structure has a third gate dielectric made of silicon dioxide, which is provided above the second gate dielectric, a parasitic field-effect transistor is involved, and the first doping region is a filling electrode of a trench capacitor of a memory cell, the second doping region is a semiconductor substrate and the channel region is a connection region of an associated selection transistor to a gate connection of the filling electrode and the gate structure comprises an insulation collar of the trench capacitor.