Patent ID: 7970960

Claim:
A direct memory access (DMA) controller comprising: a plurality of channel groups each having a plurality of DMA channels, wherein the each of the plurality of DMA channels has at least a first DMA Channel and a second DMA channel, wherein the plurality of channel groups has at least a first channel group and a second channel group; and a channel group controller controlling enablement of the DMA channels in units of channel groups, wherein the channel group controller enables the respective DMA channel of the plurality of channel groups in data transmission, wherein the channel group controller is configured to have at least two or more external processors connected to the channel group controller, wherein any one of the at least two or more external processors is configured to control any one of the DMA channels, and wherein a least two or more different external processors simultaneously control the at least first DMA channel and the second DMA channel of the respective one of at least the first or second channel group of the DMC controller or at least one of either the first DMA channel or the second DMA channel for each of the at least first channel group and the second channel group of the DMC controller.