Patent ID: 7190209

Claim:
A method of limiting power consumption during operation of an integrated circuit including, a multi-state circuit that includes a first PMOS device and a first NMOS device, the multi-state circuit being operable to switch between a first state in which the first PMOS device is turned on and the first NMOS device is turned off and a second state in which the first PMOS device is turned off and the first NMOS device is turned on; a second NMOS device with a drain connected to a supply voltage terminal and with a source connected to a source of the first PMOS device; and a second PMOS device with a drain connected to an effective ground terminal and with a source connected to a source of the first NMOS device, the method comprising: in the active mode, providing a turn on voltage signal to a gate of the second NMOS device that is higher than the multi-state circuit supply voltage bias; and providing a turn on voltage signal to a gate of the second PMOS device that is lower than the multi-state circuit effective ground bias voltage; and in a standby mode, providing a turn off voltage signal to a gate of the second NMOS device that is lower than the multi-state circuit effective ground bias voltage; and providing a turn off voltage signal to a gate of the second PMOS device that is higher than the multi-state circuit supply voltage bias.