Patent ID: 7562321

Claim:
A method for inserting -a test point in a structured application specific integrated circuit (ASIC) comprising: completing a circuit design including user-function element placement and routing selection for said structured ASIC; identifying, after said completing step, unused logic cells of said structured ASIC for test point insertion, wherein said unused logic cells are unused for user-functions in said circuit design; selecting one of said identified unused logic cells that is adjacent to a signal line which is other than on at least one of: a path determined to be timing critical and an area of said structured ASIC determined to be layout congested; inserting a test point at said selected unused logic cell of said structured ASIC without inserting a logic element into the structured ASIC and without changing the placement of user-function elements of said circuit design in said structured ASIC; and physically implementing the circuit design with said inserted test point in said structured ASIC.