Patent ID: 8892619

Claim:
A floating-point fused multiply-add (FMA) unit embodied in an integrated circuit, wherein the FMA unit comprises: a) a multiplier circuit with floating point inputs A and C and floating point output A*C; b) an adder circuit connected to the output of the multiplier circuit, wherein the adder circuit adds the floating point output A*C to a floating point input B producing a result A*C+B; wherein the adder circuit comprises: i) an exponent difference circuit implemented in parallel with the multiplier circuit; ii) a close path circuit implemented after the exponent difference circuit; iii) a far path circuit implemented after the exponent difference circuit; iv) a 2:1 Mux circuit connected to outputs of the close path circuit and the far path circuit; and v) a rounder circuit connected to an output of the 2:1 Mux circuit; c) accumulation bypass circuits forwarding an unrounded output of the 2:1 Mux circuit to inputs of the close path circuit and the far path circuit, and forwarding an exponent result in carry save format to an input of the exponent difference circuit; and d) a multiply-add bypass circuit forwarding the unrounded output of the 2:1 Mux circuit to the floating point inputs A and C of the multiplier circuit.