Patent ID: 6933875

Claim:
A pipelined analog-to-digital converter with unequal working time for converting an analog signal into a digital signal, comprising: a plurality of transfer circuits each having: an analog-to-digital sub-converter for receiving an analog signal from the previous stage of transfer circuit and generating a digital bit signal during a sampling period; a multiply digital-to-analog converter for receiving the digital bit signal produced by the analog-to-digital sub-converter and converting the digital bit signal into a second analog signal according to a reference voltage; a subtractor for receiving the analog signal from the previous stage of transfer circuit and the second analog signal produced by the multiply digital-to-analog converter and subtracting the second analog signal from the analog signal produced by the previous stage of transfer circuit to produce a third analog signal; and an amplifier for receiving the third analog signal from the subtractor, amplifying the analog signal and transmitting the amplified analog signal to the next stage of transfer circuit, wherein the operation time of the multiply digital-to-analog converter, the subtractor and the amplifier is an amplifying period and the amplifying period is longer than the sampling period; and a decoder for receiving the digital bit signal from the analog-to-digital sub-converter inside various transfer circuits and producing a digital signal corresponding to the analog signal.