Patent ID: 8901894

Claim:
An apparatus comprising: a first circuit coupled between a first node and a second node, wherein the first circuit is configured to receive a source current via the first node and a battery discharge current via the second node, wherein the first circuit is configured to divide the source current into first and second portions Ic and Icr, respectively; wherein the first circuit is configured to divide the battery discharge current into first and second portions Idc and Idcr, respectively; wherein the first circuit is configured to transmit Ic to the second node, and wherein the first circuit is configured to transmit Idc to the first node; a second circuit coupled to the first circuit and configured to receive Icr and Idcr, wherein the second circuit is configured to generate a first voltage that is related to Icr, wherein the second circuit is configured to generate a second voltage that is related to Idcr; an analog-to-digital (ADC) conversion circuit coupled to the second circuit, wherein the ADC circuit is configured to generate a first digital signal that represents the first voltage, and wherein the ADC circuit is configured to generate a second digital signal that represents the second voltage; wherein Icr is equal Ic/N; wherein Idcr is equal to Idc/M; where N and M are values greater than one; wherein the first circuit comprises: a first FET comprising a first source coupled to the first node and configured to receive the source current, a first drain, and a first gate; a second FET comprising a second source, a second drain, and a second gate; a third FET comprising a third source coupled to the second node and configured to receive the battery discharge current, a third drain, and a third gate, and; a fourth FET comprising a fourth source, a fourth drain, and a fourth gate; wherein the first, second, third, and fourth drains are coupled together; wherein the first and second gates are coupled together; wherein the third and fourth gates are coupled together; wherein the first and second sources are coupled to the second circuit and configured to be at one common voltage in order to transmit Idcr to the second FET; wherein the third and fourth sources are coupled to the second circuit and configured to be at another common voltage in order to transmit Icr to the fourth FET.