Patent ID: 7260755

Claim:
An integrated circuit, comprising: a delay path, wherein a transition of an input signal to said delay path causes a subsequent transition of an output signal from said delay path; a pulse generator configured to receive said input signal and said output signal for generating a pulse signal having a pulse width indicative of a delay between said input signal transition and said output signal transition, wherein said pulse generator includes a first multiplexer for receiving said input signal, a second multiplexer for receiving said output signal, and a logic gate for combining outputs from said first multiplexer and second multiplexer to provide said pulse signal; wherein said first and second multiplexers selectively controlled by a rise/fall select signal; wherein said delay path can be an inverting delay path or a non-inverting delay path; and a delay line configured to receive said pulse signal from said pulse generator to generate information indicative of said pulse width of said pulse signal.