Patent ID: 7360040

Claim:
An interleaver memory structure that is implemented to process a plurality of encoded symbols during decoding processing, the interleaver memory structure comprising: a first multiplexor (MUX) that is operable to receive inputs that include sequential read addresses and sequential write addresses as inputs and whose select signal is a clock signal having even and odd cycles; a second MUX that is operable to receive the sequential read addresses and the sequential write addresses as inputs and whose select signal is an inversion of the clock signal having even and odd cycles, wherein corresponding sequential read addresses and sequential write addresses that are provided to the first MUX and to the second MUX are offset by an odd value; a first interleaver pattern memory that is operable alternatively to receive the sequential read addresses and the sequential write addresses from the first MUX; a second interleaver pattern memory that is operable alternatively to receive the sequential write addresses and the sequential read addresses from the second MUX; a first interleaver memory that is operable to: receive first input data that is written therein according to a sequential write address provided by the first interleaver pattern memory; and provide first output data that is read there from according to a sequential read address provided by the first interleaver pattern memory; a second interleaver memory that is operable to: receive second input data that is written therein according to a sequential write address provided by the second interleaver pattern memory; and provide second output data that is read there from according to a sequential read address provided by the second interleaver pattern memory; and a third MUX that is operable to receive inputs that include the first output data and the second output data and whose select signal is the clock signal having even and odd cycles.