Patent ID: 6999376

Claim:
A synchronous flash memory device comprising: an array of non-volatile memory cells arranged in addressable rows and columns; a plurality of address inputs, coupled to the array of non-volatile memory cells, comprising at least A 2 , A 1 , and A 0 ; and a state machine that can execute a method for reading a synchronous flash memory device including receiving an initial column address on address inputs A 2 , A 1 , and A 0 , initiating a burst read operation in response to the burst mode command and the burst length, and, using an internal counter circuit, generating additional column addresses starting at the initial column address, wherein the internal counter changes a signal only on column address input A 0 if the burst length is two, the internal counter changes signals only on column address inputs A 0 and A 1 if the burst length is four, and the internal counter changes signals only on column address inputs A 0 , A 1 and A 2 if the burst length is eight.