Patent ID: 6846732

Claim:
A semiconductor device fabrication method comprising the steps of: forming, on a main surface of a semiconductor substrate having a memory cell region and a peripheral circuit region defined in plane, a plurality of gate electrodes in said memory cell region; forming a gate protection film covering a top face and side face of one of said gate electrodes; forming an impurity region of a first conductivity type at the main surface of said semiconductor substrate located at both sides of said one gate electrode; forming an interlayer insulation film so as to cover said semiconductor substrate and said gate protection film, said interlayer insulation film being made of a material more readily etchable than said gate protection film when a predetermined etchant is used; removing said interlayer insulation film until a top face of said gate protection film is exposed; forming on said interlayer insulation film a mask film having an opening exposing at least a portion of said exposed gate protection film, after the step of removing said interlayer insulation film; etching said interlayer insulation film and said gate protection film using said predetermined etchant with said mask film as a mask to form a hole reaching said impurity region, and having at least a portion of a side face defining said hole formed by said gate protection film; forming a conductor film so as to fill said hole and cover said interlayer insulation film; and forming a pad contact in said hole by leaving a portion of said conductor film in said hole, and removing other portions of said conductor film.