Patent ID: 7725694

Claim:
A microcomputer comprising: a CPU configured to perform a plurality of tasks in a parallel time-sharing operation, the tasks including at least one special task having a fixed loop program with a constant increase of an instruction address; and a skip judging circuit configured to output a write prohibit signal to the CPU for a predetermined time period indicating that the CPU executes instructions but does not utilize the execution result of the instructions, wherein, when the instruction address in the fixed loop program overflows, the instruction address is reset to an initial address, and the instruction address starts to increase from the initial address, the CPU being further configured so that, when the CPU performs a conditional branch instruction in the special task, the conditional branch instruction located at a conditional branch instruction address, the conditional branch instruction including a branch destination address, one or more instructions located at one or more instruction addresses between the conditional branch instruction address and the branch destination address and when it is determined in the conditional branch instruction that a result of a condition judging process in the conditional branch instruction is that execution should proceed to the branch destination address, the skip judging circuit outputs the write prohibit signal to the CPU so that the CPU executes the one or more instructions but is adapted to perform an invalidation step that prohibits utilizing the execution result of the one or more instructions in both the CPU and a periphery circuit, and a process time for a case where the result of the condition judging process is that execution should proceed to the branch destination address for performing the invalidation step is substantially equal to a process time for a case where the result of the condition judging process is that execution should proceed to the one or more instruction addresses just after the conditional branch instruction address, wherein, when it is determined in the conditional branch instruction that a result of the condition judging process in the conditional branch instruction is that execution should not proceed to the branch destination address, the CPU executes the one or more instructions located at instruction addresses between the conditional branch instruction address and the branch destination address and the skip judging circuit does not output the write prohibit signal.