Patent ID: 7373485

Claim:
A clustered superscalar processor comprising: a plurality of clusters, each cluster including: an instruction window for storing instructions; an upper level register file for outputting a register value in accordance with the instructions and storing an execution result of each instruction; and a functional unit for executing the instruction with the register value, wherein the execution result of each of the instructions is written to the upper level register file; a lower level register file, connected to the plurality of clusters, for storing execution results of the functional units; a bypass route connected between the plurality of clusters; and a control unit for communicating the execution result of the instruction generated by the functional unit of one of the clusters to another cluster via the bypass route, wherein the control unit determines whether or not another cluster will use the execution result of the instruction of the one of the clusters before the one of the clusters executes the instruction, and selectively communicates the instruction execution result of the one of the clusters to the upper level register file of another cluster that requires the instruction execution result based on the determination result.