Patent ID: 7694194

Claim:
A semiconductor device, comprising: a memory circuit that includes a memory array and a plurality of ports capable of accessing said memory array with different frequencies, respectively; an access management circuit configured to divide an address space of said memory array into a plurality of segments virtually and to control accessing said memory array segment by segment; a plurality of test circuits provided correspondingly to said ports, said test circuits being configured to access said memory array segment by segment concurrently and asynchronously via the corresponding ports, respectively, and to perform various tests on said memory circuit, each said test being different from each other of said tests; and a set of pointers provided correspondingly to said plurality of segments, said pointers being configured to indicate access statuses of which segments are currently accessed by said test circuits and which ports are used for accessing the memory circuit while the test circuits perform the tests on the memory circuit concurrently and asynchronously, wherein each respective test circuit is configured to refer to the pointers and to perform a test assigned to the test circuit on one of said plurality of segments when the pointer assigned to a target segment indicates that the target segment is not currently accessed by any of the other test circuits, or to temporarily suspend the assigned test on the target segment when the pointer indicates that the target segment is currently accessed by one of the other test circuits, thereby to allow said plurality of test circuits to perform various tests concurrently on said memory circuit.