Patent ID: 7793082

Claim:
An integrated circuit comprising: at least one processing pipeline stage having an input register, processing circuitry coupled to said input register to receive an input signal therefrom, and an output register coupled to said processing circuitry to receive an output signal therefrom; wherein said output register is configured to sample said output signal at a speculative sampling point to form a speculative value, to output said speculative value as a downstream input signal to one or more further processing pipeline stages during at least a speculation period, and to be responsive to a change in said output signal during said speculation period to trigger an error recovery operation; and said processing circuitry includes at least one latch disposed in a signal path between said input register and said output register of the same processing pipeline stage, said at least one latch being responsive to a latch control signal to be non-transmissive during a period matched to said speculation period so as to block a change in said input signal resulting in a change in said output signal during said speculation period; wherein said processing circuitry includes first combinational circuitry disposed in said signal path between said input register and said latch and second combinational circuitry disposed in said signal path between said latch and said output register.