Patent ID: 7443793

Claim:
A processor comprising: scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements; and traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements; wherein the scheduling circuitry is configured for utilization of at least one time slot table, the time slot table comprising a plurality of locations, each of the locations corresponding to a transmission time slot and being configured to store at least one entry, the scheduling circuitry being operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry in the presence of collisions between requests from the transmission elements for each of one or more of the time slots, through the use of a linking of colliding transmission elements and by moving at least one entry from a first location within the at least one time slot table to a second location within the at least one time slot table.