Patent ID: 7279931

Claim:
A complementary MOS transistor output stage structure comprising: a first PMOS transistor, wherein the first PMOS transistor including a first source, a first gate, a first drain, and a first body point, where the first source is coupled to a supply voltage, and the first gate is coupled to a first reference voltage; a second PMOS transistor, wherein the second PMOS transistor including a second source, a second gate, a second drain, and a second body point, where the second source is coupled to the first drain, the second gate is coupled to a second reference voltage, and the second drain is coupled to an output pad; a first NMOS transistor, wherein the first NMOS transistor including a third drain, a third gate, a third source, and a third body point, where the third drain is coupled to the output pad, and the third gate is coupled to a third reference voltage; and a second NMOS transistor, wherein the second NMOS transistor including a fourth drain, a fourth gate, a fourth source, and a fourth body point, where the fourth drain is coupled to the third source, the fourth gate is coupled to a fourth reference voltage, and the fourth source is coupled to the ground; wherein the first body point is coupled to a fifth reference voltage, the second body point is coupled to a sixth reference voltage; the fifth reference voltage and the sixth reference voltage are different from each other; and the PMOS and NMOS transistors are formed in a twin well structure.