Patent ID: 6895582

Claim:
A computing system comprising: a first general purpose microprocessor further comprising a first set of native processor instructions; a first random access memory coupled to said first general purpose microprocessor; a first virtual machine disposed in ROM, and executed by said first general purpose microprocessor, a first predetermined subset of said first set of native processor instructions, wherein instructions in said first predetermined subset are more likely to result in defects, in operation of said first general purpose processor when executed, than would a remaining subset of said first set of native processor instructions; a first implementation subset, which includes said first set of native processor instructions, except for said first predetermined subset; said first implementation subset is used by said first virtual machine; said first implementation subset does not include instructions for performing checks for potential erred execution of non-virtual machine application software; and, said first virtual machine has received a certification by the FAA, in response to a written claim of an improved assurance level, based, at least in part, upon a reduction in contents of said first implementation subset in relation to said first set of native instructions of said first microprocessor.