Patent ID: 7764620

Claim:
A processing unit for executing an interrupt test regarding a redundant channel having at least a first and a second channel for supplying electrical signals, the second channel connected to the first channel in parallel to form the redundant channel having an output signal, the processing unit comprising a driver for providing the electrical signals, wherein the processing unit is configured to: execute an interrupt test during a first and second time window while a logical “1” is present as the output signal of the redundant channel by: during the first time window, switching to or maintaining as a logical “0” a first signal on the first channel representing a zero-current state so that the output signal is only supplied by the second channel, testing the second channel for an interruption, and returning the first signal to logical “1” at an end of the first time window, and during the second time window, switching a second signal on the second channel to a logical “0” representing a zero-current state so that the output signal is only supplied by the first channel, testing the first channel for interruption, and returning the second signal to logical “1” at an end of the second time window; wherein the first time window starts at or within a first predetermined delay from a signal edge change in the output signal from logical “0” to logical “1” and wherein the second time window starts a second predetermined time delay after the first time window ends.