Patent ID: 8878597

Claim:
A circuit comprising: at least one transistor comprising: a first transistor and a second transistor, each of the first transistor and the second transistor having a base, a collector, and an emitter; at least one current source being configured to apply four different currents (A, B, C, and D) to the emitter of the at least one transistor, the at least one current source being configured to produce the four different currents with either: a sum of the current A and the current C being substantially equivalent to a sum of the current B and the current D; or a sum of the current A and the current D being substantially equivalent to a sum of the current B and the current C; and the circuit being configured to output: a first voltage potential between the emitter of the at least one transistor and the base during application of the current A to the emitter of the at least one transistor; a second voltage potential between the emitter of the at least one transistor and the base during application of the current B to the emitter of the at least one transistor; a third voltage potential between the emitter of the at least one transistor and the base during application of the current C to the emitter of the at least one transistor; a fourth voltage potential between the emitter of the at least one transistor and the base during application of the current D to the emitter of the at least one transistor; and the first transistor and the second transistor being configured to: output a first voltage differential corresponding to a difference between the first voltage when current A is applied to the emitter of the first transistor at a first time and the second voltage when current B is applied to the emitter of the second transistor at the first time; and output a second voltage differential corresponding to a difference between the third voltage when current C is applied to the emitter of the first transistor at a second time and the fourth voltage when current D is applied to the emitter of the second transistor at the second time.