Patent ID: 8423932

Claim:
A method of generating an emulated logic block, comprising: identifying a logic block in a first integrated circuit (IC) design to be emulated in a second IC design; determining a plurality of logic elements in the second IC design that are connectable to form the emulated logic block based on the logic block in the first IC design, wherein at least one of the plurality of logic elements in the second IC design is different from any logic elements from the logic block in the first IC design; connecting the plurality of logic elements in the second IC design to perform logic functions associated with the logic block in the first IC design; and grouping the plurality of connected logic elements as a block to form the emulated logic block in the second IC design, wherein the emulated logic block in the second IC design is functionally comparable to the logic block in the first IC design wherein the emulated logic block comprises a plurality of keypoints that matches respective keypoints of the logic block in the first IC design, wherein the plurality of keypoints comprises input and output terminals on the logic block and the emulated logic block and, wherein at least one method operation is executed through a processor.