Patent ID: 8108664

Claim:
A bus inversion system comprising: an advantage function circuit adapted to input bits to be transmitted over a bus, said advantage function circuit adapted to calculate an advantage of inversion and an advantage of non-inversion for each input bit and being adapted to calculate an advantage of inversion and an advantage of non-inversion for at least one inversion bit to be transmitted over the bus; said advantage function circuit having a plurality of first and second outputs, and at least one third and fourth outputs; a first circuit branch connected to receive the plurality of first outputs, each first output representing the advantage of inversion for a respective bit to be transmitted over the bus, said first branch being connected to the at least one third output representing the advantage of inversion for the at least one inversion bit, wherein said first circuit branch comprises: a first inverter corresponding to a summation of said first and third outputs, wherein said first inverter comprises an input electrically coupled to a first node, and a plurality of first transistors connected in parallel between the first node and a ground potential, each first transistor respectively having a gate terminal connected to one of the first or third outputs, said plurality of first transistors changing a potential at the first node based on the first and third outputs; and a circuit branch connected to receive the plurality of second outputs, each second output representing the advantage of non-inversion for a respective bit to be transmitted over the bus, said circuit branch being connected to the at least one fourth output representing the advantage of non-inversion for the at least one inversion bit, said circuit branch having a branch output corresponding to a summation of said second and fourth outputs.