Patent ID: 8420420

Claim:
A method of manufacturing a thin film transistor array substrate, comprising steps of: providing a substrate and sequentially stacking a first metal layer, a dielectric layer, a semiconductor layer, and a second metal layer on the substrate; forming a first patterned photoresist on the second metal layer; patterning the first metal layer, the dielectric layer, the semiconductor layer, and the second metal layer by using the first patterned photoresist to partially expose a surface of the dielectric layer, to form a source electrode and a drain electrode by the second metal layer, and to define a channel between the source electrode and the drain electrode; forming a protective layer to cover the source electrode, the drain electrode, the channel, and the partially-exposed surface of the dielectric layer; forming a second patterned photoresist on the protective layer; patterning the first metal layer, the dielectric layer, the semiconductor layer, the second metal layer, and the protective layer by using the second patterned photoresist to expose surfaces of the source electrode and the drain electrode, and a surface of the protective layer corresponding to the lower partially-exposed dielectric layer; forming a transparent conductive layer to cover the surfaces of the source electrode and the drain electrode, the surface of the protective layer corresponding to the lower partially-exposed dielectric layer, and the remaining second patterned photoresist; and removing the remaining second patterned photoresist and the transparent conductive layer covering the remaining second patterned photoresist altogether.