Patent ID: 8897316

Claim:
A method performed in a packet processing core for avoiding memory bandwidth utilization during packet processing, wherein the packet processing core is coupled between an ingress port and an egress port, the method comprising the steps of: receiving a plurality of packets from the ingress port; for each of the received plurality of packets: storing that packet in an on-chip packet store, and identifying a plurality of quality of service (QoS) characteristics of that packet, wherein the QoS characteristics comprise an isolation group (IG) and a class of service (CoS) within that IG to which that packet belongs; for a first set of one or more of the received plurality of packets: determining that at least one packet should be moved to an off-chip packet store prior to the packet being transmitted to the egress port based, at least in part, on that packet's QoS characteristics, wherein the step of determining that at least one packet should be moved to an off-chip packet store includes, determining that the on-chip packet store does not have available resources designated for the identified CoS in the IG, and determining that the off-chip packet store does have available resources to store packets that share one of that packet's plurality of QoS characteristics, and moving that packet to the off-chip packet store; for a second set of one or more of the received plurality of packets, determining that at least one packet should not be moved to an off-chip packet store prior to the packet being transmitted to the egress port based, at least in part, on that packet's corresponding QoS characteristics; whereby memory bandwidth utilization on a data bus between the on-chip packet store and the off-chip packet store is conserved because packets determined not to be moved to the off-chip packet store are not sent over the data bus.