Patent ID: 7265411

Claim:
A semiconductor device comprising: a gate dielectric layer formed on a semiconductor substrate; a floating gate overlying the gate dielectric layer, the floating gate having a first side surface and a second side surface opposite the first side surface; an insulated program gate having a side portion located at least along the first side surface, the program gate overlying the gate dielectric layer; an erase gate disposed adjacent the floating gate, the erase gate located at least along the second side surface, the erase gate overlying the gate dielectric layer; a coupling dielectric disposed between the floating gate and the program gate; a tunneling dielectric layer disposed between the floating gate and the erase gate; a first impurity region and a second impurity region formed in the semiconductor substrate along opposite sides of the floating gate; and a channel region within the semiconductor substrate between the first and second impurity regions, wherein the first and second side surfaces of the floating gate are directly over the channel region.