Patent ID: 8299602

Claim:
A semiconductor package comprising: a generally planar die pad defining multiple peripheral edge segments; a plurality of leads, at least some of which include at least one downset formed therein, the leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad; a conductive tape layer attached to at least some of the leads; a semiconductor die attached to the die pad and electrically connected to at least one of the leads, and to the tape layer; a package body defining a generally planar bottom surface and a side surface, the package body at least partially encapsulating the leads, the tape layer, and the semiconductor die such that the downsets of the leads and the tap layer are covered by the package body, and at least portions of the die pad and at least some of the leads are exposed in and substantially flush with the bottom surface of the package body.