Patent ID: 7298184

Claim:
A frequency divider circuit with adjustable frequency division ratio comprising: a push-pull divider with a frequency division ratio which can be adjusted at a control input, and configured to receive a first push-pull signal at a first frequency and output a second push-pull divider signal at a second frequency derived from the frequency division ratio at an output thereof; a first converter device connected to the output of the push-pull divider and configured to convert the second push-pull divider signal to a single-ended divider signal; a first single-ended divider with an adjustable frequency division ratio, and configured to output at an output thereof a third clock signal at a third frequency, where the third frequency is derived from the second frequency of the single-ended divider signal from the first converter device and the frequency division ratio; a second single-ended divider with an adjustable frequency division ratio, and connected to the output of the first single-ended divider, and configured to output a fourth clock signal at a fourth frequency, where the fourth frequency is derived from the third frequency of the third clock signal and the frequency division ratio; and a feedback path connected to the output of the push-pull divider and to the outputs of the first and second single-ended dividers, the feedback path comprising an evaluation circuit with a first input and a second input, the first input connected to the first single-ended divider and configured to receive future state of the third clock signal signal and the second input connected to the second single-ended divider and configured to receive a future state of the fourth clock signal, and wherein the evaluation circuit is configured to output a push-pull signal upon the occurrence of a predefined state of the third and fourth clock signals of the first and second single-ended dividers, wherein the push-pull signal is operable to release the control input of the push-pull divider.