Patent ID: 7334123

Claim:
A bus bridge for bridging transactions between a secure execution mode-capable processor and a security services processor, said bus bridge comprising: a transaction source detector configured to receive a security initialization transaction performed as a result of execution of a security initialization instruction and configured to determine whether said secure execution mode-capable processor is a source of said security initialization transaction; a configuration header configured to provide storage of information associated with said security services processor; and control logic coupled to said configuration header and configured to determine whether said security services processor is coupled to a non-enumerable, peripheral bus; wherein said secure execution mode-capable processor is configured to initialize the secure execution mode by executing the security initialization instruction and to operate in said secure execution mode by executing a secure operating system code segment, wherein said security initialization transaction includes at least a portion of said secure operating system code segment; and wherein said security services processor is separate from said secure execution mode-capable processor and configured to verify whether said at least a portion of said secure operating system code segment is valid during said initialization of said secure execution mode-capable processor into said secure execution mode.