Patent ID: 7782582

Claim:
An electrostatic discharge (ESD) protection circuit, comprising: an NPN transistor having a collector terminal connected to a voltage source, the NPN transistor having an emitter terminal connected to the ground via a diode, the NPN transistor having a base terminal for receiving a base current to turn on the NPN transistor to allow an electrostatic discharge at the voltage source to flow through the NPN transistor to the ground; a PMOS transistor having a source terminal coupled to the voltage source, the PMOS terminal having a drain terminal coupled to the base terminal of the NPN transistor, the PMOS transistor having a gate terminal for receiving a first and a second gate voltage; an R-C circuit coupled between the source voltage and the ground, the R-C circuit having first and second capacitors and a first resistor, the R-C circuit having a first interconnection point between the first resistor and the first capacitor to which is connected the gate terminal of the PMOS transistor and a second interconnection point between the first and second capacitors, the R-C circuit being operable to supply the first gate voltage to the PMOS transistor when there is no electrostatic discharge to turn off the PMOS transistor, the R-C circuit being operable to supply the second gate voltage to the PMOS transistor responsive to the electrostatic discharge to turn on the PMOS transistor for a predetermined time period, the second gate voltage being lower than the first gate voltage, the PMOS circuit being operable to supply the base voltage to the NPN transistor responsive to the second gate voltage; and a voltage divider circuit coupled between the voltage source and the ground, the voltage divider having second and third resistors forming a third interconnection point to which is connected the second interconnection point.