Patent ID: 7434184

Claim:
A method for verifying a digital circuit design comprising the steps of: picking a feature being verified in said digital circuit design; identifying, among primary inputs' values of said digital circuit design and memory elements' initial values of said digital circuit design, values supposedly irrelevant to said feature being verified; creating a first instance of said digital circuit design and a second instance of said digital circuit design; turning said values supposedly irrelevant to said feature being verified into wild cards in said second instance; collecting stimulus values for primary inputs' values of said digital circuit design and memory elements' initial values of said digital circuit design except said values supposedly irrelevant to said feature being verified; connecting said stimulus values to primary inputs' values of said digital circuit design and memory elements' initial values of said digital circuit design in said first instance in the same way as in said second instance except said values supposedly irrelevant to said feature being verified; determining values to observe in said digital circuit design for deciding the functional correctness of said feature being verified; and adding comparison logic to detect the predetermined consistency of said values to observe between said first instance and said second instance.