Patent ID: 7924962

Claim:
A clock regeneration circuit for a demodulator used in a digital radio communications apparatus employing an orthogonal modulation scheme, comprising: two analog/digital converters for sampling orthogonally demodulated signals of a first and a second channels orthogonally detected by an orthogonal detector, respectively, using a sampling clock signal applied thereto for conversion into digital values, and delivering the digital values; an orthogonal interfering component reducing module for reducing only an orthogonal interfering component from interfering components introduced by inter-symbol interference for signals from said two analog/digital converters; a clock phase detector for detecting the phase of a signal delivered from said orthogonal component reducing module to deliver a signal indicative of a direction of a shift of a sampling position in said two analog/digital converters; a loop filter for removing high frequency components from the signal delivered from said clock phase detector to deliver as a frequency control signal; and a voltage controlled oscillator for supplying said two analog/digital converters with a clock signal, the frequency of which is controlled by the frequency control signal from said loop filter, as the sampling clock signal, wherein said orthogonal interference component reducing module comprises an orthogonal component equalizer comprising: a first transversal filter for compensating a signal on a first channel applied from said analog/digital converter for interference caused by an orthogonal component; a first delay adjustment circuit for giving a delay amount equivalent to a delay amount at a center tap of said first transversal filter to the signal on the first channel applied from said analog/digital converter; a first adder for adding an output of said first delay adjustment circuit and an output from said first transversal filter to deliver to said clock phase detector as the signal on the first channel; a second transversal filter for compensating a signal on a second channel applied from said analog/digital converter for interference caused by an orthogonal component; a second delay adjustment circuit for giving a delay amount equivalent to a delay amount at a center tap of said second transversal filter to the signal on the second channel applied from said analog/digital converter; and a second adder for adding an output from said second delay adjustment circuit and an output from said second transversal filter to deliver to said clock phase detector as the signal on the second channel.