Patent ID: 7721127

Claim:
A multithreaded microprocessor, comprising: a plurality of thread contexts, each configured to store application-specified quality-of-service (QoS) information for a corresponding plurality of threads concurrently executed by the microprocessor; an indicator, for indicating instruction completion information specifying for which of said plurality of thread contexts the microprocessor completed an instruction; a thread scheduler, coupled to said plurality of thread contexts and said indicator, configured to schedule instructions of said plurality of thread contexts to issue to execution units of the microprocessor based on said QoS information and said instruction completion information; and a voltage-frequency scheduler, coupled to said plurality of thread contexts and said indicator, configured to determine an aggregate utilization of the microprocessor by said plurality of threads based on said QoS information and said instruction completion information during a first period while the microprocessor is operating at a first frequency and voltage, and to cause the microprocessor to operate at a second frequency and voltage during a second period based on said aggregate utilization, wherein said second frequency and voltage are different from said first frequency and voltage, wherein said QoS information comprises a number of instructions to complete over a number of clock cycles to accomplish a required quality-of-service for said corresponding thread.