Patent ID: 8233326

Claim:
A semiconductor non-volatile memory comprising: a plurality of memory sections, each memory section comprising: a substrate, equipped with a source region, a drain region, a channel region between the source region and the drain region, a first variable resistance region between the channel region and the source region, the first variable resistance region having a specific concentration of an impurity and having a variable resistance, and a second variable resistance region between the channel region and the drain region, the second variable resistance region having a specific concentration of an impurity and having a variable resistance; a source electrode, disposed in a position on the substrate corresponding to the source region; a drain electrode, disposed in a position on the substrate corresponding to the drain region; a gate electrode, disposed in a position on the substrate corresponding to the channel region; a current detection section that detects a value of current flowing in the channel region; at least one first charge accumulating section, disposed in a position on the substrate corresponding to the first variable resistance region, and accumulating charge of an amount corresponding to an application state of voltage applied to the source electrode and the gate electrode; and at least one second charge accumulating section, disposed in a position on the substrate corresponding to the second variable resistance region, and accumulating charge of an amount corresponding to the application state of voltage applied to the drain electrode and the gate electrode; a voltage application section that selectively applies a voltage to the source electrode, the drain electrode, and the gate electrode; and a control section that controls the voltage application section, such that voltage is applied a plurality of times between the gate electrode and at least one of the source electrode or the drain electrode, until the amount of charge accumulated in at least one of the respective first charge accumulating section or the respective second charge accumulating section of the plurality of memories is a specific value, and changes the voltage application state such that as the number of times that the voltage is applied increases, a charge accumulating amount per time increases, wherein the control section controlling voltage application such that, based on a value of current detected by the current detection section, in a region where the current flowing in the channel region is greater than a predetermined target value at which the amount of charge accumulated has become a specific value in at least one of the first charge accumulating section or the second charge accumulating section, when a value of current flowing in the channel region approaches the target value, a rate of increase in the charge accumulating amount per time is decreased at least once.