Patent ID: 7324520

Claim:
A processor, comprising: a micro-engine to execute a plurality of threads, each to add a segment of a data set received by the processor to a first queue of a first plurality of queues stored in a local memory of the micro-engine, wherein the local memory of the micro-engine is not available to other micro-engines in the processor; and a static random access memory (SRAM) to store a second plurality of queues, wherein the first plurality of queues is a subset of the second plurality of queues, wherein a queue number representing one of the second plurality of queues is associated with the data set, wherein the first queue is selected from the first plurality of queues based on the queue number associated with the data set, wherein, if the queue number does not match one of the first plurality of queues, the processor writes a least recently used queue to SRAM, reads a second queue of the second plurality of queues associated with the queue number from SRAM, and adds the segment of the data set to the second queue.