Patent ID: 7208764

Claim:
An array substrate, comprising: a gate electrode; a semiconductor film; a gate insulating layer formed between the gate electrode and the semiconductor film; a first conductive film formed over the semiconductor film; a second conductive film formed over the semiconductor film; a partition wall formed over the gate insulating layer, wherein the partition wall forms at least a first loop, a second loop and a third loop, and at least a portion of the partition wall contacts the semiconductor film; and a pixel electrode having a first portion and a second portion, the first portion being surrounded by the first loop of the partition wall, the first portion not overlapping vertically with the partition wall, the first portion contacting the partition wall, the second portion not being surrounded by the first loop of the partition wall, the second portion overlapping vertically with the partition wall, contacting the partition wall, and contacting the first conductive film, wherein at least a portion of the first conductive film forms at least a portion of a drain electrode, at least a portion of the second conductive film forms at least a portion of a source electrode; and the portion of the source electrode and the portion of the drain electrode are respectively surrounded by the second loop and the third loop.