Patent ID: 8196215

Claim:
A circuit for securing against non-reset of a device associated with the circuit, the circuit comprising: a first register for holding a first multi-bit value and to produce a first multi-bit output value related to the first multi-bit value; a second register for holding a second multi-bit value and to produce a second multi-bit output value related to the second multi-bit value; an inverter coupled to receive as an input only one of the first and second multi-bit output values and invert the input to output an inverted multi-bit output value wherein each bit is the inverse of the input; and a comparator arranged to compare the inverted and non-inverted multi-bit output values to produce a comparator output indicating a match or mismatch between the inverted and non-inverted output values, wherein the first and second registers are arranged such that they are subject to substantially the same operational conditions.