Patent ID: 8199579

Claim:
A nonvolatile semiconductor memory device, comprising: a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series; word lines connected to control gate electrodes of the nonvolatile memory cells; bit lines connected to first ends of the NAND cell units; a source line connected to second ends of the NAND cell units; and a control circuit configured to simultaneously erase data stored in the nonvolatile memory cells arranged in a certain area, and then control a soft program operation of setting the nonvolatile memory cells in the certain area to a first threshold voltage distribution state of the nonvolatile memory cells, the control circuit being configured to: when a characteristic of the nonvolatile memory cells is determined as being in a first state, execute the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines as the word lines except a second word line connected to the nonvolatile memory cells at the end of the NAND cell unit, and applying a second voltage higher than the first voltage by a certain voltage value to the second word line; and when the characteristic of the nonvolatile memory cells is determined as being in a second state, execute the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage by a certain voltage value to the second word line.