Patent ID: 7518916

Claim:
A method for programming a first and second tri-gate structure in a non-volatile SRAM cell having a volatile portion and a non-volatile portion, each tri-gate structure in said non-volatile portion having a recall transistor, a store transistor and a SONOS transistor, said volatile portion having an SRAM cell comprising a word line, a node supplying power to said SRAM cell and a bit line pair with a first bit line and a second bit line, said method comprising: erasing said first and second SONOS transistors associated with said non-volatile portion of said SRAM cell; grounding said first bit line and said second bit line; grounding said node supplying power to said SRAM cell; applying a voltage to said word line sufficient to turn the word line to an active state so as to discharge said internal data nodes of said SRAM cell to ground; applying a voltage to each store transistor in said first and second tri-gate structure sufficient to turn each store transistor on; and applying a programming pulse and programming voltage to each SONOS transistor in said first and second tri-gate structure to program said tri-gate structure in said non-volatile portion.