Patent ID: 7082053

Claim:
A memory storage circuit, comprising: a plurality of magnetic elements each configured to store bits in a first logic state or a second logic state; a plurality of transistors coupled to at least two of the magnetic elements, wherein the plurality of transistors are collectively configured to store bits in the first and second logic states; a first set of circuitry configured to load bits from a set of the magnetic elements into the plurality of transistors, wherein the first set of circuitry comprises a first set of conductive structures configured to pass current through the set of magnetic elements; and a second set of circuitry configured to program the set of magnetic elements, wherein the second set of circuitry comprises; a second set of conductive structures configured to induce respective magnetic fields about each of the set of magnetic elements; and a program transistor coupled between the set of magnetic elements and configured to enable current flow among the second set of conductive structures.