Patent ID: 8762600

Claim:
A digital data stream delay buffer comprising: a fast processing, small capacity (FPSC) memory section operable to receive one or more delayed data portions of an original data stream; a slow processing, large capacity (SPLC) memory section operable to receive one or more delayed data portions of the original data stream; and a control section connected to each of the memory sections and operable to, detect a delay associated with each of the received delayed data portions, control the FPSC memory section to output an aligned data stream, having substantially the same alignment as an alignment associated with the original data stream, formed from the one or more delayed data portions without using data stored in the SPLC memory section, on the condition that none of the detected delays exceeds a time period equivalent to a time period at which a memory capacity of the FPSC memory section reaches a maximum, and control the FPSC memory section to output the aligned data stream using a selected, variable amount of data stored in the SPLC memory section on the condition that one or more of the detected delays exceeds the time period, wherein the FPSC memory section contains a first data portion of the original data stream and the SPLC memory section contains a second data portion of the original data stream, and the first data portion is identical to the second data portion.