Patent ID: 7353159

Claim:
A method for simulating a hardware logic circuit using a hardware model and a simulation environment test bench in which stimuli of the simulation are built-up and simulation result data is managed, the method comprising the steps of: using a meta model compiled for integrating a plurality of n different instantiations of copies of the same hardware model for simulating multiple instances of the complete design with multiple instances of the test bench, which instantiations are identical but differ in a plurality of input variables, resolving facilities and signals of different instantiations by instantiation-specific name space specifications, running within one single simulation run on a single microprocessor system, said plurality of n different instantiations of the same hardware model, associating each of a plurality of n input channels from environment codes with a respective one of model instantiations for stimuli input purposes with a dedicated code switch, and associating each of a plurality of n output channels from said model instantiations with an invocation of a respective one of said environment codes with a respective code switch.