Patent ID: 6977404

Claim:
A semiconductor memory device comprising: a projecting semiconductor layer formed on a major surface of a semiconductor substrate; a channel region of a first conductivity type formed in part of the projecting semiconductor layer; source and drain regions of a second conductivity type formed in the projecting semiconductor layer such that the source and drain regions sandwich the channel region; a pair of first insulating films formed on a surface of the channel region on opposed side walls of the semiconductor layer; a pair of gate electrodes formed on a surface of the pair of first insulating films on the opposed side walls of the semiconductor layer; a first trench capacitor provided near the source region in the semiconductor layer, the first trench capacitor having one electrode electrically connected to the source region; and a second insulating film having a greater thickness than the first insulating films, and provided between surfaces of the pair of gate electrodes, which are opposed to the surfaces on which the first insulating films are formed, and a second trench capacitor formed adjacent to the first trench capacitor.