Patent ID: 8775745

Claim:
An apparatus for collision detection in a multibank memory, comprising: a memory bank address comparator for receiving bank address data corresponding to a first memory command and a second memory command, wherein the memory bank address comparator is operable to output a bank match signal indicative of the first memory command and the second memory command being directed to a common memory bank address; a memory index address comparator for receiving index address data corresponding to the first memory command and the second memory command, wherein the memory index address comparator is operable to output an index match signal indicative of the first memory command and the second memory command being directed to a common memory index address; and a collision detection circuit comprising a timing correction module that is operable to receive the bank match signal and the index match signal and generate at least one of a corrected bank match signal or a corrected index match signal in response to a change detected in one of the index match signal or bank match signal attributable to process variation; wherein the collision detection circuit is operable to compare the at least one of the corrected bank match signal or the corrected index match signal to generate a collision detection signal indicative of a collision in the multibank memory resulting from execution of the first memory command and the second memory command.