Patent ID: 7859024

Claim:
An integrated circuit comprising: a substrate having a semiconducting surface; a plurality of standard cells arranged in a plurality of rows comprising at least a first row and a second row immediately above said first row; said first row comprising at least a first of said standard cells, said first standard cell comprising a first decap filler cell comprising a first active area and a field dielectric outside said first active area having a portion with a full field dielectric thickness portion and a portion with a thinned field dielectric, and at least a first MOS transistors having a gate electrode on a thick gate dielectric on said first active area connected as a decoupling capacitor, and said second row comprising at least a second of said standard cells, said second standard cell comprising a second decap filler cell comprising a second active area and a field dielectric having a portion having said full field dielectric thickness and a portion having said thinned field dielectric portion, at least a second MOS transistors having a gate electrode on said thick gate dielectric on said second active area connected as a decoupling capacitor; wherein said thinned field dielectric extends from said first decap filler cell to said second decap filler cell across a border between said first and second decap filler cell.