Patent ID: 7290120

Claim:
Microprocessor having: (a) a program instruction memory which receives a sequential program instruction address addressing the next program instruction memory line which is to be read, having at least one program instruction memory line which can store an indicator flag, a long program instruction index, a short program instruction and a first source register address, (b) a directory memory for long program instructions which receives the long program instruction index addressing the next directory memory line which is to be read, having at least one directory memory line which can store a long program instruction and a second source register address, (c) a short program instruction decoding unit for decoding the short program instruction which has been read from the program instruction memory and for providing a first program instruction counter, (d) a long program instruction decoding unit for decoding the long program instruction which has been read from the directory memory and for providing a second program instruction counter, and having (e) a program instruction sequencer which generates the sequential program instruction address on the basis of the first program instruction counter and the second program instruction counter.